ser.c (222765B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * File: ser.c 7 * Purpose: SER enable/detect and test functionality. 8 * Requires: 9 */ 10 #include <shared/bsl.h> 11 #include <soc/drv.h> 12 #include <soc/error.h> 13 #include <soc/debug.h> 14 #include <soc/mem.h> 15 #include <soc/greyhound2.h> 16 17 /* Internal Use Only : Individually Test Purpose */ 18 #define _GH2_SER_TEST_MMU (1) 19 #define _GH2_SER_TEST_TCAM (1) 20 #define _GH2_SER_TEST_EP (1) 21 #define _GH2_SER_TEST_IP0 (1) 22 #define _GH2_SER_TEST_IP1 (1) 23 #define _GH2_SER_TEST_IP2 (1) 24 #define _GH2_SER_TEST_IP2_SR (1) 25 #define _GH2_SER_TEST_IP2_SR_SN (1) 26 #define _GH2_SER_TEST_CLPORT (1) 27 #define _GH2_SER_TEST_XLPORT (1) 28 #define _GH2_SER_TEST_GPORT (1) 29 30 31 /* 32 * Chip specific SER information. 33 */ 34 35 /* GH2 SKUs */ 36 #define _SOC_SER_SKIP_GH2_HR3MG (0x1 << 0) 37 #define _SOC_SER_SKIP_GH2_QUARTZ (0x1 << 1) /* no L3 */ 38 /* GH2 chip revisions */ 39 #define _SOC_SER_SKIP_GH2_A0 (0x1 << 2) 40 #define _SOC_SER_SKIP_GH2_B0 (0x1 << 3) 41 42 typedef enum { 43 _SOC_PARITY_TYPE_NONE, 44 _SOC_PARITY_TYPE_ECC, 45 _SOC_PARITY_TYPE_ECC_DUAL, 46 _SOC_PARITY_TYPE_PARITY, 47 _SOC_PARITY_TYPE_PARITY_DUAL, 48 _SOC_PARITY_TYPE_COUNTER, 49 _SOC_PARITY_TYPE_PORT_XL, 50 _SOC_PARITY_TYPE_MMU_SER, 51 _SOC_PARITY_TYPE_MMU_ECC, 52 _SOC_PARITY_TYPE_MMU_ECC_CBPH,/* 2-level ecc */ 53 _SOC_PARITY_TYPE_MMU_ECC_XQ, /* 2-level ecc */ 54 _SOC_PARITY_TYPE_MMU_PAR_E2EFC, /* par */ 55 _SOC_PARITY_TYPE_MMU_PAR_WRED, /* 2-level par */ 56 _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, /* 2-level ecc_correctable */ 57 _SOC_PARITY_TYPE_MMU_ECC_IPMCVLAN, /* ecc_correctable */ 58 _SOC_PARITY_TYPE_SER 59 } _soc_gh2_ser_info_type_t; 60 61 typedef struct _soc_gh2_ser_reg_s { 62 soc_reg_t reg; 63 char *str; 64 soc_mem_t mem; 65 } _soc_gh2_ser_reg_t; 66 67 typedef struct _soc_gh2_ser_info_s { 68 _soc_gh2_ser_info_type_t type; 69 struct _soc_gh2_ser_info_s *info; /* used for MMU */ 70 /* registers sets for parity/ecc group related */ 71 soc_field_t group_reg_enable_field; 72 soc_field_t group_reg_status_field; 73 soc_mem_t mem; 74 char *mem_str; 75 /* registers sets for parity/ecc enable */ 76 soc_reg_t enable_reg; 77 soc_field_t enable_field; 78 soc_field_t *enable_field_list; 79 /* registers sets for parity/ecc interrupt related */ 80 soc_reg_t intr_enable_reg; 81 soc_field_t intr_enable_field; 82 soc_field_t *intr_enable_field_list; 83 soc_reg_t intr_status_reg; 84 _soc_gh2_ser_reg_t *intr_status_reg_list; 85 soc_field_t intr_status_field; 86 soc_reg_t intr_clr_reg; 87 soc_field_t intr_clr_field; 88 soc_reg_t intr2_valid_reg; 89 _soc_gh2_ser_reg_t *intr2_valid_reg_list; 90 soc_reg_t intr2_multi_err_reg; 91 soc_reg_t intr2_clr_reg; 92 uint32 sku_skip; 93 }_soc_gh2_ser_info_t; 94 95 #if _GH2_SER_TEST_IP0 96 static _soc_gh2_ser_reg_t vlan_xlate_regs[] = { 97 { VLAN_XLATE_PARITY_STATUS_0r, "", INVALIDm}, 98 { VLAN_XLATE_PARITY_STATUS_1r, "", INVALIDm}, 99 { INVALIDr } 100 }; 101 #endif /* _GH2_SER_TEST_IP0 */ 102 103 #if _GH2_SER_TEST_IP1 104 static _soc_gh2_ser_reg_t _soc_gh2_l3_entry_regs[] = { 105 { L3_ENTRY_PARITY_STATUS_0r, "", INVALIDm}, 106 { L3_ENTRY_PARITY_STATUS_1r, "", INVALIDm}, 107 { INVALIDr } 108 }; 109 110 static _soc_gh2_ser_reg_t _soc_gh2_l2_entry_regs[] = { 111 { L2_ENTRY_PARITY_STATUS_0r, "", INVALIDm}, 112 { L2_ENTRY_PARITY_STATUS_1r, "", INVALIDm}, 113 { INVALIDr } 114 }; 115 #endif /* _GH2_SER_TEST_IP1 */ 116 117 #if _GH2_SER_TEST_EP 118 static _soc_gh2_ser_reg_t egr_vlan_xlate_regs[] = { 119 { EGR_VLAN_XLATE_PARITY_STATUS_0r, "", INVALIDm}, 120 { EGR_VLAN_XLATE_PARITY_STATUS_1r, "", INVALIDm}, 121 { INVALIDr } 122 }; 123 #endif /* _GH2_SER_TEST_EP */ 124 125 static _soc_gh2_ser_info_t _soc_gh2_ip0_ser_info[] = { 126 #if _GH2_SER_TEST_IP0 127 { _SOC_PARITY_TYPE_PARITY, NULL, 128 PORT_TABLE_1BIT_ERR_INTRf, PORT_TABLE_1BIT_ERR_INTRf, 129 PORT_TABm, "PORT_TAB PARITY", 130 PORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 131 INVALIDr, INVALIDf, NULL, 132 PORT_TABLE_PARITY_STATUS_INTRr, NULL, PARITY_ERRf, 133 INVALIDr, INVALIDf, 134 INVALIDr, NULL, INVALIDr, INVALIDr, 135 0 136 }, 137 { _SOC_PARITY_TYPE_ECC, NULL, 138 PORT_TABLE_ECC_INTRf, PORT_TABLE_ECC_INTRf, 139 INVALIDm, "PORT_TAB ECC", 140 PORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 141 INVALIDr, INVALIDf, NULL, 142 PORT_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 143 INVALIDr, INVALIDf, 144 INVALIDr, NULL, INVALIDr, INVALIDr, 145 0 146 }, 147 { _SOC_PARITY_TYPE_PARITY, NULL, 148 SYSTEM_CONFIG_PAR_ERRf, SYSTEM_CONFIG_PAR_ERRf, 149 SYSTEM_CONFIG_TABLEm, "SYSTEM_CONFIG_TABLE PARITY", 150 SYSTEM_CONFIG_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 151 INVALIDr, INVALIDf, NULL, 152 SYSTEM_CONFIG_TABLE_PARITY_STATUSr, NULL, INVALIDf, 153 INVALIDr, INVALIDf, 154 INVALIDr, NULL, INVALIDr, INVALIDr, 155 0 156 }, 157 { _SOC_PARITY_TYPE_PARITY, NULL, 158 SYSTEM_CONFIG_MODBASE_PAR_ERRf, SYSTEM_CONFIG_MODBASE_PAR_ERRf, 159 SYSTEM_CONFIG_TABLE_MODBASEm, "SYSTEM_CONFIG_TABLE_MODBASE PARITY", 160 SYSTEM_CONFIG_TABLE_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 161 INVALIDr, INVALIDf, NULL, 162 SYSTEM_CONFIG_TABLE_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 163 INVALIDr, INVALIDf, 164 INVALIDr, NULL, INVALIDr, INVALIDr, 165 0 166 }, 167 { _SOC_PARITY_TYPE_PARITY, NULL, 168 SR_PORT_TABLE_1BIT_ERR_INTRf, SR_PORT_TABLE_1BIT_ERR_INTRf, 169 SR_PORT_TABLEm, "SR_PORT_TABLE PARITY", 170 SR_PORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 171 INVALIDr, INVALIDf, NULL, 172 SR_PORT_TABLE_PARITY_STATUS_INTRr, NULL, PARITY_ERRf, 173 INVALIDr, INVALIDf, 174 INVALIDr, NULL, INVALIDr, INVALIDr, 175 0 176 }, 177 { _SOC_PARITY_TYPE_ECC, NULL, 178 SR_PORT_TABLE_ECC_INTRf, SR_PORT_TABLE_ECC_INTRf, 179 INVALIDm, "SR_PORT_TABLE ECC", 180 SR_PORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 181 INVALIDr, INVALIDf, NULL, 182 SR_PORT_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 183 INVALIDr, INVALIDf, 184 INVALIDr, NULL, INVALIDr, INVALIDr, 185 0 186 }, 187 { _SOC_PARITY_TYPE_PARITY, NULL, 188 SR_LPORT_PROFILE_TABLE_1BIT_ERR_INTRf, SR_LPORT_PROFILE_TABLE_1BIT_ERR_INTRf, 189 SR_LPORT_TABm, NULL, 190 SR_LPORT_PROFILE_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 191 INVALIDr, INVALIDf, NULL, 192 SR_LPORT_PROFILE_TABLE_PARITY_STATUSr, NULL, PARITY_ERRf, 193 INVALIDr, INVALIDf, 194 INVALIDr, NULL, INVALIDr, INVALIDr, 195 0 196 }, 197 { _SOC_PARITY_TYPE_ECC, NULL, 198 SR_LPORT_PROFILE_TABLE_ECC_INTRf, SR_LPORT_PROFILE_TABLE_ECC_INTRf, 199 INVALIDm, NULL, 200 SR_LPORT_PROFILE_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 201 INVALIDr, INVALIDf, NULL, 202 SR_LPORT_PROFILE_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 203 INVALIDr, INVALIDf, 204 INVALIDr, NULL, INVALIDr, INVALIDr, 205 0 206 }, 207 { _SOC_PARITY_TYPE_PARITY, NULL, 208 SOURCE_TRUNK_MAP_PARITY_ERRf, SOURCE_TRUNK_MAP_PARITY_ERRf, 209 SOURCE_TRUNK_MAP_TABLEm, NULL, 210 SOURCE_TRUNK_MAP_PARITY_CONTROLr, PARITY_ENf, NULL, 211 INVALIDr, INVALIDf, NULL, 212 SOURCE_TRUNK_MAP_PARITY_STATUSr, NULL, INVALIDf, 213 INVALIDr, INVALIDf, 214 INVALIDr, NULL, INVALIDr, INVALIDr, 215 0 216 }, 217 { _SOC_PARITY_TYPE_PARITY, NULL, 218 SOURCE_TRUNK_MAP_MODBASE_PARITY_ERRf, SOURCE_TRUNK_MAP_MODBASE_PARITY_ERRf, 219 SOURCE_TRUNK_MAP_MODBASEm, NULL, 220 SOURCE_TRUNK_MAP_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 221 INVALIDr, INVALIDf, NULL, 222 SOURCE_TRUNK_MAP_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 223 INVALIDr, INVALIDf, 224 INVALIDr, NULL, INVALIDr, INVALIDr, 225 0 226 }, 227 { _SOC_PARITY_TYPE_PARITY, NULL, 228 ING_MOD_MAP_PAR_ERRf, ING_MOD_MAP_PAR_ERRf, 229 ING_MOD_MAP_TABLEm, "ING_MOD_MAP", 230 ING_MOD_MAP_PARITY_CONTROLr, PARITY_ENf, NULL, 231 INVALIDr, INVALIDf, NULL, 232 ING_MOD_MAP_PARITY_STATUSr, NULL, INVALIDf, 233 INVALIDr, INVALIDf, 234 INVALIDr, NULL, INVALIDr, INVALIDr, 235 0 236 }, 237 { _SOC_PARITY_TYPE_ECC, NULL, 238 LPORT_TABLE_ECC_INTRf, LPORT_TABLE_ECC_INTRf, 239 INVALIDm, "LPORT_TABLE/LPORT_PROFILE_TABLE ECC", 240 LPORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 241 INVALIDr, INVALIDf, NULL, 242 LPORT_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 243 INVALIDr, INVALIDf, 244 INVALIDr, NULL, INVALIDr, INVALIDr, 245 0 246 }, 247 { _SOC_PARITY_TYPE_PARITY, NULL, 248 LPORT_TABLE_1BIT_ERR_INTRf, LPORT_TABLE_1BIT_ERR_INTRf, 249 LPORT_TABm, "LPORT_TABLE/LPORT_PROFILE_TABLE PARITY", 250 LPORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 251 INVALIDr, INVALIDf, NULL, 252 LPORT_TABLE_PARITY_STATUSr, NULL, INVALIDf, 253 INVALIDr, INVALIDf, 254 INVALIDr, NULL, INVALIDr, INVALIDr, 255 0 256 }, 257 { _SOC_PARITY_TYPE_PARITY, NULL, 258 UDF_OFFSET_PAR_ERRf, UDF_OFFSET_PAR_ERRf, 259 FP_UDF_OFFSETm, NULL, 260 UDF_OFFSET_PARITY_CONTROLr, PARITY_ENf, NULL, 261 INVALIDr, INVALIDf, NULL, 262 UDF_OFFSET_PARITY_STATUSr, NULL, INVALIDf, 263 INVALIDr, INVALIDf, 264 INVALIDr, NULL, INVALIDr, INVALIDr, 265 0 266 }, 267 { _SOC_PARITY_TYPE_PARITY, NULL, 268 ING_ETAG_PCP_MAPPING_PAR_ERRf, ING_ETAG_PCP_MAPPING_PAR_ERRf, 269 ING_ETAG_PCP_MAPPINGm, NULL, 270 ING_ETAG_PCP_MAPPING_PARITY_CONTROLr, PARITY_ENf, NULL, 271 INVALIDr, INVALIDf, NULL, 272 ING_ETAG_PCP_MAPPING_PARITY_STATUSr, NULL, INVALIDf, 273 INVALIDr, INVALIDf, 274 INVALIDr, NULL, INVALIDr, INVALIDr, 275 0 276 }, 277 { _SOC_PARITY_TYPE_PARITY, NULL, 278 MY_STATION_TCAM_DATA_PAR_INTRf, MY_STATION_TCAM_DATA_PAR_INTRf, 279 MY_STATION_TCAMm, NULL, 280 MY_STATION_TCAM_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 281 INVALIDr, INVALIDf, NULL, 282 MY_STATION_TCAM_DATA_PARITY_STATUSr, NULL, INVALIDf, 283 INVALIDr, INVALIDf, 284 INVALIDr, NULL, INVALIDr, INVALIDr, 285 0 286 }, 287 { _SOC_PARITY_TYPE_PARITY, NULL, 288 MY_STATION_TCAM_DATA_PAR_INTRf, MY_STATION_TCAM_DATA_PAR_INTRf, 289 MY_STATION_TCAM_DATA_ONLYm, NULL, 290 MY_STATION_TCAM_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 291 INVALIDr, INVALIDf, NULL, 292 MY_STATION_TCAM_DATA_PARITY_STATUSr, NULL, INVALIDf, 293 INVALIDr, INVALIDf, 294 INVALIDr, NULL, INVALIDr, INVALIDr, 295 0 296 }, 297 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 298 VXLT_PAR_ERRf, VXLT_PAR_ERRf, 299 VLAN_XLATEm, NULL, 300 VLAN_XLATE_PARITY_CONTROLr, PARITY_ENf, NULL, 301 INVALIDr, INVALIDf, NULL, 302 INVALIDr, vlan_xlate_regs, INVALIDf, 303 INVALIDr, INVALIDf, 304 INVALIDr, NULL, INVALIDr, INVALIDr, 305 0 306 }, 307 { _SOC_PARITY_TYPE_PARITY, NULL, 308 VLAN_PROTOCOL_DATA_PARITY_ERRf, VLAN_PROTOCOL_DATA_PARITY_ERRf, 309 VLAN_PROTOCOL_DATAm, NULL, 310 VLAN_PROTOCOL_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 311 INVALIDr, INVALIDf, NULL, 312 VLAN_PROTOCOL_DATA_PARITY_STATUSr, NULL, INVALIDf, 313 INVALIDr, INVALIDf, 314 INVALIDr, NULL, INVALIDr, INVALIDr, 315 0 316 }, 317 { _SOC_PARITY_TYPE_PARITY, NULL, 318 VLAN_SUBNET_DATA_PARITY_ERRf, VLAN_SUBNET_DATA_PARITY_ERRf, 319 VLAN_SUBNETm, NULL, 320 VLAN_SUBNET_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 321 INVALIDr, INVALIDf, NULL, 322 VLAN_SUBNET_DATA_PARITY_STATUSr, NULL, INVALIDf, 323 INVALIDr, INVALIDf, 324 INVALIDr, NULL, INVALIDr, INVALIDr, 325 0 326 }, 327 { _SOC_PARITY_TYPE_PARITY, NULL, 328 VLAN_SUBNET_DATA_PARITY_ERRf, VLAN_SUBNET_DATA_PARITY_ERRf, 329 VLAN_SUBNET_DATA_ONLYm, NULL, 330 VLAN_SUBNET_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 331 INVALIDr, INVALIDf, NULL, 332 VLAN_SUBNET_DATA_PARITY_STATUSr, NULL, INVALIDf, 333 INVALIDr, INVALIDf, 334 INVALIDr, NULL, INVALIDr, INVALIDr, 335 0 336 }, 337 { _SOC_PARITY_TYPE_PARITY, NULL, 338 VFP_POLICY_PAR_ERRf, VFP_POLICY_PAR_ERRf, 339 VFP_POLICY_TABLEm, NULL, 340 VFP_POLICY_PARITY_CONTROLr, PARITY_ENf, NULL, 341 INVALIDr, INVALIDf, NULL, 342 VFP_POLICY_PARITY_STATUS_INTRr, NULL, INVALIDf, 343 INVALIDr, INVALIDf, 344 INVALIDr, NULL, INVALIDr, INVALIDr, 345 0 346 }, 347 { _SOC_PARITY_TYPE_PARITY, NULL, 348 LMEP_PAR_ERRf, LMEP_PAR_ERRf, 349 LMEPm, NULL, 350 LMEP_PARITY_CONTROLr, PARITY_ENf, NULL, 351 INVALIDr, INVALIDf, NULL, 352 LMEP_PARITY_STATUSr, NULL, INVALIDf, 353 INVALIDr, INVALIDf, 354 INVALIDr, NULL, INVALIDr, INVALIDr, 355 0 356 }, 357 { _SOC_PARITY_TYPE_PARITY, NULL, 358 LMEP_DA_PAR_ERRf, LMEP_DA_PAR_ERRf, 359 LMEP_DAm, NULL, 360 LMEP_DA_PARITY_CONTROLr, PARITY_ENf, NULL, 361 INVALIDr, INVALIDf, NULL, 362 LMEP_DA_PARITY_STATUSr, NULL, INVALIDf, 363 INVALIDr, INVALIDf, 364 INVALIDr, NULL, INVALIDr, INVALIDr, 365 0 366 }, 367 { _SOC_PARITY_TYPE_PARITY, NULL, 368 VLAN_PARITY_ERRf, VLAN_PARITY_ERRf, 369 VLAN_TABm, NULL, 370 VLAN_PARITY_CONTROLr, PARITY_ENf, NULL, 371 INVALIDr, INVALIDf, NULL, 372 VLAN_PARITY_STATUSr, NULL, INVALIDf, 373 INVALIDr, INVALIDf, 374 INVALIDr, NULL, INVALIDr, INVALIDr, 375 0 376 }, 377 { _SOC_PARITY_TYPE_PARITY, NULL, 378 L3_IIF_PAR_ERRf, L3_IIF_PAR_ERRf, 379 L3_IIFm, NULL, 380 L3_IIF_PARITY_CONTROLr, PARITY_ENf, NULL, 381 INVALIDr, INVALIDf, NULL, 382 L3_IIF_PARITY_STATUSr, NULL, INVALIDf, 383 INVALIDr, INVALIDf, 384 INVALIDr, NULL, INVALIDr, INVALIDr, 385 0 386 }, 387 { _SOC_PARITY_TYPE_PARITY, NULL, 388 VLAN_STG_PARITY_ERRf, VLAN_STG_PARITY_ERRf, 389 STG_TABm, NULL, 390 VLAN_STG_PARITY_CONTROLr, PARITY_ENf, NULL, 391 INVALIDr, INVALIDf, NULL, 392 VLAN_STG_PARITY_STATUSr, NULL, INVALIDf, 393 INVALIDr, INVALIDf, 394 INVALIDr, NULL, INVALIDr, INVALIDr, 395 0 396 }, 397 { _SOC_PARITY_TYPE_ECC, NULL, 398 IARB_PKT_ECC_INTRf, IARB_PKT_ECC_INTRf, 399 INVALIDm, "IARB_PKT ECC", 400 IARB_PKT_ECC_CONTROLr, ECC_ENf, NULL, 401 INVALIDr, INVALIDf, NULL, 402 IARB_PKT_ECC_STATUS_INTRr, NULL, INVALIDf, 403 INVALIDr, INVALIDf, 404 INVALIDr, NULL, INVALIDr, INVALIDr, 405 0 406 }, 407 { _SOC_PARITY_TYPE_PARITY, NULL, 408 IARB_PKT_1BIT_ERR_INTRf, IARB_PKT_1BIT_ERR_INTRf, 409 INVALIDm, "IARB_PKT PARITY", 410 IARB_PKT_ECC_CONTROLr, ECC_ENf, NULL, 411 INVALIDr, INVALIDf, NULL, 412 IARB_PKT_PARITY_STATUS_INTRr, NULL, INVALIDf, 413 INVALIDr, INVALIDf, 414 INVALIDr, NULL, INVALIDr, INVALIDr, 415 0 416 }, 417 { _SOC_PARITY_TYPE_PARITY, NULL, 418 VFI_PAR_INTRf, VFI_PAR_INTRf, 419 VFIm, "VFI PARITY", 420 VFI_PARITY_CONTROLr, PARITY_ENf, NULL, 421 INVALIDr, INVALIDf, NULL, 422 VFI_PARITY_STATUSr, NULL, INVALIDf, 423 INVALIDr, INVALIDf, 424 INVALIDr, NULL, INVALIDr, INVALIDr, 425 _SOC_SER_SKIP_GH2_A0 426 }, 427 #endif /* _GH2_SER_TEST_IP0 */ 428 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 429 }; 430 431 static _soc_gh2_ser_info_t _soc_gh2_ip1_ser_info[] = { 432 #if _GH2_SER_TEST_IP1 433 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 434 L3_ENTRY_PAR_ERRf, L3_ENTRY_PAR_ERRf, 435 L3_ENTRY_ONLYm, NULL, 436 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, NULL, 437 INVALIDr, INVALIDf, NULL, 438 INVALIDr, _soc_gh2_l3_entry_regs, INVALIDf, 439 INVALIDr, INVALIDf, 440 INVALIDr, NULL, INVALIDr, INVALIDr, 441 0 442 }, 443 { _SOC_PARITY_TYPE_PARITY, NULL, 444 L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, 445 L2_USER_ENTRYm, NULL, 446 L2_USER_ENTRY_DATA_ONLY_PARITY_CONTROLr, PARITY_ENf, NULL, 447 INVALIDr, INVALIDf, NULL, 448 L2_USER_ENTRY_DATA_ONLY_PARITY_STATUSr, NULL, INVALIDf, 449 INVALIDr, INVALIDf, 450 INVALIDr, NULL, INVALIDr, INVALIDr, 451 0 452 }, 453 { _SOC_PARITY_TYPE_PARITY, NULL, 454 L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, 455 L2_USER_ENTRY_DATA_ONLYm, NULL, 456 L2_USER_ENTRY_DATA_ONLY_PARITY_CONTROLr, PARITY_ENf, NULL, 457 INVALIDr, INVALIDf, NULL, 458 L2_USER_ENTRY_DATA_ONLY_PARITY_STATUSr, NULL, INVALIDf, 459 INVALIDr, INVALIDf, 460 INVALIDr, NULL, INVALIDr, INVALIDr, 461 0 462 }, 463 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 464 L2_ENTRY_PAR_ERRf, L2_ENTRY_PAR_ERRf, 465 L2Xm, "L2_ENTRY/L2_ENTRY_ONLY", 466 L2_ENTRY_PARITY_CONTROLr, PARITY_ENf, NULL, 467 INVALIDr, INVALIDf, NULL, 468 INVALIDr, _soc_gh2_l2_entry_regs, INVALIDf, 469 INVALIDr, INVALIDf, 470 INVALIDr, NULL, INVALIDr, INVALIDr, 471 0 472 }, 473 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 474 L2_ENTRY_PAR_ERRf, L2_ENTRY_PAR_ERRf, 475 SR_L2_ENTRYm, "SR_L2_ENTRY", 476 L2_ENTRY_PARITY_CONTROLr, PARITY_ENf, NULL, 477 INVALIDr, INVALIDf, NULL, 478 INVALIDr, _soc_gh2_l2_entry_regs, INVALIDf, 479 INVALIDr, INVALIDf, 480 INVALIDr, NULL, INVALIDr, INVALIDr, 481 _SOC_SER_SKIP_GH2_A0 482 }, 483 { _SOC_PARITY_TYPE_PARITY, NULL, 484 RTAG7_FLOW_BASED_HASH_PARITY_INTRf, RTAG7_FLOW_BASED_HASH_PARITY_INTRf, 485 RTAG7_FLOW_BASED_HASHm, NULL, 486 RTAG7_FLOW_BASED_HASH_PARITY_CONTROLr, PARITY_ENf, NULL, 487 INVALIDr, INVALIDf, NULL, 488 RTAG7_FLOW_BASED_HASH_PARITY_STATUSr, NULL, INVALIDf, 489 INVALIDr, INVALIDf, 490 INVALIDr, NULL, INVALIDr, INVALIDr, 491 0 492 }, 493 { _SOC_PARITY_TYPE_PARITY, NULL, 494 RTAG7_PORT_BASED_HASH_PARITY_INTRf, RTAG7_PORT_BASED_HASH_PARITY_INTRf, 495 RTAG7_PORT_BASED_HASHm, NULL, 496 RTAG7_PORT_BASED_HASH_PARITY_CONTROLr, PARITY_ENf, NULL, 497 INVALIDr, INVALIDf, NULL, 498 RTAG7_PORT_BASED_HASH_PARITY_STATUSr, NULL, INVALIDf, 499 INVALIDr, INVALIDf, 500 INVALIDr, NULL, INVALIDr, INVALIDr, 501 0 502 }, 503 /* SR_RX_FLOW_ID_POOLm is 2 bit ECC (ECC_ERRf = 1) */ 504 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 505 RX_FLOW_ID_ECC_STATUS_INTRf, RX_FLOW_ID_ECC_STATUS_INTRf, 506 SR_RX_FLOW_ID_POOLm, "SR_RX_FLOW_ID_POOLm 2 bit ECC", 507 SR_RX_FLOW_ID_POOL_ECC_CONTROLr, ECC_ENf, NULL, 508 INVALIDr, INVALIDf, NULL, 509 SR_RX_FLOW_ID_POOL_ECC_STATUS_INTRr, NULL, ECC_ERRf, 510 INVALIDr, INVALIDf, 511 INVALIDr, NULL, INVALIDr, INVALIDr, 512 0 513 }, 514 { _SOC_PARITY_TYPE_PARITY, NULL, 515 RX_FLOW_ID_PARITY_STATUS_INTRf, RX_FLOW_ID_PARITY_STATUS_INTRf, 516 INVALIDm, "SR_RX_FLOW_ID_POOL PARITY", 517 SR_RX_FLOW_ID_POOL_ECC_CONTROLr, ECC_ENf, NULL, 518 INVALIDr, INVALIDf, NULL, 519 SR_RX_FLOW_ID_POOL_PARITY_STATUS_INTRr, NULL, INVALIDf, 520 INVALIDr, INVALIDf, 521 INVALIDr, NULL, INVALIDr, INVALIDr, 522 0 523 }, 524 /* SR_TX_FLOW_ID_POOLm is 2 bit ECC (ECC_ERRf = 1) */ 525 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 526 TX_FLOW_ID_ECC_STATUS_INTRf, TX_FLOW_ID_ECC_STATUS_INTRf, 527 SR_TX_FLOW_ID_POOLm, "SR_TX_FLOW_ID_POOL 2 bit ECC", 528 SR_TX_FLOW_ID_POOL_ECC_CONTROLr, ECC_ENf, NULL, 529 INVALIDr, INVALIDf, NULL, 530 SR_TX_FLOW_ID_POOL_ECC_STATUS_INTRr, NULL, ECC_ERRf, 531 INVALIDr, INVALIDf, 532 INVALIDr, NULL, INVALIDr, INVALIDr, 533 0 534 }, 535 { _SOC_PARITY_TYPE_PARITY, NULL, 536 TX_FLOW_ID_PARITY_STATUS_INTRf, TX_FLOW_ID_PARITY_STATUS_INTRf, 537 INVALIDm, "SR_TX_FLOW_ID_POOL PARITY", 538 SR_TX_FLOW_ID_POOL_ECC_CONTROLr, ECC_ENf, NULL, 539 INVALIDr, INVALIDf, NULL, 540 SR_TX_FLOW_ID_POOL_PARITY_STATUS_INTRr, NULL, INVALIDf, 541 INVALIDr, INVALIDf, 542 INVALIDr, NULL, INVALIDr, INVALIDr, 543 0 544 }, 545 { _SOC_PARITY_TYPE_PARITY, NULL, 546 L3_DEFIP_DATA_PAR_ERRf, L3_DEFIP_DATA_PAR_ERRf, 547 L3_DEFIPm, NULL, 548 L3_DEFIP_PARITY_CONTROLr, PARITY_ENf, NULL, 549 INVALIDr, INVALIDf, NULL, 550 L3_DEFIP_PARITY_STATUSr, NULL, INVALIDf, 551 INVALIDr, INVALIDf, 552 INVALIDr, NULL, INVALIDr, INVALIDr, 553 0 554 }, 555 { _SOC_PARITY_TYPE_PARITY, NULL, 556 L3_DEFIP_DATA_PAR_ERRf, L3_DEFIP_DATA_PAR_ERRf, 557 L3_DEFIP_DATA_ONLYm, NULL, 558 L3_DEFIP_PARITY_CONTROLr, PARITY_ENf, NULL, 559 INVALIDr, INVALIDf, NULL, 560 L3_DEFIP_PARITY_STATUSr, NULL, INVALIDf, 561 INVALIDr, INVALIDf, 562 INVALIDr, NULL, INVALIDr, INVALIDr, 563 0 564 }, 565 #endif /* _GH2_SER_TEST_IP1 */ 566 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 567 }; 568 569 static _soc_gh2_ser_info_t _soc_gh2_ip2_ser_info[] = { 570 #if _GH2_SER_TEST_IP2 571 { _SOC_PARITY_TYPE_PARITY, NULL, 572 EGR_MASK_PAR_ERRf, EGR_MASK_PAR_ERRf, 573 EGR_MASKm, NULL, 574 EGR_MASK_PARITY_CONTROLr, PARITY_ENf, NULL, 575 INVALIDr, INVALIDf, NULL, 576 EGR_MASK_PARITY_STATUSr, NULL, INVALIDf, 577 INVALIDr, INVALIDf, 578 INVALIDr, NULL, INVALIDr, INVALIDr, 579 0 580 }, 581 { _SOC_PARITY_TYPE_PARITY, NULL, 582 EGR_MASK_MODBASE_PAR_ERRf, EGR_MASK_MODBASE_PAR_ERRf, 583 EGR_MASK_MODBASEm, NULL, 584 EGR_MASK_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 585 INVALIDr, INVALIDf, NULL, 586 EGR_MASK_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 587 INVALIDr, INVALIDf, 588 INVALIDr, NULL, INVALIDr, INVALIDr, 589 0 590 }, 591 { _SOC_PARITY_TYPE_PARITY, NULL, 592 RMEP_PAR_ERRf, RMEP_PAR_ERRf, 593 RMEPm, NULL, 594 RMEP_PARITY_CONTROLr, PARITY_ENf, NULL, 595 INVALIDr, INVALIDf, NULL, 596 RMEP_PARITY_STATUSr, NULL, INVALIDf, 597 INVALIDr, INVALIDf, 598 INVALIDr, NULL, INVALIDr, INVALIDr, 599 0 600 }, 601 { _SOC_PARITY_TYPE_PARITY, NULL, 602 TRUNK_GROUP_PAR_ERRf, TRUNK_GROUP_PAR_ERRf, 603 TRUNK_GROUPm, NULL, 604 TRUNK_GROUP_PARITY_CONTROLr, PARITY_ENf, NULL, 605 INVALIDr, INVALIDf, NULL, 606 TRUNK_GROUP_PARITY_STATUSr, NULL, INVALIDf, 607 INVALIDr, INVALIDf, 608 INVALIDr, NULL, INVALIDr, INVALIDr, 609 0 610 }, 611 { _SOC_PARITY_TYPE_PARITY, NULL, 612 L3_ECMP_PAR_ERRf, L3_ECMP_PAR_ERRf, 613 L3_ECMPm, NULL, 614 L3_ECMP_PARITY_CONTROLr, PARITY_ENf, NULL, 615 INVALIDr, INVALIDf, NULL, 616 L3_ECMP_PARITY_STATUSr, NULL, INVALIDf, 617 INVALIDr, INVALIDf, 618 INVALIDr, NULL, INVALIDr, INVALIDr, 619 0 620 }, 621 { _SOC_PARITY_TYPE_PARITY, NULL, 622 L3_ECMP_GROUP_PAR_ERRf, L3_ECMP_GROUP_PAR_ERRf, 623 L3_ECMP_COUNTm, NULL, 624 L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, NULL, 625 INVALIDr, INVALIDf, NULL, 626 L3_ECMP_GROUP_PARITY_STATUSr, NULL, INVALIDf, 627 INVALIDr, INVALIDf, 628 INVALIDr, NULL, INVALIDr, INVALIDr, 629 0 630 }, 631 { _SOC_PARITY_TYPE_PARITY, NULL, 632 VLAN_PROFILE_2_PAR_ERRf, VLAN_PROFILE_2_PAR_ERRf, 633 VLAN_PROFILE_2m, NULL, 634 VLAN_PROFILE_2_PARITY_CONTROLr, PARITY_ENf, NULL, 635 INVALIDr, INVALIDf, NULL, 636 VLAN_PROFILE_2_PARITY_STATUSr, NULL, INVALIDf, 637 INVALIDr, INVALIDf, 638 INVALIDr, NULL, INVALIDr, INVALIDr, 639 0 640 }, 641 { _SOC_PARITY_TYPE_PARITY, NULL, 642 IFP_STORM_CONTROL_PAR_ERRf, IFP_STORM_CONTROL_PAR_ERRf, 643 FP_STORM_CONTROL_METERSm, NULL, 644 IFP_STORM_CONTROL_PARITY_CONTROLr, PARITY_ENf, NULL, 645 INVALIDr, INVALIDf, NULL, 646 IFP_STORM_CONTROL_PARITY_STATUSr, NULL, INVALIDf, 647 INVALIDr, INVALIDf, 648 INVALIDr, NULL, INVALIDr, INVALIDr, 649 0 650 }, 651 { _SOC_PARITY_TYPE_PARITY, NULL, 652 NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, 653 NONUCAST_TRUNK_BLOCK_MASKm, NULL, 654 NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, NULL, 655 INVALIDr, INVALIDf, NULL, 656 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUSr, NULL, INVALIDf, 657 INVALIDr, INVALIDf, 658 INVALIDr, NULL, INVALIDr, INVALIDr, 659 0 660 }, 661 { _SOC_PARITY_TYPE_PARITY, NULL, 662 SRC_MODID_BLOCK_PAR_ERRf, SRC_MODID_BLOCK_PAR_ERRf, 663 SRC_MODID_BLOCKm, NULL, 664 SRC_MODID_BLOCK_PARITY_CONTROLr, PARITY_ENf, NULL, 665 INVALIDr, INVALIDf, NULL, 666 SRC_MODID_BLOCK_PARITY_STATUSr, NULL, INVALIDf, 667 INVALIDr, INVALIDf, 668 INVALIDr, NULL, INVALIDr, INVALIDr, 669 0 670 }, 671 { _SOC_PARITY_TYPE_PARITY, NULL, 672 IFP_METER_PAR_ERRf, IFP_METER_PAR_ERRf, 673 FP_METER_TABLEm, NULL, 674 IFP_METER_PARITY_CONTROLr, PARITY_ENf, NULL, 675 INVALIDr, INVALIDf, NULL, 676 IFP_METER_PARITY_STATUSr, NULL, INVALIDf, 677 INVALIDr, INVALIDf, 678 INVALIDr, NULL, INVALIDr, INVALIDr, 679 0 680 }, 681 { _SOC_PARITY_TYPE_PARITY, NULL, 682 INITIAL_L3_ECMP_GROUP_PAR_ERRf, INITIAL_L3_ECMP_GROUP_PAR_ERRf, 683 INITIAL_L3_ECMP_GROUPm, NULL, 684 INITIAL_L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, NULL, 685 INVALIDr, INVALIDf, NULL, 686 INITIAL_L3_ECMP_GROUP_PARITY_STATUSr, NULL, INVALIDf, 687 INVALIDr, INVALIDf, 688 INVALIDr, NULL, INVALIDr, INVALIDr, 689 0 690 }, 691 { _SOC_PARITY_TYPE_PARITY, NULL, 692 INITIAL_L3_ECMP_PAR_ERRf, INITIAL_L3_ECMP_PAR_ERRf, 693 INITIAL_L3_ECMPm, NULL, 694 INITIAL_L3_ECMP_PARITY_CONTROLr, PARITY_ENf, NULL, 695 INVALIDr, INVALIDf, NULL, 696 INITIAL_L3_ECMP_PARITY_STATUSr, NULL, INVALIDf, 697 INVALIDr, INVALIDf, 698 INVALIDr, NULL, INVALIDr, INVALIDr, 699 0 700 }, 701 { _SOC_PARITY_TYPE_PARITY, NULL, 702 MODPORT_MAP_SW_PAR_ERRf, MODPORT_MAP_SW_PAR_ERRf, 703 MODPORT_MAP_SWm, NULL, 704 MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, NULL, 705 INVALIDr, INVALIDf, NULL, 706 MODPORT_MAP_SW_PARITY_STATUSr, NULL, INVALIDf, 707 INVALIDr, INVALIDf, 708 INVALIDr, NULL, INVALIDr, INVALIDr, 709 0 710 }, 711 { _SOC_PARITY_TYPE_PARITY, NULL, 712 MODPORT_MAP_IM_PAR_ERRf, MODPORT_MAP_IM_PAR_ERRf, 713 MODPORT_MAP_IMm, NULL, 714 MODPORT_MAP_IM_PARITY_CONTROLr, PARITY_ENf, NULL, 715 INVALIDr, INVALIDf, NULL, 716 MODPORT_MAP_IM_PARITY_STATUSr, NULL, INVALIDf, 717 INVALIDr, INVALIDf, 718 INVALIDr, NULL, INVALIDr, INVALIDr, 719 0 720 }, 721 { _SOC_PARITY_TYPE_PARITY, NULL, 722 MODPORT_MAP_EM_PAR_ERRf, MODPORT_MAP_EM_PAR_ERRf, 723 MODPORT_MAP_EMm, NULL, 724 MODPORT_MAP_EM_PARITY_CONTROLr, PARITY_ENf, NULL, 725 INVALIDr, INVALIDf, NULL, 726 MODPORT_MAP_EM_PARITY_STATUSr, NULL, INVALIDf, 727 INVALIDr, INVALIDf, 728 INVALIDr, NULL, INVALIDr, INVALIDr, 729 0 730 }, 731 { _SOC_PARITY_TYPE_PARITY, NULL, 732 ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, 733 ALTERNATE_EMIRROR_BITMAPm, NULL, 734 ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, NULL, 735 INVALIDr, INVALIDf, NULL, 736 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUSr, NULL, INVALIDf, 737 INVALIDr, INVALIDf, 738 INVALIDr, NULL, INVALIDr, INVALIDr, 739 0 740 }, 741 { _SOC_PARITY_TYPE_PARITY, NULL, 742 MAC_BLOCK_TABLE_PAR_ERRf, MAC_BLOCK_TABLE_PAR_ERRf, 743 MAC_BLOCKm, "MAC_BLOCK_TABLE", 744 MAC_BLOCK_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 745 INVALIDr, INVALIDf, NULL, 746 MAC_BLOCK_TABLE_PARITY_STATUSr, NULL, INVALIDf, 747 INVALIDr, INVALIDf, 748 INVALIDr, NULL, INVALIDr, INVALIDr, 749 0 750 }, 751 { _SOC_PARITY_TYPE_PARITY, NULL, 752 TRUNK_EGR_MASK_PAR_ERRf, TRUNK_EGR_MASK_PAR_ERRf, 753 TRUNK_EGR_MASKm, NULL, 754 TRUNK_EGR_MASK_PARITY_CONTROLr, PARITY_ENf, NULL, 755 INVALIDr, INVALIDf, NULL, 756 TRUNK_EGR_MASK_PARITY_STATUSr, NULL, INVALIDf, 757 INVALIDr, INVALIDf, 758 INVALIDr, NULL, INVALIDr, INVALIDr, 759 0 760 }, 761 { _SOC_PARITY_TYPE_PARITY, NULL, 762 L3_MTU_VALUES_PAR_ERRf, L3_MTU_VALUES_PAR_ERRf, 763 L3_MTU_VALUESm, NULL, 764 L3_MTU_VALUES_PARITY_CONTROLr, PARITY_ENf, NULL, 765 INVALIDr, INVALIDf, NULL, 766 L3_MTU_VALUES_PARITY_STATUSr, NULL, INVALIDf, 767 INVALIDr, INVALIDf, 768 INVALIDr, NULL, INVALIDr, INVALIDr, 769 0 770 }, 771 { _SOC_PARITY_TYPE_PARITY, NULL, 772 OAM_LM_COUNTERS_PAR_ERRf, OAM_LM_COUNTERS_PAR_ERRf, 773 OAM_LM_COUNTERSm, NULL, 774 OAM_LM_COUNTERS_PARITY_CONTROLr, PARITY_ENf, NULL, 775 INVALIDr, INVALIDf, NULL, 776 OAM_LM_COUNTERS_PARITY_STATUSr, NULL, INVALIDf, 777 INVALIDr, INVALIDf, 778 INVALIDr, NULL, INVALIDr, INVALIDr, 779 0 780 }, 781 { _SOC_PARITY_TYPE_PARITY, NULL, 782 ING_VLAN_COUNTER_PAR_ERRf, ING_VLAN_COUNTER_PAR_ERRf, 783 ING_VLAN_COUNTER_TABLEm, NULL, 784 ING_VLAN_COUNTER_PARITY_CONTROLr, PARITY_ENf, NULL, 785 INVALIDr, INVALIDf, NULL, 786 ING_VLAN_COUNTER_PARITY_STATUSr, NULL, INVALIDf, 787 INVALIDr, INVALIDf, 788 INVALIDr, NULL, INVALIDr, INVALIDr, 789 0 790 }, 791 { _SOC_PARITY_TYPE_PARITY, NULL, 792 ING_RX_COUNTER_PAR_ERRf, ING_RX_COUNTER_PAR_ERRf, 793 ING_RX_COUNTERm, NULL, 794 ING_RX_COUNTER_PARITY_CONTROLr, PARITY_ENf, NULL, 795 INVALIDr, INVALIDf, NULL, 796 ING_RX_COUNTER_PARITY_STATUSr, NULL, INVALIDf, 797 INVALIDr, INVALIDf, 798 INVALIDr, NULL, INVALIDr, INVALIDr, 799 0 800 }, 801 { _SOC_PARITY_TYPE_PARITY, NULL, 802 MAID_REDUCTION_PAR_ERRf, MAID_REDUCTION_PAR_ERRf, 803 MAID_REDUCTIONm, NULL, 804 MAID_REDUCTION_PARITY_CONTROLr, PARITY_ENf, NULL, 805 INVALIDr, INVALIDf, NULL, 806 MAID_REDUCTION_PARITY_STATUSr, NULL, INVALIDf, 807 INVALIDr, INVALIDf, 808 INVALIDr, NULL, INVALIDr, INVALIDr, 809 0 810 }, 811 { _SOC_PARITY_TYPE_PARITY, NULL, 812 TRUNK_BITMAP_TABLE_PAR_ERRf, TRUNK_BITMAP_TABLE_PAR_ERRf, 813 TRUNK_BITMAPm, NULL, 814 TRUNK_BITMAP_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 815 INVALIDr, INVALIDf, NULL, 816 TRUNK_BITMAP_TABLE_PARITY_STATUSr, NULL, INVALIDf, 817 INVALIDr, INVALIDf, 818 INVALIDr, NULL, INVALIDr, INVALIDr, 819 0 820 }, 821 { _SOC_PARITY_TYPE_PARITY, NULL, 822 MA_STATE_PAR_ERRf, MA_STATE_PAR_ERRf, 823 MA_STATEm, NULL, 824 MA_STATE_PARITY_CONTROLr, PARITY_ENf, NULL, 825 INVALIDr, INVALIDf, NULL, 826 MA_STATE_PARITY_STATUSr, NULL, INVALIDf, 827 INVALIDr, INVALIDf, 828 INVALIDr, NULL, INVALIDr, INVALIDr, 829 0 830 }, 831 { _SOC_PARITY_TYPE_PARITY, NULL, 832 ING_NHOP_PAR_ERRf, ING_NHOP_PAR_ERRf, 833 ING_L3_NEXT_HOPm, NULL, 834 ING_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, NULL, 835 INVALIDr, INVALIDf, NULL, 836 ING_L3_NEXT_HOP_PARITY_STATUSr, NULL, INVALIDf, 837 INVALIDr, INVALIDf, 838 INVALIDr, NULL, INVALIDr, INVALIDr, 839 0 840 }, 841 { _SOC_PARITY_TYPE_PARITY, NULL, 842 INITIAL_NHOP_PAR_ERRf, INITIAL_NHOP_PAR_ERRf, 843 INITIAL_ING_L3_NEXT_HOPm, NULL, 844 INITIAL_NHOP_PARITY_CONTROLr, PARITY_ENf, NULL, 845 INVALIDr, INVALIDf, NULL, 846 INITIAL_NHOP_PARITY_STATUSr, NULL, INVALIDf, 847 INVALIDr, INVALIDf, 848 INVALIDr, NULL, INVALIDr, INVALIDr, 849 0 850 }, 851 { _SOC_PARITY_TYPE_PARITY, NULL, 852 IFP_POLICY_PAR_ERRf, IFP_POLICY_PAR_ERRf, 853 FP_POLICY_TABLEm, NULL, 854 IFP_POLICY_PARITY_CONTROLr, PARITY_ENf, NULL, 855 INVALIDr, INVALIDf, NULL, 856 IFP_POLICY_PARITY_STATUSr, NULL, INVALIDf, 857 INVALIDr, INVALIDf, 858 INVALIDr, NULL, INVALIDr, INVALIDr, 859 0 860 }, 861 { _SOC_PARITY_TYPE_PARITY, NULL, 862 IFP_COUNTER_PAR_ERRf, IFP_COUNTER_PAR_ERRf, 863 FP_COUNTER_TABLEm, NULL, 864 IFP_COUNTER_PARITY_CONTROLr, PARITY_ENf, NULL, 865 INVALIDr, INVALIDf, NULL, 866 IFP_COUNTER_PARITY_STATUSr, NULL, INVALIDf, 867 INVALIDr, INVALIDf, 868 INVALIDr, NULL, INVALIDr, INVALIDr, 869 0 870 }, 871 { _SOC_PARITY_TYPE_PARITY, NULL, 872 MA_INDEX_PAR_ERRf, MA_INDEX_PAR_ERRf, 873 MA_INDEXm, NULL, 874 MA_INDEX_PARITY_CONTROLr, PARITY_ENf, NULL, 875 INVALIDr, INVALIDf, NULL, 876 MA_INDEX_PARITY_STATUSr, NULL, INVALIDf, 877 INVALIDr, INVALIDf, 878 INVALIDr, NULL, INVALIDr, INVALIDr, 879 0 880 }, 881 { _SOC_PARITY_TYPE_PARITY, NULL, 882 L3_IPMC_1_PAR_ERRf, L3_IPMC_1_PAR_ERRf, 883 L3_IPMC_1m, NULL, 884 L3_IPMC_1_PARITY_CONTROLr, PARITY_ENf, NULL, 885 INVALIDr, INVALIDf, NULL, 886 L3_IPMC_1_PARITY_STATUSr, NULL, INVALIDf, 887 INVALIDr, INVALIDf, 888 INVALIDr, NULL, INVALIDr, INVALIDr, 889 _SOC_SER_SKIP_GH2_A0 890 }, 891 { _SOC_PARITY_TYPE_PARITY, NULL, 892 L3_IPMC_PAR_ERRf, L3_IPMC_PAR_ERRf, 893 L3_IPMCm, NULL, 894 L3_IPMC_PARITY_CONTROLr, PARITY_ENf, NULL, 895 INVALIDr, INVALIDf, NULL, 896 L3_IPMC_PARITY_STATUSr, NULL, INVALIDf, 897 INVALIDr, INVALIDf, 898 INVALIDr, NULL, INVALIDr, INVALIDr, 899 _SOC_SER_SKIP_GH2_A0 900 }, 901 { _SOC_PARITY_TYPE_PARITY, NULL, 902 L2MC_PAR_ERRf, L2MC_PAR_ERRf, 903 L2MCm, NULL, 904 L2MC_PARITY_CONTROLr, PARITY_ENf, NULL, 905 INVALIDr, INVALIDf, NULL, 906 L2MC_PARITY_STATUSr, NULL, INVALIDf, 907 INVALIDr, INVALIDf, 908 INVALIDr, NULL, INVALIDr, INVALIDr, 909 _SOC_SER_SKIP_GH2_A0 910 }, 911 #endif /* _GH2_SER_TEST_IP2 */ 912 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 913 }; 914 915 static _soc_gh2_ser_info_t _soc_gh2_ip2_sr_ser_info[] = { 916 #if _GH2_SER_TEST_IP2_SR 917 /* SR_MAC_PROXY_PROFILEm is 2 bit ECC (ECC_ERRf = 1) */ 918 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 919 SR_MAC_PROXY_PROFILE_ECC_ERRf, SR_MAC_PROXY_PROFILE_ECC_ERRf, 920 SR_MAC_PROXY_PROFILEm, "SR_MAC_PROXY_PROFILE 2 bit ECC", 921 SR_MAC_PROXY_PROFILE_ECC_CONTROLr, ECC_ENf, NULL, 922 INVALIDr, INVALIDf, NULL, 923 SR_MAC_PROXY_PROFILE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 924 INVALIDr, INVALIDf, 925 INVALIDr, NULL, INVALIDr, INVALIDr, 926 0 927 }, 928 { _SOC_PARITY_TYPE_PARITY, NULL, 929 SR_MAC_PROXY_PROFILE_1BIT_ERRf, SR_MAC_PROXY_PROFILE_1BIT_ERRf, 930 INVALIDm, NULL, 931 SR_MAC_PROXY_PROFILE_ECC_CONTROLr, ECC_ENf, NULL, 932 INVALIDr, INVALIDf, NULL, 933 SR_MAC_PROXY_PROFILE_PARITY_STATUSr, NULL, INVALIDf, 934 INVALIDr, INVALIDf, 935 INVALIDr, NULL, INVALIDr, INVALIDr, 936 0 937 }, 938 /* SR_FLOW_ING_COUNTER_CONTROLm is 2 bit ECC (ECC_ERRf = 1) */ 939 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 940 SR_FLOW_ING_COUNTER_CONTROL_ECC_ERRf, SR_FLOW_ING_COUNTER_CONTROL_ECC_ERRf, 941 SR_FLOW_ING_COUNTER_CONTROLm, "SR_FLOW_ING_COUNTER_CONTROL 2 bit ECC", 942 SR_FLOW_ING_COUNTER_CONTROL_ECC_CONTROLr, ECC_ENf, NULL, 943 INVALIDr, INVALIDf, NULL, 944 SR_FLOW_ING_COUNTER_CONTROL_ECC_STATUSr, NULL, ECC_ERRf, 945 INVALIDr, INVALIDf, 946 INVALIDr, NULL, INVALIDr, INVALIDr, 947 0 948 }, 949 { _SOC_PARITY_TYPE_PARITY, NULL, 950 SR_FLOW_ING_COUNTER_CONTROL_1BIT_ERRf, SR_FLOW_ING_COUNTER_CONTROL_1BIT_ERRf, 951 INVALIDm, NULL, 952 SR_FLOW_ING_COUNTER_CONTROL_ECC_CONTROLr, ECC_ENf, NULL, 953 INVALIDr, INVALIDf, NULL, 954 SR_FLOW_ING_COUNTER_CONTROL_PARITY_STATUSr, NULL, INVALIDf, 955 INVALIDr, INVALIDf, 956 INVALIDr, NULL, INVALIDr, INVALIDr, 957 0 958 }, 959 { _SOC_PARITY_TYPE_PARITY, NULL, 960 SR_FLOW_COUNT_POOL0_PAR_ERRf, SR_FLOW_COUNT_POOL0_PAR_ERRf, 961 SR_FLOW_COUNT_POOL0m, NULL, 962 SR_FLOW_COUNT_POOL0_PARITY_CONTROLr, PARITY_ENf, NULL, 963 INVALIDr, INVALIDf, NULL, 964 SR_FLOW_COUNT_POOL0_PARITY_STATUSr, NULL, INVALIDf, 965 INVALIDr, INVALIDf, 966 INVALIDr, NULL, INVALIDr, INVALIDr, 967 0 968 }, 969 { _SOC_PARITY_TYPE_PARITY, NULL, 970 SR_FLOW_COUNT_POOL1_PAR_ERRf, SR_FLOW_COUNT_POOL1_PAR_ERRf, 971 SR_FLOW_COUNT_POOL1m, NULL, 972 SR_FLOW_COUNT_POOL1_PARITY_CONTROLr, PARITY_ENf, NULL, 973 INVALIDr, INVALIDf, NULL, 974 SR_FLOW_COUNT_POOL1_PARITY_STATUSr, NULL, INVALIDf, 975 INVALIDr, INVALIDf, 976 INVALIDr, NULL, INVALIDr, INVALIDr, 977 0 978 }, 979 { _SOC_PARITY_TYPE_PARITY, NULL, 980 SR_FLOW_COUNT_POOL2_PAR_ERRf, SR_FLOW_COUNT_POOL2_PAR_ERRf, 981 SR_FLOW_COUNT_POOL2m, NULL, 982 SR_FLOW_COUNT_POOL2_PARITY_CONTROLr, PARITY_ENf, NULL, 983 INVALIDr, INVALIDf, NULL, 984 SR_FLOW_COUNT_POOL2_PARITY_STATUSr, NULL, INVALIDf, 985 INVALIDr, INVALIDf, 986 INVALIDr, NULL, INVALIDr, INVALIDr, 987 0 988 }, 989 { _SOC_PARITY_TYPE_PARITY, NULL, 990 SR_FLOW_COUNT_POOL3_PAR_ERRf, SR_FLOW_COUNT_POOL3_PAR_ERRf, 991 SR_FLOW_COUNT_POOL3m, NULL, 992 SR_FLOW_COUNT_POOL3_PARITY_CONTROLr, PARITY_ENf, NULL, 993 INVALIDr, INVALIDf, NULL, 994 SR_FLOW_COUNT_POOL3_PARITY_STATUSr, NULL, INVALIDf, 995 INVALIDr, INVALIDf, 996 INVALIDr, NULL, INVALIDr, INVALIDr, 997 0 998 }, 999 { _SOC_PARITY_TYPE_PARITY, NULL, 1000 SR_FLOW_COUNT_POOL4_PAR_ERRf, SR_FLOW_COUNT_POOL4_PAR_ERRf, 1001 SR_FLOW_COUNT_POOL4m, NULL, 1002 SR_FLOW_COUNT_POOL4_PARITY_CONTROLr, PARITY_ENf, NULL, 1003 INVALIDr, INVALIDf, NULL, 1004 SR_FLOW_COUNT_POOL4_PARITY_STATUSr, NULL, INVALIDf, 1005 INVALIDr, INVALIDf, 1006 INVALIDr, NULL, INVALIDr, INVALIDr, 1007 0 1008 }, 1009 { _SOC_PARITY_TYPE_PARITY, NULL, 1010 SR_FLOW_COUNT_POOL5_PAR_ERRf, SR_FLOW_COUNT_POOL5_PAR_ERRf, 1011 SR_FLOW_COUNT_POOL5m, NULL, 1012 SR_FLOW_COUNT_POOL5_PARITY_CONTROLr, PARITY_ENf, NULL, 1013 INVALIDr, INVALIDf, NULL, 1014 SR_FLOW_COUNT_POOL5_PARITY_STATUSr, NULL, INVALIDf, 1015 INVALIDr, INVALIDf, 1016 INVALIDr, NULL, INVALIDr, INVALIDr, 1017 0 1018 }, 1019 { _SOC_PARITY_TYPE_PARITY, NULL, 1020 SR_FLOW_COUNT_POOL6_PAR_ERRf, SR_FLOW_COUNT_POOL6_PAR_ERRf, 1021 SR_FLOW_COUNT_POOL6m, NULL, 1022 SR_FLOW_COUNT_POOL6_PARITY_CONTROLr, PARITY_ENf, NULL, 1023 INVALIDr, INVALIDf, NULL, 1024 SR_FLOW_COUNT_POOL6_PARITY_STATUSr, NULL, INVALIDf, 1025 INVALIDr, INVALIDf, 1026 INVALIDr, NULL, INVALIDr, INVALIDr, 1027 0 1028 }, 1029 { _SOC_PARITY_TYPE_PARITY, NULL, 1030 SR_FLOW_COUNT_POOL7_PAR_ERRf, SR_FLOW_COUNT_POOL7_PAR_ERRf, 1031 SR_FLOW_COUNT_POOL7m, NULL, 1032 SR_FLOW_COUNT_POOL7_PARITY_CONTROLr, PARITY_ENf, NULL, 1033 INVALIDr, INVALIDf, NULL, 1034 SR_FLOW_COUNT_POOL7_PARITY_STATUSr, NULL, INVALIDf, 1035 INVALIDr, INVALIDf, 1036 INVALIDr, NULL, INVALIDr, INVALIDr, 1037 0 1038 }, 1039 { _SOC_PARITY_TYPE_PARITY, NULL, 1040 SR_PORT_COUNT_RX_PAR_ERRf, SR_PORT_COUNT_RX_PAR_ERRf, 1041 SR_PORT_COUNT_RXm, NULL, 1042 SR_PORT_COUNT_RX_PARITY_CONTROLr, PARITY_ENf, NULL, 1043 INVALIDr, INVALIDf, NULL, 1044 SR_PORT_COUNT_RX_PARITY_STATUSr, NULL, INVALIDf, 1045 INVALIDr, INVALIDf, 1046 INVALIDr, NULL, INVALIDr, INVALIDr, 1047 0 1048 }, 1049 { _SOC_PARITY_TYPE_PARITY, NULL, 1050 SR_PORT_COUNT_RX_TAGGED_PAR_ERRf, SR_PORT_COUNT_RX_TAGGED_PAR_ERRf, 1051 SR_PORT_COUNT_RX_TAGGEDm, "SR_PORT_COUNT_RX_TAGGED", 1052 SR_PORT_COUNT_RX_TAGGED_PARITY_CONTROLr, PARITY_ENf, NULL, 1053 INVALIDr, INVALIDf, NULL, 1054 SR_PORT_COUNT_RX_TAGGED_PARITY_STATUSr, NULL, INVALIDf, 1055 INVALIDr, INVALIDf, 1056 INVALIDr, NULL, INVALIDr, INVALIDr, 1057 0 1058 }, 1059 { _SOC_PARITY_TYPE_PARITY, NULL, 1060 SR_PORT_COUNT_RX_WRONG_LAN_PAR_ERRf, SR_PORT_COUNT_RX_WRONG_LAN_PAR_ERRf, 1061 SR_PORT_COUNT_RX_WRONG_LANm, "SR_PORT_COUNT_RX_WRONG_LAN", 1062 SR_PORT_COUNT_RX_WRONG_LAN_PARITY_CONTROLr, PARITY_ENf, NULL, 1063 INVALIDr, INVALIDf, NULL, 1064 SR_PORT_COUNT_RX_WRONG_LAN_PARITY_STATUSr, NULL, INVALIDf, 1065 INVALIDr, INVALIDf, 1066 INVALIDr, NULL, INVALIDr, INVALIDr, 1067 0 1068 }, 1069 { _SOC_PARITY_TYPE_PARITY, NULL, 1070 SR_PORT_COUNT_RX_ERROR_PAR_ERRf, SR_PORT_COUNT_RX_ERROR_PAR_ERRf, 1071 SR_PORT_COUNT_RX_ERRORm, "SR_PORT_COUNT_RX_ERROR", 1072 SR_PORT_COUNT_RX_ERROR_PARITY_CONTROLr, PARITY_ENf, NULL, 1073 INVALIDr, INVALIDf, NULL, 1074 SR_PORT_COUNT_RX_ERROR_PARITY_STATUSr, NULL, INVALIDf, 1075 INVALIDr, INVALIDf, 1076 INVALIDr, NULL, INVALIDr, INVALIDr, 1077 0 1078 }, 1079 { _SOC_PARITY_TYPE_PARITY, NULL, 1080 SR_PORT_COUNT_RX_TAG_ERROR_PAR_ERRf, SR_PORT_COUNT_RX_TAG_ERROR_PAR_ERRf, 1081 SR_PORT_COUNT_RX_TAG_ERRORm, NULL, 1082 SR_PORT_COUNT_RX_TAG_ERROR_PARITY_CONTROLr, PARITY_ENf, NULL, 1083 INVALIDr, INVALIDf, NULL, 1084 SR_PORT_COUNT_RX_TAG_ERROR_PARITY_STATUSr, NULL, INVALIDf, 1085 INVALIDr, INVALIDf, 1086 INVALIDr, NULL, INVALIDr, INVALIDr, 1087 0 1088 }, 1089 { _SOC_PARITY_TYPE_PARITY, NULL, 1090 SR_PORT_COUNT_RX_DUPLICATES_PAR_ERRf, SR_PORT_COUNT_RX_DUPLICATES_PAR_ERRf, 1091 SR_PORT_COUNT_RX_DUPLICATESm, NULL, 1092 SR_PORT_COUNT_RX_DUPLICATES_PARITY_CONTROLr, PARITY_ENf, NULL, 1093 INVALIDr, INVALIDf, NULL, 1094 SR_PORT_COUNT_RX_DUPLICATES_PARITY_STATUSr, NULL, INVALIDf, 1095 INVALIDr, INVALIDf, 1096 INVALIDr, NULL, INVALIDr, INVALIDr, 1097 0 1098 }, 1099 { _SOC_PARITY_TYPE_PARITY, NULL, 1100 SR_PORT_COUNT_RX_OUTOFORDER_PAR_ERRf, SR_PORT_COUNT_RX_OUTOFORDER_PAR_ERRf, 1101 SR_PORT_COUNT_RX_OUTOFORDERm, NULL, 1102 SR_PORT_COUNT_RX_OUTOFORDER_PARITY_CONTROLr, PARITY_ENf, NULL, 1103 INVALIDr, INVALIDf, NULL, 1104 SR_PORT_COUNT_RX_OUTOFORDER_PARITY_STATUSr, NULL, INVALIDf, 1105 INVALIDr, INVALIDf, 1106 INVALIDr, NULL, INVALIDr, INVALIDr, 1107 0 1108 }, 1109 { _SOC_PARITY_TYPE_PARITY, NULL, 1110 SR_PORT_COUNT_OWN_RX_PAR_ERRf, SR_PORT_COUNT_OWN_RX_PAR_ERRf, 1111 SR_PORT_COUNT_OWN_RXm, NULL, 1112 SR_PORT_COUNT_OWN_RX_PARITY_CONTROLr, PARITY_ENf, NULL, 1113 INVALIDr, INVALIDf, NULL, 1114 SR_PORT_COUNT_OWN_RX_PARITY_STATUSr, NULL, INVALIDf, 1115 INVALIDr, INVALIDf, 1116 INVALIDr, NULL, INVALIDr, INVALIDr, 1117 0 1118 }, 1119 { _SOC_PARITY_TYPE_PARITY, NULL, 1120 SR_PORT_COUNT_UNEXPECTED_FRAME_PAR_ERRf, SR_PORT_COUNT_UNEXPECTED_FRAME_PAR_ERRf, 1121 SR_PORT_COUNT_UNEXPECTED_FRAMEm, NULL, 1122 SR_PORT_COUNT_UNEXPECTED_FRAME_PARITY_CONTROLr, PARITY_ENf, NULL, 1123 INVALIDr, INVALIDf, NULL, 1124 SR_PORT_COUNT_UNEXPECTED_FRAME_PARITY_STATUSr, NULL, INVALIDf, 1125 INVALIDr, INVALIDf, 1126 INVALIDr, NULL, INVALIDr, INVALIDr, 1127 0 1128 }, 1129 { _SOC_PARITY_TYPE_PARITY, NULL, 1130 SR_PORT_MTU_ERROR_PAR_ERRf, SR_PORT_MTU_ERROR_PAR_ERRf, 1131 SR_PORT_MTU_ERRORm, NULL, 1132 SR_PORT_MTU_ERROR_PARITY_CONTROLr, PARITY_ENf, NULL, 1133 INVALIDr, INVALIDf, NULL, 1134 SR_PORT_MTU_ERROR_PARITY_STATUSr, NULL, INVALIDf, 1135 INVALIDr, INVALIDf, 1136 INVALIDr, NULL, INVALIDr, INVALIDr, 1137 0 1138 }, 1139 { _SOC_PARITY_TYPE_PARITY, NULL, 1140 SR_PORT_STU_ERROR_PAR_ERRf, SR_PORT_STU_ERROR_PAR_ERRf, 1141 SR_PORT_STU_ERRORm, NULL, 1142 SR_PORT_STU_ERROR_PARITY_CONTROLr, PARITY_ENf, NULL, 1143 INVALIDr, INVALIDf, NULL, 1144 SR_PORT_STU_ERROR_PARITY_STATUSr, NULL, INVALIDf, 1145 INVALIDr, INVALIDf, 1146 INVALIDr, NULL, INVALIDr, INVALIDr, 1147 0 1148 }, 1149 { _SOC_PARITY_TYPE_PARITY, NULL, 1150 SR_PORT_PROXY_MAC_ERROR_PAR_ERRf, SR_PORT_PROXY_MAC_ERROR_PAR_ERRf, 1151 SR_PORT_PROXY_MAC_ERRORm, NULL, 1152 SR_PORT_PROXY_MAC_ERROR_PARITY_CONTROLr, PARITY_ENf, NULL, 1153 INVALIDr, INVALIDf, NULL, 1154 SR_PORT_PROXY_MAC_ERROR_PARITY_STATUSr, NULL, INVALIDf, 1155 INVALIDr, INVALIDf, 1156 INVALIDr, NULL, INVALIDr, INVALIDr, 1157 0 1158 }, 1159 { _SOC_PARITY_TYPE_PARITY, NULL, 1160 SR_PORT_SN_WINDOW_RESET_PAR_ERRf, SR_PORT_SN_WINDOW_RESET_PAR_ERRf, 1161 SR_PORT_SN_WINDOW_RESETm, NULL, 1162 SR_PORT_SN_WINDOW_RESET_PARITY_CONTROLr, PARITY_ENf, NULL, 1163 INVALIDr, INVALIDf, NULL, 1164 SR_PORT_SN_WINDOW_RESET_PARITY_STATUSr, NULL, INVALIDf, 1165 INVALIDr, INVALIDf, 1166 INVALIDr, NULL, INVALIDr, INVALIDr, 1167 0 1168 }, 1169 { _SOC_PARITY_TYPE_PARITY, NULL, 1170 SR_PORT_COUNT_RX_PASSED_PAR_ERRf, SR_PORT_COUNT_RX_PASSED_PAR_ERRf, 1171 SR_PORT_COUNT_RX_PASSEDm, NULL, 1172 SR_PORT_COUNT_RX_PASSED_PARITY_CONTROLr, PARITY_ENf, NULL, 1173 INVALIDr, INVALIDf, NULL, 1174 SR_PORT_COUNT_RX_PASSED_PARITY_STATUSr, NULL, INVALIDf, 1175 INVALIDr, INVALIDf, 1176 INVALIDr, NULL, INVALIDr, INVALIDr, 1177 0 1178 }, 1179 /* TAF_GATE_ID_LOOKUPm is 2 bit ECC (ECC_ERRf = 1) */ 1180 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 1181 TAF_GATE_ID_LOOKUP_ECC_2B_ERRORf, TAF_GATE_ID_LOOKUP_ECC_2B_ERRORf, 1182 TAF_GATE_ID_LOOKUPm, "TAF_GATE_ID_LOOKUP 2 bit ECC", 1183 TAF_GATE_ID_LOOKUP_ECC_CONTROLr, ECC_ENf, NULL, 1184 INVALIDr, INVALIDf, NULL, 1185 TAF_GATE_ID_LOOKUP_ECC_STATUS_INTRr, NULL, ECC_ERRf, 1186 INVALIDr, INVALIDf, 1187 INVALIDr, NULL, INVALIDr, INVALIDr, 1188 _SOC_SER_SKIP_GH2_A0 1189 }, 1190 #endif /* _GH2_SER_TEST_IP2_SR */ 1191 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1192 }; 1193 1194 static _soc_gh2_ser_info_t _soc_gh2_ip2_sr_sn_ser_info[] = { 1195 #if _GH2_SER_TEST_IP2_SR_SN 1196 /* ING_MTU_CHECK_1m is 2 bit ECC (ECC_ERRf = 1) */ 1197 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 1198 IFP_MTU_CHECK_1_ECC_ERRORf, IFP_MTU_CHECK_1_ECC_ERRORf, 1199 ING_MTU_CHECK_1m, NULL, 1200 IFP_MTU_CHECK_1_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1201 INVALIDr, INVALIDf, NULL, 1202 IFP_MTU_CHECK_1_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 1203 INVALIDr, INVALIDf, 1204 INVALIDr, NULL, INVALIDr, INVALIDr, 1205 _SOC_SER_SKIP_GH2_A0 1206 }, 1207 { _SOC_PARITY_TYPE_ECC, NULL, 1208 IFP_MTU_CHECK_1_PARITY_ERRORf, IFP_MTU_CHECK_1_PARITY_ERRORf, 1209 INVALIDm, NULL, 1210 IFP_MTU_CHECK_1_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1211 INVALIDr, INVALIDf, NULL, 1212 IFP_MTU_CHECK_1_TABLE_PARITY_STATUS_INTRr, NULL, INVALIDf, 1213 INVALIDr, INVALIDf, 1214 INVALIDr, NULL, INVALIDr, INVALIDr, 1215 _SOC_SER_SKIP_GH2_A0 1216 }, 1217 /* ING_MTU_CHECK_2m is 2 bit ECC (ECC_ERRf = 1) */ 1218 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 1219 IFP_MTU_CHECK_2_ECC_ERRORf, IFP_MTU_CHECK_2_ECC_ERRORf, 1220 ING_MTU_CHECK_2m, NULL, 1221 IFP_MTU_CHECK_2_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1222 INVALIDr, INVALIDf, NULL, 1223 IFP_MTU_CHECK_2_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 1224 INVALIDr, INVALIDf, 1225 INVALIDr, NULL, INVALIDr, INVALIDr, 1226 _SOC_SER_SKIP_GH2_A0 1227 }, 1228 { _SOC_PARITY_TYPE_ECC, NULL, 1229 IFP_MTU_CHECK_2_PARITY_ERRORf, IFP_MTU_CHECK_2_PARITY_ERRORf, 1230 INVALIDm, NULL, 1231 IFP_MTU_CHECK_2_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1232 INVALIDr, INVALIDf, NULL, 1233 IFP_MTU_CHECK_2_TABLE_PARITY_STATUS_INTRr, NULL, INVALIDf, 1234 INVALIDr, INVALIDf, 1235 INVALIDr, NULL, INVALIDr, INVALIDr, 1236 _SOC_SER_SKIP_GH2_A0 1237 }, 1238 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 1239 IFP_SR_TX_ECC_ERRORf, IFP_SR_TX_ECC_ERRORf, 1240 SR_TXm, NULL, 1241 IFP_SR_TX_ECC_CONTROLr, ECC_ENf, NULL, 1242 INVALIDr, INVALIDf, NULL, 1243 IFP_SR_TX_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 1244 INVALIDr, INVALIDf, 1245 INVALIDr, NULL, INVALIDr, INVALIDr, 1246 _SOC_SER_SKIP_GH2_A0 1247 }, 1248 { _SOC_PARITY_TYPE_ECC, NULL, 1249 IFP_SR_TX_PARITY_ERRORf, IFP_SR_TX_PARITY_ERRORf, 1250 INVALIDm, NULL, 1251 IFP_SR_TX_ECC_CONTROLr, ECC_ENf, NULL, 1252 INVALIDr, INVALIDf, NULL, 1253 IFP_SR_TX_TABLE_PARITY_STATUS_INTRr, NULL, INVALIDf, 1254 INVALIDr, INVALIDf, 1255 INVALIDr, NULL, INVALIDr, INVALIDr, 1256 _SOC_SER_SKIP_GH2_A0 1257 }, 1258 { _SOC_PARITY_TYPE_ECC, NULL, 1259 IFP_SN_HISTORY_0_ECC_ERRORf, IFP_SN_HISTORY_0_ECC_ERRORf, 1260 INVALIDm, NULL, 1261 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1262 INVALIDr, INVALIDf, NULL, 1263 IFP_SN_HISTORY_0_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1264 INVALIDr, INVALIDf, 1265 INVALIDr, NULL, INVALIDr, INVALIDr, 1266 _SOC_SER_SKIP_GH2_A0 1267 }, 1268 { _SOC_PARITY_TYPE_ECC, NULL, 1269 IFP_SN_HISTORY_1_ECC_ERRORf, IFP_SN_HISTORY_1_ECC_ERRORf, 1270 INVALIDm, NULL, 1271 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1272 INVALIDr, INVALIDf, NULL, 1273 IFP_SN_HISTORY_1_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1274 INVALIDr, INVALIDf, 1275 INVALIDr, NULL, INVALIDr, INVALIDr, 1276 _SOC_SER_SKIP_GH2_A0 1277 }, 1278 { _SOC_PARITY_TYPE_ECC, NULL, 1279 IFP_SN_HISTORY_2_ECC_ERRORf, IFP_SN_HISTORY_2_ECC_ERRORf, 1280 INVALIDm, NULL, 1281 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1282 INVALIDr, INVALIDf, NULL, 1283 IFP_SN_HISTORY_2_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1284 INVALIDr, INVALIDf, 1285 INVALIDr, NULL, INVALIDr, INVALIDr, 1286 _SOC_SER_SKIP_GH2_A0 1287 }, 1288 { _SOC_PARITY_TYPE_ECC, NULL, 1289 IFP_SN_HISTORY_3_ECC_ERRORf, IFP_SN_HISTORY_3_ECC_ERRORf, 1290 INVALIDm, NULL, 1291 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1292 INVALIDr, INVALIDf, NULL, 1293 IFP_SN_HISTORY_3_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1294 INVALIDr, INVALIDf, 1295 INVALIDr, NULL, INVALIDr, INVALIDr, 1296 _SOC_SER_SKIP_GH2_A0 1297 }, 1298 { _SOC_PARITY_TYPE_ECC, NULL, 1299 IFP_SN_HISTORY_4_ECC_ERRORf, IFP_SN_HISTORY_4_ECC_ERRORf, 1300 INVALIDm, NULL, 1301 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1302 INVALIDr, INVALIDf, NULL, 1303 IFP_SN_HISTORY_4_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1304 INVALIDr, INVALIDf, 1305 INVALIDr, NULL, INVALIDr, INVALIDr, 1306 _SOC_SER_SKIP_GH2_A0 1307 }, 1308 { _SOC_PARITY_TYPE_ECC, NULL, 1309 IFP_SN_HISTORY_5_ECC_ERRORf, IFP_SN_HISTORY_5_ECC_ERRORf, 1310 INVALIDm, NULL, 1311 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1312 INVALIDr, INVALIDf, NULL, 1313 IFP_SN_HISTORY_5_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1314 INVALIDr, INVALIDf, 1315 INVALIDr, NULL, INVALIDr, INVALIDr, 1316 _SOC_SER_SKIP_GH2_A0 1317 }, 1318 { _SOC_PARITY_TYPE_ECC, NULL, 1319 IFP_SN_HISTORY_6_ECC_ERRORf, IFP_SN_HISTORY_6_ECC_ERRORf, 1320 INVALIDm, NULL, 1321 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1322 INVALIDr, INVALIDf, NULL, 1323 IFP_SN_HISTORY_6_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1324 INVALIDr, INVALIDf, 1325 INVALIDr, NULL, INVALIDr, INVALIDr, 1326 _SOC_SER_SKIP_GH2_A0 1327 }, 1328 { _SOC_PARITY_TYPE_ECC, NULL, 1329 IFP_SN_HISTORY_7_ECC_ERRORf, IFP_SN_HISTORY_7_ECC_ERRORf, 1330 INVALIDm, NULL, 1331 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1332 INVALIDr, INVALIDf, NULL, 1333 IFP_SN_HISTORY_7_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1334 INVALIDr, INVALIDf, 1335 INVALIDr, NULL, INVALIDr, INVALIDr, 1336 _SOC_SER_SKIP_GH2_A0 1337 }, 1338 { _SOC_PARITY_TYPE_ECC, NULL, 1339 IFP_SN_HISTORY_8_ECC_ERRORf, IFP_SN_HISTORY_8_ECC_ERRORf, 1340 INVALIDm, NULL, 1341 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1342 INVALIDr, INVALIDf, NULL, 1343 IFP_SN_HISTORY_8_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1344 INVALIDr, INVALIDf, 1345 INVALIDr, NULL, INVALIDr, INVALIDr, 1346 _SOC_SER_SKIP_GH2_A0 1347 }, 1348 { _SOC_PARITY_TYPE_ECC, NULL, 1349 IFP_SN_HISTORY_9_ECC_ERRORf, IFP_SN_HISTORY_9_ECC_ERRORf, 1350 INVALIDm, NULL, 1351 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1352 INVALIDr, INVALIDf, NULL, 1353 IFP_SN_HISTORY_9_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1354 INVALIDr, INVALIDf, 1355 INVALIDr, NULL, INVALIDr, INVALIDr, 1356 _SOC_SER_SKIP_GH2_A0 1357 }, 1358 { _SOC_PARITY_TYPE_ECC, NULL, 1359 IFP_SN_HISTORY_10_ECC_ERRORf, IFP_SN_HISTORY_10_ECC_ERRORf, 1360 INVALIDm, NULL, 1361 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1362 INVALIDr, INVALIDf, NULL, 1363 IFP_SN_HISTORY_10_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1364 INVALIDr, INVALIDf, 1365 INVALIDr, NULL, INVALIDr, INVALIDr, 1366 _SOC_SER_SKIP_GH2_A0 1367 }, 1368 { _SOC_PARITY_TYPE_ECC, NULL, 1369 IFP_SN_HISTORY_11_ECC_ERRORf, IFP_SN_HISTORY_11_ECC_ERRORf, 1370 INVALIDm, NULL, 1371 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1372 INVALIDr, INVALIDf, NULL, 1373 IFP_SN_HISTORY_11_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1374 INVALIDr, INVALIDf, 1375 INVALIDr, NULL, INVALIDr, INVALIDr, 1376 _SOC_SER_SKIP_GH2_A0 1377 }, 1378 { _SOC_PARITY_TYPE_ECC, NULL, 1379 IFP_SN_HISTORY_12_ECC_ERRORf, IFP_SN_HISTORY_12_ECC_ERRORf, 1380 INVALIDm, NULL, 1381 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1382 INVALIDr, INVALIDf, NULL, 1383 IFP_SN_HISTORY_12_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1384 INVALIDr, INVALIDf, 1385 INVALIDr, NULL, INVALIDr, INVALIDr, 1386 _SOC_SER_SKIP_GH2_A0 1387 }, 1388 { _SOC_PARITY_TYPE_ECC, NULL, 1389 IFP_SN_HISTORY_13_ECC_ERRORf, IFP_SN_HISTORY_13_ECC_ERRORf, 1390 INVALIDm, NULL, 1391 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1392 INVALIDr, INVALIDf, NULL, 1393 IFP_SN_HISTORY_13_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1394 INVALIDr, INVALIDf, 1395 INVALIDr, NULL, INVALIDr, INVALIDr, 1396 _SOC_SER_SKIP_GH2_A0 1397 }, 1398 { _SOC_PARITY_TYPE_ECC, NULL, 1399 IFP_SN_HISTORY_14_ECC_ERRORf, IFP_SN_HISTORY_14_ECC_ERRORf, 1400 INVALIDm, NULL, 1401 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1402 INVALIDr, INVALIDf, NULL, 1403 IFP_SN_HISTORY_14_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1404 INVALIDr, INVALIDf, 1405 INVALIDr, NULL, INVALIDr, INVALIDr, 1406 _SOC_SER_SKIP_GH2_A0 1407 }, 1408 { _SOC_PARITY_TYPE_ECC, NULL, 1409 IFP_SN_HISTORY_15_ECC_ERRORf, IFP_SN_HISTORY_15_ECC_ERRORf, 1410 INVALIDm, NULL, 1411 IFP_SR_RX_HISTORY_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 1412 INVALIDr, INVALIDf, NULL, 1413 IFP_SN_HISTORY_15_TABLE_ECC_STATUS_INTRr, NULL, INVALIDf, 1414 INVALIDr, INVALIDf, 1415 INVALIDr, NULL, INVALIDr, INVALIDr, 1416 _SOC_SER_SKIP_GH2_A0 1417 }, 1418 { _SOC_PARITY_TYPE_PARITY, NULL, 1419 IFP_SVM_METER_PARITY_ERRORf, IFP_SVM_METER_PARITY_ERRORf, 1420 SVM_METER_TABLEm, NULL, 1421 IFP_SVM_METER_PARITY_CONTROLr, PARITY_ENf, NULL, 1422 INVALIDr, INVALIDf, NULL, 1423 IFP_SVM_METER_PARITY_STATUSr, NULL, PARITY_ERRf, 1424 INVALIDr, INVALIDf, 1425 INVALIDr, NULL, INVALIDr, INVALIDr, 1426 _SOC_SER_SKIP_GH2_A0 1427 }, 1428 { _SOC_PARITY_TYPE_PARITY, NULL, 1429 IFP_SVM_POLICY_PARITY_ERRORf, IFP_SVM_POLICY_PARITY_ERRORf, 1430 SVM_POLICY_TABLEm, NULL, 1431 IFP_SVM_POLICY_PARITY_CONTROLr, PARITY_ENf, NULL, 1432 INVALIDr, INVALIDf, NULL, 1433 IFP_SVM_POLICY_PARITY_STATUSr, NULL, PARITY_ERRf, 1434 INVALIDr, INVALIDf, 1435 INVALIDr, NULL, INVALIDr, INVALIDr, 1436 _SOC_SER_SKIP_GH2_A0 1437 }, 1438 #endif /* _GH2_SER_TEST_IP2_SR_SN */ 1439 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1440 }; 1441 1442 static _soc_gh2_ser_info_t _soc_gh2_ep_ser_info[] = { 1443 #if _GH2_SER_TEST_EP 1444 { _SOC_PARITY_TYPE_PARITY, NULL, 1445 EGR_EFP_POLICY_TABLE_PAR_ERRf, EGR_EFP_POLICY_TABLE_PAR_ERRf, 1446 EFP_POLICY_TABLEm, NULL, 1447 EFP_POLICY_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 1448 INVALIDr, INVALIDf, NULL, 1449 EFP_POLICY_TABLE_PARITY_STATUSr, NULL, INVALIDf, 1450 INVALIDr, INVALIDf, 1451 INVALIDr, NULL, INVALIDr, INVALIDr, 1452 0 1453 }, 1454 { _SOC_PARITY_TYPE_PARITY, NULL, 1455 EGR_EFP_METER_TABLE_PAR_ERRf, EGR_EFP_METER_TABLE_PAR_ERRf, 1456 EFP_METER_TABLEm, NULL, 1457 EFP_METER_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 1458 INVALIDr, INVALIDf, NULL, 1459 EFP_METER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 1460 INVALIDr, INVALIDf, 1461 INVALIDr, NULL, INVALIDr, INVALIDr, 1462 0 1463 }, 1464 { _SOC_PARITY_TYPE_PARITY, NULL, 1465 EGR_MOD_MAP_PAR_ERRf, EGR_MOD_MAP_PAR_ERRf, 1466 EGR_MOD_MAP_TABLEm, NULL, 1467 EGR_EHCPM_PARITY_CONTROLr, EGR_MOD_MAPf, NULL, 1468 INVALIDr, INVALIDf, NULL, 1469 EGR_MOD_MAP_PARITY_STATUSr, NULL, INVALIDf, 1470 INVALIDr, INVALIDf, 1471 INVALIDr, NULL, INVALIDr, INVALIDr, 1472 0 1473 }, 1474 { _SOC_PARITY_TYPE_PARITY, NULL, 1475 EFP_COUNTER_TABLE_PAR_ERRf, EFP_COUNTER_TABLE_PAR_ERRf, 1476 EFP_COUNTER_TABLEm, NULL, 1477 EGR_EDATABUF_PARITY_CONTROL_64r, EFP_COUNTER_TABLEf, NULL, 1478 INVALIDr, INVALIDf, NULL, 1479 EFP_COUNTER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 1480 INVALIDr, INVALIDf, 1481 INVALIDr, NULL, INVALIDr, INVALIDr, 1482 0 1483 }, 1484 { _SOC_PARITY_TYPE_PARITY, NULL, 1485 EGR_PERQ_XMT_COUNTERS_PAR_ERRf, EGR_PERQ_XMT_COUNTERS_PAR_ERRf, 1486 EGR_PERQ_XMT_COUNTERSm, NULL, 1487 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_PERQ_XMT_COUNTERSf, NULL, 1488 INVALIDr, INVALIDf, NULL, 1489 EGR_PERQ_XMT_COUNTERS_PARITY_STATUSr, NULL, INVALIDf, 1490 INVALIDr, INVALIDf, 1491 INVALIDr, NULL, INVALIDr, INVALIDr, 1492 0 1493 }, 1494 { _SOC_PARITY_TYPE_PARITY, NULL, 1495 EGR_PER_Q_ECN_MARKED_PAR_ERRf, EGR_PER_Q_ECN_MARKED_PAR_ERRf, 1496 EGR_PER_Q_ECN_MARKEDm, NULL, 1497 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_PER_Q_ECN_MARKEDf, NULL, 1498 INVALIDr, INVALIDf, NULL, 1499 EGR_PER_Q_ECN_MARKED_PARITY_STATUSr, NULL, INVALIDf, 1500 INVALIDr, INVALIDf, 1501 INVALIDr, NULL, INVALIDr, INVALIDr, 1502 0 1503 }, 1504 { _SOC_PARITY_TYPE_PARITY, NULL, 1505 EGR_VLAN_COUNTER_TABLE_PAR_ERRf, EGR_VLAN_COUNTER_TABLE_PAR_ERRf, 1506 EGR_VLAN_COUNTER_TABLEm, NULL, 1507 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_VLAN_COUNTER_TABLEf, NULL, 1508 INVALIDr, INVALIDf, NULL, 1509 EGR_VLAN_COUNTER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 1510 INVALIDr, INVALIDf, 1511 INVALIDr, NULL, INVALIDr, INVALIDr, 1512 0 1513 }, 1514 { _SOC_PARITY_TYPE_PARITY, NULL, 1515 EGR_ECN_COUNTER_PAR_ERRf, EGR_ECN_COUNTER_PAR_ERRf, 1516 EGR_ECN_COUNTERm, NULL, 1517 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_ECN_COUNTERf, NULL, 1518 INVALIDr, INVALIDf, NULL, 1519 EGR_ECN_COUNTER_PARITY_STATUSr, NULL, INVALIDf, 1520 INVALIDr, INVALIDf, 1521 INVALIDr, NULL, INVALIDr, INVALIDr, 1522 0 1523 }, 1524 /* SR_FLOW_EGR_COUNTER_CONTROLm is 2 bit ECC (PARITY_ERRf = 1) */ 1525 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 1526 SR_FLOW_EGR_COUNTER_CONTROL_PAR_ERRf, SR_FLOW_EGR_COUNTER_CONTROL_PAR_ERRf, 1527 SR_FLOW_EGR_COUNTER_CONTROLm, NULL, 1528 EGR_EDATABUF_PARITY_CONTROL_64r, SR_FLOW_EGR_COUNTER_CONTROLf, NULL, 1529 INVALIDr, INVALIDf, NULL, 1530 SR_FLOW_EGR_COUNTER_CONTROL_PARITY_STATUSr, NULL, PARITY_ERRf, 1531 INVALIDr, INVALIDf, 1532 INVALIDr, NULL, INVALIDr, INVALIDr, 1533 0 1534 }, 1535 { _SOC_PARITY_TYPE_PARITY, NULL, 1536 SR_PORT_COUNT_TX_TAGGED_PAR_ERRf, SR_PORT_COUNT_TX_TAGGED_PAR_ERRf, 1537 SR_PORT_COUNT_TX_TAGGEDm, NULL, 1538 EGR_EDATABUF_PARITY_CONTROL_64r, SR_PORT_COUNT_TX_TAGGEDf, NULL, 1539 INVALIDr, INVALIDf, NULL, 1540 SR_PORT_COUNT_TX_TAGGED_PARITY_STATUSr, NULL, INVALIDf, 1541 INVALIDr, INVALIDf, 1542 INVALIDr, NULL, INVALIDr, INVALIDr, 1543 0 1544 }, 1545 { _SOC_PARITY_TYPE_PARITY, NULL, 1546 SR_PORT_COUNT_TX_PAR_ERRf, SR_PORT_COUNT_TX_PAR_ERRf, 1547 SR_PORT_COUNT_TXm, NULL, 1548 EGR_EDATABUF_PARITY_CONTROL_64r, SR_PORT_COUNT_TXf, NULL, 1549 INVALIDr, INVALIDf, NULL, 1550 SR_PORT_COUNT_TX_PARITY_STATUSr, NULL, INVALIDf, 1551 INVALIDr, INVALIDf, 1552 INVALIDr, NULL, INVALIDr, INVALIDr, 1553 0 1554 }, 1555 { _SOC_PARITY_TYPE_PARITY, NULL, 1556 SR_PORT_TX_MTU_ERROR_PAR_ERRf, SR_PORT_TX_MTU_ERROR_PAR_ERRf, 1557 SR_PORT_TX_MTU_ERRORm, NULL, 1558 EGR_EDATABUF_PARITY_CONTROL_64r, SR_PORT_TX_MTU_ERRORf, NULL, 1559 INVALIDr, INVALIDf, NULL, 1560 SR_PORT_TX_MTU_ERROR_PARITY_STATUSr, NULL, INVALIDf, 1561 INVALIDr, INVALIDf, 1562 INVALIDr, NULL, INVALIDr, INVALIDr, 1563 0 1564 }, 1565 { _SOC_PARITY_TYPE_PARITY, NULL, 1566 SR_PORT_TX_STU_ERROR_PAR_ERRf, SR_PORT_TX_STU_ERROR_PAR_ERRf, 1567 SR_PORT_TX_STU_ERRORm, NULL, 1568 EGR_EDATABUF_PARITY_CONTROL_64r, SR_PORT_TX_STU_ERRORf, NULL, 1569 INVALIDr, INVALIDf, NULL, 1570 SR_PORT_TX_STU_ERROR_PARITY_STATUSr, NULL, INVALIDf, 1571 INVALIDr, INVALIDf, 1572 INVALIDr, NULL, INVALIDr, INVALIDr, 1573 0 1574 }, 1575 { _SOC_PARITY_TYPE_PARITY, NULL, 1576 EGR_SR_FLOW_COUNT_POOL0_PAR_ERRf, EGR_SR_FLOW_COUNT_POOL0_PAR_ERRf, 1577 EGR_SR_FLOW_COUNT_POOL0m, NULL, 1578 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_SR_FLOW_COUNT_POOL0f, NULL, 1579 INVALIDr, INVALIDf, NULL, 1580 EGR_SR_FLOW_COUNT_POOL0_PARITY_STATUSr, NULL, INVALIDf, 1581 INVALIDr, INVALIDf, 1582 INVALIDr, NULL, INVALIDr, INVALIDr, 1583 0 1584 }, 1585 { _SOC_PARITY_TYPE_PARITY, NULL, 1586 EGR_SR_FLOW_COUNT_POOL1_PAR_ERRf, EGR_SR_FLOW_COUNT_POOL1_PAR_ERRf, 1587 EGR_SR_FLOW_COUNT_POOL1m, NULL, 1588 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_SR_FLOW_COUNT_POOL1f, NULL, 1589 INVALIDr, INVALIDf, NULL, 1590 EGR_SR_FLOW_COUNT_POOL1_PARITY_STATUSr, NULL, INVALIDf, 1591 INVALIDr, INVALIDf, 1592 INVALIDr, NULL, INVALIDr, INVALIDr, 1593 0 1594 }, 1595 { _SOC_PARITY_TYPE_PARITY, NULL, 1596 EGR_MFRAME_COUNTER_PAR_ERRf, EGR_MFRAME_COUNTER_PAR_ERRf, 1597 INVALIDm, NULL, 1598 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_MFRAME_COUNTERf, NULL, 1599 INVALIDr, INVALIDf, NULL, 1600 EGR_MFRAME_COUNTER_PARITY_STATUSr, NULL, INVALIDf, 1601 INVALIDr, INVALIDf, 1602 INVALIDr, NULL, INVALIDr, INVALIDr, 1603 0 1604 }, 1605 { _SOC_PARITY_TYPE_COUNTER, NULL, 1606 EGR_STATS_COUNTER_TABLE_PAR_ERRf, EGR_STATS_COUNTER_TABLE_PAR_ERRf, 1607 INVALIDm, "TDBGC0-TDBGC11", 1608 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_STATS_COUNTER_TABLEf, NULL, 1609 INVALIDr, INVALIDf, NULL, 1610 EGR_STATS_COUNTER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 1611 INVALIDr, INVALIDf, 1612 INVALIDr, NULL, INVALIDr, INVALIDr, 1613 0 1614 }, 1615 { _SOC_PARITY_TYPE_PARITY, NULL, 1616 EGR_RESI0_PAR_ERRf, EGR_RESI0_PAR_ERRf, 1617 INVALIDm, NULL, 1618 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_RESI0f, NULL, 1619 INVALIDr, INVALIDf, NULL, 1620 EGR_RESI0_PARITY_STATUSr, NULL, INVALIDf, 1621 INVALIDr, INVALIDf, 1622 INVALIDr, NULL, INVALIDr, INVALIDr, 1623 0 1624 }, 1625 { _SOC_PARITY_TYPE_PARITY, NULL, 1626 EGR_RESI23_PAR_ERRf, EGR_RESI23_PAR_ERRf, 1627 INVALIDm, NULL, 1628 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_RESI23f, NULL, 1629 INVALIDr, INVALIDf, NULL, 1630 EGR_RESI23_PARITY_STATUSr, NULL, INVALIDf, 1631 INVALIDr, INVALIDf, 1632 INVALIDr, NULL, INVALIDr, INVALIDr, 1633 0 1634 }, 1635 { _SOC_PARITY_TYPE_PARITY, NULL, 1636 EGR_CM_PAR_ERRf, EGR_CM_PAR_ERRf, 1637 INVALIDm, NULL, 1638 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_CMf, NULL, 1639 INVALIDr, INVALIDf, NULL, 1640 EGR_CM_PARITY_STATUSr, NULL, INVALIDf, 1641 INVALIDr, INVALIDf, 1642 INVALIDr, NULL, INVALIDr, INVALIDr, 1643 0 1644 }, 1645 { _SOC_PARITY_TYPE_PARITY, NULL, 1646 EGR_GE0_PAR_ERRf, EGR_GE0_PAR_ERRf, 1647 INVALIDm, "EP_EDB_GE0_MEM", 1648 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_GE0f, NULL, 1649 INVALIDr, INVALIDf, NULL, 1650 EGR_GE0_PARITY_STATUSr, NULL, INVALIDf, 1651 INVALIDr, INVALIDf, 1652 INVALIDr, NULL, INVALIDr, INVALIDr, 1653 0 1654 }, 1655 { _SOC_PARITY_TYPE_PARITY, NULL, 1656 EGR_GE1_PAR_ERRf, EGR_GE1_PAR_ERRf, 1657 INVALIDm, "EP_EDB_GE1_MEM", 1658 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_GE1f, NULL, 1659 INVALIDr, INVALIDf, NULL, 1660 EGR_GE1_PARITY_STATUSr, NULL, INVALIDf, 1661 INVALIDr, INVALIDf, 1662 INVALIDr, NULL, INVALIDr, INVALIDr, 1663 0 1664 }, 1665 { _SOC_PARITY_TYPE_PARITY, NULL, 1666 EGR_GE2_PAR_ERRf, EGR_GE2_PAR_ERRf, 1667 INVALIDm, "EP_EDB_GE2_MEM", 1668 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_GE2f, NULL, 1669 INVALIDr, INVALIDf, NULL, 1670 EGR_GE2_PARITY_STATUSr, NULL, INVALIDf, 1671 INVALIDr, INVALIDf, 1672 INVALIDr, NULL, INVALIDr, INVALIDr, 1673 0 1674 }, 1675 { _SOC_PARITY_TYPE_PARITY, NULL, 1676 EGR_GE3_PAR_ERRf, EGR_GE3_PAR_ERRf, 1677 INVALIDm, "EP_EDB_GE3_MEM", 1678 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_GE3f, NULL, 1679 INVALIDr, INVALIDf, NULL, 1680 EGR_GE3_PARITY_STATUSr, NULL, INVALIDf, 1681 INVALIDr, INVALIDf, 1682 INVALIDr, NULL, INVALIDr, INVALIDr, 1683 0 1684 }, 1685 { _SOC_PARITY_TYPE_PARITY, NULL, 1686 EGR_GE4_PAR_ERRf, EGR_GE4_PAR_ERRf, 1687 INVALIDm, "EP_EDB_GE4_MEM", 1688 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_GE4f, NULL, 1689 INVALIDr, INVALIDf, NULL, 1690 EGR_GE4_PARITY_STATUSr, NULL, INVALIDf, 1691 INVALIDr, INVALIDf, 1692 INVALIDr, NULL, INVALIDr, INVALIDr, 1693 0 1694 }, 1695 { _SOC_PARITY_TYPE_PARITY, NULL, 1696 EGR_GE5_PAR_ERRf, EGR_GE5_PAR_ERRf, 1697 INVALIDm, "EP_EDB_GE5_MEM", 1698 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_GE5f, NULL, 1699 INVALIDr, INVALIDf, NULL, 1700 EGR_GE5_PARITY_STATUSr, NULL, INVALIDf, 1701 INVALIDr, INVALIDf, 1702 INVALIDr, NULL, INVALIDr, INVALIDr, 1703 0 1704 }, 1705 { _SOC_PARITY_TYPE_PARITY, NULL, 1706 EGR_GE6_PAR_ERRf, EGR_GE6_PAR_ERRf, 1707 INVALIDm, "EP_EDB_GE6_MEM", 1708 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_GE6f, NULL, 1709 INVALIDr, INVALIDf, NULL, 1710 EGR_GE6_PARITY_STATUSr, NULL, INVALIDf, 1711 INVALIDr, INVALIDf, 1712 INVALIDr, NULL, INVALIDr, INVALIDr, 1713 0 1714 }, 1715 { _SOC_PARITY_TYPE_PARITY, NULL, 1716 EGR_XL0_PAR_ERRf, EGR_XL0_PAR_ERRf, 1717 INVALIDm, "EP_EDB_XL0_MEM", 1718 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL0f, NULL, 1719 INVALIDr, INVALIDf, NULL, 1720 EGR_XL0_PARITY_STATUSr, NULL, INVALIDf, 1721 INVALIDr, INVALIDf, 1722 INVALIDr, NULL, INVALIDr, INVALIDr, 1723 0 1724 }, 1725 { _SOC_PARITY_TYPE_PARITY, NULL, 1726 EGR_XL1_PAR_ERRf, EGR_XL1_PAR_ERRf, 1727 INVALIDm, "EP_EDB_XL1_MEM", 1728 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL1f, NULL, 1729 INVALIDr, INVALIDf, NULL, 1730 EGR_XL1_PARITY_STATUSr, NULL, INVALIDf, 1731 INVALIDr, INVALIDf, 1732 INVALIDr, NULL, INVALIDr, INVALIDr, 1733 0 1734 }, 1735 { _SOC_PARITY_TYPE_PARITY, NULL, 1736 EGR_XL2_PAR_ERRf, EGR_XL2_PAR_ERRf, 1737 INVALIDm, "EP_EDB_XL2_MEM", 1738 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL2f, NULL, 1739 INVALIDr, INVALIDf, NULL, 1740 EGR_XL2_PARITY_STATUSr, NULL, INVALIDf, 1741 INVALIDr, INVALIDf, 1742 INVALIDr, NULL, INVALIDr, INVALIDr, 1743 0 1744 }, 1745 { _SOC_PARITY_TYPE_PARITY, NULL, 1746 EGR_XL3_PAR_ERRf, EGR_XL3_PAR_ERRf, 1747 INVALIDm, "EP_EDB_XL3_MEM", 1748 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL3f, NULL, 1749 INVALIDr, INVALIDf, NULL, 1750 EGR_XL3_PARITY_STATUSr, NULL, INVALIDf, 1751 INVALIDr, INVALIDf, 1752 INVALIDr, NULL, INVALIDr, INVALIDr, 1753 0 1754 }, 1755 { _SOC_PARITY_TYPE_PARITY, NULL, 1756 EGR_XL4_PAR_ERRf, EGR_XL4_PAR_ERRf, 1757 INVALIDm, "EP_EDB_XL4_MEM", 1758 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL4f, NULL, 1759 INVALIDr, INVALIDf, NULL, 1760 EGR_XL4_PARITY_STATUSr, NULL, INVALIDf, 1761 INVALIDr, INVALIDf, 1762 INVALIDr, NULL, INVALIDr, INVALIDr, 1763 0 1764 }, 1765 { _SOC_PARITY_TYPE_PARITY, NULL, 1766 EGR_XL5_PAR_ERRf, EGR_XL5_PAR_ERRf, 1767 INVALIDm, "EP_EDB_XL5_MEM", 1768 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL5f, NULL, 1769 INVALIDr, INVALIDf, NULL, 1770 EGR_XL5_PARITY_STATUSr, NULL, INVALIDf, 1771 INVALIDr, INVALIDf, 1772 INVALIDr, NULL, INVALIDr, INVALIDr, 1773 0 1774 }, 1775 { _SOC_PARITY_TYPE_PARITY, NULL, 1776 EGR_XL6_PAR_ERRf, EGR_XL6_PAR_ERRf, 1777 INVALIDm, "EP_EDB_XL6_MEM", 1778 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL6f, NULL, 1779 INVALIDr, INVALIDf, NULL, 1780 EGR_XL6_PARITY_STATUSr, NULL, INVALIDf, 1781 INVALIDr, INVALIDf, 1782 INVALIDr, NULL, INVALIDr, INVALIDr, 1783 0 1784 }, 1785 { _SOC_PARITY_TYPE_PARITY, NULL, 1786 EGR_XL7_PAR_ERRf, EGR_XL7_PAR_ERRf, 1787 INVALIDm, "EP_EDB_XL7_MEM", 1788 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL7f, NULL, 1789 INVALIDr, INVALIDf, NULL, 1790 EGR_XL7_PARITY_STATUSr, NULL, INVALIDf, 1791 INVALIDr, INVALIDf, 1792 INVALIDr, NULL, INVALIDr, INVALIDr, 1793 0 1794 }, 1795 { _SOC_PARITY_TYPE_PARITY, NULL, 1796 EGR_XL8_PAR_ERRf, EGR_XL8_PAR_ERRf, 1797 INVALIDm, "EP_EDB_XL8_MEM", 1798 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL8f, NULL, 1799 INVALIDr, INVALIDf, NULL, 1800 EGR_XL8_PARITY_STATUSr, NULL, INVALIDf, 1801 INVALIDr, INVALIDf, 1802 INVALIDr, NULL, INVALIDr, INVALIDr, 1803 0 1804 }, 1805 { _SOC_PARITY_TYPE_PARITY, NULL, 1806 EGR_XL9_PAR_ERRf, EGR_XL9_PAR_ERRf, 1807 INVALIDm, "EP_EDB_XL9_MEM", 1808 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL9f, NULL, 1809 INVALIDr, INVALIDf, NULL, 1810 EGR_XL9_PARITY_STATUSr, NULL, INVALIDf, 1811 INVALIDr, INVALIDf, 1812 INVALIDr, NULL, INVALIDr, INVALIDr, 1813 0 1814 }, 1815 { _SOC_PARITY_TYPE_PARITY, NULL, 1816 EGR_XL10_PAR_ERRf, EGR_XL10_PAR_ERRf, 1817 INVALIDm, "EP_EDB_XL10_MEM", 1818 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL10f, NULL, 1819 INVALIDr, INVALIDf, NULL, 1820 EGR_XL10_PARITY_STATUSr, NULL, INVALIDf, 1821 INVALIDr, INVALIDf, 1822 INVALIDr, NULL, INVALIDr, INVALIDr, 1823 0 1824 }, 1825 { _SOC_PARITY_TYPE_PARITY, NULL, 1826 EGR_XL11_PAR_ERRf, EGR_XL11_PAR_ERRf, 1827 INVALIDm, "EP_EDB_XL11_MEM", 1828 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL11f, NULL, 1829 INVALIDr, INVALIDf, NULL, 1830 EGR_XL11_PARITY_STATUSr, NULL, INVALIDf, 1831 INVALIDr, INVALIDf, 1832 INVALIDr, NULL, INVALIDr, INVALIDr, 1833 0 1834 }, 1835 { _SOC_PARITY_TYPE_PARITY, NULL, 1836 EGR_XL12_PAR_ERRf, EGR_XL12_PAR_ERRf, 1837 INVALIDm, "EP_EDB_XL12_MEM", 1838 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL12f, NULL, 1839 INVALIDr, INVALIDf, NULL, 1840 EGR_XL12_PARITY_STATUSr, NULL, INVALIDf, 1841 INVALIDr, INVALIDf, 1842 INVALIDr, NULL, INVALIDr, INVALIDr, 1843 0 1844 }, 1845 { _SOC_PARITY_TYPE_PARITY, NULL, 1846 EGR_XL13_PAR_ERRf, EGR_XL13_PAR_ERRf, 1847 INVALIDm, "EP_EDB_XL13_MEM", 1848 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_XL13f, NULL, 1849 INVALIDr, INVALIDf, NULL, 1850 EGR_XL13_PARITY_STATUSr, NULL, INVALIDf, 1851 INVALIDr, INVALIDf, 1852 INVALIDr, NULL, INVALIDr, INVALIDr, 1853 0 1854 }, 1855 { _SOC_PARITY_TYPE_PARITY, NULL, 1856 EGR_CL_PAR_ERRf, EGR_CL_PAR_ERRf, 1857 INVALIDm, "EP_EDB_CL_MEM", 1858 EGR_EDATABUF_PARITY_CONTROL_64r, EGR_CLf, NULL, 1859 INVALIDr, INVALIDf, NULL, 1860 EGR_CL_PARITY_STATUSr, NULL, INVALIDf, 1861 INVALIDr, INVALIDf, 1862 INVALIDr, NULL, INVALIDr, INVALIDr, 1863 0 1864 }, 1865 { _SOC_PARITY_TYPE_PARITY, NULL, 1866 EGR_NHOP_PAR_ERRf, EGR_NHOP_PAR_ERRf, 1867 EGR_L3_NEXT_HOPm, NULL, 1868 EGR_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, NULL, 1869 INVALIDr, INVALIDf, NULL, 1870 EGR_L3_NEXT_HOP_PARITY_STATUSr, NULL, INVALIDf, 1871 INVALIDr, INVALIDf, 1872 INVALIDr, NULL, INVALIDr, INVALIDr, 1873 0 1874 }, 1875 { _SOC_PARITY_TYPE_PARITY, NULL, 1876 EGR_L3_INTF_PAR_ERRf, EGR_L3_INTF_PAR_ERRf, 1877 EGR_L3_INTFm, NULL, 1878 EGR_L3_INTF_PARITY_CONTROLr, PARITY_ENf, NULL, 1879 INVALIDr, INVALIDf, NULL, 1880 EGR_L3_INTF_PARITY_STATUSr, NULL, INVALIDf, 1881 INVALIDr, INVALIDf, 1882 INVALIDr, NULL, INVALIDr, INVALIDr, 1883 0 1884 }, 1885 { _SOC_PARITY_TYPE_PARITY, NULL, 1886 EGR_VLAN_PAR_ERRf, EGR_VLAN_PAR_ERRf, 1887 EGR_VLANm, NULL, 1888 EGR_VLAN_PARITY_CONTROLr, PARITY_ENf, NULL, 1889 INVALIDr, INVALIDf, NULL, 1890 EGR_VLAN_PARITY_STATUSr, NULL, INVALIDf, 1891 INVALIDr, INVALIDf, 1892 INVALIDr, NULL, INVALIDr, INVALIDr, 1893 0 1894 }, 1895 { _SOC_PARITY_TYPE_PARITY, NULL, 1896 EGR_VLAN_STG_PAR_ERRf, EGR_VLAN_STG_PAR_ERRf, 1897 EGR_VLAN_STGm, NULL, 1898 EGR_VLAN_STG_PARITY_CONTROLr, PARITY_ENf, NULL, 1899 INVALIDr, INVALIDf, NULL, 1900 EGR_VLAN_STG_PARITY_STATUSr, NULL, INVALIDf, 1901 INVALIDr, INVALIDf, 1902 INVALIDr, NULL, INVALIDr, INVALIDr, 1903 0 1904 }, 1905 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 1906 EGR_VXLT_PAR_ERRf, EGR_VXLT_PAR_ERRf, 1907 EGR_VLAN_XLATEm, NULL, 1908 EGR_VLAN_XLATE_PARITY_CONTROLr, PARITY_ENf, NULL, 1909 INVALIDr, INVALIDf, NULL, 1910 INVALIDr, egr_vlan_xlate_regs, INVALIDf, 1911 INVALIDr, INVALIDf, 1912 INVALIDr, NULL, INVALIDr, INVALIDr, 1913 0 1914 }, 1915 { _SOC_PARITY_TYPE_PARITY, NULL, 1916 EGR_ETAG_PCP_DE_MAPPING_PAR_ERRf, EGR_ETAG_PCP_DE_MAPPING_PAR_ERRf, 1917 EGR_ETAG_PCP_MAPPINGm, NULL, 1918 EGR_ETAG_PCP_DE_MAPPING_PARITY_CONTROLr, PARITY_ENf, NULL, 1919 INVALIDr, INVALIDf, NULL, 1920 EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr, NULL, INVALIDf, 1921 INVALIDr, INVALIDf, 1922 INVALIDr, NULL, INVALIDr, INVALIDr, 1923 0 1924 }, 1925 { _SOC_PARITY_TYPE_PARITY, NULL, 1926 EGR_GPP_ATTRIBUTES_PAR_ERRf, EGR_GPP_ATTRIBUTES_PAR_ERRf, 1927 EGR_GPP_ATTRIBUTESm, NULL, 1928 EGR_GPP_ATTRIBUTES_PARITY_CONTROLr, PARITY_ENf, NULL, 1929 INVALIDr, INVALIDf, NULL, 1930 EGR_GPP_ATTRIBUTES_PARITY_STATUSr, NULL, INVALIDf, 1931 INVALIDr, INVALIDf, 1932 INVALIDr, NULL, INVALIDr, INVALIDr, 1933 0 1934 }, 1935 { _SOC_PARITY_TYPE_PARITY, NULL, 1936 EGR_GPP_ATTRIBUTES_MODBASE_PAR_ERRf, EGR_GPP_ATTRIBUTES_MODBASE_PAR_ERRf, 1937 EGR_GPP_ATTRIBUTES_MODBASEm, NULL, 1938 EGR_GPP_ATTRIBUTES_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 1939 INVALIDr, INVALIDf, NULL, 1940 EGR_GPP_ATTRIBUTES_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 1941 INVALIDr, INVALIDf, 1942 INVALIDr, NULL, INVALIDr, INVALIDr, 1943 0 1944 }, 1945 { _SOC_PARITY_TYPE_PARITY, NULL, 1946 EGR_HEADER_ENCAP_DATA_PAR_ERRf, EGR_HEADER_ENCAP_DATA_PAR_ERRf, 1947 EGR_HEADER_ENCAP_DATAm, NULL, 1948 EGR_HEADER_ENCAP_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 1949 INVALIDr, INVALIDf, NULL, 1950 EGR_HEADER_ENCAP_DATA_PARITY_STATUSr, NULL, INVALIDf, 1951 INVALIDr, INVALIDf, 1952 INVALIDr, NULL, INVALIDr, INVALIDr, 1953 0 1954 }, 1955 { _SOC_PARITY_TYPE_PARITY, NULL, 1956 EGR_VXLAN_HEADER_PAR_ERRf, EGR_VXLAN_HEADER_PAR_ERRf, 1957 EGR_VXLAN_HEADERm, NULL, 1958 EGR_VXLAN_HEADER_PARITY_CONTROLr, PARITY_ENf, NULL, 1959 INVALIDr, INVALIDf, NULL, 1960 EGR_VXLAN_HEADER_PARITY_STATUSr, NULL, INVALIDf, 1961 INVALIDr, INVALIDf, 1962 INVALIDr, NULL, INVALIDr, INVALIDr, 1963 0 1964 }, 1965 { _SOC_PARITY_TYPE_PARITY, NULL, 1966 EGR_IP_TUNNEL_PAR_ERRf, EGR_IP_TUNNEL_PAR_ERRf, 1967 EGR_IP_TUNNELm, NULL, 1968 EGR_IP_TUNNEL_PARITY_CONTROLr, PARITY_ENf, NULL, 1969 INVALIDr, INVALIDf, NULL, 1970 EGR_IP_TUNNEL_PARITY_STATUSr, NULL, INVALIDf, 1971 INVALIDr, INVALIDf, 1972 INVALIDr, NULL, INVALIDr, INVALIDr, 1973 _SOC_SER_SKIP_GH2_A0 1974 }, 1975 /* EGR_MTU_CHECKm is 2 bit ECC (PARITY_ERRf = 1) */ 1976 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 1977 EGR_MTU_CHECK_PAR_ERRf, EGR_MTU_CHECK_PAR_ERRf, 1978 EGR_MTU_CHECKm, NULL, 1979 EGR_MTU_CHECK_PARITY_CONTROLr, PARITY_ENf, NULL, 1980 INVALIDr, INVALIDf, NULL, 1981 EGR_MTU_CHECK_PARITY_STATUSr, NULL, PARITY_ERRf, 1982 INVALIDr, INVALIDf, 1983 INVALIDr, NULL, INVALIDr, INVALIDr, 1984 0 1985 }, 1986 /* EGR_STU_CHECKm is 2 bit ECC (PARITY_ERRf = 1) */ 1987 { _SOC_PARITY_TYPE_ECC_DUAL, NULL, 1988 EGR_STU_CHECK_PAR_ERRf, EGR_STU_CHECK_PAR_ERRf, 1989 EGR_STU_CHECKm, NULL, 1990 EGR_STU_CHECK_PARITY_CONTROLr, PARITY_ENf, NULL, 1991 INVALIDr, INVALIDf, NULL, 1992 EGR_STU_CHECK_PARITY_STATUSr, NULL, PARITY_ERRf, 1993 INVALIDr, INVALIDf, 1994 INVALIDr, NULL, INVALIDr, INVALIDr, 1995 0 1996 }, 1997 { _SOC_PARITY_TYPE_ECC, NULL, 1998 EGR_INITBUF_DBE_PAR_ERRf, EGR_INITBUF_DBE_PAR_ERRf, 1999 INVALIDm, "EGR_INITBUF Double-Bit error", 2000 EGR_INITBUF_ECC_CONTROLr, ECC_ENf, NULL, 2001 INVALIDr, INVALIDf, NULL, 2002 EGR_INITBUF_ECC_STATUS_DBEr, NULL, INVALIDf, 2003 INVALIDr, INVALIDf, 2004 INVALIDr, NULL, INVALIDr, INVALIDr, 2005 0 2006 }, 2007 #endif /* _GH2_SER_TEST_EP */ 2008 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 2009 }; 2010 #if _GH2_SER_TEST_MMU 2011 static _soc_gh2_ser_reg_t cbppkthdr_regs[] = { 2012 { CBPPKTHDR_ERRPTR0r, "CBPPKTHD[0:126]",INVALIDm}, 2013 { CBPPKTHDR_ERRPTR1r, "CBPPKTHD[127:253]",INVALIDm}, 2014 { CBPPKTHDR_ERRPTR2r, "CBPPKTHD[254:286]",INVALIDm}, 2015 { CBPPKTHDR_ERRPTR3r, "CBPPKTHD[287:322]",INVALIDm}, 2016 { INVALIDr } 2017 }; 2018 2019 static _soc_gh2_ser_reg_t gh2_soc_wred_regs[] = { 2020 { WRED_AVG_QSIZE_QG_PARITY_ERR_PTRr, "WRED AVG QSIZE QGROUP", MMU_WRED_AVG_QSIZE_QGROUPm}, 2021 { WRED_CONFIG_QG_PARITY_ERR_PTRr, "WRED CONFIG QGROUP", MMU_WRED_CONFIG_QGROUPm}, 2022 { WRED_MARK_THD_PARITY_ERR_PTRr, "WRED MARK THD", MMU_WRED_MARK_THDm}, 2023 { WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr, "WRED DROP PROFILE GREEN", MMU_WRED_DROP_PROFILE_GREENm}, 2024 { WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTRr, "WRED_DROP_PROFILE YELLOW", MMU_WRED_DROP_PROFILE_YELLOWm}, 2025 { WRED_DROP_PROFILE_RED_PARITY_ERR_PTRr, "WRED DROP PROFILE RED", MMU_WRED_DROP_PROFILE_REDm}, 2026 { WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTRr, "WRED MARK PROFILE GREEN", MMU_WRED_MARK_PROFILE_GREENm}, 2027 { WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTRr, "WRED MARK PROFILE YELLOW", MMU_WRED_MARK_PROFILE_YELLOWm}, 2028 { WRED_MARK_PROFILE_RED_PARITY_ERR_PTRr, "WRED MARK PROFILE RED", MMU_WRED_MARK_PROFILE_REDm}, 2029 { WRED_AVG_QSIZE_PARITY_ERR_PTRr, "WRED AVG QSIZE", MMU_WRED_AVG_QSIZEm}, 2030 { WRED_CONFIG_PARITY_ERR_PTRr, "WRED CONFIG", MMU_WRED_CONFIGm}, 2031 { INVALIDr } 2032 }; 2033 2034 static _soc_gh2_ser_reg_t ipmcgroup2to31_regs[] = { 2035 { IPMC_GROUP_ERR_PTRr, "", INVALIDm }, 2036 { IPMC_GROUP_ERR_PTRr, "", INVALIDm }, 2037 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP2", MMU_IPMC_GROUP_TBL2m}, 2038 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP3", MMU_IPMC_GROUP_TBL3m}, 2039 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP4", MMU_IPMC_GROUP_TBL4m}, 2040 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP5", MMU_IPMC_GROUP_TBL5m}, 2041 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP6", MMU_IPMC_GROUP_TBL6m}, 2042 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP7", MMU_IPMC_GROUP_TBL7m}, 2043 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP8", MMU_IPMC_GROUP_TBL8m}, 2044 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP9", MMU_IPMC_GROUP_TBL9m}, 2045 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP10", MMU_IPMC_GROUP_TBL10m}, 2046 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP11", MMU_IPMC_GROUP_TBL11m}, 2047 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP12", MMU_IPMC_GROUP_TBL12m}, 2048 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP13", MMU_IPMC_GROUP_TBL13m}, 2049 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP14", MMU_IPMC_GROUP_TBL14m}, 2050 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP15", MMU_IPMC_GROUP_TBL15m}, 2051 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP16", MMU_IPMC_GROUP_TBL16m}, 2052 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP17", MMU_IPMC_GROUP_TBL17m}, 2053 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP18", MMU_IPMC_GROUP_TBL18m}, 2054 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP19", MMU_IPMC_GROUP_TBL19m}, 2055 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP20", MMU_IPMC_GROUP_TBL20m}, 2056 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP21", MMU_IPMC_GROUP_TBL21m}, 2057 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP22", MMU_IPMC_GROUP_TBL22m}, 2058 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP23", MMU_IPMC_GROUP_TBL23m}, 2059 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP24", MMU_IPMC_GROUP_TBL24m}, 2060 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP25", MMU_IPMC_GROUP_TBL25m}, 2061 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP26", MMU_IPMC_GROUP_TBL26m}, 2062 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP27", MMU_IPMC_GROUP_TBL27m}, 2063 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP28", MMU_IPMC_GROUP_TBL28m}, 2064 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP29", MMU_IPMC_GROUP_TBL29m}, 2065 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP30", MMU_IPMC_GROUP_TBL30m}, 2066 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP31", MMU_IPMC_GROUP_TBL31m}, 2067 { INVALIDr } 2068 }; 2069 2070 static _soc_gh2_ser_reg_t ipmcgroup32to63_regs[] = { 2071 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP32", MMU_IPMC_GROUP_TBL32m}, 2072 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP33", MMU_IPMC_GROUP_TBL33m}, 2073 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP34", MMU_IPMC_GROUP_TBL34m}, 2074 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP35", MMU_IPMC_GROUP_TBL35m}, 2075 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP36", MMU_IPMC_GROUP_TBL36m}, 2076 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP37", MMU_IPMC_GROUP_TBL37m}, 2077 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP38", MMU_IPMC_GROUP_TBL38m}, 2078 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP39", MMU_IPMC_GROUP_TBL39m}, 2079 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP40", MMU_IPMC_GROUP_TBL40m}, 2080 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP41", MMU_IPMC_GROUP_TBL41m}, 2081 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP42", MMU_IPMC_GROUP_TBL42m}, 2082 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP43", MMU_IPMC_GROUP_TBL43m}, 2083 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP44", MMU_IPMC_GROUP_TBL44m}, 2084 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP45", MMU_IPMC_GROUP_TBL45m}, 2085 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP46", MMU_IPMC_GROUP_TBL46m}, 2086 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP47", MMU_IPMC_GROUP_TBL47m}, 2087 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP48", MMU_IPMC_GROUP_TBL48m}, 2088 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP49", MMU_IPMC_GROUP_TBL49m}, 2089 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP50", MMU_IPMC_GROUP_TBL50m}, 2090 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP51", MMU_IPMC_GROUP_TBL51m}, 2091 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP52", MMU_IPMC_GROUP_TBL52m}, 2092 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP53", MMU_IPMC_GROUP_TBL53m}, 2093 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP54", MMU_IPMC_GROUP_TBL54m}, 2094 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP55", MMU_IPMC_GROUP_TBL55m}, 2095 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP56", MMU_IPMC_GROUP_TBL56m}, 2096 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP57", MMU_IPMC_GROUP_TBL57m}, 2097 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP58", MMU_IPMC_GROUP_TBL58m}, 2098 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP59", MMU_IPMC_GROUP_TBL59m}, 2099 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP60", MMU_IPMC_GROUP_TBL60m}, 2100 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP61", MMU_IPMC_GROUP_TBL61m}, 2101 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP62", MMU_IPMC_GROUP_TBL62m}, 2102 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP63", MMU_IPMC_GROUP_TBL63m}, 2103 { INVALIDr } 2104 }; 2105 2106 static _soc_gh2_ser_reg_t ipmcgroup64to65_regs[] = { 2107 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP64", MMU_IPMC_GROUP_TBL64m}, 2108 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP65", MMU_IPMC_GROUP_TBL65m}, 2109 { INVALIDr } 2110 }; 2111 2112 static _soc_gh2_ser_reg_t ipmcgroup_vld_regs[] = { 2113 { IPMC_GROUP_ERR_VLD_0r, "", INVALIDm }, 2114 { IPMC_GROUP_ERR_VLD_1r, "", INVALIDm }, 2115 { IPMC_GROUP_ERR_VLD_2r, "", INVALIDm }, 2116 { INVALIDr } 2117 }; 2118 2119 static _soc_gh2_ser_info_t _soc_gh2_mmu_ser_info[] = { 2120 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 2121 CELLECCERRORINTMASKf, CELLECCERRORf, 2122 INVALIDm, NULL, 2123 INVALIDr, INVALIDf, NULL, 2124 INVALIDr, INVALIDf, NULL, 2125 CBPCELLERRPTRr, NULL, INVALIDf, 2126 INVALIDr ,CELLECCERROR_CLRf, 2127 INVALIDr, NULL, INVALIDr, INVALIDr, 2128 0 2129 }, 2130 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 2131 CBPCELLHDRPARITYERRORINTMASKf, CBPCELLHDRPARITYERRORf, 2132 INVALIDm, NULL, 2133 INVALIDr, INVALIDf, NULL, 2134 INVALIDr, INVALIDf, NULL, 2135 CBPCELLHDRPARITYERRPTRr, NULL, INVALIDf, 2136 INVALIDr, CBPCELLHDRPARITYERROR_CLRf, 2137 INVALIDr, NULL, INVALIDr, INVALIDr, 2138 0 2139 }, 2140 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 2141 CFAPPARITYERRORINTMASKf, CFAPPARITYERRORf, 2142 INVALIDm, NULL, 2143 INVALIDr, INVALIDf, NULL, 2144 INVALIDr, INVALIDf, NULL, 2145 CFAPPARITYERRORPTRr, NULL, INVALIDf, 2146 INVALIDr, CFAPPARITYERROR_CLRf, 2147 INVALIDr, NULL, INVALIDr, INVALIDr, 2148 0 2149 }, 2150 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 2151 CCPPARITYERRORINTMASKf, CCPPARITYERRORf, 2152 INVALIDm, NULL, 2153 INVALIDr, INVALIDf, NULL, 2154 INVALIDr, INVALIDf, NULL, 2155 CCPPARITYERRORPTRr, NULL, INVALIDf, 2156 INVALIDr, CCPPARITYERROR_CLRf, 2157 INVALIDr, NULL, INVALIDr, INVALIDr, 2158 0 2159 }, 2160 { _SOC_PARITY_TYPE_MMU_ECC_CBPH, NULL, 2161 CBPPKTHDRPARITYERRORINTMASKf, CBPPKTHDRPARITYERRORf, 2162 INVALIDm, NULL, 2163 INVALIDr, INVALIDf, NULL, 2164 INVALIDr, INVALIDf, NULL, 2165 INVALIDr, cbppkthdr_regs, INVALIDf, 2166 INVALIDr, CBPPKTHDRPARITYERROR_CLRf, 2167 CBPPKTHDR_ERR_VLDr, NULL, INVALIDr, CBPPKTHDR_ERR_CLRr, 2168 0 2169 }, 2170 { _SOC_PARITY_TYPE_MMU_ECC_XQ, NULL, 2171 XQPARITYERRORINTMASKf, XQPARITYERRORf, 2172 INVALIDm, NULL, 2173 INVALIDr, INVALIDf, NULL, 2174 INVALIDr, INVALIDf, NULL, 2175 XQPARITYERRORPTRr, NULL, INVALIDf, 2176 INVALIDr, XQPARITYERROR_CLRf, 2177 XQ_ERR_VLDr, NULL, XQ_MULTI_ERRr, XQ_ERR_CLRr, 2178 0 2179 }, 2180 { _SOC_PARITY_TYPE_MMU_ECC_XQ, NULL, 2181 XQFLLPARITYERRORINTMASKf, XQFLLPARITYERRORf, 2182 INVALIDm, NULL, 2183 INVALIDr, INVALIDf, NULL, 2184 INVALIDr, INVALIDf, NULL, 2185 XQFLLPARITYERRORPTRr, NULL, INVALIDf, 2186 INVALIDr, XQFLLPARITYERROR_CLRf, 2187 XQFLL_ERR_VLDr, NULL, XQFLL_MULTI_ERRr, XQFLL_ERR_CLRr, 2188 0 2189 }, 2190 { _SOC_PARITY_TYPE_MMU_PAR_E2EFC, NULL, 2191 E2EFCPARITYERRORINTMASKf, E2EFCPARITYERRORf, 2192 INVALIDm, NULL, 2193 INVALIDr, INVALIDf, NULL, 2194 INVALIDr, INVALIDf, NULL, 2195 E2EFC_PARITYERRORPTRr, NULL, INVALIDf, 2196 INVALIDr, E2EFCPARITYERROR_CLRf, 2197 INVALIDr, NULL, INVALIDr, INVALIDr, 2198 0 2199 }, 2200 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2201 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2202 MMU_WRED_MARK_THDm, "MMU_WRED_MARK_THDm", 2203 INVALIDr, INVALIDf, NULL, 2204 INVALIDr, INVALIDf, NULL, 2205 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2206 INVALIDr, WREDPARITYERROR_CLRf, 2207 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2208 0 2209 }, 2210 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2211 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2212 MMU_WRED_DROP_PROFILE_GREENm, "MMU_WRED_DROP_PROFILE_GREENm", 2213 INVALIDr, INVALIDf, NULL, 2214 INVALIDr, INVALIDf, NULL, 2215 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2216 INVALIDr, WREDPARITYERROR_CLRf, 2217 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2218 0 2219 }, 2220 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2221 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2222 MMU_WRED_DROP_PROFILE_YELLOWm, "MMU_WRED_DROP_PROFILE_YELLOWm", 2223 INVALIDr, INVALIDf, NULL, 2224 INVALIDr, INVALIDf, NULL, 2225 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2226 INVALIDr, WREDPARITYERROR_CLRf, 2227 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2228 0 2229 }, 2230 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2231 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2232 MMU_WRED_DROP_PROFILE_REDm, "MMU_WRED_DROP_PROFILE_REDm", 2233 INVALIDr, INVALIDf, NULL, 2234 INVALIDr, INVALIDf, NULL, 2235 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2236 INVALIDr, WREDPARITYERROR_CLRf, 2237 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2238 0 2239 }, 2240 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2241 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2242 MMU_WRED_MARK_PROFILE_GREENm, "MMU_WRED_MARK_PROFILE_GREENm", 2243 INVALIDr, INVALIDf, NULL, 2244 INVALIDr, INVALIDf, NULL, 2245 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2246 INVALIDr, WREDPARITYERROR_CLRf, 2247 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2248 0 2249 }, 2250 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2251 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2252 MMU_WRED_MARK_PROFILE_YELLOWm, "MMU_WRED_MARK_PROFILE_YELLOWm", 2253 INVALIDr, INVALIDf, NULL, 2254 INVALIDr, INVALIDf, NULL, 2255 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2256 INVALIDr, WREDPARITYERROR_CLRf, 2257 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2258 0 2259 }, 2260 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2261 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2262 MMU_WRED_MARK_PROFILE_REDm, "MMU_WRED_MARK_PROFILE_REDm", 2263 INVALIDr, INVALIDf, NULL, 2264 INVALIDr, INVALIDf, NULL, 2265 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2266 INVALIDr, WREDPARITYERROR_CLRf, 2267 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2268 0 2269 }, 2270 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2271 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2272 MMU_WRED_AVG_QSIZEm, "MMU_WRED_AVG_QSIZEm", 2273 INVALIDr, INVALIDf, NULL, 2274 INVALIDr, INVALIDf, NULL, 2275 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2276 INVALIDr, WREDPARITYERROR_CLRf, 2277 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2278 0 2279 }, 2280 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2281 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2282 MMU_WRED_CONFIGm, "MMU_WRED_CONFIGm", 2283 INVALIDr, INVALIDf, NULL, 2284 INVALIDr, INVALIDf, NULL, 2285 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2286 INVALIDr, WREDPARITYERROR_CLRf, 2287 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2288 0 2289 }, 2290 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2291 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2292 MMU_WRED_AVG_QSIZE_QGROUPm, "MMU_WRED_AVG_QSIZE_QGROUPm", 2293 INVALIDr, INVALIDf, NULL, 2294 INVALIDr, INVALIDf, NULL, 2295 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2296 INVALIDr, WREDPARITYERROR_CLRf, 2297 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2298 0 2299 }, 2300 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 2301 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 2302 MMU_WRED_CONFIG_QGROUPm, "MMU_WRED_CONFIG_QGROUPm", 2303 INVALIDr, INVALIDf, NULL, 2304 INVALIDr, INVALIDf, NULL, 2305 INVALIDr, gh2_soc_wred_regs, INVALIDf, 2306 INVALIDr, WREDPARITYERROR_CLRf, 2307 WRED_PARITY_ERR_STATUSr, NULL, INVALIDr, WRED_ERR_CLRr, 2308 0 2309 }, 2310 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2311 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2312 MMU_IPMC_GROUP_TBL2m, "MMU_IPMC_GROUP_TBL2~31m", 2313 INVALIDr, INVALIDf, NULL, 2314 INVALIDr, INVALIDf, NULL, 2315 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2316 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2317 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2318 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2319 0 2320 }, 2321 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2322 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2323 MMU_IPMC_GROUP_TBL3m, "MMU_IPMC_GROUP_TBL2~31m", 2324 INVALIDr, INVALIDf, NULL, 2325 INVALIDr, INVALIDf, NULL, 2326 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2327 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2328 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2329 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2330 0 2331 }, 2332 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2333 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2334 MMU_IPMC_GROUP_TBL4m, "MMU_IPMC_GROUP_TBL2~31m", 2335 INVALIDr, INVALIDf, NULL, 2336 INVALIDr, INVALIDf, NULL, 2337 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2338 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2339 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2340 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2341 0 2342 }, 2343 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2344 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2345 MMU_IPMC_GROUP_TBL5m, "MMU_IPMC_GROUP_TBL2~31m", 2346 INVALIDr, INVALIDf, NULL, 2347 INVALIDr, INVALIDf, NULL, 2348 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2349 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2350 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2351 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2352 0 2353 }, 2354 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2355 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2356 MMU_IPMC_GROUP_TBL6m, "MMU_IPMC_GROUP_TBL2~31m", 2357 INVALIDr, INVALIDf, NULL, 2358 INVALIDr, INVALIDf, NULL, 2359 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2360 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2361 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2362 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2363 0 2364 }, 2365 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2366 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2367 MMU_IPMC_GROUP_TBL7m, "MMU_IPMC_GROUP_TBL2~31m", 2368 INVALIDr, INVALIDf, NULL, 2369 INVALIDr, INVALIDf, NULL, 2370 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2371 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2372 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2373 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2374 0 2375 }, 2376 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2377 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2378 MMU_IPMC_GROUP_TBL8m, "MMU_IPMC_GROUP_TBL2~31m", 2379 INVALIDr, INVALIDf, NULL, 2380 INVALIDr, INVALIDf, NULL, 2381 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2382 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2383 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2384 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2385 0 2386 }, 2387 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2388 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2389 MMU_IPMC_GROUP_TBL9m, "MMU_IPMC_GROUP_TBL2~31m", 2390 INVALIDr, INVALIDf, NULL, 2391 INVALIDr, INVALIDf, NULL, 2392 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2393 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2394 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2395 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2396 0 2397 }, 2398 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2399 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2400 MMU_IPMC_GROUP_TBL10m, "MMU_IPMC_GROUP_TBL2~31m", 2401 INVALIDr, INVALIDf, NULL, 2402 INVALIDr, INVALIDf, NULL, 2403 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2404 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2405 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2406 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2407 0 2408 }, 2409 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2410 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2411 MMU_IPMC_GROUP_TBL11m, "MMU_IPMC_GROUP_TBL2~31m", 2412 INVALIDr, INVALIDf, NULL, 2413 INVALIDr, INVALIDf, NULL, 2414 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2415 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2416 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2417 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2418 0 2419 }, 2420 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2421 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2422 MMU_IPMC_GROUP_TBL12m, "MMU_IPMC_GROUP_TBL2~31m", 2423 INVALIDr, INVALIDf, NULL, 2424 INVALIDr, INVALIDf, NULL, 2425 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2426 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2427 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2428 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2429 0 2430 }, 2431 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2432 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2433 MMU_IPMC_GROUP_TBL13m, "MMU_IPMC_GROUP_TBL2~31m", 2434 INVALIDr, INVALIDf, NULL, 2435 INVALIDr, INVALIDf, NULL, 2436 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2437 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2438 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2439 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2440 0 2441 }, 2442 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2443 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2444 MMU_IPMC_GROUP_TBL14m, "MMU_IPMC_GROUP_TBL2~31m", 2445 INVALIDr, INVALIDf, NULL, 2446 INVALIDr, INVALIDf, NULL, 2447 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2448 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2449 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2450 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2451 0 2452 }, 2453 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2454 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2455 MMU_IPMC_GROUP_TBL15m, "MMU_IPMC_GROUP_TBL2~31m", 2456 INVALIDr, INVALIDf, NULL, 2457 INVALIDr, INVALIDf, NULL, 2458 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2459 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2460 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2461 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2462 0 2463 }, 2464 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2465 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2466 MMU_IPMC_GROUP_TBL16m, "MMU_IPMC_GROUP_TBL2~31m", 2467 INVALIDr, INVALIDf, NULL, 2468 INVALIDr, INVALIDf, NULL, 2469 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2470 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2471 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2472 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2473 0 2474 }, 2475 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2476 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2477 MMU_IPMC_GROUP_TBL17m, "MMU_IPMC_GROUP_TBL2~31m", 2478 INVALIDr, INVALIDf, NULL, 2479 INVALIDr, INVALIDf, NULL, 2480 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2481 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2482 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2483 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2484 0 2485 }, 2486 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2487 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2488 MMU_IPMC_GROUP_TBL18m, "MMU_IPMC_GROUP_TBL2~31m", 2489 INVALIDr, INVALIDf, NULL, 2490 INVALIDr, INVALIDf, NULL, 2491 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2492 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2493 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2494 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2495 0 2496 }, 2497 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2498 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2499 MMU_IPMC_GROUP_TBL19m, "MMU_IPMC_GROUP_TBL2~31m", 2500 INVALIDr, INVALIDf, NULL, 2501 INVALIDr, INVALIDf, NULL, 2502 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2503 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2504 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2505 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2506 0 2507 }, 2508 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2509 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2510 MMU_IPMC_GROUP_TBL20m, "MMU_IPMC_GROUP_TBL2~31m", 2511 INVALIDr, INVALIDf, NULL, 2512 INVALIDr, INVALIDf, NULL, 2513 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2514 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2515 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2516 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2517 0 2518 }, 2519 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2520 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2521 MMU_IPMC_GROUP_TBL21m, "MMU_IPMC_GROUP_TBL2~31m", 2522 INVALIDr, INVALIDf, NULL, 2523 INVALIDr, INVALIDf, NULL, 2524 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2525 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2526 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2527 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2528 0 2529 }, 2530 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2531 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2532 MMU_IPMC_GROUP_TBL22m, "MMU_IPMC_GROUP_TBL2~31m", 2533 INVALIDr, INVALIDf, NULL, 2534 INVALIDr, INVALIDf, NULL, 2535 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2536 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2537 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2538 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2539 0 2540 }, 2541 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2542 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2543 MMU_IPMC_GROUP_TBL23m, "MMU_IPMC_GROUP_TBL2~31m", 2544 INVALIDr, INVALIDf, NULL, 2545 INVALIDr, INVALIDf, NULL, 2546 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2547 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2548 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2549 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2550 0 2551 }, 2552 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2553 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2554 MMU_IPMC_GROUP_TBL24m, "MMU_IPMC_GROUP_TBL2~31m", 2555 INVALIDr, INVALIDf, NULL, 2556 INVALIDr, INVALIDf, NULL, 2557 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2558 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2559 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2560 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2561 0 2562 }, 2563 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2564 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2565 MMU_IPMC_GROUP_TBL25m, "MMU_IPMC_GROUP_TBL2~31m", 2566 INVALIDr, INVALIDf, NULL, 2567 INVALIDr, INVALIDf, NULL, 2568 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2569 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2570 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2571 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2572 0 2573 }, 2574 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2575 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2576 MMU_IPMC_GROUP_TBL26m, "MMU_IPMC_GROUP_TBL2~31m", 2577 INVALIDr, INVALIDf, NULL, 2578 INVALIDr, INVALIDf, NULL, 2579 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2580 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2581 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2582 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2583 0 2584 }, 2585 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2586 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2587 MMU_IPMC_GROUP_TBL27m, "MMU_IPMC_GROUP_TBL2~31m", 2588 INVALIDr, INVALIDf, NULL, 2589 INVALIDr, INVALIDf, NULL, 2590 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2591 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2592 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2593 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2594 0 2595 }, 2596 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2597 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2598 MMU_IPMC_GROUP_TBL28m, "MMU_IPMC_GROUP_TBL2~31m", 2599 INVALIDr, INVALIDf, NULL, 2600 INVALIDr, INVALIDf, NULL, 2601 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2602 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2603 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2604 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2605 0 2606 }, 2607 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2608 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2609 MMU_IPMC_GROUP_TBL29m, "MMU_IPMC_GROUP_TBL2~31m", 2610 INVALIDr, INVALIDf, NULL, 2611 INVALIDr, INVALIDf, NULL, 2612 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2613 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2614 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2615 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2616 0 2617 }, 2618 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2619 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2620 MMU_IPMC_GROUP_TBL30m, "MMU_IPMC_GROUP_TBL2~31m", 2621 INVALIDr, INVALIDf, NULL, 2622 INVALIDr, INVALIDf, NULL, 2623 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2624 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2625 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2626 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2627 0 2628 }, 2629 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2630 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2631 MMU_IPMC_GROUP_TBL31m, "MMU_IPMC_GROUP_TBL2~31m", 2632 INVALIDr, INVALIDf, NULL, 2633 INVALIDr, INVALIDf, NULL, 2634 INVALIDr, ipmcgroup2to31_regs, INVALIDf, 2635 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2636 IPMC_GROUP_ERR_VLD_0r, ipmcgroup_vld_regs, 2637 IPMC_GROUP_MULTI_ERR_0r, IPMC_GROUP_ERR_CLR_0r, 2638 0 2639 }, 2640 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2641 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2642 MMU_IPMC_GROUP_TBL32m, "MMU_IPMC_GROUP_TBL32~63m", 2643 INVALIDr, INVALIDf, NULL, 2644 INVALIDr, INVALIDf, NULL, 2645 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2646 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2647 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2648 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2649 0 2650 }, 2651 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2652 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2653 MMU_IPMC_GROUP_TBL33m, "MMU_IPMC_GROUP_TBL32~63m", 2654 INVALIDr, INVALIDf, NULL, 2655 INVALIDr, INVALIDf, NULL, 2656 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2657 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2658 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2659 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2660 0 2661 }, 2662 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2663 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2664 MMU_IPMC_GROUP_TBL34m, "MMU_IPMC_GROUP_TBL32~63m", 2665 INVALIDr, INVALIDf, NULL, 2666 INVALIDr, INVALIDf, NULL, 2667 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2668 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2669 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2670 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2671 0 2672 }, 2673 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2674 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2675 MMU_IPMC_GROUP_TBL35m, "MMU_IPMC_GROUP_TBL32~63m", 2676 INVALIDr, INVALIDf, NULL, 2677 INVALIDr, INVALIDf, NULL, 2678 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2679 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2680 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2681 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2682 0 2683 }, 2684 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2685 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2686 MMU_IPMC_GROUP_TBL36m, "MMU_IPMC_GROUP_TBL32~63m", 2687 INVALIDr, INVALIDf, NULL, 2688 INVALIDr, INVALIDf, NULL, 2689 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2690 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2691 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2692 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2693 0 2694 }, 2695 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2696 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2697 MMU_IPMC_GROUP_TBL37m, "MMU_IPMC_GROUP_TBL32~63m", 2698 INVALIDr, INVALIDf, NULL, 2699 INVALIDr, INVALIDf, NULL, 2700 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2701 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2702 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2703 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2704 0 2705 }, 2706 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2707 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2708 MMU_IPMC_GROUP_TBL38m, "MMU_IPMC_GROUP_TBL32~63m", 2709 INVALIDr, INVALIDf, NULL, 2710 INVALIDr, INVALIDf, NULL, 2711 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2712 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2713 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2714 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2715 0 2716 }, 2717 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2718 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2719 MMU_IPMC_GROUP_TBL39m, "MMU_IPMC_GROUP_TBL32~63m", 2720 INVALIDr, INVALIDf, NULL, 2721 INVALIDr, INVALIDf, NULL, 2722 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2723 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2724 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2725 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2726 0 2727 }, 2728 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2729 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2730 MMU_IPMC_GROUP_TBL40m, "MMU_IPMC_GROUP_TBL32~63m", 2731 INVALIDr, INVALIDf, NULL, 2732 INVALIDr, INVALIDf, NULL, 2733 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2734 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2735 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2736 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2737 0 2738 }, 2739 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2740 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2741 MMU_IPMC_GROUP_TBL41m, "MMU_IPMC_GROUP_TBL32~63m", 2742 INVALIDr, INVALIDf, NULL, 2743 INVALIDr, INVALIDf, NULL, 2744 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2745 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2746 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2747 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2748 0 2749 }, 2750 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2751 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2752 MMU_IPMC_GROUP_TBL42m, "MMU_IPMC_GROUP_TBL32~63m", 2753 INVALIDr, INVALIDf, NULL, 2754 INVALIDr, INVALIDf, NULL, 2755 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2756 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2757 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2758 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2759 0 2760 }, 2761 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2762 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2763 MMU_IPMC_GROUP_TBL43m, "MMU_IPMC_GROUP_TBL32~63m", 2764 INVALIDr, INVALIDf, NULL, 2765 INVALIDr, INVALIDf, NULL, 2766 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2767 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2768 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2769 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2770 0 2771 }, 2772 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2773 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2774 MMU_IPMC_GROUP_TBL44m, "MMU_IPMC_GROUP_TBL32~63m", 2775 INVALIDr, INVALIDf, NULL, 2776 INVALIDr, INVALIDf, NULL, 2777 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2778 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2779 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2780 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2781 0 2782 }, 2783 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2784 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2785 MMU_IPMC_GROUP_TBL45m, "MMU_IPMC_GROUP_TBL32~63m", 2786 INVALIDr, INVALIDf, NULL, 2787 INVALIDr, INVALIDf, NULL, 2788 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2789 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2790 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2791 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2792 0 2793 }, 2794 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2795 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2796 MMU_IPMC_GROUP_TBL46m, "MMU_IPMC_GROUP_TBL32~63m", 2797 INVALIDr, INVALIDf, NULL, 2798 INVALIDr, INVALIDf, NULL, 2799 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2800 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2801 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2802 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2803 0 2804 }, 2805 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2806 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2807 MMU_IPMC_GROUP_TBL47m, "MMU_IPMC_GROUP_TBL32~63m", 2808 INVALIDr, INVALIDf, NULL, 2809 INVALIDr, INVALIDf, NULL, 2810 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2811 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2812 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2813 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2814 0 2815 }, 2816 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2817 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2818 MMU_IPMC_GROUP_TBL48m, "MMU_IPMC_GROUP_TBL32~63m", 2819 INVALIDr, INVALIDf, NULL, 2820 INVALIDr, INVALIDf, NULL, 2821 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2822 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2823 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2824 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2825 0 2826 }, 2827 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2828 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2829 MMU_IPMC_GROUP_TBL49m, "MMU_IPMC_GROUP_TBL32~63m", 2830 INVALIDr, INVALIDf, NULL, 2831 INVALIDr, INVALIDf, NULL, 2832 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2833 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2834 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2835 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2836 0 2837 }, 2838 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2839 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2840 MMU_IPMC_GROUP_TBL50m, "MMU_IPMC_GROUP_TBL32~63m", 2841 INVALIDr, INVALIDf, NULL, 2842 INVALIDr, INVALIDf, NULL, 2843 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2844 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2845 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2846 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2847 0 2848 }, 2849 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2850 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2851 MMU_IPMC_GROUP_TBL51m, "MMU_IPMC_GROUP_TBL32~63m", 2852 INVALIDr, INVALIDf, NULL, 2853 INVALIDr, INVALIDf, NULL, 2854 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2855 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2856 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2857 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2858 0 2859 }, 2860 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2861 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2862 MMU_IPMC_GROUP_TBL52m, "MMU_IPMC_GROUP_TBL32~63m", 2863 INVALIDr, INVALIDf, NULL, 2864 INVALIDr, INVALIDf, NULL, 2865 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2866 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2867 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2868 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2869 0 2870 }, 2871 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2872 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2873 MMU_IPMC_GROUP_TBL53m, "MMU_IPMC_GROUP_TBL32~63m", 2874 INVALIDr, INVALIDf, NULL, 2875 INVALIDr, INVALIDf, NULL, 2876 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2877 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2878 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2879 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2880 0 2881 }, 2882 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2883 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2884 MMU_IPMC_GROUP_TBL54m, "MMU_IPMC_GROUP_TBL32~63m", 2885 INVALIDr, INVALIDf, NULL, 2886 INVALIDr, INVALIDf, NULL, 2887 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2888 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2889 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2890 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2891 0 2892 }, 2893 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2894 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2895 MMU_IPMC_GROUP_TBL55m, "MMU_IPMC_GROUP_TBL32~63m", 2896 INVALIDr, INVALIDf, NULL, 2897 INVALIDr, INVALIDf, NULL, 2898 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2899 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2900 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2901 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2902 0 2903 }, 2904 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2905 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2906 MMU_IPMC_GROUP_TBL56m, "MMU_IPMC_GROUP_TBL32~63m", 2907 INVALIDr, INVALIDf, NULL, 2908 INVALIDr, INVALIDf, NULL, 2909 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2910 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2911 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2912 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2913 0 2914 }, 2915 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2916 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2917 MMU_IPMC_GROUP_TBL57m, "MMU_IPMC_GROUP_TBL32~63m", 2918 INVALIDr, INVALIDf, NULL, 2919 INVALIDr, INVALIDf, NULL, 2920 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2921 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2922 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2923 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2924 0 2925 }, 2926 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2927 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2928 MMU_IPMC_GROUP_TBL58m, "MMU_IPMC_GROUP_TBL32~63m", 2929 INVALIDr, INVALIDf, NULL, 2930 INVALIDr, INVALIDf, NULL, 2931 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2932 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2933 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2934 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2935 0 2936 }, 2937 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2938 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2939 MMU_IPMC_GROUP_TBL59m, "MMU_IPMC_GROUP_TBL32~63m", 2940 INVALIDr, INVALIDf, NULL, 2941 INVALIDr, INVALIDf, NULL, 2942 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2943 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2944 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2945 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2946 0 2947 }, 2948 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2949 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2950 MMU_IPMC_GROUP_TBL60m, "MMU_IPMC_GROUP_TBL32~63m", 2951 INVALIDr, INVALIDf, NULL, 2952 INVALIDr, INVALIDf, NULL, 2953 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2954 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2955 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2956 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2957 0 2958 }, 2959 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2960 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2961 MMU_IPMC_GROUP_TBL61m, "MMU_IPMC_GROUP_TBL32~63m", 2962 INVALIDr, INVALIDf, NULL, 2963 INVALIDr, INVALIDf, NULL, 2964 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2965 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2966 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2967 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2968 0 2969 }, 2970 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2971 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2972 MMU_IPMC_GROUP_TBL62m, "MMU_IPMC_GROUP_TBL32~63m", 2973 INVALIDr, INVALIDf, NULL, 2974 INVALIDr, INVALIDf, NULL, 2975 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2976 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2977 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2978 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2979 0 2980 }, 2981 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2982 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2983 MMU_IPMC_GROUP_TBL63m, "MMU_IPMC_GROUP_TBL32~63m", 2984 INVALIDr, INVALIDf, NULL, 2985 INVALIDr, INVALIDf, NULL, 2986 INVALIDr, ipmcgroup32to63_regs, INVALIDf, 2987 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2988 IPMC_GROUP_ERR_VLD_1r, ipmcgroup_vld_regs, 2989 IPMC_GROUP_MULTI_ERR_1r, IPMC_GROUP_ERR_CLR_1r, 2990 0 2991 }, 2992 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 2993 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 2994 MMU_IPMC_GROUP_TBL64m, "MMU_IPMC_GROUP_TBL64~65m", 2995 INVALIDr, INVALIDf, NULL, 2996 INVALIDr, INVALIDf, NULL, 2997 INVALIDr, ipmcgroup64to65_regs, INVALIDf, 2998 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2999 IPMC_GROUP_ERR_VLD_2r, ipmcgroup_vld_regs, 3000 IPMC_GROUP_MULTI_ERR_2r, IPMC_GROUP_ERR_CLR_2r, 3001 0 3002 }, 3003 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 3004 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 3005 MMU_IPMC_GROUP_TBL65m, "MMU_IPMC_GROUP_TBL64~65m", 3006 INVALIDr, INVALIDf, NULL, 3007 INVALIDr, INVALIDf, NULL, 3008 INVALIDr, ipmcgroup64to65_regs, INVALIDf, 3009 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 3010 IPMC_GROUP_ERR_VLD_2r, ipmcgroup_vld_regs, 3011 IPMC_GROUP_MULTI_ERR_2r, IPMC_GROUP_ERR_CLR_2r, 3012 0 3013 }, 3014 { _SOC_PARITY_TYPE_MMU_ECC_IPMCVLAN, NULL, 3015 IPMCVLANXPORTPARITYERRORINTMASKf,IPMCVLANXPORTPARITYERRORf, 3016 MMU_IPMC_VLAN_TBLm, NULL, 3017 INVALIDr, INVALIDf, NULL, 3018 INVALIDr, INVALIDf, NULL, 3019 IPMCPARITYERRORPTRr, NULL, INVALIDf, 3020 INVALIDr, IPMCVLANXPORTPARITYERROR_CLRf, 3021 INVALIDr, NULL, INVALIDr, INVALIDr, 3022 0 3023 }, 3024 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 3025 }; 3026 #endif /*_GH2_SER_TEST_MMU */ 3027 3028 static _soc_gh2_ser_info_t _soc_gh2_mmu_top_ser_info[] = { 3029 #if _GH2_SER_TEST_MMU 3030 { _SOC_PARITY_TYPE_MMU_SER, _soc_gh2_mmu_ser_info, 3031 INVALIDf, INVALIDf, 3032 INVALIDm, "MMU MEM PAR", 3033 MISCCONFIGr, PARITY_CHECK_ENf, NULL, 3034 MEMFAILINTMASKr, INVALIDf, NULL, 3035 MEMFAILINTSTATUSr, NULL, INVALIDf, 3036 MEMFAILINT_CLRr, INVALIDf, 3037 INVALIDr, NULL, INVALIDr, INVALIDr, 3038 0 3039 }, 3040 #endif /* _GH2_SER_TEST_MMU */ 3041 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 3042 }; 3043 3044 #if _GH2_SER_TEST_CLPORT 3045 static _soc_gh2_ser_info_t _soc_gh2_clport_ser_info[] = { 3046 { _SOC_PARITY_TYPE_ECC, NULL, 3047 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 3048 INVALIDm, NULL, 3049 CLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 3050 INVALIDr, INVALIDf, NULL, 3051 CLPORT_MIB_RSC0_ECC_STATUSr, NULL, ECC_ERRf, 3052 CLPORT_INTR_STATUSr, MIB_RX_MEM_ERRf, 3053 INVALIDr, NULL, INVALIDr, INVALIDr, 3054 0 3055 }, 3056 { _SOC_PARITY_TYPE_ECC, NULL, 3057 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 3058 INVALIDm, NULL, 3059 CLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 3060 INVALIDr, INVALIDf, NULL, 3061 CLPORT_MIB_TSC0_ECC_STATUSr, NULL, ECC_ERRf, 3062 CLPORT_INTR_STATUSr, MIB_TX_MEM_ERRf, 3063 INVALIDr, NULL, INVALIDr, INVALIDr, 3064 0 3065 }, 3066 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 3067 }; 3068 #endif /* _GH2_SER_TEST_CLPORT */ 3069 3070 static _soc_gh2_ser_info_t _soc_gh2_pgw_clport_ser_info[] = { 3071 #if _GH2_SER_TEST_CLPORT 3072 { _SOC_PARITY_TYPE_PORT_XL, _soc_gh2_clport_ser_info, 3073 PM_INTRf, PM_INTRf, 3074 INVALIDm, "CL PORT INTR", 3075 INVALIDr, INVALIDf, NULL, 3076 CLPORT_INTR_ENABLEr, INVALIDf, NULL, 3077 CLPORT_INTR_STATUSr, NULL, INVALIDf, 3078 INVALIDr, INVALIDf, 3079 INVALIDr, NULL, INVALIDr, INVALIDr, 3080 0 3081 }, 3082 { _SOC_PARITY_TYPE_ECC, NULL, 3083 TXFIFO0_DBEf, TXFIFO0_DBEf, 3084 INVALIDm, NULL, 3085 PGW_CL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3086 INVALIDr, INVALIDf, NULL, 3087 PGW_CL_TXFIFO0_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3088 INVALIDr, INVALIDf, 3089 INVALIDr, NULL, INVALIDr, INVALIDr, 3090 0 3091 }, 3092 { _SOC_PARITY_TYPE_ECC, NULL, 3093 TXFIFO1_DBEf, TXFIFO1_DBEf, 3094 INVALIDm, NULL, 3095 PGW_CL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3096 INVALIDr, INVALIDf, NULL, 3097 PGW_CL_TXFIFO1_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3098 INVALIDr, INVALIDf, 3099 INVALIDr, NULL, INVALIDr, INVALIDr, 3100 0 3101 }, 3102 { _SOC_PARITY_TYPE_ECC, NULL, 3103 TXFIFO2_DBEf, TXFIFO2_DBEf, 3104 INVALIDm, NULL, 3105 PGW_CL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3106 INVALIDr, INVALIDf, NULL, 3107 PGW_CL_TXFIFO2_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3108 INVALIDr, INVALIDf, 3109 INVALIDr, NULL, INVALIDr, INVALIDr, 3110 0 3111 }, 3112 { _SOC_PARITY_TYPE_ECC, NULL, 3113 TXFIFO3_DBEf, TXFIFO3_DBEf, 3114 INVALIDm, NULL, 3115 PGW_CL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3116 INVALIDr, INVALIDf, NULL, 3117 PGW_CL_TXFIFO3_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3118 INVALIDr, INVALIDf, 3119 INVALIDr, NULL, INVALIDr, INVALIDr, 3120 0 3121 }, 3122 { _SOC_PARITY_TYPE_ECC, NULL, 3123 RXFIFO0_DBEf, RXFIFO0_DBEf, 3124 INVALIDm, NULL, 3125 PGW_CL_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 3126 INVALIDr, INVALIDf, NULL, 3127 PGW_CL_RXFIFO_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3128 INVALIDr, INVALIDf, 3129 INVALIDr, NULL, INVALIDr, INVALIDr, 3130 0 3131 }, 3132 #endif /* _GH2_SER_TEST_CLPORT */ 3133 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 3134 }; 3135 3136 #if _GH2_SER_TEST_XLPORT 3137 static _soc_gh2_ser_info_t _soc_gh2_xlport_ser_info[] = { 3138 { _SOC_PARITY_TYPE_ECC, NULL, 3139 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 3140 INVALIDm, NULL, 3141 XLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 3142 INVALIDr, INVALIDf, NULL, 3143 XLPORT_MIB_RSC0_ECC_STATUSr, NULL, ECC_ERRf, 3144 XLPORT_INTR_STATUSr, MIB_RX_MEM_ERRf, 3145 INVALIDr, NULL, INVALIDr, INVALIDr, 3146 0 3147 }, 3148 { _SOC_PARITY_TYPE_ECC, NULL, 3149 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 3150 INVALIDm, NULL, 3151 XLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 3152 INVALIDr, INVALIDf, NULL, 3153 XLPORT_MIB_TSC0_ECC_STATUSr, NULL, ECC_ERRf, 3154 XLPORT_INTR_STATUSr, MIB_TX_MEM_ERRf, 3155 INVALIDr, NULL, INVALIDr, INVALIDr, 3156 0 3157 }, 3158 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 3159 }; 3160 #endif /* _GH2_SER_TEST_XLPORT */ 3161 3162 static _soc_gh2_ser_info_t _soc_gh2_pgw_xlport_ser_info[] = { 3163 #if _GH2_SER_TEST_XLPORT 3164 { _SOC_PARITY_TYPE_PORT_XL, _soc_gh2_xlport_ser_info, 3165 PM_INTRf, PM_INTRf, 3166 INVALIDm, "XL PORT INTR", 3167 INVALIDr, INVALIDf, NULL, 3168 XLPORT_INTR_ENABLEr, INVALIDf, NULL, 3169 XLPORT_INTR_STATUSr, NULL, INVALIDf, 3170 INVALIDr, INVALIDf, 3171 INVALIDr, NULL, INVALIDr, INVALIDr, 3172 0 3173 }, 3174 { _SOC_PARITY_TYPE_ECC, NULL, 3175 RXFIFO_DBEf, RXFIFO_DBEf, 3176 INVALIDm, NULL, 3177 PGW_XL_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 3178 INVALIDr, INVALIDf, NULL, 3179 PGW_XL_RXFIFO_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3180 INVALIDr, INVALIDf, 3181 INVALIDr, NULL, INVALIDr, INVALIDr, 3182 0 3183 }, 3184 { _SOC_PARITY_TYPE_ECC, NULL, 3185 TXFIFO0_DBEf, TXFIFO0_DBEf, 3186 INVALIDm, NULL, 3187 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3188 INVALIDr, INVALIDf, NULL, 3189 PGW_XL_TXFIFO0_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3190 INVALIDr, INVALIDf, 3191 INVALIDr, NULL, INVALIDr, INVALIDr, 3192 0 3193 }, 3194 { _SOC_PARITY_TYPE_ECC, NULL, 3195 TXFIFO1_DBEf, TXFIFO1_DBEf, 3196 INVALIDm, NULL, 3197 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3198 INVALIDr, INVALIDf, NULL, 3199 PGW_XL_TXFIFO1_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3200 INVALIDr, INVALIDf, 3201 INVALIDr, NULL, INVALIDr, INVALIDr, 3202 0 3203 }, 3204 { _SOC_PARITY_TYPE_ECC, NULL, 3205 TXFIFO2_DBEf, TXFIFO2_DBEf, 3206 INVALIDm, NULL, 3207 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3208 INVALIDr, INVALIDf, NULL, 3209 PGW_XL_TXFIFO2_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3210 INVALIDr, INVALIDf, 3211 INVALIDr, NULL, INVALIDr, INVALIDr, 3212 0 3213 }, 3214 { _SOC_PARITY_TYPE_ECC, NULL, 3215 TXFIFO3_DBEf, TXFIFO3_DBEf, 3216 INVALIDm, NULL, 3217 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3218 INVALIDr, INVALIDf, NULL, 3219 PGW_XL_TXFIFO3_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3220 INVALIDr, INVALIDf, 3221 INVALIDr, NULL, INVALIDr, INVALIDr, 3222 0 3223 }, 3224 { _SOC_PARITY_TYPE_ECC, NULL, 3225 TXFIFO0_DBE_Hf, TXFIFO0_DBE_Hf, 3226 INVALIDm, NULL, 3227 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3228 INVALIDr, INVALIDf, NULL, 3229 PGW_XL_TXFIFO0_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 3230 INVALIDr, INVALIDf, 3231 INVALIDr, NULL, INVALIDr, INVALIDr, 3232 0 3233 }, 3234 { _SOC_PARITY_TYPE_ECC, NULL, 3235 TXFIFO1_DBE_Hf, TXFIFO1_DBE_Hf, 3236 INVALIDm, NULL, 3237 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3238 INVALIDr, INVALIDf, NULL, 3239 PGW_XL_TXFIFO1_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 3240 INVALIDr, INVALIDf, 3241 INVALIDr, NULL, INVALIDr, INVALIDr, 3242 0 3243 }, 3244 { _SOC_PARITY_TYPE_ECC, NULL, 3245 TXFIFO2_DBE_Hf, TXFIFO2_DBE_Hf, 3246 INVALIDm, NULL, 3247 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3248 INVALIDr, INVALIDf, NULL, 3249 PGW_XL_TXFIFO2_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 3250 INVALIDr, INVALIDf, 3251 INVALIDr, NULL, INVALIDr, INVALIDr, 3252 0 3253 }, 3254 { _SOC_PARITY_TYPE_ECC, NULL, 3255 TXFIFO3_DBE_Hf, TXFIFO3_DBE_Hf, 3256 INVALIDm, NULL, 3257 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3258 INVALIDr, INVALIDf, NULL, 3259 PGW_XL_TXFIFO3_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 3260 INVALIDr, INVALIDf, 3261 INVALIDr, NULL, INVALIDr, INVALIDr, 3262 0 3263 }, 3264 #endif /* _GH2_SER_TEST_XLPORT */ 3265 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 3266 }; 3267 3268 static _soc_gh2_ser_info_t _soc_gh2_pgw_gport_ser_info[] = { 3269 #if _GH2_SER_TEST_GPORT 3270 { _SOC_PARITY_TYPE_ECC, NULL, 3271 TXFIFO0_DBEf, TXFIFO0_DBEf, 3272 INVALIDm, NULL, 3273 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3274 INVALIDr, INVALIDf, NULL, 3275 PGW_GE_TXFIFO0_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3276 INVALIDr, INVALIDf, 3277 INVALIDr, NULL, INVALIDr, INVALIDr, 3278 0 3279 }, 3280 { _SOC_PARITY_TYPE_ECC, NULL, 3281 TXFIFO1_DBEf, TXFIFO1_DBEf, 3282 INVALIDm, NULL, 3283 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3284 INVALIDr, INVALIDf, NULL, 3285 PGW_GE_TXFIFO1_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3286 INVALIDr, INVALIDf, 3287 INVALIDr, NULL, INVALIDr, INVALIDr, 3288 0 3289 }, 3290 { _SOC_PARITY_TYPE_ECC, NULL, 3291 TXFIFO2_DBEf, TXFIFO2_DBEf, 3292 INVALIDm, NULL, 3293 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3294 INVALIDr, INVALIDf, NULL, 3295 PGW_GE_TXFIFO2_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3296 INVALIDr, INVALIDf, 3297 INVALIDr, NULL, INVALIDr, INVALIDr, 3298 0 3299 }, 3300 { _SOC_PARITY_TYPE_ECC, NULL, 3301 TXFIFO3_DBEf, TXFIFO3_DBEf, 3302 INVALIDm, NULL, 3303 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 3304 INVALIDr, INVALIDf, NULL, 3305 PGW_GE_TXFIFO3_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3306 INVALIDr, INVALIDf, 3307 INVALIDr, NULL, INVALIDr, INVALIDr, 3308 0 3309 }, 3310 { _SOC_PARITY_TYPE_ECC, NULL, 3311 RXFIFO0_DBEf, RXFIFO0_DBEf, 3312 INVALIDm, NULL, 3313 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 3314 INVALIDr, INVALIDf, NULL, 3315 PGW_GE_RXFIFO0_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3316 INVALIDr, INVALIDf, 3317 INVALIDr, NULL, INVALIDr, INVALIDr, 3318 0 3319 }, 3320 { _SOC_PARITY_TYPE_ECC, NULL, 3321 RXFIFO1_DBEf, RXFIFO1_DBEf, 3322 INVALIDm, NULL, 3323 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 3324 INVALIDr, INVALIDf, NULL, 3325 PGW_GE_RXFIFO1_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3326 INVALIDr, INVALIDf, 3327 INVALIDr, NULL, INVALIDr, INVALIDr, 3328 0 3329 }, 3330 { _SOC_PARITY_TYPE_ECC, NULL, 3331 RXFIFO2_DBEf, RXFIFO2_DBEf, 3332 INVALIDm, NULL, 3333 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 3334 INVALIDr, INVALIDf, NULL, 3335 PGW_GE_RXFIFO2_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3336 INVALIDr, INVALIDf, 3337 INVALIDr, NULL, INVALIDr, INVALIDr, 3338 0 3339 }, 3340 { _SOC_PARITY_TYPE_ECC, NULL, 3341 RXFIFO3_DBEf, RXFIFO3_DBEf, 3342 INVALIDm, NULL, 3343 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 3344 INVALIDr, INVALIDf, NULL, 3345 PGW_GE_RXFIFO3_ECC_DBE_STATUSr, NULL, ECC_ERRf, 3346 INVALIDr, INVALIDf, 3347 INVALIDr, NULL, INVALIDr, INVALIDr, 3348 0 3349 }, 3350 #endif /* _GH2_SER_TEST_GPORT */ 3351 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 3352 }; 3353 3354 /* from FORMAT CMIC_PARITY_INTR_STATUS */ 3355 #define _GH2_PAR_MMU (0) 3356 #define _GH2_PAR_EP (1) 3357 #define _GH2_PAR_IP0 (2) 3358 #define _GH2_PAR_IP1 (3) 3359 #define _GH2_PAR_IP2 (4) 3360 #define _GH2_PAR_IP2_SR (5) 3361 #define _GH2_PAR_IP2_SR_SN (6) 3362 #define _GH2_PAR_GE8P0 (8) 3363 #define _GH2_PAR_GE8P1 (9) 3364 #define _GH2_PAR_GE8P2 (10) 3365 #define _GH2_PAR_GE0 (11) 3366 #define _GH2_PAR_GE1 (12) 3367 #define _GH2_PAR_XL0 (13) 3368 #define _GH2_PAR_XL1 (14) 3369 #define _GH2_PAR_XL2 (15) 3370 #define _GH2_PAR_XL3 (16) 3371 #define _GH2_PAR_XL4 (17) 3372 #define _GH2_PAR_XL5 (18) 3373 #define _GH2_PAR_XL6 (19) 3374 #define _GH2_PAR_CL (20) 3375 3376 #define _GH2_X_TO_CMIC_INTR(bit) (1 << (bit)) /* Bit 0-31 */ 3377 3378 typedef struct _soc_gh2_ser_route_block_s{ 3379 uint32 cmic_bit; 3380 soc_block_t blocktype; 3381 uint8 id; 3382 soc_reg_t enable_reg; 3383 soc_reg_t status_reg; 3384 void *info; 3385 } _soc_gh2_ser_route_block_t; 3386 3387 static _soc_gh2_ser_route_block_t _soc_gh2_ser_route_blocks[] = { 3388 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_MMU), SOC_BLK_MMU, 0, 3389 INVALIDr, INVALIDr, 3390 _soc_gh2_mmu_top_ser_info}, 3391 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_EP), SOC_BLK_EPIPE, 0, 3392 EGR_INTR_ENABLE_64r, EGR_INTR_STATUS_64r, 3393 _soc_gh2_ep_ser_info}, 3394 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_IP0), SOC_BLK_IPIPE, 0, 3395 IP0_INTR_ENABLEr, IP0_INTR_STATUSr, 3396 _soc_gh2_ip0_ser_info}, 3397 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_IP1), SOC_BLK_IPIPE, 0, 3398 IP1_INTR_ENABLEr, IP1_INTR_STATUSr, 3399 _soc_gh2_ip1_ser_info}, 3400 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_IP2), SOC_BLK_IPIPE, 0, 3401 IP2_INTR_ENABLEr, IP2_INTR_STATUSr, 3402 _soc_gh2_ip2_ser_info}, 3403 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_IP2_SR), SOC_BLK_IPIPE, 0, 3404 IP2_SR_INTR_ENABLEr, IP2_SR_INTR_STATUSr, 3405 _soc_gh2_ip2_sr_ser_info}, 3406 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_IP2_SR_SN), SOC_BLK_IPIPE, 0, 3407 IP2_SR_SN_INTR_ENABLEr, IP2_SR_SN_INTR_STATUSr, 3408 _soc_gh2_ip2_sr_sn_ser_info}, 3409 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_GE8P0), SOC_BLK_PGW_GE8P, 0, 3410 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 3411 _soc_gh2_pgw_gport_ser_info}, 3412 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_GE8P1), SOC_BLK_PGW_GE8P, 1, 3413 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 3414 _soc_gh2_pgw_gport_ser_info}, 3415 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_GE8P2), SOC_BLK_PGW_GE8P, 2, 3416 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 3417 _soc_gh2_pgw_gport_ser_info}, 3418 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_GE0), SOC_BLK_PGW_GE, 0, 3419 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 3420 _soc_gh2_pgw_gport_ser_info}, 3421 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_GE1), SOC_BLK_PGW_GE, 1, 3422 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 3423 _soc_gh2_pgw_gport_ser_info}, 3424 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_XL0), SOC_BLK_XLPORT, 0, 3425 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 3426 _soc_gh2_pgw_xlport_ser_info}, 3427 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_XL1), SOC_BLK_XLPORT, 1, 3428 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 3429 _soc_gh2_pgw_xlport_ser_info}, 3430 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_XL2), SOC_BLK_XLPORT, 2, 3431 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 3432 _soc_gh2_pgw_xlport_ser_info}, 3433 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_XL3), SOC_BLK_XLPORT, 3, 3434 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 3435 _soc_gh2_pgw_xlport_ser_info}, 3436 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_XL4), SOC_BLK_XLPORT, 4, 3437 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 3438 _soc_gh2_pgw_xlport_ser_info}, 3439 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_XL5), SOC_BLK_XLPORT, 5, 3440 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 3441 _soc_gh2_pgw_xlport_ser_info}, 3442 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_XL6), SOC_BLK_XLPORT, 6, 3443 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 3444 _soc_gh2_pgw_xlport_ser_info}, 3445 {_GH2_X_TO_CMIC_INTR(_GH2_PAR_CL), SOC_BLK_PGW_CL, 0, 3446 PGW_CL_INTR_ENABLEr, PGW_CL_INTR_STATUSr, 3447 _soc_gh2_pgw_clport_ser_info}, 3448 { 0 } /* table terminator */ 3449 }; 3450 3451 STATIC int 3452 _soc_gh2_ser_process_is_per_port_mem( 3453 int unit, 3454 _soc_gh2_ser_info_type_t type) 3455 { 3456 if (type == _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP) { 3457 return TRUE; 3458 } 3459 return FALSE; 3460 } 3461 3462 /* Skip those MMU ports (memories) which logical ports don't exist */ 3463 STATIC int 3464 _soc_gh2_ser_process_skip_disabled_mmu_port( 3465 int unit, 3466 _soc_gh2_ser_info_t *info) 3467 { 3468 soc_info_t *si = &SOC_INFO(unit); 3469 int logical_port, phy_port, mmu_port; 3470 _soc_gh2_ser_reg_t *reg_ptr; 3471 int ptr; 3472 3473 if (NULL == info) { 3474 return TRUE; 3475 } 3476 3477 if (info->type == _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP && 3478 info->intr_status_reg_list != NULL) { 3479 reg_ptr = info->intr_status_reg_list; 3480 } else { 3481 return FALSE; 3482 } 3483 3484 switch (info->intr2_valid_reg) { 3485 case IPMC_GROUP_ERR_VLD_0r: 3486 { 3487 mmu_port = 0; 3488 break; 3489 } 3490 case IPMC_GROUP_ERR_VLD_1r: 3491 { 3492 mmu_port = 32; 3493 break; 3494 } 3495 case IPMC_GROUP_ERR_VLD_2r: 3496 { 3497 mmu_port = 64; 3498 break; 3499 } 3500 default: 3501 { 3502 return FALSE; 3503 } 3504 } 3505 for (ptr = 0; reg_ptr[ptr].reg != INVALIDr; ptr++) { 3506 if (reg_ptr[ptr].mem == info->mem) { 3507 break; 3508 } 3509 mmu_port++; 3510 } 3511 3512 /* MMU to Physical port, Physical to Logical port */ 3513 phy_port = si->port_m2p_mapping[mmu_port]; 3514 logical_port = si->port_p2l_mapping[phy_port]; 3515 3516 if (logical_port <= 1) { 3517 return TRUE; 3518 } 3519 return FALSE; 3520 } 3521 3522 STATIC int 3523 _soc_gh2_ser_mem_skip(int unit, _soc_gh2_ser_info_t *info) 3524 { 3525 int sku; 3526 int skip = FALSE; 3527 uint16 dev_id; 3528 uint8 rev_id; 3529 3530 if (NULL == info) { 3531 return TRUE; 3532 } 3533 3534 soc_cm_get_id(unit, &dev_id, &rev_id); 3535 switch (rev_id){ 3536 case (BCM56170_A0_REV_ID): 3537 if (info->sku_skip & _SOC_SER_SKIP_GH2_A0) { 3538 skip = TRUE; 3539 } 3540 break; 3541 case (BCM56170_B0_REV_ID): 3542 if (info->sku_skip & _SOC_SER_SKIP_GH2_B0) { 3543 skip = TRUE; 3544 } 3545 break; 3546 default: 3547 skip = FALSE; 3548 break; 3549 } 3550 3551 if (FALSE == skip) { 3552 (void)soc_gh2_chip_sku_get(unit, &sku); 3553 switch (sku){ 3554 case (SOC_GH2_SKU_HURRICANE3MG): 3555 if (info->sku_skip & _SOC_SER_SKIP_GH2_HR3MG) { 3556 skip = TRUE; 3557 } 3558 break; 3559 case (SOC_GH2_SKU_QUARTZ): 3560 if (info->sku_skip & _SOC_SER_SKIP_GH2_QUARTZ) { 3561 skip = TRUE; 3562 } 3563 break; 3564 default: 3565 skip = FALSE; 3566 break; 3567 } 3568 } 3569 /* skip invalid logical port mapped from mmu port */ 3570 if (_soc_gh2_ser_process_is_per_port_mem(unit, info->type)) { 3571 if (_soc_gh2_ser_process_skip_disabled_mmu_port(unit, info)) { 3572 skip = TRUE; 3573 } 3574 } 3575 return skip; 3576 } 3577 3578 STATIC int 3579 _soc_gh2_ser_2bit_ecc_mem(int unit, soc_mem_t memTable) 3580 { 3581 int is_2bit_ecc_mem = FALSE; 3582 /* FOR _SOC_PARITY_TYPE_ECC_DUAL */ 3583 switch (memTable){ 3584 case MMU_IPMC_GROUP_TBL2m: 3585 case MMU_IPMC_GROUP_TBL3m: 3586 case MMU_IPMC_GROUP_TBL4m: 3587 case MMU_IPMC_GROUP_TBL5m: 3588 case MMU_IPMC_GROUP_TBL6m: 3589 case MMU_IPMC_GROUP_TBL7m: 3590 case MMU_IPMC_GROUP_TBL8m: 3591 case MMU_IPMC_GROUP_TBL9m: 3592 case MMU_IPMC_GROUP_TBL10m: 3593 case MMU_IPMC_GROUP_TBL11m: 3594 case MMU_IPMC_GROUP_TBL12m: 3595 case MMU_IPMC_GROUP_TBL13m: 3596 case MMU_IPMC_GROUP_TBL14m: 3597 case MMU_IPMC_GROUP_TBL15m: 3598 case MMU_IPMC_GROUP_TBL16m: 3599 case MMU_IPMC_GROUP_TBL17m: 3600 case MMU_IPMC_GROUP_TBL18m: 3601 case MMU_IPMC_GROUP_TBL19m: 3602 case MMU_IPMC_GROUP_TBL20m: 3603 case MMU_IPMC_GROUP_TBL21m: 3604 case MMU_IPMC_GROUP_TBL22m: 3605 case MMU_IPMC_GROUP_TBL23m: 3606 case MMU_IPMC_GROUP_TBL24m: 3607 case MMU_IPMC_GROUP_TBL25m: 3608 case MMU_IPMC_GROUP_TBL26m: 3609 case MMU_IPMC_GROUP_TBL27m: 3610 case MMU_IPMC_GROUP_TBL28m: 3611 case MMU_IPMC_GROUP_TBL29m: 3612 case MMU_IPMC_GROUP_TBL30m: 3613 case MMU_IPMC_GROUP_TBL31m: 3614 case MMU_IPMC_GROUP_TBL32m: 3615 case MMU_IPMC_GROUP_TBL33m: 3616 case MMU_IPMC_GROUP_TBL34m: 3617 case MMU_IPMC_GROUP_TBL35m: 3618 case MMU_IPMC_GROUP_TBL36m: 3619 case MMU_IPMC_GROUP_TBL37m: 3620 case MMU_IPMC_GROUP_TBL38m: 3621 case MMU_IPMC_GROUP_TBL39m: 3622 case MMU_IPMC_GROUP_TBL40m: 3623 case MMU_IPMC_GROUP_TBL41m: 3624 case MMU_IPMC_GROUP_TBL42m: 3625 case MMU_IPMC_GROUP_TBL43m: 3626 case MMU_IPMC_GROUP_TBL44m: 3627 case MMU_IPMC_GROUP_TBL45m: 3628 case MMU_IPMC_GROUP_TBL46m: 3629 case MMU_IPMC_GROUP_TBL47m: 3630 case MMU_IPMC_GROUP_TBL48m: 3631 case MMU_IPMC_GROUP_TBL49m: 3632 case MMU_IPMC_GROUP_TBL50m: 3633 case MMU_IPMC_GROUP_TBL51m: 3634 case MMU_IPMC_GROUP_TBL52m: 3635 case MMU_IPMC_GROUP_TBL53m: 3636 case MMU_IPMC_GROUP_TBL54m: 3637 case MMU_IPMC_GROUP_TBL55m: 3638 case MMU_IPMC_GROUP_TBL56m: 3639 case MMU_IPMC_GROUP_TBL57m: 3640 case MMU_IPMC_GROUP_TBL58m: 3641 case MMU_IPMC_GROUP_TBL59m: 3642 case MMU_IPMC_GROUP_TBL60m: 3643 case MMU_IPMC_GROUP_TBL61m: 3644 case MMU_IPMC_GROUP_TBL62m: 3645 case MMU_IPMC_GROUP_TBL63m: 3646 case MMU_IPMC_GROUP_TBL64m: 3647 case MMU_IPMC_GROUP_TBL65m: 3648 case MMU_IPMC_VLAN_TBLm: 3649 case EGR_MTU_CHECKm: 3650 case EGR_STU_CHECKm: 3651 case SR_FLOW_EGR_COUNTER_CONTROLm: 3652 case SR_RX_FLOW_ID_POOLm: 3653 case SR_TX_FLOW_ID_POOLm: 3654 case SR_MAC_PROXY_PROFILEm: 3655 case SR_FLOW_ING_COUNTER_CONTROLm: 3656 case SR_RXm: 3657 case SR_TXm: 3658 case ING_MTU_CHECK_1m: 3659 case ING_MTU_CHECK_2m: 3660 case TAF_GATE_ID_LOOKUPm: 3661 is_2bit_ecc_mem = TRUE; 3662 break; 3663 default: 3664 is_2bit_ecc_mem = FALSE; 3665 break; 3666 }; 3667 return is_2bit_ecc_mem; 3668 } 3669 3670 STATIC void 3671 _soc_gh2_mem_parity_info(int unit, int block_info_idx, int pipe, 3672 soc_field_t field_enum, uint32 *minfo) 3673 { 3674 *minfo = (SOC_BLOCK2SCH(unit, block_info_idx) << SOC_ERROR_BLK_BP) 3675 | ((pipe & 0xff) << SOC_ERROR_PIPE_BP) 3676 | (field_enum & SOC_ERROR_FIELD_ENUM_MASK); 3677 } 3678 3679 #define _SOC_GH2_MMU_E2EFC_MAX 4 3680 static soc_reg_t e2efc_regs[_SOC_GH2_MMU_E2EFC_MAX] = { 3681 INVALIDr, 3682 E2EFC_CNT_SET_LIMITr, 3683 E2EFC_CNT_RESET_LIMITr, 3684 E2EFC_CNT_DISC_LIMITr 3685 }; 3686 3687 STATIC int 3688 _soc_gh2_ser_process_mmu_e2efc(int unit,_soc_gh2_ser_info_t *info_list, 3689 int info_index, int block_info_idx, char *msg) 3690 { 3691 _soc_gh2_ser_info_t *info; 3692 soc_reg_t status_reg; 3693 uint32 intr_status; 3694 int index, mem_id; 3695 uint32 minfo; 3696 _soc_ser_correct_info_t spci; 3697 3698 info = &info_list[info_index]; 3699 status_reg = info->intr_status_reg; 3700 SOC_IF_ERROR_RETURN 3701 (soc_reg32_get(unit, status_reg, REG_PORT_ANY, 0, 3702 &intr_status)); 3703 mem_id = soc_reg_field_get(unit, status_reg, 3704 intr_status, MEM_IDf); 3705 /* CHECK if the error is valid */ 3706 if (mem_id == 0) { 3707 LOG_ERROR(BSL_LS_SOC_COMMON, 3708 (BSL_META_U(unit, 3709 "%s: parity hardware inconsistency\n"), 3710 msg)); 3711 return SOC_E_NONE; 3712 } 3713 index = soc_reg_field_get(unit, status_reg, intr_status, ENTRY_INDEXf); 3714 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 3715 info->group_reg_status_field, &minfo); 3716 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3717 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 3718 index, minfo); 3719 LOG_ERROR(BSL_LS_SOC_COMMON, 3720 (BSL_META_U(unit, 3721 "unit %d MMU E2EFC entry idx %d : parity error\n"), 3722 unit, index)); 3723 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 3724 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 3725 spci.reg = e2efc_regs[mem_id]; 3726 spci.mem = INVALIDm; 3727 spci.blk_type = SOC_BLK_MMU; 3728 spci.index = index; 3729 spci.detect_time = sal_time_usecs(); 3730 (void)soc_ser_correction(unit, &spci); 3731 3732 return SOC_E_NONE; 3733 } 3734 3735 STATIC int 3736 _soc_gh2_ser_process_port_m2l_mapping( 3737 int unit, 3738 _soc_gh2_ser_info_t *info, 3739 uint32 valid_val, 3740 int *logical_port) 3741 { 3742 soc_info_t *si = &SOC_INFO(unit); 3743 int port, phy_port, mmu_port; 3744 3745 if (NULL == info || NULL == logical_port) { 3746 return SOC_E_PARAM; 3747 } 3748 3749 port = 0; 3750 while (!(valid_val & (0x1 << port))) { 3751 port++; 3752 } 3753 3754 if (info->intr2_valid_reg == IPMC_GROUP_ERR_VLD_0r) { 3755 mmu_port = port; 3756 } else if (info->intr2_valid_reg == IPMC_GROUP_ERR_VLD_1r) { 3757 mmu_port = port + 32; 3758 } else if (info->intr2_valid_reg == IPMC_GROUP_ERR_VLD_2r) { 3759 mmu_port = port + 64; 3760 } else { 3761 return SOC_E_NOT_FOUND; 3762 } 3763 /* MMU to Physical port, Physical to Logical port */ 3764 phy_port = si->port_m2p_mapping[mmu_port]; 3765 *logical_port = si->port_p2l_mapping[phy_port]; 3766 3767 if (*logical_port <= 1) { 3768 /* Handle the invalid logical port */ 3769 return SOC_E_UNAVAIL; 3770 } 3771 3772 return SOC_E_NONE; 3773 } 3774 3775 STATIC int 3776 _soc_gh2_ser_process_mmu_group_correct(int unit,_soc_gh2_ser_info_t *info_list, 3777 int info_index, int block_info_idx, 3778 char *msg, int report_type) 3779 { 3780 soc_error_t rv; 3781 _soc_gh2_ser_info_t *info; 3782 _soc_gh2_ser_reg_t *reg_ptr; 3783 soc_reg_t valid_reg = INVALIDr; 3784 soc_reg_t status_reg, clear_reg, multi_err_reg = INVALIDr; 3785 uint32 reg_val, valid_val = 0; 3786 int index, double_bit = 0, multiple = 0; 3787 uint32 minfo; 3788 int ptr; 3789 _soc_ser_correct_info_t spci; 3790 uint8 hw_inconsist = FALSE; 3791 int logical_port, port; 3792 3793 info = &info_list[info_index]; 3794 3795 if (info->intr2_valid_reg_list != NULL) { 3796 /* 3797 * IPMC_GROUP_ERR_VLD_0/1/2 binded to the same IPMCGROUPPARITYERROR 3798 * one of VLD_0/1/2 should be 1 or there's hardware inconsistency. 3799 */ 3800 reg_ptr = info->intr2_valid_reg_list; 3801 for (ptr = 0; reg_ptr[ptr].reg != INVALIDr; ptr++) { 3802 valid_reg = reg_ptr[ptr].reg; 3803 SOC_IF_ERROR_RETURN 3804 (soc_reg32_get(unit, valid_reg, REG_PORT_ANY, 0, 3805 ®_val)); 3806 valid_val = soc_reg_field_get(unit, valid_reg, reg_val, ERR_VALIDf); 3807 if (valid_val) { 3808 break; 3809 } 3810 } 3811 if (reg_ptr[ptr].reg == INVALIDr) { 3812 hw_inconsist = TRUE; 3813 } 3814 if (valid_reg != info->intr2_valid_reg) { 3815 return SOC_E_NONE; 3816 } 3817 } else { 3818 valid_reg = info->intr2_valid_reg; 3819 SOC_IF_ERROR_RETURN 3820 (soc_reg32_get(unit, valid_reg, REG_PORT_ANY, 0, 3821 ®_val)); 3822 valid_val = soc_reg_field_get(unit, valid_reg, reg_val, ERR_VALIDf); 3823 if (valid_val == 0) { 3824 hw_inconsist = TRUE; 3825 } 3826 } 3827 3828 if (TRUE == hw_inconsist) { 3829 LOG_ERROR(BSL_LS_SOC_COMMON, 3830 (BSL_META_U(unit, 3831 "%s: ecc hardware inconsistency" 3832 "Please check %s.\n"), 3833 msg, 3834 SOC_FIELD_NAME(unit, info->group_reg_status_field))); 3835 return SOC_E_NONE; 3836 } 3837 3838 if (SOC_REG_IS_VALID(unit, info->intr2_multi_err_reg) && 3839 soc_reg_field_valid(unit, info->intr2_multi_err_reg, MULTIPLE_ERRf)) { 3840 multi_err_reg = info->intr2_multi_err_reg; 3841 } else if (soc_reg_field_valid(unit, valid_reg, MULTIPLE_ERRf)) { 3842 multi_err_reg = valid_reg; 3843 } 3844 if (INVALIDr != multi_err_reg) { 3845 multiple = 3846 soc_reg_field_get(unit, multi_err_reg, reg_val, MULTIPLE_ERRf); 3847 } 3848 3849 if (info->intr_status_reg_list != NULL) { 3850 reg_ptr = info->intr_status_reg_list; 3851 } else { 3852 return SOC_E_INTERNAL; 3853 } 3854 3855 for (ptr = 0; reg_ptr[ptr].reg != INVALIDr; ptr++) { 3856 if (ptr > 31) { 3857 LOG_ERROR(BSL_LS_SOC_COMMON, 3858 (BSL_META_U(unit, 3859 "%s: left shifting by more" 3860 " than 31 bits, ptr = %d"), 3861 msg, ptr)); 3862 return SOC_E_INTERNAL; 3863 } 3864 if (!(valid_val & (0x1 << ptr))) { 3865 continue; 3866 } 3867 status_reg = reg_ptr[ptr].reg; 3868 3869 /* convert to mmu port for mmu memories */ 3870 if (_soc_gh2_ser_process_is_per_port_mem(unit, info->type)) { 3871 rv = _soc_gh2_ser_process_port_m2l_mapping( 3872 unit, info, valid_val, &logical_port); 3873 if (SOC_SUCCESS(rv)) { 3874 port = logical_port; 3875 } else { 3876 return rv; 3877 } 3878 } else { 3879 port = REG_PORT_ANY; 3880 } 3881 SOC_IF_ERROR_RETURN( 3882 soc_reg32_get(unit, status_reg, port, 0, ®_val)); 3883 3884 index = soc_reg_field_get(unit, status_reg, reg_val, ENTRY_INDEXf); 3885 3886 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 3887 spci.flags |= SOC_SER_SRC_MEM; 3888 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 3889 double_bit = 3890 soc_reg_field_get(unit, status_reg, reg_val, DOUBLE_BIT_ERRf); 3891 spci.double_bit = 1; 3892 } 3893 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 3894 info->group_reg_status_field, &minfo); 3895 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3896 report_type, 3897 index, minfo); 3898 3899 LOG_ERROR(BSL_LS_SOC_COMMON, 3900 (BSL_META_U(unit, 3901 "%s:%s:entry idx %d:%s parity error\n"), 3902 msg, reg_ptr[ptr].str, index, 3903 double_bit ? "double-bit" : "")); 3904 3905 if (multiple & (1 << ptr)) { 3906 LOG_ERROR(BSL_LS_SOC_COMMON, 3907 (BSL_META_U(unit, 3908 "%s:%s:has multiple parity errors\n"), 3909 msg, reg_ptr[ptr].str)); 3910 spci.flags |= SOC_SER_ERR_MULTI; 3911 } 3912 spci.reg = INVALIDr; 3913 spci.mem = reg_ptr[ptr].mem; 3914 spci.flags |= SOC_SER_REG_MEM_KNOWN; 3915 spci.blk_type = SOC_BLK_MMU; 3916 spci.detect_time = sal_time_usecs(); 3917 spci.index = index; 3918 (void)soc_ser_correction(unit, &spci); 3919 3920 } 3921 /* Clear interrupt status */ 3922 clear_reg = info->intr2_clr_reg; 3923 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, 3924 REG_PORT_ANY, 0, ®_val)); 3925 soc_reg_field_set(unit, clear_reg, ®_val, 3926 CLR_ERRf, valid_val); 3927 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, 3928 REG_PORT_ANY, 0, reg_val)); 3929 return SOC_E_NONE; 3930 } 3931 3932 STATIC int 3933 _soc_gh2_ser_process_mmu_group_ecc(int unit,_soc_gh2_ser_info_t *info_list, 3934 int info_index, int block_info_idx, char *msg) 3935 { 3936 _soc_gh2_ser_info_t *info; 3937 _soc_gh2_ser_reg_t *reg_ptr; 3938 soc_reg_t valid_reg, status_reg, clear_reg; 3939 uint32 reg_val, valid_val; 3940 int index, double_bit = 0, multiple; 3941 uint32 minfo; 3942 int ptr; 3943 3944 info = &info_list[info_index]; 3945 valid_reg = info->intr2_valid_reg; 3946 SOC_IF_ERROR_RETURN 3947 (soc_reg32_get(unit, valid_reg, REG_PORT_ANY, 0, 3948 ®_val)); 3949 valid_val = soc_reg_field_get(unit, valid_reg, reg_val, ERR_VALIDf); 3950 /* CBPPKTHDR_ERR */ 3951 multiple = 3952 soc_reg_field_get(unit, valid_reg, reg_val, MULTIPLE_ERRf); 3953 if (valid_val == 0) { 3954 LOG_ERROR(BSL_LS_SOC_COMMON, 3955 (BSL_META_U(unit, 3956 "%s: ecc hardware inconsistency\n"), 3957 msg)); 3958 return SOC_E_NONE; 3959 } 3960 3961 if (info->intr_status_reg_list != NULL) { 3962 reg_ptr = info->intr_status_reg_list; 3963 } else { 3964 return SOC_E_INTERNAL; 3965 } 3966 for (ptr = 0; reg_ptr[ptr].reg != INVALIDr; ptr++) { 3967 if (!(valid_val & (0x1 << ptr))) { 3968 continue; 3969 } 3970 status_reg = reg_ptr[ptr].reg; 3971 3972 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, status_reg, 3973 REG_PORT_ANY, 0, ®_val)); 3974 index = 3975 soc_reg_field_get(unit, status_reg, reg_val, ENTRY_INDEXf); 3976 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 3977 double_bit = 3978 soc_reg_field_get(unit, status_reg, reg_val, DOUBLE_BIT_ERRf); 3979 } 3980 3981 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 3982 info->group_reg_status_field, &minfo); 3983 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3984 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 3985 index, minfo); 3986 3987 LOG_ERROR(BSL_LS_SOC_COMMON, 3988 (BSL_META_U(unit, 3989 "%s %s entry %d %s ECC error\n"), 3990 msg, reg_ptr[ptr].str, index, 3991 double_bit ? "double-bit" : "")); 3992 if (multiple & (1 << ptr)) { 3993 LOG_ERROR(BSL_LS_SOC_COMMON, 3994 (BSL_META_U(unit, 3995 "%s (%s) has multiple ECC errors\n"), 3996 msg, reg_ptr[ptr].str)); 3997 } 3998 } 3999 /* Clear interrupt status */ 4000 clear_reg = info->intr2_clr_reg; 4001 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, 4002 REG_PORT_ANY, 0, ®_val)); 4003 soc_reg_field_set(unit, clear_reg, ®_val, 4004 CLR_ERRf, valid_val); 4005 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, 4006 REG_PORT_ANY, 0, reg_val)); 4007 return SOC_E_NONE; 4008 } 4009 4010 STATIC int 4011 _soc_gh2_ser_process_mmu_ecc2(int unit,_soc_gh2_ser_info_t *info_list, 4012 int info_index, int block_info_idx, char *msg) 4013 4014 { 4015 _soc_gh2_ser_info_t *info; 4016 soc_reg_t valid_reg, status_reg, clear_reg, merr_reg; 4017 uint32 reg_val, valid_val; 4018 int index, double_bit = 0, multiple = 0; 4019 uint32 minfo; 4020 int port; 4021 4022 info = &info_list[info_index]; 4023 4024 valid_reg = info->intr2_valid_reg; 4025 SOC_IF_ERROR_RETURN 4026 (soc_reg32_get(unit, valid_reg, REG_PORT_ANY, 0, 4027 ®_val)); 4028 valid_val = soc_reg_field_get(unit, valid_reg, reg_val, ERR_VALIDf); 4029 if (valid_val == 0) { 4030 LOG_ERROR(BSL_LS_SOC_COMMON, 4031 (BSL_META_U(unit, 4032 "%s: ecc hardware inconsistency\n"), 4033 msg)); 4034 return SOC_E_NONE; 4035 } 4036 port = 0; 4037 while (!(valid_val & (0x1 << port))) { 4038 port++; 4039 } 4040 if (info->intr_status_reg != INVALIDr){ 4041 status_reg = info->intr_status_reg; 4042 } else { 4043 return SOC_E_INTERNAL; 4044 } 4045 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, status_reg, 4046 port, 0, ®_val)); 4047 index = 4048 soc_reg_field_get(unit, status_reg, reg_val, ENTRY_INDEXf); 4049 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 4050 double_bit = 4051 soc_reg_field_get(unit, status_reg, reg_val, DOUBLE_BIT_ERRf); 4052 } 4053 4054 if (info->intr2_multi_err_reg != INVALIDr) { 4055 merr_reg = info->intr2_multi_err_reg; 4056 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, merr_reg, 4057 port, 0, ®_val)); 4058 multiple = 4059 soc_reg_field_get(unit, merr_reg, reg_val, MULTIPLE_ERRf); 4060 } 4061 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 4062 info->group_reg_status_field, &minfo); 4063 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4064 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 4065 index, minfo); 4066 LOG_ERROR(BSL_LS_SOC_COMMON, 4067 (BSL_META_U(unit, 4068 "%s port %d entry %d %s ECC error\n"), 4069 msg, port, index, double_bit ? "double-bit" : "")); 4070 if (multiple) { 4071 LOG_ERROR(BSL_LS_SOC_COMMON, 4072 (BSL_META_U(unit, 4073 "%s has multiple ECC errors\n"), 4074 msg)); 4075 } 4076 /* Clear interrupt status */ 4077 clear_reg = info->intr2_clr_reg; 4078 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, 4079 REG_PORT_ANY, 0, ®_val)); 4080 soc_reg_field_set(unit, clear_reg, ®_val, 4081 CLR_ERRf, valid_val); 4082 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, 4083 REG_PORT_ANY, 0, reg_val)); 4084 return SOC_E_NONE; 4085 } 4086 4087 STATIC int 4088 _soc_gh2_ser_process_mmu_ecc(int unit,_soc_gh2_ser_info_t *info_list, 4089 int info_index, int block_info_idx, char *msg, 4090 int correctable) 4091 { 4092 _soc_gh2_ser_info_t *info; 4093 soc_reg_t status_reg; 4094 uint32 intr_status; 4095 int index, double_bit = 0; 4096 uint32 minfo; 4097 _soc_ser_correct_info_t spci; 4098 4099 info = &info_list[info_index]; 4100 status_reg = info->intr_status_reg; 4101 SOC_IF_ERROR_RETURN 4102 (soc_reg32_get(unit, status_reg, REG_PORT_ANY, 0, 4103 &intr_status)); 4104 index = soc_reg_field_get(unit, status_reg, intr_status, ENTRY_INDEXf); 4105 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 4106 double_bit = soc_reg_field_get(unit, status_reg, 4107 intr_status, DOUBLE_BIT_ERRf); 4108 } 4109 4110 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 4111 info->group_reg_status_field, &minfo); 4112 4113 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4114 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 4115 index, minfo); 4116 LOG_ERROR(BSL_LS_SOC_COMMON, 4117 (BSL_META_U(unit, 4118 "%s : entry idx %d : %s ECC error\n"), 4119 msg, index, double_bit ? "double-bit" : "")); 4120 if (correctable) { 4121 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 4122 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 4123 spci.reg = INVALIDr; 4124 spci.mem = info->mem; 4125 spci.blk_type = SOC_BLK_MMU; 4126 spci.index = index; 4127 (void)soc_ser_correction(unit, &spci); 4128 } 4129 return SOC_E_NONE; 4130 } 4131 4132 STATIC int 4133 _soc_gh2_ser_process_mmu_err(int unit, int block_info_idx, 4134 soc_reg_t group_reg, 4135 soc_reg_t clear_reg, 4136 _soc_gh2_ser_info_t *info_list) 4137 { 4138 soc_reg_t grp_reg, clr_reg; 4139 uint32 rval, group_rval; 4140 int rv = SOC_E_NONE; 4141 int info_index; 4142 _soc_gh2_ser_info_t *info; 4143 char *mem_str; 4144 4145 if (info_list->type == _SOC_PARITY_TYPE_MMU_SER){ 4146 grp_reg = info_list->intr_status_reg; 4147 clr_reg = info_list->intr_clr_reg; 4148 4149 4150 rv = _soc_gh2_ser_process_mmu_err(unit, block_info_idx, 4151 grp_reg, 4152 clr_reg, 4153 info_list->info); 4154 if (SOC_FAILURE(rv)) { 4155 LOG_CLI((BSL_META_U(unit, 4156 "process_mmu_err: Error processing %s !!\n"), 4157 info_list->mem_str)); 4158 return rv; 4159 } 4160 return rv; 4161 } 4162 for (info_index = 0; ; info_index++) { 4163 info = &info_list[info_index]; 4164 if (info->type == _SOC_PARITY_TYPE_NONE) { 4165 /* End of table */ 4166 break; 4167 } 4168 SOC_IF_ERROR_RETURN 4169 (soc_reg32_get(unit, group_reg, REG_PORT_ANY, 0, 4170 &group_rval)); 4171 if (!soc_reg_field_get(unit, group_reg, group_rval, 4172 info->group_reg_status_field)) { 4173 continue; 4174 } 4175 4176 if (info->mem_str) { 4177 mem_str = info->mem_str; 4178 } else if (info->mem != INVALIDm) { 4179 mem_str = SOC_MEM_NAME(unit, info->mem); 4180 } else { 4181 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 4182 } 4183 4184 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4185 (BSL_META_U(unit, 4186 "process_mmu_err %s analysis\n"), 4187 mem_str)); 4188 switch (info->type) { 4189 case _SOC_PARITY_TYPE_MMU_ECC: 4190 SOC_IF_ERROR_RETURN( 4191 _soc_gh2_ser_process_mmu_ecc(unit, info_list, info_index, 4192 block_info_idx, mem_str, 0)); 4193 break; 4194 case _SOC_PARITY_TYPE_MMU_ECC_XQ: 4195 SOC_IF_ERROR_RETURN( 4196 _soc_gh2_ser_process_mmu_ecc2(unit, info_list, info_index, 4197 block_info_idx, mem_str)); 4198 break; 4199 case _SOC_PARITY_TYPE_MMU_ECC_CBPH: 4200 SOC_IF_ERROR_RETURN( 4201 _soc_gh2_ser_process_mmu_group_ecc(unit, info_list, info_index, 4202 block_info_idx, mem_str)); 4203 break; 4204 case _SOC_PARITY_TYPE_MMU_PAR_E2EFC: 4205 SOC_IF_ERROR_RETURN( 4206 _soc_gh2_ser_process_mmu_e2efc(unit, info_list, info_index, 4207 block_info_idx, mem_str)); 4208 break; 4209 case _SOC_PARITY_TYPE_MMU_PAR_WRED: 4210 SOC_IF_ERROR_RETURN(_soc_gh2_ser_process_mmu_group_correct( 4211 unit, info_list, info_index, 4212 block_info_idx, mem_str, 4213 SOC_SWITCH_EVENT_DATA_ERROR_PARITY)); 4214 break; 4215 case _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP: 4216 SOC_IF_ERROR_RETURN(_soc_gh2_ser_process_mmu_group_correct( 4217 unit, info_list, info_index, 4218 block_info_idx, mem_str, 4219 SOC_SWITCH_EVENT_DATA_ERROR_ECC)); 4220 break; 4221 case _SOC_PARITY_TYPE_MMU_ECC_IPMCVLAN: 4222 SOC_IF_ERROR_RETURN( 4223 _soc_gh2_ser_process_mmu_ecc(unit, info_list, info_index, 4224 block_info_idx, mem_str, 1)); 4225 break; 4226 default: 4227 break; 4228 } 4229 /* clear interrupt */ 4230 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, REG_PORT_ANY, 4231 0, &rval)); 4232 soc_reg_field_set(unit, clear_reg, &rval, 4233 info->intr_clr_field, 1); 4234 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, REG_PORT_ANY, 4235 0, rval)); 4236 4237 } 4238 return SOC_E_NONE; 4239 } 4240 4241 STATIC int 4242 _soc_gh2_ser_process_parity_hash(int unit, int block_info_idx, int port, 4243 _soc_gh2_ser_info_t *info, 4244 char *mem_str, 4245 soc_block_t blocktype) 4246 { 4247 _soc_gh2_ser_reg_t reg_entry[2], *reg_ptr; 4248 soc_reg_t reg; 4249 _soc_ser_correct_info_t spci; 4250 uint32 bitmap = 0, len = 0, bits, rval, minfo; 4251 uint32 multiple = 0, bucket_index = 0, entry_idx, idx, has_error; 4252 char *mem_str_ptr; 4253 soc_field_t bitmapf; 4254 4255 if (info->intr_status_reg != INVALIDr) { 4256 reg_entry[0].reg = info->intr_status_reg; 4257 reg_entry[0].str = NULL; 4258 reg_entry[1].reg = INVALIDr; 4259 reg_ptr = reg_entry; 4260 } else if (info->intr_status_reg_list != NULL) { 4261 reg_ptr = info->intr_status_reg_list; 4262 } else { 4263 return SOC_E_NONE; 4264 } 4265 4266 has_error = FALSE; 4267 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 4268 reg = reg_ptr[idx].reg; 4269 mem_str_ptr = (reg_ptr[idx].str != NULL) ? 4270 reg_ptr[idx].str : mem_str; 4271 sal_memset(&spci, 0, sizeof(spci)); 4272 4273 SOC_IF_ERROR_RETURN 4274 (soc_reg32_get(unit, reg, port, 0, &rval)); 4275 4276 if (soc_reg_field_valid(unit, reg, BUCKET_IDXf)) { 4277 bucket_index = 4278 soc_reg_field_get(unit, reg, rval, BUCKET_IDXf); 4279 multiple = 4280 soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 4281 bitmap = 4282 soc_reg_field_get(unit, reg, rval, PARITY_ERR_BMf); 4283 len = soc_reg_field_length(unit, reg, PARITY_ERR_BMf); 4284 } else if (soc_reg_field_valid(unit, reg, BUCKET_IDX_0f)) { 4285 bucket_index = 4286 soc_reg_field_get(unit, reg, rval, BUCKET_IDX_0f); 4287 multiple = 4288 soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_0f); 4289 if (SR_L2_ENTRYm == info->mem) { 4290 bitmapf = SR_PARITY_ERR_BM_0f; 4291 } else { 4292 bitmapf = PARITY_ERR_BM_0f; 4293 } 4294 bitmap = 4295 soc_reg_field_get(unit, reg, rval, bitmapf); 4296 len = soc_reg_field_length(unit, reg, bitmapf); 4297 } else if (soc_reg_field_valid(unit, reg, BUCKET_IDX_1f)) { 4298 bucket_index = 4299 soc_reg_field_get(unit, reg, rval, BUCKET_IDX_1f); 4300 multiple = 4301 soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_1f); 4302 if (SR_L2_ENTRYm == info->mem) { 4303 bitmapf = SR_PARITY_ERR_BM_1f; 4304 } else { 4305 bitmapf = PARITY_ERR_BM_1f; 4306 } 4307 bitmap = 4308 soc_reg_field_get(unit, reg, rval, bitmapf); 4309 len = soc_reg_field_length(unit, reg, bitmapf); 4310 } 4311 if (bitmap != 0) { 4312 for (bits = 0; bits < len; bits++) { 4313 if (bitmap & (1 << bits)) { 4314 has_error = TRUE; 4315 break; 4316 } 4317 } 4318 entry_idx = bucket_index * len * 2 + bits + (idx * len); 4319 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 4320 info->group_reg_status_field, &minfo); 4321 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4322 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 4323 entry_idx, minfo); 4324 LOG_ERROR(BSL_LS_SOC_COMMON, 4325 (BSL_META_U(unit, 4326 "unit %d %s : entry idx %d : parity error\n"), 4327 unit, mem_str_ptr, entry_idx)); 4328 if (multiple) { 4329 LOG_ERROR(BSL_LS_SOC_COMMON, 4330 (BSL_META_U(unit, 4331 "unit %d %s has multiple parity errors\n"), 4332 unit, mem_str_ptr)); 4333 } 4334 spci.flags = SOC_SER_SRC_MEM; 4335 if (multiple) { 4336 spci.flags |= SOC_SER_ERR_MULTI; 4337 } 4338 spci.double_bit = 0; 4339 spci.reg = INVALIDr; 4340 spci.mem = info->mem; 4341 spci.blk_type = blocktype; 4342 spci.index = entry_idx; 4343 spci.detect_time = sal_time_usecs(); 4344 spci.pipe_num = 0; 4345 spci.acc_type = -1; 4346 spci.addr = (spci.mem != INVALIDm)? SOC_MEM_BASE(unit, spci.mem) : 0; 4347 if (spci.mem != INVALIDm) { 4348 spci.flags |= SOC_SER_REG_MEM_KNOWN; 4349 (void)soc_ser_correction(unit, &spci); 4350 } 4351 /* Clear parity status */ 4352 SOC_IF_ERROR_RETURN 4353 (soc_reg32_set(unit, reg, port, 0, 0)); 4354 } 4355 } 4356 if (!has_error) { 4357 LOG_VERBOSE(BSL_LS_SOC_SER, 4358 (BSL_META_U(unit, 4359 "unit %d %s parity hardware inconsistency\n"), 4360 unit, mem_str)); 4361 } 4362 4363 return SOC_E_NONE; 4364 } 4365 4366 STATIC int 4367 _soc_gh2_ser_process_parity_ecc(int unit, int block_info_idx, int port, 4368 _soc_gh2_ser_info_t *info, 4369 char *mem_str, 4370 soc_block_t blocktype, int parity_type) 4371 { 4372 _soc_gh2_ser_reg_t reg_entry[2], *reg_ptr; 4373 soc_reg_t reg; 4374 soc_field_t parity_error_field = PARITY_ERRf; 4375 _soc_ser_correct_info_t spci; 4376 uint32 rval, minfo, double_bit = 0; 4377 uint32 multiple, entry_idx, idx, has_error; 4378 char *mem_str_ptr; 4379 int report_type = SOC_SWITCH_EVENT_DATA_ERROR_PARITY; 4380 4381 if (info->intr_status_reg != INVALIDr) { 4382 reg_entry[0].reg = info->intr_status_reg; 4383 reg_entry[0].str = NULL; 4384 reg_entry[1].reg = INVALIDr; 4385 reg_ptr = reg_entry; 4386 } else if (info->intr_status_reg_list != NULL) { 4387 reg_ptr = info->intr_status_reg_list; 4388 } else { 4389 return SOC_E_NONE; 4390 } 4391 if (INVALIDf != info->intr_status_field) { 4392 parity_error_field = info->intr_status_field; 4393 } 4394 4395 has_error = FALSE; 4396 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 4397 reg = reg_ptr[idx].reg; 4398 mem_str_ptr = (reg_ptr[idx].str != NULL) ? 4399 reg_ptr[idx].str : mem_str; 4400 sal_memset(&spci, 0, sizeof(spci)); 4401 4402 SOC_IF_ERROR_RETURN 4403 (soc_reg32_get(unit, reg, port, 0, &rval)); 4404 if (soc_reg_field_get(unit, reg, rval, parity_error_field)) { 4405 has_error = TRUE; 4406 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 4407 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 4408 4409 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 4410 info->group_reg_status_field, &minfo); 4411 if (parity_type == _SOC_PARITY_TYPE_ECC_DUAL) { 4412 report_type = SOC_SWITCH_EVENT_DATA_ERROR_ECC; 4413 double_bit = 1; 4414 } else if (parity_type == _SOC_PARITY_TYPE_ECC) { 4415 report_type = SOC_SWITCH_EVENT_DATA_ERROR_ECC; 4416 if (soc_reg_field_valid(unit, reg, DOUBLE_BIT_ERRf)) { 4417 double_bit = 4418 soc_reg_field_get(unit, reg, rval, DOUBLE_BIT_ERRf); 4419 } else { 4420 return SOC_E_INTERNAL; 4421 } 4422 } 4423 4424 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4425 report_type, 4426 entry_idx, minfo); 4427 LOG_ERROR(BSL_LS_SOC_COMMON, 4428 (BSL_META_U(unit, 4429 "unit %d %s entry %d %s error\n"), 4430 unit, mem_str_ptr, entry_idx, 4431 ((parity_type == _SOC_PARITY_TYPE_ECC || 4432 parity_type == _SOC_PARITY_TYPE_ECC_DUAL) ? 4433 "ecc" : "parity"))); 4434 if (multiple) { 4435 LOG_ERROR(BSL_LS_SOC_COMMON, 4436 (BSL_META_U(unit, 4437 "unit %d %s has multiple %s errors\n"), 4438 unit, mem_str_ptr, 4439 ((parity_type == _SOC_PARITY_TYPE_ECC || 4440 parity_type == _SOC_PARITY_TYPE_ECC_DUAL) ? 4441 "ecc" : "parity"))); 4442 } 4443 spci.flags = SOC_SER_SRC_MEM; 4444 if (multiple) { 4445 spci.flags |= SOC_SER_ERR_MULTI; 4446 } 4447 if (double_bit) { 4448 spci.double_bit = 1; 4449 } 4450 spci.reg = INVALIDr; 4451 spci.mem = info->mem; 4452 spci.blk_type = blocktype; 4453 spci.index = entry_idx; 4454 spci.detect_time = sal_time_usecs(); 4455 spci.pipe_num = 0; 4456 spci.acc_type = -1; 4457 spci.addr = (spci.mem != INVALIDm)? SOC_MEM_BASE(unit, spci.mem) : 0; 4458 if (spci.mem != INVALIDm) { 4459 spci.flags |= SOC_SER_REG_MEM_KNOWN; 4460 (void)soc_ser_correction(unit, &spci); 4461 } 4462 /* Clear parity status */ 4463 SOC_IF_ERROR_RETURN 4464 (soc_reg32_set(unit, reg, port, 0, 0)); 4465 } 4466 } 4467 if (!has_error) { 4468 LOG_VERBOSE(BSL_LS_SOC_SER, 4469 (BSL_META_U(unit, 4470 "unit %d %s parity hardware inconsistency\n"), 4471 unit, mem_str)); 4472 } 4473 4474 return SOC_E_NONE; 4475 4476 } 4477 4478 #define _SOC_GH2_DBG_COUNTER_MAX (12) 4479 static soc_reg_t dbgc_regs[_SOC_GH2_DBG_COUNTER_MAX] = { 4480 TDBGC0r, TDBGC1r, TDBGC2r, TDBGC3r, 4481 TDBGC4r, TDBGC5r, TDBGC6r, TDBGC7r, 4482 TDBGC8r, TDBGC9r, TDBGC10r, TDBGC11r 4483 }; 4484 4485 STATIC int 4486 _soc_gh2_ser_process_parity_counter(int unit, int block_info_idx, int port, 4487 _soc_gh2_ser_info_t *info, 4488 char *mem_str, 4489 soc_block_t blocktype) 4490 { 4491 soc_reg_t reg, counter_reg; 4492 uint32 rval, minfo; 4493 uint32 multiple, counter_idx, port_idx; 4494 char *counter_name; 4495 _soc_ser_correct_info_t spci; 4496 soc_field_t parity_error_field = PARITY_ERRf; 4497 4498 reg = info->intr_status_reg; 4499 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, 4500 port, 0, &rval)); 4501 if (soc_reg_field_get(unit, reg, rval, parity_error_field)) { 4502 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 4503 counter_idx = soc_reg_field_get(unit, reg, rval, COUNTER_IDXf); 4504 port_idx = soc_reg_field_get(unit, reg, rval, PORT_IDXf); 4505 4506 counter_reg = dbgc_regs[counter_idx]; 4507 _soc_gh2_mem_parity_info(unit, block_info_idx, 0, 4508 info->group_reg_status_field, &minfo); 4509 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4510 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 4511 counter_idx, minfo); 4512 counter_name = SOC_REG_NAME(unit, counter_reg); 4513 LOG_ERROR(BSL_LS_SOC_COMMON, 4514 (BSL_META_U(unit, 4515 "EGR STAT COUNTER port %d %s" 4516 " : parity error\n"), 4517 port_idx, counter_name)); 4518 4519 sal_memset(&spci, 0, sizeof(spci)); 4520 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 4521 spci.mem = INVALIDm; 4522 spci.port = port_idx; 4523 spci.index = -1; 4524 spci.reg = counter_reg; 4525 spci.blk_type = blocktype; 4526 (void)soc_ser_correction(unit, &spci); 4527 if (multiple) { 4528 LOG_ERROR(BSL_LS_SOC_COMMON, 4529 (BSL_META_U(unit, 4530 "EGR STAT COUNTER has " 4531 "multiple parity errors\n"))); 4532 } 4533 }else { 4534 LOG_ERROR(BSL_LS_SOC_COMMON, 4535 (BSL_META_U(unit, 4536 "EGR STAT COUNTER parity " 4537 "hardware inconsistency\n"))); 4538 } 4539 /* Clear parity status */ 4540 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 4541 4542 return SOC_E_NONE; 4543 } 4544 4545 STATIC int 4546 _soc_gh2_process_ser(int unit, soc_block_t block_info_idx, int inst, 4547 int port, soc_reg_t group_reg, uint64 group_rval, 4548 _soc_gh2_ser_info_t *info_list, 4549 soc_block_t blocktype) 4550 4551 { 4552 _soc_gh2_ser_info_t *info; 4553 int info_index; 4554 char *mem_str; 4555 4556 for (info_index = 0; ; info_index++) { 4557 info = &info_list[info_index]; 4558 if (info->type == _SOC_PARITY_TYPE_NONE) { 4559 /* End of table */ 4560 break; 4561 } 4562 if (_soc_gh2_ser_mem_skip(unit, info)) { 4563 continue; 4564 } 4565 if (group_reg != INVALIDr) { 4566 /* Check status for the info entry in the group register */ 4567 /* for SOC_BLK_MMU, group_reg is INVALIDr */ 4568 if (!soc_reg_field_valid(unit, group_reg, 4569 info->group_reg_status_field)) { 4570 continue; 4571 } 4572 if (!soc_reg64_field32_get(unit, group_reg, group_rval, 4573 info->group_reg_status_field)) { 4574 continue; 4575 } 4576 } 4577 if (info->mem_str) { 4578 mem_str = info->mem_str; 4579 } else if (info->mem != INVALIDm) { 4580 mem_str = SOC_MEM_NAME(unit, info->mem); 4581 } else { 4582 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 4583 } 4584 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4585 (BSL_META_U(unit, 4586 "unit %d _soc_gh2_process_ser %s analysis\n"), 4587 unit, mem_str)); 4588 4589 /* Handle different parity error reporting style */ 4590 switch (info->type) { 4591 case _SOC_PARITY_TYPE_MMU_SER: 4592 SOC_IF_ERROR_RETURN 4593 (_soc_gh2_ser_process_mmu_err(unit, block_info_idx, 4594 INVALIDr, INVALIDr, 4595 info)); 4596 /* info points to _soc_gh2_mmu_top_ser_info[0] */ 4597 break; 4598 case _SOC_PARITY_TYPE_PARITY: 4599 SOC_IF_ERROR_RETURN 4600 (_soc_gh2_ser_process_parity_ecc(unit, block_info_idx, port, 4601 info, mem_str, blocktype, 4602 info->type)); 4603 break; 4604 case _SOC_PARITY_TYPE_PARITY_DUAL: 4605 SOC_IF_ERROR_RETURN 4606 (_soc_gh2_ser_process_parity_hash(unit, block_info_idx, port, 4607 info, mem_str, blocktype)); 4608 break; 4609 case _SOC_PARITY_TYPE_ECC: 4610 case _SOC_PARITY_TYPE_ECC_DUAL: 4611 SOC_IF_ERROR_RETURN 4612 (_soc_gh2_ser_process_parity_ecc(unit, block_info_idx, port, 4613 info, mem_str, blocktype, 4614 info->type)); 4615 break; 4616 case _SOC_PARITY_TYPE_COUNTER: 4617 SOC_IF_ERROR_RETURN 4618 (_soc_gh2_ser_process_parity_counter(unit, block_info_idx, port, 4619 info, mem_str, blocktype)); 4620 break; 4621 4622 default: 4623 break; 4624 } 4625 4626 } 4627 4628 return SOC_E_NONE; 4629 } 4630 4631 int 4632 soc_gh2_ser_process_all(int unit, uint32 cmic_rval) 4633 { 4634 uint8 rbi; 4635 _soc_gh2_ser_route_block_t *rb; 4636 uint32 cmic_bit; 4637 int port = REG_PORT_ANY; 4638 int block_info_idx; 4639 uint64 rb_rval64, rb_enable64, temp64; 4640 soc_reg_t tmp_reg; 4641 4642 COMPILER_64_ZERO(rb_rval64); 4643 COMPILER_64_ZERO(rb_enable64); 4644 4645 if (cmic_rval == 0) { 4646 return SOC_E_NONE; 4647 } 4648 /* Loop through each place-and-route block entry */ 4649 for (rbi = 0; ; rbi++) { 4650 rb = &_soc_gh2_ser_route_blocks[rbi]; 4651 cmic_bit = rb->cmic_bit; 4652 if (cmic_bit == 0) { 4653 /* End of table */ 4654 break; 4655 } 4656 if (!(cmic_rval & cmic_bit)) { 4657 /* Indicated bit not asserted for the route block */ 4658 continue; 4659 } 4660 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 4661 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 4662 port = SOC_BLOCK_PORT(unit, block_info_idx); 4663 break; 4664 } 4665 } 4666 if (rb->enable_reg != INVALIDr) { 4667 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 4668 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 4669 /* This port block is not configured */ 4670 LOG_ERROR(BSL_LS_SOC_COMMON, 4671 (BSL_META_U(unit, 4672 "unit %d SER error on disabled " 4673 "port block %d !!\n"), 4674 unit, block_info_idx)); 4675 continue; 4676 } 4677 SOC_IF_ERROR_RETURN(soc_reg_get(unit, rb->enable_reg, 4678 port, 0, &rb_enable64)); 4679 } 4680 /* Read per route block parity status register */ 4681 if (rb->status_reg != INVALIDr) { 4682 tmp_reg = rb->status_reg; 4683 SOC_IF_ERROR_RETURN( 4684 soc_reg_get(unit, tmp_reg, port, 0, &rb_rval64)); 4685 if (COMPILER_64_IS_ZERO(rb_rval64)) { 4686 continue; 4687 } 4688 if (!COMPILER_64_IS_ZERO(rb_enable64)) { 4689 /* mask out the disabled status */ 4690 COMPILER_64_AND(rb_rval64, rb_enable64); 4691 if (COMPILER_64_IS_ZERO(rb_rval64)){ 4692 continue; 4693 } 4694 } 4695 } 4696 4697 /* ser process per type */ 4698 SOC_IF_ERROR_RETURN( 4699 _soc_gh2_process_ser(unit, block_info_idx, rb->id, 4700 port, rb->status_reg, rb_rval64, 4701 rb->info, rb->blocktype)); 4702 4703 /* Enable interrupt */ 4704 if (rb->enable_reg != INVALIDr) { 4705 SOC_IF_ERROR_RETURN(soc_reg_get(unit, rb->enable_reg, 4706 port, 0, &rb_enable64)); 4707 COMPILER_64_SET(temp64, COMPILER_64_HI(rb_rval64), 4708 COMPILER_64_LO(rb_rval64)); 4709 COMPILER_64_NOT(temp64); 4710 COMPILER_64_AND(rb_enable64, temp64); 4711 SOC_IF_ERROR_RETURN(soc_reg_set(unit, rb->enable_reg, 4712 port, 0, rb_enable64)); 4713 COMPILER_64_OR(rb_enable64, rb_rval64); 4714 SOC_IF_ERROR_RETURN(soc_reg_set(unit, rb->enable_reg, 4715 port, 0, rb_enable64)); 4716 } 4717 }/* for rbi */ 4718 return SOC_E_NONE; 4719 } 4720 4721 /* parity enable for mmu block */ 4722 STATIC int 4723 _soc_gh2_mmu_ser_config(int unit, _soc_gh2_ser_info_t *info_list, 4724 soc_reg_t group_reg, soc_mem_t mem, 4725 int enable) 4726 { 4727 _soc_gh2_ser_info_t *info; 4728 int info_index, rv; 4729 uint32 rval; 4730 4731 rv = SOC_E_NOT_FOUND; 4732 SOC_IF_ERROR_RETURN 4733 (soc_reg32_get(unit, group_reg, REG_PORT_ANY, 0, 4734 &rval)); 4735 /* Loop through each info entry in the list */ 4736 for (info_index = 0; ; info_index++) { 4737 info = &info_list[info_index]; 4738 if (info->type == _SOC_PARITY_TYPE_NONE) { 4739 /* End of table */ 4740 break; 4741 } 4742 if ((mem != INVALIDm) && (mem != info->mem)) { 4743 continue; 4744 } 4745 rv = SOC_E_NONE; 4746 soc_reg_field_set(unit, group_reg, &rval, 4747 info->group_reg_enable_field, 4748 enable ? 1 : 0); 4749 4750 SOC_IF_ERROR_RETURN 4751 (soc_reg32_set(unit, group_reg, REG_PORT_ANY, 0, rval)); 4752 } 4753 return rv; 4754 } 4755 /* parity enable for xlport */ 4756 STATIC int 4757 _soc_gh2_pm_ser_config(int unit, _soc_gh2_ser_info_t *info_list, 4758 int block_info_idx, soc_reg_t group_reg, 4759 int enable) 4760 { 4761 _soc_gh2_ser_info_t *info; 4762 int info_index, port; 4763 uint32 rval, group_rval; 4764 soc_reg_t reg; 4765 4766 4767 port = SOC_BLOCK_PORT(unit, block_info_idx); 4768 SOC_IF_ERROR_RETURN 4769 (soc_reg32_get(unit, group_reg, REG_PORT_ANY, 0, 4770 &group_rval)); 4771 /* Loop through each info entry in the list */ 4772 for (info_index = 0; ; info_index++) { 4773 info = &info_list[info_index]; 4774 if (info->type == _SOC_PARITY_TYPE_NONE) { 4775 /* End of table */ 4776 break; 4777 } 4778 reg = info->enable_reg; 4779 SOC_IF_ERROR_RETURN 4780 (soc_reg32_get(unit, reg, port, 0, &rval)); 4781 soc_reg_field_set(unit, reg, &rval, info->enable_field, 4782 enable ? 1 : 0); 4783 SOC_IF_ERROR_RETURN 4784 (soc_reg32_set(unit, reg, port, 0, rval)); 4785 4786 soc_reg_field_set(unit, group_reg, &group_rval, 4787 info->group_reg_enable_field, 4788 enable ? 1 : 0); 4789 4790 SOC_IF_ERROR_RETURN 4791 (soc_reg32_set(unit, group_reg, port, 0, group_rval)); 4792 } 4793 return SOC_E_NONE; 4794 } 4795 4796 4797 STATIC int 4798 _soc_gh2_ser_enable_info(int unit, int block_info_idx, int inst, int port, 4799 soc_reg_t group_reg, uint64 *group_rval, 4800 _soc_gh2_ser_info_t *info_list, 4801 soc_mem_t mem, int enable) 4802 { 4803 _soc_gh2_ser_info_t *info; 4804 int info_index, rv; 4805 soc_reg_t reg; 4806 uint64 rval64; 4807 4808 rv = SOC_E_NOT_FOUND; 4809 4810 /* Loop through each info entry in the list */ 4811 for (info_index = 0; ; info_index++) { 4812 info = &info_list[info_index]; 4813 if (info->type == _SOC_PARITY_TYPE_NONE) { 4814 /* End of table */ 4815 break; 4816 } 4817 if (_soc_gh2_ser_mem_skip(unit, info)) { 4818 continue; 4819 } 4820 if ((mem != INVALIDm) && (mem != info->mem)) { 4821 continue; 4822 } 4823 rv = SOC_E_NONE; 4824 if (group_reg != INVALIDr && info->group_reg_enable_field != INVALIDf) { 4825 if (!soc_reg_field_valid(unit, group_reg, 4826 info->group_reg_enable_field)) { 4827 continue; 4828 } 4829 /* Enable the info entry in the group register */ 4830 soc_reg64_field32_set(unit, group_reg, group_rval, 4831 info->group_reg_enable_field, enable ? 1 : 0); 4832 } 4833 /* Handle different parity error reporting style */ 4834 switch (info->type) { 4835 case _SOC_PARITY_TYPE_PORT_XL: 4836 /* only ecc in pm, don't need mem information */ 4837 rv =_soc_gh2_pm_ser_config(unit, info->info, block_info_idx, 4838 info->intr_enable_reg, enable); 4839 break; 4840 case _SOC_PARITY_TYPE_MMU_SER: 4841 case _SOC_PARITY_TYPE_ECC: 4842 case _SOC_PARITY_TYPE_ECC_DUAL: 4843 case _SOC_PARITY_TYPE_PARITY: 4844 case _SOC_PARITY_TYPE_PARITY_DUAL: 4845 reg = info->enable_reg; 4846 if (!SOC_REG_IS_VALID(unit, reg)) { 4847 break; 4848 } 4849 SOC_IF_ERROR_RETURN 4850 (soc_reg_get(unit, reg, port, 0, &rval64)); 4851 soc_reg64_field32_set(unit, reg, &rval64, info->enable_field, 4852 enable ? 1 : 0); 4853 SOC_IF_ERROR_RETURN 4854 (soc_reg_set(unit, reg, port, 0, rval64)); 4855 4856 LOG_VERBOSE(BSL_LS_SOC_SOCMEM, 4857 (BSL_META_U(unit, 4858 "SER enable for: %s\n"), 4859 (info->mem == INVALIDm) ? info->mem_str : 4860 SOC_MEM_NAME(unit, info->mem))); 4861 if (info->type == _SOC_PARITY_TYPE_MMU_SER) { 4862 rv = _soc_gh2_mmu_ser_config(unit, info->info, 4863 info->intr_enable_reg, 4864 mem, enable); 4865 } 4866 break; 4867 default: break; 4868 } 4869 } 4870 return rv; 4871 } 4872 4873 int 4874 _soc_gh2_mem_parity_control(int unit, soc_mem_t mem, 4875 int copyno, int enable) 4876 { 4877 soc_reg_t parity_enable_reg = INVALIDr; 4878 soc_field_t hw_parity_field = INVALIDf; 4879 uint8 rbi; 4880 _soc_gh2_ser_route_block_t *rb; 4881 uint32 cmic_bit; 4882 int block_info_idx; 4883 soc_mem_t memTable; 4884 int port = REG_PORT_ANY; 4885 _soc_gh2_ser_info_t *info_list, *info; 4886 int info_index; 4887 uint32 misc_cfg; 4888 4889 if (!soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 4890 /* Parity checking is not enabled, nothing to do */ 4891 return SOC_E_NONE; 4892 } 4893 /* Convert component/aggregate memories to the table for which 4894 * the parity registers correspond. */ 4895 switch(mem) { 4896 case VLAN_SUBNET_ONLYm: 4897 case VLAN_SUBNET_DATA_ONLYm: 4898 mem = VLAN_SUBNETm; 4899 break; 4900 case L2_ENTRY_ONLYm: 4901 mem = L2Xm; 4902 break; 4903 case L2_USER_ENTRY_ONLYm: 4904 case L2_USER_ENTRY_DATA_ONLYm: 4905 mem = L2_USER_ENTRYm; 4906 break; 4907 case L3_DEFIP_DATA_ONLYm: 4908 mem = L3_DEFIPm; 4909 break; 4910 case L3_ENTRY_IPV4_UNICASTm: 4911 case L3_ENTRY_IPV6_UNICASTm: 4912 case L3_ENTRY_IPV4_MULTICASTm: 4913 case L3_ENTRY_IPV6_MULTICASTm: 4914 mem = L3_ENTRY_ONLYm; 4915 break; 4916 case VLAN_MACm: 4917 mem = VLAN_XLATEm; 4918 break; 4919 case MODPORT_MAPm: 4920 mem = MODPORT_MAP_SWm; 4921 break; 4922 case MY_STATION_TCAM_DATA_ONLYm: 4923 mem = MY_STATION_TCAMm; 4924 break; 4925 case EGR_IP_TUNNEL_IPV6m: 4926 mem = EGR_IP_TUNNELm; 4927 break; 4928 default: 4929 /* Do nothing, keep memory as provided */ 4930 break; 4931 } 4932 4933 /* Loop through each place-and-route block entry */ 4934 for (rbi = 0; ; rbi++) { 4935 rb = &_soc_gh2_ser_route_blocks[rbi]; 4936 cmic_bit = rb->cmic_bit; 4937 parity_enable_reg = INVALIDr; 4938 hw_parity_field = INVALIDf; 4939 if (cmic_bit == 0) { 4940 /* End of table */ 4941 break; 4942 } 4943 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 4944 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 4945 port = SOC_BLOCK_PORT(unit, block_info_idx); 4946 break; 4947 } 4948 } 4949 if ((copyno != MEM_BLOCK_ANY) && (copyno != block_info_idx)) { 4950 continue; 4951 } 4952 info_list = rb->info; 4953 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 4954 parity_enable_reg = info_list[0].enable_reg; 4955 hw_parity_field = info_list[0].enable_field; 4956 info_list = info_list[0].info; 4957 } 4958 for (info_index = 0; ; info_index++) { 4959 info = &info_list[info_index]; 4960 if (info->type == _SOC_PARITY_TYPE_NONE) { 4961 /* End of table */ 4962 break; 4963 } 4964 if (_soc_gh2_ser_mem_skip(unit, info)) { 4965 continue; 4966 } 4967 memTable = info->mem; 4968 if (memTable == INVALIDm) { 4969 continue; 4970 } 4971 if (memTable == mem) { 4972 if (parity_enable_reg == INVALIDr) { 4973 parity_enable_reg = info->enable_reg; 4974 } 4975 if (hw_parity_field == INVALIDf) { 4976 hw_parity_field = info->enable_field; 4977 } 4978 SOC_IF_ERROR_RETURN( 4979 soc_reg_field32_modify(unit, parity_enable_reg, port, 4980 hw_parity_field, 4981 enable ? 1 : 0)); 4982 4983 return SOC_E_NONE; 4984 } 4985 } 4986 } 4987 /* MMU controls */ 4988 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 4989 if (enable) { 4990 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHECK_ENf, 1); 4991 } else { 4992 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHECK_ENf, 0); 4993 } 4994 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 4995 4996 return SOC_E_NONE; 4997 } 4998 int 4999 soc_gh2_ser_enable_all(int unit, int enable) 5000 { 5001 _soc_gh2_ser_route_block_t *rb; 5002 uint8 rbi; 5003 int block_info_idx; 5004 int port = REG_PORT_ANY; 5005 uint64 rval64; 5006 int rv = SOC_E_NONE; 5007 5008 /* Loop through each place-and-route block entry */ 5009 for (rbi = 0; ; rbi++) { 5010 rb = &_soc_gh2_ser_route_blocks[rbi]; 5011 if (rb->cmic_bit == 0) { 5012 /* End of table */ 5013 break; 5014 } 5015 port = REG_PORT_ANY; 5016 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 5017 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 5018 port = SOC_BLOCK_PORT(unit, block_info_idx); 5019 break; 5020 } 5021 } 5022 if (rb->enable_reg != INVALIDr) { 5023 if (!SOC_REG_IS_VALID(unit, rb->enable_reg)) { 5024 continue; 5025 } 5026 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 5027 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 5028 /* This port block is not configured */ 5029 continue; 5030 } 5031 SOC_IF_ERROR_RETURN 5032 (soc_reg_get(unit, rb->enable_reg, port, 0, &rval64)); 5033 } 5034 rv = _soc_gh2_ser_enable_info(unit, block_info_idx, rb->id, port, 5035 rb->enable_reg, &rval64, 5036 rb->info, INVALIDm, enable); 5037 if (rv == SOC_E_NOT_FOUND) { 5038 continue; 5039 } else if (SOC_FAILURE(rv)) { 5040 return rv; 5041 } 5042 5043 if (rb->enable_reg != INVALIDr) { 5044 /* Write per route block parity enable register */ 5045 SOC_IF_ERROR_RETURN 5046 (soc_reg_set(unit, rb->enable_reg, port, 0, rval64)); 5047 } 5048 } 5049 5050 soc_gh2_ser_cmic_interrupt_enable(unit, enable); 5051 5052 return SOC_E_NONE; 5053 } 5054 5055 static _soc_generic_ser_info_t _soc_gh2_tcam_ser_info_template[] = { 5056 #if _GH2_SER_TEST_TCAM 5057 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5058 _SOC_SER_INTERLEAVE_MOD2, 5059 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 5060 _SOC_SER_FLAG_XY_READ}, 5061 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5062 _SOC_SER_INTERLEAVE_MOD2, 5063 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 5064 _SOC_SER_FLAG_XY_READ}, 5065 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 5066 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 5067 { {0, 66}, {1, 66}, {67, 132}, {68, 132} }, 0, 0, 0, 0, 5068 _SOC_SER_FLAG_XY_READ}, 5069 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5070 _SOC_SER_INTERLEAVE_MOD2, 5071 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 5072 _SOC_SER_FLAG_XY_READ}, 5073 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5074 _SOC_SER_INTERLEAVE_MOD2, 5075 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 5076 _SOC_SER_FLAG_XY_READ}, 5077 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5078 _SOC_SER_INTERLEAVE_MOD2, 5079 { {0, 72}, {1, 72}, {73, 144}, {74, 144} }, 0, 0, 0, 0, 5080 _SOC_SER_FLAG_XY_READ}, 5081 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5082 _SOC_SER_INTERLEAVE_MOD2, 5083 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 5084 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 5085 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5086 _SOC_SER_INTERLEAVE_MOD2, 5087 { {0, 238}, {1, 238}, {239, 473}, {240, 473} }, 0, 0, 0, 0, 5088 _SOC_SER_FLAG_XY_READ}, 5089 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5090 _SOC_SER_INTERLEAVE_MOD2, 5091 { {0, 76}, {1, 76}, {77, 152}, {78, 152} }, 0, 0, 0, 0, 5092 _SOC_SER_FLAG_XY_READ}, 5093 { SVC_METER_OFFSET_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 5094 _SOC_SER_INTERLEAVE_MOD2, 5095 { {0, 90}, {1, 90}, {91, 180}, {92, 180} }, 0, 0, 0, 0, 5096 _SOC_SER_FLAG_XY_READ}, 5097 #endif /* _GH2_SER_TEST_TCAM */ 5098 /* End of list */ 5099 { INVALIDm }, 5100 }; 5101 static _soc_generic_ser_info_t *_soc_gh2_tcam_ser_info[SOC_MAX_NUM_DEVICES] = {NULL}; 5102 5103 int 5104 soc_gh2_tcam_ser_init(int unit) 5105 { 5106 int alloc_size; 5107 int sku; 5108 5109 (void)soc_gh2_chip_sku_get(unit, &sku); 5110 5111 /* First, make per-unit copy of the master TCAM list */ 5112 alloc_size = sizeof(_soc_gh2_tcam_ser_info_template); 5113 if (NULL == _soc_gh2_tcam_ser_info[unit]) { 5114 if ((_soc_gh2_tcam_ser_info[unit] = 5115 sal_alloc(alloc_size, "gh2 tcam list")) == NULL) { 5116 return SOC_E_MEMORY; 5117 } 5118 sal_memset(_soc_gh2_tcam_ser_info[unit], 0, alloc_size); 5119 } 5120 if (sku == SOC_GH2_SKU_HURRICANE3MG || 5121 sku == SOC_GH2_SKU_QUARTZ 5122 ) { 5123 /* Greyhound2 */ 5124 sal_memcpy( 5125 _soc_gh2_tcam_ser_info[unit], 5126 &(_soc_gh2_tcam_ser_info_template), 5127 alloc_size); 5128 } 5129 5130 #ifdef INCLUDE_MEM_SCAN 5131 soc_mem_scan_ser_list_register(unit, TRUE, 5132 _soc_gh2_tcam_ser_info[unit]); 5133 #endif 5134 return soc_generic_ser_init(unit, _soc_gh2_tcam_ser_info[unit]); 5135 } 5136 5137 void 5138 soc_gh2_ser_fail(int unit) 5139 { 5140 soc_generic_ser_process_error(unit, _soc_gh2_tcam_ser_info[unit], 5141 _SOC_PARITY_TYPE_SER); 5142 } 5143 5144 #if defined(SER_TR_TEST_SUPPORT) 5145 int 5146 ser_test_greyhound2_mem_index_remap(int unit, ser_test_data_t *test_data, 5147 int *mem_has_ecc) 5148 { 5149 int uft_bkt_bank = 0; 5150 int uft_le_fv = 0; 5151 int uft_le_ecc = 0; 5152 int remap_status = 0; 5153 5154 *mem_has_ecc = 0; 5155 test_data->mem = test_data->mem_fv; 5156 test_data->index = test_data->index_fv; 5157 5158 if (_soc_gh2_ser_2bit_ecc_mem(unit, test_data->mem_fv)) { 5159 *mem_has_ecc = 1; 5160 } 5161 5162 if ((test_data->mem != test_data->mem_fv) || 5163 (test_data->index != test_data->index_fv)) { 5164 LOG_VERBOSE(BSL_LS_SOC_SER, 5165 (BSL_META_U(unit, 5166 "unit %d, ser_test_mem_index_remap: " 5167 "mem_fv %s, index_fv %0d, mem %s, index %0d, " 5168 "uft_bkt_bank %0d, uft_le_fv %0d, " 5169 "uft_le_ecc %0d, remap_status %0d \n"), 5170 unit, SOC_MEM_NAME(unit, test_data->mem_fv), test_data->index_fv, 5171 SOC_MEM_NAME(unit, test_data->mem), test_data->index, 5172 uft_bkt_bank, uft_le_fv, uft_le_ecc, remap_status)); 5173 } 5174 return remap_status; 5175 } 5176 5177 soc_ser_test_functions_t ser_gh2_test_fun; 5178 5179 /* Overlay memory */ 5180 const soc_ser_overlay_test_t soc_ser_gh2_overlay_mems[] = { 5181 {L3_ENTRY_IPV4_UNICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 5182 {L3_ENTRY_IPV4_MULTICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 5183 {L3_ENTRY_IPV6_MULTICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 5184 {L3_ENTRY_IPV6_UNICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 5185 {MODPORT_MAPm, MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, MODPORT_MAP_SWm, _SOC_ACC_TYPE_PIPE_ANY}, 5186 {EGR_IP_TUNNEL_IPV6m, EGR_IP_TUNNEL_PARITY_CONTROLr, PARITY_ENf, EGR_IP_TUNNELm, _SOC_ACC_TYPE_PIPE_ANY}, 5187 {INVALIDm} 5188 }; 5189 5190 STATIC int 5191 soc_gh2_tcam_entry_is_invalid(int unit, soc_mem_t mem, int index) 5192 { 5193 if (soc_feature(unit, soc_feature_field_slice_size128)) { 5194 if (mem == FP_GLOBAL_MASK_TCAMm || mem == FP_TCAMm) { 5195 if ((index / 64) % 2) { 5196 return TRUE; 5197 } 5198 } 5199 } 5200 return FALSE; 5201 } 5202 5203 /* 5204 * Function: 5205 * soc_gh2_ser_inject_error 5206 * Purpose: 5207 * Injects an error into a single memory 5208 * Parameters: 5209 * unit - (IN) Device Number 5210 * mem - (IN) The memory to test 5211 * pipeTarget - (IN) The pipe (x/y) to use when injecting the error 5212 * block - (IN) The index into which block will be injected. 5213 * index - (IN) The index into which the error will be injected. 5214 */ 5215 int soc_gh2_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, 5216 int pipeTarget, int block, int index) 5217 { 5218 _soc_generic_ser_info_t *tcam_ser_info = _soc_gh2_tcam_ser_info[unit]; 5219 soc_reg_t parity_enable_reg = INVALIDr; 5220 soc_field_t hw_parity_field = INVALIDf; 5221 soc_field_t test_field = INVALIDf; 5222 uint8 rbi; 5223 _soc_gh2_ser_route_block_t *rb; 5224 uint32 cmic_bit; 5225 int block_info_idx; 5226 soc_mem_t memTable; 5227 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 5228 int i, overlay_mem = 0; 5229 ser_test_data_t test_data; 5230 int port = REG_PORT_ANY; 5231 _soc_gh2_ser_info_t *info_list, *info; 5232 int info_index; 5233 5234 if (!SOC_MEM_IS_VALID(unit, mem)) { 5235 LOG_ERROR(BSL_LS_SOC_COMMON, 5236 (BSL_META_U(unit, 5237 "unit %d, mem %d is INVALID or not valid " 5238 "for this unit !!\n"), 5239 unit, mem)); 5240 return SOC_E_UNAVAIL; 5241 } 5242 if (tcam_ser_info != NULL) { 5243 /*TCAM_test*/ 5244 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 5245 if (tcam_ser_info[i].mem == mem) { 5246 /* Check if this entry is invalid or not */ 5247 if (soc_gh2_tcam_entry_is_invalid(unit, mem, index)) { 5248 return (SOC_E_PARAM); 5249 } 5250 soc_ser_create_test_data(unit, tmp_entry, fieldData, 5251 SER_RANGE_ENABLEr, i, VALIDf, mem, 5252 VALIDf, MEM_BLOCK_ANY, REG_PORT_ANY, 5253 _SOC_ACC_TYPE_PIPE_ANY, index, &test_data); 5254 /*Disable parity*/ 5255 SOC_IF_ERROR_RETURN( 5256 _ser_test_parity_control(unit, &test_data, 0)); 5257 /*Read the memory for successful injection*/ 5258 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 5259 /*Inject error*/ 5260 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, 5261 &test_data)); 5262 /*Enable parity*/ 5263 SOC_IF_ERROR_RETURN( 5264 _ser_test_parity_control(unit, &test_data, 1)); 5265 return SOC_E_NONE; 5266 } 5267 } 5268 } 5269 5270 /* Loop through each place-and-route block entry */ 5271 for (rbi = 0; ; rbi++) { 5272 rb = &_soc_gh2_ser_route_blocks[rbi]; 5273 cmic_bit = rb->cmic_bit; 5274 parity_enable_reg = INVALIDr; 5275 hw_parity_field = INVALIDf; 5276 if (cmic_bit == 0) { 5277 /* End of table */ 5278 break; 5279 } 5280 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 5281 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 5282 port = SOC_BLOCK_PORT(unit, block_info_idx); 5283 break; 5284 } 5285 } 5286 if ((block != MEM_BLOCK_ANY) && (block != block_info_idx)) { 5287 continue; 5288 } 5289 info_list = rb->info; 5290 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 5291 parity_enable_reg = info_list[0].enable_reg; 5292 hw_parity_field = info_list[0].enable_field; 5293 info_list = info_list[0].info; 5294 } 5295 for (info_index = 0; ; info_index++) { 5296 info = &info_list[info_index]; 5297 if (info->type == _SOC_PARITY_TYPE_NONE) { 5298 /* End of table */ 5299 break; 5300 } 5301 if (_soc_gh2_ser_mem_skip(unit, info)) { 5302 continue; 5303 } 5304 memTable = info->mem; 5305 if (memTable == INVALIDm) { 5306 continue; 5307 } 5308 /* Check if overlay memory */ 5309 for (i=0; soc_ser_gh2_overlay_mems[i].mem != INVALIDm; i++) { 5310 if ((soc_ser_gh2_overlay_mems[i].mem == mem) && 5311 (soc_ser_gh2_overlay_mems[i].base_mem == memTable)) { 5312 overlay_mem = 1; 5313 break; 5314 } 5315 } 5316 if ((memTable == mem) || (overlay_mem)) { 5317 /* Inject error */ 5318 test_data.mem = mem; 5319 test_data.tcam_parity_bit = -1; 5320 if (parity_enable_reg == INVALIDr) { 5321 parity_enable_reg = info->enable_reg; 5322 } 5323 if (hw_parity_field == INVALIDf) { 5324 hw_parity_field = info->enable_field; 5325 } 5326 if (_soc_gh2_ser_2bit_ecc_mem(unit, memTable)) { 5327 flags |= SOC_INJECT_ERROR_2BIT_ECC; 5328 test_field = ECCf; 5329 } else { 5330 test_field = EVEN_PARITYf; 5331 } 5332 soc_ser_create_test_data(unit, tmp_entry, 5333 fieldData, 5334 parity_enable_reg, 5335 SOC_INVALID_TCAM_PARITY_BIT, 5336 hw_parity_field, 5337 mem, test_field, block, 5338 port, _SOC_ACC_TYPE_PIPE_ANY, 5339 index, &test_data); 5340 /* Disable parity */ 5341 SOC_IF_ERROR_RETURN( 5342 _ser_test_parity_control(unit, &test_data, 0)); 5343 5344 /* Read the memory for successful injection */ 5345 SOC_IF_ERROR_RETURN( 5346 ser_test_mem_read(unit, 0, &test_data)); 5347 5348 /* Inject error */ 5349 SOC_IF_ERROR_RETURN( 5350 soc_ser_test_inject_full(unit, flags, &test_data)); 5351 5352 /* Enable parity */ 5353 SOC_IF_ERROR_RETURN( 5354 _ser_test_parity_control(unit, &test_data, 1)); 5355 return SOC_E_NONE; 5356 } 5357 } 5358 } 5359 /* The tested memory is not found in SER enabled list, can't inject error of it */ 5360 return SOC_E_UNAVAIL; 5361 } 5362 5363 STATIC soc_error_t 5364 _ser_gh2_ser_error_injection_support(int unit, soc_mem_t mem, 5365 int pipe_target) 5366 { 5367 int rv = SOC_E_UNAVAIL; 5368 int i = 0, hw_enable_ix = 0; 5369 int overlay_mem = 0, block_info_idx = 0; 5370 uint32 range_enable; 5371 5372 uint8 rbi; 5373 soc_mem_t memTable; 5374 int info_index; 5375 _soc_generic_ser_info_t *tcam_ser_info; 5376 _soc_gh2_ser_route_block_t *rb; 5377 _soc_gh2_ser_info_t *info_list, *info; 5378 5379 if ((mem == MMU_WRED_AVG_QSIZEm) || 5380 (mem == MMU_WRED_AVG_QSIZE_QGROUPm) || 5381 (mem == MMU_WRED_MARK_THDm)) { 5382 /* 5383 * Inject function aim for SQA to test SER in an easiler way 5384 * To support above memories, soc_mem_read need to support 5385 * FUNCTIONAL_REFRESH_ENr which is not a general case of SER. 5386 * Also, TR144 & SER recovery have supported those memories. 5387 * Thus, we disable them on inject function. 5388 */ 5389 return rv; 5390 } 5391 5392 LOG_VERBOSE(BSL_LS_SOC_SER, 5393 (BSL_META_U(unit, 5394 "unit %d, mem %s, pipe_target %d\n"), 5395 unit, SOC_MEM_NAME(unit,mem), pipe_target)); 5396 5397 if (!SOC_MEM_IS_VALID(unit, mem)) { 5398 LOG_ERROR(BSL_LS_SOC_COMMON, 5399 (BSL_META_U(unit, 5400 "unit %d, mem %d is INVALID or not valid " 5401 "for this unit !!\n"), 5402 unit, mem)); 5403 return rv; 5404 } 5405 5406 tcam_ser_info = _soc_gh2_tcam_ser_info[unit]; 5407 5408 /* Search TCAMs */ 5409 if (tcam_ser_info != NULL) { 5410 5411 /* Check if enable */ 5412 SOC_IF_ERROR_RETURN 5413 (READ_SER_RANGE_ENABLEr(unit, &range_enable)); 5414 LOG_DEBUG(BSL_LS_SOC_SER, 5415 (BSL_META_U(unit, 5416 "Search TCAMs: SER_RANGE_ENABLE 0x%X\n"), 5417 range_enable)); 5418 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 5419 if (tcam_ser_info[i].mem == mem) { 5420 5421 hw_enable_ix = tcam_ser_info[i].ser_hw_index; 5422 LOG_DEBUG(BSL_LS_SOC_SER, 5423 (BSL_META_U(unit, 5424 "SER Range HW Enable index %d\n"), 5425 hw_enable_ix)); 5426 if (((range_enable >> hw_enable_ix) & 0x1) == 0) { 5427 LOG_WARN(BSL_LS_SOC_SER, 5428 (BSL_META_U(unit, 5429 "matched mem but SER detection is disabled\n" 5430 "SER_RANGE_ENABLE 0x%X, SER Range HW index %d\n"), 5431 range_enable,hw_enable_ix)); 5432 return rv; /* matched mem but ser_detection is disabled */ 5433 } 5434 LOG_VERBOSE(BSL_LS_SOC_SER, 5435 (BSL_META_U(unit, 5436 "TCAM found\n"))); 5437 return SOC_E_NONE; /* found */ 5438 } 5439 } 5440 } 5441 5442 5443 /* Search H/W memory (route blocks) */ 5444 /* Loop through each place-and-route block entry */ 5445 for (rbi = 0; ; rbi++) { 5446 rb = &_soc_gh2_ser_route_blocks[rbi]; 5447 if (rb->cmic_bit == 0) { 5448 /* End of table */ 5449 break; 5450 } 5451 5452 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 5453 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 5454 break; 5455 } 5456 } 5457 5458 info_list = rb->info; 5459 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 5460 info_list = info_list[0].info; 5461 } 5462 for (info_index = 0; ; info_index++) { 5463 info = &info_list[info_index]; 5464 if (info->type == _SOC_PARITY_TYPE_NONE) { 5465 /* End of table */ 5466 break; 5467 } 5468 if (_soc_gh2_ser_mem_skip(unit, info)) { 5469 continue; 5470 } 5471 memTable = info->mem; 5472 if (memTable == INVALIDm) { 5473 continue; 5474 } 5475 /* Check if overlay memory */ 5476 for (i=0; soc_ser_gh2_overlay_mems[i].mem != INVALIDm; i++) { 5477 if ((soc_ser_gh2_overlay_mems[i].mem == mem) && 5478 (soc_ser_gh2_overlay_mems[i].base_mem == memTable)) { 5479 overlay_mem = 1; 5480 LOG_DEBUG(BSL_LS_SOC_SER, 5481 (BSL_META_U(unit, 5482 "mem %s base_mem %s\n"), 5483 SOC_MEM_NAME(unit,mem),SOC_MEM_NAME(unit,memTable))); 5484 break; 5485 } 5486 } 5487 if ((memTable == mem) || (overlay_mem)) { 5488 LOG_VERBOSE(BSL_LS_SOC_SER, 5489 (BSL_META_U(unit, 5490 "H/W memory (route blocks) found\n"))); 5491 return SOC_E_NONE; 5492 } 5493 } 5494 } 5495 /* The tested memory is not found in SER enabled list, can't inject error of it */ 5496 return rv; 5497 } 5498 5499 5500 /* 5501 * Function: 5502 * soc_gh2_ser_mem_test 5503 * Purpose: 5504 * Performs a SER test on a single memory 5505 * tr 144 = mem 5506 * Parameters: 5507 * unit - (IN) Device Number 5508 * mem - (IN) The memory to test 5509 * test_type - (IN) How many indices in the memory to test 5510 * cmd - (IN) TRUE if a command-line test is desired. 5511 */ 5512 int soc_gh2_ser_test_mem(int unit, soc_mem_t mem, 5513 _soc_ser_test_t test_type, int cmd) 5514 { 5515 _soc_generic_ser_info_t *tcam_ser_info = _soc_gh2_tcam_ser_info[unit]; 5516 soc_reg_t parity_enable_reg = INVALIDr; 5517 soc_field_t hw_parity_field = INVALIDf; 5518 uint8 rbi; 5519 _soc_gh2_ser_route_block_t *rb; 5520 uint32 cmic_bit; 5521 int block_info_idx; 5522 int found_mem = FALSE; 5523 soc_mem_t memTable; 5524 int testErrors = 0; 5525 ser_test_data_t test_data; 5526 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 5527 int i, overlay_mem = 0; 5528 int rv = SOC_E_NONE; 5529 int port = REG_PORT_ANY; 5530 _soc_gh2_ser_info_t *info_list, *info; 5531 int info_index; 5532 uint32 wred_refresh = 0, reg_val; 5533 5534 if (!SOC_MEM_IS_VALID(unit, mem)) { 5535 LOG_ERROR(BSL_LS_SOC_COMMON, 5536 (BSL_META_U(unit, 5537 "unit %d, mem %d is INVALID or not valid " 5538 "for this unit !!\n"), 5539 unit, mem)); 5540 return SOC_E_UNAVAIL; 5541 } 5542 5543 if (!SAL_BOOT_QUICKTURN) { 5544 soc_ser_test_long_sleep = TRUE; 5545 soc_ser_test_long_sleep_time_us = 500000; 5546 } 5547 if (tcam_ser_info != NULL) { 5548 /*TCAM_test*/ 5549 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 5550 if (tcam_ser_info[i].mem == mem) { 5551 memTable = mem; 5552 found_mem = TRUE; 5553 soc_ser_create_test_data(unit, tmp_entry, fieldData, 5554 SER_RANGE_ENABLEr, i, INVALIDf, memTable, 5555 VALIDf, MEM_BLOCK_ANY, REG_PORT_ANY, 5556 _SOC_ACC_TYPE_PIPE_ANY, 0, &test_data); 5557 if (cmd) { 5558 ser_test_cmd_generate(unit, &test_data); 5559 } else { 5560 rv = ser_test_mem(unit, 0, &test_data, 5561 test_type, &testErrors); 5562 if (rv != SOC_E_NONE) { 5563 LOG_CLI((BSL_META_U(unit, 5564 "Error during TCAM test. Aborting.\n"))); 5565 soc_ser_test_long_sleep = FALSE; 5566 return rv; 5567 } 5568 } 5569 } 5570 } 5571 } 5572 if (!found_mem) { 5573 /*H/W memory Test*/ 5574 /* Loop through each place-and-route block entry */ 5575 for (rbi = 0; ; rbi++) { 5576 rb = &_soc_gh2_ser_route_blocks[rbi]; 5577 cmic_bit = rb->cmic_bit; 5578 parity_enable_reg = INVALIDr; 5579 hw_parity_field = INVALIDf; 5580 if (cmic_bit == 0) { 5581 /* End of table */ 5582 break; 5583 } 5584 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 5585 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 5586 port = SOC_BLOCK_PORT(unit, block_info_idx); 5587 break; 5588 } 5589 } 5590 5591 info_list = rb->info; 5592 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 5593 parity_enable_reg = info_list[0].enable_reg; 5594 hw_parity_field = info_list[0].enable_field; 5595 info_list = info_list[0].info; 5596 } 5597 for (info_index = 0; ; info_index++) { 5598 info = &info_list[info_index]; 5599 if (info->type == _SOC_PARITY_TYPE_NONE) { 5600 /* End of table */ 5601 break; 5602 } 5603 if (_soc_gh2_ser_mem_skip(unit, info)) { 5604 continue; 5605 } 5606 memTable = info->mem; 5607 if (memTable == INVALIDm) { 5608 continue; 5609 } 5610 /* Check if overlay memory */ 5611 for (i=0; soc_ser_gh2_overlay_mems[i].mem != INVALIDm; i++) { 5612 if ((soc_ser_gh2_overlay_mems[i].mem == mem) && 5613 (soc_ser_gh2_overlay_mems[i].base_mem == memTable)) { 5614 overlay_mem = 1; 5615 break; 5616 } 5617 } 5618 if ((memTable == mem) || (overlay_mem)) { 5619 found_mem = TRUE; 5620 if (parity_enable_reg == INVALIDr) { 5621 parity_enable_reg = info->enable_reg; 5622 } 5623 if (hw_parity_field == INVALIDf) { 5624 hw_parity_field = info->enable_field; 5625 } 5626 if ((memTable == MMU_WRED_AVG_QSIZEm) || 5627 (memTable == MMU_WRED_AVG_QSIZE_QGROUPm) || 5628 (memTable == MMU_WRED_MARK_THDm)) { 5629 rv = soc_reg32_get(unit, 5630 FUNCTIONAL_REFRESH_ENr, port, 0, 5631 ®_val); 5632 if (rv != SOC_E_NONE) { 5633 LOG_CLI((BSL_META_U(unit, 5634 "Error of getting WRED " 5635 "refresh function Aborting.\n"))); 5636 soc_ser_test_long_sleep = FALSE; 5637 return rv; 5638 } 5639 wred_refresh = soc_reg_field_get(unit, 5640 FUNCTIONAL_REFRESH_ENr, 5641 reg_val, WRED_REFRESH_ENf); 5642 if (wred_refresh) { 5643 soc_reg_field_set(unit, 5644 FUNCTIONAL_REFRESH_ENr, ®_val, 5645 WRED_REFRESH_ENf, 0); 5646 rv = soc_reg32_set(unit, 5647 FUNCTIONAL_REFRESH_ENr, port, 0, 5648 reg_val); 5649 if (rv != SOC_E_NONE) { 5650 LOG_CLI((BSL_META_U(unit, 5651 "Error of disabling WRED " 5652 "refresh function Aborting.\n"))); 5653 soc_ser_test_long_sleep = FALSE; 5654 return rv; 5655 } 5656 } 5657 } 5658 soc_ser_create_test_data(unit, tmp_entry, 5659 fieldData, 5660 parity_enable_reg, 5661 SOC_INVALID_TCAM_PARITY_BIT, 5662 hw_parity_field, 5663 mem, INVALIDf, block_info_idx, 5664 port, _SOC_ACC_TYPE_PIPE_ANY, 5665 0, &test_data); 5666 if (cmd) { 5667 ser_test_cmd_generate(unit, &test_data); 5668 } else { 5669 rv = ser_test_mem(unit, 0, &test_data, 5670 test_type, &testErrors); 5671 } 5672 if ((memTable == MMU_WRED_AVG_QSIZEm) || 5673 (memTable == MMU_WRED_AVG_QSIZE_QGROUPm) || 5674 (memTable == MMU_WRED_MARK_THDm)) { 5675 /* restore WRED refresh configuration */ 5676 if (wred_refresh) { 5677 soc_reg_field_set(unit, 5678 FUNCTIONAL_REFRESH_ENr, ®_val, 5679 WRED_REFRESH_ENf, 1); 5680 rv = soc_reg32_set(unit, 5681 FUNCTIONAL_REFRESH_ENr, port, 0, 5682 reg_val); 5683 if (rv != SOC_E_NONE) { 5684 LOG_CLI((BSL_META_U(unit, 5685 "Error of enabling WRED " 5686 "refresh function Aborting.\n"))); 5687 soc_ser_test_long_sleep = FALSE; 5688 return rv; 5689 } 5690 } 5691 } 5692 if (rv != SOC_E_NONE) { 5693 LOG_CLI((BSL_META_U(unit, 5694 "Error during H/W test. Aborting.\n"))); 5695 soc_ser_test_long_sleep = FALSE; 5696 return rv; 5697 } 5698 break; 5699 } 5700 } 5701 if (found_mem) { 5702 break; 5703 } 5704 } 5705 5706 } 5707 if (!found_mem) { 5708 LOG_CLI((BSL_META_U(unit, 5709 "SER Test is unavaible on unit: %d for memory %s\n"), unit, 5710 SOC_MEM_NAME(unit,mem))); 5711 return SOC_E_UNAVAIL; 5712 } 5713 5714 if (testErrors == 0) { 5715 LOG_CLI((BSL_META_U(unit, 5716 "SER Test passed on unit: %d for memory %s\n"), unit, 5717 SOC_MEM_NAME(unit,mem))); 5718 } 5719 else { 5720 LOG_CLI((BSL_META_U(unit, 5721 "SER Test failed on unit: %d for memory %s\n"), unit, 5722 SOC_MEM_NAME(unit,mem))); 5723 soc_ser_test_long_sleep = FALSE; 5724 return SOC_E_MEMORY; 5725 } 5726 /* restore to default */ 5727 soc_ser_test_long_sleep = FALSE; 5728 return SOC_E_NONE; 5729 5730 } 5731 5732 /* 5733 * Function: 5734 * soc_gh2_ser_test 5735 * Purpose: 5736 * Performs a SER test on all Memories 5737 * tr 144 5738 * Parameters: 5739 * unit - (IN) Device Number 5740 * test_type - (IN) Determines how comprehensive of a test to run 5741 */ 5742 int soc_gh2_ser_test(int unit, _soc_ser_test_t test_type) 5743 { 5744 _soc_generic_ser_info_t *tcam_ser_info = _soc_gh2_tcam_ser_info[unit]; 5745 int numTCAMErr = 0; 5746 int numHwMemErr = 0; 5747 soc_reg_t parity_enable_reg = INVALIDr; 5748 soc_field_t hw_parity_field = INVALIDf; 5749 int port = REG_PORT_ANY; 5750 uint8 rbi; 5751 _soc_gh2_ser_route_block_t *rb; 5752 uint32 cmic_bit, reg_val; 5753 int block_info_idx; 5754 int rv = SOC_E_NONE; 5755 _soc_gh2_ser_info_t *info_list, *info; 5756 int info_index; 5757 soc_mem_t memTable = INVALIDm; 5758 uint32 wred_refresh = 0; 5759 5760 if (!SAL_BOOT_QUICKTURN) { 5761 soc_ser_test_long_sleep = TRUE; 5762 soc_ser_test_long_sleep_time_us = 500000; 5763 } 5764 5765 if (tcam_ser_info != NULL) { 5766 int i; 5767 /* TCAM_test */ 5768 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 5769 rv = ser_test_mem_pipe(unit, SER_RANGE_ENABLEr, i, -1, 5770 tcam_ser_info[i].mem, VALIDf, test_type, 5771 MEM_BLOCK_ANY, REG_PORT_ANY, 5772 _SOC_ACC_TYPE_PIPE_ANY, &numTCAMErr); 5773 if (rv != SOC_E_NONE) { 5774 LOG_CLI((BSL_META_U(unit, 5775 "TR 144 test failed. " 5776 "Error during TCAM test. Aborting.\n"))); 5777 soc_ser_test_long_sleep = FALSE; 5778 return rv; 5779 } 5780 } 5781 } 5782 5783 for (rbi = 0; ; rbi++) { 5784 rb = &_soc_gh2_ser_route_blocks[rbi]; 5785 cmic_bit = rb->cmic_bit; 5786 parity_enable_reg = INVALIDr; 5787 hw_parity_field = INVALIDf; 5788 if (cmic_bit == 0) { 5789 /* End of table */ 5790 break; 5791 } 5792 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 5793 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 5794 port = SOC_BLOCK_PORT(unit, block_info_idx); 5795 break; 5796 } 5797 } 5798 info_list = rb->info; 5799 5800 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 5801 parity_enable_reg = info_list[0].enable_reg; 5802 hw_parity_field = info_list[0].enable_field; 5803 info_list = info_list[0].info; 5804 } 5805 for (info_index = 0; ; info_index++) { 5806 info = &info_list[info_index]; 5807 if (info->type == _SOC_PARITY_TYPE_NONE) { 5808 /* End of table */ 5809 break; 5810 } 5811 if (_soc_gh2_ser_mem_skip(unit, info)) { 5812 continue; 5813 } 5814 memTable = info->mem; 5815 if (memTable == INVALIDm){ 5816 continue; 5817 } 5818 if (parity_enable_reg == INVALIDr) { 5819 parity_enable_reg = info->enable_reg; 5820 } 5821 if (hw_parity_field == INVALIDf) { 5822 hw_parity_field = info->enable_field; 5823 } 5824 5825 if ((memTable == MMU_WRED_AVG_QSIZEm) || 5826 (memTable == MMU_WRED_AVG_QSIZE_QGROUPm) || 5827 (memTable == MMU_WRED_MARK_THDm)) { 5828 rv = soc_reg32_get(unit, 5829 FUNCTIONAL_REFRESH_ENr, port, 0, 5830 ®_val); 5831 if (rv != SOC_E_NONE) { 5832 LOG_CLI((BSL_META_U(unit, 5833 "Error of getting WRED " 5834 "refresh function Aborting.\n"))); 5835 soc_ser_test_long_sleep = FALSE; 5836 return rv; 5837 } 5838 wred_refresh = soc_reg_field_get(unit, 5839 FUNCTIONAL_REFRESH_ENr, 5840 reg_val, WRED_REFRESH_ENf); 5841 if (wred_refresh) { 5842 soc_reg_field_set(unit, 5843 FUNCTIONAL_REFRESH_ENr, ®_val, 5844 WRED_REFRESH_ENf, 0); 5845 rv = soc_reg32_set(unit, 5846 FUNCTIONAL_REFRESH_ENr, port, 0, 5847 reg_val); 5848 if (rv != SOC_E_NONE) { 5849 LOG_CLI((BSL_META_U(unit, 5850 "Error of disabling WRED " 5851 "refresh function Aborting.\n"))); 5852 soc_ser_test_long_sleep = FALSE; 5853 return rv; 5854 } 5855 } 5856 } 5857 rv = ser_test_mem_pipe(unit, parity_enable_reg, -1, 5858 hw_parity_field, 5859 memTable, INVALIDf, test_type, 5860 block_info_idx, port, 5861 _SOC_ACC_TYPE_PIPE_ANY, &numHwMemErr); 5862 5863 if ((memTable == MMU_WRED_AVG_QSIZEm) || 5864 (memTable == MMU_WRED_AVG_QSIZE_QGROUPm) || 5865 (memTable == MMU_WRED_MARK_THDm)) { 5866 /* restore WRED refresh configuration */ 5867 if (wred_refresh) { 5868 soc_reg_field_set(unit, 5869 FUNCTIONAL_REFRESH_ENr, ®_val, 5870 WRED_REFRESH_ENf, 1); 5871 rv = soc_reg32_set(unit, 5872 FUNCTIONAL_REFRESH_ENr, port, 0, 5873 reg_val); 5874 if (rv != SOC_E_NONE) { 5875 LOG_CLI((BSL_META_U(unit, 5876 "Error of enabling WRED " 5877 "refresh function Aborting.\n"))); 5878 soc_ser_test_long_sleep = FALSE; 5879 return rv; 5880 } 5881 } 5882 } 5883 5884 if (rv != SOC_E_NONE) { 5885 LOG_CLI((BSL_META_U(unit, 5886 "TR 144 test failed. " 5887 "Error during H/W test. Aborting.\n"))); 5888 soc_ser_test_long_sleep = FALSE; 5889 return rv; 5890 } 5891 if (rb->blocktype != SOC_BLK_MMU){ 5892 parity_enable_reg = INVALIDr; 5893 hw_parity_field = INVALIDf; 5894 } 5895 } 5896 } 5897 5898 if((numTCAMErr != 0) || (numHwMemErr != 0)) { 5899 LOG_CLI((BSL_META_U(unit, 5900 "TR 144 test failed.\n"))); 5901 } 5902 5903 LOG_CLI((BSL_META_U(unit, 5904 "Total TCAM errors on unit %d: %d\n"), unit, numTCAMErr)); 5905 LOG_CLI((BSL_META_U(unit, 5906 "Total H/W parity errors on unit %d: %d\n"),unit, numHwMemErr)); 5907 soc_ser_test_long_sleep = FALSE; 5908 return SOC_E_NONE; 5909 } 5910 5911 void 5912 soc_gh2_ser_test_register(int unit) 5913 { 5914 /*Initialize chip-specific functions for SER testing*/ 5915 memset(&ser_gh2_test_fun, 0, sizeof(soc_ser_test_functions_t)); 5916 ser_gh2_test_fun.inject_error_f = &soc_gh2_ser_inject_error; 5917 ser_gh2_test_fun.test_mem = &soc_gh2_ser_test_mem; 5918 ser_gh2_test_fun.test = &soc_gh2_ser_test; 5919 ser_gh2_test_fun.injection_support = &_ser_gh2_ser_error_injection_support; 5920 5921 soc_ser_test_functions_register(unit, &ser_gh2_test_fun); 5922 } 5923 #endif /* SER_TR_TEST_SUPPORT */