bondoptions.c (10850B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 #include <shared/bsl.h> 8 9 #include <soc/defs.h> 10 11 #ifdef BCM_GREYHOUND2_SUPPORT 12 #include <soc/greyhound2.h> 13 #include <soc/bondoptions.h> 14 #include <shared/bitop.h> 15 #include <soc/iproc.h> 16 17 /**********************/ 18 /* 19 * Function to initialize the bondoptions cache based on the 20 * Bond Info read from the relevant registers. 21 */ 22 int 23 soc_greyhound2_bond_info_init(int unit) 24 { 25 26 int i, bit_val; 27 uint32 val, addr; 28 int pport_offset; 29 soc_bond_info_t *bond_info = SOC_BOND_INFO(unit); 30 const soc_reg_t soc_gh2_bond_info_regs[] = { 31 IPROC_WRAP_CHIP_OTP_STATUS_0_31_0r, 32 IPROC_WRAP_CHIP_OTP_STATUS_0_63_32r, 33 IPROC_WRAP_CHIP_OTP_STATUS_0_95_64r, 34 IPROC_WRAP_CHIP_OTP_STATUS_0_127_96r, 35 IPROC_WRAP_CHIP_OTP_STATUS_1_31_0r, 36 IPROC_WRAP_CHIP_OTP_STATUS_1_63_32r, 37 IPROC_WRAP_CHIP_OTP_STATUS_1_95_64r, 38 IPROC_WRAP_CHIP_OTP_STATUS_1_127_96r, 39 IPROC_WRAP_CHIP_OTP_STATUS_2_31_0r, 40 IPROC_WRAP_CHIP_OTP_STATUS_2_63_32r, 41 IPROC_WRAP_CHIP_OTP_STATUS_2_95_64r, 42 IPROC_WRAP_CHIP_OTP_STATUS_2_127_96r, 43 IPROC_WRAP_CHIP_OTP_STATUS_3_31_0r, 44 IPROC_WRAP_CHIP_OTP_STATUS_3_63_32r, 45 IPROC_WRAP_CHIP_OTP_STATUS_3_95_64r, 46 IPROC_WRAP_CHIP_OTP_STATUS_3_127_96r 47 }; 48 49 int reg_num = COUNTOF(soc_gh2_bond_info_regs); 50 SHR_BITDCL bond_info_regval[ 51 _SHR_BITDCLSIZE(COUNTOF(soc_gh2_bond_info_regs) * 32)] = {0}; 52 53 int feature_enables[][3] = { 54 /* Bit */ /* Bool Invert? */ /* Feature Enum */ /* Desc */ 55 {389, 0, socBondInfoFeatureEfp64HalfSlice }, /* EFP_SLICE_DEPTH */ 56 {387, 0, socBondInfoFeatureVfp64HalfSlice }, /* VFP_SLICE_DEPTH */ 57 {128, 1, socBondInfoFeatureNoL3 }, /* L3_ENABLE */ 58 {352, 1, socBondInfoFeatureNoVxlanLite }, /* VXLAN_LITE_ENABLE */ 59 {159, 0, socBondInfoFeatureNoTimeSync }, /* TS_1588_DISABLE */ 60 {151, 1, socBondInfoFeatureNoFpOam }, /* OAM_ENABLE */ 61 {156, 1, socBondInfoFeatureNoFpRouting }, /* FP_ROUTE_ENABLE */ 62 {353, 1, socBondInfoFeatureNoRRCOE }, /* RROCE_ENABLE */ 63 {354, 1, socBondInfoFeatureNoPreemption }, /* PREEMPTION_ENABLE */ 64 {355, 1, socBondInfoFeatureNoTAS }, /* TAS_ENABLE */ 65 {356, 1, socBondInfoFeatureNoHSR }, /* HSR_ENABLE */ 66 {357, 1, socBondInfoFeatureNoPRP }, /* PRP_ENABLE */ 67 {358, 1, socBondInfoFeatureNo8021CB }, /* IEEE_802_1CB_ENABLE */ 68 {-1, 0, -1 } /* Always last */ 69 }; 70 71 for (i = 0; i < reg_num; i++) { 72 addr = soc_reg_addr(unit, soc_gh2_bond_info_regs[i], REG_PORT_ANY, 0); 73 soc_iproc_getreg(unit, addr, &val); 74 SHR_BITCOPY_RANGE(bond_info_regval, (i * 32), &val, 0, 32); 75 } 76 77 SOC_BOND_OPTIONS_COPY(bond_info->rev_id, uint16, bond_info_regval, 0, 7); 78 SOC_BOND_OPTIONS_COPY(bond_info->dev_id, uint16, bond_info_regval, 8, 23); 79 80 /* IFP_SLICE_DEPTH */ 81 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 145, 146); 82 switch (val) { 83 case 0x0: 84 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureIfpSliceHalf); 85 break; 86 case 0x1: 87 /* 256 entries, skip */ 88 break; 89 case 0x2: 90 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureIfp64HalfSlice); 91 break; 92 default: 93 return SOC_E_INTERNAL; 94 } 95 96 /* L2 ENTRY Size */ 97 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 152, 153); 98 switch (val) { 99 case 0x0: 100 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL2Entry8k); 101 break; 102 case 0x1: 103 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL2Entry16k); 104 break; 105 case 0x2: 106 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL2Entry32k); 107 break; 108 case 0x3: 109 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL2Entry4k); 110 break; 111 default: 112 return SOC_E_INTERNAL; 113 } 114 115 /* LPM Size */ 116 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 154, 154); 117 switch (val) { 118 case 0x0: 119 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureLpm64); 120 break; 121 case 0x1: 122 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureLpm1k); 123 break; 124 default: 125 return SOC_E_INTERNAL; 126 } 127 128 /* NEXT_HOP and L3MC Table Size */ 129 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 155, 155); 130 switch (val) { 131 case 0x0: 132 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL3NextHop768); 133 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureIpmc64); 134 break; 135 case 0x1: 136 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL3NextHop5k); 137 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureIpmc1k); 138 break; 139 default: 140 return SOC_E_INTERNAL; 141 } 142 143 /* L2_MC */ 144 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 384, 384); 145 switch (val) { 146 case 0x0: 147 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL2mc4k); 148 break; 149 case 0x1: 150 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL2mc256); 151 break; 152 default: 153 return SOC_E_INTERNAL; 154 } 155 156 /* SPAN_TREE_GROUPS_SIZE */ 157 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 385, 385); 158 switch (val) { 159 case 0x0: 160 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureStg256); 161 break; 162 case 0x1: 163 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureStg32); 164 break; 165 default: 166 return SOC_E_INTERNAL; 167 } 168 169 /* VLAN_TRANSLATION_SIZE */ 170 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 386, 386); 171 switch (val) { 172 case 0x0: 173 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureIpVlanXlate4k); 174 break; 175 case 0x1: 176 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureIpVlanXlate256); 177 break; 178 default: 179 return SOC_E_INTERNAL; 180 } 181 182 /* L3_HOST_SIZE */ 183 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 388, 388); 184 switch (val) { 185 case 0x0: 186 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL3HostMax4k); 187 break; 188 case 0x1: 189 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureL3HostMax512); 190 break; 191 default: 192 return SOC_E_INTERNAL; 193 } 194 195 /* SR_FLOWID_SIZE */ 196 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 390, 390); 197 switch (val) { 198 case 0x0: 199 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureSRFlowId4k); 200 break; 201 case 0x1: 202 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureSRFlowId256); 203 break; 204 default: 205 return SOC_E_INTERNAL; 206 } 207 208 SOC_BOND_OPTIONS_COPY(bond_info->ifp_slice_map, uint32, 209 bond_info_regval, 133, 144); 210 SOC_BOND_OPTIONS_COPY(bond_info->efp_slice_map, uint32, 211 bond_info_regval, 147, 150); 212 SOC_BOND_OPTIONS_COPY(bond_info->vfp_slice_map, uint32, 213 bond_info_regval, 129, 132); 214 SOC_BOND_OPTIONS_COPY(bond_info->cbp_buffer_size, uint32, 215 bond_info_regval, 157, 158); 216 SOC_BOND_OPTIONS_COPY(bond_info->max_xqs_number, uint32, 217 bond_info_regval, 359, 359); 218 219 /* TSC related */ 220 /* 0~1 : QTC_DISABLE */ 221 SHR_BITCOPY_RANGE(bond_info->tsc_disabled, 0, bond_info_regval, 160, 2); 222 /* 2~8 : PM4X10_DISABLE */ 223 SHR_BITCOPY_RANGE(bond_info->tsc_disabled, 2, bond_info_regval, 162, 7); 224 /* 9~9 : PM4X25_DISABLE */ 225 SHR_BITCOPY_RANGE(bond_info->tsc_disabled, 9, bond_info_regval, 169, 1); 226 227 /* 0~3 : QTC_0_LANE_DISABLE[3:0] */ 228 pport_offset = GH2_PHY_PORT_OFFSET_QTC0; 229 for (i = 0; i < 4; i++) { 230 if (SHR_BITGET(bond_info_regval, 170 + i)) { 231 SHR_BITSET(bond_info->tsc_in_loop, pport_offset); 232 SHR_BITSET(bond_info->tsc_in_loop, pport_offset + 1); 233 SHR_BITSET(bond_info->tsc_in_loop, pport_offset + 2); 234 SHR_BITSET(bond_info->tsc_in_loop, pport_offset + 3); 235 } 236 pport_offset += 4; 237 } 238 /* 4~7 : QTC_1_LANE_DISABLE[3:0] */ 239 pport_offset = GH2_PHY_PORT_OFFSET_QTC1; 240 for (i = 0; i < 4; i++) { 241 if (SHR_BITGET(bond_info_regval, 174 + i)) { 242 SHR_BITSET(bond_info->tsc_in_loop, pport_offset); 243 SHR_BITSET(bond_info->tsc_in_loop, pport_offset + 1); 244 SHR_BITSET(bond_info->tsc_in_loop, pport_offset + 2); 245 SHR_BITSET(bond_info->tsc_in_loop, pport_offset + 3); 246 } 247 pport_offset += 4; 248 } 249 /* 8~11 : PM4X10_0_LANE_DISABLE[3:0] */ 250 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 251 GH2_PHY_PORT_OFFSET_TSCE0, bond_info_regval, 178, 4); 252 /* 12~15 : PM4X10_1_LANE_DISABLE[3:0] */ 253 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 254 GH2_PHY_PORT_OFFSET_TSCE1, bond_info_regval, 182, 4); 255 /* 16~19 : PM4X10_2_LANE_DISABLE[3:0] */ 256 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 257 GH2_PHY_PORT_OFFSET_TSCE2, bond_info_regval, 186, 4); 258 /* 20~23 : PM4X10_3_LANE_DISABLE[3:0] */ 259 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 260 GH2_PHY_PORT_OFFSET_TSCE3, bond_info_regval, 192, 4); 261 /* 24~27 : PM4X10_4_LANE_DISABLE[3:0] */ 262 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 263 GH2_PHY_PORT_OFFSET_TSCE4, bond_info_regval, 196, 4); 264 /* 28~31 : PM4X10_5_LANE_DISABLE[3:0] */ 265 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 266 GH2_PHY_PORT_OFFSET_TSCE5, bond_info_regval, 200, 4); 267 /* 32~35 : PM4X10_6_LANE_DISABLE[3:0] */ 268 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 269 GH2_PHY_PORT_OFFSET_TSCE6, bond_info_regval, 204, 4); 270 /* 36~39 : PM4X25_0_LANE_DISABLE[3:0] */ 271 SHR_BITCOPY_RANGE(bond_info->tsc_in_loop, 272 GH2_PHY_PORT_OFFSET_TSCF0, bond_info_regval, 208, 4); 273 274 for(i = 0; i < COUNTOF(feature_enables); i++) { 275 bit_val = SHR_BITGET(bond_info_regval, feature_enables[i][0]); 276 if (feature_enables[i][1]) { 277 /* Boolean invert */ 278 bit_val = !bit_val; 279 } 280 281 if (bit_val) { 282 SOC_BOND_INFO_FEATURE_SET(unit, feature_enables[i][2]); 283 } 284 } 285 286 return SOC_E_NONE; 287 } 288 #endif /* BCM_GREYHOUND2_SUPPORT */