greyhound2.c (708759B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: greyhound2.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <sal/core/boot.h> 14 15 #include <soc/firebolt.h> 16 #include <soc/bradley.h> 17 #include <soc/greyhound.h> 18 #include <soc/hurricane3.h> 19 #include <soc/greyhound2.h> 20 #include <soc/greyhound2_tdm.h> 21 #include <soc/drv.h> 22 #include <soc/mem.h> 23 #include <soc/hash.h> 24 #include <soc/lpm.h> 25 #include <soc/error.h> 26 #include <soc/debug.h> 27 #include <soc/er_tcam.h> 28 #include <soc/memtune.h> 29 #include <soc/devids.h> 30 #include <soc/defs.h> 31 #include <soc/bondoptions.h> 32 #include <soc/esw/port.h> 33 #include <soc/scache.h> 34 #include <soc/mspi.h> 35 #include <soc/iproc.h> 36 #include <soc/cmicm.h> 37 38 #include <shared/util.h> 39 #include <shared/l3.h> 40 #include <shared/bsl.h> 41 42 #ifdef BCM_GREYHOUND2_SUPPORT 43 44 #define SOC_MAX_PHY_PORTS 90 45 #define SOC_MAX_LOGICAL_PORTS 66 46 #define SOC_MAX_MMU_PORTS 66 47 48 static int gh2_port_speed[SOC_MAX_PHY_PORTS]; 49 50 /* Port config related : p2l, max_speed and TDM */ 51 #define GH2_TDM_SLOT_MAX 512 52 /* Initial TDM table */ 53 uint32 tdm_table_default[GH2_TDM_SLOT_MAX] = {0}; 54 55 /* OPTION_1 */ 56 int p2l_mapping_template_op1[] = { 57 0, -1, 58 /* TSC4L 0~5 */ 59 -1, -1, -1, -1, 60 -1, -1, -1, -1, 61 -1, -1, -1, -1, 62 -1, -1, -1, -1, 63 -1, -1, -1, -1, 64 -1, -1, -1, -1, 65 /* TSC4Q 0~1 */ 66 -1, -1, -1, -1, -1, -1, -1, -1, 67 -1, -1, -1, -1, -1, -1, -1, -1, 68 -1, -1, -1, -1, -1, -1, -1, -1, 69 -1, -1, -1, -1, -1, -1, -1, -1, 70 /* TSC 0~6*/ 71 -1, -1, -1, -1, 72 -1, -1, -1, -1, 73 -1, -1, -1, -1, 74 -1, -1, -1, -1, 75 -1, -1, -1, -1, 76 -1, -1, -1, -1, 77 -1, -1, -1, -1, 78 /* TSCF 0*/ 79 -1, -1, -1, -1 80 }; 81 int port_speed_max_template_op1[] = { 82 0, -1, 83 /* TSC4L 0~5 */ 84 -1, -1, -1, -1, 85 -1, -1, -1, -1, 86 -1, -1, -1, -1, 87 -1, -1, -1, -1, 88 -1, -1, -1, -1, 89 -1, -1, -1, -1, 90 /* TSC4Q 0~1 */ 91 -1, -1, -1, -1, -1, -1, -1, -1, 92 -1, -1, -1, -1, -1, -1, -1, -1, 93 -1, -1, -1, -1, -1, -1, -1, -1, 94 -1, -1, -1, -1, -1, -1, -1, -1, 95 /* TSC 0~6*/ 96 -1, -1, -1, -1, 97 -1, -1, -1, -1, 98 -1, -1, -1, -1, 99 -1, -1, -1, -1, 100 -1, -1, -1, -1, 101 -1, -1, -1, -1, 102 -1, -1, -1, -1, 103 /* TSCF 0*/ 104 -1, -1, -1, -1 105 }; 106 107 /* OPTION_2 */ 108 int p2l_mapping_template_op2[] = { 109 0, -1, 110 /* TSC4L 0~5 */ 111 2, 3, 4, 5, 112 6, 7, 8, 9, 113 10, 11, 12, 13, 114 14, 15, 16, 17, 115 18, 19, 20, 21, 116 22, 23, 24, 25, 117 /* TSC4Q 0~1 */ 118 -1, -1, -1, -1, -1, -1, -1, -1, 119 -1, -1, -1, -1, -1, -1, -1, -1, 120 -1, -1, -1, -1, -1, -1, -1, -1, 121 -1, -1, -1, -1, -1, -1, -1, -1, 122 /* TSC 0~6*/ 123 -1, -1, -1, -1, 124 -1, -1, -1, -1, 125 -1, -1, -1, -1, 126 -1, -1, -1, -1, 127 -1, -1, -1, -1, 128 -1, -1, -1, -1, 129 -1, -1, -1, -1, 130 /* TSCF 0*/ 131 -1, -1, -1, -1 132 }; 133 int port_speed_max_template_op2[] = { 134 0, -1, 135 /* TSC4L 0~5 */ 136 25, 25, 25, 25, 137 25, 25, 25, 25, 138 25, 25, 25, 25, 139 25, 25, 25, 25, 140 25, 25, 25, 25, 141 25, 25, 25, 25, 142 /* TSC4Q 0~1 */ 143 -1, -1, -1, -1, -1, -1, -1, -1, 144 -1, -1, -1, -1, -1, -1, -1, -1, 145 -1, -1, -1, -1, -1, -1, -1, -1, 146 -1, -1, -1, -1, -1, -1, -1, -1, 147 /* TSC 0~6*/ 148 -1, -1, -1, -1, 149 -1, -1, -1, -1, 150 -1, -1, -1, -1, 151 -1, -1, -1, -1, 152 -1, -1, -1, -1, 153 -1, -1, -1, -1, 154 -1, -1, -1, -1, 155 /* TSCF 0*/ 156 -1, -1, -1, -1 157 }; 158 159 /* OPTION_2A */ 160 int p2l_mapping_template_op2a[] = { 161 0, -1, 162 /* TSC4L 0~5 */ 163 2, 3, 4, 5, 164 6, 7, 8, 9, 165 10, 11, 12, 13, 166 14, 15, 16, 17, 167 18, 19, 20, 21, 168 22, 23, 24, 25, 169 /* TSC4Q 0~1 */ 170 -1, -1, -1, -1, -1, -1, -1, -1, 171 -1, -1, -1, -1, -1, -1, -1, -1, 172 -1, -1, -1, -1, -1, -1, -1, -1, 173 -1, -1, -1, -1, -1, -1, -1, -1, 174 /* TSC 0~6*/ 175 -1, -1, -1, -1, 176 -1, -1, -1, -1, 177 -1, -1, -1, -1, 178 -1, -1, -1, -1, 179 -1, -1, -1, -1, 180 -1, -1, -1, -1, 181 -1, -1, -1, -1, 182 /* TSCF 0*/ 183 -1, -1, -1, -1 184 }; 185 int port_speed_max_template_op2a[] = { 186 0, -1, 187 /* TSC4L 0~5 */ 188 25, 25, 25, 25, 189 25, 25, 25, 25, 190 25, 25, 25, 25, 191 25, 25, 25, 25, 192 25, 25, 25, 25, 193 25, 25, 25, 25, 194 /* TSC4Q 0~1 */ 195 -1, -1, -1, -1, -1, -1, -1, -1, 196 -1, -1, -1, -1, -1, -1, -1, -1, 197 -1, -1, -1, -1, -1, -1, -1, -1, 198 -1, -1, -1, -1, -1, -1, -1, -1, 199 /* TSC 0~6*/ 200 -1, -1, -1, -1, 201 -1, -1, -1, -1, 202 -1, -1, -1, -1, 203 -1, -1, -1, -1, 204 -1, -1, -1, -1, 205 -1, -1, -1, -1, 206 -1, -1, -1, -1, 207 /* TSCF 0*/ 208 -1, -1, -1, -1 209 }; 210 211 /* OPTION_3A */ 212 int p2l_mapping_template_op3a[] = { 213 0, -1, 214 /* TSC4L 0~5 */ 215 2, 3, 4, 5, 216 -1, -1, -1, -1, 217 -1, -1, -1, -1, 218 -1, -1, -1, -1, 219 -1, -1, -1, -1, 220 -1, -1, -1, -1, 221 /* TSC4Q 0~1 */ 222 6, 7, 8, 9, 10, 11, 12, 13, 223 14, 15, 16, 17, 18, 19, 20, 21, 224 22, 23, 24, 25, 26, 27, 28, 29, 225 30, 31, 32, 33, 34, 35, 36, 37, 226 /* TSC 0~6*/ 227 -1, -1, -1, -1, 228 -1, -1, -1, -1, 229 -1, -1, -1, -1, 230 -1, -1, -1, -1, 231 -1, -1, -1, -1, 232 -1, -1, -1, -1, 233 -1, -1, -1, -1, 234 /* TSCF 0*/ 235 -1, -1, -1, -1 236 }; 237 int port_speed_max_template_op3a[] = { 238 0, -1, 239 /* TSC4L 0~5 */ 240 10, 10, 10, 10, 241 -1, -1, -1, -1, 242 -1, -1, -1, -1, 243 -1, -1, -1, -1, 244 -1, -1, -1, -1, 245 -1, -1, -1, -1, 246 /* TSC4Q 0~1 */ 247 10, 10, 10, 10, 10, 10, 10, 10, 248 10, 10, 10, 10, 10, 10, 10, 10, 249 10, 10, 10, 10, 10, 10, 10, 10, 250 10, 10, 10, 10, 10, 10, 10, 10, 251 /* TSC 0~6*/ 252 -1, -1, -1, -1, 253 -1, -1, -1, -1, 254 -1, -1, -1, -1, 255 -1, -1, -1, -1, 256 -1, -1, -1, -1, 257 -1, -1, -1, -1, 258 -1, -1, -1, -1, 259 /* TSCF 0*/ 260 -1, -1, -1, -1 261 }; 262 263 /* OPTION_4A */ 264 int p2l_mapping_template_op4a[] = { 265 0, -1, 266 /* TSC4L 0~5 */ 267 2, 3, 4, 5, 268 6, 7, 8, 9, 269 10, 11, 12, 13, 270 14, 15, 16, 17, 271 18, 19, 20, 21, 272 22, 23, 24, 25, 273 /* TSC4Q 0~1 */ 274 26, 27, 28, 29, -1, -1, -1, -1, 275 -1, -1, -1, -1, -1, -1, -1, -1, 276 30, 31, 32, 33, -1, -1, -1, -1, 277 -1, -1, -1, -1, -1, -1, -1, -1, 278 /* TSC 0~6*/ 279 -1, -1, -1, -1, 280 -1, -1, -1, -1, 281 -1, -1, -1, -1, 282 -1, -1, -1, -1, 283 -1, -1, -1, -1, 284 -1, -1, -1, -1, 285 -1, -1, -1, -1, 286 /* TSCF 0*/ 287 -1, -1, -1, -1 288 }; 289 int port_speed_max_template_op4a[] = { 290 0, -1, 291 /* TSC4L 0~5 */ 292 25, 25, 25, 25, 293 25, 25, 25, 25, 294 25, 25, 25, 25, 295 25, 25, 25, 25, 296 25, 25, 25, 25, 297 25, 25, 25, 25, 298 /* TSC4Q 0~1 */ 299 25, 25, 25, 25, -1, -1, -1, -1, 300 -1, -1, -1, -1, -1, -1, -1, -1, 301 25, 25, 25, 25, -1, -1, -1, -1, 302 -1, -1, -1, -1, -1, -1, -1, -1, 303 /* TSC 0~6*/ 304 -1, -1, -1, -1, 305 -1, -1, -1, -1, 306 -1, -1, -1, -1, 307 -1, -1, -1, -1, 308 -1, -1, -1, -1, 309 -1, -1, -1, -1, 310 -1, -1, -1, -1, 311 /* TSCF 0*/ 312 -1, -1, -1, -1 313 }; 314 315 /* OPTION_5 */ 316 int p2l_mapping_template_op5[] = { 317 0, -1, 318 /* TSC4L 0~5 */ 319 2, 3, 4, 5, 320 6, 7, 8, 9, 321 10, 11, 12, 13, 322 14, 15, 16, 17, 323 18, 19, 20, 21, 324 22, 23, 24, 25, 325 /* TSC4Q 0~1 */ 326 26, 27, 28, 29, -1, -1, -1, -1, 327 -1, -1, -1, -1, -1, -1, -1, -1, 328 30, 31, 32, 33, -1, -1, -1, -1, 329 -1, -1, -1, -1, -1, -1, -1, -1, 330 /* TSC 0~6*/ 331 -1, -1, -1, -1, 332 -1, -1, -1, -1, 333 -1, -1, -1, -1, 334 -1, -1, -1, -1, 335 -1, -1, -1, -1, 336 -1, -1, -1, -1, 337 -1, -1, -1, -1, 338 /* TSCF 0*/ 339 -1, -1, -1, -1 340 }; 341 int port_speed_max_template_op5[] = { 342 0, -1, 343 /* TSC4L 0~5 */ 344 25, 25, 25, 25, 345 25, 25, 25, 25, 346 25, 25, 25, 25, 347 25, 25, 25, 25, 348 25, 25, 25, 25, 349 25, 25, 25, 25, 350 /* TSC4Q 0~1 */ 351 25, 25, 25, 25, -1, -1, -1, -1, 352 -1, -1, -1, -1, -1, -1, -1, -1, 353 25, 25, 25, 25, -1, -1, -1, -1, 354 -1, -1, -1, -1, -1, -1, -1, -1, 355 /* TSC 0~6*/ 356 -1, -1, -1, -1, 357 -1, -1, -1, -1, 358 -1, -1, -1, -1, 359 -1, -1, -1, -1, 360 -1, -1, -1, -1, 361 -1, -1, -1, -1, 362 -1, -1, -1, -1, 363 /* TSCF 0*/ 364 -1, -1, -1, -1 365 }; 366 367 /* OPTION_6 */ 368 int p2l_mapping_template_op6[] = { 369 0, -1, 370 /* TSC4L 0~5 */ 371 2, 3, 4, 5, 372 6, 7, 8, 9, 373 10, 11, 12, 13, 374 14, 15, 16, 17, 375 -1, -1, -1, -1, 376 -1, -1, -1, -1, 377 /* TSC4Q 0~1 */ 378 18, 19, 20, 21, 22, 23, 24, 25, 379 26, 27, 28, 29, 30, 31, 32, 33, 380 34, 35, 36, 37, 38, 39, 40, 41, 381 42, 43, 44, 45, 46, 47, 48, 49, 382 /* TSC 0~6*/ 383 -1, -1, -1, -1, 384 -1, -1, -1, -1, 385 -1, -1, -1, -1, 386 -1, -1, -1, -1, 387 -1, -1, -1, -1, 388 -1, -1, -1, -1, 389 -1, -1, -1, -1, 390 /* TSCF 0*/ 391 -1, -1, -1, -1 392 }; 393 int port_speed_max_template_op6[] = { 394 0, -1, 395 /* TSC4L 0~5 */ 396 10, 10, 10, 10, 397 10, 10, 10, 10, 398 10, 10, 10, 10, 399 10, 10, 10, 10, 400 -1, -1, -1, -1, 401 -1, -1, -1, -1, 402 /* TSC4Q 0~1 */ 403 10, 10, 10, 10, 10, 10, 10, 10, 404 10, 10, 10, 10, 10, 10, 10, 10, 405 10, 10, 10, 10, 10, 10, 10, 10, 406 10, 10, 10, 10, 10, 10, 10, 10, 407 /* TSC 0~6*/ 408 -1, -1, -1, -1, 409 -1, -1, -1, -1, 410 -1, -1, -1, -1, 411 -1, -1, -1, -1, 412 -1, -1, -1, -1, 413 -1, -1, -1, -1, 414 -1, -1, -1, -1, 415 /* TSCF 0*/ 416 -1, -1, -1, -1 417 }; 418 419 /* OPTION_7 */ 420 int p2l_mapping_template_op7[] = { 421 0, -1, 422 /* TSC4L 0~5 */ 423 2, 3, 4, 5, 424 -1, -1, -1, -1, 425 -1, -1, -1, -1, 426 -1, -1, -1, -1, 427 -1, -1, -1, -1, 428 -1, -1, -1, -1, 429 /* TSC4Q 0~1 */ 430 -1, -1, -1, -1, -1, -1, -1, -1, 431 -1, -1, -1, -1, -1, -1, -1, -1, 432 -1, -1, -1, -1, -1, -1, -1, -1, 433 -1, -1, -1, -1, -1, -1, -1, -1, 434 /* TSC 0~6*/ 435 -1, -1, -1, -1, 436 -1, -1, -1, -1, 437 -1, -1, -1, -1, 438 -1, -1, -1, -1, 439 -1, -1, -1, -1, 440 -1, -1, -1, -1, 441 -1, -1, -1, -1, 442 /* TSCF 0*/ 443 -1, -1, -1, -1 444 }; 445 int port_speed_max_template_op7[] = { 446 0, -1, 447 /* TSC4L 0~5 */ 448 10, 10, 10, 10, 449 -1, -1, -1, -1, 450 -1, -1, -1, -1, 451 -1, -1, -1, -1, 452 -1, -1, -1, -1, 453 -1, -1, -1, -1, 454 /* TSC4Q 0~1 */ 455 -1, -1, -1, -1, -1, -1, -1, -1, 456 -1, -1, -1, -1, -1, -1, -1, -1, 457 -1, -1, -1, -1, -1, -1, -1, -1, 458 -1, -1, -1, -1, -1, -1, -1, -1, 459 /* TSC 0~6*/ 460 -1, -1, -1, -1, 461 -1, -1, -1, -1, 462 -1, -1, -1, -1, 463 -1, -1, -1, -1, 464 -1, -1, -1, -1, 465 -1, -1, -1, -1, 466 -1, -1, -1, -1, 467 /* TSCF 0*/ 468 -1, -1, -1, -1 469 }; 470 471 /* OPTION_7B */ 472 int p2l_mapping_template_op7b[] = { 473 0, -1, 474 /* TSC4L 0~5 */ 475 -1, -1, -1, -1, 476 -1, -1, -1, -1, 477 -1, -1, -1, -1, 478 -1, -1, -1, -1, 479 -1, -1, -1, -1, 480 -1, -1, -1, -1, 481 /* TSC4Q 0~1 */ 482 -1, -1, -1, -1, -1, -1, -1, -1, 483 -1, -1, -1, -1, -1, -1, -1, -1, 484 -1, -1, -1, -1, -1, -1, -1, -1, 485 -1, -1, -1, -1, -1, -1, -1, -1, 486 /* TSC 0~6*/ 487 -1, -1, -1, -1, 488 -1, -1, -1, -1, 489 -1, -1, -1, -1, 490 -1, -1, -1, -1, 491 -1, -1, -1, -1, 492 -1, -1, -1, -1, 493 -1, -1, -1, -1, 494 /* TSCF 0*/ 495 -1, -1, -1, -1 496 }; 497 int port_speed_max_template_op7b[] = { 498 0, -1, 499 /* TSC4L 0~5 */ 500 -1, -1, -1, -1, 501 -1, -1, -1, -1, 502 -1, -1, -1, -1, 503 -1, -1, -1, -1, 504 -1, -1, -1, -1, 505 -1, -1, -1, -1, 506 /* TSC4Q 0~1 */ 507 -1, -1, -1, -1, -1, -1, -1, -1, 508 -1, -1, -1, -1, -1, -1, -1, -1, 509 -1, -1, -1, -1, -1, -1, -1, -1, 510 -1, -1, -1, -1, -1, -1, -1, -1, 511 /* TSC 0~6*/ 512 -1, -1, -1, -1, 513 -1, -1, -1, -1, 514 -1, -1, -1, -1, 515 -1, -1, -1, -1, 516 -1, -1, -1, -1, 517 -1, -1, -1, -1, 518 -1, -1, -1, -1, 519 /* TSCF 0*/ 520 -1, -1, -1, -1 521 }; 522 523 /* OPTION_8B */ 524 int p2l_mapping_template_op8b[] = { 525 0, -1, 526 /* TSC4L 0~5 */ 527 -1, -1, -1, -1, 528 -1, -1, -1, -1, 529 -1, -1, -1, -1, 530 -1, -1, -1, -1, 531 -1, -1, -1, -1, 532 2, 3, 4, 5, 533 /* TSC4Q 0~1 */ 534 6, 7, 8, 9, -1, -1, -1, -1, 535 -1, -1, -1, -1, -1, -1, -1, -1, 536 10, 11, 12, 13, -1, -1, -1, -1, 537 -1, -1, -1, -1, -1, -1, -1, -1, 538 /* TSC 0~6*/ 539 -1, -1, -1, -1, 540 -1, -1, -1, -1, 541 -1, -1, -1, -1, 542 -1, -1, -1, -1, 543 -1, -1, -1, -1, 544 -1, -1, -1, -1, 545 -1, -1, -1, -1, 546 /* TSCF 0*/ 547 -1, -1, -1, -1 548 }; 549 int port_speed_max_template_op8b[] = { 550 0, -1, 551 /* TSC4L 0~5 */ 552 -1, -1, -1, -1, 553 -1, -1, -1, -1, 554 -1, -1, -1, -1, 555 -1, -1, -1, -1, 556 -1, -1, -1, -1, 557 25, 25, 25, 25, 558 /* TSC4Q 0~1 */ 559 25, 25, 25, 25, -1, -1, -1, -1, 560 -1, -1, -1, -1, -1, -1, -1, -1, 561 25, 25, 25, 25, -1, -1, -1, -1, 562 -1, -1, -1, -1, -1, -1, -1, -1, 563 /* TSC 0~6*/ 564 -1, -1, -1, -1, 565 -1, -1, -1, -1, 566 -1, -1, -1, -1, 567 -1, -1, -1, -1, 568 -1, -1, -1, -1, 569 -1, -1, -1, -1, 570 -1, -1, -1, -1, 571 /* TSCF 0*/ 572 -1, -1, -1, -1 573 }; 574 575 /* OPTION_9B */ 576 int p2l_mapping_template_op9b[] = { 577 0, -1, 578 /* TSC4L 0~5 */ 579 2, 3, 4, 5, 580 6, 7, 8, 9, 581 10, 11, 12, 13, 582 14, 15, 16, 17, 583 -1, -1, -1, -1, 584 -1, -1, -1, -1, 585 /* TSC4Q 0~1 */ 586 18, 19, 20, 21, 22, 23, 24, 25, 587 26, 27, 28, 29, 30, 31, 32, 33, 588 34, 35, 36, 37, 38, 39, 40, 41, 589 42, 43, 44, 45, 46, 47, 48, 49, 590 /* TSC 0~6*/ 591 -1, -1, -1, -1, 592 -1, -1, -1, -1, 593 -1, -1, -1, -1, 594 -1, -1, -1, -1, 595 -1, -1, -1, -1, 596 -1, -1, -1, -1, 597 -1, -1, -1, -1, 598 /* TSCF 0*/ 599 -1, -1, -1, -1 600 }; 601 int port_speed_max_template_op9b[] = { 602 0, -1, 603 /* TSC4L 0~5 */ 604 10, 10, 10, 10, 605 10, 10, 10, 10, 606 10, 10, 10, 10, 607 10, 10, 10, 10, 608 -1, -1, -1, -1, 609 -1, -1, -1, -1, 610 /* TSC4Q 0~1 */ 611 10, 10, 10, 10, 10, 10, 10, 10, 612 10, 10, 10, 10, 10, 10, 10, 10, 613 10, 10, 10, 10, 10, 10, 10, 10, 614 10, 10, 10, 10, 10, 10, 10, 10, 615 /* TSC 0~6*/ 616 -1, -1, -1, -1, 617 -1, -1, -1, -1, 618 -1, -1, -1, -1, 619 -1, -1, -1, -1, 620 -1, -1, -1, -1, 621 -1, -1, -1, -1, 622 -1, -1, -1, -1, 623 /* TSCF 0*/ 624 -1, -1, -1, -1 625 }; 626 627 /* OPTION_10B */ 628 int p2l_mapping_template_op10b[] = { 629 0, -1, 630 /* TSC4L 0~5 */ 631 2, 3, 4, 5, 632 6, 7, 8, 9, 633 10, 11, 12, 13, 634 14, 15, 16, 17, 635 18, 19, 20, 21, 636 22, 23, 24, 25, 637 /* TSC4Q 0~1 */ 638 26, 27, 28, 29, -1, -1, -1, -1, 639 -1, -1, -1, -1, -1, -1, -1, -1, 640 30, 31, 32, 33, -1, -1, -1, -1, 641 -1, -1, -1, -1, -1, -1, -1, -1, 642 /* TSC 0~6*/ 643 -1, -1, -1, -1, 644 -1, -1, -1, -1, 645 -1, -1, -1, -1, 646 -1, -1, -1, -1, 647 -1, -1, -1, -1, 648 -1, -1, -1, -1, 649 -1, -1, -1, -1, 650 /* TSCF 0*/ 651 -1, -1, -1, -1 652 }; 653 int port_speed_max_template_op10b[] = { 654 0, -1, 655 /* TSC4L 0~5 */ 656 10, 10, 10, 10, 657 10, 10, 10, 10, 658 10, 10, 10, 10, 659 10, 10, 10, 10, 660 10, 10, 10, 10, 661 10, 10, 10, 10, 662 /* TSC4Q 0~1 */ 663 10, 10, 10, 10, -1, -1, -1, -1, 664 -1, -1, -1, -1, -1, -1, -1, -1, 665 10, 10, 10, 10, -1, -1, -1, -1, 666 -1, -1, -1, -1, -1, -1, -1, -1, 667 /* TSC 0~6*/ 668 -1, -1, -1, -1, 669 -1, -1, -1, -1, 670 -1, -1, -1, -1, 671 -1, -1, -1, -1, 672 -1, -1, -1, -1, 673 -1, -1, -1, -1, 674 -1, -1, -1, -1, 675 /* TSCF 0*/ 676 -1, -1, -1, -1 677 }; 678 679 /* OPTION_11B */ 680 int p2l_mapping_template_op11b[] = { 681 0, -1, 682 /* TSC4L 0~5 */ 683 -1, -1, -1, -1, 684 -1, -1, -1, -1, 685 -1, -1, -1, -1, 686 -1, -1, -1, -1, 687 -1, -1, -1, -1, 688 -1, -1, -1, -1, 689 /* TSC4Q 0~1 */ 690 2, 3, 4, 5, 6, 7, 8, 9, 691 10, 11, 12, 13, 14, 15, 16, 17, 692 18, 19, 20, 21, 22, 23, 24, 25, 693 26, 27, 28, 29, 30, 31, 32, 33, 694 /* TSC 0~6*/ 695 -1, -1, -1, -1, 696 -1, -1, -1, -1, 697 -1, -1, -1, -1, 698 -1, -1, -1, -1, 699 -1, -1, -1, -1, 700 -1, -1, -1, -1, 701 -1, -1, -1, -1, 702 /* TSCF 0*/ 703 -1, -1, -1, -1 704 }; 705 int port_speed_max_template_op11b[] = { 706 0, -1, 707 /* TSC4L 0~5 */ 708 -1, -1, -1, -1, 709 -1, -1, -1, -1, 710 -1, -1, -1, -1, 711 -1, -1, -1, -1, 712 -1, -1, -1, -1, 713 -1, -1, -1, -1, 714 /* TSC4Q 0~1 */ 715 10, 10, 10, 10, 10, 10, 10, 10, 716 10, 10, 10, 10, 10, 10, 10, 10, 717 10, 10, 10, 10, 10, 10, 10, 10, 718 10, 10, 10, 10, 10, 10, 10, 10, 719 /* TSC 0~6*/ 720 -1, -1, -1, -1, 721 -1, -1, -1, -1, 722 -1, -1, -1, -1, 723 -1, -1, -1, -1, 724 -1, -1, -1, -1, 725 -1, -1, -1, -1, 726 -1, -1, -1, -1, 727 /* TSCF 0*/ 728 -1, -1, -1, -1 729 }; 730 731 /* OPTION_12B */ 732 int p2l_mapping_template_op12b[] = { 733 0, -1, 734 /* TSC4L 0~5 */ 735 -1, -1, -1, -1, 736 -1, -1, -1, -1, 737 -1, -1, -1, -1, 738 -1, -1, -1, -1, 739 -1, -1, -1, -1, 740 -1, -1, -1, -1, 741 /* TSC4Q 0~1 */ 742 -1, -1, -1, -1, -1, -1, -1, -1, 743 -1, -1, -1, -1, -1, -1, -1, -1, 744 -1, -1, -1, -1, -1, -1, -1, -1, 745 -1, -1, -1, -1, -1, -1, -1, -1, 746 /* TSC 0~6*/ 747 -1, -1, -1, -1, 748 -1, -1, -1, -1, 749 -1, -1, -1, -1, 750 -1, -1, -1, -1, 751 -1, -1, -1, -1, 752 -1, -1, -1, -1, 753 -1, -1, -1, -1, 754 /* TSCF 0*/ 755 -1, -1, -1, -1 756 }; 757 int port_speed_max_template_op12b[] = { 758 0, -1, 759 /* TSC4L 0~5 */ 760 -1, -1, -1, -1, 761 -1, -1, -1, -1, 762 -1, -1, -1, -1, 763 -1, -1, -1, -1, 764 -1, -1, -1, -1, 765 -1, -1, -1, -1, 766 /* TSC4Q 0~1 */ 767 -1, -1, -1, -1, -1, -1, -1, -1, 768 -1, -1, -1, -1, -1, -1, -1, -1, 769 -1, -1, -1, -1, -1, -1, -1, -1, 770 -1, -1, -1, -1, -1, -1, -1, -1, 771 /* TSC 0~6*/ 772 -1, -1, -1, -1, 773 -1, -1, -1, -1, 774 -1, -1, -1, -1, 775 -1, -1, -1, -1, 776 -1, -1, -1, -1, 777 -1, -1, -1, -1, 778 -1, -1, -1, -1, 779 /* TSCF 0*/ 780 -1, -1, -1, -1 781 }; 782 783 /* OPTION_12 */ 784 int p2l_mapping_template_op12[] = { 785 0, -1, 786 /* TSC4L 0~5 */ 787 2, 3, 4, 5, 788 -1, -1, -1, -1, 789 -1, -1, -1, -1, 790 -1, -1, -1, -1, 791 -1, -1, -1, -1, 792 -1, -1, -1, -1, 793 /* TSC4Q 0~1 */ 794 -1, -1, -1, -1, -1, -1, -1, -1, 795 -1, -1, -1, -1, -1, -1, -1, -1, 796 -1, -1, -1, -1, -1, -1, -1, -1, 797 -1, -1, -1, -1, -1, -1, -1, -1, 798 /* TSC 0~6*/ 799 -1, -1, -1, -1, 800 -1, -1, -1, -1, 801 -1, -1, -1, -1, 802 -1, -1, -1, -1, 803 -1, -1, -1, -1, 804 -1, -1, -1, -1, 805 -1, -1, -1, -1, 806 /* TSCF 0*/ 807 -1, -1, -1, -1 808 }; 809 int port_speed_max_template_op12[] = { 810 0, -1, 811 /* TSC4L 0~5 */ 812 10, 10, 10, 10, 813 -1, -1, -1, -1, 814 -1, -1, -1, -1, 815 -1, -1, -1, -1, 816 -1, -1, -1, -1, 817 -1, -1, -1, -1, 818 /* TSC4Q 0~1 */ 819 -1, -1, -1, -1, -1, -1, -1, -1, 820 -1, -1, -1, -1, -1, -1, -1, -1, 821 -1, -1, -1, -1, -1, -1, -1, -1, 822 -1, -1, -1, -1, -1, -1, -1, -1, 823 /* TSC 0~6*/ 824 -1, -1, -1, -1, 825 -1, -1, -1, -1, 826 -1, -1, -1, -1, 827 -1, -1, -1, -1, 828 -1, -1, -1, -1, 829 -1, -1, -1, -1, 830 -1, -1, -1, -1, 831 /* TSCF 0*/ 832 -1, -1, -1, -1 833 }; 834 835 /* OPTION_13 */ 836 int p2l_mapping_template_op13[] = { 837 0, -1, 838 /* TSC4L 0~5 */ 839 2, 3, 4, 5, 840 6, 7, 8, 9, 841 10, 11, 12, 13, 842 14, 15, 16, 17, 843 18, 19, 20, 21, 844 22, 23, 24, 25, 845 /* TSC4Q 0~1 */ 846 -1, -1, -1, -1, -1, -1, -1, -1, 847 -1, -1, -1, -1, -1, -1, -1, -1, 848 -1, -1, -1, -1, -1, -1, -1, -1, 849 -1, -1, -1, -1, -1, -1, -1, -1, 850 /* TSC 0~6*/ 851 -1, -1, -1, -1, 852 -1, -1, -1, -1, 853 -1, -1, -1, -1, 854 -1, -1, -1, -1, 855 -1, -1, -1, -1, 856 -1, -1, -1, -1, 857 -1, -1, -1, -1, 858 /* TSCF 0*/ 859 -1, -1, -1, -1 860 }; 861 int port_speed_max_template_op13[] = { 862 0, -1, 863 /* TSC4L 0~5 */ 864 10, 10, 10, 10, 865 10, 10, 10, 10, 866 10, 10, 10, 10, 867 10, 10, 10, 10, 868 10, 10, 10, 10, 869 10, 10, 10, 10, 870 /* TSC4Q 0~1 */ 871 -1, -1, -1, -1, -1, -1, -1, -1, 872 -1, -1, -1, -1, -1, -1, -1, -1, 873 -1, -1, -1, -1, -1, -1, -1, -1, 874 -1, -1, -1, -1, -1, -1, -1, -1, 875 /* TSC 0~6*/ 876 -1, -1, -1, -1, 877 -1, -1, -1, -1, 878 -1, -1, -1, -1, 879 -1, -1, -1, -1, 880 -1, -1, -1, -1, 881 -1, -1, -1, -1, 882 -1, -1, -1, -1, 883 /* TSCF 0*/ 884 -1, -1, -1, -1 885 }; 886 887 /* OPTION_14 */ 888 int p2l_mapping_template_op14[] = { 889 0, -1, 890 /* TSC4L 0~5 */ 891 2, 3, 4, 5, 892 6, 7, 8, 9, 893 10, 11, 12, 13, 894 14, 15, 16, 17, 895 -1, -1, -1, -1, 896 -1, -1, -1, -1, 897 /* TSC4Q 0~1 */ 898 -1, -1, -1, -1, -1, -1, -1, -1, 899 -1, -1, -1, -1, -1, -1, -1, -1, 900 -1, -1, -1, -1, -1, -1, -1, -1, 901 -1, -1, -1, -1, -1, -1, -1, -1, 902 /* TSC 0~6*/ 903 -1, -1, -1, -1, 904 -1, -1, -1, -1, 905 -1, -1, -1, -1, 906 -1, -1, -1, -1, 907 -1, -1, -1, -1, 908 -1, -1, -1, -1, 909 -1, -1, -1, -1, 910 /* TSCF 0*/ 911 -1, -1, -1, -1 912 }; 913 int port_speed_max_template_op14[] = { 914 0, -1, 915 /* TSC4L 0~5 */ 916 10, 10, 10, 10, 917 10, 10, 10, 10, 918 10, 10, 10, 10, 919 10, 10, 10, 10, 920 -1, -1, -1, -1, 921 -1, -1, -1, -1, 922 /* TSC4Q 0~1 */ 923 -1, -1, -1, -1, -1, -1, -1, -1, 924 -1, -1, -1, -1, -1, -1, -1, -1, 925 -1, -1, -1, -1, -1, -1, -1, -1, 926 -1, -1, -1, -1, -1, -1, -1, -1, 927 /* TSC 0~6*/ 928 -1, -1, -1, -1, 929 -1, -1, -1, -1, 930 -1, -1, -1, -1, 931 -1, -1, -1, -1, 932 -1, -1, -1, -1, 933 -1, -1, -1, -1, 934 -1, -1, -1, -1, 935 /* TSCF 0*/ 936 -1, -1, -1, -1 937 }; 938 939 /* Below options defined in PRD 4.7*/ 940 /* OPTION_2_0, 24P 2.5G + 32P 10G */ 941 static int p2l_mapping_op2_0[] = { 942 0, -1, 943 /* TSC4L 0~5 */ 944 2, 3, 4, 5, 945 6, 7, 8, 9, 946 10, 11, 12, 13, 947 14, 15, 16, 17, 948 18, 19, 20, 21, 949 22, 23, 24, 25, 950 /* TSC4Q 0~1 */ 951 -1, -1, -1, -1, -1, -1, -1, -1, 952 -1, -1, -1, -1, -1, -1, -1, -1, 953 -1, -1, -1, -1, -1, -1, -1, -1, 954 -1, -1, -1, -1, -1, -1, -1, -1, 955 /* TSC 0~6*/ 956 26, 27, 28, 29, 957 30, 31, 32, 33, 958 34, 35, 36, 37, 959 38, 39, 40, 41, 960 42, 43, 44, 45, 961 46, 47, 48, 49, 962 50, 51, 52, 53, 963 /* TSCF 0*/ 964 54, 55, 56, 57 965 }; 966 static int port_speed_max_op2_0[] = { 967 0, -1, 968 /* TSC4L 0~5 */ 969 25, 25, 25, 25, 970 25, 25, 25, 25, 971 25, 25, 25, 25, 972 25, 25, 25, 25, 973 25, 25, 25, 25, 974 25, 25, 25, 25, 975 /* TSC4Q 0~1 */ 976 -1, -1, -1, -1, -1, -1, -1, -1, 977 -1, -1, -1, -1, -1, -1, -1, -1, 978 -1, -1, -1, -1, -1, -1, -1, -1, 979 -1, -1, -1, -1, -1, -1, -1, -1, 980 /* TSC 0~6*/ 981 110, 110, 110, 110, 982 110, 110, 110, 110, 983 110, 110, 110, 110, 984 110, 110, 110, 110, 985 110, 110, 110, 110, 986 110, 110, 110, 110, 987 110, 110, 110, 110, 988 /* TSCF 0*/ 989 110, 110, 110, 110, 990 }; 991 uint32 tdm_table_op2_0[305] = { 992 58, 62, 66, 70, 74, 2, 78, 82, 86, 59, 993 63, 3, 67, 71, 75, 79, 83, 4, 87, 60, 994 64, 68, 72, 5, 76, 80, 84, 88, 61, 6, 995 65, 69, 73, 77, 81, 7, 85, 89, 58, 62, 996 66, 70, 74, 8, 78, 82, 86, 59, 63, 9, 997 67, 71, 75, 79, 83, 10, 87, 60, 64, 68, 998 72, 11, 76, 80, 84, 88, 61, 12, 65, 69, 999 73, 77, 81, 13, 85, 89, 58, 62, 66, 70, 1000 74, 14, 78, 82, 86, 59, 63, 15, 67, 71, 1001 75, 79, 83, 16, 87, 60, 64, 68, 72, 17, 1002 76, 80, 84, 88, 61, 18, 65, 69, 73, 77, 1003 81, 19, 85, 89, 58, 62, 66, 70, 74, 20, 1004 78, 82, 86, 59, 63, 21, 67, 71, 75, 79, 1005 83, 22, 87, 60, 64, 68, 72, 23, 76, 80, 1006 84, 88, 61, 24, 65, 69, 73, 77, 81, 25, 1007 85, 89, 58, 62, 66, 70, 74, 2, 78, 82, 1008 86, 59, 63, 3, 67, 71, 75, 79, 83, 4, 1009 87, 60, 64, 68, 72, 5, 76, 80, 84, 88, 1010 61, 6, 65, 69, 73, 77, 81, 7, 85, 89, 1011 58, 62, 66, 70, 74, 8, 78, 82, 86, 59, 1012 63, 9, 67, 71, 75, 79, 83, 10, 87, 60, 1013 64, 68, 72, 11, 76, 80, 84, 88, 61, 12, 1014 65, 69, 73, 77, 81, 13, 85, 89, 58, 62, 1015 66, 70, 74, 14, 78, 82, 86, 59, 63, 15, 1016 67, 71, 75, 79, 83, 16, 87, 60, 64, 68, 1017 72, 17, 76, 80, 84, 88, 61, 18, 65, 69, 1018 73, 77, 81, 19, 85, 89, 58, 62, 66, 70, 1019 74, 20, 78, 82, 86, 59, 63, 21, 67, 71, 1020 75, 79, 83, 22, 87, 60, 64, 68, 72, 23, 1021 76, 80, 84, 88, 61, 24, 65, 69, 73, 77, 1022 81, 25, 85, 89, 0 1023 }; 1024 1025 /* OPTION_2_2, 24*2.5G + 16*10G + 4*40G */ 1026 static int p2l_mapping_op2_2[] = { 1027 0, -1, 1028 /* TSC4L 0~5 */ 1029 2, 3, 4, 5, 1030 6, 7, 8, 9, 1031 10, 11, 12, 13, 1032 14, 15, 16, 17, 1033 18, 19, 20, 21, 1034 22, 23, 24, 25, 1035 /* TSC4Q 0~1 */ 1036 -1, -1, -1, -1, -1, -1, -1, -1, 1037 -1, -1, -1, -1, -1, -1, -1, -1, 1038 -1, -1, -1, -1, -1, -1, -1, -1, 1039 -1, -1, -1, -1, -1, -1, -1, -1, 1040 /* TSC 0~6*/ 1041 26, 27, 28, 29, 1042 30, 31, 32, 33, 1043 34, 35, 36, 37, 1044 38, 39, 40, 41, 1045 42, -1, -1, -1, 1046 43, -1, -1, -1, 1047 44, -1, -1, -1, 1048 /* TSCF 0*/ 1049 45, -1, -1, -1 1050 }; 1051 1052 static int port_speed_max_op2_2[] = { 1053 0, -1, 1054 /* TSC4L 0~5 */ 1055 25, 25, 25, 25, 1056 25, 25, 25, 25, 1057 25, 25, 25, 25, 1058 25, 25, 25, 25, 1059 25, 25, 25, 25, 1060 25, 25, 25, 25, 1061 /* TSC4Q 0~1 */ 1062 -1, -1, -1, -1, -1, -1, -1, -1, 1063 -1, -1, -1, -1, -1, -1, -1, -1, 1064 -1, -1, -1, -1, -1, -1, -1, -1, 1065 -1, -1, -1, -1, -1, -1, -1, -1, 1066 /* TSC 0~6*/ 1067 110, 110, 110, 110, 1068 110, 110, 110, 110, 1069 110, 110, 110, 110, 1070 110, 110, 110, 110, 1071 420, -1, -1, -1, 1072 420, -1, -1, -1, 1073 420, -1, -1, -1, 1074 /* TSCF 0*/ 1075 420, -1, -1, -1 1076 }; 1077 1078 uint32 tdm_table_op2_2[305] = { 1079 58, 62, 66, 70, 74, 2, 78, 82, 86, 59, 1080 63, 3, 67, 71, 74, 78, 82, 4, 86, 60, 1081 64, 68, 72, 5, 74, 78, 82, 86, 61, 6, 1082 65, 69, 73, 74, 78, 7, 82, 86, 58, 62, 1083 66, 70, 74, 8, 78, 82, 86, 59, 63, 9, 1084 67, 71, 74, 78, 82, 10, 86, 60, 64, 68, 1085 72, 11, 74, 78, 82, 86, 61, 12, 65, 69, 1086 73, 74, 78, 13, 82, 86, 58, 62, 66, 70, 1087 74, 14, 78, 82, 86, 59, 63, 15, 67, 71, 1088 74, 78, 82, 16, 86, 60, 64, 68, 72, 17, 1089 74, 78, 82, 86, 61, 18, 65, 69, 73, 74, 1090 78, 19, 82, 86, 58, 62, 66, 70, 74, 20, 1091 78, 82, 86, 59, 63, 21, 67, 71, 74, 78, 1092 82, 22, 86, 60, 64, 68, 72, 23, 74, 78, 1093 82, 86, 61, 24, 65, 69, 73, 74, 78, 25, 1094 82, 86, 58, 62, 66, 70, 74, 2, 78, 82, 1095 86, 59, 63, 3, 67, 71, 74, 78, 82, 4, 1096 86, 60, 64, 68, 72, 5, 74, 78, 82, 86, 1097 61, 6, 65, 69, 73, 74, 78, 7, 82, 86, 1098 58, 62, 66, 70, 74, 8, 78, 82, 86, 59, 1099 63, 9, 67, 71, 74, 78, 82, 10, 86, 60, 1100 64, 68, 72, 11, 74, 78, 82, 86, 61, 12, 1101 65, 69, 73, 74, 78, 13, 82, 86, 58, 62, 1102 66, 70, 74, 14, 78, 82, 86, 59, 63, 15, 1103 67, 71, 74, 78, 82, 16, 86, 60, 64, 68, 1104 72, 17, 74, 78, 82, 86, 61, 18, 65, 69, 1105 73, 74, 78, 19, 82, 86, 58, 62, 66, 70, 1106 74, 20, 78, 82, 86, 59, 63, 21, 67, 71, 1107 74, 78, 82, 22, 86, 60, 64, 68, 72, 23, 1108 74, 78, 82, 86, 61, 24, 65, 69, 73, 74, 1109 78, 25, 82, 86, 0 1110 }; 1111 1112 /* OPTION_2_3, 24x2.5G + 24x10G + 2x40G */ 1113 static int p2l_mapping_op2_3[] = { 1114 0, -1, 1115 /* TSC4L 0~5 */ 1116 2, 3, 4, 5, 1117 6, 7, 8, 9, 1118 10, 11, 12, 13, 1119 14, 15, 16, 17, 1120 18, 19, 20, 21, 1121 22, 23, 24, 25, 1122 /* TSC4Q 0~1 */ 1123 -1, -1, -1, -1, -1, -1, -1, -1, 1124 -1, -1, -1, -1, -1, -1, -1, -1, 1125 -1, -1, -1, -1, -1, -1, -1, -1, 1126 -1, -1, -1, -1, -1, -1, -1, -1, 1127 /* TSC 0~6*/ 1128 26, 27, 28, 29, 1129 30, 31, 32, 33, 1130 34, 35, 36, 37, 1131 38, 39, 40, 41, 1132 42, 43, 44, 45, 1133 46, 47, 48, 49, 1134 50, -1, -1, -1, 1135 /* TSCF 0*/ 1136 51, -1, -1, -1 1137 }; 1138 1139 static int port_speed_max_op2_3[] = { 1140 0, -1, 1141 /* TSC4L 0~5 */ 1142 25, 25, 25, 25, 1143 25, 25, 25, 25, 1144 25, 25, 25, 25, 1145 25, 25, 25, 25, 1146 25, 25, 25, 25, 1147 25, 25, 25, 25, 1148 /* TSC4Q 0~1 */ 1149 -1, -1, -1, -1, -1, -1, -1, -1, 1150 -1, -1, -1, -1, -1, -1, -1, -1, 1151 -1, -1, -1, -1, -1, -1, -1, -1, 1152 -1, -1, -1, -1, -1, -1, -1, -1, 1153 /* TSC 0~6*/ 1154 110, 110, 110, 110, 1155 110, 110, 110, 110, 1156 110, 110, 110, 110, 1157 110, 110, 110, 110, 1158 110, 110, 110, 110, 1159 110, 110, 110, 110, 1160 420, -1, -1, -1, 1161 /* TSCF 0*/ 1162 420, -1, -1, -1 1163 }; 1164 1165 uint32 tdm_table_op2_3[305] = { 1166 82, 86, 58, 60, 62, 64, 66, 68, 70, 82, 1167 86, 72, 74, 76, 78, 80, 2, 10, 18, 82, 1168 86, 59, 61, 63, 65, 67, 69, 71, 82, 86, 1169 73, 75, 77, 79, 81, 3, 11, 19, 82, 86, 1170 58, 60, 62, 64, 66, 68, 70, 82, 86, 72, 1171 74, 76, 78, 80, 4, 12, 20, 82, 86, 59, 1172 61, 63, 65, 67, 69, 71, 82, 86, 73, 75, 1173 77, 79, 81, 5, 13, 21, 82, 86, 58, 60, 1174 62, 64, 66, 68, 70, 82, 86, 72, 74, 76, 1175 78, 80, 6, 14, 22, 82, 86, 59, 61, 63, 1176 65, 67, 69, 71, 82, 86, 73, 75, 77, 79, 1177 81, 7, 15, 23, 82, 86, 58, 60, 62, 64, 1178 66, 68, 70, 82, 86, 72, 74, 76, 78, 80, 1179 8, 16, 24, 82, 86, 59, 61, 63, 65, 67, 1180 69, 71, 82, 86, 73, 75, 77, 79, 81, 9, 1181 17, 25, 82, 86, 58, 60, 62, 64, 66, 68, 1182 70, 72, 82, 86, 74, 76, 78, 80, 2, 10, 1183 18, 82, 86, 59, 61, 63, 65, 67, 69, 71, 1184 73, 82, 86, 75, 77, 79, 81, 3, 11, 19, 1185 82, 86, 58, 60, 62, 64, 66, 68, 70, 72, 1186 82, 86, 74, 76, 78, 80, 4, 12, 20, 82, 1187 86, 59, 61, 63, 65, 67, 69, 71, 73, 82, 1188 86, 75, 77, 79, 81, 5, 13, 21, 82, 86, 1189 58, 60, 62, 64, 66, 68, 70, 72, 82, 86, 1190 74, 76, 78, 80, 6, 14, 22, 82, 86, 59, 1191 61, 63, 65, 67, 69, 71, 73, 82, 86, 75, 1192 77, 79, 81, 7, 15, 23, 82, 86, 58, 60, 1193 62, 64, 66, 68, 70, 72, 82, 86, 74, 76, 1194 78, 80, 8, 16, 24, 82, 86, 59, 61, 63, 1195 65, 67, 69, 71, 73, 82, 86, 75, 77, 79, 1196 81, 9, 17, 25, 0 1197 }; 1198 1199 /* OPTION_5_2, 52*2.5G + 8*10G + 2*50G */ 1200 static int p2l_mapping_op5_2[] = { 1201 0, -1, 1202 /* TSC4L 0~5 */ 1203 2, 3, 4, 5, 1204 6, 7, 8, 9, 1205 10, 11, 12, 13, 1206 14, 15, 16, 17, 1207 18, 19, 20, 21, 1208 22, 23, 24, 25, 1209 /* TSC4Q 0~1 */ 1210 26, 27, 28, 29, -1, -1, -1, -1, 1211 -1, -1, -1, -1, -1, -1, -1, -1, 1212 30, 31, 32, 33, -1, -1, -1, -1, 1213 -1, -1, -1, -1, -1, -1, -1, -1, 1214 /* TSC 0~6*/ 1215 34, 35, 36, 37, 1216 38, 39, 40, 41, 1217 42, 43, 44, 45, 1218 46, 47, 48, 49, 1219 50, 51, 52, 53, 1220 54, 55, 56, 57, 1221 58, 59, 60, 61, 1222 /* TSCF 0*/ 1223 62, -1, 63, -1 1224 }; 1225 1226 static int port_speed_max_op5_2[] = { 1227 0, -1, 1228 /* TSC4L 0~5 */ 1229 25, 25, 25, 25, 1230 25, 25, 25, 25, 1231 25, 25, 25, 25, 1232 25, 25, 25, 25, 1233 25, 25, 25, 25, 1234 25, 25, 25, 25, 1235 /* TSC4Q 0~1 */ 1236 25, 25, 25, 25, -1, -1, -1, -1, 1237 -1, -1, -1, -1, -1, -1, -1, -1, 1238 25, 25, 25, 25, -1, -1, -1, -1, 1239 -1, -1, -1, -1, -1, -1, -1, -1, 1240 /* TSC 0~6*/ 1241 25, 25, 25, 25, 1242 25, 25, 25, 25, 1243 25, 25, 25, 25, 1244 25, 25, 25, 25, 1245 110, 110, 110, 110, 1246 25, 25, 25, 25, 1247 110, 110, 110, 110, 1248 /* TSCF 0*/ 1249 530, -1, 530, -1 1250 }; 1251 1252 uint32 tdm_table_op5_2[126] = { 1253 72, 127, 86, 74, 76, 88, 84, 3, 86, 14, 1254 25, 88, 82, 42, 86, 61, 79, 88, 75, 77, 1255 28, 86, 85, 4, 88, 15, 18, 86, 83, 58, 1256 88, 66, 70, 86, 74, 76, 88, 84, 5, 63, 1257 86, 16, 19, 88, 82, 43, 86, 81, 68, 88, 1258 75, 77, 86, 85, 6, 88, 17, 20, 86, 83, 1259 29, 64, 88, 73, 0, 86, 74, 76, 88, 84, 1260 7, 86, 10, 21, 88, 82, 44, 86, 60, 78, 1261 88, 75, 77, 85, 86, 26, 8, 88, 11, 22, 1262 86, 83, 59, 88, 67, 71, 86, 74, 76, 88, 1263 84, 9, 62, 86, 12, 23, 88, 82, 45, 86, 1264 80, 69, 88, 75, 77, 86, 85, 2, 88, 13, 1265 27, 86, 24, 83, 65, 88 1266 }; 1267 1268 /* OPTION_9B_0, 48*1G + 40G RioT + 8*10G + 4*25G */ 1269 static int p2l_mapping_op9b_0[] = { 1270 0, -1, 1271 /* TSC4L 0~5 */ 1272 2, 3, 4, 5, 1273 6, 7, 8, 9, 1274 10, 11, 12, 13, 1275 14, 15, 16, 17, 1276 -1, -1, -1, -1, 1277 -1, -1, -1, -1, 1278 /* TSC4Q 0~1 */ 1279 18, 19, 20, 21, 22, 23, 24, 25, 1280 26, 27, 28, 29, 30, 31, 32, 33, 1281 34, 35, 36, 37, 38, 39, 40, 41, 1282 42, 43, 44, 45, 46, 47, 48, 49, 1283 /* TSC 0~6*/ 1284 -1, -1, -1, -1, 1285 -1, -1, -1, -1, 1286 -1, -1, -1, -1, 1287 50, -1, -1, -1, 1288 51, 52, 53, 54, 1289 55, -1, -1, -1, 1290 56, 57, 58, 59, 1291 /* TSCF 0*/ 1292 60, 61, 62, 63 1293 }; 1294 1295 static int port_speed_max_op9b_0[] = { 1296 0, -1, 1297 /* TSC4L 0~5 */ 1298 10, 10, 10, 10, 1299 10, 10, 10, 10, 1300 10, 10, 10, 10, 1301 10, 10, 10, 10, 1302 -1, -1, -1, -1, 1303 -1, -1, -1, -1, 1304 /* TSC4Q 0~1 */ 1305 10, 10, 10, 10, 10, 10, 10, 10, 1306 10, 10, 10, 10, 10, 10, 10, 10, 1307 10, 10, 10, 10, 10, 10, 10, 10, 1308 10, 10, 10, 10, 10, 10, 10, 10, 1309 /* TSC 0~6*/ 1310 -1, -1, -1, -1, 1311 -1, -1, -1, -1, 1312 -1, -1, -1, -1, 1313 420, -1, -1, -1, 1314 110, 110, 110, 110, 1315 420, -1, -1, -1, 1316 110, 110, 110, 110, 1317 /* TSCF 0*/ 1318 250, 250, 250, 250 1319 }; 1320 1321 uint32 tdm_table_op9b_0[309] = { 1322 77, 87, 29, 78, 11, 88, 70, 83, 89, 74, 1323 86, 78, 76, 70, 87, 84, 34, 88, 2, 78, 1324 89, 70, 82, 86, 52, 75, 78, 87, 77, 70, 1325 88, 85, 89, 57, 78, 86, 70, 45, 83, 87, 1326 30, 88, 78, 74, 70, 89, 76, 84, 86, 78, 1327 12, 87, 70, 82, 88, 35, 3, 78, 89, 75, 1328 70, 86, 77, 87, 85, 78, 88, 70, 53, 89, 1329 83, 76, 74, 78, 86, 70, 87, 84, 46, 88, 1330 78, 54, 89, 70, 82, 86, 31, 75, 78, 87, 1331 70, 88, 77, 85, 89, 4, 78, 86, 70, 83, 1332 87, 13, 74, 88, 78, 76, 70, 89, 84, 36, 1333 86, 78, 47, 87, 70, 82, 88, 77, 89, 78, 1334 75, 70, 86, 85, 32, 87, 14, 78, 88, 70, 1335 83, 89, 37, 56, 78, 86, 74, 70, 87, 76, 1336 84, 88, 78, 5, 89, 70, 82, 86, 75, 87, 1337 78, 77, 70, 88, 85, 48, 89, 38, 78, 86, 1338 70, 83, 87, 74, 88, 78, 76, 15, 70, 89, 1339 84, 86, 6, 78, 87, 70, 33, 82, 88, 77, 1340 89, 78, 75, 70, 86, 85, 55, 87, 78, 49, 1341 88, 70, 83, 89, 74, 86, 78, 76, 87, 70, 1342 26, 84, 88, 0, 78, 89, 70, 7, 82, 86, 1343 77, 87, 78, 75, 70, 88, 85, 16, 89, 78, 1344 39, 86, 70, 83, 87, 74, 88, 78, 76, 89, 1345 70, 84, 42, 86, 27, 78, 87, 70, 82, 88, 1346 17, 77, 75, 78, 89, 70, 86, 85, 40, 87, 1347 78, 8, 88, 70, 83, 89, 50, 74, 78, 86, 1348 70, 87, 76, 84, 88, 43, 78, 89, 70, 82, 1349 86, 75, 87, 78, 28, 77, 70, 88, 85, 41, 1350 89, 78, 10, 86, 70, 83, 87, 84, 88, 78, 1351 74, 70, 89, 76, 9, 86, 51, 78, 87, 70, 1352 82, 88, 44, 85, 78, 89, 75, 70, 86 1353 }; 1354 1355 /* OPTION_10B_0, 32*1G + 40G RioT + 8*10G + 4*25G */ 1356 static int p2l_mapping_op10b_0[] = { 1357 0, -1, 1358 /* TSC4L 0~5 */ 1359 2, 3, 4, 5, 1360 6, 7, 8, 9, 1361 10, 11, 12, 13, 1362 14, 15, 16, 17, 1363 18, 19, 20, 21, 1364 22, 23, 24, 25, 1365 /* TSC4Q 0~1 */ 1366 26, 27, 28, 29, -1, -1, -1, -1, 1367 -1, -1, -1, -1, -1, -1, -1, -1, 1368 30, 31, 32, 33, -1, -1, -1, -1, 1369 -1, -1, -1, -1, -1, -1, -1, -1, 1370 /* TSC 0~6*/ 1371 -1, -1, -1, -1, 1372 -1, -1, -1, -1, 1373 -1, -1, -1, -1, 1374 34, 35, 36, 37, 1375 38, 39, 40, 41, 1376 42, 43, 44, 45, 1377 46, 47, 48, 49, 1378 /* TSCF 0*/ 1379 50, 51, 52, 53 1380 }; 1381 1382 static int port_speed_max_op10b_0[] = { 1383 0, -1, 1384 /* TSC4L 0~5 */ 1385 10, 10, 10, 10, 1386 10, 10, 10, 10, 1387 10, 10, 10, 10, 1388 10, 10, 10, 10, 1389 10, 10, 10, 10, 1390 10, 10, 10, 10, 1391 /* TSC4Q 0~1 */ 1392 10, 10, 10, 10, -1, -1, -1, -1, 1393 -1, -1, -1, -1, -1, -1, -1, -1, 1394 10, 10, 10, 10, -1, -1, -1, -1, 1395 -1, -1, -1, -1, -1, -1, -1, -1, 1396 /* TSC 0~6*/ 1397 -1, -1, -1, -1, 1398 -1, -1, -1, -1, 1399 -1, -1, -1, -1, 1400 110, 110, 110, 110, 1401 110, 110, 110, 110, 1402 110, 110, 110, 110, 1403 110, 110, 110, 110, 1404 /* TSCF 0*/ 1405 250, 250, 250, 250 1406 }; 1407 1408 uint32 tdm_table_op10b_0[293] = { 1409 82, 77, 88, 85, 79, 89, 81, 18, 86, 70, 1410 83, 87, 75, 73, 88, 76, 84, 89, 78, 80, 1411 86, 17, 6, 87, 71, 82, 88, 74, 72, 89, 1412 77, 86, 44, 79, 87, 81, 85, 88, 83, 70, 1413 89, 75, 73, 86, 19, 76, 87, 78, 84, 88, 1414 80, 7, 89, 71, 82, 86, 74, 72, 87, 77, 1415 85, 88, 79, 81, 89, 10, 26, 86, 70, 83, 1416 87, 75, 88, 73, 76, 89, 84, 78, 86, 80, 1417 20, 87, 11, 71, 88, 74, 72, 89, 82, 77, 1418 86, 79, 85, 87, 81, 8, 88, 70, 83, 89, 1419 75, 73, 86, 76, 45, 87, 78, 84, 88, 80, 1420 27, 89, 71, 86, 74, 82, 87, 72, 77, 88, 1421 12, 79, 89, 81, 85, 86, 70, 83, 87, 75, 1422 73, 88, 9, 76, 89, 78, 84, 86, 80, 21, 1423 87, 71, 82, 88, 74, 72, 89, 77, 42, 86, 1424 79, 81, 87, 85, 83, 88, 70, 89, 75, 13, 1425 86, 73, 76, 87, 84, 78, 88, 80, 2, 89, 1426 71, 82, 86, 74, 72, 87, 22, 77, 88, 79, 1427 85, 89, 81, 43, 86, 70, 83, 87, 75, 73, 1428 88, 76, 23, 89, 78, 84, 86, 80, 87, 3, 1429 71, 88, 74, 82, 89, 72, 77, 86, 14, 79, 1430 87, 81, 85, 88, 70, 83, 89, 75, 73, 86, 1431 28, 76, 87, 78, 84, 88, 80, 24, 89, 71, 1432 82, 86, 74, 72, 87, 77, 4, 88, 79, 89, 1433 81, 85, 86, 25, 70, 87, 75, 73, 88, 83, 1434 76, 89, 15, 78, 86, 80, 84, 87, 71, 82, 1435 88, 74, 72, 89, 77, 0, 86, 79, 85, 87, 1436 81, 29, 88, 70, 83, 89, 75, 73, 86, 76, 1437 87, 5, 78, 88, 80, 84, 89, 16, 71, 86, 1438 74, 72, 87 1439 }; 1440 1441 /* OPTION_13_0, 24P 1G + 4P 10G + XAUI*/ 1442 static int p2l_mapping_op13_0[] = { 1443 0, -1, 1444 /* TSC4L 0~5 */ 1445 2, 3, 4, 5, 1446 6, 7, 8, 9, 1447 10, 11, 12, 13, 1448 14, 15, 16, 17, 1449 18, 19, 20, 21, 1450 22, 23, 24, 25, 1451 /* TSC4Q 0~1 */ 1452 -1, -1, -1, -1, -1, -1, -1, -1, 1453 -1, -1, -1, -1, -1, -1, -1, -1, 1454 -1, -1, -1, -1, -1, -1, -1, -1, 1455 -1, -1, -1, -1, -1, -1, -1, -1, 1456 /* TSC 0~6*/ 1457 -1, -1, -1, -1, 1458 -1, -1, -1, -1, 1459 -1, -1, -1, -1, 1460 -1, -1, -1, -1, 1461 26, 27, 28, 29, 1462 30, -1, -1, -1, 1463 -1, -1, -1, -1, 1464 /* TSCF 0*/ 1465 -1, -1, -1, -1 1466 }; 1467 static int port_speed_max_op13_0[] = { 1468 0, -1, 1469 /* TSC4L 0~5 */ 1470 10, 10, 10, 10, 1471 10, 10, 10, 10, 1472 10, 10, 10, 10, 1473 10, 10, 10, 10, 1474 10, 10, 10, 10, 1475 10, 10, 10, 10, 1476 /* TSC4Q 0~1 */ 1477 -1, -1, -1, -1, -1, -1, -1, -1, 1478 -1, -1, -1, -1, -1, -1, -1, -1, 1479 -1, -1, -1, -1, -1, -1, -1, -1, 1480 -1, -1, -1, -1, -1, -1, -1, -1, 1481 /* TSC 0~6*/ 1482 -1, -1, -1, -1, 1483 -1, -1, -1, -1, 1484 -1, -1, -1, -1, 1485 -1, -1, -1, -1, 1486 110, 110, 110, 110, 1487 100, -1, -1, -1, 1488 -1, -1, -1, -1, 1489 /* TSCF 0*/ 1490 -1, -1, -1, -1 1491 }; 1492 uint32 tdm_table_op13_0[72] = { 1493 75, 77, 78, 10, 74, 76, 2, 22, 75, 77, 1494 78, 127, 74, 76, 11, 3, 75, 77, 78, 23, 1495 74, 76, 12, 24, 75, 77, 78, 4, 74, 76, 1496 13, 5, 75, 77, 78, 25, 74, 76, 127, 14, 1497 75, 77, 78, 6, 74, 76, 18, 15, 75, 77, 1498 78, 7, 74, 76, 0, 19, 75, 77, 78, 16, 1499 74, 76, 8, 20, 75, 77, 78, 9, 74, 76, 1500 17, 21 1501 }; 1502 1503 /* Below options defined in PRD 4.6*/ 1504 /* OPTION_1_0, 24P 10G + 4P 10G/25G */ 1505 static int p2l_mapping_op1_0[] = { 1506 0, -1, 1507 /* TSC4L 0~5 */ 1508 -1, -1, -1, -1, 1509 -1, -1, -1, -1, 1510 -1, -1, -1, -1, 1511 -1, -1, -1, -1, 1512 -1, -1, -1, -1, 1513 -1, -1, -1, -1, 1514 /* TSC4Q 0~1 */ 1515 -1, -1, -1, -1, -1, -1, -1, -1, 1516 -1, -1, -1, -1, -1, -1, -1, -1, 1517 -1, -1, -1, -1, -1, -1, -1, -1, 1518 -1, -1, -1, -1, -1, -1, -1, -1, 1519 /* TSC 0~6*/ 1520 2, 3, 4, 5, 1521 6, 7, 8, 9, 1522 10, 11, 12, 13, 1523 14, 15, 16, 17, 1524 18, 19, 20, 21, 1525 22, -1, -1, -1, 1526 23, 24, 25, 26, 1527 /* TSCF 0*/ 1528 27, 28, 29, 30 1529 }; 1530 1531 static int port_speed_max_op1_0[] = { 1532 0, -1, 1533 /* TSC4L 0~5 */ 1534 -1, -1, -1, -1, 1535 -1, -1, -1, -1, 1536 -1, -1, -1, -1, 1537 -1, -1, -1, -1, 1538 -1, -1, -1, -1, 1539 -1, -1, -1, -1, 1540 /* TSC4Q 0~1 */ 1541 -1, -1, -1, -1, -1, -1, -1, -1, 1542 -1, -1, -1, -1, -1, -1, -1, -1, 1543 -1, -1, -1, -1, -1, -1, -1, -1, 1544 -1, -1, -1, -1, -1, -1, -1, -1, 1545 /* TSC 0~6*/ 1546 110, 110, 110, 110, 1547 110, 110, 110, 110, 1548 110, 110, 110, 110, 1549 110, 110, 110, 110, 1550 110, 110, 110, 110, 1551 100, -1, -1, -1, 1552 110, 110, 110, 110, 1553 /* TSCF 0*/ 1554 250, 250, 250, 250 1555 }; 1556 1557 uint32 tdm_table_op1_0[216] = { 1558 62, 88, 70, 60, 73, 89, 74, 76, 1559 85, 86, 83, 78, 87, 64, 58, 66, 1560 88, 69, 63, 89, 71, 61, 72, 86, 1561 75, 77, 84, 87, 82, 127, 88, 65, 1562 59, 67, 89, 68, 62, 86, 70, 60, 1563 73, 87, 74, 76, 85, 88, 83, 78, 1564 89, 64, 58, 66, 86, 69, 63, 87, 1565 71, 61, 72, 88, 75, 77, 84, 89, 1566 82, 0, 86, 65, 59, 67, 87, 68, 1567 62, 88, 70, 60, 73, 89, 74, 76, 1568 85, 86, 83, 78, 87, 64, 58, 66, 1569 88, 69, 63, 89, 71, 61, 72, 86, 1570 75, 77, 84, 87, 82, 127, 88, 65, 1571 59, 67, 89, 68, 62, 86, 70, 60, 1572 73, 87, 74, 76, 85, 88, 83, 78, 1573 89, 64, 58, 66, 86, 69, 63, 87, 1574 71, 61, 72, 88, 75, 77, 84, 89, 1575 82, 127, 86, 65, 59, 67, 87, 68, 1576 62, 88, 70, 60, 73, 89, 74, 76, 1577 85, 86, 83, 78, 87, 64, 58, 66, 1578 88, 69, 63, 89, 71, 61, 72, 86, 1579 75, 77, 84, 87, 82, 127, 88, 65, 1580 59, 67, 89, 68, 62, 86, 70, 60, 1581 73, 87, 74, 76, 85, 88, 83, 78, 1582 89, 64, 58, 66, 86, 69, 63, 87, 1583 71, 61, 72, 88, 75, 77, 84, 89, 1584 82, 127, 86, 65, 59, 67, 87, 68 1585 }; 1586 1587 /* OPTION_1_1, 24P 10G + 2P HG[50] */ 1588 static int p2l_mapping_op1_1[] = { 1589 0, -1, 1590 /* TSC4L 0~5 */ 1591 -1, -1, -1, -1, 1592 -1, -1, -1, -1, 1593 -1, -1, -1, -1, 1594 -1, -1, -1, -1, 1595 -1, -1, -1, -1, 1596 -1, -1, -1, -1, 1597 /* TSC4Q 0~1 */ 1598 -1, -1, -1, -1, -1, -1, -1, -1, 1599 -1, -1, -1, -1, -1, -1, -1, -1, 1600 -1, -1, -1, -1, -1, -1, -1, -1, 1601 -1, -1, -1, -1, -1, -1, -1, -1, 1602 /* TSC 0~6*/ 1603 2, 3, 4, 5, 1604 6, 7, 8, 9, 1605 10, 11, 12, 13, 1606 14, 15, 16, 17, 1607 18, 19, 20, 21, 1608 22, -1, -1, -1, 1609 23, 24, 25, 26, 1610 /* TSCF 0*/ 1611 27, -1, 28, -1 1612 }; 1613 static int port_speed_max_op1_1[] = { 1614 0, -1, 1615 /* TSC4L 0~5 */ 1616 -1, -1, -1, -1, 1617 -1, -1, -1, -1, 1618 -1, -1, -1, -1, 1619 -1, -1, -1, -1, 1620 -1, -1, -1, -1, 1621 -1, -1, -1, -1, 1622 /* TSC4Q 0~1 */ 1623 -1, -1, -1, -1, -1, -1, -1, -1, 1624 -1, -1, -1, -1, -1, -1, -1, -1, 1625 -1, -1, -1, -1, -1, -1, -1, -1, 1626 -1, -1, -1, -1, -1, -1, -1, -1, 1627 /* TSC 0~6*/ 1628 110, 110, 110, 110, 1629 110, 110, 110, 110, 1630 110, 110, 110, 110, 1631 110, 110, 110, 110, 1632 110, 110, 110, 110, 1633 100, -1, -1, -1, 1634 110, 110, 110, 110, 1635 /* TSCF 0*/ 1636 530, -1, 530, -1 1637 }; 1638 uint32 tdm_table_op1_1[252] = { 1639 59, 88, 66, 71, 72, 86, 74, 68, 1640 88, 60, 77, 84, 86, 78, 64, 88, 1641 63, 83, 58, 86, 67, 70, 73, 88, 1642 75, 69, 86, 61, 76, 85, 88, 127, 1643 65, 86, 62, 82, 59, 88, 66, 71, 1644 72, 86, 74, 68, 88, 60, 77, 84, 1645 86, 78, 64, 88, 63, 83, 58, 86, 1646 67, 70, 73, 88, 75, 69, 86, 61, 1647 76, 85, 88, 127, 65, 86, 62, 82, 1648 59, 88, 66, 71, 72, 86, 74, 68, 1649 88, 60, 77, 84, 86, 78, 64, 88, 1650 63, 83, 58, 86, 67, 70, 73, 88, 1651 75, 69, 86, 61, 76, 85, 88, 127, 1652 65, 86, 62, 82, 59, 88, 66, 71, 1653 72, 86, 74, 68, 88, 60, 77, 84, 1654 86, 78, 64, 88, 63, 83, 58, 86, 1655 67, 70, 73, 88, 75, 69, 86, 61, 1656 76, 85, 88, 127, 65, 86, 62, 82, 1657 59, 88, 66, 71, 72, 86, 74, 68, 1658 88, 60, 77, 84, 86, 78, 64, 88, 1659 63, 83, 58, 86, 67, 70, 73, 88, 1660 75, 69, 86, 61, 76, 85, 88, 127, 1661 65, 86, 62, 82, 59, 88, 66, 71, 1662 72, 86, 74, 68, 88, 60, 77, 84, 1663 86, 78, 64, 88, 63, 83, 58, 86, 1664 67, 70, 73, 88, 75, 69, 86, 61, 1665 76, 85, 88, 0, 65, 86, 62, 82, 1666 59, 88, 66, 71, 72, 86, 74, 68, 1667 88, 60, 77, 84, 86, 78, 64, 88, 1668 63, 83, 58, 86, 67, 70, 73, 88, 1669 75, 69, 86, 61, 76, 85, 88, 127, 1670 65, 86, 62, 82 1671 }; 1672 1673 /* OPTION_1_2, 6P 40G + 4P 10G/25G */ 1674 static int p2l_mapping_op1_2[] = { 1675 0, -1, 1676 /* TSC4L 0~5 */ 1677 -1, -1, -1, -1, 1678 -1, -1, -1, -1, 1679 -1, -1, -1, -1, 1680 -1, -1, -1, -1, 1681 -1, -1, -1, -1, 1682 -1, -1, -1, -1, 1683 /* TSC4Q 0~1 */ 1684 -1, -1, -1, -1, -1, -1, -1, -1, 1685 -1, -1, -1, -1, -1, -1, -1, -1, 1686 -1, -1, -1, -1, -1, -1, -1, -1, 1687 -1, -1, -1, -1, -1, -1, -1, -1, 1688 /* TSC 0~6*/ 1689 2, -1, -1, -1, 1690 3, -1, -1, -1, 1691 4, -1, -1, -1, 1692 5, -1, -1, -1, 1693 6, -1, -1, -1, 1694 7, -1, -1, -1, 1695 8, -1, -1, -1, 1696 /* TSCF 0*/ 1697 9, 10, 11, 12 1698 }; 1699 1700 static int port_speed_max_op1_2[] = { 1701 0, -1, 1702 /* TSC4L 0~5 */ 1703 -1, -1, -1, -1, 1704 -1, -1, -1, -1, 1705 -1, -1, -1, -1, 1706 -1, -1, -1, -1, 1707 -1, -1, -1, -1, 1708 -1, -1, -1, -1, 1709 /* TSC4Q 0~1 */ 1710 -1, -1, -1, -1, -1, -1, -1, -1, 1711 -1, -1, -1, -1, -1, -1, -1, -1, 1712 -1, -1, -1, -1, -1, -1, -1, -1, 1713 -1, -1, -1, -1, -1, -1, -1, -1, 1714 /* TSC 0~6*/ 1715 420, -1, -1, -1, 1716 420, -1, -1, -1, 1717 420, -1, -1, -1, 1718 420, -1, -1, -1, 1719 420, -1, -1, -1, 1720 100, -1, -1, -1, 1721 420, -1, -1, -1, 1722 /* TSCF 0*/ 1723 250, 250, 250, 250 1724 }; 1725 uint32 tdm_table_op1_2[105] = { 1726 86, 58, 62, 66, 88, 70, 74, 87, 1727 82, 58, 62, 89, 66, 70, 74, 86, 1728 82, 58, 78, 88, 62, 66, 87, 70, 1729 74, 82, 89, 58, 62, 66, 86, 70, 1730 74, 82, 88, 58, 62, 87, 66, 70, 1731 74, 89, 82, 58, 62, 86, 78, 66, 1732 70, 88, 74, 82, 87, 58, 62, 66, 1733 89, 70, 74, 82, 86, 58, 78, 62, 1734 88, 66, 70, 87, 74, 82, 58, 89, 1735 62, 66, 70, 86, 74, 82, 58, 88, 1736 62, 66, 87, 70, 74, 82, 89, 58, 1737 78, 62, 86, 66, 70, 74, 88, 82, 1738 58, 87, 62, 66, 70, 89, 74, 0, 1739 82 1740 }; 1741 1742 /* OPTION_1_3, 6P 40G + 2P HG[50] */ 1743 static int p2l_mapping_op1_3[] = { 1744 0, -1, 1745 /* TSC4L 0~5 */ 1746 -1, -1, -1, -1, 1747 -1, -1, -1, -1, 1748 -1, -1, -1, -1, 1749 -1, -1, -1, -1, 1750 -1, -1, -1, -1, 1751 -1, -1, -1, -1, 1752 /* TSC4Q 0~1 */ 1753 -1, -1, -1, -1, -1, -1, -1, -1, 1754 -1, -1, -1, -1, -1, -1, -1, -1, 1755 -1, -1, -1, -1, -1, -1, -1, -1, 1756 -1, -1, -1, -1, -1, -1, -1, -1, 1757 /* TSC 0~6*/ 1758 2, -1, -1, -1, 1759 3, -1, -1, -1, 1760 4, -1, -1, -1, 1761 5, -1, -1, -1, 1762 6, -1, -1, -1, 1763 7, -1, -1, -1, 1764 8, -1, -1, -1, 1765 /* TSCF 0*/ 1766 9, -1, 10, -1 1767 }; 1768 static int port_speed_max_op1_3[] = { 1769 0, -1, 1770 /* TSC4L 0~5 */ 1771 -1, -1, -1, -1, 1772 -1, -1, -1, -1, 1773 -1, -1, -1, -1, 1774 -1, -1, -1, -1, 1775 -1, -1, -1, -1, 1776 -1, -1, -1, -1, 1777 /* TSC4Q 0~1 */ 1778 -1, -1, -1, -1, -1, -1, -1, -1, 1779 -1, -1, -1, -1, -1, -1, -1, -1, 1780 -1, -1, -1, -1, -1, -1, -1, -1, 1781 -1, -1, -1, -1, -1, -1, -1, -1, 1782 /* TSC 0~6*/ 1783 420, -1, -1, -1, 1784 420, -1, -1, -1, 1785 420, -1, -1, -1, 1786 420, -1, -1, -1, 1787 420, -1, -1, -1, 1788 100, -1, -1, -1, 1789 420, -1, -1, -1, 1790 /* TSCF 0*/ 1791 530, -1, 530, -1 1792 }; 1793 uint32 tdm_table_op1_3[105] = { 1794 86, 58, 62, 66, 88, 70, 74, 86, 1795 82, 58, 62, 88, 66, 70, 74, 86, 1796 82, 58, 78, 88, 62, 66, 86, 70, 1797 74, 82, 88, 58, 62, 66, 86, 70, 1798 74, 82, 88, 58, 62, 86, 66, 70, 1799 74, 88, 82, 58, 62, 86, 78, 66, 1800 70, 88, 74, 82, 86, 58, 62, 66, 1801 88, 70, 74, 82, 86, 58, 78, 62, 1802 88, 66, 70, 86, 74, 82, 58, 88, 1803 62, 66, 70, 86, 74, 82, 58, 88, 1804 62, 66, 86, 70, 74, 82, 88, 58, 1805 78, 62, 86, 66, 70, 74, 88, 82, 1806 58, 86, 62, 66, 70, 88, 74, 0, 1807 82 1808 }; 1809 1810 /* OPTION_2_1, 12P 2.5G + 8P 40G */ 1811 static int p2l_mapping_op2_1[] = { 1812 0, -1, 1813 /* TSC4L 0~5 */ 1814 2, 3, 4, 5, 1815 6, 7, 8, 9, 1816 10, 11, 12, 13, 1817 -1, -1, -1, -1, 1818 -1, -1, -1, -1, 1819 -1, -1, -1, -1, 1820 /* TSC4Q 0~1 */ 1821 -1, -1, -1, -1, -1, -1, -1, -1, 1822 -1, -1, -1, -1, -1, -1, -1, -1, 1823 -1, -1, -1, -1, -1, -1, -1, -1, 1824 -1, -1, -1, -1, -1, -1, -1, -1, 1825 /* TSC 0~6*/ 1826 14, -1, -1, -1, 1827 15, -1, -1, -1, 1828 16, -1, -1, -1, 1829 17, -1, -1, -1, 1830 18, -1, -1, -1, 1831 19, -1, -1, -1, 1832 20, -1, -1, -1, 1833 /* TSCF 0*/ 1834 21, -1, -1, -1 1835 }; 1836 static int port_speed_max_op2_1[] = { 1837 0, -1, 1838 /* TSC4L 0~5 */ 1839 25, 25, 25, 25, 1840 25, 25, 25, 25, 1841 25, 25, 25, 25, 1842 -1, -1, -1, -1, 1843 -1, -1, -1, -1, 1844 -1, -1, -1, -1, 1845 /* TSC4Q 0~1 */ 1846 -1, -1, -1, -1, -1, -1, -1, -1, 1847 -1, -1, -1, -1, -1, -1, -1, -1, 1848 -1, -1, -1, -1, -1, -1, -1, -1, 1849 -1, -1, -1, -1, -1, -1, -1, -1, 1850 /* TSC 0~6*/ 1851 420, -1, -1, -1, 1852 420, -1, -1, -1, 1853 420, -1, -1, -1, 1854 420, -1, -1, -1, 1855 420, -1, -1, -1, 1856 420, -1, -1, -1, 1857 420, -1, -1, -1, 1858 /* TSCF 0*/ 1859 420, -1, -1, -1 1860 }; 1861 uint32 tdm_table_op2_1[144] = { 1862 6, 82, 70, 62, 78, 74, 66, 58, 1863 86, 10, 82, 70, 62, 78, 74, 66, 1864 58, 86, 7, 82, 70, 62, 78, 74, 1865 66, 58, 86, 127, 82, 70, 62, 78, 1866 74, 66, 58, 86, 8, 82, 70, 62, 1867 78, 74, 66, 58, 86, 11, 82, 70, 1868 62, 78, 74, 66, 58, 86, 9, 82, 1869 70, 62, 78, 74, 66, 58, 86, 127, 1870 82, 70, 62, 78, 74, 66, 58, 86, 1871 2, 82, 70, 62, 78, 74, 66, 58, 1872 86, 12, 82, 70, 62, 78, 74, 66, 1873 58, 86, 3, 82, 70, 62, 78, 74, 1874 66, 58, 86, 127, 82, 70, 62, 78, 1875 74, 66, 58, 86, 4, 82, 70, 62, 1876 78, 74, 66, 58, 86, 13, 82, 70, 1877 62, 78, 74, 66, 58, 86, 5, 82, 1878 70, 62, 78, 74, 66, 58, 86, 0, 1879 82, 70, 62, 78, 74, 66, 58, 86 1880 }; 1881 1882 /* OPTION_3_0, 52P 2.5G + 4P 25G + 8P 10G */ 1883 static int p2l_mapping_op3_0[] = { 1884 0, -1, 1885 /* TSC4L 0~5 */ 1886 2, 3, 4, 5, 1887 6, 7, 8, 9, 1888 10, 11, 12, 13, 1889 14, 15, 16, 17, 1890 18, 19, 20, 21, 1891 22, 23, 24, 25, 1892 /* TSC4Q 0~1 */ 1893 26, 27, 28, 29, -1, -1, -1, -1, 1894 -1, -1, -1, -1, -1, -1, -1, -1, 1895 30, 31, 32, 33, -1, -1, -1, -1, 1896 -1, -1, -1, -1, -1, -1, -1, -1, 1897 /* TSC 0~6*/ 1898 34, 35, 36, 37, 1899 38, 39, 40, 41, 1900 42, 43, 44, 45, 1901 46, 47, 48, 49, 1902 50, 51, 52, 53, 1903 54, 55, 56, 57, 1904 58, 59, 60, 61, 1905 /* TSCF 0*/ 1906 62, 63, 64, 65 1907 }; 1908 static int port_speed_max_op3_0[] = { 1909 0, -1, 1910 /* TSC4L 0~5 */ 1911 25, 25, 25, 25, 1912 25, 25, 25, 25, 1913 25, 25, 25, 25, 1914 25, 25, 25, 25, 1915 25, 25, 25, 25, 1916 25, 25, 25, 25, 1917 /* TSC4Q 0~1 */ 1918 25, 25, 25, 25, -1, -1, -1, -1, 1919 -1, -1, -1, -1, -1, -1, -1, -1, 1920 25, 25, 25, 25, -1, -1, -1, -1, 1921 -1, -1, -1, -1, -1, -1, -1, -1, 1922 /* TSC 0~6*/ 1923 25, 25, 25, 25, 1924 25, 25, 25, 25, 1925 25, 25, 25, 25, 1926 25, 25, 25, 25, 1927 110, 110, 110, 110, 1928 25, 25, 25, 25, 1929 110, 110, 110, 110, 1930 /* TSCF 0*/ 1931 250, 250, 250, 250 1932 }; 1933 uint32 tdm_table_op3_0[252] = { 1934 76, 88, 82, 71, 89, 84, 78, 86, 1935 127, 75, 27, 87, 17, 21, 88, 8, 1936 77, 89, 83, 85, 86, 61, 63, 87, 1937 45, 74, 88, 10, 22, 89, 9, 65, 1938 76, 86, 82, 84, 87, 72, 81, 88, 1939 75, 66, 89, 11, 23, 86, 2, 77, 1940 87, 83, 28, 88, 85, 59, 69, 89, 1941 74, 42, 86, 12, 24, 87, 3, 76, 1942 88, 82, 84, 89, 70, 79, 86, 0, 1943 75, 25, 87, 13, 29, 88, 4, 77, 1944 89, 83, 85, 86, 60, 62, 87, 43, 1945 74, 88, 14, 18, 89, 5, 64, 76, 1946 86, 82, 84, 87, 73, 80, 88, 75, 1947 67, 89, 15, 19, 86, 6, 77, 87, 1948 83, 26, 88, 85, 58, 68, 89, 74, 1949 44, 86, 16, 20, 87, 7, 76, 88, 1950 82, 84, 89, 71, 78, 86, 127, 75, 1951 17, 87, 21, 27, 88, 8, 77, 89, 1952 83, 85, 86, 61, 63, 87, 45, 74, 1953 88, 10, 22, 89, 9, 65, 76, 86, 1954 82, 84, 87, 72, 81, 88, 75, 66, 1955 89, 11, 23, 86, 2, 77, 87, 83, 1956 28, 85, 88, 59, 69, 89, 74, 42, 1957 86, 12, 24, 87, 3, 76, 88, 82, 1958 84, 89, 70, 79, 86, 127, 75, 29, 1959 87, 13, 25, 88, 4, 77, 89, 83, 1960 85, 86, 60, 62, 87, 43, 74, 88, 1961 14, 18, 89, 5, 64, 76, 86, 82, 1962 84, 87, 73, 80, 88, 75, 67, 89, 1963 15, 19, 86, 6, 77, 87, 83, 26, 1964 85, 88, 58, 68, 89, 74, 44, 86, 1965 16, 20, 87, 7 1966 }; 1967 1968 /* OPTION_3_1, 52P 2.5G + 4P 25G + 2P 40G */ 1969 static int p2l_mapping_op3_1[] = { 1970 0, -1, 1971 /* TSC4L 0~5 */ 1972 2, 3, 4, 5, 1973 6, 7, 8, 9, 1974 10, 11, 12, 13, 1975 14, 15, 16, 17, 1976 18, 19, 20, 21, 1977 22, 23, 24, 25, 1978 /* TSC4Q 0~1 */ 1979 26, 27, 28, 29, -1, -1, -1, -1, 1980 -1, -1, -1, -1, -1, -1, -1, -1, 1981 30, 31, 32, 33, -1, -1, -1, -1, 1982 -1, -1, -1, -1, -1, -1, -1, -1, 1983 /* TSC 0~6*/ 1984 34, 35, 36, 37, 1985 38, 39, 40, 41, 1986 42, 43, 44, 45, 1987 46, 47, 48, 49, 1988 50, -1, -1, -1, 1989 51, 52, 53, 54, 1990 55, -1, -1, -1, 1991 /* TSCF 0*/ 1992 56, 57, 58, 59 1993 }; 1994 static int port_speed_max_op3_1[] = { 1995 0, -1, 1996 /* TSC4L 0~5 */ 1997 25, 25, 25, 25, 1998 25, 25, 25, 25, 1999 25, 25, 25, 25, 2000 25, 25, 25, 25, 2001 25, 25, 25, 25, 2002 25, 25, 25, 25, 2003 /* TSC4Q 0~1 */ 2004 25, 25, 25, 25, -1, -1, -1, -1, 2005 -1, -1, -1, -1, -1, -1, -1, -1, 2006 25, 25, 25, 25, -1, -1, -1, -1, 2007 -1, -1, -1, -1, -1, -1, -1, -1, 2008 /* TSC 0~6*/ 2009 25, 25, 25, 25, 2010 25, 25, 25, 25, 2011 25, 25, 25, 25, 2012 25, 25, 25, 25, 2013 420, -1, -1, -1, 2014 25, 25, 25, 25, 2015 420, -1, -1, -1, 2016 /* TSCF 0*/ 2017 250, 250, 250, 250 2018 }; 2019 uint32 tdm_table_op3_1[128] = { 2020 127, 127, 88, 74, 13, 89, 82, 22, 2021 86, 29, 45, 74, 87, 6, 82, 88, 2022 58, 73, 89, 74, 14, 86, 82, 23, 2023 87, 64, 67, 74, 88, 7, 82, 89, 2024 79, 81, 86, 74, 15, 87, 82, 24, 2025 88, 26, 42, 74, 89, 8, 82, 86, 2026 61, 62, 87, 74, 16, 88, 82, 25, 2027 89, 69, 70, 74, 86, 9, 82, 87, 2028 0, 127, 88, 74, 17, 89, 82, 18, 2029 86, 27, 43, 74, 87, 2, 82, 88, 2030 59, 72, 89, 74, 10, 86, 82, 19, 2031 87, 65, 66, 74, 88, 3, 82, 89, 2032 78, 80, 86, 74, 11, 87, 82, 20, 2033 88, 28, 44, 74, 89, 4, 82, 86, 2034 60, 63, 87, 74, 12, 88, 82, 21, 2035 89, 68, 71, 74, 86, 5, 82, 87 2036 }; 2037 2038 /* OPTION_3_2, 52P 2.5G + 2P 50G + 8P 10G */ 2039 static int p2l_mapping_op3_2[] = { 2040 0, -1, 2041 /* TSC4L 0~5 */ 2042 2, 3, 4, 5, 2043 6, 7, 8, 9, 2044 10, 11, 12, 13, 2045 14, 15, 16, 17, 2046 18, 19, 20, 21, 2047 22, 23, 24, 25, 2048 /* TSC4Q 0~1 */ 2049 26, 27, 28, 29, -1, -1, -1, -1, 2050 -1, -1, -1, -1, -1, -1, -1, -1, 2051 30, 31, 32, 33, -1, -1, -1, -1, 2052 -1, -1, -1, -1, -1, -1, -1, -1, 2053 /* TSC 0~6*/ 2054 34, 35, 36, 37, 2055 38, 39, 40, 41, 2056 42, 43, 44, 45, 2057 46, 47, 48, 49, 2058 50, 51, 52, 53, 2059 54, 55, 56, 57, 2060 58, 59, 60, 61, 2061 /* TSCF 0*/ 2062 62, -1, 63, -1 2063 }; 2064 static int port_speed_max_op3_2[] = { 2065 0, -1, 2066 /* TSC4L 0~5 */ 2067 25, 25, 25, 25, 2068 25, 25, 25, 25, 2069 25, 25, 25, 25, 2070 25, 25, 25, 25, 2071 25, 25, 25, 25, 2072 25, 25, 25, 25, 2073 /* TSC4Q 0~1 */ 2074 25, 25, 25, 25, -1, -1, -1, -1, 2075 -1, -1, -1, -1, -1, -1, -1, -1, 2076 25, 25, 25, 25, -1, -1, -1, -1, 2077 -1, -1, -1, -1, -1, -1, -1, -1, 2078 /* TSC 0~6*/ 2079 25, 25, 25, 25, 2080 25, 25, 25, 25, 2081 25, 25, 25, 25, 2082 25, 25, 25, 25, 2083 110, 110, 110, 110, 2084 25, 25, 25, 25, 2085 110, 110, 110, 110, 2086 /* TSCF 0*/ 2087 530, -1, 530, -1 2088 }; 2089 uint32 tdm_table_op3_2[250] = { 2090 59, 88, 19, 3, 74, 86, 15, 81, 2091 88, 85, 82, 86, 70, 76, 88, 67, 2092 20, 86, 4, 27, 88, 75, 16, 86, 2093 84, 83, 88, 62, 45, 77, 86, 65, 2094 21, 88, 5, 74, 86, 17, 60, 88, 2095 85, 82, 86, 72, 69, 88, 76, 78, 2096 86, 22, 6, 88, 75, 10, 28, 86, 2097 84, 83, 88, 42, 77, 86, 58, 23, 2098 88, 7, 0, 86, 74, 11, 88, 85, 2099 80, 86, 82, 71, 88, 76, 29, 24, 2100 86, 8, 75, 88, 12, 64, 86, 84, 2101 83, 88, 43, 77, 86, 63, 25, 88, 2102 9, 74, 86, 66, 13, 88, 61, 85, 2103 82, 86, 68, 76, 88, 73, 18, 86, 2104 2, 75, 88, 26, 14, 86, 84, 83, 2105 88, 44, 77, 86, 79, 59, 88, 19, 2106 3, 74, 86, 15, 81, 88, 85, 82, 2107 86, 70, 76, 88, 67, 20, 86, 4, 2108 27, 88, 75, 16, 86, 84, 83, 88, 2109 62, 45, 77, 86, 65, 21, 88, 5, 2110 74, 86, 17, 60, 88, 85, 82, 86, 2111 72, 69, 88, 76, 78, 86, 22, 6, 2112 88, 75, 10, 28, 86, 84, 83, 88, 2113 42, 77, 86, 58, 23, 88, 7, 127, 2114 86, 74, 11, 88, 85, 82, 86, 80, 2115 71, 88, 76, 29, 24, 86, 8, 75, 2116 88, 12, 64, 86, 84, 83, 88, 43, 2117 77, 86, 63, 25, 88, 9, 74, 86, 2118 61, 13, 88, 66, 85, 82, 86, 68, 2119 76, 88, 73, 18, 86, 2, 75, 88, 2120 26, 14, 86, 84, 83, 88, 79, 44, 2121 86, 77 2122 }; 2123 2124 /* OPTION_3_3, 52P 2.5G + 2P 50G + 2P 40G */ 2125 static int p2l_mapping_op3_3[] = { 2126 0, -1, 2127 /* TSC4L 0~5 */ 2128 2, 3, 4, 5, 2129 6, 7, 8, 9, 2130 10, 11, 12, 13, 2131 14, 15, 16, 17, 2132 18, 19, 20, 21, 2133 22, 23, 24, 25, 2134 /* TSC4Q 0~1 */ 2135 26, 27, 28, 29, -1, -1, -1, -1, 2136 -1, -1, -1, -1, -1, -1, -1, -1, 2137 30, 31, 32, 33, -1, -1, -1, -1, 2138 -1, -1, -1, -1, -1, -1, -1, -1, 2139 /* TSC 0~6*/ 2140 34, 35, 36, 37, 2141 38, 39, 40, 41, 2142 42, 43, 44, 45, 2143 46, 47, 48, 49, 2144 50, -1, -1, -1, 2145 51, 52, 53, 54, 2146 55, -1, -1, -1, 2147 /* TSCF 0*/ 2148 56, -1, 57, -1 2149 }; 2150 static int port_speed_max_op3_3[] = { 2151 0, -1, 2152 /* TSC4L 0~5 */ 2153 25, 25, 25, 25, 2154 25, 25, 25, 25, 2155 25, 25, 25, 25, 2156 25, 25, 25, 25, 2157 25, 25, 25, 25, 2158 25, 25, 25, 25, 2159 /* TSC4Q 0~1 */ 2160 25, 25, 25, 25, -1, -1, -1, -1, 2161 -1, -1, -1, -1, -1, -1, -1, -1, 2162 25, 25, 25, 25, -1, -1, -1, -1, 2163 -1, -1, -1, -1, -1, -1, -1, -1, 2164 /* TSC 0~6*/ 2165 25, 25, 25, 25, 2166 25, 25, 25, 25, 2167 25, 25, 25, 25, 2168 25, 25, 25, 25, 2169 420, -1, -1, -1, 2170 25, 25, 25, 25, 2171 420, -1, -1, -1, 2172 /* TSCF 0*/ 2173 530, -1, 530, -1 2174 }; 2175 uint32 tdm_table_op3_3[128] = { 2176 42, 21, 86, 74, 62, 82, 88, 26, 2177 15, 86, 66, 74, 88, 82, 4, 86, 2178 68, 22, 88, 74, 70, 82, 86, 64, 2179 16, 88, 61, 74, 86, 82, 5, 88, 2180 43, 23, 86, 74, 73, 82, 88, 27, 2181 17, 86, 59, 74, 88, 82, 6, 86, 2182 79, 24, 88, 74, 81, 82, 86, 0, 2183 10, 88, 127, 74, 86, 82, 7, 88, 2184 44, 25, 86, 74, 63, 82, 88, 28, 2185 11, 86, 67, 74, 88, 82, 8, 86, 2186 69, 18, 88, 74, 71, 82, 86, 65, 2187 12, 88, 60, 74, 86, 82, 9, 88, 2188 45, 19, 86, 74, 72, 82, 88, 29, 2189 13, 86, 58, 74, 88, 82, 2, 86, 2190 78, 20, 88, 74, 80, 82, 86, 127, 2191 14, 88, 127, 74, 86, 82, 3, 88 2192 }; 2193 2194 /* OPTION_4_0, 48P 2.5G + 4P 25G + 8P 10G */ 2195 static int p2l_mapping_op4_0[] = { 2196 0, -1, 2197 /* TSC4L 0~5 */ 2198 2, 3, 4, 5, 2199 6, 7, 8, 9, 2200 10, 11, 12, 13, 2201 14, 15, 16, 17, 2202 18, 19, 20, 21, 2203 22, 23, 24, 25, 2204 /* TSC4Q 0~1 */ 2205 26, 27, 28, 29, -1, -1, -1, -1, 2206 -1, -1, -1, -1, -1, -1, -1, -1, 2207 30, 31, 32, 33, -1, -1, -1, -1, 2208 -1, -1, -1, -1, -1, -1, -1, -1, 2209 /* TSC 0~6*/ 2210 34, 35, 36, 37, 2211 38, 39, 40, 41, 2212 42, 43, 44, 45, 2213 46, 47, 48, 49, 2214 50, 51, 52, 53, 2215 54, -1, -1, -1, 2216 55, 56, 57, 58, 2217 /* TSCF 0*/ 2218 59, 60, 61, 62 2219 }; 2220 static int port_speed_max_op4_0[] = { 2221 0, -1, 2222 /* TSC4L 0~5 */ 2223 25, 25, 25, 25, 2224 25, 25, 25, 25, 2225 25, 25, 25, 25, 2226 25, 25, 25, 25, 2227 25, 25, 25, 25, 2228 25, 25, 25, 25, 2229 /* TSC4Q 0~1 */ 2230 25, 25, 25, 25, -1, -1, -1, -1, 2231 -1, -1, -1, -1, -1, -1, -1, -1, 2232 25, 25, 25, 25, -1, -1, -1, -1, 2233 -1, -1, -1, -1, -1, -1, -1, -1, 2234 /* TSC 0~6*/ 2235 25, 25, 25, 25, 2236 25, 25, 25, 25, 2237 25, 25, 25, 25, 2238 25, 25, 25, 25, 2239 110, 110, 110, 110, 2240 100, -1, -1, -1, 2241 110, 110, 110, 110, 2242 /* TSCF 0*/ 2243 250, 250, 250, 250 2244 }; 2245 uint32 tdm_table_op4_0[126] = { 2246 15, 85, 88, 74, 83, 89, 26, 77, 86, 43, 2247 5, 87, 78, 18, 64, 88, 16, 84, 89, 75, 2248 82, 86, 62, 76, 87, 0, 6, 88, 61, 19, 2249 89, 17, 85, 86, 83, 74, 44, 87, 27, 77, 2250 88, 58, 7, 89, 78, 20, 86, 10, 84, 87, 2251 75, 82, 88, 66, 71, 89, 76, 68, 8, 86, 2252 21, 72, 87, 11, 85, 88, 74, 83, 89, 28, 2253 77, 86, 45, 9, 87, 127, 22, 78, 88, 12, 2254 84, 89, 75, 82, 86, 63, 76, 87, 65, 2, 2255 88, 60, 23, 89, 13, 85, 86, 83, 74, 42, 2256 87, 29, 77, 88, 59, 3, 89, 78, 24, 86, 2257 14, 84, 87, 75, 82, 88, 67, 70, 89, 76, 2258 69, 4, 86, 25, 73, 87 2259 }; 2260 2261 /* OPTION_4_1, 48P 2.5G + 4P 25G + 2P 40G */ 2262 static int p2l_mapping_op4_1[] = { 2263 0, -1, 2264 /* TSC4L 0~5 */ 2265 2, 3, 4, 5, 2266 6, 7, 8, 9, 2267 10, 11, 12, 13, 2268 14, 15, 16, 17, 2269 18, 19, 20, 21, 2270 22, 23, 24, 25, 2271 /* TSC4Q 0~1 */ 2272 26, 27, 28, 29, -1, -1, -1, -1, 2273 -1, -1, -1, -1, -1, -1, -1, -1, 2274 30, 31, 32, 33, -1, -1, -1, -1, 2275 -1, -1, -1, -1, -1, -1, -1, -1, 2276 /* TSC 0~6*/ 2277 34, 35, 36, 37, 2278 38, 39, 40, 41, 2279 42, 43, 44, 45, 2280 46, 47, 48, 49, 2281 50, -1, -1, -1, 2282 51, -1, -1, -1, 2283 52, -1, -1, -1, 2284 /* TSCF 0*/ 2285 53, 54, 55, 56 2286 }; 2287 static int port_speed_max_op4_1[] = { 2288 0, -1, 2289 /* TSC4L 0~5 */ 2290 25, 25, 25, 25, 2291 25, 25, 25, 25, 2292 25, 25, 25, 25, 2293 25, 25, 25, 25, 2294 25, 25, 25, 25, 2295 25, 25, 25, 25, 2296 /* TSC4Q 0~1 */ 2297 25, 25, 25, 25, -1, -1, -1, -1, 2298 -1, -1, -1, -1, -1, -1, -1, -1, 2299 25, 25, 25, 25, -1, -1, -1, -1, 2300 -1, -1, -1, -1, -1, -1, -1, -1, 2301 /* TSC 0~6*/ 2302 25, 25, 25, 25, 2303 25, 25, 25, 25, 2304 25, 25, 25, 25, 2305 25, 25, 25, 25, 2306 420, -1, -1, -1, 2307 100, -1, -1, -1, 2308 420, -1, -1, -1, 2309 /* TSCF 0*/ 2310 250, 250, 250, 250 2311 }; 2312 uint32 tdm_table_op4_1[128] = { 2313 88, 74, 5, 89, 78, 60, 82, 86, 23, 74, 2314 87, 17, 45, 88, 82, 63, 89, 74, 6, 86, 2315 66, 127, 82, 87, 24, 74, 88, 10, 127, 89, 2316 82, 28, 86, 74, 7, 87, 78, 72, 82, 88, 2317 25, 74, 89, 11, 42, 86, 82, 69, 87, 74, 2318 8, 88, 64, 70, 82, 89, 18, 74, 86, 12, 2319 58, 87, 82, 29, 88, 74, 9, 89, 78, 61, 2320 82, 86, 19, 74, 87, 13, 43, 88, 82, 62, 2321 89, 74, 2, 86, 67, 0, 82, 87, 20, 74, 2322 88, 14, 127, 89, 82, 26, 86, 74, 3, 87, 2323 78, 73, 82, 88, 21, 74, 89, 15, 44, 86, 2324 82, 68, 87, 74, 4, 88, 65, 71, 82, 89, 2325 22, 74, 86, 16, 59, 87, 82, 27 2326 }; 2327 2328 /* OPTION_4_2, 48P 2.5G + 2P 50G + 8P 10G */ 2329 static int p2l_mapping_op4_2[] = { 2330 0, -1, 2331 /* TSC4L 0~5 */ 2332 2, 3, 4, 5, 2333 6, 7, 8, 9, 2334 10, 11, 12, 13, 2335 14, 15, 16, 17, 2336 18, 19, 20, 21, 2337 22, 23, 24, 25, 2338 /* TSC4Q 0~1 */ 2339 26, 27, 28, 29, -1, -1, -1, -1, 2340 -1, -1, -1, -1, -1, -1, -1, -1, 2341 30, 31, 32, 33, -1, -1, -1, -1, 2342 -1, -1, -1, -1, -1, -1, -1, -1, 2343 /* TSC 0~6*/ 2344 34, 35, 36, 37, 2345 38, 39, 40, 41, 2346 42, 43, 44, 45, 2347 46, 47, 48, 49, 2348 50, 51, 52, 53, 2349 54, -1, -1, -1, 2350 55, 56, 57, 58, 2351 /* TSCF 0*/ 2352 59, -1, 60, -1 2353 }; 2354 static int port_speed_max_op4_2[] = { 2355 0, -1, 2356 /* TSC4L 0~5 */ 2357 25, 25, 25, 25, 2358 25, 25, 25, 25, 2359 25, 25, 25, 25, 2360 25, 25, 25, 25, 2361 25, 25, 25, 25, 2362 25, 25, 25, 25, 2363 /* TSC4Q 0~1 */ 2364 25, 25, 25, 25, -1, -1, -1, -1, 2365 -1, -1, -1, -1, -1, -1, -1, -1, 2366 25, 25, 25, 25, -1, -1, -1, -1, 2367 -1, -1, -1, -1, -1, -1, -1, -1, 2368 /* TSC 0~6*/ 2369 25, 25, 25, 25, 2370 25, 25, 25, 25, 2371 25, 25, 25, 25, 2372 25, 25, 25, 25, 2373 110, 110, 110, 110, 2374 100, -1, -1, -1, 2375 110, 110, 110, 110, 2376 /* TSCF 0*/ 2377 530, -1, 530, -1 2378 }; 2379 uint32 tdm_table_op4_2[251] = { 2380 58, 23, 86, 16, 66, 88, 8, 75, 86, 82, 2381 29, 88, 85, 60, 86, 76, 69, 88, 17, 24, 2382 86, 127, 9, 74, 88, 83, 45, 86, 84, 78, 2383 88, 77, 71, 86, 10, 25, 88, 73, 2, 86, 2384 75, 82, 88, 85, 26, 63, 86, 76, 64, 88, 2385 11, 18, 86, 3, 74, 88, 83, 42, 86, 84, 2386 78, 88, 77, 59, 86, 12, 19, 88, 67, 4, 2387 75, 86, 82, 27, 88, 85, 61, 86, 76, 68, 2388 88, 13, 20, 86, 43, 5, 88, 74, 83, 86, 2389 84, 78, 72, 88, 77, 70, 86, 14, 21, 88, 2390 6, 75, 86, 82, 127, 88, 85, 28, 86, 76, 2391 62, 88, 15, 22, 65, 86, 7, 74, 88, 83, 2392 44, 86, 84, 78, 88, 77, 58, 86, 16, 23, 2393 88, 66, 8, 86, 75, 82, 85, 88, 29, 60, 2394 86, 76, 69, 88, 17, 24, 86, 9, 74, 88, 2395 83, 45, 86, 84, 78, 88, 77, 71, 86, 73, 2396 10, 25, 88, 2, 75, 86, 82, 85, 88, 26, 2397 63, 86, 76, 64, 88, 11, 18, 86, 59, 3, 2398 88, 74, 83, 84, 86, 42, 78, 88, 77, 0, 2399 86, 12, 19, 88, 4, 75, 86, 82, 27, 88, 2400 85, 61, 86, 76, 67, 20, 88, 13, 68, 86, 2401 5, 74, 88, 83, 43, 86, 84, 78, 88, 77, 2402 70, 86, 14, 21, 88, 75, 6, 86, 72, 82, 2403 85, 88, 28, 62, 86, 76, 65, 88, 15, 22, 2404 86, 7, 74, 88, 83, 44, 86, 84, 78, 88, 2405 77 2406 }; 2407 2408 /* OPTION_4_3, 48P 2.5G + 2P 50G + 2P 40G */ 2409 static int p2l_mapping_op4_3[] = { 2410 0, -1, 2411 /* TSC4L 0~5 */ 2412 2, 3, 4, 5, 2413 6, 7, 8, 9, 2414 10, 11, 12, 13, 2415 14, 15, 16, 17, 2416 18, 19, 20, 21, 2417 22, 23, 24, 25, 2418 /* TSC4Q 0~1 */ 2419 26, 27, 28, 29, -1, -1, -1, -1, 2420 -1, -1, -1, -1, -1, -1, -1, -1, 2421 30, 31, 32, 33, -1, -1, -1, -1, 2422 -1, -1, -1, -1, -1, -1, -1, -1, 2423 /* TSC 0~6*/ 2424 34, 35, 36, 37, 2425 38, 39, 40, 41, 2426 42, 43, 44, 45, 2427 46, 47, 48, 49, 2428 50, -1, -1, -1, 2429 51, -1, -1, -1, 2430 52, -1, -1, -1, 2431 /* TSCF 0*/ 2432 53, -2, 54, -2 2433 }; 2434 static int port_speed_max_op4_3[] = { 2435 0, -1, 2436 /* TSC4L 0~5 */ 2437 25, 25, 25, 25, 2438 25, 25, 25, 25, 2439 25, 25, 25, 25, 2440 25, 25, 25, 25, 2441 25, 25, 25, 25, 2442 25, 25, 25, 25, 2443 /* TSC4Q 0~1 */ 2444 25, 25, 25, 25, -1, -1, -1, -1, 2445 -1, -1, -1, -1, -1, -1, -1, -1, 2446 25, 25, 25, 25, -1, -1, -1, -1, 2447 -1, -1, -1, -1, -1, -1, -1, -1, 2448 /* TSC 0~6*/ 2449 25, 25, 25, 25, 2450 25, 25, 25, 25, 2451 25, 25, 25, 25, 2452 25, 25, 25, 25, 2453 420, -1, -1, -1, 2454 100, -1, -1, -1, 2455 420, -1, -1, -1, 2456 /* TSCF 0*/ 2457 530, -1, 530, -1 2458 }; 2459 uint32 tdm_table_op4_3[128] = { 2460 88, 82, 0, 86, 74, 5, 78, 88, 11, 82, 2461 86, 20, 74, 88, 27, 58, 86, 82, 60, 88, 2462 74, 6, 44, 86, 12, 82, 88, 21, 74, 86, 2463 67, 73, 88, 82, 127, 86, 74, 7, 78, 88, 2464 13, 82, 86, 22, 74, 88, 28, 70, 86, 82, 2465 63, 88, 74, 8, 45, 86, 14, 82, 88, 23, 2466 74, 86, 64, 69, 88, 82, 127, 86, 74, 9, 2467 78, 88, 15, 82, 86, 24, 74, 88, 29, 59, 2468 86, 82, 61, 88, 74, 2, 42, 86, 16, 82, 2469 88, 25, 74, 86, 66, 72, 88, 82, 127, 86, 2470 74, 3, 78, 88, 17, 82, 86, 18, 74, 88, 2471 26, 71, 86, 82, 62, 88, 74, 4, 43, 86, 2472 10, 82, 88, 19, 74, 86, 65, 68 2473 }; 2474 2475 /* OPTION_5_0, 24P 2.5G + 4P 25G + 8P 10G */ 2476 static int p2l_mapping_op5_0[] = { 2477 0, -1, 2478 /* TSC4L 0~5 */ 2479 2, 3, 4, 5, 2480 -1, -1, -1, -1, 2481 6, 7, 8, 9, 2482 -1, -1, -1, -1, 2483 10, 11, 12, 13, 2484 -1, -1, -1, -1, 2485 /* TSC4Q 0~1 */ 2486 14, 15, 16, 17, -1, -1, -1, -1, 2487 -1, -1, -1, -1, -1, -1, -1, -1, 2488 -1, -1, -1, -1, -1, -1, -1, -1, 2489 -1, -1, -1, -1, -1, -1, -1, -1, 2490 /* TSC 0~6*/ 2491 18, 19, 20, 21, 2492 -1, -1, -1, -1, 2493 22, 23, 24, 25, 2494 -1, -1, -1, -1, 2495 26, 27, 28, 29, 2496 30, -1, -1, -1, 2497 31, 32, 33, 34, 2498 /* TSCF 0*/ 2499 35, 36, 37, 38 2500 }; 2501 static int port_speed_max_op5_0[] = { 2502 0, -1, 2503 /* TSC4L 0~5 */ 2504 25, 25, 25, 25, 2505 -1, -1, -1, -1, 2506 25, 25, 25, 25, 2507 -1, -1, -1, -1, 2508 25, 25, 25, 25, 2509 -1, -1, -1, -1, 2510 /* TSC4Q 0~1 */ 2511 25, 25, 25, 25, -1, -1, -1, -1, 2512 -1, -1, -1, -1, -1, -1, -1, -1, 2513 -1, -1, -1, -1, -1, -1, -1, -1, 2514 -1, -1, -1, -1, -1, -1, -1, -1, 2515 /* TSC 0~6*/ 2516 25, 25, 25, 25, 2517 -1, -1, -1, -1, 2518 25, 25, 25, 25, 2519 -1, -1, -1, -1, 2520 110, 110, 110, 110, 2521 100, -1, -1, -1, 2522 110, 110, 110, 110, 2523 /* TSCF 0*/ 2524 250, 250, 250, 250 2525 }; 2526 uint32 tdm_table_op5_0[102] = { 2527 88, 84, 89, 75, 29, 86, 83, 87, 78, 60, 2528 88, 76, 89, 85, 21, 86, 74, 2, 87, 82, 2529 88, 10, 0, 89, 77, 86, 84, 26, 87, 75, 2530 88, 83, 58, 89, 78, 86, 66, 76, 87, 85, 2531 88, 74, 3, 89, 82, 18, 86, 11, 87, 77, 2532 68, 88, 84, 89, 75, 27, 86, 83, 87, 78, 2533 61, 88, 76, 89, 85, 127, 86, 74, 4, 87, 2534 82, 88, 12, 19, 89, 77, 86, 84, 28, 87, 2535 75, 88, 83, 59, 89, 78, 86, 67, 76, 87, 2536 85, 88, 74, 69, 89, 82, 5, 86, 13, 87, 2537 77, 20 2538 }; 2539 2540 /* OPTION_5_1, 24P 2.5G + 4P 25G + 2P 40G */ 2541 static int p2l_mapping_op5_1[] = { 2542 0, -1, 2543 /* TSC4L 0~5 */ 2544 2, 3, 4, 5, 2545 -1, -1, -1, -1, 2546 6, 7, 8, 9, 2547 -1, -1, -1, -1, 2548 10, 11, 12, 13, 2549 -1, -1, -1, -1, 2550 /* TSC4Q 0~1 */ 2551 14, 15, 16, 17, -1, -1, -1, -1, 2552 -1, -1, -1, -1, -1, -1, -1, -1, 2553 -1, -1, -1, -1, -1, -1, -1, -1, 2554 -1, -1, -1, -1, -1, -1, -1, -1, 2555 /* TSC 0~6*/ 2556 18, 19, 20, 21, 2557 -1, -1, -1, -1, 2558 22, 23, 24, 25, 2559 -1, -1, -1, -1, 2560 26, -1, -1, -1, 2561 27, -1, -1, -1, 2562 28, -1, -1, -1, 2563 /* TSCF 0*/ 2564 29, 30, 31, 32 2565 }; 2566 static int port_speed_max_op5_1[] = { 2567 0, -1, 2568 /* TSC4L 0~5 */ 2569 25, 25, 25, 25, 2570 -1, -1, -1, -1, 2571 25, 25, 25, 25, 2572 -1, -1, -1, -1, 2573 25, 25, 25, 25, 2574 -1, -1, -1, -1, 2575 /* TSC4Q 0~1 */ 2576 25, 25, 25, 25, -1, -1, -1, -1, 2577 -1, -1, -1, -1, -1, -1, -1, -1, 2578 -1, -1, -1, -1, -1, -1, -1, -1, 2579 -1, -1, -1, -1, -1, -1, -1, -1, 2580 /* TSC 0~6*/ 2581 25, 25, 25, 25, 2582 -1, -1, -1, -1, 2583 25, 25, 25, 25, 2584 -1, -1, -1, -1, 2585 420, -1, -1, -1, 2586 100, -1, -1, -1, 2587 420, -1, -1, -1, 2588 /* TSCF 0*/ 2589 250, 250, 250, 250 2590 }; 2591 uint32 tdm_table_op5_1[204] = { 2592 4, 87, 59, 74, 88, 82, 89, 78, 74, 86, 2593 21, 87, 82, 10, 88, 74, 89, 61, 82, 86, 2594 29, 87, 74, 68, 88, 82, 89, 5, 74, 86, 2595 78, 82, 87, 67, 88, 74, 82, 89, 18, 86, 2596 11, 74, 87, 82, 88, 58, 26, 89, 74, 86, 2597 82, 2, 87, 78, 74, 88, 82, 89, 60, 0, 2598 86, 74, 87, 82, 12, 88, 19, 89, 74, 82, 2599 86, 27, 87, 74, 69, 88, 82, 89, 3, 74, 2600 86, 78, 82, 87, 127, 88, 74, 59, 89, 82, 2601 86, 13, 74, 87, 20, 88, 82, 28, 89, 74, 2602 86, 82, 4, 87, 78, 74, 88, 82, 89, 61, 2603 74, 86, 66, 87, 82, 10, 88, 74, 89, 21, 2604 82, 86, 29, 87, 74, 68, 88, 82, 89, 5, 2605 74, 86, 78, 82, 87, 67, 88, 74, 58, 89, 2606 82, 86, 11, 74, 87, 18, 88, 82, 26, 89, 2607 74, 86, 82, 2, 87, 78, 74, 88, 82, 89, 2608 60, 19, 86, 74, 87, 82, 12, 88, 74, 89, 2609 127, 82, 86, 27, 87, 74, 69, 88, 82, 89, 2610 3, 74, 86, 78, 82, 87, 20, 88, 74, 13, 2611 89, 82, 86, 127, 74, 87, 66, 88, 82, 28, 2612 89, 74, 86, 82 2613 }; 2614 2615 /* OPTION_5_3, 24P 2.5G + 2P 50G + 2P 40G */ 2616 static int p2l_mapping_op5_3[] = { 2617 0, -1, 2618 /* TSC4L 0~5 */ 2619 2, 3, 4, 5, 2620 -1, -1, -1, -1, 2621 6, 7, 8, 9, 2622 -1, -1, -1, -1, 2623 10, 11, 12, 13, 2624 -1, -1, -1, -1, 2625 /* TSC4Q 0~1 */ 2626 14, 15, 16, 17, -1, -1, -1, -1, 2627 -1, -1, -1, -1, -1, -1, -1, -1, 2628 -1, -1, -1, -1, -1, -1, -1, -1, 2629 -1, -1, -1, -1, -1, -1, -1, -1, 2630 /* TSC 0~6*/ 2631 18, 19, 20, 21, 2632 -1, -1, -1, -1, 2633 22, 23, 24, 25, 2634 -1, -1, -1, -1, 2635 26, -1, -1, -1, 2636 27, -1, -1, -1, 2637 28, -1, -1, -1, 2638 /* TSCF 0*/ 2639 29, -1, 30, -1 2640 }; 2641 static int port_speed_max_op5_3[] = { 2642 0, -1, 2643 /* TSC4L 0~5 */ 2644 25, 25, 25, 25, 2645 -1, -1, -1, -1, 2646 25, 25, 25, 25, 2647 -1, -1, -1, -1, 2648 25, 25, 25, 25, 2649 -1, -1, -1, -1, 2650 /* TSC4Q 0~1 */ 2651 25, 25, 25, 25, -1, -1, -1, -1, 2652 -1, -1, -1, -1, -1, -1, -1, -1, 2653 -1, -1, -1, -1, -1, -1, -1, -1, 2654 -1, -1, -1, -1, -1, -1, -1, -1, 2655 /* TSC 0~6*/ 2656 25, 25, 25, 25, 2657 -1, -1, -1, -1, 2658 25, 25, 25, 25, 2659 -1, -1, -1, -1, 2660 420, -1, -1, -1, 2661 100, -1, -1, -1, 2662 420, -1, -1, -1, 2663 /* TSCF 0*/ 2664 530, -1, 530, -1 2665 }; 2666 uint32 tdm_table_op5_3[102] = { 2667 11, 74, 88, 82, 86, 18, 2, 88, 74, 86, 2668 82, 26, 88, 66, 74, 86, 82, 88, 68, 74, 2669 86, 78, 88, 82, 58, 86, 74, 88, 12, 82, 2670 86, 19, 88, 74, 3, 86, 82, 27, 88, 74, 2671 86, 60, 82, 88, 0, 86, 74, 78, 88, 82, 2672 86, 28, 74, 88, 13, 86, 82, 4, 88, 74, 2673 86, 82, 20, 88, 67, 74, 86, 82, 88, 69, 2674 74, 86, 78, 88, 82, 59, 86, 74, 88, 10, 2675 82, 86, 5, 88, 74, 21, 86, 82, 29, 88, 2676 74, 86, 61, 82, 88, 127, 86, 74, 78, 88, 2677 82, 86 2678 }; 2679 2680 /* OPTION_6_0, 36P 1G + 12P 10G + 4P 25G + 8P 10G */ 2681 static int p2l_mapping_op6_0[] = { 2682 0, -1, 2683 /* TSC4L 0~5 */ 2684 2, 3, 4, 5, 2685 -1, -1, -1, -1, 2686 -1, -1, -1, -1, 2687 -1, -1, -1, -1, 2688 -1, -1, -1, -1, 2689 -1, -1, -1, -1, 2690 /* TSC4Q 0~1 */ 2691 6, 7, 8, 9, 10, 11, 12, 13, 2692 14, 15, 16, 17, 18, 19, 20, 21, 2693 22, 23, 24, 25, 26, 27, 28, 29, 2694 30, 31, 32, 33, 34, 35, 36, 37, 2695 /* TSC 0~6*/ 2696 38, 39, 40, 41, 2697 -1, -1, -1, -1, 2698 42, 43, 44, 45, 2699 46, 47, 48, 49, 2700 50, 51, 52, 53, 2701 54, -1, -1, -1, 2702 55, 56, 57, 58, 2703 /* TSCF 0*/ 2704 59, 60, 61, 62 2705 }; 2706 static int port_speed_max_op6_0[] = { 2707 0, -1, 2708 /* TSC4L 0~5 */ 2709 10, 10, 10, 10, 2710 -1, -1, -1, -1, 2711 -1, -1, -1, -1, 2712 -1, -1, -1, -1, 2713 -1, -1, -1, -1, 2714 -1, -1, -1, -1, 2715 /* TSC4Q 0~1 */ 2716 10, 10, 10, 10, 10, 10, 10, 10, 2717 10, 10, 10, 10, 10, 10, 10, 10, 2718 10, 10, 10, 10, 10, 10, 10, 10, 2719 10, 10, 10, 10, 10, 10, 10, 10, 2720 /* TSC 0~6*/ 2721 100, 100, 100, 100, 2722 -1, -1, -1, -1, 2723 100, 100, 100, 100, 2724 100, 100, 100, 100, 2725 110, 110, 110, 110, 2726 100, -1, -1, -1, 2727 110, 110, 110, 110, 2728 /* TSCF 0*/ 2729 250, 250, 250, 250 2730 }; 2731 uint32 tdm_table_op6_0[315] = { 2732 86, 58, 2, 66, 88, 70, 74, 87, 82, 59, 2733 3, 89, 67, 71, 75, 86, 83, 60, 78, 88, 2734 4, 68, 87, 72, 76, 84, 89, 61, 5, 69, 2735 86, 73, 77, 85, 88, 58, 26, 87, 66, 70, 2736 74, 89, 82, 59, 27, 86, 78, 67, 71, 88, 2737 75, 83, 87, 60, 28, 68, 89, 72, 76, 84, 2738 86, 61, 78, 29, 88, 69, 73, 87, 77, 85, 2739 58, 89, 30, 66, 70, 86, 74, 82, 59, 88, 2740 31, 67, 87, 71, 75, 83, 89, 60, 78, 32, 2741 86, 68, 72, 76, 88, 84, 61, 87, 33, 69, 2742 73, 89, 77, 34, 85, 86, 58, 35, 66, 88, 2743 70, 74, 87, 82, 59, 36, 89, 67, 71, 75, 2744 86, 83, 60, 78, 88, 37, 68, 87, 72, 76, 2745 84, 89, 61, 38, 69, 86, 73, 77, 85, 88, 2746 58, 39, 87, 66, 70, 74, 89, 82, 59, 40, 2747 86, 78, 67, 71, 88, 75, 83, 87, 60, 41, 2748 68, 89, 72, 76, 84, 86, 61, 78, 42, 88, 2749 69, 73, 87, 77, 85, 58, 89, 43, 66, 70, 2750 86, 74, 82, 59, 88, 44, 67, 87, 71, 75, 2751 83, 89, 60, 78, 45, 86, 68, 72, 76, 88, 2752 84, 61, 87, 46, 69, 73, 89, 77, 47, 85, 2753 86, 58, 127, 66, 88, 70, 74, 87, 82, 59, 2754 48, 89, 67, 71, 75, 86, 83, 60, 78, 88, 2755 49, 68, 87, 72, 76, 84, 89, 61, 50, 69, 2756 86, 73, 77, 85, 88, 58, 51, 87, 66, 70, 2757 74, 89, 82, 59, 52, 86, 78, 67, 71, 88, 2758 75, 83, 87, 60, 53, 68, 89, 72, 76, 84, 2759 86, 61, 78, 54, 88, 69, 73, 87, 77, 85, 2760 58, 89, 127, 66, 70, 86, 74, 82, 59, 88, 2761 55, 67, 87, 71, 75, 83, 89, 60, 78, 56, 2762 86, 68, 72, 76, 88, 84, 61, 87, 57, 69, 2763 73, 89, 77, 0, 85 2764 }; 2765 2766 /* OPTION_6_1, 36P 1G + 12P 10G + 4P 25G + 2P 40G */ 2767 static int p2l_mapping_op6_1[] = { 2768 0, -1, 2769 /* TSC4L 0~5 */ 2770 2, 3, 4, 5, 2771 -1, -1, -1, -1, 2772 -1, -1, -1, -1, 2773 -1, -1, -1, -1, 2774 -1, -1, -1, -1, 2775 -1, -1, -1, -1, 2776 /* TSC4Q 0~1 */ 2777 6, 7, 8, 9, 10, 11, 12, 13, 2778 14, 15, 16, 17, 18, 19, 20, 21, 2779 22, 23, 24, 25, 26, 27, 28, 29, 2780 30, 31, 32, 33, 34, 35, 36, 37, 2781 /* TSC 0~6*/ 2782 38, 39, 40, 41, 2783 -1, -1, -1, -1, 2784 42, 43, 44, 45, 2785 46, 47, 48, 49, 2786 50, -1, -1, -1, 2787 51, -1, -1, -1, 2788 52, -1, -1, -1, 2789 /* TSCF 0*/ 2790 53, 54, 55, 56 2791 }; 2792 static int port_speed_max_op6_1[] = { 2793 0, -1, 2794 /* TSC4L 0~5 */ 2795 10, 10, 10, 10, 2796 -1, -1, -1, -1, 2797 -1, -1, -1, -1, 2798 -1, -1, -1, -1, 2799 -1, -1, -1, -1, 2800 -1, -1, -1, -1, 2801 /* TSC4Q 0~1 */ 2802 10, 10, 10, 10, 10, 10, 10, 10, 2803 10, 10, 10, 10, 10, 10, 10, 10, 2804 10, 10, 10, 10, 10, 10, 10, 10, 2805 10, 10, 10, 10, 10, 10, 10, 10, 2806 /* TSC 0~6*/ 2807 100, 100, 100, 100, 2808 -1, -1, -1, -1, 2809 100, 100, 100, 100, 2810 100, 100, 100, 100, 2811 420, -1, -1, -1, 2812 100, -1, -1, -1, 2813 420, -1, -1, -1, 2814 /* TSCF 0*/ 2815 250, 250, 250, 250 2816 }; 2817 uint32 tdm_table_op6_1[315] = { 2818 86, 58, 2, 66, 88, 70, 74, 87, 82, 59, 2819 3, 89, 67, 71, 74, 86, 82, 60, 78, 88, 2820 4, 68, 87, 72, 74, 82, 89, 61, 5, 69, 2821 86, 73, 74, 82, 88, 58, 26, 87, 66, 70, 2822 74, 89, 82, 59, 27, 86, 78, 67, 71, 88, 2823 74, 82, 87, 60, 28, 68, 89, 72, 74, 82, 2824 86, 61, 78, 29, 88, 69, 73, 87, 74, 82, 2825 58, 89, 30, 66, 70, 86, 74, 82, 59, 88, 2826 31, 67, 87, 71, 74, 82, 89, 60, 78, 32, 2827 86, 68, 72, 74, 88, 82, 61, 87, 33, 69, 2828 73, 89, 74, 34, 82, 86, 58, 35, 66, 88, 2829 70, 74, 87, 82, 59, 36, 89, 67, 71, 74, 2830 86, 82, 60, 78, 88, 37, 68, 87, 72, 74, 2831 82, 89, 61, 38, 69, 86, 73, 74, 82, 88, 2832 58, 39, 87, 66, 70, 74, 89, 82, 59, 40, 2833 86, 78, 67, 71, 88, 74, 82, 87, 60, 41, 2834 68, 89, 72, 74, 82, 86, 61, 78, 42, 88, 2835 69, 73, 87, 74, 82, 58, 89, 43, 66, 70, 2836 86, 74, 82, 59, 88, 44, 67, 87, 71, 74, 2837 82, 89, 60, 78, 45, 86, 68, 72, 74, 88, 2838 82, 61, 87, 46, 69, 73, 89, 74, 47, 82, 2839 86, 58, 127, 66, 88, 70, 74, 87, 82, 59, 2840 48, 89, 67, 71, 74, 86, 82, 60, 78, 88, 2841 49, 68, 87, 72, 74, 82, 89, 61, 50, 69, 2842 86, 73, 74, 82, 88, 58, 51, 87, 66, 70, 2843 74, 89, 82, 59, 52, 86, 78, 67, 71, 88, 2844 74, 82, 87, 60, 53, 68, 89, 72, 74, 82, 2845 86, 61, 78, 54, 88, 69, 73, 87, 74, 82, 2846 58, 89, 127, 66, 70, 86, 74, 82, 59, 88, 2847 55, 67, 87, 71, 74, 82, 89, 60, 78, 56, 2848 86, 68, 72, 74, 88, 82, 61, 87, 57, 69, 2849 73, 89, 74, 0, 82 2850 }; 2851 2852 /* OPTION_6_2, 36P 1G + 12P 10G + 2P 50G + 8P 10G */ 2853 static int p2l_mapping_op6_2[] = { 2854 0, -1, 2855 /* TSC4L 0~5 */ 2856 2, 3, 4, 5, 2857 -1, -1, -1, -1, 2858 -1, -1, -1, -1, 2859 -1, -1, -1, -1, 2860 -1, -1, -1, -1, 2861 -1, -1, -1, -1, 2862 /* TSC4Q 0~1 */ 2863 6, 7, 8, 9, 10, 11, 12, 13, 2864 14, 15, 16, 17, 18, 19, 20, 21, 2865 22, 23, 24, 25, 26, 27, 28, 29, 2866 30, 31, 32, 33, 34, 35, 36, 37, 2867 /* TSC 0~6*/ 2868 38, 39, 40, 41, 2869 -1, -1, -1, -1, 2870 42, 43, 44, 45, 2871 46, 47, 48, 49, 2872 50, 51, 52, 53, 2873 54, -1, -1, -1, 2874 55, 56, 57, 58, 2875 /* TSCF 0*/ 2876 59, -1, 60, -1 2877 }; 2878 static int port_speed_max_op6_2[] = { 2879 0, -1, 2880 /* TSC4L 0~5 */ 2881 10, 10, 10, 10, 2882 -1, -1, -1, -1, 2883 -1, -1, -1, -1, 2884 -1, -1, -1, -1, 2885 -1, -1, -1, -1, 2886 -1, -1, -1, -1, 2887 /* TSC4Q 0~1 */ 2888 10, 10, 10, 10, 10, 10, 10, 10, 2889 10, 10, 10, 10, 10, 10, 10, 10, 2890 10, 10, 10, 10, 10, 10, 10, 10, 2891 10, 10, 10, 10, 10, 10, 10, 10, 2892 /* TSC 0~6*/ 2893 100, 100, 100, 100, 2894 -1, -1, -1, -1, 2895 100, 100, 100, 100, 2896 100, 100, 100, 100, 2897 110, 110, 110, 110, 2898 100, -1, -1, -1, 2899 110, 110, 110, 110, 2900 /* TSCF 0*/ 2901 530, -1, 530, -1 2902 }; 2903 uint32 tdm_table_op6_2[315] = { 2904 86, 58, 2, 66, 88, 70, 74, 86, 2905 82, 59, 3, 88, 67, 71, 75, 86, 2906 83, 60, 78, 88, 4, 68, 86, 72, 2907 76, 84, 88, 61, 5, 69, 86, 73, 2908 77, 85, 88, 58, 26, 86, 66, 70, 2909 74, 88, 82, 59, 27, 86, 78, 67, 2910 71, 88, 75, 83, 86, 60, 28, 68, 2911 88, 72, 76, 84, 86, 61, 78, 29, 2912 88, 69, 73, 86, 77, 85, 58, 88, 2913 30, 66, 70, 86, 74, 82, 59, 88, 2914 31, 67, 86, 71, 75, 83, 88, 60, 2915 78, 32, 86, 68, 72, 76, 88, 84, 2916 61, 86, 33, 69, 73, 88, 77, 34, 2917 85, 86, 58, 35, 66, 88, 70, 74, 2918 86, 82, 59, 36, 88, 67, 71, 75, 2919 86, 83, 60, 78, 88, 37, 68, 86, 2920 72, 76, 84, 88, 61, 38, 69, 86, 2921 73, 77, 85, 88, 58, 39, 86, 66, 2922 70, 74, 88, 82, 59, 40, 86, 78, 2923 67, 71, 88, 75, 83, 86, 60, 41, 2924 68, 88, 72, 76, 84, 86, 61, 78, 2925 42, 88, 69, 73, 86, 77, 85, 58, 2926 88, 43, 66, 70, 86, 74, 82, 59, 2927 88, 44, 67, 86, 71, 75, 83, 88, 2928 60, 78, 45, 86, 68, 72, 76, 88, 2929 84, 61, 86, 46, 69, 73, 88, 77, 2930 47, 85, 86, 58, 127, 66, 88, 70, 2931 74, 86, 82, 59, 48, 88, 67, 71, 2932 75, 86, 83, 60, 78, 88, 49, 68, 2933 86, 72, 76, 84, 88, 61, 50, 69, 2934 86, 73, 77, 85, 88, 58, 51, 86, 2935 66, 70, 74, 88, 82, 59, 52, 86, 2936 78, 67, 71, 88, 75, 83, 86, 60, 2937 53, 68, 88, 72, 76, 84, 86, 61, 2938 78, 54, 88, 69, 73, 86, 77, 85, 2939 58, 88, 127, 66, 70, 86, 74, 82, 2940 59, 88, 55, 67, 86, 71, 75, 83, 2941 88, 60, 78, 56, 86, 68, 72, 76, 2942 88, 84, 61, 86, 57, 69, 73, 88, 2943 77, 0, 85 2944 }; 2945 2946 /* OPTION_6_3, 36P 1G + 12P 10G + 2P 50G + 2P 40G */ 2947 static int p2l_mapping_op6_3[] = { 2948 0, -1, 2949 /* TSC4L 0~5 */ 2950 2, 3, 4, 5, 2951 -1, -1, -1, -1, 2952 -1, -1, -1, -1, 2953 -1, -1, -1, -1, 2954 -1, -1, -1, -1, 2955 -1, -1, -1, -1, 2956 /* TSC4Q 0~1 */ 2957 6, 7, 8, 9, 10, 11, 12, 13, 2958 14, 15, 16, 17, 18, 19, 20, 21, 2959 22, 23, 24, 25, 26, 27, 28, 29, 2960 30, 31, 32, 33, 34, 35, 36, 37, 2961 /* TSC 0~6*/ 2962 38, 39, 40, 41, 2963 -1, -1, -1, -1, 2964 42, 43, 44, 45, 2965 46, 47, 48, 49, 2966 50, -1, -1, -1, 2967 51, -1, -1, -1, 2968 52, -1, -1, -1, 2969 /* TSCF 0*/ 2970 53, -1, 54, -1 2971 }; 2972 static int port_speed_max_op6_3[] = { 2973 0, -1, 2974 /* TSC4L 0~5 */ 2975 10, 10, 10, 10, 2976 -1, -1, -1, -1, 2977 -1, -1, -1, -1, 2978 -1, -1, -1, -1, 2979 -1, -1, -1, -1, 2980 -1, -1, -1, -1, 2981 /* TSC4Q 0~1 */ 2982 10, 10, 10, 10, 10, 10, 10, 10, 2983 10, 10, 10, 10, 10, 10, 10, 10, 2984 10, 10, 10, 10, 10, 10, 10, 10, 2985 10, 10, 10, 10, 10, 10, 10, 10, 2986 /* TSC 0~6*/ 2987 100, 100, 100, 100, 2988 -1, -1, -1, -1, 2989 100, 100, 100, 100, 2990 100, 100, 100, 100, 2991 420, -1, -1, -1, 2992 100, -1, -1, -1, 2993 420, -1, -1, -1, 2994 /* TSCF 0*/ 2995 530, -1, 530, -1 2996 }; 2997 uint32 tdm_table_op6_3[315] = { 2998 86, 58, 2, 66, 88, 70, 74, 86, 2999 82, 59, 3, 88, 67, 71, 74, 86, 3000 82, 60, 78, 88, 4, 68, 86, 72, 3001 74, 82, 88, 61, 5, 69, 86, 73, 3002 74, 82, 88, 58, 26, 86, 66, 70, 3003 74, 88, 82, 59, 27, 86, 78, 67, 3004 71, 88, 74, 82, 86, 60, 28, 68, 3005 88, 72, 74, 82, 86, 61, 78, 29, 3006 88, 69, 73, 86, 74, 82, 58, 88, 3007 30, 66, 70, 86, 74, 82, 59, 88, 3008 31, 67, 86, 71, 74, 82, 88, 60, 3009 78, 32, 86, 68, 72, 74, 88, 82, 3010 61, 86, 33, 69, 73, 88, 74, 34, 3011 82, 86, 58, 35, 66, 88, 70, 74, 3012 86, 82, 59, 36, 88, 67, 71, 74, 3013 86, 82, 60, 78, 88, 37, 68, 86, 3014 72, 74, 82, 88, 61, 38, 69, 86, 3015 73, 74, 82, 88, 58, 39, 86, 66, 3016 70, 74, 88, 82, 59, 40, 86, 78, 3017 67, 71, 88, 74, 82, 86, 60, 41, 3018 68, 88, 72, 74, 82, 86, 61, 78, 3019 42, 88, 69, 73, 86, 74, 82, 58, 3020 88, 43, 66, 70, 86, 74, 82, 59, 3021 88, 44, 67, 86, 71, 74, 82, 88, 3022 60, 78, 45, 86, 68, 72, 74, 88, 3023 82, 61, 86, 46, 69, 73, 88, 74, 3024 47, 82, 86, 58, 127, 66, 88, 70, 3025 74, 86, 82, 59, 48, 88, 67, 71, 3026 74, 86, 82, 60, 78, 88, 49, 68, 3027 86, 72, 74, 82, 88, 61, 50, 69, 3028 86, 73, 74, 82, 88, 58, 51, 86, 3029 66, 70, 74, 88, 82, 59, 52, 86, 3030 78, 67, 71, 88, 74, 82, 86, 60, 3031 53, 68, 88, 72, 74, 82, 86, 61, 3032 78, 54, 88, 69, 73, 86, 74, 82, 3033 58, 88, 127, 66, 70, 86, 74, 82, 3034 59, 88, 55, 67, 86, 71, 74, 82, 3035 88, 60, 78, 56, 86, 68, 72, 74, 3036 88, 82, 61, 86, 57, 69, 73, 88, 3037 74, 0, 82 3038 }; 3039 3040 /* OPTION_7_0, 12P 1G + 12P 10G + 4P 25G + 8P 10G */ 3041 static int p2l_mapping_op7_0[] = { 3042 0, -1, 3043 /* TSC4L 0~5 */ 3044 2, 3, 4, 5, 3045 -1, -1, -1, -1, 3046 -1, -1, -1, -1, 3047 -1, -1, -1, -1, 3048 -1, -1, -1, -1, 3049 -1, -1, -1, -1, 3050 /* TSC4Q 0~1 */ 3051 6, 7, 8, 9, 10, 11, 12, 13, 3052 -1, -1, -1, -1, -1, -1, -1, -1, 3053 -1, -1, -1, -1, -1, -1, -1, -1, 3054 -1, -1, -1, -1, -1, -1, -1, -1, 3055 /* TSC 0~6*/ 3056 14, 15, 16, 17, 3057 -1, -1, -1, -1, 3058 18, 19, 20, 21, 3059 22, 23, 24, 25, 3060 26, 27, 28, 29, 3061 30, -1, -1, -1, 3062 31, 32, 33, 34, 3063 /* TSCF 0*/ 3064 35, 36, 37, 38 3065 }; 3066 static int port_speed_max_op7_0[] = { 3067 0, -1, 3068 /* TSC4L 0~5 */ 3069 10, 10, 10, 10, 3070 -1, -1, -1, -1, 3071 -1, -1, -1, -1, 3072 -1, -1, -1, -1, 3073 -1, -1, -1, -1, 3074 -1, -1, -1, -1, 3075 /* TSC4Q 0~1 */ 3076 10, 10, 10, 10, 10, 10, 10, 10, 3077 -1, -1, -1, -1, -1, -1, -1, -1, 3078 -1, -1, -1, -1, -1, -1, -1, -1, 3079 -1, -1, -1, -1, -1, -1, -1, -1, 3080 /* TSC 0~6*/ 3081 100, 100, 100, 100, 3082 -1, -1, -1, -1, 3083 100, 100, 100, 100, 3084 100, 100, 100, 100, 3085 110, 110, 110, 110, 3086 100, -1, -1, -1, 3087 110, 110, 110, 110, 3088 /* TSCF 0*/ 3089 250, 250, 250, 250 3090 }; 3091 uint32 tdm_table_op7_0[204] = { 3092 68, 73, 86, 85, 67, 87, 32, 78, 82, 88, 3093 59, 61, 89, 75, 77, 86, 70, 69, 72, 87, 3094 84, 66, 88, 127, 33, 83, 89, 58, 60, 86, 3095 74, 76, 87, 71, 68, 73, 88, 85, 67, 89, 3096 3, 78, 82, 86, 59, 61, 87, 75, 77, 88, 3097 70, 69, 72, 89, 84, 66, 86, 26, 127, 83, 3098 87, 58, 60, 88, 74, 76, 89, 71, 68, 73, 3099 86, 85, 67, 87, 127, 78, 82, 88, 59, 61, 3100 89, 75, 77, 86, 70, 69, 72, 87, 84, 66, 3101 88, 27, 4, 83, 89, 58, 60, 86, 74, 76, 3102 87, 71, 68, 73, 88, 85, 67, 89, 28, 78, 3103 82, 86, 59, 61, 87, 75, 77, 88, 70, 69, 3104 72, 89, 84, 66, 86, 127, 127, 83, 87, 58, 3105 60, 88, 74, 76, 89, 71, 68, 73, 86, 85, 3106 67, 87, 29, 78, 82, 88, 59, 61, 89, 75, 3107 77, 86, 70, 69, 72, 87, 84, 66, 88, 30, 3108 5, 83, 89, 58, 60, 86, 74, 76, 87, 71, 3109 68, 73, 88, 85, 67, 89, 0, 78, 82, 86, 3110 59, 61, 87, 75, 77, 88, 70, 69, 72, 89, 3111 84, 66, 86, 31, 2, 83, 87, 58, 60, 88, 3112 74, 76, 89, 71 3113 }; 3114 3115 /* OPTION_7_1, 12P 1G + 12P 10G + 4P 25G + 2P 40G */ 3116 static int p2l_mapping_op7_1[] = { 3117 0, -1, 3118 /* TSC4L 0~5 */ 3119 2, 3, 4, 5, 3120 -1, -1, -1, -1, 3121 -1, -1, -1, -1, 3122 -1, -1, -1, -1, 3123 -1, -1, -1, -1, 3124 -1, -1, -1, -1, 3125 /* TSC4Q 0~1 */ 3126 6, 7, 8, 9, 10, 11, 12, 13, 3127 -1, -1, -1, -1, -1, -1, -1, -1, 3128 -1, -1, -1, -1, -1, -1, -1, -1, 3129 -1, -1, -1, -1, -1, -1, -1, -1, 3130 /* TSC 0~6*/ 3131 14, 15, 16, 17, 3132 -1, -1, -1, -1, 3133 18, 19, 20, 21, 3134 22, 23, 24, 25, 3135 26, -1, -1, -1, 3136 27, -1, -1, -1, 3137 28, -1, -1, -1, 3138 /* TSCF 0*/ 3139 29, 30, 31, 32 3140 }; 3141 static int port_speed_max_op7_1[] = { 3142 0, -1, 3143 /* TSC4L 0~5 */ 3144 10, 10, 10, 10, 3145 -1, -1, -1, -1, 3146 -1, -1, -1, -1, 3147 -1, -1, -1, -1, 3148 -1, -1, -1, -1, 3149 -1, -1, -1, -1, 3150 /* TSC4Q 0~1 */ 3151 10, 10, 10, 10, 10, 10, 10, 10, 3152 -1, -1, -1, -1, -1, -1, -1, -1, 3153 -1, -1, -1, -1, -1, -1, -1, -1, 3154 -1, -1, -1, -1, -1, -1, -1, -1, 3155 /* TSC 0~6*/ 3156 100, 100, 100, 100, 3157 -1, -1, -1, -1, 3158 100, 100, 100, 100, 3159 100, 100, 100, 100, 3160 420, -1, -1, -1, 3161 100, -1, -1, -1, 3162 420, -1, -1, -1, 3163 /* TSCF 0*/ 3164 250, 250, 250, 250 3165 }; 3166 uint32 tdm_table_op7_1[204] = { 3167 66, 86, 68, 127, 82, 87, 74, 70, 88, 61, 3168 27, 89, 82, 73, 74, 86, 58, 67, 87, 69, 3169 78, 82, 88, 74, 71, 89, 60, 5, 86, 82, 3170 72, 74, 87, 59, 66, 88, 68, 127, 82, 89, 3171 74, 70, 86, 61, 28, 87, 82, 73, 74, 88, 3172 58, 67, 89, 69, 78, 82, 86, 74, 71, 87, 3173 60, 29, 88, 82, 72, 74, 89, 59, 66, 86, 3174 68, 2, 82, 87, 74, 70, 88, 61, 127, 89, 3175 82, 73, 74, 86, 58, 67, 87, 69, 78, 82, 3176 88, 74, 71, 89, 60, 30, 86, 82, 72, 74, 3177 87, 59, 66, 88, 68, 127, 82, 89, 74, 70, 3178 86, 61, 31, 87, 82, 73, 74, 88, 58, 67, 3179 89, 69, 78, 82, 86, 74, 71, 87, 60, 3, 3180 88, 82, 72, 74, 89, 59, 66, 86, 68, 0, 3181 82, 87, 74, 70, 88, 61, 32, 89, 82, 73, 3182 74, 86, 58, 67, 87, 69, 78, 82, 88, 74, 3183 71, 89, 60, 33, 86, 82, 72, 74, 87, 59, 3184 66, 88, 68, 4, 82, 89, 74, 70, 86, 61, 3185 127, 87, 82, 73, 74, 88, 58, 67, 89, 69, 3186 78, 82, 86, 74, 71, 87, 60, 26, 88, 82, 3187 72, 74, 89, 59 3188 }; 3189 3190 /* OPTION_7_2, 12P 1G + 12P 10G + 2P 50G + 8P 10G */ 3191 static int p2l_mapping_op7_2[] = { 3192 0, -1, 3193 /* TSC4L 0~5 */ 3194 2, 3, 4, 5, 3195 -1, -1, -1, -1, 3196 -1, -1, -1, -1, 3197 -1, -1, -1, -1, 3198 -1, -1, -1, -1, 3199 -1, -1, -1, -1, 3200 /* TSC4Q 0~1 */ 3201 6, 7, 8, 9, 10, 11, 12, 13, 3202 -1, -1, -1, -1, -1, -1, -1, -1, 3203 -1, -1, -1, -1, -1, -1, -1, -1, 3204 -1, -1, -1, -1, -1, -1, -1, -1, 3205 /* TSC 0~6*/ 3206 14, 15, 16, 17, 3207 -1, -1, -1, -1, 3208 18, 19, 20, 21, 3209 22, 23, 24, 25, 3210 26, 27, 28, 29, 3211 30, -1, -1, -1, 3212 31, 32, 33, 34, 3213 /* TSCF 0*/ 3214 35, -1, 36, -1 3215 }; 3216 static int port_speed_max_op7_2[] = { 3217 0, -1, 3218 /* TSC4L 0~5 */ 3219 10, 10, 10, 10, 3220 -1, -1, -1, -1, 3221 -1, -1, -1, -1, 3222 -1, -1, -1, -1, 3223 -1, -1, -1, -1, 3224 -1, -1, -1, -1, 3225 /* TSC4Q 0~1 */ 3226 10, 10, 10, 10, 10, 10, 10, 10, 3227 -1, -1, -1, -1, -1, -1, -1, -1, 3228 -1, -1, -1, -1, -1, -1, -1, -1, 3229 -1, -1, -1, -1, -1, -1, -1, -1, 3230 /* TSC 0~6*/ 3231 100, 100, 100, 100, 3232 -1, -1, -1, -1, 3233 100, 100, 100, 100, 3234 100, 100, 100, 100, 3235 110, 110, 110, 110, 3236 100, -1, -1, -1, 3237 110, 100, 110, 110, 3238 /* TSCF 0*/ 3239 530, -1, 530, -1 3240 }; 3241 uint32 tdm_table_op7_2[204] = { 3242 77, 85, 86, 58, 33, 2, 88, 71, 74, 86, 3243 82, 60, 88, 66, 68, 73, 86, 76, 84, 88, 3244 59, 26, 78, 86, 70, 75, 88, 83, 61, 86, 3245 67, 69, 72, 88, 77, 85, 86, 58, 127, 27, 3246 88, 71, 74, 86, 82, 60, 88, 66, 68, 73, 3247 86, 76, 84, 88, 59, 3, 78, 86, 70, 75, 3248 88, 83, 61, 86, 67, 69, 72, 88, 77, 85, 3249 86, 58, 28, 127, 88, 71, 74, 86, 82, 60, 3250 88, 66, 68, 73, 86, 76, 84, 88, 59, 0, 3251 78, 86, 70, 75, 88, 83, 61, 86, 67, 69, 3252 72, 88, 77, 85, 86, 58, 29, 4, 88, 71, 3253 74, 86, 82, 60, 88, 66, 68, 73, 86, 76, 3254 84, 88, 59, 30, 78, 86, 70, 75, 88, 83, 3255 61, 86, 67, 69, 72, 88, 77, 85, 86, 58, 3256 127, 31, 88, 71, 74, 86, 82, 60, 88, 66, 3257 68, 73, 86, 76, 84, 88, 59, 5, 78, 86, 3258 70, 75, 88, 83, 61, 86, 67, 69, 72, 88, 3259 77, 85, 86, 58, 32, 127, 88, 71, 74, 86, 3260 82, 60, 88, 66, 68, 73, 86, 76, 84, 88, 3261 59, 127, 78, 86, 70, 75, 88, 83, 61, 86, 3262 67, 69, 72, 88 3263 }; 3264 3265 /* OPTION_7_3, 12P 1G + 12P 10G + 2P 50G + 2P 40G */ 3266 static int p2l_mapping_op7_3[] = { 3267 0, -1, 3268 /* TSC4L 0~5 */ 3269 2, 3, 4, 5, 3270 -1, -1, -1, -1, 3271 -1, -1, -1, -1, 3272 -1, -1, -1, -1, 3273 -1, -1, -1, -1, 3274 -1, -1, -1, -1, 3275 /* TSC4Q 0~1 */ 3276 6, 7, 8, 9, 10, 11, 12, 13, 3277 -1, -1, -1, -1, -1, -1, -1, -1, 3278 -1, -1, -1, -1, -1, -1, -1, -1, 3279 -1, -1, -1, -1, -1, -1, -1, -1, 3280 /* TSC 0~6*/ 3281 14, 15, 16, 17, 3282 -1, -1, -1, -1, 3283 18, 19, 20, 21, 3284 22, 23, 24, 25, 3285 26, -1, -1, -1, 3286 27, -1, -1, -1, 3287 28, -1, -1, -1, 3288 /* TSCF 0*/ 3289 29, -1, 30, -1 3290 }; 3291 static int port_speed_max_op7_3[] = { 3292 0, -1, 3293 /* TSC4L 0~5 */ 3294 10, 10, 10, 10, 3295 -1, -1, -1, -1, 3296 -1, -1, -1, -1, 3297 -1, -1, -1, -1, 3298 -1, -1, -1, -1, 3299 -1, -1, -1, -1, 3300 /* TSC4Q 0~1 */ 3301 10, 10, 10, 10, 10, 10, 10, 10, 3302 -1, -1, -1, -1, -1, -1, -1, -1, 3303 -1, -1, -1, -1, -1, -1, -1, -1, 3304 -1, -1, -1, -1, -1, -1, -1, -1, 3305 /* TSC 0~6*/ 3306 100, 100, 100, 100, 3307 -1, -1, -1, -1, 3308 100, 100, 100, 100, 3309 100, 100, 100, 100, 3310 420, -1, -1, -1, 3311 100, -1, -1, -1, 3312 420, -1, -1, -1, 3313 /* TSCF 0*/ 3314 530, -1, 530, -1 3315 }; 3316 uint32 tdm_table_op7_3[204] = { 3317 71, 88, 60, 74, 86, 26, 82, 0, 88, 72, 3318 68, 86, 74, 67, 82, 88, 58, 70, 86, 61, 3319 74, 88, 127, 82, 78, 86, 73, 69, 88, 74, 3320 66, 82, 86, 59, 71, 88, 60, 74, 86, 27, 3321 82, 2, 88, 72, 68, 86, 74, 67, 82, 88, 3322 58, 70, 86, 61, 74, 88, 28, 82, 78, 86, 3323 73, 69, 88, 74, 66, 82, 86, 59, 71, 88, 3324 60, 74, 86, 127, 82, 29, 88, 72, 68, 86, 3325 74, 67, 82, 88, 58, 70, 86, 61, 74, 88, 3326 127, 82, 78, 86, 73, 69, 88, 74, 66, 82, 3327 86, 59, 71, 88, 60, 74, 86, 30, 82, 3, 3328 88, 72, 68, 86, 74, 67, 82, 88, 58, 70, 3329 86, 61, 74, 88, 127, 82, 78, 86, 73, 69, 3330 88, 74, 66, 82, 86, 59, 71, 88, 60, 74, 3331 86, 31, 82, 4, 88, 72, 68, 86, 74, 67, 3332 82, 88, 58, 70, 86, 61, 74, 88, 32, 82, 3333 78, 86, 73, 69, 88, 74, 66, 82, 86, 59, 3334 71, 88, 60, 74, 86, 127, 82, 33, 88, 72, 3335 68, 86, 74, 67, 82, 88, 58, 70, 86, 61, 3336 74, 88, 5, 82, 78, 86, 73, 69, 88, 74, 3337 66, 82, 86, 59 3338 }; 3339 3340 /* OPTION_8_0, 56P 1G + 4P 25G + 4P 10G */ 3341 static int p2l_mapping_op8_0[] = { 3342 0, -1, 3343 /* TSC4L 0~5 */ 3344 2, 3, 4, 5, 3345 6, 7, 8, 9, 3346 10, 11, 12, 13, 3347 14, 15, 16, 17, 3348 18, 19, 20, 21, 3349 22, 23, 24, 25, 3350 /* TSC4Q 0~1 */ 3351 26, 27, 28, 29, 30, 31, 32, 33, 3352 34, 35, 36, 37, 38, 39, 40, 41, 3353 42, 43, 44, 45, 46, 47, 48, 49, 3354 50, 51, 52, 53, 54, 55, 56, 57, 3355 /* TSC 0~6*/ 3356 -1, -1, -1, -1, 3357 -1, -1, -1, -1, 3358 -1, -1, -1, -1, 3359 -1, -1, -1, -1, 3360 -1, -1, -1, -1, 3361 -1, -1, -1, -1, 3362 58, 59, 60, 61, 3363 /* TSCF 0*/ 3364 62, 63, 64, 65 3365 }; 3366 static int port_speed_max_op8_0[] = { 3367 0, -1, 3368 /* TSC4L 0~5 */ 3369 10, 10, 10, 10, 3370 10, 10, 10, 10, 3371 10, 10, 10, 10, 3372 10, 10, 10, 10, 3373 10, 10, 10, 10, 3374 10, 10, 10, 10, 3375 /* TSC4Q 0~1 */ 3376 10, 10, 10, 10, 10, 10, 10, 10, 3377 10, 10, 10, 10, 10, 10, 10, 10, 3378 10, 10, 10, 10, 10, 10, 10, 10, 3379 10, 10, 10, 10, 10, 10, 10, 10, 3380 /* TSC 0~6*/ 3381 -1, -1, -1, -1, 3382 -1, -1, -1, -1, 3383 -1, -1, -1, -1, 3384 -1, -1, -1, -1, 3385 -1, -1, -1, -1, 3386 -1, -1, -1, -1, 3387 110, 110, 110, 110, 3388 /* TSCF 0*/ 3389 250, 250, 250, 250 3390 }; 3391 uint32 tdm_table_op8_0[200] = { 3392 88, 15, 89, 85, 86, 39, 87, 83, 88, 20, 3393 89, 29, 86, 84, 87, 55, 88, 82, 89, 2, 3394 86, 127, 87, 85, 88, 16, 89, 83, 86, 42, 3395 87, 21, 88, 84, 89, 30, 86, 82, 87, 40, 3396 88, 3, 89, 85, 86, 56, 87, 83, 88, 17, 3397 89, 43, 86, 84, 87, 127, 88, 82, 89, 22, 3398 86, 31, 87, 85, 88, 41, 89, 83, 86, 4, 3399 87, 57, 88, 84, 89, 10, 86, 82, 87, 44, 3400 88, 23, 89, 85, 86, 32, 87, 83, 88, 34, 3401 89, 5, 86, 84, 87, 50, 88, 82, 89, 11, 3402 86, 127, 87, 85, 88, 33, 89, 83, 86, 24, 3403 87, 35, 88, 84, 89, 45, 86, 82, 87, 6, 3404 88, 51, 89, 85, 86, 12, 87, 83, 88, 46, 3405 89, 25, 86, 84, 87, 26, 88, 82, 89, 36, 3406 86, 52, 87, 85, 88, 7, 89, 83, 86, 47, 3407 87, 13, 88, 84, 89, 37, 86, 82, 87, 18, 3408 88, 27, 89, 85, 86, 53, 87, 83, 88, 8, 3409 89, 0, 86, 84, 87, 14, 88, 82, 89, 48, 3410 86, 38, 87, 85, 88, 19, 89, 83, 86, 28, 3411 87, 9, 88, 84, 89, 54, 86, 82, 87, 49 3412 }; 3413 3414 /* OPTION_8_1, 56P 1G + 4P 25G + 1P 40G */ 3415 static int p2l_mapping_op8_1[] = { 3416 0, -1, 3417 /* TSC4L 0~5 */ 3418 2, 3, 4, 5, 3419 6, 7, 8, 9, 3420 10, 11, 12, 13, 3421 14, 15, 16, 17, 3422 18, 19, 20, 21, 3423 22, 23, 24, 25, 3424 /* TSC4Q 0~1 */ 3425 26, 27, 28, 29, 30, 31, 32, 33, 3426 34, 35, 36, 37, 38, 39, 40, 41, 3427 42, 43, 44, 45, 46, 47, 48, 49, 3428 50, 51, 52, 53, 54, 55, 56, 57, 3429 /* TSC 0~6*/ 3430 -1, -1, -1, -1, 3431 -1, -1, -1, -1, 3432 -1, -1, -1, -1, 3433 -1, -1, -1, -1, 3434 -1, -1, -1, -1, 3435 -1, -1, -1, -1, 3436 58, -1, -1, -1, 3437 /* TSCF 0*/ 3438 59, 60, 61, 62 3439 }; 3440 static int port_speed_max_op8_1[] = { 3441 0, -1, 3442 /* TSC4L 0~5 */ 3443 10, 10, 10, 10, 3444 10, 10, 10, 10, 3445 10, 10, 10, 10, 3446 10, 10, 10, 10, 3447 10, 10, 10, 10, 3448 10, 10, 10, 10, 3449 /* TSC4Q 0~1 */ 3450 10, 10, 10, 10, 10, 10, 10, 10, 3451 10, 10, 10, 10, 10, 10, 10, 10, 3452 10, 10, 10, 10, 10, 10, 10, 10, 3453 10, 10, 10, 10, 10, 10, 10, 10, 3454 /* TSC 0~6*/ 3455 -1, -1, -1, -1, 3456 -1, -1, -1, -1, 3457 -1, -1, -1, -1, 3458 -1, -1, -1, -1, 3459 -1, -1, -1, -1, 3460 -1, -1, -1, -1, 3461 420, -1, -1, -1, 3462 /* TSCF 0*/ 3463 250, 250, 250, 250 3464 }; 3465 uint32 tdm_table_op8_1[176] = { 3466 88, 82, 89, 127, 86, 42, 87, 82, 88, 17, 3467 31, 89, 82, 86, 34, 87, 9, 88, 82, 89, 3468 56, 23, 86, 82, 87, 127, 88, 43, 89, 82, 3469 86, 10, 32, 87, 82, 88, 35, 89, 2, 86, 3470 82, 87, 57, 24, 88, 82, 89, 127, 86, 44, 3471 87, 82, 88, 11, 33, 89, 82, 86, 36, 87, 3472 3, 88, 82, 89, 50, 25, 86, 82, 87, 127, 3473 88, 45, 89, 82, 86, 12, 26, 87, 82, 88, 3474 37, 89, 4, 86, 82, 87, 51, 18, 88, 82, 3475 89, 127, 86, 46, 87, 82, 88, 13, 27, 89, 3476 82, 86, 38, 87, 5, 88, 82, 89, 52, 19, 3477 86, 82, 87, 127, 88, 47, 89, 82, 86, 14, 3478 28, 87, 82, 88, 39, 89, 6, 86, 82, 87, 3479 53, 20, 88, 82, 89, 0, 86, 48, 87, 82, 3480 88, 15, 29, 89, 82, 86, 40, 87, 7, 88, 3481 82, 89, 54, 21, 86, 82, 87, 127, 88, 49, 3482 89, 82, 86, 16, 30, 87, 82, 88, 41, 89, 3483 8, 86, 82, 87, 55, 22 3484 }; 3485 3486 /* OPTION_8_2, 56P 1G + 2P 50G + 4P 10G */ 3487 static int p2l_mapping_op8_2[] = { 3488 0, -1, 3489 /* TSC4L 0~5 */ 3490 2, 3, 4, 5, 3491 6, 7, 8, 9, 3492 10, 11, 12, 13, 3493 14, 15, 16, 17, 3494 18, 19, 20, 21, 3495 22, 23, 24, 25, 3496 /* TSC4Q 0~1 */ 3497 26, 27, 28, 29, 30, 31, 32, 33, 3498 34, 35, 36, 37, 38, 39, 40, 41, 3499 42, 43, 44, 45, 46, 47, 48, 49, 3500 50, 51, 52, 53, 54, 55, 56, 57, 3501 /* TSC 0~6*/ 3502 -1, -1, -1, -1, 3503 -1, -1, -1, -1, 3504 -1, -1, -1, -1, 3505 -1, -1, -1, -1, 3506 -1, -1, -1, -1, 3507 -1, -1, -1, -1, 3508 58, 59, 60, 61, 3509 /* TSCF 0*/ 3510 62, -1, 63, -1 3511 }; 3512 static int port_speed_max_op8_2[] = { 3513 0, -1, 3514 /* TSC4L 0~5 */ 3515 10, 10, 10, 10, 3516 10, 10, 10, 10, 3517 10, 10, 10, 10, 3518 10, 10, 10, 10, 3519 10, 10, 10, 10, 3520 10, 10, 10, 10, 3521 /* TSC4Q 0~1 */ 3522 10, 10, 10, 10, 10, 10, 10, 10, 3523 10, 10, 10, 10, 10, 10, 10, 10, 3524 10, 10, 10, 10, 10, 10, 10, 10, 3525 10, 10, 10, 10, 10, 10, 10, 10, 3526 /* TSC 0~6*/ 3527 -1, -1, -1, -1, 3528 -1, -1, -1, -1, 3529 -1, -1, -1, -1, 3530 -1, -1, -1, -1, 3531 -1, -1, -1, -1, 3532 -1, -1, -1, -1, 3533 110, 110, 110, 110, 3534 /* TSCF 0*/ 3535 530, -1, 530, -1 3536 }; 3537 uint32 tdm_table_op8_2[196] = { 3538 83, 88, 40, 86, 84, 88, 42, 86, 16, 88, 3539 82, 86, 57, 88, 85, 86, 22, 88, 29, 86, 3540 83, 88, 41, 86, 84, 88, 9, 86, 43, 88, 3541 82, 86, 50, 88, 85, 86, 17, 88, 34, 86, 3542 83, 88, 23, 86, 84, 88, 30, 86, 82, 88, 3543 2, 86, 44, 88, 85, 86, 35, 88, 83, 86, 3544 10, 88, 24, 86, 84, 88, 31, 86, 82, 88, 3545 51, 86, 85, 88, 0, 86, 3, 88, 83, 86, 3546 45, 88, 84, 86, 52, 88, 11, 86, 82, 88, 3547 25, 86, 85, 88, 32, 86, 36, 88, 83, 86, 3548 4, 88, 84, 86, 46, 88, 37, 86, 82, 88, 3549 12, 86, 85, 88, 18, 86, 33, 88, 83, 86, 3550 53, 88, 84, 86, 5, 88, 54, 86, 82, 88, 3551 38, 86, 85, 88, 13, 86, 19, 88, 83, 86, 3552 26, 88, 84, 86, 47, 88, 82, 86, 6, 88, 3553 48, 86, 85, 88, 127, 86, 20, 88, 83, 86, 3554 84, 88, 14, 86, 39, 88, 82, 86, 27, 88, 3555 7, 86, 85, 88, 55, 86, 83, 88, 49, 86, 3556 84, 88, 56, 86, 15, 88, 82, 86, 21, 88, 3557 85, 86, 28, 88, 8, 86 3558 }; 3559 3560 /* OPTION_8_3, 56P 1G + 2P 50G + 1P 40G */ 3561 static int p2l_mapping_op8_3[] = { 3562 0, -1, 3563 /* TSC4L 0~5 */ 3564 2, 3, 4, 5, 3565 6, 7, 8, 9, 3566 10, 11, 12, 13, 3567 14, 15, 16, 17, 3568 18, 19, 20, 21, 3569 22, 23, 24, 25, 3570 /* TSC4Q 0~1 */ 3571 26, 27, 28, 29, 30, 31, 32, 33, 3572 34, 35, 36, 37, 38, 39, 40, 41, 3573 42, 43, 44, 45, 46, 47, 48, 49, 3574 50, 51, 52, 53, 54, 55, 56, 57, 3575 /* TSC 0~6*/ 3576 -1, -1, -1, -1, 3577 -1, -1, -1, -1, 3578 -1, -1, -1, -1, 3579 -1, -1, -1, -1, 3580 -1, -1, -1, -1, 3581 -1, -1, -1, -1, 3582 58, -1, -1, -1, 3583 /* TSCF 0*/ 3584 59, -1, 60, -1 3585 }; 3586 static int port_speed_max_op8_3[] = { 3587 0, -1, 3588 /* TSC4L 0~5 */ 3589 10, 10, 10, 10, 3590 10, 10, 10, 10, 3591 10, 10, 10, 10, 3592 10, 10, 10, 10, 3593 10, 10, 10, 10, 3594 10, 10, 10, 10, 3595 /* TSC4Q 0~1 */ 3596 10, 10, 10, 10, 10, 10, 10, 10, 3597 10, 10, 10, 10, 10, 10, 10, 10, 3598 10, 10, 10, 10, 10, 10, 10, 10, 3599 10, 10, 10, 10, 10, 10, 10, 10, 3600 /* TSC 0~6*/ 3601 -1, -1, -1, -1, 3602 -1, -1, -1, -1, 3603 -1, -1, -1, -1, 3604 -1, -1, -1, -1, 3605 -1, -1, -1, -1, 3606 -1, -1, -1, -1, 3607 420, -1, -1, -1, 3608 /* TSCF 0*/ 3609 530, -1, 530, -1 3610 }; 3611 uint32 tdm_table_op8_3[184] = { 3612 86, 82, 88, 7, 86, 13, 88, 82, 86, 21, 3613 88, 46, 82, 86, 127, 88, 82, 86, 28, 88, 3614 38, 86, 82, 8, 88, 47, 86, 82, 88, 22, 3615 86, 14, 88, 82, 51, 86, 0, 88, 82, 86, 3616 39, 88, 29, 86, 82, 9, 88, 48, 86, 82, 3617 88, 23, 86, 52, 88, 82, 86, 15, 127, 88, 3618 82, 86, 53, 88, 30, 86, 82, 88, 40, 2, 3619 86, 82, 88, 127, 86, 16, 88, 82, 86, 24, 3620 49, 88, 82, 86, 54, 88, 41, 86, 82, 88, 3621 31, 3, 86, 82, 88, 127, 86, 42, 88, 82, 3622 86, 17, 88, 25, 82, 86, 55, 88, 82, 86, 3623 32, 88, 34, 86, 82, 4, 88, 127, 86, 82, 3624 88, 18, 86, 10, 88, 82, 43, 86, 127, 88, 3625 82, 86, 56, 88, 33, 86, 82, 35, 88, 5, 3626 86, 82, 88, 44, 86, 11, 88, 82, 86, 19, 3627 127, 88, 82, 86, 57, 88, 26, 86, 82, 88, 3628 36, 6, 86, 82, 88, 127, 86, 20, 88, 82, 3629 86, 12, 45, 88, 82, 86, 50, 88, 37, 86, 3630 82, 88, 27, 127 3631 }; 3632 3633 /* OPTION_9_0, 48P 1G + 4P 25G + 8P 10G */ 3634 static int p2l_mapping_op9_0[] = { 3635 0, -1, 3636 /* TSC4L 0~5 */ 3637 2, 3, 4, 5, 3638 6, 7, 8, 9, 3639 10, 11, 12, 13, 3640 14, 15, 16, 17, 3641 -1, -1, -1, -1, 3642 -1, -1, -1, -1, 3643 /* TSC4Q 0~1 */ 3644 18, 19, 20, 21, 22, 23, 24, 25, 3645 26, 27, 28, 29, 30, 31, 32, 33, 3646 34, 35, 36, 37, 38, 39, 40, 41, 3647 42, 43, 44, 45, 46, 47, 48, 49, 3648 /* TSC 0~6*/ 3649 -1, -1, -1, -1, 3650 -1, -1, -1, -1, 3651 -1, -1, -1, -1, 3652 -1, -1, -1, -1, 3653 50, 51, 52, 53, 3654 54, -1, -1, -1, 3655 55, 56, 57, 58, 3656 /* TSCF 0*/ 3657 59, 60, 61, 62 3658 }; 3659 static int port_speed_max_op9_0[] = { 3660 0, -1, 3661 /* TSC4L 0~5 */ 3662 10, 10, 10, 10, 3663 10, 10, 10, 10, 3664 10, 10, 10, 10, 3665 10, 10, 10, 10, 3666 -1, -1, -1, -1, 3667 -1, -1, -1, -1, 3668 /* TSC4Q 0~1 */ 3669 10, 10, 10, 10, 10, 10, 10, 10, 3670 10, 10, 10, 10, 10, 10, 10, 10, 3671 10, 10, 10, 10, 10, 10, 10, 10, 3672 10, 10, 10, 10, 10, 10, 10, 10, 3673 /* TSC 0~6*/ 3674 -1, -1, -1, -1, 3675 -1, -1, -1, -1, 3676 -1, -1, -1, -1, 3677 -1, -1, -1, -1, 3678 110, 110, 110, 110, 3679 100, -1, -1, -1, 3680 110, 110, 110, 110, 3681 /* TSCF 0*/ 3682 250, 250, 250, 250 3683 }; 3684 uint32 tdm_table_op9_0[240] = { 3685 84, 54, 88, 127, 89, 31, 77, 86, 83, 87, 3686 74, 88, 85, 78, 89, 3, 86, 47, 76, 87, 3687 82, 88, 75, 89, 84, 39, 86, 12, 87, 56, 3688 77, 88, 83, 89, 74, 86, 85, 78, 87, 32, 3689 88, 4, 76, 89, 82, 86, 75, 87, 84, 48, 3690 88, 40, 89, 57, 77, 86, 83, 87, 74, 88, 3691 85, 78, 89, 13, 86, 33, 76, 87, 82, 88, 3692 75, 89, 84, 5, 86, 49, 87, 41, 77, 88, 3693 83, 89, 74, 86, 85, 78, 87, 14, 88, 50, 3694 76, 89, 82, 86, 75, 87, 84, 42, 88, 26, 3695 89, 6, 77, 86, 83, 87, 74, 88, 85, 78, 3696 89, 34, 86, 51, 76, 87, 82, 88, 75, 89, 3697 84, 15, 86, 27, 87, 7, 77, 88, 83, 89, 3698 74, 86, 85, 78, 87, 43, 88, 35, 76, 89, 3699 82, 86, 75, 87, 84, 0, 88, 16, 89, 52, 3700 77, 86, 83, 87, 74, 88, 85, 78, 89, 28, 3701 86, 8, 76, 87, 82, 88, 75, 89, 84, 44, 3702 86, 36, 87, 53, 77, 88, 83, 89, 74, 86, 3703 85, 78, 87, 17, 88, 9, 76, 89, 82, 86, 3704 75, 87, 84, 29, 88, 45, 89, 55, 77, 86, 3705 83, 87, 74, 88, 85, 78, 89, 10, 86, 37, 3706 76, 87, 82, 88, 75, 89, 84, 46, 86, 30, 3707 87, 2, 77, 88, 83, 89, 74, 86, 85, 78, 3708 87, 38, 88, 11, 76, 89, 82, 86, 75, 87 3709 }; 3710 3711 /* OPTION_9_1, 48P 1G + 4P 25G + 2P 40G */ 3712 static int p2l_mapping_op9_1[] = { 3713 0, -1, 3714 /* TSC4L 0~5 */ 3715 2, 3, 4, 5, 3716 6, 7, 8, 9, 3717 10, 11, 12, 13, 3718 14, 15, 16, 17, 3719 -1, -1, -1, -1, 3720 -1, -1, -1, -1, 3721 /* TSC4Q 0~1 */ 3722 18, 19, 20, 21, 22, 23, 24, 25, 3723 26, 27, 28, 29, 30, 31, 32, 33, 3724 34, 35, 36, 37, 38, 39, 40, 41, 3725 42, 43, 44, 45, 46, 47, 48, 49, 3726 /* TSC 0~6*/ 3727 -1, -1, -1, -1, 3728 -1, -1, -1, -1, 3729 -1, -1, -1, -1, 3730 -1, -1, -1, -1, 3731 50, -1, -1, -1, 3732 51, -1, -1, -1, 3733 52, -1, -1, -1, 3734 /* TSCF 0*/ 3735 53, 54, 55, 56 3736 }; 3737 static int port_speed_max_op9_1[] = { 3738 0, -1, 3739 /* TSC4L 0~5 */ 3740 10, 10, 10, 10, 3741 10, 10, 10, 10, 3742 10, 10, 10, 10, 3743 10, 10, 10, 10, 3744 -1, -1, -1, -1, 3745 -1, -1, -1, -1, 3746 /* TSC4Q 0~1 */ 3747 10, 10, 10, 10, 10, 10, 10, 10, 3748 10, 10, 10, 10, 10, 10, 10, 10, 3749 10, 10, 10, 10, 10, 10, 10, 10, 3750 10, 10, 10, 10, 10, 10, 10, 10, 3751 /* TSC 0~6*/ 3752 -1, -1, -1, -1, 3753 -1, -1, -1, -1, 3754 -1, -1, -1, -1, 3755 -1, -1, -1, -1, 3756 420, -1, -1, -1, 3757 100, -1, -1, -1, 3758 420, -1, -1, -1, 3759 /* TSCF 0*/ 3760 250, 250, 250, 250 3761 }; 3762 uint32 tdm_table_op9_1[240] = { 3763 48, 74, 86, 82, 87, 56, 88, 74, 82, 89, 3764 57, 86, 78, 74, 87, 82, 88, 14, 89, 74, 3765 82, 86, 37, 87, 29, 74, 88, 82, 89, 4, 3766 86, 74, 49, 87, 82, 88, 78, 74, 89, 82, 3767 86, 38, 87, 74, 82, 88, 42, 89, 15, 74, 3768 86, 82, 87, 30, 88, 74, 50, 89, 82, 86, 3769 78, 74, 87, 82, 88, 5, 89, 74, 82, 86, 3770 39, 87, 43, 74, 88, 82, 89, 16, 86, 74, 3771 82, 87, 51, 88, 78, 74, 89, 82, 86, 6, 3772 87, 74, 31, 88, 82, 89, 52, 74, 86, 82, 3773 87, 40, 88, 74, 82, 89, 32, 86, 78, 74, 3774 87, 82, 88, 17, 89, 74, 82, 86, 7, 87, 3775 44, 74, 88, 82, 89, 45, 86, 74, 41, 87, 3776 82, 88, 78, 74, 89, 82, 86, 10, 87, 74, 3777 82, 88, 53, 89, 33, 74, 86, 82, 87, 8, 3778 88, 74, 82, 89, 46, 86, 78, 74, 87, 82, 3779 88, 34, 89, 74, 82, 86, 11, 87, 0, 74, 3780 88, 82, 89, 26, 86, 74, 54, 87, 82, 88, 3781 78, 74, 89, 82, 86, 9, 87, 74, 55, 88, 3782 82, 89, 35, 74, 86, 82, 87, 12, 88, 74, 3783 82, 89, 47, 86, 78, 74, 87, 82, 88, 2, 3784 89, 74, 82, 86, 27, 87, 127, 74, 88, 82, 3785 89, 36, 86, 74, 13, 87, 82, 88, 78, 74, 3786 89, 82, 86, 28, 87, 74, 82, 88, 3, 89 3787 }; 3788 3789 /* OPTION_9_2, 48P 1G + 2P 50G + 8P 10G */ 3790 static int p2l_mapping_op9_2[] = { 3791 0, -1, 3792 /* TSC4L 0~5 */ 3793 2, 3, 4, 5, 3794 6, 7, 8, 9, 3795 10, 11, 12, 13, 3796 14, 15, 16, 17, 3797 -1, -1, -1, -1, 3798 -1, -1, -1, -1, 3799 /* TSC4Q 0~1 */ 3800 18, 19, 20, 21, 22, 23, 24, 25, 3801 26, 27, 28, 29, 30, 31, 32, 33, 3802 34, 35, 36, 37, 38, 39, 40, 41, 3803 42, 43, 44, 45, 46, 47, 48, 49, 3804 /* TSC 0~6*/ 3805 -1, -1, -1, -1, 3806 -1, -1, -1, -1, 3807 -1, -1, -1, -1, 3808 -1, -1, -1, -1, 3809 50, 51, 52, 53, 3810 54, -1, -1, -1, 3811 55, 56, 57, 58, 3812 /* TSCF 0*/ 3813 59, -1, 60, -1 3814 }; 3815 static int port_speed_max_op9_2[] = { 3816 0, -1, 3817 /* TSC4L 0~5 */ 3818 10, 10, 10, 10, 3819 10, 10, 10, 10, 3820 10, 10, 10, 10, 3821 10, 10, 10, 10, 3822 -1, -1, -1, -1, 3823 -1, -1, -1, -1, 3824 /* TSC4Q 0~1 */ 3825 10, 10, 10, 10, 10, 10, 10, 10, 3826 10, 10, 10, 10, 10, 10, 10, 10, 3827 10, 10, 10, 10, 10, 10, 10, 10, 3828 10, 10, 10, 10, 10, 10, 10, 10, 3829 /* TSC 0~6*/ 3830 -1, -1, -1, -1, 3831 -1, -1, -1, -1, 3832 -1, -1, -1, -1, 3833 -1, -1, -1, -1, 3834 110, 110, 110, 110, 3835 100, -1, -1, -1, 3836 110, 110, 110, 110, 3837 /* TSCF 0*/ 3838 530, -1, 530, -1 3839 }; 3840 uint32 tdm_table_op9_2[240] = { 3841 15, 88, 77, 86, 75, 88, 83, 78, 86, 54, 3842 88, 85, 34, 86, 76, 88, 74, 86, 82, 43, 3843 88, 27, 86, 84, 8, 88, 77, 86, 75, 88, 3844 83, 78, 86, 16, 88, 85, 55, 86, 76, 88, 3845 74, 86, 82, 35, 88, 44, 86, 84, 9, 88, 3846 77, 86, 75, 88, 83, 78, 86, 28, 88, 85, 3847 56, 86, 76, 88, 74, 86, 82, 17, 88, 45, 3848 86, 84, 36, 88, 77, 86, 75, 88, 83, 78, 3849 86, 57, 88, 85, 2, 86, 76, 88, 74, 86, 3850 82, 10, 88, 29, 86, 84, 37, 88, 77, 86, 3851 75, 88, 83, 78, 86, 46, 88, 85, 3, 86, 3852 76, 88, 74, 86, 82, 50, 88, 30, 86, 84, 3853 11, 88, 77, 86, 75, 88, 83, 78, 86, 47, 3854 88, 85, 38, 86, 76, 88, 74, 86, 82, 51, 3855 88, 12, 86, 84, 4, 88, 77, 86, 75, 88, 3856 83, 78, 86, 31, 88, 85, 0, 86, 76, 88, 3857 74, 86, 82, 39, 88, 48, 86, 84, 5, 88, 3858 77, 86, 75, 88, 83, 78, 86, 32, 88, 85, 3859 13, 86, 76, 88, 74, 86, 82, 52, 88, 49, 3860 86, 84, 40, 88, 77, 86, 75, 88, 83, 78, 3861 86, 33, 88, 85, 6, 86, 76, 88, 74, 86, 3862 82, 14, 88, 53, 86, 84, 41, 88, 77, 86, 3863 75, 88, 83, 78, 86, 42, 88, 85, 127, 86, 3864 76, 88, 74, 86, 82, 7, 88, 26, 86, 84 3865 }; 3866 3867 /* OPTION_9_3, 48P 1G + 2P 50G + 2P 40G */ 3868 static int p2l_mapping_op9_3[] = { 3869 0, -1, 3870 /* TSC4L 0~5 */ 3871 2, 3, 4, 5, 3872 6, 7, 8, 9, 3873 10, 11, 12, 13, 3874 14, 15, 16, 17, 3875 -1, -1, -1, -1, 3876 -1, -1, -1, -1, 3877 /* TSC4Q 0~1 */ 3878 18, 19, 20, 21, 22, 23, 24, 25, 3879 26, 27, 28, 29, 30, 31, 32, 33, 3880 34, 35, 36, 37, 38, 39, 40, 41, 3881 42, 43, 44, 45, 46, 47, 48, 49, 3882 /* TSC 0~6*/ 3883 -1, -1, -1, -1, 3884 -1, -1, -1, -1, 3885 -1, -1, -1, -1, 3886 -1, -1, -1, -1, 3887 50, -1, -1, -1, 3888 51, -1, -1, -1, 3889 52, -1, -1, -1, 3890 /* TSCF 0*/ 3891 53, -1, 54, -1 3892 }; 3893 static int port_speed_max_op9_3[] = { 3894 0, -1, 3895 /* TSC4L 0~5 */ 3896 10, 10, 10, 10, 3897 10, 10, 10, 10, 3898 10, 10, 10, 10, 3899 10, 10, 10, 10, 3900 -1, -1, -1, -1, 3901 -1, -1, -1, -1, 3902 /* TSC4Q 0~1 */ 3903 10, 10, 10, 10, 10, 10, 10, 10, 3904 10, 10, 10, 10, 10, 10, 10, 10, 3905 10, 10, 10, 10, 10, 10, 10, 10, 3906 10, 10, 10, 10, 10, 10, 10, 10, 3907 /* TSC 0~6*/ 3908 -1, -1, -1, -1, 3909 -1, -1, -1, -1, 3910 -1, -1, -1, -1, 3911 -1, -1, -1, -1, 3912 420, -1, -1, -1, 3913 100, -1, -1, -1, 3914 420, -1, -1, -1, 3915 /* TSCF 0*/ 3916 530, -1, 530, -1 3917 }; 3918 uint32 tdm_table_op9_3[240] = { 3919 42, 54, 88, 82, 86, 74, 9, 88, 82, 86, 3920 55, 88, 74, 78, 86, 82, 88, 74, 14, 86, 3921 82, 88, 74, 86, 27, 39, 88, 82, 86, 74, 3922 43, 88, 82, 86, 74, 88, 78, 2, 86, 82, 3923 88, 74, 56, 86, 82, 88, 74, 86, 15, 44, 3924 88, 82, 86, 74, 28, 88, 82, 86, 74, 88, 3925 78, 40, 86, 82, 88, 74, 3, 86, 82, 88, 3926 0, 86, 74, 57, 88, 82, 86, 74, 16, 88, 3927 82, 86, 78, 88, 74, 82, 86, 29, 88, 74, 3928 41, 86, 82, 88, 45, 86, 74, 4, 88, 82, 3929 86, 74, 17, 88, 82, 86, 74, 88, 78, 82, 3930 86, 34, 88, 74, 30, 86, 82, 88, 46, 86, 3931 74, 50, 88, 82, 86, 74, 5, 88, 82, 86, 3932 35, 88, 74, 82, 86, 78, 88, 74, 10, 86, 3933 82, 88, 31, 86, 74, 82, 88, 127, 86, 74, 3934 47, 88, 82, 86, 78, 88, 74, 6, 86, 82, 3935 88, 74, 51, 86, 82, 88, 74, 86, 11, 36, 3936 88, 82, 86, 74, 32, 88, 82, 86, 74, 88, 3937 78, 48, 86, 82, 88, 74, 52, 86, 82, 88, 3938 74, 86, 7, 33, 88, 82, 86, 74, 12, 88, 3939 82, 86, 78, 88, 74, 37, 86, 82, 88, 74, 3940 49, 86, 82, 88, 53, 86, 74, 8, 88, 82, 3941 86, 74, 38, 88, 82, 86, 13, 88, 74, 78, 3942 86, 82, 88, 74, 26, 86, 82, 88, 74, 86 3943 }; 3944 3945 /* OPTION_10_0, 16P 1G (SGMII) + 16P 1G (QSGMII) + 4P 25G + 8P 10G */ 3946 static int p2l_mapping_op10_0[] = { 3947 0, -1, 3948 /* TSC4L 0~5 */ 3949 2, 3, 4, 5, 3950 6, 7, 8, 9, 3951 10, 11, 12, 13, 3952 14, 15, 16, 17, 3953 -1, -1, -1, -1, 3954 -1, -1, -1, -1, 3955 /* TSC4Q 0~1 */ 3956 18, 19, 20, 21, 22, 23, 24, 25, 3957 26, 27, 28, 29, 30, 31, 32, 33, 3958 -1, -1, -1, -1, -1, -1, -1, -1, 3959 -1, -1, -1, -1, -1, -1, -1, -1, 3960 /* TSC 0~6*/ 3961 -1, -1, -1, -1, 3962 -1, -1, -1, -1, 3963 -1, -1, -1, -1, 3964 -1, -1, -1, -1, 3965 34, 35, 36, 37, 3966 38, -1, -1, -1, 3967 39, 40, 41, 42, 3968 /* TSCF 0*/ 3969 43, 44, 45, 46 3970 }; 3971 static int port_speed_max_op10_0[] = { 3972 0, -1, 3973 /* TSC4L 0~5 */ 3974 10, 10, 10, 10, 3975 10, 10, 10, 10, 3976 10, 10, 10, 10, 3977 10, 10, 10, 10, 3978 -1, -1, -1, -1, 3979 -1, -1, -1, -1, 3980 /* TSC4Q 0~1 */ 3981 10, 10, 10, 10, 10, 10, 10, 10, 3982 10, 10, 10, 10, 10, 10, 10, 10, 3983 -1, -1, -1, -1, -1, -1, -1, -1, 3984 -1, -1, -1, -1, -1, -1, -1, -1, 3985 /* TSC 0~6*/ 3986 -1, -1, -1, -1, 3987 -1, -1, -1, -1, 3988 -1, -1, -1, -1, 3989 -1, -1, -1, -1, 3990 110, 110, 110, 110, 3991 100, -1, -1, -1, 3992 110, 110, 110, 110, 3993 /* TSCF 0*/ 3994 250, 250, 250, 250 3995 }; 3996 uint32 tdm_table_op10_0[224] = { 3997 89, 85, 26, 86, 77, 87, 39, 88, 75, 89, 3998 40, 83, 86, 84, 87, 76, 88, 78, 89, 74, 3999 9, 86, 82, 87, 85, 88, 77, 89, 10, 86, 4000 27, 75, 87, 83, 88, 84, 89, 76, 86, 78, 4001 2, 87, 74, 88, 82, 89, 85, 86, 41, 77, 4002 87, 11, 88, 75, 89, 83, 86, 84, 28, 87, 4003 76, 88, 78, 89, 74, 86, 34, 82, 87, 85, 4004 88, 77, 89, 3, 86, 75, 29, 87, 83, 88, 4005 84, 89, 76, 86, 78, 87, 12, 74, 88, 82, 4006 89, 85, 86, 77, 87, 35, 4, 88, 75, 89, 4007 83, 86, 84, 87, 13, 76, 88, 78, 89, 74, 4008 86, 82, 87, 85, 30, 88, 77, 89, 36, 86, 4009 75, 87, 5, 83, 88, 84, 89, 76, 86, 78, 4010 87, 74, 37, 88, 82, 89, 85, 86, 77, 87, 4011 14, 88, 31, 75, 89, 83, 86, 84, 87, 76, 4012 88, 78, 6, 89, 74, 86, 82, 87, 85, 88, 4013 0, 77, 89, 127, 86, 75, 87, 83, 88, 84, 4014 15, 89, 76, 86, 78, 87, 74, 88, 32, 82, 4015 89, 85, 86, 77, 87, 7, 88, 75, 38, 89, 4016 83, 86, 84, 87, 76, 88, 78, 89, 16, 74, 4017 86, 82, 87, 85, 88, 77, 89, 33, 8, 86, 4018 75, 87, 83, 88, 84, 89, 17, 76, 86, 78, 4019 87, 74, 88, 82 4020 }; 4021 4022 /* OPTION_10_1, 16P 1G (SGMII) + 16P 1G (QSGMII) + 4P 25G + 2P 40G */ 4023 static int p2l_mapping_op10_1[] = { 4024 0, -1, 4025 /* TSC4L 0~5 */ 4026 2, 3, 4, 5, 4027 6, 7, 8, 9, 4028 10, 11, 12, 13, 4029 14, 15, 16, 17, 4030 -1, -1, -1, -1, 4031 -1, -1, -1, -1, 4032 /* TSC4Q 0~1 */ 4033 18, 19, 20, 21, 22, 23, 24, 25, 4034 26, 27, 28, 29, 30, 31, 32, 33, 4035 -1, -1, -1, -1, -1, -1, -1, -1, 4036 -1, -1, -1, -1, -1, -1, -1, -1, 4037 /* TSC 0~6*/ 4038 -1, -1, -1, -1, 4039 -1, -1, -1, -1, 4040 -1, -1, -1, -1, 4041 -1, -1, -1, -1, 4042 34, -1, -1, -1, 4043 35, -1, -1, -1, 4044 36, -1, -1, -1, 4045 /* TSCF 0*/ 4046 37, 38, 39, 40 4047 }; 4048 static int port_speed_max_op10_1[] = { 4049 0, -1, 4050 /* TSC4L 0~5 */ 4051 10, 10, 10, 10, 4052 10, 10, 10, 10, 4053 10, 10, 10, 10, 4054 10, 10, 10, 10, 4055 -1, -1, -1, -1, 4056 -1, -1, -1, -1, 4057 /* TSC4Q 0~1 */ 4058 10, 10, 10, 10, 10, 10, 10, 10, 4059 10, 10, 10, 10, 10, 10, 10, 10, 4060 -1, -1, -1, -1, -1, -1, -1, -1, 4061 -1, -1, -1, -1, -1, -1, -1, -1, 4062 /* TSC 0~6*/ 4063 -1, -1, -1, -1, 4064 -1, -1, -1, -1, 4065 -1, -1, -1, -1, 4066 -1, -1, -1, -1, 4067 420, -1, -1, -1, 4068 100, -1, -1, -1, 4069 420, -1, -1, -1, 4070 /* TSCF 0*/ 4071 250, 250, 250, 250 4072 }; 4073 uint32 tdm_table_op10_1[224] = { 4074 74, 4, 88, 82, 89, 74, 86, 82, 87, 78, 4075 74, 88, 82, 89, 34, 86, 74, 87, 82, 28, 4076 88, 74, 89, 35, 86, 82, 87, 17, 74, 88, 4077 82, 89, 74, 86, 78, 87, 82, 5, 88, 74, 4078 89, 82, 86, 74, 87, 0, 82, 88, 29, 89, 4079 74, 86, 82, 87, 78, 88, 74, 82, 89, 127, 4080 86, 74, 87, 82, 88, 6, 10, 89, 74, 86, 4081 82, 87, 74, 88, 82, 30, 89, 74, 86, 78, 4082 87, 82, 88, 36, 74, 89, 82, 86, 74, 87, 4083 82, 88, 38, 7, 89, 74, 86, 82, 87, 11, 4084 88, 74, 82, 89, 78, 86, 74, 87, 82, 88, 4085 31, 89, 74, 12, 86, 82, 87, 74, 88, 82, 4086 89, 8, 74, 86, 82, 87, 78, 88, 74, 89, 4087 82, 32, 86, 74, 87, 37, 88, 82, 89, 13, 4088 74, 86, 82, 87, 74, 88, 78, 89, 82, 9, 4089 86, 74, 87, 82, 88, 74, 89, 39, 82, 86, 4090 33, 87, 74, 88, 82, 89, 40, 86, 74, 82, 4091 87, 78, 88, 74, 89, 82, 86, 2, 74, 87, 4092 82, 88, 14, 89, 74, 86, 82, 26, 87, 74, 4093 88, 78, 89, 82, 86, 41, 74, 87, 82, 88, 4094 15, 89, 74, 86, 82, 3, 87, 74, 88, 82, 4095 89, 74, 86, 78, 82, 87, 27, 88, 74, 89, 4096 82, 86, 16, 87 4097 }; 4098 4099 /* OPTION_10_2, 16P 1G (SGMII) + 16P 1G (QSGMII) + 2P 50G + 8P 10G */ 4100 static int p2l_mapping_op10_2[] = { 4101 0, -1, 4102 /* TSC4L 0~5 */ 4103 2, 3, 4, 5, 4104 6, 7, 8, 9, 4105 10, 11, 12, 13, 4106 14, 15, 16, 17, 4107 -1, -1, -1, -1, 4108 -1, -1, -1, -1, 4109 /* TSC4Q 0~1 */ 4110 18, 19, 20, 21, 22, 23, 24, 25, 4111 26, 27, 28, 29, 30, 31, 32, 33, 4112 -1, -1, -1, -1, -1, -1, -1, -1, 4113 -1, -1, -1, -1, -1, -1, -1, -1, 4114 /* TSC 0~6*/ 4115 -1, -1, -1, -1, 4116 -1, -1, -1, -1, 4117 -1, -1, -1, -1, 4118 -1, -1, -1, -1, 4119 34, 35, 36, 37, 4120 38, -1, -1, -1, 4121 39, 40, 41, 42, 4122 /* TSCF 0*/ 4123 43, -1, 44, -1 4124 }; 4125 static int port_speed_max_op10_2[] = { 4126 0, -1, 4127 /* TSC4L 0~5 */ 4128 10, 10, 10, 10, 4129 10, 10, 10, 10, 4130 10, 10, 10, 10, 4131 10, 10, 10, 10, 4132 -1, -1, -1, -1, 4133 -1, -1, -1, -1, 4134 /* TSC4Q 0~1 */ 4135 10, 10, 10, 10, 10, 10, 10, 10, 4136 10, 10, 10, 10, 10, 10, 10, 10, 4137 -1, -1, -1, -1, -1, -1, -1, -1, 4138 -1, -1, -1, -1, -1, -1, -1, -1, 4139 /* TSC 0~6*/ 4140 -1, -1, -1, -1, 4141 -1, -1, -1, -1, 4142 -1, -1, -1, -1, 4143 -1, -1, -1, -1, 4144 110, 110, 110, 110, 4145 100, -1, -1, -1, 4146 110, 110, 110, 110, 4147 /* TSCF 0*/ 4148 530, -1, 530, -1 4149 }; 4150 uint32 tdm_table_op10_2[224] = { 4151 84, 88, 74, 86, 40, 88, 82, 30, 86, 76, 4152 88, 85, 86, 75, 88, 78, 41, 86, 83, 88, 4153 77, 86, 84, 88, 7, 74, 86, 13, 88, 82, 4154 86, 76, 88, 85, 31, 86, 75, 88, 78, 86, 4155 83, 88, 77, 86, 34, 84, 88, 74, 86, 14, 4156 88, 82, 86, 76, 8, 88, 85, 86, 75, 88, 4157 78, 86, 83, 32, 88, 77, 86, 84, 88, 74, 4158 86, 127, 15, 88, 82, 86, 76, 88, 85, 86, 4159 35, 75, 88, 78, 86, 83, 88, 77, 86, 84, 4160 9, 88, 74, 86, 33, 88, 82, 86, 76, 88, 4161 36, 85, 86, 75, 88, 78, 86, 83, 88, 77, 4162 2, 86, 84, 88, 74, 86, 16, 88, 82, 26, 4163 86, 76, 88, 85, 86, 75, 88, 78, 17, 86, 4164 83, 88, 77, 86, 84, 88, 3, 74, 86, 37, 4165 88, 82, 86, 76, 88, 85, 38, 86, 75, 88, 4166 78, 86, 83, 88, 77, 86, 27, 84, 88, 74, 4167 86, 10, 88, 82, 86, 76, 4, 88, 85, 86, 4168 75, 88, 78, 86, 83, 28, 88, 77, 86, 84, 4169 88, 74, 86, 0, 11, 88, 82, 86, 76, 88, 4170 85, 86, 29, 75, 88, 78, 86, 83, 88, 77, 4171 86, 84, 5, 88, 74, 86, 39, 88, 82, 86, 4172 76, 88, 12, 85, 86, 75, 88, 78, 86, 83, 4173 88, 77, 6, 86 4174 }; 4175 4176 /* OPTION_10_3, 16P 1G (SGMII) + 16P 1G (QSGMII) + 2P 50G + 2P 40G */ 4177 static int p2l_mapping_op10_3[] = { 4178 0, -1, 4179 /* TSC4L 0~5 */ 4180 2, 3, 4, 5, 4181 6, 7, 8, 9, 4182 10, 11, 12, 13, 4183 14, 15, 16, 17, 4184 -1, -1, -1, -1, 4185 -1, -1, -1, -1, 4186 /* TSC4Q 0~1 */ 4187 18, 19, 20, 21, 22, 23, 24, 25, 4188 26, 27, 28, 29, 30, 31, 32, 33, 4189 -1, -1, -1, -1, -1, -1, -1, -1, 4190 -1, -1, -1, -1, -1, -1, -1, -1, 4191 /* TSC 0~6*/ 4192 -1, -1, -1, -1, 4193 -1, -1, -1, -1, 4194 -1, -1, -1, -1, 4195 -1, -1, -1, -1, 4196 34, -1, -1, -1, 4197 35, -1, -1, -1, 4198 36, -1, -1, -1, 4199 /* TSCF 0*/ 4200 37, -1, 38, -1 4201 }; 4202 static int port_speed_max_op10_3[] = { 4203 0, -1, 4204 /* TSC4L 0~5 */ 4205 10, 10, 10, 10, 4206 10, 10, 10, 10, 4207 10, 10, 10, 10, 4208 10, 10, 10, 10, 4209 -1, -1, -1, -1, 4210 -1, -1, -1, -1, 4211 /* TSC4Q 0~1 */ 4212 10, 10, 10, 10, 10, 10, 10, 10, 4213 10, 10, 10, 10, 10, 10, 10, 10, 4214 -1, -1, -1, -1, -1, -1, -1, -1, 4215 -1, -1, -1, -1, -1, -1, -1, -1, 4216 /* TSC 0~6*/ 4217 -1, -1, -1, -1, 4218 -1, -1, -1, -1, 4219 -1, -1, -1, -1, 4220 -1, -1, -1, -1, 4221 420, -1, -1, -1, 4222 100, -1, -1, -1, 4223 420, -1, -1, -1, 4224 /* TSCF 0*/ 4225 530, -1, 530, -1 4226 }; 4227 uint32 tdm_table_op10_3[224] = { 4228 0, 86, 74, 88, 82, 86, 74, 38, 88, 82, 4229 86, 78, 88, 74, 86, 82, 5, 88, 74, 86, 4230 82, 88, 74, 86, 31, 82, 88, 15, 86, 74, 4231 88, 82, 86, 78, 74, 88, 6, 86, 82, 88, 4232 74, 86, 82, 32, 88, 16, 86, 74, 88, 82, 4233 86, 74, 88, 82, 78, 86, 74, 88, 37, 86, 4234 82, 88, 74, 127, 86, 82, 88, 74, 86, 7, 4235 88, 82, 17, 86, 74, 88, 82, 86, 74, 88, 4236 78, 82, 86, 33, 88, 74, 86, 82, 88, 8, 4237 74, 86, 82, 88, 39, 86, 74, 88, 82, 26, 4238 86, 78, 88, 74, 86, 82, 88, 74, 86, 82, 4239 10, 88, 74, 86, 40, 88, 82, 86, 74, 9, 4240 88, 82, 86, 74, 88, 82, 86, 78, 27, 88, 4241 74, 86, 82, 88, 74, 86, 11, 82, 88, 41, 4242 86, 74, 88, 82, 86, 78, 74, 88, 2, 86, 4243 82, 88, 74, 86, 82, 28, 88, 74, 86, 34, 4244 88, 82, 86, 74, 88, 82, 12, 86, 78, 88, 4245 74, 86, 82, 88, 74, 3, 86, 82, 88, 74, 4246 86, 35, 88, 82, 29, 86, 74, 88, 82, 86, 4247 78, 88, 74, 82, 86, 13, 88, 74, 86, 82, 4248 88, 36, 74, 86, 82, 88, 4, 86, 74, 88, 4249 82, 30, 86, 78, 88, 74, 86, 82, 88, 74, 4250 86, 82, 14, 88 4251 }; 4252 4253 /* OPTION_11_0, 32P 1G (QSGMII)+ 4P 25G + 8P 10G */ 4254 static int p2l_mapping_op11_0[] = { 4255 0, -1, 4256 /* TSC4L 0~5 */ 4257 -1, -1, -1, -1, 4258 -1, -1, -1, -1, 4259 -1, -1, -1, -1, 4260 -1, -1, -1, -1, 4261 -1, -1, -1, -1, 4262 -1, -1, -1, -1, 4263 /* TSC4Q 0~1 */ 4264 2, 3, 4, 5, 6, 7, 8, 9, 4265 10, 11, 12, 13, 14, 15, 16, 17, 4266 18, 19, 20, 21, 22, 23, 24, 25, 4267 26, 27, 28, 29, 30, 31, 32, 33, 4268 /* TSC 0~6*/ 4269 -1, -1, -1, -1, 4270 -1, -1, -1, -1, 4271 -1, -1, -1, -1, 4272 -1, -1, -1, -1, 4273 34, 35, 36, 37, 4274 38, -1, -1, -1, 4275 39, 40, 41, 42, 4276 /* TSCF 0*/ 4277 43, 44, 45, 46 4278 }; 4279 static int port_speed_max_op11_0[] = { 4280 0, -1, 4281 /* TSC4L 0~5 */ 4282 -1, -1, -1, -1, 4283 -1, -1, -1, -1, 4284 -1, -1, -1, -1, 4285 -1, -1, -1, -1, 4286 -1, -1, -1, -1, 4287 -1, -1, -1, -1, 4288 /* TSC4Q 0~1 */ 4289 10, 10, 10, 10, 10, 10, 10, 10, 4290 10, 10, 10, 10, 10, 10, 10, 10, 4291 10, 10, 10, 10, 10, 10, 10, 10, 4292 10, 10, 10, 10, 10, 10, 10, 10, 4293 /* TSC 0~6*/ 4294 -1, -1, -1, -1, 4295 -1, -1, -1, -1, 4296 -1, -1, -1, -1, 4297 -1, -1, -1, -1, 4298 110, 110, 110, 110, 4299 100, -1, -1, -1, 4300 110, 110, 110, 110, 4301 /* TSCF 0*/ 4302 250, 250, 250, 250 4303 }; 4304 uint32 tdm_table_op11_0[224] = { 4305 87, 74, 88, 76, 89, 34, 42, 86, 85, 87, 4306 83, 88, 75, 89, 77, 51, 86, 78, 87, 84, 4307 88, 82, 89, 74, 52, 86, 76, 87, 33, 88, 4308 85, 89, 83, 35, 86, 75, 87, 77, 88, 78, 4309 89, 84, 86, 43, 82, 87, 74, 88, 76, 89, 4310 0, 86, 85, 26, 87, 83, 88, 75, 89, 77, 4311 86, 36, 78, 87, 84, 88, 82, 89, 74, 86, 4312 76, 44, 87, 53, 88, 85, 89, 83, 86, 75, 4313 27, 87, 77, 88, 78, 89, 84, 86, 82, 37, 4314 87, 74, 88, 76, 89, 45, 86, 85, 87, 54, 4315 83, 88, 75, 89, 77, 86, 78, 87, 84, 28, 4316 88, 82, 89, 74, 86, 76, 87, 38, 46, 88, 4317 85, 89, 83, 86, 75, 87, 77, 55, 88, 78, 4318 89, 84, 86, 82, 87, 74, 47, 88, 76, 89, 4319 29, 86, 85, 87, 83, 39, 88, 75, 89, 77, 4320 86, 78, 87, 84, 88, 56, 82, 89, 74, 86, 4321 76, 87, 48, 88, 85, 30, 89, 83, 86, 75, 4322 87, 77, 88, 40, 78, 89, 84, 86, 82, 87, 4323 74, 88, 76, 57, 89, 49, 86, 85, 87, 83, 4324 88, 75, 41, 89, 77, 86, 78, 87, 84, 88, 4325 82, 31, 89, 74, 86, 76, 87, 127, 88, 85, 4326 89, 50, 83, 86, 75, 87, 77, 88, 78, 89, 4327 84, 32, 86, 82 4328 }; 4329 4330 /* OPTION_11_1, 32P 1G (QSGMII)+ 4P 25G + 2P 40G */ 4331 static int p2l_mapping_op11_1[] = { 4332 0, -1, 4333 /* TSC4L 0~5 */ 4334 -1, -1, -1, -1, 4335 -1, -1, -1, -1, 4336 -1, -1, -1, -1, 4337 -1, -1, -1, -1, 4338 -1, -1, -1, -1, 4339 -1, -1, -1, -1, 4340 /* TSC4Q 0~1 */ 4341 2, 3, 4, 5, 6, 7, 8, 9, 4342 10, 11, 12, 13, 14, 15, 16, 17, 4343 18, 19, 20, 21, 22, 23, 24, 25, 4344 26, 27, 28, 29, 30, 31, 32, 33, 4345 /* TSC 0~6*/ 4346 -1, -1, -1, -1, 4347 -1, -1, -1, -1, 4348 -1, -1, -1, -1, 4349 -1, -1, -1, -1, 4350 34, -1, -1, -1, 4351 35, -1, -1, -1, 4352 36, -1, -1, -1, 4353 /* TSCF 0*/ 4354 37, 38, 39, 40 4355 }; 4356 static int port_speed_max_op11_1[] = { 4357 0, -1, 4358 /* TSC4L 0~5 */ 4359 -1, -1, -1, -1, 4360 -1, -1, -1, -1, 4361 -1, -1, -1, -1, 4362 -1, -1, -1, -1, 4363 -1, -1, -1, -1, 4364 -1, -1, -1, -1, 4365 /* TSC4Q 0~1 */ 4366 10, 10, 10, 10, 10, 10, 10, 10, 4367 10, 10, 10, 10, 10, 10, 10, 10, 4368 10, 10, 10, 10, 10, 10, 10, 10, 4369 10, 10, 10, 10, 10, 10, 10, 10, 4370 /* TSC 0~6*/ 4371 -1, -1, -1, -1, 4372 -1, -1, -1, -1, 4373 -1, -1, -1, -1, 4374 -1, -1, -1, -1, 4375 420, -1, -1, -1, 4376 100, -1, -1, -1, 4377 420, -1, -1, -1, 4378 /* TSCF 0*/ 4379 250, 250, 250, 250 4380 }; 4381 uint32 tdm_table_op11_1[224] = { 4382 74, 89, 82, 86, 78, 87, 74, 88, 82, 89, 4383 34, 74, 86, 82, 87, 74, 88, 57, 89, 82, 4384 46, 86, 74, 87, 82, 88, 78, 89, 74, 28, 4385 86, 82, 87, 74, 88, 82, 89, 0, 35, 86, 4386 74, 87, 82, 88, 74, 89, 47, 82, 86, 78, 4387 87, 74, 88, 82, 89, 29, 74, 86, 82, 87, 4388 74, 88, 82, 89, 50, 86, 36, 74, 87, 82, 4389 88, 78, 89, 74, 86, 82, 48, 87, 74, 88, 4390 82, 89, 51, 86, 74, 82, 87, 30, 88, 74, 4391 89, 82, 86, 78, 37, 87, 74, 88, 82, 89, 4392 74, 86, 49, 82, 87, 74, 88, 82, 89, 52, 4393 86, 38, 74, 87, 82, 88, 74, 89, 78, 86, 4394 82, 87, 31, 74, 88, 82, 89, 127, 86, 74, 4395 87, 82, 42, 88, 74, 89, 82, 86, 78, 87, 4396 74, 53, 88, 82, 89, 74, 86, 82, 87, 32, 4397 74, 88, 39, 89, 82, 86, 74, 87, 78, 82, 4398 88, 74, 89, 82, 86, 43, 87, 54, 74, 88, 4399 82, 89, 33, 86, 74, 87, 82, 88, 40, 74, 4400 89, 82, 86, 78, 87, 74, 88, 82, 44, 89, 4401 74, 86, 82, 87, 55, 88, 74, 82, 89, 26, 4402 86, 74, 87, 82, 88, 78, 74, 89, 82, 86, 4403 41, 87, 74, 88, 56, 82, 89, 45, 86, 74, 4404 87, 82, 88, 27 4405 }; 4406 4407 /* OPTION_11_2, 32P 1G (QSGMII)+ 2P 50G + 8P 10G */ 4408 static int p2l_mapping_op11_2[] = { 4409 0, -1, 4410 /* TSC4L 0~5 */ 4411 -1, -1, -1, -1, 4412 -1, -1, -1, -1, 4413 -1, -1, -1, -1, 4414 -1, -1, -1, -1, 4415 -1, -1, -1, -1, 4416 -1, -1, -1, -1, 4417 /* TSC4Q 0~1 */ 4418 2, 3, 4, 5, 6, 7, 8, 9, 4419 10, 11, 12, 13, 14, 15, 16, 17, 4420 18, 19, 20, 21, 22, 23, 24, 25, 4421 26, 27, 28, 29, 30, 31, 32, 33, 4422 /* TSC 0~6*/ 4423 -1, -1, -1, -1, 4424 -1, -1, -1, -1, 4425 -1, -1, -1, -1, 4426 -1, -1, -1, -1, 4427 34, 35, 36, 37, 4428 38, -1, -1, -1, 4429 39, 40, 41, 42, 4430 /* TSCF 0*/ 4431 43, -1, 44, -1 4432 }; 4433 static int port_speed_max_op11_2[] = { 4434 0, -1, 4435 /* TSC4L 0~5 */ 4436 -1, -1, -1, -1, 4437 -1, -1, -1, -1, 4438 -1, -1, -1, -1, 4439 -1, -1, -1, -1, 4440 -1, -1, -1, -1, 4441 -1, -1, -1, -1, 4442 /* TSC4Q 0~1 */ 4443 10, 10, 10, 10, 10, 10, 10, 10, 4444 10, 10, 10, 10, 10, 10, 10, 10, 4445 10, 10, 10, 10, 10, 10, 10, 10, 4446 10, 10, 10, 10, 10, 10, 10, 10, 4447 /* TSC 0~6*/ 4448 -1, -1, -1, -1, 4449 -1, -1, -1, -1, 4450 -1, -1, -1, -1, 4451 -1, -1, -1, -1, 4452 110, 110, 110, 110, 4453 100, -1, -1, -1, 4454 110, 110, 110, 110, 4455 /* TSCF 0*/ 4456 530, -1, 530, -1 4457 }; 4458 uint32 tdm_table_op11_2[224] = { 4459 88, 74, 86, 0, 76, 88, 45, 86, 83, 88, 4460 84, 86, 127, 75, 88, 77, 86, 78, 88, 82, 4461 86, 85, 29, 88, 74, 86, 76, 88, 38, 86, 4462 83, 88, 84, 46, 86, 75, 88, 77, 86, 78, 4463 88, 50, 82, 86, 85, 88, 74, 86, 76, 88, 4464 30, 47, 86, 83, 88, 84, 86, 75, 88, 39, 4465 77, 86, 78, 88, 82, 86, 85, 88, 57, 74, 4466 86, 76, 88, 48, 86, 83, 88, 84, 31, 86, 4467 75, 88, 77, 86, 78, 88, 82, 86, 85, 40, 4468 88, 74, 86, 76, 88, 51, 86, 32, 83, 88, 4469 84, 86, 75, 88, 77, 86, 78, 52, 88, 82, 4470 86, 85, 88, 74, 86, 41, 76, 88, 49, 86, 4471 83, 88, 84, 86, 53, 75, 88, 77, 86, 78, 4472 88, 82, 86, 85, 33, 88, 74, 86, 76, 88, 4473 34, 86, 83, 88, 84, 42, 86, 75, 88, 77, 4474 86, 78, 88, 54, 82, 86, 85, 88, 74, 86, 4475 76, 88, 26, 43, 86, 83, 88, 84, 86, 75, 4476 88, 35, 77, 86, 78, 88, 82, 86, 85, 88, 4477 55, 74, 86, 76, 88, 36, 86, 83, 88, 84, 4478 27, 86, 75, 88, 77, 86, 78, 88, 82, 86, 4479 85, 44, 88, 74, 86, 76, 88, 56, 86, 37, 4480 83, 88, 84, 86, 75, 88, 77, 86, 78, 28, 4481 88, 82, 86, 85 4482 }; 4483 4484 /* OPTION_11_3, 32P 1G (QSGMII)+ 2P 50G + 2P 40G */ 4485 static int p2l_mapping_op11_3[] = { 4486 0, -1, 4487 /* TSC4L 0~5 */ 4488 -1, -1, -1, -1, 4489 -1, -1, -1, -1, 4490 -1, -1, -1, -1, 4491 -1, -1, -1, -1, 4492 -1, -1, -1, -1, 4493 -1, -1, -1, -1, 4494 /* TSC4Q 0~1 */ 4495 2, 3, 4, 5, 6, 7, 8, 9, 4496 10, 11, 12, 13, 14, 15, 16, 17, 4497 18, 19, 20, 21, 22, 23, 24, 25, 4498 26, 27, 28, 29, 30, 31, 32, 33, 4499 /* TSC 0~6*/ 4500 -1, -1, -1, -1, 4501 -1, -1, -1, -1, 4502 -1, -1, -1, -1, 4503 -1, -1, -1, -1, 4504 34, -1, -1, -1, 4505 35, -1, -1, -1, 4506 36, -1, -1, -1, 4507 /* TSCF 0*/ 4508 37, -1, 38, -1 4509 }; 4510 static int port_speed_max_op11_3[] = { 4511 0, -1, 4512 /* TSC4L 0~5 */ 4513 -1, -1, -1, -1, 4514 -1, -1, -1, -1, 4515 -1, -1, -1, -1, 4516 -1, -1, -1, -1, 4517 -1, -1, -1, -1, 4518 -1, -1, -1, -1, 4519 /* TSC4Q 0~1 */ 4520 10, 10, 10, 10, 10, 10, 10, 10, 4521 10, 10, 10, 10, 10, 10, 10, 10, 4522 10, 10, 10, 10, 10, 10, 10, 10, 4523 10, 10, 10, 10, 10, 10, 10, 10, 4524 /* TSC 0~6*/ 4525 -1, -1, -1, -1, 4526 -1, -1, -1, -1, 4527 -1, -1, -1, -1, 4528 -1, -1, -1, -1, 4529 420, -1, -1, -1, 4530 100, -1, -1, -1, 4531 420, -1, -1, -1, 4532 /* TSCF 0*/ 4533 530, -1, 530, -1 4534 }; 4535 uint32 tdm_table_op11_3[224] = { 4536 88, 32, 74, 86, 78, 88, 82, 86, 74, 88, 4537 82, 86, 37, 74, 88, 127, 86, 82, 88, 74, 4538 86, 42, 82, 88, 74, 86, 78, 88, 82, 86, 4539 74, 33, 88, 82, 86, 74, 88, 38, 86, 82, 4540 43, 88, 74, 86, 82, 88, 78, 86, 74, 82, 4541 88, 39, 86, 74, 88, 82, 86, 26, 74, 88, 4542 55, 86, 82, 88, 74, 86, 82, 88, 56, 74, 4543 86, 78, 88, 82, 86, 74, 88, 44, 82, 86, 4544 27, 88, 74, 86, 82, 88, 74, 40, 86, 82, 4545 88, 74, 86, 78, 88, 82, 0, 86, 74, 88, 4546 82, 86, 45, 88, 74, 82, 86, 57, 88, 74, 4547 86, 82, 88, 28, 74, 86, 78, 88, 82, 86, 4548 74, 88, 82, 86, 41, 50, 88, 74, 86, 82, 4549 88, 74, 86, 29, 82, 88, 78, 86, 74, 88, 4550 82, 86, 74, 34, 88, 82, 86, 46, 88, 74, 4551 86, 82, 51, 88, 74, 86, 82, 88, 74, 86, 4552 78, 82, 88, 47, 86, 74, 88, 82, 86, 30, 4553 74, 88, 82, 86, 35, 88, 74, 86, 82, 88, 4554 52, 78, 86, 74, 88, 82, 86, 74, 88, 48, 4555 82, 86, 74, 88, 82, 86, 53, 88, 74, 31, 4556 86, 82, 88, 78, 86, 74, 88, 82, 36, 86, 4557 74, 88, 82, 86, 74, 88, 49, 82, 86, 54, 4558 88, 74, 86, 82 4559 }; 4560 4561 /* OPTION_12_0, 8P 1G (QGMII) + 4P 10G */ 4562 static int p2l_mapping_op12_0[] = { 4563 0, -1, 4564 /* TSC4L 0~5 */ 4565 -1, -1, -1, -1, 4566 -1, -1, -1, -1, 4567 -1, -1, -1, -1, 4568 -1, -1, -1, -1, 4569 -1, -1, -1, -1, 4570 -1, -1, -1, -1, 4571 /* TSC4Q 0~1 */ 4572 2, 3, 4, 5, 6, 7, 8, 9, 4573 -1, -1, -1, -1, -1, -1, -1, -1, 4574 10, -1, -1, -1, -1, -1, -1, -1, 4575 -1, -1, -1, -1, -1, -1, -1, -1, 4576 /* TSC 0~6*/ 4577 11, 12, 13, 14, 4578 -1, -1, -1, -1, 4579 -1, -1, -1, -1, 4580 -1, -1, -1, -1, 4581 -1, -1, -1, -1, 4582 -1, -1, -1, -1, 4583 -1, -1, -1, -1, 4584 /* TSCF 0*/ 4585 -1, -1, -1, -1 4586 }; 4587 static int port_speed_max_op12_0[] = { 4588 0, -1, 4589 /* TSC4L 0~5 */ 4590 -1, -1, -1, -1, 4591 -1, -1, -1, -1, 4592 -1, -1, -1, -1, 4593 -1, -1, -1, -1, 4594 -1, -1, -1, -1, 4595 -1, -1, -1, -1, 4596 /* TSC4Q 0~1 */ 4597 10, 10, 10, 10, 10, 10, 10, 10, 4598 -1, -1, -1, -1, -1, -1, -1, -1, 4599 25, -1, -1, -1, -1, -1, -1, -1, 4600 -1, -1, -1, -1, -1, -1, -1, -1, 4601 /* TSC 0~6*/ 4602 100, 100, 100, 100, 4603 -1, -1, -1, -1, 4604 -1, -1, -1, -1, 4605 -1, -1, -1, -1, 4606 -1, -1, -1, -1, 4607 -1, -1, -1, -1, 4608 -1, -1, -1, -1, 4609 /* TSCF 0*/ 4610 -1, -1, -1, -1 4611 }; 4612 uint32 tdm_table_op12_0[32] = { 4613 27, 58, 127, 61, 28, 127, 59, 127, 29, 60, 4614 127, 58, 30, 127, 61, 0, 31, 59, 42, 60, 4615 32, 127, 58, 127, 33, 61, 127, 59, 26, 127, 4616 60, 127 4617 }; 4618 4619 4620 /* System Clock Freq (MHz) */ 4621 #define _GH2_SYSTEM_FREQ_583 (583) /* 583.4 MHz */ 4622 #define _GH2_SYSTEM_FREQ_500 (500) /* 500 MHz */ 4623 #define _GH2_SYSTEM_FREQ_450 (450) /* 450 MHz */ 4624 #define _GH2_SYSTEM_FREQ_437 (437) /* 437.5 MHz */ 4625 #define _GH2_SYSTEM_FREQ_392 (392) /* 392.9 MHz */ 4626 #define _GH2_SYSTEM_FREQ_389 (389) /* 389 MHz */ 4627 #define _GH2_SYSTEM_FREQ_375 (375) /* 375 MHz */ 4628 #define _GH2_SYSTEM_FREQ_125 (125) /* 125 MHz */ 4629 #define _GH2_53570_SYSTEM_FREQ _GH2_SYSTEM_FREQ_583 4630 4631 #define _GH2_MAX_TSC_COUNT (8) 4632 #define _GH2_MAX_QTC_COUNT (2) 4633 #define _GH2_PORT_COUNT_PER_TSC (4) 4634 #define _GH2_PORT_COUNT_PER_QTC (16) 4635 #define _GH2_TSC_TSCF0_IDX (7) 4636 4637 #define _GH2_QTC_SERDES_OVERRDE_NONE (0) 4638 #define _GH2_QTC_SERDES_OVERRDE_QSGMII (1) 4639 #define _GH2_QTC_SERDES_OVERRDE_SGMII (2) 4640 4641 #define _GH2_QTC_SERDES_DEFAULT_MODE_NONE (0) 4642 #define _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII (1) 4643 #define _GH2_QTC_SERDES_DEFAULT_MODE_SGMII (2) 4644 4645 #define _GH2_ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) 4646 4647 /* 8 TSC (TSC0~6, TSCF0) */ 4648 static const int tsc_phy_port[] = {58, 62, 66, 70, 74, 78, 82, 86}; 4649 /* 2 QTC */ 4650 static const int qtc_phy_port[] = {26, 42}; 4651 4652 #define GH2_PORT_CFG_RENEW_PHY_PORT_MIN 26 /* first physical port of QTC#0 */ 4653 #define GH2_PORT_CFG_RENEW_PHY_PORT_MAX 89 /* last physical port of TSCF */ 4654 4655 /* Option string */ 4656 #define OPTION_1 "op1" 4657 #define OPTION_2 "op2" 4658 #define OPTION_2A "op2a" 4659 #define OPTION_3A "op3a" 4660 #define OPTION_4A "op4a" 4661 #define OPTION_5 "op5" 4662 #define OPTION_6 "op6" 4663 #define OPTION_7 "op7" 4664 #define OPTION_7B "op7b" 4665 #define OPTION_8B "op8b" 4666 #define OPTION_9B "op9b" 4667 #define OPTION_10B "op10b" 4668 #define OPTION_11B "op11b" 4669 #define OPTION_12B "op12b" 4670 #define OPTION_12 "op12" 4671 #define OPTION_13 "op13" 4672 #define OPTION_14 "op14" 4673 4674 /* Below options defined in PRD 4.7*/ 4675 #define OPTION_2_0 "op2_0" 4676 #define OPTION_2_2 "op2_2" 4677 #define OPTION_2_3 "op2_3" 4678 #define OPTION_5_2 "op5_2" 4679 #define OPTION_9B_0 "op9b_0" 4680 #define OPTION_10B_0 "op10b_0" 4681 /* Below options defined in PRD 4.6*/ 4682 #define OPTION_1_0 "op1_0" 4683 #define OPTION_1_1 "op1_1" 4684 #define OPTION_1_2 "op1_2" 4685 #define OPTION_1_3 "op1_3" 4686 #define OPTION_2_1 "op2_1" 4687 #define OPTION_3_0 "op3_0" 4688 #define OPTION_3_1 "op3_1" 4689 #define OPTION_3_2 "op3_2" 4690 #define OPTION_3_3 "op3_3" 4691 #define OPTION_4_0 "op4_0" 4692 #define OPTION_4_1 "op4_1" 4693 #define OPTION_4_2 "op4_2" 4694 #define OPTION_4_3 "op4_3" 4695 #define OPTION_5_0 "op5_0" 4696 #define OPTION_5_1 "op5_1" 4697 #define OPTION_5_3 "op5_3" 4698 #define OPTION_6_0 "op6_0" 4699 #define OPTION_6_1 "op6_1" 4700 #define OPTION_6_2 "op6_2" 4701 #define OPTION_6_3 "op6_3" 4702 #define OPTION_7_0 "op7_0" 4703 #define OPTION_7_1 "op7_1" 4704 #define OPTION_7_2 "op7_2" 4705 #define OPTION_7_3 "op7_3" 4706 #define OPTION_8_0 "op8_0" 4707 #define OPTION_8_1 "op8_1" 4708 #define OPTION_8_2 "op8_2" 4709 #define OPTION_8_3 "op8_3" 4710 #define OPTION_9_0 "op9_0" 4711 #define OPTION_9_1 "op9_1" 4712 #define OPTION_9_2 "op9_2" 4713 #define OPTION_9_3 "op9_3" 4714 #define OPTION_10_0 "op10_0" 4715 #define OPTION_10_1 "op10_1" 4716 #define OPTION_10_2 "op10_2" 4717 #define OPTION_10_3 "op10_3" 4718 #define OPTION_11_0 "op11_0" 4719 #define OPTION_11_1 "op11_1" 4720 #define OPTION_11_2 "op11_2" 4721 #define OPTION_11_3 "op11_3" 4722 #define OPTION_12_0 "op12_0" 4723 #define OPTION_13_0 "op13_0" 4724 4725 static int matched_option_idx = -1; 4726 4727 typedef struct _gh2_tsc_info_s { 4728 int port_count; 4729 uint8 valid; 4730 int phy_port_base; 4731 } _gh2_tsc_info_t; 4732 4733 typedef struct _gh2_option_info_s { 4734 char *config_op; /* option string */ 4735 int freq; 4736 int *p2l_mapping; 4737 int *speed_max; 4738 uint32 *tdm_table; 4739 int tdm_table_size; 4740 uint32 disabled_qtc_bmp; /* 2 bits: [qtc1~qtc0] */ 4741 uint32 disabled_tsc_bmp; /* 8 bits: [tscf, tsce6~tsce0] */ 4742 int default_port_ratio[_GH2_MAX_TSC_COUNT]; 4743 int num_qsgmii_supported[_GH2_MAX_QTC_COUNT]; 4744 int num_sgmii_supported[_GH2_MAX_QTC_COUNT]; 4745 int qtc_default_mode[_GH2_MAX_QTC_COUNT]; 4746 } _gh2_option_info_t; 4747 4748 _gh2_option_info_t *_gh2_option_port_config; 4749 4750 static _gh2_tsc_info_t _gh2_tsc[_GH2_MAX_TSC_COUNT]; 4751 static int _gh2_qtc_serdes_override[_GH2_MAX_QTC_COUNT]; 4752 4753 STATIC _gh2_option_info_t _gh2_b0_option_port_config[] = { 4754 /* OPTION_1 */ 4755 {OPTION_1, _GH2_SYSTEM_FREQ_583, 4756 p2l_mapping_template_op1, port_speed_max_template_op1, 4757 tdm_table_default, GH2_TDM_SLOT_MAX, 4758 0x0, 0x0, 4759 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4760 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4761 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4762 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4763 {0, 0}, {0, 0}, 4764 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4765 /* OPTION_2 */ 4766 {OPTION_2, _GH2_SYSTEM_FREQ_583, 4767 p2l_mapping_template_op2, port_speed_max_template_op2, 4768 tdm_table_default, GH2_TDM_SLOT_MAX, 4769 0x0, 0x0, 4770 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4771 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4772 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4773 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4774 {0, 0}, {0, 0}, 4775 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4776 /* OPTION_2A */ 4777 {OPTION_2A, _GH2_SYSTEM_FREQ_583, 4778 p2l_mapping_template_op2a, port_speed_max_template_op2a, 4779 tdm_table_default, GH2_TDM_SLOT_MAX, 4780 0x0, 0x0, 4781 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4782 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4783 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4784 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4785 {0, 0}, {0, 0}, 4786 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4787 /* OPTION_3A */ 4788 {OPTION_3A, _GH2_SYSTEM_FREQ_583, 4789 p2l_mapping_template_op3a, port_speed_max_template_op3a, 4790 tdm_table_default, GH2_TDM_SLOT_MAX, 4791 0x0, 0x0, 4792 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4793 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4794 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4795 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4796 {4, 4}, {4, 4}, 4797 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 4798 /* OPTION_4A */ 4799 {OPTION_4A, _GH2_SYSTEM_FREQ_583, 4800 p2l_mapping_template_op4a, port_speed_max_template_op4a, 4801 tdm_table_default, GH2_TDM_SLOT_MAX, 4802 0x0, 0x0, 4803 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4804 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4805 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4806 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4807 {0, 0}, {4, 4}, 4808 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 4809 /* OPTION_5 */ 4810 {OPTION_5, _GH2_SYSTEM_FREQ_500, 4811 p2l_mapping_template_op5, port_speed_max_template_op5, 4812 tdm_table_default, GH2_TDM_SLOT_MAX, 4813 0x0, 0x0, 4814 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4815 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4816 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4817 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4818 {0, 0}, {4, 4}, 4819 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 4820 /* OPTION_6 */ 4821 {OPTION_6, _GH2_SYSTEM_FREQ_392, 4822 p2l_mapping_template_op6, port_speed_max_template_op6, 4823 tdm_table_default, GH2_TDM_SLOT_MAX, 4824 0x0, 0x0, 4825 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4826 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4827 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4828 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4829 {4, 4}, {4, 4}, 4830 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 4831 /* OPTION_7 */ 4832 {OPTION_7, _GH2_SYSTEM_FREQ_500, 4833 p2l_mapping_template_op7, port_speed_max_template_op7, 4834 tdm_table_default, GH2_TDM_SLOT_MAX, 4835 0x0, 0x0, 4836 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4837 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4838 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4839 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4840 {0, 0}, {0, 0}, 4841 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4842 /* OPTION_7B */ 4843 {OPTION_7B, _GH2_SYSTEM_FREQ_500, 4844 p2l_mapping_template_op7b, port_speed_max_template_op7b, 4845 tdm_table_default, GH2_TDM_SLOT_MAX, 4846 0x0, 0x0, 4847 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4848 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4849 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4850 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4851 {0, 0}, {0, 0}, 4852 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4853 /* OPTION_8B */ 4854 {OPTION_8B, _GH2_SYSTEM_FREQ_500, 4855 p2l_mapping_template_op8b, port_speed_max_template_op8b, 4856 tdm_table_default, GH2_TDM_SLOT_MAX, 4857 0x0, 0x0, 4858 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4859 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4860 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4861 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4862 {0, 0}, {4, 4}, 4863 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 4864 /* OPTION_9B */ 4865 {OPTION_9B, _GH2_SYSTEM_FREQ_450, 4866 p2l_mapping_template_op9b, port_speed_max_template_op9b, 4867 tdm_table_default, GH2_TDM_SLOT_MAX, 4868 0x0, 0x0, 4869 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4870 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4871 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4872 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4873 {4, 4}, {4, 4}, 4874 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 4875 /* OPTION_10B */ 4876 {OPTION_10B, _GH2_SYSTEM_FREQ_450, 4877 p2l_mapping_template_op10b, port_speed_max_template_op10b, 4878 tdm_table_default, GH2_TDM_SLOT_MAX, 4879 0x0, 0x0, 4880 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4881 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4882 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4883 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4884 {0, 0}, {4, 4}, 4885 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 4886 /* OPTION_11B */ 4887 {OPTION_11B, _GH2_SYSTEM_FREQ_450, 4888 p2l_mapping_template_op11b, port_speed_max_template_op11b, 4889 tdm_table_default, GH2_TDM_SLOT_MAX, 4890 0x0, 0x0, 4891 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4892 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4893 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4894 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4895 {4, 4}, {4, 4}, 4896 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 4897 /* OPTION_12B */ 4898 {OPTION_12B, _GH2_SYSTEM_FREQ_392, 4899 p2l_mapping_template_op12b, port_speed_max_template_op12b, 4900 tdm_table_default, GH2_TDM_SLOT_MAX, 4901 0x0, 0x0, 4902 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4903 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4904 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4905 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4906 {0, 0}, {0, 0}, 4907 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4908 /* OPTION_12 */ 4909 {OPTION_12, _GH2_SYSTEM_FREQ_392, 4910 p2l_mapping_template_op12, port_speed_max_template_op12, 4911 tdm_table_default, GH2_TDM_SLOT_MAX, 4912 0x0, 0x0, 4913 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4914 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4915 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4916 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4917 {0, 0}, {0, 0}, 4918 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4919 /* OPTION_13 */ 4920 {OPTION_13, _GH2_SYSTEM_FREQ_125, 4921 p2l_mapping_template_op13, port_speed_max_template_op13, 4922 tdm_table_default, GH2_TDM_SLOT_MAX, 4923 0x0, 0x0, 4924 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4925 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4926 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4927 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4928 {0, 0}, {0, 0}, 4929 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4930 /* OPTION_14 */ 4931 {OPTION_14, _GH2_SYSTEM_FREQ_392, 4932 p2l_mapping_template_op14, port_speed_max_template_op14, 4933 tdm_table_default, GH2_TDM_SLOT_MAX, 4934 0x0, 0x0, 4935 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4936 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4937 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4938 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4939 {0, 0}, {0, 0}, 4940 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4941 {NULL, 0, 4942 0, 0, 4943 0, 0, 4944 0, 0, 4945 {-1, -1, -1, -1, -1, -1, -1, -1}, 4946 {0, 0}, {0, 0}, 4947 {0, 0}}, 4948 }; 4949 4950 STATIC _gh2_option_info_t _gh2_a0_option_port_config[] = { 4951 /* Below options defined in PRD 4.7*/ 4952 /* OPTION_2_0, 24P*2.5G + 32P*10G */ 4953 {OPTION_2_0, _GH2_SYSTEM_FREQ_583, 4954 p2l_mapping_op2_0, port_speed_max_op2_0, 4955 tdm_table_op2_0, _GH2_ARRAY_SIZE(tdm_table_op2_0), 4956 0x0, 0x0, 4957 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4958 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4959 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4960 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 4961 {0, 0}, {0, 0}, 4962 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4963 /* OPTION_2_2, 24*2.5G + 16*10G + 4*40G */ 4964 {OPTION_2_2, _GH2_SYSTEM_FREQ_583, 4965 p2l_mapping_op2_2, port_speed_max_op2_2, 4966 tdm_table_op2_2, _GH2_ARRAY_SIZE(tdm_table_op2_2), 4967 0x0, 0x0, 4968 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4969 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4970 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 4971 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE}, 4972 {0, 0}, {0, 0}, 4973 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4974 /* OPTION_2_3, 24*2.5G + 24*10G + 2*40G */ 4975 {OPTION_2_3, _GH2_SYSTEM_FREQ_583, 4976 p2l_mapping_op2_3, port_speed_max_op2_3, 4977 tdm_table_op2_3, _GH2_ARRAY_SIZE(tdm_table_op2_3), 4978 0x0, 0x0, 4979 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4980 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4981 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4982 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE}, 4983 {0, 0}, {0, 0}, 4984 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 4985 /* OPTION_5_2, 52*2.5G + 8*10G + 2*50G */ 4986 {OPTION_5_2, _GH2_SYSTEM_FREQ_500, 4987 p2l_mapping_op5_2, port_speed_max_op5_2, 4988 tdm_table_op5_2, _GH2_ARRAY_SIZE(tdm_table_op5_2), 4989 0x0, 0x0, 4990 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4991 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4992 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 4993 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 4994 {4, 4}, {4, 4}, 4995 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 4996 /* OPTION_9B_0, 48*1G + 40G RioT + 8*10G + 4*25G */ 4997 {OPTION_9B_0, _GH2_SYSTEM_FREQ_450, 4998 p2l_mapping_op9b_0, port_speed_max_op9b_0, 4999 tdm_table_op9b_0, _GH2_ARRAY_SIZE(tdm_table_op9b_0), 5000 0x0, 0x0, 5001 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5002 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_SINGLE, 5003 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_SINGLE, 5004 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5005 {4, 4}, {4, 4}, 5006 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5007 /* OPTION_10B_0, 32*1G + 40G RioT + 8*10G + 4*25G */ 5008 {OPTION_10B_0, _GH2_SYSTEM_FREQ_450, 5009 p2l_mapping_op10b_0, port_speed_max_op10b_0, 5010 tdm_table_op10b_0, _GH2_ARRAY_SIZE(tdm_table_op10b_0), 5011 0x0, 0x0, 5012 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5013 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5014 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5015 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5016 {4, 4}, {4, 4}, 5017 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5018 /* OPTION_13_0, 24P 1G + 4P 10G + XAUI*/ 5019 {OPTION_13_0, _GH2_SYSTEM_FREQ_125, 5020 p2l_mapping_op13_0, port_speed_max_op13_0, 5021 tdm_table_op13_0, _GH2_ARRAY_SIZE(tdm_table_op13_0), 5022 0x0, 0x0, 5023 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5024 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5025 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_SINGLE_XAUI, 5026 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5027 {0, 0}, {0, 0}, 5028 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5029 5030 /* Below options defined in PRD 4.6*/ 5031 /* OPTION_1_0, 24P 10G + 4P 10G/25G */ 5032 {OPTION_1_0, _GH2_SYSTEM_FREQ_583, 5033 p2l_mapping_op1_0, port_speed_max_op1_0, 5034 tdm_table_op1_0, _GH2_ARRAY_SIZE(tdm_table_op1_0), 5035 0x0, 0x0, 5036 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5037 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5038 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5039 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5040 {0, 0}, {0, 0}, 5041 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5042 /* OPTION_1_1, 24P 10G + 2P HG[50] */ 5043 {OPTION_1_1, _GH2_SYSTEM_FREQ_583, 5044 p2l_mapping_op1_1, port_speed_max_op1_1, 5045 tdm_table_op1_1, _GH2_ARRAY_SIZE(tdm_table_op1_1), 5046 0x0, 0x0, 5047 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5048 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5049 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5050 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5051 {0, 0}, {0, 0}, 5052 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5053 /* OPTION_1_2, 6P 40G + 4P 10G/25G */ 5054 {OPTION_1_2, _GH2_SYSTEM_FREQ_583, 5055 p2l_mapping_op1_2, port_speed_max_op1_2, 5056 tdm_table_op1_2, _GH2_ARRAY_SIZE(tdm_table_op1_2), 5057 0x0, 0x0, 5058 {SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 5059 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 5060 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5061 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5062 {0, 0}, {0, 0}, 5063 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5064 /* OPTION_1_3, 6P 40G + 2P HG[50] */ 5065 {OPTION_1_3, _GH2_SYSTEM_FREQ_583, 5066 p2l_mapping_op1_3, port_speed_max_op1_3, 5067 tdm_table_op1_3, _GH2_ARRAY_SIZE(tdm_table_op1_3), 5068 0x0, 0x0, 5069 {SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 5070 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 5071 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5072 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5073 {0, 0}, {0, 0}, 5074 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5075 /* OPTION_2_1, 12P 2.5G + 8P 40G */ 5076 {OPTION_2_1, _GH2_SYSTEM_FREQ_583, 5077 p2l_mapping_op2_1, port_speed_max_op2_1, 5078 tdm_table_op2_1, _GH2_ARRAY_SIZE(tdm_table_op2_1), 5079 0x0, 0x0, 5080 {SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 5081 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 5082 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE, 5083 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_SINGLE}, 5084 {0, 0}, {0, 0}, 5085 {_GH2_QTC_SERDES_DEFAULT_MODE_NONE, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5086 /* OPTION_3_0, 52P 2.5G + 4P 25G + 8P 10G */ 5087 {OPTION_3_0, _GH2_SYSTEM_FREQ_583, 5088 p2l_mapping_op3_0, port_speed_max_op3_0, 5089 tdm_table_op3_0, _GH2_ARRAY_SIZE(tdm_table_op3_0), 5090 0x0, 0x0, 5091 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5092 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5093 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5094 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5095 {4, 4}, {4, 4}, 5096 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5097 /* OPTION_3_1, 52P 2.5G + 4P 25G + 2P 40G */ 5098 {OPTION_3_1, _GH2_SYSTEM_FREQ_583, 5099 p2l_mapping_op3_1, port_speed_max_op3_1, 5100 tdm_table_op3_1, _GH2_ARRAY_SIZE(tdm_table_op3_1), 5101 0x0, 0x0, 5102 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5103 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5104 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5105 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5106 {4, 4}, {4, 4}, 5107 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5108 /* OPTION_3_2, 52P 2.5G + 2P 50G + 8P 10G */ 5109 {OPTION_3_2, _GH2_SYSTEM_FREQ_583, 5110 p2l_mapping_op3_2, port_speed_max_op3_2, 5111 tdm_table_op3_2, _GH2_ARRAY_SIZE(tdm_table_op3_2), 5112 0x0, 0x0, 5113 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5114 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5115 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5116 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5117 {4, 4}, {4, 4}, 5118 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5119 /* OPTION_3_3, 52P 2.5G + 2P 50G + 2P 40G */ 5120 {OPTION_3_3, _GH2_SYSTEM_FREQ_583, 5121 p2l_mapping_op3_3, port_speed_max_op3_3, 5122 tdm_table_op3_3, _GH2_ARRAY_SIZE(tdm_table_op3_3), 5123 0x0, 0x0, 5124 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5125 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5126 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5127 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5128 {4, 4}, {4, 4}, 5129 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5130 /* OPTION_4_0, 48P 2.5G + 4P 25G + 8P 10G */ 5131 {OPTION_4_0, _GH2_SYSTEM_FREQ_583, 5132 p2l_mapping_op4_0, port_speed_max_op4_0, 5133 tdm_table_op4_0, _GH2_ARRAY_SIZE(tdm_table_op4_0), 5134 0x0, 0x0, 5135 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5136 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5137 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5138 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5139 {4, 4}, {4, 4}, 5140 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5141 /* OPTION_4_1, 48P 2.5G + 4P 25G + 2P 40G */ 5142 {OPTION_4_1, _GH2_SYSTEM_FREQ_583, 5143 p2l_mapping_op4_1, port_speed_max_op4_1, 5144 tdm_table_op4_1, _GH2_ARRAY_SIZE(tdm_table_op4_1), 5145 0x0, 0x0, 5146 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5147 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5148 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5149 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5150 {4, 4}, {4, 4}, 5151 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5152 /* OPTION_4_2, 48P 2.5G + 2P 50G + 8P 10G */ 5153 {OPTION_4_2, _GH2_SYSTEM_FREQ_583, 5154 p2l_mapping_op4_2, port_speed_max_op4_2, 5155 tdm_table_op4_2, _GH2_ARRAY_SIZE(tdm_table_op4_2), 5156 0x0, 0x0, 5157 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5158 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5159 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5160 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5161 {4, 4}, {4, 4}, 5162 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5163 /* OPTION_4_3, 48P 2.5G + 2P 50G + 2P 40G */ 5164 {OPTION_4_3, _GH2_SYSTEM_FREQ_583, 5165 p2l_mapping_op4_3, port_speed_max_op4_3, 5166 tdm_table_op4_3, _GH2_ARRAY_SIZE(tdm_table_op4_3), 5167 0x0, 0x0, 5168 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5169 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5170 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5171 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5172 {4, 4}, {4, 4}, 5173 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5174 /* OPTION_5_0, 24P 2.5G + 4P 25G + 8P 10G */ 5175 {OPTION_5_0, _GH2_SYSTEM_FREQ_437, 5176 p2l_mapping_op5_0, port_speed_max_op5_0, 5177 tdm_table_op5_0, _GH2_ARRAY_SIZE(tdm_table_op5_0), 5178 0x0, 0x0, 5179 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5180 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5181 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5182 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5183 {4, 0}, {4, 0}, 5184 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5185 /* OPTION_5_1, 24P 2.5G + 4P 25G + 2P 40G */ 5186 {OPTION_5_1, _GH2_SYSTEM_FREQ_437, 5187 p2l_mapping_op5_1, port_speed_max_op5_1, 5188 tdm_table_op5_1, _GH2_ARRAY_SIZE(tdm_table_op5_1), 5189 0x0, 0x0, 5190 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5191 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5192 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5193 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5194 {4, 0}, {4, 0}, 5195 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5196 /* OPTION_5_3, 24P 2.5G + 2P 50G + 2P 40G */ 5197 {OPTION_5_3, _GH2_SYSTEM_FREQ_437, 5198 p2l_mapping_op5_3, port_speed_max_op5_3, 5199 tdm_table_op5_3, _GH2_ARRAY_SIZE(tdm_table_op5_3), 5200 0x0, 0x0, 5201 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5202 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5203 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5204 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5205 {4, 0}, {4, 0}, 5206 {_GH2_QTC_SERDES_DEFAULT_MODE_SGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5207 /* OPTION_6_0, 36P 1G + 12P 10G + 4P 25G + 8P 10G */ 5208 {OPTION_6_0, _GH2_SYSTEM_FREQ_583, 5209 p2l_mapping_op6_0, port_speed_max_op6_0, 5210 tdm_table_op6_0, _GH2_ARRAY_SIZE(tdm_table_op6_0), 5211 0x0, 0x0, 5212 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5213 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5214 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5215 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5216 {4, 4}, {4, 4}, 5217 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5218 /* OPTION_6_1, 36P 1G + 12P 10G + 4P 25G + 2P 40G */ 5219 {OPTION_6_1, _GH2_SYSTEM_FREQ_583, 5220 p2l_mapping_op6_1, port_speed_max_op6_1, 5221 tdm_table_op6_1, _GH2_ARRAY_SIZE(tdm_table_op6_1), 5222 0x0, 0x0, 5223 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5224 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5225 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5226 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5227 {4, 4}, {4, 4}, 5228 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5229 /* OPTION_6_2, 36P 1G + 12P 10G + 2P 50G + 8P 10G */ 5230 {OPTION_6_2, _GH2_SYSTEM_FREQ_583, 5231 p2l_mapping_op6_2, port_speed_max_op6_2, 5232 tdm_table_op6_2, _GH2_ARRAY_SIZE(tdm_table_op6_2), 5233 0x0, 0x0, 5234 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5235 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5236 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5237 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5238 {4, 4}, {4, 4}, 5239 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5240 /* OPTION_6_3, 36P 1G + 12P 10G + 2P 50G + 2P 40G */ 5241 {OPTION_6_3, _GH2_SYSTEM_FREQ_583, 5242 p2l_mapping_op6_3, port_speed_max_op6_3, 5243 tdm_table_op6_3, _GH2_ARRAY_SIZE(tdm_table_op6_3), 5244 0x0, 0x0, 5245 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5246 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5247 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5248 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5249 {4, 4}, {4, 4}, 5250 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5251 /* OPTION_7_0, 12P 1G + 12P 10G + 4P 25G + 8P 10G */ 5252 {OPTION_7_0, _GH2_SYSTEM_FREQ_583, 5253 p2l_mapping_op7_0, port_speed_max_op7_0, 5254 tdm_table_op7_0, _GH2_ARRAY_SIZE(tdm_table_op7_0), 5255 0x0, 0x0, 5256 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5257 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5258 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5259 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5260 {4, 0}, {0, 0}, 5261 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5262 /* OPTION_7_1, 12P 1G + 12P 10G + 4P 25G + 2P 40G */ 5263 {OPTION_7_1, _GH2_SYSTEM_FREQ_583, 5264 p2l_mapping_op7_1, port_speed_max_op7_1, 5265 tdm_table_op7_1, _GH2_ARRAY_SIZE(tdm_table_op7_1), 5266 0x0, 0x0, 5267 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5268 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5269 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5270 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5271 {4, 0}, {0, 0}, 5272 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5273 /* OPTION_7_2, 12P 1G + 12P 10G + 2P 50G + 8P 10G */ 5274 {OPTION_7_2, _GH2_SYSTEM_FREQ_583, 5275 p2l_mapping_op7_2, port_speed_max_op7_2, 5276 tdm_table_op7_2, _GH2_ARRAY_SIZE(tdm_table_op7_2), 5277 0x0, 0x0, 5278 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5279 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5280 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5281 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5282 {4, 0}, {0, 0}, 5283 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5284 /* OPTION_7_3, 12P 1G + 12P 10G + 2P 50G + 2P 40G */ 5285 {OPTION_7_3, _GH2_SYSTEM_FREQ_583, 5286 p2l_mapping_op7_3, port_speed_max_op7_3, 5287 tdm_table_op7_3, _GH2_ARRAY_SIZE(tdm_table_op7_3), 5288 0x0, 0x0, 5289 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5290 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5291 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5292 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5293 {4, 0}, {0, 0}, 5294 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5295 /* OPTION_8_0, 56P 1G + 4P 25G + 4P 10G */ 5296 {OPTION_8_0, _GH2_SYSTEM_FREQ_437, 5297 p2l_mapping_op8_0, port_speed_max_op8_0, 5298 tdm_table_op8_0, _GH2_ARRAY_SIZE(tdm_table_op8_0), 5299 0x0, 0x0, 5300 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5301 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5302 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5303 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5304 {4, 4}, {4, 4}, 5305 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5306 /* OPTION_8_1, 56P 1G + 4P 25G + 1P 40G */ 5307 {OPTION_8_1, _GH2_SYSTEM_FREQ_437, 5308 p2l_mapping_op8_1, port_speed_max_op8_1, 5309 tdm_table_op8_1, _GH2_ARRAY_SIZE(tdm_table_op8_1), 5310 0x0, 0x0, 5311 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5312 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5313 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5314 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5315 {4, 4}, {4, 4}, 5316 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5317 /* OPTION_8_2, 56P 1G + 2P 50G + 4P 10G */ 5318 {OPTION_8_2, _GH2_SYSTEM_FREQ_437, 5319 p2l_mapping_op8_2, port_speed_max_op8_2, 5320 tdm_table_op8_2, _GH2_ARRAY_SIZE(tdm_table_op8_2), 5321 0x0, 0x0, 5322 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5323 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5324 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5325 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5326 {4, 4}, {4, 4}, 5327 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5328 /* OPTION_8_3, 56P 1G + 2P 50G + 1P 40G */ 5329 {OPTION_8_3, _GH2_SYSTEM_FREQ_437, 5330 p2l_mapping_op8_3, port_speed_max_op8_3, 5331 tdm_table_op8_3, _GH2_ARRAY_SIZE(tdm_table_op8_3), 5332 0x0, 0x0, 5333 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5334 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5335 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5336 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5337 {4, 4}, {4, 4}, 5338 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5339 /* OPTION_9_0, 48P 1G + 4P 25G + 8P 10G */ 5340 {OPTION_9_0, _GH2_SYSTEM_FREQ_437, 5341 p2l_mapping_op9_0, port_speed_max_op9_0, 5342 tdm_table_op9_0, _GH2_ARRAY_SIZE(tdm_table_op9_0), 5343 0x0, 0x0, 5344 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5345 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5346 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5347 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5348 {4, 4}, {4, 4}, 5349 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5350 /* OPTION_9_1, 48P 1G + 4P 25G + 2P 40G */ 5351 {OPTION_9_1, _GH2_SYSTEM_FREQ_437, 5352 p2l_mapping_op9_1, port_speed_max_op9_1, 5353 tdm_table_op9_1, _GH2_ARRAY_SIZE(tdm_table_op9_1), 5354 0x0, 0x0, 5355 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5356 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5357 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5358 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5359 {4, 4}, {4, 4}, 5360 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5361 /* OPTION_9_2, 48P 1G + 2P 50G + 8P 10G */ 5362 {OPTION_9_2, _GH2_SYSTEM_FREQ_437, 5363 p2l_mapping_op9_2, port_speed_max_op9_2, 5364 tdm_table_op9_2, _GH2_ARRAY_SIZE(tdm_table_op9_2), 5365 0x0, 0x0, 5366 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5367 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5368 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5369 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5370 {4, 4}, {4, 4}, 5371 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5372 /* OPTION_9_3, 48P 1G + 2P 50G + 2P 40G */ 5373 {OPTION_9_3, _GH2_SYSTEM_FREQ_437, 5374 p2l_mapping_op9_3, port_speed_max_op9_3, 5375 tdm_table_op9_3, _GH2_ARRAY_SIZE(tdm_table_op9_3), 5376 0x0, 0x0, 5377 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5378 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5379 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5380 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5381 {4, 4}, {4, 4}, 5382 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5383 /* OPTION_10_0, 16P 1G (SGMII) + 16P 1G (QSGMII) + 4P 25G + 8P 10G */ 5384 {OPTION_10_0, _GH2_SYSTEM_FREQ_437, 5385 p2l_mapping_op10_0, port_speed_max_op10_0, 5386 tdm_table_op10_0, _GH2_ARRAY_SIZE(tdm_table_op10_0), 5387 0x0, 0x0, 5388 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5389 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5390 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5391 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5392 {4, 0}, {0, 0}, 5393 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5394 /* OPTION_10_1, 16P 1G (SGMII) + 16P 1G (QSGMII) + 4P 25G + 2P 40G */ 5395 {OPTION_10_1, _GH2_SYSTEM_FREQ_437, 5396 p2l_mapping_op10_1, port_speed_max_op10_1, 5397 tdm_table_op10_1, _GH2_ARRAY_SIZE(tdm_table_op10_1), 5398 0x0, 0x0, 5399 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5400 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5401 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5402 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5403 {4, 0}, {0, 0}, 5404 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5405 /* OPTION_10_2, 16P 1G (SGMII) + 16P 1G (QSGMII) + 2P 50G + 8P 10G */ 5406 {OPTION_10_2, _GH2_SYSTEM_FREQ_437, 5407 p2l_mapping_op10_2, port_speed_max_op10_2, 5408 tdm_table_op10_2, _GH2_ARRAY_SIZE(tdm_table_op10_2), 5409 0x0, 0x0, 5410 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5411 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5412 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5413 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5414 {4, 0}, {0, 0}, 5415 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5416 /* OPTION_10_3, 16P 1G (SGMII) + 16P 1G (QSGMII) + 2P 50G + 2P 40G */ 5417 {OPTION_10_3, _GH2_SYSTEM_FREQ_437, 5418 p2l_mapping_op10_3, port_speed_max_op10_3, 5419 tdm_table_op10_3, _GH2_ARRAY_SIZE(tdm_table_op10_3), 5420 0x0, 0x0, 5421 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5422 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5423 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5424 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5425 {4, 0}, {0, 0}, 5426 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_NONE}}, 5427 /* OPTION_11_0, 32P 1G (QSGMII)+ 4P 25G + 8P 10G */ 5428 {OPTION_11_0, _GH2_SYSTEM_FREQ_437, 5429 p2l_mapping_op11_0, port_speed_max_op11_0, 5430 tdm_table_op11_0, _GH2_ARRAY_SIZE(tdm_table_op11_0), 5431 0x0, 0x0, 5432 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5433 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5434 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5435 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5436 {4, 4}, {4, 4}, 5437 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5438 /* OPTION_11_1, 32P 1G (QSGMII)+ 4P 25G + 2P 40G */ 5439 {OPTION_11_1, _GH2_SYSTEM_FREQ_437, 5440 p2l_mapping_op11_1, port_speed_max_op11_1, 5441 tdm_table_op11_1, _GH2_ARRAY_SIZE(tdm_table_op11_1), 5442 0x0, 0x0, 5443 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5444 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5445 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5446 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD}, 5447 {4, 4}, {4, 4}, 5448 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5449 /* OPTION_11_2, 32P 1G (QSGMII)+ 2P 50G + 8P 10G */ 5450 {OPTION_11_2, _GH2_SYSTEM_FREQ_437, 5451 p2l_mapping_op11_2, port_speed_max_op11_2, 5452 tdm_table_op11_2, _GH2_ARRAY_SIZE(tdm_table_op11_2), 5453 0x0, 0x0, 5454 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5455 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5456 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5457 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5458 {4, 4}, {4, 4}, 5459 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5460 /* OPTION_11_3, 32P 1G (QSGMII)+ 2P 50G + 2P 40G */ 5461 {OPTION_11_3, _GH2_SYSTEM_FREQ_437, 5462 p2l_mapping_op11_3, port_speed_max_op11_3, 5463 tdm_table_op11_3, _GH2_ARRAY_SIZE(tdm_table_op11_3), 5464 0x0, 0x0, 5465 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5466 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5467 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_QUAD, 5468 SOC_GH2_PORT_RATIO_SINGLE, SOC_GH2_PORT_RATIO_DUAL_2_2}, 5469 {4, 4}, {4, 4}, 5470 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII}}, 5471 /* OPTION_12_0, 8P 1G (QGMII) + 4P 10G */ 5472 {OPTION_12_0, _GH2_SYSTEM_FREQ_125, 5473 p2l_mapping_op12_0, port_speed_max_op12_0, 5474 tdm_table_op12_0, _GH2_ARRAY_SIZE(tdm_table_op12_0), 5475 0x0, 0x0, 5476 {SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5477 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5478 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD, 5479 SOC_GH2_PORT_RATIO_QUAD, SOC_GH2_PORT_RATIO_QUAD}, 5480 {4, 4}, {4, 4}, 5481 {_GH2_QTC_SERDES_DEFAULT_MODE_QSGMII, _GH2_QTC_SERDES_DEFAULT_MODE_SGMII}}, 5482 {NULL, 0, 5483 0, 0, 5484 0, 0, 5485 0, 0, 5486 {-1, -1, -1, -1, -1, -1, -1, -1}, 5487 {0, 0}, {0, 0}, 5488 {0, 0}}, 5489 }; 5490 5491 typedef struct _gh2_sku_option_list_s { 5492 uint16 dev_id; 5493 char *option_string; /* option */ 5494 int default_option; /* 1 : the default option of the SKU */ 5495 } _gh2_sku_option_list_t; 5496 5497 _gh2_sku_option_list_t *_gh2_sku_option_support_list; 5498 5499 STATIC _gh2_sku_option_list_t _gh2_b0_sku_option_support_list[] = { 5500 {BCM56170_DEVICE_ID, OPTION_1, 1}, 5501 {BCM56170_DEVICE_ID, OPTION_2, 0}, 5502 {BCM56170_DEVICE_ID, OPTION_2A, 0}, 5503 {BCM56170_DEVICE_ID, OPTION_3A, 0}, 5504 {BCM56170_DEVICE_ID, OPTION_4A, 0}, 5505 {BCM56170_DEVICE_ID, OPTION_5, 0}, 5506 {BCM56170_DEVICE_ID, OPTION_6, 0}, 5507 {BCM56170_DEVICE_ID, OPTION_7, 0}, 5508 {BCM56170_DEVICE_ID, OPTION_7B, 0}, 5509 {BCM56170_DEVICE_ID, OPTION_8B, 0}, 5510 {BCM56170_DEVICE_ID, OPTION_9B, 0}, 5511 {BCM56170_DEVICE_ID, OPTION_10B, 0}, 5512 {BCM56170_DEVICE_ID, OPTION_11B, 0}, 5513 {BCM56170_DEVICE_ID, OPTION_12B, 0}, 5514 {BCM56170_DEVICE_ID, OPTION_12, 0}, 5515 {BCM56170_DEVICE_ID, OPTION_13, 0}, 5516 {BCM56170_DEVICE_ID, OPTION_14, 0}, 5517 {BCM56172_DEVICE_ID, OPTION_7B, 1}, 5518 {BCM56172_DEVICE_ID, OPTION_8B, 0}, 5519 {BCM56172_DEVICE_ID, OPTION_9B, 0}, 5520 {BCM56174_DEVICE_ID, OPTION_10B, 1}, 5521 {BCM56174_DEVICE_ID, OPTION_11B, 0}, 5522 {BCM56174_DEVICE_ID, OPTION_12B, 0}, 5523 {BCM56174_DEVICE_ID, OPTION_14, 0}, 5524 {BCM53570_DEVICE_ID, OPTION_1, 1}, 5525 {BCM53570_DEVICE_ID, OPTION_2, 0}, 5526 {BCM53570_DEVICE_ID, OPTION_5, 0}, 5527 {BCM53570_DEVICE_ID, OPTION_6, 0}, 5528 {BCM53570_DEVICE_ID, OPTION_7, 0}, 5529 {BCM53570_DEVICE_ID, OPTION_12, 0}, 5530 {BCM53570_DEVICE_ID, OPTION_13, 0}, 5531 {BCM53575_DEVICE_ID, OPTION_13, 1}, 5532 {0, "not existed", 0}, 5533 }; 5534 5535 STATIC _gh2_sku_option_list_t _gh2_a0_sku_option_support_list[] = { 5536 /* Below options defined in PRD 4.7*/ 5537 /* BCM56170 */ 5538 {BCM56170_DEVICE_ID, OPTION_2_0, 0}, 5539 {BCM56170_DEVICE_ID, OPTION_2_2, 1}, 5540 {BCM56170_DEVICE_ID, OPTION_2_3, 0}, 5541 {BCM56170_DEVICE_ID, OPTION_5_2, 0}, 5542 {BCM56170_DEVICE_ID, OPTION_9B_0, 0}, 5543 {BCM56170_DEVICE_ID, OPTION_10B_0, 0}, 5544 {BCM56170_DEVICE_ID, OPTION_13_0, 0}, 5545 /* BCM56172 */ 5546 {BCM56172_DEVICE_ID, OPTION_9B_0, 1}, 5547 /* BCM56174 */ 5548 {BCM56174_DEVICE_ID, OPTION_10B_0, 1}, 5549 /* BCM53570 */ 5550 {BCM53570_DEVICE_ID, OPTION_2_0, 0}, 5551 {BCM53570_DEVICE_ID, OPTION_2_2, 1}, 5552 {BCM53570_DEVICE_ID, OPTION_2_3, 0}, 5553 {BCM53570_DEVICE_ID, OPTION_5_2, 0}, 5554 {BCM53570_DEVICE_ID, OPTION_13_0, 0}, 5555 5556 /* Below options defined in PRD 4.6*/ 5557 /* BCM56170 */ 5558 {BCM56170_DEVICE_ID, OPTION_1_0, 0}, 5559 {BCM56170_DEVICE_ID, OPTION_1_1, 0}, 5560 {BCM56170_DEVICE_ID, OPTION_1_2, 0}, 5561 {BCM56170_DEVICE_ID, OPTION_1_3, 0}, 5562 {BCM56170_DEVICE_ID, OPTION_2_1, 0}, 5563 {BCM56170_DEVICE_ID, OPTION_3_0, 0}, 5564 {BCM56170_DEVICE_ID, OPTION_3_1, 0}, 5565 {BCM56170_DEVICE_ID, OPTION_3_2, 0}, 5566 {BCM56170_DEVICE_ID, OPTION_3_3, 0}, 5567 {BCM56170_DEVICE_ID, OPTION_4_0, 0}, 5568 {BCM56170_DEVICE_ID, OPTION_4_1, 0}, 5569 {BCM56170_DEVICE_ID, OPTION_4_2, 0}, 5570 {BCM56170_DEVICE_ID, OPTION_4_3, 0}, 5571 {BCM56170_DEVICE_ID, OPTION_6_0, 0}, 5572 {BCM56170_DEVICE_ID, OPTION_6_1, 0}, 5573 {BCM56170_DEVICE_ID, OPTION_6_2, 0}, 5574 {BCM56170_DEVICE_ID, OPTION_6_3, 0}, 5575 {BCM56170_DEVICE_ID, OPTION_8_0, 0}, 5576 {BCM56170_DEVICE_ID, OPTION_8_1, 0}, 5577 {BCM56170_DEVICE_ID, OPTION_8_2, 0}, 5578 {BCM56170_DEVICE_ID, OPTION_8_3, 0}, 5579 /* BCM56172 */ 5580 {BCM56172_DEVICE_ID, OPTION_5_0, 0}, 5581 {BCM56172_DEVICE_ID, OPTION_5_1, 0}, 5582 {BCM56172_DEVICE_ID, OPTION_5_3, 0}, 5583 {BCM56172_DEVICE_ID, OPTION_7_0, 0}, 5584 {BCM56172_DEVICE_ID, OPTION_7_1, 0}, 5585 {BCM56172_DEVICE_ID, OPTION_7_2, 0}, 5586 {BCM56172_DEVICE_ID, OPTION_7_3, 0}, 5587 {BCM56172_DEVICE_ID, OPTION_9_0, 0}, 5588 {BCM56172_DEVICE_ID, OPTION_9_1, 0}, 5589 {BCM56172_DEVICE_ID, OPTION_9_2, 0}, 5590 {BCM56172_DEVICE_ID, OPTION_9_3, 0}, 5591 /* BCM56174 */ 5592 {BCM56174_DEVICE_ID, OPTION_10_0, 0}, 5593 {BCM56174_DEVICE_ID, OPTION_10_1, 0}, 5594 {BCM56174_DEVICE_ID, OPTION_10_2, 0}, 5595 {BCM56174_DEVICE_ID, OPTION_10_3, 0}, 5596 {BCM56174_DEVICE_ID, OPTION_11_0, 0}, 5597 {BCM56174_DEVICE_ID, OPTION_11_1, 0}, 5598 {BCM56174_DEVICE_ID, OPTION_11_2, 0}, 5599 {BCM56174_DEVICE_ID, OPTION_11_3, 0}, 5600 /* BCM53570 */ 5601 {BCM53570_DEVICE_ID, OPTION_1_0, 0}, 5602 {BCM53570_DEVICE_ID, OPTION_1_1, 0}, 5603 {BCM53570_DEVICE_ID, OPTION_1_2, 0}, 5604 {BCM53570_DEVICE_ID, OPTION_1_3, 0}, 5605 {BCM53570_DEVICE_ID, OPTION_2_1, 0}, 5606 {BCM53570_DEVICE_ID, OPTION_3_0, 0}, 5607 {BCM53570_DEVICE_ID, OPTION_3_1, 0}, 5608 {BCM53570_DEVICE_ID, OPTION_3_2, 0}, 5609 {BCM53570_DEVICE_ID, OPTION_3_3, 0}, 5610 {BCM53570_DEVICE_ID, OPTION_4_0, 0}, 5611 {BCM53570_DEVICE_ID, OPTION_4_1, 0}, 5612 {BCM53570_DEVICE_ID, OPTION_4_2, 0}, 5613 {BCM53570_DEVICE_ID, OPTION_4_3, 0}, 5614 {BCM53570_DEVICE_ID, OPTION_6_0, 0}, 5615 {BCM53570_DEVICE_ID, OPTION_6_1, 0}, 5616 {BCM53570_DEVICE_ID, OPTION_6_2, 0}, 5617 {BCM53570_DEVICE_ID, OPTION_6_3, 0}, 5618 {BCM53570_DEVICE_ID, OPTION_8_0, 0}, 5619 {BCM53570_DEVICE_ID, OPTION_8_1, 0}, 5620 {BCM53570_DEVICE_ID, OPTION_8_2, 0}, 5621 {BCM53570_DEVICE_ID, OPTION_8_3, 0}, 5622 /* BCM53575 */ 5623 {BCM53575_DEVICE_ID, OPTION_12_0, 1}, 5624 {BCM53575_DEVICE_ID, OPTION_13_0, 0}, 5625 {0, "not existed", 0}, 5626 }; 5627 5628 #define FLEX_2P5 0 /* flex 2.5 */ 5629 #define FLEX_10 1 /* flex 10 */ 5630 #define FLEX_40 2 /* flex 40 */ 5631 #define FLEX_50 3 /* flex 50 */ 5632 #define FLEX_XAUI 4 /* flex xaui */ 5633 #define FLEX_20G_RIOT 5 /* flex 20G RioT */ 5634 #define FLEX_OFF (-1) /* core is off */ 5635 5636 typedef struct _gh2_option_tsc_flex_mode_s { 5637 char *config_op; /* option string */ 5638 int mode[_GH2_MAX_TSC_COUNT]; 5639 } _gh2_option_tsc_flex_mode_t; 5640 5641 /* Supported flex port speed of each TSC */ 5642 STATIC _gh2_option_tsc_flex_mode_t _gh2_option_tsc_flex_modes[] = { 5643 /* OPTION_1 */ 5644 {OPTION_1, {FLEX_40, FLEX_40, FLEX_40, FLEX_40, 5645 FLEX_40, FLEX_40, FLEX_40, FLEX_50}}, 5646 /* OPTION_2 */ 5647 {OPTION_2, {FLEX_40, FLEX_40, FLEX_40, FLEX_40, 5648 FLEX_40, FLEX_40, FLEX_40, FLEX_40}}, 5649 /* OPTION_2A */ 5650 {OPTION_2A, {FLEX_40, FLEX_40, FLEX_40, FLEX_40, 5651 FLEX_40, FLEX_40, FLEX_40, FLEX_40}}, 5652 /* OPTION_3A */ 5653 {OPTION_3A, {FLEX_10, FLEX_OFF, FLEX_10, FLEX_10, 5654 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_50}}, 5655 /* OPTION_4A */ 5656 {OPTION_4A, {FLEX_2P5, FLEX_2P5, FLEX_2P5, FLEX_2P5, 5657 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_50}}, 5658 /* OPTION_5 */ 5659 {OPTION_5, {FLEX_2P5, FLEX_2P5, FLEX_2P5, FLEX_2P5, 5660 FLEX_40, FLEX_2P5, FLEX_40, FLEX_50}}, 5661 /* OPTION_6 */ 5662 {OPTION_6, {FLEX_OFF, FLEX_OFF, FLEX_OFF, FLEX_OFF, 5663 FLEX_40, FLEX_XAUI, FLEX_40, FLEX_50}}, 5664 /* OPTION_7 */ 5665 {OPTION_7, {FLEX_40, FLEX_40, FLEX_40, FLEX_40, 5666 FLEX_40, FLEX_40, FLEX_40, FLEX_40}}, 5667 /* OPTION_7B */ 5668 {OPTION_7B, {FLEX_40, FLEX_40, FLEX_40, FLEX_20G_RIOT, 5669 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_40}}, 5670 /* OPTION_8B */ 5671 {OPTION_8B, {FLEX_2P5, FLEX_2P5, FLEX_2P5, FLEX_20G_RIOT, 5672 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_50}}, 5673 /* OPTION_9B */ 5674 {OPTION_9B, {FLEX_OFF, FLEX_OFF, FLEX_OFF, FLEX_20G_RIOT, 5675 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_50}}, 5676 /* OPTION_10B */ 5677 {OPTION_10B, {FLEX_OFF, FLEX_OFF, FLEX_OFF, FLEX_20G_RIOT, 5678 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_50}}, 5679 /* OPTION_11B */ 5680 {OPTION_11B, {FLEX_OFF, FLEX_OFF, FLEX_OFF, FLEX_20G_RIOT, 5681 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_50}}, 5682 /* OPTION_12B */ 5683 {OPTION_12B, {FLEX_OFF, FLEX_OFF, FLEX_40, FLEX_20G_RIOT, 5684 FLEX_40, FLEX_20G_RIOT, FLEX_40, FLEX_40}}, 5685 /* OPTION_12 */ 5686 {OPTION_12, {FLEX_OFF, FLEX_OFF, FLEX_40, FLEX_40, 5687 FLEX_40, FLEX_40, FLEX_40, FLEX_40}}, 5688 /* OPTION_13 */ 5689 {OPTION_13, {FLEX_OFF, FLEX_OFF, FLEX_OFF, FLEX_OFF, 5690 FLEX_40, FLEX_XAUI, FLEX_OFF, FLEX_OFF}}, 5691 /* OPTION_14 */ 5692 {OPTION_14, {FLEX_OFF, FLEX_OFF, FLEX_40, FLEX_OFF, 5693 FLEX_40, FLEX_OFF, FLEX_40, FLEX_50}}, 5694 /* invalid entry */ 5695 {NULL, {-1, -1, -1, -1, -1, -1, -1, -1}}, 5696 }; 5697 5698 /* MMU related */ 5699 #define GH2_A0_MMU_CBP_FULL_SIZE 0x5fff 5700 #define GH2_A0_MMU_CBP_HALF_SIZE 0x47ff 5701 #define GH2_A0_MMU_CBP_QUARTER_SIZE 0x2fff 5702 5703 #define GH2_B0_MMU_CBP_FULL_SIZE 0x7fff 5704 #define GH2_B0_MMU_CBP_HALF_SIZE 0x5fff 5705 #define GH2_B0_MMU_CBP_QUARTER_SIZE 0x3fff 5706 5707 #define CMIC_PARITY_MMU_TO_CMIC_MEMFAIL_INTR_BIT 0x0001 5708 #define CMIC_PARITY_EP_TO_CMIC_PERR_INTR_BIT 0x0002 5709 #define CMIC_PARITY_IP0_TO_CMIC_PERR_INTR_BIT 0x0004 5710 #define CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT 0x0008 5711 #define CMIC_PARITY_IP2_TO_CMIC_PERR_INTR_BIT 0x0010 5712 5713 #define _SOC_GH2_MMU_IPMC_GROUP_MAX 65 5714 static soc_mem_t ipmc_mems[_SOC_GH2_MMU_IPMC_GROUP_MAX] = { 5715 INVALIDm, INVALIDm, 5716 MMU_IPMC_GROUP_TBL2m, MMU_IPMC_GROUP_TBL3m, 5717 MMU_IPMC_GROUP_TBL4m, MMU_IPMC_GROUP_TBL5m, 5718 MMU_IPMC_GROUP_TBL6m, MMU_IPMC_GROUP_TBL7m, 5719 MMU_IPMC_GROUP_TBL8m, MMU_IPMC_GROUP_TBL9m, 5720 MMU_IPMC_GROUP_TBL10m, MMU_IPMC_GROUP_TBL11m, 5721 MMU_IPMC_GROUP_TBL12m, MMU_IPMC_GROUP_TBL13m, 5722 MMU_IPMC_GROUP_TBL14m, MMU_IPMC_GROUP_TBL15m, 5723 MMU_IPMC_GROUP_TBL16m, MMU_IPMC_GROUP_TBL17m, 5724 MMU_IPMC_GROUP_TBL18m, MMU_IPMC_GROUP_TBL19m, 5725 MMU_IPMC_GROUP_TBL20m, MMU_IPMC_GROUP_TBL21m, 5726 MMU_IPMC_GROUP_TBL22m, MMU_IPMC_GROUP_TBL23m, 5727 MMU_IPMC_GROUP_TBL24m, MMU_IPMC_GROUP_TBL25m, 5728 MMU_IPMC_GROUP_TBL26m, MMU_IPMC_GROUP_TBL27m, 5729 MMU_IPMC_GROUP_TBL28m, MMU_IPMC_GROUP_TBL29m, 5730 MMU_IPMC_GROUP_TBL30m, MMU_IPMC_GROUP_TBL31m, 5731 MMU_IPMC_GROUP_TBL32m, MMU_IPMC_GROUP_TBL33m, 5732 MMU_IPMC_GROUP_TBL34m, MMU_IPMC_GROUP_TBL35m, 5733 MMU_IPMC_GROUP_TBL36m, MMU_IPMC_GROUP_TBL37m, 5734 MMU_IPMC_GROUP_TBL38m, MMU_IPMC_GROUP_TBL39m, 5735 MMU_IPMC_GROUP_TBL40m, MMU_IPMC_GROUP_TBL41m, 5736 MMU_IPMC_GROUP_TBL42m, MMU_IPMC_GROUP_TBL43m, 5737 MMU_IPMC_GROUP_TBL44m, MMU_IPMC_GROUP_TBL45m, 5738 MMU_IPMC_GROUP_TBL46m, MMU_IPMC_GROUP_TBL47m, 5739 MMU_IPMC_GROUP_TBL48m, MMU_IPMC_GROUP_TBL49m, 5740 MMU_IPMC_GROUP_TBL50m, MMU_IPMC_GROUP_TBL51m, 5741 MMU_IPMC_GROUP_TBL52m, MMU_IPMC_GROUP_TBL53m, 5742 MMU_IPMC_GROUP_TBL54m, MMU_IPMC_GROUP_TBL55m, 5743 MMU_IPMC_GROUP_TBL56m, MMU_IPMC_GROUP_TBL57m, 5744 MMU_IPMC_GROUP_TBL58m, MMU_IPMC_GROUP_TBL59m, 5745 MMU_IPMC_GROUP_TBL60m, MMU_IPMC_GROUP_TBL61m, 5746 MMU_IPMC_GROUP_TBL62m, MMU_IPMC_GROUP_TBL63m, 5747 MMU_IPMC_GROUP_TBL64m 5748 }; 5749 5750 static int 5751 soc_greyhound2_pipe_mem_clear(int unit) 5752 { 5753 uint32 rval; 5754 int pipe_init_usec, index; 5755 soc_timeout_t to; 5756 static const struct { 5757 soc_mem_t mem; 5758 uint32 skip_flags; /* always skip on QUICKTURN or XGSSIM */ 5759 } cam_list[] = { 5760 { CPU_COS_MAPm, BOOT_F_PLISIM }, 5761 { EFP_TCAMm, BOOT_F_PLISIM }, 5762 { FP_GLOBAL_MASK_TCAMm, BOOT_F_PLISIM }, 5763 { FP_TCAMm, BOOT_F_PLISIM }, 5764 { L2_USER_ENTRYm, BOOT_F_PLISIM }, 5765 { L2_USER_ENTRY_ONLYm, BOOT_F_PLISIM }, 5766 { L3_DEFIPm, BOOT_F_PLISIM }, 5767 { L3_DEFIP_ONLYm, BOOT_F_PLISIM }, 5768 { VFP_TCAMm, BOOT_F_PLISIM }, 5769 { VLAN_SUBNETm, 0 },/* VLAN API needs all 0 mask */ 5770 { VLAN_SUBNET_ONLYm, 0 } 5771 }; 5772 5773 /* 5774 * Reset the IPIPE and EPIPE block 5775 */ 5776 rval = 0; 5777 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 5778 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 5779 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 5780 /* Set count to # entries in largest IPIPE table, L2_ENTRYm */ 5781 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x8000); 5782 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 5783 5784 rval = 0; 5785 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 5786 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 5787 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 5788 /* 5789 * Set count to # entries in largest EPIPE table, 5790 * SR_FLOW_EGR_COUNTER_CONTROLm 5791 */ 5792 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x2000); 5793 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 5794 5795 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 5796 if (SAL_BOOT_SIMULATION) { 5797 pipe_init_usec = 10000000; 5798 } else { 5799 pipe_init_usec = 50000; 5800 } 5801 soc_timeout_init(&to, pipe_init_usec, 0); 5802 5803 /* Wait for IPIPE memory initialization done. */ 5804 do { 5805 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 5806 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 5807 break; 5808 } 5809 if (soc_timeout_check(&to)) { 5810 LOG_WARN(BSL_LS_SOC_COMMON, 5811 (BSL_META_U(unit, 5812 "unit %d : ING_HW_RESET timeout\n"), unit)); 5813 break; 5814 } 5815 } while (TRUE); 5816 5817 /* Wait for EPIPE memory initialization done. */ 5818 do { 5819 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 5820 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 5821 break; 5822 } 5823 if (soc_timeout_check(&to)) { 5824 LOG_WARN(BSL_LS_SOC_COMMON, 5825 (BSL_META_U(unit, "unit %d : EGR_HW_RESET timeout\n"), unit)); 5826 break; 5827 } 5828 } while (TRUE); 5829 5830 rval = 0; 5831 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 5832 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 5833 5834 /* Processing tables that are not handled by hardware reset */ 5835 if (!SAL_BOOT_SIMULATION || SAL_BOOT_BCMSIM) { 5836 /* TCAM tables are not handled by hardware reset control */ 5837 for (index = 0; index < sizeof(cam_list) / sizeof(cam_list[0]); 5838 index++) { 5839 if (sal_boot_flags_get() & cam_list[index].skip_flags) { 5840 continue; 5841 } 5842 if (((cam_list[index].mem == EFP_TCAMm) || 5843 (cam_list[index].mem == VFP_TCAMm)) && 5844 (!soc_feature(unit, soc_feature_field_multi_stage))) { 5845 continue; 5846 } 5847 5848 SOC_IF_ERROR_RETURN 5849 (soc_mem_clear(unit, cam_list[index].mem, COPYNO_ALL, TRUE)); 5850 } 5851 5852 /* MMU_IPMC_VLAN_TBL */ 5853 SOC_IF_ERROR_RETURN 5854 (soc_mem_clear(unit, MMU_IPMC_VLAN_TBLm, COPYNO_ALL, TRUE)); 5855 5856 /* MMU_IPMC_GROUP_TBLn : n is 2 ~ 64 in GH2 */ 5857 for (index = 0; index < _SOC_GH2_MMU_IPMC_GROUP_MAX; index++) { 5858 if (ipmc_mems[index] != INVALIDm) { 5859 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, 5860 ipmc_mems[index], COPYNO_ALL, TRUE)); 5861 } 5862 } 5863 5864 } 5865 5866 return SOC_E_NONE; 5867 } 5868 5869 /* 5870 * Function: 5871 * soc_greyhound2_gmac_init() 5872 * Purpose: 5873 * To init GMAC (should be moved to mac) 5874 */ 5875 STATIC int 5876 soc_greyhound2_gmac_init(int unit) 5877 { 5878 uint32 rval; 5879 uint32 prev_reg_addr; 5880 int port; 5881 5882 rval = 0; 5883 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 5884 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, GPORT_ENf, 1); 5885 prev_reg_addr = 0xffffffff; 5886 PBMP_E_ITER(unit, port) { 5887 uint32 reg_addr; 5888 if (IS_XL_PORT(unit, port) || IS_CL_PORT(unit, port)) { 5889 continue; 5890 } 5891 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 5892 if (reg_addr != prev_reg_addr) { 5893 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 5894 prev_reg_addr = reg_addr; 5895 } 5896 } 5897 prev_reg_addr = 0xffffffff; 5898 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 5899 PBMP_E_ITER(unit, port) { 5900 uint32 reg_addr; 5901 if (IS_XL_PORT(unit, port) || IS_CL_PORT(unit, port)) { 5902 continue; 5903 } 5904 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 5905 if (reg_addr != prev_reg_addr) { 5906 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 5907 prev_reg_addr = reg_addr; 5908 } 5909 } 5910 5911 return SOC_E_NONE; 5912 } 5913 5914 /* 5915 * Func : soc_greyhound2_pgw_encap_field_modify 5916 * - To write to PGW interface on GX/XL/CL port on indicated field 5917 */ 5918 int 5919 soc_greyhound2_pgw_encap_field_modify(int unit, 5920 soc_port_t lport, 5921 soc_field_t field, 5922 uint32 val) 5923 { 5924 int pport = SOC_INFO(unit).port_l2p_mapping[lport]; 5925 5926 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_XLPORT) { 5927 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 5928 PGW_XL_CONFIGr, lport, field, val)); 5929 } else if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_CLPORT) { 5930 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 5931 PGW_CL_CONFIGr, lport, field, val)); 5932 } else { 5933 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 5934 PGW_GE_CONFIGr, lport, field, val)); 5935 } 5936 5937 return SOC_E_NONE; 5938 } 5939 /* 5940 * Function: 5941 * soc_greyhound2_higig_mode_init() 5942 * Purpose: 5943 * To init the default Higig mode for HG port 5944 */ 5945 STATIC int 5946 soc_greyhound2_higig_mode_init(int unit) 5947 { 5948 uint32 rval; 5949 int port; 5950 5951 PBMP_PORT_ITER(unit, port) { 5952 if (!IS_HG_PORT(unit, port)) { 5953 continue; 5954 } 5955 if (!IS_XL_PORT(unit, port) && !IS_CL_PORT(unit, port)) { 5956 continue; 5957 } 5958 5959 /* Section below is used to config XLPORT and PGW related HiGig encap 5960 * setting for normal init process. 5961 */ 5962 if (IS_XL_PORT(unit, port)) { 5963 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 5964 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 5965 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 5966 } 5967 if (IS_CL_PORT(unit, port)) { 5968 SOC_IF_ERROR_RETURN(READ_CLPORT_CONFIGr(unit, port, &rval)); 5969 soc_reg_field_set(unit, CLPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 5970 SOC_IF_ERROR_RETURN(WRITE_CLPORT_CONFIGr(unit, port, rval)); 5971 } 5972 5973 /* only HG ports allows PGW encap setting below */ 5974 SOC_IF_ERROR_RETURN(soc_greyhound2_pgw_encap_field_modify(unit, 5975 port, HIGIG_MODEf, 1)); 5976 } 5977 5978 return SOC_E_NONE; 5979 } 5980 5981 /* 5982 * Function: 5983 * soc_greyhound2_mib_reset() 5984 * Purpose: 5985 * Reset MIB counter 5986 */ 5987 STATIC int 5988 soc_greyhound2_mib_reset(int unit) 5989 { 5990 uint32 rval, fval; 5991 int blk, bindex; 5992 soc_info_t *si = &SOC_INFO(unit); 5993 int blk_port, phy_port; 5994 5995 /* 5996 * Reset XLPORT and CLPORT MIB counter 5997 * (registers implemented in memory). 5998 * The clear function is implemented with read-modify-write, 5999 * parity needs to be disabled 6000 */ 6001 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 6002 blk_port = SOC_BLOCK_PORT(unit, blk); 6003 if (blk_port < 0) { 6004 continue; 6005 } 6006 phy_port = si->port_l2p_mapping[blk_port]; 6007 fval = 0; 6008 for (bindex = 0; bindex < 4; bindex++) { 6009 if (si->port_p2l_mapping[phy_port + bindex] != -1) { 6010 fval |= 1 << bindex; 6011 } 6012 } 6013 rval = 0; 6014 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, fval); 6015 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, blk_port, rval)); 6016 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, blk_port, 0)); 6017 } 6018 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 6019 blk_port = SOC_BLOCK_PORT(unit, blk); 6020 if (blk_port < 0) { 6021 continue; 6022 } 6023 phy_port = si->port_l2p_mapping[blk_port]; 6024 fval = 0; 6025 for (bindex = 0; bindex < 4; bindex++) { 6026 if (si->port_p2l_mapping[phy_port + bindex] != -1) { 6027 fval |= 1 << bindex; 6028 } 6029 } 6030 rval = 0; 6031 soc_reg_field_set(unit, CLPORT_MIB_RESETr, &rval, CLR_CNTf, fval); 6032 SOC_IF_ERROR_RETURN(WRITE_CLPORT_MIB_RESETr(unit, blk_port, rval)); 6033 SOC_IF_ERROR_RETURN(WRITE_CLPORT_MIB_RESETr(unit, blk_port, 0)); 6034 } 6035 6036 return SOC_E_NONE; 6037 } 6038 6039 /* 6040 * GH2 interrupt handler functions 6041 */ 6042 STATIC soc_gh2_oam_ser_handler_t 6043 gh2_oam_ser_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 6044 STATIC soc_gh2_oam_handler_t gh2_oam_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 6045 STATIC soc_gh2_tsn_event_handler_t gh2_intr_sr_h[SOC_MAX_NUM_DEVICES] = {NULL}; 6046 STATIC soc_gh2_cosq_event_handler_t 6047 gh2_intr_tas_h[SOC_MAX_NUM_DEVICES] = {NULL}; 6048 STATIC soc_gh2_taf_event_handler_t 6049 gh2_intr_taf_h[SOC_MAX_NUM_DEVICES] = {NULL}; 6050 6051 STATIC soc_ser_functions_t gh2_ser_functions[SOC_MAX_NUM_DEVICES]; 6052 static uint8 gh2_event_handler_init = 0; 6053 6054 /* Interrupt types on GH2 */ 6055 #define GH2_INTR_PARITY (1) 6056 #define GH2_INTR_L2_OVERFLOW (2) 6057 #define GH2_INTR_OAM (3) 6058 #define GH2_INTR_TAS (4) 6059 #define GH2_INTR_SR (5) 6060 #define GH2_INTR_TAF (6) 6061 6062 /* CMIC IRQ type */ 6063 #define GH2_CMIC_IRQ3 (3) 6064 #define GH2_CMIC_IRQ4 (4) 6065 6066 /* 6067 * Helper macro to get interrupt types' device CMIC IRQx mask 6068 */ 6069 #define GH2_IRQ_MASK(bit) (1<<(bit)) /* Bit 0-31 */ 6070 /* 6071 * GH2_INTR_PARITY: CMIC_CMCx_IRQ_STAT3r 6072 * bit0-6(mmu,ep,ip), 8-20(ge,xl,cl port) 6073 */ 6074 #define GH2_IRQ3_INTR_MASK_PARITY (0x1FFF7F) 6075 /* GH2_INTR_L2_OVERFLOW: IP1_TO_CMIC_PERR_INTR (CMIC_CMCx_IRQ_STAT3r : bit 3) */ 6076 #define GH2_IRQ3_INTR_MASK_L2_OVERFLOW (0x8) 6077 /* GH2_INTR_OAM: IP2_TO_CMIC_PERR_INTR (CMIC_CMCx_IRQ_STAT3r : bit 4) */ 6078 #define GH2_IRQ3_INTR_MASK_OAM (0x10) 6079 /* GH2_INTR_TAS: MMU_TO_CMIC_MEMFAIL_INTR (CMIC_CMCx_IRQ_STAT3r : bit 0) */ 6080 #define GH2_IRQ3_INTR_MASK_TAS (0x1) 6081 /* 6082 * GH2_INTR_SR: 6083 * EP_TO_CMIC_PERR_INTR (CMIC_CMCx_IRQ_STAT3r : bit 1) 6084 * IP2_TO_CMIC_PERR_INTR (CMIC_CMCx_IRQ_STAT3r : bit 4) 6085 * IP2_SR_TH_TO_CMIC_INTR (CMIC_CMCx_IRQ_STAT4r : bit 3) 6086 * TAF_GSG_TO_CMIC_INTR (CMIC_CMCx_IRQ_STAT4r : bit 4) 6087 */ 6088 #define GH2_IRQ3_INTR_MASK_SR (0x12) 6089 #define GH2_IRQ4_INTR_MASK_SR (0x8) 6090 #define GH2_IRQ4_INTR_MASK_TAF (0x10) 6091 6092 6093 /* Fields for OAM SER and event */ 6094 soc_field_t _soc_gh2_oam_interrupt_fields[] = { 6095 SOME_RMEP_CCM_DEFECT_INTRf, 6096 SOME_RDI_DEFECT_INTRf, 6097 ANY_RMEP_TLV_PORT_DOWN_INTRf, 6098 ANY_RMEP_TLV_PORT_UP_INTRf, 6099 ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, 6100 ANY_RMEP_TLV_INTERFACE_UP_INTRf, 6101 XCON_CCM_DEFECT_INTRf, 6102 ERROR_CCM_DEFECT_INTRf, 6103 INVALIDf 6104 }; 6105 6106 /* Fields mask for TAS evnets bit 22,21,20,19,17,16 in MEMFAILINTSTATUSr */ 6107 #define GH2_TAS_INTR_STATUS_MASK (0x7B0000) 6108 6109 /* Fields mask for TAF evnets bit 22,21,20,19,17,16 in TAF_MEMFAILINTSTATUSr */ 6110 #define GH2_TAF_INTR_STATUS_MASK (0x7B0000) 6111 6112 /* Fields mask for SR events bit 43,44 in IP2_INTR_STATUSr */ 6113 #define GH2_IP2_SR_LAN_INTR_STATUS_HI_MASK (0x1800) 6114 6115 /* Fields mask for L2 overflow bit 8,9 in IP1_INTR_STATUSr */ 6116 #define GH2_IP1_L2_INTR_STATUS_MASK (0x300) 6117 6118 /* Helper function to config the interrupt mask */ 6119 STATIC int 6120 soc_gh2_cmic_interrupt_mask(int unit, int intr_type, int enable) 6121 { 6122 uint32 mask3, mask4; 6123 int rv = SOC_E_NONE; 6124 6125 mask3 = 0; 6126 mask4 = 0; 6127 switch (intr_type) { 6128 case GH2_INTR_PARITY: 6129 mask3 = GH2_IRQ3_INTR_MASK_PARITY; 6130 break; 6131 case GH2_INTR_L2_OVERFLOW: 6132 mask3 = GH2_IRQ3_INTR_MASK_L2_OVERFLOW; 6133 break; 6134 case GH2_INTR_OAM: 6135 mask3 = GH2_IRQ3_INTR_MASK_OAM; 6136 break; 6137 case GH2_INTR_TAS: 6138 mask3 = GH2_IRQ3_INTR_MASK_TAS; 6139 break; 6140 case GH2_INTR_SR: 6141 mask3 = GH2_IRQ3_INTR_MASK_SR; 6142 mask4 = GH2_IRQ4_INTR_MASK_SR; 6143 break; 6144 case GH2_INTR_TAF: 6145 mask4 = GH2_IRQ4_INTR_MASK_TAF; 6146 break; 6147 default : 6148 return SOC_E_PARAM; 6149 } 6150 6151 if (enable) { 6152 if (mask3) { 6153 SOC_IF_ERROR_RETURN(soc_cmicm_intr3_enable(unit, mask3)); 6154 } 6155 if (mask4) { 6156 SOC_IF_ERROR_RETURN(soc_cmicm_intr4_enable(unit, mask4)); 6157 } 6158 } else { 6159 /* 6160 * Each bit in IRQ3 might be shared with multiple types 6161 * Remove bits from disable mask if it is required for 6162 * the valid/working types. 6163 */ 6164 if (SOC_CONTROL(unit)->l2_overflow_enable) { 6165 /* remove l2 mask */ 6166 mask3 &= ~GH2_IRQ3_INTR_MASK_L2_OVERFLOW; 6167 } 6168 if (gh2_intr_sr_h[unit]) { 6169 /* remove sr mask */ 6170 mask3 &= ~GH2_IRQ3_INTR_MASK_SR; 6171 } 6172 if (gh2_intr_tas_h[unit]) { 6173 /* remove tas mask */ 6174 mask3 &= ~GH2_IRQ3_INTR_MASK_TAS; 6175 } 6176 if (gh2_oam_handler[unit]) { 6177 /* remove oam mask */ 6178 mask3 &= ~GH2_IRQ3_INTR_MASK_OAM; 6179 } 6180 if (gh2_ser_functions[unit]._soc_ser_parity_error_cmicm_intr_f) { 6181 /* remove ser mask */ 6182 mask3 &= ~GH2_IRQ3_INTR_MASK_PARITY; 6183 } 6184 if (gh2_intr_taf_h[unit]) { 6185 /* remove taf mask */ 6186 mask4 &= ~GH2_IRQ4_INTR_MASK_TAF; 6187 } 6188 6189 if (mask3) { 6190 SOC_IF_ERROR_RETURN(soc_cmicm_intr3_disable(unit, mask3)); 6191 } 6192 if (mask4) { 6193 SOC_IF_ERROR_RETURN(soc_cmicm_intr4_disable(unit, mask4)); 6194 } 6195 } 6196 return rv; 6197 } 6198 6199 /* SER */ 6200 void 6201 soc_gh2_ser_cmic_interrupt_enable(int unit, int enable) 6202 { 6203 (void)soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_PARITY, enable); 6204 } 6205 6206 /* OAM SER */ 6207 void 6208 soc_gh2_oam_ser_handler_register(int unit, soc_gh2_oam_ser_handler_t handler) 6209 { 6210 gh2_oam_ser_handler[unit] = handler; 6211 } 6212 6213 int 6214 soc_gh2_oam_ser_process(int unit, soc_mem_t mem, int index) 6215 { 6216 if (gh2_oam_ser_handler[unit]) { 6217 return gh2_oam_ser_handler[unit](unit, mem, index); 6218 } else { 6219 return SOC_E_UNAVAIL; 6220 } 6221 } 6222 6223 /* OAM event */ 6224 void 6225 soc_gh2_oam_handler_register(int unit, soc_gh2_oam_handler_t handler) 6226 { 6227 uint64 rval; 6228 int rv, id = 0; 6229 uint32 enable = 0; 6230 6231 gh2_oam_handler[unit] = handler; 6232 6233 if (handler != NULL) { 6234 enable = 1; 6235 } 6236 rv = READ_IP2_INTR_ENABLEr(unit, &rval); 6237 if (rv) { 6238 LOG_ERROR(BSL_LS_SOC_COMMON, 6239 (BSL_META_U(unit, 6240 "unit %d: Error reading %s reg !!\n"), 6241 unit, SOC_REG_NAME(unit, IP2_INTR_ENABLEr))); 6242 } 6243 while (_soc_gh2_oam_interrupt_fields[id] != INVALIDf) { 6244 soc_reg64_field32_set(unit, IP2_INTR_ENABLEr, &rval, 6245 _soc_gh2_oam_interrupt_fields[id], enable); 6246 id++; 6247 } 6248 rv = WRITE_IP2_INTR_ENABLEr(unit, rval); 6249 if (rv) { 6250 LOG_ERROR(BSL_LS_SOC_COMMON, 6251 (BSL_META_U(unit, 6252 "unit %d: Error writing %s reg !!\n"), 6253 unit, SOC_REG_NAME(unit, IP1_INTR_ENABLEr))); 6254 } 6255 6256 (void)soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_OAM, enable); 6257 } 6258 6259 STATIC int 6260 _soc_gh2_process_oam_interrupt(int unit) 6261 { 6262 uint64 rval; 6263 int id = 0; 6264 soc_gh2_oam_handler_t oam_handler_snapshot = gh2_oam_handler[unit]; 6265 6266 SOC_IF_ERROR_RETURN(READ_IP2_INTR_STATUSr(unit, &rval)); 6267 6268 while (_soc_gh2_oam_interrupt_fields[id] != INVALIDf) { 6269 if (soc_reg64_field32_get(unit, IP2_INTR_STATUSr, rval, 6270 _soc_gh2_oam_interrupt_fields[id])) { 6271 if (oam_handler_snapshot != NULL) { 6272 (void)(oam_handler_snapshot(unit, 6273 _soc_gh2_oam_interrupt_fields[id])); 6274 } 6275 } 6276 id++; 6277 } 6278 6279 return SOC_E_NONE; 6280 } 6281 6282 /* TAS interrupt/evnet */ 6283 int 6284 soc_gh2_cosq_event_handler_register( 6285 int unit, 6286 soc_gh2_cosq_event_handler_t handler) 6287 { 6288 int rv = SOC_E_NONE; 6289 6290 gh2_intr_tas_h[unit] = handler; 6291 6292 if (handler != NULL) { 6293 rv = soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_TAS, 1); 6294 } else { 6295 rv = soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_TAS, 0); 6296 } 6297 if (SOC_FAILURE(rv)) { 6298 gh2_intr_tas_h[unit] = NULL; 6299 } 6300 return rv; 6301 } 6302 6303 STATIC void 6304 soc_gh2_process_tas_intr(int unit) 6305 { 6306 uint32 rval; 6307 6308 rval = 0; 6309 /* check if this belong to interested TAS interrupt */ 6310 if (SOC_FAILURE(READ_MEMFAILINTSTATUSr(unit, &rval))) { 6311 return; 6312 } 6313 6314 if (rval & GH2_TAS_INTR_STATUS_MASK) { 6315 if (gh2_intr_tas_h[unit] != NULL) { 6316 gh2_intr_tas_h[unit](unit); 6317 } 6318 } 6319 return; 6320 } 6321 6322 /* TAF interrupt/evnet */ 6323 int 6324 soc_gh2_taf_event_handler_register( 6325 int unit, 6326 soc_gh2_taf_event_handler_t handler) 6327 { 6328 int rv = SOC_E_NONE; 6329 6330 gh2_intr_taf_h[unit] = handler; 6331 6332 if (handler != NULL) { 6333 rv = soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_TAF, 1); 6334 } else { 6335 rv = soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_TAF, 0); 6336 } 6337 if (SOC_FAILURE(rv)) { 6338 gh2_intr_taf_h[unit] = NULL; 6339 } 6340 return rv; 6341 } 6342 6343 STATIC void 6344 soc_gh2_process_taf_intr(int unit) 6345 { 6346 uint32 rval; 6347 6348 rval = 0; 6349 /* check if this belong to interested TAS interrupt */ 6350 if (SOC_FAILURE(READ_TAF_MEMFAILINTSTATUSr(unit, &rval))) { 6351 return; 6352 } 6353 6354 if (rval & GH2_TAF_INTR_STATUS_MASK) { 6355 if (gh2_intr_taf_h[unit] != NULL) { 6356 gh2_intr_taf_h[unit](unit 6357 ); 6358 } 6359 } 6360 return; 6361 } 6362 6363 6364 /* TSN/SR interrupt/event */ 6365 int 6366 soc_gh2_tsn_event_handler_register( 6367 int unit, 6368 soc_gh2_tsn_event_handler_t handler) 6369 { 6370 int rv; 6371 6372 gh2_intr_sr_h[unit] = handler; 6373 6374 if (handler != NULL) { 6375 rv = soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_SR, 1); 6376 } else { 6377 rv = soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_SR, 0); 6378 } 6379 if (SOC_FAILURE(rv)) { 6380 gh2_intr_sr_h[unit] = NULL; 6381 } 6382 return rv; 6383 } 6384 6385 STATIC int 6386 soc_gh2_process_sr_intr(int unit, int type) 6387 { 6388 uint64 rval64; 6389 uint32 rval32; 6390 uint8 lan_err = 0, ip_cnt_err = 0, ep_cnt_err = 0; 6391 uint16 dev_id; 6392 uint8 rev_id; 6393 6394 soc_cm_get_id(unit, &dev_id, &rev_id); 6395 6396 if (type == GH2_CMIC_IRQ3) { 6397 SOC_IF_ERROR_RETURN(READ_IP2_INTR_STATUSr(unit, &rval64)); 6398 if (COMPILER_64_HI(rval64) & GH2_IP2_SR_LAN_INTR_STATUS_HI_MASK) { 6399 lan_err = 1; 6400 } 6401 SOC_IF_ERROR_RETURN(READ_EGR_MISC_INTR_STATUSr(unit, &rval32)); 6402 if (rval32) { 6403 ep_cnt_err = 1; 6404 } 6405 } 6406 if (type == GH2_CMIC_IRQ4) { 6407 if (rev_id == BCM56170_B0_REV_ID) { 6408 SOC_IF_ERROR_RETURN(READ_IP2_SR_TH_INTR_STATUSr(unit, &rval64)); 6409 if (COMPILER_64_HI(rval64) || COMPILER_64_LO(rval64)) { 6410 ip_cnt_err = 1; 6411 } 6412 } else { 6413 SOC_IF_ERROR_RETURN( 6414 READ_IP2_SR_TH_INTR_STATUSr_REG32(unit, &rval32)); 6415 if (rval32) { 6416 ip_cnt_err = 1; 6417 } 6418 } 6419 } 6420 6421 if (lan_err || ep_cnt_err || ip_cnt_err) { 6422 if (gh2_intr_sr_h[unit] != NULL) { 6423 gh2_intr_sr_h[unit](unit, lan_err, ip_cnt_err, ep_cnt_err); 6424 } 6425 } 6426 return SOC_E_NONE; 6427 } 6428 6429 STATIC void 6430 soc_gh2_process_l2_intr(int unit) 6431 { 6432 uint32 rval; 6433 6434 if (SOC_FAILURE(READ_IP1_INTR_STATUSr(unit, &rval))) { 6435 return; 6436 } 6437 6438 if (rval & GH2_IP1_L2_INTR_STATUS_MASK) { 6439 (void)_soc_hr3_process_l2_overflow(unit); 6440 } 6441 return; 6442 } 6443 6444 /* Registered interrupt handler */ 6445 STATIC void 6446 soc_gh2_intr_handler(void *unit_vp, void *d1, void *d2, void *d3, void *d4) 6447 { 6448 int unit = PTR_TO_INT(unit_vp); 6449 int type = PTR_TO_INT(d3); 6450 int val = PTR_TO_INT(d4); 6451 uint32 mask = GH2_IRQ_MASK(val); 6452 6453 if (type == GH2_CMIC_IRQ4) { 6454 if (mask & GH2_IRQ4_INTR_MASK_SR) { 6455 soc_gh2_process_sr_intr(unit, type); 6456 } 6457 if (mask & GH2_IRQ4_INTR_MASK_TAF) { 6458 soc_gh2_process_taf_intr(unit); 6459 } 6460 (void)soc_cmicm_intr4_enable(unit, PTR_TO_INT(d2)); 6461 } else if (type == GH2_CMIC_IRQ3) { 6462 if (mask & GH2_IRQ3_INTR_MASK_TAS) { 6463 soc_gh2_process_tas_intr(unit); 6464 } 6465 if (mask & GH2_IRQ3_INTR_MASK_SR) { 6466 soc_gh2_process_sr_intr(unit, type); 6467 } 6468 if (mask & GH2_IRQ3_INTR_MASK_L2_OVERFLOW) { 6469 soc_gh2_process_l2_intr(unit); 6470 } 6471 if (mask & GH2_IRQ3_INTR_MASK_OAM) { 6472 (void)_soc_gh2_process_oam_interrupt(unit); 6473 } 6474 /* process parity */ 6475 if (mask & GH2_IRQ3_INTR_MASK_PARITY) { 6476 (void)soc_gh2_ser_process_all(unit, mask); 6477 sal_usleep(SAL_BOOT_QUICKTURN ? 1000000 : 10000); 6478 } 6479 6480 (void)soc_cmicm_intr3_enable(unit, PTR_TO_INT(d2)); 6481 } 6482 return; 6483 } 6484 6485 /* Interrupt initialization function */ 6486 STATIC void 6487 soc_gh2_interrupt_init(int unit) 6488 { 6489 int u; 6490 6491 /* Initialize event handlers */ 6492 if (!gh2_event_handler_init) { 6493 for (u = 0; u < SOC_MAX_NUM_DEVICES; u++) { 6494 gh2_oam_ser_handler[u] = NULL; 6495 gh2_oam_handler[u] = NULL; 6496 gh2_intr_sr_h[u] = NULL; 6497 gh2_intr_tas_h[u] = NULL; 6498 gh2_intr_taf_h[u] = NULL; 6499 } 6500 gh2_event_handler_init = 1; 6501 } 6502 6503 /* register the SER callback function sets */ 6504 memset(&gh2_ser_functions[unit], 0, sizeof(soc_ser_functions_t)); 6505 gh2_ser_functions[unit]._soc_ser_fail_f = &soc_gh2_ser_fail; 6506 gh2_ser_functions[unit]._soc_ser_parity_error_cmicm_intr_f = 6507 &soc_gh2_intr_handler; 6508 soc_ser_function_register(unit, &gh2_ser_functions[unit]); 6509 } 6510 6511 /* End of Interrupt handler functions */ 6512 6513 #ifdef BCM_WARM_BOOT_SUPPORT 6514 STATIC int 6515 soc_gh2_port_init_speed_scache_allocate(int unit) 6516 { 6517 int rv; 6518 uint8 *scache_ptr; 6519 soc_scache_handle_t scache_handle; 6520 uint32 alloc_get = 0; 6521 uint32 alloc_size = 0; 6522 6523 alloc_size = sizeof(int) * SOC_MAX_PHY_PORTS; 6524 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 6525 rv = soc_scache_alloc(unit, scache_handle, alloc_size); 6526 if (rv == SOC_E_CONFIG) { 6527 /* Probably Level1 */ 6528 return SOC_E_NONE; 6529 } 6530 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 6531 SOC_IF_ERROR_RETURN( 6532 soc_scache_ptr_get(unit, scache_handle, &scache_ptr, &alloc_get)); 6533 6534 if (alloc_get != alloc_size) { 6535 /* Expected size doesn't match retrieved size */ 6536 return SOC_E_INTERNAL; 6537 } 6538 if (NULL == scache_ptr) { 6539 return SOC_E_MEMORY; 6540 } 6541 6542 return SOC_E_NONE; 6543 } 6544 6545 int 6546 soc_gh2_port_init_speed_scache_sync(int unit) 6547 { 6548 int rv, phy_port; 6549 uint8 *scache_ptr; 6550 soc_scache_handle_t scache_handle; 6551 uint32 alloc_get = 0, alloc_size = 0, scache_offset = 0; 6552 6553 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 6554 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 6555 rv = soc_scache_ptr_get(unit, scache_handle, 6556 &scache_ptr, &alloc_get); 6557 if (rv == SOC_E_NOT_FOUND) { 6558 /* Probably Level1 */ 6559 return SOC_E_NONE; 6560 } 6561 alloc_size = sizeof(int) * SOC_MAX_PHY_PORTS; 6562 if (alloc_get != alloc_size) { 6563 /* Expected size doesn't match retrieved size */ 6564 return SOC_E_INTERNAL; 6565 } 6566 if (NULL == scache_ptr) { 6567 return SOC_E_MEMORY; 6568 } 6569 6570 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 6571 sal_memcpy(&scache_ptr[scache_offset], 6572 &gh2_port_speed[phy_port], 6573 sizeof(int)); 6574 scache_offset += sizeof(int); 6575 } 6576 return SOC_E_NONE; 6577 } 6578 6579 STATIC int 6580 soc_gh2_port_init_speed_scache_recovery(int unit) 6581 { 6582 int rv, phy_port; 6583 uint8 *scache_ptr; 6584 soc_scache_handle_t scache_handle; 6585 uint32 alloc_get = 0, alloc_size = 0, scache_offset = 0; 6586 6587 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 6588 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 6589 rv = soc_scache_ptr_get(unit, scache_handle, 6590 &scache_ptr, &alloc_get); 6591 if (rv == SOC_E_NOT_FOUND) { 6592 /* Probably Level1 */ 6593 return SOC_E_NONE; 6594 } 6595 alloc_size = sizeof(int) * SOC_MAX_PHY_PORTS; 6596 if (alloc_get != alloc_size) { 6597 /* Expected size doesn't match retrieved size */ 6598 return SOC_E_INTERNAL; 6599 } 6600 if (NULL == scache_ptr) { 6601 return SOC_E_MEMORY; 6602 } 6603 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 6604 sal_memcpy(&gh2_port_speed[phy_port], 6605 &scache_ptr[scache_offset], 6606 sizeof(int)); 6607 scache_offset += sizeof(int); 6608 } 6609 return SOC_E_NONE; 6610 } 6611 #endif /* BCM_WARM_BOOT_SUPPORT */ 6612 6613 #define gh2_get_pval(_map_, _idx_, _max_num_) \ 6614 ((_idx_ < _max_num_) ? _map_[_idx_]: 0) 6615 6616 #define GH2_PGW_COUNT_GE8P (3) 6617 #define GH2_PORTS_PER_PGW_GE8P (8) 6618 #define GH2_FIRST_PORT_PGW_GE8P0 (2) 6619 #define GH2_PGW_COUNT_GE (2) 6620 #define GH2_PORTS_PER_PGW_GE (16) 6621 #define GH2_FIRST_PORT_PGW_GE0 (26) 6622 #define GH2_PGW_COUNT_XL (7) 6623 #define GH2_PORTS_PER_PGW_XL (4) 6624 #define GH2_FIRST_PORT_PGW_XL0 (2) 6625 #define GH2_PGW_COUNT_CL (1) 6626 #define GH2_PORTS_PER_PGW_CL (4) 6627 #define GH2_FIRST_PORT_PGW_CL0 (30) 6628 6629 STATIC int 6630 soc_greyhound2_ledup_init(int unit) 6631 { 6632 int i, j, pval0, pval1, pval2, pval3, port_idx; 6633 uint32 led_remap0[64] = {0}, led_remap1[64] = {0}; 6634 uint32 port_cnt = 0, port0_cnt = 0, port1_cnt = 0; 6635 uint32 rval = 0, rval1 = 0; 6636 uint32 disable_4x10 = 0, disable_4x25 = 0; 6637 int phy_p; 6638 6639 struct led_remap_t { 6640 uint32 reg_addr; 6641 uint32 port0; 6642 uint32 port1; 6643 uint32 port2; 6644 uint32 port3; 6645 }; 6646 struct led_remap_t ledup0_remap_r[] = { 6647 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 6648 REMAP_PORT_0f, REMAP_PORT_1f, REMAP_PORT_2f, REMAP_PORT_3f}, 6649 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 6650 REMAP_PORT_4f, REMAP_PORT_5f, REMAP_PORT_6f, REMAP_PORT_7f}, 6651 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 6652 REMAP_PORT_8f, REMAP_PORT_9f, REMAP_PORT_10f, REMAP_PORT_11f}, 6653 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 6654 REMAP_PORT_12f, REMAP_PORT_13f, REMAP_PORT_14f, REMAP_PORT_15f}, 6655 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 6656 REMAP_PORT_16f, REMAP_PORT_17f, REMAP_PORT_18f, REMAP_PORT_19f}, 6657 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 6658 REMAP_PORT_20f, REMAP_PORT_21f, REMAP_PORT_22f, REMAP_PORT_23f}, 6659 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 6660 REMAP_PORT_24f, REMAP_PORT_25f, REMAP_PORT_26f, REMAP_PORT_27f}, 6661 {CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, 6662 REMAP_PORT_28f, REMAP_PORT_29f, REMAP_PORT_30f, REMAP_PORT_31f}, 6663 {CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, 6664 REMAP_PORT_32f, REMAP_PORT_33f, REMAP_PORT_34f, REMAP_PORT_35f}, 6665 {CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, 6666 REMAP_PORT_36f, REMAP_PORT_37f, REMAP_PORT_38f, REMAP_PORT_39f}, 6667 {CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, 6668 REMAP_PORT_40f, REMAP_PORT_41f, REMAP_PORT_42f, REMAP_PORT_43f}, 6669 {CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, 6670 REMAP_PORT_44f, REMAP_PORT_45f, REMAP_PORT_46f, REMAP_PORT_47f}, 6671 {CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, 6672 REMAP_PORT_48f, REMAP_PORT_49f, REMAP_PORT_50f, REMAP_PORT_51f}, 6673 {CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, 6674 REMAP_PORT_52f, REMAP_PORT_53f, REMAP_PORT_54f, REMAP_PORT_55f}, 6675 {CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, 6676 REMAP_PORT_56f, REMAP_PORT_57f, REMAP_PORT_58f, REMAP_PORT_59f}, 6677 {CMIC_LEDUP0_PORT_ORDER_REMAP_60_63r, 6678 REMAP_PORT_60f, REMAP_PORT_61f, REMAP_PORT_62f, REMAP_PORT_63f} 6679 }; 6680 6681 /* Greyhound2 has 2 LED chan for storing port number that is greater than 63 */ 6682 struct led_remap_t ledup1_remap_r[] = { 6683 {CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, 6684 REMAP_PORT_0f, REMAP_PORT_1f, REMAP_PORT_2f, REMAP_PORT_3f}, 6685 {CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, 6686 REMAP_PORT_4f, REMAP_PORT_5f, REMAP_PORT_6f, REMAP_PORT_7f}, 6687 {CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r, 6688 REMAP_PORT_8f, REMAP_PORT_9f, REMAP_PORT_10f, REMAP_PORT_11f}, 6689 {CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r, 6690 REMAP_PORT_12f, REMAP_PORT_13f, REMAP_PORT_14f, REMAP_PORT_15f}, 6691 {CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r, 6692 REMAP_PORT_16f, REMAP_PORT_17f, REMAP_PORT_18f, REMAP_PORT_19f}, 6693 {CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r, 6694 REMAP_PORT_20f, REMAP_PORT_21f, REMAP_PORT_22f, REMAP_PORT_23f}, 6695 {CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r, 6696 REMAP_PORT_24f, REMAP_PORT_25f, REMAP_PORT_26f, REMAP_PORT_27f}, 6697 {CMIC_LEDUP1_PORT_ORDER_REMAP_28_31r, 6698 REMAP_PORT_28f, REMAP_PORT_29f, REMAP_PORT_30f, REMAP_PORT_31f}, 6699 {CMIC_LEDUP1_PORT_ORDER_REMAP_32_35r, 6700 REMAP_PORT_32f, REMAP_PORT_33f, REMAP_PORT_34f, REMAP_PORT_35f}, 6701 {CMIC_LEDUP1_PORT_ORDER_REMAP_36_39r, 6702 REMAP_PORT_36f, REMAP_PORT_37f, REMAP_PORT_38f, REMAP_PORT_39f}, 6703 {CMIC_LEDUP1_PORT_ORDER_REMAP_40_43r, 6704 REMAP_PORT_40f, REMAP_PORT_41f, REMAP_PORT_42f, REMAP_PORT_43f}, 6705 {CMIC_LEDUP1_PORT_ORDER_REMAP_44_47r, 6706 REMAP_PORT_44f, REMAP_PORT_45f, REMAP_PORT_46f, REMAP_PORT_47f}, 6707 {CMIC_LEDUP1_PORT_ORDER_REMAP_48_51r, 6708 REMAP_PORT_48f, REMAP_PORT_49f, REMAP_PORT_50f, REMAP_PORT_51f}, 6709 {CMIC_LEDUP1_PORT_ORDER_REMAP_52_55r, 6710 REMAP_PORT_52f, REMAP_PORT_53f, REMAP_PORT_54f, REMAP_PORT_55f}, 6711 {CMIC_LEDUP1_PORT_ORDER_REMAP_56_59r, 6712 REMAP_PORT_56f, REMAP_PORT_57f, REMAP_PORT_58f, REMAP_PORT_59f}, 6713 {CMIC_LEDUP1_PORT_ORDER_REMAP_60_63r, 6714 REMAP_PORT_60f, REMAP_PORT_61f, REMAP_PORT_62f, REMAP_PORT_63f} 6715 }; 6716 /* The LED scanning out order is 6717 * LED Chan1 (physical port view): 6718 * PGW_CL0(89->86) -> PGW_XL6(85->82) ->...-> PGW_XL0(61->58) 6719 * Remap to schan 1 (remap, -56 view) 6720 * PGW_CL0(33->30) -> PGW_XL6(29->26) ->...-> PGW_XL0(5->2) 6721 * LED Chan0: 6722 * PGW_GE1(42->57) -> PGW_GE0(26->41)-> PGW_GE8P2(18->25)-> 6723 * PGW_GE8P1(10->17)-> PGW_GE8P0(2->9) 6724 * If PM4x25 is ON, PGW_CL will output 4 bytes LED status to the LED chain. 6725 * If PM4x25 is OFF, PGW_CL will output 1 byte to the LED chain. 6726 * If PM4x10 is ON, PGW_XL will output 4 bytes LED status to the LED chain. 6727 * If PM4x10 is OFF, PGW_XL will output 1 byte to the LED chain. 6728 * PGW_GE will always output 16 bytes LED status to the LED chain. 6729 * PGW_GE8P will always output 8 bytes LED status to the LED chain. 6730 */ 6731 6732 SOC_IF_ERROR_RETURN(READ_PGW_CTRL_0r(unit, &rval)); 6733 disable_4x10 = soc_reg_field_get(unit, PGW_CTRL_0r, 6734 rval, SW_PM4X10_DISABLEf); 6735 disable_4x25 = soc_reg_field_get(unit, PGW_CTRL_0r, 6736 rval, SW_PM4X25_DISABLEf); 6737 /* LED Chan1 */ 6738 /* PGW_CL0 */ 6739 for (i = GH2_PGW_COUNT_CL - 1; i >= 0; i--) { 6740 if (disable_4x25 & (1 << i)) { 6741 /* For PGW_CL, shift out 1 byte if PM4x25 is disabled */ 6742 led_remap1[port1_cnt++] = 0; 6743 port_cnt++; 6744 } else { 6745 /* For PGW_CL, port 3 is shifted out first and port 0 is the last */ 6746 for (j = GH2_PORTS_PER_PGW_CL - 1; j >= 0; j--) { 6747 led_remap1[port1_cnt++] = 6748 GH2_FIRST_PORT_PGW_CL0 + GH2_PORTS_PER_PGW_CL * i + j; 6749 port_cnt++; 6750 } 6751 } 6752 } 6753 6754 /* PGW_XL6 -> PGW_XL0 */ 6755 for (i = GH2_PGW_COUNT_XL - 1; i >= 0; i--) { 6756 if (disable_4x10 & (1 << i)) { 6757 /* For PGW_XL, shift out 1 byte if PM4x10 is disabled */ 6758 led_remap1[port1_cnt++] = 0; 6759 port_cnt++; 6760 } else { 6761 /* For PGW_XL, port 3 is shifted out first and port 0 is the last */ 6762 for (j = GH2_PORTS_PER_PGW_XL - 1; j >= 0; j--) { 6763 led_remap1[port1_cnt++] = 6764 GH2_FIRST_PORT_PGW_XL0 + GH2_PORTS_PER_PGW_XL * i + j; 6765 port_cnt++; 6766 } 6767 } 6768 } 6769 6770 /* LED Chan0 */ 6771 /* PGW_GE1 -> PGW_GE0 */ 6772 for (i = GH2_PGW_COUNT_GE - 1; i >= 0; i--) { 6773 /* For PGW_GE, port 0 is shifted out first and port 15 is the last */ 6774 for (j = 0; j < GH2_PORTS_PER_PGW_GE; j++) { 6775 phy_p = GH2_FIRST_PORT_PGW_GE0 + GH2_PORTS_PER_PGW_GE * i + j; 6776 if (SOC_INFO(unit).port_p2l_mapping[phy_p] != -1) { 6777 led_remap0[port0_cnt++] = 6778 GH2_FIRST_PORT_PGW_GE0 + GH2_PORTS_PER_PGW_GE * i + j; 6779 } else { 6780 led_remap0[port0_cnt++] = 0; 6781 } 6782 port_cnt++; 6783 } 6784 } 6785 6786 /* PGW_GE8P2 -> PGW_GE8P0 */ 6787 for (i = GH2_PGW_COUNT_GE8P - 1; i >= 0; i--) { 6788 /* For PGW_GE8P, port 0 is shifted out first and port 7 is the last */ 6789 for (j = 0; j < GH2_PORTS_PER_PGW_GE8P; j++) { 6790 led_remap0[port0_cnt++] = 6791 GH2_FIRST_PORT_PGW_GE8P0 + GH2_PORTS_PER_PGW_GE8P * i + j; 6792 port_cnt++; 6793 } 6794 } 6795 6796 /* Setup CMIC_LEDUP0/1_PORT_ORDER_REMAP registers */ 6797 for (i = 0; i < sizeof(ledup0_remap_r) / sizeof(ledup0_remap_r[0]); i++) { 6798 port_idx = i * 4; 6799 pval0 = gh2_get_pval(led_remap0, port_idx, port_cnt); 6800 pval1 = gh2_get_pval(led_remap0, port_idx + 1, port_cnt); 6801 pval2 = gh2_get_pval(led_remap0, port_idx + 2, port_cnt); 6802 pval3 = gh2_get_pval(led_remap0, port_idx + 3, port_cnt); 6803 6804 rval = 0; 6805 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 6806 ledup0_remap_r[i].port0, pval0); 6807 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 6808 ledup0_remap_r[i].port1, pval1); 6809 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 6810 ledup0_remap_r[i].port2, pval2); 6811 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 6812 ledup0_remap_r[i].port3, pval3); 6813 6814 /* coverity[result_independent_of_operands] */ 6815 SOC_IF_ERROR_RETURN 6816 (soc_pci_write(unit, 6817 soc_reg_addr(unit, ledup0_remap_r[i].reg_addr, REG_PORT_ANY, 0), 6818 rval)); 6819 } 6820 6821 for (i = 0; i < sizeof(ledup1_remap_r) / sizeof(ledup1_remap_r[0]); i++) { 6822 port_idx = i * 4; 6823 pval0 = gh2_get_pval(led_remap1, port_idx, port_cnt); 6824 pval1 = gh2_get_pval(led_remap1, port_idx + 1, port_cnt); 6825 pval2 = gh2_get_pval(led_remap1, port_idx + 2, port_cnt); 6826 pval3 = gh2_get_pval(led_remap1, port_idx + 3, port_cnt); 6827 6828 rval = 0; 6829 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 6830 ledup1_remap_r[i].port0, pval0); 6831 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 6832 ledup1_remap_r[i].port1, pval1); 6833 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 6834 ledup1_remap_r[i].port2, pval2); 6835 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 6836 ledup1_remap_r[i].port3, pval3); 6837 6838 /* coverity[result_independent_of_operands] */ 6839 SOC_IF_ERROR_RETURN 6840 (soc_pci_write(unit, 6841 soc_reg_addr(unit, ledup1_remap_r[i].reg_addr, 6842 REG_PORT_ANY, 0), rval1)); 6843 } 6844 6845 /* Initialize the LEDuP0/LEDuP1 data ram */ 6846 rval = 0; 6847 for (i = 0; i < 256; i++) { 6848 /* coverity[result_independent_of_operands] */ 6849 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit, i, rval)); 6850 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_DATA_RAMr(unit, i, rval1)); 6851 } 6852 6853 return SOC_E_NONE; 6854 } 6855 6856 #define GH2R_PGW_COUNT_GE (2) 6857 #define GH2R_PORTS_PER_PGW_GE (16) 6858 #define GH2R_FIRST_PORT_PGW_GE0 (26) 6859 #define GH2R_FIRST_PORT_PGW_GE1 (42) 6860 #define GH2R_PGW_COUNT_XL (2) 6861 #define GH2R_PORTS_PER_PGW_XL (4) 6862 #define GH2R_FIRST_PORT_PGW_XL4 (18) 6863 #define GH2R_FIRST_PORT_PGW_XL5 (22) 6864 #define GH2R_FIRST_PORT_PGW_XL6 (26) 6865 #define GH2R_PGW_COUNT_CL (1) 6866 #define GH2R_PORTS_PER_PGW_CL (4) 6867 #define GH2R_FIRST_PORT_PGW_CL0 (30) 6868 6869 STATIC int 6870 soc_greyhound2_ledupr_init(int unit) 6871 { 6872 int i, j, pval0, pval1, pval2, pval3, port_idx; 6873 uint32 led_remap0[64] = {0}, led_remap1[64] = {0}; 6874 uint32 port_cnt0 = 0,port_cnt1 = 0, rval = 0, rval1 = 0; 6875 int phy_p; 6876 6877 struct led_remap_t { 6878 uint32 reg_addr; 6879 uint32 port0; 6880 uint32 port1; 6881 uint32 port2; 6882 uint32 port3; 6883 }; 6884 struct led_remap_t ledup0_remap_r[] = { 6885 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 6886 REMAP_PORT_0f, REMAP_PORT_1f, REMAP_PORT_2f, REMAP_PORT_3f}, 6887 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 6888 REMAP_PORT_4f, REMAP_PORT_5f, REMAP_PORT_6f, REMAP_PORT_7f}, 6889 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 6890 REMAP_PORT_8f, REMAP_PORT_9f, REMAP_PORT_10f, REMAP_PORT_11f}, 6891 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 6892 REMAP_PORT_12f, REMAP_PORT_13f, REMAP_PORT_14f, REMAP_PORT_15f}, 6893 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 6894 REMAP_PORT_16f, REMAP_PORT_17f, REMAP_PORT_18f, REMAP_PORT_19f}, 6895 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 6896 REMAP_PORT_20f, REMAP_PORT_21f, REMAP_PORT_22f, REMAP_PORT_23f}, 6897 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 6898 REMAP_PORT_24f, REMAP_PORT_25f, REMAP_PORT_26f, REMAP_PORT_27f}, 6899 {CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, 6900 REMAP_PORT_28f, REMAP_PORT_29f, REMAP_PORT_30f, REMAP_PORT_31f}, 6901 {CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, 6902 REMAP_PORT_32f, REMAP_PORT_33f, REMAP_PORT_34f, REMAP_PORT_35f}, 6903 {CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, 6904 REMAP_PORT_36f, REMAP_PORT_37f, REMAP_PORT_38f, REMAP_PORT_39f}, 6905 {CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, 6906 REMAP_PORT_40f, REMAP_PORT_41f, REMAP_PORT_42f, REMAP_PORT_43f}, 6907 {CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, 6908 REMAP_PORT_44f, REMAP_PORT_45f, REMAP_PORT_46f, REMAP_PORT_47f}, 6909 {CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, 6910 REMAP_PORT_48f, REMAP_PORT_49f, REMAP_PORT_50f, REMAP_PORT_51f}, 6911 {CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, 6912 REMAP_PORT_52f, REMAP_PORT_53f, REMAP_PORT_54f, REMAP_PORT_55f}, 6913 {CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, 6914 REMAP_PORT_56f, REMAP_PORT_57f, REMAP_PORT_58f, REMAP_PORT_59f}, 6915 {CMIC_LEDUP0_PORT_ORDER_REMAP_60_63r, 6916 REMAP_PORT_60f, REMAP_PORT_61f, REMAP_PORT_62f, REMAP_PORT_63f} 6917 }; 6918 6919 /* Greyhound2 has 2 LED chan for storing port number that is greater than 63 */ 6920 struct led_remap_t ledup1_remap_r[] = { 6921 {CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, 6922 REMAP_PORT_0f, REMAP_PORT_1f, REMAP_PORT_2f, REMAP_PORT_3f}, 6923 {CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, 6924 REMAP_PORT_4f, REMAP_PORT_5f, REMAP_PORT_6f, REMAP_PORT_7f}, 6925 {CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r, 6926 REMAP_PORT_8f, REMAP_PORT_9f, REMAP_PORT_10f, REMAP_PORT_11f}, 6927 {CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r, 6928 REMAP_PORT_12f, REMAP_PORT_13f, REMAP_PORT_14f, REMAP_PORT_15f}, 6929 {CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r, 6930 REMAP_PORT_16f, REMAP_PORT_17f, REMAP_PORT_18f, REMAP_PORT_19f}, 6931 {CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r, 6932 REMAP_PORT_20f, REMAP_PORT_21f, REMAP_PORT_22f, REMAP_PORT_23f}, 6933 {CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r, 6934 REMAP_PORT_24f, REMAP_PORT_25f, REMAP_PORT_26f, REMAP_PORT_27f}, 6935 {CMIC_LEDUP1_PORT_ORDER_REMAP_28_31r, 6936 REMAP_PORT_28f, REMAP_PORT_29f, REMAP_PORT_30f, REMAP_PORT_31f}, 6937 {CMIC_LEDUP1_PORT_ORDER_REMAP_32_35r, 6938 REMAP_PORT_32f, REMAP_PORT_33f, REMAP_PORT_34f, REMAP_PORT_35f}, 6939 {CMIC_LEDUP1_PORT_ORDER_REMAP_36_39r, 6940 REMAP_PORT_36f, REMAP_PORT_37f, REMAP_PORT_38f, REMAP_PORT_39f}, 6941 {CMIC_LEDUP1_PORT_ORDER_REMAP_40_43r, 6942 REMAP_PORT_40f, REMAP_PORT_41f, REMAP_PORT_42f, REMAP_PORT_43f}, 6943 {CMIC_LEDUP1_PORT_ORDER_REMAP_44_47r, 6944 REMAP_PORT_44f, REMAP_PORT_45f, REMAP_PORT_46f, REMAP_PORT_47f}, 6945 {CMIC_LEDUP1_PORT_ORDER_REMAP_48_51r, 6946 REMAP_PORT_48f, REMAP_PORT_49f, REMAP_PORT_50f, REMAP_PORT_51f}, 6947 {CMIC_LEDUP1_PORT_ORDER_REMAP_52_55r, 6948 REMAP_PORT_52f, REMAP_PORT_53f, REMAP_PORT_54f, REMAP_PORT_55f}, 6949 {CMIC_LEDUP1_PORT_ORDER_REMAP_56_59r, 6950 REMAP_PORT_56f, REMAP_PORT_57f, REMAP_PORT_58f, REMAP_PORT_59f}, 6951 {CMIC_LEDUP1_PORT_ORDER_REMAP_60_63r, 6952 REMAP_PORT_60f, REMAP_PORT_61f, REMAP_PORT_62f, REMAP_PORT_63f} 6953 }; 6954 /* The LED scanning out order is 6955 * LED Chan1 (physical port view): 6956 * PGW_CL0(89->86) -> PGW_XL6(85->82) -> PGW_XL5(81->78) -> PGW_XL4(77->74) 6957 * Remap to schan 1 (remap, -56 view) 6958 * PGW_CL0(33->30) -> PGW_XL6(29->26) -> PGW_XL5(25->22) -> PGW_XL4(21->18) 6959 * LED Chan0: 6960 * PGW_GE1(42->57) -> PGW_GE0(26->41) 6961 * PGW_CL will output 4 bytes LED status to the LED chain. 6962 * PGW_XL will output 4 bytes LED status to the LED chain. 6963 * PGW_GE will always output 16 bytes LED status to the LED chain. 6964 * PGW_GE8P will always output 8 bytes LED status to the LED chain. 6965 */ 6966 6967 6968 /* LED Chan1 */ 6969 /* PGW_CL0 */ 6970 for (j = GH2R_PORTS_PER_PGW_CL - 1; j >= 0; j--) { 6971 led_remap1[port_cnt1++] = GH2R_FIRST_PORT_PGW_CL0 + j; 6972 } 6973 /* PGW_XL6 */ 6974 for (j = GH2R_PORTS_PER_PGW_XL - 1; j >= 0; j--) { 6975 led_remap1[port_cnt1++] = 6976 GH2R_FIRST_PORT_PGW_XL6 + j; 6977 } 6978 /* PGW_XL5, LED output not used */ 6979 for (j = GH2R_PORTS_PER_PGW_XL - 1; j >= 0; j--) { 6980 led_remap1[port_cnt1++] = 6981 GH2R_FIRST_PORT_PGW_XL5 + j; 6982 } 6983 /* PGW_XL4 */ 6984 for (j = GH2R_PORTS_PER_PGW_XL - 1; j >= 0; j--) { 6985 led_remap1[port_cnt1++] = 6986 GH2R_FIRST_PORT_PGW_XL4 + j; 6987 } 6988 6989 /* LED Chan0 */ 6990 /* PGW_GE1 from 42-57 */ 6991 for (j = 0; j < GH2R_PORTS_PER_PGW_GE; j++) { 6992 phy_p = GH2R_FIRST_PORT_PGW_GE1 + j; 6993 if (SOC_INFO(unit).port_p2l_mapping[phy_p] != -1) { 6994 led_remap0[port_cnt0++] = GH2R_FIRST_PORT_PGW_GE1 + j; 6995 } else { 6996 led_remap0[port_cnt0++] = 0; 6997 } 6998 } 6999 /* PGW_GE0 from 26-41, evn though front panel only using 26-33 */ 7000 for (j = 0; j < GH2R_PORTS_PER_PGW_GE; j++) { 7001 phy_p = GH2R_FIRST_PORT_PGW_GE0 + j; 7002 if (SOC_INFO(unit).port_p2l_mapping[phy_p] != -1) { 7003 led_remap0[port_cnt0++] = GH2R_FIRST_PORT_PGW_GE0 + j; 7004 } else { 7005 led_remap0[port_cnt0++] = 0; 7006 } 7007 } 7008 7009 /* Setup CMIC_LEDUP0/1_PORT_ORDER_REMAP registers */ 7010 for (i = 0; i < sizeof(ledup0_remap_r) / sizeof(ledup0_remap_r[0]); i++) { 7011 port_idx = i * 4; 7012 pval0 = led_remap0[port_idx]; 7013 pval1 = led_remap0[port_idx + 1]; 7014 pval2 = led_remap0[port_idx + 2]; 7015 pval3 = led_remap0[port_idx + 3]; 7016 7017 rval = 0; 7018 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 7019 ledup0_remap_r[i].port0, pval0); 7020 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 7021 ledup0_remap_r[i].port1, pval1); 7022 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 7023 ledup0_remap_r[i].port2, pval2); 7024 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 7025 ledup0_remap_r[i].port3, pval3); 7026 7027 /* coverity[result_independent_of_operands] */ 7028 SOC_IF_ERROR_RETURN 7029 (soc_pci_write(unit, 7030 soc_reg_addr(unit, ledup0_remap_r[i].reg_addr, REG_PORT_ANY, 0), 7031 rval)); 7032 } 7033 7034 for (i = 0; i < sizeof(ledup1_remap_r) / sizeof(ledup1_remap_r[0]); i++) { 7035 port_idx = i * 4; 7036 pval0 = led_remap1[port_idx]; 7037 pval1 = led_remap1[port_idx + 1]; 7038 pval2 = led_remap1[port_idx + 2]; 7039 pval3 = led_remap1[port_idx + 3]; 7040 7041 7042 rval = 0; 7043 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 7044 ledup1_remap_r[i].port0, pval0); 7045 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 7046 ledup1_remap_r[i].port1, pval1); 7047 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 7048 ledup1_remap_r[i].port2, pval2); 7049 soc_reg_field_set(unit, ledup1_remap_r[i].reg_addr, &rval1, 7050 ledup1_remap_r[i].port3, pval3); 7051 7052 /* coverity[result_independent_of_operands] */ 7053 SOC_IF_ERROR_RETURN 7054 (soc_pci_write(unit, 7055 soc_reg_addr(unit, ledup1_remap_r[i].reg_addr, 7056 REG_PORT_ANY, 0), rval1)); 7057 } 7058 7059 /* Initialize the LEDuP0/LEDuP1 data ram */ 7060 rval = 0; 7061 rval1 = 0; 7062 for (i = 0; i < 256; i++) { 7063 /* coverity[result_independent_of_operands] */ 7064 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit, i, rval)); 7065 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_DATA_RAMr(unit, i, rval1)); 7066 } 7067 7068 return SOC_E_NONE; 7069 } 7070 7071 int 7072 soc_greyhound2_init_port_mapping(int unit) 7073 { 7074 soc_info_t *si; 7075 soc_mem_t mem; 7076 uint32 rval; 7077 ing_physical_to_logical_port_number_mapping_table_entry_t entry; 7078 int logical_port, phy_port, mmu_port; 7079 int num_port, num_phy_port; 7080 uint32 fval[3]; 7081 egr_tdm_port_map_entry_t egr_tdm_port_map_entry; 7082 int idx; 7083 int shift; 7084 int port, speed; 7085 7086 si = &SOC_INFO(unit); 7087 7088 /* Ingress physical to logical port mapping */ 7089 mem = ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLEm; 7090 num_phy_port = soc_mem_index_count(unit, mem); 7091 sal_memset(&entry, 0, sizeof(entry)); 7092 for (phy_port = 0; phy_port < num_phy_port; phy_port++) { 7093 logical_port = si->port_p2l_mapping[phy_port]; 7094 soc_mem_field32_set(unit, mem, &entry, LOGICAL_PORT_NUMBERf, 7095 logical_port == -1 ? 0x7f : logical_port); 7096 SOC_IF_ERROR_RETURN 7097 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, phy_port, &entry)); 7098 } 7099 num_port = soc_mem_index_count(unit, PORT_TABm); 7100 7101 /* Egress logical to physical port mapping */ 7102 for (logical_port = 0; logical_port < num_port; logical_port++) { 7103 phy_port = si->port_l2p_mapping[logical_port]; 7104 rval = 0; 7105 soc_reg_field_set(unit, EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr, 7106 &rval, PHYSICAL_PORT_NUMBERf, 7107 phy_port == -1 ? 0x7f : phy_port); 7108 SOC_IF_ERROR_RETURN 7109 (WRITE_EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr(unit, 7110 logical_port, 7111 rval)); 7112 } 7113 7114 /* EGR_TDM_PORT_MAPm */ 7115 sal_memset(&egr_tdm_port_map_entry, 0, sizeof(egr_tdm_port_map_entry)); 7116 sal_memset(fval, 0, sizeof(fval)); 7117 mem = EGR_TDM_PORT_MAPm; 7118 for (logical_port = 0; logical_port < num_port; logical_port++) { 7119 phy_port = si->port_l2p_mapping[logical_port]; 7120 /* 7121 * Physical port of loopback port(1) is assigned -1. 7122 * The port should be programmed on physical port 1. 7123 */ 7124 if (logical_port == 1) { 7125 phy_port = 1; 7126 } 7127 if (phy_port == -1) { 7128 /* skip not mapped physical port */ 7129 continue; 7130 } 7131 idx = phy_port / 32; 7132 shift = phy_port - idx * 32; 7133 fval[idx] |= (1 << shift); 7134 } 7135 soc_mem_field_set(unit, EGR_TDM_PORT_MAPm, 7136 (void *)&egr_tdm_port_map_entry, BITMAPf, fval); 7137 SOC_IF_ERROR_RETURN 7138 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, 0, &egr_tdm_port_map_entry)); 7139 7140 /* MMU to physical port mapping and MMU to logical port mapping */ 7141 for (mmu_port = 0; mmu_port < SOC_MAX_MMU_PORTS; mmu_port++) { 7142 /* MMU to Physical port */ 7143 phy_port = si->port_m2p_mapping[mmu_port]; 7144 /* Physical to Logical port */ 7145 logical_port = si->port_p2l_mapping[phy_port]; 7146 7147 if (phy_port == 1) { 7148 /* skip loopback port */ 7149 continue; 7150 } 7151 if (phy_port == -1) { 7152 /* skip not mapped mmu port */ 7153 continue; 7154 } 7155 rval = 0; 7156 soc_reg_field_set(unit, MMU_PORT_TO_PHY_PORT_MAPPINGr, &rval, 7157 PHY_PORTf, phy_port); 7158 SOC_IF_ERROR_RETURN 7159 (WRITE_MMU_PORT_TO_PHY_PORT_MAPPINGr(unit, logical_port, rval)); 7160 7161 if (logical_port == -1) { 7162 logical_port = 1; 7163 } 7164 rval = 0; 7165 soc_reg_field_set(unit, MMU_PORT_TO_LOGIC_PORT_MAPPINGr, &rval, 7166 LOGIC_PORTf, logical_port); 7167 SOC_IF_ERROR_RETURN 7168 (WRITE_MMU_PORT_TO_LOGIC_PORT_MAPPINGr(unit, logical_port, rval)); 7169 } 7170 #ifdef BCM_WARM_BOOT_SUPPORT 7171 if (SOC_WARM_BOOT(unit)) { 7172 SOC_IF_ERROR_RETURN( 7173 soc_gh2_port_init_speed_scache_recovery(unit)); 7174 } else { 7175 SOC_IF_ERROR_RETURN( 7176 soc_gh2_port_init_speed_scache_allocate(unit)); 7177 } 7178 #endif /* BCM_WARM_BOOT_SUPPORT */ 7179 7180 /* Initialize the si->port_init_speed */ 7181 PBMP_ALL_ITER(unit, port) { 7182 /* 7183 * Let the port_init_speed as the max supported speed of xe 7184 * while the port_speed_max would be the max supported speed of hg 7185 */ 7186 switch (si->port_speed_max[port]) { 7187 case 11000: 7188 speed = 10000; 7189 break; 7190 case 21000: 7191 speed = 20000; 7192 break; 7193 case 27000: 7194 speed = 25000; 7195 break; 7196 case 42000: 7197 speed = 40000; 7198 break; 7199 case 53000: 7200 speed = 50000; 7201 break; 7202 default: 7203 speed = si->port_speed_max[port]; 7204 break; 7205 } 7206 si->port_init_speed[port] = speed; 7207 if (!SOC_WARM_BOOT(unit)) { 7208 gh2_port_speed[si->port_l2p_mapping[port]] = speed; 7209 } 7210 } 7211 return SOC_E_NONE; 7212 } 7213 7214 /* Provide the max speed mapping from xe to hg */ 7215 int 7216 soc_greyhound2_port_hg_speed_get(int unit, soc_port_t port, int *speed) 7217 { 7218 soc_info_t *si; 7219 7220 si = &SOC_INFO(unit); 7221 7222 switch (si->port_init_speed[port]) { 7223 case 10000: 7224 *speed = 11000; 7225 break; 7226 case 20000: 7227 *speed = 21000; 7228 break; 7229 case 25000: 7230 *speed = 27000; 7231 break; 7232 case 40000: 7233 *speed = 42000; 7234 break; 7235 case 50000: 7236 *speed = 53000; 7237 break; 7238 default: 7239 *speed = si->port_init_speed[port]; 7240 break; 7241 } 7242 7243 if (*speed > si->port_speed_max[port]) { 7244 *speed = si->port_speed_max[port]; 7245 } 7246 return SOC_E_NONE; 7247 } 7248 7249 /* 7250 * Check if the configured port speed matched. 7251 * 7252 * return value 7253 * 1 : check passed 7254 * 0 : check failed 7255 */ 7256 static int 7257 flex_lane_speed_check(int speed, int flex_mode, int lane_count) 7258 { 7259 /* Check invalid lane count */ 7260 if ((lane_count < 1) || (lane_count > 4)) { 7261 return 0; 7262 } 7263 if (lane_count == 3) { 7264 return 0; 7265 } 7266 7267 if (flex_mode == FLEX_2P5) { 7268 if (lane_count == 1) { 7269 /* 1G, 2.5G */ 7270 if ((speed == 10) || (speed == 25)) { 7271 return 1; 7272 } 7273 } 7274 } else if (flex_mode == FLEX_10) { 7275 if (lane_count == 1) { 7276 /* 1G, 10G, 11G */ 7277 if ((speed == 10) || (speed == 100) || (speed == 110)) { 7278 return 1; 7279 } 7280 } 7281 } else if (flex_mode == FLEX_40) { 7282 if (lane_count == 1) { 7283 /* 1G, 2.5G, 5G, 10G, 11G */ 7284 if ((speed == 10) || (speed == 25) || (speed == 50) || \ 7285 (speed == 100) || (speed == 110)) { 7286 return 1; 7287 } 7288 } 7289 if (lane_count == 2) { 7290 /* 20G, 21G */ 7291 if ((speed == 200) || (speed == 210)) { 7292 return 1; 7293 } 7294 } 7295 if (lane_count == 4) { 7296 /* 40G, 42G, 21G */ 7297 if ((speed == 400) || (speed == 420) || (speed == 210)) { 7298 return 1; 7299 } 7300 } 7301 } else if (flex_mode == FLEX_50) { 7302 if (lane_count == 1) { 7303 /* 1G, 10G, 11G, 25G */ 7304 if ((speed == 10) || (speed == 100) || (speed == 110) || \ 7305 (speed == 250)) { 7306 return 1; 7307 } 7308 } 7309 if (lane_count == 2) { 7310 /* 20G, 21G, 50G, 53G */ 7311 if ((speed == 200) || (speed == 210) || (speed == 500) || \ 7312 (speed == 530)) { 7313 return 1; 7314 } 7315 } 7316 if (lane_count == 4) { 7317 /* 40G, 42G */ 7318 if ((speed == 400) || (speed == 420)) { 7319 return 1; 7320 } 7321 } 7322 } else if (flex_mode == FLEX_XAUI) { 7323 if (lane_count == 1) { 7324 /* 1G, 2.5G */ 7325 if ((speed == 10) || (speed == 25)) { 7326 return 1; 7327 } 7328 } 7329 if (lane_count == 2) { 7330 return 0; 7331 } 7332 if (lane_count == 4) { 7333 /* 10G */ 7334 if (speed == 100) { 7335 return 1; 7336 } 7337 } 7338 } else if (flex_mode == FLEX_20G_RIOT) { 7339 if (lane_count == 1) { 7340 /* 10G */ 7341 if (speed == 100) { 7342 return 1; 7343 } 7344 } 7345 if (lane_count == 4) { 7346 /* 40G */ 7347 if (speed == 400) { 7348 return 1; 7349 } 7350 } 7351 } else { 7352 return 0; 7353 } 7354 return 0; 7355 } 7356 7357 static int 7358 soc_gh2_flex2p5_checker(int unit, 7359 int cfg_match_id, 7360 int tsc_idx, 7361 int *port_ratio) 7362 { 7363 _gh2_option_info_t *matched_port_config = NULL; 7364 int *p2l_mapping, *speed_max; 7365 int rv = SOC_E_NONE; 7366 int ratio; 7367 7368 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7369 7370 p2l_mapping = matched_port_config->p2l_mapping; 7371 speed_max = matched_port_config->speed_max; 7372 7373 ratio = -1; 7374 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7375 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7376 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7377 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7378 7379 if (flex_lane_speed_check 7380 (speed_max[tsc_phy_port[tsc_idx]], FLEX_2P5, 1) && 7381 flex_lane_speed_check 7382 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_2P5, 1) && 7383 flex_lane_speed_check 7384 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_2P5, 1) && 7385 flex_lane_speed_check 7386 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_2P5, 1)) { 7387 ratio = SOC_GH2_PORT_RATIO_QUAD; 7388 } 7389 } 7390 7391 if ((p2l_mapping[tsc_phy_port[tsc_idx]] == -1) && 7392 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7393 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7394 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7395 /* No lanes enabled on the core, assign default value */ 7396 ratio = SOC_GH2_PORT_RATIO_QUAD; 7397 } 7398 7399 if ((ratio >= SOC_GH2_PORT_RATIO_SINGLE) && 7400 (ratio < SOC_GH2_PORT_RATIO_COUNT)) { 7401 *port_ratio = ratio; 7402 rv = SOC_E_NONE; 7403 } else { 7404 rv = SOC_E_FAIL; 7405 } 7406 return rv; 7407 } 7408 7409 static int 7410 soc_gh2_flex10_checker(int unit, 7411 int cfg_match_id, 7412 int tsc_idx, 7413 int *port_ratio) 7414 { 7415 _gh2_option_info_t *matched_port_config = NULL; 7416 int *p2l_mapping, *speed_max; 7417 int rv = SOC_E_NONE; 7418 int ratio; 7419 7420 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7421 7422 p2l_mapping = matched_port_config->p2l_mapping; 7423 speed_max = matched_port_config->speed_max; 7424 7425 ratio = -1; 7426 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7427 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7428 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7429 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7430 if (flex_lane_speed_check 7431 (speed_max[tsc_phy_port[tsc_idx]], FLEX_10, 1) && 7432 flex_lane_speed_check 7433 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_10, 1) && 7434 flex_lane_speed_check 7435 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_10, 1) && 7436 flex_lane_speed_check 7437 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_10, 1)) { 7438 ratio = SOC_GH2_PORT_RATIO_QUAD; 7439 } 7440 } 7441 7442 if ((p2l_mapping[tsc_phy_port[tsc_idx]] == -1) && 7443 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7444 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7445 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7446 /* No lanes enabled on the core, assign default value */ 7447 ratio = SOC_GH2_PORT_RATIO_QUAD; 7448 } 7449 7450 if ((ratio >= SOC_GH2_PORT_RATIO_SINGLE) && 7451 (ratio < SOC_GH2_PORT_RATIO_COUNT)) { 7452 *port_ratio = ratio; 7453 rv = SOC_E_NONE; 7454 } else { 7455 rv = SOC_E_FAIL; 7456 } 7457 return rv; 7458 } 7459 7460 static int 7461 soc_gh2_flex40_checker(int unit, 7462 int cfg_match_id, 7463 int tsc_idx, 7464 int *port_ratio) 7465 { 7466 _gh2_option_info_t *matched_port_config = NULL; 7467 int *p2l_mapping, *speed_max; 7468 int rv = SOC_E_NONE; 7469 int ratio; 7470 7471 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7472 7473 p2l_mapping = matched_port_config->p2l_mapping; 7474 speed_max = matched_port_config->speed_max; 7475 7476 ratio = -1; 7477 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7478 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7479 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7480 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7481 if (flex_lane_speed_check 7482 (speed_max[tsc_phy_port[tsc_idx]], FLEX_40, 1) && 7483 flex_lane_speed_check 7484 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_40, 1) && 7485 flex_lane_speed_check 7486 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_40, 1) && 7487 flex_lane_speed_check 7488 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_40, 1)) { 7489 ratio = SOC_GH2_PORT_RATIO_QUAD; 7490 } 7491 } 7492 7493 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7494 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7495 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7496 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7497 if (flex_lane_speed_check 7498 (speed_max[tsc_phy_port[tsc_idx]], FLEX_40, 2) && 7499 flex_lane_speed_check 7500 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_40, 1) && 7501 flex_lane_speed_check 7502 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_40, 1)) { 7503 ratio = SOC_GH2_PORT_RATIO_TRI_023; 7504 } 7505 } 7506 7507 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7508 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7509 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7510 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7511 if (flex_lane_speed_check 7512 (speed_max[tsc_phy_port[tsc_idx]], FLEX_40, 1) && 7513 flex_lane_speed_check 7514 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_40, 1) && 7515 flex_lane_speed_check 7516 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_40, 2)) { 7517 ratio = SOC_GH2_PORT_RATIO_TRI_012; 7518 } 7519 } 7520 7521 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7522 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7523 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7524 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7525 if (flex_lane_speed_check 7526 (speed_max[tsc_phy_port[tsc_idx]], FLEX_40, 2) && 7527 flex_lane_speed_check 7528 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_40, 2)) { 7529 ratio = SOC_GH2_PORT_RATIO_DUAL_2_2; 7530 } 7531 } 7532 7533 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7534 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7535 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7536 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7537 if (_GH2_TSC_TSCF0_IDX == tsc_idx) { 7538 if ((speed_max[tsc_phy_port[tsc_idx]] == 100) || \ 7539 (speed_max[tsc_phy_port[tsc_idx]] == 210)) { 7540 LOG_ERROR(BSL_LS_SOC_COMMON, 7541 (BSL_META_U(unit, 7542 "Quad lane mode with speed %dGbps " 7543 "is not supported on TSCF(TSC #7).\n"), 7544 speed_max[tsc_phy_port[tsc_idx]] / 10)); 7545 return SOC_E_CONFIG; 7546 } 7547 } 7548 7549 if (flex_lane_speed_check 7550 (speed_max[tsc_phy_port[tsc_idx]], FLEX_40, 4)) { 7551 ratio = SOC_GH2_PORT_RATIO_SINGLE; 7552 } 7553 /* Check if it is XAUI port */ 7554 if (flex_lane_speed_check 7555 (speed_max[tsc_phy_port[tsc_idx]], FLEX_XAUI, 4)) { 7556 ratio = SOC_GH2_PORT_RATIO_SINGLE_XAUI; 7557 } 7558 } 7559 7560 if ((p2l_mapping[tsc_phy_port[tsc_idx]] == -1) && 7561 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7562 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7563 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7564 /* No lanes enabled on the core, assign default value */ 7565 ratio = SOC_GH2_PORT_RATIO_QUAD; 7566 } 7567 7568 if ((ratio >= SOC_GH2_PORT_RATIO_SINGLE) && 7569 (ratio < SOC_GH2_PORT_RATIO_COUNT)) { 7570 *port_ratio = ratio; 7571 rv = SOC_E_NONE; 7572 } else { 7573 rv = SOC_E_FAIL; 7574 } 7575 return rv; 7576 } 7577 7578 static int 7579 soc_gh2_flex50_checker(int unit, 7580 int cfg_match_id, 7581 int tsc_idx, 7582 int *port_ratio) 7583 { 7584 _gh2_option_info_t *matched_port_config = NULL; 7585 int *p2l_mapping, *speed_max; 7586 int rv = SOC_E_NONE; 7587 int ratio; 7588 7589 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7590 7591 p2l_mapping = matched_port_config->p2l_mapping; 7592 speed_max = matched_port_config->speed_max; 7593 7594 ratio = -1; 7595 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7596 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7597 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7598 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7599 if (flex_lane_speed_check 7600 (speed_max[tsc_phy_port[tsc_idx]], FLEX_50, 1) && 7601 flex_lane_speed_check 7602 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_50, 1) && 7603 flex_lane_speed_check 7604 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_50, 1) && 7605 flex_lane_speed_check 7606 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_50, 1)) { 7607 ratio = SOC_GH2_PORT_RATIO_QUAD; 7608 } 7609 } 7610 7611 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7612 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7613 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7614 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7615 if (flex_lane_speed_check 7616 (speed_max[tsc_phy_port[tsc_idx]], FLEX_50, 2) && 7617 flex_lane_speed_check 7618 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_50, 1) && 7619 flex_lane_speed_check 7620 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_50, 1)) { 7621 ratio = SOC_GH2_PORT_RATIO_TRI_023; 7622 } 7623 } 7624 7625 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7626 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7627 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7628 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7629 if (flex_lane_speed_check 7630 (speed_max[tsc_phy_port[tsc_idx]], FLEX_50, 1) && 7631 flex_lane_speed_check 7632 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_50, 1) && 7633 flex_lane_speed_check 7634 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_50, 2)) { 7635 ratio = SOC_GH2_PORT_RATIO_TRI_012; 7636 } 7637 } 7638 7639 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7640 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7641 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7642 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7643 if (flex_lane_speed_check 7644 (speed_max[tsc_phy_port[tsc_idx]], FLEX_50, 2) && 7645 flex_lane_speed_check 7646 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_50, 2)) { 7647 ratio = SOC_GH2_PORT_RATIO_DUAL_2_2; 7648 } 7649 } 7650 7651 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7652 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7653 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7654 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7655 if (flex_lane_speed_check 7656 (speed_max[tsc_phy_port[tsc_idx]], FLEX_50, 4)) { 7657 ratio = SOC_GH2_PORT_RATIO_SINGLE; 7658 } 7659 } 7660 7661 if ((p2l_mapping[tsc_phy_port[tsc_idx]] == -1) && 7662 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7663 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7664 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7665 /* No lanes enabled on the core, assign default value */ 7666 ratio = SOC_GH2_PORT_RATIO_QUAD; 7667 } 7668 7669 if ((ratio >= SOC_GH2_PORT_RATIO_SINGLE) && 7670 (ratio < SOC_GH2_PORT_RATIO_COUNT)) { 7671 *port_ratio = ratio; 7672 rv = SOC_E_NONE; 7673 } else { 7674 rv = SOC_E_FAIL; 7675 } 7676 return rv; 7677 } 7678 7679 static int 7680 soc_gh2_flex_xaui_checker(int unit, 7681 int cfg_match_id, 7682 int tsc_idx, 7683 int *port_ratio) 7684 { 7685 _gh2_option_info_t *matched_port_config = NULL; 7686 int *p2l_mapping, *speed_max; 7687 int rv = SOC_E_NONE; 7688 int ratio; 7689 7690 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7691 7692 p2l_mapping = matched_port_config->p2l_mapping; 7693 speed_max = matched_port_config->speed_max; 7694 7695 ratio = -1; 7696 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7697 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7698 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7699 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7700 if (flex_lane_speed_check 7701 (speed_max[tsc_phy_port[tsc_idx]], FLEX_XAUI, 1) && 7702 flex_lane_speed_check 7703 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_XAUI, 1) && 7704 flex_lane_speed_check 7705 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_XAUI, 1) && 7706 flex_lane_speed_check 7707 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_XAUI, 1)) { 7708 ratio = SOC_GH2_PORT_RATIO_QUAD; 7709 } 7710 } 7711 7712 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7713 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7714 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7715 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7716 if (flex_lane_speed_check 7717 (speed_max[tsc_phy_port[tsc_idx]], FLEX_XAUI, 4)) { 7718 ratio = SOC_GH2_PORT_RATIO_SINGLE_XAUI; 7719 } 7720 } 7721 7722 if ((p2l_mapping[tsc_phy_port[tsc_idx]] == -1) && 7723 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7724 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7725 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7726 /* No lanes enabled on the core, assign default value */ 7727 ratio = SOC_GH2_PORT_RATIO_QUAD; 7728 } 7729 7730 if ((ratio >= SOC_GH2_PORT_RATIO_SINGLE) && 7731 (ratio < SOC_GH2_PORT_RATIO_COUNT)) { 7732 *port_ratio = ratio; 7733 rv = SOC_E_NONE; 7734 } else { 7735 rv = SOC_E_FAIL; 7736 } 7737 return rv; 7738 } 7739 7740 static int 7741 soc_gh2_flex20_riot_checker(int unit, 7742 int cfg_match_id, 7743 int tsc_idx, 7744 int *port_ratio) 7745 { 7746 _gh2_option_info_t *matched_port_config = NULL; 7747 int *p2l_mapping, *speed_max; 7748 int rv = SOC_E_NONE; 7749 int ratio; 7750 7751 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7752 7753 p2l_mapping = matched_port_config->p2l_mapping; 7754 speed_max = matched_port_config->speed_max; 7755 7756 ratio = -1; 7757 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7758 (p2l_mapping[tsc_phy_port[tsc_idx]+1] != -1) && 7759 (p2l_mapping[tsc_phy_port[tsc_idx]+2] != -1) && 7760 (p2l_mapping[tsc_phy_port[tsc_idx]+3] != -1)) { 7761 if (flex_lane_speed_check 7762 (speed_max[tsc_phy_port[tsc_idx]], FLEX_20G_RIOT, 1) && 7763 flex_lane_speed_check 7764 (speed_max[tsc_phy_port[tsc_idx] + 1], FLEX_20G_RIOT, 1) && 7765 flex_lane_speed_check 7766 (speed_max[tsc_phy_port[tsc_idx] + 2], FLEX_20G_RIOT, 1) && 7767 flex_lane_speed_check 7768 (speed_max[tsc_phy_port[tsc_idx] + 3], FLEX_20G_RIOT, 1)) { 7769 ratio = SOC_GH2_PORT_RATIO_QUAD; 7770 } 7771 } 7772 7773 if ((p2l_mapping[tsc_phy_port[tsc_idx]] != -1) && 7774 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7775 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7776 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7777 if (flex_lane_speed_check 7778 (speed_max[tsc_phy_port[tsc_idx]], FLEX_20G_RIOT, 4)) { 7779 ratio = SOC_GH2_PORT_RATIO_SINGLE; 7780 } 7781 } 7782 7783 if ((p2l_mapping[tsc_phy_port[tsc_idx]] == -1) && 7784 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7785 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7786 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7787 /* No lanes enabled on the core, assign default value */ 7788 ratio = SOC_GH2_PORT_RATIO_QUAD; 7789 } 7790 7791 if ((ratio >= SOC_GH2_PORT_RATIO_SINGLE) && 7792 (ratio < SOC_GH2_PORT_RATIO_COUNT)) { 7793 *port_ratio = ratio; 7794 rv = SOC_E_NONE; 7795 } else { 7796 rv = SOC_E_FAIL; 7797 } 7798 return rv; 7799 } 7800 7801 static int 7802 soc_gh2_flex_off_checker(int unit, 7803 int cfg_match_id, 7804 int tsc_idx, 7805 int *port_ratio) 7806 { 7807 _gh2_option_info_t *matched_port_config = NULL; 7808 int *p2l_mapping; 7809 int rv = SOC_E_NONE; 7810 int ratio; 7811 7812 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7813 7814 p2l_mapping = matched_port_config->p2l_mapping; 7815 7816 ratio = -1; 7817 if ((p2l_mapping[tsc_phy_port[tsc_idx]] == -1) && 7818 (p2l_mapping[tsc_phy_port[tsc_idx]+1] == -1) && 7819 (p2l_mapping[tsc_phy_port[tsc_idx]+2] == -1) && 7820 (p2l_mapping[tsc_phy_port[tsc_idx]+3] == -1)) { 7821 /* No lanes enabled on the core, assign default value */ 7822 ratio = SOC_GH2_PORT_RATIO_QUAD; 7823 } 7824 7825 if ((ratio >= SOC_GH2_PORT_RATIO_SINGLE) && 7826 (ratio < SOC_GH2_PORT_RATIO_COUNT)) { 7827 *port_ratio = ratio; 7828 rv = SOC_E_NONE; 7829 } else { 7830 rv = SOC_E_FAIL; 7831 } 7832 return rv; 7833 } 7834 7835 7836 /* 7837 * Check portmap configured data matches the flex mode. 7838 */ 7839 static int 7840 soc_gh2_port_cfg_checker(int unit, int cfg_match_id, int flex_mode_id) 7841 { 7842 /* 7843 * Validate each core 7844 * Check if p2l and speed matched flex port mode of the TSC core. 7845 * If matched, return the PORT_RATIO_TYPE 7846 * If not matched, put warning message and return error. 7847 */ 7848 _gh2_option_info_t *matched_port_config = NULL; 7849 _gh2_option_tsc_flex_mode_t *tsc_flex_modes = NULL; 7850 int rv = SOC_E_NONE; 7851 int i; 7852 int port_ratio = SOC_GH2_PORT_RATIO_QUAD; 7853 7854 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7855 tsc_flex_modes = &_gh2_option_tsc_flex_modes[flex_mode_id]; 7856 7857 for (i = 0; i < _GH2_MAX_TSC_COUNT; i++) { 7858 switch (tsc_flex_modes->mode[i]) { 7859 case FLEX_2P5: 7860 rv = soc_gh2_flex2p5_checker(unit, cfg_match_id, 7861 i, &port_ratio); 7862 break; 7863 case FLEX_10: 7864 rv = soc_gh2_flex10_checker(unit, cfg_match_id, 7865 i, &port_ratio); 7866 break; 7867 case FLEX_40: 7868 rv = soc_gh2_flex40_checker(unit, cfg_match_id, 7869 i, &port_ratio); 7870 break; 7871 case FLEX_50: 7872 rv = soc_gh2_flex50_checker(unit, cfg_match_id, 7873 i, &port_ratio); 7874 break; 7875 case FLEX_XAUI: 7876 rv = soc_gh2_flex_xaui_checker(unit, cfg_match_id, 7877 i, &port_ratio); 7878 break; 7879 case FLEX_20G_RIOT: 7880 rv = soc_gh2_flex20_riot_checker(unit, cfg_match_id, 7881 i, &port_ratio); 7882 break; 7883 case FLEX_OFF: 7884 rv = soc_gh2_flex_off_checker(unit, cfg_match_id, 7885 i, &port_ratio); 7886 break; 7887 default: 7888 LOG_WARN(BSL_LS_SOC_COMMON, 7889 (BSL_META_U(unit, "PORTMAP config is invalid " 7890 "on TSC #%d.\n"), i)); 7891 return SOC_E_FAIL; 7892 } 7893 if (rv != SOC_E_NONE) { 7894 LOG_WARN(BSL_LS_SOC_COMMON, 7895 (BSL_META_U(unit, "Incorrect PORTMAP config " 7896 "on TSC #%d.\n"), i)); 7897 return rv; 7898 } 7899 matched_port_config->default_port_ratio[i] = port_ratio; 7900 } 7901 7902 return rv; 7903 } 7904 7905 /* Update port cfg, p2l and speed, based on spn_PORTMAP */ 7906 static int 7907 soc_gh2_port_mapping_update(int unit, 7908 int cfg_match_id, 7909 int flex_mode_id, 7910 int *updated) 7911 { 7912 int lport; 7913 int pport; 7914 int port_bw; 7915 _gh2_option_info_t *matched_port_config = NULL; 7916 int rv = SOC_E_NONE; 7917 int renew; 7918 char *config_str; 7919 char *sub_str; 7920 char *sub_str_end; 7921 int portmap_qtc_port_cnt[2] = {0, 0}; 7922 int i; 7923 7924 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 7925 7926 renew = 0; 7927 /* Scan spn_PORTMAP and update to p2l_mapping and speed max tables */ 7928 for (lport = 2; lport < SOC_MAX_LOGICAL_PORTS; lport++) { 7929 config_str = soc_property_port_get_str(unit, lport, spn_PORTMAP); 7930 if (config_str == NULL) { 7931 continue; 7932 } 7933 7934 /* 7935 * portmap.<port>=<physical port number>:<bandwidth in Gb> 7936 */ 7937 sub_str = config_str; 7938 7939 /* Parsing physical port number */ 7940 pport = sal_ctoi(sub_str, &sub_str_end); 7941 if (sub_str == sub_str_end) { 7942 LOG_WARN(BSL_LS_SOC_COMMON, 7943 (BSL_META_U(unit, "Port %d: Missing physical port " 7944 "information \"%s\"\n"), 7945 lport, config_str)); 7946 rv = SOC_E_FAIL; 7947 continue; 7948 } 7949 if (pport < GH2_PORT_CFG_RENEW_PHY_PORT_MIN || \ 7950 pport > GH2_PORT_CFG_RENEW_PHY_PORT_MAX) { 7951 LOG_WARN(BSL_LS_SOC_COMMON, 7952 (BSL_META_U(unit, "Port %d: Invalid physical port " 7953 "number %d\n"), 7954 lport, pport)); 7955 rv = SOC_E_FAIL; 7956 continue; 7957 } 7958 7959 /* Skip ':' */ 7960 sub_str = sub_str_end; 7961 if (*sub_str != '\0') { 7962 if (*sub_str != ':') { 7963 LOG_WARN(BSL_LS_SOC_COMMON, 7964 (BSL_META_U(unit, "Port %d: Bad config " 7965 "string \"%s\"\n"), 7966 lport, config_str)); 7967 rv = SOC_E_FAIL; 7968 continue; 7969 } 7970 sub_str++; 7971 } 7972 7973 /* Parsing bandwidth */ 7974 port_bw = sal_ctoi(sub_str, &sub_str_end); 7975 if (sub_str == sub_str_end) { 7976 LOG_WARN(BSL_LS_SOC_COMMON, 7977 (BSL_META_U(unit, "Port %d: Missing bandwidth " 7978 "information \"%s\"\n"), 7979 lport, config_str)); 7980 rv = SOC_E_FAIL; 7981 continue; 7982 } 7983 7984 matched_port_config->p2l_mapping[pport] = lport; 7985 matched_port_config->speed_max[pport] = port_bw * 10; 7986 /* Special case for 2.5G config */ 7987 if (!sal_strcmp(sub_str, "2.5")) { 7988 matched_port_config->speed_max[pport] = 25; 7989 } 7990 7991 /* Count the number of qtc ports from config property. */ 7992 if ((pport >= qtc_phy_port[0]) && (pport <= (qtc_phy_port[0] + 15))) { 7993 portmap_qtc_port_cnt[0]++; 7994 } 7995 if ((pport >= qtc_phy_port[1]) && (pport <= (qtc_phy_port[1] + 15))) { 7996 portmap_qtc_port_cnt[1]++; 7997 } 7998 7999 if (!renew) { 8000 renew = 1; 8001 } 8002 } 8003 8004 for (i = 0; i < 2; i++) { 8005 if (portmap_qtc_port_cnt[i] != 0) { 8006 if (portmap_qtc_port_cnt[i] == 4) { 8007 /* SGMII mode. */ 8008 matched_port_config->qtc_default_mode[i] = \ 8009 _GH2_QTC_SERDES_DEFAULT_MODE_SGMII; 8010 } else if (portmap_qtc_port_cnt[i] == 16) { 8011 /* QSGMII mode. */ 8012 matched_port_config->qtc_default_mode[i] = \ 8013 _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII; 8014 } else { 8015 /* Error configuration. */ 8016 rv = SOC_E_CONFIG; 8017 break; 8018 } 8019 } 8020 } 8021 8022 *updated = renew; 8023 8024 return rv; 8025 } 8026 8027 STATIC 8028 void soc_gh2_port_user_config_update(int unit, int cfg_match_id) 8029 { 8030 int origin_p2l_mapping[SOC_MAX_PHY_PORTS]; 8031 int origin_speed_max[SOC_MAX_PHY_PORTS]; 8032 int rv = SOC_E_NONE; 8033 _gh2_option_info_t *matched_port_config = NULL; 8034 int i; 8035 int flex_mode_id = -1; 8036 int updated; 8037 char *port_ratio_str; 8038 int port_ratio; 8039 8040 matched_port_config = &_gh2_option_port_config[cfg_match_id]; 8041 8042 /* Get the default TSC flex modes */ 8043 for (i = 0; _gh2_option_tsc_flex_modes[i].config_op; i++) { 8044 if (!sal_strcmp(matched_port_config->config_op, 8045 _gh2_option_tsc_flex_modes[i].config_op)) { 8046 flex_mode_id = i; 8047 break; 8048 } 8049 } 8050 if (flex_mode_id == -1) { 8051 /* No matched entry found */ 8052 return; 8053 } 8054 8055 /* Save copy of port cfg templates */ 8056 sal_memcpy(origin_p2l_mapping, 8057 matched_port_config->p2l_mapping, 8058 SOC_MAX_PHY_PORTS * sizeof(int)); 8059 sal_memcpy(origin_speed_max, 8060 matched_port_config->speed_max, 8061 SOC_MAX_PHY_PORTS * sizeof(int)); 8062 8063 /* 8064 * Update flex port configuration (p2l mapping and speed) 8065 * based on spn_PORTMAP user config 8066 */ 8067 updated = 0; 8068 if (SOC_SUCCESS(rv)) { 8069 rv = soc_gh2_port_mapping_update(unit, cfg_match_id, flex_mode_id, 8070 &updated); 8071 } 8072 8073 /* If success, check p2l mapping and speed based on supported flex mode */ 8074 if (SOC_SUCCESS(rv) && updated) { 8075 rv = soc_gh2_port_cfg_checker(unit, cfg_match_id, flex_mode_id); 8076 } 8077 8078 /* Any failure, restore the port cfg templates */ 8079 if ((rv != SOC_E_NONE) || (!updated)){ 8080 sal_memcpy(matched_port_config->p2l_mapping, 8081 origin_p2l_mapping, 8082 SOC_MAX_PHY_PORTS * sizeof(int)); 8083 sal_memcpy(matched_port_config->speed_max, 8084 origin_speed_max, 8085 SOC_MAX_PHY_PORTS * sizeof(int)); 8086 if (rv != SOC_E_NONE) { 8087 LOG_WARN(BSL_LS_SOC_COMMON, 8088 (BSL_META_U(unit, "Option %s port config scan failed.\n"), 8089 matched_port_config->config_op)); 8090 } 8091 if (!updated) { 8092 LOG_WARN(BSL_LS_SOC_COMMON, 8093 (BSL_META_U(unit, "Option %s port config not updated.\n"), 8094 matched_port_config->config_op)); 8095 } 8096 } 8097 8098 /* Dump the final p2l mapping table */ 8099 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8100 (BSL_META_U(unit,"Physical to Logical port mapping : " 8101 "[P] L"))); 8102 for (i = 0; i < SOC_MAX_PHY_PORTS; i++) { 8103 if (!(i % 10)) { 8104 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8105 (BSL_META_U(unit,"\n"))); 8106 } 8107 if (matched_port_config->p2l_mapping[i] == -1) { 8108 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8109 (BSL_META_U(unit,"[%2d] "), i)); 8110 } else { 8111 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8112 (BSL_META_U(unit,"[%2d]%2d "), 8113 i, matched_port_config->p2l_mapping[i])); 8114 } 8115 } 8116 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8117 (BSL_META_U(unit,"\n"))); 8118 /* Dump the final port max speed table */ 8119 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8120 (BSL_META_U(unit,"Physical port max speed : " 8121 "[P] Speed(Gb)"))); 8122 for (i = 0; i < SOC_MAX_PHY_PORTS; i++) { 8123 if (!(i % 10)) { 8124 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8125 (BSL_META_U(unit,"\n"))); 8126 } 8127 if (matched_port_config->speed_max[i] == -1) { 8128 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8129 (BSL_META_U(unit,"[%2d] "), i)); 8130 } else if (matched_port_config->speed_max[i] == -1) { 8131 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8132 (BSL_META_U(unit,"[%2d]2.5"), i)); 8133 } else { 8134 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8135 (BSL_META_U(unit,"[%2d]%2d "), 8136 i, matched_port_config->speed_max[i] / 10)); 8137 } 8138 } 8139 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8140 (BSL_META_U(unit,"\n"))); 8141 /* Dump port ratio mode of each TSC */ 8142 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8143 (BSL_META_U(unit,"TSC (0~6: TSCE, 7: TSCF) " 8144 "port ratio mode :\n"))); 8145 for (i = 0; i < (_GH2_MAX_TSC_COUNT); i++) { 8146 port_ratio = matched_port_config->default_port_ratio[i]; 8147 if (port_ratio == SOC_GH2_PORT_RATIO_SINGLE) { 8148 port_ratio_str = "SINGLE"; 8149 } else if (port_ratio == SOC_GH2_PORT_RATIO_SINGLE_XAUI) { 8150 port_ratio_str = "XAUI"; 8151 } else if (port_ratio == SOC_GH2_PORT_RATIO_DUAL_2_2) { 8152 port_ratio_str = "DUAL"; 8153 } else if (port_ratio == SOC_GH2_PORT_RATIO_TRI_012) { 8154 port_ratio_str = "TRI 012"; 8155 } else if (port_ratio == SOC_GH2_PORT_RATIO_TRI_023) { 8156 port_ratio_str = "TRI 023"; 8157 } else if (port_ratio == SOC_GH2_PORT_RATIO_QUAD) { 8158 port_ratio_str = "QUAD"; 8159 } else { 8160 port_ratio_str = "INVALID"; 8161 } 8162 8163 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8164 (BSL_META_U(unit,"TSCE #%d port mode : %s\n"), 8165 i, port_ratio_str)); 8166 } 8167 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8168 (BSL_META_U(unit,"\n"))); 8169 } 8170 8171 8172 /* 8173 * GH2 port mapping 8174 * cpu port number is fixed: physical 0, logical 0, mmu 0 8175 */ 8176 int 8177 soc_greyhound2_port_config_init(int unit, uint16 dev_id) 8178 { 8179 8180 soc_info_t *si; 8181 int rv = SOC_E_NONE; 8182 int phy_port; 8183 int *p2l_mapping = 0, *speed_max = 0; 8184 char *option; 8185 int match = -1, i, j; 8186 int valid_sku_option; 8187 char *default_option_string = NULL; 8188 int p2l_mapping_override[SOC_MAX_PHY_PORTS]; 8189 int port_speed_max_override[SOC_MAX_PHY_PORTS]; 8190 int port_num_lanes[SOC_MAX_PHY_PORTS]; 8191 _gh2_option_info_t *matched_port_config = NULL; 8192 int freq = _GH2_53570_SYSTEM_FREQ; 8193 uint16 device_id; 8194 uint8 revision_id; 8195 8196 option = soc_property_get_str(unit, spn_INIT_PORT_CONFIG_OPTION); 8197 if (option == NULL) { 8198 /* Backward compatible */ 8199 option = soc_property_get_str(unit, "bcm53570_init_port_config"); 8200 } 8201 8202 if (option == NULL) { 8203 option = OPTION_1; 8204 } 8205 8206 8207 soc_cm_get_id(unit, &device_id, &revision_id); 8208 if (revision_id == BCM56170_A0_REV_ID) { 8209 _gh2_option_port_config = _gh2_a0_option_port_config; 8210 _gh2_sku_option_support_list = _gh2_a0_sku_option_support_list; 8211 } else { 8212 _gh2_option_port_config = _gh2_b0_option_port_config; 8213 _gh2_sku_option_support_list = _gh2_b0_sku_option_support_list; 8214 } 8215 8216 valid_sku_option = 0; 8217 for (i = 0; _gh2_sku_option_support_list[i].dev_id; i++) { 8218 if (dev_id == _gh2_sku_option_support_list[i].dev_id) { 8219 /* save the default option in case nothing matched later */ 8220 if ((default_option_string == NULL) && 8221 _gh2_sku_option_support_list[i].default_option) { 8222 default_option_string = 8223 _gh2_sku_option_support_list[i].option_string; 8224 } 8225 /* compare if the optoin is suppported in the SKU */ 8226 if (!sal_strcmp(_gh2_sku_option_support_list[i].option_string, 8227 option)) { 8228 valid_sku_option = 1; 8229 break; 8230 } 8231 } 8232 } 8233 if (!valid_sku_option && default_option_string) { 8234 LOG_WARN(BSL_LS_SOC_COMMON, 8235 (BSL_META_U(unit, 8236 "Warning: option %s " 8237 "is not supported in %s \n"), option, 8238 soc_dev_name(unit))); 8239 LOG_WARN(BSL_LS_SOC_COMMON, 8240 (BSL_META_U(unit, 8241 "Use default option %s " 8242 "instead\n"), default_option_string)); 8243 /* assign the default option if nothing matched */ 8244 option = default_option_string; 8245 } 8246 8247 for (i = 0; _gh2_option_port_config[i].config_op; i++) { 8248 if (!sal_strcmp(_gh2_option_port_config[i].config_op, option)) { 8249 match = i; 8250 break; 8251 } 8252 } 8253 8254 /* Flex port configuration update */ 8255 /* Only available for B0 */ 8256 if (revision_id != BCM56170_A0_REV_ID) { 8257 soc_gh2_port_user_config_update(unit, (match == -1) ? 0 : match); 8258 } 8259 8260 for (i = 0; i < _GH2_MAX_TSC_COUNT; i++) { 8261 _gh2_tsc[i].port_count = 0; 8262 _gh2_tsc[i].valid = 0; 8263 _gh2_tsc[i].phy_port_base = tsc_phy_port[i]; 8264 if (match == -1) { 8265 _gh2_tsc[i].port_count = 8266 _gh2_option_port_config[0].default_port_ratio[i]; 8267 } else { 8268 _gh2_tsc[i].port_count = 8269 _gh2_option_port_config[match].default_port_ratio[i]; 8270 } 8271 } 8272 8273 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 8274 p2l_mapping_override[phy_port] = 0; 8275 port_speed_max_override[phy_port] = 0; 8276 port_num_lanes[phy_port] = 1; 8277 gh2_port_speed[phy_port] = 0; 8278 } 8279 8280 if (match == -1) { 8281 /* take opton 1_0 as default config */ 8282 p2l_mapping = p2l_mapping_op1_0; 8283 speed_max = port_speed_max_op1_0; 8284 freq = _GH2_53570_SYSTEM_FREQ; 8285 LOG_WARN(BSL_LS_SOC_COMMON, 8286 (BSL_META_U(unit,"%s: no device_id matched\n"), FUNCTION_NAME())); 8287 } else { 8288 matched_option_idx = match; 8289 matched_port_config = &_gh2_option_port_config[match]; 8290 8291 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8292 (BSL_META_U(unit,"%s: option matched %s\n"), 8293 FUNCTION_NAME(), matched_port_config->config_op)); 8294 8295 p2l_mapping = matched_port_config->p2l_mapping; 8296 speed_max = matched_port_config->speed_max; 8297 freq = matched_port_config->freq; 8298 8299 /* Check QTC SGMII/QSGMII selection */ 8300 for (i = 0; i < _GH2_MAX_QTC_COUNT; i++) { 8301 _gh2_qtc_serdes_override[i] = _GH2_QTC_SERDES_OVERRDE_NONE; 8302 8303 if (matched_port_config->qtc_default_mode[i] == 8304 _GH2_QTC_SERDES_DEFAULT_MODE_SGMII) { 8305 _gh2_qtc_serdes_override[i] = _GH2_QTC_SERDES_OVERRDE_SGMII; 8306 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8307 (BSL_META_U(unit,"%s: QTC%1d is SGMII\n"), 8308 FUNCTION_NAME(), i)); 8309 } else if (matched_port_config->qtc_default_mode[i] == 8310 _GH2_QTC_SERDES_DEFAULT_MODE_QSGMII) { 8311 _gh2_qtc_serdes_override[i] = _GH2_QTC_SERDES_OVERRDE_QSGMII; 8312 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8313 (BSL_META_U(unit,"%s: QTC%1d is QSGMII\n"), 8314 FUNCTION_NAME(), i)); 8315 } else { 8316 _gh2_qtc_serdes_override[i] = _GH2_QTC_SERDES_OVERRDE_NONE; 8317 } 8318 } 8319 8320 /* QSGMII or SGMII selection */ 8321 for (i = 0; i < _GH2_MAX_QTC_COUNT; i++) { 8322 if (!((1 << i) & matched_port_config->disabled_qtc_bmp)) { 8323 /* Override to the SGMII port mapping and max speed */ 8324 if (_gh2_qtc_serdes_override[i] == 8325 _GH2_QTC_SERDES_OVERRDE_SGMII) { 8326 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8327 (BSL_META_U(unit,"%s: QTC%1d SGMII overrided.\n"), 8328 FUNCTION_NAME(), i)); 8329 if (matched_port_config->num_sgmii_supported[i] == 0) { 8330 LOG_ERROR(BSL_LS_SOC_COMMON, 8331 (BSL_META_U(unit, 8332 "Warning: QTC#%d SGMII mode " 8333 "is not supported in %s option %s.\n"), i, 8334 soc_dev_name(unit), 8335 matched_port_config->config_op)); 8336 return SOC_E_CONFIG; 8337 } 8338 /* Disable original qsgmii ports */ 8339 for (j = 0; 8340 j < matched_port_config->num_qsgmii_supported[i]; 8341 j++) { 8342 p2l_mapping_override[qtc_phy_port[i] + j * 4] = -1; 8343 p2l_mapping_override[qtc_phy_port[i] + j * 4 + 1] = -1; 8344 p2l_mapping_override[qtc_phy_port[i] + j * 4 + 2] = -1; 8345 p2l_mapping_override[qtc_phy_port[i] + j * 4 + 3] = -1; 8346 } 8347 for (j = 0; 8348 j < matched_port_config->num_sgmii_supported[i]; 8349 j++) { 8350 /* 8351 * Override sgmii port to max speed 8352 * option 10b: 1G 8353 * option 4a, 5, 8b: 2.5G 8354 * other options: keep the configured speed 8355 */ 8356 p2l_mapping_override[qtc_phy_port[i] + j] = 1; 8357 port_num_lanes[qtc_phy_port[i]+j] = 4; 8358 if (!sal_strcmp 8359 (matched_port_config->config_op, OPTION_10B_0) || \ 8360 !sal_strcmp 8361 (matched_port_config->config_op, OPTION_10B)) { 8362 port_speed_max_override[qtc_phy_port[i] + j] = 10; 8363 } else if (!sal_strcmp(matched_port_config->config_op, 8364 OPTION_4A) || \ 8365 !sal_strcmp(matched_port_config->config_op, 8366 OPTION_5) || \ 8367 !sal_strcmp(matched_port_config->config_op, 8368 OPTION_8B)) { 8369 port_speed_max_override[qtc_phy_port[i] + j] = 25; 8370 } else { 8371 port_speed_max_override[qtc_phy_port[i] + j] = \ 8372 speed_max[qtc_phy_port[i] + j]; 8373 } 8374 } 8375 } else if (_gh2_qtc_serdes_override[i] == 8376 _GH2_QTC_SERDES_OVERRDE_QSGMII) { 8377 if (matched_port_config->num_qsgmii_supported[i] == 0) { 8378 LOG_ERROR(BSL_LS_SOC_COMMON, 8379 (BSL_META_U(unit, 8380 "Warning: QTC#%d QSGMII mode " 8381 "is not supported in %s option %s.\n"), i, 8382 soc_dev_name(unit), 8383 matched_port_config->config_op)); 8384 /* 8385 * Defaul configuration is QSGMII except QSGMII 8386 * is not supported 8387 */ 8388 /* No need to override the mapping and max port speed */ 8389 return SOC_E_CONFIG; 8390 } 8391 } 8392 } 8393 } 8394 8395 } 8396 8397 si = &SOC_INFO(unit); 8398 8399 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 8400 if (p2l_mapping_override[phy_port] == -1) { 8401 si->port_p2l_mapping[phy_port] = p2l_mapping_override[phy_port]; 8402 /* Same as Egr P2L */ 8403 si->port_p2m_mapping[phy_port] = p2l_mapping_override[phy_port]; 8404 /* For COSQ programming */ 8405 si->max_port_p2m_mapping[phy_port] = p2l_mapping_override[phy_port]; 8406 } else { 8407 /* speed_max reflects the valid port */ 8408 /* 8409 * For the same TDM, the phy_port should be existed in 8410 * p2l_mapping table 8411 */ 8412 if ((speed_max[phy_port] == -1) && (phy_port != 0)) { 8413 si->port_p2l_mapping[phy_port] = -1; 8414 si->port_p2m_mapping[phy_port] = -1; 8415 si->max_port_p2m_mapping[phy_port] = -1; 8416 si->port_num_lanes[p2l_mapping[phy_port]] = -1; 8417 } else { 8418 si->port_p2l_mapping[phy_port] = p2l_mapping[phy_port]; 8419 si->port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 8420 si->max_port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 8421 si->port_num_lanes[p2l_mapping[phy_port]] = 1; 8422 } 8423 } 8424 if (port_speed_max_override[phy_port] != 0) { 8425 if (port_speed_max_override[phy_port] != -1) { 8426 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 8427 port_speed_max_override[phy_port] * 100; 8428 si->port_num_lanes[p2l_mapping[phy_port]] = 8429 port_num_lanes[phy_port]; 8430 } 8431 } else { 8432 if (speed_max[phy_port] != -1) { 8433 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 8434 speed_max[phy_port] * 100; 8435 } 8436 } 8437 } 8438 8439 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 8440 if (si->port_p2l_mapping[phy_port] != -1) { 8441 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8442 (BSL_META_U(unit,"%s: Port %d, lane number %d.\n"), 8443 FUNCTION_NAME(), si->port_p2l_mapping[phy_port], 8444 si->port_num_lanes[si->port_p2l_mapping[phy_port]])); 8445 } 8446 } 8447 8448 /* physical to mmu port mapping */ 8449 { 8450 int phy_port_cpu; 8451 int phy_port_loopback; 8452 int mmu_port_cpu; 8453 int mmu_port_loopback; 8454 int num_mmu_port = SOC_MAX_MMU_PORTS; 8455 int mmu_port_max; 8456 int mmu_port; 8457 8458 phy_port_cpu = 0; 8459 mmu_port_cpu = 0; 8460 phy_port_loopback = 1; 8461 mmu_port_loopback = 1; 8462 si->port_p2m_mapping[phy_port_cpu] = mmu_port_cpu; 8463 si->port_p2m_mapping[phy_port_loopback] = mmu_port_loopback; 8464 8465 mmu_port_max = num_mmu_port - 1; 8466 for (phy_port = (SOC_MAX_PHY_PORTS - 1); 8467 phy_port > phy_port_loopback; phy_port--) { 8468 if (si->port_p2l_mapping[phy_port] != -1) { 8469 si->port_p2m_mapping[phy_port] = mmu_port_max; 8470 mmu_port_max--; 8471 } 8472 } 8473 8474 /* 8475 * reset port_m2p_mapping, actual value is setup in 8476 * soc_info_config() later 8477 */ 8478 for (mmu_port = 0; mmu_port < num_mmu_port; mmu_port++) { 8479 si->port_m2p_mapping[mmu_port] = -1; 8480 } 8481 } 8482 8483 /* system core clock */ 8484 si->frequency = freq; 8485 8486 return rv; 8487 } 8488 8489 int 8490 _soc_greyhound2_autotdm_init(int unit) 8491 { 8492 soc_info_t *si = &SOC_INFO(unit); 8493 soc_port_schedule_state_t *port_schedule_state; 8494 soc_port_map_type_t *in_portmap; 8495 int port; 8496 int rv = SOC_E_NONE; 8497 8498 port_schedule_state = sal_alloc(sizeof(soc_port_schedule_state_t), 8499 "Greyhound2 soc_port_schedule_state_t"); 8500 if (port_schedule_state == NULL) { 8501 return SOC_E_MEMORY; 8502 } 8503 sal_memset(port_schedule_state, 0, sizeof(soc_port_schedule_state_t)); 8504 8505 /* Core clock frequency */ 8506 port_schedule_state->frequency = si->frequency; 8507 8508 /* Construct in_port_map */ 8509 in_portmap = &port_schedule_state->in_port_map; 8510 8511 PBMP_PORT_ITER(unit, port) { 8512 in_portmap->log_port_speed[port] = si->port_speed_max[port]; 8513 in_portmap->port_num_lanes[port] = si->port_num_lanes[port]; 8514 } 8515 8516 /* DV requires CPU port speed 1G */ 8517 port = 0; 8518 in_portmap->log_port_speed[port] = SPEED_1G; 8519 8520 sal_memcpy(in_portmap->port_p2l_mapping, si->port_p2l_mapping, 8521 sizeof(int) * SOC_MAX_PHY_PORTS); 8522 sal_memcpy(in_portmap->port_l2p_mapping, si->port_l2p_mapping, 8523 sizeof(int) * SOC_MAX_LOGICAL_PORTS); 8524 sal_memcpy(in_portmap->port_p2m_mapping, si->port_p2m_mapping, 8525 sizeof(int) * SOC_MAX_PHY_PORTS); 8526 sal_memcpy(in_portmap->port_m2p_mapping, si->port_m2p_mapping, 8527 sizeof(int) * SOC_MAX_MMU_PORTS); 8528 sal_memcpy(&in_portmap->physical_pbm, &si->physical_pbm, sizeof(pbmp_t)); 8529 sal_memcpy(&in_portmap->hg2_pbm, &si->hg.bitmap, sizeof(pbmp_t)); 8530 8531 rv = soc_gh2_tdm_init(unit, port_schedule_state); 8532 if (rv != SOC_E_NONE) { 8533 LOG_CLI((BSL_META_U(unit, 8534 "TDM calendar generation failed.\n"))); 8535 sal_free(port_schedule_state); 8536 return rv; 8537 } 8538 8539 sal_free(port_schedule_state); 8540 8541 return rv; 8542 } 8543 8544 int 8545 _soc_greyhound2_tdm_init(int unit, uint16 dev_id) 8546 { 8547 uint32 *arr = NULL; 8548 int tdm_size; 8549 uint32 rval; 8550 iarb_tdm_table_entry_t iarb_tdm; 8551 mmu_arb_tdm_table_entry_t mmu_arb_tdm; 8552 int i, port, phy_port; 8553 _gh2_option_info_t *matched_opt_info; 8554 soc_info_t *si; 8555 int flex_mode_id = -1; 8556 8557 if (matched_option_idx == -1) { 8558 LOG_WARN(BSL_LS_SOC_COMMON, 8559 (BSL_META_U(unit, "Warning: soc_greyhound2_port_config_init should " 8560 "be invoked first! Choose bcm53570 port config.\n"))); 8561 matched_option_idx = 0; 8562 } 8563 matched_opt_info = &_gh2_option_port_config[matched_option_idx]; 8564 8565 /* Check if AutoTDM available on the option */ 8566 for (i = 0; _gh2_option_tsc_flex_modes[i].config_op; i++) { 8567 if (!sal_strcmp(matched_opt_info->config_op, 8568 _gh2_option_tsc_flex_modes[i].config_op)) { 8569 flex_mode_id = i; 8570 break; 8571 } 8572 } 8573 if (flex_mode_id != -1) { 8574 /* Apply AutoTDM */ 8575 return _soc_greyhound2_autotdm_init(unit); 8576 } 8577 8578 si = &SOC_INFO(unit); 8579 8580 8581 8582 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 8583 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 8584 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 83); 8585 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 8586 8587 arr = matched_opt_info->tdm_table; 8588 tdm_size = matched_opt_info->tdm_table_size; 8589 8590 if (arr == NULL) { 8591 return SOC_E_CONFIG; 8592 } 8593 8594 for (i = 0; i < tdm_size; i++) { 8595 phy_port = arr[i]; 8596 port = (phy_port != 127) ? si->port_p2m_mapping[phy_port] : 127; 8597 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 8598 sal_memset(&mmu_arb_tdm, 0, sizeof(mmu_arb_tdm_table_entry_t)); 8599 8600 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 8601 phy_port); 8602 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, PORT_NUMf, 8603 port); 8604 8605 if (i == tdm_size - 1) { 8606 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, WRAP_ENf, 1); 8607 } 8608 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 8609 &iarb_tdm)); 8610 SOC_IF_ERROR_RETURN(WRITE_MMU_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 8611 &mmu_arb_tdm)); 8612 } 8613 rval = 0; 8614 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 8615 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 8616 tdm_size -1); 8617 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 8618 8619 return SOC_E_NONE; 8620 } 8621 8622 STATIC int ceiling_func(uint32 numerators, uint32 denominator) 8623 { 8624 uint32 result; 8625 if (denominator == 0) { 8626 return 0xFFFFFFFF; 8627 } 8628 result = numerators / denominator; 8629 if (numerators % denominator != 0) { 8630 result++; 8631 } 8632 return result; 8633 } 8634 8635 8636 STATIC int _soc_greyhound2_mmu_init_helper_lossy(int unit) 8637 { 8638 uint32 rval; 8639 int port, phy_port; 8640 int index; 8641 soc_info_t *si = &SOC_INFO(unit); 8642 soc_pbmp_t pbmp_cpu; 8643 soc_pbmp_t pbmp_uplink; 8644 soc_pbmp_t pbmp_downlink_1g; 8645 soc_pbmp_t pbmp_downlink_2dot5g; 8646 8647 static int standard_jumbo_frame; 8648 static int cell_size; 8649 static int ethernet_mtu_cell; 8650 static int standard_jumbo_frame_cell; 8651 static int total_physical_memory; 8652 static int total_cell_memory_for_admission; 8653 static int number_of_used_memory_banks; 8654 static int reserved_for_cfap; 8655 static int skidmarker; 8656 static int prefetch; 8657 static int total_cell_memory; 8658 static int cfapfullsetpoint; 8659 static int total_advertised_cell_memory; 8660 static int number_of_uplink_ports; 8661 static int number_of_downlink_ports; 8662 static int queue_port_limit_ratio; 8663 static int egress_queue_min_reserve_uplink_ports_lossy; 8664 static int egress_queue_min_reserve_downlink_ports_lossy; 8665 static int egress_queue_min_reserve_uplink_ports_lossless; 8666 static int egress_queue_min_reserve_downlink_ports_lossless; 8667 static int egress_queue_min_reserve_cpu_ports; 8668 static int egress_xq_min_reserve_lossy_ports; 8669 static int egress_xq_min_reserve_lossless_uplink_ports; 8670 static int egress_xq_min_reserve_lossless_downlink_ports; 8671 static int num_active_pri_group_lossless; 8672 static int num_lossy_queues; 8673 static int mmu_xoff_pkt_threshold_uplink_ports; 8674 static int mmu_xoff_pkt_threshold_downlink_ports; 8675 static int mmu_xoff_cell_threshold_1g_port_downlink_ports; 8676 static int mmu_xoff_cell_threshold_2dot5g_port_downlink_ports; 8677 static int mmu_xoff_cell_threshold_all_uplink_ports; 8678 static int num_cpu_queues; 8679 static int num_cpu_ports; 8680 static int numxqs_per_uplink_ports; 8681 static int numxqs_per_downlink_ports_and_cpu_port; 8682 static int headroom_for_1g_port; 8683 static int headroom_for_2dot5g_port; 8684 static int xoff_cell_thresholds_per_port_1g_port_downlink_ports; 8685 static int xoff_cell_thresholds_per_port_2dot5g_downlink_ports; 8686 static int xoff_cell_threshold_all_uplink_ports; 8687 static int xoff_packet_thresholds_per_port_uplink_port; 8688 static int xoff_packet_thresholds_per_port_downlink_port; 8689 static int discard_limit_per_port_pg_uplink_1g_port; 8690 static int discard_limit_per_port_pg_uplink_2dot5g_port; 8691 static int discard_limit_per_port_pg_downlink_port; 8692 static int total_reserved_cells_for_uplink_ports; 8693 static int total_reserved_cells_for_downlink_ports; 8694 static int total_reserved_cells_for_cpu_port; 8695 static int total_reserved; 8696 static int shared_space_cells; 8697 static int reserved_xqs_per_uplink_port; 8698 static int shared_xqs_per_uplink_port; 8699 static int reserved_xqs_per_downlink_port; 8700 static int shared_xqs_per_downlink_port; 8701 static int cfapfullthreshold_cfapfullsetpoint_up; 8702 static int gbllimitsetlimit_gblcellsetlimit_up; 8703 static int totaldyncellsetlimit_totaldyncellsetlimit_up; 8704 static int holcosminxqcnt_qlayer8_holcosminxqcnt_up; 8705 static int holcospktsetlimit0_pktsetlimit_up; 8706 static int holcospktsetlimit7_pktsetlimit_up; 8707 static int holcospktsetlimit_qlayer0_pktsetlimit_up; 8708 static int holcospktsetlimit_qlayer7_pktsetlimit_up; 8709 static int holcospktsetlimit_qlayer8_pktsetlimit_up; 8710 static int dynxqcntport_dynxqcntport_up; 8711 static int lwmcoscellsetlimit0_cellsetlimit_up; 8712 static int lwmcoscellsetlimit7_cellsetlimit_up; 8713 static int lwmcoscellsetlimit_qlayer0_cellsetlimit_up; 8714 static int lwmcoscellsetlimit_qlayer7_cellsetlimit_up; 8715 static int lwmcoscellsetlimit_qlayer8_cellsetlimit_up; 8716 static int holcoscellmaxlimit0_cellmaxlimit_up; 8717 static int holcoscellmaxlimit7_cellmaxlimit_up; 8718 static int holcoscellmaxlimit_qlayer0_cellmaxlimit_up; 8719 static int holcoscellmaxlimit_qlayer7_cellmaxlimit_up; 8720 static int holcoscellmaxlimit_qlayer8_cellmaxlimit_up; 8721 static int dyncelllimit_dyncellsetlimit_up; 8722 static int holcospktsetlimit_qgroup0_pktsetlimit_up; 8723 static int holcoscellmaxlimit_qgroup0_cellmaxlimit_up; 8724 static int holcosminxqcnt_qlayer8_holcosminxqcnt_down_1; 8725 static int holcospktsetlimit0_pktsetlimit_down_1; 8726 static int holcospktsetlimit7_pktsetlimit_down_1; 8727 static int holcospktsetlimit_qlayer0_pktsetlimit_down_1; 8728 static int holcospktsetlimit_qlayer7_pktsetlimit_down_1; 8729 static int holcospktsetlimit_qlayer8_pktsetlimit_down_1; 8730 static int dynxqcntport_dynxqcntport_down_1; 8731 static int lwmcoscellsetlimit0_cellsetlimit_down_1; 8732 static int lwmcoscellsetlimit7_cellsetlimit_down_1; 8733 static int lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1; 8734 static int lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1; 8735 static int lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1; 8736 static int holcoscellmaxlimit0_cellmaxlimit_down_1; 8737 static int holcoscellmaxlimit7_cellmaxlimit_down_1; 8738 static int holcoscellmaxlimit_qlayer0_cellmaxlimit_down_1; 8739 static int holcoscellmaxlimit_qlayer7_cellmaxlimit_down_1; 8740 static int holcoscellmaxlimit_qlayer8_cellmaxlimit_down_1; 8741 static int dyncelllimit_dyncellsetlimit_down_1; 8742 static int holcospktsetlimit_qgroup0_pktsetlimit_down_1; 8743 static int holcoscellmaxlimit_qgroup0_cellmaxlimit_down_1; 8744 static int holcospktsetlimit0_pktsetlimit_down_2dot5; 8745 static int holcospktsetlimit7_pktsetlimit_down_2dot5; 8746 static int holcospktsetlimit_qlayer0_pktsetlimit_down_2dot5; 8747 static int holcospktsetlimit_qlayer7_pktsetlimit_down_2dot5; 8748 static int holcospktsetlimit_qlayer8_pktsetlimit_down_2dot5; 8749 static int dynxqcntport_dynxqcntport_down_2dot5; 8750 static int lwmcoscellsetlimit0_cellsetlimit_down_2dot5; 8751 static int lwmcoscellsetlimit7_cellsetlimit_down_2dot5; 8752 static int lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5; 8753 static int lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5; 8754 static int lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5; 8755 static int holcoscellmaxlimit0_cellmaxlimit_down_2dot5; 8756 static int holcoscellmaxlimit7_cellmaxlimit_down_2dot5; 8757 static int holcoscellmaxlimit_qlayer0_cellmaxlimit_down_2dot5; 8758 static int holcoscellmaxlimit_qlayer7_cellmaxlimit_down_2dot5; 8759 static int holcoscellmaxlimit_qlayer8_cellmaxlimit_down_2dot5; 8760 static int dyncelllimit_dyncellsetlimit_down_2dot5; 8761 static int holcospktsetlimit_qgroup0_pktsetlimit_down_2dot5; 8762 static int holcoscellmaxlimit_qgroup0_cellmaxlimit_down_2dot5; 8763 static int holcosminxqcnt0_holcosminxqcnt_cpu; 8764 static int holcosminxqcnt7_holcosminxqcnt_cpu; 8765 static int holcospktsetlimit0_pktsetlimit_cpu; 8766 static int holcospktsetlimit7_pktsetlimit_cpu; 8767 static int dynxqcntport_dynxqcntport_cpu; 8768 static int lwmcoscellsetlimit0_cellsetlimit_cpu; 8769 static int lwmcoscellsetlimit7_cellsetlimit_cpu; 8770 static int holcoscellmaxlimit0_cellmaxlimit_cpu; 8771 static int holcoscellmaxlimit7_cellmaxlimit_cpu; 8772 static int dyncelllimit_dyncellsetlimit_cpu; 8773 uint16 dev_id; 8774 uint8 rev_id; 8775 8776 soc_cm_get_id(unit, &dev_id, &rev_id); 8777 8778 /* setup port bitmap according the port max speed for lossy 8779 * TSC/TSCF : uplink port 8780 * QGMII/SGMII : donnlink port 8781 */ 8782 num_cpu_ports = 0; 8783 number_of_uplink_ports = 0; 8784 number_of_downlink_ports = 0; 8785 SOC_PBMP_CLEAR(pbmp_cpu); 8786 SOC_PBMP_CLEAR(pbmp_uplink); 8787 SOC_PBMP_CLEAR(pbmp_downlink_1g); 8788 SOC_PBMP_CLEAR(pbmp_downlink_2dot5g); 8789 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 8790 port = si->port_p2l_mapping[phy_port]; 8791 if (port < 0) { 8792 continue; /* this user port has not been mapping in this sku */ 8793 } else if (!SOC_PBMP_MEMBER(PBMP_ALL(unit), port)) { 8794 continue; /* this user port has been masked out by pbmp_valid */ 8795 } 8796 if (IS_XL_PORT(unit, port) || IS_CL_PORT(unit, port)) { 8797 number_of_uplink_ports++; 8798 SOC_PBMP_PORT_ADD(pbmp_uplink, port); 8799 } else if (IS_GE_PORT(unit, port)) { 8800 number_of_downlink_ports++; 8801 if (SOC_INFO(unit).port_speed_max[port] > 1000) { 8802 SOC_PBMP_PORT_ADD(pbmp_downlink_2dot5g, port); 8803 } else { 8804 SOC_PBMP_PORT_ADD(pbmp_downlink_1g, port); 8805 } 8806 } else if (IS_CPU_PORT(unit, port)) { 8807 num_cpu_ports++; 8808 SOC_PBMP_PORT_ADD(pbmp_cpu, port); 8809 } 8810 } 8811 8812 standard_jumbo_frame = 9216; 8813 cell_size = 144; 8814 ethernet_mtu_cell = ceiling_func(15 * 1024 / 10, cell_size); 8815 standard_jumbo_frame_cell = ceiling_func(standard_jumbo_frame, cell_size); 8816 if (rev_id == BCM56170_B0_REV_ID) { 8817 total_physical_memory = 32 * 1024; 8818 } else { 8819 total_physical_memory = 24 * 1024; 8820 } 8821 total_cell_memory_for_admission = 225 * 1024 / 10; 8822 number_of_used_memory_banks = 8; 8823 reserved_for_cfap = (65) * 2 + number_of_used_memory_banks * 4; 8824 skidmarker = 7; 8825 prefetch = 64 + 4; 8826 total_cell_memory = total_cell_memory_for_admission; 8827 cfapfullsetpoint = total_physical_memory - reserved_for_cfap; 8828 total_advertised_cell_memory = total_cell_memory; 8829 queue_port_limit_ratio = 8; 8830 egress_queue_min_reserve_uplink_ports_lossy = ethernet_mtu_cell; 8831 egress_queue_min_reserve_downlink_ports_lossy = ethernet_mtu_cell; 8832 egress_queue_min_reserve_uplink_ports_lossless = 0; 8833 egress_queue_min_reserve_downlink_ports_lossless = 0; 8834 egress_queue_min_reserve_cpu_ports = ethernet_mtu_cell; 8835 egress_xq_min_reserve_lossy_ports 8836 = ethernet_mtu_cell; 8837 egress_xq_min_reserve_lossless_uplink_ports = 0; 8838 egress_xq_min_reserve_lossless_downlink_ports = 0; 8839 num_active_pri_group_lossless = 0; 8840 num_lossy_queues = 8; 8841 mmu_xoff_pkt_threshold_uplink_ports = total_advertised_cell_memory; 8842 mmu_xoff_pkt_threshold_downlink_ports = total_advertised_cell_memory; 8843 mmu_xoff_cell_threshold_1g_port_downlink_ports 8844 = total_advertised_cell_memory; 8845 mmu_xoff_cell_threshold_2dot5g_port_downlink_ports 8846 = total_advertised_cell_memory; 8847 mmu_xoff_cell_threshold_all_uplink_ports = total_advertised_cell_memory; 8848 num_cpu_queues = 8; 8849 num_cpu_ports = 1; 8850 numxqs_per_uplink_ports = 6 * 1024; 8851 numxqs_per_downlink_ports_and_cpu_port = 2 * 1024; 8852 headroom_for_1g_port = 0; 8853 headroom_for_2dot5g_port = 0; 8854 xoff_cell_thresholds_per_port_1g_port_downlink_ports 8855 = mmu_xoff_cell_threshold_1g_port_downlink_ports; 8856 xoff_cell_thresholds_per_port_2dot5g_downlink_ports 8857 = mmu_xoff_cell_threshold_2dot5g_port_downlink_ports; 8858 xoff_cell_threshold_all_uplink_ports 8859 = mmu_xoff_cell_threshold_all_uplink_ports; 8860 xoff_packet_thresholds_per_port_uplink_port 8861 = mmu_xoff_pkt_threshold_uplink_ports; 8862 xoff_packet_thresholds_per_port_downlink_port 8863 = mmu_xoff_pkt_threshold_downlink_ports; 8864 discard_limit_per_port_pg_uplink_1g_port 8865 = xoff_cell_thresholds_per_port_1g_port_downlink_ports 8866 + headroom_for_1g_port; 8867 discard_limit_per_port_pg_uplink_2dot5g_port 8868 = xoff_cell_thresholds_per_port_2dot5g_downlink_ports 8869 + headroom_for_2dot5g_port; 8870 discard_limit_per_port_pg_downlink_port = total_advertised_cell_memory; 8871 total_reserved_cells_for_uplink_ports 8872 = egress_queue_min_reserve_uplink_ports_lossy 8873 * number_of_uplink_ports * num_lossy_queues 8874 + number_of_uplink_ports 8875 * egress_queue_min_reserve_uplink_ports_lossless 8876 * num_active_pri_group_lossless; 8877 total_reserved_cells_for_downlink_ports 8878 = number_of_downlink_ports 8879 * egress_queue_min_reserve_downlink_ports_lossy 8880 * (num_lossy_queues) + number_of_downlink_ports 8881 * egress_queue_min_reserve_downlink_ports_lossless 8882 * num_active_pri_group_lossless; 8883 total_reserved_cells_for_cpu_port 8884 = num_cpu_ports * egress_queue_min_reserve_cpu_ports 8885 * num_cpu_queues; 8886 total_reserved 8887 = total_reserved_cells_for_uplink_ports 8888 + total_reserved_cells_for_downlink_ports 8889 + total_reserved_cells_for_cpu_port; 8890 shared_space_cells = total_advertised_cell_memory - total_reserved; 8891 reserved_xqs_per_uplink_port 8892 = egress_xq_min_reserve_lossy_ports 8893 * num_lossy_queues + egress_xq_min_reserve_lossless_uplink_ports 8894 * num_active_pri_group_lossless; 8895 shared_xqs_per_uplink_port 8896 = numxqs_per_uplink_ports - reserved_xqs_per_uplink_port; 8897 reserved_xqs_per_downlink_port 8898 = egress_xq_min_reserve_lossy_ports 8899 * num_lossy_queues + egress_xq_min_reserve_lossless_downlink_ports 8900 * num_active_pri_group_lossless; 8901 shared_xqs_per_downlink_port 8902 = numxqs_per_downlink_ports_and_cpu_port 8903 - reserved_xqs_per_downlink_port; 8904 cfapfullthreshold_cfapfullsetpoint_up = cfapfullsetpoint; 8905 gbllimitsetlimit_gblcellsetlimit_up = total_cell_memory_for_admission; 8906 totaldyncellsetlimit_totaldyncellsetlimit_up = shared_space_cells; 8907 holcosminxqcnt_qlayer8_holcosminxqcnt_up = 0; 8908 holcospktsetlimit0_pktsetlimit_up 8909 = shared_xqs_per_uplink_port 8910 + egress_xq_min_reserve_lossy_ports; 8911 holcospktsetlimit7_pktsetlimit_up 8912 = shared_xqs_per_uplink_port 8913 + egress_xq_min_reserve_lossy_ports; 8914 holcospktsetlimit_qlayer0_pktsetlimit_up 8915 = shared_xqs_per_uplink_port 8916 + egress_xq_min_reserve_lossy_ports; 8917 holcospktsetlimit_qlayer7_pktsetlimit_up 8918 = shared_xqs_per_uplink_port 8919 + egress_xq_min_reserve_lossy_ports; 8920 holcospktsetlimit_qlayer8_pktsetlimit_up 8921 = shared_xqs_per_uplink_port 8922 + holcosminxqcnt_qlayer8_holcosminxqcnt_up; 8923 dynxqcntport_dynxqcntport_up 8924 = shared_xqs_per_uplink_port - skidmarker - prefetch; 8925 lwmcoscellsetlimit0_cellsetlimit_up 8926 = egress_queue_min_reserve_uplink_ports_lossy; 8927 lwmcoscellsetlimit7_cellsetlimit_up 8928 = egress_queue_min_reserve_uplink_ports_lossy; 8929 lwmcoscellsetlimit_qlayer0_cellsetlimit_up 8930 = egress_queue_min_reserve_uplink_ports_lossy; 8931 lwmcoscellsetlimit_qlayer7_cellsetlimit_up 8932 = egress_queue_min_reserve_uplink_ports_lossy; 8933 lwmcoscellsetlimit_qlayer8_cellsetlimit_up = 0; 8934 holcoscellmaxlimit0_cellmaxlimit_up 8935 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8936 + lwmcoscellsetlimit0_cellsetlimit_up; 8937 holcoscellmaxlimit7_cellmaxlimit_up 8938 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8939 + lwmcoscellsetlimit7_cellsetlimit_up; 8940 holcoscellmaxlimit_qlayer0_cellmaxlimit_up 8941 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8942 + lwmcoscellsetlimit_qlayer0_cellsetlimit_up; 8943 holcoscellmaxlimit_qlayer7_cellmaxlimit_up 8944 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8945 + lwmcoscellsetlimit_qlayer7_cellsetlimit_up; 8946 holcoscellmaxlimit_qlayer8_cellmaxlimit_up 8947 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8948 + lwmcoscellsetlimit_qlayer8_cellsetlimit_up; 8949 dyncelllimit_dyncellsetlimit_up = shared_space_cells; 8950 holcospktsetlimit_qgroup0_pktsetlimit_up = numxqs_per_uplink_ports - 1; 8951 holcoscellmaxlimit_qgroup0_cellmaxlimit_up 8952 = ceiling_func(total_advertised_cell_memory, queue_port_limit_ratio); 8953 holcosminxqcnt_qlayer8_holcosminxqcnt_down_1 = 0; 8954 holcospktsetlimit0_pktsetlimit_down_1 8955 = shared_xqs_per_downlink_port 8956 + egress_xq_min_reserve_lossy_ports; 8957 holcospktsetlimit7_pktsetlimit_down_1 8958 = shared_xqs_per_downlink_port 8959 + egress_xq_min_reserve_lossy_ports; 8960 holcospktsetlimit_qlayer0_pktsetlimit_down_1 8961 = shared_xqs_per_downlink_port 8962 + egress_xq_min_reserve_lossy_ports; 8963 holcospktsetlimit_qlayer7_pktsetlimit_down_1 8964 = shared_xqs_per_downlink_port 8965 + egress_xq_min_reserve_lossy_ports; 8966 holcospktsetlimit_qlayer8_pktsetlimit_down_1 8967 = shared_xqs_per_downlink_port 8968 + holcosminxqcnt_qlayer8_holcosminxqcnt_down_1; 8969 dynxqcntport_dynxqcntport_down_1 8970 = shared_xqs_per_downlink_port - skidmarker - prefetch; 8971 lwmcoscellsetlimit0_cellsetlimit_down_1 = 8972 egress_queue_min_reserve_downlink_ports_lossy; 8973 lwmcoscellsetlimit7_cellsetlimit_down_1 = 8974 egress_queue_min_reserve_downlink_ports_lossy; 8975 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1 = 8976 egress_queue_min_reserve_downlink_ports_lossy; 8977 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1 = 8978 egress_queue_min_reserve_downlink_ports_lossy; 8979 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1 = 0; 8980 holcoscellmaxlimit0_cellmaxlimit_down_1 8981 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8982 + lwmcoscellsetlimit0_cellsetlimit_down_1; 8983 holcoscellmaxlimit7_cellmaxlimit_down_1 8984 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8985 + lwmcoscellsetlimit7_cellsetlimit_down_1; 8986 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_1 8987 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8988 + lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1; 8989 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_1 8990 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8991 + lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1; 8992 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_1 8993 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 8994 + lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1; 8995 dyncelllimit_dyncellsetlimit_down_1 = shared_space_cells; 8996 holcospktsetlimit_qgroup0_pktsetlimit_down_1 8997 = numxqs_per_downlink_ports_and_cpu_port - 1; 8998 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_1 8999 = ceiling_func(total_advertised_cell_memory, queue_port_limit_ratio); 9000 holcospktsetlimit0_pktsetlimit_down_2dot5 9001 = shared_xqs_per_downlink_port 9002 + egress_xq_min_reserve_lossy_ports; 9003 holcospktsetlimit7_pktsetlimit_down_2dot5 9004 = shared_xqs_per_downlink_port 9005 + egress_xq_min_reserve_lossy_ports; 9006 holcospktsetlimit_qlayer0_pktsetlimit_down_2dot5 9007 = shared_xqs_per_downlink_port 9008 + egress_xq_min_reserve_lossy_ports; 9009 holcospktsetlimit_qlayer7_pktsetlimit_down_2dot5 9010 = shared_xqs_per_downlink_port 9011 + egress_xq_min_reserve_lossy_ports; 9012 holcospktsetlimit_qlayer8_pktsetlimit_down_2dot5 9013 = shared_xqs_per_downlink_port 9014 + holcosminxqcnt_qlayer8_holcosminxqcnt_down_1; 9015 dynxqcntport_dynxqcntport_down_2dot5 9016 = shared_xqs_per_downlink_port - skidmarker - prefetch; 9017 lwmcoscellsetlimit0_cellsetlimit_down_2dot5 = 9018 egress_queue_min_reserve_downlink_ports_lossy; 9019 lwmcoscellsetlimit7_cellsetlimit_down_2dot5 = 9020 egress_queue_min_reserve_downlink_ports_lossy; 9021 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5 = 9022 egress_queue_min_reserve_downlink_ports_lossy; 9023 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5 = 9024 egress_queue_min_reserve_downlink_ports_lossy; 9025 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5 = 0; 9026 holcoscellmaxlimit0_cellmaxlimit_down_2dot5 9027 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 9028 + lwmcoscellsetlimit0_cellsetlimit_down_2dot5; 9029 holcoscellmaxlimit7_cellmaxlimit_down_2dot5 9030 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 9031 + lwmcoscellsetlimit7_cellsetlimit_down_2dot5; 9032 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_2dot5 9033 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 9034 + lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5; 9035 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_2dot5 9036 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 9037 + lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5; 9038 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_2dot5 9039 = ceiling_func(shared_space_cells, queue_port_limit_ratio) 9040 + lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5; 9041 dyncelllimit_dyncellsetlimit_down_2dot5 = shared_space_cells; 9042 holcospktsetlimit_qgroup0_pktsetlimit_down_2dot5 9043 = numxqs_per_downlink_ports_and_cpu_port - 1; 9044 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_2dot5 9045 = ceiling_func(total_advertised_cell_memory, queue_port_limit_ratio); 9046 holcosminxqcnt0_holcosminxqcnt_cpu = egress_queue_min_reserve_cpu_ports; 9047 holcosminxqcnt7_holcosminxqcnt_cpu = egress_queue_min_reserve_cpu_ports; 9048 holcospktsetlimit0_pktsetlimit_cpu = 9049 shared_xqs_per_downlink_port + holcosminxqcnt0_holcosminxqcnt_cpu; 9050 holcospktsetlimit7_pktsetlimit_cpu = 9051 shared_xqs_per_downlink_port + holcosminxqcnt7_holcosminxqcnt_cpu; 9052 dynxqcntport_dynxqcntport_cpu = 9053 shared_xqs_per_downlink_port - skidmarker - prefetch; 9054 lwmcoscellsetlimit0_cellsetlimit_cpu = egress_queue_min_reserve_cpu_ports; 9055 lwmcoscellsetlimit7_cellsetlimit_cpu = egress_queue_min_reserve_cpu_ports; 9056 holcoscellmaxlimit0_cellmaxlimit_cpu = 9057 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 9058 lwmcoscellsetlimit0_cellsetlimit_cpu; 9059 holcoscellmaxlimit7_cellmaxlimit_cpu = 9060 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 9061 lwmcoscellsetlimit7_cellsetlimit_cpu; 9062 dyncelllimit_dyncellsetlimit_cpu = shared_space_cells; 9063 9064 if ((shared_space_cells * cell_size)/1024 <= 800) { 9065 LOG_CLI((BSL_META_U(unit, 9066 "Shared Pool Is Small,\ 9067 should be larger than 800 (value=%d)\n"), 9068 (shared_space_cells * cell_size)/1024)); 9069 return SOC_E_PARAM; 9070 } 9071 9072 /* system-based */ 9073 soc_reg_field32_modify(unit, CFAPFULLTHRESHOLDr, 9074 REG_PORT_ANY, 9075 CFAPFULLSETPOINTf, 9076 cfapfullsetpoint); 9077 soc_reg_field32_modify(unit, CFAPFULLTHRESHOLDr, 9078 REG_PORT_ANY, 9079 CFAPFULLRESETPOINTf, 9080 cfapfullthreshold_cfapfullsetpoint_up - 9081 (standard_jumbo_frame_cell * 2)); 9082 soc_reg_field32_modify(unit, GBLLIMITSETLIMITr, 9083 REG_PORT_ANY, 9084 GBLCELLSETLIMITf, 9085 total_cell_memory_for_admission); 9086 soc_reg_field32_modify(unit, GBLLIMITRESETLIMITr, 9087 REG_PORT_ANY, 9088 GBLCELLRESETLIMITf, 9089 gbllimitsetlimit_gblcellsetlimit_up); 9090 soc_reg_field32_modify(unit, TOTALDYNCELLSETLIMITr, 9091 REG_PORT_ANY, 9092 TOTALDYNCELLSETLIMITf, 9093 shared_space_cells); 9094 soc_reg_field32_modify(unit, TOTALDYNCELLRESETLIMITr, 9095 REG_PORT_ANY, 9096 TOTALDYNCELLRESETLIMITf, 9097 totaldyncellsetlimit_totaldyncellsetlimit_up - 9098 (standard_jumbo_frame_cell * 2)); 9099 soc_reg_field32_modify(unit, TWO_LAYER_SCH_MODEr, 9100 REG_PORT_ANY, 9101 SCH_MODEf, 9102 0); 9103 soc_reg_field32_modify(unit, MISCCONFIGr, 9104 REG_PORT_ANY, 9105 MULTIPLE_ACCOUNTING_FIX_ENf, 9106 1); 9107 soc_reg_field32_modify(unit, MISCCONFIGr, 9108 REG_PORT_ANY, 9109 CNG_DROP_ENf, 9110 0); 9111 soc_reg_field32_modify(unit, MISCCONFIGr, 9112 REG_PORT_ANY, 9113 DYN_XQ_ENf, 9114 1); 9115 soc_reg_field32_modify(unit, MISCCONFIGr, 9116 REG_PORT_ANY, 9117 HOL_CELL_SOP_DROP_ENf, 9118 1); 9119 soc_reg_field32_modify(unit, MISCCONFIGr, 9120 REG_PORT_ANY, 9121 DYNAMIC_MEMORY_ENf, 9122 1); 9123 soc_reg_field32_modify(unit, MISCCONFIGr, 9124 REG_PORT_ANY, 9125 SKIDMARKERf, 9126 3); 9127 soc_reg_field32_modify(unit, MMUPORTTXENABLE_0r, 9128 REG_PORT_ANY, 9129 MMUPORTTXENABLEf, 9130 0xFFFFFFFF); 9131 soc_reg_field32_modify(unit, MMUPORTTXENABLE_1r, 9132 REG_PORT_ANY, 9133 MMUPORTTXENABLEf, 9134 0xFFFFFFFF); 9135 soc_reg_field32_modify(unit, MMUPORTTXENABLE_2r, 9136 REG_PORT_ANY, 9137 MMUPORTTXENABLEf, 9138 3); 9139 9140 /* port-based : uplink */ 9141 SOC_PBMP_ITER(pbmp_uplink, port) { 9142 /* PG_CTRL0r, index 0 */ 9143 soc_reg32_get(unit, PG_CTRL0r, 9144 port, 0, &rval); 9145 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9146 PPFC_PG_ENf, 9147 0); 9148 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9149 PRI0_GRPf, 9150 0); 9151 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9152 PRI1_GRPf, 9153 1); 9154 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9155 PRI2_GRPf, 9156 2); 9157 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9158 PRI3_GRPf, 9159 3); 9160 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9161 PRI4_GRPf, 9162 4); 9163 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9164 PRI5_GRPf, 9165 5); 9166 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9167 PRI6_GRPf, 9168 6); 9169 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9170 PRI7_GRPf, 9171 7); 9172 soc_reg32_set(unit, PG_CTRL0r, 9173 port, 0, rval); 9174 9175 /* PG_CTRL1r, index 0 */ 9176 soc_reg32_get(unit, PG_CTRL1r, 9177 port, 0, &rval); 9178 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9179 PRI8_GRPf, 9180 7); 9181 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9182 PRI9_GRPf, 9183 7); 9184 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9185 PRI10_GRPf, 9186 7); 9187 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9188 PRI11_GRPf, 9189 7); 9190 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9191 PRI12_GRPf, 9192 7); 9193 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9194 PRI13_GRPf, 9195 7); 9196 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9197 PRI14_GRPf, 9198 7); 9199 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9200 PRI15_GRPf, 9201 7); 9202 soc_reg32_set(unit, PG_CTRL1r, 9203 port, 0, rval); 9204 9205 /* PG2TCr, index 0 ~ 7 */ 9206 for (index = 0; index <= 7; index++) { 9207 soc_reg32_get(unit, PG2TCr, 9208 port, index, &rval); 9209 soc_reg_field_set(unit, PG2TCr, &rval, 9210 PG_BMPf, 9211 0); 9212 soc_reg32_set(unit, PG2TCr, 9213 port, index, rval); 9214 } 9215 9216 /* IBPPKTSETLIMITr, index 0 */ 9217 soc_reg32_get(unit, IBPPKTSETLIMITr, 9218 port, 0, &rval); 9219 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 9220 PKTSETLIMITf, 9221 xoff_packet_thresholds_per_port_uplink_port); 9222 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 9223 RESETLIMITSELf, 9224 3); 9225 soc_reg32_set(unit, IBPPKTSETLIMITr, 9226 port, 0, rval); 9227 9228 /* MMU_FC_RX_ENr, index 0 */ 9229 soc_reg32_get(unit, MMU_FC_RX_ENr, 9230 port, 0, &rval); 9231 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 9232 MMU_FC_RX_ENABLEf, 9233 0); 9234 soc_reg32_set(unit, MMU_FC_RX_ENr, 9235 port, 0, rval); 9236 9237 /* MMU_FC_TX_ENr, index 0 */ 9238 soc_reg32_get(unit, MMU_FC_TX_ENr, 9239 port, 0, &rval); 9240 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 9241 MMU_FC_TX_ENABLEf, 9242 0); 9243 soc_reg32_set(unit, MMU_FC_TX_ENr, 9244 port, 0, rval); 9245 9246 /* PGCELLLIMITr, index 0 ~ 7 */ 9247 for (index = 0; index <= 7; index++) { 9248 soc_reg32_get(unit, PGCELLLIMITr, 9249 port, index, &rval); 9250 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 9251 CELLSETLIMITf, 9252 xoff_cell_threshold_all_uplink_ports); 9253 soc_reg32_set(unit, PGCELLLIMITr, 9254 port, index, rval); 9255 } 9256 9257 /* PGCELLLIMITr, index 0 ~ 7 */ 9258 for (index = 0; index <= 7; index++) { 9259 soc_reg32_get(unit, PGCELLLIMITr, 9260 port, index, &rval); 9261 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 9262 CELLRESETLIMITf, 9263 xoff_cell_threshold_all_uplink_ports); 9264 soc_reg32_set(unit, PGCELLLIMITr, 9265 port, index, rval); 9266 } 9267 9268 /* PGDISCARDSETLIMITr, index 0 ~ 7 */ 9269 for (index = 0; index <= 7; index++) { 9270 soc_reg32_get(unit, PGDISCARDSETLIMITr, 9271 port, index, &rval); 9272 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 9273 DISCARDSETLIMITf, 9274 discard_limit_per_port_pg_downlink_port); 9275 soc_reg32_set(unit, PGDISCARDSETLIMITr, 9276 port, index, rval); 9277 } 9278 9279 /* HOLCOSMINXQCNTr, index 0 ~ 7 */ 9280 for (index = 0; index <= 7; index++) { 9281 soc_reg32_get(unit, HOLCOSMINXQCNTr, 9282 port, index, &rval); 9283 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 9284 HOLCOSMINXQCNTf, 9285 egress_xq_min_reserve_lossy_ports); 9286 soc_reg32_set(unit, HOLCOSMINXQCNTr, 9287 port, index, rval); 9288 } 9289 9290 /* HOLCOSMINXQCNT_QLAYERr, index 0 ~ 7 */ 9291 for (index = 0; index <= 7; index++) { 9292 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 9293 port, index, &rval); 9294 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 9295 HOLCOSMINXQCNTf, 9296 egress_xq_min_reserve_lossy_ports); 9297 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 9298 port, index, rval); 9299 } 9300 9301 /* HOLCOSMINXQCNT_QLAYERr, index 8 ~ 63 */ 9302 for (index = 8; index <= 63; index++) { 9303 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 9304 port, index, &rval); 9305 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 9306 HOLCOSMINXQCNTf, 9307 0); 9308 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 9309 port, index, rval); 9310 } 9311 9312 /* HOLCOSPKTSETLIMITr, index 0 ~ 7 */ 9313 for (index = 0; index <= 7; index++) { 9314 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 9315 port, index, &rval); 9316 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 9317 PKTSETLIMITf, 9318 shared_xqs_per_uplink_port + 9319 egress_xq_min_reserve_lossy_ports); 9320 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 9321 port, index, rval); 9322 } 9323 9324 /* HOLCOSPKTSETLIMIT_QLAYERr, index 0 ~ 7 */ 9325 for (index = 0; index <= 7; index++) { 9326 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 9327 port, index, &rval); 9328 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 9329 PKTSETLIMITf, 9330 shared_xqs_per_uplink_port + 9331 egress_xq_min_reserve_lossy_ports); 9332 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 9333 port, index, rval); 9334 } 9335 9336 /* HOLCOSPKTSETLIMIT_QLAYERr, index 8 ~ 63 */ 9337 for (index = 8; index <= 63; index++) { 9338 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 9339 port, index, &rval); 9340 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 9341 PKTSETLIMITf, 9342 shared_xqs_per_uplink_port + 9343 holcosminxqcnt_qlayer8_holcosminxqcnt_up); 9344 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 9345 port, index, rval); 9346 } 9347 9348 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 9349 for (index = 0; index <= 6; index++) { 9350 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 9351 port, index, &rval); 9352 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 9353 PKTRESETLIMITf, 9354 holcospktsetlimit0_pktsetlimit_up - 1); 9355 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 9356 port, index, rval); 9357 } 9358 9359 /* HOLCOSPKTRESETLIMITr, index 7 */ 9360 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 9361 port, 7, &rval); 9362 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 9363 PKTRESETLIMITf, 9364 holcospktsetlimit7_pktsetlimit_up - 1); 9365 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 9366 port, 7, rval); 9367 9368 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 0 ~ 6 */ 9369 for (index = 0; index <= 6; index++) { 9370 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 9371 port, index, &rval); 9372 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 9373 PKTRESETLIMITf, 9374 holcospktsetlimit_qlayer0_pktsetlimit_up - 1); 9375 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 9376 port, index, rval); 9377 } 9378 9379 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 7 */ 9380 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 9381 port, 7, &rval); 9382 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 9383 PKTRESETLIMITf, 9384 holcospktsetlimit_qlayer7_pktsetlimit_up - 1); 9385 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 9386 port, 7, rval); 9387 9388 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 8 ~ 63 */ 9389 for (index = 8; index <= 63; index++) { 9390 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 9391 port, index, &rval); 9392 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 9393 PKTRESETLIMITf, 9394 holcospktsetlimit_qlayer8_pktsetlimit_up - 1); 9395 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 9396 port, index, rval); 9397 } 9398 9399 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 9400 for (index = 0; index <= 7; index++) { 9401 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 9402 port, index, &rval); 9403 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 9404 CNGPKTSETLIMIT0f, 9405 numxqs_per_uplink_ports - 1); 9406 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 9407 port, index, rval); 9408 } 9409 9410 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 9411 for (index = 0; index <= 7; index++) { 9412 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 9413 port, index, &rval); 9414 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 9415 CNGPKTSETLIMIT1f, 9416 numxqs_per_uplink_ports - 1); 9417 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 9418 port, index, rval); 9419 } 9420 9421 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 9422 for (index = 0; index <= 63; index++) { 9423 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 9424 port, index, &rval); 9425 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 9426 CNGPKTSETLIMIT0f, 9427 numxqs_per_uplink_ports - 1); 9428 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 9429 port, index, rval); 9430 } 9431 9432 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 9433 for (index = 0; index <= 63; index++) { 9434 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 9435 port, index, &rval); 9436 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 9437 CNGPKTSETLIMIT1f, 9438 numxqs_per_uplink_ports - 1); 9439 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 9440 port, index, rval); 9441 } 9442 9443 /* CNGPORTPKTLIMIT0r, index 0 */ 9444 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 9445 port, 0, &rval); 9446 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 9447 CNGPORTPKTLIMIT0f, 9448 numxqs_per_uplink_ports - 1); 9449 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 9450 port, 0, rval); 9451 9452 /* CNGPORTPKTLIMIT1r, index 0 */ 9453 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 9454 port, 0, &rval); 9455 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 9456 CNGPORTPKTLIMIT1f, 9457 numxqs_per_uplink_ports - 1); 9458 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 9459 port, 0, rval); 9460 9461 /* DYNXQCNTPORTr, index 0 */ 9462 soc_reg32_get(unit, DYNXQCNTPORTr, 9463 port, 0, &rval); 9464 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 9465 DYNXQCNTPORTf, 9466 shared_xqs_per_uplink_port - skidmarker - prefetch); 9467 soc_reg32_set(unit, DYNXQCNTPORTr, 9468 port, 0, rval); 9469 9470 /* DYNRESETLIMPORTr, index 0 */ 9471 soc_reg32_get(unit, DYNRESETLIMPORTr, 9472 port, 0, &rval); 9473 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 9474 DYNRESETLIMPORTf, 9475 dynxqcntport_dynxqcntport_up - 2); 9476 soc_reg32_set(unit, DYNRESETLIMPORTr, 9477 port, 0, rval); 9478 9479 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 9480 for (index = 0; index <= 7; index++) { 9481 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 9482 port, index, &rval); 9483 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 9484 CELLSETLIMITf, 9485 egress_queue_min_reserve_uplink_ports_lossy); 9486 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 9487 port, index, rval); 9488 } 9489 9490 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 7 */ 9491 for (index = 0; index <= 7; index++) { 9492 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9493 port, index, &rval); 9494 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 9495 CELLSETLIMITf, 9496 egress_queue_min_reserve_uplink_ports_lossy); 9497 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9498 port, index, rval); 9499 } 9500 9501 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 9502 for (index = 8; index <= 63; index++) { 9503 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9504 port, index, &rval); 9505 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 9506 CELLSETLIMITf, 9507 0); 9508 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9509 port, index, rval); 9510 } 9511 9512 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 9513 for (index = 0; index <= 7; index++) { 9514 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 9515 port, index, &rval); 9516 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 9517 CELLRESETLIMITf, 9518 egress_queue_min_reserve_uplink_ports_lossy); 9519 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 9520 port, index, rval); 9521 } 9522 9523 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 7 */ 9524 for (index = 0; index <= 7; index++) { 9525 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9526 port, index, &rval); 9527 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 9528 CELLRESETLIMITf, 9529 egress_queue_min_reserve_uplink_ports_lossy); 9530 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9531 port, index, rval); 9532 } 9533 9534 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 9535 for (index = 8; index <= 63; index++) { 9536 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9537 port, index, &rval); 9538 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 9539 CELLRESETLIMITf, 9540 0); 9541 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 9542 port, index, rval); 9543 } 9544 9545 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 9546 for (index = 0; index <= 6; index++) { 9547 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 9548 port, index, &rval); 9549 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 9550 CELLMAXLIMITf, 9551 ceiling_func(shared_space_cells, 9552 queue_port_limit_ratio) + 9553 lwmcoscellsetlimit0_cellsetlimit_up); 9554 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 9555 port, index, rval); 9556 } 9557 9558 /* HOLCOSCELLMAXLIMITr, index 7 */ 9559 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 9560 port, 7, &rval); 9561 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 9562 CELLMAXLIMITf, 9563 ceiling_func(shared_space_cells, 9564 queue_port_limit_ratio) + 9565 lwmcoscellsetlimit7_cellsetlimit_up); 9566 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 9567 port, 7, rval); 9568 9569 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 9570 for (index = 0; index <= 6; index++) { 9571 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9572 port, index, &rval); 9573 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 9574 CELLMAXLIMITf, 9575 ceiling_func(shared_space_cells, 9576 queue_port_limit_ratio) + 9577 lwmcoscellsetlimit_qlayer0_cellsetlimit_up); 9578 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9579 port, index, rval); 9580 } 9581 9582 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 9583 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9584 port, 7, &rval); 9585 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 9586 CELLMAXLIMITf, 9587 ceiling_func(shared_space_cells, 9588 queue_port_limit_ratio) + 9589 lwmcoscellsetlimit_qlayer7_cellsetlimit_up); 9590 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9591 port, 7, rval); 9592 9593 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 9594 for (index = 8; index <= 63; index++) { 9595 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9596 port, index, &rval); 9597 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 9598 CELLMAXLIMITf, 9599 ceiling_func(shared_space_cells, 9600 queue_port_limit_ratio) + 9601 lwmcoscellsetlimit_qlayer8_cellsetlimit_up); 9602 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9603 port, index, rval); 9604 } 9605 9606 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 9607 for (index = 0; index <= 6; index++) { 9608 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 9609 port, index, &rval); 9610 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 9611 CELLMAXRESUMELIMITf, 9612 holcoscellmaxlimit0_cellmaxlimit_up - 9613 ethernet_mtu_cell); 9614 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 9615 port, index, rval); 9616 } 9617 9618 /* HOLCOSCELLMAXLIMITr, index 7 */ 9619 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 9620 port, 7, &rval); 9621 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 9622 CELLMAXRESUMELIMITf, 9623 holcoscellmaxlimit7_cellmaxlimit_up - 9624 ethernet_mtu_cell); 9625 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 9626 port, 7, rval); 9627 9628 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 9629 for (index = 0; index <= 6; index++) { 9630 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9631 port, index, &rval); 9632 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 9633 CELLMAXRESUMELIMITf, 9634 holcoscellmaxlimit_qlayer0_cellmaxlimit_up - 9635 ethernet_mtu_cell); 9636 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9637 port, index, rval); 9638 } 9639 9640 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 9641 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9642 port, 7, &rval); 9643 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 9644 CELLMAXRESUMELIMITf, 9645 holcoscellmaxlimit_qlayer7_cellmaxlimit_up - 9646 ethernet_mtu_cell); 9647 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9648 port, 7, rval); 9649 9650 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 9651 for (index = 8; index <= 63; index++) { 9652 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9653 port, index, &rval); 9654 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 9655 CELLMAXRESUMELIMITf, 9656 holcoscellmaxlimit_qlayer8_cellmaxlimit_up - 9657 ethernet_mtu_cell); 9658 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 9659 port, index, rval); 9660 } 9661 9662 /* DYNCELLLIMITr, index 0 */ 9663 soc_reg32_get(unit, DYNCELLLIMITr, 9664 port, 0, &rval); 9665 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 9666 DYNCELLSETLIMITf, 9667 shared_space_cells); 9668 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 9669 DYNCELLRESETLIMITf, 9670 dyncelllimit_dyncellsetlimit_up - 9671 (2 * ethernet_mtu_cell)); 9672 soc_reg32_set(unit, DYNCELLLIMITr, 9673 port, 0, rval); 9674 9675 /* COLOR_DROP_ENr, index 0 */ 9676 soc_reg32_get(unit, COLOR_DROP_ENr, 9677 port, 0, &rval); 9678 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 9679 COLOR_DROP_ENf, 9680 0); 9681 soc_reg32_set(unit, COLOR_DROP_ENr, 9682 port, 0, rval); 9683 9684 /* COLOR_DROP_EN_QLAYERr, index 0 */ 9685 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 9686 port, 0, &rval); 9687 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 9688 COLOR_DROP_ENf, 9689 0); 9690 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 9691 port, 0, rval); 9692 9693 /* HOLCOSPKTSETLIMIT_QGROUPr, index 0 ~ 7 */ 9694 for (index = 0; index <= 7; index++) { 9695 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QGROUPr, 9696 port, index, &rval); 9697 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, &rval, 9698 PKTSETLIMITf, 9699 numxqs_per_uplink_ports - 1); 9700 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, 9701 port, index, rval); 9702 } 9703 9704 /* HOLCOSPKTRESETLIMIT_QGROUPr, index 0 ~ 7 */ 9705 for (index = 0; index <= 7; index++) { 9706 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 9707 port, index, &rval); 9708 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, &rval, 9709 PKTRESETLIMITf, 9710 holcospktsetlimit_qgroup0_pktsetlimit_up - 1); 9711 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 9712 port, index, rval); 9713 } 9714 9715 /* CNGCOSPKTLIMIT0_QGROUPr, index 0 ~ 7 */ 9716 for (index = 0; index <= 7; index++) { 9717 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QGROUPr, 9718 port, index, &rval); 9719 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QGROUPr, &rval, 9720 CNGPKTSETLIMIT0f, 9721 numxqs_per_uplink_ports - 1); 9722 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QGROUPr, 9723 port, index, rval); 9724 } 9725 9726 /* CNGCOSPKTLIMIT1_QGROUPr, index 0 ~ 7 */ 9727 for (index = 0; index <= 7; index++) { 9728 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QGROUPr, 9729 port, index, &rval); 9730 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QGROUPr, &rval, 9731 CNGPKTSETLIMIT1f, 9732 numxqs_per_uplink_ports - 1); 9733 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QGROUPr, 9734 port, index, rval); 9735 } 9736 9737 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 9738 for (index = 0; index <= 7; index++) { 9739 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 9740 port, index, &rval); 9741 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 9742 CELLMAXLIMITf, 9743 ceiling_func(total_advertised_cell_memory, 9744 queue_port_limit_ratio)); 9745 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 9746 port, index, rval); 9747 } 9748 9749 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 9750 for (index = 0; index <= 7; index++) { 9751 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 9752 port, index, &rval); 9753 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 9754 CELLMAXRESUMELIMITf, 9755 holcoscellmaxlimit_qgroup0_cellmaxlimit_up - 9756 ethernet_mtu_cell); 9757 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 9758 port, index, rval); 9759 } 9760 9761 /* COLOR_DROP_EN_QGROUPr, index 0 */ 9762 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 9763 port, 0, &rval); 9764 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 9765 COLOR_DROP_ENf, 9766 0); 9767 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 9768 port, 0, rval); 9769 9770 /* SHARED_POOL_CTRLr, index 0 */ 9771 soc_reg32_get(unit, SHARED_POOL_CTRLr, 9772 port, 0, &rval); 9773 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 9774 DYNAMIC_COS_DROP_ENf, 9775 255); 9776 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 9777 SHARED_POOL_DISCARD_ENf, 9778 255); 9779 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 9780 SHARED_POOL_XOFF_ENf, 9781 0); 9782 soc_reg32_set(unit, SHARED_POOL_CTRLr, 9783 port, 0, rval); 9784 9785 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 9786 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 9787 port, 0, &rval); 9788 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 9789 DYNAMIC_COS_DROP_ENf, 9790 0xFFFFFF); 9791 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 9792 port, 0, rval); 9793 9794 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 9795 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 9796 port, 0, &rval); 9797 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 9798 DYNAMIC_COS_DROP_ENf, 9799 0xFFFFFFFF); 9800 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 9801 port, 0, rval); 9802 } 9803 9804 /* port-based : downlink 1G */ 9805 SOC_PBMP_ITER(pbmp_downlink_1g, port) { 9806 /* PG_CTRL0r, index 0 */ 9807 soc_reg32_get(unit, PG_CTRL0r, 9808 port, 0, &rval); 9809 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9810 PPFC_PG_ENf, 9811 0); 9812 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9813 PRI0_GRPf, 9814 0); 9815 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9816 PRI1_GRPf, 9817 1); 9818 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9819 PRI2_GRPf, 9820 2); 9821 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9822 PRI3_GRPf, 9823 3); 9824 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9825 PRI4_GRPf, 9826 4); 9827 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9828 PRI5_GRPf, 9829 5); 9830 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9831 PRI6_GRPf, 9832 6); 9833 soc_reg_field_set(unit, PG_CTRL0r, &rval, 9834 PRI7_GRPf, 9835 7); 9836 soc_reg32_set(unit, PG_CTRL0r, 9837 port, 0, rval); 9838 9839 /* PG_CTRL1r, index 0 */ 9840 soc_reg32_get(unit, PG_CTRL1r, 9841 port, 0, &rval); 9842 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9843 PRI8_GRPf, 9844 7); 9845 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9846 PRI9_GRPf, 9847 7); 9848 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9849 PRI10_GRPf, 9850 7); 9851 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9852 PRI11_GRPf, 9853 7); 9854 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9855 PRI12_GRPf, 9856 7); 9857 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9858 PRI13_GRPf, 9859 7); 9860 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9861 PRI14_GRPf, 9862 7); 9863 soc_reg_field_set(unit, PG_CTRL1r, &rval, 9864 PRI15_GRPf, 9865 7); 9866 soc_reg32_set(unit, PG_CTRL1r, 9867 port, 0, rval); 9868 9869 /* PG2TCr, index 0 ~ 7 */ 9870 for (index = 0; index <= 7; index++) { 9871 soc_reg32_get(unit, PG2TCr, 9872 port, index, &rval); 9873 soc_reg_field_set(unit, PG2TCr, &rval, 9874 PG_BMPf, 9875 0); 9876 soc_reg32_set(unit, PG2TCr, 9877 port, index, rval); 9878 } 9879 9880 /* IBPPKTSETLIMITr, index 0 */ 9881 soc_reg32_get(unit, IBPPKTSETLIMITr, 9882 port, 0, &rval); 9883 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 9884 PKTSETLIMITf, 9885 xoff_packet_thresholds_per_port_downlink_port); 9886 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 9887 RESETLIMITSELf, 9888 3); 9889 soc_reg32_set(unit, IBPPKTSETLIMITr, 9890 port, 0, rval); 9891 9892 /* MMU_FC_RX_ENr, index 0 */ 9893 soc_reg32_get(unit, MMU_FC_RX_ENr, 9894 port, 0, &rval); 9895 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 9896 MMU_FC_RX_ENABLEf, 9897 0); 9898 soc_reg32_set(unit, MMU_FC_RX_ENr, 9899 port, 0, rval); 9900 9901 /* MMU_FC_TX_ENr, index 0 */ 9902 soc_reg32_get(unit, MMU_FC_TX_ENr, 9903 port, 0, &rval); 9904 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 9905 MMU_FC_TX_ENABLEf, 9906 0); 9907 soc_reg32_set(unit, MMU_FC_TX_ENr, 9908 port, 0, rval); 9909 9910 /* PGCELLLIMITr, index 0 ~ 6 */ 9911 for (index = 0; index <= 6; index++) { 9912 soc_reg32_get(unit, PGCELLLIMITr, 9913 port, index, &rval); 9914 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 9915 CELLSETLIMITf, 9916 xoff_cell_threshold_all_uplink_ports); 9917 soc_reg32_set(unit, PGCELLLIMITr, 9918 port, index, rval); 9919 } 9920 9921 /* PGCELLLIMITr, index 7 */ 9922 soc_reg32_get(unit, PGCELLLIMITr, 9923 port, 7, &rval); 9924 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 9925 CELLSETLIMITf, 9926 xoff_cell_thresholds_per_port_1g_port_downlink_ports); 9927 soc_reg32_set(unit, PGCELLLIMITr, 9928 port, 7, rval); 9929 9930 /* PGCELLLIMITr, index 0 ~ 6 */ 9931 for (index = 0; index <= 6; index++) { 9932 soc_reg32_get(unit, PGCELLLIMITr, 9933 port, index, &rval); 9934 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 9935 CELLRESETLIMITf, 9936 xoff_cell_threshold_all_uplink_ports); 9937 soc_reg32_set(unit, PGCELLLIMITr, 9938 port, index, rval); 9939 } 9940 9941 /* PGCELLLIMITr, index 7 */ 9942 soc_reg32_get(unit, PGCELLLIMITr, 9943 port, 7, &rval); 9944 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 9945 CELLRESETLIMITf, 9946 xoff_cell_thresholds_per_port_1g_port_downlink_ports); 9947 soc_reg32_set(unit, PGCELLLIMITr, 9948 port, 7, rval); 9949 9950 /* PGDISCARDSETLIMITr, index 0 ~ 6 */ 9951 for (index = 0; index <= 6; index++) { 9952 soc_reg32_get(unit, PGDISCARDSETLIMITr, 9953 port, index, &rval); 9954 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 9955 DISCARDSETLIMITf, 9956 discard_limit_per_port_pg_downlink_port); 9957 soc_reg32_set(unit, PGDISCARDSETLIMITr, 9958 port, index, rval); 9959 } 9960 9961 /* PGDISCARDSETLIMITr, index 7 */ 9962 soc_reg32_get(unit, PGDISCARDSETLIMITr, 9963 port, 7, &rval); 9964 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 9965 DISCARDSETLIMITf, 9966 discard_limit_per_port_pg_uplink_1g_port); 9967 soc_reg32_set(unit, PGDISCARDSETLIMITr, 9968 port, 7, rval); 9969 9970 /* HOLCOSMINXQCNTr, index 0 ~ 7 */ 9971 for (index = 0; index <= 7; index++) { 9972 soc_reg32_get(unit, HOLCOSMINXQCNTr, 9973 port, index, &rval); 9974 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 9975 HOLCOSMINXQCNTf, 9976 egress_xq_min_reserve_lossy_ports); 9977 soc_reg32_set(unit, HOLCOSMINXQCNTr, 9978 port, index, rval); 9979 } 9980 9981 /* HOLCOSMINXQCNT_QLAYERr, index 0 ~ 7 */ 9982 for (index = 0; index <= 7; index++) { 9983 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 9984 port, index, &rval); 9985 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 9986 HOLCOSMINXQCNTf, 9987 egress_xq_min_reserve_lossy_ports); 9988 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 9989 port, index, rval); 9990 } 9991 9992 /* HOLCOSMINXQCNT_QLAYERr, index 8 ~ 63 */ 9993 for (index = 8; index <= 63; index++) { 9994 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 9995 port, index, &rval); 9996 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 9997 HOLCOSMINXQCNTf, 9998 0); 9999 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 10000 port, index, rval); 10001 } 10002 10003 /* HOLCOSPKTSETLIMITr, index 0 ~ 7 */ 10004 for (index = 0; index <= 7; index++) { 10005 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 10006 port, index, &rval); 10007 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 10008 PKTSETLIMITf, 10009 shared_xqs_per_downlink_port + 10010 egress_xq_min_reserve_lossy_ports); 10011 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 10012 port, index, rval); 10013 } 10014 10015 /* HOLCOSPKTSETLIMIT_QLAYERr, index 0 ~ 7 */ 10016 for (index = 0; index <= 7; index++) { 10017 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10018 port, index, &rval); 10019 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 10020 PKTSETLIMITf, 10021 shared_xqs_per_downlink_port + 10022 egress_xq_min_reserve_lossy_ports); 10023 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10024 port, index, rval); 10025 } 10026 10027 /* HOLCOSPKTSETLIMIT_QLAYERr, index 8 ~ 63 */ 10028 for (index = 8; index <= 63; index++) { 10029 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10030 port, index, &rval); 10031 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 10032 PKTSETLIMITf, 10033 shared_xqs_per_downlink_port + 10034 holcosminxqcnt_qlayer8_holcosminxqcnt_down_1); 10035 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10036 port, index, rval); 10037 } 10038 10039 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 10040 for (index = 0; index <= 6; index++) { 10041 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 10042 port, index, &rval); 10043 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 10044 PKTRESETLIMITf, 10045 holcospktsetlimit0_pktsetlimit_down_1 - 1); 10046 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 10047 port, index, rval); 10048 } 10049 10050 /* HOLCOSPKTRESETLIMITr, index 7 */ 10051 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 10052 port, 7, &rval); 10053 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 10054 PKTRESETLIMITf, 10055 holcospktsetlimit7_pktsetlimit_down_1 - 1); 10056 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 10057 port, 7, rval); 10058 10059 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 0 ~ 6 */ 10060 for (index = 0; index <= 6; index++) { 10061 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10062 port, index, &rval); 10063 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 10064 PKTRESETLIMITf, 10065 holcospktsetlimit_qlayer0_pktsetlimit_down_1 - 1); 10066 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10067 port, index, rval); 10068 } 10069 10070 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 7 */ 10071 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10072 port, 7, &rval); 10073 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 10074 PKTRESETLIMITf, 10075 holcospktsetlimit_qlayer7_pktsetlimit_down_1 - 1); 10076 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10077 port, 7, rval); 10078 10079 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 8 ~ 63 */ 10080 for (index = 8; index <= 63; index++) { 10081 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10082 port, index, &rval); 10083 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 10084 PKTRESETLIMITf, 10085 holcospktsetlimit_qlayer8_pktsetlimit_down_1 - 1); 10086 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10087 port, index, rval); 10088 } 10089 10090 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 10091 for (index = 0; index <= 7; index++) { 10092 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 10093 port, index, &rval); 10094 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 10095 CNGPKTSETLIMIT0f, 10096 numxqs_per_downlink_ports_and_cpu_port - 1); 10097 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 10098 port, index, rval); 10099 } 10100 10101 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 10102 for (index = 0; index <= 7; index++) { 10103 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 10104 port, index, &rval); 10105 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 10106 CNGPKTSETLIMIT1f, 10107 numxqs_per_downlink_ports_and_cpu_port - 1); 10108 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 10109 port, index, rval); 10110 } 10111 10112 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 10113 for (index = 0; index <= 63; index++) { 10114 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 10115 port, index, &rval); 10116 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 10117 CNGPKTSETLIMIT0f, 10118 numxqs_per_downlink_ports_and_cpu_port - 1); 10119 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 10120 port, index, rval); 10121 } 10122 10123 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 10124 for (index = 0; index <= 63; index++) { 10125 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 10126 port, index, &rval); 10127 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 10128 CNGPKTSETLIMIT1f, 10129 numxqs_per_downlink_ports_and_cpu_port - 1); 10130 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 10131 port, index, rval); 10132 } 10133 10134 /* CNGPORTPKTLIMIT0r, index 0 */ 10135 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 10136 port, 0, &rval); 10137 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 10138 CNGPORTPKTLIMIT0f, 10139 numxqs_per_downlink_ports_and_cpu_port - 1); 10140 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 10141 port, 0, rval); 10142 10143 /* CNGPORTPKTLIMIT1r, index 0 */ 10144 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 10145 port, 0, &rval); 10146 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 10147 CNGPORTPKTLIMIT1f, 10148 numxqs_per_downlink_ports_and_cpu_port - 1); 10149 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 10150 port, 0, rval); 10151 10152 /* DYNXQCNTPORTr, index 0 */ 10153 soc_reg32_get(unit, DYNXQCNTPORTr, 10154 port, 0, &rval); 10155 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 10156 DYNXQCNTPORTf, 10157 shared_xqs_per_downlink_port - skidmarker - prefetch); 10158 soc_reg32_set(unit, DYNXQCNTPORTr, 10159 port, 0, rval); 10160 10161 /* DYNRESETLIMPORTr, index 0 */ 10162 soc_reg32_get(unit, DYNRESETLIMPORTr, 10163 port, 0, &rval); 10164 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 10165 DYNRESETLIMPORTf, 10166 dynxqcntport_dynxqcntport_down_1 - 2); 10167 soc_reg32_set(unit, DYNRESETLIMPORTr, 10168 port, 0, rval); 10169 10170 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 10171 for (index = 0; index <= 7; index++) { 10172 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 10173 port, index, &rval); 10174 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 10175 CELLSETLIMITf, 10176 egress_queue_min_reserve_downlink_ports_lossy); 10177 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 10178 port, index, rval); 10179 } 10180 10181 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 7 */ 10182 for (index = 0; index <= 7; index++) { 10183 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10184 port, index, &rval); 10185 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10186 CELLSETLIMITf, 10187 egress_queue_min_reserve_downlink_ports_lossy); 10188 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10189 port, index, rval); 10190 } 10191 10192 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 10193 for (index = 8; index <= 63; index++) { 10194 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10195 port, index, &rval); 10196 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10197 CELLSETLIMITf, 10198 0); 10199 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10200 port, index, rval); 10201 } 10202 10203 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 10204 for (index = 0; index <= 7; index++) { 10205 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 10206 port, index, &rval); 10207 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 10208 CELLRESETLIMITf, 10209 egress_queue_min_reserve_downlink_ports_lossy); 10210 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 10211 port, index, rval); 10212 } 10213 10214 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 7 */ 10215 for (index = 0; index <= 7; index++) { 10216 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10217 port, index, &rval); 10218 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10219 CELLRESETLIMITf, 10220 egress_queue_min_reserve_downlink_ports_lossy); 10221 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10222 port, index, rval); 10223 } 10224 10225 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 10226 for (index = 8; index <= 63; index++) { 10227 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10228 port, index, &rval); 10229 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10230 CELLRESETLIMITf, 10231 0); 10232 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10233 port, index, rval); 10234 } 10235 10236 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 10237 for (index = 0; index <= 6; index++) { 10238 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 10239 port, index, &rval); 10240 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 10241 CELLMAXLIMITf, 10242 ceiling_func(shared_space_cells, 10243 queue_port_limit_ratio) + 10244 lwmcoscellsetlimit0_cellsetlimit_down_1); 10245 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 10246 port, index, rval); 10247 } 10248 10249 /* HOLCOSCELLMAXLIMITr, index 7 */ 10250 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 10251 port, 7, &rval); 10252 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 10253 CELLMAXLIMITf, 10254 ceiling_func(shared_space_cells, 10255 queue_port_limit_ratio) + 10256 lwmcoscellsetlimit7_cellsetlimit_down_1); 10257 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 10258 port, 7, rval); 10259 10260 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 10261 for (index = 0; index <= 6; index++) { 10262 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10263 port, index, &rval); 10264 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10265 CELLMAXLIMITf, 10266 ceiling_func(shared_space_cells, 10267 queue_port_limit_ratio) + 10268 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1); 10269 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10270 port, index, rval); 10271 } 10272 10273 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 10274 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10275 port, 7, &rval); 10276 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10277 CELLMAXLIMITf, 10278 ceiling_func(shared_space_cells, 10279 queue_port_limit_ratio) + 10280 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1); 10281 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10282 port, 7, rval); 10283 10284 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 10285 for (index = 8; index <= 63; index++) { 10286 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10287 port, index, &rval); 10288 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10289 CELLMAXLIMITf, 10290 ceiling_func(shared_space_cells, 10291 queue_port_limit_ratio) + 10292 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1); 10293 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10294 port, index, rval); 10295 } 10296 10297 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 10298 for (index = 0; index <= 6; index++) { 10299 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 10300 port, index, &rval); 10301 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 10302 CELLMAXRESUMELIMITf, 10303 holcoscellmaxlimit0_cellmaxlimit_down_1 - 10304 ethernet_mtu_cell); 10305 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 10306 port, index, rval); 10307 } 10308 10309 /* HOLCOSCELLMAXLIMITr, index 7 */ 10310 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 10311 port, 7, &rval); 10312 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 10313 CELLMAXRESUMELIMITf, 10314 holcoscellmaxlimit7_cellmaxlimit_down_1 - 10315 ethernet_mtu_cell); 10316 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 10317 port, 7, rval); 10318 10319 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 10320 for (index = 0; index <= 6; index++) { 10321 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10322 port, index, &rval); 10323 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10324 CELLMAXRESUMELIMITf, 10325 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_1 - 10326 ethernet_mtu_cell); 10327 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10328 port, index, rval); 10329 } 10330 10331 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 10332 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10333 port, 7, &rval); 10334 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10335 CELLMAXRESUMELIMITf, 10336 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_1 - 10337 ethernet_mtu_cell); 10338 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10339 port, 7, rval); 10340 10341 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 10342 for (index = 8; index <= 63; index++) { 10343 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10344 port, index, &rval); 10345 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10346 CELLMAXRESUMELIMITf, 10347 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_1 - 10348 ethernet_mtu_cell); 10349 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10350 port, index, rval); 10351 } 10352 10353 /* DYNCELLLIMITr, index 0 */ 10354 soc_reg32_get(unit, DYNCELLLIMITr, 10355 port, 0, &rval); 10356 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 10357 DYNCELLSETLIMITf, 10358 shared_space_cells); 10359 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 10360 DYNCELLRESETLIMITf, 10361 dyncelllimit_dyncellsetlimit_down_1 - 10362 (ethernet_mtu_cell * 2)); 10363 soc_reg32_set(unit, DYNCELLLIMITr, 10364 port, 0, rval); 10365 10366 /* COLOR_DROP_ENr, index 0 */ 10367 soc_reg32_get(unit, COLOR_DROP_ENr, 10368 port, 0, &rval); 10369 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 10370 COLOR_DROP_ENf, 10371 0); 10372 soc_reg32_set(unit, COLOR_DROP_ENr, 10373 port, 0, rval); 10374 10375 /* COLOR_DROP_EN_QLAYERr, index 0 */ 10376 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 10377 port, 0, &rval); 10378 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 10379 COLOR_DROP_ENf, 10380 0); 10381 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 10382 port, 0, rval); 10383 10384 /* HOLCOSPKTSETLIMIT_QGROUPr, index 0 ~ 7 */ 10385 for (index = 0; index <= 7; index++) { 10386 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QGROUPr, 10387 port, index, &rval); 10388 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, &rval, 10389 PKTSETLIMITf, 10390 numxqs_per_downlink_ports_and_cpu_port - 1); 10391 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, 10392 port, index, rval); 10393 } 10394 10395 /* HOLCOSPKTRESETLIMIT_QGROUPr, index 0 ~ 7 */ 10396 for (index = 0; index <= 7; index++) { 10397 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 10398 port, index, &rval); 10399 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, &rval, 10400 PKTRESETLIMITf, 10401 holcospktsetlimit_qgroup0_pktsetlimit_down_1 - 1); 10402 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 10403 port, index, rval); 10404 } 10405 10406 /* CNGCOSPKTLIMIT0_QGROUPr, index 0 ~ 7 */ 10407 for (index = 0; index <= 7; index++) { 10408 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QGROUPr, 10409 port, index, &rval); 10410 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QGROUPr, &rval, 10411 CNGPKTSETLIMIT0f, 10412 numxqs_per_downlink_ports_and_cpu_port - 1); 10413 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QGROUPr, 10414 port, index, rval); 10415 } 10416 10417 /* CNGCOSPKTLIMIT1_QGROUPr, index 0 ~ 7 */ 10418 for (index = 0; index <= 7; index++) { 10419 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QGROUPr, 10420 port, index, &rval); 10421 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QGROUPr, &rval, 10422 CNGPKTSETLIMIT1f, 10423 numxqs_per_downlink_ports_and_cpu_port - 1); 10424 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QGROUPr, 10425 port, index, rval); 10426 } 10427 10428 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 10429 for (index = 0; index <= 7; index++) { 10430 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 10431 port, index, &rval); 10432 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 10433 CELLMAXLIMITf, 10434 ceiling_func(total_advertised_cell_memory, 10435 queue_port_limit_ratio)); 10436 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 10437 port, index, rval); 10438 } 10439 10440 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 10441 for (index = 0; index <= 7; index++) { 10442 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 10443 port, index, &rval); 10444 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 10445 CELLMAXRESUMELIMITf, 10446 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_1 - 10447 ethernet_mtu_cell); 10448 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 10449 port, index, rval); 10450 } 10451 10452 /* COLOR_DROP_EN_QGROUPr, index 0 */ 10453 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 10454 port, 0, &rval); 10455 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 10456 COLOR_DROP_ENf, 10457 0); 10458 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 10459 port, 0, rval); 10460 10461 /* SHARED_POOL_CTRLr, index 0 */ 10462 soc_reg32_get(unit, SHARED_POOL_CTRLr, 10463 port, 0, &rval); 10464 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 10465 DYNAMIC_COS_DROP_ENf, 10466 255); 10467 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 10468 SHARED_POOL_DISCARD_ENf, 10469 255); 10470 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 10471 SHARED_POOL_XOFF_ENf, 10472 0); 10473 soc_reg32_set(unit, SHARED_POOL_CTRLr, 10474 port, 0, rval); 10475 10476 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 10477 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 10478 port, 0, &rval); 10479 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 10480 DYNAMIC_COS_DROP_ENf, 10481 0xFFFFFF); 10482 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 10483 port, 0, rval); 10484 10485 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 10486 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 10487 port, 0, &rval); 10488 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 10489 DYNAMIC_COS_DROP_ENf, 10490 0xFFFFFFFF); 10491 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 10492 port, 0, rval); 10493 } 10494 10495 /* port-based : downlink 2.5G */ 10496 SOC_PBMP_ITER(pbmp_downlink_2dot5g, port) { 10497 /* PG_CTRL0r, index 0 */ 10498 soc_reg32_get(unit, PG_CTRL0r, 10499 port, 0, &rval); 10500 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10501 PPFC_PG_ENf, 10502 0); 10503 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10504 PRI0_GRPf, 10505 0); 10506 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10507 PRI1_GRPf, 10508 1); 10509 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10510 PRI2_GRPf, 10511 2); 10512 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10513 PRI3_GRPf, 10514 3); 10515 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10516 PRI4_GRPf, 10517 4); 10518 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10519 PRI5_GRPf, 10520 5); 10521 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10522 PRI6_GRPf, 10523 6); 10524 soc_reg_field_set(unit, PG_CTRL0r, &rval, 10525 PRI7_GRPf, 10526 7); 10527 soc_reg32_set(unit, PG_CTRL0r, 10528 port, 0, rval); 10529 10530 /* PG_CTRL1r, index 0 */ 10531 soc_reg32_get(unit, PG_CTRL1r, 10532 port, 0, &rval); 10533 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10534 PRI8_GRPf, 10535 7); 10536 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10537 PRI9_GRPf, 10538 7); 10539 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10540 PRI10_GRPf, 10541 7); 10542 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10543 PRI11_GRPf, 10544 7); 10545 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10546 PRI12_GRPf, 10547 7); 10548 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10549 PRI13_GRPf, 10550 7); 10551 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10552 PRI14_GRPf, 10553 7); 10554 soc_reg_field_set(unit, PG_CTRL1r, &rval, 10555 PRI15_GRPf, 10556 7); 10557 soc_reg32_set(unit, PG_CTRL1r, 10558 port, 0, rval); 10559 10560 /* PG2TCr, index 0 ~ 7 */ 10561 for (index = 0; index <= 7; index++) { 10562 soc_reg32_get(unit, PG2TCr, 10563 port, index, &rval); 10564 soc_reg_field_set(unit, PG2TCr, &rval, 10565 PG_BMPf, 10566 0); 10567 soc_reg32_set(unit, PG2TCr, 10568 port, index, rval); 10569 } 10570 10571 /* IBPPKTSETLIMITr, index 0 */ 10572 soc_reg32_get(unit, IBPPKTSETLIMITr, 10573 port, 0, &rval); 10574 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 10575 PKTSETLIMITf, 10576 xoff_packet_thresholds_per_port_downlink_port); 10577 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 10578 RESETLIMITSELf, 10579 3); 10580 soc_reg32_set(unit, IBPPKTSETLIMITr, 10581 port, 0, rval); 10582 10583 /* MMU_FC_RX_ENr, index 0 */ 10584 soc_reg32_get(unit, MMU_FC_RX_ENr, 10585 port, 0, &rval); 10586 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 10587 MMU_FC_RX_ENABLEf, 10588 0); 10589 soc_reg32_set(unit, MMU_FC_RX_ENr, 10590 port, 0, rval); 10591 10592 /* MMU_FC_TX_ENr, index 0 */ 10593 soc_reg32_get(unit, MMU_FC_TX_ENr, 10594 port, 0, &rval); 10595 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 10596 MMU_FC_TX_ENABLEf, 10597 0); 10598 soc_reg32_set(unit, MMU_FC_TX_ENr, 10599 port, 0, rval); 10600 10601 /* PGCELLLIMITr, index 0 ~ 6 */ 10602 for (index = 0; index <= 6; index++) { 10603 soc_reg32_get(unit, PGCELLLIMITr, 10604 port, index, &rval); 10605 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 10606 CELLSETLIMITf, 10607 xoff_cell_threshold_all_uplink_ports); 10608 soc_reg32_set(unit, PGCELLLIMITr, 10609 port, index, rval); 10610 } 10611 10612 /* PGCELLLIMITr, index 7 */ 10613 soc_reg32_get(unit, PGCELLLIMITr, 10614 port, 7, &rval); 10615 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 10616 CELLSETLIMITf, 10617 xoff_cell_thresholds_per_port_2dot5g_downlink_ports); 10618 soc_reg32_set(unit, PGCELLLIMITr, 10619 port, 7, rval); 10620 10621 /* PGCELLLIMITr, index 0 ~ 6 */ 10622 for (index = 0; index <= 6; index++) { 10623 soc_reg32_get(unit, PGCELLLIMITr, 10624 port, index, &rval); 10625 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 10626 CELLRESETLIMITf, 10627 xoff_cell_threshold_all_uplink_ports); 10628 soc_reg32_set(unit, PGCELLLIMITr, 10629 port, index, rval); 10630 } 10631 10632 /* PGCELLLIMITr, index 7 */ 10633 soc_reg32_get(unit, PGCELLLIMITr, 10634 port, 7, &rval); 10635 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 10636 CELLRESETLIMITf, 10637 xoff_cell_thresholds_per_port_2dot5g_downlink_ports); 10638 soc_reg32_set(unit, PGCELLLIMITr, 10639 port, 7, rval); 10640 10641 /* PGDISCARDSETLIMITr, index 0 ~ 6 */ 10642 for (index = 0; index <= 6; index++) { 10643 soc_reg32_get(unit, PGDISCARDSETLIMITr, 10644 port, index, &rval); 10645 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 10646 DISCARDSETLIMITf, 10647 discard_limit_per_port_pg_downlink_port); 10648 soc_reg32_set(unit, PGDISCARDSETLIMITr, 10649 port, index, rval); 10650 } 10651 10652 /* PGDISCARDSETLIMITr, index 7 */ 10653 soc_reg32_get(unit, PGDISCARDSETLIMITr, 10654 port, 7, &rval); 10655 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 10656 DISCARDSETLIMITf, 10657 discard_limit_per_port_pg_uplink_2dot5g_port); 10658 soc_reg32_set(unit, PGDISCARDSETLIMITr, 10659 port, 7, rval); 10660 10661 /* HOLCOSMINXQCNTr, index 0 ~ 7 */ 10662 for (index = 0; index <= 7; index++) { 10663 soc_reg32_get(unit, HOLCOSMINXQCNTr, 10664 port, index, &rval); 10665 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 10666 HOLCOSMINXQCNTf, 10667 egress_xq_min_reserve_lossy_ports); 10668 soc_reg32_set(unit, HOLCOSMINXQCNTr, 10669 port, index, rval); 10670 } 10671 10672 /* HOLCOSMINXQCNT_QLAYERr, index 0 ~ 7 */ 10673 for (index = 0; index <= 7; index++) { 10674 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 10675 port, index, &rval); 10676 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 10677 HOLCOSMINXQCNTf, 10678 egress_xq_min_reserve_lossy_ports); 10679 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 10680 port, index, rval); 10681 } 10682 10683 /* HOLCOSMINXQCNT_QLAYERr, index 8 ~ 63 */ 10684 for (index = 8; index <= 63; index++) { 10685 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 10686 port, index, &rval); 10687 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 10688 HOLCOSMINXQCNTf, 10689 0); 10690 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 10691 port, index, rval); 10692 } 10693 10694 /* HOLCOSPKTSETLIMITr, index 0 ~ 7 */ 10695 for (index = 0; index <= 7; index++) { 10696 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 10697 port, index, &rval); 10698 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 10699 PKTSETLIMITf, 10700 shared_xqs_per_downlink_port + 10701 egress_xq_min_reserve_lossy_ports); 10702 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 10703 port, index, rval); 10704 } 10705 10706 /* HOLCOSPKTSETLIMIT_QLAYERr, index 0 ~ 7 */ 10707 for (index = 0; index <= 7; index++) { 10708 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10709 port, index, &rval); 10710 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 10711 PKTSETLIMITf, 10712 shared_xqs_per_downlink_port + 10713 egress_xq_min_reserve_lossy_ports); 10714 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10715 port, index, rval); 10716 } 10717 10718 /* HOLCOSPKTSETLIMIT_QLAYERr, index 8 ~ 63 */ 10719 for (index = 8; index <= 63; index++) { 10720 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10721 port, index, &rval); 10722 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 10723 PKTSETLIMITf, 10724 shared_xqs_per_downlink_port + 10725 holcosminxqcnt_qlayer8_holcosminxqcnt_down_1); 10726 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 10727 port, index, rval); 10728 } 10729 10730 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 10731 for (index = 0; index <= 6; index++) { 10732 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 10733 port, index, &rval); 10734 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 10735 PKTRESETLIMITf, 10736 holcospktsetlimit0_pktsetlimit_down_2dot5 - 1); 10737 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 10738 port, index, rval); 10739 } 10740 10741 /* HOLCOSPKTRESETLIMITr, index 7 */ 10742 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 10743 port, 7, &rval); 10744 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 10745 PKTRESETLIMITf, 10746 holcospktsetlimit7_pktsetlimit_down_2dot5 - 1); 10747 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 10748 port, 7, rval); 10749 10750 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 0 ~ 6 */ 10751 for (index = 0; index <= 6; index++) { 10752 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10753 port, index, &rval); 10754 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 10755 PKTRESETLIMITf, 10756 holcospktsetlimit_qlayer0_pktsetlimit_down_2dot5 10757 - 1); 10758 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10759 port, index, rval); 10760 } 10761 10762 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 7 */ 10763 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10764 port, 7, &rval); 10765 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 10766 PKTRESETLIMITf, 10767 holcospktsetlimit_qlayer7_pktsetlimit_down_2dot5 - 1); 10768 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10769 port, 7, rval); 10770 10771 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 8 ~ 63 */ 10772 for (index = 8; index <= 63; index++) { 10773 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10774 port, index, &rval); 10775 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 10776 PKTRESETLIMITf, 10777 holcospktsetlimit_qlayer8_pktsetlimit_down_2dot5 10778 - 1); 10779 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 10780 port, index, rval); 10781 } 10782 10783 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 10784 for (index = 0; index <= 7; index++) { 10785 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 10786 port, index, &rval); 10787 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 10788 CNGPKTSETLIMIT0f, 10789 numxqs_per_downlink_ports_and_cpu_port - 1); 10790 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 10791 port, index, rval); 10792 } 10793 10794 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 10795 for (index = 0; index <= 7; index++) { 10796 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 10797 port, index, &rval); 10798 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 10799 CNGPKTSETLIMIT1f, 10800 numxqs_per_downlink_ports_and_cpu_port - 1); 10801 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 10802 port, index, rval); 10803 } 10804 10805 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 10806 for (index = 0; index <= 63; index++) { 10807 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 10808 port, index, &rval); 10809 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 10810 CNGPKTSETLIMIT0f, 10811 numxqs_per_downlink_ports_and_cpu_port - 1); 10812 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 10813 port, index, rval); 10814 } 10815 10816 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 10817 for (index = 0; index <= 63; index++) { 10818 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 10819 port, index, &rval); 10820 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 10821 CNGPKTSETLIMIT1f, 10822 numxqs_per_downlink_ports_and_cpu_port - 1); 10823 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 10824 port, index, rval); 10825 } 10826 10827 /* CNGPORTPKTLIMIT0r, index 0 */ 10828 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 10829 port, 0, &rval); 10830 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 10831 CNGPORTPKTLIMIT0f, 10832 numxqs_per_downlink_ports_and_cpu_port - 1); 10833 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 10834 port, 0, rval); 10835 10836 /* CNGPORTPKTLIMIT1r, index 0 */ 10837 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 10838 port, 0, &rval); 10839 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 10840 CNGPORTPKTLIMIT1f, 10841 numxqs_per_downlink_ports_and_cpu_port - 1); 10842 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 10843 port, 0, rval); 10844 10845 /* DYNXQCNTPORTr, index 0 */ 10846 soc_reg32_get(unit, DYNXQCNTPORTr, 10847 port, 0, &rval); 10848 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 10849 DYNXQCNTPORTf, 10850 shared_xqs_per_downlink_port - skidmarker - prefetch); 10851 soc_reg32_set(unit, DYNXQCNTPORTr, 10852 port, 0, rval); 10853 10854 /* DYNRESETLIMPORTr, index 0 */ 10855 soc_reg32_get(unit, DYNRESETLIMPORTr, 10856 port, 0, &rval); 10857 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 10858 DYNRESETLIMPORTf, 10859 dynxqcntport_dynxqcntport_down_2dot5 - 2); 10860 soc_reg32_set(unit, DYNRESETLIMPORTr, 10861 port, 0, rval); 10862 10863 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 10864 for (index = 0; index <= 7; index++) { 10865 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 10866 port, index, &rval); 10867 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 10868 CELLSETLIMITf, 10869 egress_queue_min_reserve_downlink_ports_lossy); 10870 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 10871 port, index, rval); 10872 } 10873 10874 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 7 */ 10875 for (index = 0; index <= 7; index++) { 10876 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10877 port, index, &rval); 10878 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10879 CELLSETLIMITf, 10880 egress_queue_min_reserve_downlink_ports_lossy); 10881 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10882 port, index, rval); 10883 } 10884 10885 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 10886 for (index = 8; index <= 63; index++) { 10887 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10888 port, index, &rval); 10889 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10890 CELLSETLIMITf, 10891 0); 10892 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10893 port, index, rval); 10894 } 10895 10896 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 10897 for (index = 0; index <= 7; index++) { 10898 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 10899 port, index, &rval); 10900 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 10901 CELLRESETLIMITf, 10902 egress_queue_min_reserve_downlink_ports_lossy); 10903 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 10904 port, index, rval); 10905 } 10906 10907 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 7 */ 10908 for (index = 0; index <= 7; index++) { 10909 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10910 port, index, &rval); 10911 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10912 CELLRESETLIMITf, 10913 egress_queue_min_reserve_downlink_ports_lossy); 10914 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10915 port, index, rval); 10916 } 10917 10918 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 10919 for (index = 8; index <= 63; index++) { 10920 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10921 port, index, &rval); 10922 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 10923 CELLRESETLIMITf, 10924 0); 10925 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 10926 port, index, rval); 10927 } 10928 10929 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 10930 for (index = 0; index <= 6; index++) { 10931 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 10932 port, index, &rval); 10933 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 10934 CELLMAXLIMITf, 10935 ceiling_func(shared_space_cells, 10936 queue_port_limit_ratio) + 10937 lwmcoscellsetlimit0_cellsetlimit_down_2dot5); 10938 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 10939 port, index, rval); 10940 } 10941 10942 /* HOLCOSCELLMAXLIMITr, index 7 */ 10943 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 10944 port, 7, &rval); 10945 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 10946 CELLMAXLIMITf, 10947 ceiling_func(shared_space_cells, 10948 queue_port_limit_ratio) + 10949 lwmcoscellsetlimit7_cellsetlimit_down_2dot5); 10950 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 10951 port, 7, rval); 10952 10953 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 10954 for (index = 0; index <= 6; index++) { 10955 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10956 port, index, &rval); 10957 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10958 CELLMAXLIMITf, 10959 ceiling_func(shared_space_cells, 10960 queue_port_limit_ratio) + 10961 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5); 10962 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10963 port, index, rval); 10964 } 10965 10966 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 10967 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10968 port, 7, &rval); 10969 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10970 CELLMAXLIMITf, 10971 ceiling_func(shared_space_cells, 10972 queue_port_limit_ratio) + 10973 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5); 10974 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10975 port, 7, rval); 10976 10977 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 10978 for (index = 8; index <= 63; index++) { 10979 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10980 port, index, &rval); 10981 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 10982 CELLMAXLIMITf, 10983 ceiling_func(shared_space_cells, 10984 queue_port_limit_ratio) + 10985 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5); 10986 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 10987 port, index, rval); 10988 } 10989 10990 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 10991 for (index = 0; index <= 6; index++) { 10992 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 10993 port, index, &rval); 10994 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 10995 CELLMAXRESUMELIMITf, 10996 holcoscellmaxlimit0_cellmaxlimit_down_2dot5 - 10997 ethernet_mtu_cell); 10998 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 10999 port, index, rval); 11000 } 11001 11002 /* HOLCOSCELLMAXLIMITr, index 7 */ 11003 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 11004 port, 7, &rval); 11005 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 11006 CELLMAXRESUMELIMITf, 11007 holcoscellmaxlimit7_cellmaxlimit_down_2dot5 - 11008 ethernet_mtu_cell); 11009 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 11010 port, 7, rval); 11011 11012 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 11013 for (index = 0; index <= 6; index++) { 11014 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 11015 port, index, &rval); 11016 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 11017 CELLMAXRESUMELIMITf, 11018 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_2dot5 - 11019 ethernet_mtu_cell); 11020 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 11021 port, index, rval); 11022 } 11023 11024 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 11025 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 11026 port, 7, &rval); 11027 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 11028 CELLMAXRESUMELIMITf, 11029 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_2dot5 - 11030 ethernet_mtu_cell); 11031 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 11032 port, 7, rval); 11033 11034 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 11035 for (index = 8; index <= 63; index++) { 11036 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 11037 port, index, &rval); 11038 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 11039 CELLMAXRESUMELIMITf, 11040 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_2dot5 - 11041 ethernet_mtu_cell); 11042 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 11043 port, index, rval); 11044 } 11045 11046 /* DYNCELLLIMITr, index 0 */ 11047 soc_reg32_get(unit, DYNCELLLIMITr, 11048 port, 0, &rval); 11049 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 11050 DYNCELLSETLIMITf, 11051 shared_space_cells); 11052 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 11053 DYNCELLRESETLIMITf, 11054 dyncelllimit_dyncellsetlimit_down_2dot5 - 11055 (ethernet_mtu_cell * 2)); 11056 soc_reg32_set(unit, DYNCELLLIMITr, 11057 port, 0, rval); 11058 11059 /* COLOR_DROP_ENr, index 0 */ 11060 soc_reg32_get(unit, COLOR_DROP_ENr, 11061 port, 0, &rval); 11062 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 11063 COLOR_DROP_ENf, 11064 0); 11065 soc_reg32_set(unit, COLOR_DROP_ENr, 11066 port, 0, rval); 11067 11068 /* COLOR_DROP_EN_QLAYERr, index 0 */ 11069 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 11070 port, 0, &rval); 11071 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 11072 COLOR_DROP_ENf, 11073 0); 11074 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 11075 port, 0, rval); 11076 11077 /* HOLCOSPKTSETLIMIT_QGROUPr, index 0 ~ 7 */ 11078 for (index = 0; index <= 7; index++) { 11079 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QGROUPr, 11080 port, index, &rval); 11081 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, &rval, 11082 PKTSETLIMITf, 11083 numxqs_per_downlink_ports_and_cpu_port - 1); 11084 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, 11085 port, index, rval); 11086 } 11087 11088 /* HOLCOSPKTRESETLIMIT_QGROUPr, index 0 ~ 7 */ 11089 for (index = 0; index <= 7; index++) { 11090 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 11091 port, index, &rval); 11092 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, &rval, 11093 PKTRESETLIMITf, 11094 holcospktsetlimit_qgroup0_pktsetlimit_down_2dot5 11095 - 1); 11096 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 11097 port, index, rval); 11098 } 11099 11100 /* CNGCOSPKTLIMIT0_QGROUPr, index 0 ~ 7 */ 11101 for (index = 0; index <= 7; index++) { 11102 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QGROUPr, 11103 port, index, &rval); 11104 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QGROUPr, &rval, 11105 CNGPKTSETLIMIT0f, 11106 numxqs_per_downlink_ports_and_cpu_port - 1); 11107 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QGROUPr, 11108 port, index, rval); 11109 } 11110 11111 /* CNGCOSPKTLIMIT1_QGROUPr, index 0 ~ 7 */ 11112 for (index = 0; index <= 7; index++) { 11113 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QGROUPr, 11114 port, index, &rval); 11115 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QGROUPr, &rval, 11116 CNGPKTSETLIMIT1f, 11117 numxqs_per_downlink_ports_and_cpu_port - 1); 11118 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QGROUPr, 11119 port, index, rval); 11120 } 11121 11122 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 11123 for (index = 0; index <= 7; index++) { 11124 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 11125 port, index, &rval); 11126 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 11127 CELLMAXLIMITf, 11128 ceiling_func(total_advertised_cell_memory, 11129 queue_port_limit_ratio)); 11130 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 11131 port, index, rval); 11132 } 11133 11134 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 11135 for (index = 0; index <= 7; index++) { 11136 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 11137 port, index, &rval); 11138 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 11139 CELLMAXRESUMELIMITf, 11140 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_2dot5 - 11141 ethernet_mtu_cell); 11142 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 11143 port, index, rval); 11144 } 11145 11146 /* COLOR_DROP_EN_QGROUPr, index 0 */ 11147 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 11148 port, 0, &rval); 11149 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 11150 COLOR_DROP_ENf, 11151 0); 11152 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 11153 port, 0, rval); 11154 11155 /* SHARED_POOL_CTRLr, index 0 */ 11156 soc_reg32_get(unit, SHARED_POOL_CTRLr, 11157 port, 0, &rval); 11158 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 11159 DYNAMIC_COS_DROP_ENf, 11160 255); 11161 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 11162 SHARED_POOL_DISCARD_ENf, 11163 255); 11164 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 11165 SHARED_POOL_XOFF_ENf, 11166 0); 11167 soc_reg32_set(unit, SHARED_POOL_CTRLr, 11168 port, 0, rval); 11169 11170 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 11171 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 11172 port, 0, &rval); 11173 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 11174 DYNAMIC_COS_DROP_ENf, 11175 0xFFFFFF); 11176 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 11177 port, 0, rval); 11178 11179 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 11180 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 11181 port, 0, &rval); 11182 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 11183 DYNAMIC_COS_DROP_ENf, 11184 0xFFFFFFFF); 11185 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 11186 port, 0, rval); 11187 } 11188 11189 11190 /* port-based : cpu port*/ 11191 SOC_PBMP_ITER(pbmp_cpu, port) { 11192 /* PG_CTRL0r, index 0 */ 11193 soc_reg32_get(unit, PG_CTRL0r, 11194 port, 0, &rval); 11195 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11196 PPFC_PG_ENf, 11197 0); 11198 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11199 PRI0_GRPf, 11200 0); 11201 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11202 PRI1_GRPf, 11203 1); 11204 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11205 PRI2_GRPf, 11206 2); 11207 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11208 PRI3_GRPf, 11209 3); 11210 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11211 PRI4_GRPf, 11212 4); 11213 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11214 PRI5_GRPf, 11215 5); 11216 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11217 PRI6_GRPf, 11218 6); 11219 soc_reg_field_set(unit, PG_CTRL0r, &rval, 11220 PRI7_GRPf, 11221 7); 11222 soc_reg32_set(unit, PG_CTRL0r, 11223 port, 0, rval); 11224 11225 /* PG_CTRL1r, index 0 */ 11226 soc_reg32_get(unit, PG_CTRL1r, 11227 port, 0, &rval); 11228 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11229 PRI8_GRPf, 11230 7); 11231 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11232 PRI9_GRPf, 11233 7); 11234 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11235 PRI10_GRPf, 11236 7); 11237 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11238 PRI11_GRPf, 11239 7); 11240 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11241 PRI12_GRPf, 11242 7); 11243 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11244 PRI13_GRPf, 11245 7); 11246 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11247 PRI14_GRPf, 11248 7); 11249 soc_reg_field_set(unit, PG_CTRL1r, &rval, 11250 PRI15_GRPf, 11251 7); 11252 soc_reg32_set(unit, PG_CTRL1r, 11253 port, 0, rval); 11254 11255 /* PG2TCr, index 0 ~ 7 */ 11256 for (index = 0; index <= 7; index++) { 11257 soc_reg32_get(unit, PG2TCr, 11258 port, index, &rval); 11259 soc_reg_field_set(unit, PG2TCr, &rval, 11260 PG_BMPf, 11261 0); 11262 soc_reg32_set(unit, PG2TCr, 11263 port, index, rval); 11264 } 11265 11266 /* IBPPKTSETLIMITr, index 0 */ 11267 soc_reg32_get(unit, IBPPKTSETLIMITr, 11268 port, 0, &rval); 11269 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 11270 PKTSETLIMITf, 11271 xoff_packet_thresholds_per_port_uplink_port); 11272 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 11273 RESETLIMITSELf, 11274 3); 11275 soc_reg32_set(unit, IBPPKTSETLIMITr, 11276 port, 0, rval); 11277 11278 /* MMU_FC_RX_ENr, index 0 */ 11279 soc_reg32_get(unit, MMU_FC_RX_ENr, 11280 port, 0, &rval); 11281 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 11282 MMU_FC_RX_ENABLEf, 11283 0); 11284 soc_reg32_set(unit, MMU_FC_RX_ENr, 11285 port, 0, rval); 11286 11287 /* MMU_FC_TX_ENr, index 0 */ 11288 soc_reg32_get(unit, MMU_FC_TX_ENr, 11289 port, 0, &rval); 11290 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 11291 MMU_FC_TX_ENABLEf, 11292 0); 11293 soc_reg32_set(unit, MMU_FC_TX_ENr, 11294 port, 0, rval); 11295 11296 /* PGCELLLIMITr, index 0 ~ 7 */ 11297 for (index = 0; index <= 7; index++) { 11298 soc_reg32_get(unit, PGCELLLIMITr, 11299 port, index, &rval); 11300 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 11301 CELLSETLIMITf, 11302 xoff_cell_threshold_all_uplink_ports); 11303 soc_reg32_set(unit, PGCELLLIMITr, 11304 port, index, rval); 11305 } 11306 11307 /* PGCELLLIMITr, index 0 ~ 7 */ 11308 for (index = 0; index <= 7; index++) { 11309 soc_reg32_get(unit, PGCELLLIMITr, 11310 port, index, &rval); 11311 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 11312 CELLRESETLIMITf, 11313 xoff_cell_threshold_all_uplink_ports); 11314 soc_reg32_set(unit, PGCELLLIMITr, 11315 port, index, rval); 11316 } 11317 11318 /* PGDISCARDSETLIMITr, index 0 ~ 7 */ 11319 for (index = 0; index <= 7; index++) { 11320 soc_reg32_get(unit, PGDISCARDSETLIMITr, 11321 port, index, &rval); 11322 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 11323 DISCARDSETLIMITf, 11324 discard_limit_per_port_pg_downlink_port); 11325 soc_reg32_set(unit, PGDISCARDSETLIMITr, 11326 port, index, rval); 11327 } 11328 11329 /* HOLCOSMINXQCNTr, index 0 ~ 7 */ 11330 for (index = 0; index <= 7; index++) { 11331 soc_reg32_get(unit, HOLCOSMINXQCNTr, 11332 port, index, &rval); 11333 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 11334 HOLCOSMINXQCNTf, 11335 egress_queue_min_reserve_cpu_ports); 11336 soc_reg32_set(unit, HOLCOSMINXQCNTr, 11337 port, index, rval); 11338 } 11339 11340 /* HOLCOSPKTSETLIMITr, index 0 ~ 6 */ 11341 for (index = 0; index <= 6; index++) { 11342 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 11343 port, index, &rval); 11344 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 11345 PKTSETLIMITf, 11346 shared_xqs_per_downlink_port + 11347 holcosminxqcnt0_holcosminxqcnt_cpu); 11348 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 11349 port, index, rval); 11350 } 11351 11352 /* HOLCOSPKTSETLIMITr, index 7 */ 11353 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 11354 port, 7, &rval); 11355 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 11356 PKTSETLIMITf, 11357 shared_xqs_per_downlink_port + 11358 holcosminxqcnt7_holcosminxqcnt_cpu); 11359 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 11360 port, 7, rval); 11361 11362 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 11363 for (index = 0; index <= 6; index++) { 11364 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 11365 port, index, &rval); 11366 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 11367 PKTRESETLIMITf, 11368 holcospktsetlimit0_pktsetlimit_cpu - 1); 11369 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 11370 port, index, rval); 11371 } 11372 11373 /* HOLCOSPKTRESETLIMITr, index 7 */ 11374 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 11375 port, 7, &rval); 11376 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 11377 PKTRESETLIMITf, 11378 holcospktsetlimit7_pktsetlimit_cpu - 1); 11379 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 11380 port, 7, rval); 11381 11382 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 11383 for (index = 0; index <= 7; index++) { 11384 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 11385 port, index, &rval); 11386 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 11387 CNGPKTSETLIMIT0f, 11388 numxqs_per_downlink_ports_and_cpu_port - 1); 11389 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 11390 port, index, rval); 11391 } 11392 11393 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 11394 for (index = 0; index <= 7; index++) { 11395 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 11396 port, index, &rval); 11397 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 11398 CNGPKTSETLIMIT1f, 11399 numxqs_per_downlink_ports_and_cpu_port - 1); 11400 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 11401 port, index, rval); 11402 } 11403 11404 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 11405 for (index = 0; index <= 63; index++) { 11406 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 11407 port, index, &rval); 11408 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 11409 CNGPKTSETLIMIT0f, 11410 numxqs_per_downlink_ports_and_cpu_port - 1); 11411 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 11412 port, index, rval); 11413 } 11414 11415 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 11416 for (index = 0; index <= 63; index++) { 11417 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 11418 port, index, &rval); 11419 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 11420 CNGPKTSETLIMIT1f, 11421 numxqs_per_downlink_ports_and_cpu_port - 1); 11422 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 11423 port, index, rval); 11424 } 11425 11426 /* CNGPORTPKTLIMIT0r, index 0 */ 11427 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 11428 port, 0, &rval); 11429 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 11430 CNGPORTPKTLIMIT0f, 11431 numxqs_per_downlink_ports_and_cpu_port - 1); 11432 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 11433 port, 0, rval); 11434 11435 /* CNGPORTPKTLIMIT1r, index 0 */ 11436 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 11437 port, 0, &rval); 11438 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 11439 CNGPORTPKTLIMIT1f, 11440 numxqs_per_downlink_ports_and_cpu_port - 1); 11441 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 11442 port, 0, rval); 11443 11444 /* DYNXQCNTPORTr, index 0 */ 11445 soc_reg32_get(unit, DYNXQCNTPORTr, 11446 port, 0, &rval); 11447 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 11448 DYNXQCNTPORTf, 11449 shared_xqs_per_downlink_port - skidmarker - prefetch); 11450 soc_reg32_set(unit, DYNXQCNTPORTr, 11451 port, 0, rval); 11452 11453 /* DYNRESETLIMPORTr, index 0 */ 11454 soc_reg32_get(unit, DYNRESETLIMPORTr, 11455 port, 0, &rval); 11456 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 11457 DYNRESETLIMPORTf, 11458 dynxqcntport_dynxqcntport_cpu - 2); 11459 soc_reg32_set(unit, DYNRESETLIMPORTr, 11460 port, 0, rval); 11461 11462 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 11463 for (index = 0; index <= 7; index++) { 11464 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 11465 port, index, &rval); 11466 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 11467 CELLSETLIMITf, 11468 egress_queue_min_reserve_cpu_ports); 11469 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 11470 port, index, rval); 11471 } 11472 11473 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 11474 for (index = 0; index <= 7; index++) { 11475 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 11476 port, index, &rval); 11477 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 11478 CELLRESETLIMITf, 11479 egress_queue_min_reserve_cpu_ports); 11480 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 11481 port, index, rval); 11482 } 11483 11484 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 11485 for (index = 0; index <= 6; index++) { 11486 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 11487 port, index, &rval); 11488 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 11489 CELLMAXLIMITf, 11490 ceiling_func(shared_space_cells, 11491 queue_port_limit_ratio) + 11492 lwmcoscellsetlimit0_cellsetlimit_cpu); 11493 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 11494 port, index, rval); 11495 } 11496 11497 /* HOLCOSCELLMAXLIMITr, index 7 */ 11498 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 11499 port, 7, &rval); 11500 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 11501 CELLMAXLIMITf, 11502 ceiling_func(shared_space_cells, 11503 queue_port_limit_ratio) + 11504 lwmcoscellsetlimit7_cellsetlimit_cpu); 11505 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 11506 port, 7, rval); 11507 11508 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 11509 for (index = 0; index <= 6; index++) { 11510 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 11511 port, index, &rval); 11512 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 11513 CELLMAXRESUMELIMITf, 11514 holcoscellmaxlimit0_cellmaxlimit_cpu - 11515 ethernet_mtu_cell); 11516 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 11517 port, index, rval); 11518 } 11519 11520 /* HOLCOSCELLMAXLIMITr, index 7 */ 11521 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 11522 port, 7, &rval); 11523 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 11524 CELLMAXRESUMELIMITf, 11525 holcoscellmaxlimit7_cellmaxlimit_cpu - 11526 ethernet_mtu_cell); 11527 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 11528 port, 7, rval); 11529 11530 /* DYNCELLLIMITr, index 0 */ 11531 soc_reg32_get(unit, DYNCELLLIMITr, 11532 port, 0, &rval); 11533 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 11534 DYNCELLSETLIMITf, 11535 shared_space_cells); 11536 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 11537 DYNCELLRESETLIMITf, 11538 dyncelllimit_dyncellsetlimit_cpu - 11539 ethernet_mtu_cell * 2); 11540 soc_reg32_set(unit, DYNCELLLIMITr, 11541 port, 0, rval); 11542 11543 /* COLOR_DROP_ENr, index 0 */ 11544 soc_reg32_get(unit, COLOR_DROP_ENr, 11545 port, 0, &rval); 11546 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 11547 COLOR_DROP_ENf, 11548 0); 11549 soc_reg32_set(unit, COLOR_DROP_ENr, 11550 port, 0, rval); 11551 11552 /* COLOR_DROP_EN_QLAYERr, index 0 */ 11553 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 11554 port, 0, &rval); 11555 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 11556 COLOR_DROP_ENf, 11557 0); 11558 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 11559 port, 0, rval); 11560 11561 /* COLOR_DROP_EN_QGROUPr, index 0 */ 11562 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 11563 port, 0, &rval); 11564 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 11565 COLOR_DROP_ENf, 11566 0); 11567 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 11568 port, 0, rval); 11569 11570 /* SHARED_POOL_CTRLr, index 0 */ 11571 soc_reg32_get(unit, SHARED_POOL_CTRLr, 11572 port, 0, &rval); 11573 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 11574 DYNAMIC_COS_DROP_ENf, 11575 255); 11576 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 11577 SHARED_POOL_DISCARD_ENf, 11578 255); 11579 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 11580 SHARED_POOL_XOFF_ENf, 11581 0); 11582 soc_reg32_set(unit, SHARED_POOL_CTRLr, 11583 port, 0, rval); 11584 11585 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 11586 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 11587 port, 0, &rval); 11588 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 11589 DYNAMIC_COS_DROP_ENf, 11590 0xFFFFFF); 11591 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 11592 port, 0, rval); 11593 11594 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 11595 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 11596 port, 0, &rval); 11597 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 11598 DYNAMIC_COS_DROP_ENf, 11599 0xFFFFFFFF); 11600 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 11601 port, 0, rval); 11602 } 11603 return SOC_E_NONE; 11604 } 11605 11606 11607 STATIC int _soc_greyhound2_mmu_init_helper_lossless(int unit) 11608 { 11609 uint32 rval; 11610 int port, phy_port; 11611 int index; 11612 soc_info_t *si = &SOC_INFO(unit); 11613 soc_pbmp_t pbmp_cpu; 11614 soc_pbmp_t pbmp_uplink; 11615 soc_pbmp_t pbmp_downlink_1g; 11616 soc_pbmp_t pbmp_downlink_2dot5g; 11617 soc_pbmp_t pbmp_downlink_10g; 11618 11619 static int standard_jumbo_frame; 11620 static int cell_size; 11621 static int ethernet_mtu_cell; 11622 static int standard_jumbo_frame_cell; 11623 static int total_physical_memory; 11624 static int total_cell_memory_for_admission; 11625 static int number_of_used_memory_banks; 11626 static int reserved_for_cfap; 11627 static int skidmarker; 11628 static int prefetch; 11629 static int total_cell_memory; 11630 static int cfapfullsetpoint; 11631 static int total_advertised_cell_memory; 11632 static int number_of_uplink_ports; 11633 static int number_of_downlink_ports; 11634 static int flow_control_type_pause_0_pfc_1; 11635 static int queue_port_limit_ratio; 11636 static int headroom_for_1g_port; 11637 static int headroom_for_2dot5g_port; 11638 static int headroom_for_10g_port; 11639 static int headroom_for_20g_port; 11640 static int headroom_for_25g_port; 11641 static int headroom_for_40g_port; 11642 static int num_1g_ports_downlink_ports; 11643 static int num_2dot5g_ports_downlink_ports; 11644 static int num_10g_ports_downlink_ports; 11645 static int num_20g_ports_downlink_ports; 11646 static int num_25g_ports_downlink_ports; 11647 static int num_40g_ports_downlink_ports; 11648 static int mmu_xoff_pkt_threshold_uplink_ports; 11649 static int mmu_xoff_pkt_threshold_downlink_ports; 11650 static int mmu_xoff_cell_threshold_1g_port_downlink_ports; 11651 static int mmu_xoff_cell_threshold_2dot5g_port_downlink_ports; 11652 static int mmu_xoff_cell_threshold_10g_port_downlink_ports; 11653 static int mmu_xoff_cell_threshold_20g_port_downlink_ports; 11654 static int mmu_xoff_cell_threshold_25g_port_downlink_ports; 11655 static int mmu_xoff_cell_threshold_40g_port_downlink_ports; 11656 static int mmu_xoff_cell_threshold_all_uplink_ports; 11657 static int egress_xq_min_reserve_lossless_uplink_ports; 11658 static int egress_xq_min_reserve_lossless_downlink_ports; 11659 static int egress_xq_min_reserve_lossy_up_downlink_ports; 11660 static int egress_queue_min_reserve_uplink_ports_lossy; 11661 static int egress_queue_min_reserve_downlink_ports_lossy; 11662 static int egress_queue_min_reserve_uplink_ports_lossless; 11663 static int egress_queue_min_reserve_downlink_ports_lossless; 11664 static int egress_queue_min_reserve_cpu_ports; 11665 static int egress_xq_min_reserve_lossy_ports; 11666 static int num_active_pri_group_lossless; 11667 static int num_lossy_queues; 11668 static int num_cpu_queues; 11669 static int num_cpu_ports; 11670 static int numxqs_per_uplink_ports; 11671 static int numxqs_per_downlink_ports_and_cpu_port; 11672 static int xoff_cell_thresholds_per_port_1g_port_downlink_ports; 11673 static int xoff_cell_thresholds_per_port_2dot5g_downlink_ports; 11674 static int xoff_cell_thresholds_per_port_10g_port_downlink_ports; 11675 static int xoff_cell_threshold_all_uplink_ports; 11676 static int xoff_packet_thresholds_per_port_uplink_port; 11677 static int xoff_packet_thresholds_per_port_downlink_port; 11678 static int discard_limit_per_port_pg_uplink_1g_port; 11679 static int discard_limit_per_port_pg_uplink_2dot5g_port; 11680 static int discard_limit_per_port_pg_uplink_10g_port; 11681 static int discard_limit_per_port_pg_downlink_port; 11682 static int total_reserved_cells_for_uplink_ports; 11683 static int total_reserved_cells_for_downlink_ports; 11684 static int total_reserved_cells_for_cpu_port; 11685 static int total_reserved; 11686 static int shared_space_cells; 11687 static int reserved_xqs_per_uplink_port; 11688 static int shared_xqs_per_uplink_port; 11689 static int reserved_xqs_per_downlink_port; 11690 static int shared_xqs_per_downlink_port; 11691 static int cfapfullthreshold_cfapfullsetpoint_up; 11692 static int gbllimitsetlimit_gblcellsetlimit_up; 11693 static int totaldyncellsetlimit_totaldyncellsetlimit_up; 11694 static int holcosminxqcnt_qlayer8_holcosminxqcnt_up; 11695 static int holcospktsetlimit0_pktsetlimit_up; 11696 static int holcospktsetlimit7_pktsetlimit_up; 11697 static int holcospktsetlimit_qlayer0_pktsetlimit_up; 11698 static int holcospktsetlimit_qlayer7_pktsetlimit_up; 11699 static int holcospktsetlimit_qlayer8_pktsetlimit_up; 11700 static int dynxqcntport_dynxqcntport_up; 11701 static int lwmcoscellsetlimit0_cellsetlimit_up; 11702 static int lwmcoscellsetlimit7_cellsetlimit_up; 11703 static int lwmcoscellsetlimit_qlayer0_cellsetlimit_up; 11704 static int lwmcoscellsetlimit_qlayer7_cellsetlimit_up; 11705 static int lwmcoscellsetlimit_qlayer8_cellsetlimit_up; 11706 static int holcoscellmaxlimit0_cellmaxlimit_up; 11707 static int holcoscellmaxlimit7_cellmaxlimit_up; 11708 static int holcoscellmaxlimit_qlayer0_cellmaxlimit_up; 11709 static int holcoscellmaxlimit_qlayer7_cellmaxlimit_up; 11710 static int holcoscellmaxlimit_qlayer8_cellmaxlimit_up; 11711 static int dyncelllimit_dyncellsetlimit_up; 11712 static int holcospktsetlimit_qgroup0_pktsetlimit_up; 11713 static int holcoscellmaxlimit_qgroup0_cellmaxlimit_up; 11714 static int holcosminxqcnt_qlayer8_holcosminxqcnt_down_1; 11715 static int holcospktsetlimit0_pktsetlimit_down_1; 11716 static int holcospktsetlimit7_pktsetlimit_down_1; 11717 static int holcospktsetlimit_qlayer0_pktsetlimit_down_1; 11718 static int holcospktsetlimit_qlayer7_pktsetlimit_down_1; 11719 static int holcospktsetlimit_qlayer8_pktsetlimit_down_1; 11720 static int dynxqcntport_dynxqcntport_down_1; 11721 static int lwmcoscellsetlimit0_cellsetlimit_down_1; 11722 static int lwmcoscellsetlimit7_cellsetlimit_down_1; 11723 static int lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1; 11724 static int lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1; 11725 static int lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1; 11726 static int holcoscellmaxlimit0_cellmaxlimit_down_1; 11727 static int holcoscellmaxlimit7_cellmaxlimit_down_1; 11728 static int holcoscellmaxlimit_qlayer0_cellmaxlimit_down_1; 11729 static int holcoscellmaxlimit_qlayer7_cellmaxlimit_down_1; 11730 static int holcoscellmaxlimit_qlayer8_cellmaxlimit_down_1; 11731 static int dyncelllimit_dyncellsetlimit_down_1; 11732 static int holcospktsetlimit_qgroup0_pktsetlimit_down_1; 11733 static int holcoscellmaxlimit_qgroup0_cellmaxlimit_down_1; 11734 static int holcosminxqcnt_qlayer8_holcosminxqcnt_down_2dot5; 11735 static int holcospktsetlimit0_pktsetlimit_down_2dot5; 11736 static int holcospktsetlimit7_pktsetlimit_down_2dot5; 11737 static int holcospktsetlimit_qlayer0_pktsetlimit_down_2dot5; 11738 static int holcospktsetlimit_qlayer7_pktsetlimit_down_2dot5; 11739 static int holcospktsetlimit_qlayer8_pktsetlimit_down_2dot5; 11740 static int dynxqcntport_dynxqcntport_down_2dot5; 11741 static int lwmcoscellsetlimit0_cellsetlimit_down_2dot5; 11742 static int lwmcoscellsetlimit7_cellsetlimit_down_2dot5; 11743 static int lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5; 11744 static int lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5; 11745 static int lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5; 11746 static int holcoscellmaxlimit0_cellmaxlimit_down_2dot5; 11747 static int holcoscellmaxlimit7_cellmaxlimit_down_2dot5; 11748 static int holcoscellmaxlimit_qlayer0_cellmaxlimit_down_2dot5; 11749 static int holcoscellmaxlimit_qlayer7_cellmaxlimit_down_2dot5; 11750 static int holcoscellmaxlimit_qlayer8_cellmaxlimit_down_2dot5; 11751 static int dyncelllimit_dyncellsetlimit_down_2dot5; 11752 static int holcospktsetlimit_qgroup0_pktsetlimit_down_2dot5; 11753 static int holcoscellmaxlimit_qgroup0_cellmaxlimit_down_2dot5; 11754 static int holcosminxqcnt_qlayer8_holcosminxqcnt_down_10; 11755 static int holcospktsetlimit0_pktsetlimit_down_10; 11756 static int holcospktsetlimit7_pktsetlimit_down_10; 11757 static int holcospktsetlimit_qlayer0_pktsetlimit_down_10; 11758 static int holcospktsetlimit_qlayer7_pktsetlimit_down_10; 11759 static int holcospktsetlimit_qlayer8_pktsetlimit_down_10; 11760 static int dynxqcntport_dynxqcntport_down_10; 11761 static int lwmcoscellsetlimit0_cellsetlimit_down_10; 11762 static int lwmcoscellsetlimit7_cellsetlimit_down_10; 11763 static int lwmcoscellsetlimit_qlayer0_cellsetlimit_down_10; 11764 static int lwmcoscellsetlimit_qlayer7_cellsetlimit_down_10; 11765 static int lwmcoscellsetlimit_qlayer8_cellsetlimit_down_10; 11766 static int holcoscellmaxlimit0_cellmaxlimit_down_10; 11767 static int holcoscellmaxlimit7_cellmaxlimit_down_10; 11768 static int holcoscellmaxlimit_qlayer0_cellmaxlimit_down_10; 11769 static int holcoscellmaxlimit_qlayer7_cellmaxlimit_down_10; 11770 static int holcoscellmaxlimit_qlayer8_cellmaxlimit_down_10; 11771 static int dyncelllimit_dyncellsetlimit_down_10; 11772 static int holcospktsetlimit_qgroup0_pktsetlimit_down_10; 11773 static int holcoscellmaxlimit_qgroup0_cellmaxlimit_down_10; 11774 static int holcospktsetlimit0_pktsetlimit_cpu; 11775 static int holcospktsetlimit7_pktsetlimit_cpu; 11776 static int dynxqcntport_dynxqcntport_cpu; 11777 static int lwmcoscellsetlimit0_cellsetlimit_cpu; 11778 static int lwmcoscellsetlimit7_cellsetlimit_cpu; 11779 static int holcoscellmaxlimit0_cellmaxlimit_cpu; 11780 static int holcoscellmaxlimit7_cellmaxlimit_cpu; 11781 static int dyncelllimit_dyncellsetlimit_cpu; 11782 uint16 dev_id; 11783 uint8 rev_id; 11784 11785 soc_cm_get_id(unit, &dev_id, &rev_id); 11786 11787 /* setup port bitmap according the port max speed for lossless 11788 * TSC4/TSC6/TSCF : uplink port 11789 * TSC0~3/TSC5/QGMII/SGMII : donnlink port 11790 * Note. 11791 * 1. the number of uplink port should not exceed 4 11792 * 2. cannot support donnlink port with speed > 10G 11793 */ 11794 num_cpu_ports = 0; 11795 number_of_uplink_ports = 0; 11796 number_of_downlink_ports = 0; 11797 num_1g_ports_downlink_ports = 0; 11798 num_2dot5g_ports_downlink_ports = 0; 11799 num_10g_ports_downlink_ports = 0; 11800 num_20g_ports_downlink_ports = 0; 11801 num_25g_ports_downlink_ports = 0; 11802 num_40g_ports_downlink_ports = 0; 11803 SOC_PBMP_CLEAR(pbmp_cpu); 11804 SOC_PBMP_CLEAR(pbmp_uplink); 11805 SOC_PBMP_CLEAR(pbmp_downlink_1g); 11806 SOC_PBMP_CLEAR(pbmp_downlink_2dot5g); 11807 SOC_PBMP_CLEAR(pbmp_downlink_10g); 11808 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 11809 port = si->port_p2l_mapping[phy_port]; 11810 if (port < 0) { 11811 continue; /* this user port has not been mapping in this sku */ 11812 } else if (!SOC_PBMP_MEMBER(PBMP_ALL(unit), port)) { 11813 continue; /* this user port has been masked out by pbmp_valid */ 11814 } 11815 if (IS_CL_PORT(unit, port) || 11816 (74 <= phy_port && phy_port <= 77) || 11817 (82 <= phy_port && phy_port <= 85)) { 11818 number_of_uplink_ports++; 11819 SOC_PBMP_PORT_ADD(pbmp_uplink, port); 11820 } else if (IS_GE_PORT(unit, port) || 11821 (58 <= phy_port && phy_port <= 73) || 11822 (78 <= phy_port && phy_port <= 81)) { 11823 number_of_downlink_ports++; 11824 if (SOC_INFO(unit).port_speed_max[port] > 10000) { 11825 LOG_CLI((BSL_META_U(unit, 11826 "for downlink port %d,\ 11827 the max speed cannot exceed 10G (value=%d)\n"), 11828 port, SOC_INFO(unit).port_speed_max[port])); 11829 return SOC_E_PARAM; 11830 } else if (SOC_INFO(unit).port_speed_max[port] > 2500) { 11831 num_10g_ports_downlink_ports++; 11832 SOC_PBMP_PORT_ADD(pbmp_downlink_10g, port); 11833 } else if (SOC_INFO(unit).port_speed_max[port] > 1000) { 11834 num_2dot5g_ports_downlink_ports++; 11835 SOC_PBMP_PORT_ADD(pbmp_downlink_2dot5g, port); 11836 } else { 11837 num_1g_ports_downlink_ports++; 11838 SOC_PBMP_PORT_ADD(pbmp_downlink_1g, port); 11839 } 11840 } else if (IS_CPU_PORT(unit, port)) { 11841 num_cpu_ports++; 11842 SOC_PBMP_PORT_ADD(pbmp_cpu, port); 11843 } 11844 } 11845 if (number_of_uplink_ports > 4) { 11846 LOG_CLI((BSL_META_U(unit, 11847 "Num of UplinkPorts Error,\ 11848 should be less than or equal to 4 (value=%d)\n"), 11849 number_of_uplink_ports)); 11850 return SOC_E_PARAM; 11851 } 11852 11853 standard_jumbo_frame = 9216; 11854 cell_size = 144; 11855 ethernet_mtu_cell = ceiling_func(15 * 1024 / 10, cell_size); 11856 standard_jumbo_frame_cell = 11857 ceiling_func(standard_jumbo_frame, cell_size); 11858 if (rev_id == BCM56170_B0_REV_ID) { 11859 total_physical_memory = 32 * 1024; 11860 } else { 11861 total_physical_memory = 24 * 1024; 11862 } 11863 total_cell_memory_for_admission = 225 * 1024 / 10;; 11864 number_of_used_memory_banks = 8; 11865 reserved_for_cfap = 65 * 2 + number_of_used_memory_banks * 4; 11866 skidmarker = 7; 11867 prefetch = 64 + 4; 11868 total_cell_memory = total_cell_memory_for_admission; 11869 cfapfullsetpoint = total_physical_memory - reserved_for_cfap; 11870 total_advertised_cell_memory = total_cell_memory; 11871 flow_control_type_pause_0_pfc_1 = 1; 11872 queue_port_limit_ratio = 8; 11873 headroom_for_1g_port = 30; 11874 headroom_for_2dot5g_port = 34; 11875 headroom_for_10g_port = 74; 11876 headroom_for_20g_port = 92; 11877 headroom_for_25g_port = 100; 11878 headroom_for_40g_port = 186; 11879 mmu_xoff_pkt_threshold_uplink_ports = total_advertised_cell_memory; 11880 mmu_xoff_pkt_threshold_downlink_ports = total_advertised_cell_memory; 11881 mmu_xoff_cell_threshold_1g_port_downlink_ports = headroom_for_1g_port; 11882 mmu_xoff_cell_threshold_2dot5g_port_downlink_ports = 11883 headroom_for_2dot5g_port; 11884 mmu_xoff_cell_threshold_10g_port_downlink_ports = headroom_for_10g_port; 11885 mmu_xoff_cell_threshold_20g_port_downlink_ports = headroom_for_20g_port; 11886 mmu_xoff_cell_threshold_25g_port_downlink_ports = headroom_for_25g_port; 11887 mmu_xoff_cell_threshold_40g_port_downlink_ports = headroom_for_40g_port; 11888 mmu_xoff_cell_threshold_all_uplink_ports = total_advertised_cell_memory; 11889 egress_xq_min_reserve_lossless_uplink_ports = 11890 (headroom_for_1g_port + 11891 mmu_xoff_cell_threshold_1g_port_downlink_ports) * 11892 num_1g_ports_downlink_ports + (headroom_for_2dot5g_port + 11893 mmu_xoff_cell_threshold_2dot5g_port_downlink_ports) * 11894 num_2dot5g_ports_downlink_ports + (headroom_for_10g_port + 11895 mmu_xoff_cell_threshold_10g_port_downlink_ports) * 11896 num_10g_ports_downlink_ports + (headroom_for_20g_port + 11897 mmu_xoff_cell_threshold_20g_port_downlink_ports) * 11898 num_20g_ports_downlink_ports + (headroom_for_25g_port + 11899 mmu_xoff_cell_threshold_25g_port_downlink_ports) * 11900 num_25g_ports_downlink_ports + (headroom_for_40g_port + 11901 mmu_xoff_cell_threshold_40g_port_downlink_ports) * 11902 num_40g_ports_downlink_ports; 11903 egress_xq_min_reserve_lossless_downlink_ports = 0; 11904 egress_xq_min_reserve_lossy_up_downlink_ports = ethernet_mtu_cell; 11905 egress_queue_min_reserve_uplink_ports_lossy = ethernet_mtu_cell; 11906 egress_queue_min_reserve_downlink_ports_lossy = ethernet_mtu_cell; 11907 egress_queue_min_reserve_uplink_ports_lossless = 11908 egress_xq_min_reserve_lossless_uplink_ports; 11909 egress_queue_min_reserve_downlink_ports_lossless = 0; 11910 egress_queue_min_reserve_cpu_ports = ethernet_mtu_cell; 11911 egress_xq_min_reserve_lossy_ports = 11912 ethernet_mtu_cell; 11913 num_active_pri_group_lossless = 1; 11914 num_lossy_queues = 7; 11915 num_cpu_queues = 8; 11916 num_cpu_ports = 1; 11917 numxqs_per_uplink_ports = 6 * 1024; 11918 numxqs_per_downlink_ports_and_cpu_port = 2 * 1024; 11919 xoff_cell_thresholds_per_port_1g_port_downlink_ports = 11920 mmu_xoff_cell_threshold_1g_port_downlink_ports; 11921 xoff_cell_thresholds_per_port_2dot5g_downlink_ports = 11922 mmu_xoff_cell_threshold_2dot5g_port_downlink_ports; 11923 xoff_cell_thresholds_per_port_10g_port_downlink_ports = 11924 mmu_xoff_cell_threshold_10g_port_downlink_ports; 11925 xoff_cell_threshold_all_uplink_ports = 11926 mmu_xoff_cell_threshold_all_uplink_ports; 11927 xoff_packet_thresholds_per_port_uplink_port = 11928 mmu_xoff_pkt_threshold_uplink_ports; 11929 xoff_packet_thresholds_per_port_downlink_port = 11930 mmu_xoff_pkt_threshold_downlink_ports; 11931 discard_limit_per_port_pg_uplink_1g_port = 11932 xoff_cell_thresholds_per_port_1g_port_downlink_ports + 11933 headroom_for_1g_port; 11934 discard_limit_per_port_pg_uplink_2dot5g_port = 11935 xoff_cell_thresholds_per_port_2dot5g_downlink_ports + 11936 headroom_for_2dot5g_port; 11937 discard_limit_per_port_pg_uplink_10g_port = 11938 xoff_cell_thresholds_per_port_10g_port_downlink_ports + 11939 headroom_for_10g_port; 11940 discard_limit_per_port_pg_downlink_port = total_advertised_cell_memory; 11941 total_reserved_cells_for_uplink_ports = 11942 egress_queue_min_reserve_uplink_ports_lossy * 11943 number_of_uplink_ports * num_lossy_queues + number_of_uplink_ports * 11944 egress_queue_min_reserve_uplink_ports_lossless * 11945 num_active_pri_group_lossless; 11946 total_reserved_cells_for_downlink_ports = 11947 number_of_downlink_ports * 11948 egress_queue_min_reserve_downlink_ports_lossy * (num_lossy_queues) + 11949 number_of_downlink_ports * 11950 egress_queue_min_reserve_downlink_ports_lossless; 11951 total_reserved_cells_for_cpu_port = 11952 num_cpu_ports * egress_queue_min_reserve_cpu_ports * num_cpu_queues; 11953 total_reserved = 11954 total_reserved_cells_for_uplink_ports + 11955 total_reserved_cells_for_downlink_ports + 11956 total_reserved_cells_for_cpu_port; 11957 shared_space_cells = total_advertised_cell_memory - total_reserved; 11958 reserved_xqs_per_uplink_port = 11959 egress_xq_min_reserve_lossy_ports * 11960 num_lossy_queues + egress_xq_min_reserve_lossless_uplink_ports; 11961 shared_xqs_per_uplink_port = 11962 numxqs_per_uplink_ports - reserved_xqs_per_uplink_port; 11963 reserved_xqs_per_downlink_port = 11964 egress_xq_min_reserve_lossy_ports * 11965 num_lossy_queues + egress_xq_min_reserve_lossless_downlink_ports; 11966 shared_xqs_per_downlink_port = 11967 numxqs_per_downlink_ports_and_cpu_port - 11968 reserved_xqs_per_downlink_port; 11969 cfapfullthreshold_cfapfullsetpoint_up = cfapfullsetpoint; 11970 gbllimitsetlimit_gblcellsetlimit_up = total_cell_memory_for_admission; 11971 totaldyncellsetlimit_totaldyncellsetlimit_up = shared_space_cells; 11972 holcosminxqcnt_qlayer8_holcosminxqcnt_up = 0; 11973 holcospktsetlimit0_pktsetlimit_up = 11974 shared_xqs_per_uplink_port + 11975 egress_xq_min_reserve_lossy_ports; 11976 holcospktsetlimit7_pktsetlimit_up = 11977 shared_xqs_per_uplink_port + 11978 egress_xq_min_reserve_lossless_uplink_ports; 11979 holcospktsetlimit_qlayer0_pktsetlimit_up = 11980 shared_xqs_per_uplink_port + 11981 egress_xq_min_reserve_lossy_ports; 11982 holcospktsetlimit_qlayer7_pktsetlimit_up = 11983 shared_xqs_per_uplink_port + 11984 egress_xq_min_reserve_lossless_uplink_ports; 11985 holcospktsetlimit_qlayer8_pktsetlimit_up = 11986 shared_xqs_per_uplink_port + 11987 holcosminxqcnt_qlayer8_holcosminxqcnt_up; 11988 dynxqcntport_dynxqcntport_up = 11989 shared_xqs_per_uplink_port - skidmarker - prefetch; 11990 lwmcoscellsetlimit0_cellsetlimit_up = 11991 egress_queue_min_reserve_uplink_ports_lossy; 11992 lwmcoscellsetlimit7_cellsetlimit_up = 11993 egress_queue_min_reserve_uplink_ports_lossless; 11994 lwmcoscellsetlimit_qlayer0_cellsetlimit_up = 11995 egress_queue_min_reserve_uplink_ports_lossy; 11996 lwmcoscellsetlimit_qlayer7_cellsetlimit_up = 11997 egress_queue_min_reserve_uplink_ports_lossless; 11998 lwmcoscellsetlimit_qlayer8_cellsetlimit_up = 0; 11999 holcoscellmaxlimit0_cellmaxlimit_up = 12000 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12001 lwmcoscellsetlimit0_cellsetlimit_up; 12002 holcoscellmaxlimit7_cellmaxlimit_up = 12003 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12004 lwmcoscellsetlimit7_cellsetlimit_up; 12005 holcoscellmaxlimit_qlayer0_cellmaxlimit_up = 12006 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12007 lwmcoscellsetlimit_qlayer0_cellsetlimit_up; 12008 holcoscellmaxlimit_qlayer7_cellmaxlimit_up = 12009 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12010 lwmcoscellsetlimit_qlayer7_cellsetlimit_up; 12011 holcoscellmaxlimit_qlayer8_cellmaxlimit_up = 12012 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12013 lwmcoscellsetlimit_qlayer8_cellsetlimit_up; 12014 dyncelllimit_dyncellsetlimit_up = shared_space_cells; 12015 holcospktsetlimit_qgroup0_pktsetlimit_up = numxqs_per_uplink_ports - 1; 12016 holcoscellmaxlimit_qgroup0_cellmaxlimit_up = 12017 ceiling_func(total_advertised_cell_memory, queue_port_limit_ratio); 12018 holcosminxqcnt_qlayer8_holcosminxqcnt_down_1 = 0; 12019 holcospktsetlimit0_pktsetlimit_down_1 = 12020 shared_xqs_per_downlink_port + 12021 egress_xq_min_reserve_lossy_ports; 12022 holcospktsetlimit7_pktsetlimit_down_1 = 12023 shared_xqs_per_downlink_port + 12024 egress_xq_min_reserve_lossless_downlink_ports; 12025 holcospktsetlimit_qlayer0_pktsetlimit_down_1 = 12026 shared_xqs_per_downlink_port + 12027 egress_xq_min_reserve_lossy_ports; 12028 holcospktsetlimit_qlayer7_pktsetlimit_down_1 = 12029 shared_xqs_per_downlink_port + 12030 egress_xq_min_reserve_lossless_downlink_ports; 12031 holcospktsetlimit_qlayer8_pktsetlimit_down_1 = 12032 shared_xqs_per_downlink_port + 12033 holcosminxqcnt_qlayer8_holcosminxqcnt_down_1; 12034 dynxqcntport_dynxqcntport_down_1 = 12035 shared_xqs_per_downlink_port - skidmarker - prefetch; 12036 lwmcoscellsetlimit0_cellsetlimit_down_1 = 12037 egress_queue_min_reserve_downlink_ports_lossy; 12038 lwmcoscellsetlimit7_cellsetlimit_down_1 = 12039 egress_queue_min_reserve_downlink_ports_lossless; 12040 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1 = 12041 egress_queue_min_reserve_downlink_ports_lossy; 12042 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1 = 12043 egress_queue_min_reserve_downlink_ports_lossless; 12044 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1 = 0; 12045 holcoscellmaxlimit0_cellmaxlimit_down_1 = 12046 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12047 lwmcoscellsetlimit0_cellsetlimit_down_1; 12048 holcoscellmaxlimit7_cellmaxlimit_down_1 = 12049 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12050 lwmcoscellsetlimit7_cellsetlimit_down_1; 12051 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_1 = 12052 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12053 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1; 12054 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_1 = 12055 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12056 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1; 12057 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_1 = 12058 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12059 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1; 12060 dyncelllimit_dyncellsetlimit_down_1 = shared_space_cells; 12061 holcospktsetlimit_qgroup0_pktsetlimit_down_1 = 12062 numxqs_per_downlink_ports_and_cpu_port - 1; 12063 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_1 = 12064 ceiling_func(total_advertised_cell_memory, queue_port_limit_ratio); 12065 holcosminxqcnt_qlayer8_holcosminxqcnt_down_2dot5 = 0; 12066 holcospktsetlimit0_pktsetlimit_down_2dot5 = 12067 shared_xqs_per_downlink_port + 12068 egress_xq_min_reserve_lossy_ports; 12069 holcospktsetlimit7_pktsetlimit_down_2dot5 = 12070 shared_xqs_per_downlink_port + 12071 egress_xq_min_reserve_lossless_downlink_ports; 12072 holcospktsetlimit_qlayer0_pktsetlimit_down_2dot5 = 12073 shared_xqs_per_downlink_port + 12074 egress_xq_min_reserve_lossy_ports; 12075 holcospktsetlimit_qlayer7_pktsetlimit_down_2dot5 = 12076 shared_xqs_per_downlink_port + 12077 egress_xq_min_reserve_lossless_downlink_ports; 12078 holcospktsetlimit_qlayer8_pktsetlimit_down_2dot5 = 12079 shared_xqs_per_downlink_port + 12080 holcosminxqcnt_qlayer8_holcosminxqcnt_down_2dot5; 12081 dynxqcntport_dynxqcntport_down_2dot5 = 12082 shared_xqs_per_downlink_port - skidmarker - prefetch; 12083 lwmcoscellsetlimit0_cellsetlimit_down_2dot5 = 12084 egress_queue_min_reserve_downlink_ports_lossy; 12085 lwmcoscellsetlimit7_cellsetlimit_down_2dot5 = 12086 egress_queue_min_reserve_downlink_ports_lossless; 12087 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5 = 12088 egress_queue_min_reserve_downlink_ports_lossy; 12089 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5 = 12090 egress_queue_min_reserve_downlink_ports_lossless; 12091 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5 = 0; 12092 holcoscellmaxlimit0_cellmaxlimit_down_2dot5 = 12093 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12094 lwmcoscellsetlimit0_cellsetlimit_down_2dot5; 12095 holcoscellmaxlimit7_cellmaxlimit_down_2dot5 = 12096 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12097 lwmcoscellsetlimit7_cellsetlimit_down_2dot5; 12098 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_2dot5 = 12099 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12100 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5; 12101 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_2dot5 = 12102 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12103 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5; 12104 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_2dot5 = 12105 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12106 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5; 12107 dyncelllimit_dyncellsetlimit_down_2dot5 = shared_space_cells; 12108 holcospktsetlimit_qgroup0_pktsetlimit_down_2dot5 = 12109 numxqs_per_downlink_ports_and_cpu_port - 1; 12110 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_2dot5 = 12111 ceiling_func(total_advertised_cell_memory, queue_port_limit_ratio); 12112 holcosminxqcnt_qlayer8_holcosminxqcnt_down_10 = 0; 12113 holcospktsetlimit0_pktsetlimit_down_10 = 12114 shared_xqs_per_downlink_port + 12115 egress_xq_min_reserve_lossy_ports; 12116 holcospktsetlimit7_pktsetlimit_down_10 = 12117 shared_xqs_per_downlink_port + 12118 egress_xq_min_reserve_lossless_downlink_ports; 12119 holcospktsetlimit_qlayer0_pktsetlimit_down_10 = 12120 shared_xqs_per_downlink_port + 12121 egress_xq_min_reserve_lossy_ports; 12122 holcospktsetlimit_qlayer7_pktsetlimit_down_10 = 12123 shared_xqs_per_downlink_port + 12124 egress_xq_min_reserve_lossless_downlink_ports; 12125 holcospktsetlimit_qlayer8_pktsetlimit_down_10 = 12126 shared_xqs_per_downlink_port + 12127 holcosminxqcnt_qlayer8_holcosminxqcnt_down_10; 12128 dynxqcntport_dynxqcntport_down_10 = 12129 shared_xqs_per_downlink_port - skidmarker - prefetch; 12130 lwmcoscellsetlimit0_cellsetlimit_down_10 = 12131 egress_queue_min_reserve_downlink_ports_lossy; 12132 lwmcoscellsetlimit7_cellsetlimit_down_10 = 12133 egress_queue_min_reserve_downlink_ports_lossless; 12134 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_10 = 12135 egress_queue_min_reserve_downlink_ports_lossy; 12136 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_10 = 12137 egress_queue_min_reserve_downlink_ports_lossless; 12138 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_10 = 0; 12139 holcoscellmaxlimit0_cellmaxlimit_down_10 = 12140 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12141 lwmcoscellsetlimit0_cellsetlimit_down_10; 12142 holcoscellmaxlimit7_cellmaxlimit_down_10 = 12143 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12144 lwmcoscellsetlimit7_cellsetlimit_down_10; 12145 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_10 = 12146 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12147 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_10; 12148 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_10 = 12149 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12150 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_10; 12151 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_10 = 12152 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12153 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_10; 12154 dyncelllimit_dyncellsetlimit_down_10 = shared_space_cells; 12155 holcospktsetlimit_qgroup0_pktsetlimit_down_10 = 12156 numxqs_per_downlink_ports_and_cpu_port - 1; 12157 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_10 = 12158 ceiling_func(total_advertised_cell_memory, queue_port_limit_ratio); 12159 holcospktsetlimit0_pktsetlimit_cpu = 12160 shared_xqs_per_downlink_port + 12161 egress_xq_min_reserve_lossy_ports; 12162 holcospktsetlimit7_pktsetlimit_cpu = 12163 shared_xqs_per_downlink_port + 12164 egress_xq_min_reserve_lossless_downlink_ports; 12165 dynxqcntport_dynxqcntport_cpu = 12166 shared_xqs_per_downlink_port - skidmarker - prefetch; 12167 lwmcoscellsetlimit0_cellsetlimit_cpu = egress_queue_min_reserve_cpu_ports; 12168 lwmcoscellsetlimit7_cellsetlimit_cpu = egress_queue_min_reserve_cpu_ports; 12169 holcoscellmaxlimit0_cellmaxlimit_cpu = 12170 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12171 lwmcoscellsetlimit0_cellsetlimit_cpu; 12172 holcoscellmaxlimit7_cellmaxlimit_cpu = 12173 ceiling_func(shared_space_cells, queue_port_limit_ratio) + 12174 lwmcoscellsetlimit7_cellsetlimit_cpu; 12175 dyncelllimit_dyncellsetlimit_cpu = shared_space_cells; 12176 12177 if ((shared_space_cells * cell_size)/1024 <= 800) { 12178 LOG_CLI((BSL_META_U(unit, 12179 "Shared Pool Is Small,\ 12180 should be larger than 800 (value=%d)\n"), 12181 (shared_space_cells * cell_size)/1024)); 12182 return SOC_E_PARAM; 12183 } 12184 12185 /* system-based */ 12186 soc_reg_field32_modify(unit, CFAPFULLTHRESHOLDr, 12187 REG_PORT_ANY, 12188 CFAPFULLSETPOINTf, 12189 cfapfullsetpoint); 12190 soc_reg_field32_modify(unit, CFAPFULLTHRESHOLDr, 12191 REG_PORT_ANY, 12192 CFAPFULLRESETPOINTf, 12193 cfapfullthreshold_cfapfullsetpoint_up - 12194 (standard_jumbo_frame_cell * 2)); 12195 soc_reg_field32_modify(unit, GBLLIMITSETLIMITr, 12196 REG_PORT_ANY, 12197 GBLCELLSETLIMITf, 12198 total_cell_memory_for_admission); 12199 soc_reg_field32_modify(unit, GBLLIMITRESETLIMITr, 12200 REG_PORT_ANY, 12201 GBLCELLRESETLIMITf, 12202 gbllimitsetlimit_gblcellsetlimit_up); 12203 soc_reg_field32_modify(unit, TOTALDYNCELLSETLIMITr, 12204 REG_PORT_ANY, 12205 TOTALDYNCELLSETLIMITf, 12206 shared_space_cells); 12207 soc_reg_field32_modify(unit, TOTALDYNCELLRESETLIMITr, 12208 REG_PORT_ANY, 12209 TOTALDYNCELLRESETLIMITf, 12210 totaldyncellsetlimit_totaldyncellsetlimit_up - 12211 (standard_jumbo_frame_cell * 2)); 12212 soc_reg_field32_modify(unit, TWO_LAYER_SCH_MODEr, 12213 REG_PORT_ANY, 12214 SCH_MODEf, 12215 0); 12216 soc_reg_field32_modify(unit, MISCCONFIGr, 12217 REG_PORT_ANY, 12218 MULTIPLE_ACCOUNTING_FIX_ENf, 12219 1); 12220 soc_reg_field32_modify(unit, MISCCONFIGr, 12221 REG_PORT_ANY, 12222 CNG_DROP_ENf, 12223 0); 12224 soc_reg_field32_modify(unit, MISCCONFIGr, 12225 REG_PORT_ANY, 12226 DYN_XQ_ENf, 12227 1); 12228 soc_reg_field32_modify(unit, MISCCONFIGr, 12229 REG_PORT_ANY, 12230 HOL_CELL_SOP_DROP_ENf, 12231 1); 12232 soc_reg_field32_modify(unit, MISCCONFIGr, 12233 REG_PORT_ANY, 12234 DYNAMIC_MEMORY_ENf, 12235 1); 12236 soc_reg_field32_modify(unit, MISCCONFIGr, 12237 REG_PORT_ANY, 12238 SKIDMARKERf, 12239 3); 12240 soc_reg_field32_modify(unit, MMUPORTTXENABLE_0r, 12241 REG_PORT_ANY, 12242 MMUPORTTXENABLEf, 12243 0xFFFFFFFF); 12244 soc_reg_field32_modify(unit, MMUPORTTXENABLE_1r, 12245 REG_PORT_ANY, 12246 MMUPORTTXENABLEf, 12247 0xFFFFFFFF); 12248 soc_reg_field32_modify(unit, MMUPORTTXENABLE_2r, 12249 REG_PORT_ANY, 12250 MMUPORTTXENABLEf, 12251 3); 12252 12253 /* port-based : uplink */ 12254 SOC_PBMP_ITER(pbmp_uplink, port) { 12255 /* PG_CTRL0r, index 0 */ 12256 soc_reg32_get(unit, PG_CTRL0r, 12257 port, 0, &rval); 12258 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12259 PPFC_PG_ENf, 12260 0); 12261 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12262 PRI0_GRPf, 12263 /* coverity[dead_error_line : FALSE] */ 12264 flow_control_type_pause_0_pfc_1?0:7); 12265 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12266 PRI1_GRPf, 12267 /* coverity[dead_error_line : FALSE] */ 12268 flow_control_type_pause_0_pfc_1?1:7); 12269 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12270 PRI2_GRPf, 12271 /* coverity[dead_error_line : FALSE] */ 12272 flow_control_type_pause_0_pfc_1?2:7); 12273 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12274 PRI3_GRPf, 12275 /* coverity[dead_error_line : FALSE] */ 12276 flow_control_type_pause_0_pfc_1?3:7); 12277 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12278 PRI4_GRPf, 12279 /* coverity[dead_error_line : FALSE] */ 12280 flow_control_type_pause_0_pfc_1?4:7); 12281 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12282 PRI5_GRPf, 12283 /* coverity[dead_error_line : FALSE] */ 12284 flow_control_type_pause_0_pfc_1?5:7); 12285 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12286 PRI6_GRPf, 12287 /* coverity[dead_error_line : FALSE] */ 12288 flow_control_type_pause_0_pfc_1?6:7); 12289 soc_reg_field_set(unit, PG_CTRL0r, &rval, 12290 PRI7_GRPf, 12291 /* coverity[identical_branches : FALSE] */ 12292 flow_control_type_pause_0_pfc_1?7:7); 12293 soc_reg32_set(unit, PG_CTRL0r, 12294 port, 0, rval); 12295 12296 /* PG_CTRL1r, index 0 */ 12297 soc_reg32_get(unit, PG_CTRL1r, 12298 port, 0, &rval); 12299 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12300 PRI8_GRPf, 12301 /* coverity[identical_branches : FALSE] */ 12302 flow_control_type_pause_0_pfc_1?7:7); 12303 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12304 PRI9_GRPf, 12305 /* coverity[identical_branches : FALSE] */ 12306 flow_control_type_pause_0_pfc_1?7:7); 12307 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12308 PRI10_GRPf, 12309 /* coverity[identical_branches : FALSE] */ 12310 flow_control_type_pause_0_pfc_1?7:7); 12311 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12312 PRI11_GRPf, 12313 /* coverity[identical_branches : FALSE] */ 12314 flow_control_type_pause_0_pfc_1?7:7); 12315 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12316 PRI12_GRPf, 12317 /* coverity[identical_branches : FALSE] */ 12318 flow_control_type_pause_0_pfc_1?7:7); 12319 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12320 PRI13_GRPf, 12321 /* coverity[identical_branches : FALSE] */ 12322 flow_control_type_pause_0_pfc_1?7:7); 12323 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12324 PRI14_GRPf, 12325 /* coverity[identical_branches : FALSE] */ 12326 flow_control_type_pause_0_pfc_1?7:7); 12327 soc_reg_field_set(unit, PG_CTRL1r, &rval, 12328 PRI15_GRPf, 12329 /* coverity[identical_branches : FALSE] */ 12330 flow_control_type_pause_0_pfc_1?7:7); 12331 soc_reg32_set(unit, PG_CTRL1r, 12332 port, 0, rval); 12333 12334 /* PG2TCr, index 0 ~ 7 */ 12335 for (index = 0; index <= 7; index++) { 12336 soc_reg32_get(unit, PG2TCr, 12337 port, index, &rval); 12338 soc_reg_field_set(unit, PG2TCr, &rval, 12339 PG_BMPf, 12340 0); 12341 soc_reg32_set(unit, PG2TCr, 12342 port, index, rval); 12343 } 12344 12345 /* IBPPKTSETLIMITr, index 0 */ 12346 soc_reg32_get(unit, IBPPKTSETLIMITr, 12347 port, 0, &rval); 12348 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 12349 PKTSETLIMITf, 12350 xoff_packet_thresholds_per_port_uplink_port); 12351 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 12352 RESETLIMITSELf, 12353 3); 12354 soc_reg32_set(unit, IBPPKTSETLIMITr, 12355 port, 0, rval); 12356 12357 /* MMU_FC_RX_ENr, index 0 */ 12358 soc_reg32_get(unit, MMU_FC_RX_ENr, 12359 port, 0, &rval); 12360 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 12361 MMU_FC_RX_ENABLEf, 12362 0); 12363 soc_reg32_set(unit, MMU_FC_RX_ENr, 12364 port, 0, rval); 12365 12366 /* MMU_FC_TX_ENr, index 0 */ 12367 soc_reg32_get(unit, MMU_FC_TX_ENr, 12368 port, 0, &rval); 12369 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 12370 MMU_FC_TX_ENABLEf, 12371 0); 12372 soc_reg32_set(unit, MMU_FC_TX_ENr, 12373 port, 0, rval); 12374 12375 /* PGCELLLIMITr, index 0 ~ 7 */ 12376 for (index = 0; index <= 7; index++) { 12377 soc_reg32_get(unit, PGCELLLIMITr, 12378 port, index, &rval); 12379 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 12380 CELLSETLIMITf, 12381 xoff_cell_threshold_all_uplink_ports); 12382 soc_reg32_set(unit, PGCELLLIMITr, 12383 port, index, rval); 12384 } 12385 12386 /* PGCELLLIMITr, index 0 ~ 7 */ 12387 for (index = 0; index <= 7; index++) { 12388 soc_reg32_get(unit, PGCELLLIMITr, 12389 port, index, &rval); 12390 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 12391 CELLRESETLIMITf, 12392 xoff_cell_threshold_all_uplink_ports); 12393 soc_reg32_set(unit, PGCELLLIMITr, 12394 port, index, rval); 12395 } 12396 12397 /* PGDISCARDSETLIMITr, index 0 ~ 7 */ 12398 for (index = 0; index <= 7; index++) { 12399 soc_reg32_get(unit, PGDISCARDSETLIMITr, 12400 port, index, &rval); 12401 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 12402 DISCARDSETLIMITf, 12403 discard_limit_per_port_pg_downlink_port); 12404 soc_reg32_set(unit, PGDISCARDSETLIMITr, 12405 port, index, rval); 12406 } 12407 12408 /* HOLCOSMINXQCNTr, index 0 ~ 6 */ 12409 for (index = 0; index <= 6; index++) { 12410 soc_reg32_get(unit, HOLCOSMINXQCNTr, 12411 port, index, &rval); 12412 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 12413 HOLCOSMINXQCNTf, 12414 egress_xq_min_reserve_lossy_ports); 12415 soc_reg32_set(unit, HOLCOSMINXQCNTr, 12416 port, index, rval); 12417 } 12418 12419 /* HOLCOSMINXQCNTr, index 7 */ 12420 soc_reg32_get(unit, HOLCOSMINXQCNTr, 12421 port, 7, &rval); 12422 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 12423 HOLCOSMINXQCNTf, 12424 egress_xq_min_reserve_lossless_uplink_ports); 12425 soc_reg32_set(unit, HOLCOSMINXQCNTr, 12426 port, 7, rval); 12427 12428 /* HOLCOSMINXQCNT_QLAYERr, index 0 ~ 6 */ 12429 for (index = 0; index <= 6; index++) { 12430 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 12431 port, index, &rval); 12432 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 12433 HOLCOSMINXQCNTf, 12434 egress_xq_min_reserve_lossy_ports); 12435 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 12436 port, index, rval); 12437 } 12438 12439 /* HOLCOSMINXQCNT_QLAYERr, index 7 */ 12440 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 12441 port, 7, &rval); 12442 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 12443 HOLCOSMINXQCNTf, 12444 egress_xq_min_reserve_lossless_uplink_ports); 12445 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 12446 port, 7, rval); 12447 12448 /* HOLCOSMINXQCNT_QLAYERr, index 8 ~ 63 */ 12449 for (index = 8; index <= 63; index++) { 12450 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 12451 port, index, &rval); 12452 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 12453 HOLCOSMINXQCNTf, 12454 0); 12455 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 12456 port, index, rval); 12457 } 12458 12459 /* HOLCOSPKTSETLIMITr, index 0 ~ 6 */ 12460 for (index = 0; index <= 6; index++) { 12461 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 12462 port, index, &rval); 12463 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 12464 PKTSETLIMITf, 12465 shared_xqs_per_uplink_port + 12466 egress_xq_min_reserve_lossy_ports); 12467 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 12468 port, index, rval); 12469 } 12470 12471 /* HOLCOSPKTSETLIMITr, index 7 */ 12472 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 12473 port, 7, &rval); 12474 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 12475 PKTSETLIMITf, 12476 shared_xqs_per_uplink_port + 12477 egress_xq_min_reserve_lossless_uplink_ports); 12478 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 12479 port, 7, rval); 12480 12481 /* HOLCOSPKTSETLIMIT_QLAYERr, index 0 ~ 6 */ 12482 for (index = 0; index <= 6; index++) { 12483 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 12484 port, index, &rval); 12485 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 12486 PKTSETLIMITf, 12487 shared_xqs_per_uplink_port + 12488 egress_xq_min_reserve_lossy_ports); 12489 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 12490 port, index, rval); 12491 } 12492 12493 /* HOLCOSPKTSETLIMIT_QLAYERr, index 7 */ 12494 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 12495 port, 7, &rval); 12496 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 12497 PKTSETLIMITf, 12498 shared_xqs_per_uplink_port + 12499 egress_xq_min_reserve_lossless_uplink_ports); 12500 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 12501 port, 7, rval); 12502 12503 /* HOLCOSPKTSETLIMIT_QLAYERr, index 8 ~ 63 */ 12504 for (index = 8; index <= 63; index++) { 12505 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 12506 port, index, &rval); 12507 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 12508 PKTSETLIMITf, 12509 shared_xqs_per_uplink_port + 12510 holcosminxqcnt_qlayer8_holcosminxqcnt_up); 12511 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 12512 port, index, rval); 12513 } 12514 12515 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 12516 for (index = 0; index <= 6; index++) { 12517 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 12518 port, index, &rval); 12519 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 12520 PKTRESETLIMITf, 12521 holcospktsetlimit0_pktsetlimit_up - 1); 12522 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 12523 port, index, rval); 12524 } 12525 12526 /* HOLCOSPKTRESETLIMITr, index 7 */ 12527 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 12528 port, 7, &rval); 12529 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 12530 PKTRESETLIMITf, 12531 holcospktsetlimit7_pktsetlimit_up - 1); 12532 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 12533 port, 7, rval); 12534 12535 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 0 ~ 6 */ 12536 for (index = 0; index <= 6; index++) { 12537 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 12538 port, index, &rval); 12539 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 12540 PKTRESETLIMITf, 12541 holcospktsetlimit_qlayer0_pktsetlimit_up - 1); 12542 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 12543 port, index, rval); 12544 } 12545 12546 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 7 */ 12547 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 12548 port, 7, &rval); 12549 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 12550 PKTRESETLIMITf, 12551 holcospktsetlimit_qlayer7_pktsetlimit_up - 1); 12552 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 12553 port, 7, rval); 12554 12555 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 8 ~ 63 */ 12556 for (index = 8; index <= 63; index++) { 12557 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 12558 port, index, &rval); 12559 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 12560 PKTRESETLIMITf, 12561 holcospktsetlimit_qlayer8_pktsetlimit_up - 1); 12562 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 12563 port, index, rval); 12564 } 12565 12566 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 12567 for (index = 0; index <= 7; index++) { 12568 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 12569 port, index, &rval); 12570 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 12571 CNGPKTSETLIMIT0f, 12572 numxqs_per_uplink_ports - 1); 12573 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 12574 port, index, rval); 12575 } 12576 12577 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 12578 for (index = 0; index <= 7; index++) { 12579 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 12580 port, index, &rval); 12581 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 12582 CNGPKTSETLIMIT1f, 12583 numxqs_per_uplink_ports - 1); 12584 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 12585 port, index, rval); 12586 } 12587 12588 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 12589 for (index = 0; index <= 63; index++) { 12590 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 12591 port, index, &rval); 12592 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 12593 CNGPKTSETLIMIT0f, 12594 numxqs_per_uplink_ports - 1); 12595 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 12596 port, index, rval); 12597 } 12598 12599 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 12600 for (index = 0; index <= 63; index++) { 12601 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 12602 port, index, &rval); 12603 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 12604 CNGPKTSETLIMIT1f, 12605 numxqs_per_uplink_ports - 1); 12606 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 12607 port, index, rval); 12608 } 12609 12610 /* CNGPORTPKTLIMIT0r, index 0 */ 12611 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 12612 port, 0, &rval); 12613 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 12614 CNGPORTPKTLIMIT0f, 12615 numxqs_per_uplink_ports - 1); 12616 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 12617 port, 0, rval); 12618 12619 /* CNGPORTPKTLIMIT1r, index 0 */ 12620 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 12621 port, 0, &rval); 12622 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 12623 CNGPORTPKTLIMIT1f, 12624 numxqs_per_uplink_ports - 1); 12625 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 12626 port, 0, rval); 12627 12628 /* DYNXQCNTPORTr, index 0 */ 12629 soc_reg32_get(unit, DYNXQCNTPORTr, 12630 port, 0, &rval); 12631 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 12632 DYNXQCNTPORTf, 12633 shared_xqs_per_uplink_port - skidmarker - prefetch); 12634 soc_reg32_set(unit, DYNXQCNTPORTr, 12635 port, 0, rval); 12636 12637 /* DYNRESETLIMPORTr, index 0 */ 12638 soc_reg32_get(unit, DYNRESETLIMPORTr, 12639 port, 0, &rval); 12640 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 12641 DYNRESETLIMPORTf, 12642 dynxqcntport_dynxqcntport_up - 2); 12643 soc_reg32_set(unit, DYNRESETLIMPORTr, 12644 port, 0, rval); 12645 12646 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 12647 for (index = 0; index <= 6; index++) { 12648 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 12649 port, index, &rval); 12650 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 12651 CELLSETLIMITf, 12652 egress_queue_min_reserve_uplink_ports_lossy); 12653 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 12654 port, index, rval); 12655 } 12656 12657 /* LWMCOSCELLSETLIMITr, index 7 */ 12658 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 12659 port, 7, &rval); 12660 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 12661 CELLSETLIMITf, 12662 egress_queue_min_reserve_uplink_ports_lossless); 12663 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 12664 port, 7, rval); 12665 12666 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 12667 for (index = 0; index <= 6; index++) { 12668 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12669 port, index, &rval); 12670 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 12671 CELLSETLIMITf, 12672 egress_queue_min_reserve_uplink_ports_lossy); 12673 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12674 port, index, rval); 12675 } 12676 12677 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 12678 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12679 port, 7, &rval); 12680 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 12681 CELLSETLIMITf, 12682 egress_queue_min_reserve_uplink_ports_lossless); 12683 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12684 port, 7, rval); 12685 12686 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 12687 for (index = 8; index <= 63; index++) { 12688 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12689 port, index, &rval); 12690 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 12691 CELLSETLIMITf, 12692 0); 12693 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12694 port, index, rval); 12695 } 12696 12697 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 12698 for (index = 0; index <= 6; index++) { 12699 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 12700 port, index, &rval); 12701 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 12702 CELLRESETLIMITf, 12703 egress_queue_min_reserve_uplink_ports_lossy); 12704 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 12705 port, index, rval); 12706 } 12707 12708 /* LWMCOSCELLSETLIMITr, index 7 */ 12709 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 12710 port, 7, &rval); 12711 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 12712 CELLRESETLIMITf, 12713 egress_queue_min_reserve_uplink_ports_lossless); 12714 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 12715 port, 7, rval); 12716 12717 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 12718 for (index = 0; index <= 6; index++) { 12719 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12720 port, index, &rval); 12721 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 12722 CELLRESETLIMITf, 12723 egress_queue_min_reserve_uplink_ports_lossy); 12724 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12725 port, index, rval); 12726 } 12727 12728 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 12729 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12730 port, 7, &rval); 12731 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 12732 CELLRESETLIMITf, 12733 egress_queue_min_reserve_uplink_ports_lossless); 12734 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12735 port, 7, rval); 12736 12737 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 12738 for (index = 8; index <= 63; index++) { 12739 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12740 port, index, &rval); 12741 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 12742 CELLRESETLIMITf, 12743 0); 12744 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 12745 port, index, rval); 12746 } 12747 12748 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 12749 for (index = 0; index <= 6; index++) { 12750 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 12751 port, index, &rval); 12752 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 12753 CELLMAXLIMITf, 12754 ceiling_func(shared_space_cells, 12755 queue_port_limit_ratio) + 12756 lwmcoscellsetlimit0_cellsetlimit_up); 12757 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 12758 port, index, rval); 12759 } 12760 12761 /* HOLCOSCELLMAXLIMITr, index 7 */ 12762 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 12763 port, 7, &rval); 12764 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 12765 CELLMAXLIMITf, 12766 ceiling_func(shared_space_cells, 12767 queue_port_limit_ratio) + 12768 lwmcoscellsetlimit7_cellsetlimit_up); 12769 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 12770 port, 7, rval); 12771 12772 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 12773 for (index = 0; index <= 6; index++) { 12774 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12775 port, index, &rval); 12776 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 12777 CELLMAXLIMITf, 12778 ceiling_func(shared_space_cells, 12779 queue_port_limit_ratio) + 12780 lwmcoscellsetlimit_qlayer0_cellsetlimit_up); 12781 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12782 port, index, rval); 12783 } 12784 12785 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 12786 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12787 port, 7, &rval); 12788 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 12789 CELLMAXLIMITf, 12790 ceiling_func(shared_space_cells, 12791 queue_port_limit_ratio) + 12792 lwmcoscellsetlimit_qlayer7_cellsetlimit_up); 12793 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12794 port, 7, rval); 12795 12796 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 12797 for (index = 8; index <= 63; index++) { 12798 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12799 port, index, &rval); 12800 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 12801 CELLMAXLIMITf, 12802 ceiling_func(shared_space_cells, 12803 queue_port_limit_ratio) + 12804 lwmcoscellsetlimit_qlayer8_cellsetlimit_up); 12805 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12806 port, index, rval); 12807 } 12808 12809 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 12810 for (index = 0; index <= 6; index++) { 12811 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 12812 port, index, &rval); 12813 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 12814 CELLMAXRESUMELIMITf, 12815 holcoscellmaxlimit0_cellmaxlimit_up - 12816 ethernet_mtu_cell); 12817 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 12818 port, index, rval); 12819 } 12820 12821 /* HOLCOSCELLMAXLIMITr, index 7 */ 12822 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 12823 port, 7, &rval); 12824 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 12825 CELLMAXRESUMELIMITf, 12826 holcoscellmaxlimit7_cellmaxlimit_up - 12827 ethernet_mtu_cell); 12828 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 12829 port, 7, rval); 12830 12831 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 12832 for (index = 0; index <= 6; index++) { 12833 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12834 port, index, &rval); 12835 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 12836 CELLMAXRESUMELIMITf, 12837 holcoscellmaxlimit_qlayer0_cellmaxlimit_up - 12838 ethernet_mtu_cell); 12839 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12840 port, index, rval); 12841 } 12842 12843 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 12844 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12845 port, 7, &rval); 12846 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 12847 CELLMAXRESUMELIMITf, 12848 holcoscellmaxlimit_qlayer7_cellmaxlimit_up - 12849 ethernet_mtu_cell); 12850 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12851 port, 7, rval); 12852 12853 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 12854 for (index = 8; index <= 63; index++) { 12855 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12856 port, index, &rval); 12857 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 12858 CELLMAXRESUMELIMITf, 12859 holcoscellmaxlimit_qlayer8_cellmaxlimit_up - 12860 ethernet_mtu_cell); 12861 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 12862 port, index, rval); 12863 } 12864 12865 /* DYNCELLLIMITr, index 0 */ 12866 soc_reg32_get(unit, DYNCELLLIMITr, 12867 port, 0, &rval); 12868 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 12869 DYNCELLSETLIMITf, 12870 shared_space_cells); 12871 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 12872 DYNCELLRESETLIMITf, 12873 dyncelllimit_dyncellsetlimit_up - 12874 (2 * ethernet_mtu_cell)); 12875 soc_reg32_set(unit, DYNCELLLIMITr, 12876 port, 0, rval); 12877 12878 /* COLOR_DROP_ENr, index 0 */ 12879 soc_reg32_get(unit, COLOR_DROP_ENr, 12880 port, 0, &rval); 12881 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 12882 COLOR_DROP_ENf, 12883 0); 12884 soc_reg32_set(unit, COLOR_DROP_ENr, 12885 port, 0, rval); 12886 12887 /* COLOR_DROP_EN_QLAYERr, index 0 */ 12888 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 12889 port, 0, &rval); 12890 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 12891 COLOR_DROP_ENf, 12892 0); 12893 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 12894 port, 0, rval); 12895 12896 /* HOLCOSPKTSETLIMIT_QGROUPr, index 0 ~ 7 */ 12897 for (index = 0; index <= 7; index++) { 12898 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QGROUPr, 12899 port, index, &rval); 12900 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, &rval, 12901 PKTSETLIMITf, 12902 numxqs_per_uplink_ports - 1); 12903 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, 12904 port, index, rval); 12905 } 12906 12907 /* HOLCOSPKTRESETLIMIT_QGROUPr, index 0 ~ 7 */ 12908 for (index = 0; index <= 7; index++) { 12909 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 12910 port, index, &rval); 12911 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, &rval, 12912 PKTRESETLIMITf, 12913 holcospktsetlimit_qgroup0_pktsetlimit_up - 1); 12914 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 12915 port, index, rval); 12916 } 12917 12918 /* CNGCOSPKTLIMIT0_QGROUPr, index 0 ~ 7 */ 12919 for (index = 0; index <= 7; index++) { 12920 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QGROUPr, 12921 port, index, &rval); 12922 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QGROUPr, &rval, 12923 CNGPKTSETLIMIT0f, 12924 numxqs_per_uplink_ports - 1); 12925 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QGROUPr, 12926 port, index, rval); 12927 } 12928 12929 /* CNGCOSPKTLIMIT1_QGROUPr, index 0 ~ 7 */ 12930 for (index = 0; index <= 7; index++) { 12931 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QGROUPr, 12932 port, index, &rval); 12933 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QGROUPr, &rval, 12934 CNGPKTSETLIMIT1f, 12935 numxqs_per_uplink_ports - 1); 12936 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QGROUPr, 12937 port, index, rval); 12938 } 12939 12940 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 12941 for (index = 0; index <= 7; index++) { 12942 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 12943 port, index, &rval); 12944 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 12945 CELLMAXLIMITf, 12946 ceiling_func(total_advertised_cell_memory, 12947 queue_port_limit_ratio)); 12948 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 12949 port, index, rval); 12950 } 12951 12952 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 12953 for (index = 0; index <= 7; index++) { 12954 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 12955 port, index, &rval); 12956 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 12957 CELLMAXRESUMELIMITf, 12958 holcoscellmaxlimit_qgroup0_cellmaxlimit_up - 12959 ethernet_mtu_cell); 12960 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 12961 port, index, rval); 12962 } 12963 12964 /* COLOR_DROP_EN_QGROUPr, index 0 */ 12965 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 12966 port, 0, &rval); 12967 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 12968 COLOR_DROP_ENf, 12969 0); 12970 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 12971 port, 0, rval); 12972 12973 /* SHARED_POOL_CTRLr, index 0 */ 12974 soc_reg32_get(unit, SHARED_POOL_CTRLr, 12975 port, 0, &rval); 12976 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 12977 DYNAMIC_COS_DROP_ENf, 12978 255); 12979 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 12980 SHARED_POOL_DISCARD_ENf, 12981 127); 12982 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 12983 SHARED_POOL_XOFF_ENf, 12984 0); 12985 soc_reg32_set(unit, SHARED_POOL_CTRLr, 12986 port, 0, rval); 12987 12988 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 12989 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 12990 port, 0, &rval); 12991 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 12992 DYNAMIC_COS_DROP_ENf, 12993 0xFFFFFF); 12994 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 12995 port, 0, rval); 12996 12997 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 12998 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 12999 port, 0, &rval); 13000 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 13001 DYNAMIC_COS_DROP_ENf, 13002 0xFFFFFFFF); 13003 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 13004 port, 0, rval); 13005 } 13006 13007 /* port-based : downlink 1G */ 13008 SOC_PBMP_ITER(pbmp_downlink_1g, port) { 13009 /* PG_CTRL0r, index 0 */ 13010 soc_reg32_get(unit, PG_CTRL0r, 13011 port, 0, &rval); 13012 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13013 PPFC_PG_ENf, 13014 128); 13015 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13016 PRI0_GRPf, 13017 /* coverity[dead_error_line : FALSE] */ 13018 flow_control_type_pause_0_pfc_1?0:7); 13019 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13020 PRI1_GRPf, 13021 /* coverity[dead_error_line : FALSE] */ 13022 flow_control_type_pause_0_pfc_1?1:7); 13023 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13024 PRI2_GRPf, 13025 /* coverity[dead_error_line : FALSE] */ 13026 flow_control_type_pause_0_pfc_1?2:7); 13027 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13028 PRI3_GRPf, 13029 /* coverity[dead_error_line : FALSE] */ 13030 flow_control_type_pause_0_pfc_1?3:7); 13031 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13032 PRI4_GRPf, 13033 /* coverity[dead_error_line : FALSE] */ 13034 flow_control_type_pause_0_pfc_1?4:7); 13035 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13036 PRI5_GRPf, 13037 /* coverity[dead_error_line : FALSE] */ 13038 flow_control_type_pause_0_pfc_1?5:7); 13039 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13040 PRI6_GRPf, 13041 /* coverity[dead_error_line : FALSE] */ 13042 flow_control_type_pause_0_pfc_1?6:7); 13043 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13044 PRI7_GRPf, 13045 /* coverity[identical_branches : FALSE] */ 13046 flow_control_type_pause_0_pfc_1?7:7); 13047 soc_reg32_set(unit, PG_CTRL0r, 13048 port, 0, rval); 13049 13050 /* PG_CTRL1r, index 0 */ 13051 soc_reg32_get(unit, PG_CTRL1r, 13052 port, 0, &rval); 13053 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13054 PRI8_GRPf, 13055 /* coverity[identical_branches : FALSE] */ 13056 flow_control_type_pause_0_pfc_1?7:7); 13057 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13058 PRI9_GRPf, 13059 /* coverity[identical_branches : FALSE] */ 13060 flow_control_type_pause_0_pfc_1?7:7); 13061 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13062 PRI10_GRPf, 13063 /* coverity[identical_branches : FALSE] */ 13064 flow_control_type_pause_0_pfc_1?7:7); 13065 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13066 PRI11_GRPf, 13067 /* coverity[identical_branches : FALSE] */ 13068 flow_control_type_pause_0_pfc_1?7:7); 13069 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13070 PRI12_GRPf, 13071 /* coverity[identical_branches : FALSE] */ 13072 flow_control_type_pause_0_pfc_1?7:7); 13073 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13074 PRI13_GRPf, 13075 /* coverity[identical_branches : FALSE] */ 13076 flow_control_type_pause_0_pfc_1?7:7); 13077 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13078 PRI14_GRPf, 13079 /* coverity[identical_branches : FALSE] */ 13080 flow_control_type_pause_0_pfc_1?7:7); 13081 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13082 PRI15_GRPf, 13083 /* coverity[identical_branches : FALSE] */ 13084 flow_control_type_pause_0_pfc_1?7:7); 13085 soc_reg32_set(unit, PG_CTRL1r, 13086 port, 0, rval); 13087 13088 /* PG2TCr, index 0 ~ 6 */ 13089 for (index = 0; index <= 6; index++) { 13090 soc_reg32_get(unit, PG2TCr, 13091 port, index, &rval); 13092 soc_reg_field_set(unit, PG2TCr, &rval, 13093 PG_BMPf, 13094 0); 13095 soc_reg32_set(unit, PG2TCr, 13096 port, index, rval); 13097 } 13098 13099 /* PG2TCr, index 7 */ 13100 soc_reg32_get(unit, PG2TCr, 13101 port, 7, &rval); 13102 soc_reg_field_set(unit, PG2TCr, &rval, 13103 PG_BMPf, 13104 /* coverity[dead_error_line : FALSE] */ 13105 flow_control_type_pause_0_pfc_1?128:255); 13106 soc_reg32_set(unit, PG2TCr, 13107 port, 7, rval); 13108 13109 /* IBPPKTSETLIMITr, index 0 */ 13110 soc_reg32_get(unit, IBPPKTSETLIMITr, 13111 port, 0, &rval); 13112 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 13113 PKTSETLIMITf, 13114 xoff_packet_thresholds_per_port_downlink_port); 13115 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 13116 RESETLIMITSELf, 13117 3); 13118 soc_reg32_set(unit, IBPPKTSETLIMITr, 13119 port, 0, rval); 13120 13121 /* MMU_FC_RX_ENr, index 0 */ 13122 soc_reg32_get(unit, MMU_FC_RX_ENr, 13123 port, 0, &rval); 13124 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 13125 MMU_FC_RX_ENABLEf, 13126 128); 13127 soc_reg32_set(unit, MMU_FC_RX_ENr, 13128 port, 0, rval); 13129 13130 /* MMU_FC_TX_ENr, index 0 */ 13131 soc_reg32_get(unit, MMU_FC_TX_ENr, 13132 port, 0, &rval); 13133 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 13134 MMU_FC_TX_ENABLEf, 13135 128); 13136 soc_reg32_set(unit, MMU_FC_TX_ENr, 13137 port, 0, rval); 13138 13139 /* PGCELLLIMITr, index 0 ~ 6 */ 13140 for (index = 0; index <= 6; index++) { 13141 soc_reg32_get(unit, PGCELLLIMITr, 13142 port, index, &rval); 13143 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13144 CELLSETLIMITf, 13145 xoff_cell_threshold_all_uplink_ports); 13146 soc_reg32_set(unit, PGCELLLIMITr, 13147 port, index, rval); 13148 } 13149 13150 /* PGCELLLIMITr, index 7 */ 13151 soc_reg32_get(unit, PGCELLLIMITr, 13152 port, 7, &rval); 13153 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13154 CELLSETLIMITf, 13155 xoff_cell_thresholds_per_port_1g_port_downlink_ports); 13156 soc_reg32_set(unit, PGCELLLIMITr, 13157 port, 7, rval); 13158 13159 /* PGCELLLIMITr, index 0 ~ 6 */ 13160 for (index = 0; index <= 6; index++) { 13161 soc_reg32_get(unit, PGCELLLIMITr, 13162 port, index, &rval); 13163 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13164 CELLRESETLIMITf, 13165 xoff_cell_threshold_all_uplink_ports); 13166 soc_reg32_set(unit, PGCELLLIMITr, 13167 port, index, rval); 13168 } 13169 13170 /* PGCELLLIMITr, index 7 */ 13171 soc_reg32_get(unit, PGCELLLIMITr, 13172 port, 7, &rval); 13173 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13174 CELLRESETLIMITf, 13175 xoff_cell_thresholds_per_port_1g_port_downlink_ports); 13176 soc_reg32_set(unit, PGCELLLIMITr, 13177 port, 7, rval); 13178 13179 /* PGDISCARDSETLIMITr, index 0 ~ 6 */ 13180 for (index = 0; index <= 6; index++) { 13181 soc_reg32_get(unit, PGDISCARDSETLIMITr, 13182 port, index, &rval); 13183 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 13184 DISCARDSETLIMITf, 13185 discard_limit_per_port_pg_downlink_port); 13186 soc_reg32_set(unit, PGDISCARDSETLIMITr, 13187 port, index, rval); 13188 } 13189 13190 /* PGDISCARDSETLIMITr, index 7 */ 13191 soc_reg32_get(unit, PGDISCARDSETLIMITr, 13192 port, 7, &rval); 13193 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 13194 DISCARDSETLIMITf, 13195 discard_limit_per_port_pg_uplink_1g_port); 13196 soc_reg32_set(unit, PGDISCARDSETLIMITr, 13197 port, 7, rval); 13198 13199 /* HOLCOSMINXQCNTr, index 0 ~ 6 */ 13200 for (index = 0; index <= 6; index++) { 13201 soc_reg32_get(unit, HOLCOSMINXQCNTr, 13202 port, index, &rval); 13203 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 13204 HOLCOSMINXQCNTf, 13205 egress_xq_min_reserve_lossy_ports); 13206 soc_reg32_set(unit, HOLCOSMINXQCNTr, 13207 port, index, rval); 13208 } 13209 13210 /* HOLCOSMINXQCNTr, index 7 */ 13211 soc_reg32_get(unit, HOLCOSMINXQCNTr, 13212 port, 7, &rval); 13213 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 13214 HOLCOSMINXQCNTf, 13215 egress_xq_min_reserve_lossless_downlink_ports); 13216 soc_reg32_set(unit, HOLCOSMINXQCNTr, 13217 port, 7, rval); 13218 13219 /* HOLCOSMINXQCNT_QLAYERr, index 0 ~ 6 */ 13220 for (index = 0; index <= 6; index++) { 13221 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 13222 port, index, &rval); 13223 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 13224 HOLCOSMINXQCNTf, 13225 egress_xq_min_reserve_lossy_ports); 13226 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 13227 port, index, rval); 13228 } 13229 13230 /* HOLCOSMINXQCNT_QLAYERr, index 7 */ 13231 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 13232 port, 7, &rval); 13233 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 13234 HOLCOSMINXQCNTf, 13235 egress_xq_min_reserve_lossless_downlink_ports); 13236 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 13237 port, 7, rval); 13238 13239 /* HOLCOSMINXQCNT_QLAYERr, index 8 ~ 63 */ 13240 for (index = 8; index <= 63; index++) { 13241 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 13242 port, index, &rval); 13243 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 13244 HOLCOSMINXQCNTf, 13245 0); 13246 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 13247 port, index, rval); 13248 } 13249 13250 /* HOLCOSPKTSETLIMITr, index 0 ~ 6 */ 13251 for (index = 0; index <= 6; index++) { 13252 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 13253 port, index, &rval); 13254 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 13255 PKTSETLIMITf, 13256 shared_xqs_per_downlink_port + 13257 egress_xq_min_reserve_lossy_ports); 13258 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 13259 port, index, rval); 13260 } 13261 13262 /* HOLCOSPKTSETLIMITr, index 7 */ 13263 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 13264 port, 7, &rval); 13265 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 13266 PKTSETLIMITf, 13267 shared_xqs_per_downlink_port + 13268 egress_xq_min_reserve_lossless_downlink_ports); 13269 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 13270 port, 7, rval); 13271 13272 /* HOLCOSPKTSETLIMIT_QLAYERr, index 0 ~ 6 */ 13273 for (index = 0; index <= 6; index++) { 13274 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 13275 port, index, &rval); 13276 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 13277 PKTSETLIMITf, 13278 shared_xqs_per_downlink_port + 13279 egress_xq_min_reserve_lossy_ports); 13280 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 13281 port, index, rval); 13282 } 13283 13284 /* HOLCOSPKTSETLIMIT_QLAYERr, index 7 */ 13285 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 13286 port, 7, &rval); 13287 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 13288 PKTSETLIMITf, 13289 shared_xqs_per_downlink_port + 13290 egress_xq_min_reserve_lossless_downlink_ports); 13291 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 13292 port, 7, rval); 13293 13294 /* HOLCOSPKTSETLIMIT_QLAYERr, index 8 ~ 63 */ 13295 for (index = 8; index <= 63; index++) { 13296 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 13297 port, index, &rval); 13298 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 13299 PKTSETLIMITf, 13300 shared_xqs_per_downlink_port + 13301 holcosminxqcnt_qlayer8_holcosminxqcnt_down_1); 13302 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 13303 port, index, rval); 13304 } 13305 13306 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 13307 for (index = 0; index <= 6; index++) { 13308 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 13309 port, index, &rval); 13310 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 13311 PKTRESETLIMITf, 13312 holcospktsetlimit0_pktsetlimit_down_1 - 1); 13313 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 13314 port, index, rval); 13315 } 13316 13317 /* HOLCOSPKTRESETLIMITr, index 7 */ 13318 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 13319 port, 7, &rval); 13320 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 13321 PKTRESETLIMITf, 13322 holcospktsetlimit7_pktsetlimit_down_1 - 1); 13323 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 13324 port, 7, rval); 13325 13326 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 0 ~ 6 */ 13327 for (index = 0; index <= 6; index++) { 13328 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 13329 port, index, &rval); 13330 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 13331 PKTRESETLIMITf, 13332 holcospktsetlimit_qlayer0_pktsetlimit_down_1 - 1); 13333 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 13334 port, index, rval); 13335 } 13336 13337 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 7 */ 13338 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 13339 port, 7, &rval); 13340 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 13341 PKTRESETLIMITf, 13342 holcospktsetlimit_qlayer7_pktsetlimit_down_1 - 1); 13343 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 13344 port, 7, rval); 13345 13346 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 8 ~ 63 */ 13347 for (index = 8; index <= 63; index++) { 13348 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 13349 port, index, &rval); 13350 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 13351 PKTRESETLIMITf, 13352 holcospktsetlimit_qlayer8_pktsetlimit_down_1 - 1); 13353 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 13354 port, index, rval); 13355 } 13356 13357 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 13358 for (index = 0; index <= 7; index++) { 13359 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 13360 port, index, &rval); 13361 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 13362 CNGPKTSETLIMIT0f, 13363 numxqs_per_downlink_ports_and_cpu_port - 1); 13364 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 13365 port, index, rval); 13366 } 13367 13368 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 13369 for (index = 0; index <= 7; index++) { 13370 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 13371 port, index, &rval); 13372 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 13373 CNGPKTSETLIMIT1f, 13374 numxqs_per_downlink_ports_and_cpu_port - 1); 13375 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 13376 port, index, rval); 13377 } 13378 13379 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 13380 for (index = 0; index <= 63; index++) { 13381 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 13382 port, index, &rval); 13383 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 13384 CNGPKTSETLIMIT0f, 13385 numxqs_per_downlink_ports_and_cpu_port - 1); 13386 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 13387 port, index, rval); 13388 } 13389 13390 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 13391 for (index = 0; index <= 63; index++) { 13392 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 13393 port, index, &rval); 13394 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 13395 CNGPKTSETLIMIT1f, 13396 numxqs_per_downlink_ports_and_cpu_port - 1); 13397 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 13398 port, index, rval); 13399 } 13400 13401 /* CNGPORTPKTLIMIT0r, index 0 */ 13402 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 13403 port, 0, &rval); 13404 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 13405 CNGPORTPKTLIMIT0f, 13406 numxqs_per_downlink_ports_and_cpu_port - 1); 13407 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 13408 port, 0, rval); 13409 13410 /* CNGPORTPKTLIMIT1r, index 0 */ 13411 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 13412 port, 0, &rval); 13413 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 13414 CNGPORTPKTLIMIT1f, 13415 numxqs_per_downlink_ports_and_cpu_port - 1); 13416 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 13417 port, 0, rval); 13418 13419 /* DYNXQCNTPORTr, index 0 */ 13420 soc_reg32_get(unit, DYNXQCNTPORTr, 13421 port, 0, &rval); 13422 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 13423 DYNXQCNTPORTf, 13424 shared_xqs_per_downlink_port - skidmarker - prefetch); 13425 soc_reg32_set(unit, DYNXQCNTPORTr, 13426 port, 0, rval); 13427 13428 /* DYNRESETLIMPORTr, index 0 */ 13429 soc_reg32_get(unit, DYNRESETLIMPORTr, 13430 port, 0, &rval); 13431 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 13432 DYNRESETLIMPORTf, 13433 dynxqcntport_dynxqcntport_down_1 - 2); 13434 soc_reg32_set(unit, DYNRESETLIMPORTr, 13435 port, 0, rval); 13436 13437 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 13438 for (index = 0; index <= 6; index++) { 13439 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 13440 port, index, &rval); 13441 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 13442 CELLSETLIMITf, 13443 egress_queue_min_reserve_downlink_ports_lossy); 13444 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 13445 port, index, rval); 13446 } 13447 13448 /* LWMCOSCELLSETLIMITr, index 7 */ 13449 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 13450 port, 7, &rval); 13451 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 13452 CELLSETLIMITf, 13453 egress_queue_min_reserve_downlink_ports_lossless); 13454 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 13455 port, 7, rval); 13456 13457 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 13458 for (index = 0; index <= 6; index++) { 13459 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13460 port, index, &rval); 13461 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 13462 CELLSETLIMITf, 13463 egress_queue_min_reserve_downlink_ports_lossy); 13464 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13465 port, index, rval); 13466 } 13467 13468 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 13469 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13470 port, 7, &rval); 13471 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 13472 CELLSETLIMITf, 13473 egress_queue_min_reserve_downlink_ports_lossless); 13474 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13475 port, 7, rval); 13476 13477 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 13478 for (index = 8; index <= 63; index++) { 13479 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13480 port, index, &rval); 13481 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 13482 CELLSETLIMITf, 13483 0); 13484 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13485 port, index, rval); 13486 } 13487 13488 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 13489 for (index = 0; index <= 6; index++) { 13490 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 13491 port, index, &rval); 13492 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 13493 CELLRESETLIMITf, 13494 egress_queue_min_reserve_downlink_ports_lossy); 13495 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 13496 port, index, rval); 13497 } 13498 13499 /* LWMCOSCELLSETLIMITr, index 7 */ 13500 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 13501 port, 7, &rval); 13502 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 13503 CELLRESETLIMITf, 13504 egress_queue_min_reserve_downlink_ports_lossless); 13505 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 13506 port, 7, rval); 13507 13508 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 13509 for (index = 0; index <= 6; index++) { 13510 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13511 port, index, &rval); 13512 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 13513 CELLRESETLIMITf, 13514 egress_queue_min_reserve_downlink_ports_lossy); 13515 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13516 port, index, rval); 13517 } 13518 13519 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 13520 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13521 port, 7, &rval); 13522 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 13523 CELLRESETLIMITf, 13524 egress_queue_min_reserve_downlink_ports_lossless); 13525 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13526 port, 7, rval); 13527 13528 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 13529 for (index = 8; index <= 63; index++) { 13530 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13531 port, index, &rval); 13532 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 13533 CELLRESETLIMITf, 13534 0); 13535 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 13536 port, index, rval); 13537 } 13538 13539 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 13540 for (index = 0; index <= 6; index++) { 13541 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 13542 port, index, &rval); 13543 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 13544 CELLMAXLIMITf, 13545 ceiling_func(shared_space_cells, 13546 queue_port_limit_ratio) + 13547 lwmcoscellsetlimit0_cellsetlimit_down_1); 13548 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 13549 port, index, rval); 13550 } 13551 13552 /* HOLCOSCELLMAXLIMITr, index 7 */ 13553 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 13554 port, 7, &rval); 13555 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 13556 CELLMAXLIMITf, 13557 ceiling_func(shared_space_cells, 13558 queue_port_limit_ratio) + 13559 lwmcoscellsetlimit7_cellsetlimit_down_1); 13560 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 13561 port, 7, rval); 13562 13563 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 13564 for (index = 0; index <= 6; index++) { 13565 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13566 port, index, &rval); 13567 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 13568 CELLMAXLIMITf, 13569 ceiling_func(shared_space_cells, 13570 queue_port_limit_ratio) + 13571 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_1); 13572 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13573 port, index, rval); 13574 } 13575 13576 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 13577 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13578 port, 7, &rval); 13579 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 13580 CELLMAXLIMITf, 13581 ceiling_func(shared_space_cells, 13582 queue_port_limit_ratio) + 13583 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_1); 13584 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13585 port, 7, rval); 13586 13587 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 13588 for (index = 8; index <= 63; index++) { 13589 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13590 port, index, &rval); 13591 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 13592 CELLMAXLIMITf, 13593 ceiling_func(shared_space_cells, 13594 queue_port_limit_ratio) + 13595 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_1); 13596 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13597 port, index, rval); 13598 } 13599 13600 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 13601 for (index = 0; index <= 6; index++) { 13602 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 13603 port, index, &rval); 13604 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 13605 CELLMAXRESUMELIMITf, 13606 holcoscellmaxlimit0_cellmaxlimit_down_1 - 13607 ethernet_mtu_cell); 13608 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 13609 port, index, rval); 13610 } 13611 13612 /* HOLCOSCELLMAXLIMITr, index 7 */ 13613 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 13614 port, 7, &rval); 13615 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 13616 CELLMAXRESUMELIMITf, 13617 holcoscellmaxlimit7_cellmaxlimit_down_1 - 13618 ethernet_mtu_cell); 13619 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 13620 port, 7, rval); 13621 13622 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 13623 for (index = 0; index <= 6; index++) { 13624 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13625 port, index, &rval); 13626 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 13627 CELLMAXRESUMELIMITf, 13628 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_1 - 13629 ethernet_mtu_cell); 13630 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13631 port, index, rval); 13632 } 13633 13634 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 13635 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13636 port, 7, &rval); 13637 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 13638 CELLMAXRESUMELIMITf, 13639 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_1 - 13640 ethernet_mtu_cell); 13641 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13642 port, 7, rval); 13643 13644 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 13645 for (index = 8; index <= 63; index++) { 13646 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13647 port, index, &rval); 13648 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 13649 CELLMAXRESUMELIMITf, 13650 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_1 - 13651 ethernet_mtu_cell); 13652 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 13653 port, index, rval); 13654 } 13655 13656 /* DYNCELLLIMITr, index 0 */ 13657 soc_reg32_get(unit, DYNCELLLIMITr, 13658 port, 0, &rval); 13659 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 13660 DYNCELLSETLIMITf, 13661 shared_space_cells); 13662 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 13663 DYNCELLRESETLIMITf, 13664 dyncelllimit_dyncellsetlimit_down_1 - 13665 (ethernet_mtu_cell * 2)); 13666 soc_reg32_set(unit, DYNCELLLIMITr, 13667 port, 0, rval); 13668 13669 /* COLOR_DROP_ENr, index 0 */ 13670 soc_reg32_get(unit, COLOR_DROP_ENr, 13671 port, 0, &rval); 13672 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 13673 COLOR_DROP_ENf, 13674 0); 13675 soc_reg32_set(unit, COLOR_DROP_ENr, 13676 port, 0, rval); 13677 13678 /* COLOR_DROP_EN_QLAYERr, index 0 */ 13679 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 13680 port, 0, &rval); 13681 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 13682 COLOR_DROP_ENf, 13683 0); 13684 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 13685 port, 0, rval); 13686 13687 /* HOLCOSPKTSETLIMIT_QGROUPr, index 0 ~ 7 */ 13688 for (index = 0; index <= 7; index++) { 13689 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QGROUPr, 13690 port, index, &rval); 13691 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, &rval, 13692 PKTSETLIMITf, 13693 numxqs_per_downlink_ports_and_cpu_port - 1); 13694 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, 13695 port, index, rval); 13696 } 13697 13698 /* HOLCOSPKTRESETLIMIT_QGROUPr, index 0 ~ 7 */ 13699 for (index = 0; index <= 7; index++) { 13700 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 13701 port, index, &rval); 13702 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, &rval, 13703 PKTRESETLIMITf, 13704 holcospktsetlimit_qgroup0_pktsetlimit_down_1 - 1); 13705 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 13706 port, index, rval); 13707 } 13708 13709 /* CNGCOSPKTLIMIT0_QGROUPr, index 0 ~ 7 */ 13710 for (index = 0; index <= 7; index++) { 13711 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QGROUPr, 13712 port, index, &rval); 13713 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QGROUPr, &rval, 13714 CNGPKTSETLIMIT0f, 13715 numxqs_per_downlink_ports_and_cpu_port - 1); 13716 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QGROUPr, 13717 port, index, rval); 13718 } 13719 13720 /* CNGCOSPKTLIMIT1_QGROUPr, index 0 ~ 7 */ 13721 for (index = 0; index <= 7; index++) { 13722 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QGROUPr, 13723 port, index, &rval); 13724 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QGROUPr, &rval, 13725 CNGPKTSETLIMIT1f, 13726 numxqs_per_downlink_ports_and_cpu_port - 1); 13727 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QGROUPr, 13728 port, index, rval); 13729 } 13730 13731 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 13732 for (index = 0; index <= 7; index++) { 13733 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 13734 port, index, &rval); 13735 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 13736 CELLMAXLIMITf, 13737 ceiling_func(total_advertised_cell_memory, 13738 queue_port_limit_ratio)); 13739 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 13740 port, index, rval); 13741 } 13742 13743 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 13744 for (index = 0; index <= 7; index++) { 13745 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 13746 port, index, &rval); 13747 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 13748 CELLMAXRESUMELIMITf, 13749 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_1 - 13750 ethernet_mtu_cell); 13751 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 13752 port, index, rval); 13753 } 13754 13755 /* COLOR_DROP_EN_QGROUPr, index 0 */ 13756 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 13757 port, 0, &rval); 13758 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 13759 COLOR_DROP_ENf, 13760 0); 13761 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 13762 port, 0, rval); 13763 13764 /* SHARED_POOL_CTRLr, index 0 */ 13765 soc_reg32_get(unit, SHARED_POOL_CTRLr, 13766 port, 0, &rval); 13767 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 13768 DYNAMIC_COS_DROP_ENf, 13769 255); 13770 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 13771 SHARED_POOL_DISCARD_ENf, 13772 127); 13773 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 13774 SHARED_POOL_XOFF_ENf, 13775 0); 13776 soc_reg32_set(unit, SHARED_POOL_CTRLr, 13777 port, 0, rval); 13778 13779 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 13780 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 13781 port, 0, &rval); 13782 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 13783 DYNAMIC_COS_DROP_ENf, 13784 0xFFFFFF); 13785 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 13786 port, 0, rval); 13787 13788 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 13789 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 13790 port, 0, &rval); 13791 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 13792 DYNAMIC_COS_DROP_ENf, 13793 0xFFFFFFFF); 13794 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 13795 port, 0, rval); 13796 } 13797 13798 /* port-based : downlink 2.5G */ 13799 SOC_PBMP_ITER(pbmp_downlink_2dot5g, port) { 13800 /* PG_CTRL0r, index 0 */ 13801 soc_reg32_get(unit, PG_CTRL0r, 13802 port, 0, &rval); 13803 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13804 PPFC_PG_ENf, 13805 128); 13806 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13807 PRI0_GRPf, 13808 /* coverity[dead_error_line : FALSE] */ 13809 flow_control_type_pause_0_pfc_1?0:7); 13810 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13811 PRI1_GRPf, 13812 /* coverity[dead_error_line : FALSE] */ 13813 flow_control_type_pause_0_pfc_1?1:7); 13814 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13815 PRI2_GRPf, 13816 /* coverity[dead_error_line : FALSE] */ 13817 flow_control_type_pause_0_pfc_1?2:7); 13818 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13819 PRI3_GRPf, 13820 /* coverity[dead_error_line : FALSE] */ 13821 flow_control_type_pause_0_pfc_1?3:7); 13822 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13823 PRI4_GRPf, 13824 /* coverity[dead_error_line : FALSE] */ 13825 flow_control_type_pause_0_pfc_1?4:7); 13826 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13827 PRI5_GRPf, 13828 /* coverity[dead_error_line : FALSE] */ 13829 flow_control_type_pause_0_pfc_1?5:7); 13830 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13831 PRI6_GRPf, 13832 /* coverity[dead_error_line : FALSE] */ 13833 flow_control_type_pause_0_pfc_1?6:7); 13834 soc_reg_field_set(unit, PG_CTRL0r, &rval, 13835 PRI7_GRPf, 13836 /* coverity[identical_branches : FALSE] */ 13837 flow_control_type_pause_0_pfc_1?7:7); 13838 soc_reg32_set(unit, PG_CTRL0r, 13839 port, 0, rval); 13840 13841 /* PG_CTRL1r, index 0 */ 13842 soc_reg32_get(unit, PG_CTRL1r, 13843 port, 0, &rval); 13844 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13845 PRI8_GRPf, 13846 /* coverity[identical_branches : FALSE] */ 13847 flow_control_type_pause_0_pfc_1?7:7); 13848 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13849 PRI9_GRPf, 13850 /* coverity[identical_branches : FALSE] */ 13851 flow_control_type_pause_0_pfc_1?7:7); 13852 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13853 PRI10_GRPf, 13854 /* coverity[identical_branches : FALSE] */ 13855 flow_control_type_pause_0_pfc_1?7:7); 13856 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13857 PRI11_GRPf, 13858 /* coverity[identical_branches : FALSE] */ 13859 flow_control_type_pause_0_pfc_1?7:7); 13860 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13861 PRI12_GRPf, 13862 /* coverity[identical_branches : FALSE] */ 13863 flow_control_type_pause_0_pfc_1?7:7); 13864 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13865 PRI13_GRPf, 13866 /* coverity[identical_branches : FALSE] */ 13867 flow_control_type_pause_0_pfc_1?7:7); 13868 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13869 PRI14_GRPf, 13870 /* coverity[identical_branches : FALSE] */ 13871 flow_control_type_pause_0_pfc_1?7:7); 13872 soc_reg_field_set(unit, PG_CTRL1r, &rval, 13873 PRI15_GRPf, 13874 /* coverity[identical_branches : FALSE] */ 13875 flow_control_type_pause_0_pfc_1?7:7); 13876 soc_reg32_set(unit, PG_CTRL1r, 13877 port, 0, rval); 13878 13879 /* PG2TCr, index 0 ~ 6 */ 13880 for (index = 0; index <= 6; index++) { 13881 soc_reg32_get(unit, PG2TCr, 13882 port, index, &rval); 13883 soc_reg_field_set(unit, PG2TCr, &rval, 13884 PG_BMPf, 13885 0); 13886 soc_reg32_set(unit, PG2TCr, 13887 port, index, rval); 13888 } 13889 13890 /* PG2TCr, index 7 */ 13891 soc_reg32_get(unit, PG2TCr, 13892 port, 7, &rval); 13893 soc_reg_field_set(unit, PG2TCr, &rval, 13894 PG_BMPf, 13895 /* coverity[dead_error_line : FALSE] */ 13896 flow_control_type_pause_0_pfc_1?128:255); 13897 soc_reg32_set(unit, PG2TCr, 13898 port, 7, rval); 13899 13900 /* IBPPKTSETLIMITr, index 0 */ 13901 soc_reg32_get(unit, IBPPKTSETLIMITr, 13902 port, 0, &rval); 13903 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 13904 PKTSETLIMITf, 13905 xoff_packet_thresholds_per_port_downlink_port); 13906 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 13907 RESETLIMITSELf, 13908 3); 13909 soc_reg32_set(unit, IBPPKTSETLIMITr, 13910 port, 0, rval); 13911 13912 /* MMU_FC_RX_ENr, index 0 */ 13913 soc_reg32_get(unit, MMU_FC_RX_ENr, 13914 port, 0, &rval); 13915 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 13916 MMU_FC_RX_ENABLEf, 13917 128); 13918 soc_reg32_set(unit, MMU_FC_RX_ENr, 13919 port, 0, rval); 13920 13921 /* MMU_FC_TX_ENr, index 0 */ 13922 soc_reg32_get(unit, MMU_FC_TX_ENr, 13923 port, 0, &rval); 13924 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 13925 MMU_FC_TX_ENABLEf, 13926 128); 13927 soc_reg32_set(unit, MMU_FC_TX_ENr, 13928 port, 0, rval); 13929 13930 /* PGCELLLIMITr, index 0 ~ 6 */ 13931 for (index = 0; index <= 6; index++) { 13932 soc_reg32_get(unit, PGCELLLIMITr, 13933 port, index, &rval); 13934 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13935 CELLSETLIMITf, 13936 xoff_cell_threshold_all_uplink_ports); 13937 soc_reg32_set(unit, PGCELLLIMITr, 13938 port, index, rval); 13939 } 13940 13941 /* PGCELLLIMITr, index 7 */ 13942 soc_reg32_get(unit, PGCELLLIMITr, 13943 port, 7, &rval); 13944 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13945 CELLSETLIMITf, 13946 xoff_cell_thresholds_per_port_2dot5g_downlink_ports); 13947 soc_reg32_set(unit, PGCELLLIMITr, 13948 port, 7, rval); 13949 13950 /* PGCELLLIMITr, index 0 ~ 6 */ 13951 for (index = 0; index <= 6; index++) { 13952 soc_reg32_get(unit, PGCELLLIMITr, 13953 port, index, &rval); 13954 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13955 CELLRESETLIMITf, 13956 xoff_cell_threshold_all_uplink_ports); 13957 soc_reg32_set(unit, PGCELLLIMITr, 13958 port, index, rval); 13959 } 13960 13961 /* PGCELLLIMITr, index 7 */ 13962 soc_reg32_get(unit, PGCELLLIMITr, 13963 port, 7, &rval); 13964 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 13965 CELLRESETLIMITf, 13966 xoff_cell_thresholds_per_port_2dot5g_downlink_ports); 13967 soc_reg32_set(unit, PGCELLLIMITr, 13968 port, 7, rval); 13969 13970 /* PGDISCARDSETLIMITr, index 0 ~ 6 */ 13971 for (index = 0; index <= 6; index++) { 13972 soc_reg32_get(unit, PGDISCARDSETLIMITr, 13973 port, index, &rval); 13974 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 13975 DISCARDSETLIMITf, 13976 discard_limit_per_port_pg_downlink_port); 13977 soc_reg32_set(unit, PGDISCARDSETLIMITr, 13978 port, index, rval); 13979 } 13980 13981 /* PGDISCARDSETLIMITr, index 7 */ 13982 soc_reg32_get(unit, PGDISCARDSETLIMITr, 13983 port, 7, &rval); 13984 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 13985 DISCARDSETLIMITf, 13986 discard_limit_per_port_pg_uplink_2dot5g_port); 13987 soc_reg32_set(unit, PGDISCARDSETLIMITr, 13988 port, 7, rval); 13989 13990 /* HOLCOSMINXQCNTr, index 0 ~ 6 */ 13991 for (index = 0; index <= 6; index++) { 13992 soc_reg32_get(unit, HOLCOSMINXQCNTr, 13993 port, index, &rval); 13994 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 13995 HOLCOSMINXQCNTf, 13996 egress_xq_min_reserve_lossy_ports); 13997 soc_reg32_set(unit, HOLCOSMINXQCNTr, 13998 port, index, rval); 13999 } 14000 14001 /* HOLCOSMINXQCNTr, index 7 */ 14002 soc_reg32_get(unit, HOLCOSMINXQCNTr, 14003 port, 7, &rval); 14004 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 14005 HOLCOSMINXQCNTf, 14006 egress_xq_min_reserve_lossless_downlink_ports); 14007 soc_reg32_set(unit, HOLCOSMINXQCNTr, 14008 port, 7, rval); 14009 14010 /* HOLCOSMINXQCNT_QLAYERr, index 0 ~ 6 */ 14011 for (index = 0; index <= 6; index++) { 14012 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 14013 port, index, &rval); 14014 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 14015 HOLCOSMINXQCNTf, 14016 egress_xq_min_reserve_lossy_ports); 14017 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 14018 port, index, rval); 14019 } 14020 14021 /* HOLCOSMINXQCNT_QLAYERr, index 7 */ 14022 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 14023 port, 7, &rval); 14024 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 14025 HOLCOSMINXQCNTf, 14026 egress_xq_min_reserve_lossless_downlink_ports); 14027 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 14028 port, 7, rval); 14029 14030 /* HOLCOSMINXQCNT_QLAYERr, index 8 ~ 63 */ 14031 for (index = 8; index <= 63; index++) { 14032 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 14033 port, index, &rval); 14034 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 14035 HOLCOSMINXQCNTf, 14036 0); 14037 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 14038 port, index, rval); 14039 } 14040 14041 /* HOLCOSPKTSETLIMITr, index 0 ~ 6 */ 14042 for (index = 0; index <= 6; index++) { 14043 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 14044 port, index, &rval); 14045 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 14046 PKTSETLIMITf, 14047 shared_xqs_per_downlink_port + 14048 egress_xq_min_reserve_lossy_ports); 14049 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 14050 port, index, rval); 14051 } 14052 14053 /* HOLCOSPKTSETLIMITr, index 7 */ 14054 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 14055 port, 7, &rval); 14056 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 14057 PKTSETLIMITf, 14058 shared_xqs_per_downlink_port + 14059 egress_xq_min_reserve_lossless_downlink_ports); 14060 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 14061 port, 7, rval); 14062 14063 /* HOLCOSPKTSETLIMIT_QLAYERr, index 0 ~ 6 */ 14064 for (index = 0; index <= 6; index++) { 14065 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14066 port, index, &rval); 14067 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 14068 PKTSETLIMITf, 14069 shared_xqs_per_downlink_port + 14070 egress_xq_min_reserve_lossy_ports); 14071 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14072 port, index, rval); 14073 } 14074 14075 /* HOLCOSPKTSETLIMIT_QLAYERr, index 7 */ 14076 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14077 port, 7, &rval); 14078 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 14079 PKTSETLIMITf, 14080 shared_xqs_per_downlink_port + 14081 egress_xq_min_reserve_lossless_downlink_ports); 14082 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14083 port, 7, rval); 14084 14085 /* HOLCOSPKTSETLIMIT_QLAYERr, index 8 ~ 63 */ 14086 for (index = 8; index <= 63; index++) { 14087 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14088 port, index, &rval); 14089 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 14090 PKTSETLIMITf, 14091 shared_xqs_per_downlink_port + 14092 holcosminxqcnt_qlayer8_holcosminxqcnt_down_2dot5); 14093 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14094 port, index, rval); 14095 } 14096 14097 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 14098 for (index = 0; index <= 6; index++) { 14099 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 14100 port, index, &rval); 14101 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 14102 PKTRESETLIMITf, 14103 holcospktsetlimit0_pktsetlimit_down_2dot5 - 1); 14104 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 14105 port, index, rval); 14106 } 14107 14108 /* HOLCOSPKTRESETLIMITr, index 7 */ 14109 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 14110 port, 7, &rval); 14111 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 14112 PKTRESETLIMITf, 14113 holcospktsetlimit7_pktsetlimit_down_2dot5 - 1); 14114 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 14115 port, 7, rval); 14116 14117 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 0 ~ 6 */ 14118 for (index = 0; index <= 6; index++) { 14119 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14120 port, index, &rval); 14121 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 14122 PKTRESETLIMITf, 14123 holcospktsetlimit_qlayer0_pktsetlimit_down_2dot5 - 14124 1); 14125 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14126 port, index, rval); 14127 } 14128 14129 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 7 */ 14130 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14131 port, 7, &rval); 14132 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 14133 PKTRESETLIMITf, 14134 holcospktsetlimit_qlayer7_pktsetlimit_down_2dot5 - 1); 14135 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14136 port, 7, rval); 14137 14138 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 8 ~ 63 */ 14139 for (index = 8; index <= 63; index++) { 14140 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14141 port, index, &rval); 14142 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 14143 PKTRESETLIMITf, 14144 holcospktsetlimit_qlayer8_pktsetlimit_down_2dot5 - 14145 1); 14146 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14147 port, index, rval); 14148 } 14149 14150 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 14151 for (index = 0; index <= 7; index++) { 14152 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 14153 port, index, &rval); 14154 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 14155 CNGPKTSETLIMIT0f, 14156 numxqs_per_downlink_ports_and_cpu_port - 1); 14157 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 14158 port, index, rval); 14159 } 14160 14161 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 14162 for (index = 0; index <= 7; index++) { 14163 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 14164 port, index, &rval); 14165 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 14166 CNGPKTSETLIMIT1f, 14167 numxqs_per_downlink_ports_and_cpu_port - 1); 14168 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 14169 port, index, rval); 14170 } 14171 14172 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 14173 for (index = 0; index <= 63; index++) { 14174 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 14175 port, index, &rval); 14176 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 14177 CNGPKTSETLIMIT0f, 14178 numxqs_per_downlink_ports_and_cpu_port - 1); 14179 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 14180 port, index, rval); 14181 } 14182 14183 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 14184 for (index = 0; index <= 63; index++) { 14185 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 14186 port, index, &rval); 14187 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 14188 CNGPKTSETLIMIT1f, 14189 numxqs_per_downlink_ports_and_cpu_port - 1); 14190 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 14191 port, index, rval); 14192 } 14193 14194 /* CNGPORTPKTLIMIT0r, index 0 */ 14195 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 14196 port, 0, &rval); 14197 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 14198 CNGPORTPKTLIMIT0f, 14199 numxqs_per_downlink_ports_and_cpu_port - 1); 14200 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 14201 port, 0, rval); 14202 14203 /* CNGPORTPKTLIMIT1r, index 0 */ 14204 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 14205 port, 0, &rval); 14206 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 14207 CNGPORTPKTLIMIT1f, 14208 numxqs_per_downlink_ports_and_cpu_port - 1); 14209 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 14210 port, 0, rval); 14211 14212 /* DYNXQCNTPORTr, index 0 */ 14213 soc_reg32_get(unit, DYNXQCNTPORTr, 14214 port, 0, &rval); 14215 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 14216 DYNXQCNTPORTf, 14217 shared_xqs_per_downlink_port - skidmarker - prefetch); 14218 soc_reg32_set(unit, DYNXQCNTPORTr, 14219 port, 0, rval); 14220 14221 /* DYNRESETLIMPORTr, index 0 */ 14222 soc_reg32_get(unit, DYNRESETLIMPORTr, 14223 port, 0, &rval); 14224 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 14225 DYNRESETLIMPORTf, 14226 dynxqcntport_dynxqcntport_down_2dot5 - 2); 14227 soc_reg32_set(unit, DYNRESETLIMPORTr, 14228 port, 0, rval); 14229 14230 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 14231 for (index = 0; index <= 6; index++) { 14232 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 14233 port, index, &rval); 14234 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 14235 CELLSETLIMITf, 14236 egress_queue_min_reserve_downlink_ports_lossy); 14237 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 14238 port, index, rval); 14239 } 14240 14241 /* LWMCOSCELLSETLIMITr, index 7 */ 14242 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 14243 port, 7, &rval); 14244 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 14245 CELLSETLIMITf, 14246 egress_queue_min_reserve_downlink_ports_lossless); 14247 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 14248 port, 7, rval); 14249 14250 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 14251 for (index = 0; index <= 6; index++) { 14252 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14253 port, index, &rval); 14254 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 14255 CELLSETLIMITf, 14256 egress_queue_min_reserve_downlink_ports_lossy); 14257 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14258 port, index, rval); 14259 } 14260 14261 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 14262 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14263 port, 7, &rval); 14264 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 14265 CELLSETLIMITf, 14266 egress_queue_min_reserve_downlink_ports_lossless); 14267 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14268 port, 7, rval); 14269 14270 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 14271 for (index = 8; index <= 63; index++) { 14272 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14273 port, index, &rval); 14274 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 14275 CELLSETLIMITf, 14276 0); 14277 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14278 port, index, rval); 14279 } 14280 14281 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 14282 for (index = 0; index <= 6; index++) { 14283 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 14284 port, index, &rval); 14285 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 14286 CELLRESETLIMITf, 14287 egress_queue_min_reserve_downlink_ports_lossy); 14288 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 14289 port, index, rval); 14290 } 14291 14292 /* LWMCOSCELLSETLIMITr, index 7 */ 14293 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 14294 port, 7, &rval); 14295 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 14296 CELLRESETLIMITf, 14297 egress_queue_min_reserve_downlink_ports_lossless); 14298 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 14299 port, 7, rval); 14300 14301 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 14302 for (index = 0; index <= 6; index++) { 14303 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14304 port, index, &rval); 14305 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 14306 CELLRESETLIMITf, 14307 egress_queue_min_reserve_downlink_ports_lossy); 14308 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14309 port, index, rval); 14310 } 14311 14312 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 14313 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14314 port, 7, &rval); 14315 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 14316 CELLRESETLIMITf, 14317 egress_queue_min_reserve_downlink_ports_lossless); 14318 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14319 port, 7, rval); 14320 14321 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 14322 for (index = 8; index <= 63; index++) { 14323 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14324 port, index, &rval); 14325 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 14326 CELLRESETLIMITf, 14327 0); 14328 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 14329 port, index, rval); 14330 } 14331 14332 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 14333 for (index = 0; index <= 6; index++) { 14334 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 14335 port, index, &rval); 14336 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 14337 CELLMAXLIMITf, 14338 ceiling_func(shared_space_cells, 14339 queue_port_limit_ratio) + 14340 lwmcoscellsetlimit0_cellsetlimit_down_2dot5); 14341 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 14342 port, index, rval); 14343 } 14344 14345 /* HOLCOSCELLMAXLIMITr, index 7 */ 14346 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 14347 port, 7, &rval); 14348 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 14349 CELLMAXLIMITf, 14350 ceiling_func(shared_space_cells, 14351 queue_port_limit_ratio) + 14352 lwmcoscellsetlimit7_cellsetlimit_down_2dot5); 14353 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 14354 port, 7, rval); 14355 14356 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 14357 for (index = 0; index <= 6; index++) { 14358 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14359 port, index, &rval); 14360 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 14361 CELLMAXLIMITf, 14362 ceiling_func(shared_space_cells, 14363 queue_port_limit_ratio) + 14364 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_2dot5); 14365 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14366 port, index, rval); 14367 } 14368 14369 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 14370 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14371 port, 7, &rval); 14372 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 14373 CELLMAXLIMITf, 14374 ceiling_func(shared_space_cells, 14375 queue_port_limit_ratio) + 14376 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_2dot5); 14377 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14378 port, 7, rval); 14379 14380 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 14381 for (index = 8; index <= 63; index++) { 14382 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14383 port, index, &rval); 14384 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 14385 CELLMAXLIMITf, 14386 ceiling_func(shared_space_cells, 14387 queue_port_limit_ratio) + 14388 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_2dot5); 14389 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14390 port, index, rval); 14391 } 14392 14393 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 14394 for (index = 0; index <= 6; index++) { 14395 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 14396 port, index, &rval); 14397 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 14398 CELLMAXRESUMELIMITf, 14399 holcoscellmaxlimit0_cellmaxlimit_down_2dot5 - 14400 ethernet_mtu_cell); 14401 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 14402 port, index, rval); 14403 } 14404 14405 /* HOLCOSCELLMAXLIMITr, index 7 */ 14406 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 14407 port, 7, &rval); 14408 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 14409 CELLMAXRESUMELIMITf, 14410 holcoscellmaxlimit7_cellmaxlimit_down_2dot5 - 14411 ethernet_mtu_cell); 14412 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 14413 port, 7, rval); 14414 14415 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 14416 for (index = 0; index <= 6; index++) { 14417 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14418 port, index, &rval); 14419 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 14420 CELLMAXRESUMELIMITf, 14421 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_2dot5 - 14422 ethernet_mtu_cell); 14423 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14424 port, index, rval); 14425 } 14426 14427 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 14428 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14429 port, 7, &rval); 14430 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 14431 CELLMAXRESUMELIMITf, 14432 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_2dot5 - 14433 ethernet_mtu_cell); 14434 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14435 port, 7, rval); 14436 14437 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 14438 for (index = 8; index <= 63; index++) { 14439 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14440 port, index, &rval); 14441 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 14442 CELLMAXRESUMELIMITf, 14443 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_2dot5 - 14444 ethernet_mtu_cell); 14445 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 14446 port, index, rval); 14447 } 14448 14449 /* DYNCELLLIMITr, index 0 */ 14450 soc_reg32_get(unit, DYNCELLLIMITr, 14451 port, 0, &rval); 14452 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 14453 DYNCELLSETLIMITf, 14454 shared_space_cells); 14455 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 14456 DYNCELLRESETLIMITf, 14457 dyncelllimit_dyncellsetlimit_down_2dot5 - 14458 (ethernet_mtu_cell * 2)); 14459 soc_reg32_set(unit, DYNCELLLIMITr, 14460 port, 0, rval); 14461 14462 /* COLOR_DROP_ENr, index 0 */ 14463 soc_reg32_get(unit, COLOR_DROP_ENr, 14464 port, 0, &rval); 14465 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 14466 COLOR_DROP_ENf, 14467 0); 14468 soc_reg32_set(unit, COLOR_DROP_ENr, 14469 port, 0, rval); 14470 14471 /* COLOR_DROP_EN_QLAYERr, index 0 */ 14472 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 14473 port, 0, &rval); 14474 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 14475 COLOR_DROP_ENf, 14476 0); 14477 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 14478 port, 0, rval); 14479 14480 /* HOLCOSPKTSETLIMIT_QGROUPr, index 0 ~ 7 */ 14481 for (index = 0; index <= 7; index++) { 14482 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QGROUPr, 14483 port, index, &rval); 14484 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, &rval, 14485 PKTSETLIMITf, 14486 numxqs_per_downlink_ports_and_cpu_port - 1); 14487 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, 14488 port, index, rval); 14489 } 14490 14491 /* HOLCOSPKTRESETLIMIT_QGROUPr, index 0 ~ 7 */ 14492 for (index = 0; index <= 7; index++) { 14493 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 14494 port, index, &rval); 14495 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, &rval, 14496 PKTRESETLIMITf, 14497 holcospktsetlimit_qgroup0_pktsetlimit_down_2dot5 - 14498 1); 14499 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 14500 port, index, rval); 14501 } 14502 14503 /* CNGCOSPKTLIMIT0_QGROUPr, index 0 ~ 7 */ 14504 for (index = 0; index <= 7; index++) { 14505 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QGROUPr, 14506 port, index, &rval); 14507 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QGROUPr, &rval, 14508 CNGPKTSETLIMIT0f, 14509 numxqs_per_downlink_ports_and_cpu_port - 1); 14510 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QGROUPr, 14511 port, index, rval); 14512 } 14513 14514 /* CNGCOSPKTLIMIT1_QGROUPr, index 0 ~ 7 */ 14515 for (index = 0; index <= 7; index++) { 14516 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QGROUPr, 14517 port, index, &rval); 14518 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QGROUPr, &rval, 14519 CNGPKTSETLIMIT1f, 14520 numxqs_per_downlink_ports_and_cpu_port - 1); 14521 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QGROUPr, 14522 port, index, rval); 14523 } 14524 14525 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 14526 for (index = 0; index <= 7; index++) { 14527 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 14528 port, index, &rval); 14529 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 14530 CELLMAXLIMITf, 14531 ceiling_func(total_advertised_cell_memory, 14532 queue_port_limit_ratio)); 14533 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 14534 port, index, rval); 14535 } 14536 14537 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 14538 for (index = 0; index <= 7; index++) { 14539 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 14540 port, index, &rval); 14541 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 14542 CELLMAXRESUMELIMITf, 14543 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_2dot5 - 14544 ethernet_mtu_cell); 14545 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 14546 port, index, rval); 14547 } 14548 14549 /* COLOR_DROP_EN_QGROUPr, index 0 */ 14550 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 14551 port, 0, &rval); 14552 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 14553 COLOR_DROP_ENf, 14554 0); 14555 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 14556 port, 0, rval); 14557 14558 /* SHARED_POOL_CTRLr, index 0 */ 14559 soc_reg32_get(unit, SHARED_POOL_CTRLr, 14560 port, 0, &rval); 14561 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 14562 DYNAMIC_COS_DROP_ENf, 14563 255); 14564 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 14565 SHARED_POOL_DISCARD_ENf, 14566 127); 14567 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 14568 SHARED_POOL_XOFF_ENf, 14569 0); 14570 soc_reg32_set(unit, SHARED_POOL_CTRLr, 14571 port, 0, rval); 14572 14573 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 14574 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 14575 port, 0, &rval); 14576 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 14577 DYNAMIC_COS_DROP_ENf, 14578 0xFFFFFF); 14579 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 14580 port, 0, rval); 14581 14582 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 14583 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 14584 port, 0, &rval); 14585 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 14586 DYNAMIC_COS_DROP_ENf, 14587 0xFFFFFFFF); 14588 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 14589 port, 0, rval); 14590 14591 } 14592 14593 /* port-based : downlink 10G */ 14594 SOC_PBMP_ITER(pbmp_downlink_10g, port) { 14595 /* PG_CTRL0r, index 0 */ 14596 soc_reg32_get(unit, PG_CTRL0r, 14597 port, 0, &rval); 14598 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14599 PPFC_PG_ENf, 14600 128); 14601 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14602 PRI0_GRPf, 14603 /* coverity[dead_error_line : FALSE] */ 14604 flow_control_type_pause_0_pfc_1?0:7); 14605 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14606 PRI1_GRPf, 14607 /* coverity[dead_error_line : FALSE] */ 14608 flow_control_type_pause_0_pfc_1?1:7); 14609 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14610 PRI2_GRPf, 14611 /* coverity[dead_error_line : FALSE] */ 14612 flow_control_type_pause_0_pfc_1?2:7); 14613 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14614 PRI3_GRPf, 14615 /* coverity[dead_error_line : FALSE] */ 14616 flow_control_type_pause_0_pfc_1?3:7); 14617 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14618 PRI4_GRPf, 14619 /* coverity[dead_error_line : FALSE] */ 14620 flow_control_type_pause_0_pfc_1?4:7); 14621 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14622 PRI5_GRPf, 14623 /* coverity[dead_error_line : FALSE] */ 14624 flow_control_type_pause_0_pfc_1?5:7); 14625 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14626 PRI6_GRPf, 14627 /* coverity[dead_error_line : FALSE] */ 14628 flow_control_type_pause_0_pfc_1?6:7); 14629 soc_reg_field_set(unit, PG_CTRL0r, &rval, 14630 PRI7_GRPf, 14631 /* coverity[identical_branches : FALSE] */ 14632 flow_control_type_pause_0_pfc_1?7:7); 14633 soc_reg32_set(unit, PG_CTRL0r, 14634 port, 0, rval); 14635 14636 /* PG_CTRL1r, index 0 */ 14637 soc_reg32_get(unit, PG_CTRL1r, 14638 port, 0, &rval); 14639 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14640 PRI8_GRPf, 14641 /* coverity[identical_branches : FALSE] */ 14642 flow_control_type_pause_0_pfc_1?7:7); 14643 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14644 PRI9_GRPf, 14645 /* coverity[identical_branches : FALSE] */ 14646 flow_control_type_pause_0_pfc_1?7:7); 14647 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14648 PRI10_GRPf, 14649 /* coverity[identical_branches : FALSE] */ 14650 flow_control_type_pause_0_pfc_1?7:7); 14651 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14652 PRI11_GRPf, 14653 /* coverity[identical_branches : FALSE] */ 14654 flow_control_type_pause_0_pfc_1?7:7); 14655 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14656 PRI12_GRPf, 14657 /* coverity[identical_branches : FALSE] */ 14658 flow_control_type_pause_0_pfc_1?7:7); 14659 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14660 PRI13_GRPf, 14661 /* coverity[identical_branches : FALSE] */ 14662 flow_control_type_pause_0_pfc_1?7:7); 14663 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14664 PRI14_GRPf, 14665 /* coverity[identical_branches : FALSE] */ 14666 flow_control_type_pause_0_pfc_1?7:7); 14667 soc_reg_field_set(unit, PG_CTRL1r, &rval, 14668 PRI15_GRPf, 14669 /* coverity[identical_branches : FALSE] */ 14670 flow_control_type_pause_0_pfc_1?7:7); 14671 soc_reg32_set(unit, PG_CTRL1r, 14672 port, 0, rval); 14673 14674 /* PG2TCr, index 0 ~ 6 */ 14675 for (index = 0; index <= 6; index++) { 14676 soc_reg32_get(unit, PG2TCr, 14677 port, index, &rval); 14678 soc_reg_field_set(unit, PG2TCr, &rval, 14679 PG_BMPf, 14680 0); 14681 soc_reg32_set(unit, PG2TCr, 14682 port, index, rval); 14683 } 14684 14685 /* PG2TCr, index 7 */ 14686 soc_reg32_get(unit, PG2TCr, 14687 port, 7, &rval); 14688 soc_reg_field_set(unit, PG2TCr, &rval, 14689 PG_BMPf, 14690 /* coverity[dead_error_line : FALSE] */ 14691 flow_control_type_pause_0_pfc_1?128:255); 14692 soc_reg32_set(unit, PG2TCr, 14693 port, 7, rval); 14694 14695 /* IBPPKTSETLIMITr, index 0 */ 14696 soc_reg32_get(unit, IBPPKTSETLIMITr, 14697 port, 0, &rval); 14698 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 14699 PKTSETLIMITf, 14700 xoff_packet_thresholds_per_port_downlink_port); 14701 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 14702 RESETLIMITSELf, 14703 3); 14704 soc_reg32_set(unit, IBPPKTSETLIMITr, 14705 port, 0, rval); 14706 14707 /* MMU_FC_RX_ENr, index 0 */ 14708 soc_reg32_get(unit, MMU_FC_RX_ENr, 14709 port, 0, &rval); 14710 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 14711 MMU_FC_RX_ENABLEf, 14712 128); 14713 soc_reg32_set(unit, MMU_FC_RX_ENr, 14714 port, 0, rval); 14715 14716 /* MMU_FC_TX_ENr, index 0 */ 14717 soc_reg32_get(unit, MMU_FC_TX_ENr, 14718 port, 0, &rval); 14719 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 14720 MMU_FC_TX_ENABLEf, 14721 128); 14722 soc_reg32_set(unit, MMU_FC_TX_ENr, 14723 port, 0, rval); 14724 14725 /* PGCELLLIMITr, index 0 ~ 6 */ 14726 for (index = 0; index <= 6; index++) { 14727 soc_reg32_get(unit, PGCELLLIMITr, 14728 port, index, &rval); 14729 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 14730 CELLSETLIMITf, 14731 xoff_cell_threshold_all_uplink_ports); 14732 soc_reg32_set(unit, PGCELLLIMITr, 14733 port, index, rval); 14734 } 14735 14736 /* PGCELLLIMITr, index 7 */ 14737 soc_reg32_get(unit, PGCELLLIMITr, 14738 port, 7, &rval); 14739 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 14740 CELLSETLIMITf, 14741 xoff_cell_thresholds_per_port_10g_port_downlink_ports); 14742 soc_reg32_set(unit, PGCELLLIMITr, 14743 port, 7, rval); 14744 14745 /* PGCELLLIMITr, index 0 ~ 6 */ 14746 for (index = 0; index <= 6; index++) { 14747 soc_reg32_get(unit, PGCELLLIMITr, 14748 port, index, &rval); 14749 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 14750 CELLRESETLIMITf, 14751 xoff_cell_threshold_all_uplink_ports); 14752 soc_reg32_set(unit, PGCELLLIMITr, 14753 port, index, rval); 14754 } 14755 14756 /* PGCELLLIMITr, index 7 */ 14757 soc_reg32_get(unit, PGCELLLIMITr, 14758 port, 7, &rval); 14759 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 14760 CELLRESETLIMITf, 14761 xoff_cell_thresholds_per_port_10g_port_downlink_ports); 14762 soc_reg32_set(unit, PGCELLLIMITr, 14763 port, 7, rval); 14764 14765 /* PGDISCARDSETLIMITr, index 0 ~ 6 */ 14766 for (index = 0; index <= 6; index++) { 14767 soc_reg32_get(unit, PGDISCARDSETLIMITr, 14768 port, index, &rval); 14769 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 14770 DISCARDSETLIMITf, 14771 discard_limit_per_port_pg_downlink_port); 14772 soc_reg32_set(unit, PGDISCARDSETLIMITr, 14773 port, index, rval); 14774 } 14775 14776 /* PGDISCARDSETLIMITr, index 7 */ 14777 soc_reg32_get(unit, PGDISCARDSETLIMITr, 14778 port, 7, &rval); 14779 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 14780 DISCARDSETLIMITf, 14781 discard_limit_per_port_pg_uplink_10g_port); 14782 soc_reg32_set(unit, PGDISCARDSETLIMITr, 14783 port, 7, rval); 14784 14785 /* HOLCOSMINXQCNTr, index 0 ~ 6 */ 14786 for (index = 0; index <= 6; index++) { 14787 soc_reg32_get(unit, HOLCOSMINXQCNTr, 14788 port, index, &rval); 14789 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 14790 HOLCOSMINXQCNTf, 14791 egress_xq_min_reserve_lossy_ports); 14792 soc_reg32_set(unit, HOLCOSMINXQCNTr, 14793 port, index, rval); 14794 } 14795 14796 /* HOLCOSMINXQCNTr, index 7 */ 14797 soc_reg32_get(unit, HOLCOSMINXQCNTr, 14798 port, 7, &rval); 14799 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 14800 HOLCOSMINXQCNTf, 14801 egress_xq_min_reserve_lossless_downlink_ports); 14802 soc_reg32_set(unit, HOLCOSMINXQCNTr, 14803 port, 7, rval); 14804 14805 /* HOLCOSMINXQCNT_QLAYERr, index 0 ~ 6 */ 14806 for (index = 0; index <= 6; index++) { 14807 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 14808 port, index, &rval); 14809 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 14810 HOLCOSMINXQCNTf, 14811 egress_xq_min_reserve_lossy_ports); 14812 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 14813 port, index, rval); 14814 } 14815 14816 /* HOLCOSMINXQCNT_QLAYERr, index 7 */ 14817 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 14818 port, 7, &rval); 14819 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 14820 HOLCOSMINXQCNTf, 14821 egress_xq_min_reserve_lossless_downlink_ports); 14822 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 14823 port, 7, rval); 14824 14825 /* HOLCOSMINXQCNT_QLAYERr, index 8 ~ 63 */ 14826 for (index = 8; index <= 63; index++) { 14827 soc_reg32_get(unit, HOLCOSMINXQCNT_QLAYERr, 14828 port, index, &rval); 14829 soc_reg_field_set(unit, HOLCOSMINXQCNT_QLAYERr, &rval, 14830 HOLCOSMINXQCNTf, 14831 0); 14832 soc_reg32_set(unit, HOLCOSMINXQCNT_QLAYERr, 14833 port, index, rval); 14834 } 14835 14836 /* HOLCOSPKTSETLIMITr, index 0 ~ 6 */ 14837 for (index = 0; index <= 6; index++) { 14838 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 14839 port, index, &rval); 14840 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 14841 PKTSETLIMITf, 14842 shared_xqs_per_downlink_port + 14843 egress_xq_min_reserve_lossy_ports); 14844 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 14845 port, index, rval); 14846 } 14847 14848 /* HOLCOSPKTSETLIMITr, index 7 */ 14849 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 14850 port, 7, &rval); 14851 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 14852 PKTSETLIMITf, 14853 shared_xqs_per_downlink_port + 14854 egress_xq_min_reserve_lossless_downlink_ports); 14855 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 14856 port, 7, rval); 14857 14858 /* HOLCOSPKTSETLIMIT_QLAYERr, index 0 ~ 6 */ 14859 for (index = 0; index <= 6; index++) { 14860 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14861 port, index, &rval); 14862 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 14863 PKTSETLIMITf, 14864 shared_xqs_per_downlink_port + 14865 egress_xq_min_reserve_lossy_ports); 14866 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14867 port, index, rval); 14868 } 14869 14870 /* HOLCOSPKTSETLIMIT_QLAYERr, index 7 */ 14871 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14872 port, 7, &rval); 14873 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 14874 PKTSETLIMITf, 14875 shared_xqs_per_downlink_port + 14876 egress_xq_min_reserve_lossless_downlink_ports); 14877 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14878 port, 7, rval); 14879 14880 /* HOLCOSPKTSETLIMIT_QLAYERr, index 8 ~ 63 */ 14881 for (index = 8; index <= 63; index++) { 14882 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14883 port, index, &rval); 14884 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, &rval, 14885 PKTSETLIMITf, 14886 shared_xqs_per_downlink_port + 14887 holcosminxqcnt_qlayer8_holcosminxqcnt_down_10); 14888 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QLAYERr, 14889 port, index, rval); 14890 } 14891 14892 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 14893 for (index = 0; index <= 6; index++) { 14894 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 14895 port, index, &rval); 14896 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 14897 PKTRESETLIMITf, 14898 holcospktsetlimit0_pktsetlimit_down_10 - 1); 14899 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 14900 port, index, rval); 14901 } 14902 14903 /* HOLCOSPKTRESETLIMITr, index 7 */ 14904 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 14905 port, 7, &rval); 14906 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 14907 PKTRESETLIMITf, 14908 holcospktsetlimit7_pktsetlimit_down_10 - 1); 14909 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 14910 port, 7, rval); 14911 14912 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 0 ~ 6 */ 14913 for (index = 0; index <= 6; index++) { 14914 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14915 port, index, &rval); 14916 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 14917 PKTRESETLIMITf, 14918 holcospktsetlimit_qlayer0_pktsetlimit_down_10 - 1); 14919 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14920 port, index, rval); 14921 } 14922 14923 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 7 */ 14924 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14925 port, 7, &rval); 14926 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 14927 PKTRESETLIMITf, 14928 holcospktsetlimit_qlayer7_pktsetlimit_down_10 - 1); 14929 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14930 port, 7, rval); 14931 14932 /* HOLCOSPKTRESETLIMIT_QLAYERr, index 8 ~ 63 */ 14933 for (index = 8; index <= 63; index++) { 14934 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14935 port, index, &rval); 14936 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, &rval, 14937 PKTRESETLIMITf, 14938 holcospktsetlimit_qlayer8_pktsetlimit_down_10 - 1); 14939 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QLAYERr, 14940 port, index, rval); 14941 } 14942 14943 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 14944 for (index = 0; index <= 7; index++) { 14945 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 14946 port, index, &rval); 14947 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 14948 CNGPKTSETLIMIT0f, 14949 numxqs_per_downlink_ports_and_cpu_port - 1); 14950 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 14951 port, index, rval); 14952 } 14953 14954 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 14955 for (index = 0; index <= 7; index++) { 14956 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 14957 port, index, &rval); 14958 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 14959 CNGPKTSETLIMIT1f, 14960 numxqs_per_downlink_ports_and_cpu_port - 1); 14961 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 14962 port, index, rval); 14963 } 14964 14965 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 14966 for (index = 0; index <= 63; index++) { 14967 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 14968 port, index, &rval); 14969 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 14970 CNGPKTSETLIMIT0f, 14971 numxqs_per_downlink_ports_and_cpu_port - 1); 14972 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 14973 port, index, rval); 14974 } 14975 14976 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 14977 for (index = 0; index <= 63; index++) { 14978 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 14979 port, index, &rval); 14980 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 14981 CNGPKTSETLIMIT1f, 14982 numxqs_per_downlink_ports_and_cpu_port - 1); 14983 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 14984 port, index, rval); 14985 } 14986 14987 /* CNGPORTPKTLIMIT0r, index 0 */ 14988 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 14989 port, 0, &rval); 14990 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 14991 CNGPORTPKTLIMIT0f, 14992 numxqs_per_downlink_ports_and_cpu_port - 1); 14993 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 14994 port, 0, rval); 14995 14996 /* CNGPORTPKTLIMIT1r, index 0 */ 14997 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 14998 port, 0, &rval); 14999 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 15000 CNGPORTPKTLIMIT1f, 15001 numxqs_per_downlink_ports_and_cpu_port - 1); 15002 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 15003 port, 0, rval); 15004 15005 /* DYNXQCNTPORTr, index 0 */ 15006 soc_reg32_get(unit, DYNXQCNTPORTr, 15007 port, 0, &rval); 15008 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 15009 DYNXQCNTPORTf, 15010 shared_xqs_per_downlink_port - skidmarker - prefetch); 15011 soc_reg32_set(unit, DYNXQCNTPORTr, 15012 port, 0, rval); 15013 15014 /* DYNRESETLIMPORTr, index 0 */ 15015 soc_reg32_get(unit, DYNRESETLIMPORTr, 15016 port, 0, &rval); 15017 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 15018 DYNRESETLIMPORTf, 15019 dynxqcntport_dynxqcntport_down_10 - 2); 15020 soc_reg32_set(unit, DYNRESETLIMPORTr, 15021 port, 0, rval); 15022 15023 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 15024 for (index = 0; index <= 6; index++) { 15025 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 15026 port, index, &rval); 15027 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 15028 CELLSETLIMITf, 15029 egress_queue_min_reserve_downlink_ports_lossy); 15030 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 15031 port, index, rval); 15032 } 15033 15034 /* LWMCOSCELLSETLIMITr, index 7 */ 15035 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 15036 port, 7, &rval); 15037 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 15038 CELLSETLIMITf, 15039 egress_queue_min_reserve_downlink_ports_lossless); 15040 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 15041 port, 7, rval); 15042 15043 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 15044 for (index = 0; index <= 6; index++) { 15045 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15046 port, index, &rval); 15047 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 15048 CELLSETLIMITf, 15049 egress_queue_min_reserve_downlink_ports_lossy); 15050 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15051 port, index, rval); 15052 } 15053 15054 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 15055 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15056 port, 7, &rval); 15057 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 15058 CELLSETLIMITf, 15059 egress_queue_min_reserve_downlink_ports_lossless); 15060 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15061 port, 7, rval); 15062 15063 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 15064 for (index = 8; index <= 63; index++) { 15065 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15066 port, index, &rval); 15067 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 15068 CELLSETLIMITf, 15069 0); 15070 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15071 port, index, rval); 15072 } 15073 15074 /* LWMCOSCELLSETLIMITr, index 0 ~ 6 */ 15075 for (index = 0; index <= 6; index++) { 15076 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 15077 port, index, &rval); 15078 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 15079 CELLRESETLIMITf, 15080 egress_queue_min_reserve_downlink_ports_lossy); 15081 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 15082 port, index, rval); 15083 } 15084 15085 /* LWMCOSCELLSETLIMITr, index 7 */ 15086 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 15087 port, 7, &rval); 15088 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 15089 CELLRESETLIMITf, 15090 egress_queue_min_reserve_downlink_ports_lossless); 15091 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 15092 port, 7, rval); 15093 15094 /* LWMCOSCELLSETLIMIT_QLAYERr, index 0 ~ 6 */ 15095 for (index = 0; index <= 6; index++) { 15096 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15097 port, index, &rval); 15098 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 15099 CELLRESETLIMITf, 15100 egress_queue_min_reserve_downlink_ports_lossy); 15101 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15102 port, index, rval); 15103 } 15104 15105 /* LWMCOSCELLSETLIMIT_QLAYERr, index 7 */ 15106 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15107 port, 7, &rval); 15108 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 15109 CELLRESETLIMITf, 15110 egress_queue_min_reserve_downlink_ports_lossless); 15111 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15112 port, 7, rval); 15113 15114 /* LWMCOSCELLSETLIMIT_QLAYERr, index 8 ~ 63 */ 15115 for (index = 8; index <= 63; index++) { 15116 soc_reg32_get(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15117 port, index, &rval); 15118 soc_reg_field_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, &rval, 15119 CELLRESETLIMITf, 15120 0); 15121 soc_reg32_set(unit, LWMCOSCELLSETLIMIT_QLAYERr, 15122 port, index, rval); 15123 } 15124 15125 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 15126 for (index = 0; index <= 6; index++) { 15127 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15128 port, index, &rval); 15129 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15130 CELLMAXLIMITf, 15131 ceiling_func(shared_space_cells, 15132 queue_port_limit_ratio) + 15133 lwmcoscellsetlimit0_cellsetlimit_down_10); 15134 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15135 port, index, rval); 15136 } 15137 15138 /* HOLCOSCELLMAXLIMITr, index 7 */ 15139 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15140 port, 7, &rval); 15141 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15142 CELLMAXLIMITf, 15143 ceiling_func(shared_space_cells, 15144 queue_port_limit_ratio) + 15145 lwmcoscellsetlimit7_cellsetlimit_down_10); 15146 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15147 port, 7, rval); 15148 15149 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 15150 for (index = 0; index <= 6; index++) { 15151 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15152 port, index, &rval); 15153 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 15154 CELLMAXLIMITf, 15155 ceiling_func(shared_space_cells, 15156 queue_port_limit_ratio) + 15157 lwmcoscellsetlimit_qlayer0_cellsetlimit_down_10); 15158 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15159 port, index, rval); 15160 } 15161 15162 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 15163 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15164 port, 7, &rval); 15165 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 15166 CELLMAXLIMITf, 15167 ceiling_func(shared_space_cells, 15168 queue_port_limit_ratio) + 15169 lwmcoscellsetlimit_qlayer7_cellsetlimit_down_10); 15170 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15171 port, 7, rval); 15172 15173 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 15174 for (index = 8; index <= 63; index++) { 15175 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15176 port, index, &rval); 15177 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 15178 CELLMAXLIMITf, 15179 ceiling_func(shared_space_cells, 15180 queue_port_limit_ratio) + 15181 lwmcoscellsetlimit_qlayer8_cellsetlimit_down_10); 15182 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15183 port, index, rval); 15184 } 15185 15186 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 15187 for (index = 0; index <= 6; index++) { 15188 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15189 port, index, &rval); 15190 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15191 CELLMAXRESUMELIMITf, 15192 holcoscellmaxlimit0_cellmaxlimit_down_10 - 15193 ethernet_mtu_cell); 15194 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15195 port, index, rval); 15196 } 15197 15198 /* HOLCOSCELLMAXLIMITr, index 7 */ 15199 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15200 port, 7, &rval); 15201 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15202 CELLMAXRESUMELIMITf, 15203 holcoscellmaxlimit7_cellmaxlimit_down_10 - 15204 ethernet_mtu_cell); 15205 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15206 port, 7, rval); 15207 15208 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 0 ~ 6 */ 15209 for (index = 0; index <= 6; index++) { 15210 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15211 port, index, &rval); 15212 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 15213 CELLMAXRESUMELIMITf, 15214 holcoscellmaxlimit_qlayer0_cellmaxlimit_down_10 - 15215 ethernet_mtu_cell); 15216 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15217 port, index, rval); 15218 } 15219 15220 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 7 */ 15221 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15222 port, 7, &rval); 15223 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 15224 CELLMAXRESUMELIMITf, 15225 holcoscellmaxlimit_qlayer7_cellmaxlimit_down_10 - 15226 ethernet_mtu_cell); 15227 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15228 port, 7, rval); 15229 15230 /* HOLCOSCELLMAXLIMIT_QLAYERr, index 8 ~ 63 */ 15231 for (index = 8; index <= 63; index++) { 15232 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15233 port, index, &rval); 15234 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, &rval, 15235 CELLMAXRESUMELIMITf, 15236 holcoscellmaxlimit_qlayer8_cellmaxlimit_down_10 - 15237 ethernet_mtu_cell); 15238 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QLAYERr, 15239 port, index, rval); 15240 } 15241 15242 /* DYNCELLLIMITr, index 0 */ 15243 soc_reg32_get(unit, DYNCELLLIMITr, 15244 port, 0, &rval); 15245 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 15246 DYNCELLSETLIMITf, 15247 shared_space_cells); 15248 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 15249 DYNCELLRESETLIMITf, 15250 dyncelllimit_dyncellsetlimit_down_10 - 15251 (ethernet_mtu_cell * 2)); 15252 soc_reg32_set(unit, DYNCELLLIMITr, 15253 port, 0, rval); 15254 15255 /* COLOR_DROP_ENr, index 0 */ 15256 soc_reg32_get(unit, COLOR_DROP_ENr, 15257 port, 0, &rval); 15258 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 15259 COLOR_DROP_ENf, 15260 0); 15261 soc_reg32_set(unit, COLOR_DROP_ENr, 15262 port, 0, rval); 15263 15264 /* COLOR_DROP_EN_QLAYERr, index 0 */ 15265 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 15266 port, 0, &rval); 15267 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 15268 COLOR_DROP_ENf, 15269 0); 15270 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 15271 port, 0, rval); 15272 15273 /* HOLCOSPKTSETLIMIT_QGROUPr, index 0 ~ 7 */ 15274 for (index = 0; index <= 7; index++) { 15275 soc_reg32_get(unit, HOLCOSPKTSETLIMIT_QGROUPr, 15276 port, index, &rval); 15277 soc_reg_field_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, &rval, 15278 PKTSETLIMITf, 15279 numxqs_per_downlink_ports_and_cpu_port - 1); 15280 soc_reg32_set(unit, HOLCOSPKTSETLIMIT_QGROUPr, 15281 port, index, rval); 15282 } 15283 15284 /* HOLCOSPKTRESETLIMIT_QGROUPr, index 0 ~ 7 */ 15285 for (index = 0; index <= 7; index++) { 15286 soc_reg32_get(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 15287 port, index, &rval); 15288 soc_reg_field_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, &rval, 15289 PKTRESETLIMITf, 15290 holcospktsetlimit_qgroup0_pktsetlimit_down_10 - 1); 15291 soc_reg32_set(unit, HOLCOSPKTRESETLIMIT_QGROUPr, 15292 port, index, rval); 15293 } 15294 15295 /* CNGCOSPKTLIMIT0_QGROUPr, index 0 ~ 7 */ 15296 for (index = 0; index <= 7; index++) { 15297 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QGROUPr, 15298 port, index, &rval); 15299 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QGROUPr, &rval, 15300 CNGPKTSETLIMIT0f, 15301 numxqs_per_downlink_ports_and_cpu_port - 1); 15302 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QGROUPr, 15303 port, index, rval); 15304 } 15305 15306 /* CNGCOSPKTLIMIT1_QGROUPr, index 0 ~ 7 */ 15307 for (index = 0; index <= 7; index++) { 15308 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QGROUPr, 15309 port, index, &rval); 15310 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QGROUPr, &rval, 15311 CNGPKTSETLIMIT1f, 15312 numxqs_per_downlink_ports_and_cpu_port - 1); 15313 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QGROUPr, 15314 port, index, rval); 15315 } 15316 15317 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 15318 for (index = 0; index <= 7; index++) { 15319 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 15320 port, index, &rval); 15321 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 15322 CELLMAXLIMITf, 15323 ceiling_func(total_advertised_cell_memory, 15324 queue_port_limit_ratio)); 15325 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 15326 port, index, rval); 15327 } 15328 15329 /* HOLCOSCELLMAXLIMIT_QGROUPr, index 0 ~ 7 */ 15330 for (index = 0; index <= 7; index++) { 15331 soc_reg32_get(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 15332 port, index, &rval); 15333 soc_reg_field_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, &rval, 15334 CELLMAXRESUMELIMITf, 15335 holcoscellmaxlimit_qgroup0_cellmaxlimit_down_10 - 15336 ethernet_mtu_cell); 15337 soc_reg32_set(unit, HOLCOSCELLMAXLIMIT_QGROUPr, 15338 port, index, rval); 15339 } 15340 15341 /* COLOR_DROP_EN_QGROUPr, index 0 */ 15342 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 15343 port, 0, &rval); 15344 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 15345 COLOR_DROP_ENf, 15346 0); 15347 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 15348 port, 0, rval); 15349 15350 /* SHARED_POOL_CTRLr, index 0 */ 15351 soc_reg32_get(unit, SHARED_POOL_CTRLr, 15352 port, 0, &rval); 15353 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 15354 DYNAMIC_COS_DROP_ENf, 15355 255); 15356 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 15357 SHARED_POOL_DISCARD_ENf, 15358 127); 15359 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 15360 SHARED_POOL_XOFF_ENf, 15361 0); 15362 soc_reg32_set(unit, SHARED_POOL_CTRLr, 15363 port, 0, rval); 15364 15365 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 15366 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 15367 port, 0, &rval); 15368 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 15369 DYNAMIC_COS_DROP_ENf, 15370 0xFFFFFF); 15371 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 15372 port, 0, rval); 15373 15374 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 15375 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 15376 port, 0, &rval); 15377 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 15378 DYNAMIC_COS_DROP_ENf, 15379 0xFFFFFFFF); 15380 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 15381 port, 0, rval); 15382 } 15383 15384 /* port-based : cpu port*/ 15385 SOC_PBMP_ITER(pbmp_cpu, port) { 15386 /* PG_CTRL0r, index 0 */ 15387 soc_reg32_get(unit, PG_CTRL0r, 15388 port, 0, &rval); 15389 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15390 PPFC_PG_ENf, 15391 0); 15392 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15393 PRI0_GRPf, 15394 0); 15395 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15396 PRI1_GRPf, 15397 1); 15398 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15399 PRI2_GRPf, 15400 2); 15401 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15402 PRI3_GRPf, 15403 3); 15404 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15405 PRI4_GRPf, 15406 4); 15407 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15408 PRI5_GRPf, 15409 5); 15410 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15411 PRI6_GRPf, 15412 6); 15413 soc_reg_field_set(unit, PG_CTRL0r, &rval, 15414 PRI7_GRPf, 15415 7); 15416 soc_reg32_set(unit, PG_CTRL0r, 15417 port, 0, rval); 15418 15419 /* PG_CTRL1r, index 0 */ 15420 soc_reg32_get(unit, PG_CTRL1r, 15421 port, 0, &rval); 15422 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15423 PRI8_GRPf, 15424 7); 15425 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15426 PRI9_GRPf, 15427 7); 15428 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15429 PRI10_GRPf, 15430 7); 15431 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15432 PRI11_GRPf, 15433 7); 15434 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15435 PRI12_GRPf, 15436 7); 15437 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15438 PRI13_GRPf, 15439 7); 15440 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15441 PRI14_GRPf, 15442 7); 15443 soc_reg_field_set(unit, PG_CTRL1r, &rval, 15444 PRI15_GRPf, 15445 7); 15446 soc_reg32_set(unit, PG_CTRL1r, 15447 port, 0, rval); 15448 15449 /* PG2TCr, index 0 ~ 7 */ 15450 for (index = 0; index <= 7; index++) { 15451 soc_reg32_get(unit, PG2TCr, 15452 port, index, &rval); 15453 soc_reg_field_set(unit, PG2TCr, &rval, 15454 PG_BMPf, 15455 0); 15456 soc_reg32_set(unit, PG2TCr, 15457 port, index, rval); 15458 } 15459 15460 /* IBPPKTSETLIMITr, index 0 */ 15461 soc_reg32_get(unit, IBPPKTSETLIMITr, 15462 port, 0, &rval); 15463 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 15464 PKTSETLIMITf, 15465 xoff_packet_thresholds_per_port_uplink_port); 15466 soc_reg_field_set(unit, IBPPKTSETLIMITr, &rval, 15467 RESETLIMITSELf, 15468 3); 15469 soc_reg32_set(unit, IBPPKTSETLIMITr, 15470 port, 0, rval); 15471 15472 /* MMU_FC_RX_ENr, index 0 */ 15473 soc_reg32_get(unit, MMU_FC_RX_ENr, 15474 port, 0, &rval); 15475 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, 15476 MMU_FC_RX_ENABLEf, 15477 0); 15478 soc_reg32_set(unit, MMU_FC_RX_ENr, 15479 port, 0, rval); 15480 15481 /* MMU_FC_TX_ENr, index 0 */ 15482 soc_reg32_get(unit, MMU_FC_TX_ENr, 15483 port, 0, &rval); 15484 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, 15485 MMU_FC_TX_ENABLEf, 15486 0); 15487 soc_reg32_set(unit, MMU_FC_TX_ENr, 15488 port, 0, rval); 15489 15490 /* PGCELLLIMITr, index 0 ~ 7 */ 15491 for (index = 0; index <= 7; index++) { 15492 soc_reg32_get(unit, PGCELLLIMITr, 15493 port, index, &rval); 15494 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 15495 CELLSETLIMITf, 15496 xoff_cell_threshold_all_uplink_ports); 15497 soc_reg32_set(unit, PGCELLLIMITr, 15498 port, index, rval); 15499 } 15500 15501 /* PGCELLLIMITr, index 0 ~ 7 */ 15502 for (index = 0; index <= 7; index++) { 15503 soc_reg32_get(unit, PGCELLLIMITr, 15504 port, index, &rval); 15505 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 15506 CELLRESETLIMITf, 15507 xoff_cell_threshold_all_uplink_ports); 15508 soc_reg32_set(unit, PGCELLLIMITr, 15509 port, index, rval); 15510 } 15511 15512 /* PGDISCARDSETLIMITr, index 0 ~ 7 */ 15513 for (index = 0; index <= 7; index++) { 15514 soc_reg32_get(unit, PGDISCARDSETLIMITr, 15515 port, index, &rval); 15516 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 15517 DISCARDSETLIMITf, 15518 discard_limit_per_port_pg_downlink_port); 15519 soc_reg32_set(unit, PGDISCARDSETLIMITr, 15520 port, index, rval); 15521 } 15522 15523 /* HOLCOSMINXQCNTr, index 0 ~ 7 */ 15524 for (index = 0; index <= 7; index++) { 15525 soc_reg32_get(unit, HOLCOSMINXQCNTr, 15526 port, index, &rval); 15527 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 15528 HOLCOSMINXQCNTf, 15529 egress_queue_min_reserve_cpu_ports); 15530 soc_reg32_set(unit, HOLCOSMINXQCNTr, 15531 port, index, rval); 15532 } 15533 15534 /* HOLCOSPKTSETLIMITr, index 0 ~ 6 */ 15535 for (index = 0; index <= 6; index++) { 15536 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 15537 port, index, &rval); 15538 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 15539 PKTSETLIMITf, 15540 shared_xqs_per_downlink_port + 15541 egress_xq_min_reserve_lossy_up_downlink_ports); 15542 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 15543 port, index, rval); 15544 } 15545 15546 /* HOLCOSPKTSETLIMITr, index 7 */ 15547 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 15548 port, 7, &rval); 15549 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 15550 PKTSETLIMITf, 15551 shared_xqs_per_downlink_port + 15552 egress_xq_min_reserve_lossless_downlink_ports); 15553 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 15554 port, 7, rval); 15555 15556 /* HOLCOSPKTRESETLIMITr, index 0 ~ 6 */ 15557 for (index = 0; index <= 6; index++) { 15558 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 15559 port, index, &rval); 15560 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 15561 PKTRESETLIMITf, 15562 holcospktsetlimit0_pktsetlimit_cpu - 1); 15563 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 15564 port, index, rval); 15565 } 15566 15567 /* HOLCOSPKTRESETLIMITr, index 7 */ 15568 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 15569 port, 7, &rval); 15570 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 15571 PKTRESETLIMITf, 15572 holcospktsetlimit7_pktsetlimit_cpu - 1); 15573 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 15574 port, 7, rval); 15575 15576 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 15577 for (index = 0; index <= 7; index++) { 15578 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 15579 port, index, &rval); 15580 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 15581 CNGPKTSETLIMIT0f, 15582 numxqs_per_downlink_ports_and_cpu_port - 1); 15583 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 15584 port, index, rval); 15585 } 15586 15587 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 15588 for (index = 0; index <= 7; index++) { 15589 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 15590 port, index, &rval); 15591 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 15592 CNGPKTSETLIMIT1f, 15593 numxqs_per_downlink_ports_and_cpu_port - 1); 15594 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 15595 port, index, rval); 15596 } 15597 15598 /* CNGCOSPKTLIMIT0_QLAYERr, index 0 ~ 63 */ 15599 for (index = 0; index <= 63; index++) { 15600 soc_reg32_get(unit, CNGCOSPKTLIMIT0_QLAYERr, 15601 port, index, &rval); 15602 soc_reg_field_set(unit, CNGCOSPKTLIMIT0_QLAYERr, &rval, 15603 CNGPKTSETLIMIT0f, 15604 numxqs_per_downlink_ports_and_cpu_port - 1); 15605 soc_reg32_set(unit, CNGCOSPKTLIMIT0_QLAYERr, 15606 port, index, rval); 15607 } 15608 15609 /* CNGCOSPKTLIMIT1_QLAYERr, index 0 ~ 63 */ 15610 for (index = 0; index <= 63; index++) { 15611 soc_reg32_get(unit, CNGCOSPKTLIMIT1_QLAYERr, 15612 port, index, &rval); 15613 soc_reg_field_set(unit, CNGCOSPKTLIMIT1_QLAYERr, &rval, 15614 CNGPKTSETLIMIT1f, 15615 numxqs_per_downlink_ports_and_cpu_port - 1); 15616 soc_reg32_set(unit, CNGCOSPKTLIMIT1_QLAYERr, 15617 port, index, rval); 15618 } 15619 15620 /* CNGPORTPKTLIMIT0r, index 0 */ 15621 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 15622 port, 0, &rval); 15623 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 15624 CNGPORTPKTLIMIT0f, 15625 numxqs_per_downlink_ports_and_cpu_port - 1); 15626 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 15627 port, 0, rval); 15628 15629 /* CNGPORTPKTLIMIT1r, index 0 */ 15630 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 15631 port, 0, &rval); 15632 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 15633 CNGPORTPKTLIMIT1f, 15634 numxqs_per_downlink_ports_and_cpu_port - 1); 15635 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 15636 port, 0, rval); 15637 15638 /* DYNXQCNTPORTr, index 0 */ 15639 soc_reg32_get(unit, DYNXQCNTPORTr, 15640 port, 0, &rval); 15641 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 15642 DYNXQCNTPORTf, 15643 shared_xqs_per_downlink_port - skidmarker - prefetch); 15644 soc_reg32_set(unit, DYNXQCNTPORTr, 15645 port, 0, rval); 15646 15647 /* DYNRESETLIMPORTr, index 0 */ 15648 soc_reg32_get(unit, DYNRESETLIMPORTr, 15649 port, 0, &rval); 15650 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 15651 DYNRESETLIMPORTf, 15652 dynxqcntport_dynxqcntport_cpu - 2); 15653 soc_reg32_set(unit, DYNRESETLIMPORTr, 15654 port, 0, rval); 15655 15656 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 15657 for (index = 0; index <= 7; index++) { 15658 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 15659 port, index, &rval); 15660 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 15661 CELLSETLIMITf, 15662 egress_queue_min_reserve_cpu_ports); 15663 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 15664 port, index, rval); 15665 } 15666 15667 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 15668 for (index = 0; index <= 7; index++) { 15669 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 15670 port, index, &rval); 15671 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 15672 CELLRESETLIMITf, 15673 egress_queue_min_reserve_cpu_ports); 15674 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 15675 port, index, rval); 15676 } 15677 15678 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 15679 for (index = 0; index <= 6; index++) { 15680 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15681 port, index, &rval); 15682 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15683 CELLMAXLIMITf, 15684 ceiling_func(shared_space_cells, 15685 queue_port_limit_ratio) + 15686 lwmcoscellsetlimit0_cellsetlimit_cpu); 15687 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15688 port, index, rval); 15689 } 15690 15691 /* HOLCOSCELLMAXLIMITr, index 7 */ 15692 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15693 port, 7, &rval); 15694 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15695 CELLMAXLIMITf, 15696 ceiling_func(shared_space_cells, 15697 queue_port_limit_ratio) + 15698 lwmcoscellsetlimit7_cellsetlimit_cpu); 15699 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15700 port, 7, rval); 15701 15702 /* HOLCOSCELLMAXLIMITr, index 0 ~ 6 */ 15703 for (index = 0; index <= 6; index++) { 15704 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15705 port, index, &rval); 15706 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15707 CELLMAXRESUMELIMITf, 15708 holcoscellmaxlimit0_cellmaxlimit_cpu - 15709 ethernet_mtu_cell); 15710 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15711 port, index, rval); 15712 } 15713 15714 /* HOLCOSCELLMAXLIMITr, index 7 */ 15715 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 15716 port, 7, &rval); 15717 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 15718 CELLMAXRESUMELIMITf, 15719 holcoscellmaxlimit7_cellmaxlimit_cpu - 15720 ethernet_mtu_cell); 15721 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 15722 port, 7, rval); 15723 15724 /* DYNCELLLIMITr, index 0 */ 15725 soc_reg32_get(unit, DYNCELLLIMITr, 15726 port, 0, &rval); 15727 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 15728 DYNCELLSETLIMITf, 15729 shared_space_cells); 15730 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 15731 DYNCELLRESETLIMITf, 15732 dyncelllimit_dyncellsetlimit_cpu - 15733 ethernet_mtu_cell * 2); 15734 soc_reg32_set(unit, DYNCELLLIMITr, 15735 port, 0, rval); 15736 15737 /* COLOR_DROP_ENr, index 0 */ 15738 soc_reg32_get(unit, COLOR_DROP_ENr, 15739 port, 0, &rval); 15740 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 15741 COLOR_DROP_ENf, 15742 0); 15743 soc_reg32_set(unit, COLOR_DROP_ENr, 15744 port, 0, rval); 15745 15746 /* COLOR_DROP_EN_QLAYERr, index 0 */ 15747 soc_reg32_get(unit, COLOR_DROP_EN_QLAYERr, 15748 port, 0, &rval); 15749 soc_reg_field_set(unit, COLOR_DROP_EN_QLAYERr, &rval, 15750 COLOR_DROP_ENf, 15751 0); 15752 soc_reg32_set(unit, COLOR_DROP_EN_QLAYERr, 15753 port, 0, rval); 15754 15755 /* COLOR_DROP_EN_QGROUPr, index 0 */ 15756 soc_reg32_get(unit, COLOR_DROP_EN_QGROUPr, 15757 port, 0, &rval); 15758 soc_reg_field_set(unit, COLOR_DROP_EN_QGROUPr, &rval, 15759 COLOR_DROP_ENf, 15760 0); 15761 soc_reg32_set(unit, COLOR_DROP_EN_QGROUPr, 15762 port, 0, rval); 15763 15764 /* SHARED_POOL_CTRLr, index 0 */ 15765 soc_reg32_get(unit, SHARED_POOL_CTRLr, 15766 port, 0, &rval); 15767 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 15768 DYNAMIC_COS_DROP_ENf, 15769 255); 15770 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 15771 SHARED_POOL_DISCARD_ENf, 15772 127); 15773 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 15774 SHARED_POOL_XOFF_ENf, 15775 0); 15776 soc_reg32_set(unit, SHARED_POOL_CTRLr, 15777 port, 0, rval); 15778 15779 /* SHARED_POOL_CTRL_EXT1r, index 0 */ 15780 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT1r, 15781 port, 0, &rval); 15782 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT1r, &rval, 15783 DYNAMIC_COS_DROP_ENf, 15784 0xFFFFFF); 15785 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT1r, 15786 port, 0, rval); 15787 15788 /* SHARED_POOL_CTRL_EXT2r, index 0 */ 15789 soc_reg32_get(unit, SHARED_POOL_CTRL_EXT2r, 15790 port, 0, &rval); 15791 soc_reg_field_set(unit, SHARED_POOL_CTRL_EXT2r, &rval, 15792 DYNAMIC_COS_DROP_ENf, 15793 0xFFFFFFFF); 15794 soc_reg32_set(unit, SHARED_POOL_CTRL_EXT2r, 15795 port, 0, rval); 15796 } 15797 15798 return SOC_E_NONE; 15799 } 15800 15801 15802 #define GH2_NUM_COS 8 15803 15804 15805 STATIC int 15806 _soc_greyhound2_mmu_init(int unit) 15807 { 15808 15809 { 15810 uint16 dev_id; 15811 uint8 rev_id; 15812 uint32 val, oval, cfap_max_idx; 15813 15814 soc_cm_get_id(unit, &dev_id, &rev_id); 15815 if ((dev_id & 0xF000) == 0x8000) { 15816 dev_id &= 0xFF0F; 15817 } 15818 SOC_IF_ERROR_RETURN(_soc_greyhound2_tdm_init(unit, dev_id)); 15819 15820 if (rev_id == BCM56170_B0_REV_ID) { 15821 cfap_max_idx = GH2_B0_MMU_CBP_FULL_SIZE; 15822 } else { 15823 cfap_max_idx = GH2_A0_MMU_CBP_FULL_SIZE; 15824 } 15825 SOC_IF_ERROR_RETURN(READ_CFAPCONFIGr(unit, &val)); 15826 oval = val; 15827 soc_reg_field_set(unit, CFAPCONFIGr, &val, CFAPPOOLSIZEf, cfap_max_idx); 15828 if (oval != val) { 15829 SOC_IF_ERROR_RETURN(WRITE_CFAPCONFIGr(unit, val)); 15830 } 15831 } 15832 15833 /* Enable IP to CMICM credit transfer */ 15834 { 15835 uint32 val; 15836 val = 0; 15837 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, 15838 &val, TRANSFER_ENABLEf, 1); 15839 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, 15840 &val, NUM_OF_CREDITSf, 32); 15841 SOC_IF_ERROR_RETURN(WRITE_IP_TO_CMICM_CREDIT_TRANSFERr(unit, val)); 15842 15843 if (soc_property_get(unit, spn_MMU_LOSSLESS, 0)) { 15844 SOC_IF_ERROR_RETURN(_soc_greyhound2_mmu_init_helper_lossless(unit)); 15845 } else { 15846 SOC_IF_ERROR_RETURN(_soc_greyhound2_mmu_init_helper_lossy(unit)); 15847 } 15848 /* Enable E2EFC in mmu block */ 15849 SOC_IF_ERROR_RETURN(READ_E2EFC_IBP_ENr(unit, &val)); 15850 soc_reg_field_set(unit, E2EFC_IBP_ENr, 15851 &val, SEND_RX_E2E_BKP_ENf, 1); 15852 soc_reg_field_set(unit, E2EFC_IBP_ENr, 15853 &val, ENf, 1); 15854 SOC_IF_ERROR_RETURN(WRITE_E2EFC_IBP_ENr(unit, val)); 15855 } 15856 15857 /* 15858 * Configure per-XQ packet aging for the various COSQs. 15859 * 15860 * The shortest age allowed by H/W is 250 microseconds. 15861 * The longest age allowed is 7.162 seconds (7162 msec). 15862 * The maximum ratio between the longest age and the shortest 15863 * (nonzero) age is 7:2. 15864 */ 15865 { 15866 int cos; 15867 int age[GH2_NUM_COS], max_age, min_age; 15868 int age_enable, disabled_age; 15869 int qgroup; 15870 15871 age_enable = disabled_age = max_age = 0; 15872 min_age = 7162; 15873 for (cos = 0; cos < NUM_COS(unit); cos++) { 15874 if ((age[cos] = 15875 soc_property_suffix_num_get(unit, cos, spn_MMU_XQ_AGING, 15876 "cos", 0)) > 0) { 15877 age_enable = 1; 15878 if (age[cos] > 7162) { 15879 age[cos] = 7162; 15880 } 15881 if (age[cos] < min_age) { 15882 min_age = age[cos]; 15883 } 15884 } else { 15885 disabled_age = 1; 15886 age[cos] = 0; 15887 } 15888 if (age[cos] > max_age) { 15889 max_age = age[cos]; 15890 } 15891 } 15892 if (!age_enable) { 15893 /* Disable packet aging on all COSQs */ 15894 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 0)); 15895 for (qgroup = 0; qgroup < 8; qgroup++) { 15896 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT_r(unit, qgroup, 0)); 15897 } 15898 } else { 15899 uint32 regval = 0; 15900 uint32 timerval; 15901 15902 /* Enforce the 7:2 ratio between min and max values */ 15903 if ((((max_age * 2) + 6) / 7) > min_age) { 15904 /* Keep requested max age; make min_age comply */ 15905 min_age = ((max_age * 2) + 6) / 7; 15906 } 15907 15908 /* 15909 * Give up granularity for range, if we need to 15910 * "disable" (max out) aging for any COSQ(s). 15911 */ 15912 if (disabled_age) { 15913 /* Max range */ 15914 max_age = min_age * 7 / 2; 15915 } 15916 15917 /* 15918 * Compute shortest duration of one PKTAGINGTIMERr cycle. 15919 * This duration is 1/7th of the longest packet age. 15920 * This duration is in units of 125 usec (msec * 8). 15921 */ 15922 timerval = ((8 * max_age) + 6) / 7; 15923 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, timerval)); 15924 15925 /* rPKTAGINGTIMER value 0 means aging disabled */ 15926 if (timerval != 0) { 15927 for (cos = 0; cos < NUM_COS(unit); cos++) { 15928 if (!age[cos]) { 15929 /* 15930 * Requested to be disabled, but cannot disable 15931 * individual COSQs once packet aging is enabled. 15932 * Therefore, mark this COSQ's aging duration as maxed 15933 * out. 15934 */ 15935 age[cos] = -1; 15936 } else if (age[cos] < min_age) { 15937 age[cos] = min_age; 15938 } 15939 15940 /* Normalize each "age" into # of PKTAGINGTIMERr cycles. */ 15941 if (age[cos] > 0) { 15942 age[cos] = ((8 * age[cos]) + timerval - 1) / timerval; 15943 } 15944 else { 15945 age[cos] = 7; 15946 } 15947 /* Format each "age" for its appropriate field */ 15948 regval |= ((7 - age[cos]) << (cos * 3)); 15949 } 15950 } else { 15951 regval = 0; 15952 } 15953 for (qgroup = 0; qgroup < 8; qgroup++) { 15954 SOC_IF_ERROR_RETURN 15955 (WRITE_PKTAGINGLIMIT_r(unit, qgroup, regval)); 15956 } 15957 } 15958 } 15959 15960 /* 15961 * MMU Port enable 15962 */ 15963 { 15964 soc_port_t port; 15965 pbmp_t mmu_pbmp; 15966 int phy_port; 15967 int mmu_port; 15968 soc_info_t *si = &SOC_INFO(unit); 15969 uint32 val; 15970 15971 SOC_PBMP_CLEAR(mmu_pbmp); 15972 PBMP_ALL_ITER(unit, port) { 15973 phy_port = si->port_l2p_mapping[port]; 15974 mmu_port = si->port_p2m_mapping[phy_port]; 15975 SOC_PBMP_PORT_ADD(mmu_pbmp, mmu_port); 15976 } 15977 val = 0; 15978 soc_reg_field_set(unit, MMUPORTENABLE_0r, &val, MMUPORTENABLEf, 15979 SOC_PBMP_WORD_GET(mmu_pbmp, 0)); 15980 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLE_0r(unit, val)); 15981 val = 0; 15982 soc_reg_field_set(unit, MMUPORTENABLE_1r, &val, MMUPORTENABLEf, 15983 SOC_PBMP_WORD_GET(mmu_pbmp, 1)); 15984 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLE_1r(unit, val)); 15985 val = 0; 15986 soc_reg_field_set(unit, MMUPORTENABLE_2r, &val, MMUPORTENABLEf, 15987 SOC_PBMP_WORD_GET(mmu_pbmp, 2)); 15988 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLE_2r(unit, val)); 15989 } 15990 15991 return SOC_E_NONE; 15992 } 15993 15994 /* soc_greyhound2_tsc_reset() 15995 * - to reset TSCE, TSCF and QTC on Greyhound2 15996 */ 15997 int 15998 soc_greyhound2_tsc_reset(int unit) 15999 { 16000 int blk, port; 16001 uint32 rval; 16002 16003 /* Reset SGMII4Px2 */ 16004 SOC_BLOCK_ITER(unit, blk, SOC_BLK_PMQ) { 16005 port = blk | SOC_REG_ADDR_BLOCK_ID_MASK; 16006 SOC_IF_ERROR_RETURN(soc_sgmii4px2_reset(unit, port, 0)); 16007 SOC_IF_ERROR_RETURN(soc_sgmii4px2_reset(unit, port, 1)); 16008 } 16009 16010 /* Reset QTC */ 16011 SOC_BLOCK_ITER(unit, blk, SOC_BLK_PMQ) { 16012 port = blk | SOC_REG_ADDR_BLOCK_ID_MASK; 16013 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, port, 0)); 16014 } 16015 16016 /* Reset TSCE */ 16017 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 16018 port = SOC_BLOCK_PORT(unit, blk); 16019 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, port, 0)); 16020 } 16021 16022 /* Reset TSCF */ 16023 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 16024 port = SOC_BLOCK_PORT(unit, blk); 16025 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, port, 0)); 16026 } 16027 16028 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 16029 port = SOC_BLOCK_PORT(unit, blk); 16030 if (port == -1 || port == REG_PORT_ANY) { 16031 continue; 16032 } 16033 SOC_IF_ERROR_RETURN(READ_XLPORT_MAC_CONTROLr(unit, port, &rval)); 16034 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 1); 16035 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 16036 sal_udelay(10); 16037 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 0); 16038 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 16039 } 16040 16041 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 16042 port = SOC_BLOCK_PORT(unit, blk); 16043 if (port == -1 || port == REG_PORT_ANY) { 16044 continue; 16045 } 16046 SOC_IF_ERROR_RETURN(READ_CLPORT_MAC_CONTROLr(unit, port, &rval)); 16047 soc_reg_field_set(unit, CLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 1); 16048 SOC_IF_ERROR_RETURN(WRITE_CLPORT_MAC_CONTROLr(unit, port, rval)); 16049 sal_udelay(10); 16050 soc_reg_field_set(unit, CLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 0); 16051 SOC_IF_ERROR_RETURN(WRITE_CLPORT_MAC_CONTROLr(unit, port, rval)); 16052 } 16053 16054 return SOC_E_NONE; 16055 } 16056 16057 extern int 16058 (*_phy_tsce_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *, int); 16059 extern int 16060 (*_phy_tscf_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *, int); 16061 extern int 16062 (*_phy_qtce_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *, int); 16063 16064 16065 STATIC int 16066 _soc_greyhound2_tscx_firmware_set(int unit, int port, uint8 *array, int datalen) 16067 { 16068 soc_mem_t mem = IS_CL_PORT(unit, port) ? CLPORT_WC_UCMEM_DATAm : 16069 (IS_XL_PORT(unit, port) ? XLPORT_WC_UCMEM_DATAm : 16070 GPORT_WC_UCMEM_DATAm); 16071 soc_reg_t reg = IS_CL_PORT(unit, port) ? CLPORT_WC_UCMEM_CTRLr : 16072 (IS_XL_PORT(unit, port) ? XLPORT_WC_UCMEM_CTRLr : 16073 GPORT_WC_UCMEM_CTRLr); 16074 16075 return soc_warpcore_firmware_set(unit, port, array, datalen, 0, mem, reg); 16076 } 16077 16078 #define INVALID_PPORT_ID -1 16079 /* 16080 * Func : _soc_greyhound2_mdio_addr_to_port 16081 * - To report pport_id from given phy_addr(for INT-PHY) 16082 * 16083 * INFO : 16084 * - This is HW dependent design in TOP Spec. 16085 * 1. Int-MDIO-Bus0 : SGMII4Px2_0 ~ SGMII4Px2_2 (each for 8 ports) 16086 * 2. Int-MDIO-Bus1 : TSCE0 ~ TSCE6 (each for 4 ports) 16087 * 3. Int-MDIO-Bus2 : QTC0 ~ QTC1 (each for 16 ports) 16088 * 4. Int-MDIO-Bus3 : TSCF (each for 4 ports) 16089 * - Param of "phy_addr" here has been constructed by phymod driver. 16090 */ 16091 STATIC int 16092 _soc_greyhound2_mdio_addr_to_port(uint32 phy_addr_int) 16093 { 16094 int bus, offset = 0; 16095 int mdio_addr; 16096 16097 /* Must be internal MDIO address */ 16098 if ((phy_addr_int & 0x80) == 0) { 16099 return INVALID_PPORT_ID; 16100 } 16101 16102 bus = PHY_ID_BUS_NUM(phy_addr_int); 16103 mdio_addr = phy_addr_int & 0x1f; 16104 16105 if (bus == 0) { 16106 /* for SGMII4Px2 */ 16107 if (mdio_addr <= 0x18) { 16108 offset = 1; 16109 } else { 16110 return INVALID_PPORT_ID; 16111 } 16112 } else if (bus == 1) { 16113 /* for TSCE */ 16114 if (mdio_addr <= 0x1c) { 16115 offset = 57; 16116 } else { 16117 return INVALID_PPORT_ID; 16118 } 16119 } else if (bus == 2) { 16120 if (mdio_addr <= 4) { 16121 /* for QTC0 */ 16122 offset = 25; 16123 } else if (mdio_addr <= 8) { 16124 /* for QTC1 */ 16125 offset = 37; 16126 } else { 16127 return INVALID_PPORT_ID; 16128 } 16129 } else if (bus == 3) { 16130 /* for TSCF */ 16131 if (mdio_addr <= 0x4) { 16132 offset = 85; 16133 } else { 16134 return INVALID_PPORT_ID; 16135 } 16136 } else { 16137 return INVALID_PPORT_ID; 16138 } 16139 16140 return mdio_addr + offset; 16141 } 16142 16143 /* 16144 * PHY_REG address decode for TSCx phy access : 16145 * - TSC_ADDR[31:0]={DEVICE(ADVAD)[31:27],??[26:24],TSC_ID(PHYAD)[23:19], 16146 * PORT_MODE(LANE)[18:16], IEEE_BIT[15], BLOCK[14:4], REG[3:0]} 16147 */ 16148 #define TSC_REG_ADDR_TSCID_SET(_phy_reg, _phyad) \ 16149 ((_phy_reg) |= ((_phyad) & 0x1f) << 19) 16150 16151 /* 16152 * GH2's PMQ block definition. 16153 * 1. PMQ0-PMQ2 : SGMII4Px2_0-SGMII4Px2_2 for pport2-pport25 16154 * >> Expected no SBUS-MDIO for SGMII4Px2 16155 * 2. PMQ3-PMQ4 for QTC0-QCT1 for pport26-pport57 16156 */ 16157 #define GH2_PMQ3_MIN_PPORT 26 16158 #define GH2_PMQ3_MAX_PPORT 41 16159 #define GH2_PMQ4_MIN_PPORT 42 16160 #define GH2_PMQ4_MAX_PPORT 57 16161 16162 /* 16163 * Func : soc_greyhound2_sbus_tsc_block() 16164 * - to report the valid blk of this port for wc_ucmem_data 16165 * (i.e. GPORT/XLPORT/CLPORT_WC_UCMEM_DATAm)access process. 16166 * 16167 * - Parameters : 16168 * phy_port(IN) : physical port. 16169 * blk(OUT) : the valid block 16170 * 16171 * INFO : 16172 * - PMQ block in GH2 are 16173 * 1. PMQ0-PMQ2 : SGMII4Px2_0-SGMII4Px2_2 for pport2-pport25 16174 * >> Expected no SBUS-MDIO for SGMII4Px2 16175 * 2. PMQ3-PMQ4 for QTC0-QCT1 for pport26-pport57 16176 */ 16177 int 16178 soc_greyhound2_sbus_tsc_block(int unit, int phy_port, int *blk) 16179 { 16180 soc_info_t *si = &SOC_INFO(unit); 16181 16182 *blk = -1; 16183 if (SOC_PORT_BLOCK_TYPE(unit, phy_port) == SOC_BLK_GPORT) { 16184 if ((phy_port >= GH2_PMQ3_MIN_PPORT) && 16185 (phy_port <= GH2_PMQ3_MAX_PPORT)) { 16186 *blk = si->pmq_block[3]; 16187 } else if ((phy_port >= GH2_PMQ4_MIN_PPORT) && 16188 (phy_port <= GH2_PMQ4_MAX_PPORT)) { 16189 *blk = si->pmq_block[4]; 16190 } else { 16191 /* 16192 * Port in GPORT block can be QTC port or SGMII port. 16193 * - Only QTC ports support SBus-MDIO 16194 * - SGMII4P ports return SOC_E_PORT due to no SBus-MDIO. 16195 */ 16196 LOG_INFO(BSL_LS_SOC_MII, (BSL_META_U(unit, 16197 "unit(%d),pport(%d) is unable for TSC SBus-MDIO!\n"), 16198 unit, phy_port)); 16199 return SOC_E_PORT; 16200 } 16201 } else { 16202 if ((SOC_PORT_BLOCK_TYPE(unit, phy_port) == SOC_BLK_XLPORT) || 16203 (SOC_PORT_BLOCK_TYPE(unit, phy_port) == SOC_BLK_CLPORT)) { 16204 /* for CL/XL port block */ 16205 *blk = SOC_PORT_BLOCK(unit, phy_port); 16206 } else { 16207 /* Unexpected port for SBus-MDIO */ 16208 LOG_WARN(BSL_LS_SOC_MII, (BSL_META_U(unit, 16209 "unit(%d),pport(%d) is unable for TSC SBus-MDIO!\n"), 16210 unit, phy_port)); 16211 return SOC_E_PORT; 16212 } 16213 } 16214 16215 return SOC_E_NONE; 16216 } 16217 16218 /* 16219 * Func : _soc_greyhound2_tscx_reg_read 16220 * - GH2 function to serve SBus MDIO read on TSCx 16221 */ 16222 STATIC int 16223 _soc_greyhound2_tscx_reg_read(int unit, uint32 phy_addr, 16224 uint32 phy_reg, uint32 *phy_data) 16225 { 16226 int rv, blk, port; 16227 int phy_port = _soc_greyhound2_mdio_addr_to_port(phy_addr); 16228 16229 if (phy_port == INVALID_PPORT_ID) { 16230 LOG_WARN(BSL_LS_SOC_MII, (BSL_META_U(unit, 16231 "unit%d: phy_addr=%d is unable for Sbus-MDIO read!\n"), 16232 unit, phy_addr)); 16233 return SOC_E_PARAM; 16234 } 16235 16236 port = SOC_INFO(unit).port_p2l_mapping[phy_port]; 16237 16238 SOC_IF_ERROR_RETURN 16239 (soc_greyhound2_sbus_tsc_block(unit, phy_port, &blk)); 16240 16241 LOG_INFO(BSL_LS_SOC_MII, (BSL_META_U(unit, 16242 "_soc_greyhound2_tscx_reg_read[%d]: %d/%d/%d/%d\n"), 16243 unit, phy_addr, phy_port, port, blk)); 16244 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 16245 rv = soc_sbus_tsc_reg_read(unit, port, blk, phy_addr, 16246 phy_reg, phy_data); 16247 16248 return rv; 16249 } 16250 16251 /* 16252 * Func : _soc_greyhound2_tscx_reg_read 16253 * - GH2 function to serve SBus MDIO read on TSCx 16254 */ 16255 STATIC int 16256 _soc_greyhound2_tscx_reg_write(int unit, uint32 phy_addr, 16257 uint32 phy_reg, uint32 phy_data) 16258 { 16259 int rv, blk, port; 16260 int phy_port = _soc_greyhound2_mdio_addr_to_port(phy_addr); 16261 16262 if (phy_port == INVALID_PPORT_ID) { 16263 LOG_WARN(BSL_LS_SOC_MII, (BSL_META_U(unit, 16264 "unit%d: phy_addr=%d is unable for Sbus-MDIO write!\n"), 16265 unit, phy_addr)); 16266 return SOC_E_PARAM; 16267 } 16268 16269 port = SOC_INFO(unit).port_p2l_mapping[phy_port]; 16270 16271 SOC_IF_ERROR_RETURN 16272 (soc_greyhound2_sbus_tsc_block(unit, phy_port, &blk)); 16273 16274 LOG_INFO(BSL_LS_SOC_MII, (BSL_META_U(unit, 16275 "_soc_greyhound2_tscx_reg_write[%d]: %d/%d/%d/%d\n"), 16276 unit, phy_addr, phy_port, port, blk)); 16277 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 16278 rv = soc_sbus_tsc_reg_write(unit, port, blk, phy_addr, 16279 phy_reg, phy_data); 16280 16281 return rv; 16282 } 16283 16284 /* 16285 * Func : soc_greyhound2_pgw_encap_field_get 16286 * - To write to PGW interface on GX/XL/CL port on indicated field 16287 */ 16288 int 16289 soc_greyhound2_pgw_encap_field_get(int unit, 16290 soc_port_t lport, 16291 soc_field_t field, 16292 uint32 *val) 16293 { 16294 uint32 reg_val = 0; 16295 int pport = SOC_INFO(unit).port_l2p_mapping[lport]; 16296 16297 *val = 0; 16298 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_XLPORT) { 16299 SOC_IF_ERROR_RETURN(READ_PGW_XL_CONFIGr(unit, lport, ®_val)); 16300 *val = soc_reg_field_get(unit, PGW_XL_CONFIGr, reg_val, field); 16301 } else if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_CLPORT) { 16302 SOC_IF_ERROR_RETURN(READ_PGW_CL_CONFIGr(unit, lport, ®_val)); 16303 *val = soc_reg_field_get(unit, PGW_CL_CONFIGr, reg_val, field); 16304 } else { 16305 SOC_IF_ERROR_RETURN(READ_PGW_GE_CONFIGr(unit, lport, ®_val)); 16306 *val = soc_reg_field_get(unit, PGW_GE_CONFIGr, reg_val, field); 16307 16308 } 16309 16310 return SOC_E_NONE; 16311 } 16312 16313 #define _GH2_PORTS_PER_CLBLK 4 16314 16315 #define GH2_FLOW_TYPE_SR 1 16316 #define GH2_FLOW_TYPE_TSN 2 16317 16318 STATIC int 16319 _soc_greyhound2_misc_init(int unit) 16320 { 16321 #define NUM_SUBPORT 4 /* number of subport of a XL or CL port */ 16322 static const soc_field_t port_field[] = { 16323 PORT0f, PORT1f, PORT2f, PORT3f 16324 }; 16325 uint32 rval, l2_ovf_enable, l2_tbl_size, fval; 16326 uint64 reg64; 16327 int port; 16328 uint32 entry[SOC_MAX_MEM_WORDS]; 16329 soc_field_t fields[3]; 16330 uint32 values[3]; 16331 int blk, bindex, mode; 16332 int phy_port_base; 16333 soc_info_t *si = &SOC_INFO(unit); 16334 int delay; 16335 int freq, target_freq, divisor, dividend; 16336 int index, count, sub_sel, offset; 16337 static int rtag7_field_width[] = { 16, 16, 4, 16, 8, 8, 16, 16 }; 16338 int port_count = 0; 16339 int i = 0; 16340 int flow_type; 16341 int parity_enable; 16342 char *board_name; 16343 16344 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 16345 /* Clear IPIPE/EIPIE Memories */ 16346 SOC_IF_ERROR_RETURN(soc_greyhound2_pipe_mem_clear(unit)); 16347 16348 /* CHECKME : GH2 needs the same programming as HR3 */ 16349 /* _soc_hurricane3_gport_tdm_mode_init(unit) */ 16350 16351 /* Clear MIB counter */ 16352 SOC_IF_ERROR_RETURN(soc_greyhound2_mib_reset(unit)); 16353 } 16354 16355 SOC_IF_ERROR_RETURN(soc_greyhound2_init_port_mapping(unit)); 16356 16357 soc_gh2_interrupt_init(unit); 16358 /* Do SER init and enable/disable parity according to config */ 16359 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 16360 16361 if (parity_enable) { 16362 SOC_IF_ERROR_RETURN(soc_gh2_tcam_ser_init(unit)); 16363 /* Enabling the packet drop when parity error occurred */ 16364 SOC_IF_ERROR_RETURN(READ_IPIPE_PERR_CONTROLr(unit, &rval)); 16365 fval = 1; 16366 soc_reg_field_set(unit, IPIPE_PERR_CONTROLr, &rval, DROPf, fval); 16367 SOC_IF_ERROR_RETURN(WRITE_IPIPE_PERR_CONTROLr(unit, rval)); 16368 SOC_IF_ERROR_RETURN(soc_gh2_ser_enable_all(unit, TRUE)); 16369 #if defined(SER_TR_TEST_SUPPORT) 16370 soc_gh2_ser_test_register(unit); 16371 #endif 16372 } else { 16373 SOC_IF_ERROR_RETURN(soc_gh2_ser_enable_all(unit, FALSE)); 16374 } 16375 16376 /* Enable L2 overflow bucket */ 16377 l2_tbl_size = soc_property_get(unit, spn_L2_TABLE_SIZE, 0); 16378 if (l2_tbl_size == (soc_mem_index_count(unit, L2Xm) + 16379 soc_mem_index_count(unit, L2_ENTRY_OVERFLOWm))) { 16380 /* 16381 * if l2 table size equals to l2 table size + l2 overflow table size, 16382 * it indicates the l2 overflow table is enabled. 16383 */ 16384 l2_ovf_enable = 1; 16385 } else { 16386 l2_ovf_enable = 0; 16387 } 16388 SOC_IF_ERROR_RETURN(READ_L2_LEARN_CONTROLr(unit, &rval)); 16389 soc_reg_field_set(unit, L2_LEARN_CONTROLr, &rval, 16390 OVERFLOW_BUCKET_ENABLEf, l2_ovf_enable); 16391 SOC_IF_ERROR_RETURN(WRITE_L2_LEARN_CONTROLr(unit, rval)); 16392 SOC_CONTROL_LOCK(unit); 16393 SOC_CONTROL(unit)->l2_overflow_bucket_enable = l2_ovf_enable; 16394 SOC_CONTROL_UNLOCK(unit); 16395 16396 /* Enable L2 overflow interrupt */ 16397 if (soc_property_get(unit, spn_L2_OVERFLOW_EVENT, FALSE)) { 16398 16399 SOC_CONTROL_LOCK(unit); 16400 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 16401 SOC_CONTROL_UNLOCK(unit); 16402 SOC_IF_ERROR_RETURN(soc_hr3_l2_overflow_start(unit)); 16403 /* Enable the l2 overflow interrupt */ 16404 soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_L2_OVERFLOW, 1); 16405 } else { 16406 SOC_CONTROL_LOCK(unit); 16407 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 16408 SOC_CONTROL_UNLOCK(unit); 16409 SOC_IF_ERROR_RETURN(soc_hr3_l2_overflow_stop(unit)); 16410 /* Disable the l2 overflow interrupt */ 16411 soc_gh2_cmic_interrupt_mask(unit, GH2_INTR_L2_OVERFLOW, 0); 16412 } 16413 16414 16415 /* GMAC init */ 16416 SOC_IF_ERROR_RETURN(soc_greyhound2_gmac_init(unit)); 16417 16418 /* HG init */ 16419 SOC_IF_ERROR_RETURN(soc_greyhound2_higig_mode_init(unit)); 16420 16421 /* XLPORT and CLPORT blocks init */ 16422 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 16423 port = SOC_BLOCK_PORT(unit, blk); 16424 if (port == -1 || port == REG_PORT_ANY) { 16425 continue; 16426 } 16427 phy_port_base = si->port_l2p_mapping[port]; 16428 16429 /* Assert XLPORT soft reset */ 16430 port_count = -1; 16431 rval = 0; 16432 for (bindex = 0; bindex < NUM_SUBPORT; bindex++) { 16433 if (si->port_p2l_mapping[phy_port_base + bindex] != -1) { 16434 soc_reg_field_set(unit, XLPORT_SOFT_RESETr, &rval, 16435 port_field[bindex], 1); 16436 } 16437 } 16438 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, rval)); 16439 16440 for (i = 0; i < _GH2_MAX_TSC_COUNT ; i++) { 16441 if (_gh2_tsc[i].phy_port_base == phy_port_base) { 16442 port_count = _gh2_tsc[i].port_count; 16443 break; 16444 } 16445 } 16446 if (port_count == SOC_GH2_PORT_RATIO_QUAD) { 16447 mode = SOC_GH2_PORT_MODE_QUAD; 16448 si->port_num_lanes[port] = 1; 16449 si->port_num_lanes[port + 1] = 1; 16450 si->port_num_lanes[port + 2] = 1; 16451 si->port_num_lanes[port + 3] = 1; 16452 } else if ((port_count == SOC_GH2_PORT_RATIO_SINGLE) || 16453 (port_count == SOC_GH2_PORT_RATIO_SINGLE_XAUI)) { 16454 mode = SOC_GH2_PORT_MODE_SINGLE; 16455 si->port_num_lanes[port] = 4; 16456 } else if (port_count == SOC_GH2_PORT_RATIO_DUAL_2_2) { 16457 mode = SOC_GH2_PORT_MODE_DUAL; 16458 si->port_num_lanes[port] = 2; 16459 si->port_num_lanes[port + 1] = 2; 16460 } else if (port_count == SOC_GH2_PORT_RATIO_TRI_012) { 16461 mode = SOC_GH2_PORT_MODE_TRI_012; 16462 si->port_num_lanes[port] = 1; 16463 si->port_num_lanes[port + 1] = 1; 16464 si->port_num_lanes[port + 2] = 2; 16465 } else if (port_count == SOC_GH2_PORT_RATIO_TRI_023) { 16466 mode = SOC_GH2_PORT_MODE_TRI_023; 16467 si->port_num_lanes[port] = 2; 16468 si->port_num_lanes[port + 1] = 1; 16469 si->port_num_lanes[port + 2] = 1; 16470 } else { 16471 mode = SOC_GH2_PORT_MODE_QUAD; 16472 si->port_num_lanes[port] = 1; 16473 si->port_num_lanes[port + 1] = 1; 16474 si->port_num_lanes[port + 2] = 1; 16475 si->port_num_lanes[port + 3] = 1; 16476 } 16477 16478 rval = 0; 16479 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 16480 XPORT0_CORE_PORT_MODEf, mode); 16481 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 16482 XPORT0_PHY_PORT_MODEf, mode); 16483 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 16484 16485 /* De-assert XLPORT soft reset */ 16486 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, 0)); 16487 16488 /* Enable XLPORT */ 16489 rval = 0; 16490 for (bindex = 0; bindex < NUM_SUBPORT; bindex++) { 16491 if (si->port_p2l_mapping[phy_port_base + bindex] != -1) { 16492 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, 16493 port_field[bindex], 1); 16494 } 16495 } 16496 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ENABLE_REGr(unit, port, rval)); 16497 } 16498 16499 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 16500 port = SOC_BLOCK_PORT(unit, blk); 16501 if (port == -1 || port == REG_PORT_ANY) { 16502 continue; 16503 } 16504 phy_port_base = si->port_l2p_mapping[port]; 16505 16506 /* Assert XLPORT soft reset */ 16507 port_count = -1; 16508 rval = 0; 16509 for (bindex = 0; bindex < NUM_SUBPORT; bindex++) { 16510 if (si->port_p2l_mapping[phy_port_base + bindex] != -1) { 16511 soc_reg_field_set(unit, CLPORT_SOFT_RESETr, &rval, 16512 port_field[bindex], 1); 16513 } 16514 } 16515 SOC_IF_ERROR_RETURN(WRITE_CLPORT_SOFT_RESETr(unit, port, rval)); 16516 16517 for (i = 0; i < _GH2_MAX_TSC_COUNT ; i++) { 16518 if (_gh2_tsc[i].phy_port_base == phy_port_base) { 16519 port_count = _gh2_tsc[i].port_count; 16520 break; 16521 } 16522 } 16523 if (port_count == SOC_GH2_PORT_RATIO_QUAD) { 16524 mode = SOC_GH2_PORT_MODE_QUAD; 16525 si->port_num_lanes[port] = 1; 16526 si->port_num_lanes[port + 1] = 1; 16527 si->port_num_lanes[port + 2] = 1; 16528 si->port_num_lanes[port + 3] = 1; 16529 } else if ((port_count == SOC_GH2_PORT_RATIO_SINGLE) || 16530 (port_count == SOC_GH2_PORT_RATIO_SINGLE_XAUI)) { 16531 mode = SOC_GH2_PORT_MODE_SINGLE; 16532 si->port_num_lanes[port] = 4; 16533 } else if (port_count == SOC_GH2_PORT_RATIO_DUAL_2_2) { 16534 mode = SOC_GH2_PORT_MODE_DUAL; 16535 si->port_num_lanes[port] = 2; 16536 si->port_num_lanes[port + 1] = 2; 16537 } else if (port_count == SOC_GH2_PORT_RATIO_TRI_012) { 16538 mode = SOC_GH2_PORT_MODE_TRI_012; 16539 si->port_num_lanes[port] = 1; 16540 si->port_num_lanes[port + 1] = 1; 16541 si->port_num_lanes[port + 2] = 2; 16542 } else if (port_count == SOC_GH2_PORT_RATIO_TRI_023) { 16543 mode = SOC_GH2_PORT_MODE_TRI_023; 16544 si->port_num_lanes[port] = 2; 16545 si->port_num_lanes[port + 1] = 1; 16546 si->port_num_lanes[port + 2] = 1; 16547 } else { 16548 mode = SOC_GH2_PORT_MODE_QUAD; 16549 si->port_num_lanes[port] = 1; 16550 si->port_num_lanes[port + 1] = 1; 16551 si->port_num_lanes[port + 2] = 1; 16552 si->port_num_lanes[port + 3] = 1; 16553 } 16554 16555 rval = 0; 16556 soc_reg_field_set(unit, CLPORT_MODE_REGr, &rval, 16557 XPORT0_CORE_PORT_MODEf, mode); 16558 soc_reg_field_set(unit, CLPORT_MODE_REGr, &rval, 16559 XPORT0_PHY_PORT_MODEf, mode); 16560 SOC_IF_ERROR_RETURN(WRITE_CLPORT_MODE_REGr(unit, port, rval)); 16561 16562 /* De-assert XLPORT soft reset */ 16563 SOC_IF_ERROR_RETURN(WRITE_CLPORT_SOFT_RESETr(unit, port, 0)); 16564 16565 /* Enable XLPORT */ 16566 rval = 0; 16567 for (bindex = 0; bindex < NUM_SUBPORT; bindex++) { 16568 if (si->port_p2l_mapping[phy_port_base + bindex] != -1) { 16569 soc_reg_field_set(unit, CLPORT_ENABLE_REGr, &rval, 16570 port_field[bindex], 1); 16571 } 16572 } 16573 SOC_IF_ERROR_RETURN(WRITE_CLPORT_ENABLE_REGr(unit, port, rval)); 16574 } 16575 16576 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 16577 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 16578 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 16579 16580 /* Enable dual hash on L2 and L3 tables */ 16581 fields[0] = ENABLEf; 16582 values[0] = 1; 16583 fields[1] = HASH_SELECTf; 16584 values[1] = FB_HASH_CRC32_LOWER; 16585 fields[2] = INSERT_LEAST_FULL_HALFf; 16586 values[2] = 1; 16587 SOC_IF_ERROR_RETURN 16588 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 16589 fields, values)); 16590 SOC_IF_ERROR_RETURN 16591 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 16592 fields, values)); 16593 16594 /* 16595 * Egress Enable 16596 */ 16597 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 16598 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 16599 PBMP_ALL_ITER(unit, port) { 16600 SOC_IF_ERROR_RETURN 16601 (WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, 16602 SOC_INFO(unit).port_l2p_mapping[port], entry)); 16603 } 16604 16605 COMPILER_64_ZERO(reg64); 16606 soc_reg64_field32_set(unit, EPC_LINK_BMAP_LO_64r, ®64, PORT_BITMAP_LOf, 16607 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 0)); 16608 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAP_LO_64r(unit, reg64)); 16609 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 16610 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 16611 L3SRC_HIT_ENABLEf, 1); 16612 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 16613 L2DST_HIT_ENABLEf, 1); 16614 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 16615 APPLY_EGR_MASK_ON_L2f, 1); 16616 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 16617 APPLY_EGR_MASK_ON_L3f, 1); 16618 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 16619 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 16620 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 16621 ARP_VALIDATION_ENf, 1); 16622 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 16623 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 16624 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 16625 16626 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 16627 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, RING_MODEf, 1); 16628 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 16629 16630 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 16631 * causes the outer tag to be removed from packets that don't have 16632 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 16633 */ 16634 rval = 0; 16635 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 16636 16637 /* Enable pri/cfi remarking on egress ports. */ 16638 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 16639 1); 16640 PBMP_ALL_ITER(unit, port) { 16641 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 16642 } 16643 16644 /* Multicast range initialization */ 16645 SOC_IF_ERROR_RETURN 16646 (soc_hbx_higig2_mcast_sizes_set(unit, 16647 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 16648 SOC_HBX_MULTICAST_RANGE_DEFAULT), 16649 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 16650 SOC_HBX_MULTICAST_RANGE_DEFAULT), 16651 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 16652 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 16653 16654 /* Enable vrf based l3 lookup by default. */ 16655 SOC_IF_ERROR_RETURN 16656 (soc_reg_field32_modify(unit, VRF_MASKr, REG_PORT_ANY, MASKf, 0)); 16657 16658 /* Setup SW2_FP_DST_ACTION_CONTROL */ 16659 fields[0] = HGTRUNK_RES_ENf; 16660 fields[1] = LAG_RES_ENf; 16661 values[0] = values[1] = 1; 16662 SOC_IF_ERROR_RETURN 16663 (soc_reg_fields32_modify(unit, SW2_FP_DST_ACTION_CONTROLr, 16664 REG_PORT_ANY, 2, fields, values)); 16665 16666 /* Populate and enable RTAG7 Macro flow offset table */ 16667 if (soc_mem_is_valid(unit, RTAG7_FLOW_BASED_HASHm)) { 16668 count = soc_mem_index_max(unit, RTAG7_FLOW_BASED_HASHm); 16669 sal_memset(entry, 0, sizeof(rtag7_flow_based_hash_entry_t)); 16670 for (index = 0; index < count; ) { 16671 for (sub_sel = 0; sub_sel < 8 && index < count; sub_sel++) { 16672 for (offset = 0; 16673 offset < rtag7_field_width[sub_sel] && index < count; 16674 offset++) { 16675 soc_mem_field32_set(unit, RTAG7_FLOW_BASED_HASHm, &entry, 16676 SUB_SEL_ECMPf, sub_sel); 16677 soc_mem_field32_set(unit, RTAG7_FLOW_BASED_HASHm, &entry, 16678 OFFSET_ECMPf, offset); 16679 SOC_IF_ERROR_RETURN 16680 (soc_mem_write(unit, RTAG7_FLOW_BASED_HASHm, 16681 MEM_BLOCK_ALL, index, &entry)); 16682 index++; 16683 } 16684 } 16685 } 16686 rval = 0; 16687 soc_reg_field_set(unit, RTAG7_HASH_SELr, &rval, USE_FLOW_SEL_ECMPf, 1); 16688 SOC_IF_ERROR_RETURN(WRITE_RTAG7_HASH_SELr(unit, rval)); 16689 } 16690 16691 freq = si->frequency; 16692 16693 /* 16694 * Set external MDIO freq to around 10MHz 16695 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 16696 */ 16697 target_freq = 10; 16698 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 16699 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, divisor); 16700 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 16701 16702 rval = 0; 16703 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVISORf, divisor); 16704 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVIDENDf, dividend); 16705 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 16706 16707 /* 16708 * Set internal MDIO freq to around 10MHz 16709 * Valid range is from 2.5MHz to 12.5MHz 16710 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 16711 * or 16712 * DIVISOR = core_clock_freq * DIVIDENT / (target_freq * 2) 16713 */ 16714 target_freq = 10; 16715 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 16716 divisor = soc_property_get(unit, spn_RATE_INT_MDIO_DIVISOR, divisor); 16717 dividend = soc_property_get(unit, spn_RATE_INT_MDIO_DIVIDEND, 1); 16718 rval = 0; 16719 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVISORf, 16720 divisor); 16721 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVIDENDf, 16722 dividend); 16723 /* coverity[result_independent_of_operands] */ 16724 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 16725 16726 delay = soc_property_get(unit, spn_MDIO_OUTPUT_DELAY, -1); 16727 if (delay >= 1 && delay <= 15) { 16728 SOC_IF_ERROR_RETURN(READ_CMIC_MIIM_CONFIGr(unit, &rval)); 16729 soc_reg_field_set(unit, CMIC_MIIM_CONFIGr, &rval, MDIO_OUT_DELAYf, 16730 delay); 16731 SOC_IF_ERROR_RETURN(WRITE_CMIC_MIIM_CONFIGr(unit, rval)); 16732 } 16733 16734 /* Directed Mirroring ON by default */ 16735 PBMP_ALL_ITER(unit, port) { 16736 SOC_IF_ERROR_RETURN(READ_EGR_PORT_64r(unit, port, ®64)); 16737 soc_reg64_field32_set(unit, EGR_PORT_64r, 16738 ®64, EM_SRCMOD_CHANGEf, 1); 16739 SOC_IF_ERROR_RETURN(WRITE_EGR_PORT_64r(unit, port, reg64)); 16740 SOC_IF_ERROR_RETURN(READ_IEGR_PORT_64r(unit, port, ®64)); 16741 soc_reg64_field32_set(unit, IEGR_PORT_64r, 16742 ®64, EM_SRCMOD_CHANGEf, 1); 16743 SOC_IF_ERROR_RETURN(WRITE_IEGR_PORT_64r(unit, port, reg64)); 16744 } 16745 16746 /* Attach serdes firmware set function */ 16747 _phy_tsce_firmware_set_helper[unit] = _soc_greyhound2_tscx_firmware_set; 16748 _phy_tscf_firmware_set_helper[unit] = _soc_greyhound2_tscx_firmware_set; 16749 _phy_qtce_firmware_set_helper[unit] = _soc_greyhound2_tscx_firmware_set; 16750 16751 #ifdef INCLUDE_AVS 16752 soc_hr3_avs_init(unit); 16753 #endif /* INCLUDE_AVS */ 16754 16755 16756 /* Major for L3_IIFm.TRUST_DSCP_PTRf init */ 16757 SOC_IF_ERROR_RETURN(_soc_hr3_l3iif_hw_mem_init(unit, TRUE)); 16758 16759 /* Select flow type to not eligible for cut-through */ 16760 flow_type = soc_property_get(unit, spn_FLOW_TYPE_FOR_CUT_THROUGH_CONTROL, 16761 GH2_FLOW_TYPE_SR); 16762 SOC_IF_ERROR_RETURN(READ_CUT_THROUGH_PRIORITYr(unit, &rval)); 16763 if (flow_type == GH2_FLOW_TYPE_TSN) { 16764 soc_reg_field_set(unit, CUT_THROUGH_PRIORITYr, &rval, CT_PRIORITYf, 1); 16765 } else { 16766 /* Default select SR flow type */ 16767 soc_reg_field_set(unit, CUT_THROUGH_PRIORITYr, &rval, CT_PRIORITYf, 0); 16768 } 16769 SOC_IF_ERROR_RETURN(WRITE_CUT_THROUGH_PRIORITYr(unit, rval)); 16770 16771 /* Write default value of EGR_EDB_XMIT_CTRLm for preemption */ 16772 SOC_IF_ERROR_RETURN( 16773 soc_mem_clear(unit, EGR_EDB_XMIT_CTRLm, COPYNO_ALL, TRUE)); 16774 16775 /* Write default value of GE[0~7]_MIN_FRAG_SIZEr for preemption on A0 */ 16776 { 16777 uint16 dev_id; 16778 uint8 rev_id; 16779 16780 soc_cm_get_id(unit, &dev_id, &rev_id); 16781 if (BCM56170_A0_REV_ID == rev_id || BCM56172_A0_REV_ID == rev_id 16782 || BCM56174_A0_REV_ID == rev_id || BCM53570_A0_REV_ID == rev_id 16783 || BCM53575_A0_REV_ID == rev_id 16784 ) { 16785 int reg_index; 16786 soc_reg_t reg[8] = {GE0_MIN_FRAG_SIZEr, 16787 GE1_MIN_FRAG_SIZEr, 16788 GE2_MIN_FRAG_SIZEr, 16789 GE3_MIN_FRAG_SIZEr, 16790 GE4_MIN_FRAG_SIZEr, 16791 GE5_MIN_FRAG_SIZEr, 16792 GE6_MIN_FRAG_SIZEr, 16793 GE7_MIN_FRAG_SIZEr}; 16794 16795 for (reg_index = 0; reg_index < 8; reg_index++) { 16796 rval = 0; 16797 soc_reg_field_set(unit, reg[reg_index], &rval, 16798 FINAL_FRAGf, 0x8); 16799 soc_reg_field_set(unit, reg[reg_index], &rval, 16800 NON_FINAL_FRAGf, 0x8); 16801 SOC_IF_ERROR_RETURN( 16802 soc_reg_write_all_blocks(unit, reg[reg_index], rval)); 16803 } 16804 } 16805 } 16806 16807 /* LEDuP init */ 16808 /* Add board properity which can be used in rc.soc */ 16809 board_name = soc_property_get_str(unit, spn_BOARD_NAME); 16810 16811 if (board_name) { 16812 if (soc_mem_config_set == NULL) { 16813 LOG_ERROR(BSL_LS_SOC_COMMON, 16814 (BSL_META_U(unit, "unit %d : soc_mem_config_set() is NULL\n"), 16815 unit)); 16816 return SOC_E_MEMORY; 16817 } else { 16818 if (sal_strcmp(board_name, "BCM956174R") == 0) { 16819 soc_mem_config_set("bcm956174r", "1"); 16820 SOC_IF_ERROR_RETURN(soc_greyhound2_ledupr_init(unit)); 16821 } else { 16822 if (sal_strcmp(board_name, "BCM956170R") == 0) { 16823 soc_mem_config_set("bcm956170r", "1"); 16824 } 16825 SOC_IF_ERROR_RETURN(soc_greyhound2_ledup_init(unit)); 16826 } 16827 } 16828 } else { 16829 SOC_IF_ERROR_RETURN(soc_greyhound2_ledup_init(unit)); 16830 } 16831 16832 /* 16833 * Clear CMIC_CMCx_CHy_RXBUF_THRESHOLD_CONFIG.ENABLE to not reset MMU 16834 * COS weighting count. 16835 */ 16836 for (i = 0; i < 4; i++) { 16837 rval = soc_pci_read( 16838 unit, 16839 CMIC_CMCx_CHy_RXBUF_THRESHOLD_CONFIG(SOC_PCI_CMC(unit), i)); 16840 rval &= ~0x100; /* Bit 8 ENABLEf = 0 */ 16841 soc_pci_write( 16842 unit, CMIC_CMCx_CHy_RXBUF_THRESHOLD_CONFIG(SOC_PCI_CMC(unit), i), 16843 rval); 16844 } 16845 16846 return SOC_E_NONE; 16847 } 16848 16849 /* soc_greyhound2_mem_config: 16850 * Over-ride the default table sizes (from regsfile) for any SKUs here 16851 */ 16852 int 16853 soc_greyhound2_mem_config(int unit, int dev_id) 16854 { 16855 int rv = SOC_E_NONE; 16856 soc_persist_t *sop = SOC_PERSIST(unit); 16857 uint16 dev = 0; 16858 uint8 rev = 0; 16859 16860 SOC_CONTROL(unit)->l3_defip_max_tcams = 2; 16861 SOC_CONTROL(unit)->l3_defip_tcam_size = 512; /* or 64 per OTP */ 16862 16863 if (SAL_BOOT_QUICKTURN) { 16864 soc_cm_get_id(unit, &dev, &rev); 16865 16866 /* QuickTurn with limited table entries */ 16867 sop->memState[L2_USER_ENTRYm].index_max = 11; 16868 sop->memState[L2_USER_ENTRY_ONLYm].index_max = 11; 16869 sop->memState[VFP_TCAMm].index_max = 63; 16870 sop->memState[EFP_TCAMm].index_max = 63; 16871 sop->memState[FP_TCAMm].index_max = 63; 16872 sop->memState[VLAN_SUBNETm].index_max = 11; 16873 sop->memState[VLAN_SUBNET_ONLYm].index_max = 11; 16874 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 63; 16875 sop->memState[CPU_COS_MAPm].index_max = 11; 16876 sop->memState[CPU_COS_MAP_ONLYm].index_max = 11; 16877 sop->memState[L3_DEFIPm].index_max = 63; 16878 sop->memState[L3_DEFIP_ONLYm].index_max = 63; 16879 16880 if (rev == BCM56170_B0_REV_ID) { 16881 sop->memState[MY_STATION_TCAMm].index_max = 1; 16882 sop->memState[MY_STATION_TCAM_ENTRY_ONLYm].index_max = 1; 16883 sop->memState[MY_STATION_TCAM_DATA_ONLYm].index_max = 1; 16884 } else { 16885 sop->memState[MY_STATION_TCAMm].index_max = 63; 16886 } 16887 } 16888 return rv; 16889 } 16890 16891 /* 16892 * Function: 16893 * _soc_greyhound2_gpio_set 16894 * Purpose: 16895 * Write value to the specified GPIO pin 16896 */ 16897 STATIC int 16898 _soc_greyhound2_gpio_set(int unit, int pin, int output, int val) 16899 { 16900 uint32 rval = 0; 16901 uint32 fval = 0; 16902 uint8 mask = 0xFF; 16903 16904 mask &= ~(1 << pin); 16905 16906 /* coverity[result_independent_of_operands] */ 16907 SOC_IF_ERROR_RETURN(READ_CMIC_GP_OUT_ENr(unit, &rval)); 16908 fval = soc_reg_field_get(unit, CMIC_GP_OUT_ENr, rval, OUT_ENABLEf); 16909 if (output) { 16910 fval |= 1 << pin; 16911 } else { 16912 fval &= ~(1 << pin); 16913 } 16914 soc_reg_field_set(unit, CMIC_GP_OUT_ENr, &rval, OUT_ENABLEf, fval); 16915 /* coverity[result_independent_of_operands] */ 16916 SOC_IF_ERROR_RETURN(WRITE_CMIC_GP_OUT_ENr(unit, rval)); 16917 16918 if (output) { 16919 /* coverity[result_independent_of_operands] */ 16920 SOC_IF_ERROR_RETURN(READ_CMIC_GP_DATA_OUTr(unit, &rval)); 16921 fval = soc_reg_field_get(unit, CMIC_GP_DATA_OUTr, rval, DATA_OUTf); 16922 if (val) { 16923 fval |= (val << pin); 16924 } else { 16925 fval &= ~(1 << pin); 16926 } 16927 16928 soc_reg_field_set(unit, CMIC_GP_DATA_OUTr, &rval, DATA_OUTf, fval); 16929 /* coverity[result_independent_of_operands] */ 16930 SOC_IF_ERROR_RETURN(WRITE_CMIC_GP_DATA_OUTr(unit, rval)); 16931 } 16932 16933 return SOC_E_NONE; 16934 } 16935 16936 /* 16937 * Function: 16938 * soc_greyhound2_serdes_disabled 16939 * Purpose: 16940 * Get the disabled serdes core from strap status register 16941 */ 16942 STATIC int 16943 soc_greyhound2_serdes_disabled(int unit, 16944 uint32 *disabled_tsc, 16945 uint32 *disabled_qtc) 16946 { 16947 uint32 strap_sts_1 = 0; 16948 int power_off = 0; 16949 int i = 0; 16950 soc_field_t qtc_fields[] = { 16951 STRAP_TSCQ0_PWR_OFFf, 16952 STRAP_TSCQ1_PWR_OFFf, 16953 INVALIDf 16954 }; 16955 soc_field_t tsc_fields[] = { 16956 STRAP_TSCE0_PWR_OFFf, 16957 STRAP_TSCE1_PWR_OFFf, 16958 STRAP_TSCE2_PWR_OFFf, 16959 STRAP_TSCE3_PWR_OFFf, 16960 STRAP_TSCE4_PWR_OFFf, 16961 STRAP_TSCE5_PWR_OFFf, 16962 STRAP_TSCE6_PWR_OFFf, 16963 STRAP_TSCF0_PWR_OFFf, 16964 INVALIDf 16965 }; 16966 16967 /* parameter validation */ 16968 if ((disabled_tsc == NULL) || (disabled_qtc == NULL)) { 16969 return SOC_E_PARAM; 16970 } 16971 16972 /* 16973 * For simulation, starp status register is empty. 16974 * Return all QTC and TSC not disabled. 16975 */ 16976 if (SAL_BOOT_SIMULATION) { 16977 *disabled_tsc = 0; 16978 *disabled_qtc = 0; 16979 return SOC_E_NONE; 16980 } else { 16981 if (soc_feature(unit, soc_feature_untethered_otp)) { 16982 /* read OTP information */ 16983 /* qtc */ 16984 for (i = 0; i < 2; i++) { 16985 if (SHR_BITGET(SOC_BOND_INFO(unit)->tsc_disabled, i)) { 16986 *disabled_qtc |= (1 << i); 16987 } 16988 } 16989 /* tsc */ 16990 for (i = 0; i < 8; i++) { 16991 if (SHR_BITGET(SOC_BOND_INFO(unit)->tsc_disabled, 2 + i)) { 16992 *disabled_tsc |= (1 << i); 16993 } 16994 } 16995 } else { 16996 *disabled_tsc = 0; 16997 *disabled_qtc = 0; 16998 } 16999 } 17000 17001 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUS_1r(unit, &strap_sts_1)); 17002 17003 /* Get the disabled QTC cores */ 17004 i = 0; 17005 while (qtc_fields[i] != INVALIDf) { 17006 power_off = soc_reg_field_get(unit, TOP_STRAP_STATUS_1r, 17007 strap_sts_1, qtc_fields[i]); 17008 if (power_off) { 17009 *disabled_qtc |= (1 << i); 17010 } 17011 i++; 17012 }; 17013 17014 /* Get the disabled TSC cores */ 17015 i = 0; 17016 while (tsc_fields[i] != INVALIDf) { 17017 power_off = soc_reg_field_get(unit, TOP_STRAP_STATUS_1r, 17018 strap_sts_1, tsc_fields[i]); 17019 if (power_off) { 17020 *disabled_tsc |= (1 << i); 17021 } 17022 i++; 17023 }; 17024 17025 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17026 (BSL_META_U(unit,"%s: disabled QTC(0x%x), " 17027 "disabled TSC(0x%x)\n"), 17028 FUNCTION_NAME(), *disabled_qtc, *disabled_tsc)); 17029 17030 return SOC_E_NONE; 17031 } 17032 17033 /* 17034 * Function: 17035 * _soc_greyhound2_core_disable 17036 * Purpose: 17037 * Re-config the port info for the core disabled 17038 */ 17039 STATIC int 17040 _soc_greyhound2_core_disable(int unit, int core_type, uint32 disable_core_bmp) 17041 { 17042 int i, j, idx, core_count; 17043 int phy_port, port, blk, num_port; 17044 soc_info_t *si; 17045 const int *core_phy_port; 17046 int mmu_port; 17047 17048 si = &SOC_INFO(unit); 17049 17050 switch (core_type) { 17051 case SOC_GH2_PORT_CORE_TYPE_TSC: 17052 num_port = _GH2_PORT_COUNT_PER_TSC; /* 4 */ 17053 core_phy_port = &tsc_phy_port[0]; 17054 core_count = _GH2_MAX_TSC_COUNT; /* 8 */ 17055 break; 17056 case SOC_GH2_PORT_CORE_TYPE_QTC: 17057 num_port = _GH2_PORT_COUNT_PER_QTC; /* 16 */ 17058 core_phy_port = &qtc_phy_port[0]; 17059 core_count = _GH2_MAX_QTC_COUNT; /* 2 */ 17060 break; 17061 default: 17062 return (SOC_E_PARAM); 17063 } 17064 for (i = 0; i < core_count; i++) { 17065 if ((1 << i) & disable_core_bmp){ 17066 for (j = 0; j < num_port; j++) { 17067 phy_port = core_phy_port[i] + j; 17068 port = si->port_p2l_mapping[phy_port]; 17069 mmu_port = si->port_p2m_mapping[phy_port]; 17070 17071 si->port_p2l_mapping[phy_port] = -1; 17072 /* 17073 * port_p2m_mapping value 127 for non-enabled port program in 17074 * MMU_ARB_TDM_TABLE.PORT_NUMf 17075 */ 17076 si->port_p2m_mapping[phy_port] = 127; 17077 si->max_port_p2m_mapping[phy_port] = -1; 17078 17079 /* skip native unmapped mmu ports */ 17080 if (mmu_port != -1) { 17081 si->port_m2p_mapping[mmu_port] = -1; 17082 } 17083 17084 /* skip native unmapped logical ports */ 17085 if (port != -1) { 17086 for (idx = 0; idx < SOC_DRIVER(unit)->port_num_blktype; idx++) { 17087 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, idx); 17088 if (blk < 0) { /* end of block list of each port */ 17089 break; 17090 } 17091 if(si->block_port[blk] == port){ 17092 si->block_port[blk] = -1; 17093 } 17094 si->block_valid[blk] = 0; 17095 SOC_PBMP_PORT_REMOVE(si->block_bitmap[blk], port); 17096 } 17097 17098 si->port_l2p_mapping[port] = -1; 17099 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 17100 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, port); 17101 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 17102 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, port); 17103 SOC_PBMP_PORT_REMOVE(si->st.bitmap, port); 17104 SOC_PBMP_PORT_REMOVE(si->xl.bitmap, port); 17105 SOC_PBMP_PORT_REMOVE(si->cl.bitmap, port); 17106 SOC_PBMP_PORT_REMOVE(si->all.bitmap, port); 17107 SOC_PBMP_PORT_REMOVE(si->port.bitmap, port); 17108 sal_snprintf(si->port_name[port], 17109 sizeof(si->port_name[port]), 17110 "?%d", port); 17111 si->port_offset[port] = port; 17112 } 17113 } 17114 } 17115 } 17116 17117 #define RECONFIG_PORT_INFO(ptype,str) \ 17118 si->ptype.num = 0; \ 17119 si->ptype.min = si->ptype.max = -1; \ 17120 PBMP_ITER(si->ptype.bitmap, port) { \ 17121 if (sal_strcmp(str,"")) {\ 17122 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]),\ 17123 "%s%d", str, si->ptype.num);\ 17124 }\ 17125 si->ptype.port[si->ptype.num++] = port; \ 17126 if (si->ptype.min < 0) { \ 17127 si->ptype.min = port; \ 17128 } \ 17129 if (port > si->ptype.max) { \ 17130 si->ptype.max = port; \ 17131 } \ 17132 } 17133 17134 /* coverity[pointless_string_compare] */ 17135 RECONFIG_PORT_INFO(ether,""); 17136 /* coverity[pointless_string_compare] */ 17137 RECONFIG_PORT_INFO(st,""); 17138 RECONFIG_PORT_INFO(hg,"hg"); 17139 RECONFIG_PORT_INFO(xe,"xe"); 17140 RECONFIG_PORT_INFO(ge,"ge"); 17141 #undef RECONFIG_PORT_INFO 17142 17143 return SOC_E_NONE; 17144 } 17145 17146 #define TOP_STRAP_STATUS_LCPLL1_REFCLK_SEL(val) \ 17147 (((val) >> 9) & 0x1) 17148 17149 #define TOP_STRAP_STATUS_XTAL_FREQ_SEL_B0(val) \ 17150 (((val) >> 25) & 0x1) 17151 17152 #define TOP_STRAP_STATUS_XTAL_FREQ_SEL_A0(val) \ 17153 (((val) >> 26) & 0x1) 17154 /* 17155 * Function: 17156 * soc_greyhound2_chip_reset 17157 * Purpose: 17158 * Special reset sequencing for BCM53570 17159 */ 17160 int 17161 soc_greyhound2_chip_reset(int unit) 17162 { 17163 uint32 rval, to_usec; 17164 _gh2_option_info_t *matched_opt_info; 17165 uint32 disabled_bmp; 17166 uint32 disabled_tsc = 0; 17167 uint32 disabled_qtc = 0; 17168 int i; 17169 int blk, port; 17170 soc_info_t *si; 17171 uint16 dev_id; 17172 uint8 rev_id; 17173 uint32 core_pll_ndiv; 17174 uint32 core_pll_ch0; 17175 uint32 core_pll_ch1; 17176 uint32 core_pll_ch2; 17177 uint32 core_pll_ch3; 17178 unsigned ext_clk_lcpll0, ext_clk_lcpll1; 17179 uint32 lcpll1_i_refclk_sel, lcpll_xtal_freq_sel; 17180 uint32 strap_sts=0; 17181 17182 unsigned ts_ref_freq; 17183 unsigned ts_idx; 17184 static const soc_pll_param_t ts_pll[] = { /* values for 500MHz TSPLL output */ 17185 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_DIV2 */ 17186 {25000000, 100, 0, 1, 5, 0, 2, 3, 1}, 17187 {50000000, 50, 0, 1, 5, 0, 2, 3, 1}, 17188 { 0, 100, 0, 1, 5, 0, 2, 3, 1}, /* 25MHz, from internal reference */ 17189 { 0, 50, 0, 1, 5, 0, 2, 3, 1} /* 50MHz, from internal reference */ 17190 /* 0 => 25MHz or 50Mhz from internal reference based on strap_xtal_freq_sel */ 17191 }; 17192 unsigned bs_ref_freq; 17193 unsigned bs_idx; 17194 uint32 bs0_ndiv_high, bs0_ndiv_low; 17195 uint32 bs1_ndiv_high, bs1_ndiv_low; 17196 17197 /* For performance reasons, use different settings for BSPLL0 and BSPLL1 */ 17198 static const soc_pll_param_t bs0_pll[] = { /* values for 20MHz BSPLL output */ 17199 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_FB_DIV2 */ 17200 {25000000, 60, 0, 1, 150, 4, 1, 8, 1}, 17201 {50000000, 60, 0, 1, 150, 4, 1, 8, 1}, 17202 { 0, 60 , 0, 1, 150, 4, 1, 8, 1}, /* 25MHz, from internal reference */ 17203 { 0, 60, 0, 1, 150, 4, 1, 8, 1} /* 50MHz, from internal reference */ 17204 /* 0 => 25MHz or 50Mhz from internal reference based on strap_xtal_freq_sel */ 17205 }; 17206 static const soc_pll_param_t bs1_pll[] = { /* values for 20MHz BSPLL output */ 17207 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_FB_DIV2 */ 17208 {25000000, 60, 0, 1, 150, 4, 1, 8, 1}, 17209 {50000000, 60, 0, 1, 150, 4, 1, 8, 1}, 17210 { 0, 60, 0, 1, 150, 4, 1, 8, 1}, /* 25MHz, from internal reference */ 17211 { 0, 60, 0, 1, 150, 4, 1, 8, 1} /* 50MHz, from internal reference */ 17212 /* 0 => 25MHz or 50Mhz from internal reference based on strap_xtal_freq_sel */ 17213 }; 17214 17215 /* Parameters for BSPLL particular to GH2. Same indexing as above */ 17216 static const unsigned bs_cp1[] = {3, 3, 3, 3}; 17217 static const unsigned bs_cp[] = {1, 1, 1, 1}; 17218 static const unsigned bs_cz[] = {3, 3, 3, 3}; 17219 static const unsigned bs_rp[] = {1, 1, 1, 1}; 17220 static const unsigned bs_rz[] = {1, 1, 1, 1}; 17221 static const unsigned bs_icp[] = {42, 42, 42, 42}; 17222 17223 /* MSPI init */ 17224 if (soc_mspi_init(unit) != SOC_E_NONE) { 17225 LOG_WARN(BSL_LS_SOC_COMMON, 17226 (BSL_META_U(unit, 17227 "unit %d : MSPI Init Failed\n"), unit)); 17228 } 17229 17230 soc_cm_get_id(unit, &dev_id, &rev_id); 17231 17232 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 17233 (10 * MILLISECOND_USEC); 17234 17235 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x11110100); /* block 7 - 0 */ 17236 if (rev_id == BCM56170_B0_REV_ID) { 17237 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x00430070); /* block 15 - 8 */ 17238 } else { 17239 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x00430000); /* block 15 - 8 */ 17240 } 17241 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00005064); /* block 23 - 16 */ 17242 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x02220111); /* block 31 - 24 */ 17243 WRITE_CMIC_SBUS_RING_MAP_32_39r(unit, 0x02220222); /* block 39 - 32 */ 17244 WRITE_CMIC_SBUS_RING_MAP_40_47r(unit, 0x22222222); /* block 40 - 47 */ 17245 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0); 17246 17247 sal_usleep(to_usec); 17248 17249 17250 /* core clock PLL setting */ 17251 si = &SOC_INFO(unit); 17252 switch (si->frequency) { 17253 case _GH2_SYSTEM_FREQ_125: 17254 core_pll_ndiv = 140; 17255 core_pll_ch0 = 28; 17256 core_pll_ch1 = 28; 17257 core_pll_ch2 = 14; 17258 core_pll_ch3 = 7; 17259 break; 17260 case _GH2_SYSTEM_FREQ_375: 17261 core_pll_ndiv = 120; 17262 core_pll_ch0 = 8; 17263 core_pll_ch1 = 24; 17264 core_pll_ch2 = 12; 17265 core_pll_ch3 = 6; 17266 break; 17267 case _GH2_SYSTEM_FREQ_389: 17268 core_pll_ndiv = 140; 17269 core_pll_ch0 = 9; 17270 core_pll_ch1 = 28; 17271 core_pll_ch2 = 14; 17272 core_pll_ch3 = 7; 17273 break; 17274 case _GH2_SYSTEM_FREQ_392: 17275 core_pll_ndiv = 110; 17276 core_pll_ch0 = 7; 17277 core_pll_ch1 = 22; 17278 core_pll_ch2 = 11; 17279 core_pll_ch3 = 6; 17280 break; 17281 case _GH2_SYSTEM_FREQ_437: 17282 core_pll_ndiv = 140; 17283 core_pll_ch0 = 8; 17284 core_pll_ch1 = 28; 17285 core_pll_ch2 = 14; 17286 core_pll_ch3 = 7; 17287 break; 17288 case _GH2_SYSTEM_FREQ_450: 17289 core_pll_ndiv = 90; 17290 core_pll_ch0 = 5; 17291 core_pll_ch1 = 18; 17292 core_pll_ch2 = 9; 17293 core_pll_ch3 = 5; 17294 break; 17295 case _GH2_SYSTEM_FREQ_500: 17296 core_pll_ndiv = 140; 17297 core_pll_ch0 = 7; 17298 core_pll_ch1 = 28; 17299 core_pll_ch2 = 14; 17300 core_pll_ch3 = 7; 17301 break; 17302 case _GH2_SYSTEM_FREQ_583: 17303 default: 17304 core_pll_ndiv = 140; 17305 core_pll_ch0 = 6; 17306 core_pll_ch1 = 28; 17307 core_pll_ch2 = 14; 17308 core_pll_ch3 = 7; 17309 break; 17310 } 17311 SOC_IF_ERROR_RETURN 17312 (soc_reg_field32_modify(unit, TOP_CORE_PLL_CTRL3r, 17313 REG_PORT_ANY, MSTR_NDIV_INTf, core_pll_ndiv)); 17314 SOC_IF_ERROR_RETURN 17315 (soc_reg_field32_modify(unit, TOP_CORE_PLL_CTRL4r, 17316 REG_PORT_ANY, MSTR_CH0_MDIVf, core_pll_ch0)); 17317 SOC_IF_ERROR_RETURN 17318 (soc_reg_field32_modify(unit, TOP_CORE_PLL_CTRL4r, 17319 REG_PORT_ANY, MSTR_CH1_MDIVf, core_pll_ch1)); 17320 SOC_IF_ERROR_RETURN 17321 (soc_reg_field32_modify(unit, TOP_CORE_PLL_CTRL5r, 17322 REG_PORT_ANY, MSTR_CH2_MDIVf, core_pll_ch2)); 17323 SOC_IF_ERROR_RETURN 17324 (soc_reg_field32_modify(unit, TOP_CORE_PLL_CTRL6r, 17325 REG_PORT_ANY, MSTR_CH3_MDIVf, core_pll_ch3)); 17326 SOC_IF_ERROR_RETURN 17327 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 17328 CMIC_TO_CORE_PLL_LOADf, 1)); 17329 17330 /* 250Mhz TS PLL implies 4ns resolution */ 17331 /* TSPLL configuration: 500MHz TS_CLK from 20/25/32/50MHz refclk */ 17332 /* CMICd divides by 2 on input, so this is a 250MHz clock to TS logic */ 17333 17334 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); /* 0->internal reference */ 17335 17336 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 17337 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 17338 break; 17339 } 17340 } 17341 17342 strap_sts=0; 17343 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUSr(unit, &strap_sts)); 17344 if (ts_ref_freq == 0) { 17345 if (rev_id == BCM53570_B0_REV_ID) { 17346 ts_idx = (TOP_STRAP_STATUS_XTAL_FREQ_SEL_B0(strap_sts) == 0) ? 2 : 3; 17347 } else { 17348 ts_idx = (TOP_STRAP_STATUS_XTAL_FREQ_SEL_A0(strap_sts) == 0) ? 2 : 3; 17349 } 17350 } 17351 17352 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 17353 LOG_ERROR(BSL_LS_SOC_COMMON, 17354 (BSL_META_U(unit, 17355 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params.\n"), ts_ref_freq)); 17356 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, NDIV_FRAC, MDIV, PDIV, and if 17357 all exist, use them. For now, just fail. 17358 */ 17359 } else { 17360 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_0r(unit,&rval)); 17361 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_0r, &rval, VCO_DIV2f, 17362 soc_property_get(unit, spn_PTP_TS_VCO_DIV2, ts_pll[ts_idx].vco_div2)); 17363 WRITE_TOP_TS_PLL_CTRL_0r(unit, rval); 17364 17365 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_4r(unit,&rval)); 17366 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KAf, 17367 soc_property_get(unit, spn_PTP_TS_KA, ts_pll[ts_idx].ka)); 17368 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KIf, 17369 soc_property_get(unit, spn_PTP_TS_KI, ts_pll[ts_idx].ki)); 17370 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KPf, 17371 soc_property_get(unit, spn_PTP_TS_KP, ts_pll[ts_idx].kp)); 17372 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, FREF_SELf, 17373 ts_ref_freq ? 1 : 0); 17374 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, REFCLK_SELf, 17375 ts_ref_freq ? 1 : 0); 17376 WRITE_TOP_TS_PLL_CTRL_4r(unit, rval); 17377 17378 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_3r(unit,&rval)); 17379 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_INTf, 17380 soc_property_get(unit, spn_PTP_TS_PLL_N, ts_pll[ts_idx].ndiv_int)); 17381 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_FRACf, 17382 ts_pll[ts_idx].ndiv_frac); 17383 WRITE_TOP_TS_PLL_CTRL_3r(unit, rval); 17384 17385 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 17386 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, PDIVf, 17387 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 17388 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, CH0_MDIVf, 17389 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, ts_pll[ts_idx].mdiv)); 17390 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 17391 17392 /* Enable software overwrite of TimeSync PLL settings. */ 17393 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit, &rval)); 17394 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_TS_PLL_LOADf, 1); 17395 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 17396 } 17397 17398 /* 500Mhz TSPLL -> 250MHz ref at timestamper, implies 4ns resolution */ 17399 /* clock period in nanoseconds */ 17400 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); 17401 17402 if (!soc_feature(unit, soc_feature_time_v3_no_bs)) { 17403 /* as a signal to upper-level code that the BroadSync is newly initialized 17404 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware */ 17405 /* coverity[result_independent_of_operands] */ 17406 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit, &rval)); 17407 soc_reg_field_set(unit, CMIC_BS0_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 17408 WRITE_CMIC_BS0_CONFIGr(unit, rval); 17409 17410 /* coverity[result_independent_of_operands] */ 17411 SOC_IF_ERROR_RETURN(READ_CMIC_BS1_CONFIGr(unit, &rval)); 17412 soc_reg_field_set(unit, CMIC_BS1_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 17413 WRITE_CMIC_BS1_CONFIGr(unit, rval); 17414 17415 /* BSPLL0 has not been configured, so reset/configure both BSPLL0 and BSPLL1 */ 17416 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17417 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 0); 17418 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 0); 17419 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 0); 17420 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 0); 17421 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 17422 17423 /* Different BSPLL configurations, but with same Fref */ 17424 17425 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); /* 0->internal reference */ 17426 17427 for (bs_idx = 0; bs_idx < sizeof(bs0_pll)/sizeof(bs0_pll[0]); ++bs_idx) { 17428 if (bs0_pll[bs_idx].ref_freq == bs_ref_freq) { 17429 break; 17430 } 17431 } 17432 17433 if (bs_ref_freq == 0) { 17434 if (rev_id == BCM53570_B0_REV_ID) { 17435 ts_idx = (TOP_STRAP_STATUS_XTAL_FREQ_SEL_B0(strap_sts) == 0) ? 2 : 3; 17436 } else { 17437 ts_idx = (TOP_STRAP_STATUS_XTAL_FREQ_SEL_A0(strap_sts) == 0) ? 2 : 3; 17438 } 17439 } 17440 17441 if (bs_idx == sizeof(bs0_pll)/sizeof(bs0_pll[0])) { 17442 LOG_ERROR(BSL_LS_SOC_COMMON, 17443 (BSL_META_U(unit, 17444 "Invalid value for PTP_BS_REF (%u). No default PLL params.\n"), bs_ref_freq)); 17445 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, 17446 NDIV_FRAC, MDIV, PDIV, and if all exist, use them. For now, just fail. 17447 */ 17448 } else { 17449 /* BSPLL0 */ 17450 /* Program MSC_CTRL=0x24 for External ref as confirmed by Henry */ 17451 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_6r(unit,&rval)); 17452 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_6r, &rval, MSC_CTRLf, 17453 bs_ref_freq ? 0x24 : 0x20); 17454 WRITE_TOP_BS_PLL0_CTRL_6r(unit, rval); 17455 17456 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_1r(unit,&rval)); 17457 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, PDIVf, 17458 soc_property_get(unit, spn_PTP_BS_PDIV, bs0_pll[bs_idx].pdiv)); 17459 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 17460 17461 bs0_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs0_pll[bs_idx].ndiv_int) << 6) | 17462 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs0_pll[bs_idx].ndiv_frac) >> 26) & 0x3f)); 17463 bs0_ndiv_low = ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs0_pll[bs_idx].ndiv_frac) << 6) & 0xffffc000); 17464 17465 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 17466 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC0_LCPLL_FBDIV_0f, bs0_ndiv_low); 17467 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit, rval); 17468 17469 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 17470 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC0_LCPLL_FBDIV_1f, bs0_ndiv_high); 17471 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit, rval); 17472 17473 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_0r(unit,&rval)); 17474 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_0r, &rval, CH0_MDIVf, 17475 soc_property_get(unit, spn_PTP_BS_MNDIV, bs0_pll[bs_idx].mdiv)); 17476 WRITE_TOP_BS_PLL0_CTRL_0r(unit, rval); 17477 17478 17479 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_5r(unit,&rval)); 17480 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, CP1f, bs_cp1[bs_idx]); 17481 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, CPf, bs_cp[bs_idx]); 17482 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, CZf, bs_cz[bs_idx]); 17483 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, RPf, bs_rp[bs_idx]); 17484 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, RZf, bs_rz[bs_idx]); 17485 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, ICPf, bs_icp[bs_idx]); 17486 WRITE_TOP_BS_PLL0_CTRL_5r(unit, rval); 17487 17488 17489 /* BSPLL1 */ 17490 /* Program MSC_CTRL=0x24 for external ref */ 17491 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_6r(unit,&rval)); 17492 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_6r, &rval, MSC_CTRLf, 17493 bs_ref_freq ? 0x24 : 0x20); 17494 WRITE_TOP_BS_PLL1_CTRL_6r(unit, rval); 17495 17496 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_1r(unit,&rval)); 17497 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, PDIVf, 17498 soc_property_get(unit, spn_PTP_BS_PDIV, bs1_pll[bs_idx].pdiv)); 17499 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 17500 17501 bs1_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs1_pll[bs_idx].ndiv_int) << 6) | 17502 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs1_pll[bs_idx].ndiv_frac) >> 26) & 0x3f)); 17503 bs1_ndiv_low = ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs1_pll[bs_idx].ndiv_frac) << 6) & 0xffffc000); 17504 17505 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 17506 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC1_LCPLL_FBDIV_0f, bs1_ndiv_low); 17507 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit, rval); 17508 17509 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 17510 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC1_LCPLL_FBDIV_1f, bs1_ndiv_high); 17511 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit, rval); 17512 17513 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_0r(unit,&rval)); 17514 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_0r, &rval, CH0_MDIVf, 17515 soc_property_get(unit, spn_PTP_BS_MNDIV, bs1_pll[bs_idx].mdiv)); 17516 WRITE_TOP_BS_PLL1_CTRL_0r(unit, rval); 17517 17518 17519 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_5r(unit,&rval)); 17520 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, CP1f, bs_cp1[bs_idx]); 17521 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, CPf, bs_cp[bs_idx]); 17522 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, CZf, bs_cz[bs_idx]); 17523 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, RPf, bs_rp[bs_idx]); 17524 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, RZf, bs_rz[bs_idx]); 17525 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, ICPf, bs_icp[bs_idx]); 17526 WRITE_TOP_BS_PLL1_CTRL_5r(unit, rval); 17527 17528 /* 17529 * Set frequency doubler based on reference clock. 17530 * Greyhound2 supports 25MHz/50MHz reference clocks. 17531 * LCPLL frequency doubler Boolean in PLL control 17532 * register 7 scales 25MHz so effective reference 17533 * frequency equals 50MHz. 17534 */ 17535 strap_sts=0; 17536 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUSr(unit, &strap_sts)); 17537 if (rev_id == BCM53570_B0_REV_ID) { 17538 lcpll_xtal_freq_sel = TOP_STRAP_STATUS_XTAL_FREQ_SEL_B0(strap_sts); 17539 } else { 17540 lcpll_xtal_freq_sel = TOP_STRAP_STATUS_XTAL_FREQ_SEL_A0(strap_sts); 17541 } 17542 17543 if (50000000 == bs_ref_freq || lcpll_xtal_freq_sel ) { /* STRAP_XTAL_FREQ_SEL */ 17544 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_7r(unit, &rval)); 17545 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_7r, &rval, FREQ_DOUBLER_ONf, 0); 17546 WRITE_TOP_BS_PLL0_CTRL_7r(unit, rval); 17547 17548 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_7r(unit, &rval)); 17549 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_7r, &rval, FREQ_DOUBLER_ONf, 0); 17550 WRITE_TOP_BS_PLL1_CTRL_7r(unit, rval); 17551 } else { 17552 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_7r(unit, &rval)); 17553 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_7r, &rval, FREQ_DOUBLER_ONf, 1); 17554 WRITE_TOP_BS_PLL0_CTRL_7r(unit, rval); 17555 17556 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_7r(unit, &rval)); 17557 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_7r, &rval, FREQ_DOUBLER_ONf, 1); 17558 WRITE_TOP_BS_PLL1_CTRL_7r(unit, rval); 17559 } 17560 17561 /* Enable software overwrite of BroadSync 0/1 PLL settings. */ 17562 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit, &rval)); 17563 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL0_SW_OVWRf, 1); 17564 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL1_SW_OVWRf, 1); 17565 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 17566 17567 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_1r(unit,&rval)); 17568 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, LOAD_EN_CHf, 0); 17569 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 17570 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, LOAD_EN_CHf, 1); 17571 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 17572 17573 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_1r(unit,&rval)); 17574 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, LOAD_EN_CHf, 0); 17575 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 17576 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, LOAD_EN_CHf, 1); 17577 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 17578 } 17579 17580 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17581 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 1); 17582 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 1); 17583 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 17584 17585 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17586 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 1); 17587 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 1); 17588 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 17589 17590 /* Increas drive stregth */ 17591 SOC_IF_ERROR_RETURN(READ_ICFG_IPROC_IOPAD_CTRL_21r(unit, &rval)); 17592 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_21r, &rval,IPROC_BS0_CLK_DRIVEf,0x7); 17593 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_21r, &rval,IPROC_BS0_HB_DRIVEf,0x7); 17594 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_21r, &rval,IPROC_BS0_TC_DRIVEf,0x7); 17595 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_21r, &rval,IPROC_BS0_CLK_HYSf, 0x1); 17596 WRITE_ICFG_IPROC_IOPAD_CTRL_21r(unit, rval); 17597 SOC_IF_ERROR_RETURN(READ_ICFG_IPROC_IOPAD_CTRL_20r(unit, &rval)); 17598 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_20r, &rval,IPROC_BS1_CLK_DRIVEf,0x7); 17599 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_20r, &rval,IPROC_BS1_HB_DRIVEf,0x7); 17600 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_20r, &rval,IPROC_BS1_TC_DRIVEf,0x7); 17601 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_20r, &rval,IPROC_BS1_CLK_HYSf, 0x1); 17602 WRITE_ICFG_IPROC_IOPAD_CTRL_20r(unit, rval); 17603 } 17604 17605 /* 17606 * Select LCPLL0 as external PHY reference clock and output 125MHz 17607 */ 17608 /* Pull GPIO3 low to reset the ext. PHY */ 17609 SOC_IF_ERROR_RETURN(_soc_greyhound2_gpio_set(unit, 3, TRUE, 0)); 17610 17611 /* 17612 * Delay required for ensure the output becomes stable before leave 17613 * reset state. 17614 */ 17615 sal_udelay(100); 17616 17617 /* Pull GPIO high to leave the reset state */ 17618 SOC_IF_ERROR_RETURN(_soc_greyhound2_gpio_set(unit, 3, TRUE, 1)); 17619 17620 ext_clk_lcpll0 = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); /* 0->internal reference */ 17621 ext_clk_lcpll1 = soc_property_get(unit, spn_LC_PLL_EXT_CLOCK, 0); /* 0->internal reference */ 17622 17623 strap_sts=0; 17624 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUSr(unit, &strap_sts)); 17625 17626 lcpll1_i_refclk_sel = (TOP_STRAP_STATUS_LCPLL1_REFCLK_SEL(strap_sts) == 1); 17627 17628 if (rev_id == BCM53570_B0_REV_ID) { 17629 lcpll_xtal_freq_sel = TOP_STRAP_STATUS_XTAL_FREQ_SEL_B0(strap_sts); 17630 } else { 17631 lcpll_xtal_freq_sel = TOP_STRAP_STATUS_XTAL_FREQ_SEL_A0(strap_sts); 17632 } 17633 17634 /* # Put PLL in reset state */ 17635 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17636 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_LCPLL_SOFT_RESETf, 0x1); 17637 WRITE_TOP_SOFT_RESET_REGr(unit, rval); 17638 17639 SOC_IF_ERROR_RETURN 17640 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_3r, REG_PORT_ANY, RATE_MANAGER_MODEf, 0x1)); 17641 17642 SOC_IF_ERROR_RETURN 17643 (soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_3r, REG_PORT_ANY, RATE_MANAGER_MODEf, 0x1)); 17644 17645 /* 17646 * Setup LCPLL0 17647 */ 17648 if (ext_clk_lcpll0) { /*external clk source */ 17649 SOC_IF_ERROR_RETURN 17650 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, 0xD1A4)); 17651 SOC_IF_ERROR_RETURN 17652 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, REG_PORT_ANY, FREQ_DOUBLER_ONf, (ext_clk_lcpll0 == 25000000) ? 0x1 : 0x0)); 17653 } else { /*internal clk source */ 17654 /* lcpll_xtal_freq_sel==1 internal 50Mhz */ 17655 SOC_IF_ERROR_RETURN 17656 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, 0x01A2)); 17657 SOC_IF_ERROR_RETURN 17658 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, REG_PORT_ANY, FREQ_DOUBLER_ONf, (lcpll_xtal_freq_sel) ? 0x0 : 0x1)); 17659 } 17660 SOC_IF_ERROR_RETURN 17661 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, CMIC_TO_XG_PLL0_SW_OVWRf, 0x1)); 17662 17663 /* # Setup LCPLL1 */ 17664 if (!lcpll1_i_refclk_sel) { /* External clk source */ 17665 SOC_IF_ERROR_RETURN 17666 (soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, (ext_clk_lcpll1 == 50000000) ? 0xD1A4 : 0x0BA4)); /* 0x0BA4 -> 156.25Mhz external clk Bypass enabled */ 17667 SOC_IF_ERROR_RETURN 17668 (soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, FREQ_DOUBLER_ONf, (ext_clk_lcpll1 == 50000000) ? 0x1 : 0x0)); 17669 SOC_IF_ERROR_RETURN 17670 (soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_0r, REG_PORT_ANY, CH0_MDIVf, (ext_clk_lcpll1 == 50000000) ? 0x15 : 0x14)); 17671 17672 /* # Update FBDIV via bypass holdover logic */ 17673 SOC_IF_ERROR_RETURN 17674 (soc_reg_field32_modify(unit, TOP_XG1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, XG1_LCPLL_FBDIV_1f, (ext_clk_lcpll1 == 50000000) ? 0x0834 : 0x0500)); 17675 SOC_IF_ERROR_RETURN 17676 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_3r, REG_PORT_ANY, XG1_LCPLL_HO_BYP_ENABLEf, 0x1)); 17677 SOC_IF_ERROR_RETURN 17678 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, CMIC_TO_XG_PLL1_SW_OVWRf, 0x1)); 17679 } else { /* Internal clock source */ 17680 SOC_IF_ERROR_RETURN 17681 (soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, 0x01A2)); /* 0x01A2 for both 50Mhz and 156.25 Mhz */ 17682 SOC_IF_ERROR_RETURN 17683 (soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, FREQ_DOUBLER_ONf, 0x1)); 17684 SOC_IF_ERROR_RETURN 17685 (soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_0r, REG_PORT_ANY, CH0_MDIVf, 0x15)); 17686 17687 /* # Update FBDIV via bypass holdover logic */ 17688 SOC_IF_ERROR_RETURN 17689 (soc_reg_field32_modify(unit, TOP_XG1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, XG1_LCPLL_FBDIV_1f, (lcpll_xtal_freq_sel) ? 0x0834 : 0x0500)); 17690 SOC_IF_ERROR_RETURN 17691 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_3r, REG_PORT_ANY, XG1_LCPLL_HO_BYP_ENABLEf, 0x1)); 17692 SOC_IF_ERROR_RETURN 17693 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, CMIC_TO_XG_PLL1_SW_OVWRf, 0x1)); 17694 } 17695 /* # Release PLL reset */ 17696 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17697 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_LCPLL_SOFT_RESETf, 0x0); 17698 WRITE_TOP_SOFT_RESET_REGr(unit, rval); 17699 17700 /* # Update FBDIV via bypass holdover logic again post soft reset */ 17701 SOC_IF_ERROR_RETURN 17702 (soc_reg_field32_modify(unit, TOP_XG1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, XG1_LCPLL_FBDIV_1f, ((lcpll_xtal_freq_sel)||(ext_clk_lcpll1 == 50000000)) ? 0x0834 : 0x0500)); 17703 17704 /* # Release bypass holdover logic */ 17705 SOC_IF_ERROR_RETURN 17706 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_3r, REG_PORT_ANY, XG1_LCPLL_HO_BYP_ENABLEf, 0x0)); 17707 17708 /* 17709 * TSCx or QTCx to be disabled in some sku. 17710 */ 17711 /* To be reviewed on chip */ 17712 if (matched_option_idx == -1) { 17713 LOG_WARN(BSL_LS_SOC_COMMON, 17714 (BSL_META_U(unit, "Warning: soc_greyhound2_port_config_init should " 17715 "be invoked first! Choose bcm56070 port config.\n"))); 17716 matched_option_idx = 0; 17717 } 17718 17719 matched_opt_info = &_gh2_option_port_config[matched_option_idx]; 17720 disabled_tsc = 0; 17721 disabled_qtc = 0; 17722 SOC_IF_ERROR_RETURN( 17723 soc_greyhound2_serdes_disabled(unit, 17724 &disabled_tsc, &disabled_qtc)); 17725 disabled_bmp = matched_opt_info->disabled_tsc_bmp; 17726 for (i = 0; i < _GH2_MAX_TSC_COUNT; i++) { 17727 if ((1 << i) & disabled_bmp) { 17728 disabled_tsc |= (1 << i); 17729 } 17730 } 17731 17732 disabled_bmp = matched_opt_info->disabled_qtc_bmp; 17733 for (i = 0; i < _GH2_MAX_QTC_COUNT; i++) { 17734 if ((1 << i) & disabled_bmp) { 17735 disabled_qtc |= (1 << i); 17736 } 17737 } 17738 17739 if (disabled_tsc) { 17740 SOC_IF_ERROR_RETURN( 17741 _soc_greyhound2_core_disable(unit, SOC_GH2_PORT_CORE_TYPE_TSC, 17742 disabled_tsc)); 17743 } 17744 if (disabled_qtc) { 17745 SOC_IF_ERROR_RETURN( 17746 _soc_greyhound2_core_disable(unit, SOC_GH2_PORT_CORE_TYPE_QTC, 17747 disabled_qtc)); 17748 } 17749 17750 /* Re-order port sequence */ 17751 soc_esw_dport_init(unit); 17752 17753 SOC_IF_ERROR_RETURN(READ_PGW_CTRL_0r(unit, &rval)); 17754 soc_reg_field_set(unit, PGW_CTRL_0r, &rval, SW_PM4X10_DISABLEf, 17755 disabled_tsc & 0x7f); 17756 soc_reg_field_set(unit, PGW_CTRL_0r, &rval, SW_QTC_DISABLEf, 17757 disabled_qtc); 17758 soc_reg_field_set(unit, PGW_CTRL_0r, &rval, SW_PM4X25_DISABLEf, 17759 (disabled_tsc >> 7) & 0x1); 17760 SOC_IF_ERROR_RETURN(WRITE_PGW_CTRL_0r(unit, rval)); 17761 sal_usleep(to_usec); 17762 17763 /* 17764 * Bring port blocks out of reset 17765 */ 17766 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17767 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GE8P_RST_Lf, 0x7); 17768 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GEP0_RST_Lf, 1); 17769 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GEP1_RST_Lf, 1); 17770 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP0_RST_Lf, 1); 17771 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP1_RST_Lf, 1); 17772 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP2_RST_Lf, 1); 17773 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP3_RST_Lf, 1); 17774 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP4_RST_Lf, 1); 17775 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP5_RST_Lf, 1); 17776 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP6_RST_Lf, 1); 17777 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_CLP0_RST_Lf, 1); 17778 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 17779 sal_usleep(to_usec); 17780 17781 /* Bring IP, EP, and MMU blocks out of reset */ 17782 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17783 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 17784 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 17785 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 17786 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 17787 sal_usleep(to_usec); 17788 17789 SOC_BLOCK_ITER(unit, blk, SOC_BLK_GPORT) { 17790 port = SOC_BLOCK_PORT(unit, blk); 17791 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, GPORT_TS_TIMER_47_32_REGr, port, 0, &rval)); 17792 soc_reg_field_set(unit, GPORT_TS_TIMER_47_32_REGr, &rval, TS_TIMER_47_32_VALUEf, 0x2); 17793 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, GPORT_TS_TIMER_47_32_REGr, port, 0, rval)); 17794 } 17795 sal_usleep(to_usec); 17796 17797 /* Bring network sync out of reset */ 17798 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17799 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_TS_RST_Lf, 1); 17800 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 17801 sal_usleep(to_usec); 17802 17803 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17804 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 17805 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17806 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, 17807 &rval, TOP_TS_PLL_POST_RST_Lf, 1); 17808 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17809 17810 /* speed limit settings for some SKUs option */ 17811 17812 return SOC_E_NONE; 17813 } 17814 17815 17816 STATIC int 17817 _soc_greyhound2_age_timer_get(int unit, int *age_seconds, int *enabled) 17818 { 17819 uint32 value; 17820 17821 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &value)); 17822 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_ENAf); 17823 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_VALf); 17824 17825 return SOC_E_NONE; 17826 } 17827 17828 STATIC int 17829 _soc_greyhound2_age_timer_max_get(int unit, int *max_seconds) 17830 { 17831 *max_seconds = 17832 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 17833 17834 return SOC_E_NONE; 17835 } 17836 17837 STATIC int 17838 _soc_greyhound2_age_timer_set(int unit, int age_seconds, int enable) 17839 { 17840 uint32 value; 17841 17842 value = 0; 17843 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_ENAf, enable); 17844 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_VALf, age_seconds); 17845 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, value)); 17846 17847 return SOC_E_NONE; 17848 } 17849 17850 static const soc_reg_t pvtmon_result_reg[] = { 17851 TOP_PVTMON_RESULT_0r, 17852 TOP_TMON0_RESULTr, 17853 TOP_TMON1_RESULTr, 17854 TOP_TMON2_RESULTr 17855 }; 17856 17857 int 17858 soc_gh2_temperature_monitor_get(int unit, 17859 int temperature_max, 17860 soc_switch_temperature_monitor_t *temperature_array, 17861 int *temperature_count) 17862 { 17863 soc_reg_t reg; 17864 int index; 17865 uint32 rval; 17866 int fval, cur, peak; 17867 int num_entries_out; 17868 17869 *temperature_count = 0; 17870 if (COUNTOF(pvtmon_result_reg) > temperature_max) { 17871 num_entries_out = temperature_max; 17872 } else { 17873 num_entries_out = COUNTOF(pvtmon_result_reg); 17874 } 17875 17876 /* Read from TOP_PVTMON_RESULT_0r */ 17877 index = 0; 17878 reg = pvtmon_result_reg[index]; 17879 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 17880 17881 fval = soc_reg_field_get(unit, reg, rval, PVT_DATAf); 17882 cur = (41335000 - (49055 * fval)) / 10000; 17883 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 17884 peak = (41335000 - (49055 * fval)) / 10000; 17885 (temperature_array + index)->curr = cur; 17886 (temperature_array + index)->peak = peak; 17887 17888 /* Read from TOP_TMON0/1/2_RESULT */ 17889 for (index = 1; index < num_entries_out; index++) { 17890 reg = pvtmon_result_reg[index]; 17891 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 17892 17893 cur = -1; 17894 peak = -1; 17895 if (soc_reg_field_get(unit, reg, rval, TMON_DATA_VALIDf)) { 17896 fval = soc_reg_field_get(unit, reg, rval, TMON_DATAf); 17897 cur = (41335000 - (49055 * fval)) / 10000; 17898 peak = cur; 17899 } 17900 (temperature_array + index)->curr = cur; 17901 (temperature_array + index)->peak = peak; 17902 } 17903 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17904 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17905 TOP_TEMP_MON_PEAK_RST_Lf, 0); 17906 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17907 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17908 TOP_TEMP_MON_PEAK_RST_Lf, 1); 17909 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17910 17911 *temperature_count = num_entries_out; 17912 return SOC_E_NONE; 17913 } 17914 17915 typedef struct _gh2_pgw_reg_info_s { 17916 soc_reg_t pgw_reg; 17917 uint32 valid_bm; 17918 uint32 invalid_bm; 17919 uint32 invalid_blk_num_bm; 17920 }_gh2_pgw_reg_info_t; 17921 17922 STATIC _gh2_pgw_reg_info_t _gh2_pgw_reg_info[] = { 17923 {PGW_GX_CONFIGr, 0x3c, 0, 0x1f}, 17924 {PGW_GX_TXFIFO_CTRLr, 0x3c, 0, 0x1f}, 17925 {PGW_GX_SPARE0_REGr, 0x3c, 0, 0x1f}, 17926 {PGW_GX_RXFIFO_SOFT_RESETr, 0, 0, 0x1f}, 17927 {PGW_GX_ECC_CONTROLr, 0, 0, 0x1f}, 17928 {PGW_GX_RXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x1f}, 17929 {PGW_GX_RXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x1f}, 17930 {PGW_GX_RXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x1f}, 17931 {PGW_GX_RXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x1f}, 17932 {PGW_GX_TXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x1f}, 17933 {PGW_GX_TXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x1f}, 17934 {PGW_GX_TXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x1f}, 17935 {PGW_GX_TXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x1f}, 17936 {PGW_GX_TXFIFO2_ECC_SBE_STATUSr, 0, 0, 0x1f}, 17937 {PGW_GX_TXFIFO2_ECC_DBE_STATUSr, 0, 0, 0x1f}, 17938 {PGW_GX_TXFIFO3_ECC_SBE_STATUSr, 0, 0, 0x1f}, 17939 {PGW_GX_TXFIFO3_ECC_DBE_STATUSr, 0, 0, 0x1f}, 17940 {PGW_GX_TXFIFO_OVERFLOWr, 0, 0, 0x1f}, 17941 {PGW_GX_RXFIFO0_OVERFLOW_ERRORr, 0, 0, 0x1f}, 17942 {PGW_GX_RXFIFO1_OVERFLOW_ERRORr, 0, 0, 0x1f}, 17943 {PGW_GX_TM0_CONTROLr, 0, 0, 0x1f}, 17944 {PGW_GX_TM1_CONTROLr, 0, 0, 0x1f}, 17945 {PGW_GX_TM2_CONTROLr, 0, 0, 0x1f}, 17946 {PGW_GX_TM3_CONTROLr, 0, 0, 0x1f}, 17947 {PGW_GX_TM4_CONTROLr, 0, 0, 0x1f}, 17948 {PGW_GX_TM5_CONTROLr, 0, 0, 0x1f}, 17949 {PGW_GX_TM6_CONTROLr, 0, 0, 0x1f}, 17950 {PGW_GX_TM7_CONTROLr, 0, 0, 0x1f}, 17951 {PGW_GX_TM8_CONTROLr, 0, 0, 0x1f}, 17952 {PGW_GX_BYPASS_LED_CHAIN_CONFIGr, 0, 0, 0x1f}, 17953 {PGW_GX_INTR_STATUSr, 0, 0, 0x1f}, 17954 {PGW_GX_INTR_ENABLEr, 0, 0, 0x1f}, 17955 {PGW_XL_CONFIGr, 0, 0x3c, 0x20}, 17956 {PGW_XL_TXFIFO_CTRLr, 0, 0x3c, 0x20}, 17957 {PGW_XL_SPARE0_REGr, 0, 0x3c, 0x20}, 17958 {PGW_XL_RXFIFO_SOFT_RESETr, 0, 0, 0x20}, 17959 {PGW_XL_ECC_CONTROLr, 0, 0, 0x20}, 17960 {PGW_XL_RXFIFO_ECC_SBE_STATUSr, 0, 0, 0x20}, 17961 {PGW_XL_RXFIFO_ECC_DBE_STATUSr, 0, 0, 0x20}, 17962 {PGW_XL_TXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x20}, 17963 {PGW_XL_TXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x20}, 17964 {PGW_XL_TXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x20}, 17965 {PGW_XL_TXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x20}, 17966 {PGW_XL_TXFIFO2_ECC_SBE_STATUSr, 0, 0, 0x20}, 17967 {PGW_XL_TXFIFO2_ECC_DBE_STATUSr, 0, 0, 0x20}, 17968 {PGW_XL_TXFIFO3_ECC_SBE_STATUSr, 0, 0, 0x20}, 17969 {PGW_XL_TXFIFO3_ECC_DBE_STATUSr, 0, 0, 0x20}, 17970 {PGW_XL_TXFIFO_OVERFLOWr, 0, 0, 0x20}, 17971 {PGW_XL_RXFIFO_OVERFLOW_ERRORr, 0, 0, 0x20}, 17972 {PGW_XL_TM0_CONTROLr, 0, 0, 0x20}, 17973 {PGW_XL_TM1_CONTROLr, 0, 0, 0x20}, 17974 {PGW_XL_TM2_CONTROLr, 0, 0, 0x20}, 17975 {PGW_XL_TM3_CONTROLr, 0, 0, 0x20}, 17976 {PGW_XL_TM4_CONTROLr, 0, 0, 0x20}, 17977 {PGW_XL_TM5_CONTROLr, 0, 0, 0x20}, 17978 {PGW_XL_TM6_CONTROLr, 0, 0, 0x20}, 17979 {PGW_XL_TM7_CONTROLr, 0, 0, 0x20}, 17980 {PGW_XL_TM8_CONTROLr, 0, 0, 0x20}, 17981 {PGW_XL_BYPASS_LED_CHAIN_CONFIGr, 0, 0, 0x20}, 17982 {PGW_XL_INTR_STATUSr, 0, 0, 0x20}, 17983 {PGW_XL_INTR_ENABLEr, 0, 0, 0x20}, 17984 {INVALIDr, 0, 0}, 17985 }; 17986 17987 /* 17988 * Function: 17989 * soc_greyhound2_pgw_reg_blk_index_get 17990 * Purpose: 17991 * Deal with the blk, blknum for PGW_GX and PGW_XL registers 17992 * Parameters: 17993 * reg (IN): register. 17994 * port (IN): logical port if PGW_GX's port register. 17995 * bm (IN/OUT): bm should be added for the reg. 17996 * block (IN/OUT): blk used to access the reg. 17997 * index (OUT): port index of the reg. 17998 * invalid_blk_check (IN): perform the blk check. 17999 * skip the block if the return value = 1. 18000 * Return: 18001 * SOC_E_NOT_FOUND : w/o bm,blk,invalid_blk_check case, register not matched. 18002 * 1 : register matched and the block/index has been override. 18003 * 1 : register matched and the valid bm has been override. 18004 * 1 : skip the block when the invalid_blk_check=1 18005 * SOC_E_PARAM : invalid paramter 18006 */ 18007 int 18008 soc_greyhound2_pgw_reg_blk_index_get(int unit, 18009 soc_reg_t reg, soc_port_t port, 18010 pbmp_t *bm, int *block, int *index, int invalid_blk_check) { 18011 18012 int i, p, phy_port, blk_num, pgw_blk; 18013 soc_reg_info_t *reginfo; 18014 _gh2_pgw_reg_info_t *pgw_reg = NULL; 18015 pbmp_t pgw_pbm, pgw_invalid_pbm; 18016 18017 pgw_blk = -1; 18018 SOC_PBMP_CLEAR(pgw_pbm); 18019 18020 for (i = 0; _gh2_pgw_reg_info[i].pgw_reg != INVALIDr; i ++) { 18021 if (reg == _gh2_pgw_reg_info[i].pgw_reg) { 18022 pgw_reg = &_gh2_pgw_reg_info[i]; 18023 break; 18024 } 18025 } 18026 18027 if (!pgw_reg) { 18028 return SOC_E_NOT_FOUND; 18029 } 18030 18031 reginfo = &SOC_REG_INFO(unit, reg); 18032 phy_port = 0; 18033 if (reginfo->regtype == soc_portreg) { 18034 SOC_PBMP_WORD_SET(pgw_pbm, 0, pgw_reg->valid_bm); 18035 SOC_PBMP_WORD_SET(pgw_invalid_pbm, 0, pgw_reg->invalid_bm); 18036 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 18037 } 18038 18039 if (bm != NULL) { 18040 SOC_PBMP_ITER(pgw_pbm, p) { 18041 SOC_PBMP_PORT_ADD(*bm, p); 18042 } 18043 return 1; 18044 } 18045 if (block) { 18046 if (reginfo->regtype == soc_portreg) { 18047 if (SOC_PORT_BLOCK_TYPE(unit,phy_port) == SOC_BLK_GXPORT) { 18048 if (SOC_PBMP_MEMBER(pgw_pbm, port)) { 18049 /* get the blk from phy_port=2 bindex=1 i.e. XLPORT5 */ 18050 pgw_blk = SOC_PORT_IDX_BLOCK(unit, 2, 1); 18051 if (index) { 18052 *index = phy_port - 2; 18053 } 18054 if (!invalid_blk_check) { 18055 *block = pgw_blk; 18056 return 1; 18057 } 18058 } 18059 if (SOC_PBMP_MEMBER(pgw_invalid_pbm, port)) { 18060 *block = 0; 18061 return 1; 18062 } 18063 } 18064 } 18065 } 18066 if (invalid_blk_check) { 18067 if (!block) { 18068 return SOC_E_PARAM; 18069 } 18070 /* check if the *block is valid for the reg */ 18071 18072 if (pgw_blk == -1) { 18073 pgw_blk = *block; 18074 } 18075 blk_num = SOC_BLOCK_NUMBER(unit, pgw_blk) & 0xff; 18076 if (pgw_reg->invalid_blk_num_bm & (1 << blk_num)) { 18077 return 1; 18078 } 18079 } 18080 return SOC_E_NONE; 18081 } 18082 18083 /* 18084 * Function: 18085 * soc_gh2_chip_sku_get 18086 * Purpose: 18087 * Get the chip sku 18088 * Parameters : 18089 * sku - (OUT)Greyhound2 chip sku(SOC_GH2_SKU_XXX) 18090 */ 18091 int 18092 soc_gh2_chip_sku_get(int unit, int *sku) 18093 { 18094 uint16 dev_id; 18095 uint8 rev_id; 18096 18097 soc_cm_get_id(unit, &dev_id, &rev_id); 18098 18099 if ((dev_id & 0xfff0) == 0xb170) { 18100 /* Hurricane3-MG (56170, 56172, 56174) */ 18101 *sku = SOC_GH2_SKU_HURRICANE3MG; 18102 } else if ((dev_id & 0xfff0) == 0x8570) { 18103 /* Quartz (53570, 53575) */ 18104 *sku = SOC_GH2_SKU_QUARTZ; 18105 } else { 18106 *sku = -1; 18107 return SOC_E_BADID; 18108 } 18109 18110 return SOC_E_NONE; 18111 } 18112 18113 int 18114 _soc_greyhound2_features(int unit, soc_feature_t feature) 18115 { 18116 int sku = 0; 18117 int flow_type = 0; 18118 uint16 dev_id = 0; 18119 uint8 rev_id = 0; 18120 18121 SOC_IF_ERROR_RETURN(soc_gh2_chip_sku_get(unit, &sku)); 18122 18123 flow_type = soc_property_get(unit, spn_FLOW_TYPE_FOR_CUT_THROUGH_CONTROL, 18124 GH2_FLOW_TYPE_SR); 18125 18126 soc_cm_get_id(unit, &dev_id, &rev_id); 18127 18128 switch (feature) { 18129 case soc_feature_arl_hashed: 18130 case soc_feature_arl_insert_ovr: 18131 case soc_feature_cfap_pool: 18132 case soc_feature_cos_rx_dma: 18133 case soc_feature_dcb_type37: 18134 case soc_feature_ingress_metering: 18135 case soc_feature_egress_metering: 18136 case soc_feature_l3_lookup_cmd: 18137 case soc_feature_led_proc: 18138 case soc_feature_led_data_offset_a0: 18139 case soc_feature_schmsg_alias: 18140 case soc_feature_stack_my_modid: 18141 case soc_feature_stat_dma: 18142 case soc_feature_cpuport_stat_dma: 18143 case soc_feature_table_dma: 18144 case soc_feature_tslam_dma: 18145 case soc_feature_stg: 18146 case soc_feature_stg_xgs: 18147 case soc_feature_remap_ut_prio: 18148 case soc_feature_xgxs_v7: 18149 case soc_feature_phy_cl45: 18150 case soc_feature_aging_extended: 18151 case soc_feature_modmap: 18152 case soc_feature_l2_hashed: 18153 case soc_feature_l2_lookup_cmd: 18154 case soc_feature_l2_lookup_retry: 18155 case soc_feature_l2_user_table: 18156 case soc_feature_schan_hw_timeout: 18157 case soc_feature_mdio_enhanced: 18158 case soc_feature_dodeca_serdes: 18159 case soc_feature_rxdma_cleanup: 18160 case soc_feature_fe_maxframe: 18161 case soc_feature_l2x_parity: 18162 case soc_feature_l3x_parity: 18163 case soc_feature_l2_modfifo: 18164 case soc_feature_vlan_mc_flood_ctrl: 18165 case soc_feature_vlan_translation: 18166 case soc_feature_parity_err_tocpu: 18167 case soc_feature_nip_l3_err_tocpu: 18168 case soc_feature_l3mtu_fail_tocpu: 18169 case soc_feature_meter_adjust: 18170 case soc_feature_xgxs_power: 18171 case soc_feature_src_modid_blk: 18172 case soc_feature_src_modid_blk_ucast_override: 18173 case soc_feature_src_modid_blk_opcode_override: 18174 case soc_feature_egress_blk_ucast_override: 18175 case soc_feature_stat_jumbo_adj: 18176 case soc_feature_stat_xgs3: 18177 case soc_feature_port_trunk_index: 18178 case soc_feature_port_flow_hash: 18179 case soc_feature_cpuport_switched: 18180 case soc_feature_cpuport_mirror: 18181 case soc_feature_higig2: 18182 case soc_feature_color: 18183 case soc_feature_color_inner_cfi: 18184 case soc_feature_color_prio_map: 18185 case soc_feature_untagged_vt_miss: 18186 case soc_feature_module_loopback: 18187 case soc_feature_dscp_map_per_port: 18188 case soc_feature_egr_dscp_map_per_port: 18189 case soc_feature_dscp_map_mode_all: 18190 case soc_feature_higig_lookup: 18191 case soc_feature_egr_mirror_path: 18192 case soc_feature_trunk_extended: 18193 case soc_feature_hg_trunking: 18194 case soc_feature_hg_trunk_override: 18195 case soc_feature_egr_vlan_check: 18196 case soc_feature_cpu_proto_prio: 18197 case soc_feature_hg_trunk_failover: 18198 case soc_feature_trunk_egress: 18199 case soc_feature_force_forward: 18200 case soc_feature_port_egr_block_ctl: 18201 case soc_feature_bucket_support: 18202 case soc_feature_remote_learn_trust: 18203 case soc_feature_src_mac_group: 18204 case soc_feature_storm_control: 18205 case soc_feature_hw_stats_calc: 18206 case soc_feature_mac_learn_limit: 18207 case soc_feature_linear_drr_weight: 18208 case soc_feature_igmp_mld_support: 18209 case soc_feature_basic_dos_ctrl: 18210 case soc_feature_enhanced_dos_ctrl: 18211 case soc_feature_proto_pkt_ctrl: 18212 case soc_feature_vlan_ctrl: 18213 case soc_feature_big_icmpv6_ping_check: 18214 case soc_feature_trunk_group_overlay: 18215 case soc_feature_xport_convertible: 18216 case soc_feature_dual_hash: 18217 case soc_feature_dscp: 18218 case soc_feature_rcpu_1: 18219 case soc_feature_unimac: 18220 case soc_feature_ifg_wb_include_unimac: 18221 case soc_feature_xlmac: 18222 case soc_feature_clmac: 18223 case soc_feature_generic_table_ops: 18224 case soc_feature_vlan_translation_range: 18225 case soc_feature_static_pfm: 18226 case soc_feature_sgmii_autoneg: 18227 case soc_feature_rcpu_priority: 18228 case soc_feature_rcpu_tc_mapping: 18229 case soc_feature_mem_push_pop: 18230 case soc_feature_dcb_reason_hi: 18231 case soc_feature_multi_sbus_cmds: 18232 case soc_feature_new_sbus_format: 18233 case soc_feature_new_sbus_old_resp: 18234 case soc_feature_sbus_format_v4: 18235 case soc_feature_fifo_dma: 18236 case soc_feature_fifo_dma_active: 18237 case soc_feature_l2_pending: 18238 case soc_feature_internal_loopback: 18239 case soc_feature_vlan_action: 18240 case soc_feature_mac_based_vlan: 18241 case soc_feature_ip_subnet_based_vlan: 18242 case soc_feature_packet_rate_limit: 18243 case soc_feature_system_mac_learn_limit: 18244 case soc_feature_field: 18245 case soc_feature_field_mirror_ovr: 18246 case soc_feature_field_udf_higig: 18247 case soc_feature_field_udf_ethertype: 18248 case soc_feature_field_udf_offset_hg_114B: 18249 case soc_feature_field_udf_offset_hg2_110B: 18250 case soc_feature_field_comb_read: 18251 case soc_feature_field_wide: 18252 case soc_feature_field_slice_enable: 18253 case soc_feature_field_cos: 18254 case soc_feature_field_color_indep: 18255 case soc_feature_field_qual_drop: 18256 case soc_feature_field_qual_IpType: 18257 case soc_feature_field_qual_Ip6High: 18258 case soc_feature_field_qual_vlanformat_reverse: 18259 case soc_feature_field_ingress_global_meter_pools: 18260 case soc_feature_field_ingress_ipbm: 18261 case soc_feature_field_egress_flexible_v6_key: 18262 case soc_feature_field_egress_global_counters: 18263 case soc_feature_field_ing_egr_separate_packet_byte_counters: 18264 case soc_feature_field_egress_metering: 18265 case soc_feature_field_intraslice_double_wide: 18266 case soc_feature_field_virtual_slice_group: 18267 case soc_feature_field_virtual_queue: 18268 case soc_feature_field_action_timestamp: 18269 case soc_feature_field_action_l2_change: 18270 case soc_feature_field_action_redirect_nexthop: 18271 case soc_feature_field_action_pfc_class: 18272 case soc_feature_field_action_redirect_ipmc: 18273 case soc_feature_field_slice_dest_entity_select: 18274 case soc_feature_field_packet_based_metering: 18275 case soc_feature_lport_tab_profile: 18276 case soc_feature_field_oam_actions: 18277 case soc_feature_oam: 18278 case soc_feature_ignore_cmic_xgxs_pll_status: 18279 case soc_feature_use_double_freq_for_ddr_pll: 18280 case soc_feature_counter_parity: 18281 case soc_feature_extended_pci_error: 18282 case soc_feature_qos_profile: 18283 case soc_feature_rx_timestamp: 18284 case soc_feature_rx_timestamp_upper: 18285 case soc_feature_logical_port_num: 18286 case soc_feature_timestamp_counter: 18287 case soc_feature_modport_map_profile: 18288 case soc_feature_modport_map_dest_is_hg_port_bitmap: 18289 case soc_feature_eee: 18290 case soc_feature_xy_tcam: 18291 case soc_feature_xy_tcam_direct: 18292 case soc_feature_xy_tcam_28nm: 18293 case soc_feature_vlan_egr_it_inner_replace: 18294 case soc_feature_cmicm: 18295 case soc_feature_iproc: 18296 case soc_feature_iproc_7: 18297 case soc_feature_unified_port: 18298 case soc_feature_sbusdma: 18299 case soc_feature_mirror_encap_profile: 18300 case soc_feature_higig_misc_speed_support: 18301 case soc_feature_vpd_profile: 18302 case soc_feature_color_prio_map_profile: 18303 case soc_feature_mem_parity_eccmask: 18304 case soc_feature_l2_no_vfi: 18305 case soc_feature_gmii_clkout: 18306 case soc_feature_fifo_dma_hu2: 18307 case soc_feature_proxy_port_property: 18308 case soc_feature_system_reserved_vlan: 18309 case soc_feature_ser_parity: 18310 case soc_feature_mem_cache: 18311 case soc_feature_mem_wb_cache_reload: 18312 case soc_feature_ser_engine: 18313 case soc_feature_ser_system_scrub: 18314 case soc_feature_regs_as_mem: 18315 case soc_feature_cmicd_v2: 18316 case soc_feature_cmicm_extended_interrupts: 18317 case soc_feature_int_common_init: 18318 case soc_feature_inner_tpid_enable: 18319 case soc_feature_no_tunnel: 18320 case soc_feature_eee_bb_mode: 18321 case soc_feature_hg_no_speed_change: 18322 case soc_feature_src_modid_base_index: 18323 case soc_feature_avs: 18324 case soc_feature_l2_overflow: 18325 case soc_feature_l2_overflow_bucket: 18326 case soc_feature_l2_learn_stats: 18327 case soc_feature_miml: 18328 case soc_feature_custom_header: 18329 case soc_feature_ing_capwap_parser: 18330 case soc_feature_port_extension: 18331 case soc_feature_niv: 18332 case soc_feature_gh2_rtag7: 18333 case soc_feature_no_vlan_vrf: 18334 case soc_feature_tscf: 18335 case soc_feature_sync_port_lport_tab: 18336 /* GH2 Service Metering Block is a simple version of Apache */ 18337 case soc_feature_global_meter: 18338 case soc_feature_global_meter_v2: 18339 case soc_feature_global_meter_source_l2: 18340 case soc_feature_separate_ing_lport_rtag7_profile: 18341 case soc_feature_rtag7_port_profile: 18342 case soc_feature_no_vrf_stats: 18343 case soc_feature_flowcnt: 18344 case soc_feature_high_portcount_register: 18345 case soc_feature_asf: 18346 case soc_feature_hg2_light_in_portmacro: 18347 case soc_feature_tas: 18348 case soc_feature_use_local_1588: 18349 case soc_feature_common_egr_ip_tunnel_ser: 18350 case soc_feature_memory_2bit_ecc_ser: 18351 case soc_feature_switch_match: 18352 case soc_feature_pktpri_as_dot1p: 18353 case soc_feature_cpureg_dump: 18354 case soc_feature_hr2_dual_hash: 18355 case soc_feature_discard_ability: 18356 case soc_feature_wred_drop_counter_per_port: 18357 case soc_feature_ecn_wred: 18358 case soc_feature_port_encap_speed_max_config: 18359 case soc_feature_extended_cmic_error: 18360 case soc_feature_xlmac_speed_display_above_10g: 18361 case soc_feature_xlmac_timestamp_disable: 18362 case soc_feature_serdes_firmware_pos_by_host_endian: 18363 case soc_feature_dport_update_hl: 18364 case soc_feature_phy_interface_wb: 18365 case soc_feature_port_enable_encap_restore: 18366 case soc_feature_timesync_time_capture: 18367 return TRUE; 18368 case soc_feature_tsn: 18369 case soc_feature_tsn_sr: 18370 case soc_feature_tsn_sr_hsr: 18371 case soc_feature_tsn_sr_prp: 18372 case soc_feature_tsn_sr_802_1cb: 18373 case soc_feature_tsn_mtu_stu: 18374 case soc_feature_uc_mhost: 18375 case soc_feature_ptp: 18376 return TRUE; 18377 case soc_feature_tsn_sr_auto_learn: 18378 if (NUM_PORT(unit) < 3) { 18379 /* 18380 * At least 3 ports are required to setup SR Auto Learn table. 18381 */ 18382 return FALSE; 18383 } else { 18384 return TRUE; 18385 } 18386 case soc_feature_uc: 18387 if (soc_property_get(unit, spn_UC_VALID_BMP, 1) != 0) { 18388 return TRUE; 18389 } else { 18390 return FALSE; 18391 } 18392 case soc_feature_tsn_taf: 18393 if (rev_id == BCM56170_B0_REV_ID) { 18394 return TRUE; 18395 } else { 18396 return FALSE; 18397 } 18398 case soc_feature_tsn_sr_flow_no_asf_select: 18399 if (flow_type == GH2_FLOW_TYPE_SR) { 18400 return TRUE; 18401 } else { 18402 return FALSE; 18403 } 18404 break; 18405 case soc_feature_tsn_flow_no_asf_select: 18406 if (flow_type == GH2_FLOW_TYPE_TSN) { 18407 return TRUE; 18408 } else { 18409 return FALSE; 18410 } 18411 break; 18412 case soc_feature_time_v3_no_bs: 18413 return FALSE; 18414 case soc_feature_e2ecc: 18415 case soc_feature_priority_flow_control: 18416 case soc_feature_gh_style_pfc_config: 18417 case soc_feature_time_support: 18418 case soc_feature_time_v3: 18419 case soc_feature_timesync_support: 18420 case soc_feature_timesync_v3: 18421 case soc_feature_timesync_timestampingmode: 18422 return TRUE; 18423 case soc_feature_gh2_my_station: 18424 return TRUE; 18425 case soc_feature_preempt_mib_support: 18426 case soc_feature_clmib_support: 18427 case soc_feature_ecmp_hash_bit_count_select: 18428 return TRUE; 18429 case soc_feature_field_multi_stage: 18430 return TRUE; 18431 case soc_feature_field_slices12: 18432 case soc_feature_field_meter_pools12: 18433 18434 return TRUE; 18435 case soc_feature_field_slices8: 18436 case soc_feature_field_meter_pools8: 18437 18438 return FALSE; 18439 case soc_feature_field_slice_size128: 18440 18441 return FALSE; 18442 case soc_feature_preemption: 18443 case soc_feature_preemption_cnt: 18444 return TRUE; 18445 case soc_feature_l3_no_ecmp: 18446 case soc_feature_miml_no_l3: 18447 #if 1 18448 if (!SAL_BOOT_SIMULATION) { 18449 return FALSE; 18450 } else { 18451 #endif 18452 if (sku == SOC_GH2_SKU_QUARTZ) { 18453 return TRUE; 18454 } else { 18455 return FALSE; 18456 } 18457 } 18458 break; 18459 case soc_feature_e2efc: 18460 return TRUE; 18461 /* L3 related features */ 18462 case soc_feature_l3: 18463 case soc_feature_l3_ip6: 18464 case soc_feature_l3_entry_key_type: 18465 case soc_feature_lpm_tcam: 18466 case soc_feature_ip_mcast: 18467 case soc_feature_ip_mcast_repl: 18468 case soc_feature_ipmc_unicast: 18469 case soc_feature_ipmc_use_configured_dest_mac: 18470 case soc_feature_urpf: 18471 case soc_feature_l3mc_use_egress_next_hop: 18472 case soc_feature_l3_sgv: 18473 case soc_feature_l3_dynamic_ecmp_group: 18474 case soc_feature_l3_ingress_interface: 18475 case soc_feature_l3_iif_zero_invalid: 18476 case soc_feature_l3_iif_under_4k: 18477 case soc_feature_vxlan_lite: 18478 case soc_feature_tunnel_any_in_6: 18479 case soc_feature_rroce: 18480 #if 1 18481 if (!SAL_BOOT_SIMULATION) { 18482 return TRUE; 18483 } else { 18484 #endif 18485 if (sku == SOC_GH2_SKU_QUARTZ) { 18486 return FALSE; 18487 } else { 18488 return TRUE; 18489 } 18490 } 18491 break; 18492 case soc_feature_untethered_otp: 18493 #if 1 18494 return (!SAL_BOOT_SIMULATION); 18495 #endif 18496 case soc_feature_vxlan_lite_riot: 18497 /* Only GH2-B0 suport VXLAN-Lite RIOT */ 18498 if (rev_id == BCM56170_B0_REV_ID) { 18499 return TRUE; 18500 } else { 18501 return FALSE; 18502 } 18503 break; 18504 case soc_feature_trunk_group_size: 18505 if (rev_id == BCM56170_B0_REV_ID) { 18506 /* tTRUNK_GROUP.TG_SIZE is supported in B0 */ 18507 return TRUE; 18508 } else { 18509 return FALSE; 18510 } 18511 break; 18512 default: 18513 return FALSE; 18514 } 18515 } 18516 18517 /* 18518 * Function: 18519 * soc_gh2_tdm_size_get 18520 * Purpose: 18521 * Get the TDM array size. 18522 * Parameters: 18523 * unit - unit number. 18524 * tdm_size (OUT) - TDM array size 18525 * Returns: 18526 * SOC_E_XXX 18527 */ 18528 int soc_gh2_tdm_size_get(int unit, int *tdm_size) 18529 { 18530 _gh2_option_info_t *matched_opt_info; 18531 18532 /* The function should be called only if the TDM is programmed */ 18533 if (matched_option_idx == -1) { 18534 LOG_WARN(BSL_LS_SOC_COMMON, 18535 (BSL_META_U(unit, "Warning: soc_greyhound2_port_config_init " 18536 "should be invoked first! \n"))); 18537 return SOC_E_INIT; 18538 } 18539 18540 /* Return the TDM size */ 18541 matched_opt_info = &_gh2_option_port_config[matched_option_idx]; 18542 *tdm_size = matched_opt_info->tdm_table_size; 18543 18544 return SOC_E_NONE; 18545 } 18546 18547 /* 18548 * Function: 18549 * soc_gh2_tdm_size_set 18550 * Purpose: 18551 * Set the TDM array size. 18552 * Parameters: 18553 * unit - unit number. 18554 * tdm_size (OUT) - TDM array size 18555 * Returns: 18556 * SOC_E_XXX 18557 */ 18558 int soc_gh2_tdm_size_set(int unit, int tdm_size) 18559 { 18560 _gh2_option_info_t *matched_opt_info; 18561 int flex_mode_id = -1; 18562 int i; 18563 18564 matched_opt_info = &_gh2_option_port_config[matched_option_idx]; 18565 18566 /* Check if AutoTDM available on the option */ 18567 for (i = 0; _gh2_option_tsc_flex_modes[i].config_op; i++) { 18568 if (!sal_strcmp(matched_opt_info->config_op, 18569 _gh2_option_tsc_flex_modes[i].config_op)) { 18570 flex_mode_id = i; 18571 break; 18572 } 18573 } 18574 if (flex_mode_id != -1) { 18575 /* AutoTDM option */ 18576 matched_opt_info->tdm_table_size = tdm_size; 18577 } else { 18578 LOG_WARN(BSL_LS_SOC_COMMON, 18579 (BSL_META_U(unit, "Warning: TDM size cannot be changed " 18580 "on this option.\n"))); 18581 return SOC_E_FAIL; 18582 } 18583 return SOC_E_NONE; 18584 } 18585 18586 /* 18587 * Function: 18588 * soc_gh2_64q_port_check 18589 * Purpose: 18590 * Check if the port(logical) is capable of configured up to 64 COSQ. 18591 * Parameters: 18592 * unit - StrataSwitch unit number. 18593 * port - logical port. 18594 * is_64q (OUT) - with 64 COSQ or not 18595 * Returns: 18596 * BCM_E_XXX 18597 */ 18598 int soc_gh2_64q_port_check(int unit, soc_port_t port, int *is_64q_port) 18599 { 18600 int phy_port; 18601 int mmu_port; 18602 18603 /* Array access protection. */ 18604 if ((port < 0) || (port >= SOC_MAX_NUM_PORTS)){ 18605 return SOC_E_PORT; 18606 } 18607 18608 *is_64q_port = 0; 18609 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 18610 if (phy_port < 0) { 18611 /* Invalid port. */ 18612 return SOC_E_PORT; 18613 } 18614 18615 mmu_port = SOC_INFO(unit).port_p2m_mapping[phy_port]; 18616 if ((mmu_port >= SOC_GH2_64Q_MMU_PORT_IDX_MIN) && 18617 (mmu_port <= SOC_GH2_64Q_MMU_PORT_IDX_MAX)) { 18618 *is_64q_port = 1; 18619 } else { 18620 *is_64q_port = 0; 18621 } 18622 return SOC_E_NONE; 18623 } 18624 18625 /* 18626 * For calculate GH2 MMU_MAX/MIN_BUCKET_QLAYER table index. 18627 * - mmu port 0~57 : 8 entries 18628 * - mmu port 58~65 : 64 entries 18629 * (IN) p : logical port 18630 * (IN) q : cosq 18631 * (OUT) idx : the entry index of MMU_MAX/MIN_BUCKET_QLAYER table 18632 */ 18633 int 18634 soc_gh2_mmu_bucket_qlayer_index(int unit, int p, int q, int *idx) 18635 { 18636 int is_64q; 18637 int phy_port; 18638 int mmu_port; 18639 18640 is_64q = 0; 18641 phy_port = SOC_INFO(unit).port_l2p_mapping[p]; 18642 mmu_port = SOC_INFO(unit).port_p2m_mapping[phy_port]; 18643 18644 SOC_IF_ERROR_RETURN(soc_gh2_64q_port_check(unit, p, &is_64q)); 18645 18646 18647 if (!is_64q) { 18648 *idx = (mmu_port * SOC_GH2_LEGACY_QUEUE_NUM) + q; 18649 } else { 18650 *idx = (SOC_GH2_64Q_MMU_PORT_IDX_MIN * SOC_GH2_LEGACY_QUEUE_NUM) + \ 18651 ((mmu_port-SOC_GH2_64Q_MMU_PORT_IDX_MIN) * \ 18652 SOC_GH2_QLAYER_COSQ_PER_PORT_NUM) + \ 18653 q; 18654 } 18655 return SOC_E_NONE; 18656 } 18657 18658 /* 18659 * For calculate GH2 MMU_MAX/MIN_BUCKET_QGROUP table index. 18660 * - mmu port 0~57 : not available 18661 * - mmu port 58~65 : 8 entries 18662 * (IN) p : logical port 18663 * (IN) g : queue group id 18664 * (OUT) idx : the entry index of MMU_MAX/MIN_BUCKET_QGROUP table 18665 */ 18666 int 18667 soc_gh2_mmu_bucket_qgroup_index(int unit, int p, int g, int *idx) 18668 { 18669 int is_64q = 0; 18670 int phy_port; 18671 int mmu_port; 18672 18673 SOC_IF_ERROR_RETURN(soc_gh2_64q_port_check(unit, p, &is_64q)); 18674 if (!is_64q) { 18675 /* MMU port 0~57 do not have QGROUP tables */ 18676 return SOC_E_PARAM; 18677 } 18678 18679 phy_port = SOC_INFO(unit).port_l2p_mapping[p]; 18680 mmu_port = SOC_INFO(unit).port_p2m_mapping[phy_port]; 18681 *idx = ((mmu_port - SOC_GH2_64Q_MMU_PORT_IDX_MIN) * \ 18682 SOC_GH2_QGROUP_PER_PORT_NUM) + g; 18683 18684 return SOC_E_NONE; 18685 } 18686 18687 /* 18688 * Greyhound2 chip driver functions. 18689 */ 18690 soc_functions_t soc_greyhound2_drv_funs = { 18691 _soc_greyhound2_misc_init, 18692 _soc_greyhound2_mmu_init, 18693 _soc_greyhound2_age_timer_get, 18694 _soc_greyhound2_age_timer_max_get, 18695 _soc_greyhound2_age_timer_set, 18696 _soc_greyhound2_tscx_firmware_set, 18697 _soc_greyhound2_tscx_reg_read, 18698 _soc_greyhound2_tscx_reg_write, 18699 soc_greyhound2_bond_info_init 18700 }; 18701 18702 soc_error_t 18703 soc_greyhound2_granular_speed_get(int unit, soc_port_t port, int *speed) 18704 { 18705 soc_info_t *si = &SOC_INFO(unit); 18706 18707 /* CLMAC and XLMAC only */ 18708 if (!IS_CL_PORT(unit, port) && !IS_XL_PORT(unit, port)) { 18709 return SOC_E_PARAM; 18710 } 18711 18712 *speed = gh2_port_speed[si->port_l2p_mapping[port]]; 18713 18714 return SOC_E_NONE; 18715 } 18716 18717 int 18718 soc_greyhound2_port_speed_update(int unit, soc_port_t port, int speed) 18719 { 18720 soc_info_t *si = &SOC_INFO(unit); 18721 18722 gh2_port_speed[si->port_l2p_mapping[port]] = speed; 18723 18724 return SOC_E_NONE; 18725 } 18726 18727 int 18728 soc_greyhound2_auto_tdm_realloc(int unit) 18729 { 18730 _gh2_option_info_t *matched_port_config; 18731 int option_match = 0; 18732 int qtc0_match = 0; 18733 int qtc1_match = 0; 18734 18735 if (matched_option_idx == -1) { 18736 LOG_WARN(BSL_LS_SOC_COMMON, 18737 (BSL_META_U(unit, "Warning: soc_greyhound2_port_config_init should " 18738 "be invoked first! Choose default port config.\n"))); 18739 matched_option_idx = 0; 18740 } 18741 matched_port_config = &_gh2_option_port_config[matched_option_idx]; 18742 18743 /* 18744 * The following combination requires TDM reallocation. 18745 * 18746 * Option 6 and 9B. 18747 * QTC in SGMII mode and at 2.5Gps. 18748 */ 18749 if (!sal_strcmp(matched_port_config->config_op, OPTION_6) || 18750 !sal_strcmp(matched_port_config->config_op, OPTION_9B)) { 18751 option_match = 1; 18752 } 18753 18754 if ((matched_port_config->qtc_default_mode[0] == \ 18755 _GH2_QTC_SERDES_DEFAULT_MODE_SGMII)) { 18756 if ((matched_port_config->speed_max[qtc_phy_port[0]] == 25) || 18757 (matched_port_config->speed_max[qtc_phy_port[0] + 1] == 25) || 18758 (matched_port_config->speed_max[qtc_phy_port[0] + 2] == 25) || 18759 (matched_port_config->speed_max[qtc_phy_port[0] + 3] == 25)) { 18760 qtc0_match = 1; 18761 } 18762 } 18763 18764 if ((matched_port_config->qtc_default_mode[1] == \ 18765 _GH2_QTC_SERDES_DEFAULT_MODE_SGMII)) { 18766 if ((matched_port_config->speed_max[qtc_phy_port[1]] == 25) || 18767 (matched_port_config->speed_max[qtc_phy_port[1] + 1] == 25) || 18768 (matched_port_config->speed_max[qtc_phy_port[1] + 2] == 25) || 18769 (matched_port_config->speed_max[qtc_phy_port[1] + 3] == 25)) { 18770 qtc1_match = 1; 18771 } 18772 } 18773 18774 if (option_match && (qtc0_match || qtc1_match)) { 18775 return 1; 18776 } 18777 18778 return 0; 18779 } 18780 #endif /* BCM_GREYHOUND2_SUPPORT */