greyhound.c (347775B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: greyhound.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <sal/core/boot.h> 14 15 #include <soc/firebolt.h> 16 #include <soc/bradley.h> 17 #include <soc/greyhound.h> 18 #include <soc/drv.h> 19 #include <soc/mem.h> 20 #include <soc/hash.h> 21 #include <soc/lpm.h> 22 #include <soc/error.h> 23 #include <soc/debug.h> 24 #include <soc/er_tcam.h> 25 #include <soc/memtune.h> 26 #include <soc/devids.h> 27 #include <soc/defs.h> 28 #include <soc/mspi.h> 29 #include <soc/iproc.h> 30 #include <soc/esw/portctrl.h> 31 32 #include <shared/util.h> 33 #include <shared/l3.h> 34 #include <shared/bsl.h> 35 #include <soc/soc_ser_log.h> 36 37 #ifdef BCM_GREYHOUND_SUPPORT 38 #if defined(INCLUDE_L3) 39 #include <soc/greyhound.h> 40 #endif 41 42 #define SOC_MAX_PHY_PORTS 38 43 44 /* Port config related : p2l, max_speed and TDM */ 45 /* Embedded Mode */ 46 /* 16x10G : 10G Embedded*/ 47 static const int p2l_mapping_embedded_16x10g[] = { 48 0, -1, -1, -1, -1, -1, -1, -1, 49 -1, -1, -1, -1, -1, -1, -1, -1, 50 -1, -1, -1, -1, -1, -1, 2, 3, 51 4, 5, 6, 7, 8, 9, 10, 11, 52 12, 13, 14, 15, 16, 17 53 }; 54 static const int port_speed_max_embedded_16x10g[] = { 55 -1, -1, -1, -1, -1, -1, -1, -1, 56 -1, -1, -1, -1, -1, -1, -1, -1, 57 -1, -1, -1, -1, -1, -1, 110, 110, 58 110, 110, 110, 110, 110, 110, 110, 110, 59 110, 110, 110, 110, 110, 110 60 }; 61 62 /* 8x10G: Low Port Count 10G Embedded */ 63 static const int p2l_mapping_embedded_8x10g[] = { 64 0, -1, -1, -1, -1, -1, -1, -1, 65 -1, -1, -1, -1, -1, -1, -1, -1, 66 -1, -1, -1, -1, -1, -1, 2, 3, 67 4, 5, 6, 7, 8, 9, -1, -1, 68 -1, -1, -1, -1, -1, -1 69 }; 70 static const int port_speed_max_embedded_8x10g[] = { 71 -1, -1, -1, -1, -1, -1, -1, -1, 72 -1, -1, -1, -1, -1, -1, -1, -1, 73 -1, -1, -1, -1, -1, -1, 110, 110, 74 110, 110, 110, 110, 110, 110, -1, -1, 75 -1, -1, -1, -1, -1, -1 76 }; 77 78 /* Mixed Embeded Mode */ 79 /* 12x10G + 8x2.5G + 4x5G */ 80 /* 24x2.5G */ 81 static const int p2l_mapping_mixed_embeded[] = { 82 0, -1, 2, 3, 4, 5, -1, -1, 83 -1, -1, -1, -1, -1, -1, -1, -1, 84 -1, -1, 6, 7, 8, 9, 10, 11, 85 12, 13, 14, 15, 16, 17, 18, 19, 86 20, 21, 22, 23, 24, 25 87 }; 88 89 /* 24x2.5G */ 90 static const int port_speed_max_mixed_embeded_24x2p5[] = { 91 -1, -1, 25, 25, 25, 25, -1, -1, 92 -1, -1, -1, -1, -1, -1, -1, -1, 93 -1, -1, 25, 25, 25, 25, 25, 25, 94 25, 25, 25, 25, 25, 25, 25, 25, 95 25, 25, 25, 25, 25, 25 96 }; 97 /* 12x10G + 8x2.5G + 4x5G */ 98 static const int port_speed_max_mixed_embeded[] = { 99 -1, -1, 50, 50, 50, 50, -1, -1, 100 -1, -1, -1, -1, -1, -1, -1, -1, 101 -1, -1, 25, 25, 25, 25, 25, 25, 102 25, 25, 110, 110, 110, 110, 110, 110, 103 110, 110, 110, 110, 110, 110 104 }; 105 /* 16x10G */ 106 static const int p2l_mapping_mixed_embeded_16x10g[] = { 107 0, -1, 2, -1, -1, -1, -1, -1, 108 -1, -1, -1, -1, -1, -1, -1, -1, 109 -1, -1, 3, -1, -1, -1, 4, 5, 110 6, 7, 8, 9, 10, 11, 12, 13, 111 14, 15, 16, 17, -1, -1 112 }; 113 static const int port_speed_max_mixed_embeded_16x10g[] = { 114 -1, -1, 100, -1, -1, -1, -1, -1, 115 -1, -1, -1, -1, -1, -1, -1, -1, 116 -1, -1, 100, -1, -1, -1, 110, 110, 117 110, 110, 110, 110, 110, 110, 110, 110, 118 110, 110, 110, 110, -1, -1 119 }; 120 /* Cascade Mode, Non-Cascade */ 121 /* 24x1GE + 2x10G + 2x13G*/ 122 static const int p2l_mapping_cascade[] = { 123 0, -1, 2, 3, 4, 5, 6, 7, 124 8, 9, 10, 11, 12, 13, 14, 15, 125 16, 17, 18, 19, 20, 21, 22, 23, 126 24, 25, 26, -1, 27, -1, 28, -1, 127 29, -1, -1, -1, -1, -1 128 }; 129 130 static const int port_speed_max_cascade[] = { 131 -1, -1, 10, 10, 10, 10, 10, 10, 132 10, 10, 10, 10, 10, 10, 10, 10, 133 10, 10, 10, 10, 10, 10, 10, 10, 134 10, 10, 110, -1, 110, -1, 130, -1, 135 130, -1, -1, -1, -1, -1 136 }; 137 138 /* 16x1G(4xQSGMII) + 8x2.5G + 2x10G + 2x13G*/ 139 static const int port_speed_max_cascade_2p5[] = { 140 -1, -1, 10, 10, 10, 10, 10, 10, 141 10, 10, 10, 10, 10, 10, 10, 10, 142 10, 10, 25, 25, 25, 25, 25, 25, 143 25, 25, 110, -1, 110, -1, 130, -1, 144 130, -1, -1, -1, -1, -1 145 }; 146 147 /* Non-Cascade Mode */ 148 /* 24x1GE + 4x10GE */ 149 static const int port_speed_max_non_cascade[] = { 150 -1, -1, 10, 10, 10, 10, 10, 10, 151 10, 10, 10, 10, 10, 10, 10, 10, 152 10, 10, 10, 10, 10, 10, 10, 10, 153 10, 10, 110, -1, 110, -1, 110, -1, 154 110, -1, -1, -1, -1, -1 155 }; 156 157 /* 16x1GE(QSGMII)+ 8x2.5G + 4x10GE */ 158 static const int port_speed_max_non_cascade_2p5[] = { 159 -1, -1, 10, 10, 10, 10, 10, 10, 160 10, 10, 10, 10, 10, 10, 10, 10, 161 10, 10, 25, 25, 25, 25, 25, 25, 162 25, 25, 110, -1, 110, -1, 110, -1, 163 110, -1, -1, -1, -1, -1 164 }; 165 /* 53401 option 3/56062/5345x/5342x */ 166 static const int p2l_mapping_cascade_1[] = { 167 0, -1, 2, 3, 4, 5, 6, 7, 168 8, 9, -1, -1, -1, -1, -1, -1, 169 -1, -1, 10, 11, 12, 13, 14, 15, 170 16, 17, 18, 19, 20, 21, 22, 23, 171 24, 25, 26, 27, 28, 29 172 }; 173 static const int port_speed_max_cascade_1[] = { 174 -1, -1, 10, 10, 10, 10, 10, 10, 175 10, 10, -1, -1, -1, -1, -1, -1, 176 -1, -1, 10, 10, 10, 10, 10, 10, 177 10, 10, 110, 110, 110, 110, 10, 10, 178 10, 10, 10, 10, 10, 10 179 }; 180 /* 8x1GE + 16x2.5G + 4x10G */ 181 static const int port_speed_max_56062_op1[] = { 182 -1, -1, 10, 10, 10, 10, 10, 10, 183 10, 10, -1, -1, -1, -1, -1, -1, 184 -1, -1, 25, 25, 25, 25, 25, 25, 185 25, 25, 25, 25, 25, 25, 25, 25, 186 25, 25, 110, 110, 110, 110 187 }; 188 /* 8x1GE + 8x2.5G + 6x10G */ 189 static const int port_speed_max_56062_op2[] = { 190 -1, -1, 10, 10, 10, 10, 10, 10, 191 10, 10, -1, -1, -1, -1, -1, -1, 192 -1, -1, 25, 25, 25, 25, 25, 25, 193 25, 25, 100, -1, -1, -1, 100, -1, 194 -1, -1, 110, 110, 110, 110 195 }; 196 /* 20x2.5G + 4x10G */ 197 static const int port_speed_max_53454[] = { 198 -1, -1, 25, 25, 25, 25, -1, -1, 199 -1, -1, -1, -1, -1, -1, -1, -1, 200 -1, -1, 25, 25, 25, 25, 25, 25, 201 25, 25, 110, 110, 110, 110, 25, 25, 202 25, 25, 25, 25, 25, 25 203 }; 204 /* 8x1GE + 16x2.5G + 4x10G */ 205 static const int port_speed_max_53456[] = { 206 -1, -1, 10, 10, 10, 10, 10, 10, 207 10, 10, -1, -1, -1, -1, -1, -1, 208 -1, -1, 25, 25, 25, 25, 25, 25, 209 25, 25, 110, 110, 110, 110, 25, 25, 210 25, 25, 25, 25, 25, 25 211 }; 212 /* 8x1G + 2x10G */ 213 static const int port_speed_max_53422[] = { 214 -1, -1, -1, -1, -1, -1, -1, -1, 215 -1, -1, -1, -1, -1, -1, -1, -1, 216 -1, -1, 10, 10, 10, 10, 10, 10, 217 10, 10, 110, 110, -1, -1, -1, -1, 218 -1, -1, -1, -1, -1, -1 219 }; 220 /* 8x1GE + 16x1G + 4x10G */ 221 static const int port_speed_max_53424[] = { 222 -1, -1, 10, 10, 10, 10, 10, 10, 223 10, 10, -1, -1, -1, -1, -1, -1, 224 -1, -1, 10, 10, 10, 10, 10, 10, 225 10, 10, 110, 110, 110, 110, 10, 10, 226 10, 10, 10, 10, 10, 10 227 }; 228 /* 20x1G + 4x10G */ 229 static const int port_speed_max_53426[] = { 230 -1, -1, 10, 10, 10, 10, -1, -1, 231 -1, -1, -1, -1, -1, -1, -1, -1, 232 -1, -1, 10, 10, 10, 10, 10, 10, 233 10, 10, 110, 110, 110, 110, 10, 10, 234 10, 10, 10, 10, 10, 10 235 }; 236 /* 16x1G + 4x2.5G */ 237 static const int port_speed_max_56066[] = { 238 -1, -1, -1, -1, -1, -1, -1, -1, 239 -1, -1, -1, -1, -1, -1, -1, -1, 240 -1, -1, 10, 10, 10, 10, 10, 10, 241 10, 10, 25, 25, 25, 25, 10, 10, 242 10, 10, 10, 10, 10, 10 243 }; 244 /* 53403 */ 245 /* 13x1GE + 5x10G-KR + 1xXAUI*/ 246 static const int p2l_mapping_53403[] = { 247 0, -1, 2, -1, -1, -1, -1, -1, 248 -1, -1, -1, -1, -1, -1, -1, -1, 249 -1, -1, 3, 4, 5, 6, 7, 8, 250 9, 10, 11, 12, 13, 14, 15, -1, 251 16, -1, 17, 18, 19, 20 252 }; 253 254 static const int port_speed_max_53403[] = { 255 -1, -1, 100, -1, -1, -1, -1, -1, 256 -1, -1, -1, -1, -1, -1, -1, -1, 257 -1, -1, 10, 10, 10, 10, 10, 10, 258 10, 10, 10, 10, 10, 10, 10, -1, 259 100, -1, 100, 100, 100, 100 260 }; 261 262 /* 53404 */ 263 static const int p2l_mapping_53404[] = { 264 0, -1, 2, -1, -1, -1, -1, -1, 265 -1, -1, -1, -1, -1, -1, -1, -1, 266 -1, -1, 3, 4, 5, 6, 7, 8, 267 9, 10, 11, 12, 13, -1, 14, -1, 268 -1, -1, -1, -1, -1, -1 269 }; 270 static const int port_speed_max_53404_op1[] = { 271 -1, -1, 100, -1, -1, -1, -1, -1, 272 -1, -1, -1, -1, -1, -1, -1, -1, 273 -1, -1, 10, 10, 10, 10, 10, 10, 274 10, 10, 100, -1, -1, -1, 10, -1, 275 -1, -1, -1, -1, -1, -1 276 }; 277 static const int port_speed_max_53404_op2[] = { 278 -1, -1, 100, -1, -1, -1, -1, -1, 279 -1, -1, -1, -1, -1, -1, -1, -1, 280 -1, -1, 10, 10, 10, 10, 10, 10, 281 10, -1, 100, 100, 100, -1, -1, -1, 282 -1, -1, -1, -1, -1, -1 283 }; 284 /* 53406 option 2&3 */ 285 static const int p2l_mapping_53406_op2[] = { 286 0, -1, 2, -1, 4, -1, -1, -1, 287 -1, -1, -1, -1, -1, -1, -1, -1, 288 -1, -1, 6, -1, -1, -1, 10, -1, 289 -1, -1, 14, 15, 16, 17, 18, 19, 290 20, 21, 22, 23, 24, 25 291 }; 292 static const int port_speed_max_53406_op2[] = { 293 -1, -1, 100, -1, -1, -1, -1, -1, 294 -1, -1, -1, -1, -1, -1, -1, -1, 295 -1, -1, 100, -1, -1, -1, 100, -1, 296 -1, -1, 100, -1, -1, -1, 110, 110, 297 110, 110, 110, 110, 110, 110 298 }; 299 300 /* 53406 option 4 */ 301 static const int port_speed_max_53406_op4[] = { 302 -1, -1, 10, 10, 10, 10, -1, -1, 303 -1, -1, -1, -1, -1, -1, -1, -1, 304 -1, -1, 10, 10, 10, 10, 10, 110, 305 110, 110, 110, 110, 110, 110, 110, 110, 306 110, 110, 110, 110, 110, 110 307 }; 308 309 static const int port_blk_gport[] = { 310 -1, -1, 311 0, 0, 0, 0, 312 -1, -1, -1, -1, -1, -1, -1, -1, 313 -1, -1, -1, -1, -1, -1, -1, -1, 314 -1, -1, -1, -1, -1, -1, -1, -1, 315 -1, -1, -1, -1, -1, -1, -1, -1, 316 }; 317 static const int port_blk_xlport[] = { 318 -1, -1, 319 1, 1, 1, 1, 320 -1, -1, -1, -1, -1, -1, -1, -1, 321 -1, -1, -1, -1, -1, -1, -1, -1, 322 -1, -1, -1, -1, -1, -1, -1, -1, 323 -1, -1, -1, -1, -1, -1, -1, -1, 324 }; 325 326 static const int speed_limit_56060_op2[] = { 327 0x24, 0x3, 0x4, 0x5, 328 0x25, 0x13, 0x14, 0x15, 329 0x16, 0x17, 0x18, 0x19, 330 0x1a, 0x1b, 0x1c, 0x1d, 331 0x1e, 0x1f, 0x20, 0x21, 332 0x22, 0x23, 0x2, 0x12 333 }; 334 static const int speed_limit_53406_op2[] = { 335 0x2, 0x3, 0x4, 0x5, 336 0x1b, 0x13, 0x14, 0x15, 337 0x1c, 0x17, 0x18, 0x19, 338 0x1a, 0x12, 0x16, 0x1d, 339 0x1e, 0x1f, 0x20, 0x21, 340 0x22, 0x23, 0x24, 0x25 341 }; 342 static const int speed_limit_53406_op4[] = { 343 0x16, 0x17, 0x18, 0x19, 344 0x12, 0x13, 0x14, 0x15, 345 0x2, 0x3, 0x4, 0x5, 346 0x1a, 0x1b, 0x1c, 0x1d, 347 0x1e, 0x1f, 0x20, 0x21, 348 0x22, 0x23, 0x24, 0x25 349 }; 350 static const int speed_limit_53401_op3[] = { 351 0x2, 0x3, 0x4, 0x5, 352 0x12, 0x13, 0x14, 0x15, 353 0x16, 0x17, 0x18, 0x19, 354 0x1a, 0x1e, 0x1c, 0x20, 355 0x1b, 0x1f, 0x1d, 0x21, 356 0x22, 0x23, 0x24, 0x25 357 }; 358 static const int speed_limit_53456_op1[] = { 359 0x2, 0x3, 0x4, 0x5, 360 0x12, 0x13, 0x14, 0x15, 361 0x16, 0x17, 0x18, 0x19, 362 0x1a, 0x1e, 0x1c, 0x20, 363 0x1b, 0x1f, 0x1d, 0x21, 364 0x22, 0x23, 0x24, 0x25 365 }; 366 367 /* Embedded Mode TDM */ 368 /* 56060 option 1, 53405/53415 */ 369 uint32 gh_tdm_10g_embedded[68] = { 370 22, 23, 24, 25, 26, 27, 371 28, 29, 30, 31, 32, 33, 372 34, 35, 36, 37, 0, 22, 373 23, 24, 25, 26, 27, 28, 374 29, 30, 31, 32, 33, 34, 375 35, 36, 37, 63, 22, 23, 376 24, 25, 26, 27, 28, 29, 377 30, 31, 32, 33, 34, 35, 378 36, 37, 63, 22, 23, 24, 379 25, 26, 27, 28, 29, 30, 380 31, 32, 33, 34, 35, 36, 381 37, 63}; 382 /* Mixed Embeded Mode TDM */ 383 /* 53406/53416 option 1*/ 384 uint32 gh_tdm_mixed_embeded_4x5g[68] = { 385 26, 27, 28, 29, 30, 31, 386 32, 33, 2, 18, 22, 34, 387 35, 36, 37, 0, 3, 26, 388 27, 28, 29, 30, 31, 32, 389 33, 4, 19, 23, 34, 35, 390 36, 37, 63, 5, 26, 27, 391 28, 29, 30, 31, 32, 33, 392 2, 20, 24, 34, 35, 36, 393 37, 63, 3, 26, 27, 28, 394 29, 30, 31, 32, 33, 4, 395 21, 25, 34, 35, 36, 37, 396 63, 5}; 397 /* 53406/53416 option 1*/ 398 uint32 gh_tdm_mixed_embeded_2xrxaui[68] = { 399 26, 27, 28, 29, 30, 31, 400 32, 33, 2, 18, 22, 34, 401 35, 36, 37, 0, 4, 26, 402 27, 28, 29, 30, 31, 32, 403 33, 2, 19, 23, 34, 35, 404 36, 37, 63, 4, 26, 27, 405 28, 29, 30, 31, 32, 33, 406 2, 20, 24, 34, 35, 36, 407 37, 63, 4, 26, 27, 28, 408 29, 30, 31, 32, 33, 2, 409 21, 25, 34, 35, 36, 37, 410 63, 4}; 411 412 /* Cascade Mode TDM */ 413 /* 56064 option 1/2, 53401/53411 option 1/2 */ 414 uint32 gh_tdm_cascade[96] = { 415 2, 18, 26, 28, 30, 32, 416 3, 19, 26, 28, 30, 32, 417 4, 20, 26, 28, 30, 32, 418 5, 21, 26, 28, 30, 32, 419 6, 22, 26, 28, 30, 32, 420 7, 23, 26, 28, 30, 32, 421 8, 24, 26, 28, 30, 32, 422 9, 25, 26, 28, 30, 32, 423 10, 0, 26, 28, 30, 32, 424 11, 63, 26, 28, 30, 32, 425 12, 63, 26, 28, 30, 32, 426 13, 63, 26, 28, 30, 32, 427 14, 63, 26, 28, 30, 32, 428 15, 63, 26, 28, 30, 32, 429 16, 63, 26, 28, 30, 32, 430 17, 63, 26, 28, 30, 32 431 }; 432 /* cascade mode for 53401 op3 */ 433 uint32 gh_tdm_cascade_1[78] = { 434 26, 27, 28, 29, 2, 18, 435 26, 27, 28, 29, 3, 19, 436 26, 27, 28, 29, 4, 20, 437 26, 27, 28, 29, 5, 21, 438 26, 27, 28, 29, 6, 22, 439 26, 27, 28, 29, 7, 23, 440 26, 27, 28, 29, 8, 24, 441 26, 27, 28, 29, 9, 25, 442 26, 27, 28, 29, 30, 34, 443 26, 27, 28, 29, 31, 35, 444 26, 27, 28, 29, 32, 36, 445 26, 27, 28, 29, 33, 37, 446 26, 27, 28, 29, 0, 63 447 }; 448 /* 53456/53457 op1 op2*/ 449 uint32 gh_tdm_cascade_2p5[98] = { 450 26, 28, 30, 18, 22, 2, 451 32, 26, 28, 19, 23, 3, 452 30, 32, 26, 20, 24, 4, 453 28, 30, 32, 21, 25, 5, 454 26, 28, 30, 18, 22, 6, 455 32, 26, 28, 19, 23, 7, 456 30, 32, 26, 20, 24, 8, 457 28, 30, 32, 21, 25, 9, 458 26, 28, 30, 18, 22, 10, 459 32, 26, 28, 19, 23, 11, 460 30, 32, 26, 20, 24, 12, 461 28, 30, 32, 21, 25, 13, 462 26, 28, 30, 18, 22, 14, 463 32, 26, 28, 19, 23, 15, 464 30, 32, 26, 20, 24, 16, 465 28, 30, 32, 21, 25, 17, 466 0, 63, 467 }; 468 469 /* low port count - 10G embeded */ 470 /* 53402/53412 */ 471 uint32 gh_tdm_low_port_count_10g_embeded[36] = { 472 22, 23, 24, 25, 26, 27, 473 28, 29, 0, 22, 23, 24, 474 25, 26, 27, 28, 29, 63, 475 22, 23, 24, 25, 26, 27, 476 28, 29, 63, 22, 23, 24, 477 25, 26, 27, 28, 29, 63}; 478 479 /* mixed embeded -2.5G */ 480 /* 53408/53418 */ 481 uint32 gh_tdm_mixed_embeded_2p5g[28] = { 482 2, 18, 22, 26, 30, 34, 483 0, 3, 19, 23, 27, 31, 484 35, 63, 4, 20, 24, 28, 485 32, 36, 63, 5, 21, 25, 486 29, 33, 37, 63}; 487 488 /* mixed embeded - 10G */ 489 /* 56060 option 2 */ 490 uint32 gh_tdm_mixed_embeded_10g[68] = { 491 22, 23, 24, 25, 26, 27, 492 28, 29, 30, 31, 32, 33, 493 34, 35, 2, 18, 0, 22, 494 23, 24, 25, 26, 27, 28, 495 29, 30, 31, 32, 33, 34, 496 35, 2, 18, 63, 22, 23, 497 24, 25, 26, 27, 28, 29, 498 30, 31, 32, 33, 34, 35, 499 2, 18, 63, 22, 23, 24, 500 25, 26, 27, 28, 29, 30, 501 31, 32, 33, 34, 35, 2, 502 18, 63}; 503 /* 53403 */ 504 uint32 gh_tdm_mixed_embeded_53403[80] = { 505 18, 22, 2, 32, 34, 35, 506 36, 37, 19, 23, 2, 32, 507 34, 35, 36, 37, 20, 24, 508 2, 32, 34, 35, 36, 37, 509 21, 25, 2, 32, 34, 35, 510 36, 37, 26, 63, 2, 32, 511 34, 35, 36, 37, 27, 63, 512 2, 32, 34, 35, 36, 37, 513 28, 63, 2, 32, 34, 35, 514 36, 37, 29, 63, 2, 32, 515 34, 35, 36, 37, 30, 63, 516 2, 32, 34, 35, 36, 37, 517 0, 63, 2, 32, 34, 35, 518 36, 37}; 519 /* 53404 */ 520 uint32 gh_tdm_mixed_embeded_53404[36] = { 521 18, 22, 2, 26, 27, 28, 522 19, 23, 2, 26, 27, 28, 523 20, 24, 2, 26, 27, 28, 524 21, 25, 2, 26, 27, 28, 525 30, 63, 2, 26, 27, 28, 526 0, 63, 2, 26, 27, 28, 527 }; 528 /* 53406 option 2&3 */ 529 uint32 gh_tdm_mixed_embeded_53406_op2[68]={ 530 26, 27, 28, 29, 30, 31, 531 32, 33, 2, 18, 22, 34, 532 35, 36, 37, 0, 4, 26, 533 27, 28, 29, 30, 31, 32, 534 33, 2, 18, 22, 34, 35, 535 36, 37, 63, 4, 26, 27, 536 28, 29, 30, 31, 32, 33, 537 2, 18, 22, 34, 35, 36, 538 37, 63, 4, 26, 27, 28, 539 29, 30, 31, 32, 33, 2, 540 18, 22, 34, 35, 36, 37, 541 63, 4, 542 }; 543 /* 53406 option 4 */ 544 uint32 gh_tdm_mixed_embeded_53406_op4[101]={ 545 26, 27, 28, 29, 34, 35, 546 36, 37, 30, 31, 32, 33, 547 23, 24, 25, 26, 27, 28, 548 29, 34, 35, 36, 37, 30, 549 31, 32, 33, 23, 24, 25, 550 26, 27, 28, 29, 34, 35, 551 36, 37, 30, 31, 32, 33, 552 23, 24, 25, 26, 27, 28, 553 29, 34, 35, 36, 37, 30, 554 31, 32, 33, 23, 24, 25, 555 26, 27, 28, 29, 34, 2, 556 35, 36, 37, 30, 31, 3, 557 32, 33, 23, 24, 25, 4, 558 26, 27, 28, 29, 34, 5, 559 35, 36, 37, 30, 31, 18, 560 32, 33, 23, 24, 25, 22, 561 19, 20, 21, 0, 63 562 }; 563 564 /* 56062 */ 565 uint32 gh_tdm_mixed_embeded_56062[60]={ 566 34, 35, 18, 22, 26, 2, 567 36, 37, 19, 23, 27, 3, 568 34, 35, 20, 24, 28, 4, 569 36, 37, 21, 25, 29, 5, 570 0, 63, 30, 31, 32, 33, 571 34, 35, 18, 22, 26, 6, 572 36, 37, 19, 23, 27, 7, 573 34, 35, 20, 24, 28, 8, 574 36, 37, 21, 25, 29, 9, 575 63, 63, 30, 31, 32, 33, 576 }; 577 uint32 gh_tdm_mixed_embeded_56062_op2[58]={ 578 34, 35, 36, 37, 30, 2, 579 26, 18, 20, 22, 24, 3, 580 34, 35, 36, 37, 30, 4, 581 26, 18, 20, 22, 24, 5, 582 19, 21, 23, 25, 0, 63, 583 34, 35, 36, 37, 30, 6, 584 26, 18, 20, 22, 24, 7, 585 34, 35, 36, 37, 30, 8, 586 26, 18, 20, 22, 24, 9, 587 19, 21, 23, 25, 588 }; 589 /* Elkhound -53455 */ 590 /* 53454/53455/53456/53457 */ 591 uint32 gh_tdm_elkhound_53455[48]={ 592 26, 27, 18, 22, 2, 0, 593 28, 29, 30, 34, 3, 63, 594 26, 27, 19, 23, 4, 63, 595 28, 29, 31, 35, 5, 63, 596 26, 27, 20, 24, 6, 63, 597 28, 29, 32, 36, 7, 63, 598 26, 27, 21, 25, 8, 63, 599 28, 29, 33, 37, 9, 63, 600 }; 601 /* Bloodhound -53422 */ 602 /* 53422/53424/53426 */ 603 uint32 gh_tdm_bloodhound_53422[78]={ 604 26, 27, 28, 29, 18, 2, 605 26, 27, 28, 29, 19, 3, 606 26, 27, 28, 29, 20, 4, 607 26, 27, 28, 29, 21, 5, 608 26, 27, 28, 29, 22, 6, 609 26, 27, 28, 29, 23, 7, 610 26, 27, 28, 29, 24, 8, 611 26, 27, 28, 29, 25, 9, 612 26, 27, 28, 29, 30, 34, 613 26, 27, 28, 29, 31, 35, 614 26, 27, 28, 29, 32, 36, 615 26, 27, 28, 29, 33, 37, 616 26, 27, 28, 29, 0, 63, 617 }; 618 #define _GH_MAX_TSC_COUNT (6) 619 620 /* TSC lane mode */ 621 typedef enum _gh_tsc_lane_mode_e { 622 _GH_TSC_LANE_MODE_SINGLE = 0, 623 _GH_TSC_LANE_MODE_XAUI = 1, 624 _GH_TSC_LANE_MODE_RXAUI = 2, 625 _GH_TSC_LANE_MODE_RXAUI13G = 3, /* special mode for HG-Duo[13](RXAUI) */ 626 _GH_TSC_LANE_MODE_CNT 627 } _gh_tsc_lane_mode_t; 628 629 /* Flexible Lane Mode bitmap (special mode for HG-Duo[13] is not included */ 630 #define _GH_FLEX_LANE_MODE_SINGLE (1 << _GH_TSC_LANE_MODE_SINGLE) 631 #define _GH_FLEX_LANE_MODE_XAUI (1 << _GH_TSC_LANE_MODE_XAUI) 632 #define _GH_FLEX_LANE_MODE_RXAUI (1 << _GH_TSC_LANE_MODE_RXAUI) 633 634 #define _GH_FLEX_LANE_MODE_ALL \ 635 (_GH_FLEX_LANE_MODE_SINGLE | _GH_FLEX_LANE_MODE_XAUI | \ 636 _GH_FLEX_LANE_MODE_RXAUI) 637 638 #define _GH_FLEX_LANE_MODE_IS_SUPPORT(lane_mode_bmp, lane_mode) \ 639 (((lane_mode_bmp) != 0) && ((lane_mode) != -1) && \ 640 ((lane_mode_bmp) & (1 << (lane_mode)))) 641 642 #define _GH_ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) 643 #define _GH_MAX_LPORT_COUNT (24) 644 645 static soc_reg_t speed_limit_regs[_GH_MAX_LPORT_COUNT] = { 646 SPEED_LIMIT_ENTRY0_PHYSICAL_PORT_NUMBERr, 647 SPEED_LIMIT_ENTRY1_PHYSICAL_PORT_NUMBERr, 648 SPEED_LIMIT_ENTRY2_PHYSICAL_PORT_NUMBERr, 649 SPEED_LIMIT_ENTRY3_PHYSICAL_PORT_NUMBERr, 650 SPEED_LIMIT_ENTRY4_PHYSICAL_PORT_NUMBERr, 651 SPEED_LIMIT_ENTRY5_PHYSICAL_PORT_NUMBERr, 652 SPEED_LIMIT_ENTRY6_PHYSICAL_PORT_NUMBERr, 653 SPEED_LIMIT_ENTRY7_PHYSICAL_PORT_NUMBERr, 654 SPEED_LIMIT_ENTRY8_PHYSICAL_PORT_NUMBERr, 655 SPEED_LIMIT_ENTRY9_PHYSICAL_PORT_NUMBERr, 656 SPEED_LIMIT_ENTRY10_PHYSICAL_PORT_NUMBERr, 657 SPEED_LIMIT_ENTRY11_PHYSICAL_PORT_NUMBERr, 658 SPEED_LIMIT_ENTRY12_PHYSICAL_PORT_NUMBERr, 659 SPEED_LIMIT_ENTRY13_PHYSICAL_PORT_NUMBERr, 660 SPEED_LIMIT_ENTRY14_PHYSICAL_PORT_NUMBERr, 661 SPEED_LIMIT_ENTRY15_PHYSICAL_PORT_NUMBERr, 662 SPEED_LIMIT_ENTRY16_PHYSICAL_PORT_NUMBERr, 663 SPEED_LIMIT_ENTRY17_PHYSICAL_PORT_NUMBERr, 664 SPEED_LIMIT_ENTRY18_PHYSICAL_PORT_NUMBERr, 665 SPEED_LIMIT_ENTRY19_PHYSICAL_PORT_NUMBERr, 666 SPEED_LIMIT_ENTRY20_PHYSICAL_PORT_NUMBERr, 667 SPEED_LIMIT_ENTRY21_PHYSICAL_PORT_NUMBERr, 668 SPEED_LIMIT_ENTRY22_PHYSICAL_PORT_NUMBERr, 669 SPEED_LIMIT_ENTRY23_PHYSICAL_PORT_NUMBERr 670 }; 671 static const int lane_single_override[]={1, 1, 1, 1}; 672 static const int lane_rxaui_override[]={1, -1, 1, -1}; 673 static const int lane_xaui_override[]={1, -1, -1, -1}; 674 static const int lane_rxaui_speed_override[]={100, -1, 100, -1}; 675 static const int lane_xaui_speed_override[]={100, -1, -1, -1}; 676 static const int lane_disable_override[]={-1, -1, -1, -1}; 677 static const int tsc_phy_port[] = {18, 22, 26, 30, 34, 2}; 678 679 static int matched_devid_idx = -1; 680 static int _gh_port_config_id = -1; 681 682 typedef struct _gh_tsc_info_s { 683 int lane_mode; 684 uint8 valid; 685 int phy_port_base; 686 }_gh_tsc_info_t; 687 688 typedef struct _gh_sku_speed_limit_info_s { 689 uint16 dev_id; 690 int config_op; /* sku option */ 691 const int *phy_port_mapping; 692 }_gh_sku_speed_limit_info_t; 693 694 typedef struct _gh_sku_info_s { 695 uint16 dev_id; 696 int config_op; /* sku option */ 697 int dual_port_idx; /* 0/1:tsc5 is n/a or exist */ 698 const int *port_blk_type; /* tsc5 is gxport or xlport */ 699 const int *p2l_mapping; 700 const int *speed_max; 701 uint32 *tdm_table; 702 int tdm_table_size; 703 uint32 flex_tsc_bmp; /* 6 bits: [tsc5...tsc0] */ 704 uint32 disabled_tsc_bmp; 705 int default_lane_mode[_GH_MAX_TSC_COUNT]; 706 uint32 flex_lane_modes_bmp[_GH_MAX_TSC_COUNT]; 707 }_gh_sku_info_t; 708 709 static _gh_tsc_info_t _gh_tsc[_GH_MAX_TSC_COUNT]; 710 711 STATIC _gh_sku_speed_limit_info_t _gh_sku_speed_limit[] = { 712 {BCM56060_DEVICE_ID, 2, speed_limit_56060_op2}, 713 {BCM53406_DEVICE_ID, 2, speed_limit_53406_op2}, 714 {BCM53406_DEVICE_ID, 3, speed_limit_53406_op2}, 715 {BCM53406_DEVICE_ID, 4, speed_limit_53406_op4}, 716 {BCM53369_DEVICE_ID, 2, speed_limit_53406_op2}, 717 {BCM53369_DEVICE_ID, 3, speed_limit_53406_op2}, 718 {BCM53369_DEVICE_ID, 4, speed_limit_53406_op4}, 719 {BCM53369_DEVICE_ID, 5, speed_limit_53406_op4}, 720 {BCM53456_DEVICE_ID, 1, speed_limit_53456_op1}, 721 {BCM53456_DEVICE_ID, 2, speed_limit_53456_op1}, 722 {BCM53424_DEVICE_ID, 1, speed_limit_53456_op1}, 723 {BCM53424_DEVICE_ID, 2, speed_limit_53456_op1}, 724 {BCM53401_DEVICE_ID, 3, speed_limit_53401_op3}, 725 {0,0,0} 726 }; 727 728 STATIC _gh_sku_info_t _gh_sku_port_config[] = { 729 {BCM53401_DEVICE_ID, 1, 1, port_blk_gport, 730 p2l_mapping_cascade, port_speed_max_non_cascade, 731 gh_tdm_cascade, _GH_ARRAY_SIZE(gh_tdm_cascade), 732 0, 0x10, 733 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 734 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 735 -1, _GH_TSC_LANE_MODE_SINGLE}, 736 {0, 0, 0, 0, 0, 0}}, 737 {BCM53401_DEVICE_ID, 2, 1, port_blk_gport, 738 p2l_mapping_cascade, port_speed_max_cascade, 739 gh_tdm_cascade, _GH_ARRAY_SIZE(gh_tdm_cascade), 740 0, 0x10, 741 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 742 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_RXAUI13G, 743 -1, _GH_TSC_LANE_MODE_SINGLE}, 744 {0, 0, 0, 0, 0, 0}}, 745 {BCM53401_DEVICE_ID, 3, 1, port_blk_gport, 746 p2l_mapping_cascade_1, port_speed_max_cascade_1, 747 gh_tdm_cascade_1, _GH_ARRAY_SIZE(gh_tdm_cascade_1), 748 0, 0, 749 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 750 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 751 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 752 {0, 0, 0, 0, 0, 0}}, 753 {BCM53402_DEVICE_ID, -1, 0, NULL, 754 p2l_mapping_embedded_8x10g, port_speed_max_embedded_8x10g, 755 gh_tdm_low_port_count_10g_embeded, _GH_ARRAY_SIZE(gh_tdm_low_port_count_10g_embeded), 756 0x6, 0x39, 757 {-1, _GH_TSC_LANE_MODE_SINGLE, 758 _GH_TSC_LANE_MODE_SINGLE, -1, 759 -1, -1}, 760 {0, _GH_FLEX_LANE_MODE_ALL, 761 _GH_FLEX_LANE_MODE_ALL, 0, 762 0, 0}}, 763 {BCM53403_DEVICE_ID, -1, 1, port_blk_xlport, 764 p2l_mapping_53403, port_speed_max_53403, 765 gh_tdm_mixed_embeded_53403, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53403), 766 0, 0, 767 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 768 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 769 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_XAUI}, 770 {0, 0, 0, 0, 0, 0}}, 771 {BCM53404_DEVICE_ID, 1, 1, port_blk_xlport, 772 p2l_mapping_53404, port_speed_max_53404_op1, 773 gh_tdm_mixed_embeded_53404, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53404), 774 0, 0x10, 775 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 776 _GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_SINGLE, 777 -1, _GH_TSC_LANE_MODE_XAUI}, 778 {0, 0, 0, 0, 0, 0}}, 779 {BCM53404_DEVICE_ID, 2, 1, port_blk_xlport, 780 p2l_mapping_53404, port_speed_max_53404_op2, 781 gh_tdm_mixed_embeded_53404, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53404), 782 0, 0x18, 783 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 784 _GH_TSC_LANE_MODE_SINGLE, -1, 785 -1, _GH_TSC_LANE_MODE_XAUI}, 786 {0, 0, 0, 0, 0, 0}}, 787 {BCM53405_DEVICE_ID, -1, 0, NULL, 788 p2l_mapping_embedded_16x10g, port_speed_max_embedded_16x10g, 789 gh_tdm_10g_embedded, _GH_ARRAY_SIZE(gh_tdm_10g_embedded), 790 0x1e, 0x21, 791 {-1, _GH_TSC_LANE_MODE_SINGLE, 792 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 793 _GH_TSC_LANE_MODE_SINGLE, -1}, 794 {0, _GH_FLEX_LANE_MODE_ALL, 795 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 796 _GH_FLEX_LANE_MODE_ALL, 0}}, 797 {BCM53365_DEVICE_ID, -1, 0, NULL, 798 p2l_mapping_embedded_16x10g, port_speed_max_embedded_16x10g, 799 gh_tdm_10g_embedded, _GH_ARRAY_SIZE(gh_tdm_10g_embedded), 800 0x1e, 0x21, 801 {-1, _GH_TSC_LANE_MODE_SINGLE, 802 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 803 _GH_TSC_LANE_MODE_SINGLE, -1}, 804 {0, _GH_FLEX_LANE_MODE_ALL, 805 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 806 _GH_FLEX_LANE_MODE_ALL, 0}}, 807 {BCM53406_DEVICE_ID, 1, 1, port_blk_xlport, 808 p2l_mapping_mixed_embeded, port_speed_max_mixed_embeded, 809 gh_tdm_mixed_embeded_4x5g, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_4x5g), 810 0x3c, 0, 811 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 812 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 813 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 814 {0, 0, 815 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 816 _GH_FLEX_LANE_MODE_ALL, (_GH_FLEX_LANE_MODE_SINGLE | _GH_FLEX_LANE_MODE_XAUI)}}, 817 {BCM53406_DEVICE_ID, 2, 1, port_blk_xlport, 818 p2l_mapping_53406_op2, port_speed_max_53406_op2, 819 gh_tdm_mixed_embeded_53406_op2, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53406_op2), 820 0x18, 0, 821 {_GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_XAUI, 822 _GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_SINGLE, 823 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_XAUI}, 824 {0, 0, 0, _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 0}}, 825 {BCM53406_DEVICE_ID, 3, 1, port_blk_xlport, 826 p2l_mapping_53406_op2, port_speed_max_53406_op2, 827 gh_tdm_mixed_embeded_53406_op2, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53406_op2), 828 0, 0x10, 829 {_GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_XAUI, 830 _GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_SINGLE, 831 -1, _GH_TSC_LANE_MODE_XAUI}, 832 {0, 0, 0, 0, 0, 0}}, 833 {BCM53406_DEVICE_ID, 4, 1, port_blk_xlport, 834 p2l_mapping_mixed_embeded, port_speed_max_53406_op4, 835 gh_tdm_mixed_embeded_53406_op4, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53406_op4), 836 0x1c, 0, 837 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 838 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 839 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 840 {0, 0, 841 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 842 _GH_FLEX_LANE_MODE_ALL, 0}}, 843 {BCM53369_DEVICE_ID, 1, 1, port_blk_xlport, 844 p2l_mapping_mixed_embeded, port_speed_max_mixed_embeded, 845 gh_tdm_mixed_embeded_4x5g, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_4x5g), 846 0x3c, 0, 847 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 848 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 849 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 850 {0, 0, 851 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 852 _GH_FLEX_LANE_MODE_ALL, (_GH_FLEX_LANE_MODE_SINGLE | _GH_FLEX_LANE_MODE_XAUI)}}, 853 {BCM53369_DEVICE_ID, 2, 1, port_blk_xlport, 854 p2l_mapping_53406_op2, port_speed_max_53406_op2, 855 gh_tdm_mixed_embeded_53406_op2, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53406_op2), 856 0x18, 0, 857 {_GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_XAUI, 858 _GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_SINGLE, 859 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_XAUI}, 860 {0, 0, 0, _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 0}}, 861 {BCM53369_DEVICE_ID, 3, 1, port_blk_xlport, 862 p2l_mapping_53406_op2, port_speed_max_53406_op2, 863 gh_tdm_mixed_embeded_53406_op2, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53406_op2), 864 0, 0x10, 865 {_GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_XAUI, 866 _GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_SINGLE, 867 -1, _GH_TSC_LANE_MODE_XAUI}, 868 {0, 0, 0, 0, 0, 0}}, 869 {BCM53369_DEVICE_ID, 4, 1, port_blk_xlport, 870 p2l_mapping_mixed_embeded, port_speed_max_53406_op4, 871 gh_tdm_mixed_embeded_53406_op4, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_53406_op4), 872 0x1c, 0, 873 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 874 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 875 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 876 {0, 0, 877 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 878 _GH_FLEX_LANE_MODE_ALL, 0}}, 879 {BCM53369_DEVICE_ID, 5, 0, NULL, 880 p2l_mapping_embedded_16x10g, port_speed_max_embedded_16x10g, 881 gh_tdm_10g_embedded, _GH_ARRAY_SIZE(gh_tdm_10g_embedded), 882 0x1e, 0x21, 883 {-1, _GH_TSC_LANE_MODE_SINGLE, 884 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 885 _GH_TSC_LANE_MODE_SINGLE, -1}, 886 {0, _GH_FLEX_LANE_MODE_ALL, 887 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 888 _GH_FLEX_LANE_MODE_ALL, 0}}, 889 {BCM53408_DEVICE_ID, -1, 1, port_blk_xlport, 890 p2l_mapping_mixed_embeded, port_speed_max_mixed_embeded_24x2p5, 891 gh_tdm_mixed_embeded_2p5g, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_2p5g), 892 0, 0, 893 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 894 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 895 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 896 {0, 0, 0, 0, 0, 0}}, 897 {BCM56060_DEVICE_ID, 1, 0, NULL, 898 p2l_mapping_embedded_16x10g, port_speed_max_embedded_16x10g, 899 gh_tdm_10g_embedded, _GH_ARRAY_SIZE(gh_tdm_10g_embedded), 900 0x4, 0x21, 901 {-1, _GH_TSC_LANE_MODE_SINGLE, 902 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 903 _GH_TSC_LANE_MODE_SINGLE, -1}, 904 {0, 0, _GH_FLEX_LANE_MODE_ALL, 0, 0, 0}}, 905 {BCM56060_DEVICE_ID, 2, 1, port_blk_xlport, 906 p2l_mapping_mixed_embeded_16x10g, port_speed_max_mixed_embeded_16x10g, 907 gh_tdm_mixed_embeded_10g, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_10g), 908 0x4, 0, 909 {_GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_SINGLE, 910 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 911 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_XAUI}, 912 {0, 0, _GH_FLEX_LANE_MODE_ALL, 0, 0, 0}}, 913 {BCM56062_DEVICE_ID, 1, 1, port_blk_gport, 914 p2l_mapping_cascade_1, port_speed_max_56062_op1, 915 gh_tdm_mixed_embeded_56062, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_56062), 916 0, 0, 917 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 918 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 919 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 920 {0, 0, 0, 0, 0, 0}}, 921 {BCM56062_DEVICE_ID, 2, 1, port_blk_gport, 922 p2l_mapping_cascade_1, port_speed_max_56062_op2, 923 gh_tdm_mixed_embeded_56062_op2, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_56062_op2), 924 0x3, 0, 925 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 926 _GH_TSC_LANE_MODE_XAUI, _GH_TSC_LANE_MODE_XAUI, 927 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 928 {(_GH_FLEX_LANE_MODE_SINGLE | _GH_FLEX_LANE_MODE_RXAUI), 929 (_GH_FLEX_LANE_MODE_SINGLE | _GH_FLEX_LANE_MODE_RXAUI), 930 0, 0, 931 0, 0}}, 932 {BCM56062_DEVICE_ID, 3, 1, port_blk_gport, 933 p2l_mapping_cascade_1, port_speed_max_53456, 934 gh_tdm_elkhound_53455, _GH_ARRAY_SIZE(gh_tdm_elkhound_53455), 935 0x4, 0, 936 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 937 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 938 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 939 {0, 0, _GH_FLEX_LANE_MODE_ALL, 0, 0, 0}}, 940 {BCM56063_DEVICE_ID, -1, 1, port_blk_gport, 941 p2l_mapping_cascade, port_speed_max_non_cascade, 942 gh_tdm_cascade, _GH_ARRAY_SIZE(gh_tdm_cascade), 943 0, 0x13, 944 {-1, -1, 945 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 946 -1, _GH_TSC_LANE_MODE_SINGLE}, 947 {0, 0, 0, 0, 0, 0}}, 948 {BCM56064_DEVICE_ID, 1, 1, port_blk_gport, 949 p2l_mapping_cascade, port_speed_max_non_cascade, 950 gh_tdm_cascade, _GH_ARRAY_SIZE(gh_tdm_cascade), 951 0, 0x10, 952 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 953 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 954 -1, _GH_TSC_LANE_MODE_SINGLE}, 955 {0, 0, 0, 0, 0, 0}}, 956 {BCM56064_DEVICE_ID, 2, 1, port_blk_gport, 957 p2l_mapping_cascade, port_speed_max_cascade, 958 gh_tdm_cascade, _GH_ARRAY_SIZE(gh_tdm_cascade), 959 0, 0x10, 960 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 961 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_RXAUI13G, 962 -1, _GH_TSC_LANE_MODE_SINGLE}}, 963 {BCM56065_DEVICE_ID, -1, 1, port_blk_xlport, 964 p2l_mapping_mixed_embeded, port_speed_max_mixed_embeded, 965 gh_tdm_mixed_embeded_4x5g, _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_4x5g), 966 0x3c, 0, 967 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 968 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 969 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 970 {0, 0, 971 _GH_FLEX_LANE_MODE_ALL, _GH_FLEX_LANE_MODE_ALL, 972 _GH_FLEX_LANE_MODE_ALL, (_GH_FLEX_LANE_MODE_SINGLE | _GH_FLEX_LANE_MODE_XAUI)}}, 973 {BCM56066_DEVICE_ID, -1, 0, NULL, 974 p2l_mapping_cascade_1, port_speed_max_56066, 975 gh_tdm_bloodhound_53422, _GH_ARRAY_SIZE(gh_tdm_bloodhound_53422), 976 0x4, 0x20, 977 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 978 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 979 _GH_TSC_LANE_MODE_SINGLE, -1}, 980 {0, 0, 981 (_GH_FLEX_LANE_MODE_SINGLE | _GH_FLEX_LANE_MODE_XAUI), 0, 0, 0}}, 982 {BCM53454_DEVICE_ID, -1, 1, port_blk_xlport, 983 p2l_mapping_cascade_1, port_speed_max_53454, 984 gh_tdm_elkhound_53455, _GH_ARRAY_SIZE(gh_tdm_elkhound_53455), 985 0x4, 0, 986 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 987 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 988 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 989 {0, 0, _GH_FLEX_LANE_MODE_ALL, 0, 0, 0}}, 990 {BCM53456_DEVICE_ID, 1, 1, port_blk_gport, 991 p2l_mapping_cascade, port_speed_max_non_cascade_2p5, 992 gh_tdm_cascade_2p5, _GH_ARRAY_SIZE(gh_tdm_cascade_2p5), 993 0, 0x10, 994 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 995 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 996 -1, _GH_TSC_LANE_MODE_SINGLE}, 997 {0, 0, 0, 0, 0, 0}}, 998 {BCM53456_DEVICE_ID, 2, 1, port_blk_gport, 999 p2l_mapping_cascade, port_speed_max_cascade_2p5, 1000 gh_tdm_cascade_2p5, _GH_ARRAY_SIZE(gh_tdm_cascade_2p5), 1001 0, 0x10, 1002 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1003 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_RXAUI13G, 1004 -1, _GH_TSC_LANE_MODE_SINGLE}, 1005 {0, 0, 0, 0, 0, 0}}, 1006 {BCM53456_DEVICE_ID, 3, 1, port_blk_gport, 1007 p2l_mapping_cascade_1, port_speed_max_53456, 1008 gh_tdm_elkhound_53455, _GH_ARRAY_SIZE(gh_tdm_elkhound_53455), 1009 0x4, 0, 1010 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1011 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1012 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 1013 {0, 0, _GH_FLEX_LANE_MODE_ALL, 0, 0, 0}}, 1014 {BCM53422_DEVICE_ID, -1, 0, NULL, 1015 p2l_mapping_cascade_1, port_speed_max_53422, 1016 gh_tdm_bloodhound_53422, _GH_ARRAY_SIZE(gh_tdm_bloodhound_53422), 1017 0, 0x38, 1018 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1019 _GH_TSC_LANE_MODE_SINGLE, -1, 1020 -1, -1}, 1021 {0, 0, 0, 0, 0, 0}}, 1022 {BCM53424_DEVICE_ID, 1, 1, port_blk_gport, 1023 p2l_mapping_cascade, port_speed_max_non_cascade, 1024 gh_tdm_cascade, _GH_ARRAY_SIZE(gh_tdm_cascade), 1025 0, 0x10, 1026 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1027 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1028 -1, _GH_TSC_LANE_MODE_SINGLE}, 1029 {0, 0, 0, 0, 0, 0}}, 1030 {BCM53424_DEVICE_ID, 2, 1, port_blk_gport, 1031 p2l_mapping_cascade, port_speed_max_cascade, 1032 gh_tdm_cascade, _GH_ARRAY_SIZE(gh_tdm_cascade), 1033 0, 0x10, 1034 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1035 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_RXAUI13G, 1036 -1, _GH_TSC_LANE_MODE_SINGLE}, 1037 {0, 0, 0, 0, 0, 0}}, 1038 {BCM53424_DEVICE_ID, 3, 1, port_blk_gport, 1039 p2l_mapping_cascade_1, port_speed_max_53424, 1040 gh_tdm_bloodhound_53422, _GH_ARRAY_SIZE(gh_tdm_bloodhound_53422), 1041 0x4, 0, 1042 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1043 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1044 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 1045 {0, 0, _GH_FLEX_LANE_MODE_ALL, 0, 0, 0}}, 1046 {BCM53426_DEVICE_ID, -1, 1, port_blk_xlport, 1047 p2l_mapping_cascade_1, port_speed_max_53426, 1048 gh_tdm_bloodhound_53422, _GH_ARRAY_SIZE(gh_tdm_bloodhound_53422), 1049 0x4, 0, 1050 {_GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1051 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE, 1052 _GH_TSC_LANE_MODE_SINGLE, _GH_TSC_LANE_MODE_SINGLE}, 1053 {0, 0, _GH_FLEX_LANE_MODE_ALL, 0, 0, 0}}, 1054 {0,0,0,0,0,0,0,0,0,0,{-1,-1,-1,-1,-1,-1},{0, 0, 0, 0, 0, 0}}, 1055 }; 1056 1057 /* MMU related */ 1058 /* Greyhound uses 2MB/1MB of internal Buffers */ 1059 #define GH_MMU_BUFFER_SIZE_2MB (2 * 1024 * 1024) 1060 #define GH_MMU_BUFFER_SIZE_1MB (1 * 1024 * 1024) 1061 1062 /* 24GE + 4HG +1CPU ports */ 1063 #define GH_MMU_TOTAL_PORTS 29 1064 1065 #define GH_MMU_NUM_COS 8 1066 #define GH_MMU_CELL_SIZE 128 1067 1068 1069 #define GH_MMU_IN_COS_MIN_CELLS 16 1070 #define GH_MMU_IN_COS_MIN_XQS 16 1071 1072 /* cos(8) * reserved cells */ 1073 #define GH_MMU_IN_PORT_STATIC_CELLS (GH_MMU_NUM_COS * GH_MMU_IN_COS_MIN_CELLS) 1074 1075 /* Every port has 6K packet pointers(XQs) */ 1076 #define GH_MMU_IN_PORT_TOTAL_XQS 6144 1077 /* number of cos(8) * minimum xqs per cos */ 1078 #define GH_MMU_IN_PORT_STATIC_XQS (GH_MMU_NUM_COS * GH_MMU_IN_COS_MIN_XQS) 1079 /* total xqs (8192)- static xqs */ 1080 #define GH_MMU_IN_PORT_DYNAMIC_XQS (GH_MMU_IN_PORT_TOTAL_XQS - GH_MMU_IN_PORT_STATIC_XQS) 1081 1082 /* SER related */ 1083 #define GREYHOUND_SER_PARITY_ENABLED (1) 1084 #define GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED (0) 1085 1086 /* EEE reference count related : 1087 * - The clock devider to generate ~1us reference pulses used by EEE timers. 1088 * - It is normally chip independent and should be delivered by chip team. 1089 * 1090 * GH's EEE_REF_COUNT : 1091 * 1. XLMAC : 'TSC_CLK' is the reference clock. 1092 * 2. UNIMAC : 'TS_CLK' is the reference clock. 1093 */ 1094 #define GH_TSC_CLK 645 /* for 644.531 MHz */ 1095 #define GH_TS_CLK 250 /* for 250 MHz */ 1096 #define GH_XLMAC_EEE_REF_CNT GH_TSC_CLK 1097 #define GH_UNIMAC_EEE_REF_CNT GH_TS_CLK 1098 1099 typedef enum { 1100 _SOC_PARITY_INFO_TYPE_GENERIC, 1101 _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1102 _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1103 _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 1104 _SOC_PARITY_INFO_TYPE_COUNTER, 1105 _SOC_PARITY_INFO_TYPE_MMU_ECC, 1106 _SOC_PARITY_INFO_TYPE_MMU_XQ, 1107 _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 1108 _SOC_PARITY_INFO_TYPE_MMU_IPMCVLAN, 1109 _SOC_PARITY_INFO_TYPE_MMU_WRED, 1110 _SOC_PARITY_INFO_TYPE_MMU_E2EFC, 1111 _SOC_PARITY_INFO_TYPE_MMU_CBPPKTHDR, 1112 _SOC_PARITY_INFO_TYPE_PORT_MACRO, 1113 _SOC_PARITY_INFO_TYPE_OAM, /* Not parity, but same interrupt */ 1114 _SOC_PARITY_INFO_TYPE_NUM 1115 } _soc_parity_info_type_t; 1116 1117 #define _GH_SER_F_L3 0x1 1118 1119 typedef struct _soc_parity_info_s { 1120 soc_field_t enable_field; 1121 soc_field_t error_field; 1122 char *msg; 1123 soc_mem_t mem; 1124 _soc_parity_info_type_t type; 1125 soc_reg_t control_reg; 1126 soc_reg_t intr_status0_reg; 1127 soc_reg_t intr_status1_reg; /* Also SBE force for ECC */ 1128 soc_reg_t nack_status0_reg; 1129 soc_reg_t nack_status1_reg; /* Also DBE force for ECC */ 1130 soc_field_t clear_field; /* For level 1 */ 1131 soc_reg_t level2_error_reg; /* For MMU level 2 */ 1132 soc_reg_t level2_error_vld_reg; 1133 soc_reg_t level2_error_multi_reg; 1134 soc_reg_t level2_error_clear_reg; 1135 uint32 feature; 1136 } _soc_gh_parity_info_t; 1137 1138 /* 1139 * _SOC_PARITY_INFO_TYPE_SINGLE_PARITY 1140 * PARITY_EN 1141 * ENTRY_IDX, MULTIPLE_ERR, PARITY_ERR 1142 * 1143 * _SOC_PARITY_INFO_TYPE_SINGLE_ECC 1144 * ECC_EN 1145 * ENTRY_IDX, DOUBLE_BIT_ERR, MULTIPLE_ERR, ECC_ERR 1146 * 1147 * _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER 1148 * PARITY_EN 1149 * PORT_IDX, COUNTER_IDX, MULTIPLE_ERR, PARITY_ERR 1150 * 1151 * _SOC_PARITY_INFO_TYPE_DUAL_PARITY 1152 * PARITY_EN 1153 * BUCKET_IDX, MULTIPLE_ERR, PARITY_ERR_BM 1154 */ 1155 1156 STATIC _soc_gh_parity_info_t _soc_rg2_ip0_parity_info[] = { 1157 { PARITY_ENf, VFP_POLICY_PAR_ERRf, "VFP_POLICY table parity error", 1158 VFP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1159 VFP_POLICY_PARITY_CONTROLr, 1160 VFP_POLICY_PARITY_STATUS_INTRr, INVALIDr, 1161 INVALIDr, INVALIDr }, 1162 { INVALIDf, INVALIDf }, /* table terminator */ 1163 }; 1164 1165 STATIC _soc_gh_parity_info_t _soc_gh_ip0_parity_info[] = { 1166 /* { PARITY_ENf, VXLT_PAR_ERRf,"VLAN_XLATE table parity error", 1167 VLAN_XLATEm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 1168 VLAN_XLATE_PARITY_CONTROLr, 1169 VLAN_XLATE_PARITY_STATUS_0r, VLAN_XLATE_PARITY_STATUS_1r, 1170 INVALIDr, INVALIDr }, */ 1171 /* { PPA_CMD_COMPLETEf }, */ 1172 /* { MEM_RESET_COMPLETEf }, */ 1173 /* { AGE_CMD_COMPLETEf }, */ 1174 { PARITY_ENf, VLAN_SUBNET_DATA_PARITY_ERRf, "VLAN_SUBNET_DATA table parity error", 1175 VLAN_SUBNET_DATA_ONLYm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1176 VLAN_SUBNET_DATA_PARITY_CONTROLr, 1177 VLAN_SUBNET_DATA_PARITY_STATUSr, INVALIDr, 1178 INVALIDr, INVALIDr }, 1179 { PARITY_ENf, VLAN_PROTOCOL_DATA_PARITY_ERRf, "VLAN_PROTOCOL_DATA table parity error", 1180 VLAN_PROTOCOL_DATAm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1181 VLAN_PROTOCOL_DATA_PARITY_CONTROLr, 1182 VLAN_PROTOCOL_DATA_PARITY_STATUSr, INVALIDr, 1183 INVALIDr, INVALIDr }, 1184 { PARITY_ENf, VLAN_PARITY_ERRf, "VLAN table parity error", 1185 VLAN_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1186 VLAN_PARITY_CONTROLr, 1187 VLAN_PARITY_STATUSr, INVALIDr, 1188 INVALIDr, INVALIDr }, 1189 { PARITY_ENf, VLAN_STG_PARITY_ERRf, "VLAN_STG table parity error", 1190 STG_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1191 VLAN_STG_PARITY_CONTROLr, 1192 VLAN_STG_PARITY_STATUSr, INVALIDr, 1193 INVALIDr, INVALIDr }, 1194 /* { L3_TUNNEL_RAM_PARITY_ERRf }, */ 1195 { PARITY_ENf, SOURCE_TRUNK_MAP_PARITY_ERRf, "SOURCE_TRUNK_MAP table parity error", 1196 SOURCE_TRUNK_MAP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1197 SOURCE_TRUNK_MAP_PARITY_CONTROLr, 1198 SOURCE_TRUNK_MAP_PARITY_STATUSr, INVALIDr, 1199 INVALIDr, INVALIDr }, 1200 /* { PARITY_ENf, VFP_POLICY_PAR_ERRf, "VFP_POLICY table parity error", 1201 VFP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1202 VFP_POLICY_PARITY_CONTROLr, 1203 VFP_POLICY_PARITY_STATUS_INTRr, INVALIDr, 1204 INVALIDr, INVALIDr }, */ 1205 { PARITY_ENf, LMEP_PAR_ERRf, "LMEP table parity error", 1206 LMEPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1207 LMEP_PARITY_CONTROLr, 1208 LMEP_PARITY_STATUSr, INVALIDr, 1209 INVALIDr, INVALIDr }, 1210 { PARITY_ENf, LMEP_DA_PAR_ERRf, "LMEP_DA table parity error", 1211 LMEP_DAm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1212 LMEP_DA_PARITY_CONTROLr, 1213 LMEP_DA_PARITY_STATUSr, INVALIDr, 1214 INVALIDr, INVALIDr }, 1215 /* { IARB_PKT_ECC_INTR} */ 1216 { ECC_ENf, IARB_PKT_ECC_INTRf, "Iarb packet ecc error", 1217 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1218 IARB_PKT_ECC_CONTROLr, 1219 IARB_PKT_ECC_STATUS_INTRr, INVALIDr, 1220 INVALIDr, INVALIDr }, 1221 /* {PORT_TABLE_1BIT_ERR_INTR} */ 1222 { ECC_ENf, PORT_TABLE_ECC_INTRf, "PORT table ecc error", 1223 PORT_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1224 PORT_TABLE_ECC_CONTROLr, 1225 PORT_TABLE_ECC_STATUS_INTRr, INVALIDr, 1226 INVALIDr, INVALIDr }, 1227 { PARITY_ENf, SYSTEM_CONFIG_PAR_ERRf, "SYSTEM_CONFIG table error", 1228 SYSTEM_CONFIG_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1229 SYSTEM_CONFIG_TABLE_PARITY_CONTROLr, 1230 SYSTEM_CONFIG_TABLE_PARITY_STATUSr, INVALIDr, 1231 INVALIDr, INVALIDr }, 1232 { PARITY_ENf, UDF_OFFSET_PAR_ERRf, "UDF_OFFSET table error", 1233 FP_UDF_OFFSETm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1234 UDF_OFFSET_PARITY_CONTROLr, 1235 UDF_OFFSET_PARITY_STATUSr, INVALIDr, 1236 INVALIDr, INVALIDr }, 1237 { PARITY_ENf, ING_MOD_MAP_PAR_ERRf, "ING_MOD_MAP table error", 1238 ING_MOD_MAP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1239 ING_MOD_MAP_PARITY_CONTROLr, 1240 ING_MOD_MAP_PARITY_STATUSr, INVALIDr, 1241 INVALIDr, INVALIDr }, 1242 /* {LPORT_TABLE_1BIT_ERR_INTR} */ 1243 { ECC_ENf, LPORT_TABLE_ECC_INTRf, "LPORT table error", 1244 LPORT_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1245 LPORT_TABLE_ECC_CONTROLr, 1246 LPORT_TABLE_ECC_STATUS_INTRr, INVALIDr, 1247 INVALIDr, INVALIDr }, 1248 { PARITY_ENf, ING_ETAG_PCP_MAPPING_PAR_ERRf, "ING_ETAG_PCP_MAPPING table error", 1249 ING_ETAG_PCP_MAPPINGm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1250 ING_ETAG_PCP_MAPPING_PARITY_CONTROLr, 1251 ING_ETAG_PCP_MAPPING_PARITY_STATUSr, INVALIDr, 1252 INVALIDr, INVALIDr }, 1253 { INVALIDf, INVALIDf }, /* table terminator */ 1254 }; 1255 1256 STATIC _soc_gh_parity_info_t _soc_rg2_ip1_parity_info[] = { 1257 { PARITY_ENf, INITIAL_L3_ECMP_GROUP_PAR_ERRf, 1258 "INITIAL_L3_ECMP_GROUP table parity error", 1259 INITIAL_L3_ECMP_GROUPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1260 INITIAL_L3_ECMP_GROUP_PARITY_CONTROLr, 1261 INITIAL_L3_ECMP_GROUP_PARITY_STATUSr, INVALIDr, 1262 INVALIDr, INVALIDr }, 1263 { PARITY_ENf, INITIAL_L3_ECMP_PAR_ERRf, "INITIAL_L3_ECMP table parity error", 1264 INITIAL_L3_ECMPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1265 INITIAL_L3_ECMP_PARITY_CONTROLr, 1266 INITIAL_L3_ECMP_PARITY_STATUSr, INVALIDr, 1267 INVALIDr, INVALIDr }, 1268 { INVALIDf, INVALIDf }, /* table terminator */ 1269 }; 1270 1271 1272 STATIC _soc_gh_parity_info_t _soc_gh_ip1_parity_info[] = { 1273 /* { VFI_PAR_ERRf, }, */ 1274 /* { SVP_PAR_ERRf, }, */ 1275 /* { L3_IIF_PAR_ERRf, }, */ 1276 /* { MPLS_ENTRY_PAR_ERRf, }, */ 1277 { PARITY_ENf, L2_ENTRY_PAR_ERRf, "L2_ENTRY table parity error", 1278 L2Xm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 1279 L2_ENTRY_PARITY_CONTROLr, 1280 L2_ENTRY_PARITY_STATUS_0r, L2_ENTRY_PARITY_STATUS_1r, 1281 INVALIDr, INVALIDr }, 1282 { PARITY_ENf, L2MC_PAR_ERRf, "L2MC table parity error", 1283 L2MCm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1284 L2MC_PARITY_CONTROLr, 1285 L2MC_PARITY_STATUSr, INVALIDr, 1286 INVALIDr, INVALIDr }, 1287 { PARITY_ENf, L3_ENTRY_PAR_ERRf, "L3_ENTRY table parity error", 1288 L3_ENTRY_ONLYm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 1289 L3_ENTRY_PARITY_CONTROLr, 1290 L3_ENTRY_PARITY_STATUS_0r, L3_ENTRY_PARITY_STATUS_1r, 1291 INVALIDr, INVALIDr, 1292 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1293 _GH_SER_F_L3}, 1294 { PARITY_ENf, L3_DEFIP_DATA_PAR_ERRf, "L3_DEFIP_DATA_ONLY table parity error", 1295 L3_DEFIP_DATA_ONLYm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1296 L3_DEFIP_PARITY_CONTROLr, 1297 L3_DEFIP_PARITY_STATUSr, INVALIDr, 1298 INVALIDr, INVALIDr, 1299 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1300 _GH_SER_F_L3}, 1301 { PARITY_ENf, L3MC_PAR_ERRf, "L3MC table parity error", 1302 L3_IPMCm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1303 L3MC_PARITY_CONTROLr, 1304 L3MC_PARITY_STATUSr, INVALIDr, 1305 INVALIDr, INVALIDr, 1306 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1307 _GH_SER_F_L3}, 1308 { PARITY_ENf, MA_STATE_PAR_ERRf, "MA_STATE table parity error", 1309 MA_STATEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1310 MA_STATE_PARITY_CONTROLr, 1311 MA_STATE_PARITY_STATUSr, INVALIDr, 1312 INVALIDr, INVALIDr }, 1313 { PARITY_ENf, RMEP_PAR_ERRf, "RMEP table parity error", 1314 RMEPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1315 RMEP_PARITY_CONTROLr, 1316 RMEP_PARITY_STATUSr, INVALIDr, 1317 INVALIDr, INVALIDr }, 1318 { PARITY_ENf, MAID_REDUCTION_PAR_ERRf, "MAID_REDUCTION table parity error", 1319 MAID_REDUCTIONm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1320 MAID_REDUCTION_PARITY_CONTROLr, 1321 MAID_REDUCTION_PARITY_STATUSr, INVALIDr, 1322 INVALIDr, INVALIDr }, 1323 { PARITY_ENf, MA_INDEX_PAR_ERRf, "MA_INDEX table parity error", 1324 MA_INDEXm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1325 MA_INDEX_PARITY_CONTROLr, 1326 MA_INDEX_PARITY_STATUSr, INVALIDr, 1327 INVALIDr, INVALIDr }, 1328 /* { PORT_CBL_TABLE_PAR_ERRf, }, */ 1329 { PARITY_ENf, INITIAL_NHOP_PAR_ERRf, "INITIAL_NHOP table parity error", 1330 INITIAL_ING_L3_NEXT_HOPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1331 INITIAL_NHOP_PARITY_CONTROLr, 1332 INITIAL_NHOP_PARITY_STATUSr, INVALIDr, 1333 INVALIDr, INVALIDr, 1334 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1335 _GH_SER_F_L3}, 1336 /* Start of parity-unrelated OAM faults */ 1337 1338 { ANY_RMEP_TLV_PORT_DOWN_INTRf, ANY_RMEP_TLV_PORT_DOWN_INTRf, NULL, 1339 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1340 INVALIDr, 1341 INVALIDr, INVALIDr, 1342 INVALIDr, INVALIDr }, 1343 1344 { ANY_RMEP_TLV_PORT_UP_INTRf, ANY_RMEP_TLV_PORT_UP_INTRf, NULL, 1345 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1346 INVALIDr, 1347 INVALIDr, INVALIDr, 1348 INVALIDr, INVALIDr }, 1349 1350 { ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, NULL, 1351 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1352 INVALIDr, 1353 INVALIDr, INVALIDr, 1354 INVALIDr, INVALIDr }, 1355 1356 { ANY_RMEP_TLV_INTERFACE_UP_INTRf, ANY_RMEP_TLV_INTERFACE_UP_INTRf, NULL, 1357 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1358 INVALIDr, 1359 INVALIDr, INVALIDr, 1360 INVALIDr, INVALIDr }, 1361 1362 { XCON_CCM_DEFECT_INTRf, XCON_CCM_DEFECT_INTRf, NULL, 1363 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1364 INVALIDr, 1365 INVALIDr, INVALIDr, 1366 INVALIDr, INVALIDr }, 1367 1368 { ERROR_CCM_DEFECT_INTRf, ERROR_CCM_DEFECT_INTRf, NULL, 1369 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1370 INVALIDr, 1371 INVALIDr, INVALIDr, 1372 INVALIDr, INVALIDr }, 1373 1374 { SOME_RDI_DEFECT_INTRf, SOME_RDI_DEFECT_INTRf, NULL, 1375 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1376 INVALIDr, 1377 INVALIDr, INVALIDr, 1378 INVALIDr, INVALIDr }, 1379 1380 { SOME_RMEP_CCM_DEFECT_INTRf, SOME_RMEP_CCM_DEFECT_INTRf, NULL, 1381 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 1382 INVALIDr, 1383 INVALIDr, INVALIDr, 1384 INVALIDr, INVALIDr }, 1385 1386 /* End of parity-unrelated OAM faults */ 1387 /* { VFI_1_PAR_INTRf, }, */ 1388 { PARITY_ENf, L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, 1389 "L2_USER_ENTRY_DATA_ONLY table parity error", 1390 L2_USER_ENTRY_DATA_ONLYm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1391 L2_USER_ENTRY_DATA_ONLY_PARITY_CONTROLr, 1392 L2_USER_ENTRY_DATA_ONLY_PARITY_STATUSr, INVALIDr, 1393 INVALIDr, INVALIDr }, 1394 { INVALIDf, INVALIDf }, /* table terminator */ 1395 }; 1396 1397 STATIC _soc_gh_parity_info_t _soc_rg2_ip2_parity_info[] = { 1398 { PARITY_ENf, L3_ECMP_GROUP_PAR_ERRf, "L3_ECMP_GROUP table parity error", 1399 L3_ECMP_COUNTm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1400 L3_ECMP_GROUP_PARITY_CONTROLr, 1401 L3_ECMP_GROUP_PARITY_STATUSr, INVALIDr, 1402 INVALIDr, INVALIDr }, 1403 { PARITY_ENf, L3_ECMP_PAR_ERRf, "L3_ECMP table parity error", 1404 L3_ECMPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1405 L3_ECMP_PARITY_CONTROLr, 1406 L3_ECMP_PARITY_STATUSr, INVALIDr, 1407 INVALIDr, INVALIDr }, 1408 { INVALIDf, INVALIDf }, /* table terminator */ 1409 }; 1410 1411 1412 STATIC _soc_gh_parity_info_t _soc_gh_ip2_parity_info[] = { 1413 { PARITY_ENf, ING_NHOP_PAR_ERRf, "ING_L3_NEXT_HOP table parity error", 1414 ING_L3_NEXT_HOPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1415 ING_L3_NEXT_HOP_PARITY_CONTROLr, 1416 ING_L3_NEXT_HOP_PARITY_STATUSr, INVALIDr, 1417 INVALIDr, INVALIDr, 1418 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1419 _GH_SER_F_L3}, 1420 { PARITY_ENf, IFP_METER_PAR_ERRf, "FP_METER_TABLE table parity error", 1421 FP_METER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1422 IFP_METER_PARITY_CONTROLr, 1423 IFP_METER_PARITY_STATUSr, INVALIDr, 1424 INVALIDr, INVALIDr }, 1425 { PARITY_ENf, IFP_COUNTER_PAR_ERRf, "FP_COUNTER_TABLE table parity error", 1426 FP_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1427 IFP_COUNTER_PARITY_CONTROLr, 1428 IFP_COUNTER_PARITY_STATUSr, INVALIDr, 1429 INVALIDr, INVALIDr }, 1430 { PARITY_ENf, IFP_POLICY_PAR_ERRf, "FP_POLICY_TABLE table parity error", 1431 FP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1432 IFP_POLICY_PARITY_CONTROLr, 1433 IFP_POLICY_PARITY_STATUSr, INVALIDr, 1434 INVALIDr, INVALIDr }, 1435 { PARITY_ENf, IFP_STORM_CONTROL_PAR_ERRf, 1436 "FP_STORM_CONTROL_METERS table parity error", 1437 FP_STORM_CONTROL_METERSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1438 IFP_STORM_CONTROL_PARITY_CONTROLr, 1439 IFP_STORM_CONTROL_PARITY_STATUSr, INVALIDr, 1440 INVALIDr, INVALIDr }, 1441 { PARITY_ENf, L3_MTU_VALUES_PAR_ERRf, "L3_MTU_VALUES table parity error", 1442 L3_MTU_VALUESm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1443 L3_MTU_VALUES_PARITY_CONTROLr, 1444 L3_MTU_VALUES_PARITY_STATUSr, INVALIDr, 1445 INVALIDr, INVALIDr, 1446 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1447 _GH_SER_F_L3}, 1448 { PARITY_ENf, EGR_MASK_PAR_ERRf, "EGR_MASK table parity error", 1449 EGR_MASKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1450 EGR_MASK_PARITY_CONTROLr, 1451 EGR_MASK_PARITY_STATUSr, INVALIDr, 1452 INVALIDr, INVALIDr }, 1453 { PARITY_ENf, MODPORT_MAP_SW_PAR_ERRf, "MODPORT_MAP_SW table parity error", 1454 MODPORT_MAP_SWm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1455 MODPORT_MAP_SW_PARITY_CONTROLr, 1456 MODPORT_MAP_SW_PARITY_STATUSr, INVALIDr, 1457 INVALIDr, INVALIDr }, 1458 { PARITY_ENf, MODPORT_MAP_IM_PAR_ERRf, "MODPORT_MAP_IM table parity error", 1459 MODPORT_MAP_IMm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1460 MODPORT_MAP_IM_PARITY_CONTROLr, 1461 MODPORT_MAP_IM_PARITY_STATUSr, INVALIDr, 1462 INVALIDr, INVALIDr }, 1463 { PARITY_ENf, MODPORT_MAP_EM_PAR_ERRf, "MODPORT_MAP_EM table parity error", 1464 MODPORT_MAP_EMm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1465 MODPORT_MAP_EM_PARITY_CONTROLr, 1466 MODPORT_MAP_EM_PARITY_STATUSr, INVALIDr, 1467 INVALIDr, INVALIDr }, 1468 { PARITY_ENf, OAM_LM_COUNTERS_PAR_ERRf, " OAM_LM_COUNTERS table parity error", 1469 OAM_LM_COUNTERSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1470 OAM_LM_COUNTERS_PARITY_CONTROLr, 1471 OAM_LM_COUNTERS_PARITY_STATUSr, INVALIDr, 1472 INVALIDr, INVALIDr }, 1473 { PARITY_ENf, TRUNK_EGR_MASK_PAR_ERRf, "TRUNK_EGR_MASK table parity error", 1474 TRUNK_EGR_MASKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1475 TRUNK_EGR_MASK_PARITY_CONTROLr, 1476 TRUNK_EGR_MASK_PARITY_STATUSr, INVALIDr, 1477 INVALIDr, INVALIDr }, 1478 { PARITY_ENf, TRUNK_GROUP_PAR_ERRf, "TRUNK_GROUP table parity error", 1479 TRUNK_GROUPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1480 TRUNK_GROUP_PARITY_CONTROLr, 1481 TRUNK_GROUP_PARITY_STATUSr, INVALIDr, 1482 INVALIDr, INVALIDr }, 1483 { PARITY_ENf, TRUNK_BITMAP_TABLE_PAR_ERRf, 1484 "TRUNK_BITMAP table parity error", 1485 TRUNK_BITMAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1486 TRUNK_BITMAP_TABLE_PARITY_CONTROLr, 1487 TRUNK_BITMAP_TABLE_PARITY_STATUSr, INVALIDr, 1488 INVALIDr, INVALIDr }, 1489 { PARITY_ENf, MAC_BLOCK_TABLE_PAR_ERRf, "MAC_BLOCK table parity error", 1490 MAC_BLOCKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1491 MAC_BLOCK_TABLE_PARITY_CONTROLr, 1492 MAC_BLOCK_TABLE_PARITY_STATUSr, INVALIDr, 1493 INVALIDr, INVALIDr }, 1494 { PARITY_ENf, NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, 1495 "NONUCAST_TRUNK_BLOCK_MASK table parity error", 1496 NONUCAST_TRUNK_BLOCK_MASKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1497 NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr, 1498 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUSr, INVALIDr, 1499 INVALIDr, INVALIDr }, 1500 { PARITY_ENf, SRC_MODID_BLOCK_PAR_ERRf, 1501 "SRC_MODID_BLOCK table parity error", 1502 SRC_MODID_BLOCKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1503 SRC_MODID_BLOCK_PARITY_CONTROLr, 1504 SRC_MODID_BLOCK_PARITY_STATUSr, INVALIDr, 1505 INVALIDr, INVALIDr }, 1506 { PARITY_ENf, VLAN_PROFILE_2_PAR_ERRf, "VLAN_PROFILE_2 table parity error", 1507 VLAN_PROFILE_2m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1508 VLAN_PROFILE_2_PARITY_CONTROLr, 1509 VLAN_PROFILE_2_PARITY_STATUSr, INVALIDr, 1510 INVALIDr, INVALIDr }, 1511 { PARITY_ENf, ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, 1512 "ALTERNATE_EMIRROR_BITMAP table parity error", 1513 ALTERNATE_EMIRROR_BITMAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1514 ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr, 1515 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUSr, INVALIDr, 1516 INVALIDr, INVALIDr }, 1517 { INVALIDf, INVALIDf }, /* table terminator */ 1518 }; 1519 1520 1521 STATIC _soc_gh_parity_info_t _soc_rg2_ep_parity_info[] = { 1522 { PARITY_ENf, EFP_POLICY_TABLE_PAR_ERRf, "Parity enable for EFP_POLICY_TABLE memory", 1523 EFP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1524 EFP_POLICY_TABLE_PARITY_CONTROLr, 1525 EFP_POLICY_TABLE_PARITY_STATUSr, INVALIDr, 1526 INVALIDr, INVALIDr }, 1527 { PARITY_ENf, EFP_METER_TABLE_PAR_ERRf, "Parity enable for EFP_METER_TABLE memory", 1528 EFP_METER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1529 EFP_METER_TABLE_PARITY_CONTROLr, 1530 EFP_METER_TABLE_PARITY_STATUSr, INVALIDr, 1531 INVALIDr, INVALIDr }, 1532 { EFPCTR_PAR_ENf, EGR_FP_COUNTERf, "Parity enable for efp counter memory", 1533 EFP_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1534 EGR_EDATABUF_PARITY_CONTROLr, 1535 EGR_FP_COUNTER_PARITY_STATUSr, INVALIDr, 1536 INVALIDr, INVALIDr }, 1537 { INVALIDf, INVALIDf }, /* table terminator */ 1538 }; 1539 1540 STATIC _soc_gh_parity_info_t _soc_gh_ep_parity_info[] = { 1541 { PARITY_ENf, EGR_NHOP_PAR_ERRf, NULL, 1542 EGR_L3_NEXT_HOPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1543 EGR_L3_NEXT_HOP_PARITY_CONTROLr, 1544 EGR_L3_NEXT_HOP_PARITY_STATUSr, INVALIDr, 1545 INVALIDr, INVALIDr, 1546 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1547 _GH_SER_F_L3}, 1548 { PARITY_ENf, EGR_L3_INTF_PAR_ERRf, NULL, 1549 EGR_L3_INTFm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1550 EGR_L3_INTF_PARITY_CONTROLr, 1551 EGR_L3_INTF_PARITY_STATUSr, INVALIDr, 1552 INVALIDr, INVALIDr, 1553 INVALIDf, INVALIDr, INVALIDr, INVALIDr, INVALIDr, 1554 _GH_SER_F_L3}, 1555 { PARITY_ENf, EGR_VLAN_PAR_ERRf, NULL, 1556 EGR_VLANm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1557 EGR_VLAN_PARITY_CONTROLr, 1558 EGR_VLAN_PARITY_STATUSr, INVALIDr, 1559 INVALIDr, INVALIDr }, 1560 { PARITY_ENf, EGR_VLAN_STG_PAR_ERRf, NULL, 1561 EGR_VLAN_STGm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1562 EGR_VLAN_STG_PARITY_CONTROLr, 1563 EGR_VLAN_STG_PARITY_STATUSr, INVALIDr, 1564 INVALIDr, INVALIDr }, 1565 { PARITY_ENf, EGR_VXLT_PAR_ERRf, NULL, 1566 EGR_VLAN_XLATEm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 1567 EGR_VLAN_XLATE_PARITY_CONTROLr, 1568 EGR_VLAN_XLATE_PARITY_STATUS_0r, EGR_VLAN_XLATE_PARITY_STATUS_1r, 1569 INVALIDr, INVALIDr }, 1570 { STATS_PAR_ENf, EGR_STATS_COUNTER_TABLE_PAR_ERRf, "Parity enable for egress stats counter memory", 1571 INVALIDm, _SOC_PARITY_INFO_TYPE_COUNTER, 1572 EGR_EDATABUF_PARITY_CONTROLr, 1573 EGR_STATS_COUNTER_TABLE_PARITY_STATUSr, INVALIDr, 1574 INVALIDr, INVALIDr }, 1575 { ECC_ENf, EP_INITBUF_DBEf, "EP_INITBUF double-bit ECC error", 1576 INVALIDm,_SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1577 EGR_INITBUF_ECC_CONTROLr, 1578 EGR_INITBUF_ECC_STATUS_DBEr, INVALIDr, 1579 INVALIDr, INVALIDr }, 1580 { ECC_ENf, EP_INITBUF_SBEf, "EP_INITBUF single-bit ECC error (corrected)", 1581 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1582 EGR_INITBUF_ECC_CONTROLr, 1583 EGR_INITBUF_ECC_STATUS_SBEr, INVALIDr, 1584 INVALIDr, INVALIDr }, 1585 { PERQ_PAR_ENf, EGR_PERQ_COUNTERf, "Parity enable for egress perq xmt counter memory", 1586 EGR_PERQ_XMT_COUNTERSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1587 EGR_EDATABUF_PARITY_CONTROLr, 1588 EGR_PERQ_COUNTER_PARITY_STATUSr, INVALIDr, 1589 INVALIDr, INVALIDr }, 1590 /* { EFPCTR_PAR_ENf, EGR_FP_COUNTERf, "Parity enable for efp counter memory", 1591 EFP_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1592 EGR_EDATABUF_PARITY_CONTROLr, 1593 EGR_FP_COUNTER_PARITY_STATUSr, INVALIDr, 1594 INVALIDr, INVALIDr }, */ 1595 { PARITY_ENf, EGR_MOD_MAP_TABLE_PAR_ERRf, "Parity enable for EGR_MOD_MAP_TABLE memory", 1596 EGR_MOD_MAP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1597 EGR_MOD_MAP_PARITY_CONTROLr, 1598 EGR_MOD_MAP_PARITY_STATUSr, INVALIDr, 1599 INVALIDr, INVALIDr }, 1600 /* { PARITY_ENf, EFP_POLICY_TABLE_PAR_ERRf, "Parity enable for EFP_POLICY_TABLE memory", 1601 EFP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1602 EFP_POLICY_TABLE_PARITY_CONTROLr, 1603 EFP_POLICY_TABLE_PARITY_STATUSr, INVALIDr, 1604 INVALIDr, INVALIDr }, 1605 { PARITY_ENf, EFP_METER_TABLE_PAR_ERRf, "Parity enable for EFP_METER_TABLE memory", 1606 EFP_METER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1607 EFP_METER_TABLE_PARITY_CONTROLr, 1608 EFP_METER_TABLE_PARITY_STATUSr, INVALIDr, 1609 INVALIDr, INVALIDr }, */ 1610 { PARITY_ENf, EGR_ETAG_PCP_DE_MAPPING_PAR_ERRf, "Parity enable for EGR_ETAG_PCP_MAPPING memory", 1611 EGR_ETAG_PCP_MAPPINGm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1612 EGR_ETAG_PCP_DE_MAPPING_PARITY_CONTROLr, 1613 EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr, INVALIDr, 1614 INVALIDr, INVALIDr }, 1615 { PARITY_ENf, EGR_GPP_ATTRIBUTES_PAR_ERRf, "Parity enable for EGR_GPP_ATTRIBUTES memory", 1616 EGR_GPP_ATTRIBUTESm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1617 EGR_GPP_ATTRIBUTES_PARITY_CONTROLr, 1618 EGR_GPP_ATTRIBUTES_PARITY_STATUSr, INVALIDr, 1619 INVALIDr, INVALIDr }, 1620 { PARITY_ENf, EGR_PER_Q_ECN_MARKED_PAR_ERRf, "Parity enable for EGR_PER_Q_ECN_MARKED memory", 1621 EGR_PER_Q_ECN_MARKEDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1622 EGR_PER_Q_ECN_MARKED_PARITY_CONTROLr, 1623 EGR_PER_Q_ECN_MARKED_PARITY_STATUSr, INVALIDr, 1624 INVALIDr, INVALIDr }, 1625 { RESI_ECC_ENf, EGR_RESI_DBUFf, "Parity enable for P_RESI_DATABUF memory", 1626 INVALIDm,_SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1627 EGR_EDATABUF_PARITY_CONTROLr, 1628 EGR_RESI_DBITS_PARITY_STATUSr, INVALIDr, 1629 INVALIDr, INVALIDr }, 1630 { CM_ECC_ENf, EGR_CM_DBUFf, "ECC enable for cm interaface buffer", 1631 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1632 EGR_EDATABUF_PARITY_CONTROLr, 1633 EGR_CM_DBITS_PARITY_STATUSr, INVALIDr, 1634 INVALIDr, INVALIDr }, 1635 { GP_ECC_ENf, EGR_GP_DBUFf, "ECC enable for gp interaface buffer", 1636 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1637 EGR_EDATABUF_PARITY_CONTROLr, 1638 EGR_GP_DBITS_PARITY_STATUSr, INVALIDr, 1639 INVALIDr, INVALIDr }, 1640 { XP0_ECC_ENf, EGR_XP0_DBUFf, "ECC enable for xp0 interaface buffer", 1641 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1642 EGR_EDATABUF_PARITY_CONTROLr, 1643 EGR_XP0_DBITS_PARITY_STATUSr, INVALIDr, 1644 INVALIDr, INVALIDr }, 1645 { XP1_ECC_ENf, EGR_XP1_DBUFf, "ECC enable for xp1 interaface buffer", 1646 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1647 EGR_EDATABUF_PARITY_CONTROLr, 1648 EGR_XP1_DBITS_PARITY_STATUSr, INVALIDr, 1649 INVALIDr, INVALIDr }, 1650 { XP2_ECC_ENf, EGR_XP2_DBUFf, "ECC enable for xp2 interaface buffer", 1651 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1652 EGR_EDATABUF_PARITY_CONTROLr, 1653 EGR_XP2_DBITS_PARITY_STATUSr, INVALIDr, 1654 INVALIDr, INVALIDr }, 1655 { XP3_ECC_ENf, EGR_XP3_DBUFf, "ECC enable for xp3 interaface buffer", 1656 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1657 EGR_EDATABUF_PARITY_CONTROLr, 1658 EGR_XP3_DBITS_PARITY_STATUSr, INVALIDr, 1659 INVALIDr, INVALIDr }, 1660 { XP4_ECC_ENf, EGR_XP4_DBUFf, "ECC enable for xp4 interaface buffer", 1661 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1662 EGR_EDATABUF_PARITY_CONTROLr, 1663 EGR_XP4_DBITS_PARITY_STATUSr, INVALIDr, 1664 INVALIDr, INVALIDr }, 1665 { XP5_ECC_ENf, EGR_XP5_DBUFf, "ECC enable for xp5 interaface buffer", 1666 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1667 EGR_EDATABUF_PARITY_CONTROLr, 1668 EGR_XP5_DBITS_PARITY_STATUSr, INVALIDr, 1669 INVALIDr, INVALIDr }, 1670 { XP6_ECC_ENf, EGR_XP6_DBUFf, "ECC enable for xp6 interaface buffer", 1671 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1672 EGR_EDATABUF_PARITY_CONTROLr, 1673 EGR_XP6_DBITS_PARITY_STATUSr, INVALIDr, 1674 INVALIDr, INVALIDr }, 1675 { XP7_ECC_ENf, EGR_XP7_DBUFf, "ECC enable for xp7 interaface buffer", 1676 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1677 EGR_EDATABUF_PARITY_CONTROLr, 1678 EGR_XP7_DBITS_PARITY_STATUSr, INVALIDr, 1679 INVALIDr, INVALIDr }, 1680 { XP8_ECC_ENf, EGR_XP8_DBUFf, "ECC enable for xp8 interaface buffer", 1681 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1682 EGR_EDATABUF_PARITY_CONTROLr, 1683 EGR_XP8_DBITS_PARITY_STATUSr, INVALIDr, 1684 INVALIDr, INVALIDr }, 1685 { XP9_ECC_ENf, EGR_XP9_DBUFf, "ECC enable for xp9 interaface buffer", 1686 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1687 EGR_EDATABUF_PARITY_CONTROLr, 1688 EGR_XP9_DBITS_PARITY_STATUSr, INVALIDr, 1689 INVALIDr, INVALIDr }, 1690 { XP10_ECC_ENf, EGR_XP10_DBUFf, "ECC enable for xp10 interaface buffer", 1691 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1692 EGR_EDATABUF_PARITY_CONTROLr, 1693 EGR_XP10_DBITS_PARITY_STATUSr, INVALIDr, 1694 INVALIDr, INVALIDr }, 1695 { XP11_ECC_ENf, EGR_XP11_DBUFf, "ECC enable for xp11 interaface buffer", 1696 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1697 EGR_EDATABUF_PARITY_CONTROLr, 1698 EGR_XP11_DBITS_PARITY_STATUSr, INVALIDr, 1699 INVALIDr, INVALIDr }, 1700 { XP12_ECC_ENf, EGR_XP12_DBUFf, "ECC enable for xp12 interaface buffer", 1701 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1702 EGR_EDATABUF_PARITY_CONTROLr, 1703 EGR_XP12_DBITS_PARITY_STATUSr, INVALIDr, 1704 INVALIDr, INVALIDr }, 1705 { XP13_ECC_ENf, EGR_XP13_DBUFf, "ECC enable for xp13 interaface buffer", 1706 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1707 EGR_EDATABUF_PARITY_CONTROLr, 1708 EGR_XP13_DBITS_PARITY_STATUSr, INVALIDr, 1709 INVALIDr, INVALIDr }, 1710 { XP14_ECC_ENf, EGR_XP14_DBUFf, "ECC enable for xp14 interaface buffer", 1711 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1712 EGR_EDATABUF_PARITY_CONTROLr, 1713 EGR_XP14_DBITS_PARITY_STATUSr, INVALIDr, 1714 INVALIDr, INVALIDr }, 1715 { XP15_ECC_ENf, EGR_XP15_DBUFf, "ECC enable for xp15 interaface buffer", 1716 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1717 EGR_EDATABUF_PARITY_CONTROLr, 1718 EGR_XP15_DBITS_PARITY_STATUSr, INVALIDr, 1719 INVALIDr, INVALIDr }, 1720 { XP16_ECC_ENf, EGR_XP16_DBUFf, "ECC enable for xp16 interaface buffer", 1721 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1722 EGR_EDATABUF_PARITY_CONTROLr, 1723 EGR_XP16_DBITS_PARITY_STATUSr, INVALIDr, 1724 INVALIDr, INVALIDr }, 1725 { XP17_ECC_ENf, EGR_XP15_DBUFf, "ECC enable for xp17 interaface buffer", 1726 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1727 EGR_EDATABUF_PARITY_CONTROLr, 1728 EGR_XP17_DBITS_PARITY_STATUSr, INVALIDr, 1729 INVALIDr, INVALIDr }, 1730 { XP18_ECC_ENf, EGR_XP15_DBUFf, "ECC enable for xp18 interaface buffer", 1731 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1732 EGR_EDATABUF_PARITY_CONTROLr, 1733 EGR_XP18_DBITS_PARITY_STATUSr, INVALIDr, 1734 INVALIDr, INVALIDr }, 1735 { XP19_ECC_ENf, EGR_XP15_DBUFf, "ECC enable for xp19 interaface buffer", 1736 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1737 EGR_EDATABUF_PARITY_CONTROLr, 1738 EGR_XP19_DBITS_PARITY_STATUSr, INVALIDr, 1739 INVALIDr, INVALIDr }, 1740 { INVALIDf, INVALIDf }, /* table terminator */ 1741 }; 1742 1743 1744 STATIC _soc_gh_parity_info_t _soc_gh_xl_parity_info[] = { 1745 { PM_INTRf, PM_INTRf, NULL, 1746 INVALIDm, _SOC_PARITY_INFO_TYPE_PORT_MACRO, 1747 INVALIDr, 1748 XLPORT_INTR_STATUSr, INVALIDr, 1749 INVALIDr, INVALIDr }, 1750 { TXFIFO_ECC_ENf, TXFIFO3_DBEf, NULL, 1751 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1752 PGW_XL_ECC_CONTROLr, 1753 PGW_XL_TXFIFO0_ECC_DBE_STATUSr, INVALIDr, 1754 INVALIDr, INVALIDr }, 1755 { TXFIFO_ECC_ENf, TXFIFO2_DBEf, NULL, 1756 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1757 PGW_XL_ECC_CONTROLr, 1758 PGW_XL_TXFIFO1_ECC_DBE_STATUSr, INVALIDr, 1759 INVALIDr, INVALIDr }, 1760 { TXFIFO_ECC_ENf, TXFIFO1_DBEf, NULL, 1761 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1762 PGW_XL_ECC_CONTROLr, 1763 PGW_XL_TXFIFO2_ECC_DBE_STATUSr, INVALIDr, 1764 INVALIDr, INVALIDr }, 1765 { TXFIFO_ECC_ENf, TXFIFO0_DBEf, NULL, 1766 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1767 PGW_XL_ECC_CONTROLr, 1768 PGW_XL_TXFIFO3_ECC_DBE_STATUSr, INVALIDr, 1769 INVALIDr, INVALIDr }, 1770 { RXFIFO_ECC_ENABLEf, RXFIFO_DBEf, NULL, 1771 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1772 PGW_XL_ECC_CONTROLr, 1773 PGW_XL_RXFIFO_ECC_DBE_STATUSr, INVALIDr, 1774 INVALIDr, INVALIDr }, 1775 #if GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED 1776 { TXFIFO_ECC_ENf, TXFIFO3_SBEf, NULL, 1777 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1778 PGW_XL_ECC_CONTROLr, 1779 PGW_XL_TXFIFO0_ECC_SBE_STATUSr, INVALIDr, 1780 INVALIDr, INVALIDr }, 1781 { TXFIFO_ECC_ENf, TXFIFO2_SBEf, NULL, 1782 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1783 PGW_XL_ECC_CONTROLr, 1784 PGW_XL_TXFIFO1_ECC_SBE_STATUSr, INVALIDr, 1785 INVALIDr, INVALIDr }, 1786 { TXFIFO_ECC_ENf, TXFIFO1_SBEf, NULL, 1787 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1788 PGW_XL_ECC_CONTROLr, 1789 PGW_XL_TXFIFO2_ECC_SBE_STATUSr, INVALIDr, 1790 INVALIDr, INVALIDr }, 1791 { TXFIFO_ECC_ENf, TXFIFO0_SBEf, NULL, 1792 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1793 PGW_XL_ECC_CONTROLr, 1794 PGW_XL_TXFIFO3_ECC_SBE_STATUSr, INVALIDr, 1795 INVALIDr, INVALIDr }, 1796 { RXFIFO_EN_COR_ERR_RPTf, RXFIFO_SBEf, NULL, 1797 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1798 PGW_XL_ECC_CONTROLr, 1799 PGW_XL_RXFIFO_ECC_SBE_STATUSr, INVALIDr, 1800 INVALIDr, INVALIDr }, 1801 #endif /* GREYHOUND_SER_ECC_SINGLE_ERR_RPT_ENABLED */ 1802 /* { BOD_XLP0_ERRf,}, */ 1803 { INVALIDf, INVALIDf }, /* table terminator */ 1804 }; 1805 1806 STATIC _soc_gh_parity_info_t _soc_gh_gx_parity_info[] = { 1807 { PM_INTRf, PM_INTRf, NULL, 1808 INVALIDm, _SOC_PARITY_INFO_TYPE_PORT_MACRO, 1809 INVALIDr, 1810 XLPORT_INTR_STATUSr, INVALIDr, 1811 INVALIDr, INVALIDr }, 1812 { TXFIFO_ECC_ENf, TXFIFO3_DBEf, NULL, 1813 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1814 PGW_GX_ECC_CONTROLr, 1815 PGW_GX_TXFIFO0_ECC_DBE_STATUSr, INVALIDr, 1816 INVALIDr, INVALIDr }, 1817 { TXFIFO_ECC_ENf, TXFIFO2_DBEf, NULL, 1818 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1819 PGW_GX_ECC_CONTROLr, 1820 PGW_GX_TXFIFO1_ECC_DBE_STATUSr, INVALIDr, 1821 INVALIDr, INVALIDr }, 1822 { TXFIFO_ECC_ENf, TXFIFO1_DBEf, NULL, 1823 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1824 PGW_GX_ECC_CONTROLr, 1825 PGW_GX_TXFIFO2_ECC_DBE_STATUSr, INVALIDr, 1826 INVALIDr, INVALIDr }, 1827 { TXFIFO_ECC_ENf, TXFIFO0_DBEf, NULL, 1828 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1829 PGW_GX_ECC_CONTROLr, 1830 PGW_GX_TXFIFO3_ECC_DBE_STATUSr, INVALIDr, 1831 INVALIDr, INVALIDr }, 1832 { RXFIFO_ECC_ENABLEf, RXFIFO1_DBEf, NULL, 1833 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1834 PGW_GX_ECC_CONTROLr, 1835 PGW_GX_RXFIFO1_ECC_DBE_STATUSr, INVALIDr, 1836 INVALIDr, INVALIDr }, 1837 { RXFIFO_ECC_ENABLEf, RXFIFO0_DBEf, NULL, 1838 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1839 PGW_GX_ECC_CONTROLr, 1840 PGW_GX_RXFIFO0_ECC_DBE_STATUSr, INVALIDr, 1841 INVALIDr, INVALIDr }, 1842 #if GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED 1843 { TXFIFO_ECC_ENf, TXFIFO3_SBEf, NULL, 1844 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1845 PGW_GX_ECC_CONTROLr, 1846 PGW_GX_TXFIFO0_ECC_SBE_STATUSr, INVALIDr, 1847 INVALIDr, INVALIDr }, 1848 { TXFIFO_ECC_ENf, TXFIFO2_SBEf, NULL, 1849 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1850 PGW_GX_ECC_CONTROLr, 1851 PGW_GX_TXFIFO1_ECC_SBE_STATUSr, INVALIDr, 1852 INVALIDr, INVALIDr }, 1853 { TXFIFO_ECC_ENf, TXFIFO1_SBEf, NULL, 1854 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1855 PGW_GX_ECC_CONTROLr, 1856 PGW_GX_TXFIFO2_ECC_SBE_STATUSr, INVALIDr, 1857 INVALIDr, INVALIDr }, 1858 { TXFIFO_ECC_ENf, TXFIFO0_SBEf, NULL, 1859 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1860 PGW_GX_ECC_CONTROLr, 1861 PGW_GX_TXFIFO3_ECC_SBE_STATUSr, INVALIDr, 1862 INVALIDr, INVALIDr }, 1863 { RXFIFO_EN_COR_ERR_RPTf, RXFIFO_SBEf, NULL, 1864 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1865 PGW_GX_ECC_CONTROLr, 1866 PGW_GX_RXFIFO0_ECC_SBE_STATUSr, INVALIDr, 1867 INVALIDr, INVALIDr }, 1868 #endif /* GREYHOUND_SER_ECC_SINGLE_ERR_RPT_ENABLED */ 1869 { INVALIDf, INVALIDf }, /* table terminator */ 1870 }; 1871 1872 STATIC _soc_gh_parity_info_t _soc_gh_mmu_parity_info[] = { 1873 { CELLECCERRORINTMASKf, CELLECCERRORf, NULL, 1874 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_ECC, 1875 INVALIDr, 1876 CBPCELLERRPTRr, INVALIDr, 1877 INVALIDr, INVALIDr, 1878 CELLECCERROR_CLRf, 1879 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1880 { CBPPKTHDRPARITYERRORINTMASKf, CBPPKTHDRPARITYERRORf, NULL, 1881 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_CBPPKTHDR, 1882 INVALIDr, 1883 INVALIDr, INVALIDr, 1884 INVALIDr, INVALIDr, 1885 CBPPKTHDRPARITYERROR_CLRf, 1886 CBPPKTHDR_ERR_CLRr, INVALIDr, INVALIDr, INVALIDr }, 1887 { CBPCELLHDRPARITYERRORINTMASKf, CBPCELLHDRPARITYERRORf, NULL, 1888 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_ECC, 1889 INVALIDr, 1890 CBPCELLHDRPARITYERRPTRr, INVALIDr, 1891 INVALIDr, INVALIDr, 1892 CBPCELLHDRPARITYERROR_CLRf, 1893 INVALIDr, INVALIDr, INVALIDr, INVALIDr }, 1894 { XQPARITYERRORINTMASKf, XQPARITYERRORf, NULL, 1895 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_XQ, 1896 INVALIDr, 1897 INVALIDr, INVALIDr, 1898 INVALIDr, INVALIDr, 1899 XQPARITYERROR_CLRf, 1900 XQPARITYERRORPTRr, XQ_ERR_VLDr, XQ_MULTI_ERRr, XQ_ERR_CLRr }, 1901 { CFAPPARITYERRORINTMASKf, CFAPPARITYERRORf, "CBP Free Address Pool RAM", 1902 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_ECC, 1903 INVALIDr, 1904 CFAPPARITYERRORPTRr, INVALIDr, 1905 INVALIDr, INVALIDr, 1906 CFAPPARITYERROR_CLRf, 1907 INVALIDr, INVALIDr, INVALIDr, INVALIDr }, 1908 { CCPPARITYERRORINTMASKf, CCPPARITYERRORf, "Copy Count Pool RAM", 1909 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_ECC, 1910 INVALIDr, 1911 CCPPARITYERRORPTRr, INVALIDr, 1912 INVALIDr, INVALIDr, 1913 CCPPARITYERROR_CLRf, 1914 INVALIDr, INVALIDr, INVALIDr, INVALIDr }, 1915 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1916 MMU_WRED_MARK_THDm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1917 INVALIDr, 1918 INVALIDr, INVALIDr, 1919 INVALIDr, INVALIDr, 1920 WREDPARITYERROR_CLRf, 1921 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1922 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1923 MMU_WRED_DROP_PROFILE_GREENm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1924 INVALIDr, 1925 INVALIDr, INVALIDr, 1926 INVALIDr, INVALIDr, 1927 WREDPARITYERROR_CLRf, 1928 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1929 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1930 MMU_WRED_DROP_PROFILE_YELLOWm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1931 INVALIDr, 1932 INVALIDr, INVALIDr, 1933 INVALIDr, INVALIDr, 1934 WREDPARITYERROR_CLRf, 1935 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1936 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1937 MMU_WRED_DROP_PROFILE_REDm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1938 INVALIDr, 1939 INVALIDr, INVALIDr, 1940 INVALIDr, INVALIDr, 1941 WREDPARITYERROR_CLRf, 1942 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1943 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1944 MMU_WRED_MARK_PROFILE_GREENm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1945 INVALIDr, 1946 INVALIDr, INVALIDr, 1947 INVALIDr, INVALIDr, 1948 WREDPARITYERROR_CLRf, 1949 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1950 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1951 MMU_WRED_MARK_PROFILE_YELLOWm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1952 INVALIDr, 1953 INVALIDr, INVALIDr, 1954 INVALIDr, INVALIDr, 1955 WREDPARITYERROR_CLRf, 1956 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1957 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1958 MMU_WRED_MARK_PROFILE_REDm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1959 INVALIDr, 1960 INVALIDr, INVALIDr, 1961 INVALIDr, INVALIDr, 1962 WREDPARITYERROR_CLRf, 1963 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1964 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1965 MMU_WRED_AVG_QSIZEm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1966 INVALIDr, 1967 INVALIDr, INVALIDr, 1968 INVALIDr, INVALIDr, 1969 WREDPARITYERROR_CLRf, 1970 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1971 { WREDPARITYERRORINTMASKf, WREDPARITYERRORf, NULL, 1972 MMU_WRED_CONFIGm, _SOC_PARITY_INFO_TYPE_MMU_WRED, 1973 INVALIDr, 1974 INVALIDr, INVALIDr, 1975 INVALIDr, INVALIDr, 1976 WREDPARITYERROR_CLRf, 1977 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1978 { XQFLLPARITYERRORINTMASKf, XQFLLPARITYERRORf, NULL, 1979 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_XQ, 1980 INVALIDr, 1981 INVALIDr, INVALIDr, 1982 INVALIDr, INVALIDr, 1983 XQFLLPARITYERROR_CLRf, 1984 XQFLLPARITYERRORPTRr, XQFLL_ERR_VLDr, XQFLL_MULTI_ERRr, XQFLL_ERR_CLRr }, 1985 { E2EFCPARITYERRORINTMASKf, E2EFCPARITYERRORf, NULL, 1986 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_E2EFC, 1987 INVALIDr, 1988 INVALIDr, INVALIDr, 1989 INVALIDr, INVALIDr, 1990 E2EFCPARITYERROR_CLRf, 1991 INVALIDr, INVALIDr, INVALIDr, INVALIDr }, 1992 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 1993 MMU_IPMC_GROUP_TBL2m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 1994 INVALIDr, 1995 INVALIDr, INVALIDr, 1996 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1997 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 1998 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 1999 MMU_IPMC_GROUP_TBL3m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2000 INVALIDr, 2001 INVALIDr, INVALIDr, 2002 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2003 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2004 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2005 MMU_IPMC_GROUP_TBL4m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2006 INVALIDr, 2007 INVALIDr, INVALIDr, 2008 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2009 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2010 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2011 MMU_IPMC_GROUP_TBL5m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2012 INVALIDr, 2013 INVALIDr, INVALIDr, 2014 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2015 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2016 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2017 MMU_IPMC_GROUP_TBL6m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2018 INVALIDr, 2019 INVALIDr, INVALIDr, 2020 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2021 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2022 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2023 MMU_IPMC_GROUP_TBL7m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2024 INVALIDr, 2025 INVALIDr, INVALIDr, 2026 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2027 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2028 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2029 MMU_IPMC_GROUP_TBL8m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2030 INVALIDr, 2031 INVALIDr, INVALIDr, 2032 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2033 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2034 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2035 MMU_IPMC_GROUP_TBL9m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2036 INVALIDr, 2037 INVALIDr, INVALIDr, 2038 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2039 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2040 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2041 MMU_IPMC_GROUP_TBL10m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2042 INVALIDr, 2043 INVALIDr, INVALIDr, 2044 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2045 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2046 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2047 MMU_IPMC_GROUP_TBL11m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2048 INVALIDr, 2049 INVALIDr, INVALIDr, 2050 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2051 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2052 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2053 MMU_IPMC_GROUP_TBL12m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2054 INVALIDr, 2055 INVALIDr, INVALIDr, 2056 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2057 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2058 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2059 MMU_IPMC_GROUP_TBL13m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2060 INVALIDr, 2061 INVALIDr, INVALIDr, 2062 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2063 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2064 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2065 MMU_IPMC_GROUP_TBL14m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2066 INVALIDr, 2067 INVALIDr, INVALIDr, 2068 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2069 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2070 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2071 MMU_IPMC_GROUP_TBL15m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2072 INVALIDr, 2073 INVALIDr, INVALIDr, 2074 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2075 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2076 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2077 MMU_IPMC_GROUP_TBL16m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2078 INVALIDr, 2079 INVALIDr, INVALIDr, 2080 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2081 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2082 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2083 MMU_IPMC_GROUP_TBL17m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2084 INVALIDr, 2085 INVALIDr, INVALIDr, 2086 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2087 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2088 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2089 MMU_IPMC_GROUP_TBL18m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2090 INVALIDr, 2091 INVALIDr, INVALIDr, 2092 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2093 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2094 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2095 MMU_IPMC_GROUP_TBL19m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2096 INVALIDr, 2097 INVALIDr, INVALIDr, 2098 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2099 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2100 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2101 MMU_IPMC_GROUP_TBL20m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2102 INVALIDr, 2103 INVALIDr, INVALIDr, 2104 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2105 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2106 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2107 MMU_IPMC_GROUP_TBL21m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2108 INVALIDr, 2109 INVALIDr, INVALIDr, 2110 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2111 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2112 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2113 MMU_IPMC_GROUP_TBL22m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2114 INVALIDr, 2115 INVALIDr, INVALIDr, 2116 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2117 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2118 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2119 MMU_IPMC_GROUP_TBL23m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2120 INVALIDr, 2121 INVALIDr, INVALIDr, 2122 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2123 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2124 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2125 MMU_IPMC_GROUP_TBL24m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2126 INVALIDr, 2127 INVALIDr, INVALIDr, 2128 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2129 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2130 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2131 MMU_IPMC_GROUP_TBL25m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2132 INVALIDr, 2133 INVALIDr, INVALIDr, 2134 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2135 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2136 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2137 MMU_IPMC_GROUP_TBL26m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2138 INVALIDr, 2139 INVALIDr, INVALIDr, 2140 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2141 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2142 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2143 MMU_IPMC_GROUP_TBL27m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2144 INVALIDr, 2145 INVALIDr, INVALIDr, 2146 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2147 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2148 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2149 MMU_IPMC_GROUP_TBL28m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2150 INVALIDr, 2151 INVALIDr, INVALIDr, 2152 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2153 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2154 { IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, NULL, 2155 MMU_IPMC_GROUP_TBL29m, _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP, 2156 INVALIDr, 2157 INVALIDr, INVALIDr, 2158 INVALIDr, INVALIDr, IPMCGROUPPARITYERROR_CLRf, 2159 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2160 { IPMCVLANXPORTPARITYERRORINTMASKf, IPMCVLANXPORTPARITYERRORf, 2161 "MMU_IPMV_VLAN_TBL memory", 2162 MMU_IPMC_VLAN_TBLm, _SOC_PARITY_INFO_TYPE_MMU_IPMCVLAN, 2163 INVALIDr, 2164 INVALIDr, INVALIDr, 2165 INVALIDr, INVALIDr, IPMCVLANXPORTPARITYERROR_CLRf, 2166 INVALIDr, INVALIDr, INVALIDr, INVALIDr}, 2167 { INVALIDf, INVALIDf }, /* table terminator */ 2168 }; 2169 2170 2171 #define CMIC_PARITY_MMU_TO_CMIC_MEMFAIL_INTR_BIT 0x0001 2172 #define CMIC_PARITY_EP_TO_CMIC_PERR_INTR_BIT 0x0002 2173 #define CMIC_PARITY_IP0_TO_CMIC_PERR_INTR_BIT 0x0004 2174 #define CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT 0x0008 2175 #define CMIC_PARITY_IP2_TO_CMIC_PERR_INTR_BIT 0x0010 2176 #define CMIC_PARITY_XLP0_TO_CMIC_PERR_INTR_BIT 0x0040 2177 2178 2179 typedef struct { 2180 uint32 cpi_bit; 2181 soc_block_t blocktype; 2182 soc_reg_t enable_reg; 2183 soc_reg_t status_reg; 2184 soc_reg_t clear_reg; 2185 _soc_gh_parity_info_t *info; 2186 } _soc_gh_parity_group_info_t; 2187 static _soc_gh_parity_group_info_t _soc_rg2_parity_group_info_template[] = { 2188 { CMIC_PARITY_MMU_TO_CMIC_MEMFAIL_INTR_BIT, SOC_BLK_MMU, MEMFAILINTMASKr, 2189 MEMFAILINTSTATUSr, MEMFAILINT_CLRr, _soc_gh_mmu_parity_info}, 2190 { CMIC_PARITY_EP_TO_CMIC_PERR_INTR_BIT, SOC_BLK_EPIPE, EGR_INTR_ENABLE_64r, 2191 EGR_INTR_STATUS_64r, INVALIDr, _soc_gh_ep_parity_info }, 2192 { CMIC_PARITY_EP_TO_CMIC_PERR_INTR_BIT, SOC_BLK_EPIPE, EGR_INTR_ENABLE_64r, 2193 EGR_INTR_STATUS_64r, INVALIDr, _soc_rg2_ep_parity_info }, 2194 { CMIC_PARITY_IP0_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP0_INTR_ENABLEr, 2195 IP0_INTR_STATUSr, INVALIDr, _soc_gh_ip0_parity_info }, 2196 { CMIC_PARITY_IP0_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP0_INTR_ENABLEr, 2197 IP0_INTR_STATUSr, INVALIDr, _soc_rg2_ip0_parity_info }, 2198 { CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP1_INTR_ENABLEr, 2199 IP1_INTR_STATUSr, INVALIDr, _soc_gh_ip1_parity_info }, 2200 { CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP1_INTR_ENABLEr, 2201 IP1_INTR_STATUSr, INVALIDr, _soc_rg2_ip1_parity_info }, 2202 { CMIC_PARITY_IP2_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP2_INTR_ENABLEr, 2203 IP2_INTR_STATUSr, INVALIDr, _soc_gh_ip2_parity_info }, 2204 { CMIC_PARITY_IP2_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP2_INTR_ENABLEr, 2205 IP2_INTR_STATUSr, INVALIDr, _soc_rg2_ip2_parity_info }, 2206 /* { 0x00020, PCIE_REPLAY_PERR, }, */ 2207 { CMIC_PARITY_XLP0_TO_CMIC_PERR_INTR_BIT, SOC_BLK_XLPORT, 2208 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 2209 INVALIDr, _soc_gh_xl_parity_info }, 2210 { 0 }, /* table terminator */ 2211 }; 2212 2213 static _soc_gh_parity_group_info_t _soc_gh_parity_group_info_template[] = { 2214 { CMIC_PARITY_MMU_TO_CMIC_MEMFAIL_INTR_BIT, SOC_BLK_MMU, MEMFAILINTMASKr, 2215 MEMFAILINTSTATUSr, MEMFAILINT_CLRr, _soc_gh_mmu_parity_info}, 2216 { CMIC_PARITY_EP_TO_CMIC_PERR_INTR_BIT, SOC_BLK_EPIPE, EGR_INTR_ENABLE_64r, 2217 EGR_INTR_STATUS_64r, INVALIDr, _soc_gh_ep_parity_info }, 2218 { CMIC_PARITY_IP0_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP0_INTR_ENABLEr, 2219 IP0_INTR_STATUSr, INVALIDr, _soc_gh_ip0_parity_info }, 2220 { CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP1_INTR_ENABLEr, 2221 IP1_INTR_STATUSr, INVALIDr, _soc_gh_ip1_parity_info }, 2222 { CMIC_PARITY_IP2_TO_CMIC_PERR_INTR_BIT, SOC_BLK_IPIPE, IP2_INTR_ENABLEr, 2223 IP2_INTR_STATUSr, INVALIDr, _soc_gh_ip2_parity_info }, 2224 /* { 0x00020, PCIE_REPLAY_PERR, }, */ 2225 { CMIC_PARITY_XLP0_TO_CMIC_PERR_INTR_BIT, SOC_BLK_XLPORT, 2226 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 2227 INVALIDr, _soc_gh_xl_parity_info }, 2228 { 0 }, /* table terminator */ 2229 }; 2230 2231 2232 STATIC _soc_generic_ser_info_t *_soc_gh_tcam_ser_info[SOC_MAX_NUM_DEVICES] = {NULL}; 2233 STATIC _soc_gh_parity_group_info_t *_soc_gh_parity_group_info[SOC_MAX_NUM_DEVICES] = {NULL}; 2234 2235 STATIC soc_ser_functions_t _gh_ser_functions[SOC_MAX_NUM_DEVICES]; 2236 2237 2238 STATIC soc_greyhound_oam_handler_t gh_oam_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 2239 STATIC soc_greyhound_oam_ser_handler_t gh_oam_ser_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 2240 2241 2242 #define _SOC_GREYHOUND_SER_REG 1 2243 #define _SOC_GREYHOUND_SER_MEM 0 2244 2245 typedef union _greyhound_ser_nack_reg_mem_u { 2246 soc_reg_t reg; 2247 soc_mem_t mem; 2248 } _greyhound_ser_nack_reg_mem_t; 2249 2250 STATIC int 2251 _soc_greyhound_ser_mem_skip(int unit, int skip_feature) 2252 { 2253 int skip = 0; 2254 2255 if (!soc_feature(unit, soc_feature_l3)){ 2256 if (skip_feature & _GH_SER_F_L3) { 2257 skip = 1; 2258 } 2259 } 2260 2261 return skip; 2262 } 2263 2264 STATIC int 2265 _soc_greyhound_parity_block_port(int unit, soc_block_t block, soc_port_t *port) 2266 { 2267 *port = SOC_BLOCK_PORT(unit, block); 2268 if ((*port != REG_PORT_ANY) && !SOC_PORT_VALID(unit, *port)) { 2269 return SOC_E_PORT; 2270 } 2271 2272 return SOC_E_NONE; 2273 } 2274 2275 soc_field_t _soc_gh_oam_interrupt_fields[] = { 2276 SOME_RDI_DEFECT_INTRf, 2277 SOME_RMEP_CCM_DEFECT_INTRf, 2278 ERROR_CCM_DEFECT_INTRf, 2279 ANY_RMEP_TLV_PORT_DOWN_INTRf, 2280 ANY_RMEP_TLV_PORT_UP_INTRf, 2281 ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, 2282 ANY_RMEP_TLV_INTERFACE_UP_INTRf, 2283 XCON_CCM_DEFECT_INTRf, 2284 INVALIDf 2285 }; 2286 2287 STATIC int 2288 _soc_gh_process_oam_interrupt(int unit) 2289 { 2290 uint32 rval; 2291 int found = 0, fidx = 0; 2292 soc_greyhound_oam_handler_t oam_handler_snapshot = gh_oam_handler[unit]; 2293 2294 2295 SOC_IF_ERROR_RETURN(READ_IP1_INTR_STATUSr(unit, &rval)); 2296 2297 while (_soc_gh_oam_interrupt_fields[fidx] != INVALIDf) { 2298 if (soc_reg_field_get(unit, IP1_INTR_STATUSr, rval, 2299 _soc_gh_oam_interrupt_fields[fidx])) { 2300 2301 if (oam_handler_snapshot != NULL) 2302 { 2303 (void)(oam_handler_snapshot(unit, 2304 _soc_gh_oam_interrupt_fields[fidx])); 2305 } 2306 found++; 2307 } 2308 fidx++; 2309 } 2310 if (!found) { 2311 LOG_ERROR(BSL_LS_SOC_COMMON, 2312 (BSL_META_U(unit, 2313 "Unexpected interrupt received for OAM !!\n"))); 2314 } 2315 return SOC_E_NONE; 2316 } 2317 2318 void 2319 soc_greyhound_oam_ser_handler_register(int unit, 2320 soc_greyhound_oam_ser_handler_t handler) 2321 { 2322 gh_oam_ser_handler[unit] = handler; 2323 } 2324 2325 int 2326 soc_greyhound_oam_ser_process(int unit, soc_mem_t mem, int index) 2327 { 2328 void *null_entry = NULL; 2329 int rv = SOC_E_NONE; 2330 2331 if (gh_oam_ser_handler[unit]) { 2332 return gh_oam_ser_handler[unit](unit, mem, index); 2333 } else { 2334 /* Clear the entry of MA_STATE and REMP memories */ 2335 null_entry = soc_mem_entry_null(unit, mem); 2336 if ((rv = soc_mem_write(unit, mem, MEM_BLOCK_ALL, index, null_entry)) < 0) { 2337 LOG_ERROR(BSL_LS_SOC_COMMON, 2338 (BSL_META_U(unit, 2339 "OAM SER ENTRY_CLEAR failed for %s[%d]: %s\n"), 2340 SOC_MEM_NAME(unit, mem), 2341 index, soc_errmsg(rv))); 2342 return rv; 2343 } 2344 2345 if (soc_property_get(unit, spn_ENHANCED_SER_CORRECTION_EVENT_REPORT, 0)) { 2346 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2347 SOC_SWITCH_EVENT_DATA_ERROR_PARITY_CORRECTED, mem, index); 2348 } else { 2349 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2350 SOC_SWITCH_EVENT_DATA_ERROR_CORRECTED, mem, index); 2351 } 2352 2353 LOG_ERROR(BSL_LS_SOC_COMMON, 2354 (BSL_META_U(unit, 2355 "OAM SER ENTRY_CLEAR: %s[%d] index %d\n"), 2356 SOC_MEM_NAME(unit, mem), mem, index)); 2357 return rv; 2358 } 2359 } 2360 2361 2362 2363 #if GREYHOUND_SER_PARITY_ENABLED 2364 STATIC int 2365 _soc_greyhound_parity_enable(int unit, int enable) 2366 { 2367 int group, table, reg_is_64, blk_num = 0; 2368 uint32 group_enable, regval, cmic_enable = 0, cpi_blk_bit; 2369 _soc_gh_parity_info_t *info; 2370 soc_reg_t group_reg, reg; 2371 soc_port_t block_port; 2372 soc_field_t enable_field; 2373 soc_block_t blk; 2374 uint64 group_enable64; 2375 _soc_gh_parity_group_info_t *parity_group_info; 2376 2377 parity_group_info = _soc_gh_parity_group_info[unit]; 2378 if (parity_group_info == NULL) { 2379 return SOC_E_UNAVAIL; 2380 } 2381 2382 /* loop through each group */ 2383 for (group = 0; parity_group_info[group].cpi_bit; group++) { 2384 info = parity_group_info[group].info; 2385 group_reg = parity_group_info[group].enable_reg; 2386 group_enable = 0; 2387 COMPILER_64_ZERO(group_enable64); 2388 reg_is_64 = SOC_REG_IS_64(unit, group_reg) ? 1 : 0; 2389 cpi_blk_bit = parity_group_info[group].cpi_bit; 2390 2391 SOC_BLOCK_ITER(unit, blk, 2392 parity_group_info[group].blocktype) { 2393 if (_soc_greyhound_parity_block_port(unit, blk, &block_port) < 0) { 2394 continue; 2395 } 2396 if (!SOC_REG_IS_VALID(unit, group_reg)) { 2397 break; 2398 } 2399 2400 if (reg_is_64) { 2401 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, group_reg, block_port, 2402 0, &group_enable64)); 2403 } else { 2404 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, group_reg, block_port, 2405 0, &group_enable)); 2406 } 2407 2408 if (parity_group_info[group].blocktype == SOC_BLK_XLPORT) { 2409 blk_num = SOC_BLOCK_INFO(unit, blk).number; 2410 if (blk_num == 5) { 2411 info = _soc_gh_gx_parity_info; 2412 group_reg = PGW_GX_INTR_ENABLEr; 2413 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, group_reg, 2414 block_port, 0, &group_enable)); 2415 } 2416 } 2417 2418 /* loop through each table in the group */ 2419 for (table = 0; info[table].enable_field != INVALIDf; table++) { 2420 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 2421 continue; 2422 } 2423 /* handle different parity error reporting style */ 2424 switch (info[table].type) { 2425 case _SOC_PARITY_INFO_TYPE_GENERIC: 2426 case _SOC_PARITY_INFO_TYPE_MMU_ECC: 2427 case _SOC_PARITY_INFO_TYPE_MMU_XQ: 2428 case _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP: 2429 case _SOC_PARITY_INFO_TYPE_MMU_IPMCVLAN: 2430 case _SOC_PARITY_INFO_TYPE_MMU_E2EFC: 2431 case _SOC_PARITY_INFO_TYPE_MMU_WRED: 2432 case _SOC_PARITY_INFO_TYPE_MMU_CBPPKTHDR: 2433 case _SOC_PARITY_INFO_TYPE_OAM: 2434 case _SOC_PARITY_INFO_TYPE_PORT_MACRO: 2435 enable_field = info[table].enable_field; 2436 break; 2437 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 2438 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 2439 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 2440 case _SOC_PARITY_INFO_TYPE_COUNTER: 2441 reg = info[table].control_reg; 2442 if (!SOC_REG_IS_VALID(unit, reg)) { 2443 continue; 2444 } 2445 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, 2446 block_port, 0, ®val)); 2447 soc_reg_field_set(unit, reg, ®val, 2448 info[table].enable_field, 2449 enable ? 1 : 0); 2450 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, 2451 block_port, 0, regval)); 2452 enable_field = info[table].error_field; 2453 break; 2454 default: 2455 enable_field = INVALIDf; 2456 break; 2457 } /* handle different parity error reporting style */ 2458 if (enable_field != INVALIDf) { 2459 if (reg_is_64) { 2460 soc_reg64_field32_set(unit, group_reg, &group_enable64, 2461 enable_field, enable ? 1 : 0); 2462 } else { 2463 soc_reg_field_set(unit, group_reg, &group_enable, 2464 enable_field, enable ? 1 : 0); 2465 } 2466 } 2467 } /* loop through each table in the group */ 2468 2469 if (parity_group_info[group].blocktype == 2470 SOC_BLK_XLPORT) { 2471 /* Enable XLPORT interrupts */ 2472 reg = XLPORT_INTR_ENABLEr; 2473 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, 2474 reg, block_port, 0, ®val)); 2475 soc_reg_field_set(unit, reg, ®val, 2476 TSC_ERRf, 2477 enable ? 1 : 0); 2478 soc_reg_field_set(unit, reg, ®val, 2479 MAC_RX_CDC_MEM_ERRf, 2480 enable ? 1 : 0); 2481 soc_reg_field_set(unit, reg, ®val, 2482 MAC_TX_CDC_MEM_ERRf, 2483 enable ? 1 : 0); 2484 soc_reg_field_set(unit, reg, ®val, 2485 MIB_RX_MEM_ERRf, 2486 enable ? 1 : 0); 2487 soc_reg_field_set(unit, reg, ®val, 2488 MIB_TX_MEM_ERRf, 2489 enable ? 1 : 0); 2490 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 2491 reg, block_port, 0, regval)); 2492 2493 } 2494 2495 if (reg_is_64) { 2496 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, group_reg, block_port, 2497 0, group_enable64)); 2498 } else { 2499 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, group_reg, block_port, 2500 0, group_enable)); 2501 } 2502 if (parity_group_info[group].blocktype == 2503 SOC_BLK_XLPORT) { 2504 cmic_enable |= (cpi_blk_bit << blk_num); 2505 } else { 2506 cmic_enable |= cpi_blk_bit; 2507 } 2508 2509 } 2510 } /* loop through each group */ 2511 2512 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, ®val)); 2513 if (enable) { 2514 /* MMU enables */ 2515 soc_reg_field_set(unit, MISCCONFIGr, ®val, PARITY_CHECK_ENf, 1); 2516 #if GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED 2517 soc_reg_field_set(unit, MISCCONFIGr, ®val, 2518 ECC_ONE_BIT_ERROR_INT_ENf, 1); 2519 #endif /* GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED */ 2520 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, regval)); 2521 /* Write CMIC enable register */ 2522 (void)soc_cmicm_intr3_enable(unit, cmic_enable); 2523 } else { 2524 /* MMU disables */ 2525 soc_reg_field_set(unit, MISCCONFIGr, ®val, PARITY_CHECK_ENf, 0); 2526 #if GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED 2527 soc_reg_field_set(unit, MISCCONFIGr, ®val, 2528 ECC_ONE_BIT_ERROR_INT_ENf, 0); 2529 #endif /* GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED */ 2530 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, regval)); 2531 /* Write CMIC disable register */ 2532 (void)soc_cmicm_intr3_disable(unit, cmic_enable); 2533 } 2534 return SOC_E_NONE; 2535 } 2536 #endif /* GREYHOUND_SER_PARITY_ENABLED */ 2537 2538 2539 /* SER processing for TCAMs */ 2540 /* For Ranger2 */ 2541 STATIC _soc_generic_ser_info_t _soc_rg2_tcam_ser_info_template[] = { 2542 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2543 _SOC_SER_INTERLEAVE_MOD2, 2544 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0 }, 2545 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2546 _SOC_SER_INTERLEAVE_MOD2, 2547 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2548 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 2549 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 2550 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0 }, 2551 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2552 _SOC_SER_INTERLEAVE_MOD2, 2553 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0 }, 2554 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2555 _SOC_SER_INTERLEAVE_MOD2, 2556 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2557 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2558 _SOC_SER_INTERLEAVE_MOD2, 2559 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2560 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2561 _SOC_SER_INTERLEAVE_MOD2, 2562 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0 }, 2563 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2564 _SOC_SER_INTERLEAVE_MOD2, 2565 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0 }, 2566 { INVALIDm }, 2567 }; 2568 2569 /* For Greyhound */ 2570 STATIC _soc_generic_ser_info_t _soc_gh_tcam_ser_info_template[] = { 2571 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2572 _SOC_SER_INTERLEAVE_MOD2, 2573 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2574 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 2575 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 2576 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0 }, 2577 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2578 _SOC_SER_INTERLEAVE_MOD2, 2579 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0 }, 2580 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2581 _SOC_SER_INTERLEAVE_MOD2, 2582 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2583 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2584 _SOC_SER_INTERLEAVE_MOD2, 2585 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2586 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2587 _SOC_SER_INTERLEAVE_MOD2, 2588 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0 }, 2589 { INVALIDm }, 2590 }; 2591 2592 /* For Greyhound */ 2593 STATIC _soc_generic_ser_info_t _soc_gh_no_l3_tcam_ser_info_template[] = { 2594 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2595 _SOC_SER_INTERLEAVE_MOD2, 2596 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2597 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 2598 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 2599 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0 }, 2600 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2601 _SOC_SER_INTERLEAVE_MOD2, 2602 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0 }, 2603 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2604 _SOC_SER_INTERLEAVE_MOD2, 2605 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0 }, 2606 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 2607 _SOC_SER_INTERLEAVE_MOD2, 2608 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0 }, 2609 { INVALIDm }, 2610 }; 2611 2612 2613 STATIC int 2614 _soc_greyhound_tcam_ser_init(int unit) 2615 { 2616 if (soc_feature(unit, soc_feature_field_multi_stage)) { 2617 _soc_gh_tcam_ser_info[unit] = _soc_rg2_tcam_ser_info_template; 2618 } else if (soc_feature(unit, soc_feature_l3)){ 2619 _soc_gh_tcam_ser_info[unit] = _soc_gh_tcam_ser_info_template; 2620 } else { 2621 _soc_gh_tcam_ser_info[unit] = _soc_gh_no_l3_tcam_ser_info_template; 2622 } 2623 return soc_generic_ser_init(unit, _soc_gh_tcam_ser_info[unit]); 2624 } 2625 2626 void 2627 soc_greyhound_ser_fail(int unit) 2628 2629 { 2630 soc_generic_ser_process_error(unit, _soc_gh_tcam_ser_info[unit], 0); 2631 } 2632 2633 int 2634 soc_greyhound_ser_mem_clear(int unit, soc_mem_t mem) 2635 { 2636 uint32 range_enable; 2637 int info_ix, hw_enable_ix, i; 2638 _soc_generic_ser_info_t *cur_spi; 2639 ser_memory_entry_t ser_mem; 2640 _soc_generic_ser_info_t *tcam_ser_info; 2641 2642 /* Check if enable */ 2643 SOC_IF_ERROR_RETURN 2644 (READ_SER_RANGE_ENABLEr(unit, &range_enable)); 2645 2646 if (!range_enable) { 2647 return SOC_E_NONE; 2648 } 2649 2650 info_ix = 0; 2651 tcam_ser_info = _soc_gh_tcam_ser_info[unit]; 2652 2653 while (tcam_ser_info[info_ix].mem != INVALIDm) { 2654 if (tcam_ser_info[info_ix].mem == mem) { 2655 break; 2656 } 2657 info_ix++; 2658 } 2659 hw_enable_ix = tcam_ser_info[info_ix].ser_hw_index ; 2660 2661 if ((tcam_ser_info[info_ix].mem != INVALIDm) && 2662 (range_enable & (1 << hw_enable_ix))) { 2663 cur_spi = &(tcam_ser_info[info_ix]); 2664 2665 range_enable &= ~(1 << hw_enable_ix); 2666 /* Disable SER protection on this memory */ 2667 SOC_IF_ERROR_RETURN 2668 (WRITE_SER_RANGE_ENABLEr(unit, range_enable)); 2669 2670 /* Flush SER memory segment for the table */ 2671 sal_memset(&ser_mem, 0, sizeof(ser_mem)); 2672 for (i = cur_spi->ser_section_start; 2673 i <= cur_spi->ser_section_end; 2674 i++) { 2675 SOC_IF_ERROR_RETURN 2676 (WRITE_SER_MEMORYm(unit, MEM_BLOCK_ALL, i, &ser_mem)); 2677 } 2678 2679 range_enable |= (1 << hw_enable_ix); 2680 /* Enable SER protection on this memory */ 2681 SOC_IF_ERROR_RETURN 2682 (WRITE_SER_RANGE_ENABLEr(unit, range_enable)); 2683 2684 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2685 (BSL_META_U(unit, 2686 "\t%s: SER[%d-%d]\n"), 2687 SOC_MEM_NAME(unit, cur_spi->mem), 2688 cur_spi->ser_section_start, cur_spi->ser_section_end)); 2689 } 2690 2691 return SOC_E_NONE; 2692 2693 } 2694 2695 2696 STATIC void 2697 _soc_gh_mem_parity_info(int unit, int block_info_idx, int pipe, 2698 soc_field_t field_enum, uint32 *minfo) 2699 { 2700 *minfo = (SOC_BLOCK2SCH(unit, block_info_idx) << SOC_ERROR_BLK_BP) 2701 | ((pipe & 0xff) << SOC_ERROR_PIPE_BP) 2702 | (field_enum & SOC_ERROR_FIELD_ENUM_MASK); 2703 } 2704 2705 2706 int 2707 _soc_greyhound_mem_parity_control(int unit, soc_mem_t mem, 2708 int copyno, int enable) 2709 { 2710 int group, table; 2711 uint32 misc_cfg; 2712 _soc_gh_parity_info_t *info; 2713 soc_reg_t group_reg, reg; 2714 soc_port_t block_port; 2715 soc_field_t enable_field; 2716 soc_block_t blk; 2717 _soc_gh_parity_group_info_t *parity_group_info; 2718 2719 if (!soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 2720 /* Parity checking is not enabled, nothing to do */ 2721 return SOC_E_NONE; 2722 } 2723 parity_group_info = _soc_gh_parity_group_info[unit]; 2724 if (parity_group_info == NULL) { 2725 return SOC_E_UNAVAIL; 2726 } 2727 2728 /* Convert component/aggregate memories to the table for which 2729 * the parity registers correspond. */ 2730 switch(mem) { 2731 case VLAN_SUBNETm: 2732 mem = VLAN_SUBNET_DATA_ONLYm; /* Should be VLAN_SUBNET? */ 2733 break; 2734 case L2_ENTRY_ONLYm: 2735 mem = L2Xm; 2736 break; 2737 case L2_USER_ENTRY_ONLYm: 2738 case L2_USER_ENTRY_DATA_ONLYm: 2739 mem = L2_USER_ENTRYm; 2740 break; 2741 case L3_DEFIPm: 2742 mem = L3_DEFIP_DATA_ONLYm; 2743 break; 2744 case L3_ENTRY_IPV4_UNICASTm: 2745 case L3_ENTRY_IPV6_UNICASTm: 2746 case L3_ENTRY_IPV4_MULTICASTm: 2747 case L3_ENTRY_IPV6_MULTICASTm: 2748 mem = L3_ENTRY_ONLYm; 2749 break; 2750 case VLAN_MACm: 2751 mem = VLAN_XLATEm; 2752 break; 2753 default: 2754 /* Do nothing, keep memory as provided */ 2755 break; 2756 } 2757 2758 2759 /* loop through each group */ 2760 for (group = 0; parity_group_info[group].cpi_bit; group++) { 2761 info = parity_group_info[group].info; 2762 group_reg = parity_group_info[group].enable_reg; 2763 2764 SOC_BLOCK_ITER(unit, blk, 2765 parity_group_info[group].blocktype) { 2766 if (_soc_greyhound_parity_block_port(unit, blk, &block_port) < 0) { 2767 continue; 2768 } 2769 if ((copyno != MEM_BLOCK_ANY) && (blk != copyno)) { 2770 continue; 2771 } 2772 2773 /* loop through each table in the group */ 2774 for (table = 0; info[table].enable_field != INVALIDf; table++) { 2775 if (mem != info[table].mem) { 2776 continue; 2777 } 2778 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 2779 continue; 2780 } 2781 2782 /* handle different parity error reporting style */ 2783 switch (info[table].type) { 2784 case _SOC_PARITY_INFO_TYPE_GENERIC: 2785 case _SOC_PARITY_INFO_TYPE_MMU_ECC: 2786 case _SOC_PARITY_INFO_TYPE_MMU_XQ: 2787 case _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP: 2788 case _SOC_PARITY_INFO_TYPE_MMU_IPMCVLAN: 2789 case _SOC_PARITY_INFO_TYPE_MMU_WRED: 2790 case _SOC_PARITY_INFO_TYPE_MMU_E2EFC: 2791 case _SOC_PARITY_INFO_TYPE_MMU_CBPPKTHDR: 2792 enable_field = info[table].enable_field; 2793 SOC_IF_ERROR_RETURN 2794 (soc_reg_field32_modify(unit, group_reg, block_port, 2795 enable_field, 2796 enable ? 1 : 0)); 2797 break; 2798 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 2799 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 2800 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 2801 case _SOC_PARITY_INFO_TYPE_COUNTER: 2802 reg = info[table].control_reg; 2803 if (!SOC_REG_IS_VALID(unit, reg)) { 2804 return SOC_E_NONE; 2805 } 2806 SOC_IF_ERROR_RETURN 2807 (soc_reg_field32_modify(unit, reg, block_port, 2808 info[table].enable_field, 2809 enable ? 1 : 0)); 2810 break; 2811 default: 2812 break; 2813 } /* handle different parity error reporting style */ 2814 } /* loop through each table in the group */ 2815 } 2816 } /* loop through each group */ 2817 2818 /* MMU controls */ 2819 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 2820 if (enable) { 2821 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHECK_ENf, 1); 2822 #if GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED 2823 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 2824 ECC_ONE_BIT_ERROR_INT_ENf, 1); 2825 #endif /* GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED */ 2826 } else { 2827 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHECK_ENf, 0); 2828 #if GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED 2829 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 2830 ECC_ONE_BIT_ERROR_INT_ENf, 0); 2831 #endif /* GREYHOUND_SER_ECC_1BIT_ERR_RPT_ENABLED */ 2832 } 2833 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 2834 return SOC_E_NONE; 2835 } 2836 2837 STATIC int 2838 _soc_greyhound_process_single_parity_error(int unit, int group, 2839 soc_port_t block_port, int table, 2840 int schan, char *msg, soc_block_t block) 2841 { 2842 _soc_gh_parity_info_t *info; 2843 soc_reg_t status_reg; 2844 uint32 reg_val; 2845 int index, multiple, error; 2846 uint32 minfo; 2847 _soc_ser_correct_info_t spci; 2848 2849 info = _soc_gh_parity_group_info[unit][group].info; 2850 2851 status_reg = schan ? info[table].nack_status0_reg : 2852 info[table].intr_status0_reg; 2853 if (status_reg == INVALIDr) { 2854 return SOC_E_INTERNAL; 2855 } 2856 SOC_IF_ERROR_RETURN(soc_reg32_get(unit,status_reg, 2857 block_port, 0, ®_val)); 2858 index = soc_reg_field_get(unit, status_reg, reg_val, ENTRY_IDXf); 2859 multiple = soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERRf); 2860 error = soc_reg_field_get(unit, status_reg, reg_val, PARITY_ERRf); 2861 2862 if (error) { 2863 _soc_gh_mem_parity_info(unit, block, 0, 2864 info[table].error_field, &minfo); 2865 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2866 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2867 index, minfo); 2868 LOG_ERROR(BSL_LS_SOC_COMMON, 2869 (BSL_META_U(unit, 2870 "unit %d %s entry %d parity error\n"), 2871 unit, msg, index)); 2872 if (multiple) { 2873 LOG_ERROR(BSL_LS_SOC_COMMON, 2874 (BSL_META_U(unit, 2875 "unit %d %s has multiple parity errors\n"), 2876 unit, msg)); 2877 } 2878 2879 if (info[table].mem != INVALIDm) { 2880 sal_memset(&spci, 0, sizeof(spci)); 2881 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2882 spci.reg = INVALIDr; 2883 spci.mem = info[table].mem; 2884 spci.blk_type = -1; 2885 spci.index = index; 2886 (void)soc_ser_correction(unit, &spci); 2887 } 2888 2889 } else { 2890 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2891 "unit %d %s: parity error is handled.\n"), 2892 unit, msg)); 2893 } 2894 2895 /* Clear parity status */ 2896 SOC_IF_ERROR_RETURN(soc_reg32_set(unit,status_reg, block_port, 0, 0)); 2897 return SOC_E_NONE; 2898 } 2899 2900 STATIC int 2901 _soc_greyhound_process_single_ecc_error(int unit, int group, 2902 soc_port_t block_port, int table, 2903 int schan, char *msg, soc_block_t block) 2904 { 2905 _soc_gh_parity_info_t *info; 2906 soc_reg_t status_reg; 2907 uint32 reg_val; 2908 int index, double_bit, multiple, error; 2909 uint32 minfo; 2910 _soc_ser_correct_info_t spci; 2911 2912 info = _soc_gh_parity_group_info[unit][group].info; 2913 2914 status_reg = schan ? info[table].nack_status0_reg : 2915 info[table].intr_status0_reg; 2916 if (status_reg == INVALIDr) { 2917 return SOC_E_INTERNAL; 2918 } 2919 SOC_IF_ERROR_RETURN( 2920 soc_reg32_get(unit,status_reg, block_port, 0, ®_val)); 2921 index = soc_reg_field_get(unit, status_reg, reg_val, ENTRY_IDXf); 2922 double_bit = soc_reg_field_get(unit, status_reg, 2923 reg_val, DOUBLE_BIT_ERRf); 2924 multiple = soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERRf); 2925 error = soc_reg_field_get(unit, status_reg, reg_val, ECC_ERRf); 2926 2927 if (error) { 2928 _soc_gh_mem_parity_info(unit, block, 0, 2929 info[table].error_field, &minfo); 2930 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2931 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2932 index, minfo); 2933 LOG_ERROR(BSL_LS_SOC_COMMON, 2934 (BSL_META_U(unit, 2935 "unit %d %s entry %d %s ECC error\n"), 2936 unit, msg, index, double_bit ? "double-bit" : "")); 2937 if (multiple) { 2938 LOG_ERROR(BSL_LS_SOC_COMMON, 2939 (BSL_META_U(unit, 2940 "unit %d %s has multiple ECC errors\n"), 2941 unit, msg)); 2942 } 2943 sal_memset(&spci, 0, sizeof(spci)); 2944 if (double_bit) { 2945 spci.double_bit = 1; 2946 } 2947 if (info[table].mem != INVALIDm) { 2948 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2949 spci.reg = INVALIDr; 2950 spci.mem = info[table].mem; 2951 spci.blk_type = -1; 2952 spci.index = index; 2953 spci.parity_type = SOC_PARITY_TYPE_ECC; 2954 (void)soc_ser_correction(unit, &spci); 2955 } 2956 } else { 2957 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2958 "unit %d %s: parity error is handled.\n"), 2959 unit, msg)); 2960 } 2961 2962 /* Clear parity status */ 2963 SOC_IF_ERROR_RETURN(soc_reg32_set(unit,status_reg, block_port, 0, 0)); 2964 return SOC_E_NONE; 2965 } 2966 2967 STATIC int 2968 _soc_greyhound_process_mmu_ecc(int unit, int group, 2969 soc_port_t block_port, int table, 2970 char *msg, soc_block_t block) 2971 { 2972 _soc_gh_parity_info_t *info; 2973 soc_reg_t status_reg; 2974 uint32 reg_val; 2975 int index, double_bit; 2976 uint32 minfo; 2977 2978 info = _soc_gh_parity_group_info[unit][group].info; 2979 2980 status_reg = info[table].intr_status0_reg; 2981 if (status_reg == INVALIDr) { 2982 return SOC_E_INTERNAL; 2983 } 2984 SOC_IF_ERROR_RETURN(soc_reg32_get(unit,status_reg, 2985 block_port, 0, ®_val)); 2986 index = soc_reg_field_get(unit, status_reg, reg_val, ENTRY_INDEXf); 2987 double_bit = soc_reg_field_get(unit, status_reg, 2988 reg_val, DOUBLE_BIT_ERRf); 2989 2990 _soc_gh_mem_parity_info(unit, block, 0, 2991 info[table].error_field, &minfo); 2992 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2993 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2994 index, minfo); 2995 LOG_ERROR(BSL_LS_SOC_COMMON, 2996 (BSL_META_U(unit, 2997 "unit %d %s entry %d %s ECC error\n"), 2998 unit, msg, index, double_bit ? "double-bit" : "")); 2999 3000 return SOC_E_NONE; 3001 } 3002 3003 3004 STATIC int 3005 _soc_greyhound_process_dual_parity_error(int unit, int group, 3006 soc_port_t block_port, int table, 3007 int schan, char *msg, soc_block_t block) 3008 { 3009 _soc_gh_parity_info_t *info; 3010 soc_reg_t status_reg; 3011 uint32 reg_val, bitmap = 0; 3012 int index, bucket_index = 0, multiple = 0, ix, bits, size = 0; 3013 _soc_ser_correct_info_t spci; 3014 uint32 minfo; 3015 3016 info = _soc_gh_parity_group_info[unit][group].info; 3017 3018 for (ix = 0; ix < 2; ix ++) { 3019 if (ix == 1) { 3020 status_reg = schan ? info[table].nack_status1_reg : 3021 info[table].intr_status1_reg; 3022 } else { 3023 status_reg = schan ? info[table].nack_status0_reg : 3024 info[table].intr_status0_reg; 3025 } 3026 3027 if (status_reg == INVALIDr) { 3028 continue; 3029 } 3030 3031 SOC_IF_ERROR_RETURN(soc_reg32_get(unit,status_reg, 3032 block_port, 0, ®_val)); 3033 if (soc_reg_field_valid(unit, status_reg, BUCKET_IDXf)) { 3034 bucket_index = 3035 soc_reg_field_get(unit, status_reg, reg_val, BUCKET_IDXf); 3036 multiple = 3037 soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERRf); 3038 bitmap = 3039 soc_reg_field_get(unit, status_reg, reg_val, PARITY_ERR_BMf); 3040 size = soc_reg_field_length(unit, status_reg, PARITY_ERR_BMf); 3041 } else if (soc_reg_field_valid(unit, status_reg, BUCKET_IDX_0f)) { 3042 bucket_index = 3043 soc_reg_field_get(unit, status_reg, reg_val, BUCKET_IDX_0f); 3044 multiple = 3045 soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERR_0f); 3046 bitmap = 3047 soc_reg_field_get(unit, status_reg, reg_val, PARITY_ERR_BM_0f); 3048 size = soc_reg_field_length(unit, status_reg, PARITY_ERR_BM_0f); 3049 } else if (soc_reg_field_valid(unit, status_reg, BUCKET_IDX_1f)) { 3050 bucket_index = 3051 soc_reg_field_get(unit, status_reg, reg_val, BUCKET_IDX_1f); 3052 multiple = 3053 soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERR_1f); 3054 bitmap = 3055 soc_reg_field_get(unit, status_reg, reg_val, PARITY_ERR_BM_1f); 3056 size = soc_reg_field_length(unit, status_reg, PARITY_ERR_BM_1f); 3057 } 3058 3059 3060 if (multiple) { 3061 LOG_ERROR(BSL_LS_SOC_COMMON, 3062 (BSL_META_U(unit, 3063 "unit %d %s has multiple parity errors\n"), 3064 unit, msg)); 3065 } 3066 3067 if (bitmap != 0) { 3068 for (bits = 0; bits < size; bits++) { 3069 if (bitmap & (1 << bits)) { 3070 index = 3071 bucket_index * size * 2 + bits + (ix * size); 3072 _soc_gh_mem_parity_info(unit, block, 0, 3073 info[table].error_field, &minfo); 3074 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3075 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 3076 index, minfo); 3077 LOG_ERROR(BSL_LS_SOC_COMMON, 3078 (BSL_META_U(unit, 3079 "unit %d %s entry %d parity error\n"), 3080 unit, msg, index)); 3081 if (info[table].mem != INVALIDm) { 3082 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 3083 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 3084 spci.reg = INVALIDr; 3085 spci.mem = info[table].mem; 3086 spci.blk_type = block; 3087 spci.index = index; 3088 (void)soc_ser_correction(unit, &spci); 3089 } 3090 } 3091 } 3092 } 3093 3094 /* Clear parity status */ 3095 SOC_IF_ERROR_RETURN(soc_reg32_set(unit,status_reg, block_port, 0, 0)); 3096 } 3097 3098 return SOC_E_NONE; 3099 } 3100 3101 STATIC int 3102 _soc_greyhound_process_mmu_xq(int unit, int group, 3103 soc_port_t block_port, int table, 3104 char *msg, soc_block_t block) 3105 { 3106 _soc_gh_parity_info_t *info; 3107 soc_reg_t err_reg; 3108 uint32 reg_val, valid_val, entry_index, double_err, multiple; 3109 uint32 minfo; 3110 soc_port_t port; 3111 3112 info = _soc_gh_parity_group_info[unit][group].info; 3113 3114 /* CHECK if the error is valid */ 3115 err_reg = info[table].level2_error_vld_reg; 3116 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3117 block_port, 0, ®_val)); 3118 valid_val = 3119 soc_reg_field_get(unit, err_reg, reg_val, ERR_VALIDf); 3120 if (valid_val == 0) { 3121 LOG_ERROR(BSL_LS_SOC_COMMON, 3122 (BSL_META_U(unit, 3123 "unit %d %s: parity hardware inconsistency\n"), 3124 unit, msg)); 3125 return SOC_E_NONE; 3126 } 3127 3128 port = 0; 3129 while (!(valid_val & (0x1 << port))) { 3130 port++; 3131 } 3132 3133 err_reg = info[table].level2_error_reg; 3134 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3135 port, 0, ®_val)); 3136 entry_index = 3137 soc_reg_field_get(unit, err_reg, reg_val, ENTRY_INDEXf); 3138 double_err = 3139 soc_reg_field_get(unit, err_reg, reg_val, DOUBLE_BIT_ERRf); 3140 err_reg = info[table].level2_error_multi_reg; 3141 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3142 port, 0, ®_val)); 3143 multiple = 3144 soc_reg_field_get(unit, err_reg, reg_val, MULTIPLE_ERRf); 3145 3146 _soc_gh_mem_parity_info(unit, block, 0, 3147 info[table].error_field, &minfo); 3148 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3149 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 3150 entry_index, minfo); 3151 3152 LOG_ERROR(BSL_LS_SOC_COMMON, 3153 (BSL_META_U(unit, 3154 "unit %d %s port %d entry %d %s ECC error\n"), 3155 unit, msg, port, entry_index, double_err ? "double-bit" : "")); 3156 if (multiple) { 3157 LOG_ERROR(BSL_LS_SOC_COMMON, 3158 (BSL_META_U(unit, 3159 "unit %d %s has multiple ECC errors\n"), 3160 unit, msg)); 3161 } 3162 3163 /* Clear interrupt status */ 3164 err_reg = info[table].level2_error_clear_reg; 3165 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3166 block_port, 0, ®_val)); 3167 soc_reg_field_set(unit, err_reg, ®_val, 3168 CLR_ERRf, valid_val); 3169 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, err_reg, 3170 block_port, 0, reg_val)); 3171 3172 3173 return SOC_E_NONE; 3174 } 3175 3176 #define _SOC_GH_MMU_IPMC_GROUP_MAX 30 3177 static soc_mem_t ipmc_mems[_SOC_GH_MMU_IPMC_GROUP_MAX] = { 3178 INVALIDm, INVALIDm, 3179 MMU_IPMC_GROUP_TBL2m, MMU_IPMC_GROUP_TBL3m, 3180 MMU_IPMC_GROUP_TBL4m, MMU_IPMC_GROUP_TBL5m, 3181 MMU_IPMC_GROUP_TBL6m, MMU_IPMC_GROUP_TBL7m, 3182 MMU_IPMC_GROUP_TBL8m, MMU_IPMC_GROUP_TBL9m, 3183 MMU_IPMC_GROUP_TBL10m, MMU_IPMC_GROUP_TBL11m, 3184 MMU_IPMC_GROUP_TBL12m, MMU_IPMC_GROUP_TBL13m, 3185 MMU_IPMC_GROUP_TBL14m, MMU_IPMC_GROUP_TBL15m, 3186 MMU_IPMC_GROUP_TBL16m, MMU_IPMC_GROUP_TBL17m, 3187 MMU_IPMC_GROUP_TBL18m, MMU_IPMC_GROUP_TBL19m, 3188 MMU_IPMC_GROUP_TBL20m, MMU_IPMC_GROUP_TBL21m, 3189 MMU_IPMC_GROUP_TBL22m, MMU_IPMC_GROUP_TBL23m, 3190 MMU_IPMC_GROUP_TBL24m, MMU_IPMC_GROUP_TBL25m, 3191 MMU_IPMC_GROUP_TBL26m, MMU_IPMC_GROUP_TBL27m, 3192 MMU_IPMC_GROUP_TBL28m, MMU_IPMC_GROUP_TBL29m 3193 }; 3194 3195 STATIC int 3196 _soc_greyhound_process_mmu_ipmcgroup_error(int unit, int group, 3197 soc_port_t block_port, int table, 3198 char *msg, soc_block_t block) 3199 { 3200 _soc_gh_parity_info_t *info; 3201 soc_reg_t err_reg; 3202 uint32 reg_val, valid_val, entry_index, double_err, multiple, multi_regval; 3203 uint32 minfo; 3204 int i; 3205 _soc_ser_correct_info_t spci; 3206 3207 info = _soc_gh_parity_group_info[unit][group].info; 3208 3209 err_reg = IPMC_GROUP_ERR_VLDr; 3210 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3211 block_port, 0, ®_val)); 3212 valid_val = 3213 soc_reg_field_get(unit, err_reg, reg_val, ERR_VALIDf); 3214 3215 /* CHECK if the error is valid */ 3216 if (valid_val == 0) { 3217 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3218 "unit %d %s: parity error is handled.\n"), 3219 unit, msg)); 3220 return SOC_E_NONE; 3221 } 3222 3223 /* Get the Multiple error register value */ 3224 err_reg = IPMC_GROUP_MULTI_ERRr; 3225 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3226 REG_PORT_ANY, 0, &multi_regval)); 3227 3228 for (i = 0; i < _SOC_GH_MMU_IPMC_GROUP_MAX; i++) { 3229 if (valid_val & (1 << i)) { 3230 err_reg = IPMC_GROUP_ERR_PTRr; 3231 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3232 i, 0, ®_val)); 3233 entry_index = 3234 soc_reg_field_get(unit, err_reg, reg_val, ENTRY_INDEXf); 3235 double_err = 3236 soc_reg_field_get(unit, err_reg, reg_val, DOUBLE_BIT_ERRf); 3237 3238 multiple = multi_regval & (1 << i); 3239 _soc_gh_mem_parity_info(unit, block, 0, 3240 info[table].error_field, &minfo); 3241 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3242 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 3243 entry_index, minfo); 3244 LOG_ERROR(BSL_LS_SOC_COMMON, 3245 (BSL_META_U(unit, 3246 "unit %d IPMC GROUP%d entry %d %s ECC error\n"), 3247 unit, i, entry_index, double_err ? "double-bit" : "")); 3248 if (multiple) { 3249 LOG_ERROR(BSL_LS_SOC_COMMON, 3250 (BSL_META_U(unit, 3251 "unit %d IPMC GROUP%d has multiple ECC errors\n"), 3252 unit, i)); 3253 } 3254 if (ipmc_mems[i] != INVALIDm) { 3255 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 3256 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 3257 spci.reg = INVALIDr; 3258 spci.mem = ipmc_mems[i]; 3259 spci.blk_type = SOC_BLK_MMU; 3260 spci.index = entry_index; 3261 (void)soc_ser_correction(unit, &spci); 3262 } 3263 } 3264 } 3265 3266 3267 /* Clear interrupt status */ 3268 err_reg = IPMC_GROUP_ERR_CLRr; 3269 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3270 block_port, 0, ®_val)); 3271 soc_reg_field_set(unit, err_reg, ®_val, 3272 CLR_ERRf, valid_val); 3273 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, err_reg, 3274 block_port, 0, reg_val)); 3275 3276 3277 return SOC_E_NONE; 3278 } 3279 3280 3281 STATIC int 3282 _soc_greyhound_process_mmu_ipmcvlan_error(int unit, int group, 3283 soc_port_t block_port, int table, 3284 char *msg, soc_block_t block) 3285 { 3286 3287 _soc_gh_parity_info_t *info; 3288 soc_reg_t err_reg; 3289 uint32 reg_val, entry_index, double_err; 3290 uint32 minfo; 3291 _soc_ser_correct_info_t spci; 3292 3293 info = _soc_gh_parity_group_info[unit][group].info; 3294 3295 err_reg = IPMCPARITYERRORPTRr; 3296 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3297 block_port, 0, ®_val)); 3298 entry_index = 3299 soc_reg_field_get(unit, err_reg, reg_val, ENTRY_INDEXf); 3300 double_err = 3301 soc_reg_field_get(unit, err_reg, reg_val, DOUBLE_BIT_ERRf); 3302 3303 _soc_gh_mem_parity_info(unit, block, 0, 3304 info[table].error_field, &minfo); 3305 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3306 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 3307 entry_index, minfo); 3308 LOG_ERROR(BSL_LS_SOC_COMMON, 3309 (BSL_META_U(unit, 3310 "unit %d MMU_IPMC VLAN entry %d %s ECC error\n"), 3311 unit, entry_index, double_err ? "double-bit" : "")); 3312 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 3313 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 3314 spci.reg = INVALIDr; 3315 spci.mem = MMU_IPMC_VLAN_TBLm; 3316 spci.blk_type = SOC_BLK_MMU; 3317 spci.index = entry_index; 3318 (void)soc_ser_correction(unit, &spci); 3319 3320 return SOC_E_NONE; 3321 } 3322 3323 STATIC int 3324 _soc_greyhound_process_mmu_wred_error(int unit, int group, 3325 soc_port_t block_port, int table, 3326 char *msg, soc_block_t block) 3327 { 3328 #define _SOC_GH_MMU_WRED_MAX 9 3329 static soc_mem_t wred_mems[_SOC_GH_MMU_WRED_MAX] = { 3330 MMU_WRED_MARK_THDm, 3331 MMU_WRED_DROP_PROFILE_GREENm, 3332 MMU_WRED_DROP_PROFILE_YELLOWm, 3333 MMU_WRED_DROP_PROFILE_REDm, 3334 MMU_WRED_MARK_PROFILE_GREENm, 3335 MMU_WRED_MARK_PROFILE_YELLOWm, 3336 MMU_WRED_MARK_PROFILE_REDm, 3337 MMU_WRED_AVG_QSIZEm, 3338 MMU_WRED_CONFIGm 3339 }; 3340 static soc_reg_t wred_regs[_SOC_GH_MMU_WRED_MAX] = { 3341 WRED_MARK_THD_PARITY_ERR_PTRr, 3342 WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr, 3343 WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTRr, 3344 WRED_DROP_PROFILE_RED_PARITY_ERR_PTRr, 3345 WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTRr, 3346 WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTRr, 3347 WRED_MARK_PROFILE_RED_PARITY_ERR_PTRr, 3348 WRED_AVG_QSIZE_PARITY_ERR_PTRr, 3349 WRED_CONFIG_PARITY_ERR_PTRr 3350 }; 3351 3352 3353 _soc_gh_parity_info_t *info; 3354 soc_reg_t err_reg; 3355 uint32 reg_val, valid_val, entry_index, multi_err, multiple; 3356 uint32 minfo; 3357 _soc_ser_correct_info_t spci; 3358 int i; 3359 3360 info = _soc_gh_parity_group_info[unit][group].info; 3361 3362 err_reg = WRED_PARITY_ERR_STATUSr; 3363 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3364 block_port, 0, ®_val)); 3365 valid_val = 3366 soc_reg_field_get(unit, err_reg, reg_val, ERR_VALIDf); 3367 /* CHECK if the error is valid */ 3368 if (valid_val == 0) { 3369 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3370 "unit %d %s: parity error is handled.\n"), 3371 unit, msg)); 3372 return SOC_E_NONE; 3373 } 3374 multiple = 3375 soc_reg_field_get(unit, err_reg, reg_val, MULTIPLE_ERRf); 3376 3377 for (i = 0; i < _SOC_GH_MMU_WRED_MAX; i++) { 3378 if (valid_val & (1 << i)) { 3379 err_reg = wred_regs[i]; 3380 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3381 block_port, 0, ®_val)); 3382 entry_index = 3383 soc_reg_field_get(unit, err_reg, reg_val, ENTRY_INDEXf); 3384 multi_err = (multiple & (i << 1)); 3385 _soc_gh_mem_parity_info(unit, block, 0, 3386 info[table].error_field, &minfo); 3387 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3388 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 3389 entry_index, minfo); 3390 LOG_ERROR(BSL_LS_SOC_COMMON, 3391 (BSL_META_U(unit, 3392 "unit %d %s entry %d parity error\n"), 3393 unit, SOC_MEM_NAME(unit, wred_mems[i]), 3394 entry_index)); 3395 if (multi_err) { 3396 LOG_ERROR(BSL_LS_SOC_COMMON, 3397 (BSL_META_U(unit, 3398 "unit %d %s has multiple parity errors\n"), 3399 unit, SOC_MEM_NAME(unit, wred_mems[i]))); 3400 } 3401 3402 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 3403 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 3404 spci.reg = INVALIDr; 3405 spci.mem = wred_mems[i]; 3406 spci.blk_type = SOC_BLK_MMU; 3407 spci.index = entry_index; 3408 (void)soc_ser_correction(unit, &spci); 3409 } 3410 } 3411 3412 /* Clear level 2 error status */ 3413 err_reg = WRED_ERR_CLRr; 3414 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3415 block_port, 0, ®_val)); 3416 soc_reg_field_set(unit, err_reg, ®_val, 3417 CLR_ERRf, valid_val); 3418 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, err_reg, 3419 block_port, 0, reg_val)); 3420 3421 return SOC_E_NONE; 3422 } 3423 3424 STATIC int 3425 _soc_greyhound_process_mmu_e2efc_error(int unit, int group, 3426 soc_port_t block_port, int table, 3427 char *msg, soc_block_t block) 3428 { 3429 #define _SOC_GH_MMU_E2EFC_MAX 4 3430 static soc_reg_t e2efc_regs[_SOC_GH_MMU_E2EFC_MAX] = { 3431 INVALIDr, 3432 E2EFC_CNT_SET_LIMITr, 3433 E2EFC_CNT_RESET_LIMITr, 3434 E2EFC_CNT_DISC_LIMITr 3435 }; 3436 3437 3438 _soc_gh_parity_info_t *info; 3439 soc_reg_t err_reg; 3440 uint32 reg_val, entry_index, mem_id; 3441 uint32 minfo; 3442 _soc_ser_correct_info_t spci; 3443 3444 info = _soc_gh_parity_group_info[unit][group].info; 3445 3446 err_reg = E2EFC_PARITYERRORPTRr; 3447 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3448 block_port, 0, ®_val)); 3449 mem_id = 3450 soc_reg_field_get(unit, err_reg, reg_val, MEM_IDf); 3451 /* CHECK if the error is valid */ 3452 if (mem_id == 0) { 3453 LOG_ERROR(BSL_LS_SOC_COMMON, 3454 (BSL_META_U(unit, 3455 "unit %d %s: parity hardware inconsistency\n"), 3456 unit, msg)); 3457 return SOC_E_NONE; 3458 } 3459 entry_index = 3460 soc_reg_field_get(unit, err_reg, reg_val, ENTRY_INDEXf); 3461 3462 _soc_gh_mem_parity_info(unit, block, 0, 3463 info[table].error_field, &minfo); 3464 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3465 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 3466 entry_index, minfo); 3467 LOG_ERROR(BSL_LS_SOC_COMMON, 3468 (BSL_META_U(unit, 3469 "unit %d MMU E2EFC entry %d parity error\n"), 3470 unit, entry_index)); 3471 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 3472 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 3473 spci.reg = e2efc_regs[mem_id]; 3474 spci.mem = INVALIDm; 3475 spci.blk_type = SOC_BLK_MMU; 3476 spci.index = entry_index; 3477 (void)soc_ser_correction(unit, &spci); 3478 3479 return SOC_E_NONE; 3480 } 3481 3482 3483 STATIC int 3484 _soc_greyhound_process_mmu_cbppkthdr_error(int unit, int group, 3485 soc_port_t block_port, int table, 3486 char *msg, soc_block_t block) 3487 { 3488 #define _SOC_GH_MMU_CBPPKTHDR_MAX 4 3489 static soc_reg_t cbppkthdr_regs[_SOC_GH_MMU_CBPPKTHDR_MAX] = { 3490 CBPPKTHDR_ERRPTR0r, 3491 CBPPKTHDR_ERRPTR1r, 3492 CBPPKTHDR_ERRPTR2r, 3493 CBPPKTHDR_ERRPTR3r 3494 }; 3495 3496 _soc_gh_parity_info_t *info; 3497 soc_reg_t err_reg; 3498 uint32 reg_val, valid_val, entry_index, double_err, multiple, multi_err; 3499 uint32 minfo; 3500 int i; 3501 3502 info = _soc_gh_parity_group_info[unit][group].info; 3503 3504 /* CHECK if the error is valid */ 3505 err_reg = CBPPKTHDR_ERR_VLDr; 3506 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3507 block_port, 0, ®_val)); 3508 valid_val = 3509 soc_reg_field_get(unit, err_reg, reg_val, ERR_VALIDf); 3510 if (valid_val == 0) { 3511 LOG_ERROR(BSL_LS_SOC_COMMON, 3512 (BSL_META_U(unit, 3513 "unit %d %s: parity hardware inconsistency\n"), 3514 unit, msg)); 3515 return SOC_E_NONE; 3516 } 3517 3518 multiple = 3519 soc_reg_field_get(unit, err_reg, reg_val, MULTIPLE_ERRf); 3520 3521 for (i = 0; i < _SOC_GH_MMU_CBPPKTHDR_MAX; i++) { 3522 if (valid_val & (1 << i)) { 3523 err_reg = cbppkthdr_regs[i]; 3524 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3525 block_port, 0, ®_val)); 3526 entry_index = 3527 soc_reg_field_get(unit, err_reg, reg_val, ENTRY_INDEXf); 3528 double_err = 3529 soc_reg_field_get(unit, err_reg, reg_val, DOUBLE_BIT_ERRf); 3530 multi_err = (multiple & (i << 1)); 3531 _soc_gh_mem_parity_info(unit, block, 0, 3532 info[table].error_field, &minfo); 3533 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3534 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 3535 entry_index, minfo); 3536 LOG_ERROR(BSL_LS_SOC_COMMON, 3537 (BSL_META_U(unit, 3538 "unit %d CBPPKTHDR %d entry %d %s ECC error\n"), 3539 unit, i, entry_index, double_err ? "double-bit" : "")); 3540 if (multi_err) { 3541 LOG_ERROR(BSL_LS_SOC_COMMON, 3542 (BSL_META_U(unit, 3543 "unit %d CBPPKTHDR %d has multiple ECC errors\n"), 3544 unit, i)); 3545 } 3546 } 3547 } 3548 3549 3550 /* Clear level 2 status */ 3551 err_reg = CBPPKTHDR_ERR_CLRr; 3552 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3553 block_port, 0, ®_val)); 3554 soc_reg_field_set(unit, err_reg, ®_val, 3555 CLR_ERRf, valid_val); 3556 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, err_reg, 3557 block_port, 0, reg_val)); 3558 3559 3560 return SOC_E_NONE; 3561 } 3562 3563 STATIC int 3564 _soc_greyhound_process_port_macro_error(int unit, int group, 3565 soc_port_t block_port, int table, 3566 char *msg, soc_block_t block) 3567 { 3568 3569 _soc_gh_parity_info_t *info; 3570 soc_reg_t err_reg; 3571 uint32 reg_val, err; 3572 uint32 minfo; 3573 3574 info = _soc_gh_parity_group_info[unit][group].info; 3575 3576 err_reg = XLPORT_INTR_STATUSr; 3577 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, err_reg, 3578 block_port, 0, ®_val)); 3579 3580 /* Check errors */ 3581 err = soc_reg_field_get(unit, err_reg, reg_val, TSC_ERRf); 3582 if (err) { 3583 LOG_ERROR(BSL_LS_SOC_COMMON, 3584 (BSL_META_U(unit, 3585 "unit %d port macro ECC error on TSC.\n"), 3586 unit)); 3587 } 3588 err = soc_reg_field_get(unit, err_reg, reg_val, MAC_RX_CDC_MEM_ERRf); 3589 if (err) { 3590 LOG_ERROR(BSL_LS_SOC_COMMON, 3591 (BSL_META_U(unit, 3592 "unit %d port macro ECC error on MAC RX CDC memory.\n"), 3593 unit)); 3594 } 3595 err = soc_reg_field_get(unit, err_reg, reg_val, MAC_TX_CDC_MEM_ERRf); 3596 if (err) { 3597 LOG_ERROR(BSL_LS_SOC_COMMON, 3598 (BSL_META_U(unit, 3599 "unit %d port macro ECC error on MAC TX CDC memory.\n"), 3600 unit)); 3601 } 3602 err = soc_reg_field_get(unit, err_reg, reg_val, MIB_RX_MEM_ERRf); 3603 if (err) { 3604 LOG_ERROR(BSL_LS_SOC_COMMON, 3605 (BSL_META_U(unit, 3606 "unit %d port macro ECC error on MIB RX STAT counter memory.\n"), 3607 unit)); 3608 } 3609 err = soc_reg_field_get(unit, err_reg, reg_val, MIB_TX_MEM_ERRf); 3610 if (err) { 3611 LOG_ERROR(BSL_LS_SOC_COMMON, 3612 (BSL_META_U(unit, 3613 "unit %d port macro ECC error on MIB TX STAT counter memory.\n"), 3614 unit)); 3615 } 3616 3617 /* report error */ 3618 _soc_gh_mem_parity_info(unit, block, 0, 3619 info[table].error_field, &minfo); 3620 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3621 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 3622 0, minfo); 3623 3624 return SOC_E_NONE; 3625 } 3626 3627 3628 STATIC int 3629 _soc_greyhound_process_counter_error(int unit, int group, 3630 soc_port_t block_port, int table, 3631 char *msg, soc_block_t block) 3632 { 3633 soc_cmap_t *cmap; 3634 soc_reg_t reg, counter_reg; 3635 uint32 reg_val, minfo; 3636 uint32 multiple, counter_idx, port_idx, entry_idx; 3637 char *counter_name; 3638 _soc_ser_correct_info_t spci; 3639 3640 _soc_gh_parity_info_t *info; 3641 3642 3643 info = _soc_gh_parity_group_info[unit][group].info; 3644 reg = info[table].intr_status0_reg; 3645 3646 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, 3647 block_port, 0, ®_val)); 3648 3649 if (soc_reg_field_get(unit, reg, reg_val, PARITY_ERRf)) { 3650 multiple = soc_reg_field_get(unit, reg, reg_val, MULTIPLE_ERRf); 3651 counter_idx = soc_reg_field_get(unit, reg, reg_val, COUNTER_IDXf); 3652 port_idx = soc_reg_field_get(unit, reg, reg_val, PORT_IDXf); 3653 entry_idx = soc_reg_field_get(unit, reg, reg_val, ENTRY_IDXf); 3654 3655 /* TDBGC starts at index 0x20 of counter DMA table */ 3656 if (info[table].error_field == EGR_STATS_COUNTER_TABLE_PAR_ERRf) { 3657 counter_idx += 0x20; 3658 } 3659 cmap = soc_port_cmap_get(unit, port_idx); 3660 counter_reg = cmap->cmap_base[counter_idx].reg; 3661 if (SOC_REG_IS_VALID(unit, counter_reg)) { 3662 _soc_gh_mem_parity_info(unit, block, 0, 3663 info[table].error_field, &minfo); 3664 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3665 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 3666 entry_idx, minfo); 3667 counter_name = SOC_REG_NAME(unit, counter_reg); 3668 LOG_ERROR(BSL_LS_SOC_COMMON, 3669 (BSL_META_U(unit, 3670 "EGR STAT COUNTER port %d %s entry %d parity error\n"), 3671 port_idx, counter_name, 3672 entry_idx)); 3673 sal_memset(&spci, 0, sizeof(spci)); 3674 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 3675 spci.mem = INVALIDm; 3676 spci.port = port_idx; 3677 spci.index = 0; 3678 spci.reg = counter_reg; 3679 spci.blk_type = block; 3680 (void)soc_ser_correction(unit, &spci); 3681 if (multiple) { 3682 LOG_ERROR(BSL_LS_SOC_COMMON, 3683 (BSL_META_U(unit, 3684 "EGR STAT COUNTER has multiple parity errors\n"))); 3685 } 3686 } else { 3687 LOG_ERROR(BSL_LS_SOC_COMMON, 3688 (BSL_META_U(unit, 3689 "EGR STAT COUNTER parity hardware inconsistency\n"))); 3690 } 3691 } else { 3692 LOG_ERROR(BSL_LS_SOC_COMMON, 3693 (BSL_META_U(unit, 3694 "EGR_STAT_COUNTER parity hardware inconsistency\n"))); 3695 } 3696 3697 /* Clear parity status */ 3698 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, block_port, 0, 0)); 3699 3700 return SOC_E_NONE; 3701 } 3702 3703 3704 STATIC int 3705 _soc_greyhound_process_parity_error(int unit) 3706 { 3707 int group, table, reg_is_64, blk_num = 0; 3708 uint32 cmic_rval, group_status, 3709 group_enable, cpi_blk_bit, group_clr; 3710 _soc_gh_parity_info_t *info; 3711 soc_reg_t group_reg, reg; 3712 soc_port_t block_port; 3713 soc_block_t blk; 3714 char *msg; 3715 uint64 group_status64, group_enable64, temp64; 3716 uint32 minfo; 3717 _soc_gh_parity_group_info_t *parity_group_info; 3718 3719 /* Read CMIC parity status register */ 3720 /* coverity[result_independent_of_operands] */ 3721 SOC_IF_ERROR_RETURN 3722 (READ_CMIC_CMC0_IRQ_STAT3r(unit, &cmic_rval)); 3723 if (cmic_rval == 0) { 3724 return SOC_E_NONE; 3725 } 3726 3727 parity_group_info = _soc_gh_parity_group_info[unit]; 3728 if (parity_group_info == NULL) { 3729 LOG_CLI((BSL_META_U(unit, 3730 "unit %d the parity error can't be handled.\n"), unit)); 3731 return SOC_E_UNAVAIL; 3732 } 3733 3734 /* loop through each group */ 3735 for (group = 0; parity_group_info[group].cpi_bit; group++) { 3736 info = parity_group_info[group].info; 3737 group_reg = parity_group_info[group].status_reg; 3738 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3739 (BSL_META_U(unit, 3740 "unit %d %s parity processing\n"), 3741 unit, SOC_REG_NAME(unit, group_reg))); 3742 reg_is_64 = SOC_REG_IS_64(unit,group_reg) ? 1 : 0; 3743 cpi_blk_bit = parity_group_info[group].cpi_bit; 3744 3745 SOC_BLOCK_ITER(unit, blk, 3746 parity_group_info[group].blocktype) { 3747 if (_soc_greyhound_parity_block_port(unit, blk, &block_port) < 0) { 3748 continue; 3749 } 3750 3751 if (parity_group_info[group].blocktype == SOC_BLK_XLPORT) { 3752 blk_num = SOC_BLOCK_INFO(unit, blk).number; 3753 if (blk_num == 5) { 3754 info = _soc_gh_gx_parity_info; 3755 group_reg = PGW_GX_INTR_STATUSr; 3756 } 3757 cpi_blk_bit = (cpi_blk_bit << blk_num); 3758 } 3759 3760 if (!(cmic_rval & cpi_blk_bit)) { 3761 continue; 3762 } 3763 3764 if (reg_is_64) { 3765 SOC_IF_ERROR_RETURN(soc_reg64_get( 3766 unit, group_reg, block_port, 0, &group_status64)); 3767 } else { 3768 SOC_IF_ERROR_RETURN(soc_reg32_get( 3769 unit, group_reg, block_port, 0, &group_status)); 3770 } 3771 3772 /* loop through each table in the group */ 3773 for (table = 0; info[table].error_field != INVALIDf; table++) { 3774 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 3775 continue; 3776 } 3777 if (!soc_reg_field_valid(unit, group_reg, 3778 info[table].error_field)) { 3779 if (info[table].mem != INVALIDm) { 3780 LOG_ERROR(BSL_LS_SOC_COMMON, 3781 (BSL_META_U(unit, 3782 "unit %d %s has bad error field\n"), 3783 unit, SOC_MEM_NAME(unit, info[table].mem))); 3784 } 3785 continue; 3786 } 3787 3788 if (reg_is_64) { 3789 if (!soc_reg64_field32_get(unit, group_reg, group_status64, 3790 info[table].error_field)) { 3791 continue; 3792 } 3793 } else { 3794 if (!soc_reg_field_get(unit, group_reg, group_status, 3795 info[table].error_field)) { 3796 continue; 3797 } 3798 } 3799 if (info[table].msg) { 3800 msg = info[table].msg; 3801 } else if (info[table].mem != INVALIDm) { 3802 msg = SOC_MEM_NAME(unit, info[table].mem); 3803 } else { 3804 msg = SOC_FIELD_NAME(unit, info[table].error_field); 3805 } 3806 3807 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3808 (BSL_META_U(unit, 3809 "unit %d %s analysis\n"), 3810 unit, msg)); 3811 3812 /* handle different parity error reporting style */ 3813 switch (info[table].type) { 3814 case _SOC_PARITY_INFO_TYPE_GENERIC: 3815 _soc_gh_mem_parity_info(unit, blk, 3816 0, info[table].error_field , &minfo); 3817 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3818 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 0, 3819 minfo); 3820 LOG_ERROR(BSL_LS_SOC_COMMON, 3821 (BSL_META_U(unit, 3822 "unit %d %s asserted\n"), 3823 unit, msg)); 3824 break; 3825 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 3826 SOC_IF_ERROR_RETURN 3827 (_soc_greyhound_process_single_parity_error(unit, 3828 group, block_port, table, FALSE, msg, blk)); 3829 break; 3830 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 3831 SOC_IF_ERROR_RETURN 3832 (_soc_greyhound_process_single_ecc_error(unit, 3833 group, block_port, table, FALSE, msg, blk)); 3834 break; 3835 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 3836 SOC_IF_ERROR_RETURN 3837 (_soc_greyhound_process_dual_parity_error(unit, 3838 group, block_port, table, FALSE, msg, blk)); 3839 break; 3840 case _SOC_PARITY_INFO_TYPE_MMU_ECC: 3841 SOC_IF_ERROR_RETURN 3842 (_soc_greyhound_process_mmu_ecc(unit, 3843 group, block_port, table, msg, blk)); 3844 break; 3845 case _SOC_PARITY_INFO_TYPE_MMU_XQ: 3846 SOC_IF_ERROR_RETURN 3847 (_soc_greyhound_process_mmu_xq(unit, 3848 group, block_port, table, msg, blk)); 3849 break; 3850 case _SOC_PARITY_INFO_TYPE_MMU_IPMCGROUP: 3851 SOC_IF_ERROR_RETURN 3852 (_soc_greyhound_process_mmu_ipmcgroup_error(unit, 3853 group, block_port, table, msg, blk)); 3854 break; 3855 case _SOC_PARITY_INFO_TYPE_MMU_IPMCVLAN: 3856 SOC_IF_ERROR_RETURN 3857 (_soc_greyhound_process_mmu_ipmcvlan_error(unit, 3858 group, block_port, table, msg, blk)); 3859 break; 3860 3861 case _SOC_PARITY_INFO_TYPE_MMU_WRED: 3862 SOC_IF_ERROR_RETURN 3863 (_soc_greyhound_process_mmu_wred_error(unit, 3864 group, block_port, table, msg, blk)); 3865 break; 3866 case _SOC_PARITY_INFO_TYPE_MMU_E2EFC: 3867 SOC_IF_ERROR_RETURN 3868 (_soc_greyhound_process_mmu_e2efc_error(unit, 3869 group, block_port, table, msg, blk)); 3870 break; 3871 case _SOC_PARITY_INFO_TYPE_MMU_CBPPKTHDR: 3872 SOC_IF_ERROR_RETURN 3873 (_soc_greyhound_process_mmu_cbppkthdr_error(unit, 3874 group, block_port, table, msg, blk)); 3875 break; 3876 case _SOC_PARITY_INFO_TYPE_COUNTER: 3877 SOC_IF_ERROR_RETURN 3878 (_soc_greyhound_process_counter_error(unit, 3879 group, block_port, table, msg, blk)); 3880 break; 3881 3882 case _SOC_PARITY_INFO_TYPE_OAM: 3883 SOC_IF_ERROR_RETURN 3884 (_soc_gh_process_oam_interrupt(unit)); 3885 break; 3886 case _SOC_PARITY_INFO_TYPE_PORT_MACRO: 3887 SOC_IF_ERROR_RETURN 3888 (_soc_greyhound_process_port_macro_error(unit, 3889 group, block_port, table, msg, blk)); 3890 break; 3891 3892 default: 3893 break; 3894 } /* handle different parity error reporting style */ 3895 3896 /* Level 1 interrupt status clear */ 3897 if (parity_group_info[group].clear_reg != INVALIDr) { 3898 /* Clean interrupt status */ 3899 reg = parity_group_info[group].clear_reg; 3900 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, block_port, 3901 0, &group_clr)); 3902 soc_reg_field_set(unit, reg, &group_clr, 3903 info[table].clear_field, 1); 3904 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, block_port, 0, group_clr)); 3905 } 3906 } /* loop through each table in the group */ 3907 3908 3909 3910 reg = parity_group_info[group].enable_reg; 3911 if ((parity_group_info[group].blocktype == SOC_BLK_XLPORT) && 3912 (blk_num == 5)) { 3913 reg = PGW_GX_INTR_ENABLEr; 3914 } 3915 3916 if (reg_is_64) { 3917 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, reg, block_port, 0, &group_enable64)); 3918 temp64 = group_status64; 3919 COMPILER_64_NOT(temp64); 3920 COMPILER_64_AND(group_enable64, temp64); 3921 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, reg, 3922 block_port, 0, group_enable64)); 3923 COMPILER_64_OR(group_enable64, group_status64); 3924 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, reg, 3925 block_port, 0, group_enable64)); 3926 } else { 3927 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, block_port, 0, &group_enable)); 3928 group_enable &= ~group_status; 3929 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, block_port, 0, group_enable)); 3930 group_enable |= group_status; 3931 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, block_port, 0, group_enable)); 3932 } 3933 3934 } /* loop through each block for the group */ 3935 3936 } /* loop through each group */ 3937 3938 return SOC_E_NONE; 3939 } 3940 3941 void 3942 soc_greyhound_parity_error(void *unit_vp, void *d1, void *d2, 3943 void *d3, void *d4) 3944 { 3945 int unit = PTR_TO_INT(unit_vp); 3946 (void)_soc_greyhound_process_parity_error(unit); 3947 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 3948 if (d2 != NULL) { 3949 (void)soc_cmicm_intr3_enable(unit, PTR_TO_INT(d2)); 3950 } 3951 } 3952 3953 STATIC int 3954 _soc_greyhound_mem_nack_error_process(int unit, 3955 _greyhound_ser_nack_reg_mem_t nack_reg_mem, 3956 soc_block_t block, int reg_mem) 3957 { 3958 int group, table; 3959 _soc_gh_parity_info_t *info; 3960 soc_port_t block_port; 3961 soc_block_t blk; 3962 char *msg; 3963 _soc_gh_parity_group_info_t *parity_group_info; 3964 3965 if (nack_reg_mem.mem == INVALIDm) { 3966 return SOC_E_PARAM; 3967 } 3968 3969 parity_group_info = _soc_gh_parity_group_info[unit]; 3970 if (parity_group_info == NULL) { 3971 LOG_CLI((BSL_META_U(unit, 3972 "unit %d the NACK parity error can't be handled.\n"), unit)); 3973 return SOC_E_UNAVAIL; 3974 } 3975 3976 /* loop through each group */ 3977 for (group = 0; parity_group_info[group].cpi_bit; group++) { 3978 info = parity_group_info[group].info; 3979 3980 SOC_BLOCK_ITER(unit, blk, 3981 parity_group_info[group].blocktype) { 3982 if (block != SOC_BLOCK_INFO(unit, blk).schan) { 3983 continue; 3984 } 3985 if (_soc_greyhound_parity_block_port(unit, blk, &block_port) < 0) { 3986 continue; 3987 } 3988 /* loop through each table in the group */ 3989 for (table = 0; info[table].error_field != INVALIDf; table++) { 3990 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 3991 continue; 3992 } 3993 if (info[table].mem != nack_reg_mem.mem) { 3994 continue; 3995 } 3996 if (info[table].msg) { 3997 msg = info[table].msg; 3998 } else { /* mem must be valid to get her */ 3999 msg = SOC_MEM_NAME(unit, info[table].mem); 4000 } 4001 4002 /* handle different parity error reporting style */ 4003 switch (info[table].type) { 4004 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 4005 SOC_IF_ERROR_RETURN 4006 (_soc_greyhound_process_single_parity_error(unit, 4007 group, block_port, table, FALSE, msg, block)); 4008 break; 4009 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 4010 SOC_IF_ERROR_RETURN 4011 (_soc_greyhound_process_single_ecc_error(unit, 4012 group, block_port, table, FALSE, msg, blk)); 4013 break; 4014 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 4015 SOC_IF_ERROR_RETURN 4016 (_soc_greyhound_process_dual_parity_error(unit, 4017 group, block_port, table, FALSE, msg, blk)); 4018 break; 4019 default: 4020 break; 4021 } /* handle different parity error reporting style */ 4022 } /* loop through each table in the group */ 4023 } /* loop through each block of the group */ 4024 } /* loop through each group */ 4025 4026 return SOC_E_NONE; 4027 } 4028 4029 4030 void 4031 soc_greyhound_mem_nack(void *unit_vp, void *addr_vp, void *blk_vp, 4032 void *d3, void *d4) 4033 { 4034 soc_mem_t mem = INVALIDm; 4035 int reg_mem = PTR_TO_INT(d3); 4036 int rv, unit = PTR_TO_INT(unit_vp); 4037 uint32 address = PTR_TO_INT(addr_vp); 4038 uint32 block = PTR_TO_INT(blk_vp); 4039 uint32 offset = 0, min_addr = 0; 4040 soc_regaddrinfo_t ainfo; 4041 _greyhound_ser_nack_reg_mem_t nack_reg_mem; 4042 soc_field_t error_fld = INVALIDf; 4043 uint32 minfo; 4044 _soc_ser_correct_info_t spci; 4045 char *msg; 4046 4047 if (reg_mem == _SOC_GREYHOUND_SER_REG) { 4048 nack_reg_mem.reg = INVALIDr; 4049 if (address) { 4050 soc_regaddrinfo_get(unit, &ainfo, address); 4051 nack_reg_mem.reg = ainfo.reg; 4052 } 4053 if (nack_reg_mem.reg == INVALIDr) { 4054 /* Invalid register */ 4055 return; 4056 } 4057 } else { 4058 offset = address; 4059 4060 mem = soc_addr_to_mem_extended(unit, block, 0, address); 4061 if (mem == INVALIDm) { 4062 LOG_ERROR(BSL_LS_SOC_COMMON, 4063 (BSL_META_U(unit, 4064 "unit %d mem decode failed, " 4065 "SCHAN NACK analysis failure\n"), unit)); 4066 return; 4067 } 4068 4069 nack_reg_mem.mem = mem; 4070 4071 min_addr = SOC_MEM_INFO(unit, mem).base; 4072 min_addr += SOC_MEM_INFO(unit, mem).index_min; 4073 } 4074 4075 if (reg_mem == _SOC_GREYHOUND_SER_MEM) { 4076 if ((mem == EGR_L3_NEXT_HOPm) || (mem == EGR_L3_INTFm) || 4077 (mem == EGR_VLANm) || (mem == EGR_VLAN_STGm) || 4078 (mem == EFP_COUNTER_TABLEm) || (mem == EGR_ETAG_PCP_MAPPINGm) || 4079 (mem == EGR_PERQ_XMT_COUNTERSm) || (mem == EGR_GPP_ATTRIBUTESm) || 4080 (mem == EGR_MOD_MAP_TABLEm) || 4081 (mem == EGR_PER_Q_ECN_MARKEDm) || 4082 (mem == L2_USER_ENTRY_DATA_ONLYm)) { 4083 /* 4084 * The inetrupt of parity error for these memories will not be triggered. 4085 * And the parity error status register will not be updated. 4086 * Use the offset value of S-channel msg to instead of. 4087 */ 4088 switch (mem) { 4089 case EGR_L3_NEXT_HOPm: 4090 error_fld = EGR_NHOP_PAR_ERRf; 4091 break; 4092 case EGR_L3_INTFm: 4093 error_fld = EGR_L3_INTF_PAR_ERRf; 4094 break; 4095 case EGR_VLANm: 4096 error_fld = EGR_VLAN_PAR_ERRf; 4097 break; 4098 case EGR_VLAN_STGm: 4099 error_fld = EGR_VLAN_STG_PAR_ERRf; 4100 break; 4101 case EFP_COUNTER_TABLEm: 4102 error_fld = EGR_FP_COUNTERf; 4103 break; 4104 case EGR_ETAG_PCP_MAPPINGm: 4105 error_fld = EGR_ETAG_PCP_DE_MAPPING_PAR_ERRf; 4106 break; 4107 case EGR_GPP_ATTRIBUTESm: 4108 error_fld = EGR_GPP_ATTRIBUTES_PAR_ERRf; 4109 break; 4110 case EGR_MOD_MAP_TABLEm: 4111 error_fld = EGR_MOD_MAP_TABLE_PAR_ERRf; 4112 break; 4113 case EGR_PER_Q_ECN_MARKEDm: 4114 error_fld = EGR_PER_Q_ECN_MARKED_PAR_ERRf; 4115 break; 4116 case L2_USER_ENTRY_DATA_ONLYm: 4117 mem = L2_USER_ENTRYm; 4118 error_fld = L2_USER_ENTRY_DATA_ONLY_PAR_ERRf; 4119 break; 4120 default: 4121 /* EGR_PERQ_XMT_COUNTERSm */ 4122 error_fld = EGR_PERQ_COUNTERf; 4123 break; 4124 } 4125 _soc_gh_mem_parity_info(unit, block, 0, 4126 error_fld, &minfo); 4127 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4128 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 4129 (offset - min_addr), minfo); 4130 msg = SOC_MEM_NAME(unit, mem); 4131 LOG_ERROR(BSL_LS_SOC_COMMON, 4132 (BSL_META_U(unit, 4133 "unit %d %s entry %d parity error\n"), 4134 unit, msg, (offset - min_addr))); 4135 sal_memset(&spci, 0, sizeof(spci)); 4136 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 4137 spci.reg = INVALIDr; 4138 spci.mem = mem; 4139 spci.blk_type = -1; 4140 spci.index = (offset - min_addr); 4141 (void)soc_ser_correction(unit, &spci); 4142 } else { 4143 4144 if ((rv = _soc_greyhound_mem_nack_error_process(unit, nack_reg_mem, 4145 (soc_block_t)block, reg_mem)) < 0) { 4146 LOG_ERROR(BSL_LS_SOC_COMMON, 4147 (BSL_META_U(unit, 4148 "unit %d %s entry %d SCHAN NACK analysis failure\n"), 4149 unit, SOC_MEM_NAME(unit, mem), 4150 offset - min_addr)); 4151 } 4152 } 4153 4154 LOG_CLI((BSL_META_U(unit, 4155 "unit %d %s entry %d SCHAN NACK analysis\n"), 4156 unit, SOC_MEM_NAME(unit, mem), 4157 offset - min_addr)); 4158 } else { 4159 /* Regitser */ 4160 LOG_CLI((BSL_META_U(unit, 4161 "unit %d %s REG SCHAN NACK analysis\n"), 4162 unit, SOC_REG_NAME(unit, nack_reg_mem.reg))); 4163 if ((ainfo.reg >= TDBGC0r) && (ainfo.reg <= TDBGC11r)) { 4164 error_fld = EGR_STATS_COUNTER_TABLE_PAR_ERRf; 4165 } else { 4166 LOG_ERROR(BSL_LS_SOC_COMMON, 4167 (BSL_META_U(unit, 4168 "unit %d %s REG unexpected NACK failure!\n"), 4169 unit, SOC_REG_NAME(unit, nack_reg_mem.reg))); 4170 return; 4171 } 4172 _soc_gh_mem_parity_info(unit, block, 0, 4173 error_fld, &minfo); 4174 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4175 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 4176 ainfo.idx, minfo); 4177 msg = SOC_REG_NAME(unit, nack_reg_mem.reg); 4178 LOG_ERROR(BSL_LS_SOC_COMMON, 4179 (BSL_META_U(unit, 4180 "unit %d port %d %s index %d parity error\n"), 4181 unit, ainfo.port, msg, ainfo.idx)); 4182 sal_memset(&spci, 0, sizeof(spci)); 4183 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 4184 spci.reg = ainfo.reg; 4185 spci.port = ainfo.port; 4186 spci.mem = INVALIDm; 4187 spci.blk_type = SOC_BLOCK_ANY; 4188 spci.index = ainfo.idx; 4189 (void)soc_ser_correction(unit, &spci); 4190 } 4191 } 4192 4193 static int 4194 soc_greyhound_pipe_mem_clear(int unit) 4195 { 4196 uint32 rval; 4197 int pipe_init_usec, index; 4198 soc_timeout_t to; 4199 static const struct { 4200 soc_mem_t mem; 4201 uint32 skip_flags; /* always skip on QUICKTURN or XGSSIM */ 4202 } cam_list[] = { 4203 { CPU_COS_MAPm, BOOT_F_PLISIM }, 4204 { EFP_TCAMm, BOOT_F_PLISIM }, 4205 { FP_GLOBAL_MASK_TCAMm, BOOT_F_PLISIM }, 4206 { FP_TCAMm, BOOT_F_PLISIM }, 4207 { L2_USER_ENTRYm, BOOT_F_PLISIM }, 4208 { L2_USER_ENTRY_ONLYm, BOOT_F_PLISIM }, 4209 { L3_DEFIPm, BOOT_F_PLISIM }, 4210 { L3_DEFIP_ONLYm, BOOT_F_PLISIM }, 4211 { VFP_TCAMm, BOOT_F_PLISIM }, 4212 { VLAN_SUBNETm, 0 },/* VLAN API needs all 0 mask */ 4213 { VLAN_SUBNET_ONLYm, 0 } 4214 }; 4215 4216 /* 4217 * Reset the IPIPE and EPIPE block 4218 */ 4219 rval = 0; 4220 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 4221 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 4222 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 4223 /* Set count to # entries in largest IPIPE table, L2_ENTRYm */ 4224 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x4000); 4225 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 4226 4227 rval = 0; 4228 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 4229 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 4230 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 4231 /* Set count to # entries in largest EPIPE table, EGR_VLANm */ 4232 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x1000); 4233 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 4234 4235 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 4236 if (SAL_BOOT_SIMULATION) { 4237 pipe_init_usec = 10000000; 4238 } else { 4239 pipe_init_usec = 50000; 4240 } 4241 soc_timeout_init(&to, pipe_init_usec, 0); 4242 4243 /* Wait for IPIPE memory initialization done. */ 4244 do { 4245 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 4246 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 4247 break; 4248 } 4249 if (soc_timeout_check(&to)) { 4250 LOG_WARN(BSL_LS_SOC_COMMON, 4251 (BSL_META_U(unit, 4252 "unit %d : ING_HW_RESET timeout\n"), unit)); 4253 break; 4254 } 4255 } while (TRUE); 4256 4257 /* Wait for EPIPE memory initialization done. */ 4258 do { 4259 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 4260 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 4261 break; 4262 } 4263 if (soc_timeout_check(&to)) { 4264 LOG_WARN(BSL_LS_SOC_COMMON, 4265 (BSL_META_U(unit, 4266 "unit %d : EGR_HW_RESET timeout\n"), unit)); 4267 break; 4268 } 4269 } while (TRUE); 4270 4271 rval = 0; 4272 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 4273 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 4274 4275 if (!SAL_BOOT_QUICKTURN && !SAL_BOOT_XGSSIM) { 4276 /* TCAM tables are not handled by hardware reset control */ 4277 for (index = 0; index < sizeof(cam_list) / sizeof(cam_list[0]); 4278 index++) { 4279 if (sal_boot_flags_get() & cam_list[index].skip_flags) { 4280 continue; 4281 } 4282 if (((cam_list[index].mem == EFP_TCAMm) || 4283 (cam_list[index].mem == VFP_TCAMm)) && 4284 (!soc_feature(unit, soc_feature_field_multi_stage))) { 4285 continue; 4286 } 4287 SOC_IF_ERROR_RETURN 4288 (soc_mem_clear(unit, cam_list[index].mem, COPYNO_ALL, TRUE)); 4289 } 4290 4291 /* MMU_IPMC_VLAN_TBL */ 4292 SOC_IF_ERROR_RETURN 4293 (soc_mem_clear(unit, MMU_IPMC_VLAN_TBLm, COPYNO_ALL, TRUE)); 4294 4295 /* MMU_IPMC_GROUP_TBLn : n is 2 ~ 29 in Greyhound */ 4296 for (index = 0; index < _SOC_GH_MMU_IPMC_GROUP_MAX; index++) { 4297 if (ipmc_mems[index] != INVALIDm) { 4298 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, 4299 ipmc_mems[index], COPYNO_ALL, TRUE)); 4300 } 4301 } 4302 4303 } 4304 return SOC_E_NONE; 4305 } 4306 4307 4308 #define GH_NUM_COS 8 4309 int soc_gh_xq_mem(int unit, soc_port_t port, soc_mem_t *xq) 4310 { 4311 soc_mem_t xq_mems[] = { MMU_XQ0m, 4312 MMU_XQ1m, 4313 MMU_XQ2m, 4314 MMU_XQ3m, 4315 MMU_XQ4m, 4316 MMU_XQ5m, 4317 MMU_XQ6m, 4318 MMU_XQ7m, 4319 MMU_XQ8m, 4320 MMU_XQ9m, 4321 MMU_XQ10m, 4322 MMU_XQ11m, 4323 MMU_XQ12m, 4324 MMU_XQ13m, 4325 MMU_XQ14m, 4326 MMU_XQ15m, 4327 MMU_XQ16m, 4328 MMU_XQ17m, 4329 MMU_XQ18m, 4330 MMU_XQ19m, 4331 MMU_XQ20m, 4332 MMU_XQ21m, 4333 MMU_XQ22m, 4334 MMU_XQ23m, 4335 MMU_XQ24m, 4336 MMU_XQ25m, 4337 MMU_XQ26m, 4338 MMU_XQ27m, 4339 MMU_XQ28m, 4340 MMU_XQ29m 4341 }; 4342 int max_port; 4343 max_port = sizeof(xq_mems) / sizeof(xq_mems[0]); 4344 if (port >= max_port) { 4345 return(SOC_E_PORT); 4346 } 4347 *xq = xq_mems[port]; 4348 return(SOC_E_NONE); 4349 } 4350 4351 4352 int 4353 soc_greyhound_init_port_mapping(int unit) 4354 { 4355 soc_info_t *si; 4356 soc_mem_t mem; 4357 uint32 rval; 4358 ing_physical_to_logical_port_number_mapping_table_entry_t entry; 4359 int port, phy_port; 4360 int num_port, num_phy_port; 4361 int speed; 4362 4363 si = &SOC_INFO(unit); 4364 4365 /* Ingress physical to logical port mapping */ 4366 mem = ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLEm; 4367 num_phy_port = soc_mem_index_count(unit, mem); 4368 sal_memset(&entry, 0, sizeof(entry)); 4369 for (phy_port = 0; phy_port < num_phy_port; phy_port++) { 4370 port = si->port_p2l_mapping[phy_port]; 4371 soc_mem_field32_set(unit, mem, &entry, LOGICAL_PORT_NUMBERf, 4372 port == -1 ? 0x1f : port); 4373 SOC_IF_ERROR_RETURN 4374 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, phy_port, &entry)); 4375 } 4376 num_port = soc_mem_index_count(unit, PORT_TABm); 4377 4378 /* Egress logical to physical port mapping */ 4379 for (port = 0; port < num_port; port++) { 4380 phy_port = si->port_l2p_mapping[port]; 4381 rval = 0; 4382 soc_reg_field_set(unit, EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr, 4383 &rval, PHYSICAL_PORT_NUMBERf, 4384 phy_port == -1 ? 0x3f : phy_port); 4385 SOC_IF_ERROR_RETURN 4386 (WRITE_EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr(unit, port, 4387 rval)); 4388 } 4389 /* MMU logical to physical port mapping */ 4390 /*(Here, Same as Egress logical to physical port mapping) */ 4391 for (port = 0; port < num_port; port++) { 4392 phy_port = si->port_m2p_mapping[port]; 4393 if (phy_port != -1) { 4394 rval = 0; 4395 soc_reg_field_set(unit, LOG_TO_PHY_PORT_MAPPINGr, &rval, 4396 PHY_PORTf, phy_port); 4397 SOC_IF_ERROR_RETURN 4398 (WRITE_LOG_TO_PHY_PORT_MAPPINGr(unit, port, rval)); 4399 } 4400 } 4401 4402 /* Initialize the si->port_init_speed */ 4403 PBMP_ALL_ITER(unit, port) { 4404 /* 4405 * Let the port_init_speed as the max supported speed of xe 4406 * while the port_speed_max would be the max supported speed of hg 4407 */ 4408 switch(si->port_speed_max[port]) { 4409 case 11000: 4410 speed = 10000; 4411 break; 4412 default: 4413 speed = si->port_speed_max[port]; 4414 break; 4415 } 4416 si->port_init_speed[port] = speed; 4417 } 4418 return SOC_E_NONE; 4419 } 4420 4421 /* Provide the max speed mapping from xe to hg */ 4422 int 4423 soc_greyhound_port_hg_speed_get(int unit, soc_port_t port, int *speed) 4424 { 4425 soc_info_t *si; 4426 si = &SOC_INFO(unit); 4427 4428 switch (si->port_init_speed[port]) { 4429 case 10000: 4430 *speed = 11000; 4431 break; 4432 default: 4433 *speed = si->port_init_speed[port]; 4434 break; 4435 } 4436 4437 if (*speed > si->port_speed_max[port]) { 4438 *speed = si->port_speed_max[port]; 4439 } 4440 return SOC_E_NONE; 4441 } 4442 4443 /* 4444 * GH port mapping 4445 * cpu port number is fixed: physical 0, logical 0, mmu 0 4446 */ 4447 int 4448 soc_greyhound_port_config_init(int unit, uint16 dev_id) 4449 { 4450 4451 soc_info_t *si; 4452 int rv = SOC_E_NONE; 4453 int phy_port, dual_port_idx, blk,port_idx; 4454 const int *p2l_mapping = 0,*speed_max = 0; 4455 const int *valid_port_idx = 0; 4456 char *propval,*option; 4457 int match = -1, i, j, match_option; 4458 int p2l_mapping_override[SOC_MAX_PHY_PORTS]; 4459 int port_speed_max_override[SOC_MAX_PHY_PORTS]; 4460 _gh_sku_info_t *matched_port_config; 4461 4462 4463 option = soc_property_get_str(unit, spn_BCM53400_INIT_PORT_CONFIG); 4464 if(option == NULL) { 4465 _gh_port_config_id = 1; 4466 } else { 4467 _gh_port_config_id = sal_ctoi(option, NULL); 4468 } 4469 match_option = -1; 4470 for (i=0; _gh_sku_port_config[i].dev_id; i++){ 4471 if(dev_id == _gh_sku_port_config[i].dev_id) { 4472 match = i; 4473 if (_gh_sku_port_config[i].config_op != -1 ){ 4474 match_option = 0; 4475 if (_gh_sku_port_config[i].config_op == _gh_port_config_id ){ 4476 match = i; 4477 match_option = _gh_port_config_id; 4478 break; 4479 } 4480 } 4481 } 4482 } 4483 for (i = 0; i < _GH_MAX_TSC_COUNT; i++) { 4484 _gh_tsc[i].lane_mode = -1; 4485 _gh_tsc[i].valid = 0; 4486 _gh_tsc[i].phy_port_base = tsc_phy_port[i]; 4487 propval = soc_property_suffix_num_str_get(unit, i, spn_BCM53400_INIT_PORT_CONFIG, "tsc"); 4488 if (propval) { 4489 if (sal_strcmp(propval, "SINGLE") == 0) { 4490 _gh_tsc[i].lane_mode = _GH_TSC_LANE_MODE_SINGLE; 4491 _gh_tsc[i].valid = 1; 4492 } else if (sal_strcmp(propval, "XAUI") == 0) { 4493 _gh_tsc[i].lane_mode = _GH_TSC_LANE_MODE_XAUI; 4494 _gh_tsc[i].valid = 1; 4495 } else if (sal_strcmp(propval, "RXAUI") == 0) { 4496 _gh_tsc[i].lane_mode = _GH_TSC_LANE_MODE_RXAUI; 4497 _gh_tsc[i].valid = 1; 4498 } else { 4499 if (match == -1) { 4500 /* take 53401 option 1 as default config */ 4501 _gh_tsc[i].lane_mode = _gh_sku_port_config[0].default_lane_mode[i]; 4502 4503 } else { 4504 _gh_tsc[i].lane_mode = _gh_sku_port_config[match].default_lane_mode[i]; 4505 } 4506 } 4507 } else { 4508 if (match == -1) { 4509 _gh_tsc[i].lane_mode = _gh_sku_port_config[0].default_lane_mode[i]; 4510 } else { 4511 _gh_tsc[i].lane_mode = _gh_sku_port_config[match].default_lane_mode[i]; 4512 } 4513 } 4514 } 4515 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 4516 p2l_mapping_override[phy_port] = 0; 4517 port_speed_max_override[phy_port] = 0; 4518 } 4519 dual_port_idx = 0; 4520 if (match == -1) { 4521 /* take 53401 option 1 as default config */ 4522 p2l_mapping = p2l_mapping_cascade; 4523 speed_max = port_speed_max_non_cascade; 4524 dual_port_idx = 1; 4525 valid_port_idx = port_blk_gport; 4526 LOG_WARN(BSL_LS_SOC_COMMON, 4527 (BSL_META_U(unit, 4528 "no device_id matched\n"))); 4529 } else { 4530 matched_devid_idx = match; 4531 matched_port_config = &_gh_sku_port_config[match]; 4532 if (((option != NULL) && (matched_port_config->config_op == -1)) || 4533 (match_option == 0)){ 4534 LOG_WARN(BSL_LS_SOC_COMMON, 4535 (BSL_META_U(unit, 4536 "Warning: bcm53400_init_port_config=%d config " 4537 "is not supported in %s ! \n"),_gh_port_config_id, 4538 soc_dev_name(unit))); 4539 } 4540 4541 p2l_mapping = matched_port_config->p2l_mapping; 4542 speed_max = matched_port_config->speed_max; 4543 4544 if (matched_port_config->dual_port_idx != 0) { 4545 dual_port_idx = 1; 4546 valid_port_idx = matched_port_config->port_blk_type; 4547 } 4548 for (i = 0; i <_GH_MAX_TSC_COUNT; i++) { 4549 if(_gh_tsc[i].valid) { 4550 if((1 << i) & matched_port_config->flex_tsc_bmp){ 4551 /* support flex tsc settings */ 4552 /* validate the assigned flexible lane mode */ 4553 if (!_GH_FLEX_LANE_MODE_IS_SUPPORT( 4554 matched_port_config->flex_lane_modes_bmp[i], 4555 _gh_tsc[i].lane_mode)) { 4556 LOG_WARN(BSL_LS_SOC_COMMON,(BSL_META_U(unit, 4557 "Warning: bcm53400_init_port_config_tsc%d " 4558 "config is not supported in %s ! \n"), 4559 i, soc_dev_name(unit))); 4560 _gh_tsc[i].lane_mode = 4561 matched_port_config->default_lane_mode[i]; 4562 } 4563 if(_gh_tsc[i].lane_mode == _GH_TSC_LANE_MODE_XAUI) { 4564 for (j = 0; j < 4; j++) { 4565 p2l_mapping_override[tsc_phy_port[i]+j] = 4566 lane_xaui_override[j]; 4567 port_speed_max_override[tsc_phy_port[i]+j] = 4568 lane_xaui_speed_override[j]; 4569 } 4570 } else if(_gh_tsc[i].lane_mode == _GH_TSC_LANE_MODE_RXAUI) { 4571 for (j = 0; j < 4; j++) { 4572 p2l_mapping_override[tsc_phy_port[i]+j] = 4573 lane_rxaui_override[j]; 4574 port_speed_max_override[tsc_phy_port[i]+j] = 4575 lane_rxaui_speed_override[j]; 4576 } 4577 } else { 4578 /* expected for LANEMODE_SIGNLE */ 4579 for (j = 0; j < 4; j++) { 4580 p2l_mapping_override[tsc_phy_port[i]+j] = 4581 lane_single_override[j]; 4582 } 4583 } 4584 } else { 4585 LOG_WARN(BSL_LS_SOC_COMMON, 4586 (BSL_META_U(unit, 4587 "Warning: bcm53400_init_port_config_tsc%d config " 4588 "is not supported in %s ! \n"),i,soc_dev_name(unit))); 4589 _gh_tsc[i].lane_mode = 4590 matched_port_config->default_lane_mode[i]; 4591 } 4592 } 4593 if((1 << i) & matched_port_config->disabled_tsc_bmp){ 4594 /* Disable TSC here */ 4595 for (j = 0; j < 4; j++) { 4596 p2l_mapping_override[tsc_phy_port[i]+j] = 4597 lane_disable_override[j]; 4598 port_speed_max_override[tsc_phy_port[i]+j] = 4599 lane_disable_override[j]; 4600 } 4601 } 4602 } 4603 } 4604 4605 si = &SOC_INFO(unit); 4606 4607 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 4608 if (p2l_mapping_override[phy_port] == -1){ 4609 si->port_p2l_mapping[phy_port] = p2l_mapping_override[phy_port]; 4610 /* Same as Egr P2L */ 4611 si->port_p2m_mapping[phy_port] = p2l_mapping_override[phy_port]; 4612 /* For COSQ programming */ 4613 si->max_port_p2m_mapping[phy_port] = p2l_mapping_override[phy_port]; 4614 } else { 4615 /* speed_max reflects the valid port */ 4616 /* For the same TDM, the phy_port should be existed in p2l_mapping table */ 4617 if((speed_max[phy_port] == -1) && (phy_port != 0)){ 4618 si->port_p2l_mapping[phy_port] = -1; 4619 si->port_p2m_mapping[phy_port] = -1; 4620 si->max_port_p2m_mapping[phy_port] = -1; 4621 } else { 4622 si->port_p2l_mapping[phy_port] = p2l_mapping[phy_port]; 4623 si->port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 4624 si->max_port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 4625 } 4626 } 4627 if (port_speed_max_override[phy_port] != 0){ 4628 if (port_speed_max_override[phy_port] != -1) { 4629 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 4630 port_speed_max_override[phy_port] * 100; 4631 } 4632 } else { 4633 if (speed_max[phy_port] != -1) { 4634 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 4635 speed_max[phy_port] * 100; 4636 } 4637 } 4638 if (dual_port_idx && (valid_port_idx[phy_port] != -1)) { 4639 for (port_idx = 0; port_idx < SOC_DRIVER(unit)->port_num_blktype; 4640 port_idx++) { 4641 if (valid_port_idx[phy_port] != port_idx){ 4642 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, port_idx); 4643 SOC_BLOCK_INFO(unit, blk).number |= 0xf00; 4644 } 4645 } 4646 } 4647 } 4648 return rv; 4649 } 4650 4651 4652 int 4653 _soc_greyhound_tdm_init(int unit, uint16 dev_id) 4654 { 4655 uint32 *arr = NULL; 4656 int tdm_size; 4657 uint32 rval; 4658 iarb_tdm_table_entry_t iarb_tdm; 4659 mmu_arb_tdm_table_entry_t mmu_arb_tdm; 4660 int i, port, phy_port; 4661 _gh_sku_info_t *matched_sku_info; 4662 soc_info_t *si; 4663 int tsc5_phy_port = 2; 4664 4665 si = &SOC_INFO(unit); 4666 4667 4668 4669 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 4670 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 4671 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 83); 4672 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 4673 4674 if (matched_devid_idx == -1) { 4675 LOG_WARN(BSL_LS_SOC_COMMON, 4676 (BSL_META_U(unit, 4677 "Warning: soc_greyhound_port_config_init should " 4678 "be invoked first! Choose bcm534x1 port config.\n"))); 4679 matched_devid_idx = 0; 4680 } 4681 matched_sku_info = &_gh_sku_port_config[matched_devid_idx]; 4682 4683 arr = matched_sku_info->tdm_table; 4684 tdm_size = matched_sku_info->tdm_table_size; 4685 if((matched_sku_info->dev_id == BCM53406_DEVICE_ID && matched_sku_info->config_op == 1)|| 4686 (matched_sku_info->dev_id == BCM53369_DEVICE_ID && matched_sku_info->config_op == 1)){ 4687 if( si->port_speed_max[si->port_p2l_mapping[tsc5_phy_port]] > 5000){ 4688 /* Re check after support 5G */ 4689 arr = gh_tdm_mixed_embeded_2xrxaui; 4690 tdm_size = _GH_ARRAY_SIZE(gh_tdm_mixed_embeded_2xrxaui); 4691 } 4692 } 4693 4694 if (arr == NULL) { 4695 return SOC_E_CONFIG; 4696 } 4697 4698 for (i = 0; i < tdm_size; i++) { 4699 phy_port = arr[i]; 4700 port = (phy_port != 63) ? matched_sku_info->p2l_mapping[phy_port]:63; 4701 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 4702 sal_memset(&mmu_arb_tdm, 0, sizeof(mmu_arb_tdm_table_entry_t)); 4703 4704 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 4705 phy_port); 4706 4707 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, PORT_NUMf, 4708 port); 4709 if (i == tdm_size - 1) { 4710 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, WRAP_ENf, 1); 4711 } 4712 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 4713 &iarb_tdm)); 4714 SOC_IF_ERROR_RETURN(WRITE_MMU_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 4715 &mmu_arb_tdm)); 4716 } 4717 rval = 0; 4718 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 4719 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 4720 tdm_size -1); 4721 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 4722 return SOC_E_NONE; 4723 } 4724 4725 STATIC int 4726 _soc_greyhound_mmu_init(int unit) 4727 { 4728 int cos; 4729 soc_port_t port; 4730 uint32 val, oval, cfap_max_idx; 4731 int age[GH_NUM_COS], max_age, min_age; 4732 int age_enable, disabled_age; 4733 int skid_mark; 4734 uint32 dyn_xq_per_port; 4735 uint32 limit; /* E2EFC configuration */ 4736 uint32 xq_limit, cell_limit; 4737 uint32 cell_resume_delta; 4738 uint32 cos_min_xqs, cos_min_cells; 4739 uint16 dev_id; 4740 uint8 rev_id; 4741 int mmu_total_cells; 4742 int mmu_total_dyn_cells; 4743 int mmu_total_static_cells; 4744 int total_ports; 4745 uint32 max_cell_limit_pri0; 4746 uint32 max_cell_limit_pri1_7; 4747 uint32 dyn_cell_limit; 4748 uint32 xoff_cell_limit; 4749 uint32 reset_cell_limit; 4750 uint32 xoff_pkt_limit; 4751 uint32 reset_pkt_limit; 4752 uint32 dyn_cell_reset_delta; 4753 _gh_sku_info_t *matched_sku_info; 4754 int config_op = 1; 4755 4756 soc_cm_get_id(unit, &dev_id, &rev_id); 4757 4758 SOC_IF_ERROR_RETURN(_soc_greyhound_tdm_init(unit, dev_id)); 4759 4760 matched_sku_info = &_gh_sku_port_config[matched_devid_idx]; 4761 config_op = matched_sku_info->config_op; 4762 4763 cfap_max_idx = soc_mem_index_max(unit, MMU_CFAPm); 4764 SOC_IF_ERROR_RETURN(READ_CFAPCONFIGr(unit, &val)); 4765 oval = val; 4766 soc_reg_field_set(unit, CFAPCONFIGr, &val, CFAPPOOLSIZEf, cfap_max_idx); 4767 if (oval != val) { 4768 SOC_IF_ERROR_RETURN(WRITE_CFAPCONFIGr(unit, val)); 4769 } 4770 4771 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 4772 /* set dyn_xq_en on */ 4773 soc_reg_field_set(unit, MISCCONFIGr, &val, DYN_XQ_ENf, 1); 4774 /* set HOL_CELL_SOP_DROP_EN on */ 4775 soc_reg_field_set(unit, MISCCONFIGr, &val, HOL_CELL_SOP_DROP_ENf, 1); 4776 /* set skidmarker to 3 */ 4777 soc_reg_field_set(unit, MISCCONFIGr, &val, SKIDMARKERf, 3); 4778 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 4779 4780 /* Every inactive COSQ consumes skid mark + 4 XQs; remove them from pool */ 4781 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 4782 skid_mark = soc_reg_field_get(unit, MISCCONFIGr, val, SKIDMARKERf) + 4; 4783 4784 /* Enable IP to CMICM credit transfer */ 4785 val = 0; 4786 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, TRANSFER_ENABLEf, 1); 4787 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, NUM_OF_CREDITSf, 32); 4788 SOC_IF_ERROR_RETURN(WRITE_IP_TO_CMICM_CREDIT_TRANSFERr(unit, val)); 4789 4790 if ((dev_id & 0x0060) == 0x0020) { 4791 /* Bloodhound: BCM5342x */ 4792 mmu_total_cells = GH_MMU_BUFFER_SIZE_1MB / GH_MMU_CELL_SIZE; 4793 } else { 4794 mmu_total_cells = GH_MMU_BUFFER_SIZE_2MB / GH_MMU_CELL_SIZE; 4795 /* For SKU with 1MB buffer pool, use the following line instead */ 4796 /* mmu_total_cells = GH_MMU_BUFFER_SIZE_1MB / GH_MMU_CELL_SIZE; */ 4797 } 4798 4799 if ((dev_id == BCM53403_DEVICE_ID) || (dev_id == BCM53413_DEVICE_ID) || \ 4800 (dev_id == BCM53404_DEVICE_ID) || (dev_id == BCM53414_DEVICE_ID) || \ 4801 (dev_id == BCM53406_DEVICE_ID) || (dev_id == BCM53416_DEVICE_ID) || \ 4802 (dev_id == BCM53408_DEVICE_ID) || (dev_id == BCM53418_DEVICE_ID) || \ 4803 (dev_id == BCM53454_DEVICE_ID) || (dev_id == BCM53455_DEVICE_ID) || \ 4804 (dev_id == BCM53426_DEVICE_ID) || (dev_id == BCM56065_DEVICE_ID) || \ 4805 (dev_id == BCM56066_DEVICE_ID) || 4806 ((dev_id == BCM53369_DEVICE_ID) && (config_op != 5))) { 4807 total_ports = 25; 4808 } else if ((dev_id == BCM56060_DEVICE_ID) || \ 4809 (dev_id == BCM53405_DEVICE_ID) || (dev_id == BCM53415_DEVICE_ID) || \ 4810 (dev_id == BCM53402_DEVICE_ID) || (dev_id == BCM53412_DEVICE_ID) || \ 4811 (dev_id == BCM53422_DEVICE_ID) || (dev_id == BCM53365_DEVICE_ID) || 4812 ((dev_id == BCM53369_DEVICE_ID) && (config_op == 5))) { 4813 total_ports = 17; 4814 } else { 4815 /* BCM56062,BCM56063,BCM56064,BCM53401,BCM53411,BCM53456,BCM53457,BCM53424 */ 4816 total_ports = 29; 4817 } 4818 mmu_total_static_cells = total_ports * GH_MMU_IN_PORT_STATIC_CELLS; 4819 mmu_total_dyn_cells = mmu_total_cells - mmu_total_static_cells; 4820 4821 /* total dynamic xqs - skid mark - 9(reserved xqs) */ 4822 dyn_xq_per_port = GH_MMU_IN_PORT_DYNAMIC_XQS - skid_mark - 9; 4823 /* limit includes the static minimum cells as well */ 4824 xq_limit = dyn_xq_per_port + GH_MMU_IN_COS_MIN_XQS; 4825 cos_min_xqs = GH_MMU_IN_COS_MIN_XQS; 4826 cos_min_cells = GH_MMU_IN_COS_MIN_CELLS; 4827 4828 cell_resume_delta = 12; 4829 dyn_cell_reset_delta = 24; 4830 if ((dev_id == BCM53403_DEVICE_ID) || (dev_id == BCM53413_DEVICE_ID) || \ 4831 (dev_id == BCM53404_DEVICE_ID) || (dev_id == BCM53414_DEVICE_ID) || \ 4832 (dev_id == BCM53406_DEVICE_ID) || (dev_id == BCM53416_DEVICE_ID) || \ 4833 (dev_id == BCM53408_DEVICE_ID) || (dev_id == BCM53418_DEVICE_ID) || \ 4834 (dev_id == BCM53454_DEVICE_ID) || (dev_id == BCM53455_DEVICE_ID) || \ 4835 (dev_id == BCM53426_DEVICE_ID) || (dev_id == BCM56065_DEVICE_ID) || \ 4836 (dev_id == BCM56066_DEVICE_ID) || 4837 ((dev_id == BCM53369_DEVICE_ID) && (config_op != 5))) { 4838 max_cell_limit_pri0 = 3456; 4839 max_cell_limit_pri1_7 = 48; 4840 xoff_pkt_limit = 80; 4841 reset_pkt_limit = 0; 4842 } else if ((dev_id == BCM56060_DEVICE_ID) || \ 4843 (dev_id == BCM53405_DEVICE_ID) || (dev_id == BCM53415_DEVICE_ID) || \ 4844 (dev_id == BCM53402_DEVICE_ID) || (dev_id == BCM53412_DEVICE_ID) || \ 4845 (dev_id == BCM53422_DEVICE_ID) || (dev_id == BCM53365_DEVICE_ID) || 4846 ((dev_id == BCM53369_DEVICE_ID) && (config_op == 5))) { 4847 max_cell_limit_pri0 = 4096; 4848 max_cell_limit_pri1_7 = 4096; 4849 xoff_pkt_limit = 80; 4850 reset_pkt_limit = 1; 4851 cell_resume_delta = 16; 4852 dyn_cell_reset_delta = 32; 4853 } else { 4854 /* BCM56062,BCM56063,BCM56064,BCM53401,BCM53411,BCM53456,BCM53457,BCM53424 */ 4855 max_cell_limit_pri0 = 7776; 4856 max_cell_limit_pri1_7 = 48; 4857 xoff_pkt_limit = 12; 4858 reset_pkt_limit = 0; 4859 } 4860 xoff_cell_limit = 80; 4861 reset_cell_limit = 40; 4862 4863 dyn_cell_limit = max_cell_limit_pri0 + \ 4864 ((GH_MMU_NUM_COS -1) * 4 * (1536 / GH_MMU_CELL_SIZE)); 4865 4866 PBMP_ALL_ITER(unit, port) { 4867 4868 for (cos = 0; cos < NUM_COS(unit); cos++) { 4869 /* 4870 * The HOLCOSPKTSETLIMITr register controls BOTH the XQ 4871 * size per cosq AND the HOL set limit for that cosq. 4872 */ 4873 SOC_IF_ERROR_RETURN 4874 (READ_HOLCOSPKTSETLIMITr(unit, port, cos, &val)); 4875 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &val, 4876 PKTSETLIMITf, 4877 xq_limit); 4878 SOC_IF_ERROR_RETURN 4879 (WRITE_HOLCOSPKTSETLIMITr(unit, port, cos, val)); 4880 4881 /* reset limit is set limit - 4 */ 4882 SOC_IF_ERROR_RETURN 4883 (READ_HOLCOSPKTRESETLIMITr(unit, port, cos, &val)); 4884 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &val, 4885 PKTRESETLIMITf, 4886 xq_limit-4); 4887 SOC_IF_ERROR_RETURN 4888 (WRITE_HOLCOSPKTRESETLIMITr(unit, port, cos, val)); 4889 4890 val = 0; 4891 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &val, 4892 HOLCOSMINXQCNTf, cos_min_xqs); 4893 SOC_IF_ERROR_RETURN 4894 (WRITE_HOLCOSMINXQCNTr(unit, port, cos, val)); 4895 4896 val = 0; 4897 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 4898 CELLSETLIMITf, cos_min_cells); 4899 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 4900 CELLRESETLIMITf, cos_min_cells); 4901 SOC_IF_ERROR_RETURN 4902 (WRITE_LWMCOSCELLSETLIMITr(unit, port, cos, val)); 4903 4904 cell_limit = 0; 4905 if(!cos) { 4906 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4907 CELLMAXLIMITf, max_cell_limit_pri0); 4908 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4909 CELLMAXRESUMELIMITf, max_cell_limit_pri0 - cell_resume_delta); 4910 } else { 4911 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4912 CELLMAXLIMITf, max_cell_limit_pri1_7); 4913 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4914 CELLMAXRESUMELIMITf, max_cell_limit_pri1_7 - cell_resume_delta); 4915 } 4916 SOC_IF_ERROR_RETURN 4917 (WRITE_HOLCOSCELLMAXLIMITr(unit, port, cos, cell_limit)); 4918 4919 val = 0; 4920 soc_reg_field_set(unit, PGCELLLIMITr, &val, 4921 CELLSETLIMITf, xoff_cell_limit); 4922 soc_reg_field_set(unit, PGCELLLIMITr, &val, 4923 CELLRESETLIMITf, reset_cell_limit); 4924 SOC_IF_ERROR_RETURN 4925 (WRITE_PGCELLLIMITr(unit, port, cos, val)); 4926 4927 val = 0; 4928 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &val, 4929 DISCARDSETLIMITf, mmu_total_cells-1); 4930 SOC_IF_ERROR_RETURN 4931 (WRITE_PGDISCARDSETLIMITr(unit, port, cos, val)); 4932 } 4933 4934 val = 0; 4935 soc_reg_field_set(unit, DYNXQCNTPORTr, &val, 4936 DYNXQCNTPORTf, dyn_xq_per_port); 4937 4938 SOC_IF_ERROR_RETURN(WRITE_DYNXQCNTPORTr(unit, port, val)); 4939 4940 val = 0; 4941 soc_reg_field_set(unit, DYNRESETLIMPORTr, &val, 4942 DYNRESETLIMPORTf, dyn_xq_per_port - 16); 4943 SOC_IF_ERROR_RETURN(WRITE_DYNRESETLIMPORTr(unit, port, val)); 4944 4945 val = 0; 4946 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 4947 DYNCELLSETLIMITf, dyn_cell_limit); 4948 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 4949 DYNCELLRESETLIMITf, dyn_cell_limit - 24); 4950 SOC_IF_ERROR_RETURN(WRITE_DYNCELLLIMITr(unit, port, val)); 4951 4952 cell_limit = 0; 4953 soc_reg_field_set(unit, TOTALDYNCELLSETLIMITr, 4954 &cell_limit, TOTALDYNCELLSETLIMITf, mmu_total_dyn_cells); 4955 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLSETLIMITr(unit, cell_limit)); 4956 cell_limit = 0; 4957 soc_reg_field_set(unit, TOTALDYNCELLRESETLIMITr, 4958 &cell_limit, TOTALDYNCELLRESETLIMITf, mmu_total_dyn_cells - 4959 dyn_cell_reset_delta); 4960 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLRESETLIMITr(unit, cell_limit)); 4961 4962 val = 0; 4963 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, 4964 PKTSETLIMITf, xoff_pkt_limit); 4965 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, RESETLIMITSELf, reset_pkt_limit); 4966 SOC_IF_ERROR_RETURN(WRITE_IBPPKTSETLIMITr(unit, port, val)); 4967 4968 4969 /* E2EFC configuration */ 4970 if (IS_HG_PORT(unit, port)){ 4971 SOC_IF_ERROR_RETURN(READ_IE2E_CONTROLr(unit, port, &val)); 4972 soc_reg_field_set(unit, IE2E_CONTROLr, &val, IBP_ENABLEf, 1); 4973 SOC_IF_ERROR_RETURN(WRITE_IE2E_CONTROLr(unit, port, val)); 4974 4975 limit = 0; 4976 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 4977 PKT_SET_LIMITf, 1456); 4978 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 4979 CELL_SET_LIMITf, 9504); 4980 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_SET_LIMITr(unit, port, limit)); 4981 4982 limit = 0; 4983 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 4984 PKT_RESET_LIMITf, 1456); 4985 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 4986 CELL_RESET_LIMITf, 9504); 4987 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_RESET_LIMITr(unit, port, limit)); 4988 4989 limit = 0; 4990 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 4991 PKT_DISC_LIMITf, 1456); 4992 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 4993 CELL_DISC_LIMITf, 9504); 4994 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_DISC_LIMITr(unit, port, limit)); 4995 } else { 4996 limit = 0; 4997 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 4998 PKT_SET_LIMITf, 12); 4999 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 5000 CELL_SET_LIMITf, 80); 5001 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_SET_LIMITr(unit, port, limit)); 5002 5003 limit = 0; 5004 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 5005 PKT_RESET_LIMITf, 9); 5006 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 5007 CELL_RESET_LIMITf, 60); 5008 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_RESET_LIMITr(unit, port, limit)); 5009 5010 limit = 0; 5011 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 5012 PKT_DISC_LIMITf, 1456); 5013 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 5014 CELL_DISC_LIMITf, 9504); 5015 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_DISC_LIMITr(unit, port, limit)); 5016 } 5017 } 5018 5019 /* E2EFC configuration */ 5020 SOC_IF_ERROR_RETURN(READ_E2EFC_IBP_ENr(unit, &val)); 5021 soc_reg_field_set(unit, E2EFC_IBP_ENr, &val, ENf, 1); 5022 SOC_IF_ERROR_RETURN(WRITE_E2EFC_IBP_ENr(unit, val)); 5023 5024 /* 5025 * Configure per-XQ packet aging for the various COSQs. 5026 * 5027 * The shortest age allowed by H/W is 250 microseconds. 5028 * The longest age allowed is 7.162 seconds (7162 msec). 5029 * The maximum ratio between the longest age and the shortest 5030 * (nonzero) age is 7:2. 5031 */ 5032 age_enable = disabled_age = max_age = 0; 5033 min_age = 7162; 5034 for (cos = 0; cos < NUM_COS(unit); cos++) { 5035 if ((age[cos] = 5036 soc_property_suffix_num_get(unit, cos, spn_MMU_XQ_AGING, 5037 "cos", 0)) > 0) { 5038 age_enable = 1; 5039 if (age[cos] > 7162) { 5040 age[cos] = 7162; 5041 } 5042 if (age[cos] < min_age) { 5043 min_age = age[cos]; 5044 } 5045 } else { 5046 disabled_age = 1; 5047 age[cos] = 0; 5048 } 5049 if (age[cos] > max_age) { 5050 max_age = age[cos]; 5051 } 5052 } 5053 if (!age_enable) { 5054 /* Disable packet aging on all COSQs */ 5055 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 0)); 5056 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, 0)); /* Aesthetic */ 5057 } else { 5058 uint32 regval = 0; 5059 uint32 timerval; 5060 5061 /* Enforce the 7:2 ratio between min and max values */ 5062 if ((((max_age * 2)+6) / 7) > min_age) { 5063 /* Keep requested max age; make min_age comply */ 5064 min_age = ((max_age * 2) + 6) / 7; 5065 } 5066 5067 /* 5068 * Give up granularity for range, if we need to 5069 * "disable" (max out) aging for any COSQ(s). 5070 */ 5071 if (disabled_age) { 5072 /* Max range */ 5073 max_age = min_age * 7 / 2; 5074 } 5075 5076 /* 5077 * Compute shortest duration of one PKTAGINGTIMERr cycle. 5078 * This duration is 1/7th of the longest packet age. 5079 * This duration is in units of 125 usec (msec * 8). 5080 */ 5081 timerval = ((8 * max_age) + 6) / 7; 5082 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, timerval)); 5083 5084 for (cos = 0; cos < NUM_COS(unit); cos++) { 5085 if (!age[cos]) { 5086 /* 5087 * Requested to be disabled, but cannot disable individual 5088 * COSQs once packet aging is enabled. Therefore, mark 5089 * this COSQ's aging duration as maxed out. 5090 */ 5091 age[cos] = -1; 5092 } else if (age[cos] < min_age) { 5093 age[cos] = min_age; 5094 } 5095 5096 /* Normalize each "age" into # of PKTAGINGTIMERr cycles. */ 5097 if (age[cos] > 0) { 5098 /* coverity[divide_by_zero : FALSE] */ 5099 age[cos] = ((8 * age[cos]) + timerval - 1) / timerval; 5100 } 5101 else { 5102 age[cos] = 7; 5103 } 5104 /* Format each "age" for its appropriate field */ 5105 regval |= ((7 - age[cos]) << (cos * 3)); 5106 } 5107 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, regval)); 5108 } 5109 5110 /* 5111 * Port enable 5112 */ 5113 val = 0; 5114 soc_reg_field_set(unit, MMUPORTENABLEr, &val, MMUPORTENABLEf, 5115 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 0)); 5116 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLEr(unit, val)); 5117 5118 return SOC_E_NONE; 5119 } 5120 5121 /* _soc_gh_sbus_tsc_block() 5122 * - to report the valid block of this port for wc_ucmem_data 5123 * (i.e. XLPORT_WC_UCMEM_DATAm )access process. 5124 * 5125 * - Parameters : 5126 * 1. phy_port(IN) : physical port. 5127 * 2. block(OUT) : the valid block 5128 * 5129 * Note : 5130 * - the port in TSC0Q(xlport5) reports one more associated block type. 5131 */ 5132 int 5133 _soc_gh_sbus_tsc_block(int unit, 5134 int phy_port, soc_mem_t wc_ucmem_data, int *block) 5135 { 5136 int i,port_num_blktype = 0, tmp_blk=0; 5137 5138 *block= -1; 5139 port_num_blktype = SOC_DRIVER(unit)->port_num_blktype; 5140 for (i = 0; i < port_num_blktype; i++){ 5141 tmp_blk = SOC_PORT_IDX_BLOCK(unit, phy_port, i); 5142 if ((SOC_MEM_INFO(unit, wc_ucmem_data).blocks & (1 << tmp_blk)) && 5143 SOC_INFO(unit).block_valid[tmp_blk]) { 5144 *block = tmp_blk; 5145 break; 5146 } 5147 } 5148 5149 if (*block == -1){ 5150 LOG_WARN(BSL_LS_SOC_COMMON, 5151 (BSL_META_U(unit, 5152 "_soc_gh_sbus_tsc_block(u=%d,pp=%d,mem=%d, blk=%d): " 5153 "no valid block for TSC SBUS interface!\n"), 5154 unit, phy_port, wc_ucmem_data, *block)); 5155 return SOC_E_INTERNAL; 5156 } 5157 5158 return SOC_E_NONE; 5159 } 5160 5161 #if defined(SER_TR_TEST_SUPPORT) 5162 soc_ser_test_functions_t ser_gh_test_fun; 5163 #endif 5164 5165 extern int (*_phy_tsce_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *, int); 5166 5167 STATIC int 5168 _soc_greyhound_tsce_firmware_set(int unit, int port, uint8 *array, int datalen) 5169 { 5170 /* TSC firmware set is handled by PortMod internally */ 5171 if (SOC_USE_PORTCTRL(unit)) { 5172 return SOC_E_INTERNAL; 5173 } 5174 5175 return soc_warpcore_firmware_set(unit, port, array, datalen, 0, 5176 XLPORT_WC_UCMEM_DATAm, 5177 XLPORT_WC_UCMEM_CTRLr); 5178 } 5179 5180 /* PHY_REG address decode : 5181 * - TSC_ADDR[31:0]={DEVICE(ADVAD)[31:27],??[26:24],TSC_ID(PHYAD)[23:19], 5182 * PORT_MODE(LANE)[18:16], IEEE_BIT[15], BLOCK[14:4], REG[3:0]} 5183 * - QSGMII_ADDR[31:0]={DEVICE(ADVAD)[31:27], LANE[26:16], REG_HI[15], 5184 * BLOCK[14:4], REG_LO[3:0]}} 5185 */ 5186 #define PHY_REG_ADDR_DEVAD(_phy_reg) (((_phy_reg) >> 27) & 0x1f) 5187 #define TSC_REG_ADDR_TSCID(_phy_reg) (((_phy_reg) >> 19) & 0x1f) 5188 #define TSC_REG_ADDR_PORTMODE(_phy_reg) (((_phy_reg) >> 16) & 0x7) 5189 #define QSGMII_REG_ADDR_LANE(_phy_reg) (((_phy_reg) >> 16) & 0x7ff) 5190 #define PHY_REG_ADDR_BLOCK(_phy_reg) (((_phy_reg) >> 4) & 0xfff) 5191 #define TSC_REG_ADDR_REG(_phy_reg) ((_phy_reg) & 0xf) 5192 #define QSGMII_REG_ADDR_REG(_phy_reg) ((((_phy_reg) & 0x8000) >> 11) | \ 5193 ((_phy_reg) & 0xf)) 5194 5195 #define IS_QSGMII_REGISTER(_phy_reg) (((_phy_reg) & 0xf800f000) == 0x8000) 5196 #define TSC_REG_ADDR_TSCID_SET(_phy_reg, _phyad) \ 5197 ((_phy_reg) |= ((_phyad) & 0x1f) << 19) 5198 #define QSGMII_REG_ADDR_LANE_SET(_phy_reg_new, _phy_reg) \ 5199 ((_phy_reg_new) |= ((_phy_reg) & 0x7ff0000)) 5200 5201 /* to check if this PHY register access sbus MDIO request is for 5202 * QSGMII register. 5203 */ 5204 STATIC int 5205 _soc_greyhound_qsgmii_reg_access_check(int unit, 5206 uint32 port, uint32 phyreg, int *to_qsgmii) 5207 { 5208 *to_qsgmii = 0; 5209 if (PHY_REG_ADDR_DEVAD(phyreg) == 0){ /* DEVAD==0 for PCS */ 5210 if (IS_QSGMII_REGISTER(phyreg)) { 5211 *to_qsgmii = 1; 5212 } else if ((QSGMII_REG_ADDR_REG(phyreg) < 0x10) && 5213 GH_PORT_IS_QSGMII(unit, port)) { 5214 /* means QSGMII port on accessing IEEE registers */ 5215 *to_qsgmii = 1; 5216 } 5217 } 5218 5219 return SOC_E_NONE; 5220 } 5221 5222 STATIC int 5223 _soc_greyhound_indacc_addr(uint32 phy_reg, int *target_select) 5224 { 5225 if (QSGMII_REG_ADDR_LANE(phy_reg) <= 15) { 5226 *target_select = (QSGMII_REG_ADDR_LANE(phy_reg) < 8) ? 0 : 1; 5227 return SOC_E_NONE; 5228 } 5229 5230 return SOC_E_INTERNAL; 5231 } 5232 5233 STATIC int 5234 _soc_greyhound_indacc_wait(int unit, soc_field_t fwait) 5235 { 5236 uint32 ctlsts; 5237 int poll = 1000; 5238 5239 do { 5240 SOC_IF_ERROR_RETURN( 5241 READ_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, &ctlsts)); 5242 if (soc_reg_field_get(unit, CHIP_INDACC_CTLSTSr, ctlsts, fwait)) { 5243 break; 5244 } 5245 } while (--poll > 0); 5246 5247 if (poll <= 0) { 5248 return SOC_E_TIMEOUT; 5249 } 5250 return SOC_E_NONE; 5251 } 5252 5253 STATIC int 5254 _soc_greyhound_indacc_read(int unit, uint32 phy_addr, 5255 uint32 phy_reg, uint32 *phy_data) 5256 { 5257 uint32 ctlsts; 5258 int ts; 5259 uint32 reg_addr = 0; 5260 5261 LOG_DEBUG(BSL_LS_SOC_MII, 5262 (BSL_META_U(unit, 5263 "_soc_greyhound_indacc_read" 5264 "(%d,0x%x,0x%08x,*phy_data)..\n"), 5265 unit, phy_addr, phy_reg)); 5266 5267 SOC_IF_ERROR_RETURN( 5268 _soc_greyhound_indacc_addr(phy_reg, &ts)); 5269 5270 ctlsts = 0; 5271 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, TARGET_SELECTf, ts); 5272 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, RD_REQf, 1); 5273 5274 /* assigning the reg_addr in Clause22 format */ 5275 reg_addr = phy_reg & 0x1f; 5276 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, ADDRESSf, reg_addr); 5277 5278 LOG_DEBUG(BSL_LS_SOC_MII, 5279 (BSL_META_U(unit, 5280 "_soc_greyhound_indacc_read:" 5281 "INDACC_CTLSTSr=0x%08x\n"), ctlsts)); 5282 SOC_IF_ERROR_RETURN( 5283 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, ctlsts)); 5284 5285 SOC_IF_ERROR_RETURN( 5286 _soc_greyhound_indacc_wait(unit, RD_RDYf)); 5287 5288 SOC_IF_ERROR_RETURN( 5289 READ_CHIP_INDACC_RDATAr(unit, REG_PORT_ANY, phy_data)); 5290 5291 SOC_IF_ERROR_RETURN( 5292 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, 0)); 5293 5294 return SOC_E_NONE; 5295 } 5296 5297 STATIC int 5298 _soc_greyhound_indacc_write(int unit, uint32 phy_addr, 5299 uint32 phy_reg, uint32 phy_data) 5300 { 5301 uint32 ctlsts; 5302 int ts; 5303 uint32 reg_addr = 0; 5304 5305 LOG_DEBUG(BSL_LS_SOC_MII, 5306 (BSL_META_U(unit, 5307 "_soc_greyhound_indacc_write" 5308 "(%d,0x%x,0x%08x,0x%04x)..\n"), 5309 unit, phy_addr, phy_reg, phy_data)); 5310 SOC_IF_ERROR_RETURN( 5311 WRITE_CHIP_INDACC_WDATAr(unit, REG_PORT_ANY, phy_data)); 5312 5313 SOC_IF_ERROR_RETURN( 5314 _soc_greyhound_indacc_addr(phy_reg, &ts)); 5315 5316 ctlsts = 0; 5317 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, TARGET_SELECTf, ts); 5318 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, WR_REQf, 1); 5319 5320 /* assigning the reg_addr in Clause22 format */ 5321 reg_addr = phy_reg & 0x1f; 5322 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, ADDRESSf, reg_addr); 5323 5324 LOG_DEBUG(BSL_LS_SOC_MII, 5325 (BSL_META_U(unit, 5326 "_soc_greyhound_indacc_write:" 5327 "INDACC_CTLSTSr=0x%08x\n"), ctlsts)); 5328 SOC_IF_ERROR_RETURN( 5329 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, ctlsts)); 5330 5331 SOC_IF_ERROR_RETURN( 5332 _soc_greyhound_indacc_wait(unit, WR_RDYf)); 5333 5334 SOC_IF_ERROR_RETURN( 5335 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, 0)); 5336 5337 return SOC_E_NONE; 5338 } 5339 5340 STATIC int 5341 _soc_greyhound_sbus_qsgmii_read(int unit, 5342 uint32 phy_addr, uint32 phy_reg, uint32 *phy_data) 5343 { 5344 uint32 reg_addr, reg_data; 5345 5346 *phy_data = 0; 5347 5348 LOG_DEBUG(BSL_LS_SOC_MII, 5349 (BSL_META_U(unit, 5350 "_soc_greyhound_sbus_qsgmii_read" 5351 "(%d,0x%x,0x%08x,*phy_data)..\n"), 5352 unit, phy_addr, phy_reg)); 5353 5354 /* The "phy_reg" in Sbus MDIO access is expected in 32 bits PHY address 5355 * format with AER information included. Since this interface allows 5356 * MDIO access in Claue22 only, the AER process must be applied. 5357 */ 5358 5359 /* AER process : AER block selection */ 5360 reg_addr = 0x1f; 5361 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5362 reg_data = 0xffd0; 5363 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_write(unit, 5364 phy_addr, reg_addr, reg_data)); 5365 5366 /* AER process : lane control */ 5367 reg_addr = 0x1e; 5368 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5369 /* lane control to indicated lane 0~7 for each QSGMIMI core */ 5370 reg_data = QSGMII_REG_ADDR_LANE(phy_reg) & 0x7; 5371 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_write(unit, 5372 phy_addr, reg_addr, reg_data)); 5373 5374 /* target register block selection */ 5375 reg_addr = 0x1f; 5376 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5377 reg_data = phy_reg & 0xfff0; 5378 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_write(unit, 5379 phy_addr, reg_addr, reg_data)); 5380 5381 /* read data */ 5382 reg_addr = QSGMII_REG_ADDR_REG(phy_reg); 5383 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5384 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_read(unit, 5385 phy_addr, reg_addr, ®_data)); 5386 5387 *phy_data = reg_data; 5388 5389 LOG_DEBUG(BSL_LS_SOC_MII, 5390 (BSL_META_U(unit, 5391 "_soc_greyhound_sbus_qsgmii_read()...data=0x%04x\n"), 5392 *phy_data)); 5393 5394 return SOC_E_NONE; 5395 } 5396 5397 STATIC int 5398 _soc_greyhound_sbus_qsgmii_write(int unit, 5399 uint32 phy_addr, uint32 phy_reg, uint32 phy_data) 5400 { 5401 uint32 reg_addr, reg_data; 5402 5403 LOG_DEBUG(BSL_LS_SOC_MII, 5404 (BSL_META_U(unit, 5405 "_soc_greyhound_sbus_qsgmii_write" 5406 "(%d,0x%x,0x%08x,0x%04x)..\n"), 5407 unit, phy_addr, phy_reg, phy_data)); 5408 5409 /* The "phy_reg" in Sbus MDIO access is expected in 32 bits PHY address 5410 * format with AER information included. Since this interface allows 5411 * MDIO access in Claue22 only, the AER process must be applied. 5412 */ 5413 5414 /* AER process : AER block selection */ 5415 reg_addr = 0x1f; 5416 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5417 reg_data = 0xffd0; 5418 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_write(unit, 5419 phy_addr, reg_addr, reg_data)); 5420 5421 /* AER process : lane control */ 5422 reg_addr = 0x1e; 5423 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5424 /* lane control to indicated lane 0~7 for each QSGMIMI core */ 5425 reg_data = QSGMII_REG_ADDR_LANE(phy_reg) & 0x7; 5426 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_write(unit, 5427 phy_addr, reg_addr, reg_data)); 5428 5429 /* target register block selection */ 5430 reg_addr = 0x1f; 5431 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5432 reg_data = phy_reg & 0xfff0; 5433 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_write(unit, 5434 phy_addr, reg_addr, reg_data)); 5435 5436 /* write data */ 5437 reg_addr = QSGMII_REG_ADDR_REG(phy_reg); 5438 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 5439 SOC_IF_ERROR_RETURN(_soc_greyhound_indacc_write(unit, 5440 phy_addr, reg_addr, phy_data)); 5441 5442 LOG_DEBUG(BSL_LS_SOC_MII, 5443 (BSL_META_U(unit, 5444 "_soc_greyhound_sbus_qsgmii_write()... Done!"))); 5445 5446 return SOC_E_NONE; 5447 } 5448 5449 STATIC int 5450 _soc_greyhound_mdio_addr_to_port(uint32 phy_addr) 5451 { 5452 if (PHY_ID_BUS_NUM(phy_addr) == 1) { 5453 return (phy_addr & 0x1f) + 17; 5454 } else { 5455 return (phy_addr & 0x1f) + 1; 5456 } 5457 } 5458 5459 STATIC int 5460 _soc_greyhound_mdio_reg_read(int unit, uint32 phy_addr, 5461 uint32 phy_reg, uint32 *phy_data) 5462 { 5463 int rv; 5464 int port, phy_port, blk; 5465 int qsgmii_reg = 0; 5466 5467 LOG_DEBUG(BSL_LS_SOC_MII, 5468 (BSL_META_U(unit, 5469 "_soc_greyhound_mdio_reg_read(%d,0x%x,0x%08x,*phy_data)..\n"), 5470 unit, phy_addr, phy_reg)); 5471 /* Physical port based on MDIO address */ 5472 phy_port = _soc_greyhound_mdio_addr_to_port(phy_addr); 5473 port = SOC_INFO(unit).port_p2l_mapping[phy_port]; 5474 SOC_IF_ERROR_RETURN(_soc_gh_sbus_tsc_block(unit, 5475 phy_port, XLPORT_WC_UCMEM_DATAm, &blk)); 5476 5477 /* access interface selection */ 5478 SOC_IF_ERROR_RETURN(_soc_greyhound_qsgmii_reg_access_check(unit, 5479 port, phy_reg, &qsgmii_reg)); 5480 5481 if (qsgmii_reg) { 5482 MIIM_LOCK(unit); 5483 SOC_ALLOW_WB_WRITE(unit, _soc_greyhound_sbus_qsgmii_read(unit, phy_addr, 5484 phy_reg, phy_data), rv); 5485 MIIM_UNLOCK(unit); 5486 } else { 5487 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 5488 rv = soc_sbus_tsc_reg_read(unit, port, blk, phy_addr, 5489 phy_reg, phy_data); 5490 } 5491 return rv; 5492 } 5493 5494 STATIC int 5495 _soc_greyhound_mdio_reg_write(int unit, uint32 phy_addr, 5496 uint32 phy_reg, uint32 phy_data) 5497 { 5498 int rv; 5499 int port, phy_port, blk; 5500 int qsgmii_reg = 0; 5501 5502 LOG_DEBUG(BSL_LS_SOC_MII, 5503 (BSL_META_U(unit, 5504 "_soc_greyhound_mdio_reg_write(%d,0x%x,0x%08x,0x%04x)..\n"), 5505 unit, phy_addr, phy_reg,phy_data)); 5506 /* Physical port based on MDIO address */ 5507 phy_port = _soc_greyhound_mdio_addr_to_port(phy_addr); 5508 port = SOC_INFO(unit).port_p2l_mapping[phy_port]; 5509 SOC_IF_ERROR_RETURN(_soc_gh_sbus_tsc_block(unit, 5510 phy_port, XLPORT_WC_UCMEM_DATAm, &blk)); 5511 5512 /* access interface selection */ 5513 SOC_IF_ERROR_RETURN(_soc_greyhound_qsgmii_reg_access_check(unit, 5514 port, phy_reg, &qsgmii_reg)); 5515 5516 if (qsgmii_reg) { 5517 MIIM_LOCK(unit); 5518 rv = _soc_greyhound_sbus_qsgmii_write(unit, phy_addr, 5519 phy_reg, phy_data); 5520 MIIM_UNLOCK(unit); 5521 } else { 5522 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 5523 rv = soc_sbus_tsc_reg_write(unit, port, blk, phy_addr, 5524 phy_reg, phy_data); 5525 } 5526 return rv; 5527 } 5528 5529 #define _gh_get_pval(_map_, _idx_, _max_num_) \ 5530 ((_idx_ < _max_num_) ? _map_[_idx_]: 0) 5531 5532 /* The number of ports per TSCQ */ 5533 #define _GH_PORTS_NUM_PER_TSCQ (16) 5534 /* The number of ports per TSC */ 5535 #define _GH_PORTS_NUM_PER_TSC (4) 5536 /* The first physcial port number of TSC0Q */ 5537 #define _GH_FIRST_PHY_PORT_TSC0Q (2) 5538 /* The first physcial port number of TSC0 */ 5539 #define _GH_FIRST_PHY_PORT_TSC0 (_GH_FIRST_PHY_PORT_TSC0Q + _GH_PORTS_NUM_PER_TSCQ) 5540 5541 STATIC int 5542 _greyhound_ledup_init(int unit) 5543 { 5544 int i, j, pval1, pval2, pval3, pval4, port_idx, is_qmode = 0; 5545 uint32 led_remap[64] = {0}, led_cnt = 0, rval = 0, disable_4x10 = 0, disable_4x10q = 0; 5546 int freq, cycles; 5547 int refresh_rate = 30, refresh_period; 5548 5549 struct led_remap_t { 5550 uint32 reg_addr; 5551 uint32 port0; 5552 uint32 port1; 5553 uint32 port2; 5554 uint32 port3; 5555 } ledup0_remap_r[] = { 5556 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 5557 REMAP_PORT_0f, REMAP_PORT_1f, REMAP_PORT_2f, REMAP_PORT_3f}, 5558 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 5559 REMAP_PORT_4f, REMAP_PORT_5f, REMAP_PORT_6f, REMAP_PORT_7f}, 5560 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 5561 REMAP_PORT_8f, REMAP_PORT_9f, REMAP_PORT_10f, REMAP_PORT_11f}, 5562 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 5563 REMAP_PORT_12f, REMAP_PORT_13f, REMAP_PORT_14f, REMAP_PORT_15f}, 5564 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 5565 REMAP_PORT_16f, REMAP_PORT_17f, REMAP_PORT_18f, REMAP_PORT_19f}, 5566 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 5567 REMAP_PORT_20f, REMAP_PORT_21f, REMAP_PORT_22f, REMAP_PORT_23f}, 5568 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 5569 REMAP_PORT_24f, REMAP_PORT_25f, REMAP_PORT_26f, REMAP_PORT_27f}, 5570 {CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, 5571 REMAP_PORT_28f, REMAP_PORT_29f, REMAP_PORT_30f, REMAP_PORT_31f}, 5572 {CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, 5573 REMAP_PORT_32f, REMAP_PORT_33f, REMAP_PORT_34f, REMAP_PORT_35f}, 5574 {CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, 5575 REMAP_PORT_36f, REMAP_PORT_37f, REMAP_PORT_38f, REMAP_PORT_39f} 5576 }; 5577 5578 /* Program the LED clock output frequency based on core clock */ 5579 freq = SOC_INFO(unit).frequency; 5580 5581 /* For LEDCLK_HALF_PERIOD */ 5582 /* Formula : cycles = (freq * 10^6) * (100 * 10^-9) = freq/10 */ 5583 /* Round up the value for non-integer clocks */ 5584 cycles = (freq + 9) / 10 - 1; 5585 5586 rval = 0; 5587 soc_reg_field_set(unit, CMIC_LEDUP0_CLK_DIVr, &rval, 5588 LEDCLK_HALF_PERIODf, cycles); 5589 /* coverity[result_independent_of_operands] */ 5590 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CLK_DIVr(unit, rval)); 5591 /* coverity[result_independent_of_operands] */ 5592 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CLK_DIVr(unit, rval)); 5593 5594 /* For REFRESH_CYCLE_PERIOD */ 5595 /* Formula : refresh_period = (freq * 10^6) / 30 */ 5596 /* refresh_rate = 30Hz */ 5597 refresh_period = freq * 1000000 / refresh_rate; 5598 5599 rval = 0; 5600 soc_reg_field_set(unit, CMIC_LEDUP0_CLK_PARAMSr, &rval, 5601 REFRESH_CYCLE_PERIODf, refresh_period); 5602 /* coverity[result_independent_of_operands] */ 5603 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CLK_PARAMSr(unit, rval)); 5604 /* coverity[result_independent_of_operands] */ 5605 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CLK_PARAMSr(unit, rval)); 5606 5607 /* The LED scanning out order is 5608 * TSC4(37->34) -> TSC3(33->30) -> TSC2(29->26) -> TSC1(25->22) -> TSC0(21->18) -> TSC0Q(2->17(QSGMII)/5->2(Non-QSGMII)) 5609 * If a TSC is ON, it will output 4 bytes LED status to the LED chain 5610 * If a TSCQ is ON, it will output 4 bytes for Non-QSGMII mode, or 16 bytes for QSGMII mode. 5611 * If a TSC/TSCQ is OFF, it will output 1 byte, bit[7:0] are all zero, to the LED chain 5612 */ 5613 5614 /* Construct the LED reamp by TSC status */ 5615 rval = 0; 5616 SOC_IF_ERROR_RETURN(READ_PGW_CTRL_0r(unit, &rval)); 5617 disable_4x10 = soc_reg_field_get(unit, PGW_CTRL_0r, rval, SW_PM4X10_DISABLEf); 5618 disable_4x10q = soc_reg_field_get(unit, PGW_CTRL_0r, rval, SW_PM4X10Q_DISABLEf); 5619 5620 if (!disable_4x10q) { 5621 SOC_IF_ERROR_RETURN(READ_CHIP_CONFIGr(unit, REG_PORT_ANY, &rval)); 5622 is_qmode = soc_reg_field_get(unit, CHIP_CONFIGr, rval, QMODEf); 5623 } 5624 5625 /* TSC4 LED data is shifted out first and TSC0 is the last */ 5626 for (i = 4; i >= 0; i--) { 5627 if (disable_4x10 & (1 << i)) { 5628 led_remap[led_cnt++] = 0; 5629 } else { 5630 /* For each TSC, the status of port 3 is shifted out first and port 0 is the last */ 5631 for (j = 3; j >= 0; j--) { 5632 led_remap[led_cnt++] = _GH_FIRST_PHY_PORT_TSC0 + _GH_PORTS_NUM_PER_TSC * i + j; 5633 } 5634 } 5635 } 5636 5637 /* TSCQ LED data is shifted out after TSCs */ 5638 if (disable_4x10q) { 5639 led_remap[led_cnt++] = 0; 5640 } else { 5641 if (is_qmode) { 5642 /* For QSGMII mode, the status of port 0 is shifted out first and port 15 is the last */ 5643 for (i = 0; i <= 15; i++) { 5644 led_remap[led_cnt++] = _GH_FIRST_PHY_PORT_TSC0Q + i; 5645 } 5646 } else { 5647 /* For Non-QSGMII mode, the status of port 3 is shifted out first and port 0 is the last */ 5648 for (i = 3; i >= 0; i--) { 5649 led_remap[led_cnt++] = _GH_FIRST_PHY_PORT_TSC0Q + i; 5650 } 5651 } 5652 } 5653 5654 /* Setup the led remap registers */ 5655 for (i = 0; i < sizeof(ledup0_remap_r)/sizeof(ledup0_remap_r[0]); i++) { 5656 port_idx = i * 4; 5657 pval1 = _gh_get_pval(led_remap, port_idx, led_cnt); 5658 pval2 = _gh_get_pval(led_remap, port_idx + 1, led_cnt); 5659 pval3 = _gh_get_pval(led_remap, port_idx + 2, led_cnt); 5660 pval4 = _gh_get_pval(led_remap, port_idx + 3, led_cnt); 5661 5662 rval = 0; 5663 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5664 ledup0_remap_r[i].port0, pval1); 5665 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5666 ledup0_remap_r[i].port1, pval2); 5667 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5668 ledup0_remap_r[i].port2, pval3); 5669 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5670 ledup0_remap_r[i].port3, pval4); 5671 SOC_IF_ERROR_RETURN 5672 (soc_pci_write(unit, 5673 soc_reg_addr(unit, ledup0_remap_r[i].reg_addr, REG_PORT_ANY, 0), 5674 rval)); 5675 } 5676 5677 /* Initialize the UP0 data ram */ 5678 rval = 0; 5679 for (i = 0; i < 256; i++) { 5680 /* coverity[result_independent_of_operands] */ 5681 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit, i, rval)); 5682 } 5683 5684 /* Apply LEDUP delays. */ 5685 SOC_IF_ERROR_RETURN(READ_AMAC_IDM0_IO_CONTROL_DIRECTr(unit, &rval)); 5686 5687 /* GH-1651. For QSGMII mode, set LEDSCAN_FLOP_STAGESf to 0x3. O/W, set to 0x4 */ 5688 if (is_qmode) { 5689 soc_reg_field_set(unit, AMAC_IDM0_IO_CONTROL_DIRECTr, 5690 &rval, LEDSCAN_FLOP_STAGESf, 0x3); 5691 } else { 5692 soc_reg_field_set(unit, AMAC_IDM0_IO_CONTROL_DIRECTr, 5693 &rval, LEDSCAN_FLOP_STAGESf, 0x4); 5694 } 5695 SOC_IF_ERROR_RETURN(WRITE_AMAC_IDM0_IO_CONTROL_DIRECTr(unit, rval)); 5696 5697 return SOC_E_NONE; 5698 } 5699 5700 STATIC int 5701 _soc_greyhound_qsgmii_mode_check(int unit, int *qsgmii_mode) 5702 { 5703 uint16 dev_id; 5704 uint8 rev_id; 5705 5706 soc_cm_get_id(unit, &dev_id, &rev_id); 5707 if ((dev_id & 0xF000) == 0x8000) { 5708 if ((dev_id & 0x0060) != 0x0000) { /* Elkhound and Bloodhound */ 5709 if ((dev_id & 0x00F6) == 0x0054) { /* 53454/53455 */ 5710 dev_id &= 0xFFF4; /* use 53454 */ 5711 } 5712 if ((dev_id & 0x00F6) == 0x0056) { /* 53456/53457 */ 5713 dev_id &= 0xFFF6; /* use 53456 */ 5714 } 5715 /* no change on Bloodhound */ 5716 } else { 5717 dev_id &= 0xFF0F; 5718 } 5719 /* no change on Bloodhound */ 5720 } 5721 if (dev_id == BCM56064_DEVICE_ID || dev_id == BCM56063_DEVICE_ID || 5722 dev_id == BCM53401_DEVICE_ID || dev_id == BCM56062_DEVICE_ID || 5723 dev_id == BCM53456_DEVICE_ID || dev_id == BCM53424_DEVICE_ID) { 5724 *qsgmii_mode = 1; 5725 } 5726 return SOC_E_NONE; 5727 } 5728 5729 STATIC int 5730 soc_greyhound_freq_get(int unit, int *frequency, int *change_freq){ 5731 5732 uint16 dev_id; 5733 uint8 rev_id; 5734 5735 soc_cm_get_id(unit, &dev_id, &rev_id); 5736 5737 if (((dev_id & 0xF000) == 0x8000) && 5738 (dev_id != BCM53365_DEVICE_ID)){ 5739 if ((dev_id & 0x0060) != 0x0000) { /* Elkhound and Bloodhound */ 5740 if ((dev_id & 0x00F6) == 0x0054) { /* 53454/53455 */ 5741 dev_id &= 0xFFF4; /* use 53454 */ 5742 } 5743 if ((dev_id & 0x00F6) == 0x0056) { /* 53456/53457 */ 5744 dev_id &= 0xFFF6; /* use 53456*/ 5745 } 5746 /* no change on Bloodhound */ 5747 } else { 5748 dev_id &= 0xFF0F; 5749 } 5750 } 5751 *change_freq = 0; 5752 5753 switch (dev_id) { 5754 case BCM56064_DEVICE_ID: 5755 case BCM56063_DEVICE_ID: 5756 case BCM53408_DEVICE_ID: 5757 case BCM53402_DEVICE_ID: 5758 case BCM53401_DEVICE_ID: 5759 case BCM53422_DEVICE_ID: 5760 case BCM53424_DEVICE_ID: 5761 case BCM53426_DEVICE_ID: 5762 case BCM56066_DEVICE_ID: 5763 *frequency = 176; 5764 break; 5765 case BCM53403_DEVICE_ID: 5766 case BCM53404_DEVICE_ID: 5767 *frequency = 176; 5768 *change_freq = 1; 5769 break; 5770 case BCM56060_DEVICE_ID: 5771 case BCM53405_DEVICE_ID: 5772 case BCM53406_DEVICE_ID: 5773 case BCM56062_DEVICE_ID: 5774 case BCM53454_DEVICE_ID: 5775 case BCM53456_DEVICE_ID: 5776 case BCM56065_DEVICE_ID: 5777 case BCM53365_DEVICE_ID: 5778 case BCM53369_DEVICE_ID: 5779 *frequency = 300; 5780 break; 5781 default: 5782 *frequency = 0; 5783 break; 5784 }; 5785 return SOC_E_NONE; 5786 } 5787 5788 5789 STATIC int 5790 _soc_greyhound_misc_init(int unit) 5791 { 5792 #define NUM_XLPORT 4 5793 static const soc_field_t port_field[] = { 5794 PORT0f, PORT1f, PORT2f, PORT3f 5795 }; 5796 uint32 rval, fval; 5797 uint32 prev_reg_addr; 5798 uint64 reg64; 5799 int port; 5800 uint32 entry[SOC_MAX_MEM_WORDS]; 5801 soc_field_t fields[3]; 5802 uint32 values[3]; 5803 int blk, bindex, mode; 5804 int phy_port_base; 5805 soc_info_t *si = &SOC_INFO(unit); 5806 int parity_enable, blk_port, phy_port, delay; 5807 int freq, target_freq, divisor, dividend; 5808 char *board_name; 5809 int temp; 5810 5811 #ifdef INCLUDE_MEM_SCAN 5812 /* Stop the mem scan task before all of the parity init takes place */ 5813 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_stop(unit)); 5814 #endif /* INCLUDE_MEM_SCAN */ 5815 5816 5817 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 5818 /* Clear IPIPE/EIPIE Memories */ 5819 SOC_IF_ERROR_RETURN(soc_greyhound_pipe_mem_clear(unit)); 5820 5821 /* Reset XLPORT MIB counter (registers implemented in memory). The clear 5822 * function is implemented with read-modify-write, parity needs to be 5823 * disabled */ 5824 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 5825 blk_port = SOC_BLOCK_PORT(unit, blk); 5826 if (blk_port < 0) { 5827 continue; 5828 } 5829 phy_port = si->port_l2p_mapping[blk_port]; 5830 fval = 0; 5831 for (bindex = 0; bindex < 4; bindex++) { 5832 if (si->port_p2l_mapping[phy_port + bindex] != -1) { 5833 fval |= 1 << bindex; 5834 } 5835 } 5836 rval = 0; 5837 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, fval); 5838 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, blk_port, rval)); 5839 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, blk_port, 0)); 5840 } 5841 } 5842 5843 SOC_IF_ERROR_RETURN(soc_greyhound_init_port_mapping(unit)); 5844 5845 5846 /* Turn on ingress/egress/mmu parity */ 5847 _soc_gh_tcam_ser_info[unit] = NULL; 5848 _soc_gh_parity_group_info[unit] = NULL; 5849 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 5850 if (soc_feature(unit, soc_feature_field_multi_stage)) { 5851 _soc_gh_parity_group_info[unit] = _soc_rg2_parity_group_info_template; 5852 } else { 5853 _soc_gh_parity_group_info[unit] = _soc_gh_parity_group_info_template; 5854 } 5855 if (parity_enable) { 5856 (void)_soc_greyhound_tcam_ser_init(unit); 5857 #if defined(SER_TR_TEST_SUPPORT) 5858 soc_gh_ser_test_register(unit); 5859 #endif /*defined(SER_TR_TEST_SUPPORT*/ 5860 #ifdef INCLUDE_MEM_SCAN 5861 soc_mem_scan_ser_list_register(unit, TRUE, _soc_gh_tcam_ser_info[unit]); 5862 #endif /* INCLUDE_MEM_SCAN */ 5863 memset(&_gh_ser_functions[unit], 0, sizeof(soc_ser_functions_t)); 5864 _gh_ser_functions[unit]._soc_ser_fail_f = &soc_greyhound_ser_fail; 5865 _gh_ser_functions[unit]._soc_ser_parity_error_cmicm_intr_f = 5866 &soc_greyhound_parity_error; 5867 _gh_ser_functions[unit]._soc_ser_mem_nack_f = 5868 &soc_greyhound_mem_nack; 5869 soc_ser_function_register(unit, &_gh_ser_functions[unit]); 5870 #if GREYHOUND_SER_PARITY_ENABLED 5871 /* Enabling the packet drop when parity error occurred */ 5872 SOC_IF_ERROR_RETURN(READ_IPIPE_PERR_CONTROLr(unit, &rval)); 5873 fval = 1; 5874 soc_reg_field_set(unit, IPIPE_PERR_CONTROLr, &rval, DROPf, fval); 5875 SOC_IF_ERROR_RETURN(WRITE_IPIPE_PERR_CONTROLr(unit, rval)); 5876 (void)_soc_greyhound_parity_enable(unit, TRUE); 5877 #endif /* GREYHOUND_SER_PARITY_ENABLED */ 5878 } else { 5879 #if GREYHOUND_SER_PARITY_ENABLED 5880 (void)_soc_greyhound_parity_enable(unit, FALSE); 5881 #endif /* GREYHOUND_SER_PARITY_ENABLED */ 5882 } 5883 5884 /* set QMODE enable for TSC0Q at QSGMII mode before unimac init process 5885 * - GH's QSGMII in TSC0Q only and check proper SKU to enable QMODE. 5886 */ 5887 5888 SOC_IF_ERROR_RETURN(READ_PGW_CTRL_0r(unit, &rval)); 5889 fval = soc_reg_field_get(unit, PGW_CTRL_0r, rval, SW_PM4X10Q_DISABLEf); 5890 /* ensure the TSC0Q is enabled */ 5891 if (fval == 0) { 5892 int qsgmii_mode = 0; 5893 (void)_soc_greyhound_qsgmii_mode_check(unit, &qsgmii_mode); 5894 SOC_IF_ERROR_RETURN(READ_CHIP_CONFIGr(unit, REG_PORT_ANY, &rval)); 5895 fval = 0; 5896 /* only 56064|56063|53401(also 53411)|56062|53456(also 53457)|53424 5897 support TSC0Q at QSGMII mode */ 5898 if (qsgmii_mode == 1){ 5899 fval = 1; 5900 } 5901 soc_reg_field_set(unit, CHIP_CONFIGr, &rval, QMODEf, fval); 5902 SOC_IF_ERROR_RETURN(WRITE_CHIP_CONFIGr(unit, REG_PORT_ANY, rval)); 5903 } 5904 5905 /* GMAC init should be moved to mac */ 5906 rval = 0; 5907 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 5908 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, GPORT_ENf, 1); 5909 prev_reg_addr = 0xffffffff; 5910 PBMP_E_ITER(unit, port) { 5911 uint32 reg_addr; 5912 if (IS_XL_PORT(unit, port)) { 5913 continue; 5914 } 5915 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 5916 if (reg_addr != prev_reg_addr) { 5917 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 5918 prev_reg_addr = reg_addr; 5919 } 5920 } 5921 prev_reg_addr = 0xffffffff; 5922 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 5923 PBMP_E_ITER(unit, port) { 5924 uint32 reg_addr; 5925 if (IS_XL_PORT(unit, port)) { 5926 continue; 5927 } 5928 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 5929 if (reg_addr != prev_reg_addr) { 5930 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 5931 prev_reg_addr = reg_addr; 5932 } 5933 } 5934 5935 PBMP_PORT_ITER(unit, port) { 5936 if (!IS_HG_PORT(unit, port)) { 5937 continue; 5938 } 5939 5940 /* Section below is used to config XLPORT and PGW related HiGig encap 5941 * setting for normal init process. 5942 */ 5943 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 5944 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 5945 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 5946 5947 /* only HG ports allows PGW encap setting below */ 5948 SOC_IF_ERROR_RETURN(soc_greyhound_pgw_encap_field_modify(unit, 5949 port, HIGIG_MODEf, 1)); 5950 } 5951 5952 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 5953 int lane_mode, i; 5954 port = SOC_BLOCK_PORT(unit, blk); 5955 if (port == -1 || port == REG_PORT_ANY) { 5956 continue; 5957 } 5958 phy_port_base = si->port_l2p_mapping[port]; 5959 5960 5961 lane_mode = -1; 5962 5963 for(i=0; i <_GH_MAX_TSC_COUNT ; i++){ 5964 if(_gh_tsc[i].phy_port_base == phy_port_base){ 5965 lane_mode = _gh_tsc[i].lane_mode; 5966 break; 5967 } 5968 } 5969 if (lane_mode == _GH_TSC_LANE_MODE_SINGLE) { 5970 mode = SOC_GH_PORT_MODE_QUAD; 5971 si->port_num_lanes[port] = 1; 5972 si->port_num_lanes[port+1] = 1; 5973 si->port_num_lanes[port+2] = 1; 5974 si->port_num_lanes[port+3] = 1; 5975 } else if (lane_mode == _GH_TSC_LANE_MODE_XAUI) { 5976 mode = SOC_GH_PORT_MODE_SINGLE; 5977 si->port_num_lanes[port] = 4; 5978 } else if (lane_mode == _GH_TSC_LANE_MODE_RXAUI){ 5979 mode = SOC_GH_PORT_MODE_DUAL; 5980 si->port_num_lanes[port] = 2; 5981 /* logical port_id in this case will not in serial list */ 5982 si->port_num_lanes[port+2]= 2; 5983 } else if (lane_mode == _GH_TSC_LANE_MODE_RXAUI13G){ 5984 mode = SOC_GH_PORT_MODE_DUAL; 5985 si->port_num_lanes[port] = 2; 5986 si->port_num_lanes[port+1]= 2; 5987 } else { 5988 mode = SOC_GH_PORT_MODE_QUAD; 5989 si->port_num_lanes[port] = 1; 5990 si->port_num_lanes[port+1] = 1; 5991 si->port_num_lanes[port+2] = 1; 5992 si->port_num_lanes[port+3] = 1; 5993 } 5994 rval = 0; 5995 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 5996 XPORT0_CORE_PORT_MODEf, mode); 5997 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 5998 XPORT0_PHY_PORT_MODEf, mode); 5999 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 6000 6001 /* Enable XLPORT */ 6002 rval = 0; 6003 for (bindex = 0; bindex < NUM_XLPORT; bindex++) { 6004 if (si->port_p2l_mapping[phy_port_base + bindex] != -1) { 6005 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, 6006 port_field[bindex], 1); 6007 } 6008 } 6009 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ENABLE_REGr(unit, port, rval)); 6010 } 6011 6012 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 6013 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 6014 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 6015 6016 /* Enable dual hash on L2 and L3 tables */ 6017 fields[0] = ENABLEf; 6018 values[0] = 1; 6019 fields[1] = HASH_SELECTf; 6020 values[1] = FB_HASH_CRC32_LOWER; 6021 fields[2] = INSERT_LEAST_FULL_HALFf; 6022 values[2] = 1; 6023 SOC_IF_ERROR_RETURN 6024 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 6025 fields, values)); 6026 SOC_IF_ERROR_RETURN 6027 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 6028 fields, values)); 6029 6030 /* 6031 * Egress Enable 6032 */ 6033 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 6034 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 6035 PBMP_ALL_ITER(unit, port) { 6036 SOC_IF_ERROR_RETURN 6037 (WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, SOC_INFO(unit).port_l2p_mapping[port], entry)); 6038 } 6039 6040 COMPILER_64_ZERO(reg64); 6041 soc_reg64_field32_set(unit, EPC_LINK_BMAP_64r, ®64, PORT_BITMAP_LOf, 6042 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 0)); 6043 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAP_64r(unit, reg64)); 6044 6045 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 6046 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 6047 L3SRC_HIT_ENABLEf, 1); 6048 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 6049 L2DST_HIT_ENABLEf, 1); 6050 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 6051 APPLY_EGR_MASK_ON_L2f, 1); 6052 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 6053 APPLY_EGR_MASK_ON_L3f, 1); 6054 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 6055 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 6056 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 6057 ARP_VALIDATION_ENf, 1); 6058 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 6059 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 6060 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 6061 6062 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 6063 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, RING_MODEf, 1); 6064 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 6065 6066 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 6067 * causes the outer tag to be removed from packets that don't have 6068 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 6069 */ 6070 rval = 0; 6071 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 6072 6073 /* Enable pri/cfi remarking on egress ports. */ 6074 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 6075 1); 6076 PBMP_ALL_ITER(unit, port) { 6077 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 6078 } 6079 6080 /* Multicast range initialization */ 6081 SOC_IF_ERROR_RETURN 6082 (soc_hbx_higig2_mcast_sizes_set(unit, 6083 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 6084 SOC_HBX_MULTICAST_RANGE_DEFAULT), 6085 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 6086 SOC_HBX_MULTICAST_RANGE_DEFAULT), 6087 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 6088 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 6089 6090 /* Setup SW2_FP_DST_ACTION_CONTROL */ 6091 fields[0] = HGTRUNK_RES_ENf; 6092 fields[1] = LAG_RES_ENf; 6093 values[0] = values[1] = 1; 6094 SOC_IF_ERROR_RETURN 6095 (soc_reg_fields32_modify(unit, SW2_FP_DST_ACTION_CONTROLr, 6096 REG_PORT_ANY, 2, fields, values)); 6097 6098 freq = si->frequency; 6099 if (freq == 0) { 6100 (void)soc_greyhound_freq_get(unit, &si->frequency, &temp); 6101 freq = si->frequency; 6102 } 6103 6104 /* 6105 * Set external MDIO freq to around 10MHz 6106 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 6107 */ 6108 if (!SOC_WARM_BOOT(unit)) { 6109 target_freq = 10; 6110 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 6111 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, divisor); 6112 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 6113 6114 rval = 0; 6115 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVISORf, divisor); 6116 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVIDENDf, dividend); 6117 /* coverity[result_independent_of_operands] */ 6118 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 6119 } 6120 6121 /* 6122 * Set internal MDIO freq to around 10MHz 6123 * Valid range is from 2.5MHz to 12.5MHz 6124 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 6125 * or 6126 * DIVISOR = core_clock_freq * DIVIDENT / (target_freq * 2) 6127 */ 6128 target_freq = 10; 6129 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 6130 divisor = soc_property_get(unit, spn_RATE_INT_MDIO_DIVISOR, divisor); 6131 dividend = soc_property_get(unit, spn_RATE_INT_MDIO_DIVIDEND, 1); 6132 rval = 0; 6133 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVISORf, 6134 divisor); 6135 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVIDENDf, 6136 dividend); 6137 /* coverity[result_independent_of_operands] */ 6138 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 6139 6140 delay = soc_property_get(unit, spn_MDIO_OUTPUT_DELAY, -1); 6141 if (delay >= 1 && delay <= 15) { 6142 /* coverity[result_independent_of_operands] */ 6143 SOC_IF_ERROR_RETURN(READ_CMIC_MIIM_CONFIGr(unit, &rval)); 6144 soc_reg_field_set(unit, CMIC_MIIM_CONFIGr, &rval, MDIO_OUT_DELAYf, 6145 delay); 6146 /* coverity[result_independent_of_operands] */ 6147 SOC_IF_ERROR_RETURN(WRITE_CMIC_MIIM_CONFIGr(unit, rval)); 6148 } 6149 6150 /* Directed Mirroring ON by default except for CPU port */ 6151 /* The src_port info will be changed as egress port if EM_SRCMOD_CHANGEf = 1 */ 6152 PBMP_PORT_ITER(unit, port) { 6153 SOC_IF_ERROR_RETURN(READ_EGR_PORT_64r(unit, port, ®64)); 6154 soc_reg64_field32_set(unit, EGR_PORT_64r, ®64, EM_SRCMOD_CHANGEf, 1); 6155 SOC_IF_ERROR_RETURN(WRITE_EGR_PORT_64r(unit, port, reg64)); 6156 SOC_IF_ERROR_RETURN(READ_IEGR_PORT_64r(unit, port, ®64)); 6157 soc_reg64_field32_set(unit, IEGR_PORT_64r, ®64, EM_SRCMOD_CHANGEf, 1); 6158 SOC_IF_ERROR_RETURN(WRITE_IEGR_PORT_64r(unit, port, reg64)); 6159 } 6160 6161 _phy_tsce_firmware_set_helper[unit] = _soc_greyhound_tsce_firmware_set; 6162 6163 if (soc_mspi_init(unit) != SOC_E_NONE) { 6164 LOG_WARN(BSL_LS_SOC_COMMON, 6165 (BSL_META_U(unit, 6166 "unit %d : MSPI Init Failed\n"), unit)); 6167 } 6168 6169 /* I2C set to Master Mode through Override Strap */ 6170 /* coverity[result_independent_of_operands] */ 6171 SOC_IF_ERROR_RETURN(READ_CMIC_OVERRIDE_STRAPr(unit, &rval)); 6172 soc_reg_field_set(unit, CMIC_OVERRIDE_STRAPr, &rval, ENABLE_OVERRIDE_I2C_MASTER_SLAVE_MODEf, 1); 6173 soc_reg_field_set(unit, CMIC_OVERRIDE_STRAPr, &rval, I2C_MASTER_SLAVE_MODEf, 1); 6174 /* coverity[result_independent_of_operands] */ 6175 SOC_IF_ERROR_RETURN(WRITE_CMIC_OVERRIDE_STRAPr(unit, rval)); 6176 6177 if (!SOC_WARM_BOOT(unit)) { 6178 SOC_IF_ERROR_RETURN(_greyhound_ledup_init(unit)); 6179 } 6180 6181 /* Add board properity which can be used in rc.soc */ 6182 board_name = soc_property_get_str(unit, spn_BOARD_NAME); 6183 if (board_name && 6184 ((sal_strcmp(board_name, "BCM953411K") == 0) || 6185 (sal_strcmp(board_name, "BCM953411R") == 0))) { 6186 if (soc_mem_config_set) { 6187 soc_mem_config_set("bcm953411", "1"); 6188 } else { 6189 LOG_WARN(BSL_LS_SOC_COMMON, 6190 (BSL_META_U(unit, 6191 "unit %d : soc_mem_config_set() is NULL\n"), unit)); 6192 } 6193 } 6194 6195 #ifdef INCLUDE_MEM_SCAN 6196 if (parity_enable) { 6197 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_start(unit)); 6198 } 6199 #endif /* INCLUDE_MEM_SCAN */ 6200 6201 return SOC_E_NONE; 6202 } 6203 6204 6205 6206 /* soc_greyhound_mem_config: 6207 * Over-ride the default table sizes (from regsfile) for any SKUs here 6208 */ 6209 int 6210 soc_greyhound_mem_config(int unit, int dev_id) 6211 { 6212 int rv = SOC_E_NONE; 6213 soc_persist_t *sop = SOC_PERSIST(unit); 6214 6215 switch (dev_id) { 6216 case BCM53400_DEVICE_ID: 6217 case BCM53401_DEVICE_ID: 6218 case BCM53402_DEVICE_ID: 6219 case BCM53403_DEVICE_ID: 6220 case BCM53404_DEVICE_ID: 6221 case BCM53405_DEVICE_ID: 6222 case BCM53406_DEVICE_ID: 6223 case BCM53408_DEVICE_ID: 6224 case BCM53454_DEVICE_ID: 6225 case BCM53456_DEVICE_ID: 6226 case BCM53369_DEVICE_ID: 6227 sop->memState[L2MCm].index_max = 511; 6228 sop->memState[L3_IPMCm].index_max = 63; 6229 sop->memState[L3_DEFIPm].index_max = 63; 6230 sop->memState[L3_DEFIP_ONLYm].index_max = 63; 6231 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 63; 6232 sop->memState[ING_L3_NEXT_HOPm].index_max = 767; 6233 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 767; 6234 sop->memState[EGR_L3_NEXT_HOPm].index_max = 767; 6235 sop->memState[EGR_L3_INTFm].index_max = 255; 6236 sop->memState[EFP_COUNTER_TABLEm].index_max = -1; 6237 sop->memState[EFP_METER_TABLEm].index_max = -1; 6238 sop->memState[EFP_POLICY_TABLEm].index_max = -1; 6239 sop->memState[EFP_TCAMm].index_max = -1; 6240 sop->memState[VFP_POLICY_TABLEm].index_max = -1; 6241 sop->memState[VFP_TCAMm].index_max = -1; 6242 sop->memState[L3_ECMP_COUNTm].index_max = -1; 6243 sop->memState[L3_ECMPm].index_max = -1; 6244 sop->memState[INITIAL_L3_ECMP_GROUPm].index_max = -1; 6245 sop->memState[INITIAL_L3_ECMPm].index_max = -1; 6246 SOC_CONTROL(unit)->l3_defip_max_tcams = 1; 6247 SOC_CONTROL(unit)->l3_defip_tcam_size = 64; 6248 break; 6249 case BCM53422_DEVICE_ID: 6250 case BCM53424_DEVICE_ID: 6251 case BCM53426_DEVICE_ID: 6252 sop->memState[L2MCm].index_max = 511; 6253 sop->memState[L3_IPMCm].index_max = -1; 6254 sop->memState[L3_DEFIPm].index_max = -1; 6255 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 6256 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1; 6257 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1; 6258 sop->memState[ING_L3_NEXT_HOPm].index_max = -1; 6259 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = -1; 6260 sop->memState[EGR_L3_NEXT_HOPm].index_max = -1; 6261 sop->memState[EGR_L3_INTFm].index_max = -1; 6262 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = -1; 6263 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = -1; 6264 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = -1; 6265 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = -1; 6266 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = -1; 6267 sop->memState[L3_ENTRY_ONLYm].index_max = -1; 6268 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = -1; 6269 sop->memState[L3_MTU_VALUESm].index_max = -1; 6270 sop->memState[EFP_COUNTER_TABLEm].index_max = -1; 6271 sop->memState[EFP_METER_TABLEm].index_max = -1; 6272 sop->memState[EFP_POLICY_TABLEm].index_max = -1; 6273 sop->memState[EFP_TCAMm].index_max = -1; 6274 sop->memState[VFP_POLICY_TABLEm].index_max = -1; 6275 sop->memState[VFP_TCAMm].index_max = -1; 6276 sop->memState[L3_ECMP_COUNTm].index_max = -1; 6277 sop->memState[L3_ECMPm].index_max = -1; 6278 sop->memState[INITIAL_L3_ECMP_GROUPm].index_max = -1; 6279 sop->memState[INITIAL_L3_ECMPm].index_max = -1; 6280 sop->memState[FP_TCAMm].index_max = 1023; 6281 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 1023; 6282 sop->memState[FP_COUNTER_TABLEm].index_max = 1023; 6283 sop->memState[FP_METER_TABLEm].index_max = 1023; 6284 sop->memState[FP_POLICY_TABLEm].index_max = 1023; 6285 sop->memState[MMU_CBPCELLHEADERm].index_max = 8191; 6286 sop->memState[MMU_CBPDATA0m].index_max = 8191; 6287 sop->memState[MMU_CBPDATA1m].index_max = 8191; 6288 sop->memState[MMU_CBPDATA2m].index_max = 8191; 6289 sop->memState[MMU_CBPDATA3m].index_max = 8191; 6290 sop->memState[MMU_CBPDATA4m].index_max = 8191; 6291 sop->memState[MMU_CBPDATA5m].index_max = 8191; 6292 sop->memState[MMU_CBPDATA6m].index_max = 8191; 6293 sop->memState[MMU_CBPDATA7m].index_max = 8191; 6294 sop->memState[MMU_CBPPKTHEADER0m].index_max = 8191; 6295 sop->memState[MMU_CBPPKTHEADER1m].index_max = 8191; 6296 sop->memState[MMU_CBPPKTHEADER2m].index_max = 8191; 6297 sop->memState[MMU_CBPPKTHEADER_EXTm].index_max = 8191; 6298 SOC_CONTROL(unit)->l3_defip_max_tcams = 1; 6299 SOC_CONTROL(unit)->l3_defip_tcam_size = 64; 6300 break; 6301 case BCM53365_DEVICE_ID: 6302 sop->memState[L2MCm].index_max = 511; 6303 /* no L3, VFP, EFP */ 6304 sop->memState[L3_IPMCm].index_max = -1; 6305 sop->memState[L3_DEFIPm].index_max = -1; 6306 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 6307 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1; 6308 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1; 6309 sop->memState[ING_L3_NEXT_HOPm].index_max = -1; 6310 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = -1; 6311 sop->memState[EGR_L3_NEXT_HOPm].index_max = -1; 6312 sop->memState[EGR_L3_INTFm].index_max = -1; 6313 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = -1; 6314 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = -1; 6315 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = -1; 6316 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = -1; 6317 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = -1; 6318 sop->memState[L3_ENTRY_ONLYm].index_max = -1; 6319 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = -1; 6320 sop->memState[L3_MTU_VALUESm].index_max = -1; 6321 sop->memState[L3_ECMP_COUNTm].index_max = -1; 6322 sop->memState[L3_ECMPm].index_max = -1; 6323 sop->memState[INITIAL_L3_ECMP_GROUPm].index_max = -1; 6324 sop->memState[INITIAL_L3_ECMPm].index_max = -1; 6325 sop->memState[EFP_COUNTER_TABLEm].index_max = -1; 6326 sop->memState[EFP_METER_TABLEm].index_max = -1; 6327 sop->memState[EFP_POLICY_TABLEm].index_max = -1; 6328 sop->memState[EFP_TCAMm].index_max = -1; 6329 sop->memState[VFP_POLICY_TABLEm].index_max = -1; 6330 sop->memState[VFP_TCAMm].index_max = -1; 6331 break; 6332 default: 6333 sop->memState[ING_L3_NEXT_HOPm].index_max = 1535; 6334 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 1535; 6335 sop->memState[EGR_L3_NEXT_HOPm].index_max = 1535; 6336 SOC_CONTROL(unit)->l3_defip_max_tcams = 8; 6337 SOC_CONTROL(unit)->l3_defip_tcam_size = 64; 6338 break; 6339 } 6340 if (SAL_BOOT_QUICKTURN) { 6341 /* QuickTurn with limited TCAM entries */ 6342 sop->memState[L2_USER_ENTRYm].index_max = 15; 6343 sop->memState[L2_USER_ENTRY_ONLYm].index_max = 15; 6344 sop->memState[CPU_COS_MAPm].index_max = 15; 6345 sop->memState[CPU_COS_MAP_ONLYm].index_max = 15; 6346 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 15; 6347 sop->memState[VLAN_SUBNETm].index_max = 15; 6348 sop->memState[VLAN_SUBNET_ONLYm].index_max = 15; 6349 sop->memState[VLAN_SUBNET_ONLYm].index_max = 15; 6350 sop->memState[L3_DEFIPm].index_max = 15; 6351 sop->memState[L3_DEFIP_ONLYm].index_max = 15; 6352 sop->memState[VFP_TCAMm].index_max = 15; 6353 sop->memState[EFP_TCAMm].index_max = 15; 6354 sop->memState[FP_TCAMm].index_max = 15; 6355 } 6356 return rv; 6357 } 6358 6359 /* 6360 * Function: 6361 * _soc_greyhound_gpio_set 6362 * Purpose: 6363 * Write value to the specified GPIO pin 6364 */ 6365 STATIC int 6366 _soc_greyhound_gpio_set(int unit, int pin, int val) 6367 { 6368 uint32 rval = 0; 6369 uint32 fval = 0; 6370 uint8 mask = 0xFF; 6371 6372 mask &= ~(1 << pin); 6373 6374 /* coverity[result_independent_of_operands] */ 6375 SOC_IF_ERROR_RETURN(READ_CMIC_GP_OUT_ENr(unit, &rval)); 6376 fval = soc_reg_field_get(unit, CMIC_GP_OUT_ENr, rval, OUT_ENABLEf); 6377 fval |= 1 << pin; 6378 soc_reg_field_set(unit, CMIC_GP_OUT_ENr, &rval, OUT_ENABLEf, fval); 6379 /* coverity[result_independent_of_operands] */ 6380 SOC_IF_ERROR_RETURN(WRITE_CMIC_GP_OUT_ENr(unit, rval)); 6381 6382 /* coverity[result_independent_of_operands] */ 6383 SOC_IF_ERROR_RETURN(READ_CMIC_GP_DATA_OUTr(unit, &rval)); 6384 fval = soc_reg_field_get(unit, CMIC_GP_DATA_OUTr, rval, DATA_OUTf); 6385 fval &= mask; 6386 fval |= (val << pin); 6387 6388 soc_reg_field_set(unit, CMIC_GP_DATA_OUTr, &rval, DATA_OUTf, fval); 6389 /* coverity[result_independent_of_operands] */ 6390 SOC_IF_ERROR_RETURN(WRITE_CMIC_GP_DATA_OUTr(unit, rval)); 6391 6392 return SOC_E_NONE; 6393 } 6394 6395 #define TOP_STRAP_STATUS_TSC_FIELD(val) \ 6396 (((val) >> 26) & 0x3F) 6397 #define TOP_STRAP_STATUS_LCPLL1_REFCLK_SEL(val) \ 6398 (((val) >> 9) & 0x1) 6399 6400 /* 6401 * Function: 6402 * _soc_greyhound_tsc_core_enable 6403 * Purpose: 6404 * Enable the TSC core and reconfig the port info 6405 */ 6406 STATIC int 6407 _soc_greyhound_tsc_core_enable(int unit, uint32 disabled_tsc_bmp) 6408 { 6409 int i, j, idx; 6410 int phy_port, port, blk, qsgmii_mode, num_port; 6411 uint32 disable_4x10,disable_4x10q, rval; 6412 soc_info_t *si; 6413 6414 si = &SOC_INFO(unit); 6415 disable_4x10 = 0; 6416 disable_4x10q = 0; 6417 qsgmii_mode = 0; 6418 (void)_soc_greyhound_qsgmii_mode_check(unit, &qsgmii_mode); 6419 num_port = _GH_PORTS_NUM_PER_TSC; 6420 for (i = 0; i < _GH_MAX_TSC_COUNT; i++) { 6421 if((1 << i) & disabled_tsc_bmp){ 6422 if (i == 5){ 6423 disable_4x10q = 1; 6424 if (qsgmii_mode == 1) { 6425 num_port = _GH_PORTS_NUM_PER_TSCQ; 6426 } 6427 } else { 6428 disable_4x10 |= (1 << i); 6429 } 6430 for (j = 0; j < num_port; j++) { 6431 phy_port = tsc_phy_port[i]+j; 6432 port = si->port_p2l_mapping[phy_port]; 6433 for (idx = 0; idx < SOC_DRIVER(unit)->port_num_blktype; 6434 idx++) { 6435 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, idx); 6436 if (blk < 0) { /* end of block list of each port */ 6437 break; 6438 } 6439 if(si->block_port[blk] == port){ 6440 si->block_port[blk] = -1; 6441 } 6442 si->block_valid[blk]=0; 6443 SOC_PBMP_PORT_REMOVE(si->block_bitmap[blk],port); 6444 } 6445 si->port_p2l_mapping[phy_port]= -1; 6446 si->port_p2m_mapping[phy_port] = -1; 6447 si->max_port_p2m_mapping[phy_port] = -1; 6448 si->port_l2p_mapping[port] = -1; 6449 si->port_m2p_mapping[port] = -1; 6450 6451 SOC_PBMP_PORT_REMOVE(si->ether.bitmap,port); 6452 SOC_PBMP_PORT_REMOVE(si->ge.bitmap,port); 6453 SOC_PBMP_PORT_REMOVE(si->xe.bitmap,port); 6454 SOC_PBMP_PORT_REMOVE(si->hg.bitmap,port); 6455 SOC_PBMP_PORT_REMOVE(si->st.bitmap,port); 6456 SOC_PBMP_PORT_REMOVE(si->gx.bitmap,port); 6457 SOC_PBMP_PORT_REMOVE(si->xl.bitmap,port); 6458 SOC_PBMP_PORT_REMOVE(si->all.bitmap,port); 6459 SOC_PBMP_PORT_REMOVE(si->port.bitmap,port); 6460 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 6461 "?%d", port); 6462 si->port_offset[port] = port; 6463 } 6464 } 6465 } 6466 6467 #define RECONFIGURE_PORT_CONFIG_INFO(ptype,str) \ 6468 si->ptype.num = 0; \ 6469 si->ptype.min = si->ptype.max = -1; \ 6470 PBMP_ITER(si->ptype.bitmap, port) { \ 6471 if(sal_strcmp(str,"")){\ 6472 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]),\ 6473 "%s%d", str, si->ptype.num);\ 6474 }\ 6475 si->ptype.port[si->ptype.num++] = port; \ 6476 if (si->ptype.min < 0) { \ 6477 si->ptype.min = port; \ 6478 } \ 6479 if (port > si->ptype.max) { \ 6480 si->ptype.max = port; \ 6481 } \ 6482 } 6483 6484 /* coverity[pointless_string_compare] */ 6485 RECONFIGURE_PORT_CONFIG_INFO(ether,""); 6486 /* coverity[pointless_string_compare] */ 6487 RECONFIGURE_PORT_CONFIG_INFO(st,""); 6488 RECONFIGURE_PORT_CONFIG_INFO(hg,"hg"); 6489 RECONFIGURE_PORT_CONFIG_INFO(xe,"xe"); 6490 RECONFIGURE_PORT_CONFIG_INFO(ge,"ge"); 6491 #undef RECONFIGURE_PORT_CONFIG_INFO 6492 if (!SOC_WARM_BOOT(unit)) { 6493 SOC_IF_ERROR_RETURN(READ_PGW_CTRL_0r(unit, &rval)); 6494 soc_reg_field_set(unit, PGW_CTRL_0r, &rval, SW_PM4X10_DISABLEf, disable_4x10); 6495 soc_reg_field_set(unit, PGW_CTRL_0r, &rval, SW_PM4X10Q_DISABLEf, disable_4x10q); 6496 SOC_IF_ERROR_RETURN(WRITE_PGW_CTRL_0r(unit, rval)); 6497 } 6498 SOC_IF_ERROR_RETURN(soc_dport_map_update(unit)); 6499 return SOC_E_NONE; 6500 } 6501 6502 #ifdef BCM_WARM_BOOT_SUPPORT 6503 /* 6504 * Function: 6505 * soc_greyhound_chip_warmboot_reset 6506 * Purpose: 6507 * Special re-init sequencing for BCM53400 during warmboot 6508 */ 6509 int 6510 soc_greyhound_chip_warmboot_reset(int unit) 6511 { 6512 uint32 strap_sts; 6513 _gh_sku_info_t *matched_sku_info; 6514 uint32 disabled_tsc_bmp; 6515 6516 /* The pbmp need to remap according to strap pin */ 6517 if (matched_devid_idx == -1) { 6518 LOG_WARN(BSL_LS_SOC_COMMON, 6519 (BSL_META_U(unit, 6520 "Warning: soc_greyhound_port_config_init should " 6521 "be invoked first! Choose bcm534x1 port config.\n"))); 6522 matched_devid_idx = 0; 6523 } 6524 6525 matched_sku_info = &_gh_sku_port_config[matched_devid_idx]; 6526 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUSr(unit, &strap_sts)); 6527 6528 disabled_tsc_bmp = (TOP_STRAP_STATUS_TSC_FIELD(strap_sts)) | 6529 matched_sku_info->disabled_tsc_bmp; 6530 6531 _soc_greyhound_tsc_core_enable(unit, disabled_tsc_bmp); 6532 6533 return SOC_E_NONE; 6534 } 6535 #endif /* BCM_WARM_BOOT_SUPPORT */ 6536 6537 STATIC int _soc_greyhound_disable_usb(int unit) 6538 { 6539 uint16 dev_id; 6540 uint8 rev_id; 6541 uint32 rval; 6542 6543 soc_cm_get_id(unit, &dev_id, &rev_id); 6544 /* Lite sku (sku w/o A9) */ 6545 if (((dev_id & 0x00F0) == 0x0000) || ((dev_id & 0x0061) == 0x0040) || 6546 ((dev_id & 0x0060) == 0x0020) || (dev_id == BCM53365_DEVICE_ID)) { 6547 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_USBPHY_CTRL_2r(unit, &rval)); 6548 soc_reg_field_set(unit, IPROC_WRAP_USBPHY_CTRL_2r, 6549 &rval, PHY_ISOf, 1); 6550 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_USBPHY_CTRL_2r(unit, rval)); 6551 SOC_IF_ERROR_RETURN(READ_USBH_UTMI_P0CTLr(unit, &rval)); 6552 soc_reg_field_set(unit, USBH_UTMI_P0CTLr, &rval, DFE_POWERUP_FSMf, 0); 6553 SOC_IF_ERROR_RETURN(WRITE_USBH_UTMI_P0CTLr(unit, rval)); 6554 } 6555 return SOC_E_NONE; 6556 } 6557 6558 void 6559 soc_greyhound_sbus_ring_map_config(int unit) 6560 { 6561 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x11112200); /* block 7 - 0 */ 6562 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x00430001); /* block 15 - 8 */ 6563 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00005064); /* block 23 - 16 */ 6564 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00000000); /* block 31 - 24 */ 6565 WRITE_CMIC_SBUS_RING_MAP_32_39r(unit, 0x00002222); /* block 39 - 32 */ 6566 6567 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0); 6568 6569 return; 6570 } 6571 6572 /* 6573 * Function: 6574 * soc_greyhound_chip_reset 6575 * Purpose: 6576 * Special reset sequencing for BCM53400 6577 */ 6578 6579 int 6580 soc_greyhound_chip_reset(int unit) 6581 { 6582 uint32 rval, to_usec, strap_sts; 6583 _gh_sku_info_t *matched_sku_info; 6584 uint32 disabled_tsc_bmp; 6585 int i, change_core_clk = 0; 6586 soc_info_t *si; 6587 char *board_name; 6588 6589 uint32 strap_status_1; 6590 6591 unsigned ts_ref_freq; 6592 unsigned ts_idx; 6593 static const soc_pll_param_t ts_pll[] = { /* values for 500MHz TSPLL output */ 6594 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_DIV2 */ 6595 {25000000, 100, 0, 1, 5, 2, 2, 3, 1}, 6596 {50000000, 50, 0, 1, 5, 2, 2, 3, 1}, 6597 { 0, 100, 0, 1, 5, 2, 2, 3, 1} /* 25MHz, from internal reference */ 6598 }; 6599 unsigned bs_ref_freq; 6600 unsigned bs_idx; 6601 uint32 bs0_ndiv_high, bs0_ndiv_low; 6602 uint32 bs1_ndiv_high, bs1_ndiv_low; 6603 6604 /* For performance reasons, use different settings for BSPLL0 and BSPLL1 */ 6605 static const soc_pll_param_t bs0_pll[] = { /* values for 20MHz BSPLL output */ 6606 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_FB_DIV2 */ 6607 {25000000, 64, 0, 1, 160, 4, 1, 8, 1}, 6608 {50000000, 128, 0, 1, 160, 4, 1, 8, 1}, 6609 { 0, 64, 0, 1, 160, 4, 1, 8, 1} /* 25MHz, from internal reference */ 6610 }; 6611 static const soc_pll_param_t bs1_pll[] = { /* values for 20MHz BSPLL output */ 6612 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_FB_DIV2 */ 6613 {25000000, 62, 0, 1, 155, 4, 1, 8, 1}, 6614 {50000000, 124, 0, 1, 155, 4, 1, 8, 1}, 6615 { 0, 62, 0, 1, 155, 4, 1, 8, 1} /* 25MHz, from internal reference */ 6616 }; 6617 6618 /* Parameters for BSPLL particular to GH. Same indexing as above */ 6619 static const unsigned bs_cp1[] = {1, 0, 1}; 6620 static const unsigned bs_cp[] = {3, 0, 3}; 6621 static const unsigned bs_cz[] = {3, 3, 3}; 6622 static const unsigned bs_rp[] = {7, 0, 7}; 6623 static const unsigned bs_rz[] = {7, 8, 7}; 6624 static const unsigned bs_icp[] = {16, 32, 16}; 6625 6626 si = &SOC_INFO(unit); 6627 6628 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 6629 (10 * MILLISECOND_USEC); 6630 6631 soc_greyhound_sbus_ring_map_config(unit); 6632 sal_usleep(to_usec); 6633 6634 6635 /* PCIe Serdes workaround */ 6636 READ_RESCAL_STATUS_0r(unit, &rval); 6637 if (soc_reg_field_get(unit, RESCAL_STATUS_0r, rval, RESCAL_DONEf)) { 6638 SOC_IF_ERROR_RETURN( 6639 WRITE_CHIPCOMMONG_MII_MANAGEMENT_CONTROLr(unit, 0x88)); 6640 SOC_IF_ERROR_RETURN( 6641 WRITE_CHIPCOMMONG_MII_MANAGEMENT_COMMAND_DATAr(unit, 0x517e1000)); 6642 SOC_IF_ERROR_RETURN( 6643 WRITE_CHIPCOMMONG_MII_MANAGEMENT_COMMAND_DATAr(unit, (0x5106c030 | 6644 soc_reg_field_get(unit, RESCAL_STATUS_0r, rval, RESCAL_PONf)))); 6645 sal_usleep(to_usec); 6646 SOC_IF_ERROR_RETURN ( 6647 WRITE_CHIPCOMMONG_MII_MANAGEMENT_CONTROLr(unit, 0)); 6648 } 6649 /* Power down USB PHY in Lite sku */ 6650 _soc_greyhound_disable_usb(unit); 6651 6652 /* AVS PVTMON settings fixed in temperature mode*/ 6653 SOC_IF_ERROR_RETURN ( 6654 WRITE_AVS_REG_HW_MNTR_SEQUENCER_MASK_PVT_MNTRr(unit, 0x7e)); 6655 SOC_IF_ERROR_RETURN ( 6656 soc_reg_field32_modify(unit, TOP_PVTMON_CTRL_0r, 6657 REG_PORT_ANY, BG_ADJf, 0x1)); 6658 6659 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUSr(unit, &strap_sts)); 6660 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUS_1r(unit, &strap_status_1)); 6661 6662 SOC_IF_ERROR_RETURN( 6663 soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, REG_PORT_ANY, 6664 TOP_LCPLL_SOFT_RESETf, 1)); 6665 6666 if (TOP_STRAP_STATUS_LCPLL1_REFCLK_SEL(strap_sts) == 0){ 6667 /* strap_sts = 0: from LCPLL1 differential pad */ 6668 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6669 TOP_XG_PLL1_CTRL_1r, REG_PORT_ANY, PDIVf, 3)); 6670 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6671 TOP_XG1_LCPLL_FBDIV_CTRL_0r, REG_PORT_ANY, XG1_LCPLL_FBDIV_0f, 0)); 6672 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6673 TOP_XG1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, XG1_LCPLL_FBDIV_1f, 0xf00)); 6674 6675 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL1_CTRL_5r(unit,&rval)); 6676 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, CP1f, 1); 6677 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, CPf, 1); 6678 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, CZf, 3); 6679 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, RPf, 0); 6680 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, RZf, 8); 6681 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, ICPf, 32); 6682 WRITE_TOP_XG_PLL1_CTRL_5r(unit, rval); 6683 6684 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6685 TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, 0xcbd4)); 6686 6687 } else { 6688 /* strap_lcpll1_refclk_sel == 1 */ 6689 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6690 TOP_XG_PLL1_CTRL_1r, REG_PORT_ANY, PDIVf, 1)); 6691 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6692 TOP_XG1_LCPLL_FBDIV_CTRL_0r, REG_PORT_ANY, XG1_LCPLL_FBDIV_0f, 0)); 6693 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6694 TOP_XG1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, XG1_LCPLL_FBDIV_1f, 0xfa0)); 6695 6696 if (strap_status_1 & 1) { 6697 /* 50MHz ref */ 6698 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6699 TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, FREQ_DOUBLER_ONf, 0)); 6700 } else { 6701 /* 25MHz ref */ 6702 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6703 TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, FREQ_DOUBLER_ONf, 1)); 6704 } 6705 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6706 TOP_XG_PLL1_CTRL_0r, REG_PORT_ANY, CH0_MDIVf, 0x14)); 6707 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6708 TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, 0x0192)); 6709 6710 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL1_CTRL_5r(unit,&rval)); 6711 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, CP1f, 1); 6712 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, CPf, 3); 6713 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, CZf, 3); 6714 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, RPf, 7); 6715 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, RZf, 7); 6716 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_5r, &rval, ICPf, 16); 6717 WRITE_TOP_XG_PLL1_CTRL_5r(unit, rval); 6718 } 6719 6720 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6721 TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, VCO_GAINf, 0x3)); 6722 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6723 TOP_XG_PLL1_CTRL_3r, REG_PORT_ANY, VCO_CURf, 0)); 6724 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6725 TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, VCO_CONT_ADJf, 0x1)); 6726 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6727 TOP_MISC_CONTROL_1r, REG_PORT_ANY, CMIC_TO_XG_PLL1_SW_OVWRf, 1)); 6728 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6729 TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, CPPf, 0x80)); 6730 6731 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, REG_PORT_ANY, TOP_LCPLL_SOFT_RESETf, 0)); 6732 sal_usleep(to_usec); 6733 6734 soc_greyhound_freq_get(unit, &si->frequency, &change_core_clk); 6735 6736 if(change_core_clk != 0){ 6737 /* set 53403/53404 core clock to 176MHz */ 6738 if (si->frequency == 176) { 6739 rval = 0x11; 6740 } else { 6741 rval = 0xa; 6742 } 6743 SOC_IF_ERROR_RETURN 6744 (soc_reg_field32_modify(unit, TOP_CORE_PLL_CTRL4r, 6745 REG_PORT_ANY, MSTR_CH0_MDIVf, rval)); 6746 6747 SOC_IF_ERROR_RETURN 6748 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 6749 CMIC_TO_CORE_PLL_LOADf, 1)); 6750 } 6751 6752 SOC_IF_ERROR_RETURN 6753 (soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 6754 REG_PORT_ANY, TOP_LCPLL_SOFT_RESETf, 0x1)); 6755 6756 if (strap_status_1 & 1) { 6757 /* 50 MHz clock source. */ 6758 SOC_IF_ERROR_RETURN 6759 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, 6760 REG_PORT_ANY, FREQ_DOUBLER_ONf, 0x0)); 6761 6762 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL0_CTRL_5r(unit,&rval)); 6763 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, CP1f, 1); 6764 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, CPf, 3); 6765 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, CZf, 3); 6766 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, RPf, 7); 6767 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, RZf, 7); 6768 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, ICPf, 16); 6769 WRITE_TOP_XG_PLL0_CTRL_5r(unit, rval); 6770 } else { 6771 /* 25 MHz clock source */ 6772 SOC_IF_ERROR_RETURN 6773 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, 6774 REG_PORT_ANY, FREQ_DOUBLER_ONf, 0x1)); 6775 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL0_CTRL_5r(unit,&rval)); 6776 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, CP1f, 1); 6777 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, CPf, 1); 6778 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, CZf, 3); 6779 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, RPf, 0); 6780 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, RZf, 8); 6781 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_5r, &rval, ICPf, 32); 6782 WRITE_TOP_XG_PLL0_CTRL_5r(unit, rval); 6783 } 6784 6785 SOC_IF_ERROR_RETURN 6786 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_1r, 6787 REG_PORT_ANY, PDIVf, 0x1)); 6788 6789 SOC_IF_ERROR_RETURN 6790 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_0r, 6791 REG_PORT_ANY, CH0_MDIVf, 0x18)); 6792 6793 SOC_IF_ERROR_RETURN 6794 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, 6795 REG_PORT_ANY, MSC_CTRLf, 0x0012)); 6796 6797 SOC_IF_ERROR_RETURN 6798 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, 6799 REG_PORT_ANY, VCO_CONT_ADJf, 0x1)); 6800 6801 SOC_IF_ERROR_RETURN 6802 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_3r, 6803 REG_PORT_ANY, VCO_CURf, 0x0)); 6804 6805 SOC_IF_ERROR_RETURN 6806 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, 6807 REG_PORT_ANY, VCO_GAINf, 0x3)); 6808 6809 SOC_IF_ERROR_RETURN 6810 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, 6811 REG_PORT_ANY, CMIC_TO_XG_PLL0_SW_OVWRf, 0x1)); 6812 6813 SOC_IF_ERROR_RETURN 6814 (soc_reg_field32_modify(unit, TOP_XG0_LCPLL_FBDIV_CTRL_0r, 6815 REG_PORT_ANY, XG0_LCPLL_FBDIV_0f, 0x0)); 6816 6817 SOC_IF_ERROR_RETURN 6818 (soc_reg_field32_modify(unit, TOP_XG0_LCPLL_FBDIV_CTRL_1r, 6819 REG_PORT_ANY, XG0_LCPLL_FBDIV_1f, 0xf00)); 6820 6821 SOC_IF_ERROR_RETURN 6822 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, 6823 REG_PORT_ANY, CPPf, 0x80)); 6824 6825 SOC_IF_ERROR_RETURN 6826 (soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 6827 REG_PORT_ANY, TOP_LCPLL_SOFT_RESETf, 0x0)); 6828 sal_usleep(to_usec); 6829 6830 /* BCM953411 needs enable LCPLL0 for external PHY */ 6831 board_name = soc_property_get_str(unit, spn_BOARD_NAME); 6832 if (board_name && 6833 ((sal_strcmp(board_name, "BCM953411K") == 0) || 6834 (sal_strcmp(board_name, "BCM953411R") == 0))) { 6835 SOC_IF_ERROR_RETURN(_soc_greyhound_gpio_set(unit, 3, 0)); 6836 SOC_IF_ERROR_RETURN 6837 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, 6838 REG_PORT_ANY, MSC_CTRLf, 0x1012)); 6839 SOC_IF_ERROR_RETURN(_soc_greyhound_gpio_set(unit, 3, 1)); 6840 } 6841 6842 /* TSPLL configuration: 500MHz TS_CLK from 20/25/32/50MHz refclk */ 6843 /* CMICd divides by 2 on input, so this is a 250MHz clock to TS logic */ 6844 6845 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); /* 0->internal reference */ 6846 6847 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 6848 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 6849 break; 6850 } 6851 } 6852 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 6853 LOG_ERROR(BSL_LS_SOC_COMMON, 6854 (BSL_META_U(unit, 6855 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params.\n"), ts_ref_freq)); 6856 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, NDIV_FRAC, MDIV, PDIV, and if 6857 all exist, use them. For now, just fail. 6858 */ 6859 } else { 6860 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_0r(unit,&rval)); 6861 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_0r, &rval, VCO_DIV2f, 6862 soc_property_get(unit, spn_PTP_TS_VCO_DIV2, ts_pll[ts_idx].vco_div2)); 6863 WRITE_TOP_TS_PLL_CTRL_0r(unit, rval); 6864 6865 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_4r(unit,&rval)); 6866 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KAf, 6867 soc_property_get(unit, spn_PTP_TS_KA, ts_pll[ts_idx].ka)); 6868 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KIf, 6869 soc_property_get(unit, spn_PTP_TS_KI, ts_pll[ts_idx].ki)); 6870 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KPf, 6871 soc_property_get(unit, spn_PTP_TS_KP, ts_pll[ts_idx].kp)); 6872 WRITE_TOP_TS_PLL_CTRL_4r(unit, rval); 6873 6874 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_3r(unit,&rval)); 6875 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_INTf, 6876 soc_property_get(unit, spn_PTP_TS_PLL_N, ts_pll[ts_idx].ndiv_int)); 6877 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_FRACf, 6878 ts_pll[ts_idx].ndiv_frac); 6879 WRITE_TOP_TS_PLL_CTRL_3r(unit, rval); 6880 6881 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 6882 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, PDIVf, 6883 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 6884 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, CH0_MDIVf, 6885 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, ts_pll[ts_idx].mdiv)); 6886 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 6887 6888 /* Enable software overwrite of TimeSync PLL settings. */ 6889 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit, &rval)); 6890 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_TS_PLL_LOADf, 1); 6891 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 6892 } 6893 6894 /* 500Mhz TSPLL -> 250MHz ref at timestamper, implies 4ns resolution */ 6895 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 6896 6897 if (!soc_feature(unit, soc_feature_time_v3_no_bs)) { 6898 /* as a signal to upper-level code that the BroadSync is newly initialized 6899 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware */ 6900 /* coverity[result_independent_of_operands] */ 6901 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit, &rval)); 6902 soc_reg_field_set(unit, CMIC_BS0_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 6903 WRITE_CMIC_BS0_CONFIGr(unit, rval); 6904 6905 /* coverity[result_independent_of_operands] */ 6906 SOC_IF_ERROR_RETURN(READ_CMIC_BS1_CONFIGr(unit, &rval)); 6907 soc_reg_field_set(unit, CMIC_BS1_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 6908 WRITE_CMIC_BS1_CONFIGr(unit, rval); 6909 6910 /* BSPLL0 has not been configured, so reset/configure both BSPLL0 and BSPLL1 */ 6911 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 6912 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 0); 6913 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 0); 6914 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 0); 6915 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 0); 6916 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 6917 6918 /* Different BSPLL configurations, but with same Fref */ 6919 6920 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); /* 0->internal reference */ 6921 6922 for (bs_idx = 0; bs_idx < sizeof(bs0_pll)/sizeof(bs0_pll[0]); ++bs_idx) { 6923 if (bs0_pll[bs_idx].ref_freq == bs_ref_freq) { 6924 break; 6925 } 6926 } 6927 if (bs_idx == sizeof(bs0_pll)/sizeof(bs0_pll[0])) { 6928 LOG_ERROR(BSL_LS_SOC_COMMON, 6929 (BSL_META_U(unit, 6930 "Invalid value for PTP_BS_REF (%u). No default PLL params.\n"), bs_ref_freq)); 6931 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, 6932 NDIV_FRAC, MDIV, PDIV, and if all exist, use them. For now, just fail. 6933 */ 6934 } else { 6935 /* BSPLL0 */ 6936 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_3r(unit,&rval)); 6937 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_3r, &rval, VCO_FB_DIV2f, 6938 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, bs0_pll[bs_idx].vco_div2)); 6939 WRITE_TOP_BS_PLL0_CTRL_3r(unit, rval); 6940 6941 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_1r(unit,&rval)); 6942 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, KAf, 6943 soc_property_get(unit, spn_PTP_BS_KA, bs0_pll[bs_idx].ka)); 6944 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, KIf, 6945 soc_property_get(unit, spn_PTP_BS_KI, bs0_pll[bs_idx].ki)); 6946 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, KPf, 6947 soc_property_get(unit, spn_PTP_BS_KP, bs0_pll[bs_idx].kp)); 6948 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, PDIVf, 6949 soc_property_get(unit, spn_PTP_BS_PDIV, bs0_pll[bs_idx].pdiv)); 6950 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 6951 6952 bs0_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs0_pll[bs_idx].ndiv_int) << 6) | 6953 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs0_pll[bs_idx].ndiv_frac) >> 26) & 0x3f)); 6954 bs0_ndiv_low = ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs0_pll[bs_idx].ndiv_frac) << 6) & 0xffffc000); 6955 6956 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 6957 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC0_LCPLL_FBDIV_0f, bs0_ndiv_low); 6958 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit, rval); 6959 6960 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 6961 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC0_LCPLL_FBDIV_1f, bs0_ndiv_high); 6962 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit, rval); 6963 6964 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_0r(unit,&rval)); 6965 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_0r, &rval, CH0_MDIVf, 6966 soc_property_get(unit, spn_PTP_BS_MNDIV, bs0_pll[bs_idx].mdiv)); 6967 WRITE_TOP_BS_PLL0_CTRL_0r(unit, rval); 6968 6969 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6970 TOP_BS_PLL0_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, 0x12)); 6971 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6972 TOP_BS_PLL0_CTRL_7r, REG_PORT_ANY, VCO_CONT_ADJf, 1)); 6973 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6974 TOP_BS_PLL0_CTRL_3r, REG_PORT_ANY, VCO_CURf, 0)); 6975 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6976 TOP_BS_PLL0_CTRL_3r, REG_PORT_ANY, VCO_CURf, 0)); 6977 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6978 TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, VCO_GAINf, 0)); 6979 6980 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_5r(unit,&rval)); 6981 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, CP1f, bs_cp1[bs_idx]); 6982 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, CPf, bs_cp[bs_idx]); 6983 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, CZf, bs_cz[bs_idx]); 6984 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, RPf, bs_rp[bs_idx]); 6985 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, RZf, bs_rz[bs_idx]); 6986 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_5r, &rval, ICPf, bs_icp[bs_idx]); 6987 WRITE_TOP_BS_PLL0_CTRL_5r(unit, rval); 6988 6989 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 6990 TOP_BS_PLL0_CTRL_7r, REG_PORT_ANY, CPPf, 0x80)); 6991 6992 /* BSPLL1 */ 6993 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_3r(unit,&rval)); 6994 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_3r, &rval, VCO_FB_DIV2f, 6995 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, bs1_pll[bs_idx].vco_div2)); 6996 WRITE_TOP_BS_PLL1_CTRL_3r(unit, rval); 6997 6998 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_1r(unit,&rval)); 6999 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, KAf, 7000 soc_property_get(unit, spn_PTP_BS_KA, bs1_pll[bs_idx].ka)); 7001 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, KIf, 7002 soc_property_get(unit, spn_PTP_BS_KI, bs1_pll[bs_idx].ki)); 7003 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, KPf, 7004 soc_property_get(unit, spn_PTP_BS_KP, bs1_pll[bs_idx].kp)); 7005 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, PDIVf, 7006 soc_property_get(unit, spn_PTP_BS_PDIV, bs1_pll[bs_idx].pdiv)); 7007 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 7008 7009 bs1_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs1_pll[bs_idx].ndiv_int) << 6) | 7010 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs1_pll[bs_idx].ndiv_frac) >> 26) & 0x3f)); 7011 bs1_ndiv_low = ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs1_pll[bs_idx].ndiv_frac) << 6) & 0xffffc000); 7012 7013 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 7014 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC1_LCPLL_FBDIV_0f, bs1_ndiv_low); 7015 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit, rval); 7016 7017 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 7018 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC1_LCPLL_FBDIV_1f, bs1_ndiv_high); 7019 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit, rval); 7020 7021 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_0r(unit,&rval)); 7022 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_0r, &rval, CH0_MDIVf, 7023 soc_property_get(unit, spn_PTP_BS_MNDIV, bs1_pll[bs_idx].mdiv)); 7024 WRITE_TOP_BS_PLL1_CTRL_0r(unit, rval); 7025 7026 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7027 TOP_BS_PLL1_CTRL_6r, REG_PORT_ANY, MSC_CTRLf, 0x12)); 7028 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7029 TOP_BS_PLL1_CTRL_7r, REG_PORT_ANY, VCO_CONT_ADJf, 1)); 7030 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7031 TOP_BS_PLL1_CTRL_3r, REG_PORT_ANY, VCO_CURf, 0)); 7032 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7033 TOP_BS_PLL1_CTRL_3r, REG_PORT_ANY, VCO_CURf, 0)); 7034 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7035 TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, VCO_GAINf, 0)); 7036 7037 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_5r(unit,&rval)); 7038 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, CP1f, bs_cp1[bs_idx]); 7039 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, CPf, bs_cp[bs_idx]); 7040 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, CZf, bs_cz[bs_idx]); 7041 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, RPf, bs_rp[bs_idx]); 7042 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, RZf, bs_rz[bs_idx]); 7043 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_5r, &rval, ICPf, bs_icp[bs_idx]); 7044 WRITE_TOP_BS_PLL1_CTRL_5r(unit, rval); 7045 7046 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7047 TOP_BS_PLL1_CTRL_7r, REG_PORT_ANY, CPPf, 0x80)); 7048 7049 /* 7050 * Set frequency doubler based on reference clock. 7051 * Greyhound supports 25MHz/50MHz reference clocks. 7052 * LCPLL frequency doubler Boolean in PLL control 7053 * register 7 scales 25MHz so effective reference 7054 * frequency equals 50MHz. 7055 */ 7056 if (strap_status_1 & 1) { 7057 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_7r(unit, &rval)); 7058 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_7r, &rval, FREQ_DOUBLER_ONf, 0); 7059 WRITE_TOP_BS_PLL0_CTRL_7r(unit, rval); 7060 7061 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_7r(unit, &rval)); 7062 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_7r, &rval, FREQ_DOUBLER_ONf, 0); 7063 WRITE_TOP_BS_PLL1_CTRL_7r(unit, rval); 7064 } 7065 7066 /* Enable software overwrite of BroadSync 0/1 PLL settings. */ 7067 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit, &rval)); 7068 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL0_SW_OVWRf, 1); 7069 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL1_SW_OVWRf, 1); 7070 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 7071 7072 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_1r(unit,&rval)); 7073 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, LOAD_EN_CHf, 0); 7074 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 7075 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, LOAD_EN_CHf, 1); 7076 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 7077 7078 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_1r(unit,&rval)); 7079 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, LOAD_EN_CHf, 0); 7080 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 7081 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, LOAD_EN_CHf, 1); 7082 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 7083 } 7084 7085 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 7086 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 1); 7087 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 1); 7088 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 7089 7090 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 7091 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 1); 7092 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 1); 7093 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 7094 7095 /* 16mA driving stregth */ 7096 SOC_IF_ERROR_RETURN(READ_ICFG_IPROC_IOPAD_CTRL_21r(unit, &rval)); 7097 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_21r, &rval,IPROC_BS0_CLK_DRIVEf,0x7); 7098 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_21r, &rval,IPROC_BS0_HB_DRIVEf,0x7); 7099 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_21r, &rval,IPROC_BS0_TC_DRIVEf,0x7); 7100 WRITE_ICFG_IPROC_IOPAD_CTRL_21r(unit, rval); 7101 SOC_IF_ERROR_RETURN(READ_ICFG_IPROC_IOPAD_CTRL_20r(unit, &rval)); 7102 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_20r, &rval,IPROC_BS1_CLK_DRIVEf,0x7); 7103 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_20r, &rval,IPROC_BS1_HB_DRIVEf,0x7); 7104 soc_reg_field_set(unit, ICFG_IPROC_IOPAD_CTRL_20r, &rval,IPROC_BS1_TC_DRIVEf,0x7); 7105 WRITE_ICFG_IPROC_IOPAD_CTRL_20r(unit, rval); 7106 7107 } 7108 7109 /* 7110 * Bring port blocks out of reset 7111 */ 7112 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 7113 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP0_RST_Lf, 1); 7114 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP1_RST_Lf, 1); 7115 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP2_RST_Lf, 1); 7116 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP3_RST_Lf, 1); 7117 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP4_RST_Lf, 1); 7118 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GXP0_RST_Lf, 1); 7119 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 7120 sal_usleep(to_usec); 7121 7122 /* Bring network sync out of reset */ 7123 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 7124 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_TS_RST_Lf, 1); 7125 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 7126 sal_usleep(to_usec); 7127 7128 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 7129 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 7130 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 7131 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 1); 7132 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 7133 7134 /* Bring IP, EP, and MMU blocks out of reset */ 7135 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 7136 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 7137 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 7138 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 7139 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 7140 sal_usleep(to_usec); 7141 7142 /* speed limit settings for some SKUs option */ 7143 7144 /* TSCx should be disabled in some sku. */ 7145 /* pgw_ctrl_0 */ 7146 if (matched_devid_idx == -1) { 7147 LOG_WARN(BSL_LS_SOC_COMMON, 7148 (BSL_META_U(unit, 7149 "Warning: soc_greyhound_port_config_init should " 7150 "be invoked first! Choose bcm534x1 port config.\n"))); 7151 matched_devid_idx = 0; 7152 } 7153 7154 matched_sku_info = &_gh_sku_port_config[matched_devid_idx]; 7155 disabled_tsc_bmp = (TOP_STRAP_STATUS_TSC_FIELD(strap_sts)) | 7156 matched_sku_info->disabled_tsc_bmp; 7157 7158 _soc_greyhound_tsc_core_enable(unit, disabled_tsc_bmp); 7159 7160 for (i = 0; _gh_sku_speed_limit[i].dev_id; i++){ 7161 int j; 7162 if ((matched_sku_info->dev_id == _gh_sku_speed_limit[i].dev_id) && 7163 (matched_sku_info->config_op == _gh_sku_speed_limit[i].config_op)){ 7164 for (j = 0; j < _GH_MAX_LPORT_COUNT; j++ ){ 7165 soc_reg32_set(unit, speed_limit_regs[j], 0, 0, 7166 _gh_sku_speed_limit[i].phy_port_mapping[j]); 7167 } 7168 break; 7169 } 7170 } 7171 return SOC_E_NONE; 7172 } 7173 7174 7175 int 7176 soc_greyhound_tsc_reset(int unit) 7177 { 7178 int blk, port; 7179 uint32 rval; 7180 7181 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 7182 port = SOC_BLOCK_PORT(unit, blk); 7183 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, port, 0)); 7184 } 7185 7186 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 7187 port = SOC_BLOCK_PORT(unit, blk); 7188 if (port == -1 || port == REG_PORT_ANY) { 7189 continue; 7190 } 7191 SOC_IF_ERROR_RETURN(READ_XLPORT_MAC_CONTROLr(unit, port, &rval)); 7192 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 1); 7193 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 7194 sal_udelay(10); 7195 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 0); 7196 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 7197 } 7198 return SOC_E_NONE; 7199 } 7200 7201 7202 STATIC int 7203 _soc_greyhound_age_timer_get(int unit, int *age_seconds, int *enabled) 7204 { 7205 uint32 value; 7206 7207 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &value)); 7208 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_ENAf); 7209 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_VALf); 7210 7211 return SOC_E_NONE; 7212 } 7213 7214 STATIC int 7215 _soc_greyhound_age_timer_max_get(int unit, int *max_seconds) 7216 { 7217 *max_seconds = 7218 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 7219 7220 return SOC_E_NONE; 7221 } 7222 7223 STATIC int 7224 _soc_greyhound_age_timer_set(int unit, int age_seconds, int enable) 7225 { 7226 uint32 value; 7227 7228 value = 0; 7229 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_ENAf, enable); 7230 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_VALf, age_seconds); 7231 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, value)); 7232 7233 return SOC_E_NONE; 7234 } 7235 7236 7237 void soc_greyhound_oam_handler_register(int unit, soc_greyhound_oam_handler_t handler) 7238 { 7239 uint32 rval; 7240 int rv, fidx = 0; 7241 gh_oam_handler[unit] = handler; 7242 rv = READ_IP1_INTR_ENABLEr(unit, &rval); 7243 if (rv) { 7244 LOG_ERROR(BSL_LS_SOC_COMMON, 7245 (BSL_META_U(unit, 7246 "unit %d: Error reading %s reg !!\n"), 7247 unit, SOC_REG_NAME(unit, IP1_INTR_ENABLEr))); 7248 } 7249 while (_soc_gh_oam_interrupt_fields[fidx] != INVALIDf) { 7250 soc_reg_field_set(unit, IP1_INTR_ENABLEr, &rval, 7251 _soc_gh_oam_interrupt_fields[fidx], 1); 7252 fidx++; 7253 } 7254 rv = WRITE_IP1_INTR_ENABLEr(unit, rval); 7255 if (rv) { 7256 LOG_ERROR(BSL_LS_SOC_COMMON, 7257 (BSL_META_U(unit, 7258 "unit %d: Error writing %s reg !!\n"), 7259 unit, SOC_REG_NAME(unit, IP1_INTR_ENABLEr))); 7260 } 7261 } 7262 7263 static const soc_reg_t pvtmon_result_reg[] = { 7264 TOP_PVTMON_RESULT_0r 7265 }; 7266 7267 int 7268 soc_gh_temperature_monitor_get(int unit, 7269 int temperature_max, 7270 soc_switch_temperature_monitor_t *temperature_array, 7271 int *temperature_count) 7272 { 7273 soc_reg_t reg; 7274 int index; 7275 uint32 rval; 7276 int fval, cur, peak; 7277 int num_entries_out; 7278 7279 *temperature_count = 0; 7280 if (COUNTOF(pvtmon_result_reg) > temperature_max) { 7281 num_entries_out = temperature_max; 7282 } else { 7283 num_entries_out = COUNTOF(pvtmon_result_reg); 7284 } 7285 7286 for (index = 0; index < num_entries_out; index++) { 7287 reg = pvtmon_result_reg[index]; 7288 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 7289 7290 fval = soc_reg_field_get(unit, reg, rval, PVT_DATAf); 7291 cur = (41016000 - (48517 * fval)) / 10000; 7292 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 7293 peak = (41016000 - (48517 * fval)) / 10000; 7294 (temperature_array + index)->curr = cur; 7295 (temperature_array + index)->peak = peak; 7296 } 7297 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 7298 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 7299 TOP_TEMP_MON_PEAK_RST_Lf, 0); 7300 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 7301 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 7302 TOP_TEMP_MON_PEAK_RST_Lf, 1); 7303 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 7304 7305 *temperature_count=num_entries_out; 7306 return SOC_E_NONE; 7307 } 7308 7309 typedef struct _gh_pgw_reg_info_s { 7310 soc_reg_t pgw_reg; 7311 uint32 valid_bm; 7312 uint32 invalid_bm; 7313 uint32 invalid_blk_num_bm; 7314 }_gh_pgw_reg_info_t; 7315 7316 STATIC _gh_pgw_reg_info_t _gh_pgw_reg_info[] = { 7317 {PGW_GX_CONFIGr, 0x3c, 0, 0x1f}, 7318 {PGW_GX_TXFIFO_CTRLr, 0x3c, 0, 0x1f}, 7319 {PGW_GX_SPARE0_REGr, 0x3c, 0, 0x1f}, 7320 {PGW_GX_RXFIFO_SOFT_RESETr, 0, 0, 0x1f}, 7321 {PGW_GX_ECC_CONTROLr, 0, 0, 0x1f}, 7322 {PGW_GX_RXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x1f}, 7323 {PGW_GX_RXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x1f}, 7324 {PGW_GX_RXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x1f}, 7325 {PGW_GX_RXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x1f}, 7326 {PGW_GX_TXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x1f}, 7327 {PGW_GX_TXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x1f}, 7328 {PGW_GX_TXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x1f}, 7329 {PGW_GX_TXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x1f}, 7330 {PGW_GX_TXFIFO2_ECC_SBE_STATUSr, 0, 0, 0x1f}, 7331 {PGW_GX_TXFIFO2_ECC_DBE_STATUSr, 0, 0, 0x1f}, 7332 {PGW_GX_TXFIFO3_ECC_SBE_STATUSr, 0, 0, 0x1f}, 7333 {PGW_GX_TXFIFO3_ECC_DBE_STATUSr, 0, 0, 0x1f}, 7334 {PGW_GX_TXFIFO_OVERFLOWr, 0, 0, 0x1f}, 7335 {PGW_GX_RXFIFO0_OVERFLOW_ERRORr, 0, 0, 0x1f}, 7336 {PGW_GX_RXFIFO1_OVERFLOW_ERRORr, 0, 0, 0x1f}, 7337 {PGW_GX_TM0_CONTROLr, 0, 0, 0x1f}, 7338 {PGW_GX_TM1_CONTROLr, 0, 0, 0x1f}, 7339 {PGW_GX_TM2_CONTROLr, 0, 0, 0x1f}, 7340 {PGW_GX_TM3_CONTROLr, 0, 0, 0x1f}, 7341 {PGW_GX_TM4_CONTROLr, 0, 0, 0x1f}, 7342 {PGW_GX_TM5_CONTROLr, 0, 0, 0x1f}, 7343 {PGW_GX_TM6_CONTROLr, 0, 0, 0x1f}, 7344 {PGW_GX_TM7_CONTROLr, 0, 0, 0x1f}, 7345 {PGW_GX_TM8_CONTROLr, 0, 0, 0x1f}, 7346 {PGW_GX_BYPASS_LED_CHAIN_CONFIGr, 0, 0, 0x1f}, 7347 {PGW_GX_INTR_STATUSr, 0, 0, 0x1f}, 7348 {PGW_GX_INTR_ENABLEr, 0, 0, 0x1f}, 7349 {PGW_XL_CONFIGr, 0, 0x3c, 0x20}, 7350 {PGW_XL_TXFIFO_CTRLr, 0, 0x3c, 0x20}, 7351 {PGW_XL_SPARE0_REGr, 0, 0x3c, 0x20}, 7352 {PGW_XL_RXFIFO_SOFT_RESETr, 0, 0, 0x20}, 7353 {PGW_XL_ECC_CONTROLr, 0, 0, 0x20}, 7354 {PGW_XL_RXFIFO_ECC_SBE_STATUSr, 0, 0, 0x20}, 7355 {PGW_XL_RXFIFO_ECC_DBE_STATUSr, 0, 0, 0x20}, 7356 {PGW_XL_TXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x20}, 7357 {PGW_XL_TXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x20}, 7358 {PGW_XL_TXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x20}, 7359 {PGW_XL_TXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x20}, 7360 {PGW_XL_TXFIFO2_ECC_SBE_STATUSr, 0, 0, 0x20}, 7361 {PGW_XL_TXFIFO2_ECC_DBE_STATUSr, 0, 0, 0x20}, 7362 {PGW_XL_TXFIFO3_ECC_SBE_STATUSr, 0, 0, 0x20}, 7363 {PGW_XL_TXFIFO3_ECC_DBE_STATUSr, 0, 0, 0x20}, 7364 {PGW_XL_TXFIFO_OVERFLOWr, 0, 0, 0x20}, 7365 {PGW_XL_RXFIFO_OVERFLOW_ERRORr, 0, 0, 0x20}, 7366 {PGW_XL_TM0_CONTROLr, 0, 0, 0x20}, 7367 {PGW_XL_TM1_CONTROLr, 0, 0, 0x20}, 7368 {PGW_XL_TM2_CONTROLr, 0, 0, 0x20}, 7369 {PGW_XL_TM3_CONTROLr, 0, 0, 0x20}, 7370 {PGW_XL_TM4_CONTROLr, 0, 0, 0x20}, 7371 {PGW_XL_TM5_CONTROLr, 0, 0, 0x20}, 7372 {PGW_XL_TM6_CONTROLr, 0, 0, 0x20}, 7373 {PGW_XL_TM7_CONTROLr, 0, 0, 0x20}, 7374 {PGW_XL_TM8_CONTROLr, 0, 0, 0x20}, 7375 {PGW_XL_BYPASS_LED_CHAIN_CONFIGr, 0, 0, 0x20}, 7376 {PGW_XL_INTR_STATUSr, 0, 0, 0x20}, 7377 {PGW_XL_INTR_ENABLEr, 0, 0, 0x20}, 7378 {INVALIDr, 0, 0}, 7379 }; 7380 7381 /* 7382 * Function: 7383 * soc_greyhound_pgw_reg_blk_index_get 7384 * Purpose: 7385 * Deal with the blk, blknum for PGW_GX and PGW_XL registers 7386 * Parameters: 7387 * reg (IN): register. 7388 * port (IN): logical port if PGW_GX's port register. 7389 * bm (IN/OUT): bm should be added for the reg. 7390 * block (IN/OUT): blk used to access the reg. 7391 * index (OUT): port index of the reg. 7392 * invalid_blk_check (IN): perform the blk check. 7393 * skip the block if the return value = 1. 7394 * Return: 7395 * SOC_E_NOT_FOUND : w/o bm,blk,invalid_blk_check case, register not matched. 7396 * 1 : register matched and the block/index has been override. 7397 * 1 : register matched and the valid bm has been override. 7398 * 1 : skip the block when the invalid_blk_check=1 7399 * SOC_E_PARAM : invalid paramter 7400 */ 7401 int 7402 soc_greyhound_pgw_reg_blk_index_get(int unit, 7403 soc_reg_t reg, soc_port_t port, 7404 pbmp_t *bm, int *block, int *index, int invalid_blk_check) { 7405 7406 int i, p, phy_port, blk_num, pgw_blk; 7407 soc_reg_info_t *reginfo; 7408 _gh_pgw_reg_info_t *pgw_reg = NULL; 7409 pbmp_t pgw_pbm, pgw_invalid_pbm; 7410 7411 pgw_blk = -1; 7412 SOC_PBMP_CLEAR(pgw_pbm); 7413 7414 for (i = 0; _gh_pgw_reg_info[i].pgw_reg != INVALIDr; i ++) { 7415 if (reg == _gh_pgw_reg_info[i].pgw_reg){ 7416 pgw_reg = &_gh_pgw_reg_info[i]; 7417 break; 7418 } 7419 } 7420 7421 if (!pgw_reg) { 7422 return SOC_E_NOT_FOUND; 7423 } 7424 7425 reginfo = &SOC_REG_INFO(unit, reg); 7426 phy_port = 0; 7427 if (reginfo->regtype == soc_portreg) { 7428 SOC_PBMP_WORD_SET(pgw_pbm, 0, pgw_reg->valid_bm); 7429 SOC_PBMP_WORD_SET(pgw_invalid_pbm, 0, pgw_reg->invalid_bm); 7430 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 7431 } 7432 7433 if (bm != NULL) { 7434 SOC_PBMP_ITER(pgw_pbm, p) { 7435 SOC_PBMP_PORT_ADD(*bm, p); 7436 } 7437 return 1; 7438 } 7439 if (block) { 7440 if (reginfo->regtype == soc_portreg) { 7441 if( SOC_PORT_BLOCK_TYPE(unit,phy_port) == SOC_BLK_GXPORT ){ 7442 if(SOC_PBMP_MEMBER(pgw_pbm, port)) { 7443 /* get the blk from phy_port=2 bindex=1 i.e. XLPORT5*/ 7444 pgw_blk = SOC_PORT_IDX_BLOCK(unit, 2, 1); 7445 if (index) { 7446 *index = phy_port - 2; 7447 } 7448 if (!invalid_blk_check) { 7449 *block = pgw_blk; 7450 return 1; 7451 } 7452 } 7453 if(SOC_PBMP_MEMBER(pgw_invalid_pbm, port)) { 7454 *block = 0; 7455 return 1; 7456 } 7457 } 7458 } 7459 } 7460 if (invalid_blk_check){ 7461 if(!block){ 7462 return SOC_E_PARAM; 7463 } 7464 /* check if the *block is valid for the reg */ 7465 7466 if (pgw_blk == -1) { 7467 pgw_blk = *block; 7468 } 7469 blk_num = SOC_BLOCK_NUMBER(unit, pgw_blk) & 0xff; 7470 if (pgw_reg->invalid_blk_num_bm & (1 << blk_num)){ 7471 return 1; 7472 } 7473 } 7474 return SOC_E_NONE; 7475 } 7476 7477 int 7478 _soc_greyhound_features(int unit, soc_feature_t feature){ 7479 7480 uint16 dev_id; 7481 uint8 rev_id; 7482 7483 soc_cm_get_id(unit, &dev_id, &rev_id); 7484 7485 switch (feature) { 7486 case soc_feature_tsce: 7487 case soc_feature_arl_hashed: 7488 case soc_feature_arl_insert_ovr: 7489 case soc_feature_cfap_pool: 7490 case soc_feature_cos_rx_dma: 7491 case soc_feature_dcb_type31: 7492 case soc_feature_ingress_metering: 7493 case soc_feature_egress_metering: 7494 case soc_feature_l3_ip6: 7495 case soc_feature_l3_lookup_cmd: 7496 case soc_feature_led_proc: 7497 case soc_feature_led_data_offset_a0: 7498 case soc_feature_schmsg_alias: 7499 case soc_feature_stack_my_modid: 7500 case soc_feature_stat_dma: 7501 case soc_feature_cpuport_stat_dma: 7502 case soc_feature_table_dma: 7503 case soc_feature_tslam_dma: 7504 case soc_feature_stg: 7505 case soc_feature_stg_xgs: 7506 case soc_feature_remap_ut_prio: 7507 case soc_feature_xgxs_v7: 7508 case soc_feature_phy_cl45: 7509 case soc_feature_aging_extended: 7510 case soc_feature_modmap: 7511 case soc_feature_l3_sgv: 7512 case soc_feature_l3_dynamic_ecmp_group: 7513 case soc_feature_l2_hashed: 7514 case soc_feature_l2_lookup_cmd: 7515 case soc_feature_l2_lookup_retry: 7516 case soc_feature_l2_user_table: 7517 case soc_feature_schan_hw_timeout: 7518 case soc_feature_lpm_tcam: 7519 case soc_feature_mdio_enhanced: 7520 case soc_feature_dodeca_serdes: 7521 case soc_feature_rxdma_cleanup: 7522 case soc_feature_fe_maxframe: 7523 case soc_feature_l2x_parity: 7524 case soc_feature_l3x_parity: 7525 case soc_feature_l2_modfifo: 7526 case soc_feature_vlan_mc_flood_ctrl: 7527 case soc_feature_vlan_translation: 7528 case soc_feature_parity_err_tocpu: 7529 case soc_feature_nip_l3_err_tocpu: 7530 case soc_feature_l3mtu_fail_tocpu: 7531 case soc_feature_meter_adjust: 7532 case soc_feature_xgxs_power: 7533 case soc_feature_src_modid_blk: 7534 case soc_feature_src_modid_blk_ucast_override: 7535 case soc_feature_src_modid_blk_opcode_override: 7536 case soc_feature_egress_blk_ucast_override: 7537 case soc_feature_stat_jumbo_adj: 7538 case soc_feature_stat_xgs3: 7539 case soc_feature_port_trunk_index: 7540 case soc_feature_cpuport_switched: 7541 case soc_feature_cpuport_mirror: 7542 case soc_feature_higig2: 7543 case soc_feature_color: 7544 case soc_feature_color_inner_cfi: 7545 case soc_feature_color_prio_map: 7546 case soc_feature_untagged_vt_miss: 7547 case soc_feature_module_loopback: 7548 case soc_feature_dscp_map_per_port: 7549 case soc_feature_egr_dscp_map_per_port: 7550 case soc_feature_dscp_map_mode_all: 7551 case soc_feature_higig_lookup: 7552 case soc_feature_egr_mirror_path: 7553 case soc_feature_trunk_extended: 7554 case soc_feature_hg_trunking: 7555 case soc_feature_hg_trunk_override: 7556 case soc_feature_egr_vlan_check: 7557 case soc_feature_cpu_proto_prio: 7558 case soc_feature_hg_trunk_failover: 7559 case soc_feature_trunk_egress: 7560 case soc_feature_force_forward: 7561 case soc_feature_port_egr_block_ctl: 7562 case soc_feature_bucket_support: 7563 case soc_feature_remote_learn_trust: 7564 case soc_feature_src_mac_group: 7565 case soc_feature_storm_control: 7566 case soc_feature_hw_stats_calc: 7567 case soc_feature_mac_learn_limit: 7568 case soc_feature_linear_drr_weight: 7569 case soc_feature_igmp_mld_support: 7570 case soc_feature_basic_dos_ctrl: 7571 case soc_feature_enhanced_dos_ctrl: 7572 case soc_feature_proto_pkt_ctrl: 7573 case soc_feature_vlan_ctrl: 7574 case soc_feature_big_icmpv6_ping_check: 7575 case soc_feature_trunk_group_overlay: 7576 case soc_feature_xport_convertible: 7577 case soc_feature_dual_hash: 7578 case soc_feature_dscp: 7579 case soc_feature_unimac: 7580 case soc_feature_ifg_wb_include_unimac: 7581 case soc_feature_xlmac: 7582 case soc_feature_generic_table_ops: 7583 case soc_feature_vlan_translation_range: 7584 case soc_feature_static_pfm: 7585 case soc_feature_sgmii_autoneg: 7586 #ifdef INCLUDE_RCPU 7587 case soc_feature_rcpu_1: 7588 case soc_feature_rcpu_priority: 7589 case soc_feature_rcpu_tc_mapping: 7590 #endif 7591 case soc_feature_mem_push_pop: 7592 case soc_feature_dcb_reason_hi: 7593 case soc_feature_multi_sbus_cmds: 7594 case soc_feature_new_sbus_format: 7595 case soc_feature_new_sbus_old_resp: 7596 case soc_feature_sbus_format_v4: 7597 case soc_feature_fifo_dma: 7598 case soc_feature_fifo_dma_active: 7599 case soc_feature_l3_entry_key_type: 7600 case soc_feature_l2_pending: 7601 case soc_feature_internal_loopback: 7602 case soc_feature_vlan_action: 7603 case soc_feature_mac_based_vlan: 7604 case soc_feature_ip_subnet_based_vlan: 7605 case soc_feature_packet_rate_limit: 7606 case soc_feature_system_mac_learn_limit: 7607 case soc_feature_field: 7608 case soc_feature_field_meter_pools8: 7609 case soc_feature_field_mirror_ovr: 7610 case soc_feature_field_udf_higig: 7611 case soc_feature_field_udf_ethertype: 7612 case soc_feature_field_comb_read: 7613 case soc_feature_field_wide: 7614 case soc_feature_field_slice_enable: 7615 case soc_feature_field_cos: 7616 case soc_feature_field_color_indep: 7617 case soc_feature_field_qual_drop: 7618 case soc_feature_field_qual_IpType: 7619 case soc_feature_field_qual_Ip6High: 7620 case soc_feature_field_ingress_global_meter_pools: 7621 case soc_feature_field_ingress_ipbm: 7622 case soc_feature_field_egress_flexible_v6_key: 7623 case soc_feature_field_egress_global_counters: 7624 case soc_feature_field_ing_egr_separate_packet_byte_counters: 7625 case soc_feature_field_egress_metering: 7626 case soc_feature_field_intraslice_double_wide: 7627 case soc_feature_field_virtual_slice_group: 7628 case soc_feature_field_action_timestamp: 7629 case soc_feature_field_action_l2_change: 7630 case soc_feature_field_virtual_queue: 7631 case soc_feature_field_action_redirect_nexthop: 7632 case soc_feature_field_slice_dest_entity_select: 7633 case soc_feature_field_packet_based_metering: 7634 case soc_feature_lport_tab_profile: 7635 case soc_feature_ignore_cmic_xgxs_pll_status: 7636 case soc_feature_use_double_freq_for_ddr_pll: 7637 case soc_feature_counter_parity: 7638 case soc_feature_extended_pci_error: 7639 case soc_feature_priority_flow_control: 7640 case soc_feature_gh_style_pfc_config: 7641 case soc_feature_qos_profile: 7642 case soc_feature_rx_timestamp: 7643 case soc_feature_rx_timestamp_upper: 7644 case soc_feature_logical_port_num: 7645 case soc_feature_timestamp_counter: 7646 case soc_feature_generic_counters: 7647 case soc_feature_modport_map_profile: 7648 case soc_feature_modport_map_dest_is_hg_port_bitmap: 7649 case soc_feature_eee: 7650 case soc_feature_xy_tcam: 7651 case soc_feature_xy_tcam_direct: 7652 case soc_feature_xy_tcam_28nm: 7653 case soc_feature_vlan_egr_it_inner_replace: 7654 case soc_feature_cmicm: 7655 case soc_feature_iproc: 7656 case soc_feature_iproc_7: 7657 case soc_feature_unified_port: 7658 case soc_feature_sbusdma: 7659 case soc_feature_mirror_encap_profile: 7660 case soc_feature_higig_misc_speed_support: 7661 case soc_feature_vpd_profile: 7662 case soc_feature_color_prio_map_profile: 7663 case soc_feature_port_extension: 7664 case soc_feature_niv: 7665 case soc_feature_mem_parity_eccmask: 7666 case soc_feature_discard_ability: 7667 case soc_feature_wred_drop_counter_per_port: 7668 case soc_feature_l2_no_vfi: 7669 case soc_feature_time_support: 7670 case soc_feature_time_v3: 7671 case soc_feature_timesync_support: 7672 case soc_feature_timesync_v3: 7673 case soc_feature_time_synce_divisor_setting: 7674 case soc_feature_gmii_clkout: 7675 case soc_feature_l3mc_use_egress_next_hop: 7676 case soc_feature_field_action_pfc_class: 7677 case soc_feature_fifo_dma_hu2: 7678 case soc_feature_proxy_port_property: 7679 case soc_feature_system_reserved_vlan: 7680 case soc_feature_ser_parity: 7681 case soc_feature_mem_cache: 7682 case soc_feature_mem_wb_cache_reload: 7683 case soc_feature_ser_engine: 7684 case soc_feature_ser_system_scrub: 7685 case soc_feature_regs_as_mem: 7686 case soc_feature_cmicd_v2: 7687 case soc_feature_cmicm_extended_interrupts: 7688 case soc_feature_int_common_init: 7689 case soc_feature_inner_tpid_enable: 7690 case soc_feature_no_tunnel: 7691 case soc_feature_ecn_wred: 7692 case soc_feature_eee_bb_mode: 7693 case soc_feature_field_oam_actions: 7694 case soc_feature_hg_no_speed_change: 7695 case soc_feature_hr2_dual_hash: 7696 case soc_feature_uc: 7697 case soc_feature_uc_mhost: 7698 case soc_feature_iproc_ddr: 7699 case soc_feature_ptp: 7700 case soc_feature_field_qual_vlanformat_reverse: 7701 case soc_feature_cpureg_dump: 7702 case soc_feature_ignore_mem_write_nak: 7703 case soc_feature_field_udf_offset_hg_114B: 7704 case soc_feature_field_udf_offset_hg2_110B: 7705 case soc_feature_eee_stat_clear_directly: 7706 case soc_feature_pktpri_as_dot1p: 7707 case soc_feature_cosq_hol_drop_packet_count: 7708 case soc_feature_hg2_light_in_portmacro: 7709 case soc_feature_sync_port_lport_tab: 7710 case soc_feature_port_encap_speed_max_config: 7711 case soc_feature_serdes_firmware_pos_by_host_endian: 7712 case soc_feature_dport_update_hl: 7713 return TRUE; 7714 case soc_feature_field_multi_stage: /* include VFP, EFP */ 7715 /* Ranger 2 only */ 7716 if ((dev_id & 0xF000) == 0xB000) { 7717 return TRUE; 7718 } else { 7719 return FALSE; 7720 } 7721 case soc_feature_field_slice_size128: /* Half set FP */ 7722 case soc_feature_l3_no_ecmp: /* no ecmp in l3 */ 7723 /* other than Ranger2 */ 7724 if ((dev_id & 0xF000) == 0xB000) { 7725 return FALSE; 7726 } else { 7727 return TRUE; 7728 } 7729 case soc_feature_time_v3_no_bs: 7730 /* Lite sku (sku w/o A9) */ 7731 if (((dev_id & 0x00F0) == 0x0000) || ((dev_id & 0x0061) == 0x0040) || 7732 ((dev_id & 0x0060) == 0x0020) || 7733 (dev_id == BCM53365_DEVICE_ID)|| 7734 (dev_id == BCM53369_DEVICE_ID)) { 7735 /* No BroadSync interfaces for lite SKUs */ 7736 return TRUE; 7737 } else { 7738 return FALSE; 7739 } 7740 case soc_feature_field_slices8: 7741 /* other than Bloodhound */ 7742 if ((dev_id & 0x0060) == 0x0020) { 7743 return FALSE; 7744 } else { 7745 return TRUE; 7746 } 7747 case soc_feature_field_slices4: 7748 /* Bloodhound only */ 7749 if ((dev_id & 0x0060) == 0x0020) { 7750 return TRUE; 7751 } else { 7752 return FALSE; 7753 } 7754 case soc_feature_l3: 7755 case soc_feature_ip_mcast: 7756 case soc_feature_ip_mcast_repl: 7757 case soc_feature_ipmc_unicast: 7758 case soc_feature_ipmc_use_configured_dest_mac: 7759 case soc_feature_oam: 7760 /* l3 related*/ 7761 /* other than Bloodhound and 53365 */ 7762 if (((dev_id & 0x0060) == 0x0020) || (dev_id == BCM53365_DEVICE_ID)) { 7763 return FALSE; 7764 } else { 7765 return TRUE; 7766 } 7767 7768 case soc_feature_core_clock_300m: 7769 if ((dev_id == BCM56060_DEVICE_ID) || 7770 (dev_id == BCM53405_DEVICE_ID) || 7771 (dev_id == BCM53415_DEVICE_ID) || 7772 (dev_id == BCM53406_DEVICE_ID) || 7773 (dev_id == BCM53416_DEVICE_ID) || 7774 (dev_id == BCM56062_DEVICE_ID) || 7775 (dev_id == BCM53454_DEVICE_ID) || 7776 (dev_id == BCM53455_DEVICE_ID) || 7777 (dev_id == BCM53456_DEVICE_ID) || 7778 (dev_id == BCM53457_DEVICE_ID) || 7779 (dev_id == BCM53365_DEVICE_ID) || 7780 (dev_id == BCM53369_DEVICE_ID)){ 7781 return TRUE; 7782 } else { 7783 return FALSE; 7784 } 7785 case soc_feature_timesync_timestampingmode: 7786 return TRUE; 7787 case soc_feature_portmod: 7788 return FALSE; 7789 case soc_feature_uc_image_name_with_no_chip_rev: 7790 return TRUE; 7791 default: 7792 return FALSE; 7793 } 7794 } 7795 7796 #if defined(SER_TR_TEST_SUPPORT) 7797 7798 /* Overlay memory */ 7799 const soc_ser_overlay_test_t soc_ser_gh_overlay_mems[] = { 7800 {L3_ENTRY_IPV4_UNICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 7801 {L3_ENTRY_IPV4_MULTICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 7802 {L3_ENTRY_IPV6_MULTICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 7803 {L3_ENTRY_IPV6_UNICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 7804 {MODPORT_MAPm, MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, MODPORT_MAP_SWm, _SOC_ACC_TYPE_PIPE_ANY}, 7805 {INVALIDm} 7806 }; 7807 7808 7809 7810 /* 7811 * Function: 7812 * soc_gh_ser_mem_test 7813 * Purpose: 7814 * Performs a SER test on a single Greyhound memory 7815 * Parameters: 7816 * unit - (IN) Device Number 7817 * mem - (IN) The memory to test 7818 * test_type - (IN) How many indices in the memory to test 7819 * cmd - (IN) TRUE if a command-line test is desired. 7820 */ 7821 int soc_gh_ser_mem_test(int unit, soc_mem_t mem, 7822 _soc_ser_test_t test_type, int cmd) { 7823 int group, table, i, rv = SOC_E_NONE, found_mem = FALSE; 7824 _soc_gh_parity_info_t *info; 7825 soc_mem_t memTable; 7826 soc_port_t block_port; 7827 soc_block_t blk; 7828 int testErrors = 0; 7829 ser_test_data_t test_data; 7830 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 7831 uint32 reg_val, wred_refresh = 0; 7832 int overlay_mem = 0; 7833 _soc_generic_ser_info_t *tcam_ser_info; 7834 _soc_gh_parity_group_info_t *parity_group_info; 7835 7836 soc_ser_test_long_sleep = TRUE; 7837 soc_ser_test_long_sleep_time_us = 500000; 7838 7839 tcam_ser_info = _soc_gh_tcam_ser_info[unit]; 7840 7841 if (tcam_ser_info != NULL) { 7842 /*TCAM_test*/ 7843 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 7844 if (tcam_ser_info[i].mem == mem) { 7845 found_mem = TRUE; 7846 soc_ser_create_test_data(unit, tmp_entry, fieldData, 7847 SER_RANGE_ENABLEr, i, INVALIDf, mem, 7848 VALIDf, MEM_BLOCK_ANY, REG_PORT_ANY, 7849 _SOC_ACC_TYPE_PIPE_ANY, 0, &test_data); 7850 if (cmd) { 7851 ser_test_cmd_generate(unit, &test_data); 7852 } else { 7853 rv = ser_test_mem(unit, 0, &test_data, 7854 test_type, &testErrors); 7855 if (rv != SOC_E_NONE) { 7856 LOG_CLI((BSL_META_U(unit, 7857 "Error during TCAM test. Aborting.\n"))); 7858 soc_ser_test_long_sleep = FALSE; 7859 return rv; 7860 } 7861 } 7862 } 7863 } 7864 } 7865 7866 parity_group_info = _soc_gh_parity_group_info[unit]; 7867 7868 if ((!found_mem) && (parity_group_info != NULL)) { 7869 /*H/W memory Test*/ 7870 for (group = 0; parity_group_info[group].cpi_bit; group++) { 7871 info = parity_group_info[group].info; 7872 7873 SOC_BLOCK_ITER(unit, blk, 7874 parity_group_info[group].blocktype) { 7875 if (_soc_greyhound_parity_block_port(unit, 7876 blk, &block_port) < 0) { 7877 continue; 7878 } 7879 7880 if (parity_group_info[group].blocktype == 7881 SOC_BLK_XLPORT) { 7882 /* Skip */ 7883 continue; 7884 } 7885 7886 for (table = 0; info[table].error_field != INVALIDf; table++) { 7887 memTable = info[table].mem; 7888 if (memTable == INVALIDm) { 7889 continue; 7890 } 7891 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 7892 continue; 7893 } 7894 /* Check if overlay memory */ 7895 for (i=0; soc_ser_gh_overlay_mems[i].mem != INVALIDm; i++) { 7896 if ((soc_ser_gh_overlay_mems[i].mem == mem) && 7897 (soc_ser_gh_overlay_mems[i].base_mem == memTable)) { 7898 overlay_mem = 1; 7899 break; 7900 } 7901 } 7902 7903 if ((memTable == mem) || (overlay_mem)) { 7904 found_mem = TRUE; 7905 if (parity_group_info[group].blocktype 7906 == SOC_BLK_MMU) { 7907 soc_ser_create_test_data(unit, tmp_entry, fieldData, 7908 MISCCONFIGr, 7909 SOC_INVALID_TCAM_PARITY_BIT, 7910 PARITY_CHECK_ENf, 7911 mem, INVALIDf, blk, 7912 block_port, _SOC_ACC_TYPE_PIPE_ANY, 0, 7913 &test_data); 7914 wred_refresh = 0; 7915 if ((mem == MMU_WRED_AVG_QSIZEm) || 7916 (mem == MMU_WRED_MARK_THDm)) { 7917 /* Save WRED refresh configuration */ 7918 rv = soc_reg32_get(unit, 7919 FUNCTIONAL_REFRESH_ENr, block_port, 0, 7920 ®_val); 7921 if (rv != SOC_E_NONE) { 7922 LOG_CLI((BSL_META_U(unit, 7923 "Error of getting WRED " 7924 "refresh function " 7925 "Aborting.\n"))); 7926 soc_ser_test_long_sleep = FALSE; 7927 return rv; 7928 } 7929 wred_refresh = soc_reg_field_get(unit, 7930 FUNCTIONAL_REFRESH_ENr, 7931 reg_val, WRED_REFRESH_ENf); 7932 if (wred_refresh) { 7933 soc_reg_field_set(unit, 7934 FUNCTIONAL_REFRESH_ENr, ®_val, 7935 WRED_REFRESH_ENf, 0); 7936 rv = soc_reg32_set(unit, 7937 FUNCTIONAL_REFRESH_ENr, block_port, 0, 7938 reg_val); 7939 if (rv != SOC_E_NONE) { 7940 LOG_CLI((BSL_META_U(unit, 7941 "Error of disabling WRED " 7942 "refresh function " 7943 "Aborting.\n"))); 7944 soc_ser_test_long_sleep = FALSE; 7945 return rv; 7946 } 7947 } 7948 } 7949 if (cmd) { 7950 ser_test_cmd_generate(unit, &test_data); 7951 } else { 7952 rv = ser_test_mem(unit, 0, &test_data, 7953 test_type, &testErrors); 7954 } 7955 /* restore WRED refresh configuration */ 7956 if (wred_refresh) { 7957 soc_reg_field_set(unit, 7958 FUNCTIONAL_REFRESH_ENr, ®_val, 7959 WRED_REFRESH_ENf, 1); 7960 rv = soc_reg32_set(unit, 7961 FUNCTIONAL_REFRESH_ENr, block_port, 0, 7962 reg_val); 7963 if (rv != SOC_E_NONE) { 7964 LOG_CLI((BSL_META_U(unit, 7965 "Error of enabling WRED " 7966 "refresh function " 7967 "Aborting.\n"))); 7968 soc_ser_test_long_sleep = FALSE; 7969 return rv; 7970 } 7971 } 7972 } else { 7973 if (mem == TRUNK_GROUPm) { 7974 /* 7975 * Since the RTAG field of TRUNK GROUP memories is implemented 7976 * by register. We need to assign the test field for this test 7977 */ 7978 test_data.test_field = EVEN_PARITYf; 7979 } 7980 soc_ser_create_test_data(unit, tmp_entry, fieldData, 7981 info[table].control_reg, 7982 SOC_INVALID_TCAM_PARITY_BIT, 7983 info[table].enable_field, 7984 mem, EVEN_PARITYf, blk, 7985 block_port, _SOC_ACC_TYPE_PIPE_ANY, 0, 7986 &test_data); 7987 if (cmd) { 7988 ser_test_cmd_generate(unit, &test_data); 7989 } else { 7990 rv = ser_test_mem(unit, 0, &test_data, 7991 test_type, &testErrors); 7992 } 7993 } 7994 if (rv != SOC_E_NONE) { 7995 LOG_CLI((BSL_META_U(unit, 7996 "Error during H/W test. Aborting.\n"))); 7997 soc_ser_test_long_sleep = FALSE; 7998 return rv; 7999 } 8000 break; 8001 } 8002 } 8003 if (found_mem) { 8004 break; 8005 } 8006 8007 } 8008 8009 if (found_mem) { 8010 break; 8011 } 8012 } 8013 } 8014 8015 if (!found_mem) { 8016 LOG_CLI((BSL_META_U(unit, 8017 "SER Test is unavaible on unit: %d for memory %s\n"), unit, 8018 SOC_MEM_NAME(unit,mem))); 8019 return SOC_E_UNAVAIL; 8020 } 8021 8022 if (testErrors == 0) { 8023 LOG_CLI((BSL_META_U(unit, 8024 "SER Test passed on unit: %d for memory %s\n"), unit, 8025 SOC_MEM_NAME(unit,mem))); 8026 } 8027 else { 8028 LOG_CLI((BSL_META_U(unit, 8029 "SER Test failed on unit: %d for memory %s\n"), unit, 8030 SOC_MEM_NAME(unit,mem))); 8031 soc_ser_test_long_sleep = FALSE; 8032 return SOC_E_MEMORY; 8033 } 8034 /* restore to default */ 8035 soc_ser_test_long_sleep = FALSE; 8036 return SOC_E_NONE; 8037 } 8038 8039 /* 8040 * Function: 8041 * soc_gh_ser_test 8042 * Purpose: 8043 * Performs a SER test on all Greyhound Memories 8044 * Parameters: 8045 * unit - (IN) Device Number 8046 * test_type - (IN) Determines how comprehensive of a test to run 8047 */ 8048 int soc_gh_ser_test(int unit, _soc_ser_test_t test_type) { 8049 int i, group, rv, table; 8050 _soc_gh_parity_info_t *info; 8051 soc_port_t block_port; 8052 soc_mem_t memTable; 8053 soc_field_t testfield; 8054 soc_block_t blk; 8055 int numTCAMErr = 0; 8056 int numHwMemErr = 0; 8057 uint32 reg_val, wred_refresh = 0; 8058 _soc_generic_ser_info_t *tcam_ser_info; 8059 _soc_gh_parity_group_info_t *parity_group_info; 8060 8061 soc_ser_test_long_sleep = TRUE; 8062 soc_ser_test_long_sleep_time_us = 500000; 8063 8064 tcam_ser_info = _soc_gh_tcam_ser_info[unit]; 8065 8066 if (tcam_ser_info != NULL) { 8067 /*Test each TCAM memory*/ 8068 for(i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 8069 rv = ser_test_mem_pipe(unit, SER_RANGE_ENABLEr, i, -1, 8070 tcam_ser_info[i].mem, VALIDf, test_type, 8071 MEM_BLOCK_ANY, REG_PORT_ANY, 8072 _SOC_ACC_TYPE_PIPE_ANY, &numTCAMErr); 8073 if (rv != SOC_E_NONE) { 8074 LOG_CLI((BSL_META_U(unit, 8075 "TR 144 test failed. " 8076 "Error during TCAM test. Aborting.\n"))); 8077 soc_ser_test_long_sleep = FALSE; 8078 return rv; 8079 } 8080 } 8081 } 8082 8083 parity_group_info = _soc_gh_parity_group_info[unit]; 8084 8085 if (parity_group_info != NULL) { 8086 /*H/W memory Test*/ 8087 for (group = 0; parity_group_info[group].cpi_bit; group++) { 8088 info = parity_group_info[group].info; 8089 8090 SOC_BLOCK_ITER(unit, blk, 8091 parity_group_info[group].blocktype) { 8092 if (_soc_greyhound_parity_block_port(unit, blk, &block_port) < 0) { 8093 continue; 8094 } 8095 8096 if (parity_group_info[group].blocktype == SOC_BLK_XLPORT) { 8097 /* no memoy can be tested */ 8098 continue; 8099 } 8100 8101 for (table = 0; info[table].error_field != INVALIDf; table++) { 8102 memTable = info[table].mem; 8103 if (memTable == INVALIDm) { 8104 continue; 8105 } 8106 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 8107 continue; 8108 } 8109 testfield = INVALIDf; 8110 if (parity_group_info[group].blocktype == 8111 SOC_BLK_MMU) { 8112 if ((memTable == MMU_WRED_AVG_QSIZEm) || 8113 (memTable == MMU_WRED_MARK_THDm)) { 8114 /* Save WRED refresh configuration */ 8115 rv = soc_reg32_get(unit, 8116 FUNCTIONAL_REFRESH_ENr, block_port, 0, 8117 ®_val); 8118 if (rv != SOC_E_NONE) { 8119 LOG_CLI((BSL_META_U(unit, 8120 "TR 144 test failed. " 8121 "Error of getting WRED " 8122 "refresh function Aborting.\n"))); 8123 soc_ser_test_long_sleep = FALSE; 8124 return rv; 8125 } 8126 wred_refresh = soc_reg_field_get(unit, 8127 FUNCTIONAL_REFRESH_ENr, 8128 reg_val, WRED_REFRESH_ENf); 8129 if (wred_refresh) { 8130 soc_reg_field_set(unit, 8131 FUNCTIONAL_REFRESH_ENr, ®_val, 8132 WRED_REFRESH_ENf, 0); 8133 rv = soc_reg32_set(unit, 8134 FUNCTIONAL_REFRESH_ENr, block_port, 0, 8135 reg_val); 8136 if (rv != SOC_E_NONE) { 8137 LOG_CLI((BSL_META_U(unit, 8138 "TR 144 test failed. " 8139 "Error of disabling WRED " 8140 "refresh function Aborting.\n"))); 8141 soc_ser_test_long_sleep = FALSE; 8142 return rv; 8143 } 8144 } 8145 } 8146 8147 rv = ser_test_mem_pipe(unit, MISCCONFIGr, -1, 8148 PARITY_CHECK_ENf, 8149 info[table].mem, testfield, test_type, 8150 blk, block_port, 8151 _SOC_ACC_TYPE_PIPE_ANY, &numHwMemErr); 8152 8153 if ((memTable == MMU_WRED_AVG_QSIZEm) || 8154 (memTable == MMU_WRED_MARK_THDm)) { 8155 /* restore WRED refresh configuration */ 8156 if (wred_refresh) { 8157 soc_reg_field_set(unit, 8158 FUNCTIONAL_REFRESH_ENr, ®_val, 8159 WRED_REFRESH_ENf, 1); 8160 rv = soc_reg32_set(unit, 8161 FUNCTIONAL_REFRESH_ENr, block_port, 0, 8162 reg_val); 8163 if (rv != SOC_E_NONE) { 8164 LOG_CLI((BSL_META_U(unit, 8165 "TR 144 test failed. " 8166 "Error of enabling WRED " 8167 "refresh function Aborting.\n"))); 8168 soc_ser_test_long_sleep = FALSE; 8169 return rv; 8170 } 8171 } 8172 } 8173 } else { 8174 if (memTable == TRUNK_GROUPm) { 8175 testfield = EVEN_PARITYf; 8176 } 8177 rv = ser_test_mem_pipe(unit,info[table].control_reg, -1, 8178 info[table].enable_field, 8179 info[table].mem, testfield, test_type, 8180 blk, block_port, 8181 _SOC_ACC_TYPE_PIPE_ANY, &numHwMemErr); 8182 } 8183 if (rv != SOC_E_NONE) { 8184 LOG_CLI((BSL_META_U(unit, 8185 "TR 144 test failed. " 8186 "Error during H/W test. Aborting.\n"))); 8187 soc_ser_test_long_sleep = FALSE; 8188 return rv; 8189 } 8190 } 8191 8192 } 8193 } 8194 } 8195 8196 if((numTCAMErr != 0) || (numHwMemErr != 0)) { 8197 LOG_CLI((BSL_META_U(unit, 8198 "TR 144 test failed.\n"))); 8199 } 8200 8201 LOG_CLI((BSL_META_U(unit, 8202 "Total TCAM errors on unit %d: %d\n"), unit, numTCAMErr)); 8203 LOG_CLI((BSL_META_U(unit, 8204 "Total H/W parity errors on unit %d: %d\n"),unit, numHwMemErr)); 8205 soc_ser_test_long_sleep = FALSE; 8206 return SOC_E_NONE; 8207 } 8208 8209 STATIC int soc_gh_tcam_entry_is_invalid(int unit, 8210 soc_mem_t mem, int index) 8211 { 8212 if (soc_feature(unit, soc_feature_field_slice_size128)) { 8213 if (mem == FP_GLOBAL_MASK_TCAMm || mem == FP_TCAMm) { 8214 if ((index / 64) % 2) { 8215 return TRUE; 8216 } 8217 } 8218 } 8219 return FALSE; 8220 } 8221 8222 /* 8223 * Function: 8224 * soc_gh_ser_inject_error 8225 * Purpose: 8226 * Injects an error into a single GH memory 8227 * Parameters: 8228 * unit - (IN) Device Number 8229 * mem - (IN) The memory to test 8230 * pipeTarget - (IN) The pipe (x/y) to use when injecting the error 8231 * block - (IN) The index into which block will be injected. 8232 * index - (IN) The index into which the error will be injected. 8233 */ 8234 int soc_gh_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, 8235 int pipeTarget, int block, int index) 8236 { 8237 int group, table, i; 8238 _soc_gh_parity_info_t *info; 8239 soc_mem_t memTable; 8240 soc_port_t block_port; 8241 soc_block_t blk; 8242 ser_test_data_t test_data; 8243 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 8244 int overlay_mem = 0; 8245 _soc_generic_ser_info_t *tcam_ser_info; 8246 _soc_gh_parity_group_info_t *parity_group_info; 8247 8248 tcam_ser_info = _soc_gh_tcam_ser_info[unit]; 8249 8250 if (tcam_ser_info != NULL) { 8251 /*TCAM_test*/ 8252 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 8253 if (tcam_ser_info[i].mem == mem) { 8254 /* Check if this entry is invalid or not */ 8255 if (soc_gh_tcam_entry_is_invalid(unit, mem, index)) { 8256 return (SOC_E_PARAM); 8257 } 8258 soc_ser_create_test_data(unit, tmp_entry, fieldData, 8259 SER_RANGE_ENABLEr, i, VALIDf, mem, 8260 VALIDf, MEM_BLOCK_ANY, REG_PORT_ANY, 8261 _SOC_ACC_TYPE_PIPE_ANY, index, &test_data); 8262 /*Disable parity*/ 8263 SOC_IF_ERROR_RETURN( 8264 _ser_test_parity_control(unit, &test_data, 0)); 8265 /*Read the memory for successful injection*/ 8266 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 8267 /*Inject error*/ 8268 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, 8269 &test_data)); 8270 /*Enable parity*/ 8271 SOC_IF_ERROR_RETURN( 8272 _ser_test_parity_control(unit, &test_data, 1)); 8273 return SOC_E_NONE; 8274 8275 } 8276 } 8277 } 8278 8279 parity_group_info = _soc_gh_parity_group_info[unit]; 8280 8281 if (parity_group_info != NULL) { 8282 /*H/W memory Test*/ 8283 for (group = 0; parity_group_info[group].cpi_bit; group++) { 8284 info = parity_group_info[group].info; 8285 8286 SOC_BLOCK_ITER(unit, blk, 8287 parity_group_info[group].blocktype) { 8288 if (_soc_greyhound_parity_block_port(unit, blk, 8289 &block_port) < 0) { 8290 continue; 8291 } 8292 8293 for (table = 0; info[table].error_field != INVALIDf; table++) { 8294 memTable = info[table].mem; 8295 if (memTable == INVALIDm) { 8296 continue; 8297 } 8298 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 8299 continue; 8300 } 8301 /* Check if overlay memory */ 8302 for (i=0; soc_ser_gh_overlay_mems[i].mem != INVALIDm; i++) { 8303 if ((soc_ser_gh_overlay_mems[i].mem == mem) && 8304 (soc_ser_gh_overlay_mems[i].base_mem == memTable)) { 8305 overlay_mem = 1; 8306 break; 8307 } 8308 } 8309 8310 if ((memTable == mem) || (overlay_mem)) { 8311 if((blk == block) || (block == MEM_BLOCK_ANY)) 8312 { 8313 /*Inject error*/ 8314 test_data.mem = mem; 8315 test_data.tcam_parity_bit = -1; 8316 if (parity_group_info[group].blocktype 8317 == SOC_BLK_MMU) { 8318 soc_ser_create_test_data(unit, tmp_entry, 8319 fieldData, 8320 MISCCONFIGr, 8321 SOC_INVALID_TCAM_PARITY_BIT, 8322 PARITY_CHECK_ENf, 8323 mem, EVEN_PARITYf, blk, 8324 block_port, _SOC_ACC_TYPE_PIPE_ANY, 8325 index, &test_data); 8326 } else { 8327 soc_ser_create_test_data(unit, tmp_entry, 8328 fieldData, 8329 info[table].control_reg, 8330 SOC_INVALID_TCAM_PARITY_BIT, 8331 info[table].enable_field, 8332 mem, EVEN_PARITYf, blk, 8333 block_port, _SOC_ACC_TYPE_PIPE_ANY, 8334 index, &test_data); 8335 } 8336 /*Disable parity*/ 8337 SOC_IF_ERROR_RETURN(_ser_test_parity_control( 8338 unit, &test_data, 0)); 8339 /*Read the memory for successful injection*/ 8340 SOC_IF_ERROR_RETURN(ser_test_mem_read( 8341 unit, 0, &test_data)); 8342 /*Inject error*/ 8343 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full( 8344 unit, flags, &test_data)); 8345 /*Enable parity*/ 8346 SOC_IF_ERROR_RETURN(_ser_test_parity_control( 8347 unit, &test_data, 1)); 8348 } 8349 8350 return SOC_E_NONE; 8351 } 8352 } 8353 } 8354 } 8355 } 8356 8357 /* The tested memory is not found in SER enabled list, can't inject error of it */ 8358 return SOC_E_UNAVAIL; 8359 } 8360 8361 STATIC soc_error_t 8362 _ser_gh_ser_error_injection_support(int unit, soc_mem_t mem, 8363 int pipe_target) 8364 { 8365 int rv = SOC_E_UNAVAIL; 8366 int i = 0, hw_enable_ix = 0; 8367 int group = 0, table = 0, overlay_mem = 0; 8368 uint32 range_enable; 8369 soc_mem_t memTable; 8370 soc_port_t block_port; 8371 soc_block_t blk; 8372 _soc_generic_ser_info_t *tcam_ser_info; 8373 _soc_gh_parity_group_info_t *parity_group_info; 8374 _soc_gh_parity_info_t *info; 8375 8376 LOG_VERBOSE(BSL_LS_SOC_SER, 8377 (BSL_META_U(unit, 8378 "unit %d, mem %s, pipe_target %d\n"), 8379 unit, SOC_MEM_NAME(unit,mem), pipe_target)); 8380 8381 if (!SOC_MEM_IS_VALID(unit, mem)) { 8382 LOG_ERROR(BSL_LS_SOC_COMMON, 8383 (BSL_META_U(unit, 8384 "unit %d, mem %d is INVALID or not valid " 8385 "for this unit !!\n"), 8386 unit, mem)); 8387 return rv; 8388 } 8389 8390 tcam_ser_info = _soc_gh_tcam_ser_info[unit]; 8391 8392 /* Search TCAMs */ 8393 if (tcam_ser_info != NULL) { 8394 8395 /* Check if enable */ 8396 SOC_IF_ERROR_RETURN 8397 (READ_SER_RANGE_ENABLEr(unit, &range_enable)); 8398 LOG_DEBUG(BSL_LS_SOC_SER, 8399 (BSL_META_U(unit, 8400 "Search TCAMs: SER_RANGE_ENABLE 0x%X\n"), 8401 range_enable)); 8402 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 8403 if (tcam_ser_info[i].mem == mem) { 8404 hw_enable_ix = tcam_ser_info[i].ser_hw_index; 8405 LOG_DEBUG(BSL_LS_SOC_SER, 8406 (BSL_META_U(unit, 8407 "SER Range HW Enable index %d\n"), 8408 hw_enable_ix)); 8409 if (((range_enable >> hw_enable_ix) & 0x1) == 0) { 8410 LOG_WARN(BSL_LS_SOC_SER, 8411 (BSL_META_U(unit, 8412 "matched mem but SER detection is disabled\n" 8413 "SER_RANGE_ENABLE 0x%X, SER Range HW index %d\n"), 8414 range_enable,hw_enable_ix)); 8415 return rv; /* matched mem but ser_detection is disabled */ 8416 } 8417 LOG_VERBOSE(BSL_LS_SOC_SER, 8418 (BSL_META_U(unit, 8419 "TCAM found\n"))); 8420 return SOC_E_NONE; /* found */ 8421 } 8422 } 8423 } 8424 8425 parity_group_info = _soc_gh_parity_group_info[unit]; 8426 8427 /* Search H/W memory */ 8428 if (parity_group_info != NULL) { 8429 for (group = 0; parity_group_info[group].cpi_bit; group++) { 8430 info = parity_group_info[group].info; 8431 8432 SOC_BLOCK_ITER(unit, blk, 8433 parity_group_info[group].blocktype) { 8434 if (_soc_greyhound_parity_block_port(unit, blk, 8435 &block_port) < 0) { 8436 continue; 8437 } 8438 8439 for (table = 0; info[table].error_field != INVALIDf; table++) { 8440 memTable = info[table].mem; 8441 if (memTable == INVALIDm) { 8442 continue; 8443 } 8444 if (_soc_greyhound_ser_mem_skip(unit, info[table].feature)) { 8445 continue; 8446 } 8447 /* Check if overlay memory */ 8448 for (i=0; soc_ser_gh_overlay_mems[i].mem != INVALIDm; i++) { 8449 if ((soc_ser_gh_overlay_mems[i].mem == mem) && 8450 (soc_ser_gh_overlay_mems[i].base_mem == memTable)) { 8451 overlay_mem = 1; 8452 LOG_DEBUG(BSL_LS_SOC_SER, 8453 (BSL_META_U(unit, 8454 "mem %s base_mem %s\n"), 8455 SOC_MEM_NAME(unit,mem),SOC_MEM_NAME(unit,memTable))); 8456 break; 8457 } 8458 } 8459 if ((memTable == mem) || (overlay_mem)) { 8460 LOG_VERBOSE(BSL_LS_SOC_SER, 8461 (BSL_META_U(unit, 8462 "H/W memory found\n"))); 8463 return SOC_E_NONE; /* found */ 8464 } 8465 } 8466 } 8467 } 8468 } 8469 8470 /* The tested memory is not found in SER enabled list */ 8471 return rv; 8472 } 8473 8474 void 8475 soc_gh_ser_test_register(int unit) 8476 { 8477 /*Initialize chip-specific functions for SER testing*/ 8478 memset(&ser_gh_test_fun, 0, sizeof(soc_ser_test_functions_t)); 8479 ser_gh_test_fun.inject_error_f = &soc_gh_ser_inject_error; 8480 ser_gh_test_fun.test_mem = &soc_gh_ser_mem_test; 8481 ser_gh_test_fun.test = &soc_gh_ser_test; 8482 ser_gh_test_fun.injection_support = &_ser_gh_ser_error_injection_support; 8483 8484 soc_ser_test_functions_register(unit, &ser_gh_test_fun); 8485 } 8486 #endif /* SER_TR_TEST_SUPPORT */ 8487 8488 /* To write to PGW_GX_CONFIG or PGW_XL_CONFIG register on indicated field */ 8489 int 8490 soc_greyhound_pgw_encap_field_modify(int unit, 8491 soc_port_t lport, 8492 soc_field_t field, 8493 uint32 val) 8494 { 8495 int chk_pgwgx = 0,reg_blk = 0,pindex = -1; 8496 int pport = SOC_INFO(unit).port_l2p_mapping[lport]; 8497 8498 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_GXPORT) { 8499 /* need to avoid the set been applied to QSGMII port! 8500 * - QSGMII p2-p5 belong to GXPORT block but not proper for encap set. 8501 */ 8502 chk_pgwgx = soc_greyhound_pgw_reg_blk_index_get(unit, 8503 PGW_GX_CONFIGr, lport, NULL, ®_blk, &pindex, 0); 8504 if (chk_pgwgx > 0){ 8505 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8506 PGW_GX_CONFIGr, lport, field, val)); 8507 } else { 8508 return SOC_E_UNAVAIL; 8509 } 8510 } else if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_XLPORT) { 8511 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8512 PGW_XL_CONFIGr, lport, field, val)); 8513 } else { 8514 return SOC_E_UNAVAIL; 8515 } 8516 8517 return SOC_E_NONE; 8518 } 8519 8520 /* To get from PGW_GX_CONFIG or PGW_XL_CONFIG register on indicated field */ 8521 int 8522 soc_greyhound_pgw_encap_field_get(int unit, 8523 soc_port_t lport, 8524 soc_field_t field, 8525 uint32 *val) 8526 { 8527 int chk_pgwgx = 0,reg_blk = 0,pindex = -1; 8528 uint32 reg_val = 0; 8529 int pport = SOC_INFO(unit).port_l2p_mapping[lport]; 8530 8531 *val = 0; 8532 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_GXPORT) { 8533 /* need to avoid the get to QSGMII port! 8534 * - QSGMII p2-p5 belong to GXPORT block but not proper for encap get. 8535 */ 8536 chk_pgwgx = soc_greyhound_pgw_reg_blk_index_get(unit, 8537 PGW_GX_CONFIGr, lport, NULL, ®_blk, &pindex, 0); 8538 if (chk_pgwgx > 0){ 8539 SOC_IF_ERROR_RETURN(READ_PGW_GX_CONFIGr(unit, lport, ®_val)); 8540 *val = soc_reg_field_get(unit, PGW_GX_CONFIGr, reg_val, field); 8541 } else { 8542 return SOC_E_UNAVAIL; 8543 } 8544 } else if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_XLPORT) { 8545 SOC_IF_ERROR_RETURN(READ_PGW_XL_CONFIGr(unit, lport, ®_val)); 8546 *val = soc_reg_field_get(unit, PGW_XL_CONFIGr, reg_val, field); 8547 } else { 8548 return SOC_E_UNAVAIL; 8549 } 8550 8551 return SOC_E_NONE; 8552 } 8553 8554 8555 /* 8556 * soc_gh_eee_timers_setup : 8557 * - EEE timers in different MAC noramlly has it own reset default but need 8558 * other proper value per device. 8559 * - EEE timer is speed dependent. 8560 */ 8561 int 8562 soc_gh_port_eee_timers_setup(int unit, soc_port_t port, int speed) 8563 { 8564 uint32 wake_timer = 0, lpi_timer = 0; 8565 8566 /* Native EEE feature supporting for UNIMAC/XLMAC: 8567 * - Assigning proper EEE timer to work with Ext-PHY 8568 * - Wake timer : 8569 * a. Speed 100 : 30 us 8570 * b. Speed 1G : 16.5 us 8571 * c. Speed 10G : 7.6 us 8572 * - Delay Entry timer : 8573 * a. Speed 00 : 40 us 8574 * b. Speed 1G : 4 us 8575 * c. Speed 10G : f0.4 us 8576 * 8577 * NOTE : 8578 * 1. Ext-PHY with EEE support speed in 100/1G/10G currently. 8579 */ 8580 8581 /* EEE wake timer (unit of uSec.) */ 8582 wake_timer = ((speed >= 10000) ? 7 : 8583 ((speed >= 1000) ? 17 : 30)); 8584 /* EEE dealy entry timer (unit of uSec.) */ 8585 lpi_timer = ((speed >= 10000) ? 1 : 8586 ((speed >= 1000) ? 4 : 40)); 8587 8588 if (IS_XL_PORT(unit, port)) { 8589 /* TSC-E mode : for XLMAC seting */ 8590 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8591 XLMAC_EEE_TIMERSr, port, EEE_WAKE_TIMERf, wake_timer)); 8592 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8593 XLMAC_EEE_TIMERSr, port, EEE_DELAY_ENTRY_TIMERf, lpi_timer)); 8594 } else { 8595 /* QSGMII-E mode : for UNIMAC setting 8596 * 8597 * INFO : UNIMAC EEE timer per 8598 */ 8599 /* GE speed EEE timer (unit of uSec.) */ 8600 wake_timer = 17; 8601 lpi_timer = 4; 8602 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8603 GMII_EEE_WAKE_TIMERr, port, 8604 GMII_EEE_WAKE_TIMERf, wake_timer)); 8605 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8606 GMII_EEE_DELAY_ENTRY_TIMERr, port, 8607 GMII_EEE_LPI_TIMERf, lpi_timer)); 8608 /* FE speed EEE timer (unit of uSec.) */ 8609 wake_timer = 30; 8610 lpi_timer = 40; 8611 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8612 MII_EEE_WAKE_TIMERr, port, 8613 MII_EEE_WAKE_TIMERf, wake_timer)); 8614 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8615 MII_EEE_DELAY_ENTRY_TIMERr, port, 8616 MII_EEE_LPI_TIMERf, lpi_timer)); 8617 } 8618 return SOC_E_NONE; 8619 } 8620 8621 /* EEE reference count init : 8622 * - The assignment of EEE_REF_COUNT and EEE Wake/LPI timer 8623 */ 8624 int 8625 soc_gh_port_eee_ref_count_init(int unit, soc_port_t port) 8626 { 8627 /* assigning EEE_REF_COUNT */ 8628 if (IS_XL_PORT(unit, port)) { 8629 /* TSC-E mode : for XLMAC EEE_REF_COUNT */ 8630 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8631 XLMAC_EEE_TIMERSr, port, EEE_REF_COUNTf, 8632 GH_XLMAC_EEE_REF_CNT)); 8633 } else { 8634 /* QSGMII-E mode : for UNIMAC EEE_REF_COUNT */ 8635 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 8636 UMAC_EEE_REF_COUNTr, port, EEE_REF_COUNTf, 8637 GH_UNIMAC_EEE_REF_CNT)); 8638 } 8639 return SOC_E_NONE; 8640 } 8641 8642 /* 8643 * Greyhound chip driver functions. 8644 */ 8645 soc_functions_t soc_greyhound_drv_funs = { 8646 _soc_greyhound_misc_init, 8647 _soc_greyhound_mmu_init, 8648 _soc_greyhound_age_timer_get, 8649 _soc_greyhound_age_timer_max_get, 8650 _soc_greyhound_age_timer_set, 8651 _soc_greyhound_tsce_firmware_set, 8652 _soc_greyhound_mdio_reg_read, 8653 _soc_greyhound_mdio_reg_write, 8654 }; 8655 8656 #endif /* BCM_GREYHOUND_SUPPORT */