firebolt.c (99867B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: firebolt.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <sal/core/boot.h> 14 #include <shared/bsl.h> 15 #include <soc/firebolt.h> 16 #include <soc/drv.h> 17 #include <soc/mem.h> 18 #include <soc/hash.h> 19 #include <soc/lpm.h> 20 #include <soc/error.h> 21 #include <soc/phyctrl.h> 22 #include <soc/debug.h> 23 #ifdef BCM_RAVEN_SUPPORT 24 #include <soc/post.h> 25 #endif /* BCM_RAVEN_SUPPORT */ 26 27 #ifdef BCM_FIREBOLT_SUPPORT 28 29 /* 30 * firebolt chip driver functions. 31 */ 32 soc_functions_t soc_firebolt_drv_funs = { 33 soc_firebolt_misc_init, 34 soc_firebolt_mmu_init, 35 soc_firebolt_age_timer_get, 36 soc_firebolt_age_timer_max_get, 37 soc_firebolt_age_timer_set, 38 }; 39 40 static soc_ser_functions_t _fb_ser_functions; 41 42 STATIC int 43 soc_firebolt_cam_sam_config(int unit, int sam) 44 { 45 uint32 val; 46 47 SOC_IF_ERROR_RETURN(READ_L2_USER_ENTRY_CAM_CONTROLr(unit, &val)); 48 soc_reg_field_set(unit, L2_USER_ENTRY_CAM_CONTROLr, &val, SAMf, sam); 49 SOC_IF_ERROR_RETURN(WRITE_L2_USER_ENTRY_CAM_CONTROLr(unit, val)); 50 51 SOC_IF_ERROR_RETURN(READ_L3_TUNNEL_CAM_CONTROLr(unit, &val)); 52 soc_reg_field_set(unit, L3_TUNNEL_CAM_CONTROLr, &val, SAMf, sam); 53 SOC_IF_ERROR_RETURN(WRITE_L3_TUNNEL_CAM_CONTROLr(unit, val)); 54 55 SOC_IF_ERROR_RETURN(READ_VLAN_SUBNET_CAM_CONTROLr(unit, &val)); 56 soc_reg_field_set(unit, VLAN_SUBNET_CAM_CONTROLr, &val, SAMf, sam); 57 SOC_IF_ERROR_RETURN(WRITE_VLAN_SUBNET_CAM_CONTROLr(unit, val)); 58 59 SOC_IF_ERROR_RETURN(READ_L3_DEFIP_CAM_CONTROL0r(unit, &val)); 60 soc_reg_field_set(unit, L3_DEFIP_CAM_CONTROL0r, &val, CAM0_SAMf, sam); 61 soc_reg_field_set(unit, L3_DEFIP_CAM_CONTROL0r, &val, CAM1_SAMf, sam); 62 soc_reg_field_set(unit, L3_DEFIP_CAM_CONTROL0r, &val, CAM2_SAMf, sam); 63 soc_reg_field_set(unit, L3_DEFIP_CAM_CONTROL0r, &val, CAM3_SAMf, sam); 64 soc_reg_field_set(unit, L3_DEFIP_CAM_CONTROL0r, &val, CAM4_SAMf, sam); 65 soc_reg_field_set(unit, L3_DEFIP_CAM_CONTROL0r, &val, CAM5_SAMf, sam); 66 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_CONTROL0r(unit, val)); 67 68 SOC_IF_ERROR_RETURN(READ_FP_CAM_CONTROL_LOWERr(unit, &val)); 69 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 70 FP_CAM_CONTROL_SLICE_0f, sam); 71 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 72 FP_CAM_CONTROL_SLICE_1f, sam); 73 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 74 FP_CAM_CONTROL_SLICE_2f, sam); 75 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 76 FP_CAM_CONTROL_SLICE_3f, sam); 77 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 78 FP_CAM_CONTROL_SLICE_4f, sam); 79 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 80 FP_CAM_CONTROL_SLICE_5f, sam); 81 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 82 FP_CAM_CONTROL_SLICE_6f, sam); 83 soc_reg_field_set(unit, FP_CAM_CONTROL_LOWERr, &val, 84 FP_CAM_CONTROL_SLICE_7f, sam); 85 SOC_IF_ERROR_RETURN(WRITE_FP_CAM_CONTROL_LOWERr(unit, val)); 86 87 SOC_IF_ERROR_RETURN(READ_FP_CAM_CONTROL_UPPERr(unit, &val)); 88 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 89 FP_CAM_CONTROL_SLICE_8f, sam); 90 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 91 FP_CAM_CONTROL_SLICE_9f, sam); 92 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 93 FP_CAM_CONTROL_SLICE_10f, sam); 94 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 95 FP_CAM_CONTROL_SLICE_11f, sam); 96 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 97 FP_CAM_CONTROL_SLICE_12f, sam); 98 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 99 FP_CAM_CONTROL_SLICE_13f, sam); 100 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 101 FP_CAM_CONTROL_SLICE_14f, sam); 102 soc_reg_field_set(unit, FP_CAM_CONTROL_UPPERr, &val, 103 FP_CAM_CONTROL_SLICE_15f, sam); 104 SOC_IF_ERROR_RETURN(WRITE_FP_CAM_CONTROL_UPPERr(unit, val)); 105 106 return SOC_E_NONE; 107 } 108 STATIC int 109 soc_firebolt_pipe_mem_clear(int unit) 110 { 111 uint32 rval; 112 int pipe_init_usec; 113 soc_timeout_t to; 114 115 /* 116 * Reset the IPIPE and EPIPE block 117 */ 118 rval = 0; 119 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 120 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 121 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 122 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x4000); 123 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 124 125 rval = 0; 126 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 127 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 128 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 129 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x2000); 130 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 131 132 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 133 if (SAL_BOOT_SIMULATION) { 134 pipe_init_usec = 10000000; 135 } else { 136 pipe_init_usec = 50000; 137 } 138 soc_timeout_init(&to, pipe_init_usec, 0); 139 140 /* Wait for IPIPE memory initialization done. */ 141 do { 142 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 143 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 144 break; 145 } 146 if (soc_timeout_check(&to)) { 147 LOG_WARN(BSL_LS_SOC_COMMON, 148 (BSL_META_U(unit, 149 "unit %d : ING_HW_RESET timeout\n"), unit)); 150 break; 151 } 152 } while (TRUE); 153 154 /* Wait for EPIPE memory initialization done. */ 155 do { 156 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 157 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 158 break; 159 } 160 if (soc_timeout_check(&to)) { 161 LOG_WARN(BSL_LS_SOC_COMMON, 162 (BSL_META_U(unit, 163 "unit %d : EGR_HW_RESET timeout\n"), unit)); 164 break; 165 } 166 } while (TRUE); 167 168 rval = 0; 169 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 170 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 171 172 return SOC_E_NONE; 173 } 174 175 #if defined (BCM_FIREBOLT2_SUPPORT) 176 /* SER processing for TCAMs */ 177 STATIC _soc_ser_parity_info_t _soc_fb2_ser_parity_info[] = { 178 { EFP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 179 -1, -1, -1, -1, 180 -1, 370, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_SW_COMPARE}, 181 { FP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 182 -1, -1, -1, -1, 183 -1, 370, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_SW_COMPARE}, 184 { VFP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 185 -1, -1, -1, -1, 186 -1, 370, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_SW_COMPARE}, 187 { L3_TUNNELm, _SOC_SER_PARITY_MODE_2BITS, 188 -1, -1, -1, -1, 189 -1, 183, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_SW_COMPARE}, 190 { VLAN_SUBNETm, _SOC_SER_PARITY_MODE_2BITS, 191 -1, -1, -1, -1, 192 -1, 144, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_SW_COMPARE}, 193 { INVALIDm, _SOC_SER_PARITY_MODE_NUM}, 194 }; 195 196 #endif /* BCM_FIREBOLT2_SUPPORT */ 197 198 #ifdef SOC_MEM_L3_DEFIP_WAR 199 /* 200 * Support to map out unused blocks in L3_DEFIP Table 201 */ 202 #define L3_DEFIP_CAM_NUM_INSTANCE 6 203 /* 204 * L3_DEFIP CAM BIST 205 */ 206 STATIC int 207 soc_fb_l3_defip_bist(int unit, int instance) 208 { 209 static int bist_enf[L3_DEFIP_CAM_NUM_INSTANCE] = { 210 BIST_EN0f, 211 BIST_EN1f, 212 BIST_EN2f, 213 BIST_EN3f, 214 BIST_EN4f, 215 BIST_EN5f 216 }; 217 /* 218 static int cam_samf[L3_DEFIP_CAM_NUM_INSTANCE] = 219 { CAM0_SAMf, 220 CAM1_SAMf, 221 CAM2_SAMf, 222 CAM3_SAMf, 223 CAM4_SAMf, 224 CAM5_SAMf 225 }; 226 */ 227 static int cam_bist_statr[] = { 228 L3_DEFIP_CAM_BIST_S2_STATUSr, 229 L3_DEFIP_CAM_BIST_S3_STATUSr, 230 L3_DEFIP_CAM_BIST_S5_STATUSr, 231 L3_DEFIP_CAM_BIST_S6_STATUSr, 232 L3_DEFIP_CAM_BIST_S8_STATUSr, 233 L3_DEFIP_CAM_BIST_S10_STATUSr, 234 INVALIDr 235 }; 236 uint32 cam_stat = 0; 237 uint32 cam_ctrl = 0; 238 int i; 239 int rv = SOC_E_NONE; 240 soc_timeout_t to; 241 242 if (SAL_BOOT_SIMULATION) { 243 return SOC_E_NONE; 244 } 245 246 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_CONTROL1r(unit, cam_ctrl)); 247 248 /* Enable BIST */ 249 soc_reg_field_set(unit, 250 L3_DEFIP_CAM_CONTROL1r, 251 &cam_ctrl, 252 bist_enf[instance], 253 1); 254 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_CONTROL1r(unit, cam_ctrl)); 255 256 /* Poll for BIST done */ 257 soc_timeout_init(&to, 50000, 0); /* 50 msec */ 258 do { 259 SOC_IF_ERROR_RETURN(READ_L3_DEFIP_CAM_BIST_STATUSr(unit, &cam_stat)); 260 if (soc_reg_field_get(unit, L3_DEFIP_CAM_BIST_STATUSr, 261 cam_stat, BIST_DONEf)) { 262 break; 263 } 264 if (soc_timeout_check(&to)) { 265 LOG_WARN(BSL_LS_SOC_COMMON, 266 (BSL_META_U(unit, 267 "unit %d : DEFIP_CAM_BIST timeout\n"), unit)); 268 rv = SOC_E_INTERNAL; 269 goto done; 270 } 271 } while (TRUE); 272 273 for(i = 0; cam_bist_statr[i] != INVALIDr; i++) { 274 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, cam_bist_statr[i], 275 REG_PORT_ANY, 0, 276 &cam_stat)); 277 if (cam_stat != 0) { 278 rv = SOC_E_INTERNAL; 279 goto done; 280 } 281 } 282 283 done: 284 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_CONTROL1r(unit, 0)); 285 return rv; 286 } 287 288 #define spn_L3_DEFIP_MAP "l3_defip_map" 289 290 /* 291 * Resize the L3_DEFIP tables to account for unused Blocks 292 */ 293 STATIC int 294 soc_fb_l3_defip_resize(int unit) 295 { 296 soc_persist_t *sop = SOC_PERSIST(unit); 297 int i; 298 int unused_count = 0; 299 uint32 cam_en = 0; 300 uint32 l3_defip_map = 0; 301 static int cam_enf[L3_DEFIP_CAM_NUM_INSTANCE] = 302 { CAM_0_ENABLEf, 303 CAM_1_ENABLEf, 304 CAM_2_ENABLEf, 305 CAM_3_ENABLEf, 306 CAM_4_ENABLEf, 307 CAM_5_ENABLEf 308 }; 309 310 /* Use all instances by deafult */ 311 sop->l3_defip_map = soc_property_get(unit, spn_L3_DEFIP_MAP, 0x00); 312 313 /* 314 * If config property is not specified the use SAM = 3 and do not 315 * resize the DEFIP Table 316 */ 317 if ((soc_property_get(unit, spn_L3_DEFIP_MAP, 0xFF) == 0xFF) && 318 (soc_property_get(unit, spn_L3_DEFIP_MAP, 0xF0) == 0xF0)) { 319 return SOC_E_NONE; 320 } 321 322 /* Always use SAM = 0 */ 323 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_CONTROL0r(unit, 0)); 324 325 for(i = 0; i < L3_DEFIP_CAM_NUM_INSTANCE; i++) { 326 if (soc_fb_l3_defip_bist(unit, i) < 0) { 327 LOG_ERROR(BSL_LS_SOC_COMMON, 328 (BSL_META_U(unit, 329 "unit = %d, Recommend Mapping out L3_DEFIP block %d\n"), 330 unit, i)); 331 l3_defip_map |= (1 << i); 332 } 333 if (sop->l3_defip_map & (1 << i)) { /* Map out the instance */ 334 LOG_ERROR(BSL_LS_SOC_COMMON, 335 (BSL_META_U(unit, 336 "unit = %d, Mapped out L3_DEFIP block %d\n"), 337 unit, i)); 338 unused_count++; 339 continue; 340 } 341 soc_reg_field_set(unit, 342 L3_DEFIP_CAM_ENABLEr, 343 &cam_en, 344 cam_enf[i], 345 1); 346 } 347 LOG_ERROR(BSL_LS_SOC_COMMON, 348 (BSL_META_U(unit, 349 "Recommend config add %s.%d=0x%02x); config save\n"), 350 spn_L3_DEFIP_MAP, unit, l3_defip_map)); 351 352 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_ENABLEr(unit, cam_en)); 353 sop->memState[L3_DEFIPm].index_max = 354 SOC_MEM_INFO(unit, L3_DEFIPm).index_max - 355 (unused_count << 10); 356 sop->memState[L3_DEFIP_ONLYm].index_max = 357 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 358 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 359 sop->memState[L3_DEFIPm].index_max; 360 361 return SOC_E_NONE; 362 } 363 364 /* 365 * Map an index in L3_DEFIP to the real h/w index to make by jumping over 366 * unused 1K blocks to make the table appear contiguous 367 */ 368 369 int 370 soc_fb_l3_defip_index_map(int unit, int index) 371 { 372 uint32 map = SOC_PERSIST(unit)->l3_defip_map; 373 int offset; 374 int good_block; 375 376 good_block = 0; 377 offset = -1; 378 do { 379 offset++; 380 if (map & (1 << offset)) { 381 continue; 382 } 383 good_block++; 384 } while(good_block <= (index >> 10)); 385 386 return(index + ((offset + 1 - good_block) << 10)); 387 } 388 #endif 389 390 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_RAVEN_SUPPORT) 391 int 392 soc_raptor_hw_linkscan_map_init(int unit) 393 { 394 soc_port_t port; 395 uint32 oregv = 0; 396 uint32 regv = 0; 397 soc_reg_t reg = CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0r; 398 soc_reg_t map_r[16] = { CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0r, 399 CMIC_MIIM_EXT_PHY_ADDR_MAP_7_4r, 400 CMIC_MIIM_EXT_PHY_ADDR_MAP_11_8r, 401 CMIC_MIIM_EXT_PHY_ADDR_MAP_15_12r, 402 CMIC_MIIM_EXT_PHY_ADDR_MAP_19_16r, 403 CMIC_MIIM_EXT_PHY_ADDR_MAP_23_20r, 404 CMIC_MIIM_EXT_PHY_ADDR_MAP_27_24r, 405 CMIC_MIIM_EXT_PHY_ADDR_MAP_31_28r, 406 CMIC_MIIM_EXT_PHY_ADDR_MAP_35_32r, 407 CMIC_MIIM_EXT_PHY_ADDR_MAP_39_36r, 408 CMIC_MIIM_EXT_PHY_ADDR_MAP_43_40r, 409 CMIC_MIIM_EXT_PHY_ADDR_MAP_47_44r, 410 CMIC_MIIM_EXT_PHY_ADDR_MAP_51_48r, 411 CMIC_MIIM_EXT_PHY_ADDR_MAP_55_52r, 412 CMIC_MIIM_EXT_PHY_ADDR_MAP_59_56r, 413 CMIC_MIIM_EXT_PHY_ADDR_MAP_63_60r 414 }; 415 soc_field_t map_f[4] = { PHY_ID_0f, PHY_ID_1f, PHY_ID_2f, PHY_ID_3f}; 416 417 /* Re-initialize the phy port map for the unit */ 418 PBMP_PORT_ITER(unit, port) { 419 /* Use MDIO address re-mapping for hardware linkscan */ 420 assert((uint32)(port / 4) < (sizeof(map_r)/sizeof(map_r[0]))); 421 reg = map_r[port / 4]; 422 regv = soc_pci_read(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0)); 423 oregv = regv; 424 soc_reg_field_set(unit, 425 CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0r, 426 ®v, map_f[port % 4], 427 PHY_ADDR(unit, port) & 0x1f); 428 if (oregv != regv) { 429 soc_pci_write(unit, 430 soc_reg_addr(unit, reg, REG_PORT_ANY, 0), 431 regv); 432 } 433 434 } 435 /* coverity[result_independent_of_operands] */ 436 SOC_IF_ERROR_RETURN(READ_CMIC_CONFIGr(unit, ®v)); 437 oregv = regv; 438 soc_reg_field_set(unit, CMIC_CONFIGr, ®v, MIIM_ADDR_MAP_ENABLEf, 1); 439 if (oregv != regv) { 440 WRITE_CMIC_CONFIGr(unit, regv); 441 } 442 443 return SOC_E_NONE; 444 } 445 #endif 446 447 448 int 449 soc_firebolt_misc_init(int unit) 450 { 451 uint32 rval, orval, prev_reg_addr; 452 int port; 453 uint32 imask; 454 uint32 misc_cfg; 455 int divisor, dividend; 456 457 #if defined(BCM_HAWKEYE_SUPPORT) 458 if(SOC_IS_HAWKEYE(unit)) { 459 /* Disable HW based idle mode power down feature by default */ 460 if (soc_reg_field_valid(unit, CMIC_QGPHY_QSGMII_CONTROLr, DISABLE_HW_IDLE_PWRDWNf)) { 461 /* coverity[result_independent_of_operands] */ 462 SOC_IF_ERROR_RETURN(READ_CMIC_QGPHY_QSGMII_CONTROLr(unit, &rval)); 463 soc_reg_field_set(unit, 464 CMIC_QGPHY_QSGMII_CONTROLr, 465 &rval, 466 DISABLE_HW_IDLE_PWRDWNf, 467 1); 468 SOC_IF_ERROR_RETURN(WRITE_CMIC_QGPHY_QSGMII_CONTROLr(unit, rval)); 469 } 470 471 /* 472 * To set bit ECO_EEE_LINKUP_CONFIG_EN to 0. 473 * This is for SW one second delay on HKEEE, 474 * and this needs to happen before PHY is enabled to negotiate the link. 475 * Otherwise, the EEE_DELAY_ENTRY_TIMER could be wrong sometimes. 476 */ 477 PBMP_PORT_ITER(unit, port) { 478 if(SOC_IS_HAWKEYE(unit) && soc_feature(unit, soc_feature_eee)) { 479 SOC_IF_ERROR_RETURN( 480 READ_UMAC_EEE_CTRLr(unit, port, &rval)); 481 soc_reg_field_set(unit, UMAC_EEE_CTRLr, &rval, 482 ECO_EEE_LINKUP_CONFIG_ENf, 0); 483 SOC_IF_ERROR_RETURN( 484 WRITE_UMAC_EEE_CTRLr(unit, port, rval)); 485 } 486 } 487 488 /* Enable fp slice */ 489 SOC_IF_ERROR_RETURN(READ_FP_SLICE_ENABLEr(unit, &rval)); 490 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_SLICE_ENABLE_SLICE_0f, 1); 491 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_SLICE_ENABLE_SLICE_1f, 1); 492 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_SLICE_ENABLE_SLICE_2f, 1); 493 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_SLICE_ENABLE_SLICE_3f, 1); 494 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_LOOKUP_ENABLE_SLICE_0f, 1); 495 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_LOOKUP_ENABLE_SLICE_1f, 1); 496 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_LOOKUP_ENABLE_SLICE_2f, 1); 497 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, FP_LOOKUP_ENABLE_SLICE_3f, 1); 498 SOC_IF_ERROR_RETURN(WRITE_FP_SLICE_ENABLEr(unit, rval)); 499 500 SOC_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 501 soc_reg_field_set(unit, ING_MISC_CONFIGr, &rval, USE_EPC_LINK_BMPf, 1); 502 SOC_IF_ERROR_RETURN(WRITE_ING_MISC_CONFIGr(unit, rval)); 503 PBMP_ALL_ITER(unit, port) { 504 SOC_IF_ERROR_RETURN(READ_EGR_ENABLEr(unit, port, &rval)); 505 soc_reg_field_set(unit, EGR_ENABLEr, &rval, PRT_ENABLEf, 1); 506 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEr(unit, port, rval)); 507 } 508 SOC_IF_ERROR_RETURN(READ_EGR_ENABLE_SELECTr(unit, &rval)); 509 soc_reg_field_set(unit, EGR_ENABLE_SELECTr, &rval, ENABLE_SELECTf, 1); 510 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLE_SELECTr(unit, rval)); 511 512 /* Set test mode bits to 0x10 for all FP TCAM */ 513 rval = 0x10; 514 SOC_IF_ERROR_RETURN(WRITE_FP_NON_ROTATED_CAM_CONTROLr(unit, rval)); 515 SOC_IF_ERROR_RETURN(WRITE_FP_ROTATED_CAM_CONTROLr(unit, rval)); 516 /* QSGMII Pause Work aroud */ 517 rval = 0x0; 518 SOC_IF_ERROR_RETURN(WRITE_CMIC_TX_PAUSE_CAPABILITYr(unit, rval)); 519 SOC_IF_ERROR_RETURN(WRITE_CMIC_RX_PAUSE_CAPABILITYr(unit, rval)); 520 rval = 0xffffffff; /* all pbmp */ 521 /* coverity[result_independent_of_operands] */ 522 SOC_IF_ERROR_RETURN(WRITE_CMIC_TX_PAUSE_OVERRIDE_CONTROLr(unit, rval)); 523 SOC_IF_ERROR_RETURN(WRITE_CMIC_RX_PAUSE_OVERRIDE_CONTROLr(unit, rval)); 524 } 525 #endif 526 527 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAVEN_SUPPORT) 528 if (SOC_IS_FIREBOLT2(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 529 soc_persist_t *sop; 530 uint32 entry_mask; 531 532 sop = SOC_PERSIST(unit); 533 534 /* This is really a bucket mask */ 535 entry_mask = sop->memState[L2_HITDA_ONLYm].index_max; 536 SOC_IF_ERROR_RETURN(WRITE_L2_ENTRY_ADDR_MASKr(unit, entry_mask)); 537 538 if (SOC_REG_IS_VALID(unit, L3_ENTRY_ADDR_MASKr)) { 539 /* This is really a bucket mask */ 540 entry_mask = sop->memState[L3_ENTRY_VALID_ONLYm].index_max; 541 SOC_IF_ERROR_RETURN(WRITE_L3_ENTRY_ADDR_MASKr(unit, entry_mask)); 542 } 543 544 if (SOC_REG_IS_VALID(unit, VLAN_STG_ADDR_MASKr)) { 545 entry_mask = sop->memState[STG_TABm].index_max; 546 SOC_IF_ERROR_RETURN(WRITE_VLAN_STG_ADDR_MASKr(unit, entry_mask)); 547 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_STG_ADDR_MASKr(unit, entry_mask)); 548 } 549 } 550 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAVEN_SUPPORT */ 551 552 #if defined (BCM_FIREBOLT2_SUPPORT) 553 if (SOC_IS_FIREBOLT2(unit)) { 554 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_stop(unit)); 555 } 556 #endif 557 558 if (soc_feature(unit, soc_feature_l2x_parity)) { 559 /* Enable L2_ENTRY/L3_ENTRY parity error interrupt */ 560 SOC_IF_ERROR_RETURN(READ_L2_ENTRY_PARITY_CONTROLr(unit, &rval)); 561 orval = rval; 562 soc_reg_field_set(unit, L2_ENTRY_PARITY_CONTROLr, &rval, 563 PARITY_IRQ_ENf, 0); 564 if (orval != rval) { 565 SOC_IF_ERROR_RETURN(WRITE_L2_ENTRY_PARITY_CONTROLr(unit, rval)); 566 } 567 soc_reg_field_set(unit, L2_ENTRY_PARITY_CONTROLr, &rval, 568 PARITY_ENf, 1); 569 soc_reg_field_set(unit, L2_ENTRY_PARITY_CONTROLr, &rval, 570 PARITY_IRQ_ENf, 1); 571 SOC_IF_ERROR_RETURN(WRITE_L2_ENTRY_PARITY_CONTROLr(unit, rval)); 572 } 573 574 #if defined(INCLUDE_L3) 575 if (soc_feature(unit, soc_feature_l3x_parity)) { 576 SOC_IF_ERROR_RETURN(READ_L3_ENTRY_PARITY_CONTROLr(unit, &rval)); 577 soc_reg_field_set(unit, L3_ENTRY_PARITY_CONTROLr, &rval, 578 PARITY_IRQ_ENf, 0); 579 SOC_IF_ERROR_RETURN(WRITE_L3_ENTRY_PARITY_CONTROLr(unit, rval)); 580 soc_reg_field_set(unit, L3_ENTRY_PARITY_CONTROLr, &rval, 581 PARITY_ENf, 1); 582 soc_reg_field_set(unit, L3_ENTRY_PARITY_CONTROLr, &rval, 583 PARITY_IRQ_ENf, 1); 584 SOC_IF_ERROR_RETURN(WRITE_L3_ENTRY_PARITY_CONTROLr(unit, rval)); 585 } 586 #endif /* INCLUDE_L3 */ 587 588 if (soc_feature(unit, soc_feature_l3defip_parity)) { 589 /* Enable L3_DEFIP parity error interrupt */ 590 SOC_IF_ERROR_RETURN(READ_L3_DEFIP_PARITY_CONTROLr(unit, &rval)); 591 soc_reg_field_set(unit, L3_DEFIP_PARITY_CONTROLr, &rval, 592 PARITY_IRQ_ENf, 0); 593 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_PARITY_CONTROLr(unit, rval)); 594 soc_reg_field_set(unit, L3_DEFIP_PARITY_CONTROLr, &rval, 595 PARITY_ENf, 1); 596 soc_reg_field_set(unit, L3_DEFIP_PARITY_CONTROLr, &rval, 597 PARITY_IRQ_ENf, 1); 598 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_PARITY_CONTROLr(unit, rval)); 599 } 600 601 #ifdef BCM_RAVEN_SUPPORT 602 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 603 int i; 604 soc_reg_t reg[10] = {DSCP_TABLE_PARITY_CONTROLr, EGR_L3_INTF_PARITY_CONTROLr, 605 EGR_MASK_PARITY_CONTROLr, EGR_NEXT_HOP_PARITY_CONTROLr, 606 EGR_VLAN_TABLE_PARITY_CONTROLr, FP_POLICY_PARITY_CONTROLr, 607 ING_L3_NEXT_HOP_PARITY_CONTROLr, L2MC_PARITY_CONTROLr, 608 L3_IPMC_PARITY_CONTROLr, VLAN_PARITY_CONTROLr}; 609 for (i = 0; i < 10 ; i++) { 610 /* Skip non-existed registers for HAWKEYE */ 611 if (!SOC_REG_IS_VALID(unit, reg[i])) { 612 continue; 613 } 614 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg[i], REG_PORT_ANY, 0, &rval)); 615 soc_reg_field_set(unit, reg[i], &rval, PARITY_IRQ_ENf, 0); 616 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg[i], REG_PORT_ANY, 0, rval)); 617 if (reg[i] == FP_POLICY_PARITY_CONTROLr) { 618 #if defined(BCM_HAWKEYE_SUPPORT) 619 if(SOC_IS_HAWKEYE(unit)) { 620 soc_reg_field_set(unit, reg[i], &rval, PARITY_ENf, 0xf); 621 soc_reg_field_set(unit, reg[i], &rval, PARITY_IRQ_ENf, 0xf); 622 } else 623 #endif /* BCM_HAWKEYE_SUPPORT */ 624 { 625 soc_reg_field_set(unit, reg[i], &rval, PARITY_ENf, 0xffff); 626 soc_reg_field_set(unit, reg[i], &rval, PARITY_IRQ_ENf, 0xffff); 627 } 628 } else { 629 soc_reg_field_set(unit, reg[i], &rval, PARITY_ENf, 1); 630 soc_reg_field_set(unit, reg[i], &rval, PARITY_IRQ_ENf, 1); 631 } 632 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg[i], REG_PORT_ANY, 0, rval)); 633 } 634 SOC_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 635 soc_reg_field_set(unit, ING_MISC_CONFIGr, &rval, 636 DROP_PACKET_ON_PARITY_ERRORf, 1); 637 SOC_IF_ERROR_RETURN(WRITE_ING_MISC_CONFIGr(unit, rval)); 638 } 639 if (SOC_REG_IS_VALID(unit, ILPM_TM_REG_1r)) { 640 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, ILPM_TM_REG_1r, REG_PORT_ANY, 641 TM_L3_DEFIPf, 0x10)); 642 } 643 if (SOC_REG_IS_VALID(unit, ILPM_TM_REG_2r)) { 644 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, ILPM_TM_REG_2r, REG_PORT_ANY, 645 TM_L3_DEFIPf, 0x10)); 646 } 647 if (SOC_REG_IS_VALID(unit, FP_NON_ROTATED_CAM_CONTROLr)) { 648 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, FP_NON_ROTATED_CAM_CONTROLr, REG_PORT_ANY, 649 FP_NON_ROTATED_CAM_CONTROL_f, 0x10)); 650 } 651 if (SOC_REG_IS_VALID(unit, FP_ROTATED_CAM_CONTROLr)) { 652 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, FP_ROTATED_CAM_CONTROLr, REG_PORT_ANY, 653 FP_ROTATED_CAM_CONTROL_f, 0x10)); 654 } 655 #endif /* BCM_RAVEN_SUPPORT */ 656 657 /* 658 * Only on FB. 659 */ 660 if (SOC_IS_FIREBOLT(unit)) { 661 SOC_IF_ERROR_RETURN(soc_firebolt_cam_sam_config(unit, 0)); 662 } 663 664 #ifdef SOC_MEM_L3_DEFIP_WAR 665 /* Test L3_DEFIP and adjust table size */ 666 if (soc_feature(unit, soc_feature_l3_defip_map)) { 667 SOC_IF_ERROR_RETURN(soc_fb_l3_defip_resize(unit)); 668 } 669 #endif 670 671 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 672 /* Clear IPIPE/EIPIE Memories */ 673 SOC_IF_ERROR_RETURN(soc_firebolt_pipe_mem_clear(unit)); 674 } 675 676 #if defined(BCM_RAPTOR_SUPPORT) 677 if (soc_feature(unit, soc_feature_mac_learn_limit)) { 678 SOC_IF_ERROR_RETURN 679 (soc_mem_clear(unit, PORT_OR_TRUNK_MAC_LIMITm, COPYNO_ALL, TRUE)); 680 SOC_IF_ERROR_RETURN(WRITE_SYS_MAC_LIMITr(unit, 0x3fff)); 681 } 682 #endif /* BCM_RAPTOR_SUPPORT */ 683 684 /* Enable MMU parity error interrupt */ 685 SOC_IF_ERROR_RETURN(WRITE_MEMFAILINTSTATUSr(unit, 0)); 686 SOC_IF_ERROR_RETURN(READ_MEMFAILINTMASKr(unit, &imask)); 687 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 688 CFAPPARITYERRORINTMASKf, 1); 689 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 690 CCPPARITYERRORINTMASKf, 1); 691 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 692 CBPPKTHDRPARITYERRORINTMASKf, 1); 693 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 694 CBPCELLHDRPARITYERRORINTMASKf, 1); 695 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 696 XQPARITYERRORINTMASKf, 1); 697 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 698 CRCERRORINTMASKf, 1); 699 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 700 CFAPFAILINTMASKf, 1); 701 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 702 SOFTRESETINTMASKf, 1); 703 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 704 CELLNOTIPINTMASKf, 1); 705 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 706 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 707 IPMCREPOVERLIMITERRORINTMASKf, 1); 708 } 709 SOC_IF_ERROR_RETURN(WRITE_MEMFAILINTMASKr(unit, imask)); 710 711 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 712 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 713 PARITY_CHECK_ENf, 1); 714 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 715 CELLCRCCHECKENf, 1); 716 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 717 METERING_CLK_ENf, 1); 718 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 719 720 SOC_IF_ERROR_RETURN(READ_MEMFAILINTSTATUSr(unit, &imask)); 721 soc_intr_enable(unit, IRQ_MEM_FAIL); 722 723 #if defined (BCM_FIREBOLT2_SUPPORT) 724 if (SOC_IS_FIREBOLT2(unit)) { 725 if (soc_feature(unit, soc_feature_ser_parity)) { 726 #ifdef INCLUDE_MEM_SCAN 727 soc_mem_scan_ser_list_register(unit, FALSE, 728 _soc_fb2_ser_parity_info); 729 #endif /* INCLUDE_MEM_SCAN */ 730 } 731 } 732 #endif /* BCM_FIREBOLT2_SUPPORT */ 733 734 735 memset(&_fb_ser_functions, 0, sizeof(soc_ser_functions_t)); 736 _fb_ser_functions._soc_ser_parity_error_intr_f = &soc_fb_mmu_parity_error; 737 soc_ser_function_register(unit, &_fb_ser_functions); 738 739 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAVEN_SUPPORT) 740 if (SOC_IS_FIREBOLT2(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 741 soc_field_t fields[3]; 742 uint32 values[3]; 743 744 /* Enable dual hash on L2 and L3 tables */ 745 fields[0] = ENABLEf; 746 values[0] = 1; 747 fields[1] = HASH_SELECTf; 748 values[1] = FB_HASH_CRC32_LOWER; 749 SOC_IF_ERROR_RETURN 750 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 751 2, fields, values)); 752 753 if (!SOC_IS_HAWKEYE(unit)) { 754 SOC_IF_ERROR_RETURN 755 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, 756 REG_PORT_ANY, 2, fields, values)); 757 } 758 if (!SOC_IS_FIREBOLT2(unit)) { 759 SOC_IF_ERROR_RETURN 760 (soc_reg_fields32_modify(unit, VLAN_MAC_AUX_HASH_CONTROLr, 761 REG_PORT_ANY, 2, fields, values)); 762 } 763 } 764 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAVEN_SUPPORT */ 765 766 /* 767 * Egress Enable 768 */ 769 rval = 0; 770 soc_reg_field_set(unit, EGR_ENABLEr, &rval, PRT_ENABLEf, 1); 771 PBMP_ALL_ITER(unit, port) { 772 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEr(unit, port, rval)); 773 } 774 775 rval = 0; 776 soc_reg_field_set(unit, EPC_LINK_BMAPr, &rval, PORT_BITMAPf, 777 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 0)); 778 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPr(unit, rval)); 779 #if defined(BCM_RAPTOR_SUPPORT) 780 if (soc_feature(unit, soc_feature_register_hi)) { 781 soc_reg_field_set(unit, EPC_LINK_BMAP_HIr, &rval, PORT_BITMAPf, 782 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 1)); 783 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAP_HIr(unit, rval)); 784 } 785 #endif /* BCM_RAPTOR_SUPPORT */ 786 787 /* GMAC init should be moved to mac */ 788 rval = 0; 789 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 790 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, GPORT_ENf, 1); 791 prev_reg_addr = 0xffffffff; 792 PBMP_GE_ITER(unit, port) { 793 uint32 reg_addr; 794 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 795 if (reg_addr != prev_reg_addr) { 796 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 797 prev_reg_addr = reg_addr; 798 } 799 } 800 /* Felix */ 801 prev_reg_addr = 0xffffffff; 802 PBMP_FE_ITER(unit, port) { 803 uint32 reg_addr; 804 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 805 if (reg_addr != prev_reg_addr) { 806 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 807 prev_reg_addr = reg_addr; 808 } 809 } 810 prev_reg_addr = 0xffffffff; 811 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 812 PBMP_GE_ITER(unit, port) { 813 uint32 reg_addr; 814 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 815 if (reg_addr != prev_reg_addr) { 816 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 817 prev_reg_addr = reg_addr; 818 } 819 } 820 /* Felix */ 821 PBMP_FE_ITER(unit, port) { 822 uint32 reg_addr; 823 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 824 if (reg_addr != prev_reg_addr) { 825 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 826 prev_reg_addr = reg_addr; 827 } 828 } 829 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_RAVEN_SUPPORT) 830 if (SOC_IS_RAPTOR(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 831 if (SOC_PORT_VALID(unit, 1)) { 832 soc_reg_field_set(unit, 833 GPORT_CONFIGr, 834 &rval, 835 HGIG2_EN_S0f, 836 IS_ST_PORT(unit, 1) ? 1 : 0); 837 #if defined(BCM_RAPTOR1_SUPPORT) 838 if (SOC_IS_RAPTOR(unit)) { 839 /* Select LCPLL output as the reference clock for TxPll. */ 840 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, 841 SEL_LCPLL_S0f, 1); 842 } 843 #endif 844 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, 1, rval)); 845 } 846 if (SOC_PORT_VALID(unit, 2)) { 847 soc_reg_field_set(unit, 848 GPORT_CONFIGr, 849 &rval, 850 HGIG2_EN_S1f, 851 IS_ST_PORT(unit, 2) ? 1 : 0); 852 #if defined(BCM_RAPTOR1_SUPPORT) 853 if (SOC_IS_RAPTOR(unit)) { 854 /* Select LCPLL output as the reference clock for TxPll. */ 855 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, 856 SEL_LCPLL_S1f, 1); 857 } 858 #endif 859 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, 2, rval)); 860 } 861 #if defined(BCM_RAVEN_SUPPORT) 862 if (SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 863 if (SOC_PORT_VALID(unit, 4)) { 864 soc_reg_field_set(unit, 865 GPORT_CONFIGr, 866 &rval, 867 HGIG2_EN_S3f, 868 IS_ST_PORT(unit, 4) ? 1 : 0); 869 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, 3, rval)); 870 } 871 /* coverity[result_independent_of_operands] */ 872 if (SOC_PORT_VALID(unit, 5)) { 873 soc_reg_field_set(unit, 874 GPORT_CONFIGr, 875 &rval, 876 HGIG2_EN_S4f, 877 IS_ST_PORT(unit, 5) ? 1 : 0); 878 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, 4, rval)); 879 } 880 if (soc_property_get(unit, spn_SERDES_LCPLL, 0)) { 881 /* Select between external or LCPLL clock */ 882 SOC_IF_ERROR_RETURN 883 (READ_CMIC_GFPORT_CLOCK_CONFIGr(unit, &rval)); 884 soc_reg_field_set(unit, 885 CMIC_GFPORT_CLOCK_CONFIGr, 886 &rval, 887 SEL_DOZEN_SERDES_0_REF_CLK_SRCf, 888 3); 889 soc_reg_field_set(unit, 890 CMIC_GFPORT_CLOCK_CONFIGr, 891 &rval, 892 SEL_DOZEN_SERDES_1_REF_CLK_SRCf, 893 3); 894 if (soc_reg_field_valid(unit, CMIC_GFPORT_CLOCK_CONFIGr, 895 PROG_DOZEN_SERDES_PLLDIV_CTRL_DEFf)) { 896 soc_reg_field_set(unit, 897 CMIC_GFPORT_CLOCK_CONFIGr, 898 &rval, 899 PROG_DOZEN_SERDES_PLLDIV_CTRL_DEFf, 900 3); 901 } 902 SOC_IF_ERROR_RETURN 903 (WRITE_CMIC_GFPORT_CLOCK_CONFIGr(unit, rval)); 904 } 905 } 906 #endif /* BCM_RAVEN_SUPPORT */ 907 } 908 #endif /* BCM_RAPTOR_SUPPORT || BCM_RAVEN_SUPPORT*/ 909 910 /* XMAC init should be moved to mac */ 911 if (SOC_PBMP_NOT_NULL(PBMP_XE_ALL(unit)) || 912 SOC_PBMP_NOT_NULL(PBMP_HG_ALL(unit))) { 913 rval = 0; 914 soc_reg_field_set(unit, XPORT_CONFIGr, &rval, XPORT_ENf, 1); 915 soc_reg_field_set(unit, XPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 916 PBMP_HG_ITER(unit, port) { 917 SOC_IF_ERROR_RETURN(WRITE_XPORT_CONFIGr(unit, port, rval)); 918 } 919 soc_reg_field_set(unit, XPORT_CONFIGr, &rval, HIGIG_MODEf, 0); 920 PBMP_XE_ITER(unit, port) { 921 SOC_IF_ERROR_RETURN(WRITE_XPORT_CONFIGr(unit, port, rval)); 922 } 923 } 924 925 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAVEN_SUPPORT) 926 if (SOC_IS_FIREBOLT2(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 927 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 928 * causes the outer tag to be removed from packets that don't have 929 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 930 */ 931 if (SOC_REG_IS_VALID(unit, EGR_VLAN_CONTROL_1r)) { 932 rval = 0; 933 PBMP_ALL_ITER(unit, port) { 934 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 935 } 936 } 937 } 938 #endif 939 940 /* 941 * ING_CONFIG 942 */ 943 SOC_IF_ERROR_RETURN(READ_ING_CONFIGr(unit, &rval)); 944 soc_reg_field_set(unit, ING_CONFIGr, &rval, L3SRC_HIT_ENABLEf, 1); 945 soc_reg_field_set(unit, ING_CONFIGr, &rval, L2DST_HIT_ENABLEf, 1); 946 /* Fix the reset value and make it compatible with other devices */ 947 if (soc_reg_field_valid(unit, ING_CONFIGr, APPLY_EGR_MASK_ON_L2f)) { 948 soc_reg_field_set(unit, ING_CONFIGr, &rval, 949 APPLY_EGR_MASK_ON_L2f, 1); 950 } 951 if (soc_reg_field_valid(unit, ING_CONFIGr, APPLY_EGR_MASK_ON_L3f)) { 952 soc_reg_field_set(unit, ING_CONFIGr, &rval, 953 APPLY_EGR_MASK_ON_L3f, 1); 954 } 955 if (soc_feature(unit, soc_feature_remote_learn_trust)) { 956 soc_reg_field_set(unit, ING_CONFIGr, &rval, 957 DO_NOT_LEARN_ENABLEf, 1); 958 } 959 #ifdef BCM_FIREBOLT2_SUPPORT 960 /* Turn on ARP MACSA check for VFP */ 961 if (soc_reg_field_valid(unit, ING_CONFIGr, ARP_VALIDATION_ENf)) { 962 soc_reg_field_set(unit, ING_CONFIGr, &rval, 963 ARP_VALIDATION_ENf, 1); 964 } 965 #endif /* BCM_FIREBOLT2_SUPPORT */ 966 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIGr(unit, rval)); 967 968 /* Backwards compatible mirroring by default */ 969 if (soc_feature(unit, soc_feature_xgs1_mirror)) { 970 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 971 soc_reg_field_set(unit, MISCCONFIGr, &rval, 972 DRACO_1_5_MIRRORING_MODE_ENf, 1); 973 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 974 SOC_IF_ERROR_RETURN(READ_ING_CONFIGr(unit, &rval)); 975 soc_reg_field_set(unit, ING_CONFIGr, &rval, DRACO1_5_MIRRORf, 1); 976 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIGr(unit, rval)); 977 SOC_IF_ERROR_RETURN(READ_EGR_CONFIGr(unit, &rval)); 978 soc_reg_field_set(unit, EGR_CONFIGr, &rval, DRACO1_5_MIRRORf, 1); 979 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIGr(unit, rval)); 980 } 981 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 982 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, RING_MODEf, 1); 983 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 984 985 /* 986 * Set up PVID. Done in BCM Port init. Till then PVID = 0! 987 */ 988 989 if (soc_feature(unit, soc_feature_lpm_tcam)) { 990 int rv; 991 rv = soc_mem_clear(unit, L3_DEFIPm, COPYNO_ALL, TRUE); 992 if (rv < 0) { 993 LOG_CLI((BSL_META_U(unit, 994 "soc_mem_clear: LPM flush failed.\n"))); 995 return(rv); 996 } 997 } 998 #ifdef BCM_FIREBOLT2_SUPPORT 999 if (SOC_IS_FIREBOLT2(unit)) { 1000 uint32 e[SOC_MAX_MEM_FIELD_WORDS]; 1001 /* 1002 * Uninitialized L3_DEFIP buffers prep. 1003 * Read entries from both tcam banks to clear possible false parity 1004 * error indication * DO NOT CHECK FOR READ ERRORS * 1005 */ 1006 (void)READ_L3_DEFIPm(unit, MEM_BLOCK_ANY, 1007 soc_mem_index_min(unit, L3_DEFIPm), e); 1008 (void)READ_L3_DEFIPm(unit, MEM_BLOCK_ANY, 1009 soc_mem_index_max(unit, L3_DEFIPm), e); 1010 } 1011 #endif /* BCM_FIREBOLT2_SUPPORT */ 1012 1013 /* Improves the trunk distribution for Higig and unicast trunking for 1014 * non-power of 2 number of trunk ports. 1015 */ 1016 if (soc_feature(unit, soc_feature_trunk_group_size)) { 1017 SOC_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 1018 #if defined(BCM_FIREBOLT2_SUPPORT) 1019 if(SOC_REG_FIELD_VALID(unit, ING_MISC_CONFIGr, 1020 UNIFORM_HG_TRUNK_DIST_ENABLEf)) { 1021 soc_reg_field_set(unit, ING_MISC_CONFIGr, &rval, 1022 UNIFORM_HG_TRUNK_DIST_ENABLEf, 1); 1023 } 1024 #endif /* BCM_FIREBOLT2_SUPPORT */ 1025 1026 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 1027 if(SOC_REG_FIELD_VALID(unit, ING_MISC_CONFIGr, 1028 UNIFORM_TRUNK_DIST_ENABLEf)) { 1029 soc_reg_field_set(unit, ING_MISC_CONFIGr, &rval, 1030 UNIFORM_TRUNK_DIST_ENABLEf, 1); 1031 } 1032 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 1033 1034 SOC_IF_ERROR_RETURN(WRITE_ING_MISC_CONFIGr(unit, rval)); 1035 } 1036 /* 1037 * Set reference clock (based on 133MHz core clock) 1038 * to be 133MHz * (1/27) ~= 4.93MHz 1039 * so MDC output frequency is 0.5 * 4.93MHz ~= 2.46MHz 1040 */ 1041 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, 27); 1042 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 1043 rval = 0; 1044 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVISORf, divisor); 1045 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVIDENDf, dividend); 1046 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 1047 1048 /* Match the Internal MDC freq with above for External MDC */ 1049 if (SOC_REG_IS_VALID(unit, CMIC_RATE_ADJUST_INT_MDIOr)) { 1050 divisor = soc_property_get(unit, spn_RATE_INT_MDIO_DIVISOR, 27); 1051 dividend = soc_property_get(unit, spn_RATE_INT_MDIO_DIVIDEND, 1); 1052 rval = 0; 1053 soc_reg_field_set 1054 (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVISORf, divisor); 1055 soc_reg_field_set 1056 (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVIDENDf, dividend); 1057 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 1058 } 1059 1060 if (SOC_REG_IS_VALID(unit, CMIC_RATE_ADJUST_STDMAr)) { 1061 divisor = soc_property_get(unit, spn_RATE_STDMA_DIVISOR, 6); 1062 dividend = soc_property_get(unit, spn_RATE_STDMA_DIVIDEND, 1); 1063 rval = 0; 1064 soc_reg_field_set(unit, CMIC_RATE_ADJUST_STDMAr, &rval, 1065 DIVISORf, divisor); 1066 soc_reg_field_set(unit, CMIC_RATE_ADJUST_STDMAr, &rval, 1067 DIVIDENDf, dividend); 1068 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_STDMAr(unit, rval)); 1069 } 1070 1071 if (SOC_REG_IS_VALID(unit, CMIC_RATE_ADJUST_I2Cr)) { 1072 /* 1073 * Set reference clock (based on 133MHz core clock) 1074 * to be 133MHz * (1/27) ~= 4.93MHz 1075 * so I2C output frequency is 4.93MHz ~= 5Mhz. 1076 */ 1077 divisor = soc_property_get(unit, spn_RATE_I2C_DIVISOR, 27); 1078 dividend = soc_property_get(unit, spn_RATE_I2C_DIVIDEND, 1); 1079 rval = 0; 1080 soc_reg_field_set(unit, CMIC_RATE_ADJUST_I2Cr, &rval, DIVISORf, divisor); 1081 soc_reg_field_set(unit, CMIC_RATE_ADJUST_I2Cr, &rval, DIVIDENDf, dividend); 1082 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_I2Cr(unit, rval)); 1083 } 1084 1085 rval = 0x01; /* 125KHz I2C sampling rate based on 5Mhz reference clock */ 1086 SOC_IF_ERROR_RETURN(WRITE_CMIC_I2C_STATr(unit, rval)); 1087 1088 /* 1089 * H/W linkscan default MDIO address map. 1090 */ 1091 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_RAVEN_SUPPORT) 1092 if (SOC_IS_RAPTOR(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 1093 SOC_IF_ERROR_RETURN(soc_raptor_hw_linkscan_map_init(unit)); 1094 } 1095 #endif 1096 1097 /* Remap LED processor scan ports */ 1098 #if defined(BCM_RAVEN_SUPPORT) 1099 if (SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 1100 SOC_IF_ERROR_RETURN(READ_CMIC_LED_PORT_ORDER_REMAP_20_24r(unit, &rval)); 1101 soc_reg_field_set(unit, CMIC_LED_PORT_ORDER_REMAP_20_24r, &rval, 1102 REMAP_PORT_24f, 0x3); 1103 SOC_IF_ERROR_RETURN(WRITE_CMIC_LED_PORT_ORDER_REMAP_20_24r(unit, rval)); 1104 rval = 0; 1105 soc_reg_field_set(unit, CMIC_LED_PORT_ORDER_REMAP_25_29r, &rval, 1106 REMAP_PORT_25f, 0x1); 1107 soc_reg_field_set(unit, CMIC_LED_PORT_ORDER_REMAP_25_29r, &rval, 1108 REMAP_PORT_26f, 0x2); 1109 soc_reg_field_set(unit, CMIC_LED_PORT_ORDER_REMAP_25_29r, &rval, 1110 REMAP_PORT_27f, 0x4); 1111 soc_reg_field_set(unit, CMIC_LED_PORT_ORDER_REMAP_25_29r, &rval, 1112 REMAP_PORT_28f, 0x5); 1113 soc_reg_field_set(unit, CMIC_LED_PORT_ORDER_REMAP_25_29r, &rval, 1114 REMAP_PORT_29f, 0x0); 1115 SOC_IF_ERROR_RETURN(WRITE_CMIC_LED_PORT_ORDER_REMAP_25_29r(unit, rval)); 1116 rval = 0; 1117 SOC_IF_ERROR_RETURN(WRITE_CMIC_LED_PORT_ORDER_REMAP_30_34r(unit, rval)); 1118 SOC_IF_ERROR_RETURN(WRITE_CMIC_LED_PORT_ORDER_REMAP_35_39r(unit, rval)); 1119 SOC_IF_ERROR_RETURN(WRITE_CMIC_LED_PORT_ORDER_REMAP_40_44r(unit, rval)); 1120 SOC_IF_ERROR_RETURN(WRITE_CMIC_LED_PORT_ORDER_REMAP_45_49r(unit, rval)); 1121 SOC_IF_ERROR_RETURN(WRITE_CMIC_LED_PORT_ORDER_REMAP_50_54r(unit, rval)); 1122 } 1123 #endif 1124 1125 #if defined (BCM_FIREBOLT2_SUPPORT) 1126 if (SOC_IS_FIREBOLT2(unit)) { 1127 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_start(unit)); 1128 } 1129 #endif 1130 1131 return SOC_E_NONE; 1132 } 1133 #define FB_NUM_COS 8 1134 int soc_fb_xq_mem(int unit, soc_port_t port, soc_mem_t *xq) 1135 { 1136 soc_mem_t xq_mems[] = { MMU_XQ0m, 1137 MMU_XQ1m, 1138 MMU_XQ2m, 1139 MMU_XQ3m, 1140 MMU_XQ4m, 1141 MMU_XQ5m, 1142 MMU_XQ6m, 1143 MMU_XQ7m, 1144 MMU_XQ8m, 1145 MMU_XQ9m, 1146 MMU_XQ10m, 1147 MMU_XQ11m, 1148 MMU_XQ12m, 1149 MMU_XQ13m, 1150 MMU_XQ14m, 1151 MMU_XQ15m, 1152 MMU_XQ16m, 1153 MMU_XQ17m, 1154 MMU_XQ18m, 1155 MMU_XQ19m, 1156 MMU_XQ20m, 1157 MMU_XQ21m, 1158 MMU_XQ22m, 1159 MMU_XQ23m, 1160 MMU_XQ24m, 1161 MMU_XQ25m, 1162 MMU_XQ26m, 1163 MMU_XQ27m, 1164 #if defined(BCM_RAPTOR_SUPPORT) 1165 MMU_XQ28m, 1166 MMU_XQ29m, 1167 MMU_XQ30m, 1168 MMU_XQ31m, 1169 #if defined(BCM_RAPTOR1_SUPPORT) 1170 MMU_XQ32m, 1171 MMU_XQ33m, 1172 MMU_XQ34m, 1173 MMU_XQ35m, 1174 MMU_XQ36m, 1175 MMU_XQ37m, 1176 MMU_XQ38m, 1177 MMU_XQ39m, 1178 MMU_XQ40m, 1179 MMU_XQ41m, 1180 MMU_XQ42m, 1181 MMU_XQ43m, 1182 MMU_XQ44m, 1183 MMU_XQ45m, 1184 MMU_XQ46m, 1185 MMU_XQ47m, 1186 MMU_XQ48m, 1187 MMU_XQ49m, 1188 MMU_XQ50m, 1189 MMU_XQ51m, 1190 MMU_XQ52m, 1191 MMU_XQ53m 1192 #endif /* BCM_RAPTOR1_SUPPORT */ 1193 #else 1194 MMU_XQ28m 1195 #endif /* BCM_RAPTOR_SUPPORT */ 1196 }; 1197 int max_port; 1198 max_port = sizeof(xq_mems) / sizeof(xq_mems[0]); 1199 if (port >= max_port) { 1200 return(SOC_E_PORT); 1201 } 1202 *xq = xq_mems[port]; 1203 return(SOC_E_NONE); 1204 } 1205 1206 int 1207 soc_firebolt_internal_mmu_init(int unit) 1208 { 1209 int xq_per_port, cos, limit; 1210 soc_port_t port; 1211 uint32 val, oval, cfap_max_idx; 1212 int wgt[FB_NUM_COS], tot_wgt = 0; 1213 int age[FB_NUM_COS], max_age, min_age; 1214 int age_enable, disabled_age; 1215 int inactive_cosqs = 0; 1216 int skid_mark; 1217 soc_mem_t xq_mem; 1218 1219 cfap_max_idx = soc_mem_index_max(unit, MMU_CFAPm); 1220 SOC_IF_ERROR_RETURN(READ_CFAPCONFIGr(unit, &val)); 1221 oval = val; 1222 soc_reg_field_set(unit, CFAPCONFIGr, &val, CFAPPOOLSIZEf, cfap_max_idx); 1223 if (oval != val) { 1224 SOC_IF_ERROR_RETURN(WRITE_CFAPCONFIGr(unit, val)); 1225 } 1226 1227 SOC_IF_ERROR_RETURN(READ_CFAPFULLTHRESHOLDr(unit, &val)); 1228 oval = val; 1229 /* coverity [dead_error_line] */ 1230 /* coverity[dead_error_condition : FALSE] */ 1231 if (cfap_max_idx == 0x17ff) { 1232 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 1233 CFAPFULLRESETPOINTf, 0x1700); 1234 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 1235 CFAPFULLSETPOINTf, 0x1770); 1236 } 1237 if (oval != val) { 1238 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, val)); 1239 } 1240 1241 /* 1242 * Spread the XQs across all COSQs as dictated by the weight 1243 * properties. This will allow use of all COSQs. However, if 1244 * some COSQs are later disabled, the XQs allocated here to 1245 * those disabled COSQs will be unavailable for use. 1246 */ 1247 for (cos = 0; cos < NUM_COS(unit); cos++) { 1248 wgt[cos] = 1249 soc_property_suffix_num_get(unit, cos, spn_MMU_XQ_WEIGHT, 1250 "cos", 1); 1251 tot_wgt += wgt[cos]; 1252 if (!wgt[cos]) { 1253 inactive_cosqs++; 1254 } 1255 } 1256 1257 /* Every inactive COSQ consumes skid mark + 4 XQs; remove them from pool */ 1258 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 1259 skid_mark = soc_reg_field_get(unit, MISCCONFIGr, val, SKIDMARKERf) + 4; 1260 1261 PBMP_ALL_ITER(unit, port) { 1262 SOC_IF_ERROR_RETURN(soc_fb_xq_mem(unit, port, &xq_mem)); 1263 xq_per_port = soc_mem_index_count(unit, xq_mem) - 1264 (skid_mark * inactive_cosqs); 1265 for (cos = 0; cos < NUM_COS(unit); cos++) { 1266 /* 1267 * The HOLCOSPKTSETLIMITr register controls BOTH the XQ 1268 * size per cosq AND the HOL set limit for that cosq. 1269 */ 1270 SOC_IF_ERROR_RETURN 1271 (READ_HOLCOSPKTSETLIMITr(unit, port, cos, &val)); 1272 if (!wgt[cos]) { 1273 limit = skid_mark; /* Minimum value for this register */ 1274 } else if (wgt[cos] == tot_wgt) { 1275 limit = xq_per_port; /* All available XQs */ 1276 } else { 1277 limit = (xq_per_port * wgt[cos] / tot_wgt); 1278 } 1279 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &val, 1280 PKTSETLIMITf, 1281 limit); 1282 SOC_IF_ERROR_RETURN 1283 (WRITE_HOLCOSPKTSETLIMITr(unit, port, cos, val)); 1284 1285 } 1286 } 1287 1288 /* 1289 * Configure per-XQ packet aging for the various COSQs. 1290 * 1291 * The shortest age allowed by H/W is 250 microseconds. 1292 * The longest age allowed is 7.162 seconds (7162 msec). 1293 * The maximum ratio between the longest age and the shortest 1294 * (nonzero) age is 7:2. 1295 */ 1296 age_enable = disabled_age = max_age = 0; 1297 min_age = 7162; 1298 for (cos = 0; cos < NUM_COS(unit); cos++) { 1299 if ((age[cos] = 1300 soc_property_suffix_num_get(unit, cos, spn_MMU_XQ_AGING, 1301 "cos", 0)) > 0) { 1302 age_enable = 1; 1303 if (age[cos] > 7162) { 1304 age[cos] = 7162; 1305 } 1306 if (age[cos] < min_age) { 1307 min_age = age[cos]; 1308 } 1309 } else { 1310 disabled_age = 1; 1311 age[cos] = 0; 1312 } 1313 if (age[cos] > max_age) { 1314 max_age = age[cos]; 1315 } 1316 } 1317 if (!age_enable) { 1318 /* Disable packet aging on all COSQs */ 1319 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 0)); 1320 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, 0)); /* Aesthetic */ 1321 } else { 1322 uint32 regval = 0; 1323 uint32 timerval; 1324 1325 /* Enforce the 7:2 ratio between min and max values */ 1326 if ((((max_age * 2)+6) / 7) > min_age) { 1327 /* Keep requested max age; make min_age comply */ 1328 min_age = ((max_age * 2) + 6) / 7; 1329 } 1330 1331 /* 1332 * Give up granularity for range, if we need to 1333 * "disable" (max out) aging for any COSQ(s). 1334 */ 1335 if (disabled_age) { 1336 /* Max range */ 1337 max_age = min_age * 7 / 2; 1338 } 1339 1340 /* 1341 * Compute shortest duration of one PKTAGINGTIMERr cycle. 1342 * This duration is 1/7th of the longest packet age. 1343 * This duration is in units of 125 usec (msec * 8). 1344 */ 1345 1346 timerval = ((8 * max_age) + 6) / 7; 1347 if (timerval <= 0) { 1348 return SOC_E_PARAM; 1349 } 1350 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, timerval)); 1351 1352 for (cos = 0; cos < NUM_COS(unit); cos++) { 1353 if (!age[cos]) { 1354 /* 1355 * Requested to be disabled, but cannot disable individual 1356 * COSQs once packet aging is enabled. Therefore, mark 1357 * this COSQ's aging duration as maxed out. 1358 */ 1359 age[cos] = -1; 1360 } else if (age[cos] < min_age) { 1361 age[cos] = min_age; 1362 } 1363 1364 /* Normalize each "age" into # of PKTAGINGTIMERr cycles. */ 1365 if (age[cos] > 0) { 1366 age[cos] = ((8 * age[cos]) + timerval - 1) / timerval; 1367 } 1368 else { 1369 age[cos] = 7; 1370 } 1371 /* Format each "age" for its appropriate field */ 1372 regval |= ((7 - age[cos]) << (cos * 3)); 1373 } 1374 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, regval)); 1375 } 1376 1377 /* 1378 * Port enable 1379 */ 1380 val = 0; 1381 soc_reg_field_set(unit, MMUPORTENABLEr, &val, MMUPORTENABLEf, 1382 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 0)); 1383 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLEr(unit, val)); 1384 #if defined(BCM_RAPTOR1_SUPPORT) 1385 if (soc_feature(unit, soc_feature_register_hi)) { 1386 val = 0; 1387 soc_reg_field_set(unit, MMUPORTENABLE_HIr, &val, MMUPORTENABLEf, 1388 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 1)); 1389 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLE_HIr(unit, val)); 1390 } 1391 #endif /* BCM_RAPTOR_SUPPORT */ 1392 1393 return SOC_E_NONE; 1394 } 1395 1396 int 1397 soc_firebolt_mmu_init(int unit) 1398 { 1399 int rv = SOC_E_NONE; 1400 1401 /* Don't run mmu setting for Hawkeye */ 1402 if(!SOC_IS_HAWKEYE(unit)) { 1403 rv = soc_firebolt_internal_mmu_init(unit); 1404 1405 #ifdef BCM_RAVEN_SUPPORT 1406 if (soc_feature(unit, soc_feature_post)) { 1407 sal_usecs_t stime = sal_time_usecs(); 1408 if ((rv = soc_post_init(unit)) < 0) { 1409 LOG_CLI((BSL_META_U(unit, 1410 "soc_post_init failed on unit %d\n"), unit)); 1411 } 1412 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1413 (BSL_META_U(unit, 1414 "soc_post_init: took %d usec\n"), 1415 SAL_USECS_SUB(sal_time_usecs(), stime))); 1416 } 1417 #endif 1418 } 1419 return (rv); 1420 } 1421 1422 int 1423 soc_firebolt_age_timer_get(int unit, int *age_seconds, int *enabled) 1424 { 1425 uint32 value; 1426 1427 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &value)); 1428 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_ENAf); 1429 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_VALf); 1430 1431 return SOC_E_NONE; 1432 } 1433 1434 int 1435 soc_firebolt_age_timer_max_get(int unit, int *max_seconds) 1436 { 1437 *max_seconds = 1438 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 1439 1440 return SOC_E_NONE; 1441 } 1442 1443 int 1444 soc_firebolt_age_timer_set(int unit, int age_seconds, int enable) 1445 { 1446 uint32 value; 1447 1448 value = 0; 1449 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_ENAf, enable); 1450 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_VALf, age_seconds); 1451 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, value)); 1452 1453 return SOC_E_NONE; 1454 } 1455 1456 /* 1457 * _soc_fb_mmu_parity_error 1458 * FB MMU parity error decoder 1459 */ 1460 int _soc_fb_mmu_parity_error(int unit) 1461 { 1462 uint32 istat, val; 1463 soc_control_t *soc = SOC_CONTROL(unit); 1464 1465 SOC_IF_ERROR_RETURN(READ_MEMFAILINTSTATUSr(unit, &istat)); 1466 if (istat != 0) { 1467 soc->stat.intr_mmu++; 1468 } 1469 1470 LOG_ERROR(BSL_LS_SOC_COMMON, 1471 (BSL_META_U(unit, 1472 "soc_fb_mmu_parity_error:unit = %d," 1473 "INTSTATUS = 0x%08x Fail Count = %d\n"), 1474 unit, 1475 istat, 1476 soc_reg_field_get(unit, MEMFAILINTSTATUSr, 1477 istat, MEMFAILINTCOUNTf))); 1478 1479 1480 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, istat, CFAPFAILERRORf)) { 1481 LOG_ERROR(BSL_LS_SOC_COMMON, 1482 (BSL_META_U(unit, 1483 "unit = %d, CFAPFAILERROR\n"), unit)); 1484 } 1485 1486 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, 1487 istat, CFAPPARITYERRORf)) { 1488 soc->stat.err_cfap++; 1489 SOC_IF_ERROR_RETURN(READ_CFAPPARITYERRORPTRr(unit, &val)); 1490 LOG_ERROR(BSL_LS_SOC_COMMON, 1491 (BSL_META_U(unit, 1492 "unit = %d, CFAPPARITYERRORPTR 0x%08x\n"), 1493 unit, val)); 1494 } 1495 1496 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, istat, SOFTRESETERRORf)) { 1497 soc->stat.err_sr++; 1498 LOG_ERROR(BSL_LS_SOC_COMMON, 1499 (BSL_META_U(unit, 1500 "unit = %d, MMU Soft Reset Error\n"), unit)); 1501 } 1502 1503 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, istat, CELLNOTIPERRORf)) { 1504 LOG_ERROR(BSL_LS_SOC_COMMON, 1505 (BSL_META_U(unit, 1506 "unit = %d, MMU Cell not in progress\n"), unit)); 1507 } 1508 1509 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, istat, CELLCRCERRORf)) { 1510 soc->stat.err_cellcrc++; 1511 SOC_IF_ERROR_RETURN(READ_CBPCELLCRCERRPTRr(unit, &val)); 1512 LOG_ERROR(BSL_LS_SOC_COMMON, 1513 (BSL_META_U(unit, 1514 "unit = %d, CBPCELLCRCERRPTR 0x%08x\n"), unit, val)); 1515 } 1516 1517 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, 1518 istat, CBPPKTHDRPARITYERRORf)) { 1519 soc->stat.err_cbphp++; 1520 SOC_IF_ERROR_RETURN(READ_CBPPKTHDRPARITYERRPTRr(unit, &val)); 1521 LOG_ERROR(BSL_LS_SOC_COMMON, 1522 (BSL_META_U(unit, 1523 "unit = %d, CBPPKTHDRPARITYERRPTR 0x%08x\n"), 1524 unit, val)); 1525 } 1526 1527 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, 1528 istat, CBPCELLHDRPARITYERRORf)) { 1529 soc->stat.err_cpbcrc++; 1530 SOC_IF_ERROR_RETURN(READ_CBPCELLHDRPARITYERRPTRr(unit, &val)); 1531 LOG_ERROR(BSL_LS_SOC_COMMON, 1532 (BSL_META_U(unit, 1533 "unit = %d, CBPCELLHDRPARITYERRPTR 0x%08x\n"), 1534 unit, val)); 1535 } 1536 1537 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, istat, XQPARITYERRORf)) { 1538 soc->stat.err_mp++; 1539 SOC_IF_ERROR_RETURN(READ_XQPARITYERRORPBMr(unit, &val)); 1540 LOG_ERROR(BSL_LS_SOC_COMMON, 1541 (BSL_META_U(unit, 1542 "unit = %d, XQPARITYERRORPBM 0x%08x\n"), 1543 unit, val)); 1544 } 1545 1546 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, istat, CCPPARITYERRORf)) { 1547 soc->stat.err_cpcrc++; 1548 SOC_IF_ERROR_RETURN(READ_CCPPARITYERRORPTRr(unit, &val)); 1549 LOG_ERROR(BSL_LS_SOC_COMMON, 1550 (BSL_META_U(unit, 1551 "unit = %d, CCPPARITYERRORPTR 0x%08x\n"), 1552 unit, val)); 1553 } 1554 1555 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 1556 if (soc_reg_field_get(unit, MEMFAILINTSTATUSr, 1557 istat, IPMCREPOVERLIMITERRORf)) { 1558 LOG_ERROR(BSL_LS_SOC_COMMON, 1559 (BSL_META_U(unit, 1560 "unit=%d, IPMC Over Pre-set Replication Limit\n"), 1561 unit)); 1562 } 1563 } 1564 1565 SOC_IF_ERROR_RETURN(WRITE_MEMFAILINTSTATUSr(unit, 0)); 1566 1567 return SOC_E_NONE; 1568 } 1569 1570 /* 1571 * _soc_hx_ipipe_parity_error 1572 * HX/FX L2/L3 parity error decoder 1573 */ 1574 int _soc_hx_ipipe_parity_error(int unit) 1575 { 1576 uint32 istat = 0; 1577 uint32 val = 0; 1578 _soc_ser_correct_info_t spci; 1579 1580 if (soc_feature(unit, soc_feature_l2x_parity)) { 1581 SOC_IF_ERROR_RETURN(READ_L2_ENTRY_PARITY_STATUSr(unit, &istat)); 1582 if (soc_reg_field_get(unit, L2_ENTRY_PARITY_STATUSr, 1583 istat, PARITY_ERRf)) { 1584 uint32 bucket, entry_bmap, index, b_index; 1585 bucket = soc_reg_field_get(unit, L2_ENTRY_PARITY_STATUSr, 1586 istat, BUCKET_IDXf), 1587 entry_bmap = soc_reg_field_get(unit, L2_ENTRY_PARITY_STATUSr, 1588 istat, ENTRY_BMf); 1589 LOG_ERROR(BSL_LS_SOC_COMMON, 1590 (BSL_META_U(unit, 1591 "_soc_hx_ipipe_parity_error:unit = %d," 1592 "L2_ENTRY_PARITY_STATUS = 0x%08x, " 1593 "Bucket = %d Entry Bitmap 0x%02x\n"), 1594 unit, 1595 istat, 1596 bucket, 1597 entry_bmap)); 1598 1599 if (SOC_IS_FIREBOLT2(unit)) { 1600 for (b_index = 0; ((entry_bmap & 1) == 0) && (entry_bmap != 0); entry_bmap >>= 1, b_index++) { } 1601 index = bucket*8 + b_index; 1602 1603 memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 1604 1605 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 1606 spci.reg = INVALIDr; 1607 spci.mem = L2_ENTRY_ONLYm; 1608 spci.blk_type = SOC_BLK_IPIPE; 1609 spci.index = index; 1610 (void)soc_ser_correction(unit, &spci); 1611 } 1612 1613 /* Clear all parity errors */ 1614 SOC_IF_ERROR_RETURN(READ_L2_ENTRY_PARITY_CONTROLr(unit, &val)); 1615 soc_reg_field_set(unit, L2_ENTRY_PARITY_CONTROLr, &val, 1616 PARITY_IRQ_ENf, 0); 1617 SOC_IF_ERROR_RETURN(WRITE_L2_ENTRY_PARITY_CONTROLr(unit, val)); 1618 soc_reg_field_set(unit, L2_ENTRY_PARITY_CONTROLr, &val, 1619 PARITY_IRQ_ENf, 1); 1620 SOC_IF_ERROR_RETURN(WRITE_L2_ENTRY_PARITY_CONTROLr(unit, val)); 1621 } 1622 } 1623 1624 if (soc_feature(unit, soc_feature_l3x_parity)) { 1625 SOC_IF_ERROR_RETURN(READ_L3_ENTRY_PARITY_STATUSr(unit, &istat)); 1626 if (soc_reg_field_get(unit, L3_ENTRY_PARITY_STATUSr, 1627 istat, PARITY_ERRf)) { 1628 uint32 bucket, entry_bmap, index, b_index; 1629 1630 bucket = soc_reg_field_get(unit, L3_ENTRY_PARITY_STATUSr, 1631 istat, BUCKET_IDXf), 1632 entry_bmap = soc_reg_field_get(unit, L3_ENTRY_PARITY_STATUSr, 1633 istat, ENTRY_BMf); 1634 LOG_ERROR(BSL_LS_SOC_COMMON, 1635 (BSL_META_U(unit, 1636 "_soc_hx_ipipe_parity_error:unit = %d," 1637 "L3_ENTRY_PARITY_STATUS = 0x%08x, " 1638 "Bucket = %d Entry Bitmap 0x%02x\n"), 1639 unit, 1640 istat, 1641 bucket, 1642 entry_bmap)); 1643 1644 if (SOC_IS_FIREBOLT2(unit)) { 1645 for (b_index = 0; ((entry_bmap & 1) == 0) && (entry_bmap != 0) ; entry_bmap >>= 1, b_index++) { } 1646 index = bucket*8 + b_index; 1647 1648 memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 1649 1650 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 1651 spci.reg = INVALIDr; 1652 spci.mem = L3_ENTRY_ONLYm; 1653 spci.blk_type = SOC_BLK_IPIPE; 1654 spci.index = index; 1655 (void)soc_ser_correction(unit, &spci); 1656 } 1657 1658 SOC_IF_ERROR_RETURN(READ_L3_ENTRY_PARITY_CONTROLr(unit, &val)); 1659 soc_reg_field_set(unit, L3_ENTRY_PARITY_CONTROLr, &val, 1660 PARITY_IRQ_ENf, 0); 1661 SOC_IF_ERROR_RETURN(WRITE_L3_ENTRY_PARITY_CONTROLr(unit, val)); 1662 soc_reg_field_set(unit, L3_ENTRY_PARITY_CONTROLr, &val, 1663 PARITY_IRQ_ENf, 1); 1664 SOC_IF_ERROR_RETURN(WRITE_L3_ENTRY_PARITY_CONTROLr(unit, val)); 1665 } 1666 } 1667 1668 if (soc_feature(unit, soc_feature_l3defip_parity)) { 1669 SOC_IF_ERROR_RETURN(READ_L3_DEFIP_PARITY_STATUSr(unit, &istat)); 1670 if (soc_reg_field_get(unit, L3_DEFIP_PARITY_STATUSr, 1671 istat, PARITY_ERRf)) { 1672 uint32 mem_idx; 1673 1674 mem_idx = soc_reg_field_get(unit, L3_DEFIP_PARITY_STATUSr, 1675 istat, MEMORY_IDXf); 1676 if (SOC_IS_FIREBOLT2(unit)) { 1677 uint32 mem_idx_min, mem_idx_max, index; 1678 if (mem_idx > (soc_mem_index_max(unit, L3_DEFIPm) / 2)) { 1679 /* HW idiosyncrasy for second URPF bank */ 1680 mem_idx -= 1024; 1681 } 1682 1683 mem_idx_min = mem_idx & ~0x3; 1684 mem_idx_max = mem_idx_min + 3; 1685 LOG_ERROR(BSL_LS_SOC_COMMON, 1686 (BSL_META_U(unit, 1687 "_soc_fb_ipipe_parity_error:unit = %d," 1688 "L3_DEFIP_PARITY_STATUS = 0x%08x, " 1689 "Index range = %d - %d"), 1690 unit, istat, mem_idx_min, mem_idx_max)); 1691 1692 for (index = mem_idx_min; index <= mem_idx_max; index++) { 1693 memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 1694 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 1695 spci.reg = INVALIDr; 1696 spci.mem = L3_DEFIP_DATA_ONLYm; 1697 spci.blk_type = SOC_BLK_IPIPE; 1698 spci.index = index; 1699 (void)soc_ser_correction(unit, &spci); 1700 } 1701 } else { 1702 LOG_ERROR(BSL_LS_SOC_COMMON, 1703 (BSL_META_U(unit, 1704 "_soc_fb_ipipe_parity_error:unit = %d," 1705 "L3_DEFIP_PARITY_STATUS = 0x%08x, Index = %d "), 1706 unit, 1707 istat, 1708 mem_idx)); 1709 } 1710 SOC_IF_ERROR_RETURN(READ_L3_DEFIP_PARITY_CONTROLr(unit, &val)); 1711 soc_reg_field_set(unit, L3_DEFIP_PARITY_CONTROLr, &val, 1712 PARITY_IRQ_ENf, 0); 1713 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_PARITY_CONTROLr(unit, val)); 1714 soc_reg_field_set(unit, L3_DEFIP_PARITY_CONTROLr, &val, 1715 PARITY_IRQ_ENf, 1); 1716 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_PARITY_CONTROLr(unit, val)); 1717 } 1718 } 1719 #ifdef BCM_RAVEN_SUPPORT 1720 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1721 int i; 1722 uint32 err_addr, mem_idx, slice_idx; 1723 soc_reg_t ctrl_reg[10] = {DSCP_TABLE_PARITY_CONTROLr, EGR_L3_INTF_PARITY_CONTROLr, 1724 EGR_MASK_PARITY_CONTROLr, EGR_NEXT_HOP_PARITY_CONTROLr, 1725 EGR_VLAN_TABLE_PARITY_CONTROLr, FP_POLICY_PARITY_CONTROLr, 1726 ING_L3_NEXT_HOP_PARITY_CONTROLr, L2MC_PARITY_CONTROLr, 1727 L3_IPMC_PARITY_CONTROLr, VLAN_PARITY_CONTROLr}; 1728 soc_reg_t stat_reg[10] = {DSCP_TABLE_PARITY_STATUSr, EGR_L3_INTF_PARITY_STATUSr, 1729 EGR_MASK_PARITY_STATUSr, EGR_NEXT_HOP_PARITY_STATUSr, 1730 EGR_VLAN_TABLE_PARITY_STATUSr, FP_POLICY_PARITY_STATUSr, 1731 ING_L3_NEXT_HOP_PARITY_STATUSr, L2MC_PARITY_STATUSr, 1732 L3_IPMC_PARITY_STATUSr, VLAN_PARITY_STATUSr}; 1733 1734 for (i = 0; i < 10 ; i++) { 1735 /* Skip non-existed registers for HAWKEYE */ 1736 if (!SOC_REG_IS_VALID(unit, ctrl_reg[i])) { 1737 continue; 1738 } 1739 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, stat_reg[i], REG_PORT_ANY, 0, 1740 &istat)); 1741 if (soc_reg_field_get(unit, stat_reg[i], istat, PARITY_ERRf)) { 1742 switch (stat_reg[i]) { 1743 case DSCP_TABLE_PARITY_STATUSr: 1744 case EGR_MASK_PARITY_STATUSr: 1745 case ING_L3_NEXT_HOP_PARITY_STATUSr: 1746 case L2MC_PARITY_STATUSr: 1747 case VLAN_PARITY_STATUSr: 1748 err_addr = soc_reg_field_get(unit, stat_reg[i], istat, ERR_ADDRf); 1749 LOG_ERROR(BSL_LS_SOC_COMMON, 1750 (BSL_META_U(unit, 1751 "_soc_fb_ipipe_parity_error:unit = %d," 1752 "PARITY_STATUS register (%x) = 0x%08x, Index = %d "), 1753 unit, 1754 stat_reg[i], 1755 istat, 1756 err_addr)); 1757 break; 1758 case EGR_L3_INTF_PARITY_STATUSr: 1759 case EGR_NEXT_HOP_PARITY_STATUSr: 1760 case EGR_VLAN_TABLE_PARITY_STATUSr: 1761 case L3_IPMC_PARITY_STATUSr: 1762 mem_idx = soc_reg_field_get(unit, stat_reg[i], istat, MEMORY_IDXf); 1763 LOG_ERROR(BSL_LS_SOC_COMMON, 1764 (BSL_META_U(unit, 1765 "_soc_fb_ipipe_parity_error:unit = %d," 1766 "PARITY_STATUS register (%x) = 0x%08x, Index = %d "), 1767 unit, 1768 stat_reg[i], 1769 istat, 1770 mem_idx)); 1771 break; 1772 case FP_POLICY_PARITY_STATUSr: 1773 slice_idx = soc_reg_field_get(unit, stat_reg[i], istat, SLICE_IDXf); 1774 mem_idx = soc_reg_field_get(unit, stat_reg[i], istat, MEMORY_IDXf); 1775 LOG_ERROR(BSL_LS_SOC_COMMON, 1776 (BSL_META_U(unit, 1777 "_soc_fb_ipipe_parity_error:unit = %d," 1778 "PARITY_STATUS register (%x) = 0x%08x, Slice = %d," 1779 "Index = %d "), 1780 unit, 1781 stat_reg[i], 1782 istat, 1783 slice_idx, 1784 mem_idx)); 1785 break; 1786 } 1787 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ctrl_reg[i], REG_PORT_ANY, 1788 0, &val)); 1789 soc_reg_field_set(unit, ctrl_reg[i], &val, PARITY_IRQ_ENf, 0); 1790 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ctrl_reg[i], REG_PORT_ANY, 1791 0, val)); 1792 if (ctrl_reg[i] == FP_POLICY_PARITY_CONTROLr) { 1793 soc_reg_field_set(unit, ctrl_reg[i], &val, PARITY_IRQ_ENf, 0xffff); 1794 } else { 1795 soc_reg_field_set(unit, ctrl_reg[i], &val, PARITY_IRQ_ENf, 1); 1796 } 1797 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ctrl_reg[i], REG_PORT_ANY, 1798 0, val)); 1799 } 1800 } 1801 } 1802 #endif /* BCM_RAVEN_SUPPORT */ 1803 return SOC_E_NONE; 1804 } 1805 1806 void soc_fb_mmu_parity_error(void *unit, void *d1, void *d2, 1807 void *d3, void *d4 ) 1808 { 1809 int u = PTR_TO_INT(unit); 1810 1811 COMPILER_REFERENCE(d1); 1812 COMPILER_REFERENCE(d2); 1813 COMPILER_REFERENCE(d3); 1814 COMPILER_REFERENCE(d4); 1815 _soc_hx_ipipe_parity_error(u); 1816 _soc_fb_mmu_parity_error(u); 1817 soc_intr_enable(u, IRQ_MEM_FAIL); 1818 } 1819 1820 void 1821 soc_helix_mem_config(int unit) 1822 { 1823 soc_persist_t *sop; 1824 sop = SOC_PERSIST(unit); 1825 1826 /* 1827 sop->memState[L2Xm].index_max = 8191; 1828 sop->memState[L2_ENTRY_ONLYm].index_max = 8191; 1829 sop->memState[L2_HITDA_ONLYm].index_max = 1023; 1830 sop->memState[L2_HITSA_ONLYm].index_max = 1023; 1831 1832 sop->memState[L3_ENTRY_ONLYm].index_max = 2047; 1833 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = 2047; 1834 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = 2047; 1835 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = 1023; 1836 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = 511; 1837 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = 255; 1838 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = 255; 1839 */ 1840 1841 sop->memState[L3_DEFIPm].index_max = 255; 1842 sop->memState[L3_DEFIP_ONLYm].index_max = 255; 1843 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 255; 1844 1845 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 255; 1846 1847 sop->memState[FP_TCAMm].index_max = 1023; 1848 sop->memState[FP_TCAM_PLUS_POLICYm].index_max = 1023; 1849 sop->memState[FP_POLICY_TABLEm].index_max = 1023; 1850 sop->memState[FP_METER_TABLEm].index_max = 1023; 1851 sop->memState[FP_COUNTER_TABLEm].index_max = 1023; 1852 1853 sop->memState[L3_ECMPm].index_max = 127; 1854 sop->memState[ING_L3_NEXT_HOPm].index_max = 2047; 1855 sop->memState[EGR_L3_NEXT_HOPm].index_max = 2047; 1856 1857 sop->memState[MMU_XQ0m].index_max = 0x2ff; 1858 sop->memState[MMU_XQ1m].index_max = 0x2ff; 1859 sop->memState[MMU_XQ2m].index_max = 0x2ff; 1860 sop->memState[MMU_XQ3m].index_max = 0x2ff; 1861 sop->memState[MMU_XQ4m].index_max = 0x2ff; 1862 sop->memState[MMU_XQ5m].index_max = 0x2ff; 1863 sop->memState[MMU_XQ6m].index_max = 0x2ff; 1864 sop->memState[MMU_XQ7m].index_max = 0x2ff; 1865 sop->memState[MMU_XQ8m].index_max = 0x2ff; 1866 sop->memState[MMU_XQ9m].index_max = 0x2ff; 1867 sop->memState[MMU_XQ10m].index_max = 0x2ff; 1868 sop->memState[MMU_XQ11m].index_max = 0x2ff; 1869 sop->memState[MMU_XQ12m].index_max = 0x2ff; 1870 sop->memState[MMU_XQ13m].index_max = 0x2ff; 1871 sop->memState[MMU_XQ14m].index_max = 0x2ff; 1872 sop->memState[MMU_XQ15m].index_max = 0x2ff; 1873 sop->memState[MMU_XQ16m].index_max = 0x2ff; 1874 sop->memState[MMU_XQ17m].index_max = 0x2ff; 1875 sop->memState[MMU_XQ18m].index_max = 0x2ff; 1876 sop->memState[MMU_XQ19m].index_max = 0x2ff; 1877 sop->memState[MMU_XQ20m].index_max = 0x2ff; 1878 sop->memState[MMU_XQ21m].index_max = 0x2ff; 1879 sop->memState[MMU_XQ22m].index_max = 0x2ff; 1880 sop->memState[MMU_XQ23m].index_max = 0x2ff; 1881 1882 sop->memState[MMU_XQ24m].index_max = 0x3ff; 1883 sop->memState[MMU_XQ25m].index_max = 0x3ff; 1884 sop->memState[MMU_XQ26m].index_max = 0x3ff; 1885 sop->memState[MMU_XQ27m].index_max = 0x3ff; 1886 1887 sop->memState[MMU_XQ28m].index_max = 0x2ff; 1888 1889 sop->memState[MMU_AGING_CTRm].index_max = 0x2ff; 1890 sop->memState[MMU_AGING_EXPm].index_max = 0x2ff; 1891 1892 sop->memState[MMU_CBPCELLHEADERm].index_max = 0x17ff; 1893 sop->memState[MMU_CBPDATA0m].index_max = 0x17ff; 1894 sop->memState[MMU_CBPDATA1m].index_max = 0x17ff; 1895 sop->memState[MMU_CBPDATA2m].index_max = 0x17ff; 1896 sop->memState[MMU_CBPDATA3m].index_max = 0x17ff; 1897 sop->memState[MMU_CBPDATA4m].index_max = 0x17ff; 1898 sop->memState[MMU_CBPDATA5m].index_max = 0x17ff; 1899 sop->memState[MMU_CBPDATA6m].index_max = 0x17ff; 1900 sop->memState[MMU_CBPDATA7m].index_max = 0x17ff; 1901 sop->memState[MMU_CBPDATA8m].index_max = 0x17ff; 1902 sop->memState[MMU_CBPDATA9m].index_max = 0x17ff; 1903 sop->memState[MMU_CBPDATA10m].index_max = 0x17ff; 1904 sop->memState[MMU_CBPDATA11m].index_max = 0x17ff; 1905 sop->memState[MMU_CBPDATA12m].index_max = 0x17ff; 1906 sop->memState[MMU_CBPDATA13m].index_max = 0x17ff; 1907 sop->memState[MMU_CBPDATA14m].index_max = 0x17ff; 1908 sop->memState[MMU_CBPDATA15m].index_max = 0x17ff; 1909 sop->memState[MMU_CBPPKTHEADER0m].index_max = 0x17ff; 1910 sop->memState[MMU_CBPPKTHEADER1m].index_max = 0x17ff; 1911 sop->memState[MMU_CCPm].index_max = 0x17ff; 1912 sop->memState[MMU_CFAPm].index_max = 0x17ff; 1913 } 1914 1915 void 1916 soc_bcm53300_mem_config(int unit) 1917 { 1918 soc_persist_t *sop; 1919 sop = SOC_PERSIST(unit); 1920 1921 sop->memState[MMU_CBPCELLHEADERm].index_max = 0xfff; 1922 sop->memState[MMU_CBPDATA0m].index_max = 0xfff; 1923 sop->memState[MMU_CBPDATA1m].index_max = 0xfff; 1924 sop->memState[MMU_CBPDATA2m].index_max = 0xfff; 1925 sop->memState[MMU_CBPDATA3m].index_max = 0xfff; 1926 sop->memState[MMU_CBPDATA4m].index_max = 0xfff; 1927 sop->memState[MMU_CBPDATA5m].index_max = 0xfff; 1928 sop->memState[MMU_CBPDATA6m].index_max = 0xfff; 1929 sop->memState[MMU_CBPDATA7m].index_max = 0xfff; 1930 sop->memState[MMU_CBPDATA8m].index_max = 0xfff; 1931 sop->memState[MMU_CBPDATA9m].index_max = 0xfff; 1932 sop->memState[MMU_CBPDATA10m].index_max = 0xfff; 1933 sop->memState[MMU_CBPDATA11m].index_max = 0xfff; 1934 sop->memState[MMU_CBPDATA12m].index_max = 0xfff; 1935 sop->memState[MMU_CBPDATA13m].index_max = 0xfff; 1936 sop->memState[MMU_CBPDATA14m].index_max = 0xfff; 1937 sop->memState[MMU_CBPDATA15m].index_max = 0xfff; 1938 sop->memState[MMU_CBPPKTHEADER0m].index_max = 0xfff; 1939 sop->memState[MMU_CBPPKTHEADER1m].index_max = 0xfff; 1940 sop->memState[MMU_CCPm].index_max = 0xfff; 1941 sop->memState[MMU_CFAPm].index_max = 0xfff; 1942 1943 sop->memState[EGR_VLAN_STGm].index_max = 31; 1944 sop->memState[STG_TABm].index_max = 31; 1945 sop->memState[L2MCm].index_max = 255; 1946 1947 sop->memState[TRUNK_BITMAPm].index_max = 15; 1948 sop->memState[TRUNK_EGR_MASKm].index_max = 15; 1949 sop->memState[TRUNK_GROUPm].index_max = 15; 1950 1951 sop->memState[FP_TCAMm].index_max = 511; 1952 sop->memState[FP_TCAM_PLUS_POLICYm].index_max = 511; 1953 sop->memState[FP_POLICY_TABLEm].index_max = 511; 1954 sop->memState[FP_METER_TABLEm].index_max = 511; 1955 sop->memState[FP_COUNTER_TABLEm].index_max = 511; 1956 /* sop->memState[FP_RANGE_CHECKm].index_max = 1;*/ 1957 1958 sop->memState[L3_DEFIPm].index_max = -1; 1959 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1; 1960 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1; 1961 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 1962 sop->memState[L3_ECMPm].index_max = -1; 1963 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = -1; 1964 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = -1; 1965 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = -1; 1966 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = -1; 1967 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = -1; 1968 sop->memState[L3_ENTRY_ONLYm].index_max = -1; 1969 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = -1; 1970 sop->memState[L3_IPMCm].index_max = -1; 1971 sop->memState[L3_TUNNELm].index_max = -1; 1972 sop->memState[MMU_IPMC_GROUP_TBL0m].index_max = -1; 1973 sop->memState[MMU_IPMC_GROUP_TBL1m].index_max = -1; 1974 sop->memState[MMU_IPMC_GROUP_TBL2m].index_max = -1; 1975 sop->memState[MMU_IPMC_GROUP_TBL3m].index_max = -1; 1976 sop->memState[MMU_IPMC_GROUP_TBL4m].index_max = -1; 1977 sop->memState[MMU_IPMC_GROUP_TBL5m].index_max = -1; 1978 sop->memState[MMU_IPMC_GROUP_TBL6m].index_max = -1; 1979 sop->memState[MMU_IPMC_GROUP_TBL7m].index_max = -1; 1980 sop->memState[MMU_IPMC_VLAN_TBLm].index_max = -1; 1981 } 1982 1983 #ifdef BCM_FIREBOLT2_SUPPORT 1984 void 1985 soc_firebolt2_mem_config(int unit) 1986 { 1987 soc_persist_t *sop; 1988 uint32 entry_mask, entry_request; 1989 #ifndef EXCLUDE_BCM56324 1990 uint16 dev_id; 1991 uint8 rev_id; 1992 #endif /* EXCLUDE_BCM56324 */ 1993 1994 sop = SOC_PERSIST(unit); 1995 1996 #ifndef EXCLUDE_BCM56324 1997 soc_cm_get_id(unit, &dev_id, &rev_id); 1998 if ((dev_id == BCM56322_DEVICE_ID) || (dev_id == BCM56324_DEVICE_ID)) { 1999 sop->memState[L2Xm].index_max = 0x3fff; 2000 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = 0xfff; 2001 2002 sop->memState[L3_DEFIPm].index_max = 0x7ff; 2003 sop->memState[L3_DEFIP_ONLYm].index_max = 0x7ff; 2004 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 0x7ff; 2005 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 0x7ff; 2006 sop->memState[FP_TCAMm].index_max = 0x7ff; 2007 sop->memState[FP_POLICY_TABLEm].index_max = 0x7ff; 2008 sop->memState[FP_METER_TABLEm].index_max = 0x7ff; 2009 sop->memState[FP_COUNTER_TABLEm].index_max = 0x7ff; 2010 } 2011 #endif /* EXCLUDE_BCM56324 */ 2012 2013 /* L2 tables */ 2014 entry_mask = sop->memState[L2Xm].index_max; 2015 2016 entry_request = soc_property_get(unit, spn_L2_TABLE_SIZE, entry_mask); 2017 2018 if (entry_request < entry_mask) { 2019 /* Round up to next power of 2 */ 2020 for (entry_mask >>= 1; entry_mask != 0; entry_mask >>= 1) { 2021 if (entry_request & ~entry_mask) { 2022 entry_mask = (entry_mask << 1) | 0x1; 2023 break; 2024 } 2025 } 2026 } 2027 2028 sop->memState[L2Xm].index_max = entry_mask; 2029 sop->memState[L2_ENTRY_ONLYm].index_max = entry_mask; 2030 sop->memState[L2_HITDA_ONLYm].index_max = entry_mask >> 3; 2031 sop->memState[L2_HITSA_ONLYm].index_max = entry_mask >> 3; 2032 2033 /* L3 tables */ 2034 entry_mask = sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max; 2035 2036 entry_request = soc_property_get(unit, spn_L3_TABLE_SIZE, entry_mask); 2037 2038 if (entry_request < entry_mask) { 2039 /* Round up to next power of 2 */ 2040 for (entry_mask >>= 1; entry_mask != 0; entry_mask >>= 1) { 2041 if (entry_request & ~entry_mask) { 2042 entry_mask = (entry_mask << 1) | 0x1; 2043 break; 2044 } 2045 } 2046 } 2047 2048 sop->memState[L3_ENTRY_ONLYm].index_max = entry_mask; 2049 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = entry_mask; 2050 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = entry_mask; 2051 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = entry_mask >> 1; 2052 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = entry_mask >> 2; 2053 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = entry_mask >> 3; 2054 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = entry_mask >> 3; 2055 2056 /* STG tables */ 2057 entry_mask = sop->memState[STG_TABm].index_max; 2058 2059 entry_request = soc_property_get(unit, spn_STG_TABLE_SIZE, entry_mask); 2060 2061 if (entry_request < entry_mask) { 2062 /* Round up to next power of 2 */ 2063 for (entry_mask >>= 1; entry_mask != 0; entry_mask >>= 1) { 2064 if (entry_request & ~entry_mask) { 2065 entry_mask = (entry_mask << 1) | 0x1; 2066 break; 2067 } 2068 } 2069 } 2070 2071 sop->memState[STG_TABm].index_max = entry_mask; 2072 sop->memState[EGR_VLAN_STGm].index_max = entry_mask; 2073 } 2074 #endif /* BCM_FIREBOLT2_SUPPORT */ 2075 2076 #ifdef BCM_RAPTOR_SUPPORT 2077 void 2078 soc_bcm56225_mem_config(int unit) 2079 { 2080 soc_persist_t *sop; 2081 sop = SOC_PERSIST(unit); 2082 2083 sop->memState[L3_DEFIPm].index_max = -1; 2084 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1; 2085 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1; 2086 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 2087 sop->memState[L3_ECMPm].index_max = -1; 2088 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = -1; 2089 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = -1; 2090 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = -1; 2091 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = -1; 2092 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = -1; 2093 sop->memState[L3_ENTRY_ONLYm].index_max = -1; 2094 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = -1; 2095 sop->memState[L3_IPMCm].index_max = -1; 2096 sop->memState[L3_TUNNELm].index_max = -1; 2097 sop->memState[MMU_IPMC_GROUP_TBL0m].index_max = -1; 2098 sop->memState[MMU_IPMC_GROUP_TBL1m].index_max = -1; 2099 sop->memState[MMU_IPMC_GROUP_TBL2m].index_max = -1; 2100 sop->memState[MMU_IPMC_VLAN_TBLm].index_max = -1; 2101 } 2102 2103 void 2104 soc_bcm53724_mem_config(int unit) 2105 { 2106 soc_persist_t *sop; 2107 sop = SOC_PERSIST(unit); 2108 2109 sop->memState[FP_TCAMm].index_max = 511; 2110 sop->memState[FP_POLICY_TABLEm].index_max = 511; 2111 sop->memState[FP_METER_TABLEm].index_max = 511; 2112 sop->memState[FP_COUNTER_TABLEm].index_max = 511; 2113 2114 sop->memState[L3_DEFIPm].index_max = -1; 2115 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1; 2116 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1; 2117 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 2118 sop->memState[L3_ECMPm].index_max = -1; 2119 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = -1; 2120 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = -1; 2121 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = -1; 2122 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = -1; 2123 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = -1; 2124 sop->memState[L3_ENTRY_ONLYm].index_max = -1; 2125 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = -1; 2126 sop->memState[L3_IPMCm].index_max = -1; 2127 sop->memState[L3_TUNNELm].index_max = -1; 2128 sop->memState[MMU_IPMC_GROUP_TBL0m].index_max = -1; 2129 sop->memState[MMU_IPMC_GROUP_TBL1m].index_max = -1; 2130 sop->memState[MMU_IPMC_GROUP_TBL2m].index_max = -1; 2131 sop->memState[MMU_IPMC_VLAN_TBLm].index_max = -1; 2132 2133 sop->memState[L2Xm].index_max = 8191; 2134 sop->memState[L2_ENTRY_ONLYm].index_max = 8191; 2135 sop->memState[L2_HITDA_ONLYm].index_max = 1023; 2136 sop->memState[L2_HITSA_ONLYm].index_max = 1023; 2137 } 2138 #endif /* BCM_RAPTOR_SUPPORT */ 2139 2140 #if defined(BCM_TRIUMPH_SUPPORT) 2141 static int soc_tr_modport_map[9] = {2,14,26,27,28,29,30,31,0}; 2142 #endif 2143 2144 #if defined(BCM_ENDURO_SUPPORT) 2145 static int soc_en_modport_map[5] = {26,27,28,29,0}; 2146 #endif 2147 2148 #if defined(BCM_RAVEN_SUPPORT) 2149 static int soc_rv_modport_map[5] = {1, 2, 4, 5, 0}; 2150 #endif 2151 2152 /* 2153 * Function: 2154 * soc_xgs3_port_to_higig_bitmap 2155 * Purpose: 2156 * Converts Stacking port into HG port bitmap 2157 * Parameters: 2158 * unit - StrataSwitch unit #. 2159 * port - port 2160 * hg_pbm - HG port bitmap value 2161 * Returns: 2162 * SOC_E_XXX 2163 * Note: 2164 * Raptor's port 0 is a CPU port, so -1 should apply in Raptor's 2165 * calculation of HG bitmap from port. 2166 */ 2167 int 2168 soc_xgs3_port_to_higig_bitmap(int unit, soc_port_t port, uint32 *hg_pbm) 2169 { 2170 soc_pbmp_t hg; 2171 SOC_PBMP_CLEAR(hg); 2172 if (!IS_ST_PORT(unit, port)) { 2173 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRX_SUPPORT) 2174 if (SOC_IS_HBX(unit) || SOC_IS_TRX(unit)) { 2175 if (!IS_CPU_PORT(unit, port)) { 2176 return SOC_E_PORT; 2177 } 2178 } else 2179 #endif /* BCM_BRADLEY_SUPPORT */ 2180 { 2181 return SOC_E_PORT; 2182 } 2183 } 2184 2185 #if defined(BCM_BRADLEY_SUPPORT) 2186 if (SOC_IS_HBX(unit)) { 2187 if (SOC_IS_SC_CQ(unit) && port > 24) { 2188 return SOC_E_PORT; 2189 } 2190 *hg_pbm = (1 << port); 2191 } else 2192 #endif /* BCM_BRADLEY_SUPPORT */ 2193 2194 #if defined(BCM_GREYHOUND_SUPPORT) 2195 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || 2196 SOC_IS_GREYHOUND2(unit)) { 2197 *hg_pbm = (1 << port); 2198 return SOC_E_NONE; 2199 } else 2200 #endif /* BCM_BRADLEY_SUPPORT */ 2201 2202 2203 #if defined(BCM_TRIUMPH_SUPPORT) 2204 if (SOC_IS_TR_VL(unit)) { 2205 int i; 2206 #if defined(BCM_ENDURO_SUPPORT) 2207 if(SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit) || 2208 SOC_IS_HURRICANE2(unit)) { 2209 for (i = 0; i < 5; i++) { 2210 if (soc_en_modport_map[i] == port) { 2211 *hg_pbm = 1 << i; 2212 return SOC_E_NONE; 2213 } 2214 } 2215 } else 2216 #endif 2217 { 2218 for (i = 0; i < 9; i++) { 2219 if (soc_tr_modport_map[i] == port) { 2220 *hg_pbm = 1 << i; 2221 return SOC_E_NONE; 2222 } 2223 } 2224 } 2225 return SOC_E_PORT; 2226 } else 2227 #endif /* BCM_TRIUMPH_SUPPORT */ 2228 #if defined(BCM_RAVEN_SUPPORT) 2229 if (SOC_IS_RAVEN(unit)) { 2230 int i; 2231 for (i = 0; i < 5; i++) { 2232 if (soc_rv_modport_map[i] == port) { 2233 *hg_pbm = 1 << i; 2234 return SOC_E_NONE; 2235 } 2236 } 2237 return SOC_E_PORT; 2238 } else 2239 #endif /* BCM_RAVEN_SUPPORT */ 2240 if (SOC_IS_FBX(unit)) { 2241 int hg_port; 2242 /* Other firebolt family devices */ 2243 hg_port = port - SOC_HG_OFFSET(unit); 2244 #ifdef BCM_RAPTOR1_SUPPORT 2245 if (SOC_IS_RAPTOR(unit)) { 2246 hg_port -= 1; /* On Raptor port 0 is CPU port */ 2247 } 2248 #endif 2249 SOC_PBMP_PORT_SET(hg, hg_port); 2250 *hg_pbm = SOC_PBMP_WORD_GET(hg, 0); 2251 } else { 2252 return SOC_E_UNAVAIL; 2253 } 2254 return SOC_E_NONE; 2255 } 2256 2257 /* 2258 * Function: 2259 * soc_xgs3_higig_bitmap_to_port_all 2260 * Purpose: 2261 * Converts HG port bitmap into Stacking port value 2262 * Parameters: 2263 * unit - StrataSwitch unit #. 2264 * hg_pbm - HG port bitmap value 2265 * port_max - size of input array 2266 * port_array - port array 2267 * port_count - size of returned array; 2268 * Returns: 2269 * SOC_E_XXX 2270 * Note: 2271 * Raptor's port 0 is a CPU port, so +1 should apply in Raptor's 2272 * calculation of stacking port from bitmap 2273 */ 2274 int 2275 soc_xgs3_higig_bitmap_to_port_all(int unit, uint32 hg_pbm, 2276 int port_max, soc_port_t *port_array, 2277 int *port_count) 2278 { 2279 soc_pbmp_t hg; 2280 2281 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_SCORPION_SUPPORT) 2282 if (SOC_IS_HBX(unit)){ 2283 int p; 2284 int count = 0; 2285 /* Return all ports found in port map */ 2286 for (p = 0; hg_pbm != 0; p++, hg_pbm >>= 1) { 2287 if (hg_pbm & 1) { 2288 if (port_max != 0) { 2289 if (count < port_max) { 2290 port_array[count] = p; 2291 } else { 2292 break; 2293 } 2294 } 2295 count++; 2296 } 2297 } 2298 if (port_count) { 2299 *port_count = count; 2300 } 2301 return (count > 0) ? SOC_E_NONE : SOC_E_NOT_FOUND; 2302 } else 2303 #endif 2304 #if defined(BCM_TRIUMPH_SUPPORT) 2305 if (SOC_IS_TR_VL(unit)) { 2306 int p; 2307 int count = 0; 2308 /* Return all ports found in port map */ 2309 #if defined(BCM_ENDURO_SUPPORT) 2310 if(SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit) || 2311 SOC_IS_HURRICANE2(unit)) { 2312 for (p = 0; hg_pbm != 0 && p < 5; p++) { 2313 if (hg_pbm & (1 << p)) { 2314 if (port_max != 0) { 2315 if (count < port_max) { 2316 port_array[count] = soc_en_modport_map[p]; 2317 } else { 2318 break; 2319 } 2320 } 2321 count++; 2322 } 2323 } 2324 } else 2325 #endif /* BCM_ENDURO_SUPPORT */ 2326 { 2327 for (p = 0; hg_pbm != 0 && p < 9; p++) { 2328 if (hg_pbm & (1 << p)) { 2329 if (port_max != 0) { 2330 if (count < port_max) { 2331 port_array[count] = soc_tr_modport_map[p]; 2332 } else { 2333 break; 2334 } 2335 } 2336 count++; 2337 } 2338 } 2339 } 2340 if (port_count) { 2341 *port_count = count; 2342 } 2343 return (count > 0) ? SOC_E_NONE : SOC_E_NOT_FOUND; 2344 } else 2345 #endif 2346 #if defined(BCM_RAVEN_SUPPORT) 2347 if (SOC_IS_RAVEN(unit)) { 2348 int p; 2349 int count = 0; 2350 /* Return all ports found in port map */ 2351 for (p = 0; hg_pbm != 0; p++) { 2352 if (hg_pbm & (1 << p)) { 2353 if (port_max != 0) { 2354 if (count < port_max) { 2355 port_array[count] = soc_rv_modport_map[p]; 2356 } else { 2357 break; 2358 } 2359 } 2360 count++; 2361 } 2362 } 2363 if (port_count) { 2364 *port_count = count; 2365 } 2366 return (count > 0) ? SOC_E_NONE : SOC_E_NOT_FOUND; 2367 } else 2368 #endif /* BCM_RAVEN_SUPPORT */ 2369 if (SOC_IS_FBX(unit)) { 2370 int p; 2371 int count = 0; 2372 int offset; 2373 2374 /* On Raptor port 0 is CPU port */ 2375 offset = SOC_IS_RAPTOR(unit) ? 1 : 0; 2376 SOC_PBMP_CLEAR(hg); 2377 /* Other firebolt family devices */ 2378 SOC_PBMP_WORD_SET(hg, 0, hg_pbm); 2379 /* Convert HG bitmap to port array*/ 2380 for (p=0; p<4; p++) { 2381 if (SOC_PBMP_MEMBER(hg, p)) { 2382 if (count < port_max) { 2383 port_array[count] = SOC_HG_OFFSET(unit) + p + offset; 2384 } 2385 if ((port_max != 0) && 2386 (port_max == count)) { 2387 break; 2388 } 2389 count++; 2390 } 2391 } 2392 if (port_count) { 2393 *port_count = count; 2394 } 2395 return (count > 0) ? SOC_E_NONE : SOC_E_NOT_FOUND; 2396 } 2397 return SOC_E_UNAVAIL; 2398 } 2399 2400 /* 2401 * Function: 2402 * soc_xgs3_higig_bitmap_to_port 2403 * Purpose: 2404 * Converts first bit set in HG port bitmap into Stacking port value 2405 * Parameters: 2406 * unit - StrataSwitch unit #. 2407 * hg_pbm - HG port bitmap value 2408 * port - port 2409 * Returns: 2410 * SOC_E_XXX 2411 */ 2412 int 2413 soc_xgs3_higig_bitmap_to_port(int unit, uint32 hg_pbm,soc_port_t *port) 2414 { 2415 return soc_xgs3_higig_bitmap_to_port_all(unit, hg_pbm, 1, port, NULL); 2416 } 2417 2418 /* 2419 * Function: 2420 * soc_xgs3_higig_bitmap_to_bitmap 2421 * Purpose: 2422 * Converts HG port bitmap into absolute port bitmap 2423 * Parameters: 2424 * unit - StrataSwitch unit #. 2425 * hg_pbm - HG port bitmap value 2426 * pbmp (OUT) - absolute port bitmap 2427 * Returns: 2428 * SOC_E_XXX 2429 */ 2430 2431 int 2432 soc_xgs3_higig_bitmap_to_bitmap(int unit, pbmp_t hg_pbmp, pbmp_t *pbmp) 2433 { 2434 #if defined(BCM_RAVEN_SUPPORT) || defined(BCM_TRIUMPH_SUPPORT) 2435 if (SOC_IS_RAVEN(unit) || 2436 (SOC_IS_TR_VL(unit) && 2437 !(SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || 2438 SOC_IS_GREYHOUND2(unit)))) { 2439 soc_port_t hgp; 2440 int *hg_list, len; 2441 2442 hg_list = NULL; 2443 len = 0; 2444 #if defined(BCM_RAVEN_SUPPORT) 2445 if (SOC_IS_RAVEN(unit)) { 2446 hg_list = soc_rv_modport_map; 2447 len = sizeof(soc_rv_modport_map) / sizeof(soc_rv_modport_map[0]); 2448 } 2449 #endif /* BCM_RAVEN_SUPPORT */ 2450 #if defined(BCM_TRIUMPH_SUPPORT) 2451 if (SOC_IS_TR_VL(unit)) { 2452 #if defined(BCM_ENDURO_SUPPORT) 2453 if(SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit) || 2454 SOC_IS_HURRICANE2(unit)) { 2455 hg_list = soc_en_modport_map; 2456 len = sizeof(soc_en_modport_map) / sizeof(soc_en_modport_map[0]); 2457 } else 2458 #endif 2459 { 2460 hg_list = soc_tr_modport_map; 2461 len = sizeof(soc_tr_modport_map) / sizeof(soc_tr_modport_map[0]); 2462 } 2463 } 2464 #endif /* BCM_TRIUMPH_SUPPORT */ 2465 2466 SOC_PBMP_CLEAR(*pbmp); 2467 PBMP_ITER(hg_pbmp, hgp) { 2468 if (hgp >= len) { 2469 return SOC_E_PORT; 2470 } 2471 SOC_PBMP_PORT_ADD(*pbmp, hg_list[hgp]); 2472 } 2473 return SOC_E_NONE; 2474 } else 2475 #endif /* BCM_RAVEN_SUPPORT || BCM_TRIUMPH_SUPPORT */ 2476 if (SOC_IS_FBX(unit)) { 2477 SOC_PBMP_WORD_SET(*pbmp, 0, SOC_PBMP_WORD_GET(hg_pbmp, 0) << SOC_HG_OFFSET(unit)); 2478 return SOC_E_NONE; 2479 } 2480 return SOC_E_UNAVAIL; 2481 } 2482 2483 /* 2484 * Function: 2485 * soc_xgs3_bitmap_to_higig_bitmap 2486 * Purpose: 2487 * Converts absolute port bitmap to HG port bitmap 2488 * Parameters: 2489 * unit - StrataSwitch unit #. 2490 * hg_pbm (OUT) - HG port bitmap value 2491 * pbmp - absolute port bitmap 2492 * Returns: 2493 * SOC_E_XXX 2494 */ 2495 2496 int 2497 soc_xgs3_bitmap_to_higig_bitmap(int unit, pbmp_t pbmp, pbmp_t *hg_pbm) 2498 { 2499 #if defined(BCM_RAVEN_SUPPORT) || defined(BCM_TRIUMPH_SUPPORT) 2500 if (SOC_IS_RAVEN(unit) || 2501 (SOC_IS_TR_VL(unit) && 2502 !(SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || 2503 SOC_IS_GREYHOUND2(unit)))) { 2504 soc_port_t p; 2505 int *hg_list, len, i; 2506 2507 hg_list = NULL; 2508 len = 0; 2509 #if defined(BCM_RAVEN_SUPPORT) 2510 if (SOC_IS_RAVEN(unit)) { 2511 hg_list = soc_rv_modport_map; 2512 len = sizeof(soc_rv_modport_map) / sizeof(soc_rv_modport_map[0]); 2513 } 2514 #endif /* BCM_RAVEN_SUPPORT */ 2515 #if defined(BCM_TRIUMPH_SUPPORT) 2516 if (SOC_IS_TR_VL(unit)) { 2517 #if defined(BCM_ENDURO_SUPPORT) 2518 if(SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit) || 2519 SOC_IS_HURRICANE2(unit)) { 2520 hg_list = soc_en_modport_map; 2521 len = sizeof(soc_en_modport_map) / sizeof(soc_en_modport_map[0]); 2522 } else 2523 #endif 2524 { 2525 hg_list = soc_tr_modport_map; 2526 len = sizeof(soc_tr_modport_map) / sizeof(soc_tr_modport_map[0]); 2527 } 2528 } 2529 #endif /* BCM_TRIUMPH_SUPPORT */ 2530 2531 SOC_PBMP_CLEAR(*hg_pbm); 2532 PBMP_ITER(pbmp, p) { 2533 for (i = 0; i < len; i++) { 2534 if (hg_list[i] == p) { 2535 SOC_PBMP_PORT_ADD(*hg_pbm, i); 2536 break; 2537 } 2538 } 2539 if (i == len) { 2540 return SOC_E_PORT; 2541 } 2542 } 2543 return SOC_E_NONE; 2544 } else 2545 #endif /* BCM_RAVEN_SUPPORT */ 2546 if (SOC_IS_FBX(unit)) { 2547 SOC_PBMP_WORD_SET(*hg_pbm, 0, SOC_PBMP_WORD_GET(pbmp, 0) >> SOC_HG_OFFSET(unit)); 2548 return SOC_E_NONE; 2549 } 2550 return SOC_E_UNAVAIL; 2551 } 2552 2553 /* 2554 * Function: 2555 * soc_xgs3_higig_bitmap_to_higig_port_num 2556 * Purpose: 2557 * Converts HG port bitmap into higig port number 2558 * Parameters: 2559 * hg_pbm - HG port bitmap value 2560 * hg_port_num - HG port num 2561 * Returns: 2562 * Higig port number - e.g. hg1 would be 1 2563 */ 2564 2565 int 2566 soc_xgs3_higig_bitmap_to_higig_port_num(uint32 hg_pbm, uint32 *hg_port_num) 2567 { 2568 int result = 0; 2569 /* If empty pbm passed - configuration error */ 2570 if (!hg_pbm) { 2571 return (SOC_E_CONFIG); 2572 } 2573 while (hg_pbm > 0) { 2574 hg_pbm = hg_pbm >> 1; 2575 result++; 2576 } 2577 2578 *hg_port_num = result - 1; 2579 2580 return (SOC_E_NONE); 2581 } 2582 2583 int 2584 soc_xgs3_port_num_to_higig_port_num(int unit, int port, int *hg_port) 2585 { 2586 2587 #if defined(BCM_TRIUMPH_SUPPORT) 2588 if (SOC_IS_TR_VL(unit)) { 2589 int *hg_list, len, i; 2590 2591 hg_list = NULL; 2592 len = 0; 2593 #if defined(BCM_ENDURO_SUPPORT) 2594 if(SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit) || 2595 SOC_IS_HURRICANE2(unit)) { 2596 hg_list = soc_en_modport_map; 2597 len = sizeof(soc_en_modport_map) / sizeof(soc_en_modport_map[0]); 2598 } else 2599 #endif 2600 { 2601 hg_list = soc_tr_modport_map; 2602 len = sizeof(soc_tr_modport_map) / sizeof(soc_tr_modport_map[0]); 2603 } 2604 for (i = 0; i < len; i++) { 2605 if (hg_list[i] == port) { 2606 *hg_port = i; 2607 return SOC_E_NONE; 2608 } 2609 } 2610 } 2611 #endif /* BCM_TRIUMPH_SUPPORT */ 2612 2613 #if defined(BCM_SCORPION_SUPPORT) 2614 if (SOC_IS_SC_CQ(unit)) { 2615 if (port > 0 && port < 25) { 2616 *hg_port = port; 2617 return SOC_E_NONE; 2618 } 2619 } 2620 #endif /* BCM_SCORPION_SUPPORT */ 2621 2622 #if defined(BCM_BRADLEY_SUPPORT) 2623 if (SOC_IS_HB_GW(unit)) { 2624 if (port > 0 && port < 21) { 2625 *hg_port = port; 2626 return SOC_E_NONE; 2627 } 2628 } 2629 #endif /* BCM_BRADLEY_SUPPORT */ 2630 2631 return SOC_E_PORT; 2632 } 2633 2634 #endif /* BCM_FIREBOLT_SUPPORT */