cprif_drv.c (574985B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 #include <shared/bsl.h> 10 #include <soc/error.h> 11 #include <soc/esw/port.h> 12 #include <soc/cprimod/cprimod.h> 13 #include <soc/cprimod/cprimod_internal.h> 14 #include <soc/cprimod/cprimod_dispatch.h> 15 #include <soc/cprimod/cprif_drv.h> 16 #include <soc/cprimod/cprif_drv_private.h> 17 #include "../../../../libs/phymod/chip/falcon_dpll/tier1/falcon_dpll_cfg_seq.h" 18 #include "../../../../libs/phymod/chip/falcon_dpll/tier1/falcon2_monterey_interface.h" 19 20 21 #ifdef _ERR_MSG_MODULE_NAME 22 #error "_ERR_MSG_MODULE_NAME redefined" 23 #endif 24 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_PORT 25 26 #ifdef CPRIMOD_CPRI_FALCON_SUPPORT 27 28 #define CPRIF_DRV_NUMBER_OF_MSG 1920 29 #define CPRIF_DRV_N_MG_IN_MSTR_FRM 21 30 #define CPRIF_DRV_RSVD4_MSG_SIZE 19 31 32 #define CPRIF_DRV_MEM_PREP phy_port = SOC_INFO(unit).port_l2p_mapping[port]; \ 33 port_core_index = ((phy_port-1)%4); \ 34 local_mem = mem_select[port_core_index]; \ 35 num_words = soc_mem_entry_words(unit, local_mem); \ 36 mem_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); \ 37 SOC_NULL_CHECK(mem_data_ptr); \ 38 sal_memset(mem_data_ptr, 0, sizeof(uint32) * num_words); 39 40 int cprif_pm_version_get(int unit, soc_port_t port, cprif_pm_version_t *pm_version) 41 { 42 uint32 reg_val; 43 SOC_INIT_FUNC_DEFS; 44 45 if (!SOC_REG_IS_VALID(unit, CLPORT_PM_VERSION_IDr)) { 46 pm_version->pm_type = 0xFFFF; 47 pm_version->tech_process = 0xFFFF; 48 pm_version->rev_number = 0xFFFF; 49 pm_version->rev_letter = 0xFFFF; 50 } else { 51 _SOC_IF_ERR_EXIT(READ_CLPORT_PM_VERSION_IDr(unit, port, ®_val)); 52 pm_version->pm_type = soc_reg_field_get(unit, CLPORT_PM_VERSION_IDr, reg_val,PM_TYPEf ); 53 pm_version->tech_process = soc_reg_field_get(unit, CLPORT_PM_VERSION_IDr, reg_val,TECH_PROCESSf ); 54 pm_version->rev_number = soc_reg_field_get(unit, CLPORT_PM_VERSION_IDr, reg_val,REV_NUMBERf ); 55 pm_version->rev_letter = soc_reg_field_get(unit, CLPORT_PM_VERSION_IDr, reg_val,REV_LETTERf ); 56 } 57 58 exit: 59 SOC_FUNC_RETURN; 60 } 61 62 int cprif_bfa_bfp_table_entry_t_init( cprif_bfa_bfp_table_entry_t* cprimod_bfa_bfp_table_entry) 63 { 64 SOC_INIT_FUNC_DEFS; 65 66 if (cprimod_bfa_bfp_table_entry == NULL) { 67 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprimod_bfa_bfp_table_entry NULL parameter")); 68 } 69 sal_memset(cprimod_bfa_bfp_table_entry, 0, sizeof(cprif_bfa_bfp_table_entry_t)); 70 cprimod_bfa_bfp_table_entry->axc_id = 0; 71 cprimod_bfa_bfp_table_entry->rsrv_bit_cnt = 0; 72 cprimod_bfa_bfp_table_entry->data_bit_cnt = 0; 73 74 exit: 75 SOC_FUNC_RETURN; 76 77 } 78 79 int cprif_cpri_container_map_entry_t_init( cprif_cpri_container_map_entry_t* cprif_cpri_container_map_entry) 80 { 81 SOC_INIT_FUNC_DEFS; 82 83 if (cprif_cpri_container_map_entry == NULL) { 84 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_cpri_container_map_entry NULL parameter")); 85 } 86 sal_memset(cprif_cpri_container_map_entry, 0, sizeof(cprif_cpri_container_map_entry_t)); 87 cprif_cpri_container_map_entry->map_method = 0; 88 cprif_cpri_container_map_entry->axc_id = 0; 89 cprif_cpri_container_map_entry->stuffing_at_end = 0; 90 cprif_cpri_container_map_entry->stuff_cnt = 0; 91 cprif_cpri_container_map_entry->cblk_cnt = 0; 92 cprif_cpri_container_map_entry->naxc_cnt = 0; 93 cprif_cpri_container_map_entry->Nv = 0; 94 cprif_cpri_container_map_entry->Na = 0; 95 cprif_cpri_container_map_entry->rfrm_sync = 0; 96 cprif_cpri_container_map_entry->hfrm_sync = 0; 97 cprif_cpri_container_map_entry->bfn_offset = 0; 98 cprif_cpri_container_map_entry->hfn_offset = 0; 99 cprif_cpri_container_map_entry->bfrm_offset = 0; 100 101 102 exit: 103 SOC_FUNC_RETURN; 104 105 } 106 107 int cprif_rsvd4_container_map_entry_t_init( cprif_rsvd4_container_map_entry_t* cprif_rsvd4_container_map_entry) 108 { 109 SOC_INIT_FUNC_DEFS; 110 111 if (cprif_rsvd4_container_map_entry == NULL) { 112 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_rsvd4_container_map_entry NULL parameter")); 113 } 114 sal_memset(cprif_rsvd4_container_map_entry, 0, sizeof(cprif_rsvd4_container_map_entry_t)); 115 cprif_rsvd4_container_map_entry->map_method = 0; 116 cprif_rsvd4_container_map_entry->axc_id = 0; 117 cprif_rsvd4_container_map_entry->stuffing_at_end = 0; 118 cprif_rsvd4_container_map_entry->stuff_cnt = 0; 119 cprif_rsvd4_container_map_entry->cblk_cnt = 0; 120 cprif_rsvd4_container_map_entry->rfrm_offset = 0; 121 cprif_rsvd4_container_map_entry->bfn_offset = 0; 122 cprif_rsvd4_container_map_entry->msg_ts_mode = 0; 123 cprif_rsvd4_container_map_entry->rfrm_sync = 0; 124 cprif_rsvd4_container_map_entry->hfrm_sync = 0; 125 cprif_rsvd4_container_map_entry->msg_ts_cnt = 0; 126 cprif_rsvd4_container_map_entry->msg_ts_sync = 0; 127 cprif_rsvd4_container_map_entry->use_ts_dbm = 0; 128 cprif_rsvd4_container_map_entry->ts_dbm_prof_num = 0; 129 cprif_rsvd4_container_map_entry->num_active_slots = 0; 130 cprif_rsvd4_container_map_entry->msg_addr = 0; 131 cprif_rsvd4_container_map_entry->msg_type = 0; 132 cprif_rsvd4_container_map_entry->msg_ts_offset = 0; 133 134 135 exit: 136 SOC_FUNC_RETURN; 137 138 } 139 140 int cprif_iq_buffer_config_t_init( cprif_iq_buffer_config_t* cprif_iq_buffer_config_entry) 141 { 142 SOC_INIT_FUNC_DEFS; 143 144 if (cprif_iq_buffer_config_entry == NULL) { 145 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_iq_buffer_config_entry NULL parameter")); 146 } 147 sal_memset(cprif_iq_buffer_config_entry, 0, sizeof(cprif_iq_buffer_config_t)); 148 cprif_iq_buffer_config_entry->payload_size = 0; 149 cprif_iq_buffer_config_entry->last_packet_num = 0; 150 cprif_iq_buffer_config_entry->last_payload_size = 0; 151 152 exit: 153 SOC_FUNC_RETURN; 154 155 } 156 157 int cprif_encap_decap_data_entry_t_init( cprif_encap_decap_data_entry_t* cprif_encap_decap_data_entry) 158 { 159 SOC_INIT_FUNC_DEFS; 160 161 if (cprif_encap_decap_data_entry == NULL) { 162 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_encap_decap_data_entry NULL parameter")); 163 } 164 sal_memset(cprif_encap_decap_data_entry, 0, sizeof(cprif_encap_decap_data_entry_t)); 165 cprif_encap_decap_data_entry->sample_size = 0; 166 cprif_encap_decap_data_entry->out_sample_size = 0; 167 cprif_encap_decap_data_entry->valid = 0; 168 cprif_encap_decap_data_entry->mux_enable = 0; 169 cprif_encap_decap_data_entry->queue_size = 0; 170 cprif_encap_decap_data_entry->queue_offset = 0; 171 cprif_encap_decap_data_entry->sign_ext_enable = 0; 172 cprif_encap_decap_data_entry->sign_ext_type = CPRIF_DATA_SIGN_EXT_15_TO_16; 173 cprif_encap_decap_data_entry->bit_reversal = 0; 174 cprif_encap_decap_data_entry->tx_cycle_size = 0; 175 176 exit: 177 SOC_FUNC_RETURN; 178 } 179 180 int cprif_rsvd4_encap_decap_data_entry_t_init( cprif_rsvd4_encap_decap_data_entry_t* cprif_rsvd4_encap_decap_data_entry) 181 { 182 SOC_INIT_FUNC_DEFS; 183 184 if (cprif_rsvd4_encap_decap_data_entry == NULL) { 185 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_rsvd4_encap_decap_data_entry NULL parameter")); 186 } 187 sal_memset(cprif_rsvd4_encap_decap_data_entry, 0, sizeof(cprif_rsvd4_encap_decap_data_entry_t)); 188 cprif_rsvd4_encap_decap_data_entry->gsm_pad_size = 0; 189 cprif_rsvd4_encap_decap_data_entry->gsm_extra_pad_size = 0; 190 cprif_rsvd4_encap_decap_data_entry->gsm_pad_enable = 0; 191 cprif_rsvd4_encap_decap_data_entry->gsm_control_location = 0; 192 cprif_rsvd4_encap_decap_data_entry->valid = 0; 193 cprif_rsvd4_encap_decap_data_entry->queue_size = 0; 194 cprif_rsvd4_encap_decap_data_entry->queue_offset = 0; 195 cprif_rsvd4_encap_decap_data_entry->tx_cycle_size = 0; 196 197 exit: 198 SOC_FUNC_RETURN; 199 } 200 201 int cprif_encap_header_entry_t_init( cprif_encap_header_entry_t* cprif_encap_header_entry) 202 { 203 SOC_INIT_FUNC_DEFS; 204 205 if (cprif_encap_header_entry == NULL) { 206 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_encap_header_entry NULL parameter")); 207 } 208 sal_memset(cprif_encap_header_entry, 0, sizeof(cprif_encap_header_entry_t)); 209 cprif_encap_header_entry->header_type = 0; 210 cprif_encap_header_entry->ver = 0; 211 cprif_encap_header_entry->pkttype = 0; 212 cprif_encap_header_entry->flow_id = 0; 213 cprif_encap_header_entry->ordering_info_index = 0; 214 cprif_encap_header_entry->mac_da_index = 0; 215 cprif_encap_header_entry->mac_sa_index = 0; 216 cprif_encap_header_entry->vlan_type = 0; 217 cprif_encap_header_entry->vlan_id_0_index = 0; 218 cprif_encap_header_entry->vlan_id_1_index = 0; 219 cprif_encap_header_entry->vlan_0_priority = 0; 220 cprif_encap_header_entry->vlan_1_priority = 0; 221 cprif_encap_header_entry->ether_type_index = 0; 222 cprif_encap_header_entry->use_tagid_for_vlan = 0; 223 cprif_encap_header_entry->use_tagid_for_flowid = 0; 224 cprif_encap_header_entry->use_opcode = 0; 225 cprif_encap_header_entry->roe_opcode = 0; 226 cprif_encap_header_entry->tsn_bitmap = 0; 227 cprif_encap_header_entry->gsm_q_cnt_disable = 0; 228 229 exit: 230 SOC_FUNC_RETURN; 231 } 232 233 int cprif_encap_ordering_info_entry_t_init( cprif_encap_ordering_info_entry_t* cprif_encap_ordering_info_entry) 234 { 235 SOC_INIT_FUNC_DEFS; 236 237 if (cprif_encap_ordering_info_entry == NULL) { 238 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_encap_ordering_info_entry NULL parameter")); 239 } 240 sal_memset(cprif_encap_ordering_info_entry, 0, sizeof(cprif_encap_ordering_info_entry_t)); 241 cprif_encap_ordering_info_entry->type = 0; 242 cprif_encap_ordering_info_entry->p_size = 0; 243 cprif_encap_ordering_info_entry->q_size = 0; 244 cprif_encap_ordering_info_entry->max = 0; 245 cprif_encap_ordering_info_entry->increment = 0; 246 cprif_encap_ordering_info_entry->pcnt_prop = 0; 247 cprif_encap_ordering_info_entry->qcnt_prop = 0; 248 249 exit: 250 SOC_FUNC_RETURN; 251 } 252 253 int cprif_decap_ordering_info_entry_t_init( cprif_decap_ordering_info_entry_t* cprif_decap_ordering_info_entry) 254 { 255 SOC_INIT_FUNC_DEFS; 256 257 if (cprif_decap_ordering_info_entry == NULL) { 258 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_decap_ordering_info_entry NULL parameter")); 259 } 260 sal_memset(cprif_decap_ordering_info_entry, 0, sizeof(cprif_decap_ordering_info_entry_t)); 261 262 cprif_decap_ordering_info_entry->type = 0; 263 cprif_decap_ordering_info_entry->p_size = 0x20; 264 cprif_decap_ordering_info_entry->q_size = 0; 265 cprif_decap_ordering_info_entry->max = 0xFFFFFFFF; 266 cprif_decap_ordering_info_entry->increment = 1; 267 cprif_decap_ordering_info_entry->pcnt_inc_p2 = 1; 268 cprif_decap_ordering_info_entry->qcnt_inc_p2 = 0; 269 cprif_decap_ordering_info_entry->pcnt_extended = 0; 270 cprif_decap_ordering_info_entry->pcnt_pkt_count = 0; 271 cprif_decap_ordering_info_entry->modulo_2 = 1; 272 cprif_decap_ordering_info_entry->bias = 1; 273 cprif_decap_ordering_info_entry->gsm_tsn_bitmap = 0x55; 274 275 exit: 276 SOC_FUNC_RETURN; 277 } 278 279 280 int cprif_header_compare_entry_t_init( cprif_header_compare_entry_t* cprif_header_compare_entry) 281 { 282 SOC_INIT_FUNC_DEFS; 283 284 if (cprif_header_compare_entry == NULL) { 285 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_header_compare_entry NULL parameter")); 286 } 287 sal_memset(cprif_header_compare_entry, 0, sizeof(cprif_header_compare_entry_t)); 288 289 cprif_header_compare_entry->valid = 0; 290 cprif_header_compare_entry->match_data = 0; 291 cprif_header_compare_entry->mask = 0; 292 cprif_header_compare_entry->flow_id = 0xFF; 293 cprif_header_compare_entry->ctrl_flow = 0; 294 295 exit: 296 SOC_FUNC_RETURN; 297 } 298 299 300 int cprif_modulo_rule_entry_t_init( cprif_modulo_rule_entry_t* cprif_modulo_rule_entry) 301 { 302 SOC_INIT_FUNC_DEFS; 303 304 if (cprif_modulo_rule_entry == NULL) { 305 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_modulo_rule_entry NULL parameter")); 306 } 307 sal_memset(cprif_modulo_rule_entry, 0, sizeof(cprif_modulo_rule_entry_t)); 308 309 cprif_modulo_rule_entry->active = 0; 310 cprif_modulo_rule_entry->modulo = 0; 311 cprif_modulo_rule_entry->modulo_index = 0; 312 cprif_modulo_rule_entry->dbm_enable = 0xFF; 313 cprif_modulo_rule_entry->flow_id = 0xFF; 314 cprif_modulo_rule_entry->ctrl_flow = 0; 315 316 317 exit: 318 SOC_FUNC_RETURN; 319 } 320 321 322 int cprif_rsvd4_dbm_rule_entry_t_init( cprif_rsvd4_dbm_rule_entry_t* cprif_rsvd4_dbm_rule_entry) 323 { 324 SOC_INIT_FUNC_DEFS; 325 326 if (cprif_rsvd4_dbm_rule_entry == NULL) { 327 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_rsvd4_dbm_rule_entry NULL parameter")); 328 } 329 sal_memset(cprif_rsvd4_dbm_rule_entry, 0, sizeof(cprif_rsvd4_dbm_rule_entry_t)); 330 331 cprif_rsvd4_dbm_rule_entry->bm1_mult = 0; 332 cprif_rsvd4_dbm_rule_entry->bm1[0]= 0; 333 cprif_rsvd4_dbm_rule_entry->bm1[1]= 0; 334 cprif_rsvd4_dbm_rule_entry->bm1[2]= 0; 335 cprif_rsvd4_dbm_rule_entry->bm1_size = 0; 336 cprif_rsvd4_dbm_rule_entry->bm2[0]= 0; 337 cprif_rsvd4_dbm_rule_entry->bm2[1]= 0; 338 cprif_rsvd4_dbm_rule_entry->bm2_size = 0; 339 cprif_rsvd4_dbm_rule_entry->num_slots = 0; 340 cprif_rsvd4_dbm_rule_entry->pos_index = 0; 341 cprif_rsvd4_dbm_rule_entry->pos_entries = 0; 342 343 exit: 344 SOC_FUNC_RETURN; 345 } 346 347 348 int cprif_rsvd4_secondary_dbm_rule_entry_t_init( cprif_rsvd4_secondary_dbm_rule_entry_t* cprif_rsvd4_secondary_dbm_rule_entry) 349 { 350 SOC_INIT_FUNC_DEFS; 351 352 if (cprif_rsvd4_secondary_dbm_rule_entry == NULL) { 353 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_rsvd4_secondary_dbm_rule_entry NULL parameter")); 354 } 355 sal_memset(cprif_rsvd4_secondary_dbm_rule_entry, 0, sizeof(cprif_rsvd4_secondary_dbm_rule_entry_t)); 356 357 cprif_rsvd4_secondary_dbm_rule_entry->bm1_mult = 0; 358 cprif_rsvd4_secondary_dbm_rule_entry->bm1 = 0; 359 cprif_rsvd4_secondary_dbm_rule_entry->bm1_size = 0; 360 cprif_rsvd4_secondary_dbm_rule_entry->bm2= 0; 361 cprif_rsvd4_secondary_dbm_rule_entry->bm2_size = 0; 362 cprif_rsvd4_secondary_dbm_rule_entry->num_slots = 0; 363 364 exit: 365 SOC_FUNC_RETURN; 366 } 367 368 int cprif_rsvd4_dbm_pos_table_entry_t_init( cprif_rsvd4_dbm_pos_table_entry_t* cprif_rsvd4_dbm_pos_table_entry) 369 { 370 SOC_INIT_FUNC_DEFS; 371 372 if (cprif_rsvd4_dbm_pos_table_entry == NULL) { 373 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("cprif_rsvd4_dbm_pos_table_entry NULL parameter")); 374 } 375 sal_memset(cprif_rsvd4_dbm_pos_table_entry, 0, sizeof(cprif_rsvd4_dbm_pos_table_entry_t)); 376 377 cprif_rsvd4_dbm_pos_table_entry->valid = 0; 378 cprif_rsvd4_dbm_pos_table_entry->flow_id = 0; 379 cprif_rsvd4_dbm_pos_table_entry->ctrl_flow = 0; 380 cprif_rsvd4_dbm_pos_table_entry->flow_index = 0; 381 382 exit: 383 SOC_FUNC_RETURN; 384 } 385 386 int cprif_drv_basic_frame_parser_active_table_set(int unit, int port, uint8 table) 387 { 388 uint32 reg_val; 389 uint32 field_buf; 390 SOC_INIT_FUNC_DEFS; 391 392 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, ®_val)); 393 field_buf = table; 394 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 395 BFRM_MAP_TAB_IDf, field_buf); 396 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXFRM_BFRM_CTRLr(unit, port, reg_val)); 397 398 exit: 399 SOC_FUNC_RETURN; 400 401 } 402 403 int cprif_drv_basic_frame_parser_active_table_get(int unit, int port, uint8* table) 404 { 405 uint32 reg_val; 406 uint32 field_buf; 407 SOC_INIT_FUNC_DEFS; 408 409 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, ®_val)); 410 field_buf = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val, BFRM_MAP_TAB_IDf); 411 *table = field_buf; 412 413 exit: 414 SOC_FUNC_RETURN; 415 } 416 417 int cprif_drv_basic_frame_parser_table_num_entries_set(int unit, int port, uint8 table, uint32 num_entries) 418 { 419 uint32 reg_val; 420 uint32 active_table; 421 uint32 field_buf; 422 SOC_INIT_FUNC_DEFS; 423 424 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, ®_val)); 425 426 active_table = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val, BFRM_MAP_TAB_IDf); 427 428 /* 429 * Check to see if it is trying to change number of entries to active table. 430 */ 431 if (active_table == table) { 432 _SOC_EXIT_WITH_ERR(SOC_E_PARAM,(_SOC_MSG("cannot change number of entries of active table."))); 433 } 434 435 field_buf = num_entries; 436 if (table == 0) { 437 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 438 NUM_VLD_ENTRIES_TAB0f, field_buf); 439 } else { 440 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 441 NUM_VLD_ENTRIES_TAB1f, field_buf); 442 } 443 444 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXFRM_BFRM_CTRLr(unit, port, reg_val)); 445 446 exit: 447 SOC_FUNC_RETURN; 448 } 449 450 int cprif_drv_basic_frame_parser_table_num_entries_get(int unit, int port, uint8 table, uint32* num_entries) 451 { 452 uint32 reg_val; 453 uint32 field_buf; 454 SOC_INIT_FUNC_DEFS; 455 456 if (num_entries == NULL) { 457 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("num_entries NULL parameter")); 458 } 459 460 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, ®_val)); 461 if (table == 0) { 462 field_buf = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val,NUM_VLD_ENTRIES_TAB0f); 463 } else { 464 field_buf = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val,NUM_VLD_ENTRIES_TAB1f); 465 } 466 467 *num_entries = field_buf; 468 469 exit: 470 SOC_FUNC_RETURN; 471 472 } 473 474 int cprif_drv_rx_framer_agnostic_mode_set(int unit, int port, uint32 axc_id, int enable, cprimod_agnostic_mode_type_t mode) 475 { 476 uint32 reg_val; 477 uint32 field_buf; 478 uint32 tunnel_mode = FALSE; 479 uint32 rx_agnostic_mode = FALSE; 480 cprif_pm_version_t pm_version; 481 SOC_INIT_FUNC_DEFS; 482 483 _SOC_IF_ERR_EXIT 484 (cprif_pm_version_get(unit, port, &pm_version)); 485 486 if (CPRIF_CLPORT_IS_A0(pm_version)) { 487 if ((mode == cprimod_agnostic_mode_rsvd4) || 488 (mode == cprimod_agnostic_mode_tunnel)) { 489 490 LOG_CLI(("This feature is not supported in A0.\n")); 491 return SOC_E_UNAVAIL; 492 } 493 } 494 495 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, ®_val)); 496 497 if (enable) { 498 switch (mode) { 499 case cprimod_agnostic_mode_cpri: 500 field_buf = axc_id; 501 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 502 FWD_CW_TO_ENCAP_AXCC_IDf, field_buf); 503 504 field_buf = TRUE ; 505 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 506 FWD_CW_TO_ENCAPf, field_buf); 507 508 rx_agnostic_mode = FALSE ; 509 tunnel_mode = FALSE; 510 511 break; 512 513 case cprimod_agnostic_mode_rsvd4: 514 515 field_buf = FALSE ; 516 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 517 FWD_CW_TO_ENCAPf, field_buf); 518 519 field_buf = FALSE ; 520 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 521 BRCM_RESERVED_CPM_306_0f, field_buf); 522 523 rx_agnostic_mode = TRUE; 524 tunnel_mode = FALSE; 525 526 break; 527 528 case cprimod_agnostic_mode_tunnel: 529 530 field_buf = FALSE ; 531 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 532 FWD_CW_TO_ENCAPf, field_buf); 533 534 rx_agnostic_mode = FALSE ; 535 tunnel_mode = TRUE; 536 537 break; 538 539 default: 540 break; 541 } 542 543 } else { /* Disable */ 544 field_buf = FALSE ; 545 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 546 FWD_CW_TO_ENCAPf, field_buf); 547 548 if (mode == cprimod_agnostic_mode_rsvd4) { 549 field_buf = TRUE; 550 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 551 BRCM_RESERVED_CPM_306_0f, field_buf); 552 } 553 554 rx_agnostic_mode = FALSE ; 555 tunnel_mode = FALSE; 556 } 557 558 if (CPRIF_CLPORT_IS_B0(pm_version)) { 559 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 560 RXFRM_TUNNEL_MODEf, tunnel_mode); 561 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 562 RXFRM_AGNOSTIC_MODE_ENf, rx_agnostic_mode); 563 } 564 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXFRM_BFRM_CTRLr(unit, port, reg_val)); 565 566 exit: 567 SOC_FUNC_RETURN; 568 569 } 570 571 int cprif_drv_rx_framer_agnostic_mode_get(int unit, int port,uint32* axc_id, int* enable, cprimod_agnostic_mode_type_t* mode) 572 { 573 uint32 reg_val; 574 uint32 field_buf; 575 int tunnel_mode = 0; 576 int rsvd4_agnostic = 0; 577 int fwd_cw =0; 578 cprif_pm_version_t pm_version; 579 SOC_INIT_FUNC_DEFS; 580 581 _SOC_IF_ERR_EXIT 582 (cprif_pm_version_get(unit, port, &pm_version)); 583 584 585 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, ®_val)); 586 587 if (CPRIF_CLPORT_IS_B0(pm_version)) { 588 field_buf = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val, 589 RXFRM_TUNNEL_MODEf); 590 tunnel_mode = field_buf ? 1:0; 591 592 field_buf = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val, 593 RXFRM_AGNOSTIC_MODE_ENf); 594 rsvd4_agnostic = field_buf ? 1:0; 595 } 596 597 field_buf = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val, 598 FWD_CW_TO_ENCAPf); 599 fwd_cw = field_buf ? 1:0; 600 601 *axc_id = 0; 602 603 if (tunnel_mode) { 604 *mode = cprimod_agnostic_mode_tunnel; 605 *enable = TRUE; 606 } else if (rsvd4_agnostic) { 607 *mode = cprimod_agnostic_mode_rsvd4; 608 *enable = TRUE; 609 } else if (fwd_cw) { 610 *mode = cprimod_agnostic_mode_cpri; 611 *enable = TRUE; 612 *axc_id = soc_reg_field_get(unit, CPRI_RXFRM_BFRM_CTRLr, reg_val, 613 FWD_CW_TO_ENCAP_AXCC_IDf); 614 } else { 615 *enable = FALSE; 616 } 617 618 exit: 619 SOC_FUNC_RETURN; 620 621 } 622 int cprif_drv_tx_framer_rsvd4_agnostic_mode_set(int unit, int port, int enable) 623 { 624 uint64 data; 625 uint64 write_val; 626 SOC_INIT_FUNC_DEFS; 627 628 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_2r(unit, port, &data)); 629 630 /* 631 * In RSVD4 agnostic, the framer is not run in RSVD4 mode. 632 */ 633 634 if(enable) { 635 COMPILER_64_SET(write_val, 0, 0); 636 } else { 637 COMPILER_64_SET(write_val, 0, 1); 638 } 639 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_2r, &data, 640 BRCM_RESERVED_CPM_2_0f, write_val); 641 642 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_2r(unit, port, data)); 643 644 SOC_FUNC_RETURN; 645 } 646 647 int cprif_drv_basic_frame_parser_cw_to_encap_config_set(int unit, int port, uint32 axc_id, int fwd_cw_to_encap) 648 { 649 uint32 reg_val; 650 uint32 field_buf; 651 SOC_INIT_FUNC_DEFS; 652 653 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, ®_val)); 654 655 field_buf = axc_id; 656 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 657 FWD_CW_TO_ENCAP_AXCC_IDf, field_buf); 658 659 field_buf = fwd_cw_to_encap ? 1:0 ; 660 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, ®_val, 661 FWD_CW_TO_ENCAPf, field_buf); 662 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXFRM_BFRM_CTRLr(unit, port, reg_val)); 663 664 exit: 665 SOC_FUNC_RETURN; 666 667 } 668 669 int cprif_drv_basic_frame_assembly_active_table_set(int unit, int port, uint8 table) 670 { 671 uint32 reg_val; 672 uint32 field_buf; 673 SOC_INIT_FUNC_DEFS; 674 675 676 _SOC_IF_ERR_EXIT(READ_CPRI_TXFRM_BFA_CTRLr(unit, port, ®_val)); 677 field_buf = table; 678 soc_reg_field_set(unit, CPRI_TXFRM_BFA_CTRLr, ®_val, BFA_MAP_TAB_IDf, field_buf); 679 680 _SOC_IF_ERR_EXIT(WRITE_CPRI_TXFRM_BFA_CTRLr(unit, port, reg_val)); 681 682 exit: 683 SOC_FUNC_RETURN; 684 685 } 686 687 688 int cprif_drv_basic_frame_assembly_active_table_get(int unit, int port, uint8* table) 689 { 690 uint32 reg_val; 691 uint32 field_buf; 692 SOC_INIT_FUNC_DEFS; 693 694 _SOC_IF_ERR_EXIT(READ_CPRI_TXFRM_BFA_CTRLr(unit, port, ®_val)); 695 field_buf = soc_reg_field_get(unit, CPRI_TXFRM_BFA_CTRLr, reg_val, BFA_MAP_TAB_IDf); 696 697 *table = field_buf; 698 699 exit: 700 SOC_FUNC_RETURN; 701 } 702 703 int cprif_drv_basic_frame_assembly_table_num_entries_set(int unit, int port, uint8 table, uint32 num_entries) 704 { 705 uint32 reg_val; 706 uint32 field_buf; 707 uint32 active_table; 708 SOC_INIT_FUNC_DEFS; 709 710 _SOC_IF_ERR_EXIT(READ_CPRI_TXFRM_BFA_CTRLr(unit, port, ®_val)); 711 712 active_table = soc_reg_field_get(unit, CPRI_TXFRM_BFA_CTRLr, reg_val, BFA_MAP_TAB_IDf); 713 /* 714 * Check to see if it is trying to change number of entries to active table. 715 */ 716 717 if (active_table == table) { 718 _SOC_EXIT_WITH_ERR(SOC_E_PARAM,(_SOC_MSG("cannot change number of entries of active table."))); 719 } 720 721 field_buf = num_entries; 722 if (table == 0) { 723 soc_reg_field_set(unit, CPRI_TXFRM_BFA_CTRLr, ®_val, 724 BFA_NUM_VLD_ENTRIES_TAB0f, field_buf); 725 } else { 726 soc_reg_field_set(unit, CPRI_TXFRM_BFA_CTRLr, ®_val, 727 BFA_NUM_VLD_ENTRIES_TAB1f, field_buf); 728 } 729 730 _SOC_IF_ERR_EXIT(WRITE_CPRI_TXFRM_BFA_CTRLr(unit, port, reg_val)); 731 732 exit: 733 SOC_FUNC_RETURN; 734 735 } 736 737 int cprif_drv_basic_frame_assembly_table_num_entries_get(int unit, int port, uint8 table, uint32* num_entries) 738 { 739 uint32 reg_val; 740 uint32 field_buf; 741 SOC_INIT_FUNC_DEFS; 742 743 _SOC_IF_ERR_EXIT(READ_CPRI_TXFRM_BFA_CTRLr(unit, port, ®_val)); 744 745 if (table == 0) { 746 field_buf = soc_reg_field_get(unit, CPRI_TXFRM_BFA_CTRLr, reg_val,NUM_VLD_ENTRIES_TAB0f); 747 } else { 748 field_buf = soc_reg_field_get(unit, CPRI_TXFRM_BFA_CTRLr, reg_val,NUM_VLD_ENTRIES_TAB1f); 749 } 750 *num_entries = field_buf; 751 exit: 752 SOC_FUNC_RETURN; 753 754 } 755 756 int cprif_drv_basic_frame_entry_set(int unit, int port, 757 uint8 table, 758 cprimod_direction_t dir, 759 uint8 index, 760 const cprif_bfa_bfp_table_entry_t *entry) 761 { 762 uint32 *wr_data_ptr; 763 soc_mem_t local_mem; 764 int blk; 765 int phy_port; 766 int port_core_index; 767 uint32 field_buf; 768 uint32 num_words; 769 770 771 soc_mem_t tx_mem_select[] = { CPRI_BFA_TAB0_CFG_0m, /* port_0, table 0 */ 772 CPRI_BFA_TAB0_CFG_1m, /* port_1, table 0 */ 773 CPRI_BFA_TAB0_CFG_2m, /* port_2, table 0 */ 774 CPRI_BFA_TAB0_CFG_3m, /* port_3, table 0 */ 775 CPRI_BFA_TAB1_CFG_0m, /* port_0, table 1 */ 776 CPRI_BFA_TAB1_CFG_1m, /* port_1, table 1 */ 777 CPRI_BFA_TAB1_CFG_2m, /* port_2, table 1 */ 778 CPRI_BFA_TAB1_CFG_3m }; /* port_3, table 1 */ 779 soc_mem_t rx_mem_select[] = { CPRI_BFP_TAB0_CFG_0m, /* port_0, table 0 */ 780 CPRI_BFP_TAB0_CFG_1m, /* port_1, table 0 */ 781 CPRI_BFP_TAB0_CFG_2m, /* port_2, table 0 */ 782 CPRI_BFP_TAB0_CFG_3m, /* port_3, table 0 */ 783 CPRI_BFP_TAB1_CFG_0m, /* port_0, table 1 */ 784 CPRI_BFP_TAB1_CFG_1m, /* port_1, table 1 */ 785 CPRI_BFP_TAB1_CFG_2m, /* port_2, table 1 */ 786 CPRI_BFP_TAB1_CFG_3m }; /* port_3, table 1 */ 787 788 SOC_INIT_FUNC_DEFS; 789 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 790 port_core_index = ((phy_port-1)%4); 791 792 if (dir == CPRIMOD_DIR_TX) { 793 local_mem = tx_mem_select[4*table + port_core_index]; 794 } else { 795 local_mem = rx_mem_select[4*table + port_core_index]; 796 } 797 798 num_words = soc_mem_entry_words(unit, local_mem); 799 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, "cprimod"); 800 CPRIMOD_NULL_CHECK(wr_data_ptr); 801 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 802 803 field_buf = entry->axc_id; 804 soc_mem_field_set(unit, local_mem, wr_data_ptr, AXCC_IDf, &field_buf); 805 806 /* 807 * Convert the bits into count as basic frame tables store the count. 808 */ 809 field_buf = entry->rsrv_bit_cnt/2; /* NB: this is 'cnt', not 'bits' */ 810 soc_mem_field_set(unit, local_mem, wr_data_ptr, RSRV_CNTf, &field_buf); 811 812 /* 813 * Convert the bits into count. 814 */ 815 field_buf = entry->data_bit_cnt/2; /* NB: this is 'cnt', not 'bits' */ 816 soc_mem_field_set(unit, local_mem, wr_data_ptr, DATA_CNTf, &field_buf); 817 818 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 819 _SOC_IF_ERR_EXIT 820 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 821 exit: 822 sal_free(wr_data_ptr); 823 SOC_FUNC_RETURN; 824 } 825 826 827 828 int cprif_drv_basic_frame_entry_get(int unit, int port, 829 uint8 table, 830 cprimod_direction_t dir, 831 uint8 index, 832 cprif_bfa_bfp_table_entry_t *entry) 833 { 834 835 soc_mem_t local_mem; 836 int blk; 837 int phy_port; 838 int port_core_index; 839 uint32 *rd_data_ptr; 840 uint32 field_buf; 841 uint32 num_words; 842 843 soc_mem_t tx_mem_select[] = { CPRI_BFA_TAB0_CFG_0m, /* port_0, table 0 */ 844 CPRI_BFA_TAB0_CFG_1m, /* port_1, table 0 */ 845 CPRI_BFA_TAB0_CFG_2m, /* port_2, table 0 */ 846 CPRI_BFA_TAB0_CFG_3m, /* port_3, table 0 */ 847 CPRI_BFA_TAB1_CFG_0m, /* port_0, table 1 */ 848 CPRI_BFA_TAB1_CFG_1m, /* port_1, table 1 */ 849 CPRI_BFA_TAB1_CFG_2m, /* port_2, table 1 */ 850 CPRI_BFA_TAB1_CFG_3m }; /* port_3, table 1 */ 851 852 soc_mem_t rx_mem_select[] = { CPRI_BFP_TAB0_CFG_0m, /* port_0, table 0 */ 853 CPRI_BFP_TAB0_CFG_1m, /* port_1, table 0 */ 854 CPRI_BFP_TAB0_CFG_2m, /* port_2, table 0 */ 855 CPRI_BFP_TAB0_CFG_3m, /* port_3, table 0 */ 856 CPRI_BFP_TAB1_CFG_0m, /* port_0, table 1 */ 857 CPRI_BFP_TAB1_CFG_1m, /* port_1, table 1 */ 858 CPRI_BFP_TAB1_CFG_2m, /* port_2, table 1 */ 859 CPRI_BFP_TAB1_CFG_3m }; /* port_3, table 1 */ 860 SOC_INIT_FUNC_DEFS; 861 862 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 863 port_core_index = ((phy_port-1)%4); 864 865 if (dir == CPRIMOD_DIR_TX) { 866 local_mem = tx_mem_select[4*table + port_core_index]; 867 } else { 868 local_mem = rx_mem_select[4*table + port_core_index]; 869 } 870 871 num_words = soc_mem_entry_words(unit, local_mem); 872 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 873 CPRIMOD_NULL_CHECK(rd_data_ptr); 874 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 875 876 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 877 _SOC_IF_ERR_EXIT 878 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 879 soc_mem_field_get(unit, local_mem, rd_data_ptr, AXCC_IDf, &field_buf); 880 entry->axc_id = field_buf; 881 882 soc_mem_field_get(unit, local_mem, rd_data_ptr, RSRV_CNTf, &field_buf); 883 884 /* 885 * Convert the count into bits as basic frame table store the count. 886 */ 887 entry->rsrv_bit_cnt = field_buf*2; 888 889 soc_mem_field_get(unit, local_mem, rd_data_ptr, DATA_CNTf, &field_buf); 890 891 /* 892 * Convert the count into bits. 893 */ 894 entry->data_bit_cnt = field_buf*2; 895 896 exit: 897 sal_free(rd_data_ptr); 898 SOC_FUNC_RETURN; 899 900 } 901 902 903 int cprif_drv_basic_frame_usage_entry_add(int unit, int port, 904 uint8 table, 905 cprimod_direction_t dir, 906 cprimod_basic_frame_usage_entry_t new_entry, 907 cprimod_basic_frame_usage_entry_t *user_table, 908 int num_entries_in_table, 909 int *num_entries ) 910 { 911 int table_index; 912 cprif_bfa_bfp_table_entry_t table_entry; 913 uint16 current_bit_location; 914 int table_end; 915 int entry_added=0; 916 int user_table_index; 917 int last_axc_id=100; /* valix id 0-63 and 255(0xff) */ 918 current_bit_location = 0; 919 user_table_index = 0; 920 table_end = FALSE; 921 entry_added = FALSE; 922 923 for (table_index=0; (table_index<CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY) &&(!table_end) ; table_index++) { 924 SOC_IF_ERROR_RETURN 925 (cprif_drv_basic_frame_entry_get(unit, port, 926 table, dir, 927 table_index, 928 &table_entry)); 929 930 /* 931 * reserve bits need to be count first. 932 */ 933 934 if (table_entry.rsrv_bit_cnt != 0) { 935 current_bit_location += table_entry.rsrv_bit_cnt; 936 } 937 938 /* if data count is non-zero, it is an active entry.*/ 939 if (table_entry.data_bit_cnt != 0) { 940 941 if ((new_entry.start_bit < current_bit_location) && 942 (!entry_added)) { 943 if (user_table_index < num_entries_in_table) { 944 user_table[user_table_index].start_bit = new_entry.start_bit; 945 user_table[user_table_index].num_bits = new_entry.num_bits; 946 user_table[user_table_index].axc_id = new_entry.axc_id; 947 user_table_index++; 948 } 949 entry_added = TRUE; 950 } 951 952 /* 953 * Add existing entry. 954 */ 955 956 if (user_table_index < num_entries_in_table) { 957 user_table[user_table_index].start_bit = current_bit_location; 958 user_table[user_table_index].num_bits = table_entry.data_bit_cnt; 959 user_table[user_table_index].axc_id = table_entry.axc_id; 960 current_bit_location += table_entry.data_bit_cnt; 961 user_table_index++; 962 } 963 } 964 965 /* 966 * if both count are 0, then it is end of the table. 967 */ 968 if ((table_entry.data_bit_cnt == 0) && 969 (table_entry.rsrv_bit_cnt == 0)) { 970 table_end = TRUE; 971 } 972 if ((table_entry.data_bit_cnt == 0) && 973 (table_entry.axc_id == last_axc_id)) { 974 table_end = TRUE; 975 } 976 last_axc_id = table_entry.axc_id; 977 } /* for loop table_index */ 978 979 if (!entry_added) { 980 user_table[user_table_index].start_bit = new_entry.start_bit; 981 user_table[user_table_index].num_bits = new_entry.num_bits; 982 user_table[user_table_index].axc_id = new_entry.axc_id; 983 user_table_index++; 984 entry_added = TRUE; 985 } 986 *num_entries = user_table_index; 987 988 return SOC_E_NONE; 989 } 990 991 int cprif_drv_basic_frame_usage_entry_delete(int unit, int port, 992 uint8 table, 993 cprimod_direction_t dir, 994 uint8 axc_id, 995 cprimod_basic_frame_usage_entry_t *user_table, 996 int num_entries_in_table, 997 int *num_entries) 998 { 999 int table_index; 1000 cprif_bfa_bfp_table_entry_t table_entry; 1001 uint16 current_bit_location; 1002 int table_end; 1003 int user_table_index; 1004 1005 current_bit_location = 0; 1006 user_table_index = 0; 1007 table_end = FALSE; 1008 1009 for (table_index=0; (table_index < CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY) &&(!table_end) ; table_index++) { 1010 SOC_IF_ERROR_RETURN 1011 (cprif_drv_basic_frame_entry_get(unit, port, 1012 table, dir, 1013 table_index, 1014 &table_entry)); 1015 1016 if (table_entry.rsrv_bit_cnt != 0) { 1017 current_bit_location += table_entry.rsrv_bit_cnt; 1018 } 1019 1020 /* if data count is non-zero, it is an active entry.*/ 1021 if (table_entry.data_bit_cnt != 0) { 1022 if ((table_entry.axc_id != axc_id)&& 1023 (user_table_index < num_entries_in_table)) { 1024 /* 1025 * If the AxC id is not matched, then added to the user table. 1026 */ 1027 user_table[user_table_index].start_bit = current_bit_location; 1028 user_table[user_table_index].num_bits = table_entry.data_bit_cnt; 1029 user_table[user_table_index].axc_id = table_entry.axc_id; 1030 user_table_index++; 1031 } 1032 /* 1033 * Need to count bit position regardless of deleting entry or not. 1034 */ 1035 current_bit_location += table_entry.data_bit_cnt; 1036 } 1037 1038 /* if both count are 0, then it is end of the table. */ 1039 if ((table_entry.data_bit_cnt == 0) && 1040 (table_entry.rsrv_bit_cnt == 0)) { 1041 table_end = TRUE; 1042 } 1043 } /* for loop table_index */ 1044 1045 *num_entries = user_table_index; 1046 1047 return SOC_E_NONE; 1048 } 1049 1050 int cprif_drv_basic_frame_usage_entries_get(int unit, int port, 1051 uint8 table, 1052 cprimod_direction_t dir, 1053 uint8 axc_id, 1054 cprimod_basic_frame_usage_entry_t *user_table, 1055 int num_entries_in_table, 1056 int *num_entries ) 1057 { 1058 int table_index; 1059 cprif_bfa_bfp_table_entry_t table_entry; 1060 uint16 current_bit_location; 1061 int table_end; 1062 int user_table_index; 1063 1064 current_bit_location = 0; 1065 user_table_index = 0; 1066 table_end = FALSE; 1067 1068 for (table_index=0; (table_index<CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY) &&(!table_end) ; table_index++) { 1069 SOC_IF_ERROR_RETURN 1070 (cprif_drv_basic_frame_entry_get(unit, port, 1071 table, dir, 1072 table_index, 1073 &table_entry)); 1074 1075 if (table_entry.rsrv_bit_cnt != 0) { 1076 current_bit_location += table_entry.rsrv_bit_cnt; 1077 } 1078 1079 /* if data count is non-zero, it is an active entry.*/ 1080 if (table_entry.data_bit_cnt != 0) { 1081 /* If the AxC is match or looking for all entries and still have table space. */ 1082 if (((table_entry.axc_id == axc_id)|| 1083 (CPRIMOD_AXC_ID_ALL == axc_id)) && 1084 (user_table_index < num_entries_in_table)) { 1085 /* 1086 * If the AxC id is matching, then added to the user table. 1087 */ 1088 user_table[user_table_index].start_bit = current_bit_location; 1089 user_table[user_table_index].num_bits = table_entry.data_bit_cnt; 1090 user_table[user_table_index].axc_id = table_entry.axc_id; 1091 user_table_index++; 1092 } 1093 current_bit_location += table_entry.data_bit_cnt; 1094 } 1095 1096 1097 /* if both count are 0, then it is end of the table. */ 1098 if ((table_entry.data_bit_cnt == 0) && 1099 (table_entry.rsrv_bit_cnt == 0)) { 1100 table_end = TRUE; 1101 } 1102 } /* for loop table_index */ 1103 1104 *num_entries = user_table_index; 1105 1106 return SOC_E_NONE; 1107 } 1108 1109 int cprif_drv_basic_frame_usage_table_to_hw_table_set(int unit, int port, 1110 uint8 table, 1111 cprimod_direction_t dir, 1112 int basic_frm_len, 1113 cprimod_basic_frame_usage_entry_t *user_table, 1114 int *num_entries ) /* num_entries in out */ 1115 { 1116 1117 uint16 current_bit_location = 0; 1118 uint16 reserve_bit_cnt; 1119 uint16 data_bit_cnt; 1120 uint16 current_index = 0; 1121 cprif_bfa_bfp_table_entry_t table_entry; 1122 int table_index; 1123 SOC_INIT_FUNC_DEFS; 1124 1125 cprif_bfa_bfp_table_entry_t_init(&table_entry); 1126 /* 1127 * Check for Overlap first. 1128 */ 1129 1130 if (*num_entries > 1) { 1131 for (table_index=0; (table_index < ((*num_entries)-1)) ; table_index++) { 1132 if ((user_table[table_index].start_bit+user_table[table_index].num_bits) > 1133 user_table[table_index+1].start_bit) { 1134 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Overlapping AxC Entries")); 1135 } 1136 if (((user_table[table_index].start_bit+user_table[table_index].num_bits) > basic_frm_len)|| 1137 ((user_table[table_index+1].start_bit+user_table[table_index+1].num_bits) > basic_frm_len)) { 1138 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Using More Bits than available for the speed..")); 1139 } 1140 } 1141 } 1142 1143 /* 1144 * Clear the whole table first before programming anything 1145 * to get rid of stale entries. 1146 */ 1147 cprif_bfa_bfp_table_entry_t_init( &table_entry); 1148 1149 for (table_index=0; table_index < CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY; table_index++) { 1150 _SOC_IF_ERR_EXIT 1151 (cprif_drv_basic_frame_entry_set(unit, port, 1152 table, dir, 1153 table_index, 1154 &table_entry)); 1155 } 1156 1157 current_index = 0; 1158 current_bit_location = 0; 1159 1160 for (table_index=0; table_index < *num_entries; table_index++) { 1161 1162 if (current_bit_location < user_table[table_index].start_bit) { 1163 /* 1164 * if current bit position is less than start bit, need to add rsrv bits. 1165 */ 1166 reserve_bit_cnt = user_table[table_index].start_bit - current_bit_location ; 1167 current_bit_location += reserve_bit_cnt; 1168 table_entry.axc_id = user_table[table_index].axc_id; 1169 table_entry.data_bit_cnt = 0; 1170 1171 /* fill reserve bits first. */ 1172 while (reserve_bit_cnt) { 1173 if (reserve_bit_cnt > CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY) { 1174 table_entry.rsrv_bit_cnt = CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY ; 1175 } else { 1176 table_entry.rsrv_bit_cnt = reserve_bit_cnt; 1177 } 1178 1179 reserve_bit_cnt -= table_entry.rsrv_bit_cnt; 1180 /* Do not write the last entry, will combine with data below. */ 1181 if (reserve_bit_cnt != 0) { 1182 _SOC_IF_ERR_EXIT 1183 (cprif_drv_basic_frame_entry_set(unit, port, 1184 table, dir, 1185 current_index, 1186 &table_entry)); 1187 current_index++; 1188 } 1189 } 1190 } 1191 /* 1192 * Fill data bits. 1193 */ 1194 data_bit_cnt = user_table[table_index].num_bits ; 1195 current_bit_location += data_bit_cnt; 1196 table_entry.axc_id = user_table[table_index].axc_id; 1197 if (data_bit_cnt == 0) { 1198 _SOC_IF_ERR_EXIT 1199 (cprif_drv_basic_frame_entry_set(unit, port, 1200 table, dir, 1201 current_index, 1202 &table_entry)); 1203 current_index++; 1204 } else { 1205 while (data_bit_cnt) { 1206 if (data_bit_cnt > CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY) { 1207 table_entry.data_bit_cnt = CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY; 1208 } else { 1209 table_entry.data_bit_cnt = data_bit_cnt; 1210 } 1211 1212 data_bit_cnt -= table_entry.data_bit_cnt; 1213 _SOC_IF_ERR_EXIT 1214 (cprif_drv_basic_frame_entry_set(unit, port, 1215 table, dir, 1216 current_index, 1217 &table_entry)); 1218 table_entry.rsrv_bit_cnt = 0; 1219 current_index++; 1220 } 1221 } 1222 } 1223 /* Fill the remaning bits with reserved */ 1224 if(current_bit_location < basic_frm_len) { 1225 reserve_bit_cnt = basic_frm_len-current_bit_location; 1226 table_entry.data_bit_cnt = 0; 1227 while (reserve_bit_cnt) { 1228 if (reserve_bit_cnt > CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY) { 1229 table_entry.rsrv_bit_cnt = CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY ; 1230 } else { 1231 table_entry.rsrv_bit_cnt = reserve_bit_cnt; 1232 } 1233 1234 reserve_bit_cnt -= table_entry.rsrv_bit_cnt; 1235 _SOC_IF_ERR_EXIT 1236 (cprif_drv_basic_frame_entry_set(unit, port, 1237 table, dir, 1238 current_index, 1239 &table_entry)); 1240 current_index++; 1241 1242 } 1243 } 1244 *num_entries = current_index; 1245 1246 exit: 1247 SOC_FUNC_RETURN; 1248 } 1249 1250 1251 #define CPRIF_DIAG_OUT(str) LOG_CLI(str); 1252 1253 int _cprif_print_usage_table (cprimod_basic_frame_usage_entry_t* usage_table, 1254 int num_entries ) 1255 { 1256 int index; 1257 cprimod_basic_frame_usage_entry_t* entry; 1258 1259 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1260 CPRIF_DIAG_OUT((" | AxC ID | START_BIT | NUM BITS |\n")); 1261 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1262 1263 for (index = 0; index < num_entries ; index++) { 1264 entry = &usage_table[index]; 1265 CPRIF_DIAG_OUT((" | %3d | %3d | %3d |\n", entry->axc_id,entry->start_bit, entry->num_bits)); 1266 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1267 } 1268 return SOC_E_NONE; 1269 } 1270 1271 int cprif_drv_basic_frame_debug_usage(int unit, int port, uint32 axc_id, uint8 rx_table, uint8 tx_table) 1272 { 1273 cprimod_basic_frame_usage_entry_t* tx_usage_table = NULL; 1274 cprimod_basic_frame_usage_entry_t* rx_usage_table = NULL; 1275 int tx_num_entries; 1276 int rx_num_entries; 1277 1278 SOC_INIT_FUNC_DEFS; 1279 1280 1281 tx_usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc(sizeof(cprimod_basic_frame_usage_entry_t) * 1282 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, "cprif_drv"); 1283 if (tx_usage_table == NULL) { 1284 _SOC_EXIT_WITH_ERR(SOC_E_RESOURCE, ("Unable to allocate memory\n")); 1285 } 1286 1287 rx_usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc(sizeof(cprimod_basic_frame_usage_entry_t) * 1288 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, "cprif_drv"); 1289 if (rx_usage_table == NULL) { 1290 _SOC_EXIT_WITH_ERR(SOC_E_RESOURCE, ("Unable to allocate memory\n")); 1291 } 1292 1293 1294 tx_num_entries = CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY; 1295 rx_num_entries = CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY; 1296 1297 1298 _SOC_IF_ERR_EXIT 1299 (cprif_drv_basic_frame_usage_entries_get(unit, port, 1300 rx_table, 1301 CPRIMOD_DIR_RX, 1302 axc_id, 1303 rx_usage_table, 1304 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, /* table size */ 1305 &rx_num_entries)); 1306 1307 _SOC_IF_ERR_EXIT 1308 (cprif_drv_basic_frame_usage_entries_get(unit, port, 1309 tx_table, 1310 CPRIMOD_DIR_TX, 1311 axc_id, 1312 tx_usage_table, 1313 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, /* table size */ 1314 &tx_num_entries)); 1315 1316 CPRIF_DIAG_OUT(("Rx Basic Frame Table...\n")); 1317 _cprif_print_usage_table(rx_usage_table, rx_num_entries); 1318 CPRIF_DIAG_OUT(("Tx Basic Frame Table...\n")); 1319 _cprif_print_usage_table(tx_usage_table, tx_num_entries); 1320 1321 exit: 1322 if (tx_usage_table) { 1323 sal_free(tx_usage_table); 1324 } 1325 if (rx_usage_table) { 1326 sal_free(rx_usage_table); 1327 } 1328 SOC_FUNC_RETURN; 1329 } 1330 1331 1332 int cprif_drv_basic_frame_debug_raw(int unit, int port, uint32 axc_id, uint8 rx_table, uint8 tx_table) 1333 { 1334 cprif_bfa_bfp_table_entry_t entry; 1335 int table_index; 1336 uint8 table_end = 0; 1337 1338 SOC_INIT_FUNC_DEFS; 1339 1340 CPRIF_DIAG_OUT(("Rx Basic Frame HW Table...\n")); 1341 1342 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1343 CPRIF_DIAG_OUT((" | AxC ID | RSRV_BIT | DATA BITS |\n")); 1344 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1345 1346 for (table_index=0; (table_index<CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY) &&(!table_end) ; table_index++) { 1347 1348 SOC_IF_ERROR_RETURN 1349 (cprif_drv_basic_frame_entry_get(unit, port, 1350 rx_table, CPRIMOD_DIR_RX, 1351 table_index, 1352 &entry)); 1353 if ((entry.axc_id == axc_id) || 1354 (CPRIMOD_AXC_ID_ALL == axc_id)) { 1355 CPRIF_DIAG_OUT((" | %3d | %3d | %3d |\n", 1356 entry.axc_id, entry.rsrv_bit_cnt, entry.data_bit_cnt)); 1357 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1358 } 1359 /* if both count are 0, then it is end of the table. */ 1360 if ((entry.data_bit_cnt == 0) && 1361 (entry.rsrv_bit_cnt == 0)) { 1362 table_end = TRUE; 1363 } 1364 } 1365 1366 CPRIF_DIAG_OUT(("Tx Basic Frame HW Table...\n")); 1367 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1368 CPRIF_DIAG_OUT((" | AxC ID | RSRV_BIT | DATA BITS |\n")); 1369 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1370 1371 table_end = 0; 1372 for (table_index=0; (table_index<CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY) &&(!table_end) ; table_index++) { 1373 1374 SOC_IF_ERROR_RETURN 1375 (cprif_drv_basic_frame_entry_get(unit, port, 1376 tx_table, CPRIMOD_DIR_TX, 1377 table_index, 1378 &entry)); 1379 if ((entry.axc_id == axc_id) || 1380 (CPRIMOD_AXC_ID_ALL == axc_id)) { 1381 CPRIF_DIAG_OUT((" | %3d | %3d | %3d |\n", 1382 entry.axc_id, entry.rsrv_bit_cnt, entry.data_bit_cnt)); 1383 CPRIF_DIAG_OUT((" +-------------------------------------------+\n")); 1384 } 1385 /* if both count are 0, then it is end of the table. */ 1386 if ((entry.data_bit_cnt == 0) && 1387 (entry.rsrv_bit_cnt == 0)) { 1388 table_end = TRUE; 1389 } 1390 } 1391 1392 SOC_FUNC_RETURN; 1393 } 1394 1395 int cprif_drv_cpri_container_entry_set(int unit, int port, 1396 cprimod_direction_t dir, 1397 uint8 index, 1398 const cprif_cpri_container_map_entry_t *entry) 1399 { 1400 int blk; 1401 int phy_port; 1402 int port_core_index; 1403 soc_mem_t local_mem; 1404 1405 soc_mem_t rx_mem_select[] = { CPRI_CPRSR_MAP_TAB_CFG_0m, /* slice#0 */ 1406 CPRI_CPRSR_MAP_TAB_CFG_1m, /* slice#1 */ 1407 CPRI_CPRSR_MAP_TAB_CFG_2m, /* slice#2 */ 1408 CPRI_CPRSR_MAP_TAB_CFG_3m }; /* slice#3 */ 1409 1410 soc_mem_t tx_mem_select[] = { CPRI_CA_MAP_TAB_CFG_0m, /* slice#0 */ 1411 CPRI_CA_MAP_TAB_CFG_1m, /* slice#1 */ 1412 CPRI_CA_MAP_TAB_CFG_2m, /* slice#2 */ 1413 CPRI_CA_MAP_TAB_CFG_3m }; /* slice#3 */ 1414 uint32 *wr_data_ptr; 1415 uint32 field_buf; 1416 uint32 num_words; 1417 SOC_INIT_FUNC_DEFS; 1418 1419 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1420 port_core_index = ((phy_port-1)%4); 1421 1422 if (dir == CPRIMOD_DIR_TX) 1423 local_mem = tx_mem_select[port_core_index]; 1424 else 1425 local_mem = rx_mem_select[port_core_index]; 1426 1427 num_words = soc_mem_entry_words(unit, local_mem); 1428 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 1429 CPRIMOD_NULL_CHECK(wr_data_ptr); 1430 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 1431 1432 field_buf = entry->map_method; 1433 soc_mem_field_set(unit, local_mem, wr_data_ptr, MAP_METHODf, &field_buf); 1434 1435 field_buf = entry->axc_id; 1436 soc_mem_field_set(unit, local_mem, wr_data_ptr, AXC_IDf, &field_buf); 1437 1438 field_buf = entry->stuffing_at_end; 1439 if (local_mem == tx_mem_select[port_core_index]) { 1440 soc_mem_field_set(unit, local_mem, wr_data_ptr, STUFFING_AT_ENDf, &field_buf); 1441 } else { 1442 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_0f, &field_buf); 1443 } 1444 1445 if (entry->map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_1) { 1446 field_buf = entry->stuff_cnt/2; 1447 soc_mem_field_set(unit, local_mem, wr_data_ptr, STUFF_CNTf, &field_buf); 1448 } else if (entry->map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_3) { 1449 /* stuffing conut for method #3 has quotient and remainder. */ 1450 field_buf = entry->stuff_cnt; 1451 soc_mem_field_set(unit, local_mem, wr_data_ptr, STUFF_CNTf, &field_buf); 1452 } 1453 1454 1455 field_buf = entry->cblk_cnt/2; 1456 soc_mem_field_set(unit, local_mem, wr_data_ptr, CBLK_CNTf, &field_buf); 1457 1458 field_buf = entry->naxc_cnt/2; 1459 soc_mem_field_set(unit, local_mem, wr_data_ptr, NAXC_CNTf, &field_buf); 1460 1461 field_buf = entry->Nv; 1462 soc_mem_field_set(unit, local_mem, wr_data_ptr, NVf, &field_buf); 1463 1464 field_buf = entry->Na; 1465 soc_mem_field_set(unit, local_mem, wr_data_ptr, NAf, &field_buf); 1466 1467 field_buf = entry->rfrm_sync; 1468 soc_mem_field_set(unit, local_mem, wr_data_ptr, RFRM_SYNCf, &field_buf); 1469 1470 field_buf = entry->hfrm_sync; 1471 soc_mem_field_set(unit, local_mem, wr_data_ptr, HFRM_SYNCf, &field_buf); 1472 1473 field_buf = entry->bfn_offset; 1474 soc_mem_field_set(unit, local_mem, wr_data_ptr, BFN_OFFSETf, &field_buf); 1475 1476 field_buf = entry->hfn_offset; 1477 soc_mem_field_set(unit, local_mem, wr_data_ptr, HFN_OFFSETf, &field_buf); 1478 1479 field_buf = entry->bfrm_offset; 1480 soc_mem_field_set(unit, local_mem, wr_data_ptr, BFRM_OFFSETf, &field_buf); 1481 1482 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 1483 _SOC_IF_ERR_EXIT 1484 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 1485 1486 exit: 1487 sal_free(wr_data_ptr); 1488 SOC_FUNC_RETURN; 1489 1490 } 1491 1492 int cprif_drv_cpri_container_entry_get(int unit, int port, 1493 cprimod_direction_t dir, 1494 uint8 index, 1495 cprif_cpri_container_map_entry_t *entry) 1496 { 1497 int blk; 1498 int phy_port; 1499 int port_core_index; 1500 soc_mem_t local_mem; 1501 1502 soc_mem_t rx_mem_select[] = { CPRI_CPRSR_MAP_TAB_CFG_0m, /* slice#0 */ 1503 CPRI_CPRSR_MAP_TAB_CFG_1m, /* slice#1 */ 1504 CPRI_CPRSR_MAP_TAB_CFG_2m, /* slice#2 */ 1505 CPRI_CPRSR_MAP_TAB_CFG_3m }; /* slice#3 */ 1506 1507 soc_mem_t tx_mem_select[] = { CPRI_CA_MAP_TAB_CFG_0m, /* slice#0 */ 1508 CPRI_CA_MAP_TAB_CFG_1m, /* slice#1 */ 1509 CPRI_CA_MAP_TAB_CFG_2m, /* slice#2 */ 1510 CPRI_CA_MAP_TAB_CFG_3m }; /* slice#3 */ 1511 uint32 *rd_data_ptr; 1512 uint32 field_buf; 1513 uint32 num_words; 1514 SOC_INIT_FUNC_DEFS; 1515 1516 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1517 port_core_index = ((phy_port-1)%4); 1518 1519 if (dir == CPRIMOD_DIR_TX) 1520 local_mem = tx_mem_select[port_core_index]; 1521 else 1522 local_mem = rx_mem_select[port_core_index]; 1523 1524 num_words = soc_mem_entry_words(unit, local_mem); 1525 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 1526 CPRIMOD_NULL_CHECK(rd_data_ptr); 1527 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 1528 1529 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 1530 _SOC_IF_ERR_EXIT 1531 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 1532 1533 soc_mem_field_get(unit, local_mem, rd_data_ptr, MAP_METHODf, &field_buf); 1534 entry->map_method = field_buf; 1535 1536 soc_mem_field_get(unit, local_mem, rd_data_ptr, AXC_IDf, &field_buf); 1537 entry->axc_id = field_buf; 1538 1539 if (local_mem == tx_mem_select[port_core_index]) { 1540 soc_mem_field_get(unit, local_mem, rd_data_ptr, STUFFING_AT_ENDf, &field_buf); 1541 } else { 1542 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_0f, &field_buf); 1543 } 1544 entry->stuffing_at_end = field_buf; 1545 1546 soc_mem_field_get(unit, local_mem, rd_data_ptr, STUFF_CNTf, &field_buf); 1547 if (entry->map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_3) { 1548 entry->stuff_cnt = field_buf; 1549 } else { 1550 entry->stuff_cnt = field_buf * 2; 1551 } 1552 1553 soc_mem_field_get(unit, local_mem, rd_data_ptr,CBLK_CNTf , &field_buf); 1554 entry->cblk_cnt = field_buf * 2; 1555 1556 soc_mem_field_get(unit, local_mem, rd_data_ptr, NAXC_CNTf , &field_buf); 1557 entry->naxc_cnt = field_buf * 2; 1558 1559 soc_mem_field_get(unit, local_mem, rd_data_ptr, NVf, &field_buf); 1560 entry->Nv = field_buf; 1561 1562 soc_mem_field_get(unit, local_mem, rd_data_ptr, NAf, &field_buf); 1563 entry->Na= field_buf; 1564 1565 soc_mem_field_get(unit, local_mem, rd_data_ptr, RFRM_SYNCf, &field_buf); 1566 entry->rfrm_sync = field_buf; 1567 1568 soc_mem_field_get(unit, local_mem, rd_data_ptr, HFRM_SYNCf, &field_buf); 1569 entry->hfrm_sync = field_buf; 1570 1571 soc_mem_field_get(unit, local_mem, rd_data_ptr, BFN_OFFSETf, &field_buf); 1572 entry->bfn_offset = field_buf; 1573 1574 soc_mem_field_get(unit, local_mem, rd_data_ptr, HFN_OFFSETf, &field_buf); 1575 entry->hfn_offset = field_buf; 1576 1577 soc_mem_field_get(unit, local_mem, rd_data_ptr, BFRM_OFFSETf, &field_buf); 1578 entry->bfrm_offset = field_buf; 1579 1580 exit: 1581 sal_free(rd_data_ptr); 1582 SOC_FUNC_RETURN; 1583 1584 } 1585 1586 int cprif_drv_rsvd4_container_entry_set(int unit, int port, 1587 cprimod_direction_t dir, 1588 uint8 index, 1589 const cprif_rsvd4_container_map_entry_t *entry) 1590 { 1591 int blk; 1592 int phy_port; 1593 int port_core_index; 1594 soc_mem_t local_mem; 1595 soc_mem_t rx_mem_select[] = { CPRI_CPRSR_MAP_TAB_CFG_0m, /* slice#0 */ 1596 CPRI_CPRSR_MAP_TAB_CFG_1m, /* slice#1 */ 1597 CPRI_CPRSR_MAP_TAB_CFG_2m, /* slice#2 */ 1598 CPRI_CPRSR_MAP_TAB_CFG_3m }; /* slice#3 */ 1599 1600 soc_mem_t tx_mem_select[] = { CPRI_CA_MAP_TAB_CFG_0m, /* slice#0 */ 1601 CPRI_CA_MAP_TAB_CFG_1m, /* slice#1 */ 1602 CPRI_CA_MAP_TAB_CFG_2m, /* slice#2 */ 1603 CPRI_CA_MAP_TAB_CFG_3m }; /* slice#3 */ 1604 uint32 *wr_data_ptr; 1605 uint32 field_buf; 1606 uint32 num_words; 1607 SOC_INIT_FUNC_DEFS; 1608 1609 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1610 port_core_index = ((phy_port-1)%4); 1611 1612 if (dir == CPRIMOD_DIR_TX) 1613 local_mem = tx_mem_select[port_core_index]; 1614 else 1615 local_mem = rx_mem_select[port_core_index]; 1616 1617 num_words = soc_mem_entry_words(unit, local_mem); 1618 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 1619 CPRIMOD_NULL_CHECK(wr_data_ptr); 1620 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 1621 1622 1623 field_buf = entry->map_method; 1624 soc_mem_field_set(unit, local_mem, wr_data_ptr, MAP_METHODf, &field_buf); 1625 1626 field_buf = entry->axc_id; 1627 soc_mem_field_set(unit, local_mem, wr_data_ptr, AXC_IDf, &field_buf); 1628 1629 if (dir == CPRIMOD_DIR_TX) { 1630 field_buf = entry->stuffing_at_end; 1631 soc_mem_field_set(unit, local_mem, wr_data_ptr, STUFFING_AT_ENDf, &field_buf); 1632 1633 field_buf = entry->stuff_cnt/2; 1634 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_0f, &field_buf); 1635 1636 field_buf = entry->cblk_cnt/2; 1637 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_1f, &field_buf); 1638 1639 field_buf = entry->rfrm_offset & 0xFFFFF; /* lower 20 bits only */ 1640 soc_mem_field_set(unit, local_mem, wr_data_ptr, RFRM_OFFSET_LOWf, &field_buf); 1641 1642 field_buf = (entry->rfrm_offset >> 20) & 0xFF; /* middle 8 bits only */ 1643 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_8f, &field_buf); 1644 1645 field_buf = (entry->rfrm_offset >> 28) & 0xF; /* upper 4 bits only */ 1646 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_11f, &field_buf); 1647 1648 field_buf = entry->use_ts_dbm; 1649 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_2f, &field_buf); 1650 1651 field_buf = entry->ts_dbm_prof_num; 1652 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_3f, &field_buf); 1653 1654 field_buf = entry->num_active_slots; 1655 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_4f, &field_buf); 1656 1657 field_buf = entry->msg_addr; 1658 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_5f, &field_buf); 1659 1660 field_buf = entry->msg_type; 1661 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_7f, &field_buf); 1662 1663 field_buf = entry->msg_ts_cnt; 1664 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_9f, &field_buf); 1665 1666 field_buf = entry->msg_ts_offset; 1667 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_10f, &field_buf); 1668 1669 field_buf = entry->msg_ts_mode; 1670 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_17_6f, &field_buf); 1671 1672 } else { 1673 field_buf = entry->stuffing_at_end; 1674 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_0f, &field_buf); 1675 1676 field_buf = entry->stuff_cnt/2; 1677 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_1f, &field_buf); 1678 1679 field_buf = entry->cblk_cnt/2; 1680 soc_mem_field_set(unit, local_mem, wr_data_ptr, CBLK_CNTf, &field_buf); 1681 1682 field_buf = entry->rfrm_offset & 0xFFFFF; /* lower 20 bits only */ 1683 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_2f, &field_buf); 1684 1685 field_buf = (entry->rfrm_offset >> 20) & 0xFFF; /* upper 12 bits only */ 1686 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_3f, &field_buf); 1687 1688 field_buf = entry->msg_ts_mode; 1689 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_4f, &field_buf); 1690 1691 field_buf = entry->msg_ts_sync; 1692 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_5f, &field_buf); 1693 1694 field_buf = entry->msg_ts_cnt; 1695 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_332_6f, &field_buf); 1696 1697 } 1698 1699 1700 field_buf = entry->hfrm_sync; 1701 soc_mem_field_set(unit, local_mem, wr_data_ptr, HFRM_SYNCf, &field_buf); 1702 1703 field_buf = entry->rfrm_sync; 1704 soc_mem_field_set(unit, local_mem, wr_data_ptr, RFRM_SYNCf, &field_buf); 1705 1706 1707 field_buf = entry->bfn_offset; 1708 soc_mem_field_set(unit, local_mem, wr_data_ptr, BFN_OFFSETf, &field_buf); 1709 1710 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 1711 _SOC_IF_ERR_EXIT 1712 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 1713 exit: 1714 sal_free(wr_data_ptr); 1715 SOC_FUNC_RETURN; 1716 1717 } 1718 1719 int cprif_drv_rsvd4_container_entry_get(int unit, int port, 1720 cprimod_direction_t dir, 1721 uint8 index, 1722 cprif_rsvd4_container_map_entry_t *entry) 1723 { 1724 int blk; 1725 int phy_port; 1726 int port_core_index; 1727 soc_mem_t local_mem; 1728 soc_mem_t rx_mem_select[] = { CPRI_CPRSR_MAP_TAB_CFG_0m, /* slice#0 */ 1729 CPRI_CPRSR_MAP_TAB_CFG_1m, /* slice#1 */ 1730 CPRI_CPRSR_MAP_TAB_CFG_2m, /* slice#2 */ 1731 CPRI_CPRSR_MAP_TAB_CFG_3m }; /* slice#3 */ 1732 1733 soc_mem_t tx_mem_select[] = { CPRI_CA_MAP_TAB_CFG_0m, /* slice#0 */ 1734 CPRI_CA_MAP_TAB_CFG_1m, /* slice#1 */ 1735 CPRI_CA_MAP_TAB_CFG_2m, /* slice#2 */ 1736 CPRI_CA_MAP_TAB_CFG_3m }; /* slice#3 */ 1737 uint32 *rd_data_ptr; 1738 uint32 field_buf; 1739 uint32 num_words; 1740 SOC_INIT_FUNC_DEFS; 1741 1742 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1743 port_core_index = ((phy_port-1)%4); 1744 1745 if (dir == CPRIMOD_DIR_TX) 1746 local_mem = tx_mem_select[port_core_index]; 1747 else 1748 local_mem = rx_mem_select[port_core_index]; 1749 1750 num_words = soc_mem_entry_words(unit, local_mem); 1751 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 1752 CPRIMOD_NULL_CHECK(rd_data_ptr); 1753 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 1754 1755 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 1756 _SOC_IF_ERR_EXIT 1757 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 1758 1759 soc_mem_field_get(unit, local_mem, rd_data_ptr, MAP_METHODf, &field_buf); 1760 entry->map_method = field_buf; 1761 1762 soc_mem_field_get(unit, local_mem, rd_data_ptr, AXC_IDf, &field_buf); 1763 entry->axc_id = field_buf; 1764 1765 if (dir == CPRIMOD_DIR_TX) { 1766 soc_mem_field_get(unit, local_mem, rd_data_ptr, STUFFING_AT_ENDf, &field_buf); 1767 entry->stuffing_at_end = field_buf; 1768 1769 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_0f, &field_buf); 1770 entry->stuff_cnt = field_buf * 2; 1771 1772 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_1f, &field_buf); 1773 entry->cblk_cnt = field_buf * 2; 1774 1775 soc_mem_field_get(unit, local_mem, rd_data_ptr, RFRM_OFFSET_LOWf, &field_buf); 1776 entry->rfrm_offset = field_buf & 0xFFFFF; 1777 1778 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_8f, &field_buf); 1779 entry->rfrm_offset |= ((field_buf & 0xFF) << 20); 1780 1781 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_11f, &field_buf); 1782 entry->rfrm_offset |= ((field_buf & 0xF) << 28); 1783 1784 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_2f, &field_buf); 1785 entry->use_ts_dbm = field_buf; 1786 1787 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_3f, &field_buf); 1788 entry->ts_dbm_prof_num = field_buf; 1789 1790 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_4f, &field_buf); 1791 entry->num_active_slots = field_buf; 1792 1793 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_5f, &field_buf); 1794 entry->msg_addr = field_buf; 1795 1796 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_7f, &field_buf); 1797 entry->msg_type = field_buf; 1798 1799 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_10f, &field_buf); 1800 entry->msg_ts_offset = field_buf; 1801 1802 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_9f, &field_buf); 1803 entry->msg_ts_cnt = field_buf; 1804 1805 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_17_6f, &field_buf); 1806 entry->msg_ts_mode = field_buf; 1807 1808 } else { 1809 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_0f, &field_buf); 1810 entry->stuffing_at_end = field_buf; 1811 1812 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_1f, &field_buf); 1813 entry->stuff_cnt = field_buf * 2; 1814 1815 soc_mem_field_get(unit, local_mem, rd_data_ptr, CBLK_CNTf, &field_buf); 1816 entry->cblk_cnt = field_buf * 2; 1817 1818 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_2f, &field_buf); 1819 entry->rfrm_offset = field_buf & 0xFFFFF; 1820 1821 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_3f, &field_buf); 1822 entry->rfrm_offset |= ((field_buf & 0xFFF) << 20); 1823 1824 1825 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_5f, &field_buf); 1826 entry->msg_ts_sync = field_buf; 1827 1828 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_6f, &field_buf); 1829 entry->msg_ts_cnt = field_buf; 1830 1831 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_332_4f, &field_buf); 1832 entry->msg_ts_mode = field_buf; 1833 1834 } 1835 1836 1837 soc_mem_field_get(unit, local_mem, rd_data_ptr, HFRM_SYNCf, &field_buf); 1838 entry->hfrm_sync = field_buf; 1839 1840 soc_mem_field_get(unit, local_mem, rd_data_ptr, RFRM_SYNCf, &field_buf); 1841 entry->rfrm_sync = field_buf; 1842 1843 soc_mem_field_get(unit, local_mem, rd_data_ptr, BFN_OFFSETf, &field_buf); 1844 entry->bfn_offset = field_buf; 1845 1846 exit: 1847 sal_free(rd_data_ptr); 1848 SOC_FUNC_RETURN; 1849 1850 } 1851 1852 int cprif_container_map_print_cpri_entry (cprif_cpri_container_map_entry_t* entry) 1853 { 1854 1855 CPRIF_DIAG_OUT((" 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x \n", 1856 entry->map_method, 1857 entry->axc_id, 1858 entry->stuffing_at_end, 1859 entry->stuff_cnt, 1860 entry->cblk_cnt, 1861 entry->naxc_cnt, 1862 entry->Nv, 1863 entry->Na, 1864 entry->rfrm_sync, 1865 entry->hfrm_sync, 1866 entry->bfn_offset, 1867 entry->hfn_offset, 1868 entry->bfrm_offset 1869 )); 1870 return SOC_E_NONE; 1871 } 1872 1873 int cprif_container_map_print_rsvd4_entry (cprif_rsvd4_container_map_entry_t* entry) 1874 { 1875 1876 CPRIF_DIAG_OUT((" 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%01x x0x%01x 0x%01x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x 0x%03x \n", 1877 entry->map_method, 1878 entry->axc_id, 1879 entry->stuffing_at_end, 1880 entry->stuff_cnt, 1881 entry->cblk_cnt, 1882 entry->rfrm_sync, 1883 entry->hfrm_sync, 1884 entry->msg_ts_sync, 1885 entry->bfn_offset, 1886 entry->rfrm_offset, 1887 entry->bfn_offset, 1888 entry->msg_ts_mode, 1889 entry->msg_ts_cnt, 1890 entry->use_ts_dbm, 1891 entry->ts_dbm_prof_num, 1892 entry->num_active_slots, 1893 entry->msg_addr, 1894 entry->msg_type, 1895 entry->msg_ts_offset 1896 )); 1897 return SOC_E_NONE; 1898 } 1899 1900 int cprif_container_map_debug(int unit, int port, uint8 axc_id) 1901 { 1902 cprif_cpri_container_map_entry_t cpri_entry; 1903 cprif_rsvd4_container_map_entry_t rsvd4_entry; 1904 1905 SOC_INIT_FUNC_DEFS; 1906 1907 _SOC_IF_ERR_EXIT(cprif_drv_cpri_container_entry_get(unit, port, 1908 CPRIMOD_DIR_RX, 1909 axc_id, 1910 &cpri_entry)); 1911 1912 if (cpri_entry.map_method == CPRIF_CONTAINER_MAP_RSVD4) { 1913 1914 CPRIF_DIAG_OUT((" +------------------------------------------------------------------------------------------------------------------------------------+\n")); 1915 CPRIF_DIAG_OUT((" | Map M | AxC | S END | S CNT | CBLK CNT | SYNC rhm | BFN | RFRM | TS_MODE | TS CNT | DBM EN | Prof | ASlot | Addr | Type | TS Offset|\n")); 1916 CPRIF_DIAG_OUT((" +------------------------------------------------------------------------------------------------------------------------------------+\n")); 1917 1918 _SOC_IF_ERR_EXIT 1919 (cprif_drv_rsvd4_container_entry_get(unit, port, 1920 CPRIMOD_DIR_RX, 1921 axc_id, 1922 &rsvd4_entry)); 1923 1924 _SOC_IF_ERR_EXIT 1925 (cprif_drv_rsvd4_container_entry_get(unit, port, 1926 CPRIMOD_DIR_TX, 1927 axc_id, 1928 &rsvd4_entry)); 1929 1930 } else { 1931 1932 CPRIF_DIAG_OUT((" +----------------------------------------------------------------------------------------+\n")); 1933 CPRIF_DIAG_OUT((" | Map M | AxC | S END | S CNT | CBLK CNT | Naxc | Nv | Na | SYNC rh | BFN | HFN | BFRM |\n")); 1934 CPRIF_DIAG_OUT((" +---------------------------------------------------------------------------------------+\n")); 1935 1936 1937 _SOC_IF_ERR_EXIT 1938 (cprif_drv_cpri_container_entry_get(unit, port, 1939 CPRIMOD_DIR_TX, 1940 axc_id, 1941 &cpri_entry)); 1942 1943 1944 } 1945 1946 exit: 1947 SOC_FUNC_RETURN; 1948 } 1949 1950 1951 /* 1952 * 1953 * IQ Packing/Unpacking 1954 */ 1955 int cprif_drv_iq_buffer_config_set(int unit, int port, 1956 cprimod_direction_t dir, 1957 uint8 index, 1958 cprif_iq_buffer_config_t* entry) 1959 { 1960 uint32 *wr_data_ptr; 1961 soc_mem_t local_mem; 1962 int blk; 1963 int phy_port; 1964 int port_core_index; 1965 uint32 field_buf; 1966 uint32 num_words; 1967 1968 soc_mem_t rx_mem_select[] = { CPRI_CPRSR_IQ_PK_BUFF_CFG_0m, /* slice#0 */ 1969 CPRI_CPRSR_IQ_PK_BUFF_CFG_1m, /* slice#1 */ 1970 CPRI_CPRSR_IQ_PK_BUFF_CFG_2m, /* slice#2 */ 1971 CPRI_CPRSR_IQ_PK_BUFF_CFG_3m }; /* slice#3 */ 1972 soc_mem_t tx_mem_select[] = { CPRI_CA_PAY_TAB_CFG_0m, /* slice#0 */ 1973 CPRI_CA_PAY_TAB_CFG_1m, /* slice#1 */ 1974 CPRI_CA_PAY_TAB_CFG_2m, /* slice#2 */ 1975 CPRI_CA_PAY_TAB_CFG_3m }; /* slice#3 */ 1976 SOC_INIT_FUNC_DEFS; 1977 1978 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1979 port_core_index = ((phy_port-1)%4); 1980 1981 if (dir == CPRIMOD_DIR_TX) { 1982 local_mem = tx_mem_select[port_core_index]; 1983 } else { 1984 local_mem = rx_mem_select[port_core_index]; 1985 } 1986 1987 num_words = soc_mem_entry_words(unit, local_mem); 1988 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 1989 CPRIMOD_NULL_CHECK(wr_data_ptr); 1990 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 1991 1992 /* 1993 * Convert the bits into number of sample pair. 1994 */ 1995 field_buf = entry->payload_size; 1996 soc_mem_field_set(unit, local_mem, wr_data_ptr, PLD_SIZEf, &field_buf); 1997 1998 field_buf = entry->last_packet_num; 1999 soc_mem_field_set(unit, local_mem, wr_data_ptr, NTH_PLD_IDf, &field_buf); 2000 2001 /* 2002 * Convert the bits into number of sample pair. 2003 */ 2004 field_buf = entry->last_payload_size; 2005 soc_mem_field_set(unit, local_mem, wr_data_ptr, NTH_PLD_SIZEf, &field_buf); 2006 2007 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2008 _SOC_IF_ERR_EXIT 2009 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 2010 2011 exit: 2012 sal_free(wr_data_ptr); 2013 SOC_FUNC_RETURN; 2014 } 2015 2016 int cprif_drv_iq_buffer_config_get(int unit, int port, 2017 cprimod_direction_t dir, 2018 uint8 index, 2019 cprif_iq_buffer_config_t* entry) 2020 { 2021 uint32 *rd_data_ptr; 2022 soc_mem_t local_mem; 2023 int blk; 2024 int phy_port; 2025 int port_core_index; 2026 uint32 field_buf; 2027 uint32 num_words; 2028 2029 soc_mem_t rx_mem_select[] = { CPRI_CPRSR_IQ_PK_BUFF_CFG_0m, /* slice#0 */ 2030 CPRI_CPRSR_IQ_PK_BUFF_CFG_1m, /* slice#1 */ 2031 CPRI_CPRSR_IQ_PK_BUFF_CFG_2m, /* slice#2 */ 2032 CPRI_CPRSR_IQ_PK_BUFF_CFG_3m }; /* slice#3 */ 2033 soc_mem_t tx_mem_select[] = { CPRI_CA_PAY_TAB_CFG_0m, /* slice#0 */ 2034 CPRI_CA_PAY_TAB_CFG_1m, /* slice#1 */ 2035 CPRI_CA_PAY_TAB_CFG_2m, /* slice#2 */ 2036 CPRI_CA_PAY_TAB_CFG_3m }; /* slice#3 */ 2037 SOC_INIT_FUNC_DEFS; 2038 2039 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 2040 port_core_index = ((phy_port-1)%4); 2041 2042 if (dir == CPRIMOD_DIR_TX) { 2043 local_mem = tx_mem_select[port_core_index]; 2044 } else { 2045 local_mem = rx_mem_select[port_core_index]; 2046 } 2047 2048 num_words = soc_mem_entry_words(unit, local_mem); 2049 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 2050 CPRIMOD_NULL_CHECK(rd_data_ptr); 2051 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 2052 2053 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2054 _SOC_IF_ERR_EXIT 2055 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 2056 2057 soc_mem_field_get(unit, local_mem, rd_data_ptr, PLD_SIZEf, &field_buf); 2058 entry->payload_size = field_buf; 2059 2060 soc_mem_field_get(unit, local_mem, rd_data_ptr, NTH_PLD_IDf, &field_buf); 2061 entry->last_packet_num = field_buf; 2062 2063 soc_mem_field_get(unit, local_mem, rd_data_ptr, NTH_PLD_SIZEf, &field_buf); 2064 entry->last_payload_size = field_buf; 2065 2066 exit: 2067 sal_free(rd_data_ptr); 2068 SOC_FUNC_RETURN; 2069 } 2070 2071 2072 int cprif_iq_buffer_debug(int unit, int port, uint8 axc_id) 2073 { 2074 cprif_iq_buffer_config_t entry; 2075 SOC_INIT_FUNC_DEFS; 2076 2077 cprif_iq_buffer_config_t_init(&entry); 2078 2079 CPRIF_DIAG_OUT((" +---------------------------------------------------------------------+\n")); 2080 CPRIF_DIAG_OUT((" | AxC | Payload Size | Last_Pkt_Num | Last Payload Size |\n")); 2081 CPRIF_DIAG_OUT((" +---------------------------------------------------------------------+\n")); 2082 2083 _SOC_IF_ERR_EXIT(cprif_drv_iq_buffer_config_get(unit, port, 2084 CPRIMOD_DIR_RX, 2085 axc_id, 2086 &entry)); 2087 2088 CPRIF_DIAG_OUT((" Rx 0x%03x 0x%03x 0x%03x 0x%03x\n", axc_id, entry.payload_size,entry.last_packet_num, entry.last_payload_size)); 2089 2090 _SOC_IF_ERR_EXIT(cprif_drv_iq_buffer_config_get(unit, port, 2091 CPRIMOD_DIR_TX, 2092 axc_id, 2093 &entry)); 2094 2095 CPRIF_DIAG_OUT((" Tx 0x%03x 0x%03x 0x%03x 0x%03x\n", axc_id, entry.payload_size,entry.last_packet_num, entry.last_payload_size)); 2096 exit: 2097 SOC_FUNC_RETURN; 2098 } 2099 2100 2101 /* this is for cprif_drv_decap_data_entry_set as well */ 2102 int cprif_drv_encap_data_entry_set(int unit, int port, 2103 cprimod_direction_t dir, 2104 uint32 queue_num, 2105 const cprif_encap_decap_data_entry_t *entry) 2106 { 2107 int blk; 2108 int phy_port; 2109 int port_core_index; 2110 soc_mem_t local_mem; 2111 soc_mem_t rx_mem_select[] = { CPRI_ENCAP_DATA_0m, 2112 CPRI_ENCAP_DATA_1m, 2113 CPRI_ENCAP_DATA_2m, 2114 CPRI_ENCAP_DATA_3m }; 2115 2116 soc_mem_t tx_mem_select[] = { CPRI_DECAP_DATA_0m, 2117 CPRI_DECAP_DATA_1m, 2118 CPRI_DECAP_DATA_2m, 2119 CPRI_DECAP_DATA_3m }; 2120 2121 2122 uint32 *wr_data_ptr; 2123 uint32 field_buf; 2124 uint32 num_words; 2125 SOC_INIT_FUNC_DEFS; 2126 2127 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 2128 port_core_index = ((phy_port-1)%4); 2129 2130 if (dir == CPRIMOD_DIR_TX) { 2131 local_mem = tx_mem_select[port_core_index]; 2132 } else { 2133 local_mem = rx_mem_select[port_core_index]; 2134 } 2135 2136 num_words = soc_mem_entry_words(unit, local_mem); 2137 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 2138 CPRIMOD_NULL_CHECK(wr_data_ptr); 2139 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 2140 2141 /* 2142 * Read existing configuration since not all the fields will be set 2143 * here. 2144 */ 2145 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2146 _SOC_IF_ERR_EXIT 2147 (soc_mem_read(unit, local_mem, blk, queue_num, wr_data_ptr)); 2148 2149 field_buf = entry->sample_size; 2150 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SAMPLE_SIZEf, &field_buf); 2151 2152 if (dir == CPRIMOD_DIR_RX) { 2153 2154 field_buf = entry->valid; 2155 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_VALIDf, &field_buf); 2156 2157 field_buf = entry->mux_enable; 2158 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_DEMUX_ENf, &field_buf); 2159 2160 field_buf = entry->queue_size; 2161 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SIZEf, &field_buf); 2162 2163 field_buf = entry->work_queue_select; 2164 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_WQ_SELf, &field_buf); 2165 2166 } else { 2167 field_buf = entry->mux_enable; 2168 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_MUX_ENf, &field_buf); 2169 2170 field_buf = entry->queue_size; 2171 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_BUF_SIZEf, &field_buf); 2172 2173 field_buf = entry->tx_cycle_size; 2174 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_CYC_SIZEf, &field_buf); 2175 2176 2177 } 2178 2179 field_buf = entry->out_sample_size; 2180 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_OUT_SAMPLE_SIZEf, &field_buf); 2181 2182 2183 field_buf = entry->queue_offset; 2184 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_OFFSETf, &field_buf); 2185 2186 2187 field_buf = entry->sign_ext_enable; 2188 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SIGN_EXDf, &field_buf); 2189 2190 field_buf = entry->sign_ext_type; 2191 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SIGN_EXD_TYPEf, &field_buf); 2192 2193 field_buf = entry->bit_reversal; 2194 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_BIT_REVERSALf, &field_buf); 2195 2196 2197 _SOC_IF_ERR_EXIT 2198 (soc_mem_write(unit, local_mem, blk, queue_num, wr_data_ptr)); 2199 2200 exit: 2201 sal_free(wr_data_ptr); 2202 SOC_FUNC_RETURN; 2203 2204 } 2205 2206 int cprif_drv_encap_data_entry_get(int unit, int port, 2207 cprimod_direction_t dir, 2208 uint32 queue_num, 2209 cprif_encap_decap_data_entry_t *entry) 2210 { 2211 int blk; 2212 int phy_port; 2213 int port_core_index; 2214 soc_mem_t local_mem; 2215 soc_mem_t rx_mem_select[] = { CPRI_ENCAP_DATA_0m, 2216 CPRI_ENCAP_DATA_1m, 2217 CPRI_ENCAP_DATA_2m, 2218 CPRI_ENCAP_DATA_3m }; 2219 2220 soc_mem_t tx_mem_select[] = { CPRI_DECAP_DATA_0m, 2221 CPRI_DECAP_DATA_1m, 2222 CPRI_DECAP_DATA_2m, 2223 CPRI_DECAP_DATA_3m }; 2224 2225 2226 uint32 *rd_data_ptr; 2227 uint32 field_buf; 2228 uint32 num_words; 2229 SOC_INIT_FUNC_DEFS; 2230 2231 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 2232 port_core_index = ((phy_port-1)%4); 2233 2234 if (dir == CPRIMOD_DIR_TX) { 2235 local_mem = tx_mem_select[port_core_index]; 2236 } else { 2237 local_mem = rx_mem_select[port_core_index]; 2238 } 2239 2240 num_words = soc_mem_entry_words(unit, local_mem); 2241 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 2242 CPRIMOD_NULL_CHECK(rd_data_ptr); 2243 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 2244 2245 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2246 _SOC_IF_ERR_EXIT 2247 (soc_mem_read(unit, local_mem, blk, queue_num, rd_data_ptr)); 2248 2249 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_SAMPLE_SIZEf, &field_buf); 2250 entry->sample_size = field_buf; 2251 2252 if (dir == CPRIMOD_DIR_RX) { 2253 2254 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_VALIDf, &field_buf); 2255 entry->valid = field_buf; 2256 2257 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_DEMUX_ENf, &field_buf); 2258 entry->mux_enable = field_buf; 2259 2260 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_SIZEf, &field_buf); 2261 entry->queue_size = field_buf; 2262 2263 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_WQ_SELf, &field_buf); 2264 entry->work_queue_select = field_buf; 2265 } else { 2266 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_MUX_ENf, &field_buf); 2267 entry->mux_enable = field_buf; 2268 2269 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_BUF_SIZEf, &field_buf); 2270 entry->queue_size = field_buf; 2271 2272 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_CYC_SIZEf, &field_buf); 2273 entry->tx_cycle_size = field_buf; 2274 2275 } 2276 2277 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_OUT_SAMPLE_SIZEf, &field_buf); 2278 entry->out_sample_size = field_buf; 2279 2280 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_OFFSETf, &field_buf); 2281 entry->queue_offset = field_buf; 2282 2283 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_SIGN_EXDf, &field_buf); 2284 entry->sign_ext_enable = field_buf; 2285 2286 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_SIGN_EXD_TYPEf, &field_buf); 2287 entry->sign_ext_type = field_buf; 2288 2289 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_BIT_REVERSALf, &field_buf); 2290 entry->bit_reversal= field_buf; 2291 2292 exit: 2293 sal_free(rd_data_ptr); 2294 SOC_FUNC_RETURN; 2295 2296 } 2297 2298 /* for both encap and decap allocation can use this routine */ 2299 int cprif_drv_encap_data_allocate_buffer(int unit, int port, 2300 cprimod_direction_t dir, 2301 uint16 size_in_bytes, 2302 uint16* offset) 2303 { 2304 2305 cprif_encap_decap_data_entry_t entry; 2306 uint32 *usage_map = NULL; 2307 uint8 queue; 2308 uint16 total_buf; 2309 uint16 num_words; 2310 uint16 num_entries; 2311 uint16 index; 2312 uint16 first_location; 2313 uint16 queue_entry_end_loc; 2314 uint8 location_found; 2315 int rv = SOC_E_NONE; 2316 2317 2318 if (dir == CPRIMOD_DIR_RX) { 2319 total_buf = CPRIF_ENCAP_BUFFER_NUM_ENTRIES; 2320 } else { 2321 total_buf = CPRIF_DECAP_BUFFER_NUM_ENTRIES; 2322 } 2323 /* 2324 * Allocate the memory to keep track of buffer usage. 2325 * Fill every location with 0 to mark as available. 2326 */ 2327 num_words = CPRIF_NUM_PBMP_WORDS(total_buf); 2328 usage_map = (uint32*)sal_alloc((sizeof(uint32) * num_words), "cprif_drv"); 2329 CPRIMOD_NULL_CHECK(usage_map); 2330 sal_memset(usage_map, 0, sizeof(uint32) * num_words); 2331 /* 2332 * Marked all the buffer entries that are allocated to the queue. 2333 */ 2334 for (queue = 0; queue < CPRIF_MAX_NUM_OF_QUEUES; queue++) { 2335 cprif_drv_encap_data_entry_get(unit, port, dir, queue, &entry); 2336 if (entry.queue_size != 0) { 2337 if(dir == CPRIMOD_DIR_TX) { 2338 queue_entry_end_loc = entry.queue_offset+(entry.queue_size 2339 * ((uint16)entry.tx_cycle_size)); 2340 } else { 2341 queue_entry_end_loc = entry.queue_offset+entry.queue_size; 2342 } 2343 for (index = entry.queue_offset; index < queue_entry_end_loc; index++) { 2344 CPRIF_PBMP_IDX_MARK(usage_map,index); 2345 } 2346 } 2347 } 2348 /* 2349 * Find the buffer location that can accomodate num_entries. 2350 */ 2351 index = 0; 2352 first_location = 0; 2353 location_found = FALSE; 2354 num_entries = CPRIF_NUM_OF_BUFFER_ENTRIES(size_in_bytes); 2355 2356 while (num_entries && (index < total_buf)) { 2357 num_entries = CPRIF_NUM_OF_BUFFER_ENTRIES(size_in_bytes); 2358 /* 2359 * Find first available spot. 2360 */ 2361 for ( ;index < total_buf; index++) { 2362 if (CPRIF_PBMP_AVAILABLE(usage_map, index)) { 2363 first_location = index; 2364 location_found = TRUE; 2365 break; 2366 } 2367 } /* for */ 2368 /* 2369 * Check that spot has enough available space. 2370 */ 2371 if (location_found) { 2372 for ( ;(index < total_buf) && (num_entries > 0) ; index++) { 2373 if (CPRIF_PBMP_AVAILABLE(usage_map, index)){ 2374 num_entries--; 2375 } else { 2376 location_found = FALSE; 2377 break; 2378 } 2379 } /* for */ 2380 } 2381 } /* while */ 2382 2383 if (num_entries == 0) { 2384 *offset = first_location; 2385 } else { 2386 rv = SOC_E_UNAVAIL; 2387 } 2388 if (usage_map) { 2389 sal_free(usage_map); 2390 } 2391 return rv; 2392 } 2393 2394 int cprif_drv_rsvd4_encap_data_entry_set(int unit, int port, 2395 cprimod_direction_t dir, 2396 uint32 queue_num, 2397 const cprif_rsvd4_encap_decap_data_entry_t *entry) 2398 { 2399 int blk; 2400 int phy_port; 2401 int port_core_index; 2402 soc_mem_t local_mem; 2403 soc_mem_t rx_mem_select[] = { CPRI_ENCAP_DATA_0m, 2404 CPRI_ENCAP_DATA_1m, 2405 CPRI_ENCAP_DATA_2m, 2406 CPRI_ENCAP_DATA_3m }; 2407 2408 soc_mem_t tx_mem_select[] = { CPRI_DECAP_DATA_0m, 2409 CPRI_DECAP_DATA_1m, 2410 CPRI_DECAP_DATA_2m, 2411 CPRI_DECAP_DATA_3m }; 2412 2413 2414 uint32 *wr_data_ptr; 2415 uint32 field_buf; 2416 uint32 num_words; 2417 SOC_INIT_FUNC_DEFS; 2418 2419 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 2420 port_core_index = ((phy_port-1)%4); 2421 2422 if (dir == CPRIMOD_DIR_TX) { 2423 local_mem = tx_mem_select[port_core_index]; 2424 } else { 2425 local_mem = rx_mem_select[port_core_index]; 2426 } 2427 2428 num_words = soc_mem_entry_words(unit, local_mem); 2429 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 2430 CPRIMOD_NULL_CHECK(wr_data_ptr); 2431 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 2432 2433 /* 2434 * Read existing configuration since not all the fields will be set 2435 * here. 2436 */ 2437 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2438 _SOC_IF_ERR_EXIT 2439 (soc_mem_read(unit, local_mem, blk, queue_num, wr_data_ptr)); 2440 2441 if (dir == CPRIMOD_DIR_RX) { 2442 2443 field_buf = entry->valid; 2444 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_VALIDf, &field_buf); 2445 2446 field_buf = 0; /* mux/demux is always off. */ 2447 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_DEMUX_ENf, &field_buf); 2448 2449 field_buf = (entry->queue_size+CPRIF_DATA_BUFFER_BLOCK_SIZE-1)/CPRIF_DATA_BUFFER_BLOCK_SIZE; 2450 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SIZEf, &field_buf); 2451 2452 field_buf = entry->work_queue_select; 2453 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_WQ_SELf, &field_buf); 2454 2455 field_buf = entry->gsm_control_location; 2456 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_331_3f, &field_buf); 2457 2458 field_buf = 0; 2459 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SIGN_EXDf, &field_buf); 2460 2461 field_buf = entry->gsm_pad_enable; 2462 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_331_2f, &field_buf); 2463 2464 } else { 2465 field_buf = 0; /* Mux Demux is off. */ 2466 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_MUX_ENf, &field_buf); 2467 2468 field_buf = ((entry->queue_size+CPRIF_DATA_BUFFER_BLOCK_SIZE-1)/CPRIF_DATA_BUFFER_BLOCK_SIZE)+1; 2469 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_BUF_SIZEf, &field_buf); 2470 2471 field_buf = entry->tx_cycle_size; 2472 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_CYC_SIZEf, &field_buf); 2473 2474 field_buf = entry->gsm_pad_enable; 2475 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_64_2f, &field_buf); 2476 2477 if(entry->gsm_pad_enable != 0){ 2478 field_buf = entry->gsm_control_location; 2479 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_64_3f, &field_buf); 2480 }else { 2481 field_buf = 0; 2482 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SIGN_EXDf, &field_buf); 2483 } 2484 } 2485 2486 field_buf = entry->queue_offset; 2487 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_OFFSETf, &field_buf); 2488 2489 2490 field_buf = 0; /* Sign extension is off */ 2491 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SIGN_EXD_TYPEf, &field_buf); 2492 2493 field_buf = entry->bit_reversal; 2494 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_BIT_REVERSALf, &field_buf); 2495 2496 if(queue_num >= CPRIF_MAX_NUM_OF_DATA_QUEUES) { 2497 field_buf = 16; 2498 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SAMPLE_SIZEf, &field_buf); 2499 2500 field_buf = 16; 2501 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_OUT_SAMPLE_SIZEf, &field_buf); 2502 } else { 2503 if(entry->gsm_pad_enable != 0){ 2504 2505 if (dir == CPRIMOD_DIR_RX) { 2506 field_buf = entry->gsm_pad_size; 2507 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_331_0f, &field_buf); 2508 2509 field_buf = entry->gsm_extra_pad_size; 2510 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_331_1f, &field_buf); 2511 2512 } else { 2513 field_buf = entry->gsm_pad_size; 2514 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_64_0f, &field_buf); 2515 2516 field_buf = entry->gsm_extra_pad_size; 2517 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_64_1f, &field_buf); 2518 2519 } 2520 2521 } else { 2522 field_buf = 8; 2523 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_SAMPLE_SIZEf, &field_buf); 2524 2525 field_buf = 8; 2526 soc_mem_field_set(unit, local_mem, wr_data_ptr, Q_OUT_SAMPLE_SIZEf, &field_buf); 2527 } 2528 2529 } 2530 2531 _SOC_IF_ERR_EXIT 2532 (soc_mem_write(unit, local_mem, blk, queue_num, wr_data_ptr)); 2533 2534 exit: 2535 sal_free(wr_data_ptr); 2536 SOC_FUNC_RETURN; 2537 2538 } 2539 2540 int cprif_drv_rsvd4_encap_data_entry_get(int unit, int port, 2541 cprimod_direction_t dir, 2542 uint32 queue_num, 2543 cprif_rsvd4_encap_decap_data_entry_t *entry) 2544 { 2545 int blk; 2546 int phy_port; 2547 int port_core_index; 2548 soc_mem_t local_mem; 2549 soc_mem_t rx_mem_select[] = { CPRI_ENCAP_DATA_0m, 2550 CPRI_ENCAP_DATA_1m, 2551 CPRI_ENCAP_DATA_2m, 2552 CPRI_ENCAP_DATA_3m }; 2553 2554 soc_mem_t tx_mem_select[] = { CPRI_DECAP_DATA_0m, 2555 CPRI_DECAP_DATA_1m, 2556 CPRI_DECAP_DATA_2m, 2557 CPRI_DECAP_DATA_3m }; 2558 2559 2560 uint32 *rd_data_ptr; 2561 uint32 field_buf; 2562 uint32 num_words; 2563 SOC_INIT_FUNC_DEFS; 2564 2565 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 2566 port_core_index = ((phy_port-1)%4); 2567 2568 if (dir == CPRIMOD_DIR_TX) { 2569 local_mem = tx_mem_select[port_core_index]; 2570 } else { 2571 local_mem = rx_mem_select[port_core_index]; 2572 } 2573 2574 num_words = soc_mem_entry_words(unit, local_mem); 2575 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 2576 CPRIMOD_NULL_CHECK(rd_data_ptr); 2577 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 2578 2579 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2580 _SOC_IF_ERR_EXIT 2581 (soc_mem_read(unit, local_mem, blk, queue_num, rd_data_ptr)); 2582 2583 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_64_0f, &field_buf); 2584 entry->gsm_pad_size = field_buf; 2585 2586 if (dir == CPRIMOD_DIR_RX) { 2587 2588 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_VALIDf, &field_buf); 2589 entry->valid = field_buf; 2590 2591 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_SIZEf, &field_buf); 2592 entry->queue_size = field_buf * CPRIF_DATA_BUFFER_BLOCK_SIZE; 2593 2594 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_WQ_SELf, &field_buf); 2595 entry->work_queue_select = field_buf; 2596 } else { 2597 2598 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_BUF_SIZEf, &field_buf); 2599 entry->queue_size = field_buf * CPRIF_DATA_BUFFER_BLOCK_SIZE; 2600 2601 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_CYC_SIZEf, &field_buf); 2602 entry->tx_cycle_size = field_buf; 2603 2604 } 2605 2606 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_64_1f, &field_buf); 2607 entry->gsm_extra_pad_size = field_buf; 2608 2609 soc_mem_field_get(unit, local_mem, rd_data_ptr, Q_OFFSETf, &field_buf); 2610 entry->queue_offset = field_buf; 2611 2612 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_64_2f, &field_buf); 2613 entry->gsm_pad_enable = field_buf; 2614 2615 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_64_3f, &field_buf); 2616 entry->gsm_control_location = field_buf; 2617 2618 exit: 2619 sal_free(rd_data_ptr); 2620 SOC_FUNC_RETURN; 2621 2622 } 2623 2624 2625 int cprif_drv_encap_header_entry_set(int unit, int port, 2626 uint32 queue_num, 2627 uint32 flags, 2628 const cprif_encap_header_entry_t *entry) 2629 { 2630 int blk; 2631 int phy_port; 2632 int port_core_index; 2633 soc_mem_t local_mem; 2634 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_ETH_HDR_0m, 2635 CPRI_ENCAP_QUE_ETH_HDR_1m, 2636 CPRI_ENCAP_QUE_ETH_HDR_2m, 2637 CPRI_ENCAP_QUE_ETH_HDR_3m }; 2638 uint32 *wr_data_ptr; 2639 uint32 field_buf; 2640 uint32 num_words; 2641 SOC_INIT_FUNC_DEFS; 2642 2643 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 2644 port_core_index = ((phy_port-1)%4); 2645 2646 local_mem = mem_select[port_core_index]; 2647 2648 num_words = soc_mem_entry_words(unit, local_mem); 2649 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 2650 CPRIMOD_NULL_CHECK(wr_data_ptr); 2651 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 2652 2653 /* 2654 * Read existing configuration since not all the fields will be set 2655 * here. 2656 */ 2657 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2658 _SOC_IF_ERR_EXIT 2659 (soc_mem_read(unit, local_mem, blk, queue_num, wr_data_ptr)); 2660 2661 if (flags & CPRIF_ENCAP_HEADER_FLAGS_HDR_CONFIG_SET) { 2662 field_buf = entry->header_type; 2663 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_TYPEf, &field_buf); 2664 2665 field_buf = entry->ver; 2666 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_VERf , &field_buf); 2667 2668 field_buf = entry->pkttype; 2669 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_PKTTYPEf, &field_buf); 2670 2671 field_buf = entry->ordering_info_index; 2672 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_ORDERINGINFO_INDEXf, &field_buf); 2673 2674 field_buf = entry->mac_da_index;; 2675 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_DA_IDf, &field_buf); 2676 2677 field_buf = entry->mac_sa_index; 2678 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_SA_IDf, &field_buf); 2679 2680 field_buf = entry->vlan_type; 2681 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_VLAN_TYPEf, &field_buf); 2682 2683 field_buf = entry->vlan_id_0_index; 2684 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_VLAN_ID_0f, &field_buf); 2685 2686 field_buf = entry->vlan_id_1_index; 2687 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_VLAN_ID_1f, &field_buf); 2688 2689 field_buf = entry->vlan_0_priority; 2690 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_VLAN_PRI_0f, &field_buf); 2691 2692 field_buf = entry->vlan_1_priority; 2693 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_VLAN_PRI_1f, &field_buf); 2694 2695 field_buf = entry->ether_type_index; 2696 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_VLAN_ETHER_TYPE_INDXf, &field_buf); 2697 2698 field_buf = entry->use_tagid_for_vlan; 2699 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_USE_TAG_ID_FOR_VLANf, &field_buf); 2700 2701 field_buf = entry->use_tagid_for_flowid; 2702 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_USE_TAG_ID_FOR_FLOWIDf, &field_buf); 2703 2704 field_buf = entry->flow_id & 0xFF; 2705 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_FLOWIDf , &field_buf); 2706 2707 field_buf = entry->use_opcode; 2708 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_USE_SUBTYPEf, &field_buf); 2709 2710 if (entry->use_opcode) { 2711 field_buf = entry->roe_opcode; 2712 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_HDR_SUBTYPEf, &field_buf); 2713 } 2714 } 2715 2716 if (flags & CPRIF_ENCAP_HEADER_FLAGS_GSM_CONFIG_SET) { 2717 if(entry->tsn_bitmap != 0){ 2718 field_buf = entry->tsn_bitmap; 2719 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_334_1f, &field_buf); 2720 } 2721 /* ignore this for now. 2722 field_buf = entry->gsm_q_cnt_disable; 2723 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_334_2f, &field_buf); 2724 */ 2725 } 2726 _SOC_IF_ERR_EXIT 2727 (soc_mem_write(unit, local_mem, blk, queue_num, wr_data_ptr)); 2728 2729 exit: 2730 sal_free(wr_data_ptr); 2731 SOC_FUNC_RETURN; 2732 } 2733 2734 int cprif_drv_encap_header_entry_get(int unit, int port, 2735 uint32 queue_num, 2736 cprif_encap_header_entry_t *entry) 2737 { 2738 int blk; 2739 int phy_port; 2740 int port_core_index; 2741 soc_mem_t local_mem; 2742 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_ETH_HDR_0m, 2743 CPRI_ENCAP_QUE_ETH_HDR_1m, 2744 CPRI_ENCAP_QUE_ETH_HDR_2m, 2745 CPRI_ENCAP_QUE_ETH_HDR_3m }; 2746 uint32 *rd_data_ptr; 2747 uint32 field_buf; 2748 uint32 num_words; 2749 SOC_INIT_FUNC_DEFS; 2750 2751 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 2752 port_core_index = ((phy_port-1)%4); 2753 2754 local_mem = mem_select[port_core_index]; 2755 2756 num_words = soc_mem_entry_words(unit, local_mem); 2757 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 2758 CPRIMOD_NULL_CHECK(rd_data_ptr); 2759 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 2760 2761 /* 2762 * Read configuration 2763 */ 2764 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 2765 _SOC_IF_ERR_EXIT 2766 (soc_mem_read(unit, local_mem, blk, queue_num, rd_data_ptr)); 2767 2768 2769 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_TYPEf, &field_buf); 2770 entry->header_type = field_buf; 2771 2772 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_FLOWIDf , &field_buf); 2773 entry->flow_id = field_buf; 2774 2775 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_VERf , &field_buf); 2776 entry->ver = field_buf; 2777 2778 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_PKTTYPEf, &field_buf); 2779 entry->pkttype = field_buf; 2780 2781 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_ORDERINGINFO_INDEXf, &field_buf); 2782 entry->ordering_info_index = field_buf; 2783 2784 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_DA_IDf, &field_buf); 2785 entry->mac_da_index = field_buf; 2786 2787 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_SA_IDf, &field_buf); 2788 entry->mac_sa_index = field_buf; 2789 2790 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_VLAN_TYPEf, &field_buf); 2791 entry->vlan_type = field_buf; 2792 2793 field_buf = entry->vlan_id_0_index; 2794 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_VLAN_ID_0f, &field_buf); 2795 entry->vlan_id_0_index = field_buf; 2796 2797 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_VLAN_ID_1f, &field_buf); 2798 entry->vlan_id_1_index = field_buf; 2799 2800 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_VLAN_PRI_0f, &field_buf); 2801 entry->vlan_0_priority = field_buf; 2802 2803 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_VLAN_PRI_1f, &field_buf); 2804 entry->vlan_1_priority = field_buf; 2805 2806 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_VLAN_ETHER_TYPE_INDXf, &field_buf); 2807 entry->ether_type_index = field_buf; 2808 2809 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_USE_TAG_ID_FOR_VLANf, &field_buf); 2810 entry->use_tagid_for_vlan = field_buf; 2811 2812 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_USE_TAG_ID_FOR_FLOWIDf, &field_buf); 2813 entry->use_tagid_for_flowid = field_buf; 2814 2815 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_USE_SUBTYPEf, &field_buf); 2816 entry->use_opcode = field_buf; 2817 2818 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_HDR_SUBTYPEf, &field_buf); 2819 entry->roe_opcode = field_buf; 2820 2821 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_334_1f, &field_buf); 2822 entry->tsn_bitmap = field_buf; 2823 2824 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_334_2f, &field_buf); 2825 entry->gsm_q_cnt_disable = field_buf; 2826 2827 exit: 2828 sal_free(rd_data_ptr); 2829 SOC_FUNC_RETURN; 2830 } 2831 2832 2833 2834 int cprif_drv_cprimod_to_cprif_ordering_info_type (cprimod_ordering_info_type_t cprimod_type, uint8* cprif_type) 2835 { 2836 switch (cprimod_type) { 2837 case cprimod_ordering_info_type_roe_sequence: 2838 *cprif_type = CPRIF_ORDERING_INFO_TYPE_ROE; 2839 break; 2840 2841 case cprimod_ordering_info_type_bfn_for_qcnt: 2842 *cprif_type = CPRIF_ORDERING_INFO_TYPE_BFN_FOR_QCNT; 2843 break; 2844 2845 case cprimod_ordering_info_type_use_pinfo: 2846 *cprif_type = CPRIF_ORDERING_INFO_TYPE_USE_PINFO; 2847 break; 2848 default: 2849 break; 2850 } 2851 return SOC_E_NONE; 2852 2853 } 2854 2855 int cprif_drv_cprif_to_cprimod_ordering_info_type (uint8 cprif_type , cprimod_ordering_info_type_t *cprimod_type ) 2856 { 2857 switch (cprif_type) { 2858 case CPRIF_ORDERING_INFO_TYPE_ROE : 2859 *cprimod_type = cprimod_ordering_info_type_roe_sequence; 2860 break; 2861 2862 case CPRIF_ORDERING_INFO_TYPE_BFN_FOR_QCNT : 2863 *cprimod_type = cprimod_ordering_info_type_bfn_for_qcnt; 2864 break; 2865 2866 case CPRIF_ORDERING_INFO_TYPE_USE_PINFO : 2867 *cprimod_type = cprimod_ordering_info_type_use_pinfo; 2868 break; 2869 default: 2870 break; 2871 } 2872 return SOC_E_NONE; 2873 } 2874 2875 int cprif_drv_cprimod_to_cprif_ordering_info_inc_prop (cprimod_ordering_info_prop_t cprimod_prop, uint8 *cprif_prop) 2876 { 2877 switch (cprimod_prop) { 2878 case cprimod_ordering_info_prop_no_increment: 2879 *cprif_prop = CPRIF_ORDERING_INFO_PROP_NO_INC; 2880 break; 2881 2882 case cprimod_ordering_info_prop_increment_by_constant: 2883 *cprif_prop = CPRIF_ORDERING_INFO_PROP_INC_CONST; 2884 break; 2885 2886 case cprimod_ordering_info_prop_increment_by_payload: 2887 *cprif_prop = CPRIF_ORDERING_INFO_PROP_INC_BY_PAYLOAD; 2888 break; 2889 2890 default: 2891 *cprif_prop = CPRIF_ORDERING_INFO_PROP_INC_CONST; 2892 break; 2893 } 2894 return SOC_E_NONE; 2895 } 2896 2897 2898 int cprif_drv_cprif_to_cprimod_ordering_info_inc_prop (uint8 cprif_prop, cprimod_ordering_info_prop_t *cprimod_prop) 2899 { 2900 switch (cprif_prop) { 2901 case CPRIF_ORDERING_INFO_PROP_NO_INC: 2902 *cprimod_prop = cprimod_ordering_info_prop_no_increment; 2903 break; 2904 2905 case CPRIF_ORDERING_INFO_PROP_INC_CONST: 2906 *cprimod_prop = cprimod_ordering_info_prop_increment_by_constant; 2907 break; 2908 2909 case CPRIF_ORDERING_INFO_PROP_INC_BY_PAYLOAD: 2910 *cprimod_prop = cprimod_ordering_info_prop_increment_by_payload; 2911 break; 2912 2913 default: 2914 *cprimod_prop = CPRIF_ORDERING_INFO_PROP_INC_CONST; 2915 break; 2916 } 2917 return SOC_E_NONE; 2918 } 2919 2920 2921 int cprif_drv_encap_vlan_ethtype_set(int unit, int port, 2922 uint8 ethtype_id, 2923 uint16 ethtype) 2924 2925 { 2926 uint64 reg_val; 2927 uint64 write_val; 2928 uint32 local_ethtype; 2929 2930 2931 switch (ethtype_id) { 2932 case CPRIF_ETHTYPE_ROE_ETHTYPE_0: 2933 COMPILER_64_SET(write_val, 0, (uint32) ethtype); 2934 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_CTRLr(unit, port, 2935 ®_val)); 2936 soc_reg64_field_set(unit, CPRI_ENCAP_VLAN_CTRLr, ®_val, 2937 ENCAP_ROE_ETHERTYPE_0f, write_val); 2938 SOC_IF_ERROR_RETURN(WRITE_CPRI_ENCAP_VLAN_CTRLr(unit, port, 2939 reg_val)); 2940 break; 2941 2942 case CPRIF_ETHTYPE_ROE_ETHTYPE_1: 2943 COMPILER_64_SET(write_val, 0, (uint32) ethtype); 2944 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_QINQ_CTRLr(unit, 2945 port, ®_val)); 2946 soc_reg64_field_set(unit, CPRI_ENCAP_VLAN_QINQ_CTRLr, 2947 ®_val, ENCAP_ROE_ETHERTYPE_1f, write_val); 2948 SOC_IF_ERROR_RETURN(WRITE_CPRI_ENCAP_VLAN_QINQ_CTRLr(unit, 2949 port, reg_val)); 2950 2951 break; 2952 2953 case CPRIF_ETHTYPE_VLAN_TAGGED: 2954 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_CTRLr(unit, port, 2955 ®_val)); 2956 local_ethtype = ethtype; 2957 local_ethtype = local_ethtype << 16; 2958 COMPILER_64_SET(write_val, 0, local_ethtype); 2959 soc_reg64_field_set(unit, CPRI_ENCAP_VLAN_CTRLr, ®_val, 2960 ENCAP_VLAN_TAGGEDf, write_val); 2961 SOC_IF_ERROR_RETURN(WRITE_CPRI_ENCAP_VLAN_CTRLr(unit, port, 2962 reg_val)); 2963 2964 break; 2965 2966 case CPRIF_ETHTYPE_VLAN_QINQ: 2967 local_ethtype = ethtype; 2968 local_ethtype = local_ethtype << 16; 2969 COMPILER_64_SET(write_val, 0, local_ethtype); 2970 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_QINQ_CTRLr(unit, 2971 port, ®_val)); 2972 soc_reg64_field_set(unit, CPRI_ENCAP_VLAN_QINQ_CTRLr, 2973 ®_val, ENCAP_VLAN_QINQf, write_val); 2974 SOC_IF_ERROR_RETURN(WRITE_CPRI_ENCAP_VLAN_QINQ_CTRLr(unit, 2975 port, reg_val)); 2976 2977 break; 2978 2979 default: 2980 break; 2981 } 2982 2983 return SOC_E_NONE; 2984 2985 } 2986 2987 int cprif_drv_encap_vlan_ethtype_get(int unit, int port, 2988 uint8 ethtype_id, 2989 uint16* ethtype) 2990 2991 { 2992 uint64 reg_val; 2993 uint64 read_val; 2994 2995 switch (ethtype_id) { 2996 case CPRIF_ETHTYPE_ROE_ETHTYPE_0: 2997 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_CTRLr(unit, port, 2998 ®_val)); 2999 read_val = soc_reg64_field_get(unit, CPRI_ENCAP_VLAN_CTRLr, 3000 reg_val, ENCAP_ROE_ETHERTYPE_0f); 3001 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3002 break; 3003 3004 case CPRIF_ETHTYPE_ROE_ETHTYPE_1: 3005 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_QINQ_CTRLr(unit, 3006 port, ®_val)); 3007 read_val = soc_reg64_field_get(unit, 3008 CPRI_ENCAP_VLAN_QINQ_CTRLr, reg_val, 3009 ENCAP_ROE_ETHERTYPE_1f); 3010 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3011 break; 3012 3013 case CPRIF_ETHTYPE_VLAN_TAGGED: 3014 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_CTRLr(unit, port, 3015 ®_val)); 3016 read_val = soc_reg64_field_get(unit, CPRI_ENCAP_VLAN_CTRLr, 3017 reg_val, ENCAP_VLAN_TAGGEDf); 3018 COMPILER_64_SHR(read_val, 16); 3019 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3020 break; 3021 3022 case CPRIF_ETHTYPE_VLAN_QINQ: 3023 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_VLAN_QINQ_CTRLr(unit, 3024 port, ®_val)); 3025 read_val = soc_reg64_field_get(unit, 3026 CPRI_ENCAP_VLAN_QINQ_CTRLr, reg_val, 3027 ENCAP_VLAN_QINQf); 3028 COMPILER_64_SHR(read_val, 16); 3029 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3030 break; 3031 3032 default: 3033 break; 3034 } 3035 3036 return SOC_E_NONE; 3037 3038 } 3039 3040 int cprif_drv_encap_ordering_info_entry_set(int unit, int port, 3041 uint8 index , 3042 const cprif_encap_ordering_info_entry_t *entry) 3043 { 3044 int blk; 3045 int phy_port; 3046 int port_core_index; 3047 soc_mem_t local_mem; 3048 soc_mem_t mem_select[] = { CPRI_ENCAP_ORDERING_INFO_TAB_0m, 3049 CPRI_ENCAP_ORDERING_INFO_TAB_1m, 3050 CPRI_ENCAP_ORDERING_INFO_TAB_2m, 3051 CPRI_ENCAP_ORDERING_INFO_TAB_3m }; 3052 3053 uint32 *wr_data_ptr; 3054 uint32 field_buf; 3055 uint32 num_words; 3056 SOC_INIT_FUNC_DEFS; 3057 3058 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3059 port_core_index = ((phy_port-1)%4); 3060 3061 local_mem = mem_select[port_core_index]; 3062 3063 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 3064 LOG_CLI(("Encap Ordering info only have %d entries, %d is out of range", 3065 CPRIF_ORDERING_INFO_TABLE_SIZE, 3066 index)); 3067 return SOC_E_PARAM; 3068 } 3069 3070 num_words = soc_mem_entry_words(unit, local_mem); 3071 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3072 CPRIMOD_NULL_CHECK(wr_data_ptr); 3073 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3074 3075 /* 3076 * Read existing configuration since not all the fields will be set 3077 * here. 3078 */ 3079 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3080 _SOC_IF_ERR_EXIT 3081 (soc_mem_read(unit, local_mem, blk, index, wr_data_ptr)); 3082 3083 field_buf = entry->type; 3084 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_TYPEf, &field_buf); 3085 3086 field_buf = entry->p_size; 3087 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_PSIZEf, &field_buf); 3088 3089 field_buf = entry->q_size; 3090 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_QSIZEf, &field_buf); 3091 3092 field_buf = entry->max; 3093 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQMAXf, &field_buf); 3094 3095 field_buf = entry->increment; 3096 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQINCf, &field_buf); 3097 3098 field_buf = entry->pcnt_prop; 3099 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_PCNT_PROPf, &field_buf); 3100 3101 field_buf = entry->qcnt_prop; 3102 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_QCNT_PROPf, &field_buf); 3103 3104 _SOC_IF_ERR_EXIT 3105 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 3106 3107 exit: 3108 sal_free(wr_data_ptr); 3109 SOC_FUNC_RETURN; 3110 } 3111 3112 int cprif_drv_encap_ordering_info_entry_get(int unit, int port, 3113 uint8 index, 3114 cprif_encap_ordering_info_entry_t *entry) 3115 { 3116 int blk; 3117 int phy_port; 3118 int port_core_index; 3119 soc_mem_t local_mem; 3120 soc_mem_t mem_select[] = { CPRI_ENCAP_ORDERING_INFO_TAB_0m, 3121 CPRI_ENCAP_ORDERING_INFO_TAB_1m, 3122 CPRI_ENCAP_ORDERING_INFO_TAB_2m, 3123 CPRI_ENCAP_ORDERING_INFO_TAB_3m }; 3124 uint32 *rd_data_ptr; 3125 uint32 field_buf; 3126 uint32 num_words; 3127 SOC_INIT_FUNC_DEFS; 3128 3129 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3130 port_core_index = ((phy_port-1)%4); 3131 3132 local_mem = mem_select[port_core_index]; 3133 3134 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 3135 LOG_CLI(("Encap Ordering info only have %d entries, %d is out of range", 3136 CPRIF_ORDERING_INFO_TABLE_SIZE, 3137 index)); 3138 return SOC_E_PARAM; 3139 } 3140 3141 3142 num_words = soc_mem_entry_words(unit, local_mem); 3143 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3144 CPRIMOD_NULL_CHECK(rd_data_ptr); 3145 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3146 3147 /* 3148 * Read configuration 3149 */ 3150 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3151 _SOC_IF_ERR_EXIT 3152 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 3153 3154 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_TYPEf, &field_buf); 3155 entry->type = field_buf; 3156 3157 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_PSIZEf, &field_buf); 3158 entry->p_size = field_buf; 3159 3160 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_QSIZEf, &field_buf); 3161 entry->q_size = field_buf; 3162 3163 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQMAXf, &field_buf); 3164 entry->max = field_buf; 3165 3166 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQINCf, &field_buf); 3167 entry->increment = field_buf; 3168 3169 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_PCNT_PROPf, &field_buf); 3170 entry->pcnt_prop = field_buf; 3171 3172 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_QCNT_PROPf, &field_buf); 3173 entry->qcnt_prop = field_buf; 3174 3175 exit: 3176 sal_free(rd_data_ptr); 3177 SOC_FUNC_RETURN; 3178 } 3179 3180 int cprif_drv_decap_ordering_info_entry_set(int unit, int port, 3181 uint8 index , 3182 const cprif_decap_ordering_info_entry_t *entry) 3183 { 3184 int blk; 3185 int phy_port; 3186 int port_core_index; 3187 soc_mem_t local_mem; 3188 soc_mem_t mem_select[] = { CPRI_DECAP_ORDERING_INFO_TAB_0m , 3189 CPRI_DECAP_ORDERING_INFO_TAB_1m , 3190 CPRI_DECAP_ORDERING_INFO_TAB_2m , 3191 CPRI_DECAP_ORDERING_INFO_TAB_3m }; 3192 uint32 *wr_data_ptr; 3193 uint32 field_buf; 3194 uint32 num_words; 3195 SOC_INIT_FUNC_DEFS; 3196 3197 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3198 port_core_index = ((phy_port-1)%4); 3199 3200 local_mem = mem_select[port_core_index]; 3201 3202 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 3203 LOG_CLI(("Decap Ordering info only have %d entries, %d is out of range", 3204 CPRIF_ORDERING_INFO_TABLE_SIZE, 3205 index)); 3206 return SOC_E_PARAM; 3207 } 3208 3209 num_words = soc_mem_entry_words(unit, local_mem); 3210 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3211 CPRIMOD_NULL_CHECK(wr_data_ptr); 3212 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3213 3214 /* 3215 * Read existing configuration since not all the fields will be set 3216 * here. 3217 */ 3218 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3219 _SOC_IF_ERR_EXIT 3220 (soc_mem_read(unit, local_mem, blk, index, wr_data_ptr)); 3221 3222 field_buf = entry->type; 3223 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_TYPEf, &field_buf); 3224 3225 field_buf = entry->p_size; 3226 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_PSIZEf, &field_buf); 3227 3228 field_buf = entry->q_size; 3229 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_QSIZEf, &field_buf); 3230 3231 field_buf = entry->max; 3232 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQMAXf, &field_buf); 3233 3234 field_buf = entry->increment; 3235 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQINCf, &field_buf); 3236 3237 3238 field_buf = entry->pcnt_inc_p2; 3239 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQNUM_P_INC_P2f, &field_buf); 3240 3241 field_buf = entry->qcnt_inc_p2; 3242 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQNUM_Q_INC_P2f, &field_buf); 3243 3244 field_buf = entry->pcnt_extended; 3245 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQNUM_P_EXTENDf, &field_buf); 3246 3247 field_buf = entry->pcnt_pkt_count; 3248 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQNUM_P_PKTCNTf, &field_buf); 3249 3250 field_buf = entry->modulo_2; 3251 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQNUM_MODULO_P2f, &field_buf); 3252 3253 field_buf = entry->bias; 3254 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQINC_BIASf, &field_buf); 3255 3256 field_buf = entry->gsm_tsn_bitmap; 3257 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_43_0f, &field_buf); 3258 3259 _SOC_IF_ERR_EXIT 3260 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 3261 3262 exit: 3263 sal_free(wr_data_ptr); 3264 SOC_FUNC_RETURN; 3265 } 3266 3267 int cprif_drv_decap_ordering_info_entry_get(int unit, int port, 3268 uint8 index, 3269 cprif_decap_ordering_info_entry_t *entry) 3270 { 3271 int blk; 3272 int phy_port; 3273 int port_core_index; 3274 soc_mem_t local_mem; 3275 soc_mem_t mem_select[] = { CPRI_DECAP_ORDERING_INFO_TAB_0m , 3276 CPRI_DECAP_ORDERING_INFO_TAB_1m , 3277 CPRI_DECAP_ORDERING_INFO_TAB_2m , 3278 CPRI_DECAP_ORDERING_INFO_TAB_3m }; 3279 uint32 *rd_data_ptr; 3280 uint32 field_buf; 3281 uint32 num_words; 3282 SOC_INIT_FUNC_DEFS; 3283 3284 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3285 port_core_index = ((phy_port-1)%4); 3286 3287 local_mem = mem_select[port_core_index]; 3288 3289 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 3290 LOG_CLI(("Encap Ordering info only have %d entries, %d is out of range", 3291 CPRIF_ORDERING_INFO_TABLE_SIZE, 3292 index)); 3293 return SOC_E_PARAM; 3294 } 3295 3296 3297 num_words = soc_mem_entry_words(unit, local_mem); 3298 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3299 CPRIMOD_NULL_CHECK(rd_data_ptr); 3300 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3301 3302 /* 3303 * Read configuration 3304 */ 3305 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3306 _SOC_IF_ERR_EXIT 3307 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 3308 3309 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_TYPEf, &field_buf); 3310 entry->type = field_buf; 3311 3312 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_PSIZEf, &field_buf); 3313 entry->p_size = field_buf; 3314 3315 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_QSIZEf, &field_buf); 3316 entry->q_size = field_buf; 3317 3318 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQMAXf, &field_buf); 3319 entry->max = field_buf; 3320 3321 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQINCf, &field_buf); 3322 entry->increment = field_buf; 3323 3324 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQNUM_P_INC_P2f, &field_buf); 3325 entry->pcnt_inc_p2 = field_buf; 3326 3327 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQNUM_Q_INC_P2f, &field_buf); 3328 entry->qcnt_inc_p2 = field_buf; 3329 3330 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQNUM_P_EXTENDf, &field_buf); 3331 entry->pcnt_extended = field_buf; 3332 3333 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQNUM_P_PKTCNTf, &field_buf); 3334 entry->pcnt_pkt_count = field_buf; 3335 3336 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQNUM_MODULO_P2f, &field_buf); 3337 entry->modulo_2 = field_buf; 3338 3339 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQINC_BIASf, &field_buf); 3340 entry->bias = field_buf; 3341 3342 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_43_0f, &field_buf); 3343 entry->gsm_tsn_bitmap = field_buf; 3344 3345 exit: 3346 sal_free(rd_data_ptr); 3347 SOC_FUNC_RETURN; 3348 } 3349 3350 3351 int cprif_drv_decap_queue_to_ordering_info_index_set(int unit, int port, 3352 uint32 queue, 3353 uint32 index) 3354 { 3355 int blk; 3356 int phy_port; 3357 int port_core_index; 3358 soc_mem_t local_mem; 3359 soc_mem_t mem_select[] = { CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_0m , 3360 CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_1m , 3361 CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_2m , 3362 CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_3m }; 3363 3364 uint32 *wr_data_ptr; 3365 uint32 field_buf; 3366 uint32 num_words; 3367 SOC_INIT_FUNC_DEFS; 3368 3369 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3370 port_core_index = ((phy_port-1)%4); 3371 3372 local_mem = mem_select[port_core_index]; 3373 3374 num_words = soc_mem_entry_words(unit, local_mem); 3375 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3376 CPRIMOD_NULL_CHECK(wr_data_ptr); 3377 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3378 3379 field_buf = index; 3380 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_DECAP_ORDERING_INFO_INDEXf, &field_buf); 3381 3382 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3383 _SOC_IF_ERR_EXIT 3384 (soc_mem_write(unit, local_mem, blk, queue, wr_data_ptr)); 3385 3386 exit: 3387 sal_free(wr_data_ptr); 3388 SOC_FUNC_RETURN; 3389 } 3390 3391 3392 int cprif_drv_decap_queue_to_ordering_info_index_get(int unit, int port, 3393 uint32 queue, 3394 uint32* index) 3395 3396 { 3397 int blk; 3398 int phy_port; 3399 int port_core_index; 3400 soc_mem_t local_mem; 3401 soc_mem_t mem_select[] = { CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_0m , 3402 CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_1m , 3403 CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_2m , 3404 CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_3m }; 3405 3406 uint32 *rd_data_ptr; 3407 uint32 field_buf; 3408 uint32 num_words; 3409 SOC_INIT_FUNC_DEFS; 3410 3411 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3412 port_core_index = ((phy_port-1)%4); 3413 3414 local_mem = mem_select[port_core_index]; 3415 3416 num_words = soc_mem_entry_words(unit, local_mem); 3417 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3418 CPRIMOD_NULL_CHECK(rd_data_ptr); 3419 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3420 3421 /* 3422 * Read configuration 3423 */ 3424 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3425 _SOC_IF_ERR_EXIT 3426 (soc_mem_read(unit, local_mem, blk, queue, rd_data_ptr)); 3427 3428 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_DECAP_ORDERING_INFO_INDEXf, &field_buf); 3429 *index = field_buf; 3430 3431 exit: 3432 sal_free(rd_data_ptr); 3433 SOC_FUNC_RETURN; 3434 } 3435 3436 int cprif_drv_encap_queue_ordering_info_sequence_offset_set(int unit, int port, 3437 uint32 queue, 3438 uint8 control, 3439 uint32 pq_offset) 3440 { 3441 int blk; 3442 int phy_port; 3443 int port_core_index; 3444 soc_mem_t local_mem; 3445 soc_mem_t mem_select[] = { CPRI_ENCAP_ORDERING_INFO_STS_0m, 3446 CPRI_ENCAP_ORDERING_INFO_STS_1m, 3447 CPRI_ENCAP_ORDERING_INFO_STS_2m, 3448 CPRI_ENCAP_ORDERING_INFO_STS_3m }; 3449 3450 3451 uint32 *wr_data_ptr; 3452 uint32 field_buf; 3453 uint32 num_words; 3454 SOC_INIT_FUNC_DEFS; 3455 3456 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3457 port_core_index = ((phy_port-1)%4); 3458 3459 local_mem = mem_select[port_core_index]; 3460 3461 num_words = soc_mem_entry_words(unit, local_mem); 3462 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3463 CPRIMOD_NULL_CHECK(wr_data_ptr); 3464 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3465 3466 /* 3467 * Read existing configuration since not all the fields will be set 3468 * here. 3469 */ 3470 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3471 _SOC_IF_ERR_EXIT 3472 (soc_mem_read(unit, local_mem, blk, queue, wr_data_ptr)); 3473 3474 field_buf = pq_offset; 3475 if (control) { 3476 soc_mem_field_set(unit, local_mem, wr_data_ptr, CUR_SEQ_NUM_CTLf, &field_buf); 3477 } else { 3478 soc_mem_field_set(unit, local_mem, wr_data_ptr, CUR_SEQ_NUM_DATAf, &field_buf); 3479 } 3480 _SOC_IF_ERR_EXIT 3481 (soc_mem_write(unit, local_mem, blk, queue, wr_data_ptr)); 3482 3483 exit: 3484 sal_free(wr_data_ptr); 3485 SOC_FUNC_RETURN; 3486 } 3487 3488 3489 int cprif_drv_encap_queue_ordering_info_sequence_offset_get(int unit, int port, 3490 uint32 queue, 3491 uint8 control, 3492 uint32* pq_offset) 3493 3494 { 3495 int blk; 3496 int phy_port; 3497 int port_core_index; 3498 soc_mem_t local_mem; 3499 soc_mem_t mem_select[] = { CPRI_ENCAP_ORDERING_INFO_STS_0m, 3500 CPRI_ENCAP_ORDERING_INFO_STS_1m, 3501 CPRI_ENCAP_ORDERING_INFO_STS_2m, 3502 CPRI_ENCAP_ORDERING_INFO_STS_3m }; 3503 uint32 *rd_data_ptr; 3504 uint32 field_buf; 3505 uint32 num_words; 3506 SOC_INIT_FUNC_DEFS; 3507 3508 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3509 port_core_index = ((phy_port-1)%4); 3510 3511 local_mem = mem_select[port_core_index]; 3512 3513 num_words = soc_mem_entry_words(unit, local_mem); 3514 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3515 CPRIMOD_NULL_CHECK(rd_data_ptr); 3516 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3517 3518 /* 3519 * Read configuration 3520 */ 3521 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3522 _SOC_IF_ERR_EXIT 3523 (soc_mem_read(unit, local_mem, blk, queue, rd_data_ptr)); 3524 3525 if (control) { 3526 soc_mem_field_get(unit, local_mem, rd_data_ptr, CUR_SEQ_NUM_CTLf, &field_buf); 3527 } else { 3528 soc_mem_field_get(unit, local_mem, rd_data_ptr, CUR_SEQ_NUM_DATAf, &field_buf); 3529 } 3530 3531 *pq_offset = field_buf; 3532 3533 exit: 3534 sal_free(rd_data_ptr); 3535 SOC_FUNC_RETURN; 3536 } 3537 3538 int cprif_drv_decap_queue_ordering_info_sequence_offset_set(int unit, int port, 3539 uint32 queue, 3540 uint32 pq_offset) 3541 { 3542 int blk; 3543 int phy_port; 3544 int port_core_index; 3545 soc_mem_t local_mem; 3546 soc_mem_t mem_select[] = { CPRI_DECAP_ORDERING_SEQOFF_TAB_0m , 3547 CPRI_DECAP_ORDERING_SEQOFF_TAB_1m , 3548 CPRI_DECAP_ORDERING_SEQOFF_TAB_2m , 3549 CPRI_DECAP_ORDERING_SEQOFF_TAB_3m }; 3550 uint32 *wr_data_ptr; 3551 uint32 field_buf; 3552 uint32 num_words; 3553 SOC_INIT_FUNC_DEFS; 3554 3555 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3556 port_core_index = ((phy_port-1)%4); 3557 3558 local_mem = mem_select[port_core_index]; 3559 3560 num_words = soc_mem_entry_words(unit, local_mem); 3561 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3562 CPRIMOD_NULL_CHECK(wr_data_ptr); 3563 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3564 3565 /* 3566 * Read existing configuration since not all the fields will be set 3567 * here. 3568 */ 3569 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3570 _SOC_IF_ERR_EXIT 3571 (soc_mem_read(unit, local_mem, blk, queue, wr_data_ptr)); 3572 3573 field_buf = pq_offset; 3574 soc_mem_field_set(unit, local_mem, wr_data_ptr, ORDERING_INFO_SEQOFFf, &field_buf); 3575 _SOC_IF_ERR_EXIT 3576 (soc_mem_write(unit, local_mem, blk, queue, wr_data_ptr)); 3577 3578 exit: 3579 sal_free(wr_data_ptr); 3580 SOC_FUNC_RETURN; 3581 } 3582 3583 3584 int cprif_drv_decap_queue_ordering_info_sequence_offset_get(int unit, int port, 3585 uint32 queue, 3586 uint32* pq_offset) 3587 3588 { 3589 int blk; 3590 int phy_port; 3591 int port_core_index; 3592 soc_mem_t local_mem; 3593 soc_mem_t mem_select[] = { CPRI_DECAP_ORDERING_SEQOFF_TAB_0m , 3594 CPRI_DECAP_ORDERING_SEQOFF_TAB_1m , 3595 CPRI_DECAP_ORDERING_SEQOFF_TAB_2m , 3596 CPRI_DECAP_ORDERING_SEQOFF_TAB_3m }; 3597 3598 uint32 *rd_data_ptr; 3599 uint32 field_buf; 3600 uint32 num_words; 3601 SOC_INIT_FUNC_DEFS; 3602 3603 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3604 port_core_index = ((phy_port-1)%4); 3605 3606 local_mem = mem_select[port_core_index]; 3607 3608 num_words = soc_mem_entry_words(unit, local_mem); 3609 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3610 CPRIMOD_NULL_CHECK(rd_data_ptr); 3611 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3612 3613 /* 3614 * Read configuration 3615 */ 3616 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3617 _SOC_IF_ERR_EXIT 3618 (soc_mem_read(unit, local_mem, blk, queue, rd_data_ptr)); 3619 3620 soc_mem_field_get(unit, local_mem, rd_data_ptr, ORDERING_INFO_SEQOFFf, &field_buf); 3621 3622 *pq_offset = field_buf; 3623 3624 exit: 3625 sal_free(rd_data_ptr); 3626 SOC_FUNC_RETURN; 3627 } 3628 3629 int cprif_drv_encap_mac_da_set(int unit, int port, 3630 uint32 index, 3631 uint64 mac_addr) 3632 { 3633 int blk; 3634 int phy_port; 3635 int port_core_index; 3636 soc_mem_t local_mem; 3637 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_DA_TAB_0m, 3638 CPRI_ENCAP_QUE_DA_TAB_1m, 3639 CPRI_ENCAP_QUE_DA_TAB_2m, 3640 CPRI_ENCAP_QUE_DA_TAB_3m }; 3641 3642 uint32 *wr_data_ptr; 3643 uint32 num_words; 3644 uint32 local_mac_addr[2]; 3645 SOC_INIT_FUNC_DEFS; 3646 3647 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3648 port_core_index = ((phy_port-1)%4); 3649 3650 local_mem = mem_select[port_core_index]; 3651 3652 num_words = soc_mem_entry_words(unit, local_mem); 3653 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3654 CPRIMOD_NULL_CHECK(wr_data_ptr); 3655 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3656 3657 COMPILER_64_TO_32_LO(local_mac_addr[0],mac_addr); 3658 COMPILER_64_TO_32_HI(local_mac_addr[1],mac_addr); 3659 local_mac_addr[1] &= 0xffff; 3660 3661 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_DAf, local_mac_addr); 3662 3663 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3664 _SOC_IF_ERR_EXIT 3665 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 3666 3667 exit: 3668 sal_free(wr_data_ptr); 3669 SOC_FUNC_RETURN; 3670 } 3671 3672 int cprif_drv_encap_mac_da_get(int unit, int port, 3673 uint32 index, 3674 uint64 *mac_addr) 3675 3676 { 3677 int blk; 3678 int phy_port; 3679 int port_core_index; 3680 soc_mem_t local_mem; 3681 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_DA_TAB_0m, 3682 CPRI_ENCAP_QUE_DA_TAB_1m, 3683 CPRI_ENCAP_QUE_DA_TAB_2m, 3684 CPRI_ENCAP_QUE_DA_TAB_3m }; 3685 3686 uint32 *rd_data_ptr; 3687 uint32 num_words; 3688 uint32 local_mac_addr[2]; 3689 SOC_INIT_FUNC_DEFS; 3690 3691 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3692 port_core_index = ((phy_port-1)%4); 3693 3694 local_mem = mem_select[port_core_index]; 3695 3696 num_words = soc_mem_entry_words(unit, local_mem); 3697 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3698 CPRIMOD_NULL_CHECK(rd_data_ptr); 3699 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3700 3701 /* 3702 * Read configuration 3703 */ 3704 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3705 _SOC_IF_ERR_EXIT 3706 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 3707 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_DAf, local_mac_addr); 3708 COMPILER_64_SET(*mac_addr,local_mac_addr[1], local_mac_addr[0]); 3709 3710 exit: 3711 sal_free(rd_data_ptr); 3712 SOC_FUNC_RETURN; 3713 3714 3715 } 3716 int cprif_drv_encap_mac_sa_set(int unit, int port, 3717 uint32 index, 3718 uint64 mac_addr) 3719 { 3720 int blk; 3721 int phy_port; 3722 int port_core_index; 3723 soc_mem_t local_mem; 3724 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_SA_TAB_0m, 3725 CPRI_ENCAP_QUE_SA_TAB_1m, 3726 CPRI_ENCAP_QUE_SA_TAB_2m, 3727 CPRI_ENCAP_QUE_SA_TAB_3m }; 3728 3729 uint32 *wr_data_ptr; 3730 uint32 num_words; 3731 uint32 local_mac_addr[2]; 3732 SOC_INIT_FUNC_DEFS; 3733 3734 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3735 port_core_index = ((phy_port-1)%4); 3736 3737 local_mem = mem_select[port_core_index]; 3738 3739 num_words = soc_mem_entry_words(unit, local_mem); 3740 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3741 CPRIMOD_NULL_CHECK(wr_data_ptr); 3742 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3743 3744 COMPILER_64_TO_32_LO(local_mac_addr[0],mac_addr); 3745 COMPILER_64_TO_32_HI(local_mac_addr[1],mac_addr); 3746 local_mac_addr[1] &= 0xffff; 3747 3748 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_SAf, local_mac_addr); 3749 3750 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3751 _SOC_IF_ERR_EXIT 3752 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 3753 3754 exit: 3755 sal_free(wr_data_ptr); 3756 SOC_FUNC_RETURN; 3757 } 3758 3759 int cprif_drv_encap_mac_sa_get(int unit, int port, 3760 uint32 index, 3761 uint64* mac_addr) 3762 3763 { 3764 int blk; 3765 int phy_port; 3766 int port_core_index; 3767 soc_mem_t local_mem; 3768 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_SA_TAB_0m, 3769 CPRI_ENCAP_QUE_SA_TAB_1m, 3770 CPRI_ENCAP_QUE_SA_TAB_2m, 3771 CPRI_ENCAP_QUE_SA_TAB_3m }; 3772 3773 uint32 *rd_data_ptr; 3774 uint32 num_words; 3775 uint32 local_mac_addr[2]; 3776 SOC_INIT_FUNC_DEFS; 3777 3778 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3779 port_core_index = ((phy_port-1)%4); 3780 3781 local_mem = mem_select[port_core_index]; 3782 3783 num_words = soc_mem_entry_words(unit, local_mem); 3784 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3785 CPRIMOD_NULL_CHECK(rd_data_ptr); 3786 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3787 3788 /* 3789 * Read configuration 3790 */ 3791 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3792 _SOC_IF_ERR_EXIT 3793 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 3794 3795 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_SAf, local_mac_addr); 3796 COMPILER_64_SET(*mac_addr,local_mac_addr[1], local_mac_addr[0]); 3797 exit: 3798 sal_free(rd_data_ptr); 3799 SOC_FUNC_RETURN; 3800 } 3801 3802 int cprif_drv_encap_vlan_entry_set(int unit, int port, 3803 uint32 vlan_table_num, 3804 uint32 index, 3805 uint32 vlan_id) 3806 { 3807 int blk; 3808 int phy_port; 3809 int port_core_index; 3810 soc_mem_t local_mem; 3811 3812 soc_mem_t mem_select_vlan0[] = {CPRI_ENCAP_QUE_VLAN0_TAB_0m, 3813 CPRI_ENCAP_QUE_VLAN0_TAB_1m, 3814 CPRI_ENCAP_QUE_VLAN0_TAB_2m, 3815 CPRI_ENCAP_QUE_VLAN0_TAB_3m }; 3816 3817 3818 soc_mem_t mem_select_vlan1[] = {CPRI_ENCAP_QUE_VLAN1_TAB_0m, 3819 CPRI_ENCAP_QUE_VLAN1_TAB_1m, 3820 CPRI_ENCAP_QUE_VLAN1_TAB_2m, 3821 CPRI_ENCAP_QUE_VLAN1_TAB_3m }; 3822 uint32 *wr_data_ptr; 3823 uint32 num_words; 3824 uint32 field_buf; 3825 SOC_INIT_FUNC_DEFS; 3826 3827 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3828 port_core_index = ((phy_port-1)%4); 3829 3830 if (vlan_table_num == 0) { 3831 local_mem = mem_select_vlan0[port_core_index]; 3832 } else { 3833 local_mem = mem_select_vlan1[port_core_index]; 3834 } 3835 3836 num_words = soc_mem_entry_words(unit, local_mem); 3837 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3838 CPRIMOD_NULL_CHECK(wr_data_ptr); 3839 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 3840 3841 field_buf = vlan_id; 3842 if (vlan_table_num == 0) { 3843 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_VLAN0f, &field_buf); 3844 } else { 3845 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_VLAN1f, &field_buf); 3846 } 3847 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3848 _SOC_IF_ERR_EXIT 3849 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 3850 3851 exit: 3852 sal_free(wr_data_ptr); 3853 SOC_FUNC_RETURN; 3854 } 3855 3856 int cprif_drv_encap_vlan_entry_get(int unit, int port, 3857 uint32 vlan_table_num, 3858 uint32 index, 3859 uint32* vlan_id) 3860 3861 { 3862 int blk; 3863 int phy_port; 3864 int port_core_index; 3865 soc_mem_t local_mem; 3866 soc_mem_t mem_select_vlan0[] = {CPRI_ENCAP_QUE_VLAN0_TAB_0m, 3867 CPRI_ENCAP_QUE_VLAN0_TAB_1m, 3868 CPRI_ENCAP_QUE_VLAN0_TAB_2m, 3869 CPRI_ENCAP_QUE_VLAN0_TAB_3m }; 3870 3871 3872 soc_mem_t mem_select_vlan1[] = {CPRI_ENCAP_QUE_VLAN1_TAB_0m, 3873 CPRI_ENCAP_QUE_VLAN1_TAB_1m, 3874 CPRI_ENCAP_QUE_VLAN1_TAB_2m, 3875 CPRI_ENCAP_QUE_VLAN1_TAB_3m }; 3876 3877 3878 uint32 *rd_data_ptr; 3879 uint32 num_words; 3880 uint32 field_buf; 3881 SOC_INIT_FUNC_DEFS; 3882 3883 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3884 port_core_index = ((phy_port-1)%4); 3885 3886 if (vlan_table_num == 0) { 3887 local_mem = mem_select_vlan0[port_core_index]; 3888 } else { 3889 local_mem = mem_select_vlan1[port_core_index]; 3890 } 3891 3892 num_words = soc_mem_entry_words(unit, local_mem); 3893 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 3894 CPRIMOD_NULL_CHECK(rd_data_ptr); 3895 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 3896 3897 /* 3898 * Read configuration 3899 */ 3900 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 3901 _SOC_IF_ERR_EXIT 3902 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 3903 3904 if (vlan_table_num == 0) { 3905 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_VLAN0f, &field_buf); 3906 } else { 3907 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_VLAN1f, &field_buf); 3908 } 3909 3910 *vlan_id = field_buf; 3911 3912 3913 exit: 3914 sal_free(rd_data_ptr); 3915 SOC_FUNC_RETURN; 3916 } 3917 3918 3919 int cprif_drv_decap_vlan_ethtype_set(int unit, int port, 3920 uint8 ethtype_id, 3921 uint16 ethtype) 3922 3923 { 3924 uint64 reg_val; 3925 uint64 write_val; 3926 3927 COMPILER_64_SET(write_val, 0, (uint32) ethtype); 3928 SOC_IF_ERROR_RETURN(READ_CPRI_DECAP_CTRLr(unit, port, ®_val)); 3929 3930 switch (ethtype_id) { 3931 case CPRIF_DECAP_ROE_ETHTYPE: 3932 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 3933 DECAP_ROE_ETHERTYPEf, write_val); 3934 break; 3935 3936 case CPRIF_DECAP_FAST_ETH_ETHTYPE: 3937 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 3938 DECAP_FAST_ETH_ETHERTYPEf, write_val); 3939 break; 3940 3941 case CPRIF_DECAP_VLAN_TAGGED_ETHTYPE: 3942 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 3943 DECAP_VLAN_ETYPEf, write_val); 3944 3945 break; 3946 3947 case CPRIF_DECAP_VLAN_QINQ_ETHTYPE: 3948 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 3949 DECAP_QINQ_ETYPEf, write_val); 3950 break; 3951 3952 default: 3953 break; 3954 } 3955 3956 SOC_IF_ERROR_RETURN(WRITE_CPRI_DECAP_CTRLr(unit, port, reg_val)); 3957 return SOC_E_NONE; 3958 3959 } 3960 3961 int cprif_drv_decap_vlan_ethtype_get(int unit, int port, 3962 uint8 ethtype_id, 3963 uint16* ethtype) 3964 3965 { 3966 uint64 reg_val; 3967 uint64 read_val; 3968 3969 SOC_IF_ERROR_RETURN(READ_CPRI_DECAP_CTRLr(unit, port, ®_val)); 3970 switch (ethtype_id) { 3971 case CPRIF_DECAP_ROE_ETHTYPE: 3972 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, 3973 reg_val, DECAP_ROE_ETHERTYPEf); 3974 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3975 break; 3976 3977 case CPRIF_DECAP_FAST_ETH_ETHTYPE: 3978 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, 3979 reg_val, DECAP_FAST_ETH_ETHERTYPEf); 3980 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3981 break; 3982 3983 case CPRIF_DECAP_VLAN_TAGGED_ETHTYPE: 3984 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, 3985 reg_val, DECAP_VLAN_ETYPEf); 3986 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3987 break; 3988 3989 case CPRIF_DECAP_VLAN_QINQ_ETHTYPE: 3990 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, 3991 reg_val, DECAP_QINQ_ETYPEf); 3992 *ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 3993 break; 3994 3995 default: 3996 break; 3997 } 3998 return SOC_E_NONE; 3999 } 4000 4001 int cprif_drv_decap_pkt_type_config_set(int unit, int port, 4002 uint16 roe_ethtype, 4003 uint16 fast_eth_ethtype, 4004 uint16 vlan_ethtype, 4005 uint16 qinq_ethtype) 4006 { 4007 4008 uint64 reg_val; 4009 uint64 write_val; 4010 4011 SOC_IF_ERROR_RETURN(READ_CPRI_DECAP_CTRLr(unit, port, ®_val)); 4012 4013 COMPILER_64_SET(write_val, 0, (uint32) roe_ethtype); 4014 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 4015 DECAP_ROE_ETHERTYPEf, write_val); 4016 4017 COMPILER_64_SET(write_val, 0, (uint32) fast_eth_ethtype); 4018 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 4019 DECAP_FAST_ETH_ETHERTYPEf, write_val); 4020 4021 COMPILER_64_SET(write_val, 0, (uint32) vlan_ethtype); 4022 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 4023 DECAP_VLAN_ETYPEf, write_val); 4024 4025 COMPILER_64_SET(write_val, 0, (uint32) qinq_ethtype); 4026 soc_reg64_field_set(unit, CPRI_DECAP_CTRLr, ®_val, 4027 DECAP_QINQ_ETYPEf, write_val); 4028 4029 SOC_IF_ERROR_RETURN(WRITE_CPRI_DECAP_CTRLr(unit, port, write_val)); 4030 4031 return SOC_E_NONE; 4032 4033 } 4034 4035 4036 int cprif_drv_decap_pkt_type_config_get(int unit, int port, 4037 uint16* roe_ethtype, 4038 uint16* fast_eth_ethtype, 4039 uint16* vlan_ethtype, 4040 uint16* qinq_ethtype) 4041 4042 { 4043 uint64 reg_val; 4044 uint64 read_val; 4045 4046 SOC_IF_ERROR_RETURN(READ_CPRI_DECAP_CTRLr(unit, port, ®_val)); 4047 4048 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, reg_val, 4049 DECAP_ROE_ETHERTYPEf); 4050 *roe_ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 4051 4052 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, reg_val, 4053 DECAP_FAST_ETH_ETHERTYPEf); 4054 *fast_eth_ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 4055 4056 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, reg_val, 4057 DECAP_VLAN_ETYPEf ); 4058 *vlan_ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 4059 4060 read_val = soc_reg64_field_get(unit, CPRI_DECAP_CTRLr, reg_val, 4061 DECAP_QINQ_ETYPEf); 4062 *qinq_ethtype = COMPILER_64_LO(read_val) & 0xFFFF; 4063 return SOC_E_NONE; 4064 } 4065 4066 int cprif_drv_decap_flow_classification_entry_set(int unit, int port, 4067 uint8 subtype, 4068 uint32 queue_num, 4069 uint32 option, 4070 uint32 flow_type ) 4071 { 4072 int blk; 4073 int phy_port; 4074 int port_core_index; 4075 soc_mem_t local_mem; 4076 soc_mem_t mem_select[] = { CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_0m, 4077 CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_1m, 4078 CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_2m, 4079 CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_3m}; 4080 4081 uint32 *wr_data_ptr; 4082 uint32 num_words; 4083 uint32 field_buf; 4084 SOC_INIT_FUNC_DEFS; 4085 4086 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4087 port_core_index = ((phy_port-1)%4); 4088 4089 local_mem = mem_select[port_core_index]; 4090 4091 num_words = soc_mem_entry_words(unit, local_mem); 4092 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4093 CPRIMOD_NULL_CHECK(wr_data_ptr); 4094 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 4095 4096 field_buf = flow_type; 4097 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_DECAP_CFS_FLOW_TYPEf, &field_buf); 4098 4099 field_buf = option; 4100 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_DECAP_CFS_USE_FLOWIDf, &field_buf); 4101 4102 field_buf = queue_num; 4103 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_DECAP_CFS_QUEUE_NUMf, &field_buf); 4104 4105 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4106 _SOC_IF_ERR_EXIT 4107 (soc_mem_write(unit, local_mem, blk, subtype, wr_data_ptr)); 4108 4109 exit: 4110 sal_free(wr_data_ptr); 4111 SOC_FUNC_RETURN; 4112 } 4113 4114 int cprif_drv_decap_flow_classification_entry_get(int unit, int port, 4115 uint8 subtype, 4116 uint32* queue_num, 4117 uint32* option, 4118 uint32* flow_type ) 4119 4120 { 4121 int blk; 4122 int phy_port; 4123 int port_core_index; 4124 soc_mem_t local_mem; 4125 soc_mem_t mem_select[] = { CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_0m, 4126 CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_1m , 4127 CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_2m, 4128 CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_3m}; 4129 uint32 *rd_data_ptr; 4130 uint32 num_words; 4131 uint32 field_buf; 4132 SOC_INIT_FUNC_DEFS; 4133 4134 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4135 port_core_index = ((phy_port-1)%4); 4136 4137 local_mem = mem_select[port_core_index]; 4138 4139 num_words = soc_mem_entry_words(unit, local_mem); 4140 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4141 CPRIMOD_NULL_CHECK(rd_data_ptr); 4142 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 4143 4144 /* 4145 * Read configuration 4146 */ 4147 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4148 _SOC_IF_ERR_EXIT 4149 (soc_mem_read(unit, local_mem, blk, subtype, rd_data_ptr)); 4150 4151 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_DECAP_CFS_QUEUE_NUMf, &field_buf); 4152 *queue_num = field_buf; 4153 4154 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_DECAP_CFS_USE_FLOWIDf, &field_buf); 4155 *option = field_buf; 4156 4157 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_DECAP_CFS_FLOW_TYPEf, &field_buf); 4158 *flow_type = field_buf; 4159 4160 exit: 4161 sal_free(rd_data_ptr); 4162 SOC_FUNC_RETURN; 4163 } 4164 4165 int cprif_drv_decap_flow_to_queue_map_set(int unit, int port, 4166 uint32 flow_id, 4167 uint32 queue_num) 4168 { 4169 int blk; 4170 int phy_port; 4171 int port_core_index; 4172 soc_mem_t local_mem; 4173 soc_mem_t mem_select[] = { CPRI_DECAP_FLOWID_QUE_LOOKUP_0m, 4174 CPRI_DECAP_FLOWID_QUE_LOOKUP_1m, 4175 CPRI_DECAP_FLOWID_QUE_LOOKUP_2m, 4176 CPRI_DECAP_FLOWID_QUE_LOOKUP_3m }; 4177 4178 uint32 *wr_data_ptr; 4179 uint32 num_words; 4180 uint32 field_buf; 4181 SOC_INIT_FUNC_DEFS; 4182 4183 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4184 port_core_index = ((phy_port-1)%4); 4185 4186 local_mem = mem_select[port_core_index]; 4187 4188 num_words = soc_mem_entry_words(unit, local_mem); 4189 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4190 CPRIMOD_NULL_CHECK(wr_data_ptr); 4191 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 4192 4193 field_buf = queue_num; 4194 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_NUMf, &field_buf); 4195 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4196 _SOC_IF_ERR_EXIT 4197 (soc_mem_write(unit, local_mem, blk, flow_id, wr_data_ptr)); 4198 4199 exit: 4200 sal_free(wr_data_ptr); 4201 SOC_FUNC_RETURN; 4202 } 4203 4204 int cprif_drv_decap_flow_to_queue_map_get(int unit, int port, 4205 uint32 flow_id, 4206 uint32* queue_num) 4207 4208 { 4209 int blk; 4210 int phy_port; 4211 int port_core_index; 4212 soc_mem_t local_mem; 4213 soc_mem_t mem_select[] = { CPRI_DECAP_FLOWID_QUE_LOOKUP_0m, 4214 CPRI_DECAP_FLOWID_QUE_LOOKUP_1m, 4215 CPRI_DECAP_FLOWID_QUE_LOOKUP_2m, 4216 CPRI_DECAP_FLOWID_QUE_LOOKUP_3m }; 4217 4218 uint32 *rd_data_ptr; 4219 uint32 num_words; 4220 uint32 field_buf; 4221 SOC_INIT_FUNC_DEFS; 4222 4223 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4224 port_core_index = ((phy_port-1)%4); 4225 4226 local_mem = mem_select[port_core_index]; 4227 4228 num_words = soc_mem_entry_words(unit, local_mem); 4229 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4230 CPRIMOD_NULL_CHECK(rd_data_ptr); 4231 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 4232 4233 /* 4234 * Read configuration 4235 */ 4236 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4237 _SOC_IF_ERR_EXIT 4238 (soc_mem_read(unit, local_mem, blk, flow_id, rd_data_ptr)); 4239 4240 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_NUMf, &field_buf); 4241 *queue_num = field_buf; 4242 4243 exit: 4244 sal_free(rd_data_ptr); 4245 SOC_FUNC_RETURN; 4246 } 4247 4248 int cprif_drv_tx_framer_tgen_tick_set(int unit, int port, 4249 uint32 divider, 4250 uint32 bfrm_ticks, 4251 uint32 bfrm_ticks_bitmap, 4252 uint32 bitmap_size) 4253 { 4254 4255 4256 uint64 write_val; 4257 uint64 field_buf; 4258 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG1r(unit, port, &write_val)); 4259 4260 COMPILER_64_SET(field_buf,0,divider); 4261 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, &write_val, TX_TGEN_DIVIDERf, field_buf); 4262 COMPILER_64_SET(field_buf,0,bfrm_ticks_bitmap); 4263 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, &write_val, TX_TGEN_BFRM_TICKS_BITMAPf, field_buf); 4264 COMPILER_64_SET(field_buf,0,bitmap_size); 4265 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, &write_val, TX_TGEN_BFRM_TICKS_BITMAP_SIZEf, field_buf); 4266 COMPILER_64_SET(field_buf,0,bfrm_ticks); 4267 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, &write_val, TX_TGEN_BFRM_TICKSf, field_buf); 4268 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_TGEN_CFG1r(unit, port, write_val)); 4269 4270 return SOC_E_NONE; 4271 4272 } 4273 4274 int cprif_drv_tx_framer_tgen_tick_get(int unit, int port, 4275 uint32* divider, 4276 uint32* bfrm_ticks, 4277 uint32* bfrm_ticks_bitmap, 4278 uint32* bitmap_size) 4279 4280 { 4281 uint64 reg_val; 4282 uint64 read_val; 4283 4284 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG1r(unit, port, ®_val)); 4285 4286 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG1r, reg_val, 4287 TX_TGEN_DIVIDERf); 4288 *divider = COMPILER_64_LO(read_val); 4289 4290 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG1r, reg_val, 4291 TX_TGEN_BFRM_TICKS_BITMAPf); 4292 *bfrm_ticks = COMPILER_64_LO(read_val); 4293 4294 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG1r, reg_val, 4295 TX_TGEN_BFRM_TICKS_BITMAP_SIZEf); 4296 *bitmap_size = COMPILER_64_LO(read_val); 4297 4298 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG1r, reg_val, 4299 TX_TGEN_BFRM_TICKSf); 4300 *bfrm_ticks_bitmap = COMPILER_64_LO(read_val); 4301 4302 return SOC_E_NONE; 4303 } 4304 4305 int cprif_drv_tx_framer_tgen_enable(int unit, int port, 4306 uint8 enable) 4307 { 4308 uint64 reg_val; 4309 uint64 write_val; 4310 4311 COMPILER_64_SET(write_val, 0, (uint32) enable); 4312 4313 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG2r(unit, port, ®_val)); 4314 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG2r, ®_val, 4315 TX_TGEN_ENABLEf, write_val); 4316 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_TGEN_CFG2r(unit, port, reg_val)); 4317 4318 if(!enable) { 4319 /* 4320 * to disable TGEN, GLAS need to be reset. 4321 */ 4322 SOC_IF_ERROR_RETURN 4323 (cprif_drv_glas_reset_set(unit, port, 1)); 4324 4325 SOC_IF_ERROR_RETURN 4326 (cprif_drv_glas_reset_set(unit, port, 0)); 4327 4328 } 4329 4330 4331 return SOC_E_NONE; 4332 } 4333 4334 int cprif_drv_tx_framer_tgen_offset_set(int unit, int port, 4335 uint64 offset) 4336 { 4337 uint64 write_val; 4338 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG2r(unit, port, &write_val)); 4339 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG2r, &write_val, TX_TGEN_TS_OFFSETf, offset); 4340 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_TGEN_CFG2r(unit, port, write_val)); 4341 return SOC_E_NONE; 4342 } 4343 4344 int cprif_drv_tx_framer_tgen_offset_get(int unit, int port, 4345 uint64* offset) 4346 { 4347 uint64 reg_val; 4348 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG2r(unit, port, ®_val)); 4349 *offset = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG2r, reg_val, TX_TGEN_TS_OFFSETf); 4350 return SOC_E_NONE; 4351 } 4352 4353 int cprif_drv_tx_framer_tgen_next_bfn_config_set(int unit, int port, 4354 uint32 bfn) 4355 { 4356 uint64 reg_val; 4357 uint64 write_val; 4358 4359 COMPILER_64_SET(write_val, 0, bfn); 4360 4361 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG4r(unit, port, ®_val)); 4362 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG4r, ®_val, 4363 TX_TGEN_BFNf, write_val); 4364 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_TGEN_CFG4r(unit, port, reg_val)); 4365 4366 return SOC_E_NONE; 4367 } 4368 4369 int cprif_drv_tx_framer_tgen_next_bfn_config_get(int unit, int port, 4370 uint32* bfn) 4371 { 4372 uint64 reg_val; 4373 uint64 read_val; 4374 4375 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG4r(unit, port, ®_val)); 4376 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG4r, 4377 reg_val, TX_TGEN_BFNf); 4378 *bfn = COMPILER_64_LO(read_val) & 0xFFFF; 4379 4380 return SOC_E_NONE; 4381 } 4382 4383 int cprif_drv_tx_framer_tgen_next_hfn_config_set(int unit, int port, 4384 uint32 hfn) 4385 { 4386 uint64 reg_val; 4387 uint64 write_val; 4388 4389 COMPILER_64_SET(write_val, 0, hfn); 4390 4391 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG3r(unit, port, ®_val)); 4392 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG3r, ®_val, 4393 TX_TGEN_HFNf, write_val); 4394 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_TGEN_CFG3r(unit, port, reg_val)); 4395 4396 return SOC_E_NONE; 4397 } 4398 4399 int cprif_drv_tx_framer_tgen_next_hfn_config_get(int unit, int port, 4400 uint32* hfn) 4401 { 4402 uint64 reg_val; 4403 uint64 read_val; 4404 4405 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG3r(unit, port, ®_val)); 4406 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG3r, reg_val, 4407 TX_TGEN_HFNf); 4408 *hfn = COMPILER_64_LO(read_val) & 0xFF; 4409 4410 return SOC_E_NONE; 4411 } 4412 4413 int cprif_drv_tx_framer_next_bfn_get(int unit, int port, 4414 uint32* bfn) 4415 { 4416 uint64 reg_val; 4417 uint64 read_val; 4418 4419 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_STATUSr(unit, port, ®_val)); 4420 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_STATUSr, 4421 reg_val, TX_TGEN_BF_CNT_LIVEf); 4422 *bfn = COMPILER_64_LO(read_val); 4423 4424 return SOC_E_NONE; 4425 } 4426 4427 int cprif_drv_tx_framer_next_hfn_get(int unit, int port, 4428 uint32* hfn) 4429 { 4430 uint64 reg_val; 4431 uint64 read_val; 4432 4433 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_STATUSr(unit, port, ®_val)); 4434 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_STATUSr, reg_val, 4435 TX_TGEN_HF_CNT_LIVEf); 4436 *hfn = COMPILER_64_LO(read_val); 4437 4438 return SOC_E_NONE; 4439 } 4440 4441 int cprif_drv_tx_framer_tgen_select_counter_set(int unit, int port, 4442 uint8 hfn_bfn) 4443 { 4444 uint64 reg_val; 4445 uint64 write_val; 4446 4447 COMPILER_64_SET(write_val, 0, (uint32) hfn_bfn); 4448 4449 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG1r(unit, port, ®_val)); 4450 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, ®_val, 4451 TX_TGEN_BFN_SELf, write_val); 4452 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_TGEN_CFG1r(unit, port, reg_val)); 4453 4454 return SOC_E_NONE; 4455 } 4456 4457 int cprif_drv_tx_framer_tgen_select_counter_get(int unit, int port, 4458 uint8* hfn_bfn) 4459 { 4460 uint64 reg_val; 4461 uint64 read_val; 4462 4463 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG1r(unit, port, ®_val)); 4464 read_val = soc_reg64_field_get(unit, CPRI_TXFRM_TGEN_CFG1r, reg_val, 4465 TX_TGEN_BFN_SELf); 4466 *hfn_bfn = COMPILER_64_LO(read_val) & 0xFF; 4467 4468 return SOC_E_NONE; 4469 } 4470 4471 /* 4472 * 4473 * RSVD4 Related Drivers. 4474 */ 4475 4476 int cprif_drv_rsvd4_header_compare_entry_set(int unit, int port, 4477 int index, 4478 cprimod_header_compare_entry_t* entry) 4479 { 4480 int blk; 4481 int phy_port; 4482 int port_core_index; 4483 soc_mem_t local_mem; 4484 soc_mem_t mem_select[] = { CPRI_HDR_CMP_TAB_CFG_0m, 4485 CPRI_HDR_CMP_TAB_CFG_1m, 4486 CPRI_HDR_CMP_TAB_CFG_2m, 4487 CPRI_HDR_CMP_TAB_CFG_3m}; 4488 4489 uint32 *wr_data_ptr; 4490 uint32 num_words; 4491 uint32 field_buf; 4492 SOC_INIT_FUNC_DEFS; 4493 4494 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4495 port_core_index = ((phy_port-1)%4); 4496 4497 local_mem = mem_select[port_core_index]; 4498 4499 num_words = soc_mem_entry_words(unit, local_mem); 4500 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4501 CPRIMOD_NULL_CHECK(wr_data_ptr); 4502 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 4503 4504 field_buf = entry->valid; 4505 soc_mem_field_set(unit, local_mem, wr_data_ptr, VALIDf, &field_buf); 4506 4507 field_buf = entry->match_data; 4508 soc_mem_field_set(unit, local_mem, wr_data_ptr, MATCH_DATAf, &field_buf); 4509 4510 field_buf = entry->mask; 4511 soc_mem_field_set(unit, local_mem, wr_data_ptr, MASKf, &field_buf); 4512 4513 field_buf = entry->flow_id; 4514 soc_mem_field_set(unit, local_mem, wr_data_ptr, FLOW_IDf, &field_buf); 4515 4516 field_buf = entry->flow_type; 4517 soc_mem_field_set(unit, local_mem, wr_data_ptr, CTRL_FLOWf, &field_buf); 4518 4519 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4520 _SOC_IF_ERR_EXIT 4521 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 4522 4523 exit: 4524 sal_free(wr_data_ptr); 4525 SOC_FUNC_RETURN; 4526 4527 } 4528 4529 int cprif_drv_rsvd4_header_compare_entry_get(int unit, int port, 4530 int index, 4531 cprimod_header_compare_entry_t* entry) 4532 { 4533 int blk; 4534 int phy_port; 4535 int port_core_index; 4536 soc_mem_t local_mem; 4537 soc_mem_t mem_select[] = { CPRI_HDR_CMP_TAB_CFG_0m, 4538 CPRI_HDR_CMP_TAB_CFG_1m, 4539 CPRI_HDR_CMP_TAB_CFG_2m, 4540 CPRI_HDR_CMP_TAB_CFG_3m}; 4541 4542 uint32 *rd_data_ptr; 4543 uint32 num_words; 4544 uint32 field_buf; 4545 SOC_INIT_FUNC_DEFS; 4546 4547 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4548 port_core_index = ((phy_port-1)%4); 4549 4550 local_mem = mem_select[port_core_index]; 4551 4552 num_words = soc_mem_entry_words(unit, local_mem); 4553 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4554 CPRIMOD_NULL_CHECK(rd_data_ptr); 4555 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 4556 4557 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4558 _SOC_IF_ERR_EXIT 4559 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 4560 4561 soc_mem_field_get(unit, local_mem, rd_data_ptr, VALIDf, &field_buf); 4562 entry->valid = field_buf; 4563 4564 soc_mem_field_get(unit, local_mem, rd_data_ptr, MATCH_DATAf, &field_buf); 4565 entry->match_data = field_buf;; 4566 4567 soc_mem_field_get(unit, local_mem, rd_data_ptr, MASKf, &field_buf); 4568 entry->mask = field_buf;; 4569 4570 soc_mem_field_get(unit, local_mem, rd_data_ptr, FLOW_IDf, &field_buf); 4571 entry->flow_id = field_buf;; 4572 4573 soc_mem_field_get(unit, local_mem, rd_data_ptr, CTRL_FLOWf, &field_buf); 4574 entry->flow_type = field_buf;; 4575 4576 exit: 4577 sal_free(rd_data_ptr); 4578 SOC_FUNC_RETURN; 4579 } 4580 4581 4582 int cprif_drv_rsvd4_modulo_rule_entry_set(int unit, int port, 4583 uint8 index, 4584 uint8 control_rule, 4585 cprimod_modulo_rule_entry_t* entry) 4586 { 4587 int blk; 4588 int phy_port; 4589 int port_core_index; 4590 soc_mem_t local_mem; 4591 soc_mem_t data_mem_select[] = { BRCM_RESERVED_CPM_23m, 4592 BRCM_RESERVED_CPM_24m, 4593 BRCM_RESERVED_CPM_25m, 4594 BRCM_RESERVED_CPM_26m 4595 }; 4596 soc_mem_t ctrl_mem_select[] = { BRCM_RESERVED_CPM_27m, 4597 BRCM_RESERVED_CPM_28m, 4598 BRCM_RESERVED_CPM_29m, 4599 BRCM_RESERVED_CPM_30m 4600 }; 4601 4602 uint32 *wr_data_ptr; 4603 uint32 num_words; 4604 uint32 field_buf; 4605 SOC_INIT_FUNC_DEFS; 4606 4607 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4608 port_core_index = ((phy_port-1)%4); 4609 4610 if (control_rule) { 4611 local_mem = ctrl_mem_select[port_core_index]; 4612 } else { 4613 local_mem = data_mem_select[port_core_index]; 4614 } 4615 4616 num_words = soc_mem_entry_words(unit, local_mem); 4617 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4618 CPRIMOD_NULL_CHECK(wr_data_ptr); 4619 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 4620 4621 if (control_rule) { 4622 field_buf = entry->active; 4623 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_27_5f, &field_buf); 4624 4625 field_buf = entry->modulo_value; 4626 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_27_4f, &field_buf); 4627 4628 field_buf = entry->modulo_index; 4629 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_27_3f, &field_buf); 4630 4631 field_buf = entry->dbm_enable; 4632 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_27_2f, &field_buf); 4633 4634 field_buf = entry->flow_dbm_id; 4635 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_27_1f, &field_buf); 4636 4637 field_buf = entry->flow_type; 4638 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_27_0f, &field_buf); 4639 } else { 4640 field_buf = entry->active; 4641 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_23_5f, &field_buf); 4642 4643 field_buf = entry->modulo_value; 4644 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_23_4f, &field_buf); 4645 4646 field_buf = entry->modulo_index; 4647 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_23_3f, &field_buf); 4648 4649 field_buf = entry->dbm_enable; 4650 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_23_2f, &field_buf); 4651 4652 field_buf = entry->flow_dbm_id; 4653 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_23_1f, &field_buf); 4654 4655 field_buf = entry->flow_type; 4656 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_23_0f, &field_buf); 4657 } 4658 4659 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4660 _SOC_IF_ERR_EXIT 4661 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 4662 4663 exit: 4664 sal_free(wr_data_ptr); 4665 SOC_FUNC_RETURN; 4666 4667 } 4668 4669 4670 int cprif_drv_rsvd4_modulo_rule_entry_get(int unit, int port, 4671 uint8 index, 4672 uint8 control_rule, 4673 cprimod_modulo_rule_entry_t* entry) 4674 { 4675 int blk; 4676 int phy_port; 4677 int port_core_index; 4678 soc_mem_t local_mem; 4679 soc_mem_t data_mem_select[] = { BRCM_RESERVED_CPM_23m, 4680 BRCM_RESERVED_CPM_24m, 4681 BRCM_RESERVED_CPM_25m, 4682 BRCM_RESERVED_CPM_26m 4683 }; 4684 soc_mem_t ctrl_mem_select[] = { BRCM_RESERVED_CPM_27m, 4685 BRCM_RESERVED_CPM_28m, 4686 BRCM_RESERVED_CPM_29m, 4687 BRCM_RESERVED_CPM_30m 4688 }; 4689 4690 uint32 *rd_data_ptr; 4691 uint32 num_words; 4692 uint32 field_buf; 4693 SOC_INIT_FUNC_DEFS; 4694 4695 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4696 port_core_index = ((phy_port-1)%4); 4697 4698 if (control_rule) { 4699 local_mem = ctrl_mem_select[port_core_index]; 4700 } else { 4701 local_mem = data_mem_select[port_core_index]; 4702 } 4703 4704 num_words = soc_mem_entry_words(unit, local_mem); 4705 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4706 CPRIMOD_NULL_CHECK(rd_data_ptr); 4707 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 4708 4709 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4710 _SOC_IF_ERR_EXIT 4711 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 4712 4713 if (control_rule) { 4714 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_27_5f, &field_buf); 4715 entry->active = field_buf; 4716 4717 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_27_4f, &field_buf); 4718 entry->modulo_value = field_buf;; 4719 4720 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_27_3f, &field_buf); 4721 entry->modulo_index = field_buf;; 4722 4723 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_27_2f, &field_buf); 4724 entry->dbm_enable = field_buf;; 4725 4726 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_27_1f, &field_buf); 4727 entry->flow_dbm_id = field_buf;; 4728 4729 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_27_0f, &field_buf); 4730 entry->flow_type = field_buf;; 4731 4732 } else { 4733 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_23_5f, &field_buf); 4734 entry->active = field_buf; 4735 4736 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_23_4f, &field_buf); 4737 entry->modulo_value = field_buf;; 4738 4739 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_23_3f, &field_buf); 4740 entry->modulo_index = field_buf;; 4741 4742 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_23_2f, &field_buf); 4743 entry->dbm_enable = field_buf;; 4744 4745 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_23_1f, &field_buf); 4746 entry->flow_dbm_id = field_buf;; 4747 4748 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_23_0f, &field_buf); 4749 entry->flow_type = field_buf;; 4750 } 4751 4752 exit: 4753 sal_free(rd_data_ptr); 4754 SOC_FUNC_RETURN; 4755 4756 } 4757 4758 4759 int cprif_drv_rsvd4_dual_bitmap_rule_entry_set(int unit, int port, 4760 uint8 index, 4761 cprimod_dbm_rule_entry_t* entry) 4762 { 4763 int blk; 4764 int phy_port; 4765 int port_core_index; 4766 soc_mem_t local_mem0; 4767 soc_mem_t local_mem1; 4768 soc_mem_t dbm_rule0_mem_select[] = { BRCM_RESERVED_CPM_31m, 4769 BRCM_RESERVED_CPM_32m, 4770 BRCM_RESERVED_CPM_33m, 4771 BRCM_RESERVED_CPM_34m 4772 }; 4773 soc_mem_t dbm_rule1_mem_select[] = { BRCM_RESERVED_CPM_35m, 4774 BRCM_RESERVED_CPM_36m, 4775 BRCM_RESERVED_CPM_37m, 4776 BRCM_RESERVED_CPM_38m 4777 }; 4778 4779 uint32 *wr_data_ptr0 = NULL; 4780 uint32 *wr_data_ptr1 = NULL; 4781 uint32 num_words; 4782 uint32 field_buf; 4783 SOC_INIT_FUNC_DEFS; 4784 4785 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4786 port_core_index = ((phy_port-1)%4); 4787 4788 4789 if (index >= CPRIF_DBM_RULE_PROFILE_TABLE_SIZE) { 4790 LOG_CLI(("Index %d is out of range > than %d", 4791 index, 4792 CPRIF_DBM_RULE_PROFILE_TABLE_SIZE)); 4793 return SOC_E_PARAM; 4794 } 4795 4796 local_mem0 = dbm_rule0_mem_select[port_core_index]; 4797 local_mem1 = dbm_rule1_mem_select[port_core_index]; 4798 4799 /* 4800 * Preparing DBM Rule 0. 4801 */ 4802 4803 num_words = soc_mem_entry_words(unit, local_mem0); 4804 wr_data_ptr0 = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4805 if (wr_data_ptr0 == NULL) { 4806 _SOC_EXIT_WITH_ERR(SOC_E_RESOURCE, ("Unable to allocate memory\n")); 4807 } 4808 sal_memset(wr_data_ptr0, 0, sizeof(uint32) * num_words); 4809 4810 field_buf = entry->bm1_mult; 4811 soc_mem_field_set(unit, local_mem0, wr_data_ptr0, BRCM_RESERVED_CPM_31_2f, &field_buf); 4812 4813 soc_mem_field_set(unit, local_mem0, wr_data_ptr0, BRCM_RESERVED_CPM_31_1f, entry->bm1); 4814 4815 field_buf = entry->bm1_size; 4816 soc_mem_field_set(unit, local_mem0, wr_data_ptr0, BRCM_RESERVED_CPM_31_0f, &field_buf); 4817 4818 4819 /* 4820 * Preparing DBM Rule 1. 4821 */ 4822 4823 num_words = soc_mem_entry_words(unit, local_mem1); 4824 wr_data_ptr1 = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4825 if (wr_data_ptr1 == NULL) { 4826 _SOC_EXIT_WITH_ERR(SOC_E_RESOURCE, ("Unable to allocate memory\n")); 4827 } 4828 sal_memset(wr_data_ptr1, 0, sizeof(uint32) * num_words); 4829 4830 soc_mem_field_set(unit, local_mem1, wr_data_ptr1, BRCM_RESERVED_CPM_35_4f, entry->bm2); 4831 4832 field_buf = entry->bm2_size; 4833 soc_mem_field_set(unit, local_mem1, wr_data_ptr1, BRCM_RESERVED_CPM_35_3f, &field_buf); 4834 4835 field_buf = entry->num_slots; 4836 soc_mem_field_set(unit, local_mem1, wr_data_ptr1, BRCM_RESERVED_CPM_35_2f, &field_buf); 4837 4838 field_buf = entry->pos_grp_index; 4839 soc_mem_field_set(unit, local_mem1, wr_data_ptr1, BRCM_RESERVED_CPM_35_1f, &field_buf); 4840 4841 field_buf = entry->pos_grp_size; 4842 soc_mem_field_set(unit, local_mem1, wr_data_ptr1, BRCM_RESERVED_CPM_35_0f, &field_buf); 4843 4844 4845 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4846 _SOC_IF_ERR_EXIT 4847 (soc_mem_write(unit, local_mem0, blk, index, wr_data_ptr0)); 4848 _SOC_IF_ERR_EXIT 4849 (soc_mem_write(unit, local_mem1, blk, index, wr_data_ptr1)); 4850 4851 exit: 4852 if (wr_data_ptr0) { 4853 sal_free(wr_data_ptr0); 4854 } 4855 if (wr_data_ptr1) { 4856 sal_free(wr_data_ptr1); 4857 } 4858 4859 SOC_FUNC_RETURN; 4860 4861 } 4862 4863 int cprif_drv_rsvd4_dual_bitmap_rule_entry_get(int unit, int port, 4864 uint8 index, 4865 cprimod_dbm_rule_entry_t* entry) 4866 { 4867 int blk; 4868 int phy_port; 4869 int port_core_index; 4870 soc_mem_t local_mem0; 4871 soc_mem_t local_mem1; 4872 soc_mem_t dbm_rule0_mem_select[] = { BRCM_RESERVED_CPM_31m, 4873 BRCM_RESERVED_CPM_32m, 4874 BRCM_RESERVED_CPM_33m, 4875 BRCM_RESERVED_CPM_34m 4876 }; 4877 soc_mem_t dbm_rule1_mem_select[] = { BRCM_RESERVED_CPM_35m, 4878 BRCM_RESERVED_CPM_36m, 4879 BRCM_RESERVED_CPM_37m, 4880 BRCM_RESERVED_CPM_38m 4881 }; 4882 4883 uint32 *rd_data_ptr0 = 0; 4884 uint32 *rd_data_ptr1 = 0; 4885 uint32 num_words; 4886 uint32 field_buf; 4887 SOC_INIT_FUNC_DEFS; 4888 4889 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4890 port_core_index = ((phy_port-1)%4); 4891 4892 4893 if (index >= CPRIF_DBM_RULE_PROFILE_TABLE_SIZE) { 4894 LOG_CLI(("Index %d is out of range > than %d", 4895 index, 4896 CPRIF_DBM_RULE_PROFILE_TABLE_SIZE)); 4897 return SOC_E_PARAM; 4898 } 4899 4900 local_mem0 = dbm_rule0_mem_select[port_core_index]; 4901 local_mem1 = dbm_rule1_mem_select[port_core_index]; 4902 4903 /* 4904 * Preparing DBM Rule 0. 4905 */ 4906 4907 num_words = soc_mem_entry_words(unit, local_mem0); 4908 rd_data_ptr0 = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4909 CPRIMOD_NULL_CHECK(rd_data_ptr0); 4910 sal_memset(rd_data_ptr0, 0, sizeof(uint32) * num_words); 4911 4912 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 4913 _SOC_IF_ERR_EXIT 4914 (soc_mem_read(unit, local_mem0, blk, index, rd_data_ptr0)); 4915 4916 soc_mem_field_get(unit, local_mem0, rd_data_ptr0, BRCM_RESERVED_CPM_31_2f, &field_buf); 4917 entry->bm1_mult = field_buf; 4918 4919 soc_mem_field_get(unit, local_mem0, rd_data_ptr0, BRCM_RESERVED_CPM_31_1f, entry->bm1); 4920 4921 soc_mem_field_get(unit, local_mem0, rd_data_ptr0, BRCM_RESERVED_CPM_31_0f, &field_buf); 4922 entry->bm1_size = field_buf;; 4923 4924 4925 /* 4926 * Preparing DBM Rule 1. 4927 */ 4928 4929 num_words = soc_mem_entry_words(unit, local_mem1); 4930 rd_data_ptr1 = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4931 CPRIMOD_NULL_CHECK(rd_data_ptr1); 4932 sal_memset(rd_data_ptr1, 0, sizeof(uint32) * num_words); 4933 4934 _SOC_IF_ERR_EXIT 4935 (soc_mem_read(unit, local_mem1, blk, index, rd_data_ptr1)); 4936 4937 soc_mem_field_get(unit, local_mem1, rd_data_ptr1, BRCM_RESERVED_CPM_35_4f, entry->bm2); 4938 4939 soc_mem_field_get(unit, local_mem1, rd_data_ptr1, BRCM_RESERVED_CPM_35_3f, &field_buf); 4940 entry->bm2_size = field_buf;; 4941 4942 soc_mem_field_get(unit, local_mem1, rd_data_ptr1, BRCM_RESERVED_CPM_35_2f, &field_buf); 4943 entry->num_slots = field_buf;; 4944 4945 soc_mem_field_get(unit, local_mem1, rd_data_ptr1, BRCM_RESERVED_CPM_35_1f, &field_buf); 4946 entry->pos_grp_index = field_buf;; 4947 4948 soc_mem_field_get(unit, local_mem1, rd_data_ptr1, BRCM_RESERVED_CPM_35_0f, &field_buf); 4949 entry->pos_grp_size = field_buf;; 4950 4951 4952 4953 exit: 4954 sal_free(rd_data_ptr0); 4955 sal_free(rd_data_ptr1); 4956 4957 SOC_FUNC_RETURN; 4958 4959 } 4960 4961 int cprif_drv_rsvd4_secondary_dual_bitmap_rule_entry_set(int unit, int port, 4962 uint8 index, 4963 cprimod_secondary_dbm_rule_entry_t* entry) 4964 { 4965 int blk; 4966 int phy_port; 4967 int port_core_index; 4968 soc_mem_t local_mem; 4969 soc_mem_t mem_select[] = { BRCM_RESERVED_CPM_18m, 4970 BRCM_RESERVED_CPM_19m, 4971 BRCM_RESERVED_CPM_20m, 4972 BRCM_RESERVED_CPM_21m 4973 }; 4974 4975 4976 uint32 *wr_data_ptr; 4977 uint32 num_words; 4978 uint32 field_buf; 4979 SOC_INIT_FUNC_DEFS; 4980 4981 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 4982 port_core_index = ((phy_port-1)%4); 4983 4984 4985 if (index >= CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE) { 4986 LOG_CLI(("Index %d is out of range > than %d", 4987 index, 4988 CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE)); 4989 return SOC_E_PARAM; 4990 } 4991 4992 local_mem = mem_select[port_core_index]; 4993 4994 4995 num_words = soc_mem_entry_words(unit, local_mem); 4996 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 4997 CPRIMOD_NULL_CHECK(wr_data_ptr); 4998 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 4999 5000 field_buf = entry->bm1_mult; 5001 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_18_5f, &field_buf); 5002 5003 field_buf = entry->bm1; 5004 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_18_4f, &field_buf); 5005 5006 field_buf = entry->bm1_size; 5007 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_18_3f, &field_buf); 5008 5009 field_buf = entry->bm2; 5010 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_18_2f, &field_buf); 5011 5012 field_buf = entry->bm2_size; 5013 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_18_1f, &field_buf); 5014 5015 field_buf = entry->num_slots; 5016 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_18_0f, &field_buf); 5017 5018 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5019 _SOC_IF_ERR_EXIT 5020 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 5021 5022 exit: 5023 sal_free(wr_data_ptr); 5024 5025 SOC_FUNC_RETURN; 5026 5027 } 5028 5029 int cprif_drv_rsvd4_secondary_dual_bitmap_rule_entry_get(int unit, int port, 5030 uint8 index, 5031 cprimod_secondary_dbm_rule_entry_t* entry) 5032 { 5033 int blk; 5034 int phy_port; 5035 int port_core_index; 5036 soc_mem_t local_mem; 5037 soc_mem_t mem_select[] = { BRCM_RESERVED_CPM_18m, 5038 BRCM_RESERVED_CPM_19m, 5039 BRCM_RESERVED_CPM_20m, 5040 BRCM_RESERVED_CPM_21m 5041 }; 5042 5043 5044 uint32 *rd_data_ptr; 5045 uint32 num_words; 5046 uint32 field_buf; 5047 SOC_INIT_FUNC_DEFS; 5048 5049 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 5050 port_core_index = ((phy_port-1)%4); 5051 5052 if (index >= CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE) { 5053 LOG_CLI(("Index %d is out of range > than %d", 5054 index, 5055 CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE)); 5056 return SOC_E_PARAM; 5057 } 5058 5059 local_mem = mem_select[port_core_index]; 5060 5061 num_words = soc_mem_entry_words(unit, local_mem); 5062 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 5063 CPRIMOD_NULL_CHECK(rd_data_ptr); 5064 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 5065 5066 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5067 _SOC_IF_ERR_EXIT 5068 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 5069 5070 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_18_5f, &field_buf); 5071 entry->bm1_mult = field_buf ; 5072 5073 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_18_4f, &field_buf); 5074 entry->bm1 = field_buf ; 5075 5076 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_18_3f, &field_buf); 5077 entry->bm1_size = field_buf ; 5078 5079 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_18_2f, &field_buf); 5080 entry->bm2 = field_buf ; 5081 5082 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_18_1f, &field_buf); 5083 entry->bm2_size = field_buf ; 5084 5085 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_18_0f, &field_buf); 5086 entry->num_slots = field_buf ; 5087 5088 exit: 5089 sal_free(rd_data_ptr); 5090 5091 SOC_FUNC_RETURN; 5092 5093 } 5094 5095 int cprif_drv_rsvd4_dbm_position_entry_set(int unit, int port, 5096 uint8 index, 5097 cprimod_dbm_pos_table_entry_t* entry) 5098 { 5099 int blk; 5100 int phy_port; 5101 int port_core_index; 5102 soc_mem_t local_mem; 5103 soc_mem_t mem_select[] = { BRCM_RESERVED_CPM_39m, 5104 BRCM_RESERVED_CPM_40m, 5105 BRCM_RESERVED_CPM_41m, 5106 BRCM_RESERVED_CPM_42m 5107 }; 5108 5109 5110 uint32 *wr_data_ptr; 5111 uint32 num_words; 5112 uint32 field_buf; 5113 SOC_INIT_FUNC_DEFS; 5114 5115 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 5116 port_core_index = ((phy_port-1)%4); 5117 5118 5119 if (index >= CPRIF_DBM_POSITION_TABLE_SIZE) { 5120 LOG_CLI(("Index %d is out of range > than %d", 5121 index, 5122 CPRIF_DBM_POSITION_TABLE_SIZE)); 5123 return SOC_E_PARAM; 5124 } 5125 5126 local_mem = mem_select[port_core_index]; 5127 5128 5129 num_words = soc_mem_entry_words(unit, local_mem); 5130 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 5131 CPRIMOD_NULL_CHECK(wr_data_ptr); 5132 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 5133 5134 field_buf = entry->valid; 5135 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_39_3f, &field_buf); 5136 5137 field_buf = entry->flow_type; 5138 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_39_1f, &field_buf); 5139 5140 field_buf = entry->flow_id; 5141 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_39_2f, &field_buf); 5142 5143 field_buf = entry->index; 5144 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_39_0f, &field_buf); 5145 5146 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5147 _SOC_IF_ERR_EXIT 5148 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 5149 5150 exit: 5151 sal_free(wr_data_ptr); 5152 5153 SOC_FUNC_RETURN; 5154 } 5155 5156 int cprif_drv_rsvd4_dbm_position_entry_get(int unit, int port, 5157 uint8 index, 5158 cprimod_dbm_pos_table_entry_t* entry) 5159 { 5160 int blk; 5161 int phy_port; 5162 int port_core_index; 5163 soc_mem_t local_mem; 5164 soc_mem_t mem_select[] = { BRCM_RESERVED_CPM_39m, 5165 BRCM_RESERVED_CPM_40m, 5166 BRCM_RESERVED_CPM_41m, 5167 BRCM_RESERVED_CPM_42m 5168 }; 5169 5170 5171 uint32 *rd_data_ptr; 5172 uint32 num_words; 5173 uint32 field_buf; 5174 SOC_INIT_FUNC_DEFS; 5175 5176 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 5177 port_core_index = ((phy_port-1)%4); 5178 5179 5180 if (index >= CPRIF_DBM_POSITION_TABLE_SIZE) { 5181 LOG_CLI(("Index %d is out of range > than %d", 5182 index, 5183 CPRIF_DBM_POSITION_TABLE_SIZE)); 5184 return SOC_E_PARAM; 5185 } 5186 5187 local_mem = mem_select[port_core_index]; 5188 5189 num_words = soc_mem_entry_words(unit, local_mem); 5190 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 5191 CPRIMOD_NULL_CHECK(rd_data_ptr); 5192 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 5193 5194 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5195 _SOC_IF_ERR_EXIT 5196 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 5197 5198 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_39_3f, &field_buf); 5199 entry->valid = field_buf; 5200 5201 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_39_1f, &field_buf); 5202 entry->flow_type = field_buf; 5203 5204 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_39_2f, &field_buf); 5205 entry->flow_id = field_buf; 5206 5207 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_39_0f, &field_buf); 5208 entry->index = field_buf; 5209 5210 5211 exit: 5212 sal_free(rd_data_ptr); 5213 5214 SOC_FUNC_RETURN; 5215 } 5216 5217 /* 5218 * Below are the tasks useful to clear status during Dynamic Add/Del axcs 5219 */ 5220 5221 int cprif_drv_encap_queue_sts_clear(int unit, int port, int queue_num) 5222 { 5223 int blk; 5224 int phy_port; 5225 int port_core_index; 5226 soc_mem_t local_mem; 5227 soc_mem_t mem_select[] = { CPRI_ENCAP_QUEUE_STS_0m, 5228 CPRI_ENCAP_QUEUE_STS_1m, 5229 CPRI_ENCAP_QUEUE_STS_2m, 5230 CPRI_ENCAP_QUEUE_STS_3m 5231 }; 5232 uint32 *mem_data_ptr; 5233 uint32 num_words; 5234 SOC_INIT_FUNC_DEFS; 5235 5236 CPRIF_DRV_MEM_PREP; 5237 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5238 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, queue_num, 5239 mem_data_ptr)); 5240 exit: 5241 sal_free(mem_data_ptr); 5242 SOC_FUNC_RETURN; 5243 } 5244 5245 5246 int cprif_drv_encap_ordering_info_sts_clear(int unit, int port, int queue_num) 5247 { 5248 int blk; 5249 int phy_port; 5250 int port_core_index; 5251 soc_mem_t local_mem; 5252 soc_mem_t mem_select[] = { CPRI_ENCAP_ORDERING_INFO_STS_0m, 5253 CPRI_ENCAP_ORDERING_INFO_STS_1m, 5254 CPRI_ENCAP_ORDERING_INFO_STS_2m, 5255 CPRI_ENCAP_ORDERING_INFO_STS_3m 5256 }; 5257 uint32 *mem_data_ptr; 5258 uint32 num_words; 5259 SOC_INIT_FUNC_DEFS; 5260 5261 CPRIF_DRV_MEM_PREP; 5262 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5263 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, queue_num, 5264 mem_data_ptr)); 5265 exit: 5266 sal_free(mem_data_ptr); 5267 SOC_FUNC_RETURN; 5268 } 5269 5270 5271 int cprif_drv_encap_eth_hdr_clear(int unit, int port, int queue_num) 5272 { 5273 int blk; 5274 int phy_port; 5275 int port_core_index; 5276 soc_mem_t local_mem; 5277 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_ETH_HDR_0m, 5278 CPRI_ENCAP_QUE_ETH_HDR_1m, 5279 CPRI_ENCAP_QUE_ETH_HDR_2m, 5280 CPRI_ENCAP_QUE_ETH_HDR_3m 5281 }; 5282 uint32 *mem_data_ptr; 5283 uint32 num_words; 5284 SOC_INIT_FUNC_DEFS; 5285 5286 CPRIF_DRV_MEM_PREP; 5287 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5288 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, queue_num, 5289 mem_data_ptr)); 5290 exit: 5291 sal_free(mem_data_ptr); 5292 SOC_FUNC_RETURN; 5293 5294 } 5295 5296 int cprif_drv_encap_data_tab_clear(int unit, int port, int queue_num) 5297 { 5298 int blk; 5299 int phy_port; 5300 int port_core_index; 5301 soc_mem_t local_mem; 5302 soc_mem_t mem_select[] = { CPRI_ENCAP_DATA_0m, 5303 CPRI_ENCAP_DATA_1m, 5304 CPRI_ENCAP_DATA_2m, 5305 CPRI_ENCAP_DATA_3m 5306 }; 5307 uint32 *mem_data_ptr; 5308 uint32 num_words; 5309 SOC_INIT_FUNC_DEFS; 5310 5311 CPRIF_DRV_MEM_PREP; 5312 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5313 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, queue_num, 5314 mem_data_ptr)); 5315 exit: 5316 sal_free(mem_data_ptr); 5317 SOC_FUNC_RETURN; 5318 } 5319 5320 5321 int cprif_drv_container_parser_mapp_state_tab_clear(int unit, int port, int axc_id) 5322 { 5323 int blk; 5324 int phy_port; 5325 int port_core_index; 5326 soc_mem_t local_mem; 5327 soc_mem_t mem_select[] = { CPRI_CPRSR_MAP_STATE_TAB_STS_0m, 5328 CPRI_CPRSR_MAP_STATE_TAB_STS_1m, 5329 CPRI_CPRSR_MAP_STATE_TAB_STS_2m, 5330 CPRI_CPRSR_MAP_STATE_TAB_STS_3m 5331 }; 5332 uint32 *mem_data_ptr; 5333 uint32 num_words; 5334 SOC_INIT_FUNC_DEFS; 5335 5336 CPRIF_DRV_MEM_PREP; 5337 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5338 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, axc_id, 5339 mem_data_ptr)); 5340 exit: 5341 sal_free(mem_data_ptr); 5342 SOC_FUNC_RETURN; 5343 } 5344 5345 int cprif_drv_iq_pak_buff_state_tab_clear(int unit, int port, int axc_id) 5346 { 5347 int blk; 5348 int phy_port; 5349 int port_core_index; 5350 soc_mem_t local_mem; 5351 soc_mem_t mem_select[] = { CPRI_IQ_PK_BUFF_AXC_STATE_STS_0m, 5352 CPRI_IQ_PK_BUFF_AXC_STATE_STS_1m, 5353 CPRI_IQ_PK_BUFF_AXC_STATE_STS_2m, 5354 CPRI_IQ_PK_BUFF_AXC_STATE_STS_3m 5355 }; 5356 uint32 *mem_data_ptr; 5357 uint32 num_words; 5358 SOC_INIT_FUNC_DEFS; 5359 5360 CPRIF_DRV_MEM_PREP; 5361 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5362 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, axc_id, 5363 mem_data_ptr)); 5364 exit: 5365 sal_free(mem_data_ptr); 5366 SOC_FUNC_RETURN; 5367 } 5368 5369 int cprif_drv_iq_pak_buff_payld_tab_clear(int unit, int port, int axc_id) 5370 { 5371 int blk; 5372 int phy_port; 5373 int port_core_index; 5374 soc_mem_t local_mem; 5375 soc_mem_t mem_select[] = { CPRI_IQ_PK_BUFF_AXC_PLD_STS_0m, 5376 CPRI_IQ_PK_BUFF_AXC_PLD_STS_1m, 5377 CPRI_IQ_PK_BUFF_AXC_PLD_STS_2m, 5378 CPRI_IQ_PK_BUFF_AXC_PLD_STS_3m 5379 }; 5380 uint32 *mem_data_ptr; 5381 uint32 num_words; 5382 SOC_INIT_FUNC_DEFS; 5383 5384 CPRIF_DRV_MEM_PREP; 5385 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5386 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, axc_id, 5387 mem_data_ptr)); 5388 exit: 5389 sal_free(mem_data_ptr); 5390 SOC_FUNC_RETURN; 5391 } 5392 5393 int cprif_drv_iq_unpsk_buff_state_tbl_clear(int unit, int port, int axc_id) 5394 { 5395 int blk; 5396 int phy_port; 5397 int port_core_index; 5398 soc_mem_t local_mem; 5399 soc_mem_t mem_select[] = { CPRI_IQU_STATE_STS_0m, 5400 CPRI_IQU_STATE_STS_1m, 5401 CPRI_IQU_STATE_STS_2m, 5402 CPRI_IQU_STATE_STS_3m 5403 }; 5404 uint32 *mem_data_ptr; 5405 uint32 num_words; 5406 SOC_INIT_FUNC_DEFS; 5407 5408 CPRIF_DRV_MEM_PREP; 5409 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5410 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, axc_id, 5411 mem_data_ptr)); 5412 exit: 5413 sal_free(mem_data_ptr); 5414 SOC_FUNC_RETURN; 5415 } 5416 5417 int cprif_drv_cont_assembly_map_state_tbl_clear(int unit, int port, int axc_id) 5418 { 5419 int blk; 5420 int phy_port; 5421 int port_core_index; 5422 soc_mem_t local_mem; 5423 soc_mem_t mem_select[] = { CPRI_CA_MAP_STATE_TAB_STS_0m, 5424 CPRI_CA_MAP_STATE_TAB_STS_1m, 5425 CPRI_CA_MAP_STATE_TAB_STS_2m, 5426 CPRI_CA_MAP_STATE_TAB_STS_3m 5427 }; 5428 uint32 *mem_data_ptr; 5429 uint32 num_words; 5430 SOC_INIT_FUNC_DEFS; 5431 5432 CPRIF_DRV_MEM_PREP; 5433 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5434 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, axc_id, 5435 mem_data_ptr)); 5436 exit: 5437 sal_free(mem_data_ptr); 5438 SOC_FUNC_RETURN; 5439 } 5440 5441 int cprif_drv_decap_queue_state_tbl_clear(int unit, int port, int queue_num) 5442 { 5443 int blk; 5444 int phy_port; 5445 int port_core_index; 5446 soc_mem_t local_mem; 5447 soc_mem_t mem_select[] = { CPRI_DECAP_QUEUE_STS_0m, 5448 CPRI_DECAP_QUEUE_STS_1m, 5449 CPRI_DECAP_QUEUE_STS_2m, 5450 CPRI_DECAP_QUEUE_STS_3m 5451 }; 5452 uint32 *mem_data_ptr; 5453 uint32 num_words; 5454 SOC_INIT_FUNC_DEFS; 5455 5456 CPRIF_DRV_MEM_PREP; 5457 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5458 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, queue_num, 5459 mem_data_ptr)); 5460 exit: 5461 sal_free(mem_data_ptr); 5462 SOC_FUNC_RETURN; 5463 } 5464 5465 int cprif_drv_decap_queue_data_tbl_clear(int unit, int port, int queue_num) 5466 { 5467 int blk; 5468 int phy_port; 5469 int port_core_index; 5470 soc_mem_t local_mem; 5471 soc_mem_t mem_select[] = { CPRI_DECAP_DATA_0m, 5472 CPRI_DECAP_DATA_1m, 5473 CPRI_DECAP_DATA_2m, 5474 CPRI_DECAP_DATA_3m 5475 }; 5476 uint32 *mem_data_ptr; 5477 uint32 num_words; 5478 SOC_INIT_FUNC_DEFS; 5479 5480 CPRIF_DRV_MEM_PREP; 5481 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 5482 _SOC_IF_ERR_EXIT(soc_mem_write(unit, local_mem, blk, queue_num, 5483 mem_data_ptr)); 5484 exit: 5485 sal_free(mem_data_ptr); 5486 SOC_FUNC_RETURN; 5487 } 5488 5489 /* 5490 * Program rxframer ctrl register with length of ctrl-word (based on speed) 5491 * NB: this information is also in basic_frame_cfg.ctrl_w_length, 5492 * but we duplicate it here so that users don't need to deal 5493 * with that structure. 5494 */ 5495 int cprif_drv_set_rxframer_cw_num_bytes(int unit, int port, cprimod_port_speed_t speed) 5496 { 5497 uint64 data; 5498 uint64 write_val; 5499 uint32 cw_len; 5500 SOC_INIT_FUNC_DEFS; 5501 5502 SOC_IF_ERROR_RETURN(READ_CPRI_RXFRM_CPRSR_CTRLr(unit, port, &data)); 5503 5504 cw_len = 0; 5505 switch (speed) { 5506 case cprimodSpd614p4: 5507 cw_len = 1; /* fl=16 */ 5508 break; 5509 case cprimodSpd1228p8: 5510 cw_len = 2; /* fl=32 */ 5511 break; 5512 case cprimodSpd2457p6: 5513 cw_len = 4; /* fl=64 */ 5514 break; 5515 case cprimodSpd3072p0: 5516 cw_len = 5; /* fl=80 */ 5517 break; 5518 case cprimodSpd4915p2: 5519 cw_len = 8; /* fl=128 */ 5520 break; 5521 case cprimodSpd6144p0: 5522 cw_len = 10; /* fl=160 */ 5523 break; 5524 case cprimodSpd8110p08: 5525 cw_len = 16; /* fl=256 */ 5526 break; 5527 case cprimodSpd9830p4: 5528 cw_len = 16; /* fl=256 */ 5529 break; 5530 case cprimodSpd10137p6: 5531 cw_len = 16; /* fl=320 */ 5532 break; 5533 case cprimodSpd12165p12: 5534 cw_len = 16; /* fl=768 */ 5535 break; 5536 case cprimodSpd24330p24: 5537 cw_len = 16; /* fl=768 */ 5538 break; 5539 default: 5540 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed is not supported for cpri")); 5541 break; 5542 } 5543 5544 COMPILER_64_SET(write_val, 0, cw_len); 5545 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, &data, RXFRM_CW_NUM_BYTESf, write_val); 5546 SOC_IF_ERROR_RETURN(WRITE_CPRI_RXFRM_CPRSR_CTRLr(unit, port, data)); 5547 5548 exit: 5549 SOC_FUNC_RETURN; 5550 } 5551 5552 int cprif_drv_rxpcs_interface_width_get(int unit, int port, 5553 int *is_10bit) 5554 { 5555 uint64 data; 5556 uint64 read_val; 5557 5558 5559 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 5560 5561 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 5562 RXPCS_10B_MODEf); 5563 5564 *is_10bit = COMPILER_64_IS_ZERO(read_val)? 0:1; 5565 5566 return SOC_E_NONE; 5567 5568 } 5569 5570 5571 /* 5572 * THIS is only for B0. And only for Tunnel 5573 */ 5574 int cprif_drv_rxpcs_tunnel_mode_set(int unit, int port, int enable, uint32 timestamp_interval ) 5575 { 5576 uint64 data; 5577 uint64 write_val; 5578 cprif_pm_version_t pm_version; 5579 5580 SOC_IF_ERROR_RETURN 5581 (cprif_pm_version_get(unit, port, &pm_version)); 5582 5583 if (CPRIF_CLPORT_IS_A0(pm_version)) { 5584 LOG_CLI(("TUNNEL Mode is not supported in A0.\n")); 5585 return SOC_E_UNAVAIL; 5586 } 5587 5588 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 5589 5590 if (enable) { 5591 COMPILER_64_SET(write_val, 0, TRUE); 5592 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_TUNNEL_MODEf, write_val); 5593 5594 /* force it to 8B/10B mode. */ 5595 COMPILER_64_SET(write_val, 0, 0); 5596 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_MODEf, write_val); 5597 5598 /* set timestamp interval for tunnel mode, in bits. */ 5599 COMPILER_64_SET(write_val, 0, timestamp_interval & 0xFF); 5600 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_64B66B_VALID_SH_CNTf, write_val); 5601 5602 COMPILER_64_SET(write_val, 0, (timestamp_interval & 0xFF00)>> 8 ); 5603 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_64B66B_INVALID_SH_CNTf, write_val); 5604 } else { /* disable */ 5605 COMPILER_64_SET(write_val, 0, FALSE); 5606 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_TUNNEL_MODEf, write_val); 5607 5608 5609 COMPILER_64_SET(write_val, 0, 0); 5610 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_MODEf, write_val); 5611 5612 /* Set those to default value. */ 5613 COMPILER_64_SET(write_val, 0, 0x40); 5614 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_64B66B_VALID_SH_CNTf, write_val); 5615 5616 COMPILER_64_SET(write_val, 0, 0x10 ); 5617 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_64B66B_INVALID_SH_CNTf, write_val); 5618 5619 } 5620 5621 SOC_IF_ERROR_RETURN 5622 (WRITE_CPRI_RXPCS_CTRLr(unit, port, data)); 5623 5624 return SOC_E_NONE; 5625 } 5626 5627 /* 5628 * THIS is only for both A0 and B0. 5629 */ 5630 int cprif_drv_rxpcs_tunnel_mode_get(int unit, int port, int* enable, uint32* timestamp_interval ) 5631 { 5632 uint64 data; 5633 uint64 read_val; 5634 cprif_pm_version_t pm_version; 5635 5636 SOC_IF_ERROR_RETURN 5637 (cprif_pm_version_get(unit, port, &pm_version)); 5638 5639 /* 5640 * If A0, just return as not enable, as it does not support 5641 * tunnel mode. And not an error condition unlike set. 5642 */ 5643 if (CPRIF_CLPORT_IS_A0(pm_version)) { 5644 *enable = FALSE; 5645 return SOC_E_NONE; 5646 } 5647 5648 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 5649 5650 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 5651 RXPCS_TUNNEL_MODEf); 5652 if (COMPILER_64_IS_ZERO(read_val)) { 5653 *enable = 0; 5654 } else { 5655 *enable = 1; 5656 } 5657 5658 if (*enable) { 5659 5660 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 5661 RXPCS_64B66B_VALID_SH_CNTf); 5662 5663 *timestamp_interval = COMPILER_64_LO(read_val) & 0xFF; 5664 5665 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 5666 RXPCS_64B66B_INVALID_SH_CNTf); 5667 5668 *timestamp_interval |= ((COMPILER_64_LO(read_val) & 0xFF) << 8); 5669 } 5670 return SOC_E_NONE; 5671 } 5672 5673 /* 5674 * THIS is only for B0. And only for Tunnel and RSVD4 5675 */ 5676 int cprif_drv_txpcs_agnostic_mode_set(int unit, int port, int enable, cprimod_agnostic_mode_type_t mode, uint32 timestamp_interval) 5677 { 5678 uint64 data; 5679 uint64 write_val; 5680 cprif_pm_version_t pm_version; 5681 5682 SOC_IF_ERROR_RETURN 5683 (cprif_pm_version_get(unit, port, &pm_version)); 5684 5685 if (CPRIF_CLPORT_IS_A0(pm_version)) { 5686 LOG_CLI(("This feature is not supported in A0.\n")); 5687 return SOC_E_UNAVAIL; 5688 } 5689 5690 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 5691 5692 if (enable) { 5693 switch (mode) { 5694 case cprimod_agnostic_mode_rsvd4: 5695 5696 COMPILER_64_SET(write_val, 0, FALSE); 5697 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, TX_PCS_TUNNEL_MODEf, write_val); 5698 5699 5700 COMPILER_64_SET(write_val, 0, TRUE); 5701 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, BRCM_RESERVED_CPM_11_8f, write_val); /* AGNOSTIC_MODE */ 5702 5703 break; 5704 5705 case cprimod_agnostic_mode_tunnel: 5706 5707 COMPILER_64_SET(write_val, 0, TRUE); 5708 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, TX_PCS_TUNNEL_MODEf, write_val); 5709 5710 COMPILER_64_SET(write_val, 0, FALSE); 5711 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, BRCM_RESERVED_CPM_11_8f, write_val); 5712 5713 /* set timestamp interval for tunnel mode, in bits. */ 5714 COMPILER_64_SET(write_val, 0, timestamp_interval); 5715 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, TX_PCS_TUNNEL_TS_BIT_CNTf, write_val); 5716 5717 /* force it to 8B/10B mode. */ 5718 COMPILER_64_SET(write_val, 0, 0); 5719 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, TX_PCS_MODEf, write_val); 5720 5721 break; 5722 5723 default: 5724 break; 5725 } /* switch */ 5726 } else { /* disable */ 5727 COMPILER_64_SET(write_val, 0, FALSE); 5728 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, TX_PCS_TUNNEL_MODEf, write_val); 5729 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, BRCM_RESERVED_CPM_11_8f, write_val); 5730 5731 5732 COMPILER_64_SET(write_val, 0, 0); 5733 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, TX_PCS_MODEf, write_val); 5734 } 5735 5736 SOC_IF_ERROR_RETURN 5737 (WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 5738 5739 return SOC_E_NONE; 5740 } 5741 5742 /* 5743 * THIS is only for B0. And Tunnel and RSVD4 5744 */ 5745 int cprif_drv_txpcs_agnostic_mode_get(int unit, int port, int* enable, cprimod_agnostic_mode_type_t* mode, uint32* timestamp_interval) 5746 { 5747 uint64 data; 5748 uint32 is_tunnel_mode=0; 5749 uint32 is_rsvd4_mode=0; 5750 cprif_pm_version_t pm_version; 5751 5752 SOC_IF_ERROR_RETURN 5753 (cprif_pm_version_get(unit, port, &pm_version)); 5754 5755 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 5756 5757 is_rsvd4_mode = soc_reg64_field32_get(unit, CPRI_TXPCS_CTRLr, data, 5758 BRCM_RESERVED_CPM_11_8f); 5759 5760 if (CPRIF_CLPORT_IS_B0(pm_version)) { 5761 is_tunnel_mode = soc_reg64_field32_get(unit, CPRI_TXPCS_CTRLr, data, 5762 TX_PCS_TUNNEL_MODEf); 5763 } 5764 /* check for tunnel mode enabled. */ 5765 if (is_tunnel_mode) { 5766 *enable = TRUE; 5767 *mode = cprimod_agnostic_mode_tunnel; 5768 5769 *timestamp_interval = soc_reg64_field32_get(unit, CPRI_TXPCS_CTRLr, data, 5770 TX_PCS_TUNNEL_TS_BIT_CNTf); 5771 } else if (is_rsvd4_mode){ 5772 *enable = TRUE; 5773 *mode = cprimod_agnostic_mode_rsvd4; 5774 } else { 5775 *enable = FALSE; 5776 } 5777 5778 return SOC_E_NONE; 5779 } 5780 5781 int cprif_drv_cpri_rxpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 5782 cprimod_port_speed_t speed) 5783 { 5784 int osr; 5785 uint64 data; 5786 uint64 write_val; 5787 uint32 is10b; 5788 uint32 pcs_wd_len; 5789 cprimod_cpri_pcs_mode_t pcs_mode; 5790 SOC_INIT_FUNC_DEFS; 5791 5792 /* making RSVD4 0 for reporting port type */ 5793 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 5794 soc_reg64_field32_set(unit, BRCM_RESERVED_CPM_307r, &data, BRCM_RESERVED_CPM_307_0f, 0); 5795 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_307r(unit, port, data)); 5796 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 5797 pcs_wd_len = 0; 5798 switch (speed) { 5799 case cprimodSpd614p4: 5800 pcs_wd_len = 8; 5801 pcs_mode = cprimodCpriPcsMode8b10b; 5802 is10b = 1; 5803 osr = 13; 5804 break; 5805 case cprimodSpd1228p8: 5806 pcs_wd_len = 16; 5807 pcs_mode = cprimodCpriPcsMode8b10b; 5808 is10b = 1; 5809 osr = 9; 5810 break; 5811 case cprimodSpd2457p6: 5812 pcs_wd_len = 32; 5813 pcs_mode = cprimodCpriPcsMode8b10b; 5814 is10b = 1; 5815 osr = 5; 5816 break; 5817 case cprimodSpd3072p0: 5818 pcs_wd_len = 40; 5819 pcs_mode = cprimodCpriPcsMode8b10b; 5820 is10b = 1; 5821 osr = 5; 5822 break; 5823 case cprimodSpd4915p2: 5824 pcs_wd_len = 64; 5825 pcs_mode = cprimodCpriPcsMode8b10b; 5826 is10b = 0; 5827 osr = 2; 5828 break; 5829 case cprimodSpd6144p0: 5830 pcs_wd_len = 80; 5831 pcs_mode = cprimodCpriPcsMode8b10b; 5832 is10b = 0; 5833 osr = 2; 5834 break; 5835 5836 /* Removed this as that speed is not supported. 5837 Leave the code for reference. 5838 case cprimodSpd8110p08: 5839 pcs_wd_len = 80; 5840 pcs_mode = cprimodCpriPcsMode64b66b; 5841 is10b = 0; 5842 osr = 1; 5843 break; 5844 */ 5845 case cprimodSpd9830p4: 5846 pcs_wd_len = 128; 5847 pcs_mode = cprimodCpriPcsMode8b10b; 5848 is10b = 0; 5849 osr = 1; 5850 break; 5851 case cprimodSpd10137p6: 5852 pcs_wd_len = 160; 5853 pcs_mode = cprimodCpriPcsMode64b66b; 5854 is10b = 0; 5855 osr = 1; 5856 break; 5857 case cprimodSpd12165p12: 5858 pcs_wd_len = 192; 5859 pcs_mode = cprimodCpriPcsMode64b66b; 5860 is10b = 0; 5861 osr = 1; 5862 break; 5863 case cprimodSpd24330p24: 5864 pcs_wd_len = 384; 5865 pcs_mode = cprimodCpriPcsMode64b66b; 5866 is10b = 0; 5867 osr = 0; 5868 break; 5869 default: 5870 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed is not supported for cpri")); 5871 break; 5872 } 5873 5874 COMPILER_64_SET(write_val, 0, (uint32) pcs_mode); 5875 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_MODEf, 5876 write_val); 5877 5878 COMPILER_64_SET(write_val, 0, pcs_wd_len); 5879 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_WORD_LENf, 5880 write_val); 5881 5882 COMPILER_64_SET(write_val, 0, is10b); 5883 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_10B_MODEf, 5884 write_val); 5885 5886 SOC_IF_ERROR_RETURN(WRITE_CPRI_RXPCS_CTRLr(unit, port, data)); 5887 SOC_IF_ERROR_RETURN(READ_CPRI_PMD_RX_CTRLr(unit, port, &data)); 5888 COMPILER_64_SET(write_val, 0, osr); 5889 soc_reg64_field_set(unit, CPRI_PMD_RX_CTRLr, &data, PMD_RX_OSR_MODEf, write_val); 5890 SOC_IF_ERROR_RETURN(WRITE_CPRI_PMD_RX_CTRLr(unit, port, data)); 5891 falcon2_monterey_frc_rx_osr(&phy->access, osr); 5892 5893 SOC_IF_ERROR_RETURN(cprif_drv_set_rxframer_cw_num_bytes(unit, port, speed)); 5894 5895 exit: 5896 SOC_FUNC_RETURN; 5897 } 5898 5899 int cprif_drv_cpri_rxpcs_speed_get(int unit, int port, 5900 cprimod_port_speed_t *speed) 5901 { 5902 uint64 data; 5903 uint64 read_val; 5904 uint32 pcs_wd_len; 5905 SOC_INIT_FUNC_DEFS; 5906 5907 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 5908 5909 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 5910 RXPCS_WORD_LENf); 5911 pcs_wd_len = COMPILER_64_LO(read_val); 5912 5913 switch (pcs_wd_len) { 5914 5915 case 8: 5916 *speed = cprimodSpd614p4; 5917 break; 5918 5919 case 16: 5920 *speed = cprimodSpd1228p8; 5921 break; 5922 5923 case 32: 5924 *speed = cprimodSpd2457p6; 5925 break; 5926 5927 case 40: 5928 *speed = cprimodSpd3072p0; 5929 break; 5930 5931 case 64: 5932 *speed = cprimodSpd4915p2; 5933 break; 5934 5935 case 80: 5936 *speed = cprimodSpd6144p0; 5937 break; 5938 5939 case 128: 5940 *speed = cprimodSpd9830p4; 5941 break; 5942 5943 case 160: 5944 *speed = cprimodSpd10137p6; 5945 break; 5946 5947 case 192: 5948 *speed = cprimodSpd12165p12; 5949 break; 5950 5951 case 384: 5952 *speed = cprimodSpd24330p24; 5953 break; 5954 5955 default: 5956 *speed = cprimodSpdCount; 5957 break; 5958 5959 } 5960 SOC_FUNC_RETURN; 5961 } 5962 5963 int cprif_drv_cpri_txpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 5964 cprimod_port_speed_t speed) 5965 { 5966 int osr; 5967 uint64 data; 5968 uint64 write_val; 5969 uint32 data32; 5970 cprimod_cpri_pcs_mode_t pcs_mode; 5971 int bfrm_ticks, ticks_bitmap_size, ticks_bitmap; 5972 int pcs_word_len, ctrl_byte_len; 5973 struct falcon2_monterey_uc_lane_config_st serdes_firmware_config; 5974 SOC_INIT_FUNC_DEFS; 5975 5976 pcs_word_len = 8; 5977 pcs_mode = cprimodCpriPcsMode8b10b; 5978 ctrl_byte_len=1; 5979 ticks_bitmap=0; 5980 ticks_bitmap_size=0; 5981 bfrm_ticks=64; 5982 sal_memset(&serdes_firmware_config, 0x0, sizeof(serdes_firmware_config)); 5983 falcon2_monterey_get_uc_lane_cfg(&phy->access, &serdes_firmware_config); 5984 serdes_firmware_config.field.dfe_on = 1; 5985 5986 switch (speed) { 5987 case cprimodSpd614p4: 5988 pcs_word_len = 8; 5989 pcs_mode = cprimodCpriPcsMode8b10b; 5990 ctrl_byte_len=1; 5991 ticks_bitmap=0; 5992 ticks_bitmap_size=0; 5993 bfrm_ticks=64; 5994 osr = 13; 5995 serdes_firmware_config.field.dfe_on = 0; 5996 break; 5997 case cprimodSpd1228p8: 5998 pcs_word_len = 16; 5999 pcs_mode = cprimodCpriPcsMode8b10b; 6000 ctrl_byte_len=2; 6001 ticks_bitmap=0; 6002 ticks_bitmap_size=0; 6003 bfrm_ticks=64; 6004 osr = 9; 6005 serdes_firmware_config.field.dfe_on = 0; 6006 break; 6007 case cprimodSpd2457p6: 6008 pcs_word_len = 32; 6009 pcs_mode = cprimodCpriPcsMode8b10b; 6010 ctrl_byte_len=4; 6011 ticks_bitmap=0; 6012 ticks_bitmap_size=0; 6013 bfrm_ticks=64; 6014 osr = 5; 6015 serdes_firmware_config.field.dfe_on = 0; 6016 break; 6017 case cprimodSpd3072p0: 6018 pcs_word_len = 40; 6019 pcs_mode = cprimodCpriPcsMode8b10b; 6020 ctrl_byte_len=5; 6021 ticks_bitmap=0; 6022 ticks_bitmap_size=0; 6023 bfrm_ticks=80; 6024 osr = 5; 6025 serdes_firmware_config.field.dfe_on = 0; 6026 break; 6027 case cprimodSpd4915p2: 6028 pcs_word_len = 64; 6029 pcs_mode = cprimodCpriPcsMode8b10b; 6030 ctrl_byte_len=8; 6031 ticks_bitmap=0; 6032 ticks_bitmap_size=0; 6033 bfrm_ticks=32; 6034 osr = 2; 6035 serdes_firmware_config.field.dfe_on = 0; 6036 break; 6037 case cprimodSpd6144p0: 6038 pcs_word_len = 80; 6039 pcs_mode = cprimodCpriPcsMode8b10b; 6040 ctrl_byte_len=10; 6041 ticks_bitmap=0; 6042 ticks_bitmap_size=0; 6043 bfrm_ticks=40; 6044 osr = 2; 6045 serdes_firmware_config.field.dfe_on = 0; 6046 break; 6047 /* remove this speed as it is not supported. 6048 Leaving the code for future reference. 6049 case cprimodSpd8110p08: 6050 pcs_word_len = 80; 6051 pcs_mode = cprimodCpriPcsMode64b66b; 6052 ctrl_byte_len=16; 6053 ticks_bitmap=0; 6054 ticks_bitmap_size=0; 6055 bfrm_ticks=64; 6056 osr = 1; 6057 serdes_firmware_config.field.dfe_on = 0; 6058 break; 6059 */ 6060 case cprimodSpd9830p4: 6061 pcs_word_len = 128; 6062 pcs_mode = cprimodCpriPcsMode8b10b; 6063 ctrl_byte_len=16; 6064 ticks_bitmap=0; 6065 ticks_bitmap_size=0; 6066 bfrm_ticks=64; 6067 osr = 1; 6068 serdes_firmware_config.field.dfe_on = 0; 6069 break; 6070 case cprimodSpd10137p6: 6071 pcs_word_len = 160; 6072 pcs_mode = cprimodCpriPcsMode64b66b; 6073 ctrl_byte_len=16; 6074 ticks_bitmap=0; 6075 ticks_bitmap_size=0; 6076 bfrm_ticks=66; 6077 osr = 1; 6078 break; 6079 case cprimodSpd12165p12: 6080 pcs_word_len = 192; 6081 pcs_mode = cprimodCpriPcsMode64b66b; 6082 ctrl_byte_len=16; 6083 ticks_bitmap=0xfff0; 6084 ticks_bitmap_size=4; 6085 bfrm_ticks=79; 6086 osr = 1; 6087 break; 6088 case cprimodSpd24330p24: 6089 pcs_word_len = 384; 6090 pcs_mode = cprimodCpriPcsMode64b66b; 6091 ctrl_byte_len=16; 6092 ticks_bitmap=0xfff8; 6093 ticks_bitmap_size=4; 6094 bfrm_ticks=158; 6095 osr = 0; 6096 break; 6097 default: 6098 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed is not supported for cpri")); 6099 break; 6100 } 6101 6102 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6103 6104 COMPILER_64_SET(write_val, 0, (uint32) pcs_mode); 6105 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, TX_PCS_MODEf, 6106 write_val); 6107 6108 COMPILER_64_SET(write_val, 0, (uint32) pcs_word_len); 6109 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, 6110 TX_PCS_WORD_LEN_8B10Bf, write_val); 6111 6112 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 6113 6114 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_GENERALr(unit, port, 6115 &data32)); 6116 soc_reg_field_set(unit, CPRI_TXFRM_CWA_GENERALr, &data32, TX_CWA_TCWf, 6117 ctrl_byte_len); 6118 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_CWA_GENERALr(unit, port, 6119 data32)); 6120 /* setting up tgen */ 6121 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_TGEN_CFG1r(unit, port, &data)); 6122 COMPILER_64_SET(write_val, 0, (uint32) ticks_bitmap); 6123 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, &data, 6124 TX_TGEN_BFRM_TICKS_BITMAPf, write_val); 6125 COMPILER_64_SET(write_val, 0, (uint32) ticks_bitmap_size); 6126 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, &data, 6127 TX_TGEN_BFRM_TICKS_BITMAP_SIZEf, write_val); 6128 COMPILER_64_SET(write_val, 0, (uint32) bfrm_ticks); 6129 soc_reg64_field_set(unit, CPRI_TXFRM_TGEN_CFG1r, &data, 6130 TX_TGEN_BFRM_TICKSf, write_val); 6131 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_TGEN_CFG1r(unit, port, data)); 6132 SOC_IF_ERROR_RETURN(READ_CPRI_PMD_TX_CTRLr(unit, port, &data)); 6133 COMPILER_64_SET(write_val, 0, osr); 6134 soc_reg64_field_set(unit, CPRI_PMD_TX_CTRLr, &data, PMD_TX_OSR_MODEf, write_val); 6135 SOC_IF_ERROR_RETURN(WRITE_CPRI_PMD_TX_CTRLr(unit, port, data)); 6136 falcon2_monterey_frc_tx_osr(&phy->access, osr); 6137 falcon2_monterey_set_uc_lane_cfg(&phy->access, serdes_firmware_config); 6138 exit: 6139 SOC_FUNC_RETURN; 6140 } 6141 6142 int cprif_drv_cpri_txpcs_speed_get(int unit, int port, 6143 cprimod_port_speed_t *speed) 6144 { 6145 uint64 data; 6146 uint64 read_val; 6147 uint32 pcs_word_len; 6148 SOC_INIT_FUNC_DEFS; 6149 6150 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6151 6152 read_val = soc_reg64_field_get(unit, CPRI_TXPCS_CTRLr, data, 6153 TX_PCS_WORD_LEN_8B10Bf); 6154 pcs_word_len = COMPILER_64_LO(read_val); 6155 6156 switch (pcs_word_len) { 6157 6158 case 8: 6159 *speed = cprimodSpd614p4; 6160 break; 6161 6162 case 16: 6163 *speed = cprimodSpd1228p8; 6164 break; 6165 case 32: 6166 *speed = cprimodSpd2457p6; 6167 break; 6168 6169 case 40: 6170 *speed = cprimodSpd3072p0; 6171 break; 6172 6173 case 64: 6174 *speed = cprimodSpd4915p2; 6175 break; 6176 6177 case 80: 6178 *speed = cprimodSpd6144p0; 6179 break; 6180 6181 case 128: 6182 *speed = cprimodSpd9830p4; 6183 break; 6184 6185 case 160: 6186 *speed = cprimodSpd10137p6; 6187 break; 6188 6189 case 192: 6190 *speed = cprimodSpd12165p12; 6191 break; 6192 6193 case 384: 6194 *speed = cprimodSpd24330p24; 6195 break; 6196 6197 default: 6198 *speed = cprimodSpdCount; 6199 break; 6200 } 6201 SOC_FUNC_RETURN; 6202 } 6203 6204 int cprif_drv_rsvd4_rxpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 6205 cprimod_port_rsvd4_speed_mult_t speed) 6206 { 6207 uint64 data; 6208 uint64 write_val; 6209 uint32 data32; 6210 uint32 speedi, speedv; 6211 uint32 speedi_h, speedi_l; 6212 uint64 speedi_64; 6213 int osr; 6214 uint32 is10b; 6215 SOC_INIT_FUNC_DEFS; 6216 6217 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 6218 if (speed == cprimodRsvd4SpdMult4X) { 6219 speedi = 4; 6220 speedv = 2; 6221 is10b = 1; 6222 osr = 5; 6223 } else if (speed == cprimodRsvd4SpdMult8X) { 6224 speedi = 8; 6225 speedv = 3; 6226 is10b = 0; 6227 osr = 2; 6228 } else { 6229 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed is not supported for rsvd4")); 6230 } 6231 6232 SOC_IF_ERROR_RETURN(READ_CPRI_PMD_RX_CTRLr(unit, port, &data)); 6233 COMPILER_64_SET(write_val, 0, osr); 6234 soc_reg64_field_set(unit, CPRI_PMD_RX_CTRLr, &data, PMD_RX_OSR_MODEf, write_val); 6235 SOC_IF_ERROR_RETURN(WRITE_CPRI_PMD_RX_CTRLr(unit, port, data)); 6236 falcon2_monterey_frc_rx_osr(&phy->access, osr); 6237 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 6238 COMPILER_64_SET(write_val, 0, is10b); 6239 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, RXPCS_10B_MODEf, 6240 write_val); 6241 COMPILER_64_SET(write_val, 0, (uint32) cprimodCpriPcsMode8b10b); 6242 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6243 RXPCS_MODEf, write_val); 6244 6245 COMPILER_64_SET(write_val, (uint32) 0, (uint32) 0); 6246 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6247 RXPCS_WORD_LENf, write_val); 6248 SOC_IF_ERROR_RETURN(WRITE_CPRI_RXPCS_CTRLr(unit, port, data)); 6249 6250 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, 6251 &data)); 6252 COMPILER_64_SET(write_val, (uint32) 0, (uint32) 1); 6253 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6254 RXPCS_BIT_ENDIAN_FLIPf, write_val); 6255 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6256 BRCM_RESERVED_CPM_307_6f, write_val); 6257 6258 COMPILER_64_SET(write_val, 0, (uint32) speedv); 6259 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6260 BRCM_RESERVED_CPM_307_2f, write_val); 6261 6262 COMPILER_64_SET(write_val, 0, 1); 6263 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6264 BRCM_RESERVED_CPM_307_0f, write_val); 6265 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_307r(unit, port, 6266 data)); 6267 6268 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_308r(unit, port, 6269 &data)); 6270 COMPILER_64_SET(write_val, (uint32) 0, (uint32) CPRIF_DRV_NUMBER_OF_MSG); 6271 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_308r, &data, 6272 BRCM_RESERVED_CPM_308_3f, write_val); 6273 6274 COMPILER_64_SET(write_val, (uint32) 0, (uint32) CPRIF_DRV_N_MG_IN_MSTR_FRM); 6275 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_308r, &data, 6276 BRCM_RESERVED_CPM_308_2f, write_val); 6277 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_308r(unit, port, 6278 data)); 6279 6280 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_309r(unit, port, 6281 &data)); 6282 speedi_h = 0; 6283 speedi_l = (speedi * CPRIF_DRV_NUMBER_OF_MSG * 6284 (CPRIF_DRV_N_MG_IN_MSTR_FRM*CPRIF_DRV_RSVD4_MSG_SIZE+1)) & 0xffffffff; 6285 COMPILER_64_SET(speedi_64, speedi_h, speedi_l); 6286 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_309r, &data, 6287 BRCM_RESERVED_CPM_309_0f, speedi_64); 6288 6289 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_309r(unit, port, 6290 data)); 6291 6292 6293 SOC_IF_ERROR_RETURN(READ_CPRI_ENCAP_TDM_CTRLr(unit, port, &data32)); 6294 soc_reg_field_set(unit, CPRI_ENCAP_TDM_CTRLr, &data32, 6295 TDM_DISABLEf, 1); 6296 6297 SOC_IF_ERROR_RETURN(WRITE_CPRI_ENCAP_TDM_CTRLr(unit, port, data32)); 6298 6299 _SOC_IF_ERR_EXIT(READ_CPRI_RXFRM_BFRM_CTRLr(unit, port, &data32)); 6300 soc_reg_field_set(unit, CPRI_RXFRM_BFRM_CTRLr, &data32, 6301 BRCM_RESERVED_CPM_306_0f, 1); 6302 6303 SOC_IF_ERROR_RETURN(WRITE_CPRI_RXFRM_BFRM_CTRLr(unit, port, data32)); 6304 6305 exit: 6306 SOC_FUNC_RETURN; 6307 } 6308 6309 int cprif_drv_rsvd4_rxpcs_speed_get(int unit, int port, 6310 cprimod_port_rsvd4_speed_mult_t *speed) 6311 { 6312 uint64 data; 6313 uint64 read_val; 6314 uint32 speedi; 6315 SOC_INIT_FUNC_DEFS; 6316 6317 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, 6318 &data)); 6319 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_307r, 6320 data, BRCM_RESERVED_CPM_307_2f); 6321 speedi = COMPILER_64_LO(read_val); 6322 6323 if (speedi == 2) { 6324 *speed = cprimodRsvd4SpdMult4X; 6325 } else if (speedi == 3) { 6326 *speed = cprimodRsvd4SpdMult8X; 6327 } 6328 6329 SOC_FUNC_RETURN; 6330 } 6331 6332 int cprif_drv_rsvd4_txpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 6333 cprimod_port_rsvd4_speed_mult_t speed) 6334 { 6335 uint64 data; 6336 uint64 write_val; 6337 uint32 speedi, speedv; 6338 uint32 speedi_h, speedi_l; 6339 uint64 speedi_64; 6340 int osr; 6341 SOC_INIT_FUNC_DEFS; 6342 6343 if (speed == cprimodRsvd4SpdMult4X) { 6344 speedi = 4; 6345 speedv = 2; 6346 osr = 5; 6347 } else if (speed == cprimodRsvd4SpdMult8X) { 6348 speedi = 8; 6349 speedv = 3; 6350 osr = 2; 6351 } else { 6352 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed is not supported for rsvd4")); 6353 } 6354 SOC_IF_ERROR_RETURN(READ_CPRI_PMD_TX_CTRLr(unit, port, &data)); 6355 COMPILER_64_SET(write_val, 0, osr); 6356 soc_reg64_field_set(unit, CPRI_PMD_TX_CTRLr, &data, PMD_TX_OSR_MODEf, write_val); 6357 SOC_IF_ERROR_RETURN(WRITE_CPRI_PMD_TX_CTRLr(unit, port, data)); 6358 falcon2_monterey_frc_tx_osr(&phy->access, osr); 6359 6360 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_12r(unit, port, 6361 &data)); 6362 6363 COMPILER_64_SET(write_val, 0, 1); 6364 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 6365 BRCM_RESERVED_CPM_12_3f, write_val); 6366 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 6367 BRCM_RESERVED_CPM_12_7f, write_val); 6368 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 6369 BRCM_RESERVED_CPM_12_8f, write_val); 6370 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_12r(unit, port, 6371 data)); 6372 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_3r(unit, port, 6373 &data)); 6374 6375 /* 6376 * The padding is 1 for default supported configuration. 6377 * cprimod_rsvd4_tx_padding_size_set() is used as well. 6378 */ 6379 COMPILER_64_SET(write_val, 0, 1); 6380 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_3r, &data, 6381 BRCM_RESERVED_CPM_3_1f, write_val); 6382 6383 COMPILER_64_SET(write_val, 0, speedv); 6384 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_3r, &data, 6385 BRCM_RESERVED_CPM_3_2f, write_val); 6386 6387 COMPILER_64_SET(write_val, 0, (uint32) CPRIF_DRV_NUMBER_OF_MSG); 6388 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_3r, &data, 6389 BRCM_RESERVED_CPM_3_3f, write_val); 6390 6391 COMPILER_64_SET(write_val, 0, (uint32) CPRIF_DRV_N_MG_IN_MSTR_FRM); 6392 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_3r, &data, 6393 BRCM_RESERVED_CPM_3_4f, write_val); 6394 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_3r(unit, port, 6395 data)); 6396 6397 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_4r(unit, port, 6398 &data)); 6399 speedi_h = 0; 6400 speedi_l = ((speedi*CPRIF_DRV_NUMBER_OF_MSG)-1) & 0xffffffff; 6401 COMPILER_64_SET(speedi_64, speedi_h, speedi_l); 6402 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_4r, &data, 6403 BRCM_RESERVED_CPM_4_0f, speedi_64); 6404 speedi_l = ((speedi*(CPRIF_DRV_N_MG_IN_MSTR_FRM-1) * 6405 CPRIF_DRV_NUMBER_OF_MSG)-1) & 0xffffffff; 6406 COMPILER_64_SET(speedi_64, speedi_h, speedi_l); 6407 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_4r, &data, 6408 BRCM_RESERVED_CPM_4_1f, speedi_64); 6409 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_4r(unit, port, data)); 6410 COMPILER_64_ZERO(data); 6411 COMPILER_64_SET(write_val, 0, 1); 6412 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_2r, &data, 6413 BRCM_RESERVED_CPM_2_0f, write_val); 6414 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_2r(unit, port, 6415 data)); 6416 6417 exit: 6418 SOC_FUNC_RETURN; 6419 } 6420 6421 int cprif_drv_rsvd4_txpcs_speed_get(int unit, int port, 6422 cprimod_port_rsvd4_speed_mult_t *speed) 6423 { 6424 uint64 data; 6425 uint64 read_val; 6426 uint32 speedv; 6427 SOC_INIT_FUNC_DEFS; 6428 6429 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6430 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_3r(unit, port,&data)); 6431 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_3r, 6432 data, BRCM_RESERVED_CPM_3_2f); 6433 6434 speedv = COMPILER_64_LO(read_val); 6435 *speed = cprimodSpdCount; 6436 if (speedv == 2) { 6437 *speed = cprimodRsvd4SpdMult4X; 6438 } else if (speedv == 3) { 6439 *speed = cprimodRsvd4SpdMult8X; 6440 } 6441 6442 SOC_FUNC_RETURN; 6443 } 6444 6445 int cprif_drv_txcpri_port_type_get(int unit, int port, 6446 cprimod_port_interface_type_t *interface) 6447 { 6448 uint64 data; 6449 uint64 read_val; 6450 uint32 iftype; 6451 SOC_INIT_FUNC_DEFS; 6452 6453 /* 6454 * checking the PCS configuration for RSVD4 enable. 6455 * BRCM_RESERVED_CPM_2,BRCM_RESERVED_CPM_2_0f is not 6456 * available in agnostic mode. 6457 */ 6458 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_12r(unit, port, 6459 &data)); 6460 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, 6461 data, BRCM_RESERVED_CPM_12_8f); 6462 iftype = COMPILER_64_LO(read_val); 6463 6464 if (iftype == 1) { 6465 *interface = cprimodRsvd4; 6466 } else { 6467 *interface = cprimodCpri; 6468 } 6469 6470 SOC_FUNC_RETURN; 6471 } 6472 6473 int cprif_drv_rxcpri_port_type_get(int unit, int port, 6474 cprimod_port_interface_type_t *interface) 6475 { 6476 uint64 data; 6477 uint64 read_val; 6478 uint32 iftype; 6479 SOC_INIT_FUNC_DEFS; 6480 6481 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, 6482 &data)); 6483 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_307r, 6484 data, BRCM_RESERVED_CPM_307_0f); 6485 iftype = COMPILER_64_LO(read_val); 6486 6487 if (iftype == 1) { 6488 *interface = cprimodRsvd4; 6489 } else { 6490 *interface = cprimodCpri; 6491 } 6492 6493 SOC_FUNC_RETURN; 6494 } 6495 6496 int cprif_drv_rx_frame_optional_config_set(int unit, int port, 6497 cprimod_rx_config_field_t field, 6498 int value) 6499 { 6500 uint64 data; 6501 uint64 write_val; 6502 SOC_INIT_FUNC_DEFS; 6503 6504 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 6505 COMPILER_64_SET(write_val, 0, (uint32) value); 6506 switch (field) { 6507 case cprimodRxConfig8b10bAllowSeedChange: 6508 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6509 RXPCS_8B10B_ALLOW_SEED_CHANGEf, write_val); 6510 break; 6511 case cprimodRxConfig8b10bDescrHw: 6512 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6513 RXPCS_8B10B_DESCR_HWf, write_val); 6514 break; 6515 case cprimodRxConfig8b10bDescrEn: 6516 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6517 RXPCS_8B10B_DESCR_ENf, write_val); 6518 break; 6519 case cprimodRxConfiglinkAcqSwMode: 6520 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6521 RXPCS_LINK_ACQ_SW_MODEf, write_val); 6522 break; 6523 case cprimodRxConfig64b66bLosOption: 6524 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6525 RXPCS_64B66B_LOS_OPTIONf, write_val); 6526 break; 6527 case cprimodRxConfig8b10bForceCommaAlignEn: 6528 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6529 RXPCS_8B10B_FORCE_COMMA_ALIGN_ENf, write_val); 6530 break; 6531 case cprimodRxConfig64b66bBerWindowLimit: 6532 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6533 RXPCS_64B66B_BER_WINDOW_LIMITf, write_val); 6534 break; 6535 case cprimodRxConfig64b66bBerLimit: 6536 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6537 RXPCS_64B66B_BER_LIMITf, write_val); 6538 break; 6539 case cprimodRxConfigtestMode: 6540 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6541 RXPCS_TEST_MODEf, write_val); 6542 break; 6543 case cprimodRxConfig64b66bInvalidShCnt: 6544 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6545 RXPCS_64B66B_INVALID_SH_CNTf, write_val); 6546 break; 6547 case cprimodRxConfig64b66bValidShCnt: 6548 soc_reg64_field_set(unit, CPRI_RXPCS_CTRLr, &data, 6549 RXPCS_64B66B_VALID_SH_CNTf, write_val); 6550 break; 6551 default: 6552 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Rx cpri")); 6553 break; 6554 } 6555 SOC_IF_ERROR_RETURN(WRITE_CPRI_RXPCS_CTRLr(unit, port, data)); 6556 6557 exit: 6558 SOC_FUNC_RETURN; 6559 6560 } 6561 6562 int cprif_drv_rx_frame_optional_config_get(int unit, int port, 6563 cprimod_rx_config_field_t field, 6564 int* value) 6565 { 6566 uint64 data; 6567 uint64 read_val; 6568 SOC_INIT_FUNC_DEFS; 6569 6570 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_CTRLr(unit, port, &data)); 6571 switch (field) { 6572 case cprimodRxConfig8b10bAllowSeedChange: 6573 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6574 RXPCS_8B10B_ALLOW_SEED_CHANGEf); 6575 *value = COMPILER_64_LO(read_val); 6576 break; 6577 case cprimodRxConfig8b10bDescrHw: 6578 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6579 RXPCS_8B10B_DESCR_HWf); 6580 *value = COMPILER_64_LO(read_val); 6581 break; 6582 case cprimodRxConfig8b10bDescrEn: 6583 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6584 RXPCS_8B10B_DESCR_ENf); 6585 *value = COMPILER_64_LO(read_val); 6586 break; 6587 case cprimodRxConfiglinkAcqSwMode: 6588 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6589 RXPCS_LINK_ACQ_SW_MODEf); 6590 *value = COMPILER_64_LO(read_val); 6591 break; 6592 case cprimodRxConfig64b66bLosOption: 6593 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6594 RXPCS_64B66B_LOS_OPTIONf); 6595 *value = COMPILER_64_LO(read_val); 6596 break; 6597 case cprimodRxConfig8b10bForceCommaAlignEn: 6598 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6599 RXPCS_8B10B_FORCE_COMMA_ALIGN_ENf); 6600 *value = COMPILER_64_LO(read_val); 6601 break; 6602 case cprimodRxConfig64b66bBerWindowLimit: 6603 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6604 RXPCS_64B66B_BER_WINDOW_LIMITf); 6605 *value = COMPILER_64_LO(read_val); 6606 break; 6607 case cprimodRxConfig64b66bBerLimit: 6608 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6609 RXPCS_64B66B_BER_LIMITf); 6610 *value = COMPILER_64_LO(read_val); 6611 break; 6612 case cprimodRxConfigtestMode: 6613 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6614 RXPCS_TEST_MODEf); 6615 *value = COMPILER_64_LO(read_val); 6616 break; 6617 case cprimodRxConfig64b66bInvalidShCnt: 6618 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6619 RXPCS_64B66B_INVALID_SH_CNTf); 6620 *value = COMPILER_64_LO(read_val); 6621 break; 6622 case cprimodRxConfig64b66bValidShCnt: 6623 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_CTRLr, data, 6624 RXPCS_64B66B_VALID_SH_CNTf); 6625 *value = COMPILER_64_LO(read_val); 6626 break; 6627 default: 6628 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Rx cpri")); 6629 break; 6630 } 6631 6632 exit: 6633 SOC_FUNC_RETURN; 6634 6635 } 6636 6637 6638 int cprif_drv_tx_frame_optional_config_set(int unit, int port, 6639 cprimod_tx_config_field_t field, 6640 uint32 value) 6641 { 6642 uint64 data; 6643 uint64 write_val; 6644 uint32 data32; 6645 SOC_INIT_FUNC_DEFS; 6646 6647 COMPILER_64_SET(write_val, 0, value); 6648 switch (field) { 6649 case cprimodTxConfigagnosticMode: 6650 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6651 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, 6652 BRCM_RESERVED_CPM_11_8f, write_val); 6653 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 6654 break; 6655 case cprimodTxConfigtxpmdDisableOverrideVal: 6656 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6657 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, 6658 TX_PCS_TXPMD_DISABLE_OVERRIDE_VALf, write_val); 6659 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 6660 break; 6661 case cprimodTxConfigtxpmdDisableOverrideEn: 6662 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6663 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, 6664 TX_PCS_TXPMD_DISABLE_OVERRIDE_ENf, write_val); 6665 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 6666 break; 6667 case cprimodTxConfigseed8B10B: 6668 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6669 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, 6670 TX_PCS_SEED_8B10Bf, write_val); 6671 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 6672 break; 6673 case cprimodTxConfigscrambleBypass: 6674 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6675 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, 6676 TX_PCS_SCRAMBLE_BYPASSf, write_val); 6677 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 6678 break; 6679 case cprimodTxConfigseed8b10b: 6680 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6681 soc_reg64_field_set(unit, CPRI_TXPCS_CTRLr, &data, 6682 TX_PCS_SEED_8B10Bf, write_val); 6683 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXPCS_CTRLr(unit, port, data)); 6684 break; 6685 case cprimodTxConfigcwaScrEn8b10b: 6686 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_GENERALr(unit, port, &data32)); 6687 soc_reg_field_set(unit, CPRI_TXFRM_CWA_GENERALr, &data32, 6688 TX_CWA_SCR_EN_8B10Bf, value); 6689 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_CWA_GENERALr(unit, port, data32)); 6690 break; 6691 default: 6692 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Tx cpri")); 6693 break; 6694 } 6695 6696 exit: 6697 SOC_FUNC_RETURN; 6698 6699 } 6700 6701 int cprif_drv_tx_frame_optional_config_get(int unit, int port, 6702 cprimod_tx_config_field_t field, 6703 uint32* value) 6704 { 6705 uint64 data; 6706 uint64 read_val; 6707 uint32 data32; 6708 SOC_INIT_FUNC_DEFS; 6709 6710 switch (field) { 6711 case cprimodTxConfigagnosticMode: 6712 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6713 read_val = soc_reg64_field_get(unit, CPRI_TXPCS_CTRLr, data, 6714 BRCM_RESERVED_CPM_11_8f); 6715 *value = COMPILER_64_LO(read_val); 6716 break; 6717 case cprimodTxConfigtxpmdDisableOverrideVal: 6718 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6719 read_val = soc_reg64_field_get(unit, CPRI_TXPCS_CTRLr, data, 6720 TX_PCS_TXPMD_DISABLE_OVERRIDE_VALf); 6721 *value = COMPILER_64_LO(read_val); 6722 break; 6723 case cprimodTxConfigtxpmdDisableOverrideEn: 6724 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6725 read_val = soc_reg64_field_get(unit, CPRI_TXPCS_CTRLr, data, 6726 TX_PCS_TXPMD_DISABLE_OVERRIDE_ENf); 6727 *value = COMPILER_64_LO(read_val); 6728 break; 6729 case cprimodTxConfigseed8B10B: 6730 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6731 read_val = soc_reg64_field_get(unit, CPRI_TXPCS_CTRLr, data, 6732 TX_PCS_SEED_8B10Bf); 6733 *value = COMPILER_64_LO(read_val); 6734 break; 6735 case cprimodTxConfigscrambleBypass: 6736 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6737 read_val = soc_reg64_field_get(unit, CPRI_TXPCS_CTRLr, data, 6738 TX_PCS_SCRAMBLE_BYPASSf); 6739 *value = COMPILER_64_LO(read_val); 6740 break; 6741 case cprimodTxConfigseed8b10b: 6742 SOC_IF_ERROR_RETURN(READ_CPRI_TXPCS_CTRLr(unit, port, &data)); 6743 read_val = soc_reg64_field_get(unit, CPRI_TXPCS_CTRLr, data, 6744 TX_PCS_SEED_8B10Bf); 6745 *value = COMPILER_64_LO(read_val); 6746 break; 6747 case cprimodTxConfigcwaScrEn8b10b: 6748 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_GENERALr(unit, port, &data32)); 6749 *value = soc_reg_field_get(unit, CPRI_TXFRM_CWA_GENERALr, data32, 6750 TX_CWA_SCR_EN_8B10Bf); 6751 break; 6752 default: 6753 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Tx cpri")); 6754 break; 6755 } 6756 6757 exit: 6758 SOC_FUNC_RETURN; 6759 6760 } 6761 6762 6763 int cprif_drv_rsvd4_rx_frame_optional_config_set(int unit, int port, 6764 cprimod_rsvd4_rx_config_field_t field, 6765 int value) 6766 { 6767 uint64 data; 6768 uint64 write_val; 6769 SOC_INIT_FUNC_DEFS; 6770 6771 COMPILER_64_SET(write_val, 0, (uint32) value); 6772 switch (field) { 6773 case cprimodRsvd4RxConfigDescrambleEnable: 6774 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6775 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6776 BRCM_RESERVED_CPM_307_1f, write_val); 6777 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_307r(unit, port, data)); 6778 break; 6779 case cprimodRsvd4RxConfigSyncThreshold: 6780 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6781 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6782 BRCM_RESERVED_CPM_307_3f, write_val); 6783 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_307r(unit, port, data)); 6784 break; 6785 case cprimodRsvd4RxConfigUnsyncThreshold: 6786 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6787 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6788 BRCM_RESERVED_CPM_307_4f, write_val); 6789 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_307r(unit, port, data)); 6790 break; 6791 case cprimodRsvd4RxConfigFwdIdlesToFramer: 6792 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6793 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6794 BRCM_RESERVED_CPM_307_7f, write_val); 6795 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_307r(unit, port, data)); 6796 break; 6797 6798 case cprimodRsvd4RxConfigFrameSyncThreshold: 6799 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_308r(unit, port, &data)); 6800 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_308r, &data, 6801 BRCM_RESERVED_CPM_308_0f, write_val); 6802 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_308r(unit, port, data)); 6803 break; 6804 case cprimodRsvd4RxConfigFrameUnsyncThreshold: 6805 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_308r(unit, port, &data)); 6806 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_308r, &data, 6807 BRCM_RESERVED_CPM_308_1f, write_val); 6808 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_308r(unit, port, data)); 6809 break; 6810 case cprimodRsvd4RxConfigBlockSize: 6811 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6812 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_307r, &data, 6813 BRCM_RESERVED_CPM_307_5f, write_val); 6814 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_307r(unit, port, data)); 6815 break; 6816 default: 6817 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Rx rsvd4")); 6818 break; 6819 } 6820 6821 exit: 6822 SOC_FUNC_RETURN; 6823 6824 } 6825 6826 int cprif_drv_rsvd4_rx_frame_optional_config_get(int unit, int port, 6827 cprimod_rsvd4_rx_config_field_t field, 6828 int* value) 6829 { 6830 uint64 data; 6831 uint64 read_val; 6832 SOC_INIT_FUNC_DEFS; 6833 6834 switch (field) { 6835 case cprimodRsvd4RxConfigDescrambleEnable: 6836 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6837 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_307r, data, 6838 BRCM_RESERVED_CPM_307_1f); 6839 *value = COMPILER_64_LO(read_val); 6840 break; 6841 case cprimodRsvd4RxConfigSyncThreshold: 6842 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6843 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_307r, data, 6844 BRCM_RESERVED_CPM_307_3f); 6845 *value = COMPILER_64_LO(read_val); 6846 break; 6847 case cprimodRsvd4RxConfigUnsyncThreshold: 6848 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6849 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_307r, data, 6850 BRCM_RESERVED_CPM_307_4f); 6851 *value = COMPILER_64_LO(read_val); 6852 break; 6853 case cprimodRsvd4RxConfigFrameSyncThreshold: 6854 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_308r(unit, port, &data)); 6855 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_308r, data, 6856 BRCM_RESERVED_CPM_308_0f); 6857 *value = COMPILER_64_LO(read_val); 6858 break; 6859 case cprimodRsvd4RxConfigFrameUnsyncThreshold: 6860 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_308r(unit, port, &data)); 6861 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_308r, data, 6862 BRCM_RESERVED_CPM_308_1f); 6863 *value = COMPILER_64_LO(read_val); 6864 break; 6865 case cprimodRsvd4RxConfigBlockSize: 6866 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_307r(unit, port, &data)); 6867 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_307r, data, 6868 BRCM_RESERVED_CPM_307_5f); 6869 *value = COMPILER_64_LO(read_val); 6870 break; 6871 default: 6872 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Rx rsvd4")); 6873 break; 6874 } 6875 6876 exit: 6877 SOC_FUNC_RETURN; 6878 6879 } 6880 6881 6882 int cprif_drv_rsvd4_rx_fsm_state_set(int unit, int port, 6883 cprimod_rsvd4_rx_fsm_state_t state) 6884 { 6885 uint64 data; 6886 uint64 write_val; 6887 SOC_INIT_FUNC_DEFS; 6888 6889 COMPILER_64_ZERO(data); 6890 COMPILER_64_SET(write_val, 0, state); 6891 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_310r, &data, 6892 BRCM_RESERVED_CPM_310_0f, write_val); 6893 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_310r(unit, port, data)); 6894 6895 SOC_FUNC_RETURN; 6896 } 6897 6898 int cprif_drv_rsvd4_rx_fsm_state_get(int unit, int port, 6899 cprimod_rsvd4_rx_fsm_state_t* state) 6900 { 6901 uint64 data; 6902 uint64 read_val; 6903 SOC_INIT_FUNC_DEFS; 6904 6905 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_310r(unit, port, &data)); 6906 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_310r, data, 6907 BRCM_RESERVED_CPM_310_0f); 6908 *state = COMPILER_64_LO(read_val); 6909 6910 SOC_FUNC_RETURN; 6911 } 6912 6913 6914 int cprif_drv_rsvd4_rx_overide_set(int unit, int port, 6915 cprimod_rsvd4_rx_overide_t parameter, 6916 int enable, int value) 6917 { 6918 uint64 data; 6919 uint64 write_val, write_val1; 6920 SOC_INIT_FUNC_DEFS; 6921 6922 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_311r(unit, port, &data)); 6923 6924 COMPILER_64_SET(write_val, 0, (uint32) value); 6925 COMPILER_64_SET(write_val1, 0, (uint32) enable); 6926 switch (parameter) { 6927 case cprimodRsvd4RxOverideFrameUnsyncTInvldMgRecvd: 6928 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6929 BRCM_RESERVED_CPM_311_0f, write_val); 6930 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6931 BRCM_RESERVED_CPM_311_1f, write_val1); 6932 break; 6933 case cprimodRsvd4RxOverideFrameSyncTVldMgRecvd: 6934 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6935 BRCM_RESERVED_CPM_311_2f, write_val); 6936 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6937 BRCM_RESERVED_CPM_311_3f, write_val1); 6938 break; 6939 case cprimodRsvd4RxOverideKMgIdlesRecvd: 6940 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6941 BRCM_RESERVED_CPM_311_4f, write_val); 6942 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6943 BRCM_RESERVED_CPM_311_5f, write_val1); 6944 break; 6945 case cprimodRsvd4RxOverideIdleReqRecvd: 6946 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6947 BRCM_RESERVED_CPM_311_6f, write_val); 6948 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6949 BRCM_RESERVED_CPM_311_7f, write_val1); 6950 break; 6951 case cprimodRsvd4RxOverideIdleAckRecvd: 6952 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6953 BRCM_RESERVED_CPM_311_8f, write_val); 6954 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6955 BRCM_RESERVED_CPM_311_9f, write_val1); 6956 break; 6957 case cprimodRsvd4RxOverideSeedCapAndVerifyDone: 6958 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6959 BRCM_RESERVED_CPM_311_10f, write_val); 6960 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_311r, &data, 6961 BRCM_RESERVED_CPM_311_11f, write_val1); 6962 break; 6963 default: 6964 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for rsvd4 Rx overide")); 6965 break; 6966 } 6967 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_311r(unit, port, data)); 6968 6969 exit: 6970 SOC_FUNC_RETURN; 6971 } 6972 6973 int cprif_drv_rsvd4_rx_overide_get(int unit, int port, 6974 cprimod_rsvd4_rx_overide_t parameter, 6975 int* enable, int* value) 6976 { 6977 uint64 data; 6978 uint64 read_val, read_val1; 6979 SOC_INIT_FUNC_DEFS; 6980 6981 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_311r(unit, port, &data)); 6982 switch (parameter) { 6983 case cprimodRsvd4RxOverideFrameUnsyncTInvldMgRecvd: 6984 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 6985 BRCM_RESERVED_CPM_311_0f); 6986 *value = COMPILER_64_LO(read_val); 6987 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 6988 BRCM_RESERVED_CPM_311_1f); 6989 *enable = COMPILER_64_LO(read_val1); 6990 break; 6991 case cprimodRsvd4RxOverideFrameSyncTVldMgRecvd: 6992 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 6993 BRCM_RESERVED_CPM_311_2f); 6994 *value = COMPILER_64_LO(read_val); 6995 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 6996 BRCM_RESERVED_CPM_311_3f); 6997 *enable = COMPILER_64_LO(read_val1); 6998 break; 6999 case cprimodRsvd4RxOverideKMgIdlesRecvd: 7000 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7001 BRCM_RESERVED_CPM_311_4f); 7002 *value = COMPILER_64_LO(read_val); 7003 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7004 BRCM_RESERVED_CPM_311_5f); 7005 *enable = COMPILER_64_LO(read_val1); 7006 break; 7007 case cprimodRsvd4RxOverideIdleReqRecvd: 7008 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7009 BRCM_RESERVED_CPM_311_6f); 7010 *value = COMPILER_64_LO(read_val); 7011 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7012 BRCM_RESERVED_CPM_311_7f); 7013 *enable = COMPILER_64_LO(read_val1); 7014 break; 7015 case cprimodRsvd4RxOverideIdleAckRecvd: 7016 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7017 BRCM_RESERVED_CPM_311_8f); 7018 *value = COMPILER_64_LO(read_val); 7019 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7020 BRCM_RESERVED_CPM_311_9f); 7021 *enable = COMPILER_64_LO(read_val1); 7022 break; 7023 case cprimodRsvd4RxOverideSeedCapAndVerifyDone: 7024 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7025 BRCM_RESERVED_CPM_311_10f); 7026 *value = COMPILER_64_LO(read_val); 7027 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_311r, data, 7028 BRCM_RESERVED_CPM_311_11f); 7029 *enable = COMPILER_64_LO(read_val1); 7030 break; 7031 default: 7032 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for rsvd4 Rx overide")); 7033 break; 7034 } 7035 7036 exit: 7037 SOC_FUNC_RETURN; 7038 7039 } 7040 7041 7042 int cprif_drv_rsvd4_tx_frame_optional_config_set(int unit, int port, 7043 cprimod_rsvd4_tx_config_field_t field, 7044 int value) 7045 { 7046 uint64 data; 7047 uint64 write_val; 7048 SOC_INIT_FUNC_DEFS; 7049 7050 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_12r(unit, port, &data)); 7051 COMPILER_64_SET(write_val, 0, (uint32) value); 7052 switch (field) { 7053 case cprimodRsvd4TxConfigForceOffState: 7054 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 7055 BRCM_RESERVED_CPM_12_0f, write_val); 7056 break; 7057 case cprimodRsvd4TxConfigAckT: 7058 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 7059 BRCM_RESERVED_CPM_12_1f, write_val); 7060 break; 7061 case cprimodRsvd4TxConfigForceIdleAck: 7062 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 7063 BRCM_RESERVED_CPM_12_4f, write_val); 7064 break; 7065 case cprimodRsvd4TxConfigLosEnable: 7066 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 7067 BRCM_RESERVED_CPM_12_6f, write_val); 7068 break; 7069 case cprimodRsvd4TxConfigScrambleEnable: 7070 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 7071 BRCM_RESERVED_CPM_12_5f, write_val); 7072 break; 7073 case cprimodRsvd4TxConfigScramblerSeed: 7074 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 7075 BRCM_RESERVED_CPM_12_2f, write_val); 7076 break; 7077 case cprimodRsvd4TxConfigTransmitterEnable: 7078 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_12r, &data, 7079 BRCM_RESERVED_CPM_12_7f, write_val); 7080 break; 7081 default: 7082 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Tx rsvd4 overide")); 7083 break; 7084 } 7085 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_12r(unit, port, data)); 7086 7087 exit: 7088 SOC_FUNC_RETURN; 7089 7090 } 7091 7092 int cprif_drv_rsvd4_tx_frame_optional_config_get(int unit, int port, 7093 cprimod_rsvd4_tx_config_field_t field, 7094 int* value) 7095 { 7096 uint64 data; 7097 uint64 read_val; 7098 SOC_INIT_FUNC_DEFS; 7099 7100 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_12r(unit, port, &data)); 7101 switch (field) { 7102 case cprimodRsvd4TxConfigForceOffState: 7103 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, data, 7104 BRCM_RESERVED_CPM_12_0f); 7105 *value = COMPILER_64_LO(read_val); 7106 break; 7107 case cprimodRsvd4TxConfigAckT: 7108 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, data, 7109 BRCM_RESERVED_CPM_12_1f); 7110 *value = COMPILER_64_LO(read_val); 7111 break; 7112 case cprimodRsvd4TxConfigForceIdleAck: 7113 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, data, 7114 BRCM_RESERVED_CPM_12_4f); 7115 *value = COMPILER_64_LO(read_val); 7116 break; 7117 case cprimodRsvd4TxConfigLosEnable: 7118 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, data, 7119 BRCM_RESERVED_CPM_12_6f); 7120 *value = COMPILER_64_LO(read_val); 7121 break; 7122 case cprimodRsvd4TxConfigScrambleEnable: 7123 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, data, 7124 BRCM_RESERVED_CPM_12_5f); 7125 *value = COMPILER_64_LO(read_val); 7126 break; 7127 case cprimodRsvd4TxConfigScramblerSeed: 7128 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, data, 7129 BRCM_RESERVED_CPM_12_2f); 7130 *value = COMPILER_64_LO(read_val); 7131 break; 7132 case cprimodRsvd4TxConfigTransmitterEnable: 7133 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_12r, data, 7134 BRCM_RESERVED_CPM_12_7f); 7135 *value = COMPILER_64_LO(read_val); 7136 break; 7137 default: 7138 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Tx rsvd4 overide")); 7139 break; 7140 } 7141 7142 exit: 7143 SOC_FUNC_RETURN; 7144 7145 } 7146 7147 7148 int cprif_drv_rsvd4_tx_fsm_state_set(int unit, int port, 7149 cprimod_rsvd4_tx_fsm_state_t state) 7150 { 7151 uint64 data; 7152 uint64 write_val; 7153 SOC_INIT_FUNC_DEFS; 7154 7155 COMPILER_64_ZERO(data); 7156 COMPILER_64_SET(write_val, 0, state); 7157 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_13r, &data, 7158 BRCM_RESERVED_CPM_13_0f, write_val); 7159 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_13r(unit, port, data)); 7160 7161 SOC_FUNC_RETURN; 7162 7163 } 7164 7165 int cprif_drv_rsvd4_tx_fsm_state_get(int unit, int port, 7166 cprimod_rsvd4_tx_fsm_state_t* state) 7167 { 7168 uint64 data; 7169 uint64 read_val; 7170 SOC_INIT_FUNC_DEFS; 7171 7172 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_13r(unit, port, &data)); 7173 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_13r, data, 7174 BRCM_RESERVED_CPM_13_0f); 7175 *state = COMPILER_64_LO(read_val); 7176 7177 SOC_FUNC_RETURN; 7178 } 7179 7180 7181 int cprif_drv_rsvd4_tx_overide_set(int unit, int port, 7182 cprimod_rsvd4_tx_overide_t parameter, 7183 int enable, int value) 7184 { 7185 uint64 data; 7186 uint64 write_val, write_val1; 7187 SOC_INIT_FUNC_DEFS; 7188 7189 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_14r(unit, port, &data)); 7190 COMPILER_64_SET(write_val, 0, value); 7191 COMPILER_64_SET(write_val1, 0, enable); 7192 switch (parameter) { 7193 case cprimodRsvd4TxOverideStartTx: 7194 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7195 BRCM_RESERVED_CPM_14_0f, write_val); 7196 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7197 BRCM_RESERVED_CPM_14_1f, write_val1); 7198 break; 7199 case cprimodRsvd4TxOverideRxPcsAckCap: 7200 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7201 BRCM_RESERVED_CPM_14_2f, write_val); 7202 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7203 BRCM_RESERVED_CPM_14_3f, write_val1); 7204 break; 7205 case cprimodRsvd4TxOverideRxPcsIdleReq: 7206 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7207 BRCM_RESERVED_CPM_14_4f, write_val); 7208 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7209 BRCM_RESERVED_CPM_14_5f, write_val1); 7210 break; 7211 case cprimodRsvd4TxOverideRxPcsScrLock: 7212 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7213 BRCM_RESERVED_CPM_14_6f, write_val); 7214 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7215 BRCM_RESERVED_CPM_14_7f, write_val1); 7216 break; 7217 case cprimodRsvd4TxOverideLosStauts: 7218 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7219 BRCM_RESERVED_CPM_14_8f, write_val); 7220 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_14r, &data, 7221 BRCM_RESERVED_CPM_14_9f, write_val1); 7222 break; 7223 default: 7224 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Tx rsvd4 overide")); 7225 break; 7226 } 7227 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_CPM_14r(unit, port, data)); 7228 7229 exit: 7230 SOC_FUNC_RETURN; 7231 7232 } 7233 7234 int cprif_drv_rsvd4_tx_overide_get(int unit, int port, 7235 cprimod_rsvd4_tx_overide_t parameter, 7236 int* enable, int* value) 7237 { 7238 uint64 data; 7239 uint64 read_val, read_val1; 7240 SOC_INIT_FUNC_DEFS; 7241 7242 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_CPM_14r(unit, port, &data)); 7243 switch (parameter) { 7244 case cprimodRsvd4TxOverideStartTx: 7245 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7246 BRCM_RESERVED_CPM_14_0f); 7247 *value = COMPILER_64_LO(read_val); 7248 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7249 BRCM_RESERVED_CPM_14_1f); 7250 *enable = COMPILER_64_LO(read_val1); 7251 break; 7252 case cprimodRsvd4TxOverideRxPcsAckCap: 7253 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7254 BRCM_RESERVED_CPM_14_2f); 7255 *value = COMPILER_64_LO(read_val); 7256 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7257 BRCM_RESERVED_CPM_14_3f); 7258 *enable = COMPILER_64_LO(read_val1); 7259 break; 7260 case cprimodRsvd4TxOverideRxPcsIdleReq: 7261 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7262 BRCM_RESERVED_CPM_14_4f); 7263 *value = COMPILER_64_LO(read_val); 7264 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7265 BRCM_RESERVED_CPM_14_5f); 7266 *enable = COMPILER_64_LO(read_val1); 7267 break; 7268 case cprimodRsvd4TxOverideRxPcsScrLock: 7269 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7270 BRCM_RESERVED_CPM_14_6f); 7271 *value = COMPILER_64_LO(read_val); 7272 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7273 BRCM_RESERVED_CPM_14_7f); 7274 *enable = COMPILER_64_LO(read_val1); 7275 break; 7276 case cprimodRsvd4TxOverideLosStauts: 7277 read_val = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7278 BRCM_RESERVED_CPM_14_8f); 7279 *value = COMPILER_64_LO(read_val); 7280 read_val1 = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_14r, data, 7281 BRCM_RESERVED_CPM_14_9f); 7282 *enable = COMPILER_64_LO(read_val1); 7283 break; 7284 default: 7285 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for Tx rsvd4 overide")); 7286 break; 7287 } 7288 7289 exit: 7290 SOC_FUNC_RETURN; 7291 7292 } 7293 7294 int cprif_drv_pmd_port_status_get(int unit, int port, cprimod_pmd_port_status_t status, 7295 uint32* value) 7296 { 7297 uint32 data; 7298 SOC_INIT_FUNC_DEFS; 7299 7300 SOC_IF_ERROR_RETURN(READ_CPMPORT_PMD_PORT_STATUSr(unit, port, &data)); 7301 switch (status) { 7302 case cprimodPmdPortStatusTxClockValid: 7303 *value = soc_reg_field_get(unit, CPMPORT_PMD_PORT_STATUSr, data, 7304 PMD_TX_CLK_VLD_STSf); 7305 break; 7306 7307 case cprimodPmdPortStatusRxClockValid: 7308 *value = soc_reg_field_get(unit, CPMPORT_PMD_PORT_STATUSr, data, 7309 PMD_RX_CLK_VLD_STSf); 7310 break; 7311 7312 case cprimodPmdPortStatusRxLock: 7313 *value = soc_reg_field_get(unit, CPMPORT_PMD_PORT_STATUSr, data, 7314 PMD_RX_LOCK_STSf); 7315 break; 7316 7317 case cprimodPmdPortStatusEnergyDetected: 7318 *value = soc_reg_field_get(unit, CPMPORT_PMD_PORT_STATUSr, data, 7319 PMD_ENERGY_DETECT_STSf); 7320 break; 7321 7322 case cprimodPmdPortStatusSignalDetected: 7323 *value = soc_reg_field_get(unit, CPMPORT_PMD_PORT_STATUSr, data, 7324 PMD_SIGNAL_DETECT_STSf); 7325 break; 7326 7327 default: 7328 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for PMD Port status.")); 7329 break; 7330 } 7331 7332 exit: 7333 SOC_FUNC_RETURN; 7334 } 7335 7336 int cprif_drv_rx_pcs_status_get(int unit, int port, cprimod_rx_pcs_status_t status, 7337 uint32* value) 7338 { 7339 uint64 data; 7340 uint64 read_val; 7341 SOC_INIT_FUNC_DEFS; 7342 7343 SOC_IF_ERROR_RETURN(READ_CPRI_RXPCS_STATUSr(unit, port, &data)); 7344 switch (status) { 7345 case cprimodRxPcsStatusLinkStatusLive: 7346 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_STATUSr, data, 7347 RXPCS_LINK_STATUS_LIVEf); 7348 *value = COMPILER_64_LO(read_val); 7349 break; 7350 case cprimodRxPcsStatusSeedLocked: 7351 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_STATUSr, data, 7352 RXPCS_SEED_LOCKEDf); 7353 *value = COMPILER_64_LO(read_val); 7354 break; 7355 case cprimodRxPcsStatusSeedVector: 7356 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_STATUSr, data, 7357 RXPCS_SEED_VECTORf); 7358 *value = COMPILER_64_LO(read_val); 7359 break; 7360 case cprimodRxPcsStatusLosLive: 7361 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_STATUSr, data, 7362 RXPCS_LOS_LIVEf); 7363 *value = COMPILER_64_LO(read_val); 7364 break; 7365 case cprimodRxPcsStatus64b66bHiBerLive: 7366 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_STATUSr, data, 7367 RXPCS_64B66B_HI_BER_LIVEf); 7368 *value = COMPILER_64_LO(read_val); 7369 break; 7370 case cprimodRxPcsStatus64b66bBlockLockLive: 7371 read_val = soc_reg64_field_get(unit, CPRI_RXPCS_STATUSr, data, 7372 RXPCS_64B66B_BLOCK_LOCK_LIVEf); 7373 *value = COMPILER_64_LO(read_val); 7374 break; 7375 default: 7376 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config is not supported for rsvd4 Rx overide")); 7377 break; 7378 } 7379 7380 exit: 7381 SOC_FUNC_RETURN; 7382 } 7383 7384 /* 7385 * Functions related to init 7386 */ 7387 7388 int cprif_drv_datapath_credit_reset_set(int unit, int port, int val) 7389 { 7390 uint32 read_val; 7391 SOC_INIT_FUNC_DEFS; 7392 7393 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7394 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, DATAPATH_CREDIT_RSTf, 7395 val); 7396 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7397 7398 SOC_FUNC_RETURN; 7399 } 7400 7401 int cprif_drv_datapath_credit_reset_get(int unit, int port, int* val) 7402 { 7403 uint32 read_val; 7404 SOC_INIT_FUNC_DEFS; 7405 7406 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7407 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, 7408 DATAPATH_CREDIT_RSTf); 7409 7410 SOC_FUNC_RETURN; 7411 } 7412 7413 7414 int cprif_drv_cip_rx_dp_reset_set(int unit, int port, int val) 7415 { 7416 uint32 read_val; 7417 SOC_INIT_FUNC_DEFS; 7418 7419 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7420 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_DPf, val); 7421 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7422 7423 SOC_FUNC_RETURN; 7424 } 7425 7426 int cprif_drv_cip_rx_dp_reset_get(int unit, int port, int* val) 7427 { 7428 uint32 read_val; 7429 SOC_INIT_FUNC_DEFS; 7430 7431 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7432 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_CIP_RX_DPf); 7433 7434 SOC_FUNC_RETURN; 7435 } 7436 7437 7438 int cprif_drv_cip_tx_dp_reset_set(int unit, int port, int val) 7439 { 7440 uint32 read_val; 7441 SOC_INIT_FUNC_DEFS; 7442 7443 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7444 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_TX_DPf, val); 7445 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7446 7447 SOC_FUNC_RETURN; 7448 } 7449 7450 int cprif_drv_cip_tx_dp_reset_get(int unit, int port, int* val) 7451 { 7452 uint32 read_val; 7453 SOC_INIT_FUNC_DEFS; 7454 7455 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7456 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_CIP_TX_DPf); 7457 7458 SOC_FUNC_RETURN; 7459 } 7460 7461 7462 int cprif_drv_cip_tx_h_reset_set(int unit, int port, int val) 7463 { 7464 uint32 read_val; 7465 SOC_INIT_FUNC_DEFS; 7466 7467 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7468 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_TX_Hf, val); 7469 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7470 7471 SOC_FUNC_RETURN; 7472 } 7473 7474 int cprif_drv_cip_tx_h_reset_get(int unit, int port, int* val) 7475 { 7476 uint32 read_val; 7477 SOC_INIT_FUNC_DEFS; 7478 7479 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7480 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_CIP_TX_Hf); 7481 7482 SOC_FUNC_RETURN; 7483 } 7484 7485 7486 int cprif_drv_cip_rx_h_reset_set(int unit, int port, int val) 7487 { 7488 uint32 read_val; 7489 SOC_INIT_FUNC_DEFS; 7490 7491 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7492 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_Hf, val); 7493 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7494 7495 SOC_FUNC_RETURN; 7496 } 7497 7498 int cprif_drv_cip_rx_h_reset_get(int unit, int port, int* val) 7499 { 7500 uint32 read_val; 7501 SOC_INIT_FUNC_DEFS; 7502 7503 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7504 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_CIP_RX_Hf); 7505 7506 SOC_FUNC_RETURN; 7507 } 7508 7509 7510 int cprif_drv_datapath_rx_dp_reset_set(int unit, int port, int val) 7511 { 7512 uint32 read_val; 7513 SOC_INIT_FUNC_DEFS; 7514 7515 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7516 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_RX_DPf, 7517 val); 7518 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7519 7520 SOC_FUNC_RETURN; 7521 } 7522 7523 int cprif_drv_datapath_rx_dp_reset_get(int unit, int port, int* val) 7524 { 7525 uint32 read_val; 7526 SOC_INIT_FUNC_DEFS; 7527 7528 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7529 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, 7530 RESET_DATAPATH_RX_DPf); 7531 7532 SOC_FUNC_RETURN; 7533 } 7534 7535 7536 int cprif_drv_datapath_tx_dp_reset_set(int unit, int port, int val) 7537 { 7538 uint32 read_val; 7539 SOC_INIT_FUNC_DEFS; 7540 7541 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7542 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_TX_DPf, 7543 val); 7544 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7545 7546 SOC_FUNC_RETURN; 7547 } 7548 7549 int cprif_drv_datapath_tx_dp_reset_get(int unit, int port, int* val) 7550 { 7551 uint32 read_val; 7552 SOC_INIT_FUNC_DEFS; 7553 7554 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7555 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, 7556 RESET_DATAPATH_TX_DPf); 7557 7558 SOC_FUNC_RETURN; 7559 } 7560 7561 7562 int cprif_drv_datapath_rx_h_reset_set(int unit, int port, int val) 7563 { 7564 uint32 read_val; 7565 SOC_INIT_FUNC_DEFS; 7566 7567 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7568 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_RX_Hf, 7569 val); 7570 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7571 7572 SOC_FUNC_RETURN; 7573 } 7574 7575 int cprif_drv_datapath_rx_h_reset_get(int unit, int port, int* val) 7576 { 7577 uint32 read_val; 7578 SOC_INIT_FUNC_DEFS; 7579 7580 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7581 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, 7582 RESET_DATAPATH_RX_Hf); 7583 7584 SOC_FUNC_RETURN; 7585 } 7586 7587 7588 int cprif_drv_datapath_tx_h_reset_set(int unit, int port, int val) 7589 { 7590 uint32 read_val; 7591 SOC_INIT_FUNC_DEFS; 7592 7593 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7594 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_TX_Hf, 7595 val); 7596 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7597 7598 SOC_FUNC_RETURN; 7599 } 7600 7601 int cprif_drv_datapath_tx_h_reset_get(int unit, int port, int* val) 7602 { 7603 uint32 read_val; 7604 SOC_INIT_FUNC_DEFS; 7605 7606 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7607 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, 7608 RESET_DATAPATH_TX_Hf); 7609 7610 SOC_FUNC_RETURN; 7611 } 7612 7613 /* 7614 * set Reg_cpri_cpri_rst_ctrl.reset_rx_dp to a particular value. 7615 * Default is 0 (not in reset). 7616 */ 7617 int cprif_drv_rx_dp_reset_set(int unit, int port, int val) 7618 { 7619 uint32 read_val; 7620 SOC_INIT_FUNC_DEFS; 7621 7622 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7623 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_DPf, val); 7624 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7625 7626 SOC_FUNC_RETURN; 7627 } 7628 7629 int cprif_drv_rx_dp_reset_get(int unit, int port, int* val) 7630 { 7631 uint32 read_val; 7632 SOC_INIT_FUNC_DEFS; 7633 7634 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7635 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_RX_DPf); 7636 7637 SOC_FUNC_RETURN; 7638 } 7639 7640 /* 7641 * set Reg_cpri_cpri_rst_ctrl.reset_rx_h to a particular value. 7642 * Default is 0 (not in reset). 7643 */ 7644 int cprif_drv_rx_h_reset_set(int unit, int port, int val) 7645 { 7646 uint32 read_val; 7647 SOC_INIT_FUNC_DEFS; 7648 7649 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7650 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_Hf, val); 7651 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7652 7653 SOC_FUNC_RETURN; 7654 } 7655 7656 int cprif_drv_rx_h_reset_get(int unit, int port, int* val) 7657 { 7658 uint32 read_val; 7659 SOC_INIT_FUNC_DEFS; 7660 7661 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7662 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_RX_Hf); 7663 7664 SOC_FUNC_RETURN; 7665 } 7666 7667 /* 7668 * set Reg_cpri_cpri_rst_ctrl.reset_tx_dp to a particular value. 7669 * Default is 0 (not in reset). 7670 */ 7671 int cprif_drv_tx_dp_reset_set(int unit, int port, int val) 7672 { 7673 uint32 read_val; 7674 SOC_INIT_FUNC_DEFS; 7675 7676 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7677 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_TX_DPf, val); 7678 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7679 7680 SOC_FUNC_RETURN; 7681 } 7682 7683 int cprif_drv_tx_dp_reset_get(int unit, int port, int* val) 7684 { 7685 uint32 read_val; 7686 SOC_INIT_FUNC_DEFS; 7687 7688 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7689 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_TX_DPf); 7690 7691 SOC_FUNC_RETURN; 7692 } 7693 7694 /* 7695 * set Reg_cpri_cpri_rst_ctrl.reset_tx_h to a particular value. 7696 * Default is 0 (not in reset). 7697 */ 7698 int cprif_drv_tx_h_reset_set(int unit, int port, int val) 7699 { 7700 uint32 read_val; 7701 SOC_INIT_FUNC_DEFS; 7702 7703 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7704 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_TX_Hf, val); 7705 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7706 7707 SOC_FUNC_RETURN; 7708 } 7709 7710 int cprif_drv_tx_h_reset_get(int unit, int port, int* val) 7711 { 7712 uint32 read_val; 7713 SOC_INIT_FUNC_DEFS; 7714 7715 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7716 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, RESET_TX_Hf); 7717 7718 SOC_FUNC_RETURN; 7719 } 7720 7721 /* 7722 * set Reg_cpri_cpri_rst_ctrl.glas_rst to a particular value. 7723 * Default is 0 (not in reset). 7724 */ 7725 int cprif_drv_glas_reset_set(int unit, int port, int val) 7726 { 7727 uint32 read_val; 7728 SOC_INIT_FUNC_DEFS; 7729 7730 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7731 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, GLAS_RSTf, val); 7732 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 7733 7734 SOC_FUNC_RETURN; 7735 } 7736 7737 int cprif_drv_glas_reset_get(int unit, int port, int* val) 7738 { 7739 uint32 read_val; 7740 SOC_INIT_FUNC_DEFS; 7741 7742 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 7743 *val = soc_reg_field_get(unit, CPRI_RST_CTRLr, read_val, GLAS_RSTf); 7744 7745 SOC_FUNC_RETURN; 7746 } 7747 7748 /* 7749 * set Reg_cpri_cpri_clk_ctrl.disable_cipclk_clk to a particular value. 7750 * Default is 0 (not gated). 7751 */ 7752 int cprif_drv_disable_cip_clk_set(int unit, int port, int val) 7753 { 7754 uint32 read_val; 7755 SOC_INIT_FUNC_DEFS; 7756 7757 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7758 soc_reg_field_set(unit, CPRI_CLK_CTRLr, &read_val, DISABLE_CIPCLK_CLKf, val); 7759 SOC_IF_ERROR_RETURN(WRITE_CPRI_CLK_CTRLr(unit, port, read_val)); 7760 7761 SOC_FUNC_RETURN; 7762 } 7763 7764 int cprif_drv_disable_cip_clk_get(int unit, int port, int* val) 7765 { 7766 uint32 read_val; 7767 SOC_INIT_FUNC_DEFS; 7768 7769 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7770 *val = soc_reg_field_get(unit, CPRI_CLK_CTRLr, read_val, DISABLE_CIPCLK_CLKf); 7771 7772 SOC_FUNC_RETURN; 7773 } 7774 7775 /* 7776 * set Reg_cpri_cpri_clk_ctrl.disable_glas_clk to a particular value. 7777 * Default is 0 (not gated). 7778 */ 7779 int cprif_drv_disable_glas_clk_set(int unit, int port, int val) 7780 { 7781 uint32 read_val; 7782 SOC_INIT_FUNC_DEFS; 7783 7784 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7785 soc_reg_field_set(unit, CPRI_CLK_CTRLr, &read_val, DISABLE_GLAS_CLKf, val); 7786 SOC_IF_ERROR_RETURN(WRITE_CPRI_CLK_CTRLr(unit, port, read_val)); 7787 7788 SOC_FUNC_RETURN; 7789 } 7790 7791 int cprif_drv_disable_glas_clk_get(int unit, int port, int* val) 7792 { 7793 uint32 read_val; 7794 SOC_INIT_FUNC_DEFS; 7795 7796 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7797 *val = soc_reg_field_get(unit, CPRI_CLK_CTRLr, read_val, DISABLE_GLAS_CLKf); 7798 7799 SOC_FUNC_RETURN; 7800 } 7801 7802 /* 7803 * set Reg_cpri_cpri_clk_ctrl.disable_rx_clk to a particular value. 7804 * Default is 0 (not gated). 7805 */ 7806 int cprif_drv_disable_rx_clk_set(int unit, int port, int val) 7807 { 7808 uint32 read_val; 7809 SOC_INIT_FUNC_DEFS; 7810 7811 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7812 soc_reg_field_set(unit, CPRI_CLK_CTRLr, &read_val, DISABLE_RX_CLKf, val); 7813 SOC_IF_ERROR_RETURN(WRITE_CPRI_CLK_CTRLr(unit, port, read_val)); 7814 7815 SOC_FUNC_RETURN; 7816 } 7817 7818 int cprif_drv_disable_rx_clk_get(int unit, int port, int* val) 7819 { 7820 uint32 read_val; 7821 SOC_INIT_FUNC_DEFS; 7822 7823 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7824 *val = soc_reg_field_get(unit, CPRI_CLK_CTRLr, read_val, DISABLE_RX_CLKf); 7825 7826 SOC_FUNC_RETURN; 7827 } 7828 7829 /* 7830 * set Reg_cpri_cpri_clk_ctrl.disable_tx_clk to a particular value. 7831 * Default is 0 (not gated). 7832 */ 7833 int cprif_drv_disable_tx_clk_set(int unit, int port, int val) 7834 { 7835 uint32 read_val; 7836 SOC_INIT_FUNC_DEFS; 7837 7838 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7839 soc_reg_field_set(unit, CPRI_CLK_CTRLr, &read_val, DISABLE_TX_CLKf, val); 7840 SOC_IF_ERROR_RETURN(WRITE_CPRI_CLK_CTRLr(unit, port, read_val)); 7841 7842 SOC_FUNC_RETURN; 7843 } 7844 7845 int cprif_drv_disable_tx_clk_get(int unit, int port, int* val) 7846 { 7847 uint32 read_val; 7848 SOC_INIT_FUNC_DEFS; 7849 7850 SOC_IF_ERROR_RETURN(READ_CPRI_CLK_CTRLr(unit, port, &read_val)); 7851 *val = soc_reg_field_get(unit, CPRI_CLK_CTRLr, read_val, DISABLE_TX_CLKf); 7852 7853 SOC_FUNC_RETURN; 7854 } 7855 7856 /* 7857 * Programming the cip_clk selection for a port. You could choose cip 7858 * generated from PLL0 or PLL1 7859 */ 7860 int cprif_drv_cip_clk_pll_select_set(int unit, int port, int val) 7861 { 7862 uint32 read_val; 7863 SOC_INIT_FUNC_DEFS; 7864 7865 SOC_IF_ERROR_RETURN(READ_CPRI_CIP_CLK_CTRLr(unit, port, &read_val)); 7866 soc_reg_field_set(unit, CPRI_CIP_CLK_CTRLr, &read_val, 7867 USE_PMD_CIP_CLK_PLL1f,val); 7868 SOC_IF_ERROR_RETURN(WRITE_CPRI_CIP_CLK_CTRLr(unit, port, read_val)); 7869 7870 SOC_FUNC_RETURN; 7871 } 7872 7873 int cprif_drv_cip_clk_pll_select_get(int unit, int port, int* val) 7874 { 7875 uint32 read_val; 7876 SOC_INIT_FUNC_DEFS; 7877 7878 SOC_IF_ERROR_RETURN(READ_CPRI_CIP_CLK_CTRLr(unit, port, &read_val)); 7879 *val = soc_reg_field_get(unit, CPRI_CIP_CLK_CTRLr, read_val, 7880 USE_PMD_CIP_CLK_PLL1f); 7881 7882 SOC_FUNC_RETURN; 7883 } 7884 7885 int cprif_drv_cip_clk_div_ctrl_set(int unit, int port, int val) 7886 { 7887 uint32 read_val; 7888 SOC_INIT_FUNC_DEFS; 7889 7890 SOC_IF_ERROR_RETURN(READ_CPRI_CIP_CLK_CTRLr(unit, port, &read_val)); 7891 soc_reg_field_set(unit, CPRI_CIP_CLK_CTRLr, &read_val, 7892 CIP_CLK_DIV_CTRLf,val); 7893 SOC_IF_ERROR_RETURN(WRITE_CPRI_CIP_CLK_CTRLr(unit, port, read_val)); 7894 7895 SOC_FUNC_RETURN; 7896 } 7897 7898 int cprif_drv_cip_clk_div_ctrl_get(int unit, int port, int* val) 7899 { 7900 uint32 read_val; 7901 SOC_INIT_FUNC_DEFS; 7902 7903 SOC_IF_ERROR_RETURN(READ_CPRI_CIP_CLK_CTRLr(unit, port, &read_val)); 7904 *val = soc_reg_field_get(unit, CPRI_CIP_CLK_CTRLr, read_val, 7905 CIP_CLK_DIV_CTRLf); 7906 7907 SOC_FUNC_RETURN; 7908 } 7909 7910 int cprif_drv_tx_flush_set(int unit, int port, int val) 7911 { 7912 uint32 read_val; 7913 SOC_INIT_FUNC_DEFS; 7914 7915 SOC_IF_ERROR_RETURN(READ_CPRI_TX_CTRLr(unit, port, &read_val)); 7916 soc_reg_field_set(unit, CPRI_TX_CTRLr, &read_val, TX_FLUSHf, val); 7917 SOC_IF_ERROR_RETURN(WRITE_CPRI_TX_CTRLr(unit, port, read_val)); 7918 7919 SOC_FUNC_RETURN; 7920 } 7921 7922 int cprif_drv_tx_flush_get(int unit, int port, int* val) 7923 { 7924 uint32 read_val; 7925 SOC_INIT_FUNC_DEFS; 7926 7927 SOC_IF_ERROR_RETURN(READ_CPRI_TX_CTRLr(unit, port, &read_val)); 7928 *val = soc_reg_field_get(unit, CPRI_TX_CTRLr, read_val, TX_FLUSHf); 7929 7930 SOC_FUNC_RETURN; 7931 } 7932 7933 int cprif_drv_rx_disable_set(int unit, int port, int val) 7934 { 7935 uint32 read_val; 7936 SOC_INIT_FUNC_DEFS; 7937 7938 SOC_IF_ERROR_RETURN(READ_CPRI_RX_CTRLr(unit, port, &read_val)); 7939 soc_reg_field_set(unit, CPRI_RX_CTRLr, &read_val, RX_DISABLEf, val); 7940 SOC_IF_ERROR_RETURN(WRITE_CPRI_RX_CTRLr(unit, port, read_val)); 7941 7942 SOC_FUNC_RETURN; 7943 } 7944 7945 int cprif_drv_rx_disable_get(int unit, int port, int* val) 7946 { 7947 uint32 read_val; 7948 SOC_INIT_FUNC_DEFS; 7949 7950 SOC_IF_ERROR_RETURN(READ_CPRI_RX_CTRLr(unit, port, &read_val)); 7951 *val = soc_reg_field_get(unit, CPRI_RX_CTRLr, read_val, RX_DISABLEf); 7952 7953 SOC_FUNC_RETURN; 7954 } 7955 7956 7957 int cprif_drv_cpri_or_enet_port_set(int unit, int port, int val) 7958 { 7959 uint32 read_val; 7960 SOC_INIT_FUNC_DEFS; 7961 7962 read_val = 0; 7963 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_LANE_CTRLr(unit, port, &read_val)); 7964 soc_reg_field_set(unit, CPMPORT_TOP_LANE_CTRLr, &read_val, 7965 LOGICAL_LANE_OWNERf, val); 7966 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_LANE_CTRLr(unit, port, read_val)); 7967 7968 SOC_FUNC_RETURN; 7969 } 7970 7971 int cprif_drv_cpri_or_enet_port_get(int unit, int port, int* val) 7972 { 7973 uint32 read_val; 7974 SOC_INIT_FUNC_DEFS; 7975 7976 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_LANE_CTRLr(unit, port, &read_val)); 7977 *val = soc_reg_field_get(unit, CPMPORT_TOP_LANE_CTRLr, read_val, 7978 LOGICAL_LANE_OWNERf); 7979 7980 SOC_FUNC_RETURN; 7981 } 7982 7983 int cprif_drv_cip_top_ctrl_set(int unit, int port, int val) 7984 { 7985 uint32 data; 7986 SOC_INIT_FUNC_DEFS; 7987 7988 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 7989 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_TOP_CTRLf, val); 7990 SOC_IF_ERROR_RETURN(WRITE_TOP_CTRL_CONFIGr(unit, port, data)); 7991 7992 SOC_FUNC_RETURN; 7993 } 7994 7995 int cprif_drv_cip_top_ctrl_get(int unit, int port, int *val) 7996 { 7997 uint32 data; 7998 SOC_INIT_FUNC_DEFS; 7999 8000 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 8001 *val = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, CIP_TOP_CTRLf); 8002 8003 SOC_FUNC_RETURN; 8004 } 8005 8006 int cprif_drv_pmd_iddq_set(int unit, int port, int val) 8007 { 8008 uint32 data; 8009 SOC_INIT_FUNC_DEFS; 8010 8011 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 8012 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, PMD_IDDQf, val); 8013 SOC_IF_ERROR_RETURN(WRITE_TOP_CTRL_CONFIGr(unit, port, data)); 8014 8015 SOC_FUNC_RETURN; 8016 } 8017 8018 int cprif_drv_pmd_iddq_get(int unit, int port, int *val) 8019 { 8020 uint32 data; 8021 SOC_INIT_FUNC_DEFS; 8022 8023 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 8024 *val = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, PMD_IDDQf); 8025 8026 SOC_FUNC_RETURN; 8027 } 8028 8029 int cprif_drv_top_ctrl_config_pll_ctrl_set(int unit, int port, int pll_num, int cip_pll_ctrl) 8030 { 8031 uint32 data; 8032 SOC_INIT_FUNC_DEFS; 8033 8034 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 8035 if (pll_num == 0) { 8036 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL0_CTRLf, cip_pll_ctrl); 8037 } 8038 if (pll_num == 1) { 8039 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL1_CTRLf, cip_pll_ctrl); 8040 } 8041 SOC_IF_ERROR_RETURN(WRITE_TOP_CTRL_CONFIGr(unit, port, data)); 8042 8043 SOC_FUNC_RETURN; 8044 } 8045 8046 int cprif_drv_top_ctrl_config_pll_ctrl_get(int unit, int port, int pll_num, int *cip_pll_ctrl) 8047 { 8048 uint32 data; 8049 SOC_INIT_FUNC_DEFS; 8050 8051 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 8052 if (pll_num == 0) { 8053 *cip_pll_ctrl = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, CIP_PLL0_CTRLf); 8054 } 8055 if (pll_num == 1) { 8056 *cip_pll_ctrl = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, CIP_PLL1_CTRLf); 8057 } 8058 8059 SOC_FUNC_RETURN; 8060 } 8061 8062 int cprif_drv_top_ctrl_config_ref_clk_ctrl_set(int unit, int port, int pll_num, int refin, int refout) 8063 { 8064 uint32 data; 8065 SOC_INIT_FUNC_DEFS; 8066 8067 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 8068 if (pll_num == 0) { 8069 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, PLL0_REFIN_ENf, refin); 8070 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, PLL0_REFOUT_ENf, refout); 8071 } 8072 if (pll_num == 1) { 8073 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, PLL1_REFIN_ENf, refin); 8074 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, PLL1_REFOUT_ENf, refout); 8075 } 8076 SOC_IF_ERROR_RETURN(WRITE_TOP_CTRL_CONFIGr(unit, port, data)); 8077 8078 SOC_FUNC_RETURN; 8079 } 8080 8081 int cprif_drv_top_ctrl_config_ref_clk_ctrl_get(int unit, int port, int pll_num, int *refin, int *refout) 8082 { 8083 uint32 data; 8084 SOC_INIT_FUNC_DEFS; 8085 8086 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 8087 if (pll_num == 0) { 8088 *refin = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, PLL0_REFIN_ENf); 8089 *refout = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, PLL0_REFOUT_ENf); 8090 } 8091 if (pll_num == 1) { 8092 *refin = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, PLL1_REFIN_ENf); 8093 *refout = soc_reg_field_get(unit, TOP_CTRL_CONFIGr, data, PLL1_REFOUT_ENf); 8094 } 8095 8096 SOC_FUNC_RETURN; 8097 } 8098 8099 int cprif_drv_pmd_ctrl_ln_por_h_rstb_set(int unit, int port) 8100 { 8101 uint32 data; 8102 SOC_INIT_FUNC_DEFS; 8103 8104 SOC_IF_ERROR_RETURN(READ_CPRI_PMD_TX_RST_CTRLr(unit, port, &data)); 8105 soc_reg_field_set(unit, CPRI_PMD_TX_RST_CTRLr, &data, PMD_LN_TX_DP_H_RSTBf, 1); 8106 soc_reg_field_set(unit, CPRI_PMD_TX_RST_CTRLr, &data, PMD_LN_TX_H_RSTBf, 1); 8107 soc_reg_field_set(unit, CPRI_PMD_TX_RST_CTRLr, &data, PMD_LN_TX_H_PWRDNf, 0); 8108 SOC_IF_ERROR_RETURN(WRITE_CPRI_PMD_TX_RST_CTRLr(unit, port, data)); 8109 8110 SOC_IF_ERROR_RETURN(READ_CPRI_PMD_RX_RST_CTRLr(unit, port, &data)); 8111 soc_reg_field_set(unit, CPRI_PMD_RX_RST_CTRLr, &data, PMD_LN_RX_DP_H_RSTBf, 1); 8112 soc_reg_field_set(unit, CPRI_PMD_RX_RST_CTRLr, &data, PMD_LN_RX_H_RSTBf, 1); 8113 soc_reg_field_set(unit, CPRI_PMD_RX_RST_CTRLr, &data, PMD_LN_RX_H_PWRDNf, 0); 8114 SOC_IF_ERROR_RETURN(WRITE_CPRI_PMD_RX_RST_CTRLr(unit, port, data)); 8115 SOC_FUNC_RETURN; 8116 } 8117 8118 int cprif_drv_pmd_ctrl_por_h_rstb_set(int unit, int port, int por_h_rstb) 8119 { 8120 uint32 data; 8121 SOC_INIT_FUNC_DEFS; 8122 8123 SOC_IF_ERROR_RETURN(READ_CPMPORT_PMD_CTRLr(unit, port, &data)); 8124 soc_reg_field_set(unit, CPMPORT_PMD_CTRLr, &data, PMD_POR_H_RSTBf, por_h_rstb); 8125 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_PMD_CTRLr(unit, port, data)); 8126 8127 SOC_FUNC_RETURN; 8128 } 8129 8130 int cprif_drv_pmd_ctrl_por_h_rstb_get(int unit, int port, int *por_h_rstb) 8131 { 8132 uint32 data; 8133 SOC_INIT_FUNC_DEFS; 8134 8135 SOC_IF_ERROR_RETURN(READ_CPMPORT_PMD_CTRLr(unit, port, &data)); 8136 *por_h_rstb = soc_reg_field_get(unit, CPMPORT_PMD_CTRLr, data, PMD_POR_H_RSTBf); 8137 8138 SOC_FUNC_RETURN; 8139 } 8140 8141 int cprif_drv_pmd_core_datapath_hard_reset_set(int unit, int port, int pll_num, int rst) 8142 { 8143 uint32 data; 8144 SOC_INIT_FUNC_DEFS; 8145 8146 SOC_IF_ERROR_RETURN(READ_CPMPORT_PMD_CTRLr(unit, port, &data)); 8147 if (pll_num==0) { 8148 soc_reg_field_set(unit, CPMPORT_PMD_CTRLr, &data, PMD_CORE_PLL0_DP_H_RSTBf, rst); 8149 } 8150 if (pll_num==1) { 8151 soc_reg_field_set(unit, CPMPORT_PMD_CTRLr, &data, PMD_CORE_PLL1_DP_H_RSTBf, rst); 8152 } 8153 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_PMD_CTRLr(unit, port, data)); 8154 8155 SOC_FUNC_RETURN; 8156 } 8157 8158 int cprif_drv_pmd_core_datapath_hard_reset_get(int unit, int port, int pll_num, int *rst) 8159 { 8160 uint32 data; 8161 SOC_INIT_FUNC_DEFS; 8162 8163 SOC_IF_ERROR_RETURN(READ_CPMPORT_PMD_CTRLr(unit, port, &data)); 8164 if (pll_num==0) { 8165 *rst = soc_reg_field_get(unit, CPMPORT_PMD_CTRLr, data, PMD_CORE_PLL0_DP_H_RSTBf); 8166 } 8167 if (pll_num==1) { 8168 *rst = soc_reg_field_get(unit, CPMPORT_PMD_CTRLr, data, PMD_CORE_PLL1_DP_H_RSTBf); 8169 } 8170 8171 SOC_FUNC_RETURN; 8172 } 8173 8174 int cprif_drv_cpmport_pll_ctrl_config_set(int unit, int port, int pll_num, int lcref_sel) 8175 { 8176 uint32 data; 8177 SOC_INIT_FUNC_DEFS; 8178 8179 if (pll_num == 0) { 8180 SOC_IF_ERROR_RETURN(READ_CPMPORT_PLL0_CTRL_CONFIGr(unit, port, &data)); 8181 soc_reg_field_set(unit, CPMPORT_PLL0_CTRL_CONFIGr, &data, LCREF_SELf, lcref_sel); 8182 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_PLL0_CTRL_CONFIGr(unit, port, data)); 8183 } 8184 if (pll_num == 1) { 8185 SOC_IF_ERROR_RETURN(READ_CPMPORT_PLL1_CTRL_CONFIGr(unit, port, &data)); 8186 soc_reg_field_set(unit, CPMPORT_PLL1_CTRL_CONFIGr, &data, LCREF_SELf, lcref_sel); 8187 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_PLL1_CTRL_CONFIGr(unit, port, data)); 8188 } 8189 8190 SOC_FUNC_RETURN; 8191 } 8192 8193 int cprif_drv_cpmport_pll_ctrl_config_get(int unit, int port, int pll_num, int *lcref_sel) 8194 { 8195 uint32 data; 8196 SOC_INIT_FUNC_DEFS; 8197 8198 if (pll_num == 0) { 8199 SOC_IF_ERROR_RETURN(READ_CPMPORT_PLL0_CTRL_CONFIGr(unit, port, &data)); 8200 *lcref_sel = soc_reg_field_get(unit, CPMPORT_PLL0_CTRL_CONFIGr, data, LCREF_SELf); 8201 } 8202 if (pll_num == 1) { 8203 SOC_IF_ERROR_RETURN(READ_CPMPORT_PLL1_CTRL_CONFIGr(unit, port, &data)); 8204 *lcref_sel = soc_reg_field_get(unit, CPMPORT_PLL1_CTRL_CONFIGr, data, LCREF_SELf); 8205 } 8206 8207 SOC_FUNC_RETURN; 8208 } 8209 8210 int cprif_drv_lane_swap_set(int unit, int port, int lane, cprimod_direction_t dir, 8211 int phyport) 8212 { 8213 uint32 data; 8214 SOC_INIT_FUNC_DEFS; 8215 8216 data = 0; 8217 if (dir == CPRIMOD_DIR_RX) { 8218 switch (lane) { 8219 case 0: 8220 soc_reg_field_set(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_0r, &data, 8221 RX_LOG_PHY_MAPf, phyport); 8222 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_RX_PHY_LANE_CTRL_0r(unit, port, data)); 8223 break; 8224 case 1: 8225 soc_reg_field_set(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_1r, &data, 8226 RX_LOG_PHY_MAPf, phyport); 8227 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_RX_PHY_LANE_CTRL_1r(unit, port, data)); 8228 break; 8229 case 2: 8230 soc_reg_field_set(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_2r, &data, 8231 RX_LOG_PHY_MAPf, phyport); 8232 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_RX_PHY_LANE_CTRL_2r(unit, port, data)); 8233 break; 8234 case 3: 8235 soc_reg_field_set(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_3r, &data, 8236 RX_LOG_PHY_MAPf, phyport); 8237 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_RX_PHY_LANE_CTRL_3r(unit, port, data)); 8238 break; 8239 default: 8240 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Wrong logical port number")); 8241 break; 8242 } 8243 } else { 8244 switch (lane) { 8245 case 0: 8246 soc_reg_field_set(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_0r, &data, 8247 TX_LOG_PHY_MAPf, phyport); 8248 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_TX_PHY_LANE_CTRL_0r(unit, port, data)); 8249 break; 8250 case 1: 8251 soc_reg_field_set(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_1r, &data, 8252 TX_LOG_PHY_MAPf, phyport); 8253 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_TX_PHY_LANE_CTRL_1r(unit, port, data)); 8254 break; 8255 case 2: 8256 soc_reg_field_set(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_2r, &data, 8257 TX_LOG_PHY_MAPf, phyport); 8258 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_TX_PHY_LANE_CTRL_2r(unit, port, data)); 8259 break; 8260 case 3: 8261 soc_reg_field_set(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_3r, &data, 8262 TX_LOG_PHY_MAPf, phyport); 8263 SOC_IF_ERROR_RETURN(WRITE_CPMPORT_TOP_TX_PHY_LANE_CTRL_3r(unit, port, data)); 8264 break; 8265 default: 8266 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Wrong logical port number")); 8267 break; 8268 } 8269 } 8270 8271 exit: 8272 SOC_FUNC_RETURN; 8273 } 8274 8275 int cprif_drv_lane_swap_get(int unit, int port, int lane, cprimod_direction_t dir, 8276 int *phyport) 8277 { 8278 uint32 data; 8279 SOC_INIT_FUNC_DEFS; 8280 8281 if (dir == CPRIMOD_DIR_RX) { 8282 switch (lane) { 8283 case 0: 8284 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_RX_PHY_LANE_CTRL_0r(unit, port, &data)); 8285 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_0r, 8286 data, RX_LOG_PHY_MAPf); 8287 break; 8288 case 1: 8289 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_RX_PHY_LANE_CTRL_1r(unit, port, &data)); 8290 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_1r, 8291 data, RX_LOG_PHY_MAPf); 8292 break; 8293 case 2: 8294 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_RX_PHY_LANE_CTRL_2r(unit, port, &data)); 8295 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_2r, 8296 data, RX_LOG_PHY_MAPf); 8297 break; 8298 case 3: 8299 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_RX_PHY_LANE_CTRL_3r(unit, port, &data)); 8300 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_RX_PHY_LANE_CTRL_3r, 8301 data, RX_LOG_PHY_MAPf); 8302 break; 8303 default: 8304 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Wrong logical port number")); 8305 break; 8306 } 8307 } else { 8308 switch (lane) { 8309 case 0: 8310 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_TX_PHY_LANE_CTRL_0r(unit, port, &data)); 8311 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_0r, 8312 data, TX_LOG_PHY_MAPf); 8313 break; 8314 case 1: 8315 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_TX_PHY_LANE_CTRL_1r(unit, port, &data)); 8316 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_1r, 8317 data, TX_LOG_PHY_MAPf); 8318 break; 8319 case 2: 8320 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_TX_PHY_LANE_CTRL_2r(unit, port, &data)); 8321 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_2r, 8322 data, TX_LOG_PHY_MAPf); 8323 break; 8324 case 3: 8325 SOC_IF_ERROR_RETURN(READ_CPMPORT_TOP_TX_PHY_LANE_CTRL_3r(unit, port, &data)); 8326 *phyport = soc_reg_field_get(unit, CPMPORT_TOP_TX_PHY_LANE_CTRL_3r, 8327 data, TX_LOG_PHY_MAPf); 8328 break; 8329 default: 8330 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Wrong logical port number")); 8331 break; 8332 } 8333 } 8334 8335 exit: 8336 SOC_FUNC_RETURN; 8337 } 8338 8339 int cprif_drv_rsvd4_rx_master_frame_sync_config_set(int unit, int port, 8340 uint32 master_frame_number, 8341 uint64 master_frame_start_time) 8342 { 8343 uint64 reg_val; 8344 uint64 field_buf; 8345 SOC_INIT_FUNC_DEFS; 8346 8347 COMPILER_64_SET(field_buf,0,master_frame_number); 8348 _SOC_IF_ERR_EXIT 8349 (READ_BRCM_RESERVED_CPM_317r(unit, port, ®_val)); 8350 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_317r, ®_val, BRCM_RESERVED_CPM_317_0f, field_buf); 8351 8352 COMPILER_64_COPY(field_buf,master_frame_start_time); 8353 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_317r, ®_val, BRCM_RESERVED_CPM_317_1f, field_buf); 8354 8355 _SOC_IF_ERR_EXIT 8356 (WRITE_BRCM_RESERVED_CPM_317r(unit, port, reg_val)); 8357 8358 exit: 8359 8360 SOC_FUNC_RETURN; 8361 } 8362 8363 int cprif_drv_rsvd4_rx_master_frame_sync_config_get(int unit, int port, 8364 uint32* master_frame_number, 8365 uint64* master_frame_start_time) 8366 { 8367 uint64 reg_val; 8368 uint64 field_buf; 8369 SOC_INIT_FUNC_DEFS; 8370 8371 _SOC_IF_ERR_EXIT 8372 (READ_BRCM_RESERVED_CPM_317r(unit, port, ®_val)); 8373 8374 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_317r, reg_val, BRCM_RESERVED_CPM_317_1f); 8375 COMPILER_64_TO_32_LO(*master_frame_number,field_buf); 8376 8377 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_317r, reg_val, BRCM_RESERVED_CPM_317_0f); 8378 COMPILER_64_COPY(*master_frame_start_time,field_buf); 8379 8380 exit: 8381 SOC_FUNC_RETURN; 8382 } 8383 8384 int cprif_drv_rx_control_word_status_get(int unit, int port, cprif_drv_rx_control_word_status_t* info) 8385 { 8386 uint64 reg_val; 8387 uint64 field_buf; 8388 8389 SOC_IF_ERROR_RETURN 8390 (READ_CPRI_RXFRM_CPRSR_STATUSr(unit, port, ®_val)); 8391 8392 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_HFNf); 8393 COMPILER_64_TO_32_LO(info->hyper_frame,field_buf); 8394 8395 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_BFNf); 8396 COMPILER_64_TO_32_LO(info->radio_frame,field_buf); 8397 8398 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_FNf); 8399 COMPILER_64_TO_32_LO(info->basic_frame,field_buf); 8400 8401 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_HDLC_RATEf); 8402 COMPILER_64_TO_32_LO(info->hdlc_rate,field_buf); 8403 8404 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_PROT_VERf); 8405 COMPILER_64_TO_32_LO(info->protocol_ver,field_buf); 8406 8407 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_ETH_PTRf); 8408 COMPILER_64_TO_32_LO(info->eth_pointer,field_buf); 8409 8410 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_L1_RESETf); 8411 COMPILER_64_TO_32_LO(info->reset,field_buf); 8412 8413 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_L1_RAIf); 8414 COMPILER_64_TO_32_LO(info->l1_rai,field_buf); 8415 8416 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_L1_SDIf); 8417 COMPILER_64_TO_32_LO(info->l1_sdi,field_buf); 8418 8419 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_L1_LOSf); 8420 COMPILER_64_TO_32_LO(info->l1_los,field_buf); 8421 8422 field_buf = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_STATUSr, reg_val, RXFRM_L1_LOFf); 8423 COMPILER_64_TO_32_LO(info->l1_lof,field_buf); 8424 8425 return SOC_E_NONE; 8426 } 8427 8428 int cprif_drv_cpri_rx_l1_signal_signal_protection_set(int unit, int port, uint32 signal_map, uint32 enable) 8429 { 8430 uint64 reg_val, tmp_en; 8431 8432 SOC_IF_ERROR_RETURN 8433 (READ_CPRI_RXFRM_CPRSR_CTRLr(unit, port, ®_val)); 8434 8435 if (enable != 0) { 8436 COMPILER_64_SET(tmp_en, 0, 1); 8437 } else { 8438 COMPILER_64_SET(tmp_en, 0, 0); 8439 } 8440 8441 if (CPRIMOD_L1_SIGNAL_LOF_GET(signal_map)) { 8442 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_LOFf, tmp_en ); 8443 } 8444 8445 if (CPRIMOD_L1_SIGNAL_LOS_GET(signal_map)) { 8446 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_LOSf, tmp_en ); 8447 } 8448 8449 if (CPRIMOD_L1_SIGNAL_SDI_GET(signal_map)) { 8450 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_SDIf, tmp_en ); 8451 } 8452 8453 if (CPRIMOD_L1_SIGNAL_RAI_GET(signal_map)) { 8454 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_RAIf, tmp_en ); 8455 } 8456 8457 if (CPRIMOD_L1_SIGNAL_RESET_GET(signal_map)) { 8458 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_RESETf, tmp_en ); 8459 } 8460 8461 if (CPRIMOD_L1_SIGNAL_ETH_PTR_GET(signal_map)) { 8462 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_ETH_PTRf, tmp_en ); 8463 } 8464 8465 if (CPRIMOD_L1_SIGNAL_HDLC_RATE_GET(signal_map)) { 8466 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_HDLC_RATEf, tmp_en ); 8467 } 8468 8469 if (CPRIMOD_L1_SIGNAL_PROT_VER_GET(signal_map)) { 8470 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HW_SIG_PROTECT_PROT_VERf, tmp_en ); 8471 } 8472 8473 SOC_IF_ERROR_RETURN 8474 (WRITE_CPRI_RXFRM_CPRSR_CTRLr(unit, port, reg_val)); 8475 8476 return SOC_E_NONE; 8477 } 8478 8479 int cprif_drv_cpri_rx_l1_signal_signal_protection_get(int unit, int port, uint32 signal_map, uint32* enable) 8480 { 8481 uint64 reg_val, ret_val64; 8482 8483 *enable = 0; 8484 SOC_IF_ERROR_RETURN 8485 (READ_CPRI_RXFRM_CPRSR_CTRLr(unit, port, ®_val)); 8486 8487 if (CPRIMOD_L1_SIGNAL_LOF_GET(signal_map)) { 8488 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_LOFf); 8489 if (!COMPILER_64_IS_ZERO(ret_val64) ) { 8490 CPRIMOD_L1_SIGNAL_LOF_SET(*enable); 8491 } 8492 } 8493 8494 if (CPRIMOD_L1_SIGNAL_LOS_GET(signal_map)) { 8495 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_LOSf); 8496 if (!COMPILER_64_IS_ZERO(ret_val64)) { 8497 CPRIMOD_L1_SIGNAL_LOS_SET(*enable); 8498 } 8499 } 8500 8501 if (CPRIMOD_L1_SIGNAL_SDI_GET(signal_map)) { 8502 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_SDIf); 8503 if (!COMPILER_64_IS_ZERO(ret_val64)) { 8504 CPRIMOD_L1_SIGNAL_SDI_SET(*enable); 8505 } 8506 } 8507 8508 if (CPRIMOD_L1_SIGNAL_RAI_GET(signal_map)) { 8509 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_RAIf); 8510 if (!COMPILER_64_IS_ZERO(ret_val64)) { 8511 CPRIMOD_L1_SIGNAL_RAI_SET(*enable); 8512 } 8513 } 8514 8515 if (CPRIMOD_L1_SIGNAL_RESET_GET(signal_map)) { 8516 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_RESETf); 8517 if (!COMPILER_64_IS_ZERO(ret_val64)) { 8518 CPRIMOD_L1_SIGNAL_RESET_SET(*enable); 8519 } 8520 } 8521 8522 if (CPRIMOD_L1_SIGNAL_ETH_PTR_GET(signal_map)) { 8523 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_ETH_PTRf); 8524 if (!COMPILER_64_IS_ZERO(ret_val64)) { 8525 CPRIMOD_L1_SIGNAL_ETH_PTR_SET(*enable); 8526 } 8527 } 8528 8529 if (CPRIMOD_L1_SIGNAL_HDLC_RATE_GET(signal_map)) { 8530 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_HDLC_RATEf); 8531 if (!COMPILER_64_IS_ZERO(ret_val64)) { 8532 CPRIMOD_L1_SIGNAL_HDLC_RATE_SET(*enable); 8533 } 8534 } 8535 8536 if (CPRIMOD_L1_SIGNAL_PROT_VER_GET(signal_map)) { 8537 ret_val64 = soc_reg64_field_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HW_SIG_PROTECT_PROT_VERf); 8538 if (!COMPILER_64_IS_ZERO(ret_val64)) { 8539 CPRIMOD_L1_SIGNAL_PROT_VER_SET(*enable); 8540 } 8541 } 8542 8543 return SOC_E_NONE; 8544 } 8545 8546 int cprif_drv_cpri_port_rx_cw_slow_hdlc_config_set(int unit, int port, cprif_cpri_rx_hdlc_config_t* config_info) 8547 { 8548 uint64 reg_val, val64; 8549 8550 SOC_IF_ERROR_RETURN 8551 (READ_CPRI_RXFRM_CPRSR_CTRLr(unit, port, ®_val)); 8552 /* 8553 *Need to pass uint64 to soc_reg64_field_set; 8554 *Use COMPILER_64_SET to create one 8555 */ 8556 COMPILER_64_SET(val64, 0, config_info->cw_size); 8557 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HDLC_CW_SIZEf, val64); 8558 8559 COMPILER_64_SET(val64, 0, config_info->cw_sel); 8560 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, ®_val, RXFRM_HDLC_CW_SELf, val64); 8561 8562 SOC_IF_ERROR_RETURN 8563 (WRITE_CPRI_RXFRM_CPRSR_CTRLr(unit, port, reg_val)); 8564 8565 SOC_IF_ERROR_RETURN 8566 (READ_CPRI_RX_HDLC_CTRLr(unit, port, ®_val)); 8567 8568 COMPILER_64_SET(val64, 0, config_info->ignore_fcs_err); 8569 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_IGNORE_FCS_ERRf, val64); 8570 COMPILER_64_SET(val64, 0, config_info->fcs_size); 8571 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_FCS_SIZEf, val64); 8572 COMPILER_64_SET(val64, 0, config_info->runt_frame_drop); 8573 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_RUNT_FRAME_DROPf, val64); 8574 COMPILER_64_SET(val64, 0, config_info->min_frame_size); 8575 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_MIN_FRAME_SIZEf, val64); 8576 COMPILER_64_SET(val64, 0, config_info->long_frame_drop); 8577 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_LONG_FRAME_DROPf, val64); 8578 COMPILER_64_SET(val64, 0, config_info->max_frame_size); 8579 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_MAX_FRAME_SIZEf, val64); 8580 COMPILER_64_SET(val64, 0, config_info->use_fe_mac); 8581 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_USE_FE_MACf, val64); 8582 COMPILER_64_SET(val64, 0, config_info->queue_num); 8583 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_QUEUE_NUMf, val64); 8584 COMPILER_64_SET(val64, 0, config_info->crc_byte_swap); 8585 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_CRC_BYTE_ORDERf, val64); 8586 COMPILER_64_SET(val64, 0, config_info->crc_init_val); 8587 soc_reg64_field_set(unit, CPRI_RX_HDLC_CTRLr, ®_val, RX_HDLC_CRC_INIT_VALf, val64); 8588 8589 SOC_IF_ERROR_RETURN 8590 (WRITE_CPRI_RX_HDLC_CTRLr(unit, port, reg_val)); 8591 return SOC_E_NONE; 8592 } 8593 8594 int cprif_drv_cpri_port_rx_cw_slow_hdlc_config_get(int unit, int port, cprif_cpri_rx_hdlc_config_t* config_info) 8595 { 8596 uint64 reg_val; 8597 8598 SOC_IF_ERROR_RETURN 8599 (READ_CPRI_RXFRM_CPRSR_CTRLr(unit, port, ®_val)); 8600 8601 config_info->cw_size = soc_reg64_field32_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HDLC_CW_SIZEf); 8602 config_info->cw_sel = soc_reg64_field32_get(unit, CPRI_RXFRM_CPRSR_CTRLr, reg_val, RXFRM_HDLC_CW_SELf); 8603 8604 SOC_IF_ERROR_RETURN 8605 (READ_CPRI_RX_HDLC_CTRLr(unit, port, ®_val)); 8606 8607 config_info->ignore_fcs_err = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_IGNORE_FCS_ERRf); 8608 config_info->fcs_size = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_FCS_SIZEf); 8609 config_info->runt_frame_drop = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_RUNT_FRAME_DROPf); 8610 config_info->min_frame_size = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_MIN_FRAME_SIZEf); 8611 config_info->long_frame_drop = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_LONG_FRAME_DROPf); 8612 config_info->max_frame_size = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_MAX_FRAME_SIZEf); 8613 config_info->use_fe_mac = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_USE_FE_MACf); 8614 config_info->queue_num = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_QUEUE_NUMf); 8615 config_info->crc_byte_swap = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_CRC_BYTE_ORDERf); 8616 config_info->crc_init_val = soc_reg64_field32_get(unit, CPRI_RX_HDLC_CTRLr, reg_val, RX_HDLC_CRC_INIT_VALf); 8617 8618 return SOC_E_NONE; 8619 } 8620 int cprif_drv_cpri_port_tx_cw_slow_hdlc_config_set(int unit, int port, cprif_cpri_tx_hdlc_config_t* config_info) 8621 { 8622 uint32 reg_val; 8623 8624 SOC_IF_ERROR_RETURN 8625 (READ_CPRI_TX_HDLC_CTRLr(unit, port, ®_val)); 8626 8627 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_CRC_MODEf, config_info->crc_mode); 8628 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_CW_SELf, config_info->cw_sel); 8629 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_CW_SIZEf, config_info->cw_size); 8630 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_FCS_SIZEf, config_info->fcs_size); 8631 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_MIN_FLAGf, config_info->flag_size); 8632 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_USE_FE_MACf, config_info->use_fe_mac); 8633 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_QUEUE_NUMf, config_info->queue_num); 8634 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_CRC_BYTE_ORDERf, config_info->crc_byte_swap); 8635 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_CRC_INIT_VALf, config_info->crc_init_val); 8636 soc_reg_field_set(unit, CPRI_TX_HDLC_CTRLr, ®_val, TX_HDLC_FILLING_FLAG_SELf, config_info->filling_flag_pattern); 8637 8638 SOC_IF_ERROR_RETURN 8639 (WRITE_CPRI_TX_HDLC_CTRLr(unit, port, reg_val)); 8640 return SOC_E_NONE; 8641 8642 } 8643 8644 int cprif_drv_cpri_port_tx_cw_slow_hdlc_config_get(int unit, int port, cprif_cpri_tx_hdlc_config_t* config_info) 8645 { 8646 uint32 reg_val; 8647 8648 SOC_IF_ERROR_RETURN 8649 (READ_CPRI_TX_HDLC_CTRLr(unit, port, ®_val)); 8650 8651 config_info->crc_mode = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_CRC_MODEf); 8652 config_info->cw_sel = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_CW_SELf); 8653 config_info->cw_size = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_CW_SIZEf); 8654 config_info->fcs_size = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_FCS_SIZEf); 8655 config_info->flag_size = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_MIN_FLAGf); 8656 config_info->use_fe_mac = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_USE_FE_MACf); 8657 config_info->queue_num = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_QUEUE_NUMf); 8658 config_info->crc_byte_swap = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_CRC_BYTE_ORDERf); 8659 config_info->crc_init_val = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_CRC_INIT_VALf); 8660 config_info->filling_flag_pattern = soc_reg_field_get(unit, CPRI_TX_HDLC_CTRLr, reg_val, TX_HDLC_FILLING_FLAG_SELf); 8661 8662 return SOC_E_NONE; 8663 8664 } 8665 int cprif_drv_cpri_port_rx_cw_fast_eth_word_config_set(int unit, int port, cprif_cpri_rx_fast_eth_word_config_t* config_info) 8666 { 8667 uint64 rxfrm_cprsr, val64; 8668 8669 SOC_IF_ERROR_RETURN 8670 (READ_CPRI_RXFRM_CPRSR_CTRLr(unit, port, &rxfrm_cprsr)); 8671 8672 COMPILER_64_SET(val64, 0, config_info->sub_channel_start); 8673 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, &rxfrm_cprsr, RXFRM_ETH_SCHAN_STARTf, val64); 8674 COMPILER_64_SET(val64, 0, config_info->sub_channel_size); 8675 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, &rxfrm_cprsr, RXFRM_ETH_SCHAN_SIZEf, val64); 8676 COMPILER_64_SET(val64, 0, config_info->cw_sel); 8677 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, &rxfrm_cprsr, RXFRM_ETH_CW_SELf, val64); 8678 COMPILER_64_SET(val64, 0, config_info->cw_size); 8679 soc_reg64_field_set(unit, CPRI_RXFRM_CPRSR_CTRLr, &rxfrm_cprsr, RXFRM_ETH_CW_SIZEf, val64); 8680 8681 SOC_IF_ERROR_RETURN 8682 (WRITE_CPRI_RXFRM_CPRSR_CTRLr(unit, port, rxfrm_cprsr)); 8683 return SOC_E_NONE; 8684 } 8685 8686 int cprif_drv_cpri_port_rx_cw_fast_eth_word_config_get(int unit, int port, cprif_cpri_rx_fast_eth_word_config_t* config_info) 8687 { 8688 uint64 rxfrm_cprsr; 8689 8690 SOC_IF_ERROR_RETURN 8691 (READ_CPRI_RXFRM_CPRSR_CTRLr(unit, port, &rxfrm_cprsr)); 8692 8693 config_info->sub_channel_start = soc_reg64_field32_get(unit, CPRI_RXFRM_CPRSR_CTRLr, rxfrm_cprsr, RXFRM_ETH_SCHAN_STARTf); 8694 config_info->sub_channel_size = soc_reg64_field32_get(unit, CPRI_RXFRM_CPRSR_CTRLr, rxfrm_cprsr, RXFRM_ETH_SCHAN_SIZEf); 8695 config_info->cw_sel = soc_reg64_field32_get(unit, CPRI_RXFRM_CPRSR_CTRLr, rxfrm_cprsr, RXFRM_ETH_CW_SELf); 8696 config_info->cw_size = soc_reg64_field32_get(unit, CPRI_RXFRM_CPRSR_CTRLr, rxfrm_cprsr, RXFRM_ETH_CW_SIZEf); 8697 8698 return SOC_E_NONE; 8699 } 8700 8701 int cprif_drv_cpri_port_rx_cw_fast_eth_config_set(int unit, int port, cprif_cpri_rx_fast_eth_config_t* config_info) 8702 { 8703 uint64 rxfrm_fast_eth_ctrl, val64; 8704 8705 SOC_IF_ERROR_RETURN 8706 (READ_CPRI_RX_FAST_ETH_CTRLr(unit, port, &rxfrm_fast_eth_ctrl)); 8707 COMPILER_64_SET(val64, 0, config_info->queue_num); 8708 soc_reg64_field_set(unit, CPRI_RX_FAST_ETH_CTRLr, &rxfrm_fast_eth_ctrl, RX_FAST_ETH_QUEUE_NUMf, val64); 8709 COMPILER_64_SET(val64, 0, config_info->ignore_fcs_err ? 1:0); 8710 soc_reg64_field_set(unit, CPRI_RX_FAST_ETH_CTRLr, &rxfrm_fast_eth_ctrl, RX_FAST_ETH_IGNORE_FCS_ERRf, val64); 8711 COMPILER_64_SET(val64, 0, config_info->min_packet_size); 8712 soc_reg64_field_set(unit, CPRI_RX_FAST_ETH_CTRLr, &rxfrm_fast_eth_ctrl, RX_FAST_ETH_MIN_PKT_SIZEf, val64); 8713 COMPILER_64_SET(val64, 0, config_info->min_packet_drop ? 1:0); 8714 soc_reg64_field_set(unit, CPRI_RX_FAST_ETH_CTRLr, &rxfrm_fast_eth_ctrl, RX_FAST_ETH_DROP_MIN_PKTf, val64); 8715 COMPILER_64_SET(val64, 0, config_info->max_packet_size); 8716 soc_reg64_field_set(unit, CPRI_RX_FAST_ETH_CTRLr, &rxfrm_fast_eth_ctrl, RX_FAST_ETH_MAX_PKT_SIZEf, val64); 8717 COMPILER_64_SET(val64, 0, config_info->max_packet_drop ? 1:0); 8718 soc_reg64_field_set(unit, CPRI_RX_FAST_ETH_CTRLr, &rxfrm_fast_eth_ctrl, RX_FAST_ETH_DROP_MAX_PKTf, val64); 8719 COMPILER_64_SET(val64, 0, config_info->strip_crc? 1:0); 8720 soc_reg64_field_set(unit, CPRI_RX_FAST_ETH_CTRLr, &rxfrm_fast_eth_ctrl, RX_FAST_ETH_STRIP_CRCf, val64); 8721 8722 SOC_IF_ERROR_RETURN 8723 (WRITE_CPRI_RX_FAST_ETH_CTRLr(unit, port, rxfrm_fast_eth_ctrl)); 8724 return SOC_E_NONE; 8725 } 8726 8727 int cprif_drv_cpri_port_rx_cw_fast_eth_config_get(int unit, int port, cprif_cpri_rx_fast_eth_config_t* config_info) 8728 { 8729 uint64 rxfrm_fast_eth_ctrl; 8730 8731 SOC_IF_ERROR_RETURN 8732 (READ_CPRI_RX_FAST_ETH_CTRLr(unit, port, &rxfrm_fast_eth_ctrl)); 8733 8734 config_info->queue_num = soc_reg64_field32_get(unit, CPRI_RX_FAST_ETH_CTRLr, rxfrm_fast_eth_ctrl, RX_FAST_ETH_QUEUE_NUMf); 8735 config_info->ignore_fcs_err = soc_reg64_field32_get(unit, CPRI_RX_FAST_ETH_CTRLr, rxfrm_fast_eth_ctrl, RX_FAST_ETH_IGNORE_FCS_ERRf); 8736 config_info->min_packet_size = soc_reg64_field32_get(unit, CPRI_RX_FAST_ETH_CTRLr, rxfrm_fast_eth_ctrl, RX_FAST_ETH_MIN_PKT_SIZEf); 8737 config_info->min_packet_drop = soc_reg64_field32_get(unit, CPRI_RX_FAST_ETH_CTRLr, rxfrm_fast_eth_ctrl, RX_FAST_ETH_DROP_MIN_PKTf); 8738 config_info->max_packet_size = soc_reg64_field32_get(unit, CPRI_RX_FAST_ETH_CTRLr, rxfrm_fast_eth_ctrl, RX_FAST_ETH_MAX_PKT_SIZEf); 8739 config_info->max_packet_drop = soc_reg64_field32_get(unit, CPRI_RX_FAST_ETH_CTRLr, rxfrm_fast_eth_ctrl, RX_FAST_ETH_DROP_MAX_PKTf); 8740 config_info->strip_crc = soc_reg64_field32_get(unit, CPRI_RX_FAST_ETH_CTRLr, rxfrm_fast_eth_ctrl, RX_FAST_ETH_STRIP_CRCf); 8741 8742 return SOC_E_NONE; 8743 } 8744 8745 int cprif_drv_cpri_port_tx_cw_fast_eth_config_set(int unit, int port, cprif_cpri_tx_fast_eth_config_t* config_info) 8746 { 8747 uint64 txfrm_cwa, val64; 8748 8749 SOC_IF_ERROR_RETURN 8750 (READ_CPRI_TX_FAST_ETH_CTRLr(unit, port, &txfrm_cwa)); 8751 8752 COMPILER_64_SET(val64, 0, config_info->queue_num); 8753 soc_reg64_field_set(unit, CPRI_TX_FAST_ETH_CTRLr, &txfrm_cwa, TX_FAST_ETH_QUEUE_NUMf, val64); 8754 COMPILER_64_SET(val64, 0, config_info->min_ipg); 8755 soc_reg64_field_set(unit, CPRI_TX_FAST_ETH_CTRLr, &txfrm_cwa, TX_FAST_ETH_MIN_IPGf, val64); 8756 COMPILER_64_SET(val64, 0, config_info->crc_mode); 8757 soc_reg64_field_set(unit, CPRI_TX_FAST_ETH_CTRLr, &txfrm_cwa, TX_FAST_ETH_CRC_MODEf, val64); 8758 COMPILER_64_SET(val64, 0, config_info->cw_sel); 8759 soc_reg64_field_set(unit, CPRI_TX_FAST_ETH_CTRLr, &txfrm_cwa, TX_FAST_ETH_CW_SELf, val64); 8760 COMPILER_64_SET(val64, 0, config_info->cw_size); 8761 soc_reg64_field_set(unit, CPRI_TX_FAST_ETH_CTRLr, &txfrm_cwa, TX_FAST_ETH_CW_SIZEf, val64); 8762 COMPILER_64_SET(val64, 0, config_info->sub_channel_size); 8763 soc_reg64_field_set(unit, CPRI_TX_FAST_ETH_CTRLr, &txfrm_cwa, TX_FAST_ETH_SCHAN_SIZEf, val64); 8764 COMPILER_64_SET(val64, 0, config_info->sub_channel_start); 8765 soc_reg64_field_set(unit, CPRI_TX_FAST_ETH_CTRLr, &txfrm_cwa, TX_FAST_ETH_SCHAN_STARTf, val64); 8766 SOC_IF_ERROR_RETURN 8767 (WRITE_CPRI_TX_FAST_ETH_CTRLr(unit, port, txfrm_cwa)); 8768 8769 return SOC_E_NONE; 8770 } 8771 8772 int cprif_drv_cpri_port_tx_cw_fast_eth_config_get(int unit, int port, cprif_cpri_tx_fast_eth_config_t* config_info) 8773 { 8774 uint64 txfrm_cwa; 8775 8776 SOC_IF_ERROR_RETURN 8777 (READ_CPRI_TX_FAST_ETH_CTRLr(unit, port, &txfrm_cwa)); 8778 8779 config_info->queue_num = soc_reg64_field32_get(unit, CPRI_TX_FAST_ETH_CTRLr, txfrm_cwa, TX_FAST_ETH_QUEUE_NUMf); 8780 config_info->min_ipg = soc_reg64_field32_get(unit, CPRI_TX_FAST_ETH_CTRLr, txfrm_cwa, TX_FAST_ETH_MIN_IPGf); 8781 config_info->crc_mode = soc_reg64_field32_get(unit, CPRI_TX_FAST_ETH_CTRLr, txfrm_cwa, TX_FAST_ETH_CRC_MODEf); 8782 config_info->cw_sel = soc_reg64_field32_get(unit, CPRI_TX_FAST_ETH_CTRLr, txfrm_cwa, TX_FAST_ETH_CW_SELf); 8783 config_info->cw_size = soc_reg64_field32_get(unit, CPRI_TX_FAST_ETH_CTRLr, txfrm_cwa, TX_FAST_ETH_CW_SIZEf); 8784 8785 config_info->sub_channel_size = soc_reg64_field32_get(unit, CPRI_TX_FAST_ETH_CTRLr, txfrm_cwa, TX_FAST_ETH_SCHAN_SIZEf); 8786 config_info->sub_channel_start = soc_reg64_field32_get(unit, CPRI_TX_FAST_ETH_CTRLr, txfrm_cwa, TX_FAST_ETH_SCHAN_STARTf); 8787 8788 return SOC_E_NONE; 8789 } 8790 8791 int cprif_drv_rx_vsd_ctrl_copy_id_get(int unit, int port, uint32* copy_id) 8792 { 8793 uint32 reg_val=0; 8794 8795 SOC_IF_ERROR_RETURN 8796 (READ_CPRI_RXFRM_VSD_CTRLr(unit, port, ®_val)); 8797 *copy_id = soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_SEC_NUM_GEN_COPY_IDf); 8798 8799 return SOC_E_NONE; 8800 } 8801 8802 int cprif_drv_rx_vsd_ctrl_copy_id_set(int unit, int port, uint32 copy_id) 8803 { 8804 uint32 reg_val=0; 8805 8806 if (copy_id > 1) { 8807 LOG_CLI(("copy_id %d is out of range, either 0 or 1 only", copy_id)); 8808 return SOC_E_PARAM; 8809 } 8810 SOC_IF_ERROR_RETURN 8811 (READ_CPRI_RXFRM_VSD_CTRLr(unit, port, ®_val)); 8812 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_SEC_NUM_GEN_COPY_IDf, copy_id); 8813 SOC_IF_ERROR_RETURN 8814 (WRITE_CPRI_RXFRM_VSD_CTRLr(unit, port, reg_val)); 8815 8816 return SOC_E_NONE; 8817 } 8818 8819 int cprif_drv_rx_vsd_ctrl_rsvd_mask_set(int unit, int port, uint32* rsvd_mask) 8820 { 8821 uint64 reg_val; 8822 8823 COMPILER_64_SET(reg_val,rsvd_mask[1],rsvd_mask[0]); 8824 SOC_IF_ERROR_RETURN 8825 (WRITE_CPRI_RXFRM_VSD_RSRV_MASK0_CTRLr(unit, port, reg_val)); 8826 8827 COMPILER_64_SET(reg_val,rsvd_mask[3],rsvd_mask[2]); 8828 SOC_IF_ERROR_RETURN 8829 (WRITE_CPRI_RXFRM_VSD_RSRV_MASK1_CTRLr(unit, port, reg_val)); 8830 8831 return SOC_E_NONE; 8832 8833 } 8834 8835 int cprif_drv_rx_vsd_ctrl_rsvd_mask_get(int unit, int port, uint32* rsvd_mask) 8836 { 8837 uint64 reg_val; 8838 8839 /* get current rsvd_mask. */ 8840 SOC_IF_ERROR_RETURN 8841 (READ_CPRI_RXFRM_VSD_RSRV_MASK0_CTRLr(unit, port, ®_val)); 8842 rsvd_mask[0] = COMPILER_64_LO(reg_val); 8843 rsvd_mask[1] = COMPILER_64_HI(reg_val); 8844 8845 SOC_IF_ERROR_RETURN 8846 (READ_CPRI_RXFRM_VSD_RSRV_MASK1_CTRLr(unit, port, ®_val)); 8847 rsvd_mask[2] = COMPILER_64_LO(reg_val); 8848 rsvd_mask[3] = COMPILER_64_HI(reg_val); 8849 8850 return SOC_E_NONE; 8851 } 8852 8853 int cprif_drv_rx_vsd_ctrl_ctrl_mask_set(int unit, int port, uint32 copy_id, uint32* ctrl_mask) 8854 { 8855 uint64 reg_val0; 8856 uint64 reg_val1; 8857 8858 COMPILER_64_SET(reg_val0,ctrl_mask[1],ctrl_mask[0]); 8859 COMPILER_64_SET(reg_val1,ctrl_mask[3],ctrl_mask[2]); 8860 8861 if (copy_id == 0) { 8862 SOC_IF_ERROR_RETURN 8863 (WRITE_CPRI_RXFRM_VSD_MASK0_COPY0_CTRLr(unit, port,reg_val0)); 8864 SOC_IF_ERROR_RETURN 8865 (WRITE_CPRI_RXFRM_VSD_MASK1_COPY0_CTRLr(unit, port,reg_val1)); 8866 } else { 8867 SOC_IF_ERROR_RETURN 8868 (WRITE_CPRI_RXFRM_VSD_MASK0_COPY1_CTRLr(unit, port,reg_val0)); 8869 SOC_IF_ERROR_RETURN 8870 (WRITE_CPRI_RXFRM_VSD_MASK1_COPY1_CTRLr(unit, port,reg_val1)); 8871 } 8872 return SOC_E_NONE; 8873 } 8874 8875 int cprif_drv_rx_vsd_ctrl_ctrl_mask_get(int unit, int port, uint32 copy_id, uint32* ctrl_mask) 8876 { 8877 uint64 reg_val0; 8878 uint64 reg_val1; 8879 if (copy_id == 0) { 8880 SOC_IF_ERROR_RETURN 8881 (READ_CPRI_RXFRM_VSD_MASK0_COPY0_CTRLr(unit, port,®_val0)); 8882 SOC_IF_ERROR_RETURN 8883 (READ_CPRI_RXFRM_VSD_MASK1_COPY0_CTRLr(unit, port,®_val1)); 8884 } else { 8885 SOC_IF_ERROR_RETURN 8886 (READ_CPRI_RXFRM_VSD_MASK0_COPY1_CTRLr(unit, port,®_val0)); 8887 SOC_IF_ERROR_RETURN 8888 (READ_CPRI_RXFRM_VSD_MASK1_COPY1_CTRLr(unit, port,®_val1)); 8889 } 8890 ctrl_mask[0] = COMPILER_64_LO(reg_val0); 8891 ctrl_mask[1] = COMPILER_64_HI(reg_val0); 8892 8893 ctrl_mask[2] = COMPILER_64_LO(reg_val1); 8894 ctrl_mask[3] = COMPILER_64_HI(reg_val1); 8895 8896 return SOC_E_NONE; 8897 } 8898 8899 int cprif_drv_rx_vsd_ctrl_config_set(int unit, int port, cprif_cpri_vsd_config_t* config_info) 8900 { 8901 uint32 copy_id=0xff; 8902 uint64 ctrl_mask; 8903 uint32 reg_val=0; 8904 8905 /* 8906 * Clear the control mask before updating the config to stop the processing. 8907 */ 8908 8909 SOC_IF_ERROR_RETURN 8910 (cprif_drv_rx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 8911 8912 COMPILER_64_ZERO(ctrl_mask); 8913 if (copy_id == 0){ 8914 SOC_IF_ERROR_RETURN 8915 (WRITE_CPRI_RXFRM_VSD_MASK0_COPY1_CTRLr(unit, port,ctrl_mask)); 8916 SOC_IF_ERROR_RETURN 8917 (WRITE_CPRI_RXFRM_VSD_MASK1_COPY1_CTRLr(unit, port,ctrl_mask)); 8918 copy_id = 1; /* new copy id */ 8919 } else { /* copy_id is 1 */ 8920 SOC_IF_ERROR_RETURN 8921 (WRITE_CPRI_RXFRM_VSD_MASK0_COPY0_CTRLr(unit, port,ctrl_mask)); 8922 SOC_IF_ERROR_RETURN 8923 (WRITE_CPRI_RXFRM_VSD_MASK1_COPY0_CTRLr(unit, port,ctrl_mask)); 8924 copy_id = 0; /* new copy id */ 8925 } 8926 8927 SOC_IF_ERROR_RETURN 8928 (cprif_drv_rx_vsd_ctrl_copy_id_set(unit, port, copy_id)); 8929 8930 /* 8931 * Update the vsd ctrl configuration. 8932 */ 8933 8934 SOC_IF_ERROR_RETURN 8935 (READ_CPRI_RXFRM_VSD_CTRLr(unit, port, ®_val)); 8936 8937 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_BYTE_ORDERf, config_info->byte_order); 8938 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_QUEUE_NUMf, config_info->queue_num); 8939 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_FLOW_BYTES_COPY0f, config_info->flow_bytes); 8940 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_SCHAN_STEP_COPY0f, config_info->sub_channel_steps); 8941 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_SCHAN_BYTES_COPY0f, config_info->sub_channel_num_bytes); 8942 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_SCHAN_SIZE_COPY0f, config_info->sub_channel_size); 8943 soc_reg_field_set(unit, CPRI_RXFRM_VSD_CTRLr, ®_val, RXFRM_VSD_CTRL_SCHAN_START_COPY0f, config_info->sub_channel_start); 8944 8945 SOC_IF_ERROR_RETURN 8946 (WRITE_CPRI_RXFRM_VSD_CTRLr(unit, port, reg_val)); 8947 8948 SOC_IF_ERROR_RETURN 8949 (WRITE_CPRI_RXFRM_VSD_RSRV_MASK0_CTRLr(unit, port,config_info->rsvd_mask[0])); 8950 SOC_IF_ERROR_RETURN 8951 (WRITE_CPRI_RXFRM_VSD_RSRV_MASK1_CTRLr(unit, port,config_info->rsvd_mask[1])); 8952 8953 return SOC_E_NONE; 8954 } 8955 8956 int cprif_drv_rx_vsd_ctrl_config_get(int unit, int port, cprif_cpri_vsd_config_t* config_info) 8957 { 8958 uint32 reg_val=0; 8959 8960 8961 /* 8962 * Get the vsd ctrl configuration. 8963 */ 8964 8965 SOC_IF_ERROR_RETURN 8966 (READ_CPRI_RXFRM_VSD_CTRLr(unit, port, ®_val)); 8967 8968 config_info->byte_order = soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_BYTE_ORDERf); 8969 config_info->queue_num = soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_QUEUE_NUMf); 8970 config_info->flow_bytes = soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_FLOW_BYTES_COPY0f); 8971 config_info->sub_channel_steps = soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_SCHAN_STEP_COPY0f); 8972 config_info->sub_channel_size = soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_SCHAN_SIZE_COPY0f); 8973 config_info->sub_channel_start = soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_SCHAN_START_COPY0f); 8974 config_info->sub_channel_num_bytes =soc_reg_field_get(unit, CPRI_RXFRM_VSD_CTRLr, reg_val, RXFRM_VSD_CTRL_SCHAN_BYTES_COPY0f); 8975 8976 8977 SOC_IF_ERROR_RETURN 8978 (READ_CPRI_RXFRM_VSD_RSRV_MASK0_CTRLr(unit, port, &config_info->rsvd_mask[0])); 8979 SOC_IF_ERROR_RETURN 8980 (READ_CPRI_RXFRM_VSD_RSRV_MASK1_CTRLr(unit, port, &config_info->rsvd_mask[1])); 8981 8982 return SOC_E_NONE; 8983 } 8984 8985 8986 int cprif_drv_rx_vsd_ctrl_flow_config_set(int unit, int port, 8987 uint32 sector_num, 8988 const cprif_cpri_rx_vsd_ctrl_flow_config_t *entry) 8989 { 8990 int phy_port; 8991 int port_core_index; 8992 soc_mem_t local_mem; 8993 soc_mem_t mem_select[] = { CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_0m, 8994 CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_1m, 8995 CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_2m, 8996 CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_3m}; 8997 uint32 *wr_data_ptr; 8998 uint32 field_buf; 8999 uint32 num_words; 9000 uint32 blk_num=0; 9001 SOC_INIT_FUNC_DEFS; 9002 9003 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9004 port_core_index = ((phy_port-1)%4); 9005 9006 local_mem = mem_select[port_core_index]; 9007 9008 num_words = soc_mem_entry_words(unit, local_mem); 9009 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9010 CPRIMOD_NULL_CHECK(wr_data_ptr); 9011 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9012 9013 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9014 9015 field_buf = entry->group_id; 9016 soc_mem_field_set(unit, local_mem, wr_data_ptr, GROUP_IDf, &field_buf); 9017 9018 field_buf = entry->hyper_frame_number; 9019 soc_mem_field_set(unit, local_mem, wr_data_ptr, HFN_INDEXf, &field_buf); 9020 9021 field_buf = entry->hyper_frame_modulo;; 9022 soc_mem_field_set(unit, local_mem, wr_data_ptr, HFN_MODULOf, &field_buf); 9023 9024 field_buf = entry->filter_zero_data;; 9025 soc_mem_field_set(unit, local_mem, wr_data_ptr, FILTER_ZERO_DATAf, &field_buf); 9026 9027 _SOC_IF_ERR_EXIT 9028 (soc_mem_write(unit, local_mem, blk_num, sector_num, wr_data_ptr)); 9029 9030 exit: 9031 sal_free(wr_data_ptr); 9032 SOC_FUNC_RETURN; 9033 } 9034 9035 int cprif_drv_rx_vsd_ctrl_flow_config_get(int unit, int port, 9036 uint32 sector_num, 9037 cprif_cpri_rx_vsd_ctrl_flow_config_t *entry) 9038 { 9039 int phy_port; 9040 int port_core_index; 9041 soc_mem_t local_mem; 9042 soc_mem_t mem_select[] = { CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_0m, 9043 CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_1m, 9044 CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_2m, 9045 CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_3m}; 9046 uint32 *rd_data_ptr; 9047 uint32 field_buf; 9048 uint32 num_words; 9049 uint32 blk_num=0; 9050 SOC_INIT_FUNC_DEFS; 9051 9052 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9053 port_core_index = ((phy_port-1)%4); 9054 9055 local_mem = mem_select[port_core_index]; 9056 9057 num_words = soc_mem_entry_words(unit, local_mem); 9058 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9059 CPRIMOD_NULL_CHECK(rd_data_ptr); 9060 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9061 9062 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9063 9064 _SOC_IF_ERR_EXIT 9065 (soc_mem_read(unit, local_mem, blk_num , sector_num, rd_data_ptr)); 9066 9067 soc_mem_field_get(unit, local_mem, rd_data_ptr, GROUP_IDf, &field_buf); 9068 entry->group_id = field_buf; 9069 9070 soc_mem_field_get(unit, local_mem, rd_data_ptr, HFN_INDEXf, &field_buf); 9071 entry->hyper_frame_number = field_buf; 9072 9073 soc_mem_field_get(unit, local_mem, rd_data_ptr, HFN_MODULOf, &field_buf); 9074 entry->hyper_frame_modulo = field_buf; 9075 9076 soc_mem_field_get(unit, local_mem, rd_data_ptr, FILTER_ZERO_DATAf, &field_buf); 9077 entry->filter_zero_data = field_buf; 9078 exit: 9079 sal_free(rd_data_ptr); 9080 SOC_FUNC_RETURN; 9081 } 9082 9083 int cprif_drv_rx_vsd_ctrl_group_num_sector_set(int unit, int port, 9084 uint32 group_id, 9085 uint32 num_sector) 9086 { 9087 int phy_port; 9088 int port_core_index; 9089 soc_mem_t local_mem; 9090 soc_mem_t mem_select[] = { CPRI_VSDCTRL_NUM_SEC_TAB_CFG_0m, 9091 CPRI_VSDCTRL_NUM_SEC_TAB_CFG_1m, 9092 CPRI_VSDCTRL_NUM_SEC_TAB_CFG_2m, 9093 CPRI_VSDCTRL_NUM_SEC_TAB_CFG_3m }; 9094 uint32 *wr_data_ptr; 9095 uint32 field_buf; 9096 uint32 num_words; 9097 uint32 blk_num=0; 9098 SOC_INIT_FUNC_DEFS; 9099 9100 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9101 port_core_index = ((phy_port-1)%4); 9102 9103 local_mem = mem_select[port_core_index]; 9104 9105 num_words = soc_mem_entry_words(unit, local_mem); 9106 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9107 CPRIMOD_NULL_CHECK(wr_data_ptr); 9108 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9109 9110 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9111 9112 field_buf = num_sector; 9113 soc_mem_field_set(unit, local_mem, wr_data_ptr, NUM_SECf, &field_buf); 9114 9115 _SOC_IF_ERR_EXIT 9116 (soc_mem_write(unit, local_mem, blk_num, group_id, wr_data_ptr)); 9117 9118 exit: 9119 sal_free(wr_data_ptr); 9120 SOC_FUNC_RETURN; 9121 } 9122 9123 int cprif_drv_rx_vsd_ctrl_group_num_sector_get(int unit, int port, 9124 uint32 group_id, 9125 uint32* num_sector) 9126 { 9127 int phy_port; 9128 int port_core_index; 9129 soc_mem_t local_mem; 9130 soc_mem_t mem_select[] = { CPRI_VSDCTRL_NUM_SEC_TAB_CFG_0m, 9131 CPRI_VSDCTRL_NUM_SEC_TAB_CFG_1m, 9132 CPRI_VSDCTRL_NUM_SEC_TAB_CFG_2m, 9133 CPRI_VSDCTRL_NUM_SEC_TAB_CFG_3m }; 9134 9135 uint32 *rd_data_ptr; 9136 uint32 field_buf; 9137 uint32 num_words; 9138 uint32 blk_num=0; 9139 SOC_INIT_FUNC_DEFS; 9140 9141 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9142 port_core_index = ((phy_port-1)%4); 9143 9144 local_mem = mem_select[port_core_index]; 9145 9146 num_words = soc_mem_entry_words(unit, local_mem); 9147 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9148 CPRIMOD_NULL_CHECK(rd_data_ptr); 9149 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9150 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9151 9152 _SOC_IF_ERR_EXIT 9153 (soc_mem_read(unit, local_mem, blk_num , group_id, rd_data_ptr)); 9154 9155 soc_mem_field_get(unit, local_mem, rd_data_ptr, NUM_SECf, &field_buf); 9156 *num_sector = field_buf; 9157 exit: 9158 sal_free(rd_data_ptr); 9159 SOC_FUNC_RETURN; 9160 } 9161 9162 int cprif_drv_rx_vsd_ctrl_group_config_set(int unit, int port, 9163 uint32 group_id, 9164 uint32 tag_id, 9165 uint32 grp_ptr_index) 9166 { 9167 int phy_port; 9168 int port_core_index; 9169 soc_mem_t local_mem; 9170 soc_mem_t mem_select[] = { CPRI_VSDCTRL_GRP_CFG_TAB_CFG_0m, 9171 CPRI_VSDCTRL_GRP_CFG_TAB_CFG_1m, 9172 CPRI_VSDCTRL_GRP_CFG_TAB_CFG_2m, 9173 CPRI_VSDCTRL_GRP_CFG_TAB_CFG_3m }; 9174 uint32 *wr_data_ptr; 9175 uint32 field_buf; 9176 uint32 num_words; 9177 uint32 blk_num=0; 9178 SOC_INIT_FUNC_DEFS; 9179 9180 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9181 port_core_index = ((phy_port-1)%4); 9182 9183 local_mem = mem_select[port_core_index]; 9184 9185 num_words = soc_mem_entry_words(unit, local_mem); 9186 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9187 CPRIMOD_NULL_CHECK(wr_data_ptr); 9188 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9189 9190 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9191 9192 field_buf = tag_id; 9193 soc_mem_field_set(unit, local_mem, wr_data_ptr, TAG_IDf, &field_buf); 9194 9195 field_buf = grp_ptr_index; 9196 soc_mem_field_set(unit, local_mem, wr_data_ptr, GRP_PTRf, &field_buf); 9197 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9198 9199 _SOC_IF_ERR_EXIT 9200 (soc_mem_write(unit, local_mem, blk_num, group_id, wr_data_ptr)); 9201 9202 exit: 9203 sal_free(wr_data_ptr); 9204 SOC_FUNC_RETURN; 9205 } 9206 9207 int cprif_drv_rx_vsd_ctrl_group_config_get(int unit, int port, 9208 uint32 group_id, 9209 uint32* tag_id, 9210 uint32* grp_ptr_index) 9211 { 9212 int phy_port; 9213 int port_core_index; 9214 soc_mem_t local_mem; 9215 soc_mem_t mem_select[] = { CPRI_VSDCTRL_GRP_CFG_TAB_CFG_0m, 9216 CPRI_VSDCTRL_GRP_CFG_TAB_CFG_1m, 9217 CPRI_VSDCTRL_GRP_CFG_TAB_CFG_2m, 9218 CPRI_VSDCTRL_GRP_CFG_TAB_CFG_3m }; 9219 9220 uint32 *rd_data_ptr; 9221 uint32 field_buf; 9222 uint32 num_words; 9223 uint32 blk_num=0; 9224 SOC_INIT_FUNC_DEFS; 9225 9226 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9227 port_core_index = ((phy_port-1)%4); 9228 9229 local_mem = mem_select[port_core_index]; 9230 9231 num_words = soc_mem_entry_words(unit, local_mem); 9232 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9233 CPRIMOD_NULL_CHECK(rd_data_ptr); 9234 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9235 9236 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9237 _SOC_IF_ERR_EXIT 9238 (soc_mem_read(unit, local_mem, blk_num , group_id, rd_data_ptr)); 9239 9240 soc_mem_field_get(unit, local_mem, rd_data_ptr, TAG_IDf, &field_buf); 9241 *tag_id = field_buf; 9242 9243 soc_mem_field_get(unit, local_mem, rd_data_ptr, GRP_PTRf, &field_buf); 9244 *grp_ptr_index = field_buf; 9245 exit: 9246 sal_free(rd_data_ptr); 9247 SOC_FUNC_RETURN; 9248 } 9249 9250 9251 int cprif_drv_rx_vsd_ctrl_group_assign_ptr_set(int unit, int port, 9252 uint32 ptr_index, 9253 uint32 sec_num) 9254 { 9255 int phy_port; 9256 int port_core_index; 9257 soc_mem_t local_mem; 9258 soc_mem_t mem_select[] = { CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_0m, 9259 CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_1m, 9260 CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_2m, 9261 CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_3m }; 9262 uint32 *wr_data_ptr; 9263 uint32 field_buf; 9264 uint32 num_words; 9265 uint32 blk_num=0; 9266 SOC_INIT_FUNC_DEFS; 9267 9268 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9269 port_core_index = ((phy_port-1)%4); 9270 9271 local_mem = mem_select[port_core_index]; 9272 9273 num_words = soc_mem_entry_words(unit, local_mem); 9274 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9275 CPRIMOD_NULL_CHECK(wr_data_ptr); 9276 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9277 9278 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9279 9280 field_buf = sec_num; 9281 soc_mem_field_set(unit, local_mem, wr_data_ptr, SEC_NUMf, &field_buf); 9282 9283 9284 _SOC_IF_ERR_EXIT 9285 (soc_mem_write(unit, local_mem, blk_num, ptr_index, wr_data_ptr)); 9286 9287 exit: 9288 sal_free(wr_data_ptr); 9289 SOC_FUNC_RETURN; 9290 } 9291 9292 int cprif_drv_rx_vsd_ctrl_group_assign_ptr_get(int unit, int port, 9293 uint32 ptr_index, 9294 uint32* sec_num) 9295 { 9296 int phy_port; 9297 int port_core_index; 9298 soc_mem_t local_mem; 9299 soc_mem_t mem_select[] = { CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_0m, 9300 CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_1m, 9301 CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_2m, 9302 CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_3m }; 9303 9304 uint32 *rd_data_ptr; 9305 uint32 field_buf; 9306 uint32 num_words; 9307 uint32 blk_num=0; 9308 SOC_INIT_FUNC_DEFS; 9309 9310 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9311 port_core_index = ((phy_port-1)%4); 9312 9313 local_mem = mem_select[port_core_index]; 9314 9315 num_words = soc_mem_entry_words(unit, local_mem); 9316 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9317 CPRIMOD_NULL_CHECK(rd_data_ptr); 9318 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9319 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9320 9321 _SOC_IF_ERR_EXIT 9322 (soc_mem_read(unit, local_mem, blk_num , ptr_index, rd_data_ptr)); 9323 9324 soc_mem_field_get(unit, local_mem, rd_data_ptr, SEC_NUMf, &field_buf); 9325 *sec_num = field_buf; 9326 9327 exit: 9328 sal_free(rd_data_ptr); 9329 SOC_FUNC_RETURN; 9330 } 9331 9332 int cprif_drv_allocate_grp_ptr (uint32* grp_ptr_mask, uint32 num_sec, uint32* ptr_index) 9333 { 9334 uint16 num_entries; 9335 uint16 index; 9336 uint16 first_location; 9337 uint8 location_found; 9338 9339 /* 9340 * Find the grp ptr location that can accomodate num_sec. 9341 */ 9342 index = 0; 9343 first_location = 0; 9344 location_found = FALSE; 9345 num_entries = num_sec; 9346 9347 while (num_entries && (index < CPRIF_VSD_CTRL_NUM_GROUP_PTR)) { 9348 num_entries = num_sec; 9349 /* 9350 * Find first available spot. 9351 */ 9352 for ( ; index < CPRIF_VSD_CTRL_NUM_GROUP_PTR; index++) { 9353 if (CPRIF_PBMP_AVAILABLE(grp_ptr_mask, index)) { 9354 first_location = index; 9355 location_found = TRUE; 9356 break; 9357 } 9358 } /* for */ 9359 /* 9360 * Check that spot has enough available space. 9361 */ 9362 if (location_found) { 9363 for ( ;(index < CPRIF_VSD_CTRL_NUM_GROUP_PTR) && (num_entries > 0) ; index++) { 9364 if (CPRIF_PBMP_AVAILABLE(grp_ptr_mask, index)){ 9365 num_entries--; 9366 } else { 9367 location_found = FALSE; 9368 break; 9369 } 9370 } /* for */ 9371 } 9372 } /* while */ 9373 9374 if (num_entries == 0) { 9375 *ptr_index = first_location; 9376 } else { 9377 return SOC_E_UNAVAIL; 9378 } 9379 return SOC_E_NONE; 9380 } 9381 9382 9383 int cprif_drv_tx_vsd_ctrl_copy_id_get(int unit, int port, uint32* copy_id) 9384 { 9385 uint32 reg_val=0; 9386 9387 SOC_IF_ERROR_RETURN 9388 (READ_CPRI_TXFRM_CWA_VSD_CTRL_CFGr(unit, port, ®_val)); 9389 *copy_id = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CFGr, reg_val, 9390 TX_CWA_VSD_CTRL_COPY_IDf); 9391 9392 return SOC_E_NONE; 9393 } 9394 9395 int cprif_drv_tx_vsd_ctrl_copy_id_set(int unit, int port, uint32 copy_id) 9396 { 9397 uint32 reg_val=0; 9398 9399 if (copy_id > 1) { 9400 LOG_CLI(("copy_id %d is out of range, either 0 or 1 only", copy_id)); 9401 return SOC_E_PARAM; 9402 } 9403 SOC_IF_ERROR_RETURN 9404 (READ_CPRI_TXFRM_CWA_VSD_CTRL_CFGr(unit, port, ®_val)); 9405 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CFGr, ®_val, TX_CWA_VSD_CTRL_COPY_IDf, copy_id); 9406 SOC_IF_ERROR_RETURN 9407 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_CFGr(unit, port, reg_val)); 9408 9409 return SOC_E_NONE; 9410 } 9411 9412 int cprif_drv_tx_vsd_ctrl_rsvd_mask_set(int unit, int port, uint32* rsvd_mask) 9413 { 9414 uint64 reg_val; 9415 9416 COMPILER_64_SET(reg_val,rsvd_mask[1],rsvd_mask[0]); 9417 SOC_IF_ERROR_RETURN 9418 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK0_CTRL2r(unit, port, reg_val)); 9419 9420 COMPILER_64_SET(reg_val,rsvd_mask[3],rsvd_mask[2]); 9421 SOC_IF_ERROR_RETURN 9422 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK1_CTRL2r(unit, port, reg_val)); 9423 9424 return SOC_E_NONE; 9425 9426 } 9427 9428 int cprif_drv_tx_vsd_ctrl_rsvd_mask_get(int unit, int port, uint32* rsvd_mask) 9429 { 9430 uint64 reg_val; 9431 9432 /* get current rsvd_mask. */ 9433 SOC_IF_ERROR_RETURN 9434 (READ_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK0_CTRL2r(unit, port, ®_val)); 9435 rsvd_mask[0] = COMPILER_64_LO(reg_val); 9436 rsvd_mask[1] = COMPILER_64_HI(reg_val); 9437 9438 SOC_IF_ERROR_RETURN 9439 (READ_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK1_CTRL2r(unit, port, ®_val)); 9440 rsvd_mask[2] = COMPILER_64_LO(reg_val); 9441 rsvd_mask[3] = COMPILER_64_HI(reg_val); 9442 9443 return SOC_E_NONE; 9444 } 9445 9446 int cprif_drv_tx_vsd_ctrl_ctrl_mask_set(int unit, int port, uint32 copy_id, uint32* ctrl_mask) 9447 { 9448 uint64 reg_val0; 9449 uint64 reg_val1; 9450 9451 COMPILER_64_SET(reg_val0,ctrl_mask[1],ctrl_mask[0]); 9452 COMPILER_64_SET(reg_val1,ctrl_mask[3],ctrl_mask[2]); 9453 9454 if (copy_id == 0) { 9455 SOC_IF_ERROR_RETURN 9456 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL0r(unit, port,reg_val0)); 9457 SOC_IF_ERROR_RETURN 9458 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL0r(unit, port,reg_val1)); 9459 } else { 9460 SOC_IF_ERROR_RETURN 9461 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL1r(unit, port,reg_val0)); 9462 SOC_IF_ERROR_RETURN 9463 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL1r(unit, port,reg_val1)); 9464 } 9465 return SOC_E_NONE; 9466 } 9467 9468 int cprif_drv_tx_vsd_ctrl_ctrl_mask_get(int unit, int port, uint32 copy_id, uint32* ctrl_mask) 9469 { 9470 uint64 reg_val0; 9471 uint64 reg_val1; 9472 if (copy_id == 0) { 9473 SOC_IF_ERROR_RETURN 9474 (READ_CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL0r(unit, port,®_val0)); 9475 SOC_IF_ERROR_RETURN 9476 (READ_CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL0r(unit, port,®_val1)); 9477 } else { 9478 SOC_IF_ERROR_RETURN 9479 (READ_CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL1r(unit, port,®_val0)); 9480 SOC_IF_ERROR_RETURN 9481 (READ_CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL1r(unit, port,®_val1)); 9482 } 9483 ctrl_mask[0] = COMPILER_64_LO(reg_val0); 9484 ctrl_mask[1] = COMPILER_64_HI(reg_val0); 9485 9486 ctrl_mask[2] = COMPILER_64_LO(reg_val1); 9487 ctrl_mask[3] = COMPILER_64_HI(reg_val1); 9488 9489 return SOC_E_NONE; 9490 } 9491 9492 9493 int cprif_drv_tx_vsd_ctrl_flow_config_set(int unit, int port, 9494 uint32 sector_num, 9495 const cprif_cpri_tx_vsd_ctrl_flow_config_t *entry) 9496 { 9497 int phy_port; 9498 int port_core_index; 9499 soc_mem_t local_mem; 9500 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_CONFIG_CFG_0m, 9501 CPRI_CWA_VSD_CTRL_CONFIG_CFG_1m, 9502 CPRI_CWA_VSD_CTRL_CONFIG_CFG_2m, 9503 CPRI_CWA_VSD_CTRL_CONFIG_CFG_3m}; 9504 uint32 *wr_data_ptr; 9505 uint32 field_buf; 9506 uint32 num_words; 9507 uint32 blk_num=0; 9508 SOC_INIT_FUNC_DEFS; 9509 9510 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9511 port_core_index = ((phy_port-1)%4); 9512 9513 local_mem = mem_select[port_core_index]; 9514 9515 num_words = soc_mem_entry_words(unit, local_mem); 9516 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9517 CPRIMOD_NULL_CHECK(wr_data_ptr); 9518 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9519 9520 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9521 9522 field_buf = entry->hyper_frame_number; 9523 soc_mem_field_set(unit, local_mem, wr_data_ptr, HFN_INDEXf, &field_buf); 9524 9525 field_buf = entry->hyper_frame_modulo;; 9526 soc_mem_field_set(unit, local_mem, wr_data_ptr, HFN_MODULOf, &field_buf); 9527 9528 field_buf = entry->repeat_mode; 9529 soc_mem_field_set(unit, local_mem, wr_data_ptr, REPEAT_MODEf, &field_buf); 9530 9531 _SOC_IF_ERR_EXIT 9532 (soc_mem_write(unit, local_mem, blk_num, sector_num, wr_data_ptr)); 9533 9534 exit: 9535 sal_free(wr_data_ptr); 9536 SOC_FUNC_RETURN; 9537 } 9538 9539 int cprif_drv_tx_vsd_ctrl_flow_config_get(int unit, int port, 9540 uint32 sector_num, 9541 cprif_cpri_tx_vsd_ctrl_flow_config_t *entry) 9542 { 9543 int phy_port; 9544 int port_core_index; 9545 soc_mem_t local_mem; 9546 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_CONFIG_CFG_0m, 9547 CPRI_CWA_VSD_CTRL_CONFIG_CFG_1m, 9548 CPRI_CWA_VSD_CTRL_CONFIG_CFG_2m, 9549 CPRI_CWA_VSD_CTRL_CONFIG_CFG_3m}; 9550 uint32 *rd_data_ptr; 9551 uint32 field_buf; 9552 uint32 num_words; 9553 uint32 blk_num=0; 9554 SOC_INIT_FUNC_DEFS; 9555 9556 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9557 port_core_index = ((phy_port-1)%4); 9558 9559 local_mem = mem_select[port_core_index]; 9560 9561 num_words = soc_mem_entry_words(unit, local_mem); 9562 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9563 CPRIMOD_NULL_CHECK(rd_data_ptr); 9564 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9565 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9566 9567 _SOC_IF_ERR_EXIT 9568 (soc_mem_read(unit, local_mem, blk_num , sector_num, rd_data_ptr)); 9569 9570 soc_mem_field_get(unit, local_mem, rd_data_ptr, HFN_INDEXf, &field_buf); 9571 entry->hyper_frame_number = field_buf; 9572 9573 soc_mem_field_get(unit, local_mem, rd_data_ptr, HFN_MODULOf, &field_buf); 9574 entry->hyper_frame_modulo = field_buf; 9575 9576 soc_mem_field_get(unit, local_mem, rd_data_ptr, REPEAT_MODEf, &field_buf); 9577 entry->repeat_mode = field_buf; 9578 exit: 9579 sal_free(rd_data_ptr); 9580 SOC_FUNC_RETURN; 9581 } 9582 9583 9584 int cprif_drv_tx_vsd_ctrl_flow_id_to_group_mapping_set(int unit, int port, 9585 uint32 roe_flow_id, 9586 uint32 group_id) 9587 { 9588 int phy_port; 9589 int port_core_index; 9590 soc_mem_t local_mem; 9591 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_0m, 9592 CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_1m, 9593 CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_2m, 9594 CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_3m}; 9595 uint32 *wr_data_ptr; 9596 uint32 field_buf; 9597 uint32 num_words; 9598 uint32 blk_num=0; 9599 SOC_INIT_FUNC_DEFS; 9600 9601 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9602 port_core_index = ((phy_port-1)%4); 9603 9604 local_mem = mem_select[port_core_index]; 9605 9606 num_words = soc_mem_entry_words(unit, local_mem); 9607 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9608 CPRIMOD_NULL_CHECK(wr_data_ptr); 9609 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9610 9611 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9612 9613 field_buf = group_id; 9614 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_CTRL_GROUP_IDf, &field_buf); 9615 9616 _SOC_IF_ERR_EXIT 9617 (soc_mem_write(unit, local_mem, blk_num, roe_flow_id, wr_data_ptr)); 9618 9619 exit: 9620 sal_free(wr_data_ptr); 9621 SOC_FUNC_RETURN; 9622 } 9623 9624 int cprif_drv_tx_vsd_ctrl_flow_id_to_group_mapping_get(int unit, int port, 9625 uint32 roe_flow_id, 9626 uint32* group_id) 9627 9628 { 9629 int phy_port; 9630 int port_core_index; 9631 soc_mem_t local_mem; 9632 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_0m, 9633 CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_1m, 9634 CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_2m, 9635 CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_3m}; 9636 9637 uint32 *rd_data_ptr; 9638 uint32 field_buf; 9639 uint32 num_words; 9640 uint32 blk_num=0; 9641 SOC_INIT_FUNC_DEFS; 9642 9643 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9644 port_core_index = ((phy_port-1)%4); 9645 9646 local_mem = mem_select[port_core_index]; 9647 9648 num_words = soc_mem_entry_words(unit, local_mem); 9649 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9650 CPRIMOD_NULL_CHECK(rd_data_ptr); 9651 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9652 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9653 9654 _SOC_IF_ERR_EXIT 9655 (soc_mem_read(unit, local_mem, blk_num , roe_flow_id, rd_data_ptr)); 9656 9657 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_CTRL_GROUP_IDf, &field_buf); 9658 *group_id = field_buf; 9659 exit: 9660 sal_free(rd_data_ptr); 9661 SOC_FUNC_RETURN; 9662 } 9663 9664 9665 int cprif_drv_tx_vsd_ctrl_group_config_set(int unit, int port, 9666 uint32 group_id, 9667 uint32 num_sector, 9668 uint32 grp_ptr_index) 9669 { 9670 int phy_port; 9671 int port_core_index; 9672 soc_mem_t local_mem; 9673 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_0m, 9674 CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_1m, 9675 CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_2m, 9676 CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_3m}; 9677 uint32 *wr_data_ptr; 9678 uint32 field_buf; 9679 uint32 num_words; 9680 uint32 blk_num=0; 9681 SOC_INIT_FUNC_DEFS; 9682 9683 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9684 port_core_index = ((phy_port-1)%4); 9685 9686 local_mem = mem_select[port_core_index]; 9687 9688 num_words = soc_mem_entry_words(unit, local_mem); 9689 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9690 CPRIMOD_NULL_CHECK(wr_data_ptr); 9691 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9692 9693 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9694 9695 field_buf = num_sector; 9696 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_CTRL_NUM_SECf, &field_buf); 9697 9698 field_buf = grp_ptr_index; 9699 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_CTRL_GROUP_PTRf, &field_buf); 9700 9701 _SOC_IF_ERR_EXIT 9702 (soc_mem_write(unit, local_mem, blk_num, group_id, wr_data_ptr)); 9703 9704 exit: 9705 sal_free(wr_data_ptr); 9706 SOC_FUNC_RETURN; 9707 } 9708 9709 int cprif_drv_tx_vsd_ctrl_group_config_get(int unit, int port, 9710 uint32 group_id, 9711 uint32* num_sector, 9712 uint32* grp_ptr_index) 9713 { 9714 int phy_port; 9715 int port_core_index; 9716 soc_mem_t local_mem; 9717 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_0m, 9718 CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_1m, 9719 CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_2m, 9720 CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_3m}; 9721 9722 uint32 *rd_data_ptr; 9723 uint32 field_buf; 9724 uint32 num_words; 9725 uint32 blk_num=0; 9726 SOC_INIT_FUNC_DEFS; 9727 9728 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9729 port_core_index = ((phy_port-1)%4); 9730 9731 local_mem = mem_select[port_core_index]; 9732 9733 num_words = soc_mem_entry_words(unit, local_mem); 9734 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9735 CPRIMOD_NULL_CHECK(rd_data_ptr); 9736 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9737 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9738 9739 _SOC_IF_ERR_EXIT 9740 (soc_mem_read(unit, local_mem, blk_num , group_id, rd_data_ptr)); 9741 9742 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_CTRL_NUM_SECf, &field_buf); 9743 *num_sector = field_buf; 9744 9745 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_CTRL_GROUP_PTRf, &field_buf); 9746 *grp_ptr_index = field_buf; 9747 exit: 9748 sal_free(rd_data_ptr); 9749 SOC_FUNC_RETURN; 9750 } 9751 9752 int cprif_drv_tx_vsd_ctrl_group_assign_ptr_set(int unit, int port, 9753 uint32 ptr_index, 9754 uint32 sec_num) 9755 { 9756 int phy_port; 9757 int port_core_index; 9758 soc_mem_t local_mem; 9759 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_0m, 9760 CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_1m, 9761 CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_2m, 9762 CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_3m}; 9763 uint32 *wr_data_ptr; 9764 uint32 field_buf; 9765 uint32 num_words; 9766 uint32 blk_num=0; 9767 SOC_INIT_FUNC_DEFS; 9768 9769 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9770 port_core_index = ((phy_port-1)%4); 9771 9772 local_mem = mem_select[port_core_index]; 9773 9774 num_words = soc_mem_entry_words(unit, local_mem); 9775 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9776 CPRIMOD_NULL_CHECK(wr_data_ptr); 9777 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9778 9779 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9780 9781 field_buf = sec_num; 9782 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_CTRL_SECTORf, &field_buf); 9783 9784 9785 _SOC_IF_ERR_EXIT 9786 (soc_mem_write(unit, local_mem, blk_num, ptr_index, wr_data_ptr)); 9787 9788 exit: 9789 sal_free(wr_data_ptr); 9790 SOC_FUNC_RETURN; 9791 } 9792 9793 int cprif_drv_tx_vsd_ctrl_group_assign_ptr_get(int unit, int port, 9794 uint32 ptr_index, 9795 uint32* sec_num) 9796 { 9797 int phy_port; 9798 int port_core_index; 9799 soc_mem_t local_mem; 9800 soc_mem_t mem_select[] = { CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_0m, 9801 CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_1m, 9802 CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_2m, 9803 CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_3m}; 9804 9805 uint32 *rd_data_ptr; 9806 uint32 field_buf; 9807 uint32 num_words; 9808 uint32 blk_num=0; 9809 SOC_INIT_FUNC_DEFS; 9810 9811 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9812 port_core_index = ((phy_port-1)%4); 9813 9814 local_mem = mem_select[port_core_index]; 9815 9816 num_words = soc_mem_entry_words(unit, local_mem); 9817 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9818 CPRIMOD_NULL_CHECK(rd_data_ptr); 9819 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9820 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9821 9822 _SOC_IF_ERR_EXIT 9823 (soc_mem_read(unit, local_mem, blk_num , ptr_index, rd_data_ptr)); 9824 9825 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_CTRL_SECTORf, &field_buf); 9826 *sec_num = field_buf; 9827 9828 exit: 9829 sal_free(rd_data_ptr); 9830 SOC_FUNC_RETURN; 9831 } 9832 9833 9834 int cprif_drv_tx_vsd_ctrl_config_set(int unit, int port, const cprif_cpri_vsd_config_t* config_info) 9835 { 9836 uint32 copy_id=0xff; 9837 uint64 ctrl_mask; 9838 uint32 reg_val=0; 9839 9840 /* 9841 * Clear the control mask before updating the config to stop the processing. 9842 */ 9843 9844 SOC_IF_ERROR_RETURN 9845 (cprif_drv_tx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 9846 9847 COMPILER_64_ZERO(ctrl_mask); 9848 if (copy_id == 0){ 9849 SOC_IF_ERROR_RETURN 9850 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL1r(unit, port,ctrl_mask)); 9851 SOC_IF_ERROR_RETURN 9852 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL1r(unit, port,ctrl_mask)); 9853 copy_id = 1; /* new copy id */ 9854 } else { /* copy_id is 1 */ 9855 SOC_IF_ERROR_RETURN 9856 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL0r(unit, port,ctrl_mask)); 9857 SOC_IF_ERROR_RETURN 9858 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL0r(unit, port,ctrl_mask)); 9859 copy_id = 0; /* new copy id */ 9860 } 9861 9862 SOC_IF_ERROR_RETURN 9863 (cprif_drv_tx_vsd_ctrl_copy_id_set(unit, port, copy_id)); 9864 9865 /* 9866 * Update the vsd ctrl configuration. 9867 */ 9868 9869 SOC_IF_ERROR_RETURN 9870 (READ_CPRI_TXFRM_CWA_VSD_CTRL_CTRLr(unit, port, ®_val)); 9871 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, ®_val, TX_CWA_VSD_CTRL_BYTE_ORDERf, config_info->byte_order); 9872 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, ®_val, TX_CWA_VSD_CTRL_FLOW_BYTESf, config_info->flow_bytes); 9873 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, ®_val, TX_CWA_VSD_CTRL_SCHAN_STEPf, config_info->sub_channel_steps); 9874 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, ®_val, TX_CWA_VSD_CTRL_SCHAN_BYTESf, config_info->sub_channel_num_bytes); 9875 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, ®_val, TX_CWA_VSD_CTRL_SCHAN_SIZEf, config_info->sub_channel_size); 9876 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, ®_val, TX_CWA_VSD_CTRL_SCHAN_STARTf, config_info->sub_channel_start); 9877 SOC_IF_ERROR_RETURN 9878 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_CTRLr(unit, port, reg_val)); 9879 9880 SOC_IF_ERROR_RETURN 9881 (READ_CPRI_TXFRM_CWA_VSD_CTRL_CFGr(unit, port, ®_val)); 9882 soc_reg_field_set(unit, CPRI_TXFRM_CWA_VSD_CTRL_CFGr, ®_val, TX_CWA_VSD_CTRL_QUEUE_NUMf, config_info->queue_num); 9883 SOC_IF_ERROR_RETURN 9884 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_CFGr(unit, port, reg_val)); 9885 9886 SOC_IF_ERROR_RETURN 9887 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK0_CTRL2r(unit, port,config_info->rsvd_mask[0])); 9888 SOC_IF_ERROR_RETURN 9889 (WRITE_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK1_CTRL2r(unit, port,config_info->rsvd_mask[1])); 9890 9891 return SOC_E_NONE; 9892 } 9893 9894 int cprif_drv_tx_vsd_ctrl_config_get(int unit, int port, cprif_cpri_vsd_config_t* config_info) 9895 { 9896 uint32 reg_val=0; 9897 9898 SOC_IF_ERROR_RETURN 9899 (READ_CPRI_TXFRM_CWA_VSD_CTRL_CTRLr(unit, port, ®_val)); 9900 9901 config_info->byte_order = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, reg_val, TX_CWA_VSD_CTRL_BYTE_ORDERf); 9902 config_info->flow_bytes = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, reg_val, TX_CWA_VSD_CTRL_FLOW_BYTESf); 9903 config_info->sub_channel_steps = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, reg_val, TX_CWA_VSD_CTRL_SCHAN_STEPf); 9904 config_info->sub_channel_num_bytes = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, reg_val, TX_CWA_VSD_CTRL_SCHAN_BYTESf); 9905 config_info->sub_channel_size = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, reg_val, TX_CWA_VSD_CTRL_SCHAN_SIZEf); 9906 config_info->sub_channel_start = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CTRLr, reg_val, TX_CWA_VSD_CTRL_SCHAN_STARTf); 9907 9908 SOC_IF_ERROR_RETURN 9909 (READ_CPRI_TXFRM_CWA_VSD_CTRL_CFGr(unit, port, ®_val)); 9910 config_info->queue_num = soc_reg_field_get(unit, CPRI_TXFRM_CWA_VSD_CTRL_CFGr, reg_val, TX_CWA_VSD_CTRL_QUEUE_NUMf); 9911 9912 SOC_IF_ERROR_RETURN 9913 (READ_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK0_CTRL2r(unit, port, &config_info->rsvd_mask[0])); 9914 9915 SOC_IF_ERROR_RETURN 9916 (READ_CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK1_CTRL2r(unit, port, &config_info->rsvd_mask[1])); 9917 9918 return SOC_E_NONE; 9919 } 9920 int cprif_drv_encap_tag_to_flow_id_set(int unit, int port, 9921 uint32 tag_id, 9922 uint32 flow_id) 9923 { 9924 int phy_port; 9925 int port_core_index; 9926 soc_mem_t local_mem; 9927 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_CTL_FLOWID_TAB_0m, 9928 CPRI_ENCAP_QUE_CTL_FLOWID_TAB_1m, 9929 CPRI_ENCAP_QUE_CTL_FLOWID_TAB_2m, 9930 CPRI_ENCAP_QUE_CTL_FLOWID_TAB_3m}; 9931 uint32 *wr_data_ptr; 9932 uint32 field_buf; 9933 uint32 num_words; 9934 uint32 blk_num=0; 9935 SOC_INIT_FUNC_DEFS; 9936 9937 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9938 port_core_index = ((phy_port-1)%4); 9939 9940 local_mem = mem_select[port_core_index]; 9941 9942 num_words = soc_mem_entry_words(unit, local_mem); 9943 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9944 CPRIMOD_NULL_CHECK(wr_data_ptr); 9945 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 9946 9947 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 9948 9949 field_buf = flow_id; 9950 soc_mem_field_set(unit, local_mem, wr_data_ptr, QUEUE_ENCAP_CTL_FLOWIDf, &field_buf); 9951 9952 9953 _SOC_IF_ERR_EXIT 9954 (soc_mem_write(unit, local_mem, blk_num, tag_id, wr_data_ptr)); 9955 9956 exit: 9957 sal_free(wr_data_ptr); 9958 SOC_FUNC_RETURN; 9959 } 9960 9961 int cprif_drv_encap_tag_to_flow_id_get(int unit, int port, 9962 uint32 tag_id, 9963 uint32* flow_id) 9964 { 9965 int phy_port; 9966 int port_core_index; 9967 soc_mem_t local_mem; 9968 soc_mem_t mem_select[] = { CPRI_ENCAP_QUE_CTL_FLOWID_TAB_0m, 9969 CPRI_ENCAP_QUE_CTL_FLOWID_TAB_0m, 9970 CPRI_ENCAP_QUE_CTL_FLOWID_TAB_0m, 9971 CPRI_ENCAP_QUE_CTL_FLOWID_TAB_0m}; 9972 9973 uint32 *rd_data_ptr; 9974 uint32 field_buf; 9975 uint32 num_words; 9976 uint32 blk_num=0; 9977 SOC_INIT_FUNC_DEFS; 9978 9979 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 9980 port_core_index = ((phy_port-1)%4); 9981 9982 local_mem = mem_select[port_core_index]; 9983 9984 num_words = soc_mem_entry_words(unit, local_mem); 9985 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 9986 CPRIMOD_NULL_CHECK(rd_data_ptr); 9987 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 9988 9989 _SOC_IF_ERR_EXIT 9990 (soc_mem_read(unit, local_mem, blk_num , tag_id, rd_data_ptr)); 9991 9992 soc_mem_field_get(unit, local_mem, rd_data_ptr, QUEUE_ENCAP_CTL_FLOWIDf, &field_buf); 9993 *flow_id = field_buf; 9994 9995 exit: 9996 sal_free(rd_data_ptr); 9997 SOC_FUNC_RETURN; 9998 } 9999 10000 int cprif_drv_rx_vsd_raw_config_set(int unit, int port, 10001 uint32 index, 10002 cprif_cpri_vsd_raw_config_t* config) 10003 { 10004 int phy_port; 10005 int port_core_index; 10006 soc_mem_t local_mem; 10007 soc_mem_t mem_select[] = {CPRI_VSDRAW_LOC_TAB_CFG_0m, 10008 CPRI_VSDRAW_LOC_TAB_CFG_1m, 10009 CPRI_VSDRAW_LOC_TAB_CFG_2m, 10010 CPRI_VSDRAW_LOC_TAB_CFG_3m}; 10011 uint32 *wr_data_ptr; 10012 uint32 field_buf; 10013 uint32 num_words; 10014 uint32 blk_num=0; 10015 SOC_INIT_FUNC_DEFS; 10016 10017 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10018 port_core_index = ((phy_port-1)%4); 10019 10020 local_mem = mem_select[port_core_index]; 10021 10022 num_words = soc_mem_entry_words(unit, local_mem); 10023 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10024 CPRIMOD_NULL_CHECK(wr_data_ptr); 10025 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 10026 10027 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10028 10029 field_buf = config->schan_start; 10030 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_SCHAN_STARTf, &field_buf); 10031 10032 field_buf = config->schan_size; 10033 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_SCHAN_SIZEf, &field_buf); 10034 10035 field_buf = config->cw_select; 10036 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_CW_SELf, &field_buf); 10037 10038 field_buf = config->cw_size; 10039 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_CW_SIZEf, &field_buf); 10040 10041 10042 _SOC_IF_ERR_EXIT 10043 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 10044 10045 exit: 10046 sal_free(wr_data_ptr); 10047 SOC_FUNC_RETURN; 10048 } 10049 10050 int cprif_drv_rx_vsd_raw_config_get(int unit, int port, 10051 uint32 index, 10052 cprif_cpri_vsd_raw_config_t* config) 10053 { 10054 int phy_port; 10055 int port_core_index; 10056 soc_mem_t local_mem; 10057 soc_mem_t mem_select[] = {CPRI_VSDRAW_LOC_TAB_CFG_0m, 10058 CPRI_VSDRAW_LOC_TAB_CFG_1m, 10059 CPRI_VSDRAW_LOC_TAB_CFG_2m, 10060 CPRI_VSDRAW_LOC_TAB_CFG_3m}; 10061 uint32 *rd_data_ptr; 10062 uint32 field_buf; 10063 uint32 num_words; 10064 uint32 blk_num=0; 10065 SOC_INIT_FUNC_DEFS; 10066 10067 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10068 port_core_index = ((phy_port-1)%4); 10069 10070 local_mem = mem_select[port_core_index]; 10071 10072 num_words = soc_mem_entry_words(unit, local_mem); 10073 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10074 CPRIMOD_NULL_CHECK(rd_data_ptr); 10075 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 10076 10077 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10078 10079 _SOC_IF_ERR_EXIT 10080 (soc_mem_read(unit, local_mem, blk_num , index, rd_data_ptr)); 10081 10082 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_SCHAN_STARTf, &field_buf); 10083 config->schan_start = field_buf; 10084 10085 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_SCHAN_SIZEf, &field_buf); 10086 config->schan_size = field_buf; 10087 10088 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_CW_SELf, &field_buf); 10089 config->cw_select = field_buf; 10090 10091 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_CW_SIZEf, &field_buf); 10092 config->cw_size = field_buf; 10093 10094 exit: 10095 sal_free(rd_data_ptr); 10096 SOC_FUNC_RETURN; 10097 } 10098 10099 10100 int cprif_drv_rx_vsd_raw_filter_config_set(int unit, int port, 10101 uint32 index, 10102 cprif_cpri_rx_vsd_raw_filter_config_t* config) 10103 { 10104 int phy_port; 10105 int port_core_index; 10106 soc_mem_t local_mem; 10107 soc_mem_t mem_select[] = {CPRI_VSDRAW_FLT_TAB_CFG_0m, 10108 CPRI_VSDRAW_FLT_TAB_CFG_1m, 10109 CPRI_VSDRAW_FLT_TAB_CFG_2m, 10110 CPRI_VSDRAW_FLT_TAB_CFG_3m}; 10111 uint32 *wr_data_ptr; 10112 uint32 field_buf; 10113 uint32 num_words; 10114 uint32 blk_num=0; 10115 SOC_INIT_FUNC_DEFS; 10116 10117 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10118 port_core_index = ((phy_port-1)%4); 10119 10120 local_mem = mem_select[port_core_index]; 10121 10122 num_words = soc_mem_entry_words(unit, local_mem); 10123 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10124 CPRIMOD_NULL_CHECK(wr_data_ptr); 10125 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 10126 10127 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10128 10129 field_buf = config->filter_mode; 10130 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_FILTER_MODEf, &field_buf); 10131 10132 field_buf = config->hfn_index; 10133 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_HFN_INDEXf, &field_buf); 10134 10135 field_buf = config->hfn_modulo; 10136 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_HFN_MODULOf, &field_buf); 10137 10138 field_buf = config->match_offset; 10139 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_MATCH_OFFSETf, &field_buf); 10140 10141 field_buf = config->match_value; 10142 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_MATCH_VALUEf, &field_buf); 10143 10144 field_buf = config->match_mask; 10145 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_MATCH_MASKf, &field_buf); 10146 10147 field_buf = config->queue_num; 10148 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_QUEUE_NUMf, &field_buf); 10149 10150 10151 _SOC_IF_ERR_EXIT 10152 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 10153 10154 exit: 10155 sal_free(wr_data_ptr); 10156 SOC_FUNC_RETURN; 10157 } 10158 10159 int cprif_drv_rx_vsd_raw_filter_config_get(int unit, int port, 10160 uint32 index, 10161 cprif_cpri_rx_vsd_raw_filter_config_t* config) 10162 { 10163 int phy_port; 10164 int port_core_index; 10165 soc_mem_t local_mem; 10166 soc_mem_t mem_select[] = {CPRI_VSDRAW_FLT_TAB_CFG_0m, 10167 CPRI_VSDRAW_FLT_TAB_CFG_1m, 10168 CPRI_VSDRAW_FLT_TAB_CFG_2m, 10169 CPRI_VSDRAW_FLT_TAB_CFG_3m}; 10170 uint32 *rd_data_ptr; 10171 uint32 field_buf; 10172 uint32 num_words; 10173 uint32 blk_num=0; 10174 SOC_INIT_FUNC_DEFS; 10175 10176 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10177 port_core_index = ((phy_port-1)%4); 10178 10179 local_mem = mem_select[port_core_index]; 10180 10181 num_words = soc_mem_entry_words(unit, local_mem); 10182 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10183 CPRIMOD_NULL_CHECK(rd_data_ptr); 10184 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 10185 10186 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10187 _SOC_IF_ERR_EXIT 10188 (soc_mem_read(unit, local_mem, blk_num , index, rd_data_ptr)); 10189 10190 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_FILTER_MODEf, &field_buf); 10191 config->filter_mode = field_buf; 10192 10193 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_HFN_INDEXf, &field_buf); 10194 config->hfn_index = field_buf; 10195 10196 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_HFN_MODULOf, &field_buf); 10197 config->hfn_modulo = field_buf; 10198 10199 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_MATCH_OFFSETf, &field_buf); 10200 config->match_offset = field_buf; 10201 10202 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_MATCH_VALUEf, &field_buf); 10203 config->match_value = field_buf; 10204 10205 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_MATCH_MASKf, &field_buf); 10206 config->match_mask = field_buf; 10207 10208 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_QUEUE_NUMf, &field_buf); 10209 config->queue_num = field_buf; 10210 10211 exit: 10212 sal_free(rd_data_ptr); 10213 SOC_FUNC_RETURN; 10214 } 10215 10216 10217 int cprif_drv_tx_vsd_raw_config_set(int unit, int port, 10218 uint32 index, 10219 cprif_cpri_vsd_raw_config_t* config) 10220 { 10221 int phy_port; 10222 int port_core_index; 10223 soc_mem_t local_mem; 10224 soc_mem_t mem_select[] = {CPRI_CWA_VSD_RAW_LOC_TAB_CFG_0m, 10225 CPRI_CWA_VSD_RAW_LOC_TAB_CFG_1m, 10226 CPRI_CWA_VSD_RAW_LOC_TAB_CFG_2m, 10227 CPRI_CWA_VSD_RAW_LOC_TAB_CFG_3m}; 10228 uint32 *wr_data_ptr; 10229 uint32 field_buf; 10230 uint32 num_words; 10231 uint32 blk_num=0; 10232 SOC_INIT_FUNC_DEFS; 10233 10234 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10235 port_core_index = ((phy_port-1)%4); 10236 10237 local_mem = mem_select[port_core_index]; 10238 10239 num_words = soc_mem_entry_words(unit, local_mem); 10240 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10241 CPRIMOD_NULL_CHECK(wr_data_ptr); 10242 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 10243 10244 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10245 10246 field_buf = config->schan_start; 10247 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_SCHAN_STARTf, &field_buf); 10248 10249 field_buf = config->schan_size; 10250 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_SCHAN_SIZEf, &field_buf); 10251 10252 field_buf = config->cw_select; 10253 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_CW_SELf, &field_buf); 10254 10255 field_buf = config->cw_size; 10256 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_CW_SIZEf, &field_buf); 10257 10258 10259 _SOC_IF_ERR_EXIT 10260 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 10261 10262 exit: 10263 sal_free(wr_data_ptr); 10264 SOC_FUNC_RETURN; 10265 } 10266 10267 int cprif_drv_tx_vsd_raw_config_get(int unit, int port, 10268 uint32 index, 10269 cprif_cpri_vsd_raw_config_t* config) 10270 { 10271 int phy_port; 10272 int port_core_index; 10273 soc_mem_t local_mem; 10274 soc_mem_t mem_select[] = {CPRI_CWA_VSD_RAW_LOC_TAB_CFG_0m, 10275 CPRI_CWA_VSD_RAW_LOC_TAB_CFG_1m, 10276 CPRI_CWA_VSD_RAW_LOC_TAB_CFG_2m, 10277 CPRI_CWA_VSD_RAW_LOC_TAB_CFG_3m}; 10278 uint32 *rd_data_ptr; 10279 uint32 field_buf; 10280 uint32 num_words; 10281 uint32 blk_num=0; 10282 SOC_INIT_FUNC_DEFS; 10283 10284 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10285 port_core_index = ((phy_port-1)%4); 10286 10287 local_mem = mem_select[port_core_index]; 10288 10289 num_words = soc_mem_entry_words(unit, local_mem); 10290 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10291 CPRIMOD_NULL_CHECK(rd_data_ptr); 10292 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 10293 10294 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10295 10296 _SOC_IF_ERR_EXIT 10297 (soc_mem_read(unit, local_mem, blk_num , index, rd_data_ptr)); 10298 10299 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_SCHAN_STARTf, &field_buf); 10300 config->schan_start = field_buf; 10301 10302 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_SCHAN_SIZEf, &field_buf); 10303 config->schan_size = field_buf; 10304 10305 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_CW_SELf, &field_buf); 10306 config->cw_select = field_buf; 10307 10308 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_CW_SIZEf, &field_buf); 10309 config->cw_size = field_buf; 10310 10311 exit: 10312 sal_free(rd_data_ptr); 10313 SOC_FUNC_RETURN; 10314 } 10315 10316 10317 int cprif_drv_tx_vsd_raw_filter_config_set(int unit, int port, 10318 uint32 index, 10319 cprif_cpri_tx_vsd_raw_filter_config_t* config) 10320 { 10321 int phy_port; 10322 int port_core_index; 10323 soc_mem_t local_mem; 10324 soc_mem_t mem_select[] = {CPRI_CWA_VSD_RAW_MAP_TAB_CFG_0m, 10325 CPRI_CWA_VSD_RAW_MAP_TAB_CFG_1m, 10326 CPRI_CWA_VSD_RAW_MAP_TAB_CFG_2m, 10327 CPRI_CWA_VSD_RAW_MAP_TAB_CFG_3m}; 10328 uint32 *wr_data_ptr; 10329 uint32 field_buf; 10330 uint32 num_words; 10331 uint32 blk_num=0; 10332 SOC_INIT_FUNC_DEFS; 10333 10334 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10335 port_core_index = ((phy_port-1)%4); 10336 10337 local_mem = mem_select[port_core_index]; 10338 10339 num_words = soc_mem_entry_words(unit, local_mem); 10340 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10341 CPRIMOD_NULL_CHECK(wr_data_ptr); 10342 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 10343 10344 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10345 10346 field_buf = config->queue_num; 10347 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_QUEUE_NUMf, &field_buf); 10348 10349 field_buf = config->map_mode; 10350 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_MAP_MODEf, &field_buf); 10351 10352 field_buf = config->repeat_mode; 10353 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_REPEAT_MODEf, &field_buf); 10354 10355 field_buf = config->bfn0_filter_enable; 10356 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_BFN0_FILTER_MODEf, &field_buf); 10357 10358 field_buf = config->bfn1_filter_enable; 10359 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_BFN1_FILTER_MODEf, &field_buf); 10360 10361 field_buf = config->hfn_index; 10362 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_HFN_INDEXf, &field_buf); 10363 10364 field_buf = config->hfn_modulo; 10365 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_HFN_MODULOf, &field_buf); 10366 10367 field_buf = config->idle_value; 10368 soc_mem_field_set(unit, local_mem, wr_data_ptr, VSD_RAW_IDLE_VALUEf, &field_buf); 10369 10370 10371 _SOC_IF_ERR_EXIT 10372 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 10373 10374 exit: 10375 sal_free(wr_data_ptr); 10376 SOC_FUNC_RETURN; 10377 } 10378 10379 int cprif_drv_tx_vsd_raw_filter_config_get(int unit, int port, 10380 uint32 index, 10381 cprif_cpri_tx_vsd_raw_filter_config_t* config) 10382 { 10383 int phy_port; 10384 int port_core_index; 10385 soc_mem_t local_mem; 10386 soc_mem_t mem_select[] = {CPRI_CWA_VSD_RAW_MAP_TAB_CFG_0m, 10387 CPRI_CWA_VSD_RAW_MAP_TAB_CFG_1m, 10388 CPRI_CWA_VSD_RAW_MAP_TAB_CFG_2m, 10389 CPRI_CWA_VSD_RAW_MAP_TAB_CFG_3m}; 10390 uint32 *rd_data_ptr; 10391 uint32 field_buf; 10392 uint32 num_words; 10393 uint32 blk_num=0; 10394 SOC_INIT_FUNC_DEFS; 10395 10396 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10397 port_core_index = ((phy_port-1)%4); 10398 10399 local_mem = mem_select[port_core_index]; 10400 10401 num_words = soc_mem_entry_words(unit, local_mem); 10402 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10403 CPRIMOD_NULL_CHECK(rd_data_ptr); 10404 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 10405 10406 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10407 _SOC_IF_ERR_EXIT 10408 (soc_mem_read(unit, local_mem, blk_num , index, rd_data_ptr)); 10409 10410 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_QUEUE_NUMf, &field_buf); 10411 config->queue_num = field_buf; 10412 10413 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_MAP_MODEf, &field_buf); 10414 config->map_mode = field_buf; 10415 10416 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_REPEAT_MODEf, &field_buf); 10417 config->repeat_mode = field_buf; 10418 10419 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_BFN0_FILTER_MODEf, &field_buf); 10420 config->bfn0_filter_enable = field_buf; 10421 10422 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_BFN1_FILTER_MODEf, &field_buf); 10423 config->bfn1_filter_enable = field_buf; 10424 10425 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_HFN_INDEXf, &field_buf); 10426 config->hfn_index = field_buf; 10427 10428 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_HFN_MODULOf, &field_buf); 10429 config->hfn_modulo = field_buf; 10430 10431 soc_mem_field_get(unit, local_mem, rd_data_ptr, VSD_RAW_IDLE_VALUEf, &field_buf); 10432 config->idle_value = field_buf; 10433 10434 exit: 10435 sal_free(rd_data_ptr); 10436 SOC_FUNC_RETURN; 10437 } 10438 10439 int cprif_drv_tx_vsd_raw_radio_frame_filter_set(int unit, int port_num, 10440 uint32 bfn0_value, 10441 uint32 bfn0_mask, 10442 uint32 bfn1_value, 10443 uint32 bfn1_mask) 10444 { 10445 uint64 vsd_raw_ctrl, val64; 10446 10447 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_VSD_RAW_CTRLr(unit, port_num, &vsd_raw_ctrl)); 10448 COMPILER_64_SET(val64, 0, bfn0_value); 10449 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, &vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN0_VALUEf, val64); 10450 COMPILER_64_SET(val64, 0, bfn0_mask); 10451 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, &vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN0_MASKf, val64); 10452 COMPILER_64_SET(val64, 0, bfn1_value); 10453 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, &vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN1_VALUEf, val64); 10454 COMPILER_64_SET(val64, 0, bfn1_mask); 10455 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, &vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN1_MASKf, val64); 10456 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_CWA_VSD_RAW_CTRLr(unit, port_num, vsd_raw_ctrl)); 10457 return SOC_E_NONE; 10458 } 10459 10460 int cprif_drv_tx_vsd_raw_radio_frame_filter_get(int unit, int port_num, 10461 uint32* bfn0_value, 10462 uint32* bfn0_mask, 10463 uint32* bfn1_value, 10464 uint32* bfn1_mask) 10465 { 10466 uint64 vsd_raw_ctrl; 10467 10468 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_VSD_RAW_CTRLr(unit, port_num, &vsd_raw_ctrl)); 10469 10470 *bfn0_value = soc_reg64_field32_get(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN0_VALUEf); 10471 *bfn0_mask = soc_reg64_field32_get(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN0_MASKf); 10472 *bfn1_value = soc_reg64_field32_get(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN1_VALUEf); 10473 *bfn1_mask = soc_reg64_field32_get(unit, CPRI_TXFRM_CWA_VSD_RAW_CTRLr, vsd_raw_ctrl, TX_CWA_VSD_RAW_BFN1_MASKf); 10474 10475 return SOC_E_NONE; 10476 } 10477 10478 int cprif_drv_rx_brcm_rsvd5_config_set(int unit, int port, 10479 uint32 schan_start, uint32 schan_size, 10480 uint32 queue_num, int parity_disable) 10481 { 10482 uint32 reg_val=0; 10483 SOC_INIT_FUNC_DEFS; 10484 10485 10486 soc_reg_field_set(unit, BRCM_RESERVED_CPM_315r, ®_val, 10487 BRCM_RESERVED_CPM_315_0f, schan_start); 10488 10489 soc_reg_field_set(unit, BRCM_RESERVED_CPM_315r, ®_val, 10490 BRCM_RESERVED_CPM_315_1f, schan_size); 10491 10492 soc_reg_field_set(unit, BRCM_RESERVED_CPM_315r, ®_val, 10493 BRCM_RESERVED_CPM_315_2f, parity_disable?1:0); 10494 10495 _SOC_IF_ERR_EXIT(WRITE_BRCM_RESERVED_CPM_315r(unit, port, reg_val)); 10496 10497 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_300r(unit, port, ®_val)); 10498 10499 soc_reg_field_set(unit, BRCM_RESERVED_CPM_300r, ®_val, 10500 BRCM_RESERVED_CPM_300_0f, queue_num); 10501 10502 _SOC_IF_ERR_EXIT(WRITE_BRCM_RESERVED_CPM_300r(unit, port, reg_val)); 10503 10504 10505 exit: 10506 SOC_FUNC_RETURN; 10507 10508 } 10509 10510 int cprif_drv_rx_brcm_rsvd5_config_get(int unit, int port, 10511 uint32* schan_start, uint32* schan_size, 10512 uint32* queue_num, int* parity_disable) 10513 { 10514 uint32 reg_val=0; 10515 uint32 field_buf=0; 10516 SOC_INIT_FUNC_DEFS; 10517 10518 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_315r(unit, port, ®_val)); 10519 *schan_start = soc_reg_field_get(unit, BRCM_RESERVED_CPM_315r, reg_val, 10520 BRCM_RESERVED_CPM_315_0f); 10521 10522 *schan_size = soc_reg_field_get(unit, BRCM_RESERVED_CPM_315r, reg_val, 10523 BRCM_RESERVED_CPM_315_1f); 10524 10525 field_buf = soc_reg_field_get(unit, BRCM_RESERVED_CPM_315r, reg_val, 10526 BRCM_RESERVED_CPM_315_2f); 10527 if (field_buf) { 10528 *parity_disable = 1; 10529 } else { 10530 *parity_disable = 0; 10531 } 10532 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_300r(unit, port, ®_val)); 10533 10534 *queue_num = soc_reg_field_get(unit, BRCM_RESERVED_CPM_300r, reg_val, 10535 BRCM_RESERVED_CPM_300_0f); 10536 10537 exit: 10538 SOC_FUNC_RETURN; 10539 } 10540 10541 int cprif_drv_tx_brcm_rsvd5_config_set(int unit, int port, 10542 uint32 schan_start, 10543 uint32 schan_size, 10544 uint32 queue_num, 10545 int crc_enable) 10546 { 10547 uint64 reg_val; 10548 uint64 val64; 10549 SOC_INIT_FUNC_DEFS; 10550 10551 COMPILER_64_ZERO(reg_val); 10552 COMPILER_64_ZERO(val64); 10553 COMPILER_64_SET(val64, 0, schan_start); 10554 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_0r, ®_val, 10555 BRCM_RESERVED_CPM_0_3f, val64); 10556 10557 COMPILER_64_SET(val64, 0, schan_size); 10558 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_0r, ®_val, 10559 BRCM_RESERVED_CPM_0_2f, val64); 10560 10561 COMPILER_64_SET(val64, 0, queue_num); 10562 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_0r, ®_val, 10563 BRCM_RESERVED_CPM_0_0f, val64); 10564 10565 COMPILER_64_SET(val64, 0, crc_enable?1:0); 10566 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_0r, ®_val, 10567 BRCM_RESERVED_CPM_0_1f, val64); 10568 10569 _SOC_IF_ERR_EXIT(WRITE_BRCM_RESERVED_CPM_0r(unit, port, reg_val)); 10570 10571 exit: 10572 SOC_FUNC_RETURN; 10573 } 10574 10575 10576 int cprif_drv_tx_brcm_rsvd5_config_get(int unit, int port, 10577 uint32* schan_start, 10578 uint32* schan_size, 10579 uint32* queue_num, 10580 int* crc_enable) 10581 { 10582 uint64 reg_val; 10583 uint64 field_buf; 10584 SOC_INIT_FUNC_DEFS; 10585 10586 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_0r(unit, port, ®_val)); 10587 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_0r, reg_val, 10588 BRCM_RESERVED_CPM_0_3f); 10589 10590 *schan_start = COMPILER_64_LO(field_buf); 10591 10592 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_0r, reg_val, 10593 BRCM_RESERVED_CPM_0_2f); 10594 *schan_size = COMPILER_64_LO(field_buf); 10595 10596 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_0r, reg_val, 10597 BRCM_RESERVED_CPM_0_0f); 10598 *queue_num = COMPILER_64_LO(field_buf); 10599 10600 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_0r, reg_val, 10601 BRCM_RESERVED_CPM_0_1f); 10602 if (!COMPILER_64_IS_ZERO(field_buf)) { 10603 *crc_enable = 1; 10604 } else { 10605 *crc_enable = 0; 10606 } 10607 exit: 10608 SOC_FUNC_RETURN; 10609 } 10610 10611 int cprif_drv_rx_gcw_config_set(int unit, int port, 10612 uint32 index, 10613 cprif_cpri_rx_gcw_config_t* config) 10614 { 10615 int phy_port; 10616 int port_core_index; 10617 soc_mem_t local_mem; 10618 soc_mem_t mem_select[] = {CPRI_GCW_CFG_TAB_CFG_0m, 10619 CPRI_GCW_CFG_TAB_CFG_1m, 10620 CPRI_GCW_CFG_TAB_CFG_2m, 10621 CPRI_GCW_CFG_TAB_CFG_3m}; 10622 uint32 *wr_data_ptr; 10623 uint32 field_buf; 10624 uint32 num_words; 10625 uint32 blk_num=0; 10626 SOC_INIT_FUNC_DEFS; 10627 10628 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10629 port_core_index = ((phy_port-1)%4); 10630 10631 local_mem = mem_select[port_core_index]; 10632 10633 num_words = soc_mem_entry_words(unit, local_mem); 10634 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10635 CPRIMOD_NULL_CHECK(wr_data_ptr); 10636 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 10637 10638 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10639 10640 field_buf = config->Ns; 10641 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_NSf, &field_buf); 10642 10643 field_buf = config->Xs; 10644 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_XSf, &field_buf); 10645 10646 field_buf = config->Y; 10647 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_Yf, &field_buf); 10648 10649 10650 field_buf = config->mask; 10651 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_MASKf, &field_buf); 10652 10653 field_buf = config->filter_mode; 10654 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_FILTER_MODEf, &field_buf); 10655 10656 10657 field_buf = config->hfn_index; 10658 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_HFN_INDEXf, &field_buf); 10659 10660 field_buf = config->hfn_modulo; 10661 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_HFN_MODULOf, &field_buf); 10662 10663 field_buf = config->match_value; 10664 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_MATCH_VALUEf, &field_buf); 10665 10666 field_buf = config->match_mask; 10667 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_MATCH_MASKf, &field_buf); 10668 10669 10670 10671 _SOC_IF_ERR_EXIT 10672 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 10673 10674 exit: 10675 sal_free(wr_data_ptr); 10676 SOC_FUNC_RETURN; 10677 } 10678 10679 int cprif_drv_rx_gcw_config_get(int unit, int port, 10680 uint32 index, 10681 cprif_cpri_rx_gcw_config_t* config) 10682 { 10683 int phy_port; 10684 int port_core_index; 10685 soc_mem_t local_mem; 10686 soc_mem_t mem_select[] = {CPRI_GCW_CFG_TAB_CFG_0m, 10687 CPRI_GCW_CFG_TAB_CFG_1m, 10688 CPRI_GCW_CFG_TAB_CFG_2m, 10689 CPRI_GCW_CFG_TAB_CFG_3m}; 10690 uint32 *rd_data_ptr; 10691 uint32 field_buf; 10692 uint32 num_words; 10693 uint32 blk_num=0; 10694 SOC_INIT_FUNC_DEFS; 10695 10696 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10697 port_core_index = ((phy_port-1)%4); 10698 10699 local_mem = mem_select[port_core_index]; 10700 10701 num_words = soc_mem_entry_words(unit, local_mem); 10702 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10703 CPRIMOD_NULL_CHECK(rd_data_ptr); 10704 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 10705 10706 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10707 10708 _SOC_IF_ERR_EXIT 10709 (soc_mem_read(unit, local_mem, blk_num , index, rd_data_ptr)); 10710 10711 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_NSf, &field_buf); 10712 config->Ns = field_buf; 10713 10714 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_XSf, &field_buf); 10715 config->Xs = field_buf; 10716 10717 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_Yf, &field_buf); 10718 config->Y = field_buf; 10719 10720 10721 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_MASKf, &field_buf); 10722 config->mask = field_buf; 10723 10724 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_FILTER_MODEf, &field_buf); 10725 config->filter_mode = field_buf; 10726 10727 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_HFN_INDEXf, &field_buf); 10728 config->hfn_index = field_buf; 10729 10730 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_HFN_MODULOf, &field_buf); 10731 config->hfn_modulo = field_buf; 10732 10733 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_MATCH_VALUEf, &field_buf); 10734 config->match_value = field_buf; 10735 10736 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_MATCH_MASKf, &field_buf); 10737 config->match_mask = field_buf; 10738 10739 exit: 10740 sal_free(rd_data_ptr); 10741 SOC_FUNC_RETURN; 10742 } 10743 10744 int cprif_drv_tx_gcw_config_set(int unit, int port, 10745 uint32 index, 10746 cprif_cpri_tx_gcw_config_t* config) 10747 { 10748 int phy_port; 10749 int port_core_index; 10750 soc_mem_t local_mem; 10751 soc_mem_t mem_select[] = {CPRI_CWA_GCW_CFG_TAB_CFG_0m, 10752 CPRI_CWA_GCW_CFG_TAB_CFG_1m, 10753 CPRI_CWA_GCW_CFG_TAB_CFG_2m, 10754 CPRI_CWA_GCW_CFG_TAB_CFG_3m}; 10755 uint32 *wr_data_ptr; 10756 uint32 field_buf; 10757 uint32 num_words; 10758 uint32 blk_num=0; 10759 SOC_INIT_FUNC_DEFS; 10760 10761 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10762 port_core_index = ((phy_port-1)%4); 10763 10764 local_mem = mem_select[port_core_index]; 10765 10766 num_words = soc_mem_entry_words(unit, local_mem); 10767 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10768 CPRIMOD_NULL_CHECK(wr_data_ptr); 10769 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 10770 10771 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10772 10773 field_buf = config->Ns; 10774 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_NSf, &field_buf); 10775 10776 field_buf = config->Xs; 10777 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_XSf, &field_buf); 10778 10779 field_buf = config->Y; 10780 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_Yf, &field_buf); 10781 10782 10783 field_buf = config->mask; 10784 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_MASKf, &field_buf); 10785 10786 field_buf = config->repeat_mode; 10787 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_REPEAT_MODEf, &field_buf); 10788 10789 field_buf = config->bfn0_filter_enable; 10790 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_BFN0_FILTER_MODEf, &field_buf); 10791 10792 field_buf = config->bfn1_filter_enable; 10793 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_BFN1_FILTER_MODEf, &field_buf); 10794 10795 10796 field_buf = config->hfn_index; 10797 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_HFN_INDEXf, &field_buf); 10798 10799 field_buf = config->hfn_modulo; 10800 soc_mem_field_set(unit, local_mem, wr_data_ptr, GCW_HFN_MODULOf, &field_buf); 10801 10802 _SOC_IF_ERR_EXIT 10803 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 10804 10805 exit: 10806 sal_free(wr_data_ptr); 10807 SOC_FUNC_RETURN; 10808 } 10809 10810 int cprif_drv_tx_gcw_config_get(int unit, int port, 10811 uint32 index, 10812 cprif_cpri_tx_gcw_config_t* config) 10813 { 10814 int phy_port; 10815 int port_core_index; 10816 soc_mem_t local_mem; 10817 soc_mem_t mem_select[] = {CPRI_CWA_GCW_CFG_TAB_CFG_0m, 10818 CPRI_CWA_GCW_CFG_TAB_CFG_1m, 10819 CPRI_CWA_GCW_CFG_TAB_CFG_2m, 10820 CPRI_CWA_GCW_CFG_TAB_CFG_3m}; 10821 uint32 *rd_data_ptr; 10822 uint32 field_buf; 10823 uint32 num_words; 10824 uint32 blk_num=0; 10825 SOC_INIT_FUNC_DEFS; 10826 10827 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10828 port_core_index = ((phy_port-1)%4); 10829 10830 local_mem = mem_select[port_core_index]; 10831 10832 num_words = soc_mem_entry_words(unit, local_mem); 10833 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 10834 CPRIMOD_NULL_CHECK(rd_data_ptr); 10835 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 10836 10837 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 10838 10839 _SOC_IF_ERR_EXIT 10840 (soc_mem_read(unit, local_mem, blk_num , index, rd_data_ptr)); 10841 10842 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_NSf, &field_buf); 10843 config->Ns = field_buf; 10844 10845 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_XSf, &field_buf); 10846 config->Xs = field_buf; 10847 10848 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_Yf, &field_buf); 10849 config->Y = field_buf; 10850 10851 10852 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_MASKf, &field_buf); 10853 config->mask = field_buf; 10854 10855 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_REPEAT_MODEf, &field_buf); 10856 config->repeat_mode = field_buf; 10857 10858 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_BFN0_FILTER_MODEf, &field_buf); 10859 config->bfn0_filter_enable = field_buf; 10860 10861 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_BFN1_FILTER_MODEf, &field_buf); 10862 config->bfn1_filter_enable = field_buf; 10863 10864 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_HFN_INDEXf, &field_buf); 10865 config->hfn_index = field_buf; 10866 10867 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_HFN_MODULOf, &field_buf); 10868 config->hfn_modulo = field_buf; 10869 10870 10871 exit: 10872 sal_free(rd_data_ptr); 10873 SOC_FUNC_RETURN; 10874 } 10875 10876 int cprif_drv_tx_gcw_filter_set(int unit, int port, 10877 uint32 bfn0_value, uint32 bfn0_mask, 10878 uint32 bfn1_value, uint32 bfn1_mask) 10879 { 10880 uint64 gcw_ctrl, val64; 10881 10882 COMPILER_64_ZERO(gcw_ctrl); 10883 COMPILER_64_SET(val64, 0, bfn0_value); 10884 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_GCWr, &gcw_ctrl, TX_CWA_GCW_BFN0_VALUEf, val64); 10885 10886 COMPILER_64_SET(val64, 0, bfn0_mask); 10887 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_GCWr, &gcw_ctrl, TX_CWA_GCW_BFN0_MASKf, val64); 10888 10889 COMPILER_64_SET(val64, 0, bfn1_value); 10890 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_GCWr, &gcw_ctrl, TX_CWA_GCW_BFN1_VALUEf, val64); 10891 10892 COMPILER_64_SET(val64, 0, bfn1_mask); 10893 soc_reg64_field_set(unit, CPRI_TXFRM_CWA_GCWr, &gcw_ctrl, TX_CWA_GCW_BFN1_MASKf, val64); 10894 10895 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_CWA_GCWr(unit, port, gcw_ctrl)); 10896 10897 return SOC_E_NONE; 10898 } 10899 10900 int cprif_drv_tx_gcw_filter_get(int unit, int port, 10901 uint32* bfn0_value, uint32* bfn0_mask, 10902 uint32* bfn1_value, uint32* bfn1_mask) 10903 { 10904 uint64 gcw_ctrl, val64; 10905 10906 COMPILER_64_ZERO(gcw_ctrl); 10907 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_GCWr(unit, port, &gcw_ctrl)); 10908 10909 val64 = soc_reg64_field_get(unit, CPRI_TXFRM_CWA_GCWr, gcw_ctrl, TX_CWA_GCW_BFN0_VALUEf); 10910 *bfn0_value = COMPILER_64_LO(val64); 10911 10912 val64 = soc_reg64_field_get(unit, CPRI_TXFRM_CWA_GCWr, gcw_ctrl, TX_CWA_GCW_BFN0_MASKf); 10913 *bfn0_mask = COMPILER_64_LO(val64); 10914 10915 val64 = soc_reg64_field_get(unit, CPRI_TXFRM_CWA_GCWr, gcw_ctrl, TX_CWA_GCW_BFN1_VALUEf); 10916 *bfn1_value = COMPILER_64_LO(val64); 10917 10918 val64 = soc_reg64_field_get(unit, CPRI_TXFRM_CWA_GCWr, gcw_ctrl, TX_CWA_GCW_BFN1_MASKf); 10919 *bfn1_mask = COMPILER_64_LO(val64); 10920 10921 return SOC_E_NONE; 10922 } 10923 10924 int cprif_drv_tx_control_word_set(int unit, int port, 10925 cprif_drv_tx_control_word_t* control) 10926 { 10927 uint32 reg_val; 10928 10929 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_L1r(unit, port, ®_val)); 10930 soc_reg_field_set(unit, CPRI_TXFRM_CWA_L1r, ®_val, TX_CWA_POINTER_Pf, control->enet_ptr ); 10931 soc_reg_field_set(unit, CPRI_TXFRM_CWA_L1r, ®_val, TX_CWA_L1_FUNCf, control->l1_fun); 10932 soc_reg_field_set(unit, CPRI_TXFRM_CWA_L1r, ®_val, TX_CWA_HDLC_BITRATEf, control->hdlc_rate); 10933 soc_reg_field_set(unit, CPRI_TXFRM_CWA_L1r, ®_val, TX_CWA_PROTOCOLf, control->protocol_ver); 10934 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_CWA_L1r(unit, port, reg_val)); 10935 return SOC_E_NONE; 10936 } 10937 10938 int cprif_drv_tx_control_word_size_set(int unit, int port, uint32 cw_size_in_bytes) 10939 { 10940 uint32 reg_val=0; 10941 10942 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_GENERALr(unit, port, 10943 ®_val)); 10944 10945 soc_reg_field_set(unit, CPRI_TXFRM_CWA_GENERALr, ®_val, TX_CWA_TCWf, 10946 cw_size_in_bytes); 10947 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_CWA_GENERALr(unit, port, 10948 reg_val)); 10949 10950 return SOC_E_NONE; 10951 } 10952 10953 int cprif_drv_tx_control_word_size_get(int unit, int port, uint32* cw_size_in_bytes) 10954 { 10955 uint32 reg_val=0; 10956 10957 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_CWA_GENERALr(unit, port, 10958 ®_val)); 10959 10960 *cw_size_in_bytes = soc_reg_field_get(unit, CPRI_TXFRM_CWA_GENERALr, reg_val, TX_CWA_TCWf); 10961 10962 return SOC_E_NONE; 10963 } 10964 10965 /* RSVD4 */ 10966 int cprif_drv_rsvd4_rx_control_message_config_set( int unit, int port, 10967 uint32 sm_queue_num, 10968 uint32 default_tag, 10969 uint32 no_match_tag) 10970 { 10971 uint32 reg_val; 10972 SOC_INIT_FUNC_DEFS; 10973 10974 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_300r(unit, port, ®_val)); 10975 10976 soc_reg_field_set(unit, BRCM_RESERVED_CPM_300r, ®_val, 10977 BRCM_RESERVED_CPM_300_0f, sm_queue_num); 10978 10979 _SOC_IF_ERR_EXIT(WRITE_BRCM_RESERVED_CPM_300r(unit, port, reg_val)); 10980 10981 10982 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_318r(unit, port, ®_val)); 10983 10984 soc_reg_field_set(unit, BRCM_RESERVED_CPM_318r, ®_val, 10985 BRCM_RESERVED_CPM_318_1f, default_tag); 10986 10987 soc_reg_field_set(unit, BRCM_RESERVED_CPM_318r, ®_val, 10988 BRCM_RESERVED_CPM_318_2f, no_match_tag); 10989 10990 _SOC_IF_ERR_EXIT(WRITE_BRCM_RESERVED_CPM_318r(unit, port, reg_val)); 10991 exit: 10992 SOC_FUNC_RETURN; 10993 } 10994 10995 int cprif_drv_rsvd4_rx_control_flow_config_set ( int unit, int port, 10996 uint32 control_flow_id, 10997 cprif_rsvd4_rx_ctrl_flow_config_t* config) 10998 { 10999 int phy_port; 11000 int port_core_index; 11001 soc_mem_t local_mem; 11002 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_339m, 11003 BRCM_RESERVED_CPM_340m, 11004 BRCM_RESERVED_CPM_341m, 11005 BRCM_RESERVED_CPM_342m}; 11006 uint32 *wr_data_ptr; 11007 uint32 field_buf; 11008 uint32 num_words; 11009 uint32 blk_num=0; 11010 SOC_INIT_FUNC_DEFS; 11011 11012 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11013 port_core_index = ((phy_port-1)%4); 11014 11015 local_mem = mem_select[port_core_index]; 11016 11017 num_words = soc_mem_entry_words(unit, local_mem); 11018 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11019 CPRIMOD_NULL_CHECK(wr_data_ptr); 11020 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 11021 11022 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11023 11024 field_buf = config->proc_type; 11025 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_339_0f, &field_buf); 11026 11027 field_buf = config->queue_num; 11028 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_339_1f, &field_buf); 11029 11030 field_buf = config->sync_profile; 11031 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_339_2f, &field_buf); 11032 11033 11034 field_buf = config->sync_enable; 11035 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_339_3f, &field_buf); 11036 11037 _SOC_IF_ERR_EXIT 11038 (soc_mem_write(unit, local_mem, blk_num, control_flow_id, wr_data_ptr)); 11039 exit: 11040 sal_free(wr_data_ptr); 11041 SOC_FUNC_RETURN; 11042 } 11043 11044 int cprif_drv_rsvd4_rx_control_flow_config_get( int unit, int port, 11045 uint32 control_flow_id, 11046 cprif_rsvd4_rx_ctrl_flow_config_t* config) 11047 11048 { 11049 int phy_port; 11050 int port_core_index; 11051 soc_mem_t local_mem; 11052 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_339m, 11053 BRCM_RESERVED_CPM_340m, 11054 BRCM_RESERVED_CPM_341m, 11055 BRCM_RESERVED_CPM_342m}; 11056 11057 uint32 *rd_data_ptr; 11058 uint32 field_buf; 11059 uint32 num_words; 11060 uint32 blk_num=0; 11061 SOC_INIT_FUNC_DEFS; 11062 11063 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11064 port_core_index = ((phy_port-1)%4); 11065 11066 local_mem = mem_select[port_core_index]; 11067 11068 num_words = soc_mem_entry_words(unit, local_mem); 11069 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11070 CPRIMOD_NULL_CHECK(rd_data_ptr); 11071 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 11072 11073 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11074 11075 _SOC_IF_ERR_EXIT 11076 (soc_mem_read(unit, local_mem, blk_num, control_flow_id, rd_data_ptr)); 11077 11078 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_339_0f, &field_buf); 11079 config->proc_type = field_buf; 11080 11081 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_339_1f, &field_buf); 11082 config->queue_num = field_buf; 11083 11084 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_339_2f, &field_buf); 11085 config->sync_profile= field_buf; 11086 11087 11088 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_339_3f, &field_buf); 11089 config->sync_enable= field_buf; 11090 11091 11092 exit: 11093 sal_free(rd_data_ptr); 11094 SOC_FUNC_RETURN; 11095 } 11096 11097 int cprif_drv_rx_control_flow_tag_option_set(int unit, int port, 11098 uint32 control_flow_id, 11099 uint32 tag_option) 11100 { 11101 uint32 reg_val; 11102 uint32 tag_opt; 11103 SOC_INIT_FUNC_DEFS; 11104 11105 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_318r(unit, port, ®_val)); 11106 11107 tag_opt = soc_reg_field_get(unit, BRCM_RESERVED_CPM_318r, reg_val, 11108 BRCM_RESERVED_CPM_318_0f); 11109 11110 if (tag_option) { 11111 tag_opt |= (0x1 << control_flow_id); 11112 } else { 11113 tag_opt &= ~(0x1 << control_flow_id); 11114 } 11115 11116 soc_reg_field_set(unit, BRCM_RESERVED_CPM_318r, ®_val, 11117 BRCM_RESERVED_CPM_318_0f, tag_opt); 11118 11119 _SOC_IF_ERR_EXIT(WRITE_BRCM_RESERVED_CPM_318r(unit, port, reg_val)); 11120 11121 exit: 11122 SOC_FUNC_RETURN; 11123 } 11124 11125 int cprif_drv_rx_sync_profile_entry_set (int unit, int port, 11126 uint32 profile_id, 11127 cprif_rsvd4_rx_sync_profile_entry_t* profile) 11128 { 11129 uint64 reg_val; 11130 uint64 val64; 11131 SOC_INIT_FUNC_DEFS; 11132 11133 COMPILER_64_ZERO(reg_val); 11134 COMPILER_64_ZERO(val64); 11135 COMPILER_64_SET(val64, 0, profile->bfn_offset); 11136 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_319r, ®_val, 11137 BRCM_RESERVED_CPM_319_2f, val64); 11138 11139 COMPILER_64_SET(val64, 0, profile->rfrm_offset); 11140 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_319r, ®_val, 11141 BRCM_RESERVED_CPM_319_1f, val64); 11142 11143 COMPILER_64_SET(val64, 0, profile->count_cycle); 11144 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_319r, ®_val, 11145 BRCM_RESERVED_CPM_319_0f, val64); 11146 switch (profile_id) { 11147 11148 case 0 : 11149 _SOC_IF_ERR_EXIT 11150 (WRITE_BRCM_RESERVED_CPM_319r(unit, port, reg_val)); 11151 break; 11152 case 1 : 11153 _SOC_IF_ERR_EXIT 11154 (WRITE_BRCM_RESERVED_CPM_320r(unit, port, reg_val)); 11155 break; 11156 case 2 : 11157 _SOC_IF_ERR_EXIT 11158 (WRITE_BRCM_RESERVED_CPM_321r(unit, port, reg_val)); 11159 break; 11160 case 3 : 11161 _SOC_IF_ERR_EXIT 11162 (WRITE_BRCM_RESERVED_CPM_322r(unit, port, reg_val)); 11163 break; 11164 default: 11165 LOG_CLI(("profile_id %d is out of range, between 0-3 ", profile_id)); 11166 return SOC_E_PARAM; 11167 break; 11168 } 11169 exit: 11170 SOC_FUNC_RETURN; 11171 11172 } 11173 11174 int cprif_drv_rx_sync_profile_entry_get (int unit, int port, 11175 uint32 profile_id, 11176 cprif_rsvd4_rx_sync_profile_entry_t* profile) 11177 { 11178 uint64 reg_val; 11179 uint64 field_buf; 11180 SOC_INIT_FUNC_DEFS; 11181 11182 COMPILER_64_SET(reg_val, 0, 0); 11183 COMPILER_64_SET(field_buf, 0, 0); 11184 11185 switch (profile_id) { 11186 11187 case 0 : 11188 _SOC_IF_ERR_EXIT 11189 (READ_BRCM_RESERVED_CPM_319r(unit, port, ®_val)); 11190 break; 11191 case 1 : 11192 _SOC_IF_ERR_EXIT 11193 (READ_BRCM_RESERVED_CPM_320r(unit, port, ®_val)); 11194 break; 11195 case 2 : 11196 _SOC_IF_ERR_EXIT 11197 (READ_BRCM_RESERVED_CPM_321r(unit, port, ®_val)); 11198 break; 11199 case 3 : 11200 _SOC_IF_ERR_EXIT 11201 (READ_BRCM_RESERVED_CPM_322r(unit, port, ®_val)); 11202 break; 11203 default: 11204 LOG_CLI(("profile_id %d is out of range, between 0-3 ", profile_id)); 11205 return SOC_E_PARAM; 11206 break; 11207 } 11208 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_319r, reg_val, 11209 BRCM_RESERVED_CPM_319_2f); 11210 11211 profile->bfn_offset = COMPILER_64_LO(field_buf); 11212 11213 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_319r, reg_val, 11214 BRCM_RESERVED_CPM_319_1f); 11215 profile->rfrm_offset = COMPILER_64_LO(field_buf); 11216 11217 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_319r, reg_val, 11218 BRCM_RESERVED_CPM_319_0f); 11219 profile->count_cycle = COMPILER_64_LO(field_buf); 11220 11221 exit: 11222 SOC_FUNC_RETURN; 11223 11224 } 11225 11226 int cprif_drv_rx_tag_config_set ( int unit, int port, 11227 uint32 default_tag, 11228 uint32 no_match_tag) 11229 { 11230 uint32 reg_val; 11231 SOC_INIT_FUNC_DEFS; 11232 11233 _SOC_IF_ERR_EXIT(READ_BRCM_RESERVED_CPM_318r(unit, port, ®_val)); 11234 11235 soc_reg_field_set(unit, BRCM_RESERVED_CPM_318r, ®_val, 11236 BRCM_RESERVED_CPM_318_1f, default_tag); 11237 11238 soc_reg_field_set(unit, BRCM_RESERVED_CPM_318r, ®_val, 11239 BRCM_RESERVED_CPM_318_2f, no_match_tag); 11240 11241 _SOC_IF_ERR_EXIT(WRITE_BRCM_RESERVED_CPM_318r(unit, port, reg_val)); 11242 exit: 11243 SOC_FUNC_RETURN; 11244 } 11245 11246 11247 int cprif_drv_rx_tag_gen_entry_set( int unit, int port, 11248 uint32 index, 11249 cprif_rx_tag_gen_entry_t* entry) 11250 { 11251 int phy_port; 11252 int port_core_index; 11253 soc_mem_t local_mem; 11254 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_335m, 11255 BRCM_RESERVED_CPM_336m, 11256 BRCM_RESERVED_CPM_337m, 11257 BRCM_RESERVED_CPM_338m}; 11258 uint32 *wr_data_ptr; 11259 uint32 field_buf; 11260 uint32 num_words; 11261 uint32 blk_num=0; 11262 SOC_INIT_FUNC_DEFS; 11263 11264 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11265 port_core_index = ((phy_port-1)%4); 11266 11267 local_mem = mem_select[port_core_index]; 11268 11269 num_words = soc_mem_entry_words(unit, local_mem); 11270 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11271 CPRIMOD_NULL_CHECK(wr_data_ptr); 11272 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 11273 11274 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11275 11276 field_buf = entry->valid; 11277 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_335_0f, &field_buf); 11278 11279 field_buf = entry->header; 11280 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_335_1f, &field_buf); 11281 11282 field_buf = entry->mask; 11283 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_335_2f, &field_buf); 11284 11285 11286 field_buf = entry->tag_id; 11287 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_335_3f, &field_buf); 11288 11289 field_buf = entry->rtwp_word_count; 11290 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_335_4f, &field_buf); 11291 11292 _SOC_IF_ERR_EXIT 11293 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 11294 exit: 11295 sal_free(wr_data_ptr); 11296 SOC_FUNC_RETURN; 11297 } 11298 11299 int cprif_drv_rx_tag_gen_entry_get( int unit, int port, 11300 uint32 index, 11301 cprif_rx_tag_gen_entry_t* entry) 11302 { 11303 int phy_port; 11304 int port_core_index; 11305 soc_mem_t local_mem; 11306 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_335m, 11307 BRCM_RESERVED_CPM_336m, 11308 BRCM_RESERVED_CPM_337m, 11309 BRCM_RESERVED_CPM_338m}; 11310 uint32 *rd_data_ptr; 11311 uint32 field_buf; 11312 uint32 num_words; 11313 uint32 blk_num=0; 11314 SOC_INIT_FUNC_DEFS; 11315 11316 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11317 port_core_index = ((phy_port-1)%4); 11318 11319 local_mem = mem_select[port_core_index]; 11320 11321 num_words = soc_mem_entry_words(unit, local_mem); 11322 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11323 CPRIMOD_NULL_CHECK(rd_data_ptr); 11324 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 11325 11326 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11327 11328 _SOC_IF_ERR_EXIT 11329 (soc_mem_read(unit, local_mem, blk_num, index, rd_data_ptr)); 11330 11331 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_335_0f, &field_buf); 11332 entry->valid = field_buf; 11333 11334 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_335_1f, &field_buf); 11335 entry->header = field_buf; 11336 11337 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_335_2f, &field_buf); 11338 entry->mask = field_buf; 11339 11340 11341 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_335_3f, &field_buf); 11342 entry->tag_id = field_buf; 11343 11344 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_335_4f, &field_buf); 11345 entry->rtwp_word_count = field_buf; 11346 11347 exit: 11348 sal_free(rd_data_ptr); 11349 SOC_FUNC_RETURN; 11350 } 11351 11352 int cprif_drv_brcm_rsvd4_tx_control_group_entry_set( int unit, int port, 11353 uint32 index, 11354 cprif_control_group_entry_t* entry) 11355 { 11356 int phy_port; 11357 int port_core_index; 11358 soc_mem_t local_mem; 11359 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_56m, 11360 BRCM_RESERVED_CPM_57m, 11361 BRCM_RESERVED_CPM_58m, 11362 BRCM_RESERVED_CPM_59m}; 11363 uint32 *wr_data_ptr; 11364 uint32 field_buf; 11365 uint32 num_words; 11366 uint32 blk_num=0; 11367 SOC_INIT_FUNC_DEFS; 11368 11369 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11370 port_core_index = ((phy_port-1)%4); 11371 11372 local_mem = mem_select[port_core_index]; 11373 11374 num_words = soc_mem_entry_words(unit, local_mem); 11375 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11376 CPRIMOD_NULL_CHECK(wr_data_ptr); 11377 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 11378 11379 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11380 11381 field_buf = entry->valid_mask; 11382 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_8f , &field_buf); 11383 11384 field_buf = entry->queue_num[0]; 11385 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_7f, &field_buf); 11386 11387 field_buf = entry->queue_num[1]; 11388 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_6f, &field_buf); 11389 11390 field_buf = entry->queue_num[2]; 11391 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_5f, &field_buf); 11392 11393 field_buf = entry->queue_num[3]; 11394 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_4f, &field_buf); 11395 11396 field_buf = entry->proc_type[0]; 11397 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_3f, &field_buf); 11398 11399 field_buf = entry->proc_type[1]; 11400 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_2f, &field_buf); 11401 11402 field_buf = entry->proc_type[2]; 11403 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_1f, &field_buf); 11404 11405 field_buf = entry->proc_type[3]; 11406 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_56_0f, &field_buf); 11407 11408 _SOC_IF_ERR_EXIT 11409 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 11410 exit: 11411 sal_free(wr_data_ptr); 11412 SOC_FUNC_RETURN; 11413 } 11414 11415 int cprif_drv_brcm_rsvd4_tx_control_group_entry_get( int unit, int port, 11416 uint32 index, 11417 cprif_control_group_entry_t* entry) 11418 { 11419 int phy_port; 11420 int port_core_index; 11421 soc_mem_t local_mem; 11422 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_56m, 11423 BRCM_RESERVED_CPM_57m, 11424 BRCM_RESERVED_CPM_58m, 11425 BRCM_RESERVED_CPM_59m}; 11426 uint32 *rd_data_ptr; 11427 uint32 field_buf; 11428 uint32 num_words; 11429 uint32 blk_num=0; 11430 SOC_INIT_FUNC_DEFS; 11431 11432 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11433 port_core_index = ((phy_port-1)%4); 11434 11435 local_mem = mem_select[port_core_index]; 11436 11437 num_words = soc_mem_entry_words(unit, local_mem); 11438 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11439 CPRIMOD_NULL_CHECK(rd_data_ptr); 11440 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 11441 11442 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11443 11444 _SOC_IF_ERR_EXIT 11445 (soc_mem_read(unit, local_mem, blk_num, index, rd_data_ptr)); 11446 11447 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_8f, &field_buf); 11448 entry->valid_mask = field_buf; 11449 11450 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_7f, &field_buf); 11451 entry->queue_num[0] = field_buf; 11452 11453 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_6f, &field_buf); 11454 entry->queue_num[1] = field_buf; 11455 11456 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_5f, &field_buf); 11457 entry->queue_num[2] = field_buf; 11458 11459 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_4f, &field_buf); 11460 entry->queue_num[3] = field_buf; 11461 11462 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_3f, &field_buf); 11463 entry->proc_type[0] = field_buf; 11464 11465 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_2f, &field_buf); 11466 entry->proc_type[1] = field_buf; 11467 11468 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_1f, &field_buf); 11469 entry->proc_type[2] = field_buf; 11470 11471 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_56_0f, &field_buf); 11472 entry->proc_type[3] = field_buf; 11473 11474 exit: 11475 sal_free(rd_data_ptr); 11476 SOC_FUNC_RETURN; 11477 } 11478 11479 int cprif_drv_tx_control_eth_msg_config_set(int unit, int port, 11480 uint32 msg_node, 11481 uint32 msg_subnode, 11482 uint32 msg_type, 11483 uint32 msg_padding) 11484 { 11485 uint64 reg_val, val64; 11486 11487 SOC_IF_ERROR_RETURN 11488 (READ_BRCM_RESERVED_CPM_5r(unit, port, ®_val)); 11489 11490 COMPILER_64_SET(val64, 0, msg_node); 11491 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_5r, ®_val, BRCM_RESERVED_CPM_5_3f, val64); 11492 COMPILER_64_SET(val64, 0,msg_subnode); 11493 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_5r, ®_val, BRCM_RESERVED_CPM_5_2f, val64); 11494 COMPILER_64_SET(val64, 0, msg_type); 11495 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_5r, ®_val, BRCM_RESERVED_CPM_5_1f, val64); 11496 COMPILER_64_SET(val64, 0, msg_padding); 11497 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_5r, ®_val, BRCM_RESERVED_CPM_5_0f, val64); 11498 SOC_IF_ERROR_RETURN 11499 (WRITE_BRCM_RESERVED_CPM_5r(unit, port, reg_val)); 11500 11501 return SOC_E_NONE; 11502 } 11503 11504 int cprif_drv_tx_control_eth_msg_config_get(int unit, int port, 11505 uint32* msg_node, 11506 uint32* msg_subnode, 11507 uint32* msg_type, 11508 uint32* msg_padding) 11509 { 11510 uint64 reg_val; 11511 uint64 field_buf; 11512 11513 SOC_IF_ERROR_RETURN 11514 (READ_BRCM_RESERVED_CPM_5r(unit, port, ®_val)); 11515 11516 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_5r, reg_val, BRCM_RESERVED_CPM_5_3f); 11517 *msg_node = COMPILER_64_LO(field_buf); 11518 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_5r, reg_val, BRCM_RESERVED_CPM_5_2f); 11519 *msg_subnode = COMPILER_64_LO(field_buf); 11520 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_5r, reg_val, BRCM_RESERVED_CPM_5_1f); 11521 *msg_type=COMPILER_64_LO(field_buf); 11522 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_5r, reg_val, BRCM_RESERVED_CPM_5_0f); 11523 *msg_padding =COMPILER_64_LO(field_buf); 11524 11525 return SOC_E_NONE; 11526 } 11527 11528 int cprif_drv_tx_control_single_msg_config_set(int unit, int port, 11529 uint32 msg_id, 11530 uint32 msg_type) 11531 { 11532 uint64 reg_val, val64; 11533 11534 SOC_IF_ERROR_RETURN 11535 (READ_BRCM_RESERVED_CPM_5r(unit, port, ®_val)); 11536 11537 COMPILER_64_SET(val64, 0, msg_id); 11538 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_5r, ®_val, BRCM_RESERVED_CPM_5_4f, val64); 11539 COMPILER_64_SET(val64, 0, msg_type); 11540 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_5r, ®_val, BRCM_RESERVED_CPM_5_5f, val64); 11541 SOC_IF_ERROR_RETURN 11542 (WRITE_BRCM_RESERVED_CPM_5r(unit, port, reg_val)); 11543 11544 return SOC_E_NONE; 11545 } 11546 11547 int cprif_drv_tx_control_single_tunnel_msg_config_set(int unit, int port, 11548 uint32 crc_option) 11549 { 11550 uint64 reg_val, val64; 11551 11552 SOC_IF_ERROR_RETURN 11553 (READ_BRCM_RESERVED_CPM_5r(unit, port, ®_val)); 11554 11555 COMPILER_64_SET(val64, 0, crc_option); 11556 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_5r, ®_val, BRCM_RESERVED_CPM_5_6f, val64); 11557 SOC_IF_ERROR_RETURN 11558 (WRITE_BRCM_RESERVED_CPM_5r(unit, port, reg_val)); 11559 11560 return SOC_E_NONE; 11561 } 11562 11563 int cprif_drv_tx_control_single_msg_config_get(int unit, int port, 11564 uint32* msg_id, 11565 uint32* msg_type) 11566 { 11567 uint64 reg_val; 11568 uint64 field_buf; 11569 11570 SOC_IF_ERROR_RETURN 11571 (READ_BRCM_RESERVED_CPM_5r(unit, port, ®_val)); 11572 11573 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_5r, reg_val, BRCM_RESERVED_CPM_5_4f); 11574 *msg_id = COMPILER_64_LO(field_buf); 11575 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_5r, reg_val, BRCM_RESERVED_CPM_5_5f); 11576 *msg_type = COMPILER_64_LO(field_buf); 11577 11578 return SOC_E_NONE; 11579 } 11580 11581 11582 int cprif_drv_brcm_rsvd4_tx_control_flow_config_set( int unit, int port, 11583 uint32 flow_id, 11584 uint32 queue_num, 11585 uint32 proc_type) 11586 { 11587 int phy_port; 11588 int port_core_index; 11589 soc_mem_t local_mem; 11590 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_52m, 11591 BRCM_RESERVED_CPM_53m, 11592 BRCM_RESERVED_CPM_54m, 11593 BRCM_RESERVED_CPM_55m}; 11594 uint32 *wr_data_ptr; 11595 uint32 field_buf; 11596 uint32 num_words; 11597 uint32 blk_num=0; 11598 SOC_INIT_FUNC_DEFS; 11599 11600 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11601 port_core_index = ((phy_port-1)%4); 11602 11603 local_mem = mem_select[port_core_index]; 11604 11605 num_words = soc_mem_entry_words(unit, local_mem); 11606 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11607 CPRIMOD_NULL_CHECK(wr_data_ptr); 11608 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 11609 11610 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11611 11612 11613 field_buf = queue_num; 11614 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_52_0f, &field_buf); 11615 11616 11617 field_buf = proc_type; 11618 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_52_1f,&field_buf); 11619 11620 11621 _SOC_IF_ERR_EXIT 11622 (soc_mem_write(unit, local_mem, blk_num, flow_id, wr_data_ptr)); 11623 exit: 11624 sal_free(wr_data_ptr); 11625 SOC_FUNC_RETURN; 11626 } 11627 11628 int cprif_drv_brcm_rsvd4_tx_control_flow_config_get( int unit, int port, 11629 uint32 flow_id, 11630 uint32* queue_num, 11631 uint32* proc_type) 11632 { 11633 int phy_port; 11634 int port_core_index; 11635 soc_mem_t local_mem; 11636 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_52m, 11637 BRCM_RESERVED_CPM_53m, 11638 BRCM_RESERVED_CPM_54m, 11639 BRCM_RESERVED_CPM_55m}; 11640 uint32 *rd_data_ptr; 11641 uint32 field_buf; 11642 uint32 num_words; 11643 uint32 blk_num=0; 11644 SOC_INIT_FUNC_DEFS; 11645 11646 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11647 port_core_index = ((phy_port-1)%4); 11648 11649 local_mem = mem_select[port_core_index]; 11650 11651 num_words = soc_mem_entry_words(unit, local_mem); 11652 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11653 CPRIMOD_NULL_CHECK(rd_data_ptr); 11654 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 11655 11656 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11657 11658 _SOC_IF_ERR_EXIT 11659 (soc_mem_read(unit, local_mem, blk_num, flow_id, rd_data_ptr)); 11660 11661 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_52_0f, &field_buf); 11662 *queue_num = field_buf; 11663 11664 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_52_1f, &field_buf); 11665 *proc_type = field_buf; 11666 11667 11668 exit: 11669 sal_free(rd_data_ptr); 11670 SOC_FUNC_RETURN; 11671 } 11672 11673 int cprif_drv_brcm_rsvd4_control_flow_header_index_set( int unit, int port, 11674 uint32 roe_flow_id, 11675 uint32 header_index) 11676 { 11677 int phy_port; 11678 int port_core_index; 11679 soc_mem_t local_mem; 11680 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_44m, 11681 BRCM_RESERVED_CPM_45m, 11682 BRCM_RESERVED_CPM_46m, 11683 BRCM_RESERVED_CPM_47m}; 11684 uint32 *wr_data_ptr; 11685 uint32 field_buf; 11686 uint32 num_words; 11687 uint32 blk_num=0; 11688 SOC_INIT_FUNC_DEFS; 11689 11690 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11691 port_core_index = ((phy_port-1)%4); 11692 11693 local_mem = mem_select[port_core_index]; 11694 11695 num_words = soc_mem_entry_words(unit, local_mem); 11696 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11697 CPRIMOD_NULL_CHECK(wr_data_ptr); 11698 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 11699 11700 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11701 11702 11703 field_buf = header_index; 11704 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_44_0f, &field_buf); 11705 11706 _SOC_IF_ERR_EXIT 11707 (soc_mem_write(unit, local_mem, blk_num, roe_flow_id, wr_data_ptr)); 11708 exit: 11709 sal_free(wr_data_ptr); 11710 SOC_FUNC_RETURN; 11711 } 11712 11713 int cprif_drv_brcm_rsvd4_control_flow_header_index_get( int unit, int port, 11714 uint32 roe_flow_id, 11715 uint32* header_index) 11716 { 11717 int phy_port; 11718 int port_core_index; 11719 soc_mem_t local_mem; 11720 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_44m, 11721 BRCM_RESERVED_CPM_45m, 11722 BRCM_RESERVED_CPM_46m, 11723 BRCM_RESERVED_CPM_47m}; 11724 uint32 *rd_data_ptr; 11725 uint32 field_buf; 11726 uint32 num_words; 11727 uint32 blk_num=0; 11728 SOC_INIT_FUNC_DEFS; 11729 11730 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11731 port_core_index = ((phy_port-1)%4); 11732 11733 local_mem = mem_select[port_core_index]; 11734 11735 num_words = soc_mem_entry_words(unit, local_mem); 11736 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11737 CPRIMOD_NULL_CHECK(rd_data_ptr); 11738 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 11739 11740 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11741 11742 _SOC_IF_ERR_EXIT 11743 (soc_mem_read(unit, local_mem, blk_num, roe_flow_id, rd_data_ptr)); 11744 11745 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_44_0f, &field_buf); 11746 *header_index= field_buf; 11747 11748 exit: 11749 sal_free(rd_data_ptr); 11750 SOC_FUNC_RETURN; 11751 } 11752 11753 int cprif_drv_brcm_rsvd4_control_header_entry_set( int unit, int port, 11754 uint32 index, 11755 uint32 header_node, 11756 uint32 header_subnode, 11757 uint32 node) 11758 { 11759 int phy_port; 11760 int port_core_index; 11761 soc_mem_t local_mem; 11762 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_48m, 11763 BRCM_RESERVED_CPM_49m, 11764 BRCM_RESERVED_CPM_50m, 11765 BRCM_RESERVED_CPM_51m}; 11766 uint32 *wr_data_ptr; 11767 uint32 field_buf; 11768 uint32 num_words; 11769 uint32 blk_num=0; 11770 SOC_INIT_FUNC_DEFS; 11771 11772 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11773 port_core_index = ((phy_port-1)%4); 11774 11775 local_mem = mem_select[port_core_index]; 11776 11777 num_words = soc_mem_entry_words(unit, local_mem); 11778 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11779 CPRIMOD_NULL_CHECK(wr_data_ptr); 11780 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 11781 11782 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11783 11784 field_buf = (header_node << 5)|header_subnode; 11785 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_48_1f, &field_buf); 11786 11787 field_buf = node; 11788 soc_mem_field_set(unit, local_mem, wr_data_ptr, BRCM_RESERVED_CPM_48_0f, &field_buf); 11789 11790 _SOC_IF_ERR_EXIT 11791 (soc_mem_write(unit, local_mem, blk_num, index, wr_data_ptr)); 11792 exit: 11793 sal_free(wr_data_ptr); 11794 SOC_FUNC_RETURN; 11795 } 11796 11797 int cprif_drv_brcm_rsvd4_control_header_entry_get( int unit, int port, 11798 uint32 index, 11799 uint32* header_node, 11800 uint32* header_subnode, 11801 uint32* node) 11802 { 11803 int phy_port; 11804 int port_core_index; 11805 soc_mem_t local_mem; 11806 soc_mem_t mem_select[] = {BRCM_RESERVED_CPM_48m, 11807 BRCM_RESERVED_CPM_49m, 11808 BRCM_RESERVED_CPM_50m, 11809 BRCM_RESERVED_CPM_51m}; 11810 uint32 *rd_data_ptr; 11811 uint32 field_buf; 11812 uint32 num_words; 11813 uint32 blk_num=0; 11814 SOC_INIT_FUNC_DEFS; 11815 11816 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11817 port_core_index = ((phy_port-1)%4); 11818 11819 local_mem = mem_select[port_core_index]; 11820 11821 num_words = soc_mem_entry_words(unit, local_mem); 11822 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 11823 CPRIMOD_NULL_CHECK(rd_data_ptr); 11824 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 11825 11826 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 11827 11828 _SOC_IF_ERR_EXIT 11829 (soc_mem_read(unit, local_mem, blk_num, index, rd_data_ptr)); 11830 11831 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_48_1f, &field_buf); 11832 *header_node = field_buf >> 5; 11833 *header_subnode = field_buf & 0x1F; 11834 11835 soc_mem_field_get(unit, local_mem, rd_data_ptr, BRCM_RESERVED_CPM_48_1f, &field_buf); 11836 *node = field_buf; 11837 exit: 11838 sal_free(rd_data_ptr); 11839 SOC_FUNC_RETURN; 11840 } 11841 11842 int cprif_drv_stuff_rsrv_bits_set( int unit, int port, 11843 int roe_stuffing_bit, 11844 int roe_reserved_bit) 11845 { 11846 uint32 data32; 11847 SOC_INIT_FUNC_DEFS; 11848 11849 SOC_IF_ERROR_RETURN(READ_CPRI_TXFRM_GENERAL_CTRLr(unit, port, 11850 &data32)); 11851 soc_reg_field_set(unit, CPRI_TXFRM_GENERAL_CTRLr, &data32, CA_STUFF_BITf, 11852 roe_stuffing_bit); 11853 soc_reg_field_set(unit, CPRI_TXFRM_GENERAL_CTRLr, &data32, BFA_RSRV_BITf, 11854 roe_reserved_bit); 11855 SOC_IF_ERROR_RETURN(WRITE_CPRI_TXFRM_GENERAL_CTRLr(unit, port, 11856 data32)); 11857 11858 SOC_FUNC_RETURN; 11859 } 11860 11861 int cprif_drv_pmd_reset_seq(int unit, int port, int pmd_touched) 11862 { 11863 int val; 11864 uint32 reg_val; 11865 SOC_INIT_FUNC_DEFS; 11866 11867 if(pmd_touched == 0) { 11868 SOC_IF_ERROR_RETURN(cprif_drv_cip_top_ctrl_get(unit, port, &val)); 11869 if(val == 0) { 11870 SOC_IF_ERROR_RETURN(READ_CLPORT_XGXS0_CTRL_REGr(unit, port, ®_val)); 11871 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, ®_val, RSTB_HWf, 1); 11872 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, ®_val, PWRDWNf, 0); 11873 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, ®_val, IDDQf, 0); 11874 SOC_IF_ERROR_RETURN(WRITE_CLPORT_XGXS0_CTRL_REGr(unit, port, reg_val)); 11875 } else { 11876 /* removing iddq from cpri side */ 11877 SOC_IF_ERROR_RETURN(READ_CLPORT_XGXS0_CTRL_REGr(unit, port, ®_val)); 11878 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, ®_val, RSTB_HWf, 1); 11879 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, ®_val, PWRDWNf, 0); 11880 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, ®_val, IDDQf, 0); 11881 SOC_IF_ERROR_RETURN(WRITE_CLPORT_XGXS0_CTRL_REGr(unit, port, reg_val)); 11882 SOC_IF_ERROR_RETURN(cprif_drv_pmd_iddq_set(unit, port, 0)); 11883 } 11884 } 11885 SOC_FUNC_RETURN; 11886 } 11887 11888 int cprif_drv_cpri_port_interrupt_enable_set(int unit, int port, 11889 int int_dir, int enable) 11890 { 11891 uint32 rval = 0, new_rval = 0; 11892 soc_field_t rx_fields[4] = { 11893 PORT_0_RX_INTERRUPT_ENABLEf, 11894 PORT_1_RX_INTERRUPT_ENABLEf, 11895 PORT_2_RX_INTERRUPT_ENABLEf, 11896 PORT_3_RX_INTERRUPT_ENABLEf 11897 }; 11898 soc_field_t tx_fields[4] = { 11899 PORT_0_TX_INTERRUPT_ENABLEf, 11900 PORT_1_TX_INTERRUPT_ENABLEf, 11901 PORT_2_TX_INTERRUPT_ENABLEf, 11902 PORT_3_TX_INTERRUPT_ENABLEf 11903 }; 11904 soc_field_t rx_field = INVALIDf; 11905 soc_field_t tx_field = INVALIDf; 11906 int phy_port = 0; 11907 int port_index = 0; 11908 SOC_INIT_FUNC_DEFS; 11909 11910 _SOC_IF_ERR_EXIT(READ_CPRI_INTR_ENABLEr(unit, port, &rval)); 11911 11912 new_rval = rval; 11913 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11914 port_index = ((phy_port-1)%4); 11915 11916 if (int_dir & CPRIF_RX_INTR) { 11917 rx_field = rx_fields[port_index]; 11918 soc_reg_field_set(unit, CPRI_INTR_ENABLEr, &new_rval, rx_field, enable); 11919 } 11920 11921 if (int_dir & CPRIF_TX_INTR) { 11922 tx_field = tx_fields[port_index]; 11923 soc_reg_field_set(unit, CPRI_INTR_ENABLEr, &new_rval, tx_field, enable); 11924 } 11925 11926 if (rx_field != INVALIDf || tx_field != INVALIDf) { 11927 if (rval != new_rval) { 11928 _SOC_IF_ERR_EXIT(WRITE_CPRI_INTR_ENABLEr(unit, port, new_rval)); 11929 } 11930 } else { 11931 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Unknown interrupt type")); 11932 } 11933 11934 exit: 11935 SOC_FUNC_RETURN; 11936 } 11937 11938 int cprif_drv_cpri_port_interrupt_enable_get(int unit, int port, 11939 int int_dir, int *enable) 11940 { 11941 uint32 rval; 11942 soc_field_t rx_fields[4] = { 11943 PORT_0_RX_INTERRUPT_ENABLEf, 11944 PORT_1_RX_INTERRUPT_ENABLEf, 11945 PORT_2_RX_INTERRUPT_ENABLEf, 11946 PORT_3_RX_INTERRUPT_ENABLEf 11947 }; 11948 soc_field_t tx_fields[4] = { 11949 PORT_0_TX_INTERRUPT_ENABLEf, 11950 PORT_1_TX_INTERRUPT_ENABLEf, 11951 PORT_2_TX_INTERRUPT_ENABLEf, 11952 PORT_3_TX_INTERRUPT_ENABLEf 11953 }; 11954 soc_field_t field = INVALIDf; 11955 int phy_port = 0; 11956 int port_index = 0; 11957 SOC_INIT_FUNC_DEFS; 11958 11959 _SOC_IF_ERR_EXIT(READ_CPRI_INTR_ENABLEr(unit, port, &rval)); 11960 11961 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 11962 port_index = ((phy_port-1)%4); 11963 11964 switch (int_dir) { 11965 case CPRIF_RX_INTR: 11966 field = rx_fields[port_index]; 11967 break; 11968 case CPRIF_TX_INTR: 11969 field = tx_fields[port_index]; 11970 break; 11971 default: 11972 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 11973 ("Unknown interrupt type")); 11974 break; 11975 } 11976 11977 *enable = soc_reg_field_get(unit, CPRI_INTR_ENABLEr, rval, field); 11978 11979 exit: 11980 SOC_FUNC_RETURN; 11981 } 11982 11983 int cprif_drv_cpri_port_interrupt_status_get(int unit, int port, 11984 int *status) 11985 { 11986 uint32 rval; 11987 soc_field_t fields[8] = { 11988 PORT_0_RX_INTERRUPT_STATUSf, 11989 PORT_1_RX_INTERRUPT_STATUSf, 11990 PORT_2_RX_INTERRUPT_STATUSf, 11991 PORT_3_RX_INTERRUPT_STATUSf, 11992 PORT_0_TX_INTERRUPT_STATUSf, 11993 PORT_1_TX_INTERRUPT_STATUSf, 11994 PORT_2_TX_INTERRUPT_STATUSf, 11995 PORT_3_TX_INTERRUPT_STATUSf 11996 }; 11997 uint32 port_intr_status[8] = { 11998 CPRIF_PORT_0_RX_INTR, 11999 CPRIF_PORT_1_RX_INTR, 12000 CPRIF_PORT_2_RX_INTR, 12001 CPRIF_PORT_3_RX_INTR, 12002 CPRIF_PORT_0_TX_INTR, 12003 CPRIF_PORT_1_TX_INTR, 12004 CPRIF_PORT_2_TX_INTR, 12005 CPRIF_PORT_3_TX_INTR 12006 }; 12007 int i = 0; 12008 SOC_INIT_FUNC_DEFS; 12009 12010 _SOC_IF_ERR_EXIT(READ_CPRI_INTR_STATUSr(unit, port, &rval)); 12011 12012 12013 for (i = 0; i < sizeof(fields)/sizeof(soc_field_t); i++) { 12014 if (soc_reg_field_get(unit, CPRI_INTR_STATUSr, rval, fields[i])) { 12015 *status |= port_intr_status[i]; 12016 } 12017 } 12018 12019 exit: 12020 SOC_FUNC_RETURN; 12021 } 12022 12023 /* 12024 * Enable CPRI port RX interrupts. 12025 * RX interrupts can be of 3 types 12026 * 1. RX operational error type interrupts. 12027 * 2. RX functional error type interrupts. 12028 * 3. RX memory ECC error type interrupts. 12029 */ 12030 int cprif_drv_cpri_port_rx_interrupts_enable_set(int unit, 12031 int port, 12032 int rx_intr_flags, 12033 int enable) 12034 { 12035 uint32 rval, new_rval; 12036 uint32 rx_op_err = 0; 12037 uint32 rx_func_err = 0; 12038 uint32 rx_ecc_err = 0; 12039 SOC_INIT_FUNC_DEFS; 12040 12041 _SOC_IF_ERR_EXIT(READ_CPRI_RX_INTR_ENABLEr(unit, port, &rval)); 12042 12043 new_rval = rval; 12044 if (rx_intr_flags & CPRIF_RX_OP_ERR_INTR) { 12045 rx_op_err = soc_reg_field_get(unit, CPRI_RX_INTR_ENABLEr, 12046 rval, RX_OP_ERR_INTERRUPT_ENABLEf); 12047 if (enable != rx_op_err) { 12048 soc_reg_field_set(unit, CPRI_RX_INTR_ENABLEr, &new_rval, 12049 RX_OP_ERR_INTERRUPT_ENABLEf, enable); 12050 } 12051 } 12052 12053 if (rx_intr_flags & CPRIF_RX_FUNC_ERR_INTR) { 12054 rx_func_err = soc_reg_field_get(unit, CPRI_RX_INTR_ENABLEr, 12055 rval, RX_FUNC_INTERRUPT_ENABLEf); 12056 if (enable != rx_func_err) { 12057 soc_reg_field_set(unit, CPRI_RX_INTR_ENABLEr, &new_rval, 12058 RX_FUNC_INTERRUPT_ENABLEf, enable); 12059 } 12060 } 12061 12062 if (rx_intr_flags & CPRIF_RX_ECC_ERR_INTR) { 12063 rx_ecc_err = soc_reg_field_get(unit, CPRI_RX_INTR_ENABLEr, 12064 rval, RX_ECC_INTERRUPT_ENABLEf); 12065 if (enable != rx_ecc_err) { 12066 soc_reg_field_set(unit, CPRI_RX_INTR_ENABLEr, &new_rval, 12067 RX_ECC_INTERRUPT_ENABLEf, enable); 12068 } 12069 } 12070 12071 if (new_rval != rval) { 12072 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_INTR_ENABLEr(unit, port, new_rval)); 12073 } 12074 12075 exit: 12076 SOC_FUNC_RETURN; 12077 } 12078 12079 /* 12080 * Get CPRI port RX interrupts enable status. 12081 */ 12082 int cprif_drv_cpri_port_rx_interrupt_enable_get(int unit, 12083 int port, 12084 int rx_intr_flags, 12085 int *status) 12086 { 12087 uint32 rval; 12088 soc_field_t field = INVALIDf; 12089 SOC_INIT_FUNC_DEFS; 12090 12091 _SOC_IF_ERR_EXIT(READ_CPRI_RX_INTR_ENABLEr(unit, port, &rval)); 12092 12093 switch (rx_intr_flags) { 12094 case CPRIF_RX_OP_ERR_INTR: 12095 field = RX_OP_ERR_INTERRUPT_ENABLEf; 12096 break; 12097 case CPRIF_RX_FUNC_ERR_INTR: 12098 field = RX_FUNC_INTERRUPT_ENABLEf; 12099 break; 12100 case CPRIF_RX_ECC_ERR_INTR: 12101 field = RX_ECC_INTERRUPT_ENABLEf; 12102 break; 12103 default: 12104 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 12105 ("Unknown Rx interrupt type")); 12106 break; 12107 } 12108 12109 if (field != INVALIDf) { 12110 *status = soc_reg_field_get(unit, CPRI_RX_INTR_ENABLEr, rval, field); 12111 } 12112 12113 exit: 12114 SOC_FUNC_RETURN; 12115 } 12116 12117 /* 12118 * Enable CPRI port RX Operational error interrupts. 12119 * RX Lane Operational Error Interrupts. 12120 * 1. RX Lane Combined DATA Queue Overflow Error 12121 * 2. RX Lane Combined Control Queue Overflow Error 12122 * 3. RX Lane Combined GSM Time-stamp Error 12123 * 4. RX Lane MISC WQ and CDC Overflow Error 12124 * 5. RX RX Lane RxFramer BRCM_RSVD4 Time-stamp 12125 * detection Error 12126 */ 12127 int cprif_drv_cpri_port_rx_op_err_interrupts_enable_set(int unit, 12128 int port, 12129 int rx_op_err_intr_flags, 12130 int enable) 12131 { 12132 uint32 rval, new_rval; 12133 SOC_INIT_FUNC_DEFS; 12134 12135 _SOC_IF_ERR_EXIT(READ_CPRI_RX_OP_ERR_INTR_ENABLEr(unit, port, &rval)); 12136 12137 new_rval = rval; 12138 if (rx_op_err_intr_flags & CPRI_INTR_RX_ENCAP_DATA_Q_OVRFLOW) { 12139 if(!(soc_reg_field_get(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, 12140 new_rval, 12141 RX_ENCAP_DATA_Q_OVFL_ERR_INTERRUPT_ENABLEf))) { 12142 soc_reg_field_set(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, &new_rval, 12143 RX_ENCAP_DATA_Q_OVFL_ERR_INTERRUPT_ENABLEf, 12144 enable); 12145 } 12146 } 12147 12148 if (rx_op_err_intr_flags & CPRI_INTR_RX_ENCAP_CTRL_Q_OVRFLOW) { 12149 if(!(soc_reg_field_get(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, 12150 new_rval, 12151 RX_ENCAP_CTRL_Q_OVFL_ERR_INTERRUPT_ENABLEf))) { 12152 soc_reg_field_set(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, &new_rval, 12153 RX_ENCAP_CTRL_Q_OVFL_ERR_INTERRUPT_ENABLEf, 12154 enable); 12155 } 12156 } 12157 12158 if (rx_op_err_intr_flags & CPRI_INTR_RX_ENCAP_GSM_TIMESTAMP) { 12159 if(!(soc_reg_field_get(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, 12160 new_rval, BRCM_RESERVED_CPM_301_2f))) { 12161 soc_reg_field_set(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, &new_rval, 12162 BRCM_RESERVED_CPM_301_2f, enable); 12163 } 12164 } 12165 12166 if (rx_op_err_intr_flags & CPRI_INTR_RX_ENCAP_MISC_ERROR) { 12167 if(!(soc_reg_field_get(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, 12168 new_rval, RX_ENCAP_MISC_INTERRUPT_ENABLEf))) { 12169 soc_reg_field_set(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, &new_rval, 12170 RX_ENCAP_MISC_INTERRUPT_ENABLEf, enable); 12171 } 12172 } 12173 12174 if (rx_op_err_intr_flags & CPRI_INTR_RX_ENCAP_RSVD4_EVENTS) { 12175 if(!(soc_reg_field_get(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, 12176 new_rval, BRCM_RESERVED_CPM_301_3f))) { 12177 soc_reg_field_set(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, &new_rval, 12178 BRCM_RESERVED_CPM_301_3f, enable); 12179 } 12180 } 12181 12182 if (new_rval != rval) { 12183 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_OP_ERR_INTR_ENABLEr(unit, port, 12184 new_rval)); 12185 } 12186 12187 exit: 12188 SOC_FUNC_RETURN; 12189 } 12190 12191 /* 12192 * Enable CPRI port RX Operational error interrupts. 12193 * RX Lane Operational Error Interrupts. 12194 * 1. RX Lane Combined DATA Queue Overflow Error 12195 * 2. RX Lane Combined Control Queue Overflow Error 12196 * 3. RX Lane Combined GSM Time-stamp Error 12197 * 4. RX Lane MISC WQ and CDC Overflow Error 12198 * 5. RX RX Lane RxFramer BRCM_RSVD4 Time-stamp 12199 * detection Error 12200 */ 12201 int cprif_drv_cpri_port_rx_op_err_interrupts_enable_get(int unit, 12202 int port, 12203 int rx_op_err_intr_flags, 12204 int *status) 12205 { 12206 uint32 rval; 12207 soc_field_t field = INVALIDf; 12208 SOC_INIT_FUNC_DEFS; 12209 12210 _SOC_IF_ERR_EXIT(READ_CPRI_RX_OP_ERR_INTR_ENABLEr(unit, port, &rval)); 12211 12212 switch(rx_op_err_intr_flags) { 12213 case CPRI_INTR_RX_ENCAP_DATA_Q_OVRFLOW: 12214 field = RX_ENCAP_DATA_Q_OVFL_ERR_INTERRUPT_ENABLEf; 12215 break; 12216 case CPRI_INTR_RX_ENCAP_CTRL_Q_OVRFLOW: 12217 field = RX_ENCAP_CTRL_Q_OVFL_ERR_INTERRUPT_ENABLEf; 12218 break; 12219 case CPRI_INTR_RX_ENCAP_GSM_TIMESTAMP: 12220 field = BRCM_RESERVED_CPM_301_2f; 12221 break; 12222 case CPRI_INTR_RX_ENCAP_MISC_ERROR: 12223 field = RX_ENCAP_MISC_INTERRUPT_ENABLEf; 12224 break; 12225 case CPRI_INTR_RX_ENCAP_RSVD4_EVENTS: 12226 field = BRCM_RESERVED_CPM_301_3f; 12227 break; 12228 default: 12229 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 12230 ("Unknown Rx interrupt type")); 12231 break; 12232 } 12233 12234 if (field != INVALIDf) { 12235 *status = soc_reg_field_get(unit, CPRI_RX_OP_ERR_INTR_ENABLEr, rval, 12236 field); 12237 } 12238 12239 exit: 12240 SOC_FUNC_RETURN; 12241 } 12242 12243 /* 12244 * Enable CPRI port RX Functional interrupts. 12245 * RX Functional interrupts can be of 3 types 12246 * 1. RX 12247 * 2. RX functional error type interrupts. 12248 * 3. RX memory ECC error type interrupts. 12249 */ 12250 int cprif_drv_cpri_port_rx_func_interrupts_enable_set(int unit, 12251 int port, 12252 int rx_func_intr_flags, 12253 int enable) 12254 { 12255 uint32 rval, new_rval; 12256 SOC_INIT_FUNC_DEFS; 12257 12258 _SOC_IF_ERR_EXIT(READ_CPRI_RX_FUNC_INTR_ENABLEr(unit, port, &rval)); 12259 12260 new_rval = rval; 12261 if (rx_func_intr_flags & CPRI_INTR_RXFRM_CW_PARSER) { 12262 if(!(soc_reg_field_get(unit, CPRI_RX_FUNC_INTR_ENABLEr, 12263 new_rval, RX_RXFRM_CPRSR_INTERRUPT_ENABLEf))) { 12264 soc_reg_field_set(unit, CPRI_RX_FUNC_INTR_ENABLEr, &new_rval, 12265 RX_RXFRM_CPRSR_INTERRUPT_ENABLEf, enable); 12266 } 12267 } 12268 12269 if (rx_func_intr_flags & CPRI_INTR_RX_1588_SW) { 12270 if(!(soc_reg_field_get(unit, CPRI_RX_FUNC_INTR_ENABLEr, 12271 new_rval, RX_1588_SW_INTERRUPT_ENABLEf))) { 12272 soc_reg_field_set(unit, CPRI_RX_FUNC_INTR_ENABLEr, &new_rval, 12273 RX_1588_SW_INTERRUPT_ENABLEf, enable); 12274 } 12275 } 12276 12277 if (rx_func_intr_flags & CPRI_INTR_RX_1588_FIFO) { 12278 if(!(soc_reg_field_get(unit, CPRI_RX_FUNC_INTR_ENABLEr, 12279 new_rval, RX_1588_FIFO_INTERRUPT_ENABLEf))) { 12280 soc_reg_field_set(unit, CPRI_RX_FUNC_INTR_ENABLEr, &new_rval, 12281 RX_1588_FIFO_INTERRUPT_ENABLEf, enable); 12282 } 12283 } 12284 12285 if (rx_func_intr_flags & CPRI_INTR_RXFRM_GCW) { 12286 if(!(soc_reg_field_get(unit, CPRI_RX_FUNC_INTR_ENABLEr, 12287 new_rval, RX_RXFRM_GCW_INTERRUPT_ENABLEf))) { 12288 soc_reg_field_set(unit, CPRI_RX_FUNC_INTR_ENABLEr, &new_rval, 12289 RX_RXFRM_GCW_INTERRUPT_ENABLEf, enable); 12290 } 12291 } 12292 12293 if (rx_func_intr_flags & CPRI_INTR_RXPCS) { 12294 if(!(soc_reg_field_get(unit, CPRI_RX_FUNC_INTR_ENABLEr, 12295 new_rval, RX_RXPCS_INTERRUPT_ENABLEf))) { 12296 soc_reg_field_set(unit, CPRI_RX_FUNC_INTR_ENABLEr, &new_rval, 12297 RX_RXPCS_INTERRUPT_ENABLEf, enable); 12298 } 12299 } 12300 12301 if (rx_func_intr_flags & CPRI_INTR_RXPCS_FEC) { 12302 if(!(soc_reg_field_get(unit, CPRI_RX_FUNC_INTR_ENABLEr, 12303 new_rval, RX_RXPCS_FEC_INTERRUPT_ENABLEf))) { 12304 soc_reg_field_set(unit, CPRI_RX_FUNC_INTR_ENABLEr, &new_rval, 12305 RX_RXPCS_FEC_INTERRUPT_ENABLEf, enable); 12306 } 12307 } 12308 12309 if (new_rval != rval) { 12310 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_FUNC_INTR_ENABLEr(unit, port, new_rval)); 12311 } 12312 12313 exit: 12314 SOC_FUNC_RETURN; 12315 } 12316 12317 /* 12318 * Get CPRI port RX functional interrupts enable status. 12319 */ 12320 int cprif_drv_cpri_port_rx_func_interrupts_enable_get(int unit, 12321 int port, 12322 int rx_func_intr_flags, 12323 int *status) 12324 { 12325 uint32 rval; 12326 soc_field_t field = INVALIDf; 12327 SOC_INIT_FUNC_DEFS; 12328 12329 _SOC_IF_ERR_EXIT(READ_CPRI_RX_FUNC_INTR_ENABLEr(unit, port, &rval)); 12330 12331 switch(rx_func_intr_flags) { 12332 case CPRI_INTR_RXFRM_CW_PARSER: 12333 field = RX_RXFRM_CPRSR_INTERRUPT_ENABLEf; 12334 break; 12335 case CPRI_INTR_RX_1588_SW: 12336 field = RX_1588_SW_INTERRUPT_ENABLEf; 12337 break; 12338 case CPRI_INTR_RX_1588_FIFO: 12339 field = RX_1588_FIFO_INTERRUPT_ENABLEf; 12340 break; 12341 case CPRI_INTR_RXFRM_GCW: 12342 field = RX_RXFRM_GCW_INTERRUPT_ENABLEf; 12343 break; 12344 case CPRI_INTR_RXPCS: 12345 field = RX_RXPCS_INTERRUPT_ENABLEf; 12346 break; 12347 case CPRI_INTR_RXPCS_FEC: 12348 field = RX_RXPCS_FEC_INTERRUPT_ENABLEf; 12349 break; 12350 default: 12351 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 12352 ("Unknown Rx interrupt type")); 12353 break; 12354 } 12355 12356 if (field != INVALIDf) { 12357 *status = soc_reg_field_get(unit, CPRI_RX_FUNC_INTR_ENABLEr, 12358 rval, field); 12359 } 12360 12361 exit: 12362 SOC_FUNC_RETURN; 12363 } 12364 12365 /* 12366 * Enable CPRI port TX interrupts. 12367 * TX interrupts can be of 3 types 12368 * 1. TX operational error type interrupts. 12369 * 2. TX functional error type interrupts. 12370 * 3. TX memory ECC error type interrupts. 12371 */ 12372 int cprif_drv_cpri_port_tx_interrupts_enable_set(int unit, 12373 int port, 12374 int tx_intr_flags, 12375 int enable) 12376 { 12377 uint32 rval, new_rval; 12378 uint32 tx_op_err = 0; 12379 uint32 tx_func_err = 0; 12380 uint32 tx_ecc_err = 0; 12381 SOC_INIT_FUNC_DEFS; 12382 12383 _SOC_IF_ERR_EXIT(READ_CPRI_TX_INTR_ENABLEr(unit, port, &rval)); 12384 12385 new_rval = rval; 12386 if (tx_intr_flags & CPRIF_TX_OP_ERR_INTR) { 12387 tx_op_err = soc_reg_field_get(unit, CPRI_TX_INTR_ENABLEr, 12388 rval, TX_OP_ERR_INTERRUPT_ENABLEf); 12389 if (enable != tx_op_err) { 12390 soc_reg_field_set(unit, CPRI_TX_INTR_ENABLEr, &new_rval, 12391 TX_OP_ERR_INTERRUPT_ENABLEf, enable); 12392 } 12393 } 12394 12395 if (tx_intr_flags & CPRIF_TX_FUNC_ERR_INTR) { 12396 tx_func_err = soc_reg_field_get(unit, CPRI_TX_INTR_ENABLEr, 12397 rval, TX_FUNC_INTERRUPT_ENABLEf); 12398 if (enable != tx_func_err) { 12399 soc_reg_field_set(unit, CPRI_TX_INTR_ENABLEr, &new_rval, 12400 TX_FUNC_INTERRUPT_ENABLEf, enable); 12401 } 12402 } 12403 12404 if (tx_intr_flags & CPRIF_TX_ECC_ERR_INTR) { 12405 tx_ecc_err = soc_reg_field_get(unit, CPRI_TX_INTR_ENABLEr, 12406 rval, TX_ECC_INTERRUPT_ENABLEf); 12407 if (enable != tx_ecc_err) { 12408 soc_reg_field_set(unit, CPRI_TX_INTR_ENABLEr, &new_rval, 12409 TX_ECC_INTERRUPT_ENABLEf, enable); 12410 } 12411 } 12412 12413 if (new_rval != rval) { 12414 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_INTR_ENABLEr(unit, port, new_rval)); 12415 } 12416 12417 exit: 12418 SOC_FUNC_RETURN; 12419 } 12420 12421 /* 12422 * Get CPRI port TX interrupts enable status. 12423 */ 12424 int cprif_drv_cpri_port_tx_interrupt_enable_get(int unit, 12425 int port, 12426 int tx_intr_flags, 12427 int *status) 12428 { 12429 uint32 rval; 12430 soc_field_t field = INVALIDf; 12431 SOC_INIT_FUNC_DEFS; 12432 12433 _SOC_IF_ERR_EXIT(READ_CPRI_TX_INTR_ENABLEr(unit, port, &rval)); 12434 12435 switch (tx_intr_flags) { 12436 case CPRIF_TX_OP_ERR_INTR: 12437 field = TX_OP_ERR_INTERRUPT_ENABLEf; 12438 break; 12439 case CPRIF_TX_FUNC_ERR_INTR: 12440 field = TX_FUNC_INTERRUPT_ENABLEf; 12441 break; 12442 case CPRIF_TX_ECC_ERR_INTR: 12443 field = TX_ECC_INTERRUPT_ENABLEf; 12444 break; 12445 default: 12446 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 12447 ("Unknown Rx interrupt type")); 12448 break; 12449 } 12450 12451 if (field != INVALIDf) { 12452 *status = soc_reg_field_get(unit, CPRI_TX_INTR_ENABLEr, rval, field); 12453 } 12454 12455 exit: 12456 SOC_FUNC_RETURN; 12457 } 12458 12459 /* 12460 * Enable CPRI port TX Functional interrupts. 12461 * TX Functional interrupts can be of 3 types 12462 * 1. TX 12463 * 2. TX functional error type interrupts. 12464 * 3. TX memory ECC error type interrupts. 12465 */ 12466 int cprif_drv_cpri_port_tx_op_err_interrupts_enable_set(int unit, 12467 int port, 12468 int tx_op_err_intr_flags, 12469 int enable) 12470 { 12471 uint32 rval, new_rval; 12472 SOC_INIT_FUNC_DEFS; 12473 12474 _SOC_IF_ERR_EXIT(READ_CPRI_TX_OP_ERR_INTR_ENABLEr(unit, port, &rval)); 12475 12476 new_rval = rval; 12477 12478 if (tx_op_err_intr_flags & CPRI_INTR_TX_DECAP_DATA_Q_OVRFLOW) { 12479 if(!(soc_reg_field_get(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, 12480 new_rval, TX_DECAP_DATA_Q_OVFL_ERR_INTERRUPT_ENABLEf))) { 12481 soc_reg_field_set(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, &new_rval, 12482 TX_DECAP_DATA_Q_OVFL_ERR_INTERRUPT_ENABLEf, enable); 12483 } 12484 } 12485 12486 if (tx_op_err_intr_flags & CPRI_INTR_TX_DECAP_DATA_Q_UNDRFLOW) { 12487 if(!(soc_reg_field_get(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, 12488 new_rval, TX_DECAP_DATA_Q_UDFL_ERR_INTERRUPT_ENABLEf))) { 12489 soc_reg_field_set(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, &new_rval, 12490 TX_DECAP_DATA_Q_UDFL_ERR_INTERRUPT_ENABLEf, enable); 12491 } 12492 } 12493 12494 if (tx_op_err_intr_flags & CPRI_INTR_TX_DECAP_DATA_Q_BUFFSIZE_ERR) { 12495 if(!(soc_reg_field_get(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, 12496 new_rval, TX_DECAP_DATA_Q_BUFFSIZE_ERR_INTERRUPT_ENABLEf))) { 12497 soc_reg_field_set(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, &new_rval, 12498 TX_DECAP_DATA_Q_BUFFSIZE_ERR_INTERRUPT_ENABLEf, enable); 12499 } 12500 } 12501 12502 if (tx_op_err_intr_flags & CPRI_INTR_TX_DECAP_AG_MODE_INTR) { 12503 if(!(soc_reg_field_get(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, 12504 new_rval, TX_DECAP_AG_MODE_INTERRUPT_ENABLEf))) { 12505 soc_reg_field_set(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, &new_rval, 12506 TX_DECAP_AG_MODE_INTERRUPT_ENABLEf, enable); 12507 } 12508 } 12509 12510 if (tx_op_err_intr_flags & CPRI_INTR_TX_TXPCS_MISC_INTR) { 12511 if(!(soc_reg_field_get(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, 12512 new_rval, TX_TXPCS_MISC_INTERRUPT_ENABLEf))) { 12513 soc_reg_field_set(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, &new_rval, 12514 TX_TXPCS_MISC_INTERRUPT_ENABLEf, enable); 12515 } 12516 } 12517 12518 if (new_rval != rval) { 12519 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_OP_ERR_INTR_ENABLEr(unit, port, new_rval)); 12520 } 12521 12522 exit: 12523 SOC_FUNC_RETURN; 12524 } 12525 12526 /* 12527 * Get CPRI port TX functional interrupts enable status. 12528 */ 12529 int cprif_drv_cpri_port_tx_op_err_interrupts_enable_get(int unit, 12530 int port, 12531 int tx_op_err_intr_flags, 12532 int *status) 12533 { 12534 uint32 rval; 12535 soc_field_t field = INVALIDf; 12536 SOC_INIT_FUNC_DEFS; 12537 12538 _SOC_IF_ERR_EXIT(READ_CPRI_TX_OP_ERR_INTR_ENABLEr(unit, port, &rval)); 12539 12540 12541 switch (tx_op_err_intr_flags) { 12542 case CPRI_INTR_TX_DECAP_DATA_Q_OVRFLOW: 12543 field = TX_DECAP_DATA_Q_OVFL_ERR_INTERRUPT_ENABLEf; 12544 break; 12545 case CPRI_INTR_TX_DECAP_DATA_Q_UNDRFLOW: 12546 field = TX_DECAP_DATA_Q_UDFL_ERR_INTERRUPT_ENABLEf; 12547 break; 12548 case CPRI_INTR_TX_DECAP_DATA_Q_BUFFSIZE_ERR: 12549 field = TX_DECAP_DATA_Q_BUFFSIZE_ERR_INTERRUPT_ENABLEf; 12550 break; 12551 case CPRI_INTR_TX_DECAP_AG_MODE_INTR: 12552 field = TX_DECAP_AG_MODE_INTERRUPT_ENABLEf; 12553 break; 12554 case CPRI_INTR_TX_TXPCS_MISC_INTR: 12555 field = TX_TXPCS_MISC_INTERRUPT_ENABLEf; 12556 break; 12557 default: 12558 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 12559 ("Unknown Rx interrupt type")); 12560 break; 12561 } 12562 12563 if (field != INVALIDf) { 12564 *status = soc_reg_field_get(unit, CPRI_TX_OP_ERR_INTR_ENABLEr, rval, 12565 field); 12566 } 12567 12568 exit: 12569 SOC_FUNC_RETURN; 12570 } 12571 12572 12573 /* 12574 * Enable CPRI port TX Functional interrupts. 12575 * TX Functional interrupts can be of 3 types 12576 * 1. TX 12577 * 2. TX functional error type interrupts. 12578 * 3. TX memory ECC error type interrupts. 12579 */ 12580 int cprif_drv_cpri_port_tx_func_interrupts_enable_set(int unit, 12581 int port, 12582 int tx_func_intr_flags, 12583 int enable) 12584 { 12585 uint32 rval, new_rval; 12586 SOC_INIT_FUNC_DEFS; 12587 12588 _SOC_IF_ERR_EXIT(READ_CPRI_TX_FUNC_INTR_ENABLEr(unit, port, &rval)); 12589 12590 new_rval = rval; 12591 12592 if (tx_func_intr_flags & CPRI_INTR_TX_1588_SW) { 12593 if(!(soc_reg_field_get(unit, CPRI_TX_FUNC_INTR_ENABLEr, 12594 new_rval, TX_1588_SW_INTERRUPT_ENABLEf))) { 12595 soc_reg_field_set(unit, CPRI_TX_FUNC_INTR_ENABLEr, &new_rval, 12596 TX_1588_SW_INTERRUPT_ENABLEf, enable); 12597 } 12598 } 12599 12600 if (tx_func_intr_flags & CPRI_INTR_TX_1588_FIFO) { 12601 if(!(soc_reg_field_get(unit, CPRI_TX_FUNC_INTR_ENABLEr, 12602 new_rval, TX_1588_FIFO_INTERRUPT_ENABLEf))) { 12603 soc_reg_field_set(unit, CPRI_TX_FUNC_INTR_ENABLEr, &new_rval, 12604 TX_1588_FIFO_INTERRUPT_ENABLEf, enable); 12605 } 12606 } 12607 12608 if (tx_func_intr_flags & CPRI_INTR_TX_GCW) { 12609 if(!(soc_reg_field_get(unit, CPRI_TX_FUNC_INTR_ENABLEr, 12610 new_rval, TX_GCW_INTERRUPT_ENABLEf))) { 12611 soc_reg_field_set(unit, CPRI_TX_FUNC_INTR_ENABLEr, &new_rval, 12612 TX_GCW_INTERRUPT_ENABLEf, enable); 12613 } 12614 } 12615 12616 if (new_rval != rval) { 12617 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_FUNC_INTR_ENABLEr(unit, port, new_rval)); 12618 } 12619 12620 exit: 12621 SOC_FUNC_RETURN; 12622 } 12623 12624 /* 12625 * Get CPRI port TX functional interrupts enable status. 12626 */ 12627 int cprif_drv_cpri_port_tx_func_interrupts_enable_get(int unit, 12628 int port, 12629 int tx_func_intr_flags, 12630 int *status) 12631 { 12632 uint32 rval; 12633 soc_field_t field = INVALIDf; 12634 SOC_INIT_FUNC_DEFS; 12635 12636 _SOC_IF_ERR_EXIT(READ_CPRI_TX_FUNC_INTR_ENABLEr(unit, port, &rval)); 12637 12638 switch (tx_func_intr_flags) { 12639 case CPRI_INTR_TX_1588_SW: 12640 field = TX_1588_SW_INTERRUPT_ENABLEf; 12641 break; 12642 case CPRI_INTR_TX_1588_FIFO: 12643 field = TX_1588_FIFO_INTERRUPT_ENABLEf; 12644 break; 12645 case CPRI_INTR_TX_GCW: 12646 field = TX_GCW_INTERRUPT_ENABLEf; 12647 break; 12648 default: 12649 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 12650 ("Unknown Rx interrupt type")); 12651 break; 12652 } 12653 12654 if (field != INVALIDf) { 12655 *status = soc_reg_field_get(unit, CPRI_TX_FUNC_INTR_ENABLEr, rval, field); 12656 } 12657 12658 exit: 12659 SOC_FUNC_RETURN; 12660 } 12661 12662 /* Enable interrupt to detect link UP - Link Status Latched High. */ 12663 int cprif_drv_rx_pcs_link_up_intr_enable_set(int unit, 12664 int port, 12665 int enable) 12666 { 12667 uint32 rval; 12668 uint32 rxpcs_los_lh = 0; 12669 SOC_INIT_FUNC_DEFS; 12670 12671 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_ENABLEr(unit, port, &rval)); 12672 rxpcs_los_lh = soc_reg_field_get(unit, CPRI_RXPCS_INTR_ENABLEr, 12673 rval, RXPCS_LINK_STATUS_LH_INTERRUPT_ENf); 12674 12675 /* do nothing if the requested operation is already set */ 12676 if (!(enable && rxpcs_los_lh)) { 12677 soc_reg_field_set(unit, CPRI_RXPCS_INTR_ENABLEr, &rval, 12678 RXPCS_LINK_STATUS_LH_INTERRUPT_ENf, enable); 12679 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_INTR_ENABLEr(unit, port, rval)); 12680 } 12681 12682 exit: 12683 SOC_FUNC_RETURN; 12684 } 12685 12686 /* Get interrupt enable Status to detect link UP event */ 12687 int cprif_drv_rx_pcs_link_up_intr_enable_get(int unit, 12688 int port, 12689 int *status) 12690 { 12691 uint32 rval; 12692 SOC_INIT_FUNC_DEFS; 12693 12694 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_ENABLEr(unit, port, &rval)); 12695 *status = soc_reg_field_get(unit, CPRI_RXPCS_INTR_ENABLEr, 12696 rval, RXPCS_LINK_STATUS_LH_INTERRUPT_ENf); 12697 12698 exit: 12699 SOC_FUNC_RETURN; 12700 } 12701 12702 /* 12703 * Get link interrupt Status by checking Link Status Latched High. 12704 * The link is UP is the LOS LL is set. 12705 */ 12706 int cprif_drv_rx_pcs_link_up_intr_status_get(int unit, 12707 int port, 12708 int *status) 12709 { 12710 uint32 rval; 12711 SOC_INIT_FUNC_DEFS; 12712 12713 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_STATUSr(unit, port, &rval)); 12714 *status = soc_reg_field_get(unit, CPRI_RXPCS_INTR_STATUSr, 12715 rval, RXPCS_LINK_STATUS_LH_INTERRUPT_STATUSf); 12716 12717 exit: 12718 SOC_FUNC_RETURN; 12719 } 12720 12721 /* 12722 * This function checks if the link is UP by checking the 12723 * RXPCS Link Staus status. If the Link Stauts LH(latched high) 12724 * status is set, meaning the link is UP, the Link Status LH STATUS 12725 * is cleared by writing 1 to the field. 12726 * 12727 * Note: Currently called from the link event interrupt 12728 * handler, to check a link status change. 12729 */ 12730 int cprif_drv_rx_pcs_link_up_intr_status_clr_get(int unit, 12731 int port, 12732 int *status) 12733 { 12734 uint32 rval; 12735 int is_enabled = 0; 12736 SOC_INIT_FUNC_DEFS; 12737 12738 /* 12739 * Check if the Link up event interrupt is enabled 12740 * if not, ignore and return. 12741 */ 12742 _SOC_IF_ERR_EXIT(cprif_drv_rx_pcs_link_up_intr_enable_get(unit, port, 12743 &is_enabled)); 12744 12745 if(!is_enabled) { 12746 return SOC_E_NONE; 12747 } 12748 12749 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_STATUSr(unit, port, &rval)); 12750 *status = soc_reg_field_get(unit, CPRI_RXPCS_INTR_STATUSr, 12751 rval, RXPCS_LINK_STATUS_LH_INTERRUPT_STATUSf); 12752 12753 if (*status) { 12754 LOG_CLI(("Port(%s)-%d UP!! Clearing interrupt \n", 12755 SOC_PORT_NAME(unit, port), port)); 12756 /* 12757 * Only Clear the bit that are processing. 12758 */ 12759 rval = 0; 12760 soc_reg_field_set(unit, CPRI_RXPCS_INTR_STATUSr, &rval, 12761 RXPCS_LINK_STATUS_LH_INTERRUPT_STATUSf, 1); 12762 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_INTR_STATUSr(unit, port, rval)); 12763 } 12764 12765 exit: 12766 SOC_FUNC_RETURN; 12767 } 12768 12769 /* Enable interrupt to detect link DOWN - Link Status signal is latched low */ 12770 int cprif_drv_rx_pcs_link_down_intr_enable_set(int unit, 12771 int port, 12772 int enable) 12773 { 12774 uint32 rval; 12775 uint32 rxpcs_los_ll = 0; 12776 SOC_INIT_FUNC_DEFS; 12777 12778 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_ENABLEr(unit, port, &rval)); 12779 rxpcs_los_ll = soc_reg_field_get(unit, CPRI_RXPCS_INTR_ENABLEr, 12780 rval, RXPCS_LINK_STATUS_LL_INTERRUPT_ENf); 12781 12782 /* do nothing if the requested operation is already set */ 12783 if (!(enable && rxpcs_los_ll)) { 12784 soc_reg_field_set(unit, CPRI_RXPCS_INTR_ENABLEr, &rval, 12785 RXPCS_LINK_STATUS_LL_INTERRUPT_ENf, enable); 12786 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_INTR_ENABLEr(unit, port, rval)); 12787 } 12788 12789 exit: 12790 SOC_FUNC_RETURN; 12791 } 12792 12793 /* Get interrupt enable status to detect link DOWN - Link Status signal(latched low) */ 12794 int cprif_drv_rx_pcs_link_down_intr_enable_get(int unit, 12795 int port, 12796 int *status) 12797 { 12798 uint32 rval; 12799 SOC_INIT_FUNC_DEFS; 12800 12801 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_ENABLEr(unit, port, &rval)); 12802 *status = soc_reg_field_get(unit, CPRI_RXPCS_INTR_ENABLEr, 12803 rval, RXPCS_LINK_STATUS_LL_INTERRUPT_ENf); 12804 12805 exit: 12806 SOC_FUNC_RETURN; 12807 } 12808 12809 /* 12810 * Get link interrupt Status by checking Link Status signal - latched low. 12811 * The link is DOWN is the LOS LH is set. 12812 */ 12813 int cprif_drv_rx_pcs_link_down_intr_status_get(int unit, 12814 int port, 12815 int *status) 12816 { 12817 uint32 rval; 12818 int is_enabled; 12819 SOC_INIT_FUNC_DEFS; 12820 12821 /* 12822 * Check if the Link down event interrupt is enabled 12823 * if not, ignore the status and return. 12824 */ 12825 _SOC_IF_ERR_EXIT(cprif_drv_rx_pcs_link_down_intr_enable_get(unit, port, 12826 &is_enabled)); 12827 if (is_enabled) { 12828 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_STATUSr(unit, port, &rval)); 12829 *status = soc_reg_field_get(unit, CPRI_RXPCS_INTR_STATUSr, 12830 rval, RXPCS_LINK_STATUS_LL_INTERRUPT_STATUSf); 12831 } 12832 12833 exit: 12834 SOC_FUNC_RETURN; 12835 } 12836 12837 /* 12838 * This function checks if the link is DOWN by checking the 12839 * RXPCS LINK_STATUS LL signal status. If the LINK_STATUS LL(latched low) 12840 * status is set, meaning the link is DOWN, the Link Status LL STATUS 12841 * is cleared by writing 1 to the field. 12842 * 12843 * Note: Currently called from the link event interrupt 12844 * handler, to check a link status change. 12845 */ 12846 int cprif_drv_rx_pcs_link_down_intr_status_clr_get(int unit, 12847 int port, 12848 int *status) 12849 { 12850 uint32 rval; 12851 int is_enabled = 0; 12852 SOC_INIT_FUNC_DEFS; 12853 12854 /* 12855 * Check if the Link down event interrupt is enabled 12856 * if not, return. 12857 */ 12858 _SOC_IF_ERR_EXIT(cprif_drv_rx_pcs_link_down_intr_enable_get(unit, port, 12859 &is_enabled)); 12860 if (!is_enabled) { 12861 return SOC_E_NONE; 12862 } 12863 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_INTR_STATUSr(unit, port, &rval)); 12864 *status = soc_reg_field_get(unit, CPRI_RXPCS_INTR_STATUSr, 12865 rval, RXPCS_LINK_STATUS_LL_INTERRUPT_STATUSf); 12866 12867 if (*status) { 12868 LOG_CLI(("Port(%s)-%d DOWN!! Clearing interrupt\n", 12869 SOC_PORT_NAME(unit, port), port)); 12870 /* 12871 * Only Clear the bit that are processing. 12872 */ 12873 rval = 0; 12874 soc_reg_field_set(unit, CPRI_RXPCS_INTR_STATUSr, &rval, 12875 RXPCS_LINK_STATUS_LL_INTERRUPT_STATUSf, 1); 12876 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_INTR_STATUSr(unit, port, rval)); 12877 } 12878 12879 exit: 12880 SOC_FUNC_RETURN; 12881 } 12882 12883 int cprif_drv_rx_1588_fifo_intr_enable_set(int unit, int port, int enable) 12884 { 12885 uint32 rval; 12886 int curr_val = 0; 12887 SOC_INIT_FUNC_DEFS; 12888 12889 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROLr(unit, port, 12890 &rval)); 12891 curr_val = soc_reg_field_get(unit, CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROLr, 12892 rval, RX_TS_FIFO_INTERRUPT_ENf); 12893 12894 if (curr_val != enable) { 12895 soc_reg_field_set(unit, CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROLr, &rval, 12896 RX_TS_FIFO_INTERRUPT_ENf, enable); 12897 } 12898 12899 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROLr(unit, port, 12900 rval)); 12901 12902 exit: 12903 SOC_FUNC_RETURN; 12904 } 12905 12906 int cprif_drv_rx_1588_fifo_intr_enable_get(int unit, int port, int *status) 12907 { 12908 uint32 rval; 12909 SOC_INIT_FUNC_DEFS; 12910 12911 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROLr(unit, port, 12912 &rval)); 12913 *status = soc_reg_field_get(unit, CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROLr, 12914 rval, RX_TS_FIFO_INTERRUPT_ENf); 12915 12916 exit: 12917 SOC_FUNC_RETURN; 12918 } 12919 12920 int cprif_drv_tx_1588_fifo_intr_enable_set(int unit, int port, int enable) 12921 { 12922 uint32 rval; 12923 int curr_val = 0; 12924 SOC_INIT_FUNC_DEFS; 12925 12926 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROLr(unit, port, 12927 &rval)); 12928 curr_val = soc_reg_field_get(unit, CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROLr, 12929 rval, TX_TS_FIFO_INTERRUPT_ENf); 12930 12931 if (curr_val != enable) { 12932 soc_reg_field_set(unit, CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROLr, &rval, 12933 TX_TS_FIFO_INTERRUPT_ENf, enable); 12934 } 12935 12936 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROLr(unit, port, 12937 rval)); 12938 12939 exit: 12940 SOC_FUNC_RETURN; 12941 } 12942 12943 int cprif_drv_tx_1588_fifo_intr_enable_get(int unit, int port, int *status) 12944 { 12945 uint32 rval; 12946 SOC_INIT_FUNC_DEFS; 12947 12948 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROLr(unit, port, 12949 &rval)); 12950 *status = soc_reg_field_get(unit, CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROLr, 12951 rval, TX_TS_FIFO_INTERRUPT_ENf); 12952 12953 exit: 12954 SOC_FUNC_RETURN; 12955 } 12956 12957 int cprif_drv_rx_1588_sw_intr_enable_set(int unit, int port, int enable) 12958 { 12959 uint32 rval; 12960 int curr_val = 0; 12961 SOC_INIT_FUNC_DEFS; 12962 12963 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CAP_INTR_ENABLE_CONTROLr(unit, port, 12964 &rval)); 12965 curr_val = soc_reg_field_get(unit, CPRI_RX_1588_CAP_INTR_ENABLE_CONTROLr, 12966 rval, RX_CAPTURED_TS_INTERRUPT_ENf); 12967 12968 if (curr_val != enable) { 12969 soc_reg_field_set(unit, CPRI_RX_1588_CAP_INTR_ENABLE_CONTROLr, &rval, 12970 RX_CAPTURED_TS_INTERRUPT_ENf, enable); 12971 } 12972 12973 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_1588_CAP_INTR_ENABLE_CONTROLr(unit, port, 12974 rval)); 12975 12976 exit: 12977 SOC_FUNC_RETURN; 12978 } 12979 12980 int cprif_drv_rx_1588_sw_intr_enable_get(int unit, int port, int *status) 12981 { 12982 uint32 rval; 12983 SOC_INIT_FUNC_DEFS; 12984 12985 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CAP_INTR_ENABLE_CONTROLr(unit, port, 12986 &rval)); 12987 *status = soc_reg_field_get(unit, CPRI_RX_1588_CAP_INTR_ENABLE_CONTROLr, 12988 rval, RX_CAPTURED_TS_INTERRUPT_ENf); 12989 12990 exit: 12991 SOC_FUNC_RETURN; 12992 } 12993 12994 int cprif_drv_tx_1588_sw_intr_enable_set(int unit, int port, int enable) 12995 { 12996 uint32 rval; 12997 int curr_val = 0; 12998 SOC_INIT_FUNC_DEFS; 12999 13000 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CAP_INTR_ENABLE_CONTROLr(unit, port, 13001 &rval)); 13002 curr_val = soc_reg_field_get(unit, CPRI_TX_1588_CAP_INTR_ENABLE_CONTROLr, 13003 rval, TX_CAPTURED_TS_INTERRUPT_ENf); 13004 13005 if (curr_val != enable) { 13006 soc_reg_field_set(unit, CPRI_TX_1588_CAP_INTR_ENABLE_CONTROLr, &rval, 13007 TX_CAPTURED_TS_INTERRUPT_ENf, enable); 13008 } 13009 13010 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_CAP_INTR_ENABLE_CONTROLr(unit, port, 13011 rval)); 13012 13013 exit: 13014 SOC_FUNC_RETURN; 13015 } 13016 13017 int cprif_drv_tx_1588_sw_intr_enable_get(int unit, int port, int *status) 13018 { 13019 uint32 rval; 13020 SOC_INIT_FUNC_DEFS; 13021 13022 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CAP_INTR_ENABLE_CONTROLr(unit, port, 13023 &rval)); 13024 *status = soc_reg_field_get(unit, CPRI_TX_1588_CAP_INTR_ENABLE_CONTROLr, 13025 rval, TX_CAPTURED_TS_INTERRUPT_ENf); 13026 13027 exit: 13028 SOC_FUNC_RETURN; 13029 } 13030 13031 int cprif_drv_fast_clk_bit_time_period_set(int unit, int port, uint32 bit_time_period) 13032 { 13033 uint32 fast_clk_tp; 13034 SOC_INIT_FUNC_DEFS; 13035 13036 _SOC_IF_ERR_EXIT(READ_CPRI_FAST_CLK_CTRLr(unit, port, &fast_clk_tp)); 13037 soc_reg_field_set(unit, CPRI_FAST_CLK_CTRLr, &fast_clk_tp, FAST_CLK_PERIODf, bit_time_period); 13038 _SOC_IF_ERR_EXIT(WRITE_CPRI_FAST_CLK_CTRLr(unit, port, fast_clk_tp)); 13039 13040 exit: 13041 SOC_FUNC_RETURN; 13042 } 13043 13044 13045 int cprif_drv_fast_clk_bit_time_period_get(int unit, int port, uint32* fast_clk) 13046 { 13047 uint32 fast_clk_tp; 13048 SOC_INIT_FUNC_DEFS; 13049 _SOC_IF_ERR_EXIT(READ_CPRI_FAST_CLK_CTRLr(unit, port, &fast_clk_tp)); 13050 *fast_clk = soc_reg_field_get(unit, CPRI_FAST_CLK_CTRLr, fast_clk_tp, FAST_CLK_PERIODf); 13051 13052 exit: 13053 SOC_FUNC_RETURN; 13054 } 13055 13056 int cprif_drv_1588_bit_time_period_set(int unit, int port, cprimod_direction_t direction, cprimod_port_speed_t speed) 13057 { 13058 uint32 bit_period32; 13059 uint64 bit_period64; 13060 uint64 bit_period; 13061 SOC_INIT_FUNC_DEFS; 13062 13063 bit_period32 = 0x682b; 13064 switch(speed) { 13065 case cprimodSpd614p4 : 13066 bit_period32 = 0x682ab; /* ROUND((1000*1024*32*8)/614.4 ,0) */ 13067 break; 13068 case cprimodSpd1228p8 : 13069 bit_period32 = 0x34155; /* ROUND((1000*1024*32*8)/1228.8 ,0) */ 13070 break; 13071 case cprimodSpd2457p6 : 13072 bit_period32 = 0x1a0ab; /* ROUND((1000*1024*32*8)/2457.6 ,0) */ 13073 break; 13074 case cprimodSpd3072p0 : 13075 bit_period32 = 0x14d55; /* ROUND((1000*1024*32*8)/3072 ,0) */ 13076 break; 13077 case cprimodSpd4915p2 : 13078 bit_period32 = 0xd055 ; /* ROUND((1000*1024*32*8)/4915.2 ,0) */ 13079 break; 13080 case cprimodSpd6144p0 : 13081 bit_period32 = 0xa6aa ; /* ROUND((1000*1024*32*8)/6144 ,0) */ 13082 break; 13083 case cprimodSpd8110p08 : 13084 bit_period32 = 0x7e43 ; /* ROUND((1000*1024*32*8)/8110.08 ,0) */ 13085 break; 13086 case cprimodSpd9830p4 : 13087 bit_period32 = 0x682b ; /* ROUND((1000*1024*32*8)/9830.4 ,0) */ 13088 break; 13089 case cprimodSpd10137p6 : 13090 bit_period32 = 0x6503 ; /* ROUND((1000*1024*32*8)/10137.6 ,0) */ 13091 break; 13092 case cprimodSpd12165p12: 13093 bit_period32 = 0x542d ; /* ROUND((1000*1024*32*8)/12165.12,0) */ 13094 break; 13095 case cprimodSpd24330p24: 13096 bit_period32 = 0x2a16 ; /* ROUND((1000*1024*32*8)/24330.24,0) */ 13097 break; 13098 case cprimodSpdCount : 13099 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Bad speed")); 13100 break; 13101 } 13102 COMPILER_64_SET(bit_period64, 0, bit_period32); 13103 if(direction == CPRIMOD_DIR_TX) { 13104 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CTRLr(unit, port, &bit_period)); 13105 soc_reg64_field_set(unit, CPRI_TX_1588_CTRLr, &bit_period, TX_BIT_TIME_PERIODf, bit_period64); 13106 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_CTRLr(unit, port, bit_period)); 13107 } else { 13108 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CTRLr(unit, port, &bit_period)); 13109 soc_reg64_field_set(unit, CPRI_RX_1588_CTRLr, &bit_period, RX_BIT_TIME_PERIODf, bit_period64); 13110 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_1588_CTRLr(unit, port, bit_period)); 13111 } 13112 13113 exit: 13114 SOC_FUNC_RETURN; 13115 13116 } 13117 13118 int cprif_drv_1588_bit_time_period_get(int unit, int port, cprimod_direction_t direction, uint32* bit_time_period) 13119 { 13120 uint64 bit_period; 13121 uint64 bit_period64; 13122 SOC_INIT_FUNC_DEFS; 13123 if(direction == CPRIMOD_DIR_TX) { 13124 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CTRLr(unit, port, &bit_period)); 13125 bit_period64 = soc_reg64_field_get(unit, CPRI_TX_1588_CTRLr, bit_period, TX_BIT_TIME_PERIODf); 13126 } else { 13127 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CTRLr(unit, port, &bit_period)); 13128 bit_period64 = soc_reg64_field_get(unit, CPRI_RX_1588_CTRLr, bit_period, RX_BIT_TIME_PERIODf); 13129 } 13130 *bit_time_period = COMPILER_64_LO(bit_period64); 13131 13132 exit: 13133 SOC_FUNC_RETURN; 13134 } 13135 13136 13137 int cprif_drv_1588_timestamp_capture_config_set(int unit, int port, cprimod_direction_t direction, cprimod_1588_capture_config_t *config) 13138 { 13139 uint64 ctrl; 13140 uint64 cap_bfn; 13141 uint64 cap_hfn; 13142 uint64 hfn_only; 13143 uint64 val64; 13144 SOC_INIT_FUNC_DEFS; 13145 13146 COMPILER_64_SET(cap_bfn, 0, config->capture_bfn_num); 13147 COMPILER_64_SET(cap_hfn, 0, config->capture_hfn_num); 13148 if(config->mode == cprimod_1588_MATCH_HFN_ONLY) { 13149 COMPILER_64_SET(hfn_only, 0, 1); 13150 } else { 13151 COMPILER_64_SET(hfn_only, 0, 0); 13152 } 13153 COMPILER_64_SET(val64, 0, 1); 13154 if(direction == CPRIMOD_DIR_TX) { 13155 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CTRLr(unit, port, &ctrl)); 13156 soc_reg64_field_set(unit, CPRI_TX_1588_CTRLr, &ctrl, TX_TS_CAPTURE_EVERY_BFNf, hfn_only); 13157 soc_reg64_field_set(unit, CPRI_TX_1588_CTRLr, &ctrl, TX_TS_CAPTURE_BFNf, cap_bfn); 13158 soc_reg64_field_set(unit, CPRI_TX_1588_CTRLr, &ctrl, TX_TS_CAPTURE_HFNf, cap_hfn); 13159 soc_reg64_field_set(unit, CPRI_TX_1588_CTRLr, &ctrl, 13160 TX_TS_CAPTURE_REQf, val64); 13161 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_CTRLr(unit, port, ctrl)); 13162 } else { 13163 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CTRLr(unit, port, &ctrl)); 13164 soc_reg64_field_set(unit, CPRI_RX_1588_CTRLr, &ctrl, RX_TS_CAPTURE_EVERY_BFNf, hfn_only); 13165 soc_reg64_field_set(unit, CPRI_RX_1588_CTRLr, &ctrl, RX_TS_CAPTURE_BFNf, cap_bfn); 13166 soc_reg64_field_set(unit, CPRI_RX_1588_CTRLr, &ctrl, RX_TS_CAPTURE_HFNf, cap_hfn); 13167 soc_reg64_field_set(unit, CPRI_RX_1588_CTRLr, &ctrl, 13168 RX_TS_CAPTURE_REQf, val64); 13169 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_1588_CTRLr(unit, port, ctrl)); 13170 } 13171 13172 exit: 13173 SOC_FUNC_RETURN; 13174 13175 } 13176 int cprif_drv_1588_timestamp_capture_config_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_capture_config_t* config) 13177 { 13178 uint64 ctrl; 13179 uint64 cap_bfn; 13180 uint64 cap_hfn; 13181 uint64 hfn_only; 13182 uint8 hfn_only8; 13183 SOC_INIT_FUNC_DEFS; 13184 13185 if(direction == CPRIMOD_DIR_TX) { 13186 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CTRLr(unit, port, &ctrl)); 13187 hfn_only = soc_reg64_field_get(unit, CPRI_TX_1588_CTRLr, ctrl, TX_TS_CAPTURE_EVERY_BFNf); 13188 cap_bfn = soc_reg64_field_get(unit, CPRI_TX_1588_CTRLr, ctrl, TX_TS_CAPTURE_BFNf); 13189 cap_hfn = soc_reg64_field_get(unit, CPRI_TX_1588_CTRLr, ctrl, TX_TS_CAPTURE_HFNf); 13190 } else { 13191 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CTRLr(unit, port, &ctrl)); 13192 hfn_only = soc_reg64_field_get(unit, CPRI_RX_1588_CTRLr, ctrl, RX_TS_CAPTURE_EVERY_BFNf); 13193 cap_bfn = soc_reg64_field_get(unit, CPRI_RX_1588_CTRLr, ctrl, RX_TS_CAPTURE_BFNf); 13194 cap_hfn = soc_reg64_field_get(unit, CPRI_RX_1588_CTRLr, ctrl, RX_TS_CAPTURE_HFNf); 13195 } 13196 config->capture_bfn_num = COMPILER_64_LO(cap_bfn) & 0xFFFF; 13197 config->capture_hfn_num = COMPILER_64_LO(cap_hfn) & 0xFFFF; 13198 hfn_only8 = COMPILER_64_LO(hfn_only) & 0xff; 13199 if(hfn_only8) { 13200 config->mode = cprimod_1588_MATCH_HFN_ONLY; 13201 } else { 13202 config->mode = cprimod_1588_MATCH_BFN_AND_HFN; 13203 } 13204 13205 exit: 13206 SOC_FUNC_RETURN; 13207 } 13208 13209 13210 int cprif_drv_1588_captured_timestamp_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_ts_type_t ts_type, uint8 mx_cnt, uint8* count, uint64* captured_time) 13211 { 13212 int i; 13213 uint64 ctrl; 13214 uint64 ts; 13215 uint64 val_zero; 13216 uint64 ts_stat; 13217 uint32 ts_stat32; 13218 SOC_INIT_FUNC_DEFS; 13219 if (mx_cnt==0) { 13220 *count = 0; 13221 SOC_FUNC_RETURN; 13222 } 13223 if (ts_type == CPRIMOD_1588_TS_TYPE_SW_CAP) { 13224 if (direction == CPRIMOD_DIR_TX) { 13225 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CAP_INTR_STATUSr(unit, port, &ts)); 13226 ts_stat = soc_reg64_field_get(unit, CPRI_TX_1588_CAP_INTR_STATUSr, ts, TX_CAPTURED_TS_INTERRUPT_STATUSf); 13227 ts_stat32 = COMPILER_64_LO(ts_stat); 13228 if (ts_stat32) { 13229 *count = 1; 13230 *captured_time = soc_reg64_field_get(unit, CPRI_TX_1588_CAP_INTR_STATUSr, ts, TX_CAPTURED_TSf); 13231 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_CAP_INTR_STATUSr(unit, port, ts)); 13232 /* disable Tx capture as auto clear is Hw not working */ 13233 COMPILER_64_ZERO(val_zero); 13234 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CTRLr(unit, port, &ctrl)); 13235 soc_reg64_field_set(unit, CPRI_TX_1588_CTRLr, &ctrl, 13236 TX_TS_CAPTURE_REQf, val_zero); 13237 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_CTRLr(unit, port, ctrl)); 13238 } else { 13239 *count = 0; 13240 } 13241 } else { 13242 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CAP_INTR_STATUSr(unit, port, &ts)); 13243 ts_stat = soc_reg64_field_get(unit, CPRI_RX_1588_CAP_INTR_STATUSr, ts, RX_CAPTURED_TS_INTERRUPT_STATUSf); 13244 ts_stat32 = COMPILER_64_LO(ts_stat); 13245 if (ts_stat32) { 13246 *count = 1; 13247 *captured_time = soc_reg64_field_get(unit, CPRI_RX_1588_CAP_INTR_STATUSr, ts, RX_CAPTURED_TSf); 13248 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_1588_CAP_INTR_STATUSr(unit, port, ts)); 13249 } else { 13250 *count = 0; 13251 } 13252 } 13253 } else if (ts_type == CPRIMOD_1588_TS_TYPE_FIFO) { 13254 if (direction == CPRIMOD_DIR_TX) { 13255 for (i=0; i < mx_cnt; i++) { 13256 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_FIFO_INTR_STATUSr(unit, port, &ts)); 13257 ts_stat = soc_reg64_field_get(unit, CPRI_TX_1588_FIFO_INTR_STATUSr, ts, TX_TS_FIFO_INTERRUPT_STATUSf); 13258 ts_stat32 = COMPILER_64_LO(ts_stat); 13259 if (ts_stat32 == 0) { 13260 break; 13261 } else { 13262 captured_time[i] = soc_reg64_field_get(unit, CPRI_TX_1588_FIFO_INTR_STATUSr, ts, TX_TS_FIFOf); 13263 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_FIFO_INTR_STATUSr(unit, port, ts)); 13264 } 13265 } 13266 *count = i; 13267 } else { 13268 for (i=0; i < mx_cnt; i++) { 13269 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_FIFO_INTR_STATUSr(unit, port, &ts)); 13270 ts_stat = soc_reg64_field_get(unit, CPRI_RX_1588_FIFO_INTR_STATUSr, ts, RX_TS_FIFO_INTERRUPT_STATUSf); 13271 ts_stat32 = COMPILER_64_LO(ts_stat); 13272 if (ts_stat32 == 0) { 13273 break; 13274 } else { 13275 captured_time[i] = soc_reg64_field_get(unit, CPRI_RX_1588_FIFO_INTR_STATUSr, ts, RX_TS_FIFOf); 13276 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_1588_FIFO_INTR_STATUSr(unit, port, ts)); 13277 } 13278 } 13279 *count = i; 13280 } 13281 } 13282 13283 exit: 13284 SOC_FUNC_RETURN; 13285 } 13286 13287 13288 int cprif_drv_1588_timestamp_adjust_set(int unit, int port, cprimod_direction_t direction, cprimod_1588_time_t* adjust_time) 13289 { 13290 uint64 ts_adj_l; 13291 uint64 adj_time; 13292 uint64 adj_time_sub; 13293 uint64 bitflipmsk; 13294 uint64 bit53mask; 13295 SOC_INIT_FUNC_DEFS; 13296 13297 COMPILER_64_COPY(adj_time, adjust_time->nano_sec); 13298 COMPILER_64_SHL(adj_time,4); 13299 COMPILER_64_SET(adj_time_sub,0, adjust_time->sub_nano_sec & 0xf); 13300 COMPILER_64_OR(adj_time, adj_time_sub); 13301 if(adjust_time->sign_bit) { 13302 COMPILER_64_SET(bitflipmsk, 0xffffffff, 0xffffffff); 13303 COMPILER_64_XOR(adj_time, bitflipmsk); 13304 COMPILER_64_ADD_32(adj_time, 1); 13305 } 13306 COMPILER_64_SET(bit53mask, 0x1fffff, 0xffffffff); 13307 COMPILER_64_AND(adj_time, bit53mask); 13308 COMPILER_64_ZERO(ts_adj_l); 13309 if(direction == CPRIMOD_DIR_TX) { 13310 soc_reg64_field_set(unit, CPRI_TX_TS_ADJ_CTRLr, &ts_adj_l, TX_TS_ADJf, adj_time); 13311 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_TS_ADJ_CTRLr(unit, port, ts_adj_l)); 13312 } else { 13313 soc_reg64_field_set(unit, CPRI_RX_TS_ADJ_CTRLr, &ts_adj_l, RX_TS_ADJf, adj_time); 13314 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_TS_ADJ_CTRLr(unit, port, ts_adj_l)); 13315 } 13316 13317 exit: 13318 SOC_FUNC_RETURN; 13319 13320 } 13321 int cprif_drv_1588_timestamp_adjust_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_time_t* adjust_time) 13322 { 13323 uint64 ts_adj; 13324 uint64 adj_time; 13325 uint64 adj_time_cp; 13326 uint64 bitflipmsk; 13327 uint64 bit53mask; 13328 uint32 subns; 13329 SOC_INIT_FUNC_DEFS; 13330 adjust_time->sign_bit = 0; 13331 if(direction == CPRIMOD_DIR_TX) { 13332 _SOC_IF_ERR_EXIT(READ_CPRI_TX_TS_ADJ_CTRLr(unit, port, &ts_adj)); 13333 adj_time = soc_reg64_field_get(unit, CPRI_TX_TS_ADJ_CTRLr, ts_adj, TX_TS_ADJf); 13334 } else { 13335 _SOC_IF_ERR_EXIT(READ_CPRI_RX_TS_ADJ_CTRLr(unit, port, &ts_adj)); 13336 adj_time = soc_reg64_field_get(unit, CPRI_RX_TS_ADJ_CTRLr, ts_adj, RX_TS_ADJf); 13337 } 13338 COMPILER_64_COPY(adj_time_cp, adj_time); 13339 COMPILER_64_SHR(adj_time_cp,52); 13340 if(!COMPILER_64_IS_ZERO(adj_time_cp)) { 13341 adjust_time->sign_bit = 1; 13342 COMPILER_64_SET(bitflipmsk, 0xffffffff, 0xffffffff); 13343 COMPILER_64_XOR(adj_time, bitflipmsk); 13344 COMPILER_64_ADD_32(adj_time, 1); 13345 } 13346 COMPILER_64_SET(bit53mask, 0x1fffff, 0xffffffff); 13347 COMPILER_64_AND(adj_time, bit53mask); 13348 COMPILER_64_TO_32_LO(subns, adj_time); 13349 adjust_time->sub_nano_sec = subns & 0xf; 13350 COMPILER_64_COPY(adjust_time->nano_sec, adj_time); 13351 COMPILER_64_SHR(adjust_time->nano_sec,4); 13352 13353 exit: 13354 SOC_FUNC_RETURN; 13355 } 13356 13357 int cprif_drv_1588_timestamp_fifo_config_set(int unit, int port, cprimod_direction_t direction, uint16 modulo) 13358 { 13359 uint64 ctrl; 13360 uint64 mod_ctl; 13361 SOC_INIT_FUNC_DEFS; 13362 13363 COMPILER_64_SET(mod_ctl, 0, modulo); 13364 if(direction == CPRIMOD_DIR_TX) { 13365 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CTRLr(unit, port, &ctrl)); 13366 soc_reg64_field_set(unit, CPRI_TX_1588_CTRLr, &ctrl, TX_TS_MOD_CNTf, mod_ctl); 13367 _SOC_IF_ERR_EXIT(WRITE_CPRI_TX_1588_CTRLr(unit, port, ctrl)); 13368 } else { 13369 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CTRLr(unit, port, &ctrl)); 13370 soc_reg64_field_set(unit, CPRI_RX_1588_CTRLr, &ctrl, RX_TS_MOD_CNTf, mod_ctl); 13371 _SOC_IF_ERR_EXIT(WRITE_CPRI_RX_1588_CTRLr(unit, port, ctrl)); 13372 } 13373 13374 exit: 13375 SOC_FUNC_RETURN; 13376 13377 } 13378 13379 int cprif_drv_1588_timestamp_fifo_config_get(int unit, int port, cprimod_direction_t direction, uint16* modulo) 13380 { 13381 uint64 ctrl; 13382 uint64 mod_ctl; 13383 SOC_INIT_FUNC_DEFS; 13384 if(direction == CPRIMOD_DIR_TX) { 13385 _SOC_IF_ERR_EXIT(READ_CPRI_TX_1588_CTRLr(unit, port, &ctrl)); 13386 mod_ctl = soc_reg64_field_get(unit, CPRI_TX_1588_CTRLr, ctrl, TX_TS_MOD_CNTf); 13387 } else { 13388 _SOC_IF_ERR_EXIT(READ_CPRI_RX_1588_CTRLr(unit, port, &ctrl)); 13389 mod_ctl = soc_reg64_field_get(unit, CPRI_RX_1588_CTRLr, ctrl, RX_TS_MOD_CNTf); 13390 } 13391 COMPILER_64_TO_32_LO(*modulo, mod_ctl); 13392 13393 exit: 13394 SOC_FUNC_RETURN; 13395 } 13396 13397 int cprif_drv_1588_timestamp_cmic_config_set(int unit, int port, cprimod_direction_t direction, uint16 modulo) 13398 { 13399 uint32 mod_ctrl; 13400 SOC_INIT_FUNC_DEFS; 13401 _SOC_IF_ERR_EXIT(READ_CPRI_RF_TS_CTRLr(unit, port, &mod_ctrl)); 13402 if(direction == CPRIMOD_DIR_TX) { 13403 soc_reg_field_set(unit, CPRI_RF_TS_CTRLr, &mod_ctrl, TX_RF_TS_IF_MOD_CNTf, modulo); 13404 } else { 13405 soc_reg_field_set(unit, CPRI_RF_TS_CTRLr, &mod_ctrl, RX_RF_TS_IF_MOD_CNTf, modulo); 13406 } 13407 _SOC_IF_ERR_EXIT(WRITE_CPRI_RF_TS_CTRLr(unit, port, mod_ctrl)); 13408 13409 exit: 13410 SOC_FUNC_RETURN; 13411 13412 } 13413 13414 int cprif_drv_1588_timestamp_cmic_config_get(int unit, int port, cprimod_direction_t direction, uint16* modulo) 13415 { 13416 uint32 mod_ctrl; 13417 SOC_INIT_FUNC_DEFS; 13418 _SOC_IF_ERR_EXIT(READ_CPRI_RF_TS_CTRLr(unit, port, &mod_ctrl)); 13419 if(direction == CPRIMOD_DIR_TX) { 13420 *modulo = soc_reg_field_get(unit, CPRI_RF_TS_CTRLr, mod_ctrl, TX_RF_TS_IF_MOD_CNTf); 13421 } else { 13422 *modulo = soc_reg_field_get(unit, CPRI_RF_TS_CTRLr, mod_ctrl, RX_RF_TS_IF_MOD_CNTf); 13423 } 13424 13425 exit: 13426 SOC_FUNC_RETURN; 13427 } 13428 13429 int cprif_drv_ingress_presentation_time_enable_set(int unit, int port, int enable) 13430 { 13431 uint32 reg_val=0; 13432 uint64 reg64_val; 13433 uint32 field_buf; 13434 uint64 field64_buf; 13435 cprif_pm_version_t pm_version; 13436 13437 SOC_INIT_FUNC_DEFS; 13438 13439 COMPILER_64_ZERO(reg64_val); 13440 _SOC_IF_ERR_EXIT 13441 (cprif_pm_version_get(unit, port, &pm_version)); 13442 13443 if (CPRIF_CLPORT_IS_A0(pm_version)) { 13444 /* 13445 * Only A0, use 32 bits. 13446 */ 13447 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr_REG32(unit, port, ®_val)); 13448 field_buf = enable ? 1 : 0; 13449 soc_reg_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®_val, 13450 ING_AGNOSTIC_MODE_ENf, field_buf); 13451 _SOC_IF_ERR_EXIT(WRITE_CPRI_ING_PRES_TM_CTRLr_REG32(unit, port, reg_val)); 13452 } else if (CPRIF_CLPORT_IS_B0(pm_version)) { 13453 /* 13454 * B0 use 64 bits. 13455 */ 13456 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr(unit, port, ®64_val)); 13457 if (enable) { 13458 COMPILER_64_SET(field64_buf, 0, 1); 13459 } else { 13460 COMPILER_64_ZERO(field64_buf); 13461 } 13462 soc_reg64_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®64_val, 13463 ING_AGNOSTIC_MODE_ENf, field64_buf); 13464 _SOC_IF_ERR_EXIT(WRITE_CPRI_ING_PRES_TM_CTRLr(unit, port, reg64_val)); 13465 } else { 13466 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Need Support for New Version.\n")); 13467 } 13468 13469 exit: 13470 SOC_FUNC_RETURN; 13471 } 13472 13473 int cprif_drv_ingress_presentation_time_enable_get(int unit, int port, int* enable) 13474 { 13475 uint32 reg_val; 13476 uint64 reg64_val; 13477 uint32 field_buf; 13478 uint64 field64_buf; 13479 cprif_pm_version_t pm_version; 13480 SOC_INIT_FUNC_DEFS; 13481 13482 _SOC_IF_ERR_EXIT 13483 (cprif_pm_version_get(unit, port, &pm_version)); 13484 13485 *enable = 0; 13486 if (CPRIF_CLPORT_IS_A0(pm_version)) { 13487 /* 13488 * Only A0, use 32 bits. 13489 */ 13490 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr_REG32(unit, port, ®_val)); 13491 field_buf = soc_reg_field_get(unit, CPRI_ING_PRES_TM_CTRLr , reg_val, 13492 ING_AGNOSTIC_MODE_ENf); 13493 *enable = field_buf? 1:0; 13494 } else if (CPRIF_CLPORT_IS_B0(pm_version)) { 13495 /* 13496 * B0 use 64 bits. 13497 */ 13498 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr(unit, port, ®64_val)); 13499 field64_buf = soc_reg64_field_get(unit, CPRI_ING_PRES_TM_CTRLr , reg64_val, 13500 ING_AGNOSTIC_MODE_ENf); 13501 *enable = (COMPILER_64_IS_ZERO(field64_buf))? 0:1; 13502 13503 } else { 13504 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Need Support for New Version.\n")); 13505 } 13506 13507 exit: 13508 SOC_FUNC_RETURN; 13509 } 13510 13511 13512 int cprif_drv_ingress_presentation_time_config_set(int unit, int port, cprif_cpri_ingress_pres_time_ctrl_t* config) 13513 { 13514 uint32 reg_val; 13515 uint64 reg64_val; 13516 uint32 field_buf; 13517 uint64 field64_buf; 13518 cprif_pm_version_t pm_version; 13519 SOC_INIT_FUNC_DEFS; 13520 13521 _SOC_IF_ERR_EXIT 13522 (cprif_pm_version_get(unit, port, &pm_version)); 13523 13524 if (CPRIF_CLPORT_IS_A0(pm_version)) { 13525 /* 13526 * Only A0, use 32 bits. 13527 */ 13528 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr_REG32(unit, port, ®_val)); 13529 field_buf = config->pres_mod_cnt; 13530 soc_reg_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®_val, 13531 ING_PRES_MOD_CNTf, field_buf); 13532 field_buf = config->bfn_offset; 13533 soc_reg_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®_val, 13534 ING_PRES_BFN_OFFSETf, field_buf); 13535 field_buf = config->hfn_offset; 13536 soc_reg_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®_val, 13537 ING_PRES_HFN_OFFSETf, field_buf); 13538 field_buf = config->hfrm_sync; 13539 soc_reg_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®_val, 13540 ING_PRES_HFRM_SYNCf, field_buf); 13541 field_buf = config->rfrm_sync; 13542 soc_reg_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®_val, 13543 ING_PRES_RFRM_SYNCf, field_buf); 13544 _SOC_IF_ERR_EXIT(WRITE_CPRI_ING_PRES_TM_CTRLr_REG32(unit, port, reg_val)); 13545 13546 } else if (CPRIF_CLPORT_IS_B0(pm_version)) { 13547 /* 13548 * B0 use 64 bits. 13549 */ 13550 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr(unit, port, ®64_val)); 13551 COMPILER_64_SET(field64_buf, 0, config->pres_mod_cnt); 13552 soc_reg64_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®64_val, 13553 ING_PRES_MOD_CNTf, field64_buf); 13554 COMPILER_64_SET(field64_buf, 0, config->bfn_offset); 13555 soc_reg64_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®64_val, 13556 ING_PRES_BFN_OFFSETf, field64_buf); 13557 COMPILER_64_SET(field64_buf, 0, config->hfn_offset); 13558 soc_reg64_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®64_val, 13559 ING_PRES_HFN_OFFSETf, field64_buf); 13560 COMPILER_64_SET(field64_buf, 0, config->hfrm_sync); 13561 soc_reg64_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®64_val, 13562 ING_PRES_HFRM_SYNCf, field64_buf); 13563 COMPILER_64_SET(field64_buf, 0, config->rfrm_sync); 13564 soc_reg64_field_set(unit, CPRI_ING_PRES_TM_CTRLr , ®64_val, 13565 ING_PRES_RFRM_SYNCf, field64_buf); 13566 _SOC_IF_ERR_EXIT(WRITE_CPRI_ING_PRES_TM_CTRLr(unit, port, reg64_val)); 13567 13568 /* set approximate increment disable setting. */ 13569 _SOC_IF_ERR_EXIT(READ_CPRI_ING_TS_APPROX_INCr(unit, port, ®_val)); 13570 field_buf = config->approx_inc_disable? 1:0; 13571 soc_reg_field_set(unit, CPRI_ING_TS_APPROX_INCr, ®_val, 13572 ING_PRES_TS_APPROX_INC_DISABLEf, field_buf); 13573 _SOC_IF_ERR_EXIT(WRITE_CPRI_ING_TS_APPROX_INCr(unit, port, reg_val)); 13574 13575 13576 } else { 13577 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Need Support for New Version.\n")); 13578 } 13579 13580 exit: 13581 SOC_FUNC_RETURN; 13582 } 13583 13584 int cprif_drv_ingress_presentation_time_config_get(int unit, int port, cprif_cpri_ingress_pres_time_ctrl_t* config) 13585 { 13586 uint32 reg_val; 13587 uint64 reg64_val; 13588 uint64 rval64; 13589 cprif_pm_version_t pm_version; 13590 SOC_INIT_FUNC_DEFS; 13591 13592 _SOC_IF_ERR_EXIT 13593 (cprif_pm_version_get(unit, port, &pm_version)); 13594 13595 if (CPRIF_CLPORT_IS_A0(pm_version)) { 13596 /* 13597 * Only A0, use 32 bits. 13598 */ 13599 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr_REG32(unit, port, ®_val)); 13600 13601 config->pres_mod_cnt = soc_reg_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg_val, 13602 ING_PRES_MOD_CNTf); 13603 13604 config->bfn_offset = soc_reg_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg_val, 13605 ING_PRES_BFN_OFFSETf); 13606 13607 config->hfn_offset = soc_reg_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg_val, 13608 ING_PRES_HFN_OFFSETf); 13609 13610 config->hfrm_sync = soc_reg_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg_val, 13611 ING_PRES_HFRM_SYNCf); 13612 13613 config->rfrm_sync = soc_reg_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg_val, 13614 ING_PRES_RFRM_SYNCf); 13615 13616 } else if (CPRIF_CLPORT_IS_B0(pm_version)) { 13617 /* 13618 * B0 use 64 bits. 13619 */ 13620 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_CTRLr(unit, port, ®64_val)); 13621 13622 rval64 = soc_reg64_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg64_val, 13623 ING_PRES_MOD_CNTf); 13624 COMPILER_64_TO_32_LO(config->pres_mod_cnt, rval64); 13625 13626 rval64 = soc_reg64_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg64_val, 13627 ING_PRES_BFN_OFFSETf); 13628 COMPILER_64_TO_32_LO(config->bfn_offset, rval64); 13629 13630 rval64 = soc_reg64_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg64_val, 13631 ING_PRES_HFN_OFFSETf); 13632 COMPILER_64_TO_32_LO(config->hfn_offset, rval64); 13633 13634 rval64 = soc_reg64_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg64_val, 13635 ING_PRES_HFRM_SYNCf); 13636 COMPILER_64_TO_32_LO(config->hfrm_sync, rval64); 13637 13638 rval64 = soc_reg64_field_get(unit, CPRI_ING_PRES_TM_CTRLr, reg64_val, 13639 ING_PRES_RFRM_SYNCf); 13640 COMPILER_64_TO_32_LO(config->rfrm_sync, rval64); 13641 } else { 13642 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Need Support for New Version.\n")); 13643 } 13644 13645 exit: 13646 SOC_FUNC_RETURN; 13647 } 13648 13649 int cprif_drv_ingress_presentation_time_adjust_set(int unit, int port, uint32 time) 13650 { 13651 uint32 reg_val; 13652 uint32 field_buf; 13653 SOC_INIT_FUNC_DEFS; 13654 13655 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_OFFSETr(unit, port, ®_val)); 13656 field_buf = time; 13657 soc_reg_field_set(unit, CPRI_ING_PRES_TM_OFFSETr , ®_val, 13658 ING_PRES_TIME_OFFSETf, field_buf); 13659 _SOC_IF_ERR_EXIT(WRITE_CPRI_ING_PRES_TM_OFFSETr(unit, port, reg_val)); 13660 13661 exit: 13662 SOC_FUNC_RETURN; 13663 13664 } 13665 13666 int cprif_drv_ingress_presentation_time_adjust_get(int unit, int port, uint32* time) 13667 { 13668 uint32 reg_val; 13669 SOC_INIT_FUNC_DEFS; 13670 13671 _SOC_IF_ERR_EXIT(READ_CPRI_ING_PRES_TM_OFFSETr(unit, port, ®_val)); 13672 *time = soc_reg_field_get(unit, CPRI_ING_PRES_TM_OFFSETr , reg_val, 13673 ING_PRES_TIME_OFFSETf); 13674 13675 exit: 13676 SOC_FUNC_RETURN; 13677 } 13678 13679 int cprif_drv_ingress_presentation_time_approximate_increment_set(int unit, int port, uint32 time) 13680 { 13681 uint32 reg_val; 13682 uint32 field_buf; 13683 SOC_INIT_FUNC_DEFS; 13684 13685 _SOC_IF_ERR_EXIT(READ_CPRI_ING_TS_APPROX_INCr(unit, port, ®_val)); 13686 field_buf = time; 13687 soc_reg_field_set(unit, CPRI_ING_TS_APPROX_INCr , ®_val, 13688 ING_PRES_TS_APPROX_INCf, field_buf); 13689 _SOC_IF_ERR_EXIT(WRITE_CPRI_ING_TS_APPROX_INCr(unit, port, reg_val)); 13690 13691 exit: 13692 SOC_FUNC_RETURN; 13693 } 13694 13695 int cprif_drv_ingress_presentation_time_approximate_increment_get(int unit, int port, uint32* time) 13696 { 13697 uint32 reg_val; 13698 SOC_INIT_FUNC_DEFS; 13699 13700 _SOC_IF_ERR_EXIT(READ_CPRI_ING_TS_APPROX_INCr(unit, port, ®_val)); 13701 *time = soc_reg_field_get(unit, CPRI_ING_TS_APPROX_INCr , reg_val, 13702 ING_PRES_TS_APPROX_INCf); 13703 13704 exit: 13705 SOC_FUNC_RETURN; 13706 } 13707 13708 int cprif_drv_egress_agnostic_mode_enable_set(int unit, int port, int enable, cprimod_cpri_roe_ordering_info_option_t mode) 13709 { 13710 uint64 reg_val; 13711 uint64 field_buf; 13712 uint32 agnostic_mode = 0; 13713 uint32 buff_extend = 0; 13714 cprif_pm_version_t pm_version; 13715 SOC_INIT_FUNC_DEFS; 13716 13717 _SOC_IF_ERR_EXIT(READ_CPRI_DECAP_AGNOSTIC_MODE_CTRLr(unit, port, ®_val)); 13718 13719 _SOC_IF_ERR_EXIT 13720 (cprif_pm_version_get(unit, port, &pm_version)); 13721 13722 if (CPRIF_CLPORT_IS_A0(pm_version)) { 13723 if (mode != CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP){ 13724 LOG_CLI(("Forcing to timestamp Mode. This A0 HW only support Timestamp Mode.\n")); 13725 } 13726 COMPILER_64_SET(field_buf, 0, (uint32) enable ? 1: 0); 13727 soc_reg64_field_set(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , ®_val, 13728 EGR_AGNOSTIC_MODE_ENf, field_buf); 13729 } else if (CPRIF_CLPORT_IS_B0(pm_version)) { 13730 13731 if (enable) { 13732 if (mode == CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP){ 13733 agnostic_mode = 1; 13734 buff_extend = 0; 13735 } else {/* Seq_Num */ 13736 agnostic_mode = 0; 13737 buff_extend = 1; 13738 } 13739 } else { /* Disable */ 13740 agnostic_mode = 0; 13741 buff_extend = 0; 13742 } 13743 13744 COMPILER_64_SET(field_buf, 0, agnostic_mode); 13745 soc_reg64_field_set(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , ®_val, 13746 EGR_AGNOSTIC_MODE_ENf, field_buf); 13747 13748 COMPILER_64_SET(field_buf, 0, buff_extend); 13749 soc_reg64_field_set(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , ®_val, 13750 EGR_BUFF_EXTENDf, field_buf); 13751 } else { 13752 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Need Support for New Version.\n")); 13753 } 13754 _SOC_IF_ERR_EXIT(WRITE_CPRI_DECAP_AGNOSTIC_MODE_CTRLr(unit, port, reg_val)); 13755 13756 exit: 13757 SOC_FUNC_RETURN; 13758 } 13759 13760 int cprif_drv_egress_agnostic_mode_enable_get(int unit, int port, int* enable, cprimod_cpri_roe_ordering_info_option_t* mode) 13761 { 13762 uint64 reg_val; 13763 uint64 field_buf; 13764 uint32 agnostic_mode; 13765 uint32 buff_extend; 13766 cprif_pm_version_t pm_version; 13767 SOC_INIT_FUNC_DEFS; 13768 13769 _SOC_IF_ERR_EXIT(READ_CPRI_DECAP_AGNOSTIC_MODE_CTRLr(unit, port, ®_val)); 13770 13771 _SOC_IF_ERR_EXIT 13772 (cprif_pm_version_get(unit, port, &pm_version)); 13773 13774 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , reg_val, 13775 EGR_AGNOSTIC_MODE_ENf); 13776 agnostic_mode = COMPILER_64_LO(field_buf); 13777 13778 if (CPRIF_CLPORT_IS_A0(pm_version)) { 13779 *enable = agnostic_mode? 1 :0; 13780 /* In A0, only timestamp is supported. */ 13781 *mode = CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP; 13782 } else if (CPRIF_CLPORT_IS_B0(pm_version)) { 13783 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , reg_val, 13784 EGR_BUFF_EXTENDf); 13785 buff_extend = COMPILER_64_LO(field_buf); 13786 if (agnostic_mode) { 13787 *enable = TRUE; 13788 *mode = CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP; 13789 } else if (buff_extend) { 13790 *enable = TRUE; 13791 *mode = CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM; 13792 } else { 13793 *enable = FALSE; 13794 } 13795 } else { 13796 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Need Support for New Version.\n")); 13797 } 13798 exit: 13799 SOC_FUNC_RETURN; 13800 } 13801 13802 int cprif_drv_egress_agnostic_mode_config_set(int unit, int port, cprif_cpri_egress_agnostic_config_t* config) 13803 { 13804 uint64 reg_val; 13805 uint64 field_buf; 13806 SOC_INIT_FUNC_DEFS; 13807 13808 _SOC_IF_ERR_EXIT(READ_CPRI_DECAP_AGNOSTIC_MODE_CTRLr(unit, port, ®_val)); 13809 13810 COMPILER_64_SET(field_buf, 0, (uint32) config->rd_ptr_max); 13811 soc_reg64_field_set(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , ®_val, 13812 EGR_AGNOSTIC_MODE_RD_PTR_MAXf, field_buf); 13813 13814 COMPILER_64_SET(field_buf, 0, (uint32) config->queue_num); 13815 soc_reg64_field_set(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , ®_val, 13816 EGR_AGNOSTIC_MODE_QUEUE_NUMf, field_buf); 13817 13818 COMPILER_64_SET(field_buf, 0, (uint32) config->mod_cnt); 13819 soc_reg64_field_set(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , ®_val, 13820 EGR_AGNOSTIC_MODE_MOD_CNTf, field_buf); 13821 13822 _SOC_IF_ERR_EXIT(WRITE_CPRI_DECAP_AGNOSTIC_MODE_CTRLr(unit, port, reg_val)); 13823 13824 exit: 13825 SOC_FUNC_RETURN; 13826 } 13827 13828 int cprif_drv_egress_agnostic_mode_config_get(int unit, int port, cprif_cpri_egress_agnostic_config_t* config) 13829 { 13830 uint64 reg_val; 13831 uint64 field_buf; 13832 SOC_INIT_FUNC_DEFS; 13833 13834 _SOC_IF_ERR_EXIT(READ_CPRI_DECAP_AGNOSTIC_MODE_CTRLr(unit, port, ®_val)); 13835 13836 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , reg_val, 13837 EGR_AGNOSTIC_MODE_RD_PTR_MAXf); 13838 13839 config->rd_ptr_max = COMPILER_64_LO(field_buf); 13840 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , reg_val, 13841 EGR_AGNOSTIC_MODE_QUEUE_NUMf); 13842 config->queue_num = COMPILER_64_LO(field_buf); 13843 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_AGNOSTIC_MODE_CTRLr , reg_val, 13844 EGR_AGNOSTIC_MODE_MOD_CNTf); 13845 config->mod_cnt = COMPILER_64_LO(field_buf); 13846 exit: 13847 SOC_FUNC_RETURN; 13848 } 13849 13850 int cprif_drv_egress_presentation_time_config_set(int unit, int port, uint32 mod_offset, uint32 mod_count) 13851 { 13852 uint64 reg_val; 13853 uint64 field_buf; 13854 SOC_INIT_FUNC_DEFS; 13855 13856 _SOC_IF_ERR_EXIT(READ_CPRI_DECAP_PRES_TIME_CTRLr(unit, port, ®_val)); 13857 COMPILER_64_SET(field_buf,0, mod_offset); 13858 soc_reg64_field_set(unit, CPRI_DECAP_PRES_TIME_CTRLr , ®_val, 13859 PRES_TIME_MOD_OFFSETf, field_buf); 13860 COMPILER_64_SET(field_buf,0, mod_count); 13861 soc_reg64_field_set(unit, CPRI_DECAP_PRES_TIME_CTRLr , ®_val, 13862 PRES_TIME_MOD_CNTf, field_buf); 13863 _SOC_IF_ERR_EXIT(WRITE_CPRI_DECAP_PRES_TIME_CTRLr(unit, port, reg_val)); 13864 13865 exit: 13866 SOC_FUNC_RETURN; 13867 } 13868 13869 int cprif_drv_egress_presentation_time_config_get(int unit, int port, uint32* mod_offset, uint32* mod_count) 13870 { 13871 uint64 reg_val; 13872 uint64 field_buf; 13873 SOC_INIT_FUNC_DEFS; 13874 13875 _SOC_IF_ERR_EXIT(READ_CPRI_DECAP_PRES_TIME_CTRLr(unit, port, ®_val)); 13876 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_PRES_TIME_CTRLr , reg_val, 13877 PRES_TIME_MOD_OFFSETf); 13878 *mod_offset = COMPILER_64_LO(field_buf); 13879 13880 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_PRES_TIME_CTRLr , reg_val, 13881 PRES_TIME_MOD_CNTf); 13882 *mod_count = COMPILER_64_LO(field_buf); 13883 exit: 13884 SOC_FUNC_RETURN; 13885 } 13886 13887 int cprif_drv_cpri_port_ecc_interrupt_status_get(int unit, int port, 13888 cprimod_cpri_ecc_intr_info_t *ecc_err_info) 13889 { 13890 uint32 rval = 0; 13891 uint32 i = 0, err_addr = 0x0; 13892 int is_ecc_intr_enabled = 0; 13893 int ecc1b_err = 0, ecc2b_err = 0, ecc_multib_err = 0; 13894 _cpri_ecc_interrupts_info_t *intr_ptr = &_cpri_port_ecc_intrs_info[0]; 13895 SOC_INIT_FUNC_DEFS; 13896 13897 /* 13898 * Check if RX or TX ECC interrupts are enabled, currently 13899 * there is no selective RX or TX ECC interrupt enabling. 13900 * Checking either RX or TX ECC interrupt is ok to process 13901 * further. 13902 */ 13903 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_rx_interrupt_enable_get(unit, port, 13904 CPRIF_RX_ECC_ERR_INTR, &is_ecc_intr_enabled)); 13905 13906 if (!is_ecc_intr_enabled) { 13907 /* ecc interrupt not enabled skip further processing */ 13908 return SOC_E_NONE; 13909 } 13910 /* Init the ecc error type to none */ 13911 ecc_err_info->ecc_num_bits_err = CPRIMOD_PM_ECC_ERR_NONE; 13912 13913 while (intr_ptr->ecc_status_reg != INVALIDr) { 13914 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, intr_ptr->ecc_status_reg, 13915 port, 0, &rval)); 13916 13917 /* Check if 1-bit ECC error */ 13918 if (intr_ptr->ecc1b_err_status_fld != INVALIDf) { 13919 ecc1b_err = soc_reg_field_get(unit, intr_ptr->ecc_status_reg, 13920 rval, intr_ptr->ecc1b_err_status_fld); 13921 } 13922 13923 /* Check if 2-bit ECC error */ 13924 if (intr_ptr->ecc2b_err_status_fld != INVALIDf) { 13925 ecc2b_err = soc_reg_field_get(unit, intr_ptr->ecc_status_reg, 13926 rval, intr_ptr->ecc2b_err_status_fld); 13927 } 13928 13929 /* Check if multi-bit ECC error */ 13930 if (intr_ptr->ecc_multib_err_status_fld != INVALIDf) { 13931 ecc_multib_err = soc_reg_field_get(unit, intr_ptr->ecc_status_reg, 13932 rval, 13933 intr_ptr->ecc_multib_err_status_fld); 13934 } 13935 13936 /* Get the address */ 13937 if (ecc1b_err || ecc2b_err || ecc_multib_err) { 13938 err_addr = soc_reg_field_get(unit, intr_ptr->ecc_status_reg, 13939 rval, intr_ptr->ecc_event_addr); 13940 13941 ecc_err_info->port = port; 13942 ecc_err_info->err_mem_info = intr_ptr->mem; 13943 ecc_err_info->ecc_reg_info = intr_ptr->ecc_status_reg; 13944 ecc_err_info->ecc_num_bits_err = (ecc1b_err)? 13945 CPRIMOD_PM_ECC_ERR_1_BIT: (ecc2b_err)? 13946 CPRIMOD_PM_ECC_ERR_2_BIT: 13947 CPRIMOD_PM_ECC_ERR_MULTI_BIT; 13948 ecc_err_info->err_addr = err_addr; 13949 ecc_err_info->mem_str = intr_ptr->mem_str; 13950 } 13951 13952 /* Clear status if 1-bit ECC error */ 13953 if (ecc1b_err) { 13954 soc_reg_field_set(unit, intr_ptr->ecc_status_reg, 13955 &rval, intr_ptr->ecc1b_err_status_fld, 1); 13956 } 13957 13958 /* Clear status if 2-bit ECC error */ 13959 if (ecc2b_err) { 13960 soc_reg_field_set(unit, intr_ptr->ecc_status_reg, 13961 &rval, intr_ptr->ecc2b_err_status_fld, 1); 13962 } 13963 13964 /* Clear status if multi-bit ECC error */ 13965 if (ecc_multib_err) { 13966 soc_reg_field_set(unit, intr_ptr->ecc_status_reg, 13967 &rval, intr_ptr->ecc_multib_err_status_fld, 1); 13968 } 13969 13970 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, intr_ptr->ecc_status_reg, 13971 port, 0, rval)); 13972 i++; 13973 13974 intr_ptr = &_cpri_port_ecc_intrs_info[i]; 13975 13976 if (ecc1b_err || ecc2b_err || ecc_multib_err) { 13977 LOG_VERBOSE(BSL_LS_BCM_PORT, 13978 (BSL_META_U(unit, 13979 "[i-%d] [1b-%d] [2b-%d] [mb-%d] [addr-%x]\n\n"), 13980 i, ecc1b_err, ecc2b_err, 13981 ecc_multib_err, err_addr)); 13982 break; 13983 } 13984 } 13985 13986 exit: 13987 SOC_FUNC_RETURN; 13988 } 13989 13990 int cprif_drv_cpri_port_ecc_interrupt_enable_set(int unit, int port, int enable) 13991 { 13992 uint32 rval = 0; 13993 uint32 i = 0; 13994 _cpri_ecc_interrupts_info_t *intr_ptr = &_cpri_port_ecc_intrs_info[0]; 13995 SOC_INIT_FUNC_DEFS; 13996 13997 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_rx_interrupts_enable_set(unit, port, 13998 CPRIF_RX_ECC_ERR_INTR, enable)); 13999 14000 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_tx_interrupts_enable_set(unit, port, 14001 CPRIF_TX_ECC_ERR_INTR, enable)); 14002 14003 while (intr_ptr->ecc_en_reg != INVALIDr) { 14004 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, intr_ptr->ecc_en_reg, 14005 port, 0, &rval)); 14006 14007 /* Enable 1-bit ECC error reporting */ 14008 if (intr_ptr->ecc1b_en_fld != INVALIDf) { 14009 soc_reg_field_set(unit, intr_ptr->ecc_en_reg, 14010 &rval, intr_ptr->ecc1b_en_fld, 14011 enable); 14012 } 14013 14014 /* Enable 2-bit ECC error reporting */ 14015 if (intr_ptr->ecc2b_en_fld != INVALIDf) { 14016 soc_reg_field_set(unit, intr_ptr->ecc_en_reg, 14017 &rval, intr_ptr->ecc2b_en_fld, 14018 enable); 14019 } 14020 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, intr_ptr->ecc_en_reg, 14021 port, 0, rval)); 14022 intr_ptr = &_cpri_port_ecc_intrs_info[++i]; 14023 } 14024 14025 exit: 14026 SOC_FUNC_RETURN; 14027 } 14028 14029 int cprif_drv_cpri_port_interrupt_type_num_subid_get(int unit, int port, 14030 cprimod_cpri_port_intr_type_t intr, 14031 int* num_subid) 14032 14033 { 14034 SOC_INIT_FUNC_DEFS; 14035 if (!(intr < _shrCpriIntrCount)) { 14036 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Invalid interrupt type(%d)", intr)); 14037 } 14038 *num_subid = _cpri_port_intrs_info[intr].max_id; 14039 exit: 14040 SOC_FUNC_RETURN; 14041 } 14042 14043 int cprif_drv_cpri_port_interrupt_type_enable_set(int unit, int port, 14044 cprimod_cpri_port_intr_type_t intr, 14045 int data, int enable) 14046 { 14047 uint32 rval = 0; 14048 uint64 rval64; 14049 SOC_INIT_FUNC_DEFS; 14050 14051 COMPILER_64_ZERO(rval64); 14052 if (!(intr < _shrCpriIntrCount)) { 14053 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Invalid interrupt type(%d)", intr)); 14054 } 14055 14056 /* check if the register is 64-bit */ 14057 if (_cpri_port_intrs_info[intr].is_64bit) { 14058 _SOC_IF_ERR_EXIT(soc_reg64_get(unit, 14059 _cpri_port_intrs_info[intr].enable_reg, 14060 port, 0, &rval64)); 14061 /* Check if the programming is queue num or AxC id based */ 14062 if (_cpri_port_intrs_info[intr].max_id != 0) { 14063 if (enable) { 14064 COMPILER_64_BITSET(rval64, data); 14065 } else { 14066 COMPILER_64_BITCLR(rval64, data); 14067 } 14068 } else { 14069 /* set the field */ 14070 soc_reg64_field32_set(unit, _cpri_port_intrs_info[intr].enable_reg, 14071 &rval64, _cpri_port_intrs_info[intr].enable_field, 14072 enable); 14073 } 14074 _SOC_IF_ERR_EXIT(soc_reg64_set(unit, 14075 _cpri_port_intrs_info[intr].enable_reg, 14076 port, 0, rval64)); 14077 } else { 14078 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, 14079 _cpri_port_intrs_info[intr].enable_reg, 14080 port, 0, &rval)); 14081 /* Check if the programming is queue num based */ 14082 if (_cpri_port_intrs_info[intr].max_id != 0) { 14083 rval |= (1 << data); 14084 } else { 14085 /* set the field */ 14086 soc_reg_field_set(unit, _cpri_port_intrs_info[intr].enable_reg, 14087 &rval, 14088 _cpri_port_intrs_info[intr].enable_field, enable); 14089 } 14090 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, 14091 _cpri_port_intrs_info[intr].enable_reg, port, 0, rval)); 14092 } 14093 exit: 14094 SOC_FUNC_RETURN; 14095 } 14096 14097 int cprif_drv_cpri_port_interrupt_type_enable_get(int unit, int port, 14098 cprimod_cpri_port_intr_type_t intr, 14099 int data, int *enable) 14100 { 14101 uint32 rval = 0; 14102 uint64 rval64; 14103 SOC_INIT_FUNC_DEFS; 14104 14105 if (!(intr < _shrCpriIntrCount)) { 14106 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Invalid interrupt type(%d)", intr)); 14107 } 14108 14109 /* check if the register is 64-bit */ 14110 COMPILER_64_ZERO(rval64); 14111 if (_cpri_port_intrs_info[intr].is_64bit) { 14112 _SOC_IF_ERR_EXIT(soc_reg64_get(unit, 14113 _cpri_port_intrs_info[intr].enable_reg, 14114 port, 0, &rval64)); 14115 /* Check if the programming is queue num or AxC id based */ 14116 if (_cpri_port_intrs_info[intr].max_id != 0) { 14117 *enable = COMPILER_64_BITTEST(rval64, data); 14118 } else { 14119 /* set the field */ 14120 *enable = soc_reg64_field32_get(unit, 14121 _cpri_port_intrs_info[intr].enable_reg, rval64, 14122 _cpri_port_intrs_info[intr].enable_field); 14123 } 14124 } else { 14125 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, 14126 _cpri_port_intrs_info[intr].enable_reg, 14127 port, 0, &rval)); 14128 /* Check if the programming is queue num based */ 14129 if (_cpri_port_intrs_info[intr].max_id != 0) { 14130 *enable = (rval & (1 << data)); 14131 } else { 14132 /* set the field */ 14133 *enable = soc_reg_field_get(unit, 14134 _cpri_port_intrs_info[intr].enable_reg, rval, 14135 _cpri_port_intrs_info[intr].enable_field); 14136 } 14137 } 14138 14139 exit: 14140 SOC_FUNC_RETURN; 14141 } 14142 14143 int cprif_drv_cpri_port_interrupt_type_status_get(int unit, int port, 14144 cprimod_cpri_port_intr_type_t intr, 14145 int data, int *status) 14146 { 14147 uint32 rval = 0; 14148 uint32 clear32 = 0; 14149 uint64 rval64; 14150 uint64 clear64; 14151 SOC_INIT_FUNC_DEFS; 14152 14153 if (!(intr < _shrCpriIntrCount)) { 14154 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Invalid interrupt type(%d)", intr)); 14155 } 14156 14157 /* check if the register is 64-bit */ 14158 COMPILER_64_ZERO(rval64); 14159 COMPILER_64_ZERO(clear64); 14160 if (_cpri_port_intrs_info[intr].is_status_64bit) { 14161 _SOC_IF_ERR_EXIT(soc_reg64_get(unit, 14162 _cpri_port_intrs_info[intr].status_reg, 14163 port, 0, &rval64)); 14164 /* Check if the programming is queue num or AxC id based */ 14165 if (_cpri_port_intrs_info[intr].max_id != 0) { 14166 *status = COMPILER_64_BITTEST(rval64, data); 14167 COMPILER_64_BITSET(clear64, data); 14168 } else { 14169 /* get the field */ 14170 *status = soc_reg64_field32_get(unit, 14171 _cpri_port_intrs_info[intr].status_reg, rval64, 14172 _cpri_port_intrs_info[intr].status_field); 14173 14174 /* prep to clear the status w1tc bit. */ 14175 soc_reg64_field32_set(unit, 14176 _cpri_port_intrs_info[intr].status_reg, &clear64, 14177 _cpri_port_intrs_info[intr].status_field,1); 14178 } 14179 14180 if (*status) { 14181 _SOC_IF_ERR_EXIT 14182 (soc_reg64_set(unit, 14183 _cpri_port_intrs_info[intr].status_reg, 14184 port, 0, clear64)); 14185 } 14186 } else { 14187 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, 14188 _cpri_port_intrs_info[intr].status_reg, 14189 port, 0, &rval)); 14190 /* Check if the programming is queue num based */ 14191 if (_cpri_port_intrs_info[intr].max_id != 0) { 14192 *status = (rval & (1 << data)); 14193 clear32 = (1 << data); 14194 } else { 14195 /* set the field */ 14196 *status = soc_reg_field_get(unit, 14197 _cpri_port_intrs_info[intr].status_reg, rval, 14198 _cpri_port_intrs_info[intr].status_field); 14199 /* prep to clear w1tc bit. */ 14200 soc_reg_field_set(unit, 14201 _cpri_port_intrs_info[intr].status_reg, &clear32, 14202 _cpri_port_intrs_info[intr].status_field,1); 14203 } 14204 if (*status) { 14205 _SOC_IF_ERR_EXIT 14206 (soc_reg32_set(unit, 14207 _cpri_port_intrs_info[intr].status_reg, 14208 port, 0, clear32)); 14209 } 14210 } 14211 14212 exit: 14213 SOC_FUNC_RETURN; 14214 } 14215 14216 14217 int cprif_drv_compression_entry_set(int unit, int port, 14218 int index, 14219 uint32 comp_val_0, 14220 uint32 comp_val_1) 14221 { 14222 int blk; 14223 int phy_port; 14224 int port_core_index; 14225 soc_mem_t local_mem; 14226 soc_mem_t mem_select[] = { CPRI_DECAP_COMP_TAB_0m, 14227 CPRI_DECAP_COMP_TAB_1m, 14228 CPRI_DECAP_COMP_TAB_2m, 14229 CPRI_DECAP_COMP_TAB_3m}; 14230 14231 uint32 *wr_data_ptr = NULL; 14232 uint32 num_words; 14233 uint32 field_buf; 14234 SOC_INIT_FUNC_DEFS; 14235 14236 if (index >= CPRIF_COMPRESSION_TABLE_SIZE) { 14237 _SOC_EXIT_WITH_ERR 14238 (SOC_E_PARAM, ("Compression table unsuppoprted index %d.\n",index)); 14239 } 14240 14241 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14242 port_core_index = ((phy_port-1)%4); 14243 14244 local_mem = mem_select[port_core_index]; 14245 14246 num_words = soc_mem_entry_words(unit, local_mem); 14247 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 14248 CPRIMOD_NULL_CHECK(wr_data_ptr); 14249 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 14250 14251 field_buf = comp_val_0; 14252 soc_mem_field_set(unit, local_mem, wr_data_ptr,COMP_VAL_0f, &field_buf); 14253 field_buf = comp_val_1; 14254 soc_mem_field_set(unit, local_mem, wr_data_ptr,COMP_VAL_1f, &field_buf); 14255 14256 14257 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14258 _SOC_IF_ERR_EXIT 14259 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 14260 14261 exit: 14262 sal_free(wr_data_ptr); 14263 SOC_FUNC_RETURN; 14264 14265 } 14266 14267 int cprif_drv_compression_entry_get(int unit, int port, 14268 int index, 14269 uint32* comp_val_0, 14270 uint32* comp_val_1) 14271 { 14272 int blk; 14273 int phy_port; 14274 int port_core_index; 14275 soc_mem_t local_mem; 14276 soc_mem_t mem_select[] = { CPRI_DECAP_COMP_TAB_0m, 14277 CPRI_DECAP_COMP_TAB_1m, 14278 CPRI_DECAP_COMP_TAB_2m, 14279 CPRI_DECAP_COMP_TAB_3m}; 14280 uint32 *rd_data_ptr = NULL; 14281 uint32 num_words; 14282 uint32 field_buf; 14283 SOC_INIT_FUNC_DEFS; 14284 14285 if (index >= CPRIF_COMPRESSION_TABLE_SIZE) { 14286 _SOC_EXIT_WITH_ERR 14287 (SOC_E_PARAM, ("Compression table unsuppoprted index %d.\n",index)); 14288 } 14289 14290 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14291 port_core_index = ((phy_port-1)%4); 14292 14293 local_mem = mem_select[port_core_index]; 14294 14295 num_words = soc_mem_entry_words(unit, local_mem); 14296 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 14297 CPRIMOD_NULL_CHECK(rd_data_ptr); 14298 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 14299 14300 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14301 _SOC_IF_ERR_EXIT 14302 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 14303 14304 soc_mem_field_get(unit, local_mem, rd_data_ptr, COMP_VAL_0f, &field_buf); 14305 *comp_val_0 = field_buf; 14306 14307 soc_mem_field_get(unit, local_mem, rd_data_ptr, COMP_VAL_1f, &field_buf); 14308 *comp_val_1 = field_buf; 14309 exit: 14310 sal_free(rd_data_ptr); 14311 SOC_FUNC_RETURN; 14312 } 14313 14314 int cprif_drv_decompression_entry_set(int unit, int port, 14315 int index, 14316 uint32 decomp_val) 14317 { 14318 int blk; 14319 int phy_port; 14320 int port_core_index; 14321 soc_mem_t local_mem; 14322 soc_mem_t mem_select[] = { CPRI_DECAP_ULAW_LUT_0m, 14323 CPRI_DECAP_ULAW_LUT_1m, 14324 CPRI_DECAP_ULAW_LUT_2m, 14325 CPRI_DECAP_ULAW_LUT_3m}; 14326 14327 uint32 *wr_data_ptr = NULL; 14328 uint32 num_words; 14329 uint32 field_buf; 14330 SOC_INIT_FUNC_DEFS; 14331 14332 if (index >= CPRIF_DECOMPRESSION_TABLE_SIZE) { 14333 _SOC_EXIT_WITH_ERR 14334 (SOC_E_PARAM, ("DeCompression table unsuppoprted index %d.\n",index)); 14335 } 14336 14337 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14338 port_core_index = ((phy_port-1)%4); 14339 14340 local_mem = mem_select[port_core_index]; 14341 14342 num_words = soc_mem_entry_words(unit, local_mem); 14343 wr_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 14344 CPRIMOD_NULL_CHECK(wr_data_ptr); 14345 sal_memset(wr_data_ptr, 0, sizeof(uint32) * num_words); 14346 14347 field_buf = decomp_val; 14348 soc_mem_field_set(unit, local_mem, wr_data_ptr,DECOMP_VALf, &field_buf); 14349 14350 14351 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14352 _SOC_IF_ERR_EXIT 14353 (soc_mem_write(unit, local_mem, blk, index, wr_data_ptr)); 14354 14355 exit: 14356 sal_free(wr_data_ptr); 14357 SOC_FUNC_RETURN; 14358 14359 } 14360 14361 int cprif_drv_decompression_entry_get(int unit, int port, 14362 int index, 14363 uint32* decomp_val) 14364 { 14365 int blk; 14366 int phy_port; 14367 int port_core_index; 14368 soc_mem_t local_mem; 14369 soc_mem_t mem_select[] = { CPRI_DECAP_ULAW_LUT_0m, 14370 CPRI_DECAP_ULAW_LUT_1m, 14371 CPRI_DECAP_ULAW_LUT_2m, 14372 CPRI_DECAP_ULAW_LUT_3m}; 14373 uint32 *rd_data_ptr = NULL; 14374 uint32 num_words; 14375 uint32 field_buf; 14376 SOC_INIT_FUNC_DEFS; 14377 14378 if (index >= CPRIF_DECOMPRESSION_TABLE_SIZE) { 14379 _SOC_EXIT_WITH_ERR 14380 (SOC_E_PARAM, ("DeCompression table unsuppoprted index %d.\n",index)); 14381 } 14382 14383 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14384 port_core_index = ((phy_port-1)%4); 14385 14386 local_mem = mem_select[port_core_index]; 14387 14388 num_words = soc_mem_entry_words(unit, local_mem); 14389 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 14390 CPRIMOD_NULL_CHECK(rd_data_ptr); 14391 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 14392 14393 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14394 _SOC_IF_ERR_EXIT 14395 (soc_mem_read(unit, local_mem, blk, index, rd_data_ptr)); 14396 14397 soc_mem_field_get(unit, local_mem, rd_data_ptr, DECOMP_VALf, &field_buf); 14398 *decomp_val = field_buf; 14399 14400 exit: 14401 sal_free(rd_data_ptr); 14402 SOC_FUNC_RETURN; 14403 } 14404 14405 int cprif_drv_decap_queue_flow_control_entry_set(int unit, int port, 14406 int index, 14407 int enable, 14408 uint32 queue_num, 14409 uint32 xon_buff_count, 14410 uint32 xoff_buff_count) 14411 { 14412 int blk; 14413 int phy_port; 14414 int port_core_index; 14415 soc_mem_t local_mem; 14416 soc_mem_t mem_select[] = {CPRI_DECAP_FLOW_CONTROL_0m, 14417 CPRI_DECAP_FLOW_CONTROL_1m, 14418 CPRI_DECAP_FLOW_CONTROL_2m, 14419 CPRI_DECAP_FLOW_CONTROL_3m}; 14420 uint32 wr_data=0; 14421 uint32 field_buf; 14422 SOC_INIT_FUNC_DEFS; 14423 14424 if (index >= CPRIF_CONTROL_FLOW_TABLE_SIZE) { 14425 _SOC_EXIT_WITH_ERR 14426 (SOC_E_PARAM, ("Flow Control table unsuppoprted index %d.\n",index)); 14427 } 14428 14429 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14430 port_core_index = ((phy_port-1)%4); 14431 14432 local_mem = mem_select[port_core_index]; 14433 14434 14435 field_buf = enable? 1:0; 14436 soc_mem_field_set(unit, local_mem, &wr_data, FLOW_CONTROL_ENf, &field_buf); 14437 14438 field_buf = queue_num; 14439 soc_mem_field_set(unit, local_mem, &wr_data, QUEUE_NUMf, &field_buf); 14440 14441 field_buf = xon_buff_count; 14442 soc_mem_field_set(unit, local_mem, &wr_data, XONf, &field_buf); 14443 14444 field_buf = xoff_buff_count; 14445 soc_mem_field_set(unit, local_mem, &wr_data, XOFFf, &field_buf); 14446 14447 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14448 _SOC_IF_ERR_EXIT 14449 (soc_mem_write(unit, local_mem, blk, index, &wr_data)); 14450 14451 exit: 14452 SOC_FUNC_RETURN; 14453 14454 } 14455 14456 int cprif_drv_decap_queue_flow_control_entry_get(int unit, int port, 14457 int index, 14458 int* enable, 14459 uint32* queue_num, 14460 uint32* xon_buff_count, 14461 uint32* xoff_buff_count) 14462 { 14463 int blk; 14464 int phy_port; 14465 int port_core_index; 14466 soc_mem_t local_mem; 14467 soc_mem_t mem_select[] = {CPRI_DECAP_FLOW_CONTROL_0m, 14468 CPRI_DECAP_FLOW_CONTROL_1m, 14469 CPRI_DECAP_FLOW_CONTROL_2m, 14470 CPRI_DECAP_FLOW_CONTROL_3m}; 14471 uint32 rd_data=0; 14472 uint32 field_buf; 14473 SOC_INIT_FUNC_DEFS; 14474 14475 if (index >= CPRIF_CONTROL_FLOW_TABLE_SIZE) { 14476 _SOC_EXIT_WITH_ERR 14477 (SOC_E_PARAM, ("Flow Control table unsuppoprted index %d.\n",index)); 14478 } 14479 14480 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14481 port_core_index = ((phy_port-1)%4); 14482 14483 local_mem = mem_select[port_core_index]; 14484 14485 14486 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14487 _SOC_IF_ERR_EXIT 14488 (soc_mem_read(unit, local_mem, blk, index, &rd_data)); 14489 14490 soc_mem_field_get(unit, local_mem, &rd_data, FLOW_CONTROL_ENf, &field_buf); 14491 *enable = field_buf; 14492 14493 soc_mem_field_get(unit, local_mem, &rd_data, QUEUE_NUMf, &field_buf); 14494 *queue_num = field_buf; 14495 14496 soc_mem_field_get(unit, local_mem, &rd_data, XONf, &field_buf); 14497 *xon_buff_count = field_buf; 14498 14499 soc_mem_field_get(unit, local_mem, &rd_data, XOFFf, &field_buf); 14500 *xoff_buff_count = field_buf; 14501 exit: 14502 SOC_FUNC_RETURN; 14503 } 14504 14505 int cprif_drv_cpri_port_fec_enable_set(int unit, int port, cprimod_direction_t dir, int enable) 14506 { 14507 uint64 data; 14508 SOC_INIT_FUNC_DEFS; 14509 14510 if (dir == CPRIMOD_DIR_RX) { 14511 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_CL91_CTRLr(unit, port, &data)); 14512 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_CL91_CTRLr, &data, RXPCS_FEC_CL91_ENABLEf, (uint32) enable); 14513 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_CL91_CTRLr(unit, port, data)); 14514 } else { 14515 _SOC_IF_ERR_EXIT(READ_CPRI_TXPCS_FEC_CL91_CTRLr(unit, port, &data)); 14516 soc_reg64_field32_set(unit, CPRI_TXPCS_FEC_CL91_CTRLr, &data, TXPCS_FEC_CL91_ENABLEf, (uint32) enable); 14517 _SOC_IF_ERR_EXIT(WRITE_CPRI_TXPCS_FEC_CL91_CTRLr(unit, port, data)); 14518 } 14519 exit: 14520 SOC_FUNC_RETURN; 14521 } 14522 14523 int cprif_drv_cpri_port_fec_enable_get(int unit, int port, cprimod_direction_t dir, int* enable) 14524 { 14525 uint64 data; 14526 SOC_INIT_FUNC_DEFS; 14527 14528 if (dir == CPRIMOD_DIR_RX) { 14529 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_CL91_CTRLr(unit, port, &data)); 14530 *enable = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_CL91_CTRLr, data, RXPCS_FEC_CL91_ENABLEf); 14531 } else { 14532 _SOC_IF_ERR_EXIT(READ_CPRI_TXPCS_FEC_CL91_CTRLr(unit, port, &data)); 14533 *enable = soc_reg64_field32_get(unit, CPRI_TXPCS_FEC_CL91_CTRLr, data, TXPCS_FEC_CL91_ENABLEf); 14534 } 14535 14536 exit: 14537 SOC_FUNC_RETURN; 14538 } 14539 14540 int cprif_drv_cpri_port_fec_timestamp_config_set(int unit, int port, cprimod_direction_t dir, const cprimod_fec_timestamp_config_t* config) 14541 { 14542 uint64 data; 14543 uint32 source_select=0; 14544 SOC_INIT_FUNC_DEFS; 14545 14546 if (dir == CPRIMOD_DIR_RX) { 14547 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_CL91_TS_CTRLr(unit, port, &data)); 14548 soc_reg64_field32_set(unit, CPRI_RXPCS_CL91_TS_CTRLr, &data, CL91_TS_ENf, config->enable); 14549 14550 source_select = (config->fec_fifo_ts_source_select == CPRIMOD_CPRI_FEC_TS_SOURCE_257B)? 1:0; 14551 soc_reg64_field32_set(unit, CPRI_RXPCS_CL91_TS_CTRLr, &data, SEND_CL91_257B_TS_TO_TSFIFOf, source_select); 14552 14553 source_select = (config->fec_cmic_ts_source_select == CPRIMOD_CPRI_FEC_TS_SOURCE_66B)? 1:0; 14554 soc_reg64_field32_set(unit, CPRI_RXPCS_CL91_TS_CTRLr, &data, SEND_CL91_66B_TS_TO_CMICf, source_select); 14555 14556 soc_reg64_field32_set(unit, CPRI_RXPCS_CL91_TS_CTRLr, &data, CB_3_BIT_OFFSETf, config->control_bit_offset_0); 14557 soc_reg64_field32_set(unit, CPRI_RXPCS_CL91_TS_CTRLr, &data, CB_2_BIT_OFFSETf, config->control_bit_offset_1); 14558 soc_reg64_field32_set(unit, CPRI_RXPCS_CL91_TS_CTRLr, &data, CB_1_BIT_OFFSETf, config->control_bit_offset_2); 14559 soc_reg64_field32_set(unit, CPRI_RXPCS_CL91_TS_CTRLr, &data, CB_0_BIT_OFFSETf, config->control_bit_offset_3); 14560 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_CL91_TS_CTRLr(unit, port, data)); 14561 } else { 14562 _SOC_IF_ERR_EXIT(READ_CPRI_TXPCS_CL91_TS_CTRLr(unit, port, &data)); 14563 soc_reg64_field32_set(unit, CPRI_TXPCS_CL91_TS_CTRLr, &data, CL91_TS_ENf, config->enable); 14564 soc_reg64_field32_set(unit, CPRI_TXPCS_CL91_TS_CTRLr, &data, SEND_CL91_257B_TS_TO_TSFIFOf,(uint32)config->fec_fifo_ts_source_select); 14565 soc_reg64_field32_set(unit, CPRI_TXPCS_CL91_TS_CTRLr, &data, SEND_CL91_66B_TS_TO_CMICf, (uint32)config->fec_cmic_ts_source_select); 14566 soc_reg64_field32_set(unit, CPRI_TXPCS_CL91_TS_CTRLr, &data, CB_3_BIT_OFFSETf, config->control_bit_offset_0); 14567 soc_reg64_field32_set(unit, CPRI_TXPCS_CL91_TS_CTRLr, &data, CB_2_BIT_OFFSETf, config->control_bit_offset_1); 14568 soc_reg64_field32_set(unit, CPRI_TXPCS_CL91_TS_CTRLr, &data, CB_1_BIT_OFFSETf, config->control_bit_offset_2); 14569 soc_reg64_field32_set(unit, CPRI_TXPCS_CL91_TS_CTRLr, &data, CB_0_BIT_OFFSETf, config->control_bit_offset_3); 14570 _SOC_IF_ERR_EXIT(WRITE_CPRI_TXPCS_CL91_TS_CTRLr(unit, port, data)); 14571 } 14572 exit: 14573 SOC_FUNC_RETURN; 14574 } 14575 14576 int cprif_drv_cpri_port_fec_timestamp_config_get(int unit, int port, cprimod_direction_t dir, cprimod_fec_timestamp_config_t* config) 14577 { 14578 uint64 data; 14579 SOC_INIT_FUNC_DEFS; 14580 14581 if (dir == CPRIMOD_DIR_RX) { 14582 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_CL91_TS_CTRLr(unit, port, &data)); 14583 config->enable = soc_reg64_field32_get(unit, CPRI_RXPCS_CL91_TS_CTRLr, data, CL91_TS_ENf); 14584 config->fec_fifo_ts_source_select = soc_reg64_field32_get(unit, CPRI_RXPCS_CL91_TS_CTRLr, data, SEND_CL91_257B_TS_TO_TSFIFOf); 14585 if (config->fec_fifo_ts_source_select == 1) { 14586 config->fec_fifo_ts_source_select = CPRIMOD_CPRI_FEC_TS_SOURCE_257B; 14587 } else { 14588 config->fec_fifo_ts_source_select = CPRIMOD_CPRI_FEC_TS_SOURCE_66B; 14589 } 14590 config->fec_cmic_ts_source_select = soc_reg64_field32_get(unit, CPRI_RXPCS_CL91_TS_CTRLr, data, SEND_CL91_66B_TS_TO_CMICf); 14591 if (config->fec_cmic_ts_source_select ==1) { 14592 config->fec_cmic_ts_source_select = CPRIMOD_CPRI_FEC_TS_SOURCE_66B; 14593 } else { 14594 config->fec_cmic_ts_source_select = CPRIMOD_CPRI_FEC_TS_SOURCE_257B; 14595 } 14596 14597 config->control_bit_offset_0 = soc_reg64_field32_get(unit, CPRI_RXPCS_CL91_TS_CTRLr, data, CB_3_BIT_OFFSETf); 14598 config->control_bit_offset_1 = soc_reg64_field32_get(unit, CPRI_RXPCS_CL91_TS_CTRLr, data, CB_2_BIT_OFFSETf); 14599 config->control_bit_offset_2 = soc_reg64_field32_get(unit, CPRI_RXPCS_CL91_TS_CTRLr, data, CB_1_BIT_OFFSETf); 14600 config->control_bit_offset_3 = soc_reg64_field32_get(unit, CPRI_RXPCS_CL91_TS_CTRLr, data, CB_0_BIT_OFFSETf); 14601 } else { 14602 _SOC_IF_ERR_EXIT(READ_CPRI_TXPCS_CL91_TS_CTRLr(unit, port, &data)); 14603 config->enable = soc_reg64_field32_get(unit, CPRI_TXPCS_CL91_TS_CTRLr, data, CL91_TS_ENf); 14604 config->fec_fifo_ts_source_select = soc_reg64_field32_get(unit, CPRI_TXPCS_CL91_TS_CTRLr, data, SEND_CL91_257B_TS_TO_TSFIFOf); 14605 config->fec_cmic_ts_source_select = soc_reg64_field32_get(unit, CPRI_TXPCS_CL91_TS_CTRLr, data, SEND_CL91_66B_TS_TO_CMICf); 14606 config->control_bit_offset_0 = soc_reg64_field32_get(unit, CPRI_TXPCS_CL91_TS_CTRLr, data, CB_3_BIT_OFFSETf); 14607 config->control_bit_offset_1 = soc_reg64_field32_get(unit, CPRI_TXPCS_CL91_TS_CTRLr, data, CB_2_BIT_OFFSETf); 14608 config->control_bit_offset_2 = soc_reg64_field32_get(unit, CPRI_TXPCS_CL91_TS_CTRLr, data, CB_1_BIT_OFFSETf); 14609 config->control_bit_offset_3 = soc_reg64_field32_get(unit, CPRI_TXPCS_CL91_TS_CTRLr, data, CB_0_BIT_OFFSETf); 14610 } 14611 14612 exit: 14613 SOC_FUNC_RETURN; 14614 } 14615 14616 int cprif_drv_cpri_port_fec_aux_config_set(int unit, int port, cprimod_fec_aux_config_para_t parameter_id, uint32 value) 14617 { 14618 uint64 data; 14619 SOC_INIT_FUNC_DEFS; 14620 14621 switch(parameter_id) { 14622 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX: 14623 _SOC_IF_ERR_EXIT(READ_CPRI_TXPCS_FEC_CL91_CTRLr(unit, port, &data)); 14624 soc_reg64_field32_set(unit, CPRI_TXPCS_FEC_CL91_CTRLr, &data, TXPCS_FEC_CL91_SCR_BYPASSf, value); 14625 _SOC_IF_ERR_EXIT(WRITE_CPRI_TXPCS_FEC_CL91_CTRLr(unit, port, data)); 14626 break; 14627 case CPRIMOD_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX: 14628 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_1_CTRLr(unit, port, &data)); 14629 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_1_CTRLr, &data, RXPCS_FEC_CS_CW_DESCRAMBLE_BYPASSf, value); 14630 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_1_CTRLr(unit, port, data)); 14631 break; 14632 case CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE: 14633 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_2_CTRLr(unit, port, &data)); 14634 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_2_CTRLr, &data, RXPCS_FEC_DECODER_BYPASS_INDICATION_ENABLEf, value); 14635 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_2_CTRLr(unit, port, data)); 14636 break; 14637 case CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE: 14638 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_2_CTRLr(unit, port, &data)); 14639 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_2_CTRLr, &data, RXPCS_FEC_DECODER_BYPASS_CORRECTION_ENABLEf, value); 14640 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_2_CTRLr(unit, port, data)); 14641 break; 14642 case CPRIMOD_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCK_ENABLE: 14643 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14644 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_3_CTRLr, &data, RXPCS_FEC_GBOX_CORRUPT_ALTERNATE_BLOCKS_ENABLEf, value); 14645 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_3_CTRLr(unit, port, data)); 14646 break; 14647 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE: 14648 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14649 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_3_CTRLr, &data, RXPCS_FEC_GBOX_SYMBOL_ERROR_CORRUPT_ENABLEf, value); 14650 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_3_CTRLr(unit, port, data)); 14651 break; 14652 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TIMER_PERIOD: 14653 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14654 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_3_CTRLr, &data, RXPCS_FEC_GBOX_SYMBOL_ERROR_TMR_PERIODf, value); 14655 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_3_CTRLr(unit, port, data)); 14656 break; 14657 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_COUNT_THRESHOLD: 14658 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14659 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_3_CTRLr, &data, RXPCS_FEC_GBOX_SYMBOL_ERR_CNT_THRESHOLDf, value); 14660 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_3_CTRLr(unit, port, data)); 14661 break; 14662 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_WINDOW: 14663 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14664 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_3_CTRLr, &data, RXPCS_FEC_GBOX_SET_SYMB_ERR_WINDOW_128f, value); 14665 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_3_CTRLr(unit, port, data)); 14666 break; 14667 case CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_DENOMINATOR: 14668 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_4_CTRLr(unit, port, &data)); 14669 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_4_CTRLr, &data, RXPCS_FEC_GBOX_TICK_DENOMf, value); 14670 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_4_CTRLr(unit, port, data)); 14671 break; 14672 case CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_NUMERATOR: 14673 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_4_CTRLr(unit, port, &data)); 14674 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_4_CTRLr, &data, RXPCS_FEC_GBOX_TICK_NUMERf, value); 14675 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_4_CTRLr(unit, port, data)); 14676 break; 14677 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SOFT_RESET: 14678 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_0_CTRLr(unit, port, &data)); 14679 soc_reg64_field32_set(unit, CPRI_RXPCS_FEC_0_CTRLr, &data, RXPCS_FEC_SOFT_RESETf, value); 14680 _SOC_IF_ERR_EXIT(WRITE_CPRI_RXPCS_FEC_0_CTRLr(unit, port, data)); 14681 break; 14682 default : 14683 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Bad Aux config")); 14684 break; 14685 } 14686 exit: 14687 SOC_FUNC_RETURN; 14688 } 14689 14690 int cprif_drv_cpri_port_fec_aux_config_get(int unit, int port, cprimod_fec_aux_config_para_t parameter_id, uint32* value) 14691 { 14692 uint64 data; 14693 SOC_INIT_FUNC_DEFS; 14694 14695 switch(parameter_id) { 14696 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX: 14697 _SOC_IF_ERR_EXIT(READ_CPRI_TXPCS_FEC_CL91_CTRLr(unit, port, &data)); 14698 *value = soc_reg64_field32_get(unit, CPRI_TXPCS_FEC_CL91_CTRLr, data, TXPCS_FEC_CL91_SCR_BYPASSf); 14699 break; 14700 case CPRIMOD_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX: 14701 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_1_CTRLr(unit, port, &data)); 14702 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_1_CTRLr, data, RXPCS_FEC_CS_CW_DESCRAMBLE_BYPASSf); 14703 break; 14704 case CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE: 14705 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_2_CTRLr(unit, port, &data)); 14706 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_2_CTRLr, data, RXPCS_FEC_DECODER_BYPASS_INDICATION_ENABLEf); 14707 break; 14708 case CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE: 14709 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_2_CTRLr(unit, port, &data)); 14710 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_2_CTRLr, data, RXPCS_FEC_DECODER_BYPASS_CORRECTION_ENABLEf); 14711 break; 14712 case CPRIMOD_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCK_ENABLE: 14713 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14714 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_3_CTRLr, data, RXPCS_FEC_GBOX_CORRUPT_ALTERNATE_BLOCKS_ENABLEf); 14715 break; 14716 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE: 14717 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14718 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_3_CTRLr, data, RXPCS_FEC_GBOX_SYMBOL_ERROR_CORRUPT_ENABLEf); 14719 break; 14720 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TIMER_PERIOD: 14721 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14722 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_3_CTRLr, data, RXPCS_FEC_GBOX_SYMBOL_ERROR_TMR_PERIODf); 14723 break; 14724 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_COUNT_THRESHOLD: 14725 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14726 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_3_CTRLr, data, RXPCS_FEC_GBOX_SYMBOL_ERR_CNT_THRESHOLDf); 14727 break; 14728 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_WINDOW: 14729 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_3_CTRLr(unit, port, &data)); 14730 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_3_CTRLr, data, RXPCS_FEC_GBOX_SET_SYMB_ERR_WINDOW_128f); 14731 break; 14732 case CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_DENOMINATOR: 14733 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_4_CTRLr(unit, port, &data)); 14734 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_4_CTRLr, data, RXPCS_FEC_GBOX_TICK_DENOMf); 14735 break; 14736 case CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_NUMERATOR: 14737 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_4_CTRLr(unit, port, &data)); 14738 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_4_CTRLr, data, RXPCS_FEC_GBOX_TICK_NUMERf); 14739 break; 14740 case CPRIMOD_CPRI_FEC_AUX_CONFIG_SOFT_RESET: 14741 _SOC_IF_ERR_EXIT(READ_CPRI_RXPCS_FEC_0_CTRLr(unit, port, &data)); 14742 *value = soc_reg64_field32_get(unit, CPRI_RXPCS_FEC_0_CTRLr, data, RXPCS_FEC_SOFT_RESETf); 14743 break; 14744 default : 14745 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Bad Aux config")); 14746 break; 14747 } 14748 exit: 14749 SOC_FUNC_RETURN; 14750 14751 } 14752 14753 int cprif_drv_init(int unit, int port) 14754 { 14755 uint32 read_val; 14756 SOC_INIT_FUNC_DEFS; 14757 14758 _SOC_IF_ERR_EXIT(cprif_drv_pmd_ctrl_ln_por_h_rstb_set(unit, port)); 14759 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 14760 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, GLAS_RST_Hf, 1); 14761 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, GLAS_RSTf, 1); 14762 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, DATAPATH_CREDIT_RSTf, 1); 14763 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_TX_Hf, 1); 14764 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_TX_DPf, 1); 14765 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_Hf, 1); 14766 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_DPf, 1); 14767 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_TX_Hf, 1); 14768 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_TX_DPf,1); 14769 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_RX_Hf, 1); 14770 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_RX_DPf,1); 14771 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_TX_Hf, 1); 14772 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_TX_DPf, 1); 14773 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_Hf, 1); 14774 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_DPf, 1); 14775 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 14776 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 14777 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, GLAS_RST_Hf, 0); 14778 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, GLAS_RSTf, 0); 14779 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, DATAPATH_CREDIT_RSTf, 0); 14780 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_TX_Hf, 0); 14781 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_TX_DPf, 0); 14782 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_Hf, 0); 14783 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_DPf, 0); 14784 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_TX_Hf, 0); 14785 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_TX_DPf,0); 14786 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_RX_Hf, 0); 14787 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_DATAPATH_RX_DPf,0); 14788 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_TX_Hf, 0); 14789 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_TX_DPf, 0); 14790 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_Hf, 0); 14791 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_DPf, 0); 14792 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 14793 14794 exit: 14795 SOC_FUNC_RETURN; 14796 } 14797 14798 int cprif_drv_port_link_down_reset(int unit, int port) 14799 { 14800 uint32 read_val; 14801 SOC_INIT_FUNC_DEFS; 14802 14803 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 14804 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_DPf, 1); 14805 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_DPf, 1); 14806 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 14807 SOC_IF_ERROR_RETURN(READ_CPRI_RST_CTRLr(unit, port, &read_val)); 14808 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_RX_DPf, 0); 14809 soc_reg_field_set(unit, CPRI_RST_CTRLr, &read_val, RESET_CIP_RX_DPf, 0); 14810 SOC_IF_ERROR_RETURN(WRITE_CPRI_RST_CTRLr(unit, port, read_val)); 14811 14812 SOC_FUNC_RETURN; 14813 } 14814 int cprif_drv_rx_gcw_word_get(int unit, int port, int group_index, uint16* word) 14815 { 14816 uint64 reg_val; 14817 uint64 field_buf; 14818 int reg_index; 14819 int phy_port; 14820 int port_core_index; 14821 uint32 mask; 14822 soc_mem_t local_mem; 14823 soc_mem_t mem_select[] = {CPRI_GCW_CFG_TAB_CFG_0m, 14824 CPRI_GCW_CFG_TAB_CFG_1m, 14825 CPRI_GCW_CFG_TAB_CFG_2m, 14826 CPRI_GCW_CFG_TAB_CFG_3m}; 14827 14828 14829 soc_reg_t reg_select[] = {CPRI_RX_GCW_0_STATUSr, 14830 CPRI_RX_GCW_1_STATUSr, 14831 CPRI_RX_GCW_2_STATUSr, 14832 CPRI_RX_GCW_3_STATUSr}; 14833 14834 soc_field_t reg_field_select[] = {RXFRM_GCW_WORD0f, 14835 RXFRM_GCW_WORD1f, 14836 RXFRM_GCW_WORD2f, 14837 RXFRM_GCW_WORD3f, 14838 RXFRM_GCW_WORD4f, 14839 RXFRM_GCW_WORD5f, 14840 RXFRM_GCW_WORD6f, 14841 RXFRM_GCW_WORD7f, 14842 RXFRM_GCW_WORD8f, 14843 RXFRM_GCW_WORD9f, 14844 RXFRM_GCW_WORD10f, 14845 RXFRM_GCW_WORD11f, 14846 RXFRM_GCW_WORD12f, 14847 RXFRM_GCW_WORD13f, 14848 RXFRM_GCW_WORD14f, 14849 RXFRM_GCW_WORD15f}; 14850 14851 uint32 *rd_data_ptr; 14852 uint32 field_buf32; 14853 uint32 num_words; 14854 uint32 blk_num=0; 14855 14856 SOC_INIT_FUNC_DEFS; 14857 14858 if (group_index >= CPRIF_GCW_MAX_GROUP) { 14859 _SOC_EXIT_WITH_ERR 14860 (SOC_E_PARAM, ("GCW group index %d.\n",group_index)); 14861 } 14862 14863 reg_index = group_index / CPRIF_GCW_NUM_WORD_IN_STATUS ; 14864 14865 _SOC_IF_ERR_EXIT 14866 (soc_reg_get(unit, reg_select[reg_index], port, 0, ®_val)); 14867 14868 field_buf = soc_reg64_field_get(unit, reg_select[reg_index], reg_val, 14869 reg_field_select[group_index]); 14870 14871 /* Mask reading from CPRI_GCW_CFG_TAB_CFG memory*/ 14872 14873 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14874 port_core_index = ((phy_port-1)%4); 14875 14876 local_mem = mem_select[port_core_index]; 14877 14878 num_words = soc_mem_entry_words(unit, local_mem); 14879 rd_data_ptr = (uint32*)sal_alloc(sizeof(uint32) * num_words, ""); 14880 CPRIMOD_NULL_CHECK(rd_data_ptr); 14881 sal_memset(rd_data_ptr, 0, sizeof(uint32) * num_words); 14882 14883 blk_num = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14884 14885 _SOC_IF_ERR_EXIT 14886 (soc_mem_read(unit, local_mem, blk_num , group_index, rd_data_ptr)); 14887 14888 soc_mem_field_get(unit, local_mem, rd_data_ptr, GCW_MASKf, &field_buf32); 14889 mask = field_buf32; 14890 14891 *word = 0; 14892 *word = (mask & 1) ? *word | (COMPILER_64_LO(field_buf) & 0x00FF) : *word & 0xFF00; 14893 *word = (mask & 2) ? *word | (COMPILER_64_LO(field_buf) & 0xFF00) : *word & 0x00FF; 14894 14895 exit: 14896 SOC_FUNC_RETURN; 14897 } 14898 14899 int cprif_drv_tx_gcw_word_set(int unit, int port, int group_index, uint16 word) 14900 { 14901 int blk; 14902 int phy_port; 14903 int port_core_index; 14904 soc_mem_t local_mem; 14905 soc_mem_t mem_select[] = {CPRI_CWA_GCW_REGS_CFG_0m, 14906 CPRI_CWA_GCW_REGS_CFG_1m, 14907 CPRI_CWA_GCW_REGS_CFG_2m, 14908 CPRI_CWA_GCW_REGS_CFG_3m}; 14909 uint16 wr_data=0; 14910 SOC_INIT_FUNC_DEFS; 14911 14912 if (group_index >= CPRIF_GCW_MAX_GROUP) { 14913 _SOC_EXIT_WITH_ERR 14914 (SOC_E_PARAM, ("GCW group index %d.\n",group_index)); 14915 } 14916 14917 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 14918 port_core_index = ((phy_port-1)%4); 14919 14920 local_mem = mem_select[port_core_index]; 14921 14922 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 14923 14924 wr_data = word; 14925 14926 _SOC_IF_ERR_EXIT 14927 (soc_mem_write(unit, local_mem, blk, group_index, &wr_data)); 14928 14929 exit: 14930 SOC_FUNC_RETURN; 14931 } 14932 14933 14934 int cprif_drv_encap_header_field_mapping_set(int unit, int port, cprif_drv_encap_hdr_field_mapping_t *mapping) 14935 { 14936 uint64 reg_val; 14937 uint64 field_buf; 14938 cprif_pm_version_t pm_version; 14939 SOC_INIT_FUNC_DEFS; 14940 14941 _SOC_IF_ERR_EXIT 14942 (cprif_pm_version_get(unit, port, &pm_version)); 14943 14944 if (CPRIF_CLPORT_IS_B0(pm_version)){ 14945 _SOC_IF_ERR_EXIT 14946 (READ_CPRI_ENCAP_HDR_FLD_MAPPINGr(unit, port, ®_val)); 14947 14948 COMPILER_64_SET(field_buf,0, mapping->hdr_byte0_sel); 14949 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14950 HDR_BYTE0_SELf, field_buf); 14951 14952 COMPILER_64_SET(field_buf,0, mapping->hdr_byte1_sel); 14953 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14954 HDR_BYTE1_SELf, field_buf); 14955 14956 COMPILER_64_SET(field_buf,0, mapping->hdr_byte2_sel); 14957 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14958 HDR_BYTE2_SELf, field_buf); 14959 14960 COMPILER_64_SET(field_buf,0, mapping->hdr_byte3_sel); 14961 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14962 HDR_BYTE3_SELf, field_buf); 14963 14964 COMPILER_64_SET(field_buf,0, mapping->hdr_byte4_sel); 14965 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14966 HDR_BYTE4_SELf, field_buf); 14967 14968 COMPILER_64_SET(field_buf,0, mapping->hdr_byte5_sel); 14969 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14970 HDR_BYTE5_SELf, field_buf); 14971 14972 COMPILER_64_SET(field_buf,0, mapping->hdr_byte6_sel); 14973 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14974 HDR_BYTE6_SELf, field_buf); 14975 14976 COMPILER_64_SET(field_buf,0, mapping->hdr_byte7_sel); 14977 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14978 HDR_BYTE7_SELf, field_buf); 14979 14980 COMPILER_64_SET(field_buf,0, mapping->hdr_byte8_sel); 14981 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14982 HDR_BYTE8_SELf, field_buf); 14983 14984 COMPILER_64_SET(field_buf,0, mapping->hdr_byte9_sel); 14985 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14986 HDR_BYTE9_SELf, field_buf); 14987 14988 COMPILER_64_SET(field_buf,0, mapping->hdr_byte10_sel); 14989 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14990 HDR_BYTE10_SELf, field_buf); 14991 14992 COMPILER_64_SET(field_buf,0, mapping->hdr_byte11_sel); 14993 soc_reg64_field_set(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, ®_val, 14994 HDR_BYTE11_SELf, field_buf); 14995 14996 _SOC_IF_ERR_EXIT 14997 (WRITE_CPRI_ENCAP_HDR_FLD_MAPPINGr(unit, port, reg_val)); 14998 } else { 14999 _SOC_EXIT_WITH_ERR 15000 (SOC_E_UNAVAIL, ("CPRI_ENCAP_HDR_FLD_MAPPING is not support in this Version..\n")); 15001 } 15002 15003 exit: 15004 SOC_FUNC_RETURN; 15005 } 15006 15007 int cprif_drv_encap_header_field_mapping_get(int unit, int port, cprif_drv_encap_hdr_field_mapping_t *mapping) 15008 { 15009 uint64 reg_val; 15010 uint64 field_buf; 15011 cprif_pm_version_t pm_version; 15012 SOC_INIT_FUNC_DEFS; 15013 15014 _SOC_IF_ERR_EXIT 15015 (cprif_pm_version_get(unit, port, &pm_version)); 15016 15017 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15018 _SOC_IF_ERR_EXIT 15019 (READ_CPRI_ENCAP_HDR_FLD_MAPPINGr(unit, port, ®_val)); 15020 15021 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15022 HDR_BYTE0_SELf); 15023 mapping->hdr_byte0_sel = COMPILER_64_LO(field_buf); 15024 15025 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15026 HDR_BYTE1_SELf); 15027 mapping->hdr_byte1_sel = COMPILER_64_LO(field_buf); 15028 15029 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15030 HDR_BYTE2_SELf); 15031 mapping->hdr_byte2_sel = COMPILER_64_LO(field_buf); 15032 15033 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15034 HDR_BYTE3_SELf); 15035 mapping->hdr_byte3_sel = COMPILER_64_LO(field_buf); 15036 15037 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15038 HDR_BYTE4_SELf); 15039 mapping->hdr_byte4_sel = COMPILER_64_LO(field_buf); 15040 15041 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15042 HDR_BYTE5_SELf); 15043 mapping->hdr_byte5_sel = COMPILER_64_LO(field_buf); 15044 15045 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15046 HDR_BYTE6_SELf); 15047 mapping->hdr_byte6_sel = COMPILER_64_LO(field_buf); 15048 15049 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15050 HDR_BYTE7_SELf); 15051 mapping->hdr_byte7_sel = COMPILER_64_LO(field_buf); 15052 15053 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15054 HDR_BYTE8_SELf); 15055 mapping->hdr_byte8_sel = COMPILER_64_LO(field_buf); 15056 15057 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15058 HDR_BYTE9_SELf); 15059 mapping->hdr_byte9_sel = COMPILER_64_LO(field_buf); 15060 15061 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15062 HDR_BYTE10_SELf); 15063 mapping->hdr_byte10_sel = COMPILER_64_LO(field_buf); 15064 15065 field_buf = soc_reg64_field_get(unit, CPRI_ENCAP_HDR_FLD_MAPPINGr, reg_val, 15066 HDR_BYTE11_SELf); 15067 mapping->hdr_byte11_sel = COMPILER_64_LO(field_buf); 15068 15069 } else { 15070 _SOC_EXIT_WITH_ERR 15071 (SOC_E_UNAVAIL, ("CPRI_ENCAP_HDR_FLD_MAPPING is not support in this Version..\n")); 15072 } 15073 15074 exit: 15075 SOC_FUNC_RETURN; 15076 } 15077 int cprif_drv_decap_header_field_mapping_set(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mapping) 15078 { 15079 uint32 reg_val; 15080 cprif_pm_version_t pm_version; 15081 SOC_INIT_FUNC_DEFS; 15082 15083 _SOC_IF_ERR_EXIT 15084 (cprif_pm_version_get(unit, port, &pm_version)); 15085 15086 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15087 _SOC_IF_ERR_EXIT 15088 (READ_CPRI_DECAP_HDR_FLD_MAPPINGr(unit, port, ®_val)); 15089 15090 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, SUBTYPE_SELf, mapping->subtype); 15091 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, FLOWID_SELf, mapping->flowid); 15092 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, LENGTH_15_8_SELf, mapping->length_15_8); 15093 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, LENGTH_7_0_SELf, mapping->length_7_0); 15094 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, ORDERINGINFO_31_24_SELf, mapping->orderinginfo_31_24); 15095 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, ORDERINGINFO_23_16_SELf, mapping->orderinginfo_23_16); 15096 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, ORDERINGINFO_15_8_SELf, mapping->orderinginfo_15_8); 15097 soc_reg_field_set(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, ®_val, ORDERINGINFO_7_0_SELf, mapping->orderinginfo_7_0); 15098 15099 _SOC_IF_ERR_EXIT 15100 (WRITE_CPRI_DECAP_HDR_FLD_MAPPINGr(unit, port, reg_val)); 15101 } else { 15102 _SOC_EXIT_WITH_ERR 15103 (SOC_E_UNAVAIL, ("CPRI_DECAP_HDR_FLD_MAPPING is not support in this Version..\n")); 15104 } 15105 15106 exit: 15107 SOC_FUNC_RETURN; 15108 } 15109 15110 int cprif_drv_decap_header_field_mapping_get(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mapping) 15111 { 15112 uint32 reg_val; 15113 cprif_pm_version_t pm_version; 15114 SOC_INIT_FUNC_DEFS; 15115 15116 _SOC_IF_ERR_EXIT 15117 (cprif_pm_version_get(unit, port, &pm_version)); 15118 15119 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15120 _SOC_IF_ERR_EXIT 15121 (READ_CPRI_DECAP_HDR_FLD_MAPPINGr(unit, port, ®_val)); 15122 15123 mapping->subtype = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, SUBTYPE_SELf); 15124 mapping->flowid = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, FLOWID_SELf); 15125 mapping->length_15_8 = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, LENGTH_15_8_SELf); 15126 mapping->length_7_0 = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, LENGTH_7_0_SELf); 15127 mapping->orderinginfo_31_24 = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, ORDERINGINFO_31_24_SELf); 15128 mapping->orderinginfo_23_16 = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, ORDERINGINFO_23_16_SELf); 15129 mapping->orderinginfo_15_8 = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, ORDERINGINFO_15_8_SELf); 15130 mapping->orderinginfo_7_0 = soc_reg_field_get(unit, CPRI_DECAP_HDR_FLD_MAPPINGr, reg_val, ORDERINGINFO_7_0_SELf); 15131 15132 } else { 15133 _SOC_EXIT_WITH_ERR 15134 (SOC_E_UNAVAIL, ("CPRI_DECAP_HDR_FLD_MAPPING is not support in this Version..\n")); 15135 } 15136 15137 exit: 15138 SOC_FUNC_RETURN; 15139 } 15140 15141 15142 int cprif_drv_decap_header_field_mask_set(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mask) 15143 { 15144 uint64 reg_val; 15145 uint64 field_buf; 15146 cprif_pm_version_t pm_version; 15147 SOC_INIT_FUNC_DEFS; 15148 15149 _SOC_IF_ERR_EXIT 15150 (cprif_pm_version_get(unit, port, &pm_version)); 15151 15152 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15153 _SOC_IF_ERR_EXIT 15154 (READ_CPRI_DECAP_HDR_FLD_MASKINGr(unit, port, ®_val)); 15155 15156 COMPILER_64_SET(field_buf,0, mask->subtype); 15157 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15158 SUBTYPE_MASKf, field_buf); 15159 15160 COMPILER_64_SET(field_buf,0, mask->flowid); 15161 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15162 FLOWID_MASKf, field_buf); 15163 15164 COMPILER_64_SET(field_buf,0, mask->length_15_8); 15165 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15166 LENGTH_15_8_MASKf, field_buf); 15167 15168 COMPILER_64_SET(field_buf,0, mask->length_7_0); 15169 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15170 LENGTH_7_0_MASKf, field_buf); 15171 15172 COMPILER_64_SET(field_buf,0, mask->orderinginfo_31_24); 15173 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15174 ORDERINGINFO_31_24_MASKf, field_buf); 15175 15176 COMPILER_64_SET(field_buf,0, mask->orderinginfo_23_16); 15177 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15178 ORDERINGINFO_23_16_MASKf, field_buf); 15179 15180 COMPILER_64_SET(field_buf,0, mask->orderinginfo_15_8); 15181 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15182 ORDERINGINFO_15_8_MASKf, field_buf); 15183 15184 COMPILER_64_SET(field_buf,0, mask->orderinginfo_7_0); 15185 soc_reg64_field_set(unit, CPRI_DECAP_HDR_FLD_MASKINGr, ®_val, 15186 ORDERINGINFO_7_0_MASKf, field_buf); 15187 15188 15189 _SOC_IF_ERR_EXIT 15190 (WRITE_CPRI_DECAP_HDR_FLD_MASKINGr(unit, port, reg_val)); 15191 } else { 15192 _SOC_EXIT_WITH_ERR 15193 (SOC_E_UNAVAIL, ("CPRI_DECAP_HDR_FLD_MASKING is not support in this Version..\n")); 15194 } 15195 15196 exit: 15197 SOC_FUNC_RETURN; 15198 } 15199 15200 int cprif_drv_decap_header_field_mask_get(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mask) 15201 { 15202 uint64 reg_val; 15203 uint64 field_buf; 15204 cprif_pm_version_t pm_version; 15205 SOC_INIT_FUNC_DEFS; 15206 15207 _SOC_IF_ERR_EXIT 15208 (cprif_pm_version_get(unit, port, &pm_version)); 15209 15210 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15211 _SOC_IF_ERR_EXIT 15212 (READ_CPRI_DECAP_HDR_FLD_MASKINGr(unit, port, ®_val)); 15213 15214 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15215 SUBTYPE_MASKf); 15216 mask->subtype = COMPILER_64_LO(field_buf); 15217 15218 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15219 FLOWID_MASKf); 15220 mask->flowid = COMPILER_64_LO(field_buf); 15221 15222 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15223 LENGTH_15_8_MASKf); 15224 mask->length_15_8 = COMPILER_64_LO(field_buf); 15225 15226 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15227 LENGTH_7_0_MASKf); 15228 mask->length_7_0 = COMPILER_64_LO(field_buf); 15229 15230 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15231 ORDERINGINFO_31_24_MASKf); 15232 mask->orderinginfo_31_24 = COMPILER_64_LO(field_buf); 15233 15234 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15235 ORDERINGINFO_23_16_MASKf); 15236 mask->orderinginfo_23_16 = COMPILER_64_LO(field_buf); 15237 15238 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15239 ORDERINGINFO_15_8_MASKf); 15240 mask->orderinginfo_15_8 = COMPILER_64_LO(field_buf); 15241 15242 field_buf = soc_reg64_field_get(unit, CPRI_DECAP_HDR_FLD_MASKINGr, reg_val, 15243 ORDERINGINFO_7_0_MASKf); 15244 mask->orderinginfo_7_0 = COMPILER_64_LO(field_buf); 15245 } else { 15246 _SOC_EXIT_WITH_ERR 15247 (SOC_E_PARAM, ("CPRI_DECAP_HDR_FLD_MASKING is not support in this Version..\n")); 15248 } 15249 15250 exit: 15251 SOC_FUNC_RETURN; 15252 } 15253 15254 /* any negative value above the threshold will be set to -256 */ 15255 int cprif_drv_compression_negative_saturation_threshold_set( int unit, int port, uint32 threshold_value ) 15256 { 15257 uint32 reg_val; 15258 cprif_pm_version_t pm_version; 15259 SOC_INIT_FUNC_DEFS; 15260 15261 _SOC_IF_ERR_EXIT 15262 (cprif_pm_version_get(unit, port, &pm_version)); 15263 15264 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15265 15266 /* 15267 * Check for value over 14 bits. 15268 */ 15269 if ((threshold_value & ~0x3FFF) != 0) { 15270 _SOC_EXIT_WITH_ERR 15271 (SOC_E_PARAM, (" The threshold_value cannot exceed 14 bit value.\n")); 15272 } 15273 15274 15275 _SOC_IF_ERR_EXIT 15276 (READ_CPRI_DECAP_COMP_NEG_SAT_CTRLr(unit, port, ®_val)); 15277 15278 soc_reg_field_set(unit, CPRI_DECAP_COMP_NEG_SAT_CTRLr, ®_val, COMP_NEG_SATf, threshold_value); 15279 15280 _SOC_IF_ERR_EXIT 15281 (WRITE_CPRI_DECAP_COMP_NEG_SAT_CTRLr(unit, port, reg_val)); 15282 } else { 15283 _SOC_EXIT_WITH_ERR 15284 (SOC_E_PARAM, ("CPRI_DECAP_COMP_NEG_SAT_CTRL is not support in this Version..\n")); 15285 } 15286 15287 exit: 15288 SOC_FUNC_RETURN; 15289 } 15290 15291 int cprif_drv_compression_negative_saturation_threshold_get( int unit, int port, uint32* threshold_value ) 15292 { 15293 uint32 reg_val; 15294 cprif_pm_version_t pm_version; 15295 SOC_INIT_FUNC_DEFS; 15296 15297 _SOC_IF_ERR_EXIT 15298 (cprif_pm_version_get(unit, port, &pm_version)); 15299 15300 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15301 _SOC_IF_ERR_EXIT 15302 (READ_CPRI_DECAP_COMP_NEG_SAT_CTRLr(unit, port, ®_val)); 15303 15304 *threshold_value = soc_reg_field_get(unit, CPRI_DECAP_COMP_NEG_SAT_CTRLr, reg_val, COMP_NEG_SATf); 15305 15306 } else { 15307 _SOC_EXIT_WITH_ERR 15308 (SOC_E_PARAM, ("CPRI_DECAP_COMP_NEG_SAT_CTRL is not support in this Version..\n")); 15309 } 15310 15311 exit: 15312 SOC_FUNC_RETURN; 15313 } 15314 15315 /* -256 will force to this value. */ 15316 int cprif_drv_decompression_negative_saturation_value_set( int unit, int port, uint32 sat_value) 15317 { 15318 uint32 reg_val; 15319 cprif_pm_version_t pm_version; 15320 SOC_INIT_FUNC_DEFS; 15321 15322 _SOC_IF_ERR_EXIT 15323 (cprif_pm_version_get(unit, port, &pm_version)); 15324 15325 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15326 /* 15327 * Check for value over 15 bits. 15328 */ 15329 if ((sat_value & ~0x7FFF) != 0) { 15330 _SOC_EXIT_WITH_ERR 15331 (SOC_E_PARAM, (" The saturation value cannot exceed 15 bit value.\n")); 15332 } 15333 15334 _SOC_IF_ERR_EXIT 15335 (READ_CPRI_DECAP_DCOMP_NEG_SAT_CTRLr(unit, port, ®_val)); 15336 15337 soc_reg_field_set(unit, CPRI_DECAP_DCOMP_NEG_SAT_CTRLr, ®_val, DCOMP_NEG_SATf, sat_value); 15338 15339 _SOC_IF_ERR_EXIT 15340 (WRITE_CPRI_DECAP_DCOMP_NEG_SAT_CTRLr(unit, port, reg_val)); 15341 } else { 15342 _SOC_EXIT_WITH_ERR 15343 (SOC_E_PARAM, ("CPRI_DECAP_DCOMP_NEG_SAT_CTRL is not support in this Version..\n")); 15344 } 15345 15346 exit: 15347 SOC_FUNC_RETURN; 15348 } 15349 15350 int cprif_drv_decompression_negative_saturation_value_get( int unit, int port, uint32* sat_value) 15351 { 15352 uint32 reg_val; 15353 cprif_pm_version_t pm_version; 15354 SOC_INIT_FUNC_DEFS; 15355 15356 _SOC_IF_ERR_EXIT 15357 (cprif_pm_version_get(unit, port, &pm_version)); 15358 15359 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15360 _SOC_IF_ERR_EXIT 15361 (READ_CPRI_DECAP_DCOMP_NEG_SAT_CTRLr(unit, port, ®_val)); 15362 15363 *sat_value = soc_reg_field_get(unit, CPRI_DECAP_DCOMP_NEG_SAT_CTRLr, reg_val, DCOMP_NEG_SATf); 15364 15365 } else { 15366 _SOC_EXIT_WITH_ERR 15367 (SOC_E_PARAM, ("CPRI_DECAP_DCOMP_NEG_SAT_CTRL is not support in this Version..\n")); 15368 } 15369 15370 exit: 15371 SOC_FUNC_RETURN; 15372 } 15373 15374 15375 int cprif_drv_ingress_traffic_rate_set(int unit, int port, uint32 rate) 15376 { 15377 uint32 reg_val; 15378 cprif_pm_version_t pm_version; 15379 SOC_INIT_FUNC_DEFS; 15380 15381 _SOC_IF_ERR_EXIT 15382 (cprif_pm_version_get(unit, port, &pm_version)); 15383 15384 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15385 _SOC_IF_ERR_EXIT 15386 (READ_CPMPORT_TOP_LANE_CTRLr(unit, port, ®_val)); 15387 15388 soc_reg_field_set(unit, CPMPORT_TOP_LANE_CTRLr, ®_val, INGRESS_RATEf, rate); 15389 15390 _SOC_IF_ERR_EXIT 15391 (WRITE_CPMPORT_TOP_LANE_CTRLr(unit, port, reg_val)); 15392 } 15393 15394 exit: 15395 SOC_FUNC_RETURN; 15396 } 15397 15398 int cprif_drv_ingress_traffic_rate_get(int unit, int port, uint32* rate) 15399 { 15400 uint32 reg_val; 15401 cprif_pm_version_t pm_version; 15402 SOC_INIT_FUNC_DEFS; 15403 15404 _SOC_IF_ERR_EXIT 15405 (cprif_pm_version_get(unit, port, &pm_version)); 15406 15407 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15408 _SOC_IF_ERR_EXIT 15409 (READ_CPMPORT_TOP_LANE_CTRLr(unit, port, ®_val)); 15410 15411 *rate = soc_reg_field_get(unit, CPMPORT_TOP_LANE_CTRLr, reg_val, INGRESS_RATEf); 15412 15413 } else { 15414 _SOC_EXIT_WITH_ERR 15415 (SOC_E_PARAM, ("CPMPORT_TOP_LANE_CTRL INGRESS_RATE is not support in this Version..\n")); 15416 } 15417 15418 exit: 15419 SOC_FUNC_RETURN; 15420 } 15421 15422 int cprif_drv_extended_header_enable_set (int unit, int port, cprimod_direction_t dir, int enable) 15423 { 15424 uint32 reg_val; 15425 cprif_pm_version_t pm_version; 15426 SOC_INIT_FUNC_DEFS; 15427 15428 _SOC_IF_ERR_EXIT 15429 (cprif_pm_version_get(unit, port, &pm_version)); 15430 15431 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15432 15433 if (dir == CPRIMOD_DIR_RX) { 15434 _SOC_IF_ERR_EXIT 15435 (READ_CPRI_ENCAP_EXD_HDR_CTRLr(unit, port, ®_val)); 15436 15437 soc_reg_field_set(unit, CPRI_ENCAP_EXD_HDR_CTRLr, ®_val, EXTENDED_HDR_ENf, enable?1:0); 15438 15439 _SOC_IF_ERR_EXIT 15440 (WRITE_CPRI_ENCAP_EXD_HDR_CTRLr(unit, port, reg_val)); 15441 } else { 15442 _SOC_IF_ERR_EXIT 15443 (READ_CPRI_DECAP_EXD_HDR_CTRLr(unit, port, ®_val)); 15444 15445 soc_reg_field_set(unit, CPRI_ENCAP_EXD_HDR_CTRLr, ®_val, EXTENDED_HDR_ENf, enable?1:0); 15446 15447 _SOC_IF_ERR_EXIT 15448 (WRITE_CPRI_DECAP_EXD_HDR_CTRLr(unit, port, reg_val)); 15449 } 15450 } else { 15451 _SOC_EXIT_WITH_ERR 15452 (SOC_E_PARAM, ("EXTENDED HEADER is not support in this Version..\n")); 15453 } 15454 15455 exit: 15456 SOC_FUNC_RETURN; 15457 } 15458 15459 int cprif_drv_extended_header_enable_get (int unit, int port, cprimod_direction_t dir, int* enable) 15460 { 15461 uint32 reg_val; 15462 cprif_pm_version_t pm_version; 15463 SOC_INIT_FUNC_DEFS; 15464 15465 _SOC_IF_ERR_EXIT 15466 (cprif_pm_version_get(unit, port, &pm_version)); 15467 15468 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15469 15470 if (dir == CPRIMOD_DIR_RX) { 15471 _SOC_IF_ERR_EXIT 15472 (READ_CPRI_ENCAP_EXD_HDR_CTRLr(unit, port, ®_val)); 15473 15474 *enable = soc_reg_field_get(unit, CPRI_ENCAP_EXD_HDR_CTRLr, reg_val, EXTENDED_HDR_ENf); 15475 15476 } else { 15477 _SOC_IF_ERR_EXIT 15478 (READ_CPRI_DECAP_EXD_HDR_CTRLr(unit, port, ®_val)); 15479 15480 *enable = soc_reg_field_get(unit, CPRI_DECAP_EXD_HDR_CTRLr, reg_val, EXTENDED_HDR_ENf); 15481 } 15482 } else { 15483 _SOC_EXIT_WITH_ERR 15484 (SOC_E_PARAM, ("EXTENDED HEADER is not support in this Version..\n")); 15485 } 15486 15487 exit: 15488 SOC_FUNC_RETURN; 15489 } 15490 15491 /* 15492 * adjust 8 bits signed to 5 bits signed. 15493 */ 15494 uint32 _convert_int_to_cprif_drv_adjust_value (int adjust_value) { 15495 15496 uint32 value=0; 15497 15498 /* 15499 * saturate the value to its max. 15500 */ 15501 if ((adjust_value < CPRIF_LEN_ADJUST_NEG_MAX) || 15502 (adjust_value > CPRIF_LEN_ADJUST_POS_MAX)) { 15503 if (adjust_value < 0) { 15504 adjust_value = CPRIF_LEN_ADJUST_NEG_MAX; 15505 } else { 15506 adjust_value = CPRIF_LEN_ADJUST_POS_MAX; 15507 } 15508 } 15509 15510 /* removed signed and extra bits. */ 15511 value = adjust_value & 0x0F; 15512 15513 if ( adjust_value < 0) { 15514 value |= CPRIF_LEN_ADJUST_SIGNED_BIT; 15515 } 15516 return value; 15517 } 15518 15519 int _convert_cprif_drv_to_int_adjust_value (uint32 value) { 15520 15521 int adjust_value = 0; 15522 15523 /* get value */ 15524 adjust_value = value & CPRIF_LEN_ADJUST_VALUE_BITS; 15525 15526 if (value & CPRIF_LEN_ADJUST_SIGNED_BIT) { 15527 /* negative # */ 15528 adjust_value = adjust_value * (-1); 15529 } 15530 15531 return adjust_value; 15532 } 15533 15534 15535 int cprif_drv_length_field_adjustment_set (int unit, int port, cprimod_direction_t dir, int adjust_value) 15536 { 15537 uint32 reg_val; 15538 uint32 field_value=0; 15539 cprif_pm_version_t pm_version; 15540 SOC_INIT_FUNC_DEFS; 15541 15542 _SOC_IF_ERR_EXIT 15543 (cprif_pm_version_get(unit, port, &pm_version)); 15544 15545 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15546 15547 field_value = _convert_int_to_cprif_drv_adjust_value(adjust_value); 15548 15549 if (dir == CPRIMOD_DIR_RX) { 15550 _SOC_IF_ERR_EXIT 15551 (READ_CPRI_ENCAP_LEN_FLD_ADJr(unit, port, ®_val)); 15552 15553 soc_reg_field_set(unit, CPRI_ENCAP_LEN_FLD_ADJr, ®_val, LENGTH_ADJ_VALUEf, field_value); 15554 15555 _SOC_IF_ERR_EXIT 15556 (WRITE_CPRI_ENCAP_LEN_FLD_ADJr(unit, port, reg_val)); 15557 } else { 15558 _SOC_IF_ERR_EXIT 15559 (READ_CPRI_DECAP_LEN_FLD_ADJr(unit, port, ®_val)); 15560 15561 soc_reg_field_set(unit, CPRI_DECAP_LEN_FLD_ADJr, ®_val, LENGTH_ADJ_VALUEf, field_value); 15562 15563 _SOC_IF_ERR_EXIT 15564 (WRITE_CPRI_DECAP_LEN_FLD_ADJr(unit, port, reg_val)); 15565 } 15566 } else { 15567 _SOC_EXIT_WITH_ERR 15568 (SOC_E_PARAM, ("EXTENDED HEADER is not support in this Version..\n")); 15569 } 15570 15571 exit: 15572 SOC_FUNC_RETURN; 15573 } 15574 15575 int cprif_drv_length_field_adjustment_get (int unit, int port, cprimod_direction_t dir, int* adjust_value) 15576 { 15577 uint32 reg_val; 15578 uint32 field_value=0; 15579 cprif_pm_version_t pm_version; 15580 SOC_INIT_FUNC_DEFS; 15581 15582 _SOC_IF_ERR_EXIT 15583 (cprif_pm_version_get(unit, port, &pm_version)); 15584 15585 if (CPRIF_CLPORT_IS_B0(pm_version)){ 15586 15587 if (dir == CPRIMOD_DIR_RX) { 15588 _SOC_IF_ERR_EXIT 15589 (READ_CPRI_ENCAP_LEN_FLD_ADJr(unit, port, ®_val)); 15590 15591 field_value = soc_reg_field_get(unit, CPRI_ENCAP_LEN_FLD_ADJr, reg_val, LENGTH_ADJ_VALUEf); 15592 } else { 15593 _SOC_IF_ERR_EXIT 15594 (READ_CPRI_DECAP_LEN_FLD_ADJr(unit, port, ®_val)); 15595 15596 field_value = soc_reg_field_get(unit, CPRI_DECAP_LEN_FLD_ADJr, reg_val, LENGTH_ADJ_VALUEf); 15597 } 15598 15599 field_value = _convert_cprif_drv_to_int_adjust_value(field_value); 15600 } else { 15601 _SOC_EXIT_WITH_ERR 15602 (SOC_E_PARAM, ("EXTENDED HEADER is not support in this Version..\n")); 15603 } 15604 exit: 15605 SOC_FUNC_RETURN; 15606 } 15607 15608 int cprif_drv_rsvd4_tx_padding_size_set (int unit, int port, uint32 padding_size) 15609 { 15610 uint64 reg_val; 15611 uint64 field_buf; 15612 SOC_INIT_FUNC_DEFS; 15613 15614 _SOC_IF_ERR_EXIT 15615 (READ_BRCM_RESERVED_CPM_3r(unit, port, ®_val)); 15616 15617 COMPILER_64_SET(field_buf, 0, padding_size); 15618 soc_reg64_field_set(unit, BRCM_RESERVED_CPM_3r, ®_val, 15619 BRCM_RESERVED_CPM_3_1f, field_buf); 15620 15621 _SOC_IF_ERR_EXIT 15622 (WRITE_BRCM_RESERVED_CPM_3r(unit, port, reg_val)); 15623 15624 exit: 15625 SOC_FUNC_RETURN; 15626 } 15627 15628 int cprif_drv_rsvd4_tx_padding_size_get (int unit, int port, uint32* padding_size) 15629 { 15630 uint64 reg_val; 15631 uint64 field_buf; 15632 SOC_INIT_FUNC_DEFS; 15633 15634 _SOC_IF_ERR_EXIT 15635 (READ_BRCM_RESERVED_CPM_3r(unit, port, ®_val)); 15636 15637 field_buf = soc_reg64_field_get(unit, BRCM_RESERVED_CPM_3r, reg_val, 15638 BRCM_RESERVED_CPM_3_1f); 15639 *padding_size = COMPILER_64_LO(field_buf); 15640 15641 exit: 15642 SOC_FUNC_RETURN; 15643 } 15644 15645 int cprif_drv_cpri_work_queue_interrupt_status_clear (int unit, int port) 15646 { 15647 uint32 reg_val; 15648 SOC_INIT_FUNC_DEFS; 15649 15650 _SOC_IF_ERR_EXIT 15651 (READ_CPRI_ENCAP_MISC_FIFO_INTR_STATUSr(unit, port, ®_val)); 15652 /* Write 1 will clear the fields. */ 15653 soc_reg_field_set(unit, CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, ®_val, 15654 ENCAP_WQ_FIFO_FAULT_INTERRUPT_STATUS_0f,1); 15655 soc_reg_field_set(unit, CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, ®_val, 15656 ENCAP_WQ_FIFO_FAULT_INTERRUPT_STATUS_1f,1); 15657 soc_reg_field_set(unit, CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, ®_val, 15658 ENCAP_WQ_FIFO_FAULT_INTERRUPT_STATUS_2f,1); 15659 soc_reg_field_set(unit, CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, ®_val, 15660 ENCAP_WQ_FIFO_FAULT_INTERRUPT_STATUS_3f,1); 15661 soc_reg_field_set(unit, CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, ®_val, 15662 ENCAP_WQ_FIFO_FAULT_INTERRUPT_STATUS_0f,1); 15663 soc_reg_field_set(unit, CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, ®_val, 15664 ENCAP_WQ_FIFO_FAULT_INTERRUPT_STATUS_0f,1); 15665 _SOC_IF_ERR_EXIT 15666 (WRITE_CPRI_ENCAP_MISC_FIFO_INTR_STATUSr(unit, port, reg_val)); 15667 15668 exit: 15669 SOC_FUNC_RETURN; 15670 } 15671 15672 int cprif_drv_cpri_byte_error_count_clear (int unit, int port) 15673 { 15674 uint32 reg_val; 15675 SOC_INIT_FUNC_DEFS; 15676 15677 /* reading of the register itself will clear the counter.. */ 15678 _SOC_IF_ERR_EXIT 15679 (READ_CPRI_RX_STATS_CNTR_0_STATUSr(unit, port, ®_val)); 15680 exit: 15681 SOC_FUNC_RETURN; 15682 } 15683 15684 15685 #ifdef CPRIMOD_SUPPORT_ECC_INJECT 15686 int cprif_drv_cpri_port_ecc_interrupt_test(int unit, int port) 15687 { 15688 uint32 rval = 0; 15689 uint64 rval64 = 0; 15690 uint32 err_addr = 0x0; 15691 uint32 is_64 = 0; 15692 uint32 ecc_ctrl_inc = 0; 15693 uint32 ecc_err_type = 0; 15694 uint32 entry[SOC_MAX_MEM_WORDS]; 15695 int ecc1b_err = 0; 15696 int ecc2b_err = 0; 15697 int ecc_multib_err = 0; 15698 int cnt = 0; 15699 int min_idx = 0, max_idx = 0, use_idx = 0; 15700 int blk, phy_port; 15701 int cpri_mem_cnt = 0; 15702 int idx = 0; 15703 int intr_info_idx = 0; 15704 soc_mem_t *cpri_mem_list_ptr = NULL; 15705 soc_mem_t mem; 15706 _cpri_ecc_interrupts_info_t *intr_ptr = &_cpri_port_ecc_intrs_info[0]; 15707 _cpri_ecc_inject_ctrl_t *ecc_ctrl = &_cpri_ecc_err_ctrl_info[0]; 15708 SOC_INIT_FUNC_DEFS; 15709 15710 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 15711 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 15712 15713 /* Get the count of CPRI memories */ 15714 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 15715 if (!soc_mem_is_valid(unit, mem) || 15716 !(SOC_BLOCK_TYPE(unit, SOC_MEM_BLOCK_ANY(unit, mem)) == 15717 SOC_BLK_CPRI)) { 15718 continue; 15719 } 15720 cpri_mem_cnt++; 15721 } 15722 15723 LOG_VERBOSE(BSL_LS_BCM_PORT, 15724 (BSL_META_U(unit, "Cpri Memories count - %d\n"), cpri_mem_cnt)); 15725 15726 cpri_mem_list_ptr = (soc_mem_t *)sal_alloc(sizeof(soc_mem_t) * cpri_mem_cnt, 15727 "cpri_mem_list"); 15728 15729 if (!cpri_mem_list_ptr) { 15730 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Failed to allocate memory\n")); 15731 } 15732 15733 /* Populate the array with CPRI related memories */ 15734 for (mem = 0; mem <= NUM_SOC_MEM; mem++) { 15735 if (!soc_mem_is_valid(unit, mem) || 15736 !(SOC_BLOCK_TYPE(unit, SOC_MEM_BLOCK_ANY(unit, mem)) == 15737 SOC_BLK_CPRI)) { 15738 continue; 15739 } 15740 cpri_mem_list_ptr[idx++] = mem; 15741 } 15742 15743 /* index to cpri memory */ 15744 idx = 0; 15745 15746 while (ecc_ctrl->en_r != INVALIDr) { 15747 15748 /* Check if register is 64-bit to call 64-bit reg operations */ 15749 is_64 = 0; 15750 if (SOC_REG_IS_64(unit, ecc_ctrl->en_r)) { 15751 is_64 = 1; 15752 } 15753 15754 /* 15755 * Enable Inject 1-bit ecc error and then 2-bits ecc error 15756 * on read. 15757 * Select an index in the memory and perform a read, to trigger 15758 * and ECC error. Check the ECC interrupt status and report. 15759 */ 15760 for (ecc_err_type = _cpriEccInject1bErrOnRead; 15761 ecc_err_type < _cpriEccInjectCount; 15762 ecc_err_type++) 15763 { 15764 if (is_64) { 15765 _SOC_IF_ERR_EXIT(soc_reg64_get(unit, ecc_ctrl->en_r, 15766 port, 0, &rval64)); 15767 15768 /* Inject ECC error */ 15769 if (ecc_ctrl->en_f != INVALIDf) { 15770 soc_reg64_field32_set(unit, ecc_ctrl->en_r, &rval64, 15771 ecc_ctrl->en_f, ecc_err_type); 15772 } 15773 15774 _SOC_IF_ERR_EXIT(soc_reg64_set(unit, ecc_ctrl->en_r, 15775 port, 0, rval64)); 15776 } else { 15777 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, ecc_ctrl->en_r, 15778 port, 0, &rval)); 15779 15780 /* Inject ECC error */ 15781 if (ecc_ctrl->en_f != INVALIDf) { 15782 soc_reg_field_set(unit, ecc_ctrl->en_r, &rval, 15783 ecc_ctrl->en_f, ecc_err_type); 15784 } 15785 15786 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, ecc_ctrl->en_r, 15787 port, 0, rval)); 15788 } 15789 15790 15791 /* 15792 * Perform a memory read on each Mem and 15793 * check the ECC intr status 15794 */ 15795 for (idx = 0; idx < cpri_mem_cnt; idx++) { 15796 15797 mem = cpri_mem_list_ptr[idx]; 15798 min_idx = soc_mem_index_min(unit, mem); 15799 max_idx = soc_mem_index_max(unit, mem); 15800 use_idx = (max_idx - min_idx)/2; 15801 15802 _SOC_IF_ERR_EXIT(soc_mem_read(unit, mem, blk, use_idx, entry)); 15803 15804 cnt = 0; 15805 intr_info_idx = 0; 15806 intr_ptr = &_cpri_port_ecc_intrs_info[intr_info_idx]; 15807 while (intr_ptr->ecc_status_reg != INVALIDr) { 15808 15809 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, 15810 intr_ptr->ecc_status_reg, 15811 port, 0, &rval)); 15812 15813 /* Check if 1-bit ECC error */ 15814 if (intr_ptr->ecc1b_err_status_fld != INVALIDf) { 15815 ecc1b_err = soc_reg_field_get(unit, 15816 intr_ptr->ecc_status_reg, 15817 rval, intr_ptr->ecc1b_err_status_fld); 15818 } 15819 15820 /* Check if 2-bit ECC error */ 15821 if (intr_ptr->ecc2b_err_status_fld != INVALIDf) { 15822 ecc2b_err = soc_reg_field_get(unit, 15823 intr_ptr->ecc_status_reg, 15824 rval, intr_ptr->ecc2b_err_status_fld); 15825 } 15826 15827 /* Check if multi-bit ECC error */ 15828 if (intr_ptr->ecc_multib_err_status_fld != INVALIDf) { 15829 ecc_multib_err = soc_reg_field_get(unit, 15830 intr_ptr->ecc_status_reg, rval, 15831 intr_ptr->ecc_multib_err_status_fld); 15832 } 15833 15834 /* Get the address */ 15835 if (ecc1b_err || ecc2b_err || ecc_multib_err) { 15836 err_addr = soc_reg_field_get(unit, 15837 intr_ptr->ecc_status_reg, 15838 rval, intr_ptr->ecc_event_addr); 15839 15840 cnt++; 15841 } 15842 15843 /* Clear error if 1-bit ECC error */ 15844 if (ecc1b_err) { 15845 soc_reg_field_set(unit, intr_ptr->ecc_status_reg, &rval, 15846 intr_ptr->ecc1b_err_status_fld, 1); 15847 } 15848 15849 /* Clear error if 2-bit ECC error */ 15850 if (ecc2b_err) { 15851 soc_reg_field_set(unit, intr_ptr->ecc_status_reg, &rval, 15852 intr_ptr->ecc2b_err_status_fld, 1); 15853 } 15854 15855 /* Clear error if multi-bit ECC error */ 15856 if (ecc_multib_err) { 15857 soc_reg_field_set(unit, intr_ptr->ecc_status_reg, &rval, 15858 intr_ptr->ecc_multib_err_status_fld, 1); 15859 } 15860 15861 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, 15862 intr_ptr->ecc_status_reg, 15863 port, 0, rval)); 15864 15865 intr_info_idx++; 15866 15867 if (ecc1b_err || ecc2b_err || ecc_multib_err) { 15868 LOG_VERBOSE(BSL_LS_BCM_PORT, 15869 (BSL_META_U(unit, 15870 "r - %s\nf - %s\nr - %s\nm(%s) - %s\n\r\n"), 15871 SOC_REG_NAME(unit, ecc_ctrl->en_r), 15872 SOC_FIELD_NAME(unit, ecc_ctrl->en_f), 15873 SOC_REG_NAME(unit, intr_ptr->ecc_status_reg), 15874 ecc1b_err? "1-bit": ecc2b_err? "2-bit": "m-bit", 15875 SOC_MEM_NAME(unit, mem))); 15876 15877 LOG_VERBOSE(BSL_LS_BCM_PORT, 15878 (BSL_META_U(unit, 15879 "[i-%d] [1b-%d] [2b-%d] [mb-%d] [addr-%x]\n\n"), 15880 intr_info_idx, ecc1b_err, ecc2b_err, 15881 ecc_multib_err, err_addr)); 15882 } 15883 intr_ptr = &_cpri_port_ecc_intrs_info[intr_info_idx]; 15884 } 15885 15886 } 15887 15888 if (is_64) { 15889 _SOC_IF_ERR_EXIT(soc_reg64_get(unit, ecc_ctrl->en_r, 15890 port, 0, &rval64)); 15891 15892 /* Set Inject ECC error to NONE */ 15893 if (ecc_ctrl->en_f != INVALIDf) { 15894 soc_reg64_field32_set(unit, ecc_ctrl->en_r, &rval64, 15895 ecc_ctrl->en_f, _cpriEccInjectnoErr); 15896 } 15897 15898 _SOC_IF_ERR_EXIT(soc_reg64_set(unit, ecc_ctrl->en_r, 15899 port, 0, rval64)); 15900 } else { 15901 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, ecc_ctrl->en_r, 15902 port, 0, &rval)); 15903 15904 /* Set Inject ECC error to NONE */ 15905 if (ecc_ctrl->en_f != INVALIDf) { 15906 soc_reg_field_set(unit, ecc_ctrl->en_r, &rval, 15907 ecc_ctrl->en_f, _cpriEccInjectnoErr); 15908 } 15909 15910 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, ecc_ctrl->en_r, 15911 port, 0, rval)); 15912 } 15913 15914 is_64 = 0; 15915 if (SOC_REG_IS_64(unit, ecc_ctrl->dis_r)){ 15916 is_64 = 1; 15917 } 15918 15919 if (is_64) { 15920 _SOC_IF_ERR_EXIT(soc_reg64_get(unit, ecc_ctrl->dis_r, 15921 port, 0, &rval64)); 15922 15923 /* Disable - Inject ECC error */ 15924 if (ecc_ctrl->dis_f != INVALIDf) { 15925 soc_reg64_field32_set(unit, ecc_ctrl->dis_r, &rval64, 15926 ecc_ctrl->dis_f, 1); 15927 } 15928 15929 _SOC_IF_ERR_EXIT(soc_reg64_set(unit, ecc_ctrl->dis_r, 15930 port, 0, rval64)); 15931 15932 /* Disable - Inject ECC error */ 15933 if (ecc_ctrl->dis_f != INVALIDf) { 15934 soc_reg64_field32_set(unit, ecc_ctrl->dis_r, &rval64, 15935 ecc_ctrl->dis_f, 0); 15936 } 15937 15938 _SOC_IF_ERR_EXIT(soc_reg64_set(unit, ecc_ctrl->dis_r, 15939 port, 0, rval64)); 15940 } else { 15941 _SOC_IF_ERR_EXIT(soc_reg32_get(unit, ecc_ctrl->dis_r, 15942 port, 0, &rval)); 15943 15944 /* Disable - Inject ECC error */ 15945 if (ecc_ctrl->dis_f != INVALIDf) { 15946 soc_reg_field_set(unit, ecc_ctrl->dis_r, &rval, 15947 ecc_ctrl->dis_f, 1); 15948 } 15949 15950 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, ecc_ctrl->dis_r, 15951 port, 0, rval)); 15952 15953 /* Disable - Inject ECC error */ 15954 if (ecc_ctrl->dis_f != INVALIDf) { 15955 soc_reg_field_set(unit, ecc_ctrl->dis_r, &rval, 15956 ecc_ctrl->dis_f, 0); 15957 } 15958 15959 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, ecc_ctrl->dis_r, 15960 port, 0, rval)); 15961 } 15962 } 15963 ecc_ctrl_inc++; 15964 ecc_ctrl = &_cpri_ecc_err_ctrl_info[ecc_ctrl_inc]; 15965 } 15966 15967 exit: 15968 if (cpri_mem_list_ptr) { 15969 sal_free(cpri_mem_list_ptr); 15970 } 15971 SOC_FUNC_RETURN; 15972 15973 } 15974 #endif /* CPRIMOD_SUPPORT_ECC_INJECT */ 15975 15976 #endif /* CPRIMOD_CPRI_FALCON_SUPPORT */ 15977 15978 #undef _ERR_MSG_MODULE_NAME