cprif.c (322231B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <shared/bsl.h> 12 #include <soc/error.h> 13 #include <soc/esw/port.h> 14 #include <soc/cprimod/cprimod.h> 15 #include <soc/cprimod/cprimod_internal.h> 16 #include <soc/cprimod/cprimod_dispatch.h> 17 #include <soc/cprimod/cprif_drv.h> 18 #include "../../../../libs/phymod/chip/falcon_dpll/tier1/falcon2_monterey_interface.h" 19 #include "../../../../libs/phymod/chip/falcon_dpll/tier1/falcon_api_uc_common.h" 20 #include "../../../../libs/phymod/chip/falcon_dpll/tier1/falcon_dpll_cfg_seq.h" 21 #include "../../../../libs/phymod/chip/falcon_dpll/tier1/falcon2_monterey_enum.h" 22 #include "../../../../libs/phymod/chip/tscf_gen3/tier1/tefmod_gen3.h" 23 24 25 #ifdef _ERR_MSG_MODULE_NAME 26 #error "_ERR_MSG_MODULE_NAME redefined" 27 #endif 28 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_PORT 29 30 #ifdef CPRIMOD_CPRI_FALCON_SUPPORT 31 #define CPRI_NOF_LANES_IN_CORE 4 32 33 #define CPRI_PMD_CRC_UCODE_VERIFY 1 34 35 extern unsigned char falcon_dpll_ucode[]; 36 extern unsigned short falcon_dpll_ucode_ver; 37 extern unsigned short falcon_dpll_ucode_crc; 38 extern unsigned short falcon_dpll_ucode_len; 39 40 STATIC 41 int _cprif_cpri_port_intr_hierarchy_enable(int unit, int port, int enable); 42 43 extern cprimod_interrupt_callback_entry_t cpri_intr_cbs[SOC_MAX_NUM_DEVICES][_shrCpriIntrCount]; 44 45 int cprif_test_api_dispatch(int unit, int port, int* value) 46 { 47 SOC_INIT_FUNC_DEFS; 48 LOG_CLI((" cprif_test_api_dispatch call u=%d port=%d .\n",unit,port)); 49 SOC_FUNC_RETURN; 50 51 } 52 53 static 54 int _cprif_from_speed_toframe_len (cprimod_port_speed_t speed) 55 { 56 int basic_frm_len = 0; 57 58 switch (speed) { 59 case cprimodSpd614p4: 60 basic_frm_len = 128; /* 16*8 */ 61 break; 62 case cprimodSpd1228p8: 63 basic_frm_len = 256; /* 16*16 */ 64 break; 65 case cprimodSpd2457p6: 66 basic_frm_len = 512; /* 16*32 */ 67 break; 68 case cprimodSpd3072p0: 69 basic_frm_len = 640; /* 16*40 */ 70 break; 71 case cprimodSpd4915p2: 72 basic_frm_len = 1024; /* 16*64 */ 73 break; 74 case cprimodSpd6144p0: 75 basic_frm_len = 1280; /* 16*80 */ 76 break; 77 case cprimodSpd8110p08: 78 basic_frm_len = 2048; /* 16*128 */ 79 break; 80 case cprimodSpd9830p4: 81 basic_frm_len = 2048; /* 16*128 */ 82 break; 83 case cprimodSpd10137p6: 84 basic_frm_len = 2560; /* 16*160 */ 85 break; 86 case cprimodSpd12165p12: 87 basic_frm_len = 3072; /* 16*192 */ 88 break; 89 case cprimodSpd24330p24: 90 basic_frm_len = 6144; /* 16*384 */ 91 break; 92 default: 93 basic_frm_len = 256; /* 16*16 */ 94 break; 95 } 96 97 return(basic_frm_len); 98 } 99 100 static 101 int _cprif_from_speed_towd_len (cprimod_port_speed_t speed) 102 { 103 104 int wd_len = 0; 105 106 switch (speed) { 107 case cprimodSpd614p4: 108 wd_len = 8; 109 break; 110 case cprimodSpd1228p8: 111 wd_len = 16; 112 break; 113 case cprimodSpd2457p6: 114 wd_len = 32; 115 break; 116 case cprimodSpd3072p0: 117 wd_len = 40; 118 break; 119 case cprimodSpd4915p2: 120 wd_len = 64; 121 break; 122 case cprimodSpd6144p0: 123 wd_len = 80; 124 break; 125 case cprimodSpd8110p08: 126 wd_len = 80; 127 break; 128 case cprimodSpd9830p4: 129 wd_len = 128; 130 break; 131 case cprimodSpd10137p6: 132 wd_len = 128; 133 break; 134 case cprimodSpd12165p12: 135 wd_len = 128; 136 break; 137 case cprimodSpd24330p24: 138 wd_len = 128; 139 break; 140 default: 141 wd_len = 16; 142 break; 143 } 144 return(wd_len); 145 } 146 147 static 148 int _cprif_get_basic_frm_len(int unit, int port, int *basic_frm_len, cprimod_direction_t dir) 149 { 150 cprimod_port_speed_t speed; 151 cprimod_port_interface_type_t interface; 152 153 SOC_INIT_FUNC_DEFS; 154 155 SOC_IF_ERROR_RETURN(cprif_drv_txcpri_port_type_get(unit, port, 156 &interface)); 157 if (interface == cprimodRsvd4){ 158 /* 159 * For RSVD4, there is a fixed table need to be programmed. 160 * The size of the table is same as message group size. 161 */ 162 *basic_frm_len = CPRIF_RSVD4_MSG_GRP_SIZE; 163 } else { 164 if (dir == CPRIMOD_DIR_TX) { 165 _SOC_IF_ERR_EXIT(cprif_drv_cpri_txpcs_speed_get(unit, port, &speed)); 166 } else { 167 _SOC_IF_ERR_EXIT(cprif_drv_cpri_rxpcs_speed_get(unit, port, &speed)); 168 } 169 *basic_frm_len = _cprif_from_speed_toframe_len(speed); 170 } 171 172 exit: 173 SOC_FUNC_RETURN; 174 } 175 176 int cprif_basic_frame_parser_active_table_set(int unit, int port, cprimod_basic_frame_table_id_t table, int sync_enable) 177 { 178 cprimod_basic_frame_usage_entry_t* usage_table; 179 uint8 new_active_table; 180 uint8 current_active_table; 181 int num_entries = 0; 182 int basic_frm_len =0; 183 184 SOC_INIT_FUNC_DEFS; 185 186 usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc(sizeof(cprimod_basic_frame_usage_entry_t) * 187 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, "cprif_drv"); 188 SOC_NULL_CHECK(usage_table); 189 _SOC_IF_ERR_EXIT(_cprif_get_basic_frm_len(unit, port, &basic_frm_len, CPRIMOD_DIR_RX)); 190 191 if (table == cprimod_basic_frame_table_0) { 192 new_active_table = 0; 193 current_active_table = 1; 194 } else { 195 new_active_table = 1; 196 current_active_table = 0; 197 } 198 /* 199 * Get Entries from the new_active_table/current standby table to be reprogram to 200 * current_active_table/new standby table. 201 */ 202 _SOC_IF_ERR_EXIT 203 (cprif_drv_basic_frame_usage_entries_get(unit, port, 204 new_active_table, 205 CPRIMOD_DIR_RX, 206 CPRIMOD_AXC_ID_ALL, 207 usage_table, 208 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, /* table size */ 209 &num_entries)); 210 _SOC_IF_ERR_EXIT 211 (cprif_drv_basic_frame_parser_active_table_set(unit, port, new_active_table)); 212 213 /* 214 * Only when sync_enable, active and standby table will get sync up. 215 * This sync_enable is only needed for CPRI structure aware mode. 216 */ 217 218 if (sync_enable) { 219 _SOC_IF_ERR_EXIT 220 (cprif_drv_basic_frame_usage_table_to_hw_table_set(unit, port, 221 current_active_table, 222 CPRIMOD_DIR_RX, 223 basic_frm_len, 224 usage_table, 225 &num_entries)); 226 _SOC_IF_ERR_EXIT 227 (cprif_drv_basic_frame_parser_table_num_entries_set(unit, port, current_active_table, num_entries)); 228 } 229 exit: 230 sal_free(usage_table); 231 SOC_FUNC_RETURN; 232 233 } 234 235 int cprif_basic_frame_parser_active_table_get(int unit, int port, cprimod_basic_frame_table_id_t* table) 236 { 237 uint8 tmp_table; 238 SOC_INIT_FUNC_DEFS; 239 240 _SOC_IF_ERR_EXIT 241 (cprif_drv_basic_frame_parser_active_table_get(unit, port, &tmp_table)); 242 243 if (tmp_table == CPRIF_BASIC_FRAME_TABLE_0) { 244 *table = cprimod_basic_frame_table_0; 245 } else { 246 *table = cprimod_basic_frame_table_1; 247 } 248 249 exit: 250 SOC_FUNC_RETURN; 251 252 } 253 254 255 int cprif_basic_frame_parser_table_num_entries_set(int unit, int port, cprimod_basic_frame_table_id_t table, uint32 num_entries) 256 { 257 uint8 tmp_table; 258 259 SOC_INIT_FUNC_DEFS; 260 261 if (table == cprimod_basic_frame_table_0) { 262 tmp_table = 0; 263 } else { 264 tmp_table = 1; 265 } 266 267 _SOC_IF_ERR_EXIT 268 (cprif_drv_basic_frame_parser_table_num_entries_set(unit, port, tmp_table, num_entries)); 269 270 exit: 271 SOC_FUNC_RETURN; 272 273 } 274 275 int cprif_basic_frame_parser_table_num_entries_get(int unit, int port, cprimod_basic_frame_table_id_t table, uint32* num_entries) 276 { 277 uint8 tmp_table; 278 279 SOC_INIT_FUNC_DEFS; 280 281 if (num_entries == NULL) { 282 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("num_entries NULL parameter")); 283 } 284 285 if (table == cprimod_basic_frame_table_0) { 286 tmp_table = 0; 287 } else { 288 tmp_table = 1; 289 } 290 291 _SOC_IF_ERR_EXIT 292 (cprif_drv_basic_frame_parser_table_num_entries_get(unit, port, tmp_table, num_entries)); 293 294 exit: 295 SOC_FUNC_RETURN; 296 297 } 298 299 300 int cprif_basic_frame_parser_switch_active_table(int unit, int port) 301 { 302 cprimod_basic_frame_table_id_t table; 303 SOC_INIT_FUNC_DEFS; 304 305 _SOC_IF_ERR_EXIT 306 (cprif_basic_frame_parser_active_table_get(unit, port,&table)); 307 if (table == cprimod_basic_frame_table_0) { 308 _SOC_IF_ERR_EXIT 309 (cprif_drv_basic_frame_parser_active_table_set(unit, port, cprimod_basic_frame_table_1)); 310 } else { 311 _SOC_IF_ERR_EXIT 312 (cprif_drv_basic_frame_parser_active_table_set(unit, port, cprimod_basic_frame_table_0)); 313 } 314 315 exit: 316 SOC_FUNC_RETURN; 317 318 } 319 320 321 int cprif_basic_frame_assembly_active_table_set(int unit, int port, cprimod_basic_frame_table_id_t table, int sync_enable) 322 { 323 cprimod_basic_frame_usage_entry_t* usage_table; 324 uint8 new_active_table; 325 uint8 current_active_table; 326 int num_entries = 0; 327 int basic_frm_len =0; 328 329 SOC_INIT_FUNC_DEFS; 330 331 usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc(sizeof(cprimod_basic_frame_usage_entry_t) * 332 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, "cprif_drv"); 333 SOC_NULL_CHECK(usage_table); 334 _SOC_IF_ERR_EXIT(_cprif_get_basic_frm_len(unit, port, &basic_frm_len, CPRIMOD_DIR_TX)); 335 336 if (table == cprimod_basic_frame_table_0) { 337 new_active_table = 0; 338 current_active_table = 1; 339 } else { 340 new_active_table = 1; 341 current_active_table = 0; 342 } 343 /* 344 * Get Entries from the new_active_table/current standby table before activation to be reprogram to 345 * current_active_table/new standby table. 346 */ 347 348 _SOC_IF_ERR_EXIT 349 (cprif_drv_basic_frame_usage_entries_get(unit, port, 350 new_active_table, 351 CPRIMOD_DIR_TX, 352 CPRIMOD_AXC_ID_ALL, 353 usage_table, 354 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, /* table size */ 355 &num_entries)); 356 _SOC_IF_ERR_EXIT 357 (cprif_drv_basic_frame_assembly_active_table_set(unit, port, new_active_table)); 358 359 /* 360 * Only when sync_enable, active and standby table will get sync up. 361 * This sync_enable is only needed for CPRI structure aware mode. 362 */ 363 if (sync_enable) { 364 _SOC_IF_ERR_EXIT 365 (cprif_drv_basic_frame_usage_table_to_hw_table_set(unit, port, 366 current_active_table, 367 CPRIMOD_DIR_TX, 368 basic_frm_len, 369 usage_table, 370 &num_entries)); 371 _SOC_IF_ERR_EXIT 372 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, current_active_table, num_entries)); 373 } 374 exit: 375 sal_free(usage_table); 376 SOC_FUNC_RETURN; 377 378 } 379 380 381 int cprif_basic_frame_assembly_active_table_get(int unit, int port, cprimod_basic_frame_table_id_t* table) 382 { 383 uint8 tmp_table; 384 SOC_INIT_FUNC_DEFS; 385 386 _SOC_IF_ERR_EXIT 387 (cprif_drv_basic_frame_assembly_active_table_get(unit, port, &tmp_table)); 388 389 if (tmp_table == CPRIF_BASIC_FRAME_TABLE_0) { 390 *table = cprimod_basic_frame_table_0; 391 } else { 392 *table = cprimod_basic_frame_table_1; 393 } 394 395 exit: 396 SOC_FUNC_RETURN; 397 } 398 int cprif_basic_frame_assembly_table_num_entries_set(int unit, int port, cprimod_basic_frame_table_id_t table, uint32 num_entries) 399 { 400 uint8 table_num; 401 SOC_INIT_FUNC_DEFS; 402 403 if (table == cprimod_basic_frame_table_0) { 404 table_num = 0; 405 } else { 406 table_num = 1; 407 } 408 409 _SOC_IF_ERR_EXIT 410 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, table_num, num_entries)); 411 412 exit: 413 SOC_FUNC_RETURN; 414 415 } 416 417 int cprif_basic_frame_assembly_table_num_entries_get(int unit, int port, cprimod_basic_frame_table_id_t table, uint32* num_entries) 418 { 419 uint8 table_num; 420 SOC_INIT_FUNC_DEFS; 421 422 if (table == cprimod_basic_frame_table_0) { 423 table_num = 0; 424 } else { 425 table_num = 1; 426 } 427 _SOC_IF_ERR_EXIT 428 (cprif_drv_basic_frame_assembly_table_num_entries_get(unit, port, table_num, num_entries)); 429 exit: 430 SOC_FUNC_RETURN; 431 432 } 433 434 int cprif_basic_frame_assembly_switch_active_table(int unit, int port) 435 { 436 cprimod_basic_frame_table_id_t table; 437 SOC_INIT_FUNC_DEFS; 438 439 _SOC_IF_ERR_EXIT 440 (cprif_basic_frame_assembly_active_table_get(unit, port,&table)); 441 if (table == cprimod_basic_frame_table_0) { 442 _SOC_IF_ERR_EXIT 443 (cprif_drv_basic_frame_assembly_active_table_set(unit, port, cprimod_basic_frame_table_1)); 444 } else { 445 _SOC_IF_ERR_EXIT 446 (cprif_drv_basic_frame_assembly_active_table_set(unit, port, cprimod_basic_frame_table_0)); 447 } 448 449 exit: 450 SOC_FUNC_RETURN; 451 } 452 453 int cprif_rx_axc_basic_frame_add(int unit, int port, 454 uint32 axc_id, 455 uint32 start_bit, 456 uint32 num_bits) 457 { 458 cprimod_basic_frame_usage_entry_t new_entry; 459 cprimod_basic_frame_usage_entry_t* usage_table=NULL; 460 uint8 active_table; 461 uint8 standby_table; 462 int num_entries = 0 ; 463 int basic_frm_len =0; 464 465 SOC_INIT_FUNC_DEFS; 466 467 _SOC_IF_ERR_EXIT(_cprif_get_basic_frm_len(unit, port, &basic_frm_len, CPRIMOD_DIR_RX)); 468 if ((axc_id >= CPRIF_MAX_NUM_OF_AXC)&&(axc_id != 0xff)) { 469 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 470 axc_id, 471 CPRIF_MAX_NUM_OF_AXC)) ; 472 return SOC_E_PARAM; 473 } 474 475 _SOC_IF_ERR_EXIT(cprif_drv_basic_frame_parser_active_table_get(unit, port, 476 &active_table)); 477 478 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 479 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 480 } else { 481 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 482 } 483 484 usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc 485 (sizeof(cprimod_basic_frame_usage_entry_t) * CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY , "cprimod"); 486 CPRIMOD_NULL_CHECK(usage_table); 487 488 new_entry.axc_id = axc_id; 489 new_entry.start_bit = start_bit; 490 new_entry.num_bits = num_bits; 491 492 /* 493 * Transfer HW table to usage table and also add the new 494 * entry to the appropriate location. 495 */ 496 497 _SOC_IF_ERR_EXIT 498 (cprif_drv_basic_frame_usage_entry_add(unit, port, 499 standby_table, 500 CPRIMOD_DIR_RX, 501 new_entry, 502 usage_table, 503 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, 504 &num_entries)); 505 506 _SOC_IF_ERR_EXIT 507 (cprif_drv_basic_frame_usage_table_to_hw_table_set(unit, port, 508 standby_table, 509 CPRIMOD_DIR_RX, 510 basic_frm_len, 511 usage_table, 512 &num_entries)); 513 _SOC_IF_ERR_EXIT 514 (cprif_drv_basic_frame_parser_table_num_entries_set(unit, port, standby_table, num_entries)); 515 516 exit: 517 sal_free(usage_table); 518 SOC_FUNC_RETURN; 519 520 } 521 522 int cprif_rx_axc_basic_frame_delete(int unit, int port, 523 uint32 axc_id) 524 { 525 cprimod_basic_frame_usage_entry_t* usage_table=NULL; 526 uint8 active_table; 527 uint8 standby_table; 528 int num_entries = 0; 529 int basic_frm_len =0; 530 531 SOC_INIT_FUNC_DEFS; 532 533 _SOC_IF_ERR_EXIT(_cprif_get_basic_frm_len(unit, port, &basic_frm_len, CPRIMOD_DIR_RX)); 534 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 535 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 536 axc_id, 537 CPRIF_MAX_NUM_OF_AXC)) ; 538 return SOC_E_PARAM; 539 } 540 541 _SOC_IF_ERR_EXIT(cprif_drv_basic_frame_parser_active_table_get(unit, port, 542 &active_table)); 543 544 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 545 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 546 } else { 547 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 548 } 549 550 usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc 551 (sizeof(cprimod_basic_frame_usage_entry_t) * CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY , "cprimod"); 552 CPRIMOD_NULL_CHECK(usage_table); 553 _SOC_IF_ERR_EXIT 554 (cprif_drv_basic_frame_usage_entry_delete(unit, port, 555 standby_table, 556 CPRIMOD_DIR_RX, 557 axc_id, 558 usage_table, 559 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, 560 &num_entries)); 561 562 _SOC_IF_ERR_EXIT 563 (cprif_drv_basic_frame_usage_table_to_hw_table_set(unit, port, 564 standby_table, 565 CPRIMOD_DIR_RX, 566 basic_frm_len, 567 usage_table, 568 &num_entries)); 569 _SOC_IF_ERR_EXIT 570 (cprif_drv_basic_frame_parser_table_num_entries_set(unit, port, standby_table, num_entries)); 571 572 573 exit: 574 sal_free(usage_table); 575 SOC_FUNC_RETURN; 576 577 } 578 579 int cprif_rx_axc_basic_frame_clear(int unit, int port) 580 { 581 cprif_bfa_bfp_table_entry_t table_entry; 582 uint8 active_table; 583 uint8 standby_table; 584 int table_index; 585 586 SOC_INIT_FUNC_DEFS; 587 588 _SOC_IF_ERR_EXIT(cprif_drv_basic_frame_parser_active_table_get(unit, port, 589 &active_table)); 590 591 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 592 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 593 } else { 594 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 595 } 596 597 /* clear the entry. */ 598 cprif_bfa_bfp_table_entry_t_init( &table_entry); 599 600 for (table_index=0; table_index < CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY ; table_index++) { 601 602 _SOC_IF_ERR_EXIT 603 (cprif_drv_basic_frame_entry_set(unit, port, 604 standby_table, 605 CPRIMOD_DIR_RX, 606 table_index, 607 &table_entry)); 608 } 609 610 exit: 611 SOC_FUNC_RETURN; 612 613 } 614 615 int cprif_rx_axc_basic_frame_get(int unit, int port, 616 uint32 axc_id, 617 cprimod_basic_frame_table_id_t table, 618 cprimod_basic_frame_usage_entry_t* usage_table, 619 int* num_entries) 620 { 621 uint8 tmp_table; 622 SOC_INIT_FUNC_DEFS; 623 624 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 625 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 626 axc_id, 627 CPRIF_MAX_NUM_OF_AXC)) ; 628 return SOC_E_PARAM; 629 } 630 631 if (table == cprimod_basic_frame_table_0) { 632 tmp_table = CPRIF_BASIC_FRAME_TABLE_0; 633 } else { 634 tmp_table = CPRIF_BASIC_FRAME_TABLE_1; 635 } 636 637 _SOC_IF_ERR_EXIT 638 (cprif_drv_basic_frame_usage_entries_get(unit, port, 639 tmp_table, 640 CPRIMOD_DIR_RX, 641 axc_id, 642 usage_table, 643 *num_entries, /* table size */ 644 num_entries)); 645 646 exit: 647 SOC_FUNC_RETURN; 648 649 } 650 651 int cprif_tx_axc_basic_frame_add(int unit, int port, uint32 axc_id, uint32 start_bit, uint32 num_bits) 652 { 653 cprimod_basic_frame_usage_entry_t new_entry; 654 cprimod_basic_frame_usage_entry_t* usage_table=NULL; 655 uint8 active_table; 656 uint8 standby_table; 657 int num_entries = 0 ; 658 int basic_frm_len =0; 659 660 SOC_INIT_FUNC_DEFS; 661 662 _SOC_IF_ERR_EXIT(_cprif_get_basic_frm_len(unit, port, &basic_frm_len, CPRIMOD_DIR_TX)); 663 if ((axc_id >= CPRIF_MAX_NUM_OF_AXC)&&(axc_id != 0xff)) { 664 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 665 axc_id, 666 CPRIF_MAX_NUM_OF_AXC)) ; 667 return SOC_E_PARAM; 668 } 669 670 _SOC_IF_ERR_EXIT(cprif_drv_basic_frame_assembly_active_table_get(unit, port, 671 &active_table)); 672 673 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 674 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 675 } else { 676 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 677 } 678 679 usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc 680 (sizeof(cprimod_basic_frame_usage_entry_t) * CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY , "cprimod"); 681 CPRIMOD_NULL_CHECK(usage_table); 682 683 new_entry.axc_id = axc_id; 684 new_entry.start_bit = start_bit; 685 new_entry.num_bits = num_bits; 686 687 /* 688 * Transfer HW table to usage table and also add the new 689 * entry to the appropriate location. 690 */ 691 692 _SOC_IF_ERR_EXIT 693 (cprif_drv_basic_frame_usage_entry_add(unit, port, 694 standby_table, 695 CPRIMOD_DIR_TX, 696 new_entry, 697 usage_table, 698 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, 699 &num_entries)); 700 701 _SOC_IF_ERR_EXIT 702 (cprif_drv_basic_frame_usage_table_to_hw_table_set(unit, port, 703 standby_table, 704 CPRIMOD_DIR_TX, 705 basic_frm_len, 706 usage_table, 707 &num_entries)); 708 _SOC_IF_ERR_EXIT 709 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, standby_table, num_entries)); 710 711 exit: 712 sal_free(usage_table); 713 SOC_FUNC_RETURN; 714 715 } 716 717 718 int cprif_tx_axc_basic_frame_delete(int unit, int port, uint32 axc_id) 719 { 720 cprimod_basic_frame_usage_entry_t* usage_table=NULL; 721 uint8 active_table; 722 uint8 standby_table; 723 int num_entries = 0; 724 int basic_frm_len =0; 725 726 SOC_INIT_FUNC_DEFS; 727 728 _SOC_IF_ERR_EXIT(_cprif_get_basic_frm_len(unit, port, &basic_frm_len, CPRIMOD_DIR_TX)); 729 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 730 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 731 axc_id, 732 CPRIF_MAX_NUM_OF_AXC)) ; 733 return SOC_E_PARAM; 734 } 735 736 _SOC_IF_ERR_EXIT(cprif_drv_basic_frame_assembly_active_table_get(unit, port, 737 &active_table)); 738 739 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 740 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 741 } else { 742 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 743 } 744 745 usage_table = (cprimod_basic_frame_usage_entry_t*)sal_alloc 746 (sizeof(cprimod_basic_frame_usage_entry_t) * CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY , "cprimod"); 747 CPRIMOD_NULL_CHECK(usage_table); 748 _SOC_IF_ERR_EXIT 749 (cprif_drv_basic_frame_usage_entry_delete(unit, port, 750 standby_table, 751 CPRIMOD_DIR_TX, 752 axc_id, 753 usage_table, 754 CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY, 755 &num_entries)); 756 757 _SOC_IF_ERR_EXIT 758 (cprif_drv_basic_frame_usage_table_to_hw_table_set(unit, port, 759 standby_table, 760 CPRIMOD_DIR_TX, 761 basic_frm_len, 762 usage_table, 763 &num_entries)); 764 _SOC_IF_ERR_EXIT 765 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, standby_table, num_entries)); 766 767 exit: 768 sal_free(usage_table); 769 SOC_FUNC_RETURN; 770 771 } 772 773 int cprif_tx_axc_basic_frame_clear(int unit, int port) 774 { 775 uint16 table_index = 0; 776 cprif_bfa_bfp_table_entry_t table_entry; 777 uint8 active_table; 778 uint8 standby_table; 779 780 SOC_INIT_FUNC_DEFS; 781 782 _SOC_IF_ERR_EXIT(cprif_drv_basic_frame_assembly_active_table_get(unit, port, 783 &active_table)); 784 785 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 786 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 787 } else { 788 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 789 } 790 791 /* clear the entry. */ 792 cprif_bfa_bfp_table_entry_t_init( &table_entry); 793 794 for (table_index=0; table_index < CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY ; table_index++) { 795 796 _SOC_IF_ERR_EXIT 797 (cprif_drv_basic_frame_entry_set( unit, port, standby_table, 798 CPRIMOD_DIR_TX, table_index, &table_entry)); 799 } 800 801 exit: 802 SOC_FUNC_RETURN; 803 804 } 805 806 int cprif_tx_axc_basic_frame_get(int unit, int port, 807 uint32 axc_id, 808 cprimod_basic_frame_table_id_t table, 809 cprimod_basic_frame_usage_entry_t* usage_table, 810 int* num_entries) 811 { 812 SOC_INIT_FUNC_DEFS; 813 814 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 815 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 816 axc_id, 817 CPRIF_MAX_NUM_OF_AXC)) ; 818 return SOC_E_PARAM; 819 } 820 821 _SOC_IF_ERR_EXIT 822 (cprif_drv_basic_frame_usage_entries_get(unit, port, 823 table, 824 CPRIMOD_DIR_TX, 825 axc_id, 826 usage_table, 827 *num_entries, /* table size */ 828 num_entries)); 829 830 exit: 831 SOC_FUNC_RETURN; 832 833 } 834 835 int cprif_basic_frame_debug(int unit, int port, uint32 axc_id, 836 cprimod_basic_frame_table_id_t rx_table, 837 cprimod_basic_frame_table_id_t tx_table, 838 uint32 flags) 839 { 840 841 SOC_INIT_FUNC_DEFS; 842 843 /* 844 * If axc_id is not between 0-63, and not control AxC, it want to list all AxCs. 845 */ 846 /* coverity[unsigned_compare:FALSE] */ 847 if (!((axc_id >= 0) && (axc_id <=63)) && 848 (axc_id != CPRIMOD_AXC_ID_CONTROL)) { 849 axc_id = CPRIMOD_AXC_ID_ALL ; 850 } 851 852 853 switch (flags) { 854 855 case CPRIMOD_DEBUG_BASIC_FRAME_RAW : 856 cprif_drv_basic_frame_debug_raw (unit, port, axc_id, rx_table, tx_table); 857 break; 858 case CPRIMOD_DEBUG_BASIC_FRAME_USAGE : 859 default: 860 cprif_drv_basic_frame_debug_usage (unit, port, axc_id, rx_table, tx_table); 861 break; 862 } 863 864 SOC_FUNC_RETURN; 865 866 } 867 868 869 /* 870 * 871 * CONTAINER Mapping 872 */ 873 static 874 int _cprif_cpri_container_map_config_set(int unit, int port, 875 cprimod_direction_t dir, 876 uint8 axc_id, 877 cprimod_cpri_container_config_t* config_info) 878 { 879 cprif_cpri_container_map_entry_t entry; 880 uint32 quotient; 881 uint32 remainder; 882 uint32 Na,Nc,Naxc,K,Nst,Nv; /* CPRI spec. */ 883 SOC_INIT_FUNC_DEFS; 884 885 cprif_cpri_container_map_entry_t_init( &entry); 886 887 if (config_info->map_method == cprimod_cpri_frame_map_method_1) { 888 entry.map_method = CPRIF_CONTAINER_MAP_CPRI_METHOD_1; 889 } else if (config_info->map_method == cprimod_cpri_frame_map_method_3) { 890 entry.map_method = CPRIF_CONTAINER_MAP_CPRI_METHOD_3; 891 } else { 892 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Unsupported Map Method Only Method 1 and 3 are supported")); 893 } 894 895 Naxc = config_info->Naxc; 896 Nst = config_info->Nst; 897 K = config_info->K; 898 899 Na = config_info->Na; 900 Nc = config_info->Nc; 901 Nv = config_info->Nv; 902 903 entry.axc_id = axc_id; 904 905 /* For CPRI, stuffing is always at the beginning. */ 906 entry.stuffing_at_end = CPRIF_CONTAINER_MAP_STUFFING_AT_BEGINNING; 907 908 909 if (entry.map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_1) { 910 /* MAP METHOD #1 */ 911 entry.cblk_cnt = K*Naxc; 912 entry.naxc_cnt = 2; 913 entry.stuff_cnt = Nst; 914 entry.Na = 0; 915 entry.Nv = 0; 916 } else if (entry.map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_3) { 917 /* MAP METHOD #3 */ 918 entry.naxc_cnt = Naxc; /* has to be 2M */ 919 entry.cblk_cnt = K*Nc*Naxc; 920 921 if (Nv) { 922 quotient = ((K * Nc) / Nv); 923 remainder = ((K * Nc) % Nv); 924 entry.stuff_cnt = ((quotient & 0x00ff) << 13) | (remainder & 0x1fff); 925 } else { 926 entry.stuff_cnt = 0; 927 } 928 entry.Na = Na; 929 entry.Nv = Nv; 930 } 931 932 entry.bfrm_offset = config_info->basic_frame_offset; 933 entry.hfn_offset = config_info->hyper_frame_offset; 934 entry.bfn_offset = config_info->radio_frame_offset; 935 936 if (config_info->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER) { 937 entry.hfrm_sync = 1; 938 entry.rfrm_sync = 0; /* don't care */ 939 940 } else if (config_info->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO) { 941 entry.hfrm_sync = 0; 942 entry.rfrm_sync = 1; 943 944 } else if (config_info->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC) { 945 entry.hfrm_sync = 0; 946 entry.rfrm_sync = 0; 947 948 } else if (config_info->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_TUNNEL) { 949 entry.hfrm_sync = 1; 950 entry.rfrm_sync = 1; 951 } else { 952 /* ERROR Condition */ 953 } 954 955 _SOC_IF_ERR_EXIT(cprif_drv_cpri_container_entry_set(unit, port, 956 dir, 957 axc_id, 958 &entry)); 959 exit: 960 SOC_FUNC_RETURN; 961 962 } 963 964 static 965 int _cprif_cpri_container_map_config_get(int unit, int port, 966 cprimod_direction_t dir, 967 uint8 axc_id, 968 cprimod_cpri_container_config_t* config_info) 969 { 970 cprif_cpri_container_map_entry_t entry; 971 972 SOC_INIT_FUNC_DEFS; 973 974 if (config_info == NULL) { 975 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info NULL parameter")); 976 } 977 if (SOC_E_NONE != cprimod_cpri_container_config_t_init( config_info)) { 978 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info initialization failed")); 979 } 980 981 _SOC_IF_ERR_EXIT(cprif_drv_cpri_container_entry_get(unit, port, dir, axc_id, &entry)); 982 983 if (entry.map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_1) { 984 config_info->map_method = cprimod_cpri_frame_map_method_1; 985 } else if (entry.map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_3){ 986 config_info->map_method = cprimod_cpri_frame_map_method_3; 987 }else { 988 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Unsupported Map Method Only Method 1 and 3 are supported")); 989 } 990 if (entry.map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_1) { 991 config_info->cblk_cnt = entry.cblk_cnt; 992 config_info->Nst = entry.stuff_cnt; 993 config_info->Na = entry.Na; 994 config_info->Nv = entry.Nv; 995 } else if (entry.map_method == CPRIF_CONTAINER_MAP_CPRI_METHOD_3) { 996 config_info->Naxc = entry.naxc_cnt; 997 config_info->Na = entry.Na; 998 config_info->Nv = entry.Nv; 999 config_info->cblk_cnt = entry.cblk_cnt; 1000 config_info->Nst = 0; 1001 } 1002 1003 config_info->basic_frame_offset = entry.bfrm_offset; 1004 config_info->hyper_frame_offset = entry.hfn_offset; 1005 config_info->radio_frame_offset = entry.bfn_offset; 1006 1007 if (entry.hfrm_sync == 1) { 1008 config_info->frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER; 1009 } else { 1010 if(entry.rfrm_sync == 1){ 1011 config_info->frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO; 1012 } else { 1013 config_info->frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC; 1014 } 1015 } 1016 1017 exit: 1018 SOC_FUNC_RETURN; 1019 1020 } 1021 1022 static 1023 int _cprif_rsvd4_container_map_config_set(int unit, int port, 1024 cprimod_direction_t dir, 1025 uint8 flow_id, 1026 cprimod_rsvd4_container_config_t* config_info) 1027 { 1028 cprif_rsvd4_container_map_entry_t entry; 1029 SOC_INIT_FUNC_DEFS; 1030 1031 cprif_rsvd4_container_map_entry_t_init( &entry); 1032 1033 /* always this. */ 1034 entry.map_method = CPRIF_CONTAINER_MAP_RSVD4; 1035 1036 entry.axc_id = config_info->axc_id; 1037 1038 /* For RSVD4, stuffing is always at the end. */ 1039 entry.stuffing_at_end = CPRIF_CONTAINER_MAP_STUFFING_AT_END; 1040 entry.stuff_cnt = config_info->stuffing_cnt; 1041 1042 entry.cblk_cnt = config_info->container_block_cnt; 1043 1044 entry.rfrm_offset = config_info->message_number_offset; 1045 entry.bfn_offset = config_info->master_frame_offset; 1046 1047 if ((config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_NO_SYNC)|| 1048 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_NO_SYNC )) { 1049 entry.hfrm_sync = 1; 1050 entry.rfrm_sync = 0; /* don't care */ 1051 } else if ((config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_OFFSET)|| 1052 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_OFFSET)) { 1053 entry.hfrm_sync = 0; 1054 entry.rfrm_sync = 1; 1055 } else if ((config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_AND_MASTER_OFFSET)|| 1056 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_AND_MASTER_OFFSET)) { 1057 entry.hfrm_sync = 0; 1058 entry.rfrm_sync = 0; 1059 } 1060 1061 /* 1062 * if GSM mode and rx dirction and any one of msg_ts mode. 1063 */ 1064 1065 if ( 1066 ((config_info->msg_ts_mode==CPRIMOD_RSVD4_MSG_TS_MODE_GSM_DL)|| 1067 (config_info->msg_ts_mode==CPRIMOD_RSVD4_MSG_TS_MODE_GSM_UL)) && 1068 (dir == CPRIMOD_DIR_RX) && 1069 ((config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_NO_SYNC)|| 1070 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_OFFSET)|| 1071 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_AND_MASTER_OFFSET)) 1072 ) { 1073 entry.msg_ts_sync = 1; 1074 } 1075 1076 if (config_info->msg_ts_mode == CPRIMOD_RSVD4_MSG_TS_MODE_WCDMA) { 1077 entry.msg_ts_mode = CPRIF_CONTAINER_MAP_MSG_TS_MODE_WCDMA; 1078 } else if (config_info->msg_ts_mode == CPRIMOD_RSVD4_MSG_TS_MODE_LTE) { 1079 entry.msg_ts_mode = CPRIF_CONTAINER_MAP_MSG_TS_MODE_LTE; 1080 } else if (config_info->msg_ts_mode == CPRIMOD_RSVD4_MSG_TS_MODE_GSM_DL) { 1081 entry.msg_ts_mode = CPRIF_CONTAINER_MAP_MSG_TS_MODE_GSM_DL; 1082 }else if (config_info->msg_ts_mode == CPRIMOD_RSVD4_MSG_TS_MODE_GSM_UL) { 1083 entry.msg_ts_mode = CPRIF_CONTAINER_MAP_MSG_TS_MODE_GSM_UL; 1084 } 1085 1086 entry.msg_ts_cnt = config_info->msg_ts_cnt; 1087 1088 if (dir == CPRIMOD_DIR_TX) { 1089 entry.use_ts_dbm = config_info->use_ts_dbm; 1090 1091 if (entry.use_ts_dbm) { 1092 entry.ts_dbm_prof_num = config_info->ts_dbm_prof_num; 1093 entry.num_active_slots = config_info->num_active_slots; 1094 } 1095 entry.msg_addr = config_info->msg_addr; 1096 entry.msg_type = config_info->msg_type; 1097 entry.msg_ts_offset = config_info->msg_ts_offset; 1098 } 1099 _SOC_IF_ERR_EXIT(cprif_drv_rsvd4_container_entry_set(unit, port, 1100 dir, 1101 flow_id, 1102 &entry)); 1103 exit: 1104 SOC_FUNC_RETURN; 1105 1106 } 1107 1108 static 1109 int _cprif_rsvd4_container_map_config_get(int unit, int port, 1110 cprimod_direction_t dir, 1111 uint8 flow_id, 1112 cprimod_rsvd4_container_config_t* config_info) 1113 { 1114 cprif_rsvd4_container_map_entry_t entry; 1115 SOC_INIT_FUNC_DEFS; 1116 1117 if (config_info == NULL) { 1118 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info NULL parameter")); 1119 } 1120 if (SOC_E_NONE != cprimod_rsvd4_container_config_t_init( config_info)) { 1121 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info initialization failed")); 1122 } 1123 1124 _SOC_IF_ERR_EXIT 1125 (cprif_drv_rsvd4_container_entry_get(unit, port, 1126 dir, 1127 flow_id, 1128 &entry)); 1129 1130 config_info->axc_id = entry.axc_id; 1131 config_info->stuffing_cnt = entry.stuff_cnt; 1132 config_info->container_block_cnt = entry.cblk_cnt; 1133 config_info->message_number_offset = entry.rfrm_offset; 1134 config_info->master_frame_offset = entry.bfn_offset; 1135 1136 if (entry.hfrm_sync == 1) { 1137 if (entry.msg_ts_sync == 1){ 1138 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_NO_SYNC; 1139 } else { 1140 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_NO_SYNC; 1141 } 1142 } else { 1143 if (entry.rfrm_sync == 1) { 1144 if (entry.msg_ts_sync == 1){ 1145 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_OFFSET; 1146 } else { 1147 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_OFFSET; 1148 } 1149 } else { 1150 if (entry.msg_ts_sync == 1){ 1151 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_AND_MASTER_OFFSET; 1152 } else { 1153 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_AND_MASTER_OFFSET; 1154 } 1155 } 1156 } 1157 1158 switch (entry.msg_ts_mode) { 1159 case CPRIF_CONTAINER_MAP_MSG_TS_MODE_WCDMA: 1160 config_info->msg_ts_mode = CPRIMOD_RSVD4_MSG_TS_MODE_WCDMA; 1161 break; 1162 1163 case CPRIF_CONTAINER_MAP_MSG_TS_MODE_LTE: 1164 config_info->msg_ts_mode = CPRIMOD_RSVD4_MSG_TS_MODE_LTE; 1165 break; 1166 case CPRIF_CONTAINER_MAP_MSG_TS_MODE_GSM_DL: 1167 config_info->msg_ts_mode = CPRIMOD_RSVD4_MSG_TS_MODE_GSM_DL; 1168 break; 1169 1170 case CPRIF_CONTAINER_MAP_MSG_TS_MODE_GSM_UL: 1171 config_info->msg_ts_mode = CPRIMOD_RSVD4_MSG_TS_MODE_GSM_UL; 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 config_info->msg_ts_cnt = entry.msg_ts_cnt; 1178 1179 if (dir == CPRIMOD_DIR_TX) { 1180 config_info->use_ts_dbm = entry.use_ts_dbm; 1181 config_info->ts_dbm_prof_num = entry.ts_dbm_prof_num ; 1182 config_info->num_active_slots = entry.num_active_slots; 1183 config_info->msg_addr = entry.msg_addr; 1184 config_info->msg_type = entry.msg_type; 1185 config_info->msg_ts_offset = entry.msg_ts_offset; 1186 } 1187 1188 exit: 1189 SOC_FUNC_RETURN; 1190 1191 } 1192 1193 int cprif_cpri_rx_axc_container_config_set(int unit, int port, uint32 axc_id, cprimod_cpri_container_config_t* config_info) 1194 { 1195 SOC_INIT_FUNC_DEFS; 1196 1197 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1198 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1199 axc_id, 1200 CPRIF_MAX_NUM_OF_AXC)) ; 1201 return SOC_E_PARAM; 1202 } 1203 1204 _SOC_IF_ERR_EXIT 1205 (_cprif_cpri_container_map_config_set(unit, port, 1206 CPRIMOD_DIR_RX, 1207 axc_id, 1208 config_info)); 1209 exit: 1210 SOC_FUNC_RETURN; 1211 } 1212 1213 int cprif_cpri_rx_axc_container_config_get(int unit, int port, uint32 axc_id, cprimod_cpri_container_config_t* config_info) 1214 { 1215 SOC_INIT_FUNC_DEFS; 1216 1217 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1218 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1219 axc_id, 1220 CPRIF_MAX_NUM_OF_AXC)) ; 1221 return SOC_E_PARAM; 1222 } 1223 1224 /* NOT IMPLEMENTED */ 1225 _SOC_IF_ERR_EXIT 1226 (_cprif_cpri_container_map_config_get(unit, port, 1227 CPRIMOD_DIR_RX, 1228 axc_id, 1229 config_info)); 1230 exit: 1231 SOC_FUNC_RETURN; 1232 1233 } 1234 1235 int cprif_cpri_tx_axc_container_config_set(int unit, int port, uint32 axc_id, cprimod_cpri_container_config_t* config_info) 1236 { 1237 SOC_INIT_FUNC_DEFS; 1238 1239 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1240 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1241 axc_id, 1242 CPRIF_MAX_NUM_OF_AXC)) ; 1243 return SOC_E_PARAM; 1244 } 1245 1246 _SOC_IF_ERR_EXIT 1247 (_cprif_cpri_container_map_config_set(unit, port, 1248 CPRIMOD_DIR_TX, 1249 axc_id, 1250 config_info)); 1251 1252 exit: 1253 SOC_FUNC_RETURN; 1254 1255 } 1256 1257 int cprif_cpri_tx_axc_container_config_get(int unit, int port, uint32 axc_id, cprimod_cpri_container_config_t* config_info) 1258 { 1259 SOC_INIT_FUNC_DEFS; 1260 1261 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1262 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1263 axc_id, 1264 CPRIF_MAX_NUM_OF_AXC)) ; 1265 return SOC_E_PARAM; 1266 } 1267 1268 /* NOT IMPLEMENTED */ 1269 _SOC_IF_ERR_EXIT 1270 (_cprif_cpri_container_map_config_get(unit, port, 1271 CPRIMOD_DIR_TX, 1272 axc_id, 1273 config_info)); 1274 1275 exit: 1276 SOC_FUNC_RETURN; 1277 1278 } 1279 1280 1281 int cprif_rsvd4_rx_axc_container_config_set(int unit, int port, uint32 flow_id, cprimod_rsvd4_container_config_t* config_info) 1282 { 1283 SOC_INIT_FUNC_DEFS; 1284 1285 if (flow_id >= CPRIF_MAX_NUM_OF_AXC) { 1286 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1287 flow_id, 1288 CPRIF_MAX_NUM_OF_AXC)) ; 1289 return SOC_E_PARAM; 1290 } 1291 1292 _SOC_IF_ERR_EXIT 1293 (_cprif_rsvd4_container_map_config_set(unit, port, 1294 CPRIMOD_DIR_RX, 1295 flow_id, 1296 config_info)); 1297 exit: 1298 SOC_FUNC_RETURN; 1299 1300 } 1301 1302 int cprif_rsvd4_rx_axc_container_config_get(int unit, int port, uint32 flow_id, cprimod_rsvd4_container_config_t* config_info) 1303 { 1304 SOC_INIT_FUNC_DEFS; 1305 1306 if (flow_id >= CPRIF_MAX_NUM_OF_AXC) { 1307 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1308 flow_id, 1309 CPRIF_MAX_NUM_OF_AXC)) ; 1310 return SOC_E_PARAM; 1311 } 1312 1313 _SOC_IF_ERR_EXIT 1314 (_cprif_rsvd4_container_map_config_get(unit, port, 1315 CPRIMOD_DIR_RX, 1316 flow_id, 1317 config_info)); 1318 exit: 1319 SOC_FUNC_RETURN; 1320 1321 } 1322 1323 int cprif_rsvd4_tx_axc_container_config_set(int unit, int port, uint32 flow_id, cprimod_rsvd4_container_config_t* config_info) 1324 { 1325 SOC_INIT_FUNC_DEFS; 1326 1327 if (flow_id >= CPRIF_MAX_NUM_OF_AXC) { 1328 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1329 flow_id, 1330 CPRIF_MAX_NUM_OF_AXC)) ; 1331 return SOC_E_PARAM; 1332 } 1333 1334 _SOC_IF_ERR_EXIT 1335 (_cprif_rsvd4_container_map_config_set(unit, port, 1336 CPRIMOD_DIR_TX, 1337 flow_id, 1338 config_info)); 1339 exit: 1340 SOC_FUNC_RETURN; 1341 1342 } 1343 1344 int cprif_rsvd4_tx_axc_container_config_get(int unit, int port, uint32 flow_id, cprimod_rsvd4_container_config_t* config_info) 1345 { 1346 SOC_INIT_FUNC_DEFS; 1347 1348 if (flow_id >= CPRIF_MAX_NUM_OF_AXC) { 1349 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1350 flow_id, 1351 CPRIF_MAX_NUM_OF_AXC)) ; 1352 return SOC_E_PARAM; 1353 } 1354 1355 _SOC_IF_ERR_EXIT 1356 (_cprif_rsvd4_container_map_config_get(unit, port, 1357 CPRIMOD_DIR_TX, 1358 flow_id, 1359 config_info)); 1360 exit: 1361 SOC_FUNC_RETURN; 1362 1363 } 1364 1365 /* 1366 * 1367 * IQ Packing/Unpacking 1368 */ 1369 1370 int cprif_rx_roe_payload_size_set(int unit, int port, uint32 axc_id, cprimod_payload_size_info_t* config_info) 1371 { 1372 cprif_iq_buffer_config_t entry; 1373 SOC_INIT_FUNC_DEFS; 1374 1375 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1376 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1377 axc_id, 1378 CPRIF_MAX_NUM_OF_AXC)) ; 1379 return SOC_E_PARAM; 1380 } 1381 1382 cprif_iq_buffer_config_t_init( &entry); 1383 1384 entry.payload_size = config_info->packet_size; 1385 entry.last_packet_num = config_info->last_packet_num; 1386 entry.last_payload_size = config_info->last_packet_size; 1387 1388 _SOC_IF_ERR_EXIT (cprif_drv_iq_buffer_config_set(unit, port, 1389 CPRIMOD_DIR_RX, 1390 axc_id, 1391 &entry)); 1392 exit: 1393 SOC_FUNC_RETURN; 1394 1395 } 1396 1397 int cprif_rx_roe_payload_size_get(int unit, int port, uint32 axc_id, cprimod_payload_size_info_t* config_info) 1398 { 1399 cprif_iq_buffer_config_t entry; 1400 SOC_INIT_FUNC_DEFS; 1401 1402 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1403 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1404 axc_id, 1405 CPRIF_MAX_NUM_OF_AXC)) ; 1406 return SOC_E_PARAM; 1407 } 1408 1409 cprif_iq_buffer_config_t_init( &entry); 1410 1411 _SOC_IF_ERR_EXIT(cprif_drv_iq_buffer_config_get(unit, port, 1412 CPRIMOD_DIR_RX, 1413 axc_id, 1414 &entry)); 1415 1416 config_info->packet_size = entry.payload_size; 1417 config_info->last_packet_num = entry.last_packet_num; 1418 config_info->last_packet_size = entry.last_payload_size; 1419 1420 exit: 1421 SOC_FUNC_RETURN; 1422 1423 } 1424 1425 int cprif_tx_roe_payload_size_set(int unit, int port, uint32 axc_id, cprimod_payload_size_info_t* config_info) 1426 { 1427 cprif_iq_buffer_config_t entry; 1428 SOC_INIT_FUNC_DEFS; 1429 1430 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1431 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1432 axc_id, 1433 CPRIF_MAX_NUM_OF_AXC)) ; 1434 return SOC_E_PARAM; 1435 } 1436 1437 cprif_iq_buffer_config_t_init( &entry); 1438 1439 entry.payload_size = config_info->packet_size; 1440 entry.last_packet_num = config_info->last_packet_num; 1441 entry.last_payload_size = config_info->last_packet_size; 1442 1443 _SOC_IF_ERR_EXIT (cprif_drv_iq_buffer_config_set(unit, port, 1444 CPRIMOD_DIR_TX, 1445 axc_id, 1446 &entry)); 1447 exit: 1448 SOC_FUNC_RETURN; 1449 1450 } 1451 1452 int cprif_tx_roe_payload_size_get(int unit, int port, uint32 axc_id, cprimod_payload_size_info_t* config_info) 1453 { 1454 cprif_iq_buffer_config_t entry; 1455 SOC_INIT_FUNC_DEFS; 1456 1457 if (axc_id >= CPRIF_MAX_NUM_OF_AXC) { 1458 CPRIMOD_DEBUG_ERROR(("AxC ID %d is out of range > than %d", 1459 axc_id, 1460 CPRIF_MAX_NUM_OF_AXC)) ; 1461 return SOC_E_PARAM; 1462 } 1463 1464 cprif_iq_buffer_config_t_init( &entry); 1465 1466 _SOC_IF_ERR_EXIT(cprif_drv_iq_buffer_config_get(unit, port, 1467 CPRIMOD_DIR_TX, 1468 axc_id, 1469 &entry)); 1470 1471 config_info->packet_size = entry.payload_size; 1472 config_info->last_packet_num = entry.last_packet_num; 1473 config_info->last_packet_size = entry.last_payload_size; 1474 1475 exit: 1476 SOC_FUNC_RETURN; 1477 1478 } 1479 1480 /* 1481 * 1482 * ENCAP/DECAP DATA Configuration. 1483 */ 1484 int cprif_cpri_encap_data_config_set(int unit, int port, uint32 queue_num, cprimod_encap_decap_data_config_t* config_info) 1485 { 1486 cprif_encap_decap_data_entry_t entry; 1487 uint16 queue_offset=0; 1488 1489 SOC_INIT_FUNC_DEFS; 1490 1491 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1492 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1493 queue_num, 1494 CPRIF_MAX_NUM_OF_QUEUES)) ; 1495 return SOC_E_PARAM; 1496 } 1497 1498 cprif_encap_decap_data_entry_t_init( &entry); 1499 1500 entry.valid = 1; 1501 entry.sample_size = config_info->sample_size; 1502 entry.out_sample_size = entry.sample_size; 1503 1504 /* for 16 bits to 15 bits, process before compression. */ 1505 1506 if (config_info->truncation_enable) { 1507 if ((config_info->truncation_type == cprimod_truncation_type_16_to_15)|| 1508 (config_info->truncation_type == cprimod_truncation_type_add_1)) { 1509 if (entry.out_sample_size == 16) { 1510 entry.out_sample_size = 15; 1511 entry.sign_ext_enable = 1; 1512 if (config_info->truncation_type == cprimod_truncation_type_16_to_15) { 1513 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_16_TO_15; 1514 } else { 1515 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_ADD_1; 1516 } 1517 1518 } else { 1519 LOG_CLI(("truncation can only apply to 16 bit sample.\n")); 1520 } 1521 } 1522 } 1523 1524 if (config_info->compression_type == cprimod_decompress) { 1525 if (entry.out_sample_size == 9) { 1526 entry.out_sample_size = 15; 1527 } else { 1528 LOG_CLI(("decompression can only apply to 9 bits sample.\n")); 1529 } 1530 } else if (config_info->compression_type == cprimod_compress) { 1531 1532 if (entry.out_sample_size == 15) { 1533 entry.out_sample_size = 9; 1534 } else { 1535 LOG_CLI(("Compression can only be done on 15 bit samples.")); 1536 } 1537 } 1538 1539 /* for 15 bits to 16 bits, process after compression. */ 1540 if (config_info->truncation_enable) { 1541 if ((config_info->truncation_type == cprimod_truncation_type_15_to_16)|| 1542 (config_info->truncation_type == cprimod_truncation_type_add_0)) { 1543 if (entry.out_sample_size == 15) { 1544 entry.out_sample_size = 16; 1545 entry.sign_ext_enable = 1; 1546 if (config_info->truncation_type == cprimod_truncation_type_15_to_16) { 1547 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_15_TO_16; 1548 } else { 1549 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_ADD_0; 1550 } 1551 } else { 1552 LOG_CLI(("15 to 16 or add 0 truncation can only apply to 15 bit sample.\n")); 1553 } 1554 } 1555 } 1556 1557 /* 1558 * Agnostic Mode do not need to allocate as there will only be one queue. 1559 * It will always start at 0. 1560 */ 1561 1562 if (config_info->is_agnostic) { 1563 queue_offset = 0; 1564 } else { 1565 _SOC_IF_ERR_EXIT 1566 (cprif_drv_encap_data_allocate_buffer(unit, port, 1567 CPRIMOD_DIR_RX, 1568 config_info->buffer_size, 1569 &queue_offset)); 1570 } 1571 1572 entry.mux_enable = config_info->mux_enable; 1573 entry.queue_offset = queue_offset; 1574 /* 1575 * Convert the number of bytes into number of 16 bytes entries. 1576 */ 1577 entry.queue_size = CPRIF_NUM_OF_BUFFER_ENTRIES(config_info->buffer_size); 1578 entry.work_queue_select = config_info->priority; 1579 entry.bit_reversal = config_info->bit_reversal; 1580 1581 _SOC_IF_ERR_EXIT(cprif_drv_encap_data_entry_set(unit, port, 1582 CPRIMOD_DIR_RX, 1583 queue_num, 1584 &entry)); 1585 1586 exit: 1587 SOC_FUNC_RETURN; 1588 1589 } 1590 1591 int cprif_cpri_encap_data_config_get(int unit, int port, uint32 queue_num, cprimod_encap_decap_data_config_t* config_info) 1592 { 1593 cprif_encap_decap_data_entry_t entry; 1594 SOC_INIT_FUNC_DEFS; 1595 1596 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1597 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1598 queue_num, 1599 CPRIF_MAX_NUM_OF_QUEUES)) ; 1600 return SOC_E_PARAM; 1601 } 1602 1603 _SOC_IF_ERR_EXIT(cprif_drv_encap_data_entry_get(unit, port, 1604 CPRIMOD_DIR_RX, 1605 queue_num, 1606 &entry)); 1607 config_info->sample_size = entry.sample_size; 1608 config_info->truncation_enable = entry.sign_ext_enable; 1609 if (config_info->truncation_enable) { 1610 if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_15_TO_16) { 1611 config_info->truncation_type = cprimod_truncation_type_15_to_16; 1612 } else if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_ADD_0) { 1613 config_info->truncation_type = cprimod_truncation_type_add_0; 1614 } else if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_16_TO_15) { 1615 config_info->truncation_type = cprimod_truncation_type_16_to_15; 1616 } else if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_ADD_1) { 1617 config_info->truncation_type = cprimod_truncation_type_add_1; 1618 } 1619 } 1620 1621 if ((entry.out_sample_size == 9) && (entry.sample_size > 9)) { 1622 config_info->compression_type = cprimod_compress; 1623 } else if ((entry.out_sample_size >= 15) && 1624 (entry.sample_size < 15)) { 1625 config_info->compression_type = cprimod_decompress; 1626 } 1627 1628 config_info->mux_enable = entry.mux_enable; 1629 config_info->bit_reversal = entry.bit_reversal; 1630 /* 1631 * Convert number of 16 bytes entries into bytes. 1632 */ 1633 config_info->buffer_size = entry.queue_size * CPRIF_DATA_BUFFER_BLOCK_SIZE; 1634 config_info->priority = entry.work_queue_select; 1635 1636 exit: 1637 SOC_FUNC_RETURN; 1638 1639 } 1640 1641 1642 int cprif_cpri_decap_data_config_set(int unit, int port, uint32 queue_num, cprimod_encap_decap_data_config_t* config_info) 1643 { 1644 cprif_encap_decap_data_entry_t entry; 1645 uint16 queue_offset =0; 1646 uint32 buffer_size_in_bytes; 1647 1648 SOC_INIT_FUNC_DEFS; 1649 1650 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1651 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1652 queue_num, 1653 CPRIF_MAX_NUM_OF_QUEUES)) ; 1654 return SOC_E_PARAM; 1655 } 1656 1657 cprif_encap_decap_data_entry_t_init( &entry); 1658 1659 entry.valid = 1; 1660 entry.sample_size = config_info->sample_size; 1661 entry.out_sample_size = entry.sample_size; 1662 1663 /* for 16 bits to 15 bits, process before compression. */ 1664 1665 if (config_info->truncation_enable) { 1666 if ((config_info->truncation_type == cprimod_truncation_type_16_to_15)|| 1667 (config_info->truncation_type == cprimod_truncation_type_add_1)) { 1668 if (entry.out_sample_size == 16) { 1669 entry.out_sample_size = 15; 1670 entry.sign_ext_enable = 1; 1671 if (config_info->truncation_type == cprimod_truncation_type_16_to_15) { 1672 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_16_TO_15; 1673 } else { 1674 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_ADD_1; 1675 } 1676 1677 } else { 1678 LOG_CLI(("truncation can only apply to 16 bit sample.\n")); 1679 } 1680 } 1681 } 1682 1683 if (config_info->compression_type == cprimod_decompress) { 1684 if (entry.out_sample_size == 9) { 1685 entry.out_sample_size = 15; 1686 } else { 1687 LOG_CLI(("decompression can only apply to 9 bits sample.\n")); 1688 } 1689 } else if (config_info->compression_type == cprimod_compress) { 1690 1691 if (entry.out_sample_size == 15) { 1692 entry.out_sample_size = 9; 1693 } else { 1694 LOG_CLI(("Compression can only be done on 15 bit samples.")); 1695 } 1696 } 1697 1698 /* for 15 bits to 16 bits, process after compression. */ 1699 if (config_info->truncation_enable) { 1700 if ((config_info->truncation_type == cprimod_truncation_type_15_to_16)|| 1701 (config_info->truncation_type == cprimod_truncation_type_add_0)) { 1702 if (entry.out_sample_size == 15) { 1703 entry.out_sample_size = 16; 1704 entry.sign_ext_enable = 1; 1705 if (config_info->truncation_type == cprimod_truncation_type_15_to_16) { 1706 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_15_TO_16; 1707 } else { 1708 entry.sign_ext_type = CPRIF_DATA_SIGN_EXT_ADD_0; 1709 } 1710 } else { 1711 LOG_CLI(("15 to 16 or add 0 truncation can only apply to 15 bit sample.\n")); 1712 } 1713 } 1714 } 1715 1716 /* 1717 * Calculate space for the buffer. 1718 */ 1719 1720 buffer_size_in_bytes = CPRIF_NUM_OF_BUFFER_ENTRIES(config_info->buffer_size) * CPRIF_DATA_BUFFER_BLOCK_SIZE * config_info->cycle_size; 1721 1722 /* 1723 * Agnostic Mode do not need to allocate as there will only be one queue. 1724 * It will always start at 0. 1725 */ 1726 if (config_info->is_agnostic) { 1727 queue_offset = 0; 1728 } else { 1729 _SOC_IF_ERR_EXIT 1730 (cprif_drv_encap_data_allocate_buffer(unit, port, 1731 CPRIMOD_DIR_TX, 1732 buffer_size_in_bytes, 1733 &queue_offset)); 1734 } 1735 entry.mux_enable = config_info->mux_enable; 1736 entry.queue_offset = queue_offset; /* Memory management Here. */ 1737 /* 1738 * Conver Buffer Size into number of 16 bits entries. 1739 */ 1740 entry.queue_size = CPRIF_NUM_OF_BUFFER_ENTRIES(config_info->buffer_size); 1741 entry.tx_cycle_size = config_info->cycle_size; 1742 entry.bit_reversal = config_info->bit_reversal; 1743 1744 _SOC_IF_ERR_EXIT(cprif_drv_encap_data_entry_set(unit, port, 1745 CPRIMOD_DIR_TX, 1746 queue_num, 1747 &entry)); 1748 1749 exit: 1750 SOC_FUNC_RETURN; 1751 1752 } 1753 1754 int cprif_cpri_decap_data_config_get(int unit, int port, uint32 queue_num, cprimod_encap_decap_data_config_t* config_info) 1755 { 1756 cprif_encap_decap_data_entry_t entry; 1757 SOC_INIT_FUNC_DEFS; 1758 1759 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1760 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1761 queue_num, 1762 CPRIF_MAX_NUM_OF_QUEUES)) ; 1763 return SOC_E_PARAM; 1764 } 1765 1766 _SOC_IF_ERR_EXIT(cprif_drv_encap_data_entry_get(unit, port, 1767 CPRIMOD_DIR_TX, 1768 queue_num, 1769 &entry)); 1770 config_info->sample_size = entry.sample_size; 1771 config_info->truncation_enable = entry.sign_ext_enable; 1772 if (config_info->truncation_enable) { 1773 if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_15_TO_16) { 1774 config_info->truncation_type = cprimod_truncation_type_15_to_16; 1775 } else if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_ADD_0) { 1776 config_info->truncation_type = cprimod_truncation_type_add_0; 1777 } else if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_16_TO_15) { 1778 config_info->truncation_type = cprimod_truncation_type_16_to_15; 1779 } else if (entry.sign_ext_type == CPRIF_DATA_SIGN_EXT_ADD_1) { 1780 config_info->truncation_type = cprimod_truncation_type_add_1; 1781 } 1782 } 1783 1784 if ((entry.out_sample_size == 9) && (entry.sample_size > 9)) { 1785 config_info->compression_type = cprimod_compress; 1786 } else if ((entry.out_sample_size >= 15) && 1787 (entry.sample_size < 15)) { 1788 config_info->compression_type = cprimod_decompress; 1789 } 1790 1791 config_info->mux_enable = entry.mux_enable; 1792 config_info->bit_reversal = entry.bit_reversal; 1793 /* 1794 * Convert number of 16 bytes entries into bytes. 1795 */ 1796 config_info->buffer_size = entry.queue_size * CPRIF_DATA_BUFFER_BLOCK_SIZE ; 1797 config_info->cycle_size = entry.tx_cycle_size; 1798 1799 exit: 1800 SOC_FUNC_RETURN; 1801 1802 } 1803 1804 int cprif_rsvd4_encap_data_config_set(int unit, int port, uint32 queue_num, cprimod_rsvd4_encap_data_config_t* config_info) 1805 { 1806 uint16 queue_offset=0; 1807 cprif_rsvd4_encap_decap_data_entry_t entry; 1808 1809 SOC_INIT_FUNC_DEFS; 1810 1811 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1812 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1813 queue_num, 1814 CPRIF_MAX_NUM_OF_QUEUES)) ; 1815 return SOC_E_PARAM; 1816 } 1817 1818 cprif_rsvd4_encap_decap_data_entry_t_init( &entry); 1819 1820 entry.valid = 1; 1821 entry.gsm_pad_size = config_info->gsm_pad_size; 1822 entry.gsm_extra_pad_size = config_info->gsm_extra_pad_size; 1823 entry.gsm_pad_enable = config_info->gsm_pad_enable; 1824 entry.gsm_control_location = config_info->gsm_control_location; 1825 entry.queue_size = config_info->buffer_size; 1826 entry.work_queue_select = config_info->priority; 1827 entry.bit_reversal = config_info->bit_reversal; 1828 1829 _SOC_IF_ERR_EXIT (cprif_drv_encap_data_allocate_buffer(unit, port, 1830 CPRIMOD_DIR_RX, 1831 config_info->buffer_size, 1832 &queue_offset)); 1833 entry.queue_offset = queue_offset; 1834 1835 _SOC_IF_ERR_EXIT(cprif_drv_rsvd4_encap_data_entry_set(unit, port, 1836 CPRIMOD_DIR_RX, 1837 queue_num, 1838 &entry)); 1839 1840 exit: 1841 SOC_FUNC_RETURN; 1842 } 1843 1844 int cprif_rsvd4_encap_data_config_get(int unit, int port, uint32 queue_num, cprimod_rsvd4_encap_data_config_t* config_info) 1845 { 1846 1847 cprif_rsvd4_encap_decap_data_entry_t entry; 1848 1849 SOC_INIT_FUNC_DEFS; 1850 1851 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1852 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1853 queue_num, 1854 CPRIF_MAX_NUM_OF_QUEUES)) ; 1855 return SOC_E_PARAM; 1856 } 1857 1858 cprif_rsvd4_encap_decap_data_entry_t_init( &entry); 1859 1860 _SOC_IF_ERR_EXIT(cprif_drv_rsvd4_encap_data_entry_get(unit, port, 1861 CPRIMOD_DIR_RX, 1862 queue_num, 1863 &entry)); 1864 1865 config_info->gsm_pad_size = entry.gsm_pad_size; 1866 config_info->gsm_extra_pad_size = entry.gsm_extra_pad_size; 1867 config_info->gsm_pad_enable = entry.gsm_pad_enable; 1868 config_info->gsm_control_location = entry.gsm_control_location; 1869 config_info->buffer_size = entry.queue_size; 1870 config_info->priority = entry.work_queue_select; 1871 config_info->bit_reversal = entry.bit_reversal; 1872 1873 1874 exit: 1875 SOC_FUNC_RETURN; 1876 1877 } 1878 1879 int cprif_rsvd4_decap_data_config_set(int unit, int port, uint32 queue_num, cprimod_rsvd4_decap_data_config_t* config_info) 1880 { 1881 uint16 queue_offset =0; 1882 uint32 buffer_size_in_bytes; 1883 cprif_rsvd4_encap_decap_data_entry_t entry; 1884 1885 SOC_INIT_FUNC_DEFS; 1886 1887 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1888 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1889 queue_num, 1890 CPRIF_MAX_NUM_OF_QUEUES)) ; 1891 return SOC_E_PARAM; 1892 } 1893 1894 cprif_rsvd4_encap_decap_data_entry_t_init( &entry); 1895 1896 entry.valid = 1; 1897 entry.gsm_pad_size = config_info->gsm_pad_size; 1898 entry.gsm_extra_pad_size = config_info->gsm_extra_pad_size; 1899 entry.gsm_pad_enable = config_info->gsm_pad_enable; 1900 entry.gsm_control_location = config_info->gsm_control_location; 1901 entry.queue_size = config_info->buffer_size; 1902 entry.tx_cycle_size = config_info->cycle_size; 1903 entry.bit_reversal = config_info->bit_reversal; 1904 1905 buffer_size_in_bytes = CPRIF_NUM_OF_BUFFER_ENTRIES(config_info->buffer_size) 1906 * CPRIF_DATA_BUFFER_BLOCK_SIZE 1907 * config_info->cycle_size; 1908 _SOC_IF_ERR_EXIT(cprif_drv_encap_data_allocate_buffer(unit, port, 1909 CPRIMOD_DIR_TX, 1910 buffer_size_in_bytes, 1911 &queue_offset)); 1912 entry.queue_offset = queue_offset; 1913 1914 _SOC_IF_ERR_EXIT(cprif_drv_rsvd4_encap_data_entry_set(unit, port, 1915 CPRIMOD_DIR_TX, 1916 queue_num, 1917 &entry)); 1918 exit: 1919 SOC_FUNC_RETURN; 1920 1921 } 1922 1923 int cprif_rsvd4_decap_data_config_get(int unit, int port, uint32 queue_num, cprimod_rsvd4_decap_data_config_t* config_info) 1924 { 1925 cprif_rsvd4_encap_decap_data_entry_t entry; 1926 1927 SOC_INIT_FUNC_DEFS; 1928 1929 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1930 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1931 queue_num, 1932 CPRIF_MAX_NUM_OF_QUEUES)) ; 1933 return SOC_E_PARAM; 1934 } 1935 1936 cprif_rsvd4_encap_decap_data_entry_t_init( &entry); 1937 1938 _SOC_IF_ERR_EXIT(cprif_drv_rsvd4_encap_data_entry_get(unit, port, 1939 CPRIMOD_DIR_TX, 1940 queue_num, 1941 &entry)); 1942 1943 config_info->gsm_pad_size = entry.gsm_pad_size; 1944 config_info->gsm_extra_pad_size = entry.gsm_extra_pad_size; 1945 config_info->gsm_pad_enable = entry.gsm_pad_enable; 1946 config_info->gsm_control_location = entry.gsm_control_location; 1947 config_info->buffer_size = entry.queue_size; 1948 config_info->cycle_size = entry.tx_cycle_size; 1949 config_info->bit_reversal = entry.bit_reversal; 1950 1951 1952 exit: 1953 SOC_FUNC_RETURN; 1954 1955 } 1956 1957 int cprif_encap_header_config_set(int unit, int port, uint32 queue_num, cprimod_encap_header_config_t* config_info) 1958 { 1959 cprif_encap_header_entry_t entry; 1960 uint32 pc_id; 1961 SOC_INIT_FUNC_DEFS; 1962 1963 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 1964 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 1965 queue_num, 1966 CPRIF_MAX_NUM_OF_QUEUES)) ; 1967 return SOC_E_PARAM; 1968 } 1969 1970 if (config_info->header_type == cprimod_hdr_encap_type_roe) { 1971 entry.header_type = CPRIF_ENCAP_HEADER_HDR_TYPE_ROE; 1972 } else if (config_info->header_type == cprimod_hdr_encap_type_encap_none) { 1973 entry.header_type = CPRIF_ENCAP_HEADER_HDR_TYPE_ENCAP_NONE; 1974 } else { 1975 /* not suppose to be here. */ 1976 } 1977 1978 if (config_info->roe_frame_format == CPRIMOD_CPRI_ROE_FRAME_FORMAT_IEEE1914) { 1979 entry.ver = (config_info->roe_subtype & 0xc0) >> 6; 1980 entry.pkttype = (config_info->roe_subtype & 0x3f); 1981 entry.flow_id = config_info->flow_id; 1982 1983 } else if (config_info->roe_frame_format == CPRIMOD_CPRI_ROE_FRAME_FORMAT_RSVD3) { 1984 entry.ver = (config_info->version & 0x0c)>>2; 1985 entry.pkttype = ((config_info->version & 0x3) << 4 ) | ((config_info->flow_id & 0xf00) >> 8); 1986 entry.flow_id = config_info->flow_id & 0xFF; 1987 } else if ((config_info->roe_frame_format == CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8)|| 1988 (config_info->roe_frame_format == CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12)) { 1989 1990 entry.roe_opcode = config_info->ecpri_msg_type; 1991 /* msb of pc_id */ 1992 pc_id = ((config_info->ecpri_pc_id & 0xFF00) >> 8); 1993 entry.ver = (pc_id & 0xc0) >> 6; 1994 entry.pkttype = (pc_id & 0x3f); 1995 /* lsb of pc_id */ 1996 entry.flow_id = config_info->ecpri_pc_id & 0x00FF; 1997 1998 } else { 1999 CPRIMOD_DEBUG_ERROR(("Unsupported RoE Frame Format %d", 2000 config_info->roe_frame_format)); 2001 return SOC_E_PARAM; 2002 } 2003 2004 switch (config_info->vlan_type) { 2005 case cprimodHdrVlanTypeUntagged : 2006 entry.vlan_type = CPRIF_ENCAP_HEADER_VLAN_TYPE_UNTAGGED; 2007 break; 2008 2009 case cprimodHdrVlanTypeTaggedVlan0 : 2010 entry.vlan_type = CPRIF_ENCAP_HEADER_VLAN_TYPE_TAGGED_VLAN_0; 2011 break; 2012 2013 case cprimodHdrVlanTypeQinQ : 2014 entry.vlan_type = CPRIF_ENCAP_HEADER_VLAN_TYPE_Q_IN_Q; 2015 break; 2016 2017 case cprimodHdrVlanTypeTaggedVlan1 : 2018 entry.vlan_type = CPRIF_ENCAP_HEADER_VLAN_TYPE_TAGGED_VLAN_1; 2019 break; 2020 default: 2021 entry.vlan_type = CPRIF_ENCAP_HEADER_VLAN_TYPE_UNTAGGED; 2022 break; 2023 } 2024 2025 2026 entry.ordering_info_index = config_info->ordering_info_index; 2027 entry.mac_da_index = config_info->mac_da_index; 2028 entry.mac_sa_index = config_info->mac_sa_index; 2029 entry.vlan_id_0_index = config_info->vlan_id_0_index; 2030 entry.vlan_id_1_index = config_info->vlan_id_1_index; 2031 entry.vlan_0_priority = config_info->vlan_0_priority; 2032 entry.vlan_1_priority = config_info->vlan_1_priority; 2033 entry.ether_type_index = config_info->vlan_eth_type_index; 2034 entry.use_tagid_for_flowid = config_info->use_tagid_for_flowid; 2035 entry.use_tagid_for_vlan = config_info->use_tagid_for_vlan; 2036 entry.use_opcode = config_info->use_opcode; 2037 if ((config_info->roe_frame_format != CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8)&& 2038 (config_info->roe_frame_format != CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12)) { 2039 entry.roe_opcode = config_info->roe_opcode; 2040 } 2041 _SOC_IF_ERR_EXIT 2042 (cprif_drv_encap_header_entry_set(unit, port, 2043 queue_num, 2044 CPRIF_ENCAP_HEADER_FLAGS_HDR_CONFIG_SET, 2045 &entry)); 2046 exit: 2047 SOC_FUNC_RETURN; 2048 2049 } 2050 2051 int cprif_encap_header_config_get(int unit, int port, uint32 queue_num, cprimod_encap_header_config_t* config_info) 2052 { 2053 cprif_encap_header_entry_t entry; 2054 SOC_INIT_FUNC_DEFS; 2055 2056 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 2057 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2058 queue_num, 2059 CPRIF_MAX_NUM_OF_QUEUES)) ; 2060 return SOC_E_PARAM; 2061 } 2062 2063 cprif_encap_header_entry_t_init(&entry); 2064 2065 _SOC_IF_ERR_EXIT 2066 (cprif_drv_encap_header_entry_get(unit, port, 2067 queue_num, 2068 &entry)); 2069 2070 if (entry.header_type == CPRIF_ENCAP_HEADER_HDR_TYPE_ROE) { 2071 config_info->header_type = cprimod_hdr_encap_type_roe; 2072 } else if (entry.header_type == CPRIF_ENCAP_HEADER_HDR_TYPE_ENCAP_NONE) { 2073 config_info->header_type = cprimod_hdr_encap_type_encap_none; 2074 } 2075 switch (entry.vlan_type) { 2076 case CPRIF_ENCAP_HEADER_VLAN_TYPE_UNTAGGED: 2077 config_info->vlan_type = cprimodHdrVlanTypeUntagged; 2078 break; 2079 2080 case CPRIF_ENCAP_HEADER_VLAN_TYPE_TAGGED_VLAN_0: 2081 config_info->vlan_type = cprimodHdrVlanTypeTaggedVlan0; 2082 break; 2083 2084 case CPRIF_ENCAP_HEADER_VLAN_TYPE_Q_IN_Q: 2085 config_info->vlan_type = cprimodHdrVlanTypeQinQ; 2086 break; 2087 2088 case CPRIF_ENCAP_HEADER_VLAN_TYPE_TAGGED_VLAN_1: 2089 config_info->vlan_type = cprimodHdrVlanTypeTaggedVlan1; 2090 break; 2091 default: 2092 config_info->vlan_type = cprimodHdrVlanTypeUntagged; /* ???? */ 2093 break; 2094 } 2095 2096 config_info->flow_id = entry.flow_id; 2097 config_info->roe_subtype = (entry.pkttype & 0x3f)| ((entry.ver & 0x3)<<6); 2098 config_info->ordering_info_index = entry.ordering_info_index; 2099 config_info->mac_da_index = entry.mac_da_index; 2100 config_info->mac_sa_index = entry.mac_sa_index; 2101 config_info->vlan_id_0_index = entry.vlan_id_0_index; 2102 config_info->vlan_id_1_index = entry.vlan_id_1_index; 2103 config_info->vlan_0_priority = entry.vlan_0_priority; 2104 config_info->vlan_1_priority = entry.vlan_1_priority; 2105 config_info->vlan_eth_type_index = entry.ether_type_index; 2106 config_info->use_tagid_for_flowid = entry.use_tagid_for_flowid; 2107 config_info->use_tagid_for_vlan = entry.use_tagid_for_vlan; 2108 config_info->use_opcode = entry.use_opcode; 2109 config_info->roe_opcode = entry.roe_opcode; 2110 2111 exit: 2112 SOC_FUNC_RETURN; 2113 2114 } 2115 2116 int cprif_rx_rsvd4_gsm_tsn_bitmap_set(int unit, int port, uint32 queue_num, uint32 tsn_bitmap) 2117 { 2118 cprif_encap_header_entry_t entry; 2119 SOC_INIT_FUNC_DEFS; 2120 2121 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 2122 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2123 queue_num, 2124 CPRIF_MAX_NUM_OF_QUEUES)) ; 2125 return SOC_E_PARAM; 2126 } 2127 2128 cprif_encap_header_entry_t_init( &entry); 2129 2130 entry.tsn_bitmap = tsn_bitmap; 2131 2132 _SOC_IF_ERR_EXIT 2133 (cprif_drv_encap_header_entry_set(unit, port, 2134 queue_num, 2135 CPRIF_ENCAP_HEADER_FLAGS_GSM_CONFIG_SET, 2136 &entry)); 2137 exit: 2138 SOC_FUNC_RETURN; 2139 2140 } 2141 2142 int cprif_rx_rsvd4_gsm_tsn_bitmap_get(int unit, int port, uint8 queue_num, uint8* tsn_bitmap) 2143 { 2144 cprif_encap_header_entry_t entry; 2145 SOC_INIT_FUNC_DEFS; 2146 2147 2148 cprif_encap_header_entry_t_init(&entry); 2149 2150 _SOC_IF_ERR_EXIT 2151 (cprif_drv_encap_header_entry_get(unit, port, 2152 queue_num, 2153 &entry)); 2154 *tsn_bitmap = entry.tsn_bitmap; 2155 exit: 2156 SOC_FUNC_RETURN; 2157 2158 } 2159 2160 static 2161 int _cprif_sequence_number_size_validate(uint8 p_size, uint8 q_size) 2162 { 2163 2164 if ((p_size < 1) || (p_size > 32)) { 2165 LOG_CLI(("P size need to be between 1 and 32.\n")); 2166 return SOC_E_PARAM; 2167 } 2168 2169 if (q_size > p_size) { 2170 LOG_CLI(("Q size cannot exceed P size.\n")); 2171 return SOC_E_PARAM; 2172 } 2173 2174 if ((q_size+p_size)>32) { 2175 LOG_CLI(("P and Q cannot exceed 32.\n")); 2176 return SOC_E_PARAM; 2177 } 2178 return SOC_E_NONE; 2179 } 2180 2181 2182 int cprif_encap_ordering_info_entry_set(int unit, int port, 2183 uint32 index, 2184 const cprimod_encap_ordering_info_entry_t* user_entry) 2185 { 2186 cprif_encap_ordering_info_entry_t entry; 2187 uint32 p_mask; 2188 uint32 q_mask; 2189 uint32 r_mask; 2190 uint8 r_bits; 2191 SOC_INIT_FUNC_DEFS; 2192 2193 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 2194 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2195 index, 2196 CPRIF_ORDERING_INFO_TABLE_SIZE)) ; 2197 return SOC_E_PARAM; 2198 } 2199 2200 cprif_encap_ordering_info_entry_t_init( &entry); 2201 2202 cprif_drv_cprimod_to_cprif_ordering_info_type(user_entry->type, &entry.type); 2203 cprif_drv_cprimod_to_cprif_ordering_info_inc_prop(user_entry->pcnt_prop, &entry.pcnt_prop); 2204 cprif_drv_cprimod_to_cprif_ordering_info_inc_prop(user_entry->qcnt_prop, &entry.qcnt_prop); 2205 2206 entry.p_size = user_entry->pcnt_size; 2207 entry.q_size = user_entry->qcnt_size; 2208 2209 _SOC_IF_ERR_EXIT 2210 (_cprif_sequence_number_size_validate(entry.p_size, entry.q_size)); 2211 2212 p_mask = ((0x00000001<<entry.p_size)-1); 2213 q_mask = ((0x00000001 << entry.q_size)-1); 2214 r_bits = 32 - entry.p_size - entry.q_size; 2215 r_mask = ((0x00000001 << r_bits)-1); 2216 2217 entry.max = 0x00; 2218 entry.max |= (user_entry->pcnt_max & p_mask); 2219 entry.max |= ((user_entry->qcnt_max & q_mask) << entry.p_size); 2220 2221 entry.increment = 0x00; 2222 entry.increment |= (user_entry->pcnt_increment & p_mask); 2223 entry.increment |= ((user_entry->qcnt_increment & q_mask) << entry.p_size); 2224 entry.increment |= ((user_entry->seq_reserve_value & r_mask) << (entry.p_size+entry.q_size)); 2225 2226 _SOC_IF_ERR_EXIT 2227 (cprif_drv_encap_ordering_info_entry_set(unit, port, 2228 index, 2229 &entry)); 2230 2231 2232 exit: 2233 SOC_FUNC_RETURN; 2234 2235 } 2236 2237 int cprif_encap_ordering_info_entry_get(int unit, int port, uint32 index, cprimod_encap_ordering_info_entry_t* user_entry) 2238 { 2239 cprif_encap_ordering_info_entry_t entry; 2240 uint32 p_mask; 2241 uint32 q_mask; 2242 uint32 r_mask; 2243 uint8 r_bits; 2244 2245 SOC_INIT_FUNC_DEFS; 2246 2247 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 2248 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2249 index, 2250 CPRIF_ORDERING_INFO_TABLE_SIZE)) ; 2251 return SOC_E_PARAM; 2252 } 2253 2254 cprif_encap_ordering_info_entry_t_init( &entry); 2255 2256 _SOC_IF_ERR_EXIT 2257 (cprif_drv_encap_ordering_info_entry_get(unit, port, 2258 index, 2259 &entry)); 2260 2261 cprif_drv_cprif_to_cprimod_ordering_info_type(entry.type, &user_entry->type); 2262 cprif_drv_cprif_to_cprimod_ordering_info_inc_prop(entry.pcnt_prop,&user_entry->pcnt_prop); 2263 cprif_drv_cprif_to_cprimod_ordering_info_inc_prop(entry.qcnt_prop,&user_entry->qcnt_prop); 2264 2265 _SOC_IF_ERR_EXIT 2266 (_cprif_sequence_number_size_validate(entry.p_size, entry.q_size)); 2267 2268 user_entry->pcnt_size = entry.p_size; 2269 user_entry->qcnt_size = entry.q_size; 2270 2271 p_mask = (0x00000001 << entry.p_size)-1; 2272 q_mask = (0x00000001 << entry.q_size)-1; 2273 r_bits = 32 - entry.p_size - entry.q_size; 2274 r_mask = ((0x00000001 << r_bits)-1); 2275 2276 2277 user_entry->pcnt_max = entry.max & p_mask; 2278 user_entry->qcnt_max = ((entry.max >> entry.p_size) & q_mask); 2279 2280 user_entry->pcnt_increment = entry.increment & p_mask; 2281 user_entry->qcnt_increment = ((entry.increment >> entry.p_size) & q_mask); 2282 user_entry->seq_reserve_value = ((entry.increment >> (entry.p_size+entry.q_size)) & r_mask); 2283 2284 exit: 2285 SOC_FUNC_RETURN; 2286 2287 } 2288 2289 2290 2291 int cprif_decap_ordering_info_entry_set(int unit, int port, uint32 index, 2292 const cprimod_decap_ordering_info_entry_t* user_entry) 2293 { 2294 cprif_decap_ordering_info_entry_t entry; 2295 uint32 p_mask; 2296 uint32 q_mask; 2297 uint32 r_mask; 2298 uint8 r_bits; 2299 2300 SOC_INIT_FUNC_DEFS; 2301 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 2302 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2303 index, 2304 CPRIF_ORDERING_INFO_TABLE_SIZE)) ; 2305 return SOC_E_PARAM; 2306 } 2307 2308 cprif_decap_ordering_info_entry_t_init( &entry); 2309 2310 cprif_drv_cprimod_to_cprif_ordering_info_type(user_entry->type, &entry.type); 2311 2312 entry.p_size = user_entry->pcnt_size; 2313 entry.q_size = user_entry->qcnt_size; 2314 2315 _SOC_IF_ERR_EXIT 2316 (_cprif_sequence_number_size_validate(entry.p_size, entry.q_size)); 2317 2318 p_mask = ((0x00000001 << entry.p_size)-1); 2319 q_mask = ((0x00000001 << entry.q_size)-1); 2320 r_bits = 32 - entry.p_size - entry.q_size; 2321 r_mask = ((0x00000001 << r_bits)-1); 2322 2323 entry.max = 0x00; 2324 entry.max |= (user_entry->pcnt_max & p_mask); 2325 entry.max |= ((user_entry->qcnt_max & q_mask) << entry.p_size); 2326 2327 entry.bias = 0x00; 2328 entry.bias |= (user_entry->pcnt_bias & p_mask); 2329 entry.bias |= ((user_entry->qcnt_bias & q_mask) << entry.p_size); 2330 2331 entry.increment = 0x00; 2332 entry.increment |= (user_entry->pcnt_increment & p_mask); 2333 entry.increment |= ((user_entry->qcnt_increment & q_mask) << entry.p_size); 2334 entry.increment |= ((user_entry->seq_reserve_value & r_mask) << (entry.p_size+entry.q_size)); 2335 2336 entry.pcnt_inc_p2 = user_entry->pcnt_increment_p2; 2337 entry.qcnt_inc_p2 = user_entry->qcnt_increment_p2; 2338 entry.pcnt_extended = user_entry->pcnt_extended; 2339 entry.pcnt_pkt_count = user_entry->pcnt_pkt_count; 2340 entry.modulo_2 = user_entry->modulo_2; 2341 2342 entry.gsm_tsn_bitmap = user_entry->gsm_tsn_bitmap; 2343 2344 _SOC_IF_ERR_EXIT 2345 (cprif_drv_decap_ordering_info_entry_set(unit, port, 2346 index, 2347 &entry)); 2348 exit: 2349 SOC_FUNC_RETURN; 2350 2351 } 2352 2353 int cprif_decap_ordering_info_entry_get(int unit, int port, uint32 index, 2354 cprimod_decap_ordering_info_entry_t* user_entry) 2355 { 2356 cprif_decap_ordering_info_entry_t entry; 2357 uint32 p_mask; 2358 uint32 q_mask; 2359 uint32 r_mask; 2360 uint8 r_bits; 2361 2362 SOC_INIT_FUNC_DEFS; 2363 2364 if (index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 2365 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2366 index, 2367 CPRIF_ORDERING_INFO_TABLE_SIZE)) ; 2368 return SOC_E_PARAM; 2369 } 2370 2371 cprif_decap_ordering_info_entry_t_init( &entry); 2372 2373 _SOC_IF_ERR_EXIT 2374 (cprif_drv_decap_ordering_info_entry_get(unit, port, 2375 index, 2376 &entry)); 2377 cprif_drv_cprif_to_cprimod_ordering_info_type(entry.type, &user_entry->type); 2378 2379 _SOC_IF_ERR_EXIT 2380 (_cprif_sequence_number_size_validate(entry.p_size, entry.q_size)); 2381 2382 user_entry->pcnt_increment_p2 = entry.pcnt_inc_p2; 2383 user_entry->qcnt_increment_p2 = entry.qcnt_inc_p2; 2384 user_entry->pcnt_extended = entry.pcnt_extended; 2385 user_entry->pcnt_pkt_count = entry.pcnt_pkt_count; 2386 user_entry->modulo_2 = entry.modulo_2; 2387 user_entry->gsm_tsn_bitmap = entry.gsm_tsn_bitmap; 2388 2389 user_entry->pcnt_size = entry.p_size; 2390 user_entry->qcnt_size = entry.q_size; 2391 2392 p_mask = ((0x00000001 << entry.p_size)-1); 2393 q_mask = ((0x00000001 << entry.q_size)-1); 2394 r_bits = 32 - entry.p_size - entry.q_size; 2395 r_mask = ((0x00000001 << r_bits)-1); 2396 2397 2398 user_entry->pcnt_max = (entry.max & p_mask); 2399 user_entry->qcnt_max = ((entry.max >> entry.p_size) & q_mask); 2400 2401 user_entry->pcnt_bias = (entry.bias & p_mask); 2402 user_entry->qcnt_bias = ((entry.bias >> entry.p_size) & q_mask); 2403 2404 user_entry->pcnt_increment = (entry.increment & p_mask); 2405 user_entry->qcnt_increment = ((entry.increment>>entry.p_size) & q_mask); 2406 user_entry->seq_reserve_value = ((entry.increment >> (entry.p_size+entry.q_size)) & r_mask); 2407 2408 exit: 2409 SOC_FUNC_RETURN; 2410 2411 } 2412 2413 int cprif_encap_ordering_info_sequence_offset_set(int unit, int port, uint32 queue, 2414 uint32 control, 2415 cprimod_cpri_ordering_info_offset_t* offset_entry) 2416 { 2417 uint32 offset; 2418 uint32 p_mask; 2419 uint32 q_mask; 2420 2421 SOC_INIT_FUNC_DEFS; 2422 2423 if (queue >= CPRIF_MAX_NUM_OF_QUEUES) { 2424 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2425 queue, 2426 CPRIF_MAX_NUM_OF_QUEUES)) ; 2427 return SOC_E_PARAM; 2428 } 2429 2430 2431 _SOC_IF_ERR_EXIT 2432 (_cprif_sequence_number_size_validate(offset_entry->p_size, offset_entry->q_size)); 2433 2434 /* p_cnt only valid from 1-32 */ 2435 2436 p_mask = 0xFFFFFFFF; 2437 /* coverity[large_shift:FALSE] */ 2438 if (offset_entry->p_size < 32) { 2439 p_mask = ((0x00000001 << offset_entry->p_size)-1); 2440 } 2441 2442 q_mask = ((0x00000001 << offset_entry->q_size)-1); 2443 2444 offset = 0; 2445 offset |= (offset_entry->p_offset & p_mask); 2446 /* coverity[large_shift:FALSE] */ 2447 offset |= ((offset_entry->q_offset & q_mask) << offset_entry->p_size); 2448 2449 _SOC_IF_ERR_EXIT 2450 (cprif_drv_encap_queue_ordering_info_sequence_offset_set (unit, port, 2451 queue, control, 2452 offset)); 2453 2454 2455 exit: 2456 SOC_FUNC_RETURN; 2457 2458 } 2459 2460 /* caller need to provide the p_size and q_size. */ 2461 int cprif_encap_ordering_info_sequence_offset_get(int unit, int port, uint32 queue, 2462 uint8 control, 2463 uint32 pcnt_size, uint32 qcnt_size, 2464 cprimod_cpri_ordering_info_offset_t* offset_entry) 2465 { 2466 uint32 offset; 2467 uint32 p_mask; 2468 uint32 q_mask; 2469 2470 SOC_INIT_FUNC_DEFS; 2471 2472 if (queue >= CPRIF_MAX_NUM_OF_QUEUES) { 2473 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2474 queue, 2475 CPRIF_MAX_NUM_OF_QUEUES)) ; 2476 return SOC_E_PARAM; 2477 } 2478 2479 offset_entry->p_size = pcnt_size; 2480 offset_entry->q_size = qcnt_size; 2481 2482 _SOC_IF_ERR_EXIT(_cprif_sequence_number_size_validate(offset_entry->p_size, 2483 offset_entry->q_size)); 2484 2485 p_mask = 0xFFFFFFFF; 2486 /* coverity[large_shift:FALSE] */ 2487 if (offset_entry->p_size < 32) { 2488 p_mask = ((0x00000001 << offset_entry->p_size)-1); 2489 } 2490 q_mask = ((0x00000001 << offset_entry->q_size)-1); 2491 2492 _SOC_IF_ERR_EXIT 2493 (cprif_drv_encap_queue_ordering_info_sequence_offset_get (unit, port, 2494 queue, control, 2495 &offset)); 2496 offset_entry->p_offset = offset & p_mask; 2497 /* coverity[large_shift:FALSE] */ 2498 offset_entry->q_offset = ((offset >> offset_entry->p_size) & q_mask); 2499 exit: 2500 SOC_FUNC_RETURN; 2501 2502 } 2503 2504 2505 int cprif_decap_ordering_info_sequence_offset_set(int unit, int port, uint32 queue, 2506 cprimod_cpri_ordering_info_offset_t* offset_entry) 2507 { 2508 uint32 offset; 2509 uint32 p_mask; 2510 uint32 q_mask; 2511 SOC_INIT_FUNC_DEFS; 2512 2513 if (queue >= CPRIF_MAX_NUM_OF_QUEUES) { 2514 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2515 queue, 2516 CPRIF_MAX_NUM_OF_QUEUES)) ; 2517 return SOC_E_PARAM; 2518 } 2519 2520 _SOC_IF_ERR_EXIT 2521 (_cprif_sequence_number_size_validate(offset_entry->p_size, offset_entry->q_size)); 2522 2523 p_mask = 0xFFFFFFFF; 2524 if (offset_entry->p_size < 32) { 2525 p_mask = ((0x00000001 << offset_entry->p_size)-1); 2526 } 2527 2528 q_mask = ((0x00000001 << offset_entry->q_size)-1); 2529 2530 offset = 0; 2531 offset |= (offset_entry->p_offset & p_mask); 2532 offset |= ((offset_entry->q_offset & q_mask) << offset_entry->q_size); 2533 2534 _SOC_IF_ERR_EXIT 2535 (cprif_drv_decap_queue_ordering_info_sequence_offset_set (unit, port, 2536 queue, 2537 offset)); 2538 2539 2540 exit: 2541 SOC_FUNC_RETURN; 2542 2543 } 2544 2545 /* caller need to provide the p_size and q_size. */ 2546 int cprif_decap_ordering_info_sequence_offset_get(int unit, int port, uint32 queue, 2547 uint32 pcnt_size, uint32 qcnt_size, 2548 cprimod_cpri_ordering_info_offset_t* offset_entry) 2549 { 2550 uint32 offset; 2551 uint32 p_mask; 2552 uint32 q_mask; 2553 2554 SOC_INIT_FUNC_DEFS; 2555 2556 if (queue >= CPRIF_MAX_NUM_OF_QUEUES) { 2557 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2558 queue, 2559 CPRIF_MAX_NUM_OF_QUEUES)) ; 2560 return SOC_E_PARAM; 2561 } 2562 2563 offset_entry->p_offset = 0; 2564 offset_entry->q_offset = 0; 2565 offset_entry->p_size = pcnt_size; 2566 offset_entry->q_size = qcnt_size; 2567 2568 _SOC_IF_ERR_EXIT(_cprif_sequence_number_size_validate( 2569 offset_entry->p_size, offset_entry->q_size)); 2570 2571 p_mask = 0xFFFFFFFF; 2572 if (offset_entry->p_size < 32) { 2573 p_mask = ((0x00000001 << offset_entry->p_size)-1); 2574 } 2575 q_mask = ((0x00000001 << offset_entry->q_size)-1); 2576 2577 _SOC_IF_ERR_EXIT 2578 (cprif_drv_decap_queue_ordering_info_sequence_offset_get (unit, port, 2579 queue, 2580 &offset)); 2581 offset_entry->p_offset = offset & p_mask; 2582 if (offset_entry->p_size < 32) { 2583 offset_entry->q_offset = ((offset >> offset_entry->p_size) & q_mask); 2584 } 2585 2586 exit: 2587 SOC_FUNC_RETURN; 2588 2589 } 2590 2591 2592 static 2593 int _cprif_pack_mac_addr(cprimod_mac_addr_t addr, uint64 *mac_addr) 2594 { 2595 int loop; 2596 uint64 tmp_addr; 2597 uint8 shift_bits; 2598 2599 /* packing addr bytes */ 2600 COMPILER_64_ZERO(*mac_addr); 2601 shift_bits = 0; 2602 for(loop = 0; loop < CPRIF_NUM_BYTES_IN_MAC_ADDR; loop++) { 2603 2604 /* 2605 * Change shift bit formula when the packing byte order 2606 * need to be reverse. (loop * 8). Change both pack and unpack. 2607 */ 2608 shift_bits = (CPRIF_NUM_BYTES_IN_MAC_ADDR - 1 - loop)*8; 2609 COMPILER_64_SET(tmp_addr, 0, (uint32) addr[loop]); 2610 COMPILER_64_SHL(tmp_addr, shift_bits); 2611 COMPILER_64_OR(*mac_addr, tmp_addr); 2612 } 2613 2614 return SOC_E_NONE; 2615 } 2616 2617 int _cprif_unpack_mac_addr(uint64 mac_addr, cprimod_mac_addr_t addr) 2618 { 2619 int loop; 2620 uint64 tmp_addr; 2621 uint8 shift_bits; 2622 2623 /* unpacking addr bytes */ 2624 COMPILER_64_ZERO(tmp_addr); 2625 for(loop = 0; loop < CPRIF_NUM_BYTES_IN_MAC_ADDR; loop++) { 2626 2627 shift_bits = (CPRIF_NUM_BYTES_IN_MAC_ADDR - 1 - loop)*8; 2628 COMPILER_64_COPY(tmp_addr, mac_addr); 2629 COMPILER_64_SHR(tmp_addr, shift_bits); 2630 addr[loop] = COMPILER_64_LO(tmp_addr) & 0xff; 2631 } 2632 return SOC_E_NONE; 2633 } 2634 2635 int cprif_encap_mac_da_entry_set(int unit, int port, uint32 index, cprimod_mac_addr_t addr) 2636 { 2637 uint64 mac_addr; 2638 2639 SOC_INIT_FUNC_DEFS; 2640 2641 if (index >= CPRIF_MAC_ADDR_TABLE_SIZE) { 2642 CPRIMOD_DEBUG_ERROR(("Index %d is out of range > than %d", 2643 index, 2644 CPRIF_MAC_ADDR_TABLE_SIZE)) ; 2645 return SOC_E_PARAM; 2646 } 2647 2648 COMPILER_64_ZERO(mac_addr); 2649 2650 /* packing addr bytes */ 2651 _cprif_pack_mac_addr(addr,&mac_addr); 2652 2653 _SOC_IF_ERR_EXIT 2654 (cprif_drv_encap_mac_da_set(unit, port, 2655 index, 2656 mac_addr)); 2657 2658 exit: 2659 SOC_FUNC_RETURN; 2660 2661 } 2662 2663 int cprif_encap_mac_da_entry_get(int unit, int port, uint32 index, cprimod_mac_addr_t addr) 2664 { 2665 uint64 mac_addr; 2666 2667 SOC_INIT_FUNC_DEFS; 2668 2669 if (index >= CPRIF_MAC_ADDR_TABLE_SIZE) { 2670 CPRIMOD_DEBUG_ERROR(("Index %d is out of range > than %d", 2671 index, 2672 CPRIF_MAC_ADDR_TABLE_SIZE)) ; 2673 return SOC_E_PARAM; 2674 } 2675 2676 COMPILER_64_ZERO(mac_addr); 2677 _SOC_IF_ERR_EXIT 2678 (cprif_drv_encap_mac_da_get(unit, port, 2679 index, 2680 &mac_addr)); 2681 2682 _cprif_unpack_mac_addr(mac_addr, addr); 2683 2684 exit: 2685 SOC_FUNC_RETURN; 2686 2687 } 2688 2689 2690 int cprif_encap_mac_sa_entry_set(int unit, int port, uint32 index, cprimod_mac_addr_t addr) 2691 { 2692 uint64 mac_addr; 2693 SOC_INIT_FUNC_DEFS; 2694 2695 if (index >= CPRIF_MAC_ADDR_TABLE_SIZE) { 2696 CPRIMOD_DEBUG_ERROR(("Index %d is out of range > than %d", 2697 index, 2698 CPRIF_MAC_ADDR_TABLE_SIZE)) ; 2699 return SOC_E_PARAM; 2700 } 2701 2702 COMPILER_64_ZERO(mac_addr); 2703 2704 /* packing addr bytes */ 2705 _cprif_pack_mac_addr(addr,&mac_addr); 2706 2707 _SOC_IF_ERR_EXIT 2708 (cprif_drv_encap_mac_sa_set(unit, port, 2709 index, 2710 mac_addr)); 2711 2712 exit: 2713 SOC_FUNC_RETURN; 2714 2715 } 2716 2717 int cprif_encap_mac_sa_entry_get(int unit, int port, uint32 index, cprimod_mac_addr_t addr) 2718 { 2719 uint64 mac_addr; 2720 2721 SOC_INIT_FUNC_DEFS; 2722 2723 if (index >= CPRIF_MAC_ADDR_TABLE_SIZE) { 2724 CPRIMOD_DEBUG_ERROR(("Index %d is out of range > than %d", 2725 index, 2726 CPRIF_MAC_ADDR_TABLE_SIZE)) ; 2727 return SOC_E_PARAM; 2728 } 2729 2730 COMPILER_64_ZERO(mac_addr); 2731 _SOC_IF_ERR_EXIT 2732 (cprif_drv_encap_mac_sa_get(unit, port, 2733 index, 2734 &mac_addr)); 2735 2736 _cprif_unpack_mac_addr(mac_addr, addr); 2737 2738 exit: 2739 SOC_FUNC_RETURN; 2740 2741 } 2742 2743 int cprif_encap_vlan_id_entry_set(int unit, int port, cprimod_vlan_table_id_t table_id, uint32 index, uint32 vlan_id) 2744 { 2745 uint8 table_num; 2746 SOC_INIT_FUNC_DEFS; 2747 2748 if (index >= CPRIF_VLAN_ID_TABLE_SIZE) { 2749 CPRIMOD_DEBUG_ERROR(("Index %d is out of range > than %d", 2750 index, 2751 CPRIF_VLAN_ID_TABLE_SIZE)); 2752 return SOC_E_PARAM; 2753 } 2754 2755 if (table_id == cprimodVlanTable0) { 2756 table_num = 0; 2757 } else { 2758 table_num = 1; 2759 } 2760 2761 _SOC_IF_ERR_EXIT 2762 (cprif_drv_encap_vlan_entry_set(unit, port, 2763 table_num, 2764 index, 2765 vlan_id)); 2766 2767 2768 2769 exit: 2770 SOC_FUNC_RETURN; 2771 2772 } 2773 2774 int cprif_encap_vlan_id_entry_get(int unit, int port, cprimod_vlan_table_id_t table_id, uint32 index, uint32* vlan_id) 2775 { 2776 uint8 table_num; 2777 SOC_INIT_FUNC_DEFS; 2778 2779 if (index >= CPRIF_VLAN_ID_TABLE_SIZE) { 2780 CPRIMOD_DEBUG_ERROR(("Index %d is out of range > than %d", 2781 index, 2782 CPRIF_VLAN_ID_TABLE_SIZE)); 2783 return SOC_E_PARAM; 2784 } 2785 2786 if (table_id == cprimodVlanTable0) { 2787 table_num = 0; 2788 } else { 2789 table_num = 1; 2790 } 2791 2792 _SOC_IF_ERR_EXIT 2793 (cprif_drv_encap_vlan_entry_get(unit, port, 2794 table_num, 2795 index, 2796 vlan_id)); 2797 exit: 2798 SOC_FUNC_RETURN; 2799 2800 } 2801 2802 2803 static 2804 void _cprif_cprimod_to_cprif_decap_ethtype_id(cprimod_ethertype_t type_id, uint8 *int_type) 2805 { 2806 switch (type_id) { 2807 case cprimodEthertypeRoe: 2808 *int_type = CPRIF_DECAP_ROE_ETHTYPE; 2809 break; 2810 2811 case cprimodEthertypeFast: 2812 *int_type = CPRIF_DECAP_FAST_ETH_ETHTYPE; 2813 break; 2814 2815 case cprimodEthertypeVlan: 2816 *int_type = CPRIF_DECAP_VLAN_TAGGED_ETHTYPE; 2817 break; 2818 2819 case cprimodEthertypeQinQ: 2820 *int_type = CPRIF_DECAP_VLAN_QINQ_ETHTYPE; 2821 break; 2822 2823 default: 2824 *int_type = CPRIF_DECAP_ROE_ETHTYPE; 2825 break; 2826 2827 } 2828 } 2829 2830 int cprif_decap_ethertype_config_set(int unit, int port, cprimod_ethertype_t type_id, uint16 ethertype) 2831 { 2832 uint8 int_type; 2833 SOC_INIT_FUNC_DEFS; 2834 2835 _cprif_cprimod_to_cprif_decap_ethtype_id(type_id, &int_type); 2836 2837 _SOC_IF_ERR_EXIT 2838 (cprif_drv_decap_vlan_ethtype_set(unit, port, 2839 int_type, 2840 ethertype)); 2841 exit: 2842 SOC_FUNC_RETURN; 2843 2844 } 2845 2846 int cprif_decap_ethertype_config_get(int unit, int port, cprimod_ethertype_t type_id, uint16* ethertype) 2847 { 2848 uint8 int_type; 2849 SOC_INIT_FUNC_DEFS; 2850 2851 _cprif_cprimod_to_cprif_decap_ethtype_id(type_id, &int_type); 2852 2853 _SOC_IF_ERR_EXIT 2854 (cprif_drv_decap_vlan_ethtype_get(unit, port, 2855 int_type, 2856 ethertype)); 2857 2858 exit: 2859 SOC_FUNC_RETURN; 2860 2861 } 2862 2863 static 2864 void _cprif_cprimod_to_cprif_encap_ethtype_id(cprimod_ethertype_t type_id, uint8 *int_type) 2865 { 2866 switch (type_id) { 2867 case cprimodEthertypeRoe: 2868 *int_type = CPRIF_ETHTYPE_ROE_ETHTYPE_0; 2869 break; 2870 2871 case cprimodEthertypeRoe1: 2872 *int_type = CPRIF_ETHTYPE_ROE_ETHTYPE_1; 2873 break; 2874 2875 case cprimodEthertypeVlan: 2876 *int_type = CPRIF_ETHTYPE_VLAN_TAGGED; 2877 break; 2878 2879 case cprimodEthertypeQinQ: 2880 *int_type = CPRIF_ETHTYPE_VLAN_QINQ; 2881 break; 2882 2883 default: 2884 *int_type = CPRIF_ETHTYPE_ROE_ETHTYPE_0; 2885 break; 2886 2887 } 2888 } 2889 2890 2891 int cprif_encap_ethertype_config_set(int unit, int port, cprimod_ethertype_t type_id, uint16 ethertype) 2892 { 2893 uint8 int_type; 2894 SOC_INIT_FUNC_DEFS; 2895 2896 _cprif_cprimod_to_cprif_encap_ethtype_id(type_id, &int_type); 2897 2898 _SOC_IF_ERR_EXIT 2899 (cprif_drv_encap_vlan_ethtype_set(unit, port, 2900 int_type, 2901 ethertype)); 2902 2903 exit: 2904 SOC_FUNC_RETURN; 2905 } 2906 2907 int cprif_encap_ethertype_config_get(int unit, int port, cprimod_ethertype_t type_id, uint16* ethertype) 2908 { 2909 uint8 int_type; 2910 SOC_INIT_FUNC_DEFS; 2911 2912 _cprif_cprimod_to_cprif_encap_ethtype_id(type_id, &int_type); 2913 2914 _SOC_IF_ERR_EXIT 2915 (cprif_drv_encap_vlan_ethtype_get(unit, port, 2916 int_type, 2917 ethertype)); 2918 exit: 2919 SOC_FUNC_RETURN; 2920 } 2921 2922 int cprif_encap_memory_clear(int unit, int port, int queue_num) 2923 { 2924 SOC_INIT_FUNC_DEFS; 2925 _SOC_IF_ERR_EXIT(cprif_drv_encap_queue_sts_clear(unit, port, 2926 queue_num)); 2927 _SOC_IF_ERR_EXIT(cprif_drv_encap_ordering_info_sts_clear(unit, port, 2928 queue_num)); 2929 exit: 2930 SOC_FUNC_RETURN; 2931 } 2932 2933 2934 int cprif_cpri_rx_framer_state_clear(int unit, int port, int queue_num) 2935 { 2936 SOC_INIT_FUNC_DEFS; 2937 /* only for data framer state queue_num <64 for data axc*/ 2938 if (queue_num < 64) { 2939 _SOC_IF_ERR_EXIT(cprif_drv_container_parser_mapp_state_tab_clear(unit, 2940 port, queue_num)); 2941 _SOC_IF_ERR_EXIT(cprif_drv_iq_pak_buff_state_tab_clear(unit, port, 2942 queue_num)); 2943 _SOC_IF_ERR_EXIT(cprif_drv_iq_pak_buff_payld_tab_clear(unit, port, 2944 queue_num)); 2945 } 2946 exit: 2947 SOC_FUNC_RETURN; 2948 2949 } 2950 2951 /* 2952 * Before clearing queue from decap the flows should be cleared. This will 2953 * be done at higher level. Keeping the flow and removing the queue may result 2954 * in unpredictable behavior 2955 */ 2956 2957 int cprif_decap_memory_clear(int unit, int port, int queue_num) 2958 { 2959 SOC_INIT_FUNC_DEFS; 2960 2961 _SOC_IF_ERR_EXIT(cprif_drv_decap_queue_state_tbl_clear(unit, port, 2962 queue_num)); 2963 exit: 2964 SOC_FUNC_RETURN; 2965 2966 } 2967 2968 int cprif_cpri_tx_framer_state_clear(int unit, int port, int queue_num) 2969 { 2970 SOC_INIT_FUNC_DEFS; 2971 /* only for data framer state queue_num <64 for data axc*/ 2972 if (queue_num < 64) { 2973 _SOC_IF_ERR_EXIT(cprif_drv_iq_unpsk_buff_state_tbl_clear(unit, port, 2974 queue_num)); 2975 _SOC_IF_ERR_EXIT(cprif_drv_cont_assembly_map_state_tbl_clear(unit, port, 2976 queue_num)); 2977 } 2978 exit: 2979 SOC_FUNC_RETURN; 2980 2981 } 2982 2983 #define CPRIF_DECAP_CLS_OPTION_USE_QUEUE_NUM 0 2984 #define CPRIF_DECAP_CLS_OPTION_USE_FLOW_ID_TO_QUEUE 1 2985 #define CPRIF_DECAP_CLS_OPTION_USE_USE_OPCODE_QUEUE 2 2986 2987 int cprif_decap_flow_classification_config_set(int unit, int port, 2988 uint8 subtype, 2989 uint32 queue_num, 2990 cprimod_cls_option_t cls_option, 2991 cprimod_cls_flow_type_t flow_type) 2992 { 2993 uint32 option=0; 2994 uint32 type=0; 2995 SOC_INIT_FUNC_DEFS; 2996 2997 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 2998 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 2999 queue_num, 3000 CPRIF_MAX_NUM_OF_QUEUES)) ; 3001 return SOC_E_PARAM; 3002 } 3003 3004 switch (cls_option) { 3005 case cprimodClsOptionUseQueueNum: 3006 option = CPRIF_DECAP_CLS_OPTION_USE_QUEUE_NUM; 3007 break; 3008 3009 case cprimodClsOptionUseFlowIdToQueue: 3010 option = CPRIF_DECAP_CLS_OPTION_USE_FLOW_ID_TO_QUEUE; 3011 break; 3012 3013 case cprimodClsOptionUseOpcodeToQueue: 3014 option = CPRIF_DECAP_CLS_OPTION_USE_USE_OPCODE_QUEUE; 3015 break; 3016 3017 default: 3018 break; 3019 } 3020 3021 switch (flow_type) { 3022 case cprimodClsFlowTypeData: 3023 type = CPRIF_DECAP_CLS_FLOW_TYPE_DATA; 3024 break; 3025 3026 case cprimodClsFlowTypeDataWithExt: /* Not Suppoprted */ 3027 type = CPRIF_DECAP_CLS_FLOW_TYPE_DATA_WITH_EXT; 3028 break; 3029 3030 case cprimodClsFlowTypeCtrlWithOpcode: 3031 type = CPRIF_DECAP_CLS_FLOW_TYPE_CTRL_WITH_OPCODE; 3032 break; 3033 3034 case cprimodClsFlowTypeCtrl: 3035 type = CPRIF_DECAP_CLS_FLOW_TYPE_CTRL; 3036 break; 3037 default: 3038 break; 3039 } 3040 3041 3042 _SOC_IF_ERR_EXIT 3043 (cprif_drv_decap_flow_classification_entry_set (unit, port, 3044 subtype, 3045 queue_num, 3046 option, 3047 type)); 3048 3049 3050 exit: 3051 SOC_FUNC_RETURN; 3052 3053 } 3054 3055 int cprif_decap_flow_classification_config_get(int unit, int port, 3056 uint8 subtype, 3057 uint32* queue_num, 3058 cprimod_cls_option_t* cls_option, 3059 cprimod_cls_flow_type_t* flow_type) 3060 { 3061 uint32 option; 3062 uint32 type; 3063 3064 SOC_INIT_FUNC_DEFS; 3065 3066 _SOC_IF_ERR_EXIT 3067 (cprif_drv_decap_flow_classification_entry_get(unit, port, 3068 subtype, 3069 queue_num, 3070 &option, 3071 &type)); 3072 switch (option) { 3073 case CPRIF_DECAP_CLS_OPTION_USE_QUEUE_NUM: 3074 *cls_option = cprimodClsOptionUseQueueNum; 3075 break; 3076 3077 case CPRIF_DECAP_CLS_OPTION_USE_FLOW_ID_TO_QUEUE: 3078 *cls_option = cprimodClsOptionUseFlowIdToQueue; 3079 break; 3080 3081 case CPRIF_DECAP_CLS_OPTION_USE_USE_OPCODE_QUEUE: 3082 *cls_option = cprimodClsOptionUseOpcodeToQueue; 3083 break; 3084 3085 default: 3086 break; 3087 } 3088 3089 switch (type) { 3090 case CPRIF_DECAP_CLS_FLOW_TYPE_DATA: 3091 *flow_type = cprimodClsFlowTypeData; 3092 break; 3093 3094 case CPRIF_DECAP_CLS_FLOW_TYPE_DATA_WITH_EXT: /* Not Suppoprted */ 3095 *flow_type = cprimodClsFlowTypeDataWithExt; 3096 break; 3097 3098 case CPRIF_DECAP_CLS_FLOW_TYPE_CTRL_WITH_OPCODE: 3099 *flow_type = cprimodClsFlowTypeCtrlWithOpcode; 3100 break; 3101 3102 case CPRIF_DECAP_CLS_FLOW_TYPE_CTRL: 3103 *flow_type = cprimodClsFlowTypeCtrl; 3104 break; 3105 default: 3106 break; 3107 } 3108 3109 exit: 3110 SOC_FUNC_RETURN; 3111 3112 } 3113 3114 int cprif_decap_flow_to_queue_mapping_set(int unit, int port, uint32 flow_id, uint32 queue_num) 3115 { 3116 uint8 queue; 3117 SOC_INIT_FUNC_DEFS; 3118 3119 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 3120 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 3121 queue_num, 3122 CPRIF_MAX_NUM_OF_QUEUES)) ; 3123 return SOC_E_PARAM; 3124 } 3125 3126 queue = queue_num; 3127 _SOC_IF_ERR_EXIT 3128 (cprif_drv_decap_flow_to_queue_map_set(unit, port, 3129 flow_id, 3130 queue)); 3131 exit: 3132 SOC_FUNC_RETURN; 3133 3134 } 3135 3136 int cprif_decap_flow_to_queue_mapping_get(int unit, int port, uint32 flow_id, uint32* queue_num) 3137 { 3138 3139 SOC_INIT_FUNC_DEFS; 3140 3141 _SOC_IF_ERR_EXIT 3142 (cprif_drv_decap_flow_to_queue_map_get(unit, port, 3143 flow_id, 3144 queue_num)); 3145 exit: 3146 SOC_FUNC_RETURN; 3147 3148 } 3149 3150 int cprif_decap_queue_to_ordering_info_index_mapping_set(int unit, int port, uint32 queue_num, uint32 ordering_info_index) 3151 { 3152 SOC_INIT_FUNC_DEFS; 3153 3154 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 3155 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 3156 queue_num, 3157 CPRIF_MAX_NUM_OF_QUEUES)) ; 3158 return SOC_E_PARAM; 3159 } 3160 3161 if (ordering_info_index >= CPRIF_ORDERING_INFO_TABLE_SIZE) { 3162 CPRIMOD_DEBUG_ERROR(("Decap Ordering info only have %d entries, %d is out of range", 3163 CPRIF_ORDERING_INFO_TABLE_SIZE, 3164 ordering_info_index)); 3165 return SOC_E_PARAM; 3166 } 3167 3168 _SOC_IF_ERR_EXIT 3169 (cprif_drv_decap_queue_to_ordering_info_index_set(unit, port, 3170 queue_num, 3171 ordering_info_index)); 3172 exit: 3173 SOC_FUNC_RETURN; 3174 3175 } 3176 3177 int cprif_decap_queue_to_ordering_info_index_mapping_get(int unit, int port, uint32 queue_num, uint32* ordering_info_index) 3178 { 3179 3180 SOC_INIT_FUNC_DEFS; 3181 3182 if (queue_num >= CPRIF_MAX_NUM_OF_QUEUES) { 3183 CPRIMOD_DEBUG_ERROR(("Queue %d is out of range > than %d", 3184 queue_num, 3185 CPRIF_MAX_NUM_OF_QUEUES)) ; 3186 return SOC_E_PARAM; 3187 } 3188 _SOC_IF_ERR_EXIT 3189 (cprif_drv_decap_queue_to_ordering_info_index_get(unit, port, 3190 queue_num, 3191 ordering_info_index)); 3192 exit: 3193 SOC_FUNC_RETURN; 3194 3195 } 3196 3197 int cprif_tx_framer_tgen_tick_set(int unit, int port, uint32 divider, uint32 basic_frame_tick, uint32 tick_bitmap, uint32 tick_bitmap_size) 3198 { 3199 SOC_INIT_FUNC_DEFS; 3200 3201 _SOC_IF_ERR_EXIT 3202 (cprif_drv_tx_framer_tgen_tick_set(unit, port, 3203 divider, 3204 basic_frame_tick, 3205 tick_bitmap, 3206 tick_bitmap_size)); 3207 3208 exit: 3209 SOC_FUNC_RETURN; 3210 3211 } 3212 3213 int cprif_tx_framer_tgen_tick_get(int unit, int port, uint32* divider, uint32* basic_frame_tick, uint32* tick_bitmap, uint32* tick_bitmap_size) 3214 { 3215 SOC_INIT_FUNC_DEFS; 3216 3217 _SOC_IF_ERR_EXIT 3218 (cprif_drv_tx_framer_tgen_tick_get(unit, port, 3219 divider, 3220 basic_frame_tick, 3221 tick_bitmap, 3222 tick_bitmap_size)); 3223 exit: 3224 SOC_FUNC_RETURN; 3225 3226 } 3227 3228 int cprif_tx_framer_tgen_enable(int unit, int port, uint8 enable) 3229 { 3230 SOC_INIT_FUNC_DEFS; 3231 3232 _SOC_IF_ERR_EXIT 3233 (cprif_drv_tx_framer_tgen_enable(unit, port, enable)); 3234 3235 exit: 3236 SOC_FUNC_RETURN; 3237 3238 } 3239 3240 3241 int cprif_tx_framer_tgen_offset_set(int unit, int port, uint64 timestamp_offset) 3242 { 3243 SOC_INIT_FUNC_DEFS; 3244 3245 _SOC_IF_ERR_EXIT 3246 (cprif_drv_tx_framer_tgen_offset_set(unit, port,timestamp_offset)); 3247 3248 3249 3250 exit: 3251 SOC_FUNC_RETURN; 3252 3253 } 3254 3255 int cprif_tx_framer_tgen_offset_get(int unit, int port, uint64* timestamp_offset) 3256 { 3257 SOC_INIT_FUNC_DEFS; 3258 3259 _SOC_IF_ERR_EXIT 3260 (cprif_drv_tx_framer_tgen_offset_get(unit, port,timestamp_offset)); 3261 3262 exit: 3263 SOC_FUNC_RETURN; 3264 3265 } 3266 3267 int cprif_tx_framer_tgen_next_bfn_config_set(int unit, int port, uint32 tgen_bfn) 3268 { 3269 SOC_INIT_FUNC_DEFS; 3270 3271 _SOC_IF_ERR_EXIT 3272 (cprif_drv_tx_framer_tgen_next_bfn_config_set(unit, port, tgen_bfn)); 3273 3274 exit: 3275 SOC_FUNC_RETURN; 3276 3277 } 3278 3279 int cprif_tx_framer_tgen_next_bfn_config_get(int unit, int port, uint32* tgen_bfn) 3280 { 3281 SOC_INIT_FUNC_DEFS; 3282 3283 _SOC_IF_ERR_EXIT 3284 (cprif_drv_tx_framer_tgen_next_bfn_config_get(unit, port, tgen_bfn)); 3285 3286 exit: 3287 SOC_FUNC_RETURN; 3288 3289 } 3290 3291 int cprif_tx_framer_tgen_next_hfn_config_set(int unit, int port, uint32 tgen_hfn) 3292 { 3293 SOC_INIT_FUNC_DEFS; 3294 3295 _SOC_IF_ERR_EXIT 3296 (cprif_drv_tx_framer_tgen_next_hfn_config_set(unit, port, tgen_hfn)); 3297 3298 exit: 3299 SOC_FUNC_RETURN; 3300 3301 } 3302 3303 int cprif_tx_framer_tgen_next_hfn_config_get(int unit, int port, uint32* tgen_hfn) 3304 { 3305 SOC_INIT_FUNC_DEFS; 3306 3307 _SOC_IF_ERR_EXIT 3308 (cprif_drv_tx_framer_tgen_next_hfn_config_get(unit, port, tgen_hfn)); 3309 exit: 3310 SOC_FUNC_RETURN; 3311 3312 } 3313 3314 int cprif_tx_framer_next_bfn_get(int unit, int port, uint32* tgen_bfn) 3315 { 3316 SOC_INIT_FUNC_DEFS; 3317 3318 _SOC_IF_ERR_EXIT 3319 (cprif_drv_tx_framer_next_bfn_get(unit, port, tgen_bfn)); 3320 exit: 3321 SOC_FUNC_RETURN; 3322 3323 } 3324 3325 int cprif_tx_framer_next_hfn_get(int unit, int port, uint32* tgen_hfn) 3326 { 3327 SOC_INIT_FUNC_DEFS; 3328 3329 _SOC_IF_ERR_EXIT 3330 (cprif_drv_tx_framer_next_hfn_get(unit, port, tgen_hfn)); 3331 exit: 3332 SOC_FUNC_RETURN; 3333 } 3334 3335 int cprif_tx_framer_tgen_select_counter_set(int unit, int port, cprimod_tgen_counter_select_t tgen_counter_select) 3336 { 3337 uint8 bfn_hfn; 3338 SOC_INIT_FUNC_DEFS; 3339 3340 if (tgen_counter_select == cprimodTgenCounterSelectBfn) { 3341 bfn_hfn = CPRIF_TX_TGEN_USE_BFN; 3342 } else { 3343 bfn_hfn = CPRIF_TX_TGEN_USE_HFN; 3344 } 3345 3346 _SOC_IF_ERR_EXIT 3347 (cprif_drv_tx_framer_tgen_select_counter_set(unit,port,bfn_hfn)); 3348 exit: 3349 SOC_FUNC_RETURN; 3350 3351 } 3352 3353 int cprif_tx_framer_tgen_select_counter_get(int unit, int port, cprimod_tgen_counter_select_t* tgen_counter_select) 3354 { 3355 uint8 bfn_hfn; 3356 SOC_INIT_FUNC_DEFS; 3357 3358 bfn_hfn = 0; 3359 3360 _SOC_IF_ERR_EXIT 3361 (cprif_drv_tx_framer_tgen_select_counter_get(unit,port,&bfn_hfn)); 3362 3363 if (bfn_hfn == CPRIF_TX_TGEN_USE_BFN) { 3364 *tgen_counter_select = cprimodTgenCounterSelectBfn; 3365 } else { 3366 *tgen_counter_select = cprimodTgenCounterSelectHfn; 3367 } 3368 3369 exit: 3370 SOC_FUNC_RETURN; 3371 3372 } 3373 3374 3375 int cprif_header_compare_entry_add(int unit, int port, 3376 cprimod_header_compare_entry_t* entry) 3377 { 3378 cprimod_header_compare_entry_t local_entry; 3379 int index; 3380 3381 cprimod_header_compare_entry_t_init( &local_entry); 3382 for(index=0; index < CPRIF_HEADER_COMPARE_TABLE_SIZE;index++) { 3383 SOC_IF_ERROR_RETURN 3384 (cprif_drv_rsvd4_header_compare_entry_get(unit, port, 3385 index, 3386 &local_entry)); 3387 /* 3388 * if empty spot is found, add the entry. 3389 */ 3390 if (local_entry.valid == 0) { 3391 return(cprif_drv_rsvd4_header_compare_entry_set(unit, port, 3392 index, 3393 entry)); 3394 } 3395 } 3396 LOG_CLI(("Header Compare Table No Empty Space Found.\n")); 3397 return SOC_E_PARAM; 3398 } 3399 3400 3401 int cprif_header_compare_entry_delete(int unit, int port, 3402 cprimod_header_compare_entry_t* entry) 3403 { 3404 cprimod_header_compare_entry_t local_entry; 3405 int index; 3406 3407 cprimod_header_compare_entry_t_init( &local_entry); 3408 3409 for(index=0; index < CPRIF_HEADER_COMPARE_TABLE_SIZE;index++) { 3410 SOC_IF_ERROR_RETURN 3411 (cprif_drv_rsvd4_header_compare_entry_get(unit, port, 3412 index, 3413 &local_entry)); 3414 /* 3415 * if valid entry, compare to see if match. 3416 */ 3417 if (local_entry.valid == 1) { 3418 3419 /* 3420 * If matched entry found, invalidate and get out. 3421 */ 3422 3423 if ((local_entry.match_data == entry->match_data) && 3424 (local_entry.mask == entry->mask) && 3425 (local_entry.flow_id == entry->flow_id) && 3426 (local_entry.flow_type == entry->flow_type)) { 3427 3428 cprimod_header_compare_entry_t_init( &local_entry); 3429 local_entry.valid = 0; 3430 return(cprif_drv_rsvd4_header_compare_entry_set(unit, port, 3431 index, 3432 &local_entry)); 3433 } 3434 } 3435 } 3436 LOG_CLI(("No Matching Header Compare Entry Found to Delete .\n")); 3437 return SOC_E_PARAM; 3438 } 3439 3440 int cprif_header_compare_entry_for_flow_delete(int unit, int port, uint8 flow_id, cprimod_flow_type_t flow_type) 3441 { 3442 cprimod_header_compare_entry_t local_entry; 3443 int index; 3444 3445 cprimod_header_compare_entry_t_init( &local_entry); 3446 3447 for(index=0; index < CPRIF_HEADER_COMPARE_TABLE_SIZE;index++) { 3448 SOC_IF_ERROR_RETURN 3449 (cprif_drv_rsvd4_header_compare_entry_get(unit, port, 3450 index, 3451 &local_entry)); 3452 /* 3453 * if valid entry, compare to see if match. 3454 */ 3455 if (local_entry.valid == 1) { 3456 3457 /* 3458 * If matched entry found, invalidate and get out. 3459 */ 3460 3461 if ((local_entry.flow_id == flow_id) && 3462 (local_entry.flow_type == flow_type)) { 3463 3464 cprimod_header_compare_entry_t_init( &local_entry); 3465 local_entry.valid = 0; 3466 return(cprif_drv_rsvd4_header_compare_entry_set(unit, port, 3467 index, 3468 &local_entry)); 3469 } 3470 } 3471 } 3472 LOG_CLI(("No Matching Header Compare Entry Found to Delete .\n")); 3473 return SOC_E_PARAM; 3474 } 3475 3476 int cprif_modulo_rule_entry_set(int unit, int port, 3477 uint8 modulo_rule_num, 3478 cprimod_transmission_rule_type_t modulo_rule_type, 3479 cprimod_modulo_rule_entry_t* modulo_rule) 3480 { 3481 uint8 ctrl_rule; 3482 SOC_INIT_FUNC_DEFS; 3483 3484 if (modulo_rule_type == cprimodTxRuleTypeCtrl) { 3485 ctrl_rule = CPRIF_MODULO_RULE_USE_CTRL_RULE; 3486 if (modulo_rule_num >= CPRIF_MODULO_RULE_CTRL_RULE_SIZE) { 3487 CPRIMOD_DEBUG_ERROR(("Rule Num %d is out of range > than %d", 3488 modulo_rule_num, 3489 CPRIF_MODULO_RULE_CTRL_RULE_SIZE)); 3490 return SOC_E_PARAM; 3491 } 3492 3493 } else { 3494 ctrl_rule = CPRIF_MODULO_RULE_USE_DATA_RULE; 3495 if (modulo_rule_num >= CPRIF_MODULO_RULE_DATA_RULE_SIZE) { 3496 CPRIMOD_DEBUG_ERROR(("Rule Num %d is out of range > than %d", 3497 modulo_rule_num, 3498 CPRIF_MODULO_RULE_DATA_RULE_SIZE)); 3499 return SOC_E_PARAM; 3500 } 3501 } 3502 3503 _SOC_IF_ERR_EXIT 3504 (cprif_drv_rsvd4_modulo_rule_entry_set(unit, port, 3505 modulo_rule_num, 3506 ctrl_rule, 3507 modulo_rule)); 3508 exit: 3509 SOC_FUNC_RETURN; 3510 3511 } 3512 3513 int cprif_modulo_rule_entry_get(int unit, int port, 3514 uint8 modulo_rule_num, 3515 cprimod_transmission_rule_type_t modulo_rule_type, 3516 cprimod_modulo_rule_entry_t* modulo_rule) 3517 { 3518 uint8 ctrl_rule; 3519 SOC_INIT_FUNC_DEFS; 3520 3521 if (modulo_rule_type == cprimodTxRuleTypeCtrl) { 3522 ctrl_rule = CPRIF_MODULO_RULE_USE_CTRL_RULE; 3523 if (modulo_rule_num >= CPRIF_MODULO_RULE_CTRL_RULE_SIZE) { 3524 CPRIMOD_DEBUG_ERROR(("Rule Num %d is out of range > than %d", 3525 modulo_rule_num, 3526 CPRIF_MODULO_RULE_CTRL_RULE_SIZE)); 3527 return SOC_E_PARAM; 3528 } 3529 3530 } else { 3531 ctrl_rule = CPRIF_MODULO_RULE_USE_DATA_RULE; 3532 if (modulo_rule_num >= CPRIF_MODULO_RULE_DATA_RULE_SIZE) { 3533 CPRIMOD_DEBUG_ERROR(("Rule Num %d is out of range > than %d", 3534 modulo_rule_num, 3535 CPRIF_MODULO_RULE_DATA_RULE_SIZE)); 3536 return SOC_E_PARAM; 3537 } 3538 } 3539 3540 3541 _SOC_IF_ERR_EXIT 3542 (cprif_drv_rsvd4_modulo_rule_entry_get(unit, port, 3543 modulo_rule_num, 3544 ctrl_rule, 3545 modulo_rule)); 3546 exit: 3547 SOC_FUNC_RETURN; 3548 } 3549 3550 int cprif_dual_bitmap_rule_entry_set(int unit, int port, 3551 uint8 dbm_rule_num, 3552 cprimod_dbm_rule_entry_t* dbm_rule) 3553 { 3554 SOC_INIT_FUNC_DEFS; 3555 3556 if (dbm_rule_num >= CPRIF_DBM_RULE_PROFILE_TABLE_SIZE) { 3557 CPRIMOD_DEBUG_ERROR(("DBM Rule Number %d is out of range > than %d", 3558 dbm_rule_num, 3559 CPRIF_DBM_RULE_PROFILE_TABLE_SIZE)); 3560 return SOC_E_PARAM; 3561 } 3562 3563 3564 _SOC_IF_ERR_EXIT 3565 (cprif_drv_rsvd4_dual_bitmap_rule_entry_set(unit, port, 3566 dbm_rule_num, 3567 dbm_rule)); 3568 exit: 3569 SOC_FUNC_RETURN; 3570 3571 } 3572 3573 int cprif_dual_bitmap_rule_entry_get(int unit, int port, 3574 uint8 dbm_rule_num, 3575 cprimod_dbm_rule_entry_t* dbm_rule) 3576 { 3577 3578 SOC_INIT_FUNC_DEFS; 3579 3580 if (dbm_rule_num >= CPRIF_DBM_RULE_PROFILE_TABLE_SIZE) { 3581 CPRIMOD_DEBUG_ERROR(("DBM Rule Number %d is out of range > than %d", 3582 dbm_rule_num, 3583 CPRIF_DBM_RULE_PROFILE_TABLE_SIZE)); 3584 return SOC_E_PARAM; 3585 } 3586 3587 _SOC_IF_ERR_EXIT 3588 (cprif_drv_rsvd4_dual_bitmap_rule_entry_get(unit, port, 3589 dbm_rule_num, 3590 dbm_rule)); 3591 exit: 3592 SOC_FUNC_RETURN; 3593 3594 } 3595 3596 int cprif_secondary_dual_bitmap_rule_entry_set(int unit, int port, 3597 uint8 dbm_rule_num, 3598 cprimod_secondary_dbm_rule_entry_t* dbm_rule) 3599 { 3600 SOC_INIT_FUNC_DEFS; 3601 3602 if (dbm_rule_num >= CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE) { 3603 CPRIMOD_DEBUG_ERROR(("Secondary DBM Rule Number %d is out of range > than %d", 3604 dbm_rule_num, 3605 CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE)); 3606 return SOC_E_PARAM; 3607 } 3608 3609 3610 _SOC_IF_ERR_EXIT 3611 (cprif_drv_rsvd4_secondary_dual_bitmap_rule_entry_set(unit, port, 3612 dbm_rule_num, 3613 dbm_rule)); 3614 exit: 3615 SOC_FUNC_RETURN; 3616 3617 } 3618 3619 int cprif_secondary_dual_bitmap_rule_entry_get(int unit, int port, 3620 uint8 dbm_rule_num, 3621 cprimod_secondary_dbm_rule_entry_t* dbm_rule) 3622 { 3623 3624 SOC_INIT_FUNC_DEFS; 3625 3626 if (dbm_rule_num >= CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE) { 3627 CPRIMOD_DEBUG_ERROR(("Secondary DBM Rule Number %d is out of range > than %d", 3628 dbm_rule_num, 3629 CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE)); 3630 return SOC_E_PARAM; 3631 } 3632 3633 _SOC_IF_ERR_EXIT 3634 (cprif_drv_rsvd4_secondary_dual_bitmap_rule_entry_get(unit, port, 3635 dbm_rule_num, 3636 dbm_rule)); 3637 exit: 3638 SOC_FUNC_RETURN; 3639 3640 } 3641 3642 int cprif_dbm_position_entry_set(int unit, int port, uint8 index, 3643 cprimod_dbm_pos_table_entry_t* pos_entry) 3644 { 3645 SOC_INIT_FUNC_DEFS; 3646 3647 if (index >= CPRIF_DBM_POSITION_TABLE_SIZE) { 3648 CPRIMOD_DEBUG_ERROR(("DBM Position Table Index %d is out of range > than %d", 3649 index, 3650 CPRIF_DBM_POSITION_TABLE_SIZE)); 3651 return SOC_E_PARAM; 3652 } 3653 3654 _SOC_IF_ERR_EXIT 3655 (cprif_drv_rsvd4_dbm_position_entry_set(unit, port, index, pos_entry)); 3656 exit: 3657 SOC_FUNC_RETURN; 3658 3659 } 3660 3661 int cprif_dbm_position_entry_get(int unit, int port, uint8 index, 3662 cprimod_dbm_pos_table_entry_t* pos_entry) 3663 { 3664 SOC_INIT_FUNC_DEFS; 3665 if (index >= CPRIF_DBM_POSITION_TABLE_SIZE) { 3666 CPRIMOD_DEBUG_ERROR(("DBM Position Table Index %d is out of range > than %d", 3667 index, 3668 CPRIF_DBM_POSITION_TABLE_SIZE)); 3669 return SOC_E_PARAM; 3670 } 3671 3672 _SOC_IF_ERR_EXIT 3673 (cprif_drv_rsvd4_dbm_position_entry_get(unit, port, index, pos_entry)); 3674 exit: 3675 SOC_FUNC_RETURN; 3676 3677 } 3678 3679 int cprif_fast_clk_bit_time_period_set(int unit, int port, uint32 bit_time_period) 3680 { 3681 SOC_INIT_FUNC_DEFS; 3682 _SOC_IF_ERR_EXIT( 3683 cprif_drv_fast_clk_bit_time_period_set(unit, port, bit_time_period)); 3684 3685 exit: 3686 SOC_FUNC_RETURN; 3687 3688 } 3689 3690 int cprif_fast_clk_bit_time_period_get(int unit, int port, uint32* bit_time_period) 3691 { 3692 SOC_INIT_FUNC_DEFS; 3693 _SOC_IF_ERR_EXIT( 3694 cprif_drv_fast_clk_bit_time_period_get(unit, port, bit_time_period)); 3695 3696 exit: 3697 SOC_FUNC_RETURN; 3698 3699 } 3700 3701 3702 3703 static 3704 int _cprif_port_rx_speed_set(int unit, int port, const phymod_phy_access_t* phy, 3705 cprimod_port_speed_t speed) 3706 { 3707 uint32 wd_len; 3708 SOC_INIT_FUNC_DEFS; 3709 3710 SOC_IF_ERROR_RETURN(cprif_drv_cpri_rxpcs_speed_set(unit, port, phy, 3711 speed)); 3712 3713 if (speed <=cprimodSpd9830p4) { 3714 SOC_IF_ERROR_RETURN 3715 (cprif_drv_ingress_traffic_rate_set(unit, port, CPRIF_INGRESS_RATE_ONE_THIRD)); 3716 } else { 3717 SOC_IF_ERROR_RETURN 3718 (cprif_drv_ingress_traffic_rate_set(unit, port, CPRIF_INGRESS_RATE_TWO_THIRD)); 3719 } 3720 3721 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_clear(unit, port)); 3722 wd_len = _cprif_from_speed_towd_len(speed); 3723 /* Adding AXC for control word */ 3724 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_add(unit, port, 255, 3725 0, wd_len)); 3726 3727 exit: 3728 SOC_FUNC_RETURN; 3729 } 3730 3731 int cprif_port_rx_interface_config_set(int unit, int port, const phymod_phy_access_t* phy, 3732 const cprimod_port_interface_config_t* config) 3733 { 3734 SOC_INIT_FUNC_DEFS; 3735 3736 if (config->speed >= cprimodSpdCount) { 3737 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed not supported for CPRI")); 3738 } 3739 _SOC_IF_ERR_EXIT(_cprif_port_rx_speed_set(unit, port, phy, config->speed)); 3740 3741 exit: 3742 SOC_FUNC_RETURN; 3743 } 3744 3745 int cprif_port_rx_interface_config_get(int unit, int port, 3746 cprimod_port_interface_config_t* config) 3747 { 3748 cprimod_port_rsvd4_speed_mult_t rsvd4_speed; 3749 SOC_INIT_FUNC_DEFS; 3750 3751 SOC_IF_ERROR_RETURN(cprif_drv_rxcpri_port_type_get(unit, port, 3752 &(config->interface))); 3753 if (config->interface == cprimodRsvd4) { 3754 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rxpcs_speed_get(unit, port, 3755 &rsvd4_speed)); 3756 switch(rsvd4_speed) { 3757 case cprimodRsvd4SpdMult4X: 3758 config->speed = cprimodSpd3072p0; 3759 break; 3760 case cprimodRsvd4SpdMult8X: 3761 config->speed = cprimodSpd6144p0; 3762 break; 3763 default: 3764 config->speed = cprimodSpd3072p0; 3765 break; 3766 } 3767 } else { 3768 SOC_IF_ERROR_RETURN(cprif_drv_cpri_rxpcs_speed_get(unit, port, 3769 &(config->speed))); 3770 } 3771 3772 SOC_FUNC_RETURN; 3773 } 3774 3775 static 3776 int _cprif_port_tx_speed_set(int unit, int port, const phymod_phy_access_t* phy, 3777 cprimod_port_speed_t speed) 3778 { 3779 uint32 wd_len; 3780 SOC_INIT_FUNC_DEFS; 3781 3782 SOC_IF_ERROR_RETURN(cprif_drv_cpri_txpcs_speed_set(unit, port, phy, 3783 speed)); 3784 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_clear(unit, port)); 3785 wd_len = _cprif_from_speed_towd_len(speed); 3786 /* Adding AXC for control word */ 3787 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_add(unit, port, 255, 3788 0, wd_len)); 3789 3790 exit: 3791 SOC_FUNC_RETURN; 3792 } 3793 3794 int cprif_port_tx_interface_config_set(int unit, int port, const phymod_phy_access_t* phy, 3795 const cprimod_port_interface_config_t* config) 3796 { 3797 SOC_INIT_FUNC_DEFS; 3798 3799 if (config->speed >= cprimodSpdCount) { 3800 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed not supported for CPRI")); 3801 } 3802 SOC_IF_ERROR_RETURN(_cprif_port_tx_speed_set(unit, port, phy, 3803 config->speed)); 3804 3805 exit: 3806 SOC_FUNC_RETURN; 3807 } 3808 3809 int cprif_port_tx_interface_config_get(int unit, int port, 3810 cprimod_port_interface_config_t* config) 3811 { 3812 cprimod_port_rsvd4_speed_mult_t rsvd4_speed; 3813 SOC_INIT_FUNC_DEFS; 3814 3815 SOC_IF_ERROR_RETURN(cprif_drv_txcpri_port_type_get(unit, port, 3816 &(config->interface))); 3817 if (config->interface == cprimodRsvd4) { 3818 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_txpcs_speed_get(unit, port, 3819 &rsvd4_speed)); 3820 switch(rsvd4_speed) { 3821 case cprimodRsvd4SpdMult4X: 3822 config->speed = cprimodSpd3072p0; 3823 break; 3824 case cprimodRsvd4SpdMult8X: 3825 config->speed = cprimodSpd6144p0; 3826 break; 3827 default: 3828 config->speed = cprimodSpd3072p0; 3829 break; 3830 } 3831 } else { 3832 SOC_IF_ERROR_RETURN(cprif_drv_cpri_txpcs_speed_get(unit, port, 3833 &(config->speed))); 3834 } 3835 3836 SOC_FUNC_RETURN; 3837 } 3838 3839 int cprif_port_rsvd4_rx_interface_config_set(int unit, int port, const phymod_phy_access_t* phy, 3840 const cprimod_port_rsvd4_config_t* config) { 3841 SOC_INIT_FUNC_DEFS; 3842 3843 if (config->speed >= cprimodRsvd4SpdMultCount) { 3844 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed not supported for CPRI")); 3845 } 3846 /* coverity[mixed_enums:FALSE] */ 3847 SOC_IF_ERROR_RETURN(cprif_drv_cpri_rxpcs_speed_set(unit, port, phy, 3848 config->speed)); 3849 exit: 3850 SOC_FUNC_RETURN; 3851 3852 } 3853 3854 int cprif_port_rsvd4_tx_interface_config_set(int unit, int port, const phymod_phy_access_t* phy, 3855 const cprimod_port_rsvd4_config_t* config) { 3856 SOC_INIT_FUNC_DEFS; 3857 3858 if (config->speed >= cprimodRsvd4SpdMultCount) { 3859 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed not supported for CPRI")); 3860 } 3861 /* coverity[mixed_enums:FALSE] */ 3862 SOC_IF_ERROR_RETURN(cprif_drv_cpri_txpcs_speed_set(unit, port, phy, 3863 config->speed)); 3864 3865 exit: 3866 SOC_FUNC_RETURN; 3867 } 3868 3869 int cprif_port_rsvd4_tx_interface_config_get(int unit, int port, 3870 cprimod_port_rsvd4_config_t* config) { 3871 SOC_INIT_FUNC_DEFS; 3872 3873 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_txpcs_speed_get(unit, port, 3874 &(config->speed))); 3875 3876 SOC_FUNC_RETURN; 3877 } 3878 3879 int cprif_port_rx_frame_optional_config_set(int unit, int port, 3880 cprimod_rx_config_field_t field, int value) 3881 { 3882 SOC_INIT_FUNC_DEFS; 3883 3884 SOC_IF_ERROR_RETURN(cprif_drv_rx_frame_optional_config_set( 3885 unit, port, field, value)); 3886 SOC_FUNC_RETURN; 3887 } 3888 3889 int cprif_port_rx_frame_optional_config_get(int unit, int port, 3890 cprimod_rx_config_field_t field, int* value) 3891 { 3892 SOC_INIT_FUNC_DEFS; 3893 3894 SOC_IF_ERROR_RETURN(cprif_drv_rx_frame_optional_config_get( 3895 unit, port, field, value)); 3896 3897 SOC_FUNC_RETURN; 3898 } 3899 3900 3901 int cprif_port_tx_frame_optional_config_set(int unit, int port, 3902 cprimod_tx_config_field_t field, uint32 value) 3903 { 3904 SOC_INIT_FUNC_DEFS; 3905 3906 SOC_IF_ERROR_RETURN(cprif_drv_tx_frame_optional_config_set( 3907 unit, port, field, value)); 3908 SOC_FUNC_RETURN; 3909 } 3910 3911 int cprif_port_tx_frame_optional_config_get(int unit, int port, 3912 cprimod_tx_config_field_t field, uint32* value) 3913 { 3914 SOC_INIT_FUNC_DEFS; 3915 3916 SOC_IF_ERROR_RETURN(cprif_drv_tx_frame_optional_config_get( 3917 unit, port, field, value)); 3918 3919 SOC_FUNC_RETURN; 3920 } 3921 3922 3923 int cprif_port_rsvd4_rx_frame_optional_config_set(int unit, int port, 3924 cprimod_rsvd4_rx_config_field_t field, int value) 3925 { 3926 SOC_INIT_FUNC_DEFS; 3927 3928 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rx_frame_optional_config_set( 3929 unit, port, field, value)); 3930 3931 SOC_FUNC_RETURN; 3932 } 3933 3934 int cprif_port_rsvd4_rx_frame_optional_config_get(int unit, int port, 3935 cprimod_rsvd4_rx_config_field_t field, int* value) 3936 { 3937 SOC_INIT_FUNC_DEFS; 3938 3939 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rx_frame_optional_config_get( 3940 unit, port, field, value)); 3941 3942 SOC_FUNC_RETURN; 3943 } 3944 3945 3946 int _cprif_port_rsvd4_basic_frame_table_set (int unit, int port, cprimod_direction_t dir) 3947 { 3948 cprif_bfa_bfp_table_entry_t table_entry; 3949 uint8 active_table; 3950 uint8 standby_table; 3951 int index = 0; 3952 SOC_INIT_FUNC_DEFS; 3953 3954 if (dir == CPRIMOD_DIR_RX) { 3955 /* add following 3956 *entry num axcc_id rsrv_cnt data_cnt Description 3957 *0 0 0 24 extract 24 bits of hdr 3958 *1 1 0 128 extract 128 bits of pld 3959 */ 3960 3961 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_clear(unit, port)); 3962 3963 _SOC_IF_ERR_EXIT 3964 (cprif_drv_basic_frame_parser_active_table_get(unit, port, &active_table)); 3965 3966 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 3967 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 3968 } else { 3969 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 3970 } 3971 3972 table_entry.axc_id = 0; 3973 table_entry.rsrv_bit_cnt = 0; 3974 table_entry.data_bit_cnt = CPRIMOD_RSVD4_HEADER_SIZE; 3975 3976 _SOC_IF_ERR_EXIT 3977 (cprif_drv_basic_frame_entry_set(unit, port, 3978 standby_table, 3979 CPRIMOD_DIR_RX, 3980 0, 3981 &table_entry)); 3982 table_entry.axc_id = 1; 3983 table_entry.rsrv_bit_cnt = 0; 3984 table_entry.data_bit_cnt = CPRIMOD_RSVD4_PAYLOAD_SIZE; 3985 3986 _SOC_IF_ERR_EXIT 3987 (cprif_drv_basic_frame_entry_set(unit, port, 3988 standby_table, 3989 CPRIMOD_DIR_RX, 3990 1, 3991 &table_entry)); 3992 3993 _SOC_IF_ERR_EXIT 3994 (cprif_drv_basic_frame_parser_table_num_entries_set(unit, port, 3995 standby_table, 3996 2)); 3997 3998 3999 } else if (dir == CPRIMOD_DIR_TX) { 4000 /*entry num axcc_id rsrv_cnt data_cnt Description 4001 *0 0 0 24 extract 24 bits of hdr 4002 *1 1 0 128 extract 128 bits of pld 4003 *2 0 0 24 extract 24 bits of hdr 4004 *3 1 0 128 extract 128 bits of pld 4005 * ............................... 4006 *40 0 0 24 extract 24 bits of hdr 4007 *41 1 0 128 extract 128 bits of pld 4008 * 4009 * i axcc_id start bit datasize 4010 * 4011 * 0 0 0*(24+128) = 0 24 4012 * 0 1 0*(24+128)+24 = 24 128 4013 * 1 0 1*(24+128) = 152 24 4014 * 1 1 1*(24+128)+24 = 176 128 4015 * 2 0 2*(24+128) = 304 24 4016 * 2 1 2*(24+128)+24 = 328 128 4017 */ 4018 4019 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_clear(unit, port)); 4020 4021 _SOC_IF_ERR_EXIT 4022 (cprif_drv_basic_frame_assembly_active_table_get(unit, port, &active_table)); 4023 4024 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 4025 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 4026 } else { 4027 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 4028 } 4029 4030 for(index = 0; index < 21; index++) { 4031 table_entry.axc_id = 0; 4032 table_entry.rsrv_bit_cnt = 0; 4033 table_entry.data_bit_cnt = CPRIMOD_RSVD4_HEADER_SIZE; 4034 4035 _SOC_IF_ERR_EXIT 4036 (cprif_drv_basic_frame_entry_set(unit, port, 4037 standby_table, 4038 CPRIMOD_DIR_TX, 4039 index*2, 4040 &table_entry)); 4041 table_entry.axc_id = 1; 4042 table_entry.rsrv_bit_cnt = 0; 4043 table_entry.data_bit_cnt = CPRIMOD_RSVD4_PAYLOAD_SIZE; 4044 4045 _SOC_IF_ERR_EXIT 4046 (cprif_drv_basic_frame_entry_set(unit, port, 4047 standby_table, 4048 CPRIMOD_DIR_TX, 4049 index*2+1, 4050 &table_entry)); 4051 4052 } 4053 4054 table_entry.axc_id = 1; 4055 table_entry.rsrv_bit_cnt = 8; 4056 table_entry.data_bit_cnt = 0; 4057 4058 _SOC_IF_ERR_EXIT 4059 (cprif_drv_basic_frame_entry_set(unit, port, 4060 standby_table, 4061 CPRIMOD_DIR_TX, 4062 42, 4063 &table_entry)); 4064 4065 _SOC_IF_ERR_EXIT 4066 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, 4067 standby_table, 4068 43)); 4069 } 4070 exit: 4071 SOC_FUNC_RETURN; 4072 } 4073 4074 int cprif_port_rsvd4_rx_speed_set(int unit, int port, const phymod_phy_access_t* phy, cprimod_port_rsvd4_speed_mult_t speed) 4075 { 4076 SOC_INIT_FUNC_DEFS; 4077 4078 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rxpcs_speed_set(unit, port, phy, speed)); 4079 SOC_IF_ERROR_RETURN 4080 (cprif_drv_ingress_traffic_rate_set(unit, port, CPRIF_INGRESS_RATE_ONE_THIRD)); 4081 4082 SOC_IF_ERROR_RETURN 4083 (_cprif_port_rsvd4_basic_frame_table_set (unit, port, CPRIMOD_DIR_RX)); 4084 4085 SOC_FUNC_RETURN; 4086 } 4087 4088 int cprif_port_rsvd4_rx_speed_get(int unit, int port, cprimod_port_rsvd4_speed_mult_t* speed) 4089 { 4090 SOC_INIT_FUNC_DEFS; 4091 4092 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rxpcs_speed_get(unit, port, speed)); 4093 4094 SOC_FUNC_RETURN; 4095 4096 } 4097 4098 int cprif_port_rsvd4_tx_speed_set(int unit, int port, const phymod_phy_access_t* phy, cprimod_port_rsvd4_speed_mult_t speed) 4099 { 4100 uint32 divider, basic_frame_tick; 4101 SOC_INIT_FUNC_DEFS; 4102 4103 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_txpcs_speed_set(unit, port, phy, speed)); 4104 4105 if (speed == cprimodRsvd4SpdMult4X) { 4106 divider = 2; 4107 basic_frame_tick = 200; 4108 } else if (speed == cprimodRsvd4SpdMult8X) { 4109 divider = 1; 4110 basic_frame_tick = 100; 4111 } else { 4112 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Speed is not supported for rsvd4")); 4113 } 4114 4115 SOC_IF_ERROR_RETURN 4116 (_cprif_port_rsvd4_basic_frame_table_set (unit, port, CPRIMOD_DIR_TX)); 4117 4118 SOC_IF_ERROR_RETURN(cprif_tx_framer_tgen_tick_set(unit, port, divider, basic_frame_tick, 0, 0)); 4119 exit: 4120 SOC_FUNC_RETURN; 4121 4122 } 4123 4124 int cprif_port_rsvd4_tx_speed_get(int unit, int port, cprimod_port_rsvd4_speed_mult_t* speed) 4125 { 4126 SOC_INIT_FUNC_DEFS; 4127 4128 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_txpcs_speed_get(unit, port, speed)); 4129 4130 SOC_FUNC_RETURN; 4131 4132 } 4133 4134 int cprif_port_rsvd4_rx_fsm_state_set(int unit, int port, 4135 cprimod_rsvd4_rx_fsm_state_t state) 4136 { 4137 SOC_INIT_FUNC_DEFS; 4138 4139 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rx_fsm_state_set( 4140 unit, port, state)); 4141 4142 SOC_FUNC_RETURN; 4143 } 4144 4145 4146 int cprif_port_rsvd4_rx_fsm_state_get(int unit, int port, 4147 cprimod_rsvd4_rx_fsm_state_t* state) 4148 { 4149 SOC_INIT_FUNC_DEFS; 4150 4151 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rx_fsm_state_get( 4152 unit, port, state)); 4153 4154 SOC_FUNC_RETURN; 4155 } 4156 4157 4158 int cprif_port_rsvd4_rx_overide_set(int unit, int port, 4159 cprimod_rsvd4_rx_overide_t parameter, int enable, int value) 4160 { 4161 SOC_INIT_FUNC_DEFS; 4162 4163 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rx_overide_set( 4164 unit, port, parameter, enable, value)); 4165 4166 SOC_FUNC_RETURN; 4167 4168 } 4169 4170 int cprif_port_rsvd4_rx_overide_get(int unit, int port, 4171 cprimod_rsvd4_rx_overide_t parameter, int* enable, int* value) 4172 { 4173 SOC_INIT_FUNC_DEFS; 4174 4175 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rx_overide_get( 4176 unit, port, parameter, enable, value)); 4177 4178 SOC_FUNC_RETURN; 4179 4180 } 4181 4182 4183 int cprif_port_rsvd4_tx_frame_optional_config_set(int unit, int port, 4184 cprimod_rsvd4_tx_config_field_t field, int value) 4185 { 4186 SOC_INIT_FUNC_DEFS; 4187 4188 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_frame_optional_config_set( 4189 unit, port, field, value)); 4190 4191 SOC_FUNC_RETURN; 4192 4193 } 4194 4195 int cprif_port_rsvd4_tx_frame_optional_config_get(int unit, int port, 4196 cprimod_rsvd4_tx_config_field_t field, int* value) 4197 { 4198 SOC_INIT_FUNC_DEFS; 4199 4200 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_frame_optional_config_get( 4201 unit, port, field, value)); 4202 4203 SOC_FUNC_RETURN; 4204 4205 } 4206 4207 4208 int cprif_port_rsvd4_tx_fsm_state_set(int unit, int port, 4209 cprimod_rsvd4_tx_fsm_state_t state) 4210 { 4211 SOC_INIT_FUNC_DEFS; 4212 4213 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_fsm_state_set( 4214 unit, port, state)); 4215 SOC_FUNC_RETURN; 4216 4217 } 4218 4219 4220 int cprif_port_rsvd4_tx_fsm_state_get(int unit, int port, 4221 cprimod_rsvd4_tx_fsm_state_t *state) 4222 { 4223 SOC_INIT_FUNC_DEFS; 4224 4225 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_fsm_state_get( 4226 unit, port, state)); 4227 SOC_FUNC_RETURN; 4228 4229 } 4230 4231 4232 int cprif_port_rsvd4_tx_overide_set(int unit, int port, 4233 cprimod_rsvd4_tx_overide_t parameter, int enable, int value) 4234 { 4235 SOC_INIT_FUNC_DEFS; 4236 4237 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_overide_set( 4238 unit, port, parameter, enable, value)); 4239 4240 SOC_FUNC_RETURN; 4241 4242 } 4243 4244 int cprif_port_rsvd4_tx_overide_get(int unit, int port, 4245 cprimod_rsvd4_tx_overide_t parameter, int* enable, int* value) 4246 { 4247 SOC_INIT_FUNC_DEFS; 4248 4249 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_overide_get( 4250 unit, port, parameter, enable, value)); 4251 4252 SOC_FUNC_RETURN; 4253 4254 } 4255 4256 int cprif_port_rx_pcs_status_get(int unit, int port, 4257 cprimod_rx_pcs_status_t status, uint32* value) 4258 { 4259 SOC_INIT_FUNC_DEFS; 4260 4261 SOC_IF_ERROR_RETURN(cprif_drv_rx_pcs_status_get( 4262 unit, port, status, value)); 4263 SOC_FUNC_RETURN; 4264 4265 } 4266 4267 int cprif_port_pmd_status_get(int unit, int port, cprimod_pmd_port_status_t status, uint32* value) 4268 { 4269 SOC_INIT_FUNC_DEFS; 4270 4271 SOC_IF_ERROR_RETURN(cprif_drv_pmd_port_status_get( unit, port, status, value)); 4272 4273 SOC_FUNC_RETURN; 4274 } 4275 4276 STATIC 4277 int _cpri_core_firmware_load(const phymod_core_access_t* core, cprimod_firmware_load_method_t load_method, cprimod_firmware_loader_f fw_loader) 4278 { 4279 SOC_INIT_FUNC_DEFS; 4280 /* 4281 * Temporarily supress the DEADCODE until this forced phymodFirmwareLoadMethodInternal 4282 * is removed. 4283 */ 4284 4285 /* coverity[dead_error_condition:FALSE] */ 4286 load_method = phymodFirmwareLoadMethodInternal; 4287 /* coverity[dead_error_condition:FALSE] */ 4288 switch(load_method){ 4289 case phymodFirmwareLoadMethodInternal: 4290 _SOC_IF_ERR_EXIT(falcon2_monterey_ucode_mdio_load(&core->access, falcon_dpll_ucode, falcon_dpll_ucode_len)); 4291 break; 4292 /* coverity[dead_error_condition:FALSE] */ 4293 case phymodFirmwareLoadMethodExternal: 4294 PHYMOD_NULL_CHECK(fw_loader); 4295 _SOC_IF_ERR_EXIT(falcon2_monterey_ucode_init(&core->access)); 4296 _SOC_IF_ERR_EXIT 4297 (falcon2_monterey_pram_firmware_enable(&core->access, 1, 0)); 4298 _SOC_IF_ERR_EXIT(fw_loader(core, falcon_dpll_ucode_len, falcon_dpll_ucode)); 4299 _SOC_IF_ERR_EXIT 4300 (falcon2_monterey_pram_firmware_enable(&core->access, 0, 0)); 4301 break; 4302 /* coverity[dead_error_condition:FALSE] */ 4303 case phymodFirmwareLoadMethodNone: 4304 break; 4305 default: 4306 _SOC_EXIT_WITH_ERR(SOC_E_CONFIG, (_PHYMOD_MSG("illegal fw load method %u"), load_method)); 4307 } 4308 4309 exit: 4310 SOC_FUNC_RETURN; 4311 } 4312 4313 /* cpri_or_pmd == 1 => cpri lane swap 4314 cpri_or_pmd == 0 => PMD lane swap */ 4315 STATIC 4316 int _cpri_core_lane_map_set(int unit, int port, 4317 const phymod_core_access_t* core, 4318 const phymod_lane_map_t* lane_map, int cpri_or_pmd) 4319 { 4320 uint32_t lane; 4321 uint32_t map_lane; 4322 uint8_t pmd_tx_addr[4], pmd_rx_addr[4]; 4323 SOC_INIT_FUNC_DEFS; 4324 4325 if (lane_map->num_of_lanes != CPRI_NOF_LANES_IN_CORE){ 4326 return PHYMOD_E_CONFIG; 4327 } 4328 for (lane = 0; lane < CPRI_NOF_LANES_IN_CORE; lane++){ 4329 if ((lane_map->lane_map_tx[lane] >= CPRI_NOF_LANES_IN_CORE)|| 4330 (lane_map->lane_map_rx[lane] >= CPRI_NOF_LANES_IN_CORE)){ 4331 return SOC_E_PARAM; 4332 } 4333 } 4334 /* PMD lane addr is based on PCS logical to physical mapping */ 4335 for (lane = 0; lane < CPRI_NOF_LANES_IN_CORE; lane++){ 4336 pmd_tx_addr[(lane_map->lane_map_tx[lane] & 0xf)] = lane; 4337 pmd_rx_addr[(lane_map->lane_map_rx[lane] & 0xf)] = lane; 4338 } 4339 4340 if(cpri_or_pmd) { 4341 for (lane = 0; lane < CPRI_NOF_LANES_IN_CORE; lane++){ 4342 map_lane = lane_map->lane_map_tx[lane]; 4343 SOC_IF_ERROR_RETURN 4344 (cprif_drv_lane_swap_set(unit, port, lane, CPRIMOD_DIR_TX, map_lane)); 4345 map_lane = lane_map->lane_map_rx[lane]; 4346 SOC_IF_ERROR_RETURN 4347 (cprif_drv_lane_swap_set(unit, port, lane, CPRIMOD_DIR_RX, map_lane)); 4348 } 4349 } else { 4350 _SOC_IF_ERR_EXIT 4351 (falcon2_monterey_map_lanes(&core->access, CPRI_NOF_LANES_IN_CORE, pmd_tx_addr, pmd_rx_addr)); 4352 } 4353 4354 exit: 4355 SOC_FUNC_RETURN; 4356 } 4357 4358 STATIC 4359 int _cpri_firmware_core_config_set(const phymod_phy_access_t* phy, phymod_firmware_core_config_t fw_core_config) 4360 { 4361 struct falcon2_monterey_uc_core_config_st serdes_firmware_core_config; 4362 SOC_INIT_FUNC_DEFS; 4363 4364 sal_memset(&serdes_firmware_core_config, 0, sizeof(serdes_firmware_core_config)); 4365 serdes_firmware_core_config.field.core_cfg_from_pcs = fw_core_config.CoreConfigFromPCS; 4366 serdes_firmware_core_config.field.vco_rate = fw_core_config.VcoRate; 4367 serdes_firmware_core_config.field.disable_write_pll_iqp = fw_core_config.disable_write_pll_iqp; 4368 _SOC_IF_ERR_EXIT(falcon2_monterey_set_uc_core_config(&phy->access, serdes_firmware_core_config)); 4369 4370 exit: 4371 SOC_FUNC_RETURN; 4372 } 4373 4374 STATIC 4375 int _cpri_pmd_pll_configure (phymod_access_t* pc, int pll_div, phymod_ref_clk_t ref_clock) 4376 { 4377 enum falcon2_monterey_pll_enum pll_cfg; 4378 SOC_INIT_FUNC_DEFS; 4379 4380 switch (pll_div) { 4381 case phymod_TSCF_PLL_DIV160: 4382 pll_cfg = FALCON2_MONTEREY_pll_div_160x_vco2; 4383 break; 4384 case phymod_TSCF_PLL_DIV165: 4385 pll_cfg = FALCON2_MONTEREY_pll_div_165x_refc122; 4386 break; 4387 case phymod_TSCF_PLL_DIV198: 4388 pll_cfg = FALCON2_MONTEREY_pll_div_198x; 4389 break; 4390 case phymod_TSCF_PLL_DIV200: 4391 pll_cfg = FALCON2_MONTEREY_pll_div_200x; 4392 break; 4393 default: 4394 pll_cfg = FALCON2_MONTEREY_pll_div_160x_vco2; 4395 break; 4396 } 4397 4398 _SOC_IF_ERR_EXIT 4399 (falcon2_monterey_configure_pll(pc, pll_cfg)); 4400 4401 exit: 4402 SOC_FUNC_RETURN; 4403 } 4404 4405 /* 4406 * Caculate vco rate in MHz. 4407 */ 4408 STATIC 4409 int _cpri_pmd_pll_to_vco_rate(phymod_access_t* pc, int pll_div, phymod_ref_clk_t ref_clk, uint32_t* vco_rate) 4410 { 4411 uint32_t pll_multiplier = 0; 4412 4413 switch (pll_div){ 4414 case phymod_TSCF_PLL_DIV160: 4415 pll_multiplier = 160; 4416 break; 4417 case phymod_TSCF_PLL_DIV165: 4418 pll_multiplier = 165; 4419 break; 4420 case phymod_TSCF_PLL_DIV198: 4421 pll_multiplier = 198; 4422 break; 4423 case phymod_TSCF_PLL_DIV200: 4424 pll_multiplier = 200; 4425 break; 4426 default: 4427 pll_multiplier = 160; 4428 break; 4429 } 4430 *vco_rate = pll_multiplier * 122 + pll_multiplier *88/100; 4431 4432 return SOC_E_NONE; 4433 } 4434 4435 /* 4436 * get fast clock bit time period based on VCO. 4437 */ 4438 STATIC 4439 int _cpri_fast_clock_bit_time_period_get (int pll_div, uint32_t* bit_time_period) 4440 { 4441 4442 switch (pll_div){ 4443 case phymod_TSCF_PLL_DIV160: 4444 *bit_time_period = 0x683; 4445 break; 4446 case phymod_TSCF_PLL_DIV165: 4447 *bit_time_period = 0x650; 4448 break; 4449 case phymod_TSCF_PLL_DIV198: 4450 *bit_time_period = 0x543; 4451 break; 4452 case phymod_TSCF_PLL_DIV200: 4453 *bit_time_period = 0x535; 4454 break; 4455 default: 4456 *bit_time_period = 0x683; 4457 break; 4458 } 4459 return SOC_E_NONE; 4460 } 4461 4462 STATIC 4463 int _cpri_core_init_pass2(int unit, int port, const phymod_core_access_t* core, 4464 const phymod_core_init_config_t* init_config, 4465 const phymod_core_status_t* core_status) 4466 { 4467 phymod_phy_access_t phy_access; 4468 phymod_phy_access_t phy_access_copy; 4469 phymod_core_access_t core_copy; 4470 phymod_firmware_core_config_t firmware_core_config_tmp; 4471 uint32_t vco_rate; 4472 uint32_t fast_clock_bit_time_period = 0; 4473 4474 SOC_INIT_FUNC_DEFS; 4475 sal_memcpy(&phy_access.access, &core->access, sizeof(phy_access.access)); 4476 sal_memcpy(&core_copy, core, sizeof(core_copy)); 4477 4478 phy_access.type = core->type; \ 4479 phy_access.port_loc = core->port_loc; \ 4480 phy_access.device_op_mode = core->device_op_mode; \ 4481 phy_access.access.lane_mask = 0x1; 4482 4483 core_copy.access.lane_mask = 0x1; 4484 phy_access_copy = phy_access; 4485 phy_access_copy.access = core->access; 4486 phy_access_copy.access.lane_mask = 0x1; 4487 phy_access_copy.type = core->type; 4488 4489 #ifndef CPRI_PMD_CRC_UCODE_VERIFY 4490 if (init_config->firmware_load_method != phymodFirmwareLoadMethodNone) { 4491 int rv; 4492 rv = falcon2_monterey_ucode_load_verify(&core_copy.access, (uint8_t *) &falcon_dpll_ucode, falcon_dpll_ucode_len); 4493 if (rv != SOC_E_NONE) { 4494 /*_SOC_EXIT_WITH_ERR(SOC_E_FAIL, ("devad 0x%x lane 0x%x: UC load-verify failed\n", core->access.addr, core->access.lane_mask));*/ 4495 SOC_IF_ERROR_RETURN(rv); 4496 } 4497 } 4498 #endif 4499 4500 /* cpri lane swap */ 4501 SOC_IF_ERROR_RETURN 4502 (_cpri_core_lane_map_set(unit, port, &core_copy, &init_config->lane_map, 1)); 4503 4504 if (PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY_GET(init_config)) { 4505 #ifndef CPRI_PMD_CRC_UCODE_VERIFY 4506 /* poll the ready bit in 10 ms */ 4507 _SOC_IF_ERR_EXIT 4508 (falcon2_monterey_poll_uc_dsc_ready_for_cmd_equals_1(&phy_access_copy.access, 100)); 4509 4510 #else 4511 _SOC_IF_ERR_EXIT 4512 (falcon2_monterey_ucode_crc_verify(&core_copy.access, falcon_dpll_ucode_len, falcon_dpll_ucode_crc)); 4513 #endif 4514 } 4515 4516 _SOC_IF_ERR_EXIT 4517 (falcon2_monterey_pmd_ln_h_rstb_pkill_override(&phy_access_copy.access, 0x0)); 4518 4519 /* set charge pump current */ 4520 if (init_config->afe_pll.afe_pll_change_default){ 4521 _SOC_IF_ERR_EXIT 4522 (falcon2_monterey_afe_pll_reg_set(&core_copy.access, &init_config->afe_pll)); 4523 firmware_core_config_tmp.disable_write_pll_iqp = 1; 4524 } else { 4525 _SOC_IF_ERR_EXIT 4526 (falcon2_monterey_afe_pll_reg_set(&core_copy.access, &init_config->afe_pll)); 4527 firmware_core_config_tmp.disable_write_pll_iqp = 0; 4528 } 4529 4530 /* PLL configuration */ 4531 phy_access_copy.access.lane_mask = 0x1; 4532 firmware_core_config_tmp = init_config->firmware_core_config; 4533 firmware_core_config_tmp.CoreConfigFromPCS = 0; 4534 4535 4536 /* reset core DP */ 4537 core_copy.access.pll_idx = 0; 4538 _SOC_IF_ERR_EXIT 4539 (falcon2_monterey_core_soft_reset_release(&core_copy.access, 0)); 4540 4541 falcon2_monterey_write_cip_clk_div(&core_copy.access, 2); 4542 4543 if (init_config->pll1_div_init_value) { 4544 core_copy.access.pll_idx = 1; 4545 _SOC_IF_ERR_EXIT 4546 (falcon2_monterey_core_soft_reset_release(&core_copy.access, 0)); 4547 falcon2_monterey_write_cip_clk_div(&core_copy.access, 2); 4548 } 4549 /* PLL0 config */ 4550 phy_access_copy.access.pll_idx = 0; 4551 4552 SOC_IF_ERROR_RETURN 4553 (_cpri_pmd_pll_configure(&phy_access_copy.access, init_config->pll0_div_init_value, init_config->interface.ref_clock)); 4554 SOC_IF_ERROR_RETURN 4555 (_cpri_pmd_pll_to_vco_rate(&phy_access_copy.access, init_config->pll0_div_init_value, init_config->interface.ref_clock, &vco_rate)); 4556 firmware_core_config_tmp.VcoRate = MHZ_TO_VCO_RATE(vco_rate); 4557 SOC_IF_ERROR_RETURN 4558 (_cpri_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 4559 4560 /* 4561 * match the PLL0 setting with fclk_bit_timer_period. 4562 */ 4563 SOC_IF_ERROR_RETURN 4564 (_cpri_fast_clock_bit_time_period_get(init_config->pll0_div_init_value, &fast_clock_bit_time_period)); 4565 4566 SOC_IF_ERROR_RETURN 4567 (cprif_drv_fast_clk_bit_time_period_set(unit, port, fast_clock_bit_time_period)); 4568 4569 /* PLL1 config */ 4570 if (init_config->pll1_div_init_value) { 4571 phy_access_copy.access.pll_idx = 1; 4572 SOC_IF_ERROR_RETURN 4573 (_cpri_pmd_pll_configure(&phy_access_copy.access, init_config->pll1_div_init_value, init_config->interface.ref_clock)); 4574 SOC_IF_ERROR_RETURN 4575 (_cpri_pmd_pll_to_vco_rate(&phy_access_copy.access, init_config->pll1_div_init_value, init_config->interface.ref_clock, &vco_rate)); 4576 4577 SOC_IF_ERROR_RETURN 4578 (_cpri_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 4579 } 4580 /* Release core DP soft reset */ 4581 core_copy.access.pll_idx = 0; 4582 _SOC_IF_ERR_EXIT 4583 (falcon2_monterey_core_soft_reset_release(&core_copy.access, 1)); 4584 4585 if (init_config->pll1_div_init_value) { 4586 core_copy.access.pll_idx = 1; 4587 _SOC_IF_ERR_EXIT 4588 (falcon2_monterey_core_soft_reset_release(&core_copy.access, 1)); 4589 } 4590 4591 exit: 4592 SOC_FUNC_RETURN; 4593 4594 } 4595 4596 STATIC 4597 int _cpri_core_init_pass1(int unit, int port, const phymod_core_access_t* core, 4598 const phymod_core_init_config_t* init_config, 4599 const phymod_core_status_t* core_status) 4600 { 4601 uint32_t uc_enable = 0; 4602 phymod_phy_access_t phy_access; 4603 phymod_core_access_t core_copy; 4604 SOC_INIT_FUNC_DEFS; 4605 4606 sal_memcpy(&phy_access.access, &core->access, sizeof(phy_access.access)); 4607 sal_memcpy(&core_copy, core, sizeof(core_copy)); 4608 4609 phy_access.type = core->type; \ 4610 phy_access.port_loc = core->port_loc; \ 4611 phy_access.device_op_mode = core->device_op_mode; \ 4612 phy_access.access.lane_mask = 0xf; 4613 4614 core_copy.access.lane_mask = 0x1; 4615 4616 /* De-assert PMD core power and core data path reset */ 4617 SOC_IF_ERROR_RETURN(cprif_drv_pmd_reset_seq(unit, port, core_status->pmd_active)); 4618 4619 SOC_IF_ERROR_RETURN(tefmod_gen3_pmd_reset_seq(&core_copy.access, core_status->pmd_active)); 4620 4621 _SOC_IF_ERR_EXIT 4622 (falcon2_monterey_uc_active_get(&phy_access.access, &uc_enable)); 4623 if (uc_enable) return SOC_E_NONE; 4624 4625 /* PMD lane swap */ 4626 SOC_IF_ERROR_RETURN 4627 (_cpri_core_lane_map_set(unit, port, &core_copy, &init_config->lane_map, 0)); 4628 4629 /* Micro code load */ 4630 _rv = _cpri_core_firmware_load(&core_copy, init_config->firmware_load_method, init_config->firmware_loader); 4631 if (_rv != SOC_E_NONE) { 4632 _SOC_EXIT_WITH_ERR(SOC_E_CONFIG, ("devad 0x%"PRIx32" lane 0x%"PRIx32": UC firmware-load failed\n", core->access.addr, core->access.lane_mask)); 4633 } 4634 /* pmd lane hard reset */ 4635 PHYMOD_IF_ERR_RETURN 4636 (falcon2_monterey_pmd_ln_h_rstb_pkill_override(&core_copy.access, 0x1)); 4637 4638 /* Set uc_active = 1 */ 4639 PHYMOD_IF_ERR_RETURN 4640 (falcon2_monterey_uc_active_set(&core_copy.access, 1)); 4641 4642 /* De-assert micro reset */ 4643 PHYMOD_IF_ERR_RETURN 4644 (falcon2_monterey_uc_reset(&core_copy.access, 0)); 4645 4646 if (PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY_GET(init_config)) { 4647 #ifdef TSCF_GEN3_PMD_CRC_UCODE_VERIFY 4648 PHYMOD_IF_ERR_RETURN( 4649 falcon2_monterey_start_ucode_crc_calc(&core_copy.access, falcon_dpll_ucode_len)); 4650 #endif 4651 } 4652 4653 exit: 4654 SOC_FUNC_RETURN; 4655 4656 } 4657 4658 int cprif_core_init(int unit, int port, const phymod_core_access_t* core, 4659 const phymod_core_init_config_t* init_config, 4660 phymod_core_status_t* core_status) 4661 { 4662 phymod_phy_access_t phy_access; 4663 SOC_INIT_FUNC_DEFS; 4664 4665 /* remove POR H reset */ 4666 4667 SOC_IF_ERROR_RETURN(cprif_drv_cip_top_ctrl_set(unit, port, 0)); 4668 SOC_IF_ERROR_RETURN(cprif_drv_pmd_ctrl_por_h_rstb_set(unit, port, 0)); 4669 4670 if ((!CPRIMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config) && 4671 !CPRIMOD_CORE_INIT_F_EXECUTE_PASS2_GET(init_config)) || 4672 CPRIMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config)) { 4673 SOC_IF_ERROR_RETURN 4674 (_cpri_core_init_pass1(unit, port, core, init_config, core_status)); 4675 4676 if (CPRIMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config)) { 4677 return SOC_E_NONE; 4678 } 4679 } 4680 4681 if ( (!CPRIMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config) && 4682 !CPRIMOD_CORE_INIT_F_EXECUTE_PASS2_GET(init_config)) || 4683 CPRIMOD_CORE_INIT_F_EXECUTE_PASS2_GET(init_config)) { 4684 SOC_IF_ERROR_RETURN 4685 (_cpri_core_init_pass2(unit, port, core, init_config, core_status)); 4686 } 4687 4688 /* PLL programming */ 4689 if (init_config->pll0_div_init_value) { 4690 /* PLL is CPRI */ 4691 SOC_IF_ERROR_RETURN(cprif_drv_top_ctrl_config_pll_ctrl_set(unit, port, 0, 1)); 4692 /* enable reg clk in and ref clk out */ 4693 SOC_IF_ERROR_RETURN(cprif_drv_top_ctrl_config_ref_clk_ctrl_set(unit, port, 0, 1, 1)); 4694 /* Set lcref_sel */ 4695 SOC_IF_ERROR_RETURN(cprif_drv_cpmport_pll_ctrl_config_set(unit, port, 0, 0)); 4696 4697 sal_memcpy(&phy_access.access, &core->access, sizeof(phy_access.access)); 4698 phy_access.access.lane_mask = 0x1; 4699 /* need to set the heart beat */ 4700 _SOC_IF_ERR_EXIT(falcon2_monterey_pll_heart_beat_set(&phy_access.access, 0)); 4701 4702 /* 4703 * init pll0 4704 */ 4705 SOC_IF_ERROR_RETURN(cprif_drv_pmd_core_datapath_hard_reset_set(unit, port, 0, 1)); 4706 /* wait for pll to lock */ 4707 } 4708 if (init_config->pll1_div_init_value) { 4709 /* PLL is CPRI */ 4710 SOC_IF_ERROR_RETURN(cprif_drv_top_ctrl_config_pll_ctrl_set(unit, port, 1, 1)); 4711 /* enable reg clk in and ref clk out */ 4712 SOC_IF_ERROR_RETURN(cprif_drv_top_ctrl_config_ref_clk_ctrl_set(unit, port, 1, 1, 1)); 4713 /* Set lcref_sel */ 4714 SOC_IF_ERROR_RETURN(cprif_drv_cpmport_pll_ctrl_config_set(unit, port, 1, 1)); 4715 /* 4716 * init pll1 4717 */ 4718 SOC_IF_ERROR_RETURN(cprif_drv_pmd_core_datapath_hard_reset_set(unit, port, 1, 1)); 4719 /* wait for pll to lock */ 4720 } 4721 exit: 4722 SOC_FUNC_RETURN; 4723 } 4724 4725 int cprif_cpri_pll_status_get(int unit, int port, 4726 const phymod_phy_access_t* phy, 4727 int* pll_sel, int* pll_lock) 4728 { 4729 uint8 pll_sel8, pll_lock8; 4730 phymod_phy_access_t phy_access_copy; 4731 SOC_INIT_FUNC_DEFS; 4732 4733 sal_memcpy(&phy_access_copy, phy, sizeof(phy_access_copy)); 4734 falcon2_monterey_pll_select_get(&phy->access, &pll_sel8); 4735 *pll_sel = pll_sel8; 4736 if(*pll_sel == 1) { 4737 phy_access_copy.access.pll_idx = 1; 4738 } else { 4739 phy_access_copy.access.pll_idx = 0; 4740 } 4741 falcon2_monterey_pll_lock_get(&phy_access_copy.access, &pll_lock8); 4742 *pll_lock = pll_lock8; 4743 4744 SOC_FUNC_RETURN; 4745 4746 } 4747 4748 4749 int cprif_port_init(int unit, int port, const phymod_phy_access_t* phy, 4750 const cprimod_port_init_config_t* port_config) 4751 { 4752 uint32 wd_len; 4753 uint32 pll_mode0; 4754 uint32 pll_mode1; 4755 uint32_t vco_rate; 4756 phymod_firmware_core_config_t firmware_core_config_tmp; 4757 phymod_phy_access_t phy_access_copy; 4758 struct falcon2_monterey_uc_lane_config_st serdes_firmware_config; 4759 phymod_tx_t tx_afe; 4760 cprimod_basic_frame_table_id_t table; 4761 uint32 fast_clock_bit_time_period = 0; 4762 SOC_INIT_FUNC_DEFS; 4763 4764 sal_memset(&tx_afe, 0, sizeof(phymod_tx_t)); 4765 sal_memcpy(&phy_access_copy, phy, sizeof(phy_access_copy)); 4766 phy_access_copy.access.pll_idx = 0; 4767 falcon2_monterey_pll_mode_get(&phy_access_copy.access, &pll_mode0); 4768 phy_access_copy.access.pll_idx = 1; 4769 falcon2_monterey_pll_mode_get(&phy_access_copy.access, &pll_mode1); 4770 SOC_IF_ERROR_RETURN(cprif_drv_pmd_ctrl_ln_por_h_rstb_set(unit, port)); 4771 /* PLL0 is selected for cpri for now Need to change when new speeds are supported */ 4772 falcon2_monterey_lane_soft_reset_release(&phy->access, 0); 4773 /* pll_in_use tells which plls are in use, check if PLL0 is used (enabled) And 4774 if vco required is vco of pll0 then use pll0 for the lane */ 4775 if (((port_config->pll_in_use & cprimodInUsePll0) != 0) && 4776 (port_config->vco_for_lane == pll_mode0)) { 4777 falcon2_monterey_pll_select_set(&phy->access, 0); 4778 SOC_IF_ERROR_RETURN(cprif_drv_cip_clk_pll_select_set(unit, port, 0)); 4779 /* pll_in_use tells which plls are in use, check if PLL1 is used (enabled) And 4780 if vco required is vco of pll1 then use pll1 for the lane */ 4781 } else if (((port_config->pll_in_use & cprimodInUsePll1) != 0) && 4782 (port_config->vco_for_lane == pll_mode1)) { 4783 falcon2_monterey_pll_select_set(&phy->access, 1); 4784 SOC_IF_ERROR_RETURN(cprif_drv_cip_clk_pll_select_set(unit, port, 1)); 4785 } else { 4786 /* When required vco does not match with existing pll vco try to use pll that is 4787 not used by other lanes */ 4788 if ((port_config->pll_in_use & cprimodInUsePll0) == 0) { 4789 /* if pll0 is not used by other lanes bringup pll0 for new vco */ 4790 falcon2_monterey_pll_select_set(&phy->access, 0); 4791 phy_access_copy.access.pll_idx = 0; 4792 SOC_IF_ERROR_RETURN(cprif_drv_cip_clk_pll_select_set(unit, port, 0)); 4793 } else { 4794 falcon2_monterey_pll_select_set(&phy->access, 1); 4795 phy_access_copy.access.pll_idx = 1; 4796 SOC_IF_ERROR_RETURN(cprif_drv_cip_clk_pll_select_set(unit, port, 1)); 4797 } 4798 _SOC_IF_ERR_EXIT 4799 (falcon2_monterey_core_soft_reset_release(&phy_access_copy.access, 0)); 4800 SOC_IF_ERROR_RETURN 4801 (_cpri_pmd_pll_configure(&phy_access_copy.access, port_config->vco_for_lane, 0)); 4802 SOC_IF_ERROR_RETURN 4803 (_cpri_pmd_pll_to_vco_rate(&phy_access_copy.access, 4804 port_config->vco_for_lane, 0, &vco_rate)); 4805 4806 /* 4807 * match the PLL0 setting with fclk_bit_timer_period. 4808 */ 4809 if (phy_access_copy.access.pll_idx == 0) { 4810 _SOC_IF_ERR_EXIT 4811 (_cpri_fast_clock_bit_time_period_get(port_config->vco_for_lane, &fast_clock_bit_time_period)); 4812 4813 _SOC_IF_ERR_EXIT 4814 (cprif_drv_fast_clk_bit_time_period_set(unit, port, fast_clock_bit_time_period)); 4815 } 4816 4817 firmware_core_config_tmp.disable_write_pll_iqp = 0; 4818 firmware_core_config_tmp.CoreConfigFromPCS = 0; 4819 firmware_core_config_tmp.VcoRate = MHZ_TO_VCO_RATE(vco_rate); 4820 4821 SOC_IF_ERROR_RETURN 4822 (_cpri_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 4823 _SOC_IF_ERR_EXIT 4824 (falcon2_monterey_core_soft_reset_release(&phy_access_copy.access, 1)); 4825 4826 } 4827 serdes_firmware_config.field.lane_cfg_from_pcs = 0; 4828 serdes_firmware_config.field.an_enabled = 0; 4829 serdes_firmware_config.field.dfe_on = 1; 4830 serdes_firmware_config.field.dfe_lp_mode = 0; 4831 serdes_firmware_config.field.force_brdfe_on = 0; 4832 serdes_firmware_config.field.media_type = phymodFirmwareMediaTypeOptics; 4833 serdes_firmware_config.field.unreliable_los = 1; 4834 if((port_config->rx_cpri_speed == cprimodSpd10137p6)|| 4835 (port_config->rx_cpri_speed == cprimodSpd12165p12)|| 4836 (port_config->rx_cpri_speed == cprimodSpd24330p24)) { 4837 serdes_firmware_config.field.scrambling_dis = 0; 4838 } else { 4839 serdes_firmware_config.field.scrambling_dis = 1; 4840 } 4841 serdes_firmware_config.field.cl72_auto_polarity_en = 0; 4842 serdes_firmware_config.field.cl72_restart_timeout_en = 0; 4843 serdes_firmware_config.word = 0; 4844 PHYMOD_IF_ERR_RETURN(falcon2_monterey_set_uc_lane_cfg(&phy->access, serdes_firmware_config)); 4845 falcon2_monterey_lane_soft_reset_release(&phy->access, 1); 4846 4847 SOC_IF_ERROR_RETURN(cprif_drv_tx_h_reset_set(unit, port, cpriResetEnAssert)); 4848 SOC_IF_ERROR_RETURN(cprif_drv_rx_h_reset_set(unit, port, cpriResetEnAssert)); 4849 4850 SOC_IF_ERROR_RETURN(cprif_drv_cip_tx_h_reset_set(unit, port, 4851 cpriResetEnAssert)); 4852 SOC_IF_ERROR_RETURN(cprif_drv_cip_rx_h_reset_set(unit, port, 4853 cpriResetEnAssert)); 4854 4855 SOC_IF_ERROR_RETURN(cprif_drv_datapath_tx_h_reset_set(unit, port, 4856 cpriResetEnAssert)); 4857 SOC_IF_ERROR_RETURN(cprif_drv_datapath_rx_h_reset_set(unit, port, 4858 cpriResetEnAssert)); 4859 4860 SOC_IF_ERROR_RETURN(cprif_drv_tx_h_reset_set(unit, port, 4861 cpriResetEnDeassert)); 4862 SOC_IF_ERROR_RETURN(cprif_drv_rx_h_reset_set(unit, port, 4863 cpriResetEnDeassert)); 4864 4865 SOC_IF_ERROR_RETURN(cprif_drv_cip_tx_h_reset_set(unit, port, 4866 cpriResetEnDeassert)); 4867 SOC_IF_ERROR_RETURN(cprif_drv_cip_rx_h_reset_set(unit, port, 4868 cpriResetEnDeassert)); 4869 4870 SOC_IF_ERROR_RETURN(cprif_drv_datapath_tx_h_reset_set(unit, port, 4871 cpriResetEnDeassert)); 4872 SOC_IF_ERROR_RETURN(cprif_drv_datapath_rx_h_reset_set(unit, port, 4873 cpriResetEnDeassert)); 4874 /* remove POR H reset */ 4875 /* SOC_IF_ERROR_RETURN(cprif_drv_pmd_ctrl_por_h_rstb_set(unit, port, 0)); */ 4876 4877 /* 4878 * set polarity port_config->polarity 4879 * set other per lane PMD setting 4880 */ 4881 falcon2_monterey_tx_rx_polarity_set(&phy->access, port_config->polarity_tx, port_config->polarity_rx); 4882 /* 4883 * Check speed if current VCO will support it or through error 4884 */ 4885 falcon2_monterey_lane_soft_reset_release(&phy->access, 0); 4886 if (port_config->interface == cprimodCpri) { 4887 SOC_IF_ERROR_RETURN(cprif_drv_tx_frame_optional_config_set(unit, 4888 port, 4889 cprimodTxConfigseed8B10B, 4890 port_config->serdes_scrambler_seed)); 4891 SOC_IF_ERROR_RETURN(cprif_drv_tx_frame_optional_config_set(unit, 4892 port, 4893 cprimodTxConfigcwaScrEn8b10b, 4894 port_config->serdes_scrambler_enable)); 4895 SOC_IF_ERROR_RETURN(cprif_drv_rx_frame_optional_config_set(unit, 4896 port, 4897 cprimodRxConfig8b10bDescrEn, 4898 port_config->serdes_scrambler_enable)); 4899 4900 SOC_IF_ERROR_RETURN(_cprif_port_tx_speed_set(unit, port, phy, 4901 port_config->tx_cpri_speed)); 4902 SOC_IF_ERROR_RETURN(_cprif_port_rx_speed_set(unit, port, phy, 4903 port_config->rx_cpri_speed)); 4904 } else { 4905 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_frame_optional_config_set(unit, 4906 port, 4907 cprimodRsvd4TxConfigScramblerSeed, 4908 port_config->serdes_scrambler_seed)); 4909 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_tx_frame_optional_config_set(unit, 4910 port, 4911 cprimodRsvd4TxConfigScrambleEnable, 4912 port_config->serdes_scrambler_enable)); 4913 SOC_IF_ERROR_RETURN(cprif_drv_rsvd4_rx_frame_optional_config_set(unit, 4914 port, 4915 cprimodRsvd4RxConfigDescrambleEnable, 4916 port_config->serdes_scrambler_enable)); 4917 4918 SOC_IF_ERROR_RETURN(cprif_port_rsvd4_tx_speed_set(unit, port, phy, 4919 port_config->tx_rsvd4_speed)); 4920 SOC_IF_ERROR_RETURN(cprif_port_rsvd4_rx_speed_set(unit, port, phy, 4921 port_config->rx_rsvd4_speed)); 4922 } 4923 falcon2_monterey_lane_soft_reset_release(&phy->access, 1); 4924 4925 if (port_config->interface == cprimodCpri) { 4926 _SOC_IF_ERR_EXIT 4927 (cprimod_basic_frame_parser_active_table_get(unit, port,&table)); 4928 if (table == cprimod_basic_frame_table_0) { 4929 _SOC_IF_ERR_EXIT 4930 (cprif_basic_frame_parser_active_table_set(unit, port,cprimod_basic_frame_table_1, TRUE)); 4931 } else { 4932 _SOC_IF_ERR_EXIT 4933 (cprif_basic_frame_parser_active_table_set(unit, port,cprimod_basic_frame_table_0, TRUE)); 4934 } 4935 _SOC_IF_ERR_EXIT 4936 (cprif_basic_frame_assembly_active_table_get(unit, port,&table)); 4937 if (table == cprimod_basic_frame_table_0) { 4938 _SOC_IF_ERR_EXIT 4939 (cprif_basic_frame_assembly_active_table_set(unit, port,cprimod_basic_frame_table_1, TRUE)); 4940 } else { 4941 _SOC_IF_ERR_EXIT 4942 (cprif_basic_frame_assembly_active_table_set(unit, port,cprimod_basic_frame_table_0, TRUE)); 4943 } 4944 } else { 4945 _SOC_IF_ERR_EXIT 4946 (cprif_basic_frame_parser_switch_active_table(unit, port)); 4947 4948 _SOC_IF_ERR_EXIT 4949 (cprif_basic_frame_assembly_switch_active_table(unit, port)); 4950 } 4951 4952 _SOC_IF_ERR_EXIT 4953 (cprif_drv_stuff_rsrv_bits_set(unit, port, port_config->roe_stuffing_bit, port_config->roe_reserved_bit)); 4954 _SOC_IF_ERR_EXIT(cprif_drv_glas_reset_set(unit, port, 1)); 4955 _SOC_IF_ERR_EXIT(cprif_drv_cip_rx_dp_reset_set(unit, port, 1)); 4956 _SOC_IF_ERR_EXIT(cprif_drv_datapath_rx_dp_reset_set(unit, port, 1)); 4957 _SOC_IF_ERR_EXIT(cprif_drv_rx_dp_reset_set(unit, port, 1)); 4958 _SOC_IF_ERR_EXIT(cprif_drv_datapath_credit_reset_set(unit, port, 1)); 4959 /* remove soft resets Rx path*/ 4960 _SOC_IF_ERR_EXIT(cprif_drv_glas_reset_set(unit, port, 0)); 4961 _SOC_IF_ERR_EXIT(cprif_drv_cip_rx_dp_reset_set(unit, port, 0)); 4962 _SOC_IF_ERR_EXIT(cprif_drv_datapath_rx_dp_reset_set(unit, port, 0)); 4963 _SOC_IF_ERR_EXIT(cprif_drv_rx_dp_reset_set(unit, port, 0)); 4964 _SOC_IF_ERR_EXIT(cprif_drv_datapath_credit_reset_set(unit, port, 0)); 4965 /* remove soft resets Tx path*/ 4966 _SOC_IF_ERR_EXIT(cprif_drv_cip_tx_dp_reset_set(unit, port, 1)); 4967 _SOC_IF_ERR_EXIT(cprif_drv_datapath_tx_dp_reset_set(unit, port, 1)); 4968 _SOC_IF_ERR_EXIT(cprif_drv_tx_dp_reset_set(unit, port, 1)); 4969 _SOC_IF_ERR_EXIT(cprif_drv_cip_tx_dp_reset_set(unit, port, 0)); 4970 _SOC_IF_ERR_EXIT(cprif_drv_datapath_tx_dp_reset_set(unit, port, 0)); 4971 _SOC_IF_ERR_EXIT(cprif_drv_tx_dp_reset_set(unit, port, 0)); 4972 if (port_config->interface == cprimodCpri) { 4973 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_clear(unit, port)); 4974 wd_len = _cprif_from_speed_towd_len(port_config->rx_cpri_speed); 4975 /* Adding AXC for control word */ 4976 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_add(unit, port, 255, 4977 0, wd_len)); 4978 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_clear(unit, port)); 4979 wd_len = _cprif_from_speed_towd_len(port_config->tx_cpri_speed); 4980 /* Adding AXC for control word */ 4981 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_add(unit, port, 255, 4982 0, wd_len)); 4983 } else { 4984 SOC_IF_ERROR_RETURN 4985 (_cprif_port_rsvd4_basic_frame_table_set(unit, port, CPRIMOD_DIR_RX)); 4986 SOC_IF_ERROR_RETURN 4987 (_cprif_port_rsvd4_basic_frame_table_set(unit, port, CPRIMOD_DIR_TX)); 4988 } 4989 4990 /* Enable CPRI Port Link Status Interrupts for HW Linkscan handling */ 4991 4992 /* 4993 * This will not be enable for HW linkscan as there is already another 4994 * Link status interrupt going to the CMIC. CMIC_MIIM_LINK_STATUS_0 4995 * and CMIC_MIIM_LINK_STATUS_1. 4996 */ 4997 #if 0 4998 if (port_config->interface == cprimodCpri) { 4999 _SOC_IF_ERR_EXIT(_cprif_cpri_port_link_event_intr_enable_set(unit, 5000 port, 1)); 5001 } 5002 #endif 5003 5004 /* Enable ECC interrupts if parity is enabled */ 5005 if (port_config->parity_enable) { 5006 cprimod_cpri_port_ecc_interrupt_enable_set(unit, port, 1); 5007 } 5008 5009 /* 5010 * Enable all the interrupts in the interrupts hierarchy during 5011 * the init except the actual interrupts, which need 5012 * to enabled using the interrupt enable API 5013 */ 5014 _SOC_IF_ERR_EXIT(_cprif_cpri_port_intr_hierarchy_enable(unit, port, 1)); 5015 5016 /* Program TX AFE setting */ 5017 SOC_IF_ERROR_RETURN 5018 (phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &tx_afe)); 5019 if (port_config->tx_params_user_config) { 5020 tx_afe.pre = port_config->tx_params[0].pre; 5021 tx_afe.main = port_config->tx_params[0].main; 5022 tx_afe.post = port_config->tx_params[0].post; 5023 } 5024 SOC_IF_ERROR_RETURN 5025 (phymod_phy_tx_set(phy, &tx_afe)); 5026 /* Set time period for Tx and Rx timestamping */ 5027 SOC_IF_ERROR_RETURN(cprimod_1588_bit_time_period_set(unit, port, CPRIMOD_DIR_TX, port_config->tx_cpri_speed)); 5028 SOC_IF_ERROR_RETURN(cprimod_1588_bit_time_period_set(unit, port, CPRIMOD_DIR_RX, port_config->rx_cpri_speed)); 5029 5030 exit: 5031 SOC_FUNC_RETURN; 5032 } 5033 5034 5035 int cprif_rsvd4_rx_master_frame_sync_config_set(int unit, int port, uint32 master_frame_number, uint64 master_frame_start_time) 5036 { 5037 SOC_INIT_FUNC_DEFS; 5038 5039 _SOC_IF_ERR_EXIT 5040 (cprif_drv_rsvd4_rx_master_frame_sync_config_set(unit, port, 5041 master_frame_number, 5042 master_frame_start_time)); 5043 5044 exit: 5045 SOC_FUNC_RETURN; 5046 5047 } 5048 5049 int cprif_rsvd4_rx_master_frame_sync_config_get(int unit, int port, uint32* master_frame_number, uint64* master_frame_start_time) 5050 { 5051 SOC_INIT_FUNC_DEFS; 5052 5053 _SOC_IF_ERR_EXIT 5054 (cprif_drv_rsvd4_rx_master_frame_sync_config_get(unit, port, 5055 master_frame_number, 5056 master_frame_start_time)); 5057 5058 5059 exit: 5060 SOC_FUNC_RETURN; 5061 5062 } 5063 5064 int cprif_cpri_rx_control_word_sync_info_get(int unit, int port, uint32* hyper_frame_num, uint32* radio_frame_num) 5065 { 5066 cprif_drv_rx_control_word_status_t cw_info; 5067 SOC_INIT_FUNC_DEFS; 5068 5069 sal_memset(&cw_info, 0, sizeof(cprif_drv_rx_control_word_status_t)); 5070 5071 _SOC_IF_ERR_EXIT 5072 (cprif_drv_rx_control_word_status_get(unit, port, &cw_info)); 5073 5074 *hyper_frame_num = cw_info.hyper_frame; 5075 *radio_frame_num = cw_info.radio_frame; 5076 5077 exit: 5078 SOC_FUNC_RETURN; 5079 5080 } 5081 5082 int cprif_cpri_rx_control_word_l1_signal_info_get(int unit, int port, cprimod_cpri_cw_l1_protocol_info_t* l1_info) 5083 { 5084 cprif_drv_rx_control_word_status_t cw_info; 5085 SOC_INIT_FUNC_DEFS; 5086 5087 sal_memset(&cw_info, 0, sizeof(cprif_drv_rx_control_word_status_t)); 5088 5089 _SOC_IF_ERR_EXIT 5090 (cprif_drv_rx_control_word_status_get(unit, port, &cw_info)); 5091 5092 l1_info->hdlc_rate = cw_info.hdlc_rate; 5093 l1_info->protocol_ver = cw_info.protocol_ver; 5094 l1_info->eth_pointer = cw_info.eth_pointer; 5095 l1_info->reset = cw_info.reset ? 1:0; 5096 l1_info->l1_rai = cw_info.l1_rai ? 1:0; 5097 l1_info->l1_sdi = cw_info.l1_sdi ? 1:0; 5098 l1_info->l1_los = cw_info.l1_los ? 1:0; 5099 l1_info->l1_lof = cw_info.l1_lof ? 1:0; 5100 5101 exit: 5102 SOC_FUNC_RETURN; 5103 5104 } 5105 5106 int cprif_cpri_rx_control_word_l1_signal_signal_protection_set(int unit, int port, uint32 signal_map, uint32 enable) 5107 { 5108 SOC_INIT_FUNC_DEFS; 5109 5110 _SOC_IF_ERR_EXIT 5111 (cprif_drv_cpri_rx_l1_signal_signal_protection_set(unit, port, signal_map, enable)); 5112 5113 exit: 5114 SOC_FUNC_RETURN; 5115 5116 } 5117 5118 int cprif_cpri_rx_control_word_l1_signal_signal_protection_get(int unit, int port, uint32 signal_map, uint32* enable) 5119 { 5120 SOC_INIT_FUNC_DEFS; 5121 5122 _SOC_IF_ERR_EXIT 5123 (cprif_drv_cpri_rx_l1_signal_signal_protection_get(unit, port, signal_map, enable)); 5124 5125 exit: 5126 SOC_FUNC_RETURN; 5127 5128 } 5129 5130 static 5131 void _cprimod_to_cprif_fcs_size ( cprimod_cpri_hdlc_fcs_size_t cprimod_fcs_size, uint32* cprif_fcs_size) 5132 { 5133 switch (cprimod_fcs_size) { 5134 case CPRIMOD_CPRI_HDLC_FCS_SIZE_8_BITS: 5135 *cprif_fcs_size = CPRIF_HDLC_FCS_SIZE_8_BITS; 5136 break; 5137 case CPRIMOD_CPRI_HDLC_FCS_SIZE_16_BITS: 5138 *cprif_fcs_size = CPRIF_HDLC_FCS_SIZE_16_BITS; 5139 break; 5140 case CPRIMOD_CPRI_HDLC_FCS_SIZE_32_BITS: 5141 *cprif_fcs_size = CPRIF_HDLC_FCS_SIZE_32_BITS; 5142 break; 5143 default: 5144 *cprif_fcs_size = CPRIF_HDLC_FCS_SIZE_8_BITS; 5145 break; 5146 } 5147 } 5148 5149 static 5150 void _cprif_to_cprimod_fcs_size ( uint32 cprif_fcs_size, cprimod_cpri_hdlc_fcs_size_t *cprimod_fcs_size) 5151 { 5152 switch (cprif_fcs_size) { 5153 case CPRIF_HDLC_FCS_SIZE_8_BITS: 5154 *cprimod_fcs_size = CPRIMOD_CPRI_HDLC_FCS_SIZE_8_BITS; 5155 break; 5156 case CPRIF_HDLC_FCS_SIZE_16_BITS: 5157 *cprimod_fcs_size = CPRIMOD_CPRI_HDLC_FCS_SIZE_16_BITS; 5158 break; 5159 case CPRIF_HDLC_FCS_SIZE_32_BITS: 5160 *cprimod_fcs_size = CPRIMOD_CPRI_HDLC_FCS_SIZE_32_BITS; 5161 break; 5162 default: 5163 *cprimod_fcs_size = CPRIMOD_CPRI_HDLC_FCS_SIZE_8_BITS; 5164 break; 5165 } 5166 } 5167 5168 static 5169 void _cprimod_to_cprif_filling_flag_pattern(cprimod_cpri_hdlc_filling_flag_pattern_t cprimod_pattern, uint32* cprif_pattern) 5170 { 5171 switch (cprimod_pattern) { 5172 5173 case CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E: 5174 *cprif_pattern = CPRIF_HDLC_FILLING_FLAG_PATTERN_7E; 5175 break; 5176 case CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7F: 5177 *cprif_pattern = CPRIF_HDLC_FILLING_FLAG_PATTERN_7F; 5178 break; 5179 case CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_FF: 5180 *cprif_pattern = CPRIF_HDLC_FILLING_FLAG_PATTERN_FF; 5181 break; 5182 default: 5183 *cprif_pattern = CPRIF_HDLC_FILLING_FLAG_PATTERN_7E; 5184 break; 5185 } 5186 } 5187 5188 static 5189 void _cprif_to_cprimod_filling_flag_pattern( uint32 cprif_pattern, cprimod_cpri_hdlc_filling_flag_pattern_t *cprimod_pattern) 5190 { 5191 switch (cprif_pattern) { 5192 5193 case CPRIF_HDLC_FILLING_FLAG_PATTERN_7E: 5194 *cprimod_pattern = CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E; 5195 break; 5196 case CPRIF_HDLC_FILLING_FLAG_PATTERN_7F: 5197 *cprimod_pattern = CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7F; 5198 break; 5199 case CPRIF_HDLC_FILLING_FLAG_PATTERN_FF: 5200 *cprimod_pattern = CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_FF; 5201 break; 5202 default: 5203 *cprimod_pattern = CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E; 5204 break; 5205 } 5206 } 5207 5208 static 5209 void _cprimod_to_cprif_hdlc_crc_mode( cprimod_cpri_crc_mode_t cprimod_mode, uint32* cprif_mode) 5210 { 5211 switch (cprimod_mode) { 5212 case CPRIMOD_CPRI_CRC_MODE_APPEND: 5213 *cprif_mode = CPRIF_HDLC_CRC_MODE_APPEND; 5214 break; 5215 case CPRIMOD_CPRI_CRC_MODE_REPLACE: 5216 *cprif_mode = CPRIF_HDLC_CRC_MODE_REPLACE; 5217 break; 5218 case CPRIMOD_CPRI_CRC_MODE_NO_UPDATE: 5219 *cprif_mode = CPRIF_HDLC_CRC_MODE_NO_UPDATE; 5220 break; 5221 default: 5222 *cprif_mode = CPRIF_HDLC_CRC_MODE_APPEND; 5223 } 5224 } 5225 5226 static 5227 void _cprif_to_cprimod_hdlc_crc_mode( uint32 cprif_mode , cprimod_cpri_crc_mode_t* cprimod_mode) 5228 { 5229 switch (cprif_mode) { 5230 case CPRIF_HDLC_CRC_MODE_APPEND: 5231 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_APPEND ; 5232 break; 5233 case CPRIF_HDLC_CRC_MODE_REPLACE: 5234 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_REPLACE; 5235 break; 5236 case CPRIF_HDLC_CRC_MODE_NO_UPDATE: 5237 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_NO_UPDATE ; 5238 break; 5239 default: 5240 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_APPEND; 5241 } 5242 } 5243 5244 int cprif_cpri_port_cw_slow_hdlc_config_set(int unit, int port, const cprimod_slow_hdlc_config_info_t* config_info) 5245 { 5246 cprif_cpri_rx_hdlc_config_t rx_config; 5247 cprif_cpri_tx_hdlc_config_t tx_config; 5248 SOC_INIT_FUNC_DEFS; 5249 5250 5251 /**** RX Setting ****/ 5252 sal_memset(&rx_config, 0, sizeof(cprif_cpri_rx_hdlc_config_t)); 5253 5254 rx_config.cw_sel = config_info->cw_sel; 5255 rx_config.cw_size= config_info->cw_size; 5256 5257 if (config_info->crc_byte_swap) { 5258 rx_config.crc_byte_swap= CPRIF_HDLC_CRC_BYTE_SWAP; 5259 } else { 5260 rx_config.crc_byte_swap= CPRIF_HDLC_CRC_BYTE_NO_SWAP; 5261 } 5262 5263 if (config_info->crc_init_val == CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1) { 5264 rx_config.crc_init_val = CPRIF_HDLC_CRC_INIT_VAL_ALL_1S; 5265 } else { 5266 rx_config.crc_init_val = CPRIF_HDLC_CRC_INIT_VAL_ALL_0S; 5267 } 5268 5269 rx_config.queue_num= config_info->queue_num; 5270 5271 if (config_info->use_fe_mac) { 5272 rx_config.use_fe_mac= CPRIF_HDLC_USE_FE_MAC; 5273 5274 } else { 5275 rx_config.use_fe_mac= CPRIF_HDLC_USE_HDLC; 5276 } 5277 5278 if (config_info->no_fcs_err_check) { 5279 rx_config.ignore_fcs_err= CPRIF_HDLC_FCS_NO_CHECK; 5280 } else { 5281 rx_config.ignore_fcs_err= CPRIF_HDLC_FCS_CHECK; 5282 } 5283 _cprimod_to_cprif_fcs_size(config_info->fcs_size, &rx_config.fcs_size); 5284 5285 rx_config.runt_frame_drop= config_info->runt_frame_drop ? 1 : 0; 5286 rx_config.long_frame_drop= config_info->long_frame_drop ? 1 : 0; 5287 rx_config.min_frame_size = config_info->min_frame_size; 5288 rx_config.max_frame_size = config_info->max_frame_size;; 5289 5290 _SOC_IF_ERR_EXIT 5291 (cprif_drv_cpri_port_rx_cw_slow_hdlc_config_set(unit, port, &rx_config)); 5292 5293 /**** TX Setting ****/ 5294 5295 sal_memset(&tx_config, 0, sizeof(cprif_cpri_tx_hdlc_config_t)); 5296 5297 tx_config.cw_sel = config_info->cw_sel; 5298 tx_config.cw_size= config_info->cw_size; 5299 _cprimod_to_cprif_filling_flag_pattern(config_info->tx_filling_flag_pattern, &tx_config.filling_flag_pattern); 5300 5301 if (config_info->tx_flag_size == CPRIMOD_HDLC_FLAG_SIZE_1_BYTE) { 5302 tx_config.flag_size = CPRIF_HDLC_FLAG_SIZE_1_BYTE; 5303 } else if (config_info->tx_flag_size == CPRIMOD_HDLC_FLAG_SIZE_2_BYTE) { 5304 tx_config.flag_size = CPRIF_HDLC_FLAG_SIZE_2_BYTE; 5305 } else { 5306 5307 } 5308 if (config_info->crc_byte_swap) { 5309 tx_config.crc_byte_swap= CPRIF_HDLC_CRC_BYTE_SWAP; 5310 } else { 5311 tx_config.crc_byte_swap= CPRIF_HDLC_CRC_BYTE_NO_SWAP; 5312 } 5313 5314 if (config_info->crc_init_val == CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1) { 5315 tx_config.crc_init_val = CPRIF_HDLC_CRC_INIT_VAL_ALL_1S; 5316 } else { 5317 tx_config.crc_init_val = CPRIF_HDLC_CRC_INIT_VAL_ALL_0S; 5318 } 5319 5320 tx_config.queue_num = config_info->queue_num; 5321 5322 if (config_info->use_fe_mac) { 5323 tx_config.use_fe_mac= CPRIF_HDLC_USE_FE_MAC; 5324 5325 } else { 5326 tx_config.use_fe_mac= CPRIF_HDLC_USE_HDLC; 5327 } 5328 5329 _cprimod_to_cprif_fcs_size(config_info->fcs_size, &tx_config.fcs_size); 5330 _cprimod_to_cprif_hdlc_crc_mode(config_info->tx_crc_mode, &tx_config.crc_mode); 5331 5332 _SOC_IF_ERR_EXIT 5333 (cprif_drv_cpri_port_tx_cw_slow_hdlc_config_set(unit, port, &tx_config)); 5334 5335 exit: 5336 SOC_FUNC_RETURN; 5337 5338 } 5339 5340 int cprif_cpri_port_cw_slow_hdlc_config_get(int unit, int port, cprimod_slow_hdlc_config_info_t* config_info) 5341 { 5342 cprif_cpri_rx_hdlc_config_t rx_config; 5343 cprif_cpri_tx_hdlc_config_t tx_config; 5344 SOC_INIT_FUNC_DEFS; 5345 5346 5347 /**** RX Setting ****/ 5348 sal_memset(&rx_config, 0, sizeof(cprif_cpri_rx_hdlc_config_t)); 5349 5350 _SOC_IF_ERR_EXIT 5351 (cprif_drv_cpri_port_rx_cw_slow_hdlc_config_get(unit, port, &rx_config)); 5352 5353 config_info->cw_sel = rx_config.cw_sel; 5354 config_info->cw_size = rx_config.cw_size; 5355 config_info->crc_byte_swap = (rx_config.crc_byte_swap == CPRIF_HDLC_CRC_BYTE_SWAP)?1:0; 5356 5357 if (rx_config.crc_init_val == CPRIF_HDLC_CRC_INIT_VAL_ALL_1S) { 5358 config_info->crc_init_val = CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1; 5359 } else { 5360 config_info->crc_init_val = CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_0; 5361 } 5362 5363 config_info->queue_num = rx_config.queue_num ; 5364 5365 config_info->use_fe_mac = (rx_config.use_fe_mac == CPRIF_HDLC_USE_FE_MAC )?1:0; 5366 5367 config_info->no_fcs_err_check = (rx_config.ignore_fcs_err == CPRIF_HDLC_FCS_NO_CHECK)? 1:0; 5368 5369 _cprif_to_cprimod_fcs_size (rx_config.fcs_size, &config_info->fcs_size); 5370 5371 config_info->runt_frame_drop = rx_config.runt_frame_drop ? 1:0; 5372 config_info->long_frame_drop = rx_config.long_frame_drop ? 1:0; 5373 config_info->min_frame_size = rx_config.min_frame_size; 5374 config_info->max_frame_size = rx_config.max_frame_size; 5375 5376 5377 /**** TX Setting ****/ 5378 5379 sal_memset(&tx_config, 0, sizeof(cprif_cpri_tx_hdlc_config_t)); 5380 _SOC_IF_ERR_EXIT 5381 (cprif_drv_cpri_port_tx_cw_slow_hdlc_config_get(unit, port, &tx_config)); 5382 5383 config_info->cw_sel = tx_config.cw_sel; 5384 config_info->cw_size = tx_config.cw_size; 5385 _cprif_to_cprimod_filling_flag_pattern(tx_config.filling_flag_pattern, &config_info->tx_filling_flag_pattern); 5386 5387 if (tx_config.flag_size == CPRIF_HDLC_FLAG_SIZE_1_BYTE) { 5388 config_info->tx_flag_size = CPRIMOD_HDLC_FLAG_SIZE_1_BYTE; 5389 } else if (tx_config.flag_size == CPRIF_HDLC_FLAG_SIZE_2_BYTE) { 5390 config_info->tx_flag_size = CPRIMOD_HDLC_FLAG_SIZE_2_BYTE; 5391 } 5392 5393 _cprif_to_cprimod_hdlc_crc_mode(tx_config.crc_mode,&config_info->tx_crc_mode); 5394 5395 exit: 5396 SOC_FUNC_RETURN; 5397 } 5398 5399 static 5400 void _cprimod_to_cprif_fast_eth_crc_mode( cprimod_cpri_crc_mode_t cprimod_mode, uint32* cprif_mode) 5401 { 5402 switch (cprimod_mode) { 5403 case CPRIMOD_CPRI_CRC_MODE_APPEND: 5404 *cprif_mode = CPRIF_FAST_ETH_CRC_MODE_APPEND; 5405 break; 5406 case CPRIMOD_CPRI_CRC_MODE_REPLACE: 5407 *cprif_mode = CPRIF_FAST_ETH_CRC_MODE_REPLACE; 5408 break; 5409 case CPRIMOD_CPRI_CRC_MODE_NO_UPDATE: 5410 *cprif_mode = CPRIF_FAST_ETH_CRC_MODE_NO_UPDATE; 5411 break; 5412 default: 5413 *cprif_mode = CPRIF_FAST_ETH_CRC_MODE_APPEND; 5414 break; 5415 } 5416 } 5417 5418 static 5419 void _cprif_to_cprimod_fast_eth_crc_mode( uint32 cprif_mode, cprimod_cpri_crc_mode_t* cprimod_mode) 5420 { 5421 switch (cprif_mode) { 5422 case CPRIF_FAST_ETH_CRC_MODE_APPEND: 5423 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_APPEND; 5424 break; 5425 case CPRIF_FAST_ETH_CRC_MODE_REPLACE: 5426 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_REPLACE; 5427 break; 5428 case CPRIF_FAST_ETH_CRC_MODE_NO_UPDATE: 5429 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_NO_UPDATE; 5430 break; 5431 default: 5432 *cprimod_mode = CPRIMOD_CPRI_CRC_MODE_APPEND; 5433 break; 5434 } 5435 } 5436 5437 int cprif_cpri_port_cw_fast_eth_config_set(int unit, int port, const cprimod_fast_eth_config_info_t* config_info) 5438 { 5439 cprif_cpri_rx_fast_eth_config_t rx_config; 5440 cprif_cpri_rx_fast_eth_word_config_t rx_word_config; 5441 cprif_cpri_tx_fast_eth_config_t tx_config; 5442 SOC_INIT_FUNC_DEFS; 5443 5444 5445 sal_memset(&rx_config, 0, sizeof(cprif_cpri_rx_fast_eth_config_t)); 5446 sal_memset(&rx_word_config, 0, sizeof(cprif_cpri_rx_fast_eth_word_config_t)); 5447 5448 rx_word_config.sub_channel_start = config_info->schan_start ; 5449 rx_word_config.sub_channel_size = config_info->schan_size ; 5450 rx_word_config.cw_sel = config_info->cw_sel ; 5451 rx_word_config.cw_size = config_info->cw_size ; 5452 _SOC_IF_ERR_EXIT 5453 (cprif_drv_cpri_port_rx_cw_fast_eth_word_config_set(unit, port, &rx_word_config)); 5454 5455 rx_config.queue_num = config_info->queue_num ; 5456 rx_config.ignore_fcs_err = config_info->no_fcs_err_check ; 5457 rx_config.min_packet_drop = config_info->min_packet_drop ; 5458 rx_config.max_packet_drop = config_info->max_packet_drop ; 5459 rx_config.min_packet_size = config_info->min_packet_size ; 5460 rx_config.max_packet_size = config_info->max_packet_size ; 5461 rx_config.strip_crc = config_info->strip_crc; 5462 5463 _SOC_IF_ERR_EXIT 5464 (cprif_drv_cpri_port_rx_cw_fast_eth_config_set(unit, port, &rx_config)); 5465 5466 sal_memset(&tx_config, 0, sizeof(cprif_cpri_tx_fast_eth_config_t)); 5467 tx_config.sub_channel_start = config_info->schan_start ; 5468 tx_config.sub_channel_size = config_info->schan_size ; 5469 tx_config.cw_sel = config_info->cw_sel ; 5470 tx_config.cw_size = config_info->cw_size ; 5471 tx_config.queue_num = config_info->queue_num ; 5472 tx_config.min_ipg = config_info->min_ipg; 5473 _cprimod_to_cprif_fast_eth_crc_mode(config_info->tx_crc_mode, &tx_config.crc_mode); 5474 _SOC_IF_ERR_EXIT 5475 (cprif_drv_cpri_port_tx_cw_fast_eth_config_set(unit, port, &tx_config)); 5476 exit: 5477 SOC_FUNC_RETURN; 5478 5479 } 5480 5481 int cprif_cpri_port_cw_fast_eth_config_get(int unit, int port, cprimod_fast_eth_config_info_t* config_info) 5482 { 5483 cprif_cpri_rx_fast_eth_config_t rx_config; 5484 cprif_cpri_rx_fast_eth_word_config_t rx_word_config; 5485 cprif_cpri_tx_fast_eth_config_t tx_config; 5486 SOC_INIT_FUNC_DEFS; 5487 5488 5489 sal_memset(&rx_config, 0, sizeof(cprif_cpri_rx_fast_eth_config_t)); 5490 sal_memset(&rx_word_config, 0, sizeof(cprif_cpri_rx_fast_eth_word_config_t)); 5491 5492 _SOC_IF_ERR_EXIT 5493 (cprif_drv_cpri_port_rx_cw_fast_eth_word_config_get(unit, port, &rx_word_config)); 5494 5495 config_info->schan_start = rx_word_config.sub_channel_start; 5496 config_info->schan_size = rx_word_config.sub_channel_size; 5497 config_info->cw_sel = rx_word_config.cw_sel; 5498 config_info->cw_size = rx_word_config.cw_size; 5499 5500 _SOC_IF_ERR_EXIT 5501 (cprif_drv_cpri_port_rx_cw_fast_eth_config_get(unit, port, &rx_config)); 5502 5503 config_info->queue_num = rx_config.queue_num; 5504 config_info->no_fcs_err_check = rx_config.ignore_fcs_err; 5505 config_info->min_packet_drop = rx_config.min_packet_drop; 5506 config_info->max_packet_drop = rx_config.max_packet_drop; 5507 config_info->min_packet_size = rx_config.min_packet_size; 5508 config_info->max_packet_size = rx_config.max_packet_size; 5509 config_info->strip_crc = rx_config.strip_crc; 5510 5511 5512 sal_memset(&tx_config, 0, sizeof(cprif_cpri_tx_fast_eth_config_t)); 5513 _SOC_IF_ERR_EXIT 5514 (cprif_drv_cpri_port_tx_cw_fast_eth_config_get(unit, port, &tx_config)); 5515 5516 config_info->schan_start = tx_config.sub_channel_start; 5517 config_info->schan_size = tx_config.sub_channel_size; 5518 config_info->cw_sel = tx_config.cw_sel; 5519 config_info->cw_size = tx_config.cw_size; 5520 config_info->queue_num = tx_config.queue_num; 5521 config_info->min_ipg = tx_config.min_ipg; 5522 _cprif_to_cprimod_fast_eth_crc_mode(tx_config.crc_mode,&config_info->tx_crc_mode); 5523 exit: 5524 SOC_FUNC_RETURN; 5525 } 5526 5527 5528 static 5529 void _cprimod_to_cprif_vsd_control_schan_num_bytes( cprimod_cpri_vsd_control_subchan_num_bytes_t cprimod_mode, uint32* cprif_mode) 5530 { 5531 switch (cprimod_mode) { 5532 case CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1: 5533 *cprif_mode = CPRIF_VSD_SCHAN_NUM_OF_BYTES_1; 5534 break; 5535 case CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2: 5536 *cprif_mode = CPRIF_VSD_SCHAN_NUM_OF_BYTES_2; 5537 break; 5538 case CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4: 5539 *cprif_mode = CPRIF_VSD_SCHAN_NUM_OF_BYTES_4; 5540 break; 5541 default: 5542 *cprif_mode = CPRIF_VSD_SCHAN_NUM_OF_BYTES_1; 5543 break; 5544 } 5545 } 5546 5547 static 5548 void _cprif_to_cprimod_vsd_control_schan_num_bytes( uint32 cprif_mode, cprimod_cpri_vsd_control_subchan_num_bytes_t *cprimod_mode) 5549 { 5550 switch (cprif_mode) { 5551 case CPRIF_VSD_SCHAN_NUM_OF_BYTES_1: 5552 *cprimod_mode = CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1; 5553 break; 5554 case CPRIF_VSD_SCHAN_NUM_OF_BYTES_2: 5555 *cprimod_mode = CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2; 5556 break; 5557 case CPRIF_VSD_SCHAN_NUM_OF_BYTES_4: 5558 *cprimod_mode = CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4; 5559 break; 5560 default: 5561 *cprimod_mode = CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1; 5562 break; 5563 } 5564 } 5565 5566 static 5567 void _cprimod_to_cprif_vsd_control_flow_num_bytes( cprimod_cpri_vsd_control_flow_num_bytes_t cprimod_mode, uint32* cprif_mode) 5568 { 5569 switch (cprimod_mode) { 5570 case CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_2: 5571 *cprif_mode = CPRIF_VSD_FLOW_NUM_OF_BYTES_2; 5572 break; 5573 case CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_4: 5574 *cprif_mode = CPRIF_VSD_FLOW_NUM_OF_BYTES_4; 5575 break; 5576 default: 5577 *cprif_mode = CPRIF_VSD_FLOW_NUM_OF_BYTES_2; 5578 break; 5579 } 5580 } 5581 5582 static 5583 void _cprif_to_cprimod_vsd_control_flow_num_bytes( uint32 cprif_mode , cprimod_cpri_vsd_control_flow_num_bytes_t *cprimod_mode) 5584 { 5585 switch (cprif_mode) { 5586 case CPRIF_VSD_FLOW_NUM_OF_BYTES_2: 5587 *cprimod_mode = CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_2; 5588 break; 5589 case CPRIF_VSD_FLOW_NUM_OF_BYTES_4: 5590 *cprimod_mode = CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_4; 5591 break; 5592 default: 5593 *cprimod_mode = CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_2; 5594 break; 5595 } 5596 } 5597 5598 int cprif_cpri_port_rx_vsd_cw_config_set(int unit, int port, const cprimod_cpri_rx_vsd_config_info_t* config_info) 5599 { 5600 cprif_cpri_vsd_config_t config; 5601 SOC_INIT_FUNC_DEFS; 5602 5603 5604 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_config_t)); 5605 5606 config.sub_channel_start = config_info->subchan_start ; 5607 config.sub_channel_size = config_info->subchan_size ; 5608 config.sub_channel_steps = config_info->subchan_steps ; 5609 config.queue_num = config_info->queue_num ; 5610 5611 _cprimod_to_cprif_vsd_control_schan_num_bytes(config_info->subchan_bytes, 5612 &config.sub_channel_num_bytes); 5613 5614 _cprimod_to_cprif_vsd_control_flow_num_bytes(config_info->flow_bytes, 5615 &config.flow_bytes); 5616 config.byte_order = CPRIF_VSD_CTRL_BYTE_NO_SWAP ; 5617 5618 COMPILER_64_SET(config.rsvd_mask[0],config_info->rsvd_sector_mask[1],config_info->rsvd_sector_mask[0]); 5619 COMPILER_64_SET(config.rsvd_mask[1],config_info->rsvd_sector_mask[3],config_info->rsvd_sector_mask[2]); 5620 5621 _SOC_IF_ERR_EXIT 5622 (cprif_drv_rx_vsd_ctrl_config_set(unit, port, &config)); 5623 exit: 5624 SOC_FUNC_RETURN; 5625 5626 } 5627 5628 int cprif_cpri_port_rx_vsd_cw_config_get(int unit, int port, cprimod_cpri_rx_vsd_config_info_t* config_info) 5629 { 5630 cprif_cpri_vsd_config_t config; 5631 SOC_INIT_FUNC_DEFS; 5632 5633 5634 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_config_t)); 5635 5636 _SOC_IF_ERR_EXIT 5637 (cprif_drv_rx_vsd_ctrl_config_get(unit, port, &config)); 5638 5639 config_info->subchan_start = config.sub_channel_start; 5640 config_info->subchan_size = config.sub_channel_size; 5641 config_info->subchan_steps = config.sub_channel_steps; 5642 config_info->queue_num = config.queue_num; 5643 5644 _cprif_to_cprimod_vsd_control_schan_num_bytes(config.sub_channel_num_bytes, 5645 &config_info->subchan_bytes); 5646 5647 _cprif_to_cprimod_vsd_control_flow_num_bytes(config.flow_bytes, 5648 &config_info->flow_bytes); 5649 5650 config_info->rsvd_sector_mask[0] = COMPILER_64_LO(config.rsvd_mask[0]); 5651 config_info->rsvd_sector_mask[1] = COMPILER_64_HI(config.rsvd_mask[0]); 5652 config_info->rsvd_sector_mask[2] = COMPILER_64_LO(config.rsvd_mask[1]); 5653 config_info->rsvd_sector_mask[3] = COMPILER_64_HI(config.rsvd_mask[1]); 5654 5655 exit: 5656 SOC_FUNC_RETURN; 5657 } 5658 5659 int cprif_cpri_port_rx_vsd_ctrl_flow_add(int unit, int port, uint32 group_id, const cprimod_cpri_rx_vsd_flow_info_t* config_info) 5660 { 5661 uint32 rsvd_mask[4]={0}; 5662 uint32 ctrl_mask[4]={0}; 5663 uint32 grp_ptr_mask[2]={0}; 5664 uint32 valid_group_mask[2]={0}; 5665 uint32 grp_ptr_index=0; 5666 uint32 tag_id; 5667 int index=0; 5668 uint32 sector=0; 5669 uint32 section=0; 5670 uint32 sector_num[CPRIF_VSD_CTRL_MAX_GROUP_SIZE]; 5671 uint32 copy_id; 5672 cprif_cpri_rx_vsd_ctrl_flow_config_t flow_config; 5673 uint32 group=0; 5674 uint32 num_sector=0; 5675 5676 SOC_INIT_FUNC_DEFS; 5677 5678 if (group_id > CPRIF_VSD_CTRL_NUM_GROUPS) { 5679 LOG_CLI(("VSD CTRL group_id =%d is out of range.\n",group_id)); 5680 return SOC_E_PARAM; 5681 } 5682 5683 _SOC_IF_ERR_EXIT 5684 (cprif_drv_rx_vsd_ctrl_rsvd_mask_get(unit, port, rsvd_mask)); 5685 5686 if (config_info->num_sector > CPRIF_VSD_CTRL_MAX_GROUP_SIZE) { 5687 return SOC_E_PARAM; 5688 } 5689 5690 for ( index=0 ; index < config_info->num_sector ; index++) { 5691 5692 if (config_info->section_num[index] >= CPRIF_VSD_CTRL_MAX_NUM_SECTION){ 5693 /* if sector has illegal number, error and get out */ 5694 return SOC_E_PARAM; 5695 } 5696 if (!CPRIF_PBMP_IS_SET(rsvd_mask, config_info->section_num[index])) { 5697 /* if sector is not reserved, error and get out */ 5698 return SOC_E_PARAM; 5699 } 5700 5701 /* find sector number */ 5702 sector = 0; 5703 for (section = 0; section <= config_info->section_num[index]; section++) 5704 { 5705 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 5706 sector++; 5707 } 5708 } 5709 sector_num[index] = sector -1; 5710 } 5711 5712 _SOC_IF_ERR_EXIT 5713 (cprif_drv_rx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 5714 5715 _SOC_IF_ERR_EXIT 5716 (cprif_drv_rx_vsd_ctrl_ctrl_mask_get(unit, port, copy_id, ctrl_mask)); 5717 5718 /* find valid group list. */ 5719 sector = 0; 5720 for ( section = 0 ; (section < CPRIF_VSD_CTRL_MAX_NUM_SECTION) && (sector < CPRIF_VSD_CTRL_MAX_NUM_SECTOR); section++) { 5721 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 5722 if (CPRIF_PBMP_IS_SET(ctrl_mask, section)) { 5723 /* This is valid sector. */ 5724 _SOC_IF_ERR_EXIT 5725 (cprif_drv_rx_vsd_ctrl_flow_config_get(unit, port, sector, &flow_config)); 5726 5727 if (flow_config.group_id == group_id) { 5728 _SOC_EXIT_WITH_ERR 5729 (SOC_E_PARAM, ("The requested group id %d is already configured. Delete first.\n",group_id)); 5730 } 5731 5732 CPRIF_PBMP_IDX_MARK(valid_group_mask, flow_config.group_id); 5733 } 5734 sector++; 5735 } 5736 } 5737 5738 /* marked all used grp ptr. */ 5739 for ( group = 0 ; group < CPRIF_VSD_CTRL_NUM_GROUPS; group++) { 5740 if (CPRIF_PBMP_IS_SET(valid_group_mask, group)){ 5741 _SOC_IF_ERR_EXIT 5742 (cprif_drv_rx_vsd_ctrl_group_config_get(unit, port, group, &tag_id, &grp_ptr_index)); 5743 5744 _SOC_IF_ERR_EXIT 5745 (cprif_drv_rx_vsd_ctrl_group_num_sector_get(unit, port, group, &num_sector)); 5746 for(index = 0; index < (num_sector + 1); index++){ 5747 CPRIF_PBMP_IDX_MARK(grp_ptr_mask, grp_ptr_index + index); 5748 } 5749 } 5750 } 5751 5752 /* get the grp ptr space. */ 5753 _SOC_IF_ERR_EXIT 5754 (cprif_drv_allocate_grp_ptr(grp_ptr_mask, config_info->num_sector, &grp_ptr_index)); 5755 5756 _SOC_IF_ERR_EXIT 5757 (cprif_drv_rx_vsd_ctrl_group_num_sector_set(unit, port, group_id, config_info->num_sector-1)); 5758 5759 _SOC_IF_ERR_EXIT 5760 (cprif_drv_rx_vsd_ctrl_group_config_set(unit, port, group_id, config_info->tag_id, grp_ptr_index)); 5761 sal_memset(&flow_config, 0, sizeof(cprif_cpri_rx_vsd_ctrl_flow_config_t)); 5762 5763 flow_config.group_id = group_id; 5764 flow_config.hyper_frame_number = config_info->hyper_frame_number; 5765 flow_config.hyper_frame_modulo = config_info->hyper_frame_modulo; 5766 flow_config.filter_zero_data = config_info->filter_zero_data? 1:0; 5767 5768 5769 for(index = 0; index < config_info->num_sector; index++){ 5770 5771 _SOC_IF_ERR_EXIT 5772 (cprif_drv_rx_vsd_ctrl_flow_config_set(unit,port, 5773 sector_num[index], 5774 &flow_config)); 5775 5776 _SOC_IF_ERR_EXIT 5777 (cprif_drv_rx_vsd_ctrl_group_assign_ptr_set(unit, port, 5778 grp_ptr_index + index, 5779 sector_num[index])); 5780 } 5781 5782 /* add ctrl_mask with new bits. */ 5783 for ( index=0 ; index < config_info->num_sector ; index++) { 5784 CPRIF_PBMP_IDX_MARK(ctrl_mask, config_info->section_num[index]); 5785 } 5786 5787 /* update the ctrl mask to alternate location and set the active copy. */ 5788 5789 _SOC_IF_ERR_EXIT 5790 (cprif_drv_rx_vsd_ctrl_ctrl_mask_set(unit, port, (copy_id == 0) ? 1:0, ctrl_mask)); 5791 5792 _SOC_IF_ERR_EXIT 5793 (cprif_drv_rx_vsd_ctrl_copy_id_set(unit, port, (copy_id == 0) ? 1:0)); 5794 5795 exit: 5796 SOC_FUNC_RETURN; 5797 5798 } 5799 5800 int cprif_cpri_port_rx_vsd_ctrl_flow_delete (int unit, int port, uint32 group_id) 5801 { 5802 uint32 rsvd_mask[4]={0}; 5803 uint32 ctrl_mask[4]={0}; 5804 uint32 sector=0; 5805 uint32 section=0; 5806 uint32 copy_id; 5807 cprif_cpri_rx_vsd_ctrl_flow_config_t flow_config; 5808 5809 SOC_INIT_FUNC_DEFS; 5810 5811 if (group_id > CPRIF_VSD_CTRL_NUM_GROUPS) { 5812 LOG_CLI(("VSD CTRL group_id =%d is out of range.\n",group_id)); 5813 return SOC_E_PARAM; 5814 } 5815 5816 _SOC_IF_ERR_EXIT 5817 (cprif_drv_rx_vsd_ctrl_rsvd_mask_get(unit, port, rsvd_mask)); 5818 5819 _SOC_IF_ERR_EXIT 5820 (cprif_drv_rx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 5821 5822 _SOC_IF_ERR_EXIT 5823 (cprif_drv_rx_vsd_ctrl_ctrl_mask_get(unit, port, copy_id, ctrl_mask)); 5824 5825 /* unmark ctrl_mask with section belong to the group.. */ 5826 sector = 0; 5827 for ( section = 0 ; (section < CPRIF_VSD_CTRL_MAX_NUM_SECTION) && (sector < CPRIF_VSD_CTRL_MAX_NUM_SECTOR); section++) { 5828 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 5829 if (CPRIF_PBMP_IS_SET(ctrl_mask, section)) { 5830 /* This is valid sector. */ 5831 _SOC_IF_ERR_EXIT 5832 (cprif_drv_rx_vsd_ctrl_flow_config_get(unit, port, sector, &flow_config)); 5833 5834 if (flow_config.group_id == group_id) { 5835 CPRIF_PBMP_IDX_UNMARK(ctrl_mask, section); 5836 } 5837 } 5838 sector++; 5839 } 5840 } 5841 5842 /* update the ctrl mask to alternate location and set the active copy. */ 5843 _SOC_IF_ERR_EXIT 5844 (cprif_drv_rx_vsd_ctrl_ctrl_mask_set(unit, port, (copy_id == 0) ? 1:0, ctrl_mask)); 5845 5846 _SOC_IF_ERR_EXIT 5847 (cprif_drv_rx_vsd_ctrl_copy_id_set(unit, port, (copy_id == 0) ? 1:0)); 5848 5849 exit: 5850 SOC_FUNC_RETURN; 5851 5852 } 5853 5854 int cprif_cpri_port_rx_vsd_ctrl_flow_get(int unit, int port, uint32 group_id, cprimod_cpri_rx_vsd_flow_info_t* config_info) 5855 { 5856 int sector=-1; 5857 int section=0; 5858 int index=0; 5859 uint32 num_sector=0; 5860 uint32 grp_ptr_index=0; 5861 uint32 sector_num; 5862 uint32 sector_mask[2]={0}; 5863 uint32 valid_sector_mask[2]={0}; 5864 uint32 valid_group_mask[4]={0}; 5865 uint32 rsvd_mask[4]={0}; 5866 uint32 ctrl_mask[4]={0}; 5867 cprif_cpri_rx_vsd_ctrl_flow_config_t flow_config; 5868 uint32 copy_id=0; 5869 5870 SOC_INIT_FUNC_DEFS; 5871 5872 if (group_id > CPRIF_VSD_CTRL_NUM_GROUPS) { 5873 LOG_CLI(("VSD CTRL group_id =%d is out of range.\n",group_id)); 5874 return SOC_E_PARAM; 5875 } 5876 5877 _SOC_IF_ERR_EXIT 5878 (cprif_drv_rx_vsd_ctrl_rsvd_mask_get(unit, port, rsvd_mask)); 5879 5880 _SOC_IF_ERR_EXIT 5881 (cprif_drv_rx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 5882 5883 _SOC_IF_ERR_EXIT 5884 (cprif_drv_rx_vsd_ctrl_ctrl_mask_get(unit, port, copy_id, ctrl_mask)); 5885 5886 /* find valid sector list and group list.*/ 5887 sector = 0; 5888 for ( section = 0 ; (section < CPRIF_VSD_CTRL_MAX_NUM_SECTION) && (sector < CPRIF_VSD_CTRL_MAX_NUM_SECTOR); section++) { 5889 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 5890 if (CPRIF_PBMP_IS_SET(ctrl_mask, section)) { 5891 /* This is valid sector. Mark it. */ 5892 CPRIF_PBMP_IDX_MARK(valid_sector_mask, sector); 5893 _SOC_IF_ERR_EXIT 5894 (cprif_drv_rx_vsd_ctrl_flow_config_get(unit, port, sector, &flow_config)); 5895 CPRIF_PBMP_IDX_MARK(valid_group_mask, flow_config.group_id); 5896 5897 } 5898 sector++; 5899 } 5900 } 5901 5902 if (CPRIF_PBMP_IS_SET(valid_group_mask, group_id)) { 5903 _SOC_IF_ERR_EXIT 5904 (cprif_drv_rx_vsd_ctrl_group_config_get(unit, port, 5905 group_id, 5906 &(config_info->tag_id), 5907 &grp_ptr_index)); 5908 5909 _SOC_IF_ERR_EXIT 5910 (cprif_drv_rx_vsd_ctrl_group_num_sector_get(unit, port, 5911 group_id, 5912 &num_sector)); 5913 5914 for (index = 0; index < num_sector+1; index++){ 5915 5916 _SOC_IF_ERR_EXIT 5917 (cprif_drv_rx_vsd_ctrl_group_assign_ptr_get(unit, port, 5918 grp_ptr_index + index, 5919 §or_num)); 5920 CPRIF_PBMP_IDX_MARK(sector_mask, sector_num); 5921 _SOC_IF_ERR_EXIT 5922 (cprif_drv_rx_vsd_ctrl_flow_config_get(unit,port, 5923 sector_num, 5924 &flow_config)); 5925 } 5926 5927 config_info->hyper_frame_number = flow_config.hyper_frame_number; 5928 config_info->hyper_frame_modulo = flow_config.hyper_frame_modulo; 5929 config_info->filter_zero_data = flow_config.filter_zero_data; 5930 5931 /* 5932 * convert sector number to section number. 5933 */ 5934 sector = 0; 5935 index = 0; 5936 for ( section = 0 ; (section < CPRIF_VSD_CTRL_MAX_NUM_SECTION) && (sector < CPRIF_VSD_CTRL_MAX_NUM_SECTOR); section++) { 5937 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 5938 if (CPRIF_PBMP_IS_SET(sector_mask, sector) && 5939 (index < CPRIF_VSD_CTRL_MAX_GROUP_SIZE)) { 5940 config_info->section_num[index] = section; 5941 index++; 5942 } 5943 sector++; 5944 } 5945 } 5946 config_info->num_sector = index; 5947 } else { 5948 LOG_CLI(("The requested group id %d is not configured.\n",group_id)); 5949 return SOC_E_NOT_FOUND; 5950 } 5951 exit: 5952 SOC_FUNC_RETURN; 5953 } 5954 5955 int cprif_encap_control_queue_tag_to_flow_id_map_set(int unit, int port, uint32 tag_id, uint32 flow_id) 5956 { 5957 SOC_INIT_FUNC_DEFS; 5958 5959 5960 if (tag_id >= CPRIF_TAG_FLOW_MAP_MAX) { 5961 LOG_CLI(("Tag to Flow MaP TAG_ID = %d is out of range.\n",tag_id)); 5962 return SOC_E_PARAM; 5963 } 5964 5965 _SOC_IF_ERR_EXIT 5966 (cprif_drv_encap_tag_to_flow_id_set(unit, port, tag_id, flow_id)); 5967 5968 exit: 5969 SOC_FUNC_RETURN; 5970 5971 } 5972 5973 int cprif_encap_control_queue_tag_to_flow_id_map_get(int unit, int port, uint32 tag_id, uint32* flow_id) 5974 { 5975 SOC_INIT_FUNC_DEFS; 5976 5977 _SOC_IF_ERR_EXIT 5978 (cprif_drv_encap_tag_to_flow_id_get(unit, port, tag_id, flow_id)); 5979 exit: 5980 SOC_FUNC_RETURN; 5981 5982 } 5983 5984 int cprif_cpri_port_tx_vsd_cw_config_set(int unit, int port, const cprimod_cpri_tx_vsd_config_info_t* config_info) 5985 { 5986 cprif_cpri_vsd_config_t config; 5987 SOC_INIT_FUNC_DEFS; 5988 5989 5990 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_config_t)); 5991 5992 config.sub_channel_start = config_info->subchan_start ; 5993 config.sub_channel_size = config_info->subchan_size ; 5994 config.sub_channel_steps = config_info->subchan_steps ; 5995 config.queue_num = config_info->queue_num ; 5996 5997 _cprimod_to_cprif_vsd_control_schan_num_bytes(config_info->subchan_bytes, 5998 &config.sub_channel_num_bytes); 5999 6000 _cprimod_to_cprif_vsd_control_flow_num_bytes(config_info->flow_bytes, 6001 &config.flow_bytes); 6002 config.byte_order = config_info->byte_order_swap? CPRIF_VSD_CTRL_BYTE_SWAP : CPRIF_VSD_CTRL_BYTE_NO_SWAP ; 6003 6004 COMPILER_64_SET(config.rsvd_mask[0],config_info->rsvd_sector_mask[1],config_info->rsvd_sector_mask[0]); 6005 COMPILER_64_SET(config.rsvd_mask[1],config_info->rsvd_sector_mask[3],config_info->rsvd_sector_mask[2]); 6006 6007 _SOC_IF_ERR_EXIT 6008 (cprif_drv_tx_vsd_ctrl_config_set(unit, port, &config)); 6009 exit: 6010 SOC_FUNC_RETURN; 6011 } 6012 6013 int cprif_cpri_port_tx_vsd_cw_config_get(int unit, int port, cprimod_cpri_tx_vsd_config_info_t* config_info) 6014 { 6015 cprif_cpri_vsd_config_t config; 6016 SOC_INIT_FUNC_DEFS; 6017 6018 6019 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_config_t)); 6020 6021 _SOC_IF_ERR_EXIT 6022 (cprif_drv_tx_vsd_ctrl_config_get(unit, port, &config)); 6023 6024 config_info->subchan_start = config.sub_channel_start; 6025 config_info->subchan_size = config.sub_channel_size; 6026 config_info->subchan_steps = config.sub_channel_steps; 6027 config_info->queue_num = config.queue_num; 6028 config_info->byte_order_swap= (config.byte_order == CPRIF_VSD_CTRL_BYTE_SWAP)? 1 : 0;; 6029 6030 _cprif_to_cprimod_vsd_control_schan_num_bytes(config.sub_channel_num_bytes, 6031 &config_info->subchan_bytes); 6032 6033 _cprif_to_cprimod_vsd_control_flow_num_bytes(config.flow_bytes,&config_info->flow_bytes); 6034 6035 config_info->rsvd_sector_mask[0] = COMPILER_64_LO(config.rsvd_mask[0]); 6036 config_info->rsvd_sector_mask[1] = COMPILER_64_HI(config.rsvd_mask[0]); 6037 config_info->rsvd_sector_mask[2] = COMPILER_64_LO(config.rsvd_mask[1]); 6038 config_info->rsvd_sector_mask[3] = COMPILER_64_HI(config.rsvd_mask[1]); 6039 6040 exit: 6041 6042 SOC_FUNC_RETURN; 6043 6044 } 6045 6046 int cprif_cpri_port_tx_vsd_ctrl_flow_add(int unit, int port, uint32 group_id, uint32* group_list, const cprimod_cpri_tx_vsd_flow_info_t* config_info) 6047 { 6048 6049 uint32 rsvd_mask[4]={0}; 6050 uint32 ctrl_mask[4]={0}; 6051 uint32 grp_ptr_mask[2]={0}; 6052 uint32 grp_ptr_index=0; 6053 int index=0; 6054 uint32 sector=0; 6055 uint32 section=0; 6056 uint32 sector_num[CPRIF_VSD_CTRL_MAX_GROUP_SIZE]; 6057 uint32 copy_id; 6058 cprif_cpri_tx_vsd_ctrl_flow_config_t flow_config; 6059 uint32 group=0; 6060 uint32 num_sector=0; 6061 SOC_INIT_FUNC_DEFS; 6062 6063 if (group_id > CPRIF_VSD_CTRL_NUM_GROUPS) { 6064 LOG_CLI(("VSD CTRL group_id =%d is out of range.\n",group_id)); 6065 return SOC_E_PARAM; 6066 } 6067 6068 if (CPRIF_PBMP_IS_SET(group_list, group_id)){ 6069 LOG_CLI(("VSD CTRL group_id =%d is already configured.\n",group_id)); 6070 return SOC_E_PARAM; 6071 } 6072 6073 _SOC_IF_ERR_EXIT 6074 (cprif_drv_tx_vsd_ctrl_rsvd_mask_get(unit, port, rsvd_mask)); 6075 6076 if (config_info->num_sector > CPRIF_VSD_CTRL_MAX_GROUP_SIZE) { 6077 LOG_CLI(("Num Of Sector =%d is out of range.\n",config_info->num_sector)); 6078 return SOC_E_PARAM; 6079 } 6080 6081 for ( index=0 ; index < config_info->num_sector ; index++) { 6082 6083 if (config_info->section_num[index] >= CPRIF_VSD_CTRL_MAX_NUM_SECTION){ 6084 /* if sector has illegal number, error and get out */ 6085 return SOC_E_PARAM; 6086 } 6087 if (!CPRIF_PBMP_IS_SET(rsvd_mask, config_info->section_num[index])) { 6088 /* if sector is not reserved, error and get out */ 6089 return SOC_E_PARAM; 6090 } 6091 6092 /* find sector number */ 6093 sector = 0; 6094 for (section = 0; section <= config_info->section_num[index]; section++) 6095 { 6096 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 6097 sector++; 6098 } 6099 } 6100 sector_num[index] = sector -1; 6101 } 6102 6103 _SOC_IF_ERR_EXIT 6104 (cprif_drv_tx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 6105 6106 _SOC_IF_ERR_EXIT 6107 (cprif_drv_tx_vsd_ctrl_ctrl_mask_get(unit, port, copy_id, ctrl_mask)); 6108 6109 /* marked all used grp ptr. */ 6110 for (group = 0 ; group < CPRIF_VSD_CTRL_NUM_GROUPS; group++) { 6111 if (CPRIF_PBMP_IS_SET(group_list, group)){ 6112 _SOC_IF_ERR_EXIT 6113 (cprif_drv_tx_vsd_ctrl_group_config_get(unit, port, 6114 group, 6115 &num_sector, 6116 &grp_ptr_index)); 6117 for(index = 0; index < (num_sector + 1); index++){ 6118 CPRIF_PBMP_IDX_MARK(grp_ptr_mask, grp_ptr_index + index); 6119 } 6120 } 6121 } 6122 6123 6124 /* get the grp ptr space. */ 6125 _SOC_IF_ERR_EXIT 6126 (cprif_drv_allocate_grp_ptr(grp_ptr_mask, config_info->num_sector, &grp_ptr_index)); 6127 6128 _SOC_IF_ERR_EXIT 6129 (cprif_drv_tx_vsd_ctrl_group_config_set(unit, port, group_id, config_info->num_sector-1, grp_ptr_index)); 6130 6131 sal_memset(&flow_config, 0, sizeof(cprif_cpri_tx_vsd_ctrl_flow_config_t)); 6132 6133 flow_config.hyper_frame_number = config_info->hyper_frame_number; 6134 flow_config.hyper_frame_modulo = config_info->hyper_frame_modulo; 6135 flow_config.repeat_mode = config_info->repeat_mode ? 1:0; 6136 6137 6138 for(index = 0; index < config_info->num_sector; index++){ 6139 6140 _SOC_IF_ERR_EXIT 6141 (cprif_drv_tx_vsd_ctrl_flow_config_set(unit,port, 6142 sector_num[index], 6143 &flow_config)); 6144 6145 _SOC_IF_ERR_EXIT 6146 (cprif_drv_tx_vsd_ctrl_group_assign_ptr_set(unit, port, 6147 grp_ptr_index + index, 6148 sector_num[index])); 6149 } 6150 6151 /* 6152 * Program flow id to vsd control group id mapping. 6153 */ 6154 _SOC_IF_ERR_EXIT 6155 (cprif_drv_tx_vsd_ctrl_flow_id_to_group_mapping_set(unit, port, 6156 config_info->roe_flow_id, 6157 group_id)); 6158 /* add ctrl_mask with new bits. */ 6159 for ( index=0 ; index < config_info->num_sector ; index++) { 6160 CPRIF_PBMP_IDX_MARK(ctrl_mask, config_info->section_num[index]); 6161 } 6162 6163 /* update the ctrl mask to alternate location and set the active copy. */ 6164 6165 _SOC_IF_ERR_EXIT 6166 (cprif_drv_tx_vsd_ctrl_ctrl_mask_set(unit, port, (copy_id == 0) ? 1:0, ctrl_mask)); 6167 6168 _SOC_IF_ERR_EXIT 6169 (cprif_drv_tx_vsd_ctrl_copy_id_set(unit, port, (copy_id == 0) ? 1:0)); 6170 6171 /* update the group list */ 6172 CPRIF_PBMP_IDX_MARK(group_list, group_id); 6173 exit: 6174 SOC_FUNC_RETURN; 6175 6176 } 6177 6178 int cprif_cpri_port_tx_vsd_ctrl_flow_delete(int unit, int port, uint32 group_id, uint32* group_list) 6179 { 6180 uint32 num_sector=0; 6181 uint32 grp_ptr_index; 6182 int index; 6183 int sector; 6184 int section; 6185 uint32 sector_num[CPRIF_VSD_CTRL_MAX_GROUP_SIZE]; 6186 uint32 rsvd_mask[4]={0}; 6187 uint32 ctrl_mask[4]={0}; 6188 uint32 sector_mask[2]={0}; 6189 uint32 copy_id; 6190 SOC_INIT_FUNC_DEFS; 6191 6192 if (!CPRIF_PBMP_IS_SET(group_list, group_id)){ 6193 LOG_CLI(("VSD CTRL group_id =%d is not configured.\n",group_id)); 6194 return SOC_E_PARAM; 6195 } 6196 6197 _SOC_IF_ERR_EXIT 6198 (cprif_drv_tx_vsd_ctrl_rsvd_mask_get(unit, port, rsvd_mask)); 6199 6200 _SOC_IF_ERR_EXIT 6201 (cprif_drv_tx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 6202 6203 _SOC_IF_ERR_EXIT 6204 (cprif_drv_tx_vsd_ctrl_ctrl_mask_get(unit, port, copy_id, ctrl_mask)); 6205 6206 _SOC_IF_ERR_EXIT 6207 (cprif_drv_tx_vsd_ctrl_group_config_get(unit, port, group_id, &num_sector, &grp_ptr_index)); 6208 6209 num_sector += 1; 6210 6211 for (index = 0; index < num_sector; index++){ 6212 _SOC_IF_ERR_EXIT 6213 (cprif_drv_tx_vsd_ctrl_group_assign_ptr_get(unit, port, 6214 grp_ptr_index + index, 6215 §or_num[index])); 6216 6217 CPRIF_PBMP_IDX_MARK(sector_mask, sector_num[index]); 6218 6219 } 6220 6221 sector = 0; 6222 index = 0; 6223 for ( section = 0 ; (section < CPRIF_VSD_CTRL_MAX_NUM_SECTION) && (sector < CPRIF_VSD_CTRL_MAX_NUM_SECTOR); section++) { 6224 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 6225 if (CPRIF_PBMP_IS_SET(sector_mask, sector)) { 6226 if (CPRIF_PBMP_IS_SET(ctrl_mask, section)){ 6227 CPRIF_PBMP_IDX_UNMARK(ctrl_mask,section); 6228 } 6229 } 6230 sector++; 6231 } 6232 } 6233 6234 /* update the ctrl mask to alternate location and set the active copy. */ 6235 6236 _SOC_IF_ERR_EXIT 6237 (cprif_drv_tx_vsd_ctrl_ctrl_mask_set(unit, port, (copy_id == 0) ? 1:0, ctrl_mask)); 6238 6239 _SOC_IF_ERR_EXIT 6240 (cprif_drv_tx_vsd_ctrl_copy_id_set(unit, port, (copy_id == 0) ? 1:0)); 6241 6242 /* update the group list */ 6243 CPRIF_PBMP_IDX_UNMARK(group_list, group_id); 6244 exit: 6245 SOC_FUNC_RETURN; 6246 6247 } 6248 6249 int cprif_cpri_port_tx_vsd_ctrl_flow_get(int unit, int port, uint32 group_id, uint32* group_list, cprimod_cpri_tx_vsd_flow_info_t* config_info) 6250 { 6251 uint32 num_sector=0; 6252 uint32 grp_ptr_index; 6253 uint32 group_num; 6254 int index; 6255 int sector; 6256 int section; 6257 uint32 copy_id; 6258 uint32 sector_num[CPRIF_VSD_CTRL_MAX_GROUP_SIZE]; 6259 cprif_cpri_tx_vsd_ctrl_flow_config_t flow_config; 6260 uint32 rsvd_mask[4]={0}; 6261 uint32 ctrl_mask[4]={0}; 6262 uint32 sector_mask[2]={0}; 6263 SOC_INIT_FUNC_DEFS; 6264 6265 if (!CPRIF_PBMP_IS_SET(group_list, group_id)){ 6266 LOG_CLI(("VSD CTRL group_id =%d is not configured.\n",group_id)); 6267 return SOC_E_PARAM; 6268 } 6269 _SOC_IF_ERR_EXIT 6270 (cprif_drv_tx_vsd_ctrl_rsvd_mask_get(unit, port, rsvd_mask)); 6271 6272 _SOC_IF_ERR_EXIT 6273 (cprif_drv_tx_vsd_ctrl_copy_id_get(unit, port, ©_id)); 6274 6275 _SOC_IF_ERR_EXIT 6276 (cprif_drv_tx_vsd_ctrl_ctrl_mask_get(unit, port, copy_id, ctrl_mask)); 6277 6278 6279 _SOC_IF_ERR_EXIT 6280 (cprif_drv_tx_vsd_ctrl_group_config_get(unit, port, group_id, &num_sector, &grp_ptr_index)); 6281 6282 num_sector += 1; 6283 6284 for (index = 0; index < num_sector; index++){ 6285 _SOC_IF_ERR_EXIT 6286 (cprif_drv_tx_vsd_ctrl_group_assign_ptr_get(unit, port, 6287 grp_ptr_index + index, 6288 §or_num[index])); 6289 6290 CPRIF_PBMP_IDX_MARK(sector_mask, sector_num[index]); 6291 6292 _SOC_IF_ERR_EXIT 6293 (cprif_drv_tx_vsd_ctrl_flow_config_get(unit,port, 6294 sector_num[index], 6295 &flow_config)); 6296 6297 config_info->hyper_frame_number = flow_config.hyper_frame_number; 6298 config_info->hyper_frame_modulo = flow_config.hyper_frame_modulo; 6299 config_info->repeat_mode = flow_config.repeat_mode; 6300 } 6301 6302 group_num = 0xff; 6303 for (index = 0; index < 128 ; index++){ 6304 _SOC_IF_ERR_EXIT 6305 (cprif_drv_tx_vsd_ctrl_flow_id_to_group_mapping_get(unit, port, 6306 index, 6307 &group_num)); 6308 if (group_num == group_id) { 6309 config_info->roe_flow_id = index; 6310 continue; 6311 } 6312 } 6313 6314 sector = 0; 6315 index = 0; 6316 for ( section = 0 ; (section < CPRIF_VSD_CTRL_MAX_NUM_SECTION) && (sector < CPRIF_VSD_CTRL_MAX_NUM_SECTOR); section++) { 6317 if (CPRIF_PBMP_IS_SET(rsvd_mask, section)) { 6318 if (CPRIF_PBMP_IS_SET(sector_mask, sector) && 6319 (index < num_sector)) { 6320 if (CPRIF_PBMP_IS_SET(ctrl_mask, section)) { 6321 config_info->section_num[index] = section; 6322 index++; 6323 } else { 6324 LOG_CLI(("The requested group id %d is not configured.\n",group_id)); 6325 return SOC_E_NOT_FOUND; 6326 } 6327 } 6328 sector++; 6329 } 6330 } 6331 config_info->num_sector = index; 6332 exit: 6333 SOC_FUNC_RETURN; 6334 6335 } 6336 void _cprimod_to_cprif_cw_filter_mode( cprimod_cpri_cw_filter_mode_t cprimod_mode, uint32* cprif_mode) 6337 { 6338 switch (cprimod_mode) { 6339 case CPRIMOD_CPRI_CW_FILTER_DISABLE: 6340 *cprif_mode = CPRIF_VSD_RAW_FILTER_MODE_DISABLE; 6341 break; 6342 case CPRIMOD_CPRI_CW_FILTER_NON_ZERO: 6343 *cprif_mode = CPRIF_VSD_RAW_FILTER_MODE_NON_ZERO; 6344 break; 6345 case CPRIMOD_CPRI_CW_FILTER_PERIODIC: 6346 *cprif_mode = CPRIF_VSD_RAW_FILTER_MODE_PERIODIC; 6347 break; 6348 case CPRIMOD_CPRI_CW_FILTER_CHANGE: 6349 *cprif_mode = CPRIF_VSD_RAW_FILTER_MODE_CHANGE; 6350 break; 6351 case CPRIMOD_CPRI_CW_FILTER_PATTERN_MATCH: 6352 *cprif_mode = CPRIF_VSD_RAW_FILTER_MODE_PATTERN_MATCH; 6353 break; 6354 default: 6355 *cprif_mode = CPRIF_VSD_RAW_FILTER_MODE_DISABLE; 6356 break; 6357 } 6358 } 6359 6360 void _cprif_to_cprimod_cw_filter_mode( uint32 cprif_mode , cprimod_cpri_cw_filter_mode_t *cprimod_mode) 6361 { 6362 switch (cprif_mode) { 6363 case CPRIF_VSD_RAW_FILTER_MODE_DISABLE: 6364 *cprimod_mode = CPRIMOD_CPRI_CW_FILTER_DISABLE; 6365 break; 6366 case CPRIF_VSD_RAW_FILTER_MODE_NON_ZERO: 6367 *cprimod_mode = CPRIMOD_CPRI_CW_FILTER_NON_ZERO; 6368 break; 6369 case CPRIF_VSD_RAW_FILTER_MODE_PERIODIC: 6370 *cprimod_mode = CPRIMOD_CPRI_CW_FILTER_PERIODIC; 6371 break; 6372 case CPRIF_VSD_RAW_FILTER_MODE_CHANGE: 6373 *cprimod_mode = CPRIMOD_CPRI_CW_FILTER_CHANGE; 6374 break; 6375 case CPRIF_VSD_RAW_FILTER_MODE_PATTERN_MATCH: 6376 *cprimod_mode = CPRIMOD_CPRI_CW_FILTER_PATTERN_MATCH; 6377 break; 6378 default: 6379 *cprimod_mode = CPRIMOD_CPRI_CW_FILTER_DISABLE; 6380 break; 6381 } 6382 } 6383 6384 int cprif_cpri_port_rx_vsd_raw_config_set(int unit, int port, uint32 index, const cprimod_cpri_rx_vsd_raw_config_t* config_info) 6385 { 6386 cprif_cpri_vsd_raw_config_t config; 6387 cprif_cpri_rx_vsd_raw_filter_config_t filter_config; 6388 SOC_INIT_FUNC_DEFS; 6389 6390 if (index >= CPRIF_VSD_RAW_MAX_GROUP) { 6391 LOG_CLI(("VSD RAW index =%d is out of range.\n",index)); 6392 return SOC_E_PARAM; 6393 } 6394 6395 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_raw_config_t)); 6396 config.schan_start = config_info->schan_start; 6397 config.schan_size = config_info->schan_size; 6398 config.cw_select = config_info->cw_sel; 6399 config.cw_size = config_info->cw_size; 6400 6401 _SOC_IF_ERR_EXIT 6402 (cprif_drv_rx_vsd_raw_config_set(unit, port, index, &config)); 6403 6404 sal_memset(&filter_config, 0, sizeof(cprif_cpri_rx_vsd_raw_filter_config_t)); 6405 6406 _cprimod_to_cprif_cw_filter_mode(config_info->filter_mode, &filter_config.filter_mode); 6407 6408 filter_config.hfn_index = config_info->hyper_frame_index; 6409 filter_config.hfn_modulo = config_info->hyper_frame_modulo; 6410 filter_config.match_value = config_info->match_value; 6411 filter_config.match_offset = config_info->match_offset; 6412 filter_config.match_mask = config_info->match_mask; 6413 filter_config.queue_num = config_info->queue_num; 6414 6415 _SOC_IF_ERR_EXIT 6416 (cprif_drv_rx_vsd_raw_filter_config_set(unit, port, index, &filter_config)); 6417 6418 exit: 6419 SOC_FUNC_RETURN; 6420 6421 } 6422 6423 int cprif_cpri_port_rx_vsd_raw_config_get(int unit, int port, uint32 index, cprimod_cpri_rx_vsd_raw_config_t* config_info) 6424 { 6425 cprif_cpri_vsd_raw_config_t config; 6426 cprif_cpri_rx_vsd_raw_filter_config_t filter_config; 6427 SOC_INIT_FUNC_DEFS; 6428 6429 if (index >= CPRIF_VSD_RAW_MAX_GROUP) { 6430 LOG_CLI(("VSD RAW index =%d is out of range.\n",index)); 6431 return SOC_E_PARAM; 6432 } 6433 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_raw_config_t)); 6434 6435 _SOC_IF_ERR_EXIT 6436 (cprif_drv_rx_vsd_raw_config_get(unit, port, index, &config)); 6437 config_info->schan_start = config.schan_start; 6438 config_info->schan_size = config.schan_size; 6439 config_info->cw_sel = config.cw_select; 6440 config_info->cw_size = config.cw_size; 6441 6442 sal_memset(&filter_config, 0, sizeof(cprif_cpri_rx_vsd_raw_filter_config_t)); 6443 6444 _SOC_IF_ERR_EXIT 6445 (cprif_drv_rx_vsd_raw_filter_config_get(unit, port, index, &filter_config)); 6446 config_info->filter_mode = filter_config.filter_mode; 6447 6448 _cprif_to_cprimod_cw_filter_mode(filter_config.filter_mode, &config_info->filter_mode); 6449 config_info->hyper_frame_index = filter_config.hfn_index; 6450 config_info->hyper_frame_modulo = filter_config.hfn_modulo; 6451 config_info->match_value = filter_config.match_value; 6452 config_info->match_offset = filter_config.match_offset; 6453 config_info->match_mask = filter_config.match_mask; 6454 config_info->queue_num = filter_config.queue_num; 6455 6456 exit: 6457 SOC_FUNC_RETURN; 6458 6459 } 6460 6461 int cprif_cpri_port_tx_vsd_raw_config_set(int unit, int port, uint32 index, const cprimod_cpri_tx_vsd_raw_config_t* config_info) 6462 { 6463 cprif_cpri_vsd_raw_config_t config; 6464 cprif_cpri_tx_vsd_raw_filter_config_t filter_config; 6465 SOC_INIT_FUNC_DEFS; 6466 6467 if (index >= CPRIF_VSD_RAW_MAX_GROUP) { 6468 LOG_CLI(("VSD RAW index =%d is out of range.\n",index)); 6469 return SOC_E_PARAM; 6470 } 6471 6472 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_raw_config_t)); 6473 config.schan_start = config_info->schan_start; 6474 config.schan_size = config_info->schan_size; 6475 config.cw_select = config_info->cw_sel; 6476 config.cw_size = config_info->cw_size; 6477 6478 _SOC_IF_ERR_EXIT 6479 (cprif_drv_tx_vsd_raw_config_set(unit, port, index, &config)); 6480 6481 sal_memset(&filter_config, 0, sizeof(cprif_cpri_tx_vsd_raw_filter_config_t)); 6482 6483 filter_config.queue_num = config_info->queue_num; 6484 6485 if (config_info->map_mode == CPRIMOD_CPRI_CW_MAP_MODE_ROE_FRAME){ 6486 filter_config.map_mode = CPRIF_VSD_RAW_MAP_MODE_USE_ROE_HDR; 6487 } else { 6488 filter_config.map_mode = CPRIF_VSD_RAW_MAP_MODE_USE_MODULO; 6489 } 6490 6491 if (config_info->repeat_enable) { 6492 filter_config.repeat_mode = CPRIF_CW_REPEAT_MODE_CONTINUOUS; 6493 } else { 6494 filter_config.repeat_mode = CPRIF_CW_REPEAT_MODE_ONCE; 6495 } 6496 6497 if (config_info->bfn0_filter_enable) { 6498 filter_config.bfn0_filter_enable = 1; 6499 } else { 6500 filter_config.bfn0_filter_enable = 0; 6501 } 6502 6503 if (config_info->bfn1_filter_enable) { 6504 filter_config.bfn1_filter_enable = 1; 6505 } else { 6506 filter_config.bfn1_filter_enable = 0; 6507 } 6508 6509 filter_config.hfn_index = config_info->hyper_frame_index; 6510 filter_config.hfn_modulo = config_info->hyper_frame_modulo; 6511 filter_config.idle_value = config_info->idle_value; 6512 6513 _SOC_IF_ERR_EXIT 6514 (cprif_drv_tx_vsd_raw_filter_config_set(unit, port, index, &filter_config)); 6515 exit: 6516 SOC_FUNC_RETURN; 6517 6518 } 6519 6520 int cprif_cpri_port_tx_vsd_raw_config_get(int unit, int port, uint32 index, cprimod_cpri_tx_vsd_raw_config_t* config_info) 6521 { 6522 cprif_cpri_vsd_raw_config_t config; 6523 cprif_cpri_tx_vsd_raw_filter_config_t filter_config; 6524 SOC_INIT_FUNC_DEFS; 6525 6526 if (index >= CPRIF_VSD_RAW_MAX_GROUP) { 6527 LOG_CLI(("VSD RAW index =%d is out of range.\n",index)); 6528 return SOC_E_PARAM; 6529 } 6530 6531 sal_memset(&config, 0, sizeof(cprif_cpri_vsd_raw_config_t)); 6532 6533 _SOC_IF_ERR_EXIT 6534 (cprif_drv_tx_vsd_raw_config_get(unit, port, index, &config)); 6535 config_info->schan_start = config.schan_start; 6536 config_info->schan_size = config.schan_size; 6537 config_info->cw_sel = config.cw_select; 6538 config_info->cw_size = config.cw_size; 6539 6540 sal_memset(&filter_config, 0, sizeof(cprif_cpri_tx_vsd_raw_filter_config_t)); 6541 6542 _SOC_IF_ERR_EXIT 6543 (cprif_drv_tx_vsd_raw_filter_config_get(unit, port, index, &filter_config)); 6544 6545 config_info->hyper_frame_index = filter_config.hfn_index; 6546 config_info->hyper_frame_modulo = filter_config.hfn_modulo; 6547 config_info->queue_num = filter_config.queue_num; 6548 config_info->idle_value = filter_config.idle_value; 6549 6550 if (filter_config.bfn0_filter_enable) { 6551 config_info->bfn0_filter_enable = 1; 6552 } else { 6553 config_info->bfn0_filter_enable = 0; 6554 } 6555 6556 if (filter_config.bfn1_filter_enable) { 6557 config_info->bfn1_filter_enable = 1; 6558 } else { 6559 config_info->bfn1_filter_enable = 0; 6560 } 6561 if (filter_config.repeat_mode == CPRIF_CW_REPEAT_MODE_CONTINUOUS){ 6562 config_info->repeat_enable = 1; 6563 } else { 6564 config_info->repeat_enable = 0; 6565 } 6566 if (filter_config.map_mode == CPRIF_VSD_RAW_MAP_MODE_USE_ROE_HDR) { 6567 config_info->map_mode = CPRIMOD_CPRI_CW_MAP_MODE_ROE_FRAME; 6568 } else { 6569 config_info->map_mode = CPRIMOD_CPRI_CW_MAP_MODE_PERIODIC; 6570 } 6571 6572 exit: 6573 SOC_FUNC_RETURN; 6574 6575 } 6576 6577 int cprif_cpri_port_tx_vsd_raw_filter_set(int unit, int port, uint32 bfn0_value, uint32 bfn0_mask, uint32 bfn1_value, uint32 bfn1_mask) 6578 { 6579 SOC_INIT_FUNC_DEFS; 6580 6581 _SOC_IF_ERR_EXIT 6582 (cprif_drv_tx_vsd_raw_radio_frame_filter_set(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 6583 exit: 6584 SOC_FUNC_RETURN; 6585 6586 } 6587 6588 int cprif_cpri_port_tx_vsd_raw_filter_get(int unit, int port, uint32* bfn0_value, uint32* bfn0_mask, uint32* bfn1_value, uint32* bfn1_mask) 6589 { 6590 SOC_INIT_FUNC_DEFS; 6591 6592 _SOC_IF_ERR_EXIT 6593 (cprif_drv_tx_vsd_raw_radio_frame_filter_get(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 6594 exit: 6595 SOC_FUNC_RETURN; 6596 6597 } 6598 6599 int cprif_cpri_port_rx_brcm_rsvd5_control_config_set(int unit, int port, uint32 schan_start, uint32 schan_size, uint32 queue_num, int parity_disable) 6600 { 6601 SOC_INIT_FUNC_DEFS; 6602 _SOC_IF_ERR_EXIT 6603 (cprif_drv_rx_brcm_rsvd5_config_set(unit, port,schan_start, schan_size, queue_num, parity_disable)); 6604 6605 exit: 6606 SOC_FUNC_RETURN; 6607 6608 } 6609 6610 int cprif_cpri_port_rx_brcm_rsvd5_control_config_get(int unit, int port, uint32* schan_start, uint32* schan_size, uint32* queue_num, int* parity_disable) 6611 { 6612 SOC_INIT_FUNC_DEFS; 6613 _SOC_IF_ERR_EXIT 6614 (cprif_drv_rx_brcm_rsvd5_config_get(unit, port,schan_start, schan_size, queue_num, parity_disable)); 6615 6616 exit: 6617 SOC_FUNC_RETURN; 6618 6619 } 6620 6621 int cprif_cpri_port_tx_brcm_rsvd5_control_config_set(int unit, int port, uint32 schan_start, uint32 schan_size, uint32 queue_num, int crc_enable) 6622 { 6623 SOC_INIT_FUNC_DEFS; 6624 6625 _SOC_IF_ERR_EXIT 6626 (cprif_drv_tx_brcm_rsvd5_config_set(unit, port,schan_start, schan_size, queue_num, crc_enable)); 6627 exit: 6628 SOC_FUNC_RETURN; 6629 6630 } 6631 6632 int cprif_cpri_port_tx_brcm_rsvd5_control_config_get(int unit, int port, uint32* schan_start, uint32* schan_size, uint32* queue_num, int* crc_enable) 6633 { 6634 SOC_INIT_FUNC_DEFS; 6635 6636 _SOC_IF_ERR_EXIT 6637 (cprif_drv_tx_brcm_rsvd5_config_get(unit, port,schan_start, schan_size, queue_num, crc_enable)); 6638 exit: 6639 SOC_FUNC_RETURN; 6640 6641 } 6642 6643 void _cprimod_to_cprif_gcw_mask( cprimod_cpri_gcw_mask_t cprimod_mode, uint32* cprif_mode) 6644 { 6645 switch (cprimod_mode) { 6646 case CPRIMOD_CPRI_GCW_MASK_NONE: 6647 *cprif_mode = CPRIF_GCW_MASK_NONE; 6648 break; 6649 case CPRIMOD_CPRI_GCW_MASK_LSB: 6650 *cprif_mode = CPRIF_GCW_MASK_LSB; 6651 break; 6652 case CPRIMOD_CPRI_GCW_MASK_MSB: 6653 *cprif_mode = CPRIF_GCW_MASK_MSB; 6654 break; 6655 case CPRIMOD_CPRI_GCW_MASK_BOTH: 6656 *cprif_mode = CPRIF_GCW_MASK_BOTH; 6657 break; 6658 default: 6659 *cprif_mode = CPRIF_GCW_MASK_NONE; 6660 break; 6661 } 6662 } 6663 6664 void _cprif_to_cprimod_gcw_mask( uint32 cprif_mode, cprimod_cpri_gcw_mask_t* cprimod_mode) 6665 { 6666 switch (cprif_mode) { 6667 case CPRIF_GCW_MASK_NONE: 6668 *cprimod_mode = CPRIMOD_CPRI_GCW_MASK_NONE; 6669 break; 6670 case CPRIF_GCW_MASK_LSB: 6671 *cprimod_mode = CPRIMOD_CPRI_GCW_MASK_LSB; 6672 break; 6673 case CPRIF_GCW_MASK_MSB: 6674 *cprimod_mode = CPRIMOD_CPRI_GCW_MASK_MSB; 6675 break; 6676 case CPRIF_GCW_MASK_BOTH: 6677 *cprimod_mode = CPRIMOD_CPRI_GCW_MASK_BOTH; 6678 break; 6679 default: 6680 *cprimod_mode = cprimodGcwMaskNone; 6681 break; 6682 } 6683 } 6684 6685 6686 int cprif_cpri_port_rx_gcw_config_set(int unit, int port, uint32 index, const cprimod_cpri_rx_gcw_config_t* config_info) 6687 { 6688 cprif_cpri_rx_gcw_config_t config; 6689 SOC_INIT_FUNC_DEFS; 6690 6691 if (index >= CPRIF_GCW_MAX_GROUP) { 6692 LOG_CLI(("GCW index =%d is out of range.\n",index)); 6693 return SOC_E_PARAM; 6694 } 6695 6696 sal_memset(&config, 0, sizeof(cprif_cpri_rx_gcw_config_t)); 6697 6698 config.Ns = config_info->Ns; 6699 config.Xs = config_info->Xs; 6700 config.Y = config_info->Y; 6701 config.hfn_index = config_info->hyper_frame_index; 6702 config.hfn_modulo = config_info->hyper_frame_modulo; 6703 config.match_mask = config_info->match_mask; 6704 config.match_value = config_info->match_value; 6705 6706 _cprimod_to_cprif_gcw_mask(config_info->mask, &config.mask); 6707 _cprimod_to_cprif_cw_filter_mode(config_info->filter_mode, &config.filter_mode); 6708 6709 _SOC_IF_ERR_EXIT 6710 (cprif_drv_rx_gcw_config_set(unit, port, 6711 index, &config)); 6712 exit: 6713 SOC_FUNC_RETURN; 6714 } 6715 6716 int cprif_cpri_port_rx_gcw_config_get(int unit, int port, uint32 index, cprimod_cpri_rx_gcw_config_t* config_info) 6717 { 6718 cprif_cpri_rx_gcw_config_t config; 6719 SOC_INIT_FUNC_DEFS; 6720 6721 if (index >= CPRIF_GCW_MAX_GROUP) { 6722 LOG_CLI(("GCW index =%d is out of range.\n",index)); 6723 return SOC_E_PARAM; 6724 } 6725 6726 sal_memset(&config, 0, sizeof(cprif_cpri_rx_gcw_config_t)); 6727 _SOC_IF_ERR_EXIT 6728 (cprif_drv_rx_gcw_config_get(unit, port, 6729 index, &config)); 6730 6731 config_info->Ns = config.Ns; 6732 config_info->Xs = config.Xs; 6733 config_info->Y = config.Y; 6734 config_info->hyper_frame_index = config.hfn_index; 6735 config_info->hyper_frame_modulo = config.hfn_modulo; 6736 config_info->match_mask = config.match_mask; 6737 config_info->match_value = config.match_value; 6738 6739 _cprif_to_cprimod_gcw_mask(config.mask, &config_info->mask); 6740 _cprif_to_cprimod_cw_filter_mode(config.filter_mode, &config_info->filter_mode); 6741 6742 exit: 6743 SOC_FUNC_RETURN; 6744 6745 } 6746 6747 int cprif_cpri_port_tx_gcw_config_set(int unit, int port, uint32 index, const cprimod_cpri_tx_gcw_config_t* config_info) 6748 { 6749 cprif_cpri_tx_gcw_config_t config; 6750 SOC_INIT_FUNC_DEFS; 6751 6752 if (index >= CPRIF_GCW_MAX_GROUP) { 6753 LOG_CLI(("GCW index =%d is out of range.\n",index)); 6754 return SOC_E_PARAM; 6755 } 6756 6757 sal_memset(&config, 0, sizeof(cprif_cpri_tx_gcw_config_t)); 6758 config.Ns = config_info->Ns; 6759 config.Xs = config_info->Xs; 6760 config.Y = config_info->Y; 6761 _cprimod_to_cprif_gcw_mask(config_info->mask, &config.mask); 6762 6763 if (config_info->bfn0_filter_enable) { 6764 config.bfn0_filter_enable = 1; 6765 } else { 6766 config.bfn0_filter_enable = 0; 6767 } 6768 6769 if (config_info->bfn1_filter_enable) { 6770 config.bfn1_filter_enable = 1; 6771 } else { 6772 config.bfn1_filter_enable = 0; 6773 } 6774 6775 if (config_info->repeat_enable){ 6776 config.repeat_mode = CPRIF_CW_REPEAT_MODE_CONTINUOUS; 6777 } else { 6778 config.repeat_mode = CPRIF_CW_REPEAT_MODE_ONCE; 6779 } 6780 config.hfn_index = config_info->hyper_frame_index; 6781 config.hfn_modulo = config_info->hyper_frame_modulo; 6782 6783 _SOC_IF_ERR_EXIT 6784 (cprif_drv_tx_gcw_config_set(unit, port, 6785 index, &config)); 6786 exit: 6787 SOC_FUNC_RETURN; 6788 } 6789 6790 int cprif_cpri_port_tx_gcw_config_get(int unit, int port, uint32 index, cprimod_cpri_tx_gcw_config_t* config_info) 6791 { 6792 cprif_cpri_tx_gcw_config_t config; 6793 SOC_INIT_FUNC_DEFS; 6794 6795 if (index >= CPRIF_GCW_MAX_GROUP) { 6796 LOG_CLI(("GCW index =%d is out of range.\n",index)); 6797 return SOC_E_PARAM; 6798 } 6799 6800 sal_memset(&config, 0, sizeof(cprif_cpri_tx_gcw_config_t)); 6801 _SOC_IF_ERR_EXIT 6802 (cprif_drv_tx_gcw_config_get(unit, port, 6803 index, &config)); 6804 config_info->Ns = config.Ns; 6805 config_info->Xs = config.Xs; 6806 config_info->Y = config.Y; 6807 _cprif_to_cprimod_gcw_mask(config.mask, &config_info->mask); 6808 6809 if (config.repeat_mode == CPRIF_CW_REPEAT_MODE_CONTINUOUS){ 6810 config_info->repeat_enable = 1; 6811 } else { 6812 config_info->repeat_enable = 0; 6813 } 6814 6815 if (config.bfn0_filter_enable) { 6816 config_info->bfn0_filter_enable = 1; 6817 } else { 6818 config_info->bfn0_filter_enable = 0; 6819 } 6820 6821 if (config.bfn1_filter_enable) { 6822 config_info->bfn1_filter_enable = 1; 6823 } else { 6824 config_info->bfn1_filter_enable = 0; 6825 } 6826 6827 config_info->hyper_frame_index = config.hfn_index; 6828 config_info->hyper_frame_modulo = config.hfn_modulo; 6829 6830 exit: 6831 SOC_FUNC_RETURN; 6832 } 6833 6834 int cprif_cpri_port_tx_gcw_filter_set(int unit, int port, uint32 bfn0_value, uint32 bfn0_mask, uint32 bfn1_value, uint32 bfn1_mask) 6835 { 6836 SOC_INIT_FUNC_DEFS; 6837 6838 _SOC_IF_ERR_EXIT 6839 (cprif_drv_tx_gcw_filter_set(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 6840 exit: 6841 SOC_FUNC_RETURN; 6842 6843 } 6844 6845 int cprif_cpri_port_tx_gcw_filter_get(int unit, int port, uint32* bfn0_value, uint32* bfn0_mask, uint32* bfn1_value, uint32* bfn1_mask) 6846 { 6847 SOC_INIT_FUNC_DEFS; 6848 6849 _SOC_IF_ERR_EXIT 6850 (cprif_drv_tx_gcw_filter_get(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 6851 6852 6853 exit: 6854 SOC_FUNC_RETURN; 6855 6856 } 6857 6858 int cprif_cpri_port_tx_control_word_set(int unit, int port, const cprimod_cpri_cw_l1_config_info_t* control_info) 6859 { 6860 cprif_drv_tx_control_word_t control; 6861 SOC_INIT_FUNC_DEFS; 6862 6863 sal_memset(&control, 0, sizeof(cprif_drv_tx_control_word_t)); 6864 control.enet_ptr = control_info->enet_ptr; 6865 control.l1_fun = control_info->l1_fun; 6866 control.hdlc_rate = control_info->hdlc_rate; 6867 control.protocol_ver= control_info->protocol_ver; 6868 _SOC_IF_ERR_EXIT 6869 (cprif_drv_tx_control_word_set(unit, port, &control)); 6870 exit: 6871 SOC_FUNC_RETURN; 6872 } 6873 6874 int cprif_rsvd4_rx_control_message_config_set(int unit, int port, uint32 queue_num, uint32 default_tag, uint32 no_match_tag) 6875 { 6876 SOC_INIT_FUNC_DEFS; 6877 6878 _SOC_IF_ERR_EXIT 6879 (cprif_drv_rsvd4_rx_control_message_config_set( unit, port, 6880 queue_num, 6881 default_tag, 6882 no_match_tag)); 6883 exit: 6884 SOC_FUNC_RETURN; 6885 } 6886 6887 void _cprimod_to_cprif_proc_type( cprimod_control_msg_proc_type_t cprimod_mode, uint32* cprif_mode) 6888 { 6889 switch (cprimod_mode) { 6890 case CPRIMOD_CONTROL_MSG_PROC_TYPE_FE: 6891 *cprif_mode = CPRIF_CTRL_FLOW_PROC_TYPE_ETH; 6892 break; 6893 case CPRIMOD_CONTROL_MSG_PROC_TYPE_FCB: 6894 *cprif_mode = CPRIF_CTRL_FLOW_PROC_TYPE_FCB; 6895 break; 6896 case CPRIMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD: 6897 *cprif_mode = CPRIF_CTRL_FLOW_PROC_TYPE_PAYLOAD; 6898 break; 6899 case CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE: 6900 *cprif_mode = CPRIF_CTRL_FLOW_PROC_TYPE_FULL_MSG; 6901 break; 6902 case CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG: 6903 *cprif_mode = CPRIF_CTRL_FLOW_PROC_TYPE_FULL_MSG_WITH_TAG; 6904 break; 6905 default: 6906 *cprif_mode = CPRIF_CTRL_FLOW_PROC_TYPE_ETH; 6907 break; 6908 } 6909 } 6910 6911 void _cprif_to_cprimod_proc_type( uint32 cprif_mode, cprimod_control_msg_proc_type_t* cprimod_mode) 6912 { 6913 switch (cprif_mode) { 6914 case CPRIF_CTRL_FLOW_PROC_TYPE_ETH: 6915 *cprimod_mode = CPRIMOD_CONTROL_MSG_PROC_TYPE_FE; 6916 break; 6917 case CPRIF_CTRL_FLOW_PROC_TYPE_FCB: 6918 *cprimod_mode = CPRIMOD_CONTROL_MSG_PROC_TYPE_FCB; 6919 break; 6920 case CPRIF_CTRL_FLOW_PROC_TYPE_PAYLOAD: 6921 *cprimod_mode = CPRIMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD; 6922 break; 6923 case CPRIF_CTRL_FLOW_PROC_TYPE_FULL_MSG: 6924 *cprimod_mode = CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE; 6925 break; 6926 case CPRIF_CTRL_FLOW_PROC_TYPE_FULL_MSG_WITH_TAG: 6927 *cprimod_mode = CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG; 6928 break; 6929 default: 6930 *cprimod_mode = CPRIMOD_CONTROL_MSG_PROC_TYPE_FE; 6931 break; 6932 } 6933 } 6934 6935 int cprif_rsvd4_rx_control_flow_config_set(int unit, int port, uint32 flow_id, cprimod_control_flow_config_t* config) 6936 { 6937 cprif_rsvd4_rx_ctrl_flow_config_t config_info; 6938 SOC_INIT_FUNC_DEFS; 6939 6940 if (flow_id >= CPRIF_CTRL_FLOW_MAX) { 6941 LOG_CLI(("control flow flow_id =%d is out of range.\n",flow_id)); 6942 return SOC_E_PARAM; 6943 } 6944 6945 sal_memset(&config_info, 0, sizeof(cprif_rsvd4_rx_ctrl_flow_config_t)); 6946 6947 _cprimod_to_cprif_proc_type(config->proc_type, &config_info.proc_type); 6948 config_info.queue_num = config->queue_num; 6949 config_info.sync_profile = config->sync_profile; 6950 config_info.sync_enable = config->sync_enable; 6951 6952 _SOC_IF_ERR_EXIT 6953 (cprif_drv_rsvd4_rx_control_flow_config_set ( unit, port, 6954 flow_id, 6955 &config_info)); 6956 6957 exit: 6958 SOC_FUNC_RETURN; 6959 6960 } 6961 6962 int cprif_rsvd4_rx_control_flow_config_get(int unit, int port, uint32 flow_id, cprimod_control_flow_config_t* config) 6963 { 6964 cprif_rsvd4_rx_ctrl_flow_config_t config_info; 6965 SOC_INIT_FUNC_DEFS; 6966 6967 if (flow_id >= CPRIF_CTRL_FLOW_MAX) { 6968 LOG_CLI(("control flow flow_id =%d is out of range.\n",flow_id)); 6969 return SOC_E_PARAM; 6970 } 6971 6972 sal_memset(&config_info, 0, sizeof(cprif_rsvd4_rx_ctrl_flow_config_t)); 6973 6974 _SOC_IF_ERR_EXIT 6975 (cprif_drv_rsvd4_rx_control_flow_config_get(unit, port, 6976 flow_id, 6977 &config_info)); 6978 _cprif_to_cprimod_proc_type(config_info.proc_type, &config->proc_type); 6979 config->queue_num = config_info.queue_num; 6980 config->sync_profile = config_info.sync_profile; 6981 config->sync_enable = config_info.sync_enable; 6982 exit: 6983 SOC_FUNC_RETURN; 6984 } 6985 6986 int cprif_rsvd4_rx_sync_profile_entry_set(int unit, int port, uint32 profile_id, const cprimod_sync_profile_entry_t* entry) 6987 { 6988 cprif_rsvd4_rx_sync_profile_entry_t int_entry; 6989 SOC_INIT_FUNC_DEFS; 6990 6991 if (profile_id >= CPRIF_SYNC_PROFILE_MAX) { 6992 LOG_CLI(("sync profile_id =%d is out of range.\n",profile_id)); 6993 return SOC_E_PARAM; 6994 } 6995 sal_memset(&int_entry, 0, sizeof(cprif_rsvd4_rx_sync_profile_entry_t)); 6996 6997 int_entry.bfn_offset = entry->master_frame_offset; 6998 int_entry.rfrm_offset = entry->message_offset; 6999 7000 if (entry->count_cycle == CPRIMOD_SYNC_COUNT_CYCLE_UP_TO_6MF){ 7001 int_entry.count_cycle = CPRIF_SYNC_PROFILE_UP_TO_6MF; 7002 } else { 7003 int_entry.count_cycle = CPRIF_SYNC_PROFILE_EVERY_MF; 7004 } 7005 7006 _SOC_IF_ERR_EXIT 7007 (cprif_drv_rx_sync_profile_entry_set(unit, port, profile_id, &int_entry)); 7008 exit: 7009 SOC_FUNC_RETURN; 7010 } 7011 7012 int cprif_rsvd4_rx_sync_profile_entry_get(int unit, int port, uint32 profile_id, cprimod_sync_profile_entry_t* entry) 7013 { 7014 cprif_rsvd4_rx_sync_profile_entry_t int_entry; 7015 SOC_INIT_FUNC_DEFS; 7016 7017 if (profile_id >= CPRIF_SYNC_PROFILE_MAX) { 7018 LOG_CLI(("sync profile_id =%d is out of range.\n",profile_id)); 7019 return SOC_E_PARAM; 7020 } 7021 7022 sal_memset(&int_entry, 0, sizeof(cprif_rsvd4_rx_sync_profile_entry_t)); 7023 7024 _SOC_IF_ERR_EXIT 7025 (cprif_drv_rx_sync_profile_entry_get(unit, port, profile_id, &int_entry)); 7026 entry->master_frame_offset = int_entry.bfn_offset; 7027 entry->message_offset = int_entry.rfrm_offset; 7028 7029 if ( int_entry.count_cycle == CPRIF_SYNC_PROFILE_UP_TO_6MF){ 7030 entry->count_cycle = CPRIMOD_SYNC_COUNT_CYCLE_UP_TO_6MF; 7031 } else { 7032 entry->count_cycle = CPRIMOD_SYNC_COUNT_CYCLE_EVERY_MF; 7033 } 7034 7035 exit: 7036 SOC_FUNC_RETURN; 7037 7038 } 7039 int cprif_rx_tag_config_set(int unit, int port, uint32 default_tag, uint32 no_match_tag) 7040 { 7041 SOC_INIT_FUNC_DEFS; 7042 7043 _SOC_IF_ERR_EXIT 7044 (cprif_drv_rx_tag_config_set( unit, port, default_tag, no_match_tag)); 7045 7046 exit: 7047 SOC_FUNC_RETURN; 7048 7049 } 7050 7051 int cprif_rx_tag_gen_entry_add(int unit, int port, cprimod_tag_gen_entry_t* entry) 7052 { 7053 cprif_rx_tag_gen_entry_t table_entry; 7054 int index; 7055 7056 SOC_INIT_FUNC_DEFS; 7057 7058 for(index=0; index < CPRIF_TAG_GEN_MAX_ENTRY; index++) { 7059 _SOC_IF_ERR_EXIT 7060 (cprif_drv_rx_tag_gen_entry_get(unit, port, index, &table_entry)); 7061 7062 if (table_entry.valid == 0) { 7063 /* found an avaialble location */ 7064 table_entry.valid = 1; 7065 table_entry.mask = entry->mask; 7066 table_entry.header = entry->header; 7067 table_entry.tag_id = entry->tag_id; 7068 table_entry.rtwp_word_count = entry->word_count; 7069 7070 return (cprif_drv_rx_tag_gen_entry_set(unit, port, index, &table_entry)); 7071 } 7072 } 7073 LOG_CLI(("No Space to add Tag Gen Entry .\n")); 7074 return SOC_E_PARAM; 7075 exit: 7076 SOC_FUNC_RETURN; 7077 } 7078 7079 int cprif_rx_tag_gen_entry_delete(int unit, int port, cprimod_tag_gen_entry_t* entry) 7080 { 7081 cprif_rx_tag_gen_entry_t table_entry; 7082 int index; 7083 7084 SOC_INIT_FUNC_DEFS; 7085 7086 for(index=0; index < CPRIF_TAG_GEN_MAX_ENTRY; index++) { 7087 _SOC_IF_ERR_EXIT 7088 (cprif_drv_rx_tag_gen_entry_get(unit, port, index, &table_entry)); 7089 7090 if (table_entry.valid == 1) { 7091 /* found a valid entry */ 7092 if ((table_entry.mask == entry->mask) && 7093 (table_entry.header == entry->header) && 7094 (table_entry.tag_id == entry->tag_id)){ 7095 /* Matching valid entry found, delete the entry by invalidating the entry.*/ 7096 table_entry.valid = 0; 7097 return (cprif_drv_rx_tag_gen_entry_set(unit, port, index, &table_entry)); 7098 } 7099 } 7100 } 7101 LOG_CLI(("No Matching Entry Found .\n")); 7102 return SOC_E_PARAM; 7103 exit: 7104 SOC_FUNC_RETURN; 7105 7106 } 7107 7108 int cprif_rx_control_flow_tag_option_set(int unit, int port, uint32 flow_id, cprimod_cpri_tag_option_t tag_option) 7109 { 7110 SOC_INIT_FUNC_DEFS; 7111 7112 _SOC_IF_ERR_EXIT 7113 (cprif_drv_rx_control_flow_tag_option_set(unit, port, 7114 flow_id, 7115 (tag_option == CPRIMOD_CPRI_TAG_LOOKUP)?1:0)); 7116 exit: 7117 SOC_FUNC_RETURN; 7118 7119 } 7120 7121 int cprif_rsvd4_tx_control_flow_group_member_add(int unit, int port, uint32 group_id, 7122 uint32 priority, uint32 queue_num, 7123 cprimod_control_msg_proc_type_t proc_type) 7124 { 7125 cprif_control_group_entry_t entry; 7126 SOC_INIT_FUNC_DEFS; 7127 7128 if (group_id >= CPRIF_TX_CONTROL_MAX_GROUP) { 7129 LOG_CLI(("RSVD4 Tx Control Group group_id =%d is out of range.\n",group_id)); 7130 return SOC_E_PARAM; 7131 } 7132 7133 if (priority >= CPRIF_TX_CONTROL_MAX_MEMBER) { 7134 LOG_CLI(("RSVD4 Tx Control Priority =%d is out of range.\n",priority)); 7135 return SOC_E_PARAM; 7136 } 7137 7138 _SOC_IF_ERR_EXIT 7139 (cprif_drv_brcm_rsvd4_tx_control_group_entry_get(unit, port,group_id, &entry)); 7140 7141 entry.queue_num[priority] = queue_num; 7142 _cprimod_to_cprif_proc_type(proc_type, &entry.proc_type[priority]); 7143 entry.valid_mask |= (0x1 << priority); 7144 7145 _SOC_IF_ERR_EXIT 7146 (cprif_drv_brcm_rsvd4_tx_control_group_entry_set(unit, port,group_id, &entry)); 7147 7148 exit: 7149 SOC_FUNC_RETURN; 7150 7151 } 7152 7153 int cprif_rsvd4_tx_control_flow_group_member_delete(int unit, int port, uint32 group_id, uint32 priority) 7154 { 7155 cprif_control_group_entry_t entry; 7156 SOC_INIT_FUNC_DEFS; 7157 7158 if (group_id >= CPRIF_TX_CONTROL_MAX_GROUP) { 7159 LOG_CLI(("RSVD4 Tx Control Group group_id =%d is out of range.\n",group_id)); 7160 return SOC_E_PARAM; 7161 } 7162 7163 if (priority >= CPRIF_TX_CONTROL_MAX_MEMBER) { 7164 LOG_CLI(("RSVD4 Tx Control Priority =%d is out of range.\n",priority)); 7165 return SOC_E_PARAM; 7166 } 7167 7168 _SOC_IF_ERR_EXIT 7169 (cprif_drv_brcm_rsvd4_tx_control_group_entry_get(unit, port,group_id, &entry)); 7170 7171 /* masked off the valid bit. */ 7172 entry.valid_mask &= ~(0x1 << priority); 7173 7174 _SOC_IF_ERR_EXIT 7175 (cprif_drv_brcm_rsvd4_tx_control_group_entry_set(unit, port,group_id, &entry)); 7176 7177 exit: 7178 SOC_FUNC_RETURN; 7179 7180 } 7181 7182 int cprif_rsvd4_tx_eth_message_config_set(int unit, int port, uint32 msg_node, uint32 msg_subnode, uint32 msg_type, uint32 msg_padding) 7183 { 7184 SOC_INIT_FUNC_DEFS; 7185 7186 _SOC_IF_ERR_EXIT 7187 (cprif_drv_tx_control_eth_msg_config_set( unit, port, 7188 msg_node, msg_subnode, 7189 msg_type, msg_padding)); 7190 exit: 7191 SOC_FUNC_RETURN; 7192 7193 } 7194 7195 int cprif_rsvd4_tx_single_raw_message_config_set(int unit, int port, uint32 msg_id, uint32 msg_type) 7196 { 7197 SOC_INIT_FUNC_DEFS; 7198 7199 _SOC_IF_ERR_EXIT 7200 (cprif_drv_tx_control_single_msg_config_set(unit, port, msg_id, msg_type)); 7201 7202 exit: 7203 SOC_FUNC_RETURN; 7204 7205 } 7206 7207 7208 int cprif_rsvd4_tx_single_tunnel_message_config_set(int unit, int port, cprimod_cpri_crc_option_t crc_option) 7209 { 7210 SOC_INIT_FUNC_DEFS; 7211 7212 _SOC_IF_ERR_EXIT 7213 (cprif_drv_tx_control_single_tunnel_msg_config_set(unit, port, (crc_option == CPRIMOD_CPRI_CRC_REGENERATE)?1:0)); 7214 exit: 7215 SOC_FUNC_RETURN; 7216 7217 } 7218 7219 int cprif_rsvd4_tx_control_flow_config_set(int unit, int port, uint32 flow_id, const cprimod_rsvd4_tx_config_info_t* config_info) 7220 { 7221 uint32 int_proc_type=0; 7222 cprif_cpri_tx_fast_eth_config_t tx_config; 7223 SOC_INIT_FUNC_DEFS; 7224 7225 if (flow_id >= CPRIF_CTRL_FLOW_MAX) { 7226 LOG_CLI(("control flow flow_id =%d is out of range.\n",flow_id)); 7227 return SOC_E_PARAM; 7228 } 7229 7230 if(config_info->proc_type == CPRIMOD_CONTROL_MSG_PROC_TYPE_FE){ 7231 sal_memset(&tx_config, 0, sizeof(cprif_cpri_tx_fast_eth_config_t)); 7232 tx_config.crc_mode = config_info->crc_mode; 7233 tx_config.min_ipg = 4; 7234 tx_config.queue_num = 0x7f;/*defult value of reg*/ 7235 tx_config.cw_sel = 0; 7236 tx_config.cw_size = 0; 7237 tx_config.sub_channel_size = 0; 7238 tx_config.sub_channel_start = 0x10;/*defult value of reg*/ 7239 7240 _SOC_IF_ERR_EXIT 7241 (cprif_drv_cpri_port_tx_cw_fast_eth_config_set(unit, port, &tx_config)); 7242 } 7243 7244 _cprimod_to_cprif_proc_type(config_info->proc_type, &int_proc_type); 7245 7246 _SOC_IF_ERR_EXIT 7247 (cprif_drv_brcm_rsvd4_tx_control_flow_config_set( unit, port, flow_id, config_info->queue_num, int_proc_type)); 7248 exit: 7249 SOC_FUNC_RETURN; 7250 7251 } 7252 7253 int cprif_rsvd4_tx_control_flow_config_get(int unit, int port, uint32 flow_id, cprimod_rsvd4_tx_config_info_t config_info) 7254 { 7255 uint32 int_proc_type; 7256 uint32 queue_num; 7257 SOC_INIT_FUNC_DEFS; 7258 7259 if (flow_id >= CPRIF_CTRL_FLOW_MAX) { 7260 LOG_CLI(("control flow flow_id =%d is out of range.\n",flow_id)); 7261 return SOC_E_PARAM; 7262 } 7263 _SOC_IF_ERR_EXIT 7264 (cprif_drv_brcm_rsvd4_tx_control_flow_config_get( unit, port, flow_id, &queue_num, &int_proc_type)); 7265 7266 config_info.queue_num = queue_num; 7267 7268 _cprif_to_cprimod_proc_type(int_proc_type, &config_info.proc_type); 7269 7270 exit: 7271 SOC_FUNC_RETURN; 7272 } 7273 7274 int cprif_rsvd4_tx_control_flow_header_index_set(int unit, int port, uint32 roe_flow_id, uint32 index) 7275 { 7276 SOC_INIT_FUNC_DEFS; 7277 7278 if (roe_flow_id >= CPRIF_CTRL_MAX_ROE_FLOW_ID) { 7279 LOG_CLI(("control flow roe_flow_id =%d is out of range.\n",roe_flow_id)); 7280 return SOC_E_PARAM; 7281 } 7282 _SOC_IF_ERR_EXIT 7283 (cprif_drv_brcm_rsvd4_control_flow_header_index_set( unit, port, 7284 roe_flow_id, 7285 index)); 7286 exit: 7287 SOC_FUNC_RETURN; 7288 } 7289 7290 int cprif_rsvd4_tx_control_flow_header_index_get(int unit, int port, uint32 roe_flow_id, uint32* index) 7291 { 7292 SOC_INIT_FUNC_DEFS; 7293 7294 if (roe_flow_id >= CPRIF_CTRL_MAX_ROE_FLOW_ID) { 7295 LOG_CLI(("control flow roe_flow_id =%d is out of range.\n",roe_flow_id)); 7296 return SOC_E_PARAM; 7297 } 7298 _SOC_IF_ERR_EXIT 7299 (cprif_drv_brcm_rsvd4_control_flow_header_index_get( unit, port, 7300 roe_flow_id, 7301 index)); 7302 exit: 7303 SOC_FUNC_RETURN; 7304 } 7305 7306 int cprif_rsvd4_tx_control_header_entry_set(int unit, int port, uint32 index, uint32 header_node, uint32 header_subnode, uint32 payload_node) 7307 { 7308 SOC_INIT_FUNC_DEFS; 7309 7310 if (index >= CPRIF_TX_HEADER_CONFIG_TABLE_SIZE) { 7311 LOG_CLI(("header look up index =%d is out of range.\n",index)); 7312 return SOC_E_PARAM; 7313 } 7314 7315 _SOC_IF_ERR_EXIT 7316 (cprif_drv_brcm_rsvd4_control_header_entry_set( unit, port, 7317 index, 7318 header_node, 7319 header_subnode, 7320 payload_node)); 7321 exit: 7322 SOC_FUNC_RETURN; 7323 } 7324 7325 int cprif_rsvd4_tx_control_header_entry_get(int unit, int port, uint32 index, uint32* header_node, uint32* header_subnode, uint32* payload_node) 7326 { 7327 SOC_INIT_FUNC_DEFS; 7328 7329 if (index >= CPRIF_TX_HEADER_CONFIG_TABLE_SIZE) { 7330 LOG_CLI(("header look up index =%d is out of range.\n",index)); 7331 return SOC_E_PARAM; 7332 } 7333 _SOC_IF_ERR_EXIT 7334 (cprif_drv_brcm_rsvd4_control_header_entry_get( unit, port, 7335 index, 7336 header_node, 7337 header_subnode, 7338 payload_node)); 7339 exit: 7340 SOC_FUNC_RETURN; 7341 } 7342 7343 int cprif_rsvd4_fast_eth_config_set(int unit, int port, const cprimod_cpri_fast_eth_config_t* config_info) 7344 { 7345 cprif_cpri_rx_fast_eth_config_t rx_config; 7346 SOC_INIT_FUNC_DEFS; 7347 7348 rx_config.queue_num = config_info->queue_num ; /* Not used for for RSVD4 */ 7349 rx_config.ignore_fcs_err = config_info->no_fcs_err_check ; 7350 rx_config.min_packet_drop = config_info->min_packet_drop ; 7351 rx_config.max_packet_drop = config_info->max_packet_drop ; 7352 rx_config.min_packet_size = config_info->min_packet_size ; 7353 rx_config.max_packet_size = config_info->max_packet_size ; 7354 rx_config.strip_crc = config_info->strip_crc; 7355 7356 _SOC_IF_ERR_EXIT 7357 (cprif_drv_cpri_port_rx_cw_fast_eth_config_set(unit, port, &rx_config)); 7358 exit: 7359 SOC_FUNC_RETURN; 7360 } 7361 7362 int cprif_cpri_or_enet_port_set(int unit, int port, int val) 7363 { 7364 SOC_INIT_FUNC_DEFS; 7365 7366 _SOC_IF_ERR_EXIT (cprif_drv_cpri_or_enet_port_set(unit, port, val)); 7367 7368 exit: 7369 SOC_FUNC_RETURN; 7370 } 7371 7372 int cprif_cpri_or_enet_port_get(int unit, int port, int* val) 7373 { 7374 SOC_INIT_FUNC_DEFS; 7375 7376 _SOC_IF_ERR_EXIT (cprif_drv_cpri_or_enet_port_get(unit, port, val)); 7377 7378 exit: 7379 SOC_FUNC_RETURN; 7380 } 7381 7382 int cprif_cpri_port_rx_enable_set(int unit, int port, int val) 7383 { 7384 SOC_INIT_FUNC_DEFS; 7385 7386 /* make val ^1 to convert enable to disable */ 7387 _SOC_IF_ERR_EXIT (cprif_drv_rx_disable_set(unit, port, (val&1)^1)); 7388 7389 exit: 7390 SOC_FUNC_RETURN; 7391 7392 } 7393 7394 int cprif_cpri_port_rx_enable_get(int unit, int port, int* val) 7395 { 7396 int tmpval; 7397 SOC_INIT_FUNC_DEFS; 7398 7399 _SOC_IF_ERR_EXIT (cprif_drv_rx_disable_get(unit, port, &tmpval)); 7400 /* make val ^1 to convert disable to enable */ 7401 *val = (tmpval&1)^1; 7402 7403 exit: 7404 SOC_FUNC_RETURN; 7405 7406 } 7407 7408 int cprif_cpri_port_tx_enable_set(int unit, int port, int val) 7409 { 7410 SOC_INIT_FUNC_DEFS; 7411 7412 /* make val ^1 to convert enable to disable */ 7413 _SOC_IF_ERR_EXIT(cprif_drv_tx_frame_optional_config_set(unit, port, 7414 cprimodTxConfigtxpmdDisableOverrideVal, (val&1)^1)); 7415 _SOC_IF_ERR_EXIT(cprif_drv_tx_frame_optional_config_set(unit, port, 7416 cprimodTxConfigtxpmdDisableOverrideEn, (val&1)^1)); 7417 7418 exit: 7419 SOC_FUNC_RETURN; 7420 7421 } 7422 7423 int cprif_cpri_port_tx_enable_get(int unit, int port, int* val) 7424 { 7425 uint32 tmpval0, tmpval1; 7426 SOC_INIT_FUNC_DEFS; 7427 7428 _SOC_IF_ERR_EXIT(cprif_drv_tx_frame_optional_config_get(unit, port, 7429 cprimodTxConfigtxpmdDisableOverrideVal, &tmpval0)); 7430 _SOC_IF_ERR_EXIT(cprif_drv_tx_frame_optional_config_get(unit, port, 7431 cprimodTxConfigtxpmdDisableOverrideEn, &tmpval1)); 7432 /* make val ^1 to convert disable to enable */ 7433 *val = (tmpval0 & tmpval1 & 1) ^ 1; 7434 7435 exit: 7436 SOC_FUNC_RETURN; 7437 7438 } 7439 7440 STATIC 7441 int _cprif_cpri_port_intr_hierarchy_enable(int unit, int port, int enable) 7442 { 7443 SOC_INIT_FUNC_DEFS; 7444 7445 /* 7446 * Enable/Disable the RX/TX interrupts in the 7447 * interrupts hierarchy for the CPM. 7448 */ 7449 7450 /* Enable Level 1 Port RX/TX interrupts */ 7451 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_interrupt_enable_set(unit, port, 7452 (CPRIF_RX_INTR | CPRIF_TX_INTR), 7453 enable)); 7454 7455 /* 7456 * Enable All Level 2 Port RX interrupts. 7457 * Rx operational error interrupts 7458 * Rx functional error interrupts 7459 * Not enabling the Rx ecc error interrupts. 7460 */ 7461 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_rx_interrupts_enable_set(unit, port, 7462 (CPRIF_RX_OP_ERR_INTR | 7463 CPRIF_RX_FUNC_ERR_INTR), 7464 enable)); 7465 7466 /* 7467 * Enable All Level 3 Port RX interrupts. 7468 * All Rx operational error interrupts 7469 * All Rx functional error interrupts 7470 * Not enabling the Rx ecc error interrupts. 7471 */ 7472 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_rx_op_err_interrupts_enable_set(unit, 7473 port, CPRI_INTR_RX_OP_ERR_INTR_ALL, enable)); 7474 7475 7476 _SOC_IF_ERR_EXIT( 7477 cprif_drv_cpri_port_rx_func_interrupts_enable_set(unit, port, 7478 CPRI_INTR_RX_FUNC_ERR_INTR_ALL, 7479 enable)); 7480 7481 /* 7482 * Enable All Level 2 Port TX interrupts. 7483 * Tx operational error interrupts 7484 * Tx functional error interrupts 7485 * Not enabling the Rx ecc error interrupts. 7486 */ 7487 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_tx_interrupts_enable_set(unit, port, 7488 (CPRIF_TX_OP_ERR_INTR | 7489 CPRIF_TX_FUNC_ERR_INTR), 7490 enable)); 7491 7492 /* 7493 * Enable All Level 3 Port TX interrupts. 7494 * All Tx operational error interrupts 7495 * All Tx functional error interrupts 7496 * Not enabling the Rx ecc error interrupts. 7497 */ 7498 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_tx_op_err_interrupts_enable_set(unit, 7499 port, CPRI_INTR_TX_OP_ERR_INTR_ALL, enable)); 7500 7501 _SOC_IF_ERR_EXIT( 7502 cprif_drv_cpri_port_tx_func_interrupts_enable_set(unit, port, 7503 CPRI_INTR_TX_FUNC_ERR_INTR_ALL, 7504 enable)); 7505 exit: 7506 SOC_FUNC_RETURN; 7507 } 7508 7509 int cprif_cpri_port_interrupt_link_status_get(int unit, int port, 7510 int *is_link_intr_status) 7511 { 7512 int link_up = 0, link_down = 0; 7513 SOC_INIT_FUNC_DEFS; 7514 7515 /* Check if link is up */ 7516 _SOC_IF_ERR_EXIT( 7517 cprif_drv_rx_pcs_link_up_intr_status_clr_get(unit, port, &link_up)); 7518 7519 /* Check if link is down */ 7520 _SOC_IF_ERR_EXIT( 7521 cprif_drv_rx_pcs_link_down_intr_status_clr_get(unit, port, &link_down)); 7522 7523 /* Capture if there is any change in the link status */ 7524 *is_link_intr_status = link_up | link_down; 7525 7526 exit: 7527 SOC_FUNC_RETURN; 7528 } 7529 7530 int cprif_cpri_port_rx_1588_fifo_intr_enable_get(int unit, int port, 7531 int *status) 7532 { 7533 SOC_INIT_FUNC_DEFS; 7534 7535 _SOC_IF_ERR_EXIT(cprif_drv_rx_1588_fifo_intr_enable_get(unit, port, 7536 status)); 7537 7538 exit: 7539 SOC_FUNC_RETURN; 7540 } 7541 7542 int cprif_cpri_port_rx_1588_sw_intr_enable_get(int unit, int port, 7543 int *status) 7544 { 7545 SOC_INIT_FUNC_DEFS; 7546 7547 _SOC_IF_ERR_EXIT(cprif_drv_rx_1588_sw_intr_enable_get(unit, port, 7548 status)); 7549 7550 exit: 7551 SOC_FUNC_RETURN; 7552 } 7553 7554 7555 int cprif_cpri_port_interrupt_enable_set(int unit, int port, 7556 cprimod_cpri_port_intr_type_t intr_type, 7557 int data, int enable) 7558 { 7559 SOC_INIT_FUNC_DEFS; 7560 7561 switch(intr_type) { 7562 case _shrCpriIntrRx1588TsFifo: 7563 case _shrCpriIntrRx1588CapturedTs: 7564 case _shrCpriIntrRxPcs64B66BBlkLckLl: 7565 case _shrCpriIntrRxPcs64B66BBlkLckLh: 7566 case _shrCpriIntrRxPcs64B66BHiBerLl: 7567 case _shrCpriIntrRxPcs64B66BHiBerLh: 7568 case _shrCpriIntrRxPcsLosLl: 7569 case _shrCpriIntrRxPcsLosLh: 7570 case _shrCpriIntrRxPcsLinkStatusLl: 7571 case _shrCpriIntrRxPcsLinkStatusLh: 7572 case _shrCpriIntrRxPcsExtractFifoOvrFlow: 7573 case _shrCpriIntrRxGcw: 7574 case _shrCpriIntrRxEncapDataQOverflow: 7575 case _shrCpriIntrRxEncapCtrlQOverflow: 7576 case _shrCpriIntrRxEncapGsmTsQErr: 7577 case _shrCpriIntrRxEncapWqFiFoOverflow: 7578 case _shrCpriIntrRxEncapRxFrmInFifoOverflow: 7579 case _shrCpriIntrRxEncapIpsmCdcFifoErr: 7580 case _shrCpriIntrRxFrmRsvd4Ts: 7581 case _shrCpriIntrRxFrmRsvd4SingleTsErr: 7582 case _shrCpriIntrRxFrmL1SigChange: 7583 case _shrCpriIntrRxPcsFecCsCwBad: 7584 case _shrCpriIntrTxDecapDataQOvflErr: 7585 case _shrCpriIntrTxDecapDataQUdflErr: 7586 case _shrCpriIntrTxDecapDataQBufSizeErr: 7587 case _shrCpriIntrTxDecapAgModePktMiss: 7588 case _shrCpriIntrTx1588CapturedTs: 7589 case _shrCpriIntrTx1588TsFifo: 7590 case _shrCpriIntrTxFrmCwaCtrlPktFlowIdErr: 7591 case _shrCpriIntrTxFrmBfaHfStartMisalign: 7592 case _shrCpriIntrTxFrmDrMultiEthPsizeUndersize: 7593 case _shrCpriIntrTxFrmDrAckMisalign: 7594 case _shrCpriIntrTxFrmCwaMultipleValids: 7595 case _shrCpriIntrTxFrmCwaSdvmProcOverflow: 7596 case _shrCpriIntrTxFrmArbPsizeZero: 7597 case _shrCpriIntrTxFrmArbCpriAckMismatch: 7598 case _shrCpriIntrTxFrmArbRsvd4ReqConflict: 7599 case _shrCpriIntrTxFrmArbRsvd4AckMisalign: 7600 case _shrCpriIntrTxFrmCwaHdlcBufferOverflow: 7601 case _shrCpriIntrTxFrmCwaFastEthBufferOverflow: 7602 case _shrCpriIntrTxFrmCwaVsdRawBufferOverflow: 7603 case _shrCpriIntrTxFrmCwaSdvmBufferOverflow: 7604 case _shrCpriIntrTxFrmMultiEthBufferOverflow: 7605 case _shrCpriIntrTxPcsGboxOverflow: 7606 case _shrCpriIntrTxPcsGboxUnderflow: 7607 case _shrCpriIntrTxPcsFifoOverflow: 7608 case _shrCpriIntrTxPcsFifoUnderflow: 7609 _SOC_IF_ERR_EXIT( 7610 cprif_drv_cpri_port_interrupt_type_enable_set(unit, 7611 port, intr_type, data, enable)); 7612 break; 7613 case _shrCpriIntrCount: 7614 default: 7615 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Unknow interrupt type.")); 7616 break; 7617 } 7618 7619 exit: 7620 SOC_FUNC_RETURN; 7621 } 7622 7623 STATIC 7624 int _cprif_cpri_1588_timestamp_interrupt_process ( int unit, int port, 7625 cprimod_direction_t dir, 7626 cprimod_1588_ts_type_t ts_type ) 7627 { 7628 7629 int enable = 0; 7630 int max_buf = 0; 7631 cprimod_cpri_intr_info_t data; 7632 uint64 timestamps[CPRIMOD_INTR_DATA_NUM_OF_DATA64]; 7633 uint8 num_timestamps=0; 7634 _shr_cpri_interrupt_type_t intr_type = _shrCpriIntrCount; 7635 int index; 7636 SOC_INIT_FUNC_DEFS; 7637 7638 if (ts_type == CPRIMOD_1588_TS_TYPE_SW_CAP) { 7639 if (dir == CPRIMOD_DIR_RX) { 7640 _SOC_IF_ERR_EXIT 7641 (cprif_drv_rx_1588_sw_intr_enable_get(unit, port, &enable)); 7642 intr_type = _shrCpriIntrRx1588CapturedTs; 7643 } else { 7644 _SOC_IF_ERR_EXIT 7645 (cprif_drv_tx_1588_sw_intr_enable_get(unit, port, &enable)); 7646 intr_type = _shrCpriIntrTx1588CapturedTs; 7647 } 7648 max_buf = 1; 7649 } else if (ts_type == CPRIMOD_1588_TS_TYPE_FIFO) { 7650 if (dir == CPRIMOD_DIR_RX) { 7651 _SOC_IF_ERR_EXIT 7652 (cprif_drv_rx_1588_fifo_intr_enable_get(unit, port, &enable)); 7653 intr_type = _shrCpriIntrRx1588TsFifo; 7654 } else { 7655 _SOC_IF_ERR_EXIT 7656 (cprif_drv_tx_1588_fifo_intr_enable_get(unit, port, &enable)); 7657 intr_type = _shrCpriIntrTx1588TsFifo; 7658 } 7659 max_buf = CPRIMOD_INTR_DATA_NUM_OF_DATA64; 7660 } 7661 7662 if (enable) { 7663 _SOC_IF_ERR_EXIT 7664 (cprif_drv_1588_captured_timestamp_get(unit, port, 7665 dir, 7666 ts_type, 7667 max_buf, 7668 &num_timestamps, 7669 timestamps)); 7670 if (num_timestamps > 0) { 7671 data.cpri_intr_type = intr_type; 7672 data.data = num_timestamps; 7673 for (index=0; index < num_timestamps ; index++) { 7674 COMPILER_64_COPY(data.data64[index], timestamps[index]); 7675 } 7676 if (cpri_intr_cbs[unit][intr_type].cb_func != NULL) { 7677 cpri_intr_cbs[unit][intr_type].cb_func(unit, port, &data, cpri_intr_cbs[unit][intr_type].cb_data); 7678 } 7679 } 7680 } 7681 7682 exit: 7683 SOC_FUNC_RETURN; 7684 } 7685 7686 STATIC 7687 int _cprif_cpri_port_interrupt_type_process(int unit, int port, 7688 cprimod_cpri_port_intr_type_t intr_type) 7689 { 7690 int index; 7691 int intr_enable = 0; 7692 int intr_status = 0; 7693 int num_subid = 0; 7694 cprimod_cpri_intr_info_t data; 7695 SOC_INIT_FUNC_DEFS; 7696 7697 _SOC_IF_ERR_EXIT 7698 (cprif_drv_cpri_port_interrupt_type_num_subid_get(unit, port, intr_type, &num_subid)); 7699 7700 for (index=0; index <= num_subid; index++) { 7701 _SOC_IF_ERR_EXIT 7702 (cprif_drv_cpri_port_interrupt_type_enable_get(unit, port, 7703 intr_type, 7704 index, 7705 &intr_enable)); 7706 if (intr_enable) { 7707 _SOC_IF_ERR_EXIT 7708 (cprif_drv_cpri_port_interrupt_type_status_get(unit, port, 7709 intr_type, 7710 index, 7711 &intr_status)); 7712 if (intr_status) { 7713 data.cpri_intr_type = intr_type; 7714 data.axc_id = index; 7715 data.queue_num = index; 7716 if (cpri_intr_cbs[unit][intr_type].cb_func != NULL) { 7717 cpri_intr_cbs[unit][intr_type].cb_func(unit, port, &data, cpri_intr_cbs[unit][intr_type].cb_data); 7718 } 7719 } 7720 } 7721 } 7722 exit: 7723 SOC_FUNC_RETURN; 7724 } 7725 7726 int cprif_cpri_port_interrupt_process(int unit, int port) 7727 { 7728 cprimod_cpri_port_intr_type_t intr_type; 7729 SOC_INIT_FUNC_DEFS; 7730 7731 /* 7732 * 1588 Rx FIFO Timestamp Processing. 7733 */ 7734 _SOC_IF_ERR_EXIT 7735 (_cprif_cpri_1588_timestamp_interrupt_process(unit, port, 7736 CPRIMOD_DIR_RX, 7737 CPRIMOD_1588_TS_TYPE_FIFO)); 7738 /* 7739 * 1588 Tx FIFO Timestamp Processing. 7740 */ 7741 _SOC_IF_ERR_EXIT 7742 (_cprif_cpri_1588_timestamp_interrupt_process(unit, port, 7743 CPRIMOD_DIR_TX, 7744 CPRIMOD_1588_TS_TYPE_FIFO)); 7745 /* 7746 * 1588 Rx Capture Timestamp Processing. 7747 */ 7748 _SOC_IF_ERR_EXIT 7749 (_cprif_cpri_1588_timestamp_interrupt_process(unit, port, 7750 CPRIMOD_DIR_RX, 7751 CPRIMOD_1588_TS_TYPE_SW_CAP)); 7752 /* 7753 * 1588 Tx Capture Timestamp Processing. 7754 */ 7755 _SOC_IF_ERR_EXIT 7756 (_cprif_cpri_1588_timestamp_interrupt_process(unit, port, 7757 CPRIMOD_DIR_TX, 7758 CPRIMOD_1588_TS_TYPE_SW_CAP)); 7759 7760 /* 7761 * Process all other interrupts except above 4 types. 7762 */ 7763 7764 for (intr_type = 0; intr_type < _shrCpriIntrCount; intr_type++) { 7765 7766 if ( (intr_type != _shrCpriIntrRx1588CapturedTs) && 7767 (intr_type != _shrCpriIntrTx1588CapturedTs) && 7768 (intr_type != _shrCpriIntrRx1588TsFifo) && 7769 (intr_type != _shrCpriIntrTx1588TsFifo)) { 7770 7771 _SOC_IF_ERR_EXIT 7772 (_cprif_cpri_port_interrupt_type_process(unit, port, intr_type)); 7773 } 7774 } 7775 7776 exit: 7777 SOC_FUNC_RETURN; 7778 } 7779 7780 int cprif_1588_bit_time_period_set(int unit, int port, cprimod_direction_t direction, cprimod_port_speed_t speed) 7781 { 7782 SOC_INIT_FUNC_DEFS; 7783 _SOC_IF_ERR_EXIT( 7784 cprif_drv_1588_bit_time_period_set(unit, port, direction, speed)); 7785 7786 exit: 7787 SOC_FUNC_RETURN; 7788 7789 } 7790 7791 int cprif_1588_bit_time_period_get(int unit, int port, cprimod_direction_t direction, uint32* bit_time_period) 7792 { 7793 SOC_INIT_FUNC_DEFS; 7794 _SOC_IF_ERR_EXIT( 7795 cprif_drv_1588_bit_time_period_get(unit, port, direction, bit_time_period)); 7796 7797 exit: 7798 SOC_FUNC_RETURN; 7799 7800 } 7801 7802 int cprif_1588_timestamp_capture_config_set(int unit, int port, cprimod_direction_t direction, cprimod_1588_capture_config_t *config) 7803 { 7804 SOC_INIT_FUNC_DEFS; 7805 _SOC_IF_ERR_EXIT( 7806 cprif_drv_1588_timestamp_capture_config_set(unit, port, direction, config)); 7807 exit: 7808 SOC_FUNC_RETURN; 7809 7810 } 7811 int cprif_1588_timestamp_capture_config_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_capture_config_t* config) 7812 { 7813 SOC_INIT_FUNC_DEFS; 7814 _SOC_IF_ERR_EXIT( 7815 cprif_drv_1588_timestamp_capture_config_get(unit, port, direction, config)); 7816 exit: 7817 SOC_FUNC_RETURN; 7818 7819 } 7820 7821 int cprif_1588_captured_timestamp_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_ts_type_t ts_type, uint8 mx_cnt, uint8* count, uint64* captured_time) 7822 { 7823 SOC_INIT_FUNC_DEFS; 7824 _SOC_IF_ERR_EXIT( 7825 cprif_drv_1588_captured_timestamp_get(unit, port, direction, ts_type, mx_cnt, count, captured_time)); 7826 exit: 7827 SOC_FUNC_RETURN; 7828 7829 } 7830 7831 int cprif_1588_timestamp_adjust_set(int unit, int port, cprimod_direction_t direction, cprimod_1588_time_t *adjust_time) 7832 { 7833 SOC_INIT_FUNC_DEFS; 7834 _SOC_IF_ERR_EXIT( 7835 cprif_drv_1588_timestamp_adjust_set(unit, port, direction, adjust_time)); 7836 exit: 7837 SOC_FUNC_RETURN; 7838 7839 } 7840 int cprif_1588_timestamp_adjust_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_time_t* adjust_time) 7841 { 7842 SOC_INIT_FUNC_DEFS; 7843 _SOC_IF_ERR_EXIT( 7844 cprif_drv_1588_timestamp_adjust_get(unit, port, direction, adjust_time)); 7845 exit: 7846 SOC_FUNC_RETURN; 7847 7848 } 7849 7850 int cprif_1588_timestamp_fifo_config_set(int unit, int port, cprimod_direction_t direction, uint16 modulo) 7851 { 7852 SOC_INIT_FUNC_DEFS; 7853 _SOC_IF_ERR_EXIT( 7854 cprif_drv_1588_timestamp_fifo_config_set(unit, port, direction, modulo)); 7855 exit: 7856 SOC_FUNC_RETURN; 7857 7858 } 7859 7860 int cprif_1588_timestamp_fifo_config_get(int unit, int port, cprimod_direction_t direction, uint16* modulo) 7861 { 7862 SOC_INIT_FUNC_DEFS; 7863 7864 _SOC_IF_ERR_EXIT( 7865 cprif_drv_1588_timestamp_fifo_config_get(unit, port, direction, modulo)); 7866 exit: 7867 SOC_FUNC_RETURN; 7868 7869 } 7870 7871 int cprif_1588_timestamp_cmic_config_set(int unit, int port, cprimod_direction_t direction, uint16 modulo) 7872 { 7873 SOC_INIT_FUNC_DEFS; 7874 7875 _SOC_IF_ERR_EXIT( 7876 cprif_drv_1588_timestamp_cmic_config_set(unit, port, direction, modulo)); 7877 7878 exit: 7879 SOC_FUNC_RETURN; 7880 7881 } 7882 7883 int cprif_1588_timestamp_cmic_config_get(int unit, int port, cprimod_direction_t direction, uint16* modulo) 7884 { 7885 SOC_INIT_FUNC_DEFS; 7886 7887 _SOC_IF_ERR_EXIT( 7888 cprif_drv_1588_timestamp_cmic_config_get(unit, port, direction, modulo)); 7889 7890 exit: 7891 SOC_FUNC_RETURN; 7892 7893 } 7894 7895 int cprif_cpri_basic_frame_info_get (int unit, int port, cprimod_direction_t dir, 7896 uint32* frame_len_in_bits, 7897 uint32* control_word_len_in_bits) 7898 { 7899 cprimod_port_speed_t speed; 7900 cprimod_port_interface_type_t interface; 7901 7902 SOC_INIT_FUNC_DEFS; 7903 7904 SOC_IF_ERROR_RETURN(cprif_drv_txcpri_port_type_get(unit, port, 7905 &interface)); 7906 if (interface == cprimodCpri) { 7907 if (dir == CPRIMOD_DIR_TX) { 7908 _SOC_IF_ERR_EXIT(cprif_drv_cpri_txpcs_speed_get(unit, port, &speed)); 7909 } else { 7910 _SOC_IF_ERR_EXIT(cprif_drv_cpri_rxpcs_speed_get(unit, port, &speed)); 7911 } 7912 *frame_len_in_bits = _cprif_from_speed_toframe_len(speed); 7913 *control_word_len_in_bits = _cprif_from_speed_towd_len(speed); 7914 } 7915 7916 exit: 7917 SOC_FUNC_RETURN; 7918 } 7919 7920 int cprif_cpri_agnostic_mode_basic_frame_config_set(int unit, int port, cprimod_direction_t dir, int enable) 7921 { 7922 cprimod_port_speed_t speed; 7923 uint32 cw_len; 7924 uint32 frame_len; 7925 int bits_cnt; 7926 int current_index=1; 7927 uint8 active_table; 7928 uint8 standby_table; 7929 cprif_bfa_bfp_table_entry_t table_entry; 7930 7931 SOC_INIT_FUNC_DEFS; 7932 7933 if (dir == CPRIMOD_DIR_RX) { 7934 7935 /* 7936 * Setup Rx Basic Frame Parser Table. 7937 */ 7938 _SOC_IF_ERR_EXIT(cprif_drv_cpri_rxpcs_speed_get(unit, port, &speed)); 7939 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_clear(unit, port)); 7940 7941 /* 7942 * Adding control word. 7943 */ 7944 cw_len = _cprif_from_speed_towd_len(speed); 7945 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_add(unit, port, CPRIMOD_AXC_ID_CONTROL, 7946 0, cw_len)); 7947 7948 if (enable) { 7949 /* 7950 * Adding data AxCs for the rest of the basic frame. 7951 */ 7952 frame_len = _cprif_from_speed_toframe_len(speed); 7953 _SOC_IF_ERR_EXIT 7954 (cprif_rx_axc_basic_frame_add(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, 7955 cw_len, frame_len-cw_len)); 7956 } 7957 /* 7958 * Set the control word to be forwarded to encap with 7959 * AxC ID is 0. 7960 */ 7961 7962 _SOC_IF_ERR_EXIT 7963 (cprif_drv_rx_framer_agnostic_mode_set(unit, port, 0 /* AxC_ID */, enable, cprimod_agnostic_mode_cpri)); 7964 7965 } else { /* CPRIMOD_DIR_TX case */ 7966 7967 /* 7968 * Setup Tx Basic Frame Assebler Table. 7969 */ 7970 7971 _SOC_IF_ERR_EXIT(cprif_drv_cpri_txpcs_speed_get(unit, port, &speed)); 7972 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_clear(unit, port)); 7973 7974 if (enable) { 7975 /* 7976 * Adding AxC for the whole frame. Not require to add control frame as it 7977 * will come from RoE frame. Need to set the control word size to 0. 7978 */ 7979 frame_len = _cprif_from_speed_toframe_len(speed); 7980 7981 /* 7982 * Special Table handling for BFA table. 7983 */ 7984 cprif_bfa_bfp_table_entry_t_init(&table_entry); 7985 _SOC_IF_ERR_EXIT 7986 (cprif_drv_basic_frame_assembly_active_table_get(unit, port, &active_table)); 7987 7988 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 7989 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 7990 } else { 7991 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 7992 } 7993 7994 bits_cnt = frame_len; 7995 table_entry.axc_id = CPRIMOD_AXC_ID_AGNOSTIC; 7996 table_entry.rsrv_bit_cnt = 0; 7997 while (bits_cnt) { 7998 if (bits_cnt > CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY) { 7999 table_entry.data_bit_cnt = CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY ; 8000 } else { 8001 table_entry.data_bit_cnt = bits_cnt; 8002 } 8003 8004 bits_cnt -= table_entry.data_bit_cnt; 8005 _SOC_IF_ERR_EXIT 8006 (cprif_drv_basic_frame_entry_set(unit, port, 8007 standby_table, 8008 CPRIMOD_DIR_TX, 8009 current_index, 8010 &table_entry)); 8011 current_index++; 8012 } 8013 _SOC_IF_ERR_EXIT 8014 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, standby_table, current_index)); 8015 8016 _SOC_IF_ERR_EXIT 8017 (cprif_drv_tx_control_word_size_set(unit, port, 0)); 8018 } else { /* disable case */ 8019 /* 8020 * Adding control word back, and set the control word size. 8021 */ 8022 cw_len = _cprif_from_speed_towd_len(speed); 8023 _SOC_IF_ERR_EXIT 8024 (cprif_tx_axc_basic_frame_add(unit, port, CPRIMOD_AXC_ID_CONTROL, 8025 0, cw_len)); 8026 _SOC_IF_ERR_EXIT 8027 (cprif_drv_tx_control_word_size_set(unit, port, cw_len/8)); 8028 } 8029 } 8030 8031 exit: 8032 SOC_FUNC_RETURN; 8033 8034 } 8035 8036 int cprif_cpri_interface_bus_width_get(int unit, int port, int* is_10bit_mode) 8037 { 8038 SOC_INIT_FUNC_DEFS; 8039 8040 _SOC_IF_ERR_EXIT (cprif_drv_rxpcs_interface_width_get(unit, port, is_10bit_mode)); 8041 8042 exit: 8043 SOC_FUNC_RETURN; 8044 8045 } 8046 8047 int cprif_cpri_tunnel_mode_basic_frame_config_set(int unit, int port, cprimod_direction_t dir, int enable) 8048 { 8049 uint8 active_table; 8050 uint8 standby_table; 8051 cprif_bfa_bfp_table_entry_t table_entry; 8052 int index=0; 8053 int is_10bit = -1; 8054 cprimod_port_interface_type_t interface_type=0; 8055 cprimod_port_speed_t speed=0; 8056 uint32 cw_len; 8057 8058 SOC_INIT_FUNC_DEFS; 8059 8060 if (dir == CPRIMOD_DIR_RX) { 8061 8062 /* 8063 * Setup Rx Basic Frame Parser Table. 8064 */ 8065 8066 _SOC_IF_ERR_EXIT 8067 (cprif_drv_basic_frame_parser_active_table_get(unit, port, &active_table)); 8068 8069 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 8070 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 8071 } else { 8072 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 8073 } 8074 8075 _SOC_IF_ERR_EXIT (cprif_drv_rxpcs_interface_width_get(unit, port, &is_10bit)); 8076 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_clear(unit, port)); 8077 8078 if (enable) { 8079 8080 cprif_bfa_bfp_table_entry_t_init(&table_entry); 8081 table_entry.axc_id = CPRIMOD_AXC_ID_AGNOSTIC; 8082 8083 if (is_10bit) { 8084 table_entry.rsrv_bit_cnt = 54; 8085 table_entry.data_bit_cnt = 10; 8086 } else { 8087 table_entry.rsrv_bit_cnt = 24; 8088 table_entry.data_bit_cnt = 40; 8089 } 8090 8091 for (index = 0; index < CPRIF_TUNNEL_MODE_NUM_OF_BFP_ENTRIES ; index++) { 8092 _SOC_IF_ERR_EXIT 8093 (cprif_drv_basic_frame_entry_set(unit, port, 8094 standby_table, 8095 CPRIMOD_DIR_RX, 8096 index, 8097 &table_entry)); 8098 } 8099 _SOC_IF_ERR_EXIT 8100 (cprif_drv_basic_frame_parser_table_num_entries_set(unit, port, 8101 standby_table, 8102 CPRIF_TUNNEL_MODE_NUM_OF_BFP_ENTRIES)); 8103 } 8104 8105 _SOC_IF_ERR_EXIT 8106 (cprif_drv_rx_framer_agnostic_mode_set(unit, port, 8107 CPRIMOD_AXC_ID_AGNOSTIC, 8108 enable, 8109 cprimod_agnostic_mode_tunnel)); 8110 8111 } else { /* CPRIMOD_DIR_TX case */ 8112 8113 /* 8114 * Setup Tx Basic Frame Assebler Table. 8115 */ 8116 8117 _SOC_IF_ERR_EXIT 8118 (cprif_drv_basic_frame_assembly_active_table_get(unit, port, &active_table)); 8119 8120 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 8121 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 8122 } else { 8123 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 8124 } 8125 8126 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_clear(unit, port)); 8127 8128 if (enable) { 8129 8130 /* TX side is always 40 bits interface. */ 8131 cprif_bfa_bfp_table_entry_t_init(&table_entry); 8132 table_entry.axc_id = CPRIMOD_AXC_ID_AGNOSTIC; 8133 table_entry.rsrv_bit_cnt = 24; 8134 table_entry.data_bit_cnt = 40; 8135 8136 for (index = 0; index < CPRIF_TUNNEL_MODE_NUM_OF_BFA_ENTRIES ; index++) { 8137 _SOC_IF_ERR_EXIT 8138 (cprif_drv_basic_frame_entry_set(unit, port, 8139 standby_table, 8140 CPRIMOD_DIR_TX, 8141 index, 8142 &table_entry)); 8143 } 8144 _SOC_IF_ERR_EXIT 8145 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, 8146 standby_table, 8147 CPRIF_TUNNEL_MODE_NUM_OF_BFA_ENTRIES)); 8148 _SOC_IF_ERR_EXIT 8149 (cprif_drv_tx_control_word_size_set(unit, port, 0)); 8150 8151 } else { /* Disable */ 8152 8153 _SOC_IF_ERR_EXIT 8154 (cprif_drv_txcpri_port_type_get(unit, port, &interface_type)); 8155 if (interface_type == cprimodRsvd4) { 8156 _SOC_IF_ERR_EXIT 8157 (_cprif_port_rsvd4_basic_frame_table_set (unit, port, CPRIMOD_DIR_TX)); 8158 8159 } else { /* CPRI port */ 8160 _SOC_IF_ERR_EXIT 8161 (cprif_drv_cpri_txpcs_speed_get(unit, port, &speed)); 8162 cw_len = _cprif_from_speed_towd_len(speed); 8163 _SOC_IF_ERR_EXIT 8164 (cprif_tx_axc_basic_frame_add(unit, port, CPRIMOD_AXC_ID_CONTROL, 0, cw_len)); 8165 _SOC_IF_ERR_EXIT 8166 (cprif_drv_tx_control_word_size_set(unit, port, cw_len/8)); 8167 } 8168 } 8169 } 8170 exit: 8171 SOC_FUNC_RETURN; 8172 8173 } 8174 8175 8176 int cprif_rsvd4_agnostic_mode_basic_frame_config_set(int unit, int port, cprimod_direction_t dir, int enable) 8177 { 8178 uint8 active_table; 8179 uint8 standby_table; 8180 cprif_bfa_bfp_table_entry_t table_entry; 8181 int index=0; 8182 8183 SOC_INIT_FUNC_DEFS; 8184 8185 if (dir == CPRIMOD_DIR_RX) { 8186 8187 _SOC_IF_ERR_EXIT 8188 (cprif_drv_rx_framer_agnostic_mode_set(unit, port, 8189 CPRIMOD_AXC_ID_AGNOSTIC, 8190 enable, 8191 cprimod_agnostic_mode_rsvd4)); 8192 /* 8193 * Setup Rx Basic Frame Parser Table. 8194 */ 8195 8196 _SOC_IF_ERR_EXIT 8197 (cprif_drv_basic_frame_parser_active_table_get(unit, port, &active_table)); 8198 8199 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 8200 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 8201 } else { 8202 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 8203 } 8204 8205 _SOC_IF_ERR_EXIT(cprif_rx_axc_basic_frame_clear(unit, port)); 8206 8207 if (enable) { 8208 8209 cprif_bfa_bfp_table_entry_t_init(&table_entry); 8210 table_entry.axc_id = CPRIMOD_AXC_ID_AGNOSTIC; 8211 8212 table_entry.rsrv_bit_cnt = 0; 8213 table_entry.data_bit_cnt = 128; 8214 8215 for (index = 0; index < CPRIF_RSVD4_AGNOSTIC_MODE_NUM_OF_BFP_ENTRIES; index++) { 8216 _SOC_IF_ERR_EXIT 8217 (cprif_drv_basic_frame_entry_set(unit, port, 8218 standby_table, 8219 CPRIMOD_DIR_RX, 8220 index, 8221 &table_entry)); 8222 } 8223 _SOC_IF_ERR_EXIT 8224 (cprif_drv_basic_frame_parser_table_num_entries_set(unit, port, 8225 standby_table, 8226 CPRIF_RSVD4_AGNOSTIC_MODE_NUM_OF_BFP_ENTRIES)); 8227 } 8228 } else { /* CPRIMOD_DIR_TX case */ 8229 8230 /* 8231 * Setup Tx Basic Frame Assebler Table. 8232 */ 8233 8234 _SOC_IF_ERR_EXIT 8235 (cprif_drv_basic_frame_assembly_active_table_get(unit, port, &active_table)); 8236 8237 if (active_table == CPRIF_BASIC_FRAME_TABLE_0) { 8238 standby_table = CPRIF_BASIC_FRAME_TABLE_1; 8239 } else { 8240 standby_table = CPRIF_BASIC_FRAME_TABLE_0; 8241 } 8242 8243 _SOC_IF_ERR_EXIT(cprif_tx_axc_basic_frame_clear(unit, port)); 8244 8245 if (enable) { 8246 8247 cprif_bfa_bfp_table_entry_t_init(&table_entry); 8248 table_entry.axc_id = CPRIMOD_AXC_ID_AGNOSTIC; 8249 table_entry.rsrv_bit_cnt = 0; 8250 table_entry.data_bit_cnt = 128; 8251 8252 for (index = 0; index < CPRIF_RSVD4_AGNOSTIC_MODE_NUM_OF_BFA_ENTRIES; index++) { 8253 _SOC_IF_ERR_EXIT 8254 (cprif_drv_basic_frame_entry_set(unit, port, 8255 standby_table, 8256 CPRIMOD_DIR_TX, 8257 index, 8258 &table_entry)); 8259 } 8260 _SOC_IF_ERR_EXIT 8261 (cprif_drv_basic_frame_assembly_table_num_entries_set(unit, port, 8262 standby_table, 8263 CPRIF_RSVD4_AGNOSTIC_MODE_NUM_OF_BFA_ENTRIES)); 8264 8265 } else { /* disable case */ 8266 } 8267 8268 _SOC_IF_ERR_EXIT 8269 (cprif_drv_tx_framer_rsvd4_agnostic_mode_set(unit, port, enable)); 8270 } 8271 8272 exit: 8273 SOC_FUNC_RETURN; 8274 } 8275 8276 int cprif_encap_presentation_time_enable_set(int unit, int port, int enable) 8277 { 8278 SOC_INIT_FUNC_DEFS; 8279 8280 _SOC_IF_ERR_EXIT 8281 (cprif_drv_ingress_presentation_time_enable_set(unit, port, enable)); 8282 8283 exit: 8284 SOC_FUNC_RETURN; 8285 8286 } 8287 8288 int cprif_encap_presentation_time_enable_get(int unit, int port, int* enable) 8289 { 8290 SOC_INIT_FUNC_DEFS; 8291 8292 _SOC_IF_ERR_EXIT 8293 (cprif_drv_ingress_presentation_time_enable_get(unit, port, enable)); 8294 8295 exit: 8296 SOC_FUNC_RETURN; 8297 8298 } 8299 8300 int cprif_encap_presentation_time_config_set(int unit, int port, const cprimod_encap_presentation_time_config_t* config) 8301 { 8302 cprif_cpri_ingress_pres_time_ctrl_t pres_time_config; 8303 SOC_INIT_FUNC_DEFS; 8304 8305 pres_time_config.pres_mod_cnt = config->mod_count; 8306 pres_time_config.bfn_offset = config->radio_frame_offset; 8307 pres_time_config.hfn_offset = config->hyper_frame_offset; 8308 8309 8310 pres_time_config.hfrm_sync = 0; 8311 pres_time_config.rfrm_sync = 0; 8312 8313 if (config->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER) { 8314 pres_time_config.hfrm_sync = 1; 8315 pres_time_config.rfrm_sync = 0; /* don't care */ 8316 8317 } else if (config->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO) { 8318 pres_time_config.hfrm_sync = 0; 8319 pres_time_config.rfrm_sync = 1; 8320 } else if (config->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC) { 8321 pres_time_config.hfrm_sync = 0; 8322 pres_time_config.rfrm_sync = 0; 8323 } else if (config->frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_TUNNEL) { 8324 pres_time_config.hfrm_sync = 1; 8325 pres_time_config.rfrm_sync = 1; 8326 } 8327 8328 pres_time_config.approx_inc_disable = config->approx_inc_disable; 8329 8330 _SOC_IF_ERR_EXIT 8331 (cprif_drv_ingress_presentation_time_config_set(unit, port, &pres_time_config)); 8332 8333 exit: 8334 SOC_FUNC_RETURN; 8335 8336 } 8337 8338 int cprif_encap_presentation_time_config_get(int unit, int port, cprimod_encap_presentation_time_config_t* config) 8339 { 8340 cprif_cpri_ingress_pres_time_ctrl_t pres_time_config; 8341 SOC_INIT_FUNC_DEFS; 8342 8343 _SOC_IF_ERR_EXIT 8344 (cprif_drv_ingress_presentation_time_config_get(unit, port, &pres_time_config)); 8345 8346 config->mod_count = pres_time_config.pres_mod_cnt; 8347 config->radio_frame_offset = pres_time_config.bfn_offset; 8348 config->hyper_frame_offset = pres_time_config.hfn_offset; 8349 8350 if (pres_time_config.hfrm_sync == 1) { 8351 config->frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER; 8352 } else { 8353 if(pres_time_config.rfrm_sync == 1) { 8354 config->frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO; 8355 } else { 8356 config->frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC; 8357 } 8358 } 8359 8360 exit: 8361 SOC_FUNC_RETURN; 8362 8363 } 8364 8365 int cprif_encap_presentation_time_adjust_set(int unit, int port, uint32 time) 8366 { 8367 SOC_INIT_FUNC_DEFS; 8368 8369 _SOC_IF_ERR_EXIT 8370 (cprif_drv_ingress_presentation_time_adjust_set(unit, port, time)); 8371 8372 exit: 8373 SOC_FUNC_RETURN; 8374 8375 } 8376 8377 int cprif_encap_presentation_time_adjust_get(int unit, int port, uint32* time) 8378 { 8379 SOC_INIT_FUNC_DEFS; 8380 8381 _SOC_IF_ERR_EXIT 8382 (cprif_drv_ingress_presentation_time_adjust_get(unit, port, time)); 8383 8384 8385 exit: 8386 SOC_FUNC_RETURN; 8387 8388 } 8389 8390 int cprif_encap_presentation_time_approximate_increment_set(int unit, int port, uint32 time) 8391 { 8392 SOC_INIT_FUNC_DEFS; 8393 8394 _SOC_IF_ERR_EXIT 8395 (cprif_drv_ingress_presentation_time_approximate_increment_set(unit, port, time)); 8396 8397 exit: 8398 SOC_FUNC_RETURN; 8399 8400 } 8401 8402 int cprif_encap_presentation_time_approximate_increment_get(int unit, int port, uint32* time) 8403 { 8404 SOC_INIT_FUNC_DEFS; 8405 8406 _SOC_IF_ERR_EXIT 8407 (cprif_drv_ingress_presentation_time_approximate_increment_get(unit, port, time)); 8408 8409 exit: 8410 SOC_FUNC_RETURN; 8411 8412 } 8413 8414 int cprif_decap_agnostic_mode_enable_set(int unit, int port, int enable, cprimod_cpri_roe_ordering_info_option_t mode) 8415 { 8416 SOC_INIT_FUNC_DEFS; 8417 8418 _SOC_IF_ERR_EXIT 8419 (cprif_drv_egress_agnostic_mode_enable_set(unit, port, enable, mode)); 8420 8421 exit: 8422 SOC_FUNC_RETURN; 8423 8424 } 8425 8426 int cprif_decap_agnostic_mode_enable_get(int unit, int port, int* enable, cprimod_cpri_roe_ordering_info_option_t* mode) 8427 { 8428 SOC_INIT_FUNC_DEFS; 8429 8430 _SOC_IF_ERR_EXIT 8431 (cprif_drv_egress_agnostic_mode_enable_get(unit, port, enable, mode)); 8432 8433 exit: 8434 SOC_FUNC_RETURN; 8435 } 8436 8437 int cprif_decap_agnostic_mode_config_set(int unit, int port, const cprimod_decap_agnostic_mode_config_t* config) 8438 { 8439 cprif_cpri_egress_agnostic_config_t cprif_config; 8440 SOC_INIT_FUNC_DEFS; 8441 8442 /* 8443 * calculate cycle size x buffer size to # of 16 bytes buffer 8444 */ 8445 8446 cprif_config.rd_ptr_max = (CPRIF_NUM_OF_BUFFER_ENTRIES(config->packet_size) * config->mod_count); 8447 8448 if ( cprif_config.rd_ptr_max >= CPRIF_DECAP_BUFFER_NUM_ENTRIES) { 8449 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("\n Requested Buffer %d Max Buffer Entries %d, Packet Size %d bytes Cycle Size %d.\n", 8450 cprif_config.rd_ptr_max, 8451 CPRIF_DECAP_BUFFER_NUM_ENTRIES, 8452 config->packet_size, 8453 config->mod_count)); 8454 } 8455 8456 cprif_config.queue_num = config->queue_num; 8457 cprif_config.mod_cnt = config->mod_count; 8458 8459 _SOC_IF_ERR_EXIT 8460 (cprif_drv_egress_agnostic_mode_config_set(unit, port, &cprif_config)); 8461 exit: 8462 SOC_FUNC_RETURN; 8463 8464 } 8465 8466 int cprif_decap_agnostic_mode_config_get(int unit, int port, cprimod_decap_agnostic_mode_config_t* config) 8467 { 8468 cprif_cpri_egress_agnostic_config_t cprif_config; 8469 SOC_INIT_FUNC_DEFS; 8470 8471 _SOC_IF_ERR_EXIT 8472 (cprif_drv_egress_agnostic_mode_config_get(unit, port, &cprif_config)); 8473 config->packet_size = ((cprif_config.rd_ptr_max)/cprif_config.mod_cnt)*CPRIF_DATA_BUFFER_BLOCK_SIZE; 8474 config->queue_num = cprif_config.queue_num; 8475 config->mod_count = cprif_config.mod_cnt; 8476 exit: 8477 SOC_FUNC_RETURN; 8478 } 8479 8480 int cprif_decap_presentation_time_config_set(int unit, int port, uint32 mod_offset, uint32 mod_count) 8481 { 8482 SOC_INIT_FUNC_DEFS; 8483 8484 _SOC_IF_ERR_EXIT 8485 (cprif_drv_egress_presentation_time_config_set(unit, port, mod_offset, mod_count)); 8486 exit: 8487 SOC_FUNC_RETURN; 8488 8489 } 8490 8491 int cprif_decap_presentation_time_config_get(int unit, int port, uint32* mod_offset, uint32* mod_count) 8492 { 8493 SOC_INIT_FUNC_DEFS; 8494 8495 _SOC_IF_ERR_EXIT 8496 (cprif_drv_egress_presentation_time_config_get(unit, port, mod_offset, mod_count)); 8497 exit: 8498 SOC_FUNC_RETURN; 8499 } 8500 8501 int cprif_compression_lookup_table_set(int unit, int port, int table_depth, const uint32* table) 8502 { 8503 int index =0; 8504 SOC_INIT_FUNC_DEFS; 8505 8506 if (table_depth < CPRIF_COMPRESSION_TABLE_SIZE) { 8507 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("\n Table Need 1024 entries.")); 8508 } 8509 8510 for (index = 0; index < CPRIF_COMPRESSION_TABLE_SIZE; index++) { 8511 _SOC_IF_ERR_EXIT 8512 (cprif_drv_compression_entry_set(unit, port, index, table[index], table[index])); 8513 } 8514 exit: 8515 SOC_FUNC_RETURN; 8516 8517 } 8518 8519 int cprif_compression_lookup_table_get(int unit, int port, int max_depth, int* table_depth, uint32* table) 8520 { 8521 int index =0; 8522 SOC_INIT_FUNC_DEFS; 8523 8524 if (max_depth < CPRIF_COMPRESSION_TABLE_SIZE) { 8525 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("\n Table Buffer Need 1024 entries.")); 8526 } 8527 8528 for (index = 0; index < CPRIF_COMPRESSION_TABLE_SIZE; index++) { 8529 _SOC_IF_ERR_EXIT 8530 (cprif_drv_compression_entry_get(unit, port, index, &table[index], &table[index])); 8531 } 8532 *table_depth = CPRIF_COMPRESSION_TABLE_SIZE; 8533 exit: 8534 SOC_FUNC_RETURN; 8535 8536 } 8537 8538 int cprif_decompression_lookup_table_set(int unit, int port, int table_depth, const uint32* table) 8539 { 8540 int index =0; 8541 SOC_INIT_FUNC_DEFS; 8542 8543 if (table_depth < CPRIF_DECOMPRESSION_TABLE_SIZE) { 8544 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("\n Table Need 256 entries.")); 8545 } 8546 8547 for (index = 0; index < CPRIF_DECOMPRESSION_TABLE_SIZE; index++) { 8548 _SOC_IF_ERR_EXIT 8549 (cprif_drv_decompression_entry_set(unit, port, index, table[index])); 8550 } 8551 exit: 8552 SOC_FUNC_RETURN; 8553 } 8554 8555 int cprif_decompression_lookup_table_get(int unit, int port, int max_depth, int* table_depth, uint32* table) 8556 { 8557 int index =0; 8558 SOC_INIT_FUNC_DEFS; 8559 8560 if (max_depth < CPRIF_DECOMPRESSION_TABLE_SIZE) { 8561 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("\n Buffer Need 256 entries.")); 8562 } 8563 8564 for (index = 0; index < CPRIF_DECOMPRESSION_TABLE_SIZE; index++) { 8565 _SOC_IF_ERR_EXIT 8566 (cprif_drv_decompression_entry_get(unit, port, index, &table[index])); 8567 } 8568 *table_depth = CPRIF_DECOMPRESSION_TABLE_SIZE; 8569 exit: 8570 SOC_FUNC_RETURN; 8571 } 8572 8573 int cprif_cpri_port_decap_queue_flow_control_set(int unit, int port, uint32 queue_num, int enable, uint32_t xon_threshold, uint32_t xoff_threshold) 8574 { 8575 int index = 0; 8576 uint32 xon_num_buff; 8577 uint32 xoff_num_buff; 8578 SOC_INIT_FUNC_DEFS; 8579 8580 if ((queue_num < CPRIF_CONTROL_FLOW_MIN_QUEUE_NUM) || 8581 (queue_num >= CPRIF_MAX_NUM_OF_QUEUES)) { 8582 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("\n Cannot Support Flow Control on this Queue.")); 8583 } 8584 index = queue_num - CPRIF_CONTROL_FLOW_MIN_QUEUE_NUM; 8585 xon_num_buff = CPRIF_NUM_OF_BUFFER_ENTRIES(xon_threshold); 8586 xoff_num_buff = CPRIF_NUM_OF_BUFFER_ENTRIES(xoff_threshold); 8587 8588 _SOC_IF_ERR_EXIT 8589 (cprif_drv_decap_queue_flow_control_entry_set(unit, port, 8590 index, 8591 enable, 8592 queue_num, 8593 xon_num_buff, 8594 xoff_num_buff)); 8595 8596 8597 8598 exit: 8599 SOC_FUNC_RETURN; 8600 8601 } 8602 8603 int cprif_cpri_port_decap_queue_flow_control_get(int unit, int port, uint32 queue_num, int* enable, uint32_t* xon_threshold, uint32_t* xoff_threshold) 8604 { 8605 int index=0; 8606 uint32 hw_queue_num=0; 8607 uint32 xon_num_buff=0; 8608 uint32 xoff_num_buff=0; 8609 SOC_INIT_FUNC_DEFS; 8610 8611 if ((queue_num < CPRIF_CONTROL_FLOW_MIN_QUEUE_NUM) || 8612 (queue_num >= CPRIF_MAX_NUM_OF_QUEUES)) { 8613 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("\n Cannot Support Flow Control on this Queue.")); 8614 } 8615 index = queue_num - CPRIF_CONTROL_FLOW_MIN_QUEUE_NUM; 8616 8617 _SOC_IF_ERR_EXIT 8618 (cprif_drv_decap_queue_flow_control_entry_get(unit, port, 8619 index, 8620 enable, 8621 &hw_queue_num, 8622 &xon_num_buff, 8623 &xoff_num_buff)); 8624 *xon_threshold = xon_num_buff * CPRIF_DATA_BUFFER_BLOCK_SIZE; 8625 *xoff_threshold = xoff_num_buff * CPRIF_DATA_BUFFER_BLOCK_SIZE; 8626 8627 exit: 8628 SOC_FUNC_RETURN; 8629 8630 } 8631 8632 int cprif_cpri_port_fec_enable_set(int unit, int port, cprimod_direction_t dir, int enable) 8633 { 8634 SOC_INIT_FUNC_DEFS; 8635 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_fec_enable_set(unit, port, dir, enable)); 8636 exit: 8637 SOC_FUNC_RETURN; 8638 8639 } 8640 8641 int cprif_cpri_port_fec_enable_get(int unit, int port, cprimod_direction_t dir, int* enable) 8642 { 8643 SOC_INIT_FUNC_DEFS; 8644 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_fec_enable_get(unit, port, dir, enable)); 8645 exit: 8646 SOC_FUNC_RETURN; 8647 8648 } 8649 8650 int cprif_cpri_port_fec_timestamp_config_set(int unit, int port, cprimod_direction_t dir, const cprimod_fec_timestamp_config_t* config) 8651 { 8652 SOC_INIT_FUNC_DEFS; 8653 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_fec_timestamp_config_set(unit, port, dir, config)); 8654 exit: 8655 SOC_FUNC_RETURN; 8656 8657 } 8658 8659 int cprif_cpri_port_fec_timestamp_config_get(int unit, int port, cprimod_direction_t dir, cprimod_fec_timestamp_config_t* config) 8660 { 8661 SOC_INIT_FUNC_DEFS; 8662 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_fec_timestamp_config_get(unit, port, dir, config)); 8663 exit: 8664 SOC_FUNC_RETURN; 8665 8666 } 8667 8668 int cprif_cpri_port_fec_aux_config_set(int unit, int port, cprimod_fec_aux_config_para_t parameter_id, uint32 value) 8669 { 8670 SOC_INIT_FUNC_DEFS; 8671 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_fec_aux_config_set(unit, port, parameter_id, value)); 8672 exit: 8673 SOC_FUNC_RETURN; 8674 8675 } 8676 8677 int cprif_cpri_port_fec_aux_config_get(int unit, int port, cprimod_fec_aux_config_para_t parameter_id, uint32* value) 8678 { 8679 SOC_INIT_FUNC_DEFS; 8680 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_fec_aux_config_get(unit, port, parameter_id, value)); 8681 exit: 8682 SOC_FUNC_RETURN; 8683 8684 } 8685 8686 int cprif_cpri_port_ecc_interrupt_enable_set(int unit, int port, int enable) 8687 { 8688 SOC_INIT_FUNC_DEFS; 8689 8690 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_ecc_interrupt_enable_set(unit, 8691 port, enable)); 8692 8693 exit: 8694 SOC_FUNC_RETURN; 8695 } 8696 8697 int cprif_cpri_port_ecc_interrupt_status_get(int unit, int port, 8698 cprimod_cpri_ecc_intr_info_t *ecc_err_info) 8699 { 8700 SOC_INIT_FUNC_DEFS; 8701 8702 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_ecc_interrupt_status_get(unit, port, 8703 ecc_err_info)); 8704 8705 exit: 8706 SOC_FUNC_RETURN; 8707 } 8708 8709 #ifdef CPRIMOD_SUPPORT_ECC_INJECT 8710 int cprif_cpri_port_ecc_interrupt_test(int unit, int port) 8711 { 8712 SOC_INIT_FUNC_DEFS; 8713 8714 _SOC_IF_ERR_EXIT(cprif_drv_cpri_port_ecc_interrupt_test(unit, port)); 8715 8716 exit: 8717 SOC_FUNC_RETURN; 8718 } 8719 #endif 8720 8721 int cprif_cpri_port_reset_set(int unit, int port, int rst) 8722 { 8723 SOC_INIT_FUNC_DEFS; 8724 _SOC_IF_ERR_EXIT(cprif_drv_datapath_tx_h_reset_set(unit, port, rst)); 8725 _SOC_IF_ERR_EXIT(cprif_drv_datapath_rx_h_reset_set(unit, port, rst)); 8726 8727 exit: 8728 SOC_FUNC_RETURN; 8729 8730 } 8731 8732 int cprif_cpri_port_reset_get(int unit, int port, int* rst) 8733 { 8734 SOC_INIT_FUNC_DEFS; 8735 _SOC_IF_ERR_EXIT(cprif_drv_datapath_rx_h_reset_get(unit, port, rst)); 8736 8737 exit: 8738 SOC_FUNC_RETURN; 8739 8740 } 8741 8742 int cprif_cpri_init(int unit, int port) 8743 { 8744 SOC_INIT_FUNC_DEFS; 8745 _SOC_IF_ERR_EXIT(cprif_drv_init(unit, port)); 8746 8747 exit: 8748 SOC_FUNC_RETURN; 8749 } 8750 8751 int cprif_cpri_port_rx_gcw_word_get(int unit, int port, int group_index, uint16* gcw_word) 8752 { 8753 SOC_INIT_FUNC_DEFS; 8754 8755 _SOC_IF_ERR_EXIT 8756 (cprif_drv_rx_gcw_word_get(unit, port, group_index, gcw_word)); 8757 8758 exit: 8759 SOC_FUNC_RETURN; 8760 8761 } 8762 8763 8764 int cprif_cpri_port_tx_gcw_word_set(int unit, int port, int group_index, uint16 gcw_word) 8765 { 8766 SOC_INIT_FUNC_DEFS; 8767 8768 _SOC_IF_ERR_EXIT 8769 (cprif_drv_tx_gcw_word_set(unit, port, group_index, gcw_word)); 8770 8771 exit: 8772 SOC_FUNC_RETURN; 8773 8774 } 8775 8776 int cprif_cpri_mac_drain_start(int unit, int port) 8777 { 8778 SOC_INIT_FUNC_DEFS; 8779 8780 _SOC_IF_ERR_EXIT 8781 (cprif_drv_tx_flush_set(unit, port, 1)); 8782 exit: 8783 SOC_FUNC_RETURN; 8784 8785 } 8786 8787 int cprif_cpri_mac_drain_stop(int unit, int port) 8788 { 8789 SOC_INIT_FUNC_DEFS; 8790 8791 _SOC_IF_ERR_EXIT 8792 (cprif_drv_tx_flush_set(unit, port, 0)); 8793 exit: 8794 SOC_FUNC_RETURN; 8795 8796 } 8797 8798 int cprif_cpri_mac_credit_reset_set(int unit, int port, int rst) 8799 { 8800 SOC_INIT_FUNC_DEFS; 8801 8802 _SOC_IF_ERR_EXIT 8803 (cprif_drv_datapath_credit_reset_set(unit, port, rst)); 8804 8805 8806 exit: 8807 SOC_FUNC_RETURN; 8808 8809 } 8810 8811 int cprif_cpri_mac_credit_reset_get(int unit, int port, int* rst) 8812 { 8813 SOC_INIT_FUNC_DEFS; 8814 8815 _SOC_IF_ERR_EXIT 8816 (cprif_drv_datapath_credit_reset_get(unit, port, rst)); 8817 8818 8819 exit: 8820 SOC_FUNC_RETURN; 8821 8822 } 8823 8824 int cprif_cpri_port_link_up_event(int unit, int port) 8825 { 8826 SOC_INIT_FUNC_DEFS; 8827 8828 #if 0 8829 LOG_CLI(("Port(%s)-%d Link Up Event \n", 8830 SOC_PORT_NAME(unit, port), port)); 8831 #endif 8832 _SOC_IF_ERR_EXIT 8833 (cprif_drv_cpri_byte_error_count_clear(unit, port)); 8834 _SOC_IF_ERR_EXIT 8835 (cprif_drv_cpri_work_queue_interrupt_status_clear(unit, port)); 8836 exit: 8837 SOC_FUNC_RETURN; 8838 8839 } 8840 8841 int cprif_cpri_port_link_down_event(int unit, int port) 8842 { 8843 SOC_INIT_FUNC_DEFS; 8844 8845 #if 0 8846 LOG_CLI(("Port(%s)-%d Link Down Resetting Port \n", 8847 SOC_PORT_NAME(unit, port), port)); 8848 #endif 8849 _SOC_IF_ERR_EXIT 8850 (cprif_drv_port_link_down_reset(unit, port)); 8851 exit: 8852 SOC_FUNC_RETURN; 8853 8854 } 8855 8856 int cprif_cpri_port_rx_tunnel_mode_set(int unit, int port, int enable, uint32 payload_size) 8857 { 8858 uint32 timestamp_interval; 8859 SOC_INIT_FUNC_DEFS; 8860 8861 timestamp_interval = payload_size; 8862 _SOC_IF_ERR_EXIT 8863 (cprif_drv_rxpcs_tunnel_mode_set(unit, port, enable, timestamp_interval)); 8864 8865 exit: 8866 SOC_FUNC_RETURN; 8867 8868 } 8869 8870 int cprif_cpri_port_rx_tunnel_mode_get(int unit, int port, int* enable, uint32* payload_size) 8871 { 8872 uint32 timestamp_interval; 8873 SOC_INIT_FUNC_DEFS; 8874 8875 8876 _SOC_IF_ERR_EXIT 8877 (cprif_drv_rxpcs_tunnel_mode_get(unit, port, enable, ×tamp_interval)); 8878 8879 if (*enable) { 8880 *payload_size = timestamp_interval; 8881 } 8882 8883 exit: 8884 SOC_FUNC_RETURN; 8885 8886 } 8887 8888 int cprif_cpri_port_tx_agnostic_mode_set(int unit, int port, int enable, cprimod_agnostic_mode_type_t mode, uint32 payload_size) 8889 { 8890 uint32 timestamp_interval; 8891 SOC_INIT_FUNC_DEFS; 8892 8893 timestamp_interval = payload_size; 8894 _SOC_IF_ERR_EXIT 8895 (cprif_drv_txpcs_agnostic_mode_set(unit, port, enable, mode, timestamp_interval)); 8896 8897 exit: 8898 SOC_FUNC_RETURN; 8899 8900 } 8901 8902 int cprif_cpri_port_tx_agnostic_mode_get(int unit, int port, int* enable, cprimod_agnostic_mode_type_t* mode, uint32* payload_size) 8903 { 8904 uint32 timestamp_interval; 8905 SOC_INIT_FUNC_DEFS; 8906 8907 _SOC_IF_ERR_EXIT 8908 (cprif_drv_txpcs_agnostic_mode_get(unit, port, enable, mode, ×tamp_interval)); 8909 8910 if (*enable) { 8911 *payload_size = timestamp_interval; 8912 } 8913 8914 exit: 8915 SOC_FUNC_RETURN; 8916 8917 } 8918 8919 int cprif_cpri_port_rx_agnostic_mode_get(int unit, int port, int* enable, cprimod_agnostic_mode_type_t* mode) 8920 { 8921 uint32 axc_id=0xfe; 8922 SOC_INIT_FUNC_DEFS; 8923 8924 _SOC_IF_ERR_EXIT 8925 (cprif_drv_rx_framer_agnostic_mode_get(unit, port, &axc_id, enable, mode)); 8926 8927 exit: 8928 SOC_FUNC_RETURN; 8929 8930 } 8931 8932 int cprif_cpri_port_link_get(int unit, int port, int* link) 8933 { 8934 int tunnel_mode=FALSE; 8935 uint32 payload; 8936 uint32 value=0; 8937 SOC_INIT_FUNC_DEFS; 8938 8939 SOC_IF_ERROR_RETURN 8940 (cprif_cpri_port_rx_tunnel_mode_get(unit, port, &tunnel_mode, &payload)); 8941 8942 /* 8943 * If tunnel mode, get status from PMD since PCS is bypassed. 8944 */ 8945 if (tunnel_mode) { 8946 _SOC_IF_ERR_EXIT 8947 (cprif_port_pmd_status_get(unit, port,cprimodPmdPortStatusRxLock, &value)); 8948 } else { 8949 _SOC_IF_ERR_EXIT 8950 (cprif_port_rx_pcs_status_get(unit, port, cprimodRxPcsStatusLinkStatusLive, &value)); 8951 } 8952 8953 *link = (value != 0)? 1:0; 8954 exit: 8955 SOC_FUNC_RETURN; 8956 8957 } 8958 8959 uint32 _cprimod_to_cprif_drv_roe_header_field(cprimod_cpri_roe_header_field_t cprimod_field) 8960 { 8961 uint32 cprif_drv_field; 8962 8963 switch (cprimod_field) { 8964 case CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE: 8965 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_SUBTYPE; 8966 break; 8967 8968 case CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID: 8969 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_FLOW_ID; 8970 break; 8971 8972 case CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8: 8973 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_15_8; 8974 break; 8975 8976 case CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0: 8977 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_7_0; 8978 break; 8979 8980 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24: 8981 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_31_24; 8982 break; 8983 8984 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16: 8985 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_23_16; 8986 break; 8987 8988 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8: 8989 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_15_8; 8990 break; 8991 8992 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0: 8993 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_7_0; 8994 break; 8995 8996 case CPRIMOD_CPRI_ROE_HEADER_FIELD_OPCODE: 8997 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_OPCODE; 8998 break; 8999 9000 case CPRIMOD_CPRI_ROE_HEADER_FIELD_UNMAPPED: 9001 default: 9002 cprif_drv_field = CPRIF_ENCAP_HEADER_FIELD_ID_UNMAPPED; 9003 break; 9004 } 9005 return cprif_drv_field; 9006 } 9007 9008 cprimod_cpri_roe_header_field_t _cprif_drv_to_cprimod_roe_header_field(uint32 cprif_drv_field) 9009 { 9010 cprimod_cpri_roe_header_field_t cprimod_field; 9011 9012 switch (cprif_drv_field) { 9013 case CPRIF_ENCAP_HEADER_FIELD_ID_SUBTYPE: 9014 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE; 9015 break; 9016 9017 case CPRIF_ENCAP_HEADER_FIELD_ID_FLOW_ID: 9018 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID; 9019 break; 9020 9021 case CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_15_8: 9022 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8; 9023 break; 9024 9025 case CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_7_0: 9026 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0; 9027 break; 9028 9029 case CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_31_24: 9030 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24; 9031 break; 9032 9033 case CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_23_16: 9034 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16; 9035 break; 9036 9037 case CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_15_8: 9038 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8; 9039 break; 9040 9041 case CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_7_0: 9042 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0; 9043 break; 9044 9045 case CPRIF_ENCAP_HEADER_FIELD_ID_OPCODE: 9046 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_OPCODE; 9047 break; 9048 9049 case CPRIF_ENCAP_HEADER_FIELD_ID_UNMAPPED: 9050 default: 9051 cprimod_field = CPRIMOD_CPRI_ROE_HEADER_FIELD_UNMAPPED; 9052 break; 9053 } 9054 return cprimod_field; 9055 9056 } 9057 9058 uint32 _cprimod_to_cprif_drv_ecpri_header_field(cprimod_cpri_ecpri_header_field_t cprimod_field) 9059 { 9060 uint32 cprif_drv_field; 9061 9062 switch (cprimod_field) { 9063 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_0: 9064 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_0; 9065 break; 9066 9067 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1: 9068 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_1; 9069 break; 9070 9071 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2: 9072 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_2; 9073 break; 9074 9075 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3: 9076 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_3; 9077 break; 9078 9079 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_4: 9080 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_4; 9081 break; 9082 9083 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_5: 9084 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_5; 9085 break; 9086 9087 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_6: 9088 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_6; 9089 break; 9090 9091 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_7: 9092 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_7; 9093 break; 9094 9095 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_8: 9096 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_8; 9097 break; 9098 9099 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_9: 9100 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_9; 9101 break; 9102 9103 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_10: 9104 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_10; 9105 break; 9106 9107 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_11: 9108 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_11; 9109 break; 9110 9111 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0: 9112 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_VLAN_0_BYTE_0; 9113 break; 9114 9115 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1: 9116 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_VLAN_0_BYTE_1; 9117 break; 9118 9119 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0: 9120 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_VLAN_1_BYTE_0; 9121 break; 9122 9123 case CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1: 9124 cprif_drv_field = CPRIF_DECAP_HEADER_FIELD_ID_VLAN_1_BYTE_1; 9125 break; 9126 default: 9127 cprif_drv_field = 0x9; 9128 } 9129 9130 return cprif_drv_field; 9131 9132 } 9133 9134 cprimod_cpri_ecpri_header_field_t _cprif_drv_to_cprimod_ecpri_header_field(uint32 cprif_drv_field) 9135 { 9136 cprimod_cpri_ecpri_header_field_t cprimod_field; 9137 switch (cprif_drv_field) { 9138 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_0: 9139 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_0; 9140 break; 9141 9142 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_1: 9143 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9144 break; 9145 9146 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_2: 9147 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9148 break; 9149 9150 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_3: 9151 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9152 break; 9153 9154 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_4: 9155 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9156 break; 9157 9158 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_5: 9159 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9160 break; 9161 9162 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_6: 9163 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9164 break; 9165 9166 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_7: 9167 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9168 break; 9169 9170 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_8: 9171 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9172 break; 9173 9174 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_9: 9175 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9176 break; 9177 9178 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_10: 9179 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9180 break; 9181 9182 case CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_11: 9183 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1; 9184 break; 9185 9186 case CPRIF_DECAP_HEADER_FIELD_ID_VLAN_0_BYTE_0: 9187 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0; 9188 break; 9189 9190 case CPRIF_DECAP_HEADER_FIELD_ID_VLAN_0_BYTE_1: 9191 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1; 9192 break; 9193 9194 case CPRIF_DECAP_HEADER_FIELD_ID_VLAN_1_BYTE_0: 9195 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0; 9196 break; 9197 9198 case CPRIF_DECAP_HEADER_FIELD_ID_VLAN_1_BYTE_1: 9199 cprimod_field = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1; 9200 break; 9201 default: 9202 cprimod_field = 0x9; 9203 } 9204 9205 return cprimod_field; 9206 9207 } 9208 9209 int cprif_cpri_encap_header_field_mapping_set(int unit, int port, const cprimod_cpri_encap_header_field_mapping_t* config_mapping) 9210 { 9211 cprif_drv_encap_hdr_field_mapping_t drv_mapping; 9212 SOC_INIT_FUNC_DEFS; 9213 9214 drv_mapping.hdr_byte0_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte0_sel); 9215 drv_mapping.hdr_byte1_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte1_sel); 9216 drv_mapping.hdr_byte2_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte2_sel); 9217 drv_mapping.hdr_byte3_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte3_sel); 9218 drv_mapping.hdr_byte4_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte4_sel); 9219 drv_mapping.hdr_byte5_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte5_sel); 9220 drv_mapping.hdr_byte6_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte6_sel); 9221 drv_mapping.hdr_byte7_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte7_sel); 9222 drv_mapping.hdr_byte8_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte8_sel); 9223 drv_mapping.hdr_byte9_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte9_sel); 9224 drv_mapping.hdr_byte10_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte10_sel); 9225 drv_mapping.hdr_byte11_sel = _cprimod_to_cprif_drv_roe_header_field(config_mapping->hdr_byte11_sel); 9226 9227 _SOC_IF_ERR_EXIT 9228 (cprif_drv_encap_header_field_mapping_set(unit, port, &drv_mapping)); 9229 9230 9231 exit: 9232 SOC_FUNC_RETURN; 9233 9234 } 9235 9236 int cprif_cpri_encap_header_field_mapping_get(int unit, int port, cprimod_cpri_encap_header_field_mapping_t* config_mapping) 9237 { 9238 cprif_drv_encap_hdr_field_mapping_t drv_mapping; 9239 SOC_INIT_FUNC_DEFS; 9240 9241 _SOC_IF_ERR_EXIT 9242 (cprif_drv_encap_header_field_mapping_get(unit, port, &drv_mapping)); 9243 9244 config_mapping->hdr_byte0_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte0_sel); 9245 config_mapping->hdr_byte1_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte1_sel); 9246 config_mapping->hdr_byte2_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte2_sel); 9247 config_mapping->hdr_byte3_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte3_sel); 9248 config_mapping->hdr_byte4_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte4_sel); 9249 config_mapping->hdr_byte5_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte5_sel); 9250 config_mapping->hdr_byte6_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte6_sel); 9251 config_mapping->hdr_byte7_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte7_sel); 9252 config_mapping->hdr_byte8_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte8_sel); 9253 config_mapping->hdr_byte9_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte9_sel); 9254 config_mapping->hdr_byte10_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte10_sel); 9255 config_mapping->hdr_byte11_sel = _cprif_drv_to_cprimod_roe_header_field(drv_mapping.hdr_byte11_sel); 9256 9257 exit: 9258 SOC_FUNC_RETURN; 9259 9260 } 9261 9262 9263 int cprif_cpri_decap_header_field_mapping_set(int unit, int port, const cprimod_cpri_decap_header_field_mapping_t* config_mapping) 9264 { 9265 cprif_drv_decap_hdr_field_mapping_t drv_mapping; 9266 SOC_INIT_FUNC_DEFS; 9267 9268 drv_mapping.subtype = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->subtype_sel); 9269 drv_mapping.flowid = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->flowid_sel); 9270 drv_mapping.length_15_8 = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->length_15_8_sel ); 9271 drv_mapping.length_7_0 = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->length_7_0_sel); 9272 drv_mapping.orderinginfo_31_24 = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->orderinginfo_31_24_sel); 9273 drv_mapping.orderinginfo_23_16 = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->orderinginfo_23_16_sel ); 9274 drv_mapping.orderinginfo_15_8 = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->orderinginfo_15_8_sel); 9275 drv_mapping.orderinginfo_7_0 = _cprimod_to_cprif_drv_ecpri_header_field(config_mapping->orderinginfo_7_0_sel); 9276 9277 _SOC_IF_ERR_EXIT 9278 (cprif_drv_decap_header_field_mapping_set(unit, port, &drv_mapping)); 9279 9280 exit: 9281 SOC_FUNC_RETURN; 9282 9283 } 9284 9285 int cprif_cpri_decap_header_field_mapping_get(int unit, int port, cprimod_cpri_decap_header_field_mapping_t* config_mapping) 9286 { 9287 cprif_drv_decap_hdr_field_mapping_t drv_mapping; 9288 SOC_INIT_FUNC_DEFS; 9289 9290 _SOC_IF_ERR_EXIT 9291 (cprif_drv_decap_header_field_mapping_get(unit, port, &drv_mapping)); 9292 9293 config_mapping->subtype_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.subtype) ; 9294 config_mapping->flowid_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.flowid) ; 9295 config_mapping->length_15_8_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.length_15_8); 9296 config_mapping->length_7_0_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.length_7_0) ; 9297 config_mapping->orderinginfo_31_24_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.orderinginfo_31_24) ; 9298 config_mapping->orderinginfo_23_16_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.orderinginfo_23_16); 9299 config_mapping->orderinginfo_15_8_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.orderinginfo_15_8) ; 9300 config_mapping->orderinginfo_7_0_sel = _cprif_drv_to_cprimod_ecpri_header_field(drv_mapping.orderinginfo_7_0) ; 9301 9302 exit: 9303 SOC_FUNC_RETURN; 9304 } 9305 9306 int cprif_cpri_decap_header_field_mask_set(int unit, int port, cprimod_cpri_roe_header_field_t field_id, uint32 mask ) 9307 { 9308 cprif_drv_decap_hdr_field_mapping_t mask_config; 9309 SOC_INIT_FUNC_DEFS; 9310 9311 _SOC_IF_ERR_EXIT 9312 (cprif_drv_decap_header_field_mask_get(unit, port, &mask_config)); 9313 9314 switch (field_id) { 9315 9316 case CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE: 9317 mask_config.subtype = mask; 9318 break; 9319 9320 case CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID: 9321 mask_config.flowid = mask; 9322 break; 9323 9324 case CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8: 9325 mask_config.length_15_8 = mask; 9326 break; 9327 9328 case CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0: 9329 mask_config.length_7_0 = mask; 9330 break; 9331 9332 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24: 9333 mask_config.orderinginfo_31_24 = mask; 9334 break; 9335 9336 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16: 9337 mask_config.orderinginfo_23_16 = mask; 9338 break; 9339 9340 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8: 9341 mask_config.orderinginfo_15_8 = mask; 9342 break; 9343 9344 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0: 9345 mask_config.orderinginfo_7_0 = mask; 9346 break; 9347 default: 9348 break; 9349 } 9350 9351 _SOC_IF_ERR_EXIT 9352 (cprif_drv_decap_header_field_mask_set(unit, port, &mask_config)); 9353 exit: 9354 SOC_FUNC_RETURN; 9355 } 9356 9357 int cprif_cpri_decap_header_field_mask_get(int unit, int port, cprimod_cpri_roe_header_field_t field_id, uint32* mask ) 9358 { 9359 cprif_drv_decap_hdr_field_mapping_t mask_config; 9360 SOC_INIT_FUNC_DEFS; 9361 9362 _SOC_IF_ERR_EXIT 9363 (cprif_drv_decap_header_field_mask_get(unit, port, &mask_config)); 9364 9365 switch (field_id) { 9366 9367 case CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE: 9368 *mask = mask_config.subtype; 9369 break; 9370 9371 case CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID: 9372 *mask = mask_config.flowid; 9373 break; 9374 9375 case CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8: 9376 *mask = mask_config.length_15_8; 9377 break; 9378 9379 case CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0: 9380 *mask = mask_config.length_7_0; 9381 break; 9382 9383 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24: 9384 *mask = mask_config.orderinginfo_31_24; 9385 break; 9386 9387 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16: 9388 *mask = mask_config.orderinginfo_23_16; 9389 break; 9390 9391 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8: 9392 *mask = mask_config.orderinginfo_15_8; 9393 break; 9394 9395 case CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0: 9396 *mask = mask_config.orderinginfo_7_0; 9397 break; 9398 default: 9399 break; 9400 } 9401 exit: 9402 SOC_FUNC_RETURN; 9403 } 9404 9405 int cprif_cpri_header_field_adjustment_config_set (int unit, int port, 9406 cprimod_direction_t dir, 9407 int ext_hdr_enable, 9408 int len_field_adj) 9409 { 9410 SOC_INIT_FUNC_DEFS; 9411 9412 _SOC_IF_ERR_EXIT 9413 (cprif_drv_length_field_adjustment_set(unit, port, dir, len_field_adj)); 9414 9415 _SOC_IF_ERR_EXIT 9416 (cprif_drv_extended_header_enable_set(unit, port, dir, ext_hdr_enable)); 9417 9418 exit: 9419 SOC_FUNC_RETURN; 9420 } 9421 9422 int cprif_cpri_header_field_adjustment_config_get( int unit, int port, 9423 cprimod_direction_t dir, 9424 int* ext_hdr_enable, 9425 int* len_field_adj) 9426 { 9427 SOC_INIT_FUNC_DEFS; 9428 9429 _SOC_IF_ERR_EXIT 9430 (cprif_drv_length_field_adjustment_get(unit, port, dir, len_field_adj)); 9431 9432 _SOC_IF_ERR_EXIT 9433 (cprif_drv_extended_header_enable_get(unit, port, dir, ext_hdr_enable)); 9434 9435 exit: 9436 SOC_FUNC_RETURN; 9437 } 9438 9439 int cprif_cpri_port_compression_saturation_config_set(int unit, int port, uint32 threshold_value) 9440 { 9441 SOC_INIT_FUNC_DEFS; 9442 9443 _SOC_IF_ERR_EXIT 9444 (cprif_drv_compression_negative_saturation_threshold_set(unit, port, threshold_value)); 9445 exit: 9446 SOC_FUNC_RETURN; 9447 9448 } 9449 9450 int cprif_cpri_port_compression_saturation_config_get(int unit, int port, uint32* threshold_value) 9451 { 9452 SOC_INIT_FUNC_DEFS; 9453 9454 _SOC_IF_ERR_EXIT 9455 (cprif_drv_compression_negative_saturation_threshold_get(unit, port, threshold_value)); 9456 exit: 9457 SOC_FUNC_RETURN; 9458 9459 } 9460 9461 int cprif_cpri_port_decompression_saturation_config_set(int unit, int port, uint32 sat_value) 9462 { 9463 SOC_INIT_FUNC_DEFS; 9464 9465 _SOC_IF_ERR_EXIT 9466 (cprif_drv_decompression_negative_saturation_value_set(unit, port, sat_value)); 9467 exit: 9468 SOC_FUNC_RETURN; 9469 9470 } 9471 9472 int cprif_cpri_port_decompression_saturation_config_get(int unit, int port, uint32* sat_value) 9473 { 9474 SOC_INIT_FUNC_DEFS; 9475 9476 _SOC_IF_ERR_EXIT 9477 (cprif_drv_decompression_negative_saturation_value_get(unit, port, sat_value)); 9478 exit: 9479 SOC_FUNC_RETURN; 9480 9481 } 9482 9483 int cprif_rsvd4_tx_padding_size_set(int unit, int port, uint32 padding_size) 9484 { 9485 SOC_INIT_FUNC_DEFS; 9486 9487 _SOC_IF_ERR_EXIT 9488 (cprif_drv_rsvd4_tx_padding_size_set(unit, port, padding_size)); 9489 exit: 9490 SOC_FUNC_RETURN; 9491 9492 } 9493 9494 int cprif_rsvd4_tx_padding_size_get(int unit, int port, uint32* padding_size) 9495 { 9496 SOC_INIT_FUNC_DEFS; 9497 9498 _SOC_IF_ERR_EXIT 9499 (cprif_drv_rsvd4_tx_padding_size_get(unit, port, padding_size)); 9500 9501 exit: 9502 SOC_FUNC_RETURN; 9503 9504 } 9505 9506 #endif /* CPRIMOD_CPRI_FALCON_SUPPORT */ 9507 9508 #undef _ERR_MSG_MODULE_NAME