uc_dbg.c (19665B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: ukernel_debug.c 8 * Purpose: 9 */ 10 11 #include <stddef.h> /* for offsetof */ 12 13 #include <sal/core/boot.h> 14 #include <sal/core/libc.h> 15 #include <shared/alloc.h> 16 17 #include <soc/drv.h> 18 #if 0 19 #include <soc/dcb.h> 20 #include <soc/dcbformats.h> /* only for 5670 crc erratum warning */ 21 #include <soc/pbsmh.h> 22 #include <soc/higig.h> 23 #include <soc/cm.h> 24 #include <soc/property.h> 25 #endif 26 #include <soc/debug.h> 27 #include <soc/error.h> 28 #include <shared/bsl.h> 29 30 #if defined(SOC_UKERNEL_DEBUG) 31 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_IPROC_SUPPORT) 32 33 #include <soc/cmicm.h> 34 #include <soc/shared/mos_intr_common.h> 35 #include <soc/uc_msg.h> 36 #include <soc/uc.h> 37 38 #include <soc/uc_dbg.h> 39 40 _soc_cmic_ucdbg_stats_t cmic_uc_dbg_stat[SOC_MAX_NUM_DEVICES]; 41 int cmic_ucdbg_initialized[SOC_MAX_NUM_DEVICES] = {0}; 42 43 mos_msg_cmic_ucdbg_t ucdbg_stat; 44 45 #define UCDBG_HOSTLOG_HDR_VALID(pstat, indx)\ 46 (pstat)->hostlog[(indx)].hdr.h.valid 47 48 #define UCBDG_HOSTLOG_BUFF(pstat, indx)\ 49 (pstat)->hostlog[(indx)].log 50 51 #define UCBDG_CMICM_ADDR(base, field) \ 52 ((uint32) ((base) + offsetof(mos_msg_cmic_ucdbg_t,field))) 53 54 #define UCBDG_CMICM_HDR_WORD_ADDR(base, indx) \ 55 ((uint32) ((base) + offsetof(mos_msg_cmic_ucdbg_t,hdr.word[(indx)]))) 56 57 STATIC 58 char *mos_msg_ucdbg_mod_state[] = { 59 "_bcmUcDbgUcUnInitialized", 60 "_bcmUcDbgUcSP408InitComplete", 61 "_bcmUcDbgUcUARTInitComplete", 62 "_bcmUcDbgUcCmicIRQInitComplete", 63 "_bcmUcDbgUcTimesyncIRQInitComplete", 64 "_bcmUcDbgUcMosDMAInitComplete", 65 "_bcmUcDbgUcPKTDMAInitComplete", 66 "_bcmUcDbgUcSBUSDMAInitComplete", 67 "_bcmUcDbgUcMoSMsgInitStarted", 68 "_bcmUcDbgUcBoardInitComplete", 69 "_bcmUcDbgUcWaitingForHostSync", 70 "_bcmUcDbgUcRunning", 71 "_bcmUcDbgUcDMAFail", 72 "_bcmUcDbgHostInitialized", 73 "_bcmUcDbgHostRunning", 74 }; 75 76 77 /* array of pointers to log buffer entry */ 78 mos_msg_ucdbg_entry_t **puclog_buffarray = NULL; 79 80 /* These are addresses in the uC SRAM and not directly addresable by SDK 81 - they are addresses for PCI Operatins */ 82 STATIC uint32 83 _soc_cmic_ucdebug_shared_sram_base(int unit) 84 { 85 uint32 ucdbg_msg_base = 0; 86 87 ucdbg_msg_base = soc_cmic_timestamp_base(unit) + sizeof(mos_msg_timestamps_t); 88 return (ucdbg_msg_base); 89 } 90 91 STATIC void 92 _soc_cmic_ucdebug_dump_sram_info(int unit) 93 { 94 uint32 ucdbg_msg_base = 0, tmp = 0, tmp1 = 0; 95 uint32 debug[12]; 96 97 ucdbg_msg_base = _soc_cmic_ucdebug_shared_sram_base(unit); 98 99 tmp = soc_uc_mem_read(unit, UCBDG_CMICM_ADDR(ucdbg_msg_base, puclog_buff)); 100 tmp1= soc_ntohl(tmp); 101 bsl_printf("%s Got puclog_buff: %08x \n", __FUNCTION__, tmp1); 102 103 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (0 * 4))); 104 debug[0]= soc_ntohl(tmp); 105 bsl_printf("debug[0]: %08x \n", debug[0]); 106 107 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (1 * 4))); 108 debug[1]= soc_ntohl(tmp); 109 bsl_printf("debug[1]: %08x \n", debug[1]); 110 111 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (2 * 4))); 112 debug[2]= soc_ntohl(tmp); 113 bsl_printf("debug[2]: %08x \n", debug[2]); 114 115 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (3 * 4))); 116 debug[3] = soc_ntohl(tmp); 117 bsl_printf("debug[3]: %08x \n", debug[3]); 118 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (4 * 4))); 119 debug[4] = soc_ntohl(tmp); 120 bsl_printf("debug[4]: %08x \n", debug[4]); 121 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (5 * 4))); 122 debug[5] = soc_ntohl(tmp); 123 bsl_printf("debug[5]: %08x \n", debug[5]); 124 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (6 * 4))); 125 debug[6] = soc_ntohl(tmp); 126 bsl_printf("debug[6]: %08x \n", debug[6]); 127 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (7 * 4))); 128 debug[7] = soc_ntohl(tmp); 129 bsl_printf("debug[7]: %08x \n", debug[7]); 130 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (8 * 4))); 131 debug[8] = soc_ntohl(tmp); 132 bsl_printf("debug[8]: %08x \n", debug[8]); 133 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (9 * 4))); 134 debug[9] = soc_ntohl(tmp); 135 bsl_printf("debug[9]: %08x \n", debug[9]); 136 137 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (10 * 4))); 138 debug[10] = soc_ntohl(tmp); 139 bsl_printf("debug[10]: %08x \n", debug[10]); 140 141 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (11 * 4))); 142 debug[11] = soc_ntohl(tmp); 143 bsl_printf("debug[11]: %08x \n", debug[11]); 144 } 145 146 STATIC int 147 _soc_cmic_ucdebug_allocate_shared_memory(int unit) 148 { 149 int logbuffarray_size = 0; 150 uint32 ucdbg_msg_base = 0, tmp = 0; 151 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 152 mos_msg_cmic_ucdbg_t *pucdbg_cache = NULL; 153 154 pucdbg_cache = &phostdbg_stat->ucdbg_cache; 155 156 /* ukernel log entries are given as a array of pointers to UC 157 * mostly following the following contruct : 158 * mos_msg_ucdbg_entry_t *uclog[MOS_UCDBG_MAX_LOG_ENTRIES_UC] 159 */ 160 161 logbuffarray_size = sizeof(mos_msg_ucdbg_entry_t*) * 162 MOS_UCDBG_MAX_LOG_ENTRIES_UC; 163 164 puclog_buffarray = soc_cm_salloc(unit, logbuffarray_size, 165 "uC log ent ptrs"); 166 if (puclog_buffarray == NULL) { 167 bsl_printf("%s(): Error in allocating dmable buff for UC log ..\n", 168 FUNCTION_NAME()); 169 return (0); 170 } 171 172 for (tmp=0; tmp < MOS_UCDBG_MAX_LOG_ENTRIES_UC; tmp++) { 173 174 /* keeping host side ptr cache of uc log buffers */ 175 phostdbg_stat->puclog[tmp] = soc_cm_salloc(unit, 176 sizeof(mos_msg_ucdbg_entry_t), "uc log ent"); 177 if (phostdbg_stat->puclog[tmp] == NULL) { 178 bsl_printf("dmable memory allocation failure for uclog indx:%d \n", 179 tmp); 180 goto exit; 181 } 182 183 memset((void*)phostdbg_stat->puclog[tmp], 0x0, 184 sizeof(mos_msg_ucdbg_entry_t)); 185 soc_cm_sflush(unit, phostdbg_stat->puclog[tmp], 186 sizeof(mos_msg_ucdbg_entry_t)); 187 soc_cm_sinval(unit, phostdbg_stat->puclog[tmp], 188 sizeof(mos_msg_ucdbg_entry_t)); 189 puclog_buffarray[tmp] = (mos_msg_ucdbg_entry_t *)INT_TO_PTR(soc_htonl(soc_cm_l2p(unit, phostdbg_stat->puclog[tmp]))); 190 } 191 192 soc_cm_sflush(unit, puclog_buffarray, logbuffarray_size); 193 soc_cm_sinval(unit, puclog_buffarray, logbuffarray_size); 194 195 pucdbg_cache->puclog_buff = puclog_buffarray; 196 197 /* Putting the array of log buffers location (puclog_buffarray) 198 * to shared memory uC SRAM 199 */ 200 ucdbg_msg_base = _soc_cmic_ucdebug_shared_sram_base(unit); 201 soc_uc_mem_write(unit, UCBDG_CMICM_ADDR(ucdbg_msg_base, puclog_buff), 202 soc_htonl(soc_cm_l2p(unit, puclog_buffarray))); 203 204 exit: 205 206 return (0); 207 208 } 209 210 STATIC void 211 _soc_cmic_ucdebug_thread(void *unit_vp) 212 { 213 int unit = PTR_TO_INT(unit_vp); 214 uint32 ucdbg_msg_base = 0, tmp = 0; 215 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 216 mos_msg_cmic_ucdbg_t *pucdbg_cache = NULL; 217 218 pucdbg_cache = &phostdbg_stat->ucdbg_cache; 219 ucdbg_msg_base = _soc_cmic_ucdebug_shared_sram_base(unit); 220 221 while (1) { 222 223 tmp = soc_uc_mem_read(unit, 224 UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, UCDBG_OFFSET_STATE_UC)); 225 pucdbg_cache->hdr.s.state_uc = soc_ntohl(tmp); 226 227 if(pucdbg_cache->hdr.s.state_uc == _bcmUcDbgUcWaitingForHostSync) { 228 229 _soc_cmic_ucdebug_allocate_shared_memory(unit); 230 231 pucdbg_cache->hdr.s.capture_mode = _bcmUcDbgLogCaptureFreerun; 232 pucdbg_cache->hdr.s.state_host = _bcmUcDbgHostRunning; 233 234 235 /* ucdbg_msg_base in uC SRAM - not directly addressable by SDK, 236 * needs to be accessed via PCI operations 237 */ 238 ucdbg_msg_base = _soc_cmic_ucdebug_shared_sram_base(unit); 239 240 /* by defualt capture mode is _bcmUcDbgLogCaptureFreerun */ 241 soc_uc_mem_write(unit, 242 UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, UCDBG_OFFSET_CAPTURE_MODE), 243 (uint32)soc_htonl(pucdbg_cache->hdr.s.capture_mode)); 244 245 /* setting the host state tp _bcmUcDbgHostRunning */ 246 soc_uc_mem_write(unit, 247 UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, UCBDG_OFFSET_STATE_HOST), 248 (uint32)soc_htonl(pucdbg_cache->hdr.s.state_host)); 249 250 /* for now closing the thread since memory init is complete */ 251 break; 252 253 } 254 #if 0 255 else { 256 _soc_cmic_ucdebug_dump_sram_info(unit); 257 } 258 #endif 259 260 /* sleeping for sometime*/ 261 sal_sleep(10); 262 263 } 264 /* ukernel debug thread closing */ 265 } 266 267 int 268 soc_cmic_ucdebug_init(int unit, int uC) 269 { 270 uint32 ucdbg_msg_base = 0; 271 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 272 mos_msg_cmic_ucdbg_t *pucdbg_cache = NULL; 273 274 if(!soc_feature(unit, soc_feature_ukernel_debug)) { 275 return (SOC_E_UNAVAIL); 276 } 277 278 if (uC != 1) { 279 return (SOC_E_NONE); 280 } 281 282 283 pucdbg_cache = &phostdbg_stat->ucdbg_cache; 284 285 /* host side memory initialization */ 286 287 phostdbg_stat->flags = 0; 288 phostdbg_stat->sw_intr_count_uc0 = 0; 289 phostdbg_stat->sw_intr_count_uc1 = 0; 290 phostdbg_stat->hostlog_indx_wr = 0; 291 phostdbg_stat->hostlog_indx_rd = 0; 292 293 /* ukernel side data structure initialization */ 294 memset(pucdbg_cache, 0x0, sizeof(mos_msg_cmic_ucdbg_t)); 295 296 /* host side uC sRAM needs to be reinited after uC starts running */ 297 /* setting it to 0 instead of init since uc init sets SRAM to zero */ 298 pucdbg_cache->hdr.s.state_host = 0; 299 pucdbg_cache->hdr.s.rdindx = 0; 300 pucdbg_cache->hdr.s.filter_mask = 0; 301 pucdbg_cache->hdr.s.state_uc = _bcmUcDbgUcUnInitialized; 302 pucdbg_cache->hdr.s.capture_mode = _bcmUcDbgLogCaptureFreerun; 303 304 305 /* ucdbg_msg_base in uC SRAM - not directly addressable by SDK, needs to be 306 accessed via PCI operations */ 307 ucdbg_msg_base = _soc_cmic_ucdebug_shared_sram_base(unit); 308 309 soc_uc_mem_write(unit, UCBDG_CMICM_ADDR(ucdbg_msg_base, puclog_buff), 0); 310 311 soc_uc_mem_write(unit, 312 UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, UCBDG_OFFSET_STATE_HOST), 313 (uint32)soc_htonl(pucdbg_cache->hdr.s.state_host)); 314 soc_uc_mem_write(unit, 315 UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, UCDBG_OFFSET_STATE_UC), 316 (uint32)soc_htonl(pucdbg_cache->hdr.s.state_uc)); 317 318 soc_uc_mem_write(unit, UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, 2), 0); 319 soc_uc_mem_write(unit, UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, 3), 0); 320 soc_uc_mem_write(unit, UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, 4), 0); 321 soc_uc_mem_write(unit, UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, 5), 0); 322 soc_uc_mem_write(unit, UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, 6), 0); 323 soc_uc_mem_write(unit, UCBDG_CMICM_HDR_WORD_ADDR(ucdbg_msg_base, 7), 0); 324 325 if (cmic_ucdbg_initialized[unit]) { 326 bsl_printf("UKENREL DBG module already initlaized\n"); 327 return (SOC_E_NONE); 328 } 329 330 /* create uc initialization monitoring thread */ 331 sal_thread_create("cmic uc dbg thrd", SAL_THREAD_STKSZ, 150, 332 _soc_cmic_ucdebug_thread, INT_TO_PTR(unit)); 333 334 cmic_ucdbg_initialized[unit] = 1; 335 336 return (SOC_E_NONE); 337 } 338 339 void 340 soc_cmic_ucdebug_deinit(int unit) 341 { 342 if(!soc_feature(unit, soc_feature_ukernel_debug)) { 343 return; 344 } 345 } 346 347 int 348 soc_cmic_ucdebug_log_add(int unit, mos_msg_ucdbg_logtype_t logtype, 349 const char *format, ...) 350 { 351 va_list vargs; 352 char *buff = NULL; 353 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 354 int bufflen = 0; 355 356 if(!soc_feature(unit, soc_feature_ukernel_debug)) { 357 return (SOC_E_UNAVAIL); 358 } 359 if (!cmic_ucdbg_initialized[unit]) { 360 return (SOC_E_INIT); 361 } 362 363 364 buff = UCBDG_HOSTLOG_BUFF(phostdbg_stat, phostdbg_stat->hostlog_indx_wr); 365 366 memset(buff, 0x0, MOS_UCDBG_LOG_BUFF_SIZE); 367 368 switch(logtype) { 369 case _bcmCmicUcDbgLogHostMcsLoad: 370 sal_sprintf(buff, "%s" , "HostMcsLoad: "); 371 break; 372 case _bcmCmicUcDbgLogHostUcMsg: 373 sal_sprintf(buff, "%s", "HostUcMsg : "); 374 break; 375 case _bcmCmicUcDbgLogHostPtpRx: 376 sal_sprintf(buff, "%s", "HostPtpRx : "); 377 break; 378 case _bcmCmicUcDbgLogHostPtp: 379 sal_sprintf(buff, "%s", "HostPtp : "); 380 break; 381 default: 382 sal_sprintf(buff, "%s", "Host : "); 383 } 384 385 bufflen = sal_strlen(buff); 386 387 388 va_start(vargs, format); 389 sal_vsnprintf(buff + bufflen, (MOS_UCDBG_LOG_BUFF_SIZE - bufflen), format, vargs); 390 va_end(vargs); 391 392 phostdbg_stat->hostlog_indx_wr = 393 (phostdbg_stat->hostlog_indx_wr + 1) % MOS_UCDBG_MAX_LOG_ENTRIES_HOST; 394 395 return (SOC_E_NONE); 396 397 } 398 399 int 400 soc_cmic_ucdebug_sw_intr_count_inc(int unit, uint32 rupt_num) 401 { 402 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 403 404 if(!soc_feature(unit, soc_feature_ukernel_debug)) { 405 return (SOC_E_UNAVAIL); 406 } 407 if (!cmic_ucdbg_initialized[unit]) { 408 return (SOC_E_INIT); 409 } 410 411 412 switch(rupt_num) { 413 case CMICM_SW_INTR_UC0: 414 phostdbg_stat->sw_intr_count_uc0++; 415 break; 416 case CMICM_SW_INTR_UC1: 417 phostdbg_stat->sw_intr_count_uc1++; 418 break; 419 default: 420 break; 421 } 422 return (SOC_E_NONE); 423 } 424 425 int 426 soc_cmic_ucdebug_core_communication_status(int unit, unsigned int flag) 427 { 428 if (!cmic_ucdbg_initialized[unit]) { 429 return (SOC_E_INIT); 430 } 431 432 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 433 phostdbg_stat->flags |= flag; 434 435 return (SOC_E_INIT); 436 } 437 438 STATIC void 439 _soc_cmic_ucddebug_output_show(void* owner, void* time_as_ptr, void *unit_as_ptr, 440 void *unused_2, void* unused_3) 441 { 442 sal_usecs_t callback_time = (sal_usecs_t)(size_t)time_as_ptr; 443 int unit = (int)(size_t)unit_as_ptr; 444 int tmp = 0; 445 mos_msg_cmic_ucdbg_t *pucdbg_cache =NULL; 446 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 447 uint32 ucdbg_msg_base = 0; 448 449 ucdbg_msg_base = _soc_cmic_ucdebug_shared_sram_base(unit); 450 pucdbg_cache = &phostdbg_stat->ucdbg_cache; 451 452 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (UCDBG_OFFSET_STATE_UC * 4))); 453 if (pucdbg_cache->hdr.s.state_uc != soc_ntohl(tmp)) { 454 pucdbg_cache->hdr.s.state_uc = soc_ntohl(tmp); 455 bsl_printf("Ukernel State : %s\n", 456 (pucdbg_cache->hdr.s.state_uc >= _bcmUcDbgMaxState) 457 ? "Unknown State" : mos_msg_ucdbg_mod_state[pucdbg_cache->hdr.s.state_uc]); 458 } 459 460 /* SDK side log output */ 461 for (tmp = phostdbg_stat->hostlog_indx_rd; tmp < phostdbg_stat->hostlog_indx_wr; tmp++) { 462 bsl_printf("%s", phostdbg_stat->hostlog[tmp].log); 463 phostdbg_stat->hostlog_indx_rd++; 464 } 465 466 /* UKERNEL side log output */ 467 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (UCDBG_OFFSET_WR_INDX * 4))); 468 pucdbg_cache->hdr.s.wrindx = soc_ntohl(tmp); 469 for (tmp = pucdbg_cache->hdr.s.rdindx; tmp < pucdbg_cache->hdr.s.wrindx; tmp++) { 470 if (phostdbg_stat->puclog[tmp] != NULL) { 471 soc_cm_sinval(unit, phostdbg_stat->puclog[tmp], sizeof(mos_msg_ucdbg_entry_t)); 472 bsl_printf("%s", phostdbg_stat->puclog[tmp]->log); 473 } 474 else { 475 bsl_printf("phostdbg_stat->uclog[tmp] is NULL\n"); 476 } 477 pucdbg_cache->hdr.s.rdindx++; 478 } 479 if (callback_time) { 480 sal_dpc_time(callback_time, &_soc_cmic_ucddebug_output_show, 481 INT_TO_PTR(&_soc_cmic_ucddebug_output_show), time_as_ptr, 482 unit_as_ptr, 0, 0); 483 } 484 485 } 486 487 int 488 soc_cmic_ucdebug_dump_start(int unit) 489 { 490 sal_usecs_t callback_time = CMIC_UCDEBUG_OUTPUT_DISP_TIMEOUT; 491 492 if(!soc_feature(unit, soc_feature_ukernel_debug)) { 493 return (SOC_E_UNAVAIL); 494 } 495 if (!cmic_ucdbg_initialized[unit]) { 496 return (SOC_E_FAIL); 497 } 498 sal_dpc_cancel(INT_TO_PTR(&_soc_cmic_ucddebug_output_show)); 499 500 _soc_cmic_ucddebug_output_show(INT_TO_PTR(&_soc_cmic_ucddebug_output_show), 501 INT_TO_PTR(callback_time), INT_TO_PTR(unit), 0, 0); 502 return (SOC_E_NONE); 503 504 } 505 506 int 507 soc_cmic_ucdebug_dump_stop(int unit) 508 { 509 if(!soc_feature(unit, soc_feature_ukernel_debug)) { 510 return (SOC_E_UNAVAIL); 511 } 512 if (!cmic_ucdbg_initialized[unit]) { 513 return (SOC_E_FAIL); 514 } 515 sal_dpc_cancel(INT_TO_PTR(&_soc_cmic_ucddebug_output_show)); 516 return (SOC_E_NONE); 517 } 518 519 int 520 soc_cmic_ucdebug_status(int unit) 521 { 522 _soc_cmic_ucdbg_stats_t *phostdbg_stat = &cmic_uc_dbg_stat[unit]; 523 mos_msg_cmic_ucdbg_t *pucdbg_cache = NULL; 524 uint32 tmp = 0; 525 uint32 ucdbg_msg_base = 0; 526 uint32 host_index = 0, area_in, area_out; 527 528 pucdbg_cache = &phostdbg_stat->ucdbg_cache; 529 530 if(!soc_feature(unit, soc_feature_ukernel_debug)) { 531 return (SOC_E_UNAVAIL); 532 } 533 if (!cmic_ucdbg_initialized[unit]) { 534 return (SOC_E_FAIL); 535 } 536 537 ucdbg_msg_base = _soc_cmic_ucdebug_shared_sram_base(unit); 538 539 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (UCBDG_OFFSET_STATE_HOST * 4))); 540 pucdbg_cache->hdr.s.state_host = soc_ntohl(tmp); 541 542 tmp = soc_uc_mem_read(unit, (ucdbg_msg_base+ (UCDBG_OFFSET_STATE_UC * 4))); 543 pucdbg_cache->hdr.s.state_uc = soc_ntohl(tmp); 544 545 bsl_printf("Host State : %s\n", 546 (pucdbg_cache->hdr.s.state_host >= _bcmUcDbgMaxState) 547 ? "Unknown State" : mos_msg_ucdbg_mod_state[pucdbg_cache->hdr.s.state_host]); 548 bsl_printf("Ukernel State : %s\n", 549 (pucdbg_cache->hdr.s.state_uc >= _bcmUcDbgMaxState) 550 ? "Unknown State" : mos_msg_ucdbg_mod_state[pucdbg_cache->hdr.s.state_uc]); 551 bsl_printf("Software Interrupt Count uc0: %d\n", phostdbg_stat->sw_intr_count_uc0); 552 bsl_printf("Software Interrupt Count uc1: %d\n", phostdbg_stat->sw_intr_count_uc1); 553 554 for (host_index = 0; host_index < (NUM_UCS + 2); host_index++) { 555 tmp = soc_uc_mem_read(unit, (uint32)( 556 UCBDG_CMICM_ADDR(ucdbg_msg_base, msg_host) + 557 host_index * sizeof(mos_msg_ucbdg_msg_area_t))); 558 area_in = soc_ntohl(tmp); 559 tmp = soc_uc_mem_read(unit, (uint32)( 560 UCBDG_CMICM_ADDR(ucdbg_msg_base, msg_host) + 561 (host_index * sizeof(mos_msg_ucbdg_msg_area_t)) 562 + sizeof(uint32))); 563 area_out = soc_ntohl(tmp); 564 bsl_printf("uC1 SRAM host index:%d area_in : 0x%x area_out : 0x%x\n", 565 host_index, area_in, area_out); 566 } 567 568 tmp = soc_uc_mem_read(unit, (uint32)( 569 UCBDG_CMICM_ADDR(ucdbg_msg_base, msg_area_base))); 570 bsl_printf("uc: msg area base : 0x%x\n", 571 soc_ntohl(tmp)); 572 573 bsl_printf("Host: Ukernel debug module base sram : 0x%x\n", 574 ucdbg_msg_base); 575 tmp = soc_uc_mem_read(unit, (uint32)( 576 UCBDG_CMICM_ADDR(ucdbg_msg_base, ucdbg_msg_base))); 577 bsl_printf("UC: uc debug module SRAM msg area base: 0x%x\n", 578 soc_ntohl(tmp)); 579 580 tmp = soc_uc_mem_read(unit, (uint32)( 581 UCBDG_CMICM_ADDR(ucdbg_msg_base, uc_processor_num))); 582 bsl_printf("uC image seen processor number : 0x%x\n", 583 soc_ntohl(tmp)); 584 585 return (SOC_E_NONE); 586 587 } 588 #else 589 int uc_dbg_c_file_not_empty; 590 #endif /* #if defined(BCM_CMICM_SUPPORT) || defined(BCM_IPROC_SUPPORT) */ 591 #endif 592