shmoo_sjc16.c (264414B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * DDR4 Memory Support 8 */ 9 #include <shared/bsl.h> 10 11 #include <sal/core/boot.h> 12 #include <sal/core/libc.h> 13 #include <shared/alloc.h> 14 #include <soc/memtune.h> 15 #include <soc/iproc.h> 16 17 18 #include <soc/drv.h> 19 #include <soc/debug.h> 20 #include <soc/cm.h> 21 #ifdef BCM_CMICM_SUPPORT 22 #include <soc/cmicm.h> 23 #endif 24 25 #ifndef BCM_SJC16_SUPPORT 26 #define BCM_SJC16_SUPPORT 27 #endif 28 29 #ifdef BCM_SJC16_SUPPORT 30 #include <soc/shmoo_sjc16.h> 31 #include <soc/phy/phy_sjc16.h> 32 #include <soc/phy/ydc_ddr_bist.h> 33 #endif 34 35 #ifdef BCM_HELIX5_SUPPORT 36 37 static sjc16_shmoo_dram_info_t shmoo_dram_info = 38 { 39 /*.ctl_type =*/ 0, 40 /*.dram_type =*/ 0, 41 /*.dram_bitmap =*/ 0x00000000, 42 /*.interface_bitwidth =*/ 0, 43 /*.split_bus =*/ 0, 44 /*.num_columns =*/ -1, 45 /*.num_rows =*/ -1, 46 /*.num_banks =*/ -1, 47 /*.num_bank_groups =*/ -1, 48 /*.data_rate_mbps =*/ -1, 49 /*.ref_clk_mhz =*/ -1, 50 /*.refi =*/ 0, 51 /*.command_parity_latency =*/ 0, 52 /*.sim_system_mode =*/ 0 53 }; 54 55 const uint32 shmoo_order_sjc16_ddr4[SHMOO_SJC16_DDR4_ECC_32P4_SEQUENCE_COUNT] = 56 { 57 SHMOO_SJC16_RD_EN_FISH, 58 SHMOO_SJC16_RD_EXTENDED, 59 SHMOO_SJC16_WR_EXTENDED, 60 SHMOO_SJC16_ADDR_CTRL_EXTENDED, 61 SHMOO_SJC16_RD_EN_FISH_ECC, 62 SHMOO_SJC16_RD_EXTENDED_ECC, 63 SHMOO_SJC16_WR_EXTENDED_ECC 64 }; 65 66 uint32 67 _shmoo_sjc16_check_dram(int phy_ndx) 68 { 69 return ((shmoo_dram_info.dram_bitmap >> phy_ndx) & 0x1); 70 } 71 72 STATIC int 73 _initialize_bist(int unit, int phy_ndx, int bit, sjc16_shmoo_container_t *scPtr) 74 { 75 ydc_ddr_bist_info_t bist_info; 76 77 switch ((*scPtr).shmooType) { 78 case SHMOO_SJC16_RD_EN_FISH: 79 bist_info.write_weight = 0; 80 bist_info.read_weight = 1; 81 bist_info.bist_timer_us = 0; 82 bist_info.bist_num_actions = 1; 83 bist_info.bist_start_address = 0x00000000; 84 bist_info.bist_end_address = 0x0FFFFFFF; 85 bist_info.mpr_mode = 0; 86 bist_info.prbs_mode = 0; 87 bist_info.addr_prbs_mode = 0; 88 break; 89 case SHMOO_SJC16_RD_EXTENDED: 90 bist_info.write_weight = 255; 91 bist_info.read_weight = 255; 92 bist_info.bist_timer_us = 0; 93 bist_info.bist_num_actions = 51510; 94 bist_info.bist_start_address = 0x00000000; 95 bist_info.bist_end_address = 0x0FFFFFFF; 96 bist_info.mpr_mode = 0; 97 bist_info.prbs_mode = 1; 98 bist_info.addr_prbs_mode = 0; 99 break; 100 case SHMOO_SJC16_WR_EXTENDED: 101 bist_info.write_weight = 255; 102 bist_info.read_weight = 255; 103 bist_info.bist_timer_us = 0; 104 bist_info.bist_num_actions = 51510; 105 bist_info.bist_start_address = 0x00000000; 106 bist_info.bist_end_address = 0x0FFFFFFF; 107 bist_info.mpr_mode = 0; 108 bist_info.prbs_mode = 1; 109 bist_info.addr_prbs_mode = 0; 110 break; 111 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 112 bist_info.write_weight = 255; 113 bist_info.read_weight = 255; 114 bist_info.bist_timer_us = 0; 115 bist_info.bist_num_actions = 51510; 116 bist_info.bist_start_address = 0x00000000; 117 bist_info.bist_end_address = 0x0FFFFFFF; 118 bist_info.mpr_mode = 0; 119 bist_info.prbs_mode = 1; 120 bist_info.addr_prbs_mode = 0; 121 break; 122 case SHMOO_SJC16_ADDR_EXTENDED: 123 bist_info.write_weight = 255; 124 bist_info.read_weight = 255; 125 bist_info.bist_timer_us = 0; 126 bist_info.bist_num_actions = 51510; 127 bist_info.bist_start_address = 0x00000000; 128 bist_info.bist_end_address = 0x0FFFFFFF; 129 bist_info.mpr_mode = 0; 130 bist_info.prbs_mode = 1; 131 bist_info.addr_prbs_mode = 0; 132 break; 133 case SHMOO_SJC16_CTRL_EXTENDED: 134 bist_info.write_weight = 255; 135 bist_info.read_weight = 255; 136 bist_info.bist_timer_us = 0; 137 bist_info.bist_num_actions = 51510; 138 bist_info.bist_start_address = 0x00000000; 139 bist_info.bist_end_address = 0x0FFFFFFF; 140 bist_info.mpr_mode = 0; 141 bist_info.prbs_mode = 1; 142 bist_info.addr_prbs_mode = 0; 143 break; 144 case SHMOO_SJC16_RD_EN_FISH_ECC: 145 bist_info.write_weight = 0; 146 bist_info.read_weight = 1; 147 bist_info.bist_timer_us = 0; 148 bist_info.bist_num_actions = 1; 149 bist_info.bist_start_address = 0x00000000; 150 bist_info.bist_end_address = 0x0FFFFFFF; 151 bist_info.mpr_mode = 0; 152 bist_info.prbs_mode = 0; 153 bist_info.addr_prbs_mode = 0; 154 break; 155 case SHMOO_SJC16_RD_EXTENDED_ECC: 156 bist_info.write_weight = 255; 157 bist_info.read_weight = 255; 158 bist_info.bist_timer_us = 0; 159 bist_info.bist_num_actions = 51510; 160 bist_info.bist_start_address = 0x00000000; 161 bist_info.bist_end_address = 0x0FFFFFFF; 162 bist_info.mpr_mode = 0; 163 bist_info.prbs_mode = 1; 164 bist_info.addr_prbs_mode = 0; 165 break; 166 case SHMOO_SJC16_WR_EXTENDED_ECC: 167 bist_info.write_weight = 255; 168 bist_info.read_weight = 255; 169 bist_info.bist_timer_us = 0; 170 bist_info.bist_num_actions = 51510; 171 bist_info.bist_start_address = 0x00000000; 172 bist_info.bist_end_address = 0x0FFFFFFF; 173 bist_info.mpr_mode = 0; 174 bist_info.prbs_mode = 1; 175 bist_info.addr_prbs_mode = 0; 176 break; 177 default: 178 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (unsigned int)(*scPtr).shmooType)); 179 return SOC_E_FAIL; 180 } 181 182 return soc_ydc_ddr_bist_config_set(unit, phy_ndx, &bist_info); 183 } 184 185 STATIC int 186 _run_bist(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr, sjc16_shmoo_error_array_t *seaPtr) 187 { 188 ydc_ddr_bist_err_cnt_t be; 189 190 switch ((*scPtr).shmooType) { 191 case SHMOO_SJC16_RD_EN_FISH: 192 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 193 break; 194 case SHMOO_SJC16_RD_EXTENDED: 195 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 196 197 if(shmoo_dram_info.interface_bitwidth == 16) 198 { 199 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF; 200 } 201 else 202 { 203 (*seaPtr)[0] = be.bist_err_occur; 204 } 205 break; 206 case SHMOO_SJC16_WR_EXTENDED: 207 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 208 209 if(shmoo_dram_info.interface_bitwidth == 16) 210 { 211 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF; 212 } 213 else 214 { 215 (*seaPtr)[0] = be.bist_err_occur; 216 } 217 break; 218 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 219 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 220 221 if(shmoo_dram_info.interface_bitwidth == 16) 222 { 223 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF; 224 } 225 else 226 { 227 (*seaPtr)[0] = be.bist_err_occur; 228 } 229 break; 230 case SHMOO_SJC16_ADDR_EXTENDED: 231 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 232 233 if(shmoo_dram_info.interface_bitwidth == 16) 234 { 235 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF; 236 } 237 else 238 { 239 (*seaPtr)[0] = be.bist_err_occur; 240 } 241 break; 242 case SHMOO_SJC16_CTRL_EXTENDED: 243 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 244 245 if(shmoo_dram_info.interface_bitwidth == 16) 246 { 247 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF; 248 } 249 else 250 { 251 (*seaPtr)[0] = be.bist_err_occur; 252 } 253 break; 254 case SHMOO_SJC16_RD_EN_FISH_ECC: 255 /* iproc16_clear_ecc_syndrome(); */ 256 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 257 break; 258 case SHMOO_SJC16_RD_EXTENDED_ECC: 259 /* iproc16_clear_ecc_syndrome(); */ 260 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 261 262 if(be.bist_err_occur /* | iproc16_read_ecc_syndrome() */) 263 { 264 (*seaPtr)[0] = 0xFFFFFFFF; 265 } 266 else 267 { 268 (*seaPtr)[0] = 0x00000000; 269 } 270 break; 271 case SHMOO_SJC16_WR_EXTENDED_ECC: 272 /* iproc16_clear_ecc_syndrome(); */ 273 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be)); 274 275 if(be.bist_err_occur /* | iproc16_read_ecc_syndrome() */) 276 { 277 (*seaPtr)[0] = 0xFFFFFFFF; 278 } 279 else 280 { 281 (*seaPtr)[0] = 0x00000000; 282 } 283 break; 284 default: 285 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (unsigned int)(*scPtr).shmooType)); 286 return SOC_E_FAIL; 287 } 288 289 return SOC_E_NONE; 290 } 291 292 STATIC int 293 _calculate_ui_position(uint32 linearPos, sjc16_shmoo_container_t *scPtr, sjc16_ui_position_t *upPtr) 294 { 295 uint32 ui; 296 uint32 position; 297 298 position = linearPos; 299 300 for(ui = 0; ui < SHMOO_SJC16_MAX_EFFECTIVE_UI_COUNT; ui++) 301 { 302 if(linearPos <= (*scPtr).endUI[ui]) 303 { 304 if(ui != 0) 305 { 306 position = linearPos - ((*scPtr).endUI[ui - 1] + 1); 307 } 308 break; 309 } 310 } 311 312 if(ui == SHMOO_SJC16_MAX_EFFECTIVE_UI_COUNT) 313 { 314 ui--; 315 position = linearPos - ((*scPtr).endUI[ui] + 1); 316 } 317 318 (*upPtr).ui = ui; 319 (*upPtr).position = position; 320 321 return SOC_E_NONE; 322 } 323 324 STATIC int 325 _calculate_addr_ui_position(uint32 linearPos, sjc16_shmoo_container_t *scPtr, sjc16_ui_position_t *upPtr) 326 { 327 uint32 ui; 328 uint32 position; 329 330 position = linearPos; 331 332 for(ui = 1; ui < SHMOO_SJC16_MAX_EFFECTIVE_UI_COUNT; ui += 2) 333 { 334 if(linearPos <= (*scPtr).endUI[ui]) 335 { 336 if(ui != 1) 337 { 338 position = linearPos - ((*scPtr).endUI[ui - 2] + 1); 339 } 340 break; 341 } 342 } 343 344 if(ui >= SHMOO_SJC16_MAX_EFFECTIVE_UI_COUNT) 345 { 346 ui -= 2; 347 position = linearPos - ((*scPtr).endUI[ui] + 1); 348 } 349 350 (*upPtr).ui = ui >> 1; 351 (*upPtr).position = position; 352 353 return SOC_E_NONE; 354 } 355 356 STATIC int 357 _write_mr(uint32 mr_ndx, uint32 mr_data, uint32 mr_mask) 358 { 359 #if defined(CONFIG_HELIX5) 360 int unit = 0; 361 uint32 val; 362 uint32 data; 363 uint32 reg_mr_field_lsb; 364 uint32 reg_mr_single_field_lsb; 365 uint32 reg_mr_field_mask; 366 367 reg_mr_single_field_lsb = 0; 368 reg_mr_field_mask = 0x1FFFF; 369 370 switch(mr_ndx) 371 { 372 case 0: 373 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_46r(unit, &val)); 374 reg_mr_field_lsb = 8; 375 break; 376 case 1: 377 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_47r(unit, &val)); 378 reg_mr_field_lsb = 0; 379 break; 380 case 2: 381 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_48r(unit, &val)); 382 reg_mr_field_lsb = 0; 383 break; 384 case 3: 385 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_50r(unit, &val)); 386 reg_mr_field_lsb = 0; 387 break; 388 case 4: 389 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_51r(unit, &val)); 390 reg_mr_field_lsb = 0; 391 break; 392 case 5: 393 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_52r(unit, &val)); 394 reg_mr_field_lsb = 0; 395 break; 396 case 6: 397 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_53r(unit, &val)); 398 reg_mr_field_lsb = 0; 399 break; 400 default: 401 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported MR register: %d\n"), mr_ndx)); 402 return SOC_E_FAIL; 403 } 404 405 data = (val >> reg_mr_field_lsb) & reg_mr_field_mask; 406 data &= ~mr_mask; 407 data |= (mr_data & mr_mask); 408 val &= ~(reg_mr_field_mask << reg_mr_field_lsb); 409 val |= data << reg_mr_field_lsb; 410 411 switch(mr_ndx) 412 { 413 case 0: 414 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_46r(unit, val)); 415 break; 416 case 1: 417 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_47r(unit, val)); 418 break; 419 case 2: 420 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_48r(unit, val)); 421 break; 422 case 3: 423 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_50r(unit, val)); 424 break; 425 case 4: 426 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_51r(unit, val)); 427 break; 428 case 5: 429 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_52r(unit, val)); 430 break; 431 case 6: 432 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_53r(unit, val)); 433 break; 434 } 435 436 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_49r(unit, &val)); 437 val &= ~(reg_mr_field_mask << reg_mr_single_field_lsb); 438 val |= data << reg_mr_single_field_lsb; 439 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_49r(unit, val)); 440 441 val = 0x01800000 | mr_ndx; 442 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_37r(unit, val)); 443 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 444 445 val |= 0x02000000; 446 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_37r(unit, val)); 447 sal_usleep(SHMOO_SJC16_LONG_SLEEP); 448 449 val &= ~(0x02000000); 450 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_37r(unit, val)); 451 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 452 #endif /* CONFIG_HELIX5 */ 453 return SOC_E_NONE; 454 } 455 456 STATIC int 457 _reset_dram(sjc16_shmoo_container_t *scPtr) 458 { 459 #if defined(CONFIG_HELIX5) 460 uint32 i, iMemC, iBist, iPhy; 461 int unit = 0; 462 uint32 reg_addr; 463 uint32 data, reset_ctrl_data, read_fifo_ctrl_data; 464 465 i = (SHMOO_SJC16_RESULT2D_X)*(SHMOO_SJC16_RESULT2D_Y) - 1; 466 reg_addr = 0x1023B000; 467 iMemC = i; 468 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i]); 469 (*scPtr).result2D[i--] &= 0xFFFFFFFE; 470 471 for(reg_addr = 0x1023B004; reg_addr < 0x1023B29C; reg_addr+=4) 472 { 473 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 474 } 475 476 iBist = i; 477 for(reg_addr = 0x1023BC00; reg_addr < 0x1023BDF0; reg_addr+=4) 478 { 479 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 480 } 481 482 iPhy = i; 483 for(reg_addr = 0x1023C000; reg_addr < 0x1023C144; reg_addr+=4) 484 { 485 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 486 } 487 488 for(reg_addr = 0x1023C400; reg_addr < 0x1023C544; reg_addr+=4) 489 { 490 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 491 } 492 493 for(reg_addr = 0x1023C800; reg_addr < 0x1023C944; reg_addr+=4) 494 { 495 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 496 } 497 498 for(reg_addr = 0x1023CC00; reg_addr < 0x1023CD44; reg_addr+=4) 499 { 500 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 501 } 502 503 for(reg_addr = 0x1023D000; reg_addr < 0x1023D144; reg_addr+=4) 504 { 505 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 506 } 507 508 for(reg_addr = 0x1023F000; reg_addr < 0x1023F00C; reg_addr+=4) 509 { 510 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 511 } 512 513 for(reg_addr = 0x1023F400; reg_addr < 0x1023F428; reg_addr+=4) 514 { 515 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 516 } 517 518 for(reg_addr = 0x1023F800; reg_addr < 0x1023F824; reg_addr+=4) 519 { 520 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 521 } 522 523 for(reg_addr = 0x1023FC00; reg_addr < 0x1023FC48; reg_addr+=4) 524 { 525 soc_iproc_getreg(unit, reg_addr, &(*scPtr).result2D[i--]); 526 } 527 528 SOC_IF_ERROR_RETURN(WRITE_DDR_S1_IDM_RESET_CONTROLr(unit, 1)); 529 SOC_IF_ERROR_RETURN(WRITE_DDR_S0_IDM_RESET_CONTROLr(unit, 1)); 530 531 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 532 533 SOC_IF_ERROR_RETURN(WRITE_DDR_S1_IDM_RESET_CONTROLr(unit, 0)); 534 SOC_IF_ERROR_RETURN(WRITE_DDR_S0_IDM_RESET_CONTROLr(unit, 0)); 535 536 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 537 538 reset_ctrl_data = 0; 539 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, 0)); 540 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 541 542 read_fifo_ctrl_data = 0; 543 DDR_PHY_SET_FIELD(read_fifo_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, READ_FIFO_CTRL, W2R_MIN_DELAY_2, 0); 544 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRLr(unit, read_fifo_ctrl_data)); 545 546 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 547 548 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, READ_FIFO_RESET_N, 1); 549 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 550 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 551 552 DDR_PHY_SET_FIELD(read_fifo_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, READ_FIFO_CTRL, ENABLE, 1); 553 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRLr(unit, read_fifo_ctrl_data)); 554 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 555 556 i = iPhy; 557 for(reg_addr = 0x1023C000; reg_addr < 0x1023C144; reg_addr+=4) 558 { 559 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 560 } 561 562 for(reg_addr = 0x1023C400; reg_addr < 0x1023C544; reg_addr+=4) 563 { 564 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 565 } 566 567 for(reg_addr = 0x1023C800; reg_addr < 0x1023C944; reg_addr+=4) 568 { 569 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 570 } 571 572 for(reg_addr = 0x1023CC00; reg_addr < 0x1023CD44; reg_addr+=4) 573 { 574 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 575 } 576 577 for(reg_addr = 0x1023D000; reg_addr < 0x1023D144; reg_addr+=4) 578 { 579 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 580 } 581 582 for(reg_addr = 0x1023F000; reg_addr < 0x1023F00C; reg_addr+=4) 583 { 584 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 585 } 586 587 for(reg_addr = 0x1023F400; reg_addr < 0x1023F428; reg_addr+=4) 588 { 589 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 590 } 591 592 for(reg_addr = 0x1023F800; reg_addr < 0x1023F824; reg_addr+=4) 593 { 594 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 595 } 596 597 for(reg_addr = 0x1023FC00; reg_addr < 0x1023FC48; reg_addr+=4) 598 { 599 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 600 } 601 602 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 603 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 604 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 605 606 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 607 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 608 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 609 610 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 611 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 612 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 613 614 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 615 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 616 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 617 618 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 619 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 620 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 621 622 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 623 624 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 625 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 626 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 627 628 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 629 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 630 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 631 632 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 633 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 634 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 635 636 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 637 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 638 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 639 640 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 641 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 642 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 643 644 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 645 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 646 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 647 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 648 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 649 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 650 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 651 652 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 653 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 654 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 655 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 656 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 657 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 658 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 659 660 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 661 662 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 663 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 664 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 665 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 666 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 667 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 668 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 669 670 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 671 672 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 673 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 674 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 675 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 676 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 677 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 678 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 679 680 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 681 682 i = iMemC; 683 684 for(reg_addr = 0x1023B000; reg_addr < 0x1023B29C; reg_addr+=4) 685 { 686 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 687 } 688 689 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &data)); 690 data |= 0x01; 691 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_00r(unit, data)); 692 693 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_89r(unit, &data)); 694 while(!(data & (0x800))) { 695 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_89r(unit, &data)); 696 } 697 698 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_91r(unit, &data)); 699 data |= 0x800; 700 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_91r(unit, data)); 701 702 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 703 704 i = iBist; 705 for(reg_addr = 0x1023BC00; reg_addr < 0x1023BDF0; reg_addr+=4) 706 { 707 soc_iproc_setreg(unit, reg_addr, (*scPtr).result2D[i--]); 708 } 709 710 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 711 #endif 712 713 return SOC_E_NONE; 714 } 715 716 STATIC int 717 _shmoo_sjc16_rd_en_fish(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 718 { 719 uint32 x; 720 uint32 d; 721 uint32 data; 722 723 uint32 jump = 3; 724 uint32 wp0_pre = 0, wp1_pre = 0, wp2_pre = 0, wp3_pre = 0; 725 uint32 wp0_post = 0, wp1_post = 0, wp2_post = 0, wp3_post = 0; 726 uint32 sp0_pre = 0xFF, sp1_pre = 0xFF, sp2_pre = 0xFF, sp3_pre = 0xFF; 727 uint32 sp0_post = 0xFF, sp1_post = 0xFF, sp2_post = 0xFF, sp3_post = 0xFF; 728 uint32 fish0 = 1, fish1 = 1, fish2 = 1, fish3 = 1; 729 730 (*scPtr).engageUIshift = 0; 731 (*scPtr).shmooType = SHMOO_SJC16_RD_EN_FISH; 732 733 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n\n"))); 734 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "***** Interface.......: %3d\n"), phy_ndx)); 735 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: RD_EN_FISH\n"))); 736 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Searching.......: RD_2G_DELAY\n"))); 737 738 _initialize_bist(unit, phy_ndx, -1, scPtr); 739 740 for(d = 0; d < 32; d++) 741 { 742 if(fish0) 743 { 744 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIGr(unit, &data)); 745 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_FIFO_CONFIG, RD_2G_DELAY, d); 746 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIGr(unit, data)); 747 } 748 if(fish1) 749 { 750 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIGr(unit, &data)); 751 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, DDR4_REN_FIFO_CONFIG, RD_2G_DELAY, d); 752 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIGr(unit, data)); 753 } 754 if(fish2) 755 { 756 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIGr(unit, &data)); 757 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, DDR4_REN_FIFO_CONFIG, RD_2G_DELAY, d); 758 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIGr(unit, data)); 759 } 760 if(fish3) 761 { 762 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIGr(unit, &data)); 763 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, DDR4_REN_FIFO_CONFIG, RD_2G_DELAY, d); 764 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIGr(unit, data)); 765 } 766 767 for(x = 0; x < (((*scPtr).endUI[3] + 1) >> jump); x++) 768 { 769 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 770 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, x << jump); 771 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 772 773 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 774 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 775 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 776 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 777 778 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 779 780 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 781 782 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 783 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 784 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 785 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 786 787 788 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 789 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 790 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 791 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 792 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 793 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 794 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 795 796 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 797 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 798 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 799 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 800 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 801 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 802 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 803 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 804 805 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 806 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 807 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 808 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 809 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 810 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 811 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 812 813 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 814 815 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 816 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 817 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 818 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 819 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 820 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 821 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 822 823 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 824 825 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFOr(unit, &wp0_pre)); 826 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFOr(unit, &wp1_pre)); 827 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFOr(unit, &wp2_pre)); 828 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFOr(unit, &wp3_pre)); 829 830 wp0_pre &= 0xF; 831 wp1_pre &= 0xF; 832 wp2_pre &= 0xF; 833 wp3_pre &= 0xF; 834 835 _run_bist(unit, phy_ndx, scPtr, NULL); 836 837 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFOr(unit, &wp0_post)); 838 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFOr(unit, &wp1_post)); 839 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFOr(unit, &wp2_post)); 840 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFOr(unit, &wp3_post)); 841 842 wp0_post &= 0xF; 843 wp1_post &= 0xF; 844 wp2_post &= 0xF; 845 wp3_post &= 0xF; 846 847 if(wp0_post < wp0_pre) 848 { 849 wp0_post += 0x10; 850 } 851 if(wp1_post < wp1_pre) 852 { 853 wp1_post += 0x10; 854 } 855 if(wp2_post < wp2_pre) 856 { 857 wp2_post += 0x10; 858 } 859 if(wp3_post < wp3_pre) 860 { 861 wp3_post += 0x10; 862 } 863 864 if(fish0) 865 { 866 sp0_pre = wp0_pre; 867 sp0_post = wp0_post; 868 869 if(wp0_post - wp0_pre == 4) 870 { 871 fish0 = 0; 872 } 873 } 874 if(fish1) 875 { 876 sp1_pre = wp1_pre; 877 sp1_post = wp1_post; 878 879 if(wp1_post - wp1_pre == 4) 880 { 881 fish1 = 0; 882 } 883 } 884 if(fish2) 885 { 886 sp2_pre = wp2_pre; 887 sp2_post = wp2_post; 888 889 if(wp2_post - wp2_pre == 4) 890 { 891 fish2 = 0; 892 } 893 } 894 if(fish3) 895 { 896 sp3_pre = wp3_pre; 897 sp3_post = wp3_post; 898 899 if(wp3_post - wp3_pre == 4) 900 { 901 fish3 = 0; 902 } 903 } 904 } 905 906 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Delay %02u........: %01u %01u %01u %01u PRE: %02u %02u %02u %02u POST: %02u %02u %02u %02u\n"), 907 d, fish3, fish2, fish1, fish0, sp3_pre, sp2_pre, sp1_pre, sp0_pre, sp3_post, sp2_post, sp1_post, sp0_post)); 908 909 if(!(fish0 || fish1 || fish2 || fish3)) 910 { 911 break; 912 } 913 } 914 915 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 916 917 return SOC_E_NONE; 918 } 919 920 STATIC int 921 _shmoo_sjc16_rd_en_fish_ecc(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 922 { 923 uint32 x; 924 uint32 d; 925 uint32 data; 926 uint32 jump = 3; 927 uint32 wp4_pre = 0; 928 uint32 wp4_post = 0; 929 uint32 fish4 = 1; 930 931 (*scPtr).engageUIshift = 0; 932 (*scPtr).shmooType = SHMOO_SJC16_RD_EN_FISH; 933 934 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n\n"))); 935 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "***** Interface.......: %3d\n"), phy_ndx)); 936 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: RD_EN_FISH_ECC\n"))); 937 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Searching.......: RD_2G_DELAY\n"))); 938 939 _initialize_bist(unit, phy_ndx, -1, scPtr); 940 941 for(d = 0; d < 32; d++) 942 { 943 if(fish4) 944 { 945 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIGr(unit, &data)); 946 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_FIFO_CONFIG, RD_2G_DELAY, d); 947 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIGr(unit, data)); 948 } 949 950 for(x = 0; x < (((*scPtr).endUI[3] + 1) >> jump); x++) 951 { 952 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 953 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, x << jump); 954 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 955 956 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 957 958 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 959 960 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 961 962 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 963 964 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 965 966 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 967 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 968 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 969 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 970 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 971 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 972 973 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 974 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 975 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 976 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 977 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 978 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 979 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 980 981 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 982 983 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 984 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 985 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 986 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 987 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 988 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 989 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 990 991 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 992 993 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 994 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 995 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 996 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 997 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 998 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 999 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 1000 1001 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1002 1003 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFOr(unit, &wp4_pre)); 1004 1005 wp4_pre &= 0xF; 1006 1007 _run_bist(unit, phy_ndx, scPtr, NULL); 1008 1009 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFOr(unit, &wp4_post)); 1010 1011 wp4_post &= 0xF; 1012 1013 if(wp4_post < wp4_pre) 1014 { 1015 wp4_post += 0x10; 1016 } 1017 1018 if(wp4_post - wp4_pre == 4) 1019 { 1020 fish4 = 0; 1021 } 1022 } 1023 1024 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Delay %02u........: %01u PRE: %02u POST: %02u\n"), 1025 d, fish4, wp4_pre, wp4_post)); 1026 1027 if(!fish4) 1028 { 1029 break; 1030 } 1031 } 1032 1033 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 1034 1035 return SOC_E_NONE; 1036 } 1037 1038 STATIC int 1039 _shmoo_sjc16_wr_extended(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1040 { 1041 uint32 x; 1042 uint32 ui; 1043 uint32 position; 1044 uint32 y; 1045 uint32 yCapMin; 1046 uint32 yCapMax; 1047 uint32 sizeY; 1048 uint32 xStart; 1049 int MRfield; 1050 uint32 data; 1051 sjc16_shmoo_error_array_t sea; 1052 1053 yCapMin = 8; 1054 yCapMax = 71; 1055 xStart = 0; 1056 1057 sizeY = yCapMax - yCapMin; 1058 (*scPtr).engageUIshift = 1; 1059 (*scPtr).sizeX = (*scPtr).endUI[2] + 1; 1060 (*scPtr).sizeY = sizeY; 1061 (*scPtr).yCapMin = yCapMin; 1062 (*scPtr).yCapMax = yCapMax; 1063 (*scPtr).shmooType = SHMOO_SJC16_WR_EXTENDED; 1064 1065 _initialize_bist(unit, phy_ndx, -1, scPtr); 1066 1067 for(y = yCapMin; y < yCapMax; y++) 1068 { 1069 if(y > SHMOO_SJC16_DDR4_VREF_RANGE_CROSSOVER) 1070 { /* Vref Range 1 */ 1071 MRfield = y - 23; 1072 } 1073 else 1074 { /* Vref Range 2 */ 1075 MRfield = y | 0x40; 1076 } 1077 _write_mr(6, MRfield, 0x7F); 1078 1079 position = 0; 1080 ui = 0; 1081 1082 for(x = 0; x < (*scPtr).sizeX; x++) 1083 { 1084 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, &data)); 1085 if((x > (*scPtr).endUI[ui]) && (ui < SHMOO_SJC16_LAST_EFFECTIVE_UI)) 1086 { 1087 ui++; 1088 position = 0; 1089 } 1090 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, UI_SHIFT, ui); 1091 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, position); 1092 position++; 1093 1094 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 1095 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 1096 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 1097 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 1098 1099 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1100 1101 _run_bist(unit, phy_ndx, scPtr, &sea); 1102 1103 (*scPtr).result2D[x + xStart] = sea[0]; 1104 } 1105 1106 xStart += (*scPtr).sizeX; 1107 } 1108 1109 return SOC_E_NONE; 1110 } 1111 1112 STATIC int 1113 _shmoo_sjc16_wr_extended_ecc(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1114 { 1115 uint32 x; 1116 uint32 ui; 1117 uint32 position; 1118 uint32 y; 1119 uint32 yCapMin; 1120 uint32 yCapMax; 1121 uint32 sizeY; 1122 uint32 xStart; 1123 uint32 data; 1124 sjc16_shmoo_error_array_t sea; 1125 1126 yCapMin = 0; 1127 yCapMax = 1; 1128 sizeY = 1; 1129 xStart = 0; 1130 1131 (*scPtr).engageUIshift = 1; 1132 (*scPtr).sizeX = (*scPtr).endUI[3] + 1; 1133 (*scPtr).sizeY = sizeY; 1134 (*scPtr).yCapMin = yCapMin; 1135 (*scPtr).yCapMax = yCapMax; 1136 (*scPtr).shmooType = SHMOO_SJC16_WR_EXTENDED; 1137 1138 _initialize_bist(unit, phy_ndx, -1, scPtr); 1139 1140 for(y = yCapMin; y < yCapMax; y++) 1141 { 1142 position = 0; 1143 ui = 0; 1144 1145 for(x = 0; x < (*scPtr).sizeX; x++) 1146 { 1147 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, &data)); 1148 1149 if((x > (*scPtr).endUI[ui]) && (ui < SHMOO_SJC16_LAST_EFFECTIVE_UI)) 1150 { 1151 ui++; 1152 position = 0; 1153 } 1154 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, WRITE_MAX_VDL_DATA, UI_SHIFT, ui); 1155 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, position); 1156 position++; 1157 1158 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, data)); 1159 1160 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1161 1162 _run_bist(unit, phy_ndx, scPtr, &sea); 1163 1164 (*scPtr).result2D[x + xStart] = sea[0]; 1165 } 1166 1167 xStart += (*scPtr).sizeX; 1168 } 1169 1170 return SOC_E_NONE; 1171 } 1172 1173 STATIC int 1174 _shmoo_sjc16_rd_extended(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1175 { 1176 uint32 x; 1177 uint32 y; 1178 uint32 yCapMin; 1179 uint32 yCapMax; 1180 uint32 sizeY; 1181 uint32 xStart; 1182 uint32 data; 1183 sjc16_shmoo_error_array_t sea; 1184 1185 xStart = 0; 1186 1187 yCapMin = 42; 1188 yCapMax = 105; 1189 (*scPtr).sizeX = (*scPtr).endUI[2] + 1; 1190 1191 if((*scPtr).debugMode & SHMOO_SJC16_CTL_FLAGS_EXT_VREF_RANGE_BIT) 1192 { 1193 yCapMin = 11; 1194 yCapMax = 126; 1195 } 1196 1197 sizeY = yCapMax - yCapMin; 1198 (*scPtr).engageUIshift = 0; 1199 (*scPtr).sizeY = sizeY; 1200 (*scPtr).yCapMin = yCapMin; 1201 (*scPtr).yCapMax = yCapMax; 1202 (*scPtr).shmooType = SHMOO_SJC16_RD_EXTENDED; 1203 1204 _initialize_bist(unit, phy_ndx, -1, scPtr); 1205 1206 for(y = yCapMin; y < yCapMax; y++) 1207 { 1208 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, &data)); 1209 1210 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, VREF_DAC_CONFIG, DATA, y << 1); 1211 1212 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 1213 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 1214 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 1215 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 1216 1217 for(x = (*scPtr).calibStart; x < (*scPtr).sizeX; x++) 1218 { 1219 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 1220 1221 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, x); 1222 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 1223 1224 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1225 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1226 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1227 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1228 1229 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1230 1231 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 1232 1233 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1234 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1235 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1236 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1237 1238 1239 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 1240 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 1241 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 1242 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 1243 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 1244 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 1245 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 1246 1247 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 1248 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 1249 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 1250 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 1251 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 1252 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 1253 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 1254 1255 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1256 1257 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 1258 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 1259 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 1260 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 1261 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 1262 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 1263 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 1264 1265 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1266 1267 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 1268 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 1269 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 1270 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 1271 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 1272 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 1273 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 1274 1275 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1276 1277 _run_bist(unit, phy_ndx, scPtr, &sea); 1278 1279 (*scPtr).result2D[x + xStart] = sea[0]; 1280 } 1281 1282 xStart += (*scPtr).sizeX; 1283 } 1284 1285 return SOC_E_NONE; 1286 } 1287 1288 STATIC int 1289 _shmoo_sjc16_rd_extended_ecc(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1290 { 1291 uint32 x; 1292 uint32 y; 1293 uint32 yCapMin; 1294 uint32 yCapMax; 1295 uint32 sizeY; 1296 uint32 xStart; 1297 uint32 data; 1298 sjc16_shmoo_error_array_t sea; 1299 1300 sizeY = SHMOO_SJC16_MAX_VREF_RANGE; 1301 xStart = 0; 1302 1303 yCapMin = 58; 1304 yCapMax = 89; 1305 (*scPtr).sizeX = (*scPtr).endUI[3] + 1; 1306 1307 if((*scPtr).debugMode & SHMOO_SJC16_CTL_FLAGS_EXT_VREF_RANGE_BIT) 1308 { 1309 yCapMin = 11; 1310 yCapMax = 126; 1311 } 1312 1313 (*scPtr).engageUIshift = 0; 1314 (*scPtr).sizeY = sizeY; 1315 (*scPtr).yCapMin = yCapMin; 1316 (*scPtr).yCapMax = yCapMax; 1317 (*scPtr).shmooType = SHMOO_SJC16_RD_EXTENDED; 1318 1319 _initialize_bist(unit, phy_ndx, -1, scPtr); 1320 1321 for(y = yCapMin; y < yCapMax; y++) 1322 { 1323 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, &data)); 1324 1325 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, VREF_DAC_CONFIG, DATA, y << 1); 1326 1327 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, data)); 1328 1329 for(x = (*scPtr).calibStart; x < (*scPtr).sizeX; x++) 1330 { 1331 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 1332 1333 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, x); 1334 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 1335 1336 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1337 1338 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1339 1340 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 1341 1342 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1343 1344 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 1345 1346 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 1347 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 1348 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 1349 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 1350 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 1351 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 1352 1353 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 1354 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 1355 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 1356 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 1357 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 1358 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 1359 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 1360 1361 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1362 1363 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 1364 1365 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 1366 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 1367 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 1368 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 1369 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 1370 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 1371 1372 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1373 1374 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 1375 1376 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 1377 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 1378 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 1379 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 1380 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 1381 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 1382 1383 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1384 1385 _run_bist(unit, phy_ndx, scPtr, &sea); 1386 1387 (*scPtr).result2D[x + xStart] = sea[0]; 1388 } 1389 1390 xStart += (*scPtr).sizeX; 1391 } 1392 1393 return SOC_E_NONE; 1394 } 1395 1396 STATIC int 1397 _shmoo_sjc16_addr_ctrl_extended(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1398 { 1399 uint32 x; 1400 uint32 ui, addr_ui; 1401 uint32 position; 1402 uint32 data; 1403 uint32 prevResult; 1404 sjc16_shmoo_error_array_t sea; 1405 1406 (*scPtr).engageUIshift = 1; 1407 (*scPtr).sizeX = (*scPtr).endUI[8] + 1; 1408 (*scPtr).sizeY = 1; 1409 (*scPtr).yCapMin = 0; 1410 (*scPtr).yCapMax = 1; 1411 (*scPtr).shmooType = SHMOO_SJC16_ADDR_CTRL_EXTENDED; 1412 1413 _initialize_bist(unit, phy_ndx, -1, scPtr); 1414 1415 ui = 0; 1416 addr_ui = 0; 1417 position = 0; 1418 prevResult = 1; 1419 1420 for(x = (*scPtr).calibStart; x < (*scPtr).sizeX; x++) 1421 { 1422 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, &data)); 1423 if((x > (*scPtr).endUI[ui]) && (ui < SHMOO_SJC16_LAST_EFFECTIVE_UI)) 1424 { 1425 ui++; 1426 addr_ui = ui >> 1; 1427 if((addr_ui << 1) == ui) 1428 { 1429 position = 0; 1430 } 1431 } 1432 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, UI_SHIFT, addr_ui); 1433 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, position); 1434 position++; 1435 1436 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, data)); 1437 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, data)); 1438 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, data)); 1439 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, data)); 1440 1441 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1442 1443 if(prevResult) 1444 { 1445 #if defined(CONFIG_HELIX5) 1446 _reset_dram(scPtr); 1447 #endif 1448 } 1449 1450 _run_bist(unit, phy_ndx, scPtr, &sea); 1451 1452 (*scPtr).result2D[x] = sea[0]; 1453 } 1454 1455 return SOC_E_NONE; 1456 } 1457 1458 STATIC int 1459 _shmoo_sjc16_addr_extended(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1460 { 1461 uint32 x; 1462 uint32 ui, addr_ui; 1463 uint32 position; 1464 uint32 data; 1465 uint32 prevResult; 1466 sjc16_shmoo_error_array_t sea; 1467 1468 (*scPtr).engageUIshift = 1; 1469 (*scPtr).sizeX = (*scPtr).endUI[8] + 1; 1470 (*scPtr).sizeY = 1; 1471 (*scPtr).yCapMin = 0; 1472 (*scPtr).yCapMax = 1; 1473 (*scPtr).shmooType = SHMOO_SJC16_ADDR_EXTENDED; 1474 1475 _initialize_bist(unit, phy_ndx, -1, scPtr); 1476 1477 ui = 0; 1478 addr_ui = 0; 1479 position = 0; 1480 prevResult = 1; 1481 1482 for(x = (*scPtr).calibStart; x < (*scPtr).sizeX; x++) 1483 { 1484 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, &data)); 1485 if((x > (*scPtr).endUI[ui]) && (ui < SHMOO_SJC16_LAST_EFFECTIVE_UI)) 1486 { 1487 ui++; 1488 addr_ui = ui >> 1; 1489 if((addr_ui << 1) == ui) 1490 { 1491 position = 0; 1492 } 1493 } 1494 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, UI_SHIFT, addr_ui); 1495 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, position); 1496 position++; 1497 1498 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, data)); 1499 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, data)); 1500 1501 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1502 1503 if(prevResult) 1504 { 1505 #if defined(CONFIG_HELIX5) 1506 _reset_dram(scPtr); 1507 #endif 1508 } 1509 1510 _run_bist(unit, phy_ndx, scPtr, &sea); 1511 1512 (*scPtr).result2D[x] = sea[0]; 1513 1514 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "x: %03u Addr UI: %u Addr Step: %03u Result: 0x%08X\n"), 1515 x, addr_ui, position, sea[0])); 1516 } 1517 1518 return SOC_E_NONE; 1519 } 1520 1521 STATIC int 1522 _shmoo_sjc16_ctrl_extended(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1523 { 1524 uint32 x; 1525 uint32 ui, addr_ui; 1526 uint32 position; 1527 uint32 data; 1528 uint32 prevResult; 1529 sjc16_shmoo_error_array_t sea; 1530 1531 (*scPtr).engageUIshift = 1; 1532 (*scPtr).sizeX = (*scPtr).endUI[8] + 1; 1533 (*scPtr).sizeY = 1; 1534 (*scPtr).yCapMin = 0; 1535 (*scPtr).yCapMax = 1; 1536 (*scPtr).shmooType = SHMOO_SJC16_CTRL_EXTENDED; 1537 1538 _initialize_bist(unit, phy_ndx, -1, scPtr); 1539 1540 ui = 0 ; 1541 addr_ui = 0; 1542 position = 0; 1543 prevResult = 1; 1544 1545 for(x = (*scPtr).calibStart; x < (*scPtr).sizeX; x++) 1546 { 1547 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, &data)); 1548 if((x > (*scPtr).endUI[ui]) && (ui < SHMOO_SJC16_LAST_EFFECTIVE_UI)) 1549 { 1550 ui++; 1551 addr_ui = ui >> 1; 1552 if((addr_ui << 1) == ui) 1553 { 1554 position = 0; 1555 } 1556 } 1557 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, UI_SHIFT, addr_ui); 1558 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, position); 1559 position++; 1560 1561 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, data)); 1562 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, data)); 1563 1564 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1565 1566 if(prevResult) 1567 { 1568 #if defined(CONFIG_HELIX5) 1569 _reset_dram(scPtr); 1570 #endif 1571 } 1572 1573 _run_bist(unit, phy_ndx, scPtr, &sea); 1574 1575 (*scPtr).result2D[x] = sea[0]; 1576 1577 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "x: %03u Addr UI: %u Addr Step: %03u Result: 0x%08X\n"), 1578 x, addr_ui, position, sea[0])); 1579 } 1580 1581 return SOC_E_NONE; 1582 } 1583 1584 STATIC int 1585 _shmoo_sjc16_do(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1586 { 1587 switch ((*scPtr).shmooType) { 1588 case SHMOO_SJC16_RD_EN_FISH: 1589 return _shmoo_sjc16_rd_en_fish(unit, phy_ndx, scPtr); 1590 case SHMOO_SJC16_RD_EXTENDED: 1591 return _shmoo_sjc16_rd_extended(unit, phy_ndx, scPtr); 1592 case SHMOO_SJC16_WR_EXTENDED: 1593 return _shmoo_sjc16_wr_extended(unit, phy_ndx, scPtr); 1594 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 1595 return _shmoo_sjc16_addr_ctrl_extended(unit, phy_ndx, scPtr); 1596 case SHMOO_SJC16_ADDR_EXTENDED: 1597 return _shmoo_sjc16_addr_extended(unit, phy_ndx, scPtr); 1598 case SHMOO_SJC16_CTRL_EXTENDED: 1599 if(!SHMOO_SJC16_QUICK_SHMOO_CTRL_EXTENDED) 1600 { 1601 return _shmoo_sjc16_ctrl_extended(unit, phy_ndx, scPtr); 1602 } 1603 break; 1604 case SHMOO_SJC16_RD_EN_FISH_ECC: 1605 return _shmoo_sjc16_rd_en_fish_ecc(unit, phy_ndx, scPtr); 1606 case SHMOO_SJC16_RD_EXTENDED_ECC: 1607 return _shmoo_sjc16_rd_extended_ecc(unit, phy_ndx, scPtr); 1608 case SHMOO_SJC16_WR_EXTENDED_ECC: 1609 return _shmoo_sjc16_wr_extended_ecc(unit, phy_ndx, scPtr); 1610 default: 1611 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (*scPtr).shmooType)); 1612 return SOC_E_FAIL; 1613 } 1614 return SOC_E_NONE; 1615 } 1616 1617 STATIC int 1618 _calib_2D(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr, uint32 calibMode, uint32 calibPos) 1619 { 1620 uint32 x; 1621 uint32 y; 1622 uint32 xStart; 1623 uint32 sizeX; 1624 uint32 calibStart; 1625 uint32 yCapMin; 1626 uint32 yCapMax; 1627 uint32 i; 1628 uint32 iter; 1629 uint32 shiftAmount; 1630 uint32 dataMask; 1631 int32 passStart; 1632 int32 failStart; 1633 int32 passStartSeen; 1634 int32 failStartSeen; 1635 int32 passLength; 1636 int32 maxPassStart; 1637 int32 maxPassLength; 1638 int32 maxMidPointX; 1639 uint32 maxPassLengthArray[SHMOO_SJC16_WORD]; 1640 uint32 xSum[SHMOO_SJC16_WORD], ySum[SHMOO_SJC16_WORD], passCount[SHMOO_SJC16_WORD]; 1641 1642 xStart = 0; 1643 sizeX = (*scPtr).sizeX; 1644 calibStart = (*scPtr).calibStart; 1645 yCapMin = (*scPtr).yCapMin; 1646 yCapMax = (*scPtr).yCapMax; 1647 1648 switch(calibMode) 1649 { 1650 case SHMOO_SJC16_BIT: 1651 iter = shmoo_dram_info.interface_bitwidth; 1652 shiftAmount = 0; 1653 dataMask = 0x1; 1654 break; 1655 case SHMOO_SJC16_BYTE: 1656 iter = shmoo_dram_info.interface_bitwidth >> 3; 1657 shiftAmount = 3; 1658 dataMask = 0xFF; 1659 break; 1660 case SHMOO_SJC16_HALFWORD: 1661 iter = shmoo_dram_info.interface_bitwidth >> 4; 1662 shiftAmount = 4; 1663 dataMask = 0xFFFF; 1664 break; 1665 case SHMOO_SJC16_WORD: 1666 iter = 1; 1667 shiftAmount = 5; 1668 dataMask = 0xFFFFFFFF; 1669 break; 1670 default: 1671 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported 2D calibration mode: %02u\n"), calibMode)); 1672 return SOC_E_FAIL; 1673 } 1674 1675 for(i = 0; i < iter; i++) 1676 { 1677 (*scPtr).resultData[i] = 0; 1678 maxPassLengthArray[i] = 0; 1679 xSum[i] = 0; 1680 ySum[i] = 0; 1681 passCount[i] = 0; 1682 } 1683 1684 for(y = yCapMin; y < yCapMax; y++) 1685 { 1686 for(i = 0; i < iter; i++) 1687 { 1688 passStart = -1; 1689 failStart = -1; 1690 passLength = -1; 1691 passStartSeen = -1; 1692 failStartSeen = -1; 1693 maxPassStart = -2; 1694 maxPassLength = -2; 1695 maxMidPointX = -2; 1696 for(x = calibStart; x < sizeX; x++) 1697 { 1698 if(((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask) 1699 { /* FAIL */ 1700 if(failStart < 0) { 1701 failStart = x; 1702 if(maxPassLength < passLength) 1703 { 1704 maxPassStart = passStart; 1705 maxPassLength = passLength; 1706 } 1707 passStart = -1; 1708 passLength = -1; 1709 if((failStartSeen < 0) && (maxPassLength > 0)) 1710 { 1711 failStartSeen = x; 1712 } 1713 } 1714 } 1715 else 1716 { /* PASS */ 1717 xSum[i] += x; 1718 ySum[i] += y; 1719 passCount[i]++; 1720 if(passStart < 0) 1721 { 1722 passStart = x; 1723 passLength = 1; 1724 failStart = -1; 1725 if((passStartSeen < 0) && (passLength < x)) 1726 { 1727 passStartSeen = x; 1728 } 1729 } 1730 else 1731 { 1732 passLength++; 1733 } 1734 1735 if(x == sizeX - 1) 1736 { 1737 if(maxPassLength < passLength) 1738 { 1739 maxPassStart = passStart; 1740 maxPassLength = passLength; 1741 } 1742 } 1743 } 1744 } 1745 1746 switch (calibPos) { 1747 case SHMOO_SJC16_CALIB_FAIL_START: 1748 case SHMOO_SJC16_CALIB_RISING_EDGE: 1749 if(failStartSeen > 0) 1750 { 1751 maxMidPointX = failStartSeen; 1752 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1753 } 1754 break; 1755 case SHMOO_SJC16_CALIB_PASS_START: 1756 case SHMOO_SJC16_CALIB_FALLING_EDGE: 1757 if(passStartSeen > 0) 1758 { 1759 maxMidPointX = passStartSeen; 1760 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1761 } 1762 break; 1763 case SHMOO_SJC16_CALIB_CENTER_PASS: 1764 if((maxPassLength > 0) && (maxPassLengthArray[i] < maxPassLength)) 1765 { 1766 maxMidPointX = (maxPassStart + maxPassStart + maxPassLength) >> 1; 1767 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1768 maxPassLengthArray[i] = maxPassLength; 1769 } 1770 break; 1771 case SHMOO_SJC16_CALIB_VDL_ZERO: 1772 maxMidPointX = 0; 1773 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1774 break; 1775 case SHMOO_SJC16_CALIB_XY_AVERAGE: 1776 if (passCount[i]) { 1777 (*scPtr).resultData[i] = ((ySum[i] / passCount[i]) << 16) | ((xSum[i] / passCount[i]) & 0xFFFF); 1778 } else { 1779 (*scPtr).resultData[i] = ((ySum[i] << 16) | (xSum[i] & 0xFFFF)); 1780 } 1781 break; 1782 default: 1783 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration position: %02u\n"), calibPos)); 1784 return SOC_E_FAIL; 1785 } 1786 } 1787 xStart += sizeX; 1788 } 1789 1790 (*scPtr).calibMode = calibMode; 1791 (*scPtr).calibPos = calibPos; 1792 1793 return SOC_E_NONE; 1794 } 1795 1796 STATIC int 1797 _shmoo_sjc16_calib_2D(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1798 { 1799 switch ((*scPtr).shmooType) { 1800 case SHMOO_SJC16_RD_EN_FISH: 1801 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_BYTE, SHMOO_SJC16_CALIB_CENTER_PASS); 1802 case SHMOO_SJC16_RD_EXTENDED: 1803 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_BYTE, SHMOO_SJC16_CALIB_XY_AVERAGE); 1804 case SHMOO_SJC16_WR_EXTENDED: 1805 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_BYTE, SHMOO_SJC16_CALIB_XY_AVERAGE); 1806 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 1807 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD, SHMOO_SJC16_CALIB_CENTER_PASS); 1808 case SHMOO_SJC16_ADDR_EXTENDED: 1809 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD, SHMOO_SJC16_CALIB_CENTER_PASS); 1810 case SHMOO_SJC16_CTRL_EXTENDED: 1811 if(!SHMOO_SJC16_QUICK_SHMOO_CTRL_EXTENDED) 1812 { 1813 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD, SHMOO_SJC16_CALIB_CENTER_PASS); 1814 } 1815 break; 1816 case SHMOO_SJC16_RD_EN_FISH_ECC: 1817 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD, SHMOO_SJC16_CALIB_CENTER_PASS); 1818 case SHMOO_SJC16_RD_EXTENDED_ECC: 1819 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD, SHMOO_SJC16_CALIB_CENTER_PASS); 1820 case SHMOO_SJC16_WR_EXTENDED_ECC: 1821 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD, SHMOO_SJC16_CALIB_CENTER_PASS); 1822 default: 1823 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (*scPtr).shmooType)); 1824 return SOC_E_FAIL; 1825 } 1826 return SOC_E_NONE; 1827 } 1828 1829 STATIC int 1830 _shmoo_sjc16_set_new_step(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 1831 { 1832 uint32 calibMode; 1833 uint32 engageUIshift; 1834 uint32 MRfield0, MRfield1, MRfield2, MRfield3; 1835 uint32 data; 1836 sjc16_ui_position_t up; 1837 1838 calibMode = (*scPtr).calibMode; 1839 engageUIshift = (*scPtr).engageUIshift; 1840 1841 switch ((*scPtr).shmooType) { 1842 case SHMOO_SJC16_RD_EN_FISH: 1843 break; 1844 case SHMOO_SJC16_RD_EXTENDED: 1845 1846 switch(calibMode) 1847 { 1848 case SHMOO_SJC16_BIT: 1849 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 1850 (*scPtr).shmooType, calibMode)); 1851 return SOC_E_FAIL; 1852 case SHMOO_SJC16_BYTE: 1853 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 1854 1855 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 1856 1857 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1858 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1859 1860 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1861 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1862 1863 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[2] & 0xFFFF); 1864 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1865 1866 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[3] & 0xFFFF); 1867 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1868 1869 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1870 1871 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 1872 1873 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1874 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1875 1876 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1877 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1878 1879 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[2] & 0xFFFF); 1880 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1881 1882 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[3] & 0xFFFF); 1883 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1884 1885 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, &data)); 1886 1887 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[0] >> 16) & 0xFFFF) << 1); 1888 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 1889 1890 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[1] >> 16) & 0xFFFF) << 1); 1891 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 1892 1893 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[2] >> 16) & 0xFFFF) << 1); 1894 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 1895 1896 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[3] >> 16) & 0xFFFF) << 1); 1897 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 1898 1899 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1900 break; 1901 case SHMOO_SJC16_HALFWORD: 1902 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 1903 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 1904 1905 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1906 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1907 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1908 1909 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1910 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1911 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1912 1913 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1914 1915 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 1916 1917 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1918 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1919 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1920 1921 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1922 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1923 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1924 1925 1926 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, &data)); 1927 1928 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[0] >> 16) & 0xFFFF) << 1); 1929 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 1930 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 1931 1932 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[1] >> 16) & 0xFFFF) << 1); 1933 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 1934 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 1935 1936 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1937 break; 1938 case SHMOO_SJC16_WORD: 1939 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 1940 1941 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 1942 1943 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1944 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1945 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1946 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1947 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1948 1949 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1950 1951 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 1952 1953 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1954 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1955 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1956 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1957 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 1958 1959 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, &data)); 1960 1961 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[0] >> 16) & 0xFFFF) << 1); 1962 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 1963 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 1964 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 1965 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 1966 1967 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1968 break; 1969 default: 1970 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 1971 (*scPtr).shmooType, calibMode)); 1972 return SOC_E_FAIL; 1973 } 1974 1975 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 1976 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 1977 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 1978 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 1979 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 1980 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 1981 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 1982 1983 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 1984 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 1985 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 1986 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 1987 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 1988 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 1989 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 1990 1991 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 1992 1993 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 1994 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 1995 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 1996 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 1997 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 1998 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 1999 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 2000 2001 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2002 2003 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 2004 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 2005 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 2006 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 2007 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 2008 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 2009 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 2010 2011 break; 2012 case SHMOO_SJC16_WR_EXTENDED: 2013 switch(calibMode) 2014 { 2015 case SHMOO_SJC16_BIT: 2016 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2017 (*scPtr).shmooType, calibMode)); 2018 return SOC_E_FAIL; 2019 case SHMOO_SJC16_BYTE: 2020 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, &data)); 2021 2022 if(engageUIshift) 2023 { 2024 _calculate_ui_position((*scPtr).resultData[0] & 0xFFFF, scPtr, &up); 2025 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2026 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2027 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 2028 2029 _calculate_ui_position((*scPtr).resultData[1] & 0xFFFF, scPtr, &up); 2030 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2031 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2032 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 2033 2034 _calculate_ui_position((*scPtr).resultData[2] & 0xFFFF, scPtr, &up); 2035 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2036 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2037 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 2038 2039 _calculate_ui_position((*scPtr).resultData[3] & 0xFFFF, scPtr, &up); 2040 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2041 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2042 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 2043 } 2044 else 2045 { 2046 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2047 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 2048 2049 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 2050 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 2051 2052 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[2] & 0xFFFF); 2053 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 2054 2055 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[3] & 0xFFFF); 2056 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 2057 } 2058 2059 MRfield0 = ((*scPtr).resultData[0] >> 16) & 0xFFFF; 2060 MRfield1 = ((*scPtr).resultData[1] >> 16) & 0xFFFF; 2061 MRfield2 = ((*scPtr).resultData[2] >> 16) & 0xFFFF; 2062 MRfield3 = ((*scPtr).resultData[3] >> 16) & 0xFFFF; 2063 2064 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REGr(unit, MRfield0)); 2065 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REGr(unit, MRfield1)); 2066 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REGr(unit, MRfield2)); 2067 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REGr(unit, MRfield3)); 2068 2069 MRfield0 = (MRfield0 + MRfield1 + MRfield2 + MRfield3) >> 2; 2070 2071 if(MRfield0 > SHMOO_SJC16_DDR4_VREF_RANGE_CROSSOVER) 2072 { /* Vref Range 1 */ 2073 MRfield0 = MRfield0 - 23; 2074 } 2075 else 2076 { /* Vref Range 2 */ 2077 MRfield0 = MRfield0 | 0x40; 2078 } 2079 _write_mr(6, MRfield0, 0x7F); 2080 2081 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2082 break; 2083 case SHMOO_SJC16_HALFWORD: 2084 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, &data)); 2085 2086 if(engageUIshift) 2087 { 2088 _calculate_ui_position((*scPtr).resultData[0] & 0xFFFF, scPtr, &up); 2089 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2090 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2091 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 2092 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 2093 2094 _calculate_ui_position((*scPtr).resultData[1] & 0xFFFF, scPtr, &up); 2095 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2096 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2097 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 2098 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 2099 } 2100 else 2101 { 2102 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2103 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 2104 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 2105 2106 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 2107 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 2108 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 2109 } 2110 2111 MRfield0 = ((*scPtr).resultData[0] >> 16) & 0xFFFF; 2112 MRfield2 = ((*scPtr).resultData[1] >> 16) & 0xFFFF; 2113 2114 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REGr(unit, MRfield0)); 2115 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REGr(unit, MRfield0)); 2116 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REGr(unit, MRfield2)); 2117 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REGr(unit, MRfield2)); 2118 2119 MRfield0 = (MRfield0 + MRfield2) >> 1; 2120 2121 if(MRfield0 > SHMOO_SJC16_DDR4_VREF_RANGE_CROSSOVER) 2122 { /* Vref Range 1 */ 2123 MRfield0 = MRfield0 - 23; 2124 } 2125 else 2126 { /* Vref Range 2 */ 2127 MRfield0 = MRfield0 | 0x40; 2128 } 2129 _write_mr(6, MRfield0, 0x7F); 2130 2131 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2132 break; 2133 case SHMOO_SJC16_WORD: 2134 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, &data)); 2135 if(engageUIshift) 2136 { 2137 _calculate_ui_position((*scPtr).resultData[0] & 0xFFFF, scPtr, &up); 2138 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2139 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2140 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 2141 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 2142 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 2143 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 2144 } 2145 else 2146 { 2147 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2148 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 2149 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 2150 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 2151 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 2152 } 2153 2154 MRfield0 = ((*scPtr).resultData[0] >> 16) & 0xFFFF; 2155 2156 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REGr(unit, MRfield0)); 2157 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REGr(unit, MRfield0)); 2158 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REGr(unit, MRfield0)); 2159 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REGr(unit, MRfield0)); 2160 2161 if(MRfield0 > SHMOO_SJC16_DDR4_VREF_RANGE_CROSSOVER) 2162 { /* Vref Range 1 */ 2163 MRfield0 = MRfield0 - 23; 2164 } 2165 else 2166 { /* Vref Range 2 */ 2167 MRfield0 = MRfield0 | 0x40; 2168 } 2169 _write_mr(6, MRfield0, 0x7F); 2170 2171 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2172 break; 2173 default: 2174 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2175 (*scPtr).shmooType, calibMode)); 2176 return SOC_E_FAIL; 2177 } 2178 break; 2179 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 2180 switch(calibMode) 2181 { 2182 case SHMOO_SJC16_BIT: 2183 case SHMOO_SJC16_BYTE: 2184 case SHMOO_SJC16_HALFWORD: 2185 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2186 (*scPtr).shmooType, calibMode)); 2187 return SOC_E_FAIL; 2188 case SHMOO_SJC16_WORD: 2189 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, &data)); 2190 2191 if(engageUIshift) 2192 { 2193 _calculate_addr_ui_position((*scPtr).resultData[0] & 0xFFFF, scPtr, &up); 2194 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, UI_SHIFT, up.ui); 2195 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, up.position); 2196 } 2197 else 2198 { 2199 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2200 } 2201 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, data)); 2202 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, data)); 2203 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, data)); 2204 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, data)); 2205 2206 #if defined(CONFIG_HELIX5) 2207 _reset_dram(scPtr); 2208 #endif 2209 2210 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2211 break; 2212 default: 2213 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2214 (*scPtr).shmooType, calibMode)); 2215 return SOC_E_FAIL; 2216 } 2217 break; 2218 case SHMOO_SJC16_ADDR_EXTENDED: 2219 switch(calibMode) 2220 { 2221 case SHMOO_SJC16_BIT: 2222 case SHMOO_SJC16_BYTE: 2223 case SHMOO_SJC16_HALFWORD: 2224 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2225 (*scPtr).shmooType, calibMode)); 2226 return SOC_E_FAIL; 2227 case SHMOO_SJC16_WORD: 2228 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, &data)); 2229 2230 if(engageUIshift) 2231 { 2232 _calculate_addr_ui_position((*scPtr).resultData[0] & 0xFFFF, scPtr, &up); 2233 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, UI_SHIFT, up.ui); 2234 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, up.position); 2235 } 2236 else 2237 { 2238 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2239 } 2240 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, data)); 2241 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, data)); 2242 2243 #if defined(CONFIG_HELIX5) 2244 _reset_dram(scPtr); 2245 #endif 2246 2247 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2248 break; 2249 default: 2250 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2251 (*scPtr).shmooType, calibMode)); 2252 return SOC_E_FAIL; 2253 } 2254 break; 2255 case SHMOO_SJC16_CTRL_EXTENDED: 2256 if(SHMOO_SJC16_QUICK_SHMOO_CTRL_EXTENDED) 2257 { 2258 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2259 } 2260 else 2261 { 2262 switch(calibMode) 2263 { 2264 case SHMOO_SJC16_BIT: 2265 case SHMOO_SJC16_BYTE: 2266 case SHMOO_SJC16_HALFWORD: 2267 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2268 (*scPtr).shmooType, calibMode)); 2269 return SOC_E_FAIL; 2270 case SHMOO_SJC16_WORD: 2271 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, &data)); 2272 if(engageUIshift) 2273 { 2274 _calculate_addr_ui_position((*scPtr).resultData[0] & 0xFFFF, scPtr, &up); 2275 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_CTRL, UI_SHIFT, up.ui); 2276 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_CTRL, MAX_VDL_STEP, up.position); 2277 } 2278 else 2279 { 2280 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2281 } 2282 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, data)); 2283 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, data)); 2284 2285 #if defined(CONFIG_HELIX5) 2286 _reset_dram(scPtr); 2287 #endif 2288 2289 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2290 break; 2291 default: 2292 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2293 (*scPtr).shmooType, calibMode)); 2294 return SOC_E_FAIL; 2295 } 2296 } 2297 break; 2298 case SHMOO_SJC16_RD_EN_FISH_ECC: 2299 break; 2300 case SHMOO_SJC16_RD_EXTENDED_ECC: 2301 switch(calibMode) 2302 { 2303 case SHMOO_SJC16_BIT: 2304 case SHMOO_SJC16_BYTE: 2305 case SHMOO_SJC16_HALFWORD: 2306 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2307 (*scPtr).shmooType, calibMode)); 2308 return SOC_E_FAIL; 2309 case SHMOO_SJC16_WORD: 2310 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 2311 2312 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 2313 2314 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2315 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 2316 2317 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2318 2319 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 2320 2321 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2322 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 2323 2324 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, &data)); 2325 2326 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, VREF_DAC_CONFIG, DATA, (((*scPtr).resultData[0] >> 16) & 0xFFFF) << 1); 2327 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, data)); 2328 2329 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2330 break; 2331 default: 2332 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2333 (*scPtr).shmooType, calibMode)); 2334 return SOC_E_FAIL; 2335 } 2336 2337 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 2338 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 2339 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 2340 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 2341 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 2342 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 2343 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 2344 2345 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 2346 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 2347 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 2348 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 2349 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 2350 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 2351 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 2352 2353 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2354 2355 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 2356 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 2357 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 2358 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 2359 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 2360 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 2361 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 2362 2363 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2364 2365 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 2366 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 2367 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 2368 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 2369 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 2370 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 2371 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 2372 2373 break; 2374 case SHMOO_SJC16_WR_EXTENDED_ECC: 2375 switch(calibMode) 2376 { 2377 case SHMOO_SJC16_BIT: 2378 case SHMOO_SJC16_BYTE: 2379 case SHMOO_SJC16_HALFWORD: 2380 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2381 (*scPtr).shmooType, calibMode)); 2382 return SOC_E_FAIL; 2383 case SHMOO_SJC16_WORD: 2384 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, &data)); 2385 if(engageUIshift) 2386 { 2387 _calculate_ui_position((*scPtr).resultData[0] & 0xFFFF, scPtr, &up); 2388 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, WRITE_MAX_VDL_DATA, UI_SHIFT, up.ui); 2389 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, up.position); 2390 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, data)); 2391 } 2392 else 2393 { 2394 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2395 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, data)); 2396 } 2397 2398 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2399 break; 2400 default: 2401 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n"), 2402 (*scPtr).shmooType, calibMode)); 2403 return SOC_E_FAIL; 2404 } 2405 break; 2406 default: 2407 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (*scPtr).shmooType)); 2408 return SOC_E_FAIL; 2409 } 2410 2411 data = 0; 2412 2413 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2414 2415 return SOC_E_NONE; 2416 } 2417 2418 STATIC int 2419 _plot(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr, uint32 plotMode) 2420 { 2421 uint32 x; 2422 uint32 y; 2423 uint32 xStart; 2424 uint32 sizeX; 2425 uint32 sizeY; 2426 uint32 yCapMin; 2427 uint32 yCapMax; 2428 uint32 yJump; 2429 uint32 i; 2430 uint32 ui; 2431 uint32 iter; 2432 uint32 shiftAmount; 2433 uint32 dataMask; 2434 uint32 calibMode; 2435 uint32 calibPos; 2436 uint32 calibStart; 2437 uint32 engageUIshift; 2438 uint32 step1000; 2439 uint32 size1000UI; 2440 uint32 calibShiftAmount; 2441 uint32 maxMidPointX; 2442 uint32 maxMidPointY; 2443 char str0[SHMOO_SJC16_STRING_LENGTH]; 2444 char str1[SHMOO_SJC16_STRING_LENGTH]; 2445 char str2[SHMOO_SJC16_STRING_LENGTH]; 2446 char pass_low[2]; 2447 char fail_high[2]; 2448 char outOfSearch[2]; 2449 2450 outOfSearch[0] = ' '; 2451 outOfSearch[1] = 0; 2452 2453 sizeX = (*scPtr).sizeX; 2454 sizeY = (*scPtr).sizeY; 2455 yCapMin = (*scPtr).yCapMin; 2456 yCapMax = (*scPtr).yCapMax; 2457 yJump = (*scPtr).yJump; 2458 calibMode = (*scPtr).calibMode; 2459 calibPos = (*scPtr).calibPos; 2460 calibStart = (*scPtr).calibStart; 2461 engageUIshift = (*scPtr).engageUIshift; 2462 step1000 = (*scPtr).step1000; 2463 size1000UI = (*scPtr).size1000UI; 2464 2465 switch (calibPos) { 2466 case SHMOO_SJC16_CALIB_RISING_EDGE: 2467 case SHMOO_SJC16_CALIB_FALLING_EDGE: 2468 pass_low[0] = '_'; 2469 pass_low[1] = 0; 2470 fail_high[0] = '|'; 2471 fail_high[1] = 0; 2472 break; 2473 case SHMOO_SJC16_CALIB_CENTER_PASS: 2474 case SHMOO_SJC16_CALIB_PASS_START: 2475 case SHMOO_SJC16_CALIB_FAIL_START: 2476 case SHMOO_SJC16_CALIB_VDL_ZERO: 2477 case SHMOO_SJC16_CALIB_XY_AVERAGE: 2478 pass_low[0] = '+'; 2479 pass_low[1] = 0; 2480 fail_high[0] = '-'; 2481 fail_high[1] = 0; 2482 break; 2483 default: 2484 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration position: %02u\n"), calibPos)); 2485 return SOC_E_FAIL; 2486 } 2487 2488 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n\n"))); 2489 2490 switch(plotMode) 2491 { 2492 case SHMOO_SJC16_BIT: 2493 iter = shmoo_dram_info.interface_bitwidth; 2494 shiftAmount = 0; 2495 dataMask = 0x1; 2496 switch(calibMode) 2497 { 2498 case SHMOO_SJC16_BIT: 2499 calibShiftAmount = 0; 2500 break; 2501 case SHMOO_SJC16_BYTE: 2502 calibShiftAmount = 3; 2503 break; 2504 case SHMOO_SJC16_HALFWORD: 2505 calibShiftAmount = 4; 2506 break; 2507 case SHMOO_SJC16_WORD: 2508 calibShiftAmount = 5; 2509 break; 2510 default: 2511 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02u\n"), calibMode)); 2512 return SOC_E_FAIL; 2513 } 2514 break; 2515 case SHMOO_SJC16_BYTE: 2516 iter = shmoo_dram_info.interface_bitwidth >> 3; 2517 shiftAmount = 3; 2518 dataMask = 0xFF; 2519 switch(calibMode) 2520 { 2521 case SHMOO_SJC16_BIT: 2522 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from byte mode to bit mode\n"))); 2523 iter = shmoo_dram_info.interface_bitwidth; 2524 shiftAmount = 0; 2525 dataMask = 0x1; 2526 calibShiftAmount = 0; 2527 break; 2528 case SHMOO_SJC16_BYTE: 2529 calibShiftAmount = 0; 2530 break; 2531 case SHMOO_SJC16_HALFWORD: 2532 calibShiftAmount = 1; 2533 break; 2534 case SHMOO_SJC16_WORD: 2535 calibShiftAmount = 2; 2536 break; 2537 default: 2538 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02u\n"), calibMode)); 2539 return SOC_E_FAIL; 2540 } 2541 break; 2542 case SHMOO_SJC16_HALFWORD: 2543 iter = shmoo_dram_info.interface_bitwidth >> 4; 2544 shiftAmount = 4; 2545 dataMask = 0xFFFF; 2546 switch(calibMode) 2547 { 2548 case SHMOO_SJC16_BIT: 2549 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from halfword mode to bit mode\n"))); 2550 iter = 32; 2551 shiftAmount = 0; 2552 dataMask = 0x1; 2553 calibShiftAmount = 0; 2554 break; 2555 case SHMOO_SJC16_BYTE: 2556 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from halfword mode to byte mode\n"))); 2557 iter = 4; 2558 shiftAmount = 3; 2559 dataMask = 0xFF; 2560 calibShiftAmount = 0; 2561 break; 2562 case SHMOO_SJC16_HALFWORD: 2563 calibShiftAmount = 0; 2564 break; 2565 case SHMOO_SJC16_WORD: 2566 calibShiftAmount = 1; 2567 break; 2568 default: 2569 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02u\n"), calibMode)); 2570 return SOC_E_FAIL; 2571 } 2572 break; 2573 case SHMOO_SJC16_WORD: 2574 iter = 1; 2575 shiftAmount = 5; 2576 dataMask = 0xFFFFFFFF; 2577 switch(calibMode) 2578 { 2579 case SHMOO_SJC16_BIT: 2580 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from word mode to bit mode\n"))); 2581 iter = 32; 2582 shiftAmount = 0; 2583 dataMask = 0x1; 2584 calibShiftAmount = 0; 2585 break; 2586 case SHMOO_SJC16_BYTE: 2587 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from word mode to byte mode\n"))); 2588 iter = 4; 2589 shiftAmount = 3; 2590 dataMask = 0xFF; 2591 calibShiftAmount = 0; 2592 break; 2593 case SHMOO_SJC16_HALFWORD: 2594 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from word mode to halfword mode\n"))); 2595 iter = 2; 2596 shiftAmount = 4; 2597 dataMask = 0xFFFF; 2598 calibShiftAmount = 0; 2599 break; 2600 case SHMOO_SJC16_WORD: 2601 calibShiftAmount = 0; 2602 break; 2603 default: 2604 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02u\n"), calibMode)); 2605 return SOC_E_FAIL; 2606 } 2607 break; 2608 default: 2609 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported plot mode: %02u\n"), plotMode)); 2610 return SOC_E_FAIL; 2611 } 2612 /* 2613 if(engageUIshift) 2614 { */ 2615 ui = 0; 2616 2617 for(x = 0; x < sizeX; x++) 2618 { 2619 if((ui < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT) && (x > (*scPtr).endUI[ui])) 2620 { 2621 str0[x] = ' '; 2622 str1[x] = ' '; 2623 str2[x] = ' '; 2624 ui++; 2625 } 2626 else 2627 { 2628 str0[x] = '0' + (x / 100); 2629 str1[x] = '0' + ((x % 100) / 10); 2630 str2[x] = '0' + (x % 10); 2631 } 2632 } 2633 /* } 2634 else 2635 { 2636 for(x = 0; x < sizeX; x++) 2637 { 2638 str0[x] = '0' + (x / 100); 2639 str1[x] = '0' + ((x % 100) / 10); 2640 str2[x] = '0' + (x % 10); 2641 } 2642 } */ 2643 2644 str0[x] = 0; 2645 str1[x] = 0; 2646 str2[x] = 0; 2647 2648 for(i = 0; i < iter; i++) 2649 { 2650 xStart = 0; 2651 maxMidPointX = (*scPtr).resultData[i >> calibShiftAmount] & 0xFFFF; 2652 maxMidPointY = ((*scPtr).resultData[i >> calibShiftAmount] >> 16) & 0xFFFF; 2653 2654 if((sizeY > 1) || (i == 0)) 2655 { 2656 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "***** Interface.......: %3d\n"), phy_ndx)); 2657 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** VDL step size...: %3u.%03u ps\n"), 2658 (step1000 / 1000), (step1000 % 1000))); 2659 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** UI size.........: %3u.%03u steps\n"), 2660 (size1000UI / 1000), (size1000UI % 1000))); 2661 2662 switch((*scPtr).shmooType) 2663 { 2664 case SHMOO_SJC16_RD_EXTENDED: 2665 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: RD_EXTENDED\n"))); 2666 break; 2667 case SHMOO_SJC16_WR_EXTENDED: 2668 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: WR_EXTENDED\n"))); 2669 break; 2670 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 2671 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: ADDR_CTRL_EXTENDED\n"))); 2672 break; 2673 case SHMOO_SJC16_ADDR_EXTENDED: 2674 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: ADDR_EXTENDED\n"))); 2675 break; 2676 case SHMOO_SJC16_CTRL_EXTENDED: 2677 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: CTRL_EXTENDED\n"))); 2678 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Quick Shmoo.....: Off\n"))); 2679 break; 2680 case SHMOO_SJC16_RD_EXTENDED_ECC: 2681 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: RD_EXTENDED_ECC\n"))); 2682 break; 2683 case SHMOO_SJC16_WR_EXTENDED_ECC: 2684 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: WR_EXTENDED_ECC\n"))); 2685 break; 2686 default: 2687 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (*scPtr).shmooType)); 2688 return SOC_E_FAIL; 2689 } 2690 2691 if(engageUIshift) 2692 { 2693 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** UI shift........: On\n"))); 2694 } 2695 else 2696 { 2697 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** UI shift........: Off or N/A\n"))); 2698 } 2699 } 2700 2701 if(sizeY > 1) 2702 { 2703 switch(calibMode) 2704 { 2705 case SHMOO_SJC16_BIT: 2706 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Bit-wise\n"))); 2707 break; 2708 case SHMOO_SJC16_BYTE: 2709 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Byte-wise\n"))); 2710 break; 2711 case SHMOO_SJC16_HALFWORD: 2712 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Halfword-wise\n"))); 2713 break; 2714 case SHMOO_SJC16_WORD: 2715 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Word-wise\n"))); 2716 break; 2717 default: 2718 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02u\n"), calibMode)); 2719 return SOC_E_FAIL; 2720 } 2721 2722 switch(plotMode) 2723 { 2724 case SHMOO_SJC16_BIT: 2725 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Bit-wise\n"))); 2726 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Bit.............: %03u\n"), i)); 2727 break; 2728 case SHMOO_SJC16_BYTE: 2729 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Byte-wise\n"))); 2730 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Byte............: %03u\n"), i)); 2731 break; 2732 case SHMOO_SJC16_HALFWORD: 2733 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Halfword-wise\n"))); 2734 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Halfword........: %03u\n"), i)); 2735 break; 2736 case SHMOO_SJC16_WORD: 2737 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Word-wise\n"))); 2738 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Word............: %03u\n"), i)); 2739 break; 2740 default: 2741 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported plot mode: %02u\n"), plotMode)); 2742 return SOC_E_FAIL; 2743 } 2744 2745 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " * Center X........: %03u\n"), maxMidPointX)); 2746 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " * Center Y........: %03u\n"), maxMidPointY)); 2747 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str0)); 2748 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str1)); 2749 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str2)); 2750 2751 for(y = yCapMin; y < yCapMax; y++) 2752 { 2753 2754 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %03u "), y << yJump)); 2755 2756 for(x = 0; x < calibStart; x++) 2757 { 2758 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), outOfSearch)); 2759 } 2760 2761 for(x = calibStart; x < sizeX; x++) 2762 { 2763 if(((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask) 2764 { /* FAIL - RISING EDGE */ 2765 if(x != maxMidPointX) 2766 { /* REGULAR FAIL */ 2767 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2768 } 2769 else 2770 { /* FAIL - RISING EDGE */ 2771 if((calibPos == SHMOO_SJC16_CALIB_RISING_EDGE) || (calibPos == SHMOO_SJC16_CALIB_FAIL_START)) 2772 { /* RISING EDGE */ 2773 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2774 } 2775 else 2776 { /* FAIL */ 2777 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2778 } 2779 } 2780 } 2781 else 2782 { /* PASS - MIDPOINT - FALLING EDGE */ 2783 if(x != maxMidPointX) 2784 { /* REGULAR PASS */ 2785 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), pass_low)); 2786 } 2787 else 2788 { /* POTENTIAL MIDPOINT - FALLING EDGE */ 2789 if(y == maxMidPointY) 2790 { /* MID POINT - FALLING EDGE */ 2791 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2792 } 2793 else 2794 { /* PASS */ 2795 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), pass_low)); 2796 } 2797 } 2798 } 2799 } 2800 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2801 xStart += sizeX; 2802 } 2803 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2804 } 2805 else 2806 { 2807 if(i == 0) 2808 { 2809 switch(calibMode) 2810 { 2811 case SHMOO_SJC16_BIT: 2812 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Bit-wise\n"))); 2813 break; 2814 case SHMOO_SJC16_BYTE: 2815 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Byte-wise\n"))); 2816 break; 2817 case SHMOO_SJC16_HALFWORD: 2818 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Halfword-wise\n"))); 2819 break; 2820 case SHMOO_SJC16_WORD: 2821 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Word-wise\n"))); 2822 break; 2823 default: 2824 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02u\n"), calibMode)); 2825 return SOC_E_FAIL; 2826 } 2827 2828 switch(plotMode) 2829 { 2830 case SHMOO_SJC16_BIT: 2831 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Bit-wise\n"))); 2832 break; 2833 case SHMOO_SJC16_BYTE: 2834 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Byte-wise\n"))); 2835 break; 2836 case SHMOO_SJC16_HALFWORD: 2837 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Halfword-wise\n"))); 2838 break; 2839 case SHMOO_SJC16_WORD: 2840 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Word-wise\n"))); 2841 break; 2842 default: 2843 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported plot mode: %02u\n"), plotMode)); 2844 return SOC_E_FAIL; 2845 } 2846 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str0)); 2847 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str1)); 2848 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str2)); 2849 } 2850 2851 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %03u "), i)); 2852 2853 for(x = 0; x < calibStart; x++) 2854 { 2855 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), outOfSearch)); 2856 } 2857 2858 for(x = calibStart; x < sizeX; x++) 2859 { 2860 if(((*scPtr).result2D[x] >> (i << shiftAmount)) & dataMask) 2861 { /* FAIL - RISING EDGE */ 2862 if(x != maxMidPointX) 2863 { /* REGULAR FAIL */ 2864 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2865 } 2866 else 2867 { /* FAIL - RISING EDGE */ 2868 if((calibPos == SHMOO_SJC16_CALIB_RISING_EDGE) || (calibPos == SHMOO_SJC16_CALIB_FAIL_START)) 2869 { /* RISING EDGE */ 2870 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2871 } 2872 else 2873 { /* FAIL */ 2874 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2875 } 2876 } 2877 } 2878 else 2879 { /* PASS - MIDPOINT - FALLING EDGE */ 2880 if(x != maxMidPointX) 2881 { /* REGULAR PASS */ 2882 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), pass_low)); 2883 } 2884 else 2885 { /* MID POINT - FALLING EDGE */ 2886 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2887 } 2888 } 2889 } 2890 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2891 } 2892 } 2893 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2894 2895 return SOC_E_NONE; 2896 } 2897 2898 STATIC int 2899 _shmoo_sjc16_plot(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr) 2900 { 2901 switch ((*scPtr).shmooType) { 2902 case SHMOO_SJC16_RD_EN_FISH: 2903 break; 2904 case SHMOO_SJC16_RD_EXTENDED: 2905 return _plot(unit, phy_ndx, scPtr, SHMOO_SJC16_BYTE); 2906 case SHMOO_SJC16_WR_EXTENDED: 2907 return _plot(unit, phy_ndx, scPtr, SHMOO_SJC16_BYTE); 2908 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 2909 return _plot(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD); 2910 case SHMOO_SJC16_ADDR_EXTENDED: 2911 return _plot(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD); 2912 case SHMOO_SJC16_CTRL_EXTENDED: 2913 if(!SHMOO_SJC16_QUICK_SHMOO_CTRL_EXTENDED) 2914 { 2915 return _plot(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD); 2916 } 2917 else 2918 { 2919 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n\n"))); 2920 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "***** Interface.......: %3d\n"), phy_ndx)); 2921 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: CTRL_EXTENDED\n"))); 2922 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Quick Shmoo.....: On\n"))); 2923 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot............: Off\n"))); 2924 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Copying.........: VDL_STEP\n"))); 2925 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** From............: AD00 - AD09\n"))); 2926 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** To..............: AD10 - WE_N\n"))); 2927 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2928 } 2929 break; 2930 case SHMOO_SJC16_RD_EN_FISH_ECC: 2931 break; 2932 case SHMOO_SJC16_RD_EXTENDED_ECC: 2933 return _plot(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD); 2934 case SHMOO_SJC16_WR_EXTENDED_ECC: 2935 return _plot(unit, phy_ndx, scPtr, SHMOO_SJC16_WORD); 2936 default: 2937 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (*scPtr).shmooType)); 2938 return SOC_E_FAIL; 2939 } 2940 return SOC_E_NONE; 2941 } 2942 2943 int 2944 _sjc16_calculate_step_size(int unit, int phy_ndx, sjc16_step_size_t *ssPtr) 2945 { 2946 uint32 data; 2947 uint32 obs_interval, ro_vdl_step1, ro_vdl_step2, ucount1, ucount2; 2948 uint32 reset_ctrl_data; 2949 uint32 fld_dcount; 2950 uint32 fld_ro_overflow; 2951 uint32 timeout; 2952 2953 if(shmoo_dram_info.sim_system_mode) 2954 { 2955 (*ssPtr).step1000 = 1953; 2956 (*ssPtr).size1000UI = 128000; 2957 2958 return SOC_E_NONE; 2959 } 2960 2961 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 2962 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 2963 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 2964 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 2965 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 2966 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 2967 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 2968 2969 data = 0; 2970 obs_interval = 2000; 2971 ro_vdl_step1 = 128; 2972 ro_vdl_step2 = 256; 2973 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, OBS_INTERVAL, obs_interval); 2974 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, SEL_FC_REFCLK, 0); 2975 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 2976 2977 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2978 2979 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &reset_ctrl_data)); 2980 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_FC_RESET_N, 0); 2981 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_RO_RESET_N, 0); 2982 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 2983 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2984 2985 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, START_OBS, 0); 2986 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, EN_NLDL_CLKOUT_BAR, 0); 2987 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 2988 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2989 2990 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, RO_VDL_STEP, ro_vdl_step1); 2991 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 2992 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2993 2994 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, EN_NLDL_CLKOUT_BAR, 1); 2995 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 2996 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 2997 2998 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_FC_RESET_N, 1); 2999 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_RO_RESET_N, 1); 3000 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 3001 3002 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3003 3004 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, START_OBS, 1); 3005 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 3006 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3007 3008 timeout = 2000; 3009 do 3010 { 3011 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr(unit, &data)); 3012 3013 fld_dcount = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, STATUS_FREQ_CNTR_DCOUNT, DCOUNT); 3014 if(!fld_dcount) 3015 { 3016 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr(unit, &data)); 3017 fld_ro_overflow = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, STATUS_FREQ_CNTR_UCOUNT, RO_OVERFLOW); 3018 if(fld_ro_overflow & 0x4) 3019 { 3020 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "VDL step size computation rollover during first pass\n"))); 3021 return SOC_E_FAIL; 3022 } 3023 ucount1 = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, STATUS_FREQ_CNTR_UCOUNT, RO_UCOUNT); 3024 break; 3025 } 3026 3027 if(timeout == 0) 3028 { 3029 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Timed out waiting for first pass of VDL step size computation\n"))); 3030 return SOC_E_TIMEOUT; 3031 } 3032 3033 timeout--; 3034 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3035 } 3036 while(TRUE); 3037 3038 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_FC_RESET_N, 0); 3039 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_RO_RESET_N, 0); 3040 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 3041 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3042 3043 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, &data)); 3044 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, START_OBS, 0); 3045 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, EN_NLDL_CLKOUT_BAR, 0); 3046 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 3047 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3048 3049 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, RO_VDL_STEP, ro_vdl_step2); 3050 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 3051 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3052 3053 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, EN_NLDL_CLKOUT_BAR, 1); 3054 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 3055 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3056 3057 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_FC_RESET_N, 1); 3058 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_RO_RESET_N, 1); 3059 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 3060 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3061 3062 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, START_OBS, 1); 3063 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 3064 3065 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3066 3067 timeout = 2000; 3068 do 3069 { 3070 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr(unit, &data)); 3071 3072 fld_dcount = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, STATUS_FREQ_CNTR_DCOUNT, DCOUNT); 3073 if(!fld_dcount) 3074 { 3075 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr(unit, &data)); 3076 fld_ro_overflow = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, STATUS_FREQ_CNTR_UCOUNT, RO_OVERFLOW); 3077 if(fld_ro_overflow & 0x4) 3078 { 3079 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "VDL step size computation rollover during second pass\n"))); 3080 return SOC_E_FAIL; 3081 } 3082 ucount2 = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, STATUS_FREQ_CNTR_UCOUNT, RO_UCOUNT); 3083 break; 3084 } 3085 3086 if(timeout == 0) 3087 { 3088 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Timed out waiting for second pass of VDL step size computation\n"))); 3089 return SOC_E_TIMEOUT; 3090 } 3091 3092 timeout--; 3093 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3094 } 3095 while(TRUE); 3096 3097 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_FC_RESET_N, 0); 3098 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, FREQ_CNTR_RO_RESET_N, 0); 3099 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 3100 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3101 3102 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, &data)); 3103 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, START_OBS, 0); 3104 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, FREQ_CNTR_CONFIG, EN_NLDL_CLKOUT_BAR, 0); 3105 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, data)); 3106 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3107 3108 /* BEGIN: Adjustment */ 3109 (*ssPtr).step1000 = (((((((1140000000 << (0x1 & (shmoo_dram_info.dram_type != SHMOO_SJC16_DRAM_TYPE_DDR4))) / (ro_vdl_step2 - ro_vdl_step1)) << 3) / shmoo_dram_info.data_rate_mbps) * obs_interval) / ucount2) * (ucount1 - ucount2)) / ucount1; 3110 /* END: Adjustment */ 3111 (*ssPtr).size1000UI = (((1000000000 / shmoo_dram_info.data_rate_mbps) * 1000) / ((*ssPtr).step1000)) >> (0x1 & (shmoo_dram_info.dram_type == SHMOO_SJC16_DRAM_TYPE_DDR4)); 3112 3113 return SOC_E_NONE; 3114 } 3115 3116 int 3117 _sjc16_zq_calibration(int unit, int phy_ndx) 3118 { 3119 uint32 data; 3120 uint32 setting; 3121 uint32 error, status; 3122 uint32 timeout; 3123 uint32 fld_comp_done; 3124 uint32 temp1, temp2; 3125 uint32 dq_pd, dq_nd, dq_pterm, dq_nterm; 3126 uint32 aq_pd, aq_nd, aq_pterm, aq_nterm; 3127 3128 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, &data)); 3129 3130 setting = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, SHARED_VREF_DAC_CONFIG, DATA); 3131 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, SHARED_VREF_DAC_CONFIG, DATA, 0x42); 3132 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, data)); 3133 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3134 3135 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_COMMON_RESCAL_INIT_CONFIGr(unit, &data)); 3136 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, RESCAL_INIT_CONFIG, COMP_INIT_FDEPTH, 0xB); 3137 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, RESCAL_INIT_CONFIG, PNCOMP_INIT_DIFF, 0x1F); /* TEMPORARY */ 3138 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_RESCAL_INIT_CONFIGr(unit, data)); 3139 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3140 3141 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 3142 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RESCAL_RESET_N, 1); 3143 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 3144 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3145 3146 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIGr(unit, &data)); 3147 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, RESCAL_OPERATION_CONFIG, COMP_EN, 1); 3148 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIGr(unit, data)); 3149 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3150 3151 error = 0; 3152 status = 0; 3153 timeout = 2000; 3154 do 3155 { 3156 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_COMMON_STATUS_RESCALr(unit, &data)); 3157 3158 fld_comp_done = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_COMMON, STATUS_RESCAL, COMP_DONE); 3159 if(fld_comp_done) 3160 { 3161 status = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_COMMON, STATUS_RESCAL, COMP_ERROR); 3162 error = status & 0x1C; 3163 if(error) 3164 { 3165 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: ZQ calibration error - Manual IO programming may be required for correct operation\n"))); 3166 error |= 0x10020; 3167 } 3168 break; 3169 } 3170 3171 if(timeout == 0) 3172 { 3173 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Timed out waiting for ZQ calibration\n"))); 3174 return SOC_E_TIMEOUT; 3175 } 3176 3177 timeout--; 3178 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3179 } 3180 while(TRUE); 3181 3182 temp1 = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_COMMON, STATUS_RESCAL, PCOMP_CODE_2CORE); 3183 temp2 = DDR_PHY_GET_FIELD(data, SJC16_DDR4_PHY_COMMON, STATUS_RESCAL, NCOMP_CODE_2CORE); 3184 3185 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIGr(unit, &data)); 3186 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, RESCAL_OPERATION_CONFIG, COMP_EN, 0); 3187 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIGr(unit, data)); 3188 3189 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 3190 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RESCAL_RESET_N, 0); 3191 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 3192 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3193 3194 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, &data)); 3195 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, SHARED_VREF_DAC_CONFIG, DATA, setting); 3196 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, data)); 3197 3198 dq_pd = temp1; 3199 dq_nd = temp2; 3200 dq_pterm = temp1; 3201 dq_nterm = temp2; 3202 aq_pd = temp1; 3203 aq_nd = temp2; 3204 aq_pterm = temp1; 3205 aq_nterm = temp2; 3206 3207 if((dq_pd | dq_nd | dq_pterm | dq_nterm | aq_pd | aq_pterm | aq_nterm) & 0xFFFFFFE0) 3208 { 3209 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: ZQ calibration out of bounds - Manual IO programming may be required for correct operation\n"))); 3210 error |= 0x40000; 3211 } 3212 3213 if(error) 3214 { 3215 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Status Code......................: 0x%02X\n"), status)); 3216 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Pdrive.................: 0x%02X\n"), 0xFF & dq_pd)); 3217 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Ndrive.................: 0x%02X\n"), 0xFF & dq_nd)); 3218 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Ptermination...........: 0x%02X\n"), 0xFF & dq_pterm)); 3219 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Ntermination (RFU).....: 0x%02X\n"), 0xFF & dq_nterm)); 3220 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Pdrive........................: 0x%02X\n"), 0xFF & aq_pd)); 3221 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Ndrive........................: 0x%02X\n"), 0xFF & aq_nd)); 3222 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Ptermination..................: 0x%02X\n"), 0xFF & aq_pterm)); 3223 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Ntermination (RFU)............: 0x%02X\n"), 0xFF & aq_nterm)); 3224 3225 if(error & 0x40000) 3226 { 3227 dq_pd &= 0x1F; 3228 dq_nd &= 0x1F; 3229 dq_pterm &= 0x1F; 3230 dq_nterm &= 0x1F; 3231 aq_pd &= 0x1F; 3232 aq_nd &= 0x1F; 3233 aq_pterm &= 0x1F; 3234 aq_nterm &= 0x1F; 3235 } 3236 3237 /* return SOC_E_FAIL; */ 3238 } 3239 else 3240 { 3241 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Status Code......................: 0x%02X\n"), status)); 3242 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Pdrive.................: 0x%02X\n"), 0xFF & dq_pd)); 3243 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Ndrive.................: 0x%02X\n"), 0xFF & dq_nd)); 3244 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Ptermination...........: 0x%02X\n"), 0xFF & dq_pterm)); 3245 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DQ/DQS/CK Ntermination (RFU).....: 0x%02X\n"), 0xFF & dq_nterm)); 3246 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Pdrive........................: 0x%02X\n"), 0xFF & aq_pd)); 3247 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Ndrive........................: 0x%02X\n"), 0xFF & aq_nd)); 3248 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Ptermination..................: 0x%02X\n"), 0xFF & aq_pterm)); 3249 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "AQ Ntermination (RFU)............: 0x%02X\n"), 0xFF & aq_nterm)); 3250 } 3251 3252 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_COMMON_IO_CONFIGr(unit, &data)); 3253 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, PD, dq_pd); 3254 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, PTERM, dq_pterm); 3255 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, ND, dq_nd); 3256 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, NTERM, dq_nterm); 3257 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, PULL_UP_OFF_B, 0x0); 3258 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, RX_BIAS, 0x0); 3259 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, PEAK, 0x0); 3260 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, DEM, 0x0); 3261 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, IO_CONFIG, RXENB, 0x1); 3262 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_IO_CONFIGr(unit, data)); 3263 3264 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_IO_CONFIGr(unit, &data)); 3265 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, PD, aq_pd); 3266 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, PTERM, aq_pterm); 3267 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, ND, aq_nd); 3268 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, NTERM, aq_nterm); 3269 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, PULL_UP_OFF_B, 0x0); 3270 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, RX_BIAS, 0x0); 3271 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, PEAK, 0x0); 3272 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, DEM, 0x0); 3273 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, RXENB, 0x1); 3274 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, IO_CONFIG, RXENB_ALERT_N, 0x0); 3275 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_IO_CONFIGr(unit, data)); 3276 3277 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_SUPPLEMENT_IO_CONFIGr(unit, &data)); 3278 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, PD, aq_pd); 3279 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, PTERM, aq_pterm); 3280 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, ND, aq_nd); 3281 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, NTERM, aq_nterm); 3282 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, PULL_UP_OFF_B, 0x0); 3283 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, RX_BIAS, 0x0); 3284 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, PEAK, 0x0); 3285 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, DEM, 0x0); 3286 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, RXENB_ALERT_N_2, 0x0); 3287 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, RXENB_ALERT_N_3, 0x0); 3288 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_SUPPLEMENT, IO_CONFIG, RXENB_ALERT_N_4, 0x0); 3289 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_SUPPLEMENT_IO_CONFIGr(unit, data)); 3290 3291 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIGr(unit, &data)); 3292 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, PD, dq_pd); 3293 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, PTERM, dq_pterm); 3294 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, ND, dq_nd); 3295 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, NTERM, dq_nterm); 3296 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, PULL_UP_OFF_B, 0x0); 3297 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, RX_BIAS, 0x0); 3298 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, PEAK, 0x0); 3299 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, DEM, 0x0); 3300 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DATA_IO_CONFIG, RXENB, 0x0); 3301 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIGr(unit, data)); 3302 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIGr(unit, data)); 3303 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIGr(unit, data)); 3304 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIGr(unit, data)); 3305 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIGr(unit, data)); 3306 3307 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIGr(unit, &data)); 3308 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, PD, dq_pd); 3309 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, PTERM, dq_pterm); 3310 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, ND, dq_nd); 3311 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, NTERM, dq_nterm); 3312 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, PULL_UP_OFF_B, 0x0); 3313 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, RX_BIAS, 0x0); 3314 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, PEAK, 0x0); 3315 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, DEM, 0x0); 3316 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DQS_IO_CONFIG, RXENB, 0x0); 3317 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIGr(unit, data)); 3318 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIGr(unit, data)); 3319 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIGr(unit, data)); 3320 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIGr(unit, data)); 3321 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIGr(unit, data)); 3322 sal_usleep(SHMOO_SJC16_LONG_SLEEP); 3323 3324 return SOC_E_NONE; 3325 } 3326 3327 STATIC int 3328 _shmoo_sjc16_entry(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr, uint32 mode) 3329 { 3330 /* Mode 0: Sequential entry 3331 * Mode 1: Single entry 3332 */ 3333 3334 uint32 i; 3335 uint32 data, temp; 3336 sjc16_step_size_t ss; 3337 3338 (*scPtr).calibStart = 0; 3339 3340 switch ((*scPtr).shmooType) { 3341 case SHMOO_SJC16_RD_EN_FISH: 3342 data = 0; 3343 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_3, 0); 3344 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_2, 0); 3345 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_1, 0); 3346 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_0, 1); 3347 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_PLUS_1, 0); 3348 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_PLUS_2, 0); 3349 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3350 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3351 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3352 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3353 3354 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 3355 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 3356 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 3357 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 3358 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 3359 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 3360 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 3361 3362 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 3363 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 3364 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 3365 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 3366 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 3367 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 3368 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 3369 3370 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3371 3372 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 3373 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 3374 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 3375 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 3376 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 3377 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 3378 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 3379 3380 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3381 3382 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 3383 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 3384 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 3385 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 3386 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 3387 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 3388 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 3389 3390 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3391 3392 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3393 (*scPtr).step1000 = ss.step1000; 3394 (*scPtr).size1000UI = ss.size1000UI; 3395 3396 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3397 { 3398 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3399 } 3400 break; 3401 case SHMOO_SJC16_RD_EXTENDED: 3402 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3403 (*scPtr).step1000 = ss.step1000; 3404 (*scPtr).size1000UI = ss.size1000UI; 3405 temp = (ss.size1000UI * 125) / 100000; /* 125% */ 3406 if(temp > SHMOO_SJC16_MAX_VDL_LENGTH) 3407 { 3408 (*scPtr).sizeX = SHMOO_SJC16_MAX_VDL_LENGTH; 3409 } 3410 else 3411 { 3412 (*scPtr).sizeX = temp; 3413 } 3414 3415 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3416 { 3417 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3418 } 3419 break; 3420 case SHMOO_SJC16_WR_EXTENDED: 3421 _write_mr(6, 0x80, 0x80); 3422 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3423 3424 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3425 (*scPtr).step1000 = ss.step1000; 3426 (*scPtr).size1000UI = ss.size1000UI; 3427 temp = (ss.size1000UI * 125) / 100000; /* 125% */ 3428 if(temp > SHMOO_SJC16_MAX_VDL_LENGTH) 3429 { 3430 (*scPtr).sizeX = SHMOO_SJC16_MAX_VDL_LENGTH; 3431 } 3432 else 3433 { 3434 (*scPtr).sizeX = temp; 3435 } 3436 3437 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3438 { 3439 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3440 } 3441 break; 3442 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 3443 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3444 (*scPtr).step1000 = ss.step1000; 3445 (*scPtr).size1000UI = ss.size1000UI; 3446 temp = (ss.size1000UI * 25) / 10000; /* 250% */ 3447 if(temp > SHMOO_SJC16_MAX_VDL_LENGTH) 3448 { 3449 (*scPtr).sizeX = SHMOO_SJC16_MAX_VDL_LENGTH; 3450 } 3451 else 3452 { 3453 (*scPtr).sizeX = temp; 3454 } 3455 3456 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3457 { 3458 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3459 } 3460 break; 3461 case SHMOO_SJC16_ADDR_EXTENDED: 3462 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3463 (*scPtr).step1000 = ss.step1000; 3464 (*scPtr).size1000UI = ss.size1000UI; 3465 temp = (ss.size1000UI * 25) / 10000; /* 250% */ 3466 if(temp > SHMOO_SJC16_MAX_VDL_LENGTH) 3467 { 3468 (*scPtr).sizeX = SHMOO_SJC16_MAX_VDL_LENGTH; 3469 } 3470 else 3471 { 3472 (*scPtr).sizeX = temp; 3473 } 3474 3475 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3476 { 3477 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3478 } 3479 break; 3480 case SHMOO_SJC16_CTRL_EXTENDED: 3481 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3482 (*scPtr).step1000 = ss.step1000; 3483 (*scPtr).size1000UI = ss.size1000UI; 3484 temp = (ss.size1000UI * 25) / 10000; /* 250% */ 3485 if(temp > SHMOO_SJC16_MAX_VDL_LENGTH) 3486 { 3487 (*scPtr).sizeX = SHMOO_SJC16_MAX_VDL_LENGTH; 3488 } 3489 else 3490 { 3491 (*scPtr).sizeX = temp; 3492 } 3493 3494 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3495 { 3496 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3497 } 3498 break; 3499 case SHMOO_SJC16_RD_EN_FISH_ECC: 3500 /* iproc16_enable_ecc() */; 3501 3502 data = 0; 3503 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_MINUS_3, 0); 3504 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_MINUS_2, 0); 3505 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_MINUS_1, 0); 3506 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_0, 1); 3507 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_PLUS_1, 0); 3508 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_PLUS_2, 0); 3509 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3510 3511 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 3512 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 3513 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 3514 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 3515 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 3516 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 3517 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 3518 3519 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 3520 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 3521 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 3522 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 3523 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 3524 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 3525 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 3526 3527 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3528 3529 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 3530 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 3531 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 3532 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 3533 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 3534 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 3535 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 3536 3537 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3538 3539 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 3540 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 3541 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 3542 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 3543 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 3544 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 3545 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 3546 3547 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3548 3549 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3550 (*scPtr).step1000 = ss.step1000; 3551 (*scPtr).size1000UI = ss.size1000UI; 3552 3553 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3554 { 3555 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3556 } 3557 break; 3558 case SHMOO_SJC16_RD_EXTENDED_ECC: 3559 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3560 (*scPtr).step1000 = ss.step1000; 3561 (*scPtr).size1000UI = ss.size1000UI; 3562 temp = (ss.size1000UI * 125) / 100000; /* 125% */ 3563 if(temp > SHMOO_SJC16_MAX_VDL_LENGTH) 3564 { 3565 (*scPtr).sizeX = SHMOO_SJC16_MAX_VDL_LENGTH; 3566 } 3567 else 3568 { 3569 (*scPtr).sizeX = temp; 3570 } 3571 3572 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3573 { 3574 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3575 } 3576 break; 3577 case SHMOO_SJC16_WR_EXTENDED_ECC: 3578 _sjc16_calculate_step_size(unit, phy_ndx, &ss); 3579 (*scPtr).step1000 = ss.step1000; 3580 (*scPtr).size1000UI = ss.size1000UI; 3581 temp = (ss.size1000UI * 125) / 100000; /* 125% */ 3582 if(temp > SHMOO_SJC16_MAX_VDL_LENGTH) 3583 { 3584 (*scPtr).sizeX = SHMOO_SJC16_MAX_VDL_LENGTH; 3585 } 3586 else 3587 { 3588 (*scPtr).sizeX = temp; 3589 } 3590 3591 for(i = 0; i < SHMOO_SJC16_MAX_VISIBLE_UI_COUNT; i++) 3592 { 3593 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3594 } 3595 break; 3596 default: 3597 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (*scPtr).shmooType)); 3598 return SOC_E_FAIL; 3599 } 3600 return SOC_E_NONE; 3601 } 3602 3603 STATIC int 3604 _shmoo_sjc16_exit(int unit, int phy_ndx, sjc16_shmoo_container_t *scPtr, uint32 mode) 3605 { 3606 /* Mode 0: Sequential exit 3607 * Mode 1: Single exit 3608 */ 3609 3610 uint32 data; 3611 3612 switch ((*scPtr).shmooType) { 3613 case SHMOO_SJC16_RD_EN_FISH: 3614 data = 0; 3615 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_3, 0); 3616 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_2, 0); 3617 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_1, 1); 3618 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_0, 1); 3619 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_PLUS_1, 1); 3620 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_PLUS_2, 0); 3621 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3622 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3623 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3624 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3625 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3626 break; 3627 case SHMOO_SJC16_RD_EXTENDED: 3628 break; 3629 case SHMOO_SJC16_WR_EXTENDED: 3630 _write_mr(6, 0x00, 0x80); 3631 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3632 break; 3633 case SHMOO_SJC16_ADDR_CTRL_EXTENDED: 3634 break; 3635 case SHMOO_SJC16_ADDR_EXTENDED: 3636 break; 3637 case SHMOO_SJC16_CTRL_EXTENDED: 3638 break; 3639 case SHMOO_SJC16_RD_EN_FISH_ECC: 3640 data = 0; 3641 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_MINUS_3, 0); 3642 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_MINUS_2, 0); 3643 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_MINUS_1, 1); 3644 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_0, 1); 3645 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_PLUS_1, 1); 3646 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, DDR4_REN_STRETCH_CONFIG, A_PLUS_2, 0); 3647 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIGr(unit, data)); 3648 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 3649 break; 3650 case SHMOO_SJC16_RD_EXTENDED_ECC: 3651 break; 3652 case SHMOO_SJC16_WR_EXTENDED_ECC: 3653 break; 3654 default: 3655 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02u\n"), (*scPtr).shmooType)); 3656 return SOC_E_FAIL; 3657 } 3658 3659 return SOC_E_NONE; 3660 } 3661 3662 STATIC int 3663 _shmoo_sjc16_save(int unit, int phy_ndx, sjc16_shmoo_config_param_t *config_param) 3664 { 3665 uint32 data; 3666 3667 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0r(unit, &data)); 3668 (*config_param).dq_byte_wr_min_vdl_bit[0][0] = (uint8) data; 3669 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1r(unit, &data)); 3670 (*config_param).dq_byte_wr_min_vdl_bit[0][1] = (uint8) data; 3671 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2r(unit, &data)); 3672 (*config_param).dq_byte_wr_min_vdl_bit[0][2] = (uint8) data; 3673 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3r(unit, &data)); 3674 (*config_param).dq_byte_wr_min_vdl_bit[0][3] = (uint8) data; 3675 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4r(unit, &data)); 3676 (*config_param).dq_byte_wr_min_vdl_bit[0][4] = (uint8) data; 3677 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5r(unit, &data)); 3678 (*config_param).dq_byte_wr_min_vdl_bit[0][5] = (uint8) data; 3679 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6r(unit, &data)); 3680 (*config_param).dq_byte_wr_min_vdl_bit[0][6] = (uint8) data; 3681 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7r(unit, &data)); 3682 (*config_param).dq_byte_wr_min_vdl_bit[0][7] = (uint8) data; 3683 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBIr(unit, &data)); 3684 (*config_param).dq_byte_wr_min_vdl_dbi[0] = (uint8) data; 3685 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDCr(unit, &data)); 3686 (*config_param).dq_byte_wr_min_vdl_edc[0] = (uint8) data; 3687 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, &data)); 3688 (*config_param).dq_byte_wr_max_vdl_data[0] = data; 3689 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, &data)); 3690 (*config_param).dq_byte_wr_max_vdl_dqs[0] = data; 3691 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0r(unit, &data)); 3692 (*config_param).dq_byte_rd_min_vdl_bit[0][0] = (uint8) data; 3693 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1r(unit, &data)); 3694 (*config_param).dq_byte_rd_min_vdl_bit[0][1] = (uint8) data; 3695 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2r(unit, &data)); 3696 (*config_param).dq_byte_rd_min_vdl_bit[0][2] = (uint8) data; 3697 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3r(unit, &data)); 3698 (*config_param).dq_byte_rd_min_vdl_bit[0][3] = (uint8) data; 3699 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4r(unit, &data)); 3700 (*config_param).dq_byte_rd_min_vdl_bit[0][4] = (uint8) data; 3701 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5r(unit, &data)); 3702 (*config_param).dq_byte_rd_min_vdl_bit[0][5] = (uint8) data; 3703 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6r(unit, &data)); 3704 (*config_param).dq_byte_rd_min_vdl_bit[0][6] = (uint8) data; 3705 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7r(unit, &data)); 3706 (*config_param).dq_byte_rd_min_vdl_bit[0][7] = (uint8) data; 3707 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBIr(unit, &data)); 3708 (*config_param).dq_byte_rd_min_vdl_dbi[0] = (uint8) data; 3709 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDCr(unit, &data)); 3710 (*config_param).dq_byte_rd_min_vdl_edc[0] = (uint8) data; 3711 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 3712 (*config_param).dq_byte_rd_max_vdl_dqsp[0] = data; 3713 /* READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDNr(unit, &data)); */ 3714 (*config_param).dq_byte_rd_max_vdl_dqsn[0] = data; 3715 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIGr(unit, &data)); 3716 (*config_param).dq_byte_ren_fifo_config[0] = data; 3717 /* READ_DDR4_PHY_DQ_BYTE0_EDCEN_FIFO_CONFIGr(unit, &data)); */ 3718 (*config_param).dq_byte_edcen_fifo_config[0] = data; 3719 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSMr(unit, &data)); 3720 (*config_param).dq_byte_rd_max_vdl_fsm[0] = data; 3721 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, &data)); 3722 (*config_param).dq_byte_vref_dac_config[0] = data; 3723 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REGr(unit, &data)); 3724 (*config_param).dq_byte_macro_reserved_reg[0] = data; 3725 3726 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0r(unit, &data)); 3727 (*config_param).dq_byte_wr_min_vdl_bit[1][0] = (uint8) data; 3728 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1r(unit, &data)); 3729 (*config_param).dq_byte_wr_min_vdl_bit[1][1] = (uint8) data; 3730 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2r(unit, &data)); 3731 (*config_param).dq_byte_wr_min_vdl_bit[1][2] = (uint8) data; 3732 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3r(unit, &data)); 3733 (*config_param).dq_byte_wr_min_vdl_bit[1][3] = (uint8) data; 3734 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4r(unit, &data)); 3735 (*config_param).dq_byte_wr_min_vdl_bit[1][4] = (uint8) data; 3736 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5r(unit, &data)); 3737 (*config_param).dq_byte_wr_min_vdl_bit[1][5] = (uint8) data; 3738 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6r(unit, &data)); 3739 (*config_param).dq_byte_wr_min_vdl_bit[1][6] = (uint8) data; 3740 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7r(unit, &data)); 3741 (*config_param).dq_byte_wr_min_vdl_bit[1][7] = (uint8) data; 3742 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBIr(unit, &data)); 3743 (*config_param).dq_byte_wr_min_vdl_dbi[1] = (uint8) data; 3744 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDCr(unit, &data)); 3745 (*config_param).dq_byte_wr_min_vdl_edc[1] = (uint8) data; 3746 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, &data)); 3747 (*config_param).dq_byte_wr_max_vdl_data[1] = data; 3748 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, &data)); 3749 (*config_param).dq_byte_wr_max_vdl_dqs[1] = data; 3750 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0r(unit, &data)); 3751 (*config_param).dq_byte_rd_min_vdl_bit[1][0] = (uint8) data; 3752 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1r(unit, &data)); 3753 (*config_param).dq_byte_rd_min_vdl_bit[1][1] = (uint8) data; 3754 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2r(unit, &data)); 3755 (*config_param).dq_byte_rd_min_vdl_bit[1][2] = (uint8) data; 3756 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3r(unit, &data)); 3757 (*config_param).dq_byte_rd_min_vdl_bit[1][3] = (uint8) data; 3758 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4r(unit, &data)); 3759 (*config_param).dq_byte_rd_min_vdl_bit[1][4] = (uint8) data; 3760 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5r(unit, &data)); 3761 (*config_param).dq_byte_rd_min_vdl_bit[1][5] = (uint8) data; 3762 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6r(unit, &data)); 3763 (*config_param).dq_byte_rd_min_vdl_bit[1][6] = (uint8) data; 3764 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7r(unit, &data)); 3765 (*config_param).dq_byte_rd_min_vdl_bit[1][7] = (uint8) data; 3766 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBIr(unit, &data)); 3767 (*config_param).dq_byte_rd_min_vdl_dbi[1] = (uint8) data; 3768 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDCr(unit, &data)); 3769 (*config_param).dq_byte_rd_min_vdl_edc[1] = (uint8) data; 3770 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 3771 (*config_param).dq_byte_rd_max_vdl_dqsp[1] = data; 3772 /* READ_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDNr(unit, &data)); */ 3773 (*config_param).dq_byte_rd_max_vdl_dqsn[1] = data; 3774 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIGr(unit, &data)); 3775 (*config_param).dq_byte_ren_fifo_config[1] = data; 3776 /* READ_DDR4_PHY_DQ_BYTE1_EDCEN_FIFO_CONFIGr(unit, &data)); */ 3777 (*config_param).dq_byte_edcen_fifo_config[1] = data; 3778 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSMr(unit, &data)); 3779 (*config_param).dq_byte_rd_max_vdl_fsm[1] = data; 3780 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, &data)); 3781 (*config_param).dq_byte_vref_dac_config[1] = data; 3782 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REGr(unit, &data)); 3783 (*config_param).dq_byte_macro_reserved_reg[1] = data; 3784 3785 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0r(unit, &data)); 3786 (*config_param).dq_byte_wr_min_vdl_bit[2][0] = (uint8) data; 3787 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1r(unit, &data)); 3788 (*config_param).dq_byte_wr_min_vdl_bit[2][1] = (uint8) data; 3789 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2r(unit, &data)); 3790 (*config_param).dq_byte_wr_min_vdl_bit[2][2] = (uint8) data; 3791 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3r(unit, &data)); 3792 (*config_param).dq_byte_wr_min_vdl_bit[2][3] = (uint8) data; 3793 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4r(unit, &data)); 3794 (*config_param).dq_byte_wr_min_vdl_bit[2][4] = (uint8) data; 3795 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5r(unit, &data)); 3796 (*config_param).dq_byte_wr_min_vdl_bit[2][5] = (uint8) data; 3797 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6r(unit, &data)); 3798 (*config_param).dq_byte_wr_min_vdl_bit[2][6] = (uint8) data; 3799 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7r(unit, &data)); 3800 (*config_param).dq_byte_wr_min_vdl_bit[2][7] = (uint8) data; 3801 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBIr(unit, &data)); 3802 (*config_param).dq_byte_wr_min_vdl_dbi[2] = (uint8) data; 3803 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDCr(unit, &data)); 3804 (*config_param).dq_byte_wr_min_vdl_edc[2] = (uint8) data; 3805 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, &data)); 3806 (*config_param).dq_byte_wr_max_vdl_data[2] = data; 3807 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, &data)); 3808 (*config_param).dq_byte_wr_max_vdl_dqs[2] = data; 3809 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0r(unit, &data)); 3810 (*config_param).dq_byte_rd_min_vdl_bit[2][0] = (uint8) data; 3811 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1r(unit, &data)); 3812 (*config_param).dq_byte_rd_min_vdl_bit[2][1] = (uint8) data; 3813 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2r(unit, &data)); 3814 (*config_param).dq_byte_rd_min_vdl_bit[2][2] = (uint8) data; 3815 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3r(unit, &data)); 3816 (*config_param).dq_byte_rd_min_vdl_bit[2][3] = (uint8) data; 3817 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4r(unit, &data)); 3818 (*config_param).dq_byte_rd_min_vdl_bit[2][4] = (uint8) data; 3819 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5r(unit, &data)); 3820 (*config_param).dq_byte_rd_min_vdl_bit[2][5] = (uint8) data; 3821 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6r(unit, &data)); 3822 (*config_param).dq_byte_rd_min_vdl_bit[2][6] = (uint8) data; 3823 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7r(unit, &data)); 3824 (*config_param).dq_byte_rd_min_vdl_bit[2][7] = (uint8) data; 3825 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBIr(unit, &data)); 3826 (*config_param).dq_byte_rd_min_vdl_dbi[2] = (uint8) data; 3827 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDCr(unit, &data)); 3828 (*config_param).dq_byte_rd_min_vdl_edc[2] = (uint8) data; 3829 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 3830 (*config_param).dq_byte_rd_max_vdl_dqsp[2] = data; 3831 /* READ_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSNr(unit, &data)); */ 3832 (*config_param).dq_byte_rd_max_vdl_dqsn[2] = data; 3833 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIGr(unit, &data)); 3834 (*config_param).dq_byte_ren_fifo_config[2] = data; 3835 /* READ_DDR4_PHY_DQ_BYTE2_EDCEN_FIFO_CONFIGr(unit, &data)); */ 3836 (*config_param).dq_byte_edcen_fifo_config[2] = data; 3837 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSMr(unit, &data)); 3838 (*config_param).dq_byte_rd_max_vdl_fsm[2] = data; 3839 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, &data)); 3840 (*config_param).dq_byte_vref_dac_config[2] = data; 3841 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REGr(unit, &data)); 3842 (*config_param).dq_byte_macro_reserved_reg[2] = data; 3843 3844 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0r(unit, &data)); 3845 (*config_param).dq_byte_wr_min_vdl_bit[3][0] = (uint8) data; 3846 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1r(unit, &data)); 3847 (*config_param).dq_byte_wr_min_vdl_bit[3][1] = (uint8) data; 3848 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2r(unit, &data)); 3849 (*config_param).dq_byte_wr_min_vdl_bit[3][2] = (uint8) data; 3850 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3r(unit, &data)); 3851 (*config_param).dq_byte_wr_min_vdl_bit[3][3] = (uint8) data; 3852 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4r(unit, &data)); 3853 (*config_param).dq_byte_wr_min_vdl_bit[3][4] = (uint8) data; 3854 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5r(unit, &data)); 3855 (*config_param).dq_byte_wr_min_vdl_bit[3][5] = (uint8) data; 3856 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6r(unit, &data)); 3857 (*config_param).dq_byte_wr_min_vdl_bit[3][6] = (uint8) data; 3858 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7r(unit, &data)); 3859 (*config_param).dq_byte_wr_min_vdl_bit[3][7] = (uint8) data; 3860 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBIr(unit, &data)); 3861 (*config_param).dq_byte_wr_min_vdl_dbi[3] = (uint8) data; 3862 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDCr(unit, &data)); 3863 (*config_param).dq_byte_wr_min_vdl_edc[3] = (uint8) data; 3864 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, &data)); 3865 (*config_param).dq_byte_wr_max_vdl_data[3] = data; 3866 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, &data)); 3867 (*config_param).dq_byte_wr_max_vdl_dqs[3] = data; 3868 3869 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0r(unit, &data)); 3870 (*config_param).dq_byte_rd_min_vdl_bit[3][0] = (uint8) data; 3871 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1r(unit, &data)); 3872 (*config_param).dq_byte_rd_min_vdl_bit[3][1] = (uint8) data; 3873 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2r(unit, &data)); 3874 (*config_param).dq_byte_rd_min_vdl_bit[3][2] = (uint8) data; 3875 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3r(unit, &data)); 3876 (*config_param).dq_byte_rd_min_vdl_bit[3][3] = (uint8) data; 3877 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4r(unit, &data)); 3878 (*config_param).dq_byte_rd_min_vdl_bit[3][4] = (uint8) data; 3879 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5r(unit, &data)); 3880 (*config_param).dq_byte_rd_min_vdl_bit[3][5] = (uint8) data; 3881 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6r(unit, &data)); 3882 (*config_param).dq_byte_rd_min_vdl_bit[3][6] = (uint8) data; 3883 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7r(unit, &data)); 3884 (*config_param).dq_byte_rd_min_vdl_bit[3][7] = (uint8) data; 3885 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBIr(unit, &data)); 3886 (*config_param).dq_byte_rd_min_vdl_dbi[3] = (uint8) data; 3887 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDCr(unit, &data)); 3888 (*config_param).dq_byte_rd_min_vdl_edc[3] = (uint8) data; 3889 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 3890 (*config_param).dq_byte_rd_max_vdl_dqsp[3] = data; 3891 /* READ_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSNr(unit, &data)); */ 3892 (*config_param).dq_byte_rd_max_vdl_dqsn[3] = data; 3893 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIGr(unit, &data)); 3894 (*config_param).dq_byte_ren_fifo_config[3] = data; 3895 /* READ_DDR4_PHY_DQ_BYTE3_EDCEN_FIFO_CONFIGr(unit, &data)); */ 3896 (*config_param).dq_byte_edcen_fifo_config[3] = data; 3897 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSMr(unit, &data)); 3898 (*config_param).dq_byte_rd_max_vdl_fsm[3] = data; 3899 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, &data)); 3900 (*config_param).dq_byte_vref_dac_config[3] = data; 3901 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REGr(unit, &data)); 3902 (*config_param).dq_byte_macro_reserved_reg[3] = data; 3903 3904 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0r(unit, &data)); 3905 (*config_param).dq_byte_wr_min_vdl_bit[4][0] = (uint8) data; 3906 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1r(unit, &data)); 3907 (*config_param).dq_byte_wr_min_vdl_bit[4][1] = (uint8) data; 3908 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2r(unit, &data)); 3909 (*config_param).dq_byte_wr_min_vdl_bit[4][2] = (uint8) data; 3910 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3r(unit, &data)); 3911 (*config_param).dq_byte_wr_min_vdl_bit[4][3] = (uint8) data; 3912 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4r(unit, &data)); 3913 (*config_param).dq_byte_wr_min_vdl_bit[4][4] = (uint8) data; 3914 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5r(unit, &data)); 3915 (*config_param).dq_byte_wr_min_vdl_bit[4][5] = (uint8) data; 3916 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6r(unit, &data)); 3917 (*config_param).dq_byte_wr_min_vdl_bit[4][6] = (uint8) data; 3918 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7r(unit, &data)); 3919 (*config_param).dq_byte_wr_min_vdl_bit[4][7] = (uint8) data; 3920 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBIr(unit, &data)); 3921 (*config_param).dq_byte_wr_min_vdl_dbi[4] = (uint8) data; 3922 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDCr(unit, &data)); 3923 (*config_param).dq_byte_wr_min_vdl_edc[4] = (uint8) data; 3924 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, &data)); 3925 (*config_param).dq_byte_wr_max_vdl_data[4] = data; 3926 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQSr(unit, &data)); 3927 (*config_param).dq_byte_wr_max_vdl_dqs[4] = data; 3928 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0r(unit, &data)); 3929 (*config_param).dq_byte_rd_min_vdl_bit[4][0] = (uint8) data; 3930 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1r(unit, &data)); 3931 (*config_param).dq_byte_rd_min_vdl_bit[4][1] = (uint8) data; 3932 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2r(unit, &data)); 3933 (*config_param).dq_byte_rd_min_vdl_bit[4][2] = (uint8) data; 3934 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3r(unit, &data)); 3935 (*config_param).dq_byte_rd_min_vdl_bit[4][3] = (uint8) data; 3936 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4r(unit, &data)); 3937 (*config_param).dq_byte_rd_min_vdl_bit[4][4] = (uint8) data; 3938 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5r(unit, &data)); 3939 (*config_param).dq_byte_rd_min_vdl_bit[4][5] = (uint8) data; 3940 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6r(unit, &data)); 3941 (*config_param).dq_byte_rd_min_vdl_bit[4][6] = (uint8) data; 3942 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7r(unit, &data)); 3943 (*config_param).dq_byte_rd_min_vdl_bit[4][7] = (uint8) data; 3944 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBIr(unit, &data)); 3945 (*config_param).dq_byte_rd_min_vdl_dbi[4] = (uint8) data; 3946 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDCr(unit, &data)); 3947 (*config_param).dq_byte_rd_min_vdl_edc[4] = (uint8) data; 3948 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 3949 (*config_param).dq_byte_rd_max_vdl_dqsp[4] = data; 3950 /* READ_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSNr(unit, &data)); */ 3951 (*config_param).dq_byte_rd_max_vdl_dqsn[4] = data; 3952 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIGr(unit, &data)); 3953 (*config_param).dq_byte_ren_fifo_config[4] = data; 3954 /* READ_DDR4_PHY_DQ_BYTE4_EDCEN_FIFO_CONFIGr(unit, &data)); */ 3955 (*config_param).dq_byte_edcen_fifo_config[4] = data; 3956 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSMr(unit, &data)); 3957 (*config_param).dq_byte_rd_max_vdl_fsm[4] = data; 3958 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, &data)); 3959 (*config_param).dq_byte_vref_dac_config[4] = data; 3960 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REGr(unit, &data)); 3961 (*config_param).dq_byte_macro_reserved_reg[4] = data; 3962 3963 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, &data)); 3964 (*config_param).aq_l_max_vdl_addr = data; 3965 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, &data)); 3966 (*config_param).aq_l_max_vdl_ctrl = data; 3967 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MACRO_RESERVED_REGr(unit, &data)); 3968 (*config_param).aq_l_macro_reserved_reg = data; 3969 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, &data)); 3970 (*config_param).aq_u_max_vdl_addr = data; 3971 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, &data)); 3972 (*config_param).aq_u_max_vdl_ctrl = data; 3973 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_U_MACRO_RESERVED_REGr(unit, &data)); 3974 (*config_param).aq_u_macro_reserved_reg = data; 3975 3976 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_COMMON_MACRO_RESERVED_REGr(unit, &data)); 3977 (*config_param).common_macro_reserved_reg = data; 3978 3979 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIGr(unit, &data)); 3980 (*config_param).control_regs_read_clock_config = data; 3981 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRLr(unit, &data)); 3982 (*config_param).control_regs_input_shift_ctrl = data; 3983 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 3984 (*config_param).control_regs_ren_fifo_central_init = data; 3985 /* READ_DDR4_PHY_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); */ 3986 (*config_param).control_regs_edcen_fifo_central_init = data; 3987 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, &data)); 3988 (*config_param).control_regs_shared_vref_dac_config = data; 3989 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESERVED_REGr(unit, &data)); 3990 (*config_param).control_regs_reserved_reg = data; 3991 3992 return SOC_E_NONE; 3993 } 3994 3995 STATIC int 3996 _shmoo_sjc16_restore(int unit, int phy_ndx, sjc16_shmoo_config_param_t *config_param) 3997 { 3998 uint32 data; 3999 uint32 MRfield0, MRfield1, MRfield2, MRfield3; 4000 4001 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][0]; 4002 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0r(unit, data)); 4003 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][1]; 4004 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1r(unit, data)); 4005 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][2]; 4006 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2r(unit, data)); 4007 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][3]; 4008 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3r(unit, data)); 4009 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][4]; 4010 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4r(unit, data)); 4011 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][5]; 4012 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5r(unit, data)); 4013 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][6]; 4014 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6r(unit, data)); 4015 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[0][7]; 4016 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7r(unit, data)); 4017 data = (uint32) (*config_param).dq_byte_wr_min_vdl_dbi[0]; 4018 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBIr(unit, data)); 4019 data = (uint32) (*config_param).dq_byte_wr_min_vdl_edc[0]; 4020 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDCr(unit, data)); 4021 data = (*config_param).dq_byte_wr_max_vdl_data[0]; 4022 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 4023 data = (*config_param).dq_byte_wr_max_vdl_dqs[0]; 4024 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, data)); 4025 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][0]; 4026 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0r(unit, data)); 4027 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][1]; 4028 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1r(unit, data)); 4029 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][2]; 4030 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2r(unit, data)); 4031 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][3]; 4032 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3r(unit, data)); 4033 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][4]; 4034 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4r(unit, data)); 4035 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][5]; 4036 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5r(unit, data)); 4037 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][6]; 4038 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6r(unit, data)); 4039 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[0][7]; 4040 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7r(unit, data)); 4041 data = (uint32) (*config_param).dq_byte_rd_min_vdl_dbi[0]; 4042 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBIr(unit, data)); 4043 data = (uint32) (*config_param).dq_byte_rd_min_vdl_edc[0]; 4044 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDCr(unit, data)); 4045 data = (*config_param).dq_byte_rd_max_vdl_dqsp[0]; 4046 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 4047 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4048 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4049 4050 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 4051 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4052 4053 /* data = (*config_param).dq_byte_rd_max_vdl_dqsn[0]; 4054 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDNr(unit, data)); */ 4055 4056 data = (*config_param).dq_byte_ren_fifo_config[0]; 4057 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIGr(unit, data)); 4058 /* data = (*config_param).dq_byte_edcen_fifo_config[0]; 4059 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_EDCEN_FIFO_CONFIGr(unit, data)); */ 4060 4061 data = (*config_param).dq_byte_rd_max_vdl_fsm[0]; 4062 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4063 data = (*config_param).dq_byte_vref_dac_config[0]; 4064 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 4065 data = (*config_param).dq_byte_macro_reserved_reg[0]; 4066 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REGr(unit, data)); 4067 4068 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][0]; 4069 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0r(unit, data)); 4070 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][1]; 4071 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1r(unit, data)); 4072 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][2]; 4073 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2r(unit, data)); 4074 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][3]; 4075 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3r(unit, data)); 4076 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][4]; 4077 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4r(unit, data)); 4078 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][5]; 4079 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5r(unit, data)); 4080 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][6]; 4081 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6r(unit, data)); 4082 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[1][7]; 4083 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7r(unit, data)); 4084 data = (uint32) (*config_param).dq_byte_wr_min_vdl_dbi[1]; 4085 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBIr(unit, data)); 4086 data = (uint32) (*config_param).dq_byte_wr_min_vdl_edc[1]; 4087 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDCr(unit, data)); 4088 data = (*config_param).dq_byte_wr_max_vdl_data[1]; 4089 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 4090 data = (*config_param).dq_byte_wr_max_vdl_dqs[1]; 4091 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, data)); 4092 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][0]; 4093 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0r(unit, data)); 4094 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][1]; 4095 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1r(unit, data)); 4096 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][2]; 4097 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2r(unit, data)); 4098 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][3]; 4099 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3r(unit, data)); 4100 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][4]; 4101 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4r(unit, data)); 4102 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][5]; 4103 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5r(unit, data)); 4104 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][6]; 4105 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6r(unit, data)); 4106 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[1][7]; 4107 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7r(unit, data)); 4108 data = (uint32) (*config_param).dq_byte_rd_min_vdl_dbi[1]; 4109 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBIr(unit, data)); 4110 data = (uint32) (*config_param).dq_byte_rd_min_vdl_edc[1]; 4111 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDCr(unit, data)); 4112 data = (*config_param).dq_byte_rd_max_vdl_dqsp[1]; 4113 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 4114 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4115 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4116 4117 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE1, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 4118 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4119 /* data = (*config_param).dq_byte_rd_max_vdl_dqsn[1]; 4120 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSNr(unit, data)); */ 4121 data = (*config_param).dq_byte_ren_fifo_config[1]; 4122 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIGr(unit, data)); 4123 /* data = (*config_param).dq_byte_edcen_fifo_config[1]; 4124 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_EDCEN_FIFO_CONFIGr(unit, data)); */ 4125 data = (*config_param).dq_byte_rd_max_vdl_fsm[1]; 4126 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4127 data = (*config_param).dq_byte_vref_dac_config[1]; 4128 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 4129 data = (*config_param).dq_byte_macro_reserved_reg[1]; 4130 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REGr(unit, data)); 4131 4132 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][0]; 4133 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0r(unit, data)); 4134 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][1]; 4135 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1r(unit, data)); 4136 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][2]; 4137 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2r(unit, data)); 4138 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][3]; 4139 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3r(unit, data)); 4140 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][4]; 4141 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4r(unit, data)); 4142 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][5]; 4143 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5r(unit, data)); 4144 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][6]; 4145 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6r(unit, data)); 4146 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[2][7]; 4147 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7r(unit, data)); 4148 data = (uint32) (*config_param).dq_byte_wr_min_vdl_dbi[2]; 4149 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBIr(unit, data)); 4150 data = (uint32) (*config_param).dq_byte_wr_min_vdl_edc[2]; 4151 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDCr(unit, data)); 4152 data = (*config_param).dq_byte_wr_max_vdl_data[2]; 4153 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 4154 data = (*config_param).dq_byte_wr_max_vdl_dqs[2]; 4155 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, data)); 4156 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][0]; 4157 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0r(unit, data)); 4158 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][1]; 4159 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1r(unit, data)); 4160 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][2]; 4161 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2r(unit, data)); 4162 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][3]; 4163 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3r(unit, data)); 4164 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][4]; 4165 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4r(unit, data)); 4166 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][5]; 4167 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5r(unit, data)); 4168 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][6]; 4169 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6r(unit, data)); 4170 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[2][7]; 4171 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7r(unit, data)); 4172 data = (uint32) (*config_param).dq_byte_rd_min_vdl_dbi[2]; 4173 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBIr(unit, data)); 4174 data = (uint32) (*config_param).dq_byte_rd_min_vdl_edc[2]; 4175 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDCr(unit, data)); 4176 data = (*config_param).dq_byte_rd_max_vdl_dqsp[2]; 4177 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 4178 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4179 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4180 4181 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE2, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 4182 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4183 /* data = (*config_param).dq_byte_rd_max_vdl_dqsn[2]; 4184 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSNr(unit, data)); */ 4185 data = (*config_param).dq_byte_ren_fifo_config[2]; 4186 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIGr(unit, data)); 4187 /* data = (*config_param).dq_byte_edcen_fifo_config[2]; 4188 SOC_IF_ERROR_RETURN(WRITE_DDR4_DDR4_PHY_DQ_BYTE2_EDCEN_FIFO_CONFIGr(unit, data)); */ 4189 data = (*config_param).dq_byte_rd_max_vdl_fsm[2]; 4190 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4191 data = (*config_param).dq_byte_vref_dac_config[2]; 4192 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 4193 data = (*config_param).dq_byte_macro_reserved_reg[2]; 4194 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REGr(unit, data)); 4195 4196 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][0]; 4197 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0r(unit, data)); 4198 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][1]; 4199 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1r(unit, data)); 4200 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][2]; 4201 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2r(unit, data)); 4202 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][3]; 4203 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3r(unit, data)); 4204 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][4]; 4205 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4r(unit, data)); 4206 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][5]; 4207 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5r(unit, data)); 4208 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][6]; 4209 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6r(unit, data)); 4210 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[3][7]; 4211 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7r(unit, data)); 4212 data = (uint32) (*config_param).dq_byte_wr_min_vdl_dbi[3]; 4213 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBIr(unit, data)); 4214 data = (uint32) (*config_param).dq_byte_wr_min_vdl_edc[3]; 4215 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDCr(unit, data)); 4216 data = (*config_param).dq_byte_wr_max_vdl_data[3]; 4217 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 4218 data = (*config_param).dq_byte_wr_max_vdl_dqs[3]; 4219 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, data)); 4220 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][0]; 4221 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0r(unit, data)); 4222 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][1]; 4223 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1r(unit, data)); 4224 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][2]; 4225 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2r(unit, data)); 4226 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][3]; 4227 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3r(unit, data)); 4228 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][4]; 4229 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4r(unit, data)); 4230 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][5]; 4231 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5r(unit, data)); 4232 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][6]; 4233 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6r(unit, data)); 4234 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[3][7]; 4235 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7r(unit, data)); 4236 data = (uint32) (*config_param).dq_byte_rd_min_vdl_dbi[3]; 4237 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBIr(unit, data)); 4238 data = (uint32) (*config_param).dq_byte_rd_min_vdl_edc[3]; 4239 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDCr(unit, data)); 4240 data = (*config_param).dq_byte_rd_max_vdl_dqsp[3]; 4241 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 4242 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4243 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4244 4245 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE3, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 4246 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4247 /* data = (*config_param).dq_byte_rd_max_vdl_dqsn[3]; 4248 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSNr(unit, data)); */ 4249 data = (*config_param).dq_byte_ren_fifo_config[3]; 4250 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIGr(unit, data)); 4251 /* data = (*config_param).dq_byte_edcen_fifo_config[3]; 4252 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_EDCEN_FIFO_CONFIGr(unit, data)); */ 4253 data = (*config_param).dq_byte_rd_max_vdl_fsm[3]; 4254 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4255 data = (*config_param).dq_byte_vref_dac_config[3]; 4256 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 4257 data = (*config_param).dq_byte_macro_reserved_reg[3]; 4258 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REGr(unit, data)); 4259 4260 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][0]; 4261 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0r(unit, data)); 4262 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][1]; 4263 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1r(unit, data)); 4264 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][2]; 4265 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2r(unit, data)); 4266 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][3]; 4267 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3r(unit, data)); 4268 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][4]; 4269 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4r(unit, data)); 4270 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][5]; 4271 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5r(unit, data)); 4272 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][6]; 4273 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6r(unit, data)); 4274 data = (uint32) (*config_param).dq_byte_wr_min_vdl_bit[4][7]; 4275 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7r(unit, data)); 4276 data = (uint32) (*config_param).dq_byte_wr_min_vdl_dbi[4]; 4277 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBIr(unit, data)); 4278 data = (uint32) (*config_param).dq_byte_wr_min_vdl_edc[4]; 4279 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDCr(unit, data)); 4280 data = (*config_param).dq_byte_wr_max_vdl_data[4]; 4281 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, data)); 4282 data = (*config_param).dq_byte_wr_max_vdl_dqs[4]; 4283 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQSr(unit, data)); 4284 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][0]; 4285 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0r(unit, data)); 4286 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][1]; 4287 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1r(unit, data)); 4288 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][2]; 4289 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2r(unit, data)); 4290 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][3]; 4291 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3r(unit, data)); 4292 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][4]; 4293 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4r(unit, data)); 4294 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][5]; 4295 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5r(unit, data)); 4296 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][6]; 4297 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6r(unit, data)); 4298 data = (uint32) (*config_param).dq_byte_rd_min_vdl_bit[4][7]; 4299 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7r(unit, data)); 4300 data = (uint32) (*config_param).dq_byte_rd_min_vdl_dbi[4]; 4301 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBIr(unit, data)); 4302 data = (uint32) (*config_param).dq_byte_rd_min_vdl_edc[4]; 4303 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDCr(unit, data)); 4304 data = (*config_param).dq_byte_rd_max_vdl_dqsp[4]; 4305 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 4306 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4307 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4308 4309 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE4, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 4310 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 4311 /* data = (*config_param).dq_byte_rd_max_vdl_dqsn[4]; 4312 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSNr(unit, data)); */ 4313 data = (*config_param).dq_byte_ren_fifo_config[4]; 4314 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIGr(unit, data)); 4315 /* data = (*config_param).dq_byte_edcen_fifo_config[4]; 4316 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_EDCEN_FIFO_CONFIGr(unit, data)); */ 4317 data = (*config_param).dq_byte_rd_max_vdl_fsm[4]; 4318 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4319 data = (*config_param).dq_byte_vref_dac_config[4]; 4320 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, data)); 4321 data = (*config_param).dq_byte_macro_reserved_reg[4]; 4322 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REGr(unit, data)); 4323 4324 data = (*config_param).aq_l_max_vdl_addr; 4325 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, data)); 4326 data = (*config_param).aq_l_max_vdl_ctrl; 4327 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, data)); 4328 data = (*config_param).aq_l_macro_reserved_reg; 4329 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MACRO_RESERVED_REGr(unit, data)); 4330 data = (*config_param).aq_u_max_vdl_addr; 4331 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, data)); 4332 data = (*config_param).aq_u_max_vdl_ctrl; 4333 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, data)); 4334 data = (*config_param).aq_u_macro_reserved_reg; 4335 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MACRO_RESERVED_REGr(unit, data)); 4336 4337 data = (*config_param).common_macro_reserved_reg; 4338 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_MACRO_RESERVED_REGr(unit, data)); 4339 4340 data = (*config_param).control_regs_read_clock_config; 4341 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIGr(unit, data)); 4342 data = (*config_param).control_regs_input_shift_ctrl; 4343 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRLr(unit, data)); 4344 data = (*config_param).control_regs_ren_fifo_central_init; 4345 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 4346 /* data = (*config_param).control_regs_edcen_fifo_central_init; 4347 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr(unit, data)); */ 4348 data = (*config_param).control_regs_shared_vref_dac_config; 4349 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, data)); 4350 data = (*config_param).control_regs_reserved_reg; 4351 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESERVED_REGr(unit, data)); 4352 4353 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 4354 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 0); 4355 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 0); 4356 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 0); 4357 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 0); 4358 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 0); 4359 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 4360 4361 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 4362 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 4363 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 4364 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 4365 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 4366 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 4367 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 4368 4369 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4370 4371 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, &data)); 4372 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 4373 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 4374 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 4375 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 4376 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 4377 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, data)); 4378 4379 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4380 4381 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 4382 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 4383 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 4384 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 4385 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 4386 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 4387 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 4388 4389 sal_usleep(SHMOO_SJC16_DEEP_SLEEP); 4390 4391 MRfield0 = (*config_param).dq_byte_macro_reserved_reg[0]; 4392 MRfield1 = (*config_param).dq_byte_macro_reserved_reg[1]; 4393 MRfield2 = (*config_param).dq_byte_macro_reserved_reg[2]; 4394 MRfield3 = (*config_param).dq_byte_macro_reserved_reg[3]; 4395 4396 MRfield0 = (MRfield0 + MRfield1 + MRfield2 + MRfield3) >> 2; 4397 4398 if(MRfield0 > SHMOO_SJC16_DDR4_VREF_RANGE_CROSSOVER) 4399 { /* Vref Range 1 */ 4400 MRfield0 = MRfield0 - 23; 4401 } 4402 else 4403 { /* Vref Range 2 */ 4404 MRfield0 = MRfield0 | 0x40; 4405 } 4406 _write_mr(6, MRfield0, 0x7F); 4407 4408 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4409 4410 return SOC_E_NONE; 4411 } 4412 4413 /* 4414 * Function: 4415 * soc_sjc16_shmoo_ctl 4416 * Purpose: 4417 * Perform shmoo (PHY calibration) on specific DRC index. 4418 * Parameters: 4419 * unit - unit number 4420 * phy_ndx - DRC index to perform shmoo on. 4421 * shmoo_type - Selects shmoo sub-section to be performs (-1 for full shmoo) 4422 * stat - RFU 4423 * plot - Plot shmoo results when not equal to 0 4424 * action - Save/restore functionality 4425 * *config_param - PHY configuration saved/restored 4426 * Returns: 4427 * SOC_E_XXX 4428 * This routine may be called after a device is attached 4429 * or whenever a chip reset is required. 4430 */ 4431 4432 int 4433 soc_sjc16_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat, int plot, int action, sjc16_shmoo_config_param_t *config_param) 4434 { 4435 sjc16_shmoo_container_t *scPtr = NULL; 4436 uint32 dramType; 4437 uint32 ctlType; 4438 uint32 i; 4439 int ndx, ndxEnd; 4440 const uint32 *seqPtr; 4441 uint32 seqCount; 4442 4443 dramType = shmoo_dram_info.dram_type; 4444 ctlType = shmoo_dram_info.ctl_type; 4445 4446 if(!stat) 4447 { 4448 scPtr = sal_alloc(sizeof(sjc16_shmoo_container_t), "SJC16 Shmoo Container"); 4449 if(scPtr == NULL) 4450 { 4451 return SOC_E_MEMORY; 4452 } 4453 sal_memset(scPtr, 0, sizeof(sjc16_shmoo_container_t)); 4454 4455 if(phy_ndx != SHMOO_SJC16_INTERFACE_RSVP) 4456 { 4457 ndx = phy_ndx; 4458 ndxEnd = phy_ndx + 1; 4459 } 4460 else 4461 { 4462 ndx = 0; 4463 ndxEnd = SHMOO_SJC16_MAX_INTERFACES; 4464 } 4465 4466 for(; ndx < ndxEnd; ndx++) 4467 { 4468 if(!_shmoo_sjc16_check_dram(ndx)) { 4469 continue; 4470 } 4471 4472 if(action == SHMOO_SJC16_ACTION_RESTORE) 4473 { 4474 switch(ctlType) 4475 { 4476 case SHMOO_SJC16_CTL_TYPE_RSVP: 4477 break; 4478 case SHMOO_SJC16_CTL_TYPE_1: 4479 _shmoo_sjc16_restore(unit, phy_ndx, config_param); 4480 break; 4481 default: 4482 if(scPtr != NULL) 4483 { 4484 sal_free(scPtr); 4485 scPtr = NULL; 4486 } 4487 4488 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported controller type: %02u\n"), ctlType)); 4489 4490 return SOC_E_FAIL; 4491 } 4492 } 4493 else if((action == SHMOO_SJC16_ACTION_RUN) || (action == SHMOO_SJC16_ACTION_RUN_AND_SAVE)) 4494 { 4495 switch(ctlType) 4496 { 4497 case SHMOO_SJC16_CTL_TYPE_RSVP: 4498 break; 4499 case SHMOO_SJC16_CTL_TYPE_1: 4500 switch(dramType) 4501 { 4502 case SHMOO_SJC16_DRAM_TYPE_DDR4: 4503 seqPtr = &shmoo_order_sjc16_ddr4[0]; 4504 if(shmoo_dram_info.ecc_32p4) 4505 { 4506 seqCount = SHMOO_SJC16_DDR4_ECC_32P4_SEQUENCE_COUNT; 4507 } 4508 else 4509 { 4510 seqCount = SHMOO_SJC16_DDR4_SEQUENCE_COUNT; 4511 } 4512 break; 4513 default: 4514 if(scPtr != NULL) 4515 { 4516 sal_free(scPtr); 4517 scPtr = NULL; 4518 } 4519 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported dram type: %02u\n"), dramType)); 4520 return SOC_E_FAIL; 4521 } 4522 4523 (*scPtr).dramType = dramType; 4524 (*scPtr).ctlType = ctlType; 4525 4526 if(shmoo_type != SHMOO_SJC16_SHMOO_RSVP) 4527 { 4528 (*scPtr).shmooType = shmoo_type; 4529 _shmoo_sjc16_entry(unit, ndx, scPtr, SHMOO_SJC16_SINGLE); 4530 _shmoo_sjc16_do(unit, ndx, scPtr); 4531 _shmoo_sjc16_calib_2D(unit, ndx, scPtr); 4532 _shmoo_sjc16_set_new_step(unit, ndx, scPtr); 4533 if(plot) 4534 { 4535 _shmoo_sjc16_plot(unit, ndx, scPtr); 4536 } 4537 _shmoo_sjc16_exit(unit, ndx, scPtr, SHMOO_SJC16_SINGLE); 4538 } 4539 else 4540 { 4541 for(i = 0; i < seqCount; i++) 4542 { 4543 (*scPtr).shmooType = seqPtr[i]; 4544 _shmoo_sjc16_entry(unit, ndx, scPtr, SHMOO_SJC16_SEQUENTIAL); 4545 _shmoo_sjc16_do(unit, ndx, scPtr); 4546 _shmoo_sjc16_calib_2D(unit, ndx, scPtr); 4547 _shmoo_sjc16_set_new_step(unit, ndx, scPtr); 4548 if(plot) 4549 { 4550 _shmoo_sjc16_plot(unit, ndx, scPtr); 4551 } 4552 _shmoo_sjc16_exit(unit, ndx, scPtr, SHMOO_SJC16_SEQUENTIAL); 4553 } 4554 } 4555 4556 break; 4557 default: 4558 if(scPtr != NULL) 4559 { 4560 sal_free(scPtr); 4561 scPtr = NULL; 4562 } 4563 4564 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported controller type: %02u\n"), ctlType)); 4565 4566 return SOC_E_FAIL; 4567 } 4568 } 4569 4570 if((action == SHMOO_SJC16_ACTION_RUN_AND_SAVE) || (action == SHMOO_SJC16_ACTION_SAVE)) 4571 { 4572 _shmoo_sjc16_save(unit, phy_ndx, config_param); 4573 } 4574 } 4575 4576 if(scPtr != NULL) 4577 { 4578 sal_free(scPtr); 4579 scPtr = NULL; 4580 } 4581 4582 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DDR Tuning Complete\n"))); 4583 } 4584 else 4585 { 4586 /* Report only */ 4587 switch(ctlType) 4588 { 4589 case SHMOO_SJC16_CTL_TYPE_RSVP: 4590 break; 4591 case SHMOO_SJC16_CTL_TYPE_1: 4592 break; 4593 default: 4594 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported controller type: %02u\n"), ctlType)); 4595 return SOC_E_FAIL; 4596 } 4597 } 4598 return SOC_E_NONE; 4599 } 4600 4601 /* Set Dram Parameters/Info to Shmoo driver */ 4602 int 4603 soc_sjc16_shmoo_dram_info_set(int unit, sjc16_shmoo_dram_info_t *sdi) 4604 { 4605 #if(!SHMOO_SJC16_PHY_CONSTANT_CONFIG) 4606 shmoo_dram_info.ctl_type = (*sdi).ctl_type; 4607 shmoo_dram_info.dram_type = (*sdi).dram_type; 4608 shmoo_dram_info.dram_bitmap = (*sdi).dram_bitmap; 4609 shmoo_dram_info.interface_bitwidth = (*sdi).interface_bitwidth; 4610 shmoo_dram_info.ecc_32p4 = (*sdi).ecc_32p4; 4611 shmoo_dram_info.num_columns = (*sdi).num_columns; 4612 shmoo_dram_info.num_rows = (*sdi).num_rows; 4613 shmoo_dram_info.num_banks = (*sdi).num_banks; 4614 shmoo_dram_info.num_bank_groups = (*sdi).num_bank_groups; 4615 shmoo_dram_info.data_rate_mbps = (*sdi).data_rate_mbps; 4616 shmoo_dram_info.ref_clk_mhz = (*sdi).ref_clk_mhz; 4617 shmoo_dram_info.refi = (*sdi).refi; 4618 shmoo_dram_info.command_parity_latency = (*sdi).command_parity_latency; 4619 shmoo_dram_info.sim_system_mode = (*sdi).sim_system_mode; 4620 #endif 4621 return SOC_E_NONE; 4622 } 4623 4624 /* Configure PHY PLL and wait for lock */ 4625 int 4626 _soc_sjc16_shmoo_phy_cfg_pll(int unit, int phy_ndx) 4627 { 4628 uint32 val; 4629 int fref, fref_post, fref_eff_int, fref_eff_frac, freq_vco, data_rate; 4630 int pdiv10, ndiv_int10; 4631 uint32 frequency_doubler_mode; 4632 uint32 iso_in, ldo_ctrl, ssc_limit, ssc_mode, ssc_step, pll_ctrl, en_ctrl; 4633 uint32 pdiv, ndiv_int, ndiv_frac, mdiv, fref_eff_info, vco_sel; 4634 uint32 timeout; 4635 4636 data_rate = shmoo_dram_info.data_rate_mbps; 4637 fref = shmoo_dram_info.ref_clk_mhz; 4638 4639 iso_in = 0; 4640 ldo_ctrl = 0x0000; 4641 ssc_limit = 0x000000; 4642 ssc_mode = 0; 4643 ssc_step = 0x0000; 4644 pll_ctrl = 0x00000000; 4645 4646 if(shmoo_dram_info.ref_clk_mhz != 100) 4647 { 4648 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Unsupported reference flock frequency: %4d MHz\n"), shmoo_dram_info.ref_clk_mhz)); 4649 return SOC_E_FAIL; 4650 } 4651 4652 fref_eff_int = 33; 4653 fref_eff_frac = 333; 4654 freq_vco = data_rate << 1; 4655 4656 frequency_doubler_mode = 0; /* Frequency doubler OFF */ 4657 en_ctrl = frequency_doubler_mode; 4658 4659 fref_post = fref << frequency_doubler_mode; 4660 pdiv10 = (10000 * fref_post) / ((1000 * fref_eff_int) + fref_eff_frac); 4661 4662 if((pdiv10 % 10) >= 5) 4663 { 4664 pdiv = (pdiv10 / 10) + 1; 4665 } 4666 else 4667 { 4668 pdiv = (pdiv10 / 10); 4669 } 4670 4671 ndiv_int10 = (10000 * freq_vco) / ((1000 * fref_eff_int) + fref_eff_frac); 4672 4673 if((ndiv_int10 % 10) >= 5) 4674 { 4675 ndiv_int = (ndiv_int10 / 10) + 1; 4676 } 4677 else 4678 { 4679 ndiv_int = (ndiv_int10 / 10); 4680 } 4681 4682 ndiv_frac = 0; /* ndiv fraction OFF */ 4683 mdiv = 1; 4684 fref_eff_info = fref_eff_int; 4685 4686 if(freq_vco > 5500) 4687 { 4688 vco_sel = 1; 4689 } 4690 else 4691 { 4692 vco_sel = 0; 4693 } 4694 4695 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "PHY PLL Configuration\n"))); 4696 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Fref...........: %4d\n"), fref)); 4697 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "PDIV...........: %4d\n"), pdiv)); 4698 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "NDIV...........: %4d\n"), ndiv_int)); 4699 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Fvco...........: %4d\n"), freq_vco)); 4700 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Data rate......: %4d\n"), data_rate)); 4701 4702 #if defined(CONFIG_HELIX5) 4703 SOC_IF_ERROR_RETURN(READ_DDR_APB_PWR_RSTr(unit, &val)); 4704 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_PWR_ONf, 1); 4705 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_PWR_ON_LDOf, 1); 4706 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_RESETBf, 0); 4707 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_POST_RESETBf, 0); 4708 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_PWR_RSTr(unit, val)); 4709 4710 SOC_IF_ERROR_RETURN(READ_DDR_APB_DBG_1r(unit, &val)); 4711 soc_reg_field_set(unit, DDR_APB_DBG_1r, &val, I_PLL_CTRLf, pll_ctrl); 4712 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_DBG_1r(unit, val)); 4713 4714 SOC_IF_ERROR_RETURN(READ_DDR_APB_DBG_2r(unit, &val)); 4715 soc_reg_field_set(unit, DDR_APB_DBG_2r, &val, I_LDO_CTRLf, ldo_ctrl); 4716 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_DBG_2r(unit, val)); 4717 4718 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4719 4720 SOC_IF_ERROR_RETURN(READ_DDR_APB_PWR_RSTr(unit, &val)); 4721 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_ISO_INf, iso_in); 4722 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_PWR_RSTr(unit, val)); 4723 4724 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4725 4726 SOC_IF_ERROR_RETURN(READ_DDR_APB_LP_FREQ_2r(unit, &val)); 4727 soc_reg_field_set(unit, DDR_APB_LP_FREQ_2r, &val, I_NDIV_FRACf, ndiv_frac); 4728 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_LP_FREQ_2r(unit, val)); 4729 4730 SOC_IF_ERROR_RETURN(READ_DDR_APB_LP_FREQ_1r(unit, &val)); 4731 soc_reg_field_set(unit, DDR_APB_LP_FREQ_1r, &val, I_NDIV_INTf, ndiv_int); 4732 soc_reg_field_set(unit, DDR_APB_LP_FREQ_1r, &val, I_PDIVf, pdiv); 4733 soc_reg_field_set(unit, DDR_APB_LP_FREQ_1r, &val, I_MDIV_2TO0f, (mdiv & 0x7)); 4734 soc_reg_field_set(unit, DDR_APB_LP_FREQ_1r, &val, I_FREFEFF_INFOf, fref_eff_info); 4735 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_LP_FREQ_1r(unit, val)); 4736 4737 SOC_IF_ERROR_RETURN(READ_DDR_APB_PWR_RSTr(unit, &val)); 4738 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_MDIV_3f, (mdiv >> 3)); 4739 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_PWR_RSTr(unit, val)); 4740 4741 SOC_IF_ERROR_RETURN(READ_DDR_APB_SSC_2r(unit, &val)); 4742 soc_reg_field_set(unit, DDR_APB_SSC_2r, &val, I_SSC_LIMITf, ssc_limit); 4743 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_SSC_2r(unit, val)); 4744 4745 SOC_IF_ERROR_RETURN(READ_DDR_APB_SSC_1r(unit, &val)); 4746 soc_reg_field_set(unit, DDR_APB_SSC_1r, &val, I_SSC_MODEf, ssc_mode); 4747 soc_reg_field_set(unit, DDR_APB_SSC_1r, &val, I_SSC_STEPf, ssc_step); 4748 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_SSC_1r(unit, val)); 4749 4750 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4751 4752 SOC_IF_ERROR_RETURN(READ_DDR_APB_LP_VCO_CTRL_2r(unit, &val)); 4753 soc_reg_field_set(unit, DDR_APB_LP_VCO_CTRL_2r, &val, I_VCO_SELf, vco_sel); 4754 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_LP_VCO_CTRL_2r(unit, val)); 4755 4756 SOC_IF_ERROR_RETURN(READ_DDR_APB_CLK_ROUTEr(unit, &val)); 4757 soc_reg_field_set(unit, DDR_APB_CLK_ROUTEr, &val, I_EN_CTRLf, en_ctrl); 4758 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_CLK_ROUTEr(unit, val)); 4759 4760 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4761 4762 SOC_IF_ERROR_RETURN(READ_DDR_APB_PWR_RSTr(unit, &val)); 4763 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_RESETBf, 1); 4764 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_PWR_RSTr(unit, val)); 4765 4766 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4767 4768 timeout = 20000; 4769 do 4770 { 4771 SOC_IF_ERROR_RETURN(READ_DDR_APB_PWR_RSTr(unit, &val)); 4772 if(soc_reg_field_get(unit, DDR_APB_PWR_RSTr, val, O_LOCKf)) 4773 { 4774 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Lock status....: Locked\n"))); 4775 break; 4776 } 4777 4778 if(timeout == 0) 4779 { 4780 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Lock status....: Timed out\n"))); 4781 return SOC_E_TIMEOUT; 4782 } 4783 4784 timeout--; 4785 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4786 } 4787 while(TRUE); 4788 4789 SOC_IF_ERROR_RETURN(READ_DDR_APB_PWR_RSTr(unit, &val)); 4790 soc_reg_field_set(unit, DDR_APB_PWR_RSTr, &val, I_POST_RESETBf, 1); 4791 SOC_IF_ERROR_RETURN(WRITE_DDR_APB_PWR_RSTr(unit, val)); 4792 4793 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4794 4795 SOC_IF_ERROR_RETURN(WRITE_DDR_S1_IDM_RESET_CONTROLr(unit, 1)); 4796 SOC_IF_ERROR_RETURN(WRITE_DDR_S0_IDM_RESET_CONTROLr(unit, 1)); 4797 4798 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4799 4800 SOC_IF_ERROR_RETURN(WRITE_DDR_S1_IDM_RESET_CONTROLr(unit, 0)); 4801 SOC_IF_ERROR_RETURN(WRITE_DDR_S0_IDM_RESET_CONTROLr(unit, 0)); 4802 4803 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4804 4805 #endif 4806 4807 return SOC_E_NONE; 4808 } 4809 4810 int 4811 soc_sjc16_shmoo_phy_init(int unit, int phy_ndx) 4812 { 4813 int ndx, ndxEnd; 4814 uint32 data, reset_ctrl_data, read_fifo_ctrl_data; 4815 sjc16_step_size_t ss; 4816 uint32 step1000; 4817 uint32 size1000UI; 4818 uint32 setting; 4819 uint32 ck_ui, addr_ctrl_ui, dqs_ui, data_ui; 4820 4821 if(phy_ndx != SHMOO_SJC16_INTERFACE_RSVP) 4822 { 4823 ndx = phy_ndx; 4824 ndxEnd = phy_ndx + 1; 4825 } 4826 else 4827 { 4828 ndx = 0; 4829 ndxEnd = SHMOO_SJC16_MAX_INTERFACES; 4830 } 4831 4832 for(; ndx < ndxEnd; ndx++) 4833 { 4834 if(!_shmoo_sjc16_check_dram(ndx)) 4835 { 4836 continue; 4837 } 4838 4839 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A Series - PHY Initialization (PHY index: %02d)\n"), ndx)); 4840 4841 /*A01*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A01. Configure PHY PLL\n"))); 4842 _soc_sjc16_shmoo_phy_cfg_pll(unit, ndx); 4843 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4844 4845 /*A02*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A02. Reset all PHY logic\n"))); 4846 reset_ctrl_data = 0; 4847 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 4848 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4849 4850 /*A03*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A03. Enable Read FIFO\n"))); 4851 read_fifo_ctrl_data = 0; 4852 DDR_PHY_SET_FIELD(read_fifo_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, READ_FIFO_CTRL, W2R_MIN_DELAY_2, 0); 4853 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRLr(unit, read_fifo_ctrl_data)); 4854 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4855 4856 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, READ_FIFO_RESET_N, 1); 4857 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 4858 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4859 4860 DDR_PHY_SET_FIELD(read_fifo_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, READ_FIFO_CTRL, ENABLE, 1); 4861 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRLr(unit, read_fifo_ctrl_data)); 4862 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4863 4864 /*A04*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A04. Configure input shift control\n"))); 4865 data = 0; 4866 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, INPUT_SHIFT_CTRL, DATAPATH_SHIFT_ENABLE, 0); 4867 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, INPUT_SHIFT_CTRL, DATAPATH_ADDITIONAL_LATENCY, 0); 4868 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, INPUT_SHIFT_CTRL, ADDRPATH_SHIFT_ENABLE, 0); 4869 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, INPUT_SHIFT_CTRL, ADDRPATH_ADDITIONAL_LATENCY, 0); 4870 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, INPUT_SHIFT_CTRL, RCMD_SHIFT_ENABLE, 1); 4871 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, INPUT_SHIFT_CTRL, RCMD_ADDITIONAL_LATENCY, 5); 4872 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRLr(unit, data)); 4873 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4874 4875 /*A05*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A05. Configure power regulation\n"))); 4876 data = 0; 4877 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, LDO_CONFIG, PWRDN, 1); 4878 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_LDO_CONFIGr(unit, data)); 4879 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_LDO_CONFIGr(unit, data)); 4880 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIGr(unit, data)); 4881 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIGr(unit, data)); 4882 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIGr(unit, data)); 4883 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIGr(unit, data)); 4884 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIGr(unit, data)); 4885 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIGr(unit, data)); 4886 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIGr(unit, data)); 4887 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIGr(unit, data)); 4888 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIGr(unit, data)); 4889 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIGr(unit, data)); 4890 4891 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4892 4893 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, LDO_CONFIG, BIAS_CTRL, 0); 4894 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, LDO_CONFIG, BYPASS, 0); 4895 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, LDO_CONFIG, CTRL, 0x00); 4896 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, LDO_CONFIG, REF_EXT, 1); 4897 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, LDO_CONFIG, REF_SEL_EXT, 0); 4898 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_LDO_CONFIGr(unit, data)); 4899 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_LDO_CONFIGr(unit, data)); 4900 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIGr(unit, data)); 4901 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIGr(unit, data)); 4902 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIGr(unit, data)); 4903 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIGr(unit, data)); 4904 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIGr(unit, data)); 4905 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIGr(unit, data)); 4906 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIGr(unit, data)); 4907 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIGr(unit, data)); 4908 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIGr(unit, data)); 4909 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIGr(unit, data)); 4910 4911 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4912 4913 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, LDO_CONFIG, PWRDN, 0); 4914 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_LDO_CONFIGr(unit, data)); 4915 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_LDO_CONFIGr(unit, data)); 4916 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIGr(unit, data)); 4917 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIGr(unit, data)); 4918 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIGr(unit, data)); 4919 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIGr(unit, data)); 4920 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIGr(unit, data)); 4921 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIGr(unit, data)); 4922 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIGr(unit, data)); 4923 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIGr(unit, data)); 4924 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIGr(unit, data)); 4925 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIGr(unit, data)); 4926 4927 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4928 4929 /*A06*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A06. Configure reference voltage\n"))); 4930 /*R06*/ data = 0; 4931 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, SHARED_VREF_DAC_CONFIG, CTRL, 0x0001); 4932 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, data)); 4933 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 4934 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 4935 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 4936 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 4937 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, data)); 4938 4939 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4940 4941 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, SHARED_VREF_DAC_CONFIG, DATA, 0x92); 4942 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, data)); 4943 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 4944 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 4945 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 4946 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 4947 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, data)); 4948 4949 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4950 4951 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, SHARED_VREF_DAC_CONFIG, CTRL, 0x0000); 4952 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, data)); 4953 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIGr(unit, data)); 4954 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIGr(unit, data)); 4955 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIGr(unit, data)); 4956 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIGr(unit, data)); 4957 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIGr(unit, data)); 4958 4959 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4960 4961 /*A07*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A07. Release VDL resets\n"))); 4962 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, VDL_1G_RESET_N, 1); 4963 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 4964 4965 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 4966 4967 /*A08*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A08. Compute VDL step size\n"))); 4968 _sjc16_calculate_step_size(unit, ndx, &ss); 4969 4970 step1000 = ss.step1000; 4971 size1000UI = ss.size1000UI; 4972 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " VDL step size........: %3d.%03d ps\n"), 4973 (step1000 / 1000), (step1000 % 1000))); 4974 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " UI size..............: %3d.%03d steps\n"), 4975 (size1000UI / 1000), (size1000UI % 1000))); 4976 4977 /*A09*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A09. Configure read clock\n"))); 4978 data = 0; 4979 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, READ_CLOCK_CONFIG, FREE_RUNNING_MODE, 0); 4980 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIGr(unit, data)); 4981 4982 4983 data = 0; 4984 setting = size1000UI / 1000; /* 50% placement on 2G clock */ 4985 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_READ_MAX_VDL_FSM, MAX_VDL_STEP, setting); 4986 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4987 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4988 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4989 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4990 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSMr(unit, data)); 4991 4992 data = 0; 4993 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_3, 0); 4994 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_2, 0); 4995 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_MINUS_1, 1); 4996 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_0, 1); 4997 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_PLUS_1, 1); 4998 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_STRETCH_CONFIG, A_PLUS_2, 0); 4999 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIGr(unit, data)); 5000 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIGr(unit, data)); 5001 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIGr(unit, data)); 5002 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIGr(unit, data)); 5003 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIGr(unit, data)); 5004 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5005 5006 /*A10*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A10. Configure UI shifts\n"))); 5007 ck_ui = SHMOO_SJC16_DDR4_INIT_CK_UI_SHIFT; 5008 addr_ctrl_ui = SHMOO_SJC16_DDR4_INIT_ADDR_CTRL_UI_SHIFT; 5009 dqs_ui = SHMOO_SJC16_DDR4_INIT_DQS_UI_SHIFT; 5010 data_ui = SHMOO_SJC16_DDR4_INIT_DATA_UI_SHIFT; 5011 5012 data = 0; 5013 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, MAX_VDL_CK, UI_SHIFT, ck_ui); 5014 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_MAX_VDL_CKr(unit, data)); 5015 5016 5017 data = 0; 5018 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, UI_SHIFT, addr_ctrl_ui); 5019 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, data)); 5020 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, data)); 5021 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, data)); 5022 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, data)); 5023 5024 data = 0; 5025 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DQS, UI_SHIFT, dqs_ui); 5026 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, data)); 5027 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, data)); 5028 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, data)); 5029 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, data)); 5030 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQSr(unit, data)); 5031 5032 data = 0; 5033 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, UI_SHIFT, data_ui); 5034 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 5035 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 5036 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 5037 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 5038 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, data)); 5039 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5040 5041 /*A11*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A11. Configure VDLs\n"))); 5042 data = SHMOO_SJC16_DDR4_INIT_WRITE_MIN_VDL_POS; 5043 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0r(unit, data)); 5044 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1r(unit, data)); 5045 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2r(unit, data)); 5046 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3r(unit, data)); 5047 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4r(unit, data)); 5048 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5r(unit, data)); 5049 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6r(unit, data)); 5050 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7r(unit, data)); 5051 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBIr(unit, data)); 5052 5053 /* DDR_PHY_REG_WRITE(unit, SHMOO_SJC16_PHY_REG_BASE, 0, SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC, data)); */ 5054 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0r(unit, data)); 5055 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1r(unit, data)); 5056 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2r(unit, data)); 5057 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3r(unit, data)); 5058 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4r(unit, data)); 5059 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5r(unit, data)); 5060 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6r(unit, data)); 5061 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7r(unit, data)); 5062 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBIr(unit, data)); 5063 5064 /* DDR_PHY_REG_WRITE(unit, SHMOO_SJC16_PHY_REG_BASE, 0, SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC, data)); */ 5065 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0r(unit, data)); 5066 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1r(unit, data)); 5067 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2r(unit, data)); 5068 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3r(unit, data)); 5069 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4r(unit, data)); 5070 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5r(unit, data)); 5071 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6r(unit, data)); 5072 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7r(unit, data)); 5073 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBIr(unit, data)); 5074 5075 /* DDR_PHY_REG_WRITE(unit, SHMOO_SJC16_PHY_REG_BASE, 0, SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC, data)); */ 5076 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0r(unit, data)); 5077 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1r(unit, data)); 5078 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2r(unit, data)); 5079 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3r(unit, data)); 5080 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4r(unit, data)); 5081 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5r(unit, data)); 5082 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6r(unit, data)); 5083 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7r(unit, data)); 5084 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBIr(unit, data)); 5085 5086 /* DDR_PHY_REG_WRITE(unit, SHMOO_SJC16_PHY_REG_BASE, 0, SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC, data)); */ 5087 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0r(unit, data)); 5088 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1r(unit, data)); 5089 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2r(unit, data)); 5090 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3r(unit, data)); 5091 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4r(unit, data)); 5092 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5r(unit, data)); 5093 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6r(unit, data)); 5094 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7r(unit, data)); 5095 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBIr(unit, data)); 5096 5097 5098 data = SHMOO_SJC16_DDR4_INIT_READ_MIN_VDL_POS; 5099 5100 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0r(unit, data)); 5101 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1r(unit, data)); 5102 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2r(unit, data)); 5103 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3r(unit, data)); 5104 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4r(unit, data)); 5105 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5r(unit, data)); 5106 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6r(unit, data)); 5107 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7r(unit, data)); 5108 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBIr(unit, data)); 5109 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDCr(unit, data)); 5110 5111 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0r(unit, data)); 5112 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1r(unit, data)); 5113 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2r(unit, data)); 5114 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3r(unit, data)); 5115 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4r(unit, data)); 5116 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5r(unit, data)); 5117 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6r(unit, data)); 5118 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7r(unit, data)); 5119 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBIr(unit, data)); 5120 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDCr(unit, data)); 5121 5122 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0r(unit, data)); 5123 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1r(unit, data)); 5124 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2r(unit, data)); 5125 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3r(unit, data)); 5126 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4r(unit, data)); 5127 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5r(unit, data)); 5128 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6r(unit, data)); 5129 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7r(unit, data)); 5130 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBIr(unit, data)); 5131 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDCr(unit, data)); 5132 5133 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0r(unit, data)); 5134 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1r(unit, data)); 5135 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2r(unit, data)); 5136 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3r(unit, data)); 5137 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4r(unit, data)); 5138 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5r(unit, data)); 5139 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6r(unit, data)); 5140 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7r(unit, data)); 5141 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBIr(unit, data)); 5142 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDCr(unit, data)); 5143 5144 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0r(unit, data)); 5145 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1r(unit, data)); 5146 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2r(unit, data)); 5147 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3r(unit, data)); 5148 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4r(unit, data)); 5149 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5r(unit, data)); 5150 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6r(unit, data)); 5151 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7r(unit, data)); 5152 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBIr(unit, data)); 5153 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDCr(unit, data)); 5154 5155 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, &data)); 5156 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DQS, MAX_VDL_STEP, 0); 5157 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, data)); 5158 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, data)); 5159 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, data)); 5160 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, data)); 5161 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQSr(unit, data)); 5162 5163 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, &data)); 5164 setting = (size1000UI * 3) / 20000; /* 15% adjustment */ 5165 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, WRITE_MAX_VDL_DATA, MAX_VDL_STEP, setting); 5166 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, data)); 5167 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, data)); 5168 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, data)); 5169 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, data)); 5170 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATAr(unit, data)); 5171 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5172 5173 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, &data)); 5174 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MAX_VDL_STEP, 0); 5175 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, MASTER_MODE, 1); 5176 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 1); 5177 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5178 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5179 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5180 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5181 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5182 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5183 5184 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, READ_MAX_VDL_DQS_MASTER_CTRL, FORCE_UPDATE, 0); 5185 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5186 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5187 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5188 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5189 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRLr(unit, data)); 5190 5191 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, &data)); /* ADDR/CTRL should be in a working position */ 5192 setting = size1000UI / 1250; /* 80% adjustment */ 5193 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_AQ, L_MAX_VDL_ADDR, MAX_VDL_STEP, setting); 5194 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_ADDRr(unit, data)); 5195 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_ADDRr(unit, data)); 5196 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_L_MAX_VDL_CTRLr(unit, data)); 5197 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_AQ_U_MAX_VDL_CTRLr(unit, data)); 5198 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5199 5200 /*A12*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A12. ZQ calibration\n"))); 5201 /*R12*/ if(shmoo_dram_info.sim_system_mode) 5202 { 5203 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Skipped for emulation\n"))); 5204 5205 goto SHMOO_SJC16_ZQ_CALIBRATION_END; 5206 } 5207 5208 _sjc16_zq_calibration(unit, ndx); 5209 5210 SHMOO_SJC16_ZQ_CALIBRATION_END: 5211 5212 /*A13*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A13. Enable CK\n"))); 5213 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_COMMON_CK_CONFIGr(unit, &data)); 5214 5215 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_COMMON, CK_CONFIG, CK_ENABLE, 1); 5216 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_COMMON_CK_CONFIGr(unit, data)); 5217 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5218 5219 /*A14*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A14. Configure FIFOs\n"))); 5220 data = 0; 5221 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 0); 5222 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 0); 5223 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 0); 5224 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 0); 5225 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 0); 5226 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_RD2_2G_SELECT, 0); 5227 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_RD2_2G_SELECT, 1); 5228 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_RD2_2G_SELECT, 2); 5229 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_RD2_2G_SELECT, 3); 5230 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_RD2_2G_SELECT, 4); 5231 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 5232 5233 data = 0; 5234 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_FIFO_CONFIG, RD_2G_DELAY, 6); 5235 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_REN_FIFO_CONFIG, RD2_2G_DELAY, SHMOO_SJC16_DDR4_INIT_REN_RD2_2G_DELAY); 5236 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIGr(unit, data)); 5237 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIGr(unit, data)); 5238 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIGr(unit, data)); 5239 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIGr(unit, data)); 5240 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIGr(unit, data)); 5241 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5242 5243 /*A15*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A15. Program DRAM parameters into PHY\n"))); 5244 data = 0; 5245 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_DRAM_PARAMETER_CONFIG, T_PHY_WRDATA, 0x0); 5246 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_DRAM_PARAMETER_CONFIG, BURST_LENGTH, 0x0); 5247 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIGr(unit, data)); 5248 5249 data = 0; 5250 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_OE_CONFIG, OE_POST_CYCLES, 1); 5251 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_DQ_BYTE0, DDR4_OE_CONFIG, OE_PRE_CYCLES, 0); 5252 5253 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIGr(unit, data)); 5254 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIGr(unit, data)); 5255 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIGr(unit, data)); 5256 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIGr(unit, data)); 5257 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIGr(unit, data)); 5258 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5259 5260 /*A16*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A16. Set active PHY interfaces\n"))); 5261 data = 0; 5262 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, ACTIVE_INTERFACES_CONFIG, ACTIVE_ADDRESS, 1); 5263 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, ACTIVE_INTERFACES_CONFIG, ACTIVE_BYTES_BITMAP, 0x0F); 5264 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIGr(unit, data)); 5265 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5266 5267 /*A17*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A17. Release PHY resets\n"))); 5268 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DRC_1G_RESET_N, 1); 5269 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_1G_RESET_N, 1); 5270 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, PHY_2G_RESET_N, 1); 5271 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, DDR4_GLUE_RESET_N, 1); 5272 DDR_PHY_SET_FIELD(reset_ctrl_data, SJC16_DDR4_PHY_CONTROL_REGS, RESET_CTRL, RCMD_FIFO_RESET_N, 1); 5273 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_RESET_CTRLr(unit, reset_ctrl_data)); 5274 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5275 5276 /*A18*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A18. Enable FIFOs\n"))); 5277 SOC_IF_ERROR_RETURN(READ_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, &data)); 5278 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE0_WRITE_ENABLE, 1); 5279 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE1_WRITE_ENABLE, 1); 5280 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE2_WRITE_ENABLE, 1); 5281 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE3_WRITE_ENABLE, 1); 5282 DDR_PHY_SET_FIELD(data, SJC16_DDR4_PHY_CONTROL_REGS, DDR4_REN_FIFO_CENTRAL_INITIALIZER, DQ_BYTE4_WRITE_ENABLE, 1); 5283 SOC_IF_ERROR_RETURN(WRITE_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZERr(unit, data)); 5284 sal_usleep(SHMOO_SJC16_SHORT_SLEEP); 5285 5286 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A Series - PHY Initialization complete (PHY index: %02d)\n"), ndx)); 5287 } 5288 5289 return SOC_E_NONE; 5290 } 5291 5292 #endif