shmoo_ddr40.c (395354B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * DDR3 Memory support 8 */ 9 10 #include <shared/bsl.h> 11 12 #include <sal/core/boot.h> 13 #include <sal/core/libc.h> 14 #include <shared/alloc.h> 15 #include <soc/memtune.h> 16 #include <soc/mcm/memregs.h> 17 18 #include <soc/drv.h> 19 #include <soc/cm.h> 20 #include <soc/mem.h> 21 #ifdef BCM_CMICM_SUPPORT 22 #include <soc/cmicm.h> 23 #endif 24 25 #ifdef BCM_PETRA_SUPPORT 26 #include <soc/dpp/dpp_config_defs.h> 27 #endif 28 29 #ifdef BCM_PETRA_SUPPORT 30 #include <soc/dpp/ARAD/arad_dram.h> 31 #include <soc/dpp/ARAD/arad_api_mgmt.h> 32 #endif 33 34 #ifdef BCM_HURRICANE2_SUPPORT 35 #include <soc/iproc.h> 36 #endif 37 38 #ifdef BCM_DDR3_SUPPORT 39 #include <soc/shmoo_ddr40.h> 40 #include <soc/phy/ddr40.h> 41 42 #define DDR_TIMEOUT_10mS 1000 43 #define NUM_DATA 8 44 #define SET_UNOVR_STEP(v) ( 0x20000 | ( (v) & 0x3F ) ) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ 45 #define SET_OVR_STEP(v) ( 0x30000 | ( (v) & 0x3F ) ) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ 46 47 #define RD_EN_DQS_CORROLATION 2 48 #define MAX_SHMOO_INTERFACES 32 49 50 /*********************************************************************** 51 * DDR Initialization Functions 52 */ 53 54 static uint32 shmoo_dram_config = 0x00000000; 55 static uint32 dram0_clamshell_enable = 0; 56 static uint32 dram1_clamshell_enable = 0; 57 58 59 60 /* 61 drc_regs_table used to find the correct register id for each DR 62 this tabe must be coordinate with the enum drc_reg_set_e 63 */ 64 65 uint32 drc_regs_table[DRC_REG_COUNT][8] = { 66 { DRCA_BIST_CONFIGURATIONSr, DRCB_BIST_CONFIGURATIONSr, DRCC_BIST_CONFIGURATIONSr, DRCD_BIST_CONFIGURATIONSr, DRCE_BIST_CONFIGURATIONSr, DRCF_BIST_CONFIGURATIONSr, DRCG_BIST_CONFIGURATIONSr, DRCH_BIST_CONFIGURATIONSr}, 67 { DRCA_BIST_END_ADDRESSr, DRCB_BIST_END_ADDRESSr, DRCC_BIST_END_ADDRESSr, DRCD_BIST_END_ADDRESSr, DRCE_BIST_END_ADDRESSr, DRCF_BIST_END_ADDRESSr, DRCG_BIST_END_ADDRESSr, DRCH_BIST_END_ADDRESSr}, 68 { DRCA_BIST_ERROR_OCCURREDr, DRCB_BIST_ERROR_OCCURREDr, DRCC_BIST_ERROR_OCCURREDr, DRCD_BIST_ERROR_OCCURREDr, DRCE_BIST_ERROR_OCCURREDr, DRCF_BIST_ERROR_OCCURREDr, DRCG_BIST_ERROR_OCCURREDr, DRCH_BIST_ERROR_OCCURREDr}, 69 { DRCA_BIST_NUMBER_OF_ACTIONSr, DRCB_BIST_NUMBER_OF_ACTIONSr, DRCC_BIST_NUMBER_OF_ACTIONSr, DRCD_BIST_NUMBER_OF_ACTIONSr, DRCE_BIST_NUMBER_OF_ACTIONSr, DRCF_BIST_NUMBER_OF_ACTIONSr, DRCG_BIST_NUMBER_OF_ACTIONSr, DRCH_BIST_NUMBER_OF_ACTIONSr}, 70 { DRCA_BIST_PATTERN_WORD_0r, DRCB_BIST_PATTERN_WORD_0r, DRCC_BIST_PATTERN_WORD_0r, DRCD_BIST_PATTERN_WORD_0r, DRCE_BIST_PATTERN_WORD_0r, DRCF_BIST_PATTERN_WORD_0r, DRCG_BIST_PATTERN_WORD_0r, DRCH_BIST_PATTERN_WORD_0r}, 71 { DRCA_BIST_PATTERN_WORD_1r, DRCB_BIST_PATTERN_WORD_1r, DRCC_BIST_PATTERN_WORD_1r, DRCD_BIST_PATTERN_WORD_1r, DRCE_BIST_PATTERN_WORD_1r, DRCF_BIST_PATTERN_WORD_1r, DRCG_BIST_PATTERN_WORD_1r, DRCH_BIST_PATTERN_WORD_1r}, 72 { DRCA_BIST_PATTERN_WORD_2r, DRCB_BIST_PATTERN_WORD_2r, DRCC_BIST_PATTERN_WORD_2r, DRCD_BIST_PATTERN_WORD_2r, DRCE_BIST_PATTERN_WORD_2r, DRCF_BIST_PATTERN_WORD_2r, DRCG_BIST_PATTERN_WORD_2r, DRCH_BIST_PATTERN_WORD_2r}, 73 { DRCA_BIST_PATTERN_WORD_3r, DRCB_BIST_PATTERN_WORD_3r, DRCC_BIST_PATTERN_WORD_3r, DRCD_BIST_PATTERN_WORD_3r, DRCE_BIST_PATTERN_WORD_3r, DRCF_BIST_PATTERN_WORD_3r, DRCG_BIST_PATTERN_WORD_3r, DRCH_BIST_PATTERN_WORD_3r}, 74 { DRCA_BIST_PATTERN_WORD_4r, DRCB_BIST_PATTERN_WORD_4r, DRCC_BIST_PATTERN_WORD_4r, DRCD_BIST_PATTERN_WORD_4r, DRCE_BIST_PATTERN_WORD_4r, DRCF_BIST_PATTERN_WORD_4r, DRCG_BIST_PATTERN_WORD_4r, DRCH_BIST_PATTERN_WORD_4r}, 75 { DRCA_BIST_PATTERN_WORD_5r, DRCB_BIST_PATTERN_WORD_5r, DRCC_BIST_PATTERN_WORD_5r, DRCD_BIST_PATTERN_WORD_5r, DRCE_BIST_PATTERN_WORD_5r, DRCF_BIST_PATTERN_WORD_5r, DRCG_BIST_PATTERN_WORD_5r, DRCH_BIST_PATTERN_WORD_5r}, 76 { DRCA_BIST_PATTERN_WORD_6r, DRCB_BIST_PATTERN_WORD_6r, DRCC_BIST_PATTERN_WORD_6r, DRCD_BIST_PATTERN_WORD_6r, DRCE_BIST_PATTERN_WORD_6r, DRCF_BIST_PATTERN_WORD_6r, DRCG_BIST_PATTERN_WORD_6r, DRCH_BIST_PATTERN_WORD_6r}, 77 { DRCA_BIST_PATTERN_WORD_7r, DRCB_BIST_PATTERN_WORD_7r, DRCC_BIST_PATTERN_WORD_7r, DRCD_BIST_PATTERN_WORD_7r, DRCE_BIST_PATTERN_WORD_7r, DRCF_BIST_PATTERN_WORD_7r, DRCG_BIST_PATTERN_WORD_7r, DRCH_BIST_PATTERN_WORD_7r}, 78 { DRCA_BIST_START_ADDRESSr, DRCB_BIST_START_ADDRESSr, DRCC_BIST_START_ADDRESSr, DRCD_BIST_START_ADDRESSr, DRCE_BIST_START_ADDRESSr, DRCF_BIST_START_ADDRESSr, DRCG_BIST_START_ADDRESSr, DRCH_BIST_START_ADDRESSr}, 79 { DRCA_BIST_STATUSESr, DRCB_BIST_STATUSESr, DRCC_BIST_STATUSESr, DRCD_BIST_STATUSESr, DRCE_BIST_STATUSESr, DRCF_BIST_STATUSESr, DRCG_BIST_STATUSESr, DRCH_BIST_STATUSESr}, 80 { DRCA_DPI_STATUSr, DRCB_DPI_STATUSr, DRCC_DPI_STATUSr, DRCD_DPI_STATUSr, DRCE_DPI_STATUSr, DRCF_DPI_STATUSr, DRCG_DPI_STATUSr, DRCH_DPI_STATUSr}, 81 { DRCA_DRAM_INIT_FINISHEDr, DRCB_DRAM_INIT_FINISHEDr, DRCC_DRAM_INIT_FINISHEDr, DRCD_DRAM_INIT_FINISHEDr, DRCE_DRAM_INIT_FINISHEDr, DRCF_DRAM_INIT_FINISHEDr, DRCG_DRAM_INIT_FINISHEDr, DRCH_DRAM_INIT_FINISHEDr} 82 }; 83 84 85 86 87 const KATANAfreq_grade_mem_set_set_t KATANAfgmss[FREQ_COUNT][GRADE_COUNT] = 88 { 89 { /* FREQ_400 */ 90 /* GRADE_DEFAULT */ 91 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 92 /* GRADE_080808 */ 93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 94 /* GRADE_090909 */ 95 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 96 /* GRADE_101010 */ 97 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 98 /* GRADE_111111 */ 99 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 100 /* GRADE_121212 */ 101 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 102 /* GRADE_131313 */ 103 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 104 /* GRADE_141414 */ 105 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 106 }, 107 108 { /* FREQ_500 */ 109 /* GRADE_DEFAULT */ 110 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 111 /* GRADE_080808 */ 112 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 113 /* GRADE_090909 */ 114 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 115 /* GRADE_101010 */ 116 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 117 /* GRADE_111111 */ 118 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 119 /* GRADE_121212 */ 120 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 121 /* GRADE_131313 */ 122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 123 /* GRADE_141414 */ 124 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 125 }, 126 127 { /* FREQ_533 */ 128 /* GRADE_DEFAULT */ 129 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 130 /* GRADE_080808 */ 131 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 132 /* GRADE_090909 */ 133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 134 /* GRADE_101010 */ 135 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 136 /* GRADE_111111 */ 137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 138 /* GRADE_121212 */ 139 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 140 /* GRADE_131313 */ 141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 142 /* GRADE_141414 */ 143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 144 }, 145 146 { /* FREQ_667 */ 147 /* GRADE_DEFAULT */ 148 {10, 5, 17, 32, 48, 5, 8, 15, 11, 17, 24, 0, 0, 2600, 14, 18, {100, 54, 37}, 272, 9, 7, 10, 16, 667, 0x1b50, 0x0210}, 149 /* GRADE_080808 */ 150 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 151 /* GRADE_090909 */ 152 {10, 5, 17, 32, 48, 5, 8, 15, 11, 17, 24, 0, 0, 2600, 14, 18, {100, 54, 37}, 272, 9, 7, 10, 16, 667, 0x1b50, 0x0210}, 153 /* GRADE_101010 */ 154 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 155 /* GRADE_111111 */ 156 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 157 /* GRADE_121212 */ 158 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 159 /* GRADE_131313 */ 160 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 161 /* GRADE_141414 */ 162 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 163 }, 164 165 { /* FREQ_800 */ 166 /* GRADE_DEFAULT */ 167 {13, 6, 20, 32, 48, 6, 10, 16, 15, 20, 26, 0, 0, 3120, 16, 21, {120, 64, 44}, 272, 11, 8, 12, 21, 800, 0x1d70, 0x0218}, 168 /* GRADE_080808 */ 169 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 170 /* GRADE_090909 */ 171 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 172 /* GRADE_101010 */ 173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 174 /* GRADE_111111 */ 175 {13, 6, 20, 32, 48, 6, 10, 16, 15, 20, 26, 0, 0, 3120, 16, 21, {120, 64, 44}, 272, 11, 8, 12, 21, 800, 0x1d70, 0x0218}, 176 /* GRADE_121212 */ 177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 178 /* GRADE_131313 */ 179 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 180 /* GRADE_141414 */ 181 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 182 }, 183 184 { /* FREQ_914 */ 185 /* GRADE_DEFAULT */ 186 {16, 7, 22, 32, 48, 10, 14, 16, 19, 21, 29, 0, 0, 3565, 16, 26, {138, 74, 51}, 304, 13, 9, 14, 25, 914, 0x1f14, 0x0220}, 187 /* GRADE_080808 */ 188 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 189 /* GRADE_090909 */ 190 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 191 /* GRADE_101010 */ 192 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 193 /* GRADE_111111 */ 194 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 195 /* GRADE_121212 */ 196 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 197 /* GRADE_131313 */ 198 {16, 7, 22, 32, 48, 10, 14, 16, 19, 21, 29, 0, 0, 3565, 16, 26, {138, 74, 51}, 304, 13, 9, 14, 25, 914, 0x1f14, 0x0220}, 199 /* GRADE_141414 */ 200 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 201 }, 202 203 { /* FREQ_933 */ 204 /* GRADE_DEFAULT */ 205 {16, 7, 22, 32, 48, 10, 14, 17, 19, 21, 29, 0, 0, 3565, 16, 26, {138, 74, 51}, 304, 13, 9, 14, 25, 933, 0x1f14, 0x0220}, 206 /* GRADE_080808 */ 207 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 208 /* GRADE_090909 */ 209 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 210 /* GRADE_101010 */ 211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 212 /* GRADE_111111 */ 213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 214 /* GRADE_121212 */ 215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 216 /* GRADE_131313 */ 217 {16, 7, 22, 32, 48, 10, 14, 17, 19, 21, 29, 0, 0, 3565, 16, 26, {138, 74, 51}, 304, 13, 9, 14, 25, 933, 0x1f14, 0x0220}, 218 /* GRADE_141414 */ 219 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 220 }, 221 222 { /* FREQ_1066 */ 223 /* GRADE_DEFAULT */ 224 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 225 /* GRADE_080808 */ 226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 227 /* GRADE_090909 */ 228 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 229 /* GRADE_101010 */ 230 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 231 /* GRADE_111111 */ 232 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 233 /* GRADE_121212 */ 234 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 235 /* GRADE_131313 */ 236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1}, 237 /* GRADE_141414 */ 238 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, -1}, -1, -1, -1, -1, -1, -1, -1, -1} 239 } 240 }; 241 242 uint32 DRC_REG_READ(int unit, uint32 channel, drc_reg_set_t base, uint32 *rvp) 243 { 244 soc_reg_t reg = drc_regs_table[base][channel]; 245 246 return soc_reg32_get(unit, reg, REG_PORT_ANY, 0, rvp); 247 } 248 249 uint32 DRC_REG_WRITE(int unit, uint32 channel, drc_reg_set_t base, uint32 rv) 250 { 251 soc_reg_t reg = drc_regs_table[base][channel]; 252 253 return soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rv); 254 } 255 256 void 257 soc_ddr40_set_shmoo_dram_config(uint32 unit, uint32 dram_config) 258 { 259 shmoo_dram_config = dram_config; 260 } 261 262 uint32 263 _check_dram(int ci) 264 { 265 return (shmoo_dram_config & (0x1 << ci)); 266 } 267 268 uint32 269 _check_dram_either(int ci) 270 { 271 uint32 result; 272 273 result = _check_dram(ci); 274 275 if(ci & 0x1) { 276 result |= _check_dram(ci - 1); 277 } else { 278 result |= _check_dram(ci + 1); 279 } 280 281 return result; 282 } 283 284 uint32 285 _check_dram_both(int ci) 286 { 287 uint32 result; 288 289 if(_check_dram(ci)){ 290 result = 1; 291 } else { 292 result = 0; 293 } 294 295 if(ci & 0x1) { 296 if(!_check_dram(ci - 1)) { 297 result = 0; 298 } 299 } else { 300 if(!_check_dram(ci + 1)) { 301 result = 0; 302 } 303 } 304 305 return result; 306 } 307 308 void 309 _soc_ddr40_katana_phy_init_mem_set_wrapper(uint32 unit, KATANAfreq_grade_mem_set_set_t *fgmssPtr, int freq_loc, int grade_loc) 310 { 311 fgmssPtr->twl = KATANAfgmss[freq_loc][grade_loc].twl; 312 fgmssPtr->twr = KATANAfgmss[freq_loc][grade_loc].twr; 313 fgmssPtr->trc = KATANAfgmss[freq_loc][grade_loc].trc; 314 fgmssPtr->rfifo_afull = KATANAfgmss[freq_loc][grade_loc].rfifo_afull; 315 fgmssPtr->rfifo_full = KATANAfgmss[freq_loc][grade_loc].rfifo_full; 316 fgmssPtr->trtw = KATANAfgmss[freq_loc][grade_loc].trtw; 317 fgmssPtr->twtr = KATANAfgmss[freq_loc][grade_loc].twtr; 318 fgmssPtr->tfaw = KATANAfgmss[freq_loc][grade_loc].tfaw; 319 fgmssPtr->tread_enb = soc_property_get(unit,spn_DDR3_TREAD_ENB, KATANAfgmss[freq_loc][grade_loc].tread_enb); 320 fgmssPtr->bank_unavail_rd = soc_property_get(unit,spn_DDR3_BANK_UNAVAIL_RD, KATANAfgmss[freq_loc][grade_loc].bank_unavail_rd); 321 fgmssPtr->bank_unavail_wr = soc_property_get(unit,spn_DDR3_BANK_UNAVAIL_WR, KATANAfgmss[freq_loc][grade_loc].bank_unavail_wr); 322 fgmssPtr->rr_read = soc_property_get(unit,spn_DDR3_ROUND_ROBIN_READ, KATANAfgmss[freq_loc][grade_loc].rr_read); 323 fgmssPtr->rr_write = soc_property_get(unit,spn_DDR3_ROUND_ROBIN_WRITE, KATANAfgmss[freq_loc][grade_loc].rr_write); 324 fgmssPtr->refrate = soc_property_get(unit,spn_DDR3_REFRESH_INTVL_OVERRIDE, KATANAfgmss[freq_loc][grade_loc].refrate); 325 fgmssPtr->trp_read = soc_property_get(unit,spn_DDR3_TRP_READ, KATANAfgmss[freq_loc][grade_loc].trp_read); 326 fgmssPtr->trp_write = soc_property_get(unit,spn_DDR3_TRP_WRITE, KATANAfgmss[freq_loc][grade_loc].trp_write); 327 fgmssPtr->trfc[MEM_4G] = KATANAfgmss[freq_loc][grade_loc].trfc[MEM_4G]; 328 fgmssPtr->trfc[MEM_2G] = KATANAfgmss[freq_loc][grade_loc].trfc[MEM_2G]; 329 fgmssPtr->trfc[MEM_1G] = KATANAfgmss[freq_loc][grade_loc].trfc[MEM_1G]; 330 fgmssPtr->tzq = KATANAfgmss[freq_loc][grade_loc].tzq; 331 fgmssPtr->cl = KATANAfgmss[freq_loc][grade_loc].cl; 332 fgmssPtr->cwl = KATANAfgmss[freq_loc][grade_loc].cwl; 333 fgmssPtr->wr = KATANAfgmss[freq_loc][grade_loc].wr; 334 fgmssPtr->jedec = KATANAfgmss[freq_loc][grade_loc].jedec; 335 fgmssPtr->mhz = KATANAfgmss[freq_loc][grade_loc].mhz; 336 fgmssPtr->mr0 = KATANAfgmss[freq_loc][grade_loc].mr0; 337 fgmssPtr->mr2 = KATANAfgmss[freq_loc][grade_loc].mr2; 338 } 339 340 #if 0 /* Uncomment this when required */ 341 void 342 _soc_ddr40_arad_phy_init_mem_set_wrapper(uint32 unit, ARADfreq_grade_mem_set_set_t *fgmssPtr, int freq_loc, int grade_loc) 343 { 344 fgmssPtr->Jedec = ARADfgmss[freq_loc][grade_loc].Jedec; 345 fgmssPtr->Cl = ARADfgmss[freq_loc][grade_loc].Cl; 346 fgmssPtr->Cwl = ARADfgmss[freq_loc][grade_loc].Cwl; 347 fgmssPtr->Wr = ARADfgmss[freq_loc][grade_loc].Wr; 348 fgmssPtr->DdrMhz = ARADfgmss[freq_loc][grade_loc].DdrMhz; 349 fgmssPtr->ReadDataDelay = ARADfgmss[freq_loc][grade_loc].ReadDataDelay; 350 fgmssPtr->ModeRegWr1 = ARADfgmss[freq_loc][grade_loc].ModeRegWr1; 351 fgmssPtr->ModeRegWr2 = ARADfgmss[freq_loc][grade_loc].ModeRegWr2; 352 fgmssPtr->ExtModeWr1 = ARADfgmss[freq_loc][grade_loc].ExtModeWr1; 353 fgmssPtr->ExtModeWr2 = ARADfgmss[freq_loc][grade_loc].ExtModeWr2; 354 fgmssPtr->ExtModeWr3 = ARADfgmss[freq_loc][grade_loc].ExtModeWr3; 355 fgmssPtr->EMR2 = ARADfgmss[freq_loc][grade_loc].EMR2; 356 fgmssPtr->EMR3 = ARADfgmss[freq_loc][grade_loc].EMR3; 357 fgmssPtr->DDRtRST = ARADfgmss[freq_loc][grade_loc].DDRtRST; 358 fgmssPtr->DDRtDLL = ARADfgmss[freq_loc][grade_loc].DDRtDLL; 359 fgmssPtr->DDRtRC = ARADfgmss[freq_loc][grade_loc].DDRtRC; 360 fgmssPtr->DDRtRRD = ARADfgmss[freq_loc][grade_loc].DDRtRRD; 361 fgmssPtr->DDRtRFC = ARADfgmss[freq_loc][grade_loc].DDRtRFC; 362 fgmssPtr->DDRtRCDR = ARADfgmss[freq_loc][grade_loc].DDRtRCDR; 363 fgmssPtr->DDRtRCDW = ARADfgmss[freq_loc][grade_loc].DDRtRCDW; 364 fgmssPtr->InitWaitPRD = ARADfgmss[freq_loc][grade_loc].InitWaitPRD; 365 fgmssPtr->CntRASRDPRD = ARADfgmss[freq_loc][grade_loc].CntRASRDPRD; 366 fgmssPtr->CntRASWRPRD = ARADfgmss[freq_loc][grade_loc].CntRASWRPRD; 367 fgmssPtr->CntRDAPPRD = ARADfgmss[freq_loc][grade_loc].CntRDAPPRD; 368 fgmssPtr->CntWRAPPRD = ARADfgmss[freq_loc][grade_loc].CntWRAPPRD; 369 fgmssPtr->IndWrRdAddrMode = ARADfgmss[freq_loc][grade_loc].IndWrRdAddrMode; 370 fgmssPtr->NumCols = ARADfgmss[freq_loc][grade_loc].NumCols; 371 fgmssPtr->APBitPos = ARADfgmss[freq_loc][grade_loc].APBitPos; 372 fgmssPtr->RefreshBurstSize = ARADfgmss[freq_loc][grade_loc].RefreshBurstSize; 373 fgmssPtr->RefreshDelayPrd = ARADfgmss[freq_loc][grade_loc].RefreshDelayPrd; 374 fgmssPtr->DDRtZQCS = ARADfgmss[freq_loc][grade_loc].DDRtZQCS; 375 fgmssPtr->DDRtFAW = ARADfgmss[freq_loc][grade_loc].DDRtFAW; 376 fgmssPtr->CntRdPrd = ARADfgmss[freq_loc][grade_loc].CntRdPrd; 377 fgmssPtr->CntWrPrd = ARADfgmss[freq_loc][grade_loc].CntWrPrd; 378 fgmssPtr->Enable8Banks = ARADfgmss[freq_loc][grade_loc].Enable8Banks; 379 fgmssPtr->DDRResetPolarity = ARADfgmss[freq_loc][grade_loc].DDRResetPolarity; 380 fgmssPtr->StaticOdtEn = ARADfgmss[freq_loc][grade_loc].StaticOdtEn; 381 fgmssPtr->AddrTermHalf = ARADfgmss[freq_loc][grade_loc].AddrTermHalf; 382 fgmssPtr->DRAMType = ARADfgmss[freq_loc][grade_loc].DRAMType; 383 fgmssPtr->BurstSizeMode = ARADfgmss[freq_loc][grade_loc].BurstSizeMode; 384 fgmssPtr->WrLatency = ARADfgmss[freq_loc][grade_loc].WrLatency; 385 fgmssPtr->CntRDWRPRD = ARADfgmss[freq_loc][grade_loc].CntRDWRPRD; 386 fgmssPtr->CntWRRDPRD = ARADfgmss[freq_loc][grade_loc].CntWRRDPRD; 387 fgmssPtr->DDRtREFI = ARADfgmss[freq_loc][grade_loc].DDRtREFI; 388 fgmssPtr->DynOdtLength = ARADfgmss[freq_loc][grade_loc].DynOdtLength; 389 fgmssPtr->DynOdtStartDelay = ARADfgmss[freq_loc][grade_loc].DynOdtStartDelay; 390 fgmssPtr->DDR3ZQCalibGenPrd = ARADfgmss[freq_loc][grade_loc].DDR3ZQCalibGenPrd; 391 fgmssPtr->ReadDelay = ARADfgmss[freq_loc][grade_loc].ReadDelay; 392 fgmssPtr->IntialCalibMprAddr = ARADfgmss[freq_loc][grade_loc].IntialCalibMprAddr; 393 } 394 #endif 395 396 const size_mem_type_set_t smts[MEM_COUNT] = { 397 {0, 2}, /* MEM_4G, 14b */ 398 {1, 1}, /* MEM_2G, 13b */ 399 {2, 0} /* MEM_1G, 12b */ 400 }; 401 402 int 403 _soc_ddr40_mem_rowstoloc(uint32 rows) 404 { 405 switch(rows) { 406 case MEM_ROWS_32K: 407 return MEM_4G; 408 case MEM_ROWS_16K: 409 return MEM_2G; 410 default: 411 return MEM_1G; 412 } 413 } 414 415 int 416 _soc_ddr40_mem_gradetoloc(uint32 grade) 417 { 418 switch(grade) { 419 case MEM_GRADE_080808: 420 return GRADE_080808; 421 case MEM_GRADE_090909: 422 return GRADE_090909; 423 case MEM_GRADE_101010: 424 return GRADE_101010; 425 case MEM_GRADE_111111: 426 return GRADE_111111; 427 case MEM_GRADE_121212: 428 return GRADE_121212; 429 case MEM_GRADE_131313: 430 return GRADE_131313; 431 case MEM_GRADE_141414: 432 return GRADE_141414; 433 default: 434 return GRADE_DEFAULT; 435 } 436 } 437 438 const phy_freq_div_set_t pfds[PHY_COUNT][FREQ_COUNT] = { 439 /* 400 500 533 667 800 914 933 1066 */ 440 /* PHY_ RSVP */ {{-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}}, 441 /* PHY_ NS */ {{80,10}, {100,10}, {96,9}, {80,6}, {80,5}, {128,7}, {112,6}, {128,6}}, 442 /* PHY_ ENG */ {{80,10}, {100,10}, {96,9}, {80,6}, {80,5}, {128,7}, {168,9}, {192,9}}, 443 /* PHY_ AND */ {{80,10}, {100,10}, {96,9}, {80,6}, {128,8}, {128,7}, {112,6}, {128,6}}, 444 /* PHY_ CE */ {{-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}, {-1,-1}} 445 }; 446 447 int 448 _soc_ddr40_phy_freqtoloc(uint32 freq) 449 { 450 switch(freq) { 451 case DDR_FREQ_400: 452 return FREQ_400; 453 case DDR_FREQ_500: 454 return FREQ_500; 455 case DDR_FREQ_533: 456 return FREQ_533; 457 case DDR_FREQ_667: 458 return FREQ_667; 459 case DDR_FREQ_800: 460 return FREQ_800; 461 case DDR_FREQ_914: 462 return FREQ_914; 463 case DDR_FREQ_933: 464 return FREQ_933; 465 case DDR_FREQ_1066: 466 return FREQ_1066; 467 default: 468 if(freq > DDR_FREQ_1066) { 469 LOG_INFO(BSL_LS_SOC_DDR, 470 (BSL_META("Overclocking Frequency %d MHz \n"), 471 freq)); 472 return FREQ_1066; 473 } 474 LOG_ERROR(BSL_LS_SOC_COMMON, 475 (BSL_META("Unsupported Frequency %d MHz \n"), freq)); 476 return SOC_E_FAIL; 477 } 478 } 479 480 #if 1 /* Uncomment this when required */ 481 STATIC void 482 _shmoo_print_diagnostics(int unit, int ci, int wl) { 483 484 int x, y; 485 uint32 data; 486 487 x = 0x004C; 488 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 489 LOG_INFO(BSL_LS_SOC_DDR, 490 (BSL_META_U(unit, 491 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL CALIB STATUS\n"), 492 x, data)); 493 } else { 494 LOG_INFO(BSL_LS_SOC_DDR, 495 (BSL_META_U(unit, 496 "Address = 0x%04X\t\tERROR \t\tVDL CALIB STATUS\n"), 497 x)); 498 } 499 x = 0x0058; 500 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 501 LOG_INFO(BSL_LS_SOC_DDR, 502 (BSL_META_U(unit, 503 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL RD EN CALIB STATUS\n"), 504 x, data)); 505 } else { 506 LOG_INFO(BSL_LS_SOC_DDR, 507 (BSL_META_U(unit, 508 "Address = 0x%04X\t\tERROR \t\tVDL RD EN CALIB STATUS\n"), 509 x)); 510 } 511 x = 0x0050; 512 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 513 LOG_INFO(BSL_LS_SOC_DDR, 514 (BSL_META_U(unit, 515 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL DQ/DQS CALIB STATUS\n"), 516 x, data)); 517 } else { 518 LOG_INFO(BSL_LS_SOC_DDR, 519 (BSL_META_U(unit, 520 "Address = 0x%04X\t\tERROR \t\tVDL DQ/DQS CALIB STATUS\n"), 521 x)); 522 } 523 x = 0x0054; 524 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 525 LOG_INFO(BSL_LS_SOC_DDR, 526 (BSL_META_U(unit, 527 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL WR DQ CALIB STATUS\n"), 528 x, data)); 529 } else { 530 LOG_INFO(BSL_LS_SOC_DDR, 531 (BSL_META_U(unit, 532 "Address = 0x%04X\t\tERROR \t\tVDL WR DQ CALIB STATUS\n"), 533 x)); 534 } 535 x = 0x0030; 536 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 537 LOG_INFO(BSL_LS_SOC_DDR, 538 (BSL_META_U(unit, 539 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE CTL\n"), 540 x, data)); 541 } else { 542 LOG_INFO(BSL_LS_SOC_DDR, 543 (BSL_META_U(unit, 544 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE CTL\n"), 545 x)); 546 } 547 x = 0x0034; 548 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 549 LOG_INFO(BSL_LS_SOC_DDR, 550 (BSL_META_U(unit, 551 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BIT CTL\n"), 552 x, data)); 553 } else { 554 LOG_INFO(BSL_LS_SOC_DDR, 555 (BSL_META_U(unit, 556 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BIT CTL\n"), 557 x)); 558 } 559 x = 0x003C; 560 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 561 LOG_INFO(BSL_LS_SOC_DDR, 562 (BSL_META_U(unit, 563 "Address = 0x%04X\t\tData = 0x%08X\t\tZQ PVT COMP CTL\n"), 564 x, data)); 565 } else { 566 LOG_INFO(BSL_LS_SOC_DDR, 567 (BSL_META_U(unit, 568 "Address = 0x%04X\t\tERROR \t\tZQ PVT COMP CTL\n"), 569 x)); 570 } 571 x = 0x006C; 572 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 573 LOG_INFO(BSL_LS_SOC_DDR, 574 (BSL_META_U(unit, 575 "Address = 0x%04X\t\tData = 0x%08X\t\tVREF DAC CONTROL\n"), 576 x, data)); 577 } else { 578 LOG_INFO(BSL_LS_SOC_DDR, 579 (BSL_META_U(unit, 580 "Address = 0x%04X\t\tERROR \t\tVREF DAC CONTROL\n"), 581 x)); 582 } 583 if(wl == 0) { 584 y = 0; 585 } else { 586 y = 0x0200; 587 } 588 x = y + 0x0200; 589 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 590 LOG_INFO(BSL_LS_SOC_DDR, 591 (BSL_META_U(unit, 592 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE RD EN\n"), 593 x, data)); 594 } else { 595 LOG_INFO(BSL_LS_SOC_DDR, 596 (BSL_META_U(unit, 597 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE RD EN\n"), 598 x)); 599 } 600 x = y + 0x0274; 601 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 602 LOG_INFO(BSL_LS_SOC_DDR, 603 (BSL_META_U(unit, 604 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE0 BIT RD EN\n"), 605 x, data)); 606 } else { 607 LOG_INFO(BSL_LS_SOC_DDR, 608 (BSL_META_U(unit, 609 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE0 BIT RD EN\n"), 610 x)); 611 } 612 x = y + 0x0314; 613 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 614 LOG_INFO(BSL_LS_SOC_DDR, 615 (BSL_META_U(unit, 616 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE1 BIT RD EN\n"), 617 x, data)); 618 } else { 619 LOG_INFO(BSL_LS_SOC_DDR, 620 (BSL_META_U(unit, 621 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE1 BIT RD EN\n"), 622 x)); 623 } 624 x = y + 0x0234; 625 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 626 LOG_INFO(BSL_LS_SOC_DDR, 627 (BSL_META_U(unit, 628 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE0 BIT0 R DQ\n"), 629 x, data)); 630 } else { 631 LOG_INFO(BSL_LS_SOC_DDR, 632 (BSL_META_U(unit, 633 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE0 BIT0 R DQ\n"), 634 x)); 635 } 636 x = y + 0x02D4; 637 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 638 LOG_INFO(BSL_LS_SOC_DDR, 639 (BSL_META_U(unit, 640 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE1 BIT0 R DQ\n"), 641 x, data)); 642 } else { 643 LOG_INFO(BSL_LS_SOC_DDR, 644 (BSL_META_U(unit, 645 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE1 BIT0 R DQ\n"), 646 x)); 647 } 648 x = y + 0x0208; 649 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 650 LOG_INFO(BSL_LS_SOC_DDR, 651 (BSL_META_U(unit, 652 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE0 R DQS\n"), 653 x, data)); 654 } else { 655 LOG_INFO(BSL_LS_SOC_DDR, 656 (BSL_META_U(unit, 657 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE0 R DQS\n"), 658 x)); 659 } 660 x = y + 0x02A8; 661 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 662 LOG_INFO(BSL_LS_SOC_DDR, 663 (BSL_META_U(unit, 664 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE1 R DQS\n"), 665 x, data)); 666 } else { 667 LOG_INFO(BSL_LS_SOC_DDR, 668 (BSL_META_U(unit, 669 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE1 R DQS\n"), 670 x)); 671 } 672 x = y + 0x0204; 673 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 674 LOG_INFO(BSL_LS_SOC_DDR, 675 (BSL_META_U(unit, 676 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE0 WR DQ\n"), 677 x, data)); 678 } else { 679 LOG_INFO(BSL_LS_SOC_DDR, 680 (BSL_META_U(unit, 681 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE0 WR DQ\n"), 682 x)); 683 } 684 x = y + 0x0210; 685 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 686 LOG_INFO(BSL_LS_SOC_DDR, 687 (BSL_META_U(unit, 688 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE0 BIT WR DQ\n"), 689 x, data)); 690 } else { 691 LOG_INFO(BSL_LS_SOC_DDR, 692 (BSL_META_U(unit, 693 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE0 BIT WR DQ\n"), 694 x)); 695 } 696 x = y + 0x02A4; 697 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 698 LOG_INFO(BSL_LS_SOC_DDR, 699 (BSL_META_U(unit, 700 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE1 WR DQ\n"), 701 x, data)); 702 } else { 703 LOG_INFO(BSL_LS_SOC_DDR, 704 (BSL_META_U(unit, 705 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE1 WR DQ\n"), 706 x)); 707 } 708 x = y + 0x02B0; 709 if(DDR40_REG_READ(unit, ci, 0x00, x, &data) == SOC_E_NONE) { 710 LOG_INFO(BSL_LS_SOC_DDR, 711 (BSL_META_U(unit, 712 "Address = 0x%04X\t\tData = 0x%08X\t\tVDL OVRIDE BYTE1 BIT WR DQ\n"), 713 x, data)); 714 } else { 715 LOG_INFO(BSL_LS_SOC_DDR, 716 (BSL_META_U(unit, 717 "Address = 0x%04X\t\tERROR \t\tVDL OVRIDE BYTE1 BIT WR DQ\n"), 718 x)); 719 } 720 } 721 #endif 722 723 int _soc_ddr40_pll_calc(uint32 freq,int *ndiv, int *mdiv) { 724 725 uint32 m,n, diff, err, nval=0, mval=0; 726 727 err = freq; /* Maximum error */ 728 729 for (n=120; n>=60; n--) { 730 m = (n * 50 / freq); /* Round Down */ 731 diff = (50 * n / m) - freq; 732 if (diff < err) { 733 err = diff; 734 nval = n; 735 mval = m; 736 } 737 m++; /* Round Up */ 738 diff = freq - (50 * n / m); 739 if (diff < err) { 740 err = diff; 741 nval = n; 742 mval = m; 743 } 744 if (err == 0) { 745 break; 746 } 747 } 748 749 if ((ndiv != NULL) && (mdiv != NULL)) { 750 *ndiv = (int)nval; 751 *mdiv = (int)mval; 752 } 753 LOG_INFO(BSL_LS_SOC_DDR, 754 (BSL_META("Freq=%d n=%d m=%d err=%d\n"), 755 freq, nval, mval, err)); 756 return err; 757 } 758 759 int 760 soc_ddr40_phy_pll_ctl(int unit, int ci, uint32 freq, uint32 phyType, int stat) 761 { 762 uint32 rval; 763 sal_usecs_t to_val; 764 soc_timeout_t to; 765 uint32 pllfreq; 766 767 /* Per Speed & Grade Parameters */ 768 int ndiv, mdiv, freq_loc; 769 770 freq_loc = _soc_ddr40_phy_freqtoloc(freq); 771 772 if (freq_loc < 0) { 773 return SOC_E_INTERNAL; /* Unsupported Frequency */ 774 } 775 776 if (SAL_BOOT_QUICKTURN) { 777 to_val = 10000000; /* 10 Sec */ 778 } else { 779 to_val = 50000; /* 50 mS */ 780 } 781 782 ndiv = pfds[phyType][freq_loc].ndiv; 783 mdiv = pfds[phyType][freq_loc].mdiv; 784 785 pllfreq = soc_property_get(unit, spn_DDR3_PLL_MHZ, freq); 786 787 if (pllfreq != freq) { 788 _soc_ddr40_pll_calc(pllfreq, &ndiv, &mdiv); 789 } 790 791 if (!stat) { 792 switch(phyType) { 793 case DDR_PHYTYPE_RSVP: 794 break; 795 case DDR_PHYTYPE_NS: 796 if(SOC_IS_KATANA(unit)) { 797 LOG_INFO(BSL_LS_SOC_DDR, 798 (BSL_META_U(unit, 799 "A01. Reset DDR PLL\n"))); 800 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 801 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 802 TOP_DDR3_PLL_RST_Lf, 0); 803 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 804 TOP_DDR3_PLL_POST_RST_Lf, 0); 805 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 806 807 LOG_INFO(BSL_LS_SOC_DDR, 808 (BSL_META_U(unit, 809 "A02. Set PLL div.(mdiv/ndiv:%d/%d)\n"), 810 mdiv,ndiv)); 811 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit,DDR3_PLL_CTRL_REGISTER_3r, 812 REG_PORT_ANY, NDIV_INTf, ndiv)); 813 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit,DDR3_PLL_CTRL_REGISTER_4r, 814 REG_PORT_ANY, CH0_MDIVf, mdiv)); 815 816 LOG_INFO(BSL_LS_SOC_DDR, 817 (BSL_META_U(unit, 818 "A03. Unreset PLL (mdiv:%d ndiv:%d)\n"), 819 mdiv,ndiv)); 820 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 821 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 822 TOP_DDR3_PLL_RST_Lf, 1); 823 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 824 825 LOG_INFO(BSL_LS_SOC_DDR, 826 (BSL_META_U(unit, 827 "A04. Wait for PLL lock\n"))); 828 to_val = 50000; /* 50 mS */ 829 soc_timeout_init(&to, to_val, 0); 830 do { 831 SOC_IF_ERROR_RETURN(READ_DDR3_PLL_STATUSr(unit,&rval)); 832 if (soc_reg_field_get(unit, DDR3_PLL_STATUSr, rval, DDR3_PLL_LOCKf)) { 833 break; 834 } 835 if (soc_timeout_check(&to)) { 836 LOG_ERROR(BSL_LS_SOC_COMMON, 837 (BSL_META_U(unit, 838 "Timed out waiting for DDR3 PLL to Lock\n"))); 839 return SOC_E_TIMEOUT; 840 } 841 } while (TRUE); 842 843 LOG_INFO(BSL_LS_SOC_DDR, 844 (BSL_META_U(unit, 845 "A05. Unreset post PLL lock\n"))); 846 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 847 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_DDR3_PLL_POST_RST_Lf, 1); 848 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 849 } else { 850 LOG_INFO(BSL_LS_SOC_DDR, 851 (BSL_META_U(unit, 852 "A01. Reset DDR PLL\n"))); 853 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 854 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 855 TOP_DDR_PLL0_RST_Lf, 0); 856 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 857 TOP_DDR_PLL0_POST_RST_Lf, 0); 858 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 859 860 LOG_INFO(BSL_LS_SOC_DDR, 861 (BSL_META_U(unit, 862 "A02. Set PLL div.(mdiv/ndiv:%d/%d)\n"), 863 mdiv,ndiv)); 864 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit,TOP_DDR_PLL0_CTRL_REGISTER_3r, 865 REG_PORT_ANY, NDIV_INTf, ndiv)); 866 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit,TOP_DDR_PLL0_CTRL_REGISTER_4r, 867 REG_PORT_ANY, CH0_MDIVf, mdiv)); 868 869 LOG_INFO(BSL_LS_SOC_DDR, 870 (BSL_META_U(unit, 871 "A03. Unreset PLL (mdiv:%d ndiv:%d)\n"), 872 mdiv,ndiv)); 873 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 874 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 875 TOP_DDR_PLL0_RST_Lf, 1); 876 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 877 878 LOG_INFO(BSL_LS_SOC_DDR, 879 (BSL_META_U(unit, 880 "A04. Wait for PLL lock\n"))); 881 to_val = 50000; /* 50 mS */ 882 soc_timeout_init(&to, to_val, 0); 883 do { 884 SOC_IF_ERROR_RETURN(READ_TOP_DDR_PLL0_STATUSr(unit,&rval)); 885 if (soc_reg_field_get(unit, TOP_DDR_PLL0_STATUSr, rval, DDR_PLL0_LOCKf)) { 886 break; 887 } 888 if (soc_timeout_check(&to)) { 889 LOG_ERROR(BSL_LS_SOC_COMMON, 890 (BSL_META_U(unit, 891 "Timed out waiting for DDR3 PLL to Lock\n"))); 892 return SOC_E_TIMEOUT; 893 } 894 } while (TRUE); 895 896 LOG_INFO(BSL_LS_SOC_DDR, 897 (BSL_META_U(unit, 898 "A05. Unreset post PLL lock\n"))); 899 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 900 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_DDR_PLL0_POST_RST_Lf, 1); 901 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 902 } 903 904 LOG_INFO(BSL_LS_SOC_DDR, 905 (BSL_META_U(unit, 906 "A06. Wait for a while after lock\n"))); 907 sal_usleep(2000); 908 break; 909 case DDR_PHYTYPE_ENG: 910 /* SOC_DEBUG(SOC_DBG_DDR, ("A01. Reset DPRC\n")); 911 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, DRCALL, DRC_SPARE_REGISTER_3r, &rval)); 912 soc_reg_field_set(unit, DRCBROADCAST_SPARE_REGISTER_3r, &rval, 913 DPRC_ALIGN_PHY_RSTNf, 0); 914 soc_reg_field_set(unit, DRCBROADCAST_SPARE_REGISTER_3r, &rval, 915 CLK_DIV_RSTNf, 0); 916 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, DRCALL, DRC_SPARE_REGISTER_3r, rval)); 917 918 SOC_DEBUG(SOC_DBG_DDR, ("A02. Bypass PLL mode\n")); 919 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, DRCALL, DRC_DPI_POWERr, &rval)); 920 soc_reg_field_set(unit, DRCBROADCAST_DPI_POWERr, &rval, 921 BYPASS_PLLf, 0); 922 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, DRCALL, DRC_DPI_POWERr, rval)); 923 924 SOC_DEBUG(SOC_DBG_DDR, ("A02. Set PLL div.(mdiv/ndiv:%d/%d)\n",mdiv,ndiv)); 925 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit,DDR3_PLL_CTRL_REGISTER_3r, 926 REG_PORT_ANY, NDIV_INTf, ndiv)); 927 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit,DDR3_PLL_CTRL_REGISTER_4r, 928 REG_PORT_ANY, CH0_MDIVf, mdiv)); 929 930 SOC_DEBUG(SOC_DBG_DDR, ("A03. Enable clock dividers\n")); 931 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, DRCALL, DRC_SPARE_REGISTER_3r, &rval)); 932 soc_reg_field_set(unit, DRCBROADCAST_SPARE_REGISTER_3r, &rval, 933 CLK_DIV_RSTNf, 1); 934 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, DRCALL, DRC_SPARE_REGISTER_3r, rval)); 935 936 SOC_DEBUG(SOC_DBG_DDR, ("A04. Wait for a while after clock divider enable\n")); 937 sal_usleep(2000); 938 939 SOC_DEBUG(SOC_DBG_DDR, ("A05. Unreset DPRC\n")); 940 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, DRCALL, DRC_SPARE_REGISTER_3r, &rval)); 941 soc_reg_field_set(unit, DRCBROADCAST_SPARE_REGISTER_3r, &rval, 942 DPRC_ALIGN_PHY_RSTNf, 1); 943 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, DRCALL, DRC_SPARE_REGISTER_3r, rval)); 944 945 SOC_DEBUG(SOC_DBG_DDR, ("A06. Wait for a while after clock divider enable\n")); 946 sal_usleep(2000); */ 947 break; 948 case DDR_PHYTYPE_CE: 949 break; 950 case DDR_PHYTYPE_HR2: 951 break; 952 default: 953 LOG_ERROR(BSL_LS_SOC_COMMON, 954 (BSL_META_U(unit, 955 "Error. Unsupported PHY type\n"))); 956 return SOC_E_FAIL; 957 } 958 } else { 959 /* report only */ 960 switch(phyType) { 961 case DDR_PHYTYPE_RSVP: 962 break; 963 case DDR_PHYTYPE_NS: 964 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 965 LOG_CLI((BSL_META_U(unit, 966 "TOP_SOFT_RESET_REG:%x\n"), rval)); 967 SOC_IF_ERROR_RETURN(READ_DDR3_PLL_CTRL_REGISTER_3r(unit,&rval)); 968 LOG_CLI((BSL_META_U(unit, 969 "DDR3_PLL_CTRL_REGISTER_3r:%x\n"), rval)); 970 SOC_IF_ERROR_RETURN(READ_DDR3_PLL_CTRL_REGISTER_4r(unit,&rval)); 971 LOG_CLI((BSL_META_U(unit, 972 "DDR3_PLL_CTRL_REGISTER_4r:%x\n"), rval)); 973 break; 974 case DDR_PHYTYPE_ENG: 975 break; 976 case DDR_PHYTYPE_CE: 977 break; 978 case DDR_PHYTYPE_HR2: 979 break; 980 default: 981 LOG_ERROR(BSL_LS_SOC_COMMON, 982 (BSL_META_U(unit, 983 "Error. Unsupported PHY type\n"))); 984 return SOC_E_FAIL; 985 } 986 } 987 988 return SOC_E_NONE; 989 } 990 991 /*********************************************************************** 992 * Function to reset the PLL. Will reset the PLL. 993 */ 994 int 995 soc_ddr40_phy_pll_rst (int unit, int ci, uint32 phyType, int cnt) 996 { 997 int i = 0; 998 int intCnt; 999 uint32 rval; 1000 1001 if(cnt == 0) { 1002 intCnt = 1; 1003 } else { 1004 intCnt = cnt; 1005 } 1006 1007 for(i = 0; i < intCnt; i++) { 1008 switch(phyType) { 1009 case DDR_PHYTYPE_RSVP: 1010 break; 1011 case DDR_PHYTYPE_NS: 1012 LOG_INFO(BSL_LS_SOC_DDR, 1013 (BSL_META_U(unit, 1014 "A1. Reset DDR(ci=%d PLL(Iter=%d)\n"), 1015 ci,i)); 1016 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 1017 soc_reg_field_set(unit,TOP_SOFT_RESET_REG_2r, &rval, 1018 TOP_DDR3_PLL_RST_Lf, 0); 1019 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 1020 TOP_DDR3_PLL_POST_RST_Lf, 0); 1021 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 1022 1023 sal_usleep(2000); 1024 1025 LOG_INFO(BSL_LS_SOC_DDR, 1026 (BSL_META_U(unit, 1027 "A2. Unreset DDR(ci=%d PLL(Iter=%d)\n"), 1028 ci,i)); 1029 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit,&rval)); 1030 soc_reg_field_set(unit,TOP_SOFT_RESET_REG_2r,&rval, 1031 TOP_DDR3_PLL_RST_Lf, 1); 1032 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit,rval)); 1033 break; 1034 case DDR_PHYTYPE_ENG: 1035 break; 1036 case DDR_PHYTYPE_CE: 1037 break; 1038 case DDR_PHYTYPE_HR2: 1039 break; 1040 default: 1041 LOG_ERROR(BSL_LS_SOC_COMMON, 1042 (BSL_META_U(unit, 1043 "Error. Unsupported PHY type\n"))); 1044 return SOC_E_FAIL; 1045 } 1046 } 1047 1048 return SOC_E_NONE; 1049 } 1050 1051 /*********************************************************************** 1052 * Functions to set/report the PVT params 1053 */ 1054 int 1055 _soc_ddr40_phy_PVT_ctl(int unit, int ci, uint32 phyType, int stat) 1056 { 1057 /* WORKS ON ONLY ONE CI; DOES NOT ITERATE OVER ALL CIs. */ 1058 /* ONLY EVEN CIs SHOULD BE PASSED */ 1059 1060 uint32 rval; 1061 sal_usecs_t to_val; 1062 soc_timeout_t to; 1063 1064 /* uint32 mhz; */ 1065 int ciC; 1066 /* uint32 data; */ 1067 1068 if (!stat) { 1069 switch(phyType) { 1070 case DDR_PHYTYPE_RSVP: 1071 break; 1072 case DDR_PHYTYPE_NS: 1073 case DDR_PHYTYPE_ENG: 1074 case DDR_PHYTYPE_HR2: 1075 if (SAL_BOOT_QUICKTURN) { 1076 to_val = 10000000; /* 10 Sec */ 1077 } else { 1078 to_val = 50000; /* 50 mS */ 1079 } 1080 1081 ciC = ci & 0xFFFFFFFE; 1082 1083 LOG_INFO(BSL_LS_SOC_DDR, 1084 (BSL_META_U(unit, 1085 "E01. Reset Vref before Shmoo\n"))); 1086 rval = 0x820; 1087 SOC_IF_ERROR_RETURN(MODIFY_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ciC, rval, 0xFFF)); 1088 1089 LOG_INFO(BSL_LS_SOC_DDR, 1090 (BSL_META_U(unit, 1091 "D04. Calibrate ZQ (ddr40_phy_calib_zq) before Shmoo\n"))); 1092 1093 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1094 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,0); 1095 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 1096 1097 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1098 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,1); 1099 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 1100 1101 soc_timeout_init(&to, to_val, 0); 1102 do { 1103 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1104 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, ZQ_PVT_COMP_CTL, SAMPLE_DONE)) { 1105 break; 1106 } 1107 if (soc_timeout_check(&to)) { 1108 LOG_ERROR(BSL_LS_SOC_COMMON, 1109 (BSL_META_U(unit, 1110 "CI%d: Timed out waiting for ZQ Calibration\n"), ciC)); 1111 return SOC_E_TIMEOUT; 1112 } 1113 } while (TRUE); 1114 1115 /* SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,0,&data)); 1116 mhz = soc_reg_field_get(unit, CI_PHY_CONTROLr, data, DDR_MHZf); 1117 mhz = SOC_DDR3_CLOCK_MHZ(unit); 1118 */ 1119 1120 if (!SAL_BOOT_QUICKTURN) { 1121 uint32 rd_en_byte_mode=0, rd_en_byte_vdl_steps=0, rd_en_bit_vdl_offset=0; 1122 1123 LOG_INFO(BSL_LS_SOC_DDR, 1124 (BSL_META_U(unit, 1125 "D07. VDL Calibration before Shmoo\n"))); 1126 rval = 0; 1127 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 1128 1129 rval = 0; 1130 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_FAST,1); 1131 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_ONCE,1); 1132 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_AUTO,1); 1133 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 1134 soc_timeout_init(&to, to_val, 0); 1135 do { 1136 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1137 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 1138 break; 1139 } 1140 if (soc_timeout_check(&to)) { 1141 LOG_ERROR(BSL_LS_SOC_COMMON, 1142 (BSL_META_U(unit, 1143 "CI%d: Timed out waiting for VDL Calibration Idle\n"), ciC)); 1144 return SOC_E_TIMEOUT; 1145 } 1146 } while (TRUE); 1147 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1148 if (soc_property_get(unit, spn_DIAG_EMULATOR_PARTIAL_INIT, 0x0) == 0) { 1149 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 1150 LOG_ERROR(BSL_LS_SOC_COMMON, 1151 (BSL_META_U(unit, 1152 "CI%d: VDL Calibration Did Not Lock reg=%x \n"), ciC, rval)); 1153 return SOC_E_FAIL; 1154 } 1155 } 1156 1157 LOG_INFO(BSL_LS_SOC_DDR, 1158 (BSL_META_U(unit, 1159 "VDL calibration result: 0x%0x (cal_steps = %d)\n"), 1160 rval, DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_TOTAL) >> 4)); 1161 1162 /* clear VDL calib control */ 1163 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,0)); 1164 1165 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(unit,ciC,&rval)); 1166 1167 rd_en_byte_mode = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BYTE_SEL); 1168 rd_en_byte_vdl_steps = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_TOTAL) >> 4; 1169 rd_en_bit_vdl_offset = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BIT_OFFSET); 1170 COMPILER_REFERENCE(rd_en_byte_mode); 1171 COMPILER_REFERENCE(rd_en_byte_vdl_steps); 1172 COMPILER_REFERENCE(rd_en_bit_vdl_offset); 1173 1174 soc_timeout_init(&to, to_val, 0); 1175 do { 1176 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1177 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 1178 break; 1179 } 1180 if (soc_timeout_check(&to)) { 1181 LOG_ERROR(BSL_LS_SOC_COMMON, 1182 (BSL_META_U(unit, 1183 "CI%d: Timed out waiting for VDL Calibration Idle(1)\n"), ciC)); 1184 return SOC_E_TIMEOUT; 1185 } 1186 } while (TRUE); 1187 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1188 if (soc_property_get(unit, spn_DIAG_EMULATOR_PARTIAL_INIT, 0x0) == 0) { 1189 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 1190 LOG_ERROR(BSL_LS_SOC_COMMON, 1191 (BSL_META_U(unit, 1192 "CI%d: VDL Calibration Did Not Lock(1)\n"), ciC)); 1193 return SOC_E_FAIL; 1194 } 1195 } 1196 } else { 1197 LOG_INFO(BSL_LS_SOC_DDR, 1198 (BSL_META_U(unit, 1199 "D07. VDL Calibration SKIPPED before Shmoo\n"))); 1200 }/* Not QUICKTURN */ 1201 break; 1202 case DDR_PHYTYPE_CE: 1203 break; 1204 default: 1205 LOG_ERROR(BSL_LS_SOC_COMMON, 1206 (BSL_META_U(unit, 1207 "Error. Unsupported PHY type\n"))); 1208 return SOC_E_FAIL; 1209 } 1210 } else { 1211 /* report only */ 1212 switch(phyType) { 1213 case DDR_PHYTYPE_RSVP: 1214 break; 1215 case DDR_PHYTYPE_NS: 1216 break; 1217 case DDR_PHYTYPE_ENG: 1218 break; 1219 case DDR_PHYTYPE_CE: 1220 break; 1221 case DDR_PHYTYPE_HR2: 1222 break; 1223 default: 1224 LOG_ERROR(BSL_LS_SOC_COMMON, 1225 (BSL_META_U(unit, 1226 "Error. Unsupported PHY type\n"))); 1227 return SOC_E_FAIL; 1228 } 1229 } 1230 return SOC_E_NONE; 1231 } 1232 1233 /*********************************************************************** 1234 * Functions to Calibrate the PHY 1235 */ 1236 int 1237 soc_ddr40_phy_calibrate(int unit, int ci, uint32 phyType, int stat) 1238 { 1239 uint32 rval; 1240 /* uint64 rval64; */ 1241 soc_timeout_t to; 1242 sal_usecs_t to_val; 1243 /* int mhz; CI_PHY_CONTROL */ 1244 int ciC, ciCS, ciCM; 1245 /* uint32 data; */ 1246 uint32 mr0, mr1, mr2, mr3; 1247 1248 KATANAfreq_grade_mem_set_set_t T0fgmss; 1249 /* ARADfreq_grade_mem_set_set_t ENGfgmss; */ 1250 /* int grade_loc; */ 1251 int freq_loc, grade_loc; 1252 1253 freq_loc = _soc_ddr40_phy_freqtoloc(SOC_DDR3_CLOCK_MHZ(unit)); 1254 grade_loc = _soc_ddr40_mem_gradetoloc(SOC_DDR3_MEM_GRADE(unit)); 1255 1256 if (freq_loc < 0) { 1257 return SOC_E_INTERNAL; /* Unsupported Frequency */ 1258 } 1259 1260 if (SAL_BOOT_QUICKTURN) { 1261 to_val = 10000000; /* 10 Sec */ 1262 } else { 1263 to_val = 50000; /* 50 mS */ 1264 } 1265 1266 if (!stat) { 1267 switch(phyType) { 1268 case DDR_PHYTYPE_RSVP: 1269 break; 1270 case DDR_PHYTYPE_NS: 1271 _soc_ddr40_katana_phy_init_mem_set_wrapper(unit, &T0fgmss, freq_loc, grade_loc); 1272 if (T0fgmss.mhz == -1) { 1273 return SOC_E_INTERNAL; /* Unsupported Frequency / Grade Combination */ 1274 } 1275 1276 LOG_INFO(BSL_LS_SOC_DDR, 1277 (BSL_META_U(unit, 1278 "C01. Check Power Up Reset_Bar\n"))); 1279 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1280 if(!_check_dram_either(ciC)) { 1281 continue; 1282 } 1283 soc_timeout_init(&to, to_val, 0); 1284 do { 1285 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,ciC,&rval)); 1286 if (soc_reg_field_get(unit, CI_PHY_CONTROLr, rval, PWRUP_RSBf )) { 1287 break; 1288 } 1289 if (soc_timeout_check(&to)) { 1290 LOG_ERROR(BSL_LS_SOC_COMMON, 1291 (BSL_META_U(unit, 1292 "CI%d: Timed out waiting for DDR PHY to Power Up\n"), ciC)); 1293 return SOC_E_TIMEOUT; 1294 } 1295 } while (TRUE); 1296 } 1297 1298 LOG_INFO(BSL_LS_SOC_DDR, 1299 (BSL_META_U(unit, 1300 "C02. Config and Release PLL from reset\n"))); 1301 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1302 if(!_check_dram_either(ciC)) { 1303 continue; 1304 } 1305 /* Divider */ 1306 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(unit,ciC,&rval)); 1307 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_DIVIDERS,NDIV,16); 1308 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_DIVIDERS,POST_DIV,1); 1309 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(unit,ciC,rval)); 1310 /* Reset */ 1311 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,&rval)); 1312 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,0); 1313 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 1314 1315 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,&rval)); 1316 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,1); 1317 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 1318 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,0); 1319 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 1320 } 1321 1322 LOG_INFO(BSL_LS_SOC_DDR, 1323 (BSL_META_U(unit, 1324 "C03. Poll PLL Lock\n"))); 1325 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1326 if(!_check_dram_either(ciC)) { 1327 continue; 1328 } 1329 soc_timeout_init(&to, to_val, 0); 1330 do { 1331 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_STATUSr(unit,ciC,&rval)); 1332 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, PLL_STATUS, LOCK)) { 1333 break; 1334 } 1335 if (soc_timeout_check(&to)) { 1336 LOG_ERROR(BSL_LS_SOC_COMMON, 1337 (BSL_META_U(unit, 1338 "CI%d: Timed out waiting for DDR PHY PLL to Lock\n"), ciC)); 1339 return SOC_E_TIMEOUT; 1340 } 1341 } while (TRUE); 1342 } 1343 1344 LOG_INFO(BSL_LS_SOC_DDR, 1345 (BSL_META_U(unit, 1346 "C04. Calibrate ZQ (ddr40_phy_calib_zq)\n"))); 1347 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1348 if(!_check_dram_either(ciC)) { 1349 continue; 1350 } 1351 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1352 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,0); 1353 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 1354 1355 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1356 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,1); 1357 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 1358 } 1359 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1360 if(!_check_dram_either(ciC)) { 1361 continue; 1362 } 1363 soc_timeout_init(&to, to_val, 0); 1364 do { 1365 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1366 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, ZQ_PVT_COMP_CTL, SAMPLE_DONE)) { 1367 break; 1368 } 1369 if (soc_timeout_check(&to)) { 1370 LOG_ERROR(BSL_LS_SOC_COMMON, 1371 (BSL_META_U(unit, 1372 "CI%d: Timed out waiting for ZQ Calibration\n"), ciC)); 1373 return SOC_E_TIMEOUT; 1374 } 1375 } while (TRUE); 1376 } 1377 1378 LOG_INFO(BSL_LS_SOC_DDR, 1379 (BSL_META_U(unit, 1380 "C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT\n"))); 1381 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1382 if(!_check_dram_either(ciC)) { 1383 continue; 1384 } 1385 rval = 0x3f1ffff; /* all bits except RESET and CKE */ 1386 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(unit,ciC,rval)); 1387 1388 rval = 0; /* AGUTMANN disable VTT override , previously 0x1ffff; */ 1389 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(unit,ciC,rval)); 1390 1391 } 1392 1393 LOG_INFO(BSL_LS_SOC_DDR, 1394 (BSL_META_U(unit, 1395 "C06. DDR40_PHY_DDR3_MISC\n"))); 1396 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1397 if(!_check_dram_either(ciC)) { 1398 continue; 1399 } 1400 rval = 0; 1401 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,VDDO_VOLTS,1); 1402 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,RT120B_G,1); 1403 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,RT60B,1); 1404 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(unit,ciC,rval)); 1405 1406 rval = 0; 1407 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,VDDO_VOLTS,1); 1408 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,RT120B_G,1); 1409 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTLr(unit,ciC,rval)); 1410 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTLr(unit,ciC,rval)); 1411 } 1412 1413 /* SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,0,&data)); 1414 mhz = soc_reg_field_get(unit, CI_PHY_CONTROLr, data, DDR_MHZf); 1415 mhz = SOC_DDR3_CLOCK_MHZ(unit); 1416 */ 1417 1418 if (!SAL_BOOT_QUICKTURN) { 1419 uint32 rd_en_byte_mode=0, rd_en_byte_vdl_steps=0, rd_en_bit_vdl_offset=0; 1420 1421 LOG_INFO(BSL_LS_SOC_DDR, 1422 (BSL_META_U(unit, 1423 "C07. VDL Calibration\n"))); 1424 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1425 if(!_check_dram_either(ciC)) { 1426 continue; 1427 } 1428 rval = 0; 1429 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 1430 1431 rval = 0; 1432 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_FAST,1); 1433 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_ONCE,1); 1434 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_AUTO,1); 1435 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 1436 } 1437 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1438 if(!_check_dram_either(ciC)) { 1439 continue; 1440 } 1441 soc_timeout_init(&to, to_val, 0); 1442 do { 1443 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1444 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 1445 break; 1446 } 1447 if (soc_timeout_check(&to)) { 1448 LOG_ERROR(BSL_LS_SOC_COMMON, 1449 (BSL_META_U(unit, 1450 "CI%d: Timed out waiting for VDL Calibration Idle\n"), ciC)); 1451 return SOC_E_TIMEOUT; 1452 } 1453 } while (TRUE); 1454 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1455 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 1456 LOG_ERROR(BSL_LS_SOC_COMMON, 1457 (BSL_META_U(unit, 1458 "CI%d: VDL Calibration Did Not Lock reg=%x \n"), ciC, rval)); 1459 return SOC_E_FAIL; 1460 } 1461 1462 LOG_INFO(BSL_LS_SOC_DDR, 1463 (BSL_META_U(unit, 1464 "VDL calibration result: 0x%0x (cal_steps = %d)\n"), 1465 rval, DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_TOTAL) >> 4)); 1466 1467 /* clear VDL calib control */ 1468 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,0)); 1469 1470 } 1471 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1472 if(!_check_dram_either(ciC)) { 1473 continue; 1474 } 1475 1476 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(unit,ciC,&rval)); 1477 1478 rd_en_byte_mode = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BYTE_SEL); 1479 rd_en_byte_vdl_steps = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_TOTAL) >> 4; 1480 rd_en_bit_vdl_offset = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BIT_OFFSET); 1481 1482 COMPILER_REFERENCE(rd_en_byte_mode); 1483 COMPILER_REFERENCE(rd_en_byte_vdl_steps); 1484 COMPILER_REFERENCE(rd_en_bit_vdl_offset); 1485 1486 /* rval = 0; 1487 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ci,rval)); 1488 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_STEPS,1); 1489 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ci,rval)); 1490 */ 1491 } 1492 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1493 if(!_check_dram_either(ciC)) { 1494 continue; 1495 } 1496 soc_timeout_init(&to, to_val, 0); 1497 do { 1498 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1499 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 1500 break; 1501 } 1502 if (soc_timeout_check(&to)) { 1503 LOG_ERROR(BSL_LS_SOC_COMMON, 1504 (BSL_META_U(unit, 1505 "CI%d: Timed out waiting for VDL Calibration Idle(1)\n"), ciC)); 1506 return SOC_E_TIMEOUT; 1507 } 1508 } while (TRUE); 1509 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 1510 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 1511 LOG_ERROR(BSL_LS_SOC_COMMON, 1512 (BSL_META_U(unit, 1513 "CI%d: VDL Calibration Did Not Lock(1)\n"), ciC)); 1514 return SOC_E_FAIL; 1515 } 1516 } 1517 } else { 1518 LOG_INFO(BSL_LS_SOC_DDR, 1519 (BSL_META_U(unit, 1520 "C07. VDL Calibration SKIPPED\n"))); 1521 }/* Not QUICKTURN */ 1522 1523 LOG_INFO(BSL_LS_SOC_DDR, 1524 (BSL_META_U(unit, 1525 "C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....\n"))); 1526 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1527 if(!_check_dram_either(ciC)) { 1528 continue; 1529 } 1530 rval = 0; 1531 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_DATA_DLY,RD_DATA_DLY, 1532 (SOC_DDR3_CLOCK_MHZ(unit) <= 400) ? 1 : (SOC_DDR3_CLOCK_MHZ(unit) <= 667) ? 2 : 3); 1533 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit,ciC,rval)); 1534 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit,ciC,rval)); 1535 1536 rval = 0; 1537 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_ENABLE,1); 1538 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_LE_ADJ,1); 1539 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_TE_ADJ,1); 1540 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_READ_CONTROLr(unit,ciC,rval)); 1541 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_READ_CONTROLr(unit,ciC,rval)); 1542 1543 if(SOC_DDR3_CLOCK_MHZ(unit) > 800) { 1544 rval = 3; 1545 } else { 1546 rval = 1; 1547 } 1548 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODEr(unit,ciC,rval)); 1549 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODEr(unit,ciC,rval)); 1550 } 1551 1552 LOG_INFO(BSL_LS_SOC_DDR, 1553 (BSL_META_U(unit, 1554 "C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....\n"))); 1555 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1556 if(!_check_dram_either(ciC)) { 1557 continue; 1558 } 1559 rval = 0; 1560 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,IDLE_PAD_CONTROL,AUTO_DQ_IDDQ_MODE,1); 1561 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,IDLE_PAD_CONTROL,AUTO_DQ_RXENB_MODE,1); 1562 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROLr(unit,ciC,rval)); 1563 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROLr(unit,ciC,rval)); 1564 } 1565 1566 LOG_INFO(BSL_LS_SOC_DDR, 1567 (BSL_META_U(unit, 1568 "C10. Set refresh count to 7.8us\n"))); 1569 /* Set refresh count to 7.8us (by the time it starts, it already finishes MRS and ZQCal setting) */ 1570 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 1571 if(!_check_dram(ciC)) { 1572 continue; 1573 } 1574 SOC_IF_ERROR_RETURN(READ_CI_CONFIG4r(unit,ciC,&rval)); 1575 soc_reg_field_set(unit, CI_CONFIG4r, &rval, REFRESH_INTERVALf, T0fgmss.refrate); 1576 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG4r(unit,ciC,rval)); 1577 } 1578 sal_usleep(2000); 1579 1580 LOG_INFO(BSL_LS_SOC_DDR, 1581 (BSL_META_U(unit, 1582 "C11. Set CKE (clock enable)\n"))); 1583 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 1584 if(!_check_dram(ciC)) { 1585 continue; 1586 } 1587 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,ciC,&rval)); 1588 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, AUTO_INITf, 0); 1589 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, CKEf, 0x3); 1590 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit,ciC,rval)); 1591 } 1592 sal_usleep(1000); 1593 1594 LOG_INFO(BSL_LS_SOC_DDR, 1595 (BSL_META_U(unit, 1596 "C12. Wait for Phy Ready\n"))); 1597 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1598 if(!_check_dram_either(ciC)) { 1599 continue; 1600 } 1601 soc_timeout_init(&to, to_val, 0); 1602 do { 1603 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,ciC,&rval)); 1604 if (soc_reg_field_get(unit, CI_PHY_CONTROLr, rval, READYf)) { 1605 break; 1606 } 1607 if (soc_timeout_check(&to)) { 1608 LOG_ERROR(BSL_LS_SOC_COMMON, 1609 (BSL_META_U(unit, 1610 "CI%d: Timed out waiting for PHY Ready\n"), ciC)); 1611 return SOC_E_TIMEOUT; 1612 } 1613 } while (TRUE); 1614 } 1615 1616 LOG_INFO(BSL_LS_SOC_DDR, 1617 (BSL_META_U(unit, 1618 "C13. CI DDR Init : MR0, MR1, MR2, and MR3 command\n"))); 1619 dram0_clamshell_enable = soc_property_get(unit, spn_DRAM0_CLAMSHELL_ENABLE, 0); 1620 dram1_clamshell_enable = soc_property_get(unit, spn_DRAM1_CLAMSHELL_ENABLE, 0); 1621 1622 if(dram0_clamshell_enable || dram1_clamshell_enable) { 1623 LOG_INFO(BSL_LS_SOC_DDR, 1624 (BSL_META_U(unit, 1625 " Manual Init\n"))); 1626 1627 if(dram0_clamshell_enable) { 1628 if(dram1_clamshell_enable) { 1629 LOG_ERROR(BSL_LS_SOC_COMMON, 1630 (BSL_META_U(unit, 1631 "Illegal clam shell configuration\n"))); 1632 return SOC_E_FAIL; 1633 } 1634 1635 ciCM = 0; /* Only Even CIs Mirrored */ 1636 ciCS = 1; /* Only Odd CIs Straight */ 1637 } else { 1638 ciCM = 1; /* Only Odd CIs Mirrored */ 1639 ciCS = 0; /* Only Even CIs Straight */ 1640 } 1641 1642 for (ciC = ciCM; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1643 if(!_check_dram(ciC)) { 1644 continue; 1645 } 1646 1647 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR0r(unit,ciC,&rval)); 1648 mr0 = soc_reg_field_get( unit, CI_DDR_MR0r, rval, Af ); 1649 mr0 = (mr0 & 0x00007E07) | ((mr0 & 0x0A8) << 1) | ((mr0 & 0x150) >> 1); 1650 soc_reg_field_set( unit, CI_DDR_MR0r, &mr0, Af, mr0 ); 1651 soc_reg_field_set( unit, CI_DDR_MR0r, &mr0, BAf, 0 ); 1652 1653 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR1r(unit,ciC,&rval)); 1654 mr2 = soc_reg_field_get( unit, CI_DDR_MR1r, rval, Af ); 1655 mr2 = (mr2 & 0x00007E07) | ((mr2 & 0x0A8) << 1) | ((mr2 & 0x150) >> 1); 1656 soc_reg_field_set( unit, CI_DDR_MR2r, &mr2, Af, mr2 ); 1657 soc_reg_field_set( unit, CI_DDR_MR2r, &mr2, BAf, 2 ); 1658 1659 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR2r(unit,ciC,&rval)); 1660 mr1 = soc_reg_field_get( unit, CI_DDR_MR2r, rval, Af ); 1661 mr1 = (mr1 & 0x00007E07) | ((mr1 & 0x0A8) << 1) | ((mr1 & 0x150) >> 1); 1662 soc_reg_field_set( unit, CI_DDR_MR1r, &mr1, Af, mr1 ); 1663 soc_reg_field_set( unit, CI_DDR_MR1r, &mr1, BAf, 1 ); 1664 1665 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR3r(unit,ciC,&rval)); 1666 mr3 = soc_reg_field_get( unit, CI_DDR_MR3r, rval, Af ); 1667 mr3 = (mr3 & 0x00007E07) | ((mr3 & 0x0A8) << 1) | ((mr3 & 0x150) >> 1); 1668 soc_reg_field_set( unit, CI_DDR_MR3r, &mr3, Af, mr3 ); 1669 soc_reg_field_set( unit, CI_DDR_MR3r, &mr3, BAf, 3 ); 1670 1671 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR0r(unit,ciC,mr0)); 1672 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR1r(unit,ciC,mr1)); 1673 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR2r(unit,ciC,mr2)); 1674 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR3r(unit,ciC,mr3)); 1675 } 1676 1677 rval = 0; 1678 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DONEf, 1 ); 1679 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, REQf, 1 ); 1680 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_CMDf, 0x0 ); 1681 1682 /* MR2 */ 1683 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 1684 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x2 ); 1685 for (ciC = ciCS; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1686 if(!_check_dram(ciC)) { 1687 continue; 1688 } 1689 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1690 } 1691 1692 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 1693 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x1 ); 1694 for (ciC = ciCM; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1695 if(!_check_dram(ciC)) { 1696 continue; 1697 } 1698 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1699 } 1700 1701 /* MR3 */ 1702 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 1703 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x3 ); 1704 for (ciC = ciCS; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1705 if(!_check_dram(ciC)) { 1706 continue; 1707 } 1708 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1709 } 1710 1711 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 1712 for (ciC = ciCM; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1713 if(!_check_dram(ciC)) { 1714 continue; 1715 } 1716 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1717 } 1718 1719 /* MR1 */ 1720 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 1721 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x1 ); 1722 for (ciC = ciCS; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1723 if(!_check_dram(ciC)) { 1724 continue; 1725 } 1726 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1727 } 1728 1729 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 1730 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x2 ); 1731 for (ciC = ciCM; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1732 if(!_check_dram(ciC)) { 1733 continue; 1734 } 1735 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1736 } 1737 1738 /* MR0 */ 1739 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 1740 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x0 ); 1741 for (ciC = ciCS; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1742 if(!_check_dram(ciC)) { 1743 continue; 1744 } 1745 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1746 } 1747 1748 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 1749 for (ciC = ciCM; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Every other CI */ 1750 if(!_check_dram(ciC)) { 1751 continue; 1752 } 1753 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1754 } 1755 1756 /* ZQ Cal Long */ 1757 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_CMDf, 0x3 ); 1758 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x3 ); 1759 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x3 ); 1760 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=1) { /* All CIs */ 1761 if(!_check_dram(ciC)) { 1762 continue; 1763 } 1764 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciC, rval) ); 1765 } 1766 1767 } else { 1768 LOG_INFO(BSL_LS_SOC_DDR, 1769 (BSL_META_U(unit, 1770 " Auto Init\n"))); 1771 1772 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 1773 if(!_check_dram(ciC)) { 1774 continue; 1775 } 1776 SOC_IF_ERROR_RETURN(READ_CI_MRS_CMDr(unit,ciC,&rval)); 1777 soc_reg_field_set(unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 3); 1778 SOC_IF_ERROR_RETURN(WRITE_CI_MRS_CMDr(unit,ciC,rval)); 1779 } 1780 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 1781 if(!_check_dram(ciC)) { 1782 continue; 1783 } 1784 SOC_IF_ERROR_RETURN(READ_CI_DDR_AUTOINITr(unit,ciC,&rval)); 1785 soc_reg_field_set(unit, CI_DDR_AUTOINITr, &rval, DONEf, 1); 1786 soc_reg_field_set(unit, CI_DDR_AUTOINITr, &rval, STARTf, 1); 1787 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_AUTOINITr(unit,ciC,rval)); 1788 } 1789 sal_usleep(1000); 1790 1791 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 1792 if(!_check_dram(ciC)) { 1793 continue; 1794 } 1795 soc_timeout_init(&to, to_val, 0); 1796 do { 1797 SOC_IF_ERROR_RETURN(READ_CI_DDR_AUTOINITr(unit,ciC,&rval)); 1798 if (soc_reg_field_get(unit, CI_DDR_AUTOINITr, rval, DONEf)) { 1799 break; 1800 } 1801 if (soc_timeout_check(&to)) { 1802 LOG_ERROR(BSL_LS_SOC_COMMON, 1803 (BSL_META_U(unit, 1804 "CI%d: Timed out DDR Init\n"), ciC)); 1805 return SOC_E_TIMEOUT; 1806 } 1807 } while (TRUE); 1808 } 1809 } 1810 1811 /* (19) Add some delay for TZQinit (512 DDR CLK) */ 1812 sal_usleep(5120); 1813 1814 LOG_INFO(BSL_LS_SOC_DDR, 1815 (BSL_META_U(unit, 1816 "C14. Clear Read/Write FIFO errors\n"))); 1817 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 1818 if(!_check_dram(ciC)) { 1819 continue; 1820 } 1821 rval = 0; 1822 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_CORRECTED_ERRORf, 1); 1823 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_UNCORRECTED_ERRORf, 1); 1824 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_CORRECTED_ERRORf, 1); 1825 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_UNCORRECTED_ERRORf, 1); 1826 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_BL0_RD_FIFO_ERRORf, 1); 1827 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_BL1_RD_FIFO_ERRORf, 1); 1828 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_OVERFLOWf, 1); 1829 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_OVERFLOWf, 1); 1830 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_READY_EVENTf, 1); 1831 SOC_IF_ERROR_RETURN(WRITE_CI_ERRORr(unit,ciC,rval)); 1832 } 1833 1834 if(SOC_IS_KATANA2(unit)) { 1835 LOG_INFO(BSL_LS_SOC_DDR, 1836 (BSL_META_U(unit, 1837 "C15. Config and Release BIST from reset\n"))); 1838 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 1839 if(!_check_dram(ciC)) { 1840 continue; 1841 } 1842 rval = 0; 1843 soc_reg_field_set(unit, BISTGENERALCONFIGURATIONSr, &rval, NUMCOLSf, 2); 1844 SOC_IF_ERROR_RETURN(WRITE_BISTGENERALCONFIGURATIONSr(unit,ciC,rval)); 1845 1846 SOC_IF_ERROR_RETURN(READ_BISTCONFIGr(unit,ciC,&rval)); 1847 soc_reg_field_set(unit, BISTCONFIGr, &rval, BIST_RESETBf, 1); 1848 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGr(unit,ciC,rval)); 1849 } 1850 } 1851 break; 1852 case DDR_PHYTYPE_ENG: 1853 /* _soc_ddr40_arad_phy_init_mem_set_wrapper(unit, &ENGfgmss, freq_loc, grade_loc); */ 1854 LOG_INFO(BSL_LS_SOC_DDR, 1855 (BSL_META_U(unit, 1856 "C01. Check Power Up Reset_Bar\n"))); 1857 #ifdef BCM_PETRA_SUPPORT 1858 if(SOC_IS_ARAD(unit)) { 1859 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1860 if(!_check_dram_either(ciC)) { 1861 continue; 1862 } 1863 soc_timeout_init(&to, to_val, 0); 1864 do { 1865 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ciC>>1, DRC_DPI_STATUSr, &rval)); 1866 if (soc_reg_field_get(unit, DRCA_DPI_STATUSr, rval, PWRUP_RSBf)) { 1867 break; 1868 } 1869 if (soc_timeout_check(&to)) { 1870 LOG_ERROR(BSL_LS_SOC_COMMON, 1871 (BSL_META_U(unit, 1872 "CI%d: Timed out waiting for DDR PHY to Power Up\n"), ciC)); 1873 return SOC_E_TIMEOUT; 1874 } 1875 } while (TRUE); 1876 } 1877 } 1878 #endif /* BCM_PETRA_SUPPORT */ 1879 1880 LOG_INFO(BSL_LS_SOC_DDR, 1881 (BSL_META_U(unit, 1882 "C02. Config and Release PLL from reset\n"))); 1883 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1884 if(!_check_dram_either(ciC)) { 1885 continue; 1886 } 1887 /* Divider */ 1888 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(unit,ciC,&rval)); 1889 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_DIVIDERS,NDIV,16); 1890 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_DIVIDERS,POST_DIV,1); 1891 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(unit,ciC,rval)); 1892 /* Reset */ 1893 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,&rval)); 1894 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,0); 1895 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 1896 1897 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,&rval)); 1898 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,1); 1899 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 1900 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,0); 1901 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 1902 } 1903 1904 LOG_INFO(BSL_LS_SOC_DDR, 1905 (BSL_META_U(unit, 1906 "C03. Poll PLL Lock\n"))); 1907 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1908 if(!_check_dram_either(ciC)) { 1909 continue; 1910 } 1911 soc_timeout_init(&to, to_val, 0); 1912 do { 1913 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_STATUSr(unit,ciC,&rval)); 1914 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, PLL_STATUS, LOCK)) { 1915 break; 1916 } 1917 if (soc_timeout_check(&to)) { 1918 LOG_ERROR(BSL_LS_SOC_COMMON, 1919 (BSL_META_U(unit, 1920 "CI%d: Timed out waiting for DDR PHY PLL to Lock\n"), ciC)); 1921 return SOC_E_TIMEOUT; 1922 } 1923 } while (TRUE); 1924 } 1925 1926 LOG_INFO(BSL_LS_SOC_DDR, 1927 (BSL_META_U(unit, 1928 "C04. Calibrate ZQ (ddr40_phy_calib_zq)\n"))); 1929 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1930 if(!_check_dram_either(ciC)) { 1931 continue; 1932 } 1933 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1934 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,0); 1935 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 1936 1937 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1938 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,1); 1939 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 1940 } 1941 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1942 if(!_check_dram_either(ciC)) { 1943 continue; 1944 } 1945 soc_timeout_init(&to, to_val, 0); 1946 do { 1947 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 1948 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, ZQ_PVT_COMP_CTL, SAMPLE_DONE)) { 1949 break; 1950 } 1951 if (soc_timeout_check(&to)) { 1952 LOG_ERROR(BSL_LS_SOC_COMMON, 1953 (BSL_META_U(unit, 1954 "CI%d: Timed out waiting for ZQ Calibration\n"), ciC)); 1955 return SOC_E_TIMEOUT; 1956 } 1957 } while (TRUE); 1958 } 1959 1960 LOG_INFO(BSL_LS_SOC_DDR, 1961 (BSL_META_U(unit, 1962 "C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT\n"))); 1963 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1964 if(!_check_dram_either(ciC)) { 1965 continue; 1966 } 1967 rval = 0x3f1ffff; /* all bits except RESET and CKE */ 1968 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(unit,ciC,rval)); 1969 1970 rval = 0; /* AGUTMANN disable VTT override , previously 0x1ffff; */ 1971 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(unit,ciC,rval)); 1972 1973 } 1974 1975 LOG_INFO(BSL_LS_SOC_DDR, 1976 (BSL_META_U(unit, 1977 "C06. DDR40_PHY_DDR3_MISC\n"))); 1978 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 1979 if(!_check_dram_either(ciC)) { 1980 continue; 1981 } 1982 rval = 0; 1983 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,VDDO_VOLTS,1); 1984 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,RT120B_G,1); 1985 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,RT60B,1); 1986 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(unit,ciC,rval)); 1987 1988 rval = 0; 1989 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,VDDO_VOLTS,1); 1990 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,RT120B_G,1); 1991 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,NO_DQS_RD,0); 1992 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTLr(unit,ciC,rval)); 1993 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTLr(unit,ciC,rval)); 1994 } 1995 1996 /* SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,0,&data)); 1997 mhz = soc_reg_field_get(unit, CI_PHY_CONTROLr, data, DDR_MHZf); 1998 mhz = SOC_DDR3_CLOCK_MHZ(unit); 1999 */ 2000 2001 if (!SAL_BOOT_QUICKTURN) { 2002 uint32 rd_en_byte_mode=0, rd_en_byte_vdl_steps=0, rd_en_bit_vdl_offset=0; 2003 2004 LOG_INFO(BSL_LS_SOC_DDR, 2005 (BSL_META_U(unit, 2006 "C07. VDL Calibration\n"))); 2007 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2008 if(!_check_dram_either(ciC)) { 2009 continue; 2010 } 2011 rval = 0; 2012 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 2013 2014 rval = 0; 2015 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_FAST,1); 2016 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_ONCE,1); 2017 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_AUTO,1); 2018 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 2019 } 2020 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2021 if(!_check_dram_either(ciC)) { 2022 continue; 2023 } 2024 soc_timeout_init(&to, to_val, 0); 2025 do { 2026 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2027 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 2028 break; 2029 } 2030 if (soc_timeout_check(&to)) { 2031 LOG_ERROR(BSL_LS_SOC_COMMON, 2032 (BSL_META_U(unit, 2033 "CI%d: Timed out waiting for VDL Calibration Idle\n"), ciC)); 2034 return SOC_E_TIMEOUT; 2035 } 2036 } while (TRUE); 2037 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2038 if (soc_property_get(unit, spn_DIAG_EMULATOR_PARTIAL_INIT, 0x0) == 0) { 2039 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 2040 LOG_ERROR(BSL_LS_SOC_COMMON, 2041 (BSL_META_U(unit, 2042 "CI%d: VDL Calibration Did Not Lock reg=%x \n"), ciC, rval)); 2043 return SOC_E_FAIL; 2044 } 2045 } 2046 2047 LOG_INFO(BSL_LS_SOC_DDR, 2048 (BSL_META_U(unit, 2049 "VDL calibration result: 0x%0x (cal_steps = %d)\n"), 2050 rval, DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_TOTAL) >> 4)); 2051 2052 /* clear VDL calib control */ 2053 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,0)); 2054 2055 } 2056 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2057 if(!_check_dram_either(ciC)) { 2058 continue; 2059 } 2060 2061 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(unit,ciC,&rval)); 2062 rd_en_byte_mode = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BYTE_SEL); 2063 rd_en_byte_vdl_steps = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_TOTAL) >> 4; 2064 rd_en_bit_vdl_offset = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BIT_OFFSET); 2065 COMPILER_REFERENCE(rd_en_byte_mode); 2066 COMPILER_REFERENCE(rd_en_byte_vdl_steps); 2067 COMPILER_REFERENCE(rd_en_bit_vdl_offset); 2068 2069 /* rval = 0; 2070 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ci,rval)); 2071 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_STEPS,1); 2072 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ci,rval)); 2073 */ 2074 } 2075 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2076 if(!_check_dram_either(ciC)) { 2077 continue; 2078 } 2079 soc_timeout_init(&to, to_val, 0); 2080 do { 2081 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2082 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 2083 break; 2084 } 2085 if (soc_timeout_check(&to)) { 2086 LOG_ERROR(BSL_LS_SOC_COMMON, 2087 (BSL_META_U(unit, 2088 "CI%d: Timed out waiting for VDL Calibration Idle(1)\n"), ciC)); 2089 return SOC_E_TIMEOUT; 2090 } 2091 } while (TRUE); 2092 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2093 if (soc_property_get(unit, spn_DIAG_EMULATOR_PARTIAL_INIT, 0x0) == 0) { 2094 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 2095 LOG_ERROR(BSL_LS_SOC_COMMON, 2096 (BSL_META_U(unit, 2097 "CI%d: VDL Calibration Did Not Lock(1)\n"), ciC)); 2098 return SOC_E_FAIL; 2099 } 2100 } 2101 } 2102 } else { 2103 LOG_INFO(BSL_LS_SOC_DDR, 2104 (BSL_META_U(unit, 2105 "C07. VDL Calibration SKIPPED\n"))); 2106 }/* Not QUICKTURN */ 2107 2108 LOG_INFO(BSL_LS_SOC_DDR, 2109 (BSL_META_U(unit, 2110 "C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....\n"))); 2111 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2112 if(!_check_dram_either(ciC)) { 2113 continue; 2114 } 2115 rval = 0; 2116 #if 0 /* def BCM_PETRA_SUPPORT */ 2117 DDR40_SET_FIELD(rval, DDR40_PHY_WORD_LANE_0, READ_DATA_DLY, RD_DATA_DLY, arad_dram_read_data_dly_get(unit, SOC_DDR3_CLOCK_MHZ(unit))); 2118 #else 2119 DDR40_SET_FIELD(rval, DDR40_PHY_WORD_LANE_0, READ_DATA_DLY, RD_DATA_DLY, 1); 2120 #endif 2121 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ciC, rval)); 2122 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ciC, rval)); 2123 2124 rval = 0; 2125 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_ENABLE,1); 2126 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_LE_ADJ,1); 2127 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_TE_ADJ,1); 2128 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_READ_CONTROLr(unit,ciC,rval)); 2129 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_READ_CONTROLr(unit,ciC,rval)); 2130 2131 rval = 3; 2132 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODEr(unit,ciC,rval)); 2133 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODEr(unit,ciC,rval)); 2134 } 2135 2136 LOG_INFO(BSL_LS_SOC_DDR, 2137 (BSL_META_U(unit, 2138 "C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....\n"))); 2139 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2140 if(!_check_dram_either(ciC)) { 2141 continue; 2142 } 2143 rval = 0; 2144 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,IDLE_PAD_CONTROL,AUTO_DQ_IDDQ_MODE,1); 2145 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,IDLE_PAD_CONTROL,AUTO_DQ_RXENB_MODE,1); 2146 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROLr(unit,ciC,rval)); 2147 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROLr(unit,ciC,rval)); 2148 } 2149 2150 LOG_INFO(BSL_LS_SOC_DDR, 2151 (BSL_META_U(unit, 2152 "C10. Wait for Phy Ready\n"))); 2153 #ifdef BCM_PETRA_SUPPORT 2154 if(SOC_IS_ARAD(unit)) { 2155 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2156 if(!_check_dram_either(ciC)) { 2157 continue; 2158 } 2159 soc_timeout_init(&to, to_val, 0); 2160 do { 2161 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ciC>>1, DRC_DPI_STATUSr, &rval)); 2162 if (soc_reg_field_get(unit, DRCA_DPI_STATUSr, rval, READYf)) { 2163 break; 2164 } 2165 if (soc_timeout_check(&to)) { 2166 LOG_ERROR(BSL_LS_SOC_COMMON, 2167 (BSL_META_U(unit, 2168 "CI%d: Timed out waiting for PHY Ready\n"), ciC)); 2169 return SOC_E_TIMEOUT; 2170 } 2171 } while (TRUE); 2172 } 2173 } 2174 #endif /* BCM_PETRA_SUPPORT */ 2175 break; 2176 case DDR_PHYTYPE_CE: 2177 break; 2178 case DDR_PHYTYPE_HR2: 2179 LOG_INFO(BSL_LS_SOC_DDR, 2180 (BSL_META_U(unit, 2181 "C01. Check Power Up Reset_Bar\n"))); 2182 /* Skipped for DDR_PHYTYPE_HR2 */ 2183 2184 LOG_INFO(BSL_LS_SOC_DDR, 2185 (BSL_META_U(unit, 2186 "C02. Config and Release PLL from reset\n"))); 2187 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2188 if(!_check_dram_either(ciC)) { 2189 continue; 2190 } 2191 /* Divider */ 2192 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(unit,ciC,&rval)); 2193 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_DIVIDERS,NDIV,16); 2194 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_DIVIDERS,POST_DIV,1); 2195 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(unit,ciC,rval)); 2196 /* Reset */ 2197 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,&rval)); 2198 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,0); 2199 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 2200 2201 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,&rval)); 2202 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,1); 2203 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 2204 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,PLL_CONFIG,RESET,0); 2205 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(unit,ciC,rval)); 2206 } 2207 2208 LOG_INFO(BSL_LS_SOC_DDR, 2209 (BSL_META_U(unit, 2210 "C03. Poll PLL Lock\n"))); 2211 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2212 if(!_check_dram_either(ciC)) { 2213 continue; 2214 } 2215 soc_timeout_init(&to, to_val, 0); 2216 do { 2217 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_PLL_STATUSr(unit,ciC,&rval)); 2218 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, PLL_STATUS, LOCK)) { 2219 break; 2220 } 2221 if (soc_timeout_check(&to)) { 2222 LOG_ERROR(BSL_LS_SOC_COMMON, 2223 (BSL_META_U(unit, 2224 "CI%d: Timed out waiting for DDR PHY PLL to Lock\n"), ciC)); 2225 return SOC_E_TIMEOUT; 2226 } 2227 } while (TRUE); 2228 } 2229 2230 LOG_INFO(BSL_LS_SOC_DDR, 2231 (BSL_META_U(unit, 2232 "C04. Calibrate ZQ (ddr40_phy_calib_zq)\n"))); 2233 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2234 if(!_check_dram_either(ciC)) { 2235 continue; 2236 } 2237 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 2238 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,0); 2239 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 2240 2241 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 2242 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,ZQ_PVT_COMP_CTL,SAMPLE_EN,1); 2243 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,rval)); 2244 } 2245 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2246 if(!_check_dram_either(ciC)) { 2247 continue; 2248 } 2249 soc_timeout_init(&to, to_val, 0); 2250 do { 2251 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit,ciC,&rval)); 2252 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, ZQ_PVT_COMP_CTL, SAMPLE_DONE)) { 2253 break; 2254 } 2255 if (soc_timeout_check(&to)) { 2256 LOG_ERROR(BSL_LS_SOC_COMMON, 2257 (BSL_META_U(unit, 2258 "CI%d: Timed out waiting for ZQ Calibration\n"), ciC)); 2259 return SOC_E_TIMEOUT; 2260 } 2261 } while (TRUE); 2262 } 2263 2264 LOG_INFO(BSL_LS_SOC_DDR, 2265 (BSL_META_U(unit, 2266 "C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT\n"))); 2267 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2268 if(!_check_dram_either(ciC)) { 2269 continue; 2270 } 2271 rval = 0x3f1ffff; /* all bits except RESET and CKE */ 2272 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(unit,ciC,rval)); 2273 2274 rval = 0; /* AGUTMANN disable VTT override , previously 0x1ffff; */ 2275 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(unit,ciC,rval)); 2276 2277 } 2278 2279 LOG_INFO(BSL_LS_SOC_DDR, 2280 (BSL_META_U(unit, 2281 "C06. DDR40_PHY_DDR3_MISC\n"))); 2282 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2283 if(!_check_dram_either(ciC)) { 2284 continue; 2285 } 2286 rval = 0; 2287 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,VDDO_VOLTS,1); 2288 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,RT120B_G,1); 2289 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,DRIVE_PAD_CTL,RT60B,1); 2290 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(unit,ciC,rval)); 2291 2292 rval = 0; 2293 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,VDDO_VOLTS,1); 2294 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,RT120B_G,1); 2295 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,DRIVE_PAD_CTL,NO_DQS_RD,0); 2296 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTLr(unit,ciC,rval)); 2297 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTLr(unit,ciC,rval)); 2298 } 2299 2300 /* SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,0,&data)); 2301 mhz = soc_reg_field_get(unit, CI_PHY_CONTROLr, data, DDR_MHZf); 2302 mhz = SOC_DDR3_CLOCK_MHZ(unit); 2303 */ 2304 2305 if (!SAL_BOOT_QUICKTURN) { 2306 uint32 rd_en_byte_mode=0, rd_en_byte_vdl_steps=0, rd_en_bit_vdl_offset=0; 2307 2308 LOG_INFO(BSL_LS_SOC_DDR, 2309 (BSL_META_U(unit, 2310 "C07. VDL Calibration\n"))); 2311 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2312 if(!_check_dram_either(ciC)) { 2313 continue; 2314 } 2315 rval = 0; 2316 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 2317 2318 rval = 0; 2319 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_FAST,1); 2320 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_ONCE,1); 2321 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_AUTO,1); 2322 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,rval)); 2323 } 2324 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2325 if(!_check_dram_either(ciC)) { 2326 continue; 2327 } 2328 soc_timeout_init(&to, to_val, 0); 2329 do { 2330 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2331 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 2332 break; 2333 } 2334 if (soc_timeout_check(&to)) { 2335 LOG_ERROR(BSL_LS_SOC_COMMON, 2336 (BSL_META_U(unit, 2337 "CI%d: Timed out waiting for VDL Calibration Idle\n"), ciC)); 2338 return SOC_E_TIMEOUT; 2339 } 2340 } while (TRUE); 2341 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2342 if (soc_property_get(unit, spn_DIAG_EMULATOR_PARTIAL_INIT, 0x0) == 0) { 2343 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 2344 LOG_ERROR(BSL_LS_SOC_COMMON, 2345 (BSL_META_U(unit, 2346 "CI%d: VDL Calibration Did Not Lock reg=%x \n"), ciC, rval)); 2347 return SOC_E_FAIL; 2348 } 2349 } 2350 2351 LOG_INFO(BSL_LS_SOC_DDR, 2352 (BSL_META_U(unit, 2353 "VDL calibration result: 0x%0x (cal_steps = %d)\n"), 2354 rval, DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_TOTAL) >> 4)); 2355 2356 /* clear VDL calib control */ 2357 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ciC,0)); 2358 2359 } 2360 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2361 if(!_check_dram_either(ciC)) { 2362 continue; 2363 } 2364 2365 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(unit,ciC,&rval)); 2366 rd_en_byte_mode = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BYTE_SEL); 2367 rd_en_byte_vdl_steps = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_TOTAL) >> 4; 2368 rd_en_bit_vdl_offset = DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BIT_OFFSET); 2369 COMPILER_REFERENCE(rd_en_byte_mode); 2370 COMPILER_REFERENCE(rd_en_byte_vdl_steps); 2371 COMPILER_REFERENCE(rd_en_bit_vdl_offset); 2372 2373 /* rval = 0; 2374 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ci,rval)); 2375 DDR40_SET_FIELD(rval,DDR40_PHY_CONTROL_REGS,VDL_CALIBRATE,CALIB_STEPS,1); 2376 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit,ci,rval)); 2377 */ 2378 } 2379 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2380 if(!_check_dram_either(ciC)) { 2381 continue; 2382 } 2383 soc_timeout_init(&to, to_val, 0); 2384 do { 2385 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2386 if (DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 2387 break; 2388 } 2389 if (soc_timeout_check(&to)) { 2390 LOG_ERROR(BSL_LS_SOC_COMMON, 2391 (BSL_META_U(unit, 2392 "CI%d: Timed out waiting for VDL Calibration Idle(1)\n"), ciC)); 2393 return SOC_E_TIMEOUT; 2394 } 2395 } while (TRUE); 2396 SOC_IF_ERROR_RETURN(READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit,ciC,&rval)); 2397 if (soc_property_get(unit, spn_DIAG_EMULATOR_PARTIAL_INIT, 0x0) == 0) { 2398 if (0 == DDR40_GET_FIELD(rval, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) { 2399 LOG_ERROR(BSL_LS_SOC_COMMON, 2400 (BSL_META_U(unit, 2401 "CI%d: VDL Calibration Did Not Lock(1)\n"), ciC)); 2402 return SOC_E_FAIL; 2403 } 2404 } 2405 } 2406 } else { 2407 LOG_INFO(BSL_LS_SOC_DDR, 2408 (BSL_META_U(unit, 2409 "C07. VDL Calibration SKIPPED\n"))); 2410 }/* Not QUICKTURN */ 2411 2412 LOG_INFO(BSL_LS_SOC_DDR, 2413 (BSL_META_U(unit, 2414 "C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....\n"))); 2415 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2416 if(!_check_dram_either(ciC)) { 2417 continue; 2418 } 2419 rval = 0; 2420 #if 0 /* def BCM_PETRA_SUPPORT */ 2421 DDR40_SET_FIELD(rval, DDR40_PHY_WORD_LANE_0, READ_DATA_DLY, RD_DATA_DLY, arad_dram_read_data_dly_get(unit, SOC_DDR3_CLOCK_MHZ(unit))); 2422 #else 2423 DDR40_SET_FIELD(rval, DDR40_PHY_WORD_LANE_0, READ_DATA_DLY, RD_DATA_DLY, 1); 2424 #endif 2425 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ciC, rval)); 2426 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ciC, rval)); 2427 2428 rval = 0; 2429 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_ENABLE,1); 2430 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_LE_ADJ,1); 2431 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,READ_CONTROL,DQ_ODT_TE_ADJ,1); 2432 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_READ_CONTROLr(unit,ciC,rval)); 2433 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_READ_CONTROLr(unit,ciC,rval)); 2434 2435 rval = 3; 2436 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODEr(unit,ciC,rval)); 2437 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODEr(unit,ciC,rval)); 2438 } 2439 2440 LOG_INFO(BSL_LS_SOC_DDR, 2441 (BSL_META_U(unit, 2442 "C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....\n"))); 2443 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2444 if(!_check_dram_either(ciC)) { 2445 continue; 2446 } 2447 rval = 0; 2448 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,IDLE_PAD_CONTROL,AUTO_DQ_IDDQ_MODE,1); 2449 DDR40_SET_FIELD(rval,DDR40_PHY_WORD_LANE_0,IDLE_PAD_CONTROL,AUTO_DQ_RXENB_MODE,1); 2450 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROLr(unit,ciC,rval)); 2451 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROLr(unit,ciC,rval)); 2452 } 2453 2454 LOG_INFO(BSL_LS_SOC_DDR, 2455 (BSL_META_U(unit, 2456 "C10. Wait for Phy Ready\n"))); 2457 /* Skipped for DDR_PHYTYPE_HR2 */ 2458 break; 2459 default: 2460 LOG_ERROR(BSL_LS_SOC_COMMON, 2461 (BSL_META_U(unit, 2462 "Error. Unsupported PHY type\n"))); 2463 return SOC_E_FAIL; 2464 } 2465 } else { 2466 /* report only */ 2467 switch(phyType) { 2468 case DDR_PHYTYPE_RSVP: 2469 break; 2470 case DDR_PHYTYPE_NS: 2471 break; 2472 case DDR_PHYTYPE_ENG: 2473 break; 2474 case DDR_PHYTYPE_CE: 2475 break; 2476 case DDR_PHYTYPE_HR2: 2477 break; 2478 default: 2479 LOG_ERROR(BSL_LS_SOC_COMMON, 2480 (BSL_META_U(unit, 2481 "Error. Unsupported PHY type\n"))); 2482 return SOC_E_FAIL; 2483 } 2484 } 2485 return SOC_E_NONE; 2486 } 2487 2488 /*********************************************************************** 2489 * Functions to reset the controller 2490 */ 2491 int 2492 soc_ddr40_ctlr_reset (int unit, int ci, uint32 ctlType, int stat) 2493 { 2494 uint32 rval; 2495 2496 if (!stat) { 2497 switch(ctlType) { 2498 case DDR_CTLR_TRSVP: 2499 break; 2500 case DDR_CTLR_T0: 2501 LOG_INFO(BSL_LS_SOC_DDR, 2502 (BSL_META_U(unit, 2503 "(1) Bring CI out of software reset\n"))); 2504 SOC_IF_ERROR_RETURN(READ_CI_RESETr(unit,ci,&rval)); 2505 soc_reg_field_set(unit, CI_RESETr, &rval, TREX2_DEBUG_ENABLEf, 0); 2506 soc_reg_field_set(unit, CI_RESETr, &rval, DDR_RESET_Nf, 0); 2507 soc_reg_field_set(unit, CI_RESETr, &rval, PHY_SW_INITf, 1); 2508 soc_reg_field_set(unit, CI_RESETr, &rval, SW_RESETf, 0); 2509 SOC_IF_ERROR_RETURN(WRITE_CI_RESETr(unit,ci,rval)); 2510 sal_usleep(2000); 2511 2512 LOG_INFO(BSL_LS_SOC_DDR, 2513 (BSL_META_U(unit, 2514 "(6) Clear CI DDR Reset\n"))); 2515 SOC_IF_ERROR_RETURN(READ_CI_RESETr(unit,ci,&rval)); 2516 soc_reg_field_set(unit, CI_RESETr, &rval, TREX2_DEBUG_ENABLEf, 0); 2517 soc_reg_field_set(unit, CI_RESETr, &rval, DDR_RESET_Nf, 1); 2518 soc_reg_field_set(unit, CI_RESETr, &rval, PHY_SW_INITf, 0); 2519 soc_reg_field_set(unit, CI_RESETr, &rval, SW_RESETf, 0); 2520 SOC_IF_ERROR_RETURN(WRITE_CI_RESETr(unit,ci,rval)); 2521 sal_usleep(2000); 2522 2523 LOG_INFO(BSL_LS_SOC_DDR, 2524 (BSL_META_U(unit, 2525 "(6) Set DDR_RST_N\n"))); 2526 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,ci,&rval)); 2527 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, DDR_MHZf, SOC_DDR3_CLOCK_MHZ(unit)); 2528 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, RST_Nf, 3); 2529 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit,ci,rval)); 2530 sal_usleep(2000); 2531 break; 2532 case DDR_CTLR_T1: 2533 break; 2534 case DDR_CTLR_T2: 2535 break; 2536 case DDR_CTLR_T3: 2537 break; 2538 default: 2539 break; 2540 } 2541 } else { 2542 /* report only */ 2543 switch(ctlType) { 2544 case DDR_CTLR_TRSVP: 2545 break; 2546 case DDR_CTLR_T0: 2547 break; 2548 case DDR_CTLR_T1: 2549 break; 2550 case DDR_CTLR_T2: 2551 break; 2552 case DDR_CTLR_T3: 2553 break; 2554 default: 2555 break; 2556 } 2557 } 2558 return SOC_E_NONE; 2559 } 2560 2561 /*********************************************************************** 2562 * Functions to set/report the Controller Parameters 2563 */ 2564 int 2565 soc_ddr40_ctlr_ctl(int unit, int ci, uint32 ctlType, int stat) 2566 { 2567 uint32 rval; 2568 int row_loc, freq_loc, grade_loc; 2569 int ciC; 2570 2571 KATANAfreq_grade_mem_set_set_t T0fgmss; 2572 /* ARADfreq_grade_mem_set_set_t T1fgmss; */ 2573 2574 row_loc = _soc_ddr40_mem_rowstoloc(SOC_DDR3_NUM_ROWS(unit)); 2575 freq_loc = _soc_ddr40_phy_freqtoloc(SOC_DDR3_CLOCK_MHZ(unit)); 2576 grade_loc = _soc_ddr40_mem_gradetoloc(SOC_DDR3_MEM_GRADE(unit)); 2577 2578 if (freq_loc < 0) { 2579 return SOC_E_INTERNAL; /* Unsupported Frequency */ 2580 } 2581 2582 if (!stat) { 2583 switch(ctlType) { 2584 case DDR_CTLR_TRSVP: 2585 break; 2586 case DDR_CTLR_T0: 2587 _soc_ddr40_katana_phy_init_mem_set_wrapper(unit, &T0fgmss, freq_loc, grade_loc); 2588 if (T0fgmss.mhz == -1) { 2589 return SOC_E_INTERNAL; /* Unsupported Frequency / Grade Combination */ 2590 } 2591 2592 LOG_INFO(BSL_LS_SOC_DDR, 2593 (BSL_META_U(unit, 2594 "B01. Bring CI out of software reset\n"))); 2595 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 2596 if(!_check_dram(ciC)) { 2597 continue; 2598 } 2599 SOC_IF_ERROR_RETURN(READ_CI_RESETr(unit,ciC,&rval)); 2600 soc_reg_field_set(unit, CI_RESETr, &rval, TREX2_DEBUG_ENABLEf, 0); 2601 soc_reg_field_set(unit, CI_RESETr, &rval, DDR_RESET_Nf, 0); 2602 soc_reg_field_set(unit, CI_RESETr, &rval, PHY_SW_INITf, 1); 2603 soc_reg_field_set(unit, CI_RESETr, &rval, SW_RESETf, 0); 2604 SOC_IF_ERROR_RETURN(WRITE_CI_RESETr(unit,ciC,rval)); 2605 sal_usleep(2000); 2606 } 2607 2608 LOG_INFO(BSL_LS_SOC_DDR, 2609 (BSL_META_U(unit, 2610 "B02. Set Strap and parameter per speed and grade\n"))); 2611 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 2612 if(!_check_dram(ciC)) { 2613 continue; 2614 } 2615 SOC_IF_ERROR_RETURN(READ_CI_CONFIG0r(unit,ciC,&rval)); 2616 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TWLf, (ciC & 0x1)?(T0fgmss.twl-1):T0fgmss.twl); 2617 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TWRf, T0fgmss.twr); 2618 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TRCf, T0fgmss.trc); 2619 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG0r(unit,ciC,rval)); 2620 2621 SOC_IF_ERROR_RETURN(READ_CI_CONFIG1r(unit,ciC,&rval)); 2622 soc_reg_field_set(unit, CI_CONFIG1r, &rval, RFIFO_ALMOST_FULL_THRESHOLDf, T0fgmss.rfifo_afull); 2623 soc_reg_field_set(unit, CI_CONFIG1r, &rval, RFIFO_FULL_THRESHOLDf, T0fgmss.rfifo_full); 2624 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG1r(unit,ciC,rval)); 2625 2626 SOC_IF_ERROR_RETURN(READ_CI_CONFIG2r(unit,ciC,&rval)); 2627 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TRTWf, T0fgmss.trtw); 2628 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TWTRf, T0fgmss.twtr); 2629 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TFAWf, T0fgmss.tfaw); 2630 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TREAD_ENBf, (ciC & 0x1)?(T0fgmss.tread_enb-1):T0fgmss.tread_enb); 2631 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG2r(unit,ciC,rval)); 2632 2633 SOC_IF_ERROR_RETURN(READ_CI_CONFIG3r(unit,ciC,&rval)); 2634 soc_reg_field_set(unit, CI_CONFIG3r, &rval, BANK_UNAVAILABLE_WRf, T0fgmss.bank_unavail_wr); 2635 soc_reg_field_set(unit, CI_CONFIG3r, &rval, BANK_UNAVAILABLE_RDf, T0fgmss.bank_unavail_rd); 2636 soc_reg_field_set(unit, CI_CONFIG3r, &rval, RR_READf, T0fgmss.rr_read); 2637 soc_reg_field_set(unit, CI_CONFIG3r, &rval, RR_WRITEf, T0fgmss.rr_write); 2638 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG3r(unit,ciC,rval)); 2639 2640 SOC_IF_ERROR_RETURN(READ_CI_CONFIG6r(unit,ciC,&rval)); 2641 soc_reg_field_set(unit, CI_CONFIG6r, &rval, TRFCf, T0fgmss.trfc[row_loc]); 2642 soc_reg_field_set(unit, CI_CONFIG6r, &rval, TRP_READf, T0fgmss.trp_read); 2643 soc_reg_field_set(unit, CI_CONFIG6r, &rval, TRP_WRITEf, T0fgmss.trp_write); 2644 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG6r(unit,ciC,rval)); 2645 2646 SOC_IF_ERROR_RETURN(READ_CI_CONFIG7r(unit,ciC,&rval)); 2647 soc_reg_field_set(unit, CI_CONFIG7r, &rval, TZQf, T0fgmss.tzq); 2648 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG7r(unit,ciC,rval)); 2649 2650 SOC_IF_ERROR_RETURN(READ_CI_PHY_STRAPS0r(unit,ciC,&rval)); 2651 soc_reg_field_set(unit, CI_PHY_STRAPS0r, &rval, CLf, T0fgmss.cl); 2652 soc_reg_field_set(unit, CI_PHY_STRAPS0r, &rval, CWLf, T0fgmss.cwl); 2653 soc_reg_field_set(unit, CI_PHY_STRAPS0r, &rval, WRf, T0fgmss.wr); 2654 soc_reg_field_set(unit, CI_PHY_STRAPS0r, &rval, CHIP_SIZEf, smts[row_loc].chip_siz); 2655 soc_reg_field_set(unit, CI_PHY_STRAPS0r, &rval, AD_WIDTHf, smts[row_loc].ad_width); 2656 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_STRAPS0r(unit,ciC,rval)); 2657 2658 SOC_IF_ERROR_RETURN(READ_CI_PHY_STRAPS1r(unit,ciC,&rval)); 2659 soc_reg_field_set(unit, CI_PHY_STRAPS1r, &rval, JEDECf, T0fgmss.jedec); 2660 soc_reg_field_set(unit, CI_PHY_STRAPS1r, &rval, MHZf, T0fgmss.mhz); 2661 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_STRAPS1r(unit,ciC,rval)); 2662 } 2663 2664 LOG_INFO(BSL_LS_SOC_DDR, 2665 (BSL_META_U(unit, 2666 "B03. Clear CI Phy reset\n"))); 2667 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 2668 if(!_check_dram(ciC)) { 2669 continue; 2670 } 2671 rval = 0; 2672 SOC_IF_ERROR_RETURN(WRITE_CI_RESETr(unit,ciC,rval)); 2673 } 2674 sal_usleep(2000); 2675 2676 LOG_INFO(BSL_LS_SOC_DDR, 2677 (BSL_META_U(unit, 2678 "B04. Set config MR0, MR1, and MR2 registers\n"))); 2679 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 2680 if(!_check_dram(ciC)) { 2681 continue; 2682 } 2683 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR0r(unit,ciC,&rval)); 2684 soc_reg_field_set(unit, CI_DDR_MR0r, &rval, Af, T0fgmss.mr0); 2685 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR0r(unit,ciC,rval)); 2686 2687 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR1r(unit,ciC,&rval)); 2688 soc_reg_field_set(unit, CI_DDR_MR1r, &rval, Af, 0x10); 2689 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR1r(unit,ciC,rval)); 2690 2691 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR2r(unit,ciC,&rval)); 2692 soc_reg_field_set(unit, CI_DDR_MR2r, &rval, Af, T0fgmss.mr2); 2693 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR2r(unit,ciC,rval)); 2694 } 2695 2696 LOG_INFO(BSL_LS_SOC_DDR, 2697 (BSL_META_U(unit, 2698 "B05. Clear CI DDR Reset\n"))); 2699 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 2700 if(!_check_dram(ciC)) { 2701 continue; 2702 } 2703 SOC_IF_ERROR_RETURN(READ_CI_RESETr(unit,ciC,&rval)); 2704 soc_reg_field_set(unit, CI_RESETr, &rval, TREX2_DEBUG_ENABLEf, 0); 2705 soc_reg_field_set(unit, CI_RESETr, &rval, DDR_RESET_Nf, 1); 2706 soc_reg_field_set(unit, CI_RESETr, &rval, PHY_SW_INITf, 0); 2707 soc_reg_field_set(unit, CI_RESETr, &rval, SW_RESETf, 0); 2708 SOC_IF_ERROR_RETURN(WRITE_CI_RESETr(unit,ciC,rval)); 2709 } 2710 sal_usleep(2000); 2711 2712 LOG_INFO(BSL_LS_SOC_DDR, 2713 (BSL_META_U(unit, 2714 "B06. Set DDR_RST_N\n"))); 2715 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 2716 if(!_check_dram(ciC)) { 2717 continue; 2718 } 2719 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,ciC,&rval)); 2720 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, DDR_MHZf, T0fgmss.mhz); 2721 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, RST_Nf, 3); 2722 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit,ciC,rval)); 2723 } 2724 sal_usleep(2000); 2725 2726 LOG_INFO(BSL_LS_SOC_DDR, 2727 (BSL_META_U(unit, 2728 "B06.1 Write 0x1 to PHY_STRAPS_CONTROL\n"))); 2729 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC+=2) { /* Only Even CIs */ 2730 if(!_check_dram_either(ciC)) { 2731 continue; 2732 } 2733 rval = 0x1; 2734 SOC_IF_ERROR_RETURN(WRITE_DDR40_PHY_CONTROL_REGS_STRAP_CONTROLr(unit,ciC,rval)); 2735 } 2736 sal_usleep(2000); 2737 2738 LOG_INFO(BSL_LS_SOC_DDR, 2739 (BSL_META_U(unit, 2740 "B07. Make sure PHY AUTOINIT at strap is NOT set\n"))); 2741 for (ciC = 0; ciC < MAX_SHMOO_INTERFACES; ciC++) { 2742 if(!_check_dram(ciC)) { 2743 continue; 2744 } 2745 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit,ciC,&rval)); 2746 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, AUTO_INITf, 0); 2747 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, CKEf, 0); 2748 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit,ciC,rval)); 2749 } 2750 sal_usleep(2000); 2751 break; 2752 case DDR_CTLR_T1: 2753 break; 2754 case DDR_CTLR_T2: 2755 break; 2756 case DDR_CTLR_T3: 2757 break; 2758 default: 2759 break; 2760 } 2761 } else { 2762 /* report only */ 2763 switch(ctlType) { 2764 case DDR_CTLR_TRSVP: 2765 break; 2766 case DDR_CTLR_T0: 2767 break; 2768 case DDR_CTLR_T1: 2769 break; 2770 case DDR_CTLR_T2: 2771 break; 2772 case DDR_CTLR_T3: 2773 break; 2774 default: 2775 break; 2776 } 2777 } 2778 return SOC_E_NONE; 2779 } 2780 2781 /*********************************************************************** 2782 * Functions to set/report the Controller Parameters 2783 */ 2784 int 2785 soc_ddr40_ctlr_zqcal_ctl(int unit, int ci, uint32 ctlType, int stat) 2786 { 2787 if (!stat) { 2788 switch(ctlType) { 2789 case DDR_CTLR_TRSVP: 2790 break; 2791 case DDR_CTLR_T0: 2792 break; 2793 case DDR_CTLR_T1: 2794 break; 2795 case DDR_CTLR_T2: 2796 break; 2797 case DDR_CTLR_T3: 2798 break; 2799 default: 2800 break; 2801 } 2802 } else { 2803 /* report only */ 2804 switch(ctlType) { 2805 case DDR_CTLR_TRSVP: 2806 break; 2807 case DDR_CTLR_T0: 2808 break; 2809 case DDR_CTLR_T1: 2810 break; 2811 case DDR_CTLR_T2: 2812 break; 2813 case DDR_CTLR_T3: 2814 break; 2815 default: 2816 break; 2817 } 2818 } 2819 return SOC_E_NONE; 2820 } 2821 2822 /*********************************************************************** 2823 * Functions to Read / Write / Modify DDR Memory 2824 */ 2825 int _DDRWrRdComplete(int unit, int ci, uint32 uTimeout) 2826 { 2827 uint32 i; 2828 uint32 data = 0; 2829 uint32 uAck = 0; 2830 2831 /* wait for the ACK to indicate rd/wr op is finished */ 2832 for (i = 0; i < uTimeout; i++) { 2833 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_CTRLr(unit, ci, &data)); 2834 uAck = soc_reg_field_get(unit, CI_MEM_ACC_CTRLr, data, MEM_ACC_ACKf); 2835 if (uAck) { 2836 return SOC_E_NONE; 2837 } 2838 sal_udelay(10); 2839 } 2840 2841 /* timed out */ 2842 return (SOC_E_TIMEOUT); 2843 } 2844 2845 int soc_ddr40_read(int unit, int ci, uint32 addr, uint32 * pData0, 2846 uint32 * pData1, uint32 * pData2, uint32 * pData3, 2847 uint32 * pData4, uint32 * pData5, uint32 * pData6, 2848 uint32 * pData7) 2849 { 2850 2851 uint32 uCmd; 2852 2853 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA0r(unit, ci, 0)); 2854 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA1r(unit, ci, 0)); 2855 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA2r(unit, ci, 0)); 2856 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA3r(unit, ci, 0)); 2857 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA4r(unit, ci, 0)); 2858 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA5r(unit, ci, 0)); 2859 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA6r(unit, ci, 0)); 2860 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA7r(unit, ci, 0)); 2861 2862 uCmd = 0; 2863 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_ACKf, 1); 2864 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_REQf, 1); 2865 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_RD_WR_Nf, 1); 2866 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_ADDRf, addr); 2867 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_CTRLr(unit, ci, uCmd)); 2868 2869 if (SOC_E_NONE != _DDRWrRdComplete(unit, ci, DDR_TIMEOUT_10mS)) { 2870 LOG_ERROR(BSL_LS_SOC_COMMON, 2871 (BSL_META_U(unit, 2872 "Error timeout reading from CI:%d addr:0x%x\n"), 2873 ci, addr)); 2874 return SOC_E_TIMEOUT; 2875 } 2876 2877 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA0r(unit, ci, pData0)); 2878 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA1r(unit, ci, pData1)); 2879 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA2r(unit, ci, pData2)); 2880 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA3r(unit, ci, pData3)); 2881 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA4r(unit, ci, pData4)); 2882 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA5r(unit, ci, pData5)); 2883 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA6r(unit, ci, pData6)); 2884 SOC_IF_ERROR_RETURN(READ_CI_MEM_ACC_DATA7r(unit, ci, pData7)); 2885 return SOC_E_NONE; 2886 } 2887 2888 int soc_ddr40_write(int unit, int ci, uint32 addr, uint32 uData0, 2889 uint32 uData1, uint32 uData2, uint32 uData3, 2890 uint32 uData4, uint32 uData5, uint32 uData6, uint32 uData7) 2891 { 2892 2893 uint32 uCmd; 2894 2895 /* setup the data */ 2896 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA0r(unit, ci, uData0)); 2897 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA1r(unit, ci, uData1)); 2898 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA2r(unit, ci, uData2)); 2899 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA3r(unit, ci, uData3)); 2900 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA4r(unit, ci, uData4)); 2901 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA5r(unit, ci, uData5)); 2902 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA6r(unit, ci, uData6)); 2903 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_DATA7r(unit, ci, uData7)); 2904 2905 uCmd = 0; 2906 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_ACKf, 1); 2907 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_REQf, 1); 2908 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_RD_WR_Nf, 0); 2909 soc_reg_field_set(unit, CI_MEM_ACC_CTRLr, &uCmd, MEM_ACC_ADDRf, addr); 2910 SOC_IF_ERROR_RETURN(WRITE_CI_MEM_ACC_CTRLr(unit, ci, uCmd)); 2911 2912 if (SOC_E_NONE != _DDRWrRdComplete(unit, ci, DDR_TIMEOUT_10mS)) { 2913 LOG_ERROR(BSL_LS_SOC_COMMON, 2914 (BSL_META_U(unit, 2915 "Error timeout writing to CI:%d addr:0x%x\n"), ci, 2916 addr)); 2917 return SOC_E_TIMEOUT; 2918 } 2919 return SOC_E_NONE; 2920 } 2921 2922 /*********************************************************************** 2923 * Functions to Read / Write / Modify DDR Phy Registers 2924 */ 2925 #ifdef BCM_PETRA_SUPPORT 2926 int 2927 soc_ddr40_arad_phy_reg_ci_read(int unit, int ci, uint32 reg_addr, uint32 * reg_data) 2928 { 2929 arad_dram_rbus_read(unit, (ci>>1), reg_addr, reg_data); 2930 return SOC_E_NONE; 2931 } 2932 2933 int 2934 soc_ddr40_arad_phy_reg_ci_write(int unit, int ci, uint32 reg_addr, uint32 reg_data) 2935 { 2936 arad_dram_rbus_write(unit, (ci>>1), reg_addr, reg_data); 2937 return SOC_E_NONE; 2938 } 2939 2940 int 2941 soc_ddr40_arad_phy_reg_ci_modify(int unit, uint32 ci, uint32 reg_addr, uint32 data, uint32 mask) 2942 { 2943 arad_dram_rbus_modify(unit, (ci>>1), reg_addr, data, mask); 2944 return SOC_E_NONE; 2945 } 2946 #endif 2947 2948 int 2949 soc_ddr40_katana_phy_reg_ci_read(int unit, int ci, uint32 reg_addr, uint32 * reg_data) 2950 { 2951 uint32 rval; 2952 soc_timeout_t to; 2953 2954 rval = 0; 2955 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ACKf, 1); /* write 1 to clear */ 2956 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ERR_ACKf, 1); /* write 1 to clear */ 2957 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ADDRf, 2958 reg_addr); 2959 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_RD_WR_Nf, 1); 2960 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_REQf, 1); 2961 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_PHY_REG_CTRLr(unit, ci, rval)); 2962 2963 if (SAL_BOOT_SIMULATION) { 2964 soc_timeout_init(&to, 10000000, 0); /* 10 Sec */ 2965 } else { 2966 soc_timeout_init(&to, 50000, 0); /* 50 mS */ 2967 } 2968 do { 2969 SOC_IF_ERROR_RETURN(READ_CI_DDR_PHY_REG_CTRLr(unit, ci, &rval)); 2970 if (soc_reg_field_get(unit, CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ACKf)) { 2971 break; 2972 } 2973 if (soc_reg_field_get 2974 (unit, CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ERR_ACKf)) { 2975 return SOC_E_FAIL; 2976 } 2977 if (soc_timeout_check(&to)) { 2978 return SOC_E_TIMEOUT; 2979 } 2980 } while (TRUE); 2981 SOC_IF_ERROR_RETURN(READ_CI_DDR_PHY_REG_DATAr(unit, ci, reg_data)); 2982 return SOC_E_NONE; 2983 } 2984 2985 /* DDR regs Indirect Write */ 2986 int 2987 soc_ddr40_katana_phy_reg_ci_write(int unit, int ci, uint32 reg_addr, uint32 reg_data) 2988 { 2989 uint32 rval; 2990 soc_timeout_t to; 2991 2992 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_PHY_REG_DATAr(unit, ci, reg_data)); 2993 2994 rval = 0; 2995 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ACKf, 1); /* write 1 to clear */ 2996 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ERR_ACKf, 1); /* write 1 to clear */ 2997 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ADDRf, 2998 reg_addr); 2999 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_RD_WR_Nf, 0); 3000 soc_reg_field_set(unit, CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_REQf, 1); 3001 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_PHY_REG_CTRLr(unit, ci, rval)); 3002 3003 if (SAL_BOOT_SIMULATION) { 3004 soc_timeout_init(&to, 10000000, 0); /* 10 Sec */ 3005 } else { 3006 soc_timeout_init(&to, 50000, 0); /* 50 mS */ 3007 } 3008 do { 3009 SOC_IF_ERROR_RETURN(READ_CI_DDR_PHY_REG_CTRLr(unit, ci, &rval)); 3010 if (soc_reg_field_get(unit, CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ACKf)) { 3011 break; 3012 } 3013 if (soc_reg_field_get 3014 (unit, CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ERR_ACKf)) { 3015 return SOC_E_FAIL; 3016 } 3017 if (soc_timeout_check(&to)) { 3018 return SOC_E_TIMEOUT; 3019 } 3020 } while (TRUE); 3021 return SOC_E_NONE; 3022 } 3023 3024 int 3025 soc_ddr40_katana_phy_reg_ci_modify(int unit, uint32 ci, uint32 reg_addr, uint32 data, 3026 uint32 mask) 3027 { 3028 int rv = SOC_E_NONE; 3029 uint32 tmp, otmp; 3030 3031 data = data & mask; 3032 3033 SOC_IF_ERROR_RETURN(soc_ddr40_katana_phy_reg_ci_read(unit, ci, reg_addr, &tmp)); 3034 otmp = tmp; 3035 tmp &= ~(mask); 3036 tmp |= data; 3037 3038 if (otmp != tmp) { 3039 SOC_IF_ERROR_RETURN 3040 (soc_ddr40_katana_phy_reg_ci_write(unit, ci, reg_addr, tmp)); 3041 } 3042 3043 return rv; 3044 } 3045 3046 #ifdef BCM_HURRICANE2_SUPPORT 3047 int 3048 soc_ddr40_hurricane2_phy_reg_ci_read( 3049 int unit, int ci, uint32 reg_addr, uint32 *reg_data) 3050 { 3051 uint32 base; 3052 uint32 rval; 3053 3054 if (reg_data == NULL) { 3055 return SOC_E_PARAM; 3056 } 3057 3058 /* Get DDR PHY register base address */ 3059 base = soc_reg_addr(unit, DDR_PHY_CONTROL_REGS_REVISIONr, REG_PORT_ANY, 0); 3060 3061 rval = soc_iproc_getreg(unit, base + reg_addr, reg_data); 3062 return rval; 3063 } 3064 3065 int 3066 soc_ddr40_hurricane2_phy_reg_ci_write( 3067 int unit, int ci, uint32 reg_addr, uint32 reg_data) 3068 { 3069 int rv; 3070 uint32 base; 3071 uint32 dummy; 3072 3073 /* Get DDR PHY register base address */ 3074 base = soc_reg_addr(unit, DDR_PHY_CONTROL_REGS_REVISIONr, REG_PORT_ANY, 0); 3075 3076 rv = soc_iproc_setreg(unit, base + reg_addr, reg_data); 3077 3078 /* Need to read a PHY register after PHY write */ 3079 if (rv == SOC_E_NONE) { 3080 (void)soc_iproc_getreg(unit, base, &dummy); 3081 } 3082 3083 return rv; 3084 } 3085 3086 int 3087 soc_ddr40_hurricane2_phy_reg_ci_modify( 3088 int unit, uint32 ci, uint32 reg_addr, uint32 data, uint32 mask) 3089 { 3090 int rv = SOC_E_NONE; 3091 uint32 tmp, otmp; 3092 3093 data = data & mask; 3094 3095 SOC_IF_ERROR_RETURN( 3096 soc_ddr40_hurricane2_phy_reg_ci_read(unit, ci, reg_addr, &tmp)); 3097 otmp = tmp; 3098 tmp &= ~(mask); 3099 tmp |= data; 3100 3101 if (otmp != tmp) { 3102 SOC_IF_ERROR_RETURN( 3103 soc_ddr40_hurricane2_phy_reg_ci_write(unit, ci, reg_addr, tmp)); 3104 } 3105 3106 return rv; 3107 } 3108 #endif /* BCM_HURRICANE2_SUPPORT */ 3109 3110 int 3111 soc_ddr40_phy_reg_ci_read(int unit, int ci, uint32 reg_addr, uint32 * reg_data) 3112 { 3113 if(SOC_IS_KATANAX(unit)) { 3114 return soc_ddr40_katana_phy_reg_ci_read(unit, ci, reg_addr, reg_data); 3115 #ifdef BCM_PETRA_SUPPORT 3116 } else if(SOC_IS_ARAD(unit)) { 3117 return soc_ddr40_arad_phy_reg_ci_read(unit, ci, reg_addr, reg_data); 3118 #endif 3119 #ifdef BCM_HURRICANE2_SUPPORT 3120 } else if(SOC_IS_HURRICANE2(unit)) { 3121 return soc_ddr40_hurricane2_phy_reg_ci_read( 3122 unit, ci, reg_addr, reg_data); 3123 #endif 3124 } else { 3125 return SOC_E_INTERNAL; /* Unsupported configuration */ 3126 } 3127 } 3128 3129 int 3130 soc_ddr40_phy_reg_ci_write(int unit, int ci, uint32 reg_addr, uint32 reg_data) 3131 { 3132 if(SOC_IS_KATANAX(unit)) { 3133 return soc_ddr40_katana_phy_reg_ci_write(unit, ci, reg_addr, reg_data); 3134 #ifdef BCM_PETRA_SUPPORT 3135 } else if(SOC_IS_ARAD(unit)) { 3136 return soc_ddr40_arad_phy_reg_ci_write(unit, ci, reg_addr, reg_data); 3137 #endif 3138 #ifdef BCM_HURRICANE2_SUPPORT 3139 } else if(SOC_IS_HURRICANE2(unit)) { 3140 return soc_ddr40_hurricane2_phy_reg_ci_write( 3141 unit, ci, reg_addr, reg_data); 3142 #endif 3143 } else { 3144 return SOC_E_INTERNAL; /* Unsupported configuration */ 3145 } 3146 } 3147 3148 int 3149 soc_ddr40_phy_reg_ci_modify(int unit, uint32 ci, uint32 reg_addr, uint32 data, 3150 uint32 mask) 3151 { 3152 if(SOC_IS_KATANAX(unit)) { 3153 return soc_ddr40_katana_phy_reg_ci_modify(unit, ci, reg_addr, data, mask); 3154 #ifdef BCM_PETRA_SUPPORT 3155 } else if(SOC_IS_ARAD(unit)) { 3156 return soc_ddr40_arad_phy_reg_ci_modify(unit, ci, reg_addr, data, mask); 3157 #endif 3158 #ifdef BCM_HURRICANE2_SUPPORT 3159 } else if(SOC_IS_HURRICANE2(unit)) { 3160 return soc_ddr40_hurricane2_phy_reg_ci_modify( 3161 unit, ci, reg_addr, data, mask); 3162 #endif 3163 } else { 3164 return SOC_E_INTERNAL; /* Unsupported configuration */ 3165 } 3166 } 3167 3168 3169 /*********************************************************************** 3170 * Shmoo Functions 3171 */ 3172 3173 uint32 _get_random(void) 3174 { 3175 static uint32 m_w = 6483; /* must not be zero */ 3176 static uint32 m_z = 31245; /* must not be zero */ 3177 3178 m_z = 36969 * (m_z & 65535) + (m_z >> 16); 3179 m_w = 18000 * (m_w & 65535) + (m_w >> 16); 3180 return (m_z << 16) + m_w; /* 32-bit result */ 3181 } 3182 3183 /* Generate NUM_DATA uint32 data for memory accesses */ 3184 STATIC void _fill_in_data(uint32 * data) 3185 { 3186 int32 i; 3187 3188 for (i = 0; i < NUM_DATA; i++) { 3189 if (i & 0x1) { 3190 data[i] = 0xa5a5a500 | i; 3191 } else { 3192 data[i] = 0x5a5a5a00 | i; 3193 } 3194 } 3195 return; 3196 } 3197 3198 STATIC void _test_mem_write(int unit, int ci, int addr, uint32 * uDataWR) 3199 { 3200 if(SOC_IS_KATANAX(unit)) { 3201 int32 i; 3202 for (i = 0; i < NUM_DATA / 8; i++) { 3203 soc_ddr40_write(unit, ci, addr + i, uDataWR[i * 8], 3204 uDataWR[(i * 8) + 1], uDataWR[(i * 8) + 2], 3205 uDataWR[(i * 8) + 3], uDataWR[(i * 8) + 4], 3206 uDataWR[(i * 8) + 5], uDataWR[(i * 8) + 6], 3207 uDataWR[(i * 8) + 7]); 3208 } 3209 } 3210 } 3211 3212 STATIC uint32 _test_rd_data_fifo_status(int unit, int ci, int wl, int loop) 3213 { 3214 int i; 3215 uint32 addr; 3216 uint32 uDataRD[NUM_DATA]; 3217 uint32 rval = 0; 3218 uint32 result_fail = 1; 3219 3220 if(!SOC_IS_KATANAX(unit)) { 3221 return result_fail; 3222 } 3223 3224 addr = (_get_random() & 0xFFFFFF); 3225 for (i = 0; i < NUM_DATA / 8; i++) { 3226 soc_ddr40_read(unit, (ci + wl), addr + i, &uDataRD[(i * 8)], 3227 &uDataRD[(i * 8) + 1], &uDataRD[(i * 8) + 2], 3228 &uDataRD[(i * 8) + 3], &uDataRD[(i * 8) + 4], 3229 &uDataRD[(i * 8) + 5], &uDataRD[(i * 8) + 6], 3230 &uDataRD[(i * 8) + 7]); 3231 } 3232 rval = 0; 3233 if (wl == 0) { 3234 READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, &rval); 3235 } else { 3236 READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, &rval); 3237 } 3238 3239 result_fail = (rval>0) ? 0xffff : 0; 3240 3241 return result_fail; 3242 } 3243 3244 uint32 3245 _test_func_self_test_1_katana(int unit, int ci, int wl, int loop, uint32 flag) 3246 { 3247 uint32 i; 3248 int j, cinum; 3249 uint32 rval = 0; 3250 uint32 result_fail = 0; 3251 uint32 wdata[16]; 3252 uint32 rdata[16]; 3253 uint32 *rdPtr; 3254 int k, m; 3255 uint32 data = 0, fifo_status0, fifo_status1; 3256 3257 uint32 startAddr; 3258 3259 uint32 efold = 0; 3260 3261 rdPtr = &rdata[0]; 3262 3263 /* Alternate data test */ 3264 cinum = ci + wl; 3265 j = 0; 3266 while (j < loop) { 3267 rval = 0; 3268 SOC_IF_ERROR_RETURN(READ_CI_DDR_TESTr(unit, cinum, &rval)); 3269 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, MODEf, 0); 3270 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_TESTf, 0); 3271 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_DONEf, 1); /* write 1 to clear */ 3272 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_TEST_FAILf, 1); /* write 1 to clear */ 3273 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_TESTr(unit, cinum, rval)); 3274 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_BURSTr 3275 (unit, cinum, 0x1ff0)); 3276 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_STEPr(unit, cinum, 1)); 3277 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_ITERr 3278 (unit, cinum, 2)); 3279 startAddr = _get_random() & 0xffffff; 3280 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_STARTr 3281 (unit, cinum, startAddr)); 3282 3283 for(k = 0; k < 8; k++) { 3284 wdata[k] = _get_random(); 3285 } 3286 3287 for(k = 8; k < 16; k++) { 3288 wdata[k] = wdata[k-8]; 3289 } 3290 3291 SOC_IF_ERROR_RETURN 3292 (WRITE_CI_DDR_TEST_DATA0r(unit, cinum, wdata[0])); 3293 SOC_IF_ERROR_RETURN 3294 (WRITE_CI_DDR_TEST_DATA1r(unit, cinum, wdata[1])); 3295 SOC_IF_ERROR_RETURN 3296 (WRITE_CI_DDR_TEST_DATA2r(unit, cinum, wdata[2])); 3297 SOC_IF_ERROR_RETURN 3298 (WRITE_CI_DDR_TEST_DATA3r(unit, cinum, wdata[3])); 3299 SOC_IF_ERROR_RETURN 3300 (WRITE_CI_DDR_TEST_DATA4r(unit, cinum, wdata[4])); 3301 SOC_IF_ERROR_RETURN 3302 (WRITE_CI_DDR_TEST_DATA5r(unit, cinum, wdata[5])); 3303 SOC_IF_ERROR_RETURN 3304 (WRITE_CI_DDR_TEST_DATA6r(unit, cinum, wdata[6])); 3305 SOC_IF_ERROR_RETURN 3306 (WRITE_CI_DDR_TEST_DATA7r(unit, cinum, wdata[7])); 3307 3308 SOC_IF_ERROR_RETURN 3309 (WRITE_CI_DDR_TEST_ALT_DATA0r(unit, cinum, wdata[8])); 3310 SOC_IF_ERROR_RETURN 3311 (WRITE_CI_DDR_TEST_ALT_DATA1r(unit, cinum, wdata[9])); 3312 SOC_IF_ERROR_RETURN 3313 (WRITE_CI_DDR_TEST_ALT_DATA2r(unit, cinum, wdata[10])); 3314 SOC_IF_ERROR_RETURN 3315 (WRITE_CI_DDR_TEST_ALT_DATA3r(unit, cinum, wdata[11])); 3316 SOC_IF_ERROR_RETURN 3317 (WRITE_CI_DDR_TEST_ALT_DATA4r(unit, cinum, wdata[12])); 3318 SOC_IF_ERROR_RETURN 3319 (WRITE_CI_DDR_TEST_ALT_DATA5r(unit, cinum, wdata[13])); 3320 SOC_IF_ERROR_RETURN 3321 (WRITE_CI_DDR_TEST_ALT_DATA6r(unit, cinum, wdata[14])); 3322 SOC_IF_ERROR_RETURN 3323 (WRITE_CI_DDR_TEST_ALT_DATA7r(unit, cinum, wdata[15])); 3324 3325 rval = 0; 3326 SOC_IF_ERROR_RETURN(READ_CI_DDR_TESTr(unit, cinum, &rval)); 3327 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_TESTf, 1); 3328 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_TESTr(unit, cinum, rval)); 3329 3330 i = 0; 3331 do { 3332 sal_usleep(20); 3333 SOC_IF_ERROR_RETURN(READ_CI_DDR_TESTr(unit, cinum, &rval)); 3334 if (soc_reg_field_get(unit, CI_DDR_TESTr, rval, RAM_DONEf)) { 3335 if (soc_reg_field_get 3336 (unit, CI_DDR_TESTr, rval, RAM_TEST_FAILf)) { 3337 result_fail = 1; 3338 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA0r(unit, cinum, rdPtr)); 3339 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA1r(unit, cinum, rdPtr+1)); 3340 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA2r(unit, cinum, rdPtr+2)); 3341 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA3r(unit, cinum, rdPtr+3)); 3342 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA4r(unit, cinum, rdPtr+4)); 3343 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA5r(unit, cinum, rdPtr+5)); 3344 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA6r(unit, cinum, rdPtr+6)); 3345 SOC_IF_ERROR_RETURN(READ_CI_DDR_TEST_FAILED_DATA7r(unit, cinum, rdPtr+7)); 3346 for(k = 0; k < 8; k++) { 3347 for(m = 31; m >= 16; m--) { 3348 efold |= (((wdata[k] ^ rdata[k]) >> m) & 0x00000001) << ((m%8)+8); 3349 } 3350 for(m = 15; m >= 0; m--) { 3351 efold |= (((wdata[k] ^ rdata[k]) >> m) & 0x00000001) << (m%8); 3352 } 3353 } 3354 } 3355 break; 3356 } 3357 if (i > 10000) { 3358 LOG_ERROR(BSL_LS_SOC_COMMON, 3359 (BSL_META_U(unit, 3360 "Functional Self-Test timeout (1) \n"))); 3361 result_fail = 0xFFFF; 3362 return SOC_E_FAIL; 3363 } 3364 i++; 3365 } while (TRUE); 3366 j++; 3367 } 3368 3369 if (result_fail != 0) { 3370 if((flag & 0x1) == 0) { 3371 if(efold & 0xFF00) { 3372 efold |= 0xFF00; 3373 } 3374 if(efold & 0x00FF) { 3375 efold |= 0x00FF; 3376 } 3377 } 3378 if((flag & 0x2) != 0) { 3379 if(wl == 0) { 3380 READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, &data); 3381 fifo_status0 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS, 3382 STATUS0); 3383 fifo_status1 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS, 3384 STATUS1); 3385 } else { 3386 READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, &data); 3387 fifo_status0 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, 3388 STATUS0); 3389 fifo_status1 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, 3390 STATUS1); 3391 } 3392 efold = 0x0000; 3393 if(fifo_status0 != 0) { 3394 efold |= 0x00FF; 3395 } 3396 if(fifo_status1 != 0) { 3397 efold |= 0xFF00; 3398 } 3399 /* LOG_CLI((BSL_META_U(unit, 3400 "FIFO-0: %d\tFIFO-1: %d\n"), fifo_status0, fifo_status1)); */ 3401 } 3402 if(result_fail != 0xFFFF) { 3403 result_fail = efold; 3404 } 3405 } 3406 3407 return result_fail; 3408 } 3409 3410 uint32 3411 _test_func_self_test_1_katana2(int unit, int ci, int wl, int loop, uint32 flag) 3412 { 3413 uint32 i; 3414 int j, cinum; 3415 uint32 rval = 0; 3416 uint32 result_fail = 0; 3417 uint32 wdata[8]; 3418 uint32 rdata; 3419 int k; 3420 uint32 data = 0, fifo_status0, fifo_status1; 3421 3422 uint32 startAddr; 3423 3424 uint32 efold = 0; 3425 3426 /* _configure_arad_mpr(unit, ci, wl, flag & 0x4); */ 3427 cinum = ci + wl; 3428 3429 j = 0; 3430 while (j < loop) { 3431 rval = 0; 3432 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 3433 if(flag & 0x4) { 3434 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, 0); 3435 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, READWEIGHTf, 255); 3436 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, 0); 3437 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PRBSMODEf, 0); 3438 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 3439 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, 0); 3440 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, 0); 3441 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, 0); 3442 } else { 3443 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, 255); 3444 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, READWEIGHTf, 255); 3445 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, 0); 3446 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PRBSMODEf, 1); 3447 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 3448 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, 0); 3449 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, 0); 3450 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, 0); 3451 } 3452 3453 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 3454 3455 SOC_IF_ERROR_RETURN(READ_BISTNUMBEROFACTIONSr(unit, cinum, &rval)); 3456 soc_reg_field_set(unit, BISTNUMBEROFACTIONSr, &rval, BISTNUMACTIONSf, 510); 3457 SOC_IF_ERROR_RETURN(WRITE_BISTNUMBEROFACTIONSr(unit, cinum, rval)); 3458 3459 /* startAddr = _get_random() & 0xffffff; */ 3460 startAddr = 0x0; 3461 /* SOC_IF_ERROR_RETURN(READ_BISTSTARTADDRESSr(unit, cinum, &rval)); */ 3462 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTSTARTADDRESSr, cinum, 0, &rval)); 3463 soc_reg_field_set(unit, BISTSTARTADDRESSr, &rval, BISTSTARTADDRESSf, startAddr); 3464 /* SOC_IF_ERROR_RETURN(WRITE_BISTSTARTADDRESSr(unit, cinum, rval)); */ 3465 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, BISTSTARTADDRESSr, cinum, 0, rval)); 3466 3467 /* SOC_IF_ERROR_RETURN(READ_BISTENDADDRESSr(unit, cinum, &rval)); */ 3468 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTENDADDRESSr, cinum, 0, &rval)); 3469 soc_reg_field_set(unit, BISTENDADDRESSr, &rval, BISTENDADDRESSf, 0xFFFFFF); 3470 /* SOC_IF_ERROR_RETURN(WRITE_BISTENDADDRESSr(unit, cinum, rval)); */ 3471 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, BISTENDADDRESSr, cinum, 0, rval)); 3472 3473 if(flag & 0x4) { 3474 for(k = 0; k < 8; k+=2) { 3475 wdata[k] = 0x0; 3476 wdata[k+1] = 0xFFFFFFFF; 3477 } 3478 } else { 3479 for(k = 0; k < 8; k++) { 3480 wdata[k] = _get_random(); 3481 } 3482 } 3483 3484 SOC_IF_ERROR_RETURN 3485 (WRITE_BISTPATTERNWORD0r(unit, cinum, wdata[0])); 3486 SOC_IF_ERROR_RETURN 3487 (WRITE_BISTPATTERNWORD1r(unit, cinum, wdata[1])); 3488 SOC_IF_ERROR_RETURN 3489 (WRITE_BISTPATTERNWORD2r(unit, cinum, wdata[2])); 3490 SOC_IF_ERROR_RETURN 3491 (WRITE_BISTPATTERNWORD3r(unit, cinum, wdata[3])); 3492 SOC_IF_ERROR_RETURN 3493 (WRITE_BISTPATTERNWORD4r(unit, cinum, wdata[4])); 3494 SOC_IF_ERROR_RETURN 3495 (WRITE_BISTPATTERNWORD5r(unit, cinum, wdata[5])); 3496 SOC_IF_ERROR_RETURN 3497 (WRITE_BISTPATTERNWORD6r(unit, cinum, wdata[6])); 3498 SOC_IF_ERROR_RETURN 3499 (WRITE_BISTPATTERNWORD7r(unit, cinum, wdata[7])); 3500 3501 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 3502 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, INDWRRDADDRMODEf, 1); 3503 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 3504 3505 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 3506 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 1); 3507 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 3508 3509 i = 0; 3510 do { 3511 sal_usleep(20); 3512 SOC_IF_ERROR_RETURN(READ_BISTSTATUSESr(unit, cinum, &rval)); 3513 if (soc_reg_field_get(unit, BISTSTATUSESr, rval, BISTFINISHEDf)) { 3514 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 3515 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 0); 3516 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 3517 3518 /* SOC_IF_ERROR_RETURN(READ_BISTERROROCCURREDr(unit, cinum, &rval)); */ 3519 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTERROROCCURREDr, cinum, 0, &rval)); 3520 rdata = soc_reg_field_get(unit, BISTERROROCCURREDr, rval, ERROCCURREDf); 3521 /* if(wl == 0) { 3522 efold = rdata & 0xFFFF; 3523 } else { 3524 efold = (rdata >> 16) & 0xFFFF; 3525 } */ 3526 efold = (rdata & 0xFFFF) | ((rdata >> 16) & 0xFFFF); 3527 if(efold != 0) { 3528 result_fail = 1; 3529 } 3530 break; 3531 } 3532 if (i > 10000) { 3533 LOG_ERROR(BSL_LS_SOC_COMMON, 3534 (BSL_META_U(unit, 3535 "Functional Self-Test timeout (1) \n"))); 3536 result_fail = 0xFFFF; 3537 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 3538 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 0); 3539 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 3540 return SOC_E_FAIL; 3541 } 3542 i++; 3543 } while (TRUE); 3544 j++; 3545 } 3546 3547 if ((result_fail != 0) || (flag & 0x2)) { 3548 if((flag & 0x1) == 0) { 3549 if(efold & 0xFF00) { 3550 efold |= 0xFF00; 3551 } 3552 if(efold & 0x00FF) { 3553 efold |= 0x00FF; 3554 } 3555 } 3556 if((flag & 0x2) != 0) { 3557 if(wl == 0) { 3558 READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, &data); 3559 fifo_status0 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS, 3560 STATUS0); 3561 fifo_status1 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS, 3562 STATUS1); 3563 } else { 3564 READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, &data); 3565 fifo_status0 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, 3566 STATUS0); 3567 fifo_status1 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, 3568 STATUS1); 3569 } 3570 efold = 0x0000; 3571 if(fifo_status0 != 0) { 3572 efold |= 0x00FF; 3573 } 3574 if(fifo_status1 != 0) { 3575 efold |= 0xFF00; 3576 } 3577 if(efold != 0x0) { 3578 result_fail = 2; 3579 } 3580 } 3581 if(result_fail != 0xFFFF) { 3582 result_fail = efold; 3583 } 3584 } 3585 3586 return result_fail; 3587 } 3588 3589 #ifdef BCM_PETRA_SUPPORT 3590 uint32 3591 _test_func_self_test_1_arad(int unit, int ci, int wl, int loop, uint32 flag) 3592 { 3593 uint32 i; 3594 int j; 3595 uint32 rval = 0; 3596 uint32 result_fail = 0; 3597 uint32 wdata[8]; 3598 uint32 rdata; 3599 int k; 3600 uint32 data, fifo_status0, fifo_status1; 3601 3602 uint32 startAddr; 3603 3604 uint32 efold = 0; 3605 3606 /* _configure_arad_mpr(unit, ci, wl, flag & 0x4); */ 3607 3608 j = 0; 3609 while (j < loop) { 3610 rval = 0; 3611 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 3612 if(flag & 0x4) { 3613 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, WRITE_WEIGHTf, 0); 3614 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, READ_WEIGHTf, 255); 3615 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, PATTERN_BIT_MODEf, 0); 3616 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, PRBS_MODEf, 0); 3617 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, CONS_ADDR_8_BANKSf, 1); 3618 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, ADDRESS_SHIFT_MODEf, 0); 3619 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, DATA_SHIFT_MODEf, 0); 3620 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, DATA_ADDR_MODEf, 0); 3621 } else { 3622 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, WRITE_WEIGHTf, 255); 3623 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, READ_WEIGHTf, 255); 3624 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, PATTERN_BIT_MODEf, 0); 3625 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, PRBS_MODEf, 1); 3626 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, CONS_ADDR_8_BANKSf, 1); 3627 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, ADDRESS_SHIFT_MODEf, 0); 3628 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, DATA_SHIFT_MODEf, 0); 3629 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, DATA_ADDR_MODEf, 0); 3630 } 3631 3632 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 3633 3634 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_NUMBER_OF_ACTIONSr, &rval)); 3635 soc_reg_field_set(unit, DRCA_BIST_NUMBER_OF_ACTIONSr, &rval, BIST_NUM_ACTIONSf, 510); 3636 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_NUMBER_OF_ACTIONSr, rval)); 3637 3638 /* startAddr = _get_random() & 0xffffff; */ 3639 startAddr = 0x0; 3640 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_START_ADDRESSr, &rval)); 3641 soc_reg_field_set(unit, DRCA_BIST_START_ADDRESSr, &rval, BIST_START_ADDRESSf, startAddr); 3642 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_START_ADDRESSr, rval)); 3643 3644 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_END_ADDRESSr, &rval)); 3645 soc_reg_field_set(unit, DRCA_BIST_END_ADDRESSr, &rval, BIST_END_ADDRESSf, 0xFFFFFF); 3646 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_END_ADDRESSr, rval)); 3647 3648 if(flag & 0x4) { 3649 for(k = 0; k < 8; k+=2) { 3650 wdata[k] = 0x0; 3651 wdata[k+1] = 0xFFFFFFFF; 3652 } 3653 } else { 3654 for(k = 0; k < 8; k++) { 3655 wdata[k] = _get_random(); 3656 } 3657 } 3658 3659 SOC_IF_ERROR_RETURN 3660 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_0r, wdata[0])); 3661 SOC_IF_ERROR_RETURN 3662 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_1r, wdata[1])); 3663 SOC_IF_ERROR_RETURN 3664 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_2r, wdata[2])); 3665 SOC_IF_ERROR_RETURN 3666 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_3r, wdata[3])); 3667 SOC_IF_ERROR_RETURN 3668 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_4r, wdata[4])); 3669 SOC_IF_ERROR_RETURN 3670 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_5r, wdata[5])); 3671 SOC_IF_ERROR_RETURN 3672 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_6r, wdata[6])); 3673 SOC_IF_ERROR_RETURN 3674 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_7r, wdata[7])); 3675 3676 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 3677 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, IND_WR_RD_ADDR_MODEf, 1); 3678 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 3679 3680 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 3681 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, BIST_ENf, 1); 3682 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 3683 3684 i = 0; 3685 do { 3686 sal_usleep(20); 3687 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_STATUSESr, &rval)); 3688 if (soc_reg_field_get(unit, DRCA_BIST_STATUSESr, rval, BIST_FINISHEDf)) { 3689 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 3690 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, BIST_ENf, 0); 3691 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 3692 3693 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_ERROR_OCCURREDr, &rval)); 3694 rdata = soc_reg_field_get(unit, DRCA_BIST_ERROR_OCCURREDr, rval, ERR_OCCURREDf); 3695 if(wl == 0) { 3696 efold = rdata & 0xFFFF; 3697 } else { 3698 efold = (rdata >> 16) & 0xFFFF; 3699 } 3700 if(efold != 0) { 3701 result_fail = 1; 3702 } 3703 break; 3704 } 3705 if (i > 10000) { 3706 LOG_ERROR(BSL_LS_SOC_COMMON, 3707 (BSL_META_U(unit, 3708 "Functional Self-Test timeout (1) \n"))); 3709 result_fail = 0xFFFF; 3710 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 3711 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, BIST_ENf, 0); 3712 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 3713 return SOC_E_FAIL; 3714 } 3715 i++; 3716 } while (TRUE); 3717 j++; 3718 } 3719 3720 if ((result_fail != 0) || (flag & 0x2)) { 3721 if((flag & 0x1) == 0) { 3722 if(efold & 0xFF00) { 3723 efold |= 0xFF00; 3724 } 3725 if(efold & 0x00FF) { 3726 efold |= 0x00FF; 3727 } 3728 } 3729 if((flag & 0x2) != 0) { 3730 if(wl == 0) { 3731 READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, &data); 3732 fifo_status0 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS, 3733 STATUS0); 3734 fifo_status1 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS, 3735 STATUS1); 3736 } else { 3737 READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, &data); 3738 fifo_status0 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, 3739 STATUS0); 3740 fifo_status1 = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, 3741 STATUS1); 3742 } 3743 efold = 0x0000; 3744 if(fifo_status0 != 0) { 3745 efold |= 0x00FF; 3746 } 3747 if(fifo_status1 != 0) { 3748 efold |= 0xFF00; 3749 } 3750 if(efold != 0x0) { 3751 result_fail = 2; 3752 } 3753 /* LOG_CLI((BSL_META_U(unit, 3754 "FIFO-0: %d\tFIFO-1: %d\n"), fifo_status0, fifo_status1)); */ 3755 } 3756 if(result_fail != 0xFFFF) { 3757 result_fail = efold; 3758 } 3759 } 3760 3761 return result_fail; 3762 } 3763 #endif 3764 3765 #ifdef BCM_HURRICANE2_SUPPORT 3766 STATIC uint32 3767 _test_func_self_test_1_hurricane2(int unit, int ci, int wl, int loop, uint32 flag) 3768 { 3769 uint32 i; 3770 int j; 3771 uint32 rval = 0; 3772 uint32 result_fail = 0; 3773 uint32 wdata[8]; 3774 uint32 rdata; 3775 int k; 3776 uint32 data, fifo_status0, fifo_status1; 3777 3778 uint32 startAddr; 3779 3780 uint32 efold = 0; 3781 3782 j = 0; 3783 while (j < loop) { 3784 rval = 0; 3785 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 3786 if(flag & 0x4) { 3787 soc_reg_field_set( 3788 unit, DDR_BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, 0); 3789 soc_reg_field_set( 3790 unit, DDR_BISTCONFIGURATIONSr, &rval, READWEIGHTf, 255); 3791 soc_reg_field_set( 3792 unit, DDR_BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, 0); 3793 soc_reg_field_set( 3794 unit, DDR_BISTCONFIGURATIONSr, &rval, PRBSMODEf, 0); 3795 soc_reg_field_set( 3796 unit, DDR_BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 3797 soc_reg_field_set( 3798 unit, DDR_BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, 0); 3799 soc_reg_field_set( 3800 unit, DDR_BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, 0); 3801 soc_reg_field_set( 3802 unit, DDR_BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, 0); 3803 } else { 3804 soc_reg_field_set( 3805 unit, DDR_BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, 255); 3806 soc_reg_field_set( 3807 unit, DDR_BISTCONFIGURATIONSr, &rval, READWEIGHTf, 255); 3808 soc_reg_field_set( 3809 unit, DDR_BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, 0); 3810 soc_reg_field_set( 3811 unit, DDR_BISTCONFIGURATIONSr, &rval, PRBSMODEf, 1); 3812 soc_reg_field_set( 3813 unit, DDR_BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 3814 soc_reg_field_set( 3815 unit, DDR_BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, 0); 3816 soc_reg_field_set( 3817 unit, DDR_BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, 0); 3818 soc_reg_field_set( 3819 unit, DDR_BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, 0); 3820 } 3821 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 3822 3823 SOC_IF_ERROR_RETURN(READ_DDR_BISTNUMBEROFACTIONSr(unit, &rval)); 3824 soc_reg_field_set( 3825 unit, DDR_BISTNUMBEROFACTIONSr, &rval, BISTNUMACTIONSf, 510); 3826 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTNUMBEROFACTIONSr(unit, rval)); 3827 3828 /* startAddr = _get_random() & 0xffffff; */ 3829 startAddr = 0x0; 3830 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTARTADDRESSr(unit, &rval)); 3831 soc_reg_field_set( 3832 unit, DDR_BISTSTARTADDRESSr, &rval, BISTSTARTADDRESSf, startAddr); 3833 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTSTARTADDRESSr(unit, rval)); 3834 3835 SOC_IF_ERROR_RETURN(READ_DDR_BISTENDADDRESSr(unit, &rval)); 3836 soc_reg_field_set( 3837 unit, DDR_BISTENDADDRESSr, &rval, BISTENDADDRESSf, 0xFFFFFF); 3838 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTENDADDRESSr(unit, rval)); 3839 3840 if(flag & 0x4) { 3841 for(k = 0; k < 8; k+=2) { 3842 wdata[k] = 0x0; 3843 wdata[k+1] = 0xFFFFFFFF; 3844 } 3845 } else { 3846 for(k = 0; k < 8; k++) { 3847 wdata[k] = _get_random(); 3848 } 3849 } 3850 3851 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD0r(unit, wdata[0])); 3852 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD1r(unit, wdata[1])); 3853 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD2r(unit, wdata[2])); 3854 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD3r(unit, wdata[3])); 3855 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD4r(unit, wdata[4])); 3856 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD5r(unit, wdata[5])); 3857 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD6r(unit, wdata[6])); 3858 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD7r(unit, wdata[7])); 3859 3860 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 3861 soc_reg_field_set( 3862 unit, DDR_BISTCONFIGURATIONSr, &rval, INDWRRDADDRMODEf, 1); 3863 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 3864 3865 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 3866 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 1); 3867 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 3868 3869 i = 0; 3870 do { 3871 sal_usleep(20); 3872 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTATUSESr(unit, &rval)); 3873 if (soc_reg_field_get( 3874 unit, DDR_BISTSTATUSESr, rval, BISTFINISHEDf)) { 3875 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 3876 soc_reg_field_set( 3877 unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 3878 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 3879 3880 SOC_IF_ERROR_RETURN(READ_DDR_BISTERROROCCURREDr(unit, &rval)); 3881 rdata = soc_reg_field_get( 3882 unit, DDR_BISTERROROCCURREDr, rval, ERROCCURREDf); 3883 if(wl == 0) { 3884 efold = rdata & 0xFFFF; 3885 } else { 3886 efold = (rdata >> 16) & 0xFFFF; 3887 } 3888 if(efold != 0) { 3889 result_fail = 1; 3890 } 3891 break; 3892 } 3893 if (i > 10000) { 3894 LOG_ERROR(BSL_LS_SOC_COMMON, 3895 (BSL_META_U(unit, 3896 "Functional Self-Test timeout (1) \n"))); 3897 result_fail = 0xFFFF; 3898 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 3899 soc_reg_field_set( 3900 unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 3901 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 3902 return SOC_E_FAIL; 3903 } 3904 i++; 3905 } while (TRUE); 3906 j++; 3907 } 3908 3909 if ((result_fail != 0) || (flag & 0x2)) { 3910 if((flag & 0x1) == 0) { 3911 if(efold & 0xFF00) { 3912 efold |= 0xFF00; 3913 } 3914 if(efold & 0x00FF) { 3915 efold |= 0x00FF; 3916 } 3917 } 3918 if((flag & 0x2) != 0) { 3919 if(wl == 0) { 3920 READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, &data); 3921 fifo_status0 = DDR40_GET_FIELD( 3922 data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS,STATUS0); 3923 fifo_status1 = DDR40_GET_FIELD( 3924 data, DDR40_PHY_WORD_LANE_0, READ_FIFO_STATUS, STATUS1); 3925 } else { 3926 READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, &data); 3927 fifo_status0 = DDR40_GET_FIELD( 3928 data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, STATUS0); 3929 fifo_status1 = DDR40_GET_FIELD( 3930 data, DDR40_PHY_WORD_LANE_1, READ_FIFO_STATUS, STATUS1); 3931 } 3932 efold = 0x0000; 3933 if(fifo_status0 != 0) { 3934 efold |= 0x00FF; 3935 } 3936 if(fifo_status1 != 0) { 3937 efold |= 0xFF00; 3938 } 3939 if(efold != 0x0) { 3940 result_fail = 2; 3941 } 3942 /* LOG_CLI((BSL_META_U(unit, 3943 "FIFO-0: %d\tFIFO-1: %d\n"), fifo_status0, fifo_status1)); */ 3944 } 3945 if(result_fail != 0xFFFF) { 3946 result_fail = efold; 3947 } 3948 } 3949 3950 return result_fail; 3951 } 3952 #endif /* BCM_HURRICANE2_SUPPORT */ 3953 3954 /* Flag Settings: 3955 * flag[0]: 0 - Mask errors per byte 3956 * 1 - Do not mask errors 3957 * flag[1]: 0 - Compare data 3958 * 1 - Check FIFO status 3959 * flag[2]: 0 - Disable MPR 3960 * 1 - Enable MPR 3961 */ 3962 3963 uint32 3964 _test_func_self_test_1(int unit, int ci, int wl, int loop, uint32 flag) 3965 { 3966 if(SOC_IS_KATANA(unit)) { 3967 return _test_func_self_test_1_katana(unit, ci, wl, loop, flag); 3968 } else if(SOC_IS_KATANA2(unit)) { 3969 return _test_func_self_test_1_katana2(unit, ci, wl, loop, flag);; 3970 #ifdef BCM_PETRA_SUPPORT 3971 } else if(SOC_IS_ARAD(unit)) { 3972 return _test_func_self_test_1_arad(unit, ci, wl, loop, flag); 3973 #endif 3974 #ifdef BCM_HURRICANE2_SUPPORT 3975 } else if(SOC_IS_HURRICANE2(unit)) { 3976 return _test_func_self_test_1_hurricane2(unit, ci, wl, loop, flag); 3977 #endif 3978 } else { 3979 return SOC_E_INTERNAL; /* Unsupported configuration */ 3980 } 3981 } 3982 3983 uint32 3984 _test_func_self_test_2_katana(int unit, int ci, int wl, int loop) 3985 { 3986 int i, j, lane, cinum; 3987 uint32 rval = 0; 3988 uint32 result_fail = 0; 3989 uint32 max_num_lane; 3990 3991 max_num_lane = 2; 3992 3993 /* Alternate data test */ 3994 cinum = ci + wl; 3995 for (lane = 0; lane < max_num_lane; lane++) { 3996 if(!_check_dram(ci+lane)) { 3997 continue; 3998 } 3999 j = 0; 4000 while (j < loop) { 4001 rval = 0; 4002 SOC_IF_ERROR_RETURN(READ_CI_DDR_TESTr(unit, (ci + lane), &rval)); 4003 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, MODEf, 0); 4004 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_TESTf, 0); 4005 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_DONEf, 1); /* write 1 to clear */ 4006 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_TEST_FAILf, 1); /* write 1 to clear */ 4007 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_TESTr(unit, (ci + lane), rval)); 4008 SOC_IF_ERROR_RETURN(READ_CI_DDR_TESTr(unit, (ci + lane), &rval)); 4009 4010 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_BURSTr 4011 (unit, cinum, 0x1FF0)); 4012 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_STEPr(unit, (ci + lane), 1)); 4013 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_ITERr 4014 (unit, cinum, 2)); 4015 4016 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_STARTr(unit, cinum, (_get_random() & 0xffffff))); 4017 4018 SOC_IF_ERROR_RETURN 4019 (WRITE_CI_DDR_TEST_DATA0r(unit, cinum, _get_random())); 4020 SOC_IF_ERROR_RETURN 4021 (WRITE_CI_DDR_TEST_DATA1r(unit, cinum, _get_random())); 4022 SOC_IF_ERROR_RETURN 4023 (WRITE_CI_DDR_TEST_DATA2r(unit, cinum, _get_random())); 4024 SOC_IF_ERROR_RETURN 4025 (WRITE_CI_DDR_TEST_DATA3r(unit, cinum, _get_random())); 4026 SOC_IF_ERROR_RETURN 4027 (WRITE_CI_DDR_TEST_DATA4r(unit, cinum, _get_random())); 4028 SOC_IF_ERROR_RETURN 4029 (WRITE_CI_DDR_TEST_DATA5r(unit, cinum, _get_random())); 4030 SOC_IF_ERROR_RETURN 4031 (WRITE_CI_DDR_TEST_DATA6r(unit, cinum, _get_random())); 4032 SOC_IF_ERROR_RETURN 4033 (WRITE_CI_DDR_TEST_DATA7r(unit, cinum, _get_random())); 4034 4035 SOC_IF_ERROR_RETURN 4036 (WRITE_CI_DDR_TEST_ALT_DATA0r(unit, cinum, _get_random())); 4037 SOC_IF_ERROR_RETURN 4038 (WRITE_CI_DDR_TEST_ALT_DATA1r(unit, cinum, _get_random())); 4039 SOC_IF_ERROR_RETURN 4040 (WRITE_CI_DDR_TEST_ALT_DATA2r(unit, cinum, _get_random())); 4041 SOC_IF_ERROR_RETURN 4042 (WRITE_CI_DDR_TEST_ALT_DATA3r(unit, cinum, _get_random())); 4043 SOC_IF_ERROR_RETURN 4044 (WRITE_CI_DDR_TEST_ALT_DATA4r(unit, cinum, _get_random())); 4045 SOC_IF_ERROR_RETURN 4046 (WRITE_CI_DDR_TEST_ALT_DATA5r(unit, cinum, _get_random())); 4047 SOC_IF_ERROR_RETURN 4048 (WRITE_CI_DDR_TEST_ALT_DATA6r(unit, cinum, _get_random())); 4049 SOC_IF_ERROR_RETURN 4050 (WRITE_CI_DDR_TEST_ALT_DATA7r(unit, cinum, _get_random())); 4051 4052 rval = 0; 4053 soc_reg_field_set(unit, CI_DDR_TESTr, &rval, RAM_TESTf, 1); 4054 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_TESTr(unit, (ci + lane), rval)); 4055 4056 i = 0; 4057 do { 4058 sal_usleep(20); 4059 SOC_IF_ERROR_RETURN(READ_CI_DDR_TESTr 4060 (unit, (ci + lane), &rval)); 4061 if (soc_reg_field_get(unit, CI_DDR_TESTr, rval, RAM_DONEf)) { 4062 if (soc_reg_field_get 4063 (unit, CI_DDR_TESTr, rval, RAM_TEST_FAILf)) { 4064 result_fail = result_fail + 1; 4065 } 4066 break; 4067 } 4068 if (i > 100000) { 4069 LOG_ERROR(BSL_LS_SOC_COMMON, 4070 (BSL_META_U(unit, 4071 "Functional Self-Test timeout (2) \n"))); 4072 return SOC_E_FAIL; 4073 } 4074 i++; 4075 } while (TRUE); 4076 j++; 4077 } 4078 } 4079 4080 if (result_fail > 0) { 4081 result_fail = 0xffff; 4082 } 4083 4084 return result_fail; 4085 } 4086 4087 uint32 4088 _test_func_self_test_2_katana2(int unit, int ci, int wl, int loop) 4089 { 4090 int i, j, cinum; 4091 uint32 rval = 0; 4092 uint32 result_fail = 0; 4093 uint32 result_both = 0; 4094 uint32 wdata[8]; 4095 int k, dram; 4096 4097 uint32 startAddr; 4098 4099 /* Alternate data test */ 4100 for(dram = 0; dram < 2; dram++) { 4101 cinum = ci + dram; 4102 4103 if(!_check_dram(cinum)) { 4104 continue; 4105 } 4106 4107 j = 0; 4108 while (j < loop) { 4109 rval = 0; 4110 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 4111 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, 255); 4112 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, READWEIGHTf, 255); 4113 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, 0); 4114 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PRBSMODEf, 1); 4115 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 4116 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, 0); 4117 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, 0); 4118 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, 0); 4119 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 4120 4121 SOC_IF_ERROR_RETURN(READ_BISTNUMBEROFACTIONSr(unit, cinum, &rval)); 4122 soc_reg_field_set(unit, BISTNUMBEROFACTIONSr, &rval, BISTNUMACTIONSf, 510); 4123 SOC_IF_ERROR_RETURN(WRITE_BISTNUMBEROFACTIONSr(unit, cinum, rval)); 4124 4125 /* startAddr = _get_random() & 0xffffff; */ 4126 startAddr =0x0; 4127 /* SOC_IF_ERROR_RETURN(READ_BISTSTARTADDRESSr(unit, cinum, &rval)); */ 4128 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTSTARTADDRESSr, cinum, 0, &rval)); 4129 soc_reg_field_set(unit, BISTSTARTADDRESSr, &rval, BISTSTARTADDRESSf, startAddr); 4130 /* SOC_IF_ERROR_RETURN(WRITE_BISTSTARTADDRESSr(unit, cinum, rval)); */ 4131 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, BISTSTARTADDRESSr, cinum, 0, rval)); 4132 4133 /* SOC_IF_ERROR_RETURN(READ_BISTENDADDRESSr(unit, cinum, &rval)); */ 4134 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTENDADDRESSr, cinum, 0, &rval)); 4135 soc_reg_field_set(unit, BISTENDADDRESSr, &rval, BISTENDADDRESSf, 0xFFFFFF); 4136 /* SOC_IF_ERROR_RETURN(WRITE_BISTENDADDRESSr(unit, cinum, rval)); */ 4137 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, BISTENDADDRESSr, cinum, 0, rval)); 4138 4139 for(k = 0; k < 8; k++) { 4140 wdata[k] = _get_random(); 4141 } 4142 4143 SOC_IF_ERROR_RETURN 4144 (WRITE_BISTPATTERNWORD0r(unit, cinum, wdata[0])); 4145 SOC_IF_ERROR_RETURN 4146 (WRITE_BISTPATTERNWORD1r(unit, cinum, wdata[1])); 4147 SOC_IF_ERROR_RETURN 4148 (WRITE_BISTPATTERNWORD2r(unit, cinum, wdata[2])); 4149 SOC_IF_ERROR_RETURN 4150 (WRITE_BISTPATTERNWORD3r(unit, cinum, wdata[3])); 4151 SOC_IF_ERROR_RETURN 4152 (WRITE_BISTPATTERNWORD4r(unit, cinum, wdata[4])); 4153 SOC_IF_ERROR_RETURN 4154 (WRITE_BISTPATTERNWORD5r(unit, cinum, wdata[5])); 4155 SOC_IF_ERROR_RETURN 4156 (WRITE_BISTPATTERNWORD6r(unit, cinum, wdata[6])); 4157 SOC_IF_ERROR_RETURN 4158 (WRITE_BISTPATTERNWORD7r(unit, cinum, wdata[7])); 4159 4160 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 4161 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, INDWRRDADDRMODEf, 1); 4162 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 4163 4164 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 4165 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 1); 4166 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 4167 4168 i = 0; 4169 do { 4170 sal_usleep(20); 4171 SOC_IF_ERROR_RETURN(READ_BISTSTATUSESr(unit, cinum, &rval)); 4172 if (soc_reg_field_get(unit, BISTSTATUSESr, rval, BISTFINISHEDf)) { 4173 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 4174 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 0); 4175 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 4176 4177 /* SOC_IF_ERROR_RETURN(READ_BISTERROROCCURREDr(unit, cinum, &rval)); */ 4178 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTERROROCCURREDr, cinum, 0, &rval)); 4179 result_fail = soc_reg_field_get(unit, BISTERROROCCURREDr, rval, ERROCCURREDf); 4180 result_fail = (result_fail & 0xFFFF) | ((result_fail >> 16) & 0xFFFF); 4181 break; 4182 } 4183 if (i > 10000) { 4184 LOG_ERROR(BSL_LS_SOC_COMMON, 4185 (BSL_META_U(unit, 4186 "Functional Self-Test timeout (1) \n"))); 4187 result_fail = 0xFFFF; 4188 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, cinum, &rval)); 4189 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 0); 4190 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, cinum, rval)); 4191 return SOC_E_FAIL; 4192 } 4193 i++; 4194 } while (TRUE); 4195 j++; 4196 } 4197 4198 if (result_fail > 0) { 4199 result_fail = 0xffff; 4200 } 4201 4202 result_both |= result_fail; 4203 } 4204 4205 return result_both; 4206 } 4207 4208 #ifdef BCM_PETRA_SUPPORT 4209 uint32 4210 _test_func_self_test_2_arad(int unit, int ci, int wl, int loop) 4211 { 4212 int i, j; 4213 uint32 rval = 0; 4214 uint32 result_fail = 0; 4215 uint32 wdata[8]; 4216 int k; 4217 4218 uint32 startAddr; 4219 4220 /* Alternate data test */ 4221 j = 0; 4222 while (j < loop) { 4223 rval = 0; 4224 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, (ci>>1), DRC_BIST_CONFIGURATIONSr, &rval)); 4225 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, WRITE_WEIGHTf, 255); 4226 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, READ_WEIGHTf, 255); 4227 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, PATTERN_BIT_MODEf, 0); 4228 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, PRBS_MODEf, 1); 4229 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, CONS_ADDR_8_BANKSf, 1); 4230 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, ADDRESS_SHIFT_MODEf, 0); 4231 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, DATA_SHIFT_MODEf, 0); 4232 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, DATA_ADDR_MODEf, 0); 4233 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 4234 4235 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_NUMBER_OF_ACTIONSr, &rval)); 4236 soc_reg_field_set(unit, DRCA_BIST_NUMBER_OF_ACTIONSr, &rval, BIST_NUM_ACTIONSf, 510); 4237 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_NUMBER_OF_ACTIONSr, rval)); 4238 4239 /* startAddr = _get_random() & 0xffffff; */ 4240 startAddr =0x0; 4241 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_START_ADDRESSr, &rval)); 4242 soc_reg_field_set(unit, DRCA_BIST_START_ADDRESSr, &rval, BIST_START_ADDRESSf, startAddr); 4243 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_START_ADDRESSr, rval)); 4244 4245 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_END_ADDRESSr, &rval)); 4246 soc_reg_field_set(unit, DRCA_BIST_END_ADDRESSr, &rval, BIST_END_ADDRESSf, 0xFFFFFF); 4247 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_END_ADDRESSr, rval)); 4248 4249 for(k = 0; k < 8; k++) { 4250 wdata[k] = _get_random(); 4251 } 4252 4253 SOC_IF_ERROR_RETURN 4254 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_0r, wdata[0])); 4255 SOC_IF_ERROR_RETURN 4256 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_1r, wdata[1])); 4257 SOC_IF_ERROR_RETURN 4258 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_2r, wdata[2])); 4259 SOC_IF_ERROR_RETURN 4260 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_3r, wdata[3])); 4261 SOC_IF_ERROR_RETURN 4262 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_4r, wdata[4])); 4263 SOC_IF_ERROR_RETURN 4264 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_5r, wdata[5])); 4265 SOC_IF_ERROR_RETURN 4266 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_6r, wdata[6])); 4267 SOC_IF_ERROR_RETURN 4268 (DRC_REG_WRITE(unit, ci>>1, DRC_BIST_PATTERN_WORD_7r, wdata[7])); 4269 4270 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 4271 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, IND_WR_RD_ADDR_MODEf, 1); 4272 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 4273 4274 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 4275 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, BIST_ENf, 1); 4276 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 4277 4278 i = 0; 4279 do { 4280 sal_usleep(20); 4281 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_STATUSESr, &rval)); 4282 if (soc_reg_field_get(unit, DRCA_BIST_STATUSESr, rval, BIST_FINISHEDf)) { 4283 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 4284 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, BIST_ENf, 0); 4285 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 4286 4287 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_ERROR_OCCURREDr, &rval)); 4288 result_fail = soc_reg_field_get(unit, DRCA_BIST_ERROR_OCCURREDr, rval, ERR_OCCURREDf); 4289 break; 4290 } 4291 if (i > 10000) { 4292 LOG_ERROR(BSL_LS_SOC_COMMON, 4293 (BSL_META_U(unit, 4294 "Functional Self-Test timeout (1) \n"))); 4295 result_fail = 0xFFFF; 4296 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, &rval)); 4297 soc_reg_field_set(unit, DRCA_BIST_CONFIGURATIONSr, &rval, BIST_ENf, 0); 4298 SOC_IF_ERROR_RETURN(DRC_REG_WRITE(unit, ci>>1, DRC_BIST_CONFIGURATIONSr, rval)); 4299 return SOC_E_FAIL; 4300 } 4301 i++; 4302 } while (TRUE); 4303 j++; 4304 } 4305 4306 if (result_fail > 0) { 4307 result_fail = 0xffff; 4308 } 4309 4310 return result_fail; 4311 } 4312 #endif 4313 4314 #ifdef BCM_HURRICANE2_SUPPORT 4315 STATIC uint32 4316 _test_func_self_test_2_hurricane2(int unit, int ci, int wl, int loop) 4317 { 4318 int i, j; 4319 uint32 rval = 0; 4320 uint32 result_fail = 0; 4321 uint32 wdata[8]; 4322 int k; 4323 4324 uint32 startAddr; 4325 4326 /* Alternate data test */ 4327 j = 0; 4328 while (j < loop) { 4329 rval = 0; 4330 4331 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 4332 soc_reg_field_set( 4333 unit, DDR_BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, 255); 4334 soc_reg_field_set( 4335 unit, DDR_BISTCONFIGURATIONSr, &rval, READWEIGHTf, 255); 4336 soc_reg_field_set( 4337 unit, DDR_BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, 0); 4338 soc_reg_field_set( 4339 unit, DDR_BISTCONFIGURATIONSr, &rval, PRBSMODEf, 1); 4340 soc_reg_field_set( 4341 unit, DDR_BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 4342 soc_reg_field_set( 4343 unit, DDR_BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, 0); 4344 soc_reg_field_set( 4345 unit, DDR_BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, 0); 4346 soc_reg_field_set( 4347 unit, DDR_BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, 0); 4348 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 4349 4350 SOC_IF_ERROR_RETURN(READ_DDR_BISTNUMBEROFACTIONSr(unit, &rval)); 4351 soc_reg_field_set( 4352 unit, DDR_BISTNUMBEROFACTIONSr, &rval, BISTNUMACTIONSf, 510); 4353 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTNUMBEROFACTIONSr(unit, rval)); 4354 4355 /* startAddr = _get_random() & 0xffffff; */ 4356 startAddr = 0x0; 4357 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTARTADDRESSr(unit, &rval)); 4358 soc_reg_field_set( 4359 unit, DDR_BISTSTARTADDRESSr, &rval, BISTSTARTADDRESSf, startAddr); 4360 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTSTARTADDRESSr(unit, rval)); 4361 4362 SOC_IF_ERROR_RETURN(READ_DDR_BISTENDADDRESSr(unit, &rval)); 4363 soc_reg_field_set( 4364 unit, DDR_BISTENDADDRESSr, &rval, BISTENDADDRESSf, 0xFFFFFF); 4365 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTENDADDRESSr(unit, rval)); 4366 4367 4368 for(k = 0; k < 8; k++) { 4369 wdata[k] = _get_random(); 4370 } 4371 4372 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD0r(unit, wdata[0])); 4373 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD1r(unit, wdata[1])); 4374 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD2r(unit, wdata[2])); 4375 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD3r(unit, wdata[3])); 4376 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD4r(unit, wdata[4])); 4377 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD5r(unit, wdata[5])); 4378 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD6r(unit, wdata[6])); 4379 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD7r(unit, wdata[7])); 4380 4381 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 4382 soc_reg_field_set( 4383 unit, DDR_BISTCONFIGURATIONSr, &rval, INDWRRDADDRMODEf, 1); 4384 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 4385 4386 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 4387 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 1); 4388 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 4389 4390 i = 0; 4391 4392 do { 4393 sal_usleep(20); 4394 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTATUSESr(unit, &rval)); 4395 if (soc_reg_field_get( 4396 unit, DDR_BISTSTATUSESr, rval, BISTFINISHEDf)) { 4397 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 4398 soc_reg_field_set( 4399 unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 4400 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 4401 4402 SOC_IF_ERROR_RETURN(READ_DDR_BISTERROROCCURREDr(unit, &rval)); 4403 result_fail = soc_reg_field_get( 4404 unit, DDR_BISTERROROCCURREDr, rval, ERROCCURREDf); 4405 break; 4406 } 4407 if (i > 10000) { 4408 LOG_ERROR(BSL_LS_SOC_COMMON, 4409 (BSL_META_U(unit, 4410 "Functional Self-Test timeout (1) \n"))); 4411 result_fail = 0xFFFF; 4412 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 4413 soc_reg_field_set( 4414 unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 4415 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 4416 return SOC_E_FAIL; 4417 } 4418 i++; 4419 } while (TRUE); 4420 j++; 4421 } 4422 4423 if (result_fail > 0) { 4424 result_fail = 0xffff; 4425 } 4426 4427 return result_fail; 4428 } 4429 #endif /* BCM_HURRICANE2_SUPPORT */ 4430 4431 uint32 4432 _test_func_self_test_2(int unit, int ci, int wl, int loop) 4433 { 4434 if(SOC_IS_KATANA(unit)) { 4435 return _test_func_self_test_2_katana(unit, ci, wl, loop); 4436 } else if(SOC_IS_KATANA2(unit)) { 4437 return _test_func_self_test_2_katana2(unit, ci, wl, loop); 4438 #ifdef BCM_PETRA_SUPPORT 4439 } else if(SOC_IS_ARAD(unit)) { 4440 return _test_func_self_test_2_arad(unit, ci, wl, loop); 4441 #endif 4442 #ifdef BCM_HURRICANE2_SUPPORT 4443 } else if(SOC_IS_HURRICANE2(unit)) { 4444 return _test_func_self_test_2_hurricane2(unit, ci, wl, loop); 4445 #endif 4446 } else { 4447 return SOC_E_INTERNAL; /* Unsupported configuration */ 4448 } 4449 } 4450 4451 STATIC uint32 _test_mem_read(int unit, int ci, uint32 addr, uint32 * data_exp) 4452 { 4453 int i, j; 4454 uint32 uDataRD[NUM_DATA]; 4455 uint32 result = 0; 4456 4457 if(!SOC_IS_KATANAX(unit)) { 4458 return result; 4459 } 4460 4461 for (i = 0; i < NUM_DATA / 8; i++) { 4462 soc_ddr40_read(unit, ci, addr + i, &uDataRD[(i * 8)], 4463 &uDataRD[(i * 8) + 1], &uDataRD[(i * 8) + 2], 4464 &uDataRD[(i * 8) + 3], &uDataRD[(i * 8) + 4], 4465 &uDataRD[(i * 8) + 5], &uDataRD[(i * 8) + 6], 4466 &uDataRD[(i * 8) + 7]); 4467 4468 if (data_exp != NULL) { 4469 for (j = 0; j < 8; j++) { 4470 if (data_exp[(i * 8) + j] != uDataRD[(i * 8) + j]) { 4471 result |= data_exp[(i * 8) + j] ^ uDataRD[(i * 8) + j]; 4472 } 4473 } 4474 result |= (result >> 16); 4475 result &= 0xFFFF; 4476 } 4477 } 4478 return result; 4479 } 4480 4481 STATIC uint32 _test_mem_wr_rd(int unit, int ci, uint32 addr) 4482 { 4483 uint32 uDataWR[NUM_DATA]; 4484 uint32 result = 0; 4485 4486 if(!SOC_IS_KATANAX(unit)) { 4487 return result; 4488 } 4489 4490 _fill_in_data(uDataWR); 4491 _test_mem_write(unit, ci, addr, uDataWR); 4492 4493 result = _test_mem_read(unit, ci, addr, uDataWR); 4494 4495 return result; 4496 } 4497 4498 /* Prepare for shmoo-calibration */ 4499 int _soc_ddr_shmoo_prepare_for_shmoo(int unit, int ci) 4500 { 4501 int wl; 4502 uint32 data = 0; 4503 int timeout_cnt, calib_steps; 4504 int clock_period1000, clock_period; 4505 4506 wl = 0; 4507 /* I want to display all STATUS value here and report */ 4508 READ_DDR40_PHY_CONTROL_REGS_PLL_STATUSr(unit, ci, &data); 4509 LOG_INFO(BSL_LS_SOC_DDR, 4510 (BSL_META_U(unit, 4511 "(WL=%d) data = 0x%x \n"), wl, data)); 4512 LOG_INFO(BSL_LS_SOC_DDR, 4513 (BSL_META_U(unit, 4514 "(WL=%d) PLL_STATUS : LOCK_LOST = 0x%x \n"), wl, 4515 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, PLL_STATUS, 4516 LOCK_LOST))); 4517 4518 LOG_INFO(BSL_LS_SOC_DDR, 4519 (BSL_META_U(unit, 4520 "(WL=%d) PLL_STATUS : LOCK = 0x%x \n"), wl, 4521 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, PLL_STATUS, 4522 LOCK))); 4523 READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(unit, ci, &data); 4524 4525 LOG_INFO(BSL_LS_SOC_DDR, 4526 (BSL_META_U(unit, 4527 "(WL=%d) data = 0x%x \n"), wl, data)); 4528 4529 LOG_INFO(BSL_LS_SOC_DDR, 4530 (BSL_META_U(unit, 4531 "(WL=%d) ZQ_PVT_COMP_CTL : PD_COMP = 0x%x \n"), wl, 4532 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, ZQ_PVT_COMP_CTL, 4533 PD_COMP))); 4534 4535 LOG_INFO(BSL_LS_SOC_DDR, 4536 (BSL_META_U(unit, 4537 "(WL=%d) ZQ_PVT_COMP_CTL : ND_COMP = 0x%x \n"), wl, 4538 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, ZQ_PVT_COMP_CTL, 4539 ND_COMP))); 4540 if (wl == 0) { 4541 READ_DDR40_PHY_WORD_LANE_0_READ_CONTROLr(unit, ci, &data); 4542 4543 LOG_INFO(BSL_LS_SOC_DDR, 4544 (BSL_META_U(unit, 4545 "(WL=%d) data = 0x%x \n"), wl, data)); 4546 4547 LOG_INFO(BSL_LS_SOC_DDR, 4548 (BSL_META_U(unit, 4549 "(WL=%d) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_ENABLE = 0x%x \n"), 4550 wl, DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_CONTROL, 4551 DQ_ODT_ENABLE))); 4552 4553 LOG_INFO(BSL_LS_SOC_DDR, 4554 (BSL_META_U(unit, 4555 "(WL=%d) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_LE_ADJ = 0x%x \n"), 4556 wl, DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_CONTROL, 4557 DQ_ODT_LE_ADJ))); 4558 4559 LOG_INFO(BSL_LS_SOC_DDR, 4560 (BSL_META_U(unit, 4561 "(WL=%d) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_TE_ADJ = 0x%x \n"), 4562 wl, DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, READ_CONTROL, 4563 DQ_ODT_TE_ADJ))); 4564 } else { /* if (wl==0) */ 4565 READ_DDR40_PHY_WORD_LANE_1_READ_CONTROLr(unit, ci, &data); 4566 4567 LOG_INFO(BSL_LS_SOC_DDR, 4568 (BSL_META_U(unit, 4569 "(WL=%d) data = 0x%x \n"), wl, data)); 4570 4571 LOG_INFO(BSL_LS_SOC_DDR, 4572 (BSL_META_U(unit, 4573 "(WL=%d) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_ENABLE = 0x%x \n"), 4574 wl, DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_CONTROL, 4575 DQ_ODT_ENABLE))); 4576 4577 LOG_INFO(BSL_LS_SOC_DDR, 4578 (BSL_META_U(unit, 4579 "(WL=%d) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_LE_ADJ = 0x%x \n"), 4580 wl, DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_CONTROL, 4581 DQ_ODT_LE_ADJ))); 4582 4583 LOG_INFO(BSL_LS_SOC_DDR, 4584 (BSL_META_U(unit, 4585 "(WL=%d) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_TE_ADJ = 0x%x \n"), 4586 wl, DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, READ_CONTROL, 4587 DQ_ODT_TE_ADJ))); 4588 } 4589 READ_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, ci, &data); 4590 LOG_INFO(BSL_LS_SOC_DDR, 4591 (BSL_META_U(unit, 4592 "(WL=%d) data = 0x%x \n"), 4593 wl, data)); 4594 LOG_INFO(BSL_LS_SOC_DDR, 4595 (BSL_META_U(unit, 4596 "(WL=%d) VDL_CALIBRATE : CALIB_FAST = 0x%x \n"), 4597 wl, 4598 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4599 CALIB_FAST))); 4600 LOG_INFO(BSL_LS_SOC_DDR, 4601 (BSL_META_U(unit, 4602 "(WL=%d) VDL_CALIBRATE : CALIB_ONCE = 0x%x \n"), 4603 wl, 4604 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4605 CALIB_ONCE))); 4606 LOG_INFO(BSL_LS_SOC_DDR, 4607 (BSL_META_U(unit, 4608 "(WL=%d) VDL_CALIBRATE : CALIB_ALWAYS = 0x%x \n"), 4609 wl, 4610 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4611 CALIB_ALWAYS))); 4612 LOG_INFO(BSL_LS_SOC_DDR, 4613 (BSL_META_U(unit, 4614 "(WL=%d) VDL_CALIBRATE : CALIB_TEST = 0x%x \n"), 4615 wl, 4616 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4617 CALIB_TEST))); 4618 LOG_INFO(BSL_LS_SOC_DDR, 4619 (BSL_META_U(unit, 4620 "(WL=%d) VDL_CALIBRATE : CALIB_CLOCKS = 0x%x \n"), 4621 wl, 4622 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4623 CALIB_CLOCKS))); 4624 LOG_INFO(BSL_LS_SOC_DDR, 4625 (BSL_META_U(unit, 4626 "(WL=%d) VDL_CALIBRATE : CALIB_BYTE = 0x%x \n"), 4627 wl, 4628 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4629 CALIB_BYTE))); 4630 LOG_INFO(BSL_LS_SOC_DDR, 4631 (BSL_META_U(unit, 4632 "(WL=%d) VDL_CALIBRATE : CALIB_PHYBIST = 0x%x \n"), 4633 wl, 4634 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4635 CALIB_PHYBIST))); 4636 LOG_INFO(BSL_LS_SOC_DDR, 4637 (BSL_META_U(unit, 4638 "(WL=%d) VDL_CALIBRATE : CALIB_FTM = 0x%x \n"), 4639 wl, 4640 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4641 CALIB_FTM))); 4642 LOG_INFO(BSL_LS_SOC_DDR, 4643 (BSL_META_U(unit, 4644 "(WL=%d) VDL_CALIBRATE : CALIB_AUTO = 0x%x \n"), 4645 wl, 4646 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4647 CALIB_AUTO))); 4648 LOG_INFO(BSL_LS_SOC_DDR, 4649 (BSL_META_U(unit, 4650 "(WL=%d) VDL_CALIBRATE : CALIB_STEPS = 0x%x \n"), 4651 wl, 4652 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4653 CALIB_STEPS))); 4654 LOG_INFO(BSL_LS_SOC_DDR, 4655 (BSL_META_U(unit, 4656 "(WL=%d) VDL_CALIBRATE : CALIB_DQS_PAIR = 0x%x \n"), 4657 wl, 4658 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4659 CALIB_DQS_PAIR))); 4660 LOG_INFO(BSL_LS_SOC_DDR, 4661 (BSL_META_U(unit, 4662 "(WL=%d) VDL_CALIBRATE : CALIB_DQS_CLOCKS = 0x%x \n"), 4663 wl, 4664 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4665 CALIB_DQS_CLOCKS))); 4666 LOG_INFO(BSL_LS_SOC_DDR, 4667 (BSL_META_U(unit, 4668 "(WL=%d) VDL_CALIBRATE : CALIB_BIT_OFFSET = 0x%x \n"), 4669 wl, 4670 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4671 CALIB_BIT_OFFSET))); 4672 LOG_INFO(BSL_LS_SOC_DDR, 4673 (BSL_META_U(unit, 4674 "(WL=%d) VDL_CALIBRATE : RD_EN_CAL = 0x%x \n"), 4675 wl, 4676 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4677 RD_EN_CAL))); 4678 LOG_INFO(BSL_LS_SOC_DDR, 4679 (BSL_META_U(unit, 4680 "(WL=%d) VDL_CALIBRATE : BIT_CAL = 0x%x \n"), 4681 wl, 4682 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4683 BIT_CAL))); 4684 LOG_INFO(BSL_LS_SOC_DDR, 4685 (BSL_META_U(unit, 4686 "(WL=%d) VDL_CALIBRATE : SET_MR_MPR = 0x%x \n"), 4687 wl, 4688 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4689 SET_MR_MPR))); 4690 LOG_INFO(BSL_LS_SOC_DDR, 4691 (BSL_META_U(unit, 4692 "(WL=%d) VDL_CALIBRATE : DQ0_ONLY = 0x%x \n"), 4693 wl, 4694 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4695 DQ0_ONLY))); 4696 LOG_INFO(BSL_LS_SOC_DDR, 4697 (BSL_META_U(unit, 4698 "(WL=%d) VDL_CALIBRATE : SET_WR_DQ = 0x%x \n"), 4699 wl, 4700 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4701 SET_WR_DQ))); 4702 LOG_INFO(BSL_LS_SOC_DDR, 4703 (BSL_META_U(unit, 4704 "(WL=%d) VDL_CALIBRATE : BIT_REFRESH = 0x%x \n"), 4705 wl, 4706 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4707 BIT_REFRESH))); 4708 LOG_INFO(BSL_LS_SOC_DDR, 4709 (BSL_META_U(unit, 4710 "(WL=%d) VDL_CALIBRATE : RD_DLY_CAL = 0x%x \n"), 4711 wl, 4712 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4713 RD_DLY_CAL))); 4714 LOG_INFO(BSL_LS_SOC_DDR, 4715 (BSL_META_U(unit, 4716 "(WL=%d) VDL_CALIBRATE : EXIT_IN_SR = 0x%x \n"), 4717 wl, 4718 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4719 EXIT_IN_SR))); 4720 LOG_INFO(BSL_LS_SOC_DDR, 4721 (BSL_META_U(unit, 4722 "(WL=%d) VDL_CALIBRATE : SKIP_RST = 0x%x \n"), 4723 wl, 4724 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4725 SKIP_RST))); 4726 LOG_INFO(BSL_LS_SOC_DDR, 4727 (BSL_META_U(unit, 4728 "(WL=%d) VDL_CALIBRATE : AUTO_INIT = 0x%x \n"), 4729 wl, 4730 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4731 AUTO_INIT))); 4732 LOG_INFO(BSL_LS_SOC_DDR, 4733 (BSL_META_U(unit, 4734 "(WL=%d) VDL_CALIBRATE : USE_STRAPS = 0x%x \n"), 4735 wl, 4736 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIBRATE, 4737 USE_STRAPS))); 4738 READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit, ci, &data); 4739 LOG_INFO(BSL_LS_SOC_DDR, 4740 (BSL_META_U(unit, 4741 "(WL=%d) data = 0x%x \n"), 4742 wl, data)); 4743 LOG_INFO(BSL_LS_SOC_DDR, 4744 (BSL_META_U(unit, 4745 "(WL=%d) VDL_CALIB_STATUS : CALIB_LOCK = 0x%x \n"), 4746 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 4747 CALIB_LOCK))); 4748 LOG_INFO(BSL_LS_SOC_DDR, 4749 (BSL_META_U(unit, 4750 "(WL=%d) VDL_CALIB_STATUS : CALIB_IDLE = 0x%x \n"), 4751 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 4752 CALIB_IDLE))); 4753 LOG_INFO(BSL_LS_SOC_DDR, 4754 (BSL_META_U(unit, 4755 "(WL=%d) VDL_CALIB_STATUS : CALIB_BYTE_SEL = 0x%x \n"), 4756 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 4757 CALIB_BYTE_SEL))); 4758 LOG_INFO(BSL_LS_SOC_DDR, 4759 (BSL_META_U(unit, 4760 "(WL=%d) VDL_CALIB_STATUS : CALIB_BIT_OFFSET set if byte mode = 0x%x \n"), 4761 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 4762 CALIB_BIT_OFFSET))); 4763 LOG_INFO(BSL_LS_SOC_DDR, 4764 (BSL_META_U(unit, 4765 "(WL=%d) NOTE: For single step calibration total result, please see below \n"), 4766 wl)); 4767 READ_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(unit, ci, &data); 4768 LOG_INFO(BSL_LS_SOC_DDR, 4769 (BSL_META_U(unit, 4770 "(WL=%d) data = 0x%x \n"), 4771 wl, data)); 4772 LOG_INFO(BSL_LS_SOC_DDR, 4773 (BSL_META_U(unit, 4774 "(WL=%d) VDL_DQ_CALIB_STATUS : DQ_CALIB_LOCK = 0x%x \n"), 4775 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 4776 DQ_CALIB_LOCK))); 4777 LOG_INFO(BSL_LS_SOC_DDR, 4778 (BSL_META_U(unit, 4779 "(WL=%d) VDL_DQ_CALIB_STATUS : DQS_CALIB_LOCK = 0x%x \n"), 4780 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 4781 DQS_CALIB_LOCK))); 4782 LOG_INFO(BSL_LS_SOC_DDR, 4783 (BSL_META_U(unit, 4784 "(WL=%d) VDL_DQ_CALIB_STATUS : DQS_CALIB_MODE DQS(1=pair) = 0x%x \n"), 4785 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 4786 DQS_CALIB_MODE))); 4787 LOG_INFO(BSL_LS_SOC_DDR, 4788 (BSL_META_U(unit, 4789 "(WL=%d) VDL_DQ_CALIB_STATUS : DQS_CALIB_CLOCKS DQS(0=half bit) = 0x%x \n"), 4790 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 4791 DQS_CALIB_CLOCKS))); 4792 LOG_INFO(BSL_LS_SOC_DDR, 4793 (BSL_META_U(unit, 4794 "(WL=%d) VDL_DQ_CALIB_STATUS : DQ_CALIB_TOTAL DQ (steps) = 0x%x \n"), 4795 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 4796 DQ_CALIB_TOTAL) >> 4)); 4797 LOG_INFO(BSL_LS_SOC_DDR, 4798 (BSL_META_U(unit, 4799 "(WL=%d) VDL_DQ_CALIB_STATUS : DQS_CALIB_TOTAL DQS (steps) = 0x%x \n"), 4800 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 4801 DQS_CALIB_TOTAL) >> 4)); 4802 READ_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(unit, ci, &data); 4803 LOG_INFO(BSL_LS_SOC_DDR, 4804 (BSL_META_U(unit, 4805 "(WL=%d) data = 0x%x \n"), 4806 wl, data)); 4807 LOG_INFO(BSL_LS_SOC_DDR, 4808 (BSL_META_U(unit, 4809 "(WL=%d) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_LOCK = 0x%x \n"), 4810 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4811 VDL_WR_CHAN_CALIB_STATUS, WR_CHAN_CALIB_LOCK))); 4812 LOG_INFO(BSL_LS_SOC_DDR, 4813 (BSL_META_U(unit, 4814 "(WL=%d) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_BYTE_SEL (1=byte) = 0x%x \n"), 4815 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4816 VDL_WR_CHAN_CALIB_STATUS, 4817 WR_CHAN_CALIB_BYTE_SEL))); 4818 LOG_INFO(BSL_LS_SOC_DDR, 4819 (BSL_META_U(unit, 4820 "(WL=%d) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_CLOCKS (0=1/2bit) = 0x%x \n"), 4821 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4822 VDL_WR_CHAN_CALIB_STATUS, WR_CHAN_CALIB_CLOCKS))); 4823 LOG_INFO(BSL_LS_SOC_DDR, 4824 (BSL_META_U(unit, 4825 "(WL=%d) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_TOTAL (steps) = 0x%x \n"), 4826 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4827 VDL_WR_CHAN_CALIB_STATUS, 4828 WR_CHAN_CALIB_TOTAL) >> 4)); 4829 LOG_INFO(BSL_LS_SOC_DDR, 4830 (BSL_META_U(unit, 4831 "(WL=%d) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_BIT_OFFSET (in byte mode, setting for bit vdl)= 0x%x \n"), 4832 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4833 VDL_WR_CHAN_CALIB_STATUS, 4834 WR_CHAN_CALIB_BIT_OFFSET))); 4835 READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(unit, ci, &data); 4836 LOG_INFO(BSL_LS_SOC_DDR, 4837 (BSL_META_U(unit, 4838 "(WL=%d) data = 0x%x \n"), 4839 wl, data)); 4840 LOG_INFO(BSL_LS_SOC_DDR, 4841 (BSL_META_U(unit, 4842 "(WL=%d) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_LOCK = 0x%x \n"), 4843 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4844 VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_LOCK))); 4845 LOG_INFO(BSL_LS_SOC_DDR, 4846 (BSL_META_U(unit, 4847 "(WL=%d) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_BYTE_SEL (1=byte) = 0x%x \n"), 4848 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4849 VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BYTE_SEL))); 4850 LOG_INFO(BSL_LS_SOC_DDR, 4851 (BSL_META_U(unit, 4852 "(WL=%d) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_CLOCKS (0=1/2bit) = 0x%x \n"), 4853 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4854 VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_CLOCKS))); 4855 LOG_INFO(BSL_LS_SOC_DDR, 4856 (BSL_META_U(unit, 4857 "(WL=%d) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_TOTAL (steps) = 0x%x \n"), 4858 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4859 VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_TOTAL) >> 4)); 4860 LOG_INFO(BSL_LS_SOC_DDR, 4861 (BSL_META_U(unit, 4862 "(WL=%d) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_BIT_OFFSET (in byte mode, setting for bit vdl)= 0x%x \n"), 4863 wl, DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 4864 VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_BIT_OFFSET))); 4865 4866 /* Calculate VDL calibration steps */ 4867 /* calib steps */ 4868 WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, ci, 0x0); 4869 WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, ci, 0x200); /* calib_auto = 1 */ 4870 data = 0; 4871 timeout_cnt = 0; 4872 calib_steps = 1; 4873 do { 4874 sal_usleep(10); 4875 READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit, ci, &data); 4876 if (DDR40_GET_FIELD 4877 (data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_IDLE)) { 4878 calib_steps = 4879 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 4880 CALIB_TOTAL); 4881 if (DDR40_GET_FIELD 4882 (data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK)) 4883 LOG_INFO(BSL_LS_SOC_DDR, 4884 (BSL_META_U(unit, 4885 "(WL=%d) VDL_CALIB_STATUS : NOT CALIB_LOCK \n"), 4886 wl)); 4887 break; /* Check to and wait till we find idle state */ 4888 } /* if ( DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_LOCK ) ) */ 4889 if (timeout_cnt > 20000) { 4890 LOG_CLI((BSL_META_U(unit, 4891 "REWRITE Memory Register Mode failed\n"))); 4892 break; 4893 } 4894 timeout_cnt += 1; 4895 } while (TRUE); 4896 READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit, ci, &data); 4897 clock_period1000 = 1000000000 / SOC_DDR3_CLOCK_MHZ(unit); 4898 clock_period = clock_period1000 / 1000; 4899 4900 LOG_INFO(BSL_LS_SOC_DDR, 4901 (BSL_META_U(unit, 4902 "-----------------------------------------\n"))); 4903 LOG_INFO(BSL_LS_SOC_DDR, 4904 (BSL_META_U(unit, 4905 "--- Single STEP Calibration ---\n"))); 4906 LOG_INFO(BSL_LS_SOC_DDR, 4907 (BSL_META_U(unit, 4908 "-----------------------------------------\n"))); 4909 LOG_INFO(BSL_LS_SOC_DDR, 4910 (BSL_META_U(unit, 4911 "(WL=%d) VDL_CALIB_STATUS : CALIB_LOCK = %0d \n"), wl, 4912 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 4913 CALIB_LOCK))); 4914 LOG_INFO(BSL_LS_SOC_DDR, 4915 (BSL_META_U(unit, 4916 "(WL=%d) VDL_CALIB_STATUS : CALIB_IDLE = %0d \n"), wl, 4917 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 4918 CALIB_IDLE))); 4919 LOG_INFO(BSL_LS_SOC_DDR, 4920 (BSL_META_U(unit, 4921 "(WL=%d) VDL_CALIB_STATUS : 360' CALIB_TOTAL = %4d.000 (steps)\n"), wl, 4922 calib_steps)); 4923 LOG_INFO(BSL_LS_SOC_DDR, 4924 (BSL_META_U(unit, 4925 "(WL=%d) VDL_CALIB_STATUS : 90' CALIB TOTAL = %4d.%03d (steps)\n"), wl, 4926 (calib_steps >> 2), (((calib_steps * 1000) - (((calib_steps >> 2) << 2) * 1000)) >> 2))); 4927 LOG_INFO(BSL_LS_SOC_DDR, 4928 (BSL_META_U(unit, 4929 "(WL=%d) VDL_CALIB_STATUS : 360' steps time = %4d.%03d (ps) \n"), 4930 wl, clock_period, clock_period1000 - (clock_period * 1000))); 4931 LOG_INFO(BSL_LS_SOC_DDR, 4932 (BSL_META_U(unit, 4933 "(WL=%d) VDL_CALIB_STATUS : 90' steps time = %4d.%03d (ps) \n"), 4934 wl, (clock_period >> 2), ((clock_period1000 - (((clock_period >> 2) << 2) * 1000)) >> 2))); 4935 LOG_INFO(BSL_LS_SOC_DDR, 4936 (BSL_META_U(unit, 4937 "(WL=%d) VDL_CALIB_STATUS : Single step time = %4d.%03d (ps) \n"), 4938 wl, (clock_period / calib_steps), ((clock_period1000 - (((clock_period / calib_steps) * calib_steps) * 1000)) / calib_steps))); 4939 4940 /* Do one dummy memory read to fix RTL bug on RD_FIFO write pointer coming out of reset bug */ 4941 data = _test_mem_read(unit, (ci + wl), 0, NULL); 4942 4943 return SOC_E_NONE; 4944 } /* _soc_ddr_shmoo_prepare_for_shmoo */ 4945 4946 4947 /* RESET MEMORY and Rewrite MRS register */ 4948 int _soc_katana_mem_reset_and_init_after_shmoo_addr(int unit, int ci) 4949 { 4950 int i, ciCS, ciCM, ciC, num_lane, timeout_cnt; 4951 uint32 data, rval; 4952 4953 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &data)); 4954 soc_reg_field_set(unit, CI_PHY_CONTROLr, &data, CKEf, 0); 4955 soc_reg_field_set(unit, CI_PHY_CONTROLr, &data, RST_Nf, 0); 4956 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit, ci, data)); 4957 sal_usleep(2000); 4958 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &data)); 4959 soc_reg_field_set(unit, CI_PHY_CONTROLr, &data, CKEf, 0); 4960 soc_reg_field_set(unit, CI_PHY_CONTROLr, &data, RST_Nf, 3); 4961 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit, ci, data)); 4962 sal_usleep(2000); 4963 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &data)); 4964 soc_reg_field_set(unit, CI_PHY_CONTROLr, &data, CKEf, 3); 4965 soc_reg_field_set(unit, CI_PHY_CONTROLr, &data, RST_Nf, 3); 4966 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit, ci, data)); 4967 sal_usleep(2000); 4968 4969 if(dram0_clamshell_enable || dram1_clamshell_enable) { 4970 4971 ciC = ci & 0xFFFFFFFE; 4972 4973 if(dram0_clamshell_enable) { 4974 ciCM = ciC; /* Only Even CIs Mirrored */ 4975 ciCS = ciC + 1; /* Only Odd CIs Straight */ 4976 } else { 4977 ciCM = ciC + 1; /* Only Odd CIs Mirrored */ 4978 ciCS = ciC; /* Only Even CIs Straight */ 4979 } 4980 4981 rval = 0; 4982 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DONEf, 1 ); 4983 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, REQf, 1 ); 4984 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_CMDf, 0x0 ); 4985 4986 /* MR2 */ 4987 if(_check_dram(ciCS)) { 4988 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 4989 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x2 ); 4990 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCS, rval) ); 4991 } 4992 if(_check_dram(ciCM)) { 4993 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 4994 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x1 ); 4995 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCM, rval) ); 4996 } 4997 4998 /* MR3 */ 4999 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x3 ); 5000 if(_check_dram(ciCS)) { 5001 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 5002 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCS, rval) ); 5003 } 5004 if(_check_dram(ciCM)) { 5005 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 5006 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCM, rval) ); 5007 } 5008 5009 /* MR1 */ 5010 if(_check_dram(ciCS)) { 5011 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 5012 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x1 ); 5013 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCS, rval) ); 5014 } 5015 if(_check_dram(ciCM)) { 5016 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 5017 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x2 ); 5018 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCM, rval) ); 5019 } 5020 5021 /* MR0 */ 5022 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x0 ); 5023 if(_check_dram(ciCS)) { 5024 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 5025 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCS, rval) ); 5026 } 5027 if(_check_dram(ciCM)) { 5028 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 5029 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCM, rval) ); 5030 } 5031 5032 /* ZQ Cal Long */ 5033 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_CMDf, 0x3 ); 5034 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x3 ); 5035 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x3 ); 5036 if(_check_dram(ciCS)) { 5037 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCS, rval) ); 5038 } 5039 if(_check_dram(ciCM)) { 5040 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ciCM, rval) ); 5041 } 5042 5043 } else { 5044 5045 num_lane = 2; 5046 5047 for (i = 0; i < num_lane; i++) { 5048 if(!_check_dram(ci+i)) { 5049 continue; 5050 } 5051 SOC_IF_ERROR_RETURN(READ_CI_DDR_AUTOINITr(unit, ci + i, &data)); 5052 soc_reg_field_set(unit, CI_DDR_AUTOINITr, &data, DONEf, 1); 5053 soc_reg_field_set(unit, CI_DDR_AUTOINITr, &data, STARTf, 0); 5054 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_AUTOINITr(unit, ci + i, data)); 5055 soc_reg_field_set(unit, CI_DDR_AUTOINITr, &data, STARTf, 1); 5056 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_AUTOINITr(unit, ci + i, data)); 5057 } 5058 for (i = 0; i < num_lane; i++) { 5059 if(!_check_dram(ci+i)) { 5060 continue; 5061 } 5062 timeout_cnt = 0; 5063 do { 5064 sal_usleep(10); 5065 SOC_IF_ERROR_RETURN(READ_CI_DDR_AUTOINITr(unit, ci + i, &data)); 5066 if (soc_reg_field_get(unit, CI_DDR_AUTOINITr, data, DONEf)) { 5067 break; 5068 } 5069 if (timeout_cnt > 20000) { 5070 LOG_CLI((BSL_META_U(unit, 5071 "REWRITE Memory Register Mode failed (DRAM %2d)\n"), ci+i)); 5072 break; 5073 } 5074 timeout_cnt += 1; 5075 } while (TRUE); 5076 } 5077 5078 } 5079 5080 sal_usleep(2000); 5081 5082 return SOC_E_NONE; 5083 } 5084 5085 #ifdef BCM_PETRA_SUPPORT 5086 int _soc_arad_mem_reset_and_init_after_shmoo_addr(int unit, int ci) 5087 { 5088 int timeout_cnt; 5089 uint32 rval; 5090 #ifdef BCM_PETRA_SUPPORT 5091 uint8 is_valid[SOC_DPP_DEFS_MAX(HW_DRAM_INTERFACES_MAX)] = {0}; 5092 5093 is_valid[ci>>1] = 1; 5094 5095 arad_mgmt_dram_init_drc_soft_init(unit, is_valid, 1); 5096 sal_usleep(2000); 5097 arad_mgmt_dram_init_drc_soft_init(unit, is_valid, 0); 5098 #endif 5099 5100 timeout_cnt = 0; 5101 do { 5102 sal_usleep(10); 5103 SOC_IF_ERROR_RETURN(DRC_REG_READ(unit, ci>>1, DRC_DRAM_INIT_FINISHEDr, &rval)); 5104 if (soc_reg_field_get(unit, DRCA_DRAM_INIT_FINISHEDr, rval, DRAM_INIT_FINISHEDf)) { 5105 break; 5106 } 5107 if (timeout_cnt > 20000) { 5108 LOG_ERROR(BSL_LS_SOC_COMMON, 5109 (BSL_META_U(unit, 5110 "CI%d: Timed out DRAM re-initialization\n"), ci)); 5111 return SOC_E_TIMEOUT; 5112 } 5113 timeout_cnt += 1; 5114 } while (TRUE); 5115 5116 return SOC_E_NONE; 5117 } 5118 #endif 5119 5120 int 5121 _soc_mem_reset_and_init_after_shmoo_addr(int unit, int ci) 5122 { 5123 if(SOC_IS_KATANAX(unit)) { 5124 return _soc_katana_mem_reset_and_init_after_shmoo_addr(unit, ci); 5125 #ifdef BCM_PETRA_SUPPORT 5126 } else if(SOC_IS_ARAD(unit)) { 5127 return _soc_arad_mem_reset_and_init_after_shmoo_addr(unit, ci); 5128 #endif 5129 } else { 5130 return SOC_E_INTERNAL; /* Unsupported configuration */ 5131 } 5132 } 5133 5134 /* Initialize VDL 90' result from VDL Calibration */ 5135 int _shmoo_init_vdl_result(int unit, int ci, int wl, int self_test, uint32 * result) 5136 { 5137 int byte, bit; 5138 uint32 data_expected[NUM_DATA]; 5139 uint32 data, setting, setting_steps, setting_byte_sel; 5140 int32 steps_calib_total; 5141 int calib_steps; 5142 5143 _fill_in_data(data_expected); 5144 if (self_test == 0) { 5145 _test_mem_write(unit, (ci + wl), 0, data_expected); 5146 } 5147 5148 /* RD_DATA_DELAY */ 5149 data = 1; /* 0 is undefined for RD_DATA_DELAY */ 5150 if(wl == 0) { 5151 WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, data); 5152 5153 } else { 5154 WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, data); 5155 } 5156 5157 /* RD_EN */ 5158 READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(unit, ci, &data); 5159 setting_byte_sel = 5160 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, 5161 RD_EN_CALIB_BYTE_SEL); 5162 setting_steps = 5163 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_RD_EN_CALIB_STATUS, 5164 RD_EN_CALIB_TOTAL) >> 4; 5165 if(setting_byte_sel) { 5166 setting = (setting_steps * 3) >> 1; 5167 } else { 5168 setting = setting_steps >> 1; 5169 } 5170 setting_byte_sel = 1; 5171 if (wl == 0) { 5172 setting += SHMOO_CI02_WL0_OFFSET_RD_EN; 5173 } else { 5174 setting += SHMOO_CI0_WL1_OFFSET_RD_EN; 5175 } 5176 if (setting & 0x80000000) { 5177 setting = 0; 5178 } else if (setting > 63) { 5179 setting = 63; 5180 } 5181 DDR40_SET_FIELD(setting, DDR40_PHY_CONTROL_REGS, VDL_OVRIDE_BYTE_CTL, 5182 BYTE_SEL, setting_byte_sel); 5183 data = SET_OVR_STEP(setting); 5184 if (wl == 0) { 5185 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5186 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 5187 data); 5188 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 5189 data); 5190 } else { 5191 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5192 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 5193 data); 5194 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 5195 data); 5196 } 5197 5198 /* RD_DQ */ 5199 READ_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(unit, ci, &data); 5200 steps_calib_total = 5201 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 5202 DQ_CALIB_TOTAL) >> 4; 5203 setting = steps_calib_total; 5204 if (wl == 0) { 5205 setting += SHMOO_CI02_WL0_OFFSET_RD_DQ; 5206 } else { 5207 setting += SHMOO_CI0_WL1_OFFSET_RD_DQ; 5208 } 5209 if (setting & 0x80000000) { 5210 setting = 0; 5211 } else if (setting > 63) { 5212 setting = 63; 5213 } 5214 data = SET_OVR_STEP(setting); 5215 for (byte = 0; byte < 2; byte++) { 5216 for (bit = 0; bit < 8; bit++) { 5217 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(wl, byte, 5218 bit, unit, 5219 ci, data); 5220 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(wl, byte, 5221 bit, unit, 5222 ci, data); 5223 } 5224 } 5225 5226 /* RD_DQS */ 5227 READ_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(unit, ci, &data); 5228 setting_byte_sel = 5229 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 5230 DQS_CALIB_MODE); 5231 setting_steps = 5232 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 5233 DQS_CALIB_TOTAL) >> 4; 5234 calib_steps = 5235 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 5236 CALIB_TOTAL); 5237 LOG_INFO(BSL_LS_SOC_DDR, 5238 (BSL_META_U(unit, 5239 "calib_steps: %d\n"), 5240 calib_steps)); 5241 setting = (setting_steps * (1 + setting_byte_sel)); 5242 if (wl == 0) { 5243 setting += SHMOO_CI02_WL0_OFFSET_RD_DQS; 5244 } else { 5245 setting += SHMOO_CI0_WL1_OFFSET_RD_DQS; 5246 } 5247 if (setting & 0x80000000) { 5248 setting = 0; 5249 } else if (setting > 63) { 5250 setting = 63; 5251 } 5252 data = SET_OVR_STEP(setting); 5253 if (wl == 0) { 5254 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 5255 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 5256 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 5257 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 5258 } else { 5259 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 5260 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 5261 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 5262 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 5263 } 5264 5265 /* WR_DQ */ 5266 /* bit mode */ 5267 READ_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(unit, ci, &data); 5268 setting_byte_sel = 5269 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_WR_CHAN_CALIB_STATUS, 5270 WR_CHAN_CALIB_BYTE_SEL); 5271 setting_steps = 5272 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_WR_CHAN_CALIB_STATUS, 5273 WR_CHAN_CALIB_TOTAL) >> 4; 5274 setting = setting_steps; 5275 if (SOC_IS_ARAD(unit)) { 5276 /* Same offset applies to both WLs */ 5277 setting += SOC_DDR3_OFFSET_WR_DQ_CI02_WL0(unit); 5278 } else { 5279 if (SOC_IS_KATANAX(unit) && (dram0_clamshell_enable || dram1_clamshell_enable)) { 5280 setting += SHMOO_CI02_WL0_OFFSET_WR_DQ; 5281 } else { 5282 if (wl == 0) { 5283 setting += SHMOO_CI02_WL0_OFFSET_WR_DQ; 5284 } else { 5285 setting += SHMOO_CI0_WL1_OFFSET_WR_DQ; 5286 } 5287 } 5288 } 5289 if (setting & 0x80000000) { 5290 setting = 0; 5291 } else if (setting > 63) { 5292 setting = 63; 5293 } 5294 DDR40_SET_FIELD(setting, DDR40_PHY_CONTROL_REGS, VDL_OVRIDE_BYTE_CTL, 5295 BYTE_SEL, setting_byte_sel); 5296 data = SET_OVR_STEP(setting); 5297 for (byte = 0; byte < 2; byte++) { 5298 for (bit = 0; bit < 8; bit++) { 5299 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_Wr(wl, byte, bit, 5300 unit, ci, 5301 data); 5302 } 5303 } 5304 /* byte */ 5305 data = SET_OVR_STEP(0); 5306 if (wl == 0) { 5307 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_Wr(unit, ci, data); 5308 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_Wr(unit, ci, data); 5309 } else { 5310 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_Wr(unit, ci, data); 5311 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_Wr(unit, ci, data); 5312 } 5313 5314 /* ADDR */ 5315 if ( wl == 0 ) { 5316 /* Hardware adjust ADDR 90' prior VDL 5317 * Because we cannot trust ADDR Calibration result as it reports 0 steps 5318 * We then will use WR_DQ 90' calibration result to adjust ADDR (by 90') to become 180' for the address 5319 * Excluded below and use WR_DQ instead 5320 * setting_byte_sel = DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_BYTE_SEL ) ; 5321 * setting_steps = DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, CALIB_TOTAL )>>4 ; 5322 * setting = (setting_steps*(1+setting_byte_sel)); 5323 */ 5324 READ_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(unit, ci, &data); 5325 setting_byte_sel = 5326 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 5327 VDL_WR_CHAN_CALIB_STATUS, WR_CHAN_CALIB_BYTE_SEL); 5328 setting_steps = 5329 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 5330 VDL_WR_CHAN_CALIB_STATUS, 5331 WR_CHAN_CALIB_TOTAL) >> 4; 5332 setting = setting_steps; 5333 DDR40_SET_FIELD(setting, DDR40_PHY_CONTROL_REGS, VDL_OVRIDE_BYTE_CTL, 5334 BYTE_SEL, setting_byte_sel); 5335 5336 data = SET_OVR_STEP(40); 5337 WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(unit, ci, data); 5338 } 5339 5340 /* Shmoo */ 5341 /* Do one dummy memory read to fix RTL bug on RD_FIFO write pointer coming out of reset bug */ 5342 data = _test_mem_read(unit, (ci + wl), 0, NULL); 5343 5344 /* Clear the FIFO error state */ 5345 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5346 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5347 return SOC_E_NONE; 5348 } 5349 5350 #if 0 /* Uncomment this when required */ 5351 int 5352 _shmoo_rd_en_rd_data_dly(int unit, int ci, int wl, int self_test, uint32 * result) 5353 { 5354 int i, j; 5355 uint32 data; 5356 uint32 data_expected[NUM_DATA]; 5357 int see_pass, see_fail, rd_en_pass, rd_en_fail, rd_en_size; 5358 uint32 dataB1p, dataB1n; 5359 5360 int rd_data_dly_pass_sum = 0; 5361 int rd_data_dly_pass_count = 0; 5362 int rd_data_dly_pass_avg = 0; 5363 int rd_en_window_found = 0; 5364 5365 _fill_in_data(data_expected); 5366 if (self_test == 0) { 5367 _test_mem_write(unit, (ci + wl), 0, data_expected); 5368 } 5369 5370 /* Clear the FIFO error state */ 5371 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5372 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5373 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 1); 5374 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 1); 5375 /* Clear any error status from previous run */ 5376 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, 1); 5377 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, 0); 5378 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, 1); 5379 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, 0); 5380 5381 /* RD_EN should be good by this point. We now find the best RD_DATA_DLY (for fast speed, we start from 3 and up) */ 5382 rd_en_size = 0; 5383 5384 if(wl == 0) { 5385 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &dataB1p); 5386 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, &dataB1n); 5387 dataB1p = 5388 DDR40_GET_FIELD(dataB1p, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_R_P, 5389 OVR_STEP); 5390 dataB1n = 5391 DDR40_GET_FIELD(dataB1n, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_R_N, 5392 OVR_STEP); 5393 } else { 5394 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &dataB1p); 5395 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, &dataB1n); 5396 dataB1p = 5397 DDR40_GET_FIELD(dataB1p, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_R_P, 5398 OVR_STEP); 5399 dataB1n = 5400 DDR40_GET_FIELD(dataB1n, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_R_N, 5401 OVR_STEP); 5402 } 5403 5404 /* Find Best RD_DATA_DLY */ 5405 for (j = 1; j < 8; ++j) { 5406 /* For every single RD_DATA_DLY, we shmoo RD_EN to find the largest window */ 5407 data = j; 5408 if (wl == 0) { 5409 WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, data); 5410 } else { 5411 WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, data); 5412 } 5413 see_pass = 0; 5414 see_fail = 0; 5415 rd_en_pass = 0; 5416 rd_en_fail = 0; 5417 rd_en_size = 0; 5418 rd_en_window_found = 0; 5419 for (i = 0; i < 64; ++i) { 5420 data = SET_OVR_STEP(i); 5421 5422 /* RD_EN */ 5423 if (wl == 0) { 5424 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5425 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, 5426 ci, 5427 data); 5428 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, 5429 ci, 5430 data); 5431 } else { 5432 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5433 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, 5434 ci, 5435 data); 5436 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, 5437 ci, 5438 data); 5439 } 5440 5441 /* Clear the FIFO error state */ 5442 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5443 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5444 sal_usleep(9); 5445 if (self_test==0) { 5446 result[i] = _test_mem_read(unit, (ci+wl), 0, data_expected); 5447 } else if (self_test==2) { 5448 result[i] = _test_rd_data_fifo_status(unit, ci, wl, 1); 5449 } else { 5450 result[i] = 5451 _test_func_self_test_1(unit, ci, wl, 1, 0); 5452 } 5453 5454 if (result[i] == 0) { /* PASS */ 5455 if (see_pass == 0) { 5456 rd_en_pass = i; 5457 see_pass = 1; 5458 } 5459 } else { 5460 if (see_pass==1 && see_fail==0) { 5461 rd_en_fail = i; 5462 see_fail = 1; 5463 } 5464 } 5465 5466 if(rd_en_window_found == 0) { 5467 if (see_pass==1 && see_fail==1) { 5468 rd_en_size = rd_en_fail - rd_en_pass; 5469 if(rd_en_size < 3) { 5470 see_pass = 0; 5471 see_fail = 0; 5472 } else { 5473 rd_data_dly_pass_sum += j; 5474 rd_data_dly_pass_count++; 5475 rd_en_window_found = 1; 5476 } 5477 } else if (see_pass==1 && i==63) { 5478 rd_en_size = i - rd_en_pass; 5479 if(rd_en_size < 3) { 5480 see_pass = 0; 5481 see_fail = 0; 5482 } else { 5483 rd_data_dly_pass_sum += j; 5484 rd_data_dly_pass_count++; 5485 rd_en_window_found = 1; 5486 } 5487 } 5488 } 5489 } 5490 } 5491 5492 if(rd_data_dly_pass_count != 0) { 5493 rd_data_dly_pass_avg = rd_data_dly_pass_sum / rd_data_dly_pass_count; 5494 } else { 5495 rd_data_dly_pass_avg = 1; 5496 } 5497 5498 /* set RD_EN and RD_DATA_DLY */ 5499 /* For every single RD_DATA_DLY, we shmoo RD_EN to find the largest window */ 5500 data = rd_data_dly_pass_avg; 5501 if (wl == 0) { 5502 WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, data); 5503 } else { 5504 WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, data); 5505 } 5506 5507 /* Do one dummy memory read to fix RTL bug on RD_FIFO write pointer coming out of reset bug */ 5508 data = _test_mem_read(unit, (ci + wl), 0, NULL); 5509 for (i = 0; i < 64; ++i) { 5510 data = SET_OVR_STEP(i); 5511 5512 /* RD_EN */ 5513 if (wl == 0) { 5514 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5515 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 5516 data); 5517 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 5518 data); 5519 } else { 5520 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5521 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 5522 data); 5523 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 5524 data); 5525 } 5526 5527 /* Clear the FIFO error state */ 5528 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5529 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5530 sal_usleep(9); 5531 if (self_test == 0) { 5532 result[i] = _test_mem_read(unit, (ci + wl), 0, data_expected); 5533 } else if (self_test==2) { 5534 result[i] = _test_rd_data_fifo_status(unit, ci, wl, 1); 5535 } else { 5536 result[i] = 5537 _test_func_self_test_1(unit, ci, wl, 1, 0); 5538 } 5539 } 5540 5541 return SOC_E_NONE; 5542 } 5543 #endif 5544 5545 int 5546 _shmoo_rd_data_dly(int unit, int ci, int wl, int self_test, uint32 * result) 5547 { 5548 int i, j; 5549 uint32 data; 5550 uint32 data_expected[NUM_DATA]; 5551 int see_pass, see_fail, rd_en_pass, rd_en_fail, rd_en_size; 5552 uint32 dataB1p, dataB1n; 5553 uint32 result0 = 0; 5554 5555 int rd_data_dly_pass_sum = 0; 5556 int rd_data_dly_pass_count = 0; 5557 int rd_data_dly_pass_avg = 0; 5558 int rd_en_window_found = 0; 5559 5560 _fill_in_data(data_expected); 5561 if (self_test == 0) { 5562 _test_mem_write(unit, (ci + wl), 0, data_expected); 5563 } 5564 5565 /* Clear the FIFO error state */ 5566 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5567 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5568 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 1); 5569 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 1); 5570 /* Clear any error status from previous run */ 5571 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, 1); 5572 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(unit, ci, 0); 5573 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, 1); 5574 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(unit, ci, 0); 5575 5576 /* RD_EN should be good by this point. We now find the best RD_DATA_DLY (for fast speed, we start from 3 and up) */ 5577 rd_en_size = 0; 5578 5579 if(wl == 0) { 5580 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &dataB1p); 5581 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, &dataB1n); 5582 dataB1p = 5583 DDR40_GET_FIELD(dataB1p, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_R_P, 5584 OVR_STEP); 5585 dataB1n = 5586 DDR40_GET_FIELD(dataB1n, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_R_N, 5587 OVR_STEP); 5588 } else { 5589 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &dataB1p); 5590 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, &dataB1n); 5591 dataB1p = 5592 DDR40_GET_FIELD(dataB1p, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_R_P, 5593 OVR_STEP); 5594 dataB1n = 5595 DDR40_GET_FIELD(dataB1n, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_R_N, 5596 OVR_STEP); 5597 } 5598 5599 /* Find Best RD_DATA_DLY */ 5600 for (j = 1; j < 8; ++j) { 5601 /* For every single RD_DATA_DLY, we shmoo RD_EN to find the largest window */ 5602 data = j; 5603 if (wl == 0) { 5604 WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, data); 5605 } else { 5606 WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, data); 5607 } 5608 see_pass = 0; 5609 see_fail = 0; 5610 rd_en_pass = 0; 5611 rd_en_fail = 0; 5612 rd_en_size = 0; 5613 rd_en_window_found = 0; 5614 LOG_INFO(BSL_LS_SOC_DDR, 5615 (BSL_META_U(unit, 5616 "RD_DATA_DLY Iter: %d\t"), 5617 j)); 5618 for (i = 0; i < 64; ++i) { 5619 data = SET_OVR_STEP(i); 5620 5621 /* RD_EN */ 5622 if (wl == 0) { 5623 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5624 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, 5625 ci, 5626 data); 5627 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, 5628 ci, 5629 data); 5630 } else { 5631 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5632 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, 5633 ci, 5634 data); 5635 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, 5636 ci, 5637 data); 5638 } 5639 5640 /* Clear the FIFO error state */ 5641 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5642 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5643 sal_usleep(9); 5644 if (self_test==0) { 5645 result[i] = _test_mem_read(unit, (ci+wl), 0, data_expected); 5646 } else if (self_test==2) { 5647 result[i] = _test_rd_data_fifo_status(unit, ci, wl, 1); 5648 } else { 5649 result[i] = 5650 _test_func_self_test_1(unit, ci, wl, 1, 3); 5651 } 5652 5653 if (result[i] == 0) { /* PASS */ 5654 LOG_INFO(BSL_LS_SOC_DDR, 5655 (BSL_META_U(unit, 5656 "+"))); 5657 if (see_pass == 0) { 5658 rd_en_pass = i; 5659 see_pass = 1; 5660 } 5661 } else { 5662 LOG_INFO(BSL_LS_SOC_DDR, 5663 (BSL_META_U(unit, 5664 "-"))); 5665 if (see_pass==1 && see_fail==0) { 5666 rd_en_fail = i; 5667 see_fail = 1; 5668 } 5669 } 5670 5671 if(rd_en_window_found == 0) { 5672 if (see_pass==1 && see_fail==1) { 5673 rd_en_size = rd_en_fail - rd_en_pass; 5674 if(rd_en_size < 3) { 5675 see_pass = 0; 5676 see_fail = 0; 5677 } else { 5678 rd_data_dly_pass_sum += j; 5679 rd_data_dly_pass_count++; 5680 rd_en_window_found = 1; 5681 } 5682 } else if (see_pass==1 && i==63) { 5683 rd_en_size = i - rd_en_pass; 5684 if(rd_en_size < 3) { 5685 see_pass = 0; 5686 see_fail = 0; 5687 } else { 5688 rd_data_dly_pass_sum += j; 5689 rd_data_dly_pass_count++; 5690 rd_en_window_found = 1; 5691 } 5692 } 5693 } 5694 } 5695 LOG_INFO(BSL_LS_SOC_DDR, 5696 (BSL_META_U(unit, 5697 "\n"))); 5698 if(rd_data_dly_pass_count != 0) { 5699 rd_data_dly_pass_avg = rd_data_dly_pass_sum + 1; 5700 break; 5701 } 5702 LOG_INFO(BSL_LS_SOC_DDR, 5703 (BSL_META_U(unit, 5704 "RD_DATA_DLY Iter: %d\tCount: %d\tSum: %2d\n"), 5705 j, rd_data_dly_pass_count, rd_data_dly_pass_sum)); 5706 } 5707 /* 5708 if(rd_data_dly_pass_count != 0) { 5709 rd_data_dly_pass_avg = rd_data_dly_pass_sum / rd_data_dly_pass_count; 5710 } else { 5711 rd_data_dly_pass_avg = 1; 5712 } */ 5713 5714 if(rd_data_dly_pass_count == 0) { 5715 rd_data_dly_pass_avg = 4; 5716 LOG_INFO(BSL_LS_SOC_DDR, 5717 (BSL_META_U(unit, 5718 "Did not find valid RD_DATA_DELAY. Forcing RD_DATA_DELAY = %d\n"), 5719 rd_data_dly_pass_avg)); 5720 } else { 5721 /* if(wl == 0) { 5722 rd_data_dly_pass_avg = 7; 5723 LOG_INFO(BSL_LS_SOC_DDR, 5724 (BSL_META_U(unit, 5725 "Found valid RD_DATA_DELAY but forcing RD_DATA_DELAY = %d\n"), 5726 rd_data_dly_pass_avg)); 5727 } */ 5728 /* if(wl == 1) { 5729 rd_data_dly_pass_avg = result0; 5730 LOG_INFO(BSL_LS_SOC_DDR, 5731 (BSL_META_U(unit, 5732 "Found valid RD_DATA_DELAY but copying WL0 RD_DATA_DELAY = %d\n"), 5733 rd_data_dly_pass_avg)); 5734 } */ 5735 } 5736 5737 /* set RD_EN and RD_DATA_DLY */ 5738 /* For every single RD_DATA_DLY, we shmoo RD_EN to find the largest window */ 5739 data = rd_data_dly_pass_avg; 5740 if (wl == 0) { 5741 LOG_INFO(BSL_LS_SOC_DDR, 5742 (BSL_META_U(unit, 5743 "Switching to RD_DATA_DELAY Step : %2d (WL = 0)\n"), 5744 data)); 5745 /* result0 = data; */ 5746 WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, data); 5747 } else { 5748 READ_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, &result0); 5749 result0 = 5750 DDR40_GET_FIELD(result0, DDR40_PHY_WORD_LANE_0, READ_DATA_DLY, RD_DATA_DLY); 5751 if(data > result0) { 5752 LOG_INFO(BSL_LS_SOC_DDR, 5753 (BSL_META_U(unit, 5754 "Equalizing to RD_DATA_DELAY Step : %2d (Both WLs)\n"), 5755 data)); 5756 WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, data); 5757 WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, data); 5758 } else { 5759 LOG_INFO(BSL_LS_SOC_DDR, 5760 (BSL_META_U(unit, 5761 "Copying WL0 RD_DATA_DELAY Step : %2d (WL = 1)\n"), 5762 result0)); 5763 WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, result0); 5764 } 5765 } 5766 5767 /* Clear the FIFO error state */ 5768 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5769 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5770 5771 return SOC_E_NONE; 5772 } 5773 5774 STATIC int _shmoo_rd_dq(int unit, int ci, int wl) 5775 { 5776 uint32 data = 0; 5777 uint32 init_rd_dqs_step; 5778 uint32 init_rd_en_step; 5779 uint32 new_rd_dqs_step; 5780 uint32 new_rd_en_step; 5781 uint32 new_rd_dq_step0 = 0xFFFFFFFF; 5782 uint32 new_rd_dq_step1 = 0xFFFFFFFF; 5783 uint32 result; 5784 int byte, bit; 5785 int i; 5786 int fail_count0 = 0; 5787 int pass_count0 = 0; 5788 int max_pass0 = 0; 5789 int first_fail0 = 63; 5790 int fail_count1 = 0; 5791 int pass_count1 = 0; 5792 int max_pass1 = 0; 5793 int first_fail1 = 63; 5794 uint32 new_rd_en_avg_step; 5795 5796 if(wl == 0) { 5797 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, &data); 5798 init_rd_dqs_step = 5799 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE0_R_P, 5800 OVR_STEP); 5801 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, &data); 5802 init_rd_en_step = 5803 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE0_BIT_RD_EN, 5804 OVR_STEP); 5805 new_rd_dqs_step = 0; 5806 if(init_rd_en_step > (init_rd_dqs_step >> RD_EN_DQS_CORROLATION)) { 5807 new_rd_en_step = init_rd_en_step - (init_rd_dqs_step >> RD_EN_DQS_CORROLATION); 5808 } else { 5809 new_rd_en_step = 0; 5810 } 5811 new_rd_en_avg_step = new_rd_en_step; 5812 data = SET_OVR_STEP(new_rd_dqs_step); 5813 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 5814 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 5815 data = SET_OVR_STEP(new_rd_en_step); 5816 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, data); 5817 LOG_INFO(BSL_LS_SOC_DDR, 5818 (BSL_META_U(unit, 5819 "Initial RD_DQS Setting (Byte 0): %2d\n"), 5820 init_rd_dqs_step)); 5821 LOG_INFO(BSL_LS_SOC_DDR, 5822 (BSL_META_U(unit, 5823 "Initial RD_EN Setting (Byte 0): %2d\n"), 5824 init_rd_en_step)); 5825 LOG_INFO(BSL_LS_SOC_DDR, 5826 (BSL_META_U(unit, 5827 "New RD_DQS Setting (Byte 0): %2d\n"), 5828 new_rd_dqs_step)); 5829 LOG_INFO(BSL_LS_SOC_DDR, 5830 (BSL_META_U(unit, 5831 "New RD_EN Setting (Byte 0): %2d\n"), 5832 new_rd_en_step)); 5833 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &data); 5834 init_rd_dqs_step = 5835 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_R_P, 5836 OVR_STEP); 5837 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, &data); 5838 init_rd_en_step = 5839 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_BIT_RD_EN, 5840 OVR_STEP); 5841 new_rd_dqs_step = 0; 5842 if(init_rd_en_step > (init_rd_dqs_step >> RD_EN_DQS_CORROLATION)) { 5843 new_rd_en_step = init_rd_en_step - (init_rd_dqs_step >> RD_EN_DQS_CORROLATION); 5844 } else { 5845 new_rd_en_step = 0; 5846 } 5847 new_rd_en_avg_step = (new_rd_en_avg_step + new_rd_en_step) >> 1; 5848 data = SET_OVR_STEP(new_rd_dqs_step); 5849 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 5850 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 5851 data = SET_OVR_STEP(new_rd_en_step); 5852 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, data); 5853 LOG_INFO(BSL_LS_SOC_DDR, 5854 (BSL_META_U(unit, 5855 "Initial RD_DQS Setting (Byte 1): %2d\n"), 5856 init_rd_dqs_step)); 5857 LOG_INFO(BSL_LS_SOC_DDR, 5858 (BSL_META_U(unit, 5859 "Initial RD_EN Setting (Byte 1): %2d\n"), 5860 init_rd_en_step)); 5861 LOG_INFO(BSL_LS_SOC_DDR, 5862 (BSL_META_U(unit, 5863 "New RD_DQS Setting (Byte 1): %2d\n"), 5864 new_rd_dqs_step)); 5865 LOG_INFO(BSL_LS_SOC_DDR, 5866 (BSL_META_U(unit, 5867 "New RD_EN Setting (Byte 1): %2d\n"), 5868 new_rd_en_step)); 5869 data = SET_OVR_STEP(new_rd_en_avg_step); 5870 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5871 } else { 5872 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, &data); 5873 init_rd_dqs_step = 5874 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE0_R_P, 5875 OVR_STEP); 5876 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, &data); 5877 init_rd_en_step = 5878 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE0_BIT_RD_EN, 5879 OVR_STEP); 5880 new_rd_dqs_step = 0; 5881 if(init_rd_en_step > (init_rd_dqs_step >> RD_EN_DQS_CORROLATION)) { 5882 new_rd_en_step = init_rd_en_step - (init_rd_dqs_step >> RD_EN_DQS_CORROLATION); 5883 } else { 5884 new_rd_en_step = 0; 5885 } 5886 new_rd_en_avg_step = new_rd_en_step; 5887 data = SET_OVR_STEP(new_rd_dqs_step); 5888 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 5889 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 5890 data = SET_OVR_STEP(new_rd_en_step); 5891 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, data); 5892 LOG_INFO(BSL_LS_SOC_DDR, 5893 (BSL_META_U(unit, 5894 "Initial RD_DQS Setting (Byte 0): %2d\n"), 5895 init_rd_dqs_step)); 5896 LOG_INFO(BSL_LS_SOC_DDR, 5897 (BSL_META_U(unit, 5898 "Initial RD_EN Setting (Byte 0): %2d\n"), 5899 init_rd_en_step)); 5900 LOG_INFO(BSL_LS_SOC_DDR, 5901 (BSL_META_U(unit, 5902 "New RD_DQS Setting (Byte 0): %2d\n"), 5903 new_rd_dqs_step)); 5904 LOG_INFO(BSL_LS_SOC_DDR, 5905 (BSL_META_U(unit, 5906 "New RD_EN Setting (Byte 0): %2d\n"), 5907 new_rd_en_step)); 5908 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &data); 5909 init_rd_dqs_step = 5910 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_R_P, 5911 OVR_STEP); 5912 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, &data); 5913 init_rd_en_step = 5914 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_BIT_RD_EN, 5915 OVR_STEP); 5916 new_rd_dqs_step = 0; 5917 if(init_rd_en_step > (init_rd_dqs_step >> RD_EN_DQS_CORROLATION)) { 5918 new_rd_en_step = init_rd_en_step - (init_rd_dqs_step >> RD_EN_DQS_CORROLATION); 5919 } else { 5920 new_rd_en_step = 0; 5921 } 5922 new_rd_en_avg_step = (new_rd_en_avg_step + new_rd_en_step) >> 1; 5923 data = SET_OVR_STEP(new_rd_dqs_step); 5924 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 5925 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 5926 data = SET_OVR_STEP(new_rd_en_step); 5927 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, data); 5928 LOG_INFO(BSL_LS_SOC_DDR, 5929 (BSL_META_U(unit, 5930 "Initial RD_DQS Setting (Byte 1): %2d\n"), 5931 init_rd_dqs_step)); 5932 LOG_INFO(BSL_LS_SOC_DDR, 5933 (BSL_META_U(unit, 5934 "Initial RD_EN Setting (Byte 1): %2d\n"), 5935 init_rd_en_step)); 5936 LOG_INFO(BSL_LS_SOC_DDR, 5937 (BSL_META_U(unit, 5938 "New RD_DQS Setting (Byte 1): %2d\n"), 5939 new_rd_dqs_step)); 5940 LOG_INFO(BSL_LS_SOC_DDR, 5941 (BSL_META_U(unit, 5942 "New RD_EN Setting (Byte 1): %2d\n"), 5943 new_rd_en_step)); 5944 data = SET_OVR_STEP(new_rd_en_avg_step); 5945 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 5946 } 5947 5948 for (i = 0; i < 64; ++i) { 5949 data = SET_OVR_STEP(i); 5950 5951 /* RD_DQ */ 5952 for (byte = 0; byte < 2; byte++) { 5953 for (bit = 0; bit < 8; bit++) { 5954 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(wl, 5955 byte, 5956 bit, 5957 unit, 5958 ci, 5959 data); 5960 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(wl, 5961 byte, 5962 bit, 5963 unit, 5964 ci, 5965 data); 5966 } 5967 } 5968 5969 /* Clear the FIFO error state */ 5970 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 5971 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 5972 sal_usleep(9); 5973 result = _test_func_self_test_1(unit, ci, wl, 1, 0); 5974 5975 if(new_rd_dq_step0 == 0xFFFFFFFF) { 5976 if((result & 0x00FF) != 0) { 5977 if(first_fail0 == 63) { 5978 first_fail0 = i; 5979 } 5980 if(max_pass0 < pass_count0) { 5981 max_pass0 = pass_count0; 5982 } 5983 pass_count0 = 0; 5984 fail_count0++; 5985 } else { 5986 fail_count0 = 0; 5987 pass_count0++; 5988 } 5989 if((max_pass0 >= 5) && (fail_count0 == 5)) { 5990 new_rd_dq_step0 = i; 5991 } 5992 } 5993 if(new_rd_dq_step1 == 0xFFFFFFFF) { 5994 if((result & 0xFF00) != 0) { 5995 if(first_fail1 == 63) { 5996 first_fail1 = i; 5997 } 5998 if(max_pass1 < pass_count1) { 5999 max_pass1 = pass_count1; 6000 } 6001 pass_count1 = 0; 6002 fail_count1++; 6003 } else { 6004 fail_count1 = 0; 6005 pass_count1++; 6006 } 6007 if((max_pass1 >= 5) && (fail_count1 == 5)) { 6008 new_rd_dq_step1 = i; 6009 } 6010 } 6011 if((new_rd_dq_step0 != 0xFFFFFFFF) && (new_rd_dq_step1 != 0xFFFFFFFF)) { 6012 break; 6013 } 6014 } 6015 if(i == 64) { 6016 if(new_rd_dq_step0 == 0xFFFFFFFF) { 6017 new_rd_dq_step0 = first_fail0; 6018 } 6019 if(new_rd_dq_step1 == 0xFFFFFFFF) { 6020 new_rd_dq_step1 = first_fail1; 6021 } 6022 } 6023 6024 LOG_INFO(BSL_LS_SOC_DDR, 6025 (BSL_META_U(unit, 6026 "Switching to RD_DQ Step (Byte 0) : %2d\n"), 6027 new_rd_dq_step0)); 6028 LOG_INFO(BSL_LS_SOC_DDR, 6029 (BSL_META_U(unit, 6030 "Switching to RD_DQ Step (Byte 1) : %2d\n"), 6031 new_rd_dq_step1)); 6032 6033 data = SET_OVR_STEP(new_rd_dq_step0); 6034 for (bit = 0; bit < 8; bit++) { 6035 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(wl, 0, 6036 bit, unit, 6037 ci, data); 6038 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(wl, 0, 6039 bit, unit, 6040 ci, data); 6041 } 6042 data = SET_OVR_STEP(new_rd_dq_step1); 6043 for (bit = 0; bit < 8; bit++) { 6044 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(wl, 1, 6045 bit, unit, 6046 ci, data); 6047 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(wl, 1, 6048 bit, unit, 6049 ci, data); 6050 } 6051 6052 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6053 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6054 return SOC_E_NONE; 6055 6056 } 6057 6058 STATIC int _shmoo_rd_en_rd_dq(int unit, int ci, int wl, int self_test, vref_word_shmoo *vwsPtr) 6059 { 6060 uint32 data; 6061 int byte, bit; 6062 int i, j; 6063 6064 uint32 data_expected[NUM_DATA]; 6065 6066 _fill_in_data(data_expected); 6067 if (self_test == 0) { 6068 _test_mem_write(unit, (ci + wl), 0, data_expected); 6069 } 6070 6071 for (i = 0; i < 64; ++i) { 6072 data = SET_OVR_STEP(i); 6073 6074 /* RD_DQ */ 6075 for (byte = 0; byte < 2; byte++) { 6076 for (bit = 0; bit < 8; bit++) { 6077 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(wl, 6078 byte, 6079 bit, 6080 unit, 6081 ci, 6082 data); 6083 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(wl, 6084 byte, 6085 bit, 6086 unit, 6087 ci, 6088 data); 6089 } 6090 } 6091 6092 for (j = 0; j < 64; ++j) { 6093 data = SET_OVR_STEP(j); 6094 6095 /* RD_EN */ 6096 if (wl == 0) { 6097 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 6098 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 6099 data); 6100 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 6101 data); 6102 } else { 6103 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 6104 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 6105 data); 6106 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 6107 data); 6108 } 6109 6110 /* Clear the FIFO error state */ 6111 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6112 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6113 sal_usleep(9); 6114 if (self_test == 0) { 6115 (*vwsPtr)[i].raw_result[j] = _test_mem_read(unit, (ci + wl), 0, data_expected); 6116 } else if (self_test==2) { 6117 (*vwsPtr)[i].raw_result[j] = _test_rd_data_fifo_status(unit, ci, wl, 1); 6118 } else { 6119 (*vwsPtr)[i].raw_result[j] = 6120 _test_func_self_test_1(unit, ci, wl, 1, 0); /* MPR = 4 */ 6121 } 6122 } 6123 } 6124 6125 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6126 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6127 return SOC_E_NONE; 6128 6129 } 6130 6131 #if 0 /* Uncomment this when required */ 6132 STATIC int _shmoo_rd_en(int unit, int ci, int wl, int self_test, uint32 * result) 6133 { 6134 uint32 data; 6135 int i; 6136 6137 uint32 data_expected[NUM_DATA]; 6138 6139 _fill_in_data(data_expected); 6140 if (self_test == 0) { 6141 _test_mem_write(unit, (ci + wl), 0, data_expected); 6142 } 6143 6144 for (i = 0; i < 64; ++i) { 6145 data = SET_OVR_STEP(i); 6146 6147 /* RD_EN */ 6148 if (wl == 0) { 6149 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 6150 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 6151 data); 6152 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 6153 data); 6154 } else { 6155 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 6156 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 6157 data); 6158 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 6159 data); 6160 } 6161 6162 /* Clear the FIFO error state */ 6163 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6164 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6165 sal_usleep(9); 6166 if (self_test == 0) { 6167 result[i] = _test_mem_read(unit, (ci + wl), 0, data_expected); 6168 } else if (self_test==2) { 6169 result[i] = _test_rd_data_fifo_status(unit, ci, wl, 1); 6170 } else { 6171 if(SOC_IS_KATANAX(unit)) { 6172 result[i] = 6173 _test_func_self_test_1(unit, ci, wl, 1, 3); 6174 } else { 6175 result[i] = 6176 _test_func_self_test_1(unit, ci, wl, 1, 3); /* MPR = 4 */ 6177 } 6178 } 6179 } 6180 6181 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6182 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6183 return SOC_E_NONE; 6184 6185 } 6186 #endif 6187 6188 STATIC int _shmoo_rd_dqs(int unit, int ci, int wl, int self_test, vref_word_shmoo *vwsPtr) 6189 { 6190 int32 i, vref; 6191 uint32 data; 6192 uint32 data_expected[NUM_DATA]; 6193 6194 uint32 init_rd_en_step0, init_rd_en_step1; 6195 uint32 new_rd_en_step, new_rd_en_byte_step; 6196 6197 _fill_in_data(data_expected); 6198 if (self_test == 0) { 6199 _test_mem_write(unit, (ci + wl), 0, data_expected); 6200 } 6201 6202 /* Do one dummy memory read to fix RTL bug on RD_FIFO write pointer coming out of reset bug */ 6203 data = _test_mem_read(unit, (ci + wl), 0, NULL); 6204 if(wl == 0) { 6205 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, &data); 6206 init_rd_en_step0 = 6207 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE0_BIT_RD_EN, 6208 OVR_STEP); 6209 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, &data); 6210 init_rd_en_step1 = 6211 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_BIT_RD_EN, 6212 OVR_STEP); 6213 } else { 6214 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, &data); 6215 init_rd_en_step0 = 6216 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE0_BIT_RD_EN, 6217 OVR_STEP); 6218 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, &data); 6219 init_rd_en_step1 = 6220 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_BIT_RD_EN, 6221 OVR_STEP); 6222 } 6223 for(vref = 16; vref < 49; vref++) { 6224 data = (vref << 6) | vref; 6225 MODIFY_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ci, data, 0xFFF); 6226 for (i = 0; i < 64; ++i) { 6227 6228 /* RD_DQS */ 6229 if (wl == 0) { 6230 data = SET_OVR_STEP(i); 6231 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 6232 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 6233 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 6234 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 6235 new_rd_en_step = init_rd_en_step0 + (i >> RD_EN_DQS_CORROLATION); 6236 (*vwsPtr)[vref].uncapped_rd_en_step[0] = new_rd_en_step; 6237 if(new_rd_en_step > 63) { 6238 new_rd_en_step = 63; 6239 } 6240 new_rd_en_byte_step = new_rd_en_step; 6241 data = SET_OVR_STEP(new_rd_en_step); 6242 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, data); 6243 new_rd_en_step = init_rd_en_step1 + (i >> RD_EN_DQS_CORROLATION); 6244 (*vwsPtr)[vref].uncapped_rd_en_step[1] = new_rd_en_step; 6245 if(new_rd_en_step > 63) { 6246 new_rd_en_step = 63; 6247 } 6248 new_rd_en_byte_step += new_rd_en_step; 6249 data = SET_OVR_STEP(new_rd_en_step); 6250 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, data); 6251 new_rd_en_byte_step = new_rd_en_byte_step >> 1; 6252 data = SET_OVR_STEP(new_rd_en_byte_step); 6253 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 6254 } else { 6255 data = SET_OVR_STEP(i); 6256 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 6257 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 6258 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 6259 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 6260 new_rd_en_step = init_rd_en_step0 + (i >> RD_EN_DQS_CORROLATION); 6261 (*vwsPtr)[vref].uncapped_rd_en_step[0] = new_rd_en_step; 6262 if(new_rd_en_step > 63) { 6263 new_rd_en_step = 63; 6264 } 6265 new_rd_en_byte_step = new_rd_en_step; 6266 data = SET_OVR_STEP(new_rd_en_step); 6267 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, data); 6268 new_rd_en_step = init_rd_en_step1 + (i >> RD_EN_DQS_CORROLATION); 6269 (*vwsPtr)[vref].uncapped_rd_en_step[1] = new_rd_en_step; 6270 if(new_rd_en_step > 63) { 6271 new_rd_en_step = 63; 6272 } 6273 new_rd_en_byte_step += new_rd_en_step; 6274 data = SET_OVR_STEP(new_rd_en_step); 6275 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, data); 6276 new_rd_en_byte_step = new_rd_en_byte_step >> 1; 6277 data = SET_OVR_STEP(new_rd_en_byte_step); 6278 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 6279 } 6280 6281 /* Clear the FIFO error state */ 6282 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6283 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6284 sal_usleep(9); 6285 if (self_test == 0) { 6286 (*vwsPtr)[vref].raw_result[i] = _test_mem_read(unit, (ci + wl), 0, data_expected); 6287 } else if (self_test == 2) { 6288 (*vwsPtr)[vref].raw_result[i] = _test_rd_data_fifo_status(unit, ci, wl, 1); 6289 } else { 6290 (*vwsPtr)[vref].raw_result[i] = 6291 _test_func_self_test_1(unit, ci, wl, 1, 0); 6292 } 6293 } 6294 } 6295 6296 /* Clear the FIFO error state */ 6297 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6298 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6299 return SOC_E_NONE; 6300 6301 } 6302 6303 /* Make a shmoo with the write dq vdl values */ 6304 STATIC int _shmoo_wr_dq(int unit, int ci, int wl, int self_test, uint32 * result) 6305 { 6306 int32 i; 6307 int32 byte, bit; 6308 uint32 data; 6309 uint32 data_expected[NUM_DATA]; 6310 6311 _fill_in_data(data_expected); 6312 if (self_test == 0) { 6313 _test_mem_write(unit, (ci + wl), 0, data_expected); 6314 } 6315 6316 /* Do one dummy memory read to fix RTL bug on RD_FIFO write pointer coming out of reset bug */ 6317 data = _test_mem_read(unit, (ci + wl), 0, NULL); 6318 for (i = 0; i < 64; ++i) { 6319 data = SET_OVR_STEP(i); 6320 6321 /* WR_DQ */ 6322 for (byte = 0; byte < 2; byte++) { 6323 for (bit = 0; bit < 8; bit++) { 6324 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_Wr(wl, byte, 6325 bit, unit, 6326 ci, data); 6327 } 6328 } 6329 6330 /* Clear the FIFO error state */ 6331 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6332 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6333 sal_usleep(9); 6334 if (self_test==0) { 6335 result[i] = _test_mem_read(unit, (ci+wl), 0, data_expected); 6336 } else if (self_test==2) { 6337 result[i] = _test_rd_data_fifo_status(unit, ci, wl, 1); 6338 } else { 6339 result[i] = 6340 _test_func_self_test_1(unit, ci, wl, 1, 1); 6341 } 6342 } 6343 6344 /* Clear the FIFO error state */ 6345 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6346 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6347 return SOC_E_NONE; 6348 } 6349 6350 /* Make a shmoo with the Address */ 6351 STATIC int _shmoo_addr(int unit, int ci, int wl, int self_test, uint32 * result) 6352 { 6353 uint32 data; 6354 uint32 setting, setting_idx; 6355 uint32 see_pass, see_fail_after_pass; 6356 uint32 start_vdl_val, pass_start, pass_end; 6357 uint32 use_byte_sel; 6358 6359 pass_start = 64; /* 64 means "have not found pass yet" */ 6360 pass_end = 64; /* 64 means "have not found pass yet" */ 6361 start_vdl_val = 0; 6362 6363 for(use_byte_sel = 0; use_byte_sel <= 1; use_byte_sel++) { 6364 /* Find pass_end of window */ 6365 see_pass = 0; 6366 see_fail_after_pass = 0; 6367 6368 /* Do one dummy memory read to fix RTL bug on RD_FIFO write pointer coming out of reset bug */ 6369 data = _test_mem_read(unit, (ci + wl), 0, NULL); 6370 for (setting = start_vdl_val; setting < 64; setting++) { 6371 data = SET_OVR_STEP(setting); 6372 DDR40_SET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_OVRIDE_BIT_CTL, 6373 BYTE_SEL, use_byte_sel); 6374 WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(unit, ci, data); 6375 data = SET_OVR_STEP(setting); 6376 DDR40_SET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_OVRIDE_BYTE_CTL, 6377 BYTE_SEL, use_byte_sel); 6378 WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTLr(unit, ci, data); 6379 if (setting == 0) { 6380 _soc_mem_reset_and_init_after_shmoo_addr(unit, ci); 6381 } 6382 6383 /* Clear the FIFO error state */ 6384 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6385 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6386 READ_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(unit, ci, &data); 6387 sal_usleep(9); 6388 setting_idx = (64 * use_byte_sel) + setting; 6389 if (self_test == 0) { 6390 result[setting_idx] = _test_mem_wr_rd(unit, (ci + wl), 0); 6391 } else { 6392 result[setting_idx] = 6393 _test_func_self_test_2(unit, ci, wl, 1); 6394 } 6395 if (see_pass == 0 && see_fail_after_pass == 0) { /* First time and so far see no pass */ 6396 if (result[setting_idx] == 0) { /* result_fail = 0 means PASSED */ 6397 see_pass = 1; 6398 pass_start = setting; 6399 } 6400 /* result_fail = 0 means PASSED */ 6401 } else { 6402 if (see_fail_after_pass == 0) { /* seeing FAIL for the first time */ 6403 if (result[setting_idx] > 0) { /* seeing FAIL for the first time */ 6404 see_fail_after_pass = 1; 6405 pass_end = setting - 1; 6406 } else { 6407 pass_end = setting; 6408 } 6409 } 6410 } 6411 if(result[setting_idx] > 0) { 6412 _soc_mem_reset_and_init_after_shmoo_addr(unit, ci); 6413 } 6414 } 6415 6416 setting_idx = 128 + (2 * use_byte_sel); 6417 result[setting_idx] = pass_start; 6418 setting_idx = 128 + (2 * use_byte_sel) + 1; 6419 result[setting_idx] = pass_end; 6420 } 6421 6422 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 6423 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 6424 6425 return SOC_E_NONE; 6426 } 6427 6428 /* Make a shmoo with the write data mask vdl values */ 6429 STATIC int _shmoo_wr_dm(int unit, int ci, int wl, uint32 * result) 6430 { 6431 LOG_CLI((BSL_META_U(unit, 6432 " ------------------------------------------------------\n"))); 6433 LOG_CLI((BSL_META_U(unit, 6434 " THIS SHMOO WR_DM feature is NOT SUPPORTED ........ \n"))); 6435 LOG_CLI((BSL_META_U(unit, 6436 " ------------------------------------------------------\n"))); 6437 return SOC_E_NONE; 6438 } 6439 6440 STATIC int _calib_all(int unit, int ci, uint32 *result, uint32 size, vref_word_shmoo *vwsPtr, int flag, uint32 *Xpos, int type) 6441 { 6442 int i, bit, vref, byte, bit_loc; 6443 int passStart; 6444 int failStart; 6445 int passLength; 6446 int maxPassStart; 6447 int maxPassLength; 6448 int maxMidPoint; 6449 int calib_steps; 6450 uint32 data; 6451 int ninty_deg_steps, rd_dq_steps, Tfix_steps; 6452 int mPLover; 6453 int vrefCap; 6454 6455 vrefCap = (type == SHMOO_RD_DQ) ? 49 : 1; 6456 vref = (type == SHMOO_RD_DQ) ? 16 : 0; 6457 6458 for(; vref < vrefCap; vref++) { 6459 for(bit = 0; bit < 16; bit++) { 6460 passStart = -1; 6461 failStart = -1; 6462 passLength = -1; 6463 maxPassStart = -2; 6464 maxPassLength = -2; 6465 maxMidPoint = -2; 6466 for(i = 0; i < size; i++) { 6467 if((result[i] & (0x1 << bit)) == 0) { 6468 (*vwsPtr)[vref].bs[bit].result[i] = '+'; 6469 if(passStart < 0) { 6470 passStart = i; 6471 passLength = 1; 6472 failStart = -1; 6473 } else { 6474 passLength++; 6475 } 6476 if(i == size - 1) { 6477 if(maxPassLength < passLength) { 6478 maxPassStart = passStart; 6479 maxPassLength = passLength; 6480 } 6481 } 6482 } else { 6483 (*vwsPtr)[vref].bs[bit].result[i] = '-'; 6484 if(failStart < 0) { 6485 failStart = i; 6486 if(maxPassLength < passLength) { 6487 maxPassStart = passStart; 6488 maxPassLength = passLength; 6489 } 6490 passStart = -1; 6491 passLength = -1; 6492 } 6493 } 6494 } 6495 (*vwsPtr)[vref].bs[bit].result[size] = 0; 6496 /* SINGLE CALIBRATION */ 6497 switch(type) { 6498 case SHMOO_ADDRC: 6499 WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, ci, 0x0); 6500 WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, ci, 0x200); 6501 data = 0; 6502 calib_steps = 0; 6503 READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(unit, ci, &data); 6504 calib_steps = 6505 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_CALIB_STATUS, 6506 CALIB_TOTAL); 6507 READ_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(unit, ci, &data); 6508 rd_dq_steps = 6509 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 6510 DQ_CALIB_TOTAL) >> 4; 6511 ninty_deg_steps = calib_steps >> 2; 6512 Tfix_steps = ninty_deg_steps - rd_dq_steps; 6513 if((maxPassStart + maxPassLength) > 64) { 6514 mPLover = maxPassStart + maxPassLength - 64; 6515 maxPassLength = (3 * (mPLover - 1)) + (Tfix_steps << 1) - maxPassStart + 1; 6516 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6517 if(maxMidPoint > 63) { 6518 maxMidPoint = 63; 6519 } 6520 } else { 6521 if((result[63] & (0x1 << bit)) == 0) { 6522 i = 21 - ((Tfix_steps << 1) / (3 * rd_dq_steps)); 6523 /* X = 63/3 - 2Tfix / 3Tstep */ 6524 if(i < 0) { 6525 i = 64; 6526 } else { 6527 i += 64; 6528 } 6529 for(; i < size; i++) { 6530 if((result[i] & (0x1 << bit)) != 0) { 6531 maxPassLength += i - 64; 6532 break; 6533 } 6534 } 6535 mPLover = maxPassStart + maxPassLength - 64; 6536 maxPassLength = (3 * (mPLover - 1)) + (Tfix_steps << 1) - maxPassStart + 1; 6537 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6538 if(maxMidPoint > 63) { 6539 maxMidPoint = 63; 6540 } 6541 } else { 6542 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6543 } 6544 } 6545 break; 6546 default: 6547 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6548 break; 6549 } 6550 if(type != SHMOO_WR_DQ) { 6551 if(maxMidPoint != -2) { 6552 (*vwsPtr)[vref].bs[bit].result[maxMidPoint] = 'X'; 6553 } 6554 (*vwsPtr)[vref].step[bit] = maxMidPoint; 6555 Xpos[bit] = maxMidPoint; 6556 } 6557 } 6558 if(type == SHMOO_WR_DQ) { 6559 for(byte = 0; byte < 2; byte++) { 6560 passStart = -1; 6561 failStart = -1; 6562 passLength = -1; 6563 maxPassStart = -2; 6564 maxPassLength = -20; 6565 maxMidPoint = -2; 6566 for(i = 0; i < size; i++) { 6567 if(((result[i] >> (byte << 3)) & 0xFF) == 0) { 6568 if(passStart < 0) { 6569 passStart = i; 6570 passLength = 1; 6571 failStart = -1; 6572 } else { 6573 passLength++; 6574 } 6575 if(i == size - 1) { 6576 if(maxPassLength < (passLength - 7)) { 6577 maxPassStart = passStart; 6578 maxPassLength = passLength; 6579 } 6580 } 6581 } else { 6582 if(failStart < 0) { 6583 failStart = i; 6584 if(maxPassLength < (passLength - 7)) { 6585 maxPassStart = passStart; 6586 maxPassLength = passLength; 6587 } 6588 passStart = -1; 6589 passLength = -1; 6590 } 6591 } 6592 } 6593 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6594 for(bit = 0; bit < 8; bit++) { 6595 bit_loc = (byte << 3) + bit; 6596 if((maxMidPoint >= 0) && (maxMidPoint <= 63)) { 6597 (*vwsPtr)[vref].bs[bit_loc].result[maxMidPoint] = 'X'; 6598 } 6599 (*vwsPtr)[vref].step[bit_loc] = maxMidPoint; 6600 Xpos[bit_loc] = maxMidPoint; 6601 } 6602 } 6603 } 6604 } 6605 6606 return SOC_E_NONE; 6607 } 6608 6609 STATIC int _calib_all2(int unit, int ci, int wl, uint32 size, vref_word_shmoo *vwsPtr, int flag, uint32 *Xpos, int type) 6610 { 6611 int i, bit, vref, byte, bit_loc; 6612 int passStart; 6613 int failStart; 6614 int passLength; 6615 int maxPassStart; 6616 int maxPassLength; 6617 int maxMidPoint; 6618 uint32 data; 6619 int vrefAvg; 6620 int overallmPL0 = -3; 6621 int overallmPL1 = -3; 6622 int overallmPLiter0 = -3; 6623 int overallmPLiter1 = -3; 6624 int maxMidPoint0 = -4; 6625 int maxMidPoint1 = -4; 6626 6627 for(vref = 16; vref < 49; vref++) { 6628 for(bit = 0; bit < 16; bit++) { 6629 passStart = -1; 6630 failStart = -1; 6631 passLength = -1; 6632 maxPassStart = -2; 6633 maxPassLength = -2; 6634 maxMidPoint = -2; 6635 for(i = 0; i < size; i++) { 6636 if(((*vwsPtr)[vref].raw_result[i] & (0x1 << bit)) == 0) { 6637 (*vwsPtr)[vref].bs[bit].result[i] = '+'; 6638 if(passStart < 0) { 6639 passStart = i; 6640 passLength = 1; 6641 failStart = -1; 6642 } else { 6643 passLength++; 6644 } 6645 if(i == size - 1) { 6646 if(maxPassLength < passLength) { 6647 maxPassStart = passStart; 6648 maxPassLength = passLength; 6649 } 6650 } 6651 } else { 6652 (*vwsPtr)[vref].bs[bit].result[i] = '-'; 6653 if(failStart < 0) { 6654 failStart = i; 6655 if(maxPassLength < passLength) { 6656 maxPassStart = passStart; 6657 maxPassLength = passLength; 6658 } 6659 passStart = -1; 6660 passLength = -1; 6661 } 6662 } 6663 } 6664 (*vwsPtr)[vref].bs[bit].result[size] = 0; 6665 /* SINGLE CALIBRATION */ 6666 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6667 (*vwsPtr)[vref].step[bit] = maxMidPoint; 6668 Xpos[bit] = maxMidPoint; 6669 } 6670 for(byte = 0; byte < 2; byte++) { 6671 passStart = -1; 6672 failStart = -1; 6673 passLength = -1; 6674 maxPassStart = -2; 6675 maxPassLength = -2; 6676 maxMidPoint = -2; 6677 for(i = 0; i < size; i++) { 6678 if((((*vwsPtr)[vref].raw_result[i] >> (byte << 3)) & 0xFF) == 0) { 6679 (*vwsPtr)[vref].bytes[byte].result[i] = '+'; 6680 if(passStart < 0) { 6681 passStart = i; 6682 passLength = 1; 6683 failStart = -1; 6684 } else { 6685 passLength++; 6686 } 6687 if(i == size - 1) { 6688 if(maxPassLength < passLength) { 6689 maxPassStart = passStart; 6690 maxPassLength = passLength; 6691 } 6692 } 6693 } else { 6694 (*vwsPtr)[vref].bytes[byte].result[i] = '-'; 6695 if(failStart < 0) { 6696 failStart = i; 6697 if(maxPassLength < passLength) { 6698 maxPassStart = passStart; 6699 maxPassLength = passLength; 6700 } 6701 passStart = -1; 6702 passLength = -1; 6703 } 6704 } 6705 } 6706 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6707 for(bit = 0; bit < 8; bit++) { 6708 bit_loc = (byte << 3) + bit; 6709 if((maxMidPoint >= 0) && (maxMidPoint <= 63)) { 6710 (*vwsPtr)[vref].bs[bit_loc].result[maxMidPoint] = 'X'; 6711 } 6712 (*vwsPtr)[vref].step[bit_loc] = maxMidPoint; 6713 } 6714 (*vwsPtr)[vref].bytes[byte].result[maxMidPoint] = 'X'; 6715 (*vwsPtr)[vref].bytes[byte].result[size] = 0; 6716 if(byte) { 6717 if(overallmPL1 < maxPassLength) { 6718 overallmPL1 = maxPassLength; 6719 overallmPLiter1 = vref; 6720 maxMidPoint1 = maxMidPoint; 6721 } 6722 } else { 6723 if(overallmPL0 < maxPassLength) { 6724 overallmPL0 = maxPassLength; 6725 overallmPLiter0 = vref; 6726 maxMidPoint0 = maxMidPoint; 6727 } 6728 } 6729 } 6730 } 6731 6732 for(bit = 0; bit < 8; bit++) { 6733 Xpos[bit] = maxMidPoint0; 6734 } 6735 for(bit = 8; bit < 16; bit++) { 6736 Xpos[bit] = maxMidPoint1; 6737 } 6738 6739 vrefAvg = (overallmPLiter0 + overallmPLiter1) >> 1; 6740 LOG_INFO(BSL_LS_SOC_DDR, 6741 (BSL_META_U(unit, 6742 "Switching to Vref Step : %2d\n"), 6743 vrefAvg)); 6744 data = (vrefAvg << 6) | vrefAvg; 6745 MODIFY_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ci, data, 0xFFF); 6746 6747 return SOC_E_NONE; 6748 } 6749 6750 STATIC int _calib_all3(int unit, int ci, int wl, uint32 size, vref_word_shmoo *vwsPtr, int flag, uint32 *Xpos, int type) 6751 { 6752 int i, bit, vref; 6753 int passStart; 6754 int failStart; 6755 int passLength; 6756 int maxPassStart; 6757 int maxPassLength; 6758 int maxMidPoint; 6759 uint32 data; 6760 int overallmPL0 = 0; 6761 int overallmPL1 = 0; 6762 int overallmPLiter0 = 0; 6763 int overallmPLiter1 = 0; 6764 int maxMidPoint0 = 0; 6765 int maxMidPoint1 = 0; 6766 int yMidPoint0 = 0; 6767 int yMidPoint1 = 0; 6768 6769 for(vref = 0; vref < 64; vref++) { 6770 for(bit = 0; bit < 16; bit++) { 6771 passStart = -1; 6772 failStart = -1; 6773 passLength = -1; 6774 maxPassStart = -2; 6775 maxPassLength = -2; 6776 maxMidPoint = -2; 6777 for(i = 0; i < size; i++) { 6778 if(((*vwsPtr)[vref].raw_result[i] & (0x1 << bit)) == 0) { 6779 (*vwsPtr)[vref].bs[bit].result[i] = '+'; 6780 if(passStart < 0) { 6781 passStart = i; 6782 passLength = 1; 6783 failStart = -1; 6784 } else { 6785 passLength++; 6786 } 6787 if(i == size - 1) { 6788 if(maxPassLength < passLength) { 6789 maxPassStart = passStart; 6790 maxPassLength = passLength; 6791 } 6792 } 6793 } else { 6794 (*vwsPtr)[vref].bs[bit].result[i] = '-'; 6795 if(failStart < 0) { 6796 failStart = i; 6797 if(maxPassLength < passLength) { 6798 maxPassStart = passStart; 6799 maxPassLength = passLength; 6800 } 6801 passStart = -1; 6802 passLength = -1; 6803 } 6804 } 6805 } 6806 (*vwsPtr)[vref].bs[bit].result[size] = 0; 6807 /* SINGLE CALIBRATION */ 6808 maxMidPoint = (maxPassStart + maxPassStart + maxPassLength) >> 1; 6809 if(maxMidPoint != -2) { 6810 (*vwsPtr)[vref].bs[bit].result[maxMidPoint] = 'X'; 6811 } 6812 (*vwsPtr)[vref].step[bit] = maxMidPoint; 6813 if(bit >> 3) { 6814 if(maxPassLength >= 5) { 6815 overallmPL1++; 6816 overallmPLiter1 += vref; 6817 } 6818 } else { 6819 if(maxPassLength >= 5) { 6820 overallmPL0++; 6821 overallmPLiter0 += vref; 6822 } 6823 } 6824 } 6825 } 6826 6827 if(overallmPL0 != 0) { 6828 yMidPoint0 = overallmPLiter0 / overallmPL0; 6829 for(bit = 0; bit < 8; bit++) { 6830 maxMidPoint0 += (*vwsPtr)[yMidPoint0].step[bit]; 6831 } 6832 maxMidPoint0 = maxMidPoint0 >> 3; 6833 } 6834 if(overallmPL1 != 0) { 6835 yMidPoint1 = overallmPLiter1 / overallmPL1; 6836 for(bit = 8; bit < 16; bit++) { 6837 maxMidPoint1 += (*vwsPtr)[yMidPoint1].step[bit]; 6838 } 6839 maxMidPoint1 = maxMidPoint1 >> 3; 6840 } 6841 6842 for(bit = 0; bit < 8; bit++) { 6843 Xpos[bit] = maxMidPoint0; 6844 } 6845 for(bit = 8; bit < 16; bit++) { 6846 Xpos[bit] = maxMidPoint1; 6847 } 6848 6849 /* RD_DQ */ 6850 data = SET_OVR_STEP(yMidPoint0); 6851 LOG_INFO(BSL_LS_SOC_DDR, 6852 (BSL_META_U(unit, 6853 "Switching to RD_DQ Step (Byte 0) : %2d\n"), 6854 yMidPoint0)); 6855 for (bit = 0; bit < 8; bit++) { 6856 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(wl, 6857 0, 6858 bit, 6859 unit, 6860 ci, 6861 data); 6862 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(wl, 6863 0, 6864 bit, 6865 unit, 6866 ci, 6867 data); 6868 } 6869 data = SET_OVR_STEP(yMidPoint1); 6870 LOG_INFO(BSL_LS_SOC_DDR, 6871 (BSL_META_U(unit, 6872 "Switching to RD_DQ Step (Byte 1) : %2d\n"), 6873 yMidPoint1)); 6874 for (bit = 0; bit < 8; bit++) { 6875 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(wl, 6876 1, 6877 bit, 6878 unit, 6879 ci, 6880 data); 6881 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(wl, 6882 1, 6883 bit, 6884 unit, 6885 ci, 6886 data); 6887 } 6888 6889 return SOC_E_NONE; 6890 } 6891 6892 /* Get Init steps */ 6893 int 6894 _soc_ddr40_shmoo_get_init_step(int unit, int ci, soc_ddr_shmoo_param_t *sp) 6895 { 6896 uint32 data = 0; 6897 uint32 calib_total; 6898 int byte, bit, en, n; 6899 6900 switch (sp->type) { 6901 case SHMOO_RD_EN: 6902 READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(unit, ci, &data); 6903 calib_total = 6904 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 6905 VDL_RD_EN_CALIB_STATUS, RD_EN_CALIB_TOTAL) >> 4; 6906 if (sp->wl == 0) { 6907 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, &data); /* Byte 0 */ 6908 sp->init_step[0] = 6909 (DDR40_GET_FIELD 6910 (data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE0_BIT_RD_EN, 6911 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 6912 VDL_OVRIDE_BYTE0_BIT_RD_EN, 6913 OVR_STEP) : calib_total; 6914 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, &data); /* Byte 1 */ 6915 sp->init_step[1] = 6916 (DDR40_GET_FIELD 6917 (data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_BIT_RD_EN, 6918 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 6919 VDL_OVRIDE_BYTE1_BIT_RD_EN, 6920 OVR_STEP) : calib_total; 6921 } else { 6922 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, &data); /* Byte 0 */ 6923 sp->init_step[0] = 6924 (DDR40_GET_FIELD 6925 (data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE0_BIT_RD_EN, 6926 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, 6927 VDL_OVRIDE_BYTE0_BIT_RD_EN, 6928 OVR_STEP) : calib_total; 6929 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, &data); /* Byte 1 */ 6930 sp->init_step[1] = 6931 (DDR40_GET_FIELD 6932 (data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_BIT_RD_EN, 6933 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, 6934 VDL_OVRIDE_BYTE1_BIT_RD_EN, 6935 OVR_STEP) : calib_total; 6936 } 6937 if (sp->wl == 0) { 6938 READ_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, &data); 6939 sp->init_step[2] = data; 6940 } else { 6941 READ_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, &data); 6942 sp->init_step[2] = data; 6943 } 6944 break; 6945 case SHMOO_RD_DQ: 6946 READ_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(unit, ci, &data); 6947 calib_total = 6948 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_DQ_CALIB_STATUS, 6949 DQ_CALIB_TOTAL) >> 4; 6950 n = 0; 6951 for (byte = 0; byte < 2; byte++) { 6952 for (bit = 0; bit < 8; bit++) { 6953 READ_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(sp->wl, byte, 6954 bit, 6955 unit, ci, 6956 &data); 6957 en = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 6958 VDL_OVRIDE_BYTE0_BIT0_R_P, OVR_EN); 6959 sp->init_step[n] = 6960 (en) ? GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 6961 VDL_OVRIDE_BYTE0_BIT0_R_P, 6962 OVR_STEP) : calib_total; 6963 n++; 6964 } 6965 } 6966 break; 6967 case SHMOO_WR_DQ: 6968 READ_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(unit, ci, &data); 6969 calib_total = 6970 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 6971 VDL_WR_CHAN_CALIB_STATUS, 6972 WR_CHAN_CALIB_TOTAL) >> 4; 6973 n = 0; 6974 for (byte = 0; byte < 2; byte++) { 6975 for (bit = 0; bit < 8; bit++) { 6976 READ_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_Wr(sp->wl, byte, 6977 bit, unit, 6978 ci, &data); 6979 en = DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 6980 VDL_OVRIDE_BYTE0_BIT0_W, OVR_EN); 6981 sp->init_step[n] = 6982 (en) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 6983 VDL_OVRIDE_BYTE0_BIT0_W, 6984 OVR_STEP) : calib_total; 6985 n++; 6986 } 6987 } 6988 break; 6989 case SHMOO_ADDRC: 6990 break; 6991 case SHMOO_WR_DM: 6992 READ_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(unit, ci, &data); 6993 calib_total = 6994 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, 6995 VDL_WR_CHAN_CALIB_STATUS, 6996 WR_CHAN_CALIB_TOTAL) >> 4; 6997 if (sp->wl == 0) { 6998 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_Wr(unit, ci, &data); 6999 sp->init_step[0] = 7000 (DDR40_GET_FIELD 7001 (data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE0_DM_W, 7002 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 7003 VDL_OVRIDE_BYTE0_DM_W, 7004 OVR_STEP) : calib_total; 7005 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_Wr(unit, ci, &data); 7006 sp->init_step[1] = 7007 (DDR40_GET_FIELD 7008 (data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_DM_W, 7009 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, 7010 VDL_OVRIDE_BYTE1_DM_W, 7011 OVR_STEP) : calib_total; 7012 } else { 7013 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_Wr(unit, ci, &data); 7014 sp->init_step[0] = 7015 (DDR40_GET_FIELD 7016 (data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE0_DM_W, 7017 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, 7018 VDL_OVRIDE_BYTE0_DM_W, 7019 OVR_STEP) : calib_total; 7020 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_Wr(unit, ci, &data); 7021 sp->init_step[1] = 7022 (DDR40_GET_FIELD 7023 (data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_DM_W, 7024 OVR_EN)) ? DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, 7025 VDL_OVRIDE_BYTE1_DM_W, 7026 OVR_STEP) : calib_total; 7027 } 7028 break; 7029 default: 7030 break; 7031 } 7032 return SOC_E_NONE; 7033 } 7034 7035 int 7036 _soc_ddr40_shmoo_do(int unit, int ci, soc_ddr_shmoo_param_t *sp) 7037 { 7038 switch (sp->type) { 7039 case SHMOO_INIT_VDL_RESULT: 7040 return _shmoo_init_vdl_result(unit, ci, sp->wl, 1, sp->result); 7041 case SHMOO_RD_EN: 7042 _shmoo_rd_data_dly(unit, ci, sp->wl, 1, sp->result); 7043 return _shmoo_rd_en_rd_dq(unit, ci, sp->wl, 1, sp->vwsPtr); 7044 case SHMOO_RD_DQ: 7045 _shmoo_rd_dq(unit, ci, sp->wl); 7046 return _shmoo_rd_dqs(unit, ci, sp->wl, 1, sp->vwsPtr); 7047 case SHMOO_WR_DQ: 7048 return _shmoo_wr_dq(unit, ci, sp->wl, 1, sp->result); 7049 case SHMOO_ADDRC: 7050 return _shmoo_addr(unit, ci, sp->wl, 1, sp->result); 7051 case SHMOO_WR_DM: 7052 return _shmoo_wr_dm(unit, ci, sp->wl, sp->result); 7053 } 7054 return SOC_E_PARAM; 7055 } 7056 7057 int 7058 _soc_ddr40_shmoo_calib(int unit, int ci, soc_ddr_shmoo_param_t *sp) 7059 { 7060 switch (sp->type) { 7061 case SHMOO_INIT_VDL_RESULT: 7062 return SOC_E_NONE; 7063 case SHMOO_RD_EN: 7064 return _calib_all3(unit, ci, sp->wl, 64, sp->vwsPtr, 0, sp->new_step, sp->type); 7065 case SHMOO_RD_DQ: 7066 return _calib_all2(unit, ci, sp->wl, 64, sp->vwsPtr, 0, sp->new_step, sp->type); 7067 case SHMOO_WR_DQ: 7068 return _calib_all(unit, ci, sp->result, 64, sp->vwsPtr, 0, sp->new_step, sp->type); 7069 case SHMOO_ADDRC: 7070 return _calib_all(unit, ci, sp->result, 128, sp->vwsPtr, 0, sp->new_step, sp->type); 7071 } 7072 return SOC_E_PARAM; 7073 } 7074 7075 int _soc_ddr40_shmoo_plot(soc_ddr_shmoo_param_t *sp) 7076 { 7077 int i; 7078 int vref, vref_count; 7079 char str[65]; 7080 vref_word_shmoo *vwsPtr = sp->vwsPtr; 7081 7082 str[64] = 0; 7083 7084 LOG_CLI((BSL_META("\n"))); 7085 7086 switch (sp->type) { 7087 case SHMOO_INIT_VDL_RESULT: 7088 return SOC_E_NONE; 7089 break; 7090 case SHMOO_RD_EN: 7091 LOG_CLI((BSL_META("**** RD_EN Shmoo (WL=%d)\n"), sp->wl)); 7092 break; 7093 case SHMOO_RD_DQ: 7094 LOG_CLI((BSL_META("**** RD_DQS Shmoo (WL=%d)\n"), sp->wl)); 7095 break; 7096 case SHMOO_WR_DQ: 7097 LOG_CLI((BSL_META("**** WR_DQ Shmoo (WL=%d)\n"), sp->wl)); 7098 break; 7099 case SHMOO_ADDRC: 7100 LOG_CLI((BSL_META("**** ADDRC Shmoo\n"))); 7101 /*LOG_CLI((BSL_META("**** ADDRC Shmoo (WL=%d)\n"), sp->wl));*/ 7102 break; 7103 default: 7104 LOG_CLI((BSL_META("**** ????? Shmoo (WL=%d)\n"), sp->wl)); 7105 break; 7106 } 7107 LOG_CLI((BSL_META("\n"))); 7108 7109 if(sp->type == SHMOO_WR_DQ) { 7110 for (i = 0; i < 64; i++) { 7111 str[i] = '0' + (i/10); 7112 } 7113 LOG_CLI((BSL_META(" %s\n"), str)); 7114 7115 for ( i = 0; i < 64; i++ ) { 7116 str[i] = '0' + (i%10); 7117 } 7118 LOG_CLI((BSL_META(" %s\n"), str)); 7119 7120 vref_count = 16; 7121 7122 for (vref = 0; vref < vref_count; vref++) { 7123 LOG_CLI((BSL_META(" %02d %s\n"), vref, (*vwsPtr)[0].bs[vref].result)); 7124 } 7125 7126 LOG_CLI((BSL_META("\n"))); 7127 return SOC_E_NONE; 7128 } 7129 7130 7131 if (sp->type == SHMOO_ADDRC) { 7132 LOG_CLI((BSL_META("\n BYTE_SEL = 0 \n"))); 7133 } else { 7134 LOG_CLI((BSL_META("\n BYTE = 0 \n"))); 7135 } 7136 7137 for (i = 0; i < 64; i++) { 7138 str[i] = '0' + (i/10); 7139 } 7140 LOG_CLI((BSL_META(" %s\n"), str)); 7141 7142 for ( i = 0; i < 64; i++ ) { 7143 str[i] = '0' + (i%10); 7144 } 7145 LOG_CLI((BSL_META(" %s\n"), str)); 7146 7147 vref_count = (sp->type == SHMOO_RD_DQ) ? 49 : 1; 7148 vref = (sp->type == SHMOO_RD_DQ) ? 16 : 0; 7149 7150 vref_count = (sp->type == SHMOO_RD_EN) ? 64 : vref_count; 7151 7152 for (; vref < vref_count; vref++) { 7153 if(sp->type == SHMOO_RD_DQ) { 7154 LOG_CLI((BSL_META(" %02d %s\n"), vref, (*vwsPtr)[vref].bytes[0].result)); 7155 /* for(i = 0; i < 8; i++) { 7156 LOG_CLI((BSL_META(" %02d-%02d %s\n"), vref, i, (*vwsPtr)[vref].bs[i].result)); 7157 } */ 7158 } else if(sp->type == SHMOO_RD_EN) { 7159 LOG_CLI((BSL_META(" %02d %s\n"), vref, (*vwsPtr)[vref].bs[0].result)); 7160 } else if(sp->type == SHMOO_WR_DQ) { 7161 LOG_CLI((BSL_META(" %02d %s\n"), vref, (*vwsPtr)[vref].bs[0].result)); 7162 } else if((sp->type == SHMOO_ADDRC)) { 7163 LOG_CLI((BSL_META(" %02d "), vref)); 7164 for(i = 0; i < 64; i++) { 7165 LOG_CLI((BSL_META("%c"), (*vwsPtr)[vref].bs[0].result[i])); 7166 } 7167 LOG_CLI((BSL_META("\n"))); 7168 } else { 7169 LOG_CLI((BSL_META("UNKNOWN SHMOO\n"))); 7170 return -1; 7171 } 7172 } 7173 LOG_CLI((BSL_META("\n"))); 7174 7175 if (sp->type == SHMOO_ADDRC) { 7176 LOG_CLI((BSL_META("\n BYTE_SEL = 1 \n"))); 7177 } else { 7178 LOG_CLI((BSL_META("\n BYTE = 1 \n"))); 7179 } 7180 7181 for (i = 0; i < 64; i++) 7182 str[i] = '0' + (i / 10); 7183 LOG_CLI((BSL_META(" %s\n"), str)); 7184 7185 for (i = 0; i < 64; i++) 7186 str[i] = '0' + (i % 10); 7187 LOG_CLI((BSL_META(" %s\n"), str)); 7188 7189 vref = (sp->type == SHMOO_RD_DQ) ? 16 : 0; 7190 7191 for (; vref < vref_count; vref++) { 7192 if(sp->type == SHMOO_RD_DQ) { 7193 LOG_CLI((BSL_META(" %02d %s\n"), vref, (*vwsPtr)[vref].bytes[1].result)); 7194 /* for(i = 8; i < 16; i++) { 7195 LOG_CLI((BSL_META(" %02d-%02d %s\n"), vref, i, (*vwsPtr)[vref].bs[i].result)); 7196 } */ 7197 } else if(sp->type == SHMOO_RD_EN) { 7198 LOG_CLI((BSL_META(" %02d %s\n"), vref, (*vwsPtr)[vref].bs[8].result)); 7199 } else if(sp->type == SHMOO_WR_DQ) { 7200 LOG_CLI((BSL_META(" %02d %s\n"), vref, (*vwsPtr)[vref].bs[8].result)); 7201 } else if((sp->type == SHMOO_ADDRC)) { 7202 LOG_CLI((BSL_META(" %02d "), vref)); 7203 for(i = 64; i < 128; i++) { 7204 LOG_CLI((BSL_META("%c"), (*vwsPtr)[vref].bs[0].result[i])); 7205 } 7206 LOG_CLI((BSL_META("\n"))); 7207 } else { 7208 LOG_CLI((BSL_META("UNKNOWN SHMOO\n"))); 7209 return -1; 7210 } 7211 } 7212 LOG_CLI((BSL_META("\n"))); 7213 7214 return SOC_E_NONE; 7215 } 7216 7217 int 7218 _soc_ddr40_shmoo_set_new_step(int unit, int ci, soc_ddr_shmoo_param_t *sp) 7219 { 7220 uint32 data = 0; 7221 int byte, bit, n; 7222 int indx; 7223 uint32 init_rd_dqs_step; 7224 uint32 init_rd_en_step; 7225 uint32 new_rd_dqs_step; 7226 uint32 new_rd_en_step; 7227 uint32 vref_pick; 7228 uint32 new_rd_en_avg_step; 7229 vref_word_shmoo *vwsPtr = sp->vwsPtr; 7230 7231 switch (sp->type) { 7232 case SHMOO_RD_EN: 7233 if (sp->wl == 0) { 7234 n = sp->new_step[0]; 7235 data = SET_OVR_STEP(n); 7236 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 7237 data); 7238 n = sp->new_step[8]; 7239 data = SET_OVR_STEP(n); 7240 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 7241 data); 7242 n = (sp->new_step[0] + sp->new_step[8]) >> 1; 7243 data = SET_OVR_STEP(n); 7244 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 7245 } else { 7246 n = sp->new_step[0]; 7247 data = SET_OVR_STEP(n); 7248 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, 7249 data); 7250 n = sp->new_step[8]; 7251 data = SET_OVR_STEP(n); 7252 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, 7253 data); 7254 n = (sp->new_step[0] + sp->new_step[8]) >> 1; 7255 data = SET_OVR_STEP(n); 7256 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 7257 } 7258 break; 7259 case SHMOO_RD_DQ: 7260 READ_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ci, &data); 7261 vref_pick = 7262 DDR40_GET_FIELD(data, DDR40_PHY_CONTROL_REGS, VREF_DAC_CONTROL, 7263 DAC0); 7264 if (sp->wl == 0) { 7265 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, &data); 7266 init_rd_dqs_step = 7267 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE0_R_P, 7268 OVR_STEP); 7269 init_rd_en_step = (*vwsPtr)[vref_pick].uncapped_rd_en_step[0]; 7270 new_rd_dqs_step = sp->new_step[0]; 7271 new_rd_en_step = init_rd_en_step - ((init_rd_dqs_step - new_rd_dqs_step) >> RD_EN_DQS_CORROLATION); 7272 LOG_INFO(BSL_LS_SOC_DDR, 7273 (BSL_META_U(unit, 7274 "Switching to RD_DQS Step (Byte 0): %2d\n"), 7275 new_rd_dqs_step)); 7276 LOG_INFO(BSL_LS_SOC_DDR, 7277 (BSL_META_U(unit, 7278 "Switching to RD_EN Step (Byte 0): %2d\n"), 7279 new_rd_en_step)); 7280 data = SET_OVR_STEP(new_rd_dqs_step); 7281 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 7282 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 7283 data = SET_OVR_STEP(new_rd_en_step); 7284 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, data); 7285 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &data); 7286 new_rd_en_avg_step = new_rd_en_step; 7287 init_rd_dqs_step = 7288 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_0, VDL_OVRIDE_BYTE1_R_P, 7289 OVR_STEP); 7290 init_rd_en_step = (*vwsPtr)[vref_pick].uncapped_rd_en_step[1]; 7291 new_rd_dqs_step = sp->new_step[8]; 7292 new_rd_en_step = init_rd_en_step - ((init_rd_dqs_step - new_rd_dqs_step) >> RD_EN_DQS_CORROLATION); 7293 LOG_INFO(BSL_LS_SOC_DDR, 7294 (BSL_META_U(unit, 7295 "Switching to RD_DQS Step (Byte 1): %2d\n"), 7296 new_rd_dqs_step)); 7297 LOG_INFO(BSL_LS_SOC_DDR, 7298 (BSL_META_U(unit, 7299 "Switching to RD_EN Step (Byte 1): %2d\n"), 7300 new_rd_en_step)); 7301 data = SET_OVR_STEP(new_rd_dqs_step); 7302 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 7303 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 7304 data = SET_OVR_STEP(new_rd_en_step); 7305 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, data); 7306 new_rd_en_avg_step = (new_rd_en_avg_step + new_rd_en_step) >> 1; 7307 data = SET_OVR_STEP(new_rd_en_avg_step); 7308 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 7309 } else { 7310 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, &data); 7311 init_rd_dqs_step = 7312 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE0_R_P, 7313 OVR_STEP); 7314 init_rd_en_step = (*vwsPtr)[vref_pick].uncapped_rd_en_step[0]; 7315 new_rd_dqs_step = sp->new_step[0]; 7316 new_rd_en_step = init_rd_en_step - ((init_rd_dqs_step - new_rd_dqs_step) >> RD_EN_DQS_CORROLATION); 7317 LOG_INFO(BSL_LS_SOC_DDR, 7318 (BSL_META_U(unit, 7319 "Switching to RD_DQS Step (Byte 0): %2d\n"), 7320 new_rd_dqs_step)); 7321 LOG_INFO(BSL_LS_SOC_DDR, 7322 (BSL_META_U(unit, 7323 "Switching to RD_EN Step (Byte 0): %2d\n"), 7324 new_rd_en_step)); 7325 data = SET_OVR_STEP(new_rd_dqs_step); 7326 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, data); 7327 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, data); 7328 data = SET_OVR_STEP(new_rd_en_step); 7329 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, data); 7330 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, &data); 7331 new_rd_en_avg_step = new_rd_en_step; 7332 init_rd_dqs_step = 7333 DDR40_GET_FIELD(data, DDR40_PHY_WORD_LANE_1, VDL_OVRIDE_BYTE1_R_P, 7334 OVR_STEP); 7335 init_rd_en_step = (*vwsPtr)[vref_pick].uncapped_rd_en_step[1]; 7336 new_rd_dqs_step = sp->new_step[8]; 7337 new_rd_en_step = init_rd_en_step - ((init_rd_dqs_step - new_rd_dqs_step) >> RD_EN_DQS_CORROLATION); 7338 LOG_INFO(BSL_LS_SOC_DDR, 7339 (BSL_META_U(unit, 7340 "Switching to RD_DQS Step (Byte 1): %2d\n"), 7341 new_rd_dqs_step)); 7342 LOG_INFO(BSL_LS_SOC_DDR, 7343 (BSL_META_U(unit, 7344 "Switching to RD_EN Step (Byte 1): %2d\n"), 7345 new_rd_en_step)); 7346 data = SET_OVR_STEP(new_rd_dqs_step); 7347 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, data); 7348 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, data); 7349 data = SET_OVR_STEP(new_rd_en_step); 7350 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, data); 7351 new_rd_en_avg_step = (new_rd_en_avg_step + new_rd_en_step) >> 1; 7352 data = SET_OVR_STEP(new_rd_en_avg_step); 7353 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, data); 7354 } 7355 break; 7356 case SHMOO_WR_DQ: 7357 n = 0; 7358 for (byte = 0; byte < 2; byte++) { 7359 for (bit = 0; bit < 8; bit++) { 7360 data = SET_OVR_STEP(sp->new_step[n]); 7361 indx = (sp->wl*4) + (byte*2) + (bit/4); 7362 COMPILER_REFERENCE(indx); 7363 WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_Wr(sp->wl, byte, 7364 bit, unit, 7365 ci, data); 7366 n++; 7367 } 7368 } 7369 break; 7370 case SHMOO_ADDRC: 7371 n = 0; 7372 if (sp->wl == 0) { 7373 data = SET_OVR_STEP(sp->new_step[n]); 7374 DDR40_SET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_OVRIDE_BIT_CTL, 7375 BYTE_SEL, 0); 7376 WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(unit, ci, data); 7377 DDR40_SET_FIELD(data, DDR40_PHY_CONTROL_REGS, VDL_OVRIDE_BYTE_CTL, 7378 BYTE_SEL, 0); 7379 WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTLr(unit, ci, 0); 7380 sal_usleep(2000); 7381 _soc_mem_reset_and_init_after_shmoo_addr(unit, ci); 7382 n = _test_func_self_test_2(unit, ci, 0, 1); 7383 } 7384 break; 7385 default: 7386 break; 7387 } 7388 return SOC_E_NONE; 7389 } 7390 7391 /*********************************************************************** 7392 * Functions to schmoo the DDR vdl/voltage etc. 7393 */ 7394 int 7395 soc_ddr40_shmoo_ctl(int unit, int ci, uint32 phyType, uint32 ctlType, int stat, int isplot) 7396 { 7397 soc_ddr_shmoo_param_t *sp; 7398 int ciC; 7399 uint32 error_mask0, error_mask1; 7400 uint32 rval; 7401 7402 ciC = ci & 0xFFFFFFFE; 7403 7404 if (!stat) { 7405 switch(ctlType) { 7406 case DDR_CTLR_TRSVP: 7407 break; 7408 case DDR_CTLR_T0: 7409 7410 rval = 0; 7411 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, WFIFO_CTL_CORRECTED_ERROR_DISINTf, 1); 7412 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, WFIFO_CTL_UNCORRECTED_ERROR_DISINTf, 1); 7413 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, RFIFO_CTL_CORRECTED_ERROR_DISINTf, 1); 7414 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, RFIFO_CTL_UNCORRECTED_ERROR_DISINTf, 1); 7415 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, PHY_BL0_RD_FIFO_ERRORf, 1); 7416 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, PHY_BL1_RD_FIFO_ERRORf, 1); 7417 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, RFIFO_OVERFLOW_DISINTf, 1); 7418 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, WB_OVERFLOW_DISINTf, 1); 7419 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, PHY_READYf, 1); 7420 if(_check_dram(ciC)) { 7421 SOC_IF_ERROR_RETURN(READ_CI_ERROR_MASKr(unit, ciC, &error_mask0)); 7422 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC, rval)); 7423 } 7424 if(_check_dram(ciC + 1)) { 7425 SOC_IF_ERROR_RETURN(READ_CI_ERROR_MASKr(unit, ciC + 1, &error_mask1)); 7426 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC + 1, rval)); 7427 } 7428 7429 if((ci & 0x1) == 0) { 7430 if(_check_dram_either(ci)) { 7431 SOC_IF_ERROR_RETURN(_soc_ddr40_phy_PVT_ctl(unit, ci, 1, stat)); 7432 SOC_IF_ERROR_RETURN(_soc_ddr_shmoo_prepare_for_shmoo(unit, ci)); 7433 } 7434 } 7435 sp = sal_alloc(sizeof(soc_ddr_shmoo_param_t), "Shmoo_Params"); 7436 if (sp == NULL) { 7437 return(SOC_E_MEMORY); 7438 } 7439 sal_memset(sp, 0, sizeof(soc_ddr_shmoo_param_t)); 7440 sp->vwsPtr = sal_alloc(sizeof(vref_word_shmoo), "Shmoo_vws"); 7441 if (sp->vwsPtr == NULL) { 7442 sal_free(sp); 7443 return(SOC_E_MEMORY); 7444 } 7445 for(sp->wl = 0; sp->wl < 2; sp->wl++) { 7446 if(!_check_dram(ci+(sp->wl))) { 7447 continue; 7448 } 7449 sp->type = SHMOO_INIT_VDL_RESULT; 7450 LOG_INFO(BSL_LS_SOC_DDR, 7451 (BSL_META_U(unit, 7452 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7453 sp->type, ci, sp->wl)); 7454 _shmoo_print_diagnostics(unit, ci, sp->wl); 7455 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7456 _soc_ddr40_shmoo_do(unit, ci, sp); 7457 _soc_ddr40_shmoo_calib(unit,ci, sp); 7458 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7459 LOG_INFO(BSL_LS_SOC_DDR, 7460 (BSL_META_U(unit, 7461 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7462 sp->type, ci, sp->wl)); 7463 _shmoo_print_diagnostics(unit, ci, sp->wl); 7464 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7465 _soc_ddr40_shmoo_plot(sp); 7466 } 7467 } 7468 for(sp->wl = 0; sp->wl < 2; sp->wl++) { 7469 if(!_check_dram(ci+(sp->wl))) { 7470 continue; 7471 } 7472 sp->type = SHMOO_RD_EN; 7473 LOG_INFO(BSL_LS_SOC_DDR, 7474 (BSL_META_U(unit, 7475 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7476 sp->type, ci, sp->wl)); 7477 _shmoo_print_diagnostics(unit, ci, sp->wl); 7478 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7479 _soc_ddr40_shmoo_do(unit, ci, sp); 7480 _soc_ddr40_shmoo_calib(unit,ci, sp); 7481 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7482 LOG_INFO(BSL_LS_SOC_DDR, 7483 (BSL_META_U(unit, 7484 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7485 sp->type, ci, sp->wl)); 7486 _shmoo_print_diagnostics(unit, ci, sp->wl); 7487 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7488 _soc_ddr40_shmoo_plot(sp); 7489 } 7490 sp->type = SHMOO_RD_DQ; 7491 LOG_INFO(BSL_LS_SOC_DDR, 7492 (BSL_META_U(unit, 7493 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7494 sp->type, ci, sp->wl)); 7495 _shmoo_print_diagnostics(unit, ci, sp->wl); 7496 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7497 _soc_ddr40_shmoo_do(unit, ci, sp); 7498 _soc_ddr40_shmoo_calib(unit,ci, sp); 7499 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7500 LOG_INFO(BSL_LS_SOC_DDR, 7501 (BSL_META_U(unit, 7502 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7503 sp->type, ci, sp->wl)); 7504 _shmoo_print_diagnostics(unit, ci, sp->wl); 7505 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7506 _soc_ddr40_shmoo_plot(sp); 7507 } 7508 sp->type = SHMOO_WR_DQ; 7509 LOG_INFO(BSL_LS_SOC_DDR, 7510 (BSL_META_U(unit, 7511 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7512 sp->type, ci, sp->wl)); 7513 _shmoo_print_diagnostics(unit, ci, sp->wl); 7514 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7515 _soc_ddr40_shmoo_do(unit, ci, sp); 7516 _soc_ddr40_shmoo_calib(unit,ci, sp); 7517 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7518 LOG_INFO(BSL_LS_SOC_DDR, 7519 (BSL_META_U(unit, 7520 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7521 sp->type, ci, sp->wl)); 7522 _shmoo_print_diagnostics(unit, ci, sp->wl); 7523 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7524 _soc_ddr40_shmoo_plot(sp); 7525 } 7526 if((_check_dram_both(ci+(sp->wl)) && (sp->wl == 1)) || (!_check_dram_both(ci+(sp->wl)) && _check_dram_either(ci+(sp->wl)))) { 7527 sp->wl = 0; 7528 for(sp->type = SHMOO_ADDRC; sp->type < SHMOO_WR_DM; sp->type++) { 7529 LOG_INFO(BSL_LS_SOC_DDR, 7530 (BSL_META_U(unit, 7531 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = Both\n"), 7532 sp->type, ci)); 7533 _shmoo_print_diagnostics(unit, ci, sp->wl); 7534 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7535 _soc_ddr40_shmoo_do(unit, ci, sp); 7536 _soc_ddr40_shmoo_calib(unit,ci,sp); 7537 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7538 LOG_INFO(BSL_LS_SOC_DDR, 7539 (BSL_META_U(unit, 7540 "AFTER SHMOO: Type = %d\tCI = %d\tWL = Both\n"), 7541 sp->type, ci)); 7542 _shmoo_print_diagnostics(unit, ci, sp->wl); 7543 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7544 _soc_ddr40_shmoo_plot(sp); 7545 } 7546 } 7547 sp->wl = 1; 7548 } 7549 } 7550 if (sp->vwsPtr != NULL) { 7551 sal_free(sp->vwsPtr); 7552 } 7553 if (sp != NULL) { 7554 sal_free(sp); 7555 } 7556 7557 rval = 0; 7558 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_CORRECTED_ERRORf, 1); 7559 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_UNCORRECTED_ERRORf, 1); 7560 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_CORRECTED_ERRORf, 1); 7561 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_UNCORRECTED_ERRORf, 1); 7562 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_BL0_RD_FIFO_ERRORf, 1); 7563 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_BL1_RD_FIFO_ERRORf, 1); 7564 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_OVERFLOWf, 1); 7565 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_OVERFLOWf, 1); 7566 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_READY_EVENTf, 1); 7567 if(_check_dram(ciC)) { 7568 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC, error_mask0)); 7569 SOC_IF_ERROR_RETURN(WRITE_CI_ERRORr(unit, ciC, rval)); 7570 } 7571 if(_check_dram(ciC + 1)) { 7572 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC + 1, error_mask1)); 7573 SOC_IF_ERROR_RETURN(WRITE_CI_ERRORr(unit, ciC + 1, rval)); 7574 } 7575 7576 LOG_VERBOSE(BSL_LS_SOC_COMMON, 7577 (BSL_META_U(unit, 7578 "DDR Tuning Complete\n"))); 7579 break; 7580 case DDR_CTLR_T1: 7581 if((ci & 0x1) == 0) { 7582 if(_check_dram_either(ci)) { 7583 SOC_IF_ERROR_RETURN(_soc_ddr40_phy_PVT_ctl(unit, ci, 1, stat)); 7584 SOC_IF_ERROR_RETURN(_soc_ddr_shmoo_prepare_for_shmoo(unit, ci)); 7585 } 7586 } 7587 sp = sal_alloc(sizeof(soc_ddr_shmoo_param_t), "Shmoo_Params"); 7588 if (sp == NULL) { 7589 return(SOC_E_MEMORY); 7590 } 7591 sal_memset(sp, 0, sizeof(soc_ddr_shmoo_param_t)); 7592 sp->vwsPtr = sal_alloc(sizeof(vref_word_shmoo), "Shmoo_vws"); 7593 if (sp->vwsPtr == NULL) { 7594 sal_free(sp); 7595 return(SOC_E_MEMORY); 7596 } 7597 for(sp->wl = 0; sp->wl < 2; sp->wl++) { 7598 if(!_check_dram(ci+(sp->wl))) { 7599 continue; 7600 } 7601 sp->type = SHMOO_INIT_VDL_RESULT; 7602 LOG_INFO(BSL_LS_SOC_DDR, 7603 (BSL_META_U(unit, 7604 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7605 sp->type, ci, sp->wl)); 7606 _shmoo_print_diagnostics(unit, ci, sp->wl); 7607 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7608 _soc_ddr40_shmoo_do(unit, ci, sp); 7609 _soc_ddr40_shmoo_calib(unit,ci, sp); 7610 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7611 LOG_INFO(BSL_LS_SOC_DDR, 7612 (BSL_META_U(unit, 7613 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7614 sp->type, ci, sp->wl)); 7615 _shmoo_print_diagnostics(unit, ci, sp->wl); 7616 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7617 _soc_ddr40_shmoo_plot(sp); 7618 } 7619 } 7620 for(sp->wl = 0; sp->wl < 2; sp->wl++) { 7621 if(!_check_dram(ci+(sp->wl))) { 7622 continue; 7623 } 7624 sp->type = SHMOO_RD_EN; 7625 LOG_INFO(BSL_LS_SOC_DDR, 7626 (BSL_META_U(unit, 7627 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7628 sp->type, ci, sp->wl)); 7629 _shmoo_print_diagnostics(unit, ci, sp->wl); 7630 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7631 _soc_ddr40_shmoo_do(unit, ci, sp); 7632 _soc_ddr40_shmoo_calib(unit,ci, sp); 7633 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7634 LOG_INFO(BSL_LS_SOC_DDR, 7635 (BSL_META_U(unit, 7636 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7637 sp->type, ci, sp->wl)); 7638 _shmoo_print_diagnostics(unit, ci, sp->wl); 7639 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7640 _soc_ddr40_shmoo_plot(sp); 7641 } 7642 sp->type = SHMOO_RD_DQ; 7643 LOG_INFO(BSL_LS_SOC_DDR, 7644 (BSL_META_U(unit, 7645 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7646 sp->type, ci, sp->wl)); 7647 _shmoo_print_diagnostics(unit, ci, sp->wl); 7648 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7649 _soc_ddr40_shmoo_do(unit, ci, sp); 7650 _soc_ddr40_shmoo_calib(unit,ci, sp); 7651 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7652 LOG_INFO(BSL_LS_SOC_DDR, 7653 (BSL_META_U(unit, 7654 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7655 sp->type, ci, sp->wl)); 7656 _shmoo_print_diagnostics(unit, ci, sp->wl); 7657 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7658 _soc_ddr40_shmoo_plot(sp); 7659 } 7660 sp->type = SHMOO_WR_DQ; 7661 LOG_INFO(BSL_LS_SOC_DDR, 7662 (BSL_META_U(unit, 7663 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7664 sp->type, ci, sp->wl)); 7665 _shmoo_print_diagnostics(unit, ci, sp->wl); 7666 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7667 _soc_ddr40_shmoo_do(unit, ci, sp); 7668 _soc_ddr40_shmoo_calib(unit,ci, sp); 7669 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7670 LOG_INFO(BSL_LS_SOC_DDR, 7671 (BSL_META_U(unit, 7672 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7673 sp->type, ci, sp->wl)); 7674 _shmoo_print_diagnostics(unit, ci, sp->wl); 7675 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7676 _soc_ddr40_shmoo_plot(sp); 7677 } 7678 if((_check_dram_both(ci+(sp->wl)) && (sp->wl == 1)) || (!_check_dram_both(ci+(sp->wl)) && _check_dram_either(ci+(sp->wl)))) { 7679 sp->wl = 0; 7680 for(sp->type = SHMOO_ADDRC; sp->type < SHMOO_WR_DM; sp->type++) { 7681 LOG_INFO(BSL_LS_SOC_DDR, 7682 (BSL_META_U(unit, 7683 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = Both\n"), 7684 sp->type, ci)); 7685 _shmoo_print_diagnostics(unit, ci, sp->wl); 7686 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7687 _soc_ddr40_shmoo_do(unit, ci, sp); 7688 _soc_ddr40_shmoo_calib(unit,ci,sp); 7689 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7690 LOG_INFO(BSL_LS_SOC_DDR, 7691 (BSL_META_U(unit, 7692 "AFTER SHMOO: Type = %d\tCI = %d\tWL = Both\n"), 7693 sp->type, ci)); 7694 _shmoo_print_diagnostics(unit, ci, sp->wl); 7695 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7696 _soc_ddr40_shmoo_plot(sp); 7697 } 7698 } 7699 sp->wl = 1; 7700 } 7701 } 7702 if (sp->vwsPtr != NULL) { 7703 sal_free(sp->vwsPtr); 7704 } 7705 if (sp != NULL) { 7706 sal_free(sp); 7707 } 7708 LOG_VERBOSE(BSL_LS_SOC_COMMON, 7709 (BSL_META_U(unit, 7710 "DDR Tuning Complete\n"))); 7711 break; 7712 case DDR_CTLR_T2: 7713 if((ci & 0x1) == 0) { 7714 if(_check_dram_either(ci)) { 7715 SOC_IF_ERROR_RETURN(_soc_ddr40_phy_PVT_ctl(unit, ci, 1, stat)); 7716 SOC_IF_ERROR_RETURN(_soc_ddr_shmoo_prepare_for_shmoo(unit, ci)); 7717 } 7718 } 7719 sp = sal_alloc(sizeof(soc_ddr_shmoo_param_t), "Shmoo_Params"); 7720 if (sp == NULL) { 7721 return(SOC_E_MEMORY); 7722 } 7723 sal_memset(sp, 0, sizeof(soc_ddr_shmoo_param_t)); 7724 sp->vwsPtr = sal_alloc(sizeof(vref_word_shmoo), "Shmoo_vws"); 7725 if (sp->vwsPtr == NULL) { 7726 sal_free(sp); 7727 return(SOC_E_MEMORY); 7728 } 7729 for(sp->wl = 0; sp->wl < 2; sp->wl++) { 7730 if(!_check_dram(ci+(sp->wl))) { 7731 continue; 7732 } 7733 sp->type = SHMOO_INIT_VDL_RESULT; 7734 LOG_INFO(BSL_LS_SOC_DDR, 7735 (BSL_META_U(unit, 7736 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7737 sp->type, ci, sp->wl)); 7738 _shmoo_print_diagnostics(unit, ci, sp->wl); 7739 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7740 _soc_ddr40_shmoo_do(unit, ci, sp); 7741 _soc_ddr40_shmoo_calib(unit,ci, sp); 7742 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7743 LOG_INFO(BSL_LS_SOC_DDR, 7744 (BSL_META_U(unit, 7745 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7746 sp->type, ci, sp->wl)); 7747 _shmoo_print_diagnostics(unit, ci, sp->wl); 7748 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7749 _soc_ddr40_shmoo_plot(sp); 7750 } 7751 } 7752 for(sp->wl = 0; sp->wl < 2; sp->wl++) { 7753 if(!_check_dram(ci+(sp->wl))) { 7754 continue; 7755 } 7756 sp->type = SHMOO_RD_EN; 7757 LOG_INFO(BSL_LS_SOC_DDR, 7758 (BSL_META_U(unit, 7759 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7760 sp->type, ci, sp->wl)); 7761 _shmoo_print_diagnostics(unit, ci, sp->wl); 7762 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7763 _soc_ddr40_shmoo_do(unit, ci, sp); 7764 _soc_ddr40_shmoo_calib(unit,ci, sp); 7765 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7766 LOG_INFO(BSL_LS_SOC_DDR, 7767 (BSL_META_U(unit, 7768 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7769 sp->type, ci, sp->wl)); 7770 _shmoo_print_diagnostics(unit, ci, sp->wl); 7771 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7772 _soc_ddr40_shmoo_plot(sp); 7773 } 7774 sp->type = SHMOO_RD_DQ; 7775 LOG_INFO(BSL_LS_SOC_DDR, 7776 (BSL_META_U(unit, 7777 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7778 sp->type, ci, sp->wl)); 7779 _shmoo_print_diagnostics(unit, ci, sp->wl); 7780 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7781 _soc_ddr40_shmoo_do(unit, ci, sp); 7782 _soc_ddr40_shmoo_calib(unit,ci, sp); 7783 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7784 LOG_INFO(BSL_LS_SOC_DDR, 7785 (BSL_META_U(unit, 7786 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7787 sp->type, ci, sp->wl)); 7788 _shmoo_print_diagnostics(unit, ci, sp->wl); 7789 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7790 _soc_ddr40_shmoo_plot(sp); 7791 } 7792 sp->type = SHMOO_WR_DQ; 7793 LOG_INFO(BSL_LS_SOC_DDR, 7794 (BSL_META_U(unit, 7795 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7796 sp->type, ci, sp->wl)); 7797 _shmoo_print_diagnostics(unit, ci, sp->wl); 7798 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7799 _soc_ddr40_shmoo_do(unit, ci, sp); 7800 _soc_ddr40_shmoo_calib(unit,ci, sp); 7801 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7802 LOG_INFO(BSL_LS_SOC_DDR, 7803 (BSL_META_U(unit, 7804 "AFTER SHMOO: Type = %d\tCI = %d\tWL = %d\n"), 7805 sp->type, ci, sp->wl)); 7806 _shmoo_print_diagnostics(unit, ci, sp->wl); 7807 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7808 _soc_ddr40_shmoo_plot(sp); 7809 } 7810 if((_check_dram_both(ci+(sp->wl)) && (sp->wl == 1)) || (!_check_dram_both(ci+(sp->wl)) && _check_dram_either(ci+(sp->wl)))) { 7811 sp->wl = 0; 7812 for(sp->type = SHMOO_ADDRC; sp->type < SHMOO_WR_DM; sp->type++) { 7813 LOG_INFO(BSL_LS_SOC_DDR, 7814 (BSL_META_U(unit, 7815 "BEFORE SHMOO: Type = %d\tCI = %d\tWL = Both\n"), 7816 sp->type, ci)); 7817 _shmoo_print_diagnostics(unit, ci, sp->wl); 7818 _soc_ddr40_shmoo_get_init_step(unit, ci, sp); 7819 _soc_ddr40_shmoo_do(unit, ci, sp); 7820 _soc_ddr40_shmoo_calib(unit,ci,sp); 7821 _soc_ddr40_shmoo_set_new_step(unit, ci, sp); 7822 LOG_INFO(BSL_LS_SOC_DDR, 7823 (BSL_META_U(unit, 7824 "AFTER SHMOO: Type = %d\tCI = %d\tWL = Both\n"), 7825 sp->type, ci)); 7826 _shmoo_print_diagnostics(unit, ci, sp->wl); 7827 if (isplot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) { 7828 _soc_ddr40_shmoo_plot(sp); 7829 } 7830 } 7831 sp->wl = 1; 7832 } 7833 } 7834 if (sp->vwsPtr != NULL) { 7835 sal_free(sp->vwsPtr); 7836 } 7837 if (sp != NULL) { 7838 sal_free(sp); 7839 } 7840 LOG_VERBOSE(BSL_LS_SOC_COMMON, 7841 (BSL_META_U(unit, 7842 "DDR Tuning Complete\n"))); 7843 break; 7844 case DDR_CTLR_T3: 7845 break; 7846 default: 7847 break; 7848 } 7849 } else { 7850 /* report only */ 7851 switch(ctlType) { 7852 case DDR_CTLR_TRSVP: 7853 break; 7854 case DDR_CTLR_T0: 7855 break; 7856 case DDR_CTLR_T1: 7857 break; 7858 case DDR_CTLR_T2: 7859 break; 7860 case DDR_CTLR_T3: 7861 break; 7862 default: 7863 break; 7864 } 7865 } 7866 return SOC_E_NONE; 7867 } 7868 7869 #define OVR_COMPRESS(_v) (((_v) & 0x3f) | \ 7870 (((_v) & 0x100) ? 0x40 : 0) | \ 7871 (((_v) & 0x10000) ? 0x80 : 0)) 7872 7873 7874 int soc_ddr40_shmoo_savecfg(int unit, int ci) 7875 { 7876 char name_str[32], val_str[96]; 7877 uint32 value[4], valarr[4] = { 0, 0, 0, 0}; 7878 7879 if (soc_mem_config_set == NULL) { 7880 return SOC_E_UNAVAIL; 7881 } 7882 7883 /* SHMOO_RD_DATA_DLY: */ 7884 READ_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, (uint32 *)&valarr[0]); /* Only Bits 0..2 */ 7885 READ_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, (uint32 *)&valarr[1]); /* Only Bits 0..2 */ 7886 value[0] = ((valarr[1] & 0x7) << 8) | (valarr[0] & 0x7); 7887 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_RD_DATA_DLY, ci, unit); 7888 sal_sprintf(val_str, "0x%08x", value[0]); 7889 if (soc_mem_config_set(name_str, val_str) < 0) { 7890 return SOC_E_MEMORY; 7891 } 7892 7893 /* SHMOO_RD_EN: */ 7894 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, (uint32 *)&valarr[0]); 7895 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, (uint32 *)&valarr[1]); 7896 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, (uint32 *)&valarr[2]); 7897 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | (OVR_COMPRESS(valarr[2]) << 16); 7898 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, (uint32 *)&valarr[0]); 7899 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, (uint32 *)&valarr[1]); 7900 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, (uint32 *)&valarr[2]); 7901 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | (OVR_COMPRESS(valarr[2]) << 16); 7902 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_RD_EN, ci, unit); 7903 sal_sprintf(val_str, "0x%08x,0x%08x", value[0], value[1]); 7904 if (soc_mem_config_set(name_str, val_str) < 0) { 7905 return SOC_E_MEMORY; 7906 } 7907 7908 /* SHMOO_RD_DQ : */ 7909 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7910 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7911 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7912 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7913 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7914 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7915 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7916 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7917 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7918 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7919 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7920 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7921 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7922 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7923 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7924 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7925 value[2] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7926 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7927 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7928 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7929 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7930 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7931 value[3] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7932 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7933 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_RD_DQ_WL0_RP, ci, unit); 7934 sal_sprintf(val_str, "0x%08x,0x%08x,0x%08x,0x%08x", value[0], value[1], value[2], value[3]); 7935 if (soc_mem_config_set(name_str, val_str) < 0) { 7936 return SOC_E_MEMORY; 7937 } 7938 7939 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7940 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7941 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7942 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7943 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7944 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7945 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7946 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7947 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7948 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7949 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7950 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7951 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7952 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7953 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7954 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7955 value[2] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7956 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7957 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Pr(unit, ci, (uint32 *)&valarr[0]); 7958 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Pr(unit, ci, (uint32 *)&valarr[1]); 7959 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Pr(unit, ci, (uint32 *)&valarr[2]); 7960 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Pr(unit, ci, (uint32 *)&valarr[3]); 7961 value[3] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7962 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7963 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_RD_DQ_WL1_RP, ci, unit); 7964 sal_sprintf(val_str, "0x%08x,0x%08x,0x%08x,0x%08x", value[0], value[1], value[2], value[3]); 7965 if (soc_mem_config_set(name_str, val_str) < 0) { 7966 return SOC_E_MEMORY; 7967 } 7968 7969 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Nr(unit, ci, (uint32 *)&valarr[0]); 7970 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Nr(unit, ci, (uint32 *)&valarr[1]); 7971 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Nr(unit, ci, (uint32 *)&valarr[2]); 7972 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Nr(unit, ci, (uint32 *)&valarr[3]); 7973 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7974 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7975 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Nr(unit, ci, (uint32 *)&valarr[0]); 7976 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Nr(unit, ci, (uint32 *)&valarr[1]); 7977 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Nr(unit, ci, (uint32 *)&valarr[2]); 7978 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Nr(unit, ci, (uint32 *)&valarr[3]); 7979 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7980 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7981 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Nr(unit, ci, (uint32 *)&valarr[0]); 7982 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Nr(unit, ci, (uint32 *)&valarr[1]); 7983 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Nr(unit, ci, (uint32 *)&valarr[2]); 7984 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Nr(unit, ci, (uint32 *)&valarr[3]); 7985 value[2] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7986 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7987 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Nr(unit, ci, (uint32 *)&valarr[0]); 7988 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Nr(unit, ci, (uint32 *)&valarr[1]); 7989 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Nr(unit, ci, (uint32 *)&valarr[2]); 7990 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Nr(unit, ci, (uint32 *)&valarr[3]); 7991 value[3] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 7992 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 7993 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_RD_DQ_WL0_RN, ci, unit); 7994 sal_sprintf(val_str, "0x%08x,0x%08x,0x%08x,0x%08x", value[0], value[1], value[2], value[3]); 7995 if (soc_mem_config_set(name_str, val_str) < 0) { 7996 return SOC_E_MEMORY; 7997 } 7998 7999 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Nr(unit, ci, (uint32 *)&valarr[0]); 8000 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Nr(unit, ci, (uint32 *)&valarr[1]); 8001 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Nr(unit, ci, (uint32 *)&valarr[2]); 8002 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Nr(unit, ci, (uint32 *)&valarr[3]); 8003 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8004 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8005 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Nr(unit, ci, (uint32 *)&valarr[0]); 8006 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Nr(unit, ci, (uint32 *)&valarr[1]); 8007 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Nr(unit, ci, (uint32 *)&valarr[2]); 8008 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Nr(unit, ci, (uint32 *)&valarr[3]); 8009 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8010 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8011 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Nr(unit, ci, (uint32 *)&valarr[0]); 8012 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Nr(unit, ci, (uint32 *)&valarr[1]); 8013 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Nr(unit, ci, (uint32 *)&valarr[2]); 8014 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Nr(unit, ci, (uint32 *)&valarr[3]); 8015 value[2] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8016 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8017 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Nr(unit, ci, (uint32 *)&valarr[0]); 8018 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Nr(unit, ci, (uint32 *)&valarr[1]); 8019 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Nr(unit, ci, (uint32 *)&valarr[2]); 8020 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Nr(unit, ci, (uint32 *)&valarr[3]); 8021 value[3] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8022 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8023 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_RD_DQ_WL1_RN, ci, unit); 8024 sal_sprintf(val_str, "0x%08x,0x%08x,0x%08x,0x%08x", value[0], value[1], value[2], value[3]); 8025 if (soc_mem_config_set(name_str, val_str) < 0) { 8026 return SOC_E_MEMORY; 8027 } 8028 8029 /* SHMOO_RD_DQS: */ 8030 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, (uint32 *)&valarr[0]); 8031 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, (uint32 *)&valarr[1]); 8032 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, (uint32 *)&valarr[2]); 8033 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, (uint32 *)&valarr[3]); 8034 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8035 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8036 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, (uint32 *)&valarr[0]); 8037 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, (uint32 *)&valarr[1]); 8038 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, (uint32 *)&valarr[2]); 8039 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, (uint32 *)&valarr[3]); 8040 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8041 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8042 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_RD_DQS, ci, unit); 8043 sal_sprintf(val_str, "0x%08x,0x%08x", value[0], value[1]); 8044 if (soc_mem_config_set(name_str, val_str) < 0) { 8045 return SOC_E_MEMORY; 8046 } 8047 8048 /* SHMOO_VREF: */ 8049 READ_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ci, (uint32 *)&valarr[0]); 8050 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_VREF, ci, unit); 8051 sal_sprintf(val_str, "0x%08x", valarr[0]); 8052 if (soc_mem_config_set(name_str, val_str) < 0) { 8053 return SOC_E_MEMORY; 8054 } 8055 8056 /* SHMOO_WR_DQ : */ 8057 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_Wr(unit, ci, (uint32 *)&valarr[0]); 8058 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_Wr(unit, ci, (uint32 *)&valarr[1]); 8059 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_Wr(unit, ci, (uint32 *)&valarr[2]); 8060 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_Wr(unit, ci, (uint32 *)&valarr[3]); 8061 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8062 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8063 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_WR_DQ, ci, unit); 8064 sal_sprintf(val_str, "0x%08x", value[0]); 8065 if (soc_mem_config_set(name_str, val_str) < 0) { 8066 return SOC_E_MEMORY; 8067 } 8068 8069 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_Wr(unit, ci, (uint32 *)&valarr[0]); 8070 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_Wr(unit, ci, (uint32 *)&valarr[1]); 8071 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_Wr(unit, ci, (uint32 *)&valarr[2]); 8072 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_Wr(unit, ci, (uint32 *)&valarr[3]); 8073 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8074 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8075 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_Wr(unit, ci, (uint32 *)&valarr[0]); 8076 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_Wr(unit, ci, (uint32 *)&valarr[1]); 8077 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_Wr(unit, ci, (uint32 *)&valarr[2]); 8078 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_Wr(unit, ci, (uint32 *)&valarr[3]); 8079 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8080 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8081 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_Wr(unit, ci, (uint32 *)&valarr[0]); 8082 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_Wr(unit, ci, (uint32 *)&valarr[1]); 8083 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_Wr(unit, ci, (uint32 *)&valarr[2]); 8084 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_Wr(unit, ci, (uint32 *)&valarr[3]); 8085 value[2] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8086 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8087 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_Wr(unit, ci, (uint32 *)&valarr[0]); 8088 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_Wr(unit, ci, (uint32 *)&valarr[1]); 8089 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_Wr(unit, ci, (uint32 *)&valarr[2]); 8090 READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_Wr(unit, ci, (uint32 *)&valarr[3]); 8091 value[3] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8092 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8093 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_WR_DQ_WL0, ci, unit); 8094 sal_sprintf(val_str, "0x%08x,0x%08x,0x%08x,0x%08x", value[0], value[1], value[2], value[3]); 8095 if (soc_mem_config_set(name_str, val_str) < 0) { 8096 return SOC_E_MEMORY; 8097 } 8098 8099 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_Wr(unit, ci, (uint32 *)&valarr[0]); 8100 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_Wr(unit, ci, (uint32 *)&valarr[1]); 8101 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_Wr(unit, ci, (uint32 *)&valarr[2]); 8102 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_Wr(unit, ci, (uint32 *)&valarr[3]); 8103 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8104 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8105 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_Wr(unit, ci, (uint32 *)&valarr[0]); 8106 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_Wr(unit, ci, (uint32 *)&valarr[1]); 8107 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_Wr(unit, ci, (uint32 *)&valarr[2]); 8108 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_Wr(unit, ci, (uint32 *)&valarr[3]); 8109 value[1] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8110 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8111 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_Wr(unit, ci, (uint32 *)&valarr[0]); 8112 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_Wr(unit, ci, (uint32 *)&valarr[1]); 8113 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_Wr(unit, ci, (uint32 *)&valarr[2]); 8114 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_Wr(unit, ci, (uint32 *)&valarr[3]); 8115 value[2] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8116 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8117 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_Wr(unit, ci, (uint32 *)&valarr[0]); 8118 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_Wr(unit, ci, (uint32 *)&valarr[1]); 8119 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_Wr(unit, ci, (uint32 *)&valarr[2]); 8120 READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_Wr(unit, ci, (uint32 *)&valarr[3]); 8121 value[3] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8) | 8122 (OVR_COMPRESS(valarr[2]) << 16) | (OVR_COMPRESS(valarr[3]) << 24); 8123 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_WR_DQ_WL1, ci, unit); 8124 sal_sprintf(val_str, "0x%08x,0x%08x,0x%08x,0x%08x", value[0], value[1], value[2], value[3]); 8125 if (soc_mem_config_set(name_str, val_str) < 0) { 8126 return SOC_E_MEMORY; 8127 } 8128 8129 /* SHMOO_ADDRC: */ 8130 READ_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(unit, ci, (uint32 *)&valarr[0]); 8131 READ_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTLr(unit, ci, (uint32 *)&valarr[1]); 8132 value[0] = OVR_COMPRESS(valarr[0]) | (OVR_COMPRESS(valarr[1]) << 8); 8133 sal_sprintf(name_str, "%s_ci%d.%d", spn_DDR3_TUNE_ADDRC, ci, unit); 8134 sal_sprintf(val_str, "0x%08x", value[0]); 8135 if (soc_mem_config_set(name_str, val_str) < 0) { 8136 return SOC_E_MEMORY; 8137 } 8138 return SOC_E_NONE; 8139 } 8140 8141 #define OVR_EXPAND(_v) (((_v) & 0x3f) | (0x20000) | \ 8142 (((_v)&0x40) ? 0x100 : 0) | \ 8143 (((_v)&0x80) ? 0x10000 : 0)) 8144 8145 int soc_ddr40_shmoo_restorecfg(int unit, int ci) 8146 { 8147 int value[4], valarr[4]; 8148 int ciC; 8149 uint32 error_mask0, error_mask1; 8150 uint32 rval; 8151 8152 ciC = ci & 0xFFFFFFFE; 8153 8154 if(SOC_IS_KATANAX(unit)) { 8155 rval = 0; 8156 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, WFIFO_CTL_CORRECTED_ERROR_DISINTf, 1); 8157 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, WFIFO_CTL_UNCORRECTED_ERROR_DISINTf, 1); 8158 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, RFIFO_CTL_CORRECTED_ERROR_DISINTf, 1); 8159 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, RFIFO_CTL_UNCORRECTED_ERROR_DISINTf, 1); 8160 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, PHY_BL0_RD_FIFO_ERRORf, 1); 8161 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, PHY_BL1_RD_FIFO_ERRORf, 1); 8162 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, RFIFO_OVERFLOW_DISINTf, 1); 8163 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, WB_OVERFLOW_DISINTf, 1); 8164 soc_reg_field_set(unit, CI_ERROR_MASKr, &rval, PHY_READYf, 1); 8165 if(_check_dram(ciC)) { 8166 SOC_IF_ERROR_RETURN(READ_CI_ERROR_MASKr(unit, ciC, &error_mask0)); 8167 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC, rval)); 8168 } 8169 if(_check_dram(ciC + 1)) { 8170 SOC_IF_ERROR_RETURN(READ_CI_ERROR_MASKr(unit, ciC + 1, &error_mask1)); 8171 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC + 1, rval)); 8172 } 8173 } 8174 8175 /* SHMOO_RD_DATA_DLY: */ 8176 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_RD_DATA_DLY,4,value) != 1) { 8177 return SOC_E_CONFIG; 8178 } 8179 valarr[0] = value[0] & 0x7; 8180 valarr[1] = (value[0] >> 8) & 0x7; 8181 WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(unit, ci, valarr[0]); 8182 WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(unit, ci, valarr[1]); 8183 8184 /* SHMOO_RD_EN: */ 8185 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_RD_EN,4,value) != 2) { 8186 return SOC_E_CONFIG; 8187 } 8188 valarr[0] = OVR_EXPAND(value[0]); 8189 valarr[1] = OVR_EXPAND(value[0]>>8); 8190 valarr[2] = OVR_EXPAND(value[0]>>16); 8191 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, valarr[0]); 8192 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, valarr[1]); 8193 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, valarr[2]); 8194 valarr[0] = OVR_EXPAND(value[1]); 8195 valarr[1] = OVR_EXPAND(value[1]>>8); 8196 valarr[2] = OVR_EXPAND(value[1]>>16); 8197 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(unit, ci, valarr[0]); 8198 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(unit, ci, valarr[1]); 8199 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(unit, ci, valarr[2]); 8200 8201 /* SHMOO_RD_DQ : */ 8202 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_RD_DQ_WL0_RP,4,value) != 4) { 8203 return SOC_E_CONFIG; 8204 } 8205 valarr[0] = OVR_EXPAND(value[0]); 8206 valarr[1] = OVR_EXPAND(value[0]>>8); 8207 valarr[2] = OVR_EXPAND(value[0]>>16); 8208 valarr[3] = OVR_EXPAND(value[0]>>24); 8209 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Pr(unit, ci, valarr[0]); 8210 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Pr(unit, ci, valarr[1]); 8211 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Pr(unit, ci, valarr[2]); 8212 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Pr(unit, ci, valarr[3]); 8213 valarr[0] = OVR_EXPAND(value[1]); 8214 valarr[1] = OVR_EXPAND(value[1]>>8); 8215 valarr[2] = OVR_EXPAND(value[1]>>16); 8216 valarr[3] = OVR_EXPAND(value[1]>>24); 8217 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Pr(unit, ci, valarr[0]); 8218 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Pr(unit, ci, valarr[1]); 8219 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Pr(unit, ci, valarr[2]); 8220 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Pr(unit, ci, valarr[3]); 8221 valarr[0] = OVR_EXPAND(value[2]); 8222 valarr[1] = OVR_EXPAND(value[2]>>8); 8223 valarr[2] = OVR_EXPAND(value[2]>>16); 8224 valarr[3] = OVR_EXPAND(value[2]>>24); 8225 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Pr(unit, ci, valarr[0]); 8226 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Pr(unit, ci, valarr[1]); 8227 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Pr(unit, ci, valarr[2]); 8228 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Pr(unit, ci, valarr[3]); 8229 valarr[0] = OVR_EXPAND(value[3]); 8230 valarr[1] = OVR_EXPAND(value[3]>>8); 8231 valarr[2] = OVR_EXPAND(value[3]>>16); 8232 valarr[3] = OVR_EXPAND(value[3]>>24); 8233 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Pr(unit, ci, valarr[0]); 8234 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Pr(unit, ci, valarr[1]); 8235 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Pr(unit, ci, valarr[2]); 8236 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Pr(unit, ci, valarr[3]); 8237 8238 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_RD_DQ_WL1_RP,4,value) != 4) { 8239 return SOC_E_CONFIG; 8240 } 8241 valarr[0] = OVR_EXPAND(value[0]); 8242 valarr[1] = OVR_EXPAND(value[0]>>8); 8243 valarr[2] = OVR_EXPAND(value[0]>>16); 8244 valarr[3] = OVR_EXPAND(value[0]>>24); 8245 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Pr(unit, ci, valarr[0]); 8246 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Pr(unit, ci, valarr[1]); 8247 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Pr(unit, ci, valarr[2]); 8248 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Pr(unit, ci, valarr[3]); 8249 valarr[0] = OVR_EXPAND(value[1]); 8250 valarr[1] = OVR_EXPAND(value[1]>>8); 8251 valarr[2] = OVR_EXPAND(value[1]>>16); 8252 valarr[3] = OVR_EXPAND(value[1]>>24); 8253 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Pr(unit, ci, valarr[0]); 8254 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Pr(unit, ci, valarr[1]); 8255 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Pr(unit, ci, valarr[2]); 8256 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Pr(unit, ci, valarr[3]); 8257 valarr[0] = OVR_EXPAND(value[2]); 8258 valarr[1] = OVR_EXPAND(value[2]>>8); 8259 valarr[2] = OVR_EXPAND(value[2]>>16); 8260 valarr[3] = OVR_EXPAND(value[2]>>24); 8261 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Pr(unit, ci, valarr[0]); 8262 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Pr(unit, ci, valarr[1]); 8263 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Pr(unit, ci, valarr[2]); 8264 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Pr(unit, ci, valarr[3]); 8265 valarr[0] = OVR_EXPAND(value[3]); 8266 valarr[1] = OVR_EXPAND(value[3]>>8); 8267 valarr[2] = OVR_EXPAND(value[3]>>16); 8268 valarr[3] = OVR_EXPAND(value[3]>>24); 8269 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Pr(unit, ci, valarr[0]); 8270 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Pr(unit, ci, valarr[1]); 8271 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Pr(unit, ci, valarr[2]); 8272 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Pr(unit, ci, valarr[3]); 8273 8274 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_RD_DQ_WL0_RN,4,value) != 4) { 8275 return SOC_E_CONFIG; 8276 } 8277 valarr[0] = OVR_EXPAND(value[0]); 8278 valarr[1] = OVR_EXPAND(value[0]>>8); 8279 valarr[2] = OVR_EXPAND(value[0]>>16); 8280 valarr[3] = OVR_EXPAND(value[0]>>24); 8281 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Nr(unit, ci, valarr[0]); 8282 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Nr(unit, ci, valarr[1]); 8283 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Nr(unit, ci, valarr[2]); 8284 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Nr(unit, ci, valarr[3]); 8285 valarr[0] = OVR_EXPAND(value[1]); 8286 valarr[1] = OVR_EXPAND(value[1]>>8); 8287 valarr[2] = OVR_EXPAND(value[1]>>16); 8288 valarr[3] = OVR_EXPAND(value[1]>>24); 8289 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Nr(unit, ci, valarr[0]); 8290 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Nr(unit, ci, valarr[1]); 8291 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Nr(unit, ci, valarr[2]); 8292 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Nr(unit, ci, valarr[3]); 8293 valarr[0] = OVR_EXPAND(value[2]); 8294 valarr[1] = OVR_EXPAND(value[2]>>8); 8295 valarr[2] = OVR_EXPAND(value[2]>>16); 8296 valarr[3] = OVR_EXPAND(value[2]>>24); 8297 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Nr(unit, ci, valarr[0]); 8298 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Nr(unit, ci, valarr[1]); 8299 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Nr(unit, ci, valarr[2]); 8300 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Nr(unit, ci, valarr[3]); 8301 valarr[0] = OVR_EXPAND(value[3]); 8302 valarr[1] = OVR_EXPAND(value[3]>>8); 8303 valarr[2] = OVR_EXPAND(value[3]>>16); 8304 valarr[3] = OVR_EXPAND(value[3]>>24); 8305 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Nr(unit, ci, valarr[0]); 8306 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Nr(unit, ci, valarr[1]); 8307 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Nr(unit, ci, valarr[2]); 8308 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Nr(unit, ci, valarr[3]); 8309 8310 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_RD_DQ_WL1_RN,4,value) != 4) { 8311 return SOC_E_CONFIG; 8312 } 8313 valarr[0] = OVR_EXPAND(value[0]); 8314 valarr[1] = OVR_EXPAND(value[0]>>8); 8315 valarr[2] = OVR_EXPAND(value[0]>>16); 8316 valarr[3] = OVR_EXPAND(value[0]>>24); 8317 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Nr(unit, ci, valarr[0]); 8318 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Nr(unit, ci, valarr[1]); 8319 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Nr(unit, ci, valarr[2]); 8320 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Nr(unit, ci, valarr[3]); 8321 valarr[0] = OVR_EXPAND(value[1]); 8322 valarr[1] = OVR_EXPAND(value[1]>>8); 8323 valarr[2] = OVR_EXPAND(value[1]>>16); 8324 valarr[3] = OVR_EXPAND(value[1]>>24); 8325 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Nr(unit, ci, valarr[0]); 8326 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Nr(unit, ci, valarr[1]); 8327 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Nr(unit, ci, valarr[2]); 8328 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Nr(unit, ci, valarr[3]); 8329 valarr[0] = OVR_EXPAND(value[2]); 8330 valarr[1] = OVR_EXPAND(value[2]>>8); 8331 valarr[2] = OVR_EXPAND(value[2]>>16); 8332 valarr[3] = OVR_EXPAND(value[2]>>24); 8333 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Nr(unit, ci, valarr[0]); 8334 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Nr(unit, ci, valarr[1]); 8335 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Nr(unit, ci, valarr[2]); 8336 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Nr(unit, ci, valarr[3]); 8337 valarr[0] = OVR_EXPAND(value[3]); 8338 valarr[1] = OVR_EXPAND(value[3]>>8); 8339 valarr[2] = OVR_EXPAND(value[3]>>16); 8340 valarr[3] = OVR_EXPAND(value[3]>>24); 8341 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Nr(unit, ci, valarr[0]); 8342 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Nr(unit, ci, valarr[1]); 8343 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Nr(unit, ci, valarr[2]); 8344 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Nr(unit, ci, valarr[3]); 8345 8346 8347 /* SHMOO_RD_DQS: */ 8348 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_RD_DQS,4,value) != 2) { 8349 return SOC_E_CONFIG; 8350 } 8351 valarr[0] = OVR_EXPAND(value[0]); 8352 valarr[1] = OVR_EXPAND(value[0]>>8); 8353 valarr[2] = OVR_EXPAND(value[0]>>16); 8354 valarr[3] = OVR_EXPAND(value[0]>>24); 8355 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, valarr[0]); 8356 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, valarr[1]); 8357 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, valarr[2]); 8358 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, valarr[3]); 8359 valarr[0] = OVR_EXPAND(value[1]); 8360 valarr[1] = OVR_EXPAND(value[1]>>8); 8361 valarr[2] = OVR_EXPAND(value[1]>>16); 8362 valarr[3] = OVR_EXPAND(value[1]>>24); 8363 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(unit, ci, valarr[0]); 8364 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(unit, ci, valarr[1]); 8365 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(unit, ci, valarr[2]); 8366 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(unit, ci, valarr[3]); 8367 8368 /* SHMOO_VREF: */ 8369 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_VREF,2,value) != 1) { 8370 return SOC_E_CONFIG; 8371 } 8372 WRITE_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ci, value[0]); 8373 8374 /* SHMOO_WR_DQ : */ 8375 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_WR_DQ,2,value) != 1) { 8376 return SOC_E_CONFIG; 8377 } 8378 valarr[0] = OVR_EXPAND(value[0]); 8379 valarr[1] = OVR_EXPAND(value[0]>>8); 8380 valarr[2] = OVR_EXPAND(value[0]>>16); 8381 valarr[3] = OVR_EXPAND(value[0]>>24); 8382 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_Wr(unit, ci, valarr[0]); 8383 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_Wr(unit, ci, valarr[1]); 8384 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_Wr(unit, ci, valarr[2]); 8385 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_Wr(unit, ci, valarr[3]); 8386 8387 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_WR_DQ_WL0,4,value) != 4) { 8388 return SOC_E_CONFIG; 8389 } 8390 valarr[0] = OVR_EXPAND(value[0]); 8391 valarr[1] = OVR_EXPAND(value[0]>>8); 8392 valarr[2] = OVR_EXPAND(value[0]>>16); 8393 valarr[3] = OVR_EXPAND(value[0]>>24); 8394 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_Wr(unit, ci, valarr[0]); 8395 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_Wr(unit, ci, valarr[1]); 8396 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_Wr(unit, ci, valarr[2]); 8397 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_Wr(unit, ci, valarr[3]); 8398 valarr[0] = OVR_EXPAND(value[1]); 8399 valarr[1] = OVR_EXPAND(value[1]>>8); 8400 valarr[2] = OVR_EXPAND(value[1]>>16); 8401 valarr[3] = OVR_EXPAND(value[1]>>24); 8402 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_Wr(unit, ci, valarr[0]); 8403 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_Wr(unit, ci, valarr[1]); 8404 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_Wr(unit, ci, valarr[2]); 8405 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_Wr(unit, ci, valarr[3]); 8406 valarr[0] = OVR_EXPAND(value[2]); 8407 valarr[1] = OVR_EXPAND(value[2]>>8); 8408 valarr[2] = OVR_EXPAND(value[2]>>16); 8409 valarr[3] = OVR_EXPAND(value[2]>>24); 8410 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_Wr(unit, ci, valarr[0]); 8411 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_Wr(unit, ci, valarr[1]); 8412 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_Wr(unit, ci, valarr[2]); 8413 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_Wr(unit, ci, valarr[3]); 8414 valarr[0] = OVR_EXPAND(value[3]); 8415 valarr[1] = OVR_EXPAND(value[3]>>8); 8416 valarr[2] = OVR_EXPAND(value[3]>>16); 8417 valarr[3] = OVR_EXPAND(value[3]>>24); 8418 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_Wr(unit, ci, valarr[0]); 8419 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_Wr(unit, ci, valarr[1]); 8420 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_Wr(unit, ci, valarr[2]); 8421 WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_Wr(unit, ci, valarr[3]); 8422 8423 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_WR_DQ_WL1,4,value) != 4) { 8424 return SOC_E_CONFIG; 8425 } 8426 valarr[0] = OVR_EXPAND(value[0]); 8427 valarr[1] = OVR_EXPAND(value[0]>>8); 8428 valarr[2] = OVR_EXPAND(value[0]>>16); 8429 valarr[3] = OVR_EXPAND(value[0]>>24); 8430 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_Wr(unit, ci, valarr[0]); 8431 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_Wr(unit, ci, valarr[1]); 8432 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_Wr(unit, ci, valarr[2]); 8433 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_Wr(unit, ci, valarr[3]); 8434 valarr[0] = OVR_EXPAND(value[1]); 8435 valarr[1] = OVR_EXPAND(value[1]>>8); 8436 valarr[2] = OVR_EXPAND(value[1]>>16); 8437 valarr[3] = OVR_EXPAND(value[1]>>24); 8438 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_Wr(unit, ci, valarr[0]); 8439 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_Wr(unit, ci, valarr[1]); 8440 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_Wr(unit, ci, valarr[2]); 8441 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_Wr(unit, ci, valarr[3]); 8442 valarr[0] = OVR_EXPAND(value[2]); 8443 valarr[1] = OVR_EXPAND(value[2]>>8); 8444 valarr[2] = OVR_EXPAND(value[2]>>16); 8445 valarr[3] = OVR_EXPAND(value[2]>>24); 8446 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_Wr(unit, ci, valarr[0]); 8447 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_Wr(unit, ci, valarr[1]); 8448 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_Wr(unit, ci, valarr[2]); 8449 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_Wr(unit, ci, valarr[3]); 8450 valarr[0] = OVR_EXPAND(value[3]); 8451 valarr[1] = OVR_EXPAND(value[3]>>8); 8452 valarr[2] = OVR_EXPAND(value[3]>>16); 8453 valarr[3] = OVR_EXPAND(value[3]>>24); 8454 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_Wr(unit, ci, valarr[0]); 8455 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_Wr(unit, ci, valarr[1]); 8456 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_Wr(unit, ci, valarr[2]); 8457 WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_Wr(unit, ci, valarr[3]); 8458 8459 /* SHMOO_ADDRC: */ 8460 if (soc_property_ci_get_csv(unit, ci, spn_DDR3_TUNE_ADDRC,2,value) != 1) { 8461 return SOC_E_CONFIG; 8462 } 8463 valarr[0] = OVR_EXPAND(value[0]); 8464 valarr[1] = OVR_EXPAND(value[0]>>8); 8465 WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(unit, ci, valarr[0]); 8466 WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTLr(unit, ci, valarr[1]); 8467 8468 /* Clear the FIFO error state */ 8469 WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(unit, ci, 0); 8470 WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(unit, ci, 0); 8471 8472 if(SOC_IS_KATANAX(unit)) { 8473 rval = 0; 8474 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_CORRECTED_ERRORf, 1); 8475 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_UNCORRECTED_ERRORf, 1); 8476 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_CORRECTED_ERRORf, 1); 8477 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_UNCORRECTED_ERRORf, 1); 8478 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_BL0_RD_FIFO_ERRORf, 1); 8479 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_BL1_RD_FIFO_ERRORf, 1); 8480 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_OVERFLOWf, 1); 8481 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_OVERFLOWf, 1); 8482 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_READY_EVENTf, 1); 8483 if(_check_dram(ciC)) { 8484 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC, error_mask0)); 8485 SOC_IF_ERROR_RETURN(WRITE_CI_ERRORr(unit, ciC, rval)); 8486 } 8487 if(_check_dram(ciC + 1)) { 8488 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, ciC + 1, error_mask1)); 8489 SOC_IF_ERROR_RETURN(WRITE_CI_ERRORr(unit, ciC + 1, rval)); 8490 } 8491 } 8492 8493 return SOC_E_NONE; 8494 } 8495 8496 8497 #endif /* DDR3 Support */