shmoo_and28.c (272649B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * 28nm PHY Support 8 */ 9 #include <shared/bsl.h> 10 11 #include <sal/core/boot.h> 12 #include <sal/core/libc.h> 13 #include <shared/alloc.h> 14 #include <soc/memtune.h> 15 16 #include <soc/drv.h> 17 #include <soc/debug.h> 18 #include <soc/cm.h> 19 #ifdef BCM_CMICM_SUPPORT 20 #include <soc/cmicm.h> 21 #endif 22 23 #ifdef BCM_AND28_SUPPORT 24 #include <soc/shmoo_and28.h> 25 #include <soc/phy/ddr34.h> 26 27 static uint32 SHMOO_AND28_PHY_TYPE = SHMOO_AND28_PHY_TYPE_RSVP; 28 static uint32 DDR34_PHY_REGS_TABLE(DDR34_PHY_MAX_REG_INDEX); 29 static uint32 DDR34_PHY_FIELDS_TABLE(DDR34_PHY_MAX_FIELD_INDEX, 0); 30 31 static and28_shmoo_dram_info_t shmoo_dram_info = 32 { 33 /*.ctl_type =*/ 0, 34 /*.dram_type =*/ 0, 35 /*.dram_bitmap =*/ 0x00000000, 36 /*.interface_bitwidth =*/ 0, 37 /*.split_bus =*/ 0, 38 /*.num_columns =*/ -1, 39 /*.num_rows =*/ -1, 40 /*.num_banks =*/ -1, 41 /*.num_bank_groups =*/ -1, 42 /*.data_rate_mbps =*/ -1, 43 /*.ref_clk_mhz =*/ -1, 44 /*.refi =*/ 0, 45 /*.command_parity_latency =*/ 0, 46 /*.sim_system_mode =*/ 0 47 }; 48 49 soc_and28_phy_reg_read_t soc_and28_phy_reg_read = NULL; 50 soc_and28_phy_reg_write_t soc_and28_phy_reg_write = NULL; 51 soc_and28_phy_reg_modify_t soc_and28_phy_reg_modify = NULL; 52 static _shmoo_and28_drc_bist_conf_set_t _shmoo_and28_drc_bist_conf_set = NULL; 53 static _shmoo_and28_drc_bist_err_cnt_t _shmoo_and28_drc_bist_err_cnt = NULL; 54 static _shmoo_and28_drc_dram_init_t _shmoo_and28_drc_dram_init = NULL; 55 56 const uint32 shmoo_order_and28_ddr3[SHMOO_AND28_DDR3_SEQUENCE_COUNT] = 57 { 58 SHMOO_AND28_RD_EN, 59 SHMOO_AND28_RD_EXTENDED, 60 SHMOO_AND28_WR_EXTENDED, 61 SHMOO_AND28_ADDR_EXTENDED, 62 SHMOO_AND28_CTRL_EXTENDED 63 }; 64 65 const uint32 shmoo_order_and28_ddr3l[SHMOO_AND28_DDR3L_SEQUENCE_COUNT] = 66 { 67 SHMOO_AND28_RD_EN, 68 SHMOO_AND28_RD_EXTENDED, 69 SHMOO_AND28_WR_EXTENDED, 70 SHMOO_AND28_ADDR_EXTENDED, 71 SHMOO_AND28_CTRL_EXTENDED 72 }; 73 74 const uint32 shmoo_order_and28_ddr4[SHMOO_AND28_DDR4_SEQUENCE_COUNT] = 75 { 76 SHMOO_AND28_RD_EN, 77 SHMOO_AND28_RD_EXTENDED, 78 SHMOO_AND28_WR_EXTENDED, 79 SHMOO_AND28_ADDR_EXTENDED, 80 SHMOO_AND28_CTRL_EXTENDED 81 }; 82 83 uint32 84 _shmoo_and28_validate_config(void) 85 { 86 return ( 87 (shmoo_dram_info.ctl_type != 0) 88 && (shmoo_dram_info.dram_type != 0) 89 /* && (shmoo_dram_info.dram_bitmap != 0) */ 90 && (shmoo_dram_info.interface_bitwidth != 0) 91 /* && (shmoo_dram_info.split_bus != 0) */ 92 && (shmoo_dram_info.num_columns != -1) 93 && (shmoo_dram_info.num_rows != -1) 94 && (shmoo_dram_info.num_banks != -1) 95 && (shmoo_dram_info.num_bank_groups != -1) 96 && (shmoo_dram_info.data_rate_mbps != -1) 97 && (shmoo_dram_info.ref_clk_mhz != -1) 98 /* && (shmoo_dram_info.refi != 0) */ 99 /* && (shmoo_dram_info.command_parity_latency != 0) */ 100 /* && (shmoo_dram_info.sim_system_mode != 0) */ 101 ); 102 } 103 104 uint32 105 _shmoo_and28_validate_cbi(void) 106 { 107 return ( 108 (soc_and28_phy_reg_read != NULL) 109 && (soc_and28_phy_reg_write != NULL) 110 && (soc_and28_phy_reg_modify != NULL) 111 && (_shmoo_and28_drc_bist_conf_set != NULL) 112 && (_shmoo_and28_drc_bist_err_cnt != NULL) 113 && (_shmoo_and28_drc_dram_init != NULL) 114 ); 115 } 116 117 uint32 118 _shmoo_and28_check_dram(int phy_ndx) 119 { 120 if(shmoo_dram_info.interface_bitwidth == 32) 121 { 122 return ((shmoo_dram_info.dram_bitmap >> phy_ndx) & 0x1); 123 } 124 else 125 { 126 return ((shmoo_dram_info.dram_bitmap >> (phy_ndx << 1)) & 0x3); 127 } 128 } 129 130 STATIC int 131 _and28_initialize_bist(int unit, int phy_ndx, int bit, and28_shmoo_container_t *scPtr, and28_bist_info_t *biPtr) 132 { 133 switch((*scPtr).shmooType) 134 { 135 case SHMOO_AND28_RD_EN: 136 (*biPtr).write_weight = 255; 137 (*biPtr).read_weight = 255; 138 (*biPtr).bist_timer_us = 0; 139 (*biPtr).bist_num_actions = 51510; 140 (*biPtr).bist_start_address = 0x00000000; 141 (*biPtr).bist_end_address = 0x00FFFFFF; 142 (*biPtr).mpr_mode = 0; 143 (*biPtr).prbs_mode = 1; 144 break; 145 case SHMOO_AND28_RD_EXTENDED: 146 (*biPtr).write_weight = 255; 147 (*biPtr).read_weight = 255; 148 (*biPtr).bist_timer_us = 0; 149 (*biPtr).bist_num_actions = 51510; 150 (*biPtr).bist_start_address = 0x00000000; 151 (*biPtr).bist_end_address = 0x00FFFFFF; 152 (*biPtr).mpr_mode = 0; 153 (*biPtr).prbs_mode = 1; 154 break; 155 case SHMOO_AND28_WR_EXTENDED: 156 (*biPtr).write_weight = 255; 157 (*biPtr).read_weight = 255; 158 (*biPtr).bist_timer_us = 0; 159 (*biPtr).bist_num_actions = 51510; 160 (*biPtr).bist_start_address = 0x00000000; 161 (*biPtr).bist_end_address = 0x00FFFFFF; 162 (*biPtr).mpr_mode = 0; 163 (*biPtr).prbs_mode = 1; 164 break; 165 case SHMOO_AND28_ADDR_EXTENDED: 166 (*biPtr).write_weight = 255; 167 (*biPtr).read_weight = 255; 168 (*biPtr).bist_timer_us = 0; 169 (*biPtr).bist_num_actions = 51510; 170 (*biPtr).bist_start_address = 0x00000000; 171 (*biPtr).bist_end_address = 0x00FFFFFF; 172 (*biPtr).mpr_mode = 0; 173 (*biPtr).prbs_mode = 1; 174 break; 175 case SHMOO_AND28_CTRL_EXTENDED: 176 (*biPtr).write_weight = 255; 177 (*biPtr).read_weight = 255; 178 (*biPtr).bist_timer_us = 0; 179 (*biPtr).bist_num_actions = 51510; 180 (*biPtr).bist_start_address = 0x00000000; 181 (*biPtr).bist_end_address = 0x00FFFFFF; 182 (*biPtr).mpr_mode = 0; 183 (*biPtr).prbs_mode = 1; 184 break; 185 default: 186 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 187 return SOC_E_FAIL; 188 } 189 return SOC_E_NONE; 190 } 191 192 STATIC int 193 _and28_run_bist(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, and28_bist_info_t *biPtr, and28_shmoo_error_array_t *seaPtr) 194 { 195 and28_bist_err_cnt_t be; 196 197 switch((*scPtr).shmooType) 198 { 199 case SHMOO_AND28_RD_EN: 200 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_conf_set(unit, phy_ndx, (*biPtr))); 201 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_err_cnt(unit, phy_ndx, &be)); 202 203 (*seaPtr)[0] = be.bist_err_occur; 204 break; 205 case SHMOO_AND28_RD_EXTENDED: 206 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_conf_set(unit, phy_ndx, (*biPtr))); 207 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_err_cnt(unit, phy_ndx, &be)); 208 209 (*seaPtr)[0] = be.bist_err_occur; 210 break; 211 case SHMOO_AND28_WR_EXTENDED: 212 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_conf_set(unit, phy_ndx, (*biPtr))); 213 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_err_cnt(unit, phy_ndx, &be)); 214 215 (*seaPtr)[0] = be.bist_err_occur; 216 break; 217 case SHMOO_AND28_ADDR_EXTENDED: 218 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_conf_set(unit, phy_ndx, (*biPtr))); 219 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_err_cnt(unit, phy_ndx, &be)); 220 221 (*seaPtr)[0] = be.bist_err_occur; 222 break; 223 case SHMOO_AND28_CTRL_EXTENDED: 224 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_conf_set(unit, phy_ndx, (*biPtr))); 225 SOC_IF_ERROR_RETURN(_shmoo_and28_drc_bist_err_cnt(unit, phy_ndx, &be)); 226 227 (*seaPtr)[0] = be.bist_err_occur; 228 break; 229 default: 230 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 231 return SOC_E_FAIL; 232 } 233 234 return SOC_E_NONE; 235 } 236 237 STATIC int 238 _shmoo_and28_rd_en(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 239 { 240 uint32 x; 241 uint32 y; 242 uint32 jump; 243 uint32 yCapMin; 244 uint32 yCapMax; 245 uint32 xStart; 246 uint32 data; 247 and28_bist_info_t bi; 248 and28_shmoo_error_array_t sea; 249 250 yCapMin = 0; 251 yCapMax = (*scPtr).sizeY; 252 jump = (*scPtr).yJump; 253 xStart = 0; 254 255 (*scPtr).engageUIshift = 0; 256 (*scPtr).yCapMin = yCapMin; 257 (*scPtr).yCapMax = yCapMax; 258 (*scPtr).shmooType = SHMOO_AND28_RD_EN; 259 260 _and28_initialize_bist(unit, phy_ndx, -1, scPtr, &bi); 261 262 for(y = yCapMin; y < yCapMax; y++) 263 { 264 data = 0; 265 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1); 266 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, y << jump); 267 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 268 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 269 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 270 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 271 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 272 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 273 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 274 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 275 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 276 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 277 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 278 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 279 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 280 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 281 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 282 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 283 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 284 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 285 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 286 { 287 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 288 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 289 } 290 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 291 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 292 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 293 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 294 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 295 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 296 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 297 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 298 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 299 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 300 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 301 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 302 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 303 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 304 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 305 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 306 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 307 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 308 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 309 { 310 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 311 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 312 } 313 314 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 315 { 316 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 317 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 318 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 319 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 320 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 321 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 322 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 323 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 324 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 325 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 326 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 327 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 328 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 329 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 330 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 331 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 332 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 333 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 334 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 335 { 336 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 337 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 338 } 339 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 340 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 341 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 342 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 343 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 344 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 345 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 346 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 347 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 348 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 349 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 350 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 351 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 352 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 353 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 354 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 355 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 356 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 357 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 358 { 359 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 360 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 361 } 362 } 363 364 for(x = 0; x < (*scPtr).sizeX; x++) 365 { 366 data = 0; 367 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 368 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, x); 369 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 370 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 371 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 372 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 373 374 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 375 { 376 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 377 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 378 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 379 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 380 } 381 382 data = 0; 383 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 384 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 385 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 386 387 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 388 { 389 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 390 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 391 } 392 393 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 394 395 _and28_run_bist(unit, phy_ndx, scPtr, &bi, &sea); 396 397 (*scPtr).result2D[x + xStart] = sea[0]; 398 } 399 400 xStart += (*scPtr).sizeX; 401 } 402 403 return SOC_E_NONE; 404 } 405 406 STATIC int 407 _shmoo_and28_wr_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 408 { 409 uint32 x; 410 uint32 data; 411 and28_bist_info_t bi; 412 and28_shmoo_error_array_t sea; 413 414 (*scPtr).engageUIshift = 0; 415 (*scPtr).sizeY = 1; 416 (*scPtr).yCapMin = 0; 417 (*scPtr).yCapMax = 1; 418 (*scPtr).shmooType = SHMOO_AND28_WR_EXTENDED; 419 420 _and28_initialize_bist(unit, phy_ndx, -1, scPtr, &bi); 421 422 for(x = 0; x < (*scPtr).sizeX; x++) 423 { 424 data = 0; 425 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1); 426 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, x); 427 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 428 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 429 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 430 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 431 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 432 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 433 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 434 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 435 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 436 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 437 { 438 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 439 } 440 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 441 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 442 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 443 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 444 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 445 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 446 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 447 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 448 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 449 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 450 { 451 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 452 } 453 454 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 455 { 456 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 457 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 458 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 459 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 460 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 461 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 462 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 463 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 464 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 465 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 466 { 467 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 468 } 469 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 470 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 471 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 472 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 473 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 474 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 475 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 476 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 477 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 478 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 479 { 480 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 481 } 482 } 483 484 data = 0; 485 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 486 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 487 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 488 489 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 490 { 491 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 492 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 493 } 494 495 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 496 497 _and28_run_bist(unit, phy_ndx, scPtr, &bi, &sea); 498 499 (*scPtr).result2D[x] = sea[0]; 500 } 501 502 return SOC_E_NONE; 503 } 504 505 int 506 _shmoo_and28_rd_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 507 { 508 uint32 x; 509 uint32 y; 510 uint32 yCapMin; 511 uint32 yCapMax; 512 uint32 xStart; 513 uint32 data, temp; 514 uint32 rd_dqs_pos0 = 0, rd_dqs_pos1 = 0, rd_en_pos0 = 0, rd_en_pos1 = 0, rd_dqs_delta0 = 0, rd_dqs_delta1 = 0; 515 uint32 rd_dq_fail_count0 = 0, rd_dq_fail_count1 = 0; 516 uint32 rd_dqs_pos2 = 0, rd_dqs_pos3 = 0, rd_en_pos2 = 0, rd_en_pos3 = 0, rd_dqs_delta2 = 0, rd_dqs_delta3 = 0; 517 uint32 rd_dq_fail_count2 = 0, rd_dq_fail_count3 = 0; 518 and28_bist_info_t bi; 519 and28_shmoo_error_array_t sea; 520 521 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 522 { 523 yCapMin = 28; 524 yCapMax = 61; 525 } 526 else 527 { 528 yCapMin = 16; 529 yCapMax = 49; 530 } 531 xStart = 0; 532 533 (*scPtr).engageUIshift = 0; 534 (*scPtr).sizeY = SHMOO_AND28_MAX_VREF_RANGE; 535 (*scPtr).yCapMin = yCapMin; 536 (*scPtr).yCapMax = yCapMax; 537 (*scPtr).yJump = 0; 538 (*scPtr).shmooType = SHMOO_AND28_RD_EXTENDED; 539 540 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 541 rd_dqs_pos0 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP); 542 543 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 544 rd_dqs_pos1 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP); 545 546 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 547 { 548 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 549 rd_dqs_pos2 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP); 550 551 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 552 rd_dqs_pos3 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP); 553 } 554 555 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 556 rd_en_pos0 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 557 558 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 559 rd_en_pos1 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 560 561 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 562 { 563 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 564 rd_en_pos2 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 565 566 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 567 rd_en_pos3 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 568 } 569 570 _and28_initialize_bist(unit, phy_ndx, -1, scPtr, &bi); 571 572 x = 0; 573 data = 0; 574 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1); 575 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, x); 576 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 577 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 578 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 579 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 580 581 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 582 { 583 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 584 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 585 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 586 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 587 } 588 589 rd_dqs_delta0 = x - rd_dqs_pos0; 590 rd_dqs_delta1 = x - rd_dqs_pos1; 591 592 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 593 { 594 rd_dqs_delta2 = x - rd_dqs_pos2; 595 rd_dqs_delta3 = x - rd_dqs_pos3; 596 } 597 598 temp = rd_en_pos0 + rd_dqs_delta0; 599 data = 0; 600 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 601 if(temp & 0x80000000) 602 { 603 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 604 } 605 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 606 { 607 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 608 } 609 else 610 { 611 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 612 } 613 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 614 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 615 616 temp = rd_en_pos1 + rd_dqs_delta1; 617 data = 0; 618 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 619 if(temp & 0x80000000) 620 { 621 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 622 } 623 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 624 { 625 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 626 } 627 else 628 { 629 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 630 } 631 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 632 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 633 634 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 635 { 636 temp = rd_en_pos2 + rd_dqs_delta2; 637 data = 0; 638 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 639 if(temp & 0x80000000) 640 { 641 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 642 } 643 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 644 { 645 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 646 } 647 else 648 { 649 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 650 } 651 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 652 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 653 654 temp = rd_en_pos3 + rd_dqs_delta3; 655 data = 0; 656 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 657 if(temp & 0x80000000) 658 { 659 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 660 } 661 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 662 { 663 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 664 } 665 else 666 { 667 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 668 } 669 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 670 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 671 } 672 673 rd_dq_fail_count0 = 0; 674 rd_dq_fail_count1 = 0; 675 676 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 677 { 678 rd_dq_fail_count2 = 0; 679 rd_dq_fail_count3 = 0; 680 } 681 682 for(x = 0; x < (*scPtr).sizeX; x++) 683 { 684 data = 0; 685 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1); 686 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, x); 687 if(rd_dq_fail_count0 <= SHMOO_AND28_RD_DQ_FAIL_CAP) 688 { 689 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 690 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 691 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 692 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 693 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 694 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 695 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 696 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 697 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 698 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 699 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 700 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 701 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 702 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 703 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 704 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 705 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 706 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 707 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 708 { 709 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 710 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 711 } 712 } 713 if(rd_dq_fail_count1 <= SHMOO_AND28_RD_DQ_FAIL_CAP) 714 { 715 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 716 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 717 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 718 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 719 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 720 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 721 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 722 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 723 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 724 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 725 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 726 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 727 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 728 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 729 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 730 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 731 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 732 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 733 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 734 { 735 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 736 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 737 } 738 } 739 740 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 741 { 742 if(rd_dq_fail_count2 <= SHMOO_AND28_RD_DQ_FAIL_CAP) 743 { 744 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 745 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 746 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 747 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 748 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 749 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 750 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 751 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 752 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 753 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 754 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 755 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 756 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 757 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 758 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 759 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 760 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 761 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 762 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 763 { 764 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 765 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 766 } 767 } 768 if(rd_dq_fail_count3 <= SHMOO_AND28_RD_DQ_FAIL_CAP) 769 { 770 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 771 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 772 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 773 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 774 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 775 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 776 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 777 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 778 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 779 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 780 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 781 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 782 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 783 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 784 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 785 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 786 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 787 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 788 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 789 { 790 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 791 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 792 } 793 } 794 } 795 data = 0; 796 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 797 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 798 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 799 800 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 801 { 802 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 803 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 804 } 805 806 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 807 808 _and28_run_bist(unit, phy_ndx, scPtr, &bi, &sea); 809 810 if((sea[0] & 0x000000FF) == 0x000000FF) 811 { 812 rd_dq_fail_count0++; 813 } 814 if((sea[0] & 0x0000FF00) == 0x0000FF00) 815 { 816 rd_dq_fail_count1++; 817 } 818 819 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 820 { 821 if((sea[0] & 0x00FF0000) == 0x00FF0000) 822 { 823 rd_dq_fail_count2++; 824 } 825 if((sea[0] & 0xFF000000) == 0xFF000000) 826 { 827 rd_dq_fail_count3++; 828 } 829 } 830 831 if((rd_dq_fail_count0 > SHMOO_AND28_RD_DQ_FAIL_CAP) && (rd_dq_fail_count1 > SHMOO_AND28_RD_DQ_FAIL_CAP)) 832 { 833 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 834 { 835 if((rd_dq_fail_count2 > SHMOO_AND28_RD_DQ_FAIL_CAP) && (rd_dq_fail_count3 > SHMOO_AND28_RD_DQ_FAIL_CAP)) 836 { 837 break; 838 } 839 } 840 else 841 { 842 break; 843 } 844 } 845 } 846 847 for(y = yCapMin; y < yCapMax; y++) 848 { 849 READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, &data); 850 /* DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, y); */ 851 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, y); 852 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, data); 853 854 for(x = 0; x < (*scPtr).sizeX; x++) 855 { 856 data = 0; 857 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1); 858 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, x); 859 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 860 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 861 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 862 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 863 864 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 865 { 866 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 867 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 868 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 869 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 870 } 871 872 rd_dqs_delta0 = x - rd_dqs_pos0; 873 rd_dqs_delta1 = x - rd_dqs_pos1; 874 875 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 876 { 877 rd_dqs_delta2 = x - rd_dqs_pos2; 878 rd_dqs_delta3 = x - rd_dqs_pos3; 879 } 880 881 temp = rd_en_pos0 + rd_dqs_delta0; 882 data = 0; 883 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 884 if(temp & 0x80000000) 885 { 886 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 887 } 888 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 889 { 890 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 891 } 892 else 893 { 894 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 895 } 896 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 897 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 898 899 temp = rd_en_pos1 + rd_dqs_delta1; 900 data = 0; 901 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 902 if(temp & 0x80000000) 903 { 904 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 905 } 906 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 907 { 908 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 909 } 910 else 911 { 912 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 913 } 914 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 915 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 916 917 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 918 { 919 temp = rd_en_pos2 + rd_dqs_delta2; 920 data = 0; 921 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 922 if(temp & 0x80000000) 923 { 924 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 925 } 926 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 927 { 928 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 929 } 930 else 931 { 932 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 933 } 934 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 935 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 936 937 temp = rd_en_pos3 + rd_dqs_delta3; 938 data = 0; 939 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 940 if(temp & 0x80000000) 941 { 942 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 943 } 944 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 945 { 946 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 947 } 948 else 949 { 950 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 951 } 952 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 953 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 954 } 955 956 data = 0; 957 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 958 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 959 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 960 961 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 962 { 963 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 964 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 965 } 966 967 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 968 969 _and28_run_bist(unit, phy_ndx, scPtr, &bi, &sea); 970 971 (*scPtr).result2D[x + xStart] = sea[0]; 972 } 973 974 xStart += (*scPtr).sizeX; 975 } 976 977 return SOC_E_NONE; 978 } 979 980 STATIC int 981 _shmoo_and28_addr_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 982 { 983 uint32 x; 984 uint32 data; 985 and28_bist_info_t bi; 986 and28_shmoo_error_array_t sea; 987 988 (*scPtr).engageUIshift = 0; 989 (*scPtr).sizeY = 1; 990 (*scPtr).yCapMin = 0; 991 (*scPtr).yCapMax = 1; 992 (*scPtr).shmooType = SHMOO_AND28_ADDR_EXTENDED; 993 994 _and28_initialize_bist(unit, phy_ndx, -1, scPtr, &bi); 995 996 for(x = 0; x < (*scPtr).sizeX; x++) 997 { 998 data = 0; 999 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1); 1000 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, x); 1001 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(unit, phy_ndx, data); 1002 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(unit, phy_ndx, data); 1003 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(unit, phy_ndx, data); 1004 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(unit, phy_ndx, data); 1005 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(unit, phy_ndx, data); 1006 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(unit, phy_ndx, data); 1007 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(unit, phy_ndx, data); 1008 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(unit, phy_ndx, data); 1009 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(unit, phy_ndx, data); 1010 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(unit, phy_ndx, data); 1011 1012 data = 0; 1013 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 1014 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 1015 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 1016 1017 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1018 { 1019 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 1020 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 1021 } 1022 1023 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1024 1025 _and28_run_bist(unit, phy_ndx, scPtr, &bi, &sea); 1026 1027 (*scPtr).result2D[x] = sea[0]; 1028 } 1029 1030 return SOC_E_NONE; 1031 } 1032 1033 STATIC int 1034 _shmoo_and28_ctrl_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 1035 { 1036 uint32 x; 1037 uint32 data; 1038 and28_bist_info_t bi; 1039 and28_shmoo_error_array_t sea; 1040 1041 (*scPtr).engageUIshift = 0; 1042 (*scPtr).sizeY = 1; 1043 (*scPtr).yCapMin = 0; 1044 (*scPtr).yCapMax = 1; 1045 (*scPtr).shmooType = SHMOO_AND28_CTRL_EXTENDED; 1046 1047 _and28_initialize_bist(unit, phy_ndx, -1, scPtr, &bi); 1048 1049 for(x = 0; x < (*scPtr).sizeX; x++) 1050 { 1051 data = 0; 1052 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD10, FORCE, 1); 1053 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD10, VDL_STEP, x); 1054 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(unit, phy_ndx, data); 1055 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(unit, phy_ndx, data); 1056 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(unit, phy_ndx, data); 1057 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(unit, phy_ndx, data); 1058 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(unit, phy_ndx, data); 1059 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(unit, phy_ndx, data); 1060 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(unit, phy_ndx, data); 1061 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(unit, phy_ndx, data); 1062 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(unit, phy_ndx, data); 1063 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(unit, phy_ndx, data); 1064 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(unit, phy_ndx, data); 1065 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(unit, phy_ndx, data); 1066 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(unit, phy_ndx, data); 1067 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(unit, phy_ndx, data); 1068 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(unit, phy_ndx, data); 1069 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(unit, phy_ndx, data); 1070 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(unit, phy_ndx, data); 1071 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(unit, phy_ndx, data); 1072 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(unit, phy_ndx, data); 1073 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(unit, phy_ndx, data); 1074 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(unit, phy_ndx, data); 1075 1076 data = 0; 1077 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 1078 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 1079 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 1080 1081 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1082 { 1083 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 1084 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 1085 } 1086 1087 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1088 1089 _and28_run_bist(unit, phy_ndx, scPtr, &bi, &sea); 1090 1091 (*scPtr).result2D[x] = sea[0]; 1092 } 1093 1094 return SOC_E_NONE; 1095 } 1096 1097 STATIC int 1098 _shmoo_and28_do(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 1099 { 1100 switch((*scPtr).shmooType) 1101 { 1102 case SHMOO_AND28_RD_EN: 1103 return _shmoo_and28_rd_en(unit, phy_ndx, scPtr); 1104 case SHMOO_AND28_RD_EXTENDED: 1105 return _shmoo_and28_rd_extended(unit, phy_ndx, scPtr); 1106 case SHMOO_AND28_WR_EXTENDED: 1107 return _shmoo_and28_wr_extended(unit, phy_ndx, scPtr); 1108 case SHMOO_AND28_ADDR_EXTENDED: 1109 return _shmoo_and28_addr_extended(unit, phy_ndx, scPtr); 1110 case SHMOO_AND28_CTRL_EXTENDED: 1111 if(!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED) 1112 { 1113 return _shmoo_and28_ctrl_extended(unit, phy_ndx, scPtr); 1114 } 1115 break; 1116 default: 1117 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 1118 return SOC_E_FAIL; 1119 } 1120 return SOC_E_NONE; 1121 } 1122 1123 STATIC int 1124 _and28_calib_2D(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 calibMode, uint32 calibPos) 1125 { 1126 uint32 x; 1127 uint32 y; 1128 uint32 xStart; 1129 uint32 sizeX; 1130 uint32 calibStart; 1131 uint32 yCapMin; 1132 uint32 yCapMax; 1133 uint32 i; 1134 uint32 iter; 1135 uint32 shiftAmount; 1136 uint32 dataMask; 1137 int32 passStart; 1138 int32 failStart; 1139 int32 passStartSeen; 1140 int32 failStartSeen; 1141 int32 passLength; 1142 int32 maxPassStart; 1143 int32 maxPassLength; 1144 int32 maxMidPointX; 1145 uint32 maxPassLengthArray[SHMOO_AND28_WORD]; 1146 1147 xStart = 0; 1148 sizeX = (*scPtr).sizeX; 1149 calibStart = (*scPtr).calibStart; 1150 yCapMin = (*scPtr).yCapMin; 1151 yCapMax = (*scPtr).yCapMax; 1152 1153 switch(calibMode) 1154 { 1155 case SHMOO_AND28_BIT: 1156 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 1157 { 1158 iter = shmoo_dram_info.interface_bitwidth << 1; 1159 } 1160 else 1161 { 1162 iter = shmoo_dram_info.interface_bitwidth; 1163 } 1164 shiftAmount = 0; 1165 dataMask = 0x1; 1166 break; 1167 case SHMOO_AND28_BYTE: 1168 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 1169 { 1170 iter = shmoo_dram_info.interface_bitwidth >> 2; 1171 } 1172 else 1173 { 1174 iter = shmoo_dram_info.interface_bitwidth >> 3; 1175 } 1176 shiftAmount = 3; 1177 dataMask = 0xFF; 1178 break; 1179 case SHMOO_AND28_HALFWORD: 1180 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 1181 { 1182 iter = shmoo_dram_info.interface_bitwidth >> 3; 1183 } 1184 else 1185 { 1186 iter = shmoo_dram_info.interface_bitwidth >> 4; 1187 } 1188 shiftAmount = 4; 1189 dataMask = 0xFFFF; 1190 break; 1191 case SHMOO_AND28_WORD: 1192 iter = 1; 1193 shiftAmount = 5; 1194 if(shmoo_dram_info.split_bus && !(_shmoo_and28_check_dram(phy_ndx) > 1)) 1195 { 1196 dataMask = 0x0000FFFF; 1197 } 1198 else 1199 { 1200 dataMask = 0xFFFFFFFF; 1201 } 1202 break; 1203 default: 1204 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported 2D calibration mode: %02lu\n"), (long unsigned int)calibMode)); 1205 return SOC_E_FAIL; 1206 } 1207 1208 for(i = 0; i < iter; i++) 1209 { 1210 (*scPtr).resultData[i] = 0; 1211 maxPassLengthArray[i] = 0; 1212 } 1213 1214 for(y = yCapMin; y < yCapMax; y++) 1215 { 1216 for(i = 0; i < iter; i++) 1217 { 1218 passStart = -1; 1219 failStart = -1; 1220 passLength = -1; 1221 passStartSeen = -1; 1222 failStartSeen = -1; 1223 maxPassStart = -2; 1224 maxPassLength = -2; 1225 maxMidPointX = -2; 1226 for(x = calibStart; x < sizeX; x++) 1227 { 1228 if(((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask) 1229 { /* FAIL */ 1230 if(failStart < 0) { 1231 failStart = x; 1232 if(maxPassLength < passLength) 1233 { 1234 maxPassStart = passStart; 1235 maxPassLength = passLength; 1236 } 1237 passStart = -1; 1238 passLength = -1; 1239 if((failStartSeen < 0) && (maxPassLength > 0)) 1240 { 1241 failStartSeen = x; 1242 } 1243 } 1244 } 1245 else 1246 { /* PASS */ 1247 if(passStart < 0) 1248 { 1249 passStart = x; 1250 passLength = 1; 1251 failStart = -1; 1252 if((passStartSeen < 0) && (passLength < x)) 1253 { 1254 passStartSeen = x; 1255 } 1256 } 1257 else 1258 { 1259 passLength++; 1260 } 1261 1262 if(x == sizeX - 1) 1263 { 1264 if(maxPassLength < passLength) 1265 { 1266 maxPassStart = passStart; 1267 maxPassLength = passLength; 1268 } 1269 } 1270 } 1271 } 1272 1273 switch(calibPos) 1274 { 1275 case SHMOO_AND28_CALIB_FAIL_START: 1276 case SHMOO_AND28_CALIB_RISING_EDGE: 1277 if(failStartSeen > 0) 1278 { 1279 maxMidPointX = failStartSeen; 1280 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1281 } 1282 break; 1283 case SHMOO_AND28_CALIB_PASS_START: 1284 case SHMOO_AND28_CALIB_FALLING_EDGE: 1285 if(passStartSeen > 0) 1286 { 1287 maxMidPointX = passStartSeen; 1288 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1289 } 1290 break; 1291 case SHMOO_AND28_CALIB_CENTER_PASS: 1292 if((maxPassLength > 0) && (maxPassLengthArray[i] < maxPassLength)) 1293 { 1294 maxMidPointX = (maxPassStart + maxPassStart + maxPassLength) >> 1; 1295 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1296 maxPassLengthArray[i] = maxPassLength; 1297 } 1298 break; 1299 case SHMOO_AND28_CALIB_VDL_ZERO: 1300 maxMidPointX = 0; 1301 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF); 1302 break; 1303 default: 1304 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration position: %02lu\n"), (long unsigned int)calibPos)); 1305 return SOC_E_FAIL; 1306 } 1307 } 1308 xStart += sizeX; 1309 } 1310 1311 (*scPtr).calibMode = calibMode; 1312 (*scPtr).calibPos = calibPos; 1313 1314 return SOC_E_NONE; 1315 } 1316 1317 STATIC int 1318 _shmoo_and28_calib_2D(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 1319 { 1320 switch((*scPtr).shmooType) 1321 { 1322 case SHMOO_AND28_RD_EN: 1323 return _and28_calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS); 1324 case SHMOO_AND28_RD_EXTENDED: 1325 return _and28_calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS); 1326 case SHMOO_AND28_WR_EXTENDED: 1327 return _and28_calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS); 1328 case SHMOO_AND28_ADDR_EXTENDED: 1329 return _and28_calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_WORD, SHMOO_AND28_CALIB_CENTER_PASS); 1330 case SHMOO_AND28_CTRL_EXTENDED: 1331 if(!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED) 1332 { 1333 return _and28_calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_WORD, SHMOO_AND28_CALIB_CENTER_PASS); 1334 } 1335 break; 1336 default: 1337 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 1338 return SOC_E_FAIL; 1339 } 1340 return SOC_E_NONE; 1341 } 1342 1343 STATIC int 1344 _shmoo_and28_set_new_step(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 1345 { 1346 uint32 calibMode; 1347 /* uint32 engageUIshift; */ 1348 uint32 val, yVal; 1349 uint32 data, temp; 1350 uint32 rd_dqs_pos0 = 0, rd_dqs_pos1 = 0, rd_en_pos0 = 0, rd_en_pos1 = 0, rd_dqs_delta0 = 0, rd_dqs_delta1 = 0; 1351 uint32 rd_dqs_pos2 = 0, rd_dqs_pos3 = 0, rd_en_pos2 = 0, rd_en_pos3 = 0, rd_dqs_delta2 = 0, rd_dqs_delta3 = 0; 1352 1353 calibMode = (*scPtr).calibMode; 1354 /* engageUIshift = (*scPtr).engageUIshift; */ 1355 1356 switch((*scPtr).shmooType) 1357 { 1358 case SHMOO_AND28_RD_EN: 1359 switch(calibMode) 1360 { 1361 case SHMOO_AND28_BIT: 1362 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 1363 return SOC_E_FAIL; 1364 case SHMOO_AND28_BYTE: 1365 data = 0; 1366 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1367 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1368 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1369 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1370 1371 data = 0; 1372 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1373 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1374 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1375 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1376 1377 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1378 { 1379 data = 0; 1380 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1381 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[2] & 0xFFFF); 1382 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1383 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1384 1385 data = 0; 1386 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1387 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[3] & 0xFFFF); 1388 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1389 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1390 } 1391 1392 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1393 break; 1394 case SHMOO_AND28_HALFWORD: 1395 data = 0; 1396 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1397 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1398 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1399 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1400 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1401 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1402 1403 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1404 { 1405 data = 0; 1406 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1407 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1408 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1409 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1410 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1411 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1412 } 1413 1414 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1415 break; 1416 case SHMOO_AND28_WORD: 1417 data = 0; 1418 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1419 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1420 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1421 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1422 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1423 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1424 1425 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1426 { 1427 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1428 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1429 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1430 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1431 } 1432 1433 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1434 break; 1435 default: 1436 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 1437 return SOC_E_FAIL; 1438 } 1439 break; 1440 case SHMOO_AND28_RD_EXTENDED: 1441 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 1442 rd_dqs_pos0 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP); 1443 1444 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 1445 rd_dqs_pos1 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP); 1446 1447 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1448 { 1449 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 1450 rd_dqs_pos2 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP); 1451 1452 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 1453 rd_dqs_pos3 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP); 1454 } 1455 1456 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 1457 rd_en_pos0 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 1458 1459 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 1460 rd_en_pos1 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 1461 1462 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1463 { 1464 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 1465 rd_en_pos2 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 1466 1467 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 1468 rd_en_pos3 = DDR34_GET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP); 1469 } 1470 1471 switch(calibMode) 1472 { 1473 case SHMOO_AND28_BIT: 1474 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 1475 return SOC_E_FAIL; 1476 case SHMOO_AND28_BYTE: 1477 val = (*scPtr).resultData[0] & 0xFFFF; 1478 rd_dqs_delta0 = val - rd_dqs_pos0; 1479 data = 0; 1480 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1); 1481 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1482 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1483 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1484 1485 temp = rd_en_pos0 + rd_dqs_delta0; 1486 data = 0; 1487 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1488 if(temp & 0x80000000) 1489 { 1490 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1491 } 1492 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1493 { 1494 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1495 } 1496 else 1497 { 1498 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1499 } 1500 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1501 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1502 1503 val = (*scPtr).resultData[1] & 0xFFFF; 1504 rd_dqs_delta1 = val - rd_dqs_pos1; 1505 data = 0; 1506 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, FORCE, 1); 1507 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1508 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1509 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1510 1511 temp = rd_en_pos1 + rd_dqs_delta1; 1512 data = 0; 1513 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1514 if(temp & 0x80000000) 1515 { 1516 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1517 } 1518 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1519 { 1520 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1521 } 1522 else 1523 { 1524 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1525 } 1526 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1527 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1528 1529 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1530 { 1531 val = (*scPtr).resultData[2] & 0xFFFF; 1532 rd_dqs_delta2 = val - rd_dqs_pos2; 1533 data = 0; 1534 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, FORCE, 1); 1535 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1536 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1537 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1538 1539 temp = rd_en_pos2 + rd_dqs_delta2; 1540 data = 0; 1541 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1542 if(temp & 0x80000000) 1543 { 1544 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1545 } 1546 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1547 { 1548 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1549 } 1550 else 1551 { 1552 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1553 } 1554 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1555 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1556 1557 val = (*scPtr).resultData[3] & 0xFFFF; 1558 rd_dqs_delta3 = val - rd_dqs_pos3; 1559 data = 0; 1560 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, FORCE, 1); 1561 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1562 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1563 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1564 1565 temp = rd_en_pos3 + rd_dqs_delta3; 1566 data = 0; 1567 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1568 if(temp & 0x80000000) 1569 { 1570 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1571 } 1572 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1573 { 1574 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1575 } 1576 else 1577 { 1578 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1579 } 1580 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1581 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1582 } 1583 1584 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1585 { 1586 yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF) 1587 + (((*scPtr).resultData[2] >> 16) & 0xFFFF) + (((*scPtr).resultData[3] >> 16) & 0xFFFF)) >> 2; 1588 } 1589 else 1590 { 1591 yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1; 1592 } 1593 READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, &data); 1594 /* DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal); */ 1595 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal); 1596 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, data); 1597 1598 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1599 break; 1600 case SHMOO_AND28_HALFWORD: 1601 val = (*scPtr).resultData[0] & 0xFFFF; 1602 rd_dqs_delta0 = val - rd_dqs_pos0; 1603 rd_dqs_delta1 = val - rd_dqs_pos1; 1604 data = 0; 1605 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1); 1606 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1607 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1608 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1609 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1610 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1611 1612 temp = rd_en_pos0 + rd_dqs_delta0; 1613 data = 0; 1614 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1615 if(temp & 0x80000000) 1616 { 1617 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1618 } 1619 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1620 { 1621 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1622 } 1623 else 1624 { 1625 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1626 } 1627 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1628 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1629 1630 temp = rd_en_pos1 + rd_dqs_delta1; 1631 data = 0; 1632 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1633 if(temp & 0x80000000) 1634 { 1635 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1636 } 1637 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1638 { 1639 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1640 } 1641 else 1642 { 1643 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1644 } 1645 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1646 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1647 1648 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1649 { 1650 val = (*scPtr).resultData[1] & 0xFFFF; 1651 rd_dqs_delta2 = val - rd_dqs_pos2; 1652 rd_dqs_delta3 = val - rd_dqs_pos3; 1653 data = 0; 1654 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, FORCE, 1); 1655 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1656 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1657 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1658 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1659 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1660 1661 temp = rd_en_pos2 + rd_dqs_delta2; 1662 data = 0; 1663 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1664 if(temp & 0x80000000) 1665 { 1666 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1667 } 1668 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1669 { 1670 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1671 } 1672 else 1673 { 1674 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1675 } 1676 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1677 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1678 1679 temp = rd_en_pos3 + rd_dqs_delta3; 1680 data = 0; 1681 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1682 if(temp & 0x80000000) 1683 { 1684 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1685 } 1686 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1687 { 1688 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1689 } 1690 else 1691 { 1692 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1693 } 1694 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1695 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1696 } 1697 1698 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1699 { 1700 yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1; 1701 } 1702 else 1703 { 1704 yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF; 1705 } 1706 READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, &data); 1707 /* DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal); */ 1708 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal); 1709 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, data); 1710 1711 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1712 break; 1713 case SHMOO_AND28_WORD: 1714 val = (*scPtr).resultData[0] & 0xFFFF; 1715 rd_dqs_delta0 = val - rd_dqs_pos0; 1716 rd_dqs_delta1 = val - rd_dqs_pos1; 1717 data = 0; 1718 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1); 1719 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1720 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1721 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1722 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1723 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1724 1725 temp = rd_en_pos0 + rd_dqs_delta0; 1726 data = 0; 1727 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1728 if(temp & 0x80000000) 1729 { 1730 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1731 } 1732 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1733 { 1734 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1735 } 1736 else 1737 { 1738 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1739 } 1740 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1741 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1742 1743 temp = rd_en_pos1 + rd_dqs_delta1; 1744 data = 0; 1745 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1746 if(temp & 0x80000000) 1747 { 1748 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1749 } 1750 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1751 { 1752 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1753 } 1754 else 1755 { 1756 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1757 } 1758 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1759 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1760 1761 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1762 { 1763 rd_dqs_delta2 = val - rd_dqs_pos2; 1764 rd_dqs_delta3 = val - rd_dqs_pos3; 1765 data = 0; 1766 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1); 1767 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val); 1768 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1769 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1770 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 1771 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 1772 1773 temp = rd_en_pos2 + rd_dqs_delta2; 1774 data = 0; 1775 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1776 if(temp & 0x80000000) 1777 { 1778 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1779 } 1780 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1781 { 1782 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1783 } 1784 else 1785 { 1786 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1787 } 1788 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1789 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1790 1791 temp = rd_en_pos3 + rd_dqs_delta3; 1792 data = 0; 1793 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 1794 if(temp & 0x80000000) 1795 { 1796 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0); 1797 } 1798 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH) 1799 { 1800 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 1801 } 1802 else 1803 { 1804 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp); 1805 } 1806 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 1807 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 1808 } 1809 1810 yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF; 1811 READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, &data); 1812 /* DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal); */ 1813 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal); 1814 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, data); 1815 1816 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1817 break; 1818 default: 1819 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 1820 return SOC_E_FAIL; 1821 } 1822 break; 1823 case SHMOO_AND28_WR_EXTENDED: 1824 switch(calibMode) 1825 { 1826 case SHMOO_AND28_BIT: 1827 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 1828 return SOC_E_FAIL; 1829 case SHMOO_AND28_BYTE: 1830 data = 0; 1831 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1); 1832 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1833 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1834 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1835 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1836 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1837 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1838 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1839 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1840 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1841 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1842 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1843 { 1844 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1845 } 1846 1847 data = 0; 1848 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_WR_DQ0, FORCE, 1); 1849 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_1, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1850 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1851 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1852 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1853 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1854 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1855 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1856 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1857 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1858 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1859 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1860 { 1861 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1862 } 1863 1864 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1865 { 1866 data = 0; 1867 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, FORCE, 1); 1868 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[2] & 0xFFFF); 1869 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1870 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1871 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1872 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1873 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1874 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1875 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1876 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1877 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1878 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1879 { 1880 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1881 } 1882 1883 data = 0; 1884 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_WR_DQ0, FORCE, 1); 1885 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_3, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[3] & 0xFFFF); 1886 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1887 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1888 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1889 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1890 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1891 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1892 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1893 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1894 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1895 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1896 { 1897 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1898 } 1899 } 1900 1901 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1902 break; 1903 case SHMOO_AND28_HALFWORD: 1904 data = 0; 1905 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1); 1906 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1907 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1908 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1909 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1910 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1911 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1912 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1913 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1914 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1915 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1916 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1917 { 1918 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1919 } 1920 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1921 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1922 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1923 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1924 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1925 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1926 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1927 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1928 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1929 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1930 { 1931 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1932 } 1933 1934 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 1935 { 1936 data = 0; 1937 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, FORCE, 1); 1938 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF); 1939 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1940 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1941 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1942 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1943 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1944 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1945 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1946 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1947 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1948 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1949 { 1950 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1951 } 1952 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1953 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1954 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1955 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1956 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1957 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1958 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1959 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1960 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1961 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1962 { 1963 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1964 } 1965 } 1966 1967 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 1968 break; 1969 case SHMOO_AND28_WORD: 1970 data = 0; 1971 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1); 1972 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 1973 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1974 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1975 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1976 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1977 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1978 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1979 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1980 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1981 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1982 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1983 { 1984 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1985 } 1986 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 1987 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 1988 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 1989 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 1990 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 1991 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 1992 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 1993 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 1994 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 1995 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 1996 { 1997 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 1998 } 1999 2000 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 2001 { 2002 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 2003 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 2004 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 2005 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 2006 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 2007 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 2008 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 2009 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 2010 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 2011 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 2012 { 2013 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 2014 } 2015 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 2016 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 2017 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 2018 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 2019 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 2020 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 2021 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 2022 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 2023 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 2024 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 2025 { 2026 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 2027 } 2028 } 2029 2030 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2031 break; 2032 default: 2033 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2034 return SOC_E_FAIL; 2035 } 2036 break; 2037 case SHMOO_AND28_ADDR_EXTENDED: 2038 switch(calibMode) 2039 { 2040 case SHMOO_AND28_BIT: 2041 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2042 return SOC_E_FAIL; 2043 case SHMOO_AND28_BYTE: 2044 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2045 return SOC_E_FAIL; 2046 case SHMOO_AND28_HALFWORD: 2047 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2048 return SOC_E_FAIL; 2049 case SHMOO_AND28_WORD: 2050 data = 0; 2051 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1); 2052 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2053 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(unit, phy_ndx, data); 2054 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(unit, phy_ndx, data); 2055 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(unit, phy_ndx, data); 2056 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(unit, phy_ndx, data); 2057 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(unit, phy_ndx, data); 2058 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(unit, phy_ndx, data); 2059 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(unit, phy_ndx, data); 2060 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(unit, phy_ndx, data); 2061 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(unit, phy_ndx, data); 2062 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(unit, phy_ndx, data); 2063 2064 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2065 break; 2066 default: 2067 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2068 return SOC_E_FAIL; 2069 } 2070 break; 2071 case SHMOO_AND28_CTRL_EXTENDED: 2072 if(SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED) 2073 { 2074 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(unit, phy_ndx, &data); 2075 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1); 2076 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(unit, phy_ndx, data); 2077 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(unit, phy_ndx, data); 2078 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(unit, phy_ndx, data); 2079 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(unit, phy_ndx, data); 2080 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(unit, phy_ndx, data); 2081 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(unit, phy_ndx, data); 2082 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(unit, phy_ndx, data); 2083 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(unit, phy_ndx, data); 2084 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(unit, phy_ndx, data); 2085 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(unit, phy_ndx, data); 2086 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(unit, phy_ndx, data); 2087 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(unit, phy_ndx, data); 2088 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(unit, phy_ndx, data); 2089 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(unit, phy_ndx, data); 2090 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(unit, phy_ndx, data); 2091 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(unit, phy_ndx, data); 2092 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(unit, phy_ndx, data); 2093 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(unit, phy_ndx, data); 2094 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(unit, phy_ndx, data); 2095 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(unit, phy_ndx, data); 2096 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(unit, phy_ndx, data); 2097 2098 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2099 } 2100 else 2101 { 2102 switch(calibMode) 2103 { 2104 case SHMOO_AND28_BIT: 2105 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2106 return SOC_E_FAIL; 2107 case SHMOO_AND28_BYTE: 2108 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2109 return SOC_E_FAIL; 2110 case SHMOO_AND28_HALFWORD: 2111 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2112 return SOC_E_FAIL; 2113 case SHMOO_AND28_WORD: 2114 data = 0; 2115 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD10, FORCE, 1); 2116 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD10, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF); 2117 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(unit, phy_ndx, data); 2118 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(unit, phy_ndx, data); 2119 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(unit, phy_ndx, data); 2120 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(unit, phy_ndx, data); 2121 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(unit, phy_ndx, data); 2122 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(unit, phy_ndx, data); 2123 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(unit, phy_ndx, data); 2124 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(unit, phy_ndx, data); 2125 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(unit, phy_ndx, data); 2126 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(unit, phy_ndx, data); 2127 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(unit, phy_ndx, data); 2128 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(unit, phy_ndx, data); 2129 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(unit, phy_ndx, data); 2130 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(unit, phy_ndx, data); 2131 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(unit, phy_ndx, data); 2132 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(unit, phy_ndx, data); 2133 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(unit, phy_ndx, data); 2134 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(unit, phy_ndx, data); 2135 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(unit, phy_ndx, data); 2136 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(unit, phy_ndx, data); 2137 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(unit, phy_ndx, data); 2138 2139 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2140 break; 2141 default: 2142 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type and calibration mode combination during set new step: %02lu / %02lu\n"), (long unsigned int)(*scPtr).shmooType, (long unsigned int)calibMode)); 2143 return SOC_E_FAIL; 2144 } 2145 } 2146 break; 2147 default: 2148 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 2149 return SOC_E_FAIL; 2150 } 2151 2152 data = 0; 2153 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 2154 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 2155 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 2156 2157 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 2158 { 2159 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 2160 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 2161 } 2162 2163 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2164 2165 return SOC_E_NONE; 2166 } 2167 2168 STATIC int 2169 _and28_plot(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 plotMode) 2170 { 2171 uint32 x; 2172 uint32 y; 2173 uint32 xStart; 2174 uint32 sizeX; 2175 uint32 sizeY; 2176 uint32 yCapMin; 2177 uint32 yCapMax; 2178 uint32 yJump; 2179 uint32 i; 2180 uint32 ui; 2181 uint32 iter; 2182 uint32 shiftAmount; 2183 uint32 dataMask; 2184 uint32 calibMode; 2185 uint32 calibPos; 2186 uint32 calibStart; 2187 uint32 engageUIshift; 2188 uint32 step1000; 2189 uint32 size1000UI; 2190 uint32 calibShiftAmount; 2191 uint32 maxMidPointX; 2192 uint32 maxMidPointY; 2193 char str0[SHMOO_AND28_STRING_LENGTH]; 2194 char str1[SHMOO_AND28_STRING_LENGTH]; 2195 char str2[SHMOO_AND28_STRING_LENGTH]; 2196 char pass_low[2]; 2197 char fail_high[2]; 2198 char outOfSearch[2]; 2199 2200 outOfSearch[0] = ' '; 2201 outOfSearch[1] = 0; 2202 2203 sizeX = (*scPtr).sizeX; 2204 sizeY = (*scPtr).sizeY; 2205 yCapMin = (*scPtr).yCapMin; 2206 yCapMax = (*scPtr).yCapMax; 2207 yJump = (*scPtr).yJump; 2208 calibMode = (*scPtr).calibMode; 2209 calibPos = (*scPtr).calibPos; 2210 calibStart = (*scPtr).calibStart; 2211 engageUIshift = (*scPtr).engageUIshift; 2212 step1000 = (*scPtr).step1000; 2213 size1000UI = (*scPtr).size1000UI; 2214 2215 switch(calibPos) 2216 { 2217 case SHMOO_AND28_CALIB_RISING_EDGE: 2218 case SHMOO_AND28_CALIB_FALLING_EDGE: 2219 pass_low[0] = '_'; 2220 pass_low[1] = 0; 2221 fail_high[0] = '|'; 2222 fail_high[1] = 0; 2223 break; 2224 case SHMOO_AND28_CALIB_CENTER_PASS: 2225 case SHMOO_AND28_CALIB_PASS_START: 2226 case SHMOO_AND28_CALIB_FAIL_START: 2227 case SHMOO_AND28_CALIB_VDL_ZERO: 2228 pass_low[0] = '+'; 2229 pass_low[1] = 0; 2230 fail_high[0] = '-'; 2231 fail_high[1] = 0; 2232 break; 2233 default: 2234 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration position: %02lu\n"), (long unsigned int)calibPos)); 2235 return SOC_E_FAIL; 2236 } 2237 2238 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n\n"))); 2239 2240 switch(plotMode) 2241 { 2242 case SHMOO_AND28_BIT: 2243 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2244 { 2245 iter = shmoo_dram_info.interface_bitwidth << 1; 2246 } 2247 else 2248 { 2249 iter = shmoo_dram_info.interface_bitwidth; 2250 } 2251 shiftAmount = 0; 2252 dataMask = 0x1; 2253 switch(calibMode) 2254 { 2255 case SHMOO_AND28_BIT: 2256 calibShiftAmount = 0; 2257 break; 2258 case SHMOO_AND28_BYTE: 2259 calibShiftAmount = 3; 2260 break; 2261 case SHMOO_AND28_HALFWORD: 2262 calibShiftAmount = 4; 2263 break; 2264 case SHMOO_AND28_WORD: 2265 calibShiftAmount = 5; 2266 break; 2267 default: 2268 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02lu\n"), (long unsigned int)calibMode)); 2269 return SOC_E_FAIL; 2270 } 2271 break; 2272 case SHMOO_AND28_BYTE: 2273 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2274 { 2275 iter = shmoo_dram_info.interface_bitwidth >> 2; 2276 } 2277 else 2278 { 2279 iter = shmoo_dram_info.interface_bitwidth >> 3; 2280 } 2281 shiftAmount = 3; 2282 dataMask = 0xFF; 2283 switch(calibMode) 2284 { 2285 case SHMOO_AND28_BIT: 2286 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from byte mode to bit mode\n"))); 2287 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2288 { 2289 iter = shmoo_dram_info.interface_bitwidth << 1; 2290 } 2291 else 2292 { 2293 iter = shmoo_dram_info.interface_bitwidth; 2294 } 2295 shiftAmount = 0; 2296 dataMask = 0x1; 2297 calibShiftAmount = 0; 2298 break; 2299 case SHMOO_AND28_BYTE: 2300 calibShiftAmount = 0; 2301 break; 2302 case SHMOO_AND28_HALFWORD: 2303 calibShiftAmount = 1; 2304 break; 2305 case SHMOO_AND28_WORD: 2306 calibShiftAmount = 2; 2307 break; 2308 default: 2309 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02lu\n"), (long unsigned int)calibMode)); 2310 return SOC_E_FAIL; 2311 } 2312 break; 2313 case SHMOO_AND28_HALFWORD: 2314 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2315 { 2316 iter = shmoo_dram_info.interface_bitwidth >> 3; 2317 } 2318 else 2319 { 2320 iter = shmoo_dram_info.interface_bitwidth >> 4; 2321 } 2322 shiftAmount = 4; 2323 dataMask = 0xFFFF; 2324 switch(calibMode) 2325 { 2326 case SHMOO_AND28_BIT: 2327 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from halfword mode to bit mode\n"))); 2328 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2329 { 2330 iter = shmoo_dram_info.interface_bitwidth << 1; 2331 } 2332 else 2333 { 2334 iter = shmoo_dram_info.interface_bitwidth; 2335 } 2336 shiftAmount = 0; 2337 dataMask = 0x1; 2338 calibShiftAmount = 0; 2339 break; 2340 case SHMOO_AND28_BYTE: 2341 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from halfword mode to byte mode\n"))); 2342 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2343 { 2344 iter = shmoo_dram_info.interface_bitwidth >> 2; 2345 } 2346 else 2347 { 2348 iter = shmoo_dram_info.interface_bitwidth >> 3; 2349 } 2350 shiftAmount = 3; 2351 dataMask = 0xFF; 2352 calibShiftAmount = 0; 2353 break; 2354 case SHMOO_AND28_HALFWORD: 2355 calibShiftAmount = 0; 2356 break; 2357 case SHMOO_AND28_WORD: 2358 calibShiftAmount = 1; 2359 break; 2360 default: 2361 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02lu\n"), (long unsigned int)calibMode)); 2362 return SOC_E_FAIL; 2363 } 2364 break; 2365 case SHMOO_AND28_WORD: 2366 iter = 1; 2367 shiftAmount = 5; 2368 if(shmoo_dram_info.split_bus && !(_shmoo_and28_check_dram(phy_ndx) > 1)) 2369 { 2370 dataMask = 0x0000FFFF; 2371 } 2372 else 2373 { 2374 dataMask = 0xFFFFFFFF; 2375 } 2376 switch(calibMode) 2377 { 2378 case SHMOO_AND28_BIT: 2379 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from word mode to bit mode\n"))); 2380 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2381 { 2382 iter = shmoo_dram_info.interface_bitwidth << 1; 2383 } 2384 else 2385 { 2386 iter = shmoo_dram_info.interface_bitwidth; 2387 } 2388 shiftAmount = 0; 2389 dataMask = 0x1; 2390 calibShiftAmount = 0; 2391 break; 2392 case SHMOO_AND28_BYTE: 2393 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from word mode to byte mode\n"))); 2394 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2395 { 2396 iter = shmoo_dram_info.interface_bitwidth >> 2; 2397 } 2398 else 2399 { 2400 iter = shmoo_dram_info.interface_bitwidth >> 3; 2401 } 2402 shiftAmount = 3; 2403 dataMask = 0xFF; 2404 calibShiftAmount = 0; 2405 break; 2406 case SHMOO_AND28_HALFWORD: 2407 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "WARNING: Plot mode coerced from word mode to halfword mode\n"))); 2408 if(shmoo_dram_info.split_bus && (_shmoo_and28_check_dram(phy_ndx) > 1)) 2409 { 2410 iter = shmoo_dram_info.interface_bitwidth >> 3; 2411 } 2412 else 2413 { 2414 iter = shmoo_dram_info.interface_bitwidth >> 4; 2415 } 2416 shiftAmount = 4; 2417 dataMask = 0xFFFF; 2418 calibShiftAmount = 0; 2419 break; 2420 case SHMOO_AND28_WORD: 2421 calibShiftAmount = 0; 2422 break; 2423 default: 2424 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02lu\n"), (long unsigned int)calibMode)); 2425 return SOC_E_FAIL; 2426 } 2427 break; 2428 default: 2429 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported plot mode: %02lu\n"), (long unsigned int)plotMode)); 2430 return SOC_E_FAIL; 2431 } 2432 /* 2433 if(engageUIshift) 2434 { */ 2435 ui = 0; 2436 2437 for(x = 0; x < sizeX; x++) 2438 { 2439 if((ui < SHMOO_AND28_MAX_VISIBLE_UI_COUNT) && (x > (*scPtr).endUI[ui])) 2440 { 2441 str0[x] = ' '; 2442 str1[x] = ' '; 2443 str2[x] = ' '; 2444 ui++; 2445 } 2446 else 2447 { 2448 str0[x] = '0' + (x / 100); 2449 str1[x] = '0' + ((x % 100) / 10); 2450 str2[x] = '0' + (x % 10); 2451 } 2452 } 2453 /* } 2454 else 2455 { 2456 for(x = 0; x < sizeX; x++) 2457 { 2458 str0[x] = '0' + (x / 100); 2459 str1[x] = '0' + ((x % 100) / 10); 2460 str2[x] = '0' + (x % 10); 2461 } 2462 } */ 2463 2464 str0[x] = 0; 2465 str1[x] = 0; 2466 str2[x] = 0; 2467 2468 for(i = 0; i < iter; i++) 2469 { 2470 xStart = 0; 2471 maxMidPointX = (*scPtr).resultData[i >> calibShiftAmount] & 0xFFFF; 2472 maxMidPointY = ((*scPtr).resultData[i >> calibShiftAmount] >> 16) & 0xFFFF; 2473 2474 if((sizeY > 1) || (i == 0)) 2475 { 2476 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "***** Interface.......: %3d\n"), phy_ndx)); 2477 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** VDL step size...: %3lu.%03lu ps\n"), (long unsigned int)(step1000 / 1000), (long unsigned int)(step1000 % 1000))); 2478 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** UI size.........: %3lu.%03lu steps\n"), (long unsigned int)(size1000UI / 1000), (long unsigned int)(size1000UI % 1000))); 2479 2480 switch((*scPtr).shmooType) 2481 { 2482 case SHMOO_AND28_RD_EN: 2483 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: RD_EN\n"))); 2484 break; 2485 case SHMOO_AND28_RD_EXTENDED: 2486 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: RD_EXTENDED\n"))); 2487 break; 2488 case SHMOO_AND28_WR_EXTENDED: 2489 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: WR_EXTENDED\n"))); 2490 break; 2491 case SHMOO_AND28_ADDR_EXTENDED: 2492 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: ADDR_EXTENDED\n"))); 2493 break; 2494 case SHMOO_AND28_CTRL_EXTENDED: 2495 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: CTRL_EXTENDED\n"))); 2496 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Quick Shmoo.....: Off\n"))); 2497 break; 2498 default: 2499 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 2500 return SOC_E_FAIL; 2501 } 2502 2503 if(engageUIshift) 2504 { 2505 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** UI shift........: On\n"))); 2506 } 2507 else 2508 { 2509 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** UI shift........: Off or N/A\n"))); 2510 } 2511 } 2512 2513 if(sizeY > 1) 2514 { 2515 switch(calibMode) 2516 { 2517 case SHMOO_AND28_BIT: 2518 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Bit-wise\n"))); 2519 break; 2520 case SHMOO_AND28_BYTE: 2521 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Byte-wise\n"))); 2522 break; 2523 case SHMOO_AND28_HALFWORD: 2524 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Halfword-wise\n"))); 2525 break; 2526 case SHMOO_AND28_WORD: 2527 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 2D Word-wise\n"))); 2528 break; 2529 default: 2530 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02lu\n"), (long unsigned int)calibMode)); 2531 return SOC_E_FAIL; 2532 } 2533 2534 switch(plotMode) 2535 { 2536 case SHMOO_AND28_BIT: 2537 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Bit-wise\n"))); 2538 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Bit.............: %03lu\n"), (long unsigned int)i)); 2539 break; 2540 case SHMOO_AND28_BYTE: 2541 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Byte-wise\n"))); 2542 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Byte............: %03lu\n"), (long unsigned int)i)); 2543 break; 2544 case SHMOO_AND28_HALFWORD: 2545 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Halfword-wise\n"))); 2546 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Halfword........: %03lu\n"), (long unsigned int)i)); 2547 break; 2548 case SHMOO_AND28_WORD: 2549 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 2D Word-wise\n"))); 2550 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** Word............: %03lu\n"), (long unsigned int)i)); 2551 break; 2552 default: 2553 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported plot mode: %02lu\n"), (long unsigned int)plotMode)); 2554 return SOC_E_FAIL; 2555 } 2556 2557 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " * Center X........: %03lu\n"), (long unsigned int)maxMidPointX)); 2558 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " * Center Y........: %03lu\n"), (long unsigned int)maxMidPointY)); 2559 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str0)); 2560 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str1)); 2561 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str2)); 2562 2563 for(y = yCapMin; y < yCapMax; y++) 2564 { 2565 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %03lu "), (long unsigned int)(y << yJump))); 2566 2567 for(x = 0; x < calibStart; x++) 2568 { 2569 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), outOfSearch)); 2570 } 2571 2572 for(x = calibStart; x < sizeX; x++) 2573 { 2574 if(((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask) 2575 { /* FAIL - RISING EDGE */ 2576 if(x != maxMidPointX) 2577 { /* REGULAR FAIL */ 2578 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2579 } 2580 else 2581 { /* FAIL - RISING EDGE */ 2582 if((calibPos == SHMOO_AND28_CALIB_RISING_EDGE) || (calibPos == SHMOO_AND28_CALIB_FAIL_START)) 2583 { /* RISING EDGE */ 2584 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2585 } 2586 else 2587 { /* FAIL */ 2588 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2589 } 2590 } 2591 } 2592 else 2593 { /* PASS - MIDPOINT - FALLING EDGE */ 2594 if(x != maxMidPointX) 2595 { /* REGULAR PASS */ 2596 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), pass_low)); 2597 } 2598 else 2599 { /* POTENTIAL MIDPOINT - FALLING EDGE */ 2600 if(y == maxMidPointY) 2601 { /* MID POINT - FALLING EDGE */ 2602 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2603 } 2604 else 2605 { /* PASS */ 2606 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), pass_low)); 2607 } 2608 } 2609 } 2610 } 2611 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2612 xStart += sizeX; 2613 } 2614 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2615 } 2616 else 2617 { 2618 if(i == 0) 2619 { 2620 switch(calibMode) 2621 { 2622 case SHMOO_AND28_BIT: 2623 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Bit-wise\n"))); 2624 break; 2625 case SHMOO_AND28_BYTE: 2626 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Byte-wise\n"))); 2627 break; 2628 case SHMOO_AND28_HALFWORD: 2629 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Halfword-wise\n"))); 2630 break; 2631 case SHMOO_AND28_WORD: 2632 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Calib mode......: 1D Word-wise\n"))); 2633 break; 2634 default: 2635 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported calibration mode during plot: %02lu\n"), (long unsigned int)calibMode)); 2636 return SOC_E_FAIL; 2637 } 2638 2639 switch(plotMode) 2640 { 2641 case SHMOO_AND28_BIT: 2642 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Bit-wise\n"))); 2643 break; 2644 case SHMOO_AND28_BYTE: 2645 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Byte-wise\n"))); 2646 break; 2647 case SHMOO_AND28_HALFWORD: 2648 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Halfword-wise\n"))); 2649 break; 2650 case SHMOO_AND28_WORD: 2651 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot mode.......: 1D Word-wise\n"))); 2652 break; 2653 default: 2654 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported plot mode: %02lu\n"), (long unsigned int)plotMode)); 2655 return SOC_E_FAIL; 2656 } 2657 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str0)); 2658 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str1)); 2659 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %s\n"), str2)); 2660 } 2661 2662 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " %03lu "), (long unsigned int)i)); 2663 2664 for(x = 0; x < calibStart; x++) 2665 { 2666 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), outOfSearch)); 2667 } 2668 2669 for(x = calibStart; x < sizeX; x++) 2670 { 2671 if(((*scPtr).result2D[x] >> (i << shiftAmount)) & dataMask) 2672 { /* FAIL - RISING EDGE */ 2673 if(x != maxMidPointX) 2674 { /* REGULAR FAIL */ 2675 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2676 } 2677 else 2678 { /* FAIL - RISING EDGE */ 2679 if((calibPos == SHMOO_AND28_CALIB_RISING_EDGE) || (calibPos == SHMOO_AND28_CALIB_FAIL_START)) 2680 { /* RISING EDGE */ 2681 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2682 } 2683 else 2684 { /* FAIL */ 2685 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), fail_high)); 2686 } 2687 } 2688 } 2689 else 2690 { /* PASS - MIDPOINT - FALLING EDGE */ 2691 if(x != maxMidPointX) 2692 { /* REGULAR PASS */ 2693 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "%s"), pass_low)); 2694 } 2695 else 2696 { /* MID POINT - FALLING EDGE */ 2697 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "X"))); 2698 } 2699 } 2700 } 2701 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2702 } 2703 } 2704 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2705 2706 return SOC_E_NONE; 2707 } 2708 2709 STATIC int 2710 _shmoo_and28_plot(int unit, int phy_ndx, and28_shmoo_container_t *scPtr) 2711 { 2712 switch((*scPtr).shmooType) 2713 { 2714 case SHMOO_AND28_RD_EN: 2715 return _and28_plot(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE); 2716 case SHMOO_AND28_RD_EXTENDED: 2717 return _and28_plot(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE); 2718 case SHMOO_AND28_WR_EXTENDED: 2719 return _and28_plot(unit, phy_ndx, scPtr, SHMOO_AND28_BIT); 2720 case SHMOO_AND28_ADDR_EXTENDED: 2721 return _and28_plot(unit, phy_ndx, scPtr, SHMOO_AND28_WORD); 2722 case SHMOO_AND28_CTRL_EXTENDED: 2723 if(!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED) 2724 { 2725 return _and28_plot(unit, phy_ndx, scPtr, SHMOO_AND28_WORD); 2726 } 2727 else 2728 { 2729 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n\n"))); 2730 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "***** Interface.......: %3d\n"), phy_ndx)); 2731 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " **** Shmoo type......: CTRL_EXTENDED\n"))); 2732 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Quick Shmoo.....: On\n"))); 2733 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Plot............: Off\n"))); 2734 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " *** Copying.........: VDL_STEP\n"))); 2735 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** From............: AD00 - AD09\n"))); 2736 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " ** To..............: AD10 - WE_N\n"))); 2737 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "\n"))); 2738 } 2739 break; 2740 default: 2741 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 2742 return SOC_E_FAIL; 2743 } 2744 return SOC_E_NONE; 2745 } 2746 2747 int 2748 _and28_calculate_step_size(int unit, int phy_ndx, and28_step_size_t *ssPtr) 2749 { 2750 uint32 data; 2751 uint32 timeout; 2752 2753 if(shmoo_dram_info.sim_system_mode) 2754 { 2755 (*ssPtr).step1000 = 8000; 2756 (*ssPtr).size1000UI = 66988; 2757 2758 return SOC_E_NONE; 2759 } 2760 2761 data = 0; 2762 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, phy_ndx, data); 2763 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2764 2765 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CALIBRATE, CALIB_ONCE, 1); 2766 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CALIBRATE, UPDATE_REGS, 0); 2767 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CALIBRATE, UPDATE_FAST, 0); 2768 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, phy_ndx, data); 2769 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2770 2771 timeout = 2000; 2772 do 2773 { 2774 READ_DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r(unit, phy_ndx, &data); 2775 2776 if(DDR34_GET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_IDLE)) 2777 { 2778 /* LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " VDL calibration complete.\n"))); */ 2779 break; 2780 } 2781 2782 if (timeout == 0) 2783 { 2784 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " VDL calibration failed!!! (Timeout)\n"))); 2785 return SOC_E_TIMEOUT; 2786 } 2787 2788 timeout--; 2789 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2790 } 2791 while(TRUE); 2792 2793 if(DDR34_GET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_LOCK_4B) == 0) 2794 { 2795 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " VDL calibration failed!!! (No lock)\n"))); 2796 return SOC_E_FAIL; 2797 } 2798 2799 (*ssPtr).size1000UI = DDR34_GET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_TOTAL_STEPS) * 500; 2800 (*ssPtr).step1000 = ((1000000000 / shmoo_dram_info.data_rate_mbps) * 1000) / ((*ssPtr).size1000UI); 2801 2802 data = 0; 2803 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr(unit, phy_ndx, data); 2804 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2805 2806 return SOC_E_NONE; 2807 } 2808 2809 int 2810 _and28_zq_calibration(int unit, int phy_ndx) 2811 { 2812 int i; 2813 uint32 data; 2814 uint32 vref_dac; 2815 uint32 p_drive, n_drive; 2816 uint32 p_term, n_term; 2817 uint32 p_idle, n_idle; 2818 uint32 aq_p_drive, aq_n_drive; 2819 2820 READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, &vref_dac); 2821 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 2822 { 2823 data = vref_dac; 2824 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32); 2825 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 32); 2826 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, data); 2827 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2828 } 2829 2830 p_drive = 16; 2831 n_drive = 16; 2832 2833 READ_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, &data); 2834 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1); 2835 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1); 2836 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2837 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2838 2839 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_IDDQ, 0); 2840 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 0); 2841 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 31); 2842 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2843 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2844 2845 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 0); 2846 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1); 2847 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2848 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2849 2850 for(i = 0; i < SHMOO_AND28_MAX_ZQ_CAL_RANGE; i++) 2851 { 2852 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, i); 2853 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2854 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2855 2856 READ_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, &data); 2857 if(DDR34_GET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_STATUS)) 2858 { 2859 p_drive = i; 2860 break; 2861 } 2862 } 2863 2864 if(i == SHMOO_AND28_MAX_ZQ_CAL_RANGE) 2865 { 2866 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " WARNING: ZQ calibration error (P) - Manual IO programming required for correct operation\n"))); 2867 /* return SOC_E_FAIL; */ 2868 } 2869 2870 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 0); 2871 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 0); 2872 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2873 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2874 2875 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 31); 2876 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 0); 2877 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2878 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2879 2880 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1); 2881 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 0); 2882 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2883 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2884 2885 for(i = 0; i < SHMOO_AND28_MAX_ZQ_CAL_RANGE; i++) 2886 { 2887 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, i); 2888 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2889 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2890 2891 READ_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, &data); 2892 if(DDR34_GET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_STATUS)) 2893 { 2894 n_drive = i; 2895 break; 2896 } 2897 } 2898 2899 if(i == SHMOO_AND28_MAX_ZQ_CAL_RANGE) 2900 { 2901 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " WARNING: ZQ calibration error (N) - Manual IO programming required for correct operation\n"))); 2902 /* return SOC_E_FAIL; */ 2903 } 2904 2905 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1); 2906 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1); 2907 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2908 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2909 2910 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_IDDQ, 0); 2911 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 0); 2912 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 0); 2913 WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(unit, phy_ndx, data); 2914 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 2915 2916 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 2917 { 2918 aq_p_drive = p_drive; 2919 aq_n_drive = n_drive; 2920 2921 if(p_drive < 6) 2922 { 2923 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " WARNING: ZQ calibration error (P offset) - Manual IO programming required for correct operation\n"))); 2924 /* return SOC_E_FAIL; */ 2925 } 2926 else 2927 { 2928 p_drive -= 6; 2929 } 2930 2931 p_term = p_drive; 2932 n_term = 0; 2933 2934 p_idle = p_drive; 2935 n_idle = 0; 2936 } 2937 else 2938 { 2939 aq_p_drive = p_drive; 2940 aq_n_drive = n_drive; 2941 2942 p_term = 6; 2943 n_term = 6; 2944 2945 p_idle = 0; 2946 n_idle = 0; 2947 } 2948 2949 data = 0; 2950 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_IDLE_STRENGTH, p_idle); 2951 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_IDLE_STRENGTH, n_idle); 2952 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_TERM_STRENGTH, p_term); 2953 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_TERM_STRENGTH, n_term); 2954 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_STRENGTH, aq_p_drive); 2955 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_STRENGTH, aq_n_drive); 2956 WRITE_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2957 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 2958 { 2959 WRITE_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr(unit, phy_ndx, data); 2960 } 2961 2962 data = 0; 2963 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 2964 { 2965 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_IDLE_STRENGTH, p_idle); 2966 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_IDLE_STRENGTH, n_idle); 2967 } 2968 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term); 2969 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term); 2970 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive); 2971 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive); 2972 WRITE_DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2973 WRITE_DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2974 2975 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 2976 { 2977 WRITE_DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2978 WRITE_DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2979 } 2980 2981 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 2982 { 2983 data = 0; 2984 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term); 2985 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term); 2986 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive); 2987 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive); 2988 WRITE_DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2989 WRITE_DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2990 WRITE_DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2991 WRITE_DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2992 2993 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 2994 { 2995 WRITE_DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2996 WRITE_DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2997 WRITE_DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2998 WRITE_DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 2999 } 3000 3001 data = 0; 3002 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term); 3003 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term); 3004 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive); 3005 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive); 3006 WRITE_DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3007 WRITE_DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3008 3009 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3010 { 3011 WRITE_DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3012 WRITE_DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3013 } 3014 } 3015 3016 data = 0; 3017 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3018 { 3019 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_PD_STRENGTH, p_drive); 3020 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_ND_STRENGTH, n_drive); 3021 } 3022 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH, p_drive); 3023 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH, n_drive); 3024 WRITE_DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3025 WRITE_DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3026 3027 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3028 { 3029 WRITE_DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3030 WRITE_DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr(unit, phy_ndx, data); 3031 } 3032 3033 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 3034 { 3035 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, vref_dac); 3036 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 3037 } 3038 3039 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " P drive..........: 0x%02lX\n"), (long unsigned int) p_drive)); 3040 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " N drive..........: 0x%02lX\n"), (long unsigned int) n_drive)); 3041 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " P termination....: 0x%02lX\n"), (long unsigned int) p_term)); 3042 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " N termination....: 0x%02lX\n"), (long unsigned int) n_term)); 3043 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " P idle...........: 0x%02lX\n"), (long unsigned int) p_idle)); 3044 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " N idle...........: 0x%02lX\n"), (long unsigned int) n_idle)); 3045 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " AQ P drive.......: 0x%02lX\n"), (long unsigned int) aq_p_drive)); 3046 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " AQ N drive.......: 0x%02lX\n"), (long unsigned int) aq_n_drive)); 3047 3048 return SOC_E_NONE; 3049 } 3050 3051 STATIC int 3052 _shmoo_and28_entry(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 mode) 3053 { 3054 /* Mode 0: Sequential entry 3055 * Mode 1: Single entry 3056 */ 3057 3058 uint32 i; 3059 uint32 data, temp; 3060 and28_step_size_t ss; 3061 3062 (*scPtr).calibStart = 0; 3063 3064 switch((*scPtr).shmooType) 3065 { 3066 case SHMOO_AND28_RD_EN: 3067 /*A04*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "R04. Configure reference voltage\n"))); 3068 /*R04*/ READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, &data); 3069 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 3070 { 3071 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32); 3072 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 44); 3073 } 3074 else 3075 { 3076 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32); 3077 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 32); 3078 } 3079 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, data); 3080 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 3081 3082 /*A08*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "R08. ZQ calibration\n"))); 3083 /*R08*/ if(shmoo_dram_info.sim_system_mode) 3084 { 3085 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Skipped for emulation\n"))); 3086 3087 goto SHMOO_AND28_RD_EN_ZQ_CALIBRATION_END; 3088 } 3089 3090 _and28_zq_calibration(unit, phy_ndx); 3091 3092 SHMOO_AND28_RD_EN_ZQ_CALIBRATION_END: 3093 3094 _and28_calculate_step_size(unit, phy_ndx, &ss); 3095 (*scPtr).step1000 = ss.step1000; 3096 (*scPtr).size1000UI = ss.size1000UI; 3097 temp = (ss.size1000UI * 3) / 1000; /* 300% */ 3098 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3099 { 3100 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH; 3101 } 3102 else 3103 { 3104 (*scPtr).sizeX = temp; 3105 } 3106 3107 temp = (ss.size1000UI * 125) / 100000; /* 125% */ 3108 (*scPtr).yJump = 2; 3109 temp = temp >> (*scPtr).yJump; 3110 if(temp > SHMOO_AND28_MAX_VREF_RANGE) 3111 { 3112 (*scPtr).sizeY = SHMOO_AND28_MAX_VREF_RANGE; 3113 } 3114 else 3115 { 3116 (*scPtr).sizeY = temp; 3117 } 3118 3119 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++) 3120 { 3121 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3122 } 3123 3124 data = 0; 3125 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1); 3126 temp = (*scPtr).size1000UI / 1000; /* 100% */ 3127 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3128 { 3129 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 3130 } 3131 else 3132 { 3133 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, temp); 3134 } 3135 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(unit, phy_ndx, data); 3136 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(unit, phy_ndx, data); 3137 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(unit, phy_ndx, data); 3138 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(unit, phy_ndx, data); 3139 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(unit, phy_ndx, data); 3140 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(unit, phy_ndx, data); 3141 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(unit, phy_ndx, data); 3142 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(unit, phy_ndx, data); 3143 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(unit, phy_ndx, data); 3144 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(unit, phy_ndx, data); 3145 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(unit, phy_ndx, data); 3146 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(unit, phy_ndx, data); 3147 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(unit, phy_ndx, data); 3148 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(unit, phy_ndx, data); 3149 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(unit, phy_ndx, data); 3150 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(unit, phy_ndx, data); 3151 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(unit, phy_ndx, data); 3152 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(unit, phy_ndx, data); 3153 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(unit, phy_ndx, data); 3154 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(unit, phy_ndx, data); 3155 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(unit, phy_ndx, data); 3156 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(unit, phy_ndx, data); 3157 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(unit, phy_ndx, data); 3158 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(unit, phy_ndx, data); 3159 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(unit, phy_ndx, data); 3160 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(unit, phy_ndx, data); 3161 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(unit, phy_ndx, data); 3162 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(unit, phy_ndx, data); 3163 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(unit, phy_ndx, data); 3164 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(unit, phy_ndx, data); 3165 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(unit, phy_ndx, data); 3166 3167 data = 0; 3168 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3169 { 3170 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_CONTROL, MODE, 1); 3171 } 3172 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 3173 { 3174 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_CONTROL, MODE, 0); 3175 } 3176 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_CONTROL, RD_EN_MODE, 0); 3177 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_CONTROL, RD_DATA_DLY, SHMOO_AND28_RD_DATA_DLY_INIT); 3178 WRITE_DDR34_PHY_BYTE_LANE_0_READ_CONTROLr(unit, phy_ndx, data); 3179 WRITE_DDR34_PHY_BYTE_LANE_1_READ_CONTROLr(unit, phy_ndx, data); 3180 3181 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3182 { 3183 WRITE_DDR34_PHY_BYTE_LANE_2_READ_CONTROLr(unit, phy_ndx, data); 3184 WRITE_DDR34_PHY_BYTE_LANE_3_READ_CONTROLr(unit, phy_ndx, data); 3185 } 3186 3187 data = 0; 3188 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, FORCE, 1); 3189 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, ENABLE_CS1, 1); 3190 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3191 { 3192 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS1_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT - 1); 3193 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS0_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT - 1); 3194 } 3195 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 3196 { 3197 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS1_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT); 3198 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS0_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT); 3199 } 3200 WRITE_DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr(unit, phy_ndx, data); 3201 WRITE_DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr(unit, phy_ndx, data); 3202 3203 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3204 { 3205 WRITE_DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr(unit, phy_ndx, data); 3206 WRITE_DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr(unit, phy_ndx, data); 3207 } 3208 3209 data = 0; 3210 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1); 3211 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_RD_EN_VDL_INIT); 3212 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 3213 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 3214 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 3215 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 3216 3217 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3218 { 3219 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 3220 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 3221 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 3222 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 3223 } 3224 3225 data = 0; 3226 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1); 3227 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, SHMOO_AND28_RD_DQ_VDL_INIT); 3228 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 3229 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 3230 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 3231 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 3232 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 3233 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 3234 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 3235 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 3236 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 3237 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 3238 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 3239 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 3240 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 3241 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 3242 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 3243 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 3244 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 3245 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 3246 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3247 { 3248 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 3249 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 3250 } 3251 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 3252 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 3253 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 3254 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 3255 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 3256 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 3257 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 3258 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 3259 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 3260 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 3261 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 3262 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 3263 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 3264 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 3265 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 3266 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 3267 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 3268 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 3269 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3270 { 3271 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 3272 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 3273 } 3274 3275 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3276 { 3277 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 3278 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 3279 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 3280 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 3281 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 3282 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 3283 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 3284 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 3285 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 3286 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 3287 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 3288 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 3289 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 3290 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 3291 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 3292 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 3293 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 3294 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 3295 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3296 { 3297 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 3298 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 3299 } 3300 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 3301 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 3302 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 3303 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 3304 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 3305 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 3306 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 3307 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 3308 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 3309 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 3310 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 3311 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 3312 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 3313 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 3314 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 3315 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 3316 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 3317 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 3318 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3319 { 3320 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr(unit, phy_ndx, data); 3321 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr(unit, phy_ndx, data); 3322 } 3323 } 3324 3325 data = 0; 3326 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1); 3327 temp = (((*scPtr).size1000UI * 3) / 4000) + SHMOO_AND28_RD_DQS_VDL_OFFSET; /* 75% + Offset */ 3328 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3329 { 3330 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 3331 } 3332 else 3333 { 3334 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, temp); 3335 } 3336 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 3337 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 3338 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 3339 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 3340 3341 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3342 { 3343 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 3344 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 3345 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 3346 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 3347 } 3348 3349 data = 0; 3350 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, WR_CHAN_DLY_CYC, FORCE, 1); 3351 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, WR_CHAN_DLY_CYC, CYCLES, SHMOO_AND28_WR_CYC_INIT); 3352 WRITE_DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 3353 WRITE_DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 3354 3355 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3356 { 3357 WRITE_DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 3358 WRITE_DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 3359 } 3360 3361 data = 0; 3362 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1); 3363 temp = (*scPtr).size1000UI / 2000; 3364 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3365 { 3366 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 3367 } 3368 else 3369 { 3370 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, temp); 3371 } 3372 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 3373 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 3374 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 3375 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 3376 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 3377 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 3378 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 3379 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 3380 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 3381 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3382 { 3383 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 3384 } 3385 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 3386 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 3387 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 3388 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 3389 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 3390 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 3391 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 3392 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 3393 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 3394 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3395 { 3396 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 3397 } 3398 3399 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3400 { 3401 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 3402 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 3403 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 3404 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 3405 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 3406 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 3407 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 3408 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 3409 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 3410 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3411 { 3412 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 3413 } 3414 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 3415 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 3416 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 3417 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 3418 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 3419 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 3420 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 3421 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 3422 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 3423 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3424 { 3425 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 3426 } 3427 } 3428 3429 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 3430 break; 3431 case SHMOO_AND28_RD_EXTENDED: 3432 _and28_calculate_step_size(unit, phy_ndx, &ss); 3433 (*scPtr).step1000 = ss.step1000; 3434 (*scPtr).size1000UI = ss.size1000UI; 3435 temp = (ss.size1000UI * 125) / 100000; /* 125% */ 3436 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3437 { 3438 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH; 3439 } 3440 else 3441 { 3442 (*scPtr).sizeX = temp; 3443 } 3444 3445 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++) 3446 { 3447 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3448 } 3449 break; 3450 case SHMOO_AND28_WR_EXTENDED: 3451 _and28_calculate_step_size(unit, phy_ndx, &ss); 3452 (*scPtr).step1000 = ss.step1000; 3453 (*scPtr).size1000UI = ss.size1000UI; 3454 temp = (ss.size1000UI * 125) / 100000; /* 125% */ 3455 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3456 { 3457 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH; 3458 } 3459 else 3460 { 3461 (*scPtr).sizeX = temp; 3462 } 3463 3464 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++) 3465 { 3466 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3467 } 3468 break; 3469 case SHMOO_AND28_ADDR_EXTENDED: 3470 _and28_calculate_step_size(unit, phy_ndx, &ss); 3471 (*scPtr).step1000 = ss.step1000; 3472 (*scPtr).size1000UI = ss.size1000UI; 3473 temp = (ss.size1000UI * 25) / 10000; /* 250% */ 3474 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3475 { 3476 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH; 3477 } 3478 else 3479 { 3480 (*scPtr).sizeX = temp; 3481 } 3482 3483 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++) 3484 { 3485 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3486 } 3487 break; 3488 case SHMOO_AND28_CTRL_EXTENDED: 3489 _and28_calculate_step_size(unit, phy_ndx, &ss); 3490 (*scPtr).step1000 = ss.step1000; 3491 (*scPtr).size1000UI = ss.size1000UI; 3492 temp = (ss.size1000UI * 25) / 10000; /* 250% */ 3493 if(temp > SHMOO_AND28_MAX_VDL_LENGTH) 3494 { 3495 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH; 3496 } 3497 else 3498 { 3499 (*scPtr).sizeX = temp; 3500 } 3501 3502 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++) 3503 { 3504 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000; 3505 } 3506 break; 3507 default: 3508 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 3509 return SOC_E_FAIL; 3510 } 3511 return SOC_E_NONE; 3512 } 3513 3514 STATIC int 3515 _shmoo_and28_exit(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 mode) 3516 { 3517 /* Mode 0: Sequential exit 3518 * Mode 1: Single exit 3519 */ 3520 3521 switch((*scPtr).shmooType) 3522 { 3523 case SHMOO_AND28_RD_EN: 3524 break; 3525 case SHMOO_AND28_RD_EXTENDED: 3526 break; 3527 case SHMOO_AND28_WR_EXTENDED: 3528 break; 3529 case SHMOO_AND28_ADDR_EXTENDED: 3530 break; 3531 case SHMOO_AND28_CTRL_EXTENDED: 3532 break; 3533 default: 3534 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported shmoo type: %02lu\n"), (long unsigned int)(*scPtr).shmooType)); 3535 return SOC_E_FAIL; 3536 } 3537 3538 return SOC_E_NONE; 3539 } 3540 3541 STATIC int 3542 _shmoo_and28_save(int unit, int phy_ndx, and28_shmoo_config_param_t *config_param) 3543 { 3544 uint32 data; 3545 3546 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(unit, phy_ndx, &data); 3547 (*config_param).control_regs_ad[0] = (uint16) data; 3548 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(unit, phy_ndx, &data); 3549 (*config_param).control_regs_ad[1] = (uint16) data; 3550 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(unit, phy_ndx, &data); 3551 (*config_param).control_regs_ad[2] = (uint16) data; 3552 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(unit, phy_ndx, &data); 3553 (*config_param).control_regs_ad[3] = (uint16) data; 3554 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(unit, phy_ndx, &data); 3555 (*config_param).control_regs_ad[4] = (uint16) data; 3556 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(unit, phy_ndx, &data); 3557 (*config_param).control_regs_ad[5] = (uint16) data; 3558 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(unit, phy_ndx, &data); 3559 (*config_param).control_regs_ad[6] = (uint16) data; 3560 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(unit, phy_ndx, &data); 3561 (*config_param).control_regs_ad[7] = (uint16) data; 3562 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(unit, phy_ndx, &data); 3563 (*config_param).control_regs_ad[8] = (uint16) data; 3564 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(unit, phy_ndx, &data); 3565 (*config_param).control_regs_ad[9] = (uint16) data; 3566 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(unit, phy_ndx, &data); 3567 (*config_param).control_regs_ad[10] = (uint16) data; 3568 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(unit, phy_ndx, &data); 3569 (*config_param).control_regs_ad[11] = (uint16) data; 3570 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(unit, phy_ndx, &data); 3571 (*config_param).control_regs_ad[12] = (uint16) data; 3572 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(unit, phy_ndx, &data); 3573 (*config_param).control_regs_ad[13] = (uint16) data; 3574 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(unit, phy_ndx, &data); 3575 (*config_param).control_regs_ad[14] = (uint16) data; 3576 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(unit, phy_ndx, &data); 3577 (*config_param).control_regs_ad[15] = (uint16) data; 3578 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(unit, phy_ndx, &data); 3579 (*config_param).control_regs_ba[0] = (uint16) data; 3580 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(unit, phy_ndx, &data); 3581 (*config_param).control_regs_ba[1] = (uint16) data; 3582 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(unit, phy_ndx, &data); 3583 (*config_param).control_regs_ba[2] = (uint16) data; 3584 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(unit, phy_ndx, &data); 3585 (*config_param).control_regs_aux[0] = (uint16) data; 3586 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(unit, phy_ndx, &data); 3587 (*config_param).control_regs_aux[1] = (uint16) data; 3588 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(unit, phy_ndx, &data); 3589 (*config_param).control_regs_aux[2] = (uint16) data; 3590 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(unit, phy_ndx, &data); 3591 (*config_param).control_regs_cs[0] = (uint16) data; 3592 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(unit, phy_ndx, &data); 3593 (*config_param).control_regs_cs[1] = (uint16) data; 3594 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(unit, phy_ndx, &data); 3595 (*config_param).control_regs_par = (uint16) data; 3596 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(unit, phy_ndx, &data); 3597 (*config_param).control_regs_ras_n = (uint16) data; 3598 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(unit, phy_ndx, &data); 3599 (*config_param).control_regs_cas_n = (uint16) data; 3600 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(unit, phy_ndx, &data); 3601 (*config_param).control_regs_cke = (uint16) data; 3602 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(unit, phy_ndx, &data); 3603 (*config_param).control_regs_rst_n = (uint16) data; 3604 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(unit, phy_ndx, &data); 3605 (*config_param).control_regs_odt = (uint16) data; 3606 READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(unit, phy_ndx, &data); 3607 (*config_param).control_regs_we_n = (uint16) data; 3608 READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, &data); 3609 (*config_param).control_regs_vref_dac_control = data; 3610 3611 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3612 { 3613 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, &data); 3614 } 3615 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 3616 { 3617 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr(unit, phy_ndx, &data); 3618 } 3619 (*config_param).wr_vdl_dqsp[0] = (uint16) data; 3620 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3621 { 3622 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, &data); 3623 (*config_param).wr_vdl_dqsn[0] = (uint16) data; 3624 } 3625 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, &data); 3626 (*config_param).wr_vdl_dq[0][0] = (uint16) data; 3627 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, &data); 3628 (*config_param).wr_vdl_dq[0][1] = (uint16) data; 3629 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, &data); 3630 (*config_param).wr_vdl_dq[0][2] = (uint16) data; 3631 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, &data); 3632 (*config_param).wr_vdl_dq[0][3] = (uint16) data; 3633 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, &data); 3634 (*config_param).wr_vdl_dq[0][4] = (uint16) data; 3635 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, &data); 3636 (*config_param).wr_vdl_dq[0][5] = (uint16) data; 3637 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, &data); 3638 (*config_param).wr_vdl_dq[0][6] = (uint16) data; 3639 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, &data); 3640 (*config_param).wr_vdl_dq[0][7] = (uint16) data; 3641 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(unit, phy_ndx, &data); 3642 (*config_param).wr_vdl_dm[0] = (uint16) data; 3643 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3644 { 3645 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(unit, phy_ndx, &data); 3646 (*config_param).wr_vdl_edc[0] = (uint16) data; 3647 } 3648 READ_DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr(unit, phy_ndx, &data); 3649 (*config_param).wr_chan_dly_cyc[0] = (uint8) data; 3650 3651 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 3652 (*config_param).rd_vdl_dqsp[0] = (uint16) data; 3653 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, &data); 3654 (*config_param).rd_vdl_dqsn[0] = (uint16) data; 3655 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, &data); 3656 (*config_param).rd_vdl_dqp[0][0] = (uint16) data; 3657 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, &data); 3658 (*config_param).rd_vdl_dqp[0][1] = (uint16) data; 3659 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, &data); 3660 (*config_param).rd_vdl_dqp[0][2] = (uint16) data; 3661 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, &data); 3662 (*config_param).rd_vdl_dqp[0][3] = (uint16) data; 3663 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, &data); 3664 (*config_param).rd_vdl_dqp[0][4] = (uint16) data; 3665 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, &data); 3666 (*config_param).rd_vdl_dqp[0][5] = (uint16) data; 3667 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, &data); 3668 (*config_param).rd_vdl_dqp[0][6] = (uint16) data; 3669 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, &data); 3670 (*config_param).rd_vdl_dqp[0][7] = (uint16) data; 3671 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(unit, phy_ndx, &data); 3672 (*config_param).rd_vdl_dmp[0] = (uint16) data; 3673 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, &data); 3674 (*config_param).rd_vdl_dqn[0][0] = (uint16) data; 3675 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, &data); 3676 (*config_param).rd_vdl_dqn[0][1] = (uint16) data; 3677 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, &data); 3678 (*config_param).rd_vdl_dqn[0][2] = (uint16) data; 3679 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, &data); 3680 (*config_param).rd_vdl_dqn[0][3] = (uint16) data; 3681 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, &data); 3682 (*config_param).rd_vdl_dqn[0][4] = (uint16) data; 3683 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, &data); 3684 (*config_param).rd_vdl_dqn[0][5] = (uint16) data; 3685 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, &data); 3686 (*config_param).rd_vdl_dqn[0][6] = (uint16) data; 3687 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, &data); 3688 (*config_param).rd_vdl_dqn[0][7] = (uint16) data; 3689 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(unit, phy_ndx, &data); 3690 (*config_param).rd_vdl_dmn[0] = (uint16) data; 3691 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 3692 (*config_param).rd_en_vdl_cs[0][0] = (uint16) data; 3693 READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, &data); 3694 (*config_param).rd_en_vdl_cs[0][1] = (uint16) data; 3695 READ_DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr(unit, phy_ndx, &data); 3696 (*config_param).rd_en_dly_cyc[0] = (uint16) data; 3697 READ_DDR34_PHY_BYTE_LANE_0_READ_CONTROLr(unit, phy_ndx, &data); 3698 (*config_param).rd_control[0] = (uint8) data; 3699 3700 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3701 { 3702 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, &data); 3703 } 3704 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 3705 { 3706 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr(unit, phy_ndx, &data); 3707 } 3708 (*config_param).wr_vdl_dqsp[1] = (uint16) data; 3709 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3710 { 3711 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, &data); 3712 (*config_param).wr_vdl_dqsn[1] = (uint16) data; 3713 } 3714 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, &data); 3715 (*config_param).wr_vdl_dq[1][0] = (uint16) data; 3716 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, &data); 3717 (*config_param).wr_vdl_dq[1][1] = (uint16) data; 3718 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, &data); 3719 (*config_param).wr_vdl_dq[1][2] = (uint16) data; 3720 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, &data); 3721 (*config_param).wr_vdl_dq[1][3] = (uint16) data; 3722 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, &data); 3723 (*config_param).wr_vdl_dq[1][4] = (uint16) data; 3724 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, &data); 3725 (*config_param).wr_vdl_dq[1][5] = (uint16) data; 3726 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, &data); 3727 (*config_param).wr_vdl_dq[1][6] = (uint16) data; 3728 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, &data); 3729 (*config_param).wr_vdl_dq[1][7] = (uint16) data; 3730 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(unit, phy_ndx, &data); 3731 (*config_param).wr_vdl_dm[1] = (uint16) data; 3732 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3733 { 3734 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(unit, phy_ndx, &data); 3735 (*config_param).wr_vdl_edc[1] = (uint16) data; 3736 } 3737 READ_DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr(unit, phy_ndx, &data); 3738 (*config_param).wr_chan_dly_cyc[1] = (uint8) data; 3739 3740 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 3741 (*config_param).rd_vdl_dqsp[1] = (uint16) data; 3742 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, &data); 3743 (*config_param).rd_vdl_dqsn[1] = (uint16) data; 3744 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, &data); 3745 (*config_param).rd_vdl_dqp[1][0] = (uint16) data; 3746 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, &data); 3747 (*config_param).rd_vdl_dqp[1][1] = (uint16) data; 3748 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, &data); 3749 (*config_param).rd_vdl_dqp[1][2] = (uint16) data; 3750 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, &data); 3751 (*config_param).rd_vdl_dqp[1][3] = (uint16) data; 3752 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, &data); 3753 (*config_param).rd_vdl_dqp[1][4] = (uint16) data; 3754 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, &data); 3755 (*config_param).rd_vdl_dqp[1][5] = (uint16) data; 3756 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, &data); 3757 (*config_param).rd_vdl_dqp[1][6] = (uint16) data; 3758 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, &data); 3759 (*config_param).rd_vdl_dqp[1][7] = (uint16) data; 3760 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(unit, phy_ndx, &data); 3761 (*config_param).rd_vdl_dmp[1] = (uint16) data; 3762 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, &data); 3763 (*config_param).rd_vdl_dqn[1][0] = (uint16) data; 3764 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, &data); 3765 (*config_param).rd_vdl_dqn[1][1] = (uint16) data; 3766 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, &data); 3767 (*config_param).rd_vdl_dqn[1][2] = (uint16) data; 3768 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, &data); 3769 (*config_param).rd_vdl_dqn[1][3] = (uint16) data; 3770 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, &data); 3771 (*config_param).rd_vdl_dqn[1][4] = (uint16) data; 3772 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, &data); 3773 (*config_param).rd_vdl_dqn[1][5] = (uint16) data; 3774 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, &data); 3775 (*config_param).rd_vdl_dqn[1][6] = (uint16) data; 3776 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, &data); 3777 (*config_param).rd_vdl_dqn[1][7] = (uint16) data; 3778 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(unit, phy_ndx, &data); 3779 (*config_param).rd_vdl_dmn[1] = (uint16) data; 3780 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 3781 (*config_param).rd_en_vdl_cs[1][0] = (uint16) data; 3782 READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, &data); 3783 (*config_param).rd_en_vdl_cs[1][1] = (uint16) data; 3784 READ_DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr(unit, phy_ndx, &data); 3785 (*config_param).rd_en_dly_cyc[1] = (uint16) data; 3786 READ_DDR34_PHY_BYTE_LANE_1_READ_CONTROLr(unit, phy_ndx, &data); 3787 (*config_param).rd_control[1] = (uint8) data; 3788 3789 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 3790 { 3791 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3792 { 3793 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, &data); 3794 } 3795 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 3796 { 3797 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr(unit, phy_ndx, &data); 3798 } 3799 (*config_param).wr_vdl_dqsp[2] = (uint16) data; 3800 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3801 { 3802 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, &data); 3803 (*config_param).wr_vdl_dqsn[2] = (uint16) data; 3804 } 3805 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, &data); 3806 (*config_param).wr_vdl_dq[2][0] = (uint16) data; 3807 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, &data); 3808 (*config_param).wr_vdl_dq[2][1] = (uint16) data; 3809 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, &data); 3810 (*config_param).wr_vdl_dq[2][2] = (uint16) data; 3811 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, &data); 3812 (*config_param).wr_vdl_dq[2][3] = (uint16) data; 3813 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, &data); 3814 (*config_param).wr_vdl_dq[2][4] = (uint16) data; 3815 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, &data); 3816 (*config_param).wr_vdl_dq[2][5] = (uint16) data; 3817 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, &data); 3818 (*config_param).wr_vdl_dq[2][6] = (uint16) data; 3819 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, &data); 3820 (*config_param).wr_vdl_dq[2][7] = (uint16) data; 3821 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(unit, phy_ndx, &data); 3822 (*config_param).wr_vdl_dm[2] = (uint16) data; 3823 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3824 { 3825 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(unit, phy_ndx, &data); 3826 (*config_param).wr_vdl_edc[2] = (uint16) data; 3827 } 3828 READ_DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr(unit, phy_ndx, &data); 3829 (*config_param).wr_chan_dly_cyc[2] = (uint8) data; 3830 3831 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 3832 (*config_param).rd_vdl_dqsp[2] = (uint16) data; 3833 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, &data); 3834 (*config_param).rd_vdl_dqsn[2] = (uint16) data; 3835 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, &data); 3836 (*config_param).rd_vdl_dqp[2][0] = (uint16) data; 3837 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, &data); 3838 (*config_param).rd_vdl_dqp[2][1] = (uint16) data; 3839 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, &data); 3840 (*config_param).rd_vdl_dqp[2][2] = (uint16) data; 3841 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, &data); 3842 (*config_param).rd_vdl_dqp[2][3] = (uint16) data; 3843 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, &data); 3844 (*config_param).rd_vdl_dqp[2][4] = (uint16) data; 3845 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, &data); 3846 (*config_param).rd_vdl_dqp[2][5] = (uint16) data; 3847 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, &data); 3848 (*config_param).rd_vdl_dqp[2][6] = (uint16) data; 3849 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, &data); 3850 (*config_param).rd_vdl_dqp[2][7] = (uint16) data; 3851 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(unit, phy_ndx, &data); 3852 (*config_param).rd_vdl_dmp[2] = (uint16) data; 3853 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, &data); 3854 (*config_param).rd_vdl_dqn[2][0] = (uint16) data; 3855 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, &data); 3856 (*config_param).rd_vdl_dqn[2][1] = (uint16) data; 3857 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, &data); 3858 (*config_param).rd_vdl_dqn[2][2] = (uint16) data; 3859 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, &data); 3860 (*config_param).rd_vdl_dqn[2][3] = (uint16) data; 3861 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, &data); 3862 (*config_param).rd_vdl_dqn[2][4] = (uint16) data; 3863 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, &data); 3864 (*config_param).rd_vdl_dqn[2][5] = (uint16) data; 3865 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, &data); 3866 (*config_param).rd_vdl_dqn[2][6] = (uint16) data; 3867 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, &data); 3868 (*config_param).rd_vdl_dqn[2][7] = (uint16) data; 3869 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(unit, phy_ndx, &data); 3870 (*config_param).rd_vdl_dmn[2] = (uint16) data; 3871 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 3872 (*config_param).rd_en_vdl_cs[2][0] = (uint16) data; 3873 READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, &data); 3874 (*config_param).rd_en_vdl_cs[2][1] = (uint16) data; 3875 READ_DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr(unit, phy_ndx, &data); 3876 (*config_param).rd_en_dly_cyc[2] = (uint16) data; 3877 READ_DDR34_PHY_BYTE_LANE_2_READ_CONTROLr(unit, phy_ndx, &data); 3878 (*config_param).rd_control[2] = (uint8) data; 3879 3880 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3881 { 3882 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, &data); 3883 } 3884 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 3885 { 3886 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr(unit, phy_ndx, &data); 3887 } 3888 (*config_param).wr_vdl_dqsp[3] = (uint16) data; 3889 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3890 { 3891 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, &data); 3892 (*config_param).wr_vdl_dqsn[3] = (uint16) data; 3893 } 3894 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, &data); 3895 (*config_param).wr_vdl_dq[3][0] = (uint16) data; 3896 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, &data); 3897 (*config_param).wr_vdl_dq[3][1] = (uint16) data; 3898 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, &data); 3899 (*config_param).wr_vdl_dq[3][2] = (uint16) data; 3900 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, &data); 3901 (*config_param).wr_vdl_dq[3][3] = (uint16) data; 3902 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, &data); 3903 (*config_param).wr_vdl_dq[3][4] = (uint16) data; 3904 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, &data); 3905 (*config_param).wr_vdl_dq[3][5] = (uint16) data; 3906 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, &data); 3907 (*config_param).wr_vdl_dq[3][6] = (uint16) data; 3908 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, &data); 3909 (*config_param).wr_vdl_dq[3][7] = (uint16) data; 3910 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(unit, phy_ndx, &data); 3911 (*config_param).wr_vdl_dm[3] = (uint16) data; 3912 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 3913 { 3914 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(unit, phy_ndx, &data); 3915 (*config_param).wr_vdl_edc[3] = (uint16) data; 3916 } 3917 READ_DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr(unit, phy_ndx, &data); 3918 (*config_param).wr_chan_dly_cyc[3] = (uint8) data; 3919 3920 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, &data); 3921 (*config_param).rd_vdl_dqsp[3] = (uint16) data; 3922 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, &data); 3923 (*config_param).rd_vdl_dqsn[3] = (uint16) data; 3924 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, &data); 3925 (*config_param).rd_vdl_dqp[3][0] = (uint16) data; 3926 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, &data); 3927 (*config_param).rd_vdl_dqp[3][1] = (uint16) data; 3928 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, &data); 3929 (*config_param).rd_vdl_dqp[3][2] = (uint16) data; 3930 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, &data); 3931 (*config_param).rd_vdl_dqp[3][3] = (uint16) data; 3932 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, &data); 3933 (*config_param).rd_vdl_dqp[3][4] = (uint16) data; 3934 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, &data); 3935 (*config_param).rd_vdl_dqp[3][5] = (uint16) data; 3936 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, &data); 3937 (*config_param).rd_vdl_dqp[3][6] = (uint16) data; 3938 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, &data); 3939 (*config_param).rd_vdl_dqp[3][7] = (uint16) data; 3940 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(unit, phy_ndx, &data); 3941 (*config_param).rd_vdl_dmp[3] = (uint16) data; 3942 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, &data); 3943 (*config_param).rd_vdl_dqn[3][0] = (uint16) data; 3944 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, &data); 3945 (*config_param).rd_vdl_dqn[3][1] = (uint16) data; 3946 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, &data); 3947 (*config_param).rd_vdl_dqn[3][2] = (uint16) data; 3948 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, &data); 3949 (*config_param).rd_vdl_dqn[3][3] = (uint16) data; 3950 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, &data); 3951 (*config_param).rd_vdl_dqn[3][4] = (uint16) data; 3952 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, &data); 3953 (*config_param).rd_vdl_dqn[3][5] = (uint16) data; 3954 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, &data); 3955 (*config_param).rd_vdl_dqn[3][6] = (uint16) data; 3956 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, &data); 3957 (*config_param).rd_vdl_dqn[3][7] = (uint16) data; 3958 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(unit, phy_ndx, &data); 3959 (*config_param).rd_vdl_dmn[3] = (uint16) data; 3960 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, &data); 3961 (*config_param).rd_en_vdl_cs[3][0] = (uint16) data; 3962 READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, &data); 3963 (*config_param).rd_en_vdl_cs[3][1] = (uint16) data; 3964 READ_DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr(unit, phy_ndx, &data); 3965 (*config_param).rd_en_dly_cyc[3] = (uint16) data; 3966 READ_DDR34_PHY_BYTE_LANE_3_READ_CONTROLr(unit, phy_ndx, &data); 3967 (*config_param).rd_control[3] = (uint8) data; 3968 } 3969 3970 return SOC_E_NONE; 3971 } 3972 3973 STATIC int 3974 _shmoo_and28_restore(int unit, int phy_ndx, and28_shmoo_config_param_t *config_param) 3975 { 3976 uint32 data; 3977 3978 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[0]); 3979 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(unit, phy_ndx, data); 3980 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[1]); 3981 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(unit, phy_ndx, data); 3982 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[2]); 3983 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(unit, phy_ndx, data); 3984 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[3]); 3985 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(unit, phy_ndx, data); 3986 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[4]); 3987 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(unit, phy_ndx, data); 3988 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[5]); 3989 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(unit, phy_ndx, data); 3990 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[6]); 3991 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(unit, phy_ndx, data); 3992 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[7]); 3993 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(unit, phy_ndx, data); 3994 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[8]); 3995 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(unit, phy_ndx, data); 3996 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[9]); 3997 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(unit, phy_ndx, data); 3998 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[10]); 3999 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(unit, phy_ndx, data); 4000 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[11]); 4001 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(unit, phy_ndx, data); 4002 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[12]); 4003 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(unit, phy_ndx, data); 4004 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[13]); 4005 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(unit, phy_ndx, data); 4006 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[14]); 4007 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(unit, phy_ndx, data); 4008 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[15]); 4009 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(unit, phy_ndx, data); 4010 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[0]); 4011 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(unit, phy_ndx, data); 4012 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[1]); 4013 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(unit, phy_ndx, data); 4014 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[2]); 4015 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(unit, phy_ndx, data); 4016 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[0]); 4017 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(unit, phy_ndx, data); 4018 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[1]); 4019 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(unit, phy_ndx, data); 4020 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[2]); 4021 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(unit, phy_ndx, data); 4022 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cs[0]); 4023 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(unit, phy_ndx, data); 4024 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cs[1]); 4025 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(unit, phy_ndx, data); 4026 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_par); 4027 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(unit, phy_ndx, data); 4028 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ras_n); 4029 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(unit, phy_ndx, data); 4030 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cas_n); 4031 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(unit, phy_ndx, data); 4032 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cke); 4033 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(unit, phy_ndx, data); 4034 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_rst_n); 4035 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(unit, phy_ndx, data); 4036 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_odt); 4037 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(unit, phy_ndx, data); 4038 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_we_n); 4039 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(unit, phy_ndx, data); 4040 data = SET_VREF_DAC_CONTROL((*config_param).control_regs_vref_dac_control); 4041 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, phy_ndx, data); 4042 4043 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[0]); 4044 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4045 { 4046 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, data); 4047 } 4048 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4049 { 4050 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr(unit, phy_ndx, data); 4051 } 4052 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4053 { 4054 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[0]); 4055 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, data); 4056 } 4057 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][0]); 4058 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 4059 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][1]); 4060 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 4061 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][2]); 4062 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 4063 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][3]); 4064 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 4065 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][4]); 4066 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 4067 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][5]); 4068 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 4069 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][6]); 4070 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 4071 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][7]); 4072 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 4073 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[0]); 4074 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 4075 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4076 { 4077 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[0]); 4078 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 4079 } 4080 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[0]); 4081 WRITE_DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 4082 4083 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[0]); 4084 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 4085 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[0]); 4086 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 4087 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][0]); 4088 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 4089 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][1]); 4090 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 4091 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][2]); 4092 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 4093 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][3]); 4094 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 4095 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][4]); 4096 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 4097 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][5]); 4098 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 4099 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][6]); 4100 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 4101 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][7]); 4102 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 4103 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[0]); 4104 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 4105 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][0]); 4106 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 4107 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][1]); 4108 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 4109 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][2]); 4110 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 4111 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][3]); 4112 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 4113 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][4]); 4114 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 4115 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][5]); 4116 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 4117 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][6]); 4118 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 4119 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][7]); 4120 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 4121 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[0]); 4122 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 4123 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[0][0]); 4124 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 4125 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[0][1]); 4126 WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 4127 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[0]); 4128 WRITE_DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr(unit, phy_ndx, data); 4129 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[0]); 4130 WRITE_DDR34_PHY_BYTE_LANE_0_READ_CONTROLr(unit, phy_ndx, data); 4131 4132 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[1]); 4133 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4134 { 4135 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, data); 4136 } 4137 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4138 { 4139 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr(unit, phy_ndx, data); 4140 } 4141 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4142 { 4143 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[1]); 4144 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, data); 4145 } 4146 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][0]); 4147 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 4148 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][1]); 4149 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 4150 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][2]); 4151 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 4152 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][3]); 4153 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 4154 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][4]); 4155 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 4156 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][5]); 4157 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 4158 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][6]); 4159 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 4160 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][7]); 4161 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 4162 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[1]); 4163 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 4164 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4165 { 4166 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[1]); 4167 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 4168 } 4169 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[1]); 4170 WRITE_DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 4171 4172 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[1]); 4173 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 4174 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[1]); 4175 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 4176 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][0]); 4177 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 4178 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][1]); 4179 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 4180 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][2]); 4181 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 4182 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][3]); 4183 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 4184 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][4]); 4185 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 4186 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][5]); 4187 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 4188 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][6]); 4189 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 4190 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][7]); 4191 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 4192 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[1]); 4193 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 4194 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][0]); 4195 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 4196 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][1]); 4197 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 4198 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][2]); 4199 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 4200 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][3]); 4201 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 4202 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][4]); 4203 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 4204 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][5]); 4205 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 4206 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][6]); 4207 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 4208 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][7]); 4209 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 4210 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[1]); 4211 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 4212 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[1][0]); 4213 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 4214 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[1][1]); 4215 WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 4216 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[1]); 4217 WRITE_DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr(unit, phy_ndx, data); 4218 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[1]); 4219 WRITE_DDR34_PHY_BYTE_LANE_1_READ_CONTROLr(unit, phy_ndx, data); 4220 4221 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 4222 { 4223 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[2]); 4224 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4225 { 4226 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, data); 4227 } 4228 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4229 { 4230 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr(unit, phy_ndx, data); 4231 } 4232 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4233 { 4234 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[2]); 4235 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, data); 4236 } 4237 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][0]); 4238 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 4239 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][1]); 4240 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 4241 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][2]); 4242 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 4243 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][3]); 4244 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 4245 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][4]); 4246 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 4247 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][5]); 4248 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 4249 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][6]); 4250 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 4251 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][7]); 4252 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 4253 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[2]); 4254 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 4255 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4256 { 4257 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[2]); 4258 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 4259 } 4260 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[2]); 4261 WRITE_DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 4262 4263 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[2]); 4264 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 4265 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[2]); 4266 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 4267 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][0]); 4268 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 4269 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][1]); 4270 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 4271 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][2]); 4272 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 4273 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][3]); 4274 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 4275 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][4]); 4276 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 4277 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][5]); 4278 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 4279 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][6]); 4280 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 4281 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][7]); 4282 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 4283 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[2]); 4284 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 4285 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][0]); 4286 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 4287 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][1]); 4288 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 4289 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][2]); 4290 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 4291 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][3]); 4292 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 4293 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][4]); 4294 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 4295 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][5]); 4296 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 4297 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][6]); 4298 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 4299 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][7]); 4300 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 4301 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[2]); 4302 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 4303 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[2][0]); 4304 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 4305 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[2][1]); 4306 WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 4307 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[2]); 4308 WRITE_DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr(unit, phy_ndx, data); 4309 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[2]); 4310 WRITE_DDR34_PHY_BYTE_LANE_2_READ_CONTROLr(unit, phy_ndx, data); 4311 4312 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[3]); 4313 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4314 { 4315 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr(unit, phy_ndx, data); 4316 } 4317 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4318 { 4319 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr(unit, phy_ndx, data); 4320 } 4321 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4322 { 4323 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[3]); 4324 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr(unit, phy_ndx, data); 4325 } 4326 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][0]); 4327 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(unit, phy_ndx, data); 4328 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][1]); 4329 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(unit, phy_ndx, data); 4330 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][2]); 4331 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(unit, phy_ndx, data); 4332 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][3]); 4333 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(unit, phy_ndx, data); 4334 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][4]); 4335 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(unit, phy_ndx, data); 4336 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][5]); 4337 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(unit, phy_ndx, data); 4338 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][6]); 4339 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(unit, phy_ndx, data); 4340 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][7]); 4341 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(unit, phy_ndx, data); 4342 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[3]); 4343 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(unit, phy_ndx, data); 4344 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4345 { 4346 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[3]); 4347 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(unit, phy_ndx, data); 4348 } 4349 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[3]); 4350 WRITE_DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr(unit, phy_ndx, data); 4351 4352 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[3]); 4353 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(unit, phy_ndx, data); 4354 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[3]); 4355 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(unit, phy_ndx, data); 4356 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][0]); 4357 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(unit, phy_ndx, data); 4358 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][1]); 4359 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(unit, phy_ndx, data); 4360 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][2]); 4361 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(unit, phy_ndx, data); 4362 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][3]); 4363 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(unit, phy_ndx, data); 4364 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][4]); 4365 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(unit, phy_ndx, data); 4366 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][5]); 4367 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(unit, phy_ndx, data); 4368 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][6]); 4369 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(unit, phy_ndx, data); 4370 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][7]); 4371 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(unit, phy_ndx, data); 4372 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[3]); 4373 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(unit, phy_ndx, data); 4374 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][0]); 4375 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(unit, phy_ndx, data); 4376 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][1]); 4377 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(unit, phy_ndx, data); 4378 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][2]); 4379 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(unit, phy_ndx, data); 4380 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][3]); 4381 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(unit, phy_ndx, data); 4382 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][4]); 4383 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(unit, phy_ndx, data); 4384 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][5]); 4385 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(unit, phy_ndx, data); 4386 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][6]); 4387 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(unit, phy_ndx, data); 4388 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][7]); 4389 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(unit, phy_ndx, data); 4390 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[3]); 4391 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(unit, phy_ndx, data); 4392 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[3][0]); 4393 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(unit, phy_ndx, data); 4394 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[3][1]); 4395 WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(unit, phy_ndx, data); 4396 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[3]); 4397 WRITE_DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr(unit, phy_ndx, data); 4398 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[3]); 4399 WRITE_DDR34_PHY_BYTE_LANE_3_READ_CONTROLr(unit, phy_ndx, data); 4400 } 4401 4402 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4403 4404 data = 0; 4405 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1); 4406 WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(unit, phy_ndx, data); 4407 WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(unit, phy_ndx, data); 4408 4409 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 4410 { 4411 WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(unit, phy_ndx, data); 4412 WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(unit, phy_ndx, data); 4413 } 4414 4415 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4416 4417 return SOC_E_NONE; 4418 } 4419 4420 /* 4421 * Function: 4422 * soc_and28_shmoo_ctl 4423 * Purpose: 4424 * Perform shmoo (PHY calibration) on specific DRC index. 4425 * Parameters: 4426 * unit - unit number 4427 * phy_ndx - DRC index to perform shmoo on. 4428 * shmoo_type - Selects shmoo sub-section to be performs (-1 for full shmoo) 4429 * flags - SHMOO_AND28_CTL_FLAGS_STAT_BIT 4430 * 0: Runs normal shmoo functions 4431 * 1: Doesn't run shmoo. Only prints statistics. (Nothing is printed at the moment) 4432 * SHMOO_AND28_CTL_FLAGS_PLOT_BIT 4433 * 0: No shmoo plots are printed during shmoo 4434 * 1: Shmoo plots are printed during shmoo 4435 * SHMOO_AND28_CTL_FLAGS_EXT_VREF_RANGE_BIT (Not implemented at the moment) 4436 * 0: Shmoo runs with a regular range for Vref sweep in *EXTENDED shmoos 4437 * 1: Shmoo runs with an extended range for Vref sweep in *EXTENDED shmoos 4438 * action - Save/restore functionality 4439 * *config_param - PHY configuration saved/restored 4440 * Returns: 4441 * SOC_E_XXX 4442 * This routine may be called after a device is attached 4443 * or whenever a chip reset is required. 4444 */ 4445 4446 int 4447 soc_and28_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, uint32 flags, int action, and28_shmoo_config_param_t *config_param) 4448 { 4449 and28_shmoo_container_t *scPtr = NULL; 4450 uint32 dramType; 4451 uint32 ctlType; 4452 uint32 i; 4453 int ndx, ndxEnd; 4454 uint32 stat, plot; 4455 const uint32 *seqPtr; 4456 uint32 seqCount; 4457 4458 dramType = shmoo_dram_info.dram_type; 4459 ctlType = shmoo_dram_info.ctl_type; 4460 4461 stat = flags & SHMOO_AND28_CTL_FLAGS_STAT_BIT; 4462 plot = flags & SHMOO_AND28_CTL_FLAGS_PLOT_BIT; 4463 4464 if(!stat) 4465 { 4466 scPtr = sal_alloc(sizeof(and28_shmoo_container_t), "AND28 Shmoo Container"); 4467 if(scPtr == NULL) 4468 { 4469 return SOC_E_MEMORY; 4470 } 4471 sal_memset(scPtr, 0, sizeof(and28_shmoo_container_t)); 4472 4473 (*scPtr).debugMode = flags & SHMOO_AND28_DEBUG_MODE_FLAG_BITS; 4474 4475 if(phy_ndx != SHMOO_AND28_INTERFACE_RSVP) 4476 { 4477 ndx = phy_ndx; 4478 ndxEnd = phy_ndx + 1; 4479 } 4480 else 4481 { 4482 ndx = 0; 4483 ndxEnd = SHMOO_AND28_MAX_INTERFACES; 4484 } 4485 4486 for(; ndx < ndxEnd; ndx++) 4487 { 4488 if(!_shmoo_and28_check_dram(ndx)) { 4489 continue; 4490 } 4491 4492 (*scPtr).restore = 0; 4493 4494 if(action == SHMOO_AND28_ACTION_RESTORE) 4495 { 4496 (*scPtr).restore = 1; 4497 switch(ctlType) 4498 { 4499 case SHMOO_AND28_CTL_TYPE_RSVP: 4500 break; 4501 case SHMOO_AND28_CTL_TYPE_1: 4502 _shmoo_and28_restore(unit, phy_ndx, config_param); 4503 break; 4504 default: 4505 if(scPtr != NULL) 4506 { 4507 sal_free(scPtr); 4508 } 4509 4510 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported controller type: %02lu\n"), (long unsigned int)ctlType)); 4511 return SOC_E_FAIL; 4512 } 4513 } 4514 else if((action == SHMOO_AND28_ACTION_RUN) || (action == SHMOO_AND28_ACTION_RUN_AND_SAVE)) 4515 { 4516 switch(ctlType) 4517 { 4518 case SHMOO_AND28_CTL_TYPE_RSVP: 4519 break; 4520 case SHMOO_AND28_CTL_TYPE_1: 4521 switch(dramType) 4522 { 4523 case SHMOO_AND28_DRAM_TYPE_DDR3: 4524 seqPtr = &shmoo_order_and28_ddr3[0]; 4525 seqCount = SHMOO_AND28_DDR3_SEQUENCE_COUNT; 4526 break; 4527 case SHMOO_AND28_DRAM_TYPE_DDR3L: 4528 seqPtr = &shmoo_order_and28_ddr3l[0]; 4529 seqCount = SHMOO_AND28_DDR3L_SEQUENCE_COUNT; 4530 break; 4531 case SHMOO_AND28_DRAM_TYPE_DDR4: 4532 seqPtr = &shmoo_order_and28_ddr4[0]; 4533 seqCount = SHMOO_AND28_DDR4_SEQUENCE_COUNT; 4534 break; 4535 default: 4536 if(scPtr != NULL) 4537 { 4538 sal_free(scPtr); 4539 } 4540 4541 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported dram type: %02lu\n"), (long unsigned int)dramType)); 4542 return SOC_E_FAIL; 4543 } 4544 4545 (*scPtr).dramType = dramType; 4546 (*scPtr).ctlType = ctlType; 4547 4548 if(shmoo_type != SHMOO_AND28_SHMOO_RSVP) 4549 { 4550 (*scPtr).shmooType = shmoo_type; 4551 _shmoo_and28_entry(unit, ndx, scPtr, SHMOO_AND28_SINGLE); 4552 _shmoo_and28_do(unit, ndx, scPtr); 4553 _shmoo_and28_calib_2D(unit, ndx, scPtr); 4554 _shmoo_and28_set_new_step(unit, ndx, scPtr); 4555 if(plot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) 4556 { 4557 _shmoo_and28_plot(unit, ndx, scPtr); 4558 } 4559 _shmoo_and28_exit(unit, ndx, scPtr, SHMOO_AND28_SINGLE); 4560 } 4561 else 4562 { 4563 for(i = 0; i < seqCount; i++) 4564 { 4565 (*scPtr).shmooType = seqPtr[i]; 4566 _shmoo_and28_entry(unit, ndx, scPtr, SHMOO_AND28_SEQUENTIAL); 4567 _shmoo_and28_do(unit, ndx, scPtr); 4568 _shmoo_and28_calib_2D(unit, ndx, scPtr); 4569 _shmoo_and28_set_new_step(unit, ndx, scPtr); 4570 if(plot || LOG_CHECK(BSL_LS_SOC_DDR | BSL_INFO)) 4571 { 4572 _shmoo_and28_plot(unit, ndx, scPtr); 4573 } 4574 _shmoo_and28_exit(unit, ndx, scPtr, SHMOO_AND28_SEQUENTIAL); 4575 } 4576 } 4577 4578 break; 4579 default: 4580 if(scPtr != NULL) 4581 { 4582 sal_free(scPtr); 4583 } 4584 4585 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported controller type: %02lu\n"), (long unsigned int)ctlType)); 4586 return SOC_E_FAIL; 4587 } 4588 } 4589 4590 if((action == SHMOO_AND28_ACTION_RUN_AND_SAVE) || (action == SHMOO_AND28_ACTION_SAVE)) 4591 { 4592 _shmoo_and28_save(unit, phy_ndx, config_param); 4593 } 4594 } 4595 4596 if(scPtr != NULL) 4597 { 4598 sal_free(scPtr); 4599 } 4600 4601 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "DDR Tuning Complete\n"))); 4602 } 4603 else 4604 { 4605 /* Report only */ 4606 switch(ctlType) 4607 { 4608 case SHMOO_AND28_CTL_TYPE_RSVP: 4609 break; 4610 case SHMOO_AND28_CTL_TYPE_1: 4611 break; 4612 default: 4613 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported controller type: %02lu\n"), (long unsigned int)ctlType)); 4614 return SOC_E_FAIL; 4615 } 4616 } 4617 return SOC_E_NONE; 4618 } 4619 4620 /* Set Dram Parameters/Info to Shmoo driver */ 4621 int 4622 soc_and28_shmoo_dram_info_set(int unit, CONST and28_shmoo_dram_info_t *sdi) 4623 { 4624 shmoo_dram_info.ctl_type = sdi->ctl_type; 4625 shmoo_dram_info.dram_type = sdi->dram_type; 4626 shmoo_dram_info.dram_bitmap = sdi->dram_bitmap; 4627 shmoo_dram_info.interface_bitwidth = sdi->interface_bitwidth; 4628 shmoo_dram_info.split_bus = sdi->split_bus; 4629 shmoo_dram_info.num_columns = sdi->num_columns; 4630 shmoo_dram_info.num_rows = sdi->num_rows; 4631 shmoo_dram_info.num_banks = sdi->num_banks; 4632 shmoo_dram_info.num_bank_groups = sdi->num_bank_groups; 4633 shmoo_dram_info.data_rate_mbps = sdi->data_rate_mbps; 4634 shmoo_dram_info.ref_clk_mhz = sdi->ref_clk_mhz; 4635 shmoo_dram_info.refi = sdi->refi; 4636 shmoo_dram_info.command_parity_latency = sdi->command_parity_latency; 4637 shmoo_dram_info.sim_system_mode = sdi->sim_system_mode; 4638 4639 return SOC_E_NONE; 4640 } 4641 4642 /* Configure PHY PLL and wait for lock */ 4643 int 4644 _and28_phy_cfg_pll(int unit, int phy_ndx) 4645 { 4646 int ndx, ndxEnd; 4647 uint32 data; 4648 uint32 timeout; 4649 uint32 pll_config; 4650 uint32 pll_control2; 4651 uint32 pll_dividers; 4652 uint32 pll_frac_divider; 4653 4654 if(shmoo_dram_info.ref_clk_mhz != 50) 4655 { 4656 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Unsupported reference flock frequency: %4d MHz\n"), shmoo_dram_info.ref_clk_mhz)); 4657 return SOC_E_FAIL; 4658 } 4659 4660 pll_config = 0x00000000; 4661 switch(shmoo_dram_info.data_rate_mbps) 4662 { 4663 case 800: 4664 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4665 { 4666 pll_config = 0x018D0012; 4667 } 4668 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4669 { 4670 pll_config = 0x01890012; 4671 } 4672 pll_control2 = 0x94000000; 4673 pll_dividers = 0x004030C0; 4674 pll_frac_divider = 0x00000000; 4675 break; 4676 case 1066: 4677 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4678 { 4679 pll_config = 0x018D0012; 4680 } 4681 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4682 { 4683 pll_config = 0x01890012; 4684 } 4685 pll_control2 = 0x94000000; 4686 pll_dividers = 0x003030BF; 4687 pll_frac_divider = 0x000E147A; 4688 break; 4689 case 1333: 4690 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4691 { 4692 pll_config = 0x018D0012; 4693 } 4694 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4695 { 4696 pll_config = 0x01890012; 4697 } 4698 pll_control2 = 0x94000000; 4699 pll_dividers = 0x002030A0; 4700 pll_frac_divider = 0x000147AE; 4701 break; 4702 case 1600: 4703 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 4704 { 4705 pll_config = 0x018D0012; 4706 } 4707 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 4708 { 4709 pll_config = 0x01890012; 4710 } 4711 pll_control2 = 0x94000000; 4712 pll_dividers = 0x002030C0; 4713 pll_frac_divider = 0x00000000; 4714 break; 4715 default: 4716 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Unsupported data rate: %4d Mbps\n"), shmoo_dram_info.data_rate_mbps)); 4717 return SOC_E_FAIL; 4718 } 4719 4720 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " PHY PLL Configuration\n"))); 4721 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Fref.............: %4d MHz\n"), shmoo_dram_info.ref_clk_mhz)); 4722 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Data rate........: %4d Mbps\n"), shmoo_dram_info.data_rate_mbps)); 4723 4724 if(phy_ndx != SHMOO_AND28_INTERFACE_RSVP) 4725 { 4726 ndx = phy_ndx; 4727 ndxEnd = phy_ndx + 1; 4728 } 4729 else 4730 { 4731 ndx = 0; 4732 ndxEnd = SHMOO_AND28_MAX_INTERFACES; 4733 } 4734 4735 for(; ndx < ndxEnd; ndx++) 4736 { 4737 if(!_shmoo_and28_check_dram(ndx)) 4738 { 4739 continue; 4740 } 4741 4742 WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(unit, phy_ndx, pll_config); 4743 WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r(unit, phy_ndx, pll_control2); 4744 WRITE_DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr(unit, phy_ndx, pll_dividers); 4745 WRITE_DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr(unit, phy_ndx, pll_frac_divider); 4746 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4747 4748 READ_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(unit, phy_ndx, &data); 4749 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, PLL_CONFIG, RESET, 0); 4750 WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(unit, phy_ndx, data); 4751 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4752 4753 timeout = 2000; 4754 do 4755 { 4756 READ_DDR34_PHY_CONTROL_REGS_PLL_STATUSr(unit, phy_ndx, &data); 4757 4758 if(DDR34_GET_FIELD(data, DDR34_PHY_CONTROL_REGS, PLL_STATUS, LOCK)) 4759 { 4760 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " PLL locked.\n"))); 4761 break; 4762 } 4763 4764 if (timeout == 0) 4765 { 4766 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, " PLL not locked!!! (Timeout)\n"))); 4767 return SOC_E_TIMEOUT; 4768 } 4769 4770 timeout--; 4771 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4772 } 4773 while(TRUE); 4774 4775 READ_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(unit, phy_ndx, &data); 4776 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, PLL_CONFIG, RESET_POST_DIV, 0); 4777 WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(unit, phy_ndx, data); 4778 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4779 } 4780 4781 return SOC_E_NONE; 4782 } 4783 4784 int 4785 soc_and28_shmoo_phy_init(int unit, int phy_ndx) 4786 { 4787 int ndx, ndxEnd; 4788 uint32 data; 4789 uint32 dfi_ctrl; 4790 uint32 dram_config; 4791 uint32 dram_timing1; 4792 uint32 dram_timing2; 4793 uint32 dram_timing3; 4794 uint32 dram_timing4; 4795 uint32 step1000, size1000UI, sizeUI; 4796 and28_step_size_t ss; 4797 4798 if(phy_ndx != SHMOO_AND28_INTERFACE_RSVP) 4799 { 4800 ndx = phy_ndx; 4801 ndxEnd = phy_ndx + 1; 4802 } 4803 else 4804 { 4805 ndx = 0; 4806 ndxEnd = SHMOO_AND28_MAX_INTERFACES; 4807 } 4808 4809 for(; ndx < ndxEnd; ndx++) 4810 { 4811 if(!_shmoo_and28_check_dram(ndx)) 4812 { 4813 continue; 4814 } 4815 4816 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A Series - PHY Initialization (PHY index: %02d)\n"), ndx)); 4817 4818 /*A00*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A00. Detect PHY type\n"))); 4819 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_RSVP) 4820 { 4821 DDR34_REG_READ(unit, ndx, 0x00, 0x00000000, &data); 4822 SHMOO_AND28_PHY_TYPE = (data >> 8) & 0xFF; 4823 4824 switch(SHMOO_AND28_PHY_TYPE) 4825 { 4826 case SHMOO_AND28_PHY_TYPE_E0: 4827 INIT_DDR34_E0_PHY_REGS_TABLE(); 4828 INIT_DDR34_E0_PHY_FIELDS_TABLE(); 4829 break; 4830 case SHMOO_AND28_PHY_TYPE_F0: 4831 INIT_DDR34_F0_PHY_REGS_TABLE(); 4832 INIT_DDR34_F0_PHY_FIELDS_TABLE(); 4833 break; 4834 default: 4835 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported PHY type: %02X\n\n"), SHMOO_AND28_PHY_TYPE)); 4836 return SOC_E_FAIL; 4837 } 4838 } 4839 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " PHY type.........: %02X\n"), SHMOO_AND28_PHY_TYPE)); 4840 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4841 4842 /*A01*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A01. Acquire PHY control\n"))); 4843 dfi_ctrl = 0; 4844 DDR34_SET_FIELD(dfi_ctrl, DDR34_PHY_CONTROL_REGS, DFI_CNTRL, ASSERT_REQ, 1); 4845 DDR34_SET_FIELD(dfi_ctrl, DDR34_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CS0, 1); 4846 DDR34_SET_FIELD(dfi_ctrl, DDR34_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CS1, 1); 4847 DDR34_SET_FIELD(dfi_ctrl, DDR34_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CKE, 0); 4848 WRITE_DDR34_PHY_CONTROL_REGS_DFI_CNTRLr(unit, ndx, dfi_ctrl); 4849 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 4850 4851 /*A02*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A02. Configure timing parameters\n"))); 4852 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 4853 { 4854 switch(shmoo_dram_info.data_rate_mbps) 4855 { 4856 case 800: 4857 dram_timing1 = 0x0F040606; 4858 dram_timing2 = 0x04060506; 4859 dram_timing3 = 0x00044068; 4860 dram_timing4 = 0x00000000; 4861 break; 4862 case 1066: 4863 dram_timing1 = 0x14040707; 4864 dram_timing2 = 0x04080607; 4865 dram_timing3 = 0x0004408C; 4866 dram_timing4 = 0x00000000; 4867 break; 4868 case 1333: 4869 dram_timing1 = 0x18050909; 4870 dram_timing2 = 0x050A0709; 4871 dram_timing3 = 0x000450B0; 4872 dram_timing4 = 0x00000000; 4873 break; 4874 case 1600: 4875 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 4876 { 4877 dram_timing1 = 0x1C000C0C; 4878 switch(shmoo_dram_info.num_bank_groups) 4879 { 4880 case 2: dram_timing1 |= 0x00060000; break; 4881 case 4: dram_timing1 |= 0x00050000; break; 4882 default: 4883 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported number of bank groups: %d\n"), shmoo_dram_info.num_bank_groups)); 4884 return SOC_E_FAIL; 4885 } 4886 dram_timing2 = 0x060C090A; 4887 dram_timing3 = 0x003460D0; 4888 dram_timing4 = 0x00000000; 4889 } 4890 else 4891 { 4892 dram_timing1 = 0x1C060B0B; 4893 dram_timing2 = 0x060C080B; 4894 dram_timing3 = 0x000460D0; 4895 dram_timing4 = 0x00000000; 4896 } 4897 break; 4898 default: 4899 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported data rate: %4d Mbps\n"), shmoo_dram_info.data_rate_mbps)); 4900 return SOC_E_FAIL; 4901 } 4902 } 4903 else 4904 { 4905 switch(shmoo_dram_info.data_rate_mbps) 4906 { 4907 case 800: 4908 dram_timing1 = 0x0F040606; 4909 dram_timing2 = 0x04060506; 4910 dram_timing3 = 0x00044068; 4911 dram_timing4 = 0x00000000; 4912 break; 4913 case 1066: 4914 dram_timing1 = 0x14040707; 4915 dram_timing2 = 0x04080607; 4916 dram_timing3 = 0x0004408C; 4917 dram_timing4 = 0x00000000; 4918 break; 4919 case 1333: 4920 dram_timing1 = 0x18040909; 4921 dram_timing2 = 0x050A0709; 4922 dram_timing3 = 0x000450B0; 4923 dram_timing4 = 0x00000000; 4924 break; 4925 case 1600: 4926 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 4927 { 4928 dram_timing1 = 0x1C000C0C; 4929 switch(shmoo_dram_info.num_bank_groups) 4930 { 4931 case 2: dram_timing1 |= 0x00060000; break; 4932 case 4: dram_timing1 |= 0x00050000; break; 4933 default: 4934 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported number of bank groups: %d\n"), shmoo_dram_info.num_bank_groups)); 4935 return SOC_E_FAIL; 4936 } 4937 dram_timing2 = 0x060C090A; 4938 dram_timing3 = 0x003460D0; 4939 dram_timing4 = 0x00000000; 4940 } 4941 else 4942 { 4943 dram_timing1 = 0x1C050B0B; 4944 dram_timing2 = 0x060C080B; 4945 dram_timing3 = 0x000460D0; 4946 dram_timing4 = 0x00000000; 4947 } 4948 break; 4949 default: 4950 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported data rate: %4d Mbps\n"), shmoo_dram_info.data_rate_mbps)); 4951 return SOC_E_FAIL; 4952 } 4953 } 4954 4955 dram_config = 0x00001000; 4956 if(shmoo_dram_info.split_bus) 4957 { 4958 dram_config |= 0x04000000; 4959 if(shmoo_dram_info.interface_bitwidth <= 8) 4960 { 4961 dram_config |= 0x02000000; 4962 } 4963 } 4964 else 4965 { 4966 if(shmoo_dram_info.interface_bitwidth <= 16) 4967 { 4968 dram_config |= 0x02000000; 4969 } 4970 if(shmoo_dram_info.interface_bitwidth <= 8) 4971 { 4972 dram_config |= 0x01000000; 4973 } 4974 } 4975 switch(shmoo_dram_info.dram_type) 4976 { 4977 case SHMOO_AND28_DRAM_TYPE_DDR3: dram_config |= 0x00000000; break; 4978 case SHMOO_AND28_DRAM_TYPE_DDR3L: dram_config |= 0x00000000; break; 4979 case SHMOO_AND28_DRAM_TYPE_DDR4: dram_config |= 0x00000001; break; 4980 default: 4981 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported dram type: %d\n"), shmoo_dram_info.dram_type)); 4982 return SOC_E_FAIL; 4983 } 4984 switch(shmoo_dram_info.num_rows) 4985 { 4986 case 4096: dram_config |= 0x00000000; break; 4987 case 8192: dram_config |= 0x00000010; break; 4988 case 16384: dram_config |= 0x00000020; break; 4989 case 32768: dram_config |= 0x00000030; break; 4990 case 65536: dram_config |= 0x00000040; break; 4991 default: 4992 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported number of rows: %d\n"), shmoo_dram_info.num_rows)); 4993 return SOC_E_FAIL; 4994 } 4995 switch(shmoo_dram_info.num_columns) 4996 { 4997 case 512: dram_config |= 0x00000000; break; 4998 case 1024: dram_config |= 0x00000100; break; 4999 case 2048: dram_config |= 0x00000200; break; 5000 default: 5001 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported number of columns: %d\n"), shmoo_dram_info.num_columns)); 5002 return SOC_E_FAIL; 5003 } 5004 switch(shmoo_dram_info.num_banks) 5005 { 5006 case 4: dram_config |= 0x00000000; break; 5007 case 8: dram_config |= 0x00000400; break; 5008 default: 5009 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported number of banks: %d\n"), shmoo_dram_info.num_banks)); 5010 return SOC_E_FAIL; 5011 } 5012 switch(shmoo_dram_info.num_bank_groups) 5013 { 5014 case 2: dram_config |= 0x00000000; break; 5015 case 4: dram_config |= 0x00001000; break; 5016 default: 5017 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Unsupported number of bank groups: %d\n"), shmoo_dram_info.num_bank_groups)); 5018 return SOC_E_FAIL; 5019 } 5020 5021 WRITE_DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr(unit, ndx, dram_config); 5022 WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r(unit, ndx, dram_timing1); 5023 WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r(unit, ndx, dram_timing2); 5024 WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r(unit, ndx, dram_timing3); 5025 WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r(unit, ndx, dram_timing4); 5026 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5027 5028 /*A03*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A03. Configure PHY PLL\n"))); 5029 _and28_phy_cfg_pll(unit, ndx); 5030 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5031 5032 /*A04*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A04. Configure reference voltage\n"))); 5033 /*R04*/ READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ndx, &data); 5034 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 5035 { 5036 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32); 5037 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 44); 5038 } 5039 else 5040 { 5041 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32); 5042 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 32); 5043 } 5044 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ndx, data); 5045 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5046 5047 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN0, 0); 5048 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN1, 0); 5049 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN2, 0); 5050 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN3, 0); 5051 WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(unit, ndx, data); 5052 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5053 5054 /*A05*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A05. Compute VDL step size\n"))); 5055 _and28_calculate_step_size(unit, ndx, &ss); 5056 5057 step1000 = ss.step1000; 5058 size1000UI = ss.size1000UI; 5059 sizeUI = size1000UI / 1000; 5060 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " VDL calibration complete.\n"))); 5061 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " VDL step size....: %3lu.%03lu ps\n"), (long unsigned int)(step1000 / 1000), (long unsigned int)(step1000 % 1000))); 5062 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " UI size..........: %3lu.%03lu steps\n"), (long unsigned int)sizeUI, (long unsigned int)(size1000UI % 1000))); 5063 5064 /*A06*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A06. Configure ADDR/CTRL VDLs\n"))); 5065 data = 0; 5066 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1); 5067 if(sizeUI > SHMOO_AND28_MAX_VDL_LENGTH) 5068 { 5069 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1); 5070 } 5071 else 5072 { 5073 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, sizeUI); 5074 } 5075 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(unit, ndx, data); 5076 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(unit, ndx, data); 5077 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(unit, ndx, data); 5078 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(unit, ndx, data); 5079 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(unit, ndx, data); 5080 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(unit, ndx, data); 5081 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(unit, ndx, data); 5082 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(unit, ndx, data); 5083 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(unit, ndx, data); 5084 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(unit, ndx, data); 5085 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(unit, ndx, data); 5086 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(unit, ndx, data); 5087 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(unit, ndx, data); 5088 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(unit, ndx, data); 5089 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(unit, ndx, data); 5090 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(unit, ndx, data); 5091 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(unit, ndx, data); 5092 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(unit, ndx, data); 5093 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(unit, ndx, data); 5094 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(unit, ndx, data); 5095 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(unit, ndx, data); 5096 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(unit, ndx, data); 5097 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(unit, ndx, data); 5098 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(unit, ndx, data); 5099 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(unit, ndx, data); 5100 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(unit, ndx, data); 5101 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(unit, ndx, data); 5102 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(unit, ndx, data); 5103 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(unit, ndx, data); 5104 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(unit, ndx, data); 5105 WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(unit, ndx, data); 5106 5107 /*A07*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A07. Disable Virtual VTT\n"))); 5108 READ_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(unit, ndx, &data); 5109 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CTL_IDLE, 0); 5110 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CS_IDLE, 0); 5111 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CKE_IDLE, 0); 5112 WRITE_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(unit, ndx, data); 5113 5114 /*A08*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A08. ZQ calibration\n"))); 5115 /*R08*/ if(shmoo_dram_info.sim_system_mode) 5116 { 5117 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, " Skipped for emulation\n"))); 5118 5119 goto SHMOO_AND28_ZQ_CALIBRATION_END; 5120 } 5121 5122 _and28_zq_calibration(unit, ndx); 5123 5124 SHMOO_AND28_ZQ_CALIBRATION_END: 5125 5126 /*A09*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A09. Configure Static Pad Control\n"))); 5127 READ_DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr(unit, ndx, &data); 5128 if(shmoo_dram_info.split_bus) 5129 { 5130 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, STATIC_PAD_CTL, IDDQ_CLK1, 0); 5131 } 5132 else 5133 { 5134 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, STATIC_PAD_CTL, IDDQ_CLK1, 1); 5135 } 5136 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 5137 { 5138 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, STATIC_PAD_CTL, AUTO_OEB, 0); 5139 } 5140 else 5141 { 5142 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, STATIC_PAD_CTL, AUTO_OEB, 1); 5143 } 5144 if(shmoo_dram_info.split_bus) 5145 { 5146 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, STATIC_PAD_CTL, IDDQ_CS1, 0); 5147 } 5148 else 5149 { 5150 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, STATIC_PAD_CTL, IDDQ_CS1, 1); 5151 } 5152 WRITE_DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr(unit, ndx, data); 5153 5154 if(shmoo_dram_info.dram_type == SHMOO_AND28_DRAM_TYPE_DDR4) 5155 { 5156 READ_DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr(unit, ndx, &data); 5157 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, STATIC_PAD_CTL, DM_INVERT, 0); 5158 WRITE_DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr(unit, ndx, data); 5159 WRITE_DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr(unit, ndx, data); 5160 5161 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 5162 { 5163 WRITE_DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr(unit, ndx, data); 5164 WRITE_DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr(unit, ndx, data); 5165 } 5166 5167 READ_DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr(unit, ndx, &data); 5168 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, ABI_PAR_CNTRL, PAR_ENABLE, 1); 5169 WRITE_DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr(unit, ndx, data); 5170 } 5171 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5172 5173 /*A10*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A10. Configure ODT\n"))); 5174 data = 0; 5175 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 5176 { 5177 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT_FORCE, 1); 5178 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT_FORCE_VALUE, 1); 5179 } 5180 else if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 5181 { 5182 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT0_FORCE, 1); 5183 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT0_FORCE_VALUE, 1); 5184 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT1_FORCE, 1); 5185 DDR34_SET_FIELD(data, DDR34_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT1_FORCE_VALUE, 1); 5186 } 5187 WRITE_DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr(unit, ndx, data); 5188 5189 data = 0; 5190 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_ENABLE, 1); 5191 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_DELAY, 0); 5192 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_POST_LENGTH, 2); 5193 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_PRE_LENGTH, 4); 5194 WRITE_DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr(unit, ndx, data); 5195 WRITE_DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr(unit, ndx, data); 5196 5197 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 5198 { 5199 WRITE_DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr(unit, ndx, data); 5200 WRITE_DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr(unit, ndx, data); 5201 } 5202 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5203 5204 /*A11*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A11. Configure Write Pre-/Post-amble\n"))); 5205 READ_DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr(unit, ndx, &data); 5206 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQ_POSTAM_BITS, 1); 5207 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQ_PREAM_BITS, 1); 5208 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS, 0xE); 5209 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS_POSTAM_BITS, 0); 5210 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS_PREAM_BITS, 2); 5211 WRITE_DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr(unit, ndx, data); 5212 WRITE_DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr(unit, ndx, data); 5213 5214 if((shmoo_dram_info.interface_bitwidth == 32) || (_shmoo_and28_check_dram(phy_ndx) > 1)) 5215 { 5216 WRITE_DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr(unit, ndx, data); 5217 WRITE_DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr(unit, ndx, data); 5218 } 5219 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5220 5221 /*A12*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A12. Configure Auto Idle\n"))); 5222 READ_DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr(unit, ndx, &data); 5223 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE, 0); 5224 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE, 0); 5225 WRITE_DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr(unit, ndx, data); 5226 WRITE_DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr(unit, ndx, data); 5227 5228 if((shmoo_dram_info.interface_bitwidth != 32) && !(_shmoo_and28_check_dram(phy_ndx) > 1)) 5229 { 5230 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, IDLE, 1); 5231 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, RXENB, 1); 5232 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, IDDQ, 1); 5233 5234 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_E0) 5235 { 5236 DDR34_SET_FIELD(data, DDR34_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, IO_IDLE_ENABLE, 0x7FF); 5237 } 5238 } 5239 WRITE_DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr(unit, ndx, data); 5240 WRITE_DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr(unit, ndx, data); 5241 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5242 5243 if(SHMOO_AND28_PHY_TYPE == SHMOO_AND28_PHY_TYPE_F0) 5244 { 5245 WRITE_DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr(unit, ndx, 0); 5246 } 5247 5248 /*A13*/ LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A13. Release PHY control\n"))); 5249 WRITE_DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr(unit, ndx, 0); 5250 DDR34_SET_FIELD(dfi_ctrl, DDR34_PHY_CONTROL_REGS, DFI_CNTRL, ASSERT_REQ, 0); 5251 WRITE_DDR34_PHY_CONTROL_REGS_DFI_CNTRLr(unit, ndx, dfi_ctrl); 5252 sal_usleep(SHMOO_AND28_SHORT_SLEEP); 5253 5254 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "A Series - PHY Initialization complete (PHY index: %02d)\n"), ndx)); 5255 } 5256 5257 return SOC_E_NONE; 5258 } 5259 5260 /* Register Device interface CB to shmoo */ 5261 int 5262 soc_and28_shmoo_interface_cb_register(int unit, and28_shmoo_cbi_t shmoo_cbi) 5263 { 5264 soc_and28_phy_reg_read = shmoo_cbi.and28_phy_reg_read; 5265 soc_and28_phy_reg_write = shmoo_cbi.and28_phy_reg_write; 5266 soc_and28_phy_reg_modify = shmoo_cbi.and28_phy_reg_modify; 5267 _shmoo_and28_drc_bist_conf_set = shmoo_cbi.and28_drc_bist_conf_set; 5268 _shmoo_and28_drc_bist_err_cnt = shmoo_cbi.and28_drc_bist_err_cnt; 5269 _shmoo_and28_drc_dram_init = shmoo_cbi.and28_drc_dram_init; 5270 5271 if(!_shmoo_and28_validate_cbi()) 5272 { 5273 LOG_ERROR(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Null callback function detected during CBI registration\n"))); 5274 return SOC_E_FAIL; 5275 } 5276 5277 return SOC_E_NONE; 5278 } 5279 5280 #endif /* BCM_AND28_SUPPORT */