memtest.c (185280B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Memory Test Kernel 8 * 9 * Streamlined module designed for inclusion in the SOC driver for 10 * performing power-on memory tests. 11 * 12 * This module is also used by the main SOC diagnostics memory tests, 13 * fronted by user interface code. 14 */ 15 16 #include <shared/bsl.h> 17 18 #include <sal/core/libc.h> 19 20 #include <soc/cm.h> 21 #include <soc/mem.h> 22 #include <soc/debug.h> 23 #include <soc/drv.h> 24 #ifdef BCM_BRADLEY_SUPPORT 25 #include <soc/bradley.h> 26 #endif 27 #if defined(BCM_TRIUMPH2_SUPPORT) 28 #include <soc/triumph2.h> 29 #endif /* BCM_TRIUMPH2_SUPPORT */ 30 #if defined(BCM_TRIUMPH3_SUPPORT) 31 #include <soc/triumph3.h> 32 #endif /* BCM_TRIUMPH3_SUPPORT */ 33 #if defined(BCM_TRIDENT_SUPPORT) 34 #include <soc/trident.h> 35 #endif /* BCM_TRIDENT_SUPPORT */ 36 #if defined(BCM_MONTEREY_SUPPORT) 37 #include <soc/monterey.h> 38 #endif /* BCM_MONTEREY_SUPPORT */ 39 #if defined(BCM_APACHE_SUPPORT) 40 #include <soc/apache.h> 41 #endif /* BCM_APACHE_SUPPORT */ 42 #if defined(BCM_TRIDENT2_SUPPORT) 43 #include <soc/trident2.h> 44 #endif /* BCM_TRIDENT_SUPPORT */ 45 #if defined(BCM_ENDURO_SUPPORT) 46 #include <soc/enduro.h> 47 #endif /* BCM_ENDURO_SUPPORT */ 48 #if defined(BCM_HURRICANE_SUPPORT) 49 #include <soc/hurricane.h> 50 #endif /* BCM_HURRICANE_SUPPORT */ 51 #if defined(BCM_HURRICANE2_SUPPORT) 52 #include <soc/hurricane2.h> 53 #endif /* BCM_HURRICANE2_SUPPORT */ 54 #if defined(BCM_HURRICANE3_SUPPORT) 55 #include <soc/hurricane3.h> 56 #endif /* BCM_HURRICANE3_SUPPORT */ 57 #if defined(BCM_GREYHOUND_SUPPORT) 58 #include <soc/greyhound.h> 59 #endif /* BCM_GREYHOUND_SUPPORT */ 60 #if defined(BCM_GREYHOUND2_SUPPORT) 61 #include <soc/greyhound2.h> 62 #endif /* BCM_GREYHOUND2_SUPPORT */ 63 #if defined(BCM_KATANA_SUPPORT) 64 #include <soc/katana.h> 65 #endif /* BCM_KATANA_SUPPORT */ 66 #if defined(BCM_KATANA2_SUPPORT) 67 #include <soc/katana2.h> 68 #endif /* BCM_KATANA2_SUPPORT */ 69 #if defined(BCM_SABER2_SUPPORT) 70 #include <soc/saber2.h> 71 #endif /* BCM_SABER2_SUPPORT */ 72 #if defined(BCM_PETRA_SUPPORT) 73 #include <soc/dpp/drv.h> 74 #endif /* BCM_PETRA_SUPPORT */ 75 #if defined(BCM_DFE_SUPPORT) 76 #include <soc/dfe/cmn/dfe_drv.h> 77 #endif /* BCM_DFE_SUPPORT */ 78 #ifdef BCM_TOMAHAWK_SUPPORT 79 #include <soc/tomahawk.h> 80 #endif /* BCM_TOMAHAWK_SUPPORT */ 81 #ifdef BCM_TOMAHAWK3_SUPPORT 82 #include <soc/tomahawk3.h> 83 #endif /* BCM_TOMAHAWK3_SUPPORT */ 84 #if defined(BCM_TRIDENT3_SUPPORT) 85 #include <soc/trident3.h> 86 #endif /* BCM_TRIDENT3_SUPPORT */ 87 #ifdef BCM_TOMAHAWK2_SUPPORT 88 #include <soc/tomahawk2.h> 89 #endif /* BCM_TOMAHAWK2_SUPPORT */ 90 #if defined(BCM_MAVERICK2_SUPPORT) 91 #include <soc/maverick2.h> 92 #endif /* BCM_MAVERICK2_SUPPORT */ 93 #if defined(BCM_HELIX5_SUPPORT) 94 #include <soc/helix5.h> 95 #endif /* BCM_HELIX5_SUPPORT */ 96 #ifdef BCM_DNX_SUPPORT 97 #include <bcm/types.h> 98 #include <bcm_int/dnx/algo/port/algo_port_mgmt.h> 99 #include <bcm_int/dnx/algo/port/algo_port_utils.h> 100 #endif 101 102 103 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 104 /* 105 * Table memory test 106 */ 107 108 #define PAT_PLAIN 0 /* Keep writing same word */ 109 #define PAT_XOR 1 /* XOR 0xffffffff between entries */ 110 #define PAT_RANDOM 2 /* Add 0xdeadbeef between words */ 111 #define PAT_INCR 3 /* Add 1 between words */ 112 113 STATIC void 114 fillpat(uint32 *seed, uint32 *mask, uint32 *buf, int pat, int dw) 115 { 116 int i; 117 118 switch (pat) { 119 case PAT_PLAIN: 120 default: 121 for (i = 0; i < dw; i++) { 122 buf[i] = (*seed) & mask[i]; 123 } 124 break; 125 case PAT_XOR: 126 for (i = 0; i < dw; i++) { 127 buf[i] = (*seed) & mask[i]; 128 } 129 (*seed) ^= 0xffffffff; 130 break; 131 case PAT_RANDOM: 132 for (i = 0; i < dw; i++) { 133 buf[i] = (*seed) & mask[i]; 134 (*seed) += 0xdeadbeef; 135 } 136 break; 137 case PAT_INCR: 138 for (i = 0; i < dw; i++) { 139 buf[i] = (*seed) & mask[i]; 140 } 141 (*seed) += 1; 142 break; 143 } 144 } 145 146 /* 147 * Function: soc_mem_datamask_memtest 148 * Purpose: Patch a bit mask for a memory entry under test 149 * Returns: SOC_E_xxx 150 */ 151 void 152 soc_mem_datamask_memtest(int unit, soc_mem_t mem, uint32 *buf) 153 { 154 #ifdef BCM_SCORPION_SUPPORT 155 if (SOC_IS_SC_CQ(unit)) { 156 switch (mem) { 157 case FP_TCAM_Xm: 158 soc_mem_field32_set(unit, FP_TCAM_Xm, buf, IPBMf, 0x1fff); 159 soc_mem_field32_set(unit, FP_TCAM_Xm, buf, IPBM_MASKf, 0x1fff); 160 break; 161 case FP_TCAM_Ym: 162 soc_mem_field32_set(unit, FP_TCAM_Ym, buf, IPBMf, 0x1fffe000); 163 soc_mem_field32_set(unit, FP_TCAM_Ym, buf, IPBM_MASKf, 0x1fffe000); 164 break; 165 default: 166 break; 167 } 168 } 169 #endif 170 #ifdef BCM_TOMAHAWK3_SUPPORT 171 if (SOC_IS_TOMAHAWK3(unit)) { 172 switch(mem) { 173 case CDMIB_MEMm: 174 buf[0] = 0xffffffff; 175 buf[1] = 0x000000ff; 176 buf[2] = 0xffffffff; 177 buf[3] = 0x000000ff; 178 buf[4] = 0xffffffff; 179 buf[5] = 0x000000ff; 180 buf[6] = 0xffffffff; 181 buf[7] = 0x000000ff; 182 buf[8] = 0xffffffff; 183 buf[9] = 0x000000ff; 184 buf[10] = 0xffffffff; 185 buf[11] = 0x000000ff; 186 buf[12] = 0xffffffff; 187 buf[13] = 0x000000ff; 188 buf[14] = 0xffffffff; 189 buf[15] = 0x000000ff; 190 default: 191 break; 192 } 193 } 194 #endif 195 } 196 197 /* 198 * memtest_fill 199 * 200 * parm: Test parameters 201 * mem: soc_mem_t of memory to test 202 * copyno: which copy of memory to test 203 * seed: test pattern start value 204 * pat: test pattern function 205 * 206 * Returns 0 on success, -1 on error. 207 */ 208 209 #define FOREACH_FRAG \ 210 for (frag = frag_start; \ 211 frag_start <= frag_end ? frag <= frag_end : frag >= frag_end; \ 212 frag += frag_start <= frag_end ? 1 : -1) 213 214 #define FOREACH_INDEX \ 215 for (index = index_start; \ 216 index_start <= index_end ? index <= index_end : index >= index_end; \ 217 index += index_step) 218 219 STATIC int 220 memtest_fill(int unit, soc_mem_test_t *parm, unsigned array_index, int copyno, 221 uint32 *seed, int pat) 222 { 223 uint32 buf[SOC_MAX_MEM_WORDS]; 224 uint32 mask[SOC_MAX_MEM_WORDS]; 225 uint32 tcammask[SOC_MAX_MEM_WORDS]; 226 uint32 eccmask[SOC_MAX_MEM_WORDS]; 227 uint32 forcemask[SOC_MAX_MEM_WORDS]; 228 uint32 forcedata[SOC_MAX_MEM_WORDS]; 229 uint32 accum_tcammask, accum_forcemask; 230 soc_mem_t mem = parm->mem; 231 int index, dw, rv, i; 232 int index_start = parm->index_start; 233 int index_end = parm->index_end; 234 int index_step; 235 int frag; 236 int frag_start; 237 int frag_end; 238 239 index_step = parm->index_step; 240 241 242 243 dw = soc_mem_entry_words(unit, mem); 244 soc_mem_datamask_get(unit, mem, mask); 245 soc_mem_tcammask_get(unit, mem, tcammask); 246 soc_mem_eccmask_get(unit, mem, eccmask); 247 soc_mem_forcedata_get(unit, mem, forcemask, forcedata); 248 accum_tcammask = 0; 249 for (i = 0; i < dw; i++) { 250 accum_tcammask |= tcammask[i]; 251 } 252 accum_forcemask = 0; 253 for (i = 0; i < dw; i++) { 254 accum_forcemask |= forcemask[i]; 255 } 256 if (!parm->ecc_as_data) { 257 for (i = 0; i < dw; i++) { 258 mask[i] &= ~eccmask[i]; 259 } 260 } 261 soc_mem_datamask_memtest(unit, mem, mask); 262 263 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 264 if (parm->array_index_start != 0 || parm->array_index_end != parm->array_index_start) { 265 LOG_VERBOSE(BSL_LS_SOC_COMMON, 266 (BSL_META_U(unit, 267 " FILL %s[%u-%u].%s[%d-%d]\n"), 268 SOC_MEM_UFNAME(unit, mem), 269 parm->array_index_start, parm->array_index_end, 270 SOC_BLOCK_NAME(unit, copyno), 271 index_start, index_end)); 272 } else 273 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 274 { 275 { 276 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 277 LOG_VERBOSE(BSL_LS_SOC_COMMON, 278 (BSL_META_U(unit, 279 " FILL %s.%s[%d-%d]\n"), 280 SOC_MEM_UFNAME(unit, mem), 281 SOC_BLOCK_NAME(unit, copyno), 282 index_start, index_end)); 283 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 284 } 285 } 286 287 if (bsl_check(bslLayerSoc, bslSourceSocmem, bslSeverityNormal, unit)) { 288 LOG_CLI((BSL_META_U(unit, 289 " MASK"))); 290 for (i = 0; i < dw; i++) { 291 LOG_CLI((BSL_META_U(unit, 292 " 0x%08x"), mask[i])); 293 } 294 LOG_CLI((BSL_META_U(unit, 295 "\n"))); 296 if (accum_tcammask) { 297 LOG_CLI((BSL_META_U(unit, 298 " TCAM MASK"))); 299 for (i = 0; i < dw; i++) { 300 LOG_CLI((BSL_META_U(unit, 301 " 0x%08x"), tcammask[i])); 302 } 303 LOG_CLI((BSL_META_U(unit, 304 "\n"))); 305 } 306 } 307 308 if (parm->index_start < parm->index_end) { 309 frag_start = 0; 310 frag_end = parm->frag_count > 0 ? 311 (parm->frag_count - 1) : parm->frag_count; 312 } else if (parm->index_start > parm->index_end) { 313 frag_start = parm->frag_count > 0 ? 314 (parm->frag_count - 1) : parm->frag_count; 315 frag_end = 0; 316 } else { 317 frag_start = frag_end = 0; 318 } 319 FOREACH_FRAG { 320 index_start = parm->frag_index_start[frag]; 321 index_end = parm->frag_index_end[frag]; 322 323 FOREACH_INDEX { 324 if (soc_mem_test_skip(unit, parm->mem, index)) { 325 continue; 326 } 327 fillpat(seed, mask, buf, pat, dw); 328 if (accum_tcammask) { 329 /* data read back has dependency on mask */ 330 if ((SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ESM) || 331 (SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ETU)) { 332 for (i = 0; i < dw; i++) { 333 buf[i] &= ~tcammask[i]; 334 } 335 } else if (soc_feature(unit, soc_feature_xy_tcam)) { 336 for (i = 0; i < dw; i++) { 337 buf[i] |= tcammask[i]; 338 } 339 } 340 } 341 if (accum_forcemask) { 342 for (i = 0; i < dw; i++) { 343 buf[i] &= ~forcemask[i]; 344 buf[i] |= forcedata[i]; 345 } 346 } 347 if ((rv = (*parm->write_cb)(parm, array_index, copyno, index, buf)) < 0) { 348 return rv; 349 } 350 } /* FOREACH_INDEX */ 351 } /* FOREACH_FRAG */ 352 353 return SOC_E_NONE; 354 } 355 356 /* 357 * memtest_verify 358 * 359 * parm: Test parameters 360 * mem: soc_mem_t of memory to test 361 * copyno: which copy of memory to test 362 * seed: test pattern start value 363 * incr: test pattern increment value 364 * 365 * Returns 0 on success, -1 on error. 366 */ 367 368 STATIC int 369 memtest_verify(int unit, soc_mem_test_t *parm, unsigned array_index, int copyno, 370 uint32 *seed, int pat) 371 { 372 uint32 buf[SOC_MAX_MEM_WORDS]; 373 uint32 mask[SOC_MAX_MEM_WORDS]; 374 uint32 tcammask[SOC_MAX_MEM_WORDS]; 375 uint32 eccmask[SOC_MAX_MEM_WORDS]; 376 uint32 forcemask[SOC_MAX_MEM_WORDS]; 377 uint32 forcedata[SOC_MAX_MEM_WORDS]; 378 uint32 accum_tcammask, accum_forcemask; 379 uint32 cmp[SOC_MAX_MEM_WORDS]; 380 soc_mem_t mem = parm->mem; 381 int index, dw, rv, i; 382 int index_start = parm->index_start; 383 int index_end = parm->index_end; 384 int index_step; 385 int frag; 386 int frag_start; 387 int frag_end; 388 int read_cnt; 389 390 index_step = parm->index_step; 391 for (i=0;i<SOC_MAX_MEM_WORDS;i++) { 392 mask[i] = 0; 393 tcammask[i] = 0; 394 eccmask[i] = 0; 395 } 396 dw = soc_mem_entry_words(unit, mem); 397 #if defined(BCM_SAND_SUPPORT) || defined(BCM_GREYHOUND2_SUPPORT) 398 if(SOC_IS_SAND(unit) || SOC_IS_GREYHOUND2(unit)) { 399 soc_mem_datamask_rw_get(unit, mem, mask); 400 } else 401 #endif 402 { 403 soc_mem_datamask_get(unit, mem, mask); 404 } 405 soc_mem_tcammask_get(unit, mem, tcammask); 406 soc_mem_eccmask_get(unit, mem, eccmask); 407 soc_mem_forcedata_get(unit, mem, forcemask, forcedata); 408 accum_tcammask = 0; 409 for (i = 0; i < dw; i++) { 410 accum_tcammask |= tcammask[i]; 411 } 412 accum_forcemask = 0; 413 for (i = 0; i < dw; i++) { 414 accum_forcemask |= forcemask[i]; 415 } 416 if (!parm->ecc_as_data) { 417 for (i = 0; i < dw; i++) { 418 mask[i] &= ~eccmask[i]; 419 } 420 } 421 soc_mem_datamask_memtest(unit, mem, mask); 422 423 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 424 if (parm->array_index_start != 0 || parm->array_index_end != parm->array_index_start) { 425 LOG_VERBOSE(BSL_LS_SOC_COMMON, 426 (BSL_META_U(unit, 427 " VERIFY %s[%u-%u].%s[%d-%d] Reading %d times\n"), 428 SOC_MEM_UFNAME(unit, mem), 429 parm->array_index_start, parm->array_index_end, 430 SOC_BLOCK_NAME(unit, copyno), 431 index_start, index_end, 432 parm->read_count)); 433 } else 434 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 435 { 436 { 437 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 438 LOG_VERBOSE(BSL_LS_SOC_COMMON, 439 (BSL_META_U(unit, 440 " VERIFY %s.%s[%d-%d] Reading %d times\n"), 441 SOC_MEM_UFNAME(unit, mem), 442 SOC_BLOCK_NAME(unit, copyno), 443 index_start, index_end, 444 parm->read_count)); 445 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 446 } 447 } 448 449 if (parm->index_start < parm->index_end) { 450 frag_start = 0; 451 frag_end = parm->frag_count > 0 ? 452 (parm->frag_count - 1) : parm->frag_count; 453 } else if (parm->index_start > parm->index_end) { 454 frag_start = parm->frag_count > 0 ? 455 (parm->frag_count - 1) : parm->frag_count; 456 frag_end = 0; 457 } else { 458 frag_start = frag_end = 0; 459 } 460 FOREACH_FRAG { 461 index_start = parm->frag_index_start[frag]; 462 index_end = parm->frag_index_end[frag]; 463 464 FOREACH_INDEX { 465 if (soc_mem_test_skip(unit, parm->mem, index)) { 466 continue; 467 } 468 fillpat(seed, mask, cmp, pat, dw); 469 if (accum_tcammask) { 470 /* data read back has dependency on mask */ 471 if ((SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ESM) || 472 (SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ETU)) { 473 for (i = 0; i < dw; i++) { 474 cmp[i] &= ~tcammask[i]; 475 } 476 } else if (soc_feature(unit, soc_feature_xy_tcam)) { 477 for (i = 0; i < dw; i++) { 478 cmp[i] |= tcammask[i]; 479 } 480 } 481 } 482 if (accum_forcemask) { 483 for (i = 0; i < dw; i++) { 484 cmp[i] &= ~forcemask[i]; 485 cmp[i] |= forcedata[i]; 486 } 487 } 488 489 for (read_cnt = 0; read_cnt < parm->read_count; read_cnt++) { 490 if ((rv = (*parm->read_cb)(parm, array_index, copyno, index, buf)) < 0) { 491 return rv; 492 } 493 494 for (i = 0; i < dw; i++) { 495 if ((buf[i] ^ cmp[i]) & mask[i]) { 496 break; 497 } 498 } 499 500 if (i < dw) { 501 parm->err_count++; 502 if ((*parm->miscompare_cb)(parm, array_index, copyno, index, buf, 503 cmp, mask) == MT_MISCOMPARE_STOP) { 504 parm->error_count++; 505 if (!parm->continue_on_error && 506 (parm->error_count >= parm->error_max)) { 507 return SOC_E_FAIL; 508 } 509 } 510 } 511 } 512 } /* FOREACH_INDEX */ 513 } /* FOREACH_FRAG */ 514 515 return SOC_E_NONE; 516 } 517 518 /* 519 * memtest_test_by_entry_pattern 520 * 521 * Test memories one entry at a time. 522 */ 523 STATIC int 524 memtest_test_by_entry_pattern(int unit, soc_mem_test_t *parm, uint32 seed0, 525 int pat, char *desc) 526 { 527 int copyno; 528 unsigned array_index; 529 uint32 buf[SOC_MAX_MEM_WORDS]; 530 uint32 mask[SOC_MAX_MEM_WORDS]; 531 uint32 tcammask[SOC_MAX_MEM_WORDS]; 532 uint32 eccmask[SOC_MAX_MEM_WORDS]; 533 uint32 forcemask[SOC_MAX_MEM_WORDS]; 534 uint32 forcedata[SOC_MAX_MEM_WORDS]; 535 uint32 cmp[SOC_MAX_MEM_WORDS]; 536 uint32 accum_tcammask, accum_forcemask; 537 soc_mem_t mem = parm->mem; 538 int index, dw, i; 539 int index_start = parm->index_start; 540 int index_end = parm->index_end; 541 int index_step = parm->index_step; 542 int read_cnt; 543 544 dw = soc_mem_entry_words(unit, mem); 545 soc_mem_datamask_get(unit, mem, mask); 546 soc_mem_tcammask_get(unit, mem, tcammask); 547 soc_mem_eccmask_get(unit, mem, eccmask); 548 soc_mem_forcedata_get(unit, mem, forcemask, forcedata); 549 accum_tcammask = 0; 550 for (i = 0; i < dw; i++) { 551 accum_tcammask |= tcammask[i]; 552 } 553 accum_forcemask = 0; 554 for (i = 0; i < dw; i++) { 555 accum_forcemask |= forcemask[i]; 556 } 557 if (!parm->ecc_as_data) { 558 for (i = 0; i < dw; i++) { 559 mask[i] &= ~eccmask[i]; 560 } 561 } 562 soc_mem_datamask_memtest(unit, mem, mask); 563 564 for (array_index = parm->array_index_start; array_index <= parm->array_index_end; ++array_index) { 565 SOC_MEM_BLOCK_ITER(unit, mem, copyno) { 566 if (parm->copyno != COPYNO_ALL && parm->copyno != copyno) { 567 continue; 568 } 569 FOREACH_INDEX { 570 if (soc_mem_test_skip(unit, parm->mem, index)) { 571 continue; 572 } 573 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 574 if (parm->array_index_start != 0 || parm->array_index_end != parm->array_index_start) { 575 LOG_VERBOSE(BSL_LS_SOC_COMMON, 576 (BSL_META_U(unit, 577 " WRITE/READ %s[%u-%u].%s[%d]\n"), 578 SOC_MEM_UFNAME(unit, mem), 579 parm->array_index_start, parm->array_index_end, 580 SOC_BLOCK_NAME(unit, copyno), 581 index)); 582 } else 583 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 584 { 585 { 586 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 587 LOG_VERBOSE(BSL_LS_SOC_COMMON, 588 (BSL_META_U(unit, 589 " WRITE/READ %s.%s[%d]\n"), 590 SOC_MEM_UFNAME(unit, mem), 591 SOC_BLOCK_NAME(unit, copyno), 592 index)); 593 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 594 } 595 } 596 if (bsl_check(bslLayerSoc, bslSourceSocmem, bslSeverityNormal, unit)) { 597 LOG_CLI((BSL_META_U(unit, 598 " MASK"))); 599 for (i = 0; i < dw; i++) { 600 LOG_CLI((BSL_META_U(unit, 601 " 0x%08x"), mask[i])); 602 } 603 LOG_CLI((BSL_META_U(unit, 604 "\n"))); 605 if (accum_tcammask) { 606 LOG_CLI((BSL_META_U(unit, 607 " TCAM MASK"))); 608 for (i = 0; i < dw; i++) { 609 LOG_CLI((BSL_META_U(unit, 610 " 0x%08x"), tcammask[i])); 611 } 612 } 613 LOG_CLI((BSL_META_U(unit, 614 "\n"))); 615 } 616 /* First, write the data */ 617 fillpat(&seed0, mask, buf, pat, dw); 618 if (accum_tcammask) { 619 /* data read back has dependency on mask */ 620 if ((SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ESM) || 621 (SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ETU)) { 622 for (i = 0; i < dw; i++) { 623 buf[i] &= ~tcammask[i]; 624 } 625 } else if (soc_feature(unit, soc_feature_xy_tcam)) { 626 for (i = 0; i < dw; i++) { 627 buf[i] |= tcammask[i]; 628 } 629 } 630 } 631 if (accum_forcemask) { 632 for (i = 0; i < dw; i++) { 633 buf[i] &= ~forcemask[i]; 634 buf[i] |= forcedata[i]; 635 } 636 } 637 #ifdef BCM_TOMAHAWK3_SUPPORT 638 if (parm->mem == CDMIB_MEMm && index == 12) { 639 buf[14] = 0x00000000; 640 buf[15] = 0x00000000; 641 } 642 #endif 643 for (i = 0; i < dw; i++) { 644 cmp[i] = buf[i]; 645 } 646 if ((*parm->write_cb)(parm, array_index, copyno, index, buf) < 0) { 647 return -1; 648 } 649 /* Then, read the data */ 650 for (read_cnt = 0; read_cnt < parm->read_count; read_cnt++) { 651 if ((*parm->read_cb)(parm, array_index, copyno, index, buf) < 0) { 652 return -1; 653 } 654 for (i = 0; i < dw; i++) { 655 if ((buf[i] ^ cmp[i]) & mask[i]) { 656 break; 657 } 658 } 659 if (i < dw) { 660 parm->err_count++; 661 if ((*parm->miscompare_cb)(parm, array_index, copyno, index, buf, 662 cmp, mask) == MT_MISCOMPARE_STOP) { 663 parm->error_count++; 664 if (!parm->continue_on_error && 665 (parm->error_count >= parm->error_max)) { 666 return SOC_E_FAIL; 667 } 668 } 669 } 670 } 671 } 672 } 673 } 674 675 return SOC_E_NONE; 676 } 677 678 679 /* 680 * memtest_pattern 681 * 682 * Calls memtest_fill and memtest_verify on copies of the table. 683 */ 684 STATIC int 685 memtest_pattern(int unit, soc_mem_test_t *parm, uint32 seed0, 686 int pat, char *desc) 687 { 688 int copyno; 689 uint32 seed; 690 uint32 seed_save = 0; 691 int verify, rv, i; 692 uint32 array_index; 693 static char msg[80]; 694 695 #ifdef BCM_TOMAHAWK3_SUPPORT 696 int acc_type = SOC_MEM_ACC_TYPE(unit, parm->mem); 697 uint16 dev_id; 698 uint8 rev_id; 699 700 if (SOC_IS_TOMAHAWK3(unit)) { 701 soc_cm_get_id(unit, &dev_id, &rev_id); 702 /* For 56983 Skip the invalid pipes from memory tests */ 703 if(dev_id == BCM56983_DEVICE_ID && 704 (acc_type == 2 || acc_type == 3 || acc_type == 4 || acc_type == 5)) { 705 return SOC_E_NONE; 706 } 707 /* Since CDMIB_MEM is per CDPORT block and during the iteration of 708 blocks , it would iterate from all 64 blocks and in each iteration 709 it alternately write fives and as. We would verfiy only at the 710 end of the iteration and there would be a mismatch as generally 711 we verify after every write. 712 */ 713 if (parm->mem == CDMIB_MEMm) { 714 parm->test_by_entry = 1; 715 } 716 } 717 #endif 718 if (parm->test_by_entry) { 719 return memtest_test_by_entry_pattern(unit, parm, seed0, pat, desc); 720 } 721 722 /* Two passes: fill, then verify */ 723 724 for (verify = 0; verify < 2; verify++) { 725 seed = seed0; 726 727 for (array_index = parm->array_index_start; array_index <= parm->array_index_end; ++array_index) { 728 729 SOC_MEM_BLOCK_ITER(unit, parm->mem, copyno) { 730 #ifdef BCM_DNX_SUPPORT 731 if (SOC_IS_DNX(unit) && (SOC_BLOCK_TYPE(unit, SOC_MEM_BLOCK_MIN(unit, parm->mem)) == SOC_BLK_CDMAC || SOC_BLOCK_TYPE(unit, SOC_MEM_BLOCK_MIN(unit, parm->mem)) == SOC_BLK_CDPORT)) 732 { 733 bcm_pbmp_t valid_ports; 734 bcm_port_t valid_port; 735 int phy_port = 0; 736 int cd_block = 0; 737 if (dnx_algo_port_logicals_get(unit, BCM_CORE_ALL, DNX_ALGO_PORT_LOGICALS_TYPE_NIF, 0, &valid_ports) < 0) /* Get NIF logical port bitmap */ 738 { 739 break; 740 } 741 BCM_PBMP_ITER(valid_ports, valid_port) 742 { 743 phy_port = SOC_INFO(unit).port_l2p_mapping[valid_port]; /* Get NIF port first phy */ 744 cd_block = SOC_PORT_BLOCK(unit, phy_port); 745 if (copyno == cd_block) 746 { 747 parm->copyno = copyno; 748 break; 749 } 750 } 751 if (copyno != cd_block) 752 { 753 continue; 754 } 755 } 756 #endif 757 if (parm->copyno != COPYNO_ALL && parm->copyno != copyno) { 758 continue; 759 } 760 if (verify) { 761 seed_save = seed; 762 for (i = 0; i < parm->reverify_count + 1; i++) { 763 if (parm->reverify_delay > 0) { 764 sal_sleep(parm->reverify_delay); 765 } 766 if (parm->status_cb) { 767 sal_sprintf(msg, "Verifying %s", desc); 768 (*parm->status_cb)(parm, msg); 769 } 770 771 seed = seed_save; 772 if (memtest_verify(unit, parm, array_index, copyno, &seed, pat) != 0) { 773 if (!parm->continue_on_error && 774 (parm->error_count >= parm->error_max)) { 775 return SOC_E_FAIL; 776 } 777 } 778 } 779 } else { 780 if (parm->status_cb) { 781 sal_sprintf(msg, "Filling %s", desc); 782 (*parm->status_cb)(parm, msg); 783 } 784 785 if ((rv = memtest_fill(unit, parm, array_index, copyno, 786 &seed, pat)) < 0) { 787 return rv; 788 } 789 } 790 } 791 } 792 } 793 794 return SOC_E_NONE; 795 } 796 797 int 798 soc_mem_test_skip(int unit, soc_mem_t mem, int index) 799 { 800 #ifdef BCM_ESW_SUPPORT 801 if (mem == FP_GLOBAL_MASK_TCAMm || mem == FP_TCAMm || 802 mem == EFP_TCAMm || mem == VFP_TCAMm 803 || (FP_GLOBAL_MASK_TCAM_Xm == mem) 804 || (FP_GLOBAL_MASK_TCAM_Ym == mem) 805 || (FP_GM_FIELDSm == mem)) { 806 807 #ifdef BCM_TRIDENT2PLUS_SUPPORT 808 if (soc_feature(unit, soc_feature_field_stage_quarter_slice) 809 && soc_feature(unit, soc_feature_field_quarter_slice_single_tcam) 810 && soc_feature(unit, soc_feature_field_ingress_two_slice_types)) { 811 if ((FP_TCAMm == mem) || (FP_GM_FIELDSm == mem) 812 || (FP_GLOBAL_MASK_TCAMm == mem) 813 || (FP_GLOBAL_MASK_TCAM_Xm == mem) 814 || (FP_GLOBAL_MASK_TCAM_Ym == mem)) { 815 if (index < (soc_mem_index_count(unit, mem) / 2)) { 816 /* Slices of 2K entries. */ 817 if (((index / 1024) % 2) || ((index / 512) % 2)) { 818 return (TRUE); 819 } 820 } else { 821 /* Slices of 1K entries. */ 822 if (((index / 512) % 2) || ((index / 256) % 2)) { 823 return (TRUE); 824 } 825 } 826 } 827 } 828 #endif /* !BCM_TRIDENT2PLUS_SUPPORT */ 829 830 #ifdef BCM_APACHE_SUPPORT 831 if (soc_feature(unit, soc_feature_field_stage_half_slice) 832 && soc_feature(unit, soc_feature_field_half_slice_single_tcam) 833 && soc_feature(unit, soc_feature_field_ingress_two_slice_types)) { 834 if ((FP_TCAMm == mem) || (FP_GM_FIELDSm == mem) 835 || (FP_GLOBAL_MASK_TCAMm == mem) 836 || (FP_GLOBAL_MASK_TCAM_Xm == mem) 837 || (FP_GLOBAL_MASK_TCAM_Ym == mem)) { 838 if (index < (soc_mem_index_count(unit, mem) / 2)) { 839 /* Slices of 1K entries. */ 840 if ((index / 512) % 2) { 841 return (TRUE); 842 } 843 } else { 844 /* Slices of 512 entries. */ 845 if ((index / 256) % 2) { 846 return (TRUE); 847 } 848 } 849 } 850 } 851 #endif /* !BCM_APACHE_SUPPORT */ 852 if (soc_feature(unit, soc_feature_field_ingress_two_slice_types) && 853 soc_feature(unit, soc_feature_field_stage_ingress_512_half_slice)){ 854 if (mem == FP_GLOBAL_MASK_TCAMm || mem == FP_TCAMm) { 855 if (index < (soc_mem_index_count(unit, mem) / 2)) { 856 if ((index / 256) % 2) { 857 return TRUE; 858 } 859 } 860 } 861 } 862 863 if (soc_feature(unit, soc_feature_field_ingress_two_slice_types) && 864 soc_feature(unit, soc_feature_field_slices8)) { 865 if (mem == FP_GLOBAL_MASK_TCAMm || mem == FP_TCAMm) { 866 if (index >= 867 (soc_mem_index_count(unit, mem) * 3 / 4)) { 868 return TRUE; 869 } 870 } 871 } 872 873 if (soc_feature(unit, soc_feature_field_stage_egress_256_half_slice)) { 874 if (mem == EFP_TCAMm) { 875 if ((index / 128) % 2) { 876 return TRUE; 877 } 878 } 879 } 880 881 if (soc_feature(unit, soc_feature_field_stage_egress_512_half_slice)) { 882 if (mem == EFP_TCAMm) { 883 if ((index / 256) % 2) { 884 return TRUE; 885 } 886 } 887 } 888 889 if (soc_feature(unit, soc_feature_field_stage_lookup_256_half_slice)) { 890 if (mem == VFP_TCAMm) { 891 if ((index / 64) % 2) { 892 return TRUE; 893 } 894 } 895 } 896 897 if (soc_feature(unit, soc_feature_field_stage_lookup_512_half_slice)) { 898 if (mem == VFP_TCAMm) { 899 if ((index /128) % 2) { 900 return TRUE; 901 } 902 } 903 } 904 if (soc_feature(unit, soc_feature_field_slice_size128)) { 905 if ((mem == FP_GLOBAL_MASK_TCAMm) || (mem == FP_TCAMm)) { 906 if ((index/64) % 2) { 907 return TRUE; 908 } 909 } 910 } 911 } 912 913 switch ( mem ) { 914 case L3_DEFIP_ALPM_HIT_ONLYm : 915 case L3_DEFIP_ALPM_IPV4m : 916 case L3_DEFIP_ALPM_IPV4_1m : 917 case L3_DEFIP_ALPM_IPV6_64m : 918 case L3_DEFIP_ALPM_IPV6_64_1m : 919 case L3_DEFIP_ALPM_IPV6_128m : 920 case L3_DEFIP_ALPM_RAWm : 921 case L3_DEFIP_ALPM_ECCm : 922 if (! (soc_mem_index_count(unit, L3_DEFIP_ALPM_RAWm) > 0)) { 923 /* ALPM wasn't enabled */ 924 return TRUE; 925 } 926 } 927 928 #ifdef BCM_TOMAHAWK_SUPPORT 929 if (SOC_IS_TOMAHAWK(unit) && 930 !soc_feature(unit, soc_feature_advanced_flex_counter)) { 931 if ((mem >= ING_FLEX_CTR_COUNTER_TABLE_0m && 932 mem <= ING_FLEX_CTR_COUNTER_TABLE_9_PIPE3m) || 933 (mem >= EGR_FLEX_CTR_COUNTER_TABLE_0m && 934 mem <= EGR_FLEX_CTR_COUNTER_TABLE_3_Ym)) { 935 return TRUE; 936 } 937 } 938 #endif /* BCM_TOMAHAWK_SUPPORT */ 939 #ifdef BCM_TOMAHAWK2_SUPPORT 940 if (soc_feature(unit, soc_feature_field_stage_half_slice)) { 941 if ((IFP_TCAMm == mem) || 942 (IFP_TCAM_PIPE0m == mem) ||(IFP_TCAM_PIPE1m == mem) || 943 (IFP_TCAM_PIPE2m == mem) || (IFP_TCAM_PIPE3m == mem)) { 944 if ((index / 256) % 2) { 945 return TRUE; 946 } 947 } 948 if ((IFP_TCAM_WIDEm == mem) || 949 (IFP_TCAM_WIDE_PIPE0m == mem) ||(IFP_TCAM_WIDE_PIPE1m == mem) || 950 (IFP_TCAM_WIDE_PIPE2m == mem) || (IFP_TCAM_WIDE_PIPE3m == mem)) { 951 if ((index / 128) % 2) { 952 return TRUE; 953 } 954 } 955 } 956 if (soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 957 if ((IFP_TCAMm == mem) || 958 (IFP_TCAM_PIPE0m == mem) ||(IFP_TCAM_PIPE1m == mem) || 959 (IFP_TCAM_PIPE2m == mem) || (IFP_TCAM_PIPE3m == mem)) { 960 if ((index / 128) % 4) { 961 return TRUE; 962 } 963 } 964 if ((IFP_TCAM_WIDEm == mem) || 965 (IFP_TCAM_WIDE_PIPE0m == mem) ||(IFP_TCAM_WIDE_PIPE1m == mem) || 966 (IFP_TCAM_WIDE_PIPE2m == mem) || (IFP_TCAM_WIDE_PIPE3m == mem)) { 967 if ((index / 64) % 4) { 968 return TRUE; 969 } 970 } 971 } 972 #endif /* BCM_TOMAHAWK2_SUPPORT*/ 973 #ifdef BCM_TOMAHAWK3_SUPPORT 974 if (SOC_IS_TOMAHAWK3(unit)) { 975 if (CDMIB_MEMm == mem) { 976 if (index > 12) { 977 return TRUE; 978 } 979 } 980 } 981 #endif 982 #endif /* BCM_ESW_SUPPORT */ 983 984 return FALSE; 985 } 986 987 988 /* 989 * Memory test main entry point 990 */ 991 992 int 993 soc_mem_test(soc_mem_test_t *parm) 994 { 995 int rv = SOC_E_NONE; 996 int unit = parm->unit; 997 998 parm->err_count = 0; 999 1000 if (parm->patterns & MT_PAT_ZEROES) { 1001 /* Detect bits stuck at 1 */ 1002 if ((rv = memtest_pattern(unit, parm, 0x00000000, 1003 PAT_PLAIN, "0x00000000")) < 0) { 1004 goto done; 1005 } 1006 } 1007 1008 if (parm->patterns & MT_PAT_ONES) { 1009 /* Detect bits stuck at 0 */ 1010 if ((rv = memtest_pattern(unit, parm, 0xffffffff, 1011 PAT_PLAIN, "0xffffffff")) < 0) { 1012 goto done; 1013 } 1014 } 1015 1016 if (parm->patterns & MT_PAT_FIVES) { 1017 if ((rv = memtest_pattern(unit, parm, 0x55555555, 1018 PAT_PLAIN, "0x55555555")) < 0) { 1019 goto done; 1020 } 1021 } 1022 1023 if (parm->patterns & MT_PAT_AS) { 1024 if ((rv = memtest_pattern(unit, parm, 0xaaaaaaaa, 1025 PAT_PLAIN, "0xaaaaaaaa")) < 0) { 1026 goto done; 1027 } 1028 } 1029 1030 if (parm->patterns & MT_PAT_CHECKER) { 1031 /* 1032 * Checkerboard alternates 5's and a's to generate a pattern shown 1033 * below. This is useful to detecting horizontally or vertically 1034 * shorted data lines (in cases where the RAM layout is plain). 1035 * 1036 * 1 0 1 0 1 0 1 0 1 0 1 1037 * 0 1 0 1 0 1 0 1 0 1 0 1038 * 1 0 1 0 1 0 1 0 1 0 1 1039 * 0 1 0 1 0 1 0 1 0 1 0 1040 * 1 0 1 0 1 0 1 0 1 0 1 1041 */ 1042 if ((rv = memtest_pattern(unit, parm, 0x55555555, 1043 PAT_XOR, "checker-board")) < 0) { 1044 goto done; 1045 } 1046 } 1047 1048 if (parm->patterns & MT_PAT_ICHECKER) { 1049 /* Same as checker-board but inverted */ 1050 if ((rv = memtest_pattern(unit, parm, 0xaaaaaaaa, 1051 PAT_XOR, "inverted checker-board")) < 0) { 1052 goto done; 1053 } 1054 } 1055 1056 if (parm->patterns & MT_PAT_ADDR) { 1057 /* 1058 * Write a unique value in every location to make sure all 1059 * locations are distinct (detect shorted address bits). 1060 * The unique value used is the address so dumping the failed 1061 * memory may indicate where the bad data came from. 1062 */ 1063 if ((rv = memtest_pattern(unit, parm, 0, 1064 PAT_INCR, "linear increment")) < 0) { 1065 goto done; 1066 } 1067 } 1068 1069 if (parm->patterns & MT_PAT_RANDOM) { 1070 /* 1071 * Write a unique value in every location using pseudo-random data. 1072 */ 1073 if ((rv = memtest_pattern(unit, parm, 0xd246fe4b, 1074 PAT_RANDOM, "pseudo-random")) < 0) { 1075 goto done; 1076 } 1077 } 1078 1079 if (parm->patterns & MT_PAT_HEX) { 1080 /* 1081 * Write a value specified by the user. 1082 */ 1083 int i, val = 0; 1084 for (i = 0; i < 4; i ++) { 1085 val |= (parm->hex_byte & 0xff) << i*8; 1086 } 1087 if ((rv = memtest_pattern(unit, parm, val, 1088 PAT_PLAIN, "hex_byte")) < 0) { 1089 goto done; 1090 } 1091 } 1092 1093 if (parm->err_count > 0) { 1094 rv = SOC_E_FAIL; 1095 } 1096 1097 done: 1098 1099 return rv; 1100 } 1101 1102 #ifdef BCM_FIREBOLT_SUPPORT 1103 STATIC int 1104 _soc_fb_mem_parity_control(int unit, soc_mem_t mem, int copyno, int enable) 1105 { 1106 uint32 imask, oimask, misc_cfg, omisc_cfg; 1107 soc_field_t parity_f = PARITY_CHECK_ENf; 1108 1109 COMPILER_REFERENCE(copyno); 1110 1111 switch (mem) { 1112 case L2Xm: 1113 case L2_ENTRY_ONLYm: 1114 if (soc_feature(unit, soc_feature_l2x_parity)) { 1115 SOC_IF_ERROR_RETURN(READ_L2_ENTRY_PARITY_CONTROLr(unit, &imask)); 1116 soc_reg_field_set(unit, L2_ENTRY_PARITY_CONTROLr, &imask, 1117 PARITY_ENf, (enable ? 1 : 0)); 1118 soc_reg_field_set(unit, L2_ENTRY_PARITY_CONTROLr, &imask, 1119 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1120 SOC_IF_ERROR_RETURN(WRITE_L2_ENTRY_PARITY_CONTROLr(unit, imask)); 1121 } 1122 return SOC_E_NONE; 1123 1124 case L3_ENTRY_IPV4_MULTICASTm: 1125 case L3_ENTRY_IPV4_UNICASTm: 1126 case L3_ENTRY_IPV6_MULTICASTm: 1127 case L3_ENTRY_IPV6_UNICASTm: 1128 case L3_ENTRY_ONLYm: 1129 case L3_ENTRY_VALID_ONLYm: 1130 if (soc_feature(unit, soc_feature_l3x_parity)) { 1131 SOC_IF_ERROR_RETURN(READ_L3_ENTRY_PARITY_CONTROLr(unit, &imask)); 1132 soc_reg_field_set(unit, L3_ENTRY_PARITY_CONTROLr, &imask, 1133 PARITY_ENf, (enable ? 1 : 0)); 1134 soc_reg_field_set(unit, L3_ENTRY_PARITY_CONTROLr, &imask, 1135 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1136 SOC_IF_ERROR_RETURN(WRITE_L3_ENTRY_PARITY_CONTROLr(unit, imask)); 1137 } 1138 return SOC_E_NONE; 1139 1140 case L3_DEFIPm: 1141 case L3_DEFIP_DATA_ONLYm: 1142 if (soc_feature(unit, soc_feature_l3defip_parity)) { 1143 SOC_IF_ERROR_RETURN(READ_L3_DEFIP_PARITY_CONTROLr(unit, &imask)); 1144 soc_reg_field_set(unit, L3_DEFIP_PARITY_CONTROLr, &imask, 1145 PARITY_ENf, (enable ? 1 : 0)); 1146 soc_reg_field_set(unit, L3_DEFIP_PARITY_CONTROLr, &imask, 1147 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1148 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_PARITY_CONTROLr(unit, imask)); 1149 } 1150 return SOC_E_NONE; 1151 1152 #ifdef BCM_RAVEN_SUPPORT 1153 case DSCP_TABLEm: 1154 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1155 SOC_IF_ERROR_RETURN(READ_DSCP_TABLE_PARITY_CONTROLr(unit, &imask)); 1156 soc_reg_field_set(unit, DSCP_TABLE_PARITY_CONTROLr, &imask, 1157 PARITY_ENf, (enable ? 1 : 0)); 1158 soc_reg_field_set(unit, DSCP_TABLE_PARITY_CONTROLr, &imask, 1159 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1160 SOC_IF_ERROR_RETURN(WRITE_DSCP_TABLE_PARITY_CONTROLr(unit, imask)); 1161 } 1162 return SOC_E_NONE; 1163 1164 case EGR_L3_INTFm: 1165 if (!SOC_IS_HAWKEYE(unit)) { 1166 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1167 SOC_IF_ERROR_RETURN(READ_EGR_L3_INTF_PARITY_CONTROLr(unit, &imask)); 1168 soc_reg_field_set(unit, EGR_L3_INTF_PARITY_CONTROLr, &imask, 1169 PARITY_ENf, (enable ? 1 : 0)); 1170 soc_reg_field_set(unit, EGR_L3_INTF_PARITY_CONTROLr, &imask, 1171 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1172 SOC_IF_ERROR_RETURN(WRITE_EGR_L3_INTF_PARITY_CONTROLr(unit, imask)); 1173 } 1174 } 1175 return SOC_E_NONE; 1176 1177 case EGR_MASKm: 1178 if (!SOC_IS_HAWKEYE(unit)) { 1179 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1180 SOC_IF_ERROR_RETURN(READ_EGR_MASK_PARITY_CONTROLr(unit, &imask)); 1181 soc_reg_field_set(unit, EGR_MASK_PARITY_CONTROLr, &imask, 1182 PARITY_ENf, (enable ? 1 : 0)); 1183 soc_reg_field_set(unit, EGR_MASK_PARITY_CONTROLr, &imask, 1184 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1185 SOC_IF_ERROR_RETURN(WRITE_EGR_MASK_PARITY_CONTROLr(unit, imask)); 1186 } 1187 } 1188 return SOC_E_NONE; 1189 1190 case EGR_L3_NEXT_HOPm: 1191 if (!SOC_IS_HAWKEYE(unit)) { 1192 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1193 SOC_IF_ERROR_RETURN(READ_EGR_NEXT_HOP_PARITY_CONTROLr(unit, &imask)); 1194 soc_reg_field_set(unit, EGR_NEXT_HOP_PARITY_CONTROLr, &imask, 1195 PARITY_ENf, (enable ? 1 : 0)); 1196 soc_reg_field_set(unit, EGR_NEXT_HOP_PARITY_CONTROLr, &imask, 1197 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1198 SOC_IF_ERROR_RETURN(WRITE_EGR_NEXT_HOP_PARITY_CONTROLr(unit, imask)); 1199 } 1200 } 1201 return SOC_E_NONE; 1202 1203 case EGR_VLANm: 1204 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1205 SOC_IF_ERROR_RETURN(READ_EGR_VLAN_TABLE_PARITY_CONTROLr(unit, &imask)); 1206 soc_reg_field_set(unit, EGR_VLAN_TABLE_PARITY_CONTROLr, &imask, 1207 PARITY_ENf, (enable ? 1 : 0)); 1208 soc_reg_field_set(unit, EGR_VLAN_TABLE_PARITY_CONTROLr, &imask, 1209 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1210 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_TABLE_PARITY_CONTROLr(unit, imask)); 1211 } 1212 return SOC_E_NONE; 1213 1214 case FP_POLICY_TABLEm: 1215 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1216 SOC_IF_ERROR_RETURN(READ_FP_POLICY_PARITY_CONTROLr(unit, &imask)); 1217 soc_reg_field_set(unit, FP_POLICY_PARITY_CONTROLr, &imask, 1218 PARITY_ENf, (enable ? 1 : 0)); 1219 soc_reg_field_set(unit, FP_POLICY_PARITY_CONTROLr, &imask, 1220 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1221 SOC_IF_ERROR_RETURN(WRITE_FP_POLICY_PARITY_CONTROLr(unit, imask)); 1222 } 1223 return SOC_E_NONE; 1224 1225 case ING_L3_NEXT_HOPm: 1226 if (!SOC_IS_HAWKEYE(unit)) { 1227 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1228 SOC_IF_ERROR_RETURN(READ_ING_L3_NEXT_HOP_PARITY_CONTROLr(unit, &imask)); 1229 soc_reg_field_set(unit, ING_L3_NEXT_HOP_PARITY_CONTROLr, &imask, 1230 PARITY_ENf, (enable ? 1 : 0)); 1231 soc_reg_field_set(unit, ING_L3_NEXT_HOP_PARITY_CONTROLr, &imask, 1232 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1233 SOC_IF_ERROR_RETURN(WRITE_ING_L3_NEXT_HOP_PARITY_CONTROLr(unit, imask)); 1234 } 1235 } 1236 return SOC_E_NONE; 1237 1238 case L2MCm: 1239 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1240 SOC_IF_ERROR_RETURN(READ_L2MC_PARITY_CONTROLr(unit, &imask)); 1241 soc_reg_field_set(unit, L2MC_PARITY_CONTROLr, &imask, 1242 PARITY_ENf, (enable ? 1 : 0)); 1243 soc_reg_field_set(unit, L2MC_PARITY_CONTROLr, &imask, 1244 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1245 SOC_IF_ERROR_RETURN(WRITE_L2MC_PARITY_CONTROLr(unit, imask)); 1246 } 1247 return SOC_E_NONE; 1248 1249 case L3_IPMCm: 1250 if (!SOC_IS_HAWKEYE(unit)) { 1251 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1252 SOC_IF_ERROR_RETURN(READ_L3_IPMC_PARITY_CONTROLr(unit, &imask)); 1253 soc_reg_field_set(unit, L3_IPMC_PARITY_CONTROLr, &imask, 1254 PARITY_ENf, (enable ? 1 : 0)); 1255 soc_reg_field_set(unit, L3_IPMC_PARITY_CONTROLr, &imask, 1256 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1257 SOC_IF_ERROR_RETURN(WRITE_L3_IPMC_PARITY_CONTROLr(unit, imask)); 1258 } 1259 } 1260 return SOC_E_NONE; 1261 1262 case VLAN_TABm: 1263 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 1264 SOC_IF_ERROR_RETURN(READ_VLAN_PARITY_CONTROLr(unit, &imask)); 1265 soc_reg_field_set(unit, VLAN_PARITY_CONTROLr, &imask, 1266 PARITY_ENf, (enable ? 1 : 0)); 1267 soc_reg_field_set(unit, VLAN_PARITY_CONTROLr, &imask, 1268 PARITY_IRQ_ENf, (enable ? 1 : 0)); 1269 SOC_IF_ERROR_RETURN(WRITE_VLAN_PARITY_CONTROLr(unit, imask)); 1270 } 1271 return SOC_E_NONE; 1272 #endif /* BCM_RAVEN_SUPPORT */ 1273 1274 default: 1275 break; /* Look at MMU memories below */ 1276 } 1277 1278 SOC_IF_ERROR_RETURN(READ_MEMFAILINTMASKr(unit, &imask)); 1279 oimask = imask; 1280 /* MISCCONFIGr has PARITY_CHECK_EN & CELLCRCCHECKEN control */ 1281 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 1282 omisc_cfg = misc_cfg; 1283 1284 switch (mem) { 1285 /* Covered by parity */ 1286 case MMU_CFAPm: 1287 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 1288 CFAPPARITYERRORINTMASKf, (enable ? 1 : 0)); 1289 break; 1290 1291 case MMU_CCPm: 1292 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 1293 CCPPARITYERRORINTMASKf, (enable ? 1 : 0)); 1294 break; 1295 1296 case MMU_CBPPKTHEADER0m: 1297 case MMU_CBPPKTHEADER1m: 1298 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 1299 CBPPKTHDRPARITYERRORINTMASKf, (enable ? 1 : 0)); 1300 break; 1301 1302 case MMU_CBPCELLHEADERm: 1303 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 1304 CBPCELLHDRPARITYERRORINTMASKf, (enable ? 1 : 0)); 1305 break; 1306 1307 case MMU_XQ0m: 1308 case MMU_XQ1m: 1309 case MMU_XQ2m: 1310 case MMU_XQ3m: 1311 case MMU_XQ4m: 1312 case MMU_XQ5m: 1313 case MMU_XQ6m: 1314 case MMU_XQ7m: 1315 case MMU_XQ8m: 1316 case MMU_XQ9m: 1317 case MMU_XQ10m: 1318 case MMU_XQ11m: 1319 case MMU_XQ12m: 1320 case MMU_XQ13m: 1321 case MMU_XQ14m: 1322 case MMU_XQ15m: 1323 case MMU_XQ16m: 1324 case MMU_XQ17m: 1325 case MMU_XQ18m: 1326 case MMU_XQ19m: 1327 case MMU_XQ20m: 1328 case MMU_XQ21m: 1329 case MMU_XQ22m: 1330 case MMU_XQ23m: 1331 case MMU_XQ24m: 1332 case MMU_XQ25m: 1333 case MMU_XQ26m: 1334 case MMU_XQ27m: 1335 case MMU_XQ28m: 1336 #if defined(BCM_RAPTOR_SUPPORT) 1337 case MMU_XQ29m: 1338 case MMU_XQ30m: 1339 case MMU_XQ31m: 1340 #if defined(BCM_RAPTOR1_SUPPORT) 1341 case MMU_XQ32m: 1342 case MMU_XQ33m: 1343 case MMU_XQ34m: 1344 case MMU_XQ35m: 1345 case MMU_XQ36m: 1346 case MMU_XQ37m: 1347 case MMU_XQ38m: 1348 case MMU_XQ39m: 1349 case MMU_XQ40m: 1350 case MMU_XQ41m: 1351 case MMU_XQ42m: 1352 case MMU_XQ43m: 1353 case MMU_XQ44m: 1354 case MMU_XQ45m: 1355 case MMU_XQ46m: 1356 case MMU_XQ47m: 1357 case MMU_XQ48m: 1358 case MMU_XQ49m: 1359 case MMU_XQ50m: 1360 case MMU_XQ51m: 1361 case MMU_XQ52m: 1362 case MMU_XQ53m: 1363 #endif /* BCM_RAPTOR1_SUPPORT */ 1364 #endif /* BCM_RAPTOR_SUPPORT */ 1365 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 1366 XQPARITYERRORINTMASKf, (enable ? 1 : 0)); 1367 break; 1368 1369 /* Covered by CRC */ 1370 case MMU_CBPDATA0m: 1371 case MMU_CBPDATA1m: 1372 case MMU_CBPDATA2m: 1373 case MMU_CBPDATA3m: 1374 case MMU_CBPDATA4m: 1375 case MMU_CBPDATA5m: 1376 case MMU_CBPDATA6m: 1377 case MMU_CBPDATA7m: 1378 case MMU_CBPDATA8m: 1379 case MMU_CBPDATA9m: 1380 case MMU_CBPDATA10m: 1381 case MMU_CBPDATA11m: 1382 case MMU_CBPDATA12m: 1383 case MMU_CBPDATA13m: 1384 case MMU_CBPDATA14m: 1385 case MMU_CBPDATA15m: 1386 soc_reg_field_set(unit, MEMFAILINTMASKr, &imask, 1387 CRCERRORINTMASKf, (enable ? 1 : 0)); 1388 parity_f = CELLCRCCHECKENf; 1389 break; 1390 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_HAWKEYE_SUPPORT) 1391 case MMU_MIN_BUCKET_GPORTm: 1392 case MMU_MAX_BUCKET_GPORTm: 1393 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 1394 METERING_CLK_ENf, (enable ? 1 : 0)); 1395 break; 1396 #endif /* BCM_FIREBOLT2_SUPPORT */ 1397 default: 1398 return SOC_E_NONE; /* do nothing */ 1399 } 1400 if (oimask != imask) { 1401 SOC_IF_ERROR_RETURN(WRITE_MEMFAILINTMASKr(unit, imask)); 1402 } 1403 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 1404 parity_f, (enable ? 1 : 0)); 1405 if (omisc_cfg != misc_cfg) { 1406 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 1407 } 1408 return SOC_E_NONE; 1409 } 1410 #endif /* BCM_FIREBOLT_SUPPORT */ 1411 1412 #ifdef BCM_SHADOW_SUPPORT 1413 STATIC int 1414 _soc_shadow_mem_parity_control(int unit, soc_mem_t mem, int copyno, int enable) 1415 { 1416 1417 COMPILER_REFERENCE(copyno); 1418 1419 switch (mem) { 1420 case ING_VLAN_RANGEm: 1421 SOC_IF_ERROR_RETURN 1422 (soc_reg_field32_modify(unit, IPARS_DBGCTRLr, REG_PORT_ANY, 1423 VLR0_ENABLE_ECCf, (enable ? 1 : 0))); 1424 SOC_IF_ERROR_RETURN 1425 (soc_reg_field32_modify(unit, IPARS_DBGCTRLr, REG_PORT_ANY, 1426 VLR1_ENABLE_ECCf, (enable ? 1 : 0))); 1427 break; 1428 case SOURCE_TRUNK_MAP_TABLEm: 1429 SOC_IF_ERROR_RETURN 1430 (soc_reg_field32_modify(unit, IPARS_DBGCTRLr, REG_PORT_ANY, 1431 STM_ENABLE_ECCf, (enable ? 1 : 0))); 1432 break; 1433 case UDF_OFFSETm: 1434 SOC_IF_ERROR_RETURN 1435 (soc_reg_field32_modify(unit, IPARS_DBGCTRLr, REG_PORT_ANY, 1436 UDF_ENABLE_ECCf, (enable ? 1 : 0))); 1437 break; 1438 case VLAN_TABm: 1439 SOC_IF_ERROR_RETURN 1440 (soc_reg_field32_modify(unit, IVLAN_DBGCTRLr, REG_PORT_ANY, 1441 VLAN_ENABLE_ECCf, (enable ? 1 : 0))); 1442 break; 1443 case STG_TABm: 1444 SOC_IF_ERROR_RETURN 1445 (soc_reg_field32_modify(unit, IVLAN_DBGCTRLr, REG_PORT_ANY, 1446 VLAN_STG_ENABLE_ECCf, (enable ? 1 : 0))); 1447 break; 1448 case VLAN_SUBNETm: 1449 case VLAN_SUBNET_ONLYm: 1450 case VLAN_SUBNET_DATA_ONLYm: 1451 SOC_IF_ERROR_RETURN 1452 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_0r, 1453 REG_PORT_ANY, VLAN_SUBNET_ENABLE_ECCf, 1454 (enable ? 1 : 0))); 1455 SOC_IF_ERROR_RETURN 1456 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_0r, 1457 REG_PORT_ANY, VLAN_SUBNET_DATA_ENABLE_ECCf, 1458 (enable ? 1 : 0))); 1459 break; 1460 case VLAN_XLATEm: 1461 case VLAN_MACm: 1462 SOC_IF_ERROR_RETURN 1463 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1464 REG_PORT_ANY, VLAN_XLATE_MEM_0_ENABLE_ECCf, 1465 (enable ? 1 : 0))); 1466 SOC_IF_ERROR_RETURN 1467 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1468 REG_PORT_ANY, VLAN_XLATE_MEM_1_ENABLE_ECCf, 1469 (enable ? 1 : 0))); 1470 SOC_IF_ERROR_RETURN 1471 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1472 REG_PORT_ANY, VLAN_XLATE_MEM_2_ENABLE_ECCf, 1473 (enable ? 1 : 0))); 1474 SOC_IF_ERROR_RETURN 1475 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1476 REG_PORT_ANY, VLAN_XLATE_MEM_3_ENABLE_ECCf, 1477 (enable ? 1 : 0))); 1478 SOC_IF_ERROR_RETURN 1479 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1480 REG_PORT_ANY, VLAN_XLATE_MEM_4_ENABLE_ECCf, 1481 (enable ? 1 : 0))); 1482 SOC_IF_ERROR_RETURN 1483 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1484 REG_PORT_ANY, VLAN_XLATE_MEM_5_ENABLE_ECCf, 1485 (enable ? 1 : 0))); 1486 SOC_IF_ERROR_RETURN 1487 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1488 REG_PORT_ANY, VLAN_XLATE_MEM_6_ENABLE_ECCf, 1489 (enable ? 1 : 0))); 1490 SOC_IF_ERROR_RETURN 1491 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1492 REG_PORT_ANY, VLAN_XLATE_MEM_7_ENABLE_ECCf, 1493 (enable ? 1 : 0))); 1494 break; 1495 case VLAN_PROTOCOL_DATAm: 1496 SOC_IF_ERROR_RETURN 1497 (soc_reg_field32_modify(unit, VXLT_DEBUG_CONTROL_1r, 1498 REG_PORT_ANY, VLAN_PROTOCOL_ENABLE_ECCf, 1499 (enable ? 1 : 0))); 1500 break; 1501 case DSCP_TABLEm: 1502 SOC_IF_ERROR_RETURN 1503 (soc_reg_field32_modify(unit, ISW1_ECC_DEBUGr, REG_PORT_ANY, 1504 DSCP_TABLE_ENABLE_ECCf, (enable ? 1 : 0))); 1505 break; 1506 case UFLOW_Bm: 1507 SOC_IF_ERROR_RETURN 1508 (soc_reg_field32_modify(unit, ISW1_ECC_DEBUGr, REG_PORT_ANY, 1509 UFLOW_B_0_ENABLE_ECCf, (enable ? 1 : 0))); 1510 SOC_IF_ERROR_RETURN 1511 (soc_reg_field32_modify(unit, ISW1_ECC_DEBUGr, REG_PORT_ANY, 1512 UFLOW_B_1_ENABLE_ECCf, (enable ? 1 : 0))); 1513 break; 1514 case UFLOW_Am: 1515 SOC_IF_ERROR_RETURN 1516 (soc_reg_field32_modify(unit, ISW1_ECC_DEBUGr, REG_PORT_ANY, 1517 UFLOW_A_0_ENABLE_ECCf, (enable ? 1 : 0))); 1518 SOC_IF_ERROR_RETURN 1519 (soc_reg_field32_modify(unit, ISW1_ECC_DEBUGr, REG_PORT_ANY, 1520 UFLOW_A_1_ENABLE_ECCf, (enable ? 1 : 0))); 1521 break; 1522 case FP_TCAMm: 1523 SOC_IF_ERROR_RETURN 1524 (soc_reg_field32_modify(unit, FP_DEBUG_CONTROLr, REG_PORT_ANY, 1525 TCAM_ENABLE_ECCf, (enable ? 1 : 0))); 1526 break; 1527 case FP_METER_TABLEm: 1528 SOC_IF_ERROR_RETURN 1529 (soc_reg_field32_modify(unit, FP_DEBUG_CONTROLr, REG_PORT_ANY, 1530 REFRESH_ENABLEf, (enable ? 1 : 0))); 1531 SOC_IF_ERROR_RETURN 1532 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1533 METER_EVEN_SLICE_0_ENABLE_ECCf, 1534 (enable ? 1 : 0))); 1535 SOC_IF_ERROR_RETURN 1536 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1537 METER_EVEN_SLICE_1_ENABLE_ECCf, 1538 (enable ? 1 : 0))); 1539 SOC_IF_ERROR_RETURN 1540 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1541 METER_EVEN_SLICE_2_ENABLE_ECCf, 1542 (enable ? 1 : 0))); 1543 SOC_IF_ERROR_RETURN 1544 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1545 METER_EVEN_SLICE_3_ENABLE_ECCf, 1546 (enable ? 1 : 0))); 1547 SOC_IF_ERROR_RETURN 1548 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1549 METER_ODD_SLICE_0_ENABLE_ECCf, 1550 (enable ? 1 : 0))); 1551 SOC_IF_ERROR_RETURN 1552 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1553 METER_ODD_SLICE_1_ENABLE_ECCf, 1554 (enable ? 1 : 0))); 1555 SOC_IF_ERROR_RETURN 1556 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1557 METER_ODD_SLICE_2_ENABLE_ECCf, 1558 (enable ? 1 : 0))); 1559 SOC_IF_ERROR_RETURN 1560 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_1r, REG_PORT_ANY, 1561 METER_ODD_SLICE_3_ENABLE_ECCf, 1562 (enable ? 1 : 0))); 1563 break; 1564 case FP_COUNTER_TABLEm: 1565 SOC_IF_ERROR_RETURN 1566 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1567 COUNTER_SLICE_0_ENABLE_ECCf, 1568 (enable ? 1 : 0))); 1569 SOC_IF_ERROR_RETURN 1570 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1571 COUNTER_SLICE_1_ENABLE_ECCf, 1572 (enable ? 1 : 0))); 1573 SOC_IF_ERROR_RETURN 1574 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1575 COUNTER_SLICE_2_ENABLE_ECCf, 1576 (enable ? 1 : 0))); 1577 SOC_IF_ERROR_RETURN 1578 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1579 COUNTER_SLICE_3_ENABLE_ECCf, 1580 (enable ? 1 : 0))); 1581 break; 1582 case FP_STORM_CONTROL_METERSm: 1583 SOC_IF_ERROR_RETURN 1584 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1585 STORM_ENABLE_ECCf, (enable ? 1 : 0))); 1586 SOC_IF_ERROR_RETURN 1587 (soc_reg_field32_modify(unit, FP_DEBUG_CONTROLr, REG_PORT_ANY, 1588 REFRESH_ENABLEf, (enable ? 1 : 0))); 1589 break; 1590 case FP_POLICY_TABLEm: 1591 SOC_IF_ERROR_RETURN 1592 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1593 POLICY_SLICE_0_ENABLE_ECCf, 1594 (enable ? 1 : 0))); 1595 SOC_IF_ERROR_RETURN 1596 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1597 POLICY_SLICE_1_ENABLE_ECCf, 1598 (enable ? 1 : 0))); 1599 SOC_IF_ERROR_RETURN 1600 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1601 POLICY_SLICE_2_ENABLE_ECCf, 1602 (enable ? 1 : 0))); 1603 SOC_IF_ERROR_RETURN 1604 (soc_reg_field32_modify(unit, FP_RAM_CONTROL_64r, REG_PORT_ANY, 1605 POLICY_SLICE_3_ENABLE_ECCf, 1606 (enable ? 1 : 0))); 1607 break; 1608 case CELL_BUFFER3m: 1609 SOC_IF_ERROR_RETURN 1610 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1611 CELL_BUFFER3_ENABLE_ECCf, 1612 (enable ? 1 : 0))); 1613 break; 1614 case CELL_BUFFER2m: 1615 SOC_IF_ERROR_RETURN 1616 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1617 CELL_BUFFER2_ENABLE_ECCf, 1618 (enable ? 1 : 0))); 1619 break; 1620 case CELL_BUFFER1m: 1621 SOC_IF_ERROR_RETURN 1622 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1623 CELL_BUFFER1_ENABLE_ECCf, 1624 (enable ? 1 : 0))); 1625 break; 1626 case CELL_BUFFER0m: 1627 SOC_IF_ERROR_RETURN 1628 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1629 CELL_BUFFER0_ENABLE_ECCf, 1630 (enable ? 1 : 0))); 1631 break; 1632 case DEBUG_CAPTUREm: 1633 SOC_IF_ERROR_RETURN 1634 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1635 DEBUG_CAPTURE_ENABLE_ECCf, 1636 (enable ? 1 : 0))); 1637 break; 1638 case VLAN_PROFILE_2m: 1639 SOC_IF_ERROR_RETURN 1640 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1641 VLAN_PROFILE_2_ENABLE_ECCf, 1642 (enable ? 1 : 0))); 1643 break; 1644 case EGR_MASKm: 1645 SOC_IF_ERROR_RETURN 1646 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1647 EGR_MASK_ENABLE_ECCf, 1648 (enable ? 1 : 0))); 1649 break; 1650 case TRUNK_BITMAPm: 1651 SOC_IF_ERROR_RETURN 1652 (soc_reg_field32_modify(unit, ISW2_DEBUG0r, REG_PORT_ANY, 1653 TRUNK_BITMAP_ENABLE_ECCf, 1654 (enable ? 1 : 0))); 1655 break; 1656 case E2E_HOL_STATUSm: 1657 SOC_IF_ERROR_RETURN 1658 (soc_reg_field32_modify(unit, ISW2_DEBUG1r, REG_PORT_ANY, 1659 E2E_HOL_STATUS3_ENABLE_ECCf, 1660 (enable ? 1 : 0))); 1661 SOC_IF_ERROR_RETURN 1662 (soc_reg_field32_modify(unit, ISW2_DEBUG1r, REG_PORT_ANY, 1663 E2E_HOL_STATUS2_ENABLE_ECCf, 1664 (enable ? 1 : 0))); 1665 SOC_IF_ERROR_RETURN 1666 (soc_reg_field32_modify(unit, ISW2_DEBUG1r, REG_PORT_ANY, 1667 E2E_HOL_STATUS1_ENABLE_ECCf, 1668 (enable ? 1 : 0))); 1669 SOC_IF_ERROR_RETURN 1670 (soc_reg_field32_modify(unit, ISW2_DEBUG1r, REG_PORT_ANY, 1671 E2E_HOL_STATUS0_ENABLE_ECCf, 1672 (enable ? 1 : 0))); 1673 break; 1674 case EGR_VLANm: 1675 SOC_IF_ERROR_RETURN 1676 (soc_reg_field32_modify(unit, EGR_EVLAN_ECC_DEBUGr, REG_PORT_ANY, 1677 EP_VLAN_ENABLE_ECCf, (enable ? 1 : 0))); 1678 break; 1679 case EGR_VLAN_STGm: 1680 SOC_IF_ERROR_RETURN 1681 (soc_reg_field32_modify(unit, EGR_EVLAN_ECC_DEBUGr, 1682 REG_PORT_ANY, EP_VLAN_STG_ENABLE_ECCf, 1683 (enable ? 1 : 0))); 1684 break; 1685 case EGR_VLAN_XLATEm: 1686 SOC_IF_ERROR_RETURN 1687 (soc_reg_field32_modify(unit, EGR_EVXLT_ECC_DEBUGr, REG_PORT_ANY, 1688 EP_VLAN_XLATE_U_ENABLE_ECCf, 1689 (enable ? 1 : 0))); 1690 SOC_IF_ERROR_RETURN 1691 (soc_reg_field32_modify(unit, EGR_EVXLT_ECC_DEBUGr, REG_PORT_ANY, 1692 EP_VLAN_XLATE_L_ENABLE_ECCf, 1693 (enable ? 1 : 0))); 1694 break; 1695 case EGR_PRI_CNG_MAPm: 1696 SOC_IF_ERROR_RETURN 1697 (soc_reg_field32_modify(unit, EGR_EVXLT_ECC_DEBUGr, REG_PORT_ANY, 1698 EP_PRI_CNG_MAP_ENABLE_ECCf, 1699 (enable ? 1 : 0))); 1700 break; 1701 case EGR_DSCP_TABLEm: 1702 SOC_IF_ERROR_RETURN 1703 (soc_reg_field32_modify(unit, EGR_EVXLT_ECC_DEBUGr, REG_PORT_ANY, 1704 EP_DSCP_ENABLE_ECCf, (enable ? 1 : 0))); 1705 break; 1706 case EGR_SCI_TABLEm: 1707 SOC_IF_ERROR_RETURN 1708 (soc_reg_field32_modify(unit, EGR_EHCPM_ECC_DEBUGr, REG_PORT_ANY, 1709 EP_SCI_TABLE_ENABLE_ECCf, 1710 (enable ? 1 : 0))); 1711 break; 1712 case EGR_PERQ_XMT_COUNTERSm: 1713 SOC_IF_ERROR_RETURN 1714 (soc_reg_field32_modify(unit, EGR_EDB_ECC_DEBUGr, REG_PORT_ANY, 1715 EP_PERQ_XMT_COUNTER_ENABLE_ECCf, 1716 (enable ? 1 : 0))); 1717 break; 1718 case MMU_CFAP_MEMm: 1719 SOC_IF_ERROR_RETURN 1720 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1721 CFAP_ENABLE_ECCf, (enable ? 1 : 0))); 1722 break; 1723 case MMU_PKTLINK0m: 1724 SOC_IF_ERROR_RETURN 1725 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1726 PKTLINK_ENABLE_ECCf, (enable ? 1 : 0))); 1727 break; 1728 case MMU_CELLLINKm: 1729 SOC_IF_ERROR_RETURN 1730 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1731 CELLLINK_ENABLE_ECCf, (enable ? 1 : 0))); 1732 break; 1733 case MMU_CBPDATA0m: 1734 case MMU_CBPDATA1m: 1735 case MMU_CBPDATA2m: 1736 case MMU_CBPDATA3m: 1737 case MMU_CBPDATA4m: 1738 case MMU_CBPDATA5m: 1739 case MMU_CBPDATA6m: 1740 case MMU_CBPDATA7m: 1741 case MMU_CBPDATA8m: 1742 case MMU_CBPDATA9m: 1743 case MMU_CBPDATA10m: 1744 case MMU_CBPDATA11m: 1745 case MMU_CBPDATA12m: 1746 case MMU_CBPDATA13m: 1747 case MMU_CBPDATA14m: 1748 case MMU_CBPDATA15m: 1749 SOC_IF_ERROR_RETURN 1750 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1751 CELLDATA_ENABLE_ECCf, (enable ? 1 : 0))); 1752 break; 1753 case MMU_CBPPKTLENGTHm: 1754 SOC_IF_ERROR_RETURN 1755 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1756 PKTLENGTH_ENABLE_ECCf, (enable ? 1 : 0))); 1757 break; 1758 case MMU_CBPPKTHEADER0_MEM0m: 1759 case MMU_CBPPKTHEADER0_MEM1m: 1760 case MMU_CBPPKTHEADER0_MEM2m: 1761 case MMU_CBPPKTHEADER0_MEM3m: 1762 SOC_IF_ERROR_RETURN 1763 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1764 PKTHDR0_ENABLE_ECCf, (enable ? 1 : 0))); 1765 break; 1766 case MMU_AGING_EXPm: 1767 SOC_IF_ERROR_RETURN 1768 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 1769 DURATIONSELECTf, (enable ? 0x1000 : 0))); 1770 SOC_IF_ERROR_RETURN 1771 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1772 AGING_EXP_ENABLE_ECCf, (enable ? 1 : 0))); 1773 break; 1774 case MMU_AGING_CTRm: 1775 SOC_IF_ERROR_RETURN 1776 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 1777 DURATIONSELECTf, (enable ? 0x1000 : 0))); 1778 SOC_IF_ERROR_RETURN 1779 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1780 AGING_CTR_ENABLE_ECCf, (enable ? 1 : 0))); 1781 break; 1782 case ES_ARB_TDM_TABLEm: 1783 SOC_IF_ERROR_RETURN 1784 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG0r, REG_PORT_ANY, 1785 ES_ARB_TDM_TABLE_ENABLE_ECCf, 1786 (enable ? 1 : 0))); 1787 break; 1788 case CTR_MEMm: 1789 SOC_IF_ERROR_RETURN 1790 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1791 CTR_MEM_ENABLE_ECCf, (enable ? 1 : 0))); 1792 break; 1793 case MMU_WRED_PORT_THD_0_CELLm: 1794 SOC_IF_ERROR_RETURN 1795 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1796 WRED_PORT_THD_0_ENABLE_ECCf, 1797 (enable ? 1 : 0))); 1798 break; 1799 case MMU_WRED_PORT_THD_1_CELLm: 1800 SOC_IF_ERROR_RETURN 1801 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1802 WRED_PORT_THD_1_ENABLE_ECCf, 1803 (enable ? 1 : 0))); 1804 break; 1805 case MMU_WRED_THD_0_CELLm: 1806 SOC_IF_ERROR_RETURN 1807 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1808 WRED_THD_0_ENABLE_ECCf, 1809 (enable ? 1 : 0))); 1810 break; 1811 case MMU_WRED_THD_1_CELLm: 1812 SOC_IF_ERROR_RETURN 1813 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1814 WRED_THD_1_ENABLE_ECCf, 1815 (enable ? 1 : 0))); 1816 break; 1817 case MMU_WRED_PORT_CFG_CELLm: 1818 SOC_IF_ERROR_RETURN 1819 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1820 WRED_PORT_CFG_ENABLE_ECCf, 1821 (enable ? 1 : 0))); 1822 break; 1823 case MMU_WRED_CFG_CELLm: 1824 SOC_IF_ERROR_RETURN 1825 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1826 WRED_CFG_ENABLE_ECCf, 1827 (enable ? 1 : 0))); 1828 break; 1829 /* case MMU_MTRO_CPU_PKT_SHAPING_WRAPPERm: 1830 SOC_IF_ERROR_RETURN 1831 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1832 MTRO_CPU_PKT_ENABLE_ECCf, 1833 (enable ? 1 : 0))); 1834 break; 1835 case MMU_MTRO_SHAPE_G0_BUCKET_WRAPPERm: 1836 SOC_IF_ERROR_RETURN 1837 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1838 MTRO_SHAPE_G0_BUCKET_ENABLE_ECCf, 1839 (enable ? 1 : 0))); 1840 break; 1841 case MMU_MTRO_SHAPE_G0_CONFIG_WRAPPERm: 1842 SOC_IF_ERROR_RETURN 1843 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1844 MTRO_SHAPE_G0_CONFIG_ENABLE_ECCf, 1845 (enable ? 1 : 0))); 1846 break; 1847 case MMU_MTRO_SHAPE_G1_BUCKET_WRAPPERm: 1848 SOC_IF_ERROR_RETURN 1849 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1850 MTRO_SHAPE_G1_BUCKET_ENABLE_ECCf, 1851 (enable ? 1 : 0))); 1852 break; 1853 case MMU_MTRO_SHAPE_G1_CONFIG_WRAPPERm: 1854 SOC_IF_ERROR_RETURN 1855 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1856 MTRO_SHAPE_G1_CONFIG_ENABLE_ECCf, 1857 (enable ? 1 : 0))); 1858 break; 1859 case MMU_MTRO_SHAPE_G2_BUCKET_WRAPPERm: 1860 SOC_IF_ERROR_RETURN 1861 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1862 MTRO_SHAPE_G2_BUCKET_ENABLE_ECCf, 1863 (enable ? 1 : 0))); 1864 break; 1865 case MMU_MTRO_SHAPE_G2_CONFIG_WRAPPERm: 1866 SOC_IF_ERROR_RETURN 1867 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1868 MTRO_SHAPE_G2_CONFIG_ENABLE_ECCf, 1869 (enable ? 1 : 0))); 1870 break; 1871 case MMU_MTRO_SHAPE_G3_BUCKET_WRAPPERm: 1872 SOC_IF_ERROR_RETURN 1873 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1874 MTRO_SHAPE_G3_BUCKET_ENABLE_ECCf, 1875 (enable ? 1 : 0))); 1876 break; 1877 case MMU_MTRO_SHAPE_G3_CONFIG_WRAPPERm: 1878 SOC_IF_ERROR_RETURN 1879 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1880 MTRO_SHAPE_G3_CONFIG_ENABLE_ECCf, 1881 (enable ? 1 : 0))); 1882 break;*/ 1883 case ESEC_PKT_HEADER_CAPTURE_BUFFERm: 1884 SOC_IF_ERROR_RETURN 1885 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1886 DEBUGFF_ENABLE_ECCf, (enable ? 1 : 0))); 1887 SOC_IF_ERROR_RETURN 1888 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1889 DEBUGFF_ENABLE_ECCf, (enable ? 1 : 0))); 1890 break; 1891 case QL_TABLE0m: 1892 case QL_TABLE1m: 1893 SOC_IF_ERROR_RETURN 1894 (soc_reg_field32_modify(unit, MISCCONFIGr, REG_PORT_ANY, 1895 REFRESH_ENf, (enable ? 1 : 0))); 1896 break; 1897 case ESEC_SC_TABLEm: 1898 SOC_IF_ERROR_RETURN 1899 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1900 SCDB_ENABLE_ECCf, (enable ? 1 : 0))); 1901 SOC_IF_ERROR_RETURN 1902 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1903 SCDB_ENABLE_ECCf, (enable ? 1 : 0))); 1904 break; 1905 case ESEC_SA_TABLEm: 1906 SOC_IF_ERROR_RETURN 1907 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1908 SADB_ENABLE_ECCf, (enable ? 1 : 0))); 1909 SOC_IF_ERROR_RETURN 1910 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1911 SADB_ENABLE_ECCf, (enable ? 1 : 0))); 1912 break; 1913 case ESEC_SA_KEY_TABLEm: 1914 SOC_IF_ERROR_RETURN 1915 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1916 SAKEY_ENABLE_ECCf, (enable ? 1 : 0))); 1917 SOC_IF_ERROR_RETURN 1918 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1919 SAKEY_ENABLE_ECCf, (enable ? 1 : 0))); 1920 break; 1921 case OUTUNCTRLUCASTPKTSm: 1922 case OUTUNCTRLMCASTPKTSm: 1923 case OUTUNCTRLBCASTPKTSm: 1924 case OUTCTRLMCASTPKTSm: 1925 case OUTCTRLUCASTPKTSm: 1926 case OUTCTRLBCASTPKTSm: 1927 SOC_IF_ERROR_RETURN 1928 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1929 MIB1_ENABLE_ECCf, (enable ? 1 : 0))); 1930 SOC_IF_ERROR_RETURN 1931 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1932 MIB1_ENABLE_ECCf, (enable ? 1 : 0))); 1933 break; 1934 case TXSAPRTCPKTSm: 1935 case TXSACRPTPKTSm: 1936 SOC_IF_ERROR_RETURN 1937 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1938 MIB2_ENABLE_ECCf, (enable ? 1 : 0))); 1939 SOC_IF_ERROR_RETURN 1940 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1941 MIB2_ENABLE_ECCf, (enable ? 1 : 0))); 1942 break; 1943 case TXSCPRTCPKTSm: 1944 case TXSCCRPTPKTSm: 1945 SOC_IF_ERROR_RETURN 1946 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1947 MIB3_ENABLE_ECCf, (enable ? 1 : 0))); 1948 SOC_IF_ERROR_RETURN 1949 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1950 MIB3_ENABLE_ECCf, (enable ? 1 : 0))); 1951 break; 1952 case TXSCPRTCBYTm: 1953 SOC_IF_ERROR_RETURN 1954 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1955 MIB4_ENABLE_ECCf, (enable ? 1 : 0))); 1956 SOC_IF_ERROR_RETURN 1957 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1958 MIB4_ENABLE_ECCf, (enable ? 1 : 0))); 1959 break; 1960 case TXSCCRPTBYTm: 1961 SOC_IF_ERROR_RETURN 1962 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 1, 1963 MIB5_ENABLE_ECCf, (enable ? 1 : 0))); 1964 SOC_IF_ERROR_RETURN 1965 (soc_reg_field32_modify(unit, ESEC_ECC_DEBUGr, 5, 1966 MIB5_ENABLE_ECCf, (enable ? 1 : 0))); 1967 break; 1968 case IL_STAT_MEM_0m: 1969 SOC_IF_ERROR_RETURN 1970 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 9, 1971 IL_RX_STAT0_ENABLE_ECCf, 1972 (enable ? 1 : 0))); 1973 SOC_IF_ERROR_RETURN 1974 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 13, 1975 IL_RX_STAT0_ENABLE_ECCf, 1976 (enable ? 1 : 0))); 1977 SOC_IF_ERROR_RETURN 1978 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1979 XGS_COUNTER_COMPAT_MODEf, 1980 (enable ? 1 : 0))); 1981 SOC_IF_ERROR_RETURN 1982 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 1983 XGS_COUNTER_COMPAT_MODEf, 1984 (enable ? 1 : 0))); 1985 break; 1986 case IL_STAT_MEM_1m: 1987 SOC_IF_ERROR_RETURN 1988 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 9, 1989 IL_RX_STAT1_ENABLE_ECCf, 1990 (enable ? 1 : 0))); 1991 SOC_IF_ERROR_RETURN 1992 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 13, 1993 IL_RX_STAT1_ENABLE_ECCf, 1994 (enable ? 1 : 0))); 1995 SOC_IF_ERROR_RETURN 1996 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1997 XGS_COUNTER_COMPAT_MODEf, 1998 (enable ? 1 : 0))); 1999 SOC_IF_ERROR_RETURN 2000 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 2001 XGS_COUNTER_COMPAT_MODEf, 2002 (enable ? 1 : 0))); 2003 break; 2004 case IL_STAT_MEM_2m: 2005 SOC_IF_ERROR_RETURN 2006 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 9, 2007 IL_RX_STAT2_ENABLE_ECCf, 2008 (enable ? 1 : 0))); 2009 SOC_IF_ERROR_RETURN 2010 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 13, 2011 IL_RX_STAT2_ENABLE_ECCf, 2012 (enable ? 1 : 0))); 2013 SOC_IF_ERROR_RETURN 2014 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 2015 XGS_COUNTER_COMPAT_MODEf, 2016 (enable ? 1 : 0))); 2017 SOC_IF_ERROR_RETURN 2018 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 2019 XGS_COUNTER_COMPAT_MODEf, 2020 (enable ? 1 : 0))); 2021 break; 2022 case IL_STAT_MEM_3m: 2023 SOC_IF_ERROR_RETURN 2024 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 9, 2025 IL_TX_STAT0_ENABLE_ECCf, 2026 (enable ? 1 : 0))); 2027 SOC_IF_ERROR_RETURN 2028 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 13, 2029 IL_TX_STAT0_ENABLE_ECCf, 2030 (enable ? 1 : 0))); 2031 SOC_IF_ERROR_RETURN 2032 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 2033 XGS_COUNTER_COMPAT_MODEf, 2034 (enable ? 1 : 0))); 2035 SOC_IF_ERROR_RETURN 2036 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 2037 XGS_COUNTER_COMPAT_MODEf, 2038 (enable ? 1 : 0))); 2039 break; 2040 case IL_STAT_MEM_4m: 2041 SOC_IF_ERROR_RETURN 2042 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 9, 2043 IL_TX_STAT1_ENABLE_ECCf, 2044 (enable ? 1 : 0))); 2045 SOC_IF_ERROR_RETURN 2046 (soc_reg_field32_modify(unit, IL_ECC_DEBUG0r, 13, 2047 IL_TX_STAT1_ENABLE_ECCf, 2048 (enable ? 1 : 0))); 2049 SOC_IF_ERROR_RETURN 2050 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 2051 XGS_COUNTER_COMPAT_MODEf, 2052 (enable ? 1 : 0))); 2053 SOC_IF_ERROR_RETURN 2054 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 2055 XGS_COUNTER_COMPAT_MODEf, 2056 (enable ? 1 : 0))); 2057 break; 2058 case ISEC_SA_TABLEm: 2059 case ISEC_SA_KEY_TABLEm: 2060 SOC_IF_ERROR_RETURN 2061 (soc_reg_field32_modify(unit, DEBUG20r, 1, SA1_EN_ECCf, 2062 (enable ? 1 : 0))); 2063 SOC_IF_ERROR_RETURN 2064 (soc_reg_field32_modify(unit, DEBUG20r, 5, SA1_EN_ECCf, 2065 (enable ? 1 : 0))); 2066 SOC_IF_ERROR_RETURN 2067 (soc_reg_field32_modify(unit, DEBUG20r, 1, SA2_EN_ECCf, 2068 (enable ? 1 : 0))); 2069 SOC_IF_ERROR_RETURN 2070 (soc_reg_field32_modify(unit, DEBUG20r, 5, SA2_EN_ECCf, 2071 (enable ? 1 : 0))); 2072 break; 2073 case RXSAUNUSEDSAPKTSm: 2074 SOC_IF_ERROR_RETURN 2075 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2076 RXSASTATSUNUSEDSAPKTS_EN_ECCf, 2077 (enable ? 1 : 0))); 2078 SOC_IF_ERROR_RETURN 2079 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2080 RXSASTATSUNUSEDSAPKTS_EN_ECCf, 2081 (enable ? 1 : 0))); 2082 break; 2083 case RXSANOTUSINGSAPKTSm: 2084 SOC_IF_ERROR_RETURN 2085 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2086 RXSASTATSNOTUSINGSAPKTS_EN_ECCf, 2087 (enable ? 1 : 0))); 2088 SOC_IF_ERROR_RETURN 2089 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2090 RXSASTATSNOTUSINGSAPKTS_EN_ECCf, 2091 (enable ? 1 : 0))); 2092 break; 2093 case RXSANOTVLDPKTSm: 2094 SOC_IF_ERROR_RETURN 2095 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2096 RXSASTATSNOTVALIDPKTS_EN_ECCf, 2097 (enable ? 1 : 0))); 2098 SOC_IF_ERROR_RETURN 2099 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2100 RXSASTATSNOTVALIDPKTS_EN_ECCf, 2101 (enable ? 1 : 0))); 2102 break; 2103 case RXSAINVLDPKTSm: 2104 SOC_IF_ERROR_RETURN 2105 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2106 RXSASTATSINVALIDPKTS_EN_ECCf, 2107 (enable ? 1 : 0))); 2108 SOC_IF_ERROR_RETURN 2109 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2110 RXSASTATSINVALIDPKTS_EN_ECCf, 2111 (enable ? 1 : 0))); 2112 break; 2113 case RXSAOKPKTSm: 2114 SOC_IF_ERROR_RETURN 2115 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2116 RXSASTATSOKPKTS_EN_ECCf, 2117 (enable ? 1 : 0))); 2118 SOC_IF_ERROR_RETURN 2119 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2120 RXSASTATSOKPKTS_EN_ECCf, 2121 (enable ? 1 : 0))); 2122 break; 2123 case INCTRLUCASTPKTSm: 2124 case INCTRLMCASTPKTSm: 2125 case INCTRLBCASTPKTSm: 2126 SOC_IF_ERROR_RETURN 2127 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2128 RXPACKETTYPE_EN_ECCf, 2129 (enable ? 1 : 0))); 2130 SOC_IF_ERROR_RETURN 2131 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2132 RXPACKETTYPE_EN_ECCf, 2133 (enable ? 1 : 0))); 2134 break; 2135 case INCTRLDISCPKTSm: 2136 case INCTRLERRPKTSm: 2137 SOC_IF_ERROR_RETURN 2138 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2139 RXERRDSCRDSPKTS_EN_ECCf, 2140 (enable ? 1 : 0))); 2141 SOC_IF_ERROR_RETURN 2142 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2143 RXERRDSCRDSPKTS_EN_ECCf, 2144 (enable ? 1 : 0))); 2145 break; 2146 case RXUNTAGPKTSm: 2147 case RXNOTAGPKTSm: 2148 case RXBADTAGPKTSm: 2149 SOC_IF_ERROR_RETURN 2150 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2151 RXTAGUNTAGNONEBAD_EN_ECCf, 2152 (enable ? 1 : 0))); 2153 SOC_IF_ERROR_RETURN 2154 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2155 RXTAGUNTAGNONEBAD_EN_ECCf, 2156 (enable ? 1 : 0))); 2157 break; 2158 case RXUNKNOWNSCIPKTSm: 2159 case RXNOSCIPKTSm: 2160 SOC_IF_ERROR_RETURN 2161 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2162 RXSCIUNKNOWNNONEPKTS_EN_ECCf, 2163 (enable ? 1 : 0))); 2164 SOC_IF_ERROR_RETURN 2165 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2166 RXSCIUNKNOWNNONEPKTS_EN_ECCf, 2167 (enable ? 1 : 0))); 2168 break; 2169 case RXSCUNUSEDSAPKTSm: 2170 SOC_IF_ERROR_RETURN 2171 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2172 RXSCSTATSUNUSEDSAPKTS_EN_ECCf, 2173 (enable ? 1 : 0))); 2174 SOC_IF_ERROR_RETURN 2175 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2176 RXSCSTATSUNUSEDSAPKTS_EN_ECCf, 2177 (enable ? 1 : 0))); 2178 break; 2179 case RXSCNOTUSINGSAPKTSm: 2180 SOC_IF_ERROR_RETURN 2181 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2182 RXSCSTATSNOTUSINGSAPKTS_EN_ECCf, 2183 (enable ? 1 : 0))); 2184 SOC_IF_ERROR_RETURN 2185 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2186 RXSCSTATSNOTUSINGSAPKTS_EN_ECCf, 2187 (enable ? 1 : 0))); 2188 break; 2189 case RXSCLATEPKTSm: 2190 SOC_IF_ERROR_RETURN 2191 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2192 RXSCSTATSLATEPKTS_EN_ECCf, 2193 (enable ? 1 : 0))); 2194 SOC_IF_ERROR_RETURN 2195 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2196 RXSCSTATSLATEPKTS_EN_ECCf, 2197 (enable ? 1 : 0))); 2198 break; 2199 case RXSCNOTVLDPKTSm: 2200 SOC_IF_ERROR_RETURN 2201 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2202 RXSCSTATSNOTVALIDPKTS_EN_ECCf, 2203 (enable ? 1 : 0))); 2204 SOC_IF_ERROR_RETURN 2205 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2206 RXSCSTATSNOTVALIDPKTS_EN_ECCf, 2207 (enable ? 1 : 0))); 2208 break; 2209 case RXSCINVLDPKTSm: 2210 SOC_IF_ERROR_RETURN 2211 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2212 RXSCSTATSINVALIDPKTS_EN_ECCf, 2213 (enable ? 1 : 0))); 2214 SOC_IF_ERROR_RETURN 2215 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2216 RXSCSTATSINVALIDPKTS_EN_ECCf, 2217 (enable ? 1 : 0))); 2218 break; 2219 case RXSCDLYPKTSm: 2220 SOC_IF_ERROR_RETURN 2221 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2222 RXSCSTATSDELAYEDPKTS_EN_ECCf, 2223 (enable ? 1 : 0))); 2224 SOC_IF_ERROR_RETURN 2225 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2226 RXSCSTATSDELAYEDPKTS_EN_ECCf, 2227 (enable ? 1 : 0))); 2228 break; 2229 case RXSCUNCHKPKTSm: 2230 SOC_IF_ERROR_RETURN 2231 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2232 RXSCSTATSUNCHECKEDPKTS_EN_ECCf, 2233 (enable ? 1 : 0))); 2234 SOC_IF_ERROR_RETURN 2235 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2236 RXSCSTATSUNCHECKEDPKTS_EN_ECCf, 2237 (enable ? 1 : 0))); 2238 break; 2239 case RXSCOKPKTSm: 2240 SOC_IF_ERROR_RETURN 2241 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2242 RXSCSTATSOKPKTS_EN_ECCf, 2243 (enable ? 1 : 0))); 2244 SOC_IF_ERROR_RETURN 2245 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2246 RXSCSTATSOKPKTS_EN_ECCf, 2247 (enable ? 1 : 0))); 2248 break; 2249 case RXSCVLDTBYTm: 2250 SOC_IF_ERROR_RETURN 2251 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2252 RXSCSTATSOCTETSVALIDATED_EN_ECCf, 2253 (enable ? 1 : 0))); 2254 SOC_IF_ERROR_RETURN 2255 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2256 RXSCSTATSOCTETSVALIDATED_EN_ECCf, 2257 (enable ? 1 : 0))); 2258 break; 2259 case RXSCDCRPTBYTm: 2260 SOC_IF_ERROR_RETURN 2261 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2262 RXSCSTATSOCTETSDECRYPTED_EN_ECCf, 2263 (enable ? 1 : 0))); 2264 SOC_IF_ERROR_RETURN 2265 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2266 RXSCSTATSOCTETSDECRYPTED_EN_ECCf, 2267 (enable ? 1 : 0))); 2268 break; 2269 case FILTERMATCHCOUNTm: 2270 SOC_IF_ERROR_RETURN 2271 (soc_reg_field32_modify(unit, DEBUG20r, 1, 2272 FILTERMATCHCOUNT_EN_ECCf, 2273 (enable ? 1 : 0))); 2274 SOC_IF_ERROR_RETURN 2275 (soc_reg_field32_modify(unit, DEBUG20r, 5, 2276 FILTERMATCHCOUNT_EN_ECCf, 2277 (enable ? 1 : 0))); 2278 break; 2279 case ISEC_DEBUG_RAMm: 2280 SOC_IF_ERROR_RETURN 2281 (soc_reg_field32_modify(unit, DEBUG20r, 1, DEBUGRAM_EN_ECCf, 2282 (enable ? 1 : 0))); 2283 SOC_IF_ERROR_RETURN 2284 (soc_reg_field32_modify(unit, DEBUG20r, 5, DEBUGRAM_EN_ECCf, 2285 (enable ? 1 : 0))); 2286 break; 2287 default: 2288 return SOC_E_NONE; /* do nothing */ 2289 } 2290 return SOC_E_NONE; 2291 } 2292 #endif 2293 2294 #ifdef BCM_BRADLEY_SUPPORT 2295 STATIC int 2296 _soc_hb_mem_parity_control(int unit, soc_mem_t mem, int copyno, int enable) 2297 { 2298 uint32 rval, orval, imask, oimask, 2299 misc_cfg, sbs_ctrl; 2300 soc_reg_t mctlreg = INVALIDr, sbsreg = INVALIDr; 2301 soc_field_t imask_f[4] = { INVALIDf, INVALIDf, INVALIDf, INVALIDf }; 2302 int en_val = enable ? 1 : 0; 2303 int i; 2304 2305 COMPILER_REFERENCE(copyno); 2306 2307 switch (mem) { 2308 case VLAN_TABm: 2309 if (!SOC_IS_SHADOW(unit)) { 2310 mctlreg = VLAN_PARITY_CONTROLr; 2311 imask_f[0] = TOQ0_VLAN_TBL_PAR_ERR_ENf; 2312 imask_f[1] = TOQ1_VLAN_TBL_PAR_ERR_ENf; 2313 imask_f[2] = MEM1_VLAN_TBL_PAR_ERR_ENf; 2314 sbsreg = SBS_CONTROLr; 2315 } 2316 break; 2317 case L2Xm: 2318 case L2_ENTRY_ONLYm: 2319 #ifdef BCM_SCORPION_SUPPORT 2320 case L2_ENTRY_SCRATCHm: 2321 #endif 2322 mctlreg = L2_ENTRY_PARITY_CONTROLr; 2323 break; 2324 case L2MCm: 2325 mctlreg = L2MC_PARITY_CONTROLr; 2326 sbsreg = SBS_CONTROLr; 2327 break; 2328 case L3_ENTRY_ONLYm: 2329 case L3_ENTRY_VALID_ONLYm: 2330 case L3_ENTRY_IPV4_UNICASTm: 2331 case L3_ENTRY_IPV4_MULTICASTm: 2332 case L3_ENTRY_IPV6_UNICASTm: 2333 case L3_ENTRY_IPV6_MULTICASTm: 2334 mctlreg = L3_ENTRY_PARITY_CONTROLr; 2335 break; 2336 case EGR_L3_INTFm: 2337 mctlreg = EGR_L3_INTF_PARITY_CONTROLr; 2338 sbsreg = EGR_SBS_CONTROLr; 2339 break; 2340 case EGR_L3_NEXT_HOPm: 2341 mctlreg = EGR_L3_NEXT_HOP_PARITY_CONTROLr; 2342 sbsreg = EGR_SBS_CONTROLr; 2343 break; 2344 case EGR_VLANm: 2345 if (!SOC_IS_SHADOW(unit)) { 2346 mctlreg = EGR_VLAN_PARITY_CONTROLr; 2347 sbsreg = EGR_SBS_CONTROLr; 2348 } 2349 break; 2350 #ifdef BCM_SCORPION_SUPPORT 2351 case SOURCE_TRUNK_MAP_TABLEm: 2352 if (SOC_IS_SC_CQ(unit) && !SOC_IS_SHADOW(unit)) { 2353 mctlreg = SRC_TRUNK_PARITY_CONTROLr; 2354 sbsreg = SBS_CONTROLr; 2355 } /* No parity in Bradley */ 2356 break; 2357 case VLAN_MACm: 2358 case VLAN_XLATEm: 2359 if (SOC_IS_SC_CQ(unit) && !SOC_IS_SHADOW(unit)) { 2360 mctlreg = VLAN_MAC_OR_XLATE_PARITY_CONTROLr; 2361 sbsreg = SBS_CONTROLr; 2362 } /* No parity in Bradley */ 2363 break; 2364 case VFP_POLICY_TABLEm: 2365 if (SOC_IS_SC_CQ(unit)) { 2366 mctlreg = VFP_POLICY_TABLE_PARITY_CONTROLr; 2367 sbsreg = SBS_CONTROLr; 2368 } /* No parity in Bradley */ 2369 break; 2370 case L3_DEFIPm: 2371 case L3_DEFIP_DATA_ONLYm: 2372 if (SOC_IS_SC_CQ(unit)) { 2373 mctlreg = L3_DEFIP_PARITY_CONTROLr; 2374 sbsreg = SBS_CONTROLr; 2375 } /* No parity in Bradley */ 2376 break; 2377 case INITIAL_ING_L3_NEXT_HOPm: 2378 if (SOC_IS_SC_CQ(unit)) { 2379 mctlreg = INITIAL_ING_L3_NEXT_HOP_PARITY_CONTROLr; 2380 sbsreg = SBS_CONTROLr; 2381 } /* No parity in Bradley */ 2382 break; 2383 case FP_POLICY_TABLEm: 2384 if (SOC_IS_SC_CQ(unit) && !SOC_IS_SHADOW(unit)) { 2385 mctlreg = IFP_POLICY_TABLE_PARITY_CONTROLr; 2386 sbsreg = SBS_CONTROLr; 2387 } /* No parity in Bradley */ 2388 break; 2389 case ING_L3_NEXT_HOPm: 2390 if (SOC_IS_SC_CQ(unit)) { 2391 mctlreg = ING_L3_NEXT_HOP_PARITY_CONTROLr; 2392 sbsreg = SBS_CONTROLr; 2393 } /* No parity in Bradley */ 2394 break; 2395 case EGR_MASKm: 2396 if (SOC_IS_SC_CQ(unit) && !SOC_IS_SHADOW(unit)) { 2397 mctlreg = EGR_MASK_PARITY_CONTROLr; 2398 sbsreg = SBS_CONTROLr; 2399 } /* No parity in Bradley */ 2400 break; 2401 case SRC_MODID_BLOCKm: 2402 if (SOC_IS_SC_CQ(unit)) { 2403 mctlreg = SRC_MODID_BLOCK_PARITY_CONTROLr; 2404 sbsreg = SBS_CONTROLr; 2405 } /* No parity in Bradley */ 2406 break; 2407 case MODPORT_MAPm: 2408 case MODPORT_MAP_SWm: 2409 if (SOC_IS_SC_CQ(unit)) { 2410 mctlreg = MODPORT_MAP_SW_PARITY_CONTROLr; 2411 sbsreg = SBS_CONTROLr; 2412 } /* No parity in Bradley */ 2413 break; 2414 case MODPORT_MAP_IMm: 2415 if (SOC_IS_SC_CQ(unit)) { 2416 mctlreg = MODPORT_MAP_IM_PARITY_CONTROLr; 2417 sbsreg = SBS_CONTROLr; 2418 } /* No parity in Bradley */ 2419 break; 2420 case MODPORT_MAP_EMm: 2421 if (SOC_IS_SC_CQ(unit)) { 2422 mctlreg = MODPORT_MAP_EM_PARITY_CONTROLr; 2423 sbsreg = SBS_CONTROLr; 2424 } /* No parity in Bradley */ 2425 break; 2426 case EGR_VLAN_XLATEm: 2427 if (SOC_IS_SC_CQ(unit) && !SOC_IS_SHADOW(unit)) { 2428 mctlreg = EGR_VLAN_XLATE_PARITY_CONTROLr; 2429 sbsreg = EGR_SBS_CONTROLr; 2430 } 2431 break; 2432 case EGR_IP_TUNNELm: 2433 case EGR_IP_TUNNEL_IPV6m: 2434 if (SOC_IS_SC_CQ(unit)) { 2435 mctlreg = EGR_IP_TUNNEL_PARITY_CONTROLr; 2436 sbsreg = EGR_SBS_CONTROLr; 2437 } /* No parity in Bradley */ 2438 break; 2439 #endif 2440 case MMU_AGING_CTRm: 2441 imask_f[0] = AGING_CTR_PAR_ERR_ENf; 2442 break; 2443 case MMU_AGING_EXPm: 2444 imask_f[0] = AGING_EXP_PAR_ERR_ENf; 2445 break; 2446 case L3_IPMCm: 2447 #ifdef BCM_SCORPION_SUPPORT 2448 if (SOC_IS_SC_CQ(unit)) { 2449 mctlreg = L3MC_PARITY_CONTROLr; 2450 sbsreg = SBS_CONTROLr; 2451 } 2452 /* Fall through */ 2453 #endif 2454 case MMU_IPMC_VLAN_TBLm: 2455 case MMU_IPMC_VLAN_TBL_MEM0m: 2456 case MMU_IPMC_VLAN_TBL_MEM1m: 2457 case MMU_IPMC_GROUP_TBL0m: 2458 case MMU_IPMC_GROUP_TBL1m: 2459 case MMU_IPMC_GROUP_TBL2m: 2460 case MMU_IPMC_GROUP_TBL3m: 2461 #ifdef BCM_SCORPION_SUPPORT 2462 case MMU_IPMC_GROUP_TBL4m: 2463 case MMU_IPMC_GROUP_TBL5m: 2464 case MMU_IPMC_GROUP_TBL6m: 2465 #endif 2466 imask_f[0] = TOQ0_IPMC_TBL_PAR_ERR_ENf; 2467 imask_f[1] = TOQ1_IPMC_TBL_PAR_ERR_ENf; 2468 imask_f[2] = MEM1_IPMC_TBL_PAR_ERR_ENf; 2469 imask_f[3] = ENQ_IPMC_TBL_PAR_ERR_ENf; 2470 break; 2471 case MMU_CFAP_MEMm : 2472 imask_f[0] = CFAP_PAR_ERR_ENf; 2473 break; 2474 case MMU_CCP_MEMm : 2475 imask_f[0] = CCP_PAR_ERR_ENf; 2476 break; 2477 case MMU_CELLLINKm: 2478 imask_f[0] = TOQ0_CELLLINK_PAR_ERR_ENf; 2479 imask_f[1] = TOQ1_CELLLINK_PAR_ERR_ENf; 2480 break; 2481 case MMU_PKTLINK0m: 2482 case MMU_PKTLINK1m: 2483 case MMU_PKTLINK2m: 2484 case MMU_PKTLINK3m: 2485 case MMU_PKTLINK4m: 2486 case MMU_PKTLINK5m: 2487 case MMU_PKTLINK6m: 2488 case MMU_PKTLINK7m: 2489 case MMU_PKTLINK8m: 2490 case MMU_PKTLINK9m: 2491 case MMU_PKTLINK10m: 2492 case MMU_PKTLINK11m: 2493 case MMU_PKTLINK12m: 2494 case MMU_PKTLINK13m: 2495 case MMU_PKTLINK14m: 2496 case MMU_PKTLINK15m: 2497 case MMU_PKTLINK16m: 2498 case MMU_PKTLINK17m: 2499 case MMU_PKTLINK18m: 2500 case MMU_PKTLINK19m: 2501 case MMU_PKTLINK20m: 2502 #ifdef BCM_TRX_SUPPORT 2503 case MMU_PKTLINK21m: 2504 case MMU_PKTLINK22m: 2505 case MMU_PKTLINK23m: 2506 case MMU_PKTLINK24m: 2507 case MMU_PKTLINK25m: 2508 case MMU_PKTLINK26m: 2509 case MMU_PKTLINK27m: 2510 case MMU_PKTLINK28m: 2511 #endif 2512 imask_f[0] = TOQ0_PKTLINK_PAR_ERR_ENf; 2513 imask_f[1] = TOQ1_PKTLINK_PAR_ERR_ENf; 2514 break; 2515 case MMU_CBPPKTHEADER0_MEM0m: 2516 case MMU_CBPPKTHEADER0_MEM1m: 2517 case MMU_CBPPKTHEADER0_MEM2m: 2518 case MMU_CBPPKTHEADER1_MEM0m: 2519 case MMU_CBPPKTHEADER1_MEM1m: 2520 case MMU_CBPPKTHEADERCPUm: 2521 #ifdef BCM_SCORPION_SUPPORT 2522 case MMU_CBPPKTHEADER0_MEM3m: 2523 #endif 2524 imask_f[0] = TOQ0_PKTHDR1_PAR_ERR_ENf; 2525 imask_f[1] = TOQ1_PKTHDR1_PAR_ERR_ENf; 2526 break; 2527 case MMU_CBPCELLHEADERm: 2528 imask_f[0] = TOQ0_CELLHDR_PAR_ERR_ENf; 2529 imask_f[1] = TOQ1_CELLHDR_PAR_ERR_ENf; 2530 break; 2531 case MMU_CBPDATA0m: 2532 case MMU_CBPDATA1m: 2533 case MMU_CBPDATA2m: 2534 case MMU_CBPDATA3m: 2535 case MMU_CBPDATA4m: 2536 case MMU_CBPDATA5m: 2537 case MMU_CBPDATA6m: 2538 case MMU_CBPDATA7m: 2539 case MMU_CBPDATA8m: 2540 case MMU_CBPDATA9m: 2541 case MMU_CBPDATA10m: 2542 case MMU_CBPDATA11m: 2543 case MMU_CBPDATA12m: 2544 case MMU_CBPDATA13m: 2545 case MMU_CBPDATA14m: 2546 case MMU_CBPDATA15m: 2547 /* Covered by CRC */ 2548 imask_f[0] = DEQ0_CELLCRC_ERR_ENf; 2549 imask_f[1] = DEQ1_CELLCRC_ERR_ENf; 2550 break; 2551 case MMU_CBPPKTLENGTHm: 2552 /* Covered by CRC */ 2553 imask_f[0] = DEQ0_LENGTH_PAR_ERR_ENf; 2554 imask_f[1] = DEQ1_LENGTH_PAR_ERR_ENf; 2555 break; 2556 2557 case MMU_WRED_CFG_CELLm: 2558 case MMU_WRED_PORT_CFG_CELLm: 2559 case MMU_WRED_PORT_THD_0_CELLm: 2560 case MMU_WRED_PORT_THD_1_CELLm: 2561 case MMU_WRED_THD_0_CELLm: 2562 case MMU_WRED_THD_1_CELLm: 2563 imask_f[0] = WRED_PAR_ERR_ENf; 2564 break; 2565 default: 2566 /* Do nothing */ 2567 return SOC_E_NONE; 2568 } 2569 2570 /* 2571 * Turn off parity 2572 */ 2573 if (mctlreg != INVALIDr) { 2574 /* Memory has a separate parity control */ 2575 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mctlreg, REG_PORT_ANY, 0, &rval)); 2576 orval = rval; 2577 soc_reg_field_set(unit, mctlreg, &rval, PARITY_ENf, en_val); 2578 soc_reg_field_set(unit, mctlreg, &rval, PARITY_IRQ_ENf, en_val); 2579 if (orval != rval) { 2580 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mctlreg, REG_PORT_ANY, 0, rval)); 2581 } 2582 2583 if ((sbsreg != INVALIDr) && (!SOC_IS_SHADOW(unit))) { /* Dual pipe controls needed */ 2584 sbs_ctrl = 0; 2585 soc_reg_field_set(unit, sbsreg, &sbs_ctrl, PIPE_SELECTf, 2586 SOC_PIPE_SELECT_Y); 2587 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, sbsreg, REG_PORT_ANY, 0, sbs_ctrl)); 2588 2589 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mctlreg, REG_PORT_ANY, 0, &rval)); 2590 orval = rval; 2591 soc_reg_field_set(unit, mctlreg, &rval, PARITY_ENf, en_val); 2592 soc_reg_field_set(unit, mctlreg, &rval, PARITY_IRQ_ENf, en_val); 2593 if (orval != rval) { 2594 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mctlreg, REG_PORT_ANY, 0, rval)); 2595 } 2596 2597 soc_reg_field_set(unit, sbsreg, &sbs_ctrl, PIPE_SELECTf, 2598 SOC_PIPE_SELECT_X); 2599 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, sbsreg, REG_PORT_ANY, 0, sbs_ctrl)); 2600 } 2601 } else { 2602 /* Memory does not have a separate parity control */ 2603 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 2604 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_STAT_CLEARf, 1); 2605 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 2606 2607 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_STAT_CLEARf, 0); 2608 if (soc_reg_field_valid(unit, MISCCONFIGr, PARITY_GEN_ENf)) { 2609 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_GEN_ENf, en_val); 2610 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHK_ENf, en_val); 2611 } 2612 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, REFRESH_ENf, en_val); 2613 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 2614 } 2615 2616 /* 2617 * Disable parity and CRC interrupts 2618 */ 2619 if ((imask_f[0] != INVALIDr) && SOC_REG_IS_VALID(unit, MEM_FAIL_INT_ENr)) { 2620 SOC_IF_ERROR_RETURN(READ_MEM_FAIL_INT_ENr(unit, &imask)); 2621 oimask = imask; 2622 for (i = 0; i < COUNTOF(imask_f); i++) { 2623 if (imask_f[i] != INVALIDr) { 2624 soc_reg_field_set(unit, MEM_FAIL_INT_ENr, &imask, 2625 imask_f[i], en_val); 2626 } 2627 } 2628 if (oimask != imask) { 2629 SOC_IF_ERROR_RETURN(WRITE_MEM_FAIL_INT_ENr(unit, imask)); 2630 } 2631 } 2632 2633 return SOC_E_NONE; 2634 } 2635 #endif /* BCM_BRADLEY_SUPPORT */ 2636 2637 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 2638 /* 2639 * Toggle parity checks during memory tests 2640 */ 2641 int 2642 soc_mem_parity_control(int unit, soc_mem_t mem, int copyno, int enable) 2643 { 2644 if (mem != INVALIDm) { 2645 LOG_VERBOSE(BSL_LS_SOC_SER, 2646 (BSL_META_U(unit, 2647 "soc_mem_parity_control: unit %d memory %s.%s %sable\n"), 2648 unit, SOC_MEM_UFNAME(unit, mem), 2649 SOC_BLOCK_NAME(unit, copyno), 2650 enable ? "en" : "dis")); 2651 } 2652 #ifdef BCM_TRIDENT3_SUPPORT 2653 if (SOC_IS_TRIDENT3(unit)) { 2654 return soc_trident3_mem_ser_control(unit, mem, copyno, enable); 2655 } 2656 #endif 2657 #ifdef BCM_MAVERICK2_SUPPORT 2658 if (SOC_IS_MAVERICK2(unit)) { 2659 return soc_mv2_mem_ser_control(unit, mem, copyno, enable); 2660 } 2661 #endif 2662 #ifdef BCM_HELIX5_SUPPORT 2663 if (SOC_IS_HELIX5(unit)) { 2664 return soc_hx5_mem_ser_control(unit, mem, copyno, enable); 2665 } 2666 #endif 2667 #ifdef BCM_SHADOW_SUPPORT 2668 if (SOC_IS_SHADOW(unit)) { 2669 return _soc_shadow_mem_parity_control(unit, mem, copyno, enable); 2670 } 2671 #endif /* BCM_SHADOW_SUPPORT */ 2672 #ifdef BCM_TOMAHAWK3_SUPPORT 2673 if (SOC_IS_TOMAHAWK3(unit)) { 2674 return soc_tomahawk3_mem_ser_control(unit, mem, copyno, enable); 2675 } 2676 #endif /* BCM_TOMAHAWK3_SUPPORT */ 2677 #if defined(BCM_TOMAHAWK_SUPPORT) || defined(BCM_TOMAHAWK2_SUPPORT) 2678 if (SOC_IS_TOMAHAWK(unit) || SOC_IS_TOMAHAWK2(unit)) { 2679 return soc_tomahawk_mem_ser_control(unit, mem, copyno, enable); 2680 } 2681 #endif /* BCM_TOMAHAWK_SUPPORT */ 2682 #ifdef BCM_MONTEREY_SUPPORT 2683 if (SOC_IS_MONTEREY(unit)) { 2684 return _soc_monterey_mem_ser_control(unit, mem, copyno, enable); 2685 } 2686 #endif /* BCM_MONTEREY_SUPPORT */ 2687 #ifdef BCM_TRIDENT3_SUPPORT 2688 if (SOC_IS_TRIDENT3X(unit)) { 2689 2690 return SOC_E_NONE; 2691 } 2692 #endif /* BCM_MONTEREY_SUPPORT */ 2693 #ifdef BCM_APACHE_SUPPORT 2694 if (SOC_IS_APACHE(unit)) { 2695 return _soc_apache_mem_ser_control(unit, mem, copyno, enable); 2696 } 2697 #endif /* BCM_APACHE_SUPPORT */ 2698 #ifdef BCM_TRIDENT2_SUPPORT 2699 if (SOC_IS_TD2_TT2(unit)) { 2700 return _soc_trident2_mem_ser_control(unit, mem, copyno, enable); 2701 } 2702 #endif /* BCM_TRIDENT2_SUPPORT */ 2703 #ifdef BCM_TRIDENT_SUPPORT 2704 if (SOC_IS_TD_TT(unit)) { 2705 return _soc_trident_mem_parity_control(unit, mem, copyno, enable); 2706 } 2707 #endif /* BCM_TRIDENT_SUPPORT */ 2708 #ifdef BCM_TRIUMPH3_SUPPORT 2709 if (SOC_IS_TRIUMPH3(unit)) { 2710 return _soc_triumph3_mem_parity_control(unit, mem, copyno, enable); 2711 } 2712 #endif /* BCM_TRIUMPH3_SUPPORT */ 2713 #ifdef BCM_TRIUMPH2_SUPPORT 2714 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit)) { 2715 return _soc_triumph2_mem_parity_control(unit, mem, copyno, enable); 2716 } 2717 #endif /* BCM_TRIUMPH2_SUPPORT */ 2718 2719 #ifdef BCM_ENDURO_SUPPORT 2720 if (SOC_IS_ENDURO(unit)) { 2721 return _soc_enduro_mem_parity_control(unit, mem, copyno, enable); 2722 } 2723 #endif /* BCM_ENDURO_SUPPORT */ 2724 #ifdef BCM_HURRICANE1_SUPPORT 2725 if (SOC_IS_HURRICANE(unit)) { 2726 return _soc_hurricane_mem_parity_control(unit, mem, copyno, enable); 2727 } 2728 #endif /* BCM_HURRICANE_SUPPORT */ 2729 #ifdef BCM_HURRICANE2_SUPPORT 2730 if (SOC_IS_HURRICANE2(unit)) { 2731 return _soc_hurricane2_mem_parity_control(unit, mem, copyno, enable); 2732 } 2733 #endif /* BCM_HURRICANE2_SUPPORT */ 2734 #ifdef BCM_HURRICANE3_SUPPORT 2735 if (SOC_IS_HURRICANE3(unit)) { 2736 return _soc_hr3_mem_parity_control(unit, mem, copyno, enable); 2737 } 2738 #endif /* BCM_HURRICANE3_SUPPORT */ 2739 #ifdef BCM_GREYHOUND2_SUPPORT 2740 if (SOC_IS_GREYHOUND2(unit)) { 2741 return _soc_gh2_mem_parity_control(unit, mem, copyno, enable); 2742 } 2743 #endif /* BCM_GREYHOUND2_SUPPORT */ 2744 #ifdef BCM_GREYHOUND_SUPPORT 2745 if (SOC_IS_GREYHOUND(unit)) { 2746 return _soc_greyhound_mem_parity_control(unit, mem, copyno, enable); 2747 } 2748 #endif /* BCM_GREYHOUND_SUPPORT */ 2749 2750 #ifdef BCM_KATANA_SUPPORT 2751 if (SOC_IS_KATANA(unit)) { 2752 return _soc_katana_mem_parity_control(unit, mem, copyno, enable); 2753 } 2754 #endif /* BCM_KATANA_SUPPORT */ 2755 #ifdef BCM_SABER2_SUPPORT 2756 if (SOC_IS_SABER2(unit)) { 2757 return soc_saber2_mem_parity_control(unit, mem, copyno, enable); 2758 } 2759 #endif /* BCM_SABER2_SUPPORT */ 2760 #ifdef BCM_KATANA2_SUPPORT 2761 if (SOC_IS_KATANA2(unit)) { 2762 return _soc_katana2_mem_parity_control(unit, mem, copyno, enable); 2763 } 2764 #endif /* BCM_KATANA2_SUPPORT */ 2765 #ifdef BCM_FIREBOLT_SUPPORT 2766 if (SOC_IS_FB_FX_HX(unit)) { 2767 return _soc_fb_mem_parity_control(unit, mem, copyno, enable); 2768 } 2769 #endif /* BCM_FIREBOLT_SUPPORT */ 2770 2771 #ifdef BCM_BRADLEY_SUPPORT 2772 if (SOC_IS_HBX(unit)) { 2773 return _soc_hb_mem_parity_control(unit, mem, copyno, enable); 2774 } 2775 #endif /* BCM_BRADLEY_SUPPORT */ 2776 2777 #ifdef BCM_HERCULES15_SUPPORT 2778 if (SOC_IS_HERCULES15(unit)) { 2779 int copy; 2780 int port; 2781 uint32 interrupt = 0; 2782 uint32 regval; 2783 2784 /* Shut off parity interrupts during memory test */ 2785 switch (mem) { 2786 case MEM_XQm: 2787 soc_reg_field_set 2788 (unit, MMU_INTCTRLr, &interrupt, XQ_PE_ENf, 1); 2789 break; 2790 case MEM_PPm: 2791 soc_reg_field_set 2792 (unit, MMU_INTCTRLr, &interrupt, PP_DBE_ENf, 1); 2793 soc_reg_field_set 2794 (unit, MMU_INTCTRLr, &interrupt, PP_SBE_ENf, 1); 2795 break; 2796 case MEM_LLAm: 2797 soc_reg_field_set 2798 (unit, MMU_INTCTRLr, &interrupt, LLA_PE_ENf, 1); 2799 break; 2800 case MEM_INGBUFm: 2801 case MEM_MCm: 2802 case MEM_IPMCm: 2803 case MEM_UCm: 2804 case MEM_VIDm: 2805 case MEM_ING_SRCMODBLKm: 2806 case MEM_ING_MODMAPm: 2807 case MEM_EGR_MODMAPm: 2808 soc_reg_field_set 2809 (unit, MMU_INTCTRLr, &interrupt, ING_PE_ENf, 1); 2810 break; 2811 break; 2812 default: 2813 return SOC_E_NONE; /* nothing to do */ 2814 } 2815 SOC_MEM_BLOCK_ITER(unit, mem, copy) { 2816 if (copyno != COPYNO_ALL && copyno != copy) { 2817 continue; 2818 } 2819 2820 /* find the ports matching this copy/blk */ 2821 PBMP_ITER(SOC_BLOCK_BITMAP(unit, copy), port) { 2822 SOC_IF_ERROR_RETURN 2823 (READ_MMU_INTCTRLr(unit, port, ®val)); 2824 if (enable) { 2825 regval |= interrupt; 2826 } else { 2827 regval &= ~interrupt; 2828 } 2829 if (enable) { 2830 SOC_IF_ERROR_RETURN 2831 (WRITE_MMU_INTCLRr(unit, port, interrupt)); 2832 } 2833 SOC_IF_ERROR_RETURN 2834 (WRITE_MMU_INTCTRLr(unit, port, (port == 0) ? 0:regval)); 2835 SOC_IF_ERROR_RETURN(READ_MMU_CFGr(unit, port, ®val)); 2836 soc_reg_field_set(unit, MMU_CFGr, ®val, 2837 PARITY_DIAGf, enable ? 0 : 1); 2838 SOC_IF_ERROR_RETURN(WRITE_MMU_CFGr(unit, port, regval)); 2839 } 2840 } 2841 } 2842 #endif /* BCM_HERCULES15_SUPPORT */ 2843 2844 return SOC_E_NONE; 2845 } 2846 2847 /* 2848 * Clean up parity bits after memtest to avoid later parity errors 2849 */ 2850 int 2851 soc_mem_parity_clean(int unit, soc_mem_t mem, int copyno) 2852 { 2853 COMPILER_REFERENCE(unit); 2854 COMPILER_REFERENCE(mem); 2855 COMPILER_REFERENCE(copyno); 2856 /* To avoid later parity errors */ 2857 #if defined(BCM_FIREBOLT_SUPPORT) 2858 switch (mem) { 2859 case L2Xm: 2860 case L2_ENTRY_ONLYm: 2861 if (soc_feature(unit, soc_feature_l2x_parity)) { 2862 if (soc_mem_clear(unit, mem, copyno, TRUE) < 0) { 2863 return -1; 2864 } 2865 } 2866 break; 2867 2868 case L3_ENTRY_IPV4_MULTICASTm: 2869 case L3_ENTRY_IPV4_UNICASTm: 2870 case L3_ENTRY_IPV6_MULTICASTm: 2871 case L3_ENTRY_IPV6_UNICASTm: 2872 case L3_ENTRY_ONLYm: 2873 case L3_ENTRY_VALID_ONLYm: 2874 if (soc_feature(unit, soc_feature_l3x_parity)) { 2875 if (soc_mem_clear(unit, mem, copyno, TRUE) < 0) { 2876 return -1; 2877 } 2878 } 2879 break; 2880 2881 case L3_DEFIPm: 2882 case L3_DEFIP_DATA_ONLYm: 2883 if (soc_feature(unit, soc_feature_l3defip_parity)) { 2884 if (soc_mem_clear(unit, mem, copyno, TRUE) < 0) { 2885 return -1; 2886 } 2887 } 2888 break; 2889 2890 #ifdef BCM_RAPTOR_SUPPORT 2891 case DSCP_TABLEm: 2892 case EGR_L3_INTFm: 2893 case EGR_MASKm: 2894 case EGR_L3_NEXT_HOPm: 2895 case EGR_VLANm: 2896 case FP_POLICY_TABLEm: 2897 case ING_L3_NEXT_HOPm: 2898 case L2MCm: 2899 case L3_IPMCm: 2900 case VLAN_TABm: 2901 if (soc_feature(unit, soc_feature_ip_ep_mem_parity)) { 2902 if (soc_mem_clear(unit, mem, copyno, TRUE) < 0) { 2903 return -1; 2904 } 2905 } 2906 break; 2907 #endif /* BCM_RAPTOR_SUPPORT */ 2908 2909 #ifdef BCM_TRX_SUPPORT 2910 case MMU_WRED_CFG_CELLm: 2911 case MMU_WRED_THD_0_CELLm: 2912 case MMU_WRED_THD_1_CELLm: 2913 case MMU_WRED_PORT_CFG_CELLm: 2914 case MMU_WRED_PORT_THD_0_CELLm: 2915 case MMU_WRED_PORT_THD_1_CELLm: 2916 #ifdef BCM_TRIUMPH_SUPPORT 2917 case MMU_WRED_CFG_PACKETm: 2918 case MMU_WRED_THD_0_PACKETm: 2919 case MMU_WRED_THD_1_PACKETm: 2920 case MMU_WRED_PORT_CFG_PACKETm: 2921 case MMU_WRED_PORT_THD_0_PACKETm: 2922 case MMU_WRED_PORT_THD_1_PACKETm: 2923 #endif /* BCM_TRIUMPH_SUPPORT */ 2924 #ifdef BCM_ENDURO_SUPPORT 2925 case LMEPm: 2926 #endif /* BCM_ENDURO_SUPPORT */ 2927 #ifdef BCM_TRIUMPH3_SUPPORT 2928 case SVM_METER_TABLEm: 2929 case MMU_INTFO_QCN_CNM_TIMER_TBLm: 2930 case FP_METER_TABLEm: 2931 case FP_STORM_CONTROL_METERSm: 2932 #endif /* BCM_TRIUMPH3_SUPPORT */ 2933 #ifdef BCM_HURRICANE2_SUPPORT 2934 case MMU_IPMC_VLAN_TBLm: 2935 case MMU_IPMC_GROUP_TBL0m: 2936 case MMU_IPMC_GROUP_TBL1m: 2937 #endif /* BCM_SURRICANE2_SUPPORT */ 2938 if (soc_mem_clear(unit, mem, copyno, TRUE) < 0) { 2939 return -1; 2940 } 2941 break; 2942 #endif /* BCM_TRX_SUPPORT */ 2943 2944 default: 2945 break; /* Do nothing */ 2946 } 2947 #endif 2948 return SOC_E_NONE; 2949 } 2950 2951 /* Reenable parity after testing */ 2952 int 2953 soc_mem_parity_restore(int unit, soc_mem_t mem, int copyno) 2954 { 2955 /* 2956 * Some devices need memories cleared before reenabling because 2957 * of background HW processes which scan the tables and throw errors 2958 */ 2959 if (SOC_IS_TRX(unit)) { 2960 SOC_IF_ERROR_RETURN 2961 (soc_mem_parity_clean(unit, mem, copyno)); 2962 } 2963 2964 SOC_IF_ERROR_RETURN 2965 (soc_mem_parity_control(unit, mem, copyno, TRUE)); 2966 2967 /* 2968 * Other devices need memories cleared after parity is reenabled 2969 * so the HW generation of parity bits is correct. 2970 */ 2971 2972 if (!SOC_IS_TRX(unit)) { 2973 SOC_IF_ERROR_RETURN 2974 (soc_mem_parity_clean(unit, mem, copyno)); 2975 } 2976 2977 return 0; 2978 } 2979 2980 int 2981 soc_mem_cpu_write_control(int unit, soc_mem_t mem, int copyno, int enable, 2982 int *orig_enable) 2983 { 2984 #ifdef BCM_MONTEREY_SUPPORT 2985 if (SOC_IS_MONTEREY(unit)) { 2986 return _soc_monterey_mem_cpu_write_control(unit, mem, copyno, enable, 2987 orig_enable); 2988 } 2989 #endif /* BCM_MONTEREY_SUPPORT */ 2990 #ifdef BCM_APACHE_SUPPORT 2991 if (SOC_IS_APACHE(unit)) { 2992 return _soc_apache_mem_cpu_write_control(unit, mem, copyno, enable, 2993 orig_enable); 2994 } 2995 #endif /* BCM_APACHE_SUPPORT */ 2996 2997 #ifdef BCM_TRIDENT2_SUPPORT 2998 if (SOC_IS_TD2_TT2(unit)) { 2999 #ifdef BCM_TOMAHAWK3_SUPPORT 3000 if (SOC_IS_TOMAHAWK3(unit)) { 3001 return soc_tomahawk3_mem_cpu_write_control(unit, mem, copyno, enable, 3002 orig_enable); 3003 } else 3004 #endif 3005 #ifdef BCM_TRIDENT3_SUPPORT 3006 if (SOC_IS_TRIDENT3X(unit)) { 3007 return soc_trident3_mem_cpu_write_control(unit, mem, copyno, enable, 3008 orig_enable); 3009 } else 3010 #endif /* TRIDENT3_SUPPORT */ 3011 #ifdef BCM_TOMAHAWK_SUPPORT 3012 if (SOC_IS_TOMAHAWKX(unit)) { 3013 return soc_tomahawk_mem_cpu_write_control(unit, mem, copyno, enable, 3014 orig_enable); 3015 } else 3016 #endif /* BCM_TOMAHAWK_SUPPORT */ 3017 { 3018 return _soc_trident2_mem_cpu_write_control(unit, mem, copyno, enable, 3019 orig_enable); 3020 } 3021 } 3022 #endif /* BCM_TRIDENT2_SUPPORT */ 3023 3024 return SOC_E_NONE; 3025 } 3026 3027 3028 #if defined (SER_TR_TEST_SUPPORT) 3029 3030 #define _SER_TEST_MEM_SOC_FIELD_NAME(unit, field) \ 3031 ((field >= 0)? SOC_FIELD_NAME((unit), (field)) : "INVALIDf") 3032 3033 static soc_ser_test_functions_t *ser_test_functions[SOC_MAX_NUM_DEVICES]; 3034 3035 #if defined(BCM_TRIDENT_SUPPORT) 3036 #define SOC_MEM_TEST_PIPE_LOCK(unit, test_data) \ 3037 if ((test_data->pipe_select != NULL) && \ 3038 (test_data->acc_type == _SOC_ACC_TYPE_PIPE_Y)) { \ 3039 IP_ARBITER_LOCK(unit); \ 3040 (void)test_data->pipe_select(unit, TRUE, 1); \ 3041 (void)test_data->pipe_select(unit, FALSE, 1); \ 3042 } 3043 #define SOC_MEM_TEST_PIPE_UNLOCK(unit, test_data) \ 3044 if ((test_data->pipe_select != NULL) && \ 3045 (test_data->acc_type == _SOC_ACC_TYPE_PIPE_Y)) { \ 3046 (void)test_data->pipe_select(unit, TRUE, 0); \ 3047 (void)test_data->pipe_select(unit, FALSE, 0); \ 3048 IP_ARBITER_UNLOCK(unit); \ 3049 } 3050 #else 3051 #define SOC_MEM_TEST_PIPE_LOCK(unit, test_data) 3052 #define SOC_MEM_TEST_PIPE_UNLOCK(unit, test_data) 3053 #endif 3054 3055 soc_error_t 3056 soc_ser_test_enable_field_check(int unit, soc_reg_t reg, soc_mem_t mem, soc_field_t field, 3057 int fld_position, int is_mem, int *match) 3058 { 3059 uint32 entry[SOC_MAX_MEM_WORDS]; 3060 uint32 copyno; 3061 uint32 value = 0; 3062 uint32 rval32 = 0; 3063 uint64 rval64; 3064 int index = 0; 3065 int entry_count = 0; 3066 3067 if (is_mem) { 3068 if (SOC_MEM_IS_VALID(unit,mem)) { 3069 entry_count = soc_mem_index_count(unit, mem); 3070 if (entry_count > 1) { 3071 return SOC_E_PARAM; 3072 } 3073 index = SOC_MEM_INFO(unit, mem).index_min; 3074 SOC_MEM_BLOCK_ITER(unit, mem, copyno) { 3075 SOC_IF_ERROR_RETURN(soc_mem_read(unit, mem, copyno, index, entry)); 3076 value = soc_mem_field32_get(unit, mem, entry, field); 3077 if (fld_position == -1) { 3078 if (0 == value) { 3079 *match = 0; 3080 LOG_WARN(BSL_LS_SOC_SER, 3081 (BSL_META_U(unit, 3082 "parity control %s.%s is disabled !!\n"), 3083 SOC_MEM_NAME(unit, mem), 3084 SOC_FIELD_NAME(unit, field))); 3085 } else { 3086 *match = 1; 3087 } 3088 } else { 3089 if (0 == (value & (1 << fld_position))) { 3090 *match = 0; 3091 LOG_WARN(BSL_LS_SOC_SER, 3092 (BSL_META_U(unit, 3093 "parity control %s.%s[%d] is disabled !!\n"), 3094 SOC_MEM_NAME(unit, mem), 3095 SOC_FIELD_NAME(unit, field), 3096 fld_position)); 3097 } else { 3098 *match = 1; 3099 } 3100 } 3101 } 3102 } 3103 } else { 3104 if (SOC_REG_IS_VALID(unit,reg)) { 3105 if (SOC_REG_IS_64(unit,reg)) { 3106 COMPILER_64_ZERO(rval64); 3107 SOC_IF_ERROR_RETURN 3108 (soc_reg_get(unit, reg, REG_PORT_ANY, 0, &rval64)); 3109 value = soc_reg64_field32_get(unit, reg, rval64, field); 3110 } else { 3111 SOC_IF_ERROR_RETURN 3112 (soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval32)); 3113 value = soc_reg_field_get(unit, reg, rval32, field); 3114 } 3115 if (fld_position == -1) { 3116 if (0 == value) { 3117 *match = 0; 3118 LOG_WARN(BSL_LS_SOC_SER, 3119 (BSL_META_U(unit, 3120 "parity control %s.%s is disabled !!\n"), 3121 SOC_REG_NAME(unit, reg), 3122 SOC_FIELD_NAME(unit, field))); 3123 } else { 3124 *match = 1; 3125 } 3126 } else { 3127 if (0 == (value & (1 << fld_position))) { 3128 *match = 0; 3129 LOG_WARN(BSL_LS_SOC_SER, 3130 (BSL_META_U(unit, 3131 "parity control %s.%s[%d] is disabled !!\n"), 3132 SOC_REG_NAME(unit, reg), 3133 SOC_FIELD_NAME(unit, field), 3134 fld_position)); 3135 } else { 3136 *match = 1; 3137 } 3138 } 3139 } 3140 } 3141 3142 return SOC_E_NONE; 3143 } 3144 3145 soc_error_t 3146 soc_ser_test_reg_parity_control_check(int unit, _soc_reg_ser_en_info_t *info) 3147 { 3148 int i; 3149 int match = 0; 3150 int en_fld_position = -1; 3151 int ecc1b_en_fld_position = -1; 3152 soc_mem_t mem = INVALIDm; 3153 soc_mem_t ecc1b_mem = INVALIDm; 3154 soc_reg_t reg = INVALIDr; 3155 soc_reg_t ecc1b_reg = INVALIDr; 3156 soc_field_t field = INVALIDf; 3157 soc_field_t ecc1b_field = INVALIDf; 3158 uint8 flag = 0; 3159 uint8 ecc1b_flag = 0; 3160 uint32 total_count = 0; 3161 uint32 pass_count = 0; 3162 int rv = SOC_E_NONE; 3163 3164 for (i = 0; ; i++) { 3165 if (info[i].reg == INVALIDr) { 3166 break; 3167 } 3168 flag = info[i].en_ctrl.flag_reg_mem; 3169 if (flag) { 3170 mem = info[i].en_ctrl.ctrl_type.en_mem; 3171 reg = INVALIDr; 3172 } else { 3173 reg = info[i].en_ctrl.ctrl_type.en_reg; 3174 mem = INVALIDm; 3175 } 3176 field = info[i].en_ctrl.en_fld; 3177 en_fld_position = info[i].en_ctrl.en_fld_position; 3178 ecc1b_flag = info[i].ecc1b_ctrl.flag_reg_mem; 3179 if (ecc1b_flag) { 3180 ecc1b_mem = info[i].ecc1b_ctrl.ctrl_type.en_mem; 3181 ecc1b_reg = INVALIDr; 3182 } else { 3183 ecc1b_reg = info[i].ecc1b_ctrl.ctrl_type.en_reg; 3184 ecc1b_mem = INVALIDm; 3185 } 3186 ecc1b_field = info[i].ecc1b_ctrl.en_fld; 3187 ecc1b_en_fld_position = info[i].ecc1b_ctrl.en_fld_position; 3188 3189 rv = soc_ser_test_enable_field_check(unit, reg, mem, field, en_fld_position, 3190 flag, &match); 3191 if (rv != SOC_E_NONE) { 3192 if ((rv == SOC_E_PARAM) && (mem != INVALIDm)) { 3193 LOG_ERROR(BSL_LS_SOC_SER, 3194 (BSL_META_U(unit, 3195 "parity control memory(%s) is not support !!\n"), 3196 SOC_MEM_NAME(unit, mem))); 3197 } else { 3198 LOG_ERROR(BSL_LS_SOC_SER, 3199 (BSL_META_U(unit, 3200 "Get parity control data failed !!\n"))); 3201 } 3202 } 3203 total_count++; 3204 if (match) { 3205 pass_count++; 3206 } 3207 rv = soc_ser_test_enable_field_check(unit, ecc1b_reg, ecc1b_mem, ecc1b_field, 3208 ecc1b_en_fld_position, ecc1b_flag, &match); 3209 total_count++; 3210 if (match) { 3211 pass_count++; 3212 } 3213 if (rv != SOC_E_NONE) { 3214 if ((rv == SOC_E_PARAM) && (ecc1b_mem != INVALIDm)) { 3215 LOG_ERROR(BSL_LS_SOC_SER, 3216 (BSL_META_U(unit, 3217 "parity control memory(%s) is not support !!\n"), 3218 SOC_MEM_NAME(unit, ecc1b_mem))); 3219 } else { 3220 LOG_ERROR(BSL_LS_SOC_SER, 3221 (BSL_META_U(unit, 3222 "Get parity control data failed !!\n"))); 3223 } 3224 } 3225 } 3226 3227 LOG_CLI((BSL_META_U(unit, "\nRegisters parity control checked on unit %d: %d\n"), 3228 unit, total_count)); 3229 LOG_CLI((BSL_META_U(unit, "Passed fields:\t%d\n"), pass_count)); 3230 LOG_CLI((BSL_META_U(unit, "Failed fields::\t%d\n\n"), (total_count - pass_count))); 3231 3232 return SOC_E_NONE; 3233 } 3234 3235 soc_error_t 3236 soc_ser_test_mem_parity_control_check(int unit, _soc_mem_ser_en_info_t *info) 3237 { 3238 int i; 3239 int match = 0; 3240 int en_fld_position = -1; 3241 int ecc1b_en_fld_position = -1; 3242 soc_mem_t mem = INVALIDm; 3243 soc_mem_t ecc1b_mem = INVALIDm; 3244 soc_reg_t reg = INVALIDr; 3245 soc_reg_t ecc1b_reg = INVALIDr; 3246 soc_field_t field = INVALIDf; 3247 soc_field_t ecc1b_field = INVALIDf; 3248 uint8 flag = 0; 3249 uint8 ecc1b_flag = 0; 3250 uint32 check_ecc1b = 1; 3251 uint32 total_count = 0; 3252 uint32 pass_count = 0; 3253 int rv = SOC_E_NONE; 3254 3255 for (i = 0; ; i++) { 3256 if (info[i].mem == INVALIDm) { 3257 break; 3258 } 3259 flag = info[i].en_ctrl.flag_reg_mem; 3260 if (flag) { 3261 mem = info[i].en_ctrl.ctrl_type.en_mem; 3262 reg = INVALIDr; 3263 } else { 3264 reg = info[i].en_ctrl.ctrl_type.en_reg; 3265 mem = INVALIDm; 3266 } 3267 field = info[i].en_ctrl.en_fld; 3268 en_fld_position = info[i].en_ctrl.en_fld_position; 3269 ecc1b_flag = info[i].ecc1b_ctrl.flag_reg_mem; 3270 if (ecc1b_flag) { 3271 ecc1b_mem = info[i].ecc1b_ctrl.ctrl_type.en_mem; 3272 ecc1b_reg = INVALIDr; 3273 } else { 3274 ecc1b_reg = info[i].ecc1b_ctrl.ctrl_type.en_reg; 3275 ecc1b_mem = INVALIDm; 3276 } 3277 ecc1b_field = info[i].ecc1b_ctrl.en_fld; 3278 ecc1b_en_fld_position = info[i].ecc1b_ctrl.en_fld_position; 3279 3280 if(!SOC_MEM_SER_CORRECTION_TYPE(unit, info[i].mem)) { 3281 check_ecc1b = 0; 3282 } else { 3283 check_ecc1b = 1; 3284 } 3285 3286 rv = soc_ser_test_enable_field_check(unit, reg, mem, field, en_fld_position, 3287 flag, &match); 3288 total_count++; 3289 if (match) { 3290 pass_count++; 3291 } 3292 if (rv != SOC_E_NONE) { 3293 if ((rv == SOC_E_PARAM) && (mem != INVALIDm)) { 3294 LOG_ERROR(BSL_LS_SOC_SER, 3295 (BSL_META_U(unit, 3296 "parity control memory(%s) is not support !!\n"), 3297 SOC_MEM_NAME(unit, mem))); 3298 } else { 3299 LOG_ERROR(BSL_LS_SOC_SER, 3300 (BSL_META_U(unit, 3301 "Get parity control data failed !!\n"))); 3302 } 3303 } 3304 if (check_ecc1b) { 3305 rv = soc_ser_test_enable_field_check(unit, ecc1b_reg, ecc1b_mem, ecc1b_field, 3306 ecc1b_en_fld_position, ecc1b_flag, &match); 3307 total_count++; 3308 if (match) { 3309 pass_count++; 3310 } 3311 if (rv != SOC_E_NONE) { 3312 if ((rv == SOC_E_PARAM) && (ecc1b_mem != INVALIDm)) { 3313 LOG_ERROR(BSL_LS_SOC_SER, 3314 (BSL_META_U(unit, 3315 "parity control memory(%s) is not support !!\n"), 3316 SOC_MEM_NAME(unit, ecc1b_mem))); 3317 } else { 3318 LOG_ERROR(BSL_LS_SOC_SER, 3319 (BSL_META_U(unit, 3320 "Get parity control data failed !!\n"))); 3321 } 3322 } 3323 } 3324 } 3325 LOG_CLI((BSL_META_U(unit, "\nMemories parity control checked on unit %d: %d\n"), 3326 unit, total_count)); 3327 LOG_CLI((BSL_META_U(unit, "Passed fields:\t%d\n"), pass_count)); 3328 LOG_CLI((BSL_META_U(unit, "Failed fields::\t%d\n\n"), (total_count - pass_count))); 3329 3330 return SOC_E_NONE; 3331 } 3332 3333 soc_error_t 3334 soc_ser_test_bus_parity_control_check(int unit, _soc_bus_ser_en_info_t *info) 3335 { 3336 int i; 3337 int match = 0; 3338 soc_reg_t reg = INVALIDr; 3339 soc_field_t field = INVALIDf; 3340 uint32 total_count = 0; 3341 uint32 pass_count = 0; 3342 int rv = SOC_E_NONE; 3343 3344 for (i = 0; ; i++) { 3345 if (info[i].en_reg == INVALIDr) { 3346 break; 3347 } 3348 reg = info[i].en_reg; 3349 field = info[i].en_fld; 3350 3351 rv = soc_ser_test_enable_field_check(unit, reg, INVALIDm, field, -1, 0, &match); 3352 total_count++; 3353 if (match) { 3354 pass_count++; 3355 } 3356 if (rv != SOC_E_NONE) { 3357 LOG_ERROR(BSL_LS_SOC_SER, 3358 (BSL_META_U(unit, 3359 "Get parity control data failed !!\n"))); 3360 } 3361 } 3362 LOG_CLI((BSL_META_U(unit, "\nBus parity control checked on unit %d: %d\n"), 3363 unit, total_count)); 3364 LOG_CLI((BSL_META_U(unit, "Passed fields:\t%d\n"), pass_count)); 3365 LOG_CLI((BSL_META_U(unit, "Failed fields::\t%d\n\n"), (total_count - pass_count))); 3366 3367 return SOC_E_NONE; 3368 } 3369 3370 soc_error_t 3371 soc_ser_test_buf_parity_control_check(int unit, _soc_buffer_ser_en_info_t *info) 3372 { 3373 int i; 3374 int match = 0; 3375 soc_reg_t reg = INVALIDr; 3376 soc_field_t field = INVALIDf; 3377 uint32 total_count = 0; 3378 uint32 pass_count = 0; 3379 int rv = SOC_E_NONE; 3380 3381 for (i = 0; ; i++) { 3382 if (info[i].en_reg == INVALIDr) { 3383 break; 3384 } 3385 reg = info[i].en_reg; 3386 field = info[i].en_fld; 3387 3388 rv = soc_ser_test_enable_field_check(unit, reg, INVALIDm, field, -1, 0, &match); 3389 total_count++; 3390 if (match) { 3391 pass_count++; 3392 } 3393 if (rv != SOC_E_NONE) { 3394 LOG_ERROR(BSL_LS_SOC_SER, 3395 (BSL_META_U(unit, 3396 "Get parity control data failed !!\n"))); 3397 } 3398 } 3399 LOG_CLI((BSL_META_U(unit, "\nBuffer parity control checked on unit %d: %d\n"), 3400 unit, total_count)); 3401 LOG_CLI((BSL_META_U(unit, "Passed fields:\t%d\n"), pass_count)); 3402 LOG_CLI((BSL_META_U(unit, "Failed fields::\t%d\n\n"), (total_count - pass_count))); 3403 3404 return SOC_E_NONE; 3405 } 3406 3407 soc_error_t 3408 soc_ser_test_parity_control_check(int unit, int type, void *info) 3409 { 3410 switch(type) { 3411 case _SOC_SER_TYPE_REG: 3412 soc_ser_test_reg_parity_control_check(unit, (_soc_reg_ser_en_info_t *)info); 3413 break; 3414 case _SOC_SER_TYPE_MEM: 3415 soc_ser_test_mem_parity_control_check(unit, (_soc_mem_ser_en_info_t *)info); 3416 break; 3417 case _SOC_SER_TYPE_BUS: 3418 soc_ser_test_bus_parity_control_check(unit, (_soc_bus_ser_en_info_t *)info); 3419 break; 3420 case _SOC_SER_TYPE_BUF: 3421 soc_ser_test_buf_parity_control_check(unit, (_soc_buffer_ser_en_info_t *)info); 3422 break; 3423 default: 3424 break; 3425 } 3426 3427 return SOC_E_NONE; 3428 } 3429 3430 /* 3431 * Function: 3432 * ser_test_mem_write 3433 * Purpose: 3434 * A small helper function for ser_test_mem, combining common operations required to write 3435 * Parameters: 3436 * unit - (IN) Device Number 3437 * test_data - (IN) contains the current state of the test. 3438 * Returns: 3439 * An error if one is generated by the soc_mem_write, otherwise SOC_E_NONE 3440 */ 3441 soc_error_t 3442 ser_test_mem_write(int unit, uint32 flags, ser_test_data_t *test_data) 3443 { 3444 soc_error_t rv = SOC_E_NONE; 3445 uint32 write_flags = SOC_MEM_NO_FLAGS; 3446 soc_mem_field_set(unit, test_data->mem, test_data->entry_buf, 3447 test_data->test_field, test_data->field_buf); 3448 SOC_MEM_TEST_PIPE_LOCK(unit, test_data); 3449 if (flags & SOC_INJECT_ERROR_DONT_MAP_INDEX) { 3450 write_flags = SOC_MEM_DONT_MAP_INDEX; 3451 } 3452 if (test_data->acc_type != _SOC_ACC_TYPE_PIPE_ANY && 3453 test_data->acc_type != _SOC_ACC_TYPE_PIPE_ALL) { 3454 rv = soc_mem_pipe_select_write(unit, write_flags, 3455 test_data->mem, test_data->mem_block, test_data->acc_type, 3456 test_data->index, test_data->entry_buf); 3457 } else { 3458 rv = soc_mem_write_extended(unit, write_flags, test_data->mem, 3459 test_data->mem_block, test_data->index, 3460 test_data->entry_buf); 3461 } 3462 SOC_MEM_TEST_PIPE_UNLOCK(unit, test_data); 3463 if (SOC_FAILURE(rv)) { 3464 LOG_ERROR(BSL_LS_SOC_SER, 3465 (BSL_META_U(unit, 3466 "unit %d %s entry %d mem write error\n"), 3467 unit, test_data->mem_name, test_data->index)); 3468 } 3469 return rv; 3470 } 3471 3472 3473 /* 3474 * Function: 3475 * ser_test_mem_read 3476 * Purpose: 3477 * A small helper function for ser_test_mem, combining common operations required to read 3478 * Parameters: 3479 * unit - (IN) Device Number 3480 * read_func_view 3481 * - (IN) 0 - read test_data->mem //error injection view 3482 * 1 - read test_data->mem_fv //func view to induce err 3483 * test_data - (IN & OUT) contains the current state of the test. 3484 * The members entry_buf and field_buf will be modified by this function 3485 * Returns: 3486 * An error if one is generated by the soc_mem_read, otherwise SOC_E_NONE 3487 */ 3488 soc_error_t 3489 ser_test_mem_read(int unit, uint32 read_flags, ser_test_data_t *test_data) 3490 { 3491 soc_error_t rv = SOC_E_NONE; 3492 soc_mem_t mem; 3493 int index; 3494 int use_pipe_select_read = 0; 3495 uint32 read_func_view = read_flags & SER_TEST_MEM_F_READ_FUNC_VIEW; 3496 uint32 flags = SOC_MEM_NO_FLAGS; 3497 #ifdef INCLUDE_TCL 3498 /* If TCL is defined, the cache coherency flag will cause parity information 3499 to be DISCARDED on read. Turning this off here */ 3500 int coherency_check = SOC_MEM_CACHE_COHERENCY_CHECK(unit); 3501 SOC_MEM_CACHE_COHERENCY_CHECK_SET(unit, FALSE); 3502 #endif 3503 3504 if (read_func_view) { 3505 mem = test_data->mem_fv; 3506 index = test_data->index_fv; 3507 } else { 3508 mem = test_data->mem; 3509 index = test_data->index; 3510 } 3511 3512 if (soc_feature(unit, soc_feature_unique_acc_type_access)) { 3513 if ((test_data->acc_type >= 0) && 3514 (test_data->acc_type < NUM_PIPE(unit))) { 3515 use_pipe_select_read = 1; 3516 } 3517 } else if (test_data->acc_type == _SOC_ACC_TYPE_PIPE_Y) { 3518 use_pipe_select_read = 1; 3519 } 3520 if (read_flags & SER_TEST_MEM_F_DONT_MAP_INDEX) { 3521 flags = SOC_MEM_DONT_MAP_INDEX; 3522 } 3523 SOC_MEM_TEST_PIPE_LOCK(unit, test_data); 3524 if (use_pipe_select_read) { 3525 rv = soc_mem_pipe_select_read(unit, flags, mem, 3526 test_data->mem_block, 3527 test_data->acc_type, index, 3528 test_data->entry_buf); 3529 } else { 3530 /*Enable NACK on read */ 3531 flags |= SOC_MEM_SCHAN_ERR_RETURN | SOC_MEM_DONT_USE_CACHE; 3532 rv = soc_mem_read_extended(unit, flags, 3533 mem, 0, test_data->mem_block, 3534 index, test_data->entry_buf); 3535 } 3536 SOC_MEM_TEST_PIPE_UNLOCK(unit, test_data); 3537 #ifdef INCLUDE_TCL 3538 SOC_MEM_CACHE_COHERENCY_CHECK_SET(unit, coherency_check); 3539 #endif 3540 if (SOC_FAILURE(rv)) { 3541 LOG_VERBOSE(BSL_LS_SOC_SER, 3542 (BSL_META_U(unit, 3543 "unit %d NACK received for %s entry %d:\n\t"), 3544 unit, SOC_MEM_NAME(unit, mem), index)); 3545 } 3546 3547 /* For case: 3548 * (read_func_view && (inject_view != func_view) 3549 * we MUST NOT update test_data->field_buf because 3550 * test_data->test_field may be ECCf, ECC_0f, etc which is NOT 3551 * valid for func_view. 3552 */ 3553 if (!read_func_view || (test_data->mem == test_data->mem_fv)) { 3554 soc_mem_field_get(unit, mem, test_data->entry_buf, 3555 test_data->test_field, test_data->field_buf); 3556 } 3557 return rv; 3558 } 3559 3560 3561 soc_error_t 3562 soc_ser_test_inject_full(int unit, uint32 flags, ser_test_data_t *test_data) 3563 { 3564 soc_field_t key_field, mask_field; 3565 uint32 write_flags = flags & SOC_INJECT_ERROR_DONT_MAP_INDEX; 3566 3567 if ((flags & SOC_INJECT_ERROR_TCAM_FLAG) && test_data->tcam_parity_bit >= 0) { 3568 if (SOC_MEM_FIELD_VALID(unit, test_data->mem, KEYf)){ 3569 key_field = KEYf; 3570 mask_field = MASKf; 3571 } else if (SOC_MEM_FIELD_VALID(unit, test_data->mem, KEY0f)){ 3572 key_field = KEY0f; 3573 mask_field = MASK0f; 3574 } else if (SOC_MEM_FIELD_VALID(unit, test_data->mem, KEY1f)){ 3575 key_field = KEY1f; 3576 mask_field = MASK1f; 3577 } else { 3578 return SOC_E_FAIL; 3579 } 3580 test_data->test_field = key_field; 3581 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, test_data)); 3582 SOC_IF_ERROR_RETURN(soc_ser_test_inject_error(unit, test_data, 0)); 3583 test_data->test_field = mask_field; 3584 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, test_data)); 3585 if (test_data->field_buf[0] == 0) { 3586 return soc_ser_test_inject_error(unit, test_data, 0); 3587 } else { 3588 return SOC_E_NONE; 3589 } 3590 3591 } else if (flags & SOC_INJECT_ERROR_2BIT_ECC){ 3592 return soc_ser_test_inject_error(unit, test_data, 3593 write_flags | SOC_INJECT_ERROR_2BIT_ECC); 3594 } else { 3595 return soc_ser_test_inject_error(unit, test_data, write_flags); 3596 } 3597 } 3598 3599 soc_error_t 3600 soc_ser_test_inject_error(int unit, ser_test_data_t *test_data, uint32 flags) 3601 { 3602 3603 if((test_data->field_buf[0] & 1) == 1) { 3604 test_data->field_buf[0] &= 0xFFFFFFFE; 3605 } else { 3606 test_data->field_buf[0] |= 0x00000001; 3607 } 3608 3609 if (flags & SOC_INJECT_ERROR_2BIT_ECC) { 3610 if((test_data->field_buf[0] & 2) == 2) { 3611 test_data->field_buf[0] &= 0xFFFFFFFD; 3612 } else { 3613 test_data->field_buf[0] |= 0x00000002; 3614 } 3615 } 3616 3617 test_data->badData = test_data->field_buf[0]; 3618 /*Disable writing to cache for fudged data.*/ 3619 SOC_MEM_TEST_SKIP_CACHE_SET(unit, TRUE); 3620 SOC_IF_ERROR_RETURN(ser_test_mem_write(unit, flags, test_data)); 3621 SOC_MEM_TEST_SKIP_CACHE_SET(unit, FALSE); 3622 return SOC_E_NONE; 3623 } 3624 3625 /* 3626 * Function: 3627 * ser_test_mem 3628 * Purpose: 3629 * Serform a Software Error Recovery test on passed memory mem. 3630 * Parameters: 3631 * unit - (IN) Device Number 3632 * parity_enable_reg - (IN) Register which turns on and off memory protection 3633 * tcam_parity_bit - (IN) Bit in the parity_enable_reg field for TCAM parity for this memory. 3634 * This must be -1 if this memory is not protected by the TCAM 3635 * hw_parity_field - (IN) If controlled by H/W, this is the field in the enable register that 3636 * coorisponds to this memory. 3637 * mem - (IN) The memory on which to test SER 3638 * test_type - (IN) Used to determine how many indexes to test for each memory table. 3639 * mem_block - (IN) The block for this memory. MEM_BLOCK_ANY is fine for TCAM mems 3640 * port - (IN) The port for this memory/control reg. REG_PORT_ANY is fine for TCAMS 3641 * error_count - (OUT)Increments if a test on any of the indexes in this memory fail. 3642 * Returns: 3643 * The number of failed tests (This can be more than one per memory if test_type is anything 3644 * other than SER_SINGLE_INDEX.) 3645 */ 3646 3647 3648 soc_error_t 3649 ser_test_mem_pipe(int unit, soc_reg_t parity_enable_reg, int tcam_parity_bit, 3650 soc_field_t hw_parity_field, soc_mem_t mem, soc_field_t test_field, 3651 _soc_ser_test_t test_type, soc_block_t mem_block, 3652 soc_port_t port, soc_acc_type_t acc_type, int *error_count) 3653 { 3654 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_REG_FIELD_WORDS]; 3655 ser_test_data_t test_data; 3656 soc_ser_create_test_data(unit, tmp_entry, field_data, parity_enable_reg, 3657 tcam_parity_bit, hw_parity_field, mem, test_field, 3658 mem_block, port, acc_type, 0, &test_data); 3659 return ser_test_mem(unit, 0, &test_data, test_type, error_count); 3660 } 3661 3662 int 3663 ser_test_mem_index_remap(int unit, ser_test_data_t *test_data, int *mem_ecc) 3664 { 3665 int remap_status = 0; 3666 int mem_has_ecc = 0; 3667 3668 test_data->mem = test_data->mem_fv; 3669 test_data->index = test_data->index_fv; 3670 3671 #if defined(BCM_TOMAHAWK_SUPPORT) 3672 if (SOC_IS_TOMAHAWKX(unit)) { 3673 remap_status = ser_test_th_mem_index_remap(unit, test_data, 3674 &mem_has_ecc); 3675 } 3676 #endif /* BCM_TOMAHAWK_SUPPORT */ 3677 #if defined(BCM_TRIDENT3_SUPPORT) 3678 if (SOC_IS_TRIDENT3X(unit)) { 3679 remap_status = ser_test_td3_mem_index_remap(unit, test_data, 3680 &mem_has_ecc); 3681 } 3682 #endif /* BCM_TOMAHAWK_SUPPORT */ 3683 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 3684 if (SOC_IS_TD2P_TT2P(unit)) { 3685 /* If apache gets any diff, it will have own fn */ 3686 remap_status = ser_test_trident2p_mem_index_remap(unit, test_data, 3687 &mem_has_ecc); 3688 } 3689 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 3690 3691 #if defined(BCM_MONTEREY_SUPPORT) 3692 if (SOC_IS_MONTEREY(unit)) { 3693 remap_status = ser_test_monterey_mem_index_remap(unit, test_data, 3694 &mem_has_ecc); 3695 } 3696 #endif 3697 #if defined(BCM_APACHE_SUPPORT) 3698 if (SOC_IS_APACHE(unit) && !SOC_IS_MONTEREY(unit)) { 3699 remap_status = ser_test_apache_mem_index_remap(unit, test_data, 3700 &mem_has_ecc); 3701 } 3702 #endif /* BCM_APACHE_SUPPORT */ 3703 #if defined(BCM_HURRICANE3_SUPPORT) 3704 if (SOC_IS_HURRICANE3(unit)) { 3705 remap_status = ser_test_hr3_mem_index_remap(unit, test_data, &mem_has_ecc); 3706 } 3707 #endif /* BCM_HURRICANE3_SUPPORT */ 3708 #if defined(BCM_GREYHOUND2_SUPPORT) 3709 if (SOC_IS_GREYHOUND2(unit)) { 3710 remap_status = ser_test_greyhound2_mem_index_remap(unit, test_data, 3711 &mem_has_ecc); 3712 } 3713 #endif /* BCM_GREYHOUND2_SUPPORT */ 3714 if (remap_status < 0) { 3715 LOG_ERROR(BSL_LS_SOC_SER, 3716 (BSL_META_U(unit, 3717 "ser_test_mem_index_remap: " 3718 "FAILED for mem %s index %d\n"), 3719 SOC_MEM_NAME(unit, test_data->mem_fv), 3720 test_data->index_fv)); 3721 } 3722 *mem_ecc = mem_has_ecc; 3723 return remap_status; 3724 } 3725 3726 /* 3727 * Function: 3728 * soc_ser_create_test_data 3729 * Purpose: 3730 * Populates and performs data verification on a ser_test_data_t structure. This was 3731 * broken out into a separate function to avoid performing this work an excessive number 3732 * of times. 3733 * Parameters: 3734 * unit - (IN) Device Number 3735 * tmp_entry - (IN) A pointer to a uint32 array of size SOC_MEM_MAX_WORDS 3736 * fieldData - (IN) A pointer to a uint 32 array of size [SOC_MAX_REG_FIELD_WORDS] 3737 * parity_enable_reg - (IN) Register which turns on and off memory protection 3738 * tcam_parity_bit - (IN) Bit in the parity_enable_reg field for TCAM parity 3739 for this memory. This must be INVALID_TCAM_PARITY_BIT if 3740 this memory is not a TCAM protected memory. 3741 * hw_parity_field - (IN) If controlled by H/W, this is the field in the enable 3742 register that coorisponds to this memory. 3743 * mem - (IN) The memory ID on which to test SER 3744 * mem_block - (IN) The block for this memory. 3745 MEM_BLOCK_ANY is fine for TCAM mems 3746 * port - (IN) The port for this memory/control reg. 3747 REG_PORT_ANY is fine for TCAMS 3748 * acc_type - (IN) Access type for this memory. 3749 * index - (IN) The entry index on which to test SER 3750 * test_data - (OUT)A pointer to a data structure cotaining SER test info. 3751 * Returns: 3752 * SOC_E_NONE if the test passes, and error if it does 3753 */ 3754 void 3755 soc_ser_create_test_data(int unit, uint32 *tmp_entry, uint32 *field_data, 3756 soc_reg_t parity_enable_reg, int tcam_parity_bit, 3757 soc_field_t hw_parity_field, soc_mem_t mem, 3758 soc_field_t test_field, soc_block_t mem_block, 3759 soc_port_t port, soc_acc_type_t acc_type, 3760 int index, ser_test_data_t *test_data) 3761 { 3762 uint16 field_num = 0; 3763 static soc_field_t field_names[] = { 3764 ECCf, 3765 ECC_0f, 3766 EVEN_PARITYf, 3767 PARITYf, 3768 EVEN_PARITY_0f, 3769 EVEN_PARITY_LOWERf, 3770 PARITY_0f, 3771 ECCPf, 3772 EVEN_EGR_VLAN_STG_PARITY_P0f, 3773 LWR_ECC0f, 3774 DATAf, 3775 DATA_0f, 3776 INVALIDf 3777 }; 3778 int i, found = 0, field_length = 1; 3779 size_t len; 3780 int mem_has_ecc = 0; 3781 3782 test_data->mem_fv = mem; 3783 test_data->index_fv = index; 3784 /* compute test_data->mem, test_data->index */ 3785 (void)ser_test_mem_index_remap(unit, test_data, &mem_has_ecc); 3786 test_data->parity_enable_reg = parity_enable_reg; 3787 test_data->parity_enable_field = hw_parity_field; 3788 test_data->tcam_parity_bit = tcam_parity_bit; 3789 test_data->mem_block = mem_block; 3790 test_data->port = port; 3791 test_data->mem_info = &SOC_MEM_INFO(unit, test_data->mem); 3792 test_data->test_field = test_field; 3793 3794 /* An INVALIDf, 0 passed in for test_field implies we should select 3795 * any valid field. */ 3796 if ((test_field == INVALIDf) || (test_field == 0) || 3797 !SOC_MEM_FIELD_VALID(unit, test_data->mem, test_field) 3798 ) { 3799 /* select from preferred list */ 3800 for (i = 0; (field_names[i] != INVALIDf); i++) { 3801 if (SOC_MEM_FIELD_VALID(unit, test_data->mem, field_names[i])) { 3802 test_data->test_field = field_names[i]; 3803 found = 1; 3804 break; 3805 } 3806 } 3807 /* select first multi-bit field or last 1-bit field */ 3808 if (!found && (test_data->mem_info != NULL)) { 3809 field_num = test_data->mem_info->nFields; 3810 for (i = 0; i < field_num; i++) { 3811 test_data->test_field = test_data->mem_info->fields[i].field; 3812 field_length = soc_mem_field_length(unit, test_data->mem, 3813 test_data->test_field); 3814 if (field_length > 1) { 3815 found = 1; 3816 break; 3817 } 3818 } 3819 } 3820 } 3821 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 3822 "unit %d, soc_ser_create_test_data: error_inject_view: mem %s, test_field %s\n"), 3823 unit, SOC_MEM_NAME(unit, test_data->mem), 3824 _SER_TEST_MEM_SOC_FIELD_NAME(unit, test_data->test_field))); 3825 3826 test_data->acc_type = acc_type; 3827 test_data->entry_buf = tmp_entry; 3828 test_data->field_buf = field_data; 3829 #ifdef SOC_MEM_NAME 3830 /* coverity[secure_coding] */ 3831 len = sal_strlen(SOC_MEM_NAME(unit, test_data->mem)); 3832 if(sizeof(test_data->mem_name)- 1 < len) 3833 len = sizeof(test_data->mem_name)- 1; 3834 sal_strncpy(test_data->mem_name, SOC_MEM_NAME(unit, test_data->mem), len); 3835 test_data->mem_name[len] = 0; 3836 /* coverity[secure_coding] */ 3837 len = sal_strlen(_SER_TEST_MEM_SOC_FIELD_NAME(unit, test_data->test_field)); 3838 if(sizeof(test_data->field_name)- 1 < len) 3839 len = sizeof(test_data->field_name)- 1; 3840 sal_strncpy(test_data->field_name, 3841 _SER_TEST_MEM_SOC_FIELD_NAME(unit, test_data->test_field), len); 3842 test_data->field_name[len] = 0; 3843 #else 3844 sprintf(test_data->mem_name, "Mem ID: %d", test_data->mem); 3845 sprintf(test_data->field_name, "Field ID: %d", test_data->test_field); 3846 #endif 3847 test_data->badData = 0; 3848 #ifdef BCM_TRIDENT_SUPPORT 3849 test_data->pipe_select = NULL; 3850 if (SOC_IS_TRIDENT(unit) || SOC_IS_TITAN(unit)) { 3851 test_data->pipe_select = soc_trident_pipe_select; 3852 } 3853 #ifdef BCM_TRIDENT2_SUPPORT 3854 else if ((SOC_IS_TRIDENT2X(unit) || SOC_IS_TITAN2X(unit)) && \ 3855 (!SOC_IS_APACHE(unit))) { 3856 test_data->pipe_select = soc_trident2_pipe_select; 3857 } 3858 #endif 3859 #endif 3860 } 3861 3862 /* 3863 * Function: 3864 * soc_ser_create_test_data_with_new_format 3865 * Purpose: 3866 * Populates and performs data verification on a ser_test_data_t structure. This was 3867 * broken out into a separate function to avoid performing this work an excessive number 3868 * of times. 3869 * Parameters: 3870 * unit - (IN) Device Number 3871 * tmp_entry - (IN) A pointer to a uint32 array of size SOC_MEM_MAX_WORDS 3872 * fieldData - (IN) A pointer to a uint 32 array of size [SOC_MAX_REG_FIELD_WORDS] 3873 * parity_enable_reg - (IN) Register which turns on and off memory protection 3874 * parity_enable_mem - (IN) Memory which truns on and off memory protection 3875 * tcam_parity_bit - (IN) Bit in the parity_enable_reg field for TCAM parity 3876 for this memory. This must be INVALID_TCAM_PARITY_BIT if 3877 this memory is not a TCAM protected memory. 3878 * hw_parity_field - (IN) If controlled by H/W, this is the field in the enable 3879 register that coorisponds to this memory. 3880 * parity_field_position - (IN) Bit in hw_parity_field for memory protection 3881 * mem - (IN) The memory ID on which to test SER 3882 * mem_block - (IN) The block for this memory. 3883 MEM_BLOCK_ANY is fine for TCAM mems 3884 * port - (IN) The port for this memory/control reg. 3885 REG_PORT_ANY is fine for TCAMS 3886 * acc_type - (IN) Access type for this memory. 3887 * index - (IN) The entry index on which to test SER 3888 * test_data - (OUT)A pointer to a data structure cotaining SER test info. 3889 * Returns: 3890 * SOC_E_NONE if the test passes, and error if it does 3891 */ 3892 void 3893 soc_ser_create_test_data_with_new_format(int unit, uint32 *tmp_entry, uint32 *field_data, 3894 soc_reg_t parity_enable_reg, soc_mem_t parity_enable_mem, 3895 int tcam_parity_bit, soc_field_t hw_parity_field, 3896 int parity_field_position, soc_mem_t mem, 3897 soc_field_t test_field, soc_block_t mem_block, 3898 soc_port_t port, soc_acc_type_t acc_type, 3899 int index, ser_test_data_t *test_data) 3900 { 3901 uint16 field_num = 0; 3902 static soc_field_t field_names[] = { 3903 ECCf, 3904 ECC_0f, 3905 ECC0f, 3906 LWR_ECC0f, 3907 DATAf, 3908 DATA_0f, 3909 EVEN_PARITYf, 3910 PARITYf, 3911 EVEN_PARITY_0f, 3912 EVEN_PARITY_LOWERf, 3913 PARITY_0f, 3914 EVEN_EGR_VLAN_STG_PARITY_P0f, 3915 INVALIDf 3916 }; 3917 int i, found = 0, field_length = 1; 3918 size_t len; 3919 int mem_has_ecc = 0; 3920 3921 test_data->mem_fv = mem; 3922 test_data->index_fv = index; 3923 /* compute test_data->mem, test_data->index */ 3924 (void)ser_test_mem_index_remap(unit, test_data, &mem_has_ecc); 3925 test_data->parity_enable_reg = parity_enable_reg; 3926 test_data->parity_enable_mem = parity_enable_mem; 3927 test_data->parity_enable_field = hw_parity_field; 3928 test_data->parity_enable_field_position = parity_field_position; 3929 test_data->tcam_parity_bit = tcam_parity_bit; 3930 test_data->mem_block = mem_block; 3931 test_data->port = port; 3932 test_data->mem_info = &SOC_MEM_INFO(unit, test_data->mem); 3933 test_data->test_field = test_field; 3934 3935 /* An INVALIDf, 0 passed in for test_field implies we should select 3936 * any valid field. */ 3937 if ((test_field == INVALIDf) || (test_field == 0) || 3938 !SOC_MEM_FIELD_VALID(unit, test_data->mem, test_field)) { 3939 /* select from preferred list */ 3940 for (i = 0; (field_names[i] != INVALIDf); i++) { 3941 if (SOC_MEM_FIELD_VALID(unit, test_data->mem, field_names[i])) { 3942 test_data->test_field = field_names[i]; 3943 found = 1; 3944 break; 3945 } 3946 } 3947 /* select first multi-bit field or last 1-bit field */ 3948 if (!found && (test_data->mem_info != NULL)) { 3949 field_num = test_data->mem_info->nFields; 3950 for (i = 0; i < field_num; i++) { 3951 test_data->test_field = test_data->mem_info->fields[i].field; 3952 field_length = soc_mem_field_length(unit, test_data->mem, 3953 test_data->test_field); 3954 if (field_length > 1) { 3955 found = 1; 3956 break; 3957 } 3958 } 3959 } 3960 } 3961 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 3962 "unit %d, soc_ser_create_test_data: error_inject_view: mem %s, test_field %s\n"), 3963 unit, SOC_MEM_NAME(unit, test_data->mem), 3964 _SER_TEST_MEM_SOC_FIELD_NAME(unit, test_data->test_field))); 3965 3966 test_data->acc_type = acc_type; 3967 test_data->entry_buf = tmp_entry; 3968 test_data->field_buf = field_data; 3969 #ifdef SOC_MEM_NAME 3970 /* coverity[secure_coding] */ 3971 len = sal_strlen(SOC_MEM_NAME(unit, test_data->mem)); 3972 if(sizeof(test_data->mem_name)- 1 < len) { 3973 len = sizeof(test_data->mem_name)- 1; 3974 } 3975 sal_strncpy(test_data->mem_name, SOC_MEM_NAME(unit, test_data->mem), len); 3976 test_data->mem_name[len] = 0; 3977 /* coverity[secure_coding] */ 3978 len = sal_strlen(_SER_TEST_MEM_SOC_FIELD_NAME(unit, test_data->test_field)); 3979 if(sizeof(test_data->field_name)- 1 < len) { 3980 len = sizeof(test_data->field_name)- 1; 3981 } 3982 sal_strncpy(test_data->field_name, 3983 _SER_TEST_MEM_SOC_FIELD_NAME(unit, test_data->test_field), len); 3984 test_data->field_name[len] = 0; 3985 #else 3986 sprintf(test_data->mem_name, "Mem ID: %d", test_data->mem); 3987 sprintf(test_data->field_name, "Field ID: %d", test_data->test_field); 3988 #endif 3989 test_data->badData = 0; 3990 3991 #ifdef BCM_TRIDENT_SUPPORT 3992 test_data->pipe_select = NULL; 3993 #endif 3994 #ifdef BCM_TRIDENT3_SUPPORT 3995 if (SOC_IS_TRIDENT3X(unit)) { 3996 test_data->pipe_select = soc_trident3_pipe_select; 3997 } 3998 #endif 3999 } 4000 4001 4002 int soc_ser_test_long_sleep = FALSE; 4003 int soc_ser_test_long_sleep_time_us = 100000; 4004 /* 4005 * Function: 4006 * ser_test_mem 4007 * Purpose: 4008 * Serform a Software Error Recovery test on passed memory mem. 4009 * Parameters: 4010 * unit - (IN) Device Number 4011 * test_data - (IN) Structure which holds the test data and some 4012 intermediate results. 4013 * test_type - (IN) Used to determine how many indexes to test for 4014 each memory table. 4015 * error_count - (OUT)Increments if a test on any of the indexes 4016 in this memory fail. 4017 * Returns: 4018 * SOC_E_NONE if the test passes, an error if it does not 4019 */ 4020 #ifdef BCM_TOMAHAWK_SUPPORT 4021 extern int _soc_th_refresh_modify(int unit, int enable); 4022 #endif 4023 soc_error_t 4024 ser_test_mem(int unit, uint32 flags, ser_test_data_t *test_data, 4025 _soc_ser_test_t test_type, int *error_count) 4026 { 4027 int numIndexesToTest, j, read_through, startErrorCount; 4028 soc_error_t rv = SOC_E_NONE; 4029 int indexesToTest[3]; 4030 int mem_has_ecc; 4031 uint32 read_flags = 0; 4032 4033 indexesToTest[0] = soc_mem_index_min(unit,test_data->mem); 4034 startErrorCount = *error_count; 4035 /*Check that there is a meminfo structure for this memory.*/ 4036 if (!SOC_MEM_IS_VALID(unit, test_data->mem_fv)) { 4037 LOG_CLI((BSL_META_U(unit, 4038 "%s is not a valid memory for this platform. Skipping.\n"), 4039 SOC_MEM_NAME(unit, test_data->mem_fv))); 4040 return SOC_E_MEMORY; 4041 } 4042 /*Exit without testing if there is no SER flag set for this memory*/ 4043 if (!(SOC_MEM_INFO(unit,test_data->mem_fv).flags & SOC_MEM_SER_FLAGS)) { 4044 /*Verbose output: Skipping memory: name*/ 4045 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4046 "SOC_MEM_SER_FLAGS is not set for %s " 4047 "(flags 0x%8x). Skipping.\n"), 4048 SOC_MEM_NAME(unit, test_data->mem_fv), 4049 SOC_MEM_INFO(unit,test_data->mem_fv).flags)); 4050 return SOC_E_NONE; 4051 } 4052 switch (test_type) { 4053 case SER_FIRST_MID_LAST_INDEX: 4054 indexesToTest[1] = soc_mem_index_max(unit,test_data->mem_fv); 4055 indexesToTest[2] = (indexesToTest[1] - indexesToTest[0])/2; 4056 numIndexesToTest = 3; 4057 break; 4058 case SER_ALL_INDEXES: 4059 numIndexesToTest = soc_mem_index_max(unit,test_data->mem_fv) + 1; 4060 break; 4061 case SER_SINGLE_INDEX: 4062 /*FALL THOUGH*/ 4063 default: 4064 numIndexesToTest = 1; 4065 }; 4066 for (j = 0; j < numIndexesToTest; j++) { 4067 if (test_type == SER_ALL_INDEXES){ 4068 test_data->index_fv = j; 4069 } else { 4070 test_data->index_fv = indexesToTest[j]; 4071 } 4072 if (soc_feature(unit, soc_feature_field_slice_size128)) { 4073 if ((test_data->mem_fv == FP_TCAMm) || 4074 (test_data->mem_fv == FP_GLOBAL_MASK_TCAMm)) { 4075 /* Skip the entries that is not existed. */ 4076 if ((test_data->index_fv/64) % 2) { 4077 continue; 4078 } 4079 } 4080 } 4081 4082 /* Revaluate test_data->index for every index being tested */ 4083 SOC_IF_ERROR_RETURN 4084 (ser_test_mem_index_remap(unit, test_data, &mem_has_ecc)); 4085 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4086 "ser_mem_test: mem %s %s." 4087 "field %s, index_fv %d, index %d\n"), 4088 test_data->mem_name, 4089 mem_has_ecc? "is ECC protected" : " ", 4090 test_data->field_name, test_data->index_fv, 4091 test_data->index)); 4092 4093 if (soc_feature(unit, soc_feature_memory_2bit_ecc_ser)) { 4094 if (mem_has_ecc) { 4095 flags |= SOC_INJECT_ERROR_2BIT_ECC; 4096 } 4097 } else 4098 #ifdef BCM_TOMAHAWK_SUPPORT 4099 if (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 4100 /* compute mem_has_ecc - need to do tnis because for some mems in 4101 * regsfile, parity enable registers, etc are declared only for 4102 * _ECC view and not for func_view 4103 * Thus when we are here with incorrect assumption that 1b error needs to be 4104 * injected. 4105 */ 4106 /* mem_has_ecc = ser_test_mem_index_remap(unit, test_data); */ 4107 4108 /* Following assumes that in TH, we have injected 2b error if mem 4109 * was ECC protected. 4110 * For ECC protected mems, if we inject only 1b error, and even if 1b 4111 * error reporting is enabled, then we will see ser event and 4112 * correction but will not get NACK on 1st read 4113 */ 4114 if (mem_has_ecc) { 4115 flags |= SOC_INJECT_ERROR_2BIT_ECC; 4116 } 4117 } 4118 #endif /* BCM_TOMAHAWK_SUPPORT */ 4119 4120 /*Read through to the hardware.*/ 4121 if (flags & SOC_INJECT_ERROR_DONT_MAP_INDEX) { 4122 read_flags = SER_TEST_MEM_F_DONT_MAP_INDEX; 4123 } 4124 read_through = SOC_MEM_FORCE_READ_THROUGH(unit); 4125 SOC_MEM_FORCE_READ_THROUGH_SET(unit, TRUE); 4126 rv = (ser_test_mem_read(unit, read_flags, test_data)); 4127 if (SOC_FAILURE(rv)) { 4128 (*error_count)++; 4129 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4130 "SER failed. 1st Read got NACK. mem: %s field: %s\n"), 4131 test_data->mem_name, 4132 test_data->field_name)); 4133 return rv; 4134 } 4135 /*Disable Parity*/ 4136 rv = (_ser_test_parity_control(unit, test_data, 0)); 4137 if (SOC_FAILURE(rv)) { 4138 (*error_count)++; 4139 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4140 "SER failed. Disable Parity did not work. mem: %s field: %s\n"), 4141 test_data->mem_name, 4142 test_data->field_name)); 4143 return rv; 4144 } 4145 4146 /*Inject error:*/ 4147 if (flags & SOC_INJECT_ERROR_2BIT_ECC) { 4148 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4149 "SER info. 2b error will be injected for mem: %s\n"), 4150 test_data->mem_name)); 4151 } 4152 rv = (soc_ser_test_inject_error(unit, test_data, flags)); 4153 4154 if (SOC_FAILURE(rv)) { 4155 (*error_count)++; 4156 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4157 "SER failed. soc_ser_test_inject_error failed. mem: %s field: %s\n"), 4158 test_data->mem_name, 4159 test_data->field_name)); 4160 return rv; 4161 } 4162 /*Read back write to ensure value is still fudged.*/ 4163 rv = (ser_test_mem_read(unit, read_flags, test_data)); 4164 if (SOC_FAILURE(rv)) { 4165 (*error_count)++; 4166 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4167 "SER failed. could not corrupt the data. mem: %s field: %s\n"), 4168 test_data->mem_name, 4169 test_data->field_name)); 4170 return rv; 4171 } 4172 if (test_data->badData != test_data->field_buf[0]) { 4173 LOG_CLI((BSL_META_U(unit, 4174 "SER failed. Injection Error for mem: %s field: %s\n"), 4175 test_data->mem_name, 4176 test_data->field_name)); 4177 (*error_count)++; 4178 return SOC_E_FAIL; 4179 } 4180 /*Enable Parity (Even if it was not enabled before*/ 4181 rv = (_ser_test_parity_control(unit, test_data, 1)); 4182 if (SOC_FAILURE(rv)) { 4183 (*error_count)++; 4184 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 4185 "SER failed. Re-enable Parity did not work. mem: %s field: %s\n"), 4186 test_data->mem_name, 4187 test_data->field_name)); 4188 return rv; 4189 } 4190 if (SAL_BOOT_QUICKTURN) { 4191 sal_usleep(10000); /* Add delay for QT to trigger parity error */ 4192 } 4193 /*Read the memory entry with cache disabled, in order to induce the error*/ 4194 rv = ser_test_mem_read(unit, (read_flags | SER_TEST_MEM_F_READ_FUNC_VIEW), 4195 test_data); /* read func_view */ 4196 #ifdef BCM_TOMAHAWK_SUPPORT 4197 if (SOC_IS_TOMAHAWKX(unit)) { 4198 /* Following assumes that in TH, we have injected 2b error if mem 4199 * was ECC protected. 4200 * For ECC protected mems, if we inject only 1b error, and even if 1b 4201 * error reporting is enabled, then we will see ser event and 4202 * correction but will not get NACK on 1st read 4203 */ 4204 if (!SOC_FAILURE(rv)) { 4205 (*error_count)++; 4206 LOG_ERROR(BSL_LS_SOC_SER, 4207 (BSL_META_U(unit, 4208 "SER failed. Did not receive NACK on 1st Read " 4209 "for mem %s index %d\n"), 4210 SOC_MEM_NAME(unit, test_data->mem_fv), 4211 test_data->index_fv)); 4212 return SOC_E_FAIL; 4213 } 4214 } 4215 #endif /* BCM_TOMAHAWK_SUPPORT */ 4216 4217 /* 'MMU_THDM_DB_PORTSP_BST_0m' on Apache does not get corrected 4218 intime on Apache, hence we will sleep a little longer */ 4219 #ifdef BCM_APACHE_SUPPORT 4220 if (test_data->mem == MMU_THDM_DB_PORTSP_BST_0m) { 4221 sal_usleep(2000000); /*wait for memory and register ops to complete.*/ 4222 } else 4223 #endif 4224 { 4225 sal_usleep(1500000); /*wait for memory and register ops to complete.*/ 4226 } 4227 4228 if (SAL_BOOT_QUICKTURN) { 4229 sal_usleep(10000000); /* add more delay for Quickturn.*/ 4230 } else if (soc_ser_test_long_sleep) { 4231 sal_usleep(soc_ser_test_long_sleep_time_us); 4232 } 4233 /*Read the memory once more to compare it to the old value*/ 4234 rv = (ser_test_mem_read(unit, (read_flags | SER_TEST_MEM_F_READ_FUNC_VIEW), 4235 test_data)); /* read func_view */ 4236 if (SOC_FAILURE(rv)) { 4237 (*error_count)++; 4238 LOG_ERROR(BSL_LS_SOC_SER, 4239 (BSL_META_U(unit, 4240 "SER failed. Received NACK on 2nd Read " 4241 "for mem %s index %d\n"), 4242 SOC_MEM_NAME(unit, test_data->mem_fv), 4243 test_data->index_fv)); 4244 return rv; 4245 } 4246 4247 /* For case when we injected error on _ECC view, 4248 * we must now read _ECC view, so we can check: 4249 * a. whether entry got cleared for SER_ENTRY_CLEAR cases 4250 * b. whether field where we injected error matches badData 4251 */ 4252 if (test_data->mem != test_data->mem_fv) { 4253 rv = (ser_test_mem_read(unit, read_flags, test_data)); /* rd error_inject view */ 4254 if (SOC_FAILURE(rv)) { 4255 (*error_count)++; 4256 LOG_ERROR(BSL_LS_SOC_SER, 4257 (BSL_META_U(unit, 4258 "SER failed. Received NACK when reading" 4259 "error_inject view after 2nd read of" 4260 "func_view. mem %s index %d\n"), 4261 SOC_MEM_NAME(unit, test_data->mem), 4262 test_data->index)); 4263 return rv; 4264 } 4265 } 4266 SOC_MEM_FORCE_READ_THROUGH_SET(unit, read_through); 4267 if ((SOC_MEM_INFO(unit, test_data->mem_fv).flags & SOC_MEM_SER_FLAGS) == 4268 SOC_MEM_FLAG_SER_ENTRY_CLEAR) { 4269 if (0 != test_data->field_buf[0]) { 4270 (*error_count)++; 4271 LOG_ERROR(BSL_LS_SOC_SER, 4272 (BSL_META_U(unit, 4273 "SER failed to clear mem %s index %d field %s \n"), 4274 test_data->mem_name, test_data->index, 4275 test_data->field_name)); 4276 return SOC_E_FAIL; 4277 } 4278 } else if (test_data->badData == test_data->field_buf[0]) { 4279 #ifdef BCM_TRIUMPH2_SUPPORT 4280 if ((SOC_IS_TRIUMPH3(unit) && (test_data->mem == VLAN_OR_VFI_MAC_LIMITm)) || 4281 (SOC_IS_TRIUMPH2(unit) && ((test_data->mem == PORT_OR_TRUNK_MAC_LIMITm) || 4282 (test_data->mem == VLAN_OR_VFI_MAC_LIMITm))) || 4283 (SOC_IS_APOLLO(unit) && ((test_data->mem == PORT_OR_TRUNK_MAC_LIMITm) || 4284 (test_data->mem == VLAN_OR_VFI_MAC_LIMITm)))) 4285 { 4286 LOG_VERBOSE(BSL_LS_SOC_SER, 4287 (BSL_META_U(unit, 4288 "SER corrected mem %s index %d\n"), 4289 SOC_MEM_NAME(unit, test_data->mem_fv), 4290 test_data->index_fv)); 4291 } else 4292 #endif /* BCM_TRIUMPH2_SUPPORT */ 4293 { 4294 (*error_count)++; 4295 LOG_ERROR(BSL_LS_SOC_SER, 4296 (BSL_META_U(unit, 4297 "SER failed to correct mem %s index %d field %s\n"), 4298 test_data->mem_name, test_data->index, 4299 test_data->field_name)); 4300 return SOC_E_FAIL; 4301 } 4302 } 4303 else { 4304 LOG_VERBOSE(BSL_LS_SOC_SER, 4305 (BSL_META_U(unit, 4306 "SER corrected mem %s index %d\n"), 4307 SOC_MEM_NAME(unit, test_data->mem_fv), 4308 test_data->index_fv)); 4309 } 4310 } 4311 if (startErrorCount != *error_count) { 4312 LOG_CLI((BSL_META_U(unit, 4313 "SER failed to correct memory %s acc_type: %d field: %s %d:%d\n"), 4314 SOC_MEM_NAME(unit, test_data->mem_fv), 4315 (int)test_data->acc_type, 4316 test_data->field_name, 4317 startErrorCount, *error_count)); 4318 return SOC_E_FAIL; 4319 } 4320 return SOC_E_NONE; 4321 } 4322 4323 /* 4324 * Function: 4325 * _ser_test_parity_control_reg_set 4326 * Purpose: 4327 * Enables/Disables parity for tcam memories using the 'newer' soc_reg_set 4328 * call. This is what is used for Trident_2 and possibly newer devices. 4329 * Parameters: 4330 * unit - (IN) Device Number 4331 * test_data - (IN) Contains parity registers to set. 4332 * enable - (IN) (Bool) enable parity if true, disable if false 4333 * Returns: 4334 * SOC_E_NONE if no errors are encountered while setting parity. 4335 */ 4336 soc_error_t 4337 _ser_test_parity_control_reg_set(int unit, ser_test_data_t *test_data, int enable) 4338 { 4339 uint64 regData; 4340 if (enable) { 4341 /* In new devices SER_RANGE_ENABLE supports 32 ranges */ 4342 COMPILER_64_SET(regData, 0, 0xFFFFFFFF); 4343 } else { 4344 COMPILER_64_SET(regData, 0, 0x0); 4345 } 4346 return soc_reg_set(unit, test_data->parity_enable_reg, test_data->port, 0, regData); 4347 } 4348 4349 4350 /* 4351 * Function: 4352 * _ser_test_parity_control_pci_write 4353 * Purpose: 4354 * Enables/Disables parity for tcam memories using the less-compatible 4355 * soc_pci_write call. Used for older devices such as Trident and older. 4356 * Parameters: 4357 * unit - (IN) Device Number 4358 * test_data - (IN) Contains parity registers to set. 4359 * enable - (IN) (Bool) enable parity if true, disable if false 4360 * Returns: 4361 * SOC_E_NONE if no errors are encountered while setting parity. 4362 */ 4363 soc_error_t 4364 _ser_test_parity_control_pci_write(int unit, ser_test_data_t *test_data, int enable) 4365 { 4366 uint32 regDataOld; 4367 uint32 regAddr = soc_reg_addr(unit, test_data->parity_enable_reg, REG_PORT_ANY, 4368 test_data->tcam_parity_bit/16); 4369 if (enable) { 4370 regDataOld = 0xFFFF; 4371 } else { 4372 regDataOld = 0x0; 4373 } 4374 return soc_pci_write(unit,regAddr, regDataOld); 4375 } 4376 4377 4378 /* 4379 * Function: 4380 * _ser_test_parity_control 4381 * Purpose: 4382 * Disables/enables parity for the provided register. 4383 * Parameters: 4384 * unit - (IN) Device Number 4385 * test_data - (IN) Contains parity registers to set. 4386 * enable - (IN) (Bool) enable parity if true, disable if false 4387 * 4388 * Returns: 4389 * SOC_E_NONE if no errors are encountered while setting parity. 4390 */ 4391 soc_error_t 4392 _ser_test_parity_control(int unit, ser_test_data_t *test_data, int enable) 4393 { 4394 #ifdef INCLUDE_XFLOW_MACSEC 4395 int block_type = SOC_BLOCK_TYPE(unit, SOC_MEM_BLOCK_ANY(unit, test_data->mem)); 4396 #endif 4397 soc_error_t rv = SOC_E_NONE; 4398 if (test_data->tcam_parity_bit >= 0) { 4399 /*This register controls a TCAM memory*/ 4400 if (ser_test_functions[unit] != NULL && 4401 ser_test_functions[unit]->parity_control != NULL) { 4402 rv = (*(ser_test_functions[unit]->parity_control))(unit, test_data, 4403 enable); 4404 } else { 4405 rv = _ser_test_parity_control_reg_set(unit, test_data, enable); 4406 } 4407 } else { 4408 #ifdef BCM_TRIUMPH3_SUPPORT 4409 if (SOC_IS_TRIUMPH3(unit) && 4410 ser_test_functions[unit] != NULL && 4411 ser_test_functions[unit]->parity_control != NULL) { 4412 rv = (*(ser_test_functions[unit]->parity_control))(unit, test_data, 4413 enable); 4414 } else 4415 #endif 4416 { 4417 #ifdef BCM_TRIDENT2_SUPPORT 4418 if (SOC_IS_TRIDENT2(unit) || SOC_IS_TITAN2(unit)) { 4419 uint32 reg_data; 4420 /*This register is monitored by hardware*/ 4421 SOC_MEM_TEST_PIPE_LOCK(unit, test_data); 4422 rv = soc_reg32_get(unit, test_data->parity_enable_reg, 4423 test_data->port, 0, ®_data); 4424 soc_reg_field_set(unit, test_data->parity_enable_reg, ®_data, 4425 test_data->parity_enable_field, enable); 4426 rv = soc_reg32_set(unit, test_data->parity_enable_reg, 4427 test_data->port, 0, reg_data); 4428 SOC_MEM_TEST_PIPE_UNLOCK(unit, test_data); 4429 } else 4430 #endif 4431 { 4432 SOC_MEM_TEST_PIPE_LOCK(unit, test_data); 4433 #ifdef BCM_TOMAHAWK_SUPPORT 4434 if (SOC_IS_TOMAHAWKX(unit)) { 4435 if ((test_data->parity_enable_reg == MTRO_ENABLE_ECCP_MEMr) || 4436 (test_data->parity_enable_reg == Q_SCHED_ENABLE_ECCP_MEMr) || 4437 (test_data->parity_enable_reg == MMU_DQS_ENABLE_ECCP_MEMr) || 4438 (test_data->parity_enable_reg == MMU_MB_TCB_ENABLE_ECCP_MEMr) || 4439 (test_data->parity_enable_reg == MMU_ENQX_ENABLE_ECCP_MEMr)) { 4440 int i; 4441 for (i = 0; i < NUM_PIPE(unit); i++) { 4442 rv = soc_th_ser_reg_field32_modify( 4443 unit, test_data->parity_enable_reg, 4444 test_data->port, test_data->parity_enable_field, 4445 enable, 4446 0, /* index */ 4447 i); /* mmu_base_index */ 4448 } 4449 } else { 4450 #ifdef BCM_TOMAHAWK3_SUPPORT 4451 if (SOC_IS_TOMAHAWK3(unit)) { 4452 rv = soc_tomahawk3_parity_bit_enable(unit, test_data->parity_enable_reg, 4453 test_data->parity_enable_mem, 4454 test_data->parity_enable_field, 4455 test_data->parity_enable_field_position, 4456 enable); 4457 } else 4458 #endif 4459 { 4460 rv = soc_reg_field32_modify(unit, test_data->parity_enable_reg, 4461 test_data->port, 4462 test_data->parity_enable_field, enable); 4463 } 4464 } 4465 4466 } else 4467 #endif 4468 #ifdef BCM_TRIDENT3_SUPPORT 4469 if (SOC_IS_TRIDENT3X(unit)) { 4470 if ((test_data->parity_enable_reg == MTRO_ENABLE_ECCP_MEMr) || 4471 (test_data->parity_enable_reg == Q_SCHED_ENABLE_ECCP_MEMr) || 4472 (test_data->parity_enable_reg == MMU_DQS_ENABLE_ECCP_MEMr) || 4473 (test_data->parity_enable_reg == MMU_MB_TCB_ENABLE_ECCP_MEMr)) { 4474 int i; 4475 for (i = 0; i < NUM_PIPE(unit); i++) { 4476 rv = soc_td3_ser_reg_field32_modify( 4477 unit, test_data->parity_enable_reg, 4478 test_data->port, test_data->parity_enable_field, 4479 enable, 4480 0, /* index */ 4481 i); /* mmu_base_index */ 4482 } 4483 } else { 4484 rv = soc_td3_parity_bit_enable(unit, test_data->parity_enable_reg, 4485 test_data->parity_enable_mem, 4486 test_data->parity_enable_field, 4487 test_data->parity_enable_field_position, 4488 enable); 4489 } 4490 } else 4491 #endif 4492 { 4493 #ifdef INCLUDE_XFLOW_MACSEC 4494 if (soc_feature(unit, soc_feature_xflow_macsec)) { 4495 4496 rv = soc_reg_field32_modify(unit, test_data->parity_enable_reg, 4497 test_data->port, 4498 test_data->parity_enable_field, (block_type != SOC_BLK_MACSEC) ? enable : !enable); 4499 } else 4500 #endif 4501 { 4502 rv = soc_reg_field32_modify(unit, test_data->parity_enable_reg, 4503 test_data->port, 4504 test_data->parity_enable_field, enable); 4505 } 4506 } 4507 SOC_MEM_TEST_PIPE_UNLOCK(unit, test_data); 4508 } 4509 } 4510 } 4511 return rv; 4512 } 4513 4514 4515 /* 4516 * Function: 4517 * ser_test_cmd_generate 4518 * Purpose: 4519 * Creates a test for a memory the user can then run from the commandline 4520 * Parameters: 4521 * unit - (IN) Device Number 4522 * test_data - (IN) Contains all test attributes required to print the 4523 * test commands 4524 */ 4525 void 4526 ser_test_cmd_generate(int unit, ser_test_data_t *test_data) 4527 { 4528 char* pipe_str; 4529 int ypipe = FALSE; 4530 if (test_data != NULL && test_data->mem_name != NULL && 4531 SOC_MEM_FIELD_VALID(unit, test_data->mem, test_data->test_field)) { 4532 if (test_data->acc_type == _SOC_ACC_TYPE_PIPE_Y) { 4533 pipe_str = "pipe_y "; 4534 ypipe = TRUE; 4535 } else { 4536 pipe_str = ""; 4537 } 4538 LOG_CLI((BSL_META_U(unit, 4539 "\nCommand line test for memory %s: access_type: %d\n"), 4540 test_data->mem_name, test_data->acc_type)); 4541 if (ypipe) { 4542 LOG_CLI((BSL_META_U(unit, 4543 "s EGR_SBS_CONTROL PIPE_SELECT=1\n"))); 4544 LOG_CLI((BSL_META_U(unit, 4545 "s SBS_CONTROL PIPE_SELECT=1\n"))); 4546 } 4547 LOG_CLI((BSL_META_U(unit, 4548 "wr %s%s 1 1 %s=0\n"), 4549 pipe_str, test_data->mem_name, test_data->field_name)); 4550 LOG_CLI((BSL_META_U(unit, 4551 "d nocache %s%s 1 1\n"), pipe_str, test_data->mem_name)); 4552 if (test_data->tcam_parity_bit != -1) { 4553 LOG_CLI((BSL_META_U(unit, 4554 "s %s %s=0\n"), 4555 SOC_REG_NAME(unit,test_data->parity_enable_reg), 4556 SOC_FIELD_NAME(unit, 4557 test_data->parity_enable_field))); 4558 } else { 4559 LOG_CLI((BSL_META_U(unit, 4560 "s %s 0\n"), 4561 SOC_REG_NAME(unit,test_data->parity_enable_reg))); 4562 } 4563 LOG_CLI((BSL_META_U(unit, 4564 "wr nocache %s%s 1 1 %s=1\n"), 4565 pipe_str, test_data->mem_name, test_data->field_name)); 4566 if (test_data->tcam_parity_bit != -1) { 4567 LOG_CLI((BSL_META_U(unit, 4568 "s %s %s=1\n"), 4569 SOC_REG_NAME(unit, test_data->parity_enable_reg), 4570 SOC_FIELD_NAME(unit, 4571 test_data->parity_enable_field))); 4572 } else { 4573 LOG_CLI((BSL_META_U(unit, 4574 "s %s 1\n"), 4575 SOC_REG_NAME(unit,test_data->parity_enable_reg))); 4576 } 4577 LOG_CLI((BSL_META_U(unit, 4578 "d nocache %s%s 1 1\n"), pipe_str, test_data->mem_name)); 4579 if (ypipe) { 4580 LOG_CLI((BSL_META_U(unit, 4581 "s EGR_SBS_CONTROL PIPE_SELECT=0\n"))); 4582 LOG_CLI((BSL_META_U(unit, 4583 "s SBS_CONTROL PIPE_SELECT=0\n"))); 4584 } 4585 4586 } else { 4587 LOG_CLI((BSL_META_U(unit, 4588 "ERROR: Attempted to print a cmd from missing data.\n"))); 4589 } 4590 } 4591 4592 4593 /* 4594 * Function: 4595 * soc_ser_test_overlays 4596 * Purpose: 4597 * Enables SER test functions for a unit 4598 * Parameters: 4599 * unit - (IN) Device Number 4600 * test_type - (IN) Sets how many memories to test 4601 * overlays - (IN) List of all overlay memories to test 4602 * pipe_select - (IN) Chip-specific function used to change pipe select 4603 */ 4604 int 4605 soc_ser_test_overlays(int unit, _soc_ser_test_t test_type, 4606 const soc_ser_overlay_test_t *overlays, 4607 int(*pipe_select)(int,int,int) ) 4608 { 4609 int i, mem_failed=0, rv = SOC_E_NONE; 4610 soc_acc_type_t acc_type; 4611 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 4612 ser_test_data_t test_data; 4613 if (overlays == NULL) { 4614 return -1; 4615 } 4616 for (i = 0; overlays[i].mem != INVALIDm; i++) { 4617 int last_failed = mem_failed; 4618 acc_type = overlays[i].acc_type; 4619 4620 if (SOC_MEM_INFO(unit, overlays[i].mem).flags & 4621 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP) { 4622 continue; 4623 } 4624 4625 if (soc_mem_index_count(unit, overlays[i].mem) <= 0) { 4626 continue; 4627 } 4628 4629 soc_ser_create_test_data(unit, tmp_entry, fieldData, 4630 overlays[i].parity_enable_reg, 4631 SOC_INVALID_TCAM_PARITY_BIT, 4632 overlays[i].parity_enable_field, 4633 overlays[i].mem, EVEN_PARITYf, 4634 MEM_BLOCK_ANY, REG_PORT_ANY, 4635 acc_type, 0, &test_data); 4636 4637 if(NULL != pipe_select) { 4638 pipe_select(unit, TRUE, ((acc_type == _SOC_ACC_TYPE_PIPE_Y)? 1:0)); 4639 pipe_select(unit, FALSE, ((acc_type == _SOC_ACC_TYPE_PIPE_Y)? 1:0)); 4640 } 4641 4642 rv = ser_test_mem(unit, 0, &test_data, test_type, &mem_failed); 4643 4644 /*Clear memory so other views can be used.*/ 4645 if (soc_mem_clear(unit,overlays[i].mem, MEM_BLOCK_ALL, TRUE) < 0) { 4646 return -1; 4647 } 4648 4649 if(NULL != pipe_select) { 4650 pipe_select(unit, TRUE,0); 4651 pipe_select(unit, FALSE,0); 4652 } 4653 4654 if ((mem_failed != last_failed) || (rv != SOC_E_NONE)) { 4655 LOG_CLI((BSL_META_U(unit, 4656 "%s failed overlay test.\n"), 4657 SOC_MEM_NAME(unit,test_data.mem))); 4658 } 4659 } 4660 return mem_failed; 4661 } 4662 4663 4664 /* 4665 * Function: 4666 * soc_ser_test_functions_register 4667 * Purpose: 4668 * Enables SER test functions for a unit 4669 * Parameters: 4670 * unit - (IN) Device Number 4671 * fun - (IN) An instance of soc_ser_test_functions_t with pointers to 4672 * functions required for chip-specific SER test 4673 implementations. 4674 */ 4675 void 4676 soc_ser_test_functions_register(int unit, soc_ser_test_functions_t *fun) 4677 { 4678 if (unit < SOC_MAX_NUM_DEVICES) { 4679 ser_test_functions[unit] = fun; 4680 } 4681 else { 4682 LOG_VERBOSE(BSL_LS_SOC_SER, 4683 (BSL_META_U(unit, 4684 "Invalid unit parameter %d: passed to soc_ser_test_functions_t"), 4685 unit)); 4686 } 4687 } 4688 4689 4690 /* 4691 * Function: 4692 * soc_ser_inject_error 4693 * Purpose: 4694 * Redirect to appropriate chip-specific function. 4695 * These are found in the chip's soc/esw/X.c file 4696 * and registered during misc init. 4697 */ 4698 soc_error_t 4699 soc_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, int pipe, 4700 int blk, int index) 4701 { 4702 if( ser_test_functions[unit] != NULL && 4703 ser_test_functions[unit]->inject_error_f != NULL) { 4704 return (*(ser_test_functions[unit]->inject_error_f))(unit, flags, mem, 4705 pipe, blk, index); 4706 } 4707 return SOC_E_FAIL; 4708 } 4709 4710 /* 4711 * Function: 4712 * soc_ser_inject_support 4713 * Purpose: 4714 * Routine to determine Memory is supported by error 4715 * injection interface. 4716 */ 4717 soc_error_t 4718 soc_ser_inject_support(int unit, soc_mem_t mem, int pipe) 4719 { 4720 if( ser_test_functions[unit] != NULL && 4721 ser_test_functions[unit]->injection_support != NULL) { 4722 return (*(ser_test_functions[unit]->injection_support)) 4723 (unit, mem, pipe); 4724 } 4725 return SOC_E_FAIL; 4726 } 4727 4728 /* 4729 * Function: 4730 * soc_ser_test_mem 4731 * Purpose: 4732 * Redirect to appropriate chip-specific function. 4733 * These are found in the chip's soc/esw/X.c file 4734 * and registered during misc init. 4735 */ 4736 soc_error_t 4737 soc_ser_test_mem(int unit, soc_mem_t mem, _soc_ser_test_t testType, int cmd) 4738 { 4739 if( ser_test_functions[unit] != NULL && 4740 ser_test_functions[unit]->test_mem != NULL) { 4741 return (*(ser_test_functions[unit]->test_mem))(unit, mem, testType, cmd); 4742 } 4743 return SOC_E_FAIL; 4744 } 4745 4746 4747 /* 4748 * Function: 4749 * soc_ser_test 4750 * Purpose: 4751 * Redirect to appropriate chip-specific function. 4752 * These are found in the chip's soc/esw/X.c file and registered during misc init. 4753 */ 4754 soc_error_t 4755 soc_ser_test(int unit, _soc_ser_test_t testType) 4756 { 4757 if( ser_test_functions[unit] != NULL && 4758 ser_test_functions[unit]->test != NULL) { 4759 return (*(ser_test_functions[unit]->test))(unit, testType); 4760 } 4761 return SOC_E_FAIL; 4762 } 4763 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 4764 #endif /* defined (SER_TR_TEST_SUPPORT)*/ 4765 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */