iproc.c (101505B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * iProc support 8 */ 9 10 #include <shared/bsl.h> 11 12 #include <sal/core/boot.h> 13 #include <sal/core/libc.h> 14 #include <sal/types.h> 15 #include <shared/alloc.h> 16 #include <soc/memtune.h> 17 18 #include <soc/drv.h> 19 #include <soc/debug.h> 20 #include <soc/cm.h> 21 #ifdef BCM_CMICM_SUPPORT 22 #include <soc/cmicm.h> 23 #endif 24 #include <ibde.h> 25 26 #ifdef BCM_IPROC_SUPPORT 27 #include <soc/iproc.h> 28 29 #ifdef BCM_IPROC_DDR_SUPPORT 30 #include <soc/shmoo_ddr40.h> 31 #include <soc/shmoo_and28.h> 32 #include <soc/shmoo_sjc16.h> 33 #include <soc/phy/ydc_ddr_bist.h> 34 #include <sal/appl/config.h> 35 #endif 36 37 /* 38 * Function: 39 * soc_iproc_init 40 * Purpose: 41 * Initialize iProc subsystem 42 * Parameters: 43 * unit - unit number 44 * Returns: 45 * SOC_E_XXX 46 */ 47 int soc_iproc_init(int unit) 48 { 49 return SOC_E_NONE; 50 } 51 52 /* 53 * Function: 54 * soc_iproc_deinit 55 * Purpose: 56 * Free up resources aquired by init. 57 * Parameters: 58 * unit - unit number 59 * Returns: 60 * SOC_E_XXX 61 * Notes: 62 * This function is currently not used. 63 */ 64 int soc_iproc_deinit(int unit) 65 { 66 return SOC_E_NONE; 67 } 68 69 /* 70 * Function: 71 * soc_iproc_getreg 72 * Purpose: 73 * Read iProc register outside CMIC 74 * Parameters: 75 * unit - unit number 76 * Returns: 77 * SOC_E_XXX 78 */ 79 int soc_iproc_getreg(int unit, uint32 addr, uint32 *data) 80 { 81 *data = soc_cm_iproc_read(unit, addr); 82 return SOC_E_NONE; 83 } 84 85 86 /* 87 * Function: 88 * soc_iproc_setreg 89 * Purpose: 90 * Write iProc register outside CMIC 91 * Parameters: 92 * unit - unit number 93 * Returns: 94 * SOC_E_XXX 95 */ 96 int soc_iproc_setreg(int unit, uint32 addr, uint32 data) 97 { 98 soc_cm_iproc_write(unit, addr, data); 99 return SOC_E_NONE; 100 } 101 102 /* 103 * Function: soc_iproc_shutdown 104 * Purpose: Put an IPROC into sleep state 105 * Parameters: unit - unit number 106 * cpu_mask - mask of cores to shutdown 107 * level - shutdown level: 0=full, 1=partial 108 * Returns: SOC_E_xxxx 109 */ 110 int 111 soc_iproc_shutdown(int unit, uint32 cpu_mask, int level) 112 { 113 uint32 i, rval; 114 uint32 sram_base, sram_size; 115 uint32 iproc_addr; 116 117 if (!soc_feature(unit, soc_feature_iproc)) { 118 return (SOC_E_FAIL); 119 } 120 121 if ((SOC_REG_IS_VALID(unit, CRU_IHOST_PWRDWN_STATUSr)) && 122 (SOC_REG_FIELD_VALID(unit, CRU_IHOST_PWRDWN_STATUSr, LOGIC_PWRDOWN_CPU0f))) { 123 READ_CRU_IHOST_PWRDWN_STATUSr(unit, &rval); 124 if (soc_reg_field_get(unit, CRU_IHOST_PWRDWN_STATUSr, rval, LOGIC_PWRDOWN_CPU0f) == 1) { 125 /* if the uC has been shut down, do nothing */ 126 LOG_VERBOSE(BSL_LS_SOC_COMMON, 127 (BSL_META_U(unit, 128 "The uC has been shut down, do nothing.\n"))); 129 return (SOC_E_NONE); 130 } 131 } 132 133 LOG_VERBOSE(BSL_LS_SOC_COMMON, 134 (BSL_META_U(unit, 135 "iproc_shutdown\n"))); 136 137 if (SOC_IS_HELIX4(unit)) { 138 /* Assumes booting in QSPI mode with MDIO tied high */ 139 sram_base = 0x1b000000; 140 sram_size = 512 * 1024; 141 iproc_addr = sram_base + sram_size - 8; 142 143 /* load WFI loop into SRAM (ARM mode) */ 144 soc_cm_iproc_write(unit, iproc_addr, 0xe320f003); 145 soc_cm_iproc_write(unit, iproc_addr + 4, 0xeafffffd); 146 147 /* Update LUT to point at WFI loop */ 148 for (i = 0; i < 8; ++i) { 149 soc_cm_iproc_write(unit, 0xffff0400 + i*4, iproc_addr); 150 } 151 /* core 0 should be in WFI now */ 152 if (level == 0) { 153 if (cpu_mask & 0x2) { 154 READ_CRU_IHOST_PWRDWN_ENr(unit, &rval); 155 soc_reg_field_set(unit, CRU_IHOST_PWRDWN_ENr, &rval, 156 LOGIC_CLAMP_ON_NEON1f, 1); 157 WRITE_CRU_IHOST_PWRDWN_ENr(unit, rval); 158 soc_reg_field_set(unit, CRU_IHOST_PWRDWN_ENr, &rval, 159 LOGIC_PWRDOWN_NEON1f, 1); 160 WRITE_CRU_IHOST_PWRDWN_ENr(unit, rval); 161 soc_reg_field_set(unit, CRU_IHOST_PWRDWN_ENr, &rval, 162 LOGIC_CLAMP_ON_CPU1f, 1); 163 WRITE_CRU_IHOST_PWRDWN_ENr(unit, rval); 164 soc_reg_field_set(unit, CRU_IHOST_PWRDWN_ENr, &rval, 165 RAM_CLAMP_ON_CPU1f, 1); 166 WRITE_CRU_IHOST_PWRDWN_ENr(unit, rval); 167 soc_reg_field_set(unit, CRU_IHOST_PWRDWN_ENr, &rval, 168 LOGIC_PWRDOWN_CPU1f, 1); 169 WRITE_CRU_IHOST_PWRDWN_ENr(unit, rval); 170 soc_reg_field_set(unit, CRU_IHOST_PWRDWN_ENr, &rval, 171 RAM_PWRDOWN_CPU1f, 1); 172 WRITE_CRU_IHOST_PWRDWN_ENr(unit, rval); 173 } 174 /* Put cpu0 into shutdown after 100 clocks */ 175 READ_CRU_CPU0_POWERDOWNr(unit, &rval); 176 soc_reg_field_set(unit, CRU_CPU0_POWERDOWNr, &rval, 177 START_CPU0_POWERDOWN_SEQf, 1); 178 soc_reg_field_set(unit, CRU_CPU0_POWERDOWNr, &rval, 179 CPU0_POWERDOWN_TIMERf, 100); 180 WRITE_CRU_CPU0_POWERDOWNr(unit, rval); 181 } 182 } 183 return (SOC_E_NONE); 184 } 185 186 187 /* 188 * Function: 189 * soc_iproc_config_genpll 190 * Purpose: 191 * Initialize IPROC gen_pll 192 * Parameters: 193 * unit - unit number 194 * genpll_clk_tbl - the clock table for gen_pll 195 * Returns: 196 * SOC_E_XXX 197 */ 198 int 199 soc_iproc_config_genpll(int unit, uint32 *genpll_clk_tbl) 200 { 201 soc_timeout_t to; 202 sal_usecs_t to_val = 500000; /* 500ms */ 203 uint32 rval; 204 int i = 0; 205 206 /* Clear Load_en Channel3 & Channel4 */ 207 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_GEN_PLL_CTRL3r(unit, &rval)); 208 rval &= 0xffc0ffff; 209 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_GEN_PLL_CTRL3r(unit, rval)); 210 211 /* Write fast_lock =1 */ 212 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_GEN_PLL_CTRL0r(unit, &rval)); 213 soc_reg_field_set(unit, IPROC_WRAP_GEN_PLL_CTRL0r, &rval, FAST_LOCKf, 1); 214 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_GEN_PLL_CTRL0r(unit, rval)); 215 216 /* Write NDIV */ 217 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_GEN_PLL_CTRL1r(unit, &rval)); 218 rval &= 0xfffffc00; 219 soc_reg_field_set(unit, IPROC_WRAP_GEN_PLL_CTRL1r, &rval, NDIV_INTf, genpll_clk_tbl[i+1]); 220 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_GEN_PLL_CTRL1r(unit, rval)); 221 222 /* Write MDIV */ 223 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_GEN_PLL_CTRL2r(unit, &rval)); 224 rval &= 0xff0000ff; 225 soc_reg_field_set(unit, IPROC_WRAP_GEN_PLL_CTRL2r, &rval, CH3_MDIVf, genpll_clk_tbl[i+5]); 226 soc_reg_field_set(unit, IPROC_WRAP_GEN_PLL_CTRL2r, &rval, CH4_MDIVf, genpll_clk_tbl[i+6]); 227 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_GEN_PLL_CTRL2r(unit, rval)); 228 229 /* Write PLL_LOAD */ 230 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_GEN_PLL_CTRL3r(unit, &rval)); 231 soc_reg_field_set(unit, IPROC_WRAP_GEN_PLL_CTRL3r, &rval, SW_TO_GEN_PLL_LOADf, 1); 232 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_GEN_PLL_CTRL3r(unit, rval)); 233 234 235 /* Load Channel3 & Channel4 */ 236 rval &= 0xffc0ffff; 237 soc_reg_field_set(unit, IPROC_WRAP_GEN_PLL_CTRL3r, &rval, LOAD_EN_CHf, 0x18); 238 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_GEN_PLL_CTRL3r(unit, rval)); 239 240 /* Wait for IPROC_WWRAP GENPLL lock */ 241 soc_timeout_init(&to, to_val, 0); 242 for(;;) { 243 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_GEN_PLL_STATUSr(unit, &rval)); 244 if (soc_reg_field_get(unit, IPROC_WRAP_GEN_PLL_STATUSr, rval, GEN_PLL_LOCKf)) { 245 break; 246 } 247 if (soc_timeout_check(&to)) { 248 LOG_ERROR(BSL_LS_SOC_COMMON, 249 (BSL_META_U(unit, 250 "Timed out waiting for IPROC_WWRAP GENPLL lock\n"))); 251 252 return SOC_E_TIMEOUT; 253 } 254 } 255 256 return SOC_E_NONE; 257 } 258 259 #ifdef BCM_IPROC_DDR_SUPPORT 260 261 #ifdef BCM_HURRICANE2_SUPPORT 262 const static unsigned int hr2_ddr_init_tab[] = { 263 14, 0x00000001, 264 36, 0x01000000, 265 37, 0x10000000, 266 38, 0x00100400, 267 39, 0x00000400, 268 40, 0x00000100, 269 42, 0x00000001, 270 61, 0x00010100, 271 78, 0x01000200, 272 79, 0x02000040, 273 80, 0x00400100, 274 81, 0x00000200, 275 83, 0x01ffff0a, 276 84, 0x01010101, 277 85, 0x01010101, 278 86, 0x0f000003, 279 87, 0x0000010c, 280 88, 0x00010000, 281 112, 0x00000200, 282 116, 0x0d000000, 283 117, 0x00000028, 284 119, 0x00010001, 285 120, 0x00010001, 286 121, 0x00010001, 287 122, 0x00010001, 288 123, 0x00010001, 289 130, 0x00000001, 290 139, 0x00000001, 291 148, 0x00000001, 292 149, 0x00000000, 293 150, 0x00000000, 294 152, 0x03030303, 295 153, 0x03030303, 296 156, 0x02006400, 297 157, 0x02020202, 298 158, 0x00020202, 299 160, 0x01000000, 300 161, 0x01010064, 301 162, 0x01010101, 302 163, 0x00000101, 303 165, 0x00020000, 304 166, 0x00000064, 305 168, 0x000b0b00, 306 170, 0x02000200, 307 171, 0x02000200, 308 175, 0x02000200, 309 176, 0x02000200, 310 180, 0x80000100, 311 181, 0x04070303, 312 182, 0x0000000a, 313 185, 0x0010ffff, 314 187, 0x0000000f, 315 194, 0x00000204, 316 205, 0x00000000, 317 0xffffffff 318 }; 319 320 const static unsigned int hr2_ddr_init_tab_800[] = { 321 0, 0x00000600, 322 1, 0x00000000, 323 3, 0x00000050, 324 4, 0x000000c8, 325 5, 0x0c050c00, 326 6, 0x04040405, 327 7, 0x06041018, 328 8, 0x04101804, 329 9, 0x0c040406, 330 10, 0x03006db0, 331 11, 0x0c040404, 332 12, 0x03006db0, 333 13, 0x01010004, 334 15, 0x000c0c00, 335 16, 0x03000200, 336 17, 0x00001212, 337 18, 0x06060000, 338 19, 0x00000000, 339 20, 0x00009001, 340 21, 0x00900c28, 341 22, 0x00050c28, 342 23, 0x00000300, 343 24, 0x000a0003, 344 25, 0x0000000a, 345 26, 0x00000000, 346 27, 0x02000000, 347 28, 0x0200006c, 348 29, 0x0000006c, 349 30, 0x05000001, 350 31, 0x00050505, 351 32, 0x00000000, 352 35, 0x00000000, 353 41, 0x00000000, 354 43, 0x00000000, 355 44, 0x00042000, 356 45, 0x00000046, 357 46, 0x00460420, 358 47, 0x00000000, 359 48, 0x04200000, 360 49, 0x00000046, 361 50, 0x00460420, 362 51, 0x00000000, 363 52, 0x04200000, 364 53, 0x00000046, 365 54, 0x00460420, 366 55, 0x00000000, 367 56, 0x04200000, 368 57, 0x00000046, 369 58, 0x00460420, 370 59, 0x00000000, 371 60, 0x00000000, 372 62, 0x00000000, 373 63, 0x00000000, 374 64, 0x00000000, 375 65, 0x00000000, 376 66, 0x00000000, 377 67, 0x00000000, 378 68, 0x00000000, 379 69, 0x00000000, 380 70, 0x00000000, 381 71, 0x00000000, 382 72, 0x00000000, 383 73, 0x00000000, 384 74, 0x00000000, 385 75, 0x00000000, 386 76, 0x00000000, 387 77, 0x00000000, 388 82, 0x01010001, 389 89, 0x00000000, 390 90, 0x00000000, 391 91, 0x00000000, 392 92, 0x00000000, 393 93, 0x00000000, 394 94, 0x00000000, 395 95, 0x00000000, 396 96, 0x00000000, 397 97, 0x00000000, 398 98, 0x00000000, 399 99, 0x00000000, 400 100, 0x00000000, 401 101, 0x00000000, 402 102, 0x00000000, 403 103, 0x00000000, 404 104, 0x00000000, 405 105, 0x00000000, 406 106, 0x00000000, 407 107, 0x00000000, 408 108, 0x02040108, 409 109, 0x08010402, 410 110, 0x02020002, 411 111, 0x01000200, 412 113, 0x00000000, 413 114, 0x00000000, 414 115, 0x00000000, 415 118, 0x00000000, 416 124, 0x00000000, 417 125, 0x00000000, 418 126, 0x00000000, 419 127, 0x00000000, 420 128, 0x00212100, 421 129, 0x21210001, 422 131, 0x00000000, 423 132, 0x00000000, 424 133, 0x00012121, 425 134, 0x00012121, 426 135, 0x00000000, 427 136, 0x00000000, 428 137, 0x00212100, 429 138, 0x21210001, 430 140, 0x00000000, 431 141, 0x00000000, 432 142, 0x00012121, 433 143, 0x00012121, 434 144, 0x00000000, 435 145, 0x00000000, 436 146, 0x00212100, 437 147, 0x21210001, 438 151, 0x00000000, 439 167, 0x00000000, 440 169, 0x0c280000, 441 172, 0x00000c28, 442 173, 0x00007990, 443 174, 0x0c280505, 444 177, 0x00000c28, 445 178, 0x00007990, 446 179, 0x02020505, 447 183, 0x00000000, 448 184, 0x00000000, 449 186, 0x00070303, 450 188, 0x00000000, 451 189, 0x00000000, 452 190, 0x00000000, 453 191, 0x00000000, 454 192, 0x00000000, 455 193, 0x00000000, 456 195, 0x00000000, 457 196, 0x00000000, 458 197, 0x00000000, 459 198, 0x00000000, 460 199, 0x00000000, 461 200, 0x00000000, 462 201, 0x00000000, 463 202, 0x00000004, 464 203, 0x00000004, 465 204, 0x00000000, 466 206, 0x02040401, 467 207, 0x00000002, 468 208, 0x00000000, 469 209, 0x00000000, 470 210, 0x06060000, 471 211, 0x00000606, 472 212, 0x00000040, 473 213, 0x00000000, 474 214, 0x01010606, 475 215, 0x00000101, 476 216, 0x00001c1c, 477 217, 0x00000000, 478 0xffffffff 479 }; 480 481 #endif /* BCM_HURRICANE2_SUPPORT */ 482 483 #ifdef BCM_GREYHOUND_SUPPORT 484 485 unsigned int gh_ddr_init_tab[] = { 486 0xffffffff 487 }; 488 489 unsigned int gh_ddr3_init_tab_800[] = { 490 0, 0x00000600, 491 1, 0x00000000, 492 2, 0x00000000, 493 3, 0x00000000, 494 4, 0x00000000, 495 5, 0x00000000, 496 6, 0x00000000, 497 7, 0x00000400, 498 8, 0x00000000, 499 9, 0x00000000, 500 10, 0x00000000, 501 11, 0x00000004, 502 12, 0x00000000, 503 13, 0x00000000, 504 14, 0x01000000, 505 15, 0x00000050, 506 16, 0x000000c8, 507 17, 0x00000000, 508 18, 0x02000000, 509 19, 0x00050c00, 510 20, 0x00000000, 511 21, 0x00050c00, 512 22, 0x00000000, 513 23, 0x05040400, 514 24, 0x0f150004, 515 25, 0x15060404, 516 26, 0x15000405, 517 27, 0x0604040f, 518 28, 0x04040415, 519 29, 0x006db00c, 520 30, 0x040c0503, 521 31, 0x000c0404, 522 32, 0x03006db0, 523 33, 0x06000c05, 524 34, 0x00060606, 525 35, 0x010c003c, 526 36, 0x0a140a0a, 527 37, 0x0100000a, 528 38, 0x0c0c0101, 529 39, 0x01060603, 530 40, 0x00010100, 531 41, 0x00000000, 532 42, 0x00000000, 533 43, 0x008c0100, 534 44, 0x00000c28, 535 45, 0x0000008c, 536 46, 0x00000c28, 537 47, 0x00000005, 538 48, 0x00030003, 539 49, 0x000a000a, 540 50, 0x00000000, 541 51, 0x00000000, 542 52, 0x02000000, 543 53, 0x02000090, 544 54, 0x00000090, 545 55, 0x05000001, 546 56, 0x00050505, 547 57, 0x00000000, 548 58, 0x00000000, 549 59, 0x00010000, 550 60, 0x10040010, 551 61, 0x00000400, 552 62, 0x00000200, 553 63, 0x00000000, 554 64, 0x00000001, 555 65, 0x00000000, 556 66, 0x00000000, 557 67, 0x00000000, 558 68, 0x00000000, 559 69, 0x00000000, 560 70, 0x00000000, 561 71, 0x00000000, 562 72, 0x00000000, 563 73, 0x00000000, 564 74, 0x00000000, 565 75, 0x00000000, 566 76, 0x00000000, 567 77, 0x00000000, 568 78, 0x00000000, 569 79, 0x00000000, 570 80, 0x00000000, 571 81, 0x00000000, 572 82, 0x00000000, 573 83, 0x00000000, 574 84, 0x00000420, 575 85, 0x00000046, 576 86, 0x00000000, 577 87, 0x00000420, 578 88, 0x00000046, 579 89, 0x00000000, 580 90, 0x00000000, 581 92, 0x00000000, 582 93, 0x00000000, 583 94, 0x00000000, 584 95, 0x00000000, 585 96, 0x00000000, 586 97, 0x00000000, 587 98, 0x00000420, 588 99, 0x00000046, 589 100, 0x00000000, 590 101, 0x00000420, 591 102, 0x00000046, 592 103, 0x00000000, 593 104, 0x00000000, 594 106, 0x00000000, 595 107, 0x00000000, 596 108, 0x00000000, 597 109, 0x00000000, 598 110, 0x00000000, 599 111, 0x00000000, 600 139, 0x00000000, 601 140, 0x01000000, 602 141, 0x00000001, 603 142, 0x00000000, 604 143, 0x00000000, 605 144, 0x00000000, 606 145, 0x00000000, 607 146, 0x00000000, 608 147, 0x00000000, 609 148, 0x00000000, 610 149, 0x00000000, 611 150, 0x00000000, 612 152, 0x00000000, 613 153, 0x00000000, 614 155, 0x00000000, 615 156, 0x00000000, 616 157, 0x01000200, 617 158, 0x02000040, 618 159, 0x00400100, 619 160, 0x00000200, 620 161, 0x00000040, 621 162, 0x00000000, 622 163, 0x01000000, 623 164, 0x0a020101, 624 165, 0x0101ffff, 625 166, 0x01010101, 626 167, 0x01010101, 627 168, 0x00000103, 628 169, 0x00000c03, 629 170, 0x00000000, 630 171, 0x00000000, 631 172, 0x01000000, 632 173, 0x00000100, 633 174, 0x00000000, 634 175, 0x00000000, 635 176, 0x00000000, 636 177, 0x00000000, 637 178, 0x00000000, 638 179, 0x00000000, 639 180, 0x00000000, 640 181, 0x00000000, 641 182, 0x00000000, 642 183, 0x00000000, 643 184, 0x00000000, 644 185, 0x00000000, 645 186, 0x00000000, 646 187, 0x00000000, 647 188, 0x00000000, 648 189, 0x00000000, 649 190, 0x00000000, 650 191, 0x00000000, 651 192, 0x00000000, 652 193, 0x00000000, 653 194, 0x00000000, 654 195, 0x00000000, 655 196, 0x01010200, 656 197, 0x00000002, 657 198, 0x06040400, 658 199, 0x00000106, 659 200, 0x01010000, 660 201, 0x02020002, 661 202, 0x02020101, 662 203, 0x02000102, 663 204, 0x00000000, 664 205, 0x00000000, 665 206, 0x00000000, 666 207, 0x00000000, 667 208, 0x00000000, 668 209, 0x0000280d, 669 210, 0x00010000, 670 211, 0x00010000, 671 212, 0x00000003, 672 213, 0x00000000, 673 214, 0x00000000, 674 215, 0x00000000, 675 216, 0x00000000, 676 217, 0x00000000, 677 218, 0x00000000, 678 219, 0x00000000, 679 220, 0x00000000, 680 221, 0x01000000, 681 222, 0x00000001, 682 223, 0x00000100, 683 224, 0x00030300, 684 225, 0x0556AA00, 685 226, 0x000aa955, 686 227, 0x000aa955, 687 228, 0x000556aa, 688 229, 0x000556aa, 689 230, 0x000aa955, 690 231, 0x000aa955, 691 232, 0x030556aa, 692 233, 0x01000001, 693 234, 0x00010300, 694 235, 0x00676700, 695 236, 0x00676700, 696 237, 0x00676700, 697 238, 0x00676700, 698 239, 0x00676700, 699 240, 0x00676700, 700 241, 0x00676700, 701 242, 0x00676700, 702 243, 0x00676700, 703 245, 0x01000000, 704 246, 0x00000001, 705 247, 0x00000101, 706 248, 0x00010100, 707 249, 0x03000000, 708 250, 0x03030303, 709 251, 0x00030303, 710 252, 0x02020064, 711 253, 0x02020202, 712 254, 0x00010202, 713 255, 0x01010064, 714 256, 0x01010101, 715 257, 0x00020101, 716 258, 0x00000064, 717 259, 0x00000000, 718 260, 0x000d0d00, 719 261, 0x00000000, 720 262, 0x00001850, 721 263, 0x02000200, 722 264, 0x02000200, 723 265, 0x00001850, 724 266, 0x00007990, 725 267, 0x00000404, 726 268, 0x00001850, 727 269, 0x02000200, 728 270, 0x02000200, 729 271, 0x00001850, 730 272, 0x00007990, 731 273, 0x02020404, 732 274, 0x000a0100, 733 275, 0x0000000a, 734 276, 0x00000000, 735 277, 0x00000000, 736 278, 0x00000f0a, 737 279, 0x00000000, 738 280, 0x00000000, 739 281, 0x00000000, 740 282, 0x00000000, 741 283, 0x00000000, 742 284, 0x00000103, 743 285, 0x00010003, 744 286, 0x00000003, 745 287, 0x00000000, 746 288, 0x00000000, 747 289, 0x00000000, 748 290, 0x05000000, 749 291, 0x00040504, 750 292, 0x00000000, 751 293, 0x00000000, 752 294, 0x00000000, 753 295, 0x00000000, 754 296, 0x00000000, 755 297, 0x00000000, 756 298, 0x00000000, 757 299, 0x00000000, 758 300, 0x00000000, 759 301, 0x00000000, 760 302, 0x00000000, 761 303, 0x00000000, 762 304, 0x00000000, 763 0xffffffff 764 }; 765 unsigned int gh_ddr3_init_tab_1333[] = { 766 0, 0x00000600, 767 1, 0x00000000, 768 2, 0x00000000, 769 3, 0x00000000, 770 4, 0x00000000, 771 5, 0x00000000, 772 6, 0x00000000, 773 7, 0x00000700, 774 8, 0x00000000, 775 9, 0x00000000, 776 10, 0x00000000, 777 11, 0x00000007, 778 12, 0x00000000, 779 13, 0x00000000, 780 14, 0x01000000, 781 15, 0x00000086, 782 16, 0x0000014e, 783 17, 0x00000000, 784 18, 0x02000000, 785 19, 0x00071200, 786 20, 0x00000000, 787 21, 0x00071200, 788 22, 0x00000000, 789 23, 0x05040400, 790 24, 0x18210005, 791 25, 0x1e090505, 792 26, 0x21000505, 793 27, 0x09050518, 794 28, 0x0405051e, 795 29, 0x00b6d00c, 796 30, 0x050c0504, 797 31, 0x000c0405, 798 32, 0x0400b6d0, 799 33, 0x09000c05, 800 34, 0x000a090a, 801 35, 0x010c0064, 802 36, 0x0a140a0a, 803 37, 0x0100000a, 804 38, 0x13130101, 805 39, 0x00090903, 806 40, 0x00010100, 807 41, 0x00000000, 808 42, 0x00000000, 809 43, 0x00ea0100, 810 44, 0x00001448, 811 45, 0x000000ea, 812 46, 0x00001448, 813 47, 0x00000005, 814 48, 0x00040004, 815 49, 0x00100010, 816 50, 0x00000000, 817 51, 0x00000000, 818 52, 0x02000000, 819 53, 0x020000f0, 820 54, 0x000000f0, 821 55, 0x07000001, 822 56, 0x00070707, 823 57, 0x00000000, 824 58, 0x00000000, 825 59, 0x00010000, 826 60, 0x10040010, 827 61, 0x00000400, 828 62, 0x00000200, 829 63, 0x00000000, 830 64, 0x00000001, 831 65, 0x00000000, 832 66, 0x00000000, 833 67, 0x00000000, 834 68, 0x00000000, 835 69, 0x00000000, 836 70, 0x00000000, 837 71, 0x00000000, 838 72, 0x00000000, 839 73, 0x00000000, 840 74, 0x00000000, 841 75, 0x00000000, 842 76, 0x00000000, 843 77, 0x00000000, 844 78, 0x00000000, 845 79, 0x00000000, 846 80, 0x00000000, 847 81, 0x00000000, 848 82, 0x00000000, 849 83, 0x00000000, 850 84, 0x00000a50, 851 85, 0x00000046, 852 86, 0x00000010, 853 87, 0x00000a50, 854 88, 0x00000046, 855 89, 0x00000010, 856 90, 0x00000000, 857 92, 0x00000000, 858 93, 0x00000000, 859 94, 0x00000000, 860 95, 0x00000000, 861 96, 0x00000000, 862 97, 0x00000000, 863 98, 0x00000a50, 864 99, 0x00000046, 865 100, 0x00000010, 866 101, 0x00000a50, 867 102, 0x00000046, 868 103, 0x00000010, 869 104, 0x00000000, 870 106, 0x00000000, 871 107, 0x00000000, 872 108, 0x00000000, 873 109, 0x00000000, 874 110, 0x00000000, 875 111, 0x00000000, 876 139, 0x00000000, 877 140, 0x01000000, 878 141, 0x00000001, 879 142, 0x00000000, 880 143, 0x00000000, 881 144, 0x00000000, 882 145, 0x00000000, 883 146, 0x00000000, 884 147, 0x00000000, 885 148, 0x00000000, 886 149, 0x00000000, 887 150, 0x00000000, 888 152, 0x00000000, 889 153, 0x00000000, 890 155, 0x00000000, 891 156, 0x00000000, 892 157, 0x01000200, 893 158, 0x02000040, 894 159, 0x00400100, 895 160, 0x00000200, 896 161, 0x00000040, 897 162, 0x00000000, 898 163, 0x01000000, 899 164, 0x0a020101, 900 165, 0x0101ffff, 901 166, 0x01010101, 902 167, 0x01010101, 903 168, 0x00000103, 904 169, 0x00000c03, 905 170, 0x00000000, 906 171, 0x00000000, 907 172, 0x01000000, 908 173, 0x00000100, 909 174, 0x00000000, 910 175, 0x00000000, 911 176, 0x00000000, 912 177, 0x00000000, 913 178, 0x00000000, 914 179, 0x00000000, 915 180, 0x00000000, 916 181, 0x00000000, 917 182, 0x00000000, 918 183, 0x00000000, 919 184, 0x00000000, 920 185, 0x00000000, 921 186, 0x00000000, 922 187, 0x00000000, 923 188, 0x00000000, 924 189, 0x00000000, 925 190, 0x00000000, 926 191, 0x00000000, 927 192, 0x00000000, 928 193, 0x00000000, 929 194, 0x00000000, 930 195, 0x00000000, 931 196, 0x01010200, 932 197, 0x00000002, 933 198, 0x06060600, 934 199, 0x00000106, 935 200, 0x02020000, 936 201, 0x02020002, 937 202, 0x02020101, 938 203, 0x02000102, 939 204, 0x00000000, 940 205, 0x00000000, 941 206, 0x00000000, 942 207, 0x00000000, 943 208, 0x00000000, 944 209, 0x0000280d, 945 210, 0x00010000, 946 211, 0x00010000, 947 212, 0x00000003, 948 213, 0x00000000, 949 214, 0x00000000, 950 215, 0x00000000, 951 216, 0x00000000, 952 217, 0x00000000, 953 218, 0x00000000, 954 219, 0x00000000, 955 220, 0x00000000, 956 221, 0x01000000, 957 222, 0x00000001, 958 223, 0x00000100, 959 224, 0x00030300, 960 225, 0x0556AA00, 961 226, 0x000aa955, 962 227, 0x000aa955, 963 228, 0x000556aa, 964 229, 0x000556aa, 965 230, 0x000aa955, 966 231, 0x000aa955, 967 232, 0x030556aa, 968 233, 0x01000001, 969 234, 0x00010300, 970 235, 0x00676700, 971 236, 0x00676700, 972 237, 0x00676700, 973 238, 0x00676700, 974 239, 0x00676700, 975 240, 0x00676700, 976 241, 0x00676700, 977 242, 0x00676700, 978 243, 0x00676700, 979 245, 0x01000000, 980 246, 0x00000001, 981 247, 0x00000101, 982 248, 0x00010100, 983 249, 0x03000000, 984 250, 0x03030303, 985 251, 0x00030303, 986 252, 0x02020064, 987 253, 0x02020202, 988 254, 0x00010202, 989 255, 0x01010064, 990 256, 0x01010101, 991 257, 0x00020101, 992 258, 0x00000064, 993 259, 0x00000000, 994 260, 0x000e0e00, 995 261, 0x00000000, 996 262, 0x00002890, 997 263, 0x02000200, 998 264, 0x02000200, 999 265, 0x00002890, 1000 266, 0x0000cad0, 1001 267, 0x00000708, 1002 268, 0x00002890, 1003 269, 0x02000200, 1004 270, 0x02000200, 1005 271, 0x00002890, 1006 272, 0x0000cad0, 1007 273, 0x02020708, 1008 274, 0x000a0100, 1009 275, 0x0000000a, 1010 276, 0x00000000, 1011 277, 0x00000000, 1012 278, 0x00000f0a, 1013 279, 0x00000000, 1014 280, 0x00000000, 1015 281, 0x00000000, 1016 282, 0x00000000, 1017 283, 0x00000000, 1018 284, 0x00000103, 1019 285, 0x00010003, 1020 286, 0x00000003, 1021 287, 0x00000000, 1022 288, 0x00000000, 1023 289, 0x00000000, 1024 290, 0x08000000, 1025 291, 0x00060806, 1026 292, 0x00000000, 1027 293, 0x00000000, 1028 294, 0x00000000, 1029 295, 0x00000000, 1030 296, 0x00000000, 1031 297, 0x00000000, 1032 298, 0x00000000, 1033 299, 0x00000000, 1034 300, 0x00000000, 1035 301, 0x00000000, 1036 302, 0x00000000, 1037 303, 0x00000000, 1038 304, 0x00000000, 1039 0xffffffff 1040 }; 1041 1042 unsigned int gh_ddr3_init_tab_1600[] = { 1043 0, 0x00000600, 1044 1, 0x00000000, 1045 2, 0x00000000, 1046 3, 0x00000000, 1047 4, 0x00000000, 1048 5, 0x00000000, 1049 6, 0x00000000, 1050 7, 0x00000800, 1051 8, 0x00000000, 1052 9, 0x00000000, 1053 10, 0x00000000, 1054 11, 0x00000008, 1055 12, 0x00000000, 1056 13, 0x00000000, 1057 14, 0x01000000, 1058 15, 0x000000a0, 1059 16, 0x00000190, 1060 17, 0x00000000, 1061 18, 0x02000000, 1062 19, 0x00081600, 1063 20, 0x00000000, 1064 21, 0x00081600, 1065 22, 0x00000000, 1066 23, 0x05040400, 1067 24, 0x1c270006, 1068 25, 0x200b0607, 1069 26, 0x27000605, 1070 27, 0x0b06061c, 1071 28, 0x04060620, 1072 29, 0x00db600c, 1073 30, 0x060c0504, 1074 31, 0x000c0406, 1075 32, 0x0400db60, 1076 33, 0x0b000c05, 1077 34, 0x000c0b0c, 1078 35, 0x010c0078, 1079 36, 0x0a140a0a, 1080 37, 0x0100000a, 1081 38, 0x17170101, 1082 39, 0x000b0b03, 1083 40, 0x00010100, 1084 41, 0x00000000, 1085 42, 0x00000000, 1086 43, 0x01180100, 1087 44, 0x00001858, 1088 45, 0x00000118, 1089 46, 0x00001858, 1090 47, 0x00000005, 1091 48, 0x00050005, 1092 49, 0x00140014, 1093 50, 0x00000000, 1094 51, 0x00000000, 1095 52, 0x02000000, 1096 53, 0x02000120, 1097 54, 0x00000120, 1098 55, 0x08000001, 1099 56, 0x00080808, 1100 57, 0x00000000, 1101 58, 0x00000000, 1102 59, 0x00010000, 1103 60, 0x10040010, 1104 61, 0x00000400, 1105 62, 0x00000200, 1106 63, 0x00000000, 1107 64, 0x00000001, 1108 65, 0x00000000, 1109 66, 0x00000000, 1110 67, 0x00000000, 1111 68, 0x00000000, 1112 69, 0x00000000, 1113 70, 0x00000000, 1114 71, 0x00000000, 1115 72, 0x00000000, 1116 73, 0x00000000, 1117 74, 0x00000000, 1118 75, 0x00000000, 1119 76, 0x00000000, 1120 77, 0x00000000, 1121 78, 0x00000000, 1122 79, 0x00000000, 1123 80, 0x00000000, 1124 81, 0x00000000, 1125 82, 0x00000000, 1126 83, 0x00000000, 1127 84, 0x00000c70, 1128 85, 0x00000046, 1129 86, 0x00000018, 1130 87, 0x00000c70, 1131 88, 0x00000046, 1132 89, 0x00000018, 1133 90, 0x00000000, 1134 92, 0x00000000, 1135 93, 0x00000000, 1136 94, 0x00000000, 1137 95, 0x00000000, 1138 96, 0x00000000, 1139 97, 0x00000000, 1140 98, 0x00000c70, 1141 99, 0x00000046, 1142 100, 0x00000018, 1143 101, 0x00000c70, 1144 102, 0x00000046, 1145 103, 0x00000018, 1146 104, 0x00000000, 1147 106, 0x00000000, 1148 107, 0x00000000, 1149 108, 0x00000000, 1150 109, 0x00000000, 1151 110, 0x00000000, 1152 111, 0x00000000, 1153 139, 0x00000000, 1154 140, 0x01000000, 1155 141, 0x00000001, 1156 142, 0x00000000, 1157 143, 0x00000000, 1158 144, 0x00000000, 1159 145, 0x00000000, 1160 146, 0x00000000, 1161 147, 0x00000000, 1162 148, 0x00000000, 1163 149, 0x00000000, 1164 150, 0x00000000, 1165 152, 0x00000000, 1166 153, 0x00000000, 1167 155, 0x00000000, 1168 156, 0x00000000, 1169 157, 0x01000200, 1170 158, 0x02000040, 1171 159, 0x00400100, 1172 160, 0x00000200, 1173 161, 0x00000040, 1174 162, 0x00000000, 1175 163, 0x01000000, 1176 164, 0x0a020101, 1177 165, 0x0101ffff, 1178 166, 0x01010101, 1179 167, 0x01010101, 1180 168, 0x00000103, 1181 169, 0x00000c03, 1182 170, 0x00000000, 1183 171, 0x00000000, 1184 172, 0x01000000, 1185 173, 0x00000100, 1186 174, 0x00000000, 1187 175, 0x00000000, 1188 176, 0x00000000, 1189 177, 0x00000000, 1190 178, 0x00000000, 1191 179, 0x00000000, 1192 180, 0x00000000, 1193 181, 0x00000000, 1194 182, 0x00000000, 1195 183, 0x00000000, 1196 184, 0x00000000, 1197 185, 0x00000000, 1198 186, 0x00000000, 1199 187, 0x00000000, 1200 188, 0x00000000, 1201 189, 0x00000000, 1202 190, 0x00000000, 1203 191, 0x00000000, 1204 192, 0x00000000, 1205 193, 0x00000000, 1206 194, 0x00000000, 1207 195, 0x00000000, 1208 196, 0x01010200, 1209 197, 0x00000002, 1210 198, 0x06070700, 1211 199, 0x00000106, 1212 200, 0x03030000, 1213 201, 0x02020002, 1214 202, 0x02020101, 1215 203, 0x02000102, 1216 204, 0x00000000, 1217 205, 0x00000000, 1218 206, 0x00000000, 1219 207, 0x00000000, 1220 208, 0x00000000, 1221 209, 0x0000280d, 1222 210, 0x00010000, 1223 211, 0x00010000, 1224 212, 0x00000003, 1225 213, 0x00000000, 1226 214, 0x00000000, 1227 215, 0x00000000, 1228 216, 0x00000000, 1229 217, 0x00000000, 1230 218, 0x00000000, 1231 219, 0x00000000, 1232 220, 0x00000000, 1233 221, 0x01000000, 1234 222, 0x00000001, 1235 223, 0x00000100, 1236 224, 0x00030300, 1237 225, 0x0556AA00, 1238 226, 0x000aa955, 1239 227, 0x000aa955, 1240 228, 0x000556aa, 1241 229, 0x000556aa, 1242 230, 0x000aa955, 1243 231, 0x000aa955, 1244 232, 0x030556aa, 1245 233, 0x01000001, 1246 234, 0x00010300, 1247 235, 0x00676700, 1248 236, 0x00676700, 1249 237, 0x00676700, 1250 238, 0x00676700, 1251 239, 0x00676700, 1252 240, 0x00676700, 1253 241, 0x00676700, 1254 242, 0x00676700, 1255 243, 0x00676700, 1256 245, 0x01000000, 1257 246, 0x00000001, 1258 247, 0x00000101, 1259 248, 0x00010100, 1260 249, 0x03000000, 1261 250, 0x03030303, 1262 251, 0x00030303, 1263 252, 0x02020064, 1264 253, 0x02020202, 1265 254, 0x00010202, 1266 255, 0x01010064, 1267 256, 0x01010101, 1268 257, 0x00020101, 1269 258, 0x00000064, 1270 259, 0x00000000, 1271 260, 0x000e0e00, 1272 261, 0x00000000, 1273 262, 0x000030b0, 1274 263, 0x02000200, 1275 264, 0x02000200, 1276 265, 0x000030b0, 1277 266, 0x0000f370, 1278 267, 0x0000080a, 1279 268, 0x000030b0, 1280 269, 0x02000200, 1281 270, 0x02000200, 1282 271, 0x000030b0, 1283 272, 0x0000f370, 1284 273, 0x0202080a, 1285 274, 0x000a0100, 1286 275, 0x0000000a, 1287 276, 0x00000000, 1288 277, 0x00000000, 1289 278, 0x00000f0a, 1290 279, 0x00000000, 1291 280, 0x00000000, 1292 281, 0x00000000, 1293 282, 0x00000000, 1294 283, 0x00000000, 1295 284, 0x00000103, 1296 285, 0x00010003, 1297 286, 0x00000003, 1298 287, 0x00000000, 1299 288, 0x00000000, 1300 289, 0x00000000, 1301 290, 0x0a000000, 1302 291, 0x00070a07, 1303 292, 0x00000000, 1304 293, 0x00000000, 1305 294, 0x00000000, 1306 295, 0x00000000, 1307 296, 0x00000000, 1308 297, 0x00000000, 1309 298, 0x00000000, 1310 299, 0x00000000, 1311 300, 0x00000000, 1312 301, 0x00000000, 1313 302, 0x00000000, 1314 303, 0x00000000, 1315 304, 0x00000000, 1316 0xffffffff 1317 }; 1318 #endif /* BCM_GREYHOUND_SUPPORT */ 1319 1320 #ifdef BCM_HURRICANE3_SUPPORT 1321 1322 unsigned int hr3_ddr4_init_tab_1600[] = { 1323 0, 0x00000a00, 1324 1, 0x00000000, 1325 2, 0x00000000, 1326 3, 0x00000000, 1327 4, 0x00000000, 1328 5, 0x00000000, 1329 6, 0x00000000, 1330 7, 0x00000800, 1331 8, 0x00000000, 1332 9, 0x00000000, 1333 10, 0x00000000, 1334 11, 0x00000008, 1335 12, 0x00000000, 1336 13, 0x00000000, 1337 14, 0x01000000, 1338 15, 0x00027100, 1339 16, 0x00061a80, 1340 17, 0x00000000, 1341 18, 0x03000000, 1342 19, 0x00091600, 1343 20, 0x0e1c1c04, 1344 21, 0x0009168c, 1345 22, 0x0e1c1c04, 1346 23, 0x0604048c, 1347 24, 0x1b270504, 1348 25, 0x110c0602, 1349 26, 0x27050406, 1350 27, 0x0c06021b, 1351 28, 0x08060611, 1352 29, 0x00db6018, 1353 30, 0x06180904, 1354 31, 0x00180806, 1355 32, 0x0400db60, 1356 33, 0x0c001809, 1357 34, 0x000c0c0c, 1358 35, 0x01180078, 1359 36, 0x0a140a0a, 1360 37, 0x0100000a, 1361 38, 0x18180101, 1362 39, 0x000d0d03, 1363 40, 0x00010100, 1364 41, 0x00000000, 1365 42, 0x00000000, 1366 43, 0x00d00100, 1367 44, 0x00001860, 1368 45, 0x000000d0, 1369 46, 0x00001860, 1370 47, 0x00000005, 1371 48, 0x00050005, 1372 49, 0x00140014, 1373 50, 0x00000000, 1374 51, 0x00000000, 1375 52, 0x03000000, 1376 53, 0x030000d8, 1377 54, 0x000000d8, 1378 55, 0x0c000001, 1379 56, 0x00080c08, 1380 57, 0x00000000, 1381 58, 0x00000000, 1382 59, 0x00010000, 1383 60, 0x10040010, 1384 61, 0x00000400, 1385 62, 0x00000200, 1386 63, 0x00000000, 1387 64, 0x00000001, 1388 65, 0x00000000, 1389 66, 0x00000000, 1390 67, 0x00000000, 1391 68, 0x00000000, 1392 69, 0x00000000, 1393 70, 0x00000000, 1394 71, 0x00000000, 1395 72, 0x00000000, 1396 73, 0x00000000, 1397 74, 0x00000000, 1398 75, 0x00000000, 1399 76, 0x00000000, 1400 77, 0x00000000, 1401 78, 0x00000000, 1402 79, 0x00000000, 1403 80, 0x00000000, 1404 81, 0x00000000, 1405 82, 0x00000000, 1406 83, 0x00000000, 1407 84, 0x00000210, 1408 85, 0x00000101, 1409 86, 0x00000000, 1410 87, 0x00000210, 1411 88, 0x00000101, 1412 89, 0x00000000, 1413 90, 0x00000000, 1414 92, 0x00000000, 1415 93, 0x00000441, 1416 94, 0x00000441, 1417 95, 0x00000410, 1418 96, 0x00000410, 1419 97, 0x00000000, 1420 98, 0x00000210, 1421 99, 0x00000101, 1422 100, 0x00000000, 1423 101, 0x00000210, 1424 102, 0x00000101, 1425 103, 0x00000000, 1426 104, 0x00000000, 1427 106, 0x00000000, 1428 107, 0x00000441, 1429 108, 0x00000441, 1430 109, 0x00000410, 1431 110, 0x00000410, 1432 111, 0x00000000, 1433 139, 0x00000000, 1434 140, 0x01000000, 1435 141, 0x00000001, 1436 142, 0x00000000, 1437 143, 0x00000000, 1438 144, 0x00000000, 1439 145, 0x00000000, 1440 146, 0x00000000, 1441 147, 0x00000000, 1442 148, 0x00000000, 1443 149, 0x00000000, 1444 150, 0x00000000, 1445 152, 0x00000000, 1446 153, 0x00000000, 1447 155, 0x00000000, 1448 156, 0x00000000, 1449 157, 0x02000400, 1450 158, 0x04000080, 1451 159, 0x00800200, 1452 160, 0x00000200, 1453 161, 0x00000040, 1454 162, 0x00000000, 1455 163, 0x01000000, 1456 164, 0x0a020100, 1457 165, 0x0101ffff, 1458 166, 0x01010101, 1459 167, 0x01010101, 1460 168, 0x00000103, 1461 169, 0x00000c03, 1462 #ifdef CONFIG_DDR32 1463 170, 0x00000000, 1464 #else 1465 170, 0x00000001, 1466 #endif 1467 171, 0x00000000, 1468 172, 0x01000000, 1469 173, 0x00000100, 1470 174, 0x01000000, 1471 175, 0x00000000, 1472 176, 0x00000000, 1473 177, 0x00000000, 1474 178, 0x00000000, 1475 179, 0x00000000, 1476 180, 0x00000000, 1477 181, 0x00000000, 1478 182, 0x00000000, 1479 183, 0x00000000, 1480 184, 0x00000000, 1481 185, 0x00000000, 1482 186, 0x00000000, 1483 187, 0x00000000, 1484 188, 0x00000000, 1485 189, 0x00000000, 1486 190, 0x00000000, 1487 191, 0x00000000, 1488 192, 0x00000000, 1489 193, 0x00000000, 1490 194, 0x00000000, 1491 195, 0x00000000, 1492 196, 0x01010200, 1493 197, 0x00000002, 1494 198, 0x06080800, 1495 199, 0x00000106, 1496 200, 0x02020000, 1497 201, 0x00000000, 1498 202, 0x02020202, 1499 203, 0x02000202, 1500 204, 0x00000000, 1501 205, 0x00000000, 1502 206, 0x00000000, 1503 207, 0x00000000, 1504 208, 0x00000000, 1505 209, 0x0000280d, 1506 210, 0x00010000, 1507 211, 0x00010000, 1508 212, 0x00000003, 1509 213, 0x00000000, 1510 214, 0x00000000, 1511 215, 0x00000000, 1512 216, 0x00000000, 1513 217, 0x00000000, 1514 218, 0x00000000, 1515 219, 0x00000000, 1516 220, 0x00000000, 1517 221, 0x01000000, 1518 222, 0x00000001, 1519 223, 0x00000100, 1520 224, 0x00030300, 1521 225, 0x0556AA00, 1522 226, 0x000aa955, 1523 227, 0x000aa955, 1524 228, 0x000556aa, 1525 229, 0x000556aa, 1526 230, 0x000aa955, 1527 231, 0x000aa955, 1528 232, 0x030556aa, 1529 233, 0x01000001, 1530 234, 0x00010300, 1531 235, 0x00676700, 1532 236, 0x00676700, 1533 237, 0x00676700, 1534 238, 0x00676700, 1535 239, 0x00676700, 1536 240, 0x00676700, 1537 241, 0x00676700, 1538 242, 0x00676700, 1539 243, 0x00676700, 1540 245, 0x01000000, 1541 246, 0x00000001, 1542 247, 0x00000101, 1543 248, 0x00010100, 1544 249, 0x03000000, 1545 250, 0x03030303, 1546 251, 0x00030303, 1547 252, 0x02020064, 1548 253, 0x02020202, 1549 254, 0x00010202, 1550 255, 0x01010064, 1551 256, 0x01010101, 1552 257, 0x00020101, 1553 258, 0x00000064, 1554 259, 0x00000000, 1555 260, 0x000e0e00, 1556 261, 0x00000000, 1557 262, 0x000030c0, 1558 263, 0x02000200, 1559 264, 0x02000200, 1560 265, 0x000030c0, 1561 266, 0x0000f3c0, 1562 267, 0x00000d0e, 1563 268, 0x000030c0, 1564 269, 0x02000200, 1565 270, 0x02000200, 1566 271, 0x000030c0, 1567 272, 0x0000f3c0, 1568 273, 0x02020d0e, 1569 274, 0x000a0100, 1570 275, 0x0000000a, 1571 276, 0x00000000, 1572 277, 0x00000000, 1573 278, 0x00000f0a, 1574 279, 0x00000000, 1575 280, 0x00000000, 1576 281, 0x00000000, 1577 282, 0x00000000, 1578 283, 0x00000000, 1579 284, 0x00000103, 1580 285, 0x00010003, 1581 286, 0x00000003, 1582 287, 0x00000000, 1583 288, 0x00000000, 1584 289, 0x00000000, 1585 290, 0x0a000000, 1586 291, 0x00080a08, 1587 292, 0x00000000, 1588 293, 0x00000000, 1589 294, 0x00000000, 1590 295, 0x00000000, 1591 296, 0x00000000, 1592 297, 0x00000820, 1593 298, 0x00000820, 1594 299, 0x00000820, 1595 300, 0x00000820, 1596 301, 0x00000000, 1597 302, 0x00000000, 1598 303, 0x00000000, 1599 304, 0x00000000, 1600 0xffffffff 1601 }; 1602 1603 unsigned int hr3_ddr3_init_tab_1600[] = { 1604 0, 0x00000600, 1605 1, 0x00000000, 1606 2, 0x00000000, 1607 3, 0x00000000, 1608 4, 0x00000000, 1609 5, 0x00000000, 1610 6, 0x00000000, 1611 7, 0x00000800, 1612 8, 0x00000000, 1613 9, 0x00000000, 1614 10, 0x00000000, 1615 11, 0x00000008, 1616 12, 0x00000000, 1617 13, 0x00000000, 1618 14, 0x01000000, 1619 15, 0x000000a0, 1620 16, 0x00000190, 1621 17, 0x00000000, 1622 18, 0x02000000, 1623 19, 0x00081600, 1624 20, 0x00000000, 1625 21, 0x00081600, 1626 22, 0x00000000, 1627 23, 0x05040400, 1628 24, 0x1c270006, 1629 25, 0x200b0607, 1630 26, 0x27000605, 1631 27, 0x0b06061c, 1632 28, 0x04060620, 1633 29, 0x00db600c, 1634 30, 0x060c0504, 1635 31, 0x000c0406, 1636 32, 0x0400db60, 1637 33, 0x0b000c05, 1638 34, 0x000c0b0c, 1639 35, 0x010c0078, 1640 36, 0x0a140a0a, 1641 37, 0x0100000a, 1642 38, 0x17170101, 1643 39, 0x000b0b03, 1644 40, 0x00010100, 1645 41, 0x00000000, 1646 42, 0x00000000, 1647 43, 0x01180100, 1648 44, 0x00001858, 1649 45, 0x00000118, 1650 46, 0x00001858, 1651 47, 0x00000005, 1652 48, 0x00050005, 1653 49, 0x00140014, 1654 50, 0x00000000, 1655 51, 0x00000000, 1656 52, 0x02000000, 1657 53, 0x02000120, 1658 54, 0x00000120, 1659 55, 0x08000001, 1660 56, 0x00080808, 1661 57, 0x00000000, 1662 58, 0x00000000, 1663 59, 0x00010000, 1664 60, 0x10040010, 1665 61, 0x00000400, 1666 62, 0x00000200, 1667 63, 0x00000000, 1668 64, 0x00000001, 1669 65, 0x00000000, 1670 66, 0x00000000, 1671 67, 0x00000000, 1672 68, 0x00000000, 1673 69, 0x00000000, 1674 70, 0x00000000, 1675 71, 0x00000000, 1676 72, 0x00000000, 1677 73, 0x00000000, 1678 74, 0x00000000, 1679 75, 0x00000000, 1680 76, 0x00000000, 1681 77, 0x00000000, 1682 78, 0x00000000, 1683 79, 0x00000000, 1684 80, 0x00000000, 1685 81, 0x00000000, 1686 82, 0x00000000, 1687 83, 0x00000000, 1688 84, 0x00000c70, 1689 85, 0x00000046, 1690 86, 0x00000018, 1691 87, 0x00000c70, 1692 88, 0x00000046, 1693 89, 0x00000018, 1694 90, 0x00000000, 1695 92, 0x00000000, 1696 93, 0x00000000, 1697 94, 0x00000000, 1698 95, 0x00000000, 1699 96, 0x00000000, 1700 97, 0x00000000, 1701 98, 0x00000c70, 1702 99, 0x00000046, 1703 100, 0x00000018, 1704 101, 0x00000c70, 1705 102, 0x00000046, 1706 103, 0x00000018, 1707 104, 0x00000000, 1708 106, 0x00000000, 1709 107, 0x00000000, 1710 108, 0x00000000, 1711 109, 0x00000000, 1712 110, 0x00000000, 1713 111, 0x00000000, 1714 139, 0x00000000, 1715 140, 0x01000000, 1716 141, 0x00000001, 1717 142, 0x00000000, 1718 143, 0x00000000, 1719 144, 0x00000000, 1720 145, 0x00000000, 1721 146, 0x00000000, 1722 147, 0x00000000, 1723 148, 0x00000000, 1724 149, 0x00000000, 1725 150, 0x00000000, 1726 152, 0x00000000, 1727 153, 0x00000000, 1728 155, 0x00000000, 1729 156, 0x00000000, 1730 157, 0x01000200, 1731 158, 0x02000040, 1732 159, 0x00400100, 1733 160, 0x00000200, 1734 161, 0x00000040, 1735 162, 0x00000000, 1736 163, 0x01000000, 1737 164, 0x0a020101, 1738 165, 0x0101ffff, 1739 166, 0x01010101, 1740 167, 0x01010101, 1741 168, 0x00000103, 1742 169, 0x00000c03, 1743 170, 0x00000001, /* 0 if DDR32 */ 1744 171, 0x00000000, 1745 172, 0x01000000, 1746 173, 0x00000100, 1747 174, 0x00000000, 1748 175, 0x00000000, 1749 176, 0x00000000, 1750 177, 0x00000000, 1751 178, 0x00000000, 1752 179, 0x00000000, 1753 180, 0x00000000, 1754 181, 0x00000000, 1755 182, 0x00000000, 1756 183, 0x00000000, 1757 184, 0x00000000, 1758 185, 0x00000000, 1759 186, 0x00000000, 1760 187, 0x00000000, 1761 188, 0x00000000, 1762 189, 0x00000000, 1763 190, 0x00000000, 1764 191, 0x00000000, 1765 192, 0x00000000, 1766 193, 0x00000000, 1767 194, 0x00000000, 1768 195, 0x00000000, 1769 196, 0x01010200, 1770 197, 0x00000002, 1771 198, 0x06070700, 1772 199, 0x00000106, 1773 200, 0x03030000, 1774 201, 0x02020002, 1775 202, 0x02020101, 1776 203, 0x02000102, 1777 204, 0x00000000, 1778 205, 0x00000000, 1779 206, 0x00000000, 1780 207, 0x00000000, 1781 208, 0x00000000, 1782 209, 0x0000280d, 1783 210, 0x00010000, 1784 211, 0x00010000, 1785 212, 0x00000003, 1786 213, 0x00000000, 1787 214, 0x00000000, 1788 215, 0x00000000, 1789 216, 0x00000000, 1790 217, 0x00000000, 1791 218, 0x00000000, 1792 219, 0x00000000, 1793 220, 0x00000000, 1794 221, 0x01000000, 1795 222, 0x00000001, 1796 223, 0x00000100, 1797 224, 0x00030300, 1798 225, 0x0556AA00, 1799 226, 0x000aa955, 1800 227, 0x000aa955, 1801 228, 0x000556aa, 1802 229, 0x000556aa, 1803 230, 0x000aa955, 1804 231, 0x000aa955, 1805 232, 0x030556aa, 1806 233, 0x01000001, 1807 234, 0x00010300, 1808 235, 0x00676700, 1809 236, 0x00676700, 1810 237, 0x00676700, 1811 238, 0x00676700, 1812 239, 0x00676700, 1813 240, 0x00676700, 1814 241, 0x00676700, 1815 242, 0x00676700, 1816 243, 0x00676700, 1817 245, 0x01000000, 1818 246, 0x00000001, 1819 247, 0x00000101, 1820 248, 0x00010100, 1821 249, 0x03000000, 1822 250, 0x03030303, 1823 251, 0x00030303, 1824 252, 0x02020064, 1825 253, 0x02020202, 1826 254, 0x00010202, 1827 255, 0x01010064, 1828 256, 0x01010101, 1829 257, 0x00020101, 1830 258, 0x00000064, 1831 259, 0x00000000, 1832 260, 0x000e0e00, 1833 261, 0x00000000, 1834 262, 0x000030b0, 1835 263, 0x02000200, 1836 264, 0x02000200, 1837 265, 0x000030b0, 1838 266, 0x0000f370, 1839 267, 0x0000080a, 1840 268, 0x000030b0, 1841 269, 0x02000200, 1842 270, 0x02000200, 1843 271, 0x000030b0, 1844 272, 0x0000f370, 1845 273, 0x0202080a, 1846 274, 0x000a0100, 1847 275, 0x0000000a, 1848 276, 0x00000000, 1849 277, 0x00000000, 1850 278, 0x00000f0a, 1851 279, 0x00000000, 1852 280, 0x00000000, 1853 281, 0x00000000, 1854 282, 0x00000000, 1855 283, 0x00000000, 1856 284, 0x00000103, 1857 285, 0x00010003, 1858 286, 0x00000003, 1859 287, 0x00000000, 1860 288, 0x00000000, 1861 289, 0x00000000, 1862 290, 0x0a000000, 1863 291, 0x00070a07, 1864 292, 0x00000000, 1865 293, 0x00000000, 1866 294, 0x00000000, 1867 295, 0x00000000, 1868 296, 0x00000000, 1869 297, 0x00000000, 1870 298, 0x00000000, 1871 299, 0x00000000, 1872 300, 0x00000000, 1873 301, 0x00000000, 1874 302, 0x00000000, 1875 303, 0x00000000, 1876 304, 0x00000000, 1877 0xffffffff 1878 }; 1879 #endif /* BCM_HURRICANE3_SUPPORT */ 1880 1881 1882 #if defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_HURRICANE3_SUPPORT) 1883 STATIC uint32 1884 _get_random28(void) 1885 { 1886 static uint32 m_w = 6483; /* must not be zero */ 1887 static uint32 m_z = 31245; /* must not be zero */ 1888 1889 m_z = 36969 * (m_z & 65535) + (m_z >> 16); 1890 m_w = 18000 * (m_w & 65535) + (m_w >> 16); 1891 return (m_z << 16) + m_w; /* 32-bit result */ 1892 } 1893 #endif /* BCM_GREYHOUND_SUPPORT || BCM_HURRICANE3_SUPPORT */ 1894 1895 1896 /* 1897 * Function: 1898 * soc_iproc_ddr_reg_table_init 1899 * Purpose: 1900 * Initialize DDR registers based on the supplied table 1901 * Parameters: 1902 * unit - unit number 1903 * Returns: 1904 * SOC_E_XXX 1905 */ 1906 STATIC int 1907 soc_iproc_ddr_reg_table_init(int unit, int start, const unsigned int *tblptr) 1908 { 1909 int rv; 1910 uint32 base; 1911 unsigned int offset; 1912 1913 if (tblptr == NULL) { 1914 return SOC_E_PARAM; 1915 } 1916 1917 /* Get register base address */ 1918 base = soc_reg_addr(unit, start, REG_PORT_ANY, 0); 1919 1920 offset = *tblptr; 1921 while(offset != 0xffffffff) { 1922 tblptr++; 1923 rv = soc_iproc_setreg(unit, base + offset * 4, *tblptr); 1924 if (rv != SOC_E_NONE) { 1925 return rv; 1926 } 1927 tblptr++; 1928 offset = *tblptr; 1929 } 1930 1931 return SOC_E_NONE; 1932 } 1933 1934 #ifdef BCM_HURRICANE2_SUPPORT 1935 /* 1936 * Function: 1937 * soc_iproc_hr2_ddr_init 1938 * Purpose: 1939 * Initialize DDR of the embedded iProc subsystem for Hurricane2 1940 * Parameters: 1941 * unit - unit number 1942 * Returns: 1943 * SOC_E_XXX 1944 */ 1945 STATIC int 1946 soc_iproc_hr2_ddr_init(int unit) 1947 { 1948 soc_timeout_t to; 1949 sal_usecs_t to_val; 1950 uint32 rval; 1951 1952 /* Skip if DDR has been already initialized */ 1953 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &rval)); 1954 if (soc_reg_field_get(unit, DDR_DENALI_CTL_00r, rval, STARTf) == 1) { 1955 return SOC_E_NONE; 1956 } 1957 1958 /* Set up default DDR configuration */ 1959 SOC_DDR3_CLOCK_MHZ(unit) = DDR_FREQ_400; 1960 SOC_DDR3_MEM_GRADE(unit) = 0; /* to use default */ 1961 1962 /* Bring DDR controller out of reset */ 1963 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 1964 DDR_S1_IDM_RESET_CONTROLr, REG_PORT_ANY, 1965 RESETf, 0)); 1966 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 1967 DDR_S2_IDM_RESET_CONTROLr, REG_PORT_ANY, 1968 RESETf, 0)); 1969 1970 /* Set default speed */ 1971 SOC_IF_ERROR_RETURN(READ_DDR_S1_IDM_IO_CONTROL_DIRECTr(unit, &rval)); 1972 soc_reg_field_set(unit, DDR_S1_IDM_IO_CONTROL_DIRECTr, &rval, 1973 I_PHY_DDR_MHZf, SOC_DDR3_CLOCK_MHZ(unit)); 1974 SOC_IF_ERROR_RETURN(WRITE_DDR_S1_IDM_IO_CONTROL_DIRECTr(unit, rval)); 1975 1976 /* Wait for PHY ready */ 1977 to_val = 50000; /* 50 mS */ 1978 soc_timeout_init(&to, to_val, 0); 1979 for(;;) { 1980 SOC_IF_ERROR_RETURN( 1981 READ_DDR_PHY_CONTROL_REGS_REVISIONr(unit, &rval)); 1982 if (rval != 0) { 1983 break; 1984 } 1985 if (soc_timeout_check(&to)) { 1986 LOG_ERROR(BSL_LS_SOC_COMMON, 1987 (BSL_META_U(unit, 1988 "Timed out waiting for PHY to be ready\n"))); 1989 1990 return SOC_E_TIMEOUT; 1991 } 1992 } 1993 1994 /* Set Strap and parameter per speed and grade */ 1995 SOC_IF_ERROR_RETURN( 1996 READ_DDR_PHY_CONTROL_REGS_STRAP_CONTROLr(unit, &rval)); 1997 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROLr, &rval, 1998 MHZf, SOC_DDR3_CLOCK_MHZ(unit)); 1999 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROLr, &rval, 2000 AD_WIDTHf, 3); 2001 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROLr, &rval, 2002 BUS16f, 1); 2003 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROLr, &rval, 2004 CHIP_WIDTHf, 1); 2005 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROLr, &rval, 2006 CHIP_SIZEf, 3); 2007 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROLr, &rval, 2008 JEDEC_TYPEf, 25); 2009 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROLr, &rval, 2010 STRAPS_VALIDf, 1); 2011 SOC_IF_ERROR_RETURN( 2012 WRITE_DDR_PHY_CONTROL_REGS_STRAP_CONTROLr(unit, rval)); 2013 SOC_IF_ERROR_RETURN( 2014 READ_DDR_PHY_CONTROL_REGS_STRAP_CONTROL2r(unit, &rval)); 2015 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROL2r, &rval, 2016 DDR3f, 1); 2017 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROL2r, &rval, 2018 ALf, 3); 2019 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROL2r, &rval, 2020 CWLf, 9); 2021 soc_reg_field_set(unit, DDR_PHY_CONTROL_REGS_STRAP_CONTROL2r, &rval, 2022 CLf, 13); 2023 SOC_IF_ERROR_RETURN( 2024 WRITE_DDR_PHY_CONTROL_REGS_STRAP_CONTROL2r(unit, rval)); 2025 2026 /* Perform 40nm DDR PHY calibration */ 2027 soc_ddr40_set_shmoo_dram_config(unit, 1); 2028 soc_ddr40_phy_calibrate(unit, 0, DDR_PHYTYPE_HR2, 0); 2029 2030 /* DDR controller initialization */ 2031 soc_iproc_ddr_reg_table_init( 2032 unit, DDR_DENALI_CTL_00r, hr2_ddr_init_tab); 2033 soc_iproc_ddr_reg_table_init( 2034 unit, DDR_DENALI_CTL_00r, hr2_ddr_init_tab_800); 2035 2036 /* Start DDR controller */ 2037 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &rval)); 2038 soc_reg_field_set(unit, DDR_DENALI_CTL_00r, &rval, STARTf, 1); 2039 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_00r(unit, rval)); 2040 2041 /* Wait for DDR ready */ 2042 soc_timeout_init(&to, to_val, 0); 2043 for(;;) { 2044 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_89r(unit, &rval)); 2045 if (soc_reg_field_get(unit, DDR_DENALI_CTL_89r, rval, INT_STATUSf) 2046 & 0x100) { 2047 break; 2048 } 2049 if (soc_timeout_check(&to)) { 2050 LOG_ERROR(BSL_LS_SOC_COMMON, 2051 (BSL_META_U(unit, 2052 "Timed out waiting for DDR controller to be ready\n"))); 2053 2054 return SOC_E_TIMEOUT; 2055 } 2056 } 2057 2058 /* Connect DDR port to BIST for running SHMOO */ 2059 rval = 0; 2060 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, 2061 BUS16_MODEf, 1); 2062 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, 2063 ENABLE_8_BANKS_MODEf, 1); 2064 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, 2065 AXI_PORT_SELf, 1); 2066 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, 2067 BIST_RESETBf, 1); 2068 WRITE_DDR_BISTCONFIGr(unit, rval); 2069 rval = 0; 2070 2071 /* Run or restore SHMOO */ 2072 if (soc_property_get(unit, spn_DDR3_AUTO_TUNE, TRUE)) { 2073 soc_ddr40_shmoo_ctl(unit, 0, DDR_PHYTYPE_HR2, DDR_CTLR_T1, 0, 1); 2074 LOG_INFO(BSL_LS_SOC_COMMON, 2075 (BSL_META_U(unit, "DDR tuning completed.\n"))); 2076 2077 soc_ddr40_shmoo_savecfg(unit, 0); 2078 if (soc_mem_config_set != NULL) { 2079 soc_mem_config_set("ddr3_auto_tune", "0"); 2080 } 2081 LOG_INFO(BSL_LS_SOC_COMMON, 2082 (BSL_META_U(unit, 2083 "Please save the config to avoid re-tuning.\n"))); 2084 } else { 2085 soc_ddr40_shmoo_restorecfg(unit, 0); 2086 } 2087 2088 /* Connect DDR port back to NIC */ 2089 READ_DDR_BISTCONFIGr(unit, &rval); 2090 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, AXI_PORT_SELf, 0); 2091 WRITE_DDR_BISTCONFIGr(unit, rval); 2092 2093 return SOC_E_NONE; 2094 } 2095 #endif /* BCM_HURRICANE2_SUPPORT */ 2096 2097 2098 #ifdef BCM_GREYHOUND_SUPPORT 2099 2100 STATIC int 2101 soc_and28_gh_shmoo_phy_reg_read(int unit, int ci, 2102 uint32 reg_addr, uint32 *reg_data) 2103 { 2104 uint32 base; 2105 uint32 rval; 2106 2107 if (reg_data == NULL) { 2108 return SOC_E_PARAM; 2109 } 2110 2111 /* Get DDR PHY register base address */ 2112 base = soc_reg_addr(unit, DDR_PHY_CONTROL_REGS_REVISIONr, REG_PORT_ANY, 0); 2113 rval = soc_iproc_getreg(unit, base + reg_addr, reg_data); 2114 2115 return rval; 2116 } 2117 2118 STATIC int 2119 soc_and28_gh_shmoo_phy_reg_write(int unit, int ci, 2120 uint32 reg_addr, uint32 reg_data) 2121 { 2122 int rv; 2123 uint32 base; 2124 uint32 dummy; 2125 2126 /* Get DDR PHY register base address */ 2127 base = soc_reg_addr(unit, DDR_PHY_CONTROL_REGS_REVISIONr, REG_PORT_ANY, 0); 2128 rv = soc_iproc_setreg(unit, base + reg_addr, reg_data); 2129 2130 /* Need to read a PHY register after PHY write */ 2131 if (rv == SOC_E_NONE) { 2132 (void)soc_iproc_getreg(unit, base, &dummy); 2133 } 2134 2135 return rv; 2136 } 2137 2138 STATIC int 2139 soc_and28_gh_shmoo_phy_reg_modify(int unit, int ci, 2140 uint32 reg_addr, uint32 data, uint32 mask) 2141 { 2142 int rv = SOC_E_NONE; 2143 uint32 tmp, otmp; 2144 2145 data = data & mask; 2146 2147 SOC_IF_ERROR_RETURN(soc_and28_gh_shmoo_phy_reg_read( 2148 unit, ci, reg_addr, &tmp)); 2149 otmp = tmp; 2150 tmp &= ~(mask); 2151 tmp |= data; 2152 2153 if (otmp != tmp) { 2154 SOC_IF_ERROR_RETURN(soc_and28_gh_shmoo_phy_reg_write( 2155 unit, ci, reg_addr, tmp)); 2156 } 2157 2158 return rv; 2159 } 2160 2161 STATIC int 2162 soc_and28_gh_shmoo_drc_bist_conf_set(int unit, int phy_ndx, 2163 and28_bist_info_t bist_info) 2164 { 2165 uint32 rval; 2166 uint32 poll_count; 2167 2168 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2169 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, bist_info.write_weight); 2170 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, READWEIGHTf, bist_info.read_weight); 2171 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, 0); 2172 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, PRBSMODEf, bist_info.prbs_mode); 2173 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 2174 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, 0); 2175 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, 0); 2176 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, 0); 2177 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, INDWRRDADDRMODEf, 1); 2178 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2179 2180 if(!(bist_info.prbs_mode)) 2181 { 2182 if(bist_info.mpr_mode) 2183 { 2184 if(1 /* YDC_DDR_BIST_PHY_BITWITDH_IS_32 */) 2185 { 2186 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD0r(unit, 0xFFFFFFFF)); 2187 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD1r(unit, 0x00000000)); 2188 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD2r(unit, 0xFFFFFFFF)); 2189 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD3r(unit, 0x00000000)); 2190 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD4r(unit, 0xFFFFFFFF)); 2191 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD5r(unit, 0x00000000)); 2192 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD6r(unit, 0xFFFFFFFF)); 2193 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD7r(unit, 0x00000000)); 2194 } 2195 else 2196 { 2197 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD0r(unit, 0xFFFF0000)); 2198 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD1r(unit, 0xFFFF0000)); 2199 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD2r(unit, 0xFFFF0000)); 2200 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD3r(unit, 0xFFFF0000)); 2201 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD4r(unit, 0xFFFF0000)); 2202 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD5r(unit, 0xFFFF0000)); 2203 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD6r(unit, 0xFFFF0000)); 2204 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD7r(unit, 0xFFFF0000)); 2205 } 2206 } 2207 else 2208 { 2209 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD0r(unit, _get_random28())); 2210 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD1r(unit, _get_random28())); 2211 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD2r(unit, _get_random28())); 2212 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD3r(unit, _get_random28())); 2213 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD4r(unit, _get_random28())); 2214 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD5r(unit, _get_random28())); 2215 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD6r(unit, _get_random28())); 2216 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD7r(unit, _get_random28())); 2217 } 2218 } 2219 2220 SOC_IF_ERROR_RETURN(READ_DDR_BISTNUMBEROFACTIONSr(unit, &rval)); 2221 soc_reg_field_set(unit, DDR_BISTNUMBEROFACTIONSr, &rval, 2222 BISTNUMACTIONSf, bist_info.bist_num_actions); 2223 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTNUMBEROFACTIONSr(unit, rval)); 2224 2225 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTARTADDRESSr(unit, &rval)); 2226 soc_reg_field_set(unit, DDR_BISTSTARTADDRESSr, &rval, 2227 BISTSTARTADDRESSf, bist_info.bist_start_address); 2228 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTSTARTADDRESSr(unit, rval)); 2229 2230 SOC_IF_ERROR_RETURN(READ_DDR_BISTENDADDRESSr(unit, &rval)); 2231 soc_reg_field_set(unit, DDR_BISTENDADDRESSr, &rval, 2232 BISTENDADDRESSf, bist_info.bist_end_address); 2233 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTENDADDRESSr(unit, rval)); 2234 2235 /* Start BIST */ 2236 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2237 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 1); 2238 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2239 2240 poll_count = 0; 2241 2242 while(TRUE) 2243 { 2244 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTATUSESr(unit, &rval)); 2245 2246 if(soc_reg_field_get(unit, DDR_BISTSTATUSESr, rval, BISTFINISHEDf)) 2247 { 2248 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2249 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 2250 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2251 break; 2252 } 2253 2254 if(poll_count > 100000) 2255 { 2256 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2257 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 2258 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2259 2260 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "ERROR: YDC DDR BIST timeout!!!\n"))); 2261 return SOC_E_TIMEOUT; 2262 } 2263 2264 poll_count++; 2265 sal_usleep(10); 2266 } 2267 2268 return SOC_E_NONE; 2269 } 2270 2271 STATIC int 2272 soc_and28_gh_shmoo_drc_bist_err_cnt(int unit, int phy_ndx, 2273 and28_bist_err_cnt_t *error_count) 2274 { 2275 uint32 rval; 2276 2277 SOC_IF_ERROR_RETURN(READ_DDR_BISTERROROCCURREDr(unit, &rval)); 2278 error_count->bist_err_occur = soc_reg_field_get(unit, 2279 DDR_BISTERROROCCURREDr, rval, ERROCCURREDf); 2280 2281 SOC_IF_ERROR_RETURN(READ_DDR_BISTFULLMASKERRORCOUNTERr(unit, &rval)); 2282 error_count->bist_full_err_cnt = soc_reg_field_get(unit, 2283 DDR_BISTFULLMASKERRORCOUNTERr, rval, FULLERRCNTf); 2284 2285 SOC_IF_ERROR_RETURN(READ_DDR_BISTSINGLEBITMASKERRORCOUNTERr(unit, &rval)); 2286 error_count->bist_single_err_cnt = soc_reg_field_get(unit, 2287 DDR_BISTSINGLEBITMASKERRORCOUNTERr, rval, SINGLEERRCNTf); 2288 2289 SOC_IF_ERROR_RETURN(READ_DDR_BISTGLOBALERRORCOUNTERr(unit, &rval)); 2290 error_count->bist_global_err_cnt = soc_reg_field_get(unit, 2291 DDR_BISTGLOBALERRORCOUNTERr, rval, GLOBALERRCNTf); 2292 2293 return SOC_E_NONE; 2294 } 2295 2296 2297 int soc_and28_gh_shmoo_dram_init(int unit, int ci, int phase) 2298 { 2299 return SOC_E_NONE; 2300 } 2301 2302 /* Fill shmoo CB structure */ 2303 static and28_shmoo_cbi_t gh_shmoo_cbi = { 2304 soc_and28_gh_shmoo_phy_reg_read, 2305 soc_and28_gh_shmoo_phy_reg_write, 2306 soc_and28_gh_shmoo_phy_reg_modify, 2307 soc_and28_gh_shmoo_drc_bist_conf_set, 2308 soc_and28_gh_shmoo_drc_bist_err_cnt, 2309 soc_and28_gh_shmoo_dram_init 2310 }; 2311 2312 2313 #define CONFIG_DDR_GH_ROW_BITS 15 2314 #define CONFIG_DDR_GH_COL_BITS 10 2315 #define CONFIG_DDR_GH_BANK_BITS 3 2316 #define CONFIG_DDR_GH_BANK_GROUPS 1 2317 2318 /* 2319 * Function: 2320 * soc_iproc_gh_ddr_init 2321 * Purpose: 2322 * Initialize DDR of the embedded iProc subsystem for Greyhound 2323 * Parameters: 2324 * unit - unit number 2325 * Returns: 2326 * SOC_E_XXX 2327 */ 2328 STATIC int 2329 soc_iproc_gh_ddr_init(int unit) 2330 { 2331 soc_timeout_t to; 2332 sal_usecs_t to_val = 50000; /* 50ms */ 2333 uint32 rval; 2334 uint32 idx; 2335 uint16 dev_id; 2336 uint8 rev_id; 2337 and28_shmoo_dram_info_t sdi; 2338 and28_shmoo_config_param_t config_param; 2339 uint32 genpll_clk_tbl[] = 2340 { 2341 /* mode, ndiv, MDIV 2342 0 1 2 3 4 5 */ 2343 0, 96, 12, 0, 80, 6, 5, 40, /* 400 MHz AXI */ 2344 1, 96, 12, 0, 80, 12, 5, 40, /* 200 MHz AXI */ 2345 0xffffffff 2346 }; 2347 2348 /* Skip if DDR has been already initialized */ 2349 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &rval)); 2350 if (soc_reg_field_get(unit, DDR_DENALI_CTL_00r, rval, STARTf) == 1) { 2351 return SOC_E_NONE; 2352 } 2353 2354 /* Shmoo callback function registration */ 2355 soc_and28_shmoo_interface_cb_register(unit, gh_shmoo_cbi); 2356 2357 soc_cm_get_id(unit, &dev_id, &rev_id); 2358 /* Set up default DDR configuration */ 2359 if ((dev_id & 0xfff0) == 0xb060) { 2360 /* Ranger2 - 5606x: CPU 1250MHz, AXI 400MHz, DDR 800MHz */ 2361 soc_iproc_config_genpll(unit, &genpll_clk_tbl[0]);; 2362 2363 SOC_DDR3_CLOCK_MHZ(unit) = DDR_FREQ_800; 2364 SOC_DDR3_MEM_GRADE(unit) = 0; /* To use default */ 2365 } else { 2366 /* Greyhound - 5341x: CPU 600MHz, AXI 200MHz, DDR 667MHz */ 2367 soc_iproc_config_genpll(unit, &genpll_clk_tbl[8]); 2368 2369 SOC_DDR3_CLOCK_MHZ(unit) = DDR_FREQ_667; 2370 SOC_DDR3_MEM_GRADE(unit) = 0; /* to use default */ 2371 } 2372 2373 /* Initialize ATCM and BTCM for SHMOO (clear to avoid ECC error) */ 2374 for (idx = 0; idx < 64 * 1024; idx = (idx + 4)) { 2375 soc_iproc_setreg(unit, (0x01000000 + idx), 0); 2376 } 2377 for (idx = 0; idx < 128 * 1024; idx = (idx + 4)) { 2378 soc_iproc_setreg(unit, (0x01080000 + idx), 0); 2379 } 2380 2381 SOC_IF_ERROR_RETURN(READ_CRU_DDRPHY_PWR_CTRLr(unit, &rval)); 2382 2383 /* Assert power ON */ 2384 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_PWRONIN_PHYf, 1); 2385 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2386 2387 /* Assert power OK */ 2388 sal_usleep(10); 2389 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_PWROKIN_PHYf, 1); 2390 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2391 2392 /* Remove DFI isolation */ 2393 sal_usleep(150); 2394 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_ISO_PHY_DFIf, 0); 2395 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2396 2397 /* Remove PHY register isolation */ 2398 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_ISO_PHY_REGSf, 0); 2399 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2400 2401 /* Remove PLL isolation */ 2402 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_ISO_PHY_PLLf, 0); 2403 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2404 2405 /* Wait for PHY power up */ 2406 soc_timeout_init(&to, to_val, 0); 2407 for(;;) { 2408 SOC_IF_ERROR_RETURN(READ_DDR_S1_IDM_IO_STATUSr(unit, &rval)); 2409 if (soc_reg_field_get(unit, DDR_S1_IDM_IO_STATUSr, 2410 rval, O_PHY_PWRUP_RSBf)) { 2411 break; 2412 } 2413 if (soc_timeout_check(&to)) { 2414 LOG_ERROR(BSL_LS_SOC_COMMON, 2415 (BSL_META_U(unit, 2416 "Timed out waiting for PHY to power up\n"))); 2417 2418 return SOC_E_TIMEOUT; 2419 } 2420 } 2421 2422 /* Bring DDR controller out of reset */ 2423 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 2424 DDR_S1_IDM_RESET_CONTROLr, REG_PORT_ANY, RESETf, 0)); 2425 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 2426 DDR_S2_IDM_RESET_CONTROLr, REG_PORT_ANY, RESETf, 0)); 2427 sal_usleep(1000); 2428 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 2429 DDR_S0_IDM_RESET_CONTROLr, REG_PORT_ANY, RESETf, 0)); 2430 2431 /* Set default speed */ 2432 SOC_IF_ERROR_RETURN(READ_DDR_S1_IDM_IO_CONTROL_DIRECTr(unit, &rval)); 2433 soc_reg_field_set(unit, DDR_S1_IDM_IO_CONTROL_DIRECTr, &rval, 2434 I_PHY_DDR_MHZf, SOC_DDR3_CLOCK_MHZ(unit) ); 2435 SOC_IF_ERROR_RETURN(WRITE_DDR_S1_IDM_IO_CONTROL_DIRECTr(unit, rval)); 2436 2437 SOC_IF_ERROR_RETURN(READ_DDR_S2_IDM_IO_CONTROL_DIRECTr(unit, &rval)); 2438 soc_reg_field_set(unit, DDR_S2_IDM_IO_CONTROL_DIRECTr, &rval, 2439 MODE_32Bf, 1); 2440 SOC_IF_ERROR_RETURN(WRITE_DDR_S2_IDM_IO_CONTROL_DIRECTr(unit, rval)); 2441 2442 /* Wait for PHY ready */ 2443 soc_timeout_init(&to, to_val, 0); 2444 for(;;) { 2445 SOC_IF_ERROR_RETURN(READ_DDR_S1_IDM_IO_STATUSr(unit, &rval)); 2446 if (soc_reg_field_get(unit, DDR_S1_IDM_IO_STATUSr, 2447 rval, O_PHY_READYf)) { 2448 break; 2449 } 2450 if (soc_timeout_check(&to)) { 2451 LOG_ERROR(BSL_LS_SOC_COMMON, 2452 (BSL_META_U(unit, 2453 "Timed out waiting for PHY to be ready\n"))); 2454 2455 return SOC_E_TIMEOUT; 2456 } 2457 } 2458 2459 /* Get the DDR S0 out of reset */ 2460 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 2461 DDR_S0_IDM_RESET_CONTROLr, REG_PORT_ANY, RESETf, 0)); 2462 2463 /* Wait for DDR PHY up */ 2464 soc_timeout_init(&to, to_val, 0); 2465 for(;;) { 2466 SOC_IF_ERROR_RETURN( 2467 READ_DDR_PHY_CONTROL_REGS_REVISIONr(unit, &rval)); 2468 if (rval != 0) { 2469 break; 2470 } 2471 if (soc_timeout_check(&to)) { 2472 LOG_ERROR(BSL_LS_SOC_COMMON, 2473 (BSL_META_U(unit, 2474 "Timed out waiting for PHY to be ready\n"))); 2475 2476 return SOC_E_TIMEOUT; 2477 } 2478 } 2479 2480 sal_memset(&sdi, 0, sizeof(sdi)); 2481 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Calling soc_and28_shmoo_dram_info_set\n"))); 2482 sdi.data_rate_mbps = (SOC_DDR3_CLOCK_MHZ(unit) == DDR_FREQ_667) ? 2483 1333 : (SOC_DDR3_CLOCK_MHZ(unit) * 2); 2484 sdi.ref_clk_mhz = 50; 2485 sdi.ctl_type = SHMOO_AND28_CTL_TYPE_1; 2486 sdi.dram_type = SHMOO_AND28_DRAM_TYPE_DDR3; 2487 sdi.dram_bitmap = 0x00000001; 2488 sdi.interface_bitwidth = 32; 2489 sdi.num_columns = (1 << CONFIG_DDR_GH_COL_BITS); 2490 sdi.num_rows = (1 << CONFIG_DDR_GH_ROW_BITS); 2491 sdi.num_banks = (1 << CONFIG_DDR_GH_BANK_BITS); 2492 sdi.num_bank_groups = (1 << CONFIG_DDR_GH_BANK_GROUPS); 2493 sdi.refi = 7800; 2494 sdi.command_parity_latency = 0; 2495 sdi.sim_system_mode = 0; 2496 2497 SOC_IF_ERROR_RETURN(soc_and28_shmoo_dram_info_set(unit, &sdi)); 2498 SOC_IF_ERROR_RETURN(soc_and28_shmoo_phy_init(unit, 0)); 2499 2500 /* DDR controller initialization */ 2501 soc_iproc_ddr_reg_table_init(unit, DDR_DENALI_CTL_00r, gh_ddr_init_tab); 2502 2503 switch(SOC_DDR3_CLOCK_MHZ(unit)) { 2504 case DDR_FREQ_400: 2505 soc_iproc_ddr_reg_table_init( 2506 unit, DDR_DENALI_CTL_00r, gh_ddr3_init_tab_800); 2507 break; 2508 case DDR_FREQ_667: 2509 soc_iproc_ddr_reg_table_init( 2510 unit, DDR_DENALI_CTL_00r, gh_ddr3_init_tab_1333); 2511 break; 2512 case DDR_FREQ_800: 2513 soc_iproc_ddr_reg_table_init( 2514 unit, DDR_DENALI_CTL_00r, gh_ddr3_init_tab_1600); 2515 break; 2516 } 2517 2518 /* Start DDR controller */ 2519 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &rval)); 2520 soc_reg_field_set(unit, DDR_DENALI_CTL_00r, &rval, STARTf, 1); 2521 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_00r(unit, rval)); 2522 2523 /* Wait for DDR ready */ 2524 soc_timeout_init(&to, to_val, 0); 2525 for(;;) { 2526 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_175r(unit, &rval)); 2527 if (soc_reg_field_get(unit, DDR_DENALI_CTL_175r, rval, INT_STATUSf) 2528 & 0x100) { 2529 break; 2530 } 2531 if (soc_timeout_check(&to)) { 2532 LOG_ERROR(BSL_LS_SOC_COMMON, 2533 (BSL_META_U(unit, 2534 "Timed out waiting for DDR controller to be ready\n"))); 2535 2536 return SOC_E_TIMEOUT; 2537 } 2538 } 2539 2540 /* Connect DDR port to BIST for running SHMOO */ 2541 rval = 0x00100; 2542 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_177r(unit, rval)); 2543 2544 rval = 0; 2545 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, BUS16_MODEf, 1); 2546 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, ENABLE_8_BANKS_MODEf, 1); 2547 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, AXI_PORT_SELf, 1); 2548 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, BIST_RESETBf, 1); 2549 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGr(unit, rval)); 2550 2551 rval = 0; 2552 soc_reg_field_set(unit, DDR_BISTGENERALCONFIGURATIONSr, &rval, 2553 NUMCOLSf, 0x2); 2554 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTGENERALCONFIGURATIONSr(unit, rval)); 2555 2556 /* Run or restore SHMOO */ 2557 if (soc_property_get(unit, spn_DDR3_AUTO_TUNE, TRUE)) { 2558 soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, SHMOO_AND28_CTL_FLAGS_PLOT_BIT, 2559 SHMOO_AND28_ACTION_RUN, &config_param); 2560 LOG_INFO(BSL_LS_SOC_COMMON, 2561 (BSL_META_U(unit, "DDR tuning completed.\n"))); 2562 2563 if (soc_mem_config_set != NULL) { 2564 soc_mem_config_set("ddr3_auto_tune", "0"); 2565 } 2566 LOG_INFO(BSL_LS_SOC_COMMON, 2567 (BSL_META_U(unit, "Please save the config to avoid re-tuning.\n"))); 2568 } 2569 2570 /* Release DDR slave port to AXI */ 2571 READ_DDR_BISTCONFIGr(unit, &rval); 2572 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, AXI_PORT_SELf, 0); 2573 WRITE_DDR_BISTCONFIGr(unit, rval); 2574 2575 return SOC_E_NONE; 2576 } 2577 2578 #endif /* BCM_GREYHOUND_SUPPORT */ 2579 2580 #ifdef BCM_HURRICANE3_SUPPORT 2581 2582 STATIC int 2583 soc_and28_hr3_shmoo_phy_reg_read(int unit, int ci, 2584 uint32 reg_addr, uint32 *reg_data) 2585 { 2586 uint32 base; 2587 uint32 rval; 2588 2589 if (reg_data == NULL) { 2590 return SOC_E_PARAM; 2591 } 2592 2593 /* Get DDR PHY register base address */ 2594 base = soc_reg_addr(unit, DDR_PHY_CONTROL_REGS_REVISIONr, REG_PORT_ANY, 0); 2595 rval = soc_iproc_getreg(unit, base + reg_addr, reg_data); 2596 2597 return rval; 2598 } 2599 2600 STATIC int 2601 soc_and28_hr3_shmoo_phy_reg_write(int unit, int ci, 2602 uint32 reg_addr, uint32 reg_data) 2603 { 2604 int rv; 2605 uint32 base; 2606 uint32 dummy; 2607 2608 /* Get DDR PHY register base address */ 2609 base = soc_reg_addr(unit, DDR_PHY_CONTROL_REGS_REVISIONr, REG_PORT_ANY, 0); 2610 rv = soc_iproc_setreg(unit, base + reg_addr, reg_data); 2611 2612 /* Need to read a PHY register after PHY write */ 2613 if (rv == SOC_E_NONE) { 2614 (void)soc_iproc_getreg(unit, base, &dummy); 2615 } 2616 2617 return rv; 2618 } 2619 2620 STATIC int 2621 soc_and28_hr3_shmoo_phy_reg_modify(int unit, int ci, 2622 uint32 reg_addr, uint32 data, uint32 mask) 2623 { 2624 int rv = SOC_E_NONE; 2625 uint32 tmp, otmp; 2626 2627 data = data & mask; 2628 2629 SOC_IF_ERROR_RETURN(soc_and28_hr3_shmoo_phy_reg_read( 2630 unit, ci, reg_addr, &tmp)); 2631 otmp = tmp; 2632 tmp &= ~(mask); 2633 tmp |= data; 2634 2635 if (otmp != tmp) { 2636 SOC_IF_ERROR_RETURN(soc_and28_hr3_shmoo_phy_reg_write( 2637 unit, ci, reg_addr, tmp)); 2638 } 2639 2640 return rv; 2641 } 2642 2643 STATIC int 2644 soc_and28_hr3_shmoo_drc_bist_conf_set(int unit, int phy_ndx, 2645 and28_bist_info_t bist_info) 2646 { 2647 uint32 rval; 2648 uint32 poll_count; 2649 2650 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2651 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2652 &rval, WRITEWEIGHTf, bist_info.write_weight); 2653 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2654 &rval, READWEIGHTf, bist_info.read_weight); 2655 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2656 &rval, PATTERNBITMODEf, 0); 2657 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2658 &rval, PRBSMODEf, bist_info.prbs_mode); 2659 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2660 &rval, CONSADDR8BANKSf, 1); 2661 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2662 &rval, ADDRESSSHIFTMODEf, 0); 2663 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2664 &rval, DATASHIFTMODEf, 0); 2665 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2666 &rval, DATAADDRMODEf, 0); 2667 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, 2668 &rval, INDWRRDADDRMODEf, 1); 2669 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2670 2671 if(!(bist_info.prbs_mode)) 2672 { 2673 if(bist_info.mpr_mode) 2674 { 2675 if(1 /* YDC_DDR_BIST_PHY_BITWITDH_IS_32 */) 2676 { 2677 SOC_IF_ERROR_RETURN( 2678 WRITE_DDR_BISTPATTERNWORD0r(unit, 0xFFFFFFFF)); 2679 SOC_IF_ERROR_RETURN( 2680 WRITE_DDR_BISTPATTERNWORD1r(unit, 0x00000000)); 2681 SOC_IF_ERROR_RETURN( 2682 WRITE_DDR_BISTPATTERNWORD2r(unit, 0xFFFFFFFF)); 2683 SOC_IF_ERROR_RETURN( 2684 WRITE_DDR_BISTPATTERNWORD3r(unit, 0x00000000)); 2685 SOC_IF_ERROR_RETURN( 2686 WRITE_DDR_BISTPATTERNWORD4r(unit, 0xFFFFFFFF)); 2687 SOC_IF_ERROR_RETURN( 2688 WRITE_DDR_BISTPATTERNWORD5r(unit, 0x00000000)); 2689 SOC_IF_ERROR_RETURN( 2690 WRITE_DDR_BISTPATTERNWORD6r(unit, 0xFFFFFFFF)); 2691 SOC_IF_ERROR_RETURN( 2692 WRITE_DDR_BISTPATTERNWORD7r(unit, 0x00000000)); 2693 } 2694 else 2695 { 2696 SOC_IF_ERROR_RETURN( 2697 WRITE_DDR_BISTPATTERNWORD0r(unit, 0xFFFF0000)); 2698 SOC_IF_ERROR_RETURN( 2699 WRITE_DDR_BISTPATTERNWORD1r(unit, 0xFFFF0000)); 2700 SOC_IF_ERROR_RETURN( 2701 WRITE_DDR_BISTPATTERNWORD2r(unit, 0xFFFF0000)); 2702 SOC_IF_ERROR_RETURN( 2703 WRITE_DDR_BISTPATTERNWORD3r(unit, 0xFFFF0000)); 2704 SOC_IF_ERROR_RETURN( 2705 WRITE_DDR_BISTPATTERNWORD4r(unit, 0xFFFF0000)); 2706 SOC_IF_ERROR_RETURN( 2707 WRITE_DDR_BISTPATTERNWORD5r(unit, 0xFFFF0000)); 2708 SOC_IF_ERROR_RETURN( 2709 WRITE_DDR_BISTPATTERNWORD6r(unit, 0xFFFF0000)); 2710 SOC_IF_ERROR_RETURN( 2711 WRITE_DDR_BISTPATTERNWORD7r(unit, 0xFFFF0000)); 2712 } 2713 } 2714 else 2715 { 2716 SOC_IF_ERROR_RETURN( 2717 WRITE_DDR_BISTPATTERNWORD0r(unit, _get_random28())); 2718 SOC_IF_ERROR_RETURN( 2719 WRITE_DDR_BISTPATTERNWORD1r(unit, _get_random28())); 2720 SOC_IF_ERROR_RETURN( 2721 WRITE_DDR_BISTPATTERNWORD2r(unit, _get_random28())); 2722 SOC_IF_ERROR_RETURN( 2723 WRITE_DDR_BISTPATTERNWORD3r(unit, _get_random28())); 2724 SOC_IF_ERROR_RETURN( 2725 WRITE_DDR_BISTPATTERNWORD4r(unit, _get_random28())); 2726 SOC_IF_ERROR_RETURN( 2727 WRITE_DDR_BISTPATTERNWORD5r(unit, _get_random28())); 2728 SOC_IF_ERROR_RETURN( 2729 WRITE_DDR_BISTPATTERNWORD6r(unit, _get_random28())); 2730 SOC_IF_ERROR_RETURN( 2731 WRITE_DDR_BISTPATTERNWORD7r(unit, _get_random28())); 2732 } 2733 } 2734 2735 SOC_IF_ERROR_RETURN(READ_DDR_BISTNUMBEROFACTIONSr(unit, &rval)); 2736 soc_reg_field_set(unit, DDR_BISTNUMBEROFACTIONSr, &rval, 2737 BISTNUMACTIONSf, bist_info.bist_num_actions); 2738 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTNUMBEROFACTIONSr(unit, rval)); 2739 2740 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTARTADDRESSr(unit, &rval)); 2741 soc_reg_field_set(unit, DDR_BISTSTARTADDRESSr, &rval, 2742 BISTSTARTADDRESSf, bist_info.bist_start_address); 2743 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTSTARTADDRESSr(unit, rval)); 2744 2745 SOC_IF_ERROR_RETURN(READ_DDR_BISTENDADDRESSr(unit, &rval)); 2746 soc_reg_field_set(unit, DDR_BISTENDADDRESSr, &rval, 2747 BISTENDADDRESSf, bist_info.bist_end_address); 2748 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTENDADDRESSr(unit, rval)); 2749 2750 /* Start BIST */ 2751 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2752 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 1); 2753 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2754 2755 poll_count = 0; 2756 2757 while(TRUE) 2758 { 2759 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTATUSESr(unit, &rval)); 2760 2761 if(soc_reg_field_get(unit, DDR_BISTSTATUSESr, rval, BISTFINISHEDf)) 2762 { 2763 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2764 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 2765 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2766 break; 2767 } 2768 2769 if(poll_count > 100000) 2770 { 2771 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONSr(unit, &rval)); 2772 soc_reg_field_set(unit, DDR_BISTCONFIGURATIONSr, &rval, BISTENf, 0); 2773 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONSr(unit, rval)); 2774 2775 LOG_ERROR(BSL_LS_SOC_COMMON, 2776 (BSL_META_U(unit, "ERROR: YDC DDR BIST timeout!!!\n"))); 2777 return SOC_E_TIMEOUT; 2778 } 2779 2780 poll_count++; 2781 sal_usleep(10); 2782 } 2783 2784 return SOC_E_NONE; 2785 } 2786 2787 STATIC int 2788 soc_and28_hr3_shmoo_drc_bist_err_cnt(int unit, int phy_ndx, 2789 and28_bist_err_cnt_t *error_count) 2790 { 2791 uint32 rval; 2792 2793 SOC_IF_ERROR_RETURN(READ_DDR_BISTERROROCCURREDr(unit, &rval)); 2794 error_count->bist_err_occur = soc_reg_field_get( 2795 unit, DDR_BISTERROROCCURREDr, rval, ERROCCURREDf); 2796 2797 SOC_IF_ERROR_RETURN(READ_DDR_BISTFULLMASKERRORCOUNTERr(unit, &rval)); 2798 error_count->bist_full_err_cnt = soc_reg_field_get( 2799 unit, DDR_BISTFULLMASKERRORCOUNTERr, rval, FULLERRCNTf); 2800 2801 SOC_IF_ERROR_RETURN(READ_DDR_BISTSINGLEBITMASKERRORCOUNTERr(unit, &rval)); 2802 error_count->bist_single_err_cnt = soc_reg_field_get( 2803 unit, DDR_BISTSINGLEBITMASKERRORCOUNTERr, rval, SINGLEERRCNTf); 2804 2805 SOC_IF_ERROR_RETURN(READ_DDR_BISTGLOBALERRORCOUNTERr(unit, &rval)); 2806 error_count->bist_global_err_cnt = soc_reg_field_get( 2807 unit, DDR_BISTGLOBALERRORCOUNTERr, rval, GLOBALERRCNTf); 2808 2809 return SOC_E_NONE; 2810 } 2811 2812 2813 int soc_and28_hr3_shmoo_dram_init(int unit, int ci, int phase) 2814 { 2815 return SOC_E_NONE; 2816 } 2817 2818 /* Fill shmoo CB structure */ 2819 static and28_shmoo_cbi_t hr3_shmoo_cbi = { 2820 soc_and28_hr3_shmoo_phy_reg_read, 2821 soc_and28_hr3_shmoo_phy_reg_write, 2822 soc_and28_hr3_shmoo_phy_reg_modify, 2823 soc_and28_hr3_shmoo_drc_bist_conf_set, 2824 soc_and28_hr3_shmoo_drc_bist_err_cnt, 2825 soc_and28_hr3_shmoo_dram_init 2826 }; 2827 2828 /* Hurricane3 DDR4 */ 2829 #define CONFIG_DDR4_HR3_ROW_BITS 15 2830 #define CONFIG_DDR4_HR3_COL_BITS 10 2831 #define CONFIG_DDR4_HR3_BANK_BITS 2 2832 #define CONFIG_DDR4_HR3_BANK_GROUPS 2 2833 2834 /* Hurricane3 DDR3 */ 2835 #define CONFIG_DDR3_HR3_ROW_BITS 16 2836 #define CONFIG_DDR3_HR3_COL_BITS 10 2837 #define CONFIG_DDR3_HR3_BANK_BITS 3 2838 #define CONFIG_DDR3_HR3_BANK_GROUPS 1 2839 2840 /* Hurricane3 Lite DDR3 */ 2841 #define CONFIG_DDR3_HR3L_ROW_BITS 14 2842 #define CONFIG_DDR3_HR3L_COL_BITS 10 2843 #define CONFIG_DDR3_HR3L_BANK_BITS 3 2844 #define CONFIG_DDR3_HR3L_BANK_GROUPS 1 2845 2846 /* 2847 * Function: 2848 * soc_iproc_hr3_ddr3_init 2849 * Purpose: 2850 * Initialize DDR of the embedded iProc subsystem for Greyhound 2851 * Parameters: 2852 * unit - unit number 2853 * Returns: 2854 * SOC_E_XXX 2855 */ 2856 STATIC int 2857 soc_iproc_hr3_ddr_init(int unit) 2858 { 2859 soc_timeout_t to; 2860 sal_usecs_t to_val = 50000; /* 50ms */ 2861 uint32 ddr_type; /* 1 if DDR4 */ 2862 uint32 rval; 2863 uint16 dev_id; 2864 uint8 rev_id; 2865 and28_shmoo_dram_info_t sdi; 2866 and28_shmoo_config_param_t config_param; 2867 uint32 genpll_clk_tbl[] = 2868 { 2869 /* mode, ndiv, MDIV 2870 0 1 2 3 4 5 */ 2871 0, 96, 12, 0, 80, 6, 5, 40, /* 400 MHz AXI */ 2872 1, 96, 12, 0, 80, 12, 5, 40, /* 200 MHz AXI */ 2873 0xffffffff 2874 }; 2875 2876 /* Skip if DDR has been already initialized */ 2877 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &rval)); 2878 if (soc_reg_field_get(unit, DDR_DENALI_CTL_00r, rval, STARTf) == 1) { 2879 return SOC_E_NONE; 2880 } 2881 2882 /* Shmoo callback function registration */ 2883 soc_and28_shmoo_interface_cb_register(unit, hr3_shmoo_cbi); 2884 2885 /* Get device ID and chip revision */ 2886 soc_cm_get_id(unit, &dev_id, &rev_id); 2887 2888 /* Get DDR type */ 2889 SOC_IF_ERROR_RETURN(READ_DDR_S1_IDM_IO_STATUSr(unit, &rval)); 2890 ddr_type = soc_reg_field_get(unit, DDR_S1_IDM_IO_STATUSr, rval, DDR_TYPEf); 2891 if (ddr_type >= 2) { 2892 LOG_ERROR(BSL_LS_SOC_COMMON, 2893 (BSL_META_U(unit, 2894 "Unsupported DDR type for Hurricane3: %d\n"), ddr_type)); 2895 return SOC_E_UNAVAIL; 2896 } 2897 2898 /* Set up default DDR configuration */ 2899 soc_iproc_config_genpll(unit, &genpll_clk_tbl[0]);; 2900 SOC_DDR3_CLOCK_MHZ(unit) = DDR_FREQ_800; 2901 SOC_DDR3_MEM_GRADE(unit) = 0; /* To use default */ 2902 2903 SOC_IF_ERROR_RETURN(READ_CRU_DDRPHY_PWR_CTRLr(unit, &rval)); 2904 2905 /* Assert power ON */ 2906 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_PWRONIN_PHYf, 1); 2907 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2908 2909 /* Assert power OK */ 2910 sal_usleep(10); 2911 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_PWROKIN_PHYf, 1); 2912 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2913 2914 /* Remove DFI isolation */ 2915 sal_usleep(150); 2916 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_ISO_PHY_DFIf, 0); 2917 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2918 2919 /* Remove PHY register isolation */ 2920 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_ISO_PHY_REGSf, 0); 2921 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2922 2923 /* Remove PLL isolation */ 2924 soc_reg_field_set(unit, CRU_DDRPHY_PWR_CTRLr, &rval, I_ISO_PHY_PLLf, 0); 2925 SOC_IF_ERROR_RETURN(WRITE_CRU_DDRPHY_PWR_CTRLr(unit, rval)); 2926 2927 /* Wait for PHY power up */ 2928 soc_timeout_init(&to, to_val, 0); 2929 for(;;) { 2930 SOC_IF_ERROR_RETURN(READ_DDR_S1_IDM_IO_STATUSr(unit, &rval)); 2931 if (soc_reg_field_get(unit, DDR_S1_IDM_IO_STATUSr, 2932 rval, O_PHY_PWRUP_RSBf)) { 2933 break; 2934 } 2935 if (soc_timeout_check(&to)) { 2936 LOG_ERROR(BSL_LS_SOC_COMMON, 2937 (BSL_META_U(unit, 2938 "Timed out waiting for PHY to power up\n"))); 2939 2940 return SOC_E_TIMEOUT; 2941 } 2942 } 2943 2944 /* Bring DDR controller out of reset */ 2945 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 2946 DDR_S1_IDM_RESET_CONTROLr, REG_PORT_ANY, RESETf, 0)); 2947 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 2948 DDR_S2_IDM_RESET_CONTROLr, REG_PORT_ANY, RESETf, 0)); 2949 sal_usleep(1000); 2950 2951 #ifdef CONFIG_DDR32 2952 SOC_IF_ERROR_RETURN(READ_DDR_S2_IDM_IO_CONTROL_DIRECTr(unit, &rval)); 2953 soc_reg_field_set(unit, DDR_S2_IDM_IO_CONTROL_DIRECTr, &rval, 2954 MODE_32Bf, 1); 2955 SOC_IF_ERROR_RETURN(WRITE_DDR_S2_IDM_IO_CONTROL_DIRECTr(unit, rval)); 2956 #endif 2957 2958 /* Wait for DDR PHY up */ 2959 soc_timeout_init(&to, to_val, 0); 2960 for(;;) { 2961 SOC_IF_ERROR_RETURN( 2962 READ_DDR_PHY_CONTROL_REGS_REVISIONr(unit, &rval)); 2963 if (rval != 0) { 2964 break; 2965 } 2966 if (soc_timeout_check(&to)) { 2967 LOG_ERROR(BSL_LS_SOC_COMMON, 2968 (BSL_META_U(unit, 2969 "Timed out waiting for PHY to be ready\n"))); 2970 2971 return SOC_E_TIMEOUT; 2972 } 2973 } 2974 2975 sal_memset(&sdi, 0, sizeof(sdi)); 2976 LOG_INFO(BSL_LS_SOC_COMMON, 2977 (BSL_META_U(unit, "Calling soc_and28_shmoo_dram_info_set\n"))); 2978 sdi.data_rate_mbps = (SOC_DDR3_CLOCK_MHZ(unit) == DDR_FREQ_667) ? 2979 1333 : (SOC_DDR3_CLOCK_MHZ(unit) * 2); 2980 sdi.ref_clk_mhz = 50; 2981 sdi.ctl_type = SHMOO_AND28_CTL_TYPE_1; 2982 sdi.dram_bitmap = 0x00000001; 2983 #ifdef CONFIG_DDR32 2984 sdi.interface_bitwidth = 32; 2985 #else 2986 sdi.interface_bitwidth = 16; 2987 #endif 2988 sdi.refi = 7800; 2989 sdi.command_parity_latency = 0; 2990 sdi.sim_system_mode = 0; 2991 if (ddr_type) { 2992 /* DDR4 */ 2993 sdi.dram_type = SHMOO_AND28_DRAM_TYPE_DDR4; 2994 sdi.num_columns = (1 << CONFIG_DDR4_HR3_COL_BITS); 2995 sdi.num_rows = (1 << CONFIG_DDR4_HR3_ROW_BITS); 2996 sdi.num_banks = (1 << CONFIG_DDR4_HR3_BANK_BITS); 2997 sdi.num_bank_groups = (1 << CONFIG_DDR4_HR3_BANK_GROUPS); 2998 } else { 2999 /* DDR3 */ 3000 sdi.dram_type = SHMOO_AND28_DRAM_TYPE_DDR3; 3001 if (dev_id == 0xb164) { 3002 /* Hurricane3 Lite */ 3003 sdi.num_columns = (1 << CONFIG_DDR3_HR3L_COL_BITS); 3004 sdi.num_rows = (1 << CONFIG_DDR3_HR3L_ROW_BITS); 3005 sdi.num_banks = (1 << CONFIG_DDR3_HR3L_BANK_BITS); 3006 sdi.num_bank_groups = (1 << CONFIG_DDR3_HR3L_BANK_GROUPS); 3007 } else { 3008 sdi.num_columns = (1 << CONFIG_DDR3_HR3_COL_BITS); 3009 sdi.num_rows = (1 << CONFIG_DDR3_HR3_ROW_BITS); 3010 sdi.num_banks = (1 << CONFIG_DDR3_HR3_BANK_BITS); 3011 sdi.num_bank_groups = (1 << CONFIG_DDR3_HR3_BANK_GROUPS); 3012 } 3013 } 3014 3015 SOC_IF_ERROR_RETURN(soc_and28_shmoo_dram_info_set(unit, &sdi)); 3016 SOC_IF_ERROR_RETURN(soc_and28_shmoo_phy_init(unit, 0)); 3017 3018 /* DDR controller initialization */ 3019 soc_iproc_ddr_reg_table_init(unit, DDR_DENALI_CTL_00r, 3020 (ddr_type ? hr3_ddr4_init_tab_1600 : hr3_ddr3_init_tab_1600)); 3021 3022 /* Start DDR controller */ 3023 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &rval)); 3024 soc_reg_field_set(unit, DDR_DENALI_CTL_00r, &rval, STARTf, 1); 3025 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_00r(unit, rval)); 3026 3027 /* Wait for DDR ready */ 3028 soc_timeout_init(&to, to_val, 0); 3029 for(;;) { 3030 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_175r(unit, &rval)); 3031 if (soc_reg_field_get(unit, DDR_DENALI_CTL_175r, rval, INT_STATUSf) 3032 & 0x100) { 3033 break; 3034 } 3035 if (soc_timeout_check(&to)) { 3036 LOG_ERROR(BSL_LS_SOC_COMMON, 3037 (BSL_META_U(unit, 3038 "Timed out waiting for DDR controller to be ready\n"))); 3039 3040 return SOC_E_TIMEOUT; 3041 } 3042 } 3043 3044 /* Connect DDR port to BIST for running SHMOO */ 3045 rval = 0x00100; 3046 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_177r(unit, rval)); 3047 3048 rval = 0; 3049 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, BUS16_MODEf, 1); 3050 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, ENABLE_8_BANKS_MODEf, 1); 3051 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, AXI_PORT_SELf, 1); 3052 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, BIST_RESETBf, 1); 3053 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGr(unit, rval)); 3054 3055 rval = 0; 3056 soc_reg_field_set(unit, DDR_BISTGENERALCONFIGURATIONSr, &rval, 3057 NUMCOLSf, 0x2); 3058 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTGENERALCONFIGURATIONSr(unit, rval)); 3059 3060 /* Run or restore SHMOO */ 3061 if (soc_property_get(unit, spn_DDR3_AUTO_TUNE, TRUE)) { 3062 soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 3063 SHMOO_AND28_CTL_FLAGS_PLOT_BIT, SHMOO_AND28_ACTION_RUN, 3064 &config_param); 3065 LOG_INFO(BSL_LS_SOC_COMMON, 3066 (BSL_META_U(unit, "DDR tuning completed.\n"))); 3067 3068 if (soc_mem_config_set != NULL) { 3069 soc_mem_config_set("ddr3_auto_tune", "0"); 3070 } 3071 LOG_INFO(BSL_LS_SOC_COMMON, 3072 (BSL_META_U(unit, "Please save the config to avoid re-tuning.\n"))); 3073 } 3074 3075 /* Release DDR slave port to AXI */ 3076 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGr(unit, &rval)); 3077 soc_reg_field_set(unit, DDR_BISTCONFIGr, &rval, AXI_PORT_SELf, 0); 3078 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGr(unit, rval)); 3079 3080 return SOC_E_NONE; 3081 } 3082 3083 #endif /* BCM_HURRICANE3_SUPPORT */ 3084 3085 #ifdef BCM_HELIX5_SUPPORT 3086 3087 #define DDR4_FREQ_1600 1600 3088 #define CONFIG_DDR32 1 3089 #define CONFIG_DDR4_HX5_ROW_BITS 15 3090 #define CONFIG_DDR4_HX5_COL_BITS 10 3091 #define CONFIG_DDR4_HX5_BANK_BITS 2 3092 #define CONFIG_DDR4_HX5_BANK_GROUP_BITS 1 3093 3094 unsigned int hx5_ddr_init_tab[] = { 3095 0xffffffff 3096 }; 3097 3098 STATIC 3099 unsigned int hx5_ddr4_init_tab_3200[] = { 3100 0, 0x00000a00, 3101 1, 0x00000000, 3102 2, 0x00000000, 3103 3, 0x00000000, 3104 4, 0x00000000, 3105 5, 0x00000000, 3106 6, 0x00000010, 3107 7, 0x00000780, 3108 8, 0x00000c80, 3109 9, 0x102c0400, 3110 10, 0x20200800, 3111 11, 0x09080404, 3112 12, 0x3448000b, 3113 13, 0x30140c05, 3114 14, 0x0c0c0000, 3115 15, 0x0000180a, 3116 16, 0x0801b6c0, 3117 17, 0x14001811, 3118 18, 0x1800f018, 3119 19, 0x01010101, 3120 20, 0x0014032c, 3121 21, 0x01000800, 3122 22, 0x00000001, 3123 23, 0x00000000, 3124 24, 0x01000000, 3125 25, 0x000001a0, 3126 26, 0x000030c0, 3127 27, 0x000000d0, 3128 28, 0x0027000a, 3129 29, 0x01b00400, 3130 30, 0x00010000, 3131 31, 0x00101600, 3132 32, 0x0e010a09, 3133 33, 0x0700042f, 3134 34, 0x00000000, 3135 35, 0x00000000, 3136 36, 0x00000000, 3137 37, 0x00000000, 3138 38, 0x00000000, 3139 39, 0x00000000, 3140 40, 0x00000000, 3141 41, 0x00000000, 3142 42, 0x00000000, 3143 43, 0x00000000, 3144 44, 0x00000000, 3145 45, 0x00000000, 3146 46, 0x000c5000, 3147 47, 0x00000001, 3148 48, 0x00000028, 3149 49, 0x00000000, 3150 50, 0x00000400, 3151 51, 0x00000000, 3152 52, 0x00000443, 3153 53, 0x00001000, 3154 54, 0x00000000, 3155 55, 0x00000000, 3156 56, 0x00000000, 3157 57, 0x00000000, 3158 58, 0x00000000, 3159 59, 0x00000000, 3160 60, 0x00000000, 3161 61, 0x00000000, 3162 62, 0x00000000, 3163 63, 0x00000000, 3164 64, 0x00100000, 3165 65, 0x0003e800, 3166 66, 0x00000064, 3167 67, 0x00000000, 3168 68, 0x00000000, 3169 69, 0x00000000, 3170 70, 0x00000000, 3171 71, 0x00000000, 3172 72, 0x00000000, 3173 73, 0x01000000, 3174 74, 0x00040000, 3175 75, 0x00800200, 3176 76, 0x00000200, 3177 77, 0x00000040, 3178 78, 0x00020100, 3179 79, 0x0a000002, 3180 80, 0x0101ffff, 3181 81, 0x01010101, 3182 82, 0x01030101, 3183 83, 0x000c0000, 3184 84, 0x00000001, 3185 85, 0x01000100, 3186 86, 0x00000000, 3187 87, 0x01000000, 3188 88, 0x00000000, 3189 91, 0x00000000, 3190 92, 0x00000000, 3191 93, 0x00000000, 3192 94, 0x00000000, 3193 95, 0x00000000, 3194 96, 0x00000000, 3195 97, 0x00000000, 3196 98, 0x00000000, 3197 99, 0x00010615, 3198 100, 0x00000400, 3199 101, 0x00000000, 3200 102, 0x00000000, 3201 103, 0x00000000, 3202 104, 0x0000280d, 3203 105, 0x00010000, 3204 106, 0x00010000, 3205 107, 0x00000000, 3206 108, 0x00000000, 3207 109, 0x00000000, 3208 110, 0x00000000, 3209 131, 0x01000000, 3210 132, 0x00000001, 3211 133, 0x00010100, 3212 134, 0x67676700, 3213 135, 0x00006767, 3214 136, 0x00000101, 3215 137, 0x00010100, 3216 138, 0x00016403, 3217 139, 0x00000164, 3218 140, 0x00000000, 3219 141, 0x00170000, 3220 142, 0x00000500, 3221 143, 0x00006180, 3222 144, 0x02000200, 3223 145, 0x02000200, 3224 146, 0x00006180, 3225 147, 0x0003cf00, 3226 148, 0x0602171e, 3227 149, 0x000a0a05, 3228 150, 0x00000000, 3229 151, 0x00000000, 3230 152, 0x00000f0a, 3231 153, 0x000007d0, 3232 154, 0x00000000, 3233 155, 0x00000000, 3234 156, 0x00000000, 3235 157, 0x15000000, 3236 158, 0x00000017, 3237 159, 0x00000000, 3238 160, 0x00000000, 3239 161, 0x00000000, 3240 162, 0x00000000, 3241 163, 0x00000000, 3242 164, 0x00000000, 3243 165, 0x00000000, 3244 166, 0x00000000, 3245 0, 0x00000a01, 3246 0xffffffff, 0 3247 }; 3248 3249 STATIC int 3250 soc_iproc_hx5_ddr_init(int unit) 3251 { 3252 soc_timeout_t to; 3253 sal_usecs_t to_val = 50000; /* 50ms */ 3254 uint32 rval; 3255 3256 sjc16_shmoo_dram_info_t sdi; 3257 sjc16_shmoo_config_param_t config_param; 3258 3259 sal_memset(&sdi, 0, sizeof(sdi)); 3260 3261 sdi.data_rate_mbps = (DDR4_FREQ_1600 * 2); 3262 sdi.ref_clk_mhz = 100; 3263 sdi.ctl_type = SHMOO_SJC16_CTL_TYPE_1; 3264 sdi.dram_type = SHMOO_SJC16_DRAM_TYPE_DDR4; 3265 sdi.dram_bitmap = 0x00000001; 3266 sdi.interface_bitwidth = 32; 3267 #if defined(CONFIG_IPROC_DDR_ECC) 3268 sdi.ecc_32p4 = 1; 3269 #endif 3270 3271 sdi.num_rows = (1 << CONFIG_DDR4_HX5_ROW_BITS); 3272 sdi.num_columns = (1 << CONFIG_DDR4_HX5_COL_BITS); 3273 sdi.num_banks = (1 << CONFIG_DDR4_HX5_BANK_BITS); 3274 sdi.num_bank_groups = (1 << CONFIG_DDR4_HX5_BANK_GROUP_BITS); 3275 3276 sdi.refi = 7800; 3277 sdi.command_parity_latency = 0; 3278 sdi.sim_system_mode = 0; 3279 3280 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Calling soc_sjc16_shmoo_dram_info_set\n"))); 3281 SOC_IF_ERROR_RETURN(soc_sjc16_shmoo_dram_info_set(unit, &sdi)); 3282 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Calling soc_sjc16_shmoo_phy_init\n"))); 3283 SOC_IF_ERROR_RETURN(soc_sjc16_shmoo_phy_init(unit, 0)); 3284 3285 /* DDR controller initialization */ 3286 LOG_VERBOSE(BSL_LS_SOC_DDR, (BSL_META_U(unit, "Programming controller register\n"))); 3287 soc_iproc_ddr_reg_table_init(unit, DDR_DENALI_CTL_00r, hx5_ddr4_init_tab_3200); 3288 3289 /* Start DDR controller */ 3290 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_00r(unit, &rval)); 3291 soc_reg_field_set(unit, DDR_DENALI_CTL_00r, &rval, STARTf, 1); 3292 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_00r(unit, rval)); 3293 3294 /* Wait for DDR ready */ 3295 soc_timeout_init(&to, to_val, 0); 3296 for(;;) { 3297 SOC_IF_ERROR_RETURN(READ_DDR_DENALI_CTL_89r(unit, &rval)); 3298 if (soc_reg_field_get(unit, DDR_DENALI_CTL_89r, rval, INT_STATUSf) 3299 & 0x800) { 3300 break; 3301 } 3302 if (soc_timeout_check(&to)) { 3303 LOG_ERROR(BSL_LS_SOC_DDR, 3304 (BSL_META_U(unit, 3305 "Timed out waiting for DDR controller to be ready\n"))); 3306 3307 return SOC_E_TIMEOUT; 3308 } 3309 } 3310 3311 /* Connect DDR port to BIST for running SHMOO */ 3312 rval = 0x800; 3313 SOC_IF_ERROR_RETURN(WRITE_DDR_DENALI_CTL_91r(unit, rval)); 3314 3315 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGr(unit, 0x00000002)); 3316 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGr(unit, 0x00000003)); 3317 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGr(unit, 0x00004003)); 3318 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTGENERALCONFIGURATIONSr(unit, 0x00000020)); 3319 3320 /* Run or restore SHMOO */ 3321 if (soc_property_get(unit, spn_DDR3_AUTO_TUNE, TRUE)) { 3322 /* Connect DDR controller to BIST for SHMOO */ 3323 soc_sjc16_shmoo_ctl(unit, 0, SHMOO_SJC16_SHMOO_RSVP, 0, 1, SHMOO_SJC16_ACTION_RUN, &config_param); 3324 LOG_INFO(BSL_LS_SOC_DDR, 3325 (BSL_META_U(unit, "DDR tuning completed.\n"))); 3326 3327 if (soc_mem_config_set != NULL) { 3328 soc_mem_config_set("ddr3_auto_tune", "0"); 3329 } 3330 LOG_INFO(BSL_LS_SOC_DDR, 3331 (BSL_META_U(unit, "Please save the config to avoid re-tuning.\n"))); 3332 } 3333 3334 return SOC_E_NONE; 3335 } 3336 3337 int 3338 soc_ydc_ddr_bist_config_set(int unit, int phy_ndx, ydc_ddr_bist_info_t *bist_info) 3339 { 3340 uint32 data; 3341 3342 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONS_0r(unit, &data)); 3343 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, WRITE_WEIGHT, (*bist_info).write_weight); 3344 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, READ_WEIGHT, (*bist_info).read_weight); 3345 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, PATTERN_BIT_MODE, 0); 3346 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, PRBS_MODE, (*bist_info).prbs_mode); 3347 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, ADDRESS_SHIFT_MODE, 0); 3348 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, DATA_SHIFT_MODE, 0); 3349 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, DATA_ADDR_MODE, 0); 3350 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, SINGLE_BANK_TEST, 0); 3351 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_0, BG_INTERLEAVE, 1); 3352 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONS_0r(unit, data)); 3353 3354 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONS_1r(unit, &data)); 3355 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_1, ADDRESS_PRBS_MODE, (*bist_info).addr_prbs_mode); 3356 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONS_1r(unit, data)); 3357 3358 if(!((*bist_info).prbs_mode)) 3359 { 3360 if((*bist_info).mpr_mode) 3361 { 3362 if(YDC_DDR_BIST_BIST_PHY_BITWITDH_IS_32) 3363 { 3364 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD0r(unit, 0x00000000)); 3365 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD1r(unit, 0xFFFFFFFF)); 3366 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD2r(unit, 0x00000000)); 3367 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD3r(unit, 0xFFFFFFFF)); 3368 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD4r(unit, 0x00000000)); 3369 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD5r(unit, 0xFFFFFFFF)); 3370 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD6r(unit, 0x00000000)); 3371 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD7r(unit, 0xFFFFFFFF)); 3372 } 3373 else 3374 { 3375 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD0r(unit, 0xFFFF0000)); 3376 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD1r(unit, 0xFFFF0000)); 3377 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD2r(unit, 0xFFFF0000)); 3378 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD3r(unit, 0xFFFF0000)); 3379 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD4r(unit, 0xFFFF0000)); 3380 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD5r(unit, 0xFFFF0000)); 3381 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD6r(unit, 0xFFFF0000)); 3382 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPATTERNWORD7r(unit, 0xFFFF0000)); 3383 } 3384 } 3385 else 3386 { 3387 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB31_TO_0r(unit, 0x01234567)); 3388 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB_63_TO_32r(unit, 0xBA5EBA11)); 3389 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB_95_TO_64r(unit, 0xDEADBEEF)); 3390 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB_127_TO_96r(unit, 0xA600DD06)); 3391 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB31_TO_0r(unit, 0x89ABCDEF)); 3392 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB_63_TO_32r(unit, 0xD1CEF001)); 3393 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB_95_TO_64r(unit, 0xEA5EEACE)); 3394 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB_127_TO_96r(unit, 0xABAD5EED)); 3395 } 3396 } else 3397 { 3398 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB31_TO_0r(unit, 0x01234567)); 3399 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB_63_TO_32r(unit, 0xBA5EBA11)); 3400 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB_95_TO_64r(unit, 0xDEADBEEF)); 3401 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDMSB_127_TO_96r(unit, 0xA600DD06)); 3402 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB31_TO_0r(unit, 0x89ABCDEF)); 3403 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB_63_TO_32r(unit, 0xD1CEF001)); 3404 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB_95_TO_64r(unit, 0xEA5EEACE)); 3405 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSDATASEEDLSB_127_TO_96r(unit, 0xABAD5EED)); 3406 } 3407 3408 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTPRBSADDRSEEDr(unit, 0x01DE5EED)); 3409 3410 SOC_IF_ERROR_RETURN(READ_DDR_BISTNUMBEROFACTIONSr(unit, &data)); 3411 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_NUMBER_OF_ACTIONS, BIST_NUM_ACTIONS, (*bist_info).bist_num_actions); 3412 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTNUMBEROFACTIONSr(unit, data)); 3413 3414 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTARTADDRESSr(unit, &data)); 3415 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_START_ADDRESS, BIST_START_ADDRESS, (*bist_info).bist_start_address); 3416 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTSTARTADDRESSr(unit, data)); 3417 3418 SOC_IF_ERROR_RETURN(READ_DDR_BISTENDADDRESSr(unit, &data)); 3419 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_END_ADDRESS, BIST_END_ADDRESS, (*bist_info).bist_end_address); 3420 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTENDADDRESSr(unit, data)); 3421 3422 return SOC_E_NONE; 3423 } 3424 3425 int 3426 soc_ydc_ddr_bist_run(int unit, int phy_ndx, ydc_ddr_bist_err_cnt_t *error_count) 3427 { 3428 uint32 data; 3429 uint32 poll_count; 3430 3431 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONS_1r(unit, &data)); 3432 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_1, BIST_EN, 1); 3433 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONS_1r(unit, data)); 3434 3435 poll_count = 0; 3436 3437 while(TRUE) 3438 { 3439 3440 SOC_IF_ERROR_RETURN(READ_DDR_BISTSTATUSESr(unit, &data)); 3441 3442 if(YDC_DDR_BIST_BIST_GET_FIELD(data, YDC_DDR_BIST, BIST_STATUSES, BIST_FINISHED)) 3443 { 3444 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONS_1r(unit, &data)); 3445 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_1, BIST_EN, 0); 3446 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONS_1r(unit, data)); 3447 break; 3448 } 3449 3450 if(poll_count > YDC_DDR_BIST_BIST_POLL_COUNT_LIMIT) 3451 { 3452 SOC_IF_ERROR_RETURN(READ_DDR_BISTCONFIGURATIONS_1r(unit, &data)); 3453 YDC_DDR_BIST_BIST_SET_FIELD(data, YDC_DDR_BIST, BIST_CONFIGURATIONS_1, BIST_EN, 0); 3454 SOC_IF_ERROR_RETURN(WRITE_DDR_BISTCONFIGURATIONS_1r(unit, data)); 3455 3456 LOG_ERROR(BSL_LS_SOC_COMMON, 3457 (BSL_META_U(unit, "ERROR: YDC DDR BIST timeout!!!\n"))); 3458 return SOC_E_TIMEOUT; 3459 } 3460 3461 poll_count++; 3462 sal_usleep(YDC_DDR_BIST_BIST_POLL_INTERVAL_US); 3463 } 3464 3465 SOC_IF_ERROR_RETURN(READ_DDR_BISTERROROCCURREDr(unit, &data)); 3466 (*error_count).bist_err_occur = YDC_DDR_BIST_BIST_GET_FIELD(data, YDC_DDR_BIST, BIST_ERROR_OCCURRED, ERR_OCCURRED); 3467 3468 SOC_IF_ERROR_RETURN(READ_DDR_BISTFULLMASKERRORCOUNTERr(unit, &data)); 3469 (*error_count).bist_full_err_cnt = YDC_DDR_BIST_BIST_GET_FIELD(data, YDC_DDR_BIST, BIST_FULL_MASK_ERROR_COUNTER, FULL_ERR_CNT); 3470 3471 SOC_IF_ERROR_RETURN(READ_DDR_BISTSINGLEBITMASKERRORCOUNTERr(unit, &data)); 3472 (*error_count).bist_single_err_cnt = YDC_DDR_BIST_BIST_GET_FIELD(data, YDC_DDR_BIST, BIST_SINGLE_BIT_MASK_ERROR_COUNTER, SINGLE_ERR_CNT); 3473 3474 SOC_IF_ERROR_RETURN(READ_DDR_BISTGLOBALERRORCOUNTERr(unit, &data)); 3475 (*error_count).bist_global_err_cnt = YDC_DDR_BIST_BIST_GET_FIELD(data, YDC_DDR_BIST, BIST_GLOBAL_ERROR_COUNTER, GLOBAL_ERR_CNT); 3476 3477 return SOC_E_NONE; 3478 } 3479 3480 int 3481 soc_sjc16_hx5_shmoo_drc_bist_err_cnt(int unit, int phy_ndx, 3482 ydc_ddr_bist_err_cnt_t *error_count) 3483 { 3484 uint32 rval; 3485 3486 SOC_IF_ERROR_RETURN(READ_DDR_BISTERROROCCURREDr(unit, &rval)); 3487 error_count->bist_err_occur = soc_reg_field_get(unit, 3488 DDR_BISTERROROCCURREDr, rval, ERROCCURREDf); 3489 3490 SOC_IF_ERROR_RETURN(READ_DDR_BISTFULLMASKERRORCOUNTERr(unit, &rval)); 3491 error_count->bist_full_err_cnt = soc_reg_field_get(unit, 3492 DDR_BISTFULLMASKERRORCOUNTERr, rval, FULLERRCNTf); 3493 3494 SOC_IF_ERROR_RETURN(READ_DDR_BISTSINGLEBITMASKERRORCOUNTERr(unit, &rval)); 3495 error_count->bist_single_err_cnt = soc_reg_field_get(unit, 3496 DDR_BISTSINGLEBITMASKERRORCOUNTERr, rval, SINGLEERRCNTf); 3497 3498 SOC_IF_ERROR_RETURN(READ_DDR_BISTGLOBALERRORCOUNTERr(unit, &rval)); 3499 error_count->bist_global_err_cnt = soc_reg_field_get(unit, 3500 DDR_BISTGLOBALERRORCOUNTERr, rval, GLOBALERRCNTf); 3501 3502 return SOC_E_NONE; 3503 } 3504 3505 #endif /* BCM_HELIX5_SUPPORT */ 3506 3507 3508 /* 3509 * Function: 3510 * soc_iproc_ddr_init 3511 * Purpose: 3512 * Initialize DDR of the embedded iProc subsystem 3513 * Parameters: 3514 * unit - unit number 3515 * Returns: 3516 * SOC_E_XXX 3517 */ 3518 int soc_iproc_ddr_init(int unit) 3519 { 3520 3521 if (!soc_feature(unit, soc_feature_iproc_ddr)) { 3522 return SOC_E_UNAVAIL; 3523 } 3524 3525 #ifdef BCM_HURRICANE2_SUPPORT 3526 if (SOC_IS_HURRICANE2(unit)) { 3527 return soc_iproc_hr2_ddr_init(unit); 3528 } 3529 #endif /* BCM_HURRICANE2_SUPPORT */ 3530 #ifdef BCM_GREYHOUND_SUPPORT 3531 if (SOC_IS_GREYHOUND(unit)) { 3532 return soc_iproc_gh_ddr_init(unit); 3533 } 3534 #endif /* BCM_GREYHOUND_SUPPORT */ 3535 #ifdef BCM_HURRICANE3_SUPPORT 3536 if (SOC_IS_HURRICANE3(unit)) { 3537 return soc_iproc_hr3_ddr_init(unit); 3538 } 3539 #endif /* BCM_HURRICANE3_SUPPORT */ 3540 3541 #ifdef BCM_HELIX5_SUPPORT 3542 if (SOC_IS_HELIX5(unit)) { 3543 return soc_iproc_hx5_ddr_init(unit); 3544 } 3545 #endif /* BCM_HURRICANE3_SUPPORT */ 3546 3547 return SOC_E_UNAVAIL; 3548 } 3549 #endif /* BCM_IPROC_DDR_SUPPORT */ 3550 3551 #endif