cmicm_fifodma.c (20378B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Purpose: CMICM FIFO DMA Driver 8 */ 9 10 #include <shared/bsl.h> 11 #include <shared/alloc.h> 12 #include <soc/drv.h> 13 #include <soc/debug.h> 14 #include <soc/cm.h> 15 #include <soc/fifodma_internal.h> 16 17 #if defined(BCM_CMICM_SUPPORT) 18 #include <soc/cmicm.h> 19 #endif 20 21 #if defined(BCM_ESW_SUPPORT) || \ 22 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) || defined(BCM_SBUSDMA_SUPPORT) 23 #if defined(BCM_CMICM_SUPPORT) 24 25 26 /** 27 * Function used to (partially) configure the DMA to 28 * write to a redirect writes from a register/memory 29 * to a host memory. 30 * 31 * 32 * @param unit 33 * @param ch - Channel used. should be between 0 and 3. 34 * @param is_mem 35 * @param mem -name of memory, if memory is used (0 otherwise). 36 * @param reg - name of register, if register used (0 otherwise). 37 * @param copyno 38 * @param force_entry_size - in a case that entry size does not match 39 * the register\memory size - ignore when equals to 0. 40 * @param host_entries - number of host entries used by the DMA. 41 * Must be a power of 2 between 64 and 16384. 42 * Note that only after host_entries writes does the DMA wrap around the host_buff. 43 * @param host_buff - local memory on which the DMA writes. should be big enough to 44 * allow host_entries writes, 45 * in other words whould be the size of host_entries * ( size of memory or 46 * register used, in bytes). 47 * 48 * Other register the caller may need to configure seperatly: 49 * CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_THRESHOLD - The amount of writes by the DMA until a 50 * threshold based interrupt occurs. 51 * 52 * TIMEOUT_COUNT field in CMIC_CMCx_FIFO_CHy_RD_DMA - Time between a DMA write and a 53 * timeout based interrupt. 54 * (May be set to 0 to disable timeout based interrupts). 55 * 56 * Endianess field in CMIC_CMCx_FIFO_CHy_RD_DMA. 57 * 58 * @return int - success or failure. 59 */ 60 static int 61 soc_fifo_dma_start_memreg(int unit, int ch, 62 int is_mem, soc_mem_t mem, soc_reg_t reg, 63 int copyno, int force_entry_size, 64 int host_entries, void *host_buff) 65 { 66 uint8 at; 67 uint32 rval, data_beats, sel; 68 int cmc; 69 int blk; 70 schan_msg_t msg; 71 int acc_type; 72 73 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 74 (BSL_META_U(unit, 75 "cmicm fifodma start for chan %d, host entries %d\n"), 76 ch, host_entries)); 77 78 if (soc_feature(unit, soc_feature_cmicm_multi_dma_cmc)) { 79 if (ch < 0 || ch > 12 || host_buff == NULL) { 80 return SOC_E_PARAM; 81 } 82 cmc = ch / 4; 83 ch = ch % 4; 84 } else { 85 cmc = SOC_PCI_CMC(unit); 86 if (ch < 0 || ch > 3 || host_buff == NULL) { 87 return SOC_E_PARAM; 88 } 89 } 90 91 switch (host_entries) { 92 case 64: sel = 0; break; 93 case 128: sel = 1; break; 94 case 256: sel = 2; break; 95 case 512: sel = 3; break; 96 case 1024: sel = 4; break; 97 case 2048: sel = 5; break; 98 case 4096: sel = 6; break; 99 case 8192: sel = 7; break; 100 case 16384: sel = 8; break; 101 default: 102 return SOC_E_PARAM; 103 } 104 105 #ifdef BCM_IPFIX_SUPPORT 106 #ifdef BCM_PETRA_SUPPORT 107 if (!SOC_IS_DPP(unit) && !SOC_IS_DFE(unit)) 108 #endif 109 { 110 if (mem != ING_IPFIX_EXPORT_FIFOm && mem != EGR_IPFIX_EXPORT_FIFOm && 111 mem != L2_MOD_FIFOm && mem != FT_EXPORT_FIFOm && 112 mem != FT_EXPORT_DATA_ONLYm && 113 mem != EGR_SER_FIFOm && mem != ING_SER_FIFOm && 114 mem != CENTRAL_CTR_EVICTION_FIFOm) { 115 return SOC_E_BADID; 116 } 117 } 118 #endif 119 120 /* Differentiate between reg and mem to get address, size and block */ 121 if ((!is_mem) && SOC_REG_IS_VALID(unit, reg)) { 122 data_beats = BYTES2WORDS(soc_reg_bytes(unit, reg)); 123 rval = soc_reg_addr_get(unit, reg, REG_PORT_ANY, 0, 124 SOC_REG_ADDR_OPTION_NONE, &blk, &at); 125 } else { 126 data_beats = soc_mem_entry_words(unit, mem); 127 if (copyno == MEM_BLOCK_ANY) { 128 copyno = SOC_MEM_BLOCK_ANY(unit, mem); 129 } 130 rval = soc_mem_addr_get(unit, mem, 0, copyno, 0, &at); 131 blk = SOC_BLOCK2SCH(unit, copyno); 132 } 133 /*Force entry size*/ 134 if (force_entry_size > 0) 135 { 136 data_beats = BYTES2WORDS(force_entry_size); 137 } 138 139 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_SBUS_START_ADDRESS_OFFSET(cmc, ch), rval); 140 141 schan_msg_clear(&msg); 142 if (is_mem) { 143 acc_type = SOC_MEM_ACC_TYPE(unit, mem); 144 } else { 145 acc_type = 0; 146 } 147 soc_schan_header_cmd_set(unit, &msg.header, FIFO_POP_CMD_MSG, blk, 0, 148 acc_type, 4, 0, 0); 149 /* Set 1st schan ctrl word as opcode */ 150 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_OPCODE_OFFSET(cmc, ch), msg.dwords[0]); 151 152 rval = soc_cm_l2p(unit, host_buff); 153 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET(cmc, ch), 154 rval); 155 156 rval = soc_pci_read(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch)); 157 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, BEAT_COUNTf, 158 data_beats); 159 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, 160 HOST_NUM_ENTRIES_SELf, sel); 161 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, ABORTf, 0); 162 163 /* Note: Following might need to be tuned */ 164 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, 165 TIMEOUT_COUNTf, 1000); 166 /* Note: Following could be removed ?? */ 167 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, 168 NACK_FATALf, 1); 169 170 if (soc_feature(unit, soc_feature_multi_sbus_cmds)) { 171 172 } 173 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch), rval); 174 175 if (SOC_IS_ARAD(unit) || SOC_IS_DFE(unit)) { 176 /* Always 1 in Arad when interrupt mechanism is not enabled */ 177 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(cmc, ch), 178 1); 179 } else { 180 /* Note: Following might need to be tuned */ 181 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(cmc, ch), 182 host_entries/10); 183 } 184 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, ENABLEf, 1); 185 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch), rval); 186 return SOC_E_NONE; 187 } 188 189 /******************************************* 190 * @function _cmicm_fifodma_start 191 * purpose to start fifo dma channel 192 * 193 * @param unit [in] unit # 194 * @param ch [in] channel number 195 * 196 * @returns SOC_E_PARAM 197 * @returns SOC_E_NONE 198 * 199 * @end 200 */ 201 static int 202 _cmicm_fifodma_start(int unit, int ch, int is_mem, 203 soc_mem_t mem, soc_reg_t reg, 204 int copyno, int force_entry_size, 205 int host_entries, void *host_buff) 206 { 207 return soc_fifo_dma_start_memreg(unit, ch, 208 is_mem, mem, reg, 209 copyno, force_entry_size, host_entries, host_buff); 210 } 211 212 /******************************************* 213 * @function _cmicm_fifodma_stop 214 * purpose to stop fifo dma channel 215 * 216 * @param unit [in] unit # 217 * @param chan [in] channel number 218 * 219 * @returns SOC_E_BUSY 220 * @returns SOC_E_NONE 221 * 222 * @end 223 */ 224 static int 225 _cmicm_fifodma_stop(int unit, int ch) 226 { 227 int cmc, iter = 0; 228 uint32 rval; 229 int to = SAL_BOOT_QUICKTURN ? 30000000 : 10000000; 230 231 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 232 (BSL_META_U(unit, 233 "cmicm fifodma stop for chan %d\n"), ch)); 234 235 if (soc_feature(unit, soc_feature_cmicm_multi_dma_cmc)) { 236 if (ch < 0 || ch > 12) { 237 return SOC_E_PARAM; 238 } 239 cmc = ch / 4; 240 ch = ch % 4; 241 } else { 242 cmc = SOC_PCI_CMC(unit); 243 if (ch < 0 || ch > 3) { 244 return SOC_E_PARAM; 245 } 246 } 247 248 rval = soc_pci_read(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch)); 249 if (!soc_reg_field_get(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, rval, ENABLEf)) { 250 return SOC_E_NONE; 251 } 252 rval = soc_pci_read(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch)); 253 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, ABORTf, 1); 254 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch), rval); 255 256 sal_udelay(1000); 257 rval = soc_pci_read(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_STAT_OFFSET(cmc, ch)); 258 259 while (soc_reg_field_get(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_STATr, rval, DONEf) == 0 && 260 iter++ <to) { 261 sal_udelay(1000); 262 rval = soc_pci_read(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_STAT_OFFSET(cmc, ch)); 263 } 264 rval = soc_pci_read(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch)); 265 soc_reg_field_set(unit, CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr, &rval, ENABLEf, 0); 266 soc_pci_write(unit, CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(cmc, ch), rval); 267 268 if (iter >= to) { 269 LOG_ERROR(BSL_LS_SOC_FIFODMA, 270 (BSL_META_U(unit, 271 "FIFO DMA abort failed !!\n"))); 272 return SOC_E_INTERNAL; 273 } 274 return SOC_E_NONE; 275 } 276 277 278 /******************************************* 279 * @function _cmicm_fifodma_intr_enable 280 * purpose to enable interrupt 281 * 282 * @param unit [in] unit # 283 * @param ch [in] channel 284 * 285 * @returns SOC_E_BUSY 286 * @returns SOC_E_NONE 287 * 288 * @end 289 */ 290 static int 291 _cmicm_fifodma_intr_enable(int unit, int ch) 292 { 293 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 294 (BSL_META_U(unit, 295 "cmicm fifodma interrupt enable for chan %d\n"), ch)); 296 297 soc_cmicm_intr0_enable(unit, IRQ_CMCx_FIFO_CH_DMA(ch)); 298 299 return 0; 300 } 301 302 /******************************************* 303 * @function _cmicm_fifodma_intr_disable 304 * purpose to disable interrupt 305 * 306 * @param unit [in] unit # 307 * @param ch [in] channel 308 * 309 * @returns SOC_E_BUSY 310 * @returns SOC_E_NONE 311 * 312 * @end 313 */ 314 static int 315 _cmicm_fifodma_intr_disable(int unit, int ch) 316 { 317 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 318 (BSL_META_U(unit, 319 "cmicm fifodma interrupt disable for chan %d\n"), ch)); 320 321 soc_cmicm_intr0_disable(unit, IRQ_CMCx_FIFO_CH_DMA(ch)); 322 323 return 0; 324 } 325 326 /******************************************* 327 * @function _cmicm_fifodma_get_read_ptr 328 * purpose to get read ptr 329 * 330 * @param unit [in] unit # 331 * 332 * @returns SOC_E_BUSY 333 * @returns SOC_E_NONE 334 * 335 * @end 336 */ 337 static int 338 _cmicm_fifodma_get_read_ptr(int unit, int chan, void **host_ptr, int *count) 339 { 340 return 0; 341 } 342 343 /******************************************* 344 * @function _cmicm_fifodma_advance_read_ptr 345 * purpose to advance read ptr 346 * 347 * @param unit [in] unit # 348 * 349 * @returns SOC_E_BUSY 350 * @returns SOC_E_NONE 351 * 352 * @end 353 */ 354 static int 355 _cmicm_fifodma_advance_read_ptr(int unit, int chan, int count) 356 { 357 return 0; 358 } 359 360 /******************************************* 361 * @function _cmicm_fifodma_set_entries_read 362 * purpose to read set entries 363 * 364 * @param unit [in] unit # 365 * 366 * @returns SOC_E_BUSY 367 * @returns SOC_E_NONE 368 * 369 * @end 370 */ 371 static int 372 _cmicm_fifodma_set_entries_read(int unit, int ch, uint32 num) 373 { 374 int cmc; 375 376 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 377 (BSL_META_U(unit, 378 "cmicm fifodma set %d entries for chan %d\n"), num, ch)); 379 380 if (soc_feature(unit, soc_feature_cmicm_multi_dma_cmc)) { 381 if (ch < 0 || ch > 12) { 382 return SOC_E_PARAM; 383 } 384 cmc = ch / 4; 385 ch = ch % 4; 386 } else { 387 cmc = SOC_PCI_CMC(unit); 388 if (ch < 0 || ch > 3) { 389 return SOC_E_PARAM; 390 } 391 } 392 393 394 395 soc_pci_write(unit, 396 CMIC_CMCx_FIFO_CHy_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(cmc, ch), num); 397 398 return SOC_E_NONE; 399 } 400 401 /******************************************* 402 * @function _cmicm_fifodma_num_entries_get 403 * purpose to get number of entries 404 * 405 * @param unit [in] unit # 406 * 407 * @returns SOC_E_BUSY 408 * @returns SOC_E_NONE 409 * 410 * @end 411 */ 412 static int 413 _cmicm_fifodma_num_entries_get(int unit, int ch, int *count) 414 { 415 uint32 val = 0; 416 int cmc; 417 418 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 419 (BSL_META_U(unit, 420 "cmicm fifodma entries get for chan %d\n"), ch)); 421 422 if (soc_feature(unit, soc_feature_cmicm_multi_dma_cmc)) { 423 if (ch < 0 || ch > 12) { 424 return SOC_E_PARAM; 425 } 426 cmc = ch / 4; 427 ch = ch % 4; 428 } else { 429 cmc = SOC_PCI_CMC(unit); 430 if (ch < 0 || ch > 3) { 431 return SOC_E_PARAM; 432 } 433 } 434 435 val = soc_pci_read(unit, 436 CMIC_CMCx_FIFO_CHy_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(cmc, ch)); 437 438 *count = val; 439 440 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 441 (BSL_META_U(unit, 442 "cmicm fifodma %d entries get for chan %d\n"), val, ch)); 443 444 if (val) { 445 return SOC_E_NONE; 446 } 447 448 return SOC_E_EMPTY; 449 } 450 451 /******************************************* 452 * @function _cmicm_fifodma_status_clear 453 * purpose to clear fifo dma channel status 454 * 455 * @param unit [in] unit # 456 * @param chan [in] channel number 457 * 458 * @returns SOC_E_BUSY 459 * @returns SOC_E_NONE 460 * 461 * @end 462 */ 463 static int 464 _cmicm_fifodma_status_clear(int unit, int chan) 465 { 466 soc_reg_t stat_clr_reg; 467 uint32 stat_clr_addr; 468 uint32 stat_clr_mask; 469 int cmc; 470 471 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 472 (BSL_META_U(unit, 473 "cmicm fifodma status clear for chan %d\n"), chan)); 474 475 if (soc_feature(unit, soc_feature_cmicm_multi_dma_cmc)) { 476 if (chan < 0 || chan > 12) { 477 return SOC_E_PARAM; 478 } 479 cmc = chan / 4; 480 chan = chan % 4; 481 } else { 482 cmc = SOC_PCI_CMC(unit); 483 if (chan < 0 || chan > 3) { 484 return SOC_E_PARAM; 485 } 486 } 487 488 stat_clr_reg = CMIC_CMC0_FIFO_CH1_RD_DMA_STAT_CLRr; 489 stat_clr_mask = 0; 490 soc_reg_field_set(unit, stat_clr_reg, &stat_clr_mask, HOSTMEM_TIMEOUTf, 1); 491 soc_reg_field_set(unit, stat_clr_reg, &stat_clr_mask, HOSTMEM_OVERFLOWf, 1); 492 493 stat_clr_addr = CMIC_CMCx_FIFO_CHy_RD_DMA_STAT_CLR_OFFSET(cmc, chan); 494 495 soc_pci_write(unit, stat_clr_addr, stat_clr_mask); 496 497 return SOC_E_NONE; 498 } 499 500 /******************************************* 501 * @function _cmicm_fifodma_status_get 502 * purpose to obtain fifo dma channel status 503 * 504 * @param unit [in] unit # 505 * @param chan [in] channel number 506 * 507 * @returns SOC_E_BUSY 508 * @returns SOC_E_NONE 509 * 510 * @end 511 */ 512 static int 513 _cmicm_fifodma_status_get(int unit, int chan, uint32 *status) 514 { 515 uint32 stat_addr; 516 int cmc; 517 518 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 519 (BSL_META_U(unit, 520 "cmicm fifodma status get for chan %d\n"), chan)); 521 522 if (soc_feature(unit, soc_feature_cmicm_multi_dma_cmc)) { 523 if (chan < 0 || chan > 12) { 524 return SOC_E_PARAM; 525 } 526 cmc = chan / 4; 527 chan = chan % 4; 528 } else { 529 cmc = SOC_PCI_CMC(unit); 530 if (chan < 0 || chan > 3) { 531 return SOC_E_PARAM; 532 } 533 } 534 535 stat_addr = CMIC_CMCx_FIFO_CHy_RD_DMA_STAT_OFFSET(cmc, chan); 536 537 *status = soc_pci_read(unit, stat_addr); 538 539 return SOC_E_NONE; 540 } 541 542 /******************************************* 543 * @function _cmicm_fifodma_masks_get 544 * purpose to obtain fifodma masks 545 * 546 * @param unit [in] unit # 547 * @param chan [in] channel number 548 * 549 * @returns SOC_E_BUSY 550 * @returns SOC_E_NONE 551 * 552 * @end 553 */ 554 static int 555 _cmicm_fifodma_masks_get(int unit, uint32 *hostmem_timeout, uint32 *hostmem_overflow, uint32 *error, uint32 *done) 556 { 557 int rv = SOC_E_NONE; 558 559 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 560 (BSL_META_U(unit, 561 "cmicm fifodma masks get\n"))); 562 563 *hostmem_timeout = 1 << 3; 564 *hostmem_overflow = 1 << 2; 565 *error = 1 << 0; 566 *done = 1 << 4; 567 568 return rv; 569 } 570 571 /******************************************* 572 * @function _cmicm_l2mod_sbus_fifo_field_set 573 * obtain l2 mod sbus field set 574 * 575 * @param unit [in] unit # 576 * @param field [in] field 577 * @param enable [in] enable 578 * 579 * @returns SOC_E_BUSY 580 * @returns SOC_E_NONE 581 * 582 * @end 583 */ 584 static int 585 _cmicm_l2mod_sbus_fifo_field_set(int unit, soc_field_t field, int enable) 586 { 587 uint32 rval = 0; 588 uint32 fval = enable?1:0; 589 590 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 591 (BSL_META_U(unit, 592 "cmicm l2mod sbus fifo set\n"))); 593 594 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIDENT(unit) || 595 SOC_IS_TITAN2(unit) || SOC_IS_TITAN(unit)) { 596 if(soc_reg_field_valid(unit, AUX_ARB_CONTROLr, field)) { 597 SOC_IF_ERROR_RETURN(READ_AUX_ARB_CONTROLr(unit, &rval)); 598 599 soc_reg_field_set(unit, AUX_ARB_CONTROLr, &rval, field, fval); 600 601 SOC_IF_ERROR_RETURN(WRITE_AUX_ARB_CONTROLr(unit, rval)); 602 } 603 return SOC_E_NONE; 604 } 605 return SOC_E_UNAVAIL; 606 } 607 608 /******************************************* 609 * @function _cmicm_l2mod_sbus_fifo_field_get 610 * obtain l2 mod sbus field get 611 * 612 * @param unit [in] unit # 613 * @param field [in] field 614 * @param enable [in] enable 615 * 616 * @returns SOC_E_BUSY 617 * @returns SOC_E_NONE 618 * 619 * @end 620 */ 621 static int 622 _cmicm_l2mod_sbus_fifo_field_get(int unit, soc_field_t field, int *enable) 623 { 624 uint32 reg = 0; 625 uint32 fval = 0; 626 627 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 628 (BSL_META_U(unit, 629 "cmicm l2mod sbus fifo get\n"))); 630 631 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIDENT(unit) || 632 SOC_IS_TITAN2(unit) || SOC_IS_TITAN(unit)) { 633 if(soc_reg_field_valid(unit, AUX_ARB_CONTROLr, field)) { 634 SOC_IF_ERROR_RETURN(READ_AUX_ARB_CONTROLr(unit, ®)); 635 636 fval = soc_reg_field_get(unit, AUX_ARB_CONTROLr, reg, field); 637 } 638 *enable = fval?1:0; 639 return SOC_E_NONE; 640 } 641 642 return SOC_E_UNAVAIL; 643 } 644 645 /******************************************* 646 * @function cmicm_fifodma_init 647 * purpose API to Initialize cmicm FIFO DMA 648 * 649 * @param unit [in] unit 650 * @param drv [out] soc_fifodma_drv_t pointer 651 * 652 * @returns SOC_E_NONE 653 * @returns SOC_E_XXX 654 * 655 * @end 656 */ 657 int cmicm_fifodma_init(int unit, soc_fifodma_drv_t *drv) 658 { 659 int rv = SOC_E_NONE; 660 661 LOG_VERBOSE(BSL_LS_SOC_FIFODMA, 662 (BSL_META_U(unit, 663 "cmicm fifo dma init\n"))); 664 665 drv->fifodma_start = _cmicm_fifodma_start; 666 drv->fifodma_stop = _cmicm_fifodma_stop; 667 drv->fifodma_intr_enable = _cmicm_fifodma_intr_enable; 668 drv->fifodma_intr_disable = _cmicm_fifodma_intr_disable; 669 drv->fifodma_get_read_ptr = _cmicm_fifodma_get_read_ptr; 670 drv->fifodma_advance_read_ptr = _cmicm_fifodma_advance_read_ptr; 671 drv->fifodma_set_entries_read = _cmicm_fifodma_set_entries_read; 672 drv->fifodma_num_entries_get = _cmicm_fifodma_num_entries_get; 673 drv->fifodma_status_clear = _cmicm_fifodma_status_clear; 674 drv->fifodma_status_get = _cmicm_fifodma_status_get; 675 drv->fifodma_masks_get = _cmicm_fifodma_masks_get; 676 drv->l2mod_sbus_fifo_field_set = _cmicm_l2mod_sbus_fifo_field_set; 677 drv->l2mod_sbus_fifo_field_get = _cmicm_l2mod_sbus_fifo_field_get; 678 679 return(rv); 680 } 681 682 /******************************************* 683 * @function cmicm_fifodma_deinit 684 * purpose API to Deinitialize cmicm FIFO DMA 685 * 686 * @param unit [in] unit 687 * @param drv [in] soc_fifodma_drv_t pointer 688 * 689 * @returns SOC_E_NONE 690 691 * 692 * @end 693 */ 694 int cmicm_fifodma_deinit(int unit, soc_fifodma_drv_t *drv) 695 { 696 drv->fifodma_start = NULL; 697 drv->fifodma_stop = NULL; 698 drv->fifodma_intr_enable = NULL; 699 drv->fifodma_intr_disable = NULL; 700 drv->fifodma_get_read_ptr = NULL; 701 drv->fifodma_advance_read_ptr = NULL; 702 drv->fifodma_set_entries_read = NULL; 703 drv->fifodma_num_entries_get = NULL; 704 drv->fifodma_status_clear = NULL; 705 drv->fifodma_status_get = NULL; 706 drv->fifodma_masks_get = NULL; 707 drv->l2mod_sbus_fifo_field_set = NULL; 708 drv->l2mod_sbus_fifo_field_get = NULL; 709 710 return SOC_E_NONE; 711 } 712 713 #endif /* BCM_FIFODMA_SUPPORT */ 714 #endif /* BCM_ESW_SUPPORT */ 715