linux-kernel-bde.c (148254B)
1 /* 2 * Copyright 2017 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, version 2, as 6 * published by the Free Software Foundation (the "GPL"). 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License version 2 (GPLv2) for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * version 2 (GPLv2) along with this source code. 15 */ 16 /* 17 * $Id: linux-kernel-bde.c,v 1.414 Broadcom SDK $ 18 * $Copyright: (c) 2005 Broadcom Corp. 19 * All Rights Reserved.$ 20 * 21 * Linux Kernel BDE 22 * 23 */ 24 25 #include <gmodule.h> 26 #include <linux-bde.h> 27 #include <linux_dma.h> 28 #include <mpool.h> 29 #include <linux/delay.h> 30 #include <linux/types.h> 31 #include <sdk_config.h> 32 #include <soc/devids.h> 33 #include <soc/cmic.h> 34 #include <soc/drv.h> 35 #include <linux/version.h> 36 37 #include "linux_shbde.h" 38 39 40 #ifdef __GNUC__ 41 #if __GNUC__ == 8 42 /* 43 * Prevent gcc 8.1.10 using a compiler inline memcpy even if using -fno-builtin or 44 * -fno-builtin-memcpy . 45 * __inline_memcpy and __memcpy are kernel functions that may be used instead, 46 * for either an inline or non-inline implementations of the function 47 */ 48 #define MEMCPY __inline_memcpy 49 #else 50 #define MEMCPY memcpy 51 #endif /* __GNUC__ == 8 */ 52 #else /* ifdef __GNUC__ */ 53 #define MEMCPY memcpy 54 #endif /* ifdef __GNUC__ */ 55 56 #define PCI_USE_INT_NONE (-1) 57 #define PCI_USE_INT_INTX (0) 58 #define PCI_USE_INT_MSI (1) 59 #define PCI_USE_INT_MSIX (2) 60 #ifdef CONFIG_PCI_MSI 61 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,110)) 62 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 63 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) 64 #endif 65 #define msi_control_reg(base) (base + PCI_MSI_FLAGS) 66 #endif 67 #endif 68 MODULE_AUTHOR("Broadcom Corporation"); 69 MODULE_DESCRIPTION("Kernel BDE"); 70 MODULE_LICENSE("GPL"); 71 72 /* PCIe max payload */ 73 int maxpayload = 256; 74 LKM_MOD_PARAM(maxpayload, "i", int, 0); 75 MODULE_PARM_DESC(maxpayload, 76 "Limit maximum payload size and request size on PCIe devices"); 77 78 /* Use MSI or MSIX interrupts */ 79 int usemsi = -1; 80 LKM_MOD_PARAM(usemsi, "i", int, 0); 81 MODULE_PARM_DESC(usemsi, 82 "Use MSI/ MSIX interrupts if supported by kernel"); 83 84 /* Ignore all recognized devices (for debug purposes) */ 85 int nodevices; 86 LKM_MOD_PARAM(nodevices, "i", int, 0); 87 MODULE_PARM_DESC(nodevices, 88 "Ignore all recognized devices (default no)"); 89 90 int msixcnt = 1; 91 92 /* 93 * This usually is defined at /usr/include/linux/pci_ids.h 94 * But this ID is newer. 95 */ 96 #ifndef PCI_DEVICE_ID_PLX_9656 97 #define PCI_DEVICE_ID_PLX_9656 0x9656 98 #endif 99 100 #ifndef PCI_DEVICE_ID_PLX_9056 101 #define PCI_DEVICE_ID_PLX_9056 0x9056 102 #endif 103 104 /* For 2.4.x kernel support */ 105 #ifndef IRQF_SHARED 106 #define IRQF_SHARED SA_SHIRQ 107 #endif 108 109 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 110 typedef unsigned long resource_size_t; 111 #endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) */ 112 113 #ifdef BCM_ICS 114 #define BCM_ICS_CMIC_BASE 0x08000000 115 #else 116 117 /* Force interrupt line */ 118 static int forceirq = -1; 119 static uint32_t forceirqubm = 0xffffffff; 120 LKM_MOD_PARAM(forceirq, "i", int, 0); 121 LKM_MOD_PARAM(forceirqubm, "i", uint, 0); 122 MODULE_PARM_DESC(forceirq, 123 "Override IRQ line assigned by boot loader"); 124 MODULE_PARM_DESC(forceirqubm, 125 "Bitmap for overriding the IRQ line assigned by boot loader for given units"); 126 127 /* Create SPI slave device (cannot be probed) */ 128 static uint32_t spi_devid = 0; 129 LKM_MOD_PARAM(spi_devid, "i", uint, 0); 130 MODULE_PARM_DESC(spi_devid, 131 "Create SPI slave device using this device ID"); 132 133 /* Select SPI device revision (cannot be probed) */ 134 static uint32_t spi_revid = 1; 135 LKM_MOD_PARAM(spi_revid, "i", uint, 0); 136 MODULE_PARM_DESC(spi_revid, 137 "Select device revision for SPI slave device"); 138 139 #endif /* BCM_ICS */ 140 141 /* Debug output */ 142 static int debug; 143 LKM_MOD_PARAM(debug, "i", int, 0); 144 MODULE_PARM_DESC(debug, 145 "Set debug level (default 0"); 146 /* Use high memory for DMA */ 147 148 /* module param for probing EB devices. */ 149 static char *eb_bus; 150 LKM_MOD_PARAM(eb_bus, "s", charp, 0); 151 MODULE_PARM_DESC(eb_bus, 152 "List of EB devices on platform. Input format (BA=%x IRQ=%d RD16=%d WR16=%d"); 153 154 #ifdef KEYSTONE 155 /* Force SPI Frequency */ 156 static int spifreq = 0; 157 LKM_MOD_PARAM(spifreq, "i", int, 0); 158 MODULE_PARM_DESC(spifreq, 159 "Force SPI Frequency for Keystone CPU (0 for default frequency)"); 160 #endif 161 162 163 /* Compatibility */ 164 #ifdef LKM_2_4 165 #define _ISR_RET void 166 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d, struct pt_regs *_r 167 #define IRQ_NONE 168 #define IRQ_HANDLED 169 #define SYNC_IRQ(_i) synchronize_irq() 170 #else /* LKM_2_6 */ 171 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) 172 #define _ISR_RET irqreturn_t 173 #else 174 #define _ISR_RET int 175 #endif 176 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) 177 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d 178 #else 179 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d, struct pt_regs *_r 180 typedef irqreturn_t (*irq_handler_t)(int _i, void *_d, struct pt_regs *_r); 181 #endif 182 #define SYNC_IRQ(_i) synchronize_irq(_i) 183 char * ___strtok; 184 char * strtok(char * s,const char * ct) 185 { 186 char *sbegin, *send; 187 sbegin = s ? s : ___strtok; 188 if (!sbegin) { 189 return NULL; 190 } 191 sbegin += strspn(sbegin,ct); 192 if (*sbegin == '\0') { 193 ___strtok = NULL; 194 return( NULL ); 195 } 196 send = strpbrk( sbegin, ct); 197 if (send && *send != '\0') 198 *send++ = '\0'; 199 ___strtok = send; 200 return (sbegin); 201 } 202 LKM_EXPORT_SYM(___strtok); 203 LKM_EXPORT_SYM(strtok); 204 #endif /* LKM_2_x */ 205 206 /* PCIe capabilities */ 207 #ifndef PCI_CAP_ID_EXP 208 #define PCI_CAP_ID_EXP 0x10 209 #endif 210 #ifndef PCI_EXP_DEVCAP 211 #define PCI_EXP_DEVCAP 4 212 #endif 213 #ifndef PCI_EXP_DEVCTL 214 #define PCI_EXP_DEVCTL 8 215 #endif 216 #ifndef PCI_EXT_CAP_START 217 #define PCI_EXT_CAP_START 0x100 218 #endif 219 #ifndef PCI_EXT_CAP_ID 220 #define PCI_EXT_CAP_ID(_hdr) (_hdr & 0x0000ffff) 221 #endif 222 #ifndef PCI_EXT_CAP_VER 223 #define PCI_EXT_CAP_VER(_hdr) ((_hdr >> 16) & 0xf) 224 #endif 225 #ifndef PCI_EXT_CAP_NEXT 226 #define PCI_EXT_CAP_NEXT(_hdr) ((_hdr >> 20) & 0xffc) 227 #endif 228 #ifndef PCI_EXT_CAP_ID_VNDR 229 #define PCI_EXT_CAP_ID_VNDR 0x0b 230 #endif 231 232 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 233 #define PCI_FIND_DEV(_d, _v, _fr) pci_find_device(_d, _v, _fr) 234 #else 235 #define PCI_FIND_DEV(_d, _v, _fr) pci_get_device(_d, _v, _fr) 236 #endif 237 238 #if defined(CONFIG_RESOURCES_64BIT) || defined(CONFIG_PHYS_ADDR_T_64BIT) 239 #define PHYS_ADDR_IS_64BIT 240 #endif 241 242 /* Structure of private SPI device */ 243 struct spi_dev { 244 uint8 cid; /* Chip ID */ 245 uint32 part; /* Part number of the chip */ 246 uint8 rev; /* Revision of the chip */ 247 void *robo; /* ptr to robo info required to access SPI */ 248 unsigned short phyid_high; /* PHYID HIGH in MII regs of detected chip */ 249 unsigned short phyid_low; /* PHYID LOW in MII regs of detected chip */ 250 }; 251 252 struct bde_spi_device_id { 253 unsigned short phyid_high; /* PHYID HIGH in MII regs of detected chip */ 254 unsigned short phyid_low; /* PHYID LOW in MII regs of detected chip */ 255 uint32 model_info; 256 uint32 rev_info; 257 uint32 spifreq; 258 }; 259 260 /* Control Data */ 261 typedef struct bde_ctrl_s { 262 struct list_head list; 263 264 /* Specify the type of device, pci, spi, switch, ether ... */ 265 uint32 dev_type; 266 267 int domain_no; 268 int bus_no; 269 int be_pio; 270 int use_msi; 271 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 272 struct msix_entry *entries; 273 #endif 274 int msix_cnt; 275 union { 276 /* Linux PCI device pointer */ 277 struct pci_dev* _pci_dev; 278 279 /* SPI device pointer */ 280 struct spi_dev* _spi_dev; 281 } dev; 282 #define pci_device dev._pci_dev 283 #define spi_device dev._spi_dev 284 285 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 286 struct device *dma_dev; 287 #endif 288 289 /* Physical addresses */ 290 resource_size_t phys_address; 291 resource_size_t phys_address1; 292 resource_size_t phys_address2; 293 294 /* Secondary mapped base address */ 295 sal_vaddr_t alt_base_addr; 296 297 /* BDE device description */ 298 ibde_dev_t bde_dev; 299 300 /* Interrupt Handling */ 301 int iLine; /* Interrupt line */ 302 void (*isr)(void *); 303 void *isr_data; 304 305 /* 306 * Controls to allow two drivers to share a single set of 307 * hardware registers. Typically a kernel driver will handle 308 * a subset of hardware interrupts and a user mode driver 309 * will handle the remaining interrupts. 310 */ 311 void (*isr2)(void *); 312 void *isr2_data; 313 uint32_t fmask; /* Interrupts controlled by secondary handler */ 314 uint32_t imask; /* Enabled interrupts for primary handler */ 315 uint32_t imask2; /* Enabled interrupts for secondary handler */ 316 spinlock_t lock; /* Lock for IRQ mask synchronization */ 317 318 /* Hardware abstraction for shared BDE functions */ 319 shbde_hal_t shbde; 320 321 /* Device state : BDE_DEV_STATE_REMOVED/CHANGED */ 322 uint32 dev_state; 323 324 /* inst_id */ 325 uint32 inst_id; 326 } bde_ctrl_t; 327 328 static bde_ctrl_t _devices[LINUX_BDE_MAX_DEVICES]; 329 static int _ndevices = 0; 330 static int _switch_ndevices = 0; 331 static int _ether_ndevices = 0; 332 static int _cpu_ndevices = 0; 333 334 #define VALID_DEVICE(_n) ((_n >= 0) && (_n < _ndevices)) 335 336 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 337 #define ICFG_CHIP_ID_REG 0x10236000 338 #define IHOST_CMICX_MAX_INTRS 128 339 static uint32 iproc_cmicx_irqs[IHOST_CMICX_MAX_INTRS]; 340 #endif 341 342 /* CPU MMIO area used with CPU cards provided on demo boards */ 343 #if defined(BCM_SAND_SUPPORT) && (defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__)) 344 static void *cpu_address = NULL; 345 #endif 346 347 348 /* Broadcom BCM4704 */ 349 #define BCM4704_VENDOR_ID 0x14E4 350 #define BCM4704_DEVICE_ID 0x4704 351 352 /* SiByte PCI Host */ 353 #define SIBYTE_PCI_VENDOR_ID 0x166D 354 #define SIBYTE_PCI_DEVICE_ID 0x0001 355 356 /* Intel 21150 PCI-PCI Bridge */ 357 #define DC21150_VENDOR_ID 0x1011 358 #define DC21150_DEVICE_ID 0x0022 359 360 /* HiNT HB4 PCI-PCI Bridge (21150 clone) */ 361 #define HINT_HB4_VENDOR_ID 0x3388 362 #define HINT_HB4_DEVICE_ID 0x0022 363 364 /* Pericom PI7C8150 PCI-PCI Bridge (21150 clone) */ 365 #define PI7C8150_VENDOR_ID 0x12D8 366 #define PI7C8150_DEVICE_ID 0x8150 367 368 /* Pericom PI7C9X130 PCI-PCIE Bridge */ 369 #define PCI_VNDID_PERICOM 0x12D8 370 #define PCI_DEVID_PI7C9X130 0xE130 371 #define DEV_CTRL_REG 0xb8 372 373 #define MAX_PAYLOAD_256B (1 << 5) 374 #define MAX_PAYLOAD_512B (2 << 5) 375 #define MAX_READ_REQ_256B (1 << 12) 376 377 378 /* Freescale 8548 PCI-E host Bridge */ 379 #define FSL_VENDOR_ID 0x1957 380 #define FSL8548PCIE_DEVICE_ID 0x0013 381 #define FSL2020EPCIE_DEVICE_ID 0x0070 382 #define FSL8548PCIE_DEV_CTRL_REG 0x54 383 384 /* 4716 PCI-E host Bridge */ 385 #define BCM4716_VENDOR_ID 0x14e4 386 #define BCM4716PCIE_DEVICE_ID 0x4716 387 #define BCM4716PCIE_DEV_CAP_REG 0xd4 388 #define BCM4716PCIE_DEV_CTRL_REG 0xd8 389 #define BCM53000_VENDOR_ID 0x14e4 390 #define BCM53000PCIE_DEVICE_ID 0x5300 391 392 #define BCM53000PCIE_DEV(port) ((port == 0) ? pcie0 : pcie1) 393 #define BCM53000PCIE_BASE(port) ((port == 0) ? 0xb8005000 : 0xb800e000) 394 #define BCM53000PCIE_FUNC0_COFIG_SPACE 0x400 395 #define BCM53000PCIE_SROM_SPACE 0x800 396 #define BCM53000PCIE_DEV_CAP_REG 0xd4 397 #define BCM53000PCIE_DEV_CTRL_REG 0xd8 398 #define BCM53000PCIE_MAX_PAYLOAD_MASK 0x7 399 #define BCM53000PCIE_CAP_MAX_PAYLOAD_256B (1 << 0) 400 #define BCM53000PCIE_DEFAULT_STATUS 0x00100146 401 402 /* 16bit wide register. offset 14, 14*2 = 0x1c */ 403 #define BCM53000PCIE_SPROM_OFFSET 0x1c 404 /* bit 15:13 spromData.MaxPayloadSize. 1: 256 bytes */ 405 #define BCM53000PCIE_SPROM_MAX_PAYLOAD_MASK 0xe000 406 #define BCM53000PCIE_SPROM_MAX_PAYLOAD_256B (1 << 13) 407 408 409 /* Intel 21150, HiNT HB4 and other 21150-compatible */ 410 #define PCI_CFG_DEC21150_SEC_CLK 0x68 411 412 #define BCM4704_ENUM_BASE 0x18000000 413 #define BCM4704_MEMC_BASE (BCM4704_ENUM_BASE+0x8000) 414 #define BCM4704_MEMC_PRIORINV 0x18 415 416 /* PLX PCI-E Switch */ 417 #define PLX_PEX8608_DEV_ID 0x8608 418 #define PLX_PEX8617_DEV_ID 0x8617 419 #define PLX_PEX86XX_DEV_CTRL_REG 0x70 420 421 /* Broadcom BCM58525 */ 422 #define BCM58525_PCI_VENDOR_ID 0x14E4 423 #define BCM58525_PCI_DEVICE_ID 0x8025 424 #define BCM58522_PCI_DEVICE_ID 0x8022 425 426 /* Broadcom BCM58712 */ 427 #define BCM58712_PCI_VENDOR_ID 0x14E4 428 #define BCM58712_PCI_DEVICE_ID 0x168E 429 430 /* Default gicd address if not available in DTB */ 431 #define IHOST_GICD_REG_ADDR 0x10781100 432 #define IHOST_GICD_REG_REMAP_LEN 0x100 433 434 #define IHOST_GICD_REG_ADDR_VALID(d, addr) \ 435 (_devices[d].bde_dev.base_address1 && \ 436 (addr & 0xFFFFFF00) == _devices[d].phys_address1) 437 438 #define IHOST_GICD_REG_ADDR_REMAP(d, addr) \ 439 (void *)(_devices[d].bde_dev.base_address1 + (addr - _devices[d].phys_address1)) 440 441 static uint32_t _read(int d, uint32_t addr); 442 443 #ifdef BCM_ICS 444 #else 445 /* Used to determine overall memory limits across all devices */ 446 static uint32_t _pci_mem_start = 0xFFFFFFFF; 447 static uint32_t _pci_mem_end = 0; 448 449 /* Used to control MSI interrupts */ 450 static int use_msi = 0; 451 #endif 452 453 #ifdef BCM_PLX9656_LOCAL_BUS 454 455 #define CPLD_OFFSET 0x00800000 456 #define CPLD_REVISION_REG 0x0000 457 #define CPLD_REVISION_MASK 0xffff 458 #define CPLD_RESET_REG 0x0004 459 #define CPLD_RESET_NONE 0x0000 460 461 #define PL0_OFFSET 0x00800000 462 #define PL0_SIZE 0x00040000 463 #define PL0_REVISION_REG 0x0000 464 465 /* Assume there's only one PLX PCI-to-Local bus bridge if any */ 466 static bde_ctrl_t plx_ctrl; 467 static int num_plx = 0; 468 469 #endif /* BCM_PLX9656_LOCAL_BUS */ 470 471 static spinlock_t bus_lock; 472 473 static int 474 _parse_eb_args(char *str, char * format, ...) 475 __attribute__ ((format (scanf, 2, 3))); 476 477 static int 478 _parse_eb_args(char *str, char * format, ...) 479 { 480 va_list args; 481 482 va_start(args, format); 483 vsscanf(str, format, args); 484 va_end(args); 485 486 return 0; 487 } 488 489 static void 490 _bde_add_device(void) 491 { 492 int add_switch_device = 0; 493 if (_devices[_ndevices].dev_type & BDE_SWITCH_DEV_TYPE) { 494 _switch_ndevices++; 495 add_switch_device = 1; 496 } else if (_devices[_ndevices].dev_type & BDE_ETHER_DEV_TYPE) { 497 _ether_ndevices++; 498 } else if (_devices[_ndevices].dev_type & BDE_CPU_DEV_TYPE) { 499 _cpu_ndevices++; 500 } else { 501 return; 502 } 503 _ndevices++; 504 505 /* 506 * In order to be backward compatible with the user mode BDE 507 * (specifically the interrupt IOCTLs) and the CM, switch devices 508 * *must* come first. If this is not the case (due to the probing 509 * order), we let the non-switch device(s) drop down to the end of 510 * the device array. 511 */ 512 if (add_switch_device) { 513 bde_ctrl_t tmp_dev; 514 int i, s = 0; 515 516 while (s < _switch_ndevices) { 517 if (_devices[s].dev_type & BDE_SWITCH_DEV_TYPE) { 518 s++; 519 continue; 520 } 521 tmp_dev = _devices[s]; 522 for (i = s; i < _ndevices - 1; i++) { 523 _devices[i] = _devices[i+1]; 524 } 525 _devices[i] = tmp_dev; 526 } 527 528 _dma_init(_switch_ndevices-1); 529 } 530 531 /* Initialize device locks */ 532 spin_lock_init(&_devices[_ndevices-1].lock); 533 } 534 535 static int 536 _eb_device_create(resource_size_t paddr, int irq, int rd_hw, int wr_hw) 537 { 538 bde_ctrl_t *ctrl; 539 uint32 dev_rev_id = 0x0, dev_id; 540 541 dev_id = _ndevices; 542 543 ctrl = _devices + _ndevices; 544 545 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 546 ctrl->pci_device = NULL; /* No PCI bus */ 547 548 if(rd_hw) { 549 ctrl->dev_type |= BDE_DEV_BUS_RD_16BIT; 550 } 551 552 if (wr_hw) { 553 ctrl->dev_type |= BDE_DEV_BUS_WR_16BIT; 554 } 555 556 /* Map in the device */ 557 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, 0x10000); 558 ctrl->phys_address = paddr; 559 560 dev_rev_id = _read(dev_id, 0x178); /* CMIC_DEV_REV_ID */ 561 562 ctrl->bde_dev.device = dev_rev_id & 0xFFFF; 563 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xFF; 564 565 ctrl->iLine = irq; 566 ctrl->isr = NULL; 567 ctrl->isr_data = NULL; 568 569 gprintk("Created EB device at BA=%x IRQ=%d RD16=%d WR16=%d device=0x%x\n", 570 (unsigned int)paddr, irq, rd_hw, wr_hw, ctrl->bde_dev.device); 571 572 _bde_add_device(); 573 574 return 0; 575 } 576 577 #ifdef BCM_SAND_SUPPORT 578 579 #include <soc/devids.h> 580 581 static int 582 sand_device_create(void) 583 { 584 bde_ctrl_t* ctrl; 585 586 ctrl = _devices; /* FIX_ME: on petra, take first device */ 587 588 #ifndef __DUNE_LINUX_BCM_CPU_PCIE__ 589 ctrl->dev_type |= BDE_PCI_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 590 ctrl->pci_device = NULL; /* No PCI bus */ 591 592 /* Map in the device */ /* FIX_ME: not realy map anything */ 593 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(0x40000000, 0x100000); 594 ctrl->phys_address = 0x40000000; 595 596 ctrl->iLine = 0; 597 ctrl->isr = NULL; 598 ctrl->isr_data = NULL; 599 600 ctrl->bde_dev.device = BCM88950_DEVICE_ID; 601 ctrl->bde_dev.rev = BCM88950_A0_REV_ID; 602 #endif 603 604 /* Map CPU regs */ 605 #ifdef __DUNE_WRX_BCM_CPU__ 606 cpu_address = IOREMAP(0x18000000, 0x4000000); 607 #elif defined(__DUNE_GTO_BCM_CPU__) 608 cpu_address = IOREMAP(0xe0000000, 0x100000); 609 #endif 610 611 if ((ctrl->bde_dev.device == PCP_PCI_DEVICE_ID)) { 612 ctrl->bde_dev.device = GEDI_DEVICE_ID; 613 ctrl->bde_dev.rev = GEDI_REV_ID; 614 } 615 616 if ((ctrl->bde_dev.device == ACP_PCI_DEVICE_ID)) { 617 ctrl->dev_type |= BDE_PCI_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 618 } 619 620 #ifndef __DUNE_LINUX_BCM_CPU_PCIE__ 621 _bde_add_device(); 622 #endif 623 624 return 0; 625 } 626 #endif /* BCM_SAND_SUPPORT */ 627 628 #ifdef IPROC_CMICD 629 static void 630 iproc_cmicd_get_irqres(ibde_dev_t bde_dev, struct resource *res_irq) 631 { 632 shbde_iproc_config_t iproc_config, *icfg = &iproc_config; 633 634 /* iProc configuration parameters */ 635 memset(icfg, 0, sizeof(*icfg)); 636 shbde_iproc_config_init(icfg, bde_dev.device, bde_dev.rev); 637 638 if ((icfg->iproc_ver == 0) && (debug >= 1)) { 639 gprintk("Unable to determine iProc version\n"); 640 } 641 642 if (icfg->iproc_ver == 7) { 643 res_irq->start = 221; 644 } else if (icfg->iproc_ver == 10) { 645 res_irq->start = 184; 646 } 647 648 } 649 650 #include <linux/platform_device.h> 651 #include <linux/of.h> 652 653 extern int iproc_platform_driver_register(struct platform_driver *drv); 654 extern void iproc_platform_driver_unregister(struct platform_driver *drv); 655 extern int iproc_platform_device_register(struct platform_device *drv); 656 extern void iproc_platform_device_unregister(struct platform_device *drv); 657 658 extern struct resource * 659 iproc_platform_get_resource(struct platform_device *dev, unsigned int type, 660 unsigned int num); 661 662 #define IPROC_CHIPCOMMONA_BASE 0x18000000 663 #define IPROC_CMICD_BASE 0x48000000 664 #define IPROC_CMICD_SIZE 0x40000 665 #define IPROC_CMICD_INT 194 666 667 #define IPROC_CMICD_COMPATIBLE "brcm,iproc-cmicd" 668 #define IPROC_CMICX_COMPATIBLE "brcm,iproc-cmicx" 669 670 static int 671 iproc_cmicd_probe(struct platform_device *pldev) 672 { 673 bde_ctrl_t *ctrl; 674 uint32 size, dev_rev_id; 675 struct resource *memres, *irqres; 676 #ifdef CONFIG_OF 677 if (debug >= 1) { 678 gprintk("iproc_cmicd_probe %s\n", pldev->dev.of_node ? "with device node":""); 679 } 680 #endif 681 memres = iproc_platform_get_resource(pldev, IORESOURCE_MEM, 0); 682 if (memres == NULL) { 683 gprintk("Unable to retrieve iProc CMIC resources"); 684 return -1; 685 } 686 size = memres->end - memres->start + 1; 687 688 ctrl = _devices + _ndevices; 689 690 ctrl->dev_type = BDE_AXI_DEV_TYPE | BDE_SWITCH_DEV_TYPE | BDE_256K_REG_SPACE; 691 ctrl->pci_device = NULL; /* No PCI bus */ 692 693 /* Map CMIC block in the AXI memory space into CPU address space */ 694 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(memres->start, size); 695 if (!ctrl->bde_dev.base_address) { 696 gprintk("Error mapping iProc CMIC registers"); 697 return -1; 698 } 699 ctrl->phys_address = memres->start; 700 701 #ifdef CONFIG_OF 702 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 703 uint32 *icfg_chip_id; 704 icfg_chip_id = (uint32 *)IOREMAP(ICFG_CHIP_ID_REG, 2 * sizeof(uint32)); 705 if (icfg_chip_id == NULL) { 706 gprintk("Error mapping ICFG_CHIP_ID_REG\n"); 707 return -1; 708 } 709 ctrl->bde_dev.device = readl(icfg_chip_id) & 0xffff; 710 ctrl->bde_dev.rev = readl(icfg_chip_id+1) & 0xff; 711 iounmap(icfg_chip_id); 712 /* Map GICD block in the AXI memory space into CPU address space */ 713 memres = iproc_platform_get_resource(pldev, IORESOURCE_MEM, 1); 714 if (memres) { 715 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(memres->start, memres->end - memres->start + 1); 716 ctrl->phys_address1 = memres->start; 717 } else { 718 /* Use default address if not available in DTB */ 719 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(IHOST_GICD_REG_ADDR, IHOST_GICD_REG_REMAP_LEN); 720 ctrl->phys_address1 = IHOST_GICD_REG_ADDR; 721 } 722 if (ctrl->bde_dev.base_address1) { 723 if (debug >= 1) { 724 gprintk("base_address1:0x%lx phys_address1:0x%lx\n", 725 (unsigned long)ctrl->bde_dev.base_address1, (unsigned long)ctrl->phys_address1); 726 } 727 } else { 728 gprintk("Error mapping ihost GICD registers\n"); 729 } 730 } else 731 #endif 732 { 733 /* Read switch device ID from CMIC */ 734 dev_rev_id = *((uint32 *)(ctrl->bde_dev.base_address + 0x10224)); 735 #if defined(BCM_CMICM_SUPPORT) && defined(BE_HOST) 736 ctrl->bde_dev.device = ( (((dev_rev_id >> 16) & 0xff) << 8) | 737 ((dev_rev_id >> 24) & 0xff)); 738 ctrl->bde_dev.rev = (dev_rev_id >> 8) & 0xff ; 739 #else 740 ctrl->bde_dev.device = dev_rev_id & 0xffff; 741 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xff; 742 #endif 743 ctrl->bde_dev.base_address1 = 0; 744 } 745 746 #ifdef CONFIG_OF 747 if (!pldev->dev.of_node) 748 #endif 749 { 750 /* Assign locally if not available from device node */ 751 iproc_cmicd_get_irqres(ctrl->bde_dev, &pldev->resource[0]); 752 } 753 754 #ifdef CONFIG_OF 755 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 756 int i; 757 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 758 irqres = iproc_platform_get_resource(pldev, IORESOURCE_IRQ, i); 759 iproc_cmicx_irqs[i] = irqres->start; 760 if (debug >= 1) { 761 gprintk("iproc_cmicx_irqs[%d] = %d\n", i, iproc_cmicx_irqs[i]); 762 } 763 } 764 ctrl->iLine = iproc_cmicx_irqs[0]; 765 } else 766 #endif 767 { 768 irqres = iproc_platform_get_resource(pldev, IORESOURCE_IRQ, 0); 769 ctrl->iLine = irqres->start; 770 } 771 772 ctrl->isr = NULL; 773 ctrl ->isr_data = NULL; 774 775 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 776 ctrl->dma_dev = &pldev->dev; 777 #endif 778 779 /* Let's boogie */ 780 _bde_add_device(); 781 return 0; 782 } 783 784 static int 785 iproc_cmicd_remove(struct platform_device *pldev) 786 { 787 return 0; 788 } 789 #ifdef CONFIG_OF 790 static const struct of_device_id iproc_cmicd_of_match[] = { 791 { .compatible = IPROC_CMICD_COMPATIBLE }, 792 { .compatible = IPROC_CMICX_COMPATIBLE }, 793 {}, 794 }; 795 MODULE_DEVICE_TABLE(of, iproc_cmicd_of_match); 796 #endif 797 static char iproc_cmicd_string[] = "bcmiproc-cmicd"; 798 799 static struct platform_driver iproc_cmicd_driver = 800 { 801 .probe = iproc_cmicd_probe, 802 .remove = iproc_cmicd_remove, 803 .driver = 804 { 805 .name = iproc_cmicd_string, 806 .owner = THIS_MODULE, 807 #ifdef CONFIG_OF 808 .of_match_table = iproc_cmicd_of_match, 809 #endif 810 }, 811 }; 812 813 typedef enum { 814 IPROC_CMICD_RES_INTR = 0, 815 IPROC_CMICD_RES_MEM 816 } IPROC_CMICD_RES_E; 817 818 static struct resource iproc_cmicd_resources[] = { 819 [IPROC_CMICD_RES_INTR] = { 820 .flags = IORESOURCE_IRQ, 821 .start = IPROC_CMICD_INT, 822 }, 823 [IPROC_CMICD_RES_MEM] = { 824 .flags = IORESOURCE_MEM, 825 .start = IPROC_CMICD_BASE, 826 .end = IPROC_CMICD_BASE+IPROC_CMICD_SIZE-1, 827 }, 828 }; 829 830 static void 831 iproc_cmicd_release(struct device *dev) 832 { 833 } 834 835 static u64 iproc_cmicd_dmamask = DMA_BIT_MASK(32); 836 837 static struct platform_device iproc_cmicd_pdev = { 838 .name = iproc_cmicd_string, 839 .id = 0, 840 .dev = { 841 .release = iproc_cmicd_release, 842 .init_name = iproc_cmicd_string, 843 .dma_mask = &iproc_cmicd_dmamask, 844 .coherent_dma_mask = DMA_BIT_MASK(32), 845 }, 846 .resource = iproc_cmicd_resources, 847 .num_resources = ARRAY_SIZE(iproc_cmicd_resources), 848 }; 849 850 static int 851 iproc_has_cmicd(void) 852 { 853 void *iproc_cca_base; 854 uint32 cca_cid; 855 856 /* Read ChipcommonA chip id register to identify current SOC */ 857 iproc_cca_base = IOREMAP(IPROC_CHIPCOMMONA_BASE, 0x3000); 858 if (iproc_cca_base == NULL) { 859 gprintk("iproc_has_cmicd: ioremap of ChipcommonA registers failed"); 860 return 0; 861 } 862 cca_cid = readl((uint32 *)iproc_cca_base); 863 cca_cid &= 0xffff; 864 iounmap(iproc_cca_base); 865 866 /* Only allowed accessing CMICD module if the SOC has it */ 867 switch (cca_cid) { 868 default: 869 break; 870 } 871 872 /* Device has CMIC */ 873 return 1; 874 } 875 876 #define IPROC_CHIPCOMMONA_EROM_PTR_OFFSET (0x180000fc) 877 #define EROM_MAX_SIZE (0x1000) 878 #define EROM_PARTNUM_CMICD (0x14) 879 880 #define EROM_DESC_COMPIDENT (0x1) 881 #define EROM_DESC_MASTER (0x3) 882 #define EROM_DESC_ADDR (0x5) 883 #define EROM_DESC_END (0xF) 884 #define EROM_DESC_EMPTY (0) 885 886 #define EROM_IS_DESC_COMPIDENT(x) ((x & 0x7) == EROM_DESC_COMPIDENT) 887 #define EROM_IS_DESC_MASTER(x) ((x & 0x7) == EROM_DESC_MASTER) 888 #define EROM_IS_DESC_ADDR(x) ((x & 0x7) == EROM_DESC_ADDR) 889 #define EROM_IS_DESC_END(x) ((x & 0xF) == EROM_DESC_END) 890 891 #define EROM_GET_PARTNUM(x) ((x >> 8) & (0xFFF)) /* Bit 8~19 */ 892 #define EROM_GET_ADDRESS(x) ((x >> 12) & (0xFFFFF)) /* Bit 12~31 */ 893 #define EROM_GET_SIZETYPE(x) ((x >> 4) & (0x3)) /* Bit 4~5 */ 894 #define EROM_GET_AG32(x) ((x >> 3) & (0x1)) /* Bit 3 */ 895 #define EROM_GET_SIZE(x) ((x >> 12) & (0xFFFFF)) /* Bit 12~31 */ 896 #define EROM_GET_SG32(x) ((x >> 3) & (0x1)) /* Bit 3 */ 897 898 #define EROM_ADDR_SIZETYPE_4K (0) 899 #define EROM_ADDR_SIZETYPE_8K (1) 900 #define EROM_ADDR_SIZETYPE_16K (2) 901 #define EROM_ADDR_SIZETYPE_MORE (3) 902 903 #define EROM_ADDR_FLAG_AG32 (1) /* Address space greater than 32 bit */ 904 #define EROM_ADDR_FLAG_SIZE (2) /* Addition size descriptor */ 905 #define EROM_ADDR_FLAG_SG32 (4) /* Size descriptor greater than 32 bit */ 906 907 static void 908 iproc_cmicd_get_memregion(struct resource *res_mem) 909 { 910 void *erom_ptr_oft; 911 uint32_t erom_phy_addr; 912 uint32_t *erom_base; 913 uint32_t i = 0; 914 uint32_t word = 0; 915 uint8_t more_addr_word = 0; /* bit 0: AG32; bit 1: SIZE; bit 2: SG32 */ 916 uint8_t found_cmicd_dev = 0; 917 uint8_t size_type = 0; 918 bool is_compident_a = 1; /* 1: CompidentA; o/w: CompidentB */ 919 920 erom_ptr_oft = IOREMAP(IPROC_CHIPCOMMONA_EROM_PTR_OFFSET, 0x100); 921 922 erom_phy_addr = readl((uint32 *)(erom_ptr_oft)); 923 iounmap(erom_ptr_oft); 924 925 erom_base = IOREMAP(erom_phy_addr, EROM_MAX_SIZE); 926 927 while (1) { 928 word = readl((uint32 *)(erom_base + i)); 929 930 if (EROM_IS_DESC_ADDR(word) || more_addr_word) { 931 if (more_addr_word == 0) { /* Normal Addr Desc */ 932 if (EROM_GET_AG32(word) == 1) { 933 more_addr_word |= EROM_ADDR_FLAG_AG32; 934 } 935 936 size_type = EROM_GET_SIZETYPE(word); 937 if (size_type == EROM_ADDR_SIZETYPE_MORE) { 938 more_addr_word |= EROM_ADDR_FLAG_SIZE; 939 } 940 941 if (found_cmicd_dev == 1) { 942 res_mem->start = EROM_GET_ADDRESS(word) << 12; 943 if (size_type < EROM_ADDR_SIZETYPE_MORE) { 944 res_mem->end = res_mem->start + 4096 * (1 << size_type) - 1; 945 } 946 } 947 } 948 else if (more_addr_word & EROM_ADDR_FLAG_AG32) { /* UpperAddr Desc */ 949 more_addr_word &= ~EROM_ADDR_FLAG_AG32; 950 951 if (found_cmicd_dev == 1) { 952 /* res_mem->start |= word << 32; */ 953 gprintk("Expect cmicd address to be 32-bit\n"); 954 } 955 } 956 else if (more_addr_word & EROM_ADDR_FLAG_SIZE) { /* Size Desc */ 957 if (EROM_GET_SG32(word) == 1) { 958 more_addr_word |= EROM_ADDR_FLAG_SG32; 959 } 960 961 more_addr_word &= ~EROM_ADDR_FLAG_SIZE; 962 963 if (found_cmicd_dev == 1) { 964 res_mem->end = res_mem->start + (EROM_GET_SIZE(word) << 12) - 1; 965 } 966 } 967 else if (more_addr_word & EROM_ADDR_FLAG_SG32) { /* UpperSize Desc */ 968 more_addr_word &= ~EROM_ADDR_FLAG_SG32; 969 970 if (found_cmicd_dev == 1) { 971 /* res_mem->end += (word) << 32; */ 972 gprintk("Expect cmicd size to be 32-bit\n"); 973 } 974 } 975 976 if (found_cmicd_dev == 1 && more_addr_word == 0) { 977 break; /* We have gotten all necessary information, exit the loop */ 978 } 979 } 980 else if (EROM_IS_DESC_COMPIDENT(word)) { 981 if (is_compident_a == 1) { 982 if (EROM_GET_PARTNUM(word) == EROM_PARTNUM_CMICD) { 983 found_cmicd_dev = 1; 984 } 985 } 986 987 is_compident_a = 1 - is_compident_a; 988 } 989 else if (EROM_IS_DESC_END(word)) { 990 break; 991 } 992 993 i++; 994 } 995 iounmap(erom_base); 996 997 if (debug >= 1) { 998 gprintk("CMICD info by %s: cmicd_mem.start=%lx, cmicd_mem.end=%lx\n", 999 found_cmicd_dev ? "EROM" : "Default", 1000 (unsigned long)iproc_cmicd_resources[IPROC_CMICD_RES_MEM].start, 1001 (unsigned long)iproc_cmicd_resources[IPROC_CMICD_RES_MEM].end); 1002 } 1003 } 1004 #endif /* IPROC_CMICD */ 1005 1006 #ifdef BCM_ICS 1007 static int 1008 _ics_bde_create(void) 1009 { 1010 bde_ctrl_t *ctrl; 1011 uint32 dev_rev_id = 0x0; 1012 resource_size_t paddr; 1013 1014 if (_ndevices == 0) { 1015 ctrl = _devices + _ndevices; 1016 1017 ctrl->dev_type |= BDE_ICS_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 1018 ctrl->pci_device = NULL; /* No PCI bus */ 1019 1020 /* Map in the device */ 1021 paddr = BCM_ICS_CMIC_BASE; 1022 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, 0x10000); 1023 ctrl->phys_address = paddr; 1024 1025 dev_rev_id = *((unsigned int *)(KSEG1ADDR(paddr + 0x178))); 1026 1027 ctrl->bde_dev.device = dev_rev_id & 0xFFFF; 1028 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xFF; 1029 1030 ctrl->iLine = 5; /* From raptor linux BSP */ 1031 1032 ctrl->isr = NULL; 1033 ctrl->isr_data = NULL; 1034 printk("Created ICS device ..%x\n", ctrl->bde_dev.base_address); 1035 _bde_add_device(); 1036 } 1037 1038 return 0; 1039 } 1040 1041 #else /* !BCM_ICS */ 1042 1043 extern struct pci_bus *pci_find_bus(int domain, int busnr); 1044 1045 /* 1046 * PCI device table. 1047 * Populated from the include/soc/devids.h file. 1048 */ 1049 1050 static const struct pci_device_id _id_table[] = { 1051 { BROADCOM_VENDOR_ID, BCM5675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1052 { BROADCOM_VENDOR_ID, BCM5676_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1053 { BROADCOM_VENDOR_ID, BCM56218X_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1054 { BROADCOM_VENDOR_ID, BCM56218_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1055 { BROADCOM_VENDOR_ID, BCM56219_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1056 { BROADCOM_VENDOR_ID, BCM56218R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1057 { BROADCOM_VENDOR_ID, BCM56219R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1058 { BROADCOM_VENDOR_ID, BCM56214_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1059 { BROADCOM_VENDOR_ID, BCM56215_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1060 { BROADCOM_VENDOR_ID, BCM56214R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1061 { BROADCOM_VENDOR_ID, BCM56215R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1062 { BROADCOM_VENDOR_ID, BCM56216_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1063 { BROADCOM_VENDOR_ID, BCM56217_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1064 { BROADCOM_VENDOR_ID, BCM56212_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1065 { BROADCOM_VENDOR_ID, BCM56213_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1066 { BROADCOM_VENDOR_ID, BCM56230_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1067 { BROADCOM_VENDOR_ID, BCM56231_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1068 { BROADCOM_VENDOR_ID, BCM53718_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1069 { BROADCOM_VENDOR_ID, BCM53714_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1070 { BROADCOM_VENDOR_ID, BCM53716_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1071 { BROADCOM_VENDOR_ID, BCM56018_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1072 { BROADCOM_VENDOR_ID, BCM56014_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1073 { BROADCOM_VENDOR_ID, BCM56224_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1074 { BROADCOM_VENDOR_ID, BCM56225_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1075 { BROADCOM_VENDOR_ID, BCM56226_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1076 { BROADCOM_VENDOR_ID, BCM56227_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1077 { BROADCOM_VENDOR_ID, BCM56228_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1078 { BROADCOM_VENDOR_ID, BCM56229_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1079 { BROADCOM_VENDOR_ID, BCM56024_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1080 { BROADCOM_VENDOR_ID, BCM56025_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1081 { BROADCOM_VENDOR_ID, BCM53724_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1082 { BROADCOM_VENDOR_ID, BCM53726_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1083 { BROADCOM_VENDOR_ID, BCM56100_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1084 { BROADCOM_VENDOR_ID, BCM56101_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1085 { BROADCOM_VENDOR_ID, BCM56102_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1086 { BROADCOM_VENDOR_ID, BCM56105_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1087 { BROADCOM_VENDOR_ID, BCM56106_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1088 { BROADCOM_VENDOR_ID, BCM56107_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1089 { BROADCOM_VENDOR_ID, BCM56110_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1090 { BROADCOM_VENDOR_ID, BCM56111_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1091 { BROADCOM_VENDOR_ID, BCM56112_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1092 { BROADCOM_VENDOR_ID, BCM56115_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1093 { BROADCOM_VENDOR_ID, BCM56116_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1094 { BROADCOM_VENDOR_ID, BCM56117_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1095 { BROADCOM_VENDOR_ID, BCM56300_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1096 { BROADCOM_VENDOR_ID, BCM56301_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1097 { BROADCOM_VENDOR_ID, BCM56302_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1098 { BROADCOM_VENDOR_ID, BCM56303_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1099 { BROADCOM_VENDOR_ID, BCM56304_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1100 { BROADCOM_VENDOR_ID, BCM56404_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1101 { BROADCOM_VENDOR_ID, BCM56305_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1102 { BROADCOM_VENDOR_ID, BCM56306_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1103 { BROADCOM_VENDOR_ID, BCM56307_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1104 { BROADCOM_VENDOR_ID, BCM56308_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1105 { BROADCOM_VENDOR_ID, BCM56309_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1106 { BROADCOM_VENDOR_ID, BCM56310_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1107 { BROADCOM_VENDOR_ID, BCM56311_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1108 { BROADCOM_VENDOR_ID, BCM56312_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1109 { BROADCOM_VENDOR_ID, BCM56313_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1110 { BROADCOM_VENDOR_ID, BCM56314_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1111 { BROADCOM_VENDOR_ID, BCM56315_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1112 { BROADCOM_VENDOR_ID, BCM56316_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1113 { BROADCOM_VENDOR_ID, BCM56317_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1114 { BROADCOM_VENDOR_ID, BCM56318_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1115 { BROADCOM_VENDOR_ID, BCM56319_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1116 #ifndef EXCLUDE_BCM56324 1117 { BROADCOM_VENDOR_ID, BCM56322_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1118 { BROADCOM_VENDOR_ID, BCM56324_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1119 #endif /* EXCLUDE_BCM56324 */ 1120 { BROADCOM_VENDOR_ID, BCM53312_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1121 { BROADCOM_VENDOR_ID, BCM53313_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1122 { BROADCOM_VENDOR_ID, BCM53314_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1123 { BROADCOM_VENDOR_ID, BCM53324_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1124 { BROADCOM_VENDOR_ID, BCM53333_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1125 { BROADCOM_VENDOR_ID, BCM53334_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1126 { BROADCOM_VENDOR_ID, BCM53342_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1127 { BROADCOM_VENDOR_ID, BCM53343_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1128 { BROADCOM_VENDOR_ID, BCM53344_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1129 { BROADCOM_VENDOR_ID, BCM53346_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1130 { BROADCOM_VENDOR_ID, BCM53347_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1131 { BROADCOM_VENDOR_ID, BCM53393_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1132 { BROADCOM_VENDOR_ID, BCM53394_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1133 { BROADCOM_VENDOR_ID, BCM53300_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1134 { BROADCOM_VENDOR_ID, BCM53301_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1135 { BROADCOM_VENDOR_ID, BCM53302_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1136 { BROADCOM_VENDOR_ID, BCM56500_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1137 { BROADCOM_VENDOR_ID, BCM56501_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1138 { BROADCOM_VENDOR_ID, BCM56502_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1139 { BROADCOM_VENDOR_ID, BCM56503_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1140 { BROADCOM_VENDOR_ID, BCM56504_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1141 { BROADCOM_VENDOR_ID, BCM56505_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1142 { BROADCOM_VENDOR_ID, BCM56506_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1143 { BROADCOM_VENDOR_ID, BCM56507_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1144 { BROADCOM_VENDOR_ID, BCM56508_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1145 { BROADCOM_VENDOR_ID, BCM56509_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1146 { BROADCOM_VENDOR_ID, BCM56510_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1147 { BROADCOM_VENDOR_ID, BCM56511_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1148 { BROADCOM_VENDOR_ID, BCM56512_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1149 { BROADCOM_VENDOR_ID, BCM56513_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1150 { BROADCOM_VENDOR_ID, BCM56514_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1151 { BROADCOM_VENDOR_ID, BCM56516_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1152 { BROADCOM_VENDOR_ID, BCM56517_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1153 { BROADCOM_VENDOR_ID, BCM56518_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1154 { BROADCOM_VENDOR_ID, BCM56519_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1155 { BROADCOM_VENDOR_ID, BCM56580_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1156 { BROADCOM_VENDOR_ID, BCM56620_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1157 { BROADCOM_VENDOR_ID, BCM56624_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1158 { BROADCOM_VENDOR_ID, BCM56626_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1159 { BROADCOM_VENDOR_ID, BCM56628_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1160 { BROADCOM_VENDOR_ID, BCM56629_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1161 { BROADCOM_VENDOR_ID, BCM56680_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1162 { BROADCOM_VENDOR_ID, BCM56684_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1163 { BROADCOM_VENDOR_ID, BCM56700_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1164 { BROADCOM_VENDOR_ID, BCM56701_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1165 { BROADCOM_VENDOR_ID, BCM56720_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1166 { BROADCOM_VENDOR_ID, BCM56721_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1167 { BROADCOM_VENDOR_ID, BCM56725_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1168 { BROADCOM_VENDOR_ID, BCM56800_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1169 { BROADCOM_VENDOR_ID, BCM56801_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1170 { BROADCOM_VENDOR_ID, BCM56802_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1171 { BROADCOM_VENDOR_ID, BCM56803_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1172 { BROADCOM_VENDOR_ID, BCM56820_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1173 { BROADCOM_VENDOR_ID, BCM56821_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1174 { BROADCOM_VENDOR_ID, BCM56822_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1175 { BROADCOM_VENDOR_ID, BCM56823_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1176 { BROADCOM_VENDOR_ID, BCM56825_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1177 { BROADCOM_VENDOR_ID, BCM56630_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1178 { BROADCOM_VENDOR_ID, BCM56634_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1179 { BROADCOM_VENDOR_ID, BCM56636_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1180 { BROADCOM_VENDOR_ID, BCM56638_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1181 { BROADCOM_VENDOR_ID, BCM56639_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1182 { BROADCOM_VENDOR_ID, BCM56538_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1183 { BROADCOM_VENDOR_ID, BCM56520_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1184 { BROADCOM_VENDOR_ID, BCM56521_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1185 { BROADCOM_VENDOR_ID, BCM56522_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1186 { BROADCOM_VENDOR_ID, BCM56524_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1187 { BROADCOM_VENDOR_ID, BCM56526_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1188 { BROADCOM_VENDOR_ID, BCM56534_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1189 { BROADCOM_VENDOR_ID, BCM56685_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1190 { BROADCOM_VENDOR_ID, BCM56689_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1191 { BROADCOM_VENDOR_ID, BCM56331_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1192 { BROADCOM_VENDOR_ID, BCM56333_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1193 { BROADCOM_VENDOR_ID, BCM56334_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1194 { BROADCOM_VENDOR_ID, BCM56338_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1195 { BROADCOM_VENDOR_ID, BCM56320_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1196 { BROADCOM_VENDOR_ID, BCM56321_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1197 { BROADCOM_VENDOR_ID, BCM56132_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1198 { BROADCOM_VENDOR_ID, BCM56134_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1199 { BROADCOM_VENDOR_ID, BCM88732_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1200 { BROADCOM_VENDOR_ID, BCM56140_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1201 { BROADCOM_VENDOR_ID, BCM56142_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1202 { BROADCOM_VENDOR_ID, BCM56143_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1203 { BROADCOM_VENDOR_ID, BCM56144_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1204 { BROADCOM_VENDOR_ID, BCM56146_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1205 { BROADCOM_VENDOR_ID, BCM56147_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1206 { BROADCOM_VENDOR_ID, BCM56149_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1207 { BROADCOM_VENDOR_ID, BCM56150_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1208 { BROADCOM_VENDOR_ID, BCM56151_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1209 { BROADCOM_VENDOR_ID, BCM56152_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1210 { BROADCOM_VENDOR_ID, BCM56930_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1211 { BROADCOM_VENDOR_ID, BCM56931_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1212 { BROADCOM_VENDOR_ID, BCM56935_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1213 { BROADCOM_VENDOR_ID, BCM56936_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1214 { BROADCOM_VENDOR_ID, BCM56939_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1215 { BROADCOM_VENDOR_ID, BCM56840_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1216 { BROADCOM_VENDOR_ID, BCM56841_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1217 { BROADCOM_VENDOR_ID, BCM56842_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1218 { BROADCOM_VENDOR_ID, BCM56843_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1219 { BROADCOM_VENDOR_ID, BCM56844_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1220 { BROADCOM_VENDOR_ID, BCM56845_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1221 { BROADCOM_VENDOR_ID, BCM56846_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1222 { BROADCOM_VENDOR_ID, BCM56847_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1223 { BROADCOM_VENDOR_ID, BCM56549_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1224 { BROADCOM_VENDOR_ID, BCM56053_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1225 { BROADCOM_VENDOR_ID, BCM56838_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1226 { BROADCOM_VENDOR_ID, BCM56831_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1227 { BROADCOM_VENDOR_ID, BCM56835_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1228 { BROADCOM_VENDOR_ID, BCM56849_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1229 { BROADCOM_VENDOR_ID, BCM56742_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1230 { BROADCOM_VENDOR_ID, BCM56743_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1231 { BROADCOM_VENDOR_ID, BCM56744_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1232 { BROADCOM_VENDOR_ID, BCM56745_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1233 { BROADCOM_VENDOR_ID, BCM56746_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1234 { BROADCOM_VENDOR_ID, BCM56640_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1235 { BROADCOM_VENDOR_ID, BCM56548_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1236 { BROADCOM_VENDOR_ID, BCM56547_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1237 { BROADCOM_VENDOR_ID, BCM56346_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1238 { BROADCOM_VENDOR_ID, BCM56345_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1239 { BROADCOM_VENDOR_ID, BCM56344_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1240 { BROADCOM_VENDOR_ID, BCM56342_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1241 { BROADCOM_VENDOR_ID, BCM56340_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1242 { BROADCOM_VENDOR_ID, BCM56049_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1243 { BROADCOM_VENDOR_ID, BCM56048_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1244 { BROADCOM_VENDOR_ID, BCM56047_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1245 { BROADCOM_VENDOR_ID, BCM56042_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1246 { BROADCOM_VENDOR_ID, BCM56041_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1247 { BROADCOM_VENDOR_ID, BCM56040_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1248 { BROADCOM_VENDOR_ID, BCM56643_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1249 { BROADCOM_VENDOR_ID, BCM56644_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1250 { BROADCOM_VENDOR_ID, BCM56648_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1251 { BROADCOM_VENDOR_ID, BCM56649_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1252 { BROADCOM_VENDOR_ID, BCM56540_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1253 { BROADCOM_VENDOR_ID, BCM56541_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1254 { BROADCOM_VENDOR_ID, BCM56542_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1255 { BROADCOM_VENDOR_ID, BCM56543_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1256 { BROADCOM_VENDOR_ID, BCM56544_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1257 { BROADCOM_VENDOR_ID, BCM56545_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1258 { BROADCOM_VENDOR_ID, BCM56546_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1259 { BROADCOM_VENDOR_ID, BCM56044_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1260 { BROADCOM_VENDOR_ID, BCM56045_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1261 { BROADCOM_VENDOR_ID, BCM56046_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1262 { BROADCOM_VENDOR_ID, BCM55440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1263 { BROADCOM_VENDOR_ID, BCM56440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1264 { BROADCOM_VENDOR_ID, BCM56441_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1265 { BROADCOM_VENDOR_ID, BCM56442_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1266 { BROADCOM_VENDOR_ID, BCM56443_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1267 { BROADCOM_VENDOR_ID, BCM56445_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1268 { BROADCOM_VENDOR_ID, BCM56446_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1269 { BROADCOM_VENDOR_ID, BCM56447_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1270 { BROADCOM_VENDOR_ID, BCM56448_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1271 { BROADCOM_VENDOR_ID, BCM56449_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1272 { BROADCOM_VENDOR_ID, BCM56240_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1273 { BROADCOM_VENDOR_ID, BCM56241_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1274 { BROADCOM_VENDOR_ID, BCM56242_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1275 { BROADCOM_VENDOR_ID, BCM56243_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1276 { BROADCOM_VENDOR_ID, BCM56245_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1277 { BROADCOM_VENDOR_ID, BCM56246_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1278 { BROADCOM_VENDOR_ID, BCM55450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1279 { BROADCOM_VENDOR_ID, BCM55455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1280 { BROADCOM_VENDOR_ID, BCM56260_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1281 { BROADCOM_VENDOR_ID, BCM56270_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1282 { BROADCOM_VENDOR_ID, BCM56271_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1283 { BROADCOM_VENDOR_ID, BCM56272_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1284 { BROADCOM_VENDOR_ID, BCM53460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1285 { BROADCOM_VENDOR_ID, BCM53461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1286 { BROADCOM_VENDOR_ID, BCM56261_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1287 { BROADCOM_VENDOR_ID, BCM56262_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1288 { BROADCOM_VENDOR_ID, BCM56263_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1289 { BROADCOM_VENDOR_ID, BCM56265_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1290 { BROADCOM_VENDOR_ID, BCM56266_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1291 { BROADCOM_VENDOR_ID, BCM56267_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1292 { BROADCOM_VENDOR_ID, BCM56268_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1293 { BROADCOM_VENDOR_ID, BCM56233_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1294 { BROADCOM_VENDOR_ID, BCM56460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1295 { BROADCOM_VENDOR_ID, BCM56461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1296 { BROADCOM_VENDOR_ID, BCM56462_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1297 { BROADCOM_VENDOR_ID, BCM56463_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1298 { BROADCOM_VENDOR_ID, BCM56465_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1299 { BROADCOM_VENDOR_ID, BCM56466_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1300 { BROADCOM_VENDOR_ID, BCM56467_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1301 { BROADCOM_VENDOR_ID, BCM56468_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1302 { BROADCOM_VENDOR_ID, BCM56246_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1303 { BROADCOM_VENDOR_ID, BCM56248_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1304 { BROADCOM_VENDOR_ID, BCM56450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1305 { BROADCOM_VENDOR_ID, BCM56452_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1306 { BROADCOM_VENDOR_ID, BCM56454_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1307 { BROADCOM_VENDOR_ID, BCM56455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1308 { BROADCOM_VENDOR_ID, BCM56456_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1309 { BROADCOM_VENDOR_ID, BCM56457_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1310 { BROADCOM_VENDOR_ID, BCM56458_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1311 { BROADCOM_VENDOR_ID, BCM56850_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1312 { BROADCOM_VENDOR_ID, BCM56851_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1313 { BROADCOM_VENDOR_ID, BCM56852_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1314 { BROADCOM_VENDOR_ID, BCM56853_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1315 { BROADCOM_VENDOR_ID, BCM56854_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1316 { BROADCOM_VENDOR_ID, BCM56855_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1317 { BROADCOM_VENDOR_ID, BCM56834_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1318 { BROADCOM_VENDOR_ID, BCM56750_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1319 { BROADCOM_VENDOR_ID, BCM56830_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1320 { BROADCOM_VENDOR_ID, BCM55440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1321 { BROADCOM_VENDOR_ID, BCM55441_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1322 { BROADCOM_VENDOR_ID, BCM56060_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1323 { BROADCOM_VENDOR_ID, BCM56062_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1324 { BROADCOM_VENDOR_ID, BCM56063_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1325 { BROADCOM_VENDOR_ID, BCM56064_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1326 { BROADCOM_VENDOR_ID, BCM56065_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1327 { BROADCOM_VENDOR_ID, BCM56066_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1328 { BROADCOM_VENDOR_ID, BCM53401_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1329 { BROADCOM_VENDOR_ID, BCM53411_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1330 { BROADCOM_VENDOR_ID, BCM53402_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1331 { BROADCOM_VENDOR_ID, BCM53412_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1332 { BROADCOM_VENDOR_ID, BCM53403_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1333 { BROADCOM_VENDOR_ID, BCM53413_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1334 { BROADCOM_VENDOR_ID, BCM53404_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1335 { BROADCOM_VENDOR_ID, BCM53414_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1336 { BROADCOM_VENDOR_ID, BCM53405_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1337 { BROADCOM_VENDOR_ID, BCM53415_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1338 { BROADCOM_VENDOR_ID, BCM53406_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1339 { BROADCOM_VENDOR_ID, BCM53416_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1340 { BROADCOM_VENDOR_ID, BCM53408_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1341 { BROADCOM_VENDOR_ID, BCM53418_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1342 { BROADCOM_VENDOR_ID, BCM53454_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1343 { BROADCOM_VENDOR_ID, BCM53455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1344 { BROADCOM_VENDOR_ID, BCM53456_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1345 { BROADCOM_VENDOR_ID, BCM53457_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1346 { BROADCOM_VENDOR_ID, BCM53422_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1347 { BROADCOM_VENDOR_ID, BCM53424_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1348 { BROADCOM_VENDOR_ID, BCM53426_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1349 { BROADCOM_VENDOR_ID, BCM53365_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1350 { BROADCOM_VENDOR_ID, BCM53369_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1351 { BROADCOM_VENDOR_ID, BCM56960_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1352 { BROADCOM_VENDOR_ID, BCM56961_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1353 { BROADCOM_VENDOR_ID, BCM56962_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1354 { BROADCOM_VENDOR_ID, BCM56963_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1355 { BROADCOM_VENDOR_ID, BCM56930_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1356 { BROADCOM_VENDOR_ID, BCM56968_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1357 { BROADCOM_VENDOR_ID, BCM56970_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1358 { BROADCOM_VENDOR_ID, BCM56971_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1359 { BROADCOM_VENDOR_ID, BCM56972_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1360 { BROADCOM_VENDOR_ID, BCM56974_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1361 { BROADCOM_VENDOR_ID, BCM56975_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1362 { BROADCOM_VENDOR_ID, BCM56168_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1363 { BROADCOM_VENDOR_ID, BCM56169_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1364 { BROADCOM_VENDOR_ID, BCM56560_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1365 { BROADCOM_VENDOR_ID, BCM56561_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1366 { BROADCOM_VENDOR_ID, BCM56562_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1367 { BROADCOM_VENDOR_ID, BCM56565_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1368 { BROADCOM_VENDOR_ID, BCM56566_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1369 { BROADCOM_VENDOR_ID, BCM56567_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1370 { BROADCOM_VENDOR_ID, BCM56670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1371 { BROADCOM_VENDOR_ID, BCM56671_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1372 { BROADCOM_VENDOR_ID, BCM56672_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1373 { BROADCOM_VENDOR_ID, BCM56675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1374 { BROADCOM_VENDOR_ID, BCM56568_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1375 { BROADCOM_VENDOR_ID, BCM56670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1376 { BROADCOM_VENDOR_ID, BCM56760_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1377 { BROADCOM_VENDOR_ID, BCM56761_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1378 { BROADCOM_VENDOR_ID, BCM56762_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1379 { BROADCOM_VENDOR_ID, BCM56764_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1380 { BROADCOM_VENDOR_ID, BCM56765_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1381 { BROADCOM_VENDOR_ID, BCM56766_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1382 { BROADCOM_VENDOR_ID, BCM56768_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1383 { BROADCOM_VENDOR_ID, BCM56069_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1384 { BROADCOM_VENDOR_ID, BCM56068_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1385 { BROADCOM_VENDOR_ID, BCM56160_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1386 { BROADCOM_VENDOR_ID, BCM56162_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1387 { BROADCOM_VENDOR_ID, BCM56163_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1388 { BROADCOM_VENDOR_ID, BCM56164_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1389 { BROADCOM_VENDOR_ID, BCM56166_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1390 { BROADCOM_VENDOR_ID, BCM53440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1391 { BROADCOM_VENDOR_ID, BCM53443_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1392 { BROADCOM_VENDOR_ID, BCM53442_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1393 { BROADCOM_VENDOR_ID, BCM53434_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1394 { BROADCOM_VENDOR_ID, BCM56965_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1395 { BROADCOM_VENDOR_ID, BCM56969_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1396 { BROADCOM_VENDOR_ID, BCM56966_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1397 { BROADCOM_VENDOR_ID, BCM56967_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1398 { BROADCOM_VENDOR_ID, BCM56170_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1399 { BROADCOM_VENDOR_ID, BCM56172_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1400 { BROADCOM_VENDOR_ID, BCM56174_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1401 { BROADCOM_VENDOR_ID, BCM53570_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1402 { BROADCOM_VENDOR_ID, BCM53575_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1403 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9656, PCI_ANY_ID, PCI_ANY_ID }, 1404 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, PCI_ANY_ID, PCI_ANY_ID }, 1405 { BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1406 #ifdef BCM_PETRA_SUPPORT 1407 { BROADCOM_VENDOR_ID, BCM88650_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1408 { BROADCOM_VENDOR_ID, BCM88350_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1409 { BROADCOM_VENDOR_ID, BCM88351_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1410 { BROADCOM_VENDOR_ID, BCM88450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1411 { BROADCOM_VENDOR_ID, BCM88451_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1412 { BROADCOM_VENDOR_ID, BCM88550_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1413 { BROADCOM_VENDOR_ID, BCM88551_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1414 { BROADCOM_VENDOR_ID, BCM88552_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1415 { BROADCOM_VENDOR_ID, BCM88651_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1416 { BROADCOM_VENDOR_ID, BCM88654_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1417 { PCP_PCI_VENDOR_ID, PCP_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1418 { ACP_PCI_VENDOR_ID, ACP_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1419 { BROADCOM_VENDOR_ID, BCM88660_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1420 { BROADCOM_VENDOR_ID, BCM88670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1421 { BROADCOM_VENDOR_ID, BCM88671_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1422 { BROADCOM_VENDOR_ID, BCM88671M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1423 { BROADCOM_VENDOR_ID, BCM88672_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1424 { BROADCOM_VENDOR_ID, BCM88673_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1425 { BROADCOM_VENDOR_ID, BCM88674_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1426 { BROADCOM_VENDOR_ID, BCM88675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1427 { BROADCOM_VENDOR_ID, BCM88675M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1428 { BROADCOM_VENDOR_ID, BCM88676_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1429 { BROADCOM_VENDOR_ID, BCM88676M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1430 { BROADCOM_VENDOR_ID, BCM88677_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1431 { BROADCOM_VENDOR_ID, BCM88678_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1432 { BROADCOM_VENDOR_ID, BCM88679_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1433 { BROADCOM_VENDOR_ID, BCM88370_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1434 { BROADCOM_VENDOR_ID, BCM88371_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1435 { BROADCOM_VENDOR_ID, BCM88371M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1436 { BROADCOM_VENDOR_ID, BCM88375_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1437 { BROADCOM_VENDOR_ID, BCM88470_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1438 { BROADCOM_VENDOR_ID, BCM88470P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1439 { BROADCOM_VENDOR_ID, BCM88471_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1440 { BROADCOM_VENDOR_ID, BCM88473_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1441 { BROADCOM_VENDOR_ID, BCM88474_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1442 { BROADCOM_VENDOR_ID, BCM88474H_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1443 { BROADCOM_VENDOR_ID, BCM88476_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1444 { BROADCOM_VENDOR_ID, BCM88477_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1445 1446 1447 { BROADCOM_VENDOR_ID, BCM88270_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1448 { BROADCOM_VENDOR_ID, BCM88272_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1449 { BROADCOM_VENDOR_ID, BCM88273_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1450 { BROADCOM_VENDOR_ID, BCM88274_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1451 { BROADCOM_VENDOR_ID, BCM88278_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1452 { BROADCOM_VENDOR_ID, BCM88279_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1453 1454 { BROADCOM_VENDOR_ID, BCM8206_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1455 1456 { BROADCOM_VENDOR_ID, BCM88376_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1457 { BROADCOM_VENDOR_ID, BCM88376M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1458 { BROADCOM_VENDOR_ID, BCM88377_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1459 { BROADCOM_VENDOR_ID, BCM88378_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1460 { BROADCOM_VENDOR_ID, BCM88379_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1461 { BROADCOM_VENDOR_ID, BCM88680_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1462 { BROADCOM_VENDOR_ID, BCM88681_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1463 { BROADCOM_VENDOR_ID, BCM88682_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1464 { BROADCOM_VENDOR_ID, BCM88683_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1465 { BROADCOM_VENDOR_ID, BCM88684_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1466 { BROADCOM_VENDOR_ID, BCM88685_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1467 { BROADCOM_VENDOR_ID, BCM88380_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1468 { BROADCOM_VENDOR_ID, BCM88381_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1469 { BROADCOM_VENDOR_ID, BCM88202_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1470 { BROADCOM_VENDOR_ID, BCM88360_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1471 { BROADCOM_VENDOR_ID, BCM88361_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1472 { BROADCOM_VENDOR_ID, BCM88363_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1473 { BROADCOM_VENDOR_ID, BCM88460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1474 { BROADCOM_VENDOR_ID, BCM88461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1475 { BROADCOM_VENDOR_ID, BCM88560_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1476 { BROADCOM_VENDOR_ID, BCM88561_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1477 { BROADCOM_VENDOR_ID, BCM88562_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1478 { BROADCOM_VENDOR_ID, BCM88661_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1479 { BROADCOM_VENDOR_ID, BCM88664_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1480 #endif 1481 #ifdef BCM_DNX_SUPPORT 1482 { BROADCOM_VENDOR_ID, BCM88690_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1483 { BROADCOM_VENDOR_ID, BCM88690_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1484 { BROADCOM_VENDOR_ID, BCM88691_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1485 { BROADCOM_VENDOR_ID, BCM88692_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1486 { BROADCOM_VENDOR_ID, BCM88693_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1487 { BROADCOM_VENDOR_ID, BCM88694_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1488 { BROADCOM_VENDOR_ID, BCM88695_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1489 { BROADCOM_VENDOR_ID, BCM88696_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1490 { BROADCOM_VENDOR_ID, BCM88697_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1491 { BROADCOM_VENDOR_ID, BCM88698_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1492 { BROADCOM_VENDOR_ID, BCM88699_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1493 { BROADCOM_VENDOR_ID, BCM8869A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1494 { BROADCOM_VENDOR_ID, BCM8869B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1495 { BROADCOM_VENDOR_ID, BCM8869C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1496 { BROADCOM_VENDOR_ID, BCM8869D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1497 { BROADCOM_VENDOR_ID, BCM8869F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1498 { BROADCOM_VENDOR_ID, BCM88800_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1499 #endif /* BCM_DNX_SUPPORT */ 1500 #ifdef BCM_DFE_SUPPORT 1501 { BROADCOM_VENDOR_ID, BCM88750_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1502 { BROADCOM_VENDOR_ID, BCM88753_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1503 { BROADCOM_VENDOR_ID, BCM88755_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1504 { BROADCOM_VENDOR_ID, BCM88770_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1505 { BROADCOM_VENDOR_ID, BCM88773_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1506 { BROADCOM_VENDOR_ID, BCM88774_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1507 { BROADCOM_VENDOR_ID, BCM88775_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1508 { BROADCOM_VENDOR_ID, BCM88776_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1509 { BROADCOM_VENDOR_ID, BCM88777_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1510 #ifndef DNX_IGNORE_FE3200 1511 { BROADCOM_VENDOR_ID, BCM88950_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1512 #endif 1513 { BROADCOM_VENDOR_ID, BCM88953_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1514 { BROADCOM_VENDOR_ID, BCM88954_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1515 { BROADCOM_VENDOR_ID, BCM88955_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1516 { BROADCOM_VENDOR_ID, BCM88956_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1517 { BROADCOM_VENDOR_ID, BCM88752_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1518 { BROADCOM_VENDOR_ID, BCM88772_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1519 { BROADCOM_VENDOR_ID, BCM88952_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1520 #endif 1521 #ifdef BCM_DNXF_SUPPORT 1522 { BROADCOM_VENDOR_ID, BCM88790_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1523 { BROADCOM_VENDOR_ID, BCM88791_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1524 { BROADCOM_VENDOR_ID, BCM88792_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1525 { BROADCOM_VENDOR_ID, BCM88793_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1526 { BROADCOM_VENDOR_ID, BCM88794_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1527 { BROADCOM_VENDOR_ID, BCM88795_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1528 { BROADCOM_VENDOR_ID, BCM88796_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1529 { BROADCOM_VENDOR_ID, BCM88797_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1530 { BROADCOM_VENDOR_ID, BCM88798_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1531 { BROADCOM_VENDOR_ID, BCM88799_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1532 { BROADCOM_VENDOR_ID, BCM8879A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1533 { BROADCOM_VENDOR_ID, BCM8879B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1534 { BROADCOM_VENDOR_ID, BCM8879C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1535 { BROADCOM_VENDOR_ID, BCM8879D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1536 { BROADCOM_VENDOR_ID, BCM8879F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1537 #endif 1538 { BROADCOM_VENDOR_ID, BCM56860_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1539 { BROADCOM_VENDOR_ID, BCM56861_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1540 { BROADCOM_VENDOR_ID, BCM56862_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1541 { BROADCOM_VENDOR_ID, BCM56864_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1542 { BROADCOM_VENDOR_ID, BCM56865_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1543 { BROADCOM_VENDOR_ID, BCM56866_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1544 { BROADCOM_VENDOR_ID, BCM56867_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1545 { BROADCOM_VENDOR_ID, BCM56868_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1546 { BROADCOM_VENDOR_ID, BCM56833_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1547 { BROADCOM_VENDOR_ID, BCM56832_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1548 { BROADCOM_VENDOR_ID, BCM56836_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1549 { BROADCOM_VENDOR_ID, BCM56870_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1550 { BROADCOM_VENDOR_ID, BCM56370_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1551 { BROADCOM_VENDOR_ID, BCM56371_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1552 { BROADCOM_VENDOR_ID, BCM56372_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1553 { BROADCOM_VENDOR_ID, BCM56374_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1554 { BROADCOM_VENDOR_ID, BCM56375_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1555 { BROADCOM_VENDOR_ID, BCM56376_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1556 { BROADCOM_VENDOR_ID, BCM56377_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1557 { BROADCOM_VENDOR_ID, BCM56577_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1558 { BROADCOM_VENDOR_ID, BCM56578_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1559 { BROADCOM_VENDOR_ID, BCM56579_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1560 { BROADCOM_VENDOR_ID, BCM56873_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1561 { BROADCOM_VENDOR_ID, BCM56770_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1562 { BROADCOM_VENDOR_ID, BCM56771_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1563 { BROADCOM_VENDOR_ID, BCM56980_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1564 { BROADCOM_VENDOR_ID, BCM56981_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1565 { BROADCOM_VENDOR_ID, BCM56982_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1566 { BROADCOM_VENDOR_ID, BCM56983_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1567 { BROADCOM_VENDOR_ID, BCM56984_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1568 { BROADCOM_VENDOR_ID, BCM53540_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1569 { BROADCOM_VENDOR_ID, BCM53547_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1570 { BROADCOM_VENDOR_ID, BCM53548_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1571 { BROADCOM_VENDOR_ID, BCM53549_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1572 { 0, 0, 0, 0 } 1573 };; 1574 1575 MODULE_DEVICE_TABLE(pci, _id_table); 1576 1577 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 1578 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) 1579 #define MAX_RC_NUM 4 1580 1581 static struct pci_bus * 1582 pci_do_bus_find(struct pci_bus* bus, int rc, int vendor, int device) 1583 { 1584 struct list_head *tmp; 1585 struct pci_dev *dev; 1586 struct pci_bus *sub_bus; 1587 int func = 0; 1588 1589 if (unlikely(list_empty(&bus->children))) { 1590 return NULL; 1591 } 1592 list_for_each(tmp, &bus->children) { 1593 sub_bus = pci_bus_b(tmp); 1594 dev = sub_bus->self; 1595 func = dev->devfn & 0x7; 1596 if (dev->vendor == vendor && dev->device == device && rc == func) { 1597 if (debug >= 1) { 1598 gprintk("pci_do_bus_find: dev->vendor = 0x%x, dev->device = 0x%x on rc(%d)\n", 1599 dev->vendor, dev->device, rc); 1600 } 1601 return sub_bus; 1602 } 1603 } 1604 return NULL; 1605 } 1606 1607 static struct pci_dev * 1608 _pci_do_bus_dev_find(struct pci_bus* bus, unsigned int vendor, unsigned int device) 1609 { 1610 struct list_head *tmp; 1611 struct pci_dev *dev; 1612 1613 if (unlikely(list_empty(&bus->devices))) { 1614 return NULL; 1615 } 1616 list_for_each(tmp, &bus->devices) { 1617 dev = pci_dev_b(tmp); 1618 if (dev->vendor == vendor && (device == PCI_ANY_ID || dev->device == device)) { 1619 if (debug >= 1) { 1620 gprintk("_pci_do_rc_dev_find: vendor = %x, device = %x\n", vendor, device); 1621 } 1622 return dev; 1623 } 1624 } 1625 return NULL; 1626 } 1627 1628 static struct pci_dev * 1629 pci_do_rc_dev_find(int rc) 1630 { 1631 struct pci_bus *root_bus = pci_find_bus(0,0); 1632 struct pci_bus *bus_rc = NULL; 1633 struct pci_dev *dev_on_rc = NULL; 1634 unsigned int pci_dev_id = 0; 1635 1636 if(NULL == root_bus) { 1637 if (debug >= 1) gprintk("Not find root bus\n"); 1638 return NULL; 1639 } 1640 bus_rc = pci_do_bus_find(root_bus, rc, 0x184e, 0x1004); 1641 if (NULL == bus_rc) { 1642 if (debug >= 1) { 1643 gprintk("Not find vendor(0x184e) device(0x1004) bus\n"); 1644 } 1645 return NULL; 1646 } 1647 for(pci_dev_id = 0; pci_dev_id < sizeof(_id_table)/sizeof(struct pci_device_id); pci_dev_id++) { 1648 dev_on_rc = _pci_do_bus_dev_find(bus_rc, _id_table[pci_dev_id].vendor, _id_table[pci_dev_id].device); 1649 if (NULL != dev_on_rc) { 1650 return dev_on_rc; 1651 } 1652 } 1653 if (debug >= 1) { 1654 gprintk("Not find device at rc(%d)\n", rc); 1655 } 1656 return NULL; 1657 } 1658 1659 /* 1660 * Function: p2p_bridge 1661 * 1662 * Purpose: 1663 * Finalize initialization secondary PCI-PCI bridge. 1664 * Parameters: 1665 * membase - start of memory address space for secondary PCI bus 1666 * Returns: 1667 * 0 1668 * Notes: 1669 * The membase depends on the processor architecture, and is 1670 * derived from the memory space addresses set up by the kernel. 1671 */ 1672 static int 1673 p2p_bridge(void) 1674 { 1675 struct pci_dev *dev, *dev_on_rc; 1676 uint16 cmd; 1677 uint16 mem_base; 1678 uint16 mem_limit; 1679 uint8 bridge_ctrl; 1680 uint8 rc_index; 1681 1682 if ((dev = PCI_FIND_DEV(DC21150_VENDOR_ID, DC21150_DEVICE_ID, NULL)) != NULL || 1683 (dev = PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL)) != NULL || 1684 (dev = PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) != NULL) { 1685 1686 if (debug >= 1) gprintk("fixing up PCI-to-PCI bridge\n"); 1687 /* Adjust command register */ 1688 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1689 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 1690 /* Disable device */ 1691 pci_write_config_word(dev, PCI_COMMAND, 0); 1692 /* Initialize non-prefetchable memory window if needed */ 1693 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base); 1694 if (mem_base == 0) { 1695 mem_base = (uint16)((_pci_mem_start & 0xFFF00000) >> 16); 1696 mem_limit = (uint16)((_pci_mem_end & 0xFFF00000) >> 16); 1697 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); 1698 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); 1699 } 1700 /* Enable PCI clocks on remote end */ 1701 pci_write_config_word(dev, PCI_CFG_DEC21150_SEC_CLK, 0); 1702 /* Re-enable config space */ 1703 pci_write_config_word(dev, PCI_COMMAND, cmd); 1704 1705 /* Avoid DMA data corruption */ 1706 if (dev->vendor == HINT_HB4_VENDOR_ID) { 1707 /* Fix for HiNT bridge and BCM4704 DMA problem */ 1708 if ((dev = PCI_FIND_DEV(BCM4704_VENDOR_ID, BCM4704_DEVICE_ID, NULL)) != NULL) { 1709 /* Reset PrefetchEn (PE) */ 1710 pci_write_config_dword(dev, 0x8c, 1); 1711 if (debug >= 1) { 1712 gprintk("reset PrefetchEn on BCM4704 when HiNT bridge is present\n"); 1713 } 1714 } 1715 } 1716 } 1717 /* Enable fast back-to-back read/write */ 1718 if ((dev = PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) != NULL) { 1719 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1720 cmd |= PCI_COMMAND_FAST_BACK; 1721 pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bridge_ctrl); 1722 bridge_ctrl |= PCI_BRIDGE_CTL_FAST_BACK; 1723 pci_write_config_word(dev, PCI_COMMAND, 0); 1724 pci_write_config_byte(dev, PCI_BRIDGE_CONTROL, bridge_ctrl); 1725 pci_write_config_word(dev, PCI_COMMAND, cmd); 1726 } 1727 /* Netlogic XLP CPU */ 1728 for(rc_index = 0; rc_index < MAX_RC_NUM; rc_index++) { 1729 dev_on_rc = pci_do_rc_dev_find(rc_index); 1730 if (dev_on_rc != NULL ) { 1731 dev = PCI_FIND_DEV(0x184e, 0x1004, NULL); 1732 if (dev != NULL ) { 1733 pci_write_config_dword(dev,0x78,MAX_PAYLOAD_256B | 1734 MAX_READ_REQ_256B); 1735 } 1736 } 1737 } 1738 if ((dev = PCI_FIND_DEV(0x14e4, 0xb634, NULL)) != NULL) { 1739 pci_write_config_dword(dev,0x78,MAX_PAYLOAD_256B | 1740 MAX_READ_REQ_256B); 1741 } 1742 1743 if ((dev = PCI_FIND_DEV(PCI_VNDID_PERICOM, PCI_DEVID_PI7C9X130, NULL)) != NULL) { 1744 /* 1745 * Configure the PCIE cap: Max payload size: 256, Max Read 1746 * Request size: 256, disabling relax ordering. 1747 * Writes to the PCIE capability device control register 1748 */ 1749 pci_write_config_dword(dev, DEV_CTRL_REG, 1750 MAX_PAYLOAD_256B | MAX_READ_REQ_256B); 1751 } 1752 1753 if ((dev = PCI_FIND_DEV(FSL_VENDOR_ID, FSL8548PCIE_DEVICE_ID, NULL)) != NULL || 1754 (dev = PCI_FIND_DEV(FSL_VENDOR_ID, FSL2020EPCIE_DEVICE_ID, NULL)) != NULL) { 1755 /* 1756 * Configure the PCIE cap: Max payload size: 256, Max Read 1757 * Request size: 256, disabling relax ordering. 1758 * Writes to the PCIE capability device control register 1759 */ 1760 pci_write_config_dword(dev, FSL8548PCIE_DEV_CTRL_REG, 1761 MAX_PAYLOAD_256B | MAX_READ_REQ_256B); 1762 } 1763 if ((dev = PCI_FIND_DEV(BCM4716_VENDOR_ID, BCM4716PCIE_DEVICE_ID, NULL)) != NULL || 1764 (dev = PCI_FIND_DEV(BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, NULL)) != NULL) { 1765 uint32 tmp, maxpayld, device_bmp=0, mask; 1766 unsigned long addr; 1767 uint16 tmp16, tmp161; 1768 int i, bus0 = -1, bus1 = -1, port; 1769 struct pci_dev *pcie0, *pcie1; 1770 1771 pcie0 = dev; 1772 bus0 = dev->bus->number; 1773 if ((pcie1 = PCI_FIND_DEV(BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, pcie0)) != NULL) { 1774 bus1 = pcie1->bus->number; 1775 } 1776 1777 for(i = 0; i < _ndevices; i++) { 1778 bde_ctrl_t *ctrl = _devices + i; 1779 1780 mask = BDE_SWITCH_DEV_TYPE | BDE_PCI_DEV_TYPE; 1781 if ((ctrl->dev_type & mask) == mask) { 1782 if (ctrl->pci_device->bus->number == bus0) { 1783 device_bmp |= 1 << 0; 1784 } 1785 if (ctrl->pci_device->bus->number == bus1) { 1786 device_bmp |= 1 << 1; 1787 } 1788 } 1789 } 1790 1791 /* configure the PCIE cap: Max payload size: 256, Max Read 1792 * Request size: 256, disabling relax ordering. 1793 * Writes to the PCIE capability device control register 1794 */ 1795 1796 i = 0; 1797 while(device_bmp) { 1798 if (device_bmp & (1 << i)){ 1799 port = i ; 1800 pci_read_config_dword(BCM53000PCIE_DEV(port), 1801 BCM53000PCIE_DEV_CAP_REG, &tmp); 1802 maxpayld = (tmp & BCM53000PCIE_MAX_PAYLOAD_MASK); 1803 if (debug >= 1) { 1804 gprintk("port %d\n",port); 1805 gprintk("DevCap (@%x): 0x%x%c\n", BCM53000PCIE_DEV_CAP_REG, tmp, 1806 (maxpayld != BCM53000PCIE_CAP_MAX_PAYLOAD_256B) ? ' ':'\n'); 1807 } 1808 if (maxpayld != BCM53000PCIE_CAP_MAX_PAYLOAD_256B) { 1809 addr = BCM53000PCIE_BASE(port); 1810 addr |= (BCM53000PCIE_SROM_SPACE | BCM53000PCIE_SPROM_OFFSET); 1811 tmp16 = *((uint16 *)addr); 1812 if (debug >= 1){ 1813 gprintk("addr %lx spromData.MaxPayloadSize: 0x%x\n", addr, tmp16); 1814 } 1815 mask = BCM53000PCIE_SPROM_MAX_PAYLOAD_MASK; 1816 if ((tmp16 & mask) != BCM53000PCIE_SPROM_MAX_PAYLOAD_256B) { 1817 tmp161 = (tmp16 & ~mask) | BCM53000PCIE_SPROM_MAX_PAYLOAD_256B; 1818 *((uint16 *)addr) = tmp161; 1819 if (debug >= 1) { 1820 tmp16 = 0; 1821 tmp16 = *((uint16 *)addr); 1822 gprintk("Enable spromData.MaxPayloadSize to 1 (256 bytes): " 1823 "0x%x (%s w/ 0x%x)\n", tmp161, 1824 ((tmp16 & mask) == BCM53000PCIE_SPROM_MAX_PAYLOAD_256B) ? 1825 "Success":"Fail", 1826 tmp16); 1827 } 1828 } 1829 pci_read_config_dword(BCM53000PCIE_DEV(port), 1830 BCM53000PCIE_DEV_CAP_REG, &tmp); 1831 if (debug >= 1){ 1832 gprintk("DevCap (@%x): now is 0x%x\n\n", 1833 BCM53000PCIE_DEV_CAP_REG, tmp); 1834 } 1835 } 1836 1837 addr = BCM53000PCIE_BASE(port); 1838 addr |= (BCM53000PCIE_FUNC0_COFIG_SPACE | BCM53000PCIE_DEV_CTRL_REG); 1839 tmp16 = *((uint16 *)addr); 1840 if (debug >= 1) { 1841 gprintk("DevControl (@%x): 0x%x\n", BCM53000PCIE_DEV_CTRL_REG, tmp16); 1842 } 1843 if (!(tmp16 & MAX_PAYLOAD_256B) || !(tmp16 & MAX_READ_REQ_256B)) { 1844 tmp161 = tmp16 | MAX_PAYLOAD_256B | MAX_READ_REQ_256B; 1845 *((uint16 *)addr) = tmp161; 1846 if (debug >= 1) { 1847 tmp16 = 0; 1848 tmp16 = *((uint16 *)addr); 1849 gprintk("addr %lx Enable DevControl MaxPayloadSize to 1 (256 bytes): " 1850 "0x%x (%s w/ 0x%x)\n", addr, tmp161, 1851 (tmp16 & MAX_PAYLOAD_256B) ? "Success":"Fail", 1852 tmp16); 1853 gprintk("Enable DevControl MaxReadRequestSize to 1 (256 bytes): " 1854 "0x%x (%s w/ 0x%x)\n\n", tmp161, 1855 (tmp16 & MAX_READ_REQ_256B) ? "Success":"Fail", 1856 tmp16); 1857 } 1858 } 1859 device_bmp &= ~(1 << i); 1860 } 1861 i++; 1862 } 1863 } 1864 1865 /* 1866 * Configure max payload to 512 on all ports in the PLX8608/PLX8617. 1867 * The device supports 128, 512, and 1024 max payload sizes. 1868 */ 1869 dev = NULL; 1870 while ((dev = PCI_FIND_DEV(PCI_VENDOR_ID_PLX, PCI_ANY_ID, dev)) != NULL) { 1871 if ((dev->device == PLX_PEX8608_DEV_ID) || 1872 (dev->device == PLX_PEX8617_DEV_ID)) { 1873 uint16 ctrl_reg; 1874 pci_read_config_word(dev, PLX_PEX86XX_DEV_CTRL_REG, &ctrl_reg); 1875 ctrl_reg = (ctrl_reg & ~(7<<5)) | MAX_PAYLOAD_512B; 1876 pci_write_config_word(dev, PLX_PEX86XX_DEV_CTRL_REG, ctrl_reg); 1877 } 1878 } 1879 return 0; 1880 } 1881 1882 #ifdef BCM_PLX9656_LOCAL_BUS 1883 1884 #define PLX_LAS0_BA 0x00000004 /* LAS0 Local Base Address Remap */ 1885 #define PLX_LAS1_BA 0x000000f4 /* LAS1 Local Base Address Remap */ 1886 #define PLX_LAS_EN 0x00000001 /* Space Enable bit */ 1887 1888 #define PLX_MMAP_PCIBAR0 0 /* Memory-Mapped Config (PCIBAR0) */ 1889 #define PLX_LAS0_PCIBAR2 2 /* Local Address Space 0 (PCIBAR2) */ 1890 #define PLX_LAS1_PCIBAR3 3 /* Local Address Space 1 (PCIBAR3) */ 1891 1892 STATIC int 1893 _plx_las_bar_get(struct pci_dev *dev) 1894 { 1895 void *local_config_addr; 1896 int bar = -1; 1897 1898 local_config_addr = IOREMAP(pci_resource_start(dev, PLX_MMAP_PCIBAR0), 1899 pci_resource_len(dev, PLX_MMAP_PCIBAR0)); 1900 if (local_config_addr) { 1901 uint32 las_remap_reg; 1902 /* 1903 * Make sure LAS0BA or LAS1BA is enabled before returning 1904 * BAR that will be used to access the Local Bus 1905 */ 1906 las_remap_reg = ioread32(local_config_addr + PLX_LAS0_BA); 1907 if (las_remap_reg & PLX_LAS_EN) { 1908 bar = PLX_LAS0_PCIBAR2; 1909 } else { 1910 las_remap_reg = ioread32(local_config_addr + PLX_LAS1_BA); 1911 if (las_remap_reg & PLX_LAS_EN) { 1912 bar = PLX_LAS1_PCIBAR3; 1913 } 1914 } 1915 } 1916 iounmap(local_config_addr); 1917 return bar; 1918 } 1919 #endif /* BCM_PLX9656_LOCAL_BUS */ 1920 1921 static void 1922 _shbde_log_func(int level, const char *str, int param) 1923 { 1924 level = (level >= SHBDE_DBG) ? 1 : 0; 1925 if (debug >= level) { 1926 gprintk("%s (%d)\n", str, param); 1927 } 1928 } 1929 /* 1930 * Function: _device_rescan_validate 1931 * 1932 * Purpose: 1933 * Check if the device is ever probed or not. 1934 * Parameters: 1935 * dev - Linux PCI device structure 1936 * Returns: 1937 * >= 0 : dev is ever probed 1938 * reutrn value is the index point to the _devices[] 1939 * -1 : dev is not probed before. 1940 */ 1941 static int 1942 _device_rescan_validate(struct pci_dev *dev) 1943 { 1944 bde_ctrl_t *ctrl; 1945 int i; 1946 1947 if (PCI_FUNC(dev->devfn) > 0) { 1948 return -1; 1949 } 1950 ctrl = NULL; 1951 for (i = 0; i < _ndevices; i ++) { 1952 ctrl = _devices + i; 1953 /* check the device id */ 1954 if (dev->device == ctrl->bde_dev.device) { 1955 /* check the bus number */ 1956 if ((dev->bus)) { 1957 if ((dev->bus->number == ctrl->bus_no) && 1958 (pci_domain_nr(dev->bus) == ctrl->domain_no)) { 1959 return i; 1960 } 1961 } 1962 } 1963 } 1964 return -1; 1965 } 1966 1967 #ifdef CONFIG_PCI_MSI 1968 1969 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 1970 /** 1971 * _pci_msix_table_size - return the number of device's MSI-X table entries 1972 * @dev: pointer to the pci_dev data structure of MSI-X device function 1973 */ 1974 static int 1975 _pci_msix_table_size(struct pci_dev *dev) 1976 { 1977 int nr_entries = 0; 1978 1979 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,110)) 1980 u16 control; 1981 int pos; 1982 1983 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1984 if (pos) { 1985 pci_read_config_word(dev, msi_control_reg(pos), &control); 1986 nr_entries = msix_table_size(control); 1987 } 1988 #else 1989 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) 1990 { 1991 /* Pass large entry value to enable MSIX to get # of entires */ 1992 struct msix_entry *entries; 1993 entries = kmalloc(sizeof(struct msix_entry) * 1994 PCI_MSIX_FLAGS_QSIZE, GFP_KERNEL); 1995 if (entries != NULL) { 1996 nr_entries = pci_enable_msix(dev, 1997 entries, PCI_MSIX_FLAGS_QSIZE); 1998 if (nr_entries < 0) { 1999 nr_entries = 0; 2000 } 2001 pci_disable_msix(dev); 2002 kfree(entries); 2003 } 2004 } 2005 #else 2006 nr_entries = pci_msix_vec_count(dev); 2007 #endif 2008 #endif 2009 2010 return nr_entries; 2011 } 2012 #endif 2013 2014 static int 2015 _msi_connect(bde_ctrl_t *ctrl) 2016 { 2017 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2018 int ret; 2019 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2020 int i; 2021 2022 ret = _pci_msix_table_size(ctrl->pci_device); 2023 if (ret == 0) { 2024 /* MSI-X failed */ 2025 gprintk("MSI-X not supported.\n"); 2026 goto er_intx; 2027 } 2028 ctrl->entries = kcalloc(ret, sizeof(struct msix_entry), GFP_KERNEL); 2029 2030 if (!ctrl->entries) { 2031 goto er_intx; 2032 } 2033 /* Only one vector is mapped by default */ 2034 /* May be more in future, can be controlled using module param */ 2035 ctrl->msix_cnt = msixcnt; 2036 if (unlikely(debug > 1)) 2037 gprintk("MSIX Table size = %d\n", ctrl->msix_cnt); 2038 for (i = 0; i < ctrl->msix_cnt; i++) 2039 ctrl->entries[i].entry = i; 2040 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0) 2041 ret = pci_enable_msix_range(ctrl->pci_device, 2042 ctrl->entries, ctrl->msix_cnt, ctrl->msix_cnt); 2043 #else 2044 ret = pci_enable_msix(ctrl->pci_device, 2045 ctrl->entries, ctrl->msix_cnt); 2046 if (ret > 0) { 2047 /* Not enough vectors available , Retry MSI-X */ 2048 gprintk("Retrying with MSI-X interrupts = %d\n", ret); 2049 ctrl->msix_cnt = ret; 2050 msixcnt = ret; 2051 ret = pci_enable_msix(ctrl->pci_device, 2052 ctrl->entries, ctrl->msix_cnt); 2053 if (ret != 0) 2054 goto er_intx_free; 2055 } 2056 #endif 2057 if (ret < 0) { 2058 /* Error */ 2059 goto er_intx_free; 2060 } else { 2061 gprintk("Enabled MSI-X interrupts = %d\n", ctrl->msix_cnt); 2062 return 0; 2063 } 2064 } 2065 #endif 2066 2067 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2068 if (pci_enable_msi(ctrl->pci_device) == 0) { 2069 ctrl->iLine = ctrl->pci_device->irq; 2070 } else { 2071 /* MSI failed */ 2072 gprintk("Failed to initialize MSI interrupts.\n"); 2073 goto er_intx; 2074 } 2075 } else { 2076 /* failed */ 2077 gprintk("Not MSI/MSIX interrupt.\n"); 2078 goto er_intx; 2079 } 2080 return 0; 2081 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2082 er_intx_free: 2083 gprintk("Failed to enable MSI-X interrupts = %d\n", ret); 2084 kfree(ctrl->entries); 2085 #endif 2086 er_intx: 2087 return -1; 2088 2089 } 2090 2091 static int 2092 _msi_disconnect(bde_ctrl_t *ctrl) 2093 { 2094 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2095 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2096 if (ctrl->msix_cnt) { 2097 pci_disable_msix(ctrl->pci_device); 2098 kfree(ctrl->entries); 2099 ctrl->entries = NULL; 2100 ctrl->msix_cnt = 0; 2101 } 2102 } 2103 #endif 2104 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2105 pci_disable_msi(ctrl->pci_device); 2106 } else { 2107 gprintk("MSI not used\n"); 2108 } 2109 return 0; 2110 } 2111 2112 #endif 2113 2114 2115 static void 2116 config_pci_intr_type(struct pci_dev *dev, bde_ctrl_t *ctrl, int iproc) 2117 { 2118 #ifdef CONFIG_PCI_MSI 2119 int ret; 2120 shbde_iproc_config_t icfg; 2121 2122 /* Each device follows global policy by default */ 2123 ctrl->use_msi = use_msi; 2124 2125 if (unlikely(debug > 1)) 2126 gprintk("%s: msi = %d\n", __func__, ctrl->use_msi); 2127 2128 /* Check IPROC version for MSIX support */ 2129 if (iproc && ctrl->bde_dev.base_address1 && 2130 (ctrl->use_msi == PCI_USE_INT_MSIX)) { 2131 if (shbde_pci_iproc_version_get(&ctrl->shbde, dev, &icfg.iproc_ver, 2132 &icfg.cmic_ver, &icfg.cmic_rev)) { 2133 if (icfg.iproc_ver < 0xe) { 2134 gprintk("%s: MSI-X not supported, using MSI.\n", __func__); 2135 ctrl->use_msi = PCI_USE_INT_MSI; 2136 } 2137 } 2138 } 2139 2140 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2141 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2142 /* check for support MSIX vector */ 2143 ret = _pci_msix_table_size(ctrl->pci_device); 2144 if (ret == 0) { 2145 gprintk("%s: Zero MSIX table size\n", __func__); 2146 ctrl->use_msi = PCI_USE_INT_MSI; 2147 } 2148 } 2149 #endif 2150 2151 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2152 /* check for support MSI vector */ 2153 ret = pci_enable_msi(ctrl->pci_device); 2154 if (ret < 0) { 2155 ctrl->use_msi = PCI_USE_INT_INTX; 2156 gprintk("%s: Failed to enable MSI, using INTx.\n", __func__); 2157 } else { 2158 pci_disable_msi(ctrl->pci_device); 2159 } 2160 } 2161 #else 2162 ctrl->use_msi = PCI_USE_INT_INTX; 2163 #endif 2164 } 2165 2166 /* 2167 * Function: _pci_probe 2168 * 2169 * Purpose: 2170 * Device initialization callback used by the Linux PCI 2171 * subsystem. Called as a result of pci_register_driver(). 2172 * Parameters: 2173 * dev - Linux PCI device structure 2174 * Returns: 2175 * 0 2176 */ 2177 static int 2178 _pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) 2179 { 2180 bde_ctrl_t *ctrl; 2181 resource_size_t paddr; 2182 uint16 cmd = 0; 2183 uint32 bar_len; 2184 int cmic_bar; 2185 int baroff = 0; 2186 int iproc = 0; 2187 int plx_dev = 0; 2188 int eth_dev = 0; 2189 int cpu_dev = 0; 2190 int update_devid = 0; 2191 int paxb_core = 0; 2192 int add_dev = 0, rescan = 0, rescan_idx = -1; 2193 shbde_hal_t shared_bde, *shbde = &shared_bde; 2194 2195 if (debug >= 4) {gprintk("probing: vendor_id=0x%x, device_id=0x%x\n", dev->vendor, dev->device);} 2196 if (nodevices == 1) { 2197 return 0; 2198 } 2199 2200 /* Initialize Linux hardware abstraction for shared BDE functions */ 2201 linux_shbde_hal_init(shbde, _shbde_log_func); 2202 2203 /* 2204 * If an AXI-based switch device has been found already, then it means 2205 * that the AXI bus has been probed, and that we should ignore devices 2206 * found on PCI bus zero. 2207 */ 2208 2209 #if defined(IPROC_CMICD) 2210 if ((dev->bus) && (dev->bus->number == 0)) { 2211 int i; 2212 uint32 mask = BDE_SWITCH_DEV_TYPE | BDE_AXI_DEV_TYPE; 2213 2214 for (i = 0; i < _ndevices; i++) { 2215 ctrl = _devices + i; 2216 2217 if ((ctrl->dev_type & mask) == mask) { 2218 return 0; 2219 } 2220 } 2221 } 2222 #endif /* IPROC_CMICD */ 2223 2224 /* 2225 * Note that a few supported devices have a non-Broadcom PCI vendor ID, 2226 * but since none of their associated PCI device IDs collide with the 2227 * Broadcom device IDs, the probe code below only checks the device ID. 2228 */ 2229 2230 switch (dev->device) { 2231 case PCI_DEVICE_ID_PLX_9056: 2232 #ifdef DNX_TEST_BOARD 2233 break; /* a PCIe bridge to a non PCIe device should be treated as the device */ 2234 #endif /* DNX_TEST_BOARD */ 2235 case PCI_DEVICE_ID_PLX_9656: 2236 plx_dev = 1; 2237 break; 2238 case BCM53000PCIE_DEVICE_ID: 2239 cpu_dev = 1; 2240 break; 2241 /* 2242 * The device ID for 56500, 56100 and 56300 family of devices may 2243 * be incorrect just after a PCI HW reset. It needs to be read 2244 * again after stabilization. 2245 */ 2246 case BCM56102_DEVICE_ID: 2247 case BCM56504_DEVICE_ID: 2248 case BCM56304_DEVICE_ID: 2249 case BCM56314_DEVICE_ID: 2250 case BCM56112_DEVICE_ID: 2251 update_devid = 1; 2252 break; 2253 default: 2254 break; 2255 } 2256 2257 /* Check if the device is ever probed. */ 2258 rescan_idx = _device_rescan_validate(dev); 2259 if (rescan_idx != -1) { 2260 rescan = 1; 2261 } 2262 2263 ctrl = NULL; 2264 if (plx_dev) { 2265 #if defined(BCM_PLX9656_LOCAL_BUS) 2266 /* PLX chip itself won't be part of _devices[]. */ 2267 baroff = _plx_las_bar_get(dev); 2268 if (baroff == -1) { 2269 gprintk("No Local Address Space enabled in PLX\n"); 2270 return 0; 2271 } 2272 ctrl = &plx_ctrl; 2273 num_plx++; 2274 #endif 2275 } else if (eth_dev) { 2276 if (_ether_ndevices >= LINUX_BDE_MAX_ETHER_DEVICES) { 2277 return 0;; 2278 } 2279 ctrl = _devices + _ndevices; 2280 ctrl->dev_type |= BDE_ETHER_DEV_TYPE; 2281 ctrl->iLine = dev->irq; 2282 add_dev = 1; 2283 if (debug >= 1) 2284 gprintk("Found PCI device %04x:%04x as Ethernet device\n", 2285 dev->vendor, dev->device); 2286 } else if (cpu_dev) { 2287 if (_cpu_ndevices >= LINUX_BDE_MAX_CPU_DEVICES) { 2288 return 0;; 2289 } 2290 ctrl = _devices + _ndevices; 2291 ctrl->dev_type |= BDE_CPU_DEV_TYPE; 2292 add_dev = 1; 2293 if (debug >= 1) 2294 gprintk("Found PCI device %04x:%04x as CPU device\n", 2295 dev->vendor, dev->device); 2296 } else { 2297 if (PCI_FUNC(dev->devfn) > 0) { 2298 return 0; 2299 } 2300 if (_switch_ndevices >= LINUX_BDE_MAX_SWITCH_DEVICES) { 2301 return 0; 2302 } 2303 2304 if (rescan) { 2305 if (debug >= 1) { 2306 gprintk("PCI device %04x:%04x is re-probed \n", 2307 dev->vendor, dev->device); 2308 } 2309 ctrl = _devices + rescan_idx; 2310 ctrl->dev_state = BDE_DEV_STATE_CHANGED; 2311 } else { 2312 ctrl = _devices + _ndevices; 2313 ctrl->dev_type |= BDE_SWITCH_DEV_TYPE; 2314 ctrl->domain_no = pci_domain_nr(dev->bus); 2315 ctrl->bus_no = dev->bus->number; 2316 ctrl->dev_state = BDE_DEV_STATE_NORMAL; 2317 add_dev = 1; 2318 } 2319 2320 /* Save shared BDE HAL in device structure */ 2321 MEMCPY(&ctrl->shbde, shbde, sizeof(ctrl->shbde)); 2322 2323 if (update_devid) { 2324 /* Re-read the device ID */ 2325 pci_read_config_word(dev, 2326 PCI_DEVICE_ID, 2327 &ctrl->bde_dev.device); 2328 dev->device = ctrl->bde_dev.device; 2329 } 2330 2331 if (debug >= 4) {gprintk("Enabling PCI device : vendor_id=0x%x, device_id=0x%x\n", dev->vendor, dev->device);} 2332 if (pci_enable_device(dev)) { 2333 gprintk("Cannot enable PCI device : vendor_id = %x, device_id = %x\n", 2334 dev->vendor, dev->device); 2335 } 2336 2337 /* FIXME: "workarounds" previously called "total h_acks" */ 2338 /* 2339 * These are workarounds to get around some existing 2340 * kernel problems :( 2341 */ 2342 2343 /* 2344 * While probing we determine the overall limits for the PCI 2345 * memory windows across all devices. These limits are used 2346 * later on by the PCI-PCI bridge code. 2347 */ 2348 if (pci_resource_start(dev, baroff) < _pci_mem_start) { 2349 _pci_mem_start = pci_resource_start(dev, baroff); 2350 } 2351 if (pci_resource_end(dev, baroff) > _pci_mem_end) { 2352 _pci_mem_end = pci_resource_end(dev, baroff); 2353 } 2354 2355 #ifdef CONFIG_SANDPOINT 2356 /* 2357 * Something wrong with the PCI subsystem in the mousse kernel. 2358 * The device is programmed correctly, but the irq in the pci 2359 * structure is hosed. This checks for the hosed-ness and fixes it. 2360 */ 2361 if (dev->irq > 100) { 2362 dev->irq = 2; 2363 gprintk("irq problem: setting irq = %d\n", dev->irq); 2364 } 2365 #endif 2366 2367 #ifdef CONFIG_BMW 2368 /* 2369 * PCI subsystem does not always program the system correctly. 2370 */ 2371 if (dev->irq < 16 && dev->irq != 2) { 2372 dev->irq = 2; 2373 gprintk("irq problem: setting irq = %d\n", dev->irq); 2374 } 2375 #endif 2376 2377 #ifdef CONFIG_IDT_79EB334 2378 /* 2379 * IDT kernel is not currently mapping interrupts correctly 2380 * Hardwired to core mips interrupt, irq 3 for kernel 2.4.18 2381 */ 2382 if (dev->irq != 3) { 2383 dev->irq = 3; 2384 gprintk("irq problem: setting irq = %d\n", dev->irq); 2385 } 2386 #endif 2387 2388 #ifdef CONFIG_BCM94702_CPCI 2389 /* 2390 * Hardwired to core mips interrupt irq 6 on MBZ 2391 */ 2392 if (dev->irq != 6) { 2393 dev->irq = 6; 2394 gprintk("irq problem: setting irq = %d\n", dev->irq); 2395 } 2396 #endif 2397 2398 if ((PCI_FIND_DEV(BCM4704_VENDOR_ID, BCM4704_DEVICE_ID, NULL)) != NULL) { 2399 /* 2400 * Decrease the PCI bus priority for the CPU for better overall 2401 * system performance. This change significantly reduces the 2402 * number of PCI retries from other devices on the PCI bus. 2403 */ 2404 void * _mc_vbase = IOREMAP(BCM4704_MEMC_BASE, 0x1000); 2405 int priorinv = 0x80; 2406 static int done = 0; 2407 if (!done) { 2408 done = 1; 2409 writel(priorinv, _mc_vbase + BCM4704_MEMC_PRIORINV); 2410 if (debug >= 1) 2411 gprintk("set BCM4704 PriorInvTim register to 0x%x\n", priorinv); 2412 iounmap(_mc_vbase); 2413 } 2414 } 2415 2416 if ((PCI_FIND_DEV(SIBYTE_PCI_VENDOR_ID, SIBYTE_PCI_DEVICE_ID, NULL)) != NULL) { 2417 /* 2418 * The BCM91125CPCI CPU boards with a PCI-PCI bridge use the same 2419 * interrupt line for all switch ships behind the bridge. 2420 */ 2421 if (PCI_FIND_DEV(DC21150_VENDOR_ID, DC21150_DEVICE_ID, NULL) || 2422 PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL) || 2423 PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) { 2424 /* 2425 * By default we try to guess the correct IRQ based on the design. 2426 * For now we only look at the bridge vendor, but it may be necessary 2427 * to look at the switch chip configuration as well. 2428 */ 2429 if (forceirq == -1) { 2430 if ((PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL)) || 2431 ((dev->device == BCM5674_DEVICE_ID) && 2432 (PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)))) { 2433 forceirq = 58; 2434 } else { 2435 forceirq = 56; 2436 } 2437 } 2438 } 2439 } 2440 2441 if (((PCI_FIND_DEV(BCM58525_PCI_VENDOR_ID, BCM58525_PCI_DEVICE_ID, NULL)) != NULL) || 2442 ((PCI_FIND_DEV(BCM58525_PCI_VENDOR_ID, BCM58522_PCI_DEVICE_ID, NULL)) != NULL) || 2443 ((PCI_FIND_DEV(BCM58712_PCI_VENDOR_ID, BCM58712_PCI_DEVICE_ID, NULL)) != NULL) ) { 2444 /* BCM58525/BCM58712 CPU boards support 128 Max payload size */ 2445 if (maxpayload) { 2446 maxpayload = 128; 2447 if (debug >= 1) gprintk("force max payload size to 128\n"); 2448 } 2449 } 2450 2451 if (forceirq > 0 && dev->irq != (uint32) forceirq) { 2452 if (forceirqubm & (1U << (_ndevices - 1))) { 2453 dev->irq = forceirq; 2454 if (debug >= 1) gprintk("force irq to %d\n", forceirq); 2455 } 2456 } else if (debug >= 1) gprintk("found irq %d\n", dev->irq); 2457 2458 ctrl->iLine = dev->irq; 2459 if (unlikely(debug > 1)) 2460 gprintk("%s:irq = %d\n",__func__, ctrl->iLine); 2461 2462 if (shbde_pci_is_pcie(shbde, dev)) { 2463 /* Set PCIe max payload */ 2464 shbde_pci_max_payload_set(shbde, dev, maxpayload); 2465 } else { 2466 /* Set PCI retry to infinite on non-PCIe switch device */ 2467 pci_write_config_word(dev, 0x40, 0x0080); 2468 if (debug >= 1) gprintk("set DMA retry to infinite on switch device\n"); 2469 } 2470 } 2471 2472 #if defined(BCM_DFE_SUPPORT) 2473 switch (dev->device) { 2474 case BCM88750_DEVICE_ID: 2475 case BCM88753_DEVICE_ID: 2476 case BCM88755_DEVICE_ID: 2477 case BCM88770_DEVICE_ID: 2478 case BCM88773_DEVICE_ID: 2479 case BCM88774_DEVICE_ID: 2480 case BCM88775_DEVICE_ID: 2481 case BCM88776_DEVICE_ID: 2482 case BCM88777_DEVICE_ID: 2483 case BCM88950_DEVICE_ID: 2484 case BCM88953_DEVICE_ID: 2485 case BCM88954_DEVICE_ID: 2486 case BCM88955_DEVICE_ID: 2487 case BCM88956_DEVICE_ID: 2488 case BCM88752_DEVICE_ID: 2489 case BCM88772_DEVICE_ID: 2490 case BCM88952_DEVICE_ID: 2491 2492 /* 2493 * For DMA transactions - set Max_Payload_Size and 2494 * Max_Read_Request_Size to 128 bytes. 2495 */ 2496 pci_write_config_byte(dev, 0xb5, 0x0c); 2497 pci_write_config_byte(dev, 0xb4, 0x0); 2498 break; 2499 default: 2500 break; 2501 } 2502 #endif /* BCM_DFE_SUPPORT */ 2503 2504 #if defined(BCM_DNXF_SUPPORT) 2505 /*All Ramon devices from 0x8790 to 0x879F*/ 2506 if ((dev->device & BCM_DNXF_DEVID_MASK) == BCM88790_DEVICE_ID) { 2507 /* 2508 * For DMA transactions - set Max_Payload_Size and 2509 * Max_Read_Request_Size to 128 bytes. 2510 */ 2511 pci_write_config_byte(dev, 0xb5, 0x0c); 2512 pci_write_config_byte(dev, 0xb4, 0x0); 2513 2514 } 2515 #endif 2516 2517 /* Prevent compiler warning */ 2518 if (ctrl == NULL) { 2519 return 0; 2520 } 2521 2522 ctrl->be_pio = 0; 2523 ctrl->dev_type |= BDE_PCI_DEV_TYPE; 2524 ctrl->pci_device = dev; 2525 pci_set_drvdata(dev, ctrl); 2526 2527 /* Check for iProc device */ 2528 if (shbde_pci_is_iproc(shbde, dev, &cmic_bar)) { 2529 iproc = 1; 2530 if (cmic_bar >= 0) { 2531 baroff = cmic_bar; 2532 } 2533 } 2534 #ifdef DNX_TEST_BOARD 2535 else if (dev->device == PLX9056_DEVICE_ID && baroff == 0) { 2536 baroff = 2; 2537 ctrl->dev_type |= BDE_NO_IPROC/* | BDE_BYTE_SWAP*/; 2538 } 2539 #endif /* DNX_TEST_BOARD */ 2540 2541 /* Get the device revision */ 2542 pci_read_config_byte(dev, PCI_REVISION_ID, &ctrl->bde_dev.rev); 2543 2544 /* Map in the device */ 2545 ctrl->bde_dev.device = dev->device; 2546 paddr = pci_resource_start(dev, baroff); 2547 2548 switch (dev->device) { 2549 #if defined(BCM_PETRA_SUPPORT) && defined(__DUNE_LINUX_BCM_CPU_PCIE__) 2550 case GEDI_DEVICE_ID: 2551 case PCP_PCI_DEVICE_ID: 2552 bar_len = 0x1000000; 2553 break; 2554 #endif 2555 default: 2556 bar_len = pci_resource_len(dev, baroff); 2557 break; 2558 } 2559 2560 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, bar_len); 2561 ctrl->phys_address = paddr; 2562 if (debug >= 3) { 2563 gprintk("BAR %d: kernel addr:0x%lx phys addr:0x%lx length:%lx\n", 2564 baroff, (unsigned long)ctrl->bde_dev.base_address, (unsigned long)paddr, (unsigned long)bar_len); 2565 } 2566 2567 /* Map secondary address spaces */ 2568 if (iproc 2569 #ifdef DNX_TEST_BOARD 2570 || (dev->device == PLX9056_DEVICE_ID && baroff == 2) 2571 #endif /* DNX_TEST_BOARD */ 2572 ) { 2573 paddr = pci_resource_start(dev, 0); 2574 bar_len = pci_resource_len(dev, 0); 2575 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(paddr, bar_len); 2576 ctrl->phys_address1 = paddr; 2577 if (debug >= 3) { 2578 gprintk("BAR 0: kernel addr:0x%lx phys addr:0x%lx length:%lx\n", 2579 (unsigned long)ctrl->bde_dev.base_address1, (unsigned long)paddr, (unsigned long)bar_len); 2580 } 2581 } 2582 2583 /* configure interrupt type */ 2584 config_pci_intr_type(dev, ctrl, iproc); 2585 2586 /* Configure iProc PCI-AXI bridge */ 2587 if (iproc && ctrl->bde_dev.base_address1) { 2588 void *iproc_regs; 2589 shbde_iproc_config_t *icfg = &shbde->icfg; 2590 2591 /* Mapped iProc regs in PCI BAR 0 */ 2592 iproc_regs = (void *)ctrl->bde_dev.base_address1; 2593 2594 /* iProc configuration parameters */ 2595 (void)shbde_pci_iproc_version_get(shbde, dev, &icfg->iproc_ver, 2596 &icfg->cmic_ver, &icfg->cmic_rev); 2597 shbde_iproc_config_init(icfg, ctrl->bde_dev.device, ctrl->bde_dev.rev); 2598 2599 if (debug >= 2) { 2600 gprintk("iproc version = %x dma_hi_bits = %x\n", icfg->iproc_ver, icfg->dma_hi_bits); 2601 } 2602 icfg->use_msi = ctrl->use_msi; 2603 2604 /* Call shared function */ 2605 paxb_core = shbde_iproc_paxb_init(shbde, iproc_regs, icfg); 2606 2607 /* Save PCI core information for CMIC */ 2608 if (paxb_core == 1) { 2609 ctrl->dev_type |= BDE_DEV_BUS_ALT; 2610 } 2611 2612 /* Save MSI enable state information */ 2613 if (ctrl->use_msi) { 2614 ctrl->dev_type |= BDE_DEV_BUS_MSI; 2615 } 2616 2617 /* iProc PCIe preemphasis */ 2618 shbde_iproc_pcie_preemphasis_set(shbde, iproc_regs, icfg, dev); 2619 } 2620 2621 /* Save shared BDE HAL in device structure */ 2622 MEMCPY(&ctrl->shbde, shbde, sizeof(ctrl->shbde)); 2623 2624 2625 ctrl->isr = NULL; 2626 ctrl->isr_data = NULL; 2627 2628 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2629 if (!(cmd & PCI_COMMAND_MEMORY) || !(cmd & PCI_COMMAND_MASTER)) { 2630 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 2631 pci_write_config_word(dev, PCI_COMMAND, cmd); 2632 if (debug >= 1) gprintk("enable PCI resources 0x%x (PCI_COMMAND)\n", cmd); 2633 } 2634 2635 /* Check if we need 256 KB memory window (default is 64 KB) */ 2636 bar_len = pci_resource_len(dev, baroff); 2637 if (bar_len == 0x40000) { 2638 ctrl->dev_type |= BDE_256K_REG_SPACE; 2639 if (debug >= 1) gprintk("PCI resource len 256K\n"); 2640 } else if (bar_len == 0x800000) { 2641 ctrl->dev_type |= BDE_256K_REG_SPACE | BDE_8MB_REG_SPACE; 2642 if (debug >= 1) gprintk("PCI resource len 8MB\n"); 2643 } 2644 2645 2646 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 2647 ctrl->dma_dev = &dev->dev; 2648 #endif 2649 2650 if (debug >= 2) { 2651 gprintk("_pci_probe: configured dev:0x%x rev:0x%x with base_addresses: 0x%lx 0x%lx\n", 2652 (unsigned)ctrl->bde_dev.device, (unsigned)ctrl->bde_dev.rev, 2653 (unsigned long)ctrl->bde_dev.base_address, (unsigned long)ctrl->bde_dev.base_address1); 2654 } 2655 2656 if (add_dev) { 2657 _bde_add_device(); 2658 } 2659 /* Let's boogie */ 2660 return 0; 2661 } 2662 2663 /* 2664 * Function: _pci_remove 2665 * 2666 * Purpose: 2667 * Detach driver from device. Called from pci_unregister_driver(). 2668 * Parameters: 2669 * dev - Linux PCI device structure 2670 * Returns: 2671 * 0 2672 */ 2673 static void 2674 _pci_remove(struct pci_dev* dev) 2675 { 2676 bde_ctrl_t *ctrl; 2677 2678 if (nodevices == 1) { 2679 return; 2680 } 2681 2682 #if defined(BCM_DFE_SUPPORT) 2683 if (dev->device == PCI_DEVICE_ID_PLX_9056) { 2684 return; 2685 } 2686 #endif 2687 2688 ctrl = (bde_ctrl_t *) pci_get_drvdata(dev); 2689 2690 if (ctrl == NULL) { 2691 /* Unused device */ 2692 return; 2693 } 2694 ctrl->dev_state = BDE_DEV_STATE_REMOVED; 2695 if (debug >= 1) { 2696 gprintk("PCI device %04x:%04x is removed. \n", 2697 dev->vendor, dev->device); 2698 } 2699 if (ctrl->bde_dev.base_address1) { 2700 iounmap((void *)ctrl->bde_dev.base_address1); 2701 } 2702 if (ctrl->bde_dev.base_address) { 2703 iounmap((void *)ctrl->bde_dev.base_address); 2704 } 2705 2706 /* Free our interrupt handler, if we have one */ 2707 if (ctrl->isr || ctrl->isr2) { 2708 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2709 if (ctrl->use_msi >= PCI_USE_INT_MSIX) { 2710 int i; 2711 for (i = 0; i < ctrl->msix_cnt; i++) 2712 free_irq(ctrl->entries[i].vector, ctrl); 2713 } 2714 else 2715 #endif 2716 { 2717 free_irq(ctrl->iLine, ctrl); 2718 } 2719 } 2720 #ifdef CONFIG_PCI_MSI 2721 _msi_disconnect(ctrl); 2722 #endif 2723 ctrl->isr = NULL; 2724 ctrl->isr_data = NULL; 2725 ctrl->isr2 = NULL; 2726 ctrl->isr2_data = NULL; 2727 } 2728 2729 static struct pci_driver _device_driver = { 2730 probe: _pci_probe, 2731 remove: _pci_remove, 2732 id_table: _id_table, 2733 /* The rest are dynamic */ 2734 }; 2735 2736 static void 2737 _spi_device_setup(void) { 2738 bde_ctrl_t *ctrl; 2739 ctrl = _devices + _ndevices; 2740 ctrl->dev_type |= BDE_SWITCH_DEV_TYPE; 2741 ctrl->iLine = 0xa3; 2742 ctrl->be_pio = 0; 2743 ctrl->dev_type |= BDE_SPI_DEV_TYPE; 2744 ctrl->bde_dev.device = spi_devid; 2745 ctrl->bde_dev.rev = spi_revid; 2746 if (debug >= 1) { 2747 gprintk("SPI Slave Mode: force ctrl->bde_dev.device=0x%x\n",ctrl->bde_dev.device); 2748 gprintk("SPI Slave Mode: force ctrl->bde_dev.rev=0x%x\n",ctrl->bde_dev.rev); 2749 gprintk("SPI Slave Mode: force ctrl->dev_type=0x%x\n",ctrl->dev_type); 2750 } 2751 _bde_add_device(); 2752 } 2753 #endif /* BCM_ICS */ 2754 2755 2756 2757 2758 #if defined(BCM_METROCORE_LOCAL_BUS) 2759 static bde_ctrl_t* 2760 map_local_bus(uint64_t addr, uint32_t size) 2761 { 2762 bde_ctrl_t *ctrl; 2763 2764 ctrl = _devices + _ndevices; 2765 2766 /* 2767 * For now: use EB type as `local bus' 2768 * (memory mapped, no DMA, no interrupts) 2769 * metrocore local bus supports interrupts, but we don't use them. 2770 */ 2771 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE 2772 | (size > 64 * 1024 ? BDE_128K_REG_SPACE : 0); 2773 ctrl->pci_device = NULL; /* No PCI bus */ 2774 2775 /* Map in the device */ 2776 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(addr, size); 2777 ctrl->phys_address = addr; 2778 2779 _bde_add_device(); 2780 return(ctrl); 2781 } 2782 2783 #define BME_REVISION_OFFSET (0x0) 2784 2785 #endif 2786 2787 #ifdef BCM_PLX9656_LOCAL_BUS 2788 2789 #if 1 2790 #define DEV_REG_BASE_OFFSET PL0_OFFSET /* Polaris register base */ 2791 #define DEV_REG_DEVID 0 /* Device ID is first register */ 2792 #endif 2793 2794 /* 2795 * The difference at map_local_bus2: 2796 * 2797 * The PLX9656 PCI-to-LOCAL bridge chip already has been iomapped the 2798 * whole address space. So the devices off local bus don't need to be 2799 * mapped again. They only need to claim their own sub-space. 2800 */ 2801 static bde_ctrl_t * 2802 map_local_bus2(bde_ctrl_t *plx_ctrl, uint32_t dev_base, uint32_t size) 2803 { 2804 uint32_t dev_rev_id; 2805 uint8_t *addr; 2806 bde_ctrl_t *ctrl; 2807 2808 ctrl = _devices + _ndevices; 2809 2810 /* 2811 * For now: use EB type as `local bus' 2812 * (memory mapped, no DMA, no interrupts) 2813 * metrocore local bus supports interrupts, but we don't use them. 2814 */ 2815 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 2816 ctrl->dev_type |= BDE_320K_REG_SPACE; /* Polaris 18 bits address + FPGA */ 2817 ctrl->pci_device = NULL; /* No PCI bus */ 2818 2819 /* Map in the device */ 2820 ctrl->bde_dev.base_address = plx_ctrl->bde_dev.base_address + dev_base; 2821 ctrl->phys_address = plx_ctrl->phys_address + (resource_size_t)dev_base; 2822 2823 #if 1 2824 addr = (uint8_t *)ctrl->bde_dev.base_address + PL0_REVISION_REG; 2825 #endif 2826 dev_rev_id = readl(addr); 2827 ctrl->bde_dev.device = dev_rev_id >> 16; 2828 ctrl->bde_dev.rev = (dev_rev_id & 0xFF); 2829 2830 2831 _bde_add_device(); 2832 2833 switch (ctrl->bde_dev.device) { 2834 default: 2835 return 0; 2836 } 2837 return(ctrl); 2838 } 2839 2840 static int 2841 probe_plx_local_bus(void) 2842 { 2843 bde_ctrl_t *ctrl; 2844 uint32_t val; 2845 uint8_t *addr; 2846 char addr_hi_str[16]; 2847 2848 if (num_plx > 1) { 2849 printk(KERN_ERR "There's more than one PLX 9656/9056 chip\n"); 2850 return -1; 2851 } 2852 addr_hi_str[0] = 0; 2853 #ifdef PHYS_ADDR_IS_64BIT 2854 sprintf(addr_hi_str, "%08x", (uint32_t)(plx_ctrl.phys_address >> 32)); 2855 #endif 2856 printk(KERN_ERR "Found PLX %04x:%04x vir: 0x%08x phy: 0x%s%08x\n", 2857 plx_ctrl.bde_dev.device, plx_ctrl.bde_dev.rev, 2858 plx_ctrl.bde_dev.base_address, addr_hi_str, 2859 (uint32_t)(plx_ctrl.phys_address)); 2860 2861 addr = (uint8_t *)plx_ctrl.bde_dev.base_address + CPLD_OFFSET + CPLD_REVISION_REG; 2862 val = readl(addr); 2863 printk(KERN_ERR "plx: CPLD revision %d\n", val & CPLD_REVISION_MASK); 2864 #if 000 2865 addr = (uint8_t *)plx_ctrl.bde_dev.base_address + CPLD_OFFSET + CPLD_RESET_REG; 2866 writel(CPLD_RESET_NONE, addr); 2867 #endif 2868 #if 1 2869 ctrl = map_local_bus2(&plx_ctrl, PL0_OFFSET, PL0_SIZE); 2870 #endif 2871 if (ctrl == 0) 2872 return -1; 2873 2874 /* Uses PLX IRQ for Polaris LC */ 2875 ctrl->iLine = 48; 2876 ctrl->isr = NULL; 2877 ctrl->isr_data = NULL; 2878 2879 return 0; 2880 } 2881 2882 #endif /* BCM_PLX9656_LOCAL_BUS */ 2883 2884 2885 2886 2887 /* 2888 * Generic module functions 2889 */ 2890 2891 /* 2892 * Function: _init 2893 * 2894 * Purpose: 2895 * Module initialization. 2896 * Attaches to kernel BDE. 2897 * Parameters: 2898 * None 2899 * Returns: 2900 * 0 on success, < 0 on error. 2901 */ 2902 static int 2903 _init(void) 2904 { 2905 #ifdef IPROC_CMICD 2906 #ifdef CONFIG_OF 2907 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 2908 iproc_platform_driver_register(&iproc_cmicd_driver); 2909 } else 2910 #endif 2911 if (iproc_has_cmicd()) { 2912 iproc_cmicd_get_memregion(&iproc_cmicd_resources[IPROC_CMICD_RES_MEM]); 2913 iproc_platform_driver_register(&iproc_cmicd_driver); 2914 #ifdef CONFIG_OF 2915 if (!of_find_compatible_node(NULL, NULL, IPROC_CMICD_COMPATIBLE)) 2916 #endif 2917 { 2918 /* Register platform device if no device node in dtb */ 2919 iproc_platform_device_register(&iproc_cmicd_pdev); 2920 } 2921 } 2922 #endif /* IPROC_CMICD */ 2923 2924 #ifdef BCM_ICS 2925 _ics_bde_create(); 2926 #else /* PCI */ 2927 /* Register our goodies */ 2928 _device_driver.name = LINUX_KERNEL_BDE_NAME; 2929 2930 2931 /* Configure MSI interrupt support */ 2932 use_msi = usemsi; 2933 2934 #ifdef CONFIG_PCI_MSI 2935 if (use_msi == PCI_USE_INT_NONE) { 2936 /* Compilation flag determines default value */ 2937 #ifdef BDE_LINUX_USE_MSIX_INTERRUPT 2938 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2939 use_msi = PCI_USE_INT_MSIX; 2940 #else 2941 use_msi = PCI_USE_INT_MSI; 2942 #endif 2943 #elif defined(BDE_LINUX_USE_MSI_INTERRUPT) 2944 use_msi = PCI_USE_INT_MSI; 2945 #else 2946 use_msi = PCI_USE_INT_INTX; 2947 #endif 2948 } 2949 #else 2950 if (use_msi > PCI_USE_INT_INTX) { 2951 /* Warn if invalid configuration */ 2952 gprintk("MSI interrupts not supported by kernel\n"); 2953 } 2954 use_msi = PCI_USE_INT_INTX; 2955 #endif /* CONFIG_PCI_MSI */ 2956 2957 if (unlikely(debug >= 1)) 2958 gprintk("%s(%d):use_msi = %d\n", __func__, __LINE__, use_msi); 2959 if (spi_devid) { 2960 _spi_device_setup(); 2961 } else { 2962 if (pci_register_driver(&_device_driver) < 0) { 2963 return -ENODEV; 2964 } 2965 } 2966 2967 /* Note: PCI-PCI bridge uses results from pci_register_driver */ 2968 p2p_bridge(); 2969 2970 #ifdef BCM_METROCORE_LOCAL_BUS 2971 if (probe_metrocore_local_bus()) { 2972 return -1; 2973 } 2974 #endif 2975 #ifdef BCM_PLX9656_LOCAL_BUS 2976 if (num_plx > 0) { 2977 probe_plx_local_bus(); 2978 } 2979 #endif 2980 #endif /* BCM_ICS */ 2981 2982 2983 #ifdef BCM_SAND_SUPPORT 2984 sand_device_create(); 2985 #endif 2986 2987 /* 2988 * Probe for EB Bus devices. 2989 */ 2990 if (eb_bus) { 2991 char *tok; 2992 uint irq = -1, eb_rd16bit=0, eb_wr16bit =0; 2993 unsigned int eb_ba = 0x0; 2994 2995 gprintk("EB bus info: %s\n", eb_bus); 2996 tok = strtok(eb_bus,","); 2997 while (tok) { 2998 _parse_eb_args(tok, "BA=%x IRQ=%d RD16=%d WR16=%d", 2999 &eb_ba, &irq, &eb_rd16bit, &eb_wr16bit); 3000 _eb_device_create(eb_ba, irq, eb_rd16bit, eb_wr16bit); 3001 tok = strtok(NULL,","); 3002 } 3003 } 3004 3005 return 0; 3006 } 3007 3008 /* 3009 * Function: _cleanup 3010 * 3011 * Purpose: 3012 * Module cleanup function. 3013 * Parameters: 3014 * None 3015 * Returns: 3016 * Always 0 3017 */ 3018 static int 3019 _cleanup(void) 3020 { 3021 int i; 3022 3023 _dma_cleanup(); 3024 3025 #ifdef IPROC_CMICD 3026 #ifdef CONFIG_OF 3027 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3028 iproc_platform_driver_unregister(&iproc_cmicd_driver); 3029 } else 3030 #endif 3031 if (iproc_has_cmicd()) { 3032 #ifdef CONFIG_OF 3033 if (!of_find_compatible_node(NULL, NULL, IPROC_CMICD_COMPATIBLE)) 3034 #endif 3035 { 3036 iproc_platform_device_unregister(&iproc_cmicd_pdev); 3037 } 3038 iproc_platform_driver_unregister(&iproc_cmicd_driver); 3039 } 3040 #endif 3041 3042 for (i = 0; i < _ndevices; i++) { 3043 bde_ctrl_t *ctrl = _devices + i; 3044 3045 /* free allocated kernel space memory */ 3046 if (ctrl->dev_type & BDE_SPI_DEV_TYPE) { 3047 if (ctrl->spi_device) { 3048 kfree(ctrl->spi_device); 3049 } 3050 } 3051 } 3052 #if defined(BCM_SAND_SUPPORT) && (defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__)) 3053 if (cpu_address) { /* unmap CPU card MMIO */ 3054 iounmap(cpu_address); 3055 cpu_address = NULL; 3056 } 3057 #endif 3058 3059 #ifdef BCM_ICS 3060 #else 3061 pci_unregister_driver(&_device_driver); 3062 #endif /* BCM_ICS */ 3063 return 0; 3064 } 3065 3066 /* 3067 * Function: _pprint 3068 * 3069 * Purpose: 3070 * Print proc filesystem information. 3071 * Parameters: 3072 * None 3073 * Returns: 3074 * Always 0 3075 */ 3076 static int 3077 _pprint(void) 3078 { 3079 int i = 0; 3080 3081 pprintf("Broadcom Device Enumerator (%s)\n", LINUX_KERNEL_BDE_NAME); 3082 3083 _dma_pprint(); 3084 3085 if (_ndevices == 0) { 3086 pprintf("No devices found\n"); 3087 } else { 3088 pprintf("Devices:\n"); 3089 } 3090 for (i = 0; i < _ndevices; i++) { 3091 bde_ctrl_t *ctrl = _devices + i; 3092 3093 if (ctrl->dev_type & BDE_SWITCH_DEV_TYPE) { 3094 pprintf("\t%d (swi) : ", i); 3095 } else if (ctrl->dev_type & BDE_ETHER_DEV_TYPE) { 3096 pprintf("\t%d (eth) : ", i); 3097 } else if (ctrl->dev_type & BDE_CPU_DEV_TYPE) { 3098 pprintf("\t%d (cpu) : ", i); 3099 } else { 3100 pprintf("\t%d (?) : ", i); 3101 } 3102 3103 if (ctrl->dev_state == BDE_DEV_STATE_REMOVED) { 3104 pprintf("PCI device 0x%x:0x%x:%d REMOVED\n", 3105 ctrl->pci_device->vendor, 3106 ctrl->pci_device->device, 3107 ctrl->bde_dev.rev); 3108 continue; 3109 } 3110 if (ctrl->dev_type & BDE_PCI_DEV_TYPE) { 3111 pprintf("PCI device %02x:%02x.%x 0x%x:0x%x:%d:0x%.8lx:0x%.8lx:%d%s\n", 3112 (unsigned int)ctrl->pci_device->bus->number, 3113 PCI_SLOT(ctrl->pci_device->devfn), 3114 PCI_FUNC(ctrl->pci_device->devfn), 3115 ctrl->pci_device->vendor, 3116 ctrl->pci_device->device, 3117 ctrl->bde_dev.rev, 3118 (unsigned long)pci_resource_start(ctrl->pci_device, 0), 3119 (unsigned long)pci_resource_start(ctrl->pci_device, 2), 3120 ctrl->pci_device->irq, 3121 ctrl->use_msi ? " (MSI)" : ""); 3122 } else if (ctrl->dev_type & BDE_SPI_DEV_TYPE) { 3123 pprintf("SPI Device %d:%x:%x:0x%x:0x%x:%d\n", 3124 ctrl->spi_device->cid, 3125 ctrl->spi_device->part, 3126 ctrl->spi_device->rev, 3127 ctrl->spi_device->phyid_high, 3128 ctrl->spi_device->phyid_low, 3129 ctrl->bde_dev.rev); 3130 } else if (ctrl->dev_type & BDE_ICS_DEV_TYPE) { 3131 pprintf("ICS Device 0x%x:0x%x\n", 3132 ctrl->bde_dev.device, 3133 ctrl->bde_dev.rev); 3134 } else if (ctrl->dev_type & BDE_AXI_DEV_TYPE) { 3135 pprintf("AXI Device 0x%x:0x%x:0x%.8lx:%d\n", 3136 ctrl->bde_dev.device, 3137 ctrl->bde_dev.rev, 3138 (unsigned long)ctrl->phys_address, 3139 ctrl->iLine); 3140 } else if (ctrl->dev_type & BDE_EB_DEV_TYPE) { 3141 pprintf("EB Bus Device 0x%x:0x%x\n", 3142 ctrl->bde_dev.device, 3143 ctrl->bde_dev.rev); 3144 } 3145 if (debug >= 1) { 3146 pprintf("\t\timask:imask2:fmask 0x%x:0x%x:0x%x\n", 3147 ctrl->imask, 3148 ctrl->imask2, 3149 ctrl->fmask); 3150 } 3151 } 3152 return 0; 3153 } 3154 3155 /* Workaround for broken Busybox/PPC insmod */ 3156 static char _modname[] = LINUX_KERNEL_BDE_NAME; 3157 3158 static gmodule_t _gmodule = { 3159 name: LINUX_KERNEL_BDE_NAME, 3160 major: LINUX_KERNEL_BDE_MAJOR, 3161 init: _init, 3162 cleanup: _cleanup, 3163 pprint: _pprint, 3164 mmap: _dma_mmap, 3165 }; 3166 3167 gmodule_t * 3168 gmodule_get(void) 3169 { 3170 _gmodule.name = _modname; 3171 return &_gmodule; 3172 } 3173 3174 3175 /* 3176 * BDE Interface 3177 */ 3178 3179 static const char * 3180 _name(void) 3181 { 3182 return LINUX_KERNEL_BDE_NAME; 3183 } 3184 3185 static int 3186 _num_devices(int type) 3187 { 3188 switch (type) { 3189 case BDE_ALL_DEVICES: 3190 return _ndevices; 3191 case BDE_SWITCH_DEVICES: 3192 return _switch_ndevices; 3193 case BDE_ETHER_DEVICES: 3194 return _ether_ndevices; 3195 case BDE_CPU_DEVICES: 3196 return _cpu_ndevices; 3197 } 3198 3199 return 0; 3200 } 3201 3202 static const ibde_dev_t * 3203 _get_dev(int d) 3204 { 3205 if (!VALID_DEVICE(d)) { 3206 gprintk("_get_dev: Invalid device index %d\n", d); 3207 return NULL; 3208 } 3209 3210 return &_devices[d].bde_dev; 3211 } 3212 3213 static uint32 3214 _get_dev_type(int d) 3215 { 3216 if (!VALID_DEVICE(d)) { 3217 gprintk("_get_dev: Invalid device index %d\n", d); 3218 return 0; 3219 } 3220 3221 return _devices[d].dev_type; 3222 } 3223 3224 static uint32 3225 _pci_conf_read(int d, uint32 addr) 3226 { 3227 #ifdef BCM_ICS 3228 return 0xFFFFFFFF; 3229 #else 3230 uint32 rc = 0; 3231 3232 if (!VALID_DEVICE(d)) { 3233 gprintk("_pci_conf_read: Invalid device index %d\n", d); 3234 return 0xFFFFFFFF; 3235 } 3236 3237 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3238 gprintk("_pci_conf_read: Not PCI device %d, type %x\n", 3239 d, _devices[d].dev_type); 3240 return 0xFFFFFFFF; 3241 } 3242 3243 pci_read_config_dword(_devices[d].pci_device, addr, &rc); 3244 return rc; 3245 #endif /* BCM_ICS */ 3246 } 3247 3248 static int 3249 _pci_conf_write(int d, uint32 addr, uint32 data) 3250 { 3251 #ifdef BCM_ICS 3252 return -1; 3253 #else 3254 if (!VALID_DEVICE(d)) { 3255 gprintk("_pci_conf_write: Invalid device index %d\n", d); 3256 return -1; 3257 } 3258 3259 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3260 gprintk("_pci_conf_write: Not PCI device %d, type %x\n", 3261 d, _devices[d].dev_type); 3262 return -1; 3263 } 3264 3265 pci_write_config_dword(_devices[d].pci_device, addr, data); 3266 return 0; 3267 #endif /* BCM_ICS */ 3268 } 3269 3270 /* Initialized when the bde is created */ 3271 static linux_bde_bus_t _bus; 3272 3273 static void 3274 _pci_bus_features(int unit, int *be_pio, int *be_packet, int *be_other) 3275 { 3276 if ((_devices[unit].bde_dev.device & 0xFF00) != 0x5600 && 3277 (_devices[unit].bde_dev.device & 0xF000) != 0xc000 && 3278 (_devices[unit].bde_dev.device & 0xF000) != 0xb000 && 3279 (_devices[unit].bde_dev.device & 0xF000) != 0x8000 && 3280 (_devices[unit].bde_dev.device & 0xFFF0) != 0x0230 && 3281 (_devices[unit].bde_dev.device & 0xFFF0) != 0xa440) { 3282 if (be_pio) *be_pio = 0; 3283 if (be_packet) *be_packet = 0; 3284 if (be_other) *be_other = 0; 3285 } else { 3286 if (be_pio) *be_pio = _bus.be_pio; 3287 if (be_packet) *be_packet = _bus.be_packet; 3288 if (be_other) *be_other = _bus.be_other; 3289 } 3290 #if defined(BCM_METROCORE_LOCAL_BUS) 3291 if (_devices[unit].dev_type & BDE_EB_DEV_TYPE && be_pio) { 3292 *be_pio = 1; 3293 } 3294 #endif 3295 3296 } 3297 3298 static uint32_t 3299 _read(int d, uint32_t addr) 3300 { 3301 unsigned long flags; 3302 volatile uint16 msb, lsb; 3303 uint32 sl_addr, data; 3304 3305 if (!VALID_DEVICE(d)) { 3306 return -1; 3307 } 3308 3309 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3310 return -1; 3311 } 3312 3313 if (_devices[d].dev_type & BDE_DEV_BUS_RD_16BIT) { 3314 /* 3315 * Adjust the address presented to Eb slave. Move A15:A0 to A16:A1. 3316 */ 3317 sl_addr = (addr & 0xffff0000) | ((addr & 0xffff) << 1); 3318 /* Disable interrupts */ 3319 spin_lock_irqsave(&bus_lock, flags); 3320 3321 lsb = *((uint16 *)(_devices[d].bde_dev.base_address + sl_addr)); 3322 msb = *((uint16 *)(_devices[d].bde_dev.base_address + sl_addr)); 3323 spin_unlock_irqrestore(&bus_lock, flags); 3324 3325 return (msb << 16) | lsb; 3326 } else { 3327 data = ((VOL uint32_t *)_devices[d].bde_dev.base_address)[addr / 4]; 3328 #if defined(CMIC_SOFT_BYTE_SWAP) 3329 data = CMIC_SWAP32(data); 3330 #endif 3331 return data; 3332 } 3333 } 3334 3335 static int 3336 _write(int d, uint32_t addr, uint32_t data) 3337 { 3338 unsigned long flags; 3339 uint32 sl_addr; 3340 3341 if (!VALID_DEVICE(d)) { 3342 return -1; 3343 } 3344 3345 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3346 return -1; 3347 } 3348 3349 if (_devices[d].dev_type & BDE_DEV_BUS_WR_16BIT) { 3350 /* 3351 * Adjust the address presented to Eb slave. Move A15:A0 to A16:A1. 3352 */ 3353 sl_addr = (addr & 0xffff0000) | ((addr & 0xffff) << 1); 3354 3355 /* Disable interrupts */ 3356 spin_lock_irqsave(&bus_lock, flags); 3357 3358 *((VOL uint16 *)(_devices[d].bde_dev.base_address + sl_addr)) = 3359 data & 0xffff; 3360 *((VOL uint16 *)(_devices[d].bde_dev.base_address + sl_addr)) = 3361 (data >> 16) & 0xffff; 3362 spin_unlock_irqrestore(&bus_lock, flags); 3363 } else { 3364 #if defined(CMIC_SOFT_BYTE_SWAP) 3365 data = CMIC_SWAP32(data); 3366 #endif 3367 ((VOL uint32_t *)_devices[d].bde_dev.base_address)[addr / 4] = data; 3368 #ifdef KEYSTONE 3369 /* Enforce PCIe transaction ordering. Commit the write transaction */ 3370 __asm__ __volatile__("sync"); 3371 #endif 3372 } 3373 return 0; 3374 3375 } 3376 3377 static _ISR_RET 3378 _isr(_ISR_PARAMS(irq, dev_id, iregs)) 3379 { 3380 bde_ctrl_t *ctrl = (bde_ctrl_t *) dev_id; 3381 3382 if (ctrl && ctrl->isr) { 3383 ctrl->isr(ctrl->isr_data); 3384 } 3385 if (ctrl && ctrl->isr2) { 3386 ctrl->isr2(ctrl->isr2_data); 3387 } 3388 return IRQ_HANDLED; 3389 } 3390 3391 static int 3392 _interrupt_connect(int d, 3393 void (*isr)(void *), 3394 void *isr_data) 3395 { 3396 bde_ctrl_t *ctrl; 3397 unsigned long irq_flags; 3398 int isr2_dev; 3399 int isr_active; 3400 int ret = 0; 3401 3402 isr2_dev = d & LKBDE_ISR2_DEV; 3403 d &= ~LKBDE_ISR2_DEV; 3404 3405 if (!VALID_DEVICE(d)) { 3406 gprintk("_interrupt_connect: Invalid device index %d\n", d); 3407 return -1; 3408 } 3409 if (debug >= 1) { 3410 gprintk("_interrupt_connect d %d\n", d); 3411 } 3412 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3413 gprintk("_interrupt_connect: Not PCI device %d, type %x\n", 3414 d, _devices[d].dev_type); 3415 return -1; 3416 } 3417 3418 ctrl = _devices + d; 3419 3420 isr_active = (ctrl->isr || ctrl->isr2) ? 1 : 0; 3421 3422 if (unlikely(debug > 1)) 3423 gprintk("%s:isr_active = %d\n", __func__, isr_active); 3424 3425 if (isr2_dev) { 3426 if (debug >= 1) { 3427 gprintk("connect secondary isr\n"); 3428 } 3429 ctrl->isr2_data = isr_data; 3430 ctrl->isr2 = isr; 3431 if (isr_active) { 3432 /* Main handler (_isr) already installed */ 3433 return 0; 3434 } 3435 } else { 3436 if (debug >= 1) { 3437 gprintk("connect primary isr\n"); 3438 } 3439 ctrl->isr = isr; 3440 ctrl->isr_data = isr_data; 3441 if (isr_active) { 3442 /* Main handler (_isr) already installed */ 3443 return 0; 3444 } 3445 } 3446 3447 if (ctrl->iLine != -1) { 3448 irq_flags = IRQF_SHARED; 3449 #ifdef CONFIG_PCI_MSI 3450 if (ctrl->use_msi >= PCI_USE_INT_MSI) { 3451 ret = _msi_connect(ctrl); 3452 if(ret != 0) 3453 goto msi_exit; 3454 } 3455 #endif 3456 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 3457 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 3458 int i; 3459 for (i = 0; i < ctrl->msix_cnt; i++) { 3460 if (unlikely(debug >= 1)) { 3461 gprintk("%s(%d):device# = %d, irq = %d\n", 3462 __func__, __LINE__, d, ctrl->entries[i].vector); 3463 } 3464 ret = request_irq(ctrl->entries[i].vector, (irq_handler_t)_isr, 0, 3465 LINUX_KERNEL_BDE_NAME, ctrl); 3466 if (ret < 0) 3467 break; 3468 } 3469 if (ret < 0) { 3470 while (i >= 0) 3471 free_irq(ctrl->entries[i--].vector, ctrl); 3472 3473 goto err_disable_msi; 3474 } 3475 } 3476 else 3477 #endif 3478 { 3479 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 3480 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3481 int i, j; 3482 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 3483 if (unlikely(debug >= 1)) 3484 gprintk("%s(%d):device# = %d, request_irq(%d)\n", 3485 __func__, __LINE__, d, iproc_cmicx_irqs[i]); 3486 ret = request_irq(iproc_cmicx_irqs[i], (irq_handler_t)_isr, 3487 irq_flags, LINUX_KERNEL_BDE_NAME, ctrl); 3488 if (ret < 0) { 3489 gprintk("request_irq(%d) failed(%d)\n", iproc_cmicx_irqs[i], ret); 3490 break; 3491 } 3492 } 3493 if (ret < 0) { 3494 for (j = 0; j < i; j++) { 3495 free_irq(iproc_cmicx_irqs[j], ctrl); 3496 } 3497 goto err_disable_msi; 3498 } 3499 } else 3500 #endif 3501 { 3502 ret = request_irq(ctrl->iLine, _isr, irq_flags, 3503 LINUX_KERNEL_BDE_NAME, ctrl); 3504 if (ret < 0) 3505 goto err_disable_msi; 3506 3507 if (unlikely(debug >= 1)) 3508 gprintk("%s(%d):device# = %d, irq_flags = %lu, irq = %d\n", 3509 __func__, __LINE__, d, 3510 irq_flags, ctrl->pci_device ? ctrl->pci_device->irq : ctrl->iLine); 3511 } 3512 } 3513 } 3514 return 0; 3515 3516 err_disable_msi: 3517 #ifdef CONFIG_PCI_MSI 3518 _msi_disconnect(ctrl); 3519 3520 msi_exit: 3521 #endif 3522 gprintk("could not request IRQ\n"); 3523 ctrl->isr = NULL; 3524 ctrl->isr_data = NULL; 3525 ctrl->isr2 = NULL; 3526 ctrl->isr2_data = NULL; 3527 3528 return -1; 3529 } 3530 3531 static int 3532 _interrupt_disconnect(int d) 3533 { 3534 bde_ctrl_t *ctrl; 3535 int isr2_dev; 3536 int isr_active; 3537 3538 isr2_dev = d & LKBDE_ISR2_DEV; 3539 d &= ~LKBDE_ISR2_DEV; 3540 3541 if (!VALID_DEVICE(d)) { 3542 return -1; 3543 } 3544 3545 if (debug >= 1) { 3546 gprintk("_interrupt_disconnect d %d\n", d); 3547 } 3548 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3549 gprintk("_interrupt_disconnect: Not PCI device %d, type %x\n", 3550 d, _devices[d].dev_type); 3551 return -1; 3552 } 3553 3554 ctrl = _devices + d; 3555 3556 isr_active = (ctrl->isr || ctrl->isr2) ? 1 : 0; 3557 3558 if (unlikely(debug > 1)) 3559 gprintk("%s: isr_active = %d\n", __func__, isr_active); 3560 3561 if (isr2_dev) { 3562 if (debug >= 1) { 3563 gprintk("disconnect secondary isr\n"); 3564 } 3565 ctrl->isr2 = NULL; 3566 ctrl->isr2_data = NULL; 3567 ctrl->fmask = 0; 3568 if (ctrl->isr) { 3569 /* Primary handler still active */ 3570 SYNC_IRQ(ctrl->iLine); 3571 return 0; 3572 } 3573 } else { 3574 if (debug >= 1) { 3575 gprintk("disconnect primary isr\n"); 3576 } 3577 ctrl->isr = NULL; 3578 ctrl->isr_data = NULL; 3579 if (ctrl->isr2) { 3580 /* Secondary handler still active */ 3581 SYNC_IRQ(ctrl->iLine); 3582 return 0; 3583 } 3584 } 3585 3586 if (isr_active) { 3587 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 3588 if (ctrl->use_msi >= PCI_USE_INT_MSIX) { 3589 int i; 3590 for (i = 0; i < ctrl->msix_cnt; i++) { 3591 if (unlikely(debug > 1)) { 3592 gprintk("%s(%d):device# = %d, irq = %d\n", 3593 __func__, __LINE__, d, ctrl->entries[i].vector); 3594 } 3595 free_irq(ctrl->entries[i].vector, ctrl); 3596 } 3597 } 3598 else 3599 #endif 3600 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 3601 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3602 int i; 3603 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 3604 if (unlikely(debug > 1)) { 3605 gprintk("%s(%d):device# = %d, free_irq(%d)\n", 3606 __func__, __LINE__, d, iproc_cmicx_irqs[i]); 3607 } 3608 free_irq(iproc_cmicx_irqs[i], ctrl); 3609 } 3610 } else 3611 #endif 3612 { 3613 free_irq(ctrl->iLine, ctrl); 3614 } 3615 #ifdef CONFIG_PCI_MSI 3616 if (ctrl->use_msi >= PCI_USE_INT_MSI) { 3617 _msi_disconnect(ctrl); 3618 } 3619 #endif 3620 } 3621 3622 return 0; 3623 } 3624 3625 static uint32_t 3626 _iproc_ihost_read(int d, uint32_t addr) 3627 { 3628 uint32_t *mapaddr; 3629 uint32_t reg_val; 3630 mapaddr = IOREMAP(addr, sizeof(uint32_t)); 3631 if (mapaddr == NULL) { 3632 return -1; 3633 } 3634 reg_val = readl(mapaddr); 3635 iounmap(mapaddr); 3636 return reg_val; 3637 } 3638 3639 static int 3640 _iproc_ihost_write(int d, uint32_t addr, uint32_t data) 3641 { 3642 uint32_t *mapaddr; 3643 mapaddr = IOREMAP(addr, sizeof(uint32_t)); 3644 if (mapaddr == NULL) { 3645 return -1; 3646 } 3647 writel(data, mapaddr); 3648 iounmap(mapaddr); 3649 return 0; 3650 } 3651 3652 static uint32_t 3653 _iproc_read(int d, uint32_t addr) 3654 { 3655 if (!VALID_DEVICE(d)) { 3656 return -1; 3657 } 3658 3659 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3660 return -1; 3661 } 3662 3663 if (_devices[d].dev_type & BDE_AXI_DEV_TYPE) { 3664 if (IHOST_GICD_REG_ADDR_VALID(d, addr)) { 3665 return readl(IHOST_GICD_REG_ADDR_REMAP(d, addr)); 3666 } 3667 return _iproc_ihost_read(d, addr); 3668 } 3669 3670 return shbde_iproc_pci_read(&_devices[d].shbde, 3671 (void *)_devices[d].bde_dev.base_address1, 3672 addr); 3673 } 3674 3675 static int 3676 _iproc_write(int d, uint32_t addr, uint32_t data) 3677 { 3678 if (!VALID_DEVICE(d)) { 3679 return -1; 3680 } 3681 3682 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3683 return -1; 3684 } 3685 3686 if (_devices[d].dev_type & BDE_AXI_DEV_TYPE) { 3687 if (IHOST_GICD_REG_ADDR_VALID(d, addr)) { 3688 writel(data, IHOST_GICD_REG_ADDR_REMAP(d, addr)); 3689 return 0; 3690 } 3691 return _iproc_ihost_write(d, addr, data); 3692 } 3693 3694 shbde_iproc_pci_write(&_devices[d].shbde, 3695 (void *)_devices[d].bde_dev.base_address1, 3696 addr, data); 3697 3698 return 0; 3699 } 3700 3701 static int 3702 _get_cmic_ver(int d , uint32_t *ver) 3703 { 3704 3705 unsigned int cap_base; 3706 uint32_t rval = 0; 3707 3708 if (!VALID_DEVICE(d)) { 3709 gprintk("%s: Invalid device index %d\n", __func__, d); 3710 return -1; 3711 } 3712 3713 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3714 gprintk("%s: Not PCI device %d, type %x\n", __func__, 3715 d, _devices[d].dev_type); 3716 return -1; 3717 } 3718 3719 /* Look for PCIe vendor-specific extended capability (VSEC) */ 3720 cap_base = PCI_EXT_CAP_START; 3721 while (cap_base) { 3722 pci_read_config_dword(_devices[d].pci_device, cap_base, &rval); 3723 if (rval == 0xffffffff) { 3724 /* Assume PCI HW read error */ 3725 gprintk("%s: PCI HW read error\n", __func__); 3726 return -1; 3727 } 3728 3729 if (PCI_EXT_CAP_ID(rval) == PCI_EXT_CAP_ID_VNDR) { 3730 break; 3731 } 3732 cap_base = PCI_EXT_CAP_NEXT(rval); 3733 } 3734 if (cap_base) { 3735 /* 3736 * VSEC layout: 3737 * 3738 * 0x00: PCI Express Extended Capability Header 3739 * 0x04: Vendor-Specific Header 3740 * 0x08: Vendor-Specific Register 1 3741 * 0x0c: Vendor-Specific Register 2 3742 * ... 3743 * 0x24: Vendor-Specific Register 8 3744 */ 3745 pci_read_config_dword(_devices[d].pci_device, cap_base + 8, &rval); 3746 if (unlikely(debug > 1)) 3747 gprintk("%s:Found VSEC = %u\n", __func__, rval); 3748 3749 /* Determine if CMICX */ 3750 rval = ((rval >> 12) & 0xf); 3751 *ver = rval; 3752 3753 return 0; 3754 } else { 3755 gprintk("%s:VSEC not found\n", __func__); 3756 } 3757 3758 return -1; 3759 } 3760 3761 #ifdef BCM_SAND_SUPPORT 3762 int 3763 lkbde_cpu_write(int d, uint32 addr, uint32 *buf) 3764 { 3765 #if defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__) 3766 *((uint32_t*)((uint8_t*)cpu_address + addr)) = *buf; 3767 #endif 3768 3769 return 0; 3770 } 3771 3772 int 3773 lkbde_cpu_read(int d, uint32 addr, uint32 *buf) 3774 { 3775 #if defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__) 3776 *buf = *((uint32_t*)((uint8_t*)cpu_address + addr)); 3777 #else 3778 *buf = (uint32_t)(-1); 3779 #endif 3780 3781 return 0; 3782 } 3783 3784 int 3785 lkbde_cpu_pci_register(int d) 3786 { 3787 bde_ctrl_t* ctrl; 3788 uint16 cmd = 0; 3789 3790 if (!VALID_DEVICE(d)) { 3791 return -1; 3792 } 3793 3794 ctrl = &_devices[d]; 3795 3796 /* enable device */ 3797 if (pci_enable_device(ctrl->pci_device)) { 3798 gprintk("Cannot enable pci device : vendor_id = %x, device_id = %x\n", 3799 ctrl->pci_device->vendor, ctrl->pci_device->device); 3800 } 3801 3802 /* Add PCI_COMMAND_MEMORY and PCI_COMMAND_MASTER */ 3803 pci_read_config_word(ctrl->pci_device, PCI_COMMAND, &cmd); 3804 if (!(cmd & PCI_COMMAND_MEMORY) || !(cmd & PCI_COMMAND_MASTER)) { 3805 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 3806 pci_write_config_word(ctrl->pci_device, PCI_COMMAND, cmd); 3807 } 3808 3809 switch (ctrl->bde_dev.device) { 3810 case GEDI_DEVICE_ID: 3811 /* Fix bar 0 address */ /* FIXME: write full phy address */ 3812 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 3813 3814 /* Fix Max payload size */ 3815 pci_write_config_byte(ctrl->pci_device, 0x88, 0x2f); 3816 pci_write_config_byte(ctrl->pci_device, 0x89, 0x10); 3817 break; 3818 case BCM88750_DEVICE_ID: 3819 case BCM88753_DEVICE_ID: 3820 case BCM88755_DEVICE_ID: 3821 case BCM88770_DEVICE_ID: 3822 case BCM88773_DEVICE_ID: 3823 case BCM88774_DEVICE_ID: 3824 case BCM88775_DEVICE_ID: 3825 case BCM88776_DEVICE_ID: 3826 case BCM88777_DEVICE_ID: 3827 case BCM88950_DEVICE_ID: 3828 case BCM88953_DEVICE_ID: 3829 case BCM88954_DEVICE_ID: 3830 case BCM88955_DEVICE_ID: 3831 case BCM88956_DEVICE_ID: 3832 case BCM88752_DEVICE_ID: 3833 case BCM88772_DEVICE_ID: 3834 case BCM88952_DEVICE_ID: 3835 case ACP_PCI_DEVICE_ID: 3836 case BCM88650_DEVICE_ID: 3837 3838 case BCM88670_DEVICE_ID: 3839 case BCM88671_DEVICE_ID: 3840 case BCM88671M_DEVICE_ID: 3841 case BCM88672_DEVICE_ID: 3842 case BCM88673_DEVICE_ID: 3843 case BCM88674_DEVICE_ID: 3844 case BCM88675_DEVICE_ID: 3845 case BCM88675M_DEVICE_ID: 3846 case BCM88676_DEVICE_ID: 3847 case BCM88676M_DEVICE_ID: 3848 case BCM88677_DEVICE_ID: 3849 case BCM88678_DEVICE_ID: 3850 case BCM88679_DEVICE_ID: 3851 3852 case BCM88370_DEVICE_ID: 3853 case BCM88371_DEVICE_ID: 3854 case BCM88371M_DEVICE_ID: 3855 case BCM88375_DEVICE_ID: 3856 case BCM88376_DEVICE_ID: 3857 case BCM88376M_DEVICE_ID: 3858 case BCM88377_DEVICE_ID: 3859 case BCM88378_DEVICE_ID: 3860 case BCM88379_DEVICE_ID: 3861 case BCM88681_DEVICE_ID: 3862 case BCM88682_DEVICE_ID: 3863 case BCM88683_DEVICE_ID: 3864 case BCM88684_DEVICE_ID: 3865 case BCM88685_DEVICE_ID: 3866 case BCM88380_DEVICE_ID: 3867 case BCM88381_DEVICE_ID: 3868 case BCM88680_DEVICE_ID: 3869 case BCM88800_DEVICE_ID: 3870 case BCM88470_DEVICE_ID: 3871 case BCM88470P_DEVICE_ID: 3872 case BCM88471_DEVICE_ID: 3873 case BCM88473_DEVICE_ID: 3874 case BCM88474_DEVICE_ID: 3875 case BCM88474H_DEVICE_ID: 3876 case BCM88476_DEVICE_ID: 3877 case BCM88477_DEVICE_ID: 3878 case BCM88270_DEVICE_ID: 3879 case BCM88272_DEVICE_ID: 3880 case BCM88273_DEVICE_ID: 3881 case BCM88274_DEVICE_ID: 3882 case BCM88278_DEVICE_ID: 3883 case BCM8206_DEVICE_ID: 3884 case BCM88350_DEVICE_ID: 3885 case BCM88351_DEVICE_ID: 3886 case BCM88450_DEVICE_ID: 3887 case BCM88451_DEVICE_ID: 3888 case BCM88550_DEVICE_ID: 3889 case BCM88551_DEVICE_ID: 3890 case BCM88552_DEVICE_ID: 3891 case BCM88651_DEVICE_ID: 3892 case BCM88654_DEVICE_ID: 3893 case BCM88660_DEVICE_ID: 3894 case BCM88360_DEVICE_ID: 3895 case BCM88361_DEVICE_ID: 3896 case BCM88363_DEVICE_ID: 3897 case BCM88460_DEVICE_ID: 3898 case BCM88461_DEVICE_ID: 3899 case BCM88560_DEVICE_ID: 3900 case BCM88561_DEVICE_ID: 3901 case BCM88562_DEVICE_ID: 3902 case BCM88661_DEVICE_ID: 3903 case BCM88664_DEVICE_ID: 3904 /* Fix bar 0 address */ /* FIXME: write full phy address */ 3905 pci_write_config_byte(ctrl->pci_device, 0x12, 0x10); 3906 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 3907 3908 /* 3909 * For DMA transactions - set Max_Payload_Size and 3910 * Max_Read_Request_Size to 128 bytes. 3911 */ 3912 pci_write_config_byte(ctrl->pci_device, 0xb5, 0x0c); 3913 pci_write_config_byte(ctrl->pci_device, 0xb4, 0x0); 3914 break; 3915 default: 3916 break; 3917 } 3918 3919 #ifdef BCM_DNX_SUPPORT 3920 /*All Jericho 2 devices from 0x8690 to 0x869F*/ 3921 if (SOC_IS_JERICHO_2_TYPE(ctrl->bde_dev.device)) { 3922 /* Fix bar 0 address */ /* FIXME: write full phy address */ 3923 pci_write_config_byte(ctrl->pci_device, 0x12, 0x10); 3924 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 3925 3926 /* 3927 * For DMA transactions - set Max_Payload_Size and 3928 * Max_Read_Request_Size to 128 bytes. 3929 */ 3930 pci_write_config_byte(ctrl->pci_device, 0xb5, 0x0c); 3931 pci_write_config_byte(ctrl->pci_device, 0xb4, 0x0); 3932 } 3933 #endif 3934 3935 /* Redo ioremap */ 3936 if (ctrl->bde_dev.base_address) { 3937 iounmap((void *)ctrl->bde_dev.base_address); 3938 } 3939 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(ctrl->phys_address, 0x1000000); 3940 3941 if (debug >= 1) { 3942 gprintk("%s, %s(): info:\n", __FILE__, __FUNCTION__); 3943 gprintk("_ndevices=%d, _switch_ndevices=%d\n", 3944 _ndevices, _switch_ndevices); 3945 gprintk("ctrl->dev_type=0x%x, ctrl->phys_address=0x%lx\n", 3946 ctrl->dev_type, (unsigned long)ctrl->phys_address); 3947 gprintk("ctrl->bde_dev.device=0x%x, ctrl->bde_dev.rev=0x%x, " 3948 "ctrl->bde_dev.base_address=0x%lx\n", 3949 ctrl->bde_dev.device, ctrl->bde_dev.rev, 3950 (unsigned long)ctrl->bde_dev.base_address); 3951 } 3952 3953 return 0; 3954 } 3955 3956 /* 3957 * Export Low level access function - currently for PCP DMA Kernel module. 3958 */ 3959 int 3960 lkbde_mem_write(int d, uint32 addr, uint32 *buf) 3961 { 3962 bde_ctrl_t* ctrl; 3963 void *full_addr; 3964 3965 if (!VALID_DEVICE(d)) return -1; 3966 ctrl = &_devices[d]; 3967 3968 full_addr = (void *)ctrl->bde_dev.base_address + addr; 3969 *((uint32_t*)full_addr) = *buf; 3970 return 0; 3971 } 3972 LKM_EXPORT_SYM(lkbde_mem_write); 3973 3974 int 3975 lkbde_mem_read(int d, uint32 addr, uint32 *buf) 3976 { 3977 bde_ctrl_t* ctrl; 3978 void *full_addr; 3979 3980 if (!VALID_DEVICE(d)) return -1; 3981 ctrl = &_devices[d]; 3982 3983 full_addr = (void *)ctrl->bde_dev.base_address + addr; 3984 *buf = *((uint32_t*)full_addr); 3985 return 0; 3986 } 3987 LKM_EXPORT_SYM(lkbde_mem_read); 3988 #endif /* BCM_SAND_SUPPORT */ 3989 3990 static ibde_t _ibde = { 3991 name: _name, 3992 num_devices: _num_devices, 3993 get_dev: _get_dev, 3994 get_dev_type: _get_dev_type, 3995 pci_conf_read: _pci_conf_read, 3996 pci_conf_write: _pci_conf_write, 3997 pci_bus_features: _pci_bus_features, 3998 read: _read, 3999 write: _write, 4000 salloc: _salloc, 4001 sfree: _sfree, 4002 sinval: _sinval, 4003 sflush: _sflush, 4004 interrupt_connect: _interrupt_connect, 4005 interrupt_disconnect: _interrupt_disconnect, 4006 l2p: _l2p, 4007 p2l: _p2l, 4008 4009 NULL, 4010 NULL, 4011 iproc_read: _iproc_read, 4012 iproc_write: _iproc_write, 4013 get_cmic_ver: _get_cmic_ver, 4014 }; 4015 4016 /* 4017 * Function: linux_bde_create 4018 * 4019 * Purpose: 4020 * Creator function for this BDE interface. 4021 * Parameters: 4022 * bus - pointer to the bus features structure you want this 4023 * bde to export. Depends on the system. 4024 * ibde - pointer to a location to recieve the bde interface pointer. 4025 * Returns: 4026 * 0 on success 4027 * -1 on failure. 4028 * Notes: 4029 * This is the main BDE create function for this interface. 4030 * Used by the external system initialization code. 4031 */ 4032 int 4033 linux_bde_create(linux_bde_bus_t *bus, ibde_t **ibde) 4034 { 4035 4036 memset(&_bus, 0, sizeof(_bus)); 4037 4038 if (bus) { 4039 _bus = *bus; 4040 } 4041 #ifdef NONCOHERENT_DMA_MEMORY 4042 #ifdef REMAP_DMA_NONCACHED 4043 /* 4044 * If we have a non-cached DMA memory pool 4045 * there is no need to flush and invalidate. 4046 */ 4047 if (_dma_pool_allocated()) { 4048 _ibde.sinval = NULL; 4049 _ibde.sflush = NULL; 4050 } 4051 #endif 4052 #else 4053 _ibde.sinval = NULL; 4054 _ibde.sflush = NULL; 4055 #endif 4056 *ibde = &_ibde; 4057 return 0; 4058 } 4059 4060 /* 4061 * Function: linux_bde_destroy 4062 * 4063 * Purpose: 4064 * destroy this bde 4065 * Parameters: 4066 * BDE interface pointer 4067 * Returns: 4068 * 0 on success, < 0 on error. 4069 */ 4070 int 4071 linux_bde_destroy(ibde_t *ibde) 4072 { 4073 /* nothing */ 4074 return 0; 4075 } 4076 4077 /* 4078 * Backdoors provided by the kernel bde 4079 */ 4080 4081 uint32_t 4082 lkbde_get_dev_phys(int d) 4083 { 4084 if (!VALID_DEVICE(d)) { 4085 return -1; 4086 } 4087 4088 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4089 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4090 d, _devices[d].dev_type); 4091 return 0; 4092 } 4093 return _devices[d].phys_address; 4094 } 4095 4096 uint32_t 4097 lkbde_get_dev_phys_hi(int d) 4098 { 4099 if (!VALID_DEVICE(d)) { 4100 return -1; 4101 } 4102 4103 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4104 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4105 d, _devices[d].dev_type); 4106 return 0; 4107 } 4108 #ifdef PHYS_ADDR_IS_64BIT 4109 return (uint32_t)(_devices[d].phys_address >> 32); 4110 #else 4111 return 0; 4112 #endif 4113 } 4114 4115 void * 4116 lkbde_get_dev_virt(int d) 4117 { 4118 if (!VALID_DEVICE(d)) { 4119 return NULL; 4120 } 4121 4122 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4123 gprintk("lkbde_get_dev_virt: Not PCI device %d, type %x\n", 4124 d, _devices[d].dev_type); 4125 return 0; 4126 } 4127 4128 if (_devices[d].alt_base_addr) { 4129 return (void *)_devices[d].alt_base_addr; 4130 } 4131 4132 return (void *)_devices[d].bde_dev.base_address; 4133 } 4134 4135 int 4136 lkbde_get_dev_resource(int d, int rsrc, uint32_t *flags, 4137 uint32_t *phys_lo, uint32_t *phys_hi) 4138 { 4139 if (!VALID_DEVICE(d)) { 4140 return -1; 4141 } 4142 4143 *flags = 0; 4144 *phys_lo = 0; 4145 *phys_hi = 0; 4146 4147 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4148 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4149 d, _devices[d].dev_type); 4150 return 0; 4151 } 4152 4153 switch (rsrc) { 4154 case 0: 4155 *phys_lo = (uint32_t)(_devices[d].phys_address); 4156 #ifdef PHYS_ADDR_IS_64BIT 4157 *phys_hi = (uint32_t)(_devices[d].phys_address >> 32); 4158 #endif 4159 break; 4160 case 1: 4161 *phys_lo = (uint32_t)(_devices[d].phys_address1); 4162 #ifdef PHYS_ADDR_IS_64BIT 4163 *phys_hi = (uint32_t)(_devices[d].phys_address1 >> 32); 4164 #endif 4165 break; 4166 default: 4167 break; 4168 } 4169 4170 return 0; 4171 } 4172 4173 void * 4174 lkbde_get_dma_dev(int d) 4175 { 4176 if (!VALID_DEVICE(d)) { 4177 return NULL; 4178 } 4179 4180 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 4181 return (void *)_devices[d].dma_dev; 4182 #else 4183 return (void *)_devices[d].pci_device; 4184 #endif 4185 } 4186 4187 void * 4188 lkbde_get_hw_dev(int d) 4189 { 4190 if (!VALID_DEVICE(d)) { 4191 return NULL; 4192 } 4193 4194 return (void *)_devices[d].pci_device; 4195 } 4196 4197 int 4198 lkbde_dev_state_set(int d, uint32 state) 4199 { 4200 bde_ctrl_t *ctrl; 4201 4202 if (!VALID_DEVICE(d)) { 4203 return -1; 4204 } 4205 ctrl = _devices + d; 4206 ctrl->dev_state = state; 4207 return 0; 4208 } 4209 4210 int 4211 lkbde_dev_state_get(int d, uint32 *state) 4212 { 4213 bde_ctrl_t *ctrl; 4214 if (!VALID_DEVICE(d)) { 4215 gprintk("_get_dev: Invalid device index %d\n", d); 4216 return -1; 4217 } 4218 ctrl = _devices + d; 4219 4220 *state = ctrl->dev_state; 4221 return 0; 4222 } 4223 4224 int 4225 lkbde_dev_instid_set(int d, uint32 instid) 4226 { 4227 bde_ctrl_t *ctrl; 4228 4229 if (!VALID_DEVICE(d)) { 4230 return -1; 4231 } 4232 ctrl = _devices + d; 4233 ctrl->inst_id = instid; 4234 4235 return 0; 4236 } 4237 4238 int 4239 lkbde_dev_instid_get(int d, uint32 *instid) 4240 { 4241 bde_ctrl_t *ctrl; 4242 4243 if (!VALID_DEVICE(d)) { 4244 return -1; 4245 } 4246 ctrl = _devices + d; 4247 *instid = ctrl->inst_id; 4248 4249 return 0; 4250 } 4251 /* 4252 * When a secondary interrupt handler is installed this function 4253 * is used for synchronizing hardware access to the IRQ mask 4254 * register. The secondary driver will supply a non-zero fmask 4255 * (filter mask) to indicate which interrupt bits it controls. 4256 * The fmask is ignored for the primary driver. 4257 */ 4258 int 4259 lkbde_irq_mask_set(int d, uint32_t addr, uint32_t mask, uint32_t fmask) 4260 { 4261 bde_ctrl_t *ctrl; 4262 int isr2_dev, iproc_reg; 4263 unsigned long flags; 4264 4265 isr2_dev = d & LKBDE_ISR2_DEV; 4266 iproc_reg = d & LKBDE_IPROC_REG; 4267 d &= ~(LKBDE_ISR2_DEV | LKBDE_IPROC_REG); 4268 4269 if (!VALID_DEVICE(d)) { 4270 return -1; 4271 } 4272 4273 ctrl = _devices + d; 4274 4275 /* Lock is required to synchronize access from user space */ 4276 spin_lock_irqsave(&ctrl->lock, flags); 4277 4278 if (isr2_dev) { 4279 /* This is the secondary interrupt handler */ 4280 ctrl->fmask = fmask; 4281 ctrl->imask2 = mask & ctrl->fmask; 4282 } else { 4283 /* This is the primary interrupt handler */ 4284 ctrl->imask = mask & ~ctrl->fmask; 4285 } 4286 4287 if (iproc_reg) { 4288 _iproc_write(d, addr, ctrl->imask | ctrl->imask2); 4289 } else { 4290 _write(d, addr, ctrl->imask | ctrl->imask2); 4291 } 4292 4293 spin_unlock_irqrestore(&ctrl->lock, flags); 4294 4295 return 0; 4296 } 4297 4298 /* 4299 * When a secondary interrupt handler is installed, this function 4300 * is used to avoid activating the user mode interrupt handler 4301 * thread if all pending interrupts are handled in kernel space. 4302 * 4303 * The mask returned is the mask of all interrupts, it can be used 4304 * to do a logical AND with fmask, the result will tell you if 4305 * the user mode interrupt handler needs to be invoked. 4306 * 4307 * Note that if no secondary handler is installed, the value of 4308 * "mask & fmask" will be zero, and hence there will be no need to read the 4309 * current interrupt status from hardware (from kernel space). 4310 */ 4311 int 4312 lkbde_irq_mask_get(int d, uint32_t *mask, uint32_t *fmask) 4313 { 4314 bde_ctrl_t *ctrl; 4315 4316 d &= ~(LKBDE_ISR2_DEV | LKBDE_IPROC_REG); 4317 4318 if (!VALID_DEVICE(d)) { 4319 return -1; 4320 } 4321 4322 if (mask == NULL || fmask == NULL) { 4323 return -1; 4324 } 4325 4326 ctrl = _devices + d; 4327 4328 *fmask = ctrl->fmask; 4329 *mask = ctrl->imask | ctrl->imask2; 4330 4331 return 0; 4332 } 4333 4334 int 4335 lkbde_get_num_devices(int type) 4336 { 4337 return _num_devices(type); 4338 } 4339 4340 /* 4341 * Export functions 4342 */ 4343 LKM_EXPORT_SYM(linux_bde_create); 4344 LKM_EXPORT_SYM(linux_bde_destroy); 4345 LKM_EXPORT_SYM(lkbde_get_dev_phys); 4346 LKM_EXPORT_SYM(lkbde_get_dev_virt); 4347 LKM_EXPORT_SYM(lkbde_get_dev_resource); 4348 LKM_EXPORT_SYM(lkbde_get_hw_dev); 4349 LKM_EXPORT_SYM(lkbde_get_dma_dev); 4350 LKM_EXPORT_SYM(lkbde_irq_mask_set); 4351 LKM_EXPORT_SYM(lkbde_irq_mask_get); 4352 LKM_EXPORT_SYM(lkbde_get_dev_phys_hi); 4353 LKM_EXPORT_SYM(lkbde_dev_state_set); 4354 LKM_EXPORT_SYM(lkbde_dev_state_get); 4355 LKM_EXPORT_SYM(lkbde_dev_instid_set); 4356 LKM_EXPORT_SYM(lkbde_dev_instid_get); 4357 #ifdef BCM_SAND_SUPPORT 4358 LKM_EXPORT_SYM(lkbde_cpu_write); 4359 LKM_EXPORT_SYM(lkbde_cpu_read); 4360 LKM_EXPORT_SYM(lkbde_cpu_pci_register); 4361 #endif