switch.c (74405B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 #include <soc/debug.h> 8 #include <soc/drv.h> 9 #include <soc/mem.h> 10 #include <bcm/switch.h> 11 #include <bcm/error.h> 12 #include <bcm_int/esw/switch.h> 13 #include <bcm_int/esw/port.h> 14 #include <bcm_int/esw/trident3.h> 15 16 #if defined(BCM_HELIX5_SUPPORT) 17 #include <soc/helix5.h> 18 #endif 19 20 #define LARGE_SCALE_NAT_UC_ARG2REG(arg) \ 21 ((arg)==BCM_L3UC_NAT_NONE ? 0 : \ 22 (arg)==BCM_L3UC_NAT_UDP ? 1 : \ 23 (arg)==BCM_L3UC_NAT_TCP ? 2 : \ 24 (arg)==BCM_L3UC_NAT ? 3 : -1) 25 26 #define LARGE_SCALE_NAT_UC_REG2ARG(val) \ 27 ((val)==1 ? BCM_L3UC_NAT_UDP : \ 28 (val)==2 ? BCM_L3UC_NAT_TCP : \ 29 (val)==3 ? BCM_L3UC_NAT : 0) 30 31 #define LARGE_SCALE_NAT_MC_ARG2REG(arg) \ 32 ((arg)==BCM_L3MC_NAT_NONE ? 0 : \ 33 (arg)==BCM_L3MC_DNAT ? 1 : \ 34 (arg)==BCM_L3MC_DNAT_WITH_MACDA_UPDATE ? 1 : \ 35 (arg)==BCM_L3MC_SNAT ? 2 : \ 36 (arg)==BCM_L3MC_DNAT_SNAT ? 3 : \ 37 (arg)==BCM_L3MC_DNAT_SNAT_WITH_MACDA_UPDATE ? 3 : \ 38 (arg)==BCM_L3MC_DNAPT ? 4 : \ 39 (arg)==BCM_L3MC_DNAPT_WITH_MACDA_UPDATE ? 4 : \ 40 (arg)==BCM_L3MC_SNAPT ? 5 : \ 41 (arg)==BCM_L3MC_DNAPT_SNAPT ? 6 : \ 42 (arg)==BCM_L3MC_DNAPT_SNAPT_WITH_MACDA_UPDATE ? 6 : -1) 43 44 #define LARGE_SCALE_NAT_MC_REG2ARG(val, da) \ 45 ((val)==1 && !(da) ? BCM_L3MC_DNAT : \ 46 (val)==1 && (da) ? BCM_L3MC_DNAT_WITH_MACDA_UPDATE : \ 47 (val)==2 ? BCM_L3MC_SNAT : \ 48 (val)==3 && !(da) ? BCM_L3MC_DNAT_SNAT : \ 49 (val)==3 && (da) ? BCM_L3MC_DNAT_SNAT_WITH_MACDA_UPDATE : \ 50 (val)==4 && !(da) ? BCM_L3MC_DNAPT: \ 51 (val)==4 && (da) ? BCM_L3MC_DNAPT_WITH_MACDA_UPDATE: \ 52 (val)==5 ? BCM_L3MC_SNAPT: \ 53 (val)==6 && !(da) ? BCM_L3MC_DNAPT_SNAPT : \ 54 (val)==6 && (da) ? BCM_L3MC_DNAPT_SNAPT_WITH_MACDA_UPDATE : 0) 55 56 #define LARGE_SCALE_NAT_DA_UPDATE(arg) \ 57 ((arg)==BCM_L3MC_DNAT_WITH_MACDA_UPDATE || \ 58 (arg)==BCM_L3MC_DNAT_SNAT_WITH_MACDA_UPDATE || \ 59 (arg)==BCM_L3MC_DNAPT_WITH_MACDA_UPDATE || \ 60 (arg)==BCM_L3MC_DNAPT_SNAPT_WITH_MACDA_UPDATE) 61 62 #define LARGE_SCALE_NAT_UC_FIELD_ID(type) \ 63 ((type)==bcmSwitchL3UcLargeDNAT ? L3UC_DNATf : \ 64 (type)==bcmSwitchL3UcLargeSNAT ? L3UC_SNATf : \ 65 (type)==bcmSwitchL3UcLargeDNATSNAT ? L3UC_DNAT_SNATf : \ 66 (type)==bcmSwitchL3UcLargeDNAPT ? L3UC_DNAPTf : \ 67 (type)==bcmSwitchL3UcLargeSNAPT ? L3UC_SNAPTf : \ 68 L3UC_DNAPT_SNAPTf) 69 70 #define LARGE_SCALE_NAT_MC_FIELD_ID(type) \ 71 ((type)==bcmSwitchL3McLargeNATRewriteType0 ? L3MC_RW_TYPE_0_SELf : \ 72 (type)==bcmSwitchL3McLargeNATRewriteType1 ? L3MC_RW_TYPE_1_SELf : \ 73 L3MC_RW_TYPE_2_SELf) 74 75 #define LARGE_SCALE_NAT_MAC_UPDATE_FIELD_ID(type) \ 76 ((type)==bcmSwitchL3McLargeNATRewriteType0 ? L3MC_RW_TYPE_0_MAC_DA_UPDATEf : \ 77 (type)==bcmSwitchL3McLargeNATRewriteType1 ? L3MC_RW_TYPE_1_MAC_DA_UPDATEf : \ 78 L3MC_RW_TYPE_2_MAC_DA_UPDATEf) 79 80 /* Helper routines for argument translation */ 81 82 static int 83 _bool_invert(int unit, int arg, int set) 84 { 85 /* Same for both set/get */ 86 return !arg; 87 } 88 89 /* 90 * Chip 0 means no TH or TD2P 91 */ 92 bcm_switch_binding_t trident3_bindings[] = 93 { 94 95 #if defined(BCM_TRIUMPH3_SUPPORT) 96 {bcmSwitchWlanClientAuthorizeAll, 0, 97 AXP_WRX_MASTER_CTRLr, WCD_DISABLEf, 98 NULL, 0}, 99 #endif /* BCM_TRIUMPH3_SUPPORT */ 100 101 #if defined(BCM_TRIUMPH2_SUPPORT) 102 { bcmSwitchWlanClientUnauthToCpu, 0, 103 CPU_CONTROL_Mr, WLAN_DOT1X_DROPf, 104 NULL, 0}, 105 { bcmSwitchWlanClientRoamedOutErrorToCpu, 0, 106 CPU_CONTROL_Mr, WLAN_ROAM_ERRORf, 107 NULL, 0}, 108 { bcmSwitchWlanClientSrcMacMissToCpu, 0, 109 CPU_CONTROL_Mr, WCD_SA_MISSf, 110 NULL, 0}, 111 { bcmSwitchWlanClientDstMacMissToCpu, 0, 112 CPU_CONTROL_Mr, WCD_DA_MISSf, 113 NULL, 0}, 114 { bcmSwitchOamHeaderErrorToCpu, 1, 115 CPU_CONTROL_Mr, OAM_HEADER_ERROR_TOCPUf, 116 NULL, 0}, 117 { bcmSwitchOamUnknownVersionToCpu, 1, 118 CPU_CONTROL_Mr, OAM_UNKNOWN_OPCODE_VERSION_TOCPUf, 119 NULL, 0}, 120 { bcmSwitchL3SrcBindFailToCpu, 1, 121 CPU_CONTROL_Mr, MAC_BIND_FAILf, 122 NULL, 0}, 123 { bcmSwitchTunnelIp4IdShared, 1, 124 EGR_TUNNEL_ID_MASKr, SHARED_FRAG_ID_ENABLEf, 125 NULL, 0}, 126 { bcmSwitchIpfixRateViolationDataInsert, 0, 127 ING_IPFIX_FLOW_RATE_CONTROLr, SUSPECT_FLOW_INSERT_DISABLEf, 128 _bool_invert, soc_feature_ipfix_rate }, 129 { bcmSwitchIpfixRateViolationPersistent, 0, 130 ING_IPFIX_FLOW_RATE_CONTROLr, SUSPECT_FLOW_CONVERT_DISABLEf, 131 NULL, 0}, 132 { bcmSwitchCustomerQueuing, 0, 133 ING_MISC_CONFIGr, PHB2_COS_MODEf, 134 NULL, soc_feature_vlan_queue_map}, 135 { bcmSwitchOamUnknownVersionDrop, 1, 136 OAM_DROP_CONTROLr, OAM_UNKNOWN_OPCODE_VERSION_DROPf, 137 NULL, 0}, 138 { bcmSwitchDirectedMirroring, 0, 139 EGR_PORT_64r, EM_SRCMOD_CHANGEf, 140 NULL, soc_feature_src_modid_blk }, 141 { bcmSwitchDirectedMirroring, 0, 142 IEGR_PORT_64r, EM_SRCMOD_CHANGEf, 143 NULL, soc_feature_src_modid_blk }, 144 #endif 145 146 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 147 { bcmSwitchOamUnexpectedPktToCpu, 1, 148 CPU_CONTROL_Mr, OAM_UNEXPECTED_PKT_TOCPUf, 149 NULL, 0}, 150 #endif 151 152 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 153 defined(BCM_TRIDENT2_SUPPORT) 154 { bcmSwitchOamCcmToCpu, 1, 155 CCM_COPYTO_CPU_CONTROLr, ERROR_CCM_COPY_TOCPUf, 156 NULL, 0}, 157 { bcmSwitchOamXconCcmToCpu, 1, 158 CCM_COPYTO_CPU_CONTROLr, XCON_CCM_COPY_TOCPUf, 159 NULL, 0}, 160 { bcmSwitchOamXconOtherToCpu, 1, 161 CCM_COPYTO_CPU_CONTROLr, XCON_OTHER_COPY_TOCPUf, 162 NULL, 0}, 163 #endif /* !BCM_TRIUMPH3_SUPPORT */ 164 165 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) 166 { bcmSwitchL3InterfaceUrpfEnable, 1, 167 ING_CONFIG_64r, L3IIF_URPF_SELECTf, 168 NULL, soc_feature_urpf }, 169 #endif 170 171 #if defined(BCM_TRX_SUPPORT) 172 { bcmSwitchClassBasedMoveFailPktToCpu, 1, 173 CPU_CONTROL_1r, CLASS_BASED_SM_PREVENTED_TOCPUf, 174 NULL, soc_feature_class_based_learning }, 175 { bcmSwitchL3UrpfFailToCpu, 1, 176 CPU_CONTROL_1r, URPF_MISS_TOCPUf, 177 NULL, soc_feature_urpf }, 178 { bcmSwitchClassBasedMoveFailPktDrop, 1, 179 ING_MISC_CONFIG2r, CLASS_BASED_SM_PREVENTED_DROPf, 180 NULL, soc_feature_class_based_learning }, 181 { bcmSwitchSTPBlockedFieldBypass, 1, 182 ING_MISC_CONFIG2r, BLOCKED_PORTS_FP_DISABLEf, 183 NULL, 0}, 184 { bcmSwitchRateLimitLinear, 1, 185 MISCCONFIGr, ITU_MODE_SELf, 186 _bool_invert, 0}, 187 { bcmSwitchRemoteLearnTrust, 1, 188 ING_CONFIG_64r, IGNORE_HG_HDR_DONOT_LEARNf, 189 _bool_invert, 0 }, 190 { bcmSwitchMldDirectAttachedOnly, 1, 191 ING_CONFIG_64r, MLD_CHECKS_ENABLEf, 192 NULL, soc_feature_igmp_mld_support }, 193 { bcmSwitchSharedVlanL2McastEnable, 1, 194 ING_CONFIG_64r, LOOKUP_L2MC_WITH_FID_IDf, 195 NULL, 0}, 196 { bcmSwitchMldUcastEnable, 1, 197 ING_CONFIG_64r, MLD_PKTS_UNICAST_IGNOREf, 198 _bool_invert, soc_feature_igmp_mld_support }, 199 { bcmSwitchSharedVlanEnable, 1, 200 ING_CONFIG_64r, SVL_ENABLEf, 201 NULL, 0}, 202 { bcmSwitchIgmpReservedMcastEnable, 1, 203 ING_CONFIG_64r, IPV4_RESERVED_MC_ADDR_IGMP_ENABLEf, 204 NULL, soc_feature_igmp_mld_support }, 205 { bcmSwitchMldReservedMcastEnable, 1, 206 ING_CONFIG_64r, IPV6_RESERVED_MC_ADDR_MLD_ENABLEf, 207 NULL, soc_feature_igmp_mld_support }, 208 { bcmSwitchIgmpUcastEnable, 1, 209 ING_CONFIG_64r, IGMP_PKTS_UNICAST_IGNOREf, 210 _bool_invert, soc_feature_igmp_mld_support }, 211 { bcmSwitchPortEgressBlockL3, 1, 212 ING_CONFIG_64r, APPLY_EGR_MASK_ON_L3f, 213 NULL, 0}, 214 { bcmSwitchPortEgressBlockL2, 1, 215 ING_CONFIG_64r, APPLY_EGR_MASK_ON_L2f, 216 NULL, 0}, 217 { bcmSwitchHgHdrExtLengthEnable, 1, 218 ING_CONFIG_64r, IGNORE_HG_HDR_HDR_EXT_LENf, 219 _bool_invert, 0 }, 220 { bcmSwitchIp4McastL2DestCheck, 1, 221 ING_CONFIG_64r, IPV4_MC_MACDA_CHECK_ENABLEf, 222 NULL, 0}, 223 { bcmSwitchIp6McastL2DestCheck, 1, 224 ING_CONFIG_64r, IPV6_MC_MACDA_CHECK_ENABLEf, 225 NULL, 0}, 226 { bcmSwitchL3TunnelUrpfMode, 1, 227 ING_CONFIG_64r, TUNNEL_URPF_MODEf, 228 NULL, soc_feature_urpf }, 229 { bcmSwitchL3TunnelUrpfDefaultRoute, 1, 230 ING_CONFIG_64r, TUNNEL_URPF_DEFAULTROUTECHECKf, 231 _bool_invert, soc_feature_urpf }, 232 { bcmSwitchMirrorStackMode, 1, 233 ING_CONFIG_64r, STACK_MODEf, 234 NULL, soc_feature_src_modid_blk }, 235 { bcmSwitchDirectedMirroring, 1, 236 ING_CONFIG_64r, DRACO1_5_MIRRORf, 237 _bool_invert, soc_feature_xgs1_mirror }, 238 { bcmSwitchMirrorSrcModCheck, 1, 239 ING_CONFIG_64r, FB_A0_COMPATIBLEf, 240 NULL, soc_feature_src_modid_blk }, 241 { bcmSwitchProxySrcKnockout, 1, 242 IHG_LOOKUPr, REMOVE_MH_SRC_PORTf, 243 NULL, soc_feature_proxy_port_property }, 244 #endif /* BCM_1_SUPPORT */ 245 246 #if defined(BCM_TRIUMPH_SUPPORT) 247 { bcmSwitchDosAttackToCpu, 1, 248 CPU_CONTROL_0r, DOSATTACK_TOCPUf, 249 NULL, 0 }, 250 { bcmSwitchParityErrorToCpu, 1, 251 CPU_CONTROL_0r, PARITY_ERR_TOCPUf, 252 NULL, soc_feature_parity_err_tocpu }, 253 { bcmSwitchUnknownVlanToCpu, 1, 254 CPU_CONTROL_0r, UVLAN_TOCPUf, 255 NULL, 0 }, 256 { bcmSwitchSourceMacZeroDrop, 0, 257 CPU_CONTROL_0r, MACSA_ALL_ZERO_DROPf, 258 NULL, 0}, 259 { bcmSwitchMplsSequenceErrToCpu, 0, 260 ING_MISC_CONFIGr, MPLS_SEQ_NUM_FAIL_TOCPUf, 261 NULL, 0}, 262 { bcmSwitchMplsLabelMissToCpu, 0, 263 CPU_CONTROL_Mr, MPLS_LABEL_MISSf, 264 NULL, 0}, 265 { bcmSwitchMplsTtlErrToCpu, 1, 266 CPU_CONTROL_Mr, MPLS_TTL_CHECK_FAILf, 267 NULL, 0}, 268 { bcmSwitchMplsInvalidL3PayloadToCpu, 0, 269 CPU_CONTROL_Mr, MPLS_INVALID_PAYLOADf, 270 NULL, 0}, 271 { bcmSwitchMplsInvalidActionToCpu, 0, 272 CPU_CONTROL_Mr, MPLS_INVALID_ACTIONf, 273 NULL, 0}, 274 { bcmSwitchSharedVlanMismatchToCpu, 0, 275 CPU_CONTROL_0r, PVLAN_VID_MISMATCH_TOCPUf , 276 NULL, 0}, 277 { bcmSwitchForceForwardFabricTrunk, 0, 278 ING_MISC_CONFIGr, LOCAL_SW_DISABLE_HGTRUNK_RES_ENf, 279 NULL, 0}, 280 { bcmSwitchFieldMultipathHashSeed, 0, 281 FP_ECMP_HASH_CONTROLr, ECMP_HASH_SALTf, 282 NULL, 0}, 283 { bcmSwitchMplsPortIndependentLowerRange1, 0, 284 GLOBAL_MPLS_RANGE_1_LOWERr, LABELf, 285 NULL, 0}, 286 { bcmSwitchMplsPortIndependentUpperRange1, 1, 287 GLOBAL_MPLS_RANGE_1_UPPERr, LABELf, 288 NULL, 0}, 289 { bcmSwitchMplsPortIndependentLowerRange2, 1, 290 GLOBAL_MPLS_RANGE_2_LOWERr, LABELf, 291 NULL, 0}, 292 { bcmSwitchMplsPortIndependentUpperRange2, 1, 293 GLOBAL_MPLS_RANGE_2_UPPERr, LABELf, 294 NULL, 0}, 295 { bcmSwitchL3UrpfRouteEnableExternal, 1, 296 L3_DEFIP_RPF_CONTROLr, DEFIP_RPF_ENABLEf, 297 NULL, soc_feature_urpf}, 298 { bcmSwitchMplsPWControlWordToCpu, 0, 299 ING_MISC_CONFIGr, PWACH_TOCPUf, 300 NULL, soc_feature_mpls}, 301 { bcmSwitchMplsPWControlTypeToCpu, 0, 302 ING_MISC_CONFIGr, OTHER_CW_TYPE_TOCPUf, 303 NULL, soc_feature_mpls}, 304 { bcmSwitchMplsPWCountPktsAll, 0, 305 ING_MISC_CONFIGr, PW_COUNT_ALLf, 306 NULL, soc_feature_mpls}, 307 #endif /* BCM_TRIUMPH_SUPPORT */ 308 309 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 310 { bcmSwitchCpuToCpuEnable, 1, 311 ING_MISC_CONFIGr, DO_NOT_COPY_FROM_CPU_TO_CPUf, 312 _bool_invert, 0 }, 313 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 314 315 #if defined(BCM_FIREBOLT_SUPPORT) 316 { bcmSwitchCpuProtocolPrio, 0, 317 CPU_CONTROL_2r, CPU_PROTOCOL_PRIORITYf, 318 NULL, 0 }, 319 #endif /* BCM_FIREBOLT_SUPPORT */ 320 321 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) 322 { bcmSwitchAlternateStoreForward, 0, 323 ASFCONFIGr, ASF_ENf, 324 NULL, soc_feature_asf }, 325 { bcmSwitchRemoteLearnTrust, 0, 326 ING_CONFIGr, DO_NOT_LEARN_ENABLEf, 327 NULL, soc_feature_remote_learn_trust }, 328 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT */ 329 330 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 331 { bcmSwitchL3UrpfRouteEnable, 1, 332 L3_DEFIP_RPF_CONTROLr, DEFIP_RPF_ENABLEf, 333 NULL, soc_feature_urpf}, 334 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 335 336 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_TRX_SUPPORT) 337 { bcmSwitchStationMoveOverLearnLimitToCpu, 1, 338 CPU_CONTROL_1r, MACLMT_STNMV_TOCPUf, 339 NULL, soc_feature_mac_learn_limit}, 340 #endif /* BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 341 342 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) 343 { bcmSwitchControlOpcodePriority, 0, 344 CPU_CONTROL_2r, CPU_MH_CONTROL_PRIORITYf, 345 NULL, 0 }, 346 #endif /* BCM_BRADLEY_SUPPORT || BCM_RAPTOR_SUPPORT */ 347 348 349 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 350 defined(BCM_TRX_SUPPORT) 351 { bcmSwitchBpduInvalidVlanDrop, 1, 352 EGR_CONFIG_1_64r, BPDU_INVALID_VLAN_DROPf, 353 NULL, soc_feature_igmp_mld_support }, 354 { bcmSwitchMirrorInvalidVlanDrop, 1, 355 EGR_CONFIG_1_64r, MIRROR_INVALID_VLAN_DROPf, 356 NULL, soc_feature_igmp_mld_support }, 357 { bcmSwitchMcastFloodBlocking, 1, 358 IGMP_MLD_PKT_CONTROLr, PFM_RULE_APPLYf, 359 NULL, soc_feature_igmp_mld_support }, 360 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 361 362 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAVEN_SUPPORT) || \ 363 defined(BCM_TRX_SUPPORT) 364 { bcmSwitchIpmcTtl1ToCpu, 1, 365 CPU_CONTROL_1r, IPMC_TTL1_ERR_TOCPUf, 366 NULL, 0 }, 367 { bcmSwitchL3UcastTtl1ToCpu, 1, 368 CPU_CONTROL_1r, L3UC_TTL1_ERR_TOCPUf, 369 NULL, 0 }, 370 { bcmSwitchDhcpLearn, 1, 371 ING_MISC_CONFIG2r, DO_NOT_LEARN_DHCPf, 372 NULL, 0 }, 373 { bcmSwitchUnknownIpmcAsMcast, 1, 374 ING_MISC_CONFIG2r, IPMC_MISS_AS_L2MCf, 375 NULL, 0 }, 376 { bcmSwitchTunnelUnknownIpmcDrop, 1, 377 ING_MISC_CONFIG2r, UNKNOWN_TUNNEL_IPMC_DROPf, 378 NULL, 0 }, 379 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAVEN_SUPPORT || BCM_TRX_SUPPORT */ 380 381 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 382 defined(BCM_TRX_SUPPORT) 383 { bcmSwitchMcastUnknownErrToCpu, 1, 384 CPU_CONTROL_1r, MC_INDEX_ERROR_TOCPUf, 385 NULL,0}, 386 #endif /* BCM_RAPTOR_SUPPORT || BCM_BRADLEY_SUPPORT || BCM_TRX_SUPPORT */ 387 388 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) ||\ 389 defined(BCM_RAPTOR_SUPPORT) 390 { bcmSwitchDosAttackMACSAEqualMACDA, 1, 391 DOS_CONTROLr, MACSA_EQUALS_MACDA_DROPf, 392 NULL, soc_feature_enhanced_dos_ctrl }, 393 { bcmSwitchDosAttackFlagZeroSeqZero, 1, 394 DOS_CONTROLr, TCP_FLAGS_CTRL0_SEQ0_ENABLEf, 395 NULL, 0 }, 396 { bcmSwitchDosAttackSynFrag, 1, 397 DOS_CONTROLr, TCP_FLAGS_SYN_FRAG_ENABLEf, 398 NULL, 0}, 399 { bcmSwitchDosAttackIcmp, 1, 400 DOS_CONTROL_2r, ICMP_V4_PING_SIZE_ENABLEf, 401 NULL, 0 }, 402 { bcmSwitchDosAttackIcmp, 1, 403 DOS_CONTROL_2r, ICMP_V6_PING_SIZE_ENABLEf, 404 NULL, 0 }, 405 { bcmSwitchDosAttackIcmpV4, 1, 406 DOS_CONTROL_2r, ICMP_V4_PING_SIZE_ENABLEf, 407 NULL, 0 }, 408 { bcmSwitchDosAttackIcmpV6, 1, 409 DOS_CONTROL_2r, ICMP_V6_PING_SIZE_ENABLEf, 410 NULL, 0 }, 411 { bcmSwitchDosAttackIcmpFragments, 1, 412 DOS_CONTROL_2r, ICMP_FRAG_PKTS_ENABLEf, 413 NULL, soc_feature_enhanced_dos_ctrl }, 414 { bcmSwitchDosAttackTcpOffset, 1, 415 DOS_CONTROL_2r, TCP_HDR_OFFSET_EQ1_ENABLEf, 416 NULL, soc_feature_enhanced_dos_ctrl }, 417 { bcmSwitchDosAttackUdpPortsEqual, 1, 418 DOS_CONTROL_2r, UDP_SPORT_EQ_DPORT_ENABLEf, 419 NULL, soc_feature_enhanced_dos_ctrl }, 420 { bcmSwitchDosAttackTcpPortsEqual, 1, 421 DOS_CONTROL_2r, TCP_SPORT_EQ_DPORT_ENABLEf, 422 NULL, soc_feature_enhanced_dos_ctrl }, 423 { bcmSwitchDosAttackTcpFlagsSF, 1, 424 DOS_CONTROL_2r, TCP_FLAGS_SYN_FIN_ENABLEf, 425 NULL, soc_feature_enhanced_dos_ctrl }, 426 { bcmSwitchDosAttackTcpFlagsFUP, 1, 427 DOS_CONTROL_2r, TCP_FLAGS_FIN_URG_PSH_SEQ0_ENABLEf, 428 NULL, soc_feature_enhanced_dos_ctrl }, 429 { bcmSwitchDosAttackTcpHdrPartial, 1, 430 DOS_CONTROL_2r, TCP_HDR_PARTIAL_ENABLEf, 431 NULL, soc_feature_enhanced_dos_ctrl }, 432 { bcmSwitchDosAttackV6MinFragEnable, 1, 433 DOS_CONTROL_2r, IPV6_MIN_FRAG_SIZE_ENABLEf, 434 NULL, soc_feature_enhanced_dos_ctrl }, 435 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT || BCM_RAPTOR_SUPPORT */ 436 437 #if defined (BCM_TRIDENT_SUPPORT) || defined (BCM_KATANA_SUPPORT) 438 { bcmSwitchHashNivSrcIfEtagSvidSelect0, 1, 439 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_0_SELECT_Af, 440 NULL, 0 }, 441 { bcmSwitchHashNivSrcIfEtagSvidSelect1, 1, 442 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_0_SELECT_Bf, 443 NULL, 0 }, 444 { bcmSwitchHashNivDstIfEtagVidSelect0, 1, 445 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_1_SELECT_Af, 446 NULL, 0 }, 447 { bcmSwitchHashNivDstIfEtagVidSelect1, 1, 448 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_1_SELECT_Bf, 449 NULL, 0 }, 450 #endif /* BCM_TRIDENT_SUPPORT */ 451 452 453 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) ||\ 454 defined(BCM_BRADLEY_SUPPORT) 455 { bcmSwitchDirectedMirroring, 0, 456 ING_CONFIGr, DRACO1_5_MIRRORf, 457 _bool_invert, soc_feature_xgs1_mirror }, 458 { bcmSwitchDirectedMirroring, 1, 459 EGR_PORTr, EM_SRCMOD_CHANGEf, 460 NULL, soc_feature_src_modid_blk }, 461 { bcmSwitchDirectedMirroring, 1, 462 IEGR_PORTr, EM_SRCMOD_CHANGEf, 463 NULL, soc_feature_src_modid_blk }, 464 { bcmSwitchMirrorStackMode, 1, 465 ING_CONFIGr, STACK_MODEf, 466 NULL, soc_feature_src_modid_blk }, 467 { bcmSwitchMirrorStackMode, 0, 468 MISCCONFIGr, STACK_MODEf, 469 NULL, soc_feature_src_modid_blk }, 470 { bcmSwitchMirrorSrcModCheck, 0, 471 ING_CONFIGr, FB_A0_COMPATIBLEf, 472 NULL, soc_feature_src_modid_blk }, 473 { bcmSwitchSrcModBlockMirrorCopy, 0, 474 MIRROR_CONTROLr, SRC_MODID_BLOCK_MIRROR_COPYf, 475 NULL, soc_feature_src_modid_blk }, 476 { bcmSwitchSrcModBlockMirrorOnly, 0, 477 MIRROR_CONTROLr, SRC_MODID_BLOCK_MIRROR_ONLY_PKTf, 478 NULL, soc_feature_src_modid_blk }, 479 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT || BCM_BRADLEY_SUPPORT */ 480 481 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) ||\ 482 defined(BCM_RAVEN_SUPPORT) 483 { bcmSwitchDestPortHGTrunk, 0, 484 ING_MISC_CONFIGr, USE_DEST_PORTf, 485 NULL, soc_feature_port_trunk_index }, 486 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT || BCM_RAVEN_SUPPORT */ 487 488 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 489 defined(BCM_HELIX_SUPPORT) || defined(BCM_TRX_SUPPORT) 490 { bcmSwitchDirectedMirroring, 1, 491 MISCCONFIGr, DRACO_1_5_MIRRORING_MODE_ENf, 492 _bool_invert, soc_feature_xgs1_mirror }, 493 { bcmSwitchMirrorUnmarked, 1, 494 EGR_CONFIG_1_64r, RING_MODEf, 495 _bool_invert, 0 }, 496 { bcmSwitchMirrorStackMode, 1, 497 EGR_CONFIG_1_64r, STACK_MODEf, 498 NULL, soc_feature_src_modid_blk }, 499 { bcmSwitchMeterAdjust, 1, 500 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf, 501 NULL, soc_feature_meter_adjust }, 502 { bcmSwitchMeterAdjust, 1, 503 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTES_2f, 504 NULL, soc_feature_meter_adjust }, 505 { bcmSwitchMeterAdjust, 1, 506 FP_METER_CONTROLr, PACKET_IFG_BYTESf, 507 NULL, soc_feature_meter_adjust }, 508 { bcmSwitchMeterAdjust, 0, 509 EFP_METER_CONTROL_2r, PACKET_IFG_BYTESf, 510 NULL, soc_feature_meter_adjust }, 511 { bcmSwitchMeterAdjust, 1, 512 EGR_COUNTER_CONTROLr, PACKET_IFG_BYTESf, 513 NULL, soc_feature_meter_adjust }, 514 { bcmSwitchMeterAdjust, 1, 515 EGR_COUNTER_CONTROLr, PACKET_IFG_BYTES_2f, 516 NULL, soc_feature_meter_adjust }, 517 { bcmSwitchMeterAdjust, 0, 518 MTRI_IFGr, PACKET_IFG_BYTESf, 519 NULL, soc_feature_meter_adjust }, 520 { bcmSwitchEgressBlockUcast, 1, 521 ING_MISC_CONFIGr, APPLY_EGR_MASK_ON_UC_ONLYf, 522 NULL, soc_feature_egress_blk_ucast_override }, 523 { bcmSwitchSourceModBlockUcast, 1, 524 ING_MISC_CONFIGr, APPLY_SRCMOD_BLOCK_ON_UC_ONLYf, 525 NULL, soc_feature_src_modid_blk_ucast_override }, 526 { bcmSwitchHgHdrMcastFloodOverride, 1, 527 EGR_CONFIG_1_64r, FORCE_STATIC_MH_PFMf, 528 NULL, soc_feature_static_pfm }, 529 { bcmSwitchShaperAdjust, 1, 530 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf, 531 NULL, soc_feature_meter_adjust }, 532 { bcmSwitchShaperAdjust, 1, 533 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTES_2f, 534 NULL, soc_feature_meter_adjust }, 535 { bcmSwitchShaperAdjust, 0, 536 MTRI_IFGr, PACKET_IFG_BYTESf, 537 NULL, soc_feature_meter_adjust }, 538 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_BRADLEY_SUPPORT || 539 BCM_HELIX_SUPPORT || BCM_TRX_SUPPORT */ 540 541 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 542 defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 543 { bcmSwitchHgHdrErrToCpu, 1, 544 CPU_CONTROL_1r, HG_HDR_ERROR_TOCPUf, 545 NULL, soc_feature_cpu_proto_prio}, 546 { bcmSwitchClassTagPacketsToCpu, 1, 547 CPU_CONTROL_1r, HG_HDR_TYPE1_TOCPUf, 548 NULL, soc_feature_cpu_proto_prio}, 549 { bcmSwitchRemoteLearnTrust, 1, 550 EGR_CONFIG_1_64r, IGNORE_HG_HDR_DONOT_LEARNf, 551 _bool_invert, 0 }, 552 { bcmSwitchSourceModBlockControlOpcode, 1, 553 ING_MISC_CONFIGr, DO_NOT_APPLY_SRCMOD_BLOCK_ON_SCf, 554 _bool_invert, soc_feature_src_modid_blk_opcode_override }, 555 #endif /* BCM_RAPTOR_SUPPORT || BCM_BRADLEY_SUPPORT || 556 BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 557 558 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 559 defined(BCM_FIREBOLT2_SUPPORT) 560 { bcmSwitchCpuProtoBpduPriority, 0, 561 CPU_CONTROL_3r, CPU_PROTO_BPDU_PRIORITYf, 562 NULL, soc_feature_cpu_proto_prio }, 563 { bcmSwitchCpuProtoArpPriority, 0, 564 CPU_CONTROL_3r, CPU_PROTO_ARP_PRIORITYf, 565 NULL, soc_feature_cpu_proto_prio }, 566 { bcmSwitchCpuProtoIgmpPriority, 0, 567 CPU_CONTROL_3r, CPU_PROTO_IGMP_PRIORITYf, 568 NULL, soc_feature_cpu_proto_prio }, 569 { bcmSwitchCpuProtoDhcpPriority, 0, 570 CPU_CONTROL_3r, CPU_PROTO_DHCP_PRIORITYf, 571 NULL, soc_feature_cpu_proto_prio }, 572 { bcmSwitchCpuProtoIpmcReservedPriority, 0, 573 CPU_CONTROL_3r, CPU_PROTO_IPMC_RESERVED_PRIORITYf, 574 NULL, soc_feature_cpu_proto_prio }, 575 { bcmSwitchCpuProtoIpOptionsPriority, 0, 576 CPU_CONTROL_3r, CPU_PROTO_IP_OPTIONS_PRIORITYf, 577 NULL, soc_feature_cpu_proto_prio }, 578 { bcmSwitchCpuProtoExceptionsPriority, 0, 579 CPU_CONTROL_3r, CPU_PROTO_EXCEPTIONS_PRIORITYf, 580 NULL, soc_feature_cpu_proto_prio }, 581 #endif /* BCM_RAPTOR_SUPPORT || BCM_BRADLEY_SUPPORT || 582 BCM_FIREBOLT2_SUPPORT */ 583 584 #if defined(BCM_HELIX_SUPPORT) || defined(BCM_FIREBOLT_SUPPORT) || \ 585 defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRX_SUPPORT) 586 { bcmSwitchUnknownMcastToCpu, 1, 587 CPU_CONTROL_1r, UMC_TOCPUf, 588 NULL, 0 }, 589 { bcmSwitchUnknownUcastToCpu, 1, 590 CPU_CONTROL_1r, UUCAST_TOCPUf, 591 NULL, 0 }, 592 { bcmSwitchL2StaticMoveToCpu, 1, 593 CPU_CONTROL_1r, STATICMOVE_TOCPUf, 594 NULL, 0 }, 595 { bcmSwitchL3HeaderErrToCpu, 1, /* compat */ 596 CPU_CONTROL_1r, V4L3ERR_TOCPUf, 597 NULL, 0 }, 598 { bcmSwitchUnknownL3SrcToCpu, 1, 599 CPU_CONTROL_1r, UNRESOLVEDL3SRC_TOCPUf, 600 NULL, 0 }, 601 { bcmSwitchUnknownL3DestToCpu, 1, /* compat */ 602 CPU_CONTROL_1r, V4L3DSTMISS_TOCPUf, 603 NULL, 0 }, 604 { bcmSwitchIpmcPortMissToCpu, 1, 605 CPU_CONTROL_1r, IPMCPORTMISS_TOCPUf, 606 NULL, 0 }, 607 { bcmSwitchIpmcErrorToCpu, 1, 608 CPU_CONTROL_1r, IPMCERR_TOCPUf, 609 NULL, 0 }, 610 { bcmSwitchL2NonStaticMoveToCpu, 1, 611 CPU_CONTROL_1r, NONSTATICMOVE_TOCPUf, 612 NULL, 0 }, 613 { bcmSwitchV6L3ErrToCpu, 1, 614 CPU_CONTROL_1r, V6L3ERR_TOCPUf, 615 NULL, 0 }, 616 { bcmSwitchV6L3DstMissToCpu, 1, 617 CPU_CONTROL_1r, V6L3DSTMISS_TOCPUf, 618 NULL, 0 }, 619 { bcmSwitchV4L3ErrToCpu, 1, 620 CPU_CONTROL_1r, V4L3ERR_TOCPUf, 621 NULL, 0 }, 622 { bcmSwitchV4L3DstMissToCpu, 1, 623 CPU_CONTROL_1r, V4L3DSTMISS_TOCPUf, 624 NULL, 0 }, 625 { bcmSwitchTunnelErrToCpu, 1, 626 CPU_CONTROL_1r, TUNNEL_ERR_TOCPUf, 627 NULL, 0 }, 628 { bcmSwitchMartianAddrToCpu, 1, 629 CPU_CONTROL_1r, MARTIAN_ADDR_TOCPUf, 630 NULL, 0 }, 631 { bcmSwitchL3UcTtlErrToCpu, 1, 632 CPU_CONTROL_1r, L3UC_TTL_ERR_TOCPUf, 633 NULL, 0 }, 634 { bcmSwitchL3SlowpathToCpu, 1, 635 CPU_CONTROL_1r, L3_SLOWPATH_TOCPUf, 636 NULL, 0 }, 637 { bcmSwitchIpmcTtlErrToCpu, 1, 638 CPU_CONTROL_1r, IPMC_TTL_ERR_TOCPUf, 639 NULL, 0 }, 640 { bcmSwitchSampleIngressRandomSeed, 1, 641 SFLOW_ING_RAND_SEEDr, SEEDf, 642 NULL, 0 }, 643 { bcmSwitchSampleEgressRandomSeed, 1, 644 SFLOW_EGR_RAND_SEEDr, SEEDf, 645 NULL, 0 }, 646 { bcmSwitchArpReplyToCpu, 1, 647 PROTOCOL_PKT_CONTROLr, ARP_REPLY_TO_CPUf, 648 NULL, 0 }, 649 { bcmSwitchArpReplyDrop, 1, 650 PROTOCOL_PKT_CONTROLr, ARP_REPLY_DROPf, 651 NULL, 0 }, 652 { bcmSwitchArpRequestToCpu, 1, 653 PROTOCOL_PKT_CONTROLr, ARP_REQUEST_TO_CPUf, 654 NULL, 0 }, 655 { bcmSwitchArpRequestDrop, 1, 656 PROTOCOL_PKT_CONTROLr, ARP_REQUEST_DROPf, 657 NULL, 0 }, 658 { bcmSwitchNdPktToCpu, 1, 659 PROTOCOL_PKT_CONTROLr, ND_PKT_TO_CPUf, 660 NULL, 0 }, 661 { bcmSwitchNdPktDrop, 1, 662 PROTOCOL_PKT_CONTROLr, ND_PKT_DROPf, 663 NULL, 0 }, 664 { bcmSwitchDhcpPktToCpu, 1, 665 PROTOCOL_PKT_CONTROLr, DHCP_PKT_TO_CPUf, 666 NULL, 0 }, 667 { bcmSwitchDhcpPktDrop, 1, 668 PROTOCOL_PKT_CONTROLr, DHCP_PKT_DROPf, 669 NULL, 0 }, 670 { bcmSwitchDosAttackSipEqualDip, 1, 671 DOS_CONTROLr, DROP_IF_SIP_EQUALS_DIPf, 672 NULL, 0 }, 673 { bcmSwitchDosAttackV4FirstFrag, 1, 674 DOS_CONTROLr, IPV4_FIRST_FRAG_CHECK_ENABLEf, 675 NULL, 0 }, 676 { bcmSwitchNonIpL3ErrToCpu, 1, 677 CPU_CONTROL_1r, NIP_L3ERR_TOCPUf, 678 NULL, soc_feature_nip_l3_err_tocpu }, 679 { bcmSwitchSourceRouteToCpu, 1, 680 CPU_CONTROL_1r, SRCROUTE_TOCPUf, 681 NULL, 0 }, 682 { bcmSwitchParityErrorToCpu, 0, 683 CPU_CONTROL_1r, PARITY_ERR_TOCPUf, 684 NULL, soc_feature_parity_err_tocpu }, 685 { bcmSwitchDirectedMirroring, 1, 686 EGR_CONFIGr, DRACO1_5_MIRRORf, 687 _bool_invert, soc_feature_xgs1_mirror}, 688 #endif /* BCM_HELIX_SUPPORT || BCM_FIREBOLT_SUPPORT || 689 BCM_BRADLEY_SUPPORT || BCM_TRX_SUPPORT */ 690 691 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) || \ 692 defined(BCM_BRADLEY_SUPPORT) || defined(BCM_RAVEN_SUPPORT) || \ 693 defined(BCM_TRX_SUPPORT) 694 { bcmSwitchL3MtuFailToCpu, 1, 695 CPU_CONTROL_1r, L3_MTU_FAIL_TOCPUf, 696 NULL, soc_feature_l3mtu_fail_tocpu }, 697 { bcmSwitchIpmcSameVlanL3Route, 1, 698 EGR_CONFIG_1_64r, IPMC_ROUTE_SAME_VLANf, 699 NULL, soc_feature_l3}, 700 { bcmSwitchIpmcSameVlanPruning, 1, 701 MMU_SCFG_TOQ_MC_CFG0r, IPMC_IND_MODEf, 702 _bool_invert, 0 }, 703 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT || 704 BCM_BRADLEY_SUPPORT || BCM_RAVEN_SUPPORT || BCM_TRX_SUPPORT */ 705 706 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 707 { bcmSwitchPrioDropToCpu, 1, 708 CPU_CONTROL_0r, DOT1P_ADMITTANCE_DROP_TOCPUf, 709 NULL, soc_feature_niv}, 710 { bcmSwitchNivPrioDropToCpu, 1, 711 CPU_CONTROL_0r, DOT1P_ADMITTANCE_DROP_TOCPUf, 712 NULL, soc_feature_niv}, 713 #if 0 /* TD3TBD NIV_FORWARDING_DROP_TOCPUf is removed */ 714 { bcmSwitchNivInterfaceMissToCpu, 1, 715 CPU_CONTROL_0r, NIV_FORWARDING_DROP_TOCPUf, 716 NULL, soc_feature_niv}, 717 #endif 718 { bcmSwitchNivRpfFailToCpu, 1, 719 CPU_CONTROL_0r, RPF_CHECK_FAIL_TOCPUf, 720 NULL, soc_feature_niv}, 721 { bcmSwitchNivTagInvalidToCpu, 1, 722 CPU_CONTROL_0r, VNTAG_FORMAT_DROP_TOCPUf, 723 NULL, soc_feature_niv}, 724 { bcmSwitchNivTagDropToCpu, 1, 725 CPU_CONTROL_0r, DISCARD_VNTAG_PRESENT_TOCPUf, 726 NULL, soc_feature_niv}, 727 { bcmSwitchNivUntagDropToCpu, 1, 728 CPU_CONTROL_0r, DISCARD_VNTAG_NOT_PRESENT_TOCPUf, 729 NULL, soc_feature_niv}, 730 { bcmSwitchTrillTtlErrToCpu, 1, 731 CPU_CONTROL_0r, TRILL_HOPCOUNT_CHECK_FAIL_TOCPUf, 732 NULL, soc_feature_trill}, 733 { bcmSwitchTrillHeaderErrToCpu, 1, 734 CPU_CONTROL_0r, TRILL_ERROR_FRAMES_TOCPUf, 735 NULL, soc_feature_trill}, 736 { bcmSwitchTrillMismatchToCpu, 1, 737 CPU_CONTROL_0r, TRILL_UNEXPECTED_FRAMES_TOCPUf, 738 NULL, soc_feature_trill}, 739 { bcmSwitchTrillNameMissToCpu, 1, 740 CPU_CONTROL_0r, TRILL_RBRIDGE_LOOKUP_MISS_TOCPUf, 741 NULL, soc_feature_trill}, 742 { bcmSwitchTrillRpfFailToCpu, 1, 743 CPU_CONTROL_0r, TRILL_RPF_CHECK_FAIL_TOCPUf, 744 NULL, soc_feature_trill}, 745 { bcmSwitchTrillOptionsToCpu, 1, 746 CPU_CONTROL_0r, TRILL_OPTIONS_TOCPUf, 747 NULL, soc_feature_trill}, 748 { bcmSwitchTrillNameErrDrop, 1, 749 TRILL_DROP_CONTROLr, INGRESS_RBRIDGE_EQ_EGRESS_RBRIDGE_DROPf, 750 NULL, soc_feature_trill}, 751 { bcmSwitchTrillHeaderVersionErrDrop, 1, 752 TRILL_DROP_CONTROLr, TRILL_HDR_VERSION_NON_ZERO_DROPf, 753 NULL, soc_feature_trill}, 754 { bcmSwitchTrillNameMissDrop, 1, 755 TRILL_DROP_CONTROLr, UNKNOWN_INGRESS_RBRIDGE_DROPf, 756 NULL, soc_feature_trill}, 757 { bcmSwitchTrillAdjacencyFailDrop, 1, 758 TRILL_DROP_CONTROLr, TRILL_ADJACENCY_FAIL_DROPf, 759 NULL, soc_feature_trill}, 760 { bcmSwitchTrillHeaderErrDrop, 1, 761 TRILL_DROP_CONTROLr, UC_TRILL_HDR_MC_MACDA_DROPf, 762 NULL, soc_feature_trill}, 763 { bcmSwitchTrillRpfFailDrop, 1, 764 TRILL_DROP_CONTROLr, RPF_CHECK_FAIL_DROPf, 765 NULL, soc_feature_trill}, 766 { bcmSwitchIngParseL2TunnelTermDipSipSelect, 1, 767 ING_L2_TUNNEL_PARSE_CONTROLr, IFP_L2_TUNNEL_PAYLOAD_FIELD_SELf , 768 NULL, 0}, 769 { bcmSwitchIngParseL3L4IPv4, 1, 770 ING_L2_TUNNEL_PARSE_CONTROLr, IGMP_ENABLEf , 771 NULL, 0}, 772 { bcmSwitchIngParseL3L4IPv6, 1, 773 ING_L2_TUNNEL_PARSE_CONTROLr, MLD_ENABLEf , 774 NULL, 0}, 775 { bcmSwitchV6L3LocalLinkDrop, 1, 776 ING_MISC_CONFIG2r, IPV6_SIP_LINK_LOCAL_DROPf, 777 NULL, 0}, 778 /* This switch control is valid for TD+ only. 779 * 'soc_feature_l3_ecmp_1k_groups' is used to 780 * distinguish between TD and TD+ */ 781 { bcmSwitchEcmpMacroFlowHashEnable, 0, 782 ING_CONFIG_2r, ECMP_HASH_16BITSf, 783 NULL, soc_feature_l3_ecmp_1k_groups }, 784 #endif /* BCM_TRIDENT_SUPPORT || BCM_KATANA_SUPPORT || BCM_KATANA2_SUPPORT*/ 785 786 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_PE_SUPPORT) 787 #if 0 /* TD3TBD NIV_FORWARDING_DROP_TOCPUf is removed */ 788 { bcmSwitchExtenderInterfaceMissToCpu, 1, 789 CPU_CONTROL_0r, NIV_FORWARDING_DROP_TOCPUf, 790 NULL, soc_feature_port_extension}, 791 #endif 792 { bcmSwitchExtenderRpfFailToCpu, 1, 793 CPU_CONTROL_0r, RPF_CHECK_FAIL_TOCPUf, 794 NULL, soc_feature_port_extension}, 795 { bcmSwitchEtagInvalidToCpu, 1, 796 CPU_CONTROL_0r, VNTAG_FORMAT_DROP_TOCPUf, 797 NULL, soc_feature_port_extension}, 798 { bcmSwitchEtagDropToCpu, 1, 799 CPU_CONTROL_0r, DISCARD_VNTAG_PRESENT_TOCPUf, 800 NULL, soc_feature_port_extension}, 801 { bcmSwitchNonEtagDropToCpu, 1, 802 CPU_CONTROL_0r, DISCARD_VNTAG_NOT_PRESENT_TOCPUf, 803 NULL, soc_feature_port_extension}, 804 { bcmSwitchMplsGalAlertLabelToCpu, 1, 805 CPU_CONTROL_Mr, MPLS_GAL_EXPOSED_TO_CPUf, 806 NULL, 0}, 807 { bcmSwitchMplsRalAlertLabelToCpu, 1, 808 CPU_CONTROL_Mr, MPLS_RAL_EXPOSED_TO_CPUf, 809 NULL, 0}, 810 { bcmSwitchMplsIllegalReservedLabelToCpu, 1, 811 CPU_CONTROL_Mr, MPLS_ILLEGAL_RSVD_LABEL_TO_CPUf, 812 NULL, 0}, 813 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_TRIDENT2_SUPPORT || BCM_PE_SUPPORT */ 814 815 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 816 { bcmSwitchMplsUnknownAchTypeToCpu, 1, 817 CPU_CONTROL_Mr, MPLS_UNKNOWN_ACH_TYPE_TO_CPUf, 818 NULL, 0}, 819 { bcmSwitchMplsUnknownAchVersionToCpu, 1, 820 CPU_CONTROL_Mr, MPLS_UNKNOWN_ACH_VERSION_TOCPUf, 821 NULL, 0}, 822 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_TRIDENT2_SUPPORT */ 823 824 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 825 { bcmSwitchFailoverDropToCpu, 1, 826 CPU_CONTROL_1r, PROTECTION_DATA_DROP_TOCPUf, 827 NULL, 0}, 828 { bcmSwitchMplsReservedEntropyLabelToCpu, 0, 829 CPU_CONTROL_Mr, ENTROPY_LABEL_IN_0_15_RANGE_TO_CPUf, 830 NULL, 0}, 831 { bcmSwitchL3SrcBindMissToCpu, 1, 832 CPU_CONTROL_Mr, MAC_IP_BIND_LOOKUP_MISS_TOCPUf, 833 NULL, 0}, 834 { bcmSwitchMplsLookupsExceededToCpu, 0, 835 CPU_CONTROL_Mr, MPLS_OUT_OF_LOOKUPS_TOCPUf, 836 NULL, 0}, 837 { bcmSwitchTimesyncUnknownVersionToCpu, 1, 838 CPU_CONTROL_Mr, UNKNOWN_1588_VERSION_TO_CPUf, 839 NULL, 0}, 840 { bcmSwitchTimesyncIngressVersion, 1, 841 ING_1588_PARSING_CONTROLr, VERSION_CONTROLf, 842 NULL, 0}, 843 { bcmSwitchTimesyncEgressVersion, 1, 844 EGR_1588_PARSING_CONTROLr, VERSION_CONTROLf, 845 NULL, 0}, 846 { bcmSwitchCongestionCnmToCpu, 1, 847 IE2E_CONTROLr, ICNM_TO_CPUf, 848 NULL, 0}, 849 { bcmSwtichCongestionCnmProxyErrorToCpu, 1, 850 ING_MISC_CONFIGr, QCN_CNM_PRP_DLF_TO_CPUf, 851 NULL, 0}, 852 { bcmSwtichCongestionCnmProxyToCpu, 1, 853 ING_MISC_CONFIGr, QCN_CNM_PRP_TO_CPUf, 854 NULL, 0}, 855 { bcmSwitchL2GreTunnelMissToCpu, 1, 856 CPU_CONTROL_Mr, L2GRE_SIP_LOOKUP_FAIL_COPY_TOCPUf, 857 NULL, 0}, 858 { bcmSwitchL2GreVpnIdMissToCpu, 1, 859 CPU_CONTROL_Mr, L2GRE_VPNID_LOOKUP_FAIL_COPY_TOCPUf, 860 NULL, 0}, 861 { bcmSwitchWlanTunnelErrorDrop, 0, 862 ING_CONFIG_64r, WLAN_DECRYPT_OFFLOAD_ENABLEf, 863 _bool_invert, 0}, 864 { bcmSwitchMplsReservedEntropyLabelDrop, 0, 865 DROP_CONTROL_0r, ENTROPY_LABEL_IN_0_15_RANGE_DO_NOT_DROPf, 866 _bool_invert, 0}, 867 { bcmSwitchRemoteProtectionTrust, 1, 868 ING_CONFIG_64r, USE_PROT_STATUSf, 869 NULL, 0}, 870 { bcmSwitchVxlanTunnelMissToCpu, 1, 871 CPU_CONTROL_Mr, VXLAN_SIP_LOOKUP_FAIL_COPY_TOCPUf, 872 NULL, 0}, 873 { bcmSwitchVxlanVnIdMissToCpu, 1, 874 CPU_CONTROL_Mr, VXLAN_VN_ID_LOOKUP_FAIL_COPY_TOCPUf, 875 NULL, 0}, 876 { bcmSwitchHashL2GreKeyMask0, 1, 877 RTAG7_HASH_CONTROL_L2GRE_MASK_Ar, L2GRE_TUNNEL_GRE_KEY_MASK_Af, 878 NULL, soc_feature_l2gre}, 879 { bcmSwitchHashL2GreKeyMask1, 1, 880 RTAG7_HASH_CONTROL_L2GRE_MASK_Br, L2GRE_TUNNEL_GRE_KEY_MASK_Bf, 881 NULL, soc_feature_l2gre}, 882 { bcmSwitchRemoteProtectionEnable, 1 , 883 EGR_HG_HDR_PROT_STATUS_TX_CONTROLr, SET_PROT_STATUSf, 884 NULL, 0}, 885 886 #endif /* BCM_TRIUMPH3_SUPPORT */ 887 #if defined(BCM_TRIDENT2_SUPPORT) 888 { bcmSwitchL3NATEnable, 1, 889 ING_CONFIG_64r, NAT_ENABLEf, 890 NULL, 0}, 891 { bcmSwitchL3DNATHairpinToCpu, 1, 892 CPU_CONTROL_Mr, DNAT_HAIRPIN_COPY_TOCPUf, 893 NULL, 0}, 894 { bcmSwitchL3DNATMissToCpu, 1, 895 CPU_CONTROL_Mr, DNAT_MISS_COPY_TOCPUf, 896 NULL, 0}, 897 { bcmSwitchL3SNATMissToCpu, 1, 898 CPU_CONTROL_Mr, SNAT_MISS_COPY_TOCPUf, 899 NULL, 0}, 900 { bcmSwitchL3NatOtherToCpu, 1, 901 CPU_CONTROL_Mr, NAT_OTHER_COPY_TOCPUf, 902 NULL, 0}, 903 { bcmSwitchL3NatRealmCrossingIcmpToCpu, 1, 904 CPU_CONTROL_Mr, NAT_REALM_CROSSING_ICMP_COPY_TOCPUf, 905 NULL, 0}, 906 { bcmSwitchL3NatFragmentsToCpu, 1, 907 CPU_CONTROL_Mr, NAT_FRAGMENTS_COPY_TOCPUf, 908 NULL, 0}, 909 { bcmSwitchHashUseL2GreTunnelGreKey0, 1, 910 RTAG7_HASH_CONTROL_2r, L2GRE_TUNNEL_USE_GRE_KEY_Af, 911 NULL, soc_feature_l2gre}, 912 { bcmSwitchHashUseL2GreTunnelGreKey1, 1, 913 RTAG7_HASH_CONTROL_2r, L2GRE_TUNNEL_USE_GRE_KEY_Bf, 914 NULL, soc_feature_l2gre}, 915 { bcmSwitchHashL2GrePayloadSelect0, 1, 916 RTAG7_HASH_CONTROL_2r, L2GRE_PAYLOAD_HASH_SELECT_Af, 917 NULL, soc_feature_l2gre}, 918 { bcmSwitchHashL2GrePayloadSelect1, 1, 919 RTAG7_HASH_CONTROL_2r, L2GRE_PAYLOAD_HASH_SELECT_Bf, 920 NULL, soc_feature_l2gre}, 921 { bcmSwitchHashL2GreNetworkPortPayloadDisable0, 1, 922 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_L2GRE_Af, 923 NULL, soc_feature_l2gre}, 924 { bcmSwitchHashL2GreNetworkPortPayloadDisable1, 1, 925 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_L2GRE_Bf, 926 NULL, soc_feature_l2gre}, 927 { bcmSwitchEcmpMacroFlowHashEnable, 1, 928 RTAG7_HASH_SELr, USE_FLOW_SEL_ECMPf, 929 NULL, 0}, 930 { bcmSwitchMcQueueSchedMode, 1, 931 HSP_SCHED_PORT_CONFIGr, MC_GROUP_MODEf, 932 NULL, 0}, 933 #endif /* BCM_TRIDENT2_SUPPORT */ 934 935 #if defined(BCM_TRIDENT_SUPPORT) 936 { bcmSwitchHashField0Ip6FlowLabel, 1, 937 RTAG7_HASH_CONTROL_2r, ENABLE_FLOW_LABEL_IPV6_Af, 938 NULL, 0}, 939 { bcmSwitchHashField1Ip6FlowLabel, 1, 940 RTAG7_HASH_CONTROL_2r, ENABLE_FLOW_LABEL_IPV6_Bf, 941 NULL, 0}, 942 { bcmSwitchMacroFlowHashUseMSB, 1, 943 RTAG7_HASH_CONTROL_2r, MACRO_FLOW_HASH_BYTE_SELf, 944 NULL, 0}, 945 #endif 946 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_KATANA_SUPPORT) 947 { bcmSwitchHashHg2PktFieldsEnable, 1, 948 RTAG7_HASH_CONTROL_2r, TREAT_PPD2_AS_KNOWN_PPDf, 949 NULL, 0}, 950 { bcmSwitchHashField0OverlayCntagRpidEnable, 1, 951 RTAG7_HASH_CONTROL_2r, ENABLE_BIN_12_OVERLAY_Af, 952 NULL, 0}, 953 { bcmSwitchMimPayloadTpidEnable, 1, 954 RTAG7_HASH_CONTROL_2r, MIM_PAYLOAD_TPID_ENABLEf, 955 NULL, soc_feature_mim}, 956 { bcmSwitchHashMimUseTunnelHeader0, 1, 957 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_MIM_INNER_L2_Af, 958 NULL, soc_feature_mim}, 959 { bcmSwitchHashMimUseTunnelHeader1, 1, 960 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_MIM_INNER_L2_Bf, 961 NULL, soc_feature_mim}, 962 { bcmSwitchHashField1OverlayCntagRpidEnable, 1, 963 RTAG7_HASH_CONTROL_2r, ENABLE_BIN_12_OVERLAY_Bf, 964 NULL, 0}, 965 { bcmSwitchHashMPLSUseLabelStack, 0, 966 RTAG7_HASH_CONTROL_2r, USE_MPLS_STACK_FOR_HASHINGf, 967 NULL, 0}, 968 { bcmSwitchHashUseFlowSelTrunkUc , 1, 969 RTAG7_HASH_SELr, USE_FLOW_SEL_TRUNK_UCf, 970 NULL, 0}, 971 { bcmSwitchHashUseFlowSelTrunkNonUnicast , 1, 972 RTAG7_HASH_SELr, USE_FLOW_SEL_TRUNK_NONUCf, 973 NULL, 0}, 974 { bcmSwitchHashUseFlowSelEcmp, 1, 975 RTAG7_HASH_SELr, USE_FLOW_SEL_ECMPf, 976 NULL, 0}, 977 #endif 978 #if defined(BCM_TRIDENT_SUPPORT) 979 { bcmSwitchMplsPortIndependentLowerRange1, 1, 980 GLOBAL_MPLS_RANGE_1_LOWERr, LABELf, 981 NULL, 0}, 982 { bcmSwitchMplsPortIndependentUpperRange1, 1, 983 GLOBAL_MPLS_RANGE_1_UPPERr, LABELf, 984 NULL, 0}, 985 { bcmSwitchMplsPortIndependentLowerRange2, 1, 986 GLOBAL_MPLS_RANGE_2_LOWERr, LABELf, 987 NULL, 0}, 988 { bcmSwitchMplsPortIndependentUpperRange2, 1, 989 GLOBAL_MPLS_RANGE_2_UPPERr, LABELf, 990 NULL, 0}, 991 #endif 992 { bcmSwitchHashUseFlowSelMplsEcmp, 1, 993 RTAG7_HASH_SELr, USE_FLOW_SEL_MPLS_ECMPf, 994 NULL, 0}, 995 { bcmSwitchHashMPLSUseLabelStack, 1, 996 RTAG7_HASH_CONTROLr, USE_MPLS_STACK_FOR_HASHINGf, 997 NULL, 0}, 998 #if defined(BCM_TRIDENT3_SUPPORT) 999 { bcmSwitchMplsCtrlPktToCpu, 1, 1000 CPU_CONTROL_Mr, MPLS_CONTROL_PKT_TO_CPUf, 1001 NULL, 0}, 1002 { bcmSwitchInvalidTpidToCpu, 1, 1003 CPU_CONTROL_1r, INVALID_TPID_TO_CPUf, 1004 NULL, 0}, 1005 { bcmSwitchFlowSelectMissToCpu, 1, 1006 CPU_CONTROL_1r, PKT_FLOW_SELECT_MISS_TO_CPUf, 1007 NULL, 0}, 1008 { bcmSwitchL3HdrMismatchToCpu, 1, 1009 CPU_CONTROL_1r, NON_L3_FLOW_TO_CPUf, 1010 NULL, 0}, 1011 { bcmSwitchIngParseL2TunnelTermArp, 1, ING_L2_TUNNEL_PARSE_CONTROLr, 1012 PARSE_ARP_PAYLOADf, NULL, 0}, 1013 { bcmSwitchIngParseL2TunnelTermRarp, 1, ING_L2_TUNNEL_PARSE_CONTROLr, 1014 PARSE_RARP_PAYLOADf, NULL, 0}, 1015 { bcmSwitchGpeUdpDestPortSet, 1, GPE_CONTROLr, 1016 UDP_DEST_PORTf, NULL, soc_feature_flex_flow}, 1017 { bcmSwitchGeneveUdpDestPortSet, 1, GENEVE_CONTROLr, 1018 UDP_DEST_PORTf, NULL, soc_feature_flex_flow}, 1019 { bcmSwitchGpeEntropyEnable, 1, EGR_GPE_CONTROLr, 1020 UDP_SOURCE_PORT_SELf, NULL, soc_feature_flex_flow}, 1021 { bcmSwitchGeneveEntropyEnable, 1, EGR_GENEVE_CONTROLr, 1022 UDP_SOURCE_PORT_SELf, NULL, soc_feature_flex_flow}, 1023 { bcmSwitchL3UcLargeNATEnable, 1, 1024 LARGE_SCALE_NAT_CONTROLr, L3UC_NAT_ENABLEf, 1025 NULL, soc_feature_large_scale_nat}, 1026 { bcmSwitchL3McLargeNATEnable, 1, 1027 LARGE_SCALE_NAT_CONTROLr, L3MC_NAT_ENABLEf, 1028 NULL, soc_feature_large_scale_nat}, 1029 { bcmSwitchL2ChangeFieldsEnable, 1, 1030 EGR_FLEX_CONFIGr, ENABLE_CHANGE_L2_FIELDSf, 1031 NULL, soc_feature_vfi_switched_l2_change_fields}, 1032 #endif 1033 #if defined(BCM_HELIX5_SUPPORT) 1034 { bcmSwitchDosAttackTcpFirstOption, 1, 1035 PARSER1_HVE_TCP_PARSE_CONTROLr, TCP_TLV_TYPEf, 1036 NULL, soc_feature_broadscan_dos_ctrl}, 1037 { bcmSwitchDosAttackInnerTcpFirstOption, 1, 1038 PARSER2_HVE_TCP_PARSE_CONTROLr, TCP_TLV_TYPEf, 1039 NULL, soc_feature_broadscan_dos_ctrl}, 1040 { bcmSwitchDosAttackTcpFlagsMask, 1, 1041 PARSER1_HVE_TCP_PARSE_CONTROLr, TCP_FLAG_MASKf, 1042 NULL, soc_feature_broadscan_dos_ctrl}, 1043 { bcmSwitchDosAttackInnerTcpFlagsMask, 1, 1044 PARSER2_HVE_TCP_PARSE_CONTROLr, TCP_FLAG_MASKf, 1045 NULL, soc_feature_broadscan_dos_ctrl}, 1046 { bcmSwitchDosAttackTcpFlagsSR, 1, 1047 DOS_CONTROL_3r, TCP_SYN_RST_CHECKf, 1048 NULL, soc_feature_broadscan_dos_ctrl}, 1049 { bcmSwitchDosAttackTcpFlagsZero, 1, 1050 DOS_CONTROL_3r, TCP_FLAG_ZERO_CHECKf, 1051 NULL, soc_feature_broadscan_dos_ctrl}, 1052 { bcmSwitchDosAttackTcpFlagsSynOption, 1, 1053 DOS_CONTROL_3r, TCP_SYN_WITH_DATA_PAYLOAD_CHECKf, 1054 NULL, soc_feature_broadscan_dos_ctrl}, 1055 { bcmSwitchDosAttackTcpFlagsSynFirstFrag, 1, 1056 DOS_CONTROL_3r, TCP_SYN_FIRST_FRAGMENT_CHECKf, 1057 NULL, soc_feature_broadscan_dos_ctrl}, 1058 { bcmSwitchDosAttackTcpFlagsFinNoAck, 1, 1059 DOS_CONTROL_3r, TCP_FIN_NO_ACK_CHECKf, 1060 NULL, soc_feature_broadscan_dos_ctrl}, 1061 { bcmSwitchDosAttackTcpFlagsRstNoAck, 1, 1062 DOS_CONTROL_3r, TCP_RST_NO_ACK_CHECKf, 1063 NULL, soc_feature_broadscan_dos_ctrl}, 1064 { bcmSwitchDosAttackTcpFlagsNoSFRA, 1, 1065 DOS_CONTROL_3r, TCP_NO_SYN_FIN_RST_ACK_CHECKf, 1066 NULL, soc_feature_broadscan_dos_ctrl}, 1067 { bcmSwitchDosAttackTcpFlagsUrgNoUrgPtr, 1, 1068 DOS_CONTROL_3r, TCP_URG_NO_URG_POINTER_CHECKf, 1069 NULL, soc_feature_broadscan_dos_ctrl}, 1070 { bcmSwitchDosAttackTcpFlagsNoUrgWithUrgPtr, 1, 1071 DOS_CONTROL_3r, TCP_NO_URG_URG_POINTER_CHECKf, 1072 NULL, soc_feature_broadscan_dos_ctrl}, 1073 { bcmSwitchDosAttackTcpDstPortZero, 1, 1074 DOS_CONTROL_3r, TCP_DPORT_ZERO_CHECKf, 1075 NULL, soc_feature_broadscan_dos_ctrl}, 1076 { bcmSwitchDosAttackTcpSrcPortZero, 1, 1077 DOS_CONTROL_3r, TCP_SPORT_ZERO_CHECKf, 1078 NULL, soc_feature_broadscan_dos_ctrl}, 1079 { bcmSwitchDosAttackTcpFlagsResvdNonZero, 1, 1080 DOS_CONTROL_3r, TCP_RESERVED_NON_ZERO_CHECKf, 1081 NULL, soc_feature_broadscan_dos_ctrl}, 1082 { bcmSwitchDosAttackTcpV4DstBcast, 1, 1083 DOS_CONTROL_3r, TCP_IP_BROADCAST_CHECKf, 1084 NULL, soc_feature_broadscan_dos_ctrl}, 1085 { bcmSwitchDosAttackTcpFlagsAck, 1, 1086 DOS_CONTROL_3r, TCP_ACK_ACKNUMBER_ZERO_CHECKf, 1087 NULL, soc_feature_broadscan_dos_ctrl}, 1088 #endif 1089 }; 1090 1091 int 1092 _bcm_td3_switch_control_port_binding_set(int unit, 1093 bcm_port_t port, 1094 bcm_switch_control_t type, 1095 int arg, int *found) 1096 { 1097 uint64 oval64, val64; 1098 int i; 1099 bcm_switch_binding_t *b; 1100 uint32 max; 1101 int fval, fwidth, prt, idx; 1102 1103 *found = 0; 1104 1105 for (i = 0; i < COUNTOF(trident3_bindings); i++) { 1106 b = &trident3_bindings[i]; 1107 /* b->chip == 1 check will be removed after we done bringup and final clean up */ 1108 if ((b->type == type) && (b->chip == 1)) { 1109 /* We don't check the b->chip here since the table is specific for Greyhound*/ 1110 if (b->feature && !soc_feature(unit, b->feature)) { 1111 continue; 1112 } 1113 if (!soc_reg_field_valid(unit, b->reg, b->field)) { 1114 continue; 1115 } 1116 if (b->xlate_arg) { 1117 if ((fval = (b->xlate_arg)(unit, arg, 1)) < 0) { 1118 return fval; 1119 } 1120 } else { 1121 fval = arg; 1122 } 1123 /* Negative values should be treated as errors */ 1124 if (fval < 0) { 1125 return BCM_E_PARAM; 1126 } 1127 if ((b->reg == PROTOCOL_PKT_CONTROLr) || 1128 (b->reg == IGMP_MLD_PKT_CONTROLr)) { 1129 int index; 1130 1131 BCM_IF_ERROR_RETURN 1132 (_bcm_esw_port_tab_get(unit, port, 1133 PROTOCOL_PKT_INDEXf, &index)); 1134 prt = port; 1135 idx = index; 1136 } else { 1137 prt = port; 1138 idx = 0; 1139 } 1140 1141 fwidth = soc_reg_field_length(unit, b->reg, b->field); 1142 if (fwidth < 32) { 1143 max = (1 << fwidth) - 1; 1144 } else { 1145 max = -1; 1146 } 1147 SOC_IF_ERROR_RETURN(soc_reg_get(unit, b->reg, prt, idx, &val64)); 1148 oval64 = val64; 1149 soc_reg64_field32_set(unit, b->reg, &val64, b->field, 1150 ((uint32)fval > max) ? max : (uint32)fval); 1151 if (COMPILER_64_NE(val64, oval64)) { 1152 SOC_IF_ERROR_RETURN(soc_reg_set(unit, b->reg, prt, idx, val64)); 1153 } 1154 1155 if (type == bcmSwitchSharedVlanEnable) { 1156 BCM_IF_ERROR_RETURN(_bcm_td3_vlan_shared_vlan_enable_set(unit, arg)); 1157 } 1158 1159 *found = 1; 1160 break; 1161 } 1162 } 1163 return BCM_E_NONE; 1164 } 1165 1166 int 1167 _bcm_td3_switch_control_port_binding_get(int unit, 1168 bcm_port_t port, 1169 bcm_switch_control_t type, 1170 int *arg, int *found) 1171 { 1172 uint64 val64; 1173 int i; 1174 bcm_switch_binding_t *b; 1175 int prt, idx; 1176 1177 *found = 0; 1178 1179 for (i = 0; i < COUNTOF(trident3_bindings); i++) { 1180 b = &trident3_bindings[i]; 1181 /* b->chip == 1 check will be removed after we done bringup and final clean up */ 1182 if ((b->type == type) && (b->chip == 1)) { 1183 if (b->feature && !soc_feature(unit, b->feature)) { 1184 continue; 1185 } 1186 if (!SOC_REG_IS_VALID(unit, b->reg)) { 1187 continue; 1188 } 1189 1190 if (!soc_reg_field_valid(unit, b->reg, b->field)) { 1191 continue; 1192 } 1193 if ((b->reg == PROTOCOL_PKT_CONTROLr) || 1194 (b->reg == IGMP_MLD_PKT_CONTROLr)) { 1195 int index; 1196 1197 BCM_IF_ERROR_RETURN 1198 (_bcm_esw_port_tab_get(unit, port, 1199 PROTOCOL_PKT_INDEXf, &index)); 1200 prt = port; 1201 idx = index; 1202 } else { 1203 prt = port; 1204 idx = 0; 1205 } 1206 1207 if (type == bcmSwitchSharedVlanEnable) { 1208 BCM_IF_ERROR_RETURN(_bcm_td3_vlan_shared_vlan_enable_get(unit, arg)); 1209 } else { 1210 SOC_IF_ERROR_RETURN(soc_reg_get(unit, b->reg, prt, idx, &val64)); 1211 *arg = soc_reg64_field32_get(unit, b->reg, val64, b->field); 1212 } 1213 1214 if (b->xlate_arg) { 1215 *arg = (b->xlate_arg)(unit, *arg, 0); 1216 } 1217 *found = 1; 1218 break; 1219 } 1220 } 1221 return BCM_E_NONE; 1222 } 1223 1224 /* Indexing of the memories EGR_SHAPING_CONTROL & EGR_COUNTER_CONTROL: 1225 * 3-bit EGR_LPORT_PROFILE.IFG_PROFILE_INDEX,5-bit IFG byte_cnt/l2 header offset 1226 * from Editor 1227 */ 1228 STATIC int 1229 _bcm_td3_meter_index_get(int unit, bcm_port_t port, int *index) 1230 { 1231 egr_lport_profile_entry_t egr_lport_profile_entry; 1232 uint32 ifg_profile_index; 1233 egr_port_entry_t egr_port_entry; 1234 int port_type, hdr_offset; 1235 1236 SOC_IF_ERROR_RETURN( 1237 READ_EGR_LPORT_PROFILEm(unit, MEM_BLOCK_ANY, port, 1238 &egr_lport_profile_entry)); 1239 ifg_profile_index = soc_EGR_LPORT_PROFILEm_field32_get(unit, 1240 &egr_lport_profile_entry, IFG_PROFILE_INDEXf); 1241 SOC_IF_ERROR_RETURN( 1242 READ_EGR_PORTm(unit, MEM_BLOCK_ANY, port, &egr_port_entry)); 1243 port_type = soc_mem_field32_get(unit, EGR_PORTm, &egr_port_entry, 1244 PORT_TYPEf); 1245 1246 if (port_type == 0) { 1247 /* Ethernet */ 1248 *index = ifg_profile_index << 5; 1249 } else if (port_type == 1) { 1250 /* Higig */ 1251 hdr_offset = 8; 1252 if ((soc_EGR_LPORT_PROFILEm_field32_get(unit, 1253 &egr_lport_profile_entry, EH_EXT_HDR_ENABLEf)) == 1) { 1254 /* HG + EXT */ 1255 hdr_offset = 10; 1256 } 1257 *index = (ifg_profile_index << 5) | hdr_offset; 1258 } 1259 1260 return BCM_E_NONE; 1261 } 1262 1263 /* 1264 * Update following registers/memories, field 1265 * EGR_COUNTER_CONTROLm, PACKET_IFG_BYTESf 1266 * EGR_SHAPING_CONTROLm, PACKET_IFG_BYTESf 1267 * IFP_METER_CONTROLr, PACKET_IFG_BYTESf 1268 */ 1269 int 1270 _bcm_td3_meter_adjust_set(int unit, bcm_port_t port, int arg) 1271 { 1272 int len, max_val; 1273 int i, index = 0; 1274 soc_mem_t mem[2] = { EGR_COUNTER_CONTROLm, 1275 EGR_SHAPING_CONTROLm }; 1276 1277 if (!soc_feature(unit, soc_feature_meter_adjust)) { 1278 return BCM_E_UNAVAIL; 1279 } 1280 1281 BCM_IF_ERROR_RETURN(_bcm_td3_meter_index_get(unit, port, &index)); 1282 1283 for (i = 0; i < 2 ; ++i ) { 1284 len = soc_mem_field_length(unit, mem[i], PACKET_IFG_BYTESf); 1285 max_val = (1 << len) - 1; 1286 if (arg < 0 || arg > max_val) { 1287 return BCM_E_PARAM; 1288 } 1289 1290 SOC_IF_ERROR_RETURN( 1291 soc_mem_field32_modify(unit, mem[i], index, PACKET_IFG_BYTESf, 1292 arg)); 1293 } 1294 1295 len = soc_reg_field_length(unit, IFP_METER_CONTROLr, PACKET_IFG_BYTESf); 1296 max_val = (1 << len) - 1; 1297 if (arg < 0 || arg > max_val) { 1298 return BCM_E_PARAM; 1299 } 1300 SOC_IF_ERROR_RETURN( 1301 soc_reg_field32_modify(unit, IFP_METER_CONTROLr, port, 1302 PACKET_IFG_BYTESf, arg)); 1303 1304 return BCM_E_NONE; 1305 } 1306 1307 int 1308 _bcm_td3_meter_adjust_get(int unit, bcm_port_t port, int *arg) 1309 { 1310 uint32 val; 1311 int index = 0; 1312 1313 BCM_IF_ERROR_RETURN(_bcm_td3_meter_index_get(unit, port, &index)); 1314 1315 SOC_IF_ERROR_RETURN( 1316 READ_EGR_COUNTER_CONTROLm(unit, MEM_BLOCK_ANY, index, &val)); 1317 *arg = soc_mem_field32_get(unit, EGR_COUNTER_CONTROLm, &val, 1318 PACKET_IFG_BYTESf); 1319 1320 return BCM_E_NONE; 1321 } 1322 1323 int 1324 _bcm_td3_shaper_adjust_set(int unit, bcm_port_t port, int arg) 1325 { 1326 int index = 0; 1327 int len, max_val; 1328 soc_mem_t mem = EGR_SHAPING_CONTROLm; 1329 1330 BCM_IF_ERROR_RETURN(_bcm_td3_meter_index_get(unit, port, &index)); 1331 1332 len = soc_mem_field_length(unit, mem, PACKET_IFG_BYTESf); 1333 max_val = (1 << len) - 1; 1334 if (arg < 0 || arg > max_val) { 1335 return BCM_E_PARAM; 1336 } 1337 1338 SOC_IF_ERROR_RETURN( 1339 soc_mem_field32_modify(unit, mem, index, PACKET_IFG_BYTESf, arg)); 1340 1341 return BCM_E_NONE; 1342 } 1343 1344 int 1345 _bcm_td3_shaper_adjust_get(int unit, bcm_port_t port, int *arg) 1346 { 1347 uint32 val; 1348 int index = 0; 1349 1350 BCM_IF_ERROR_RETURN(_bcm_td3_meter_index_get(unit, port, &index)); 1351 1352 SOC_IF_ERROR_RETURN( 1353 READ_EGR_SHAPING_CONTROLm(unit, MEM_BLOCK_ANY, index, &val)); 1354 *arg = soc_mem_field32_get(unit, EGR_SHAPING_CONTROLm, &val, 1355 PACKET_IFG_BYTESf); 1356 1357 return BCM_E_NONE; 1358 } 1359 1360 int 1361 _bcm_td3_dosattack_pkt_size_set(int unit, bcm_switch_control_t type, int arg) 1362 { 1363 int i = 0; 1364 int num_entries = 0; 1365 uint64 val64; 1366 uint32 val32; 1367 soc_reg_t reg[2]; 1368 soc_field_t field[2]; 1369 1370 if (arg <= 0) { 1371 return BCM_E_PARAM; 1372 } 1373 switch(type) { 1374 case bcmSwitchDosAttackIcmpPktOversize: 1375 reg[0] = PARSER1_DOS_CONTROL_3r; 1376 field[0] = BIG_ICMP_PKT_SIZEf; 1377 reg[1] = PARSER2_DOS_CONTROL_3r; 1378 field[1] = BIG_ICMP_PKT_SIZEf; 1379 num_entries = 2; 1380 break; 1381 case bcmSwitchDosAttackMinTcpHdrSize: 1382 reg[0] = PARSER1_DOS_CONTROL_3r; 1383 field[0] = MIN_TCPHDR_SIZEf; 1384 reg[1] = PARSER2_DOS_CONTROL_3r; 1385 field[1] = MIN_TCPHDR_SIZEf; 1386 num_entries = 2; 1387 break; 1388 case bcmSwitchDosAttackIcmpV6PingSize: 1389 reg[0] = PARSER1_DOS_CONTROL_3r; 1390 field[0] = BIG_ICMPV6_PKT_SIZEf; 1391 reg[1] = PARSER2_DOS_CONTROL_3r; 1392 field[1] = BIG_ICMPV6_PKT_SIZEf; 1393 num_entries = 2; 1394 break; 1395 case bcmSwitchDosAttackV6MinFragSize: 1396 reg[0] = PARSER1_IPV6_MIN_FRAG_SIZEr; 1397 field[0] = PKT_LENGTHf; 1398 reg[1] = PARSER2_IPV6_MIN_FRAG_SIZEr; 1399 field[1] = PKT_LENGTHf; 1400 num_entries = 2; 1401 break; 1402 default: 1403 return (BCM_E_UNAVAIL); 1404 } 1405 1406 for (i = 0; i < num_entries; i++) { 1407 if(SOC_REG_IS_VALID(unit, reg[i])) { 1408 COMPILER_64_ZERO(val64); 1409 SOC_IF_ERROR_RETURN(soc_reg_get(unit, 1410 reg[i], REG_PORT_ANY, 0, &val64)); 1411 val32 = arg; 1412 soc_reg64_field32_set(unit, reg[i], &val64, 1413 field[i], val32); 1414 SOC_IF_ERROR_RETURN(soc_reg_set(unit, 1415 reg[i], REG_PORT_ANY, 0, val64)); 1416 } 1417 } 1418 1419 return BCM_E_NONE; 1420 } 1421 1422 int 1423 _bcm_td3_dosattack_pkt_size_get(int unit, bcm_switch_control_t type, int *arg) 1424 { 1425 uint32 val32; 1426 uint64 val64; 1427 soc_reg_t reg; 1428 soc_field_t field; 1429 1430 switch(type) { 1431 case bcmSwitchDosAttackIcmpPktOversize: 1432 reg = PARSER1_DOS_CONTROL_3r; 1433 field = BIG_ICMP_PKT_SIZEf; 1434 break; 1435 case bcmSwitchDosAttackMinTcpHdrSize: 1436 reg = PARSER1_DOS_CONTROL_3r; 1437 field = MIN_TCPHDR_SIZEf; 1438 break; 1439 case bcmSwitchDosAttackIcmpV6PingSize: 1440 reg = PARSER1_DOS_CONTROL_3r; 1441 field = BIG_ICMPV6_PKT_SIZEf; 1442 break; 1443 case bcmSwitchDosAttackV6MinFragSize: 1444 reg = PARSER1_IPV6_MIN_FRAG_SIZEr; 1445 field = PKT_LENGTHf; 1446 break; 1447 default: 1448 return (BCM_E_UNAVAIL); 1449 } 1450 if(SOC_REG_IS_VALID(unit, reg)) { 1451 COMPILER_64_ZERO(val64); 1452 SOC_IF_ERROR_RETURN(soc_reg_get(unit, 1453 reg, REG_PORT_ANY, 0, &val64)); 1454 val32 = soc_reg64_field32_get(unit, 1455 reg, val64, field); 1456 *arg = val32; 1457 } 1458 1459 return BCM_E_NONE; 1460 } 1461 1462 /* 1463 * Function: 1464 * _bcm_td3_gbp_ethertype_set 1465 * Description: 1466 * Set the ethertype for GBP 1467 * Parameters: 1468 * unit - unit number 1469 * arg - argument to set as Ethertype 1470 * Returns: 1471 * BCM_E_xxxx 1472 */ 1473 int 1474 _bcm_td3_gbp_ethertype_set(int unit, int arg) 1475 { 1476 uint32 rval; 1477 1478 if (arg < 0 || arg > 0xffff) { 1479 return BCM_E_PARAM; 1480 } 1481 1482 BCM_IF_ERROR_RETURN(READ_ING_GBP_ETHERTYPEr(unit, &rval)); 1483 /* Enable and Set ING GBP ethertype for parsing */ 1484 soc_reg_field_set(unit, ING_GBP_ETHERTYPEr, &rval, ENABLEf, 1); 1485 soc_reg_field_set(unit, ING_GBP_ETHERTYPEr, &rval, ETHERTYPEf, arg); 1486 /* Set EGR GBP ethertype for editing */ 1487 soc_reg_field_set(unit, EGR_GBP_ETHERTYPEr, &rval, ETHERTYPEf, arg); 1488 1489 SOC_IF_ERROR_RETURN(WRITE_ING_GBP_ETHERTYPEr(unit, rval)); 1490 SOC_IF_ERROR_RETURN(WRITE_EGR_GBP_ETHERTYPEr(unit, rval)); 1491 return BCM_E_NONE; 1492 } 1493 1494 /* 1495 * Function: 1496 * _bcm_td3_ing_gbp_ethertype_get 1497 * Description: 1498 * Get the ethertype field for GBP 1499 * Parameters: 1500 * unit - unit number 1501 * arg - Ethrtype to get 1502 * Returns: 1503 * BCM_E_xxxx 1504 */ 1505 1506 int 1507 _bcm_td3_ing_gbp_ethertype_get(int unit, int *arg) 1508 { 1509 uint32 rval; 1510 int enable; 1511 if (arg == NULL) { 1512 return BCM_E_PARAM; 1513 } 1514 1515 BCM_IF_ERROR_RETURN(READ_ING_GBP_ETHERTYPEr(unit, &rval)); 1516 /* If ethertype enabled, return ethertype */ 1517 enable = soc_reg_field_get(unit, ING_GBP_ETHERTYPEr, rval, ENABLEf); 1518 if (enable) { 1519 *arg = soc_reg_field_get(unit, ING_GBP_ETHERTYPEr, rval, ETHERTYPEf); 1520 } else { 1521 *arg = 0; 1522 } 1523 return BCM_E_NONE; 1524 } 1525 1526 /* 1527 * Function: 1528 * _bcm_td3_custom_fields_set 1529 * Description: 1530 * Set fields to parse custom packets 1531 * Parameters: 1532 * unit - unit number 1533 * arg - Value of fields set 1534 * Returns: 1535 * BCM_E_xxxx 1536 */ 1537 int 1538 _bcm_td3_custom_fields_set(int unit, bcm_switch_control_t type, int arg) 1539 { 1540 uint32 val32; 1541 uint64 val64; 1542 int max_val, len; 1543 soc_reg_t reg; 1544 soc_field_t field; 1545 1546 switch(type) { 1547 case bcmSwitchCustomOuterEthertype1: 1548 reg = PARSER1_USER_DEFINED_1_ETHERTYPEr; 1549 field = ETHERTYPEf; 1550 break; 1551 case bcmSwitchCustomOuterEthertype2: 1552 reg = PARSER1_USER_DEFINED_2_ETHERTYPEr; 1553 field = ETHERTYPEf; 1554 break; 1555 case bcmSwitchCustomInnerEthertype1: 1556 reg = PARSER2_USER_DEFINED_1_ETHERTYPEr; 1557 field = ETHERTYPEf; 1558 break; 1559 case bcmSwitchCustomInnerEthertype2: 1560 reg = PARSER2_USER_DEFINED_2_ETHERTYPEr; 1561 field = ETHERTYPEf; 1562 break; 1563 case bcmSwitchCustomOuterProtocolId1: 1564 reg = PARSER1_USER_DEFINED_1_IP_PROTOCOLr; 1565 field = PROTOCOL_IDf; 1566 break; 1567 case bcmSwitchCustomOuterProtocolId2: 1568 reg = PARSER1_USER_DEFINED_2_IP_PROTOCOLr; 1569 field = PROTOCOL_IDf; 1570 break; 1571 case bcmSwitchCustomInnerProtocolId1: 1572 reg = PARSER2_USER_DEFINED_1_IP_PROTOCOLr; 1573 field = PROTOCOL_IDf; 1574 break; 1575 case bcmSwitchCustomInnerProtocolId2: 1576 reg = PARSER2_USER_DEFINED_2_IP_PROTOCOLr; 1577 field = PROTOCOL_IDf; 1578 break; 1579 case bcmSwitchCustomOuterUdpDstPort1: 1580 reg = PARSER1_USER_DEFINED_1_UDP_DEST_PORTr; 1581 field = PORTf; 1582 break; 1583 case bcmSwitchCustomOuterUdpDstPort2: 1584 reg = PARSER1_USER_DEFINED_2_UDP_DEST_PORTr; 1585 field = PORTf; 1586 break; 1587 case bcmSwitchCustomInnerUdpDstPort1: 1588 reg = PARSER2_USER_DEFINED_1_UDP_DEST_PORTr; 1589 field = PORTf; 1590 break; 1591 case bcmSwitchCustomInnerUdpDstPort2: 1592 reg = PARSER2_USER_DEFINED_2_UDP_DEST_PORTr; 1593 field = PORTf; 1594 break; 1595 default: 1596 return (BCM_E_UNAVAIL); 1597 } 1598 1599 len = soc_reg_field_length(unit, reg, field); 1600 max_val = (1 << len) - 1; 1601 if (arg < 0 || arg > max_val) { 1602 return BCM_E_PARAM; 1603 } 1604 1605 if(SOC_REG_IS_VALID(unit, reg)) { 1606 COMPILER_64_ZERO(val64); 1607 SOC_IF_ERROR_RETURN(soc_reg_get(unit, 1608 reg, REG_PORT_ANY, 0, &val64)); 1609 val32 = arg; 1610 /* Enable and Set custom field value for parsing */ 1611 soc_reg64_field32_set(unit, reg, &val64, ENABLEf, 1); 1612 soc_reg64_field32_set(unit, reg, &val64, field, val32); 1613 1614 SOC_IF_ERROR_RETURN(soc_reg_set(unit, 1615 reg, REG_PORT_ANY, 0, val64)); 1616 } 1617 return BCM_E_NONE; 1618 } 1619 1620 /* 1621 * Function: 1622 * _bcm_td3_custom_fields_get 1623 * Description: 1624 * Get values of custom fields 1625 * Parameters: 1626 * unit - unit number 1627 * arg - Custom field value to get 1628 * Returns: 1629 * BCM_E_xxxx 1630 */ 1631 1632 int 1633 _bcm_td3_custom_fields_get(int unit, bcm_switch_control_t type, int *arg) 1634 { 1635 uint32 val32, enable; 1636 uint64 val64; 1637 soc_reg_t reg; 1638 soc_field_t field; 1639 1640 if (arg == NULL) { 1641 return BCM_E_PARAM; 1642 } 1643 1644 switch(type) { 1645 case bcmSwitchCustomOuterEthertype1: 1646 reg = PARSER1_USER_DEFINED_1_ETHERTYPEr; 1647 field = ETHERTYPEf; 1648 break; 1649 case bcmSwitchCustomOuterEthertype2: 1650 reg = PARSER1_USER_DEFINED_2_ETHERTYPEr; 1651 field = ETHERTYPEf; 1652 break; 1653 case bcmSwitchCustomInnerEthertype1: 1654 reg = PARSER2_USER_DEFINED_1_ETHERTYPEr; 1655 field = ETHERTYPEf; 1656 break; 1657 case bcmSwitchCustomInnerEthertype2: 1658 reg = PARSER2_USER_DEFINED_2_ETHERTYPEr; 1659 field = ETHERTYPEf; 1660 break; 1661 case bcmSwitchCustomOuterProtocolId1: 1662 reg = PARSER1_USER_DEFINED_1_IP_PROTOCOLr; 1663 field = PROTOCOL_IDf; 1664 break; 1665 case bcmSwitchCustomOuterProtocolId2: 1666 reg = PARSER1_USER_DEFINED_2_IP_PROTOCOLr; 1667 field = PROTOCOL_IDf; 1668 break; 1669 case bcmSwitchCustomInnerProtocolId1: 1670 reg = PARSER2_USER_DEFINED_1_IP_PROTOCOLr; 1671 field = PROTOCOL_IDf; 1672 break; 1673 case bcmSwitchCustomInnerProtocolId2: 1674 reg = PARSER2_USER_DEFINED_2_IP_PROTOCOLr; 1675 field = PROTOCOL_IDf; 1676 break; 1677 case bcmSwitchCustomOuterUdpDstPort1: 1678 reg = PARSER1_USER_DEFINED_1_UDP_DEST_PORTr; 1679 field = PORTf; 1680 break; 1681 case bcmSwitchCustomOuterUdpDstPort2: 1682 reg = PARSER1_USER_DEFINED_2_UDP_DEST_PORTr; 1683 field = PORTf; 1684 break; 1685 case bcmSwitchCustomInnerUdpDstPort1: 1686 reg = PARSER2_USER_DEFINED_1_UDP_DEST_PORTr; 1687 field = PORTf; 1688 break; 1689 case bcmSwitchCustomInnerUdpDstPort2: 1690 reg = PARSER2_USER_DEFINED_2_UDP_DEST_PORTr; 1691 field = PORTf; 1692 break; 1693 default: 1694 return (BCM_E_UNAVAIL); 1695 } 1696 1697 if(SOC_REG_IS_VALID(unit, reg)) { 1698 COMPILER_64_ZERO(val64); 1699 SOC_IF_ERROR_RETURN(soc_reg_get(unit, 1700 reg, REG_PORT_ANY, 0, &val64)); 1701 /* If enabled, return custom field value */ 1702 enable = soc_reg64_field32_get(unit, reg, val64, ENABLEf); 1703 if (enable) { 1704 val32 = soc_reg64_field32_get(unit, reg, val64, field); 1705 } else { 1706 val32 = 0; 1707 } 1708 *arg = val32; 1709 } 1710 return BCM_E_NONE; 1711 } 1712 1713 #if defined(BCM_HELIX5_SUPPORT) 1714 /* 1715 * Function: 1716 * _bcm_mcastgbp_default_classid_set 1717 * Description: 1718 * Set the default class id for Mcast GBP SID_DID lookup miss 1719 * Parameters: 1720 * unit - unit number 1721 * arg - argument to set as Default Classid 1722 * Returns: 1723 * BCM_E_xxxx 1724 */ 1725 int 1726 _bcm_mcastgbp_default_classid_set(int unit, int arg) 1727 { 1728 int len, max_val; 1729 uint32 rval; 1730 1731 BCM_IF_ERROR_RETURN(READ_EVXLT2_GBP_SID_DID_LOOKUP_MISS_POLICYr(unit, &rval)); 1732 1733 len = soc_reg_field_length(unit, EVXLT2_GBP_SID_DID_LOOKUP_MISS_POLICYr, CLASS_IDf); 1734 max_val = (1 << len) - 1; 1735 if (arg < 1 || arg > max_val) { 1736 return BCM_E_PARAM; 1737 } 1738 1739 /* Program default class id when there is miss in 1740 * GBP SID_DID lookup for MC flows*/ 1741 soc_reg_field_set(unit, EVXLT2_GBP_SID_DID_LOOKUP_MISS_POLICYr, &rval, CLASS_IDf, arg); 1742 SOC_IF_ERROR_RETURN(WRITE_EVXLT2_GBP_SID_DID_LOOKUP_MISS_POLICYr(unit, rval)); 1743 return BCM_E_NONE; 1744 } 1745 1746 /* 1747 * Function: 1748 * _bcm_mcastgbp_default_classid_get 1749 * Description: 1750 * Get the default class id for Mcast GBP SID_DID lookup miss 1751 * Parameters: 1752 * unit - unit number 1753 * arg - Default Classid to get 1754 * Returns: 1755 * BCM_E_xxxx 1756 */ 1757 1758 int 1759 _bcm_mcastgbp_default_classid_get(int unit, int *arg) 1760 { 1761 uint32 rval; 1762 if (arg == NULL) { 1763 return BCM_E_PARAM; 1764 } 1765 1766 BCM_IF_ERROR_RETURN(READ_EVXLT2_GBP_SID_DID_LOOKUP_MISS_POLICYr(unit, &rval)); 1767 /* Return the value of default Class Id */ 1768 *arg = soc_reg_field_get(unit, EVXLT2_GBP_SID_DID_LOOKUP_MISS_POLICYr, rval, CLASS_IDf); 1769 return BCM_E_NONE; 1770 } 1771 #endif 1772 1773 /* 1774 * Function: 1775 * _bcm_td3_vxlan_udp_source_port_sel_set 1776 * Purpose: 1777 * Select UDP Source port for VXLAN 1778 * Parameters: 1779 * unit - SOC unit number. 1780 * mode - Selection mode of UDP SourcePort. 1781 * Returns: 1782 * BCM_E_XXX. 1783 */ 1784 int 1785 _bcm_td3_vxlan_udp_source_port_sel_set(int unit, int mode) 1786 { 1787 if ((mode < bcmSwitchTunnelUdpSrcPortStatic) || 1788 (mode >= bcmSwitchTunnelUdpSrcPortCount) ) { 1789 return BCM_E_PARAM; 1790 } 1791 1792 if (!SOC_REG_IS_VALID(unit, EGR_VXLAN_CONTROLr)) { 1793 return BCM_E_UNAVAIL; 1794 } 1795 1796 if (SOC_REG_FIELD_VALID(unit, EGR_VXLAN_CONTROLr, USE_SOURCE_PORT_SELf)){ 1797 SOC_IF_ERROR_RETURN( 1798 soc_reg_field32_modify(unit, EGR_VXLAN_CONTROLr, 1799 REG_PORT_ANY, USE_SOURCE_PORT_SELf, mode)); 1800 } 1801 1802 if (SOC_REG_IS_VALID(unit,FLEX_EDITOR_VXLAN_CONTROL_64r)) { 1803 SOC_IF_ERROR_RETURN( 1804 soc_reg_field32_modify(unit, FLEX_EDITOR_VXLAN_CONTROL_64r, 1805 REG_PORT_ANY, VXLAN_FLAGSf, 0x8)); 1806 } 1807 1808 return BCM_E_NONE; 1809 } 1810 1811 /* 1812 * Function: 1813 * _bcm_td3_vxlan_udp_source_port_sel_get 1814 * Purpose: 1815 * Get UDP Source port selection mode for VXLAN 1816 * Parameters: 1817 * unit - SOC unit number. 1818 * mode - Selection mode of UDP SourcePort. 1819 * Returns: 1820 * BCM_E_XXX. 1821 */ 1822 int 1823 _bcm_td3_vxlan_udp_source_port_sel_get(int unit, int *mode) 1824 { 1825 int rv = BCM_E_NONE; 1826 uint64 reg64; 1827 1828 COMPILER_64_ZERO(reg64); 1829 1830 SOC_IF_ERROR_RETURN(READ_EGR_VXLAN_CONTROLr(unit, ®64)); 1831 *mode = soc_reg64_field32_get(unit, EGR_VXLAN_CONTROLr, 1832 reg64, USE_SOURCE_PORT_SELf); 1833 return rv; 1834 } 1835 1836 /* 1837 * Function: 1838 * _bcm_td3_gpe_udp_source_port_sel_set 1839 * Purpose: 1840 * Select UDP Source port for GPE 1841 * Parameters: 1842 * unit - SOC unit number. 1843 * mode - Selection mode of UDP SourcePort. 1844 * Returns: 1845 * BCM_E_XXX. 1846 */ 1847 int 1848 _bcm_td3_gpe_udp_source_port_sel_set(int unit, int mode) 1849 { 1850 if ((mode < bcmSwitchTunnelUdpSrcPortStatic) || 1851 (mode >= bcmSwitchTunnelUdpSrcPortCount) ) { 1852 return BCM_E_PARAM; 1853 } 1854 1855 if (!SOC_REG_IS_VALID(unit, EGR_GPE_CONTROLr)) { 1856 return BCM_E_UNAVAIL; 1857 } 1858 1859 if (SOC_REG_FIELD_VALID(unit, EGR_GPE_CONTROLr, UDP_SOURCE_PORT_SELf)){ 1860 SOC_IF_ERROR_RETURN( 1861 soc_reg_field32_modify(unit, EGR_GPE_CONTROLr, 1862 REG_PORT_ANY, UDP_SOURCE_PORT_SELf, mode)); 1863 } 1864 1865 return BCM_E_NONE; 1866 } 1867 1868 /* 1869 * Function: 1870 * _bcm_td3_gpe_udp_source_port_sel_get 1871 * Purpose: 1872 * Get UDP Source port selection mode for GPE 1873 * Parameters: 1874 * unit - SOC unit number. 1875 * mode - Selection mode of UDP SourcePort. 1876 * Returns: 1877 * BCM_E_XXX. 1878 */ 1879 int 1880 _bcm_td3_gpe_udp_source_port_sel_get(int unit, int *mode) 1881 { 1882 uint32 reg_val = 0; 1883 1884 SOC_IF_ERROR_RETURN(READ_EGR_GPE_CONTROLr(unit, ®_val)); 1885 *mode = soc_reg_field_get(unit, EGR_GPE_CONTROLr, 1886 reg_val, UDP_SOURCE_PORT_SELf); 1887 return BCM_E_NONE; 1888 } 1889 1890 /* 1891 * Function: 1892 * _bcm_td3_geneve_udp_source_port_sel_set 1893 * Purpose: 1894 * Select UDP Source port for GENEVE 1895 * Parameters: 1896 * unit - SOC unit number. 1897 * mode - Selection mode of UDP SourcePort. 1898 * Returns: 1899 * BCM_E_XXX. 1900 */ 1901 int 1902 _bcm_td3_geneve_udp_source_port_sel_set(int unit, int mode) 1903 { 1904 if ((mode < bcmSwitchTunnelUdpSrcPortStatic) || 1905 (mode >= bcmSwitchTunnelUdpSrcPortCount) ) { 1906 return BCM_E_PARAM; 1907 } 1908 1909 if (!SOC_REG_IS_VALID(unit, EGR_GENEVE_CONTROLr)) { 1910 return BCM_E_UNAVAIL; 1911 } 1912 1913 if (SOC_REG_FIELD_VALID(unit, EGR_GENEVE_CONTROLr, UDP_SOURCE_PORT_SELf)){ 1914 SOC_IF_ERROR_RETURN( 1915 soc_reg_field32_modify(unit, EGR_GENEVE_CONTROLr, 1916 REG_PORT_ANY, UDP_SOURCE_PORT_SELf, mode)); 1917 } 1918 1919 return BCM_E_NONE; 1920 } 1921 1922 /* 1923 * Function: 1924 * _bcm_td3_geneve_udp_source_port_sel_get 1925 * Purpose: 1926 * Get UDP Source port selection mode for GENEVE 1927 * Parameters: 1928 * unit - SOC unit number. 1929 * mode - Selection mode of UDP SourcePort. 1930 * Returns: 1931 * BCM_E_XXX. 1932 */ 1933 int 1934 _bcm_td3_geneve_udp_source_port_sel_get(int unit, int *mode) 1935 { 1936 uint32 reg_val = 0; 1937 1938 SOC_IF_ERROR_RETURN(READ_EGR_GENEVE_CONTROLr(unit, ®_val)); 1939 *mode = soc_reg_field_get(unit, EGR_GENEVE_CONTROLr, 1940 reg_val, UDP_SOURCE_PORT_SELf); 1941 return BCM_E_NONE; 1942 } 1943 1944 /* 1945 * Function: 1946 * _bcm_td3_ipv6_reserved_multicast_addr_multi_set 1947 * Description: 1948 * Set multiple ipv6 reserved multicast address and mask. 1949 * 1950 * Parameters: 1951 * unit - (IN) unit number 1952 * inner - (IN) inner or outer ipv6 header 1953 * index - (IN) table entry 1954 * ip6_addr - (IN) ipv6 address 1955 * ip6_mask - (IN) ipv6 addres mask 1956 * 1957 * Return Value: 1958 * BCM_E_XXX 1959 * Notes: 1960 */ 1961 int 1962 _bcm_td3_ipv6_reserved_multicast_addr_multi_set(int unit, 1963 int inner, 1964 int index, 1965 bcm_ip6_t ip6_addr, 1966 bcm_ip6_t ip6_mask) 1967 { 1968 soc_mem_t mem; 1969 uint32 ip6_fields[4]; 1970 uint32 entry_buf[SOC_MAX_MEM_FIELD_WORDS]; 1971 1972 if (inner) { 1973 mem = PARSER2_ING_IPV6_MC_RESERVED_ADDRESSm; 1974 } 1975 else { 1976 mem = PARSER1_ING_IPV6_MC_RESERVED_ADDRESSm; 1977 } 1978 /* clear entry memory */ 1979 sal_memset(entry_buf, 0, sizeof(entry_buf)); 1980 /* encode v6 address into ip6_fields */ 1981 SAL_IP6_ADDR_TO_UINT32(ip6_addr, ip6_fields); 1982 /* set address in entry */ 1983 soc_mem_field_set(unit, mem, entry_buf, ADDRESSf, &(ip6_fields[0])); 1984 /* encode v6 mask into ip6_fields */ 1985 SAL_IP6_ADDR_TO_UINT32(ip6_mask, ip6_fields); 1986 /* set the mask in entry */ 1987 soc_mem_field_set(unit, mem, entry_buf, MASKf, &(ip6_fields[0])); 1988 /* write entry to hardware */ 1989 BCM_IF_ERROR_RETURN(soc_mem_write(unit, mem, MEM_BLOCK_ALL, index, 1990 entry_buf)); 1991 return BCM_E_NONE; 1992 } 1993 1994 /* 1995 * Function: 1996 * _bcm_td3_ipv6_reserved_multicast_addr_multi_get 1997 * Description: 1998 * get multiple ipv6 reserved multicast address and mask 1999 * 2000 * Parameters: 2001 * unit - (IN) unit number 2002 * inner - (IN) inner or outer ipv6 header 2003 * index - (IN) table entry 2004 * ip6_addr - (OUT) ipv6 address 2005 * ip6_mask - (OUT) ipv6 addres mask 2006 * 2007 * Return Value: 2008 * BCM_E_XXX 2009 * Notes: 2010 */ 2011 int 2012 _bcm_td3_ipv6_reserved_multicast_addr_multi_get(int unit, 2013 int inner, 2014 int index, 2015 bcm_ip6_t *ip6_addr, 2016 bcm_ip6_t *ip6_mask) 2017 { 2018 soc_mem_t mem; 2019 uint32 ip6_fields[4]; 2020 uint32 entry_buf[SOC_MAX_MEM_FIELD_WORDS]; 2021 2022 if (inner) { 2023 mem = PARSER2_ING_IPV6_MC_RESERVED_ADDRESSm; 2024 } 2025 else { 2026 mem = PARSER1_ING_IPV6_MC_RESERVED_ADDRESSm; 2027 } 2028 /* clear entry memory */ 2029 sal_memset(entry_buf, 0, sizeof(entry_buf)); 2030 /* read entry from hardware */ 2031 BCM_IF_ERROR_RETURN(soc_mem_read(unit, mem, MEM_BLOCK_ALL, index, entry_buf)); 2032 /* deduce the address from entry */ 2033 soc_mem_field_get(unit, mem, entry_buf, ADDRESSf, &(ip6_fields[0])); 2034 /* set the address in user buf */ 2035 SAL_IP6_ADDR_FROM_UINT32(*ip6_addr, ip6_fields); 2036 2037 /* deduce the mask from entry */ 2038 soc_mem_field_get(unit, mem, entry_buf, MASKf, &(ip6_fields[0])); 2039 /* set the mask in user buf */ 2040 SAL_IP6_ADDR_FROM_UINT32(*ip6_mask, ip6_fields); 2041 2042 return BCM_E_NONE; 2043 } 2044 2045 #if defined(BCM_HELIX5_SUPPORT) 2046 /* 2047 * Function: 2048 * bcmi_hx5_switch_chip_info_get 2049 * Description: 2050 * Get IC Id for the device. 2051 * 2052 * Parameters: 2053 * unit - (IN) unit number 2054 * type - (IN) Chip Info switch Enum 2055 * max_size - (IN) Max size of data_buf 2056 * data_buf - (OUT) data buffer to be populated 2057 * actual_size - (OUT) Actual size data in data buffer 2058 * 2059 * Return Value: 2060 * BCM_E_XXX 2061 * Notes: 2062 */ 2063 int 2064 bcmi_hx5_switch_chip_info_get(int unit, 2065 bcm_switch_chip_info_t info_type, 2066 int max_size, 2067 void *data_buf, 2068 int *actual_size) 2069 { 2070 int rv = BCM_E_UNAVAIL; 2071 2072 switch(info_type) { 2073 case bcmSwitchChipInfoIcid: 2074 rv = soc_helix5_icid_get(unit, 2075 max_size, (uint8 *) data_buf, actual_size); 2076 break; 2077 default: 2078 rv = BCM_E_UNAVAIL; 2079 break; 2080 } 2081 2082 return rv; 2083 } 2084 #endif 2085 2086 int _bcm_td3_large_scale_nat_uc_set(int unit, 2087 bcm_switch_control_t type, 2088 int arg) 2089 { 2090 int val; 2091 soc_field_t fid; 2092 2093 fid = LARGE_SCALE_NAT_UC_FIELD_ID(type); 2094 val = LARGE_SCALE_NAT_UC_ARG2REG(arg); 2095 2096 if (val < 0) return BCM_E_PARAM; 2097 2098 BCM_IF_ERROR_RETURN(soc_reg_field32_modify 2099 (unit, LARGE_SCALE_NAT_CONTROLr, REG_PORT_ANY, fid, val)); 2100 2101 return BCM_E_NONE; 2102 } 2103 2104 int _bcm_td3_large_scale_nat_uc_get(int unit, 2105 bcm_switch_control_t type, 2106 int *arg) 2107 { 2108 uint32 reg_val=0; 2109 uint32 field_val=0; 2110 soc_field_t fid; 2111 2112 BCM_IF_ERROR_RETURN(READ_LARGE_SCALE_NAT_CONTROLr(unit, ®_val)); 2113 2114 fid = LARGE_SCALE_NAT_UC_FIELD_ID(type); 2115 2116 field_val = soc_reg_field_get(unit, LARGE_SCALE_NAT_CONTROLr, reg_val, fid); 2117 2118 *arg = LARGE_SCALE_NAT_UC_REG2ARG(field_val); 2119 return BCM_E_NONE; 2120 } 2121 2122 int _bcm_td3_large_scale_nat_mc_set(int unit, 2123 bcm_switch_control_t type, 2124 int arg) 2125 { 2126 soc_field_t fid1 = LARGE_SCALE_NAT_MC_FIELD_ID(type); 2127 soc_field_t fid2 = LARGE_SCALE_NAT_MAC_UPDATE_FIELD_ID(type); 2128 uint32 da_update = LARGE_SCALE_NAT_DA_UPDATE(arg); 2129 int val; 2130 2131 val = LARGE_SCALE_NAT_MC_ARG2REG(arg); 2132 2133 if (val < 0) return BCM_E_PARAM; 2134 2135 BCM_IF_ERROR_RETURN(soc_reg_field32_modify 2136 (unit, LARGE_SCALE_NAT_CONTROLr, REG_PORT_ANY, fid1, val)); 2137 2138 BCM_IF_ERROR_RETURN(soc_reg_field32_modify 2139 (unit, LARGE_SCALE_NAT_CONTROLr, REG_PORT_ANY, fid2, da_update)); 2140 2141 return BCM_E_NONE; 2142 } 2143 2144 int _bcm_td3_large_scale_nat_mc_get(int unit, 2145 bcm_switch_control_t type, 2146 int *arg) 2147 { 2148 uint32 reg_val=0; 2149 uint32 field_val=0; 2150 uint32 da_update=0; 2151 soc_field_t fid1 = LARGE_SCALE_NAT_MC_FIELD_ID(type); 2152 soc_field_t fid2 = LARGE_SCALE_NAT_MAC_UPDATE_FIELD_ID(type); 2153 2154 BCM_IF_ERROR_RETURN(READ_LARGE_SCALE_NAT_CONTROLr(unit, ®_val)); 2155 2156 field_val = soc_reg_field_get(unit, LARGE_SCALE_NAT_CONTROLr, reg_val, fid1); 2157 da_update = soc_reg_field_get(unit, LARGE_SCALE_NAT_CONTROLr, reg_val, fid2); 2158 2159 *arg = LARGE_SCALE_NAT_MC_REG2ARG(field_val, da_update); 2160 2161 return BCM_E_NONE; 2162 }