timesync.c (87789B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Timesync Configurations 8 * Purpose: API to set and get timesync config profiles for port. 9 */ 10 11 #include <soc/defs.h> 12 #include <sal/core/libc.h> 13 #if defined(BCM_TIMESYNC_V3_SUPPORT) || \ 14 defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 15 defined(BCM_SABER2_SUPPORT) 16 #include <soc/drv.h> 17 #include <soc/hash.h> 18 #include <soc/mem.h> 19 #include <soc/util.h> 20 #include <soc/debug.h> 21 #include <soc/profile_mem.h> 22 23 #include <bcm/error.h> 24 #include <bcm/port.h> 25 #include <bcm/proxy.h> 26 27 #include <bcm_int/esw/mbcm.h> 28 #include <bcm_int/esw/l3.h> 29 #if defined(BCM_KATANA_SUPPORT) 30 #include <bcm_int/esw/katana.h> 31 #endif 32 #if defined(BCM_TRIUMPH3_SUPPORT) 33 #include <bcm_int/esw/triumph3.h> 34 #endif 35 #if defined(BCM_TRIDENT2_SUPPORT) 36 #include <bcm_int/esw/trident2.h> 37 #endif 38 39 40 #include <bcm_int/esw/xgs3.h> 41 #include <bcm_int/esw_dispatch.h> 42 43 #ifdef PORTMOD_SUPPORT 44 #include <soc/portmod/portmod.h> 45 #include <soc/portmod/portmod_common.h> 46 #endif 47 48 /* Timesync module lock */ 49 STATIC sal_mutex_t _bcm_esw_timesync_mutex[BCM_MAX_NUM_UNITS] = {NULL}; 50 51 /* Timesync control profile */ 52 static soc_profile_mem_t * _bcm_esw_timesync_control_profile[BCM_MAX_NUM_UNITS]; 53 #if defined(BCM_TRIUMPH3_SUPPORT) 54 /* Timesync mpls label profile */ 55 static soc_profile_mem_t * _bcm_esw_timesync_mpls_label_profile[BCM_MAX_NUM_UNITS]; 56 #endif 57 58 /* Timesync defines */ 59 #define TIMESYNC_CONTROL_PROFILE(unit) \ 60 _bcm_esw_timesync_control_profile[unit] 61 62 #define TIMESYNC_MPLS_LABEL_PROFILE(unit) \ 63 _bcm_esw_timesync_mpls_label_profile[unit] 64 65 /* Timesync Profile index defines */ 66 #define TS_PORT_INDEX 0 67 #define TIMESYNC_MAX_PROFILE 1 68 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 69 #define TS_MPLS_INDEX_1 1 70 #define TS_MPLS_INDEX_2 2 71 #ifdef TIMESYNC_MAX_PROFILE 72 #undef TIMESYNC_MAX_PROFILE 73 #define TIMESYNC_MAX_PROFILE 3 74 #endif 75 #define TIMESYNC_MAX_MPLS_PROFILE 2 76 #endif 77 78 /* 79 * TIMESYNC module lock 80 */ 81 #define TIMESYNC_MODULE_MUTEX(unit) \ 82 _bcm_esw_timesync_mutex[unit] 83 84 #define TIMESYNC_MODULE_LOCK(unit) \ 85 sal_mutex_take(_bcm_esw_timesync_mutex[unit], sal_mutex_FOREVER); 86 87 #define TIMESYNC_MODULE_UNLOCK(unit) \ 88 sal_mutex_give(_bcm_esw_timesync_mutex[unit]); 89 90 /* Return On error with link mutex unlocked */ 91 #define _BCM_TIMESYNC_IF_ERROR_RETURN(op) \ 92 do { \ 93 int __rv__; \ 94 if (((__rv__ = (op)) < 0)) { \ 95 TIMESYNC_MODULE_UNLOCK(unit); \ 96 return(__rv__); \ 97 } \ 98 } while(0) 99 100 /* 101 * Function: 102 * _bcm_esw_port_timesync_profile_init 103 * Purpose: 104 * This function initializes timesync port and mpls profiles 105 * 106 * Parameters: 107 * unit - (IN) bcm device 108 * 109 * Returns: 110 * BCM_E_NONE - Success 111 * BCM_E_XXX 112 * Notes: 113 */ 114 int 115 _bcm_esw_port_timesync_profile_init(int unit) 116 { 117 soc_mem_t mem = 0; 118 int entry_words, alloc_size=0; 119 void *entry; 120 uint32 base_index; 121 int rv = BCM_E_NONE; 122 123 /* 124 * Initialize Timesync control profile 125 */ 126 if (TIMESYNC_CONTROL_PROFILE(unit) == NULL) { 127 TIMESYNC_CONTROL_PROFILE(unit) = sal_alloc (sizeof(soc_profile_mem_t), 128 "Timesync control profile mem"); 129 if (TIMESYNC_CONTROL_PROFILE(unit) == NULL) { 130 return BCM_E_MEMORY; 131 } 132 soc_profile_mem_t_init(TIMESYNC_CONTROL_PROFILE(unit)); 133 } else { 134 soc_profile_mem_destroy(unit, TIMESYNC_CONTROL_PROFILE(unit)); 135 } 136 137 /* 138 * Initialize Timesync mutex 139 */ 140 if (TIMESYNC_MODULE_MUTEX(unit) == NULL) { 141 TIMESYNC_MODULE_MUTEX(unit) = sal_mutex_create ("timesync_mutex"); 142 if (TIMESYNC_MODULE_MUTEX(unit) == NULL) { 143 return BCM_E_MEMORY; 144 } 145 } 146 147 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 148 if (soc_feature(unit, soc_feature_timesync_v3) || 149 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 150 SOC_IS_APACHE(unit)) { 151 mem = ING_1588_INGRESS_CTRLm; 152 entry_words = sizeof(ing_1588_ingress_ctrl_entry_t) / sizeof(uint32); 153 alloc_size = sizeof(ing_1588_ingress_ctrl_entry_t); 154 } 155 #endif /* BCM_TIMESYNC_V3_SUPPORT || BCM_TRIUMPH3_SUPPORT */ 156 157 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 158 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 159 mem = ING_1588_TS_DISPOSITION_PROFILE_TABLEm; 160 entry_words = sizeof(ing_1588_ts_disposition_profile_table_entry_t) / sizeof(uint32); 161 alloc_size = sizeof(ing_1588_ts_disposition_profile_table_entry_t); 162 } 163 #endif /*defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) */ 164 165 SOC_IF_ERROR_RETURN 166 (soc_profile_mem_create(unit, &mem, &entry_words, 1, 167 TIMESYNC_CONTROL_PROFILE(unit))); 168 169 /* Add timesync control default entry */ 170 entry = sal_alloc(alloc_size, "Timesync control profile mem"); 171 if (entry == NULL) { 172 return BCM_E_MEMORY; 173 } 174 sal_memset(entry, 0, alloc_size); 175 rv = soc_profile_mem_add(unit, TIMESYNC_CONTROL_PROFILE(unit), &entry, 1, 176 &base_index); 177 sal_free(entry); 178 if (BCM_FAILURE(rv)) { 179 return rv; 180 } 181 182 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 183 /* 184 * Initialize Timesync mpls label profile 185 */ 186 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_SABER2(unit) || SOC_IS_KATANA2(unit)) { 187 188 if (TIMESYNC_MPLS_LABEL_PROFILE(unit) == NULL) { 189 TIMESYNC_MPLS_LABEL_PROFILE(unit) = sal_alloc (sizeof(soc_profile_mem_t), 190 "Timesync mpls label profile mem"); 191 if (TIMESYNC_MPLS_LABEL_PROFILE(unit) == NULL) { 192 return BCM_E_MEMORY; 193 } 194 soc_profile_mem_t_init(TIMESYNC_MPLS_LABEL_PROFILE(unit)); 195 } else { 196 soc_profile_mem_destroy(unit, TIMESYNC_MPLS_LABEL_PROFILE(unit)); 197 } 198 199 mem = PTP_LABEL_RANGE_PROFILE_TABLEm; 200 entry_words = sizeof(ptp_label_range_profile_table_entry_t) / sizeof(uint32); 201 SOC_IF_ERROR_RETURN 202 (soc_profile_mem_create(unit, &mem, &entry_words, 1, 203 TIMESYNC_MPLS_LABEL_PROFILE(unit))); 204 205 /* Add timesync mpls label default entry */ 206 alloc_size = sizeof(ptp_label_range_profile_table_entry_t); 207 entry = sal_alloc(alloc_size, "Timesync mpls label profile mem"); 208 if (entry == NULL) { 209 return BCM_E_MEMORY; 210 } 211 sal_memset(entry, 0, alloc_size); 212 rv = soc_profile_mem_add(unit, TIMESYNC_MPLS_LABEL_PROFILE(unit), &entry, 1, 213 &base_index); 214 sal_free(entry); 215 if (BCM_FAILURE(rv)) { 216 return rv; 217 } 218 219 } 220 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_SABER2_SUPPORT */ 221 return rv; 222 } 223 224 /* 225 * Function: 226 * _bcm_esw_port_timesync_profile_delete 227 * Purpose: 228 * This function deletes timesync config profiles 229 * 230 * Parameters: 231 * unit - (IN) bcm device 232 * 233 * Returns: 234 * BCM_E_NONE - Success 235 * BCM_E_XXX 236 * Notes: 237 */ 238 int 239 _bcm_esw_port_timesync_profile_delete(int unit) 240 { 241 /* Destroy Timesync Control profile */ 242 if (TIMESYNC_CONTROL_PROFILE(unit)) { 243 BCM_IF_ERROR_RETURN( 244 soc_profile_mem_destroy(unit, TIMESYNC_CONTROL_PROFILE(unit))); 245 sal_free(TIMESYNC_CONTROL_PROFILE(unit)); 246 TIMESYNC_CONTROL_PROFILE(unit) = NULL; 247 } 248 249 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 250 /* Destroy Timesync Mpls Label profile */ 251 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_SABER2(unit) || SOC_IS_KATANA2(unit)) { 252 if (TIMESYNC_MPLS_LABEL_PROFILE(unit)) { 253 BCM_IF_ERROR_RETURN( 254 soc_profile_mem_destroy(unit, TIMESYNC_MPLS_LABEL_PROFILE(unit))); 255 sal_free(TIMESYNC_MPLS_LABEL_PROFILE(unit)); 256 TIMESYNC_MPLS_LABEL_PROFILE(unit) = NULL; 257 } 258 } 259 #endif 260 261 /* Destroy Timesync mutex */ 262 if (TIMESYNC_MODULE_MUTEX(unit)) { 263 sal_mutex_destroy(TIMESYNC_MODULE_MUTEX(unit)); 264 TIMESYNC_MODULE_MUTEX(unit) = NULL; 265 } 266 267 return BCM_E_NONE; 268 } 269 270 /* 271 * Function: 272 * _bcm_esw_port_timesync_contorl_profile_entry_add 273 * Purpose: 274 * Internal Funciton adds timesync control profiles 275 * 276 * Parameters: 277 * unit - (IN) Device number. 278 * ts_config - (IN) Timesync config 279 * *index - (OUT) profile index 280 * 281 * Returns: 282 * BCM_E_NONE - Success 283 * BCM_E_XXX 284 * Notes: 285 */ 286 STATIC int 287 _bcm_esw_port_timesync_control_profile_entry_add(int unit, 288 bcm_port_timesync_config_t *ts_config, uint32 *index) 289 { 290 int alloc_size=0; 291 void *entry; 292 int cnt, rv = BCM_E_NONE; 293 294 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 295 if (soc_feature(unit, soc_feature_timesync_v3) || 296 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 297 alloc_size = sizeof(ing_1588_ingress_ctrl_entry_t); 298 } 299 #endif 300 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 301 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 302 alloc_size = sizeof(ing_1588_ts_disposition_profile_table_entry_t); 303 } 304 #endif 305 306 entry = sal_alloc(alloc_size, "Timesync control profile mem"); 307 if (entry == NULL) { 308 return BCM_E_MEMORY; 309 } 310 sal_memset(entry, 0, alloc_size); 311 312 313 /* Set timesync message control tocpu/drop fields */ 314 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 315 if (soc_feature(unit, soc_feature_timesync_v3) || 316 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 317 for ( cnt = 0; cnt < BYTES2BITS(sizeof(uint32)); cnt++ ) 318 { 319 switch (ts_config->pkt_drop & (1 << cnt)) 320 { 321 case BCM_PORT_TIMESYNC_PKT_SYNC: 322 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 323 RX_TS_SYNC_DROPf, 1); 324 break; 325 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 326 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 327 RX_TS_DELAY_REQ_DROPf, 1); 328 break; 329 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 330 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 331 RX_TS_PDELAY_REQ_DROPf, 1); 332 break; 333 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 334 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 335 RX_TS_PDELAY_RESP_DROPf, 1); 336 break; 337 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 338 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 339 RX_TS_FOLLOW_UP_DROPf, 1); 340 break; 341 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 342 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 343 RX_TS_DELAY_RESP_DROPf, 1); 344 break; 345 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 346 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 347 RX_TS_PDELAY_RESP_FOLLOW_UP_DROPf, 1); 348 break; 349 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 350 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 351 RX_TS_MSG_TYPE_11_DROPf, 1); 352 break; 353 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 354 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 355 RX_TS_MSG_TYPE_12_DROPf, 1); 356 break; 357 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 358 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 359 RX_TS_MSG_TYPE_13_DROPf, 1); 360 break; 361 default: 362 break; 363 } 364 365 switch (ts_config->pkt_tocpu & (1 << cnt)) 366 { 367 case BCM_PORT_TIMESYNC_PKT_SYNC: 368 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 369 RX_TS_SYNC_TO_CPUf, 1); 370 break; 371 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 372 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 373 RX_TS_DELAY_REQ_TO_CPUf, 1); 374 break; 375 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 376 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 377 RX_TS_PDELAY_REQ_TO_CPUf, 1); 378 break; 379 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 380 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 381 RX_TS_PDELAY_RESP_TO_CPUf, 1); 382 break; 383 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 384 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 385 RX_TS_FOLLOW_UP_TO_CPUf, 1); 386 break; 387 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 388 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 389 RX_TS_DELAY_RESP_TO_CPUf, 1); 390 break; 391 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 392 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 393 RX_TS_PDELAY_RESP_FOLLOW_UP_TO_CPUf, 1); 394 break; 395 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 396 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 397 RX_TS_MSG_TYPE_11_TO_CPUf, 1); 398 break; 399 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 400 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 401 RX_TS_MSG_TYPE_12_TO_CPUf, 1); 402 break; 403 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 404 soc_ING_1588_INGRESS_CTRLm_field32_set(unit, entry, 405 RX_TS_MSG_TYPE_13_TO_CPUf, 1); 406 break; 407 default: 408 break; 409 } 410 } 411 412 } 413 #endif /* BCM_TIMESYNC_V3_SUPPORT || BCM_TRIUMPH3_SUPPORT */ 414 415 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 416 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 417 for ( cnt = 0; cnt < BYTES2BITS(sizeof(uint32)); cnt++ ) 418 { 419 switch (ts_config->pkt_drop & (1 << cnt)) 420 { 421 case BCM_PORT_TIMESYNC_PKT_SYNC: 422 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 423 MESSAGE_TYPE_0_DROPf, 1); 424 break; 425 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 426 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 427 MESSAGE_TYPE_1_DROPf, 1); 428 break; 429 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 430 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 431 MESSAGE_TYPE_2_DROPf, 1); 432 break; 433 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 434 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 435 MESSAGE_TYPE_3_DROPf, 1); 436 break; 437 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 438 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 439 MESSAGE_TYPE_8_DROPf, 1); 440 break; 441 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 442 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 443 MESSAGE_TYPE_9_DROPf, 1); 444 break; 445 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 446 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 447 MESSAGE_TYPE_10_DROPf, 1); 448 break; 449 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 450 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 451 MESSAGE_TYPE_11_DROPf, 1); 452 break; 453 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 454 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 455 MESSAGE_TYPE_12_DROPf, 1); 456 break; 457 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 458 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 459 MESSAGE_TYPE_13_DROPf, 1); 460 break; 461 default: 462 break; 463 } 464 465 switch (ts_config->pkt_tocpu & (1 << cnt)) 466 { 467 case BCM_PORT_TIMESYNC_PKT_SYNC: 468 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 469 MESSAGE_TYPE_0_COPY_TO_CPUf, 1); 470 break; 471 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 472 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 473 MESSAGE_TYPE_1_COPY_TO_CPUf, 1); 474 break; 475 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 476 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 477 MESSAGE_TYPE_2_COPY_TO_CPUf, 1); 478 break; 479 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 480 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 481 MESSAGE_TYPE_3_COPY_TO_CPUf, 1); 482 break; 483 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 484 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 485 MESSAGE_TYPE_8_COPY_TO_CPUf, 1); 486 break; 487 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 488 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 489 MESSAGE_TYPE_9_COPY_TO_CPUf, 1); 490 break; 491 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 492 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 493 MESSAGE_TYPE_10_COPY_TO_CPUf, 1); 494 break; 495 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 496 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 497 MESSAGE_TYPE_11_COPY_TO_CPUf, 1); 498 break; 499 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 500 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 501 MESSAGE_TYPE_12_COPY_TO_CPUf, 1); 502 break; 503 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 504 soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_set(unit, entry, 505 MESSAGE_TYPE_13_COPY_TO_CPUf, 1); 506 break; 507 default: 508 break; 509 } 510 } 511 } 512 #endif /* BCM_KATANA_SUPPORT || BCM_SABER2_SUPPORT */ 513 514 /* lock and unlocktimesync module for profile operations */ 515 TIMESYNC_MODULE_LOCK(unit); 516 rv = soc_profile_mem_add(unit, TIMESYNC_CONTROL_PROFILE(unit), &entry, 1, 517 index); 518 TIMESYNC_MODULE_UNLOCK(unit); 519 sal_free(entry); 520 return rv; 521 } 522 523 /* 524 * Function: 525 * _bcm_esw_port_timesync_contorl_profile_entry_get 526 * Purpose: 527 * Interal function gets timesync control profiles for the index 528 * 529 * Parameters: 530 * unit - (IN) Device number. 531 * ts_config - (OUT) Timesync config 532 * index - (IN) profile index 533 * 534 * Returns: 535 * BCM_E_NONE - Success 536 * BCM_E_XXX 537 * Notes: 538 */ 539 540 STATIC int 541 _bcm_esw_port_timesync_control_profile_entry_get(int unit, 542 bcm_port_timesync_config_t *ts_config, uint32 index) 543 { 544 int alloc_size=0; 545 void *entry; 546 int cnt, rv = BCM_E_NONE; 547 548 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 549 if (soc_feature(unit, soc_feature_timesync_v3) || 550 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 551 alloc_size = sizeof(ing_1588_ingress_ctrl_entry_t); 552 } 553 #endif /* BCM_TIMESYNC_V3_SUPPORT || BCM_TRIUMPH3_SUPPORT */ 554 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 555 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 556 alloc_size = sizeof(ing_1588_ts_disposition_profile_table_entry_t); 557 } 558 #endif /* BCM_KATANA_SUPPORT || BCM_SABER2_SUPPORT */ 559 560 entry = sal_alloc(alloc_size, "Timesync control profile mem"); 561 if (entry == NULL) { 562 return BCM_E_MEMORY; 563 } 564 sal_memset(entry, 0, alloc_size); 565 566 TIMESYNC_MODULE_LOCK(unit); 567 rv = soc_profile_mem_get(unit, TIMESYNC_CONTROL_PROFILE(unit), index, 1, &entry ); 568 if (BCM_FAILURE(rv)) { 569 sal_free(entry); 570 TIMESYNC_MODULE_UNLOCK(unit); 571 return rv; 572 } 573 574 /* Set timesync message control tocpu/drop fields */ 575 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 576 if (soc_feature(unit, soc_feature_timesync_v3) || 577 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 578 for ( cnt = 0; cnt < BYTES2BITS(sizeof(uint32)); cnt++ ) 579 { 580 switch (1 << cnt) 581 { 582 case BCM_PORT_TIMESYNC_PKT_SYNC: 583 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 584 RX_TS_SYNC_DROPf)) { 585 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_SYNC; 586 } 587 break; 588 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 589 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 590 RX_TS_DELAY_REQ_DROPf)) { 591 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_DELAY_REQ; 592 } 593 break; 594 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 595 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 596 RX_TS_PDELAY_REQ_DROPf)) { 597 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_PDELAY_REQ; 598 } 599 break; 600 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 601 if(soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 602 RX_TS_PDELAY_RESP_DROPf)) { 603 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_PDELAY_RESP; 604 } 605 break; 606 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 607 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 608 RX_TS_FOLLOW_UP_DROPf)) { 609 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_FOLLOWUP; 610 } 611 break; 612 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 613 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 614 RX_TS_DELAY_RESP_DROPf)) { 615 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_DELAY_RESP; 616 } 617 break; 618 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 619 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 620 RX_TS_PDELAY_RESP_FOLLOW_UP_DROPf)) { 621 ts_config->pkt_drop |= 622 BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP; 623 } 624 break; 625 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 626 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 627 RX_TS_MSG_TYPE_11_DROPf)) { 628 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_ANNOUNCE; 629 } 630 break; 631 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 632 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 633 RX_TS_MSG_TYPE_12_DROPf)) { 634 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_SIGNALLING; 635 } 636 break; 637 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 638 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 639 RX_TS_MSG_TYPE_13_DROPf)) { 640 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_MANAGMENT; 641 } 642 break; 643 default: 644 break; 645 } 646 647 switch (1 << cnt) 648 { 649 case BCM_PORT_TIMESYNC_PKT_SYNC: 650 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 651 RX_TS_SYNC_TO_CPUf)) { 652 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_SYNC; 653 } 654 break; 655 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 656 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 657 RX_TS_DELAY_REQ_TO_CPUf)) { 658 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_DELAY_REQ; 659 } 660 break; 661 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 662 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 663 RX_TS_PDELAY_REQ_TO_CPUf)) { 664 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_PDELAY_REQ; 665 } 666 break; 667 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 668 if(soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 669 RX_TS_PDELAY_RESP_TO_CPUf)) { 670 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_PDELAY_RESP; 671 } 672 break; 673 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 674 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 675 RX_TS_FOLLOW_UP_TO_CPUf)) { 676 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_FOLLOWUP; 677 } 678 break; 679 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 680 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 681 RX_TS_DELAY_RESP_TO_CPUf)) { 682 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_DELAY_RESP; 683 } 684 break; 685 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 686 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 687 RX_TS_PDELAY_RESP_FOLLOW_UP_TO_CPUf)) { 688 ts_config->pkt_tocpu |= 689 BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP; 690 } 691 break; 692 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 693 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 694 RX_TS_MSG_TYPE_11_TO_CPUf)) { 695 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_ANNOUNCE; 696 } 697 break; 698 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 699 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 700 RX_TS_MSG_TYPE_12_TO_CPUf)) { 701 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_SIGNALLING; 702 } 703 break; 704 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 705 if (soc_ING_1588_INGRESS_CTRLm_field32_get(unit, entry, 706 RX_TS_MSG_TYPE_13_TO_CPUf)) { 707 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_MANAGMENT; 708 } 709 break; 710 default: 711 break; 712 } 713 } 714 } 715 #endif /* BCM_TIMESYNC_V3_SUPPORT || BCM_TRIUMPH3_SUPPORT */ 716 717 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 718 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 719 for ( cnt = 0; cnt < BYTES2BITS(sizeof(uint32)); cnt++ ) 720 { 721 switch (1 << cnt) 722 { 723 case BCM_PORT_TIMESYNC_PKT_SYNC: 724 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 725 unit, entry,MESSAGE_TYPE_0_DROPf)) { 726 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_SYNC; 727 } 728 break; 729 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 730 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 731 unit, entry, MESSAGE_TYPE_1_DROPf)) { 732 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_DELAY_REQ; 733 } 734 break; 735 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 736 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 737 unit, entry, MESSAGE_TYPE_2_DROPf)) { 738 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_PDELAY_REQ; 739 } 740 break; 741 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 742 if(soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 743 unit, entry, MESSAGE_TYPE_3_DROPf)) { 744 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_PDELAY_RESP; 745 } 746 break; 747 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 748 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 749 unit, entry, MESSAGE_TYPE_8_DROPf)) { 750 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_FOLLOWUP; 751 } 752 break; 753 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 754 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 755 unit, entry, MESSAGE_TYPE_9_DROPf)) { 756 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_DELAY_RESP; 757 } 758 break; 759 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 760 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 761 unit, entry, MESSAGE_TYPE_10_DROPf)) { 762 ts_config->pkt_drop |= 763 BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP; 764 } 765 break; 766 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 767 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 768 unit, entry, MESSAGE_TYPE_11_DROPf)) { 769 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_ANNOUNCE; 770 } 771 break; 772 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 773 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 774 unit, entry, MESSAGE_TYPE_12_DROPf)) { 775 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_SIGNALLING; 776 } 777 break; 778 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 779 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 780 unit, entry, MESSAGE_TYPE_13_DROPf)) { 781 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_MANAGMENT; 782 } 783 break; 784 default: 785 break; 786 } 787 788 switch (1 << cnt) 789 { 790 case BCM_PORT_TIMESYNC_PKT_SYNC: 791 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 792 unit, entry, MESSAGE_TYPE_0_COPY_TO_CPUf)) { 793 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_SYNC; 794 } 795 break; 796 case BCM_PORT_TIMESYNC_PKT_DELAY_REQ: 797 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 798 unit, entry, MESSAGE_TYPE_1_COPY_TO_CPUf)) { 799 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_DELAY_REQ; 800 } 801 break; 802 case BCM_PORT_TIMESYNC_PKT_PDELAY_REQ: 803 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 804 unit, entry, MESSAGE_TYPE_2_COPY_TO_CPUf)) { 805 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_PDELAY_REQ; 806 } 807 break; 808 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP: 809 if(soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 810 unit, entry, MESSAGE_TYPE_3_COPY_TO_CPUf)) { 811 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_PDELAY_RESP; 812 } 813 break; 814 case BCM_PORT_TIMESYNC_PKT_FOLLOWUP: 815 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 816 unit, entry, MESSAGE_TYPE_8_COPY_TO_CPUf)) { 817 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_FOLLOWUP; 818 } 819 break; 820 case BCM_PORT_TIMESYNC_PKT_DELAY_RESP: 821 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 822 unit, entry, MESSAGE_TYPE_9_COPY_TO_CPUf)) { 823 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_DELAY_RESP; 824 } 825 break; 826 case BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP: 827 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 828 unit, entry, MESSAGE_TYPE_10_COPY_TO_CPUf)) { 829 ts_config->pkt_tocpu |= 830 BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP; 831 } 832 break; 833 case BCM_PORT_TIMESYNC_PKT_ANNOUNCE: 834 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 835 unit, entry, MESSAGE_TYPE_11_COPY_TO_CPUf)) { 836 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_ANNOUNCE; 837 } 838 break; 839 case BCM_PORT_TIMESYNC_PKT_SIGNALLING: 840 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 841 unit, entry, MESSAGE_TYPE_12_COPY_TO_CPUf)) { 842 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_SIGNALLING; 843 } 844 break; 845 case BCM_PORT_TIMESYNC_PKT_MANAGMENT: 846 if (soc_ING_1588_TS_DISPOSITION_PROFILE_TABLEm_field32_get( 847 unit, entry, MESSAGE_TYPE_13_COPY_TO_CPUf)) { 848 ts_config->pkt_tocpu |= BCM_PORT_TIMESYNC_PKT_MANAGMENT; 849 } 850 break; 851 default: 852 break; 853 } 854 } 855 } 856 #endif /* BCM_KATANA_SUPPORT || BCM_SABER2_SUPPORT */ 857 858 sal_free(entry); 859 TIMESYNC_MODULE_UNLOCK(unit); 860 return rv; 861 } 862 863 /* 864 * Function: 865 * _bcm_esw_port_timesync_port_profile_entry_delete 866 * Purpose: 867 * Internal function to delete timesync profiles 868 * 869 * Parameters: 870 * unit - (IN) bcm device 871 * 872 * Returns: 873 * BCM_E_NONE - Success 874 * BCM_E_XXX 875 * Notes: 876 */ 877 STATIC int 878 _bcm_esw_port_timesync_port_profile_entry_delete(int unit, int index) 879 { 880 int rv; 881 TIMESYNC_MODULE_LOCK(unit); 882 rv = soc_profile_mem_delete(unit, TIMESYNC_CONTROL_PROFILE(unit), index); 883 TIMESYNC_MODULE_UNLOCK(unit); 884 return rv; 885 } 886 887 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 888 /* 889 * Function: 890 * _bcm_esw_port_timesync_mpls_profile_entry_add 891 * Purpose: 892 * Internal Function to set timesync mpls profiles 893 * 894 * Parameters: 895 * unit - (IN) Device number. 896 * ts_config - (IN) Timesync config 897 * *index - (OUT) profile index 898 * 899 * Returns: 900 * BCM_E_NONE - Success 901 * BCM_E_XXX 902 * Notes: 903 */ 904 905 STATIC int 906 _bcm_esw_port_timesync_mpls_profile_entry_add(int unit, 907 bcm_port_timesync_config_t *ts_config, uint32 *index) 908 { 909 int alloc_size; 910 void *entry; 911 uint32 control_index; 912 int rv = BCM_E_NONE; 913 914 /* Create timesync control index */ 915 rv = _bcm_esw_port_timesync_control_profile_entry_add(unit, ts_config, 916 &control_index); 917 if (BCM_FAILURE(rv)) { 918 return rv; 919 } 920 921 /* Add and enable mpls label range */ 922 alloc_size = sizeof(ptp_label_range_profile_table_entry_t); 923 entry = sal_alloc(alloc_size, "Timesync mpls label profile mem"); 924 if (entry == NULL) { 925 return BCM_E_MEMORY; 926 } 927 sal_memset(entry, 0, alloc_size); 928 929 930 /* set timesync mpls label range */ 931 soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_set(unit, entry, 932 MIN_LABEL_OF_RANGEf, ts_config->mpls_min_label); 933 soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_set(unit, entry, 934 MAX_LABEL_OF_RANGEf, ts_config->mpls_max_label); 935 if (SOC_IS_SABER2(unit) || SOC_IS_KATANA2(unit)) { 936 soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_set(unit, entry, 937 ING_1588_TS_PROFILE_PTRf, control_index); 938 } else { 939 soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_set(unit, entry, 940 CTRL_PROFILE_INDEX_1588f, control_index); 941 } 942 soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_set(unit, entry, 943 ENABLE_1588OMPLSf, 1); 944 945 /* Set timesync mpls control profiles */ 946 TIMESYNC_MODULE_LOCK(unit); 947 rv = soc_profile_mem_add(unit, TIMESYNC_MPLS_LABEL_PROFILE(unit), &entry, 1, 948 index); 949 sal_free(entry); 950 TIMESYNC_MODULE_UNLOCK(unit); 951 return rv; 952 } 953 954 /* 955 * Function: 956 * _bcm_esw_port_timesync_mpls_profile_entry_get 957 * Purpose: 958 * Internal Function to get timesync mpls profiles 959 * 960 * Parameters: 961 * unit - (IN) Device number. 962 * ts_config - (OUT) Timesync config 963 * index - (IN) profile index 964 * 965 * Returns: 966 * BCM_E_NONE - Success 967 * BCM_E_XXX 968 * Notes: 969 */ 970 STATIC int 971 _bcm_esw_port_timesync_mpls_profile_entry_get(int unit, 972 bcm_port_timesync_config_t *ts_config, uint32 index) 973 { 974 int alloc_size; 975 void *entry; 976 int control_index; 977 int rv = BCM_E_NONE; 978 979 /* Add and enable mpls label range */ 980 alloc_size = sizeof(ptp_label_range_profile_table_entry_t); 981 entry = sal_alloc(alloc_size, "Timesync mpls label profile mem"); 982 if (entry == NULL) { 983 return BCM_E_MEMORY; 984 } 985 sal_memset(entry, 0, alloc_size); 986 987 TIMESYNC_MODULE_LOCK(unit); 988 rv = soc_profile_mem_get(unit, TIMESYNC_MPLS_LABEL_PROFILE(unit), index, 1, 989 &entry); 990 991 if (BCM_FAILURE(rv)) { 992 sal_free(entry); 993 TIMESYNC_MODULE_UNLOCK(unit); 994 return rv; 995 } 996 997 /* get mpls label range */ 998 ts_config->mpls_min_label = soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_get( 999 unit, entry, MIN_LABEL_OF_RANGEf); 1000 ts_config->mpls_max_label = soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_get( 1001 unit, entry, MAX_LABEL_OF_RANGEf); 1002 if (SOC_IS_SABER2(unit) || SOC_IS_KATANA2(unit)) { 1003 control_index = soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_get( 1004 unit, entry, ING_1588_TS_PROFILE_PTRf); 1005 } else { 1006 control_index = soc_PTP_LABEL_RANGE_PROFILE_TABLEm_field32_get( 1007 unit, entry, CTRL_PROFILE_INDEX_1588f); 1008 } 1009 /* get mpls control profiles */ 1010 if (control_index > 0) { 1011 rv = _bcm_esw_port_timesync_control_profile_entry_get(unit, ts_config, 1012 control_index); 1013 if (BCM_FAILURE(rv)) { 1014 sal_free(entry); 1015 TIMESYNC_MODULE_UNLOCK(unit); 1016 return rv; 1017 } 1018 } 1019 sal_free(entry); 1020 TIMESYNC_MODULE_UNLOCK(unit); 1021 return rv; 1022 } 1023 1024 /* 1025 * Function: 1026 * _bcm_esw_port_timesync_mpls_profile_entry_delete 1027 * Purpose: 1028 * Internal Function to delete timesync mpls profile 1029 * 1030 * Parameters: 1031 * unit - (IN) bcm device 1032 * 1033 * Returns: 1034 * BCM_E_NONE - Success 1035 * BCM_E_XXX 1036 * Notes: 1037 */ 1038 1039 STATIC int 1040 _bcm_esw_port_timesync_mpls_profile_entry_delete(int unit, int index) 1041 { 1042 int rv; 1043 TIMESYNC_MODULE_LOCK(unit); 1044 rv = soc_profile_mem_delete(unit, TIMESYNC_MPLS_LABEL_PROFILE(unit), index); 1045 TIMESYNC_MODULE_UNLOCK(unit); 1046 return rv; 1047 } 1048 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_SABER2_SUPPORT*/ 1049 1050 /* 1051 * Function: 1052 * _bcm_esw__port_timesync_config_set 1053 * Purpose: 1054 * Set Timesync Configuration profiles for the port 1055 * 1056 * Parameters: 1057 * unit - (IN) bcm device 1058 * port - (IN) port 1059 * config_count - (IN)Count of timesync profile 1060 * *config_array - (IN/OUT) Pointer to array of timesync profiles 1061 * 1062 * Returns: 1063 * BCM_E_NONE - Success 1064 * BCM_E_XXX 1065 * Notes: 1066 * Timesync config set function cleans up previous profiles before setting new 1067 * profiles. katana support one timesync port profile and triumph3 supports 1068 * one port profile and two mpls timesync profiles. 1069 */ 1070 int 1071 _bcm_esw_port_timesync_config_set(int unit, bcm_port_t port, int config_count, 1072 bcm_port_timesync_config_t *config_array, int is_remote_port) 1073 { 1074 int cnt, rv = BCM_E_NONE; 1075 int is_proxy_higig = 0, is_proxy_hybrid = 0; 1076 int prev_index = 0; 1077 uint32 rval, index; 1078 soc_mem_t mem; 1079 egr_1588_sa_entry_t sa_entry; 1080 port_tab_entry_t ptab; 1081 bcm_port_timesync_config_t *ts_config; 1082 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1083 int mpls_index = 0; 1084 int mpls_prev_index = 0; 1085 #endif 1086 1087 /* Validate Parameters */ 1088 if ((config_count > TIMESYNC_MAX_PROFILE) 1089 || ((config_count > 0) && (NULL == config_array)) 1090 || ((config_count == 0) && (NULL != config_array))) { 1091 return BCM_E_PARAM; 1092 } 1093 1094 /* Set timesync profiles */ 1095 for (cnt = 0; cnt < config_count; cnt++) 1096 { 1097 ts_config = (bcm_port_timesync_config_t*) (config_array + cnt); 1098 1099 if (ts_config->flags & BCM_PORT_TIMESYNC_DEFAULT) { 1100 /* Set one-step timestamp configurations */ 1101 if ( ts_config->flags & BCM_PORT_TIMESYNC_ONE_STEP_TIMESTAMP ) { 1102 1103 /* Enable Correction updates for ingress and egress */ 1104 1105 soc_reg_field32_modify(unit, EGR_1588_INGRESS_CTRLr, port, 1106 CF_UPDATE_ENABLEf, 1); 1107 #if defined(BCM_KATANA_SUPPORT) 1108 if (SOC_IS_KATANA(unit)) { 1109 SOC_IF_ERROR_RETURN( 1110 soc_reg_field32_modify(unit, EGR_1588_EGRESS_CTRLr, port, 1111 CF_UPDATE_ENABLEf, 1)); 1112 } 1113 #endif 1114 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 1115 defined(BCM_KATANA2_SUPPORT) || defined(BCM_SABER2_SUPPORT) || \ 1116 defined(BCM_HELIX4_SUPPORT) 1117 if (soc_feature(unit, soc_feature_timesync_v3) || 1118 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 1119 SOC_IS_KATANA2(unit) || SOC_IS_SABER2(unit) || 1120 SOC_IS_HELIX4(unit) || SOC_IS_APACHE(unit) ) { 1121 if (ts_config->flags & 1122 BCM_PORT_TIMESYNC_TIMESTAMP_CFUPDATE_ALL) { 1123 SOC_IF_ERROR_RETURN( 1124 soc_reg_field32_modify(unit, EGR_1588_EGRESS_CTRLr, port, 1125 CF_UPDATE_MODEf, 1)); 1126 1127 } 1128 else { 1129 /* TR3: The ingress port is default enabled for correction 1130 * updates for one-step timestamping and hence the 1131 * EGR update mode is set to ingress based correction 1132 * updates. 1133 */ 1134 SOC_IF_ERROR_RETURN( 1135 soc_reg_field32_modify(unit, EGR_1588_EGRESS_CTRLr, port, 1136 CF_UPDATE_MODEf, 2)); 1137 } 1138 } 1139 #endif 1140 1141 #if defined(BCM_KATANA2_SUPPORT) 1142 /* KT2: Enabling 48bit timestamping mode */ 1143 if (SOC_IS_KATANA2(unit)) { 1144 SOC_IF_ERROR_RETURN( 1145 soc_reg_field32_modify(unit, EGR_1588_PARSING_CONTROLr, 1146 port, TIMESTAMPING_MODEf, 1)); 1147 } 1148 #endif 1149 1150 /* Set sign extension from timestamp field, for ingress 1151 * Front Panel port or HG Proxy port 1152 */ 1153 #if defined(INCLUDE_L3) 1154 if (soc_feature(unit, soc_feature_higig_lookup)) { 1155 bcm_esw_proxy_server_get(unit, port, 1156 BCM_PROXY_MODE_HIGIG, &is_proxy_higig); 1157 bcm_esw_proxy_server_get(unit, port, 1158 BCM_PROXY_MODE_HYBRID, &is_proxy_hybrid); 1159 } 1160 #endif /* INCLUDE_L3 */ 1161 1162 if ((IS_E_PORT(unit, port) && !SOC_IS_STACK_PORT(unit, port)) || 1163 (IS_HG_PORT(unit, port) && 1164 (is_proxy_higig || is_proxy_hybrid))) { 1165 soc_reg_field32_modify(unit, EGR_1588_INGRESS_CTRLr, port, 1166 FORCE_ITS_SIGN_FROM_TSf, 1); 1167 } else { 1168 soc_reg_field32_modify(unit, EGR_1588_INGRESS_CTRLr, port, 1169 FORCE_ITS_SIGN_FROM_TSf, 0); 1170 1171 } 1172 1173 /* Enable Source Address update for corrections */ 1174 if (!BCM_MAC_IS_ZERO(ts_config->src_mac_addr)) { 1175 SOC_IF_ERROR_RETURN( 1176 soc_reg_field32_modify(unit, EGR_1588_EGRESS_CTRLr, 1177 port, SA_UPDATE_ENABLEf, 1)); 1178 sal_memset(&sa_entry, 0, sizeof(egr_1588_sa_entry_t)); 1179 soc_mem_mac_addr_set(unit, EGR_1588_SAm , &sa_entry, 1180 SAf, ts_config->src_mac_addr); 1181 BCM_IF_ERROR_RETURN( 1182 soc_mem_write(unit, EGR_1588_SAm, MEM_BLOCK_ALL, 1183 port, &sa_entry)); 1184 } 1185 #if defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) 1186 /* Disable automatic timestamp offset balancing in UNIMAC */ 1187 if (SOC_IS_HURRICANE2(unit) || SOC_IS_GREYHOUND(unit) || 1188 SOC_IS_HURRICANE3(unit) || SOC_IS_GREYHOUND2(unit)) { 1189 if (!IS_XL_PORT(unit, port) && !IS_CL_PORT(unit, port)) { 1190 if (SOC_REG_IS_VALID(unit, UMAC_TIMESTAMP_ADJUSTr) && 1191 SOC_REG_FIELD_VALID( 1192 unit, UMAC_TIMESTAMP_ADJUSTr, AUTO_ADJUSTf) && 1193 SOC_REG_FIELD_VALID( 1194 unit, UMAC_TIMESTAMP_ADJUSTr, ADJUSTf) && 1195 SOC_REG_FIELD_VALID( 1196 unit, UMAC_TIMESTAMP_ADJUSTr, EN_1588f)) { 1197 1198 SOC_IF_ERROR_RETURN( 1199 READ_UMAC_TIMESTAMP_ADJUSTr( 1200 unit, port, &rval)); 1201 soc_reg_field_set( 1202 unit, UMAC_TIMESTAMP_ADJUSTr, &rval, 1203 AUTO_ADJUSTf, 0); 1204 soc_reg_field_set( 1205 unit, UMAC_TIMESTAMP_ADJUSTr, &rval, 1206 ADJUSTf, 0); 1207 soc_reg_field_set( 1208 unit, UMAC_TIMESTAMP_ADJUSTr, &rval, 1209 EN_1588f, 1); 1210 SOC_IF_ERROR_RETURN( 1211 WRITE_UMAC_TIMESTAMP_ADJUSTr( 1212 unit, port, rval)); 1213 } 1214 } 1215 } 1216 #endif /* BCM_HURRICANE2_SUPPORT || BCM_GREYHOUND_SUPPORT */ 1217 } 1218 1219 /* Set two-step correction update enable */ 1220 if ( ts_config->flags & BCM_PORT_TIMESYNC_TWO_STEP_TIMESTAMP) { 1221 /* Set two-step timestamping in mac for all event pkts */ 1222 SOC_IF_ERROR_RETURN( 1223 READ_EGR_1588_EGRESS_CTRLr(unit, port,&rval)); 1224 soc_reg_field_set(unit, EGR_1588_EGRESS_CTRLr, &rval, 1225 TX_TS_SYNCf, 1); 1226 soc_reg_field_set(unit, EGR_1588_EGRESS_CTRLr, &rval, 1227 TX_TS_DELAY_REQf, 1); 1228 soc_reg_field_set(unit, EGR_1588_EGRESS_CTRLr, &rval, 1229 TX_TS_PDELAY_REQf, 1); 1230 soc_reg_field_set(unit, EGR_1588_EGRESS_CTRLr, &rval, 1231 TX_TS_PDELAY_RESPf, 1); 1232 SOC_IF_ERROR_RETURN( 1233 WRITE_EGR_1588_EGRESS_CTRLr(unit, port, rval)); 1234 } 1235 1236 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 1237 defined(BCM_SABER2_SUPPORT) 1238 if (soc_feature(unit, soc_feature_timesync_v3) || 1239 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 1240 SOC_IS_SABER2(unit) || SOC_IS_APACHE(unit) || SOC_IS_KATANA2(unit)) { 1241 if (ts_config->pkt_drop & BCM_PORT_TIMESYNC_PKT_INVALID) { 1242 SOC_IF_ERROR_RETURN( 1243 soc_reg_field32_modify(unit, EGR_1588_EGRESS_CTRLr, port, 1244 DROP_INVALID_1588_PKTf, 1)); 1245 } 1246 } 1247 #endif 1248 /* Create timesync control index */ 1249 rv = _bcm_esw_port_timesync_control_profile_entry_add(unit, ts_config, 1250 &index); 1251 if (BCM_FAILURE(rv)) { 1252 return rv; 1253 } 1254 1255 if (SOC_IS_TRIDENT3X(unit)) { 1256 BCM_IF_ERROR_RETURN(_bcm_esw_port_tab_get(unit, port, 1257 CTRL_PROFILE_INDEX_1588f, &prev_index)); 1258 BCM_IF_ERROR_RETURN(_bcm_esw_port_tab_set(unit, port, 1259 _BCM_CPU_TABS_ETHER, CTRL_PROFILE_INDEX_1588f, index)); 1260 BCM_IF_ERROR_RETURN(_bcm_esw_port_tab_set(unit, port, 1261 _BCM_CPU_TABS_ETHER, IEEE_802_1AS_ENABLEf, 1)); 1262 } else { 1263 soc_mem_lock(unit, PORT_TABm); 1264 mem = SOC_PORT_MEM_TAB(unit, port); 1265 rv = soc_mem_read(unit, mem, MEM_BLOCK_ANY, port, &ptab); 1266 if (BCM_FAILURE(rv)) { 1267 soc_mem_unlock(unit, PORT_TABm); 1268 return BCM_E_FAIL; 1269 1270 } 1271 1272 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 1273 if (soc_feature(unit, soc_feature_timesync_v3) || 1274 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 1275 prev_index = soc_PORT_TABm_field32_get(unit, 1276 &ptab, CTRL_PROFILE_INDEX_1588f); 1277 soc_PORT_TABm_field32_set(unit, &ptab, 1278 CTRL_PROFILE_INDEX_1588f, index); 1279 /* Enable Timesync for the port */ 1280 soc_PORT_TABm_field32_set(unit, &ptab, 1281 IEEE_802_1AS_ENABLEf, 1); 1282 } 1283 #endif 1284 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1285 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 1286 prev_index = soc_PORT_TABm_field32_get(unit, &ptab, 1287 ING_1588_TS_PROFILE_PTRf); 1288 soc_PORT_TABm_field32_set(unit, &ptab, 1289 ING_1588_TS_PROFILE_PTRf, index); 1290 /* Enable Timesync for the port */ 1291 soc_PORT_TABm_field32_set(unit, &ptab, 1292 ING_1588_TS_ENABLEf, 1); 1293 } 1294 #endif 1295 rv = soc_mem_write(unit, mem, MEM_BLOCK_ALL, port, &ptab); 1296 soc_mem_unlock(unit, PORT_TABm); 1297 } 1298 1299 /* delete old config profile */ 1300 if (prev_index > 0) { 1301 _bcm_esw_port_timesync_port_profile_entry_delete(unit, prev_index); 1302 } 1303 1304 } 1305 1306 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1307 /* Set Timesync MPLS label profile */ 1308 if ( ts_config->flags & BCM_PORT_TIMESYNC_MPLS ) { 1309 1310 if (SOC_IS_TD2_TT2(unit)) { 1311 return BCM_E_UNAVAIL; 1312 } 1313 1314 /* Check for max mpls profile entries */ 1315 if (++mpls_index > TIMESYNC_MAX_PROFILE - 1) { 1316 return BCM_E_PARAM; 1317 } 1318 1319 /* Create timesync mpls index */ 1320 rv = _bcm_esw_port_timesync_mpls_profile_entry_add(unit, ts_config, 1321 &index); 1322 if (BCM_FAILURE(rv)) { 1323 return rv; 1324 } 1325 1326 soc_mem_lock(unit, PORT_TABm);; 1327 mem = SOC_PORT_MEM_TAB(unit, port); 1328 rv = soc_mem_read(unit, mem, MEM_BLOCK_ANY, port, &ptab); 1329 if (BCM_FAILURE(rv)) { 1330 soc_mem_unlock(unit, PORT_TABm);; 1331 return BCM_E_FAIL; 1332 1333 } 1334 1335 switch (mpls_index) 1336 { 1337 case TS_MPLS_INDEX_1: 1338 mpls_prev_index = 1339 soc_PORT_TABm_field32_get(unit, &ptab, 1340 PTP_LABEL_RANGE_INDEX_1f); 1341 soc_PORT_TABm_field32_set(unit, &ptab, 1342 PTP_LABEL_RANGE_INDEX_1f,index); 1343 break; 1344 case TS_MPLS_INDEX_2: 1345 mpls_prev_index = 1346 soc_PORT_TABm_field32_get(unit,&ptab, 1347 PTP_LABEL_RANGE_INDEX_2f); 1348 soc_PORT_TABm_field32_set(unit, &ptab, 1349 PTP_LABEL_RANGE_INDEX_2f,index); 1350 break; 1351 /* coverity [dead_error_begin] */ 1352 default: 1353 mpls_prev_index = 0; 1354 break; 1355 } 1356 1357 /* Enable 1588 over MPLS for the port */ 1358 soc_PORT_TABm_field32_set(unit, &ptab, ENABLE_1588OMPLSf, 1 ); 1359 1360 rv = soc_mem_write(unit, mem, MEM_BLOCK_ALL, port, &ptab); 1361 if (BCM_FAILURE(rv)) { 1362 soc_mem_unlock(unit, PORT_TABm);; 1363 return BCM_E_FAIL; 1364 1365 } 1366 1367 soc_mem_unlock(unit, PORT_TABm);; 1368 1369 /* Delete Previous Mpls indexes */ 1370 if (mpls_index == TS_MPLS_INDEX_1 && mpls_prev_index != 0) { 1371 _bcm_esw_port_timesync_mpls_profile_entry_delete(unit, 1372 mpls_prev_index); 1373 } 1374 1375 if (mpls_index == TS_MPLS_INDEX_2 && mpls_prev_index != 0) { 1376 _bcm_esw_port_timesync_mpls_profile_entry_delete(unit, 1377 mpls_prev_index); 1378 } 1379 1380 } 1381 #endif 1382 } 1383 1384 /* Disable timesync for NULL timesync configuration */ 1385 if (config_count == 0) { 1386 if (!is_remote_port) { 1387 /* Disable one step and two step timesync */ 1388 SOC_IF_ERROR_RETURN( 1389 WRITE_EGR_1588_EGRESS_CTRLr(unit, port, 0)); 1390 SOC_IF_ERROR_RETURN( 1391 WRITE_EGR_1588_INGRESS_CTRLr(unit, port, 0)); 1392 } 1393 1394 if (SOC_IS_TRIDENT3X(unit)) { 1395 BCM_IF_ERROR_RETURN(_bcm_esw_port_tab_set(unit, port, 1396 _BCM_CPU_TABS_BOTH, IEEE_802_1AS_ENABLEf, 0)); 1397 } else { 1398 /* Disable timesync packet parsing */ 1399 soc_mem_lock(unit, PORT_TABm); 1400 mem = SOC_PORT_MEM_TAB(unit, port); 1401 rv = soc_mem_read(unit, mem, MEM_BLOCK_ANY, port, &ptab); 1402 if (BCM_FAILURE(rv)) { 1403 soc_mem_unlock(unit, PORT_TABm);; 1404 return BCM_E_FAIL; 1405 1406 } 1407 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 1408 defined(BCM_SABER2_SUPPORT) 1409 if (soc_feature(unit, soc_feature_timesync_v3) || 1410 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 1411 SOC_IS_SABER2(unit)) { 1412 if (!SOC_IS_SABER2(unit)) { 1413 /* Disable Timesync for the port */ 1414 soc_PORT_TABm_field32_set(unit, &ptab, 1415 IEEE_802_1AS_ENABLEf, 0); 1416 } 1417 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1418 if (SOC_MEM_FIELD_VALID(unit, mem, ENABLE_1588OMPLSf)) { 1419 soc_PORT_TABm_field32_set(unit, &ptab, 1420 ENABLE_1588OMPLSf, 0); 1421 } 1422 #endif 1423 } 1424 #endif 1425 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1426 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 1427 /* Disable Timesync for the port */ 1428 soc_PORT_TABm_field32_set(unit, &ptab, 1429 ING_1588_TS_ENABLEf, 0); 1430 1431 } 1432 #endif 1433 rv = soc_mem_write(unit, mem, MEM_BLOCK_ALL, port, &ptab); 1434 soc_mem_unlock(unit, PORT_TABm);; 1435 if (BCM_FAILURE(rv)) { 1436 return rv; 1437 } 1438 } 1439 } 1440 return rv; 1441 } 1442 1443 /* 1444 * Function: 1445 * _bcm_esw_port_timesync_config_get 1446 * Purpose: 1447 * Get Timesync configuration profiles for the port. 1448 * 1449 * Parameters: 1450 * unit - (IN) bcm device 1451 * port - (IN) port 1452 * array_size - (IN) Count of timesync profile 1453 * *config_array - (IN/OUT) Pointer to array of timesync profiles 1454 * *array_count - (OUT) Pointer to array of timesync profiles 1455 * 1456 * Returns: 1457 * BCM_E_NONE - Success 1458 * BCM_E_XXX 1459 * Notes: 1460 * Timesync config get function is overloaded to return supported profile 1461 * counts when config_array is passed as null. 1462 */ 1463 int 1464 _bcm_esw_port_timesync_config_get(int unit, bcm_port_t port, int array_size, 1465 bcm_port_timesync_config_t *config_array, 1466 int *array_count, int is_remote_port) 1467 { 1468 int cnt, config_cnt =0, rv = BCM_E_NONE; 1469 uint32 rval, rval_1, index = 0, value; 1470 uint32 ts_index[TIMESYNC_MAX_PROFILE]; 1471 soc_mem_t mem; 1472 egr_1588_sa_entry_t sa_entry; 1473 port_tab_entry_t ptab; 1474 bcm_port_timesync_config_t *ts_config; 1475 1476 /* Check for array_count */ 1477 if ((NULL == array_count) || 1478 (array_size > 0 && NULL == config_array)) { 1479 return BCM_E_PARAM; 1480 } 1481 1482 /* Read Port Table, do limited operations, holding port tab memory lock*/ 1483 sal_memset(ts_index, 0, sizeof(ts_index)); 1484 ts_index[TS_PORT_INDEX] = 0xffffffff; 1485 1486 if (SOC_IS_TRIDENT3X(unit)) { 1487 BCM_IF_ERROR_RETURN(_bcm_esw_port_tab_get(unit, port, 1488 CTRL_PROFILE_INDEX_1588f, (int *)&index)); 1489 /* Store all 1588 port indexes for later use */ 1490 if (ts_index[TS_PORT_INDEX] == 0xffffffff) { 1491 ts_index[TS_PORT_INDEX] = index; 1492 config_cnt++; 1493 } 1494 } else { 1495 mem = SOC_PORT_MEM_TAB(unit, port); 1496 soc_mem_lock(unit, PORT_TABm);; 1497 rv = soc_mem_read(unit, mem, MEM_BLOCK_ANY, port, &ptab); 1498 if (BCM_FAILURE(rv)) { 1499 soc_mem_unlock(unit, PORT_TABm);; 1500 return rv; 1501 } 1502 1503 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 1504 if (soc_feature(unit, soc_feature_timesync_v3) || 1505 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 1506 index = soc_PORT_TABm_field32_get(unit, 1507 &ptab, CTRL_PROFILE_INDEX_1588f); 1508 } 1509 #endif 1510 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1511 if (SOC_IS_KATANAX(unit) || SOC_IS_SABER2(unit)) { 1512 index = soc_PORT_TABm_field32_get(unit, &ptab, 1513 ING_1588_TS_PROFILE_PTRf); 1514 } 1515 #endif 1516 1517 /* Store all 1588 port indexes for later use */ 1518 if (ts_index[TS_PORT_INDEX] == 0xffffffff) { 1519 ts_index[TS_PORT_INDEX] = index; 1520 config_cnt++; 1521 } 1522 1523 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1524 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_SABER2(unit)) { 1525 index = soc_PORT_TABm_field32_get(unit, 1526 &ptab, PTP_LABEL_RANGE_INDEX_1f); 1527 if (index) { 1528 ts_index[TS_MPLS_INDEX_1] = index; 1529 config_cnt++; 1530 } 1531 1532 index = soc_PORT_TABm_field32_get(unit, 1533 &ptab, PTP_LABEL_RANGE_INDEX_2f); 1534 if (index) { 1535 ts_index[TS_MPLS_INDEX_2] = index; 1536 config_cnt++; 1537 } 1538 } 1539 #endif 1540 /* Release the port memory lock */ 1541 soc_mem_unlock(unit, PORT_TABm); 1542 } 1543 /* update config cnt */ 1544 *array_count = config_cnt; 1545 1546 /* if config_array is null, return array count */ 1547 if ((NULL == config_array)) { 1548 return BCM_E_NONE; 1549 } 1550 1551 /* lock timesync module */ 1552 TIMESYNC_MODULE_LOCK(unit); 1553 1554 for (cnt = 0; (cnt < array_size) && (array_size <= config_cnt); cnt++) 1555 { 1556 ts_config = (bcm_port_timesync_config_t*) (config_array + cnt ); 1557 1558 /* Get timesync port control profile */ 1559 if ((cnt == TS_PORT_INDEX) && (ts_index[TS_PORT_INDEX] != 0xffffffff)) { 1560 ts_config->flags |= BCM_PORT_TIMESYNC_DEFAULT; 1561 index = ts_index[TS_PORT_INDEX]; 1562 if (!is_remote_port) { 1563 value = 0; 1564 _BCM_TIMESYNC_IF_ERROR_RETURN( 1565 READ_EGR_1588_EGRESS_CTRLr(unit, port,&rval)); 1566 _BCM_TIMESYNC_IF_ERROR_RETURN( 1567 READ_EGR_1588_INGRESS_CTRLr(unit, port,&rval_1)); 1568 1569 value |= soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1570 TX_TS_SYNCf); 1571 value |= soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1572 TX_TS_DELAY_REQf); 1573 value |= soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1574 TX_TS_PDELAY_REQf); 1575 value |= soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1576 TX_TS_PDELAY_RESPf); 1577 if (value) { 1578 ts_config->flags|= BCM_PORT_TIMESYNC_TWO_STEP_TIMESTAMP; 1579 } 1580 1581 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 1582 defined(BCM_SABER2_SUPPORT) 1583 if (soc_feature(unit, soc_feature_timesync_v3) || 1584 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 1585 SOC_IS_SABER2(unit) || SOC_IS_APACHE(unit) || SOC_IS_KATANA2(unit)) { 1586 if (soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1587 DROP_INVALID_1588_PKTf)) { 1588 ts_config->pkt_drop |= BCM_PORT_TIMESYNC_PKT_INVALID; 1589 } 1590 } 1591 #endif 1592 1593 #if defined(BCM_KATANA_SUPPORT) 1594 if (SOC_IS_KATANA(unit)) { 1595 value = (soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1596 CF_UPDATE_ENABLEf) 1597 && soc_reg_field_get(unit, EGR_1588_INGRESS_CTRLr, rval_1, 1598 CF_UPDATE_ENABLEf)); 1599 } 1600 #endif 1601 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 1602 defined(BCM_KATANA2_SUPPORT) || defined(BCM_SABER2_SUPPORT) ||\ 1603 defined(BCM_HELIX4_SUPPORT) 1604 if (soc_feature(unit, soc_feature_timesync_v3) || 1605 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 1606 SOC_IS_KATANA2(unit) || SOC_IS_SABER2(unit) || 1607 SOC_IS_HELIX4(unit) || SOC_IS_APACHE(unit)) { 1608 1609 value = soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1610 CF_UPDATE_MODEf); 1611 if (value == 1) { 1612 ts_config->flags |= BCM_PORT_TIMESYNC_TIMESTAMP_CFUPDATE_ALL; 1613 } 1614 value = soc_reg_field_get(unit, EGR_1588_INGRESS_CTRLr, rval_1, 1615 CF_UPDATE_ENABLEf); 1616 } 1617 #endif 1618 if (value) { 1619 ts_config->flags |= BCM_PORT_TIMESYNC_ONE_STEP_TIMESTAMP; 1620 1621 if (soc_reg_field_get(unit, EGR_1588_EGRESS_CTRLr, rval, 1622 SA_UPDATE_ENABLEf)) { 1623 sal_memset(&sa_entry, 0, sizeof(egr_1588_sa_entry_t)); 1624 _BCM_TIMESYNC_IF_ERROR_RETURN( 1625 soc_mem_read(unit, EGR_1588_SAm, MEM_BLOCK_ANY, 1626 port, &sa_entry)); 1627 soc_mem_mac_addr_get(unit, EGR_1588_SAm ,&sa_entry, 1628 SAf, ts_config->src_mac_addr); 1629 } 1630 } 1631 } 1632 1633 rv = _bcm_esw_port_timesync_control_profile_entry_get(unit, ts_config, 1634 index); 1635 if (BCM_FAILURE(rv)) { 1636 TIMESYNC_MODULE_UNLOCK(unit); 1637 return rv; 1638 } 1639 } 1640 1641 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1642 /* Get timesync MPLS profile */ 1643 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_SABER2(unit)) { 1644 if (cnt == TS_MPLS_INDEX_1 && ts_index[TS_MPLS_INDEX_1]) { 1645 ts_config->flags|= BCM_PORT_TIMESYNC_MPLS; 1646 rv = _bcm_esw_port_timesync_mpls_profile_entry_get(unit, ts_config, 1647 ts_index[TS_MPLS_INDEX_1]); 1648 } 1649 1650 if (cnt == TS_MPLS_INDEX_2 && ts_index[TS_MPLS_INDEX_2]) { 1651 ts_config->flags|= BCM_PORT_TIMESYNC_MPLS; 1652 rv = _bcm_esw_port_timesync_mpls_profile_entry_get(unit, ts_config, 1653 ts_index[TS_MPLS_INDEX_2]); 1654 } 1655 } 1656 #endif 1657 } 1658 1659 /* unlock timesync module */ 1660 TIMESYNC_MODULE_UNLOCK(unit); 1661 1662 return rv; 1663 } 1664 1665 /* 1666 * Function: 1667 * _bcm_esw_port_timesync_timestamping_mode_set 1668 * Purpose: 1669 * Sets 32bit or 48bit Timestamping mode 1670 * 1671 * Parameters: 1672 * unit - (IN) bcm device 1673 * timestamping_mode - (IN) 32bit ot 48bit timestamping mode 1674 * 1675 * Returns: 1676 * BCM_E_NONE - Success 1677 * BCM_E_XXX 1678 */ 1679 int 1680 _bcm_esw_port_timesync_timestamping_mode_set(int unit, bcm_port_t port, 1681 bcm_switch_timesync_timestamping_mode_t timestamping_mode) 1682 { 1683 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || \ 1684 defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) || \ 1685 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 1686 uint32 rval; 1687 #endif 1688 #if defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 1689 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 1690 int val, index; 1691 #endif 1692 1693 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || \ 1694 defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) || \ 1695 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_HELIX4_SUPPORT) || \ 1696 defined(BCM_TOMAHAWK_SUPPORT) 1697 /* Enabling 48bit timestamping mode (in egress pipeline)*/ 1698 if (soc_feature(unit, soc_feature_timesync_v3) || 1699 SOC_IS_KATANA2(unit) || SOC_IS_TRIUMPH3(unit) || 1700 SOC_IS_SABER2(unit) || SOC_IS_TD2P_TT2P(unit) || 1701 SOC_IS_HELIX4(unit) || SOC_IS_APACHE(unit)) { 1702 if (SOC_IS_KATANA2(unit)) { 1703 if (soc_reg_field_valid(unit, TOP_MISC_CONTROL_0r, TIMESTAMP_VAL_MODE_SELf)) { 1704 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_0r(unit, &rval)); 1705 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 1706 TIMESTAMP_VAL_MODE_SELf, 1707 (timestamping_mode == 1708 bcmTimesyncTimestampingMode48bit) ? 0: 1); 1709 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 1710 1711 } 1712 } 1713 1714 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_HELIX4(unit)) { 1715 SOC_IF_ERROR_RETURN( 1716 soc_reg_field32_modify(unit, EGR_1588_PARSING_CONTROLr, 1717 port, MODE_48BITS_TIMESTAMPf, 1718 (timestamping_mode == 1719 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1720 SOC_IF_ERROR_RETURN( 1721 soc_reg_field32_modify(unit, PORT_MODE_REGr, 1722 port, 1723 EGR_1588_TIMESTAMPING_MODEf, 1724 (timestamping_mode == 1725 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1726 } else { 1727 SOC_IF_ERROR_RETURN( 1728 soc_reg_field32_modify(unit, EGR_1588_PARSING_CONTROLr, 1729 port, TIMESTAMPING_MODEf, 1730 (timestamping_mode == 1731 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1732 } 1733 } 1734 #endif 1735 1736 #if defined(BCM_SABER2_SUPPORT) 1737 /* in SB2, port number 1 -24 are viper ports (XPORT..) and 25-28 are eagle 1738 * ports (XLPORT..), enable 48bit timestamping mode in xlpor 1739 t block, 1740 * viper ports do not have configuration in port block. 1741 */ 1742 if (SOC_IS_SABER2(unit) && IS_XL_PORT(unit, port)) { 1743 soc_reg_field32_modify( 1744 unit, XLPORT_MODE_REGr, port, EGR_1588_TIMESTAMPING_MODEf, 1745 (timestamping_mode == bcmTimesyncTimestampingMode48bit) ? 1: 0); 1746 soc_reg_field32_modify( 1747 unit, XLPORT_MODE_REGr, port, EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1748 (timestamping_mode == bcmTimesyncTimestampingMode48bit) ? 1: 0); 1749 } 1750 #endif 1751 1752 #if defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 1753 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 1754 /* Enabling 48bit timestamping mode (in port block) */ 1755 if (SOC_IS_HURRICANE2(unit) || SOC_IS_GREYHOUND(unit) 1756 || SOC_IS_TD2P_TT2P(unit) || SOC_IS_HURRICANE3(unit) 1757 || SOC_IS_APACHE(unit) || SOC_IS_GREYHOUND2(unit) 1758 || SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3(unit)) { 1759 for(index=0; 1760 index<SOC_DRIVER(unit)->port_num_blktype; 1761 index++) { 1762 /* Get the block where the port belongs to */ 1763 val = SOC_PORT_IDX_BLOCK(unit, 1764 SOC_INFO(unit).port_l2p_mapping[port], 1765 index); 1766 if (val < 0) { 1767 break; 1768 } 1769 /* Check if it's valid in the bitmap */ 1770 if (!PBMP_MEMBER(SOC_BLOCK_BITMAP(unit, val), port)){ 1771 continue; 1772 } 1773 /* Get the block type */ 1774 val = SOC_BLOCK_TYPE(unit, val); 1775 if (val == SOC_BLK_XLPORT) { 1776 if (SOC_IS_HURRICANE2(unit) || SOC_IS_TD2P_TT2P(unit)) { 1777 SOC_IF_ERROR_RETURN( 1778 soc_reg_field32_modify( 1779 unit, XLPORT_MODE_REGr, 1780 port, EGR_1588_TIMESTAMPING_MODEf, 1781 (timestamping_mode == 1782 bcmTimesyncTimestampingMode48bit) ? 0: 1)); 1783 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || 1784 SOC_IS_GREYHOUND2(unit) || SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3(unit)) { 1785 SOC_IF_ERROR_RETURN( 1786 soc_reg_field32_modify( 1787 unit, XLPORT_MODE_REGr, 1788 port, EGR_1588_TIMESTAMPING_MODEf, 1789 (timestamping_mode == 1790 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1791 if (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2 || 1792 SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) 1793 { 1794 SOC_IF_ERROR_RETURN( 1795 soc_reg_field32_modify( 1796 unit, XLPORT_MODE_REGr, 1797 port, EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1798 (timestamping_mode == 1799 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1800 } 1801 } else if (SOC_IS_SABER2(unit) || SOC_IS_APACHE(unit)) { 1802 SOC_IF_ERROR_RETURN( 1803 soc_reg_field32_modify( 1804 unit, XLPORT_MODE_REGr, 1805 port, EGR_1588_TIMESTAMPING_MODEf, 1806 (timestamping_mode == 1807 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1808 } 1809 } else if (val == SOC_BLK_GPORT || 1810 val == SOC_BLK_GXPORT) { 1811 if(SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 1812 SOC_IS_GREYHOUND2(unit)) { 1813 SOC_IF_ERROR_RETURN( 1814 soc_reg_field32_modify( 1815 unit, GPORT_MODE_REGr, 1816 port, EGR_1588_TIMESTAMPING_MODEf, 1817 (timestamping_mode == 1818 bcmTimesyncTimestampingMode48bit) ? 0: 1)); 1819 } else if (SOC_IS_GREYHOUND(unit)) { 1820 SOC_IF_ERROR_RETURN( 1821 soc_reg_field32_modify( 1822 unit, GPORT_MODE_REGr, 1823 port, EGR_1588_TIMESTAMPING_MODEf, 1824 (timestamping_mode == 1825 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1826 1827 } 1828 } else if (val == SOC_BLK_CPORT || 1829 val == SOC_BLK_CLG2PORT || 1830 val == SOC_BLK_CLPORT) { 1831 if(SOC_IS_TD2P_TT2P(unit)) { 1832 SOC_IF_ERROR_RETURN( 1833 soc_reg_field32_modify( 1834 unit, CPORT_MODE_REGr, 1835 port, EGR_1588_TIMESTAMPING_MODEf, 1836 (timestamping_mode == 1837 bcmTimesyncTimestampingMode48bit) ? 0: 1)); 1838 } else if (SOC_IS_APACHE(unit) || SOC_IS_TOMAHAWKX(unit) || 1839 SOC_IS_GREYHOUND2(unit) || SOC_IS_TRIDENT3(unit)) { 1840 SOC_IF_ERROR_RETURN( 1841 soc_reg_field32_modify( 1842 unit, CLPORT_MODE_REGr, 1843 port, EGR_1588_TIMESTAMPING_MODEf, 1844 (timestamping_mode == 1845 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1846 if (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2 || 1847 SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) 1848 { 1849 SOC_IF_ERROR_RETURN( 1850 soc_reg_field32_modify( 1851 unit, CLPORT_MODE_REGr, 1852 port, EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1853 (timestamping_mode == 1854 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1855 } 1856 1857 } 1858 } else if (val == SOC_BLK_XLPORTB0) { 1859 if(SOC_IS_APACHE(unit)) { 1860 SOC_IF_ERROR_RETURN( 1861 soc_reg_field32_modify( 1862 unit, XLPORT_MODE_REGr, 1863 port, EGR_1588_TIMESTAMPING_MODEf, 1864 (timestamping_mode == 1865 bcmTimesyncTimestampingMode48bit) ? 1: 0)); 1866 } 1867 } 1868 } 1869 } 1870 #endif /* BCM_HURRICANE2_SUPPORT || BCM_GREYHOUND_SUPPORT */ 1871 1872 return (BCM_E_NONE); 1873 } 1874 1875 /* 1876 * Function: 1877 * _bcm_esw_port_timesync_timestamping_mode_get 1878 * Purpose: 1879 * Sets 32bit or 48bit Timestamping mode 1880 * 1881 * Parameters: 1882 * unit - (IN) bcm device 1883 * timestamping_mode - (IN/OUT) 32bit ot 48bit timestamping mode 1884 * 1885 * Returns: 1886 * BCM_E_NONE - Success 1887 * BCM_E_XXX 1888 */ 1889 int 1890 _bcm_esw_port_timesync_timestamping_mode_get(int unit, bcm_port_t port, 1891 bcm_switch_timesync_timestamping_mode_t *timestamping_mode) 1892 { 1893 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || \ 1894 defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) || \ 1895 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 1896 uint32 rval, rval_1; 1897 #endif 1898 #if defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 1899 defined(BCM_APACHE_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 1900 int val, index; 1901 #endif 1902 1903 #if defined(BCM_TIMESYNC_V3_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || \ 1904 defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_SABER2_SUPPORT) || \ 1905 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 1906 /* Enabling 48bit timestamping mode (in egress pipeline)*/ 1907 if (soc_feature(unit, soc_feature_timesync_v3) || 1908 SOC_IS_KATANA2(unit) || SOC_IS_TRIUMPH3(unit) || 1909 SOC_IS_SABER2(unit) || SOC_IS_TD2P_TT2P(unit) || 1910 SOC_IS_APACHE(unit) || SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3(unit)) { 1911 if (SOC_IS_KATANA2(unit) && !SOC_IS_SABER2(unit)) { 1912 if (soc_reg_field_valid(unit, TOP_MISC_CONTROL_0r, TIMESTAMP_VAL_MODE_SELf)) { 1913 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_0r(unit, &rval_1)); 1914 SOC_IF_ERROR_RETURN(READ_EGR_1588_PARSING_CONTROLr(unit, &rval)); 1915 1916 *timestamping_mode = (bcm_switch_timesync_timestamping_mode_t)( 1917 (!soc_reg_field_get(unit, TOP_MISC_CONTROL_0r, rval_1, 1918 TIMESTAMP_VAL_MODE_SELf)) 1919 && soc_reg_field_get(unit, EGR_1588_PARSING_CONTROLr, rval, 1920 TIMESTAMPING_MODEf)); 1921 } 1922 } else if (SOC_IS_TRIUMPH3(unit)) { 1923 SOC_IF_ERROR_RETURN( 1924 READ_EGR_1588_PARSING_CONTROLr(unit, &rval)); 1925 SOC_IF_ERROR_RETURN( 1926 READ_PORT_MODE_REGr(unit, port,&rval_1)); 1927 1928 *timestamping_mode = (bcm_switch_timesync_timestamping_mode_t)( 1929 soc_reg_field_get(unit, 1930 EGR_1588_PARSING_CONTROLr, rval, MODE_48BITS_TIMESTAMPf) 1931 && soc_reg_field_get(unit, PORT_MODE_REGr, rval_1, 1932 EGR_1588_TIMESTAMPING_MODEf)); 1933 } else { 1934 SOC_IF_ERROR_RETURN(READ_EGR_1588_PARSING_CONTROLr(unit, &rval)); 1935 1936 *timestamping_mode = (bcm_switch_timesync_timestamping_mode_t)( 1937 soc_reg_field_get(unit, EGR_1588_PARSING_CONTROLr, rval, 1938 TIMESTAMPING_MODEf)); 1939 1940 } 1941 } 1942 #endif 1943 1944 #if defined(BCM_SABER2_SUPPORT) 1945 /* in SB2, port number 1 -24 are viper ports (XPORT..)and 25-28 are eagle 1946 * ports (XLPORT..) 1947 * enable 48bit timestamping mode in xlport block, viper ports do not have 1948 * configuration in port block. 1949 */ 1950 if (SOC_IS_SABER2(unit) && IS_XL_PORT(unit, port)) { 1951 SOC_IF_ERROR_RETURN( 1952 READ_XLPORT_MODE_REGr(unit, port,&rval)); 1953 *timestamping_mode = (bcm_switch_timesync_timestamping_mode_t)( 1954 soc_reg_field_get(unit, XLPORT_MODE_REGr, rval, 1955 EGR_1588_TIMESTAMPING_MODEf)); 1956 } 1957 #endif 1958 1959 1960 #if defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 1961 defined(BCM_APACHE_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 1962 /* Enabling 48bit timestamping mode (in port block) */ 1963 if (SOC_IS_HURRICANE2(unit) || SOC_IS_GREYHOUND(unit) || 1964 SOC_IS_HURRICANE3(unit) || SOC_IS_APACHE(unit) || 1965 SOC_IS_GREYHOUND2(unit) || SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3(unit)) { 1966 for(index=0; 1967 index<SOC_DRIVER(unit)->port_num_blktype; 1968 index++) { 1969 /* Get the block where the port belongs to */ 1970 val = SOC_PORT_IDX_BLOCK(unit, 1971 SOC_INFO(unit).port_l2p_mapping[port], 1972 index); 1973 if (val < 0) { 1974 break; 1975 } 1976 /* Check if it's valid in the bitmap */ 1977 if (!PBMP_MEMBER(SOC_BLOCK_BITMAP(unit, val), port)){ 1978 continue; 1979 } 1980 /* Get the block type */ 1981 val = SOC_BLOCK_TYPE(unit, val); 1982 if (val == SOC_BLK_XLPORT) { 1983 if (SOC_IS_HURRICANE2(unit)) { 1984 SOC_IF_ERROR_RETURN( 1985 READ_XLPORT_MODE_REGr(unit, port,&rval)); 1986 *timestamping_mode = 1987 (bcm_switch_timesync_timestamping_mode_t)( 1988 !soc_reg_field_get(unit, XLPORT_MODE_REGr, rval, 1989 EGR_1588_TIMESTAMPING_MODEf)); 1990 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || 1991 SOC_IS_APACHE(unit) || SOC_IS_GREYHOUND2(unit) || 1992 SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3(unit)){ 1993 SOC_IF_ERROR_RETURN( 1994 READ_XLPORT_MODE_REGr(unit, port,&rval)); 1995 *timestamping_mode = 1996 (bcm_switch_timesync_timestamping_mode_t)( 1997 soc_reg_field_get(unit, XLPORT_MODE_REGr, rval, 1998 EGR_1588_TIMESTAMPING_MODEf)); 1999 } 2000 } else if (val == SOC_BLK_GPORT || 2001 val == SOC_BLK_GXPORT) { 2002 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 2003 SOC_IS_GREYHOUND2(unit)) { 2004 SOC_IF_ERROR_RETURN( 2005 READ_GPORT_MODE_REGr(unit, port,&rval)); 2006 *timestamping_mode = 2007 (bcm_switch_timesync_timestamping_mode_t)( 2008 !soc_reg_field_get(unit, GPORT_MODE_REGr, rval, 2009 EGR_1588_TIMESTAMPING_MODEf)); 2010 } else if (SOC_IS_GREYHOUND(unit)) { 2011 SOC_IF_ERROR_RETURN( 2012 READ_GPORT_MODE_REGr(unit, port,&rval)); 2013 *timestamping_mode = 2014 (bcm_switch_timesync_timestamping_mode_t)( 2015 soc_reg_field_get(unit, GPORT_MODE_REGr, rval, 2016 EGR_1588_TIMESTAMPING_MODEf)); 2017 } 2018 } else if (val == SOC_BLK_CLPORT || val == SOC_BLK_CLG2PORT) { 2019 if (SOC_IS_APACHE(unit) || SOC_IS_TOMAHAWKX(unit) || 2020 SOC_IS_GREYHOUND2(unit) || SOC_IS_TRIDENT3(unit)) { 2021 SOC_IF_ERROR_RETURN( 2022 READ_CLPORT_MODE_REGr(unit, port,&rval)); 2023 *timestamping_mode = 2024 (bcm_switch_timesync_timestamping_mode_t)( 2025 soc_reg_field_get(unit, CLPORT_MODE_REGr, rval, 2026 EGR_1588_TIMESTAMPING_MODEf)); 2027 } 2028 } 2029 } 2030 } 2031 #endif /* BCM_HURRICANE2_SUPPORT || BCM_GREYHOUND_SUPPORT || BCM_APACHE_SUPPORT */ 2032 2033 return (BCM_E_NONE); 2034 } 2035 /* 2036 * Function: 2037 * _bcm_esw_port_timesync_tx_timestamp_and_seqid_get 2038 * Purpose: 2039 * Retrives two-step PTP timestamp and seqid from MAC FIFO after packet TX 2040 * 2041 * Parameters: 2042 * unit - (IN) bcm device 2043 * 2044 * Returns: 2045 * BCM_E_NONE - Success 2046 * BCM_E_XXX 2047 */ 2048 int 2049 _bcm_esw_port_timesync_tx_info_get(int unit, bcm_port_t port, 2050 bcm_port_timesync_tx_info_t *tx_info) 2051 { 2052 int rv = BCM_E_NONE; 2053 #ifdef PORTMOD_SUPPORT 2054 portmod_fifo_status_t info; 2055 2056 if (soc_feature(unit, soc_feature_timesync_support)) { 2057 PORT_LOCK(unit); 2058 rv = portmod_port_timesync_tx_info_get(unit, port, &info); 2059 PORT_UNLOCK(unit); 2060 COMPILER_64_SET(tx_info->timestamp, info.timestamps_in_fifo_hi, info.timestamps_in_fifo); 2061 tx_info->sequence_id = info.sequence_id; 2062 tx_info->sub_ns = info.timestamp_sub_nanosec; 2063 } 2064 #endif 2065 return rv; 2066 } 2067 2068 2069 2070 #endif /* BCM_TIMESYNC_V3_SUPPORT || BCM_KATANA_SUPPORT || BCM_TRIUMPH3_SUPPORT */