switch.c (1208946B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: switch.c 8 * Purpose: BCM definitions for bcm_switch_control and 9 * bcm_switch_port_control functions 10 */ 11 12 #include <shared/bsl.h> 13 14 #include <sal/core/libc.h> 15 #include <soc/drv.h> 16 #include <soc/scache.h> 17 #include <soc/scache_dictionary.h> 18 #include <soc/hash.h> 19 #include <soc/ism_hash.h> 20 #include <soc/pbsmh.h> 21 #include <soc/higig.h> 22 #include <soc/format.h> 23 #include <bcm_int/common/mbox.h> 24 #if defined(INCLUDE_L3) 25 #include <soc/lpm.h> 26 #endif /* BCM_FIREBOLT2_SUPPORT */ 27 #if defined(BCM_BRADLEY_SUPPORT) 28 #include <soc/bradley.h> 29 #endif /* BCM_BRADLEY_SUPPORT */ 30 #if defined(BCM_TRIDENT2_SUPPORT) 31 #include <soc/trident2.h> 32 #endif /* BCM_TRIDENT2_SUPPORT */ 33 #if defined(BCM_MONTEREY_SUPPORT) 34 #include <soc/monterey.h> 35 #endif /* BCM_MONTEREY_SUPPORT */ 36 #if defined(BCM_APACHE_SUPPORT) 37 #include <soc/apache.h> 38 #endif /* BCM_APACHE_SUPPORT */ 39 #if defined(BCM_TRIDENT_SUPPORT) 40 #include <soc/trident.h> 41 #endif /* BCM_TRIDENT_SUPPORT */ 42 #if defined(BCM_TRIUMPH3_SUPPORT) 43 #include <soc/triumph3.h> 44 #endif /* BCM_TRIUMPH3_SUPPORT */ 45 #if defined(BCM_KATANA_SUPPORT) 46 #include <soc/katana.h> 47 #endif /* BCM_KATANA_SUPPORT */ 48 #if defined(BCM_SABER2_SUPPORT) 49 #include <soc/saber2.h> 50 #endif /* BCM_SABER2_SUPPORT */ 51 #if defined(BCM_KATANA2_SUPPORT) 52 #include <soc/katana2.h> 53 #include <bcm_int/esw/katana2.h> 54 #endif /* BCM_KATANA2_SUPPORT */ 55 #if defined(BCM_SABER2_SUPPORT) 56 #include <soc/saber2.h> 57 #endif 58 #if defined(BCM_METROLITE_SUPPORT) 59 #include <soc/metrolite.h> 60 #endif 61 #if defined(BCM_SHADOW_SUPPORT) 62 #include <soc/shadow.h> 63 #endif /* BCM_SHADOW_SUPPORT */ 64 #if defined(BCM_HURRICANE2_SUPPORT) 65 #include <soc/hurricane2.h> 66 #endif /* BCM_HURRICANE2_SUPPORT */ 67 #if defined(BCM_GREYHOUND_SUPPORT) 68 #include <soc/greyhound.h> 69 #endif /* BCM_GREYHOUND_SUPPORT */ 70 #if defined(BCM_TOMAHAWK_SUPPORT) 71 #include <soc/tomahawk.h> 72 #endif /* BCM_TOMAHAWK_SUPPORT */ 73 #if defined(BCM_TRIDENT3_SUPPORT) 74 #include <soc/trident3.h> 75 #endif /* BCM_TRIDENT3_SUPPORT */ 76 #if defined(BCM_HELIX5_SUPPORT) 77 #include <soc/helix5.h> 78 #endif /* BCM_HELIX5_SUPPORT */ 79 #if defined(BCM_MAVERICK2_SUPPORT) 80 #include <soc/maverick2.h> 81 #endif /* BCM_HELIX5_SUPPORT */ 82 #if defined(BCM_HURRICANE3_SUPPORT) 83 #include <soc/hurricane3.h> 84 #endif /* BCM_HURRICANE3_SUPPORT */ 85 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 86 #include <soc/tomahawk2.h> 87 #endif /* BCM_TOMAHAWK2_SUPPORT */ 88 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 89 #include <bcm_int/esw/trident2plus.h> 90 #include <soc/td2_td2p.h> 91 #endif /* BCM_TRIDENT2PLUS_SUPPORT*/ 92 93 #if defined(BCM_APACHE_SUPPORT) 94 #include <bcm_int/esw/monterey.h> 95 #endif /* BCM_APACHE_SUPPORT*/ 96 #if defined(BCM_APACHE_SUPPORT) 97 #include <bcm_int/esw/apache.h> 98 #endif /* BCM_APACHE_SUPPORT*/ 99 100 #if defined(BCM_TOMAHAWK3_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 101 #include <soc/tomahawk3.h> 102 #endif /* BCM_TOMAHAWK3_SUPPORT */ 103 104 #include <soc/l2x.h> 105 106 #ifdef ALPM_ENABLE 107 #include <soc/alpm.h> 108 #include <soc/esw/alpm_int.h> 109 #endif 110 111 #include <bcm/switch.h> 112 #include <bcm/error.h> 113 #include <bcm/extender.h> 114 #include <shared/shr_bprof.h> 115 116 #include <bcm_int/esw/vlan.h> 117 #include <bcm_int/esw/port.h> 118 #include <bcm_int/esw/mcast.h> 119 #include <bcm_int/esw/ipmc.h> 120 #include <bcm_int/esw/link.h> 121 #include <bcm_int/esw/mirror.h> 122 #include <bcm_int/esw/trunk.h> 123 #include <bcm_int/esw/cosq.h> 124 #include <bcm_int/esw/virtual.h> 125 #include <bcm_int/esw/switch.h> 126 #if defined(BCM_INSTRUMENTATION_SUPPORT) 127 #include <bcm_int/esw/instrumentation.h> 128 #endif /* BCM_INSTRUMENTATION_SUPPORT */ 129 #include <bcm_int/esw/pfc_deadlock.h> 130 #include <bcm_int/esw/rx.h> 131 #ifdef BCM_WARM_BOOT_SUPPORT 132 #include <bcm_int/esw/stg.h> 133 #include <bcm_int/esw/field.h> 134 #include <bcm_int/esw/mpls.h> 135 #include <bcm_int/esw/oam.h> 136 #include <bcm_int/esw/bfd.h> 137 #include <bcm_int/esw/qos.h> 138 #include <bcm_int/esw/trill.h> 139 #include <bcm_int/esw/subport.h> 140 #include <bcm_int/esw/failover.h> 141 #include <bcm_int/esw/proxy.h> 142 #include <bcm_int/esw/l2gre.h> 143 #include <bcm_int/esw/tsn.h> 144 #ifdef BCM_SABER2_SUPPORT 145 #include <bcm_int/common/sat.h> 146 #endif 147 #if defined(BCM_TRIUMPH2_SUPPORT) 148 #include <bcm_int/esw/xgs4.h> 149 #include <bcm_int/esw/vxlan.h> 150 #include <bcm_int/esw/mim.h> 151 #endif 152 #if defined(BCM_TRIDENT3_SUPPORT) 153 #include <bcm_int/esw/flow.h> 154 #include <bcm_int/esw/hash.h> 155 #endif 156 #include <bcm_int/esw/multicast.h> 157 #include <bcm_int/esw/stack.h> 158 #include <bcm_int/esw/stat.h> 159 #include <bcm_int/esw/niv.h> 160 #include <bcm_int/esw/fcoe.h> 161 #ifdef BCM_IPFIX_SUPPORT 162 #include <bcm/ipfix.h> 163 #include <bcm_int/esw/ipfix.h> 164 #endif 165 #include <bcm/time.h> 166 #include <bcm_int/common/time.h> 167 #ifdef BCM_TOMAHAWK3_SUPPORT 168 #include <bcm_int/esw/latency_monitor.h> 169 #endif 170 #endif /* BCM_WARM_BOOT_SUPPORT */ 171 172 #if defined(BCM_XGS3_SWITCH_SUPPORT) 173 #include <bcm_int/esw/firebolt.h> 174 #include <bcm_int/esw/trx.h> 175 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 176 #if defined(BCM_TRX_SWITCH_SUPPORT) 177 #include <bcm_int/esw/trx.h> 178 #endif /* BCM_TRX_SUPPORT */ 179 #ifdef BCM_TRX_SUPPORT 180 #include <bcm_int/esw/trx.h> 181 #endif /* BCM_TRX_SUPPORT */ 182 183 #if defined(BCM_TRIUMPH_SUPPORT) 184 #include <bcm_int/esw/triumph.h> 185 #endif /* BCM_TRIUMPH_SUPPORT */ 186 #if defined(BCM_TRIUMPH2_SUPPORT) 187 #include <bcm_int/esw/triumph2.h> 188 #endif /* BCM_TRIUMPH2_SUPPORT */ 189 #ifdef BCM_TRIDENT_SUPPORT 190 #include <bcm_int/esw/trident.h> 191 #endif /* BCM_TRIDENT_SUPPORT */ 192 #ifdef BCM_HELIX5_SUPPORT 193 #include <bcm_int/esw/helix5.h> 194 #endif /* BCM_HELIX5_SUPPORT */ 195 #ifdef BCM_TRIDENT3_SUPPORT 196 #include <bcm_int/esw/trident3.h> 197 #endif /* BCM_TRIDENT3_SUPPORT */ 198 #ifdef BCM_TOMAHAWK_SUPPORT 199 #include <bcm_int/esw/tomahawk.h> 200 #include <bcm_int/esw/range.h> 201 #endif /* BCM_TOMAHAWK_SUPPORT */ 202 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 203 #include <bcm_int/esw/tomahawk2.h> 204 #endif /* BCM_TOMAHAWK2_SUPPORT */ 205 #ifdef BCM_TRIDENT2_SUPPORT 206 #include <bcm_int/esw/trident2.h> 207 #endif /* BCM_TRIDENT2_SUPPORT */ 208 #ifdef BCM_TRIUMPH3_SUPPORT 209 #include <bcm_int/esw/triumph3.h> 210 #endif /* BCM_TRIUMPH3_SUPPORT */ 211 #ifdef BCM_GREYHOUND_SUPPORT 212 #include <bcm_int/esw/greyhound.h> 213 #endif /* BCM_GREYHOUND_SUPPORT */ 214 #if defined(BCM_HGPROXY_COE_SUPPORT) 215 #include <bcm_int/esw/xgs5.h> 216 #endif /* BCM_HGPROXY_COE_SUPPORT */ 217 #ifdef BCM_HURRICANE3_SUPPORT 218 #include <bcm_int/esw/hurricane3.h> 219 #endif /* BCM_HURRICANE3_SUPPORT */ 220 #ifdef BCM_GREYHOUND2_SUPPORT 221 #include <bcm_int/esw/greyhound2.h> 222 #endif /* BCM_GREYHOUND_SUPPORT */ 223 224 #ifdef BCM_FLOWTRACKER_SUPPORT 225 #include <bcm_int/esw/flowtracker/ft_group.h> 226 #endif /* BCM_FLOWTRACKER_SUPPORT */ 227 228 229 #if defined(BCM_TRIUMPH3_SUPPORT) 230 #include <bcm_int/bst.h> 231 #endif 232 233 #if defined(BCM_COLLECTOR_SUPPORT) 234 #include <bcm_int/esw/collector.h> 235 #endif 236 237 #if defined(INCLUDE_TELEMETRY) 238 #include <bcm_int/esw/telemetry.h> 239 #endif /* INCLUDE_TELEMETRY */ 240 241 #if defined(INCLUDE_REGEX) 242 #include <bcm_int/esw/fb4regex.h> 243 #endif /* INCLUDE_REGEX */ 244 245 #include <bcm_int/control.h> 246 #include <bcm_int/esw/switch.h> 247 #include <bcm_int/esw_dispatch.h> 248 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 249 defined(BCM_HURRICANE3_SUPPORT) 250 #include <bcm_int/esw/policer.h> 251 #endif 252 #include <bcm_int/esw/lpmv6.h> 253 #if defined(BCM_TIMESYNC_V3_SUPPORT) || \ 254 defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 255 #include <bcm_int/esw/timesync.h> 256 #endif 257 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) 258 #include <bcm_int/esw/extender.h> 259 #endif 260 #if defined(BCM_ESW_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) && \ 261 (defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT)) 262 #include <soc/sbusdma.h> 263 #endif 264 #include <soc/fifodma.h> 265 #include <soc/mem.h> 266 267 #if defined(BCM_SABER2_SUPPORT) 268 #include <soc/portmod/portmod.h> 269 #include <soc/portmod/portmod_internal.h> 270 #endif 271 #if defined(PORTMOD_SUPPORT) 272 #include <soc/phy/phymod_sim.h> 273 #endif 274 #if defined(INCLUDE_XFLOW_MACSEC) 275 #include <bcm_int/common/xflow_macsec_cmn.h> 276 #endif 277 #if defined(CANCUN_SUPPORT) 278 #include <soc/esw/cancun.h> 279 #endif 280 281 #ifdef ALPM_ENABLE 282 #include <bcm_int/esw/alpm.h> 283 #include <bcm_int/esw/alpm_util.h> 284 #endif 285 #include <bcm_int/esw/flowtracker.h> 286 #include <bcm_int/esw/ifa.h> 287 #if defined(BCM_TOMAHAWK3_SUPPORT) && defined(INCLUDE_SUM) 288 #include <bcm_int/common/sum.h> 289 #endif 290 291 /* chip field */ 292 #define FB SOC_INFO_CHIP_FB 293 #define FB2 SOC_INFO_CHIP_FIREBOLT2 294 #define FH SOC_INFO_CHIP_FHX 295 #define HXFX SOC_INFO_CHIP_FX_HX 296 #define BR SOC_INFO_CHIP_BRADLEY 297 #define GW SOC_INFO_CHIP_GOLDWING 298 #define HBGW SOC_INFO_CHIP_HB_GW 299 #define RP SOC_INFO_CHIP_RAPTOR 300 #define TR SOC_INFO_CHIP_TRIUMPH 301 #define RV SOC_INFO_CHIP_RAVEN 302 #define SC SOC_INFO_CHIP_SCORPION 303 #define TRX SOC_INFO_CHIP_TRX 304 #define HK SOC_INFO_CHIP_HAWKEYE 305 #define TRVL SOC_INFO_CHIP_TR_VL 306 #define SCQ SOC_INFO_CHIP_SC_CQ 307 #define TR2 SOC_INFO_CHIP_TRIUMPH2 308 #define AP SOC_INFO_CHIP_APOLLO 309 #define VL SOC_INFO_CHIP_VALKYRIE 310 #define VL2 SOC_INFO_CHIP_VALKYRIE2 311 #define EN SOC_INFO_CHIP_ENDURO 312 #define TD SOC_INFO_CHIP_TRIDENT 313 #define TT SOC_INFO_CHIP_TITAN 314 #define TT2 SOC_INFO_CHIP_TITAN2 315 #define HU SOC_INFO_CHIP_HURRICANE 316 #define HU2 SOC_INFO_CHIP_HURRICANE2 317 #define TR3 SOC_INFO_CHIP_TRIUMPH3 318 #define HX4 SOC_INFO_CHIP_HELIX4 319 #define KT SOC_INFO_CHIP_KATANA 320 #define KT2 SOC_INFO_CHIP_KATANA2 321 #define TD2 SOC_INFO_CHIP_TRIDENT2 322 #define TH SOC_INFO_CHIP_TOMAHAWK 323 #define TD2P SOC_INFO_CHIP_TRIDENT2PLUS 324 325 #if defined(BCM_TOMAHAWK_SUPPORT) 326 _bcm_switch_tflow_mode_t _bcm_switch_tflow_mode_info[BCM_MAX_NUM_UNITS]; 327 #endif 328 329 /* 330 * Function: 331 * _bcm_esw_switch_control_gport_resolve 332 * Description: 333 * Decodes local physical port from a gport 334 * Parameters: 335 * unit - StrataSwitch PCI device unit number (driver internal). 336 * gport - a gport to decode 337 * port - (Out) Local physical port encoded in gport 338 * Returns: 339 * BCM_E_xxxx 340 * Note 341 * In case of gport contains other then local port error will be returned. 342 */ 343 344 345 STATIC int 346 _bcm_esw_switch_control_gport_resolve(int unit, bcm_gport_t gport, bcm_port_t *port) 347 { 348 bcm_module_t modid; 349 bcm_trunk_t tgid; 350 bcm_port_t local_port; 351 int id, isMymodid; 352 #if defined(BCM_KATANA2_SUPPORT) 353 int my_modid = 0, pp_port; 354 int min_subport = SOC_INFO(unit).pp_port_index_min; 355 int max_subport = SOC_INFO(unit).pp_port_index_max; 356 #endif 357 #if defined(BCM_KATANA2_SUPPORT) || defined(BCM_HGPROXY_COE_SUPPORT) 358 int is_local_subport = FALSE; 359 #endif 360 361 if (NULL == port) { 362 return BCM_E_PARAM; 363 } 364 365 BCM_IF_ERROR_RETURN( 366 _bcm_esw_gport_resolve(unit, gport, &modid, &local_port, &tgid, &id)); 367 368 369 #if defined(BCM_HGPROXY_COE_SUPPORT) 370 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 371 BCM_GPORT_IS_SET(gport) && 372 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, gport)) { 373 374 if(_bcm_xgs5_subport_coe_gport_local(unit, gport)) { 375 is_local_subport = TRUE; 376 } 377 378 if (is_local_subport == FALSE) { 379 return BCM_E_PORT; 380 } 381 382 BCM_IF_ERROR_RETURN( 383 _bcmi_coe_subport_physical_port_get(unit, 384 gport, 385 port)); 386 387 } else 388 #endif 389 390 #if defined(BCM_KATANA2_SUPPORT) 391 if (soc_feature(unit, soc_feature_linkphy_coe) || 392 soc_feature(unit, soc_feature_linkphy_coe)) { 393 BCM_IF_ERROR_RETURN(bcm_esw_stk_my_modid_get(unit, &my_modid)); 394 if (BCM_GPORT_IS_SET(gport) && 395 _BCM_KT2_GPORT_IS_LINKPHY_OR_SUBTAG_SUBPORT_GPORT(unit, gport)) { 396 if (_bcm_kt2_mod_is_coe_mod_check(unit, modid) == BCM_E_NONE) { 397 pp_port = BCM_GPORT_SUBPORT_PORT_GET(gport); 398 #if defined BCM_METROLITE_SUPPORT 399 if (soc_feature(unit, soc_feature_discontinuous_pp_port)) { 400 if (_SOC_IS_PP_PORT_LINKPHY_SUBTAG(unit, pp_port)) { 401 is_local_subport = TRUE; 402 *port = pp_port; 403 } 404 } else 405 #endif 406 { 407 if ((pp_port >= min_subport) && 408 (pp_port <= max_subport)) { 409 is_local_subport = TRUE; 410 *port = pp_port; 411 } 412 } 413 } 414 if (is_local_subport == FALSE) { 415 return BCM_E_PORT; 416 } 417 } 418 } 419 #endif 420 421 #if defined(BCM_KATANA2_SUPPORT) || defined(BCM_HGPROXY_COE_SUPPORT) 422 if (is_local_subport) { 423 /* Local subport assigned above */ 424 } else 425 #endif 426 { 427 if ((BCM_TRUNK_INVALID != tgid) || (-1 != id)) { 428 return BCM_E_PARAM; 429 } 430 /* Check if modid is local */ 431 BCM_IF_ERROR_RETURN( 432 _bcm_esw_modid_is_local(unit, modid, &isMymodid)); 433 434 if (isMymodid != TRUE) { 435 return BCM_E_PORT; 436 } 437 438 *port = local_port; 439 } 440 return (BCM_E_NONE); 441 } 442 443 444 #ifdef BCM_XGS12_SWITCH_SUPPORT 445 /* 446 * Function: 447 * _bcm_hashselect_set 448 * Description: 449 * Set the Hash Select for L2. L3 and Multipath types 450 * are not supported on these devices. 451 * Parameters: 452 * unit - StrataSwitch PCI device unit number (driver internal). 453 * type - The desired configuration parameter to set. 454 * arg - BCM_HASH_* 455 * Returns: 456 * BCM_E_xxxx 457 */ 458 459 STATIC int 460 _bcm_hashselect_set(int unit, 461 bcm_switch_control_t type, 462 int arg) 463 { 464 uint32 hash_control, val=0; 465 466 if (type != bcmSwitchHashL2) { 467 return BCM_E_UNAVAIL; 468 } 469 470 switch (arg) { 471 case BCM_HASH_ZERO: 472 val = XGS_HASH_ZERO; 473 break; 474 case BCM_HASH_LSB: 475 val = XGS_HASH_LSB; 476 break; 477 case BCM_HASH_CRC16L: 478 val = XGS_HASH_CRC16_LOWER; 479 break; 480 case BCM_HASH_CRC16U: 481 val = XGS_HASH_CRC16_UPPER; 482 break; 483 case BCM_HASH_CRC32L: 484 val = XGS_HASH_CRC32_LOWER; 485 break; 486 case BCM_HASH_CRC32U: 487 val = XGS_HASH_CRC32_UPPER; 488 break; 489 default: 490 return BCM_E_PARAM; 491 } 492 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 493 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 494 HASH_SELECTf, val); 495 BCM_IF_ERROR_RETURN(WRITE_HASH_CONTROLr(unit, hash_control)); 496 497 return BCM_E_NONE; 498 } 499 500 /* 501 * Function: 502 * _bcm_hashselect_get 503 * Description: 504 * Get the current Hash Select settings. Value returned 505 * is of the form BCM_HASH_*. 506 * All switch chip ports are configured with the same settings. 507 * Parameters: 508 * unit - StrataSwitch PCI device unit number (driver internal). 509 * type - The desired configuration parameter to retrieve. 510 * arg - Pointer to where the retrieved value will be written. 511 * Returns: 512 * BCM_E_xxxx 513 */ 514 515 STATIC int 516 _bcm_hashselect_get(int unit, 517 bcm_switch_control_t type, 518 int *arg) 519 { 520 uint32 hash_control, val=0; 521 522 if (type != bcmSwitchHashL2) { 523 return BCM_E_UNAVAIL; 524 } 525 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 526 val = soc_reg_field_get(unit, HASH_CONTROLr, 527 hash_control, HASH_SELECTf); 528 switch (val) { 529 case XGS_HASH_ZERO: 530 *arg = BCM_HASH_ZERO; 531 break; 532 case XGS_HASH_LSB: 533 *arg = BCM_HASH_LSB; 534 break; 535 case XGS_HASH_CRC16_LOWER: 536 *arg = BCM_HASH_CRC16L; 537 break; 538 case XGS_HASH_CRC16_UPPER: 539 *arg = BCM_HASH_CRC16U; 540 break; 541 case XGS_HASH_CRC32_LOWER: 542 *arg = BCM_HASH_CRC32L; 543 break; 544 case XGS_HASH_CRC32_UPPER: 545 *arg = BCM_HASH_CRC32U; 546 break; 547 } 548 return BCM_E_NONE; 549 } 550 551 /* 552 * CPU control register set/get functions. 553 * If port is specified (port < 0), only val or ival is used as appropriate. 554 * Skip stack ports if port is not specified. 555 */ 556 557 STATIC int 558 _bcm_sw_cc_get(int unit, bcm_port_t port, uint64 *val) 559 { 560 if (IS_E_PORT(unit, port)) { 561 return READ_CPU_CONTROLr(unit, port, val); 562 } else if (IS_HG_PORT(unit, port)) { 563 return READ_ICPU_CONTROLr(unit, port, val); 564 } 565 566 return BCM_E_PORT; 567 } 568 569 STATIC int 570 _bcm_sw_cc_set(int unit, bcm_port_t port, uint64 val) 571 { 572 if (IS_E_PORT(unit, port)) { 573 return WRITE_CPU_CONTROLr(unit, port, val); 574 } else if (IS_HG_PORT(unit, port)) { 575 return WRITE_ICPU_CONTROLr(unit, port, val); 576 } 577 578 return BCM_E_PORT; 579 } 580 581 /* Map unit/port/type to a field in CPU CONTROL. Returns INVALIDf on error */ 582 583 STATIC soc_field_t 584 _bcm_sw_field_get(int unit, bcm_port_t port, bcm_switch_control_t type) 585 { 586 /* Choose the field */ 587 switch(type) { 588 case bcmSwitchCpuProtocolPrio: 589 return CPU_PROTOCOL_PRIORITYf; 590 break; 591 case bcmSwitchCpuUnknownPrio: 592 return CPU_LKUPFAIL_PRIORITYf; 593 break; 594 case bcmSwitchCpuDefaultPrio: 595 return CPU_DEFAULT_PRIORITYf; 596 break; 597 case bcmSwitchL2StaticMoveToCpu: 598 return STATICMOVE_TOCPUf; 599 break; 600 case bcmSwitchUnknownVlanToCpu: 601 return UVLAN_TOCPUf; 602 break; 603 case bcmSwitchUnknownIpmcToCpu: 604 return UIPMC_TOCPUf; 605 break; 606 case bcmSwitchUnknownMcastToCpu: 607 return UMC_TOCPUf; 608 break; 609 case bcmSwitchUnknownUcastToCpu: 610 return UUCAST_TOCPUf; 611 break; 612 case bcmSwitchL3HeaderErrToCpu: 613 return L3ERR_TOCPUf; 614 break; 615 case bcmSwitchUnknownL3SrcToCpu: 616 return UNRESOLVEDL3SRC_TOCPUf; 617 break; 618 case bcmSwitchUnknownL3DestToCpu: 619 return L3DSTMISS_TOCPUf; 620 break; 621 case bcmSwitchIpmcPortMissToCpu: 622 return IPMCPORTMISS_TOCPUf; 623 break; 624 default: 625 break; 626 } 627 628 return INVALIDf; 629 } 630 #endif 631 632 /* OLP configuration book keeping */ 633 _bcm_switch_olp_bookeeping_t _bcm_switch_olp_bk_info[BCM_MAX_NUM_UNITS]; 634 635 #ifdef BCM_WARM_BOOT_SUPPORT 636 637 /* 638 * Function: 639 * _bcm_esw_switch_tflow_wb_scache_size_get 640 * Purpose: 641 * Returns required scache size for tflow mode 642 * Parameters: 643 * unit - (IN) Unit number. 644 * req_scache_size - (OUT) Request scache size 645 * Returns: 646 * BCM_E_XXX 647 * Notes: 648 */ 649 STATIC int 650 _bcm_esw_switch_tflow_wb_scache_size_get(int unit, int *req_scache_size) 651 { 652 653 if (soc_feature(unit,soc_feature_th_tflow)) { 654 #if defined(BCM_TOMAHAWK_SUPPORT) 655 BCM_IF_ERROR_RETURN( 656 bcm_th_switch_tflow_wb_scache_size_get(unit, req_scache_size)); 657 #endif /* defined(BCM_TOMAHAWK_SUPPORT) */ 658 } 659 return BCM_E_NONE; 660 } 661 662 /* 663 * Function: 664 * _bcm_esw_switch_tflow_wb_alloc 665 * Purpose: 666 * Allocates required scache size for the tflow mode recovery 667 * Parameters: 668 * unit - (IN) Unit number. 669 * Returns: 670 * BCM_E_XXX 671 * Notes: 672 */ 673 STATIC int 674 _bcm_esw_switch_tflow_wb_alloc(int unit) 675 { 676 int rv; 677 uint8 *scache_ptr; 678 soc_scache_handle_t scache_handle; 679 int req_scache_size = 0; 680 681 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 682 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_TFLOW); 683 684 rv = _bcm_esw_switch_tflow_wb_scache_size_get(unit, &req_scache_size); 685 BCM_IF_ERROR_RETURN(rv); 686 687 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 688 req_scache_size, &scache_ptr, BCM_SWITCH_WB_TFLOW_DEFAULT_VERSION, NULL); 689 690 if (BCM_E_NOT_FOUND == rv) { 691 /* Proceed with Level 1 Warm Boot */ 692 rv = BCM_E_NONE; 693 } 694 695 BCM_IF_ERROR_RETURN(rv); 696 697 return BCM_E_NONE; 698 } 699 700 /* 701 * Function: 702 * _bcm_esw_switch_tflow_scache_sync 703 * Purpose: 704 * Syncs tflow warmboot state to scache 705 * Parameters: 706 * unit - (IN) Unit number. 707 * Returns: 708 * BCM_E_XXX 709 * Notes: 710 */ 711 int 712 _bcm_esw_switch_tflow_scache_sync(int unit) 713 { 714 uint8 *scache_ptr; 715 soc_scache_handle_t scache_handle; 716 717 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 718 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_TFLOW); 719 720 BCM_IF_ERROR_RETURN 721 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 722 0, &scache_ptr, 723 BCM_SWITCH_WB_TFLOW_DEFAULT_VERSION, NULL)); 724 if (soc_feature(unit,soc_feature_th_tflow)) { 725 #if defined(BCM_TOMAHAWK_SUPPORT) 726 BCM_IF_ERROR_RETURN(bcm_th_switch_tflow_wb_sync(unit, &scache_ptr)); 727 #endif /* defined(BCM_TOMAHAWK_SUPPORT) */ 728 } 729 730 return BCM_E_NONE; 731 } 732 733 /* 734 * Function: 735 * _bcm_esw_switch_tflow_reinit 736 * Purpose: 737 * Recovers tflow warmboot state from scache 738 * Parameters: 739 * unit - (IN) Unit number. 740 * Returns: 741 * BCM_E_XXX 742 * Notes: 743 */ 744 STATIC int 745 _bcm_esw_switch_tflow_reinit(int unit) 746 { 747 int rv = BCM_E_INTERNAL; 748 uint8 *scache_ptr; 749 uint16 recovered_ver = 0; 750 soc_scache_handle_t scache_handle; 751 752 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 753 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_TFLOW); 754 755 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 756 0, &scache_ptr, 757 BCM_SWITCH_WB_TFLOW_DEFAULT_VERSION, &recovered_ver); 758 759 if (BCM_E_NOT_FOUND == rv) { 760 BCM_IF_ERROR_RETURN(_bcm_esw_switch_tflow_wb_alloc(unit)); 761 return BCM_E_NONE; 762 } else if (BCM_E_NONE == rv) { 763 if (recovered_ver >= BCM_SWITCH_WB_TFLOW_VERSION_1_0) { 764 if (soc_feature(unit,soc_feature_th_tflow)) { 765 #if defined(BCM_TOMAHAWK_SUPPORT) 766 BCM_IF_ERROR_RETURN(bcm_th_switch_tflow_wb_reinit(unit, &scache_ptr)); 767 #endif /* defined(BCM_TOMAHAWK_SUPPORT) */ 768 } 769 } 770 if (recovered_ver < BCM_SWITCH_WB_TFLOW_DEFAULT_VERSION) { 771 BCM_IF_ERROR_RETURN(_bcm_esw_switch_tflow_wb_alloc(unit)); 772 } 773 } 774 775 return rv; 776 } 777 778 779 780 /* 781 * Function: 782 * _bcm_esw_switch_agm_wb_scache_size_get 783 * Purpose: 784 * Returns required scache size for agm module 785 * Parameters: 786 * unit - (IN) Unit number. 787 * req_scache_size - (OUT) Request scache size 788 * Returns: 789 * BCM_E_XXX 790 * Notes: 791 */ 792 STATIC int 793 _bcm_esw_switch_agm_wb_scache_size_get(int unit, int *req_scache_size) 794 { 795 if (soc_feature(unit,soc_feature_agm)) { 796 #if defined(BCM_TOMAHAWK_SUPPORT) 797 BCM_IF_ERROR_RETURN( 798 bcm_th_switch_agm_wb_scache_size_get(unit, req_scache_size)); 799 #endif /* defined(BCM_TOMAHAWK_SUPPORT) */ 800 } 801 return BCM_E_NONE; 802 } 803 804 /* 805 * Function: 806 * _bcm_esw_switch_agm_wb_alloc 807 * Purpose: 808 * Allocates required scache size for the agm module recovery 809 * Parameters: 810 * unit - (IN) Unit number. 811 * Returns: 812 * BCM_E_XXX 813 * Notes: 814 */ 815 STATIC int 816 _bcm_esw_switch_agm_wb_alloc(int unit) 817 { 818 int rv; 819 uint8 *scache_ptr; 820 soc_scache_handle_t scache_handle; 821 int req_scache_size = 0; 822 823 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 824 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_AGM); 825 826 rv = _bcm_esw_switch_agm_wb_scache_size_get(unit, &req_scache_size); 827 BCM_IF_ERROR_RETURN(rv); 828 829 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 830 req_scache_size, &scache_ptr, BCM_SWITCH_WB_AGM_DEFAULT_VERSION, NULL); 831 832 if (BCM_E_NOT_FOUND == rv) { 833 /* Proceed with Level 1 Warm Boot */ 834 rv = BCM_E_NONE; 835 } 836 837 BCM_IF_ERROR_RETURN(rv); 838 839 return BCM_E_NONE; 840 } 841 842 /* 843 * Function: 844 * _bcm_esw_switch_agm_scache_sync 845 * Purpose: 846 * Syncs agm warmboot state to scache 847 * Parameters: 848 * unit - (IN) Unit number. 849 * Returns: 850 * BCM_E_XXX 851 * Notes: 852 */ 853 int 854 _bcm_esw_switch_agm_scache_sync(int unit) 855 { 856 uint8 *scache_ptr; 857 soc_scache_handle_t scache_handle; 858 859 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 860 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_AGM); 861 862 BCM_IF_ERROR_RETURN 863 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 864 0, &scache_ptr, 865 BCM_SWITCH_WB_AGM_DEFAULT_VERSION, NULL)); 866 if (soc_feature(unit,soc_feature_agm)) { 867 #if defined(BCM_TOMAHAWK_SUPPORT) 868 BCM_IF_ERROR_RETURN(bcm_th_switch_agm_wb_sync(unit, &scache_ptr)); 869 #endif /* defined(BCM_TOMAHAWK_SUPPORT) */ 870 } 871 872 return BCM_E_NONE; 873 } 874 875 /* 876 * Function: 877 * _bcm_esw_switch_agm_reinit 878 * Purpose: 879 * Recovers agm warmboot state from scache 880 * Parameters: 881 * unit - (IN) Unit number. 882 * Returns: 883 * BCM_E_XXX 884 * Notes: 885 */ 886 STATIC int 887 _bcm_esw_switch_agm_reinit(int unit) 888 { 889 int rv = BCM_E_INTERNAL; 890 uint8 *scache_ptr; 891 uint16 recovered_ver = 0; 892 soc_scache_handle_t scache_handle; 893 894 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 895 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_AGM); 896 897 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 898 0, &scache_ptr, 899 BCM_SWITCH_WB_AGM_DEFAULT_VERSION, &recovered_ver); 900 901 if (BCM_E_NOT_FOUND == rv) { 902 #if defined(BCM_TOMAHAWK_SUPPORT) 903 BCM_IF_ERROR_RETURN(bcm_th_switch_agm_init(unit)); 904 #endif 905 BCM_IF_ERROR_RETURN(_bcm_esw_switch_agm_wb_alloc(unit)); 906 return BCM_E_NONE; 907 } else if (BCM_E_NONE == rv) { 908 if (recovered_ver >= BCM_SWITCH_WB_AGM_VERSION_1_0) { 909 if (soc_feature(unit,soc_feature_agm)) { 910 #if defined(BCM_TOMAHAWK_SUPPORT) 911 BCM_IF_ERROR_RETURN(bcm_th_switch_agm_wb_reinit(unit, &scache_ptr)); 912 #endif /* defined(BCM_TOMAHAWK_SUPPORT) */ 913 } 914 } 915 if (recovered_ver < BCM_SWITCH_WB_AGM_DEFAULT_VERSION) { 916 BCM_IF_ERROR_RETURN(_bcm_esw_switch_agm_wb_alloc(unit)); 917 } 918 } 919 920 return rv; 921 } 922 923 /* 924 * Function: 925 * _bcm_esw_switch_hash_wb_scache_size_get 926 * Purpose: 927 * Returns required scache size for switch hash module 928 * Parameters: 929 * unit - (IN) Unit number. 930 * req_scache_size - (OUT) Request scache size 931 * Returns: 932 * BCM_E_XXX 933 * Notes: 934 */ 935 STATIC int 936 _bcm_esw_switch_hash_wb_scache_size_get(int unit, int *req_scache_size) 937 { 938 if (soc_feature(unit,soc_feature_flex_hashing)) { 939 #if defined(BCM_TRIDENT2_SUPPORT) 940 BCM_IF_ERROR_RETURN( 941 bcmi_td2_switch_wb_hash_entry_scache_size_get(unit, req_scache_size)); 942 #endif /* defined(BCM_TRIDENT2_SUPPORT) */ 943 } 944 return BCM_E_NONE; 945 } 946 947 /* 948 * Function: 949 * _bcm_esw_switch_hash_wb_alloc 950 * Purpose: 951 * Allocates required scache size for the switch hash module recovery 952 * Parameters: 953 * unit - (IN) Unit number. 954 * Returns: 955 * BCM_E_XXX 956 * Notes: 957 */ 958 STATIC int 959 _bcm_esw_switch_hash_wb_alloc(int unit) 960 { 961 int rv; 962 uint8 *scache_ptr; 963 soc_scache_handle_t scache_handle; 964 int req_scache_size = 0; 965 966 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 967 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_FLEXHASH); 968 969 rv = _bcm_esw_switch_hash_wb_scache_size_get(unit, &req_scache_size); 970 BCM_IF_ERROR_RETURN(rv); 971 972 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 973 req_scache_size, &scache_ptr, BCM_SWITCH_WB_FLEXHASH_DEFAULT_VERSION, NULL); 974 975 if (BCM_E_NOT_FOUND == rv) { 976 /* Proceed with Level 1 Warm Boot */ 977 rv = BCM_E_NONE; 978 } 979 980 BCM_IF_ERROR_RETURN(rv); 981 982 return BCM_E_NONE; 983 } 984 985 /* 986 * Function: 987 * _bcm_esw_switch_hash_scache_sync 988 * Purpose: 989 * Syncs switch hash warmboot state to scache 990 * Parameters: 991 * unit - (IN) Unit number. 992 * Returns: 993 * BCM_E_XXX 994 * Notes: 995 */ 996 int 997 _bcm_esw_switch_hash_scache_sync(int unit) 998 { 999 uint8 *scache_ptr; 1000 soc_scache_handle_t scache_handle; 1001 1002 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1003 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_FLEXHASH); 1004 1005 BCM_IF_ERROR_RETURN 1006 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1007 0, &scache_ptr, 1008 BCM_SWITCH_WB_FLEXHASH_DEFAULT_VERSION, NULL)); 1009 if (soc_feature(unit,soc_feature_flex_hashing)) { 1010 #if defined(BCM_TRIDENT2_SUPPORT) 1011 BCM_IF_ERROR_RETURN(bcmi_td2_switch_wb_hash_entry_sync(unit, &scache_ptr)); 1012 #endif /* defined(BCM_TRIDENT2_SUPPORT) */ 1013 } 1014 1015 return BCM_E_NONE; 1016 } 1017 1018 /* 1019 * Function: 1020 * _bcm_esw_switch_hash_reinit 1021 * Purpose: 1022 * Recovers switch hash warmboot state from scache 1023 * Parameters: 1024 * unit - (IN) Unit number. 1025 * Returns: 1026 * BCM_E_XXX 1027 * Notes: 1028 */ 1029 STATIC int 1030 _bcm_esw_switch_hash_reinit(int unit) 1031 { 1032 int rv = BCM_E_INTERNAL; 1033 uint8 *scache_ptr; 1034 uint16 recovered_ver = 0; 1035 soc_scache_handle_t scache_handle; 1036 1037 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1038 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_FLEXHASH); 1039 1040 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1041 0, &scache_ptr, 1042 BCM_SWITCH_WB_FLEXHASH_DEFAULT_VERSION, &recovered_ver); 1043 1044 if (BCM_E_NOT_FOUND == rv) { 1045 return _bcm_esw_switch_hash_wb_alloc(unit); 1046 } else if (BCM_E_NONE == rv) { 1047 if (recovered_ver >= BCM_SWITCH_WB_FLEXHASH_VERSION_1_0) { 1048 if (soc_feature(unit,soc_feature_flex_hashing)) { 1049 #if defined(BCM_TRIDENT2_SUPPORT) 1050 BCM_IF_ERROR_RETURN(bcmi_td2_switch_wb_hash_entry_reinit(unit, &scache_ptr)); 1051 #endif /* defined(BCM_TRIDENT2_SUPPORT) */ 1052 } 1053 } 1054 if (recovered_ver >= BCM_SWITCH_WB_FLEXHASH_VERSION_1_1) { 1055 if (soc_feature(unit,soc_feature_flex_hashing)) { 1056 #if defined(BCM_TOMAHAWK_SUPPORT) 1057 if (SOC_IS_TOMAHAWKX(unit)) { 1058 BCM_IF_ERROR_RETURN 1059 (bcmi_th_switch_wb_hash_entry_reinit(unit, &scache_ptr)); 1060 } 1061 #endif /*BCM_TOMAHAWK_SUPPORT*/ 1062 } 1063 } 1064 } 1065 1066 return rv; 1067 } 1068 1069 /* 1070 * Function: 1071 * bcmi_esw_switch_l2_wb_scache_size_get 1072 * Purpose: 1073 * Returns required scache size for L2 part 1074 * Parameters: 1075 * unit - (IN) Unit number. 1076 * req_scache_size - (OUT) Request scache size 1077 * Returns: 1078 * BCM_E_XXX 1079 * Notes: 1080 */ 1081 STATIC int 1082 bcmi_esw_switch_l2_wb_scache_size_get(int unit, int *req_scache_size) 1083 { 1084 SOC_IF_ERROR_RETURN(soc_l2x_wb_scache_size_get(unit, req_scache_size)); 1085 return BCM_E_NONE; 1086 } 1087 1088 /* 1089 * Function: 1090 * bcmi_esw_switch_l2_wb_alloc 1091 * Purpose: 1092 * Allocates required scache size for the L2 part recovery 1093 * Parameters: 1094 * unit - (IN) Unit number. 1095 * Returns: 1096 * BCM_E_XXX 1097 * Notes: 1098 */ 1099 STATIC int 1100 bcmi_esw_switch_l2_wb_alloc(int unit) 1101 { 1102 int rv; 1103 uint8 *scache_ptr; 1104 soc_scache_handle_t scache_handle; 1105 int req_scache_size = 0; 1106 1107 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1108 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_L2); 1109 1110 rv = bcmi_esw_switch_l2_wb_scache_size_get(unit, &req_scache_size); 1111 BCM_IF_ERROR_RETURN(rv); 1112 1113 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 1114 req_scache_size, &scache_ptr, BCM_SWITCH_WB_L2_DEFAULT_VERSION, NULL); 1115 1116 if (BCM_E_NOT_FOUND == rv) { 1117 /* Proceed with Level 1 Warm Boot */ 1118 rv = BCM_E_NONE; 1119 } 1120 1121 BCM_IF_ERROR_RETURN(rv); 1122 1123 return BCM_E_NONE; 1124 } 1125 1126 /* 1127 * Function: 1128 * bcmi_esw_switch_l2_scache_sync 1129 * Purpose: 1130 * Syncs L2 part warmboot state to scache 1131 * Parameters: 1132 * unit - (IN) Unit number. 1133 * Returns: 1134 * BCM_E_XXX 1135 * Notes: 1136 */ 1137 int 1138 bcmi_esw_switch_l2_scache_sync(int unit) 1139 { 1140 uint8 *scache_ptr; 1141 soc_scache_handle_t scache_handle; 1142 1143 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1144 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_L2); 1145 1146 BCM_IF_ERROR_RETURN 1147 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1148 0, &scache_ptr, 1149 BCM_SWITCH_WB_L2_DEFAULT_VERSION, NULL)); 1150 SOC_IF_ERROR_RETURN(soc_l2x_scache_sync(unit, &scache_ptr)); 1151 1152 return BCM_E_NONE; 1153 } 1154 1155 /* 1156 * Function: 1157 * bcmi_esw_switch_l2_reinit 1158 * Purpose: 1159 * Recovers L2 part warmboot state from scache 1160 * Parameters: 1161 * unit - (IN) Unit number. 1162 * Returns: 1163 * BCM_E_XXX 1164 * Notes: 1165 */ 1166 STATIC int 1167 bcmi_esw_switch_l2_reinit(int unit) 1168 { 1169 int rv = BCM_E_INTERNAL; 1170 uint8 *scache_ptr; 1171 uint16 recovered_ver = 0; 1172 soc_scache_handle_t scache_handle; 1173 1174 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1175 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_L2); 1176 1177 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1178 0, &scache_ptr, 1179 BCM_SWITCH_WB_L2_DEFAULT_VERSION, &recovered_ver); 1180 1181 if (BCM_E_NOT_FOUND == rv) { 1182 BCM_IF_ERROR_RETURN(bcmi_esw_switch_l2_wb_alloc(unit)); 1183 return BCM_E_NONE; 1184 } else if (BCM_E_NONE == rv) { 1185 if (recovered_ver >= BCM_SWITCH_WB_L2_VERSION_1_0) { 1186 SOC_IF_ERROR_RETURN(soc_l2x_reinit(unit, &scache_ptr)); 1187 } 1188 if (recovered_ver < BCM_SWITCH_WB_L2_DEFAULT_VERSION) { 1189 BCM_IF_ERROR_RETURN(bcmi_esw_switch_l2_wb_alloc(unit)); 1190 } 1191 } 1192 1193 return rv; 1194 } 1195 1196 #ifdef BCM_HURRICANE3_SUPPORT 1197 /* 1198 * Function: 1199 * bcmi_esw_switch_misc_wb_scache_size_get 1200 * Purpose: 1201 * Returns required scache size for L2 part 1202 * Parameters: 1203 * unit - (IN) Unit number. 1204 * req_scache_size - (OUT) Request scache size 1205 * Returns: 1206 * BCM_E_XXX 1207 * Notes: 1208 */ 1209 STATIC int 1210 bcmi_esw_switch_misc_wb_scache_size_get(int unit, int *req_scache_size) 1211 { 1212 int alloc_size = 0; 1213 1214 /* bcmSwitchHashDualMoveDepth */ 1215 alloc_size += sizeof(SOC_DUAL_HASH_MOVE_MAX(unit)); 1216 1217 /* bcmSwitchHashDualMoveDepthL2 */ 1218 alloc_size += sizeof(SOC_DUAL_HASH_MOVE_MAX_L2X(unit)); 1219 1220 /* bcmSwitchHashDualMoveDepthL3 */ 1221 alloc_size += sizeof(SOC_DUAL_HASH_MOVE_MAX_L3X(unit)); 1222 1223 /* bcmSwitchHashDualMoveDepthVlan */ 1224 alloc_size += sizeof(SOC_DUAL_HASH_MOVE_MAX_VLAN(unit)); 1225 1226 /* bcmSwitchHashDualMoveDepthMpls */ 1227 alloc_size += sizeof(SOC_DUAL_HASH_MOVE_MAX_MPLS(unit)); 1228 1229 /* bcmSwitchHashDualMoveDepthEgressVlan */ 1230 alloc_size += sizeof(SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit)); 1231 1232 /* bcmSwitchL3TunnelIpV4ModeOnly */ 1233 alloc_size += sizeof(int); 1234 1235 /* bcmSwitchL2OverflowEvent */ 1236 alloc_size += sizeof(SOC_CONTROL(unit)->l2_overflow_enable); 1237 1238 *req_scache_size += alloc_size; 1239 1240 return BCM_E_NONE; 1241 } 1242 1243 /* 1244 * Function: 1245 * bcmi_esw_switch_misc_wb_alloc 1246 * Purpose: 1247 * Allocates required scache size for the L2 part recovery 1248 * Parameters: 1249 * unit - (IN) Unit number. 1250 * Returns: 1251 * BCM_E_XXX 1252 * Notes: 1253 */ 1254 STATIC int 1255 bcmi_esw_switch_misc_wb_alloc(int unit) 1256 { 1257 int rv; 1258 uint8 *scache_ptr; 1259 soc_scache_handle_t scache_handle; 1260 int req_scache_size = 0; 1261 1262 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1263 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_MISC); 1264 1265 rv = bcmi_esw_switch_misc_wb_scache_size_get(unit, &req_scache_size); 1266 BCM_IF_ERROR_RETURN(rv); 1267 1268 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 1269 req_scache_size, &scache_ptr, 1270 BCM_SWITCH_WB_MISC_DEFAULT_VERSION, NULL); 1271 1272 if (BCM_E_NOT_FOUND == rv) { 1273 /* Proceed with Level 1 Warm Boot */ 1274 rv = BCM_E_NONE; 1275 } 1276 1277 return rv; 1278 } 1279 1280 /* 1281 * Function: 1282 * bcmi_esw_switch_misc_scache_sync 1283 * Purpose: 1284 * Syncs L2 part warmboot state to scache 1285 * Parameters: 1286 * unit - (IN) Unit number. 1287 * Returns: 1288 * BCM_E_XXX 1289 * Notes: 1290 */ 1291 int 1292 bcmi_esw_switch_misc_scache_sync(int unit) 1293 { 1294 uint8 *scache_ptr; 1295 int size; 1296 soc_scache_handle_t scache_handle; 1297 1298 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1299 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_MISC); 1300 1301 BCM_IF_ERROR_RETURN 1302 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1303 0, &scache_ptr, 1304 BCM_SWITCH_WB_MISC_DEFAULT_VERSION, NULL)); 1305 1306 /* bcmSwitchHashDualMoveDepth */ 1307 sal_memcpy(scache_ptr, &SOC_DUAL_HASH_MOVE_MAX(unit), 1308 sizeof(SOC_DUAL_HASH_MOVE_MAX(unit))); 1309 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX(unit)); 1310 /* bcmSwitchHashDualMoveDepthL2 */ 1311 sal_memcpy(scache_ptr, &SOC_DUAL_HASH_MOVE_MAX_L2X(unit), 1312 sizeof(SOC_DUAL_HASH_MOVE_MAX_L2X(unit))); 1313 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_L2X(unit)); 1314 /* bcmSwitchHashDualMoveDepthL3 */ 1315 sal_memcpy(scache_ptr, &SOC_DUAL_HASH_MOVE_MAX_L3X(unit), 1316 sizeof(SOC_DUAL_HASH_MOVE_MAX_L3X(unit))); 1317 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_L3X(unit)); 1318 /* bcmSwitchHashDualMoveDepthVlan */ 1319 sal_memcpy(scache_ptr, &SOC_DUAL_HASH_MOVE_MAX_VLAN(unit), 1320 sizeof(SOC_DUAL_HASH_MOVE_MAX_VLAN(unit))); 1321 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_VLAN(unit)); 1322 /* bcmSwitchHashDualMoveDepthMpls */ 1323 sal_memcpy(scache_ptr, &SOC_DUAL_HASH_MOVE_MAX_MPLS(unit), 1324 sizeof(SOC_DUAL_HASH_MOVE_MAX_MPLS(unit))); 1325 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_MPLS(unit)); 1326 /* bcmSwitchHashDualMoveDepthEgressVlan */ 1327 sal_memcpy(scache_ptr, &SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit), 1328 sizeof(SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit))); 1329 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit)); 1330 /* bcmSwitchL3TunnelIpV4ModeOnly */ 1331 soc_tunnel_term_block_size_get(unit, &size); 1332 sal_memcpy(scache_ptr, &size, sizeof(size)); 1333 scache_ptr += sizeof(size); 1334 /* bcmSwitchL2OverflowEvent */ 1335 sal_memcpy(scache_ptr, &SOC_CONTROL(unit)->l2_overflow_enable, 1336 sizeof(SOC_CONTROL(unit)->l2_overflow_enable)); 1337 1338 return BCM_E_NONE; 1339 } 1340 1341 /* 1342 * Function: 1343 * bcmi_esw_switch_misc_reinit 1344 * Purpose: 1345 * Recovers L2 part warmboot state from scache 1346 * Parameters: 1347 * unit - (IN) Unit number. 1348 * Returns: 1349 * BCM_E_XXX 1350 * Notes: 1351 */ 1352 STATIC int 1353 bcmi_esw_switch_misc_reinit(int unit) 1354 { 1355 int rv = BCM_E_INTERNAL, size; 1356 uint8 *scache_ptr; 1357 uint16 recovered_ver = 0; 1358 soc_scache_handle_t scache_handle; 1359 1360 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1361 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_MISC); 1362 1363 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1364 0, &scache_ptr, 1365 BCM_SWITCH_WB_MISC_DEFAULT_VERSION, 1366 &recovered_ver); 1367 1368 if (BCM_E_NOT_FOUND == rv) { 1369 BCM_IF_ERROR_RETURN(bcmi_esw_switch_misc_wb_alloc(unit)); 1370 return BCM_E_NONE; 1371 } else if (BCM_E_NONE == rv) { 1372 if (recovered_ver >= BCM_SWITCH_WB_MISC_VERSION_1_0) { 1373 /* bcmSwitchHashDualMoveDepth */ 1374 sal_memcpy(&SOC_DUAL_HASH_MOVE_MAX(unit), scache_ptr, 1375 sizeof(SOC_DUAL_HASH_MOVE_MAX(unit))); 1376 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX(unit)); 1377 /* bcmSwitchHashDualMoveDepthL2 */ 1378 sal_memcpy(&SOC_DUAL_HASH_MOVE_MAX_L2X(unit), scache_ptr, 1379 sizeof(SOC_DUAL_HASH_MOVE_MAX_L2X(unit))); 1380 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_L2X(unit)); 1381 /* bcmSwitchHashDualMoveDepthL3 */ 1382 sal_memcpy(&SOC_DUAL_HASH_MOVE_MAX_L3X(unit), scache_ptr, 1383 sizeof(SOC_DUAL_HASH_MOVE_MAX_L3X(unit))); 1384 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_L3X(unit)); 1385 /* bcmSwitchHashDualMoveDepthVlan */ 1386 sal_memcpy(&SOC_DUAL_HASH_MOVE_MAX_VLAN(unit), scache_ptr, 1387 sizeof(SOC_DUAL_HASH_MOVE_MAX_VLAN(unit))); 1388 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_VLAN(unit)); 1389 /* bcmSwitchHashDualMoveDepthMpls */ 1390 sal_memcpy(&SOC_DUAL_HASH_MOVE_MAX_MPLS(unit), scache_ptr, 1391 sizeof(SOC_DUAL_HASH_MOVE_MAX_MPLS(unit))); 1392 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_MPLS(unit)); 1393 /* bcmSwitchHashDualMoveDepthEgressVlan */ 1394 sal_memcpy(&SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit), scache_ptr, 1395 sizeof(SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit))); 1396 scache_ptr += sizeof(SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit)); 1397 /* bcmSwitchL3TunnelIpV4ModeOnly */ 1398 sal_memcpy(&size, scache_ptr, sizeof(size)); 1399 soc_tunnel_term_block_size_set(unit, size); 1400 scache_ptr += sizeof(size); 1401 /* bcmSwitchL2OverflowEvent */ 1402 sal_memcpy(&SOC_CONTROL(unit)->l2_overflow_enable, scache_ptr, 1403 sizeof(SOC_CONTROL(unit)->l2_overflow_enable)); 1404 } 1405 if (recovered_ver < BCM_SWITCH_WB_MISC_DEFAULT_VERSION) { 1406 BCM_IF_ERROR_RETURN(bcmi_esw_switch_misc_wb_alloc(unit)); 1407 } 1408 } 1409 1410 return rv; 1411 } 1412 #endif /* BCM_HURRICANE3_SUPPORT */ 1413 1414 /* 1415 * Function: 1416 * _bcm_esw_switch_wb_alloc 1417 * Purpose: 1418 * Allocates required scache size for the switch module recovery 1419 * Parameters: 1420 * unit - (IN) Unit number. 1421 * Returns: 1422 * BCM_E_XXX 1423 * Notes: 1424 */ 1425 STATIC int 1426 _bcm_esw_switch_wb_alloc(int unit) 1427 { 1428 if (soc_feature(unit,soc_feature_flex_hashing)) { 1429 BCM_IF_ERROR_RETURN(_bcm_esw_switch_hash_wb_alloc(unit)); 1430 } 1431 1432 if (soc_feature(unit,soc_feature_agm)) { 1433 BCM_IF_ERROR_RETURN(_bcm_esw_switch_agm_wb_alloc(unit)); 1434 } 1435 1436 if (soc_feature(unit,soc_feature_th_tflow)) { 1437 BCM_IF_ERROR_RETURN(_bcm_esw_switch_tflow_wb_alloc(unit)); 1438 } 1439 1440 #ifdef BCM_TRIDENT2_SUPPORT 1441 if (SOC_IS_TD2_TT2(unit)) { 1442 BCM_IF_ERROR_RETURN(bcmi_esw_switch_l2_wb_alloc(unit)); 1443 } 1444 #endif /* BCM_TRIDENT2_SUPPORT */ 1445 1446 #ifdef BCM_HURRICANE3_SUPPORT 1447 if (SOC_IS_HURRICANE3(unit)) { 1448 BCM_IF_ERROR_RETURN(bcmi_esw_switch_misc_wb_alloc(unit)); 1449 } 1450 #endif /* BCM_HURRICANE3_SUPPORT */ 1451 1452 return BCM_E_NONE; 1453 } 1454 1455 #ifdef BCM_TOMAHAWK_SUPPORT 1456 /* 1457 * Function: 1458 * _bcm_esw_switch_tpid_reinit 1459 * Purpose: 1460 * Recovers tpid information 1461 * Parameters: 1462 * unit - (IN) Unit number. 1463 * Returns: 1464 * BCM_E_XXX 1465 * Notes: 1466 */ 1467 STATIC int 1468 _bcm_esw_switch_tpid_reinit(int unit) 1469 { 1470 int i = 0; 1471 int tpid_index = 0; 1472 uint32 l2_tunnel_parse_control = 0; 1473 uint8 tpid_enable = 0; 1474 int rv = BCM_E_NONE; 1475 soc_field_t tpid_enable_field[] = { 1476 MIM_PAYLOAD_TPID_ENABLEf, 1477 VXLAN_PAYLOAD_TPID_ENABLEf, 1478 L2GRE_PAYLOAD_TPID_ENABLEf}; 1479 #ifdef BCM_TOMAHAWK3_SUPPORT 1480 if (SOC_IS_TOMAHAWK3(unit)) { 1481 return BCM_E_NONE; 1482 } 1483 #endif 1484 /* Recover TPID reference count from ING_L2_TUNNEL_PARSE_CONTROLr */ 1485 BCM_IF_ERROR_RETURN( 1486 READ_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 1487 &l2_tunnel_parse_control)); 1488 for (i = 0; i < 3; i++) { 1489 tpid_index = 0; 1490 if (!soc_reg_field_valid(unit, 1491 ING_L2_TUNNEL_PARSE_CONTROLr,tpid_enable_field[i])) { 1492 continue; 1493 } 1494 tpid_enable = soc_reg_field_get(unit, 1495 ING_L2_TUNNEL_PARSE_CONTROLr, 1496 l2_tunnel_parse_control, 1497 tpid_enable_field[i]); 1498 while (tpid_enable) { 1499 if (tpid_enable & 0x1) { 1500 BCM_IF_ERROR_RETURN( 1501 _bcm_fb2_outer_tpid_tab_ref_count_add(unit, tpid_index, 1)); 1502 } 1503 tpid_enable >>= 1; 1504 tpid_index++; 1505 } 1506 } 1507 1508 return rv; 1509 } 1510 #endif /* BCM_TOMAHAWK_SUPPORT */ 1511 1512 /* 1513 * Function: 1514 * _bcm_esw_switch_scache_sync 1515 * Purpose: 1516 * Syncs switch warmboot state to scache 1517 * Parameters: 1518 * unit - (IN) Unit number. 1519 * Returns: 1520 * BCM_E_XXX 1521 * Notes: 1522 */ 1523 int 1524 _bcm_esw_switch_scache_sync(int unit) 1525 { 1526 if (soc_feature(unit,soc_feature_flex_hashing)) { 1527 BCM_IF_ERROR_RETURN(_bcm_esw_switch_hash_scache_sync(unit)); 1528 } 1529 1530 if (soc_feature(unit,soc_feature_agm)) { 1531 BCM_IF_ERROR_RETURN(_bcm_esw_switch_agm_scache_sync(unit)); 1532 } 1533 1534 if (soc_feature(unit,soc_feature_th_tflow)) { 1535 BCM_IF_ERROR_RETURN(_bcm_esw_switch_tflow_scache_sync(unit)); 1536 } 1537 1538 #ifdef BCM_TRIDENT2_SUPPORT 1539 if (SOC_IS_TD2_TT2(unit)) { 1540 BCM_IF_ERROR_RETURN(bcmi_esw_switch_l2_scache_sync(unit)); 1541 } 1542 #endif /* BCM_TRIDENT2_SUPPORT */ 1543 1544 #ifdef BCM_HURRICANE3_SUPPORT 1545 if (SOC_IS_HURRICANE3(unit)) { 1546 BCM_IF_ERROR_RETURN(bcmi_esw_switch_misc_scache_sync(unit)); 1547 } 1548 #endif /* BCM_HURRICANE3_SUPPORT */ 1549 1550 return BCM_E_NONE; 1551 } 1552 1553 /* 1554 * Function: 1555 * _bcm_esw_switch_reinit 1556 * Purpose: 1557 * Recovers switch warmboot state from scache 1558 * Parameters: 1559 * unit - (IN) Unit number. 1560 * Returns: 1561 * BCM_E_XXX 1562 * Notes: 1563 */ 1564 STATIC int 1565 _bcm_esw_switch_reinit(int unit) 1566 { 1567 if (soc_feature(unit,soc_feature_flex_hashing)) { 1568 BCM_IF_ERROR_RETURN(_bcm_esw_switch_hash_reinit(unit)); 1569 } 1570 1571 if (soc_feature(unit,soc_feature_agm)) { 1572 BCM_IF_ERROR_RETURN(_bcm_esw_switch_agm_reinit(unit)); 1573 } 1574 1575 if (soc_feature(unit,soc_feature_th_tflow)) { 1576 BCM_IF_ERROR_RETURN(_bcm_esw_switch_tflow_reinit(unit)); 1577 } 1578 1579 #ifdef BCM_TOMAHAWK_SUPPORT 1580 if (soc_feature(unit, soc_feature_l2_tunnel_transit_payload_tpid_parser)) { 1581 BCM_IF_ERROR_RETURN(_bcm_esw_switch_tpid_reinit(unit)); 1582 } 1583 #endif /* BCM_TOMAHAWK_SUPPORT */ 1584 1585 #ifdef BCM_TRIDENT2_SUPPORT 1586 if (SOC_IS_TD2_TT2(unit)) { 1587 BCM_IF_ERROR_RETURN(bcmi_esw_switch_l2_reinit(unit)); 1588 } 1589 #endif /* BCM_TRIDENT2_SUPPORT */ 1590 1591 #ifdef BCM_HURRICANE3_SUPPORT 1592 if (SOC_IS_HURRICANE3(unit)) { 1593 BCM_IF_ERROR_RETURN(bcmi_esw_switch_misc_reinit(unit)); 1594 } 1595 #endif /* BCM_HURRICANE3_SUPPORT */ 1596 1597 return BCM_E_NONE; 1598 } 1599 /* 1600 * Function: 1601 * _bcm_esw_switch_olp_wb_scache_size_get 1602 * Purpose: 1603 * Returns required scache size for switch OLP module 1604 * Parameters: 1605 * unit - (IN) Unit number. 1606 * req_scache_size - (OUT) Request scache size 1607 * Returns: 1608 * BCM_E_XXX 1609 * Notes: 1610 */ 1611 STATIC int 1612 _bcm_esw_switch_olp_wb_scache_size_get(int unit, int *req_scache_size) 1613 { 1614 int alloc_size = 0; 1615 1616 #if defined(BCM_OLP_SUPPORT) 1617 if (soc_feature(unit, soc_feature_olp)) { 1618 alloc_size = sizeof(_bcm_switch_olp_bk_info[unit].api_ver); 1619 } 1620 #endif 1621 *req_scache_size = alloc_size; 1622 return BCM_E_NONE; 1623 } 1624 1625 /* 1626 * Function: 1627 * _bcm_esw_switch_olp_wb_alloc 1628 * Purpose: 1629 * Allocates required scache size for the switch olp module recovery 1630 * Parameters: 1631 * unit - (IN) Unit number. 1632 * Returns: 1633 * BCM_E_XXX 1634 * Notes: 1635 */ 1636 int 1637 _bcm_esw_switch_olp_wb_alloc(int unit) 1638 { 1639 int rv; 1640 uint8 *scache_ptr; 1641 soc_scache_handle_t scache_handle; 1642 int req_scache_size = 0; 1643 1644 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1645 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_OLP); 1646 1647 rv = _bcm_esw_switch_olp_wb_scache_size_get(unit, &req_scache_size); 1648 BCM_IF_ERROR_RETURN(rv); 1649 1650 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 1651 req_scache_size, &scache_ptr, BCM_SWITCH_WB_OLP_DEFAULT_VERSION, NULL); 1652 1653 if (BCM_E_NOT_FOUND == rv) { 1654 /* Proceed with Level 1 Warm Boot */ 1655 rv = BCM_E_NONE; 1656 } 1657 BCM_IF_ERROR_RETURN(rv); 1658 return BCM_E_NONE; 1659 } 1660 1661 #if defined(BCM_OLP_SUPPORT) 1662 /* 1663 * Function: 1664 * _bcm_esw_switch_olp_scache_sync 1665 * Purpose: 1666 * Syncs switch olp warmboot state to scache 1667 * Parameters: 1668 * unit - (IN) Unit number. 1669 * Returns: 1670 * BCM_E_XXX 1671 * Notes: 1672 */ 1673 STATIC int 1674 _bcm_esw_switch_olp_scache_sync(int unit) 1675 { 1676 uint8 *scache_ptr; 1677 soc_scache_handle_t scache_handle; 1678 1679 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1680 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_OLP); 1681 1682 BCM_IF_ERROR_RETURN 1683 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1684 0, &scache_ptr, 1685 BCM_SWITCH_WB_OLP_DEFAULT_VERSION, NULL)); 1686 *scache_ptr = _BCM_SWITCH_OLP_APIV(unit); 1687 1688 LOG_DEBUG(BSL_LS_BCM_COMMON, 1689 (BSL_META_U(unit, 1690 "saving api ver %d\n "), 1691 *scache_ptr )); 1692 return BCM_E_NONE; 1693 } 1694 #endif /* BCM_OLP_SUPPORT */ 1695 1696 /* 1697 * Function: 1698 * _bcm_esw_switch_olp_reinit 1699 * Purpose: 1700 * Recovers switch olp warmboot state from scache 1701 * Parameters: 1702 * unit - (IN) Unit number. 1703 * Returns: 1704 * BCM_E_XXX 1705 * Notes: 1706 */ 1707 STATIC int 1708 _bcm_esw_switch_olp_reinit(int unit) 1709 { 1710 int rv = BCM_E_INTERNAL; 1711 uint8 *scache_ptr; 1712 uint16 recovered_ver = 0; 1713 soc_scache_handle_t scache_handle; 1714 1715 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1716 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_OLP); 1717 1718 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1719 0, &scache_ptr, 1720 BCM_SWITCH_WB_OLP_DEFAULT_VERSION, &recovered_ver); 1721 1722 if (BCM_E_NOT_FOUND == rv) { 1723 return _bcm_esw_switch_olp_wb_alloc(unit); 1724 } else if (BCM_E_NONE == rv) { 1725 if (recovered_ver >= BCM_SWITCH_WB_OLP_VERSION_1_0) { 1726 _BCM_SWITCH_OLP_APIV_SET(unit, *scache_ptr); 1727 } 1728 } 1729 LOG_DEBUG(BSL_LS_BCM_COMMON, 1730 (BSL_META_U(unit, 1731 " recovered scahe ver %d got api ver %d\n "), 1732 recovered_ver, *scache_ptr )); 1733 return rv; 1734 } 1735 1736 /* 1737 * Function: 1738 * _bcm_esw_switch_olp_init 1739 * Purpose: 1740 * Initializes OLP module 1741 * Parameters: 1742 * unit - (IN) Unit number. 1743 * Returns: 1744 * BCM_E_XXX 1745 * Notes: 1746 */ 1747 int 1748 _bcm_esw_switch_olp_init(int unit) 1749 { 1750 if (SOC_WARM_BOOT(unit)) { 1751 return _bcm_esw_switch_olp_reinit(unit); 1752 } else { 1753 /* initialize to default In absense of warmboot */ 1754 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_OPEN_API); 1755 } 1756 BCM_IF_ERROR_RETURN(_bcm_esw_switch_olp_wb_alloc(unit)); 1757 1758 /* 1759 * In case of KT2,SB2 and TD2+ OLP can be programmed by either of 1760 * bcm_l2_station_xxx API or bcm_switch_olp_l2_addr_xxx. Force other 1761 * devices to use bcm_switch_olp_l2_addr_xxx. 1762 */ 1763 if(!SOC_IS_KATANA2(unit) && !SOC_IS_TRIDENT2PLUS(unit)) { 1764 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_TRUE_API); 1765 } 1766 return BCM_E_NONE; 1767 } 1768 1769 /* 1770 * Function: 1771 * _bcm_esw_switch_encap_wb_scache_size_get 1772 * Purpose: 1773 * Returns required scache size for switch encap module 1774 * Parameters: 1775 * unit - (IN) Unit number. 1776 * req_scache_size - (OUT) Request scache size 1777 * Returns: 1778 * BCM_E_XXX 1779 * Notes: 1780 */ 1781 STATIC int 1782 _bcm_esw_switch_encap_wb_scache_size_get(int unit, 1783 int *req_scache_size) 1784 { 1785 if (soc_feature(unit, soc_feature_miml) || 1786 soc_feature(unit, soc_feature_custom_header)) { 1787 #if defined(BCM_HURRICANE3_SUPPORT) 1788 BCM_IF_ERROR_RETURN( 1789 _bcm_hr3_switch_encap_wb_scache_size_get(unit, req_scache_size)); 1790 #endif 1791 } 1792 return BCM_E_NONE; 1793 } 1794 1795 /* 1796 * Function: 1797 * _bcm_esw_switch_encap_wb_alloc 1798 * Purpose: 1799 * Allocates required scache size for the switch encap module recovery 1800 * Parameters: 1801 * unit - (IN) Unit number. 1802 * Returns: 1803 * BCM_E_XXX 1804 * Notes: 1805 */ 1806 STATIC int 1807 _bcm_esw_switch_encap_wb_alloc(int unit) 1808 { 1809 int rv; 1810 uint8 *scache_ptr; 1811 soc_scache_handle_t scache_handle; 1812 int req_scache_size = 0; 1813 1814 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1815 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_ENCAP); 1816 1817 rv = _bcm_esw_switch_encap_wb_scache_size_get(unit, &req_scache_size); 1818 BCM_IF_ERROR_RETURN(rv); 1819 1820 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 1821 req_scache_size, &scache_ptr, BCM_SWITCH_WB_ENCAP_DEFAULT_VERSION, NULL); 1822 1823 if (BCM_E_NOT_FOUND == rv) { 1824 /* Proceed with Level 1 Warm Boot */ 1825 rv = BCM_E_NONE; 1826 } 1827 1828 BCM_IF_ERROR_RETURN(rv); 1829 1830 return BCM_E_NONE; 1831 } 1832 1833 /* 1834 * Function: 1835 * _bcm_esw_switch_encap_scache_sync 1836 * Purpose: 1837 * Syncs switch encap warmboot state to scache 1838 * Parameters: 1839 * unit - (IN) Unit number. 1840 * Returns: 1841 * BCM_E_XXX 1842 * Notes: 1843 */ 1844 int 1845 _bcm_esw_switch_encap_scache_sync(int unit) 1846 { 1847 uint8 *scache_ptr; 1848 soc_scache_handle_t scache_handle; 1849 1850 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1851 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_ENCAP); 1852 1853 BCM_IF_ERROR_RETURN 1854 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1855 0, &scache_ptr, 1856 BCM_SWITCH_WB_ENCAP_DEFAULT_VERSION, NULL)); 1857 if (soc_feature(unit, soc_feature_miml) || 1858 soc_feature(unit, soc_feature_custom_header)) { 1859 #if defined(BCM_HURRICANE3_SUPPORT) 1860 BCM_IF_ERROR_RETURN(_bcm_hr3_switch_encap_sync(unit, &scache_ptr)); 1861 #endif /* BCM_HURRICANE3_SUPPORT */ 1862 } 1863 1864 return BCM_E_NONE; 1865 } 1866 1867 #if defined (BCM_WARM_BOOT_SUPPORT) 1868 /* 1869 * Function: 1870 * _bcm_esw_switch_encap_reinit 1871 * Purpose: 1872 * Recovers switch encap warmboot state from scache 1873 * Parameters: 1874 * unit - (IN) Unit number. 1875 * Returns: 1876 * BCM_E_XXX 1877 * Notes: 1878 */ 1879 STATIC int 1880 _bcm_esw_switch_encap_reinit(int unit) 1881 { 1882 int rv = BCM_E_INTERNAL; 1883 uint8 *scache_ptr; 1884 uint16 recovered_ver = 0; 1885 soc_scache_handle_t scache_handle; 1886 1887 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 1888 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_ENCAP); 1889 1890 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 1891 0, &scache_ptr, 1892 BCM_SWITCH_WB_ENCAP_DEFAULT_VERSION, &recovered_ver); 1893 1894 if (rv == BCM_E_NOT_FOUND) { 1895 return _bcm_esw_switch_encap_wb_alloc(unit); 1896 } else if (rv == BCM_E_NONE) { 1897 if (recovered_ver >= BCM_SWITCH_WB_ENCAP_VERSION_1_0) { 1898 #if defined(BCM_HURRICANE3_SUPPORT) 1899 BCM_IF_ERROR_RETURN(_bcm_hr3_switch_encap_reinit(unit, &scache_ptr)); 1900 #endif /* BCM_HURRICANE3_SUPPORT */ 1901 } 1902 } 1903 1904 return rv; 1905 } 1906 #endif /* BCM_WARM_BOOT_SUPPORT */ 1907 1908 #ifdef BCM_TOMAHAWK_SUPPORT 1909 int 1910 bcm_esw_scache_ver_get( 1911 int unit, 1912 int module, 1913 OUT uint16* const version) 1914 { 1915 soc_scache_handle_t handle; 1916 uint8* scache_ptr; 1917 uint32 size; 1918 int rv; 1919 SOC_SCACHE_HANDLE_SET(handle, unit, module, 0); 1920 rv = soc_scache_ptr_get(unit, handle, &scache_ptr, &size); 1921 if (rv == SOC_E_NONE) { 1922 sal_memcpy(version, scache_ptr, sizeof(uint16)); 1923 } 1924 1925 if ((rv == SOC_E_NOT_FOUND) || (rv == SOC_E_NONE)) { 1926 rv = BCM_E_NONE; 1927 } 1928 return rv; 1929 } 1930 #endif 1931 1932 int 1933 _bcm_esw_scache_ptr_get(int unit, soc_scache_handle_t handle, int create, 1934 uint32 size, uint8 **scache_ptr, 1935 uint16 default_ver, uint16 *recovered_ver) 1936 { 1937 int stable_size, stable_used, alloc_size, rv; 1938 uint32 alloc_get; 1939 uint16 version = default_ver; 1940 1941 if (NULL == scache_ptr) { 1942 return BCM_E_PARAM; 1943 } 1944 1945 SOC_SCACHE_ALIGN_SIZE(size); 1946 1947 /* Individual BCM module implementations are version-aware. The 1948 * default_ver is the latest version that the module is aware of. 1949 * Each module should be able to understand versions <= default_ver. 1950 * The actual recovered_ver is returned to the calling module during 1951 * warm boot initialization. The individual module needs to parse its 1952 * scache based on the recovered_ver. 1953 */ 1954 alloc_size = size + SOC_WB_SCACHE_CONTROL_SIZE; 1955 1956 SOC_IF_ERROR_RETURN(soc_stable_size_get(unit, &stable_size)); 1957 SOC_IF_ERROR_RETURN(soc_stable_used_get(unit, &stable_used)); 1958 1959 rv = soc_scache_ptr_get(unit, handle, scache_ptr, &alloc_get); 1960 if ((SOC_E_NOT_FOUND == rv) && 1961 create && (alloc_size > (stable_size - stable_used))) { 1962 /* scache out of space - requested scache chunk 1963 * is greater than available scache space */ 1964 if (stable_size > 0) { 1965 LOG_ERROR(BSL_LS_BCM_COMMON, 1966 (BSL_META_U(unit, 1967 "Scache out of space." 1968 "max=%d bytes, used=%d bytes, alloc_size=%d bytes\n "), 1969 stable_size, stable_used, alloc_size )); 1970 return BCM_E_RESOURCE; 1971 } else { /* level 1 recovery */ 1972 LOG_VERBOSE(BSL_LS_BCM_COMMON, 1973 (BSL_META_U(unit, 1974 "Scache not found...Level 1 recovery\n"))); 1975 return BCM_E_NOT_FOUND; 1976 } 1977 } else { 1978 if (create) { 1979 if (SOC_E_NOT_FOUND == rv) { 1980 SOC_IF_ERROR_RETURN 1981 (soc_scache_alloc(unit, handle, alloc_size)); 1982 } else if (alloc_size != alloc_get) { 1983 LOG_VERBOSE(BSL_LS_BCM_COMMON, 1984 (BSL_META_U(unit, 1985 "Reallocating %d bytes of scache space\n"), 1986 (alloc_size - alloc_get))); 1987 BCM_IF_ERROR_RETURN 1988 (soc_scache_realloc(unit, handle, (alloc_size - alloc_get))); 1989 } 1990 rv = soc_scache_ptr_get(unit, handle, scache_ptr, &alloc_get); 1991 LOG_VERBOSE(BSL_LS_BCM_COMMON, 1992 (BSL_META_U(unit, 1993 "Allocated raw scache pointer=%p, %d bytes\n"), 1994 scache_ptr, alloc_size)); 1995 } 1996 if (SOC_FAILURE(rv)) { 1997 return rv; 1998 } else if ((0 != size) && (alloc_get != alloc_size) && 1999 !SOC_WARM_BOOT(unit) && (!create)) { 2000 /* Expected size doesn't match retrieved size. 2001 * This is expected during 'sync' operation 2002 * during SDK downgrade */ 2003 LOG_VERBOSE(BSL_LS_BCM_COMMON, 2004 (BSL_META_U(unit, 2005 "Reallocating %d bytes of scache space\n"), 2006 (alloc_size - alloc_get))); 2007 BCM_IF_ERROR_RETURN 2008 (soc_scache_realloc(unit, handle, (alloc_size - alloc_get))); 2009 rv = soc_scache_ptr_get(unit, handle, scache_ptr, &alloc_get); 2010 if (SOC_FAILURE(rv)) { 2011 return rv; 2012 } 2013 2014 } else if (NULL == *scache_ptr) { 2015 return BCM_E_MEMORY; 2016 } 2017 2018 if (!SOC_WARM_BOOT(unit)) { 2019 /* Newly allocated, set up version info */ 2020 sal_memcpy(*scache_ptr, &version, sizeof(uint16)); 2021 } 2022 2023 if (SOC_WARM_BOOT(unit)) { 2024 /* Warm Boot recovery, verify the correct version */ 2025 sal_memcpy(&version, *scache_ptr, sizeof(uint16)); 2026 LOG_VERBOSE(BSL_LS_BCM_COMMON, 2027 (BSL_META_U(unit, 2028 "Obtained scache pointer=%p, %d bytes, " 2029 "version=%d.%d\n"), 2030 scache_ptr, alloc_get, 2031 SOC_SCACHE_VERSION_MAJOR(version), 2032 SOC_SCACHE_VERSION_MINOR(version))); 2033 2034 if (version > default_ver) { 2035 LOG_ERROR(BSL_LS_BCM_COMMON, 2036 (BSL_META_U(unit, 2037 "Downgrade detected. " 2038 "Current version=%d.%d found %d.%d\n"), 2039 SOC_SCACHE_VERSION_MAJOR(default_ver), 2040 SOC_SCACHE_VERSION_MINOR(default_ver), 2041 SOC_SCACHE_VERSION_MAJOR(version), 2042 SOC_SCACHE_VERSION_MINOR(version))); 2043 /* Notify the application with an event */ 2044 /* The application will then need to reconcile the 2045 version differences using the documented behavioral 2046 differences on per module (handle) basis */ 2047 SOC_IF_ERROR_RETURN 2048 (soc_event_generate(unit, 2049 SOC_SWITCH_EVENT_WARM_BOOT_DOWNGRADE, 2050 handle, version, default_ver)); 2051 rv = BCM_E_NONE; 2052 2053 } else if (version < default_ver) { 2054 LOG_VERBOSE(BSL_LS_BCM_COMMON, 2055 (BSL_META_U(unit, 2056 "Upgrade scenario supported. " 2057 "Current version=%d.%d found %d.%d\n"), 2058 SOC_SCACHE_VERSION_MAJOR(default_ver), 2059 SOC_SCACHE_VERSION_MINOR(default_ver), 2060 SOC_SCACHE_VERSION_MAJOR(version), 2061 SOC_SCACHE_VERSION_MINOR(version))); 2062 rv = BCM_E_NONE; 2063 } 2064 if (recovered_ver) { 2065 /* Modules that support multiple versions will suppy a pointer 2066 * to the recovered_ver. Others will not care */ 2067 *recovered_ver = version; 2068 } 2069 } 2070 } 2071 2072 /* Advance over scache control info */ 2073 2074 *scache_ptr += SOC_WB_SCACHE_CONTROL_SIZE; 2075 return BCM_E_NONE; 2076 } 2077 2078 #ifdef BCM_XGS3_SWITCH_SUPPORT 2079 STATIC int 2080 _bcm_switch_control_sync(int unit, int arg) 2081 { 2082 int rv = BCM_E_NONE; 2083 int backup_size; 2084 uint8 *scache_module_ptr = NULL; 2085 2086 BCM_IF_ERROR_RETURN(soc_scache_module_max_alloc(unit, 2087 &scache_module_ptr, &backup_size)); 2088 #ifdef BCM_SHADOW_SUPPORT 2089 if (SOC_IS_SHADOW(unit)) { 2090 /* Only few modules are applicable for Shadow */ 2091 if (_BCM_SYNC_SUCCESS(rv)) { 2092 rv = _bcm_esw_vlan_sync(unit); 2093 } 2094 if (_BCM_SYNC_SUCCESS(rv)) { 2095 rv = _bcm_esw_port_sync(unit); 2096 } 2097 if (_BCM_SYNC_SUCCESS(rv)) { 2098 rv = _bcm_esw_link_sync(unit); 2099 } 2100 if (_BCM_SYNC_SUCCESS(rv)) { 2101 rv = _bcm_switch_control_scache_sync(unit); 2102 } 2103 } else 2104 #endif /* BCM_SHADOW_SUPPORT */ 2105 { 2106 /* Sync scache dictionary first */ 2107 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_DICTIONARY_HANDLE, (&scache_module_ptr), 2108 0, 0, backup_size,soc_scache_module_data_backup, rv); 2109 rv = soc_scache_dictionary_sync(unit); 2110 if (!_BCM_SYNC_SUCCESS(rv)) { 2111 LOG_CLI((BSL_META_U(unit, "scache dictionary sync failed\n"))); 2112 sal_free(scache_module_ptr); 2113 return rv; 2114 } 2115 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_DICTIONARY_HANDLE, (&scache_module_ptr), 2116 0, 0, soc_scache_module_dirty_set, rv); 2117 2118 /* Call each module to write Level 2 Warm Boot info */ 2119 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_VLAN, (&scache_module_ptr), 2120 0, 0, backup_size, soc_scache_module_data_backup, rv); 2121 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_VLAN, 2122 _bcm_esw_vlan_sync, (&scache_module_ptr), rv); 2123 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_VLAN, (&scache_module_ptr), 2124 0, 0, soc_scache_module_dirty_set, rv); 2125 2126 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_STG, (&scache_module_ptr), 2127 0, 0, backup_size, soc_scache_module_data_backup, rv); 2128 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_STG, 2129 _bcm_esw_stg_sync, (&scache_module_ptr), rv); 2130 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_STG, (&scache_module_ptr), 2131 0, 0, soc_scache_module_dirty_set, rv); 2132 2133 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_COSQ, (&scache_module_ptr), 2134 0, 0, backup_size, soc_scache_module_data_backup, rv); 2135 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_COSQ, 2136 _bcm_esw_cosq_sync, (&scache_module_ptr), rv); 2137 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_COSQ, (&scache_module_ptr), 2138 0, 0, soc_scache_module_dirty_set, rv); 2139 2140 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_MIRROR, (&scache_module_ptr), 2141 0, 0, backup_size, soc_scache_module_data_backup, rv); 2142 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_MIRROR, 2143 _bcm_esw_mirror_sync, (&scache_module_ptr), rv); 2144 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_MIRROR, (&scache_module_ptr), 2145 0, 0, soc_scache_module_dirty_set, rv); 2146 2147 #ifdef BCM_TRIUMPH_SUPPORT 2148 if (soc_feature(unit, soc_feature_virtual_switching) || 2149 soc_feature(unit, soc_feature_gport_service_counters) || 2150 soc_feature(unit, soc_feature_fast_init) || 2151 soc_feature(unit, soc_feature_int_common_init)){ 2152 #if defined(BCM_TRX_SUPPORT) 2153 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_COMMON, (&scache_module_ptr), 2154 0, 0, backup_size, soc_scache_module_data_backup, rv); 2155 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_COMMON, 2156 _bcm_common_scache_sync, (&scache_module_ptr), rv); 2157 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_COMMON, (&scache_module_ptr), 2158 0, 0, soc_scache_module_dirty_set, rv); 2159 #endif /* BCM_TRX_SUPPORT */ 2160 } 2161 #endif 2162 2163 #ifdef BCM_TRIUMPH2_SUPPORT 2164 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_UDF, (&scache_module_ptr), 2165 0, 0, backup_size, soc_scache_module_data_backup, rv); 2166 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_UDF, 2167 _bcm_esw_udf_scache_sync, (&scache_module_ptr), rv); 2168 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_UDF, (&scache_module_ptr), 2169 0, 0, soc_scache_module_dirty_set, rv); 2170 #endif /* BCM_TRIUMPH2_SUPPORT */ 2171 #ifdef BCM_TOMAHAWK_SUPPORT 2172 if (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 2173 if (SOC_MEM_IS_VALID(unit, IFP_RANGE_CHECKm)) { 2174 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_RANGE, (&scache_module_ptr), 2175 0, 0, backup_size, soc_scache_module_data_backup, rv); 2176 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_RANGE, 2177 _bcm_esw_range_scache_sync, (&scache_module_ptr), rv); 2178 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_RANGE, (&scache_module_ptr), 2179 0, 0, soc_scache_module_dirty_set, rv); 2180 } 2181 } 2182 #endif 2183 2184 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_SWITCH, (&scache_module_ptr), 2185 1, 5, backup_size,soc_scache_module_data_backup, rv); 2186 2187 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_SWITCH, 2188 _bcm_esw_switch_scache_sync, (&scache_module_ptr), rv); 2189 #if defined(BCM_OLP_SUPPORT) 2190 if (soc_feature(unit, soc_feature_olp)) { 2191 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_SWITCH, 2192 _bcm_esw_switch_olp_scache_sync, (&scache_module_ptr), rv); 2193 } 2194 #endif 2195 2196 #ifdef BCM_HURRICANE3_SUPPORT 2197 if (soc_feature(unit, soc_feature_miml) || 2198 soc_feature(unit, soc_feature_custom_header)) { 2199 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_SWITCH, 2200 _bcm_esw_switch_encap_scache_sync, (&scache_module_ptr), rv); 2201 } 2202 #endif /* BCM_HURRICANE3_SUPPORT */ 2203 2204 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_SWITCH, (&scache_module_ptr), 2205 1, 5, soc_scache_module_dirty_set, rv); 2206 2207 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FIELD, (&scache_module_ptr), 2208 0, 1, backup_size,soc_scache_module_data_backup, rv); 2209 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_FIELD, 2210 _bcm_esw_field_scache_sync, (&scache_module_ptr), rv); 2211 if (rv == BCM_E_UNAVAIL) { 2212 rv = BCM_E_NONE; 2213 } 2214 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_FIELD, (&scache_module_ptr), 2215 0, 1, soc_scache_module_dirty_set, rv); 2216 2217 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_RX, (&scache_module_ptr), 2218 0, 0, backup_size,soc_scache_module_data_backup, rv); 2219 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_RX, 2220 _bcm_esw_rx_sync, (&scache_module_ptr), rv); 2221 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_RX, (&scache_module_ptr), 2222 0, 0, soc_scache_module_dirty_set, rv); 2223 2224 #ifdef INCLUDE_L3 2225 #ifdef BCM_TRX_SUPPORT 2226 if (SOC_IS_TRX(unit) && !(SOC_IS_TITAN(unit) || SOC_IS_TITAN2X(unit))) { 2227 if (soc_feature(unit, soc_feature_virtual_switching)) { 2228 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_VIRTUAL, (&scache_module_ptr), 2229 0, 0, backup_size,soc_scache_module_data_backup, rv); 2230 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_COMMON, 2231 _bcm_esw_virtual_sync, (&scache_module_ptr), rv); 2232 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_VIRTUAL, (&scache_module_ptr), 2233 0, 0, soc_scache_module_dirty_set, rv); 2234 } 2235 } 2236 #endif /* BCM_TRX_SUPPORT */ 2237 /* 2238 * Check whether L3 feature is enabled before syncing L3 module. 2239 */ 2240 if ((soc_feature(unit, soc_feature_l3) && 2241 soc_property_get(unit, spn_L3_ENABLE, 1)) 2242 #ifdef BCM_HURRICANE3_SUPPORT 2243 /* 2244 * Buckhound doesn't support L3 feature but MiML reuses some L3 2245 * functions for resource management. 2246 */ 2247 || ((!soc_feature(unit, soc_feature_l3) && 2248 soc_feature(unit, soc_feature_miml_no_l3))) 2249 #endif 2250 ) { 2251 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_L3, (&scache_module_ptr), 2252 0, 0, backup_size,soc_scache_module_data_backup, rv); 2253 2254 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_L3, 2255 _bcm_esw_l3_sync, (&scache_module_ptr), rv); 2256 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_L3, (&scache_module_ptr), 2257 0, 0, soc_scache_module_dirty_set, rv); 2258 } 2259 2260 if (soc_feature(unit, soc_feature_ip_mcast)) { 2261 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_IPMC, (&scache_module_ptr), 2262 0, 0, backup_size,soc_scache_module_data_backup, rv); 2263 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_IPMC, 2264 _bcm_esw_ipmc_sync, (&scache_module_ptr), rv); 2265 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_IPMC, (&scache_module_ptr), 2266 0, 0, soc_scache_module_dirty_set, rv); 2267 } 2268 2269 if (soc_feature(unit, soc_feature_mpls)) { 2270 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_MPLS, (&scache_module_ptr), 2271 0, 0, backup_size,soc_scache_module_data_backup, rv); 2272 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_MPLS, 2273 _bcm_esw_mpls_sync, (&scache_module_ptr), rv); 2274 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_MPLS, (&scache_module_ptr), 2275 0, 0, soc_scache_module_dirty_set, rv); 2276 2277 } 2278 2279 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_MULTICAST, (&scache_module_ptr), 2280 0, 0, backup_size,soc_scache_module_data_backup, rv); 2281 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_MULTICAST, 2282 _bcm_esw_multicast_sync, (&scache_module_ptr), rv); 2283 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_MULTICAST, (&scache_module_ptr), 2284 0, 0, soc_scache_module_dirty_set, rv); 2285 2286 if (soc_feature(unit, soc_feature_td3_style_proxy)) { 2287 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_PROXY, (&scache_module_ptr), 2288 0, 0, backup_size,soc_scache_module_data_backup, rv); 2289 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_PROXY, 2290 bcmi_proxy_server_sync, (&scache_module_ptr), rv); 2291 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_PROXY, (&scache_module_ptr), 2292 0, 0, soc_scache_module_dirty_set, rv); 2293 } 2294 2295 #endif /* INCLUDE_L3 */ 2296 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_TRUNK, (&scache_module_ptr), 2297 0, 0, backup_size,soc_scache_module_data_backup, rv); 2298 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_TRUNK, 2299 _bcm_esw_trunk_sync, (&scache_module_ptr), rv); 2300 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_TRUNK, (&scache_module_ptr), 2301 0, 0, soc_scache_module_dirty_set, rv); 2302 2303 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_LINKSCAN, (&scache_module_ptr), 2304 0, 0, backup_size,soc_scache_module_data_backup, rv); 2305 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_LINKSCAN, 2306 _bcm_esw_link_sync,(&scache_module_ptr), rv); 2307 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_LINKSCAN, (&scache_module_ptr), 2308 0, 0, soc_scache_module_dirty_set, rv); 2309 2310 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_PORT, (&scache_module_ptr), 2311 BCM_PORT_WB_SCACHE_PART_MIN, 2312 BCM_PORT_WB_SCACHE_PART_MAX, 2313 backup_size,soc_scache_module_data_backup, rv); 2314 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_PORT, 2315 _bcm_esw_port_sync, (&scache_module_ptr), rv); 2316 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_PORT, (&scache_module_ptr), 2317 BCM_PORT_WB_SCACHE_PART_MIN, 2318 BCM_PORT_WB_SCACHE_PART_MAX, 2319 soc_scache_module_dirty_set, rv); 2320 2321 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_OAM, (&scache_module_ptr), 2322 0, 0, backup_size,soc_scache_module_data_backup, rv); 2323 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_OAM, 2324 _bcm_esw_oam_sync, (&scache_module_ptr), rv); 2325 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_OAM, (&scache_module_ptr), 2326 0, 0, soc_scache_module_dirty_set, rv); 2327 2328 #if defined(INCLUDE_BFD) 2329 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_BFD, (&scache_module_ptr), 2330 0, 0, backup_size,soc_scache_module_data_backup, rv); 2331 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_BFD, 2332 _bcm_esw_bfd_sync, (&scache_module_ptr), rv); 2333 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_BFD, (&scache_module_ptr), 2334 0, 0, soc_scache_module_dirty_set, rv); 2335 #endif 2336 2337 2338 2339 if (soc_feature(unit, soc_feature_time_support)) { 2340 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_TIME, (&scache_module_ptr), 2341 0, 0, backup_size,soc_scache_module_data_backup, rv); 2342 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_TIME, 2343 _bcm_time_scache_sync, (&scache_module_ptr), rv); 2344 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_TIME, (&scache_module_ptr), 2345 0, 0, soc_scache_module_dirty_set, rv); 2346 } 2347 2348 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_QOS, (&scache_module_ptr), 2349 0, 0, backup_size,soc_scache_module_data_backup, rv); 2350 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_QOS, 2351 _bcm_esw_qos_sync, (&scache_module_ptr), rv); 2352 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_QOS, (&scache_module_ptr), 2353 0, 0, soc_scache_module_dirty_set, rv); 2354 2355 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_STACK, (&scache_module_ptr), 2356 0, 0, backup_size,soc_scache_module_data_backup, rv); 2357 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_STK, 2358 _bcm_esw_stk_sync, (&scache_module_ptr), rv); 2359 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_STACK, (&scache_module_ptr), 2360 0, 0, soc_scache_module_dirty_set, rv); 2361 2362 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_SWITCH_CONTROL, (&scache_module_ptr), 2363 0, 0, backup_size,soc_scache_module_data_backup, rv); 2364 rv = _bcm_switch_control_scache_sync(unit); 2365 if (!_BCM_SYNC_SUCCESS(rv)) { 2366 LOG_CLI((BSL_META_U(unit, "Switch_control_sync failed\n"))); 2367 sal_free(scache_module_ptr); 2368 return rv; 2369 } 2370 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_SWITCH_CONTROL, (&scache_module_ptr), 2371 0, 0, soc_scache_module_dirty_set, rv); 2372 2373 #ifdef BCM_IPFIX_SUPPORT 2374 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_IPFIX, (&scache_module_ptr), 2375 0, 0, backup_size,soc_scache_module_data_backup, rv); 2376 rv = _bcm_esw_ipfix_sync(unit); 2377 if (!_BCM_SYNC_SUCCESS(rv)) { 2378 LOG_CLI((BSL_META_U(unit, "IPFIX sync failed\n"))); 2379 sal_free(scache_module_ptr); 2380 return rv; 2381 } 2382 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_IPFIX, (&scache_module_ptr), 2383 0, 0, soc_scache_module_dirty_set, rv); 2384 #endif /* BCM_IPFIX_SUPPORT */ 2385 #ifdef INCLUDE_L3 2386 #ifdef BCM_TRIDENT_SUPPORT 2387 if (SOC_IS_TRIDENT(unit) || SOC_IS_TRIDENT2X(unit) || 2388 SOC_IS_TOMAHAWKX(unit)) { 2389 if (soc_feature(unit, soc_feature_trill)) { 2390 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_TRILL, (&scache_module_ptr), 2391 0, 0, backup_size,soc_scache_module_data_backup, rv); 2392 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_TRILL, 2393 _bcm_esw_trill_sync, (&scache_module_ptr), rv); 2394 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_TRILL, (&scache_module_ptr), 2395 0, 0, soc_scache_module_dirty_set, rv); 2396 } 2397 } 2398 #endif /* BCM_TRIDENT_SUPPORT */ 2399 2400 #ifdef BCM_TRIDENT2_SUPPORT 2401 if (soc_feature(unit, soc_feature_vxlan)) { 2402 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_VXLAN, (&scache_module_ptr), 2403 0, 0, backup_size,soc_scache_module_data_backup, rv); 2404 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_VXLAN, 2405 _bcm_esw_vxlan_sync, (&scache_module_ptr), rv); 2406 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_VXLAN, (&scache_module_ptr), 2407 0, 0, soc_scache_module_dirty_set, rv); 2408 } 2409 #endif /* BCM_TRIDENT2_SUPPORT */ 2410 2411 #ifdef BCM_TRIDENT_SUPPORT 2412 if (soc_feature(unit, soc_feature_mim)) { 2413 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_MIM, (&scache_module_ptr), 2414 0, 0, backup_size,soc_scache_module_data_backup, rv); 2415 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_MIM, 2416 _bcm_esw_mim_sync, (&scache_module_ptr), rv); 2417 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_MIM, (&scache_module_ptr), 2418 0, 0, soc_scache_module_dirty_set, rv); 2419 } 2420 #endif 2421 2422 #ifdef BCM_TRIUMPH3_SUPPORT 2423 if (soc_feature(unit, soc_feature_l2gre)) { 2424 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_L2GRE, 2425 (&scache_module_ptr),0, 0, backup_size, 2426 soc_scache_module_data_backup, rv); 2427 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_L2GRE, 2428 _bcm_esw_l2gre_sync, (&scache_module_ptr), rv); 2429 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_L2GRE, (&scache_module_ptr), 2430 0, 0, soc_scache_module_dirty_set, rv); 2431 } 2432 #endif /* BCM_TRIUMPH3_SUPPORT */ 2433 2434 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_NIV, (&scache_module_ptr), 2435 0, 0, backup_size,soc_scache_module_data_backup, rv); 2436 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_NIV, 2437 _bcm_esw_niv_sync, (&scache_module_ptr), rv); 2438 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_NIV, (&scache_module_ptr), 2439 0, 0, soc_scache_module_dirty_set, rv); 2440 2441 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_SUBPORT, (&scache_module_ptr), 2442 0, 0, backup_size,soc_scache_module_data_backup, rv); 2443 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_SUBPORT, 2444 _bcm_esw_subport_sync, (&scache_module_ptr), rv); 2445 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_SUBPORT, (&scache_module_ptr), 2446 0, 0, soc_scache_module_dirty_set, rv); 2447 #ifdef BCM_TRIDENT3_SUPPORT 2448 if (soc_feature(unit, soc_feature_flex_flow)) { 2449 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FLOW, (&scache_module_ptr), 2450 0, 0, backup_size,soc_scache_module_data_backup, rv); 2451 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_FLOW, 2452 _bcm_esw_flow_sync, (&scache_module_ptr), rv); 2453 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_FLOW, (&scache_module_ptr), 2454 0, 0, soc_scache_module_dirty_set, rv); 2455 } 2456 #endif /* BCM_TRIDENT3_SUPPORT */ 2457 2458 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) 2459 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_EXTENDER, (&scache_module_ptr), 2460 0, 0, backup_size,soc_scache_module_data_backup, rv); 2461 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_EXTENDER, 2462 _bcm_esw_extender_sync, (&scache_module_ptr), rv); 2463 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_EXTENDER, (&scache_module_ptr), 2464 0, 0, soc_scache_module_dirty_set, rv); 2465 #endif 2466 #endif /* INCLUDE_L3 */ 2467 2468 #ifdef BCM_TRIDENT3_SUPPORT 2469 if (soc_feature(unit, soc_feature_hash_flex_bin)) { 2470 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FLOW, (&scache_module_ptr), 2471 0, 0, backup_size,soc_scache_module_data_backup, rv); 2472 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_HASH, 2473 _bcm_esw_hash_sync, (&scache_module_ptr), rv); 2474 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_HASH, (&scache_module_ptr), 2475 0, 0, soc_scache_module_dirty_set, rv); 2476 } 2477 #endif /* BCM_TRIDENT3_SUPPORT */ 2478 2479 #if defined(INCLUDE_REGEX) 2480 /* No WARMBOOT support for REGEX */ 2481 #endif /* INCLUDE_REGEX */ 2482 2483 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 2484 defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HURRICANE3_SUPPORT) || \ 2485 defined(BCM_GLOBAL_METER_V2_SUPPORT) 2486 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 2487 SOC_IS_TD2_TT2(unit) || 2488 soc_feature(unit, soc_feature_global_meter_v2)) { 2489 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_POLICER, (&scache_module_ptr), 2490 0, 0, backup_size,soc_scache_module_data_backup, rv); 2491 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_GLB_METER, 2492 _bcm_esw_global_meter_policer_sync, (&scache_module_ptr), rv); 2493 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_POLICER, (&scache_module_ptr), 2494 0, 0, soc_scache_module_dirty_set, rv); 2495 } 2496 2497 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 2498 SOC_IS_TD2_TT2(unit) || SOC_IS_HURRICANE3(unit)) { 2499 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_STAT, (&scache_module_ptr), 2500 0, 1, backup_size,soc_scache_module_data_backup, rv); 2501 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_STAT, 2502 _bcm_esw_stat_sync, (&scache_module_ptr), rv); 2503 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_STAT, (&scache_module_ptr), 2504 0, 1, soc_scache_module_dirty_set, rv); 2505 } 2506 2507 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 2508 if (soc_feature(unit, soc_feature_fcoe)) { 2509 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FCOE, (&scache_module_ptr), 2510 0, 0, backup_size,soc_scache_module_data_backup, rv); 2511 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_FCOE, 2512 _bcm_esw_fcoe_sync, (&scache_module_ptr), rv); 2513 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_FCOE, (&scache_module_ptr), 2514 0, 0, soc_scache_module_dirty_set, rv); 2515 2516 } 2517 } 2518 #endif /* BCM_KATANA_SUPPORT */ 2519 #if defined(INCLUDE_XFLOW_MACSEC) 2520 if (soc_feature(unit, soc_feature_xflow_macsec)) { 2521 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_XFLOW_MACSEC, (&scache_module_ptr), 2522 0, 0, backup_size, soc_scache_module_data_backup, rv); 2523 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_XFLOW_MACSEC, 2524 _bcm_common_xflow_macsec_sync, (&scache_module_ptr), rv); 2525 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_XFLOW_MACSEC, (&scache_module_ptr), 2526 0, 0, soc_scache_module_dirty_set, rv); 2527 } 2528 #endif 2529 #if defined(BCM_TSN_SUPPORT) 2530 if (soc_feature(unit, soc_feature_tsn)) { 2531 _BCM_SYNC_MODULE_BACKUP( 2532 unit, BCM_MODULE_TSN, (&scache_module_ptr), 2533 BCM_TSN_WB_SCACHE_PART_MIN, 2534 BCM_TSN_WB_SCACHE_PART_MAX, 2535 backup_size, soc_scache_module_data_backup, rv); 2536 _BCM_SYNC_MODULE( 2537 unit, SHR_BPROF_BCM_TSN, 2538 bcm_esw_tsn_sync, (&scache_module_ptr), rv); 2539 _BCM_SYNC_MODULE_DIRTY( 2540 unit, BCM_MODULE_TSN, (&scache_module_ptr), 2541 BCM_TSN_WB_SCACHE_PART_MIN, 2542 BCM_TSN_WB_SCACHE_PART_MAX, 2543 soc_scache_module_dirty_set, rv); 2544 } 2545 #endif /* BCM_TSN_SUPPORT */ 2546 } 2547 #if defined(BCM_KATANA2_SUPPORT) 2548 if (_BCM_SYNC_SUCCESS(rv)) { 2549 #if defined(BCM_METROLITE_SUPPORT) 2550 if (SOC_IS_METROLITE(unit)) { 2551 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, 2552 (&scache_module_ptr), 2553 1, 1, backup_size, 2554 soc_scache_module_data_backup, rv); 2555 rv = _soc_ml_flexio_scache_sync(unit); 2556 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, 2557 (&scache_module_ptr), 2558 1, 1, soc_scache_module_dirty_set,rv); 2559 } else 2560 #endif 2561 2562 #if defined(BCM_SABER2_SUPPORT) 2563 if (SOC_IS_SABER2(unit)) { 2564 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2565 1, 1, backup_size,soc_scache_module_data_backup, rv); 2566 rv = _soc_saber2_flexio_scache_sync(unit); 2567 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2568 1, 1, soc_scache_module_dirty_set, rv); 2569 } else 2570 #endif 2571 if (SOC_IS_KATANA2(unit)) { 2572 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2573 0, 0, backup_size,soc_scache_module_data_backup, rv); 2574 rv = _soc_katana2_flexio_scache_sync(unit); 2575 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2576 0, 0, soc_scache_module_dirty_set, rv); 2577 } 2578 } 2579 #endif 2580 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 2581 if (_BCM_SYNC_SUCCESS(rv)) { 2582 if (SOC_IS_TD2P_TT2P(unit)) { 2583 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2584 0, 0, backup_size,soc_scache_module_data_backup, rv); 2585 rv = soc_td2p_flexport_scache_sync(unit); 2586 if (!_BCM_SYNC_SUCCESS(rv)) { 2587 LOG_CLI((BSL_META_U(unit, "Flexport sync failed\n"))); 2588 sal_free(scache_module_ptr); 2589 return rv; 2590 } 2591 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2592 0, 0, soc_scache_module_dirty_set, rv); 2593 } 2594 } 2595 #endif 2596 #if defined(BCM_APACHE_SUPPORT) 2597 if (_BCM_SYNC_SUCCESS(rv)) { 2598 if (SOC_IS_APACHE(unit)) { 2599 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2600 0, 0, backup_size,soc_scache_module_data_backup, rv); 2601 #if defined(BCM_MONTEREY_SUPPORT) 2602 if (SOC_IS_MONTEREY(unit)) { 2603 rv = soc_monterey_flexport_scache_sync(unit); 2604 } else 2605 #endif 2606 { 2607 rv = soc_apache_flexport_scache_sync(unit); 2608 } 2609 if (!_BCM_SYNC_SUCCESS(rv)) { 2610 LOG_CLI((BSL_META_U(unit, "Flexport sync failed\n"))); 2611 sal_free(scache_module_ptr); 2612 return rv; 2613 } 2614 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2615 0, 0, soc_scache_module_dirty_set, rv); 2616 } 2617 } 2618 #endif /* BCM_APACHE_SUPPORT */ 2619 2620 #ifdef BCM_TOMAHAWK3_SUPPORT 2621 if (_BCM_SYNC_SUCCESS(rv)) { 2622 if (SOC_IS_TOMAHAWK3(unit)) { 2623 if (SOC_INFO(unit).flex_eligible) { 2624 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2625 0, 0, backup_size,soc_scache_module_data_backup, rv); 2626 rv = soc_th3_flexport_scache_sync(unit); 2627 if (!_BCM_SYNC_SUCCESS(rv)) { 2628 LOG_CLI((BSL_META_U(unit, "Flexport sync failed\n"))); 2629 sal_free(scache_module_ptr); 2630 return rv; 2631 } 2632 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2633 0, 0, soc_scache_module_dirty_set, rv); 2634 } 2635 } 2636 } 2637 #endif 2638 2639 #ifdef BCM_TOMAHAWK2_SUPPORT 2640 if (_BCM_SYNC_SUCCESS(rv)) { 2641 if (SOC_IS_TOMAHAWK2(unit)) { 2642 if (SOC_INFO(unit).flex_eligible) { 2643 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2644 0, 0, backup_size,soc_scache_module_data_backup, rv); 2645 rv = soc_th2_flexport_scache_sync(unit); 2646 if (!_BCM_SYNC_SUCCESS(rv)) { 2647 LOG_CLI((BSL_META_U(unit, "Flexport sync failed\n"))); 2648 sal_free(scache_module_ptr); 2649 return rv; 2650 } 2651 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2652 0, 0, soc_scache_module_dirty_set, rv); 2653 } 2654 } 2655 } 2656 2657 if (_BCM_SYNC_SUCCESS(rv)) { 2658 if (SOC_IS_TOMAHAWK2(unit)) { 2659 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2660 0, 0, backup_size,soc_scache_module_data_backup, rv); 2661 rv = soc_th2_tdm_scache_sync(unit); 2662 if (!_BCM_SYNC_SUCCESS(rv)) { 2663 LOG_CLI((BSL_META_U(unit, "TDM sync failed\n"))); 2664 sal_free(scache_module_ptr); 2665 return rv; 2666 } 2667 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2668 0, 0, soc_scache_module_dirty_set, rv); 2669 } 2670 } 2671 #endif /* BCM_TOMAHAWK2_SUPPORT */ 2672 2673 #ifdef BCM_TRIDENT3_SUPPORT 2674 if (_BCM_SYNC_SUCCESS(rv)) { 2675 if (SOC_IS_TRIDENT3(unit)) { 2676 if (SOC_INFO(unit).flex_eligible) { 2677 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2678 0, 0, backup_size,soc_scache_module_data_backup, rv); 2679 rv = soc_td3_flexport_scache_sync(unit); 2680 if (!_BCM_SYNC_SUCCESS(rv)) { 2681 LOG_CLI((BSL_META_U(unit, "Flexport sync failed\n"))); 2682 sal_free(scache_module_ptr); 2683 return rv; 2684 } 2685 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2686 0, 0, soc_scache_module_dirty_set, rv); 2687 } 2688 } 2689 2690 #ifdef BCM_MAVERICK2_SUPPORT 2691 if (SOC_IS_MAVERICK2(unit)) { 2692 if (SOC_INFO(unit).flex_eligible) { 2693 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2694 0, 0, backup_size,soc_scache_module_data_backup, rv); 2695 rv = soc_mv2_flexport_scache_sync(unit); 2696 if (!_BCM_SYNC_SUCCESS(rv)) { 2697 LOG_CLI((BSL_META_U(unit, "Flexport sync failed\n"))); 2698 sal_free(scache_module_ptr); 2699 return rv; 2700 } 2701 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2702 0, 0, soc_scache_module_dirty_set, rv); 2703 } 2704 } 2705 #endif /* BCM_MAVERICK2_SUPPORT */ 2706 2707 #ifdef BCM_HELIX5_SUPPORT 2708 if (SOC_IS_HELIX5(unit)) { 2709 if (SOC_INFO(unit).flex_eligible) { 2710 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2711 0, 0, backup_size,soc_scache_module_data_backup, rv); 2712 rv = soc_hx5_flexport_scache_sync(unit); 2713 if (!_BCM_SYNC_SUCCESS(rv)) { 2714 LOG_CLI((BSL_META_U(unit, "Flexport sync failed\n"))); 2715 sal_free(scache_module_ptr); 2716 return rv; 2717 } 2718 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 2719 0, 0, soc_scache_module_dirty_set, rv); 2720 } 2721 } 2722 #endif /* BCM_HELIX5_SUPPORT */ 2723 } 2724 2725 if (_BCM_SYNC_SUCCESS(rv)) { 2726 #ifdef BCM_HELIX5_SUPPORT 2727 if (SOC_IS_HELIX5(unit)) { 2728 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2729 0, 0, backup_size,soc_scache_module_data_backup, rv); 2730 rv = soc_hx5_tdm_scache_sync(unit); 2731 if (!_BCM_SYNC_SUCCESS(rv)) { 2732 LOG_CLI((BSL_META_U(unit, "TDM sync failed\n"))); 2733 sal_free(scache_module_ptr); 2734 return rv; 2735 } 2736 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2737 0, 0, soc_scache_module_dirty_set, rv); 2738 } 2739 #endif /* BCM_HELIX5_SUPPORT */ 2740 2741 #ifdef BCM_MAVERICK2_SUPPORT 2742 if (SOC_IS_MAVERICK2(unit)) { 2743 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2744 0, 0, backup_size,soc_scache_module_data_backup, rv); 2745 rv = soc_mv2_tdm_scache_sync(unit); 2746 if (!_BCM_SYNC_SUCCESS(rv)) { 2747 LOG_CLI((BSL_META_U(unit, "TDM sync failed\n"))); 2748 sal_free(scache_module_ptr); 2749 return rv; 2750 } 2751 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2752 0, 0, soc_scache_module_dirty_set, rv); 2753 } 2754 #endif /* BCM_MAVERICK2_SUPPORT */ 2755 2756 if (SOC_IS_TRIDENT3(unit)) { 2757 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2758 0, 0, backup_size,soc_scache_module_data_backup, rv); 2759 rv = soc_td3_tdm_scache_sync(unit); 2760 if (!_BCM_SYNC_SUCCESS(rv)) { 2761 LOG_CLI((BSL_META_U(unit, "TDM sync failed\n"))); 2762 sal_free(scache_module_ptr); 2763 return rv; 2764 } 2765 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_TDM_HANDLE, (&scache_module_ptr), 2766 0, 0, soc_scache_module_dirty_set, rv); 2767 } 2768 } 2769 #endif /* BCM_TRIDENT3_SUPPORT */ 2770 2771 if (_BCM_SYNC_SUCCESS(rv)) { 2772 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_MEMCACHE_HANDLE, (&scache_module_ptr), 2773 0, 0, backup_size,soc_scache_module_data_backup, rv); 2774 rv = _bcm_mem_scache_sync(unit); 2775 if (rv == BCM_E_UNAVAIL) { 2776 rv = BCM_E_NONE; 2777 } 2778 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_MEMCACHE_HANDLE, (&scache_module_ptr), 2779 0, 0, soc_scache_module_dirty_set, rv); 2780 } 2781 2782 if (_BCM_SYNC_SUCCESS(rv) && 2783 soc_feature(unit, soc_feature_l3_shared_defip_table) && 2784 (SOC_IS_TD2_TT2(unit) || SOC_IS_TRIUMPH3(unit))) { 2785 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_SOC_DEFIP_HANDLE, (&scache_module_ptr), 2786 0, 0, backup_size,soc_scache_module_data_backup, rv); 2787 rv = soc_control_defip_scache_sync(unit); 2788 if (rv == BCM_E_UNAVAIL) { 2789 rv = BCM_E_NONE; 2790 } 2791 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_SOC_DEFIP_HANDLE, (&scache_module_ptr), 2792 0, 0, soc_scache_module_dirty_set, rv); 2793 } 2794 2795 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 2796 if (_BCM_SYNC_SUCCESS(rv) && 2797 (SOC_IS_TRIDENT2X(unit) || SOC_IS_TITAN2X(unit) || 2798 SOC_IS_TRIDENT(unit) || SOC_IS_TITAN(unit))) { 2799 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_SOC_OVERLAY_TCAM_HANDLE, (&scache_module_ptr), 2800 0, 0, backup_size,soc_scache_module_data_backup, rv); 2801 rv = soc_control_overlay_tcam_scache_sync(unit); 2802 if (rv == BCM_E_UNAVAIL) { 2803 rv = BCM_E_NONE; 2804 } 2805 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_SOC_OVERLAY_TCAM_HANDLE, (&scache_module_ptr), 2806 0, 0, soc_scache_module_dirty_set, rv); 2807 } 2808 #endif 2809 2810 #if defined(BCM_SABER2_SUPPORT) 2811 if (SOC_IS_SABER2(unit) && soc_feature(unit, soc_feature_sat) && soc_property_get(unit, spn_SAT_ENABLE, 0)) { 2812 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_SAT, (&scache_module_ptr), 2813 0, 0, backup_size,soc_scache_module_data_backup, rv); 2814 rv = bcm_common_sat_wb_sync(unit, 0); 2815 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_SAT, (&scache_module_ptr), 2816 0, 0, soc_scache_module_dirty_set, rv); 2817 } 2818 #endif 2819 2820 #if defined(BCM_SABER2_SUPPORT) || defined(BCM_APACHE_SUPPORT) || \ 2821 defined(BCM_TRIUMPH3_SUPPORT) 2822 if (SOC_IS_SABER2(unit) || SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWK2(unit) || 2823 SOC_IS_TRIDENT3X(unit) || (soc_feature(unit, soc_feature_hierarchical_protection))) { 2824 2825 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FAILOVER, (&scache_module_ptr), 2826 0, 0, backup_size,soc_scache_module_data_backup, rv); 2827 rv = bcm_esw_failover_sync(unit); 2828 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_FAILOVER, (&scache_module_ptr), 2829 0, 0, soc_scache_module_dirty_set, rv); 2830 } 2831 #endif 2832 2833 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_L2, (&scache_module_ptr), 2834 0, 0, backup_size, soc_scache_module_data_backup, rv); 2835 rv = _bcm_esw_l2_wb_sync(unit); 2836 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_L2, (&scache_module_ptr), 2837 0, 0, soc_scache_module_dirty_set, rv); 2838 2839 #ifdef PORTMOD_SUPPORT 2840 if (_BCM_SYNC_SUCCESS(rv) && 2841 (soc_property_get(unit, spn_PHY_SIMUL, 0) || SAL_BOOT_PLISIM)) { 2842 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_PHYSIM_HANDLE, (&scache_module_ptr), 2843 0, 0, backup_size,soc_scache_module_data_backup, rv); 2844 rv = soc_physim_scache_sync(unit); 2845 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_PHYSIM_HANDLE, (&scache_module_ptr), 2846 0, 0, soc_scache_module_dirty_set, rv); 2847 } 2848 #endif 2849 2850 #if defined(CANCUN_SUPPORT) 2851 if (soc_feature(unit, soc_feature_cancun)) { 2852 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_CANCUN_HANDLE, (&scache_module_ptr), 2853 0, 0, backup_size,soc_scache_module_data_backup, rv); 2854 rv = soc_cancun_scache_sync(unit); 2855 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_CANCUN_HANDLE, (&scache_module_ptr), 2856 0, 0, soc_scache_module_dirty_set, rv); 2857 } 2858 #endif 2859 2860 #if defined(BCM_FLOWTRACKER_SUPPORT) 2861 if (soc_feature(unit, soc_feature_flex_flowtracker_ver_1)) { 2862 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FLOWTRACKER, (&scache_module_ptr), 2863 0, 0, backup_size, soc_scache_module_data_backup, rv); 2864 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_FT, 2865 bcm_esw_flowtracker_sync, (&scache_module_ptr), rv); 2866 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_FLOWTRACKER, (&scache_module_ptr), 2867 0, 0, soc_scache_module_dirty_set, rv); 2868 } else 2869 #endif /* BCM_FLOWTRACKER_SUPPORT */ 2870 { 2871 /* Flowtracker warmboot sync */ 2872 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FLOWTRACKER, (&scache_module_ptr), 2873 0, 0, backup_size, soc_scache_module_data_backup, 2874 rv); 2875 rv = _bcm_esw_flowtracker_sync(unit); 2876 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_FLOWTRACKER, (&scache_module_ptr), 2877 0, 0, soc_scache_module_dirty_set, rv); 2878 } 2879 2880 #if defined(BCM_COLLECTOR_SUPPORT) 2881 /* Collector warmboot sync */ 2882 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_COLLECTOR, (&scache_module_ptr), 2883 0, 0, backup_size, soc_scache_module_data_backup, 2884 rv); 2885 rv = _bcm_esw_collector_sync(unit); 2886 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_COLLECTOR, (&scache_module_ptr), 2887 0, 0, soc_scache_module_dirty_set, rv); 2888 #endif 2889 2890 #if defined(INCLUDE_TELEMETRY) 2891 /* Telemetry warmboot sync */ 2892 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_TELEMETRY, (&scache_module_ptr), 2893 0, 0, backup_size, soc_scache_module_data_backup, 2894 rv); 2895 rv = _bcm_esw_telemetry_sync(unit); 2896 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_TELEMETRY, (&scache_module_ptr), 2897 0, 0, soc_scache_module_dirty_set, rv); 2898 #endif 2899 2900 #ifdef BCM_TOMAHAWK3_SUPPORT 2901 if (SOC_IS_TOMAHAWK3(unit)) { 2902 if (soc_feature(unit, soc_feature_latency_monitor)) { 2903 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_LATENCY_MONITOR, (&scache_module_ptr), 2904 0, 0, backup_size, soc_scache_module_data_backup, rv); 2905 _bcm_th3_latency_monitor_sync(unit); 2906 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_LATENCY_MONITOR, (&scache_module_ptr), 2907 0, 0, soc_scache_module_dirty_set, rv); 2908 } 2909 } 2910 #endif 2911 2912 #if defined(INCLUDE_IFA) 2913 /* IFA warmboot sync */ 2914 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_IFA, (&scache_module_ptr), 2915 0, 0, backup_size, soc_scache_module_data_backup, 2916 rv); 2917 rv = _bcm_esw_ifa_sync(unit); 2918 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_IFA, (&scache_module_ptr), 2919 0, 0, soc_scache_module_dirty_set, rv); 2920 #endif 2921 2922 #if defined(BCM_TOMAHAWK3_SUPPORT) && defined(INCLUDE_SUM) 2923 if (SOC_IS_TOMAHAWK3(unit)) { 2924 /* SUM warmboot sync */ 2925 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_SUM, (&scache_module_ptr), 2926 0, 0, backup_size, soc_scache_module_data_backup, 2927 rv); 2928 rv = _bcm_th3_sum_sync(unit); 2929 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_SUM, (&scache_module_ptr), 2930 0, 0, soc_scache_module_dirty_set, rv); 2931 } 2932 #endif 2933 2934 sal_free(scache_module_ptr); 2935 /* Now send all data to the persistent storage */ 2936 if (_BCM_SYNC_SUCCESS(rv)) { 2937 rv = soc_scache_commit(unit); 2938 } 2939 2940 /* Mark scache as clean */ 2941 SOC_CONTROL_LOCK(unit); 2942 SOC_CONTROL(unit)->scache_dirty = 0; 2943 SOC_CONTROL_UNLOCK(unit); 2944 2945 return rv; 2946 } 2947 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 2948 2949 /* 2950 * Function: 2951 * _bcm_switch_downgrade 2952 * Purpose: 2953 * Set the switch for doing a warmboot downgrade 2954 * Parameters: 2955 * unit - (IN) Unit number. 2956 * arg - (IN) Version to downgrade. 2957 * Returns: 2958 * BCM_E_XXX 2959 * Notes: 2960 */ 2961 2962 STATIC int 2963 _bcm_switch_downgrade(int unit, int arg) 2964 { 2965 int rv = BCM_E_NONE; 2966 2967 rv = _bcm_field_wb_downgrade_config_set(unit,arg); 2968 2969 #if defined(INCLUDE_BFD) 2970 if( rv == BCM_E_NONE) { 2971 rv = _bcm_esw_bfd_wb_downgrade_config_set(unit,arg); 2972 /* 2973 * BFD could return UNAVAIL when BFD feature is compiled 2974 * but BFD not initialized due to firmware 2975 * NOT being present. So ignoring the UNAVAIL error 2976 */ 2977 if (rv == BCM_E_UNAVAIL) { 2978 rv = BCM_E_NONE; 2979 } 2980 } 2981 #endif 2982 2983 /* reset the dirty flag of all the scache handles 2984 * so that we flush all the modules scache to persistent media 2985 * irrespective of whether module data is modified or not 2986 */ 2987 BCM_IF_ERROR_RETURN(soc_scache_handle_state_dirty_flag_set(unit)); 2988 return rv; 2989 } 2990 2991 #endif /* BCM_WARM_BOOT_SUPPORT */ 2992 2993 STATIC int 2994 bcmi_esw_bfd_rx_disable(int unit, int disable) 2995 { 2996 int result = BCM_E_NONE; 2997 uint32 val = 0; 2998 uint64 val64; 2999 3000 COMPILER_64_ZERO(val64); 3001 if (!disable) { 3002 /* 3003 * Coverity 3004 * 3005 * Coverity complains that expression is always true 3006 * irrespective of its value for ROBO version of 3007 * SOC_REG_IS_VALID 3008 */ 3009 3010 /* coverity[constant expression result */ 3011 if(SOC_REG_IS_VALID(unit, BFD_RX_UDP_CONTROLr)) { 3012 BCM_IF_ERROR_RETURN(READ_BFD_RX_UDP_CONTROLr(unit,&val)); 3013 soc_reg_field_set(unit, BFD_RX_UDP_CONTROLr, &val, 3014 BFD_UDP_PORT1_HOPf, 3784); 3015 soc_reg_field_set(unit, BFD_RX_UDP_CONTROLr, &val, 3016 BFD_UDP_PORTM_HOPf, 4784); 3017 BCM_IF_ERROR_RETURN(WRITE_BFD_RX_UDP_CONTROLr(unit, val)); 3018 /* coverity[constant expression result */ 3019 } else if(SOC_REG_IS_VALID(unit, BFD_RX_UDP_CONTROL_64r)) { 3020 BCM_IF_ERROR_RETURN(READ_BFD_RX_UDP_CONTROL_64r(unit,&val64)); 3021 soc_reg64_field32_set(unit, BFD_RX_UDP_CONTROL_64r, &val64, 3022 BFD_UDP_PORT1_HOPf, 3784); 3023 soc_reg64_field32_set(unit, BFD_RX_UDP_CONTROL_64r, &val64, 3024 BFD_UDP_PORTM_HOPf, 4784); 3025 soc_reg64_field32_set(unit, BFD_RX_UDP_CONTROL_64r, &val64, 3026 BFD_UDP_PORT_LAGf, 6784); 3027 BCM_IF_ERROR_RETURN(WRITE_BFD_RX_UDP_CONTROL_64r(unit, val64)); 3028 } else { 3029 LOG_CLI((BSL_META_U(unit, 3030 "Not implemented.\n"))); 3031 result = BCM_E_UNAVAIL; 3032 } 3033 } else { 3034 /* coverity[constant expression result */ 3035 if(SOC_REG_IS_VALID(unit, BFD_RX_UDP_CONTROLr)) { 3036 BCM_IF_ERROR_RETURN(READ_BFD_RX_UDP_CONTROLr(unit,&val)); 3037 soc_reg_field_set(unit, BFD_RX_UDP_CONTROLr, &val, 3038 BFD_UDP_PORTM_HOPf, 0); 3039 soc_reg_field_set(unit, BFD_RX_UDP_CONTROLr, &val, 3040 BFD_UDP_PORT1_HOPf, 0); 3041 BCM_IF_ERROR_RETURN(WRITE_BFD_RX_UDP_CONTROLr(unit, val)); 3042 /* coverity[constant expression result */ 3043 } else if (SOC_REG_IS_VALID(unit, BFD_RX_UDP_CONTROL_64r)) { 3044 BCM_IF_ERROR_RETURN(READ_BFD_RX_UDP_CONTROL_64r(unit,&val64)); 3045 soc_reg64_field32_set(unit, BFD_RX_UDP_CONTROL_64r, &val64, 3046 BFD_UDP_PORT1_HOPf, 0); 3047 soc_reg64_field32_set(unit, BFD_RX_UDP_CONTROL_64r, &val64, 3048 BFD_UDP_PORTM_HOPf, 0); 3049 soc_reg64_field32_set(unit, BFD_RX_UDP_CONTROL_64r, &val64, 3050 BFD_UDP_PORT_LAGf, 0); 3051 BCM_IF_ERROR_RETURN(WRITE_BFD_RX_UDP_CONTROL_64r(unit, val64)); 3052 } else { 3053 LOG_CLI((BSL_META_U(unit, 3054 "Not implemented.\n"))); 3055 result = BCM_E_UNAVAIL; 3056 } 3057 } 3058 return result; 3059 } 3060 #ifdef BCM_XGS3_SWITCH_SUPPORT 3061 3062 /* 3063 * Function: 3064 * _bcm_vrf_max_get 3065 * Description: 3066 * Get the current maximum vrf value. 3067 * Parameters: 3068 * unit - (IN) BCM device number. 3069 * arg - (OUT)Pointer to where the retrieved value will be written. 3070 * Returns: 3071 * BCM_E_xxxx 3072 */ 3073 STATIC int 3074 _bcm_vrf_max_get(int unit, int *arg) 3075 { 3076 *arg = SOC_VRF_MAX(unit); 3077 return (BCM_E_NONE); 3078 } 3079 3080 3081 /* Helper routines for argument translation */ 3082 3083 STATIC int 3084 _bool_invert(int unit, int arg, int set) 3085 { 3086 /* Same for both set/get */ 3087 return !arg; 3088 } 3089 3090 /* Helper routines for "chip-wide" packet aging set/get */ 3091 3092 STATIC int 3093 _bcm_fb_pkt_age_set(int unit, int arg) 3094 { 3095 int aging_ticks = arg; 3096 uint32 pat_val = 0; 3097 3098 if (!arg) { 3099 /* Disable packet aging on all COSQs */ 3100 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 0)); 3101 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, 0)); /* Aesthetic */ 3102 } else if ((arg < 0) || (arg > 7162)) { 3103 return BCM_E_PARAM; 3104 } else { 3105 /* Use 125 us clock pulses */ 3106 soc_reg_field_set(unit, PKTAGINGTIMERr, &pat_val, AGINGTICKSELf, 0); 3107 3108 /* Convert ms request to 125 us pulses */ 3109 aging_ticks *= 8; 3110 3111 /* We want this many pulses to happen before aging, 3112 * but the HW setting is pulses per cycle. 3113 * We need to divide the by the number of cycles before aging.*/ 3114 aging_ticks = 3115 (aging_ticks + NUM_MMU_AGE_CYCLES - 1) / NUM_MMU_AGE_CYCLES; 3116 soc_reg_field_set(unit, PKTAGINGTIMERr, &pat_val, 3117 DURATIONSELECTf, aging_ticks); 3118 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, pat_val)); 3119 3120 /* Set all COSQs to the same value 3121 * - They use the maximum of NUM_MMU_AGE_CYCLES to expire */ 3122 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, 0)); 3123 } 3124 3125 return BCM_E_NONE; 3126 } 3127 3128 #ifdef BCM_TRX_SUPPORT 3129 STATIC int 3130 _bcm_ts_pkt_age_set(int unit, int arg) 3131 { 3132 int aging_ticks = arg; 3133 uint32 pat_val = 0; 3134 3135 if (!arg) { 3136 /* Disable packet aging on all COSQs */ 3137 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 0)); 3138 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT0r(unit, 0)); /* Aesthetic */ 3139 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT1r(unit, 0)); /* Aesthetic */ 3140 } else if ((arg < 0) || (arg > 7162)) { 3141 return BCM_E_PARAM; 3142 } else { 3143 /* Use 125 us clock pulses */ 3144 soc_reg_field_set(unit, PKTAGINGTIMERr, &pat_val, AGINGTICKSELf, 0); 3145 3146 /* Convert ms request to 125 us pulses */ 3147 aging_ticks *= 8; 3148 3149 /* We want this many pulses to happen before aging, 3150 * but the HW setting is pulses per cycle. 3151 * We need to divide the by the number of cycles before aging.*/ 3152 aging_ticks = 3153 (aging_ticks + NUM_MMU_AGE_CYCLES - 1) / NUM_MMU_AGE_CYCLES; 3154 soc_reg_field_set(unit, PKTAGINGTIMERr, &pat_val, 3155 DURATIONSELECTf, aging_ticks); 3156 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, pat_val)); 3157 3158 /* Set all COSQs to the same value 3159 * - They use the maximum of NUM_MMU_AGE_CYCLES to expire */ 3160 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT0r(unit, 0)); 3161 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT1r(unit, 0)); 3162 } 3163 3164 return BCM_E_NONE; 3165 } 3166 #endif 3167 3168 #ifdef BCM_KATANA_SUPPORT 3169 STATIC int 3170 _bcm_kt_pkt_age_set(int unit, int arg) 3171 { 3172 int aging_ticks = arg; 3173 uint32 pat_val = 0; 3174 3175 if (!arg) { 3176 /* Disable packet aging on all COSQs */ 3177 SOC_IF_ERROR_RETURN(WRITE_PKTINTAGINGTIMERr(unit, 0)); 3178 SOC_IF_ERROR_RETURN(WRITE_PKTINTAGINGLIMIT0r(unit, 0)); /* Aesthetic */ 3179 SOC_IF_ERROR_RETURN(WRITE_PKTINTAGINGLIMIT1r(unit, 0)); /* Aesthetic */ 3180 /* Register valid only when external memory is present */ 3181 if (soc_feature(unit, soc_feature_ddr3)) { 3182 SOC_IF_ERROR_RETURN(WRITE_PKTEXTAGINGTIMERr(unit, 0)); 3183 SOC_IF_ERROR_RETURN(WRITE_PKTEXTAGINGLIMIT0r(unit, 0)); /* Aesthetic */ 3184 SOC_IF_ERROR_RETURN(WRITE_PKTEXTAGINGLIMIT1r(unit, 0)); /* Aesthetic */ 3185 } 3186 3187 } else if ((arg < 0) || (arg > 7162)) { 3188 return BCM_E_PARAM; 3189 } else { 3190 /* Convert ms request to 125 us pulses */ 3191 aging_ticks *= 8; 3192 3193 /* 125 us pulses need to elapse before aging, 3194 * but the HW programming is pulses per cycle. 3195 * So we need to divide the aging_ticks value by 3196 * number of MMU age cycles. */ 3197 aging_ticks = 3198 (aging_ticks + NUM_MMU_AGE_CYCLES - 1) / NUM_MMU_AGE_CYCLES; 3199 3200 /* Use 125 us clock pulses for PKTINTAGINGTIMER*/ 3201 soc_reg_field_set(unit, PKTINTAGINGTIMERr, &pat_val, AGINGTICKSELf, 0); 3202 soc_reg_field_set(unit, PKTINTAGINGTIMERr, &pat_val, 3203 DURATIONSELECTf, aging_ticks); 3204 SOC_IF_ERROR_RETURN(WRITE_PKTINTAGINGTIMERr(unit, pat_val)); 3205 3206 /* Set all COSQs to the same value 3207 * - They use the maximum of NUM_MMU_AGE_CYCLES to expire */ 3208 SOC_IF_ERROR_RETURN(WRITE_PKTINTAGINGLIMIT0r(unit, 0)); 3209 SOC_IF_ERROR_RETURN(WRITE_PKTINTAGINGLIMIT1r(unit, 0)); 3210 3211 /* Use 125 us clock pulses for PKTEXTAGINGTIMER*/ 3212 /* Register valid only when external memeory is present */ 3213 if (soc_feature(unit, soc_feature_ddr3)) { 3214 soc_reg_field_set(unit, PKTEXTAGINGTIMERr, &pat_val, 3215 AGINGTICKSELf, 0); 3216 soc_reg_field_set(unit, PKTEXTAGINGTIMERr, &pat_val, 3217 DURATIONSELECTf, aging_ticks); 3218 SOC_IF_ERROR_RETURN(WRITE_PKTEXTAGINGTIMERr(unit, pat_val)); 3219 3220 /* Set all COSQs to the same value 3221 * - They use the maximum of NUM_MMU_AGE_CYCLES to expire */ 3222 SOC_IF_ERROR_RETURN(WRITE_PKTEXTAGINGLIMIT0r(unit, 0)); /* Aesthetic */ 3223 SOC_IF_ERROR_RETURN(WRITE_PKTEXTAGINGLIMIT1r(unit, 0)); /* Aesthetic */ 3224 } 3225 3226 } 3227 3228 return BCM_E_NONE; 3229 } 3230 #endif 3231 3232 STATIC int 3233 _bcm_fb_pkt_age_get(int unit, int *arg) 3234 { 3235 uint32 timerval, limitval, mask; 3236 int i, loopcount; 3237 3238 /* Check that all COSQs have the same value */ 3239 SOC_IF_ERROR_RETURN(READ_PKTAGINGLIMITr(unit, &limitval)); 3240 limitval &= 0xFFFFFF; /* AGINGLIMITCOSn fields only */ 3241 loopcount = mask = soc_reg_field_get(unit, PKTAGINGLIMITr, 3242 limitval, AGINGLIMITCOS0f); 3243 /* Make mask of eight identical AGINGLIMITCOSn fields */ 3244 for (i = 1; i < 8; i++) { 3245 mask = (mask << 3) | loopcount; 3246 } 3247 3248 if (mask != limitval) { 3249 /* COSQs currently are not programmed identically */ 3250 return BCM_E_CONFIG; 3251 } 3252 3253 /* Return the (common) setting */ 3254 loopcount = NUM_MMU_AGE_CYCLES - loopcount; 3255 SOC_IF_ERROR_RETURN(READ_PKTAGINGTIMERr(unit, &timerval)); 3256 3257 *arg = 3258 (loopcount * 3259 soc_reg_field_get(unit, PKTAGINGTIMERr, timerval, DURATIONSELECTf)) / 8; 3260 3261 return BCM_E_NONE; 3262 } 3263 3264 #ifdef BCM_TRX_SUPPORT 3265 STATIC int 3266 _bcm_ts_pkt_age_get(int unit, int *arg) 3267 { 3268 uint32 timerval, limitval, mask; 3269 int i, loopcount; 3270 3271 /* Check that all COSQs have the same value */ 3272 SOC_IF_ERROR_RETURN(READ_PKTAGINGLIMIT0r(unit, &limitval)); 3273 limitval &= 0xFFFFFF; /* AGINGLIMITPRIn fields only */ 3274 loopcount = mask = soc_reg_field_get(unit, PKTAGINGLIMIT0r, 3275 limitval, AGINGLIMITPRI0f); 3276 /* Make mask of eight identical AGINGLIMITPRIn fields */ 3277 for (i = 1; i < 8; i++) { 3278 mask = (mask << 3) | loopcount; 3279 } 3280 3281 if (mask != limitval) { 3282 /* COSQs currently are not programmed identically */ 3283 return BCM_E_CONFIG; 3284 } 3285 3286 /* Check second register */ 3287 SOC_IF_ERROR_RETURN(READ_PKTAGINGLIMIT1r(unit, &limitval)); 3288 limitval &= 0xFFFFFF; /* AGINGLIMITPRIn fields only */ 3289 if (mask != limitval) { 3290 /* COSQs currently are not programmed identically */ 3291 return BCM_E_CONFIG; 3292 } 3293 3294 /* Return the (common) setting */ 3295 loopcount = NUM_MMU_AGE_CYCLES - loopcount; 3296 SOC_IF_ERROR_RETURN(READ_PKTAGINGTIMERr(unit, &timerval)); 3297 3298 *arg = 3299 (loopcount * 3300 soc_reg_field_get(unit, PKTAGINGTIMERr, timerval, DURATIONSELECTf)) / 8; 3301 3302 return BCM_E_NONE; 3303 } 3304 #endif 3305 3306 #ifdef BCM_KATANA_SUPPORT 3307 STATIC int 3308 _bcm_kt_pkt_age_get(int unit, int *arg) 3309 { 3310 uint32 timerval, limitval, mask; 3311 int i, loopcount; 3312 3313 /* Check that all COSQs have the same value */ 3314 SOC_IF_ERROR_RETURN(READ_PKTINTAGINGLIMIT0r(unit, &limitval)); 3315 limitval &= 0xFFFFFF; /* AGINGLIMITPRIn fields only */ 3316 loopcount = mask = soc_reg_field_get(unit, PKTINTAGINGLIMIT0r, 3317 limitval, AGINGLIMITPRI0f); 3318 /* Make mask of eight identical AGINGLIMITPRIn fields */ 3319 for (i = 1; i < 8; i++) { 3320 mask = (mask << 3) | loopcount; 3321 } 3322 3323 if (mask != limitval) { 3324 /* COSQs currently are not programmed identically */ 3325 return BCM_E_CONFIG; 3326 } 3327 3328 /* Check second register */ 3329 SOC_IF_ERROR_RETURN(READ_PKTINTAGINGLIMIT1r(unit, &limitval)); 3330 limitval &= 0xFFFFFF; /* AGINGLIMITPRIn fields only */ 3331 if (mask != limitval) { 3332 /* COSQs currently are not programmed identically */ 3333 return BCM_E_CONFIG; 3334 } 3335 3336 /* Return the (common) setting */ 3337 loopcount = NUM_MMU_AGE_CYCLES - loopcount; 3338 SOC_IF_ERROR_RETURN(READ_PKTINTAGINGTIMERr(unit, &timerval)); 3339 3340 *arg = 3341 (loopcount * 3342 soc_reg_field_get(unit, PKTINTAGINGTIMERr, timerval, DURATIONSELECTf)) / 8; 3343 3344 return BCM_E_NONE; 3345 } 3346 #endif 3347 3348 STATIC int 3349 _bcm_fb_er_color_mode_set(int unit, bcm_port_t port, int arg) 3350 { 3351 bcm_port_t portout = port; 3352 #ifdef BCM_TRIDENT2_SUPPORT 3353 if (BCM_GPORT_IS_PROXY(port)) { 3354 BCM_IF_ERROR_RETURN( 3355 _bcm_esw_switch_control_gport_resolve(unit, port, &portout)); 3356 } 3357 #endif /* BCM_TRIDENT2_SUPPORT */ 3358 3359 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 3360 if (soc_feature(unit, soc_feature_egr_vlan_control_is_memory)) { 3361 uint32 cfi_as_cng; 3362 3363 switch (arg) { 3364 case BCM_COLOR_PRIORITY: 3365 cfi_as_cng = 0; 3366 break; 3367 case BCM_COLOR_OUTER_CFI: 3368 cfi_as_cng = 0xf; 3369 break; 3370 case BCM_COLOR_INNER_CFI: 3371 cfi_as_cng = 0x1; 3372 break; 3373 default: 3374 return BCM_E_PARAM; 3375 } 3376 3377 if (soc_feature(unit, soc_feature_egr_all_profile)) { 3378 BCM_IF_ERROR_RETURN 3379 (bcm_esw_port_egr_lport_field_set(unit, port, 3380 EGR_VLAN_CONTROL_1m, CFI_AS_CNGf, cfi_as_cng)); 3381 } else { 3382 #if defined (BCM_HGPROXY_COE_SUPPORT) 3383 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 3384 BCM_GPORT_IS_SUBPORT_PORT(port)) { 3385 BCM_IF_ERROR_RETURN( 3386 bcm_esw_port_egr_lport_field_set(unit, port, 3387 EGR_VLAN_CONTROL_1m, CFI_AS_CNGf, cfi_as_cng)); 3388 } else 3389 #endif 3390 { 3391 uint32 oldval; 3392 egr_vlan_control_1_entry_t entry; 3393 BCM_IF_ERROR_RETURN( 3394 READ_EGR_VLAN_CONTROL_1m(unit, MEM_BLOCK_ANY, portout, 3395 &entry)); 3396 3397 oldval = soc_EGR_VLAN_CONTROL_1m_field32_get(unit, &entry, 3398 CFI_AS_CNGf); 3399 if (oldval != cfi_as_cng) { 3400 soc_EGR_VLAN_CONTROL_1m_field32_set( 3401 unit, &entry, CFI_AS_CNGf, cfi_as_cng); 3402 3403 BCM_IF_ERROR_RETURN( 3404 _bcm_esw_port_config_set(unit, portout, 3405 _bcmPortCfiAsCng, cfi_as_cng)); 3406 3407 BCM_IF_ERROR_RETURN( 3408 WRITE_EGR_VLAN_CONTROL_1m(unit, MEM_BLOCK_ANY, portout, 3409 &entry)); 3410 } 3411 } 3412 } 3413 } else 3414 #endif 3415 #if defined(BCM_TOMAHAWK3_SUPPORT) 3416 if (SOC_IS_TOMAHAWK3(unit)) { 3417 uint8 cfi_as_cng = 0; 3418 uint32 val; 3419 uint64 rval64; 3420 3421 switch (arg) { 3422 case BCM_COLOR_PRIORITY: 3423 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 3424 if (soc_reg64_field32_get( 3425 unit, ING_CONFIG_64r, rval64, CFI_AS_CNGf)) { 3426 soc_reg64_field32_set( 3427 unit, ING_CONFIG_64r, &rval64, CFI_AS_CNGf, 0); 3428 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, rval64)); 3429 } 3430 break; 3431 case BCM_COLOR_OUTER_CFI: 3432 cfi_as_cng = 0xf; 3433 break; 3434 case BCM_COLOR_INNER_CFI: 3435 return BCM_E_UNAVAIL; 3436 default: 3437 return BCM_E_PARAM; 3438 } 3439 3440 BCM_IF_ERROR_RETURN(READ_EGR_VLAN_CONTROL_1r(unit, portout, &val)); 3441 if (cfi_as_cng != 3442 soc_reg_field_get(unit, EGR_VLAN_CONTROL_1r, val, CFI_AS_CNGf)) { 3443 SOC_IF_ERROR_RETURN(_bcm_esw_port_config_set( 3444 unit, port, _bcmPortCfiAsCng, cfi_as_cng)); 3445 soc_reg_field_set( 3446 unit, EGR_VLAN_CONTROL_1r, &val, CFI_AS_CNGf, cfi_as_cng); 3447 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, portout, val)); 3448 } 3449 } else 3450 #endif /* BCM_TOMAHAWK3_SUPPORT */ 3451 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) \ 3452 || defined(BCM_RAPTOR_SUPPORT) 3453 if (SOC_IS_FIREBOLT2(unit) || SOC_IS_TRX(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 3454 uint32 val, oval, rval, cfi_as_cng; 3455 uint64 rval64; 3456 3457 BCM_IF_ERROR_RETURN 3458 (READ_EGR_VLAN_CONTROL_1r(unit, portout, &val)); 3459 3460 oval = val; 3461 3462 switch (arg) { 3463 case BCM_COLOR_PRIORITY: 3464 cfi_as_cng = 0; 3465 if (SOC_IS_TRX(unit)) { 3466 if (soc_feature(unit, soc_feature_color_inner_cfi)) { 3467 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 3468 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3469 CFI_AS_CNGf, 0); 3470 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3471 CVLAN_CFI_AS_CNGf, 0); 3472 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, rval64)); 3473 } 3474 } 3475 break; 3476 case BCM_COLOR_OUTER_CFI: 3477 cfi_as_cng = 0xf; 3478 break; 3479 case BCM_COLOR_INNER_CFI: 3480 if (SOC_IS_TRX(unit)) { 3481 if (soc_feature(unit, soc_feature_color_inner_cfi)) { 3482 cfi_as_cng = 0x0; 3483 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 3484 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3485 CFI_AS_CNGf, 0); 3486 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3487 CVLAN_CFI_AS_CNGf, 1); 3488 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, rval64)); 3489 } else { 3490 return BCM_E_UNAVAIL; 3491 } 3492 } else { 3493 cfi_as_cng = 0x1; 3494 } 3495 break; 3496 default: 3497 return BCM_E_PARAM; 3498 } 3499 3500 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &val, 3501 CFI_AS_CNGf, cfi_as_cng); 3502 if (oval != val) { 3503 BCM_IF_ERROR_RETURN 3504 (_bcm_esw_port_config_set(unit, port, 3505 _bcmPortCfiAsCng, 3506 cfi_as_cng)); 3507 /* Workaround for FB2 HW bug. For ports with DT_MODE = 0, 3508 * CNG is incorrectly picked from CNG_MAPr 3509 * instead of ING_PRI_CNG_MAP table. 3510 * GNATS 9151 */ 3511 if (SOC_IS_FIREBOLT2(unit)) { 3512 BCM_IF_ERROR_RETURN(READ_ING_CONFIGr(unit, &rval)); 3513 if((soc_reg_field_get(unit, ING_CONFIGr, rval, 3514 DT_MODEf) == 0) && 3515 (arg == BCM_COLOR_OUTER_CFI || 3516 arg == BCM_COLOR_INNER_CFI)) { 3517 BCM_IF_ERROR_RETURN 3518 (_bcm_esw_port_config_set(unit, port, 3519 _bcmPortNni, 3520 1)); 3521 } 3522 } 3523 BCM_IF_ERROR_RETURN 3524 (WRITE_EGR_VLAN_CONTROL_1r(unit, portout, val)); 3525 } 3526 } else 3527 #endif 3528 if (SOC_IS_HUMV(unit)) { 3529 return BCM_E_UNAVAIL; 3530 } else { 3531 uint32 val, oval, eval = 0, oeval; 3532 int inner_cfg = soc_feature(unit, soc_feature_color_inner_cfi); 3533 soc_reg_t cfg_reg, egr_cfg_reg; 3534 3535 cfg_reg = ING_CONFIGr; 3536 egr_cfg_reg = EGR_CONFIGr; 3537 3538 SOC_IF_ERROR_RETURN(soc_reg_read_any_block(unit, cfg_reg, &val)); 3539 oval = val; 3540 if (egr_cfg_reg != INVALIDr) { 3541 SOC_IF_ERROR_RETURN 3542 (soc_reg_read_any_block(unit, egr_cfg_reg, &eval)); 3543 } 3544 oeval = eval; 3545 switch (arg) { 3546 case BCM_COLOR_PRIORITY: 3547 soc_reg_field_set(unit, cfg_reg, &val, CFI_AS_CNGf, 0); 3548 if (inner_cfg) { 3549 soc_reg_field_set(unit, cfg_reg, &val, CVLAN_CFI_AS_CNGf, 0); 3550 } 3551 if (egr_cfg_reg != INVALIDr) { 3552 soc_reg_field_set(unit, egr_cfg_reg, &eval, CFI_AS_CNGf, 0); 3553 } 3554 break; 3555 case BCM_COLOR_OUTER_CFI: 3556 soc_reg_field_set(unit, cfg_reg, &val, CFI_AS_CNGf, 1); 3557 if (inner_cfg) { 3558 soc_reg_field_set(unit, cfg_reg, &val, CVLAN_CFI_AS_CNGf, 0); 3559 } 3560 if (egr_cfg_reg != INVALIDr) { 3561 soc_reg_field_set(unit, egr_cfg_reg, &eval, CFI_AS_CNGf, 1); 3562 } 3563 break; 3564 case BCM_COLOR_INNER_CFI: 3565 if (inner_cfg) { 3566 soc_reg_field_set(unit, cfg_reg, &val, CFI_AS_CNGf, 0); 3567 soc_reg_field_set(unit, cfg_reg, &val, CVLAN_CFI_AS_CNGf, 1); 3568 } else { 3569 return BCM_E_UNAVAIL; 3570 } 3571 break; 3572 default: 3573 return BCM_E_PARAM; 3574 } 3575 if (oval != val) { 3576 SOC_IF_ERROR_RETURN(soc_reg_write_all_blocks(unit, cfg_reg, val)); 3577 } 3578 if ((egr_cfg_reg != INVALIDr) && (oeval != eval)) { 3579 SOC_IF_ERROR_RETURN 3580 (soc_reg_write_all_blocks(unit, egr_cfg_reg, eval)); 3581 } 3582 } 3583 return BCM_E_NONE; 3584 } 3585 3586 STATIC int 3587 _bcm_fb_er_color_mode_get(int unit, bcm_port_t port, int *arg) 3588 { 3589 #ifdef BCM_TRIDENT2_SUPPORT 3590 if (BCM_GPORT_IS_PROXY(port)) { 3591 BCM_IF_ERROR_RETURN( 3592 _bcm_esw_switch_control_gport_resolve(unit, port, &port)); 3593 } 3594 #endif /* BCM_TRIDENT2_SUPPORT */ 3595 3596 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 3597 if (soc_feature(unit, soc_feature_egr_vlan_control_is_memory)) { 3598 uint32 cfi_as_cng; 3599 if (soc_feature(unit, soc_feature_egr_all_profile)) { 3600 BCM_IF_ERROR_RETURN( 3601 bcm_esw_port_egr_lport_field_get( 3602 unit, port, EGR_VLAN_CONTROL_1m, 3603 CFI_AS_CNGf, &cfi_as_cng)); 3604 } else { 3605 #if defined (BCM_HGPROXY_COE_SUPPORT) 3606 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 3607 BCM_GPORT_IS_SUBPORT_PORT(port)) { 3608 BCM_IF_ERROR_RETURN( 3609 bcm_esw_port_egr_lport_field_get(unit, port, 3610 EGR_VLAN_CONTROL_1m, CFI_AS_CNGf, &cfi_as_cng)); 3611 } else 3612 #endif 3613 { 3614 egr_vlan_control_1_entry_t entry; 3615 BCM_IF_ERROR_RETURN( 3616 soc_mem_read(unit, EGR_VLAN_CONTROL_1m, MEM_BLOCK_ANY, port, 3617 &entry)); 3618 3619 cfi_as_cng = soc_EGR_VLAN_CONTROL_1m_field32_get( 3620 unit, &entry, CFI_AS_CNGf); 3621 } 3622 } 3623 if (cfi_as_cng == 0) { 3624 *arg = BCM_COLOR_PRIORITY; 3625 } else if (cfi_as_cng == 1) { 3626 *arg = BCM_COLOR_INNER_CFI; 3627 } else { 3628 *arg = BCM_COLOR_OUTER_CFI; 3629 } 3630 } else 3631 #endif 3632 3633 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) \ 3634 || defined(BCM_RAPTOR_SUPPORT) 3635 if (SOC_IS_FIREBOLT2(unit) || SOC_IS_TRX(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 3636 uint32 val, cfi_as_cng; 3637 uint64 rval64; 3638 int cvlan_cfi_as_cng = 0; 3639 3640 if (soc_feature(unit, soc_feature_color_inner_cfi)) { 3641 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 3642 cvlan_cfi_as_cng = soc_reg64_field32_get(unit, ING_CONFIG_64r, rval64, 3643 CVLAN_CFI_AS_CNGf); 3644 } 3645 3646 BCM_IF_ERROR_RETURN 3647 (READ_EGR_VLAN_CONTROL_1r(unit, port, &val)); 3648 3649 cfi_as_cng = soc_reg_field_get(unit, EGR_VLAN_CONTROL_1r, val, 3650 CFI_AS_CNGf); 3651 if (cfi_as_cng == 0) { 3652 if (cvlan_cfi_as_cng && soc_feature(unit, soc_feature_color_inner_cfi)) { 3653 *arg = BCM_COLOR_INNER_CFI; 3654 } else { 3655 *arg = BCM_COLOR_PRIORITY; 3656 } 3657 } else if ((cfi_as_cng == 1) && !SOC_IS_TRX(unit)) { 3658 *arg = BCM_COLOR_INNER_CFI; 3659 } else { 3660 *arg = BCM_COLOR_OUTER_CFI; 3661 } 3662 } else 3663 #endif 3664 { 3665 uint32 val; 3666 soc_reg_t cfg_reg; 3667 cfg_reg = ING_CONFIGr; 3668 3669 SOC_IF_ERROR_RETURN(soc_reg_read_any_block(unit, cfg_reg, &val)); 3670 3671 3672 if (soc_reg_field_get(unit, cfg_reg, val, CFI_AS_CNGf)) { 3673 *arg = BCM_COLOR_OUTER_CFI; 3674 } else if (soc_feature(unit, soc_feature_color_inner_cfi) && 3675 soc_reg_field_get(unit, cfg_reg, val, CVLAN_CFI_AS_CNGf)) { 3676 *arg = BCM_COLOR_INNER_CFI; 3677 } else { 3678 *arg = BCM_COLOR_PRIORITY; 3679 } 3680 } 3681 return BCM_E_NONE; 3682 } 3683 3684 /* 3685 * Function: 3686 * _bcm_fb_er_hashselect_set 3687 * Description: 3688 * Set the Hash Select for L2, L3 or Multipath type. 3689 * Parameters: 3690 * unit - StrataSwitch PCI device unit number (driver internal). 3691 * type - The desired configuration parameter to set. 3692 * arg - BCM_HASH_* 3693 * Returns: 3694 * BCM_E_xxxx 3695 */ 3696 3697 STATIC int 3698 _bcm_fb_er_hashselect_set(int unit, bcm_switch_control_t type, int arg) 3699 { 3700 uint32 hash_control, val=0; 3701 soc_field_t field; 3702 soc_reg_t hash_reg = HASH_CONTROLr; 3703 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 3704 defined(BCM_TRX_SUPPORT) 3705 int dual = FALSE; 3706 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 3707 3708 switch (type) { 3709 case bcmSwitchHashL2: 3710 field = L2_AND_VLAN_MAC_HASH_SELECTf; 3711 if (!soc_reg_field_valid(unit, hash_reg, field)) { 3712 return BCM_E_UNAVAIL; 3713 } 3714 break; 3715 case bcmSwitchHashL3: 3716 if (soc_reg_field_valid(unit, HASH_CONTROLr, L3_HASH_SELECTf) && 3717 soc_feature(unit, soc_feature_l3)) { 3718 field = L3_HASH_SELECTf; 3719 } else { 3720 return BCM_E_UNAVAIL; 3721 } 3722 break; 3723 case bcmSwitchHashMultipath: 3724 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_SELf) && 3725 soc_feature(unit, soc_feature_l3)) { 3726 field = ECMP_HASH_SELf; 3727 if ((arg == BCM_HASH_CRC16L) || (arg == BCM_HASH_CRC16U)) { 3728 return BCM_E_PARAM; 3729 } 3730 } else { 3731 return BCM_E_UNAVAIL; 3732 } 3733 break; 3734 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 3735 defined(BCM_TRX_SUPPORT) 3736 case bcmSwitchHashL2Dual: 3737 dual = TRUE; 3738 hash_reg = L2_AUX_HASH_CONTROLr; 3739 field = HASH_SELECTf; 3740 if (!soc_reg_field_valid(unit, hash_reg, field)) { 3741 return BCM_E_UNAVAIL; 3742 } 3743 break; 3744 case bcmSwitchHashL3Dual: 3745 if (soc_reg_field_valid(unit, L3_AUX_HASH_CONTROLr, HASH_SELECTf) && 3746 soc_feature(unit, soc_feature_l3)) { 3747 dual = TRUE; 3748 hash_reg = L3_AUX_HASH_CONTROLr; 3749 field = HASH_SELECTf; 3750 } else { 3751 return BCM_E_UNAVAIL; 3752 } 3753 break; 3754 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 3755 #if defined(BCM_TRIUMPH_SUPPORT) 3756 case bcmSwitchHashIpfixIngress: 3757 if (soc_reg_field_valid(unit, ING_IPFIX_HASH_CONTROLr, HASH_SELECT_Af)) { 3758 hash_reg = ING_IPFIX_HASH_CONTROLr; 3759 field = HASH_SELECT_Af; 3760 } else { 3761 return BCM_E_UNAVAIL; 3762 } 3763 break; 3764 case bcmSwitchHashIpfixEgress: 3765 if (soc_reg_field_valid(unit, EGR_IPFIX_HASH_CONTROLr, HASH_SELECT_Af)) { 3766 hash_reg = EGR_IPFIX_HASH_CONTROLr; 3767 field = HASH_SELECT_Af; 3768 } else { 3769 return BCM_E_UNAVAIL; 3770 } 3771 break; 3772 case bcmSwitchHashIpfixIngressDual: 3773 if (soc_reg_field_valid(unit, ING_IPFIX_HASH_CONTROLr, HASH_SELECT_Bf)) { 3774 hash_reg = ING_IPFIX_HASH_CONTROLr; 3775 field = HASH_SELECT_Bf; 3776 } else { 3777 return BCM_E_UNAVAIL; 3778 } 3779 break; 3780 case bcmSwitchHashIpfixEgressDual: 3781 if (soc_reg_field_valid(unit, EGR_IPFIX_HASH_CONTROLr, HASH_SELECT_Bf)) { 3782 hash_reg = EGR_IPFIX_HASH_CONTROLr; 3783 field = HASH_SELECT_Bf; 3784 } else { 3785 return BCM_E_UNAVAIL; 3786 } 3787 break; 3788 case bcmSwitchHashMPLS: 3789 if (soc_reg_field_valid(unit, MPLS_ENTRY_HASH_CONTROLr, HASH_SELECT_Af)) { 3790 hash_reg = MPLS_ENTRY_HASH_CONTROLr; 3791 field = HASH_SELECT_Af; 3792 } else { 3793 return BCM_E_UNAVAIL; 3794 } 3795 break; 3796 case bcmSwitchHashMPLSDual: 3797 if (soc_reg_field_valid(unit, MPLS_ENTRY_HASH_CONTROLr, HASH_SELECT_Bf)) { 3798 hash_reg = MPLS_ENTRY_HASH_CONTROLr; 3799 field = HASH_SELECT_Bf; 3800 } else { 3801 return BCM_E_UNAVAIL; 3802 } 3803 break; 3804 #else 3805 case bcmSwitchHashIpfixIngress: 3806 case bcmSwitchHashIpfixEgress: 3807 case bcmSwitchHashIpfixIngressDual: 3808 case bcmSwitchHashIpfixEgressDual: 3809 case bcmSwitchHashMPLS: 3810 case bcmSwitchHashMPLSDual: 3811 return BCM_E_UNAVAIL; 3812 #endif /* BCM_TRIUMPH_SUPPORT */ 3813 #if defined(BCM_TRX_SUPPORT) 3814 case bcmSwitchHashVlanTranslate: 3815 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 3816 hash_reg = VLAN_XLATE_HASH_CONTROLr; 3817 field = HASH_SELECT_Af; 3818 } else { 3819 return BCM_E_UNAVAIL; 3820 } 3821 break; 3822 case bcmSwitchHashVlanTranslateDual: 3823 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 3824 hash_reg = VLAN_XLATE_HASH_CONTROLr; 3825 field = HASH_SELECT_Bf; 3826 } else { 3827 return BCM_E_UNAVAIL; 3828 } 3829 break; 3830 case bcmSwitchHashEgressVlanTranslate: 3831 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 3832 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 3833 field = HASH_SELECT_Af; 3834 } else { 3835 return BCM_E_UNAVAIL; 3836 } 3837 break; 3838 case bcmSwitchHashEgressVlanTranslateDual: 3839 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 3840 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 3841 field = HASH_SELECT_Bf; 3842 } else { 3843 return BCM_E_UNAVAIL; 3844 } 3845 break; 3846 #else 3847 case bcmSwitchHashVlanTranslate: 3848 case bcmSwitchHashVlanTranslateDual: 3849 case bcmSwitchHashEgressVlanTranslate: 3850 case bcmSwitchHashEgressVlanTranslateDual: 3851 return BCM_E_UNAVAIL; 3852 #endif /* BCM_TRX_SUPPORT */ 3853 #if defined(BCM_TRIUMPH3_SUPPORT) 3854 case bcmSwitchHashWlanPort: 3855 if (soc_feature(unit, soc_feature_wlan) && 3856 (soc_reg_field_valid(unit, AXP_WRX_SVP_HASH_CTRLr, SELECT_Af))) { 3857 hash_reg = AXP_WRX_SVP_HASH_CTRLr; 3858 field = SELECT_Af; 3859 } else { 3860 return BCM_E_UNAVAIL; 3861 } 3862 break; 3863 case bcmSwitchHashWlanPortDual: 3864 if (soc_feature(unit, soc_feature_wlan) && 3865 (soc_reg_field_valid(unit, AXP_WRX_SVP_HASH_CTRLr, SELECT_Bf))) { 3866 hash_reg = AXP_WRX_SVP_HASH_CTRLr; 3867 field = SELECT_Bf; 3868 } else { 3869 return BCM_E_UNAVAIL; 3870 } 3871 break; 3872 case bcmSwitchHashWlanClient: 3873 if (soc_feature(unit, soc_feature_wlan) && 3874 (soc_reg_field_valid(unit, AXP_WRX_WCD_HASH_CTRLr, SELECT_Af))) { 3875 hash_reg = AXP_WRX_WCD_HASH_CTRLr; 3876 field = SELECT_Af; 3877 } else { 3878 return BCM_E_UNAVAIL; 3879 } 3880 break; 3881 case bcmSwitchHashWlanClientDual: 3882 if (soc_feature(unit, soc_feature_wlan) && 3883 (soc_reg_field_valid(unit, AXP_WRX_WCD_HASH_CTRLr, SELECT_Bf))) { 3884 hash_reg = AXP_WRX_WCD_HASH_CTRLr; 3885 field = SELECT_Bf; 3886 } else { 3887 return BCM_E_UNAVAIL; 3888 } 3889 break; 3890 case bcmSwitchHashRegexAction: 3891 if (soc_feature(unit, soc_feature_regex) && 3892 (soc_reg_field_valid(unit, FT_HASH_CONTROLr, HASH_SELECT_Af))) { 3893 hash_reg = FT_HASH_CONTROLr; 3894 field = HASH_SELECT_Af; 3895 } else { 3896 return BCM_E_UNAVAIL; 3897 } 3898 break; 3899 case bcmSwitchHashRegexActionDual: 3900 if (soc_feature(unit, soc_feature_regex) && 3901 (soc_reg_field_valid(unit, FT_HASH_CONTROLr, HASH_SELECT_Bf))) { 3902 hash_reg = FT_HASH_CONTROLr; 3903 field = HASH_SELECT_Bf; 3904 } else { 3905 return BCM_E_UNAVAIL; 3906 } 3907 break; 3908 #else 3909 case bcmSwitchHashWlanPort: 3910 case bcmSwitchHashWlanPortDual: 3911 case bcmSwitchHashWlanClient: 3912 case bcmSwitchHashWlanClientDual: 3913 case bcmSwitchHashRegexAction: 3914 case bcmSwitchHashRegexActionDual: 3915 return BCM_E_UNAVAIL; 3916 #endif /* defined(BCM_TRIUMPH3_SUPPORT) */ 3917 #if defined(BCM_TRIDENT2_SUPPORT) 3918 case bcmSwitchHashL3DNATPool: 3919 if (soc_feature(unit, soc_feature_nat) && soc_reg_field_valid(unit, 3920 ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr, HASH_SELECT_Af)) { 3921 hash_reg = ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr; 3922 field = HASH_SELECT_Af; 3923 } else { 3924 return BCM_E_UNAVAIL; 3925 } 3926 break; 3927 case bcmSwitchHashL3DNATPoolDual: 3928 if (soc_feature(unit, soc_feature_nat) && soc_reg_field_valid(unit, 3929 ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr, HASH_SELECT_Bf)) { 3930 hash_reg = ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr; 3931 field = HASH_SELECT_Bf; 3932 } else { 3933 return BCM_E_UNAVAIL; 3934 } 3935 break; 3936 case bcmSwitchHashVpVlanMemberIngress: 3937 case bcmSwitchHashVpVlanMemberIngressDual: 3938 if (soc_feature(unit, soc_feature_ing_vp_vlan_membership)) { 3939 hash_reg = ING_VP_VLAN_MEMBERSHIP_HASH_CONTROLr; 3940 field = type == bcmSwitchHashVpVlanMemberIngress? 3941 HASH_SELECT_Af: HASH_SELECT_Bf; 3942 } else { 3943 return BCM_E_UNAVAIL; 3944 } 3945 break; 3946 case bcmSwitchHashVpVlanMemberEgress: 3947 case bcmSwitchHashVpVlanMemberEgressDual: 3948 if (soc_feature(unit, soc_feature_egr_vp_vlan_membership)) { 3949 hash_reg = EGR_VP_VLAN_MEMBERSHIP_HASH_CONTROLr; 3950 field = type == bcmSwitchHashVpVlanMemberEgress? 3951 HASH_SELECT_Af: HASH_SELECT_Bf; 3952 } else { 3953 return BCM_E_UNAVAIL; 3954 } 3955 break; 3956 case bcmSwitchHashL2Endpoint: 3957 case bcmSwitchHashL2EndpointDual: 3958 if (SOC_REG_IS_VALID(unit, L2_ENDPOINT_ID_HASH_CONTROLr)) { 3959 hash_reg = L2_ENDPOINT_ID_HASH_CONTROLr; 3960 field = (type == bcmSwitchHashL2Endpoint) ? 3961 HASH_SELECT_Af: HASH_SELECT_Bf; 3962 } else { 3963 return BCM_E_UNAVAIL; 3964 } 3965 break; 3966 case bcmSwitchHashEndpointQueueMap: 3967 case bcmSwitchHashEndpointQueueMapDual: 3968 if (SOC_REG_IS_VALID(unit, ENDPOINT_QUEUE_MAP_HASH_CONTROLr)) { 3969 hash_reg = ENDPOINT_QUEUE_MAP_HASH_CONTROLr; 3970 field = (type == bcmSwitchHashEndpointQueueMap) ? 3971 HASH_SELECT_Af: HASH_SELECT_Bf; 3972 } else { 3973 return BCM_E_UNAVAIL; 3974 } 3975 break; 3976 #endif /* BCM_TRIDENT2_SUPPORT */ 3977 #if defined(BCM_KATANA2_SUPPORT) 3978 case bcmSwitchHashOamEgress: 3979 if (soc_reg_field_valid(unit, EGR_MP_GROUP_HASH_CONTROLr, 3980 HASH_SELECT_Af)) { 3981 hash_reg = EGR_MP_GROUP_HASH_CONTROLr; 3982 field = HASH_SELECT_Af; 3983 } else { 3984 return BCM_E_UNAVAIL; 3985 } 3986 break; 3987 case bcmSwitchHashOamEgressDual: 3988 if (soc_reg_field_valid(unit, EGR_MP_GROUP_HASH_CONTROLr, 3989 HASH_SELECT_Bf)) { 3990 hash_reg = EGR_MP_GROUP_HASH_CONTROLr; 3991 field = HASH_SELECT_Bf; 3992 } else { 3993 return BCM_E_UNAVAIL; 3994 } 3995 break; 3996 #endif /* BCM_KATANA2_SUPPORT */ 3997 #if defined (BCM_SABER2_SUPPORT) 3998 case bcmSwitchHashOam: 3999 if (soc_reg_field_valid(unit, MP_GROUP_HASH_CONTROLr, 4000 HASH_SELECT_Af)) { 4001 hash_reg = MP_GROUP_HASH_CONTROLr; 4002 field = HASH_SELECT_Af; 4003 } else { 4004 return BCM_E_UNAVAIL; 4005 } 4006 break; 4007 case bcmSwitchHashOamDual: 4008 if (soc_reg_field_valid(unit, MP_GROUP_HASH_CONTROLr, 4009 HASH_SELECT_Bf)) { 4010 hash_reg = MP_GROUP_HASH_CONTROLr; 4011 field = HASH_SELECT_Bf; 4012 } else { 4013 return BCM_E_UNAVAIL; 4014 } 4015 break; 4016 #endif /* BCM_SABER2_SUPPORT */ 4017 default: 4018 return BCM_E_PARAM; 4019 } 4020 4021 switch (arg) { 4022 case BCM_HASH_ZERO: 4023 val = FB_HASH_ZERO; 4024 break; 4025 case BCM_HASH_LSB: 4026 val = FB_HASH_LSB; 4027 break; 4028 case BCM_HASH_CRC16L: 4029 val = FB_HASH_CRC16_LOWER; 4030 break; 4031 case BCM_HASH_CRC16U: 4032 val = FB_HASH_CRC16_UPPER; 4033 break; 4034 case BCM_HASH_CRC32L: 4035 val = FB_HASH_CRC32_LOWER; 4036 break; 4037 case BCM_HASH_CRC32U: 4038 val = FB_HASH_CRC32_UPPER; 4039 break; 4040 default: 4041 return BCM_E_PARAM; 4042 } 4043 4044 SOC_IF_ERROR_RETURN 4045 (soc_reg_read_any_block(unit, hash_reg, &hash_control)); 4046 soc_reg_field_set(unit, hash_reg, &hash_control, field, val); 4047 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 4048 defined(BCM_TRX_SUPPORT) 4049 if (dual) { 4050 uint32 base_hash_control, base_hash; 4051 soc_field_t base_field; 4052 4053 base_field = (type == bcmSwitchHashL2Dual) ? 4054 L2_AND_VLAN_MAC_HASH_SELECTf : L3_HASH_SELECTf; 4055 4056 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &base_hash_control)); 4057 base_hash = soc_reg_field_get(unit, HASH_CONTROLr, 4058 base_hash_control, base_field); 4059 soc_reg_field_set(unit, hash_reg, &hash_control, 4060 ENABLEf, (base_hash == val) ? 0 : 1); 4061 #if defined (BCM_RAVEN_SUPPORT) 4062 /* Also write to VLAN_MAC_AUX_HASH_CONTROL for bcmSwitchHashL2Dual */ 4063 if (type == bcmSwitchHashL2Dual && 4064 SOC_REG_IS_VALID(unit, VLAN_MAC_AUX_HASH_CONTROLr)) { 4065 SOC_IF_ERROR_RETURN 4066 (READ_VLAN_MAC_AUX_HASH_CONTROLr(unit, &hash_control)); 4067 soc_reg_field_set(unit, VLAN_MAC_AUX_HASH_CONTROLr, &hash_control, 4068 HASH_SELECTf, val); 4069 soc_reg_field_set(unit, VLAN_MAC_AUX_HASH_CONTROLr, &hash_control, 4070 ENABLEf, (base_hash == val) ? 0 : 1); 4071 SOC_IF_ERROR_RETURN 4072 (WRITE_VLAN_MAC_AUX_HASH_CONTROLr(unit, hash_control)); 4073 } 4074 #endif /* BCM_RAVEN_SUPPORT */ 4075 } 4076 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 4077 SOC_IF_ERROR_RETURN 4078 (soc_reg_write_all_blocks(unit, hash_reg, hash_control)); 4079 4080 return BCM_E_NONE; 4081 } 4082 4083 /* 4084 * Function: 4085 * _bcm_fb_er_hashselect_get 4086 * Description: 4087 * Get the current Hash Select settings. Value returned 4088 * is of the form BCM_HASH_*. 4089 * All switch chip ports are configured with the same settings. 4090 * Parameters: 4091 * unit - StrataSwitch PCI device unit number (driver internal). 4092 * type - The desired configuration parameter to retrieve. 4093 * arg - Pointer to where the retrieved value will be written. 4094 * Returns: 4095 * BCM_E_xxxx 4096 */ 4097 4098 STATIC int 4099 _bcm_fb_er_hashselect_get(int unit, bcm_switch_control_t type, int *arg) 4100 { 4101 uint32 hash_control, val=0; 4102 soc_reg_t hash_reg = HASH_CONTROLr; 4103 soc_field_t field; 4104 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 4105 defined(BCM_TRX_SUPPORT) 4106 int dual = FALSE; 4107 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 4108 4109 switch (type) { 4110 case bcmSwitchHashL2: 4111 field = L2_AND_VLAN_MAC_HASH_SELECTf; 4112 if (!soc_reg_field_valid(unit, hash_reg, field)) { 4113 return BCM_E_UNAVAIL; 4114 } 4115 break; 4116 case bcmSwitchHashL3: 4117 if (soc_reg_field_valid(unit, HASH_CONTROLr, L3_HASH_SELECTf) && 4118 soc_feature(unit, soc_feature_l3)) { 4119 field = L3_HASH_SELECTf; 4120 } else { 4121 return BCM_E_UNAVAIL; 4122 } 4123 break; 4124 case bcmSwitchHashMultipath: 4125 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_SELf) && 4126 soc_feature(unit, soc_feature_l3)) { 4127 field = ECMP_HASH_SELf; 4128 } else { 4129 return BCM_E_UNAVAIL; 4130 } 4131 break; 4132 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 4133 defined(BCM_TRX_SUPPORT) 4134 case bcmSwitchHashL2Dual: 4135 dual = TRUE; 4136 hash_reg = L2_AUX_HASH_CONTROLr; 4137 field = HASH_SELECTf; 4138 if (!soc_reg_field_valid(unit, hash_reg, field)) { 4139 return BCM_E_UNAVAIL; 4140 } 4141 break; 4142 case bcmSwitchHashL3Dual: 4143 if (soc_reg_field_valid(unit, L3_AUX_HASH_CONTROLr, HASH_SELECTf) && 4144 soc_feature(unit, soc_feature_l3)) { 4145 dual = TRUE; 4146 hash_reg = L3_AUX_HASH_CONTROLr; 4147 field = HASH_SELECTf; 4148 } else { 4149 return BCM_E_UNAVAIL; 4150 } 4151 break; 4152 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 4153 #if defined(BCM_TRIUMPH_SUPPORT) 4154 case bcmSwitchHashIpfixIngress: 4155 if (soc_reg_field_valid(unit, ING_IPFIX_HASH_CONTROLr, HASH_SELECT_Af) ) { 4156 hash_reg = ING_IPFIX_HASH_CONTROLr; 4157 field = HASH_SELECT_Af; 4158 } else { 4159 return BCM_E_UNAVAIL; 4160 } 4161 break; 4162 case bcmSwitchHashIpfixEgress: 4163 if (soc_reg_field_valid(unit, EGR_IPFIX_HASH_CONTROLr, HASH_SELECT_Af) ) { 4164 hash_reg = EGR_IPFIX_HASH_CONTROLr; 4165 field = HASH_SELECT_Af; 4166 } else { 4167 return BCM_E_UNAVAIL; 4168 } 4169 break; 4170 case bcmSwitchHashIpfixIngressDual: 4171 if (soc_reg_field_valid(unit, ING_IPFIX_HASH_CONTROLr, HASH_SELECT_Bf) ) { 4172 hash_reg = ING_IPFIX_HASH_CONTROLr; 4173 field = HASH_SELECT_Bf; 4174 } else { 4175 return BCM_E_UNAVAIL; 4176 } 4177 break; 4178 case bcmSwitchHashIpfixEgressDual: 4179 if (soc_reg_field_valid(unit, EGR_IPFIX_HASH_CONTROLr, HASH_SELECT_Bf) ) { 4180 hash_reg = EGR_IPFIX_HASH_CONTROLr; 4181 field = HASH_SELECT_Bf; 4182 } else { 4183 return BCM_E_UNAVAIL; 4184 } 4185 break; 4186 case bcmSwitchHashMPLS: 4187 if (soc_reg_field_valid(unit, MPLS_ENTRY_HASH_CONTROLr, HASH_SELECT_Af)) { 4188 hash_reg = MPLS_ENTRY_HASH_CONTROLr; 4189 field = HASH_SELECT_Af; 4190 } else { 4191 return BCM_E_UNAVAIL; 4192 } 4193 break; 4194 case bcmSwitchHashMPLSDual: 4195 if (soc_reg_field_valid(unit, MPLS_ENTRY_HASH_CONTROLr, HASH_SELECT_Bf)) { 4196 hash_reg = MPLS_ENTRY_HASH_CONTROLr; 4197 field = HASH_SELECT_Bf; 4198 } else { 4199 return BCM_E_UNAVAIL; 4200 } 4201 break; 4202 #else 4203 case bcmSwitchHashIpfixIngress: 4204 case bcmSwitchHashIpfixEgress: 4205 case bcmSwitchHashIpfixIngressDual: 4206 case bcmSwitchHashIpfixEgressDual: 4207 case bcmSwitchHashMPLS: 4208 case bcmSwitchHashMPLSDual: 4209 return BCM_E_UNAVAIL; 4210 #endif /* BCM_TRIUMPH_SUPPORT */ 4211 #if defined(BCM_TRX_SUPPORT) 4212 case bcmSwitchHashVlanTranslate: 4213 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 4214 hash_reg = VLAN_XLATE_HASH_CONTROLr; 4215 field = HASH_SELECT_Af; 4216 } else { 4217 return BCM_E_UNAVAIL; 4218 } 4219 break; 4220 case bcmSwitchHashVlanTranslateDual: 4221 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 4222 hash_reg = VLAN_XLATE_HASH_CONTROLr; 4223 field = HASH_SELECT_Bf; 4224 } else { 4225 return BCM_E_UNAVAIL; 4226 } 4227 break; 4228 case bcmSwitchHashEgressVlanTranslate: 4229 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 4230 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 4231 field = HASH_SELECT_Af; 4232 } else { 4233 return BCM_E_UNAVAIL; 4234 } 4235 break; 4236 case bcmSwitchHashEgressVlanTranslateDual: 4237 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 4238 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 4239 field = HASH_SELECT_Bf; 4240 } else { 4241 return BCM_E_UNAVAIL; 4242 } 4243 break; 4244 #else 4245 case bcmSwitchHashVlanTranslate: 4246 case bcmSwitchHashVlanTranslateDual: 4247 case bcmSwitchHashEgressVlanTranslate: 4248 case bcmSwitchHashEgressVlanTranslateDual: 4249 return BCM_E_UNAVAIL; 4250 #endif /* BCM_TRX_SUPPORT */ 4251 #if defined(BCM_TRIUMPH3_SUPPORT) 4252 case bcmSwitchHashWlanPort: 4253 if (soc_feature(unit, soc_feature_wlan) && 4254 (soc_reg_field_valid(unit, AXP_WRX_SVP_HASH_CTRLr, SELECT_Af))) { 4255 hash_reg = AXP_WRX_SVP_HASH_CTRLr; 4256 field = SELECT_Af; 4257 } else { 4258 return BCM_E_UNAVAIL; 4259 } 4260 break; 4261 case bcmSwitchHashWlanPortDual: 4262 if (soc_feature(unit, soc_feature_wlan) && 4263 (soc_reg_field_valid(unit, AXP_WRX_SVP_HASH_CTRLr, SELECT_Bf))) { 4264 hash_reg = AXP_WRX_SVP_HASH_CTRLr; 4265 field = SELECT_Bf; 4266 } else { 4267 return BCM_E_UNAVAIL; 4268 } 4269 break; 4270 case bcmSwitchHashWlanClient: 4271 if (soc_feature(unit, soc_feature_wlan) && 4272 (soc_reg_field_valid(unit, AXP_WRX_WCD_HASH_CTRLr, SELECT_Af))) { 4273 hash_reg = AXP_WRX_WCD_HASH_CTRLr; 4274 field = SELECT_Af; 4275 } else { 4276 return BCM_E_UNAVAIL; 4277 } 4278 break; 4279 case bcmSwitchHashWlanClientDual: 4280 if (soc_feature(unit, soc_feature_wlan) && 4281 (soc_reg_field_valid(unit, AXP_WRX_WCD_HASH_CTRLr, SELECT_Bf))) { 4282 hash_reg = AXP_WRX_WCD_HASH_CTRLr; 4283 field = SELECT_Bf; 4284 } else { 4285 return BCM_E_UNAVAIL; 4286 } 4287 break; 4288 case bcmSwitchHashRegexAction: 4289 if (soc_feature(unit, soc_feature_regex) && 4290 (soc_reg_field_valid(unit, FT_HASH_CONTROLr, HASH_SELECT_Af))) { 4291 hash_reg = FT_HASH_CONTROLr; 4292 field = HASH_SELECT_Af; 4293 } else { 4294 return BCM_E_UNAVAIL; 4295 } 4296 break; 4297 case bcmSwitchHashRegexActionDual: 4298 if (soc_feature(unit, soc_feature_regex) && 4299 (soc_reg_field_valid(unit, FT_HASH_CONTROLr, HASH_SELECT_Bf))) { 4300 hash_reg = FT_HASH_CONTROLr; 4301 field = HASH_SELECT_Bf; 4302 } else { 4303 return BCM_E_UNAVAIL; 4304 } 4305 break; 4306 #else 4307 case bcmSwitchHashWlanPort: 4308 case bcmSwitchHashWlanPortDual: 4309 case bcmSwitchHashWlanClient: 4310 case bcmSwitchHashWlanClientDual: 4311 case bcmSwitchHashRegexAction: 4312 case bcmSwitchHashRegexActionDual: 4313 return BCM_E_UNAVAIL; 4314 #endif /* defined(BCM_TRIUMPH3_SUPPORT) */ 4315 #if defined(BCM_TRIDENT2_SUPPORT) 4316 case bcmSwitchHashL3DNATPool: 4317 if (soc_feature(unit, soc_feature_nat) && soc_reg_field_valid(unit, 4318 ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr, HASH_SELECT_Af)) { 4319 hash_reg = ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr; 4320 field = HASH_SELECT_Af; 4321 } else { 4322 return BCM_E_UNAVAIL; 4323 } 4324 break; 4325 case bcmSwitchHashL3DNATPoolDual: 4326 if (soc_feature(unit, soc_feature_nat) && soc_reg_field_valid(unit, 4327 ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr, HASH_SELECT_Bf)) { 4328 hash_reg = ING_DNAT_ADDRESS_TYPE_HASH_CONTROLr; 4329 field = HASH_SELECT_Bf; 4330 } else { 4331 return BCM_E_UNAVAIL; 4332 } 4333 break; 4334 case bcmSwitchHashVpVlanMemberIngress: 4335 case bcmSwitchHashVpVlanMemberIngressDual: 4336 if (soc_feature(unit, soc_feature_ing_vp_vlan_membership)) { 4337 hash_reg = ING_VP_VLAN_MEMBERSHIP_HASH_CONTROLr; 4338 field = type == bcmSwitchHashVpVlanMemberIngress? 4339 HASH_SELECT_Af: HASH_SELECT_Bf; 4340 } else { 4341 return BCM_E_UNAVAIL; 4342 } 4343 break; 4344 case bcmSwitchHashVpVlanMemberEgress: 4345 case bcmSwitchHashVpVlanMemberEgressDual: 4346 if (soc_feature(unit, soc_feature_egr_vp_vlan_membership)) { 4347 hash_reg = EGR_VP_VLAN_MEMBERSHIP_HASH_CONTROLr; 4348 field = type == bcmSwitchHashVpVlanMemberEgress? 4349 HASH_SELECT_Af: HASH_SELECT_Bf; 4350 } else { 4351 return BCM_E_UNAVAIL; 4352 } 4353 break; 4354 case bcmSwitchHashL2Endpoint: 4355 case bcmSwitchHashL2EndpointDual: 4356 if (SOC_REG_IS_VALID(unit, L2_ENDPOINT_ID_HASH_CONTROLr)) { 4357 hash_reg = L2_ENDPOINT_ID_HASH_CONTROLr; 4358 field = (type == bcmSwitchHashL2Endpoint) ? 4359 HASH_SELECT_Af: HASH_SELECT_Bf; 4360 } else { 4361 return BCM_E_UNAVAIL; 4362 } 4363 break; 4364 case bcmSwitchHashEndpointQueueMap: 4365 case bcmSwitchHashEndpointQueueMapDual: 4366 if (SOC_REG_IS_VALID(unit, ENDPOINT_QUEUE_MAP_HASH_CONTROLr)) { 4367 hash_reg = ENDPOINT_QUEUE_MAP_HASH_CONTROLr; 4368 field = (type == bcmSwitchHashEndpointQueueMap) ? 4369 HASH_SELECT_Af: HASH_SELECT_Bf; 4370 } else { 4371 return BCM_E_UNAVAIL; 4372 } 4373 break; 4374 #endif /* BCM_TRIDENT2_SUPPORT */ 4375 #if defined(BCM_KATANA2_SUPPORT) 4376 case bcmSwitchHashOamEgress: 4377 if (soc_reg_field_valid(unit, EGR_MP_GROUP_HASH_CONTROLr, 4378 HASH_SELECT_Af)) { 4379 hash_reg = EGR_MP_GROUP_HASH_CONTROLr; 4380 field = HASH_SELECT_Af; 4381 } else { 4382 return BCM_E_UNAVAIL; 4383 } 4384 break; 4385 case bcmSwitchHashOamEgressDual: 4386 if (soc_reg_field_valid(unit, EGR_MP_GROUP_HASH_CONTROLr, 4387 HASH_SELECT_Bf)) { 4388 hash_reg = EGR_MP_GROUP_HASH_CONTROLr; 4389 field = HASH_SELECT_Bf; 4390 } else { 4391 return BCM_E_UNAVAIL; 4392 } 4393 break; 4394 #endif /* BCM_KATANA2_SUPPORT */ 4395 #if defined (BCM_SABER2_SUPPORT) 4396 case bcmSwitchHashOam: 4397 if (soc_reg_field_valid(unit, MP_GROUP_HASH_CONTROLr, 4398 HASH_SELECT_Af)) { 4399 hash_reg = MP_GROUP_HASH_CONTROLr; 4400 field = HASH_SELECT_Af; 4401 } else { 4402 return BCM_E_UNAVAIL; 4403 } 4404 break; 4405 case bcmSwitchHashOamDual: 4406 if (soc_reg_field_valid(unit, MP_GROUP_HASH_CONTROLr, 4407 HASH_SELECT_Bf)) { 4408 hash_reg = MP_GROUP_HASH_CONTROLr; 4409 field = HASH_SELECT_Bf; 4410 } else { 4411 return BCM_E_UNAVAIL; 4412 } 4413 break; 4414 #endif /* BCM_SABER2_SUPPORT */ 4415 default: 4416 return BCM_E_PARAM; 4417 } 4418 4419 SOC_IF_ERROR_RETURN 4420 (soc_reg_read_any_block(unit, hash_reg, &hash_control)); 4421 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 4422 defined(BCM_TRX_SUPPORT) 4423 if (dual && 4424 !soc_reg_field_get(unit, hash_reg, hash_control, ENABLEf)) { 4425 /* Dual hash not enabled, just return primary hash */ 4426 field = (type == bcmSwitchHashL2Dual) ? 4427 L2_AND_VLAN_MAC_HASH_SELECTf : L3_HASH_SELECTf; 4428 hash_reg = HASH_CONTROLr; 4429 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 4430 } 4431 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 4432 val = soc_reg_field_get(unit, hash_reg, hash_control, field); 4433 4434 switch (val) { 4435 case FB_HASH_ZERO: 4436 *arg = BCM_HASH_ZERO; 4437 break; 4438 case FB_HASH_LSB: 4439 *arg = BCM_HASH_LSB; 4440 break; 4441 case FB_HASH_CRC16_LOWER: 4442 *arg = BCM_HASH_CRC16L; 4443 break; 4444 case FB_HASH_CRC16_UPPER: 4445 *arg = BCM_HASH_CRC16U; 4446 break; 4447 case FB_HASH_CRC32_LOWER: 4448 *arg = BCM_HASH_CRC32L; 4449 break; 4450 case FB_HASH_CRC32_UPPER: 4451 *arg = BCM_HASH_CRC32U; 4452 break; 4453 } 4454 return BCM_E_NONE; 4455 } 4456 4457 /* 4458 * Function: 4459 * _bcm_xgs3_hashcontrol_set 4460 * Description: 4461 * Set the Hash Control for L2, L3 or Multipath type. 4462 * Parameters: 4463 * unit - StrataSwitch PCI device unit number (driver internal). 4464 * arg - BCM_HASH_CONTROL* 4465 * Returns: 4466 * BCM_E_xxxx 4467 */ 4468 4469 STATIC int 4470 _bcm_xgs3_hashcontrol_set(int unit, int arg) 4471 { 4472 uint32 hash_control, val=0; 4473 4474 if (!soc_feature(unit, soc_feature_l3)) { 4475 if ((arg & BCM_HASH_CONTROL_MULTIPATH_L4PORTS) || 4476 (arg & BCM_HASH_CONTROL_MULTIPATH_DIP)) { 4477 return BCM_E_UNAVAIL; 4478 } 4479 } 4480 4481 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 4482 4483 val = (arg & BCM_HASH_CONTROL_MULTIPATH_L4PORTS) ? 1 : 0; 4484 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4485 USE_TCP_UDP_PORTSf, val); 4486 4487 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_USE_DIPf)) { 4488 val = (arg & BCM_HASH_CONTROL_MULTIPATH_DIP) ? 1 : 0; 4489 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4490 ECMP_HASH_USE_DIPf, val); 4491 4492 val = BCM_HASH_CONTROL_MULTIPATH_USERDEF_VAL(arg); 4493 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4494 ECMP_HASH_UDFf, val); 4495 } 4496 4497 if (!SOC_IS_TOMAHAWK3(unit)) { 4498 val = (arg & BCM_HASH_CONTROL_TRUNK_UC_XGS2) ? 1 : 0; 4499 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4500 ENABLE_DRACO1_5_HASHf, val); 4501 4502 val = (arg & BCM_HASH_CONTROL_TRUNK_UC_SRCPORT) ? 1 : 0; 4503 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4504 UC_TRUNK_HASH_USE_SRC_PORTf, val); 4505 } 4506 4507 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_DST) ? 1 : 0; 4508 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4509 NON_UC_TRUNK_HASH_DST_ENABLEf, val); 4510 4511 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_SRC) ? 1 : 0; 4512 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4513 NON_UC_TRUNK_HASH_SRC_ENABLEf, val); 4514 4515 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_MODPORT) ? 1 : 0; 4516 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4517 NON_UC_TRUNK_HASH_MOD_PORT_ENABLEf, val); 4518 4519 #ifdef BCM_BRADLEY_SUPPORT 4520 if (SOC_IS_HB_GW(unit) || (SOC_IS_TRX(unit) && !SOC_IS_HURRICANEX(unit) && 4521 !SOC_IS_GREYHOUND(unit))) { 4522 val = (arg & BCM_HASH_CONTROL_ECMP_ENHANCE) ? 1 : 0; 4523 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4524 ECMP_HASH_USE_RTAG7f, val); 4525 4526 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_ENHANCE) ? 1 : 0; 4527 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4528 NON_UC_TRUNK_HASH_USE_RTAG7f, val); 4529 } 4530 #endif /* BCM_BRADLEY_SUPPORT */ 4531 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 4532 if (soc_feature(unit, soc_feature_riot) || 4533 soc_feature(unit, soc_feature_multi_level_ecmp)) { 4534 val = (arg & BCM_HASH_CONTROL_ECMP_OVERLAY_ENHANCE) ? 1 : 0; 4535 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 4536 ECMP1_HASH_USE_RTAG7f, val); 4537 } 4538 #endif 4539 BCM_IF_ERROR_RETURN(WRITE_HASH_CONTROLr(unit, hash_control)); 4540 4541 return BCM_E_NONE; 4542 } 4543 4544 /* 4545 * Function: 4546 * _bcm_xgs3_hashcontrol_get 4547 * Description: 4548 * Get the current Hash Control settings. 4549 * Parameters: 4550 * unit - StrataSwitch PCI device unit number (driver internal). 4551 * arg - Pointer to where the retrieved value will be written. 4552 * Returns: 4553 * BCM_E_xxxx 4554 */ 4555 4556 STATIC int 4557 _bcm_xgs3_hashcontrol_get(int unit, int *arg) 4558 { 4559 uint32 hash_control, val=0; 4560 4561 *arg = 0; 4562 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 4563 4564 4565 if (soc_feature(unit, soc_feature_l3)) { 4566 if (soc_reg_field_valid(unit, HASH_CONTROLr, USE_TCP_UDP_PORTSf)) { 4567 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4568 USE_TCP_UDP_PORTSf); 4569 if (val) *arg |= BCM_HASH_CONTROL_MULTIPATH_L4PORTS; 4570 } 4571 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_USE_DIPf)) { 4572 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4573 ECMP_HASH_USE_DIPf); 4574 if (val) *arg |= BCM_HASH_CONTROL_MULTIPATH_DIP; 4575 } 4576 4577 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_UDFf)) { 4578 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4579 ECMP_HASH_UDFf); 4580 *arg |= BCM_HASH_CONTROL_MULTIPATH_USERDEF(val); 4581 } 4582 } 4583 4584 if (!SOC_IS_TOMAHAWK3(unit)) { 4585 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4586 ENABLE_DRACO1_5_HASHf); 4587 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_UC_XGS2; 4588 4589 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4590 UC_TRUNK_HASH_USE_SRC_PORTf); 4591 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_UC_SRCPORT; 4592 } 4593 4594 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4595 NON_UC_TRUNK_HASH_DST_ENABLEf); 4596 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_DST; 4597 4598 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4599 NON_UC_TRUNK_HASH_SRC_ENABLEf); 4600 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_SRC; 4601 4602 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4603 NON_UC_TRUNK_HASH_MOD_PORT_ENABLEf); 4604 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_MODPORT; 4605 4606 #ifdef BCM_BRADLEY_SUPPORT 4607 if (SOC_IS_HB_GW(unit) || (SOC_IS_TRX(unit) && !SOC_IS_HURRICANEX(unit) && 4608 !SOC_IS_GREYHOUND(unit))) { 4609 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4610 ECMP_HASH_USE_RTAG7f); 4611 if (val) *arg |= BCM_HASH_CONTROL_ECMP_ENHANCE; 4612 4613 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4614 NON_UC_TRUNK_HASH_USE_RTAG7f); 4615 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_ENHANCE; 4616 } 4617 #endif /* BCM_BRADLEY_SUPPORT */ 4618 4619 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 4620 if (soc_feature(unit, soc_feature_riot) || 4621 soc_feature(unit, soc_feature_multi_level_ecmp)) { 4622 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 4623 ECMP1_HASH_USE_RTAG7f); 4624 4625 if (val) *arg |= BCM_HASH_CONTROL_ECMP_OVERLAY_ENHANCE; 4626 } 4627 #endif 4628 4629 return BCM_E_NONE; 4630 } 4631 4632 #ifdef BCM_TOMAHAWK_SUPPORT 4633 STATIC int 4634 _bcm_th_ecmp_random_hash_seed_set(int unit, bcm_switch_control_t type, 4635 int arg) 4636 { 4637 uint32 rval; 4638 4639 if (arg > 65535 || arg < 1) { 4640 return BCM_E_PARAM; 4641 } 4642 4643 BCM_IF_ERROR_RETURN(READ_ECMP_RANDOM_LB_CONFIGr(unit, &rval)); 4644 4645 switch(type) { 4646 case bcmSwitchECMPLevel1RandomSeed: 4647 soc_reg_field_set(unit, ECMP_RANDOM_LB_CONFIGr, &rval, SEED_1f, 4648 arg); 4649 break; 4650 case bcmSwitchECMPLevel2RandomSeed: 4651 soc_reg_field_set(unit, ECMP_RANDOM_LB_CONFIGr, &rval, SEED_2f, 4652 arg); 4653 break; 4654 default: 4655 return BCM_E_PARAM; 4656 } 4657 4658 SOC_IF_ERROR_RETURN(WRITE_ECMP_RANDOM_LB_CONFIGr(unit, rval)); 4659 4660 return BCM_E_NONE; 4661 } 4662 4663 STATIC int 4664 _bcm_th_ecmp_random_hash_seed_get(int unit, bcm_switch_control_t type, 4665 int *arg) 4666 { 4667 uint32 rval; 4668 4669 BCM_IF_ERROR_RETURN(READ_ECMP_RANDOM_LB_CONFIGr(unit, &rval)); 4670 switch(type) { 4671 case bcmSwitchECMPLevel1RandomSeed: 4672 *arg = soc_reg_field_get(unit, ECMP_RANDOM_LB_CONFIGr, rval, 4673 SEED_1f ); 4674 break; 4675 case bcmSwitchECMPLevel2RandomSeed: 4676 *arg = soc_reg_field_get(unit, ECMP_RANDOM_LB_CONFIGr, rval, 4677 SEED_2f ); 4678 break; 4679 default: 4680 return BCM_E_PARAM; 4681 } 4682 4683 return BCM_E_NONE; 4684 } 4685 #endif /* BCM_TOMAHAWK_SUPPORT */ 4686 4687 4688 #ifdef BCM_TRIUMPH2_SUPPORT 4689 STATIC int 4690 _bcm_tr2_protocol_pkt_index_get(int unit, bcm_port_t port, int *index) 4691 { 4692 port_tab_entry_t entry; 4693 soc_mem_t mem; 4694 int port_index; 4695 4696 #ifdef BCM_HGPROXY_COE_SUPPORT 4697 if (BCM_GPORT_IS_SET(port) && 4698 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port) && 4699 soc_feature(unit, soc_feature_hgproxy_subtag_coe)) { 4700 4701 if (!soc_mem_field_valid(unit, LPORT_TABm, PROTOCOL_PKT_INDEXf)) { 4702 return BCM_E_INTERNAL; 4703 } 4704 4705 port_index = port; 4706 BCM_IF_ERROR_RETURN 4707 (_bcm_esw_port_tab_get(unit, port_index, PROTOCOL_PKT_INDEXf, 4708 index)); 4709 return BCM_E_NONE; 4710 } 4711 #endif 4712 4713 #ifdef BCM_TRIDENT3_SUPPORT 4714 if (SOC_IS_TRIDENT3X(unit)) { 4715 BCM_IF_ERROR_RETURN 4716 (_bcm_esw_port_tab_get(unit, port, PROTOCOL_PKT_INDEXf, index)); 4717 } else 4718 #endif 4719 { 4720 if (!soc_mem_field_valid(unit, PORT_TABm, PROTOCOL_PKT_INDEXf)) { 4721 return BCM_E_INTERNAL; 4722 } 4723 4724 mem = PORT_TABm; 4725 port_index = port; 4726 if (IS_CPU_PORT(unit, port)) { 4727 if (SOC_MEM_IS_VALID(unit, IPORT_TABLEm)) { 4728 mem = IPORT_TABLEm; 4729 } else { 4730 port_index = SOC_IS_KATANA2(unit) ? 4731 SOC_INFO(unit).cpu_hg_pp_port_index : 4732 SOC_INFO(unit).cpu_hg_index; 4733 } 4734 } 4735 BCM_IF_ERROR_RETURN 4736 (soc_mem_read(unit, mem, MEM_BLOCK_ANY, port_index, &entry)); 4737 *index = soc_mem_field32_get(unit, mem, &entry, PROTOCOL_PKT_INDEXf); 4738 } 4739 4740 return BCM_E_NONE; 4741 } 4742 4743 STATIC int 4744 _bcm_tr2_prot_pkt_profile_set(int unit, soc_reg_t reg, bcm_port_t port, 4745 int count, soc_field_t *fields, uint32 *values) 4746 { 4747 int rv = BCM_E_NONE; 4748 soc_mem_t mem; 4749 port_tab_entry_t entry; 4750 int port_index = 0, i; 4751 uint32 prot_pkt_ctrl, igmp_mld_pkt_ctrl, *rval_ptr; 4752 uint32 old_index, index; 4753 4754 if (reg == PROTOCOL_PKT_CONTROLr) { 4755 rval_ptr = &prot_pkt_ctrl; 4756 } else if (reg == IGMP_MLD_PKT_CONTROLr) { 4757 rval_ptr = &igmp_mld_pkt_ctrl; 4758 } else { 4759 return BCM_E_INTERNAL; 4760 } 4761 4762 #ifdef BCM_HGPROXY_COE_SUPPORT 4763 if (BCM_GPORT_IS_SET(port) && 4764 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port) && 4765 soc_feature(unit, soc_feature_hgproxy_subtag_coe)) { 4766 4767 port_index = port; 4768 BCM_IF_ERROR_RETURN 4769 (_bcm_esw_port_tab_get(unit, port_index, PROTOCOL_PKT_INDEXf, 4770 (int*)&old_index)); 4771 4772 BCM_IF_ERROR_RETURN 4773 (_bcm_prot_pkt_ctrl_get(unit, old_index, &prot_pkt_ctrl, 4774 &igmp_mld_pkt_ctrl)); 4775 4776 for (i = 0; i < count; i++) { 4777 soc_reg_field_set(unit, reg, rval_ptr, fields[i], values[i]); 4778 } 4779 BCM_IF_ERROR_RETURN 4780 (_bcm_prot_pkt_ctrl_add(unit, prot_pkt_ctrl, igmp_mld_pkt_ctrl, 4781 &index)); 4782 4783 BCM_IF_ERROR_RETURN(_bcm_prot_pkt_ctrl_delete(unit, old_index)); 4784 4785 return _bcm_esw_port_tab_set(unit, port_index, _BCM_CPU_TABS_NONE, 4786 PROTOCOL_PKT_INDEXf, index); 4787 } 4788 #endif 4789 4790 if (SOC_IS_TRIDENT3X(unit)) { 4791 BCM_IF_ERROR_RETURN 4792 (_bcm_esw_port_tab_get(unit, port, PROTOCOL_PKT_INDEXf, (int *)&old_index)); 4793 } else { 4794 mem = PORT_TABm; 4795 port_index = port; 4796 BCM_IF_ERROR_RETURN 4797 (soc_mem_read(unit, mem, MEM_BLOCK_ANY, port_index, &entry)); 4798 old_index = soc_mem_field32_get(unit, mem, &entry, PROTOCOL_PKT_INDEXf); 4799 } 4800 4801 BCM_IF_ERROR_RETURN 4802 (_bcm_prot_pkt_ctrl_get(unit, old_index, &prot_pkt_ctrl, 4803 &igmp_mld_pkt_ctrl)); 4804 for (i = 0; i < count; i++) { 4805 soc_reg_field_set(unit, reg, rval_ptr, fields[i], values[i]); 4806 } 4807 BCM_IF_ERROR_RETURN 4808 (_bcm_prot_pkt_ctrl_add(unit, prot_pkt_ctrl, igmp_mld_pkt_ctrl, 4809 &index)); 4810 BCM_IF_ERROR_RETURN(_bcm_prot_pkt_ctrl_delete(unit, old_index)); 4811 4812 if (SOC_IS_TRIDENT3X(unit)) { 4813 rv = _bcm_esw_port_tab_set(unit, port, _BCM_CPU_TABS_BOTH, 4814 PROTOCOL_PKT_INDEXf, index); 4815 } else { 4816 BCM_IF_ERROR_RETURN 4817 (soc_mem_field32_modify(unit, PORT_TABm, port_index, 4818 PROTOCOL_PKT_INDEXf, index)); 4819 if (IS_CPU_PORT(unit, port)) { 4820 if (SOC_MEM_IS_VALID(unit, IPORT_TABLEm)) { 4821 mem = IPORT_TABLEm; 4822 } else { 4823 port_index = SOC_IS_KATANA2(unit) ? 4824 SOC_INFO(unit).cpu_hg_pp_port_index : 4825 SOC_INFO(unit).cpu_hg_index; 4826 } 4827 } 4828 BCM_IF_ERROR_RETURN 4829 (soc_mem_field32_modify(unit, PORT_TABm, port_index, 4830 PROTOCOL_PKT_INDEXf, index)); 4831 } 4832 return rv; 4833 } 4834 4835 STATIC int 4836 _bcm_tr2_prot_pkt_action_set(int unit, 4837 bcm_port_t port, 4838 bcm_switch_control_t type, 4839 int arg) 4840 { 4841 soc_field_t field; 4842 uint32 value; 4843 4844 value = arg ? 1 : 0; 4845 4846 switch(type) { 4847 case bcmSwitchArpReplyToCpu: 4848 field = ARP_REPLY_TO_CPUf; 4849 break; 4850 case bcmSwitchArpReplyDrop: 4851 field = ARP_REPLY_DROPf; 4852 break; 4853 case bcmSwitchArpRequestToCpu: 4854 field = ARP_REQUEST_TO_CPUf; 4855 break; 4856 case bcmSwitchArpRequestDrop: 4857 field = ARP_REQUEST_DROPf; 4858 break; 4859 case bcmSwitchNdPktToCpu: 4860 field = ND_PKT_TO_CPUf; 4861 break; 4862 case bcmSwitchNdPktDrop: 4863 field = ND_PKT_DROPf; 4864 break; 4865 case bcmSwitchDhcpPktToCpu: 4866 field = DHCP_PKT_TO_CPUf; 4867 break; 4868 case bcmSwitchDhcpPktDrop: 4869 field = DHCP_PKT_DROPf; 4870 break; 4871 default: 4872 return BCM_E_INTERNAL; 4873 } 4874 4875 return _bcm_tr2_prot_pkt_profile_set(unit, PROTOCOL_PKT_CONTROLr, port, 1, 4876 &field, &value); 4877 } 4878 #endif 4879 4880 /* 4881 * Function: 4882 * _bcm_xgs3_igmp_action_set 4883 * Description: 4884 * Set the IGMP/MLD registers 4885 * Parameters: 4886 * unit - StrataSwitch PCI device unit number (driver internal). 4887 * type - The desired configuration parameter to set. 4888 * arg - IGMP / MLD actions 4889 * Returns: 4890 * BCM_E_xxxx 4891 */ 4892 4893 STATIC int 4894 _bcm_xgs3_igmp_action_set(int unit, 4895 bcm_port_t port, 4896 bcm_switch_control_t type, 4897 int arg) 4898 { 4899 uint32 values[3]; 4900 soc_field_t fields[3]; 4901 int idx; 4902 soc_reg_t reg = INVALIDr ; 4903 int fcount = 1; 4904 int value = (arg) ? 1 : 0; 4905 4906 for (idx = 0; idx < COUNTOF(values); idx++) { 4907 values[idx] = value; 4908 fields[idx] = INVALIDf; 4909 } 4910 #if defined (BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || \ 4911 defined (BCM_TRX_SUPPORT) 4912 if (soc_feature(unit, soc_feature_igmp_mld_support)) { 4913 reg = IGMP_MLD_PKT_CONTROLr; 4914 /* Given control type select register field. */ 4915 switch (type) { 4916 case bcmSwitchIgmpPktToCpu: 4917 fields[0] = IGMP_REP_LEAVE_TO_CPUf; 4918 fields[1] = IGMP_QUERY_TO_CPUf; 4919 fields[2] = IGMP_UNKNOWN_MSG_TO_CPUf; 4920 fcount = 3; 4921 break; 4922 case bcmSwitchIgmpPktDrop: 4923 fields[0] = IGMP_REP_LEAVE_FWD_ACTIONf; 4924 fields[1] = IGMP_QUERY_FWD_ACTIONf; 4925 fields[2] = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 4926 fcount = 3; 4927 values[0] = values[1] = values[2] = 4928 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 4929 break; 4930 case bcmSwitchMldPktToCpu: 4931 fields[0] = MLD_REP_DONE_TO_CPUf; 4932 fields[1] = MLD_QUERY_TO_CPUf; 4933 fcount = 2; 4934 break; 4935 case bcmSwitchMldPktDrop: 4936 fields[0] = MLD_REP_DONE_FWD_ACTIONf; 4937 fields[1] = MLD_QUERY_FWD_ACTIONf; 4938 fcount = 2; 4939 values[0] = 4940 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 4941 break; 4942 case bcmSwitchV4ResvdMcPktToCpu: 4943 fields[0] = IPV4_RESVD_MC_PKT_TO_CPUf; 4944 break; 4945 case bcmSwitchV4ResvdMcPktFlood: 4946 fields[0] = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 4947 values[0] = 4948 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 4949 break; 4950 case bcmSwitchV4ResvdMcPktDrop: 4951 fields[0] = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 4952 values[0] = 4953 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 4954 break; 4955 case bcmSwitchV6ResvdMcPktToCpu: 4956 fields[0] = IPV6_RESVD_MC_PKT_TO_CPUf; 4957 break; 4958 case bcmSwitchV6ResvdMcPktFlood: 4959 fields[0] = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 4960 values[0] = 4961 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 4962 break; 4963 case bcmSwitchV6ResvdMcPktDrop: 4964 fields[0] = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 4965 values[0] = 4966 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 4967 break; 4968 case bcmSwitchIgmpReportLeaveDrop: 4969 fields[0] = IGMP_REP_LEAVE_FWD_ACTIONf; 4970 values[0] = 4971 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 4972 break; 4973 case bcmSwitchIgmpReportLeaveFlood: 4974 fields[0] = IGMP_REP_LEAVE_FWD_ACTIONf; 4975 values[0] = 4976 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 4977 break; 4978 case bcmSwitchIgmpReportLeaveToCpu: 4979 fields[0] = IGMP_REP_LEAVE_TO_CPUf; 4980 break; 4981 case bcmSwitchIgmpQueryDrop: 4982 fields[0] = IGMP_QUERY_FWD_ACTIONf; 4983 values[0] = 4984 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 4985 break; 4986 case bcmSwitchIgmpQueryFlood: 4987 fields[0] = IGMP_QUERY_FWD_ACTIONf; 4988 values[0] = 4989 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 4990 break; 4991 case bcmSwitchIgmpQueryToCpu: 4992 fields[0] = IGMP_QUERY_TO_CPUf; 4993 break; 4994 case bcmSwitchIgmpUnknownDrop: 4995 fields[0] = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 4996 values[0] = 4997 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 4998 break; 4999 case bcmSwitchIgmpUnknownFlood: 5000 fields[0] = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 5001 values[0] = 5002 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 5003 break; 5004 case bcmSwitchIgmpUnknownToCpu: 5005 fields[0] = IGMP_UNKNOWN_MSG_TO_CPUf; 5006 break; 5007 case bcmSwitchMldReportDoneDrop: 5008 fields[0] = MLD_REP_DONE_FWD_ACTIONf; 5009 values[0] = 5010 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 5011 break; 5012 case bcmSwitchMldReportDoneFlood: 5013 fields[0] = MLD_REP_DONE_FWD_ACTIONf; 5014 values[0] = 5015 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 5016 break; 5017 case bcmSwitchMldReportDoneToCpu: 5018 fields[0] = MLD_REP_DONE_TO_CPUf; 5019 break; 5020 case bcmSwitchMldQueryDrop: 5021 fields[0] = MLD_QUERY_FWD_ACTIONf; 5022 values[0] = 5023 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 5024 break; 5025 case bcmSwitchMldQueryFlood: 5026 fields[0] = MLD_QUERY_FWD_ACTIONf; 5027 values[0] = 5028 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 5029 break; 5030 case bcmSwitchMldQueryToCpu: 5031 fields[0] = MLD_QUERY_TO_CPUf; 5032 break; 5033 case bcmSwitchIpmcV4RouterDiscoveryDrop: 5034 fields[0] = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5035 values[0] = 5036 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 5037 break; 5038 case bcmSwitchIpmcV4RouterDiscoveryFlood: 5039 fields[0] = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5040 values[0] = 5041 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 5042 break; 5043 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 5044 fields[0] = IPV4_MC_ROUTER_ADV_PKT_TO_CPUf; 5045 break; 5046 case bcmSwitchIpmcV6RouterDiscoveryDrop: 5047 fields[0] = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5048 values[0] = 5049 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 5050 break; 5051 case bcmSwitchIpmcV6RouterDiscoveryFlood: 5052 fields[0] = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5053 values[0] = 5054 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 5055 break; 5056 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 5057 fields[0] = IPV6_MC_ROUTER_ADV_PKT_TO_CPUf; 5058 break; 5059 default: 5060 return (BCM_E_UNAVAIL); 5061 } 5062 } else 5063 #endif /* BCM_RAPTOR_SUPPORT || BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 5064 if (soc_feature(unit, soc_feature_proto_pkt_ctrl)){ 5065 reg = PROTOCOL_PKT_CONTROLr; 5066 switch (type) { 5067 case bcmSwitchIgmpPktToCpu: 5068 fields[0] = IGMP_PKT_TO_CPUf; 5069 break; 5070 case bcmSwitchIgmpPktDrop: 5071 fields[0] = IGMP_PKT_DROPf; 5072 break; 5073 case bcmSwitchV4ResvdMcPktToCpu: 5074 fields[0] = IPV4_RESVD_MC_PKT_TO_CPUf; 5075 break; 5076 case bcmSwitchV4ResvdMcPktDrop: 5077 fields[0] = IPV4_RESVD_MC_PKT_DROPf; 5078 break; 5079 case bcmSwitchV6ResvdMcPktToCpu: 5080 fields[0] = IPV6_RESVD_MC_PKT_TO_CPUf; 5081 break; 5082 case bcmSwitchV6ResvdMcPktDrop: 5083 fields[0] = IPV6_RESVD_MC_PKT_DROPf; 5084 break; 5085 default: 5086 return (BCM_E_UNAVAIL); 5087 } 5088 } else { 5089 return (BCM_E_UNAVAIL); 5090 } 5091 5092 #ifdef BCM_TRIUMPH2_SUPPORT 5093 if (SOC_REG_INFO(unit, reg).regtype != soc_portreg) { 5094 return _bcm_tr2_prot_pkt_profile_set(unit, reg, port, fcount, fields, 5095 values); 5096 } else 5097 #endif /* BCM_TRIUMPH2_SUPPORT */ 5098 { 5099 return soc_reg_fields32_modify(unit, reg, port, fcount, fields, 5100 values); 5101 } 5102 } 5103 5104 /* 5105 * Function: 5106 * _bcm_xgs3_igmp_action_get 5107 * Description: 5108 * Get the IGMP/MLD registers 5109 * Parameters: 5110 * unit - StrataSwitch PCI device unit number (driver internal). 5111 * type - The desired configuration parameter to set. 5112 * *arg - IGMP / MLD actions 5113 * Returns: 5114 * BCM_E_xxxx 5115 */ 5116 5117 STATIC int 5118 _bcm_xgs3_igmp_action_get(int unit, 5119 bcm_port_t port, 5120 bcm_switch_control_t type, 5121 int *arg) 5122 { 5123 uint32 igmp; 5124 soc_field_t field = INVALIDf; 5125 soc_reg_t reg = INVALIDr; 5126 int act_value = BCM_SWITCH_RESERVED_VALUE; 5127 int hw_value; 5128 5129 #if defined (BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || \ 5130 defined (BCM_TRX_SUPPORT) 5131 if (soc_feature(unit, soc_feature_igmp_mld_support)) { 5132 reg = IGMP_MLD_PKT_CONTROLr; 5133 /* Given control type select register field. */ 5134 switch (type) { 5135 case bcmSwitchIgmpPktToCpu: 5136 field = IGMP_REP_LEAVE_TO_CPUf; 5137 act_value = 1; 5138 break; 5139 case bcmSwitchIgmpPktDrop: 5140 field = IGMP_REP_LEAVE_FWD_ACTIONf; 5141 act_value = BCM_SWITCH_DROP_VALUE; 5142 break; 5143 case bcmSwitchMldPktToCpu: 5144 field = MLD_REP_DONE_TO_CPUf; 5145 act_value = 1; 5146 break; 5147 case bcmSwitchMldPktDrop: 5148 field = MLD_REP_DONE_FWD_ACTIONf; 5149 act_value = BCM_SWITCH_DROP_VALUE; 5150 break; 5151 case bcmSwitchV4ResvdMcPktToCpu: 5152 field = IPV4_RESVD_MC_PKT_TO_CPUf; 5153 act_value = 1; 5154 break; 5155 case bcmSwitchV4ResvdMcPktFlood: 5156 field = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 5157 act_value = BCM_SWITCH_FLOOD_VALUE; 5158 break; 5159 case bcmSwitchV4ResvdMcPktDrop: 5160 field = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 5161 act_value = BCM_SWITCH_DROP_VALUE; 5162 break; 5163 case bcmSwitchV6ResvdMcPktToCpu: 5164 field = IPV6_RESVD_MC_PKT_TO_CPUf; 5165 act_value = 1; 5166 break; 5167 case bcmSwitchV6ResvdMcPktFlood: 5168 field = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 5169 act_value = BCM_SWITCH_FLOOD_VALUE; 5170 break; 5171 case bcmSwitchV6ResvdMcPktDrop: 5172 field = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 5173 act_value = BCM_SWITCH_DROP_VALUE; 5174 break; 5175 case bcmSwitchIgmpReportLeaveDrop: 5176 field = IGMP_REP_LEAVE_FWD_ACTIONf; 5177 act_value = BCM_SWITCH_DROP_VALUE; 5178 break; 5179 case bcmSwitchIgmpReportLeaveFlood: 5180 field = IGMP_REP_LEAVE_FWD_ACTIONf; 5181 act_value = BCM_SWITCH_FLOOD_VALUE; 5182 break; 5183 case bcmSwitchIgmpReportLeaveToCpu: 5184 field = IGMP_REP_LEAVE_TO_CPUf; 5185 act_value = 1; 5186 break; 5187 case bcmSwitchIgmpQueryDrop: 5188 field = IGMP_QUERY_FWD_ACTIONf; 5189 act_value = BCM_SWITCH_DROP_VALUE; 5190 break; 5191 case bcmSwitchIgmpQueryFlood: 5192 field = IGMP_QUERY_FWD_ACTIONf; 5193 act_value = BCM_SWITCH_FLOOD_VALUE; 5194 break; 5195 case bcmSwitchIgmpQueryToCpu: 5196 field = IGMP_QUERY_TO_CPUf; 5197 act_value = 1; 5198 break; 5199 case bcmSwitchIgmpUnknownDrop: 5200 field = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 5201 act_value = BCM_SWITCH_DROP_VALUE; 5202 break; 5203 case bcmSwitchIgmpUnknownFlood: 5204 field = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 5205 act_value = BCM_SWITCH_FLOOD_VALUE; 5206 break; 5207 case bcmSwitchIgmpUnknownToCpu: 5208 field = IGMP_UNKNOWN_MSG_TO_CPUf; 5209 act_value = 1; 5210 break; 5211 case bcmSwitchMldReportDoneDrop: 5212 field = MLD_REP_DONE_FWD_ACTIONf; 5213 act_value = BCM_SWITCH_DROP_VALUE; 5214 break; 5215 case bcmSwitchMldReportDoneFlood: 5216 field = MLD_REP_DONE_FWD_ACTIONf; 5217 act_value = BCM_SWITCH_FLOOD_VALUE; 5218 break; 5219 case bcmSwitchMldReportDoneToCpu: 5220 field = MLD_REP_DONE_TO_CPUf; 5221 act_value = 1; 5222 break; 5223 case bcmSwitchMldQueryDrop: 5224 field = MLD_QUERY_FWD_ACTIONf; 5225 act_value = BCM_SWITCH_DROP_VALUE; 5226 break; 5227 case bcmSwitchMldQueryFlood: 5228 field = MLD_QUERY_FWD_ACTIONf; 5229 act_value = BCM_SWITCH_FLOOD_VALUE; 5230 break; 5231 case bcmSwitchMldQueryToCpu: 5232 field = MLD_QUERY_TO_CPUf; 5233 act_value = 1; 5234 break; 5235 case bcmSwitchIpmcV4RouterDiscoveryDrop: 5236 field = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5237 act_value = BCM_SWITCH_DROP_VALUE; 5238 break; 5239 case bcmSwitchIpmcV4RouterDiscoveryFlood: 5240 field = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5241 act_value = BCM_SWITCH_FLOOD_VALUE; 5242 break; 5243 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 5244 field = IPV4_MC_ROUTER_ADV_PKT_TO_CPUf; 5245 act_value = 1; 5246 break; 5247 case bcmSwitchIpmcV6RouterDiscoveryDrop: 5248 field = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5249 act_value = BCM_SWITCH_DROP_VALUE; 5250 break; 5251 case bcmSwitchIpmcV6RouterDiscoveryFlood: 5252 field = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 5253 act_value = BCM_SWITCH_FLOOD_VALUE; 5254 break; 5255 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 5256 field = IPV6_MC_ROUTER_ADV_PKT_TO_CPUf; 5257 act_value = 1; 5258 break; 5259 default: 5260 return (BCM_E_UNAVAIL); 5261 } 5262 } else 5263 #endif /* BCM_RAPTOR_SUPPORT || BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 5264 if (soc_feature(unit, soc_feature_proto_pkt_ctrl)){ 5265 reg = PROTOCOL_PKT_CONTROLr; 5266 switch (type) { 5267 case bcmSwitchIgmpPktToCpu: 5268 field = IGMP_PKT_TO_CPUf; 5269 act_value = 1; 5270 break; 5271 case bcmSwitchIgmpPktDrop: 5272 field = IGMP_PKT_DROPf; 5273 act_value = 1; 5274 break; 5275 case bcmSwitchV4ResvdMcPktToCpu: 5276 field = IPV4_RESVD_MC_PKT_TO_CPUf; 5277 act_value = 1; 5278 break; 5279 case bcmSwitchV4ResvdMcPktDrop: 5280 field = IPV4_RESVD_MC_PKT_DROPf; 5281 act_value = 1; 5282 break; 5283 case bcmSwitchV6ResvdMcPktToCpu: 5284 field = IPV6_RESVD_MC_PKT_TO_CPUf; 5285 act_value = 1; 5286 break; 5287 case bcmSwitchV6ResvdMcPktDrop: 5288 field = IPV6_RESVD_MC_PKT_DROPf; 5289 act_value = 1; 5290 break; 5291 default: 5292 return (BCM_E_UNAVAIL); 5293 } 5294 } else { 5295 return (BCM_E_UNAVAIL); 5296 } 5297 5298 if (soc_reg_field_valid(unit, reg, field)) { 5299 #if defined (BCM_TRIDENT3_SUPPORT) 5300 if (SOC_IS_TRIDENT3X(unit)) { 5301 int index; 5302 BCM_IF_ERROR_RETURN 5303 (_bcm_tr2_protocol_pkt_index_get(unit, port, &index)); 5304 if(SOC_REG_INFO(unit, reg).regtype == soc_portreg) { 5305 BCM_IF_ERROR_RETURN(soc_reg32_get(unit, reg, (soc_port_t)index, 5306 0, &igmp)); 5307 } else { 5308 BCM_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 5309 index, &igmp)); 5310 } 5311 } else 5312 #endif 5313 #if defined(BCM_TRIUMPH2_SUPPORT) 5314 if (soc_mem_field_valid(unit, PORT_TABm, PROTOCOL_PKT_INDEXf)) { 5315 int index; 5316 5317 BCM_IF_ERROR_RETURN 5318 (_bcm_tr2_protocol_pkt_index_get(unit, port, &index)); 5319 if(SOC_REG_INFO(unit, reg).regtype == soc_portreg) { 5320 BCM_IF_ERROR_RETURN(soc_reg32_get(unit, reg, (soc_port_t)index, 5321 0, &igmp)); 5322 } else { 5323 BCM_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 5324 index, &igmp)); 5325 } 5326 } else 5327 #endif 5328 { 5329 #if defined (BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || \ 5330 defined (BCM_TRX_SUPPORT) 5331 if (IGMP_MLD_PKT_CONTROLr == reg) { 5332 BCM_IF_ERROR_RETURN(READ_IGMP_MLD_PKT_CONTROLr(unit, port, &igmp)); 5333 } else 5334 #endif /* BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT || BCM_FIREBOLT2_SUPPORT */ 5335 { 5336 BCM_IF_ERROR_RETURN(READ_PROTOCOL_PKT_CONTROLr(unit, port, &igmp)); 5337 } 5338 } 5339 hw_value = soc_reg_field_get(unit, reg, igmp, field); 5340 *arg = (act_value == hw_value) ? 1 : 0; 5341 return (BCM_E_NONE); 5342 } 5343 5344 return (BCM_E_UNAVAIL); 5345 } 5346 5347 #if defined(BCM_TRIUMPH2_SUPPORT) 5348 5349 /* 5350 * Function: 5351 * _bcm_tr2_ep_redirect_action_set 5352 * Description: 5353 * Programs action on EP, for EP redirect feature 5354 * Parameters: 5355 * unit - StrataSwitch PCI device unit number (driver internal). 5356 * port - Port number 5357 * type - The desired action to set. 5358 * arg - Action value 5359 * Returns: 5360 * BCM_E_xxxx 5361 */ 5362 STATIC int 5363 _bcm_tr2_ep_redirect_action_set(int unit, 5364 bcm_port_t port, 5365 bcm_switch_control_t type, 5366 int arg) 5367 { 5368 5369 uint32 values[2]; 5370 soc_field_t fields[2]; 5371 int idx; 5372 soc_reg_t reg = INVALIDr ; 5373 int fcount = 1; 5374 int value = (arg) ? 1 : 0; 5375 5376 5377 if (!SOC_IS_TRIUMPH2(unit) && !SOC_IS_APOLLO(unit) && 5378 !SOC_IS_VALKYRIE2(unit) && !SOC_IS_KATANA2(unit) && 5379 !SOC_IS_TRIUMPH3(unit)) { 5380 return BCM_E_UNAVAIL; 5381 } 5382 5383 for (idx = 0; idx < COUNTOF(values); idx++) { 5384 values[idx] = value; 5385 fields[idx] = INVALIDf; 5386 } 5387 5388 reg = EGR_CPU_CONTROLr; 5389 switch (type) { 5390 case bcmSwitchUnknownVlanToCpu: 5391 fields[0] = VLAN_TOCPUf; 5392 break; 5393 case bcmSwitchL3HeaderErrToCpu: 5394 fields[0] = L3ERR_TOCPUf; 5395 break; 5396 case bcmSwitchIpmcTtlErrToCpu: 5397 fields[0] = TTL_DROP_TOCPUf; 5398 break; 5399 case bcmSwitchHgHdrErrToCpu: 5400 fields[0] = HIGIG_TOCPUf; 5401 break; 5402 case bcmSwitchStgInvalidToCpu: 5403 fields[0] = STG_TOCPUf; 5404 break; 5405 case bcmSwitchVlanTranslateEgressMissToCpu: 5406 fields[0] = VXLT_TOCPUf; 5407 break; 5408 case bcmSwitchTunnelErrToCpu: 5409 fields[0] = TUNNEL_TOCPUf; 5410 break; 5411 case bcmSwitchL3PktErrToCpu: 5412 fields[0] = L3PKT_ERR_TOCPUf; 5413 break; 5414 case bcmSwitchMtuFailureToCpu: 5415 fields[0] = MTU_TOCPUf; 5416 break; 5417 case bcmSwitchSrcKnockoutToCpu: 5418 fields[0] = PRUNE_TOCPUf; 5419 break; 5420 case bcmSwitchWlanTunnelMismatchToCpu: 5421 fields[0] = WLAN_MOVE_TOCPUf; 5422 break; 5423 case bcmSwitchWlanTunnelMismatchDrop: 5424 fields[0] = WLAN_MOVE_DROPf; 5425 break; 5426 case bcmSwitchWlanPortMissToCpu: 5427 fields[0] = WLAN_SVP_MISS_TOCPUf; 5428 break; 5429 default: 5430 return(BCM_E_UNAVAIL); 5431 } 5432 5433 for (idx = 0; idx < fcount; idx++) { 5434 if (!SOC_REG_FIELD_VALID(unit, reg, fields[idx])) { 5435 return BCM_E_UNAVAIL; 5436 } 5437 } 5438 5439 return soc_reg_fields32_modify(unit, reg, port, fcount, fields, values); 5440 } 5441 5442 5443 /* 5444 * Function: 5445 * _bcm_tr2_ep_redirect_action_get 5446 * Description: 5447 * Gets action on EP, for EP redirect feature 5448 * Parameters: 5449 * unit - StrataSwitch PCI device unit number (driver internal). 5450 * port - Port number 5451 * type - The desired action to set. 5452 * arg - (OUT) Action value programmed 5453 * Returns: 5454 * BCM_E_xxxx 5455 */ 5456 STATIC int 5457 _bcm_tr2_ep_redirect_action_get(int unit, 5458 bcm_port_t port, 5459 bcm_switch_control_t type, 5460 int *arg) 5461 { 5462 int egr_arg, ing_arg; 5463 uint64 ing_reg_val, egr_reg_val; 5464 uint32 ing_reg, egr_reg, ing_field, egr_field; 5465 5466 5467 if (!SOC_IS_TRIUMPH2(unit) && !SOC_IS_APOLLO(unit) && 5468 !SOC_IS_VALKYRIE2(unit) && !SOC_IS_KATANA2(unit) && 5469 !SOC_IS_TRIUMPH3(unit)) { 5470 return BCM_E_UNAVAIL; 5471 } 5472 5473 ing_reg = INVALIDr; 5474 ing_field = INVALIDf; 5475 egr_reg = EGR_CPU_CONTROLr; 5476 5477 switch (type) { 5478 case bcmSwitchUnknownVlanToCpu: 5479 /* Egress vs ingress comparison necessary only for overwrriten */ 5480 /* switch controls */ 5481 if (SOC_IS_TR_VL(unit)) { 5482 ing_reg = CPU_CONTROL_0r; 5483 } else { 5484 ing_reg = CPU_CONTROL_1r; 5485 } 5486 ing_field = UVLAN_TOCPUf; 5487 egr_field = VLAN_TOCPUf; 5488 break; 5489 case bcmSwitchL3HeaderErrToCpu: 5490 /* Egress vs ingress comparison necessary only for overwrriten */ 5491 /* switch controls */ 5492 ing_reg = CPU_CONTROL_1r; 5493 ing_field = V4L3ERR_TOCPUf; 5494 egr_field = L3ERR_TOCPUf; 5495 break; 5496 case bcmSwitchIpmcTtlErrToCpu: 5497 /* Egress vs ingress comparison necessary only for overwrriten */ 5498 /* switch controls */ 5499 ing_reg = CPU_CONTROL_1r; 5500 ing_field = IPMC_TTL_ERR_TOCPUf; 5501 egr_field = TTL_DROP_TOCPUf; 5502 break; 5503 case bcmSwitchHgHdrErrToCpu: 5504 /* Egress vs ingress comparison necessary only for overwrriten */ 5505 /* switch controls */ 5506 ing_reg = CPU_CONTROL_1r; 5507 ing_field = HG_HDR_ERROR_TOCPUf; 5508 egr_field = HIGIG_TOCPUf; 5509 break; 5510 case bcmSwitchTunnelErrToCpu: 5511 /* Egress vs ingress comparison necessary only for overwrriten */ 5512 /* switch controls */ 5513 ing_reg = CPU_CONTROL_1r; 5514 ing_field = TUNNEL_ERR_TOCPUf; 5515 egr_field = TUNNEL_TOCPUf; 5516 break; 5517 case bcmSwitchStgInvalidToCpu: 5518 egr_field = STG_TOCPUf; 5519 break; 5520 case bcmSwitchVlanTranslateEgressMissToCpu: 5521 egr_field = VXLT_TOCPUf; 5522 break; 5523 case bcmSwitchL3PktErrToCpu: 5524 egr_field = L3PKT_ERR_TOCPUf; 5525 break; 5526 case bcmSwitchMtuFailureToCpu: 5527 egr_field = MTU_TOCPUf; 5528 break; 5529 case bcmSwitchSrcKnockoutToCpu: 5530 egr_field = PRUNE_TOCPUf; 5531 break; 5532 case bcmSwitchWlanTunnelMismatchToCpu: 5533 egr_field = WLAN_MOVE_TOCPUf; 5534 break; 5535 case bcmSwitchWlanTunnelMismatchDrop: 5536 egr_field = WLAN_MOVE_DROPf; 5537 break; 5538 case bcmSwitchWlanPortMissToCpu: 5539 egr_field = WLAN_SVP_MISS_TOCPUf; 5540 break; 5541 5542 default: 5543 return(BCM_E_UNAVAIL); 5544 } 5545 5546 SOC_IF_ERROR_RETURN(soc_reg_get(unit, egr_reg, port, 0, 5547 &egr_reg_val)); 5548 if (!SOC_REG_FIELD_VALID(unit, egr_reg, egr_field)) { 5549 return BCM_E_UNAVAIL; 5550 } 5551 egr_arg = soc_reg64_field32_get(unit, egr_reg, egr_reg_val, 5552 egr_field); 5553 if (ing_reg != INVALIDr) { 5554 SOC_IF_ERROR_RETURN(soc_reg_get(unit, ing_reg, port, 0, 5555 &ing_reg_val)); 5556 if (!SOC_REG_FIELD_VALID(unit, ing_reg, ing_field)) { 5557 return BCM_E_UNAVAIL; 5558 } 5559 ing_arg = soc_reg64_field32_get(unit, ing_reg, ing_reg_val, 5560 ing_field); 5561 if (egr_arg != ing_arg) { 5562 return(BCM_E_CONFIG); 5563 } 5564 } 5565 5566 *arg = egr_arg; 5567 return(BCM_E_NONE); 5568 } 5569 5570 /* 5571 * Function: 5572 * _bcm_tr2_ep_redirect_action_cosq_set 5573 * Description: 5574 * Programs CPU COSQ for EP redirect actions 5575 * Parameters: 5576 * unit - StrataSwitch PCI device unit number (driver internal). 5577 * port - Port number 5578 * type - The desired action to set. 5579 * arg - Action value 5580 * Returns: 5581 * BCM_E_xxxx 5582 */ 5583 STATIC int 5584 _bcm_tr2_ep_redirect_action_cosq_set(int unit, 5585 bcm_port_t port, 5586 bcm_switch_control_t type, 5587 int arg) 5588 { 5589 uint32 values[2]; 5590 soc_field_t fields[2]; 5591 int idx; 5592 soc_reg_t reg = INVALIDr ; 5593 int fcount = 1; 5594 5595 5596 if (!SOC_IS_TRIUMPH2(unit) && !SOC_IS_APOLLO(unit) && 5597 !SOC_IS_VALKYRIE2(unit)) { 5598 return BCM_E_UNAVAIL; 5599 } 5600 5601 if (!soc_feature(unit, soc_feature_internal_loopback)) { 5602 return BCM_E_UNAVAIL; 5603 } 5604 5605 if (arg < 0 || arg > NUM_CPU_COSQ(unit)) { 5606 return BCM_E_PARAM; 5607 } 5608 5609 for (idx = 0; idx < COUNTOF(values); idx++) { 5610 values[idx] = arg; 5611 fields[idx] = INVALIDf; 5612 } 5613 5614 reg = EGR_CPU_COS_CONTROL_1_64r; 5615 switch (type) { 5616 case bcmSwitchUnknownVlanToCpuCosq: 5617 fields[0] = VLAN_CPU_COSf; 5618 break; 5619 case bcmSwitchStgInvalidToCpuCosq: 5620 fields[0] = STG_CPU_COSf; 5621 break; 5622 case bcmSwitchVlanTranslateEgressMissToCpuCosq: 5623 fields[0] = VXLT_CPU_COSf; 5624 break; 5625 case bcmSwitchTunnelErrToCpuCosq: 5626 fields[0] = TUNNEL_CPU_COSf; 5627 break; 5628 case bcmSwitchL3HeaderErrToCpuCosq: 5629 fields[0] = L3ERR_CPU_COSf; 5630 break; 5631 case bcmSwitchL3PktErrToCpuCosq: 5632 fields[0] = L3PKT_ERR_CPU_COSf; 5633 break; 5634 case bcmSwitchIpmcTtlErrToCpuCosq: 5635 fields[0] = TTL_DROP_CPU_COSf; 5636 break; 5637 case bcmSwitchMtuFailureToCpuCosq: 5638 fields[0] = MTU_CPU_COSf; 5639 break; 5640 case bcmSwitchHgHdrErrToCpuCosq: 5641 fields[0] = HIGIG_CPU_COSf; 5642 break; 5643 case bcmSwitchSrcKnockoutToCpuCosq: 5644 fields[0] = PRUNE_CPU_COSf; 5645 break; 5646 case bcmSwitchWlanTunnelMismatchToCpuCosq: 5647 reg = EGR_CPU_COS_CONTROL_2r; 5648 fields[0] = WLAN_MOVE_CPU_COSf; 5649 break; 5650 case bcmSwitchWlanPortMissToCpuCosq: 5651 reg = EGR_CPU_COS_CONTROL_2r; 5652 fields[0] = WLAN_SVP_MISS_CPU_COSf; 5653 break; 5654 default: 5655 return(BCM_E_UNAVAIL); 5656 } 5657 5658 return soc_reg_fields32_modify(unit, reg, port, fcount, fields, values); 5659 } 5660 5661 /* 5662 * Function: 5663 * _bcm_tr2_ep_redirect_action_cosq_get 5664 * Description: 5665 * Gets action on EP, for EP redirect feature 5666 * Parameters: 5667 * unit - StrataSwitch PCI device unit number (driver internal). 5668 * port - Port number 5669 * type - The desired action to set. 5670 * arg - (OUT) Action value programmed 5671 * Returns: 5672 * BCM_E_xxxx 5673 */ 5674 STATIC int 5675 _bcm_tr2_ep_redirect_action_cosq_get(int unit, 5676 bcm_port_t port, 5677 bcm_switch_control_t type, 5678 int *arg) 5679 { 5680 uint64 reg_val; 5681 uint32 reg, field; 5682 5683 5684 if (!SOC_IS_TRIUMPH2(unit) && !SOC_IS_APOLLO(unit) && 5685 !SOC_IS_VALKYRIE2(unit)) { 5686 return BCM_E_UNAVAIL; 5687 } 5688 5689 if (!soc_feature(unit, soc_feature_internal_loopback)) { 5690 return BCM_E_UNAVAIL; 5691 } 5692 5693 reg = EGR_CPU_COS_CONTROL_1_64r; 5694 switch (type) { 5695 case bcmSwitchUnknownVlanToCpuCosq: 5696 field = VLAN_CPU_COSf; 5697 break; 5698 case bcmSwitchStgInvalidToCpuCosq: 5699 field = STG_CPU_COSf; 5700 break; 5701 case bcmSwitchVlanTranslateEgressMissToCpuCosq: 5702 field = VXLT_CPU_COSf; 5703 break; 5704 case bcmSwitchTunnelErrToCpuCosq: 5705 field = TUNNEL_CPU_COSf; 5706 break; 5707 case bcmSwitchL3HeaderErrToCpuCosq: 5708 field = L3ERR_CPU_COSf; 5709 break; 5710 case bcmSwitchL3PktErrToCpuCosq: 5711 field = L3PKT_ERR_CPU_COSf; 5712 break; 5713 case bcmSwitchIpmcTtlErrToCpuCosq: 5714 field = TTL_DROP_CPU_COSf; 5715 break; 5716 case bcmSwitchMtuFailureToCpuCosq: 5717 field = MTU_CPU_COSf; 5718 break; 5719 case bcmSwitchHgHdrErrToCpuCosq: 5720 field = HIGIG_CPU_COSf; 5721 break; 5722 case bcmSwitchSrcKnockoutToCpuCosq: 5723 field = PRUNE_CPU_COSf; 5724 break; 5725 case bcmSwitchWlanTunnelMismatchToCpuCosq: 5726 reg = EGR_CPU_COS_CONTROL_2r; 5727 field = WLAN_MOVE_CPU_COSf; 5728 break; 5729 case bcmSwitchWlanPortMissToCpuCosq: 5730 reg = EGR_CPU_COS_CONTROL_2r; 5731 field = WLAN_SVP_MISS_CPU_COSf; 5732 break; 5733 default: 5734 return(BCM_E_UNAVAIL); 5735 } 5736 5737 SOC_IF_ERROR_RETURN( 5738 soc_reg_get(unit, reg, port, 0, ®_val)); 5739 *arg = soc_reg64_field32_get(unit, reg, reg_val, field); 5740 return(BCM_E_NONE); 5741 } 5742 5743 STATIC int 5744 _bcm_tr2_layered_qos_resolution_set(int unit, 5745 bcm_port_t port, 5746 bcm_switch_control_t type, 5747 int arg) 5748 { 5749 uint64 rval64; 5750 uint32 rval, value; 5751 5752 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || SOC_IS_TRIUMPH3(unit) || 5753 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) || SOC_IS_KATANAX(unit) || 5754 SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit) || 5755 SOC_IS_TD_TT(unit)) { 5756 value = arg ? 0 : 1; /* layered resolution : serial resolution */ 5757 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 5758 if (!SOC_IS_TOMAHAWK3(unit)) { 5759 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 5760 IGNORE_PPD0_PRESERVE_QOSf, value); 5761 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 5762 IGNORE_PPD2_PRESERVE_QOSf, value); 5763 } 5764 if((!SOC_IS_ENDURO(unit)) && (!SOC_IS_HURRICANEX(unit)) && 5765 (!SOC_IS_GREYHOUND(unit)) && (!SOC_IS_TOMAHAWK3(unit))) { 5766 if(SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, 5767 IGNORE_PPD3_PRESERVE_QOSf)){ 5768 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 5769 IGNORE_PPD3_PRESERVE_QOSf, value); 5770 } 5771 } 5772 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, rval64)); 5773 5774 if (SOC_IS_TRIDENT3X(unit) || SOC_IS_TOMAHAWK3(unit)) { 5775 SOC_IF_ERROR_RETURN( 5776 READ_FLEX_EDITOR_HIGIG_HEADER_CONFIGr(unit, &rval)); 5777 soc_reg_field_set(unit, FLEX_EDITOR_HIGIG_HEADER_CONFIGr, &rval, 5778 DISABLE_PPD0_PRESERVE_QOSf, value); 5779 soc_reg_field_set(unit, FLEX_EDITOR_HIGIG_HEADER_CONFIGr, &rval, 5780 DISABLE_PPD2_PRESERVE_QOSf, value); 5781 SOC_IF_ERROR_RETURN( 5782 WRITE_FLEX_EDITOR_HIGIG_HEADER_CONFIGr(unit, rval)); 5783 if(SOC_REG_FIELD_VALID(unit, EGR_CONFIG_1_64r, 5784 DISABLE_PPD3_PRESERVE_QOSf)){ 5785 SOC_IF_ERROR_RETURN( 5786 READ_EGR_CONFIG_1_64r(unit, &rval64)); 5787 soc_reg64_field32_set(unit, EGR_CONFIG_1_64r, &rval64, 5788 DISABLE_PPD3_PRESERVE_QOSf, value); 5789 SOC_IF_ERROR_RETURN( 5790 WRITE_EGR_CONFIG_1_64r(unit, rval64)); 5791 } 5792 } else { 5793 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 5794 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, 5795 DISABLE_PPD0_PRESERVE_QOSf, value); 5796 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, 5797 DISABLE_PPD2_PRESERVE_QOSf, value); 5798 if((!SOC_IS_ENDURO(unit)) && (!SOC_IS_HURRICANEX(unit)) && 5799 (!SOC_IS_GREYHOUND(unit))) { 5800 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, 5801 DISABLE_PPD3_PRESERVE_QOSf, value); 5802 } 5803 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 5804 } 5805 5806 return BCM_E_NONE; 5807 } 5808 5809 return BCM_E_UNAVAIL; 5810 } 5811 5812 STATIC int 5813 _bcm_tr2_layered_qos_resolution_get(int unit, 5814 bcm_port_t port, 5815 bcm_switch_control_t type, 5816 int *arg) 5817 { 5818 uint64 rval64; 5819 5820 if (SOC_IS_TOMAHAWK3(unit)) { 5821 return BCM_E_UNAVAIL; 5822 } 5823 5824 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || SOC_IS_TRIUMPH3(unit) || 5825 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) || SOC_IS_KATANAX(unit) || 5826 SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit) || 5827 SOC_IS_TD_TT(unit)) { 5828 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 5829 *arg = soc_reg64_field32_get(unit, ING_CONFIG_64r, rval64, 5830 IGNORE_PPD0_PRESERVE_QOSf) ? 0 : 1; 5831 return BCM_E_NONE; 5832 } 5833 5834 return BCM_E_UNAVAIL; 5835 } 5836 5837 STATIC int 5838 _bcm_tr2_ehg_error2cpu_set(int unit, bcm_port_t port, int arg) 5839 { 5840 if (soc_feature(unit, soc_feature_embedded_higig) || 5841 soc_feature(unit, soc_feature_higig_over_ethernet)) { 5842 uint32 rval; 5843 soc_field_t ehg_field; 5844 5845 if (!IS_ST_PORT(unit, port)) { 5846 return (BCM_E_CONFIG); 5847 } 5848 5849 if (SOC_REG_FIELD_VALID(unit, CPU_CONTROL_0r, NON_EMBEDDED_HG_TOCPUf)) { 5850 ehg_field = NON_EMBEDDED_HG_TOCPUf; 5851 } else if (SOC_REG_FIELD_VALID(unit, CPU_CONTROL_0r, EHG_NONHG_TOCPUf)) { 5852 ehg_field = EHG_NONHG_TOCPUf; 5853 } else if (SOC_REG_FIELD_VALID(unit, CPU_CONTROL_0r, 5854 EHG_NONHG_TO_CPUf)) { 5855 ehg_field = EHG_NONHG_TO_CPUf; 5856 } else { 5857 return BCM_E_UNAVAIL; 5858 } 5859 BCM_IF_ERROR_RETURN(READ_CPU_CONTROL_0r(unit, &rval)); 5860 soc_reg_field_set(unit, CPU_CONTROL_0r, &rval, 5861 ehg_field, arg ? 1 : 0); 5862 BCM_IF_ERROR_RETURN(WRITE_CPU_CONTROL_0r(unit, rval)); 5863 5864 return (BCM_E_NONE); 5865 } 5866 5867 return (BCM_E_UNAVAIL); 5868 } 5869 5870 STATIC int 5871 _bcm_tr2_ehg_error2cpu_get(int unit, bcm_port_t port, int *arg) 5872 { 5873 if (soc_feature(unit, soc_feature_embedded_higig) || 5874 soc_feature(unit, soc_feature_higig_over_ethernet)) { 5875 uint32 rval; 5876 soc_field_t ehg_field; 5877 5878 if (!IS_ST_PORT(unit, port)) { 5879 return (BCM_E_CONFIG); 5880 } 5881 if (SOC_REG_FIELD_VALID(unit, CPU_CONTROL_0r, NON_EMBEDDED_HG_TOCPUf)) { 5882 ehg_field = NON_EMBEDDED_HG_TOCPUf; 5883 } else if (SOC_REG_FIELD_VALID(unit, CPU_CONTROL_0r, EHG_NONHG_TOCPUf)) { 5884 ehg_field = EHG_NONHG_TOCPUf; 5885 } else if (SOC_REG_FIELD_VALID(unit, CPU_CONTROL_0r, 5886 EHG_NONHG_TO_CPUf)) { 5887 ehg_field = EHG_NONHG_TO_CPUf; 5888 } else { 5889 return BCM_E_UNAVAIL; 5890 } 5891 BCM_IF_ERROR_RETURN(READ_CPU_CONTROL_0r(unit, &rval)); 5892 *arg = soc_reg_field_get(unit, CPU_CONTROL_0r, rval, ehg_field); 5893 5894 return (BCM_E_NONE); 5895 } 5896 5897 return (BCM_E_UNAVAIL); 5898 } 5899 5900 STATIC int 5901 _bcm_tr2_mirror_egress_true_set(int unit, bcm_port_t port, 5902 bcm_switch_control_t type, int arg) 5903 { 5904 uint32 values[2]; 5905 soc_field_t fields[2]; 5906 5907 if (soc_feature(unit, soc_feature_egr_mirror_true)) { 5908 if (type == bcmSwitchMirrorEgressTrueColorSelect) { 5909 fields[0] = REDIRECT_DROP_PRECEDENCEf; 5910 switch (arg) { 5911 case bcmColorGreen: 5912 values[0] = 1; 5913 break; 5914 case bcmColorYellow: 5915 values[0] = 2; 5916 break; 5917 case bcmColorRed: 5918 values[0] = 3; 5919 break; 5920 default: 5921 values[0] = 0; /* No change */ 5922 break; 5923 } 5924 return soc_reg_fields32_modify(unit, EGR_PORT_64r, port, 1, 5925 fields, values); 5926 } else if (type == bcmSwitchMirrorEgressTruePriority) { 5927 fields[0] = REDIRECT_INT_PRI_SELf; 5928 fields[1] = REDIRECT_INT_PRIf; 5929 if ((arg < 0) || (arg > 0xf)) { 5930 values[0] = 0; 5931 values[1] = 0; 5932 } else { 5933 values[0] = 1; 5934 values[1] = arg & 0xf; 5935 } 5936 return soc_reg_fields32_modify(unit, EGR_PORT_64r, port, 2, 5937 fields, values); 5938 } 5939 } 5940 return (BCM_E_UNAVAIL); 5941 } 5942 5943 STATIC int 5944 _bcm_tr2_mirror_egress_true_get(int unit, bcm_port_t port, 5945 bcm_switch_control_t type, int *arg) 5946 { 5947 uint64 rval64; 5948 5949 if (soc_feature(unit, soc_feature_egr_mirror_true)) { 5950 BCM_IF_ERROR_RETURN(READ_EGR_PORT_64r(unit, port, &rval64)); 5951 if (type == bcmSwitchMirrorEgressTrueColorSelect) { 5952 switch (soc_reg64_field32_get(unit, EGR_PORT_64r, rval64, 5953 REDIRECT_DROP_PRECEDENCEf)) { 5954 case 1: 5955 *arg = bcmColorGreen; 5956 break; 5957 case 2: 5958 *arg = bcmColorYellow; 5959 break; 5960 case 3: 5961 *arg = bcmColorRed; 5962 break; 5963 case 0: 5964 default: 5965 *arg = -1; /* No change */ 5966 break; 5967 } 5968 return BCM_E_NONE; 5969 } else if (type == bcmSwitchMirrorEgressTruePriority) { 5970 if (soc_reg64_field32_get(unit, EGR_PORT_64r, rval64, 5971 REDIRECT_INT_PRI_SELf)) { 5972 *arg = soc_reg64_field32_get(unit, EGR_PORT_64r, rval64, 5973 REDIRECT_INT_PRIf); 5974 } else { 5975 *arg = -1; 5976 } 5977 return BCM_E_NONE; 5978 } 5979 } 5980 return (BCM_E_UNAVAIL); 5981 } 5982 #endif /* BCM_TRIUMPH2_SUPPORT */ 5983 #if defined(BCM_OLP_SUPPORT) 5984 STATIC int 5985 _bcm_switch_xgs_mac_get(int unit, bcm_switch_control_t type, int *value) 5986 { 5987 uint32 val_lo, val_hi; 5988 uint64 rval; 5989 uint64 mac_field; 5990 5991 COMPILER_64_ZERO(rval); 5992 SOC_IF_ERROR_RETURN(READ_IARB_OLP_CONFIGr(unit, &rval)); 5993 5994 mac_field = soc_reg64_field_get(unit, IARB_OLP_CONFIGr, rval, MACDAf); 5995 5996 COMPILER_64_TO_32_LO(val_lo, mac_field); 5997 COMPILER_64_TO_32_HI(val_hi, mac_field); 5998 5999 switch (type) { 6000 case bcmSwitchOamOlpStationMacOui: 6001 6002 *value = 0xffffff & ((val_hi << 8) | ((val_lo >> 24) & 0xff)); 6003 break; 6004 6005 case bcmSwitchOamOlpStationMacNonOui: 6006 6007 *value = (val_lo & 0xffffff); 6008 break; 6009 default: 6010 LOG_ERROR(BSL_LS_BCM_COMMON, 6011 (BSL_META_U(unit, 6012 "Not supported switch control\n"))); 6013 return BCM_E_PARAM; 6014 break; 6015 } 6016 return BCM_E_NONE; 6017 } 6018 6019 STATIC int 6020 _bcm_switch_xgs_mac_set(int unit, bcm_switch_control_t type, int value) 6021 { 6022 egr_olp_config_entry_t eolp_cfg; 6023 uint64 iarb_olp_cfg; 6024 uint64 mac_field; 6025 uint32 val_lo, val_hi; 6026 uint64 mask_field; 6027 int set; 6028 bcm_port_t port; 6029 bcm_pbmp_t ports; 6030 int olp_port; 6031 bcm_mac_t xgs_mac; 6032 int index=0; 6033 /* Set MAC address in IARB_OLP_CONFIG */ 6034 6035 COMPILER_64_ZERO(iarb_olp_cfg); 6036 SOC_IF_ERROR_RETURN(READ_IARB_OLP_CONFIGr(unit, &iarb_olp_cfg)); 6037 6038 mac_field = soc_reg64_field_get(unit, IARB_OLP_CONFIGr, iarb_olp_cfg, MACDAf); 6039 6040 COMPILER_64_TO_32_LO(val_lo, mac_field); 6041 COMPILER_64_TO_32_HI(val_hi, mac_field); 6042 6043 switch (type) { 6044 case bcmSwitchOamOlpStationMacOui: 6045 6046 val_lo = (val_lo & 0xffffff) | ((value & 0xff) << 24); 6047 val_hi = (value >> 8) & 0xffff; 6048 COMPILER_64_SET(mac_field, val_hi, val_lo); 6049 break; 6050 6051 case bcmSwitchOamOlpStationMacNonOui: 6052 6053 val_lo = (val_lo & 0xff000000) | (value & 0xffffff); 6054 COMPILER_64_SET(mac_field, val_hi, val_lo); 6055 break; 6056 default: 6057 LOG_ERROR(BSL_LS_BCM_COMMON, 6058 (BSL_META_U(unit, 6059 "Not supported switch control\n"))); 6060 return BCM_E_PARAM; 6061 break; 6062 } 6063 6064 soc_reg64_field_set(unit, IARB_OLP_CONFIGr, &iarb_olp_cfg, MACDAf, mac_field); 6065 6066 SOC_IF_ERROR_RETURN(WRITE_IARB_OLP_CONFIGr(unit, iarb_olp_cfg)); 6067 6068 SAL_MAC_ADDR_FROM_UINT64(xgs_mac, mac_field); 6069 6070 /* Set MAC address in EGR_OLP_CONFIG */ 6071 #if defined (BCM_APACHE_SUPPORT) 6072 if (soc_feature(unit, soc_feature_ep_redirect_v2) || SOC_IS_MONTEREY(unit)) { 6073 SOC_IF_ERROR_RETURN( 6074 READ_EGR_OLP_CONFIG_1m(unit, MEM_BLOCK_ANY, index, &eolp_cfg)); 6075 6076 soc_mem_mac_addr_set(unit, EGR_OLP_CONFIG_1m, &eolp_cfg, 6077 MACSAf, xgs_mac); 6078 SOC_IF_ERROR_RETURN( 6079 WRITE_EGR_OLP_CONFIG_1m(unit, MEM_BLOCK_ALL, 6080 index, &eolp_cfg)); 6081 SOC_IF_ERROR_RETURN( 6082 WRITE_EGR_OLP_CONFIG_2m(unit, MEM_BLOCK_ALL, 6083 index, &eolp_cfg)); 6084 } else 6085 #endif 6086 { 6087 SOC_IF_ERROR_RETURN( 6088 READ_EGR_OLP_CONFIGm(unit, MEM_BLOCK_ANY, index, &eolp_cfg)); 6089 6090 soc_mem_mac_addr_set(unit, EGR_OLP_CONFIGm, &eolp_cfg, 6091 MACSAf, xgs_mac); 6092 SOC_IF_ERROR_RETURN( 6093 WRITE_EGR_OLP_CONFIGm(unit, MEM_BLOCK_ALL, 6094 index, &eolp_cfg)); 6095 } 6096 6097 /* Set mask and data values in ING_OLP_CONFIG_ register */ 6098 if (COMPILER_64_IS_ZERO(mac_field)) { 6099 set = FALSE; 6100 COMPILER_64_SET(mask_field, 0x0, 0x0); 6101 } else { 6102 set = TRUE; 6103 COMPILER_64_SET(mask_field, 0XFFFF, 0xFFFFFFFF); 6104 } 6105 6106 SOC_IF_ERROR_RETURN(WRITE_ING_OLP_CONFIG_0_64r(unit, mac_field)); 6107 SOC_IF_ERROR_RETURN(WRITE_ING_OLP_CONFIG_1_64r(unit, mask_field)); 6108 6109 /* Enable/Disable the OLP MACDA prefix checking for front panel ports */ 6110 BCM_PBMP_ASSIGN(ports, PBMP_PORT_ALL(unit)); 6111 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 6112 if(SOC_IS_TD2P_TT2P(unit) || SOC_IS_APACHE(unit)) { 6113 port_tab_entry_t port_entry; 6114 iarb_ing_port_table_entry_t iarb_ing_port_entry; 6115 6116 PBMP_ITER(ports, port) { 6117 SOC_IF_ERROR_RETURN(soc_mem_read(unit, PORT_TABm, 6118 MEM_BLOCK_ANY, port, &port_entry)); 6119 6120 SOC_IF_ERROR_RETURN(soc_mem_read(unit, IARB_ING_PORT_TABLEm, 6121 MEM_BLOCK_ANY, port, &iarb_ing_port_entry)); 6122 if (soc_IARB_ING_PORT_TABLEm_field32_get(unit, &iarb_ing_port_entry, 6123 OLP_ENABLEf)) { 6124 olp_port = TRUE; 6125 } else { 6126 olp_port = FALSE; 6127 } 6128 6129 if (!IS_HG_PORT(unit, port) && (TRUE == set) && (FALSE == olp_port)) { 6130 soc_PORT_TABm_field32_set(unit, &port_entry, 6131 OLP_MAC_DA_PREFIX_CHECK_ENABLEf, 1); 6132 } else { 6133 soc_PORT_TABm_field32_set(unit, &port_entry, 6134 OLP_MAC_DA_PREFIX_CHECK_ENABLEf, 0); 6135 } 6136 SOC_IF_ERROR_RETURN(soc_mem_write(unit, PORT_TABm, 6137 MEM_BLOCK_ALL, port, &port_entry)); 6138 } 6139 } else 6140 #endif 6141 { 6142 ing_physical_port_table_entry_t port_entry; 6143 iarb_ing_physical_port_entry_t iarb_entry; 6144 6145 PBMP_ITER(ports, port) { 6146 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ING_PHYSICAL_PORT_TABLEm, 6147 MEM_BLOCK_ANY, port, &port_entry)); 6148 6149 SOC_IF_ERROR_RETURN(soc_mem_read(unit, IARB_ING_PHYSICAL_PORTm, 6150 MEM_BLOCK_ANY, port, &iarb_entry)); 6151 6152 if (soc_IARB_ING_PHYSICAL_PORTm_field32_get(unit, &iarb_entry, 6153 OLP_ENABLEf)) { 6154 olp_port = TRUE; 6155 } else { 6156 olp_port = FALSE; 6157 } 6158 if (!IS_HG_PORT(unit, port) && (TRUE == set) && (FALSE == olp_port)) { 6159 soc_ING_PHYSICAL_PORT_TABLEm_field32_set(unit, &port_entry, 6160 OLP_MAC_DA_PREFIX_CHECK_ENABLEf, 1); 6161 } else { 6162 soc_ING_PHYSICAL_PORT_TABLEm_field32_set(unit, &port_entry, 6163 OLP_MAC_DA_PREFIX_CHECK_ENABLEf, 0); 6164 } 6165 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_PHYSICAL_PORT_TABLEm, 6166 MEM_BLOCK_ALL, port, &port_entry)); 6167 } 6168 } 6169 return BCM_E_NONE; 6170 } 6171 #endif /* BCM_OLP_SUPPORT */ 6172 6173 #ifdef BCM_TRIDENT_SUPPORT 6174 /* 6175 * Function: 6176 * _bcm_td_mirror_uc_cos_set 6177 * Description: 6178 * Sets the COS for unicast mirror traffic 6179 * Parameters: 6180 * unit - StrataSwitch unit number. 6181 * cosq - COSQ value. 6182 * Returns: 6183 * BCM_E_xxxx 6184 */ 6185 6186 #define COSQ_DISABLE -1 6187 6188 STATIC int 6189 _bcm_td_mirror_uc_cos_set(int unit, int cosq) 6190 { 6191 int rv = BCM_E_UNAVAIL; 6192 int limit; 6193 int enable = FALSE; 6194 uint64 rval; 6195 soc_reg_t reg = ING_MIRROR_COS_CONTROLr; 6196 6197 limit = (1<<soc_reg_field_length(unit, reg, MIRR_COSf)); 6198 6199 if (cosq == COSQ_DISABLE) { 6200 /* disable */ 6201 enable = FALSE; 6202 cosq = 0; 6203 rv = BCM_E_NONE; 6204 } else if (cosq >= 0 && cosq < limit) { 6205 /* enable */ 6206 enable = TRUE; 6207 rv = BCM_E_NONE; 6208 } else { 6209 /* cosq out of range */ 6210 rv = BCM_E_PARAM; 6211 } 6212 6213 if (BCM_SUCCESS(rv)) { 6214 COMPILER_64_ZERO(rval); 6215 soc_reg64_field32_set(unit, reg, &rval, MIRR_COSf, cosq); 6216 soc_reg64_field32_set(unit, reg, &rval, ENABLEf, enable); 6217 rv = WRITE_ING_MIRROR_COS_CONTROLr(unit, rval); 6218 } 6219 6220 return rv; 6221 } 6222 6223 /* 6224 * Function: 6225 * _bcm_td_mirror_uc_cos_get 6226 * Description: 6227 * Sets the COS for unicast mirror traffic 6228 * Parameters: 6229 * unit - StrataSwitch unit number. 6230 * cosq - pointer to COSQ value. 6231 * Returns: 6232 * BCM_E_xxxx 6233 */ 6234 STATIC int 6235 _bcm_td_mirror_uc_cos_get(int unit, int *cosq) 6236 { 6237 uint64 rval; 6238 int rv; 6239 soc_reg_t reg = ING_MIRROR_COS_CONTROLr; 6240 6241 if (cosq != NULL) { 6242 rv = READ_ING_MIRROR_COS_CONTROLr(unit, &rval); 6243 6244 if (SOC_SUCCESS(rv)) { 6245 if (soc_reg64_field32_get(unit, reg, rval, ENABLEf)) { 6246 *cosq = (int)soc_reg64_field32_get(unit, reg, rval, MIRR_COSf); 6247 } else { 6248 *cosq = COSQ_DISABLE; 6249 } 6250 } 6251 } else { 6252 rv = BCM_E_PARAM; 6253 } 6254 6255 return rv; 6256 } 6257 6258 /* 6259 * Function: 6260 * _bcm_td_mirror_mc_cos_set 6261 * Description: 6262 * Sets the COS for multicast mirror traffic 6263 * Parameters: 6264 * unit - StrataSwitch unit number. 6265 * cosq - COSQ value. 6266 * Returns: 6267 * BCM_E_xxxx 6268 */ 6269 STATIC int 6270 _bcm_td_mirror_mc_cos_set(int unit, int cosq) 6271 { 6272 int rv = BCM_E_NONE; 6273 int limit; 6274 int enable = FALSE; 6275 uint32 rval; 6276 soc_reg_t reg = MTP_COSr; 6277 soc_field_t v = VALUEf; 6278 soc_field_t e = ENABLEf; 6279 6280 #if defined(BCM_TOMAHAWK3_SUPPORT) 6281 if (SOC_IS_TOMAHAWK3(unit)) { 6282 reg = MMU_MTP_COSr; 6283 v = MTP_COSf; 6284 } 6285 #endif 6286 6287 /* register field names are slightly different */ 6288 if (!soc_reg_field_valid(unit, reg, v)) { 6289 /* Try TRIUMPH3-like fields */ 6290 v = MTP_COSf; 6291 e = MTP_COS_ENABLEf; 6292 if (!soc_reg_field_valid(unit, reg, v)) { 6293 rv = BCM_E_UNAVAIL; 6294 } 6295 } 6296 6297 if (BCM_SUCCESS(rv)) { 6298 limit = (1<<soc_reg_field_length(unit, reg, v)); 6299 6300 if (cosq == COSQ_DISABLE) { 6301 /* disable */ 6302 enable = FALSE; 6303 cosq = 0; 6304 rv = BCM_E_NONE; 6305 } else if (cosq >= 0 && cosq < limit) { 6306 /* enable */ 6307 enable = TRUE; 6308 rv = BCM_E_NONE; 6309 } else { 6310 /* cosq out of range */ 6311 rv = BCM_E_PARAM; 6312 } 6313 6314 if (BCM_SUCCESS(rv)) { 6315 rval = 0; 6316 soc_reg_field_set(unit, reg, &rval, v, cosq); 6317 soc_reg_field_set(unit, reg, &rval, e, enable); 6318 rv = soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval); 6319 } 6320 } 6321 6322 return rv; 6323 } 6324 6325 6326 /* 6327 * Function: 6328 * _bcm_td_mirror_mc_cos_get 6329 * Description: 6330 * Sets the COS for multicast mirror traffic 6331 * Parameters: 6332 * unit - StrataSwitch unit number. 6333 * cosq - pointer to COSQ value. 6334 * Returns: 6335 * BCM_E_xxxx 6336 */ 6337 6338 STATIC int 6339 _bcm_td_mirror_mc_cos_get(int unit, int *cosq) 6340 { 6341 uint32 rval; 6342 int rv = BCM_E_NONE; 6343 soc_reg_t reg = MTP_COSr; 6344 soc_field_t v = VALUEf; 6345 soc_field_t e = ENABLEf; 6346 6347 #if defined(BCM_TOMAHAWK3_SUPPORT) 6348 if (SOC_IS_TOMAHAWK3(unit)) { 6349 reg = MMU_MTP_COSr; 6350 v = MTP_COSf; 6351 } 6352 #endif 6353 if (cosq != NULL) { 6354 /* register field names are slightly different */ 6355 if (!soc_reg_field_valid(unit, reg, v)) { 6356 /* Try TRIUMPH3-like fields */ 6357 v = MTP_COSf; 6358 e = MTP_COS_ENABLEf; 6359 if (!soc_reg_field_valid(unit, reg, v)) { 6360 rv = BCM_E_UNAVAIL; 6361 } 6362 } 6363 6364 if (BCM_SUCCESS(rv)) { 6365 /* have reasonable register fields */ 6366 rv = soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval); 6367 6368 if (SOC_SUCCESS(rv)) { 6369 if (soc_reg_field_get(unit, reg, rval, e)) { 6370 *cosq = (int)soc_reg_field_get(unit, reg, rval, v); 6371 } else { 6372 *cosq = COSQ_DISABLE; 6373 } 6374 } 6375 } 6376 } else { 6377 rv = BCM_E_PARAM; 6378 } 6379 6380 return rv; 6381 } 6382 6383 #ifdef BCM_TOMAHAWK3_SUPPORT 6384 /* 6385 * Function: 6386 * _bcm_th3_mirror_cpu_cos_set 6387 * Description: 6388 * This function sets COS for mirrored traffic destined for CPU port 6389 * Parameters: 6390 * unit - StrataSwitch unit number. 6391 * cosq - COSQ value (0-47). 6392 * Returns: 6393 * BCM_E_xxxx 6394 */ 6395 STATIC int 6396 _bcm_th3_mirror_cpu_cos_set(int unit, int cosq) 6397 { 6398 int rv = BCM_E_NONE; 6399 int enable = FALSE; 6400 uint32 rval; 6401 soc_reg_t reg = MMU_MTP_CPU_COSr; 6402 soc_field_t v = MTP_CPU_COSf; 6403 soc_field_t e = ENABLEf; 6404 6405 /* Validity of a register (SOC_REG_IS_VALID) is checked under 6406 * soc_reg_field_valid 6407 */ 6408 if (!soc_reg_field_valid(unit, reg, v) || 6409 !soc_reg_field_valid(unit, reg, e)) { 6410 return BCM_E_UNAVAIL; 6411 } 6412 6413 if (cosq == COSQ_DISABLE) { 6414 /* disable */ 6415 enable = FALSE; 6416 cosq = 0; 6417 } else if (cosq >= 0 && cosq < SOC_TH3_NUM_CPU_QUEUES) { 6418 /* Cos q number ranges from 0-47 */ 6419 /* enable */ 6420 enable = TRUE; 6421 } else { 6422 /* cosq out of range */ 6423 rv = BCM_E_PARAM; 6424 } 6425 6426 if (BCM_SUCCESS(rv)) { 6427 rval = 0; 6428 soc_reg_field_set(unit, reg, &rval, v, cosq); 6429 soc_reg_field_set(unit, reg, &rval, e, enable); 6430 rv = soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval); 6431 } 6432 6433 return rv; 6434 } 6435 6436 /* 6437 * Function: 6438 * _bcm_th3_mirror_cpu_cos_get 6439 * Description: 6440 * This function reads COS for mirror traffic destined for CPU port 6441 * Parameters: 6442 * unit - StrataSwitch unit number. 6443 * cosq - pointer to COSQ value. 6444 * Returns: 6445 * BCM_E_xxxx 6446 */ 6447 6448 STATIC int 6449 _bcm_th3_mirror_cpu_cos_get(int unit, int *cosq) 6450 { 6451 uint32 rval; 6452 int rv = BCM_E_NONE; 6453 soc_reg_t reg = MMU_MTP_CPU_COSr; 6454 soc_field_t v = MTP_CPU_COSf; 6455 soc_field_t e = ENABLEf; 6456 6457 /* Validity of a register (SOC_REG_IS_VALID) is checked under 6458 * soc_reg_field_valid 6459 */ 6460 if (!soc_reg_field_valid(unit, reg, v) || 6461 !soc_reg_field_valid(unit, reg, e)) { 6462 return BCM_E_UNAVAIL; 6463 } 6464 6465 if (cosq != NULL) { 6466 rv = soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval); 6467 6468 if (SOC_SUCCESS(rv)) { 6469 if (soc_reg_field_get(unit, reg, rval, e)) { 6470 *cosq = (int)soc_reg_field_get(unit, reg, rval, v); 6471 } else { 6472 *cosq = COSQ_DISABLE; 6473 } 6474 } 6475 } else { 6476 rv = BCM_E_PARAM; 6477 } 6478 6479 return rv; 6480 } 6481 #endif /* BCM_TOMAHAWK3_SUPPORT */ 6482 #endif /* BCM_TRIDENT_SUPPORT */ 6483 6484 #if defined(BCM_HAWKEYE_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) 6485 /* 6486 * Function: 6487 * _bcm_xgs3_switch_ethertype_set 6488 * Description: 6489 * Set the ethertype field for MMRP, and SRP registers 6490 * Parameters: 6491 * unit - StrataSwitch PCI device unit number (driver internal). 6492 * port - port number. 6493 * type - The required switch control to set the ethertype for 6494 * arg - argument to set as Ethrtype 6495 * Returns: 6496 * BCM_E_xxxx 6497 */ 6498 6499 STATIC int 6500 _bcm_xgs3_switch_ethertype_set(int unit, bcm_port_t port, 6501 bcm_switch_control_t type, 6502 int arg) 6503 { 6504 soc_reg_t reg = INVALIDr ; 6505 uint16 ethertype; 6506 6507 if (!soc_feature(unit, soc_feature_timesync_support)) { 6508 return BCM_E_UNAVAIL; 6509 } 6510 ethertype = (uint16)arg; 6511 6512 /* Given control type select register. */ 6513 switch (type) { 6514 case bcmSwitchMMRPEthertype: 6515 reg = MMRP_CONTROL_2r; 6516 break; 6517 case bcmSwitchTimeSyncEthertype: 6518 reg = TS_CONTROLr; 6519 break; 6520 case bcmSwitchSRPEthertype: 6521 reg = SRP_CONTROL_2r; 6522 break; 6523 default: 6524 return BCM_E_PARAM; 6525 } 6526 6527 if (!SOC_REG_FIELD_VALID(unit, reg, ETHERTYPEf)) { 6528 return BCM_E_UNAVAIL; 6529 } 6530 6531 return soc_reg_field32_modify(unit, reg, port, ETHERTYPEf, ethertype); 6532 } 6533 6534 /* 6535 * Function: 6536 * _bcm_xgs3_switch_ethertype_get 6537 * Description: 6538 * Get the ethertype field for MMRP, and SRP registers 6539 * Parameters: 6540 * unit - StrataSwitch PCI device unit number (driver internal). 6541 * port - port number. 6542 * type - The required switch control to get the ethertype for 6543 * arg - Ethrtype to get 6544 * Returns: 6545 * BCM_E_xxxx 6546 */ 6547 6548 STATIC int 6549 _bcm_xgs3_switch_ethertype_get(int unit, bcm_port_t port, 6550 bcm_switch_control_t type, 6551 int *arg) 6552 { 6553 soc_reg_t reg = INVALIDr ; 6554 uint16 ethertype; 6555 uint32 regval; 6556 6557 if (!soc_feature(unit, soc_feature_timesync_support)) { 6558 return BCM_E_UNAVAIL; 6559 } 6560 6561 /* Given control type select register. */ 6562 switch (type) { 6563 case bcmSwitchMMRPEthertype: 6564 reg = MMRP_CONTROL_2r; 6565 break; 6566 case bcmSwitchTimeSyncEthertype: 6567 reg = TS_CONTROLr; 6568 break; 6569 case bcmSwitchSRPEthertype: 6570 reg = SRP_CONTROL_2r; 6571 break; 6572 default: 6573 return BCM_E_PARAM; 6574 } 6575 6576 if (!soc_reg_field_valid(unit, reg, ETHERTYPEf)) { 6577 return BCM_E_UNAVAIL; 6578 } 6579 SOC_IF_ERROR_RETURN( 6580 soc_reg32_get(unit, reg, REG_PORT_ANY, 0, ®val)); 6581 ethertype = soc_reg_field_get(unit, reg, regval, ETHERTYPEf); 6582 6583 *arg = (int)ethertype; 6584 6585 return BCM_E_NONE; 6586 } 6587 /* 6588 * Function: 6589 * _bcm_xgs3_switch_mac_lo_set 6590 * Description: 6591 * Set the low 24 bits of MAC address field for MMRP, and SRP registers 6592 * Parameters: 6593 * unit - StrataSwitch PCI device unit number (driver internal). 6594 * port - port number. 6595 * type - The required switch control type to set the mac for 6596 * mac_lo - MAC address 6597 * Returns: 6598 * BCM_E_xxxx 6599 */ 6600 6601 STATIC int 6602 _bcm_xgs3_switch_mac_lo_set(int unit, bcm_port_t port, 6603 bcm_switch_control_t type, 6604 uint32 mac_lo) 6605 { 6606 uint32 regval, fieldval; 6607 soc_reg_t reg = INVALIDr ; 6608 soc_field_t f_lo = INVALIDf; 6609 6610 6611 if (!soc_feature(unit, soc_feature_timesync_support)) { 6612 return BCM_E_UNAVAIL; 6613 } 6614 6615 /* Given control type select register. */ 6616 switch (type) { 6617 case bcmSwitchMMRPDestMacNonOui: 6618 reg = MMRP_CONTROL_1r; 6619 f_lo = MAC_DA_LOWERf; 6620 break; 6621 case bcmSwitchTimeSyncDestMacNonOui: 6622 reg = TS_CONTROL_1r; 6623 f_lo = MAC_DA_LOWERf; 6624 break; 6625 case bcmSwitchSRPDestMacNonOui: 6626 reg = SRP_CONTROL_1r; 6627 f_lo = MAC_DA_LOWERf; 6628 break; 6629 default: 6630 return BCM_E_PARAM; 6631 } 6632 6633 if (!soc_reg_field_valid(unit, reg, f_lo)) { 6634 return BCM_E_UNAVAIL; 6635 } 6636 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, ®val)); 6637 fieldval = soc_reg_field_get(unit, reg, regval, f_lo); 6638 fieldval |= ((mac_lo << 8) >> 8); 6639 soc_reg_field_set(unit, reg, ®val, f_lo, fieldval); 6640 6641 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, REG_PORT_ANY, 0, regval)); 6642 return BCM_E_NONE; 6643 } 6644 6645 /* 6646 * Function: 6647 * _bcm_xgs3_switch_mac_hi_set 6648 * Description: 6649 * Set the upper 24 bits of MAC address field for MMRP, and SRP registers 6650 * Parameters: 6651 * unit - StrataSwitch PCI device unit number (driver internal). 6652 * port - port number. 6653 * type - The required switch control type to set upper MAC for 6654 * mac_hi - MAC address 6655 * Returns: 6656 * BCM_E_xxxx 6657 */ 6658 6659 STATIC int 6660 _bcm_xgs3_switch_mac_hi_set(int unit, bcm_port_t port, 6661 bcm_switch_control_t type, 6662 uint32 mac_hi) 6663 { 6664 soc_reg_t reg1, reg2; 6665 soc_field_t f_lo, f_hi; 6666 uint32 fieldval, regval1, regval2; 6667 6668 reg1 = reg2 = INVALIDr; 6669 6670 if (!soc_feature(unit, soc_feature_timesync_support)) { 6671 return BCM_E_UNAVAIL; 6672 } 6673 6674 /* Given control type select register. */ 6675 switch (type) { 6676 case bcmSwitchMMRPDestMacOui: 6677 reg1 = MMRP_CONTROL_1r; 6678 reg2 = MMRP_CONTROL_2r; 6679 f_lo = MAC_DA_LOWERf; 6680 f_hi = MAC_DA_UPPERf; 6681 break; 6682 case bcmSwitchTimeSyncDestMacOui: 6683 reg1 = TS_CONTROL_1r; 6684 reg2 = TS_CONTROL_2r; 6685 f_lo = MAC_DA_LOWERf; 6686 f_hi = MAC_DA_UPPERf; 6687 break; 6688 case bcmSwitchSRPDestMacOui: 6689 reg1 = SRP_CONTROL_1r; 6690 reg2 = SRP_CONTROL_2r; 6691 f_lo = MAC_DA_LOWERf; 6692 f_hi = MAC_DA_UPPERf; 6693 break; 6694 default: 6695 return BCM_E_PARAM; 6696 } 6697 6698 if (!soc_reg_field_valid(unit, reg1, f_lo)) { 6699 return BCM_E_UNAVAIL; 6700 } 6701 if (!soc_reg_field_valid(unit, reg2, f_hi)) { 6702 return BCM_E_UNAVAIL; 6703 } 6704 6705 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg1, REG_PORT_ANY, 0, ®val1)); 6706 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg2, REG_PORT_ANY, 0, ®val2)); 6707 6708 fieldval = (mac_hi << 24); 6709 soc_reg_field_set(unit, reg1, ®val1, f_lo, fieldval); 6710 fieldval = (mac_hi >> 8) & 0xffff; 6711 soc_reg_field_set(unit, reg2, ®val2, f_hi, fieldval); 6712 6713 SOC_IF_ERROR_RETURN( 6714 soc_reg32_set(unit, reg1, REG_PORT_ANY, 0, regval1)); 6715 SOC_IF_ERROR_RETURN( 6716 soc_reg32_set(unit, reg2, REG_PORT_ANY, 0, regval2)); 6717 return BCM_E_NONE; 6718 } 6719 6720 6721 /* 6722 * Function: 6723 * _bcm_xgs3_switch_mac_lo_get 6724 * Description: 6725 * Get the lower 24 bits of MAC address field for MMRP, and SRP registers 6726 * Parameters: 6727 * unit - StrataSwitch PCI device unit number (driver internal). 6728 * port - port number. 6729 * type - The required switch control type to get MAC for 6730 * arg - arg to get the lower MAC address 6731 * Returns: 6732 * BCM_E_xxxx 6733 */ 6734 6735 STATIC int 6736 _bcm_xgs3_switch_mac_lo_get(int unit, bcm_port_t port, 6737 bcm_switch_control_t type, 6738 int *arg) 6739 { 6740 soc_reg_t reg = INVALIDr ; 6741 soc_field_t f_lo = INVALIDf; 6742 uint32 regval, mac; 6743 6744 if (!soc_feature(unit, soc_feature_timesync_support)) { 6745 return BCM_E_UNAVAIL; 6746 } 6747 6748 /* Given control type select register. */ 6749 switch (type) { 6750 case bcmSwitchMMRPDestMacNonOui: 6751 reg = MMRP_CONTROL_1r; 6752 f_lo = MAC_DA_LOWERf; 6753 break; 6754 case bcmSwitchTimeSyncDestMacNonOui: 6755 reg = TS_CONTROL_1r; 6756 f_lo = MAC_DA_LOWERf; 6757 break; 6758 case bcmSwitchSRPDestMacNonOui: 6759 reg = SRP_CONTROL_1r; 6760 f_lo = MAC_DA_LOWERf; 6761 break; 6762 case bcmSwitchRemoteCpuLocalMacNonOui: 6763 reg = CMIC_PKT_LMAC0_LOr; 6764 f_lo = MAC0_LOf; 6765 break; 6766 case bcmSwitchRemoteCpuDestMacNonOui: 6767 reg = CMIC_PKT_RMACr; 6768 f_lo = MAC0_LOf; 6769 break; 6770 default: 6771 return BCM_E_PARAM; 6772 } 6773 6774 if (!soc_reg_field_valid(unit, reg, f_lo)) { 6775 return BCM_E_UNAVAIL; 6776 } 6777 6778 SOC_IF_ERROR_RETURN( 6779 soc_reg32_get(unit, reg, REG_PORT_ANY, 0, ®val)); 6780 mac = soc_reg_field_get(unit, reg, regval, f_lo); 6781 6782 *arg = (mac << 8) >> 8; 6783 6784 return BCM_E_NONE; 6785 } 6786 6787 /* 6788 * Function: 6789 * _bcm_xgs3_switch_mac_hi_get 6790 * Description: 6791 * Get the upper 24 bits of MAC address field for MMRP, and SRP registers 6792 * Parameters: 6793 * unit - StrataSwitch PCI device unit number (driver internal). 6794 * port - port number. 6795 * type - The required switch control type to get MAC for 6796 * arg - arg to get the upper MAC address 6797 * Returns: 6798 * BCM_E_xxxx 6799 */ 6800 6801 STATIC int 6802 _bcm_xgs3_switch_mac_hi_get(int unit, bcm_port_t port, 6803 bcm_switch_control_t type, 6804 int *arg) 6805 { 6806 soc_reg_t reg1, reg2; 6807 soc_field_t f_lo, f_hi; 6808 uint32 mac, regval1, regval2; 6809 6810 reg1 = reg2 = INVALIDr; 6811 6812 if (!soc_feature(unit, soc_feature_timesync_support)) { 6813 return BCM_E_UNAVAIL; 6814 } 6815 6816 /* Given control type select register. */ 6817 switch (type) { 6818 case bcmSwitchMMRPDestMacOui: 6819 reg1 = MMRP_CONTROL_1r; 6820 reg2 = MMRP_CONTROL_2r; 6821 f_lo = MAC_DA_LOWERf; 6822 f_hi = MAC_DA_UPPERf; 6823 break; 6824 case bcmSwitchTimeSyncDestMacOui: 6825 reg1 = TS_CONTROL_1r; 6826 reg2 = TS_CONTROL_2r; 6827 f_lo = MAC_DA_LOWERf; 6828 f_hi = MAC_DA_UPPERf; 6829 break; 6830 case bcmSwitchSRPDestMacOui: 6831 reg1 = SRP_CONTROL_1r; 6832 reg2 = SRP_CONTROL_2r; 6833 f_lo = MAC_DA_LOWERf; 6834 f_hi = MAC_DA_UPPERf; 6835 break; 6836 default: 6837 return BCM_E_PARAM; 6838 } 6839 6840 if (!soc_reg_field_valid(unit, reg1, f_lo)) { 6841 return BCM_E_UNAVAIL; 6842 } 6843 if (!soc_reg_field_valid(unit, reg2, f_hi)) { 6844 return BCM_E_UNAVAIL; 6845 } 6846 SOC_IF_ERROR_RETURN( 6847 soc_reg32_get(unit, reg1, REG_PORT_ANY, 0, ®val1)); 6848 mac = (soc_reg_field_get(unit, reg1, regval1, f_lo) >> 24); 6849 6850 SOC_IF_ERROR_RETURN( 6851 soc_reg32_get(unit, reg2, REG_PORT_ANY, 0, ®val2)); 6852 mac |= (soc_reg_field_get(unit, reg2, regval2, f_hi) << 8); 6853 6854 *arg = (int)mac; 6855 6856 return BCM_E_NONE; 6857 } 6858 6859 /* 6860 * Function: 6861 * _bcm_xgs3_eav_action_set 6862 * Description: 6863 * Set the Time-Sync, MMRP, and SRP registers 6864 * Parameters: 6865 * unit - StrataSwitch PCI device unit number (driver internal). 6866 * type - The desired configuration parameter to set. 6867 * arg - EAV actions 6868 * Returns: 6869 * BCM_E_xxxx 6870 */ 6871 6872 STATIC int 6873 _bcm_xgs3_eav_action_set(int unit, 6874 bcm_port_t port, 6875 bcm_switch_control_t type, 6876 int arg) 6877 { 6878 uint32 values[3]; 6879 soc_field_t fields[3]; 6880 int idx; 6881 soc_reg_t reg = INVALIDr ; 6882 int fcount = 1; 6883 int value = (arg) ? 1 : 0; 6884 6885 if (!soc_feature(unit, soc_feature_timesync_support)) { 6886 return BCM_E_UNAVAIL; 6887 } 6888 6889 for (idx = 0; idx < COUNTOF(values); idx++) { 6890 values[idx] = value; 6891 fields[idx] = INVALIDf; 6892 } 6893 6894 reg = PROTOCOL_PKT_CONTROLr; 6895 /* Given control type select register field. */ 6896 switch (type) { 6897 case bcmSwitchTimeSyncPktToCpu: 6898 if (soc_reg_field_valid(unit, reg, TS_PKT_TO_CPUf)) { 6899 fields[0] = TS_PKT_TO_CPUf; 6900 } else { 6901 return BCM_E_UNAVAIL; 6902 } 6903 break; 6904 case bcmSwitchTimeSyncPktDrop: 6905 if (soc_reg_field_valid(unit, reg, TS_FWD_ACTIONf)) { 6906 fields[0] = TS_FWD_ACTIONf; 6907 values[0] = (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 6908 } else { 6909 return BCM_E_UNAVAIL; 6910 } 6911 break; 6912 case bcmSwitchTimeSyncPktFlood: 6913 if (soc_reg_field_valid(unit, reg, TS_FWD_ACTIONf)) { 6914 fields[0] = TS_FWD_ACTIONf; 6915 values[0] = (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 6916 } else { 6917 return BCM_E_UNAVAIL; 6918 } 6919 break; 6920 case bcmSwitchMmrpPktToCpu: 6921 if (soc_reg_field_valid(unit, reg, MMRP_PKT_TO_CPUf)) { 6922 fields[0] = MMRP_PKT_TO_CPUf; 6923 } else { 6924 return BCM_E_UNAVAIL; 6925 } 6926 break; 6927 case bcmSwitchMmrpPktDrop: 6928 if (soc_reg_field_valid(unit, reg, MMRP_FWD_ACTIONf)) { 6929 fields[0] = MMRP_FWD_ACTIONf; 6930 values[0] = (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 6931 } else { 6932 return BCM_E_UNAVAIL; 6933 } 6934 break; 6935 case bcmSwitchMmrpPktFlood: 6936 if (soc_reg_field_valid(unit, reg, MMRP_FWD_ACTIONf)) { 6937 fields[0] = MMRP_FWD_ACTIONf; 6938 values[0] = (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 6939 } else { 6940 return BCM_E_UNAVAIL; 6941 } 6942 break; 6943 case bcmSwitchSrpPktToCpu: 6944 if (soc_reg_field_valid(unit, reg, SRP_PKT_TO_CPUf)) { 6945 fields[0] = SRP_PKT_TO_CPUf; 6946 } else { 6947 return BCM_E_UNAVAIL; 6948 } 6949 break; 6950 case bcmSwitchSrpPktDrop: 6951 if (soc_reg_field_valid(unit, reg, SRP_FWD_ACTIONf)) { 6952 fields[0] = SRP_FWD_ACTIONf; 6953 values[0] = (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 6954 } else { 6955 return BCM_E_UNAVAIL; 6956 } 6957 break; 6958 case bcmSwitchSrpPktFlood: 6959 if (soc_reg_field_valid(unit, reg, SRP_FWD_ACTIONf)) { 6960 fields[0] = SRP_FWD_ACTIONf; 6961 values[0] = (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 6962 } else { 6963 return BCM_E_UNAVAIL; 6964 } 6965 break; 6966 default: 6967 return (BCM_E_UNAVAIL); 6968 } 6969 6970 #ifdef BCM_TRIUMPH2_SUPPORT 6971 if (SOC_REG_INFO(unit, reg).regtype != soc_portreg) { 6972 return _bcm_tr2_prot_pkt_profile_set(unit, reg, port, fcount, fields, 6973 values); 6974 } else 6975 #endif /* BCM_TRIUMPH2_SUPPORT */ 6976 { 6977 return soc_reg_fields32_modify(unit, reg, port, fcount, fields, 6978 values); 6979 } 6980 } 6981 6982 /* 6983 * Function: 6984 * _bcm_xgs3_eav_action_get 6985 * Description: 6986 * Get the Time-Sync, MMRP, and SRP registers 6987 * Parameters: 6988 * unit - StrataSwitch PCI device unit number (driver internal). 6989 * type - The desired configuration parameter to set. 6990 * *arg - EAV actions 6991 * Returns: 6992 * BCM_E_xxxx 6993 */ 6994 6995 STATIC int 6996 _bcm_xgs3_eav_action_get(int unit, 6997 bcm_port_t port, 6998 bcm_switch_control_t type, 6999 int *arg) 7000 { 7001 uint32 eav; 7002 soc_field_t field = INVALIDf; 7003 soc_reg_t reg = INVALIDr; 7004 int act_value = BCM_SWITCH_RESERVED_VALUE; 7005 int hw_value = -1; 7006 7007 reg = PROTOCOL_PKT_CONTROLr; 7008 /* Given control type select register field. */ 7009 switch (type) { 7010 case bcmSwitchTimeSyncPktToCpu: 7011 field = TS_PKT_TO_CPUf; 7012 act_value = 1; 7013 break; 7014 case bcmSwitchTimeSyncPktDrop: 7015 field = TS_FWD_ACTIONf; 7016 act_value = BCM_SWITCH_DROP_VALUE; 7017 break; 7018 case bcmSwitchTimeSyncPktFlood: 7019 field = TS_FWD_ACTIONf; 7020 act_value = BCM_SWITCH_FLOOD_VALUE; 7021 break; 7022 case bcmSwitchMmrpPktToCpu: 7023 field = MMRP_PKT_TO_CPUf; 7024 act_value = 1; 7025 break; 7026 case bcmSwitchMmrpPktDrop: 7027 field = MMRP_FWD_ACTIONf; 7028 act_value = BCM_SWITCH_DROP_VALUE; 7029 break; 7030 case bcmSwitchMmrpPktFlood: 7031 field = MMRP_FWD_ACTIONf; 7032 act_value = BCM_SWITCH_FLOOD_VALUE; 7033 break; 7034 case bcmSwitchSrpPktToCpu: 7035 field = SRP_PKT_TO_CPUf; 7036 act_value = 1; 7037 break; 7038 case bcmSwitchSrpPktDrop: 7039 field = SRP_FWD_ACTIONf; 7040 act_value = BCM_SWITCH_DROP_VALUE; 7041 break; 7042 case bcmSwitchSrpPktFlood: 7043 field = SRP_FWD_ACTIONf; 7044 act_value = BCM_SWITCH_FLOOD_VALUE; 7045 break; 7046 default: 7047 return (BCM_E_UNAVAIL); 7048 } 7049 7050 if (soc_reg_field_valid(unit, reg, field)) { 7051 #ifdef BCM_TRIUMPH2_SUPPORT 7052 if (SOC_REG_INFO(unit, reg).regtype != soc_portreg) { 7053 int index; 7054 7055 BCM_IF_ERROR_RETURN 7056 (_bcm_tr2_protocol_pkt_index_get(unit, port, &index)); 7057 BCM_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, index, &eav)); 7058 } else 7059 #endif /* BCM_TRIUMPH2_SUPPORT */ 7060 { 7061 BCM_IF_ERROR_RETURN(READ_PROTOCOL_PKT_CONTROLr(unit, port, &eav)); 7062 } 7063 hw_value = soc_reg_field_get(unit, reg, eav, field); 7064 } else { 7065 return BCM_E_UNAVAIL; 7066 } 7067 7068 *arg = (act_value == hw_value) ? 1 : 0; 7069 return (BCM_E_NONE); 7070 } 7071 #endif /* HAWKEYE, TRIUMPH2, APOLLO */ 7072 7073 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRX_SUPPORT) 7074 /* 7075 * Function: 7076 * _bcm_xgs3_selectcontrol_set 7077 * Description: 7078 * Set the enhanced (aka rtag 7) hash select control. 7079 * Parameters: 7080 * unit - StrataSwitch PCI device unit number (driver internal). 7081 * arg - BCM_HASH_CONTROL* 7082 * Returns: 7083 * BCM_E_xxxx 7084 */ 7085 7086 STATIC int 7087 _bcm_xgs3_selectcontrol_set(int unit, int arg) 7088 { 7089 uint64 hash_control; 7090 uint32 val; 7091 #if defined(BCM_TRIDENT2_SUPPORT) 7092 uint32 hash_control_4; 7093 #endif 7094 #if defined(BCM_HURRICANE_SUPPORT) 7095 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 7096 return (BCM_E_UNAVAIL); 7097 } 7098 7099 #endif 7100 #if defined(BCM_TRIDENT2_SUPPORT) 7101 if (SOC_IS_TD2_TT2(unit) && !SOC_IS_TOMAHAWK3(unit)) { 7102 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_4r(unit, &hash_control_4)); 7103 val = (arg & BCM_HASH_FIELD0_DISABLE_VXLAN) ? 1 : 0; 7104 soc_reg_field_set(unit, RTAG7_HASH_CONTROL_4r, 7105 &hash_control_4, DISABLE_HASH_VXLAN_Af, val); 7106 val = (arg & BCM_HASH_FIELD1_DISABLE_VXLAN) ? 1 : 0; 7107 soc_reg_field_set(unit, RTAG7_HASH_CONTROL_4r, 7108 &hash_control_4, DISABLE_HASH_VXLAN_Bf, val); 7109 BCM_IF_ERROR_RETURN(WRITE_RTAG7_HASH_CONTROL_4r(unit, hash_control_4)); 7110 } 7111 #endif 7112 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &hash_control)); 7113 7114 val = (arg & BCM_HASH_FIELD0_DISABLE_IP4 ) ? 1 : 0; 7115 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7116 DISABLE_HASH_IPV4_Af, val); 7117 7118 val = (arg & BCM_HASH_FIELD1_DISABLE_IP4) ? 1 : 0; 7119 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7120 DISABLE_HASH_IPV4_Bf, val); 7121 7122 val = (arg & BCM_HASH_FIELD0_DISABLE_IP6) ? 1 : 0; 7123 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7124 DISABLE_HASH_IPV6_Af, val); 7125 7126 val = (arg & BCM_HASH_FIELD1_DISABLE_IP6) ? 1 : 0; 7127 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7128 DISABLE_HASH_IPV6_Bf, val); 7129 7130 val = (arg & BCM_HASH_FIELD0_DISABLE_MPLS) ? 1 : 0; 7131 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7132 DISABLE_HASH_MPLS_Af, val); 7133 7134 val = (arg & BCM_HASH_FIELD1_DISABLE_MPLS) ? 1 : 0; 7135 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7136 DISABLE_HASH_MPLS_Bf, val); 7137 7138 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP) ? 1 : 0; 7139 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7140 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Af, val); 7141 7142 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP) ? 1 : 0; 7143 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7144 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Bf, val); 7145 7146 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP) ? 1 : 0; 7147 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7148 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Af, val); 7149 7150 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP) ? 1 : 0; 7151 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7152 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Bf, val); 7153 7154 #ifdef BCM_TRIUMPH2_SUPPORT 7155 if (SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROLr, DISABLE_HASH_MIM_Af)) { 7156 val = (arg & BCM_HASH_FIELD0_DISABLE_MIM) ? 1 : 0; 7157 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7158 DISABLE_HASH_MIM_Af, val); 7159 7160 val = (arg & BCM_HASH_FIELD1_DISABLE_MIM) ? 1 : 0; 7161 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7162 DISABLE_HASH_MIM_Bf, val); 7163 } 7164 #endif 7165 7166 #ifdef BCM_TRIDENT_SUPPORT 7167 if (SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROLr, DISABLE_FCOE_HASH_Af)) { 7168 val = (arg & BCM_HASH_FIELD0_DISABLE_FCOE) ? 1 : 0; 7169 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7170 DISABLE_FCOE_HASH_Af, val); 7171 7172 val = (arg & BCM_HASH_FIELD1_DISABLE_FCOE) ? 1 : 0; 7173 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7174 DISABLE_FCOE_HASH_Bf, val); 7175 } 7176 #endif /* BCM_TRIDENT_SUPPORT */ 7177 7178 #ifdef BCM_TRX_SUPPORT 7179 if (SOC_IS_TRX(unit)) { 7180 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP6) ? 1 : 0; 7181 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7182 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Af, val); 7183 7184 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP6) ? 1 : 0; 7185 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7186 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Bf, val); 7187 7188 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP6) ? 1 : 0; 7189 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7190 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Af, val); 7191 7192 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP6) ? 1 : 0; 7193 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7194 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Bf, val); 7195 7196 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP4 | 7197 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7198 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7199 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Af, val); 7200 7201 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP6 | 7202 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7203 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7204 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Af, val); 7205 7206 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP4 | 7207 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7208 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7209 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Bf, val); 7210 7211 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP6 | 7212 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7213 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7214 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Bf, val); 7215 7216 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP4 | 7217 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7218 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7219 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Af, val); 7220 7221 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP6 | 7222 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7223 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7224 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Af, val); 7225 7226 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP4 | 7227 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7228 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7229 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Bf, val); 7230 7231 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP6 | 7232 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7233 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7234 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Bf, val); 7235 } else 7236 #endif 7237 { 7238 #ifdef BCM_HB_GW_SUPPORT 7239 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE) ? 1 : 0; 7240 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7241 DISABLE_HASH_INNER_IPV4_OVER_GRE_Af, val); 7242 7243 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE) ? 1 : 0; 7244 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7245 DISABLE_HASH_INNER_IPV4_OVER_GRE_Bf, val); 7246 7247 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE) ? 1 : 0; 7248 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7249 DISABLE_HASH_INNER_IPV6_OVER_GRE_Af, val); 7250 7251 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE) ? 1 : 0; 7252 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 7253 DISABLE_HASH_INNER_IPV6_OVER_GRE_Bf, val); 7254 #endif 7255 } 7256 7257 BCM_IF_ERROR_RETURN(WRITE_RTAG7_HASH_CONTROLr(unit, hash_control)); 7258 7259 return BCM_E_NONE; 7260 } 7261 7262 /* 7263 * Function: 7264 * _bcm_xgs3_selectcontrol_get 7265 * Description: 7266 * Get the current enhanced (aka rtag 7) hash control settings. 7267 * Parameters: 7268 * unit - StrataSwitch PCI device unit number (driver internal). 7269 * arg - Pointer to where the retrieved value will be written. 7270 * Returns: 7271 * BCM_E_xxxx 7272 */ 7273 7274 STATIC int 7275 _bcm_xgs3_selectcontrol_get(int unit, int *arg) 7276 { 7277 uint64 hash_control; 7278 uint32 val; 7279 #if defined(BCM_TRIDENT2_SUPPORT) 7280 uint32 hash_control_4; 7281 #endif 7282 #if defined(BCM_HURRICANE_SUPPORT) 7283 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 7284 return (BCM_E_UNAVAIL); 7285 } 7286 7287 #endif 7288 7289 *arg = 0; 7290 #if defined(BCM_TRIDENT2_SUPPORT) 7291 if (SOC_IS_TD2_TT2(unit) && !SOC_IS_TOMAHAWK3(unit)) { 7292 /* VXLAN for hash block A/B */ 7293 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_4r(unit, &hash_control_4)); 7294 val = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_4r, hash_control_4, 7295 DISABLE_HASH_VXLAN_Af); 7296 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_VXLAN; 7297 7298 val = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_4r, hash_control_4, 7299 DISABLE_HASH_VXLAN_Bf); 7300 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_VXLAN; 7301 } 7302 #endif 7303 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &hash_control)); 7304 7305 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7306 DISABLE_HASH_IPV4_Af); 7307 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_IP4; 7308 7309 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7310 DISABLE_HASH_IPV4_Bf); 7311 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_IP4; 7312 7313 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7314 DISABLE_HASH_IPV6_Af); 7315 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_IP6; 7316 7317 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7318 DISABLE_HASH_IPV6_Bf); 7319 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_IP6; 7320 7321 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7322 DISABLE_HASH_MPLS_Af); 7323 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_MPLS; 7324 7325 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7326 DISABLE_HASH_MPLS_Bf); 7327 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_MPLS; 7328 7329 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7330 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Af); 7331 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP; 7332 7333 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7334 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Bf); 7335 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP; 7336 7337 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7338 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Af); 7339 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP; 7340 7341 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7342 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Bf); 7343 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP; 7344 7345 #ifdef BCM_TRIUMPH2_SUPPORT 7346 if (SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROLr, DISABLE_HASH_MIM_Af)) { 7347 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7348 DISABLE_HASH_MIM_Af); 7349 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_MIM; 7350 7351 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7352 DISABLE_HASH_MIM_Bf); 7353 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_MIM; 7354 } 7355 #endif 7356 7357 #ifdef BCM_TRIDENT_SUPPORT 7358 if (SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROLr, DISABLE_FCOE_HASH_Af)) { 7359 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7360 DISABLE_FCOE_HASH_Af); 7361 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_FCOE; 7362 7363 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7364 DISABLE_FCOE_HASH_Bf); 7365 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_FCOE; 7366 } 7367 #endif 7368 7369 #ifdef BCM_TRX_SUPPORT 7370 if (SOC_IS_TRX(unit)) { 7371 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7372 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Af); 7373 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP6; 7374 7375 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7376 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Bf); 7377 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP6; 7378 7379 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7380 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Af); 7381 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP6; 7382 7383 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7384 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Bf); 7385 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP6; 7386 7387 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7388 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Af); 7389 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP4; 7390 7391 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7392 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Af); 7393 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP6; 7394 7395 if ((*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP4) && 7396 (*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP6)) 7397 *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE; 7398 7399 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7400 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Bf); 7401 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP4; 7402 7403 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7404 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Bf); 7405 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP6; 7406 7407 if ((*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP4) && 7408 (*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP6)) 7409 *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE; 7410 7411 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7412 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Af); 7413 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP4; 7414 7415 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7416 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Af); 7417 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP6; 7418 7419 if ((*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP4) && 7420 (*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP6)) 7421 *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE; 7422 7423 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7424 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Bf); 7425 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP4; 7426 7427 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7428 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Bf); 7429 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP6; 7430 7431 if ((*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP4) && 7432 (*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP6)) 7433 *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE; 7434 } else 7435 #endif 7436 { 7437 #ifdef BCM_HB_GW_SUPPORT 7438 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7439 DISABLE_HASH_INNER_IPV4_OVER_GRE_Af); 7440 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE; 7441 7442 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7443 DISABLE_HASH_INNER_IPV4_OVER_GRE_Bf); 7444 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE; 7445 7446 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7447 DISABLE_HASH_INNER_IPV6_OVER_GRE_Af); 7448 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE; 7449 7450 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 7451 DISABLE_HASH_INNER_IPV6_OVER_GRE_Bf); 7452 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE; 7453 #endif 7454 } 7455 7456 return BCM_E_NONE; 7457 } 7458 7459 /* 7460 * Function: 7461 * _bcm_kt2_selectcontrol_set 7462 * Description: 7463 * Set the enhanced (aka rtag 7) hash select control. 7464 * Parameters: 7465 * unit - StrataSwitch PCI device unit number (driver internal). 7466 * arg - BCM_HASH_CONTROL* 7467 * Returns: 7468 * BCM_E_xxxx 7469 */ 7470 7471 STATIC int 7472 _bcm_kt2_selectcontrol_set(int unit, int arg) 7473 { 7474 uint64 hash_control; 7475 uint32 val; 7476 7477 #if defined(BCM_HURRICANE_SUPPORT) 7478 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 7479 return (BCM_E_UNAVAIL); 7480 } 7481 #endif 7482 7483 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_64r(unit, &hash_control)); 7484 7485 val = (arg & BCM_HASH_FIELD0_DISABLE_IP4 ) ? 1 : 0; 7486 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7487 DISABLE_HASH_IPV4_Af, val); 7488 7489 val = (arg & BCM_HASH_FIELD1_DISABLE_IP4) ? 1 : 0; 7490 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7491 DISABLE_HASH_IPV4_Bf, val); 7492 7493 val = (arg & BCM_HASH_FIELD0_DISABLE_IP6) ? 1 : 0; 7494 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7495 DISABLE_HASH_IPV6_Af, val); 7496 7497 val = (arg & BCM_HASH_FIELD1_DISABLE_IP6) ? 1 : 0; 7498 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7499 DISABLE_HASH_IPV6_Bf, val); 7500 7501 val = (arg & BCM_HASH_FIELD0_DISABLE_MPLS) ? 1 : 0; 7502 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7503 DISABLE_HASH_MPLS_Af, val); 7504 7505 val = (arg & BCM_HASH_FIELD1_DISABLE_MPLS) ? 1 : 0; 7506 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7507 DISABLE_HASH_MPLS_Bf, val); 7508 7509 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP) ? 1 : 0; 7510 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7511 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Af, val); 7512 7513 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP) ? 1 : 0; 7514 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7515 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Bf, val); 7516 7517 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP) ? 1 : 0; 7518 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7519 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Af, val); 7520 7521 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP) ? 1 : 0; 7522 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7523 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Bf, val); 7524 7525 val = (arg & BCM_HASH_FIELD0_DISABLE_MIM) ? 1 : 0; 7526 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7527 DISABLE_HASH_MIM_Af, val); 7528 7529 val = (arg & BCM_HASH_FIELD1_DISABLE_MIM) ? 1 : 0; 7530 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7531 DISABLE_HASH_MIM_Bf, val); 7532 7533 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP6) ? 1 : 0; 7534 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7535 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Af, val); 7536 7537 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP6) ? 1 : 0; 7538 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7539 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Bf, val); 7540 7541 val = (arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP6) ? 1 : 0; 7542 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7543 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Af, val); 7544 7545 val = (arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP6) ? 1 : 0; 7546 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7547 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Bf, val); 7548 7549 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP4 | 7550 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7551 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7552 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Af, val); 7553 7554 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP6 | 7555 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7556 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7557 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Af, val); 7558 7559 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP4 | 7560 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7561 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7562 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Bf, val); 7563 7564 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP6 | 7565 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE)) ? 1 : 0; 7566 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7567 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Bf, val); 7568 7569 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP4 | 7570 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7571 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7572 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Af, val); 7573 7574 val = (arg & (BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP6 | 7575 BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7576 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7577 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Af, val); 7578 7579 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP4 | 7580 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7581 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7582 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Bf, val); 7583 7584 val = (arg & (BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP6 | 7585 BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE)) ? 1 : 0; 7586 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_64r, &hash_control, 7587 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Bf, val); 7588 7589 BCM_IF_ERROR_RETURN(WRITE_RTAG7_HASH_CONTROL_64r(unit, hash_control)); 7590 7591 return BCM_E_NONE; 7592 } 7593 7594 /* 7595 * Function: 7596 * _bcm_kt2_selectcontrol_get 7597 * Description: 7598 * Get the current enhanced (aka rtag 7) hash control settings. 7599 * Parameters: 7600 * unit - StrataSwitch PCI device unit number (driver internal). 7601 * arg - Pointer to where the retrieved value will be written. 7602 * Returns: 7603 * BCM_E_xxxx 7604 */ 7605 7606 STATIC int 7607 _bcm_kt2_selectcontrol_get(int unit, int *arg) 7608 { 7609 uint64 hash_control; 7610 uint32 val; 7611 7612 7613 *arg = 0; 7614 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_64r(unit, &hash_control)); 7615 7616 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7617 DISABLE_HASH_IPV4_Af); 7618 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_IP4; 7619 7620 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7621 DISABLE_HASH_IPV4_Bf); 7622 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_IP4; 7623 7624 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7625 DISABLE_HASH_IPV6_Af); 7626 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_IP6; 7627 7628 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7629 DISABLE_HASH_IPV6_Bf); 7630 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_IP6; 7631 7632 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7633 DISABLE_HASH_MPLS_Af); 7634 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_MPLS; 7635 7636 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7637 DISABLE_HASH_MPLS_Bf); 7638 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_MPLS; 7639 7640 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7641 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Af); 7642 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP; 7643 7644 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7645 DISABLE_HASH_INNER_IPV4_OVER_IPV4_Bf); 7646 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP; 7647 7648 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7649 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Af); 7650 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP; 7651 7652 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7653 DISABLE_HASH_INNER_IPV6_OVER_IPV4_Bf); 7654 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP; 7655 7656 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7657 DISABLE_HASH_MIM_Af); 7658 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_MIM; 7659 7660 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7661 DISABLE_HASH_MIM_Bf); 7662 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_MIM; 7663 7664 7665 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7666 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Af); 7667 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_IP6; 7668 7669 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7670 DISABLE_HASH_INNER_IPV4_OVER_IPV6_Bf); 7671 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_IP6; 7672 7673 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7674 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Af); 7675 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_IP6; 7676 7677 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7678 DISABLE_HASH_INNER_IPV6_OVER_IPV6_Bf); 7679 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_IP6; 7680 7681 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7682 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Af); 7683 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP4; 7684 7685 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7686 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Af); 7687 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP6; 7688 7689 if ((*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP4) && 7690 (*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE_IP6)) 7691 *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP4_GRE; 7692 7693 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7694 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV4_Bf); 7695 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP4; 7696 7697 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7698 DISABLE_HASH_INNER_IPV4_OVER_GRE_IPV6_Bf); 7699 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP6; 7700 7701 if ((*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP4) && 7702 (*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE_IP6)) 7703 *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP4_GRE; 7704 7705 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7706 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Af); 7707 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP4; 7708 7709 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7710 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Af); 7711 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP6; 7712 7713 if ((*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP4) && 7714 (*arg & BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE_IP6)) 7715 *arg |= BCM_HASH_FIELD0_DISABLE_TUNNEL_IP6_GRE; 7716 7717 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7718 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV4_Bf); 7719 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP4; 7720 7721 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_64r, hash_control, 7722 DISABLE_HASH_INNER_IPV6_OVER_GRE_IPV6_Bf); 7723 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP6; 7724 7725 if ((*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP4) && 7726 (*arg & BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE_IP6)) 7727 *arg |= BCM_HASH_FIELD1_DISABLE_TUNNEL_IP6_GRE; 7728 7729 return BCM_E_NONE; 7730 } 7731 7732 /* 7733 * Function: 7734 * _bcm_xgs3_fieldconfig_set 7735 * Description: 7736 * Set the enhanced (aka rtag 7) field config settings. 7737 * Parameters: 7738 * unit - StrataSwitch PCI device unit number (driver internal). 7739 * type - The desired configuration parameter to set. 7740 * arg - BCM_HASH_CONTROL* 7741 * Returns: 7742 * BCM_E_xxxx 7743 */ 7744 7745 STATIC int 7746 _bcm_xgs3_fieldconfig_set(int unit, 7747 bcm_switch_control_t type, int arg) 7748 { 7749 soc_reg_t reg; 7750 soc_field_t field; 7751 uint64 hash_control; 7752 uint32 val; 7753 7754 #if defined(BCM_HURRICANE_SUPPORT) 7755 if(SOC_IS_HURRICANEX(unit)) { 7756 return (BCM_E_UNAVAIL); 7757 } 7758 #endif 7759 7760 #ifdef BCM_TRIDENT_SUPPORT 7761 if (SOC_IS_TD_TT(unit)|| SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit)) { 7762 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_3_64r)) { 7763 reg = RTAG7_HASH_CONTROL_3_64r; 7764 } else { 7765 reg = RTAG7_HASH_CONTROL_3r; 7766 } 7767 switch (type) { 7768 case bcmSwitchHashField0Config: 7769 field = HASH_A0_FUNCTION_SELECTf; 7770 break; 7771 case bcmSwitchHashField0Config1: 7772 field = HASH_A1_FUNCTION_SELECTf; 7773 break; 7774 case bcmSwitchHashField1Config: 7775 field = HASH_B0_FUNCTION_SELECTf; 7776 break; 7777 case bcmSwitchHashField1Config1: 7778 field = HASH_B1_FUNCTION_SELECTf; 7779 break; 7780 case bcmSwitchMacroFlowHashFieldConfig: 7781 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2r)) { 7782 reg = RTAG7_HASH_CONTROL_2r; 7783 } else if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2_64r)) { 7784 reg = RTAG7_HASH_CONTROL_2_64r; 7785 } 7786 field = MACRO_FLOW_HASH_FUNC_SELf; 7787 break; 7788 default: 7789 return BCM_E_UNAVAIL; 7790 } 7791 switch (arg) { 7792 case BCM_HASH_FIELD_CONFIG_CRC16XOR8: 7793 val = ENHANCE_XGS3_HASH_CRC16XOR8; 7794 break; 7795 case BCM_HASH_FIELD_CONFIG_CRC16XOR4: 7796 val = ENHANCE_XGS3_HASH_CRC16XOR4; 7797 break; 7798 case BCM_HASH_FIELD_CONFIG_CRC16XOR2: 7799 val = ENHANCE_XGS3_HASH_CRC16XOR2; 7800 break; 7801 case BCM_HASH_FIELD_CONFIG_CRC16XOR1: 7802 val = ENHANCE_XGS3_HASH_CRC16XOR1; 7803 break; 7804 case BCM_HASH_FIELD_CONFIG_CRC16: 7805 val = ENHANCE_XGS3_HASH_CRC16; 7806 break; 7807 case BCM_HASH_FIELD_CONFIG_XOR16: 7808 val = ENHANCE_XGS3_HASH_XOR16; 7809 break; 7810 case BCM_HASH_FIELD_CONFIG_CRC16CCITT: 7811 val = ENHANCE_XGS3_HASH_CRC16CCITT; 7812 break; 7813 case BCM_HASH_FIELD_CONFIG_CRC32LO: 7814 val = ENHANCE_XGS3_HASH_CRC32LO; 7815 break; 7816 case BCM_HASH_FIELD_CONFIG_CRC32HI: 7817 val = ENHANCE_XGS3_HASH_CRC32HI; 7818 break; 7819 case BCM_HASH_FIELD_CONFIG_CRC32_ETH_LO: 7820 val = ENHANCE_XGS3_HASH_ETH_CRC32LO; 7821 break; 7822 case BCM_HASH_FIELD_CONFIG_CRC32_ETH_HI: 7823 val = ENHANCE_XGS3_HASH_ETH_CRC32HI; 7824 break; 7825 case BCM_HASH_FIELD_CONFIG_CRC32_KOOPMAN_LO: 7826 val = ENHANCE_XGS3_HASH_KOOPMAN_CRC32LO; 7827 break; 7828 case BCM_HASH_FIELD_CONFIG_CRC32_KOOPMAN_HI: 7829 val = ENHANCE_XGS3_HASH_KOOPMAN_CRC32HI; 7830 break; 7831 default: 7832 val = 0; 7833 break; 7834 } 7835 } else 7836 #endif /* BCM_TRIDENT_SUPPORT */ 7837 { 7838 reg = RTAG7_HASH_CONTROLr; 7839 switch (type) { 7840 case bcmSwitchHashField0Config: 7841 field = HASH_MODE_Af; 7842 break; 7843 case bcmSwitchHashField1Config: 7844 field = HASH_MODE_Bf; 7845 break; 7846 default: 7847 return BCM_E_UNAVAIL; 7848 } 7849 switch (arg) { 7850 case BCM_HASH_FIELD_CONFIG_CRC16XOR8: 7851 val = ENHANCE_XGS3_HASH_CRC16XOR8; 7852 break; 7853 case BCM_HASH_FIELD_CONFIG_CRC16XOR4: 7854 val = ENHANCE_XGS3_HASH_CRC16XOR4; 7855 break; 7856 case BCM_HASH_FIELD_CONFIG_CRC16XOR2: 7857 val = ENHANCE_XGS3_HASH_CRC16XOR2; 7858 break; 7859 case BCM_HASH_FIELD_CONFIG_CRC16XOR1: 7860 val = ENHANCE_XGS3_HASH_CRC16XOR1; 7861 break; 7862 case BCM_HASH_FIELD_CONFIG_CRC16: 7863 val = ENHANCE_XGS3_HASH_CRC16; 7864 break; 7865 case BCM_HASH_FIELD_CONFIG_XOR16: 7866 case BCM_HASH_FIELD_CONFIG_CRC16CCITT: 7867 case BCM_HASH_FIELD_CONFIG_CRC32LO: 7868 case BCM_HASH_FIELD_CONFIG_CRC32HI: 7869 return BCM_E_UNAVAIL; 7870 default: 7871 val = 0; 7872 break; 7873 } 7874 } 7875 7876 if (!SOC_REG_FIELD_VALID(unit, reg, field)) { 7877 return BCM_E_UNAVAIL; 7878 } 7879 7880 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &hash_control)); 7881 soc_reg64_field32_set(unit, reg, &hash_control, field, val); 7882 BCM_IF_ERROR_RETURN(soc_reg_set(unit, reg, REG_PORT_ANY, 0, hash_control)); 7883 7884 return BCM_E_NONE; 7885 } 7886 7887 /* 7888 * Function: 7889 * _bcm_xgs3_fieldconfig_get 7890 * Description: 7891 * Get the current enhanced (aka rtag 7) field config settings. 7892 * Parameters: 7893 * unit - StrataSwitch PCI device unit number (driver internal). 7894 * type - The desired configuration parameter to retrieve. 7895 * arg - Pointer to where the retrieved value will be written. 7896 * Returns: 7897 * BCM_E_xxxx 7898 */ 7899 7900 STATIC int 7901 _bcm_xgs3_fieldconfig_get(int unit, 7902 bcm_switch_control_t type, int *arg) 7903 { 7904 soc_reg_t reg; 7905 soc_field_t field; 7906 uint64 hash_control; 7907 uint32 val; 7908 7909 #if defined(BCM_HURRICANE_SUPPORT) 7910 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 7911 return (BCM_E_UNAVAIL); 7912 } 7913 #endif 7914 7915 #ifdef BCM_TRIDENT_SUPPORT 7916 if (SOC_IS_TD_TT(unit) || SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit)) { 7917 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_3_64r)) { 7918 reg = RTAG7_HASH_CONTROL_3_64r; 7919 } else { 7920 reg = RTAG7_HASH_CONTROL_3r; 7921 } 7922 switch (type) { 7923 case bcmSwitchHashField0Config: 7924 field = HASH_A0_FUNCTION_SELECTf; 7925 break; 7926 case bcmSwitchHashField0Config1: 7927 field = HASH_A1_FUNCTION_SELECTf; 7928 break; 7929 case bcmSwitchHashField1Config: 7930 field = HASH_B0_FUNCTION_SELECTf; 7931 break; 7932 case bcmSwitchHashField1Config1: 7933 field = HASH_B1_FUNCTION_SELECTf; 7934 break; 7935 case bcmSwitchMacroFlowHashFieldConfig: 7936 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2r)) { 7937 reg = RTAG7_HASH_CONTROL_2r; 7938 } else if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2_64r)) { 7939 reg = RTAG7_HASH_CONTROL_2_64r; 7940 } 7941 field = MACRO_FLOW_HASH_FUNC_SELf; 7942 break; 7943 default: 7944 return BCM_E_UNAVAIL; 7945 } 7946 } else 7947 #endif /* BCM_TRIDENT_SUPPORT */ 7948 { 7949 reg = RTAG7_HASH_CONTROLr; 7950 switch (type) { 7951 case bcmSwitchHashField0Config: 7952 field = HASH_MODE_Af; 7953 break; 7954 case bcmSwitchHashField1Config: 7955 field = HASH_MODE_Bf; 7956 break; 7957 default: 7958 return BCM_E_UNAVAIL; 7959 } 7960 } 7961 7962 if (!SOC_REG_FIELD_VALID(unit, reg, field)) { 7963 return BCM_E_UNAVAIL; 7964 } 7965 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &hash_control)); 7966 val = soc_reg64_field32_get(unit, reg, hash_control, field); 7967 7968 switch (val) { 7969 case ENHANCE_XGS3_HASH_CRC16XOR8: 7970 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR8; 7971 break; 7972 case ENHANCE_XGS3_HASH_CRC16XOR4: 7973 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR4; 7974 break; 7975 case ENHANCE_XGS3_HASH_CRC16XOR2: 7976 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR2; 7977 break; 7978 case ENHANCE_XGS3_HASH_CRC16XOR1: 7979 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR1; 7980 break; 7981 case ENHANCE_XGS3_HASH_CRC16: 7982 *arg = BCM_HASH_FIELD_CONFIG_CRC16; 7983 break; 7984 case ENHANCE_XGS3_HASH_XOR16: 7985 *arg = BCM_HASH_FIELD_CONFIG_XOR16; 7986 break; 7987 case ENHANCE_XGS3_HASH_CRC16CCITT: 7988 *arg = BCM_HASH_FIELD_CONFIG_CRC16CCITT; 7989 break; 7990 case ENHANCE_XGS3_HASH_CRC32LO: 7991 *arg = BCM_HASH_FIELD_CONFIG_CRC32LO; 7992 break; 7993 case ENHANCE_XGS3_HASH_CRC32HI: 7994 *arg = BCM_HASH_FIELD_CONFIG_CRC32HI; 7995 break; 7996 case ENHANCE_XGS3_HASH_ETH_CRC32LO: 7997 *arg = BCM_HASH_FIELD_CONFIG_CRC32_ETH_LO; 7998 break; 7999 case ENHANCE_XGS3_HASH_ETH_CRC32HI: 8000 *arg = BCM_HASH_FIELD_CONFIG_CRC32_ETH_HI; 8001 break; 8002 case ENHANCE_XGS3_HASH_KOOPMAN_CRC32LO: 8003 *arg = BCM_HASH_FIELD_CONFIG_CRC32_KOOPMAN_LO; 8004 break; 8005 case ENHANCE_XGS3_HASH_KOOPMAN_CRC32HI: 8006 *arg = BCM_HASH_FIELD_CONFIG_CRC32_KOOPMAN_HI; 8007 break; 8008 default: 8009 *arg = 0; 8010 break; 8011 } 8012 8013 return BCM_E_NONE; 8014 } 8015 8016 _hash_bmap_t hash_select_common[] = 8017 { 8018 { BCM_HASH_FIELD_DSTMOD, 0x0001 }, 8019 { BCM_HASH_FIELD_DSTPORT, 0x0002 }, 8020 { BCM_HASH_FIELD_SRCMOD, 0x0004 }, 8021 { BCM_HASH_FIELD_SRCPORT, 0x0008 } 8022 }; 8023 8024 _hash_bmap_t hash_select_ip4[] = 8025 { 8026 { BCM_HASH_FIELD_PROTOCOL, 0x0010 }, 8027 { BCM_HASH_FIELD_DSTL4, 0x0020 }, 8028 { BCM_HASH_FIELD_SRCL4, 0x0040 }, 8029 { BCM_HASH_FIELD_VLAN, 0x0080 }, 8030 { BCM_HASH_FIELD_IP4DST_LO, 0x0100 }, 8031 { BCM_HASH_FIELD_IP4DST_HI, 0x0200 }, 8032 { BCM_HASH_FIELD_IP4SRC_LO, 0x0400 }, 8033 { BCM_HASH_FIELD_IP4SRC_HI, 0x0800 } 8034 }; 8035 8036 _hash_bmap_t hash_select_ip6[] = 8037 { 8038 { BCM_HASH_FIELD_NXT_HDR, 0x0010 }, 8039 { BCM_HASH_FIELD_DSTL4, 0x0020 }, 8040 { BCM_HASH_FIELD_SRCL4, 0x0040 }, 8041 { BCM_HASH_FIELD_VLAN, 0x0080 }, 8042 { BCM_HASH_FIELD_IP6DST_LO, 0x0100 }, 8043 { BCM_HASH_FIELD_IP6DST_HI, 0x0200 }, 8044 { BCM_HASH_FIELD_IP6SRC_LO, 0x0400 }, 8045 { BCM_HASH_FIELD_IP6SRC_HI, 0x0800 } 8046 }; 8047 8048 _hash_bmap_t hash_select_l2[] = 8049 { 8050 { BCM_HASH_FIELD_VLAN, 0x0010 }, 8051 { BCM_HASH_FIELD_ETHER_TYPE,0x0020 }, 8052 { BCM_HASH_FIELD_MACDA_LO, 0x0040 }, 8053 { BCM_HASH_FIELD_MACDA_MI, 0x0080 }, 8054 { BCM_HASH_FIELD_MACDA_HI, 0x0100 }, 8055 { BCM_HASH_FIELD_MACSA_LO, 0x0200 }, 8056 { BCM_HASH_FIELD_MACSA_MI, 0x0400 }, 8057 { BCM_HASH_FIELD_MACSA_HI, 0x0800 } 8058 }; 8059 8060 _hash_bmap_t hash_select_mpls[] = 8061 { 8062 { BCM_HASH_FIELD_VLAN, 0x0010 }, 8063 { BCM_HASH_FIELD_IP4DST_LO, 0x0020 }, 8064 { BCM_HASH_FIELD_IP4DST_HI, 0x0040 }, 8065 { BCM_HASH_FIELD_IP4SRC_LO, 0x0080 }, 8066 { BCM_HASH_FIELD_IP4SRC_HI, 0x0100 }, 8067 { BCM_HASH_FIELD_IP6DST_LO, 0x0020 }, 8068 { BCM_HASH_FIELD_IP6DST_HI, 0x0040 }, 8069 { BCM_HASH_FIELD_IP6SRC_LO, 0x0080 }, 8070 { BCM_HASH_FIELD_IP6SRC_HI, 0x0100 }, 8071 { BCM_HASH_FIELD_RSVD_LABELS,0x0200 }, 8072 { BCM_HASH_FIELD_2ND_LABEL, 0x0400 }, 8073 { BCM_HASH_FIELD_TOP_LABEL, 0x0800 } 8074 }; 8075 8076 _hash_bmap_t hash_select_unknown[] = 8077 { 8078 { BCM_HASH_FIELD_LOAD_BALANCE,0x0010 } 8079 }; 8080 8081 8082 _hash_bmap_t hash_field_payload_control[] = 8083 { 8084 { BCM_HASH_SELECT_INNER_L2, 0x0000 }, 8085 { BCM_HASH_SELECT_INNER_L3, 0x0001 } 8086 }; 8087 8088 _hash_bmap_t hash_field_tunnel_control[]= 8089 { 8090 { BCM_HASH_SELECT_OUTER_L2, 0x0000}, 8091 { BCM_HASH_SELECT_TUNNEL_INNER_L2, 0x0002}, 8092 { BCM_HASH_SELECT_INNER_L3, 0x0003} 8093 }; 8094 8095 8096 _hash_bmap_t hash_field_ipv6_collapse_control[] = 8097 { 8098 { BCM_HASH_IP6_COLLAPSE_XOR, 0x0000}, 8099 { BCM_HASH_IP6_COLLAPSE_LSB, 0x0001} 8100 }; 8101 8102 _hash_bmap_t hash_field_ipsec_control[] = 8103 { 8104 { BCM_HASH_IPSEC_SELECT_OUTER_L4_PORT, 0x0000}, 8105 { BCM_HASH_IPSEC_SELECT_SPI, 0x0002} 8106 }; 8107 8108 _hash_fieldselect_t hash_select_info[] = 8109 { 8110 { bcmSwitchHashIP4Field0, 8111 hash_select_ip4, COUNTOF(hash_select_ip4), 8112 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Af}, 8113 { bcmSwitchHashIP4Field1, 8114 hash_select_ip4, COUNTOF(hash_select_ip4), 8115 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Bf}, 8116 { bcmSwitchHashIP6Field0, 8117 hash_select_ip6, COUNTOF(hash_select_ip6), 8118 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Af}, 8119 { bcmSwitchHashIP6Field1, 8120 hash_select_ip6, COUNTOF(hash_select_ip6), 8121 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Bf}, 8122 { bcmSwitchHashL2Field0, 8123 hash_select_l2, COUNTOF(hash_select_l2), 8124 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Af}, 8125 { bcmSwitchHashL2Field1, 8126 hash_select_l2, COUNTOF(hash_select_l2), 8127 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Bf}, 8128 { bcmSwitchHashMPLSField0, 8129 hash_select_mpls, COUNTOF(hash_select_mpls), 8130 RTAG7_HASH_FIELD_BMAP_4r, MPLS_FIELD_BITMAP_Af}, 8131 { bcmSwitchHashMPLSField1, 8132 hash_select_mpls, COUNTOF(hash_select_mpls), 8133 RTAG7_HASH_FIELD_BMAP_4r, MPLS_FIELD_BITMAP_Bf}, 8134 { bcmSwitchHashHG2UnknownField0, 8135 hash_select_unknown, COUNTOF(hash_select_unknown), 8136 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Af}, 8137 { bcmSwitchHashHG2UnknownField1, 8138 hash_select_unknown, COUNTOF(hash_select_unknown), 8139 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Bf} 8140 8141 }; 8142 8143 #if defined(BCM_TRIUMPH2_SUPPORT) 8144 _hash_bmap_t hash_select_mpls_l2[] = 8145 { 8146 { BCM_HASH_FIELD_VLAN, 0x0010 }, 8147 { BCM_HASH_FIELD_ETHER_TYPE,0x0020 }, 8148 { BCM_HASH_FIELD_MACDA_LO, 0x0040 }, 8149 { BCM_HASH_FIELD_MACDA_MI, 0x0080 }, 8150 { BCM_HASH_FIELD_MACDA_HI, 0x0100 }, 8151 { BCM_HASH_FIELD_MACSA_LO, 0x0200 }, 8152 { BCM_HASH_FIELD_MACSA_MI, 0x0400 }, 8153 { BCM_HASH_FIELD_MACSA_HI, 0x0800 } 8154 }; 8155 8156 _hash_bmap_t hash_select_mpls_l3[] = 8157 { 8158 { BCM_HASH_FIELD_PROTOCOL, 0x0010 }, 8159 { BCM_HASH_FIELD_DSTL4, 0x0020 }, 8160 { BCM_HASH_FIELD_SRCL4, 0x0040 }, 8161 { BCM_HASH_FIELD_VLAN, 0x0080 }, 8162 { BCM_HASH_FIELD_IP4DST_LO, 0x0100 }, 8163 { BCM_HASH_FIELD_IP4DST_HI, 0x0200 }, 8164 { BCM_HASH_FIELD_IP4SRC_LO, 0x0400 }, 8165 { BCM_HASH_FIELD_IP4SRC_HI, 0x0800 } 8166 }; 8167 8168 _hash_bmap_t hash_select_mpls_tunnel[] = 8169 { 8170 { BCM_HASH_FIELD_2ND_LABEL, 0x0010 }, 8171 { BCM_HASH_FIELD_TOP_LABEL, 0x0020 }, 8172 { BCM_HASH_FIELD_MACDA_LO, 0x0040 }, 8173 { BCM_HASH_FIELD_MACDA_MI, 0x0080 }, 8174 { BCM_HASH_FIELD_MACDA_HI, 0x0100 }, 8175 { BCM_HASH_FIELD_MACSA_LO, 0x0200 }, 8176 { BCM_HASH_FIELD_MACSA_MI, 0x0400 }, 8177 { BCM_HASH_FIELD_MACSA_HI, 0x0800 } 8178 }; 8179 8180 _hash_bmap_t hash_select_mim[] = 8181 { 8182 { BCM_HASH_FIELD_VLAN, 0x0010 }, 8183 { BCM_HASH_FIELD_ETHER_TYPE,0x0020 }, 8184 { BCM_HASH_FIELD_MACDA_LO, 0x0040 }, 8185 { BCM_HASH_FIELD_MACDA_MI, 0x0080 }, 8186 { BCM_HASH_FIELD_MACDA_HI, 0x0100 }, 8187 { BCM_HASH_FIELD_MACSA_LO, 0x0200 }, 8188 { BCM_HASH_FIELD_MACSA_MI, 0x0400 }, 8189 { BCM_HASH_FIELD_MACSA_HI, 0x0800 } 8190 }; 8191 8192 _hash_bmap_t hash_select_mim_l3[] = 8193 { 8194 { BCM_HASH_FIELD_PROTOCOL, 0x0010 }, 8195 { BCM_HASH_FIELD_DSTL4, 0x0020 }, 8196 { BCM_HASH_FIELD_SRCL4, 0x0040 }, 8197 { BCM_HASH_FIELD_VLAN, 0x0080 }, 8198 { BCM_HASH_FIELD_IP4DST_LO, 0x0100 }, 8199 { BCM_HASH_FIELD_IP4DST_HI, 0x0200 }, 8200 { BCM_HASH_FIELD_IP4SRC_LO, 0x0400 }, 8201 { BCM_HASH_FIELD_IP4SRC_HI, 0x0800 } 8202 }; 8203 8204 _hash_bmap_t hash_select_mim_tunnel[] = 8205 { 8206 { BCM_HASH_FIELD_LOOKUP_ID_LO, 0x0010 }, 8207 { BCM_HASH_FIELD_LOOKUP_ID_HI, 0x0020 }, 8208 { BCM_HASH_FIELD_MACDA_LO, 0x0040 }, 8209 { BCM_HASH_FIELD_MACDA_MI, 0x0080 }, 8210 { BCM_HASH_FIELD_MACDA_HI, 0x0100 }, 8211 { BCM_HASH_FIELD_MACSA_LO, 0x0200 }, 8212 { BCM_HASH_FIELD_MACSA_MI, 0x0400 }, 8213 { BCM_HASH_FIELD_MACSA_HI, 0x0800 } 8214 }; 8215 8216 _hash_fieldselect_t hash_select_info_tr2[] = 8217 { 8218 { bcmSwitchHashIP4Field0, 8219 hash_select_ip4, COUNTOF(hash_select_ip4), 8220 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Af}, 8221 { bcmSwitchHashIP4Field1, 8222 hash_select_ip4, COUNTOF(hash_select_ip4), 8223 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Bf}, 8224 { bcmSwitchHashIP6Field0, 8225 hash_select_ip6, COUNTOF(hash_select_ip6), 8226 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Af}, 8227 { bcmSwitchHashIP6Field1, 8228 hash_select_ip6, COUNTOF(hash_select_ip6), 8229 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Bf}, 8230 { bcmSwitchHashL2Field0, 8231 hash_select_l2, COUNTOF(hash_select_l2), 8232 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Af}, 8233 { bcmSwitchHashL2Field1, 8234 hash_select_l2, COUNTOF(hash_select_l2), 8235 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Bf}, 8236 { bcmSwitchHashL2MPLSField0, 8237 hash_select_mpls_l2, COUNTOF(hash_select_mpls_l2), 8238 RTAG7_MPLS_L2_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L2_PAYLOAD_BITMAP_Af}, 8239 { bcmSwitchHashL2MPLSField1, 8240 hash_select_mpls_l2, COUNTOF(hash_select_mpls_l2), 8241 RTAG7_MPLS_L2_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L2_PAYLOAD_BITMAP_Bf}, 8242 { bcmSwitchHashL3MPLSField0, 8243 hash_select_mpls_l3, COUNTOF(hash_select_mpls_l3), 8244 RTAG7_MPLS_L3_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L3_PAYLOAD_BITMAP_Af}, 8245 { bcmSwitchHashL3MPLSField1, 8246 hash_select_mpls_l3, COUNTOF(hash_select_mpls_l3), 8247 RTAG7_MPLS_L3_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L3_PAYLOAD_BITMAP_Bf}, 8248 { bcmSwitchHashMPLSTunnelField0, 8249 hash_select_mpls_tunnel, COUNTOF(hash_select_mpls_tunnel), 8250 RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr, MPLS_OUTER_BITMAP_Af}, 8251 { bcmSwitchHashMPLSTunnelField1, 8252 hash_select_mpls_tunnel, COUNTOF(hash_select_mpls_tunnel), 8253 RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr, MPLS_OUTER_BITMAP_Bf}, 8254 { bcmSwitchHashMIMField0, 8255 hash_select_mim, COUNTOF(hash_select_mim), 8256 RTAG7_MIM_PAYLOAD_HASH_FIELD_BMAPr, MIM_PAYLOAD_BITMAP_Af}, 8257 { bcmSwitchHashMIMField1, 8258 hash_select_mim, COUNTOF(hash_select_mim), 8259 RTAG7_MIM_PAYLOAD_HASH_FIELD_BMAPr, MIM_PAYLOAD_BITMAP_Bf}, 8260 { bcmSwitchHashMIMTunnelField0, 8261 hash_select_mim_tunnel, COUNTOF(hash_select_mim_tunnel), 8262 RTAG7_MIM_OUTER_HASH_FIELD_BMAPr, MIM_OUTER_BITMAP_Af}, 8263 { bcmSwitchHashMIMTunnelField1, 8264 hash_select_mim_tunnel, COUNTOF(hash_select_mim_tunnel), 8265 RTAG7_MIM_OUTER_HASH_FIELD_BMAPr, MIM_OUTER_BITMAP_Bf}, 8266 { bcmSwitchHashHG2UnknownField0, 8267 hash_select_unknown, COUNTOF(hash_select_unknown), 8268 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Af}, 8269 { bcmSwitchHashHG2UnknownField1, 8270 hash_select_unknown, COUNTOF(hash_select_unknown), 8271 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Bf} 8272 }; 8273 #endif 8274 8275 #ifdef BCM_TRIDENT_SUPPORT 8276 _hash_bmap_t hash_select_td_common[] = 8277 { 8278 { BCM_HASH_FIELD_DSTMOD, 0x0001 }, 8279 { BCM_HASH_FIELD_DSTPORT, 0x0002 }, 8280 { BCM_HASH_FIELD_SRCMOD, 0x0004 }, 8281 { BCM_HASH_FIELD_SRCPORT, 0x0008 }, 8282 { BCM_HASH_FIELD_CNTAG_FLOW_ID, 0x1000 } 8283 }; 8284 8285 _hash_bmap_t hash_select_td_mpls_tunnel[] = 8286 { 8287 { BCM_HASH_MPLS_FIELD_3RD_LABEL, 0x0010 }, 8288 { BCM_HASH_MPLS_FIELD_IP4SRC_LO, 0x0020 }, 8289 { BCM_HASH_MPLS_FIELD_IP4SRC_HI, 0x0040 }, 8290 { BCM_HASH_MPLS_FIELD_IP4DST_LO, 0x0080 }, 8291 { BCM_HASH_MPLS_FIELD_IP4DST_HI, 0x0100 }, 8292 { BCM_HASH_MPLS_FIELD_LABELS_4MSB, 0x0200 }, 8293 { BCM_HASH_MPLS_FIELD_2ND_LABEL, 0x0400 }, 8294 { BCM_HASH_MPLS_FIELD_TOP_LABEL, 0x0800 }, 8295 }; 8296 8297 _hash_bmap_t hash_select_td_mpls_tunnel_5_labels[] = 8298 { 8299 { BCM_HASH_MPLS_FIELD_3RD_LABEL_4MSB_5TH_LABEL, 0x0010 }, 8300 { BCM_HASH_MPLS_FIELD_IP4SRC_IP6SRC_LO_4MSB_4TH_LABEL, 0x0020 }, 8301 { BCM_HASH_MPLS_FIELD_IP4SRC_IP6SRC_HI_4MSB, 0x0040 }, 8302 { BCM_HASH_MPLS_FIELD_IP4DST_IP6DST_LO_5TH_LABEL, 0x0080 }, 8303 { BCM_HASH_MPLS_FIELD_IP4DST_IP6DST_HI_4TH_LABEL, 0x0100 }, 8304 { BCM_HASH_MPLS_FIELD_LABELS_4MSB_3RD_LABEL, 0x0200 }, 8305 { BCM_HASH_MPLS_FIELD_2ND_LABEL, 0x0400 }, 8306 { BCM_HASH_MPLS_FIELD_TOP_LABEL, 0x0800 }, 8307 }; 8308 8309 _hash_bmap_t hash_select_td_fcoe[] = 8310 { 8311 { BCM_HASH_FCOE_FIELD_VLAN, 0x0010 }, 8312 { BCM_HASH_FCOE_FIELD_VIRTUAL_FABRIC_ID, 0x0020 }, 8313 { BCM_HASH_FCOE_FIELD_RESPONDER_EXCHANGE_ID, 0x0040 }, 8314 { BCM_HASH_FCOE_FIELD_ORIGINATOR_EXCHANGE_ID, 0x0080 }, 8315 { BCM_HASH_FCOE_FIELD_DST_ID_LO, 0x0100 }, 8316 { BCM_HASH_FCOE_FIELD_DST_ID_HI, 0x0200 }, 8317 { BCM_HASH_FCOE_FIELD_SRC_ID_LO, 0x0400 }, 8318 { BCM_HASH_FCOE_FIELD_SRC_ID_HI, 0x0800 }, 8319 }; 8320 8321 _hash_bmap_t hash_select_td_trill[] = 8322 { 8323 { BCM_HASH_TRILL_FIELD_VLAN, 0x0010 }, 8324 { BCM_HASH_TRILL_FIELD_ETHER_TYPE, 0x0020 }, 8325 { BCM_HASH_TRILL_FIELD_MACSA_LO, 0x0040 }, 8326 { BCM_HASH_TRILL_FIELD_MACSA_MI, 0x0080 }, 8327 { BCM_HASH_TRILL_FIELD_MACDA_LO, 0x0100 }, 8328 { BCM_HASH_TRILL_FIELD_MACDA_MI, 0x0200 }, 8329 { BCM_HASH_TRILL_FIELD_ING_RBRIDGE_NAME, 0x0400 }, 8330 { BCM_HASH_TRILL_FIELD_EGR_RBRIDGE_NAME, 0x0800 }, 8331 }; 8332 8333 _hash_fieldselect_t hash_select_info_td[] = 8334 { 8335 { bcmSwitchHashIP4Field0, 8336 hash_select_ip4, COUNTOF(hash_select_ip4), 8337 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Af}, 8338 { bcmSwitchHashIP4Field1, 8339 hash_select_ip4, COUNTOF(hash_select_ip4), 8340 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Bf}, 8341 { bcmSwitchHashIP4TcpUdpField0, 8342 hash_select_ip4, COUNTOF(hash_select_ip4), 8343 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_2r, IPV4_TCP_UDP_FIELD_BITMAP_Af}, 8344 { bcmSwitchHashIP4TcpUdpField1, 8345 hash_select_ip4, COUNTOF(hash_select_ip4), 8346 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_2r, IPV4_TCP_UDP_FIELD_BITMAP_Bf}, 8347 { bcmSwitchHashIP4TcpUdpPortsEqualField0, 8348 hash_select_ip4, COUNTOF(hash_select_ip4), 8349 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_1r, 8350 IPV4_TCP_UDP_SRC_EQ_DST_FIELD_BITMAP_Af}, 8351 { bcmSwitchHashIP4TcpUdpPortsEqualField1, 8352 hash_select_ip4, COUNTOF(hash_select_ip4), 8353 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_1r, 8354 IPV4_TCP_UDP_SRC_EQ_DST_FIELD_BITMAP_Bf}, 8355 { bcmSwitchHashIP6Field0, 8356 hash_select_ip6, COUNTOF(hash_select_ip6), 8357 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Af}, 8358 { bcmSwitchHashIP6Field1, 8359 hash_select_ip6, COUNTOF(hash_select_ip6), 8360 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Bf}, 8361 { bcmSwitchHashIP6TcpUdpField0, 8362 hash_select_ip6, COUNTOF(hash_select_ip6), 8363 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_2r, IPV6_TCP_UDP_FIELD_BITMAP_Af}, 8364 { bcmSwitchHashIP6TcpUdpField1, 8365 hash_select_ip6, COUNTOF(hash_select_ip6), 8366 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_2r, IPV6_TCP_UDP_FIELD_BITMAP_Bf}, 8367 { bcmSwitchHashIP6TcpUdpPortsEqualField0, 8368 hash_select_ip6, COUNTOF(hash_select_ip6), 8369 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_1r, 8370 IPV6_TCP_UDP_SRC_EQ_DST_FIELD_BITMAP_Af}, 8371 { bcmSwitchHashIP6TcpUdpPortsEqualField1, 8372 hash_select_ip6, COUNTOF(hash_select_ip6), 8373 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_1r, 8374 IPV6_TCP_UDP_SRC_EQ_DST_FIELD_BITMAP_Bf}, 8375 { bcmSwitchHashL2Field0, 8376 hash_select_l2, COUNTOF(hash_select_l2), 8377 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Af}, 8378 { bcmSwitchHashL2Field1, 8379 hash_select_l2, COUNTOF(hash_select_l2), 8380 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Bf}, 8381 { bcmSwitchHashL2MPLSField0, 8382 hash_select_mpls_l2, COUNTOF(hash_select_mpls_l2), 8383 RTAG7_MPLS_L2_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L2_PAYLOAD_BITMAP_Af}, 8384 { bcmSwitchHashL2MPLSField1, 8385 hash_select_mpls_l2, COUNTOF(hash_select_mpls_l2), 8386 RTAG7_MPLS_L2_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L2_PAYLOAD_BITMAP_Bf}, 8387 { bcmSwitchHashL3MPLSField0, 8388 hash_select_mpls_l3, COUNTOF(hash_select_mpls_l3), 8389 RTAG7_MPLS_L3_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L3_PAYLOAD_BITMAP_Af}, 8390 { bcmSwitchHashL3MPLSField1, 8391 hash_select_mpls_l3, COUNTOF(hash_select_mpls_l3), 8392 RTAG7_MPLS_L3_PAYLOAD_HASH_FIELD_BMAPr, MPLS_L3_PAYLOAD_BITMAP_Bf}, 8393 { bcmSwitchHashMPLSTunnelField0, 8394 hash_select_td_mpls_tunnel, COUNTOF(hash_select_td_mpls_tunnel), 8395 RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr, MPLS_OUTER_BITMAP_Af}, 8396 { bcmSwitchHashMPLSTunnelField1, 8397 hash_select_td_mpls_tunnel, COUNTOF(hash_select_td_mpls_tunnel), 8398 RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr, MPLS_OUTER_BITMAP_Bf}, 8399 { bcmSwitchHashMIMField0, 8400 hash_select_mim, COUNTOF(hash_select_mim), 8401 RTAG7_MIM_PAYLOAD_HASH_FIELD_BMAPr, MIM_PAYLOAD_BITMAP_Af}, 8402 { bcmSwitchHashMIMField1, 8403 hash_select_mim, COUNTOF(hash_select_mim), 8404 RTAG7_MIM_PAYLOAD_HASH_FIELD_BMAPr, MIM_PAYLOAD_BITMAP_Bf}, 8405 { bcmSwitchHashMIMTunnelField0, 8406 hash_select_mim_tunnel, COUNTOF(hash_select_mim_tunnel), 8407 RTAG7_MIM_OUTER_HASH_FIELD_BMAPr, MIM_OUTER_BITMAP_Af}, 8408 { bcmSwitchHashMIMTunnelField1, 8409 hash_select_mim_tunnel, COUNTOF(hash_select_mim_tunnel), 8410 RTAG7_MIM_OUTER_HASH_FIELD_BMAPr, MIM_OUTER_BITMAP_Bf}, 8411 { bcmSwitchHashFCOEField0, 8412 hash_select_td_fcoe, COUNTOF(hash_select_td_fcoe), 8413 RTAG7_FCOE_HASH_FIELD_BMAPr, FCOE_FIELD_BITMAP_Af}, 8414 { bcmSwitchHashFCOEField1, 8415 hash_select_td_fcoe, COUNTOF(hash_select_td_fcoe), 8416 RTAG7_FCOE_HASH_FIELD_BMAPr, FCOE_FIELD_BITMAP_Bf}, 8417 { bcmSwitchHashL2TrillField0, 8418 hash_select_l2, COUNTOF(hash_select_l2), 8419 RTAG7_TRILL_PAYLOAD_L2_HASH_FIELD_BMAPr, TRILL_PAYLOAD_L2_BITMAP_Af}, 8420 { bcmSwitchHashL2TrillField1, 8421 hash_select_l2, COUNTOF(hash_select_l2), 8422 RTAG7_TRILL_PAYLOAD_L2_HASH_FIELD_BMAPr, TRILL_PAYLOAD_L2_BITMAP_Bf}, 8423 { bcmSwitchHashL3TrillField0, 8424 hash_select_ip4, COUNTOF(hash_select_ip4), 8425 RTAG7_TRILL_PAYLOAD_L3_HASH_FIELD_BMAPr, TRILL_PAYLOAD_L3_BITMAP_Af}, 8426 { bcmSwitchHashL3TrillField1, 8427 hash_select_ip4, COUNTOF(hash_select_ip4), 8428 RTAG7_TRILL_PAYLOAD_L3_HASH_FIELD_BMAPr, TRILL_PAYLOAD_L3_BITMAP_Bf}, 8429 { bcmSwitchHashTrillTunnelField0, 8430 hash_select_td_trill, COUNTOF(hash_select_td_trill), 8431 RTAG7_TRILL_TUNNEL_HASH_FIELD_BMAPr, TRILL_TUNNEL_BITMAP_Af}, 8432 { bcmSwitchHashTrillTunnelField1, 8433 hash_select_td_trill, COUNTOF(hash_select_td_trill), 8434 RTAG7_TRILL_TUNNEL_HASH_FIELD_BMAPr, TRILL_TUNNEL_BITMAP_Bf}, 8435 { bcmSwitchHashL2VxlanField0, 8436 hash_select_l2, COUNTOF(hash_select_l2), 8437 RTAG7_VXLAN_PAYLOAD_L2_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L2_BITMAP_Af}, 8438 { bcmSwitchHashL2VxlanField1, 8439 hash_select_l2, COUNTOF(hash_select_l2), 8440 RTAG7_VXLAN_PAYLOAD_L2_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L2_BITMAP_Bf}, 8441 { bcmSwitchHashL3VxlanField0, 8442 hash_select_ip4, COUNTOF(hash_select_ip4), 8443 RTAG7_VXLAN_PAYLOAD_L3_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L3_BITMAP_Af}, 8444 { bcmSwitchHashL3VxlanField1, 8445 hash_select_ip4, COUNTOF(hash_select_ip4), 8446 RTAG7_VXLAN_PAYLOAD_L3_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L3_BITMAP_Bf}, 8447 { bcmSwitchHashL2L2GreField0, 8448 hash_select_l2, COUNTOF(hash_select_l2), 8449 RTAG7_L2GRE_PAYLOAD_L2_HASH_FIELD_BMAPr, L2GRE_PAYLOAD_L2_BITMAP_Af}, 8450 { bcmSwitchHashL2L2GreField1, 8451 hash_select_l2, COUNTOF(hash_select_l2), 8452 RTAG7_L2GRE_PAYLOAD_L2_HASH_FIELD_BMAPr, L2GRE_PAYLOAD_L2_BITMAP_Bf}, 8453 { bcmSwitchHashL3L2GreField0, 8454 hash_select_ip4, COUNTOF(hash_select_ip4), 8455 RTAG7_L2GRE_PAYLOAD_L3_HASH_FIELD_BMAPr, L2GRE_PAYLOAD_L3_BITMAP_Af}, 8456 { bcmSwitchHashL3L2GreField1, 8457 hash_select_ip4, COUNTOF(hash_select_ip4), 8458 RTAG7_L2GRE_PAYLOAD_L3_HASH_FIELD_BMAPr, L2GRE_PAYLOAD_L3_BITMAP_Bf}, 8459 { bcmSwitchHashHG2UnknownField0, 8460 hash_select_unknown, COUNTOF(hash_select_unknown), 8461 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Af}, 8462 { bcmSwitchHashHG2UnknownField1, 8463 hash_select_unknown, COUNTOF(hash_select_unknown), 8464 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Bf}, 8465 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 8466 || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 8467 { bcmSwitchHashL3L2MPLSField0, 8468 hash_select_ip4, COUNTOF(hash_select_ip4), 8469 RTAG7_MPLS_L2_PAYLOAD_L3_HASH_FIELD_BMAPr,MPLS_L2_PAYLOAD_L3_BITMAP_Af}, 8470 { bcmSwitchHashL3L2MPLSField1, 8471 hash_select_ip4, COUNTOF(hash_select_ip4), 8472 RTAG7_MPLS_L2_PAYLOAD_L3_HASH_FIELD_BMAPr,MPLS_L2_PAYLOAD_L3_BITMAP_Bf}, 8473 #endif 8474 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_KATANA2_SUPPORT) \ 8475 || defined(BCM_TOMAHAWK_SUPPORT) 8476 { bcmSwitchHashL3MiMField0, 8477 hash_select_mim_l3, COUNTOF(hash_select_mim_l3), 8478 RTAG7_MIM_PAYLOAD_L3_HASH_FIELD_BMAPr, MIM_PAYLOAD_L3_BITMAP_Af}, 8479 { bcmSwitchHashL3MiMField1, 8480 hash_select_mim_l3, COUNTOF(hash_select_mim_l3), 8481 RTAG7_MIM_PAYLOAD_L3_HASH_FIELD_BMAPr, MIM_PAYLOAD_L3_BITMAP_Bf}, 8482 #endif 8483 { 0 } 8484 }; 8485 8486 _hash_fieldselect_t hash_select_control_td[] = 8487 { 8488 { bcmSwitchHashTrillPayloadSelect0, 8489 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8490 RTAG7_HASH_CONTROLr, TRILL_PAYLOAD_HASH_SELECT_Af}, 8491 { bcmSwitchHashTrillPayloadSelect1, 8492 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8493 RTAG7_HASH_CONTROLr, TRILL_PAYLOAD_HASH_SELECT_Bf}, 8494 { bcmSwitchHashTrillTunnelSelect0, 8495 hash_field_tunnel_control, COUNTOF(hash_field_tunnel_control), 8496 RTAG7_HASH_CONTROLr, TRILL_TUNNEL_HASH_SELECT_Af}, 8497 { bcmSwitchHashTrillTunnelSelect1, 8498 hash_field_tunnel_control, COUNTOF(hash_field_tunnel_control), 8499 RTAG7_HASH_CONTROLr, TRILL_TUNNEL_HASH_SELECT_Bf}, 8500 { bcmSwitchHashIP6AddrCollapseSelect0, 8501 hash_field_ipv6_collapse_control, COUNTOF(hash_field_ipv6_collapse_control), 8502 RTAG7_HASH_CONTROLr, IPV6_COLLAPSED_ADDR_SELECT_Af}, 8503 { bcmSwitchHashIP6AddrCollapseSelect1, 8504 hash_field_ipv6_collapse_control, COUNTOF(hash_field_ipv6_collapse_control), 8505 RTAG7_HASH_CONTROLr, IPV6_COLLAPSED_ADDR_SELECT_Bf}, 8506 { bcmSwitchHashIPSecSelect0, 8507 hash_field_ipsec_control, COUNTOF(hash_field_ipsec_control), 8508 RTAG7_HASH_CONTROLr, IPSEC_HASH_SELECT_Af}, 8509 { bcmSwitchHashIPSecSelect1, 8510 hash_field_ipsec_control, COUNTOF(hash_field_ipsec_control), 8511 RTAG7_HASH_CONTROLr, IPSEC_HASH_SELECT_Bf}, 8512 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 8513 || defined(BCM_KATANA2_SUPPORT) 8514 { bcmSwitchHashL2MPLSPayloadSelect0, 8515 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8516 RTAG7_HASH_CONTROLr, MPLS_PAYLOAD_HASH_SELECT_Af}, 8517 { bcmSwitchHashL2MPLSPayloadSelect1, 8518 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8519 RTAG7_HASH_CONTROLr, MPLS_PAYLOAD_HASH_SELECT_Bf}, 8520 { bcmSwitchHashMiMPayloadSelect0, 8521 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8522 RTAG7_HASH_CONTROLr, MIM_PAYLOAD_HASH_SELECT_Af}, 8523 { bcmSwitchHashMiMPayloadSelect1, 8524 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8525 RTAG7_HASH_CONTROLr, MIM_PAYLOAD_HASH_SELECT_Bf}, 8526 #endif 8527 { 0 } 8528 }; 8529 8530 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 8531 _hash_fieldselect_t hash_select_control_td2[] = 8532 { 8533 { bcmSwitchHashVxlanPayloadSelect0, 8534 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8535 RTAG7_HASH_CONTROL_4r, VXLAN_PAYLOAD_HASH_SELECT_Af}, 8536 { bcmSwitchHashVxlanPayloadSelect1, 8537 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8538 RTAG7_HASH_CONTROL_4r, VXLAN_PAYLOAD_HASH_SELECT_Bf}, 8539 { bcmSwitchHashL2MPLSPayloadSelect0, 8540 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8541 RTAG7_HASH_CONTROL_2r, MPLS_PAYLOAD_HASH_SELECT_Af}, 8542 { bcmSwitchHashL2MPLSPayloadSelect1, 8543 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8544 RTAG7_HASH_CONTROL_2r, MPLS_PAYLOAD_HASH_SELECT_Bf}, 8545 { bcmSwitchHashMiMPayloadSelect0, 8546 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8547 RTAG7_HASH_CONTROL_2r, MIM_PAYLOAD_HASH_SELECT_Af}, 8548 { bcmSwitchHashMiMPayloadSelect1, 8549 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8550 RTAG7_HASH_CONTROL_2r, MIM_PAYLOAD_HASH_SELECT_Bf}, 8551 { 0 } 8552 }; 8553 #endif 8554 8555 _hash_fieldselect_t hash_select_control_kt2[] = 8556 { 8557 { bcmSwitchHashIP6AddrCollapseSelect0, 8558 hash_field_ipv6_collapse_control, COUNTOF(hash_field_ipv6_collapse_control), 8559 RTAG7_HASH_CONTROL_64r, IPV6_COLLAPSED_ADDR_SELECT_Af}, 8560 { bcmSwitchHashIP6AddrCollapseSelect1, 8561 hash_field_ipv6_collapse_control, COUNTOF(hash_field_ipv6_collapse_control), 8562 RTAG7_HASH_CONTROL_64r, IPV6_COLLAPSED_ADDR_SELECT_Bf}, 8563 { bcmSwitchHashL2MPLSPayloadSelect0, 8564 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8565 RTAG7_HASH_CONTROL_2_64r, MPLS_PAYLOAD_HASH_SELECT_Af}, 8566 { bcmSwitchHashL2MPLSPayloadSelect1, 8567 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8568 RTAG7_HASH_CONTROL_2_64r, MPLS_PAYLOAD_HASH_SELECT_Bf}, 8569 { bcmSwitchHashIPSecSelect0, 8570 hash_field_ipsec_control, COUNTOF(hash_field_ipsec_control), 8571 RTAG7_HASH_CONTROL_64r, IPSEC_HASH_SELECT_Af}, 8572 { bcmSwitchHashIPSecSelect1, 8573 hash_field_ipsec_control, COUNTOF(hash_field_ipsec_control), 8574 RTAG7_HASH_CONTROL_64r, IPSEC_HASH_SELECT_Bf}, 8575 { bcmSwitchHashMiMPayloadSelect0, 8576 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8577 RTAG7_HASH_CONTROL_2_64r, MIM_PAYLOAD_HASH_SELECT_Af}, 8578 { bcmSwitchHashMiMPayloadSelect1, 8579 hash_field_payload_control, COUNTOF(hash_field_payload_control), 8580 RTAG7_HASH_CONTROL_2_64r, MIM_PAYLOAD_HASH_SELECT_Bf}, 8581 { 0 } 8582 }; 8583 8584 #endif /* BCM_TRIDENT_SUPPORT */ 8585 8586 /* 8587 * Function: 8588 * _bcm_xgs3_fieldselect_set 8589 * Description: 8590 * Set the enhanced (aka rtag 7) field select settings. 8591 * Parameters: 8592 * unit - StrataSwitch PCI device unit number (driver internal). 8593 * type - The desired configuration parameter to set. 8594 * arg - BCM_HASH_CONTROL* 8595 * Returns: 8596 * BCM_E_xxxx 8597 */ 8598 8599 STATIC int 8600 _bcm_xgs3_fieldselect_set(int unit, 8601 bcm_switch_control_t type, int arg) 8602 { 8603 uint32 hash_control; 8604 int i, j, count, common_count; 8605 uint32 flags = 0; 8606 _hash_fieldselect_t *info, *base_info = hash_select_info; 8607 _hash_bmap_t *common_bmap; 8608 #if defined(BCM_TRIDENT_SUPPORT) 8609 int mpls_label_stack = 0; 8610 #endif 8611 #if defined(BCM_HURRICANE_SUPPORT) 8612 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 8613 return (BCM_E_UNAVAIL); 8614 } 8615 #endif 8616 8617 common_bmap = hash_select_common; 8618 common_count = COUNTOF(hash_select_common); 8619 count = COUNTOF(hash_select_info); 8620 #if defined(BCM_TRIUMPH2_SUPPORT) 8621 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 8622 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) || 8623 SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 8624 SOC_IS_KATANAX(unit)) { 8625 #ifdef BCM_TRIDENT_SUPPORT 8626 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 8627 SOC_IS_KATANAX(unit)) { 8628 common_bmap = hash_select_td_common; 8629 common_count = COUNTOF(hash_select_td_common); 8630 base_info = hash_select_info_td; 8631 count = COUNTOF(hash_select_info_td) - 1; 8632 } else 8633 #endif /* BCM_TRIDENT_SUPPORT */ 8634 { 8635 base_info = hash_select_info_tr2; 8636 count = COUNTOF(hash_select_info_tr2); 8637 } 8638 } 8639 #endif 8640 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_KATANA_SUPPORT) || \ 8641 defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 8642 if (soc_feature(unit, soc_feature_mpls_5_label_parsing)) { 8643 BCM_IF_ERROR_RETURN( 8644 bcm_esw_switch_control_get(unit, bcmSwitchHashMPLSUseLabelStack, 8645 &mpls_label_stack)); 8646 } 8647 #endif 8648 for (i = 0; i < count; i++) { 8649 info = base_info + i; 8650 if (info->type != type) { 8651 continue; 8652 } 8653 #ifdef BCM_TRIDENT_SUPPORT 8654 if (info->type == bcmSwitchHashMPLSTunnelField0 || 8655 info->type == bcmSwitchHashMPLSTunnelField1) { 8656 if (mpls_label_stack) { 8657 info->map = hash_select_td_mpls_tunnel_5_labels; 8658 if (SOC_REG_IS_VALID(unit,RTAG7_MPLS_OUTER_HASH_FIELD_BMAP_EXTENDEDr)) { 8659 info->reg = RTAG7_MPLS_OUTER_HASH_FIELD_BMAP_EXTENDEDr; 8660 info->field = 8661 (info->type == bcmSwitchHashMPLSTunnelField0) ? 8662 MPLS_OUTER_BITMAP_EXTENDED_Af : 8663 MPLS_OUTER_BITMAP_EXTENDED_Bf; 8664 } else { 8665 info->reg = RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr; 8666 info->field = (info->type == bcmSwitchHashMPLSTunnelField0) ? 8667 MPLS_OUTER_BITMAP_Af : MPLS_OUTER_BITMAP_Bf; 8668 } 8669 } else { 8670 info->map = hash_select_td_mpls_tunnel; 8671 info->reg = RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr; 8672 info->field = (info->type == bcmSwitchHashMPLSTunnelField0) ? 8673 MPLS_OUTER_BITMAP_Af : MPLS_OUTER_BITMAP_Bf; 8674 } 8675 } 8676 #endif 8677 for (j = 0; j < common_count; j++) { 8678 if (common_bmap[j].flag & arg) { 8679 flags |= common_bmap[j].hw_map; 8680 } 8681 } 8682 8683 for (j = 0; j < info->size; j++) { 8684 if (info->map[j].flag & arg) { 8685 flags |= info->map[j].hw_map; 8686 } 8687 } 8688 8689 SOC_IF_ERROR_RETURN 8690 (soc_reg32_get(unit, info->reg, 8691 REG_PORT_ANY, 0, &hash_control)); 8692 soc_reg_field_set(unit, info->reg, 8693 &hash_control, info->field, flags); 8694 SOC_IF_ERROR_RETURN 8695 (soc_reg32_set(unit, info->reg, REG_PORT_ANY, 0, hash_control)); 8696 } 8697 8698 return BCM_E_NONE; 8699 } 8700 8701 /* 8702 * Function: 8703 * _bcm_xgs3_fieldselect_get 8704 * Description: 8705 * Get the current enhanced (aka rtag 7) field select settings. 8706 * Parameters: 8707 * unit - StrataSwitch PCI device unit number (driver internal). 8708 * type - The desired configuration parameter to retrieve. 8709 * arg - Pointer to where the retrieved value will be written. 8710 * Returns: 8711 * BCM_E_xxxx 8712 */ 8713 8714 STATIC int 8715 _bcm_xgs3_fieldselect_get(int unit, 8716 bcm_switch_control_t type, int *arg) 8717 { 8718 uint32 hash_control; 8719 int i, j, count, common_count; 8720 uint32 flags; 8721 _hash_fieldselect_t *info, *base_info = hash_select_info; 8722 _hash_bmap_t *common_bmap; 8723 #if defined(BCM_TRIDENT_SUPPORT) 8724 int mpls_label_stack = 0; 8725 #endif 8726 #if defined(BCM_HURRICANE_SUPPORT) 8727 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 8728 return (BCM_E_UNAVAIL); 8729 } 8730 #endif 8731 8732 common_bmap = hash_select_common; 8733 common_count = COUNTOF(hash_select_common); 8734 count = COUNTOF(hash_select_info); 8735 #if defined(BCM_TRIUMPH2_SUPPORT) 8736 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 8737 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) || 8738 SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 8739 SOC_IS_KATANAX(unit)) { 8740 #ifdef BCM_TRIDENT_SUPPORT 8741 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 8742 SOC_IS_KATANAX(unit)) { 8743 common_bmap = hash_select_td_common; 8744 common_count = COUNTOF(hash_select_td_common); 8745 base_info = hash_select_info_td; 8746 count = COUNTOF(hash_select_info_td) - 1; 8747 } else 8748 #endif /* BCM_TRIDENT_SUPPORT */ 8749 { 8750 base_info = hash_select_info_tr2; 8751 count = COUNTOF(hash_select_info_tr2); 8752 } 8753 } 8754 #endif 8755 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_KATANA_SUPPORT) || \ 8756 defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 8757 if (soc_feature(unit, soc_feature_mpls_5_label_parsing)) { 8758 BCM_IF_ERROR_RETURN( 8759 bcm_esw_switch_control_get(unit, bcmSwitchHashMPLSUseLabelStack, 8760 &mpls_label_stack)); 8761 } 8762 #endif 8763 for (i = 0; i < count; i++) { 8764 info = base_info + i; 8765 if (info->type != type) { 8766 continue; 8767 } 8768 #ifdef BCM_TRIDENT_SUPPORT 8769 if (info->type == bcmSwitchHashMPLSTunnelField0 || 8770 info->type == bcmSwitchHashMPLSTunnelField1) { 8771 if (mpls_label_stack) { 8772 info->map = hash_select_td_mpls_tunnel_5_labels; 8773 if (SOC_REG_IS_VALID(unit,RTAG7_MPLS_OUTER_HASH_FIELD_BMAP_EXTENDEDr)) { 8774 info->reg = RTAG7_MPLS_OUTER_HASH_FIELD_BMAP_EXTENDEDr; 8775 info->field = 8776 (info->type == bcmSwitchHashMPLSTunnelField0) ? 8777 MPLS_OUTER_BITMAP_EXTENDED_Af : 8778 MPLS_OUTER_BITMAP_EXTENDED_Bf; 8779 } else { 8780 info->reg = RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr; 8781 info->field = (info->type == bcmSwitchHashMPLSTunnelField0) ? 8782 MPLS_OUTER_BITMAP_Af : MPLS_OUTER_BITMAP_Bf; 8783 } 8784 } else { 8785 info->map = hash_select_td_mpls_tunnel; 8786 info->reg = RTAG7_MPLS_OUTER_HASH_FIELD_BMAPr; 8787 info->field = (info->type == bcmSwitchHashMPLSTunnelField0) ? 8788 MPLS_OUTER_BITMAP_Af : MPLS_OUTER_BITMAP_Bf; 8789 } 8790 } 8791 #endif 8792 SOC_IF_ERROR_RETURN 8793 (soc_reg32_get(unit, info->reg, 8794 REG_PORT_ANY, 0, &hash_control)); 8795 flags = soc_reg_field_get(unit, info->reg, 8796 hash_control, info->field); 8797 *arg = 0; 8798 for (j = 0; j < common_count; j++) { 8799 if (common_bmap[j].hw_map & flags) { 8800 *arg |= common_bmap[j].flag; 8801 } 8802 } 8803 8804 for (j = 0; j < info->size; j++) { 8805 if (info->map[j].hw_map & flags) { 8806 *arg |= info->map[j].flag; 8807 } 8808 } 8809 } 8810 8811 return BCM_E_NONE; 8812 } 8813 8814 8815 /* 8816 * Function: 8817 * _bcm_xgs3_field_control_get 8818 * Description: 8819 * Set RTAG7 field controls for hash blocks. 8820 * Parameters: 8821 * unit - unit no. 8822 * type - switch control enum type. 8823 * arg - BCM_HASH_CONTROL* 8824 * Returns: 8825 * BCM_E_xxxx 8826 */ 8827 8828 STATIC int 8829 _bcm_xgs3_field_control_get(int unit, 8830 bcm_switch_control_t type, int *arg) 8831 { 8832 uint64 hash_control; 8833 uint32 val; 8834 int cnt, i; 8835 uint32 count = 0; 8836 _hash_fieldselect_t *base_info = NULL, *info; 8837 8838 #ifdef BCM_TRIDENT_SUPPORT 8839 if ((SOC_IS_KATANA2(unit)) || ((SOC_IS_APACHE(unit)) && 8840 (type == bcmSwitchHashL2MPLSPayloadSelect0 || 8841 type == bcmSwitchHashL2MPLSPayloadSelect1 || 8842 type == bcmSwitchHashMiMPayloadSelect0 || 8843 type == bcmSwitchHashMiMPayloadSelect1))) { 8844 base_info = hash_select_control_kt2; 8845 count = COUNTOF(hash_select_control_kt2) - 1; 8846 } else 8847 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 8848 if ((SOC_IS_TD2_TT2(unit) && !SOC_IS_TOMAHAWK3(unit)) && 8849 (type == bcmSwitchHashVxlanPayloadSelect0 || 8850 type == bcmSwitchHashVxlanPayloadSelect1 || 8851 type == bcmSwitchHashL2MPLSPayloadSelect0 || 8852 type == bcmSwitchHashL2MPLSPayloadSelect1 || 8853 type == bcmSwitchHashMiMPayloadSelect0 || 8854 type == bcmSwitchHashMiMPayloadSelect1 8855 )) { 8856 base_info = hash_select_control_td2; 8857 count = COUNTOF(hash_select_control_td2) - 1; 8858 } else 8859 #endif 8860 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 8861 SOC_IS_KATANA(unit)) { 8862 base_info = hash_select_control_td; 8863 count = COUNTOF(hash_select_control_td) - 1; 8864 } 8865 #endif /* BCM_TRIDENT_SUPPORT */ 8866 8867 if (0 == count) { 8868 return BCM_E_UNAVAIL; 8869 } 8870 8871 for (i = 0; i < count; i++) 8872 { 8873 info = base_info + i; 8874 if (info->type != type) { 8875 continue; 8876 } 8877 8878 SOC_IF_ERROR_RETURN 8879 (soc_reg_get(unit, info->reg, 8880 REG_PORT_ANY, 0, &hash_control)); 8881 8882 val = soc_reg64_field32_get(unit, info->reg, 8883 hash_control, info->field); 8884 8885 for (cnt = 0; cnt < info->size; cnt++) { 8886 8887 if (info->map[cnt].hw_map == val) { 8888 break; 8889 } 8890 } 8891 if (info->size == cnt) { 8892 return BCM_E_INTERNAL; 8893 } 8894 8895 *arg = info->map[cnt].flag; 8896 8897 } 8898 8899 return BCM_E_NONE; 8900 } 8901 8902 /* 8903 * Function: 8904 * _bcm_xgs3_field_control_set 8905 * Description: 8906 * Get RTAG7 field controls for hash blocks. 8907 * Parameters: 8908 * unit - unit no. 8909 * type - switch control enum type. 8910 * *arg - BCM_HASH_CONTROL* 8911 * Returns: 8912 * BCM_E_xxxx 8913 */ 8914 8915 STATIC int 8916 _bcm_xgs3_field_control_set(int unit, 8917 bcm_switch_control_t type, int arg) 8918 { 8919 uint64 hash_control; 8920 int cnt, i; 8921 uint32 count = 0; 8922 _hash_fieldselect_t *base_info = NULL, *info; 8923 8924 #ifdef BCM_TRIDENT_SUPPORT 8925 if ((SOC_IS_KATANA2(unit)) || ((SOC_IS_APACHE(unit)) && 8926 (type == bcmSwitchHashL2MPLSPayloadSelect0 || 8927 type == bcmSwitchHashL2MPLSPayloadSelect1 || 8928 type == bcmSwitchHashMiMPayloadSelect0 || 8929 type == bcmSwitchHashMiMPayloadSelect1))) { 8930 base_info = hash_select_control_kt2; 8931 count = COUNTOF(hash_select_control_kt2) - 1; 8932 } else 8933 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 8934 if ((SOC_IS_TD2_TT2(unit) && !SOC_IS_TOMAHAWK3(unit)) && 8935 (type == bcmSwitchHashVxlanPayloadSelect0 || 8936 type == bcmSwitchHashVxlanPayloadSelect1 || 8937 type == bcmSwitchHashL2MPLSPayloadSelect0 || 8938 type == bcmSwitchHashL2MPLSPayloadSelect1 || 8939 type == bcmSwitchHashMiMPayloadSelect0 || 8940 type == bcmSwitchHashMiMPayloadSelect1 8941 )) { 8942 base_info = hash_select_control_td2; 8943 count = COUNTOF(hash_select_control_td2) - 1; 8944 } else 8945 #endif 8946 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 8947 SOC_IS_KATANA(unit)) { 8948 base_info = hash_select_control_td; 8949 count = COUNTOF(hash_select_control_td) - 1; 8950 } 8951 #endif /* BCM_TRIDENT_SUPPORT */ 8952 8953 if (0 == count) { 8954 return BCM_E_UNAVAIL; 8955 } 8956 8957 for (i = 0; i < count; i++) 8958 { 8959 info = base_info + i; 8960 if (info->type != type) { 8961 continue; 8962 } 8963 8964 for (cnt = 0; cnt < info->size; cnt++) { 8965 if (info->map[cnt].flag == arg) { 8966 break; 8967 } 8968 } 8969 if (info->size == cnt) { 8970 return BCM_E_PARAM; 8971 } 8972 8973 SOC_IF_ERROR_RETURN 8974 (soc_reg_get(unit, info->reg, 8975 REG_PORT_ANY, 0, &hash_control)); 8976 soc_reg64_field32_set(unit, info->reg, 8977 &hash_control, info->field, info->map[cnt].hw_map); 8978 SOC_IF_ERROR_RETURN 8979 (soc_reg_set(unit, info->reg, REG_PORT_ANY, 0, hash_control)); 8980 } 8981 8982 return BCM_E_NONE; 8983 } 8984 8985 /* 8986 * Enhanced hash bit selection/offset helper function 8987 */ 8988 8989 #if defined(BCM_TRIUMPH3_SUPPORT) 8990 STATIC int 8991 _bcm_tr3_hash_offset(int unit, bcm_port_t port, bcm_switch_control_t type, 8992 hash_offset_info_t *info) 8993 { 8994 8995 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 8996 int index = -1; 8997 #endif 8998 8999 /* The RTAG7 port index is of 0 .. 319. The indexes are arranged with 0 - 9000 * 255 lport followed by physical ports index 0 .. 63 9001 * 9002 * For td2p, the index is got from PORT_TAB.RTAG7_PORT_PROFILE_INDEX or from 9003 * LPORT_PROFILE_TABLE.RTAG7_PORT_PROFILE_INDEX 9004 * 9005 * The index field will be ignored for LPORTs. 9006 */ 9007 if (BCM_GPORT_IS_SET(port)) { 9008 info->idx = -1; 9009 } else { 9010 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 9011 if(soc_feature(unit, soc_feature_separate_ing_lport_rtag7_profile)) { 9012 BCM_IF_ERROR_RETURN 9013 (_bcm_esw_port_tab_get(unit, port, RTAG7_PORT_PROFILE_INDEXf, &index)); 9014 info->idx = index; 9015 } else 9016 #endif 9017 { 9018 info->idx = SOC_IS_TOMAHAWK3(unit) ? port : port + soc_mem_index_count(unit, LPORT_TABm); 9019 } 9020 } 9021 9022 switch (type) { 9023 case bcmSwitchTrunkHashSet0UnicastOffset: 9024 info->hash_concat = 0; 9025 info->sub_f = SUB_SEL_TRUNK_UCf; 9026 info->offset_f = OFFSET_TRUNK_UCf; 9027 info->concat_f = CONCATENATE_HASH_FIELDS_TRUNK_UCf; 9028 info->regmem = RTAG7_PORT_BASED_HASHm; 9029 break; 9030 case bcmSwitchTrunkHashSet0NonUnicastOffset: 9031 info->hash_concat = 0; 9032 info->sub_f = SUB_SEL_TRUNK_NONUCf; 9033 info->offset_f = OFFSET_TRUNK_NONUCf; 9034 info->concat_f = CONCATENATE_HASH_FIELDS_TRUNK_NONUCf; 9035 info->regmem = RTAG7_PORT_BASED_HASHm; 9036 break; 9037 case bcmSwitchTrunkFailoverHashOffset: 9038 info->hash_concat = 0; 9039 info->sub_f = SUB_SEL_PLFSf; 9040 info->offset_f = OFFSET_PLFSf; 9041 info->concat_f = CONCATENATE_HASH_FIELDS_PLFSf; 9042 info->regmem = RTAG7_PORT_BASED_HASHm; 9043 break; 9044 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 9045 info->hash_concat = 0; 9046 info->sub_f = SUB_SEL_HG_TRUNK_UCf; 9047 info->offset_f = OFFSET_HG_TRUNK_UCf; 9048 info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNK_UCf; 9049 info->regmem = RTAG7_PORT_BASED_HASHm; 9050 break; 9051 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 9052 info->hash_concat = 0; 9053 info->sub_f = SUB_SEL_HG_TRUNK_NONUCf; 9054 info->offset_f = OFFSET_HG_TRUNK_NONUCf; 9055 info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNK_NONUCf; 9056 info->regmem = RTAG7_PORT_BASED_HASHm; 9057 break; 9058 case bcmSwitchFabricTrunkFailoverHashOffset: 9059 info->hash_concat = 0; 9060 info->sub_f = SUB_SEL_HG_TRUNK_FAILOVERf; 9061 info->offset_f = OFFSET_HG_TRUNK_FAILOVERf; 9062 info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNK_FAILOVERf; 9063 info->regmem = RTAG7_PORT_BASED_HASHm; 9064 break; 9065 case bcmSwitchFabricTrunkDynamicHashOffset: 9066 if (soc_feature(unit, soc_feature_hg_dlb)) { 9067 info->hash_concat = 0; 9068 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized) && 9069 !soc_feature(unit, soc_feature_td3_dlb)) { 9070 info->sub_f = SUB_SEL_DLB_HGT_LAGf; 9071 info->offset_f = OFFSET_DLB_HGT_LAGf; 9072 info->concat_f = CONCATENATE_HASH_FIELDS_DLB_HGT_LAGf; 9073 info->regmem = RTAG7_PORT_BASED_HASHm; 9074 } else { 9075 info->sub_f = SUB_SEL_DLB_HGTf; 9076 info->offset_f = OFFSET_DLB_HGTf; 9077 info->concat_f = CONCATENATE_HASH_FIELDS_DLB_HGTf; 9078 info->regmem = RTAG7_PORT_BASED_HASHm; 9079 } 9080 } else { 9081 return BCM_E_UNAVAIL; 9082 } 9083 break; 9084 case bcmSwitchTrunkDynamicHashOffset: 9085 if (soc_feature(unit, soc_feature_lag_dlb)) { 9086 info->hash_concat = 0; 9087 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized) && 9088 !soc_feature(unit, soc_feature_td3_dlb)) { 9089 info->sub_f = SUB_SEL_DLB_HGT_LAGf; 9090 info->offset_f = OFFSET_DLB_HGT_LAGf; 9091 info->concat_f = CONCATENATE_HASH_FIELDS_DLB_HGT_LAGf; 9092 info->regmem = RTAG7_PORT_BASED_HASHm; 9093 } else { 9094 info->sub_f = SUB_SEL_DLB_LAGf; 9095 info->offset_f = OFFSET_DLB_LAGf; 9096 info->concat_f = CONCATENATE_HASH_FIELDS_DLB_LAGf; 9097 info->regmem = RTAG7_PORT_BASED_HASHm; 9098 } 9099 } else { 9100 return BCM_E_UNAVAIL; 9101 } 9102 break; 9103 case bcmSwitchEcmpDynamicHashOffset: 9104 if (soc_feature(unit, soc_feature_ecmp_dlb)) { 9105 info->hash_concat = 0; 9106 info->sub_f = SUB_SEL_DLB_ECMPf; 9107 info->offset_f = OFFSET_DLB_ECMPf; 9108 info->concat_f = CONCATENATE_HASH_FIELDS_DLB_ECMPf; 9109 info->regmem = RTAG7_PORT_BASED_HASHm; 9110 } else { 9111 return BCM_E_UNAVAIL; 9112 } 9113 break; 9114 case bcmSwitchFabricTrunkResilientHashOffset: 9115 if (soc_feature(unit, soc_feature_hg_resilient_hash)) { 9116 info->hash_concat = 0; 9117 info->sub_f = SUB_SEL_RH_HGTf; 9118 info->offset_f = OFFSET_RH_HGTf; 9119 info->concat_f = CONCATENATE_HASH_FIELDS_RH_HGTf; 9120 info->regmem = RTAG7_PORT_BASED_HASHm; 9121 } else { 9122 return BCM_E_UNAVAIL; 9123 } 9124 break; 9125 case bcmSwitchTrunkResilientHashOffset: 9126 if (soc_feature(unit, soc_feature_lag_resilient_hash)) { 9127 info->hash_concat = 0; 9128 info->sub_f = SUB_SEL_RH_LAGf; 9129 info->offset_f = OFFSET_RH_LAGf; 9130 info->concat_f = CONCATENATE_HASH_FIELDS_RH_LAGf; 9131 info->regmem = RTAG7_PORT_BASED_HASHm; 9132 } else { 9133 return BCM_E_UNAVAIL; 9134 } 9135 break; 9136 case bcmSwitchEcmpResilientHashOffset: 9137 if (soc_feature(unit, soc_feature_ecmp_resilient_hash) || 9138 soc_feature(unit, soc_feature_ecmp_resilient_hash_optimized)) { 9139 info->hash_concat = 0; 9140 info->sub_f = SUB_SEL_RH_ECMPf; 9141 info->offset_f = OFFSET_RH_ECMPf; 9142 info->concat_f = CONCATENATE_HASH_FIELDS_RH_ECMPf; 9143 info->regmem = RTAG7_PORT_BASED_HASHm; 9144 } else { 9145 return BCM_E_UNAVAIL; 9146 } 9147 break; 9148 case bcmSwitchECMPVxlanHashOffset: 9149 if ((SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || 9150 (SOC_IS_TRIDENT3X(unit))) && (!SOC_IS_TOMAHAWK3(unit))) { 9151 info->hash_concat = 0; 9152 info->sub_f = SUB_SEL_VXLAN_ECMPf; 9153 info->offset_f = OFFSET_VXLAN_ECMPf; 9154 info->concat_f = CONCATENATE_HASH_FIELDS_VXLAN_ECMPf; 9155 info->regmem = RTAG7_PORT_BASED_HASHm; 9156 } else { 9157 return BCM_E_UNAVAIL; 9158 } 9159 break; 9160 case bcmSwitchECMPUnderlayVxlanHashOffset: 9161 if (SOC_IS_TOMAHAWKX(unit) && (!SOC_IS_TOMAHAWK3(unit))) { 9162 info->hash_concat = 0; 9163 info->sub_f = SUB_SEL_VXLAN_ECMP_LEVEL2f; 9164 info->offset_f = OFFSET_VXLAN_ECMP_LEVEL2f; 9165 info->concat_f = CONCATENATE_HASH_FIELDS_VXLAN_ECMP_LEVEL2f; 9166 info->regmem = RTAG7_PORT_BASED_HASHm; 9167 } else { 9168 return BCM_E_UNAVAIL; 9169 } 9170 break; 9171 case bcmSwitchECMPL2GreHashOffset: 9172 if (SOC_IS_KATANA2(unit)) { 9173 return BCM_E_UNAVAIL; 9174 } else { 9175 info->hash_concat = 0; 9176 info->sub_f = SUB_SEL_L2GRE_ECMPf; 9177 info->offset_f = OFFSET_L2GRE_ECMPf; 9178 info->concat_f = CONCATENATE_HASH_FIELDS_L2GRE_ECMPf; 9179 info->regmem = RTAG7_PORT_BASED_HASHm; 9180 } 9181 break; 9182 case bcmSwitchECMPUnderlayL2GreHashOffset: 9183 if (SOC_IS_TOMAHAWKX(unit)) { 9184 info->hash_concat = 0; 9185 info->sub_f = SUB_SEL_L2GRE_ECMP_LEVEL2f; 9186 info->offset_f = OFFSET_L2GRE_ECMP_LEVEL2f; 9187 info->concat_f = CONCATENATE_HASH_FIELDS_L2GRE_ECMP_LEVEL2f; 9188 info->regmem = RTAG7_PORT_BASED_HASHm; 9189 } else { 9190 return BCM_E_UNAVAIL; 9191 } 9192 break; 9193 case bcmSwitchECMPTrillHashOffset: 9194 if (SOC_IS_KATANA2(unit) || SOC_IS_TOMAHAWK3(unit)) { 9195 return BCM_E_UNAVAIL; 9196 } else { 9197 info->hash_concat = 0; 9198 info->sub_f = SUB_SEL_TRILL_ECMPf; 9199 info->offset_f = OFFSET_TRILL_ECMPf; 9200 info->concat_f = CONCATENATE_HASH_FIELDS_TRILL_ECMPf; 9201 info->regmem = RTAG7_PORT_BASED_HASHm; 9202 } 9203 break; 9204 case bcmSwitchECMPUnderlayTrillHashOffset: 9205 if (SOC_IS_TOMAHAWKX(unit) && (!SOC_IS_TOMAHAWK3(unit))) { 9206 info->hash_concat = 0; 9207 info->sub_f = SUB_SEL_TRILL_ECMP_LEVEL2f; 9208 info->offset_f = OFFSET_TRILL_ECMP_LEVEL2f; 9209 info->concat_f = CONCATENATE_HASH_FIELDS_TRILL_ECMP_LEVEL2f; 9210 info->regmem = RTAG7_PORT_BASED_HASHm; 9211 } else { 9212 return BCM_E_UNAVAIL; 9213 } 9214 break; 9215 case bcmSwitchECMPMplsHashOffset: 9216 info->hash_concat = 0; 9217 info->sub_f = SUB_SEL_MPLS_ECMPf; 9218 info->offset_f = OFFSET_MPLS_ECMPf; 9219 info->concat_f = CONCATENATE_HASH_FIELDS_MPLS_ECMPf; 9220 info->regmem = RTAG7_PORT_BASED_HASHm; 9221 break; 9222 case bcmSwitchVirtualPortDynamicHashOffset: 9223 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || 9224 SOC_IS_TRIDENT3X(unit)) { 9225 info->hash_concat = 0; 9226 info->sub_f = SUB_SEL_VPLAGf; 9227 info->offset_f = OFFSET_VPLAGf; 9228 info->concat_f = CONCATENATE_HASH_FIELDS_VPLAGf; 9229 info->regmem = RTAG7_PORT_BASED_HASHm; 9230 } else { 9231 return BCM_E_UNAVAIL; 9232 } 9233 break; 9234 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 9235 if (SOC_IS_TOMAHAWKX(unit)) { 9236 info->hash_concat = 0; 9237 info->sub_f = SUB_SEL_VPLAG_LEVEL2f; 9238 info->offset_f = OFFSET_VPLAG_LEVEL2f; 9239 info->concat_f = CONCATENATE_HASH_FIELDS_VPLAG_LEVEL2f; 9240 info->regmem = RTAG7_PORT_BASED_HASHm; 9241 } else { 9242 return BCM_E_UNAVAIL; 9243 } 9244 break; 9245 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 9246 info->hash_concat = 0; 9247 info->sub_f = SUB_SEL_LBID_UCf; 9248 info->offset_f = OFFSET_LBID_UCf; 9249 info->concat_f = CONCATENATE_HASH_FIELDS_LBID_UCf; 9250 info->regmem = RTAG7_PORT_BASED_HASHm; 9251 break; 9252 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 9253 info->hash_concat = 0; 9254 info->sub_f = SUB_SEL_LBID_NONUCf; 9255 info->offset_f = OFFSET_LBID_NONUCf; 9256 info->concat_f = CONCATENATE_HASH_FIELDS_LBID_NONUCf; 9257 info->regmem = RTAG7_PORT_BASED_HASHm; 9258 break; 9259 case bcmSwitchECMPHashSet0Offset: 9260 info->hash_concat = 0; 9261 info->sub_f = SUB_SEL_ECMPf; 9262 info->offset_f = OFFSET_ECMPf; 9263 info->concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 9264 info->regmem = RTAG7_PORT_BASED_HASHm; 9265 break; 9266 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 9267 case bcmSwitchECMPOverlayHashOffset: 9268 if (soc_feature(unit, soc_feature_riot) || 9269 soc_feature(unit, soc_feature_multi_level_ecmp)) { 9270 info->hash_concat = 0; 9271 info->sub_f = SUB_SEL_ECMP_LEVEL1f; 9272 info->offset_f = OFFSET_ECMP_LEVEL1f; 9273 info->concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL1f; 9274 info->regmem = RTAG7_PORT_BASED_HASHm; 9275 break; 9276 } else { 9277 return BCM_E_UNAVAIL; 9278 } 9279 #endif 9280 case bcmSwitchECMPUnderlayHashSet0Offset: 9281 if (SOC_IS_TOMAHAWKX(unit)) { 9282 info->hash_concat = 0; 9283 info->sub_f = SUB_SEL_ECMP_LEVEL2f; 9284 info->offset_f = OFFSET_ECMP_LEVEL2f; 9285 info->concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL2f; 9286 info->regmem = RTAG7_PORT_BASED_HASHm; 9287 } else { 9288 return BCM_E_UNAVAIL; 9289 } 9290 break; 9291 case bcmSwitchEntropyHashSet0Offset: 9292 info->hash_concat = 0; /* 1 required for mpls label(20 bits) 9293 * and customer should guarantee it. 9294 */ 9295 info->sub_f = SUB_SEL_ENTROPY_LABELf; 9296 info->offset_f = OFFSET_ENTROPY_LABELf; 9297 info->concat_f = CONCATENATE_HASH_FIELDS_ENTROPY_LABELf; 9298 info->regmem = RTAG7_PORT_BASED_HASHm; 9299 break; 9300 default: 9301 return BCM_E_UNAVAIL; 9302 } 9303 return BCM_E_NONE; 9304 } 9305 9306 9307 STATIC int 9308 _bcm_tr3_symmetric_hash_control_set(int unit, int arg) 9309 { 9310 uint64 hash_control; 9311 uint32 valid_bit_mask, val; 9312 soc_reg_t rtag7_hash_ctrl; 9313 9314 valid_bit_mask = (BCM_SYMMETRIC_HASH_0_IP4_ENABLE | 9315 BCM_SYMMETRIC_HASH_1_IP4_ENABLE | 9316 BCM_SYMMETRIC_HASH_0_IP6_ENABLE | 9317 BCM_SYMMETRIC_HASH_1_IP6_ENABLE | 9318 BCM_SYMMETRIC_HASH_0_SUPPRESS_UNIDIR_FIELD_ENABLE | 9319 BCM_SYMMETRIC_HASH_1_SUPPRESS_UNIDIR_FIELD_ENABLE | 9320 BCM_SYMMETRIC_HASH_0_FCOE_ENABLE | 9321 BCM_SYMMETRIC_HASH_1_FCOE_ENABLE); 9322 9323 if (arg & (~valid_bit_mask)) { 9324 return BCM_E_PARAM; 9325 } 9326 9327 rtag7_hash_ctrl = SOC_IS_KATANA2(unit) ? \ 9328 RTAG7_HASH_CONTROL_64r : RTAG7_HASH_CONTROLr; 9329 9330 BCM_IF_ERROR_RETURN( 9331 soc_reg_get(unit, rtag7_hash_ctrl, REG_PORT_ANY, 0, 9332 &hash_control)); 9333 9334 val = (arg & BCM_SYMMETRIC_HASH_0_IP4_ENABLE ) ? 1 : 0; 9335 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9336 SYMMETRIC_HASH_IPV4_Af, val); 9337 9338 val = (arg & BCM_SYMMETRIC_HASH_1_IP4_ENABLE) ? 1 : 0; 9339 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9340 SYMMETRIC_HASH_IPV4_Bf, val); 9341 9342 val = (arg & BCM_SYMMETRIC_HASH_0_IP6_ENABLE) ? 1 : 0; 9343 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9344 SYMMETRIC_HASH_IPV6_Af, val); 9345 9346 val = (arg & BCM_SYMMETRIC_HASH_1_IP6_ENABLE) ? 1 : 0; 9347 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9348 SYMMETRIC_HASH_IPV6_Bf, val); 9349 9350 val = (arg & BCM_SYMMETRIC_HASH_0_SUPPRESS_UNIDIR_FIELD_ENABLE) ? 1 : 0; 9351 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9352 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Af, val); 9353 9354 val = (arg & BCM_SYMMETRIC_HASH_1_SUPPRESS_UNIDIR_FIELD_ENABLE) ? 1 : 0; 9355 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9356 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Bf, val); 9357 9358 if (SOC_REG_FIELD_VALID(unit, rtag7_hash_ctrl, SYMMETRIC_HASH_FCOE_Af)) { 9359 val = (arg & BCM_SYMMETRIC_HASH_0_FCOE_ENABLE) ? 1 : 0; 9360 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9361 SYMMETRIC_HASH_FCOE_Af, val); 9362 9363 val = (arg & BCM_SYMMETRIC_HASH_1_FCOE_ENABLE) ? 1 : 0; 9364 soc_reg64_field32_set(unit, rtag7_hash_ctrl, &hash_control, 9365 SYMMETRIC_HASH_FCOE_Bf, val); 9366 } else { 9367 /* 9368 * The fields SYMMETRIC_HASH_FCOE_Af and SYMMETRIC_HASH_FCOE_Bf 9369 * are invalid for the unit. Appropriate error code should be 9370 * returned if the request is to set either of them. 9371 */ 9372 if ((arg & BCM_SYMMETRIC_HASH_0_FCOE_ENABLE) || 9373 (arg & BCM_SYMMETRIC_HASH_1_FCOE_ENABLE)) { 9374 return BCM_E_PARAM; 9375 } 9376 } 9377 9378 BCM_IF_ERROR_RETURN( 9379 soc_reg_set(unit, rtag7_hash_ctrl, REG_PORT_ANY, 0, 9380 hash_control)); 9381 return BCM_E_NONE; 9382 } 9383 9384 9385 STATIC int 9386 _bcm_tr3_symmetric_hash_control_get(int unit, int *arg) 9387 { 9388 uint64 hash_control; 9389 uint32 val; 9390 soc_reg_t rtag7_hash_ctrl; 9391 9392 9393 rtag7_hash_ctrl = SOC_IS_KATANA2(unit) ? \ 9394 RTAG7_HASH_CONTROL_64r : RTAG7_HASH_CONTROLr; 9395 9396 *arg = 0; 9397 9398 BCM_IF_ERROR_RETURN( 9399 soc_reg_get(unit, rtag7_hash_ctrl, REG_PORT_ANY, 0, 9400 &hash_control)); 9401 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9402 SYMMETRIC_HASH_IPV4_Af); 9403 if (val) *arg |= BCM_SYMMETRIC_HASH_0_IP4_ENABLE; 9404 9405 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9406 SYMMETRIC_HASH_IPV4_Bf); 9407 if (val) *arg |= BCM_SYMMETRIC_HASH_1_IP4_ENABLE; 9408 9409 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9410 SYMMETRIC_HASH_IPV6_Af); 9411 if (val) *arg |= BCM_SYMMETRIC_HASH_0_IP6_ENABLE; 9412 9413 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9414 SYMMETRIC_HASH_IPV6_Bf); 9415 if (val) *arg |= BCM_SYMMETRIC_HASH_1_IP6_ENABLE; 9416 9417 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9418 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Af); 9419 if (val) *arg |= BCM_SYMMETRIC_HASH_0_SUPPRESS_UNIDIR_FIELD_ENABLE; 9420 9421 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9422 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Bf); 9423 if (val) *arg |= BCM_SYMMETRIC_HASH_1_SUPPRESS_UNIDIR_FIELD_ENABLE; 9424 9425 if (SOC_REG_FIELD_VALID(unit, rtag7_hash_ctrl, SYMMETRIC_HASH_FCOE_Af)) { 9426 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9427 SYMMETRIC_HASH_FCOE_Af); 9428 if (val) *arg |= BCM_SYMMETRIC_HASH_0_FCOE_ENABLE; 9429 9430 val = soc_reg64_field32_get(unit, rtag7_hash_ctrl, hash_control, 9431 SYMMETRIC_HASH_FCOE_Bf); 9432 if (val) *arg |= BCM_SYMMETRIC_HASH_1_FCOE_ENABLE; 9433 } 9434 9435 return BCM_E_NONE; 9436 } 9437 #endif /* BCM_TRIUMPH3_SUPPORT */ 9438 9439 9440 STATIC int 9441 _bcm_hash_offset(int unit, bcm_port_t port, bcm_switch_control_t type, 9442 hash_offset_info_t *info) 9443 { 9444 switch (type) { 9445 case bcmSwitchTrunkHashSet0UnicastOffset: 9446 info->idx = 0; 9447 info->hash_concat = 0; 9448 info->sub_f = SUB_SEL_UCf; 9449 info->offset_f = OFFSET_UCf; 9450 info->concat_f = -1; 9451 info->regmem = RTAG7_HASH_TRUNKr; 9452 break; 9453 case bcmSwitchTrunkHashSet0NonUnicastOffset: 9454 info->idx = 0; 9455 info->hash_concat = 0; 9456 info->sub_f = SUB_SEL_NONUCf; 9457 info->offset_f = OFFSET_NONUCf; 9458 info->concat_f = -1; 9459 info->regmem = RTAG7_HASH_TRUNKr; 9460 break; 9461 case bcmSwitchTrunkHashSet1NonUnicastOffset: 9462 info->idx = 1; 9463 info->hash_concat = 0; 9464 info->sub_f = SUB_SEL_NONUCf; 9465 info->offset_f = OFFSET_NONUCf; 9466 info->concat_f = -1; 9467 info->regmem = RTAG7_HASH_TRUNKr; 9468 break; 9469 case bcmSwitchTrunkHashSet1UnicastOffset: 9470 info->idx = 1; 9471 info->hash_concat = 0; 9472 info->sub_f = SUB_SEL_UCf; 9473 info->offset_f = OFFSET_UCf; 9474 info->concat_f = -1; 9475 info->regmem = RTAG7_HASH_TRUNKr; 9476 break; 9477 case bcmSwitchTrunkFailoverHashOffset: 9478 info->idx = 0; 9479 info->hash_concat = 0; 9480 info->sub_f = SUB_SELf; 9481 info->offset_f = OFFSETf; 9482 info->concat_f = -1; 9483 info->regmem = RTAG7_HASH_PLFSr; 9484 break; 9485 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 9486 info->idx = 0; 9487 info->hash_concat = 0; 9488 info->sub_f = SUB_SEL_UCf; 9489 info->offset_f = OFFSET_UCf; 9490 info->concat_f = -1; 9491 info->regmem = RTAG7_HASH_HG_TRUNKr; 9492 break; 9493 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 9494 info->idx = 0; 9495 info->hash_concat = 0; 9496 info->sub_f = SUB_SEL_NONUCf; 9497 info->offset_f = OFFSET_NONUCf; 9498 info->concat_f = -1; 9499 info->regmem = RTAG7_HASH_HG_TRUNKr; 9500 break; 9501 case bcmSwitchFabricTrunkHashSet1UnicastOffset: 9502 info->idx = 1; 9503 info->hash_concat = 0; 9504 info->sub_f = SUB_SEL_UCf; 9505 info->offset_f = OFFSET_UCf; 9506 info->concat_f = -1; 9507 info->regmem = RTAG7_HASH_HG_TRUNKr; 9508 break; 9509 case bcmSwitchFabricTrunkHashSet1NonUnicastOffset: 9510 info->idx = 1; 9511 info->hash_concat = 0; 9512 info->sub_f = SUB_SEL_NONUCf; 9513 info->offset_f = OFFSET_NONUCf; 9514 info->concat_f = -1; 9515 info->regmem = RTAG7_HASH_HG_TRUNKr; 9516 break; 9517 case bcmSwitchFabricTrunkFailoverHashOffset: 9518 info->idx = 0; 9519 info->hash_concat = 0; 9520 info->sub_f = SUB_SELf; 9521 info->offset_f = OFFSETf; 9522 info->concat_f = -1; 9523 info->regmem = RTAG7_HASH_HG_TRUNK_FAILOVERr; 9524 break; 9525 case bcmSwitchFabricTrunkDynamicHashOffset: 9526 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_DLB_HGTr)) { 9527 info->idx = 0; 9528 info->hash_concat = 0; 9529 info->sub_f = SUB_SELf; 9530 info->offset_f = OFFSETf; 9531 info->concat_f = -1; 9532 info->regmem = RTAG7_HASH_DLB_HGTr; 9533 } else { 9534 return BCM_E_UNAVAIL; 9535 } 9536 break; 9537 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 9538 info->idx = 0; 9539 info->hash_concat = 0; 9540 info->sub_f = SUB_SEL_UCf; 9541 info->offset_f = OFFSET_UCf; 9542 info->concat_f = -1; 9543 info->regmem = RTAG7_HASH_LBIDr; 9544 break; 9545 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 9546 info->idx = 0; 9547 info->hash_concat = 0; 9548 info->sub_f = SUB_SEL_NONUCf; 9549 info->offset_f = OFFSET_NONUCf; 9550 info->concat_f = -1; 9551 info->regmem = RTAG7_HASH_LBIDr; 9552 break; 9553 case bcmSwitchLoadBalanceHashSet1UnicastOffset: 9554 info->idx = 1; 9555 info->hash_concat = 0; 9556 info->sub_f = SUB_SEL_UCf; 9557 info->offset_f = OFFSET_UCf; 9558 info->concat_f = -1; 9559 info->regmem = RTAG7_HASH_LBIDr; 9560 break; 9561 case bcmSwitchLoadBalanceHashSet1NonUnicastOffset: 9562 info->idx = 1; 9563 info->hash_concat = 0; 9564 info->sub_f = SUB_SEL_NONUCf; 9565 info->offset_f = OFFSET_NONUCf; 9566 info->concat_f = -1; 9567 info->regmem = RTAG7_HASH_LBIDr; 9568 break; 9569 case bcmSwitchECMPHashSet0Offset: 9570 info->idx = 0; 9571 info->hash_concat = 0; 9572 info->sub_f = SUB_SELf; 9573 info->offset_f = OFFSETf; 9574 info->concat_f = -1; 9575 info->regmem = RTAG7_HASH_ECMPr; 9576 break; 9577 case bcmSwitchECMPHashSet1Offset: 9578 info->idx = 1; 9579 info->hash_concat = 0; 9580 info->sub_f = SUB_SELf; 9581 info->offset_f = OFFSETf; 9582 info->concat_f = -1; 9583 info->regmem = RTAG7_HASH_ECMPr; 9584 break; 9585 #ifdef BCM_KATANA_SUPPORT 9586 case bcmSwitchEntropyHashSet0Offset: 9587 info->idx = 0; 9588 info->hash_concat = 0; 9589 info->sub_f = SUB_SEL_ENTROPY_LABELf; 9590 info->offset_f = OFFSET_ENTROPY_LABELf; 9591 info->concat_f = CONCATENATE_HASH_FIELDS_ENTROPY_LABELf; 9592 info->regmem = RTAG7_HASH_ENTROPY_LABELr; 9593 break; 9594 case bcmSwitchEntropyHashSet1Offset: 9595 info->idx = 1; 9596 info->hash_concat = 0; 9597 info->sub_f = SUB_SEL_ENTROPY_LABELf; 9598 info->offset_f = OFFSET_ENTROPY_LABELf; 9599 info->concat_f = CONCATENATE_HASH_FIELDS_ENTROPY_LABELf; 9600 info->regmem = RTAG7_HASH_ENTROPY_LABELr; 9601 break; 9602 #endif /* BCM_KATANA_SUPPORT */ 9603 default: 9604 return BCM_E_UNAVAIL; 9605 } 9606 9607 return BCM_E_NONE; 9608 } 9609 9610 /* 9611 * Function: 9612 * _bcm_xgs3_fieldoffset_set 9613 * Description: 9614 * Set the enhanced (aka rtag 7) bits selection offset. 9615 * Parameters: 9616 * unit - StrataSwitch PCI device unit number (driver internal). 9617 * port - port 9618 * type - The desired configuration parameter to set. 9619 * arg - BCM_HASH_CONTROL* 9620 * Returns: 9621 * BCM_E_xxxx 9622 */ 9623 9624 STATIC int 9625 _bcm_xgs3_fieldoffset_set(int unit, bcm_port_t port, 9626 bcm_switch_control_t type, int arg) 9627 { 9628 uint32 hash_control; 9629 int sub_field_width[8]; 9630 int total_width, offset = -1, i; 9631 hash_offset_info_t info; 9632 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 9633 || defined(BCM_KATANA_SUPPORT) 9634 int is_hg_port = 0; 9635 #endif 9636 #if defined(BCM_TRIUMPH3_SUPPORT) 9637 int rv = BCM_E_NONE; 9638 #endif 9639 9640 #if defined(BCM_HURRICANE_SUPPORT) 9641 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 9642 return (BCM_E_UNAVAIL); 9643 } 9644 #endif 9645 9646 if (arg < 0) { 9647 return BCM_E_PARAM; 9648 } 9649 9650 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 9651 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 9652 SOC_IS_KATANA2(unit)) { 9653 BCM_IF_ERROR_RETURN(_bcm_tr3_hash_offset(unit, port, type, &info)); 9654 } else 9655 #endif /* BCM_TRIUMPH3_SUPPORT */ 9656 { 9657 BCM_IF_ERROR_RETURN(_bcm_hash_offset(unit, port, type, &info)); 9658 } 9659 9660 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 9661 || defined(BCM_KATANA_SUPPORT) 9662 if (!BCM_GPORT_IS_SET(port) && IS_HG_PORT(unit, port)) { 9663 is_hg_port = 1; 9664 } 9665 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) { 9666 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 9667 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 9668 #if defined(BCM_TOMAHAWK3_SUPPORT) 9669 if (SOC_IS_TOMAHAWK3(unit)) { 9670 sub_field_width[2] = 6; /* LBN (6bit) */ 9671 } else 9672 #endif /* BCM_TOMAHAWK3_SUPPORT */ 9673 { 9674 sub_field_width[2] = 4; /* LBN (4bit) */ 9675 } 9676 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 9677 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 9678 sub_field_width[5] = 8; /* SW1 LBID ( 8 bit)*/ 9679 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 9680 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 9681 } else if (SOC_IS_KATANA(unit)) { 9682 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 9683 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 9684 sub_field_width[2] = 4; /* LBN (4bit) */ 9685 if (is_hg_port) { 9686 sub_field_width[3] = 7; /* MH.DPORT (7 bit) */ 9687 } else { 9688 if (type == bcmSwitchEntropyHashSet0Offset || 9689 type == bcmSwitchEntropyHashSet1Offset) { 9690 sub_field_width[3] = 64; /* HASH_A0 B0 A1 B1 (64 bit) */ 9691 } else { 9692 sub_field_width[3] = 16; /* HASH_A0 (16 bit) */ 9693 } 9694 } 9695 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 9696 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 9697 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 9698 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 9699 } else if (SOC_IS_KATANA2(unit)) { 9700 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 9701 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 9702 sub_field_width[2] = 4; /* LBN (4bit) */ 9703 if (is_hg_port) { 9704 sub_field_width[3] = 7; /* MH.DPORT (7 bit) */ 9705 } else { 9706 sub_field_width[3] = 16; /* HASH_A0 (16 bit) */ 9707 } 9708 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 9709 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 9710 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 9711 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 9712 } else 9713 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_TRIDENT_SUPPORT || BCM_KATANA_SUPPORT */ 9714 { 9715 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 9716 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 9717 sub_field_width[2] = 4; /* LBN (4bit) */ 9718 sub_field_width[3] = 5; 9719 sub_field_width[4] = 8; 9720 sub_field_width[5] = 0; 9721 sub_field_width[6] = 0; 9722 sub_field_width[7] = 0; 9723 } 9724 9725 /* Get hash bits width */ 9726 total_width = 0; 9727 for (i = 0; i < 8; i++) { 9728 total_width += sub_field_width[i]; 9729 } 9730 /* Concatenate if offset value exceeds total hash width */ 9731 if (arg >= total_width) { 9732 if (info.concat_f == -1) { 9733 /* BCM_E_UNAVAIL is returned if arg >= total width of 9734 * non-concatenate fields and concatenate field is unavailable 9735 */ 9736 return BCM_E_UNAVAIL; 9737 } 9738 info.hash_concat = 1; 9739 } 9740 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 9741 || defined(BCM_KATANA_SUPPORT) 9742 /* Concatenate if enforced or if offset value exceeds total hash width */ 9743 if (info.hash_concat == 1) { 9744 /* Concatenation hash computation order is referenced from 9745 * fb_Irsel1_arch::compute_rtag7_hash 9746 */ 9747 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD_TT(unit)) { 9748 sub_field_width[0] = 64; /* Concat B1,B0,A1,A0(64bit) */ 9749 sub_field_width[1] = 0; /* 0 */ 9750 #if defined(BCM_TOMAHAWK3_SUPPORT) 9751 if (SOC_IS_TOMAHAWK3(unit)) { 9752 sub_field_width[2] = 6; /* LBN (6bit) */ 9753 sub_field_width[3] = 64; /* Concat B1,B0,A1,A0(64bit) */ 9754 } else 9755 #endif /* BCM_TOMAHAWK3_SUPPORT */ 9756 { 9757 sub_field_width[2] = 4; /* LBN (4bit) */ 9758 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 9759 } 9760 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 9761 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 9762 sub_field_width[6] = 0; /* 0 */ 9763 sub_field_width[7] = 0; /* 0 */ 9764 } else if (SOC_IS_KATANA(unit)) { 9765 sub_field_width[0] = 64; /* HASH_A0 B0 A1 B1(64bit) */ 9766 sub_field_width[1] = 0; /* 0 */ 9767 sub_field_width[2] = 4; /* LBN (4 bit) */ 9768 if (is_hg_port) { 9769 sub_field_width[3] = 7; /* MH.DPORT (7 bit) */ 9770 } else { 9771 sub_field_width[3] = 64; /* HASH_A0 B0 A1 B1 (64 bit) */ 9772 } 9773 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 9774 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 9775 sub_field_width[6] = 0; /* 0 */ 9776 sub_field_width[7] = 0; /* 0 */ 9777 } else if (SOC_IS_KATANA2(unit)) { 9778 sub_field_width[0] = 64; /* HASH_A0 B0 A1 B1(64bit) */ 9779 sub_field_width[1] = 0; /* 0 */ 9780 sub_field_width[2] = 4; /* LBN (4 bit) */ 9781 if (is_hg_port) { 9782 sub_field_width[3] = 7; /* MH.DPORT (7 bit) */ 9783 } else { 9784 sub_field_width[3] = 64; /* HASH_A0 B0 A1 B1 (64 bit) */ 9785 } 9786 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 9787 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 9788 sub_field_width[6] = 0; /* 0 */ 9789 sub_field_width[7] = 0; /* 0 */ 9790 } 9791 /* Get concatenated hash bits width */ 9792 arg = arg - total_width; 9793 total_width = 0; 9794 for (i = 0; i < 8; i++) { 9795 total_width += sub_field_width[i]; 9796 } 9797 } 9798 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_TRIDENT_SUPPORT || BCM_KATANA_SUPPORT */ 9799 9800 /* Select hash sub select and hash bit offset */ 9801 offset = arg % total_width; 9802 for (i = 0; i < 8; i++) { 9803 offset -= sub_field_width[i]; 9804 if (offset < 0) { 9805 offset += sub_field_width[i]; 9806 break; 9807 } 9808 } 9809 9810 #if defined (BCM_TOMAHAWK_SUPPORT) 9811 #define BCM_TH_HASH_BIN_A0 0 9812 #define BCM_TH_HASH_BIN_A1 6 9813 #define BCM_TH_HASH_BIN_B0 1 9814 #define BCM_TH_HASH_BIN_B1 7 9815 9816 if ((soc_feature(unit, soc_feature_th_tflow)) && 9817 (SOC_INFO(unit).th_tflow_enabled == 1) && 9818 ( _bcm_switch_tflow_mode_info[unit].enabled == 0)) { 9819 /* i is rtag7 offset field index */ 9820 if (i == BCM_TH_HASH_BIN_B0) { 9821 i = BCM_TH_HASH_BIN_A0; 9822 } else if (i == BCM_TH_HASH_BIN_B1) { 9823 i = BCM_TH_HASH_BIN_A1; 9824 } 9825 } 9826 #endif 9827 9828 #if defined(BCM_TRIUMPH3_SUPPORT) 9829 if (SOC_MEM_IS_VALID(unit, info.regmem)) { 9830 /* LPORT Profile */ 9831 /* LPORT_PROFILE_TABLE is used by front panel ports too for TD3 */ 9832 if (BCM_GPORT_IS_PROXY(port) || SOC_IS_TRIDENT3X(unit) || 9833 (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 9834 BCM_GPORT_IS_SUBPORT_PORT(port))) { 9835 9836 int field_count = 0; 9837 soc_field_t fields[3]; 9838 uint32 values[3]; 9839 9840 fields[0] = info.sub_f; 9841 values[0] = i; 9842 field_count++; 9843 fields[1] = info.offset_f; 9844 values[1] = offset; 9845 field_count++; 9846 if (info.concat_f != -1) { 9847 fields[2] = info.concat_f; 9848 values[2] = info.hash_concat; 9849 field_count++; 9850 } 9851 PORT_LOCK(unit); 9852 rv = bcm_esw_port_lport_fields_set(unit, port, 9853 LPORT_PROFILE_RTAG7_TAB, 9854 field_count, fields, values); 9855 PORT_UNLOCK(unit); 9856 if (BCM_FAILURE(rv)) { 9857 return rv; 9858 } 9859 } else { 9860 uint32 hash_control_entry[SOC_MAX_MEM_WORDS]; 9861 SOC_IF_ERROR_RETURN 9862 (soc_mem_read(unit, info.regmem, 9863 MEM_BLOCK_ANY, info.idx, hash_control_entry)); 9864 if (!soc_mem_field_valid(unit, info.regmem, info.sub_f) || 9865 !soc_mem_field_valid(unit, info.regmem, info.offset_f)) { 9866 return (BCM_E_UNAVAIL); 9867 } 9868 soc_mem_field32_set(unit, 9869 info.regmem, hash_control_entry, info.sub_f, i); 9870 soc_mem_field32_set(unit, 9871 info.regmem, hash_control_entry, 9872 info.offset_f, offset); 9873 if (info.concat_f != -1) { 9874 soc_mem_field32_set(unit, 9875 info.regmem, hash_control_entry, 9876 info.concat_f, info.hash_concat); 9877 } 9878 SOC_IF_ERROR_RETURN 9879 (soc_mem_write(unit, 9880 info.regmem, MEM_BLOCK_ALL, info.idx, 9881 hash_control_entry)); 9882 } 9883 } else 9884 #endif /* BCM_TRIUMPH3_SUPPORT */ 9885 if (SOC_REG_IS_VALID(unit, info.regmem)) { 9886 SOC_IF_ERROR_RETURN 9887 (soc_reg32_get(unit, info.regmem, 9888 REG_PORT_ANY, info.idx, &hash_control)); 9889 soc_reg_field_set(unit, 9890 info.regmem, &hash_control, info.sub_f, i); 9891 soc_reg_field_set(unit, 9892 info.regmem, &hash_control, info.offset_f, offset); 9893 if (info.concat_f != -1) { 9894 soc_reg_field_set(unit, 9895 info.regmem, &hash_control, 9896 info.concat_f, info.hash_concat); 9897 } 9898 SOC_IF_ERROR_RETURN 9899 (soc_reg32_set(unit, 9900 info.regmem, REG_PORT_ANY, info.idx, hash_control)); 9901 } 9902 9903 return BCM_E_NONE; 9904 } 9905 9906 /* 9907 * Function: 9908 * _bcm_xgs3_fieldoffset_get 9909 * Description: 9910 * Get the current enhanced (aka rtag 7) bit selection offset. 9911 * Parameters: 9912 * unit - StrataSwitch PCI device unit number (driver internal). 9913 * type - The desired configuration parameter to retrieve. 9914 * arg - Pointer to where the retrieved value will be written. 9915 * Returns: 9916 * BCM_E_xxxx 9917 */ 9918 9919 STATIC int 9920 _bcm_xgs3_fieldoffset_get(int unit, bcm_port_t port, 9921 bcm_switch_control_t type, int *arg) 9922 { 9923 uint32 hash_control; 9924 int sub_field_width[8]; 9925 int idx = 0, i; 9926 hash_offset_info_t info; 9927 9928 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 9929 || defined(BCM_KATANA_SUPPORT) 9930 int total_width = 0; 9931 int concat = 0; 9932 int is_hg_port = 0; 9933 #endif 9934 #if defined(BCM_TRIUMPH3_SUPPORT) 9935 int rv = BCM_E_NONE; 9936 #endif 9937 9938 #if defined(BCM_HURRICANE_SUPPORT) 9939 if (SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)) { 9940 return (BCM_E_UNAVAIL); 9941 } 9942 #endif 9943 9944 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 9945 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 9946 SOC_IS_KATANA2(unit)) { 9947 BCM_IF_ERROR_RETURN(_bcm_tr3_hash_offset(unit, port, type, &info)); 9948 } else 9949 #endif /* BCM_TRIUMPH3_SUPPORT */ 9950 { 9951 BCM_IF_ERROR_RETURN(_bcm_hash_offset(unit, port, type, &info)); 9952 } 9953 9954 #if defined(BCM_TRIUMPH3_SUPPORT) 9955 if (SOC_MEM_IS_VALID(unit, info.regmem)) { 9956 /* LPORT Profile */ 9957 if (BCM_GPORT_IS_PROXY(port) || 9958 (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 9959 BCM_GPORT_IS_SUBPORT_PORT(port))) { 9960 9961 int field_count = 0; 9962 soc_field_t fields[3]; 9963 uint32 values[3]; 9964 9965 fields[0] = info.sub_f; 9966 field_count++; 9967 fields[1] = info.offset_f; 9968 field_count++; 9969 if (info.concat_f != -1) { 9970 fields[2] = info.concat_f; 9971 field_count++; 9972 } 9973 PORT_LOCK(unit); 9974 rv = bcm_esw_port_lport_fields_get(unit, port, 9975 LPORT_PROFILE_RTAG7_TAB, 9976 field_count, fields, values); 9977 PORT_UNLOCK(unit); 9978 if (BCM_FAILURE(rv)) { 9979 return rv; 9980 } 9981 idx = values[0]; 9982 *arg = values[1]; 9983 if (info.concat_f != -1) { 9984 concat = values[2]; 9985 } 9986 } else { 9987 uint32 hash_control_entry[SOC_MAX_MEM_WORDS]; 9988 SOC_IF_ERROR_RETURN 9989 (soc_mem_read(unit, info.regmem, 9990 MEM_BLOCK_ANY, info.idx, hash_control_entry)); 9991 if (!soc_mem_field_valid(unit, info.regmem, info.sub_f) || 9992 !soc_mem_field_valid(unit, info.regmem, info.offset_f)) { 9993 return (BCM_E_UNAVAIL); 9994 } 9995 idx = soc_mem_field32_get(unit, info.regmem, 9996 hash_control_entry, info.sub_f); 9997 *arg = soc_mem_field32_get(unit, info.regmem, 9998 hash_control_entry, info.offset_f); 9999 if (info.concat_f != -1) { 10000 concat = soc_mem_field32_get(unit, info.regmem, 10001 hash_control_entry, info.concat_f); 10002 } 10003 } 10004 } else 10005 #endif /* BCM_TRIUMPH3_SUPPORT */ 10006 if (SOC_REG_IS_VALID(unit, info.regmem)) { 10007 SOC_IF_ERROR_RETURN 10008 (soc_reg32_get(unit, info.regmem, REG_PORT_ANY, info.idx, &hash_control)); 10009 idx = soc_reg_field_get(unit, info.regmem, hash_control, info.sub_f); 10010 *arg = soc_reg_field_get(unit, info.regmem, hash_control, info.offset_f); 10011 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_KATANA_SUPPORT) 10012 if (info.concat_f != -1) { 10013 concat = soc_reg_field_get(unit, info.regmem, hash_control, info.concat_f); 10014 } 10015 #endif 10016 } 10017 10018 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 10019 || defined(BCM_KATANA_SUPPORT) 10020 if (!BCM_GPORT_IS_SET(port) && IS_HG_PORT(unit, port)) { 10021 is_hg_port = 1; 10022 } 10023 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) { 10024 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 10025 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 10026 #if defined(BCM_TOMAHAWK3_SUPPORT) 10027 if (SOC_IS_TOMAHAWK3(unit)) { 10028 sub_field_width[2] = 6; /* LBN (6bit) */ 10029 } else 10030 #endif /* BCM_TOMAHAWK3_SUPPORT */ 10031 { 10032 sub_field_width[2] = 4; /* LBN (4bit) */ 10033 } 10034 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 10035 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 10036 sub_field_width[5] = 8; /* SW1 LBID ( 8 bit)*/ 10037 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 10038 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 10039 } else if (SOC_IS_KATANA(unit)) { 10040 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 10041 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 10042 sub_field_width[2] = 4; /* LBN (4bit) */ 10043 if (is_hg_port) { 10044 sub_field_width[3] = 7; /* MH.DPORT (7bit) */ 10045 } else { 10046 if (type == bcmSwitchEntropyHashSet0Offset || 10047 type == bcmSwitchEntropyHashSet1Offset) { 10048 sub_field_width[3] = 64; /* HASH_A0 B0 A1 B1 (64bit) */ 10049 } else { 10050 sub_field_width[3] = 16; /* HASH_A0 (16bit) */ 10051 } 10052 } 10053 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 10054 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 10055 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 10056 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 10057 } else if (SOC_IS_KATANA2(unit)) { 10058 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 10059 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 10060 sub_field_width[2] = 4; /* LBN (4bit) */ 10061 if (is_hg_port) { 10062 sub_field_width[3] = 7; /* MH.DPORT (7bit) */ 10063 } else { 10064 sub_field_width[3] = 16; /* HASH_A0 (16bit) */ 10065 } 10066 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 10067 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 10068 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 10069 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 10070 } else 10071 #endif /* BCM_TRIDENT_SUPPORT || BCM_TRIUMPH3_SUPPORT || BCM_KATANA_SUPPORT */ 10072 { 10073 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 10074 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 10075 sub_field_width[2] = 4; /* LBN (4bit) */ 10076 sub_field_width[3] = 5; 10077 sub_field_width[4] = 8; 10078 sub_field_width[5] = 0; 10079 sub_field_width[6] = 0; 10080 sub_field_width[7] = 0; 10081 } 10082 10083 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 10084 || defined(BCM_KATANA_SUPPORT) 10085 if (concat) { 10086 /* Get hash bits width */ 10087 for (i = 0; i < 8; i++) { 10088 total_width += sub_field_width[i]; 10089 } 10090 10091 /* Concatenation hash computation order is referenced from 10092 * fb_Irsel1_arch::compute_rtag7_hash 10093 */ 10094 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) { 10095 sub_field_width[0] = 64; /* Concat B1,B0,A1,A0(64bit) */ 10096 sub_field_width[1] = 0; /* 0 */ 10097 #if defined(BCM_TOMAHAWK3_SUPPORT) 10098 if (SOC_IS_TOMAHAWK3(unit)) { 10099 sub_field_width[2] = 6; /* LBN (6bit) */ 10100 sub_field_width[3] = 64; /* Concat B1,B0,A1,A0(64bit) */ 10101 } else 10102 #endif /* BCM_TOMAHAWK3_SUPPORT */ 10103 { 10104 sub_field_width[2] = 4; /* LBN (4bit) */ 10105 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 10106 } 10107 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 10108 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 10109 sub_field_width[6] = 0; /* 0 */ 10110 sub_field_width[7] = 0; /* 0 */ 10111 } else if (SOC_IS_KATANA(unit)) { 10112 sub_field_width[0] = 64; /* HASH_A0 B0 A1 B1(64bit) */ 10113 sub_field_width[1] = 0; /* 0 */ 10114 sub_field_width[2] = 4; /* LBN (4 bit) */ 10115 if (is_hg_port) { 10116 sub_field_width[3] = 7; /* MH.DPORT (7bit) */ 10117 } else { 10118 sub_field_width[3] = 64; /* HASH_A0 B0 A1 B1 (64bit) */ 10119 } 10120 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 10121 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 10122 sub_field_width[6] = 0; /* 0 */ 10123 sub_field_width[7] = 0; /* 0 */ 10124 } else if (SOC_IS_KATANA2(unit)) { 10125 sub_field_width[0] = 64; /* HASH_A0 B0 A1 B1(64bit) */ 10126 sub_field_width[1] = 0; /* 0 */ 10127 sub_field_width[2] = 4; /* LBN (4 bit) */ 10128 if (is_hg_port) { 10129 sub_field_width[3] = 7; /* MH.DPORT (7bit) */ 10130 } else { 10131 sub_field_width[3] = 64; /* HASH_A0 B0 A1 B1 (64bit) */ 10132 } 10133 sub_field_width[4] = 8; /* MH.LBID (8 bit) */ 10134 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 10135 sub_field_width[6] = 0; /* 0 */ 10136 sub_field_width[7] = 0; /* 0 */ 10137 } 10138 10139 *arg += total_width; 10140 } 10141 #endif /* BCM_TRIDENT_SUPPORT || BCM_TRIUMPH3_SUPPORT || BCM_KATANA_SUPPORT*/ 10142 10143 for (i = 0; i < idx; i++) { 10144 *arg += sub_field_width[i]; 10145 } 10146 10147 return BCM_E_NONE; 10148 } 10149 #endif /* BCM_BRADLEY_SUPPORT || BCM_TRX_SUPPORT */ 10150 10151 #if defined(BCM_TRIDENT2_SUPPORT) 10152 STATIC int 10153 _bcm_td2_switch_udf_hash_set(int unit, int arg) 10154 { 10155 if(SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_3r, 10156 ENABLE_UDF_FIELD_1_Af) && 10157 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_3r, 10158 ENABLE_UDF_FIELD_1_Bf)){ 10159 uint32 hash_control, val; 10160 10161 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_3r(unit, &hash_control)); 10162 10163 val = (arg & BCM_HASH_FIELD0_ENABLE_UDFHASH ) ? 1 : 0; 10164 soc_reg_field_set(unit, RTAG7_HASH_CONTROL_3r, &hash_control, 10165 ENABLE_UDF_FIELD_1_Af, val); 10166 soc_reg_field_set(unit, RTAG7_HASH_CONTROL_3r, &hash_control, 10167 ENABLE_UDF_FIELD_2_Af, val); 10168 10169 val = (arg & BCM_HASH_FIELD1_ENABLE_UDFHASH ) ? 1 : 0; 10170 soc_reg_field_set(unit, RTAG7_HASH_CONTROL_3r, &hash_control, 10171 ENABLE_UDF_FIELD_1_Bf, val); 10172 soc_reg_field_set(unit, RTAG7_HASH_CONTROL_3r, &hash_control, 10173 ENABLE_UDF_FIELD_2_Bf, val); 10174 10175 BCM_IF_ERROR_RETURN(WRITE_RTAG7_HASH_CONTROL_3r(unit, hash_control)); 10176 10177 return BCM_E_NONE; 10178 }else{ 10179 return BCM_E_UNAVAIL; 10180 } 10181 } 10182 10183 STATIC int 10184 _bcm_td2_switch_udf_hash_get(int unit, int *arg) 10185 { 10186 if(SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_3r, 10187 ENABLE_UDF_FIELD_1_Af) && 10188 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_3r, 10189 ENABLE_UDF_FIELD_1_Bf)){ 10190 uint32 hash_control, val; 10191 10192 *arg = 0; 10193 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_3r(unit, &hash_control)); 10194 10195 val = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_3r, hash_control, 10196 ENABLE_UDF_FIELD_1_Af); 10197 *arg |= (val ? BCM_HASH_FIELD0_ENABLE_UDFHASH : 0); 10198 10199 val = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_3r, hash_control, 10200 ENABLE_UDF_FIELD_1_Bf); 10201 *arg |= (val ? BCM_HASH_FIELD1_ENABLE_UDFHASH : 0); 10202 10203 return BCM_E_NONE; 10204 }else{ 10205 return BCM_E_UNAVAIL; 10206 } 10207 } 10208 10209 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 10210 STATIC int 10211 _bcm_th2_switch_udf_hash_set(int unit, int arg) 10212 { 10213 uint64 hash_control; 10214 uint32 val; 10215 10216 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_3_64r(unit, &hash_control)); 10217 10218 val = (arg & BCM_HASH_FIELD0_ENABLE_UDFHASH ) ? 1 : 0; 10219 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_3_64r, &hash_control, 10220 ENABLE_UDF_FIELD_1_Af, val); 10221 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_3_64r, &hash_control, 10222 ENABLE_UDF_FIELD_2_Af, val); 10223 10224 val = (arg & BCM_HASH_FIELD1_ENABLE_UDFHASH ) ? 1 : 0; 10225 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_3_64r, &hash_control, 10226 ENABLE_UDF_FIELD_1_Bf, val); 10227 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_3_64r, &hash_control, 10228 ENABLE_UDF_FIELD_2_Bf, val); 10229 10230 BCM_IF_ERROR_RETURN(WRITE_RTAG7_HASH_CONTROL_3_64r(unit, hash_control)); 10231 10232 return BCM_E_NONE; 10233 } 10234 10235 STATIC int 10236 _bcm_th2_switch_udf_hash_get(int unit, int *arg) 10237 { 10238 uint64 hash_control; 10239 uint32 val; 10240 10241 *arg = 0; 10242 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROL_3_64r(unit, &hash_control)); 10243 10244 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_3_64r, hash_control, 10245 ENABLE_UDF_FIELD_1_Af); 10246 *arg |= (val ? BCM_HASH_FIELD0_ENABLE_UDFHASH : 0); 10247 10248 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_3_64r, hash_control, 10249 ENABLE_UDF_FIELD_1_Bf); 10250 *arg |= (val ? BCM_HASH_FIELD1_ENABLE_UDFHASH : 0); 10251 10252 return BCM_E_NONE; 10253 } 10254 #endif /* BCM_TOMAHAWK2_SUPPORT || BCM_TOMAHAWK3_SUPPORT */ 10255 #endif /* BCM_TRIDENT2_SUPPORT */ 10256 10257 #ifdef BCM_TRIDENT_SUPPORT 10258 10259 STATIC int 10260 _bcm_td_macroflow_hash_info_get(int unit, bcm_switch_control_t type, 10261 hash_offset_info_t *hash_info) 10262 { 10263 hash_info->regmem = RTAG7_FLOW_BASED_HASHm; 10264 switch(type) 10265 { 10266 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10267 case bcmSwitchMacroFlowEcmpHashConcatEnable: 10268 hash_info->sub_f = SUB_SEL_ECMPf; 10269 hash_info->offset_f = OFFSET_ECMPf; 10270 hash_info->concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 10271 hash_info->hash_concat = 1; 10272 break; 10273 #endif 10274 case bcmSwitchMacroFlowHashMinOffset: 10275 case bcmSwitchMacroFlowHashMaxOffset: 10276 case bcmSwitchMacroFlowHashStrideOffset: 10277 hash_info->sub_f = SUB_SEL_ECMPf; 10278 hash_info->offset_f = OFFSET_ECMPf; 10279 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10280 if (SOC_MEM_FIELD_VALID(unit, hash_info->regmem, 10281 CONCATENATE_HASH_FIELDS_ECMPf)) { 10282 hash_info->concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 10283 } else 10284 #endif 10285 { 10286 hash_info->concat_f = -1; 10287 } 10288 hash_info->hash_concat = 0; 10289 break; 10290 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10291 /* Set RTAG7 Macro Flow Concatenation */ 10292 case bcmSwitchMacroFlowEcmpHashOverlayConcatEnable: 10293 if (soc_feature(unit, soc_feature_riot) || 10294 soc_feature(unit, soc_feature_multi_level_ecmp)) { 10295 hash_info->sub_f = SUB_SEL_ECMP_LEVEL1f; 10296 hash_info->offset_f = OFFSET_ECMP_LEVEL1f; 10297 hash_info->concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL1f; 10298 hash_info->hash_concat = 1; 10299 } else { 10300 return BCM_E_UNAVAIL; 10301 } 10302 break; 10303 case bcmSwitchMacroFlowHashOverlayMinOffset: 10304 case bcmSwitchMacroFlowHashOverlayMaxOffset: 10305 case bcmSwitchMacroFlowHashOverlayStrideOffset: 10306 if (soc_feature(unit, soc_feature_riot) || 10307 soc_feature(unit, soc_feature_multi_level_ecmp)) { 10308 hash_info->sub_f = SUB_SEL_ECMP_LEVEL1f; 10309 hash_info->offset_f = OFFSET_ECMP_LEVEL1f; 10310 hash_info->concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL1f; 10311 hash_info->hash_concat = 0; 10312 } else { 10313 return BCM_E_UNAVAIL; 10314 } 10315 break; 10316 #endif 10317 10318 #ifdef BCM_TOMAHAWK_SUPPORT 10319 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 10320 if (SOC_IS_TOMAHAWKX(unit)) { 10321 hash_info->sub_f = SUB_SEL_ECMP_LEVEL2f; 10322 hash_info->offset_f = OFFSET_ECMP_LEVEL2f; 10323 hash_info->concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL2f; 10324 hash_info->hash_concat = 1; 10325 } else { 10326 return BCM_E_UNAVAIL; 10327 } 10328 break; 10329 #endif /* BCM_TOMAHAWK_SUPPORT */ 10330 10331 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10332 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 10333 hash_info->sub_f = SUB_SEL_LBID_OR_ENTROPY_LABELf; 10334 hash_info->offset_f = OFFSET_LBID_OR_ENTROPY_LABELf; 10335 hash_info->concat_f = CONCATENATE_HASH_FIELDS_LBID_OR_ENTROPY_LABELf; 10336 hash_info->hash_concat = 1; 10337 break; 10338 10339 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 10340 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 10341 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 10342 hash_info->sub_f = SUB_SEL_LBID_OR_ENTROPY_LABELf; 10343 hash_info->offset_f = OFFSET_LBID_OR_ENTROPY_LABELf; 10344 hash_info->concat_f = CONCATENATE_HASH_FIELDS_LBID_OR_ENTROPY_LABELf; 10345 hash_info->hash_concat = 0; 10346 break; 10347 10348 case bcmSwitchMacroFlowTrunkHashConcatEnable: 10349 hash_info->sub_f = SUB_SEL_TRUNKf; 10350 hash_info->offset_f = OFFSET_TRUNKf; 10351 hash_info->concat_f = CONCATENATE_HASH_FIELDS_TRUNKf; 10352 hash_info->hash_concat = 1; 10353 break; 10354 10355 case bcmSwitchMacroFlowTrunkHashMinOffset: 10356 case bcmSwitchMacroFlowTrunkHashMaxOffset: 10357 case bcmSwitchMacroFlowTrunkHashStrideOffset: 10358 hash_info->sub_f = SUB_SEL_TRUNKf; 10359 hash_info->offset_f = OFFSET_TRUNKf; 10360 hash_info->concat_f = CONCATENATE_HASH_FIELDS_TRUNKf; 10361 hash_info->hash_concat = 0; 10362 break; 10363 10364 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 10365 if (SOC_IS_TOMAHAWK3(unit)) { 10366 return BCM_E_UNAVAIL; 10367 } 10368 hash_info->sub_f = SUB_SEL_HG_TRUNKf; 10369 hash_info->offset_f = OFFSET_HG_TRUNKf; 10370 hash_info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNKf; 10371 hash_info->hash_concat = 1; 10372 break; 10373 10374 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 10375 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 10376 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 10377 if (SOC_IS_TOMAHAWK3(unit)) { 10378 return BCM_E_UNAVAIL; 10379 } 10380 hash_info->sub_f = SUB_SEL_HG_TRUNKf; 10381 hash_info->offset_f = OFFSET_HG_TRUNKf; 10382 hash_info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNKf; 10383 hash_info->hash_concat = 0; 10384 break; 10385 #endif 10386 default: 10387 return BCM_E_UNAVAIL; 10388 } 10389 return BCM_E_NONE; 10390 } 10391 10392 STATIC void 10393 _bcm_td_macroflow_param_base_get(int unit, int *base_arr, uint8 concat_view) { 10394 int sub_sel_id; 10395 int sub_field_width[8]; 10396 10397 if (concat_view) { 10398 /* sub field width: 64, 0, 4, 64, 8, 8, 0, 0 */ 10399 sub_field_width[0] = 64; /* Concat B1,B0,A1,A0(64bit) */ 10400 sub_field_width[1] = 0; /* 0 */ 10401 #if defined(BCM_TOMAHAWK3_SUPPORT) 10402 if (SOC_IS_TOMAHAWK3(unit)) { 10403 sub_field_width[2] = 6; /* LBN (6bit) */ 10404 } else 10405 #endif /* BCM_TOMAHAWK3_SUPPORT */ 10406 { 10407 sub_field_width[2] = 4; /* LBN (4bit) */ 10408 } 10409 sub_field_width[3] = 64; /* Concat B1,B0,A1,A0(64bit) */ 10410 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8bit) */ 10411 sub_field_width[5] = 8; /* SW1 LBID (8bit) */ 10412 sub_field_width[6] = 0; /* 0 */ 10413 sub_field_width[7] = 0; /* 0 */ 10414 } else { 10415 /* sub field width: 16, 16, 4, 16, 8, 8, 16, 16 */ 10416 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 10417 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 10418 #if defined(BCM_TOMAHAWK3_SUPPORT) 10419 if (SOC_IS_TOMAHAWK3(unit)) { 10420 sub_field_width[2] = 6; /* LBN (6bit) */ 10421 } else 10422 #endif /* BCM_TOMAHAWK3_SUPPORT */ 10423 { 10424 sub_field_width[2] = 4; /* LBN (4bit) */ 10425 } 10426 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 10427 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8bit) */ 10428 sub_field_width[5] = 8; /* SW1 LBID ( 8bit) */ 10429 sub_field_width[6] = 16; /* HASH_A1 (16bit) */ 10430 sub_field_width[7] = 16; /* HASH_B1 (16bit) */ 10431 } 10432 10433 /* base[0] = 0 10434 * base[1] = base[0] + width of base[0] 10435 * base[2] = base[1] + width of base[1] 10436 * base[3] = base[2] + width of base[2] 10437 * base[4] = base[3] + width of base[3] 10438 * base[5] = base[4] + width of base[4] 10439 * base[6] = base[5] + width of base[5] 10440 * base[7] = base[6] + width of base[6] 10441 * base[8] = base[7] + width of base[7] 10442 */ 10443 if (base_arr) { 10444 base_arr[0] = 0; 10445 for (sub_sel_id=1 ; sub_sel_id<=8 ; sub_sel_id++) { 10446 base_arr[sub_sel_id] = 10447 base_arr[sub_sel_id-1] + sub_field_width[sub_sel_id-1]; 10448 } 10449 } 10450 return; 10451 } 10452 10453 STATIC int 10454 _bcm_td_macroflow_param_get(int unit, bcm_switch_control_t type, 10455 int **sub_field_base, int *min_offset, 10456 int *max_offset, int *stride_offset, 10457 int *concat_enable) 10458 { 10459 static int base[9]; 10460 rtag7_flow_based_hash_entry_t entry; 10461 int min, max, stride; 10462 int index, offset; 10463 uint32 fval, sub_sel; 10464 hash_offset_info_t hash_info; 10465 int concat_value = 0; 10466 10467 sal_memset(&hash_info, 0, sizeof(hash_offset_info_t)); 10468 BCM_IF_ERROR_RETURN(_bcm_td_macroflow_hash_info_get(unit, type, 10469 &hash_info)); 10470 10471 if (!SOC_MEM_IS_VALID(unit, hash_info.regmem)) { 10472 return BCM_E_UNAVAIL; 10473 } 10474 10475 SOC_IF_ERROR_RETURN 10476 (soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 0, &entry)); 10477 sub_sel = soc_mem_field32_get(unit, hash_info.regmem, &entry, 10478 hash_info.sub_f); 10479 fval = soc_mem_field32_get(unit, hash_info.regmem, &entry, 10480 hash_info.offset_f); 10481 10482 _bcm_td_macroflow_param_base_get(unit, base, 0); 10483 10484 if (hash_info.concat_f != -1) { 10485 concat_value = soc_mem_field32_get(unit, hash_info.regmem, &entry, 10486 hash_info.concat_f); 10487 _bcm_td_macroflow_param_base_get(unit, 10488 base, (hash_info.hash_concat || concat_value)); 10489 } 10490 min = base[sub_sel] + fval; 10491 10492 SOC_IF_ERROR_RETURN 10493 (soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 1, &entry)); 10494 sub_sel = soc_mem_field32_get(unit, hash_info.regmem, &entry, 10495 hash_info.sub_f); 10496 fval = soc_mem_field32_get(unit, hash_info.regmem, &entry, 10497 hash_info.offset_f); 10498 max = base[sub_sel] + fval; 10499 stride = max - min; 10500 10501 if (stride != 0) { 10502 for (index = 2; 10503 index <= soc_mem_index_max(unit, hash_info.regmem); 10504 index++) { 10505 SOC_IF_ERROR_RETURN 10506 (soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 10507 index, &entry)); 10508 sub_sel = soc_mem_field32_get(unit, hash_info.regmem, &entry, 10509 hash_info.sub_f); 10510 fval = soc_mem_field32_get(unit, hash_info.regmem, &entry, 10511 hash_info.offset_f); 10512 offset = base[sub_sel] + fval; 10513 if (offset != max + stride) { 10514 break; 10515 } 10516 max = offset; 10517 } 10518 } 10519 10520 if (sub_field_base != NULL) { 10521 *sub_field_base = base; 10522 } 10523 if (min_offset != NULL) { 10524 *min_offset = min; 10525 } 10526 if (max_offset != NULL) { 10527 *max_offset = max; 10528 } 10529 if (stride_offset != NULL) { 10530 *stride_offset = stride; 10531 } 10532 if (concat_enable != NULL) { 10533 *concat_enable = concat_value; 10534 } 10535 return BCM_E_NONE; 10536 } 10537 10538 10539 STATIC int 10540 _bcm_td_macroflow_offset_set(int unit, bcm_switch_control_t type, int arg) 10541 { 10542 int *sub_field_base; 10543 rtag7_flow_based_hash_entry_t entry; 10544 int min_offset, max_offset, stride_offset, concat_enable; 10545 int index, offset; 10546 uint32 sub_sel; 10547 hash_offset_info_t hash_info; 10548 10549 sal_memset(&hash_info, 0, sizeof(hash_offset_info_t)); 10550 /* Hash info such as sub_sel field, offset field and concatenate field 10551 * are retrieved using _bcm_td_macroflow_hash_info_get based on given type. 10552 */ 10553 BCM_IF_ERROR_RETURN(_bcm_td_macroflow_hash_info_get(unit, type, 10554 &hash_info)); 10555 /* _bcm_td_macroflow_param_get fetches sub field base, min offset, 10556 * max offset, stride offset and concatenation values currently configured 10557 * in the hardware for the given type. 10558 */ 10559 BCM_IF_ERROR_RETURN 10560 (_bcm_td_macroflow_param_get(unit, type, &sub_field_base, &min_offset, 10561 &max_offset, &stride_offset, 10562 &concat_enable)); 10563 10564 if (arg < -1 || arg >= sub_field_base[8]) { 10565 return BCM_E_PARAM; 10566 } 10567 10568 switch (type) { 10569 case bcmSwitchMacroFlowHashMinOffset: 10570 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10571 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 10572 case bcmSwitchMacroFlowTrunkHashMinOffset: 10573 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 10574 #endif 10575 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10576 case bcmSwitchMacroFlowHashOverlayMinOffset: 10577 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 10578 10579 if (arg == min_offset) { 10580 return BCM_E_NONE; 10581 } else if ((max_offset > 0) && (arg > max_offset)) { 10582 return BCM_E_PARAM; 10583 } 10584 min_offset = arg == -1 ? 0 : arg; 10585 break; 10586 case bcmSwitchMacroFlowHashMaxOffset: 10587 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10588 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 10589 case bcmSwitchMacroFlowTrunkHashMaxOffset: 10590 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 10591 #endif 10592 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10593 case bcmSwitchMacroFlowHashOverlayMaxOffset: 10594 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 10595 10596 if (arg == max_offset) { 10597 return BCM_E_NONE; 10598 } else if ((arg < min_offset) && (arg != -1)) { 10599 return BCM_E_PARAM; 10600 } 10601 max_offset = arg == -1 ? sub_field_base[8] - 1 : arg; 10602 break; 10603 case bcmSwitchMacroFlowHashStrideOffset: 10604 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10605 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 10606 case bcmSwitchMacroFlowTrunkHashStrideOffset: 10607 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 10608 #endif 10609 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10610 case bcmSwitchMacroFlowHashOverlayStrideOffset: 10611 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 10612 10613 if (arg == stride_offset) { 10614 return BCM_E_NONE; 10615 } else if (arg < 0) { 10616 return BCM_E_PARAM; 10617 } 10618 stride_offset = arg; 10619 break; 10620 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10621 case bcmSwitchMacroFlowEcmpHashConcatEnable: 10622 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 10623 case bcmSwitchMacroFlowTrunkHashConcatEnable: 10624 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 10625 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10626 case bcmSwitchMacroFlowEcmpHashOverlayConcatEnable: 10627 #endif 10628 #ifdef BCM_TOMAHAWK_SUPPORT 10629 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 10630 #endif 10631 if (arg == concat_enable) { 10632 return BCM_E_NONE; 10633 } else if (!((arg == 0) || (arg == 1))) { 10634 return BCM_E_PARAM; 10635 } 10636 concat_enable = arg; 10637 break; 10638 #endif 10639 default: 10640 return BCM_E_INTERNAL; 10641 } 10642 10643 if (stride_offset == 0 && min_offset != max_offset) { 10644 stride_offset = 1; 10645 } 10646 10647 if (((type == bcmSwitchMacroFlowHashStrideOffset) 10648 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10649 || (type == bcmSwitchMacroFlowHigigTrunkHashStrideOffset) 10650 || (type == bcmSwitchMacroFlowTrunkHashStrideOffset) 10651 || (type == bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset) 10652 #endif 10653 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10654 || (type == bcmSwitchMacroFlowHashOverlayStrideOffset) 10655 #endif 10656 ) && (stride_offset == 1) && (min_offset == max_offset)) { 10657 max_offset += stride_offset; 10658 } 10659 10660 offset = min_offset; 10661 for (index = 0; index <= soc_mem_index_max(unit, hash_info.regmem); 10662 index++) { 10663 for (sub_sel = 0; sub_sel < 7; sub_sel++) { 10664 if (offset < sub_field_base[sub_sel + 1]) { 10665 break; 10666 } 10667 } 10668 10669 SOC_IF_ERROR_RETURN 10670 (soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 10671 index, &entry)); 10672 10673 soc_mem_field32_set(unit, hash_info.regmem, &entry, 10674 hash_info.sub_f, sub_sel); 10675 soc_mem_field32_set(unit, hash_info.regmem, &entry, 10676 hash_info.offset_f, offset - sub_field_base[sub_sel]); 10677 if (hash_info.concat_f != -1) { 10678 soc_mem_field32_set(unit, hash_info.regmem, &entry, 10679 hash_info.concat_f, concat_enable); 10680 } 10681 10682 SOC_IF_ERROR_RETURN 10683 (soc_mem_write(unit, hash_info.regmem, MEM_BLOCK_ANY, 10684 index, &entry)); 10685 offset += stride_offset; 10686 if (offset > max_offset) { 10687 offset = min_offset; 10688 } 10689 } 10690 10691 return BCM_E_NONE; 10692 } 10693 #endif /* BCM_TRIDENT_SUPPORT */ 10694 10695 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 10696 STATIC int 10697 _bcm_td2_random_hash_seed_get(int unit, hash_offset_info_t *hash_info, int seed, 10698 int *offset, int *subsel) 10699 { 10700 int concat, random; 10701 uint32 hash_entry[SOC_MAX_MEM_WORDS]; 10702 10703 /* Check for hash Concatenation */ 10704 SOC_IF_ERROR_RETURN 10705 (soc_mem_read(unit, hash_info->regmem, 10706 MEM_BLOCK_ANY, 0, &hash_entry)); 10707 concat = soc_mem_field32_get(unit, hash_info->regmem, &hash_entry, 10708 hash_info->concat_f); 10709 10710 /* Generate random number for the seed as described in C standards */ 10711 random = seed * 1103515245 + 12345; 10712 /* random_seed / 65536) % 32768 */ 10713 random = (random >> 16) & 0x7FFF; 10714 10715 if (concat) { 10716 *offset = random & 0x3f; 10717 /* Use HASH A0_A1_B0_B1 */ 10718 *subsel = 0; 10719 } else { 10720 *offset = random & 0xf; 10721 /* User any of hash A0, A1, B0, B1 */ 10722 *subsel = (random & 0x30) >> 4; 10723 } 10724 10725 return BCM_E_NONE; 10726 } 10727 10728 STATIC int 10729 _bcm_td2_macroflow_hash_get(int unit, bcm_switch_control_t type, int *arg) 10730 { 10731 uint32 hash_entry[SOC_MAX_MEM_WORDS]; 10732 hash_offset_info_t hash_info; 10733 10734 sal_memset(&hash_info, 0, sizeof(hash_offset_info_t)); 10735 hash_info.regmem = RTAG7_FLOW_BASED_HASHm; 10736 10737 switch(type) 10738 { 10739 /* Get RTAG7 Macro Flow Concatenation */ 10740 case bcmSwitchMacroFlowEcmpHashConcatEnable: 10741 hash_info.concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 10742 break; 10743 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10744 /* Set RTAG7 Macro Flow Concatenation */ 10745 case bcmSwitchMacroFlowEcmpHashOverlayConcatEnable: 10746 if ((soc_feature(unit, soc_feature_riot) || 10747 soc_feature(unit, soc_feature_multi_level_ecmp))) { 10748 hash_info.concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL1f; 10749 } else { 10750 return BCM_E_UNAVAIL; 10751 } 10752 break; 10753 #endif 10754 10755 #ifdef BCM_TOMAHAWK_SUPPORT 10756 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 10757 if (SOC_IS_TOMAHAWK(unit)) { 10758 hash_info.concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL2f; 10759 } else { 10760 return BCM_E_UNAVAIL; 10761 } 10762 break; 10763 #endif /* BCM_TOMAHAWK_SUPPORT */ 10764 10765 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 10766 hash_info.concat_f = CONCATENATE_HASH_FIELDS_LBID_OR_ENTROPY_LABELf; 10767 break; 10768 10769 case bcmSwitchMacroFlowTrunkHashConcatEnable: 10770 hash_info.concat_f = CONCATENATE_HASH_FIELDS_TRUNKf; 10771 break; 10772 10773 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 10774 hash_info.concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNKf; 10775 break; 10776 10777 /* Get RTAG7 Macro Flow Hash Seed cannot be supported as the 10778 * seed values being programmed are random. 10779 */ 10780 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10781 case bcmSwitchMacroFlowECMPOverlayHashSeed: 10782 #endif 10783 case bcmSwitchMacroFlowHigigTrunkHashSeed: 10784 #if defined(BCM_TOMAHAWK3_SUPPORT) 10785 if (SOC_IS_TOMAHAWK3(unit)) { 10786 return BCM_E_UNAVAIL; 10787 } else 10788 #endif /* BCM_TOMAHAWK3_SUPPORT */ 10789 { 10790 return BCM_E_PARAM; 10791 } 10792 10793 case bcmSwitchMacroFlowECMPHashSeed: 10794 case bcmSwitchMacroFlowECMPUnderlayHashSeed: 10795 case bcmSwitchMacroFlowLoadBalanceHashSeed: 10796 case bcmSwitchMacroFlowTrunkHashSeed: 10797 default: 10798 return BCM_E_PARAM; 10799 } 10800 10801 if (soc_mem_is_valid(unit, hash_info.regmem)) { 10802 sal_memset(&hash_entry, 0, sizeof(uint32) * SOC_MAX_MEM_WORDS); 10803 10804 SOC_IF_ERROR_RETURN 10805 (soc_mem_read(unit, hash_info.regmem, 10806 MEM_BLOCK_ANY, 0, &hash_entry)); 10807 *arg = soc_mem_field32_get(unit, hash_info.regmem, &hash_entry, 10808 hash_info.concat_f); 10809 } else { 10810 return BCM_E_UNAVAIL; 10811 } 10812 10813 return BCM_E_NONE; 10814 } 10815 10816 10817 STATIC int 10818 _bcm_td2_macroflow_hash_set(int unit, bcm_switch_control_t type, int arg) 10819 { 10820 soc_mem_t hash_sel_regmem; 10821 uint32 hash_entry[SOC_MAX_MEM_WORDS]; 10822 hash_offset_info_t hash_info; 10823 soc_field_t hash_flow_select[5]; 10824 uint32 rval; 10825 int index = 0, min, max; 10826 int offset=0, subsel=0; 10827 10828 sal_memset(&hash_info, 0, sizeof(hash_offset_info_t)); 10829 sal_memset(&hash_flow_select, 0, sizeof(hash_flow_select)); 10830 10831 hash_sel_regmem = RTAG7_HASH_SELr; 10832 hash_info.regmem = RTAG7_FLOW_BASED_HASHm; 10833 10834 switch(type) 10835 { 10836 /* Set RTAG7 Macro Flow Hash Seed */ 10837 case bcmSwitchMacroFlowECMPHashSeed: 10838 hash_info.sub_f = SUB_SEL_ECMPf; 10839 hash_info.offset_f = OFFSET_ECMPf; 10840 hash_info.concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 10841 hash_flow_select[index++] = USE_FLOW_SEL_MPLS_ECMPf; 10842 hash_flow_select[index++] = USE_FLOW_SEL_L2GRE_ECMPf; 10843 hash_flow_select[index++] = USE_FLOW_SEL_VXLAN_ECMPf; 10844 hash_flow_select[index++] = USE_FLOW_SEL_RH_ECMPf; 10845 if (soc_feature(unit, soc_feature_td3_dlb)) { 10846 hash_flow_select[index++] = USE_FLOW_SEL_DLB_ECMPf; 10847 } 10848 break; 10849 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 10850 /* Set RTAG7 Macro Flow Hash Seed */ 10851 case bcmSwitchMacroFlowECMPOverlayHashSeed: 10852 if (soc_feature(unit, soc_feature_riot) || 10853 soc_feature(unit, soc_feature_multi_level_ecmp)) { 10854 hash_info.sub_f = SUB_SEL_ECMP_LEVEL1f; 10855 hash_info.offset_f = OFFSET_ECMP_LEVEL1f; 10856 hash_info.concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL1f; 10857 hash_flow_select[index++] = USE_FLOW_SEL_MPLS_ECMPf; 10858 hash_flow_select[index++] = USE_FLOW_SEL_L2GRE_ECMPf; 10859 hash_flow_select[index++] = USE_FLOW_SEL_VXLAN_ECMPf; 10860 hash_flow_select[index++] = USE_FLOW_SEL_RH_ECMPf; 10861 break; 10862 } else { 10863 return BCM_E_UNAVAIL; 10864 } 10865 #endif 10866 case bcmSwitchMacroFlowLoadBalanceHashSeed: 10867 hash_info.sub_f = SUB_SEL_LBID_OR_ENTROPY_LABELf; 10868 hash_info.offset_f = OFFSET_LBID_OR_ENTROPY_LABELf; 10869 hash_info.concat_f = CONCATENATE_HASH_FIELDS_LBID_OR_ENTROPY_LABELf; 10870 hash_flow_select[index++] = USE_FLOW_SEL_LBID_UCf; 10871 hash_flow_select[index++] = USE_FLOW_SEL_LBID_NONUCf; 10872 hash_flow_select[index++] = USE_FLOW_SEL_ENTROPY_LABELf; 10873 break; 10874 10875 #ifdef BCM_TOMAHAWK_SUPPORT 10876 case bcmSwitchMacroFlowECMPUnderlayHashSeed: 10877 if (SOC_IS_TOMAHAWKX(unit)) { 10878 hash_info.sub_f = SUB_SEL_ECMP_LEVEL2f; 10879 hash_info.offset_f = OFFSET_ECMP_LEVEL2f; 10880 hash_info.concat_f = CONCATENATE_HASH_FIELDS_ECMP_LEVEL2f; 10881 hash_flow_select[index++] = USE_FLOW_SEL_MPLS_ECMPf; 10882 hash_flow_select[index++] = USE_FLOW_SEL_L2GRE_ECMPf; 10883 hash_flow_select[index++] = USE_FLOW_SEL_VXLAN_ECMPf; 10884 hash_flow_select[index++] = USE_FLOW_SEL_RH_ECMPf; 10885 } else { 10886 return BCM_E_UNAVAIL; 10887 } 10888 break; 10889 #endif /* BCM_TOMAHAWK_SUPPORT */ 10890 10891 case bcmSwitchMacroFlowTrunkHashSeed: 10892 hash_info.sub_f = SUB_SEL_TRUNKf; 10893 hash_info.offset_f = OFFSET_TRUNKf; 10894 hash_info.concat_f = CONCATENATE_HASH_FIELDS_TRUNKf; 10895 hash_flow_select[index++] = USE_FLOW_SEL_RH_LAGf; 10896 hash_flow_select[index++] = USE_FLOW_SEL_VPLAGf; 10897 hash_flow_select[index++] = USE_FLOW_SEL_TRUNK_NONUCf; 10898 break; 10899 10900 case bcmSwitchMacroFlowHigigTrunkHashSeed: 10901 #if defined(BCM_TOMAHAWK3_SUPPORT) 10902 if (SOC_IS_TOMAHAWK3(unit)) { 10903 return BCM_E_UNAVAIL; 10904 } 10905 #endif /* BCM_TOMAHAWK3_SUPPORT */ 10906 10907 hash_info.sub_f = SUB_SEL_HG_TRUNKf; 10908 hash_info.offset_f = OFFSET_HG_TRUNKf; 10909 hash_info.concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNKf; 10910 hash_flow_select[index++] = USE_FLOW_SEL_HG_TRUNK_FAILOVERf; 10911 hash_flow_select[index++] = USE_FLOW_SEL_HG_TRUNK_NONUCf; 10912 hash_flow_select[index++] = USE_FLOW_SEL_HG_TRUNK_UCf; 10913 hash_flow_select[index++] = USE_FLOW_SEL_DLB_HGTf; 10914 hash_flow_select[index++] = USE_FLOW_SEL_RH_HGTf; 10915 break; 10916 10917 default: 10918 return BCM_E_PARAM; 10919 } 10920 10921 if (!soc_mem_is_valid(unit, hash_info.regmem)) { 10922 return BCM_E_UNAVAIL; 10923 } 10924 min = soc_mem_index_min(unit, hash_info.regmem); 10925 max = soc_mem_index_max(unit, hash_info.regmem); 10926 10927 /* Set random generated hash offset and sub select */ 10928 SOC_IF_ERROR_RETURN 10929 (_bcm_td2_random_hash_seed_get(unit, &hash_info, arg, 10930 &offset, &subsel)); 10931 10932 for (index = min; index <= max; index++ ) { 10933 SOC_IF_ERROR_RETURN 10934 (soc_mem_read(unit, hash_info.regmem, 10935 MEM_BLOCK_ANY, index, &hash_entry)); 10936 soc_mem_field32_set(unit, hash_info.regmem, &hash_entry, 10937 hash_info.sub_f, subsel); 10938 soc_mem_field32_set(unit, hash_info.regmem, &hash_entry, 10939 hash_info.offset_f, offset); 10940 SOC_IF_ERROR_RETURN 10941 (soc_mem_write(unit, hash_info.regmem, 10942 MEM_BLOCK_ALL, index, &hash_entry)); 10943 } 10944 10945 /* Enable Macro flow bits */ 10946 SOC_IF_ERROR_RETURN 10947 (soc_reg32_get(unit, hash_sel_regmem, REG_PORT_ANY, 0, &rval)); 10948 10949 for (index = 0; 10950 index < (sizeof(hash_flow_select)/sizeof(soc_field_t)); index++ ) { 10951 if (soc_reg_field_valid(unit, hash_sel_regmem, 10952 hash_flow_select[index])) { 10953 soc_reg_field_set(unit, hash_sel_regmem, &rval, hash_flow_select[index], 1); 10954 } 10955 } 10956 10957 SOC_IF_ERROR_RETURN 10958 (soc_reg32_set(unit, hash_sel_regmem, REG_PORT_ANY, 0, rval)); 10959 10960 return BCM_E_NONE; 10961 } 10962 #endif /* BCM_TRIDENT2_SUPPORT || BCM_TRIUMPH3_SUPPORT */ 10963 10964 #if defined(BCM_TRIDENT2_SUPPORT) 10965 STATIC int 10966 _bcm_td2_port_asf_enable_set(int unit, bcm_port_t port, int enable) 10967 { 10968 uint32 rval; 10969 int phy_port; 10970 uint32 asf_speed_mode; 10971 egr_edb_xmit_ctrl_entry_t entry; 10972 10973 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10974 if (phy_port == -1) { 10975 return BCM_E_PORT; 10976 } 10977 10978 /*Stop enquing any packets into the cut-through FIFO */ 10979 SOC_IF_ERROR_RETURN(READ_ASF_PORT_CFGr(unit, port, &rval)); 10980 asf_speed_mode = soc_reg_field_get(unit, ASF_PORT_CFGr, rval, 10981 ASF_PORT_SPEEDf); 10982 soc_reg_field_set(unit, ASF_PORT_CFGr, &rval, 10983 ASF_PORT_SPEEDf, 0); 10984 SOC_IF_ERROR_RETURN(WRITE_ASF_PORT_CFGr(unit, port, rval)); 10985 10986 if (!enable) { 10987 /*Wait for 8ms for all the data drained from the cut-through FIFO*/ 10988 sal_usleep(8000); 10989 } 10990 10991 /*Configure the EP block*/ 10992 SOC_IF_ERROR_RETURN(soc_mem_read(unit, EGR_EDB_XMIT_CTRLm, 10993 MEM_BLOCK_ALL, phy_port, &entry)); 10994 if (SOC_PBMP_MEMBER(SOC_INFO(unit).oversub_pbm, port)) { 10995 soc_mem_field32_set(unit, EGR_EDB_XMIT_CTRLm, &entry, 10996 WAIT_FOR_2ND_MOPf, enable ? 0 : 1); 10997 } else { 10998 soc_mem_field32_set(unit, EGR_EDB_XMIT_CTRLm, &entry, 10999 WAIT_FOR_MOPf, enable ? 0: 1); 11000 } 11001 SOC_IF_ERROR_RETURN(soc_mem_write(unit, EGR_EDB_XMIT_CTRLm, 11002 MEM_BLOCK_ALL, phy_port, &entry)); 11003 11004 /*Set/clear the cut-through enable bit*/ 11005 soc_reg_field_set(unit, ASF_PORT_CFGr, &rval, 11006 MC_ASF_ENABLEf, enable ? 1 : 0); 11007 soc_reg_field_set(unit, ASF_PORT_CFGr, &rval, 11008 UC_ASF_ENABLEf, enable ? 1 : 0); 11009 SOC_IF_ERROR_RETURN(WRITE_ASF_PORT_CFGr(unit, port, rval)); 11010 11011 if (enable) { 11012 /*Wait for 1us for UC_ASF_ENABLE/MC_ASF_ENABLE change takes effect*/ 11013 sal_usleep(1); 11014 } 11015 11016 /*Restore ASF_PORT_CFG.ASF_PORT_SPEED to the original value*/ 11017 soc_reg_field_set(unit, ASF_PORT_CFGr, &rval, 11018 ASF_PORT_SPEEDf, asf_speed_mode); 11019 SOC_IF_ERROR_RETURN(WRITE_ASF_PORT_CFGr(unit, port, rval)); 11020 11021 return BCM_E_NONE; 11022 } 11023 11024 STATIC int 11025 _bcm_td2_port_asf_enable_get(int unit, bcm_port_t port, int *enable) 11026 { 11027 uint32 rval; 11028 11029 SOC_IF_ERROR_RETURN(READ_ASF_PORT_CFGr(unit, port, &rval)); 11030 *enable = (soc_reg_field_get(unit, ASF_PORT_CFGr, rval, UC_ASF_ENABLEf)) 11031 & (soc_reg_field_get(unit, ASF_PORT_CFGr, rval, MC_ASF_ENABLEf)); 11032 11033 return BCM_E_NONE; 11034 } 11035 #endif 11036 11037 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 11038 /* 11039 * Update following memory/field 11040 * FP_METER_CONTROLm, PACKET_IFG_BYTESf 11041 * EGR_COUNTER_CONTROLm, PACKET_IFG_BYTESf 11042 * EGR_COUNTER_CONTROLm, PACKET_IFG_BYTES_2f 11043 * EGR_SHAPING_CONTROLm, PACKET_IFG_BYTESf 11044 * EGR_SHAPING_CONTROLm, PACKET_IFG_BYTES_2f 11045 */ 11046 STATIC int 11047 _bcm_xgs3_meter_adjust_set(int unit, bcm_port_t port, int arg) 11048 { 11049 int len, max_val; 11050 int i; 11051 soc_mem_t mem[3] = { FP_METER_CONTROLm, 11052 EGR_COUNTER_CONTROLm, 11053 EGR_SHAPING_CONTROLm }; 11054 11055 if (!soc_feature(unit, soc_feature_meter_adjust)) { 11056 return BCM_E_UNAVAIL; 11057 } 11058 11059 #if defined(BCM_HGPROXY_COE_SUPPORT) 11060 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 11061 BCM_GPORT_IS_SET(port) && 11062 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port)) { 11063 soc_field_t fields[2]; 11064 uint32 values[2]; 11065 fields[0] = PACKET_IFG_BYTESf; 11066 fields[1] = PACKET_IFG_BYTES_2f; 11067 values[0] = arg; 11068 values[1] = arg; 11069 return bcm_esw_port_egr_lport_fields_set( 11070 unit, port, EGR_COUNTER_CONTROLm, 2, 11071 fields, values); 11072 } 11073 #endif /* defined(BCM_HGPROXY_COE_SUPPORT) */ 11074 11075 for (i = 0; i < 3 ; ++i ) { 11076 if (SOC_MEM_FIELD_VALID(unit, mem[i], PACKET_IFG_BYTESf)) { 11077 len = soc_mem_field_length(unit, mem[i], PACKET_IFG_BYTESf); 11078 max_val = (1 << len) - 1; 11079 if (arg < 0 || arg > max_val) { 11080 return BCM_E_PARAM; 11081 } 11082 SOC_IF_ERROR_RETURN( 11083 soc_mem_field32_modify(unit, mem[i], port, 11084 PACKET_IFG_BYTESf, arg)); 11085 } 11086 11087 if (SOC_MEM_FIELD_VALID(unit, mem[i], PACKET_IFG_BYTES_2f)) { 11088 len = soc_mem_field_length(unit, mem[i], PACKET_IFG_BYTES_2f); 11089 max_val = (1 << len) - 1; 11090 if (arg < 0 || arg > max_val) { 11091 return BCM_E_PARAM; 11092 } 11093 SOC_IF_ERROR_RETURN( 11094 soc_mem_field32_modify(unit, mem[i], port, 11095 PACKET_IFG_BYTES_2f, arg)); 11096 } 11097 } 11098 11099 return BCM_E_NONE; 11100 } 11101 11102 STATIC int 11103 _bcm_xgs3_meter_adjust_get(int unit, bcm_port_t port, int *arg) 11104 { 11105 uint32 val; 11106 11107 #if defined(BCM_HGPROXY_COE_SUPPORT) 11108 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 11109 BCM_GPORT_IS_SET(port) && 11110 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port)) { 11111 return bcm_esw_port_egr_lport_field_get( 11112 unit, port, EGR_COUNTER_CONTROLm, 11113 PACKET_IFG_BYTESf, (uint32*)arg); 11114 } 11115 #endif /* defined(BCM_HGPROXY_COE_SUPPORT) */ 11116 11117 SOC_IF_ERROR_RETURN( 11118 READ_EGR_COUNTER_CONTROLm(unit, MEM_BLOCK_ANY, port, &val)); 11119 *arg = soc_mem_field32_get(unit, EGR_COUNTER_CONTROLm, &val, 11120 PACKET_IFG_BYTESf); 11121 return BCM_E_NONE; 11122 } 11123 11124 /* 11125 * Update following memory/field 11126 * EGR_SHAPING_CONTROLm, PACKET_IFG_BYTESf 11127 * EGR_SHAPING_CONTROLm, PACKET_IFG_BYTES_2f 11128 */ 11129 STATIC int 11130 _bcm_xgs3_shaper_adjust_set(int unit, bcm_port_t port, int arg) 11131 { 11132 int len, max_val; 11133 soc_mem_t mem = EGR_SHAPING_CONTROLm; 11134 11135 if (!soc_feature(unit, soc_feature_meter_adjust)) { 11136 return BCM_E_UNAVAIL; 11137 } 11138 11139 #if defined(BCM_HGPROXY_COE_SUPPORT) 11140 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 11141 BCM_GPORT_IS_SET(port) && 11142 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port)) { 11143 soc_field_t fields[2]; 11144 uint32 values[2]; 11145 fields[0] = PACKET_IFG_BYTESf; 11146 fields[1] = PACKET_IFG_BYTES_2f; 11147 values[0] = arg; 11148 values[1] = arg; 11149 return bcm_esw_port_egr_lport_fields_set( 11150 unit, port, EGR_SHAPING_CONTROLm, 2, 11151 fields, values); 11152 } 11153 #endif /* defined(BCM_HGPROXY_COE_SUPPORT) */ 11154 11155 if (SOC_MEM_FIELD_VALID(unit, mem, PACKET_IFG_BYTESf)) { 11156 len = soc_mem_field_length(unit, mem, PACKET_IFG_BYTESf); 11157 max_val = (1 << len) - 1; 11158 if (arg < 0 || arg > max_val) { 11159 return BCM_E_PARAM; 11160 } 11161 SOC_IF_ERROR_RETURN( 11162 soc_mem_field32_modify(unit, mem, port, 11163 PACKET_IFG_BYTESf, arg)); 11164 } 11165 11166 if (SOC_MEM_FIELD_VALID(unit, mem, PACKET_IFG_BYTES_2f)) { 11167 len = soc_mem_field_length(unit, mem, PACKET_IFG_BYTES_2f); 11168 max_val = (1 << len) - 1; 11169 if (arg < 0 || arg > max_val) { 11170 return BCM_E_PARAM; 11171 } 11172 SOC_IF_ERROR_RETURN( 11173 soc_mem_field32_modify(unit, mem, port, 11174 PACKET_IFG_BYTES_2f, arg)); 11175 } 11176 11177 return BCM_E_NONE; 11178 } 11179 11180 STATIC int 11181 _bcm_xgs3_shaper_adjust_get(int unit, bcm_port_t port, int *arg) 11182 { 11183 uint32 val; 11184 11185 #if defined(BCM_HGPROXY_COE_SUPPORT) 11186 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 11187 BCM_GPORT_IS_SET(port) && 11188 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port)) { 11189 return bcm_esw_port_egr_lport_field_get( 11190 unit, port, EGR_SHAPING_CONTROLm, 11191 PACKET_IFG_BYTESf, (uint32*)arg); 11192 } 11193 #endif /* defined(BCM_HGPROXY_COE_SUPPORT) */ 11194 11195 SOC_IF_ERROR_RETURN( 11196 READ_EGR_SHAPING_CONTROLm(unit, MEM_BLOCK_ANY, port, &val)); 11197 *arg = soc_mem_field32_get(unit, EGR_SHAPING_CONTROLm, &val, 11198 PACKET_IFG_BYTESf); 11199 return BCM_E_NONE; 11200 } 11201 #endif 11202 11203 #if defined(BCM_HURRICANE2_SUPPORT) 11204 /* 11205 * Update following reg/field 11206 * FP_METER_CONTROLr, PACKET_IFG_BYTESf 11207 * EGR_COUNTER_CONTROLr, PACKET_IFG_BYTESf 11208 * EGR_COUNTER_CONTROLr, PACKET_IFG_BYTES_2f 11209 * EFP_METER_CONTROL_2r, PACKET_IFG_BYTESf 11210 * EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf 11211 */ 11212 STATIC int 11213 _bcm_hr2_meter_adjust_set(int unit, bcm_port_t port, int arg) 11214 { 11215 int len, max_val; 11216 int i; 11217 soc_reg_t reg[4] = { FP_METER_CONTROLr, 11218 EGR_COUNTER_CONTROLr, 11219 EFP_METER_CONTROL_2r, 11220 EGR_SHAPING_CONTROLr }; 11221 11222 for (i = 0; i < 4 ; ++i ) { 11223 if (SOC_REG_FIELD_VALID(unit, reg[i], PACKET_IFG_BYTESf)) { 11224 len = soc_reg_field_length(unit, reg[i], PACKET_IFG_BYTESf); 11225 max_val = (1 << len) - 1; 11226 if (arg < 0 || arg > max_val) { 11227 return BCM_E_PARAM; 11228 } 11229 BCM_IF_ERROR_RETURN( 11230 soc_reg_field32_modify(unit, reg[i], port, 11231 PACKET_IFG_BYTESf, arg)); 11232 } 11233 11234 if (SOC_REG_FIELD_VALID(unit, reg[i], PACKET_IFG_BYTES_2f)) { 11235 len = soc_reg_field_length(unit, reg[i], PACKET_IFG_BYTES_2f); 11236 max_val = (1 << len) - 1; 11237 if (arg < 0 || arg > max_val) { 11238 return BCM_E_PARAM; 11239 } 11240 BCM_IF_ERROR_RETURN( 11241 soc_reg_field32_modify(unit, reg[i], port, 11242 PACKET_IFG_BYTES_2f, arg)); 11243 } 11244 } 11245 11246 return BCM_E_NONE; 11247 } 11248 11249 STATIC int 11250 _bcm_hr2_meter_adjust_get(int unit, bcm_port_t port, int *arg) 11251 { 11252 uint32 val; 11253 11254 BCM_IF_ERROR_RETURN( 11255 READ_EGR_COUNTER_CONTROLr(unit, port, &val)); 11256 *arg = soc_reg_field_get(unit, EGR_COUNTER_CONTROLr, val, 11257 PACKET_IFG_BYTESf); 11258 11259 return BCM_E_NONE; 11260 } 11261 11262 /* 11263 * Update following reg/field 11264 * EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf 11265 */ 11266 STATIC int 11267 _bcm_hr2_shaper_adjust_set(int unit, bcm_port_t port, int arg) 11268 { 11269 int len, max_val; 11270 soc_reg_t reg = EGR_SHAPING_CONTROLr; 11271 11272 if (SOC_REG_FIELD_VALID(unit, reg, PACKET_IFG_BYTESf)) { 11273 len = soc_reg_field_length(unit, reg, PACKET_IFG_BYTESf); 11274 max_val = (1 << len) - 1; 11275 if (arg < 0 || arg > max_val) { 11276 return BCM_E_PARAM; 11277 } 11278 BCM_IF_ERROR_RETURN( 11279 soc_reg_field32_modify(unit, reg, port, 11280 PACKET_IFG_BYTESf, arg)); 11281 } 11282 11283 return BCM_E_NONE; 11284 } 11285 11286 STATIC int 11287 _bcm_hr2_shaper_adjust_get(int unit, bcm_port_t port, int *arg) 11288 { 11289 uint32 val; 11290 11291 BCM_IF_ERROR_RETURN( 11292 soc_reg32_get(unit, EGR_SHAPING_CONTROLr, port, 0, &val)); 11293 *arg = soc_reg_field_get(unit, EGR_SHAPING_CONTROLr, val, 11294 PACKET_IFG_BYTESf); 11295 11296 return BCM_E_NONE; 11297 } 11298 #endif /* BCM_HURRICANE2_SUPPORT */ 11299 11300 STATIC int 11301 _bcm_fb_mod_lb_set(int unit, bcm_port_t port, int arg) 11302 { 11303 if (soc_feature(unit, soc_feature_module_loopback)) { 11304 return _bcm_esw_port_config_set(unit, port, _bcmPortModuleLoopback, 11305 (arg ? 1 : 0)); 11306 } 11307 return BCM_E_UNAVAIL; 11308 } 11309 11310 STATIC int 11311 _bcm_fb_mod_lb_get(int unit, bcm_port_t port, int *arg) 11312 { 11313 if (soc_feature(unit, soc_feature_module_loopback)) { 11314 return _bcm_esw_port_config_get(unit, port, _bcmPortModuleLoopback, 11315 arg); 11316 } 11317 return BCM_E_UNAVAIL; 11318 } 11319 11320 #define BCM_RAPTOR_BMC_IFG_0 0 11321 #define BCM_RAPTOR_BMC_IFG_16 1 11322 #define BCM_RAPTOR_BMC_IFG_20 2 11323 #define BCM_RAPTOR_BMC_IFG_24 3 11324 11325 11326 #define BCM_SC_BMC_IFG_MAX 0x1f 11327 11328 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) \ 11329 || defined(BCM_SCORPION_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 11330 STATIC int 11331 _bcm_xgs3_ing_rate_limit_ifg_set(int unit, bcm_port_t port, int arg) 11332 { 11333 #if defined(BCM_RAPTOR1_SUPPORT) 11334 if (SOC_IS_RAPTOR(unit)) { 11335 int ifg_sel = 0; 11336 if (arg >= 20) { 11337 ifg_sel = BCM_RAPTOR_BMC_IFG_24; 11338 } else if (arg >= 16) { 11339 ifg_sel = BCM_RAPTOR_BMC_IFG_20; 11340 } else if (arg > 0) { 11341 ifg_sel = BCM_RAPTOR_BMC_IFG_16; 11342 } else if (arg == 0) { 11343 ifg_sel = BCM_RAPTOR_BMC_IFG_0; 11344 } else { /* arg < 0 */ 11345 return BCM_E_PARAM; 11346 } 11347 return soc_reg_field32_modify(unit, BKPMETERINGCONFIGr, port, 11348 IFG_ACCT_SELf, ifg_sel); 11349 } else 11350 #endif /* BCM_RAPTOR1_SUPPORT */ 11351 #if defined(BCM_SCORPION_SUPPORT) 11352 if (SOC_IS_SCORPION(unit)) { 11353 if (arg > BCM_SC_BMC_IFG_MAX) { 11354 arg = BCM_SC_BMC_IFG_MAX; 11355 } else if (arg < 0) { 11356 return BCM_E_PARAM; 11357 } 11358 return soc_reg_field32_modify(unit, BKPMETERINGCONFIG1r, port, 11359 PACKET_IFG_BYTESf, arg); 11360 } else 11361 #endif /* BCM_SCORPION_SUPPORT */ 11362 #if defined (BCM_RAVEN_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 11363 if (SOC_REG_FIELD_VALID(unit, BKPMETERINGCONFIG_EXTr, IFG_ACCT_SELf)) { 11364 if (arg > BCM_FB2_BMC_IFG_MAX) { 11365 arg = BCM_FB2_BMC_IFG_MAX; 11366 } else if (arg < 0) { 11367 return BCM_E_PARAM; 11368 } 11369 return soc_reg_field32_modify(unit, BKPMETERINGCONFIG_EXTr, port, 11370 IFG_ACCT_SELf, arg); 11371 } 11372 #endif /* BCM_RAVEN_SUPPORT || BCM_FIREBOLT2_SUPPORT || BCM_HURRICANE_SUPPORT */ 11373 return BCM_E_UNAVAIL; 11374 } 11375 11376 STATIC int 11377 _bcm_xgs3_ing_rate_limit_ifg_get(int unit, bcm_port_t port, int *arg) 11378 { 11379 uint32 bmc_reg; 11380 11381 #if defined(BCM_RAPTOR1_SUPPORT) 11382 if (SOC_IS_RAPTOR(unit)) { 11383 int ifg_sel; 11384 BCM_IF_ERROR_RETURN(READ_BKPMETERINGCONFIGr(unit, port, &bmc_reg)); 11385 ifg_sel = soc_reg_field_get(unit, BKPMETERINGCONFIGr, bmc_reg, 11386 IFG_ACCT_SELf); 11387 switch (ifg_sel) { 11388 case BCM_RAPTOR_BMC_IFG_24: 11389 *arg = 24; 11390 break; 11391 case BCM_RAPTOR_BMC_IFG_20: 11392 *arg = 20; 11393 break; 11394 case BCM_RAPTOR_BMC_IFG_16: 11395 *arg = 16; 11396 break; 11397 case BCM_RAPTOR_BMC_IFG_0: 11398 *arg = 0; 11399 break; 11400 } 11401 return BCM_E_NONE; 11402 } else 11403 #endif /* BCM_RAPTOR1_SUPPORT */ 11404 #if defined(BCM_SCORPION_SUPPORT) 11405 if (SOC_IS_SCORPION(unit)) { 11406 BCM_IF_ERROR_RETURN 11407 (READ_BKPMETERINGCONFIG1r(unit, port, &bmc_reg)); 11408 *arg = soc_reg_field_get(unit, BKPMETERINGCONFIG1r, bmc_reg, 11409 PACKET_IFG_BYTESf); 11410 return BCM_E_NONE; 11411 } else 11412 #endif /* BCM_SCORPION_SUPPORT */ 11413 #if defined (BCM_RAVEN_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 11414 if (SOC_REG_FIELD_VALID(unit, BKPMETERINGCONFIG_EXTr, IFG_ACCT_SELf)) { 11415 BCM_IF_ERROR_RETURN 11416 (READ_BKPMETERINGCONFIG_EXTr(unit, port, &bmc_reg)); 11417 *arg = soc_reg_field_get(unit, BKPMETERINGCONFIG_EXTr, bmc_reg, 11418 IFG_ACCT_SELf); 11419 return BCM_E_NONE; 11420 } 11421 #endif /* BCM_RAVEN_SUPPORT || BCM_FIREBOLT2_SUPPORT || BCM_HURRICANE_SUPPORT */ 11422 return BCM_E_UNAVAIL; 11423 } 11424 #endif /* BCM_RAPTOR_SUPPORT || BCM_FIREBOLT2_SUPPORT || BCM_HURRICANE_SUPPORT 11425 || BCM_SCORPION_SUPPORT */ 11426 11427 11428 11429 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 11430 STATIC int 11431 _bcm_xgs3_urpf_port_mode_set(int unit, bcm_port_t port, int arg) 11432 { 11433 if (!soc_feature(unit, soc_feature_urpf)) { 11434 return (BCM_E_UNAVAIL); 11435 } 11436 11437 switch (arg){ 11438 case BCM_SWITCH_URPF_DISABLE: 11439 case BCM_SWITCH_URPF_LOOSE: 11440 case BCM_SWITCH_URPF_STRICT: 11441 #ifdef BCM_TRIDENT2_SUPPORT 11442 #if defined(INCLUDE_L3) 11443 if (soc_feature(unit, soc_feature_virtual_port_routing) && 11444 (BCM_GPORT_IS_NIV_PORT(port) || 11445 BCM_GPORT_IS_EXTENDER_PORT(port) || 11446 BCM_GPORT_IS_VLAN_PORT(port))) { 11447 return _bcm_td2_vp_urpf_mode_set(unit, port, arg); 11448 } else 11449 #endif 11450 #endif /* BCM_TRIDENT2_SUPPORT */ 11451 { 11452 return _bcm_esw_port_config_set(unit, port, _bcmPortL3UrpfMode, arg); 11453 } 11454 default: 11455 return (BCM_E_PARAM); 11456 } 11457 return (BCM_E_PARAM); 11458 } 11459 11460 STATIC int 11461 _bcm_xgs3_urpf_def_gw_enable(int unit, bcm_port_t port, int arg) 11462 { 11463 int enable = (arg) ? TRUE : FALSE; 11464 11465 if (!soc_feature(unit, soc_feature_urpf)) { 11466 return (BCM_E_UNAVAIL); 11467 } 11468 11469 return _bcm_esw_port_config_set(unit, port, 11470 _bcmPortL3UrpfDefaultRoute, enable); 11471 } 11472 11473 STATIC int 11474 _bcm_xgs3_urpf_route_enable(int unit, int arg) 11475 { 11476 #ifdef INCLUDE_L3 11477 int orig_val, rv = BCM_E_NONE; 11478 uint32 reg_val; 11479 #ifdef ALPM_ENABLE 11480 #if defined(BCM_TOMAHAWK_SUPPORT) 11481 int hitbit_interval = 0; 11482 #endif 11483 #endif 11484 11485 if (!SOC_REG_FIELD_VALID(unit, L3_DEFIP_RPF_CONTROLr, DEFIP_RPF_ENABLEf)) { 11486 return (BCM_E_UNAVAIL); 11487 } 11488 11489 if (!soc_feature(unit, soc_feature_urpf)) { 11490 return (BCM_E_UNAVAIL); 11491 } 11492 11493 BCM_IF_ERROR_RETURN(READ_L3_DEFIP_RPF_CONTROLr(unit, ®_val)); 11494 11495 /* Handle nothing changed case. */ 11496 orig_val = soc_reg_field_get(unit, L3_DEFIP_RPF_CONTROLr, 11497 reg_val, DEFIP_RPF_ENABLEf); 11498 if (orig_val == (arg ? 1 : 0)) { 11499 return (BCM_E_NONE); 11500 } 11501 11502 #ifdef ALPM_ENABLE 11503 #if defined(BCM_TOMAHAWK_SUPPORT) 11504 if (soc_property_get(unit, spn_L3_ALPM_ENABLE, 0) && 11505 soc_feature(unit, soc_feature_alpm2) && ALPMC(unit) && !ALPM_HIT_SKIP(unit)) { 11506 hitbit_interval = alpm_dist_hitbit_interval_get(unit); 11507 if (hitbit_interval) { 11508 (void)alpm_dist_hitbit_enable_set(unit, 0); 11509 } 11510 } 11511 #endif 11512 #endif 11513 11514 /* State changed -> Delete all the routes. */ 11515 BCM_IF_ERROR_RETURN(bcm_xgs3_defip_del_all(unit)); 11516 11517 /* Destroy Hash/Avl quick lookup structure. */ 11518 BCM_IF_ERROR_RETURN(bcm_xgs3_l3_fbx_defip_deinit(unit)); 11519 11520 /* Set urpf route enable bit. */ 11521 BCM_IF_ERROR_RETURN 11522 (soc_reg_field32_modify(unit, L3_DEFIP_RPF_CONTROLr, REG_PORT_ANY, 11523 DEFIP_RPF_ENABLEf, (arg ? 1 : 0))); 11524 11525 11526 /* Reinit Hash/Avl quick lookup structure. */ 11527 BCM_IF_ERROR_RETURN(bcm_xgs3_l3_fbx_defip_init(unit)); 11528 11529 /* Lock the DEFIP tables so the SOC TCAM scanning logic doesn't 11530 * trip up on the URPF reconfiguration. 11531 */ 11532 soc_mem_lock(unit, L3_DEFIPm); 11533 if (SOC_MEM_IS_ENABLED(unit, L3_DEFIP_PAIR_128m)) { 11534 soc_mem_lock(unit, L3_DEFIP_PAIR_128m); 11535 } 11536 11537 #if defined(BCM_TRIDENT2PLUS_SUPPORT) && defined(ALPM_ENABLE) 11538 if (SOC_IS_TRIDENT2PLUS(unit)) { 11539 if (BCM_SUCCESS(rv)) { 11540 rv = soc_alpm_ipmc_war(unit, FALSE); 11541 } 11542 11543 if (SOC_MEM_IS_ENABLED(unit, L3_DEFIP_PAIR_128m)) { 11544 if (BCM_SUCCESS(rv)) { 11545 rv = soc_alpm_128_ipmc_war(unit, FALSE); 11546 } 11547 } 11548 } 11549 #endif 11550 11551 #ifdef BCM_TRIUMPH3_SUPPORT 11552 if (SOC_IS_TRIUMPH3(unit) && 11553 !(BCM_TR3_ESM_LPM_TBL_PRESENT(unit, EXT_IPV4_DEFIPm) && 11554 BCM_TR3_ESM_LPM_TBL_PRESENT(unit, EXT_IPV6_64_DEFIPm) && 11555 BCM_TR3_ESM_LPM_TBL_PRESENT(unit, EXT_IPV6_128_DEFIPm))) { 11556 rv = _bcm_tr3_l3_defip_urpf_enable(unit, arg); 11557 } 11558 #endif 11559 11560 #ifdef BCM_TRIDENT2_SUPPORT 11561 if (BCM_SUCCESS(rv) && 11562 (SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || 11563 SOC_IS_TRIDENT3X(unit))) { 11564 /* BCM_SUCCESS test unneeded, but likely to avoid 11565 * Coverity complaints */ 11566 rv = _bcm_l3_defip_urpf_enable(unit, arg); 11567 } 11568 #endif 11569 SOC_CONTROL_LOCK(unit); 11570 SOC_CONTROL(unit)->l3_defip_urpf = arg ? 1 : 0; 11571 SOC_CONTROL_UNLOCK(unit); 11572 11573 /* Clear h/w memory before use */ 11574 if (BCM_SUCCESS(rv)) { 11575 rv = soc_mem_clear(unit, L3_DEFIPm, MEM_BLOCK_ALL, 0); 11576 #if defined(BCM_TRIDENT2PLUS_SUPPORT) && defined(ALPM_ENABLE) 11577 if (SOC_IS_TRIDENT2PLUS(unit) && BCM_SUCCESS(rv)) { 11578 rv = soc_alpm_ipmc_war(unit, TRUE); 11579 } 11580 #endif 11581 } 11582 if (SOC_MEM_IS_ENABLED(unit, L3_DEFIP_PAIR_128m)) { 11583 if (BCM_SUCCESS(rv)) { 11584 rv = soc_mem_clear(unit, L3_DEFIP_PAIR_128m, 11585 MEM_BLOCK_ALL, 0); 11586 #if defined(BCM_TRIDENT2PLUS_SUPPORT) && defined(ALPM_ENABLE) 11587 if (SOC_IS_TRIDENT2PLUS(unit) && BCM_SUCCESS(rv)) { 11588 rv = soc_alpm_128_ipmc_war(unit, TRUE); 11589 } 11590 #endif 11591 } 11592 soc_mem_unlock(unit, L3_DEFIP_PAIR_128m); 11593 } 11594 11595 soc_mem_unlock(unit, L3_DEFIPm); 11596 /* Must release the locks before return. */ 11597 11598 #ifdef ALPM_ENABLE 11599 #if defined(BCM_TOMAHAWK_SUPPORT) 11600 if (soc_property_get(unit, spn_L3_ALPM_ENABLE, 0) && 11601 soc_feature(unit, soc_feature_alpm2) && ALPMC(unit) && !ALPM_HIT_SKIP(unit)) { 11602 if (hitbit_interval) { 11603 alpm_dist_hitbit_enable_set(unit, hitbit_interval); 11604 } 11605 } 11606 #endif 11607 #endif 11608 11609 return rv; 11610 #endif /* INCLUDE_L3 */ 11611 return (BCM_E_UNAVAIL); 11612 } 11613 11614 #ifdef INCLUDE_L3 11615 STATIC int 11616 bcm_xgs3_route_tables_resize(int unit, int arg) 11617 { 11618 int tcam_count = 0; 11619 int tcam_depth = 0; 11620 int config_128b_entries = SOC_L3_DEFIP_MAX_128B_ENTRIES(unit); 11621 soc_mem_t defip_mem = L3_DEFIPm, defip_pair_mem = L3_DEFIP_PAIR_128m; 11622 11623 if (SOC_MEM_IS_VALID(unit, L3_DEFIP_LEVEL1m)) { 11624 defip_mem = L3_DEFIP_LEVEL1m; 11625 defip_pair_mem = L3_DEFIP_PAIR_LEVEL1m; 11626 } 11627 11628 11629 if (SOC_CONTROL(unit)->tcam_protect_write) { 11630 if (config_128b_entries) { 11631 config_128b_entries +=4; 11632 } 11633 } 11634 if (soc_feature(unit, soc_feature_l3_shared_defip_table)) { 11635 if (config_128b_entries != arg) { 11636 tcam_count = SOC_L3_DEFIP_MAX_TCAMS_GET(unit); 11637 tcam_depth = SOC_L3_DEFIP_TCAM_DEPTH_GET(unit); 11638 if (SOC_CONTROL(unit)->tcam_protect_write) { 11639 if (SOC_MEM_IS_ENABLED(unit, defip_pair_mem) && 11640 soc_mem_index_count(unit, defip_pair_mem)) { 11641 tcam_depth++; 11642 } 11643 if (soc_mem_index_count(unit, defip_mem)) { 11644 tcam_depth++; 11645 } 11646 } 11647 if (arg < 0 || arg > ((tcam_count * tcam_depth) / 2)) { 11648 return BCM_E_PARAM; 11649 } 11650 arg += arg % 2; 11651 return _bcm_xgs3_route_tables_resize(unit, arg); 11652 } else { 11653 return BCM_E_NONE; 11654 } 11655 } 11656 return BCM_E_UNAVAIL; 11657 } 11658 #endif /* INCLUDE_L3 */ 11659 11660 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 11661 11662 #if defined(BCM_TRIUMPH_SUPPORT) 11663 /* 11664 * Function: 11665 * _bcm_switch_default_cml_set 11666 * Purpose: 11667 * Set Gport default cml 11668 * Parameters: 11669 * unit - (IN) Device number. 11670 * type - (IN) SwitchControl Type 11671 * arg - (IN) cml value 11672 * Returns: 11673 * Boolean 11674 */ 11675 int 11676 _bcm_switch_default_cml_set(int unit, bcm_switch_control_t type, int arg) 11677 { 11678 int vp = 0; 11679 int cml=0; 11680 int rv = BCM_E_NONE; 11681 source_vp_entry_t svp; 11682 11683 11684 if (!(arg & BCM_PORT_LEARN_FWD)) { 11685 cml |= (1 << 0); 11686 } 11687 if (arg & BCM_PORT_LEARN_CPU) { 11688 cml |= (1 << 1); 11689 } 11690 if (arg & BCM_PORT_LEARN_PENDING) { 11691 cml |= (1 << 2); 11692 } 11693 if (arg & BCM_PORT_LEARN_ARL) { 11694 cml |= (1 << 3); 11695 } 11696 11697 BCM_IF_ERROR_RETURN 11698 (READ_SOURCE_VPm(unit, MEM_BLOCK_ANY, vp, &svp)); 11699 11700 switch (type) { 11701 case bcmSwitchGportAnyDefaultL2Learn: 11702 if (cml != 0x8) { 11703 soc_SOURCE_VPm_field32_set(unit, &svp, CLASS_IDf, 0x1); 11704 } else { 11705 soc_SOURCE_VPm_field32_set(unit, &svp, CLASS_IDf, 0x0); 11706 } 11707 soc_SOURCE_VPm_field32_set(unit, &svp, CML_FLAGS_NEWf, cml); 11708 break; 11709 11710 case bcmSwitchGportAnyDefaultL2Move: 11711 if (SOC_IS_TRIDENT3X(unit)) { 11712 soc_mem_field32_dest_set(unit, SOURCE_VPm, &svp, 11713 DESTINATIONf, SOC_MEM_FIF_DEST_DVP, (cml != 0x8) ? 0x1 : 0); 11714 } else { 11715 if (cml != 0x8) { 11716 soc_SOURCE_VPm_field32_set(unit, &svp, DVPf, 0x1); 11717 } else { 11718 soc_SOURCE_VPm_field32_set(unit, &svp, DVPf, 0x0); 11719 } 11720 } 11721 soc_SOURCE_VPm_field32_set(unit, &svp, CML_FLAGS_MOVEf, cml); 11722 break; 11723 11724 default: 11725 break; 11726 } 11727 11728 rv = WRITE_SOURCE_VPm(unit, MEM_BLOCK_ALL, vp, &svp); 11729 return rv; 11730 } 11731 11732 /* 11733 * Function: 11734 * _bcm_switch_default_cml_get 11735 * Purpose: 11736 * Get Gport default cml 11737 * Parameters: 11738 * unit - (IN) Device number. 11739 * type - (IN) SwitchControl Type 11740 * arg - (OUT) cml value 11741 * Returns: 11742 * Boolean 11743 */ 11744 int 11745 _bcm_switch_default_cml_get(int unit, bcm_switch_control_t type, int *arg) 11746 { 11747 int vp = 0; 11748 int cml=0x8; /* Default Value of cml */ 11749 int rv = BCM_E_NONE; 11750 source_vp_entry_t svp; 11751 int cml_default_enable=0; 11752 11753 BCM_IF_ERROR_RETURN 11754 (READ_SOURCE_VPm(unit, MEM_BLOCK_ANY, vp, &svp)); 11755 11756 11757 switch (type) { 11758 case bcmSwitchGportAnyDefaultL2Learn: 11759 cml_default_enable = soc_SOURCE_VPm_field32_get(unit, &svp, 11760 CLASS_IDf); 11761 if (cml_default_enable) { 11762 cml = soc_SOURCE_VPm_field32_get(unit, &svp, 11763 CML_FLAGS_NEWf); 11764 } 11765 break; 11766 11767 case bcmSwitchGportAnyDefaultL2Move: 11768 if (SOC_IS_TRIDENT3X(unit)) { 11769 uint32 dest_type; 11770 cml_default_enable = soc_mem_field32_dest_get(unit, SOURCE_VPm, 11771 &svp, DESTINATIONf, &dest_type); 11772 if (dest_type != SOC_MEM_FIF_DEST_DVP) { 11773 cml_default_enable = 0; 11774 } 11775 } else { 11776 cml_default_enable = soc_SOURCE_VPm_field32_get(unit, &svp, DVPf); 11777 } 11778 11779 if (cml_default_enable) { 11780 cml = soc_SOURCE_VPm_field32_get(unit, &svp, CML_FLAGS_MOVEf); 11781 } 11782 break; 11783 11784 default: 11785 break; 11786 } 11787 11788 *arg = 0; 11789 if (!(cml & (1 << 0))) { 11790 *arg |= BCM_PORT_LEARN_FWD; 11791 } 11792 if (cml & (1 << 1)) { 11793 *arg |= BCM_PORT_LEARN_CPU; 11794 } 11795 if (cml & (1 << 2)) { 11796 *arg |= BCM_PORT_LEARN_PENDING; 11797 } 11798 if (cml & (1 << 3)) { 11799 *arg |= BCM_PORT_LEARN_ARL; 11800 } 11801 11802 return rv; 11803 } 11804 11805 /* Assumption: Use this SC for Dynamic uRPF update, only if EXT-DEFIP entry used */ 11806 STATIC int 11807 _bcm_xgs3_urpf_route_enable_external(int unit, int arg) 11808 { 11809 #ifdef INCLUDE_L3 11810 int orig_val; 11811 uint32 reg_val; 11812 11813 if (!SOC_REG_FIELD_VALID(unit, L3_DEFIP_RPF_CONTROLr, DEFIP_RPF_ENABLEf)) { 11814 return (BCM_E_UNAVAIL); 11815 } 11816 11817 if (!soc_feature(unit, soc_feature_urpf)) { 11818 return (BCM_E_UNAVAIL); 11819 } 11820 11821 /* Check if any INT-DEFIP entry configured */ 11822 BCM_IF_ERROR_RETURN(bcm_xgs3_defip_verify_internal_mem_usage(unit)); 11823 11824 BCM_IF_ERROR_RETURN(READ_L3_DEFIP_RPF_CONTROLr(unit, ®_val)); 11825 11826 /* Handle nothing changed case. */ 11827 orig_val = soc_reg_field_get(unit, L3_DEFIP_RPF_CONTROLr, 11828 reg_val, DEFIP_RPF_ENABLEf); 11829 if (orig_val == (arg ? 1 : 0)) { 11830 return (BCM_E_NONE); 11831 } 11832 11833 /* State changed -> Set urpf route enable bit. */ 11834 BCM_IF_ERROR_RETURN 11835 (soc_reg_field32_modify(unit, L3_DEFIP_RPF_CONTROLr, REG_PORT_ANY, 11836 DEFIP_RPF_ENABLEf, (arg ? 1 : 0))); 11837 return (BCM_E_NONE); 11838 #endif /* INCLUDE_L3 */ 11839 return (BCM_E_UNAVAIL); 11840 } 11841 #endif 11842 11843 #if defined(BCM_SCORPION_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) 11844 STATIC int 11845 _bcm_tr2_sc_pfc_sctype_to_class(bcm_switch_control_t type) 11846 { 11847 int class = 0; 11848 11849 switch (type) { 11850 case bcmSwitchPFCClass7Queue: 11851 class = 7; 11852 break; 11853 case bcmSwitchPFCClass6Queue: 11854 class = 6; 11855 break; 11856 case bcmSwitchPFCClass5Queue: 11857 class = 5; 11858 break; 11859 case bcmSwitchPFCClass4Queue: 11860 class = 4; 11861 break; 11862 case bcmSwitchPFCClass3Queue: 11863 class = 3; 11864 break; 11865 case bcmSwitchPFCClass2Queue: 11866 class = 2; 11867 break; 11868 case bcmSwitchPFCClass1Queue: 11869 class = 1; 11870 break; 11871 case bcmSwitchPFCClass0Queue: 11872 class = 0; 11873 break; 11874 default: 11875 class = -1; 11876 break; 11877 } 11878 return class; 11879 } 11880 11881 STATIC int 11882 _bcm_tr2_sc_pfc_priority_to_cos_set(int unit, bcm_switch_control_t type, 11883 int arg) 11884 { 11885 uint32 rval; 11886 int class = 0; 11887 11888 if (soc_feature(unit, soc_feature_priority_flow_control)) { 11889 class = _bcm_tr2_sc_pfc_sctype_to_class(type); 11890 if (class < 0) { 11891 return BCM_E_INTERNAL; 11892 } 11893 if ((arg < 0) || (arg > 7)) { 11894 return BCM_E_PARAM; 11895 } 11896 if (SOC_REG_IS_VALID(unit, PRIO2COSr)) { 11897 BCM_IF_ERROR_RETURN(READ_PRIO2COSr(unit, class, &rval)); 11898 soc_reg_field_set(unit, PRIO2COSr, &rval, COS0_7_BMPf, 11899 (1 << arg)); 11900 BCM_IF_ERROR_RETURN(WRITE_PRIO2COSr(unit, class, rval)); 11901 } else { 11902 if (SOC_REG_IS_VALID(unit, PRIO2COS_PROFILEr)) { 11903 BCM_IF_ERROR_RETURN(READ_PRIO2COS_PROFILEr(unit, class, &rval)); 11904 soc_reg_field_set(unit, PRIO2COS_PROFILEr, &rval, COS_BMPf, 11905 (1 << arg)); 11906 BCM_IF_ERROR_RETURN(WRITE_PRIO2COS_PROFILEr(unit, class, rval)); 11907 } else { 11908 BCM_IF_ERROR_RETURN(READ_PRIO2COS_LLFCr(unit, class, &rval)); 11909 soc_reg_field_set(unit, PRIO2COS_LLFCr, &rval, COS0_23_BMPf, 11910 (1 << arg)); 11911 BCM_IF_ERROR_RETURN(WRITE_PRIO2COS_LLFCr(unit, class, rval)); 11912 } 11913 } 11914 return BCM_E_NONE; 11915 } 11916 return BCM_E_UNAVAIL; 11917 } 11918 11919 STATIC int 11920 _bcm_tr2_sc_pfc_priority_to_cos_get(int unit, bcm_switch_control_t type, 11921 int *arg) 11922 { 11923 uint32 rval; 11924 int cosbmp, cos, class = 0; 11925 11926 if (soc_feature(unit, soc_feature_priority_flow_control)) { 11927 if (arg == NULL) { 11928 return BCM_E_PARAM; 11929 } 11930 class = _bcm_tr2_sc_pfc_sctype_to_class(type); 11931 if (class < 0) { 11932 return BCM_E_INTERNAL; 11933 } 11934 if (SOC_REG_IS_VALID(unit, PRIO2COSr)) { 11935 BCM_IF_ERROR_RETURN(READ_PRIO2COSr(unit, class, &rval)); 11936 cosbmp = soc_reg_field_get(unit, PRIO2COSr, rval, COS0_7_BMPf); 11937 } else { 11938 if (SOC_REG_IS_VALID(unit, PRIO2COS_PROFILEr)) { 11939 BCM_IF_ERROR_RETURN(READ_PRIO2COS_PROFILEr(unit, class, &rval)); 11940 cosbmp = soc_reg_field_get(unit, PRIO2COS_PROFILEr, rval, 11941 COS_BMPf); 11942 } else { 11943 BCM_IF_ERROR_RETURN(READ_PRIO2COS_LLFCr(unit, class, &rval)); 11944 cosbmp = soc_reg_field_get(unit, PRIO2COS_LLFCr, rval, 11945 COS0_23_BMPf); 11946 } 11947 } 11948 for (cos = 0; cos < 8; cos++) { 11949 if (cosbmp & (1 << cos)) { 11950 *arg = cos; 11951 return BCM_E_NONE; 11952 } 11953 } 11954 return BCM_E_INTERNAL; 11955 } 11956 return BCM_E_UNAVAIL; 11957 } 11958 #endif /* BCM_SCORPION_SUPPORT || BCM_TRIUMPH2_SUPPORT */ 11959 11960 bcm_switch_binding_t xgs3_bindings[] = 11961 { 11962 #if defined (BCM_RAVEN_SUPPORT) 11963 { bcmSwitchSTPBlockedFieldBypass, RV | HK, 11964 ING_CONFIGr, BLOCKED_PORTS_FP_DISABLEf, 11965 NULL, 0}, 11966 #endif /* BCM_RAVEN_SUPPORT */ 11967 11968 #if defined (BCM_SCORPION_SUPPORT) 11969 { bcmSwitchSharedVlanMismatchToCpu, SCQ, 11970 CPU_CONTROL_1r, PVLAN_VID_MISMATCH_TOCPUf, 11971 NULL, 0}, 11972 { bcmSwitchForceForwardFabricTrunk, SCQ, 11973 ING_MISC_CONFIGr, LOCAL_SW_DISABLE_HGTRUNK_RES_ENf, 11974 NULL, 0}, 11975 #endif /* BCM_SCORPION_SUPPORT */ 11976 11977 #if defined(BCM_RAPTOR_SUPPORT) 11978 { bcmSwitchLearnLimitPriority, RV | HK, 11979 CPU_CONTROL_3r, CPU_MAC_LIMIT_PRIORITYf, 11980 NULL, soc_feature_mac_learn_limit }, 11981 #if defined(BCM_RAPTOR1_SUPPORT) 11982 { bcmSwitchIpmcTunnelToCpu, RP, 11983 CPU_CONTROL_1r, IPMC_TUNNEL_TO_CPUf, 11984 NULL,0}, 11985 #endif 11986 { bcmSwitchCpuToCpuEnable, RP | RV | HK, 11987 ING_CONFIGr, DISABLE_COPY_TO_CPU_FOR_CPU_PORTf, 11988 _bool_invert, 0 }, 11989 #endif /* BCM_RAPTOR_SUPPORT */ 11990 11991 #if defined(BCM_TRIUMPH3_SUPPORT) 11992 {bcmSwitchWlanClientAuthorizeAll, TR3 | HX4, 11993 AXP_WRX_MASTER_CTRLr, WCD_DISABLEf, 11994 NULL, 0}, 11995 #endif /* BCM_TRIUMPH3_SUPPORT */ 11996 11997 #if defined(BCM_TRIUMPH2_SUPPORT) 11998 { bcmSwitchWlanClientUnauthToCpu, TR2 | AP | VL2, 11999 CPU_CONTROL_Mr, WLAN_DOT1X_DROPf, 12000 NULL, 0}, 12001 { bcmSwitchWlanClientRoamedOutErrorToCpu, TR2 | AP | VL2, 12002 CPU_CONTROL_Mr, WLAN_ROAM_ERRORf, 12003 NULL, 0}, 12004 { bcmSwitchWlanClientSrcMacMissToCpu, TR2 | AP | VL2, 12005 CPU_CONTROL_Mr, WCD_SA_MISSf, 12006 NULL, 0}, 12007 { bcmSwitchWlanClientDstMacMissToCpu, TR2 | AP | VL2, 12008 CPU_CONTROL_Mr, WCD_DA_MISSf, 12009 NULL, 0}, 12010 { bcmSwitchOamHeaderErrorToCpu, TR2 | AP | VL2 | EN | TD | TR3 | HX4 | KT | KT2 12011 | TD2 | TD2P , CPU_CONTROL_Mr, OAM_HEADER_ERROR_TOCPUf, 12012 NULL, 0}, 12013 { bcmSwitchOamUnknownVersionToCpu, TR2 | AP | VL2 | EN | TD | TR3 | HX4 | KT | KT2 12014 | TD2 | TD2P , CPU_CONTROL_Mr, OAM_UNKNOWN_OPCODE_VERSION_TOCPUf, 12015 NULL, 0}, 12016 { bcmSwitchL3SrcBindFailToCpu, TR2 | AP | VL2 | TD | TR3 | HX4 | KT | KT2 | TD2 | TD2P | TH, 12017 CPU_CONTROL_Mr, MAC_BIND_FAILf, 12018 NULL, 0}, 12019 { bcmSwitchTunnelIp4IdShared, TR2 | AP | VL2 | TD | TR3 | HX4 | KT | KT2 | TD2 | TD2P | TH, 12020 EGR_TUNNEL_ID_MASKr, SHARED_FRAG_ID_ENABLEf, 12021 NULL, 0}, 12022 { bcmSwitchIpfixRateViolationDataInsert, TR2 | AP | VL2, 12023 ING_IPFIX_FLOW_RATE_CONTROLr, SUSPECT_FLOW_INSERT_DISABLEf, 12024 _bool_invert, soc_feature_ipfix_rate }, 12025 { bcmSwitchIpfixRateViolationPersistent, TR2 | AP | VL2, 12026 ING_IPFIX_FLOW_RATE_CONTROLr, SUSPECT_FLOW_CONVERT_DISABLEf, 12027 NULL, 0}, 12028 { bcmSwitchCustomerQueuing, TR2 | AP | VL2 | EN | KT | KT2, 12029 ING_MISC_CONFIGr, PHB2_COS_MODEf, 12030 NULL, soc_feature_vlan_queue_map}, 12031 { bcmSwitchOamUnknownVersionDrop, TR2 | AP | VL2 | EN | TD | TR3 | HX4 | KT 12032 | TD2 | TD2P , OAM_DROP_CONTROLr, OAM_UNKNOWN_OPCODE_VERSION_DROPf, 12033 NULL, 0}, 12034 { bcmSwitchDirectedMirroring, TR2 | AP | VL2, 12035 EGR_PORT_64r, EM_SRCMOD_CHANGEf, 12036 NULL, soc_feature_src_modid_blk }, 12037 { bcmSwitchDirectedMirroring, TR2 | AP | VL2, 12038 IEGR_PORT_64r, EM_SRCMOD_CHANGEf, 12039 NULL, soc_feature_src_modid_blk }, 12040 #endif 12041 12042 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 12043 { bcmSwitchOamUnexpectedPktToCpu, EN | TD | TR3 | HX4 | KT | KT2 | TD2 | TD2P, 12044 CPU_CONTROL_Mr, OAM_UNEXPECTED_PKT_TOCPUf, 12045 NULL, 0}, 12046 #endif 12047 12048 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 12049 defined(BCM_TRIDENT2_SUPPORT) 12050 { bcmSwitchOamCcmToCpu, KT | KT2 | TR3 | HX4 | TD2 | TD2P, 12051 CCM_COPYTO_CPU_CONTROLr, ERROR_CCM_COPY_TOCPUf, 12052 NULL, 0}, 12053 { bcmSwitchOamXconCcmToCpu, KT | KT2 | TR3 | HX4 | TD2 | TD2P, 12054 CCM_COPYTO_CPU_CONTROLr, XCON_CCM_COPY_TOCPUf, 12055 NULL, 0}, 12056 { bcmSwitchOamXconOtherToCpu, KT | TR3 | HX4 | TD2 | TD2P, 12057 CCM_COPYTO_CPU_CONTROLr, XCON_OTHER_COPY_TOCPUf, 12058 NULL, 0}, 12059 #endif /* !BCM_TRIUMPH3_SUPPORT */ 12060 12061 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) 12062 { bcmSwitchL3InterfaceUrpfEnable, TD | TR2 | TR3 | HX4 | KT | KT2 | TD2 | TD2P | TH, 12063 ING_CONFIG_64r, L3IIF_URPF_SELECTf, 12064 NULL, soc_feature_urpf }, 12065 #endif 12066 12067 #if defined(BCM_ENDURO_SUPPORT) 12068 { bcmSwitchMiMDefaultSVP, EN, 12069 ING_Q_BEGINr, MIM_EN_DEF_NETWORK_SVPf, 12070 NULL, 0}, 12071 { bcmSwitchEgressDroppedReportZeroLength, EN, 12072 EGR_Q_BEGINr, DWRR_OR_SHAPINGf, 12073 NULL, 0}, 12074 #endif 12075 12076 #if defined(BCM_TRX_SUPPORT) 12077 { bcmSwitchClassBasedMoveFailPktToCpu, TRX, 12078 CPU_CONTROL_1r, CLASS_BASED_SM_PREVENTED_TOCPUf, 12079 NULL, soc_feature_class_based_learning }, 12080 { bcmSwitchL3UrpfFailToCpu, TRX, 12081 CPU_CONTROL_1r, URPF_MISS_TOCPUf, 12082 NULL, soc_feature_urpf }, 12083 { bcmSwitchClassBasedMoveFailPktDrop, TRX, 12084 ING_MISC_CONFIG2r, CLASS_BASED_SM_PREVENTED_DROPf, 12085 NULL, soc_feature_class_based_learning }, 12086 { bcmSwitchSTPBlockedFieldBypass, TRX, 12087 ING_MISC_CONFIG2r, BLOCKED_PORTS_FP_DISABLEf, 12088 NULL, 0}, 12089 { bcmSwitchRateLimitLinear, TRX, 12090 MISCCONFIGr, ITU_MODE_SELf, 12091 _bool_invert, 0}, 12092 { bcmSwitchRemoteLearnTrust, TRX, 12093 ING_CONFIG_64r, IGNORE_HG_HDR_DONOT_LEARNf, 12094 _bool_invert, 0 }, 12095 { bcmSwitchMldDirectAttachedOnly, TRX, 12096 ING_CONFIG_64r, MLD_CHECKS_ENABLEf, 12097 NULL, soc_feature_igmp_mld_support }, 12098 { bcmSwitchSharedVlanL2McastEnable, TRX, 12099 ING_CONFIG_64r, LOOKUP_L2MC_WITH_FID_IDf, 12100 NULL, 0}, 12101 { bcmSwitchMldUcastEnable, TRX, 12102 ING_CONFIG_64r, MLD_PKTS_UNICAST_IGNOREf, 12103 _bool_invert, soc_feature_igmp_mld_support }, 12104 { bcmSwitchSharedVlanEnable, TRX, 12105 ING_CONFIG_64r, SVL_ENABLEf, 12106 NULL, 0}, 12107 { bcmSwitchIgmpReservedMcastEnable, TRX, 12108 ING_CONFIG_64r, IPV4_RESERVED_MC_ADDR_IGMP_ENABLEf, 12109 NULL, soc_feature_igmp_mld_support }, 12110 { bcmSwitchMldReservedMcastEnable, TRX, 12111 ING_CONFIG_64r, IPV6_RESERVED_MC_ADDR_MLD_ENABLEf, 12112 NULL, soc_feature_igmp_mld_support }, 12113 { bcmSwitchIgmpUcastEnable, TRX, 12114 ING_CONFIG_64r, IGMP_PKTS_UNICAST_IGNOREf, 12115 _bool_invert, soc_feature_igmp_mld_support }, 12116 { bcmSwitchPortEgressBlockL3, TRX, 12117 ING_CONFIG_64r, APPLY_EGR_MASK_ON_L3f, 12118 NULL, 0}, 12119 { bcmSwitchPortEgressBlockL2, TRX, 12120 ING_CONFIG_64r, APPLY_EGR_MASK_ON_L2f, 12121 NULL, 0}, 12122 { bcmSwitchHgHdrExtLengthEnable, TRX, 12123 ING_CONFIG_64r, IGNORE_HG_HDR_HDR_EXT_LENf, 12124 _bool_invert, 0 }, 12125 { bcmSwitchIp4McastL2DestCheck, TRX, 12126 ING_CONFIG_64r, IPV4_MC_MACDA_CHECK_ENABLEf, 12127 NULL, 0}, 12128 { bcmSwitchIp6McastL2DestCheck, TRX, 12129 ING_CONFIG_64r, IPV6_MC_MACDA_CHECK_ENABLEf, 12130 NULL, 0}, 12131 { bcmSwitchL3TunnelUrpfMode, TRX, 12132 ING_CONFIG_64r, TUNNEL_URPF_MODEf, 12133 NULL, soc_feature_urpf }, 12134 { bcmSwitchL3TunnelUrpfDefaultRoute, TRX, 12135 ING_CONFIG_64r, TUNNEL_URPF_DEFAULTROUTECHECKf, 12136 _bool_invert, soc_feature_urpf }, 12137 { bcmSwitchMirrorStackMode, TRX, 12138 ING_CONFIG_64r, STACK_MODEf, 12139 NULL, soc_feature_src_modid_blk }, 12140 { bcmSwitchDirectedMirroring, TRX, 12141 ING_CONFIG_64r, DRACO1_5_MIRRORf, 12142 _bool_invert, soc_feature_xgs1_mirror }, 12143 { bcmSwitchMirrorSrcModCheck, TRX, 12144 ING_CONFIG_64r, FB_A0_COMPATIBLEf, 12145 NULL, soc_feature_src_modid_blk }, 12146 { bcmSwitchProxySrcKnockout, TRX, 12147 IHG_LOOKUPr, REMOVE_MH_SRC_PORTf, 12148 NULL, soc_feature_proxy_port_property }, 12149 #endif /* BCM_TRX_SUPPORT */ 12150 12151 #if defined(BCM_TRIUMPH_SUPPORT) 12152 { bcmSwitchDosAttackToCpu, TRVL|HU2|KT2, 12153 CPU_CONTROL_0r, DOSATTACK_TOCPUf, 12154 NULL, 0 }, 12155 { bcmSwitchParityErrorToCpu, TRVL|KT2, 12156 CPU_CONTROL_0r, PARITY_ERR_TOCPUf, 12157 NULL, soc_feature_parity_err_tocpu }, 12158 { bcmSwitchUnknownVlanToCpu, TRVL|KT2, 12159 CPU_CONTROL_0r, UVLAN_TOCPUf, 12160 NULL, 0 }, 12161 { bcmSwitchSourceMacZeroDrop, TRVL|KT2, 12162 CPU_CONTROL_0r, MACSA_ALL_ZERO_DROPf, 12163 NULL, 0}, 12164 { bcmSwitchMplsSequenceErrToCpu, TRVL|KT2, 12165 ING_MISC_CONFIGr, MPLS_SEQ_NUM_FAIL_TOCPUf, 12166 NULL, 0}, 12167 { bcmSwitchMplsLabelMissToCpu, TRVL|KT2, 12168 CPU_CONTROL_Mr, MPLS_LABEL_MISSf, 12169 NULL, 0}, 12170 { bcmSwitchMplsTtlErrToCpu, TRVL|KT2, 12171 CPU_CONTROL_Mr, MPLS_TTL_CHECK_FAILf, 12172 NULL, 0}, 12173 { bcmSwitchMplsInvalidL3PayloadToCpu, TRVL|KT2, 12174 CPU_CONTROL_Mr, MPLS_INVALID_PAYLOADf, 12175 NULL, 0}, 12176 { bcmSwitchMplsInvalidActionToCpu, TRVL|KT2, 12177 CPU_CONTROL_Mr, MPLS_INVALID_ACTIONf, 12178 NULL, 0}, 12179 { bcmSwitchSharedVlanMismatchToCpu, TRVL|KT2, 12180 CPU_CONTROL_0r, PVLAN_VID_MISMATCH_TOCPUf , 12181 NULL, 0}, 12182 { bcmSwitchForceForwardFabricTrunk, TRVL|KT2, 12183 ING_MISC_CONFIGr, LOCAL_SW_DISABLE_HGTRUNK_RES_ENf, 12184 NULL, 0}, 12185 { bcmSwitchFieldMultipathHashSeed, TH, 12186 IFP_ECMP_HASH_CONTROLr, ECMP_HASH_SALTf, 12187 NULL, 0}, 12188 { bcmSwitchFieldMultipathHashSeed, TRVL|KT2, 12189 FP_ECMP_HASH_CONTROLr, ECMP_HASH_SALTf, 12190 NULL, 0}, 12191 { bcmSwitchMplsPortIndependentLowerRange1, TRVL|KT2, 12192 GLOBAL_MPLS_RANGE_1_LOWERr, LABELf, 12193 NULL, 0}, 12194 { bcmSwitchMplsPortIndependentUpperRange1, TRVL|KT2, 12195 GLOBAL_MPLS_RANGE_1_UPPERr, LABELf, 12196 NULL, 0}, 12197 { bcmSwitchMplsPortIndependentLowerRange2, TRVL|KT2, 12198 GLOBAL_MPLS_RANGE_2_LOWERr, LABELf, 12199 NULL, 0}, 12200 { bcmSwitchMplsPortIndependentUpperRange2, TRVL|KT2, 12201 GLOBAL_MPLS_RANGE_2_UPPERr, LABELf, 12202 NULL, 0}, 12203 { bcmSwitchL3UrpfRouteEnableExternal, TRVL | TD2 | TD2P | TH, 12204 L3_DEFIP_RPF_CONTROLr, DEFIP_RPF_ENABLEf, 12205 NULL, soc_feature_urpf}, 12206 { bcmSwitchMplsPWControlWordToCpu, TRVL|KT2, 12207 ING_MISC_CONFIGr, PWACH_TOCPUf, 12208 NULL, soc_feature_mpls}, 12209 { bcmSwitchMplsPWControlTypeToCpu, TRVL|KT2, 12210 ING_MISC_CONFIGr, OTHER_CW_TYPE_TOCPUf, 12211 NULL, soc_feature_mpls}, 12212 { bcmSwitchMplsPWCountPktsAll, TR | VL | EN, 12213 ING_MISC_CONFIGr, PW_COUNT_ALLf, 12214 NULL, soc_feature_mpls}, 12215 #endif /* BCM_TRIUMPH_SUPPORT */ 12216 12217 #if defined(BCM_FIREBOLT2_SUPPORT) 12218 { bcmSwitchL3UrpfFailToCpu, FB2, 12219 CPU_CONTROL_1r, URPF_MISS_TOCPUf, 12220 NULL, soc_feature_urpf }, 12221 { bcmSwitchCpuLookupFpCopyPrio, FB2, 12222 CPU_CONTROL_2r, CPU_VFPCOPY_PRIORITYf, 12223 NULL, 0 }, 12224 { bcmSwitchL3TunnelUrpfMode, FB2, 12225 ING_CONFIGr, TUNNEL_URPF_MODEf, 12226 NULL, soc_feature_urpf }, 12227 { bcmSwitchL3TunnelUrpfDefaultRoute, FB2, 12228 ING_CONFIGr, TUNNEL_URPF_DEFAULTROUTECHECKf, 12229 _bool_invert, soc_feature_urpf }, 12230 { bcmSwitchHgHdrExtLengthEnable, FB2, 12231 ING_CONFIGr, IGNORE_HG_HDR_HDR_EXT_LENf, 12232 _bool_invert, 0 }, 12233 { bcmSwitchUniformFabricTrunkDistribution, FB2, 12234 ING_MISC_CONFIGr, UNIFORM_HG_TRUNK_DIST_ENABLEf, 12235 NULL, soc_feature_trunk_group_size }, 12236 { bcmSwitchRateLimitLinear, FB2, 12237 MISCCONFIGr, ITU_MODE_SELf, 12238 _bool_invert, 0}, 12239 #endif /* BCM_FIREBOLT2_SUPPORT */ 12240 12241 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 12242 { bcmSwitchCpuToCpuEnable, FB2 | TRX, 12243 ING_MISC_CONFIGr, DO_NOT_COPY_FROM_CPU_TO_CPUf, 12244 _bool_invert, 0 }, 12245 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 12246 12247 #if defined(BCM_FIREBOLT_SUPPORT) 12248 { bcmSwitchCpuProtocolPrio, FB | FH, 12249 CPU_CONTROL_2r, CPU_PROTOCOL_PRIORITYf, 12250 NULL, 0 }, 12251 #endif /* BCM_FIREBOLT_SUPPORT */ 12252 12253 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) 12254 { bcmSwitchAlternateStoreForward, FB | FH | HXFX, 12255 ASFCONFIGr, ASF_ENf, 12256 NULL, soc_feature_asf }, 12257 { bcmSwitchRemoteLearnTrust, FB | FH, 12258 ING_CONFIGr, DO_NOT_LEARN_ENABLEf, 12259 NULL, soc_feature_remote_learn_trust }, 12260 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT */ 12261 12262 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) 12263 { bcmSwitchIgmpUcastEnable, FB2 | RP | RV | HK, 12264 ING_CONFIGr, IGMP_PKTS_UNICAST_IGNOREf, 12265 _bool_invert, soc_feature_igmp_mld_support }, 12266 { bcmSwitchMldUcastEnable, FB2 | RP | RV | HK, 12267 ING_CONFIGr, MLD_PKTS_UNICAST_IGNOREf, 12268 _bool_invert, soc_feature_igmp_mld_support }, 12269 { bcmSwitchIgmpReservedMcastEnable, FB2 | RP | RV | HK, 12270 ING_CONFIGr, IPV4_RESERVED_MC_ADDR_IGMP_ENABLEf, 12271 NULL, soc_feature_igmp_mld_support }, 12272 { bcmSwitchMldReservedMcastEnable, FB2 | RP | RV | HK, 12273 ING_CONFIGr, IPV6_RESERVED_MC_ADDR_MLD_ENABLEf, 12274 NULL, soc_feature_igmp_mld_support }, 12275 { bcmSwitchMldDirectAttachedOnly, FB2 | RP | RV | HK, 12276 ING_CONFIGr, MLD_CHECKS_ENABLEf, 12277 NULL, soc_feature_igmp_mld_support }, 12278 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT */ 12279 12280 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAVEN_SUPPORT) 12281 { bcmSwitchIp4McastL2DestCheck, FB2 | RV | HK, 12282 ING_CONFIGr, IPV4_MC_MACDA_CHECK_ENABLEf, 12283 NULL, 0}, 12284 { bcmSwitchIp6McastL2DestCheck, FB2 | RV | HK, 12285 ING_CONFIGr, IPV6_MC_MACDA_CHECK_ENABLEf, 12286 NULL, 0}, 12287 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAVEN_SUPPORT */ 12288 12289 #if defined(BCM_FIREBOLT2_SUPPORT) 12290 { bcmSwitchUniformUcastTrunkDistribution, FB2, 12291 ING_MISC_CONFIGr, UNIFORM_TRUNK_DIST_ENABLEf, 12292 NULL, soc_feature_trunk_group_size }, 12293 #endif /* BCM_FIREBOLT2_SUPPORT */ 12294 12295 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 12296 { bcmSwitchL3UrpfRouteEnable, FB2 | TRX, 12297 L3_DEFIP_RPF_CONTROLr, DEFIP_RPF_ENABLEf, 12298 NULL, soc_feature_urpf}, 12299 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 12300 12301 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_TRX_SUPPORT) 12302 { bcmSwitchStationMoveOverLearnLimitToCpu, RV | TRX | HK, 12303 CPU_CONTROL_1r, MACLMT_STNMV_TOCPUf, 12304 NULL, soc_feature_mac_learn_limit}, 12305 #endif /* BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 12306 12307 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) 12308 { bcmSwitchControlOpcodePriority, HBGW | RP | RV | HK, 12309 CPU_CONTROL_2r, CPU_MH_CONTROL_PRIORITYf, 12310 NULL, 0 }, 12311 #endif /* BCM_BRADLEY_SUPPORT || BCM_RAPTOR_SUPPORT */ 12312 12313 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_SCORPION_SUPPORT) || \ 12314 defined(BCM_TRIDENT_SUPPORT) 12315 { bcmSwitchAlternateStoreForward, HBGW | SCQ | TD | TT, 12316 OP_THR_CONFIGr, ASF_ENABLEf, 12317 NULL, soc_feature_asf }, 12318 #endif /* BCM_BRADLEY_SUPPORT || BCM_SCORPION_SUPPORT || BCM_TRIDENT_SUPPORT */ 12319 12320 #if defined(BCM_BRADLEY_SUPPORT) 12321 { bcmSwitchSharedVlanEnable, HBGW, 12322 ING_CONFIGr, SVL_ENABLEf, 12323 NULL, 0}, 12324 #endif /* BCM_BRADLEY_SUPPORT */ 12325 12326 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 12327 defined(BCM_TRX_SUPPORT) 12328 { bcmSwitchBpduInvalidVlanDrop, FB2 | RP | RV | TRX | HK, 12329 EGR_CONFIG_1r, BPDU_INVALID_VLAN_DROPf, 12330 NULL, soc_feature_igmp_mld_support }, 12331 { bcmSwitchMirrorInvalidVlanDrop, FB2 | RP | RV | TRX | HK, 12332 EGR_CONFIG_1r, MIRROR_INVALID_VLAN_DROPf, 12333 NULL, soc_feature_igmp_mld_support }, 12334 { bcmSwitchMcastFloodBlocking, FB2 | RP | RV | TRX | HK, 12335 IGMP_MLD_PKT_CONTROLr, PFM_RULE_APPLYf, 12336 NULL, soc_feature_igmp_mld_support }, 12337 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 12338 12339 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAVEN_SUPPORT) || \ 12340 defined(BCM_TRX_SUPPORT) 12341 { bcmSwitchIpmcTtl1ToCpu, FB2 | RV | TRX, 12342 CPU_CONTROL_1r, IPMC_TTL1_ERR_TOCPUf, 12343 NULL, 0 }, 12344 { bcmSwitchL3UcastTtl1ToCpu, FB2 | RV | TRX | HK, 12345 CPU_CONTROL_1r, L3UC_TTL1_ERR_TOCPUf, 12346 NULL, 0 }, 12347 { bcmSwitchDhcpLearn, FB2 | RV | TRX | HK, 12348 ING_MISC_CONFIG2r, DO_NOT_LEARN_DHCPf, 12349 NULL, 0 }, 12350 { bcmSwitchUnknownIpmcAsMcast, FB2 | RV | TRX | HK, 12351 ING_MISC_CONFIG2r, IPMC_MISS_AS_L2MCf, 12352 NULL, soc_feature_l3 }, 12353 { bcmSwitchTunnelUnknownIpmcDrop, FB2 | RV | TRX | HK, 12354 ING_MISC_CONFIG2r, UNKNOWN_TUNNEL_IPMC_DROPf, 12355 NULL, 0 }, 12356 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAVEN_SUPPORT || BCM_TRX_SUPPORT */ 12357 12358 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 12359 defined(BCM_TRX_SUPPORT) 12360 { bcmSwitchMcastUnknownErrToCpu, BR | GW | RP | TRX | RV | HK, 12361 CPU_CONTROL_1r, MC_INDEX_ERROR_TOCPUf, 12362 NULL,0}, 12363 #endif /* BCM_RAPTOR_SUPPORT || BCM_BRADLEY_SUPPORT || BCM_TRX_SUPPORT */ 12364 12365 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) ||\ 12366 defined(BCM_RAPTOR_SUPPORT) 12367 { bcmSwitchDosAttackMACSAEqualMACDA, FB2 | RP | TRX | RV | HK, 12368 DOS_CONTROLr, MACSA_EQUALS_MACDA_DROPf, 12369 NULL, soc_feature_enhanced_dos_ctrl }, 12370 { bcmSwitchDosAttackFlagZeroSeqZero, FB2 | RP | TRX | RV | HK, 12371 DOS_CONTROLr, TCP_FLAGS_CTRL0_SEQ0_ENABLEf, 12372 NULL, 0 }, 12373 { bcmSwitchDosAttackSynFrag, FB2 | RP | TRX | RV | HK, 12374 DOS_CONTROLr, TCP_FLAGS_SYN_FRAG_ENABLEf, 12375 NULL, 0}, 12376 { bcmSwitchDosAttackIcmp, FB2 | RP | TRX | RV, 12377 DOS_CONTROL_2r, ICMP_V4_PING_SIZE_ENABLEf, 12378 NULL, 0 }, 12379 { bcmSwitchDosAttackIcmp, FB2 | RP | TRX | RV, 12380 DOS_CONTROL_2r, ICMP_V6_PING_SIZE_ENABLEf, 12381 NULL, 0 }, 12382 { bcmSwitchDosAttackIcmpV4, FB2 | RP | TRX | RV, 12383 DOS_CONTROL_2r, ICMP_V4_PING_SIZE_ENABLEf, 12384 NULL, 0 }, 12385 { bcmSwitchDosAttackIcmpV6, FB2 | RP | TRX | RV, 12386 DOS_CONTROL_2r, ICMP_V6_PING_SIZE_ENABLEf, 12387 NULL, 0 }, 12388 { bcmSwitchDosAttackIcmpFragments, FB2 | RP | TRX | RV, 12389 DOS_CONTROL_2r, ICMP_FRAG_PKTS_ENABLEf, 12390 NULL, soc_feature_enhanced_dos_ctrl }, 12391 { bcmSwitchDosAttackTcpOffset, FB2 | RP | TRX | RV, 12392 DOS_CONTROL_2r, TCP_HDR_OFFSET_EQ1_ENABLEf, 12393 NULL, soc_feature_enhanced_dos_ctrl }, 12394 { bcmSwitchDosAttackUdpPortsEqual, FB2 | RP | TRX | RV, 12395 DOS_CONTROL_2r, UDP_SPORT_EQ_DPORT_ENABLEf, 12396 NULL, soc_feature_enhanced_dos_ctrl }, 12397 { bcmSwitchDosAttackTcpPortsEqual, FB2 | RP | TRX | RV, 12398 DOS_CONTROL_2r, TCP_SPORT_EQ_DPORT_ENABLEf, 12399 NULL, soc_feature_enhanced_dos_ctrl }, 12400 { bcmSwitchDosAttackTcpFlagsSF, FB2 | RP | TRX | RV, 12401 DOS_CONTROL_2r, TCP_FLAGS_SYN_FIN_ENABLEf, 12402 NULL, soc_feature_enhanced_dos_ctrl }, 12403 { bcmSwitchDosAttackTcpFlagsFUP, FB2 | RP | TRX | RV, 12404 DOS_CONTROL_2r, TCP_FLAGS_FIN_URG_PSH_SEQ0_ENABLEf, 12405 NULL, soc_feature_enhanced_dos_ctrl }, 12406 { bcmSwitchDosAttackTcpHdrPartial, FB2 | RP | TRX | RV, 12407 DOS_CONTROL_2r, TCP_HDR_PARTIAL_ENABLEf, 12408 NULL, soc_feature_enhanced_dos_ctrl }, 12409 { bcmSwitchDosAttackV6MinFragEnable, FB2 | RP | TRX | RV, 12410 DOS_CONTROL_2r, IPV6_MIN_FRAG_SIZE_ENABLEf, 12411 NULL, soc_feature_enhanced_dos_ctrl }, 12412 { bcmSwitchDosAttackV6MinFragSize, FB2 | RP | TRX | RV, 12413 IPV6_MIN_FRAG_SIZEr, PKT_LENGTHf, 12414 NULL, soc_feature_enhanced_dos_ctrl }, 12415 12416 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT || BCM_RAPTOR_SUPPORT */ 12417 12418 #if defined(BCM_HAWKEYE_SUPPORT) 12419 { bcmSwitchDosAttackIcmp, HK, 12420 DOS_CONTROLr, ICMP_V4_PING_SIZE_ENABLEf, 12421 NULL, 0 }, 12422 { bcmSwitchDosAttackIcmp, HK, 12423 DOS_CONTROLr, ICMP_V6_PING_SIZE_ENABLEf, 12424 NULL, 0 }, 12425 { bcmSwitchDosAttackIcmpV4, HK, 12426 DOS_CONTROLr, ICMP_V4_PING_SIZE_ENABLEf, 12427 NULL, 0 }, 12428 { bcmSwitchDosAttackIcmpV6, HK, 12429 DOS_CONTROLr, ICMP_V6_PING_SIZE_ENABLEf, 12430 NULL, 0 }, 12431 { bcmSwitchDosAttackIcmpFragments, HK, 12432 DOS_CONTROLr, ICMP_FRAG_PKTS_ENABLEf, 12433 NULL, soc_feature_enhanced_dos_ctrl }, 12434 { bcmSwitchDosAttackTcpOffset, HK, 12435 DOS_CONTROLr, TCP_HDR_OFFSET_EQ1_ENABLEf, 12436 NULL, soc_feature_enhanced_dos_ctrl }, 12437 { bcmSwitchDosAttackUdpPortsEqual, HK, 12438 DOS_CONTROLr, UDP_SPORT_EQ_DPORT_ENABLEf, 12439 NULL, soc_feature_enhanced_dos_ctrl }, 12440 { bcmSwitchDosAttackTcpPortsEqual, HK, 12441 DOS_CONTROLr, TCP_SPORT_EQ_DPORT_ENABLEf, 12442 NULL, soc_feature_enhanced_dos_ctrl }, 12443 { bcmSwitchDosAttackTcpFlagsSF, HK, 12444 DOS_CONTROLr, TCP_FLAGS_SYN_FIN_ENABLEf, 12445 NULL, soc_feature_enhanced_dos_ctrl }, 12446 { bcmSwitchDosAttackTcpFlagsFUP, HK, 12447 DOS_CONTROLr, TCP_FLAGS_FIN_URG_PSH_SEQ0_ENABLEf, 12448 NULL, soc_feature_enhanced_dos_ctrl }, 12449 { bcmSwitchDosAttackTcpHdrPartial, HK, 12450 DOS_CONTROLr, TCP_HDR_PARTIAL_ENABLEf, 12451 NULL, soc_feature_enhanced_dos_ctrl }, 12452 { bcmSwitchDosAttackIcmpPktOversize, HK, 12453 DOS_CONTROL_2r, BIG_ICMP_PKT_SIZEf, 12454 NULL, 0 }, 12455 12456 #endif /* BCM_HAWKEYE_SUPPORT */ 12457 #if defined (BCM_TRIDENT_SUPPORT) || defined (BCM_KATANA_SUPPORT) 12458 { bcmSwitchDosAttackIcmpPktOversize, TD | TR3 | HX4 | KT | KT2 | TD2 | TD2P | TH, 12459 DOS_CONTROL_3r, BIG_ICMP_PKT_SIZEf, 12460 NULL, 0 }, 12461 { bcmSwitchDosAttackIcmpV6PingSize, TD | TR3 | HX4 | KT | KT2 | TD2 | TD2P | TH, 12462 DOS_CONTROL_3r, BIG_ICMPV6_PKT_SIZEf, 12463 NULL, soc_feature_big_icmpv6_ping_check }, 12464 { bcmSwitchDosAttackMinTcpHdrSize, TD | TR3 | HX4 | KT | KT2 | TD2 | TD2P | TH, 12465 DOS_CONTROL_3r, MIN_TCPHDR_SIZEf, 12466 NULL, 0 }, 12467 { bcmSwitchIpmcSameVlanPruning, TD, 12468 CPQLINKMEMDEBUGr, IPMC_IND_MODEf, 12469 _bool_invert, 0 }, 12470 { bcmSwitchHashNivSrcIfEtagSvidSelect0, TD | TR3 | HX4 | KT | TD2 | TD2P | TH | KT2, 12471 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_0_SELECT_Af, 12472 NULL, 0 }, 12473 { bcmSwitchHashNivSrcIfEtagSvidSelect1, TD | TR3 | HX4 | KT | TD2 | TD2P | TH | KT2, 12474 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_0_SELECT_Bf, 12475 NULL, 0 }, 12476 { bcmSwitchHashNivDstIfEtagVidSelect0, TD | TR3 | HX4 | KT | TD2 | TD2P | TH | KT2, 12477 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_1_SELECT_Af, 12478 NULL, 0 }, 12479 { bcmSwitchHashNivDstIfEtagVidSelect1, TD | TR3 | HX4 | KT | TD2 | TD2P | TH | KT2, 12480 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_1_SELECT_Bf, 12481 NULL, 0 }, 12482 #endif /* BCM_TRIDENT_SUPPORT */ 12483 12484 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_SCORPION_SUPPORT) ||\ 12485 defined(BCM_RAPTOR_SUPPORT) 12486 { bcmSwitchSourceMacZeroDrop, FB2 | RP | RV | SCQ | HK, 12487 ING_MISC_CONFIG2r, MACSA_ALL_ZERO_DROPf, 12488 NULL, 0}, 12489 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_SCORPION_SUPPORT || BCM_RAPTOR_SUPPORT */ 12490 12491 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) ||\ 12492 defined(BCM_BRADLEY_SUPPORT) 12493 { bcmSwitchRemoteLearnTrust, BR | GW | RP | FB2 | RV | HK, 12494 ING_CONFIGr, IGNORE_HG_HDR_DONOT_LEARNf, 12495 _bool_invert, 0 }, 12496 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_BRADLEY_SUPPORT || BCM_RAPTOR_SUPPORT */ 12497 12498 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) ||\ 12499 defined(BCM_BRADLEY_SUPPORT) 12500 { bcmSwitchDirectedMirroring, FB | HBGW | FH, 12501 ING_CONFIGr, DRACO1_5_MIRRORf, 12502 _bool_invert, soc_feature_xgs1_mirror }, 12503 { bcmSwitchDirectedMirroring, FB | HBGW | FH | TRX, 12504 EGR_PORTr, EM_SRCMOD_CHANGEf, 12505 NULL, soc_feature_src_modid_blk }, 12506 { bcmSwitchDirectedMirroring, FB | HBGW | FH | TRX, 12507 IEGR_PORTr, EM_SRCMOD_CHANGEf, 12508 NULL, soc_feature_src_modid_blk }, 12509 { bcmSwitchMirrorStackMode, FB | HBGW | FH | HXFX, 12510 ING_CONFIGr, STACK_MODEf, 12511 NULL, soc_feature_src_modid_blk }, 12512 { bcmSwitchMirrorStackMode, FB | HBGW | FH | TRVL, 12513 MISCCONFIGr, STACK_MODEf, 12514 NULL, soc_feature_src_modid_blk }, 12515 { bcmSwitchMirrorSrcModCheck, FB | HBGW | FH | HXFX, 12516 ING_CONFIGr, FB_A0_COMPATIBLEf, 12517 NULL, soc_feature_src_modid_blk }, 12518 { bcmSwitchSrcModBlockMirrorCopy, FB | HBGW | FH | HXFX, 12519 MIRROR_CONTROLr, SRC_MODID_BLOCK_MIRROR_COPYf, 12520 NULL, soc_feature_src_modid_blk }, 12521 { bcmSwitchSrcModBlockMirrorOnly, FB | HBGW | FH | HXFX, 12522 MIRROR_CONTROLr, SRC_MODID_BLOCK_MIRROR_ONLY_PKTf, 12523 NULL, soc_feature_src_modid_blk }, 12524 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT || BCM_BRADLEY_SUPPORT */ 12525 12526 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) ||\ 12527 defined(BCM_RAVEN_SUPPORT) 12528 { bcmSwitchDestPortHGTrunk, FB | FH | HXFX | RV | HK | HU, 12529 ING_MISC_CONFIGr, USE_DEST_PORTf, 12530 NULL, soc_feature_port_trunk_index }, 12531 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT || BCM_RAVEN_SUPPORT */ 12532 12533 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 12534 defined(BCM_HELIX_SUPPORT) || defined(BCM_TRX_SUPPORT) 12535 { bcmSwitchDosAttackIcmpPktOversize, FB | BR | GW | FH | HXFX | TRX, 12536 DOS_CONTROLr, BIG_ICMP_PKT_SIZEf, 12537 NULL, 0 }, 12538 { bcmSwitchDirectedMirroring, FB | HBGW | FH | TRX, 12539 MISCCONFIGr, DRACO_1_5_MIRRORING_MODE_ENf, 12540 _bool_invert, soc_feature_xgs1_mirror }, 12541 { bcmSwitchDosAttackIcmpV6PingSize, FB | FH | HXFX | BR | GW | TRX, 12542 DOS_CONTROL_2r, BIG_ICMPV6_PKT_SIZEf, 12543 NULL, soc_feature_big_icmpv6_ping_check }, 12544 { bcmSwitchMirrorUnmarked, FB | HBGW | FH | HXFX | TRX, 12545 EGR_CONFIG_1r, RING_MODEf, 12546 _bool_invert, 0 }, 12547 { bcmSwitchMirrorStackMode, FB | HBGW | FH | TRX, 12548 EGR_CONFIG_1r, STACK_MODEf, 12549 NULL, soc_feature_src_modid_blk }, 12550 { bcmSwitchMeterAdjust, FB | HBGW | FH | HXFX | TRX, 12551 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf, 12552 NULL, soc_feature_meter_adjust }, 12553 { bcmSwitchMeterAdjust, FB | HBGW | FH | HXFX | TRX, 12554 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTES_2f, 12555 NULL, soc_feature_meter_adjust }, 12556 { bcmSwitchMeterAdjust, FB | HBGW | FH | HXFX | TRX, 12557 FP_METER_CONTROLr, PACKET_IFG_BYTESf, 12558 NULL, soc_feature_meter_adjust }, 12559 { bcmSwitchMeterAdjust, TH, 12560 IFP_METER_CONTROLr, PACKET_IFG_BYTESf, 12561 NULL, soc_feature_meter_adjust }, 12562 { bcmSwitchMeterAdjust, TRVL, 12563 EFP_METER_CONTROL_2r, PACKET_IFG_BYTESf, 12564 NULL, soc_feature_meter_adjust }, 12565 { bcmSwitchMeterAdjust, AP | TR2 | TD | TR3 | HX4 | VL2 | TD2 | TH, 12566 EGR_COUNTER_CONTROLr, PACKET_IFG_BYTESf, 12567 NULL, soc_feature_meter_adjust }, 12568 { bcmSwitchMeterAdjust, AP | TR2 | TD | TR3 | HX4 | VL2 | TD2 | TH, 12569 EGR_COUNTER_CONTROLr, PACKET_IFG_BYTES_2f, 12570 NULL, soc_feature_meter_adjust }, 12571 { bcmSwitchMeterAdjust, TRVL | KT2, 12572 MTRI_IFGr, PACKET_IFG_BYTESf, 12573 NULL, soc_feature_meter_adjust }, 12574 { bcmSwitchEgressBlockUcast, FB | HBGW | FH | HXFX | TRX, 12575 ING_MISC_CONFIGr, APPLY_EGR_MASK_ON_UC_ONLYf, 12576 NULL, soc_feature_egress_blk_ucast_override }, 12577 { bcmSwitchSourceModBlockUcast, FB | HBGW | FH | HXFX | TRX, 12578 ING_MISC_CONFIGr, APPLY_SRCMOD_BLOCK_ON_UC_ONLYf, 12579 NULL, soc_feature_src_modid_blk_ucast_override }, 12580 { bcmSwitchHgHdrMcastFloodOverride, FB | BR | GW | FH | HXFX | TRX, 12581 EGR_CONFIG_1r, FORCE_STATIC_MH_PFMf, 12582 NULL, soc_feature_static_pfm }, 12583 { bcmSwitchShaperAdjust, FB | HBGW | FH | HXFX | TRX, 12584 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf, 12585 NULL, soc_feature_meter_adjust }, 12586 { bcmSwitchShaperAdjust, FB | HBGW | FH | HXFX | TRX, 12587 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTES_2f, 12588 NULL, soc_feature_meter_adjust }, 12589 { bcmSwitchShaperAdjust, TRVL | KT2, 12590 MTRI_IFGr, PACKET_IFG_BYTESf, 12591 NULL, soc_feature_meter_adjust }, 12592 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_BRADLEY_SUPPORT || 12593 BCM_HELIX_SUPPORT || BCM_TRX_SUPPORT */ 12594 12595 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 12596 defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 12597 { bcmSwitchHgHdrErrToCpu, FB2 | HBGW | RP | TRX | RV | HK, 12598 CPU_CONTROL_1r, HG_HDR_ERROR_TOCPUf, 12599 NULL, soc_feature_cpu_proto_prio}, 12600 { bcmSwitchClassTagPacketsToCpu, FB2 | HBGW | RP | TRX | RV | HK, 12601 CPU_CONTROL_1r, HG_HDR_TYPE1_TOCPUf, 12602 NULL, soc_feature_cpu_proto_prio}, 12603 { bcmSwitchRemoteLearnTrust, BR | GW | RP | RV | FB2 | TRX | HK, 12604 EGR_CONFIG_1r, IGNORE_HG_HDR_DONOT_LEARNf, 12605 _bool_invert, 0 }, 12606 { bcmSwitchSourceModBlockControlOpcode, FB2 | HBGW | RP | TRX | RV | HK, 12607 ING_MISC_CONFIGr, DO_NOT_APPLY_SRCMOD_BLOCK_ON_SCf, 12608 _bool_invert, soc_feature_src_modid_blk_opcode_override }, 12609 #endif /* BCM_RAPTOR_SUPPORT || BCM_BRADLEY_SUPPORT || 12610 BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 12611 12612 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_BRADLEY_SUPPORT) || \ 12613 defined(BCM_FIREBOLT2_SUPPORT) 12614 { bcmSwitchCpuProtoBpduPriority, FB2 | BR | GW | RP | RV | HK, 12615 CPU_CONTROL_3r, CPU_PROTO_BPDU_PRIORITYf, 12616 NULL, soc_feature_cpu_proto_prio }, 12617 { bcmSwitchCpuProtoArpPriority, FB2 | BR | GW | RP | RV | HK, 12618 CPU_CONTROL_3r, CPU_PROTO_ARP_PRIORITYf, 12619 NULL, soc_feature_cpu_proto_prio }, 12620 { bcmSwitchCpuProtoIgmpPriority, FB2 | BR | GW | RP | RV | HK, 12621 CPU_CONTROL_3r, CPU_PROTO_IGMP_PRIORITYf, 12622 NULL, soc_feature_cpu_proto_prio }, 12623 { bcmSwitchCpuProtoDhcpPriority, FB2 | BR | GW | RP | RV | HK, 12624 CPU_CONTROL_3r, CPU_PROTO_DHCP_PRIORITYf, 12625 NULL, soc_feature_cpu_proto_prio }, 12626 { bcmSwitchCpuProtoIpmcReservedPriority, FB2 | BR | GW | RP | RV | HK, 12627 CPU_CONTROL_3r, CPU_PROTO_IPMC_RESERVED_PRIORITYf, 12628 NULL, soc_feature_cpu_proto_prio }, 12629 { bcmSwitchCpuProtoIpOptionsPriority, FB2 | BR | GW | RP | RV | HK, 12630 CPU_CONTROL_3r, CPU_PROTO_IP_OPTIONS_PRIORITYf, 12631 NULL, soc_feature_cpu_proto_prio }, 12632 { bcmSwitchCpuProtoExceptionsPriority, FB2 | BR | GW | RP | RV | HK, 12633 CPU_CONTROL_3r, CPU_PROTO_EXCEPTIONS_PRIORITYf, 12634 NULL, soc_feature_cpu_proto_prio }, 12635 #endif /* BCM_RAPTOR_SUPPORT || BCM_BRADLEY_SUPPORT || 12636 BCM_FIREBOLT2_SUPPORT */ 12637 12638 12639 #if defined(BCM_HELIX_SUPPORT) || defined(BCM_FIREBOLT_SUPPORT) || \ 12640 defined(BCM_BRADLEY_SUPPORT) 12641 { bcmSwitchUnknownIpmcToCpu, FB | BR | GW | FH | HXFX, 12642 CPU_CONTROL_1r, UIPMC_TOCPUf, 12643 NULL, soc_feature_unknown_ipmc_tocpu }, 12644 { bcmSwitchIcmpRedirectToCpu, FB | BR | GW | FH | HXFX, 12645 CPU_CONTROL_1r, ICMP_REDIRECT_TOCPUf, 12646 NULL, 0 }, 12647 { bcmSwitchCpuUnknownPrio, FB | BR | GW | FH | HXFX, 12648 CPU_CONTROL_2r, CPU_LKUPFAIL_PRIORITYf, 12649 NULL, 0 }, 12650 { bcmSwitchCpuSamplePrio, FB | BR | GW | FH | HXFX, 12651 CPU_CONTROL_2r, CPU_SFLOW_PRIORITYf, 12652 NULL, 0 }, 12653 { bcmSwitchCpuDefaultPrio, FB | BR | GW | FH | HXFX, 12654 CPU_CONTROL_2r, CPU_DEFAULT_PRIORITYf, 12655 NULL, 0 }, 12656 { bcmSwitchCpuMtuFailPrio, FB | BR | GW | FH | HXFX, 12657 CPU_CONTROL_2r, CPU_MTUFAIL_PRIORITYf, 12658 NULL, 0 }, 12659 { bcmSwitchCpuMirrorPrio, FB | BR | GW | FH | HXFX, 12660 CPU_CONTROL_2r, CPU_MIRROR_PRIORITYf, 12661 NULL, 0 }, 12662 { bcmSwitchCpuIcmpRedirectPrio, FB | BR | GW | FH | HXFX, 12663 CPU_CONTROL_2r, CPU_ICMP_REDIRECT_PRIORITYf, 12664 NULL, 0 }, 12665 { bcmSwitchCpuFpCopyPrio, FB | HBGW | FH | HXFX, 12666 CPU_CONTROL_2r, CPU_FPCOPY_PRIORITYf, 12667 NULL, 0 }, 12668 { bcmSwitchDosAttackTcpFlags, FB | BR | GW | FH, 12669 DOS_CONTROLr, TCP_FLAGS_CHECK_ENABLEf, 12670 NULL, soc_feature_basic_dos_ctrl }, 12671 { bcmSwitchDosAttackL4Port, FB | BR | GW | FH, 12672 DOS_CONTROLr, L4_PORT_CHECK_ENABLEf, 12673 NULL, soc_feature_basic_dos_ctrl }, 12674 { bcmSwitchDosAttackTcpFrag, FB | BR | GW | FH, 12675 DOS_CONTROLr, TCP_FRAG_CHECK_ENABLEf, 12676 NULL, soc_feature_basic_dos_ctrl }, 12677 { bcmSwitchDosAttackIcmp, FB | BR | GW | FH, 12678 DOS_CONTROLr, ICMP_CHECK_ENABLEf, 12679 NULL, soc_feature_basic_dos_ctrl }, 12680 #endif /* BCM_HELIX_SUPPORT || BCM_FIREBOLT_SUPPORT || 12681 BCM_BRADLEY_SUPPORT */ 12682 12683 #if defined(BCM_HELIX_SUPPORT) || defined(BCM_FIREBOLT_SUPPORT) || \ 12684 defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRX_SUPPORT) 12685 { bcmSwitchUnknownMcastToCpu, FB | BR | GW | FH | HXFX | TRX, 12686 CPU_CONTROL_1r, UMC_TOCPUf, 12687 NULL, 0 }, 12688 { bcmSwitchUnknownUcastToCpu, FB | BR | GW | FH | HXFX | TRX, 12689 CPU_CONTROL_1r, UUCAST_TOCPUf, 12690 NULL, 0 }, 12691 { bcmSwitchL2StaticMoveToCpu, FB | BR | GW | FH | HXFX | TRX, 12692 CPU_CONTROL_1r, STATICMOVE_TOCPUf, 12693 NULL, 0 }, 12694 { bcmSwitchL3HeaderErrToCpu, FB | BR | GW | FH | HXFX | TRX, /* compat */ 12695 CPU_CONTROL_1r, V4L3ERR_TOCPUf, 12696 NULL, 0 }, 12697 { bcmSwitchUnknownL3SrcToCpu, FB | BR | GW | FH | RP | RV | TRX, 12698 CPU_CONTROL_1r, UNRESOLVEDL3SRC_TOCPUf, 12699 NULL, 0 }, 12700 { bcmSwitchUnknownL3DestToCpu, FB | BR | GW | FH | HXFX | TRX, /* compat */ 12701 CPU_CONTROL_1r, V4L3DSTMISS_TOCPUf, 12702 NULL, 0 }, 12703 { bcmSwitchIpmcPortMissToCpu, FB | BR | GW | FH | RP | RV | TRX, 12704 CPU_CONTROL_1r, IPMCPORTMISS_TOCPUf, 12705 NULL, 0 }, 12706 { bcmSwitchIpmcErrorToCpu, FB | BR | GW | FH | RP | RV | TRX, 12707 CPU_CONTROL_1r, IPMCERR_TOCPUf, 12708 NULL, 0 }, 12709 { bcmSwitchL2NonStaticMoveToCpu, FB | BR | GW | FH | HXFX | TRX, 12710 CPU_CONTROL_1r, NONSTATICMOVE_TOCPUf, 12711 NULL, 0 }, 12712 { bcmSwitchV6L3ErrToCpu, FB | BR | GW | FH | HXFX | TRX, 12713 CPU_CONTROL_1r, V6L3ERR_TOCPUf, 12714 NULL, 0 }, 12715 { bcmSwitchV6L3DstMissToCpu, FB | BR | GW | FH | RP | RV | TRX, 12716 CPU_CONTROL_1r, V6L3DSTMISS_TOCPUf, 12717 NULL, 0 }, 12718 { bcmSwitchV4L3ErrToCpu, FB | BR | GW | FH | HXFX | TRX, 12719 CPU_CONTROL_1r, V4L3ERR_TOCPUf, 12720 NULL, 0 }, 12721 { bcmSwitchV4L3DstMissToCpu, FB | BR | GW | FH | HXFX | TRX, 12722 CPU_CONTROL_1r, V4L3DSTMISS_TOCPUf, 12723 NULL, 0 }, 12724 { bcmSwitchTunnelErrToCpu, FB | BR | GW | FH | HXFX | TRX, 12725 CPU_CONTROL_1r, TUNNEL_ERR_TOCPUf, 12726 NULL, 0 }, 12727 { bcmSwitchMartianAddrToCpu, FB | BR | GW | FH | HXFX | TRX, 12728 CPU_CONTROL_1r, MARTIAN_ADDR_TOCPUf, 12729 NULL, 0 }, 12730 { bcmSwitchL3UcTtlErrToCpu, FB | BR | GW | FH | HXFX | TRX, 12731 CPU_CONTROL_1r, L3UC_TTL_ERR_TOCPUf, 12732 NULL, 0 }, 12733 { bcmSwitchL3SlowpathToCpu, FB | BR | GW | FH | HXFX | TRX, 12734 CPU_CONTROL_1r, L3_SLOWPATH_TOCPUf, 12735 NULL, 0 }, 12736 { bcmSwitchIpmcTtlErrToCpu, FB | BR | GW | FH | RP | RV | TRX, 12737 CPU_CONTROL_1r, IPMC_TTL_ERR_TOCPUf, 12738 NULL, 0 }, 12739 { bcmSwitchSampleIngressRandomSeed, FB | BR | GW | FH | HXFX | TRX, 12740 SFLOW_ING_RAND_SEEDr, SEEDf, 12741 NULL, 0 }, 12742 { bcmSwitchSampleEgressRandomSeed, FB | BR | GW | FH | HXFX | TRX, 12743 SFLOW_EGR_RAND_SEEDr, SEEDf, 12744 NULL, 0 }, 12745 { bcmSwitchArpReplyToCpu, FB | BR | GW | FH | HXFX | TRX, 12746 PROTOCOL_PKT_CONTROLr, ARP_REPLY_TO_CPUf, 12747 NULL, 0 }, 12748 { bcmSwitchArpReplyDrop, FB | BR | GW | FH | HXFX | TRX, 12749 PROTOCOL_PKT_CONTROLr, ARP_REPLY_DROPf, 12750 NULL, 0 }, 12751 { bcmSwitchArpRequestToCpu, FB | BR | GW | FH | HXFX | TRX, 12752 PROTOCOL_PKT_CONTROLr, ARP_REQUEST_TO_CPUf, 12753 NULL, 0 }, 12754 { bcmSwitchArpRequestDrop, FB | BR | GW | FH | HXFX | TRX, 12755 PROTOCOL_PKT_CONTROLr, ARP_REQUEST_DROPf, 12756 NULL, 0 }, 12757 { bcmSwitchNdPktToCpu, FB | BR | GW | FH | HXFX | TRX, 12758 PROTOCOL_PKT_CONTROLr, ND_PKT_TO_CPUf, 12759 NULL, 0 }, 12760 { bcmSwitchNdPktDrop, FB | BR | GW | FH | HXFX | TRX, 12761 PROTOCOL_PKT_CONTROLr, ND_PKT_DROPf, 12762 NULL, 0 }, 12763 { bcmSwitchDhcpPktToCpu, FB | BR | GW | FH | HXFX | TRX, 12764 PROTOCOL_PKT_CONTROLr, DHCP_PKT_TO_CPUf, 12765 NULL, 0 }, 12766 { bcmSwitchDhcpPktDrop, FB | BR | GW | FH | HXFX | TRX, 12767 PROTOCOL_PKT_CONTROLr, DHCP_PKT_DROPf, 12768 NULL, 0 }, 12769 { bcmSwitchDosAttackSipEqualDip, FB | BR | GW | FH | HXFX | TRX, 12770 DOS_CONTROLr, DROP_IF_SIP_EQUALS_DIPf, 12771 NULL, 0 }, 12772 { bcmSwitchDosAttackMinTcpHdrSize, FB | BR | GW | FH | HXFX | TRX, 12773 DOS_CONTROLr, MIN_TCPHDR_SIZEf, 12774 NULL, 0 }, 12775 { bcmSwitchDosAttackV4FirstFrag, FB | BR | GW | FH | HXFX | TRX, 12776 DOS_CONTROLr, IPV4_FIRST_FRAG_CHECK_ENABLEf, 12777 NULL, 0 }, 12778 { bcmSwitchNonIpL3ErrToCpu, FB | BR | GW | FH | HXFX | TRX, 12779 CPU_CONTROL_1r, NIP_L3ERR_TOCPUf, 12780 NULL, soc_feature_nip_l3_err_tocpu }, 12781 { bcmSwitchSourceRouteToCpu, FB | BR | GW | FH | HXFX | TRX, 12782 CPU_CONTROL_1r, SRCROUTE_TOCPUf, 12783 NULL, 0 }, 12784 { bcmSwitchParityErrorToCpu, FB | HBGW | FH | HXFX | SCQ, 12785 CPU_CONTROL_1r, PARITY_ERR_TOCPUf, 12786 NULL, soc_feature_parity_err_tocpu }, 12787 { bcmSwitchDirectedMirroring, FB | HBGW | FH | TRX, 12788 EGR_CONFIGr, DRACO1_5_MIRRORf, 12789 _bool_invert, soc_feature_xgs1_mirror}, 12790 #endif /* BCM_HELIX_SUPPORT || BCM_FIREBOLT_SUPPORT || 12791 BCM_BRADLEY_SUPPORT || BCM_TRX_SUPPORT */ 12792 12793 #if defined(BCM_HELIX_SUPPORT) || defined(BCM_FIREBOLT_SUPPORT) || \ 12794 defined(BCM_BRADLEY_SUPPORT) || \ 12795 defined(BCM_SCORPION_SUPPORT) 12796 { bcmSwitchDosAttackToCpu, FB | BR | GW | FH | HXFX | SCQ, 12797 CPU_CONTROL_1r, DOSATTACK_TOCPUf, 12798 NULL, 0 }, 12799 #endif /* BCM_HELIX_SUPPORT || BCM_FIREBOLT_SUPPORT || 12800 BCM_BRADLEY_SUPPORT || BCM_SCORPION_SUPPORT*/ 12801 12802 #if defined(BCM_BRADLEY_SUPPORT) || \ 12803 defined(BCM_RAPTOR_SUPPORT) || defined(BCM_SCORPION_SUPPORT) 12804 { bcmSwitchUnknownVlanToCpu, HBGW | RP | RV | SCQ | HK, 12805 CPU_CONTROL_1r, UVLAN_TOCPUf, 12806 NULL, 0 }, 12807 12808 #endif /* BCM_BRADLEY_SUPPORT || 12809 BCM_RAPTOR_SUPPORT || BCM_SCORPION_SUPPORT */ 12810 12811 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) || \ 12812 defined(BCM_BRADLEY_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) 12813 { bcmSwitchPortEgressBlockL3, FB | FH | HXFX | HBGW | RP | RV | HK, 12814 ING_CONFIGr, APPLY_EGR_MASK_ON_L3f, 12815 NULL, soc_feature_port_egr_block_ctl }, 12816 { bcmSwitchPortEgressBlockL2, FB | FH | HXFX | HBGW | RP | RV | HK, 12817 ING_CONFIGr, APPLY_EGR_MASK_ON_L2f, 12818 NULL, soc_feature_port_egr_block_ctl }, 12819 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT || 12820 BCM_BRADLEY_SUPPORT || BCM_RAPTOR_SUPPORT */ 12821 12822 #if defined(BCM_FIREBOLT_SUPPORT) || defined(BCM_HELIX_SUPPORT) || \ 12823 defined(BCM_BRADLEY_SUPPORT) || defined(BCM_RAVEN_SUPPORT) || \ 12824 defined(BCM_TRX_SUPPORT) 12825 { bcmSwitchL3MtuFailToCpu, FB | BR | GW | FH | RP | RV | TRX, 12826 CPU_CONTROL_1r, L3_MTU_FAIL_TOCPUf, 12827 NULL, soc_feature_l3mtu_fail_tocpu }, 12828 { bcmSwitchIpmcSameVlanL3Route, FB | BR | GW | FH | HXFX | TRX | RV | HK, 12829 EGR_CONFIG_1r, IPMC_ROUTE_SAME_VLANf, 12830 NULL, soc_feature_l3}, 12831 { bcmSwitchIpmcSameVlanPruning, FB | BR | GW | FH | HXFX | TRX | RV | HK, 12832 MISCCONFIGr, IPMC_IND_MODEf, 12833 _bool_invert, 0 }, 12834 #endif /* BCM_FIREBOLT_SUPPORT || BCM_HELIX_SUPPORT || 12835 BCM_BRADLEY_SUPPORT || BCM_RAVEN_SUPPORT || BCM_TRX_SUPPORT */ 12836 12837 #if defined(BCM_HAWKEYE_SUPPORT) 12838 { bcmSwitchCpuProtoTimeSyncPrio, HK, 12839 CPU_CONTROL_4r, CPU_PROTO_TS_PRIORITYf, 12840 NULL, soc_feature_cpu_proto_prio }, 12841 { bcmSwitchCpuProtoMmrpPrio, HK, 12842 CPU_CONTROL_4r, CPU_PROTO_MMRP_PRIORITYf, 12843 NULL, soc_feature_cpu_proto_prio }, 12844 { bcmSwitchCpuProtoSrpPrio, HK, 12845 CPU_CONTROL_4r, CPU_PROTO_SRP_PRIORITYf, 12846 NULL, soc_feature_cpu_proto_prio }, 12847 12848 #endif /* BCM_HAWKEYE_SUPPORT */ 12849 12850 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 12851 { bcmSwitchPrioDropToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH | KT2, 12852 CPU_CONTROL_0r, DOT1P_ADMITTANCE_DROP_TOCPUf, 12853 NULL, soc_feature_niv}, 12854 { bcmSwitchNivPrioDropToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH | KT2, 12855 CPU_CONTROL_0r, DOT1P_ADMITTANCE_DROP_TOCPUf, 12856 NULL, soc_feature_niv}, 12857 { bcmSwitchNivInterfaceMissToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH | KT2, 12858 CPU_CONTROL_0r, NIV_FORWARDING_DROP_TOCPUf, 12859 NULL, soc_feature_niv}, 12860 { bcmSwitchNivRpfFailToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH | KT2, 12861 CPU_CONTROL_0r, NIV_RPF_CHECK_FAIL_TOCPUf, 12862 NULL, soc_feature_niv}, 12863 { bcmSwitchNivTagInvalidToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH | KT2, 12864 CPU_CONTROL_0r, VNTAG_FORMAT_DROP_TOCPUf, 12865 NULL, soc_feature_niv}, 12866 { bcmSwitchNivTagDropToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH | KT2, 12867 CPU_CONTROL_0r, DISCARD_VNTAG_PRESENT_TOCPUf, 12868 NULL, soc_feature_niv}, 12869 { bcmSwitchNivUntagDropToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH | KT2, 12870 CPU_CONTROL_0r, DISCARD_VNTAG_NOT_PRESENT_TOCPUf, 12871 NULL, soc_feature_niv}, 12872 { bcmSwitchTrillTtlErrToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH, 12873 CPU_CONTROL_0r, TRILL_HOPCOUNT_CHECK_FAIL_TOCPUf, 12874 NULL, soc_feature_trill}, 12875 { bcmSwitchTrillHeaderErrToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH, 12876 CPU_CONTROL_0r, TRILL_ERROR_FRAMES_TOCPUf, 12877 NULL, soc_feature_trill}, 12878 { bcmSwitchTrillMismatchToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH, 12879 CPU_CONTROL_0r, TRILL_UNEXPECTED_FRAMES_TOCPUf, 12880 NULL, soc_feature_trill}, 12881 { bcmSwitchTrillNameMissToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH, 12882 CPU_CONTROL_0r, TRILL_RBRIDGE_LOOKUP_MISS_TOCPUf, 12883 NULL, soc_feature_trill}, 12884 { bcmSwitchTrillRpfFailToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH, 12885 CPU_CONTROL_0r, TRILL_RPF_CHECK_FAIL_TOCPUf, 12886 NULL, soc_feature_trill}, 12887 { bcmSwitchTrillOptionsToCpu, TD | TR3 | HX4 | TD2 | TD2P | TH, 12888 CPU_CONTROL_0r, TRILL_OPTIONS_TOCPUf, 12889 NULL, soc_feature_trill}, 12890 { bcmSwitchTrillNameErrDrop, TD | TR3 | HX4 | TD2 | TD2P | TH, 12891 TRILL_DROP_CONTROLr, INGRESS_RBRIDGE_EQ_EGRESS_RBRIDGE_DROPf, 12892 NULL, soc_feature_trill}, 12893 { bcmSwitchTrillHeaderVersionErrDrop, TD | TR3 | HX4 | TD2 | TD2P | TH, 12894 TRILL_DROP_CONTROLr, TRILL_HDR_VERSION_NON_ZERO_DROPf, 12895 NULL, soc_feature_trill}, 12896 { bcmSwitchTrillNameMissDrop, TD | TR3 | HX4 | TD2 | TD2P | TH, 12897 TRILL_DROP_CONTROLr, UNKNOWN_INGRESS_RBRIDGE_DROPf, 12898 NULL, soc_feature_trill}, 12899 { bcmSwitchTrillAdjacencyFailDrop, TD | TR3 | HX4 | TD2 | TD2P | TH, 12900 TRILL_DROP_CONTROLr, TRILL_ADJACENCY_FAIL_DROPf, 12901 NULL, soc_feature_trill}, 12902 { bcmSwitchTrillHeaderErrDrop, TD | TR3 | HX4 | TD2 | TD2P | TH, 12903 TRILL_DROP_CONTROLr, UC_TRILL_HDR_MC_MACDA_DROPf, 12904 NULL, soc_feature_trill}, 12905 { bcmSwitchTrillRpfFailDrop, TD | TR3 | HX4 | TD2 | TD2P | TH, 12906 TRILL_DROP_CONTROLr, RPF_CHECK_FAIL_DROPf, 12907 NULL, soc_feature_trill}, 12908 { bcmSwitchIngParseL2TunnelTermDipSipSelect, TD | TR3 | HX4 | TD2 | TD2P | TH | KT | KT2, 12909 ING_L2_TUNNEL_PARSE_CONTROLr, IFP_L2_TUNNEL_PAYLOAD_FIELD_SELf , 12910 NULL, 0}, 12911 { bcmSwitchIngParseL3L4IPv4, TD | TT | TT2 | TR3 | HX4 | TD2 | TD2P | TH | KT | KT2, 12912 ING_L2_TUNNEL_PARSE_CONTROLr, IGMP_ENABLEf , 12913 NULL, 0}, 12914 { bcmSwitchIngParseL3L4IPv6, TD | TT | TT2 | TR3 | HX4 | TD2 | TD2P | TH | KT | KT2, 12915 ING_L2_TUNNEL_PARSE_CONTROLr, MLD_ENABLEf , 12916 NULL, 0}, 12917 { bcmSwitchV6L3LocalLinkDrop, TD | TR3 | HX4 | TD2 | TD2P | TH, 12918 ING_MISC_CONFIG2r, IPV6_SIP_LINK_LOCAL_DROPf, 12919 NULL, 0}, 12920 /* This switch control is valid for TD+ only. 12921 * 'soc_feature_l3_ecmp_1k_groups' is used to 12922 * distinguish between TD and TD+ */ 12923 { bcmSwitchEcmpMacroFlowHashEnable, TD, 12924 ING_CONFIG_2r, ECMP_HASH_16BITSf, 12925 NULL, soc_feature_l3_ecmp_1k_groups }, 12926 #endif /* BCM_TRIDENT_SUPPORT || BCM_KATANA_SUPPORT || BCM_KATANA2_SUPPORT*/ 12927 12928 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_PE_SUPPORT) 12929 { bcmSwitchExtenderInterfaceMissToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12930 CPU_CONTROL_0r, NIV_FORWARDING_DROP_TOCPUf, 12931 NULL, soc_feature_port_extension}, 12932 { bcmSwitchExtenderRpfFailToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12933 CPU_CONTROL_0r, NIV_RPF_CHECK_FAIL_TOCPUf, 12934 NULL, soc_feature_port_extension}, 12935 { bcmSwitchEtagInvalidToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12936 CPU_CONTROL_0r, VNTAG_FORMAT_DROP_TOCPUf, 12937 NULL, soc_feature_port_extension}, 12938 { bcmSwitchEtagDropToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12939 CPU_CONTROL_0r, DISCARD_VNTAG_PRESENT_TOCPUf, 12940 NULL, soc_feature_port_extension}, 12941 { bcmSwitchNonEtagDropToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12942 CPU_CONTROL_0r, DISCARD_VNTAG_NOT_PRESENT_TOCPUf, 12943 NULL, soc_feature_port_extension}, 12944 { bcmSwitchMplsGalAlertLabelToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12945 CPU_CONTROL_Mr, MPLS_GAL_EXPOSED_TO_CPUf, 12946 NULL, 0}, 12947 { bcmSwitchMplsRalAlertLabelToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12948 CPU_CONTROL_Mr, MPLS_RAL_EXPOSED_TO_CPUf, 12949 NULL, 0}, 12950 { bcmSwitchMplsIllegalReservedLabelToCpu, TR3 | HX4 | TD2 | TD2P | TH | KT2, 12951 CPU_CONTROL_Mr, MPLS_ILLEGAL_RSVD_LABEL_TO_CPUf, 12952 NULL, 0}, 12953 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_TRIDENT2_SUPPORT || BCM_PE_SUPPORT */ 12954 12955 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 12956 { bcmSwitchMplsUnknownAchTypeToCpu, TR3 | HX4 | TD2 | TD2P | TH, 12957 CPU_CONTROL_Mr, MPLS_UNKNOWN_ACH_TYPE_TO_CPUf, 12958 NULL, 0}, 12959 { bcmSwitchMplsUnknownAchVersionToCpu, TR3 | HX4 | TD2 | TD2P | TH, 12960 CPU_CONTROL_Mr, MPLS_UNKNOWN_ACH_VERSION_TOCPUf, 12961 NULL, 0}, 12962 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_TRIDENT2_SUPPORT */ 12963 12964 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 12965 { bcmSwitchFailoverDropToCpu, TR3 | HX4 | TD2P, 12966 CPU_CONTROL_1r, PROTECTION_DATA_DROP_TOCPUf, 12967 NULL, 0}, 12968 { bcmSwitchMplsReservedEntropyLabelToCpu, TR3 | HX4, 12969 CPU_CONTROL_Mr, ENTROPY_LABEL_IN_0_15_RANGE_TO_CPUf, 12970 NULL, 0}, 12971 { bcmSwitchL3SrcBindMissToCpu, TR3 | HX4 | TD2 | TD2P | TH, 12972 CPU_CONTROL_Mr, MAC_IP_BIND_LOOKUP_MISS_TOCPUf, 12973 NULL, 0}, 12974 { bcmSwitchMplsLookupsExceededToCpu, TR3 | HX4, 12975 CPU_CONTROL_Mr, MPLS_OUT_OF_LOOKUPS_TOCPUf, 12976 NULL, 0}, 12977 { bcmSwitchTimesyncUnknownVersionToCpu, TR3 | HX4 | TD2 | TD2P | TH, 12978 CPU_CONTROL_Mr, UNKNOWN_1588_VERSION_TO_CPUf, 12979 NULL, 0}, 12980 { bcmSwitchTimesyncIngressVersion, TR3 | HX4 | TD2 | TD2P | TH, 12981 ING_1588_PARSING_CONTROLr, VERSION_CONTROLf, 12982 NULL, 0}, 12983 { bcmSwitchTimesyncEgressVersion, TR3 | HX4 | TD2 | TD2P | TH, 12984 EGR_1588_PARSING_CONTROLr, VERSION_CONTROLf, 12985 NULL, 0}, 12986 { bcmSwitchCongestionCnmToCpu, TR3 | HX4 | TD2 | TD2P, 12987 IE2E_CONTROLr, ICNM_TO_CPUf, 12988 NULL, 0}, 12989 { bcmSwtichCongestionCnmProxyErrorToCpu, TR3 | HX4 | TD2 | TD2P, 12990 ING_MISC_CONFIGr, QCN_CNM_PRP_DLF_TO_CPUf, 12991 NULL, 0}, 12992 { bcmSwtichCongestionCnmProxyToCpu, TR3 | HX4 | TD2 | TD2P, 12993 ING_MISC_CONFIGr, QCN_CNM_PRP_TO_CPUf, 12994 NULL, 0}, 12995 { bcmSwitchL2GreTunnelMissToCpu, TR3 | HX4 | TD2 | TD2P | TH, 12996 CPU_CONTROL_Mr, L2GRE_SIP_LOOKUP_FAIL_COPY_TOCPUf, 12997 NULL, 0}, 12998 { bcmSwitchL2GreVpnIdMissToCpu, TR3 | HX4 | TD2 | TD2P | TH, 12999 CPU_CONTROL_Mr, L2GRE_VPNID_LOOKUP_FAIL_COPY_TOCPUf, 13000 NULL, 0}, 13001 { bcmSwitchWlanTunnelErrorDrop, TR3 | HX4, 13002 ING_CONFIG_64r, WLAN_DECRYPT_OFFLOAD_ENABLEf, 13003 _bool_invert, 0}, 13004 { bcmSwitchMplsReservedEntropyLabelDrop, TR3 | HX4, 13005 DROP_CONTROL_0r, ENTROPY_LABEL_IN_0_15_RANGE_DO_NOT_DROPf, 13006 _bool_invert, 0}, 13007 { bcmSwitchRemoteProtectionTrust, TR3 | HX4 | TD2 | TD2P | TH | KT2, 13008 ING_CONFIG_64r, USE_PROT_STATUSf, 13009 NULL, 0}, 13010 { bcmSwitchVxlanTunnelMissToCpu, TD2 | TD2P | TH, 13011 CPU_CONTROL_Mr, VXLAN_SIP_LOOKUP_FAIL_COPY_TOCPUf, 13012 NULL, 0}, 13013 { bcmSwitchVxlanVnIdMissToCpu, TD2 | TD2P | TH, 13014 CPU_CONTROL_Mr, VXLAN_VN_ID_LOOKUP_FAIL_COPY_TOCPUf, 13015 NULL, 0}, 13016 { bcmSwitchHashL2GreKeyMask0, TR3 | HX4 | TD2 | TD2P | TH, 13017 RTAG7_HASH_CONTROL_L2GRE_MASK_Ar, L2GRE_TUNNEL_GRE_KEY_MASK_Af, 13018 NULL, soc_feature_l2gre}, 13019 { bcmSwitchHashL2GreKeyMask1, TR3 | HX4 | TD2 | TD2P | TH, 13020 RTAG7_HASH_CONTROL_L2GRE_MASK_Br, L2GRE_TUNNEL_GRE_KEY_MASK_Bf, 13021 NULL, soc_feature_l2gre}, 13022 { bcmSwitchRemoteProtectionEnable, TR3 | HX4 | TD2 | TD2P | KT2 , 13023 EGR_HG_HDR_PROT_STATUS_TX_CONTROLr, SET_PROT_STATUSf, 13024 NULL, 0}, 13025 { bcmSwitchHashSctpL4Port, TR3 | HX4 | TD2 | TD2P | TH, 13026 ING_SCTP_CONTROLr, PARSE_SCTPf, 13027 NULL, 0}, 13028 #endif /* BCM_TRIUMPH3_SUPPORT */ 13029 #if defined(BCM_TRIDENT2_SUPPORT) 13030 { bcmSwitchL3NATEnable, TD2 | TD2P | TH, 13031 ING_CONFIG_64r, NAT_ENABLEf, 13032 NULL, 0}, 13033 { bcmSwitchL3DNATHairpinToCpu, TD2 | TD2P | TH, 13034 CPU_CONTROL_Mr, DNAT_HAIRPIN_COPY_TOCPUf, 13035 NULL, 0}, 13036 { bcmSwitchL3DNATMissToCpu, TD2 | TD2P | TH, 13037 CPU_CONTROL_Mr, DNAT_MISS_COPY_TOCPUf, 13038 NULL, 0}, 13039 { bcmSwitchL3SNATMissToCpu, TD2 | TD2P | TH, 13040 CPU_CONTROL_Mr, SNAT_MISS_COPY_TOCPUf, 13041 NULL, 0}, 13042 { bcmSwitchL3NatOtherToCpu, TD2 | TD2P | TH, 13043 CPU_CONTROL_Mr, NAT_OTHER_COPY_TOCPUf, 13044 NULL, 0}, 13045 { bcmSwitchL3NatRealmCrossingIcmpToCpu, TD2 | TD2P | TH, 13046 CPU_CONTROL_Mr, NAT_REALM_CROSSING_ICMP_COPY_TOCPUf, 13047 NULL, 0}, 13048 { bcmSwitchL3NatFragmentsToCpu, TD2 | TD2P | TH, 13049 CPU_CONTROL_Mr, NAT_FRAGMENTS_COPY_TOCPUf, 13050 NULL, 0}, 13051 { bcmSwitchHashUseL2GreTunnelGreKey0, TD2 | TD2P | TH, 13052 RTAG7_HASH_CONTROL_2r, L2GRE_TUNNEL_USE_GRE_KEY_Af, 13053 NULL, soc_feature_l2gre}, 13054 { bcmSwitchHashUseL2GreTunnelGreKey1, TD2 | TD2P | TH, 13055 RTAG7_HASH_CONTROL_2r, L2GRE_TUNNEL_USE_GRE_KEY_Bf, 13056 NULL, soc_feature_l2gre}, 13057 { bcmSwitchHashL2GrePayloadSelect0, TD2 | TD2P | TH, 13058 RTAG7_HASH_CONTROL_2r, L2GRE_PAYLOAD_HASH_SELECT_Af, 13059 NULL, soc_feature_l2gre}, 13060 { bcmSwitchHashL2GrePayloadSelect1, TD2 | TD2P | TH, 13061 RTAG7_HASH_CONTROL_2r, L2GRE_PAYLOAD_HASH_SELECT_Bf, 13062 NULL, soc_feature_l2gre}, 13063 { bcmSwitchHashL2GreNetworkPortPayloadDisable0, TD2 | TD2P | TH, 13064 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_L2GRE_Af, 13065 NULL, soc_feature_l2gre}, 13066 { bcmSwitchHashL2GreNetworkPortPayloadDisable1, TD2 | TD2P | TH, 13067 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_L2GRE_Bf, 13068 NULL, soc_feature_l2gre}, 13069 { bcmSwitchEcmpMacroFlowHashEnable, TD2 | TD2P | TH, 13070 RTAG7_HASH_SELr, USE_FLOW_SEL_ECMPf, 13071 NULL, 0}, 13072 { bcmSwitchMcQueueSchedMode, TD2 | TD2P, 13073 HSP_SCHED_PORT_CONFIGr, MC_GROUP_MODEf, 13074 NULL, 0}, 13075 #endif /* BCM_TRIDENT2_SUPPORT */ 13076 #if defined(BCM_KATANA2_SUPPORT) 13077 { bcmSwitchSubportPktTagToCpu, KT2, 13078 CPU_CONTROL_0r, DISCARD_LLTAG_PRESENT_TOCPUf, 13079 NULL, 0}, 13080 { bcmSwitchNonSubportPktTagToCpu, KT2, 13081 CPU_CONTROL_0r, DISCARD_LLTAG_NOT_PRESENT_TOCPUf, 13082 NULL, 0}, 13083 { bcmSwitchMimPayloadTpidEnable, KT2, 13084 RTAG7_HASH_CONTROL_2_64r, MIM_PAYLOAD_TPID_ENABLEf, 13085 NULL, soc_feature_mim}, 13086 { bcmSwitchHashMimUseTunnelHeader0, KT2, 13087 RTAG7_HASH_CONTROL_2_64r, DISABLE_HASH_MIM_INNER_L2_Af, 13088 NULL, soc_feature_mim}, 13089 { bcmSwitchHashMimUseTunnelHeader1, KT2, 13090 RTAG7_HASH_CONTROL_2_64r, DISABLE_HASH_MIM_INNER_L2_Bf, 13091 NULL, soc_feature_mim}, 13092 { bcmSwitchMacroFlowHashUseMSB, KT2, 13093 RTAG7_HASH_CONTROL_2_64r, MACRO_FLOW_HASH_BYTE_SELf, 13094 NULL, 0}, 13095 { bcmSwitchHashMPLSUseLabelStack, KT2, 13096 RTAG7_HASH_CONTROL_2_64r, USE_MPLS_STACK_FOR_HASHINGf, 13097 NULL, 0}, 13098 { bcmSwitchHashMPLSExcludeGAL, KT2, 13099 RTAG7_HASH_CONTROL_2_64r, EXCLUDE_RESERVED_LABELS_FROM_MPLS_HASHf, 13100 NULL, 0}, 13101 { bcmSwitchHashField0Ip6FlowLabel, KT2, 13102 RTAG7_HASH_CONTROL_2_64r, ENABLE_FLOW_LABEL_IPV6_Af, 13103 NULL, 0}, 13104 { bcmSwitchHashField1Ip6FlowLabel, KT2, 13105 RTAG7_HASH_CONTROL_2_64r, ENABLE_FLOW_LABEL_IPV6_Bf, 13106 NULL, 0}, 13107 #endif /* defined(BCM_KATANA2_SUPPORT) */ 13108 #if defined(BCM_TRIDENT_SUPPORT) 13109 { bcmSwitchHashField0Ip6FlowLabel, TD | TT | TT2 | TR3 | HX4 | TD2 | TD2P | TH, 13110 RTAG7_HASH_CONTROL_2r, ENABLE_FLOW_LABEL_IPV6_Af, 13111 NULL, 0}, 13112 { bcmSwitchHashField1Ip6FlowLabel, TD | TT | TT2 | TR3 | HX4 | TD2 | TD2P | TH, 13113 RTAG7_HASH_CONTROL_2r, ENABLE_FLOW_LABEL_IPV6_Bf, 13114 NULL, 0}, 13115 { bcmSwitchMacroFlowHashUseMSB, TD | TR3 | HX4 | TD2 | TD2P | TH, 13116 RTAG7_HASH_CONTROL_2r, MACRO_FLOW_HASH_BYTE_SELf, 13117 NULL, 0}, 13118 #endif 13119 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_KATANA_SUPPORT) 13120 { bcmSwitchHashHg2PktFieldsEnable, TD | TR3 | HX4 | KT | TD2 | TD2P, 13121 RTAG7_HASH_CONTROL_2r, TREAT_PPD2_AS_KNOWN_PPDf, 13122 NULL, 0}, 13123 { bcmSwitchHashHg2PktFieldsEnable, TH, 13124 ING_L2_TUNNEL_PARSE_CONTROLr , TREAT_PPD2_AS_KNOWN_PPDf, 13125 NULL, 0}, 13126 { bcmSwitchHashField0OverlayCntagRpidEnable, TD | TR3 | HX4 | KT | TD2 | TD2P | TH, 13127 RTAG7_HASH_CONTROL_2r, ENABLE_BIN_12_OVERLAY_Af, 13128 NULL, 0}, 13129 { bcmSwitchMimPayloadTpidEnable, TD | TR3 | HX4 | KT | TD2 | TD2P, 13130 RTAG7_HASH_CONTROL_2r, MIM_PAYLOAD_TPID_ENABLEf, 13131 NULL, soc_feature_mim}, 13132 { bcmSwitchHashMimUseTunnelHeader0, TD | TR3 | HX4 | KT | TD2 | TD2P | TH, 13133 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_MIM_INNER_L2_Af, 13134 NULL, soc_feature_mim}, 13135 { bcmSwitchHashMimUseTunnelHeader1, TD | TR3 | HX4 | KT | TD2 | TD2P | TH, 13136 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_MIM_INNER_L2_Bf, 13137 NULL, soc_feature_mim}, 13138 { bcmSwitchHashMimUseTunnelHeader0, TT | TT2, 13139 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_MIM_INNER_L2_Af, 13140 NULL, 0}, 13141 { bcmSwitchHashMimUseTunnelHeader1, TT | TT2, 13142 RTAG7_HASH_CONTROL_2r, DISABLE_HASH_MIM_INNER_L2_Bf, 13143 NULL, 0}, 13144 { bcmSwitchHashField1OverlayCntagRpidEnable, TD | TR3 | HX4 | KT | TD2 | TD2P | TH, 13145 RTAG7_HASH_CONTROL_2r, ENABLE_BIN_12_OVERLAY_Bf, 13146 NULL, 0}, 13147 { bcmSwitchHashMPLSUseLabelStack, TR3 | HX4 | KT, 13148 RTAG7_HASH_CONTROL_2r, USE_MPLS_STACK_FOR_HASHINGf, 13149 NULL, 0}, 13150 { bcmSwitchHashUseFlowSelTrunkUc, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13151 RTAG7_HASH_SELr, USE_FLOW_SEL_TRUNK_UCf, 13152 NULL, 0}, 13153 { bcmSwitchHashUseFlowSelEcmp, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13154 RTAG7_HASH_SELr, USE_FLOW_SEL_ECMPf, 13155 NULL, 0}, 13156 { bcmSwitchHashUseFlowSelMplsEcmp, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13157 RTAG7_HASH_SELr, USE_FLOW_SEL_MPLS_ECMPf, 13158 NULL, 0}, 13159 { bcmSwitchHashUseFlowSelTrunkNonUnicast, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13160 RTAG7_HASH_SELr, USE_FLOW_SEL_TRUNK_NONUCf, 13161 NULL, 0}, 13162 { bcmSwitchHashUseFlowSelHigigTrunkUnicast, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13163 RTAG7_HASH_SELr, USE_FLOW_SEL_HG_TRUNK_UCf, 13164 NULL, 0}, 13165 { bcmSwitchHashUseFlowSelHigigTrunkNonUnicast, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13166 RTAG7_HASH_SELr, USE_FLOW_SEL_HG_TRUNK_NONUCf, 13167 NULL, 0}, 13168 { bcmSwitchHashUseFlowSelHigigTrunkFailover, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13169 RTAG7_HASH_SELr, USE_FLOW_SEL_HG_TRUNK_FAILOVERf, 13170 NULL, 0}, 13171 { bcmSwitchHashUseFlowSelLbidUnicast, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13172 RTAG7_HASH_SELr, USE_FLOW_SEL_LBID_UCf, 13173 NULL, 0}, 13174 { bcmSwitchHashUseFlowSelLbidNonUnicast, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13175 RTAG7_HASH_SELr, USE_FLOW_SEL_LBID_NONUCf, 13176 NULL, 0}, 13177 { bcmSwitchHashUseFlowSelEntropy, TR3 | HX4 | KT2 | TD2 | TD2P | TH, 13178 RTAG7_HASH_SELr, USE_FLOW_SEL_ENTROPY_LABELf, 13179 NULL, 0}, 13180 #endif 13181 #if defined(BCM_TRIDENT_SUPPORT) 13182 { bcmSwitchV6L3SrcDstLocalLinkDropCancel, TD | TR3 | HX4 | TD2 | TD2P | TH, 13183 ING_MISC_CONFIG2r, IPV6_SIP_AND_DIP_LINK_LOCAL_DO_NOT_DROPf, 13184 NULL, 0}, 13185 #endif /* BCM_TRIDENT_SUPPORT */ 13186 13187 #if defined (BCM_TRIDENT2_SUPPORT) 13188 { bcmSwitchSTPDisabledFieldBypass, TD2 | TD2P | TH, 13189 ING_MISC_CONFIG2r, DISABLED_PORTS_FP_DISABLEf, 13190 NULL, 0}, 13191 { bcmSwitchHashUseFlowSelVpTrunk, TD2 | TD2P | TH, 13192 RTAG7_HASH_SELr, USE_FLOW_SEL_VPLAGf, 13193 NULL, 0}, 13194 { bcmSwitchHashUseFlowSelTrunkResilientHash, TD2 | TD2P, 13195 RTAG7_HASH_SELr, USE_FLOW_SEL_RH_LAGf, 13196 NULL, 0}, 13197 #endif /* BCM_TRIDENT2_SUPPORT */ 13198 #if defined (BCM_TRIDENT2PLUS_SUPPORT) 13199 { bcmSwitchHashUseFlowSelEcmpOverlay, TD2P, 13200 RTAG7_HASH_SELr, USE_FLOW_SEL_ECMP1f, 13201 NULL, 0}, 13202 #endif 13203 13204 #if defined(BCM_TOMAHAWK_SUPPORT) 13205 { bcmSwitchIngParseL2TunnelTermArp, TH, ING_L2_TUNNEL_PARSE_CONTROLr, 13206 PARSE_ARP_PAYLOADf, NULL, 0}, 13207 { bcmSwitchIngParseL2TunnelTermRarp, TH, ING_L2_TUNNEL_PARSE_CONTROLr, 13208 PARSE_RARP_PAYLOADf, NULL, 0}, 13209 #endif /* BCM_TOMAHAWK_SUPPORT */ 13210 13211 }; 13212 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 13213 13214 static uint8 *_mod_type_table[BCM_LOCAL_UNITS_MAX]; 13215 13216 STATIC int 13217 _bcm_switch_module_type_set(int unit, bcm_module_t mod, uint32 mod_type) 13218 { 13219 int modid_cnt; 13220 13221 if ((mod > SOC_MODID_MAX(unit)) || (mod_type != BCM_SWITCH_MODULE_XGS3)) { 13222 return BCM_E_PARAM; 13223 } else { 13224 if (NULL == _mod_type_table[unit]) { 13225 if (SOC_MODID_MAX(unit)) { 13226 modid_cnt = SOC_MODID_MAX(unit); 13227 } else { 13228 modid_cnt = 1; 13229 } 13230 _mod_type_table[unit] = (uint8 *)sal_alloc( 13231 (sizeof(uint8) * modid_cnt), "MOD TYPE"); 13232 if (NULL == _mod_type_table[unit]) { 13233 return BCM_E_MEMORY; 13234 } 13235 sal_memset(_mod_type_table[unit], BCM_SWITCH_MODULE_UNKNOWN, 13236 (sizeof(uint8) * modid_cnt)); 13237 } 13238 _mod_type_table[unit][mod] = mod_type; 13239 } 13240 return BCM_E_NONE; 13241 } 13242 13243 int 13244 _bcm_switch_module_type_get(int unit, bcm_module_t mod, uint32 *mod_type) 13245 { 13246 *mod_type = BCM_SWITCH_MODULE_UNKNOWN; 13247 if (mod > SOC_MODID_MAX(unit)) { 13248 return BCM_E_PARAM; 13249 } else { 13250 if (NULL != _mod_type_table[unit]) { 13251 *mod_type = _mod_type_table[unit][mod]; 13252 } 13253 } 13254 return BCM_E_NONE; 13255 } 13256 13257 13258 /* 13259 * Bulk clear of various hit bit tables 13260 */ 13261 STATIC int 13262 _bcm_esw_switch_hit_clear_set(int unit, bcm_switch_control_t type, int arg) 13263 { 13264 if (arg != 1) { 13265 return BCM_E_PARAM; 13266 } 13267 13268 switch (type) { 13269 case bcmSwitchL2HitClear: 13270 if (SOC_IS_FBX(unit)) { 13271 CLEARMEM(unit, L2_HITSA_ONLYm); 13272 CLEARMEM(unit, L2_HITDA_ONLYm); 13273 if (soc_feature(unit, soc_feature_esm_support)) { 13274 CLEARMEM(unit, EXT_SRC_HIT_BITS_L2m); 13275 CLEARMEM(unit, EXT_DST_HIT_BITS_L2m); 13276 } 13277 return BCM_E_NONE; 13278 } 13279 break; 13280 case bcmSwitchL2SrcHitClear: 13281 13282 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_HELIX4(unit)) { 13283 CLEAR_MEM_FIELD_ALL(unit, L2_ENTRY_1_HIT_ONLYm, HITSAf); 13284 CLEAR_MEM_FIELD_ALL(unit, L2_ENTRY_2_HIT_ONLYm, HITSAf); 13285 return BCM_E_NONE; 13286 } 13287 13288 if (SOC_IS_FBX(unit)) { 13289 CLEARMEM(unit, L2_HITSA_ONLYm); 13290 if (soc_feature(unit, soc_feature_esm_support)) { 13291 CLEARMEM(unit, EXT_SRC_HIT_BITS_L2m); 13292 } 13293 return BCM_E_NONE; 13294 } 13295 break; 13296 case bcmSwitchL2DstHitClear: 13297 13298 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_HELIX4(unit)) { 13299 CLEAR_MEM_FIELD_ALL(unit, L2_ENTRY_1_HIT_ONLYm, HITDAf); 13300 CLEAR_MEM_FIELD_ALL(unit, L2_ENTRY_2_HIT_ONLYm, HITDAf); 13301 return BCM_E_NONE; 13302 } 13303 13304 if (SOC_IS_FBX(unit)) { 13305 CLEARMEM(unit, L2_HITDA_ONLYm); 13306 if (soc_feature(unit, soc_feature_esm_support)) { 13307 CLEARMEM(unit, EXT_DST_HIT_BITS_L2m); 13308 } 13309 return BCM_E_NONE; 13310 } 13311 break; 13312 case bcmSwitchL3HostHitClear: 13313 if (!soc_feature(unit, soc_feature_l3) || 13314 soc_feature(unit, soc_feature_fp_based_routing)) { 13315 break; 13316 } 13317 if (SOC_IS_FBX(unit)) { 13318 CLEARMEM(unit, L3_ENTRY_HIT_ONLYm); 13319 return BCM_E_NONE; 13320 } 13321 break; 13322 case bcmSwitchL3RouteHitClear: 13323 if (!soc_feature(unit, soc_feature_l3) || 13324 soc_feature(unit, soc_feature_fp_based_routing)) { 13325 break; 13326 } 13327 if (SOC_IS_FBX(unit)) { 13328 CLEARMEM(unit, L3_DEFIP_HIT_ONLYm); 13329 CLEARMEM(unit, L3_DEFIP_128_HIT_ONLYm); 13330 if (soc_feature(unit, soc_feature_esm_support)) { 13331 CLEARMEM(unit, EXT_SRC_HIT_BITS_IPV4m); 13332 CLEARMEM(unit, EXT_SRC_HIT_BITS_IPV6_64m); 13333 CLEARMEM(unit, EXT_SRC_HIT_BITS_IPV6_128m); 13334 CLEARMEM(unit, EXT_DST_HIT_BITS_IPV4m); 13335 CLEARMEM(unit, EXT_DST_HIT_BITS_IPV6_64m); 13336 CLEARMEM(unit, EXT_DST_HIT_BITS_IPV6_128m); 13337 } 13338 return BCM_E_NONE; 13339 } 13340 break; 13341 default: 13342 break; 13343 } 13344 13345 return BCM_E_UNAVAIL; 13346 } 13347 13348 #undef CLEARMEM 13349 13350 /* 13351 * Return an error if a hit clear is not supportable on this device 13352 */ 13353 STATIC int 13354 _bcm_esw_switch_hit_clear_get(int unit, bcm_switch_control_t type, int *arg) 13355 { 13356 int rv; 13357 13358 rv = BCM_E_UNAVAIL; 13359 13360 switch (type) { 13361 case bcmSwitchL2HitClear: 13362 if (SOC_IS_FBX(unit)) { 13363 rv = BCM_E_NONE; 13364 break; 13365 } 13366 break; 13367 case bcmSwitchL2SrcHitClear: 13368 if (SOC_IS_FBX(unit)) { 13369 rv = BCM_E_NONE; 13370 break; 13371 } 13372 break; 13373 case bcmSwitchL2DstHitClear: 13374 if (SOC_IS_FBX(unit)) { 13375 rv = BCM_E_NONE; 13376 break; 13377 } 13378 break; 13379 case bcmSwitchL3HostHitClear: 13380 if (!soc_feature(unit, soc_feature_l3) || 13381 soc_feature(unit, soc_feature_fp_based_routing)) { 13382 break; 13383 } 13384 if (SOC_IS_FBX(unit)) { 13385 rv = BCM_E_NONE; 13386 break; 13387 } 13388 break; 13389 case bcmSwitchL3RouteHitClear: 13390 if (!soc_feature(unit, soc_feature_l3) || 13391 soc_feature(unit, soc_feature_fp_based_routing)) { 13392 break; 13393 } 13394 if (SOC_IS_FBX(unit)) { 13395 rv = BCM_E_NONE; 13396 break; 13397 } 13398 break; 13399 default: 13400 break; 13401 } 13402 if (rv == BCM_E_NONE && arg != NULL) { 13403 *arg = 0; 13404 } 13405 return rv; 13406 } 13407 13408 #if defined(BCM_HAWKEYE_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) \ 13409 || defined(BCM_APOLLO_SUPPORT) 13410 /* 13411 * Function: 13412 * _bcm_switch_class_pkt_prio_set 13413 * Description: 13414 * Helper function to program packet priority per traffic class. 13415 * Parameters: 13416 * unit - Device unit number 13417 * type - The desired configuration parameter to modify 13418 * arg - The value with which to set the parameter 13419 * Returns: 13420 * BCM_E_xxx 13421 */ 13422 STATIC int 13423 _bcm_switch_class_pkt_prio_set(int unit, 13424 bcm_switch_control_t type, 13425 int arg) 13426 { 13427 #if defined(BCM_HAWKEYE_SUPPORT) 13428 if (SOC_IS_HAWKEYE(unit)) { 13429 soc_reg_t reg[2]; 13430 soc_field_t field; 13431 int i; 13432 13433 reg[0] = reg[1] = INVALIDr; 13434 field = INVALIDf; 13435 13436 switch (type) { 13437 case bcmSwitchTimeSyncClassAPktPrio: 13438 reg[0] = ING_EAV_CLASSr; 13439 reg[1] = EGR_EAV_CLASSr; 13440 field = CLASS_Af; 13441 break; 13442 case bcmSwitchTimeSyncClassBPktPrio: 13443 reg[0] = ING_EAV_CLASSr; 13444 reg[1] = EGR_EAV_CLASSr; 13445 field = CLASS_Bf; 13446 break; 13447 case bcmSwitchTimeSyncClassAExeptionPktPrio: 13448 reg[0] = EGR_EAV_CLASSr; 13449 field = REMAP_CLASS_Af; 13450 break; 13451 case bcmSwitchTimeSyncClassBExeptionPktPrio: 13452 reg[0] = EGR_EAV_CLASSr; 13453 field = REMAP_CLASS_Bf; 13454 break; 13455 default: 13456 return BCM_E_PARAM; 13457 } 13458 13459 for (i = 0; i < 2; i++) { 13460 if (INVALIDr != reg[i]) { 13461 BCM_IF_ERROR_RETURN( 13462 soc_reg_field32_modify(unit, reg[i], REG_PORT_ANY, field, arg)); 13463 } 13464 } 13465 13466 return BCM_E_NONE; 13467 } 13468 #endif /* BCM_HAWKEYE_SUPPORT */ 13469 return BCM_E_UNAVAIL; 13470 } 13471 13472 /* 13473 * Function: 13474 * _bcm_switch_class_pkt_prio_get 13475 * Description: 13476 * Helper function to read packet priority per traffic class. 13477 * Parameters: 13478 * unit - Device unit number 13479 * type - The desired configuration parameter to read 13480 * arg - The value with which is programmed 13481 * Returns: 13482 * BCM_E_xxx 13483 */ 13484 STATIC int 13485 _bcm_switch_class_pkt_prio_get(int unit, 13486 bcm_switch_control_t type, 13487 int *arg) 13488 { 13489 #if defined(BCM_HAWKEYE_SUPPORT) 13490 if (SOC_IS_HAWKEYE(unit)) { 13491 soc_reg_t reg; 13492 soc_field_t field; 13493 uint32 rval; 13494 13495 switch (type) { 13496 case bcmSwitchTimeSyncClassAPktPrio: 13497 reg = ING_EAV_CLASSr; 13498 field = CLASS_Af; 13499 break; 13500 case bcmSwitchTimeSyncClassBPktPrio: 13501 reg = ING_EAV_CLASSr; 13502 field = CLASS_Bf; 13503 break; 13504 case bcmSwitchTimeSyncClassAExeptionPktPrio: 13505 reg = EGR_EAV_CLASSr; 13506 field = REMAP_CLASS_Af; 13507 break; 13508 case bcmSwitchTimeSyncClassBExeptionPktPrio: 13509 reg = EGR_EAV_CLASSr; 13510 field = REMAP_CLASS_Bf; 13511 break; 13512 default: 13513 return BCM_E_PARAM; 13514 } 13515 13516 BCM_IF_ERROR_RETURN( 13517 soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 13518 *arg = soc_reg_field_get(unit, reg, rval, field); 13519 13520 return BCM_E_NONE; 13521 } 13522 #endif /* BCM_HAWKEYE_SUPPORT */ 13523 return BCM_E_UNAVAIL; 13524 } 13525 13526 #endif /*BCM_HAWKEYE_SUPPORT || BCM_TRIUMPH2_SUPPORT || BCM_APOLLO_SUPPORT */ 13527 13528 #if (defined(BCM_RCPU_SUPPORT) || defined(BCM_OOB_RCPU_SUPPORT)) && \ 13529 defined(BCM_XGS3_SWITCH_SUPPORT) 13530 /* 13531 * Function: 13532 * _bcm_rcpu_switch_regall_idx_set 13533 * Description: 13534 * Helper function to set register to all ones if arg is non zero 13535 * and to all zeros otherwise. 13536 * Parameters: 13537 * unit - Device unit number 13538 * reg - The desired register to program 13539 * idx - The register index 13540 * arg - The value with which decission is made 13541 * Returns: 13542 * BCM_E_xxx 13543 */ 13544 STATIC int 13545 _bcm_rcpu_switch_regall_idx_set(int unit, 13546 soc_reg_t reg, 13547 int idx, 13548 soc_field_t field, 13549 int arg) 13550 { 13551 uint32 raddr, rval, value, width; 13552 13553 rval = 0; 13554 if (arg) { 13555 width = soc_reg_field_length(unit, reg, field); 13556 if (32 == width) { 13557 value = 0xffffffff; 13558 } else { 13559 value = (1 << width) - 1; 13560 } 13561 soc_reg_field_set(unit, reg, &rval, field, value); 13562 } 13563 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, idx); 13564 return soc_pci_write(unit, raddr, rval); 13565 } 13566 /* 13567 * Function: 13568 * _bcm_rcpu_switch_regall_set 13569 * Description: 13570 * Helper function to set register to all ones if arg is non zero 13571 * and to all zeros otherwise. 13572 * Parameters: 13573 * unit - Device unit number 13574 * reg - The desired register to program 13575 * arg - The value with which decission is made 13576 * Returns: 13577 * BCM_E_xxx 13578 */ 13579 STATIC int 13580 _bcm_rcpu_switch_regall_set(int unit, soc_reg_t reg, soc_field_t field, int arg) 13581 { 13582 return _bcm_rcpu_switch_regall_idx_set(unit, reg, 0, field, arg); 13583 } 13584 13585 /* 13586 * Function: 13587 * _bcm_rcpu_switch_regall_get 13588 * Description: 13589 * Helper function to return arg = 1 if register is set to all ones 13590 * and to zero otherwise. 13591 * Parameters: 13592 * unit - Device unit number 13593 * reg - The desired register to read 13594 * arg - The value returnrd 13595 * Returns: 13596 * BCM_E_xxx 13597 */ 13598 STATIC int 13599 _bcm_rcpu_switch_regall_idx_get(int unit, soc_reg_t reg, int idx, int *arg) 13600 { 13601 uint32 raddr, rval; 13602 13603 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, idx); 13604 /* coverity[result_independent_of_operands] */ 13605 BCM_IF_ERROR_RETURN( 13606 soc_pci_getreg(unit, raddr, &rval)); 13607 13608 *arg = (!rval) ? 0 : 1; 13609 13610 return BCM_E_NONE; 13611 } 13612 13613 STATIC int 13614 _bcm_rcpu_switch_regall_get(int unit, soc_reg_t reg, int *arg) 13615 { 13616 return _bcm_rcpu_switch_regall_idx_get(unit, reg, 0, arg); 13617 } 13618 13619 /* 13620 * Function: 13621 * _bcm_rcpu_switch_vlan_tpid_sig_set 13622 * Description: 13623 * Helper function to set VLAN, TPID ot Signature for RCPU 13624 * Parameters: 13625 * unit - Device unit number 13626 * type - The desired configuration parameter to modify 13627 * arg - The value to set 13628 * Returns: 13629 * BCM_E_xxx 13630 */ 13631 STATIC int 13632 _bcm_rcpu_switch_vlan_tpid_sig_set(int unit, 13633 bcm_switch_control_t type, 13634 int arg) 13635 { 13636 soc_reg_t reg = INVALIDr; 13637 soc_field_t field = INVALIDf; 13638 uint32 value, raddr, rval; 13639 13640 if (!soc_feature(unit, soc_feature_rcpu_1)) { 13641 return BCM_E_UNAVAIL; 13642 } 13643 13644 switch (type) { 13645 case bcmSwitchRemoteCpuVlan: 13646 reg = CMIC_PKT_VLANr; 13647 field = VLAN_IDf; 13648 value = (arg & 0xffff); 13649 break; 13650 case bcmSwitchRemoteCpuTpid: 13651 reg = CMIC_PKT_VLANr; 13652 field = TPIDf; 13653 value = (arg & 0xffff); 13654 break; 13655 case bcmSwitchRemoteCpuSignature: 13656 reg = CMIC_PKT_ETHER_SIGr; 13657 field = SIGNATUREf; 13658 value = (arg & 0xffff); 13659 break; 13660 case bcmSwitchRemoteCpuEthertype: 13661 reg = CMIC_PKT_ETHER_SIGr; 13662 field = ETHERTYPEf; 13663 value = (arg & 0xffff); 13664 break; 13665 default: 13666 return BCM_E_PARAM; 13667 } 13668 13669 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 13670 /* coverity[result_independent_of_operands] */ 13671 BCM_IF_ERROR_RETURN( 13672 soc_pci_getreg(unit, raddr, &rval)); 13673 soc_reg_field_set(unit, reg, &rval, field, value); 13674 13675 return soc_pci_write(unit, raddr, rval); 13676 } 13677 13678 /* 13679 * Function: 13680 * _bcm_rcpu_switch_vlan_tpid_sig_get 13681 * Description: 13682 * Helper function to get VLAN, TPID ot Signature for RCPU 13683 * Parameters: 13684 * unit - Device unit number 13685 * type - The desired configuration parameter to get 13686 * arg - The value returned 13687 * Returns: 13688 * BCM_E_xxx 13689 */ 13690 STATIC int 13691 _bcm_rcpu_switch_vlan_tpid_sig_get(int unit, 13692 bcm_switch_control_t type, 13693 int *arg) 13694 { 13695 soc_reg_t reg; 13696 soc_field_t field; 13697 uint32 raddr, rval; 13698 13699 13700 if (!soc_feature(unit, soc_feature_rcpu_1)) { 13701 return BCM_E_UNAVAIL; 13702 } 13703 13704 switch (type) { 13705 case bcmSwitchRemoteCpuVlan: 13706 reg = CMIC_PKT_VLANr; 13707 field = VLAN_IDf; 13708 break; 13709 case bcmSwitchRemoteCpuTpid: 13710 reg = CMIC_PKT_VLANr; 13711 field = TPIDf; 13712 break; 13713 case bcmSwitchRemoteCpuSignature: 13714 reg = CMIC_PKT_ETHER_SIGr; 13715 field = SIGNATUREf; 13716 break; 13717 case bcmSwitchRemoteCpuEthertype: 13718 reg = CMIC_PKT_ETHER_SIGr; 13719 field = ETHERTYPEf; 13720 break; 13721 default: 13722 return BCM_E_PARAM; 13723 } 13724 13725 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 13726 /* coverity[result_independent_of_operands] */ 13727 BCM_IF_ERROR_RETURN( 13728 soc_pci_getreg(unit, raddr, &rval)); 13729 13730 *arg = soc_reg_field_get(unit, reg, rval, field); 13731 13732 return BCM_E_NONE; 13733 } 13734 13735 13736 /* 13737 * Function: 13738 * _bcm_rcpu_switch_mac_lo_set 13739 * Description: 13740 * Set the low 24 bits of MAC address field for RCPU MAC registers 13741 * Parameters: 13742 * unit - StrataSwitch PCI device unit number (driver internal). 13743 * port - port number. 13744 * type - The required switch control type to set the mac for 13745 * mac_lo - MAC address 13746 * Returns: 13747 * BCM_E_xxxx 13748 */ 13749 13750 STATIC int 13751 _bcm_rcpu_switch_mac_lo_set(int unit, 13752 bcm_switch_control_t type, 13753 uint32 mac_lo) 13754 { 13755 uint32 regval, fieldval; 13756 soc_reg_t reg = INVALIDr ; 13757 soc_field_t f_lo = INVALIDf; 13758 13759 13760 /* Given control type select register. */ 13761 switch (type) { 13762 case bcmSwitchRemoteCpuLocalMacNonOui: 13763 reg = CMIC_PKT_LMAC0_LOr; 13764 f_lo = MAC0_LOf; 13765 break; 13766 case bcmSwitchRemoteCpuDestMacNonOui: 13767 reg = CMIC_PKT_RMACr; 13768 f_lo = MAC_LOf; 13769 break; 13770 default: 13771 return BCM_E_PARAM; 13772 } 13773 /* coverity[result_independent_of_operands] */ 13774 SOC_IF_ERROR_RETURN( 13775 soc_pci_getreg(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), 13776 ®val)); 13777 13778 fieldval = soc_reg_field_get(unit, reg, regval, f_lo); 13779 fieldval &= 0xff000000; 13780 fieldval |= ((mac_lo << 8) >> 8); 13781 soc_reg_field_set(unit, reg, ®val, f_lo, fieldval); 13782 13783 return soc_pci_write(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), 13784 regval); 13785 } 13786 13787 /* 13788 * Function: 13789 * _bcm_rcpu_switch_mac_hi_set 13790 * Description: 13791 * Set the upper 24 bits of MAC address field for RCPU registers 13792 * Parameters: 13793 * unit - StrataSwitch PCI device unit number (driver internal). 13794 * port - port number. 13795 * type - The required switch control type to set upper MAC for 13796 * mac_hi - MAC address 13797 * Returns: 13798 * BCM_E_xxxx 13799 */ 13800 13801 STATIC int 13802 _bcm_rcpu_switch_mac_hi_set(int unit, 13803 bcm_switch_control_t type, 13804 uint32 mac_hi) 13805 { 13806 soc_reg_t reg1, reg2; 13807 soc_field_t f_lo, f_hi; 13808 uint32 fieldval, regval1, regval2, raddr1, raddr2; 13809 13810 reg1 = reg2 = INVALIDr; 13811 13812 /* Given control type select register. */ 13813 switch (type) { 13814 case bcmSwitchRemoteCpuLocalMacOui: 13815 reg1 = CMIC_PKT_LMAC0_LOr; 13816 reg2 = CMIC_PKT_LMAC0_HIr; 13817 f_lo = MAC0_LOf; 13818 f_hi = MAC0_HIf; 13819 break; 13820 case bcmSwitchRemoteCpuDestMacOui: 13821 reg1 = CMIC_PKT_RMACr; 13822 reg2 = CMIC_PKT_RMAC_HIr; 13823 f_lo = MAC_LOf; 13824 f_hi = MAC_HIf; 13825 break; 13826 default: 13827 return BCM_E_PARAM; 13828 } 13829 13830 regval1 = regval2 = 0; 13831 13832 raddr1 = soc_reg_addr(unit, reg1, REG_PORT_ANY, 0); 13833 raddr2 = soc_reg_addr(unit, reg2, REG_PORT_ANY, 0); 13834 /* coverity[result_independent_of_operands] */ 13835 BCM_IF_ERROR_RETURN( 13836 soc_pci_getreg(unit, raddr1, ®val1)); 13837 /* coverity[result_independent_of_operands] */ 13838 BCM_IF_ERROR_RETURN( 13839 soc_pci_getreg(unit, raddr2, ®val2)); 13840 13841 fieldval = (mac_hi << 24); 13842 soc_reg_field_set(unit, reg1, ®val1, f_lo, fieldval); 13843 fieldval = (mac_hi >> 8) & 0xffff; 13844 soc_reg_field_set(unit, reg2, ®val2, f_hi, fieldval); 13845 /* coverity[result_independent_of_operands] */ 13846 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr1, regval1)); 13847 /* coverity[result_independent_of_operands] */ 13848 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr2, regval2)); 13849 13850 return BCM_E_NONE; 13851 } 13852 13853 13854 /* 13855 * Function: 13856 * _bcm_rcpu_switch_mac_lo_get 13857 * Description: 13858 * Get the lower 24 bits of MAC address field for RCPU MAC registers 13859 * Parameters: 13860 * unit - StrataSwitch PCI device unit number (driver internal). 13861 * port - port number. 13862 * type - The required switch control type to get MAC for 13863 * arg - arg to get the lower MAC address 13864 * Returns: 13865 * BCM_E_xxxx 13866 */ 13867 13868 STATIC int 13869 _bcm_rcpu_switch_mac_lo_get(int unit, 13870 bcm_switch_control_t type, 13871 int *arg) 13872 { 13873 soc_reg_t reg = INVALIDr ; 13874 soc_field_t f_lo = INVALIDf; 13875 uint32 regval, mac; 13876 13877 /* Given control type select register. */ 13878 switch (type) { 13879 case bcmSwitchRemoteCpuLocalMacNonOui: 13880 reg = CMIC_PKT_LMAC0_LOr; 13881 f_lo = MAC0_LOf; 13882 break; 13883 case bcmSwitchRemoteCpuDestMacNonOui: 13884 reg = CMIC_PKT_RMACr; 13885 f_lo = MAC_LOf; 13886 break; 13887 default: 13888 return BCM_E_PARAM; 13889 } 13890 /* coverity[result_independent_of_operands] */ 13891 SOC_IF_ERROR_RETURN( 13892 soc_pci_getreg(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), 13893 ®val)); 13894 mac = soc_reg_field_get(unit, reg, regval, f_lo); 13895 13896 *arg = (mac << 8) >> 8; 13897 13898 return BCM_E_NONE; 13899 } 13900 13901 /* 13902 * Function: 13903 * _bcm_rcpu_switch_mac_hi_get 13904 * Description: 13905 * Get the upper 24 bits of MAC address field for RCPU MAC registers 13906 * Parameters: 13907 * unit - StrataSwitch PCI device unit number (driver internal). 13908 * port - port number. 13909 * type - The required switch control type to get MAC for 13910 * arg - arg to get the upper MAC address 13911 * Returns: 13912 * BCM_E_xxxx 13913 */ 13914 13915 STATIC int 13916 _bcm_rcpu_switch_mac_hi_get(int unit, 13917 bcm_switch_control_t type, 13918 int *arg) 13919 { 13920 soc_reg_t reg1, reg2; 13921 soc_field_t f_lo, f_hi; 13922 uint32 mac, regval1, regval2; 13923 13924 reg1 = reg2 = INVALIDr; 13925 13926 /* Given control type select register. */ 13927 switch (type) { 13928 case bcmSwitchRemoteCpuLocalMacOui: 13929 reg1 = CMIC_PKT_LMAC0_LOr; 13930 reg2 = CMIC_PKT_LMAC0_HIr; 13931 f_lo = MAC0_LOf; 13932 f_hi = MAC0_HIf; 13933 break; 13934 case bcmSwitchRemoteCpuDestMacOui: 13935 reg1 = CMIC_PKT_RMACr; 13936 reg2 = CMIC_PKT_RMAC_HIr; 13937 f_lo = MAC_LOf; 13938 f_hi = MAC_HIf; 13939 break; 13940 default: 13941 return BCM_E_PARAM; 13942 } 13943 /* coverity[result_independent_of_operands] */ 13944 SOC_IF_ERROR_RETURN( 13945 soc_pci_getreg(unit, soc_reg_addr(unit, reg1, REG_PORT_ANY, 0), 13946 ®val1)); 13947 mac = (soc_reg_field_get(unit, reg1, regval1, f_lo) >> 24); 13948 /* coverity[result_independent_of_operands] */ 13949 SOC_IF_ERROR_RETURN( 13950 soc_pci_getreg(unit, soc_reg_addr(unit, reg2, REG_PORT_ANY, 0), 13951 ®val2)); 13952 13953 mac |= (soc_reg_field_get(unit, reg2, regval2, f_hi) << 8); 13954 13955 *arg = (int)mac; 13956 13957 return BCM_E_NONE; 13958 } 13959 13960 13961 /* 13962 * Function: 13963 * _bcm_rcpu_pipe_bypass_header_set 13964 * Description: 13965 * Prepare and program the SOBMH header for RCPU usage 13966 * Parameters: 13967 * unit - StrataSwitch PCI device unit number (driver internal). 13968 * port - port number. 13969 * type - The required switch control type to get MAC for 13970 * arg - port number to specify in the SOBMH 13971 * Returns: 13972 * BCM_E_xxxx 13973 */ 13974 STATIC int 13975 _bcm_rcpu_pipe_bypass_header_set(int unit, 13976 bcm_switch_control_t type, 13977 int arg) 13978 { 13979 uint32 pbh[3]; /* 3 words SOBMH header to program */ 13980 soc_pbsmh_hdr_t *p_pbh = (soc_pbsmh_hdr_t *)pbh; 13981 bcm_port_t port; 13982 bcm_module_t modid; 13983 uint32 raddr; 13984 int qnum; 13985 13986 if (BCM_GPORT_IS_SET(arg)) { 13987 bcm_trunk_t tgid; 13988 int id; 13989 13990 BCM_IF_ERROR_RETURN( 13991 _bcm_esw_gport_resolve(unit, arg, &modid, &port, &tgid, &id)); 13992 if ((BCM_TRUNK_INVALID != tgid) || (-1 != id) ) { 13993 return BCM_E_PORT; 13994 } 13995 } else { 13996 port = arg; 13997 modid = SOC_DEFAULT_DMA_SRCMOD_GET(unit); 13998 } 13999 14000 if (!SOC_PORT_VALID(unit, port)) { 14001 return BCM_E_PORT; 14002 } 14003 14004 /* Setup SOBMH header according to supplied argument */ 14005 if (SOC_DCB_TYPE(unit) == 23 || SOC_DCB_TYPE(unit) == 26 || 14006 SOC_DCB_TYPE(unit) == 29 || SOC_DCB_TYPE(unit) == 31 || 14007 SOC_DCB_TYPE(unit) == 30 || SOC_DCB_TYPE(unit) == 34 || 14008 SOC_DCB_TYPE(unit) == 37) { 14009 #ifdef BCM_KATANA2_SUPPORT 14010 if (SOC_DCB_TYPE(unit) == 29) { 14011 qnum = SOC_INFO(unit).port_cosq_base[port]; 14012 } else 14013 #endif 14014 { 14015 qnum = SOC_INFO(unit).port_uc_cosq_base[port]; 14016 } 14017 #ifdef BCM_TRIDENT2_SUPPORT 14018 if (SOC_DCB_TYPE(unit) == 26) { 14019 qnum = soc_td2_logical_qnum_hw_qnum(unit, port, qnum, 1); 14020 } 14021 #endif /* BCM_TRIDENT2_SUPPORT */ 14022 PBS_MH_V7_W0_START_SET(pbh); 14023 #ifdef BCM_KATANA2_SUPPORT 14024 if (SOC_DCB_TYPE(unit) == 29) { 14025 PBS_MH_V8_W1_DPORT_IPRI_SET(pbh, port, 0); 14026 PBS_MH_V8_W2_SMOD_COS_QNUM_SET(pbh, modid, 1, 0, qnum); 14027 } else 14028 #endif 14029 { 14030 PBS_MH_V7_W1_DPORT_QNUM_SET(pbh, port, qnum); 14031 PBS_MH_V7_W2_SMOD_COS_QNUM_SET(pbh, modid, 1, 0, qnum, 0); 14032 } 14033 } else if ((SOC_DCB_TYPE(unit) == 32) || (SOC_DCB_TYPE(unit) == 38)) { 14034 /* 32 for TH and 38 for TH3 */ 14035 PBS_MH_V9_W0_START_SET(pbh); 14036 PBS_MH_V9_W1_DPORT_SET(pbh, port); 14037 PBS_MH_V9_W2_SMOD_COS_SET(pbh, modid, 1, 0); 14038 } else if (SOC_DCB_TYPE(unit) == 36) { 14039 /* TD3 */ 14040 PBS_MH_V11_W0_START_SET(pbh); 14041 PBS_MH_V11_W1_DPORT_SET(pbh, port); 14042 PBS_MH_V11_W2_SMOD_COS_SET(pbh, modid, 1, 0); 14043 } else if (SOC_DCB_TYPE(unit) == 33 || SOC_DCB_TYPE(unit) == 35) { 14044 qnum = SOC_INFO(unit).port_uc_cosq_base[port]; 14045 #ifdef BCM_MONTEREY_SUPPORT 14046 if (SOC_IS_MONTEREY(unit)) { 14047 qnum = soc_monterey_logical_qnum_hw_qnum(unit, port, qnum, 1); 14048 } else 14049 #endif /* BCM_MONTEREY_SUPPORT */ 14050 #ifdef BCM_APACHE_SUPPORT 14051 if (SOC_IS_APACHE(unit)) { 14052 qnum = soc_apache_logical_qnum_hw_qnum(unit, port, qnum, 1); 14053 } else 14054 #endif /* BCM_APACHE_SUPPORT */ 14055 #ifdef BCM_TRIDENT2_SUPPORT 14056 { 14057 qnum = soc_td2_logical_qnum_hw_qnum(unit, port, qnum, 1); 14058 } 14059 #endif /* BCM_TRIDENT2_SUPPORT */ 14060 soc_pbsmh_field_set(unit, p_pbh, PBSMH_start, SOC_PBSMH_START_INTERNAL); 14061 soc_pbsmh_field_set(unit, p_pbh, PBSMH_header_type, SOC_SOBMH_FROM_CPU); 14062 soc_pbsmh_field_set(unit, p_pbh, PBSMH_dst_port, port); 14063 soc_pbsmh_field_set(unit, p_pbh, PBSMH_unicast, 1 ); 14064 soc_pbsmh_field_set(unit, p_pbh, PBSMH_dst_port, port); 14065 soc_pbsmh_field_set(unit, p_pbh, PBSMH_src_mod, modid); 14066 soc_pbsmh_field_set(unit, p_pbh, PBSMH_cos, 0); 14067 soc_pbsmh_field_set(unit, p_pbh, PBSMH_queue_num, qnum); 14068 soc_pbsmh_field_set(unit, p_pbh, PBSMH_pri, 0); 14069 } else { 14070 PBS_MH_W0_START_SET(pbh); 14071 PBS_MH_W1_RSVD_SET(pbh); 14072 if ((SOC_DCB_TYPE(unit) == 11) || (SOC_DCB_TYPE(unit) == 12) || 14073 (SOC_DCB_TYPE(unit) == 15) || (SOC_DCB_TYPE(unit) == 17) || 14074 (SOC_DCB_TYPE(unit) == 18)) { 14075 PBS_MH_V2_W2_SMOD_DPORT_COS_SET(pbh, modid, port, 0, 0, 0); 14076 } else if ((SOC_DCB_TYPE(unit) == 14) || 14077 (SOC_DCB_TYPE(unit) == 19) || 14078 (SOC_DCB_TYPE(unit) == 20)) { 14079 14080 PBS_MH_V3_W2_SMOD_DPORT_COS_SET(pbh, modid, port,0, 0, 0); 14081 } else if (SOC_DCB_TYPE(unit) == 16) { 14082 PBS_MH_V4_W2_SMOD_DPORT_COS_SET(pbh, modid, port,0, 0, 0); 14083 } else if (SOC_DCB_TYPE(unit) == 21) { 14084 PBS_MH_V5_W1_SMOD_SET(pbh, modid, 1, 0, 0); 14085 PBS_MH_V5_W2_DPORT_COS_SET(pbh, port, 0, 0); 14086 } else if (SOC_DCB_TYPE(unit) == 24) { 14087 PBS_MH_V5_W1_SMOD_SET(pbh, modid, 1, 0, 0); 14088 PBS_MH_V6_W2_DPORT_COS_QNUM_SET(pbh, port, 0, 14089 (SOC_INFO(unit).port_cosq_base[port]), 0); 14090 } else { 14091 PBS_MH_V1_W2_SMOD_DPORT_COS_SET(pbh, modid, port, 0, 0, 0); 14092 } 14093 } 14094 14095 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 14096 /* coverity[result_independent_of_operands] */ 14097 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, pbh[0])); 14098 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 14099 /* coverity[result_independent_of_operands] */ 14100 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, pbh[1])); 14101 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 14102 /* coverity[result_independent_of_operands] */ 14103 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, pbh[2])); 14104 14105 return BCM_E_NONE; 14106 } 14107 14108 /* 14109 * Function: 14110 * _bcm_rcpu_pipe_bypass_header_get 14111 * Description: 14112 * Get the SOBMH header for RCPU usage and retrieve the port numebr 14113 * Parameters: 14114 * unit - StrataSwitch PCI device unit number (driver internal). 14115 * port - port number. 14116 * type - The required switch control type to get MAC for 14117 * arg - port number in the SOBMH header 14118 * Returns: 14119 * BCM_E_xxxx 14120 */ 14121 STATIC int 14122 _bcm_rcpu_pipe_bypass_header_get(int unit, 14123 bcm_switch_control_t type, 14124 int *arg) 14125 { 14126 soc_pbsmh_hdr_t *pbh; 14127 uint32 hw_buff[3]; /* 3 words SOBMH header */ 14128 uint32 raddr; 14129 int isGport; 14130 14131 if (NULL == arg) { 14132 return BCM_E_PARAM; 14133 } 14134 14135 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 14136 /* coverity[result_independent_of_operands] */ 14137 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hw_buff[0]))); 14138 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 14139 /* coverity[result_independent_of_operands] */ 14140 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hw_buff[1]))); 14141 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 14142 /* coverity[result_independent_of_operands] */ 14143 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hw_buff[2]))); 14144 14145 pbh = (soc_pbsmh_hdr_t *)hw_buff; 14146 14147 BCM_IF_ERROR_RETURN( 14148 bcm_esw_switch_control_get(unit, bcmSwitchUseGport, &isGport)); 14149 14150 if (isGport) { 14151 _bcm_gport_dest_t gport_st; 14152 14153 gport_st.gport_type = BCM_GPORT_TYPE_MODPORT; 14154 gport_st.modid = soc_pbsmh_field_get(unit, pbh, PBSMH_src_mod); 14155 gport_st.port = soc_pbsmh_field_get(unit, pbh, PBSMH_dst_port); 14156 BCM_IF_ERROR_RETURN( 14157 _bcm_esw_gport_construct(unit, &gport_st, arg)); 14158 } else { 14159 *arg = soc_pbsmh_field_get(unit, pbh, PBSMH_dst_port); 14160 } 14161 14162 return BCM_E_NONE; 14163 } 14164 14165 /* 14166 * Function: 14167 * _bcm_rcpu_higig_header_set 14168 * Description: 14169 * Prepare and program the HIGIG header for RCPU usage 14170 * Parameters: 14171 * unit - StrataSwitch PCI device unit number (driver internal). 14172 * arg - port number to specify in the SOBMH 14173 * Returns: 14174 * BCM_E_xxxx 14175 */ 14176 STATIC int 14177 _bcm_rcpu_higig_header_set(int unit, int arg) 14178 { 14179 #if defined(BCM_HIGIG2_SUPPORT) 14180 uint32 hghdr[4]; /* 4 words HIGIG2 header to program */ 14181 soc_higig2_hdr_t *xgh = (soc_higig2_hdr_t *)hghdr; 14182 bcm_port_t port; 14183 bcm_module_t modid; 14184 uint32 raddr, rval, vlan_val; 14185 14186 if (BCM_GPORT_IS_SET(arg)) { 14187 bcm_trunk_t tgid; 14188 int id; 14189 14190 BCM_IF_ERROR_RETURN( 14191 _bcm_esw_gport_resolve(unit, arg, &modid, &port, &tgid, &id)); 14192 if ((BCM_TRUNK_INVALID != tgid) || (-1 != id) ) { 14193 return BCM_E_PORT; 14194 } 14195 } else { 14196 port = arg; 14197 modid = SOC_DEFAULT_DMA_SRCMOD_GET(unit); 14198 } 14199 14200 if (!SOC_PORT_VALID(unit, port)) { 14201 return BCM_E_PORT; 14202 } 14203 14204 sal_memset(hghdr, 0, sizeof(soc_higig2_hdr_t)); 14205 soc_higig2_field_set(unit, xgh, HG_start, SOC_HIGIG2_START); 14206 soc_higig2_field_set(unit, xgh, HG_ppd_type, 0); 14207 soc_higig2_field_set(unit, xgh, HG_dst_mod, modid); 14208 soc_higig2_field_set(unit, xgh, HG_dst_port, port); 14209 14210 raddr = soc_reg_addr(unit, CMIC_PKT_VLANr, REG_PORT_ANY, 0); 14211 /* coverity[result_independent_of_operands] */ 14212 BCM_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 14213 vlan_val = soc_reg_field_get(unit, CMIC_PKT_VLANr, rval, VLAN_IDf); 14214 if (0 == vlan_val) { 14215 vlan_val = DEFAULT_RCPU_VLAN; 14216 } 14217 soc_higig2_field_set(unit, xgh, HG_vlan_tag, vlan_val); 14218 soc_higig2_field_set(unit, xgh, HG_opcode, SOC_HIGIG_OP_CPU); 14219 14220 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 14221 /* coverity[result_independent_of_operands] */ 14222 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[0])); 14223 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 14224 /* coverity[result_independent_of_operands] */ 14225 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[1])); 14226 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 14227 /* coverity[result_independent_of_operands] */ 14228 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[2])); 14229 raddr = soc_reg_addr(unit, CMIC_PKT_RMH3r, REG_PORT_ANY, 0); 14230 /* coverity[result_independent_of_operands] */ 14231 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[3])); 14232 14233 return BCM_E_NONE; 14234 #else 14235 return BCM_E_UNAVAIL; 14236 #endif /* BCM_HIGIG2_SUPPORT */ 14237 } 14238 14239 /* 14240 * Function: 14241 * _bcm_rcpu_higig_header_get 14242 * Description: 14243 * Get the SOBMH header for RCPU usage and retrieve the port numebr 14244 * Parameters: 14245 * unit - StrataSwitch PCI device unit number (driver internal). 14246 * type - The required switch control type to get MAC for 14247 * arg - port number in the SOBMH header 14248 * Returns: 14249 * BCM_E_xxxx 14250 */ 14251 STATIC int 14252 _bcm_rcpu_higig_header_get(int unit, int *arg) 14253 { 14254 #if defined(BCM_HIGIG2_SUPPORT) 14255 uint32 hghdr[4]; /* 4 words HIGIG2 header to program */ 14256 soc_higig2_hdr_t *xgh = (soc_higig2_hdr_t *)hghdr; 14257 uint32 raddr; 14258 int isGport; 14259 14260 if (NULL == arg) { 14261 return BCM_E_PARAM; 14262 } 14263 14264 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 14265 /* coverity[result_independent_of_operands] */ 14266 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[0]))); 14267 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 14268 /* coverity[result_independent_of_operands] */ 14269 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[1]))); 14270 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 14271 /* coverity[result_independent_of_operands] */ 14272 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[2]))); 14273 raddr = soc_reg_addr(unit, CMIC_PKT_RMH3r, REG_PORT_ANY, 0); 14274 /* coverity[result_independent_of_operands] */ 14275 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[3]))); 14276 14277 BCM_IF_ERROR_RETURN( 14278 bcm_esw_switch_control_get(unit, bcmSwitchUseGport, &isGport)); 14279 14280 if (isGport) { 14281 _bcm_gport_dest_t gport_st; 14282 14283 gport_st.gport_type = BCM_GPORT_TYPE_MODPORT; 14284 gport_st.modid = soc_higig2_field_get(unit, xgh, HG_dst_mod); 14285 gport_st.port = soc_higig2_field_get(unit, xgh, HG_dst_port); 14286 BCM_IF_ERROR_RETURN( 14287 _bcm_esw_gport_construct(unit, &gport_st, arg)); 14288 } else { 14289 *arg = soc_higig2_field_get(unit, xgh, HG_dst_port); 14290 } 14291 14292 return BCM_E_NONE; 14293 #else 14294 return BCM_E_UNAVAIL; 14295 #endif 14296 } 14297 #endif /* RCPU and XGS3 SUPPORT */ 14298 14299 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 14300 defined(BCM_TRIDENT2_SUPPORT) 14301 STATIC int 14302 _bcm_switch_qcn_set(int unit, bcm_switch_control_t type, int arg) 14303 { 14304 uint32 rval, misc_config; 14305 #if defined(BCM_TRIUMPH3_SUPPORT) 14306 egr_qcn_cnm_control_table_entry_t entry; 14307 #endif 14308 if (!soc_feature(unit, soc_feature_qcn)) { 14309 return BCM_E_UNAVAIL; 14310 } 14311 14312 switch (type) { 14313 case bcmSwitchCongestionCntag: 14314 BCM_IF_ERROR_RETURN 14315 (soc_reg_field32_modify(unit, ING_QCN_CNTAG_ETHERTYPEr, 14316 REG_PORT_ANY, ENABLEf, arg ? 1 : 0)); 14317 return soc_reg_field32_modify(unit, EGR_QCN_CNTAG_ETHERTYPEr, 14318 REG_PORT_ANY, ENABLEf, arg ? 1 : 0); 14319 case bcmSwitchCongestionCntagEthertype: 14320 if (arg < 0 || arg > 0xffff) { 14321 return BCM_E_PARAM; 14322 } 14323 BCM_IF_ERROR_RETURN 14324 (soc_reg_field32_modify(unit, ING_QCN_CNTAG_ETHERTYPEr, 14325 REG_PORT_ANY, ETHERTYPEf, arg)); 14326 return soc_reg_field32_modify(unit, EGR_QCN_CNTAG_ETHERTYPEr, 14327 REG_PORT_ANY, ETHERTYPEf, arg); 14328 case bcmSwitchCongestionCnm: 14329 if (!SOC_REG_IS_VALID(unit, ING_QCN_CNM_ETHERTYPEr)) { 14330 return BCM_E_UNAVAIL; 14331 } 14332 BCM_IF_ERROR_RETURN 14333 (soc_reg_field32_modify(unit, ING_QCN_CNM_ETHERTYPEr, 14334 REG_PORT_ANY, ENABLEf, arg ? 1 : 0)); 14335 return soc_reg_field32_modify(unit, EGR_QCN_CNM_ETHERTYPEr, 14336 REG_PORT_ANY, ENABLEf, arg ? 1 : 0); 14337 case bcmSwitchCongestionCnmEthertype: 14338 if (!SOC_REG_IS_VALID(unit, ING_QCN_CNM_ETHERTYPEr)) { 14339 return BCM_E_UNAVAIL; 14340 } 14341 if (arg < 0 || arg > 0xffff) { 14342 return BCM_E_PARAM; 14343 } 14344 BCM_IF_ERROR_RETURN 14345 (soc_reg_field32_modify(unit, ING_QCN_CNM_ETHERTYPEr, 14346 REG_PORT_ANY, ETHERTYPEf, arg)); 14347 return soc_reg_field32_modify(unit, EGR_QCN_CNM_ETHERTYPEr, 14348 REG_PORT_ANY, ETHERTYPEf, arg); 14349 case bcmSwitchCongestionNotificationIdHigh: 14350 if (!SOC_MEM_IS_VALID(unit, EGR_QCN_CNM_CONTROL_TABLEm)) { 14351 return BCM_E_UNAVAIL; 14352 } 14353 if (arg < 0 || arg > 0xffffff) { 14354 return BCM_E_PARAM; 14355 } 14356 return soc_mem_field32_modify(unit, EGR_QCN_CNM_CONTROL_TABLEm, 14357 0, QCN_CPID_PREFIXf, arg); 14358 case bcmSwitchCongestionNotificationIdQueue: 14359 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_2r)) { 14360 return BCM_E_UNAVAIL; 14361 } 14362 return soc_reg_field32_modify(unit, EGR_QCN_CNM_CONTROL_2r, 14363 REG_PORT_ANY, QCN_CNM_CPID_MODEf, 14364 arg ? 0 : 1); 14365 case bcmSwitchCongestionUseOuterTpid: 14366 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_2r)) { 14367 return BCM_E_UNAVAIL; 14368 } 14369 if (arg < -1 || arg > 0xffff) { 14370 return BCM_E_PARAM; 14371 } 14372 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_2r(unit, &rval)); 14373 if (arg == -1) { 14374 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_2r, &rval, 14375 QCN_CNM_USE_DEFAULT_OUTER_TPIDf, 0); 14376 } else { 14377 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_2r, &rval, 14378 QCN_CNM_USE_DEFAULT_OUTER_TPIDf, 1); 14379 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_2r, &rval, 14380 QCN_CNM_DEFAULT_OUTER_TPIDf, arg); 14381 } 14382 return WRITE_EGR_QCN_CNM_CONTROL_2r(unit, rval); 14383 case bcmSwitchCongestionUseOuterVlan: 14384 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14385 return BCM_E_UNAVAIL; 14386 } 14387 if (arg < -1 || arg > 0xfff) { 14388 return BCM_E_PARAM; 14389 } 14390 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14391 if (arg == -1) { 14392 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14393 QCN_CNM_USE_DEFAULT_OUTER_VLAN_IDf, 0); 14394 } else { 14395 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14396 QCN_CNM_USE_DEFAULT_OUTER_VLAN_IDf, 1); 14397 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14398 QCN_CNM_DEFAULT_OUTER_VLAN_IDf, arg); 14399 } 14400 return WRITE_EGR_QCN_CNM_CONTROL_1r(unit, rval); 14401 case bcmSwitchCongestionUseOuterPktPri: 14402 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14403 return BCM_E_UNAVAIL; 14404 } 14405 if (arg < -1 || arg > 7) { 14406 return BCM_E_PARAM; 14407 } 14408 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14409 if (arg == -1) { 14410 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14411 QCN_CNM_CHANGE_OUTER_DOT1Pf, 0); 14412 } else { 14413 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14414 QCN_CNM_CHANGE_OUTER_DOT1Pf, 1); 14415 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14416 QCN_CNM_OUTER_DOT1Pf, arg); 14417 } 14418 return WRITE_EGR_QCN_CNM_CONTROL_1r(unit, rval); 14419 case bcmSwitchCongestionUseOuterCfi: 14420 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14421 return BCM_E_UNAVAIL; 14422 } 14423 if (arg < -1 || arg > 1) { 14424 return BCM_E_PARAM; 14425 } 14426 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14427 if (arg == -1) { 14428 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14429 QCN_CNM_CHANGE_OUTER_CFIf, 0); 14430 } else { 14431 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14432 QCN_CNM_CHANGE_OUTER_CFIf, 1); 14433 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14434 QCN_CNM_OUTER_CFIf, arg); 14435 } 14436 return WRITE_EGR_QCN_CNM_CONTROL_1r(unit, rval); 14437 case bcmSwitchCongestionUseInnerPktPri: 14438 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14439 return BCM_E_UNAVAIL; 14440 } 14441 if (arg < -1 || arg > 7) { 14442 return BCM_E_PARAM; 14443 } 14444 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14445 if (arg == -1) { 14446 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14447 QCN_CNM_CHANGE_INNER_DOT1Pf, 0); 14448 } else { 14449 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14450 QCN_CNM_CHANGE_INNER_DOT1Pf, 1); 14451 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14452 QCN_CNM_INNER_DOT1Pf, arg); 14453 } 14454 return WRITE_EGR_QCN_CNM_CONTROL_1r(unit, rval); 14455 case bcmSwitchCongestionUseInnerCfi: 14456 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14457 return BCM_E_UNAVAIL; 14458 } 14459 if (arg < -1 || arg > 1) { 14460 return BCM_E_PARAM; 14461 } 14462 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14463 if (arg == -1) { 14464 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14465 QCN_CNM_CHANGE_INNER_CFIf, 0); 14466 } else { 14467 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14468 QCN_CNM_CHANGE_INNER_CFIf, 1); 14469 soc_reg_field_set(unit, EGR_QCN_CNM_CONTROL_1r, &rval, 14470 QCN_CNM_INNER_CFIf, arg); 14471 } 14472 return WRITE_EGR_QCN_CNM_CONTROL_1r(unit, rval); 14473 case bcmSwitchCongestionMissingCntag: 14474 if (!SOC_REG_IS_VALID(unit, ING_MISC_CONFIGr)) { 14475 return BCM_E_UNAVAIL; 14476 } 14477 if (!soc_reg_field_valid(unit, ING_MISC_CONFIGr, QCN_DO_NOT_GENERATE_CNM_IF_NO_CNTAGf)) { 14478 return SOC_E_UNAVAIL; 14479 } 14480 if (!soc_reg_field_valid(unit, EGR_CONFIG_1r, QCN_SEND_NULL_CNTAG_IF_NO_CNTAGf)) { 14481 return SOC_E_UNAVAIL; 14482 } 14483 if (arg < -1 || arg > 1) { 14484 return BCM_E_PARAM; 14485 } 14486 BCM_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &misc_config)); 14487 if (arg == -1) { /* Do not generate CNM */ 14488 soc_reg_field_set(unit, ING_MISC_CONFIGr, &misc_config, 14489 QCN_DO_NOT_GENERATE_CNM_IF_NO_CNTAGf, 1); 14490 } else { 14491 soc_reg_field_set(unit, ING_MISC_CONFIGr, &misc_config, 14492 QCN_DO_NOT_GENERATE_CNM_IF_NO_CNTAGf, 0); 14493 BCM_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 14494 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, 14495 QCN_SEND_NULL_CNTAG_IF_NO_CNTAGf, arg ? 1 : 0); 14496 BCM_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 14497 } 14498 return WRITE_ING_MISC_CONFIGr(unit, misc_config); 14499 #if defined(BCM_TRIUMPH3_SUPPORT) 14500 case bcmSwitchCongestionCnmSrcMacOui: 14501 case bcmSwitchCongestionCnmSrcMacNonOui: 14502 if (!SOC_MEM_IS_VALID(unit, EGR_QCN_CNM_CONTROL_TABLEm)) { 14503 return BCM_E_UNAVAIL; 14504 } 14505 BCM_IF_ERROR_RETURN( 14506 soc_mem_read(unit, EGR_QCN_CNM_CONTROL_TABLEm, 14507 MEM_BLOCK_ALL, 0, &entry)); 14508 BCM_IF_ERROR_RETURN( 14509 bcm_tr3_switch_qcn_mac_set(unit, type, EGR_QCN_CNM_CONTROL_TABLEm, 14510 QCN_CNM_SWITCH_MAC_ADDRESSf, &entry, arg)); 14511 14512 BCM_IF_ERROR_RETURN(soc_mem_write(unit, EGR_QCN_CNM_CONTROL_TABLEm, 14513 MEM_BLOCK_ALL, 0, &entry)); 14514 return BCM_E_NONE; 14515 #endif 14516 default: 14517 break; 14518 } 14519 14520 return BCM_E_UNAVAIL; 14521 } 14522 STATIC int 14523 _bcm_switch_qcn_get(int unit, bcm_switch_control_t type, int *arg) 14524 { 14525 uint32 rval; 14526 egr_qcn_cnm_control_table_entry_t entry; 14527 14528 if (!soc_feature(unit, soc_feature_qcn)) { 14529 return BCM_E_UNAVAIL; 14530 } 14531 14532 if (arg == NULL) { 14533 return BCM_E_PARAM; 14534 } 14535 14536 switch (type) { 14537 case bcmSwitchCongestionCntag: 14538 /* Ingress setting should match with egress setting */ 14539 BCM_IF_ERROR_RETURN(READ_ING_QCN_CNTAG_ETHERTYPEr(unit, &rval)); 14540 *arg = soc_reg_field_get(unit, ING_QCN_CNTAG_ETHERTYPEr, rval, 14541 ENABLEf); 14542 return BCM_E_NONE; 14543 case bcmSwitchCongestionCntagEthertype: 14544 /* Ingress setting should match with egress setting */ 14545 BCM_IF_ERROR_RETURN(READ_ING_QCN_CNTAG_ETHERTYPEr(unit, &rval)); 14546 *arg = soc_reg_field_get(unit, ING_QCN_CNTAG_ETHERTYPEr, rval, 14547 ETHERTYPEf); 14548 return BCM_E_NONE; 14549 case bcmSwitchCongestionCnm: 14550 if (!SOC_REG_IS_VALID(unit, ING_QCN_CNM_ETHERTYPEr)) { 14551 return BCM_E_UNAVAIL; 14552 } 14553 /* Ingress setting should match with egress setting */ 14554 BCM_IF_ERROR_RETURN(READ_ING_QCN_CNM_ETHERTYPEr(unit, &rval)); 14555 *arg = soc_reg_field_get(unit, ING_QCN_CNM_ETHERTYPEr, rval, 14556 ENABLEf); 14557 return BCM_E_NONE; 14558 case bcmSwitchCongestionCnmEthertype: 14559 if (!SOC_REG_IS_VALID(unit, ING_QCN_CNM_ETHERTYPEr)) { 14560 return BCM_E_UNAVAIL; 14561 } 14562 /* Ingress setting should match with egress setting */ 14563 BCM_IF_ERROR_RETURN(READ_ING_QCN_CNM_ETHERTYPEr(unit, &rval)); 14564 *arg = soc_reg_field_get(unit, ING_QCN_CNM_ETHERTYPEr, rval, 14565 ETHERTYPEf); 14566 return BCM_E_NONE; 14567 case bcmSwitchCongestionNotificationIdHigh: 14568 if (!SOC_MEM_IS_VALID(unit, EGR_QCN_CNM_CONTROL_TABLEm)) { 14569 return BCM_E_UNAVAIL; 14570 } 14571 BCM_IF_ERROR_RETURN(soc_mem_read(unit, EGR_QCN_CNM_CONTROL_TABLEm, 14572 MEM_BLOCK_ANY, 0, &entry)); 14573 *arg = soc_mem_field32_get(unit, EGR_QCN_CNM_CONTROL_TABLEm, 14574 &entry, QCN_CPID_PREFIXf); 14575 return BCM_E_NONE; 14576 case bcmSwitchCongestionNotificationIdQueue: 14577 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_2r)) { 14578 return BCM_E_UNAVAIL; 14579 } 14580 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_2r(unit, &rval)); 14581 *arg = soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_2r, rval, 14582 QCN_CNM_CPID_MODEf) ? 0 : 1; 14583 return BCM_E_NONE; 14584 case bcmSwitchCongestionUseOuterTpid: 14585 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_2r)) { 14586 return BCM_E_UNAVAIL; 14587 } 14588 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_2r(unit, &rval)); 14589 if (soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_2r, rval, 14590 QCN_CNM_USE_DEFAULT_OUTER_TPIDf)) { 14591 *arg = soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_2r, rval, 14592 QCN_CNM_DEFAULT_OUTER_TPIDf); 14593 } else { 14594 *arg = -1; 14595 } 14596 return BCM_E_NONE; 14597 case bcmSwitchCongestionUseOuterVlan: 14598 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14599 return BCM_E_UNAVAIL; 14600 } 14601 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14602 if (soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, rval, 14603 QCN_CNM_USE_DEFAULT_OUTER_VLAN_IDf)) { 14604 *arg = soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, rval, 14605 QCN_CNM_DEFAULT_OUTER_VLAN_IDf); 14606 } else { 14607 *arg = -1; 14608 } 14609 return BCM_E_NONE; 14610 case bcmSwitchCongestionUseOuterPktPri: 14611 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14612 return BCM_E_UNAVAIL; 14613 } 14614 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14615 if (soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, rval, 14616 QCN_CNM_CHANGE_OUTER_DOT1Pf)) { 14617 *arg = soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, 14618 rval, QCN_CNM_OUTER_DOT1Pf); 14619 } else { 14620 *arg = -1; 14621 } 14622 return BCM_E_NONE; 14623 case bcmSwitchCongestionUseOuterCfi: 14624 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14625 return BCM_E_UNAVAIL; 14626 } 14627 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14628 if (soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, rval, 14629 QCN_CNM_CHANGE_OUTER_CFIf)) { 14630 *arg = soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, 14631 rval, QCN_CNM_OUTER_CFIf); 14632 } else { 14633 *arg = -1; 14634 } 14635 return BCM_E_NONE; 14636 case bcmSwitchCongestionUseInnerPktPri: 14637 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14638 return BCM_E_UNAVAIL; 14639 } 14640 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14641 if (soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, rval, 14642 QCN_CNM_CHANGE_INNER_DOT1Pf)) { 14643 *arg = soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, 14644 rval, QCN_CNM_INNER_DOT1Pf); 14645 } else { 14646 *arg = -1; 14647 } 14648 return BCM_E_NONE; 14649 case bcmSwitchCongestionUseInnerCfi: 14650 if (!SOC_REG_IS_VALID(unit, EGR_QCN_CNM_CONTROL_1r)) { 14651 return BCM_E_UNAVAIL; 14652 } 14653 BCM_IF_ERROR_RETURN(READ_EGR_QCN_CNM_CONTROL_1r(unit, &rval)); 14654 if (soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, rval, 14655 QCN_CNM_CHANGE_INNER_CFIf)) { 14656 *arg = soc_reg_field_get(unit, EGR_QCN_CNM_CONTROL_1r, 14657 rval, QCN_CNM_INNER_CFIf); 14658 } else { 14659 *arg = -1; 14660 } 14661 return BCM_E_NONE; 14662 case bcmSwitchCongestionMissingCntag: 14663 if (!SOC_REG_IS_VALID(unit, ING_MISC_CONFIGr)) { 14664 return BCM_E_UNAVAIL; 14665 } 14666 if (!soc_reg_field_valid(unit, ING_MISC_CONFIGr, QCN_DO_NOT_GENERATE_CNM_IF_NO_CNTAGf)) { 14667 return SOC_E_UNAVAIL; 14668 } 14669 if (!soc_reg_field_valid(unit, EGR_CONFIG_1r, QCN_SEND_NULL_CNTAG_IF_NO_CNTAGf)) { 14670 return SOC_E_UNAVAIL; 14671 } 14672 BCM_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 14673 if (soc_reg_field_get(unit, ING_MISC_CONFIGr, rval, 14674 QCN_DO_NOT_GENERATE_CNM_IF_NO_CNTAGf)) { 14675 *arg = -1; 14676 } else { 14677 BCM_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 14678 *arg = soc_reg_field_get(unit, EGR_CONFIG_1r, rval, 14679 QCN_SEND_NULL_CNTAG_IF_NO_CNTAGf) ? 1 : 0; 14680 } 14681 return BCM_E_NONE; 14682 #if defined(BCM_TRIUMPH3_SUPPORT) 14683 case bcmSwitchCongestionCnmSrcMacOui: 14684 case bcmSwitchCongestionCnmSrcMacNonOui: 14685 if (!SOC_MEM_IS_VALID(unit, EGR_QCN_CNM_CONTROL_TABLEm)) { 14686 return BCM_E_UNAVAIL; 14687 } 14688 sal_memset(&entry, 0, sizeof(egr_qcn_cnm_control_table_entry_t)); 14689 BCM_IF_ERROR_RETURN( 14690 soc_mem_read(unit, EGR_QCN_CNM_CONTROL_TABLEm, 14691 MEM_BLOCK_ALL, 0, &entry)); 14692 return bcm_tr3_switch_qcn_mac_get(unit, type, EGR_QCN_CNM_CONTROL_TABLEm, 14693 QCN_CNM_SWITCH_MAC_ADDRESSf, &entry, (uint32 *)arg); 14694 #endif 14695 default: 14696 break; 14697 } 14698 14699 return BCM_E_UNAVAIL; 14700 } 14701 14702 /* 14703 * Function: 14704 * _bcm_switch_fcoe_ing_ethertype_set 14705 * Description: 14706 * Set the ethertype field(ingress) for FCOE 14707 * Parameters: 14708 * unit - unit number 14709 * arg - argument to set as Ethrtype 14710 * Returns: 14711 * BCM_E_xxxx 14712 */ 14713 14714 STATIC int 14715 _bcm_switch_fcoe_ing_ethertype_set(int unit, int arg) 14716 { 14717 uint32 rval; 14718 14719 BCM_IF_ERROR_RETURN(READ_ING_FCOE_ETHERTYPEr(unit, &rval)); 14720 if (arg > 0) { 14721 /* Enable and Set FCOE ethertype */ 14722 soc_reg_field_set(unit, ING_FCOE_ETHERTYPEr, &rval, ENABLEf, 1); 14723 soc_reg_field_set(unit, ING_FCOE_ETHERTYPEr, &rval, ETHERTYPEf, 14724 (uint16)arg); 14725 } else { 14726 /* Reset FCOE ethertype */ 14727 soc_reg_field_set(unit, ING_FCOE_ETHERTYPEr, &rval, ENABLEf, 0); 14728 soc_reg_field_set(unit, ING_FCOE_ETHERTYPEr, &rval, ETHERTYPEf, 0); 14729 } 14730 SOC_IF_ERROR_RETURN(WRITE_ING_FCOE_ETHERTYPEr(unit, rval)); 14731 return BCM_E_NONE; 14732 } 14733 14734 /* 14735 * Function: 14736 * _bcm_switch_fcoe_ing_ethertype_get 14737 * Description: 14738 * Get the ethertype field(ingress) for FCOE 14739 * Parameters: 14740 * unit - unit number 14741 * arg - Ethrtype to get 14742 * Returns: 14743 * BCM_E_xxxx 14744 */ 14745 14746 STATIC int 14747 _bcm_switch_fcoe_ing_ethertype_get(int unit, int *arg) 14748 { 14749 uint32 rval; 14750 int enable; 14751 14752 BCM_IF_ERROR_RETURN(READ_ING_FCOE_ETHERTYPEr(unit, &rval)); 14753 /* If ethertype enabled, return ethertype */ 14754 enable = soc_reg_field_get(unit, ING_FCOE_ETHERTYPEr, rval, ENABLEf); 14755 if (enable) { 14756 *arg = soc_reg_field_get(unit, ING_FCOE_ETHERTYPEr, rval, ETHERTYPEf); 14757 } else { 14758 *arg = 0; 14759 } 14760 return BCM_E_NONE; 14761 } 14762 14763 #if defined(BCM_TRIDENT2_SUPPORT) 14764 /* 14765 * Function: 14766 * _bcm_switch_fcoe_egr_ethertype_set 14767 * Description: 14768 * Set the EGR ethertype field for FCOE 14769 * Parameters: 14770 * unit - unit number 14771 * arg - argument to set as Ethrtype 14772 * Returns: 14773 * BCM_E_xxxx 14774 */ 14775 14776 STATIC int 14777 _bcm_switch_fcoe_egr_ethertype_set(int unit, int arg) 14778 { 14779 uint32 rval; 14780 14781 BCM_IF_ERROR_RETURN(READ_EGR_FCOE_ETHERTYPEr(unit, &rval)); 14782 if (arg > 0) { 14783 /* Enable and Set FCOE EGR ethertype */ 14784 soc_reg_field_set(unit, EGR_FCOE_ETHERTYPEr, &rval, ENABLEf, 1); 14785 soc_reg_field_set(unit, EGR_FCOE_ETHERTYPEr, &rval, ETHERTYPEf, 14786 (uint16)arg); 14787 } else { 14788 /* Reset FCOE EGR ethertype */ 14789 soc_reg_field_set(unit, EGR_FCOE_ETHERTYPEr, &rval, ENABLEf, 0); 14790 soc_reg_field_set(unit, EGR_FCOE_ETHERTYPEr, &rval, ETHERTYPEf, 0); 14791 } 14792 SOC_IF_ERROR_RETURN(WRITE_EGR_FCOE_ETHERTYPEr(unit, rval)); 14793 return BCM_E_NONE; 14794 } 14795 #endif /* defined(BCM_TRIDENT2_SUPPORT) */ 14796 14797 #endif /* defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) */ 14798 14799 #if defined(BCM_KATANA2_SUPPORT) 14800 /* 14801 * Function: 14802 * _bcm_switch_subportpkttag_ethertype_set 14803 * Description: 14804 * Set the LLTAG TPID for both ingress and egress 14805 * Parameters: 14806 * unit - unit number 14807 * ethertype - argument to set as Ethrtype 14808 * Returns: 14809 * BCM_E_xxxx 14810 */ 14811 STATIC int 14812 _bcm_switch_subportpkttag_ethertype_set(int unit, int ethertype) 14813 { 14814 if (ethertype < 0 || ethertype > 0xffff) { 14815 return BCM_E_PARAM; 14816 } 14817 14818 BCM_IF_ERROR_RETURN 14819 (soc_reg_field32_modify(unit, EGR_LLTAG_TPIDr, 14820 REG_PORT_ANY, TPIDf, ethertype)); 14821 BCM_IF_ERROR_RETURN 14822 (soc_reg_field32_modify(unit, EGR_LLTAG_TPIDr, 14823 REG_PORT_ANY, LLTAG_ETHERTYPE_ENABLEf, ethertype ? 1 : 0)); 14824 14825 BCM_IF_ERROR_RETURN 14826 (soc_reg_field32_modify(unit, EGR_LLTAG_TPID_2r, 14827 REG_PORT_ANY, TPIDf, ethertype)); 14828 BCM_IF_ERROR_RETURN 14829 (soc_reg_field32_modify(unit, EGR_LLTAG_TPID_2r, 14830 REG_PORT_ANY, LLTAG_ETHERTYPE_ENABLEf, ethertype ? 1 : 0)); 14831 14832 BCM_IF_ERROR_RETURN 14833 (soc_reg_field32_modify(unit, ING_LLTAG_TPIDr, 14834 REG_PORT_ANY, TPIDf, ethertype)); 14835 BCM_IF_ERROR_RETURN 14836 (soc_reg_field32_modify(unit, ING_LLTAG_TPIDr, 14837 REG_PORT_ANY, LLTAG_ETHERTYPE_ENABLEf, ethertype ? 1 : 0)); 14838 14839 return BCM_E_NONE; 14840 } 14841 14842 /* 14843 * Function: 14844 * _bcm_switch_subportpkttag_ethertype_get 14845 * Description: 14846 * Get the LLTAG TPID for both ingress and egress 14847 * Parameters: 14848 * unit - unit number 14849 * ethertype - LLTAG Ethrtype 14850 * Returns: 14851 * BCM_E_xxxx 14852 */ 14853 STATIC int 14854 _bcm_switch_subportpkttag_ethertype_get(int unit, int *ethertype) 14855 { 14856 uint32 rval; 14857 14858 if (ethertype == NULL) { 14859 return BCM_E_PARAM; 14860 } 14861 14862 BCM_IF_ERROR_RETURN(READ_ING_LLTAG_TPIDr(unit, &rval)); 14863 if (soc_reg_field_get(unit, ING_LLTAG_TPIDr, rval, LLTAG_ETHERTYPE_ENABLEf)) { 14864 *ethertype = soc_reg_field_get(unit, ING_LLTAG_TPIDr, rval, TPIDf); 14865 } else { 14866 *ethertype = 0; 14867 } 14868 14869 return BCM_E_NONE; 14870 } 14871 #endif /* defined(BCM_KATANA2_SUPPORT) */ 14872 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || \ 14873 defined(BCM_KATANA_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 14874 defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || \ 14875 defined(BCM_SABER2_SUPPORT) 14876 14877 #if defined(BCM_SABER2_SUPPORT) 14878 int 14879 _bcm_switch_port_to_phyaddr(int unit, int port) 14880 { 14881 int phy_id; 14882 #ifdef PORTMOD_SUPPORT 14883 if (soc_feature(unit, soc_feature_portmod)) { 14884 phy_id = portmod_port_to_phyaddr(unit, port); 14885 } else 14886 #endif 14887 { 14888 phy_id = PORT_TO_PHY_ADDR(unit, port); 14889 } 14890 return phy_id; 14891 } 14892 #endif 14893 14894 /* Number of KT2 physical ports = 40 */ 14895 _bcm_l1_port_mx_lane_map_t _kt2_l1_port_mx_lane_map[] = { 14896 {0, 0, 0, 1}, /* port 0 is not valid */ 14897 {1, 0, 0, 0}, {2, 0, 1, 1}, {3, 0, 2, 2}, {4, 0, 3, 3}, 14898 {5, 0, 0, 4}, {6, 0, 1, 5}, {7, 0, 2, 6}, {8, 0, 3, 7}, 14899 {9, 0, 0, 8}, {10, 0, 1, 9}, {11, 0, 2, 10}, {12, 0, 3, 11}, 14900 {13, 0, 0, 12}, {14, 0, 1, 13}, {15, 0, 2, 14}, {16, 0, 3, 15}, 14901 {17, 0, 0, 16}, {18, 0, 1, 17}, {19, 0, 2, 18}, {20, 0, 3, 19}, 14902 {21, 0, 0, 20}, {22, 0, 1, 21}, {23, 0, 2, 22}, {24, 0, 3, 23}, 14903 {25, 0, 0, 24}, {26, 0, 0, 25}, {27, 1, 0, 26}, {28, 2, 0, 27}, 14904 {29, 2, 1, 28}, {30, 2, 2, 29}, {31, 2, 3, 30}, {32, 1, 1, 31}, 14905 {33, 1, 2, 32}, {34, 1, 3, 33}, {35, 0, 1, 34}, {36, 0, 2, 35}, 14906 {37, 0, 3, 36}, {38, 0, 1, 37}, {39, 0, 2, 38}, {40, 0, 3, 39} 14907 }; 14908 14909 STATIC int 14910 _bcm_switch_sync_port_select_set(int unit, uint32 val) 14911 { 14912 uint32 rval; 14913 /* Note: 24, 25 are invalid, 14914 * but we are just setting 0 in those cases 14915 */ 14916 if (SOC_IS_HURRICANE(unit) || SOC_IS_ENDURO(unit)) { 14917 static int16 _L1_port_val_map[] = { 14918 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14919 4, 5, 6, 7, 8, 9, 10, 11, 0, 0, 12, 12, 13, 13 14920 }; 14921 if (val >= COUNTOF(_L1_port_val_map)) { 14922 return BCM_E_PARAM; 14923 } 14924 BCM_IF_ERROR_RETURN( 14925 READ_CMIC_MISC_CONTROLr(unit, &rval)); 14926 if ((val <= 3) || ((val >= 8) && (val <= 15)) || 14927 (val == 26) || (val == 28)) { 14928 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 14929 L1_CLK0_RECOVERY_MUXf, 14930 _L1_port_val_map[val]); 14931 } else { 14932 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 14933 L1_CLK1_RECOVERY_MUXf, 14934 _L1_port_val_map[val]); 14935 } 14936 BCM_IF_ERROR_RETURN( 14937 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 14938 } else if (SOC_IS_KATANA(unit)) { 14939 BCM_IF_ERROR_RETURN( 14940 READ_TOP_MISC_CONTROLr(unit, &rval)); 14941 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 14942 L1_CLK0_RECOVERY_MUX_SELf, 14943 val); 14944 BCM_IF_ERROR_RETURN( 14945 WRITE_TOP_MISC_CONTROLr(unit, rval)); 14946 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 14947 BCM_IF_ERROR_RETURN( 14948 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 14949 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 14950 L1_RCVD_PRI_CLK_PORT_SELf, val); 14951 BCM_IF_ERROR_RETURN( 14952 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 14953 } else if (SOC_IS_HURRICANE2(unit)) { 14954 BCM_IF_ERROR_RETURN( 14955 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 14956 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 14957 L1_RCVD_PRI_PORT_SELf, val); 14958 BCM_IF_ERROR_RETURN( 14959 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 14960 } else if (SOC_IS_KATANA2(unit) && !SOC_IS_SABER2(unit)) { 14961 /* coverity[unsigned_compare] */ 14962 if ((val > (COUNTOF(_kt2_l1_port_mx_lane_map) - 1)) || 14963 !SOC_PORT_VALID(unit, val)) { 14964 return BCM_E_PARAM; 14965 } 14966 /* coverity[unchecked_value] */ 14967 READ_TOP_MISC_CONTROL_0r(unit, &rval); 14968 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 14969 L1_CLK0_RECOVERY_MUX_SELf, 14970 _kt2_l1_port_mx_lane_map[val].recovered_clock_select); 14971 BCM_IF_ERROR_RETURN( 14972 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 14973 /* For KT2 B0, need to set lane num for clk recovery for wc ports */ 14974 if((_kt2_l1_port_mx_lane_map[val].unicore_or_warpcore) && 14975 soc_reg_field_valid(unit, TOP_MISC_CONTROL_3r, 14976 L1_WC0_RECOVERY_CLK0_MUX_SELf)) { 14977 BCM_IF_ERROR_RETURN( 14978 READ_TOP_MISC_CONTROL_3r(unit, &rval)); 14979 soc_reg_field_set(unit, TOP_MISC_CONTROL_3r, &rval, 14980 (_kt2_l1_port_mx_lane_map[val].unicore_or_warpcore == 1) 14981 ? L1_WC0_RECOVERY_CLK0_MUX_SELf : L1_WC1_RECOVERY_CLK0_MUX_SELf, 14982 _kt2_l1_port_mx_lane_map[val].lane_num); 14983 BCM_IF_ERROR_RETURN( 14984 WRITE_TOP_MISC_CONTROL_3r(unit, rval)); 14985 } 14986 } 14987 #if defined(BCM_SABER2_SUPPORT) 14988 else if (SOC_IS_SABER2(unit)) { 14989 /* coverity[unchecked_value] */ 14990 /* mux value = physical port - 1*/ 14991 READ_TOP_MISC_CONTROL_0r(unit, &rval); 14992 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 14993 L1_CLK0_RECOVERY_MUX_SELf, val -1); 14994 BCM_IF_ERROR_RETURN( 14995 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 14996 /* phy port 25 to 28 are eagle ports */ 14997 /* phy xe<port num> MAIN0_SYNCE_CTLr 0 */ 14998 if ((val >= 25 && val <= 28) && 14999 SOC_PORT_VALID(unit, val)) { 15000 uint32 phy_reg = 0x9002; 15001 int phy_addr = _bcm_switch_port_to_phyaddr(unit, val); 15002 if (phy_addr == 0xff) { 15003 /* no phy address assigned */ 15004 return BCM_E_PARAM; 15005 } 15006 /* all lanes divisor configured 0 15007 * by default, eagle phy does /11, setting this configuration is 15008 * mandatory to get correct frequency... 15009 * Q: do we need to implement per lane reset .. not seen any 15010 * scenerio though currently 15011 */ 15012 BCM_IF_ERROR_RETURN( 15013 soc_sbus_mdio_write(unit, phy_addr, phy_reg, 0)); 15014 } 15015 } 15016 #endif 15017 15018 return BCM_E_NONE; 15019 } 15020 15021 STATIC int 15022 _bcm_switch_sync_port_backup_select_set(int unit, uint32 val) 15023 { 15024 uint32 rval; 15025 if (SOC_IS_KATANA(unit)) { 15026 BCM_IF_ERROR_RETURN( 15027 READ_TOP_MISC_CONTROLr(unit, &rval)); 15028 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15029 L1_CLK1_RECOVERY_MUX_SELf, 15030 val); 15031 BCM_IF_ERROR_RETURN( 15032 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15033 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 15034 BCM_IF_ERROR_RETURN( 15035 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 15036 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 15037 L1_RCVD_BKUP_CLK_PORT_SELf, val); 15038 BCM_IF_ERROR_RETURN( 15039 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 15040 } else if (SOC_IS_HURRICANE2(unit)) { 15041 BCM_IF_ERROR_RETURN( 15042 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 15043 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 15044 L1_RCVD_BKUP_PORT_SELf, val); 15045 BCM_IF_ERROR_RETURN( 15046 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 15047 } else if (SOC_IS_KATANA2(unit) && !SOC_IS_SABER2(unit)) { 15048 /* coverity[unsigned_compare] */ 15049 if ((val > (COUNTOF(_kt2_l1_port_mx_lane_map) - 1)) || 15050 !SOC_PORT_VALID(unit, val)) { 15051 return BCM_E_PARAM; 15052 } 15053 /* coverity[unchecked_value] */ 15054 BCM_IF_ERROR_RETURN( 15055 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15056 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15057 L1_CLK1_RECOVERY_MUX_SELf, 15058 _kt2_l1_port_mx_lane_map[val].recovered_clock_select); 15059 BCM_IF_ERROR_RETURN( 15060 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15061 /* For KT2 B0, need to set lane num for clk recovery for wc ports */ 15062 if((_kt2_l1_port_mx_lane_map[val].unicore_or_warpcore) && 15063 soc_reg_field_valid(unit, TOP_MISC_CONTROL_3r, 15064 L1_WC0_RECOVERY_CLK0_MUX_SELf)) { 15065 BCM_IF_ERROR_RETURN( 15066 READ_TOP_MISC_CONTROL_3r(unit, &rval)); 15067 soc_reg_field_set(unit, TOP_MISC_CONTROL_3r, &rval, 15068 (_kt2_l1_port_mx_lane_map[val].unicore_or_warpcore == 1) 15069 ? L1_WC0_RECOVERY_CLK1_MUX_SELf : L1_WC1_RECOVERY_CLK1_MUX_SELf, 15070 _kt2_l1_port_mx_lane_map[val].lane_num); 15071 BCM_IF_ERROR_RETURN( 15072 WRITE_TOP_MISC_CONTROL_3r(unit, rval)); 15073 } 15074 } 15075 #if defined(BCM_SABER2_SUPPORT) 15076 else if (SOC_IS_SABER2(unit)) { 15077 /* coverity[unchecked_value] */ 15078 /* mux value = physical port - 1*/ 15079 READ_TOP_MISC_CONTROL_0r(unit, &rval); 15080 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15081 L1_CLK1_RECOVERY_MUX_SELf, val -1); 15082 BCM_IF_ERROR_RETURN( 15083 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15084 15085 /* phy port 25 to 28 are eagle ports */ 15086 /* phy xe<port num> MAIN0_SYNCE_CTLr 0 */ 15087 if ((val >= 25 && val <= 28) && 15088 SOC_PORT_VALID(unit, val)) { 15089 uint32 phy_reg = 0x9002; 15090 int phy_addr = _bcm_switch_port_to_phyaddr(unit, val); 15091 if (phy_addr == 0xff) { 15092 /* no phy address assigned */ 15093 return BCM_E_PARAM; 15094 } 15095 /* all lanes divisor configured 0 15096 * by default, eagle phy does /11, setting this configuration is 15097 * mandatory to get correct frequency... 15098 * Q: do we need to implement per lane reset .. not seen any 15099 * scenerio though currently 15100 */ 15101 BCM_IF_ERROR_RETURN( 15102 soc_sbus_mdio_write(unit, phy_addr, phy_reg, 0)); 15103 } 15104 15105 } 15106 #endif 15107 15108 return BCM_E_NONE; 15109 } 15110 15111 15112 STATIC int 15113 _bcm_switch_sync_port_select_get(int unit, uint8 type, uint32 *val) 15114 { 15115 uint32 rval, port; 15116 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit)) { 15117 static int16 _L1_val_port_map0[] = { 15118 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15, 26, 28 15119 }; 15120 static int16 _L1_val_port_map1[] = { 15121 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23, 27, 29 15122 }; 15123 READ_CMIC_MISC_CONTROLr(unit, &rval); 15124 if (type) { /* primary (1) */ 15125 port = soc_reg_field_get(unit, CMIC_MISC_CONTROLr, rval, 15126 L1_CLK0_RECOVERY_MUXf); 15127 *val = _L1_val_port_map0[port]; 15128 } else { /* backup (0) */ 15129 port = soc_reg_field_get(unit, CMIC_MISC_CONTROLr, rval, 15130 L1_CLK1_RECOVERY_MUXf); 15131 *val = _L1_val_port_map1[port]; 15132 } 15133 } else if (SOC_IS_KATANA(unit)) { 15134 BCM_IF_ERROR_RETURN( 15135 READ_TOP_MISC_CONTROLr(unit, &rval)); 15136 if (type) { /* primary (1) */ 15137 *val = soc_reg_field_get(unit, TOP_MISC_CONTROLr, rval, 15138 L1_CLK0_RECOVERY_MUX_SELf); 15139 } else { /* backup (0) */ 15140 *val = soc_reg_field_get(unit, TOP_MISC_CONTROLr, rval, 15141 L1_CLK1_RECOVERY_MUX_SELf); 15142 } 15143 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 15144 BCM_IF_ERROR_RETURN( 15145 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 15146 if (type) { 15147 /* primary (1) */ 15148 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 15149 L1_RCVD_PRI_CLK_PORT_SELf); 15150 } else { 15151 /* backup (0) */ 15152 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 15153 L1_RCVD_BKUP_CLK_PORT_SELf); 15154 } 15155 } else if (SOC_IS_HURRICANE2(unit)) { 15156 BCM_IF_ERROR_RETURN( 15157 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 15158 if (type) { 15159 /* primary (1) */ 15160 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 15161 L1_RCVD_PRI_PORT_SELf); 15162 } else { 15163 /* backup (0) */ 15164 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 15165 L1_RCVD_BKUP_PORT_SELf); 15166 } 15167 } else if(SOC_IS_KATANA2(unit) && !SOC_IS_SABER2(unit)) { 15168 BCM_IF_ERROR_RETURN( 15169 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15170 if (type) { /* primary (1) */ 15171 port = soc_reg_field_get(unit, TOP_MISC_CONTROL_0r, rval, 15172 L1_CLK0_RECOVERY_MUX_SELf); 15173 *val = _kt2_l1_port_mx_lane_map[port + 1].recovered_clock_select; 15174 } else { /* backup (0) */ 15175 port = soc_reg_field_get(unit, TOP_MISC_CONTROL_0r, rval, 15176 L1_CLK1_RECOVERY_MUX_SELf); 15177 *val = _kt2_l1_port_mx_lane_map[port + 1].port; 15178 } 15179 } else if(SOC_IS_SABER2(unit)) { 15180 BCM_IF_ERROR_RETURN( 15181 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15182 if (type) { /* primary (1) */ 15183 port = soc_reg_field_get(unit, TOP_MISC_CONTROL_0r, rval, 15184 L1_CLK0_RECOVERY_MUX_SELf); 15185 *val = port + 1; 15186 } else { /* backup (0) */ 15187 port = soc_reg_field_get(unit, TOP_MISC_CONTROL_0r, rval, 15188 L1_CLK1_RECOVERY_MUX_SELf); 15189 *val = port + 1; 15190 } 15191 } 15192 15193 return BCM_E_NONE; 15194 } 15195 15196 STATIC int 15197 _bcm_switch_div_ctrl_select_set(int unit, uint32 val) 15198 { 15199 uint32 rval; 15200 if (SOC_IS_HURRICANE(unit) || SOC_IS_ENDURO(unit)) { 15201 if (val == 1) { 15202 BCM_IF_ERROR_RETURN( 15203 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15204 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15205 L1_CLK0_RECOVERY_DIV_CTRLf, 15206 0x0); 15207 BCM_IF_ERROR_RETURN( 15208 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15209 15210 BCM_IF_ERROR_RETURN( 15211 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15212 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15213 L1_CLK0_RECOVERY_DIV_CTRLf, 15214 0x2); 15215 BCM_IF_ERROR_RETURN( 15216 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15217 15218 BCM_IF_ERROR_RETURN( 15219 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15220 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15221 L1_CLK0_RECOVERY_DIV_CTRLf, 15222 0x3); 15223 BCM_IF_ERROR_RETURN( 15224 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15225 } else { 15226 BCM_IF_ERROR_RETURN( 15227 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15228 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15229 L1_CLK0_RECOVERY_DIV_CTRLf, 15230 0x0); 15231 BCM_IF_ERROR_RETURN( 15232 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15233 } 15234 } else if (SOC_IS_KATANA(unit)) { 15235 if (val == 1) { 15236 BCM_IF_ERROR_RETURN( 15237 READ_TOP_MISC_CONTROLr(unit, &rval)); 15238 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15239 L1_CLK0_RECOVERY_DIV_CTRLf, 15240 0x0); 15241 BCM_IF_ERROR_RETURN( 15242 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15243 15244 BCM_IF_ERROR_RETURN( 15245 READ_TOP_MISC_CONTROLr(unit, &rval)); 15246 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15247 L1_CLK0_RECOVERY_DIV_CTRLf, 15248 0x2); 15249 BCM_IF_ERROR_RETURN( 15250 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15251 15252 BCM_IF_ERROR_RETURN( 15253 READ_TOP_MISC_CONTROLr(unit, &rval)); 15254 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15255 L1_CLK0_RECOVERY_DIV_CTRLf, 15256 0x3); 15257 BCM_IF_ERROR_RETURN( 15258 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15259 } else { 15260 BCM_IF_ERROR_RETURN( 15261 READ_TOP_MISC_CONTROLr(unit, &rval)); 15262 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15263 L1_CLK0_RECOVERY_DIV_CTRLf, 15264 0x0); 15265 BCM_IF_ERROR_RETURN( 15266 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15267 } 15268 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE2(unit) || 15269 SOC_IS_HURRICANE3(unit)) { 15270 BCM_IF_ERROR_RETURN( 15271 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 15272 if (val == 1) { 15273 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 15274 L1_RCVD_FREQ_SELf, 1); 15275 } else { 15276 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 15277 L1_RCVD_FREQ_SELf, 0); 15278 } 15279 BCM_IF_ERROR_RETURN( 15280 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 15281 } else if (SOC_IS_KATANA2(unit)) { 15282 if (val == 1) { 15283 /* set SYNCE divided by 5 */ 15284 BCM_IF_ERROR_RETURN( 15285 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15286 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15287 L1_CLK0_RECOVERY_DIV_CTRLf, 15288 0x0); 15289 BCM_IF_ERROR_RETURN( 15290 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15291 15292 BCM_IF_ERROR_RETURN( 15293 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15294 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15295 L1_CLK0_RECOVERY_DIV_CTRLf, 15296 0x2); 15297 BCM_IF_ERROR_RETURN( 15298 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15299 15300 BCM_IF_ERROR_RETURN( 15301 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15302 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15303 L1_CLK0_RECOVERY_DIV_CTRLf, 15304 0x3); 15305 BCM_IF_ERROR_RETURN( 15306 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15307 15308 #if defined(BCM_SABER2_SUPPORT) 15309 /* above configuration sets synce divide by 5 so setting 15310 * phy divisors to 0 15311 */ 15312 if (SOC_IS_SABER2(unit) && 15313 SOC_PORT_VALID(unit, 25)) { 15314 /* phy port 25 to 28 are eagle ports */ 15315 /* phy xe<port num> MAIN0_SYNCE_CTLr 0 */ 15316 uint32 phy_reg = 0x9002; 15317 int phy_addr = _bcm_switch_port_to_phyaddr(unit, 25); 15318 if (phy_addr == 0xff) { 15319 /* no phy address assigned */ 15320 return BCM_E_PARAM; 15321 } 15322 /* all lanes/ports clk divisor set to zero */ 15323 BCM_IF_ERROR_RETURN( 15324 soc_sbus_mdio_write(unit, phy_addr, phy_reg, 0)); 15325 } 15326 #endif 15327 15328 } else { 15329 /* reseting all divisors */ 15330 BCM_IF_ERROR_RETURN( 15331 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15332 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15333 L1_CLK0_RECOVERY_DIV_CTRLf, 15334 0x0); 15335 BCM_IF_ERROR_RETURN( 15336 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15337 15338 #if defined(BCM_SABER2_SUPPORT) 15339 if (SOC_IS_SABER2(unit) && 15340 SOC_PORT_VALID(unit, 25)) { 15341 /* phy port 25 to 28 are eagle ports */ 15342 /* phy xe<port num> MAIN0_SYNCE_CTLr 0 */ 15343 uint32 phy_reg = 0x9002; 15344 int phy_addr = _bcm_switch_port_to_phyaddr(unit, 25); 15345 if (phy_addr == 0xff) { 15346 /* no phy address assigned */ 15347 return BCM_E_PARAM; 15348 } 15349 /* all lanes/ports clk divisor set to zero */ 15350 BCM_IF_ERROR_RETURN( 15351 soc_sbus_mdio_write(unit, phy_addr, phy_reg, 0)); 15352 } 15353 #endif 15354 15355 } 15356 } else { 15357 return BCM_E_UNAVAIL; 15358 } 15359 15360 return BCM_E_NONE; 15361 } 15362 15363 STATIC int 15364 _bcm_switch_div_ctrl_backup_select_set(int unit, uint32 val) 15365 { 15366 15367 uint32 rval; 15368 if (SOC_IS_HURRICANE(unit) || SOC_IS_ENDURO(unit)) { 15369 if (val == 1) { 15370 BCM_IF_ERROR_RETURN( 15371 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15372 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15373 L1_CLK1_RECOVERY_DIV_CTRLf, 15374 0x0); 15375 BCM_IF_ERROR_RETURN( 15376 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15377 15378 BCM_IF_ERROR_RETURN( 15379 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15380 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15381 L1_CLK1_RECOVERY_DIV_CTRLf, 15382 0x2); 15383 BCM_IF_ERROR_RETURN( 15384 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15385 15386 BCM_IF_ERROR_RETURN( 15387 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15388 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15389 L1_CLK1_RECOVERY_DIV_CTRLf, 15390 0x3); 15391 BCM_IF_ERROR_RETURN( 15392 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15393 } else { 15394 BCM_IF_ERROR_RETURN( 15395 READ_CMIC_MISC_CONTROLr(unit, &rval)); 15396 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15397 L1_CLK1_RECOVERY_DIV_CTRLf, 15398 0x0); 15399 BCM_IF_ERROR_RETURN( 15400 WRITE_CMIC_MISC_CONTROLr(unit, rval)); 15401 } 15402 } else if (SOC_IS_KATANA(unit)) { 15403 if (val == 1) { 15404 BCM_IF_ERROR_RETURN( 15405 READ_TOP_MISC_CONTROLr(unit, &rval)); 15406 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15407 L1_CLK1_RECOVERY_DIV_CTRLf, 15408 0x0); 15409 BCM_IF_ERROR_RETURN( 15410 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15411 15412 BCM_IF_ERROR_RETURN( 15413 READ_TOP_MISC_CONTROLr(unit, &rval)); 15414 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15415 L1_CLK1_RECOVERY_DIV_CTRLf, 15416 0x2); 15417 BCM_IF_ERROR_RETURN( 15418 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15419 15420 BCM_IF_ERROR_RETURN( 15421 READ_TOP_MISC_CONTROLr(unit, &rval)); 15422 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15423 L1_CLK1_RECOVERY_DIV_CTRLf, 15424 0x3); 15425 BCM_IF_ERROR_RETURN( 15426 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15427 } else { 15428 BCM_IF_ERROR_RETURN( 15429 READ_TOP_MISC_CONTROLr(unit, &rval)); 15430 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 15431 L1_CLK1_RECOVERY_DIV_CTRLf, 15432 0x0); 15433 BCM_IF_ERROR_RETURN( 15434 WRITE_TOP_MISC_CONTROLr(unit, rval)); 15435 } 15436 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE2(unit) || 15437 SOC_IS_HURRICANE3(unit)) { 15438 BCM_IF_ERROR_RETURN( 15439 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 15440 if (val == 1) { 15441 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 15442 L1_RCVD_BKUP_FREQ_SELf, 1); 15443 } else { 15444 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 15445 L1_RCVD_BKUP_FREQ_SELf, 0); 15446 } 15447 BCM_IF_ERROR_RETURN( 15448 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 15449 } else if (SOC_IS_KATANA2(unit)) { 15450 if (val == 1) { 15451 /* set SYNCE divided by 5 */ 15452 BCM_IF_ERROR_RETURN( 15453 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15454 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15455 L1_CLK1_RECOVERY_DIV_CTRLf, 15456 0x0); 15457 BCM_IF_ERROR_RETURN( 15458 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15459 15460 BCM_IF_ERROR_RETURN( 15461 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15462 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15463 L1_CLK1_RECOVERY_DIV_CTRLf, 15464 0x2); 15465 BCM_IF_ERROR_RETURN( 15466 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15467 15468 BCM_IF_ERROR_RETURN( 15469 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15470 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15471 L1_CLK1_RECOVERY_DIV_CTRLf, 15472 0x3); 15473 BCM_IF_ERROR_RETURN( 15474 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15475 15476 #if defined(BCM_SABER2_SUPPORT) 15477 /* above configuration sets synce divide by 5 so setting 15478 * phy divisors to 0 15479 */ 15480 if (SOC_IS_SABER2(unit) && 15481 SOC_PORT_VALID(unit, 25)) { 15482 /* phy port 25 to 28 are eagle ports */ 15483 /* phy xe<port num> MAIN0_SYNCE_CTLr 0 */ 15484 uint32 phy_reg = 0x9002; 15485 int phy_addr = _bcm_switch_port_to_phyaddr(unit, 25); 15486 if (phy_addr == 0xff) { 15487 /* no phy address assigned */ 15488 return BCM_E_PARAM; 15489 } 15490 /* all lanes/ports clk divisor set to zero */ 15491 BCM_IF_ERROR_RETURN( 15492 soc_sbus_mdio_write(unit, phy_addr, phy_reg, 0)); 15493 } 15494 #endif 15495 } else { 15496 /* reseting all divisors */ 15497 BCM_IF_ERROR_RETURN( 15498 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15499 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 15500 L1_CLK1_RECOVERY_DIV_CTRLf, 15501 0x0); 15502 BCM_IF_ERROR_RETURN( 15503 WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 15504 15505 #if defined(BCM_SABER2_SUPPORT) 15506 if (SOC_IS_SABER2(unit) && 15507 SOC_PORT_VALID(unit, 25)) { 15508 /* phy port 25 to 28 are eagle ports */ 15509 /* phy xe<port num> MAIN0_SYNCE_CTLr 0 */ 15510 uint32 phy_reg = 0x9002; 15511 int phy_addr = _bcm_switch_port_to_phyaddr(unit, 25); 15512 if (phy_addr == 0xff) { 15513 /* no phy address assigned */ 15514 return BCM_E_PARAM; 15515 } 15516 /* all lanes/ports clk divisor set to zero */ 15517 BCM_IF_ERROR_RETURN( 15518 soc_sbus_mdio_write(unit, phy_addr, phy_reg, 0)); 15519 } 15520 #endif 15521 } 15522 } else { 15523 return BCM_E_UNAVAIL; 15524 } 15525 15526 return BCM_E_NONE; 15527 } 15528 STATIC int 15529 _bcm_switch_div_ctrl_select_get(int unit, uint8 type, uint32 *val) 15530 { 15531 uint32 rval; 15532 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit)) { 15533 READ_CMIC_MISC_CONTROLr(unit, &rval); 15534 if (type) { /* primary (1) */ 15535 *val = soc_reg_field_get(unit, CMIC_MISC_CONTROLr, rval, 15536 L1_CLK0_RECOVERY_DIV_CTRLf); 15537 15538 } else { /* backup (0) */ 15539 *val = soc_reg_field_get(unit, CMIC_MISC_CONTROLr, rval, 15540 L1_CLK1_RECOVERY_DIV_CTRLf); 15541 } 15542 } else if (SOC_IS_KATANA(unit)) { 15543 BCM_IF_ERROR_RETURN( 15544 READ_TOP_MISC_CONTROLr(unit, &rval)); 15545 if (type) { /* primary (1) */ 15546 *val = soc_reg_field_get(unit, TOP_MISC_CONTROLr, rval, 15547 L1_CLK0_RECOVERY_DIV_CTRLf); 15548 } else { /* backup (0) */ 15549 *val = soc_reg_field_get(unit, TOP_MISC_CONTROLr, rval, 15550 L1_CLK1_RECOVERY_DIV_CTRLf); 15551 } 15552 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE2(unit) || 15553 SOC_IS_HURRICANE3(unit)) { 15554 BCM_IF_ERROR_RETURN( 15555 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 15556 if (type) { 15557 /* primary (1) */ 15558 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 15559 L1_RCVD_FREQ_SELf); 15560 } else { 15561 /* backup (0) */ 15562 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 15563 L1_RCVD_BKUP_FREQ_SELf); 15564 } 15565 } else if (SOC_IS_KATANA2(unit)) { 15566 BCM_IF_ERROR_RETURN( 15567 READ_TOP_MISC_CONTROL_0r(unit, &rval)); 15568 if (type) { /* primary (1) */ 15569 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_0r, rval, 15570 L1_CLK0_RECOVERY_DIV_CTRLf); 15571 } else { /* backup (0) */ 15572 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_0r, rval, 15573 L1_CLK1_RECOVERY_DIV_CTRLf); 15574 } 15575 } else { 15576 return BCM_E_UNAVAIL; 15577 } 15578 return BCM_E_NONE; 15579 } 15580 #endif 15581 15582 /* 15583 * Function: 15584 * bcmi_esw_l2x_freeze_mode_set 15585 * Description: 15586 * L2X freeze has different approaches with specific restrictions. 15587 * Approach can be changed by using this routine. 15588 * Parameters: 15589 * unit - (IN) Device number 15590 * arg - (IN) Mode to use 15591 * Return Value: 15592 * BCM_E_XXX 15593 */ 15594 STATIC int 15595 bcmi_esw_l2x_freeze_mode_set(int unit, int arg) 15596 { 15597 if ((arg != BCM_SWITCH_L2_FREEZE_MODE_PORT) && 15598 (arg != BCM_SWITCH_L2_FREEZE_MODE_GLOBAL)) { 15599 return BCM_E_PARAM; 15600 } 15601 15602 #ifdef BCM_TRIDENT2_SUPPORT 15603 if (SOC_IS_TD2_TT2(unit)) { 15604 return bcm_td2_l2x_freeze_mode_set(unit, arg); 15605 } else { 15606 return BCM_E_UNAVAIL; 15607 } 15608 #else 15609 return BCM_E_UNAVAIL; 15610 #endif /* BCM_TRIDENT2_SUPPORT */ 15611 } 15612 15613 /* 15614 * Function: 15615 * bcmi_esw_l2x_freeze_mode_get 15616 * Description: 15617 * L2X freeze has different approaches with specific restrictions. 15618 * Get current approach by using this routine. 15619 * Parameters: 15620 * unit - (IN) Device number 15621 * arg - (OUT) Mode in use 15622 * Return Value: 15623 * BCM_E_XXX 15624 */ 15625 STATIC int 15626 bcmi_esw_l2x_freeze_mode_get(int unit, int *arg) 15627 { 15628 if (arg == NULL) { 15629 return BCM_E_PARAM; 15630 } 15631 15632 #ifdef BCM_TRIDENT2_SUPPORT 15633 if (SOC_IS_TD2_TT2(unit)) { 15634 return bcm_td2_l2x_freeze_mode_get(unit, arg); 15635 } else { 15636 return BCM_E_UNAVAIL; 15637 } 15638 #else 15639 return BCM_E_UNAVAIL; 15640 #endif /* BCM_TRIDENT2_SUPPORT */ 15641 } 15642 15643 /* 15644 * Function: 15645 * bcm_esw_switch_control_port_proxy_validate 15646 * Description: 15647 * Checks that switch control is valid for a PROXY GPORT. 15648 * Resolves port to expected port value for the given port control type. 15649 * Parameters: 15650 * unit - (IN) Device number 15651 * port - (IN) Port to resolve 15652 * type - (IN) Switch control type 15653 * port_out - (OUT) Returns port (gport or BCM format) that 15654 * is expected for corresponding switch control type. 15655 * Return Value: 15656 * BCM_E_XXX 15657 */ 15658 STATIC int 15659 bcm_esw_switch_control_port_proxy_validate(int unit, bcm_port_t port, 15660 bcm_switch_control_t type, 15661 bcm_port_t *port_out) 15662 { 15663 int rv = BCM_E_PORT; 15664 int support = FALSE; 15665 15666 if (!soc_feature(unit, soc_feature_proxy_port_property)) { 15667 return BCM_E_PORT; 15668 } 15669 15670 switch(type) { 15671 case bcmSwitchModuleLoopback: 15672 case bcmSwitchTrunkHashSet0UnicastOffset: 15673 case bcmSwitchTrunkHashSet0NonUnicastOffset: 15674 case bcmSwitchTrunkFailoverHashOffset: 15675 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 15676 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 15677 case bcmSwitchFabricTrunkFailoverHashOffset: 15678 case bcmSwitchFabricTrunkDynamicHashOffset: 15679 case bcmSwitchTrunkDynamicHashOffset: 15680 case bcmSwitchEcmpDynamicHashOffset: 15681 case bcmSwitchFabricTrunkResilientHashOffset: 15682 case bcmSwitchTrunkResilientHashOffset: 15683 case bcmSwitchEcmpResilientHashOffset: 15684 case bcmSwitchECMPVxlanHashOffset: 15685 case bcmSwitchECMPUnderlayVxlanHashOffset: 15686 case bcmSwitchECMPL2GreHashOffset: 15687 case bcmSwitchECMPUnderlayL2GreHashOffset: 15688 case bcmSwitchECMPTrillHashOffset: 15689 case bcmSwitchECMPUnderlayTrillHashOffset: 15690 case bcmSwitchECMPMplsHashOffset: 15691 case bcmSwitchVirtualPortDynamicHashOffset: 15692 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 15693 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 15694 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 15695 case bcmSwitchECMPHashSet0Offset: 15696 case bcmSwitchECMPOverlayHashOffset: 15697 case bcmSwitchECMPUnderlayHashSet0Offset: 15698 case bcmSwitchEntropyHashSet0Offset: 15699 case bcmSwitchColorSelect: 15700 support = TRUE; 15701 break; 15702 default: 15703 support = FALSE; 15704 break; 15705 } 15706 15707 if (support) { 15708 *port_out = port; 15709 rv = BCM_E_NONE; 15710 } 15711 15712 return rv; 15713 } 15714 15715 /* 15716 * Function: 15717 * bcm_esw_switch_control_port_validate 15718 * Description: 15719 * Checks that port is valid and that control is supported 15720 * for the given port type. Resolves port to expected 15721 * port value for the given switch control type. 15722 * Current valid port types are: 15723 * GPORT PROXY 15724 * GPORT (various types) that resolves to local physical port 15725 * BCM port (non-gport) 15726 * Parameters: 15727 * unit - (IN) Device number 15728 * port - (IN) Port to resolve 15729 * type - (IN) Switch control type 15730 * port_out - (OUT) Returns port (gport or BCM format) that 15731 * is expected for corresponding switch control type. 15732 * Return Value: 15733 * BCM_E_XXX 15734 */ 15735 STATIC int 15736 bcm_esw_switch_control_port_validate(int unit, bcm_port_t port, 15737 bcm_switch_control_t type, 15738 bcm_port_t *port_out) 15739 { 15740 int rv = BCM_E_PORT; 15741 15742 if (BCM_GPORT_IS_PROXY(port)) { 15743 rv = bcm_esw_switch_control_port_proxy_validate(unit, port, 15744 type, port_out); 15745 } else { 15746 /* All other types are supported for valid physical local ports */ 15747 rv = _bcm_esw_switch_control_gport_resolve(unit, port, port_out); 15748 } 15749 15750 return rv; 15751 } 15752 15753 /* 15754 * Function: 15755 * bcm_switch_control_port_set 15756 * Description: 15757 * Specify general switch behaviors on a per-port basis. 15758 * Parameters: 15759 * unit - Device unit number 15760 * port - Port to affect 15761 * type - The desired configuration parameter to modify 15762 * arg - The value with which to set the parameter 15763 * Returns: 15764 * BCM_E_xxx 15765 */ 15766 15767 int 15768 bcm_esw_switch_control_port_set(int unit, 15769 bcm_port_t port, 15770 bcm_switch_control_t type, 15771 int arg) 15772 { 15773 #ifdef BCM_GREYHOUND2_SUPPORT 15774 if (SOC_IS_GREYHOUND2(unit)){ 15775 return bcm_gh2_switch_control_port_set( unit, port, 15776 type, arg); 15777 } 15778 #endif /* BCM_GREYHOUND2_SUPPORT */ 15779 15780 #ifdef BCM_SHADOW_SUPPORT 15781 if (SOC_IS_SHADOW(unit)) { 15782 return BCM_E_UNAVAIL; 15783 } 15784 #endif /* BCM_SHADOW_SUPPORT */ 15785 if ((type == bcmSwitchFailoverStackTrunk) || 15786 (type == bcmSwitchFailoverEtherTrunk)) { 15787 return BCM_E_UNAVAIL; 15788 } 15789 15790 #if defined(BCM_HGPROXY_COE_SUPPORT) 15791 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 15792 BCM_GPORT_IS_SET(port) && 15793 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port)) { 15794 /*Gport is used for CoE configirations 15795 *So, do not resolve it. 15796 */ 15797 } else 15798 #endif 15799 if (BCM_GPORT_IS_SET(port)) { 15800 BCM_IF_ERROR_RETURN 15801 (bcm_esw_switch_control_port_validate(unit, port, type, &port)); 15802 } 15803 15804 #ifdef BCM_XGS3_SWITCH_SUPPORT 15805 if (SOC_IS_XGS3_SWITCH(unit)) { 15806 uint64 oval64, val64; 15807 int i, found; 15808 15809 switch(type) { 15810 case bcmSwitchPktAge: 15811 #ifdef BCM_KATANA_SUPPORT 15812 if (SOC_IS_KATANAX(unit)) { 15813 return _bcm_kt_pkt_age_set(unit, arg); 15814 } else 15815 #endif 15816 #ifdef BCM_TRX_SUPPORT 15817 if (SOC_IS_TRX(unit) && !SOC_IS_HURRICANEX(unit) && 15818 !SOC_IS_GREYHOUND(unit) && 15819 !SOC_IS_TOMAHAWKX(unit)) { 15820 return _bcm_ts_pkt_age_set(unit, arg); 15821 } else 15822 #endif 15823 if (SOC_IS_FBX(unit) && !SOC_IS_TOMAHAWKX(unit)) { 15824 return _bcm_fb_pkt_age_set(unit, arg); 15825 } 15826 return BCM_E_UNAVAIL; 15827 break; 15828 case bcmSwitchHashL2: 15829 case bcmSwitchHashL3: 15830 case bcmSwitchHashMultipath: 15831 case bcmSwitchHashIpfixIngress: 15832 case bcmSwitchHashIpfixEgress: 15833 case bcmSwitchHashIpfixIngressDual: 15834 case bcmSwitchHashIpfixEgressDual: 15835 case bcmSwitchHashVlanTranslate: 15836 case bcmSwitchHashMPLS: 15837 #if defined(BCM_TRIUMPH3_SUPPORT) 15838 case bcmSwitchHashWlanPort: 15839 case bcmSwitchHashWlanPortDual: 15840 case bcmSwitchHashWlanClient: 15841 case bcmSwitchHashWlanClientDual: 15842 case bcmSwitchHashRegexAction: 15843 case bcmSwitchHashRegexActionDual: 15844 #endif 15845 #ifdef BCM_TRIDENT2_SUPPORT 15846 case bcmSwitchHashL3DNATPool: 15847 case bcmSwitchHashL3DNATPoolDual: 15848 case bcmSwitchHashVpVlanMemberIngress: 15849 case bcmSwitchHashVpVlanMemberIngressDual: 15850 case bcmSwitchHashVpVlanMemberEgress: 15851 case bcmSwitchHashVpVlanMemberEgressDual: 15852 case bcmSwitchHashL2Endpoint: 15853 case bcmSwitchHashL2EndpointDual: 15854 case bcmSwitchHashEndpointQueueMap: 15855 case bcmSwitchHashEndpointQueueMapDual: 15856 #endif 15857 return _bcm_fb_er_hashselect_set(unit, type, arg); 15858 break; 15859 case bcmSwitchHashControl: 15860 return _bcm_xgs3_hashcontrol_set(unit, arg); 15861 break; 15862 #if defined(BCM_TRIUMPH_SUPPORT) 15863 case bcmSwitchFieldMultipathHashSelect: 15864 return _bcm_field_tr_multipath_hashcontrol_set(unit, arg); 15865 break; 15866 case bcmSwitchL3UrpfRouteEnableExternal: 15867 #if defined(BCM_ENDURO_SUPPORT) 15868 if(SOC_IS_ENDURO(unit) || SOC_IS_HURRICANEX(unit)) { 15869 return BCM_E_UNAVAIL; 15870 } 15871 #endif /* BCM_ENDURO_SUPPORT */ 15872 if ((soc_feature(unit, soc_feature_urpf)) && (soc_feature(unit, soc_feature_esm_support))) { 15873 return _bcm_xgs3_urpf_route_enable_external(unit, arg); 15874 } 15875 return BCM_E_UNAVAIL; 15876 break; 15877 15878 case bcmSwitchL3IngressMode: 15879 #ifdef INCLUDE_L3 15880 if ((soc_feature(unit, soc_feature_l3)) && (soc_feature(unit,soc_feature_l3_ingress_interface))) { 15881 return bcm_xgs3_l3_ingress_mode_set(unit, arg); 15882 } 15883 #endif /* INCLUDE_L3 */ 15884 return BCM_E_UNAVAIL; 15885 break; 15886 case bcmSwitchL3IngressInterfaceMapSet: 15887 #ifdef INCLUDE_L3 15888 if ((soc_feature(unit, soc_feature_l3)) && (soc_feature(unit,soc_feature_l3_ingress_interface))) { 15889 return bcm_xgs3_l3_ingress_intf_map_set(unit, arg); 15890 } 15891 #endif /* INCLUDE_L3 */ 15892 return BCM_E_UNAVAIL; 15893 break; 15894 15895 #endif /* BCM_TRIUMPH_SUPPORT */ 15896 case bcmSwitchColorSelect: 15897 return _bcm_fb_er_color_mode_set(unit, port, arg); 15898 break; 15899 case bcmSwitchModuleLoopback: 15900 return _bcm_fb_mod_lb_set(unit, port, arg); 15901 break; 15902 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) \ 15903 || defined(BCM_SCORPION_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 15904 case bcmSwitchIngressRateLimitIncludeIFG: 15905 return _bcm_xgs3_ing_rate_limit_ifg_set(unit, port, arg); 15906 break; 15907 #endif /* BCM_RAPTOR_SUPPORT || BCM_FIREBOLT2_SUPPORT || BCM_HURRICANE_SUPPORT || BCM_SCORPION_SUPPORT */ 15908 case bcmSwitchVrfMax: 15909 #if defined(BCM_HAWKEYE_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) 15910 if (SOC_IS_HAWKEYE(unit) || SOC_IS_HURRICANEX(unit) || 15911 SOC_IS_GREYHOUND(unit)) { 15912 return BCM_E_UNAVAIL; 15913 } 15914 #endif /* BCM_HAWKEYE_SUPPORT || BCM_HURRICANE_SUPPORT */ 15915 return soc_max_vrf_set(unit, arg); 15916 break; 15917 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 15918 case bcmSwitchL3UrpfRouteEnable: 15919 if (soc_feature(unit, soc_feature_urpf)) { 15920 /* 15921 * Saber - 56246 has only 2 L3_DEFIP tcams 15922 * Both IPV6 and RPF cannot be supported 15923 * on this device. 15924 */ 15925 if (soc_feature(unit, soc_feature_l3_max_2_defip_tcams)) { 15926 if (soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 0)) { 15927 LOG_ERROR(BSL_LS_BCM_COMMON, 15928 (BSL_META_U(unit, 15929 "Cannot enable IPV6 and URPF " 15930 "only 2 L3_DEFIP tcams present\n"))); 15931 return BCM_E_CONFIG; 15932 } 15933 } 15934 return _bcm_xgs3_urpf_route_enable(unit, arg); 15935 } 15936 return BCM_E_UNAVAIL; 15937 break; 15938 case bcmSwitchL3UrpfMode: 15939 if (soc_feature(unit, soc_feature_urpf)) { 15940 return _bcm_xgs3_urpf_port_mode_set(unit, port, arg); 15941 } 15942 return BCM_E_UNAVAIL; 15943 break; 15944 case bcmSwitchL3UrpfDefaultRoute: 15945 if (soc_feature(unit, soc_feature_urpf)) { 15946 return _bcm_xgs3_urpf_def_gw_enable(unit, port, arg); 15947 } 15948 return BCM_E_UNAVAIL; 15949 break; 15950 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 15951 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 15952 defined(BCM_TRX_SUPPORT) 15953 case bcmSwitchHashL2Dual: 15954 case bcmSwitchHashL3Dual: 15955 case bcmSwitchHashVlanTranslateDual: 15956 case bcmSwitchHashEgressVlanTranslate: 15957 case bcmSwitchHashEgressVlanTranslateDual: 15958 case bcmSwitchHashMPLSDual: 15959 if (soc_feature(unit, soc_feature_dual_hash)) { 15960 return _bcm_fb_er_hashselect_set(unit, type, arg); 15961 } 15962 return BCM_E_UNAVAIL; 15963 break; 15964 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 15965 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRIUMPH_SUPPORT) 15966 case bcmSwitchHashSelectControl: 15967 if (SOC_IS_KATANA2(unit)) { 15968 return _bcm_kt2_selectcontrol_set(unit,arg); 15969 } else if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit)) { 15970 return _bcm_xgs3_selectcontrol_set(unit, arg); 15971 } 15972 return BCM_E_UNAVAIL; 15973 break; 15974 case bcmSwitchHashIP4Field0: 15975 case bcmSwitchHashIP4Field1: 15976 case bcmSwitchHashIP6Field0: 15977 case bcmSwitchHashIP6Field1: 15978 case bcmSwitchHashL2Field0: 15979 case bcmSwitchHashL2Field1: 15980 case bcmSwitchHashMPLSField0: 15981 case bcmSwitchHashMPLSField1: 15982 case bcmSwitchHashHG2UnknownField0: 15983 case bcmSwitchHashHG2UnknownField1: 15984 #ifdef BCM_TOMAHAWK3_SUPPORT 15985 if ((type == bcmSwitchHashHG2UnknownField0 || 15986 type == bcmSwitchHashHG2UnknownField1) && 15987 SOC_IS_TOMAHAWK3(unit)) { 15988 return BCM_E_UNAVAIL; 15989 } 15990 #endif 15991 15992 if ((type == bcmSwitchHashMPLSField0 || type == bcmSwitchHashMPLSField1) 15993 && (SOC_IS_ENDURO(unit) || SOC_IS_TRIUMPH2(unit) || 15994 SOC_IS_APOLLO(unit) || SOC_IS_VALKYRIE2(unit) || 15995 SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 15996 SOC_IS_KATANAX(unit))) { 15997 return BCM_E_UNAVAIL; 15998 } 15999 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit)) { 16000 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16001 } 16002 return BCM_E_UNAVAIL; 16003 break; 16004 #ifdef BCM_TRIUMPH2_SUPPORT 16005 case bcmSwitchHashL2MPLSField0: 16006 case bcmSwitchHashL2MPLSField1: 16007 #ifdef BCM_TOMAHAWK3_SUPPORT 16008 if (SOC_IS_TOMAHAWK3(unit)) { 16009 return BCM_E_UNAVAIL; 16010 } 16011 #endif 16012 case bcmSwitchHashMIMTunnelField0: 16013 case bcmSwitchHashMIMTunnelField1: 16014 case bcmSwitchHashMIMField0: 16015 case bcmSwitchHashMIMField1: 16016 #ifdef BCM_TOMAHAWK3_SUPPORT 16017 if (SOC_IS_TOMAHAWK3(unit)) { 16018 return BCM_E_UNAVAIL; 16019 } 16020 #endif 16021 case bcmSwitchHashL3MPLSField0: 16022 case bcmSwitchHashL3MPLSField1: 16023 case bcmSwitchHashMPLSTunnelField0: 16024 case bcmSwitchHashMPLSTunnelField1: 16025 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 16026 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) || 16027 SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 16028 SOC_IS_KATANAX(unit)) { 16029 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16030 } 16031 return BCM_E_UNAVAIL; 16032 break; 16033 #endif 16034 case bcmSwitchHashL3MiMField0: 16035 case bcmSwitchHashL3MiMField1: 16036 #if defined(BCM_TOMAHAWK3_SUPPORT) 16037 if (SOC_IS_TOMAHAWK3(unit)) { 16038 return BCM_E_UNAVAIL; 16039 } 16040 #endif 16041 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_KATANA2_SUPPORT) \ 16042 || defined(BCM_TOMAHAWK_SUPPORT) 16043 if (SOC_IS_TD2_TT2(unit) || SOC_IS_KATANA2(unit)) { 16044 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16045 } 16046 #endif /* BCM_TRIDENT2_SUPPORT */ 16047 return BCM_E_UNAVAIL; 16048 break; 16049 case bcmSwitchHashL3L2MPLSField0: 16050 case bcmSwitchHashL3L2MPLSField1: 16051 #if defined(BCM_TOMAHAWK3_SUPPORT) 16052 if (SOC_IS_TOMAHAWK3(unit)) { 16053 return BCM_E_UNAVAIL; 16054 } 16055 #endif 16056 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 16057 || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 16058 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 16059 SOC_IS_HELIX4(unit) || SOC_IS_KATANA2(unit)) { 16060 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16061 } 16062 #endif /* BCM_TRIDENT2_SUPPORT */ 16063 return BCM_E_UNAVAIL; 16064 break; 16065 case bcmSwitchHashL2VxlanField0: 16066 case bcmSwitchHashL2VxlanField1: 16067 case bcmSwitchHashL3VxlanField0: 16068 case bcmSwitchHashL3VxlanField1: 16069 #if defined(BCM_TRIDENT2_SUPPORT) 16070 if (SOC_IS_TD2_TT2(unit) && 16071 (soc_feature(unit, soc_feature_vxlan) || 16072 soc_feature(unit, soc_feature_flex_flow))) { 16073 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16074 } 16075 #endif 16076 return BCM_E_UNAVAIL; 16077 break; 16078 16079 case bcmSwitchHashL2L2GreField0: 16080 case bcmSwitchHashL2L2GreField1: 16081 case bcmSwitchHashL3L2GreField0: 16082 case bcmSwitchHashL3L2GreField1: 16083 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 16084 if (((SOC_IS_TD2_TT2(unit) || SOC_IS_TRIUMPH3(unit)) && 16085 soc_feature(unit, soc_feature_l2gre)) 16086 #if defined(BCM_TRIDENT3_SUPPORT) 16087 || soc_feature(unit, soc_feature_flex_flow) 16088 #endif 16089 ) { 16090 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16091 } 16092 #endif 16093 return BCM_E_UNAVAIL; 16094 break; 16095 16096 #ifdef BCM_TRIDENT_SUPPORT 16097 case bcmSwitchHashFCOEField0: 16098 case bcmSwitchHashFCOEField1: 16099 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) { 16100 /* If FCOE is supported, set the control */ 16101 if (soc_feature(unit, soc_feature_fcoe) || 16102 soc_feature(unit, soc_feature_hash_fcoe_field)) { 16103 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16104 } 16105 } 16106 return BCM_E_UNAVAIL; 16107 break; 16108 case bcmSwitchHashL2TrillField0: 16109 case bcmSwitchHashL2TrillField1: 16110 case bcmSwitchHashL3TrillField0: 16111 case bcmSwitchHashL3TrillField1: 16112 case bcmSwitchHashTrillTunnelField0: 16113 case bcmSwitchHashTrillTunnelField1: 16114 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) { 16115 #ifdef BCM_TOMAHAWK3_SUPPORT 16116 if (SOC_IS_TOMAHAWK3(unit)) { 16117 return BCM_E_UNAVAIL; 16118 } 16119 #endif 16120 if (SOC_IS_TRIDENT3X(unit)) { 16121 return BCM_E_UNAVAIL; 16122 } 16123 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16124 } 16125 return BCM_E_UNAVAIL; 16126 break; 16127 #endif /* BCM_TRIDENT_SUPPORT */ 16128 #if defined(BCM_TRIDENT_SUPPORT) 16129 case bcmSwitchHashIP4TcpUdpField0: 16130 case bcmSwitchHashIP4TcpUdpField1: 16131 case bcmSwitchHashIP4TcpUdpPortsEqualField0: 16132 case bcmSwitchHashIP4TcpUdpPortsEqualField1: 16133 case bcmSwitchHashIP6TcpUdpField0: 16134 case bcmSwitchHashIP6TcpUdpField1: 16135 case bcmSwitchHashIP6TcpUdpPortsEqualField0: 16136 case bcmSwitchHashIP6TcpUdpPortsEqualField1: 16137 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 16138 SOC_IS_KATANAX(unit)) { 16139 return _bcm_xgs3_fieldselect_set(unit, type, arg); 16140 } 16141 return BCM_E_UNAVAIL; 16142 break; 16143 case bcmSwitchHashField0PreProcessEnable: 16144 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 16145 if (SOC_IS_TOMAHAWK2(unit) || SOC_IS_TOMAHAWK3(unit)) { 16146 return (soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_3_64r, 16147 REG_PORT_ANY, HASH_PRE_PROCESSING_ENABLE_Af, arg)); 16148 } else 16149 #endif 16150 if (SOC_IS_TD_TT(unit) || SOC_IS_KATANAX(unit) || 16151 SOC_IS_TRIUMPH3(unit)) { 16152 return (soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_3r, 16153 REG_PORT_ANY, HASH_PRE_PROCESSING_ENABLE_Af, arg)); 16154 } 16155 return BCM_E_UNAVAIL; 16156 break; 16157 case bcmSwitchHashField1PreProcessEnable: 16158 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 16159 if (SOC_IS_TOMAHAWK2(unit) || SOC_IS_TOMAHAWK3(unit)) { 16160 return (soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_3_64r, 16161 REG_PORT_ANY, HASH_PRE_PROCESSING_ENABLE_Bf, arg)); 16162 } else 16163 #endif 16164 if (SOC_IS_TD_TT(unit) || SOC_IS_KATANAX(unit) || 16165 SOC_IS_TRIUMPH3(unit)) { 16166 return (soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_3r, 16167 REG_PORT_ANY, HASH_PRE_PROCESSING_ENABLE_Bf, arg)); 16168 } 16169 return BCM_E_UNAVAIL; 16170 break; 16171 #endif /* BCM_TRIDENT_SUPPORT */ 16172 16173 case bcmSwitchHashField0Config: 16174 case bcmSwitchHashField0Config1: 16175 case bcmSwitchHashField1Config: 16176 case bcmSwitchHashField1Config1: 16177 case bcmSwitchMacroFlowHashFieldConfig: 16178 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit) || 16179 SOC_IS_TD_TT(unit) || SOC_IS_TR_VL(unit) ) { 16180 return _bcm_xgs3_fieldconfig_set(unit, type, arg); 16181 } 16182 return BCM_E_UNAVAIL; 16183 break; 16184 16185 case bcmSwitchTrunkHashSet1UnicastOffset: 16186 case bcmSwitchTrunkHashSet1NonUnicastOffset: 16187 case bcmSwitchFabricTrunkHashSet1UnicastOffset: 16188 case bcmSwitchFabricTrunkHashSet1NonUnicastOffset: 16189 case bcmSwitchLoadBalanceHashSet1UnicastOffset: 16190 case bcmSwitchLoadBalanceHashSet1NonUnicastOffset: 16191 case bcmSwitchECMPHashSet1Offset: 16192 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 16193 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 16194 /* Previous devices had two hash config sets(Set0 & Set1), 16195 * which each port can select. 16196 * In Triumph3 each port can be configured with its 16197 * own hash configs. 16198 */ 16199 return BCM_E_UNAVAIL; 16200 } else 16201 #endif /* BCM_TRIUMPH3_SUPPORT */ 16202 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit) || 16203 SOC_IS_TD_TT(unit) || SOC_IS_TR_VL(unit)) { 16204 return _bcm_xgs3_fieldoffset_set(unit, port, type, arg); 16205 } 16206 return BCM_E_UNAVAIL; 16207 break; 16208 case bcmSwitchTrunkHashSet0UnicastOffset: 16209 case bcmSwitchTrunkHashSet0NonUnicastOffset: 16210 case bcmSwitchTrunkFailoverHashOffset: 16211 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 16212 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 16213 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 16214 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 16215 case bcmSwitchFabricTrunkFailoverHashOffset: 16216 case bcmSwitchFabricTrunkDynamicHashOffset: 16217 case bcmSwitchTrunkDynamicHashOffset: 16218 case bcmSwitchEcmpDynamicHashOffset: 16219 case bcmSwitchFabricTrunkResilientHashOffset: 16220 case bcmSwitchTrunkResilientHashOffset: 16221 case bcmSwitchEcmpResilientHashOffset: 16222 case bcmSwitchECMPHashSet0Offset: 16223 case bcmSwitchECMPUnderlayHashSet0Offset: 16224 case bcmSwitchECMPVxlanHashOffset: 16225 case bcmSwitchECMPUnderlayVxlanHashOffset: 16226 case bcmSwitchECMPL2GreHashOffset: 16227 case bcmSwitchECMPUnderlayL2GreHashOffset: 16228 case bcmSwitchECMPTrillHashOffset: 16229 case bcmSwitchECMPUnderlayTrillHashOffset: 16230 case bcmSwitchECMPMplsHashOffset: 16231 case bcmSwitchVirtualPortDynamicHashOffset: 16232 case bcmSwitchECMPOverlayHashOffset: 16233 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 16234 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit) || 16235 SOC_IS_TD_TT(unit) || SOC_IS_TR_VL(unit)) { 16236 return _bcm_xgs3_fieldoffset_set(unit, port, type, arg); 16237 } 16238 return BCM_E_UNAVAIL; 16239 break; 16240 #endif /* BCM_BRADLEY_SUPPORT || BCM_TRIUMPH_SUPPORT */ 16241 #ifdef BCM_TRIUMPH2_SUPPORT 16242 case bcmSwitchArpReplyToCpu: 16243 case bcmSwitchArpReplyDrop: 16244 case bcmSwitchArpRequestToCpu: 16245 case bcmSwitchArpRequestDrop: 16246 case bcmSwitchNdPktToCpu: 16247 case bcmSwitchNdPktDrop: 16248 case bcmSwitchDhcpPktToCpu: 16249 case bcmSwitchDhcpPktDrop: 16250 if (SOC_REG_INFO(unit, PROTOCOL_PKT_CONTROLr).regtype != 16251 soc_portreg) { 16252 return _bcm_tr2_prot_pkt_action_set(unit, port, type, arg); 16253 } 16254 break; 16255 #endif /* BCM_TRIUMPH2_SUPPORT */ 16256 case bcmSwitchIgmpPktToCpu: 16257 case bcmSwitchIgmpPktDrop: 16258 case bcmSwitchMldPktToCpu: 16259 case bcmSwitchMldPktDrop: 16260 case bcmSwitchV4ResvdMcPktToCpu: 16261 case bcmSwitchV4ResvdMcPktFlood: 16262 case bcmSwitchV4ResvdMcPktDrop: 16263 case bcmSwitchV6ResvdMcPktToCpu: 16264 case bcmSwitchV6ResvdMcPktFlood: 16265 case bcmSwitchV6ResvdMcPktDrop: 16266 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 16267 defined (BCM_TRX_SUPPORT) 16268 case bcmSwitchIgmpReportLeaveDrop: 16269 case bcmSwitchIgmpReportLeaveFlood: 16270 case bcmSwitchIgmpReportLeaveToCpu: 16271 case bcmSwitchIgmpQueryDrop: 16272 case bcmSwitchIgmpQueryFlood: 16273 case bcmSwitchIgmpQueryToCpu: 16274 case bcmSwitchIgmpUnknownDrop: 16275 case bcmSwitchIgmpUnknownFlood: 16276 case bcmSwitchIgmpUnknownToCpu: 16277 case bcmSwitchMldReportDoneDrop: 16278 case bcmSwitchMldReportDoneFlood: 16279 case bcmSwitchMldReportDoneToCpu: 16280 case bcmSwitchMldQueryDrop: 16281 case bcmSwitchMldQueryFlood: 16282 case bcmSwitchMldQueryToCpu: 16283 case bcmSwitchIpmcV4RouterDiscoveryDrop: 16284 case bcmSwitchIpmcV4RouterDiscoveryFlood: 16285 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 16286 case bcmSwitchIpmcV6RouterDiscoveryDrop: 16287 case bcmSwitchIpmcV6RouterDiscoveryFlood: 16288 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 16289 #endif /* defined(BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || 16290 defined(BCM_TRX_SUPPORT) */ 16291 return _bcm_xgs3_igmp_action_set(unit, port, type, arg); 16292 break; 16293 16294 case bcmSwitchDirectedMirroring: 16295 if (!soc_feature(unit, soc_feature_xgs1_mirror)) { 16296 /* Directed mirroring cannot be turned off */ 16297 return (arg == 0) ? BCM_E_PARAM : BCM_E_NONE; 16298 } 16299 break; 16300 16301 case bcmSwitchFlexibleMirrorDestinations: 16302 return _bcm_esw_mirror_flexible_set(unit, arg); 16303 16304 case bcmSwitchMirrorExclusive: 16305 return _bcm_esw_mirror_exclusive_set(unit, arg); 16306 16307 case bcmSwitchL3EgressMode: 16308 #ifdef INCLUDE_L3 16309 if (soc_feature(unit, soc_feature_l3)) { 16310 return bcm_xgs3_l3_egress_mode_set(unit, arg); 16311 } 16312 #endif /* INCLUDE_L3 */ 16313 return BCM_E_UNAVAIL; 16314 break; 16315 16316 case bcmSwitchL3HostAsRouteReturnValue: 16317 #ifdef INCLUDE_L3 16318 if (soc_feature(unit, soc_feature_l3)) { 16319 return bcm_xgs3_l3_host_as_route_return_set(unit, arg); 16320 } 16321 #endif /* INCLUDE_L3 */ 16322 return BCM_E_UNAVAIL; 16323 break; 16324 16325 case bcmSwitchL3DefipMultipathCountUpdate: 16326 #ifdef INCLUDE_L3 16327 if(soc_feature(unit, soc_feature_l3_defip_ecmp_count)) { 16328 return _bcm_xgs3_l3_multipathCountUpdate(unit, arg); 16329 } 16330 #endif /* INCLUDE_L3 */ 16331 return BCM_E_UNAVAIL; 16332 break; 16333 case bcmSwitchIpmcReplicationSharing: 16334 #ifdef INCLUDE_L3 16335 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 16336 SOC_IPMCREPLSHR_SET(unit, arg); 16337 #ifdef BCM_WARM_BOOT_SUPPORT 16338 { 16339 int rv; 16340 /* Record this value in HW for Warm Boot recovery. */ 16341 rv = _bcm_esw_ipmc_repl_wb_flags_set(unit, 16342 (arg ? _BCM_IPMC_WB_REPL_LIST : 0), 16343 _BCM_IPMC_WB_REPL_LIST); 16344 if (BCM_FAILURE(rv) && (BCM_E_UNAVAIL != rv)) { 16345 return rv; 16346 } 16347 } 16348 #endif /* BCM_WARM_BOOT_SUPPORT */ 16349 return BCM_E_NONE; 16350 } 16351 #endif /* INCLUDE_L3 */ 16352 return BCM_E_UNAVAIL; 16353 break; 16354 case bcmSwitchIpmcReplicationAvailabilityThreshold: 16355 #ifdef INCLUDE_L3 16356 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 16357 return _bcm_esw_ipmc_repl_threshold_set(unit, arg); 16358 } 16359 #endif /* INCLUDE_L3 */ 16360 return BCM_E_UNAVAIL; 16361 break; 16362 case bcmSwitchHashDualMoveDepth: 16363 if (soc_feature(unit, soc_feature_dual_hash)) { 16364 if (arg >= 0) { 16365 SOC_DUAL_HASH_MOVE_MAX(unit) = arg; 16366 return BCM_E_NONE; 16367 } else { 16368 return BCM_E_PARAM; 16369 } 16370 } 16371 return BCM_E_UNAVAIL; 16372 break; 16373 case bcmSwitchHashDualMoveDepthL2: 16374 if (soc_feature(unit, soc_feature_dual_hash)) { 16375 if (arg >= 0) { 16376 SOC_DUAL_HASH_MOVE_MAX_L2X(unit) = arg; 16377 return BCM_E_NONE; 16378 } else { 16379 return BCM_E_PARAM; 16380 } 16381 } 16382 return BCM_E_UNAVAIL; 16383 break; 16384 case bcmSwitchHashDualMoveDepthMpls: 16385 if (soc_feature(unit, soc_feature_dual_hash)) { 16386 if (arg >= 0) { 16387 SOC_DUAL_HASH_MOVE_MAX_MPLS(unit) = arg; 16388 return BCM_E_NONE; 16389 } else { 16390 return BCM_E_PARAM; 16391 } 16392 } 16393 return BCM_E_UNAVAIL; 16394 break; 16395 case bcmSwitchHashDualMoveDepthVlan: 16396 if (soc_feature(unit, soc_feature_dual_hash)) { 16397 if (arg >= 0) { 16398 SOC_DUAL_HASH_MOVE_MAX_VLAN(unit) = arg; 16399 return BCM_E_NONE; 16400 } else { 16401 return BCM_E_PARAM; 16402 } 16403 } 16404 return BCM_E_UNAVAIL; 16405 break; 16406 case bcmSwitchHashDualMoveDepthEgressVlan: 16407 if (soc_feature(unit, soc_feature_dual_hash)) { 16408 if (arg >= 0) { 16409 SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit) = arg; 16410 return BCM_E_NONE; 16411 } else { 16412 return BCM_E_PARAM; 16413 } 16414 } 16415 return BCM_E_UNAVAIL; 16416 break; 16417 case bcmSwitchHashDualMoveDepthIngVpVlanMember: 16418 if (soc_feature(unit, soc_feature_dual_hash)) { 16419 if (arg >= 0) { 16420 SOC_DUAL_HASH_MOVE_MAX_ING_VP_VLAN_MEMBER(unit) = arg; 16421 return BCM_E_NONE; 16422 } else { 16423 return BCM_E_PARAM; 16424 } 16425 } 16426 return BCM_E_UNAVAIL; 16427 break; 16428 case bcmSwitchHashDualMoveDepthEgrVpVlanMember: 16429 if (soc_feature(unit, soc_feature_dual_hash)) { 16430 if (arg >= 0) { 16431 SOC_DUAL_HASH_MOVE_MAX_EGR_VP_VLAN_MEMBER(unit) = arg; 16432 return BCM_E_NONE; 16433 } else { 16434 return BCM_E_PARAM; 16435 } 16436 } 16437 return BCM_E_UNAVAIL; 16438 break; 16439 #if defined(INCLUDE_L3) 16440 case bcmSwitchHashDualMoveDepthL3: 16441 if (soc_feature(unit, soc_feature_dual_hash)) { 16442 if (arg >= 0) { 16443 SOC_DUAL_HASH_MOVE_MAX_L3X(unit) = arg; 16444 return BCM_E_NONE; 16445 } else { 16446 return BCM_E_PARAM; 16447 } 16448 } 16449 return BCM_E_UNAVAIL; 16450 break; 16451 #endif 16452 #if defined(BCM_TRIUMPH3_SUPPORT) 16453 case bcmSwitchHashDualMoveDepthWlanPort: 16454 if (soc_feature(unit, soc_feature_dual_hash)) { 16455 if (arg >= 0) { 16456 SOC_DUAL_HASH_MOVE_MAX_WLAN_PORT(unit) = arg; 16457 return BCM_E_NONE; 16458 } else { 16459 return BCM_E_PARAM; 16460 } 16461 } 16462 return BCM_E_UNAVAIL; 16463 break; 16464 case bcmSwitchHashDualMoveDepthWlanClient: 16465 if (soc_feature(unit, soc_feature_dual_hash)) { 16466 if (arg >= 0) { 16467 SOC_DUAL_HASH_MOVE_MAX_WLAN_CLIENT(unit) = arg; 16468 return BCM_E_NONE; 16469 } else { 16470 return BCM_E_PARAM; 16471 } 16472 } 16473 return BCM_E_UNAVAIL; 16474 break; 16475 #endif 16476 case bcmSwitchL2PortBlocking: 16477 if (soc_feature(unit, soc_feature_src_mac_group)) { 16478 SOC_L2X_GROUP_ENABLE_SET(unit, _bool_invert(unit, arg, 0)); 16479 return BCM_E_NONE; 16480 } 16481 return BCM_E_UNAVAIL; 16482 break; 16483 #if defined(BCM_HAWKEYE_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) 16484 case bcmSwitchTimeSyncPktDrop: 16485 case bcmSwitchTimeSyncPktFlood: 16486 case bcmSwitchTimeSyncPktToCpu: 16487 case bcmSwitchMmrpPktDrop: 16488 case bcmSwitchMmrpPktFlood: 16489 case bcmSwitchMmrpPktToCpu: 16490 case bcmSwitchSrpPktDrop: 16491 case bcmSwitchSrpPktFlood: 16492 case bcmSwitchSrpPktToCpu: 16493 return _bcm_xgs3_eav_action_set(unit, port, type, arg); 16494 break; 16495 case bcmSwitchSRPEthertype: 16496 case bcmSwitchMMRPEthertype: 16497 case bcmSwitchTimeSyncEthertype: 16498 return _bcm_xgs3_switch_ethertype_set(unit, port, type, arg); 16499 break; 16500 case bcmSwitchSRPDestMacOui: 16501 case bcmSwitchMMRPDestMacOui: 16502 case bcmSwitchTimeSyncDestMacOui: 16503 return _bcm_xgs3_switch_mac_hi_set(unit, port, type, arg); 16504 break; 16505 case bcmSwitchSRPDestMacNonOui: 16506 case bcmSwitchMMRPDestMacNonOui: 16507 case bcmSwitchTimeSyncDestMacNonOui: 16508 return _bcm_xgs3_switch_mac_lo_set(unit, port, type, arg); 16509 break; 16510 case bcmSwitchTimeSyncMessageTypeBitmap: 16511 if (soc_reg_field_valid(unit, TS_CONTROLr, TS_MSG_BITMAPf)) { 16512 return soc_reg_field32_modify(unit, TS_CONTROLr, port, 16513 TS_MSG_BITMAPf, arg); 16514 } else { 16515 return BCM_E_UNAVAIL; 16516 } 16517 break; 16518 case bcmSwitchTimeSyncClassAPktPrio: 16519 case bcmSwitchTimeSyncClassBPktPrio: 16520 case bcmSwitchTimeSyncClassAExeptionPktPrio: 16521 case bcmSwitchTimeSyncClassBExeptionPktPrio: 16522 return _bcm_switch_class_pkt_prio_set(unit, type, arg); 16523 break; 16524 16525 #endif /* defined(BCM_HAWKEYE_SUPPORT)*/ 16526 #if defined(BCM_TRIUMPH2_SUPPORT) 16527 case bcmSwitchUnknownVlanToCpu: 16528 case bcmSwitchL3HeaderErrToCpu: 16529 case bcmSwitchIpmcTtlErrToCpu: 16530 case bcmSwitchHgHdrErrToCpu: 16531 case bcmSwitchTunnelErrToCpu: 16532 if (SOC_REG_IS_VALID(unit, EGR_CPU_CONTROLr) && 16533 soc_feature(unit, soc_feature_internal_loopback)) { 16534 BCM_IF_ERROR_RETURN( 16535 _bcm_tr2_ep_redirect_action_set(unit, port, type, arg)); 16536 } 16537 break; 16538 case bcmSwitchStgInvalidToCpu: 16539 case bcmSwitchVlanTranslateEgressMissToCpu: 16540 case bcmSwitchL3PktErrToCpu: 16541 case bcmSwitchMtuFailureToCpu: 16542 case bcmSwitchSrcKnockoutToCpu: 16543 return _bcm_tr2_ep_redirect_action_set(unit, port, type, arg); 16544 break; 16545 case bcmSwitchWlanTunnelMismatchToCpu: 16546 case bcmSwitchWlanTunnelMismatchDrop: 16547 case bcmSwitchWlanPortMissToCpu: 16548 if (soc_feature(unit, soc_feature_wlan)) { 16549 return _bcm_tr2_ep_redirect_action_set(unit, port, type, arg); 16550 } 16551 break; 16552 case bcmSwitchUnknownVlanToCpuCosq: 16553 case bcmSwitchStgInvalidToCpuCosq: 16554 case bcmSwitchVlanTranslateEgressMissToCpuCosq: 16555 case bcmSwitchTunnelErrToCpuCosq: 16556 case bcmSwitchL3HeaderErrToCpuCosq: 16557 case bcmSwitchL3PktErrToCpuCosq: 16558 case bcmSwitchIpmcTtlErrToCpuCosq: 16559 case bcmSwitchMtuFailureToCpuCosq: 16560 case bcmSwitchHgHdrErrToCpuCosq: 16561 case bcmSwitchSrcKnockoutToCpuCosq: 16562 case bcmSwitchWlanTunnelMismatchToCpuCosq: 16563 case bcmSwitchWlanPortMissToCpuCosq: 16564 return _bcm_tr2_ep_redirect_action_cosq_set(unit, port, type, arg); 16565 break; 16566 case bcmSwitchLayeredQoSResolution: 16567 #ifdef BCM_TOMAHAWK3_SUPPORT 16568 if (SOC_IS_TOMAHAWK3(unit)) { 16569 return BCM_E_UNAVAIL; 16570 } 16571 #endif 16572 return _bcm_tr2_layered_qos_resolution_set(unit, port, type, arg); 16573 break; 16574 case bcmSwitchEncapErrorToCpu: 16575 return _bcm_tr2_ehg_error2cpu_set(unit, port, arg); 16576 break; 16577 case bcmSwitchMirrorEgressTrueColorSelect: 16578 case bcmSwitchMirrorEgressTruePriority: 16579 return _bcm_tr2_mirror_egress_true_set(unit, port, type, arg); 16580 break; 16581 #endif /* BCM_TRIUMPH2_SUPPORT */ 16582 case bcmSwitchLinkDownInfoSkip: 16583 return _bcm_esw_link_port_info_skip_set(unit, port, arg); 16584 break; 16585 16586 #if defined(BCM_SABER2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 16587 case bcmSwitchDropSobmhOnLinkDown: 16588 if (SOC_IS_SABER2(unit) || SOC_IS_TOMAHAWK(unit)) { 16589 int rv = BCM_E_NONE; 16590 _bcm_esw_lc_lock(unit); 16591 16592 rv = soc_mem_field32_modify(unit, EPC_LINK_BMAPm, 0, 16593 ENABLE_SOBMH_BLOCKINGf, 16594 (arg ? 1 : 0)); 16595 16596 _bcm_esw_lc_unlock(unit); 16597 16598 if (BCM_FAILURE(rv)) { 16599 _SHR_ERROR_TRACE(rv); 16600 return rv; 16601 } 16602 return BCM_E_NONE; 16603 } 16604 return BCM_E_UNAVAIL; 16605 break; 16606 #endif 16607 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 16608 case bcmSwitchCongestionNotificationIdLow: 16609 if (!soc_feature(unit, soc_feature_qcn)) { 16610 return BCM_E_UNAVAIL; 16611 } 16612 if (arg < 0 || arg > 0xffff) { 16613 return BCM_E_PARAM; 16614 } 16615 return soc_mem_field32_modify(unit, EGR_PORTm, port, 16616 QCN_CNM_CPID_PORT_PREFIXf, arg); 16617 break; 16618 #endif /* defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) */ 16619 16620 #if defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) || \ 16621 defined(BCM_HURRICANE2_SUPPORT) 16622 case bcmSwitchMeterAdjust: 16623 #if defined(BCM_TRIDENT3_SUPPORT) 16624 if (soc_feature(unit, soc_feature_flexible_higig_hdr)) { 16625 return _bcm_td3_meter_adjust_set(unit, port, arg); 16626 } 16627 #endif 16628 #if defined(BCM_TOMAHAWK_SUPPORT) 16629 if (soc_feature(unit, soc_feature_field_multi_pipe_support)) { 16630 BCM_IF_ERROR_RETURN( 16631 bcm_th_xgs3_meter_adjust_set(unit, port, arg)); 16632 } 16633 #endif 16634 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 16635 if (soc_feature(unit, soc_feature_meter_control_is_memory)) { 16636 return _bcm_xgs3_meter_adjust_set(unit, port, arg); 16637 } 16638 #endif 16639 #if defined(BCM_HURRICANE2_SUPPORT) 16640 if (soc_feature(unit, soc_feature_meter_adjust)) { 16641 return _bcm_hr2_meter_adjust_set(unit, port, arg); 16642 } 16643 #endif /* BCM_HURRICANE2_SUPPORT */ 16644 break; 16645 #endif 16646 #if defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 16647 case bcmSwitchShaperAdjust: 16648 #if defined(BCM_TRIDENT3_SUPPORT) 16649 if (soc_feature(unit, soc_feature_flexible_higig_hdr)) { 16650 return _bcm_td3_shaper_adjust_set(unit, port, arg); 16651 } 16652 #endif 16653 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 16654 if (soc_feature(unit, soc_feature_shaper_control_is_memory)) { 16655 return _bcm_xgs3_shaper_adjust_set(unit, port, arg); 16656 } 16657 #endif 16658 #if defined(BCM_HURRICANE2_SUPPORT) 16659 if (soc_feature(unit, soc_feature_meter_adjust)) { 16660 return _bcm_hr2_shaper_adjust_set(unit, port, arg); 16661 } 16662 #endif /* BCM_HURRICANE2_SUPPORT */ 16663 break; 16664 #endif 16665 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 16666 defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) 16667 case bcmSwitchPFCClass0Queue: 16668 case bcmSwitchPFCClass1Queue: 16669 case bcmSwitchPFCClass2Queue: 16670 case bcmSwitchPFCClass3Queue: 16671 case bcmSwitchPFCClass4Queue: 16672 case bcmSwitchPFCClass5Queue: 16673 case bcmSwitchPFCClass6Queue: 16674 case bcmSwitchPFCClass7Queue: 16675 case bcmSwitchPFCClass0McastQueue: 16676 case bcmSwitchPFCClass1McastQueue: 16677 case bcmSwitchPFCClass2McastQueue: 16678 case bcmSwitchPFCClass3McastQueue: 16679 case bcmSwitchPFCClass4McastQueue: 16680 case bcmSwitchPFCClass5McastQueue: 16681 case bcmSwitchPFCClass6McastQueue: 16682 case bcmSwitchPFCClass7McastQueue: 16683 case bcmSwitchPFCClass0DestmodQueue: 16684 case bcmSwitchPFCClass1DestmodQueue: 16685 case bcmSwitchPFCClass2DestmodQueue: 16686 case bcmSwitchPFCClass3DestmodQueue: 16687 case bcmSwitchPFCClass4DestmodQueue: 16688 case bcmSwitchPFCClass5DestmodQueue: 16689 case bcmSwitchPFCClass6DestmodQueue: 16690 case bcmSwitchPFCClass7DestmodQueue: 16691 if (SOC_IS_HELIX5(unit)) { 16692 #if defined(BCM_HELIX5_SUPPORT) 16693 if (arg < 0) { 16694 return bcm_hx5_cosq_port_pfc_op(unit, port, type, 16695 _BCM_COSQ_OP_CLEAR, &arg, 0); 16696 } else { 16697 return bcm_hx5_cosq_port_pfc_op(unit, port, type, 16698 _BCM_COSQ_OP_ADD, &arg, 1); 16699 } 16700 #endif 16701 } else if (SOC_IS_TRIDENT3X(unit)) { 16702 #if defined(BCM_TRIDENT3_SUPPORT) 16703 if (arg < 0) { 16704 return bcm_td3_cosq_port_pfc_op(unit, port, type, 16705 _BCM_COSQ_OP_CLEAR, &arg, 0); 16706 } else { 16707 return bcm_td3_cosq_port_pfc_op(unit, port, type, 16708 _BCM_COSQ_OP_ADD, &arg, 1); 16709 } 16710 #endif 16711 } else if (SOC_IS_TOMAHAWKX(unit)) { 16712 #if defined(BCM_TOMAHAWK3_SUPPORT) 16713 if (SOC_IS_TOMAHAWK3(unit)) { 16714 return BCM_E_UNAVAIL; 16715 } else 16716 #endif 16717 #if defined(BCM_TOMAHAWK_SUPPORT) 16718 if (arg < 0) { 16719 return bcm_th_cosq_port_pfc_op(unit, port, type, 16720 _BCM_COSQ_OP_CLEAR, &arg, 0); 16721 } else { 16722 return bcm_th_cosq_port_pfc_op(unit, port, type, 16723 _BCM_COSQ_OP_ADD, &arg, 1); 16724 } 16725 #endif 16726 } else if (SOC_IS_MONTEREY(unit)) { 16727 #if defined(BCM_MONTEREY_SUPPORT) 16728 if (arg < 0) { 16729 return bcm_mn_cosq_port_pfc_op(unit, port, type, 16730 _BCM_COSQ_OP_CLEAR, &arg, 0); 16731 } else { 16732 return bcm_mn_cosq_port_pfc_op(unit, port, type, 16733 _BCM_COSQ_OP_ADD, &arg, 1); 16734 } 16735 #endif 16736 } else if (SOC_IS_APACHE(unit)) { 16737 #if defined(BCM_APACHE_SUPPORT) 16738 if (arg < 0) { 16739 return bcm_ap_cosq_port_pfc_op(unit, port, type, 16740 _BCM_COSQ_OP_CLEAR, &arg, 0); 16741 } else { 16742 return bcm_ap_cosq_port_pfc_op(unit, port, type, 16743 _BCM_COSQ_OP_ADD, &arg, 1); 16744 } 16745 #endif 16746 } else if (SOC_IS_TD2_TT2(unit)) { 16747 #if defined(BCM_TRIDENT2_SUPPORT) 16748 if (arg < 0) { 16749 return bcm_td2_cosq_port_pfc_op(unit, port, type, 16750 _BCM_COSQ_OP_CLEAR, &arg, 0); 16751 } else { 16752 return bcm_td2_cosq_port_pfc_op(unit, port, type, 16753 _BCM_COSQ_OP_ADD, &arg, 1); 16754 } 16755 #endif 16756 } else if (SOC_IS_TD_TT(unit)) { 16757 #if defined(BCM_TRIDENT_SUPPORT) 16758 if (arg < 0) { 16759 return bcm_td_cosq_port_pfc_op(unit, port, type, 16760 _BCM_COSQ_OP_CLEAR, &arg, 0); 16761 } else { 16762 return bcm_td_cosq_port_pfc_op(unit, port, type, 16763 _BCM_COSQ_OP_ADD, &arg, 1); 16764 } 16765 #endif 16766 } else if (SOC_IS_TRIUMPH3(unit)) { 16767 #if defined(BCM_TRIUMPH3_SUPPORT) 16768 if (arg < 0) { 16769 return bcm_tr3_cosq_port_pfc_op(unit, port, type, 16770 _BCM_COSQ_OP_CLEAR, &arg, 0); 16771 } else { 16772 return bcm_tr3_cosq_port_pfc_op(unit, port, type, 16773 _BCM_COSQ_OP_ADD, &arg, 1); 16774 } 16775 #endif 16776 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 16777 #if defined(BCM_GREYHOUND_SUPPORT) 16778 if (arg < 0) { 16779 return bcm_gh_cosq_port_pfc_op(unit, port, type, 16780 _BCM_COSQ_OP_CLEAR, arg); 16781 } else { 16782 return bcm_gh_cosq_port_pfc_op(unit, port, type, 16783 _BCM_COSQ_OP_ADD, arg); 16784 } 16785 #endif 16786 }else if (SOC_IS_KATANA2(unit)) { 16787 #ifdef BCM_KATANA2_SUPPORT 16788 if (arg < 0) { 16789 return bcm_kt2_cosq_port_pfc_op(unit, port, type, 16790 _BCM_COSQ_OP_CLEAR, &arg, 0); 16791 } else { 16792 return bcm_kt2_cosq_port_pfc_op(unit, port, type, 16793 _BCM_COSQ_OP_ADD, &arg , 1); 16794 } 16795 #endif 16796 } 16797 return BCM_E_UNAVAIL; 16798 break; 16799 16800 #endif /* defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) */ 16801 16802 #ifdef BCM_KATANA_SUPPORT 16803 case bcmSwitchEntropyHashSet1Offset: 16804 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 16805 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TRIDENT2X(unit) || 16806 SOC_IS_TOMAHAWKX(unit)) { 16807 /* Previous devices had two hash config sets(Set0 & Set1), 16808 * which each port can select. 16809 * In Triumph3 each port can be configured with its 16810 * own hash configs. 16811 */ 16812 return BCM_E_UNAVAIL; 16813 } else 16814 #endif /* BCM_TRIUMPH3_SUPPORT */ 16815 if (SOC_IS_KATANAX(unit)) { 16816 return _bcm_xgs3_fieldoffset_set(unit, port, type, arg); 16817 } 16818 return BCM_E_UNAVAIL; 16819 break; 16820 #endif /* BCM_KATANA_SUPPORT */ 16821 #if defined(BCM_KATANA_SUPPORT) 16822 case bcmSwitchEntropyHashSet0Offset: 16823 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 16824 SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit)) { 16825 return _bcm_xgs3_fieldoffset_set(unit, port, type, arg); 16826 } 16827 return BCM_E_UNAVAIL; 16828 break; 16829 #endif /* BCM_KATANA_SUPPORT */ 16830 #ifdef BCM_TRIDENT_SUPPORT 16831 case bcmSwitchMiMDefaultSVP: 16832 if (SOC_IS_TRIDENT(unit) || SOC_IS_TRIDENT2X(unit) || 16833 SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 16834 SOC_IS_TOMAHAWKX(unit)) { 16835 return _bcm_esw_port_tab_set(unit, port, _BCM_CPU_TABS_ETHER, 16836 MIM_ENABLE_DEFAULT_NETWORK_SVPf, (arg) ? 1 : 0); 16837 } 16838 break; 16839 #endif 16840 #ifdef BCM_TRIDENT_SUPPORT 16841 case bcmSwitchEcmpMacroFlowHashEnable: 16842 if (SOC_IS_TRIDENT(unit) && 16843 soc_feature(unit, soc_feature_l3_ecmp_1k_groups)) { 16844 uint32 rval, index; 16845 for (index = 0; index < 2; index++) { 16846 rval = 0; 16847 SOC_IF_ERROR_RETURN(READ_RTAG7_HASH_ECMPr(unit, index, &rval)); 16848 soc_reg_field_set(unit, RTAG7_HASH_ECMPr, &rval, USE_FLOW_HASHf, 16849 (arg) ? 1 : 0); 16850 SOC_IF_ERROR_RETURN(WRITE_RTAG7_HASH_ECMPr(unit, index, rval)); 16851 } 16852 } else if(SOC_IS_TD2_TT2(unit)) { 16853 /*Avoid return unvailbale, USE_FLOW_SEL_ECMPf of RTAG7_HASH_SELr 16854 was set in xgs3_bindings*/ 16855 } else { 16856 return BCM_E_UNAVAIL; 16857 } 16858 break; 16859 #endif 16860 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 16861 case bcmSwitchAlternateStoreForward: 16862 #ifdef BCM_APACHE_SUPPORT 16863 if (SOC_IS_APACHE(unit) && soc_feature(unit, soc_feature_asf)) { 16864 return soc_ap_cut_thru_enable_disable(unit, port, arg); 16865 } else 16866 #endif 16867 if (SOC_IS_TRIDENT2X(unit) 16868 && soc_feature(unit, soc_feature_asf)) { 16869 16870 /* If this is a Trident 2+ there are a few more things that need to be 16871 set. */ 16872 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 16873 if (SOC_IS_TRIDENT2PLUS(unit)) { 16874 return soc_td2p_port_asf_set(unit, port, arg); 16875 } else 16876 #endif 16877 { 16878 return _bcm_td2_port_asf_enable_set(unit, port, arg); 16879 } 16880 } 16881 #if defined(BCM_TOMAHAWK_SUPPORT) 16882 else if (soc_feature(unit, soc_feature_asf_multimode)) { 16883 if (!((arg >= 0) && (arg < 4))) { 16884 return BCM_E_PARAM; 16885 } 16886 return bcm_esw_port_asf_mode_set(unit, port, arg); 16887 } 16888 #endif 16889 break; 16890 #endif 16891 case bcmSwitchMcQueueSchedMode: 16892 #if defined(BCM_TOMAHAWK3_SUPPORT) 16893 if (SOC_IS_TOMAHAWK3(unit)) { 16894 return BCM_E_UNAVAIL; 16895 } else 16896 #endif 16897 #if defined(BCM_TRIDENT2_SUPPORT) 16898 if (SOC_IS_TD2_TT2(unit)) { 16899 if((arg != bcmSwitchMcUcPairGroupMode) 16900 && (arg != bcmSwitchAllMcGroupMode)) 16901 return BCM_E_PARAM; 16902 16903 if (!SOC_PORT_VALID(unit, port)) { 16904 return BCM_E_PORT; 16905 } 16906 #ifdef BCM_MONTEREY_SUPPORT 16907 if (SOC_IS_MONTEREY(unit)) { 16908 break; 16909 } else 16910 #endif 16911 16912 #ifdef BCM_APACHE_SUPPORT 16913 if (SOC_IS_APACHE(unit)) { 16914 soc_apache_sched_type_t sched_type; 16915 sched_type = _soc_apache_port_sched_type_get(unit, port); 16916 if (sched_type != SOC_APACHE_SCHED_HSP) { 16917 return BCM_E_PORT; 16918 } 16919 } else 16920 #endif 16921 { 16922 soc_trident2_sched_type_t sched_type; 16923 sched_type = _soc_trident2_port_sched_type_get(unit, port); 16924 if (sched_type != SOC_TD2_SCHED_HSP) { 16925 return BCM_E_PORT; 16926 } 16927 } 16928 } else 16929 #endif 16930 { 16931 return BCM_E_UNAVAIL; 16932 } 16933 break; 16934 case bcmSwitchTimesyncEgressTimestampingMode: 16935 #if defined(BCM_TIMESYNC_V3_SUPPORT) || \ 16936 defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 16937 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 16938 if (soc_feature(unit, soc_feature_timesync_support) && 16939 soc_feature(unit, soc_feature_timesync_timestampingmode)) { 16940 return _bcm_esw_port_timesync_timestamping_mode_set(unit, port, 16941 (bcm_switch_timesync_timestamping_mode_t)arg); 16942 } 16943 #endif 16944 return BCM_E_UNAVAIL; 16945 break; 16946 default: 16947 break; 16948 } 16949 16950 found = 0; /* True if one or more matches found */ 16951 16952 #ifdef BCM_GREYHOUND_SUPPORT 16953 if(SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 16954 BCM_IF_ERROR_RETURN( 16955 _bcm_gh_switch_control_port_binding_set(unit, port, 16956 type, arg, &found)); 16957 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 16958 } 16959 #endif /* BCM_GREYHOUND_SUPPORT */ 16960 16961 #ifdef BCM_TRIDENT3_SUPPORT 16962 if (SOC_IS_TRIDENT3X(unit)) { 16963 BCM_IF_ERROR_RETURN( 16964 _bcm_td3_switch_control_port_binding_set(unit, port, 16965 type, arg, &found)); 16966 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 16967 } 16968 #endif /* BCM_TRIDENT3_SUPPORT */ 16969 16970 #ifdef BCM_TOMAHAWK3_SUPPORT 16971 if (SOC_IS_TOMAHAWK3(unit)) { 16972 BCM_IF_ERROR_RETURN( 16973 _bcm_th3_switch_control_port_binding_set(unit, port, 16974 type, arg, &found)); 16975 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 16976 } 16977 #endif 16978 #ifdef BCM_TOMAHAWK2_SUPPORT 16979 if (SOC_IS_TOMAHAWK2(unit)) { 16980 BCM_IF_ERROR_RETURN( 16981 _bcm_th2_switch_control_port_binding_set(unit, port, 16982 type, arg, &found)); 16983 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 16984 } 16985 #endif 16986 #ifdef BCM_APACHE_SUPPORT 16987 if(SOC_IS_APACHE(unit)) { 16988 BCM_IF_ERROR_RETURN( 16989 _bcm_apache_switch_control_port_binding_set(unit, port, 16990 type, arg, &found)); 16991 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 16992 } 16993 #endif /* BCM_APACHE_SUPPORT */ 16994 16995 for (i = 0; i < COUNTOF(xgs3_bindings); i++) { 16996 bcm_switch_binding_t *b = &xgs3_bindings[i]; 16997 uint32 max; 16998 int fval, fwidth, prt, idx; 16999 if (b->type == type && (SOC_INFO(unit).chip & b->chip) != 0) { 17000 if (b->feature && !soc_feature(unit, b->feature)) { 17001 continue; 17002 } 17003 17004 if (!soc_reg_field_valid(unit, b->reg, b->field)) { 17005 continue; 17006 } 17007 17008 if (b->xlate_arg) { 17009 if ((fval = (b->xlate_arg)(unit, arg, 1)) < 0) { 17010 return fval; 17011 } 17012 } else { 17013 fval = arg; 17014 } 17015 17016 /* Negative values should be treated as errors */ 17017 if (fval < 0) { 17018 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 17019 /* Exception for several cases */ 17020 if ((b->reg != RTAG7_HASH_CONTROL_L2GRE_MASK_Ar) && 17021 (b->reg != RTAG7_HASH_CONTROL_L2GRE_MASK_Br)) 17022 #endif 17023 return BCM_E_PARAM; 17024 } 17025 17026 if ((SOC_REG_INFO(unit, b->reg).regtype == soc_portreg) || 17027 (SOC_REG_INFO(unit, b->reg).regtype == soc_ppportreg)) { 17028 #ifdef BCM_TRIUMPH2_SUPPORT 17029 if (soc_mem_field_valid(unit, PORT_TABm, 17030 PROTOCOL_PKT_INDEXf) && 17031 ((b->reg == PROTOCOL_PKT_CONTROLr) || 17032 (b->reg == IGMP_MLD_PKT_CONTROLr))) { 17033 int index; 17034 17035 BCM_IF_ERROR_RETURN 17036 (_bcm_tr2_protocol_pkt_index_get(unit, port, 17037 &index)); 17038 prt = index; 17039 idx = 0; 17040 } else 17041 #endif 17042 { 17043 prt = port; 17044 idx = 0; 17045 } 17046 } else { 17047 #ifdef BCM_TRIUMPH2_SUPPORT 17048 if (soc_mem_field_valid(unit, PORT_TABm, 17049 PROTOCOL_PKT_INDEXf) && 17050 ((b->reg == PROTOCOL_PKT_CONTROLr) || 17051 (b->reg == IGMP_MLD_PKT_CONTROLr))) { 17052 int index; 17053 17054 BCM_IF_ERROR_RETURN 17055 (_bcm_tr2_protocol_pkt_index_get(unit, port, 17056 &index)); 17057 prt = REG_PORT_ANY; 17058 idx = index; 17059 } else 17060 #endif 17061 { 17062 prt = REG_PORT_ANY; 17063 idx = 0; 17064 } 17065 } 17066 17067 fwidth = soc_reg_field_length(unit, b->reg, b->field); 17068 if (fwidth < 32) { 17069 max = (1 << fwidth) - 1; 17070 } else { 17071 max = -1; 17072 } 17073 SOC_IF_ERROR_RETURN(soc_reg_get(unit, b->reg, prt, idx, &val64)); 17074 oval64 = val64; 17075 soc_reg64_field32_set(unit, b->reg, &val64, b->field, 17076 ((uint32)fval > max) ? max : (uint32)fval); 17077 if (COMPILER_64_NE(val64, oval64)) { 17078 SOC_IF_ERROR_RETURN(soc_reg_set(unit, b->reg, prt, idx, val64)); 17079 } 17080 17081 found = 1; 17082 } 17083 } 17084 17085 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 17086 } 17087 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 17088 17089 return BCM_E_UNAVAIL; 17090 } 17091 17092 /* 17093 * Function: 17094 * bcm_switch_control_port_get 17095 * Description: 17096 * Retrieve general switch behaviors on a per-port basis 17097 * Parameters: 17098 * unit - Device unit number 17099 * port - Port to check 17100 * type - The desired configuration parameter to retrieve 17101 * arg - Pointer to where the retrieved value will be written 17102 * Returns: 17103 * BCM_E_xxx 17104 */ 17105 17106 int 17107 bcm_esw_switch_control_port_get(int unit, 17108 bcm_port_t port, 17109 bcm_switch_control_t type, 17110 int *arg) 17111 { 17112 17113 #ifdef BCM_GREYHOUND2_SUPPORT 17114 if (SOC_IS_GREYHOUND2(unit)){ 17115 return bcm_gh2_switch_control_port_get(unit, port, 17116 type, arg); 17117 } 17118 #endif /* BCM_GREYHOUND2_SUPPORT */ 17119 17120 #ifdef BCM_SHADOW_SUPPORT 17121 if (SOC_IS_SHADOW(unit)) { 17122 return BCM_E_UNAVAIL; 17123 } 17124 #endif /* BCM_SHADOW_SUPPORT */ 17125 if ((type == bcmSwitchFailoverStackTrunk) || 17126 (type == bcmSwitchFailoverEtherTrunk)) { 17127 return BCM_E_UNAVAIL; 17128 } 17129 17130 #if defined(BCM_HGPROXY_COE_SUPPORT) 17131 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 17132 BCM_GPORT_IS_SET(port) && 17133 _BCM_COE_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, port)) { 17134 /*Gport is used for CoE configirations 17135 *So, do not resolve it. 17136 */ 17137 } else 17138 #endif 17139 if (BCM_GPORT_IS_SET(port)) { 17140 BCM_IF_ERROR_RETURN 17141 (bcm_esw_switch_control_port_validate(unit, port, type, &port)); 17142 } 17143 17144 #ifdef BCM_XGS3_SWITCH_SUPPORT 17145 if (SOC_IS_XGS3_SWITCH(unit)) { 17146 uint64 val64; 17147 int i; 17148 17149 switch(type) { 17150 case bcmSwitchPktAge: 17151 #ifdef BCM_KATANA_SUPPORT 17152 if (SOC_IS_KATANAX(unit)) { 17153 return _bcm_kt_pkt_age_get(unit, arg); 17154 } else 17155 #endif 17156 #ifdef BCM_TRX_SUPPORT 17157 if (SOC_IS_TRX(unit) && !SOC_IS_HURRICANEX(unit) && 17158 !SOC_IS_GREYHOUND(unit) && 17159 !SOC_IS_TOMAHAWKX(unit)) { 17160 return _bcm_ts_pkt_age_get(unit, arg); 17161 } else 17162 #endif 17163 if (SOC_IS_FBX(unit) && !SOC_IS_TOMAHAWKX(unit)) { 17164 return _bcm_fb_pkt_age_get(unit, arg); 17165 } 17166 return BCM_E_UNAVAIL; 17167 break; 17168 case bcmSwitchHashL2: 17169 case bcmSwitchHashL3: 17170 case bcmSwitchHashMultipath: 17171 case bcmSwitchHashIpfixIngress: 17172 case bcmSwitchHashIpfixEgress: 17173 case bcmSwitchHashIpfixIngressDual: 17174 case bcmSwitchHashIpfixEgressDual: 17175 case bcmSwitchHashVlanTranslate: 17176 case bcmSwitchHashMPLS: 17177 #if defined(BCM_TRIUMPH3_SUPPORT) 17178 case bcmSwitchHashWlanPort: 17179 case bcmSwitchHashWlanPortDual: 17180 case bcmSwitchHashWlanClient: 17181 case bcmSwitchHashWlanClientDual: 17182 case bcmSwitchHashRegexAction: 17183 case bcmSwitchHashRegexActionDual: 17184 #endif 17185 #ifdef BCM_TRIDENT2_SUPPORT 17186 case bcmSwitchHashL3DNATPool: 17187 case bcmSwitchHashL3DNATPoolDual: 17188 case bcmSwitchHashVpVlanMemberIngress: 17189 case bcmSwitchHashVpVlanMemberIngressDual: 17190 case bcmSwitchHashVpVlanMemberEgress: 17191 case bcmSwitchHashVpVlanMemberEgressDual: 17192 case bcmSwitchHashL2Endpoint: 17193 case bcmSwitchHashL2EndpointDual: 17194 case bcmSwitchHashEndpointQueueMap: 17195 case bcmSwitchHashEndpointQueueMapDual: 17196 #endif 17197 return _bcm_fb_er_hashselect_get(unit, type, arg); 17198 break; 17199 case bcmSwitchHashControl: 17200 return _bcm_xgs3_hashcontrol_get(unit, arg); 17201 break; 17202 #if defined(BCM_TRIUMPH_SUPPORT) 17203 case bcmSwitchFieldMultipathHashSelect: 17204 return _bcm_field_tr_multipath_hashcontrol_get(unit, arg); 17205 break; 17206 17207 case bcmSwitchL3IngressMode: 17208 #ifdef INCLUDE_L3 17209 if ((soc_feature(unit, soc_feature_l3)) && 17210 (soc_feature(unit,soc_feature_l3_ingress_interface))) { 17211 return bcm_xgs3_l3_ingress_mode_get(unit, arg); 17212 } 17213 #endif /* INCLUDE_L3 */ 17214 return BCM_E_UNAVAIL; 17215 break; 17216 case bcmSwitchL3IngressInterfaceMapSet: 17217 #ifdef INCLUDE_L3 17218 if ((soc_feature(unit, soc_feature_l3)) && 17219 (soc_feature(unit,soc_feature_l3_ingress_interface))) { 17220 return bcm_xgs3_l3_ingress_intf_map_get(unit, arg); 17221 } 17222 #endif /* INCLUDE_L3 */ 17223 return BCM_E_UNAVAIL; 17224 break; 17225 17226 #endif /* BCM_TRIUMPH_SUPPORT */ 17227 case bcmSwitchColorSelect: 17228 return _bcm_fb_er_color_mode_get(unit, port, arg); 17229 break; 17230 case bcmSwitchModuleLoopback: 17231 return _bcm_fb_mod_lb_get(unit, port, arg); 17232 break; 17233 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) \ 17234 || defined(BCM_SCORPION_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 17235 case bcmSwitchIngressRateLimitIncludeIFG: 17236 return _bcm_xgs3_ing_rate_limit_ifg_get(unit, port, arg); 17237 break; 17238 #endif /* BCM_RAPTOR_SUPPORT || BCM_FIREBOLT2_SUPPORT || BCM_HURRICANE_SUPPORT || BCM_SCORPION_SUPPORT */ 17239 case bcmSwitchVrfMax: 17240 #if defined(BCM_HAWKEYE_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) 17241 if (SOC_IS_HAWKEYE(unit) || SOC_IS_HURRICANEX(unit) || 17242 SOC_IS_GREYHOUND(unit)) { 17243 return BCM_E_UNAVAIL; 17244 } 17245 #endif /* BCM_HAWKEYE_SUPPORT || BCM_HURRICANE_SUPPORT */ 17246 return _bcm_vrf_max_get(unit, arg); 17247 break; 17248 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 17249 case bcmSwitchL3UrpfMode: 17250 if (soc_feature(unit, soc_feature_urpf)) { 17251 #ifdef BCM_TRIDENT2_SUPPORT 17252 #if defined(INCLUDE_L3) 17253 if (soc_feature(unit, soc_feature_virtual_port_routing) && 17254 (BCM_GPORT_IS_NIV_PORT(port) || 17255 BCM_GPORT_IS_EXTENDER_PORT(port) || 17256 BCM_GPORT_IS_VLAN_PORT(port))) { 17257 return _bcm_td2_vp_urpf_mode_get(unit, port, arg); 17258 } else 17259 #endif /* INCLUDE_L3 */ 17260 #endif /* BCM_TRIDENT2_SUPPORT */ 17261 { 17262 return _bcm_esw_port_config_get(unit, port, 17263 _bcmPortL3UrpfMode, arg); 17264 } 17265 } 17266 return BCM_E_UNAVAIL; 17267 break; 17268 case bcmSwitchL3UrpfDefaultRoute: 17269 if (soc_feature(unit, soc_feature_urpf)) { 17270 return _bcm_esw_port_config_get(unit, port, 17271 _bcmPortL3UrpfDefaultRoute, arg); 17272 } 17273 return BCM_E_UNAVAIL; 17274 break; 17275 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 17276 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 17277 defined(BCM_TRX_SUPPORT) 17278 case bcmSwitchHashL2Dual: 17279 case bcmSwitchHashL3Dual: 17280 case bcmSwitchHashVlanTranslateDual: 17281 case bcmSwitchHashEgressVlanTranslate: 17282 case bcmSwitchHashEgressVlanTranslateDual: 17283 case bcmSwitchHashMPLSDual: 17284 if (soc_feature(unit, soc_feature_dual_hash)) { 17285 return _bcm_fb_er_hashselect_get(unit, type, arg); 17286 } 17287 return BCM_E_UNAVAIL; 17288 break; 17289 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAPTOR_SUPPORT || BCM_TRX_SUPPORT */ 17290 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRIUMPH_SUPPORT) 17291 case bcmSwitchHashSelectControl: 17292 if (SOC_IS_KATANA2(unit)) { 17293 return _bcm_kt2_selectcontrol_get(unit, arg); 17294 } else if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit)) { 17295 return _bcm_xgs3_selectcontrol_get(unit, arg); 17296 } 17297 return BCM_E_UNAVAIL; 17298 break; 17299 case bcmSwitchHashIP4Field0: 17300 case bcmSwitchHashIP4Field1: 17301 case bcmSwitchHashIP6Field0: 17302 case bcmSwitchHashIP6Field1: 17303 case bcmSwitchHashL2Field0: 17304 case bcmSwitchHashL2Field1: 17305 case bcmSwitchHashMPLSField0: 17306 case bcmSwitchHashMPLSField1: 17307 case bcmSwitchHashHG2UnknownField0: 17308 case bcmSwitchHashHG2UnknownField1: 17309 #ifdef BCM_TOMAHAWK3_SUPPORT 17310 if ((type == bcmSwitchHashHG2UnknownField0 || 17311 type == bcmSwitchHashHG2UnknownField1) 17312 && SOC_IS_TOMAHAWK3(unit)) { 17313 return BCM_E_UNAVAIL; 17314 } 17315 #endif 17316 if ((type == bcmSwitchHashMPLSField0 || type == bcmSwitchHashMPLSField1) 17317 && (SOC_IS_ENDURO(unit) || SOC_IS_TRIUMPH2(unit) || 17318 SOC_IS_APOLLO(unit) || SOC_IS_VALKYRIE2(unit) || 17319 SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 17320 SOC_IS_KATANAX(unit))) { 17321 return BCM_E_UNAVAIL; 17322 } 17323 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit)) { 17324 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17325 } 17326 return BCM_E_UNAVAIL; 17327 break; 17328 #ifdef BCM_TRIUMPH2_SUPPORT 17329 case bcmSwitchHashL2MPLSField0: 17330 case bcmSwitchHashL2MPLSField1: 17331 #ifdef BCM_TOMAHAWK3_SUPPORT 17332 if (SOC_IS_TOMAHAWK3(unit)) { 17333 return BCM_E_UNAVAIL; 17334 } 17335 #endif 17336 17337 case bcmSwitchHashMIMTunnelField0: 17338 case bcmSwitchHashMIMTunnelField1: 17339 case bcmSwitchHashMIMField0: 17340 case bcmSwitchHashMIMField1: 17341 #ifdef BCM_TOMAHAWK3_SUPPORT 17342 if (SOC_IS_TOMAHAWK3(unit)) { 17343 return BCM_E_UNAVAIL; 17344 } 17345 #endif 17346 case bcmSwitchHashL3MPLSField0: 17347 case bcmSwitchHashL3MPLSField1: 17348 case bcmSwitchHashMPLSTunnelField0: 17349 case bcmSwitchHashMPLSTunnelField1: 17350 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 17351 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) || 17352 SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 17353 SOC_IS_KATANAX(unit)) { 17354 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17355 } 17356 return BCM_E_UNAVAIL; 17357 break; 17358 #endif 17359 case bcmSwitchHashL3MiMField0: 17360 case bcmSwitchHashL3MiMField1: 17361 #if defined(BCM_TOMAHAWK3_SUPPORT) 17362 if (SOC_IS_TOMAHAWK3(unit)) { 17363 return BCM_E_UNAVAIL; 17364 } 17365 #endif 17366 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_KATANA2_SUPPORT) \ 17367 || defined(BCM_TOMAHAWK_SUPPORT) 17368 if (SOC_IS_TD2_TT2(unit) || SOC_IS_KATANA2(unit)) { 17369 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17370 } 17371 #endif /* BCM_TRIDENT2_SUPPORT */ 17372 return BCM_E_UNAVAIL; 17373 break; 17374 case bcmSwitchHashL3L2MPLSField0: 17375 case bcmSwitchHashL3L2MPLSField1: 17376 #if defined(BCM_TOMAHAWK3_SUPPORT) 17377 if (SOC_IS_TOMAHAWK3(unit)) { 17378 return BCM_E_UNAVAIL; 17379 } 17380 #endif 17381 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 17382 || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 17383 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 17384 SOC_IS_HELIX4(unit) || SOC_IS_KATANA2(unit)) { 17385 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17386 } 17387 #endif /* BCM_TRIDENT2_SUPPORT */ 17388 return BCM_E_UNAVAIL; 17389 break; 17390 case bcmSwitchHashL2VxlanField0: 17391 case bcmSwitchHashL2VxlanField1: 17392 case bcmSwitchHashL3VxlanField0: 17393 case bcmSwitchHashL3VxlanField1: 17394 #if defined(BCM_TRIDENT2_SUPPORT) 17395 if (SOC_IS_TD2_TT2(unit) && 17396 (soc_feature(unit, soc_feature_vxlan) || 17397 soc_feature(unit, soc_feature_flex_flow))) { 17398 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17399 } 17400 #endif 17401 return BCM_E_UNAVAIL; 17402 break; 17403 17404 case bcmSwitchHashL2L2GreField0: 17405 case bcmSwitchHashL2L2GreField1: 17406 case bcmSwitchHashL3L2GreField0: 17407 case bcmSwitchHashL3L2GreField1: 17408 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 17409 if (((SOC_IS_TD2_TT2(unit) || SOC_IS_TRIUMPH3(unit)) && 17410 soc_feature(unit, soc_feature_l2gre)) 17411 #if defined(BCM_TRIDENT3_SUPPORT) 17412 || soc_feature(unit, soc_feature_flex_flow) 17413 #endif 17414 ) { 17415 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17416 } 17417 #endif 17418 return BCM_E_UNAVAIL; 17419 break; 17420 17421 #ifdef BCM_TRIDENT_SUPPORT 17422 case bcmSwitchHashFCOEField0: 17423 case bcmSwitchHashFCOEField1: 17424 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) { 17425 /* If FCOE is supported, get the control */ 17426 if (soc_feature(unit, soc_feature_fcoe) || 17427 soc_feature(unit, soc_feature_hash_fcoe_field)) { 17428 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17429 } 17430 } 17431 return BCM_E_UNAVAIL; 17432 break; 17433 case bcmSwitchHashL2TrillField0: 17434 case bcmSwitchHashL2TrillField1: 17435 case bcmSwitchHashL3TrillField0: 17436 case bcmSwitchHashL3TrillField1: 17437 case bcmSwitchHashTrillTunnelField0: 17438 case bcmSwitchHashTrillTunnelField1: 17439 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) { 17440 if (SOC_IS_TRIDENT3X(unit) || SOC_IS_TOMAHAWK3(unit)) { 17441 return BCM_E_UNAVAIL; 17442 } 17443 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17444 } 17445 return BCM_E_UNAVAIL; 17446 break; 17447 #endif /* BCM_TRIDENT_SUPPORT */ 17448 #if defined(BCM_TRIDENT_SUPPORT) 17449 case bcmSwitchHashIP4TcpUdpField0: 17450 case bcmSwitchHashIP4TcpUdpField1: 17451 case bcmSwitchHashIP4TcpUdpPortsEqualField0: 17452 case bcmSwitchHashIP4TcpUdpPortsEqualField1: 17453 case bcmSwitchHashIP6TcpUdpField0: 17454 case bcmSwitchHashIP6TcpUdpField1: 17455 case bcmSwitchHashIP6TcpUdpPortsEqualField0: 17456 case bcmSwitchHashIP6TcpUdpPortsEqualField1: 17457 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 17458 SOC_IS_KATANAX(unit)) { 17459 return _bcm_xgs3_fieldselect_get(unit, type, arg); 17460 } 17461 return BCM_E_UNAVAIL; 17462 break; 17463 case bcmSwitchHashField0PreProcessEnable: 17464 if (SOC_IS_TOMAHAWK2(unit) || SOC_IS_TOMAHAWK3(unit)) { 17465 uint64 rtag7_hash_control_3_64; 17466 SOC_IF_ERROR_RETURN 17467 (READ_RTAG7_HASH_CONTROL_3_64r(unit, &rtag7_hash_control_3_64)); 17468 *arg = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_3_64r, 17469 rtag7_hash_control_3_64, HASH_PRE_PROCESSING_ENABLE_Af); 17470 return BCM_E_NONE; 17471 } else 17472 if (SOC_IS_TD_TT(unit) || SOC_IS_KATANAX(unit) || 17473 SOC_IS_TRIUMPH3(unit)) { 17474 uint32 rtag7_hash_control_3; 17475 SOC_IF_ERROR_RETURN 17476 (READ_RTAG7_HASH_CONTROL_3r(unit, &rtag7_hash_control_3)); 17477 *arg = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_3r, 17478 rtag7_hash_control_3, HASH_PRE_PROCESSING_ENABLE_Af); 17479 return BCM_E_NONE; 17480 } 17481 return BCM_E_UNAVAIL; 17482 break; 17483 case bcmSwitchHashField1PreProcessEnable: 17484 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 17485 if (SOC_IS_TOMAHAWK2(unit) || SOC_IS_TOMAHAWK3(unit)) { 17486 uint64 rtag7_hash_control_3_64; 17487 SOC_IF_ERROR_RETURN 17488 (READ_RTAG7_HASH_CONTROL_3_64r(unit, &rtag7_hash_control_3_64)); 17489 *arg = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_3_64r, 17490 rtag7_hash_control_3_64, HASH_PRE_PROCESSING_ENABLE_Bf); 17491 return BCM_E_NONE; 17492 } else 17493 #endif 17494 if (SOC_IS_TD_TT(unit) || SOC_IS_KATANAX(unit) || 17495 SOC_IS_TRIUMPH3(unit)) { 17496 uint32 rtag7_hash_control_3; 17497 SOC_IF_ERROR_RETURN 17498 (READ_RTAG7_HASH_CONTROL_3r(unit, &rtag7_hash_control_3)); 17499 *arg = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_3r, 17500 rtag7_hash_control_3, HASH_PRE_PROCESSING_ENABLE_Bf); 17501 return BCM_E_NONE; 17502 } 17503 return BCM_E_UNAVAIL; 17504 break; 17505 #endif /* BCM_TRIDENT_SUPPORT */ 17506 17507 case bcmSwitchHashField0Config: 17508 case bcmSwitchHashField0Config1: 17509 case bcmSwitchHashField1Config: 17510 case bcmSwitchHashField1Config1: 17511 case bcmSwitchMacroFlowHashFieldConfig: 17512 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit) || 17513 SOC_IS_TD_TT(unit) || SOC_IS_TR_VL(unit) ) { 17514 return _bcm_xgs3_fieldconfig_get(unit, type, arg); 17515 } 17516 return BCM_E_UNAVAIL; 17517 break; 17518 case bcmSwitchTrunkHashSet1UnicastOffset: 17519 case bcmSwitchTrunkHashSet1NonUnicastOffset: 17520 case bcmSwitchFabricTrunkHashSet1UnicastOffset: 17521 case bcmSwitchFabricTrunkHashSet1NonUnicastOffset: 17522 case bcmSwitchLoadBalanceHashSet1UnicastOffset: 17523 case bcmSwitchLoadBalanceHashSet1NonUnicastOffset: 17524 case bcmSwitchECMPHashSet1Offset: 17525 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 17526 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 17527 /* Previous devices had two hash config sets(Set0 & Set1), 17528 * which each port can select. 17529 * In Triumph3 each port can be configured with its 17530 * own hash configs. 17531 */ 17532 return BCM_E_UNAVAIL; 17533 } else 17534 #endif /* BCM_TRIUMPH3_SUPPORT */ 17535 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit) || 17536 SOC_IS_TD_TT(unit) || SOC_IS_TR_VL(unit) ) { 17537 return _bcm_xgs3_fieldoffset_get(unit, port, type, arg); 17538 } 17539 return BCM_E_UNAVAIL; 17540 break; 17541 case bcmSwitchTrunkHashSet0UnicastOffset: 17542 case bcmSwitchTrunkHashSet0NonUnicastOffset: 17543 case bcmSwitchTrunkFailoverHashOffset: 17544 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 17545 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 17546 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 17547 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 17548 case bcmSwitchFabricTrunkFailoverHashOffset: 17549 case bcmSwitchFabricTrunkDynamicHashOffset: 17550 case bcmSwitchTrunkDynamicHashOffset: 17551 case bcmSwitchEcmpDynamicHashOffset: 17552 case bcmSwitchFabricTrunkResilientHashOffset: 17553 case bcmSwitchTrunkResilientHashOffset: 17554 case bcmSwitchEcmpResilientHashOffset: 17555 case bcmSwitchECMPHashSet0Offset: 17556 case bcmSwitchECMPUnderlayHashSet0Offset: 17557 case bcmSwitchECMPVxlanHashOffset: 17558 case bcmSwitchECMPUnderlayVxlanHashOffset: 17559 case bcmSwitchECMPL2GreHashOffset: 17560 case bcmSwitchECMPUnderlayL2GreHashOffset: 17561 case bcmSwitchECMPTrillHashOffset: 17562 case bcmSwitchECMPUnderlayTrillHashOffset: 17563 case bcmSwitchECMPMplsHashOffset: 17564 case bcmSwitchVirtualPortDynamicHashOffset: 17565 case bcmSwitchECMPOverlayHashOffset: 17566 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 17567 if (SOC_IS_HB_GW(unit) || SOC_IS_TRX(unit) || 17568 SOC_IS_TD_TT(unit) || SOC_IS_TR_VL(unit) ) { 17569 return _bcm_xgs3_fieldoffset_get(unit, port, type, arg); 17570 } 17571 return BCM_E_UNAVAIL; 17572 break; 17573 #endif /* BCM_BRADLEY_SUPPORT || BCM_TRIUMPH_SUPPORT */ 17574 case bcmSwitchIgmpPktToCpu: 17575 case bcmSwitchIgmpPktDrop: 17576 case bcmSwitchMldPktToCpu: 17577 case bcmSwitchMldPktDrop: 17578 case bcmSwitchV4ResvdMcPktToCpu: 17579 case bcmSwitchV4ResvdMcPktFlood: 17580 case bcmSwitchV4ResvdMcPktDrop: 17581 case bcmSwitchV6ResvdMcPktToCpu: 17582 case bcmSwitchV6ResvdMcPktFlood: 17583 case bcmSwitchV6ResvdMcPktDrop: 17584 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) ||\ 17585 defined (BCM_TRX_SUPPORT) 17586 case bcmSwitchIgmpReportLeaveDrop: 17587 case bcmSwitchIgmpReportLeaveFlood: 17588 case bcmSwitchIgmpReportLeaveToCpu: 17589 case bcmSwitchIgmpQueryDrop: 17590 case bcmSwitchIgmpQueryFlood: 17591 case bcmSwitchIgmpQueryToCpu: 17592 case bcmSwitchIgmpUnknownDrop: 17593 case bcmSwitchIgmpUnknownFlood: 17594 case bcmSwitchIgmpUnknownToCpu: 17595 case bcmSwitchMldReportDoneDrop: 17596 case bcmSwitchMldReportDoneFlood: 17597 case bcmSwitchMldReportDoneToCpu: 17598 case bcmSwitchMldQueryDrop: 17599 case bcmSwitchMldQueryFlood: 17600 case bcmSwitchMldQueryToCpu: 17601 case bcmSwitchIpmcV4RouterDiscoveryDrop: 17602 case bcmSwitchIpmcV4RouterDiscoveryFlood: 17603 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 17604 case bcmSwitchIpmcV6RouterDiscoveryDrop: 17605 case bcmSwitchIpmcV6RouterDiscoveryFlood: 17606 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 17607 #endif /* defined(BCM_RAPTOR_SUPPORT) || defined(BCM_FIREBOLT2_SUPPORT) || 17608 defined(BCM_TRX_SUPPORT) */ 17609 return _bcm_xgs3_igmp_action_get(unit, port, type, arg); 17610 break; 17611 17612 #if defined(BCM_RAPTOR_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || \ 17613 defined(BCM_TRIDENT_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 17614 defined(BCM_GREYHOUND_SUPPORT) 17615 case bcmSwitchDirectedMirroring: 17616 if (SOC_IS_RAPTOR(unit) || SOC_IS_RAVEN(unit) || 17617 SOC_IS_HAWKEYE(unit) || SOC_IS_HURRICANEX(unit) || 17618 SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 17619 SOC_IS_KATANAX(unit) || SOC_IS_GREYHOUND(unit)) { 17620 *arg = 1; 17621 return BCM_E_NONE; 17622 } 17623 break; 17624 #endif 17625 case bcmSwitchFlexibleMirrorDestinations: 17626 return _bcm_esw_mirror_flexible_get(unit, arg); 17627 17628 case bcmSwitchMirrorExclusive: 17629 return _bcm_esw_mirror_exclusive_get(unit, arg); 17630 17631 case bcmSwitchL3EgressMode: 17632 #ifdef INCLUDE_L3 17633 if (soc_feature(unit, soc_feature_l3)) { 17634 return bcm_xgs3_l3_egress_mode_get(unit, arg); 17635 } 17636 #endif /* INCLUDE_L3 */ 17637 break; 17638 17639 case bcmSwitchL3HostAsRouteReturnValue: 17640 #ifdef INCLUDE_L3 17641 if (soc_feature(unit, soc_feature_l3)) { 17642 return bcm_xgs3_l3_host_as_route_return_get(unit, arg); 17643 } 17644 #endif /* INCLUDE_L3 */ 17645 return BCM_E_UNAVAIL; 17646 break; 17647 17648 case bcmSwitchL3DefipMultipathCountUpdate: 17649 #ifdef INCLUDE_L3 17650 if(soc_feature(unit, soc_feature_l3_defip_ecmp_count)) { 17651 *arg = 1; 17652 return BCM_E_NONE; 17653 } 17654 #endif /* INCLUDE_L3 */ 17655 return BCM_E_UNAVAIL; 17656 break; 17657 case bcmSwitchIpmcReplicationSharing: 17658 #ifdef INCLUDE_L3 17659 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 17660 *arg = SOC_IPMCREPLSHR_GET(unit); 17661 return BCM_E_NONE; 17662 } 17663 #endif /* INCLUDE_L3 */ 17664 return BCM_E_UNAVAIL; 17665 break; 17666 case bcmSwitchIpmcReplicationAvailabilityThreshold: 17667 #ifdef INCLUDE_L3 17668 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 17669 return _bcm_esw_ipmc_repl_threshold_get(unit, arg); 17670 } 17671 #endif /* INCLUDE_L3 */ 17672 return BCM_E_UNAVAIL; 17673 break; 17674 case bcmSwitchHashDualMoveDepth: 17675 if (soc_feature(unit, soc_feature_dual_hash)) { 17676 *arg = SOC_DUAL_HASH_MOVE_MAX(unit); 17677 return BCM_E_NONE; 17678 } 17679 return BCM_E_UNAVAIL; 17680 break; 17681 case bcmSwitchHashDualMoveDepthL2: 17682 if (soc_feature(unit, soc_feature_dual_hash)) { 17683 *arg = SOC_DUAL_HASH_MOVE_MAX_L2X(unit); 17684 return BCM_E_NONE; 17685 } 17686 return BCM_E_UNAVAIL; 17687 break; 17688 case bcmSwitchHashDualMoveDepthMpls: 17689 if (soc_feature(unit, soc_feature_dual_hash)) { 17690 *arg = SOC_DUAL_HASH_MOVE_MAX_MPLS(unit); 17691 return BCM_E_NONE; 17692 } 17693 return BCM_E_UNAVAIL; 17694 break; 17695 case bcmSwitchHashDualMoveDepthVlan: 17696 if (soc_feature(unit, soc_feature_dual_hash)) { 17697 *arg = SOC_DUAL_HASH_MOVE_MAX_VLAN(unit); 17698 return BCM_E_NONE; 17699 } 17700 return BCM_E_UNAVAIL; 17701 break; 17702 case bcmSwitchHashDualMoveDepthEgressVlan: 17703 if (soc_feature(unit, soc_feature_dual_hash)) { 17704 *arg = SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit); 17705 return BCM_E_NONE; 17706 } 17707 return BCM_E_UNAVAIL; 17708 break; 17709 case bcmSwitchHashDualMoveDepthIngVpVlanMember: 17710 if (soc_feature(unit, soc_feature_dual_hash)) { 17711 *arg = SOC_DUAL_HASH_MOVE_MAX_ING_VP_VLAN_MEMBER(unit); 17712 return BCM_E_NONE; 17713 } 17714 return BCM_E_UNAVAIL; 17715 break; 17716 case bcmSwitchHashDualMoveDepthEgrVpVlanMember: 17717 if (soc_feature(unit, soc_feature_dual_hash)) { 17718 *arg = SOC_DUAL_HASH_MOVE_MAX_EGR_VP_VLAN_MEMBER(unit); 17719 return BCM_E_NONE; 17720 } 17721 return BCM_E_UNAVAIL; 17722 break; 17723 #if defined(INCLUDE_L3) 17724 case bcmSwitchHashDualMoveDepthL3: 17725 if (soc_feature(unit, soc_feature_dual_hash)) { 17726 *arg = SOC_DUAL_HASH_MOVE_MAX_L3X(unit); 17727 return BCM_E_NONE; 17728 } 17729 return BCM_E_UNAVAIL; 17730 break; 17731 #endif 17732 #if defined(BCM_TRIUMPH3_SUPPORT) 17733 case bcmSwitchHashDualMoveDepthWlanPort: 17734 if (soc_feature(unit, soc_feature_dual_hash)) { 17735 *arg = SOC_DUAL_HASH_MOVE_MAX_WLAN_PORT(unit); 17736 return BCM_E_NONE; 17737 } 17738 return BCM_E_UNAVAIL; 17739 break; 17740 case bcmSwitchHashDualMoveDepthWlanClient: 17741 if (soc_feature(unit, soc_feature_dual_hash)) { 17742 *arg = SOC_DUAL_HASH_MOVE_MAX_WLAN_CLIENT(unit); 17743 return BCM_E_NONE; 17744 } 17745 return BCM_E_UNAVAIL; 17746 break; 17747 #endif 17748 case bcmSwitchL2PortBlocking: 17749 if (soc_feature(unit, soc_feature_src_mac_group)) { 17750 *arg = (!SOC_L2X_GROUP_ENABLE_GET(unit)); 17751 return BCM_E_NONE; 17752 } 17753 return BCM_E_UNAVAIL; 17754 break; 17755 #if defined(BCM_HAWKEYE_SUPPORT)|| defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) 17756 case bcmSwitchTimeSyncPktDrop: 17757 case bcmSwitchTimeSyncPktFlood: 17758 case bcmSwitchTimeSyncPktToCpu: 17759 case bcmSwitchMmrpPktDrop: 17760 case bcmSwitchMmrpPktFlood: 17761 case bcmSwitchMmrpPktToCpu: 17762 case bcmSwitchSrpPktDrop: 17763 case bcmSwitchSrpPktFlood: 17764 case bcmSwitchSrpPktToCpu: 17765 return _bcm_xgs3_eav_action_get(unit, port, type, arg); 17766 break; 17767 case bcmSwitchSRPEthertype: 17768 case bcmSwitchMMRPEthertype: 17769 case bcmSwitchTimeSyncEthertype: 17770 return _bcm_xgs3_switch_ethertype_get(unit, port, type, arg); 17771 break; 17772 case bcmSwitchSRPDestMacOui: 17773 case bcmSwitchMMRPDestMacOui: 17774 case bcmSwitchTimeSyncDestMacOui: 17775 return _bcm_xgs3_switch_mac_hi_get(unit, port, type, arg); 17776 break; 17777 case bcmSwitchSRPDestMacNonOui: 17778 case bcmSwitchMMRPDestMacNonOui: 17779 case bcmSwitchTimeSyncDestMacNonOui: 17780 return _bcm_xgs3_switch_mac_lo_get(unit, port, type, arg); 17781 break; 17782 case bcmSwitchTimeSyncMessageTypeBitmap: 17783 if (soc_reg_field_valid(unit, TS_CONTROLr, TS_MSG_BITMAPf)) { 17784 uint32 ts_control_rval; 17785 SOC_IF_ERROR_RETURN 17786 (READ_TS_CONTROLr(unit, &ts_control_rval)); 17787 *arg = soc_reg_field_get(unit, TS_CONTROLr, ts_control_rval, 17788 TS_MSG_BITMAPf); 17789 return BCM_E_NONE; 17790 } else { 17791 return BCM_E_UNAVAIL; 17792 } 17793 break; 17794 case bcmSwitchTimeSyncClassAPktPrio: 17795 case bcmSwitchTimeSyncClassBPktPrio: 17796 case bcmSwitchTimeSyncClassAExeptionPktPrio: 17797 case bcmSwitchTimeSyncClassBExeptionPktPrio: 17798 return _bcm_switch_class_pkt_prio_get(unit, type, arg); 17799 break; 17800 17801 17802 #endif /* defined(BCM_HAWKEYE_SUPPORT)*/ 17803 #if defined(BCM_TRIUMPH2_SUPPORT) 17804 case bcmSwitchUnknownVlanToCpu: 17805 case bcmSwitchL3HeaderErrToCpu: 17806 case bcmSwitchIpmcTtlErrToCpu: 17807 case bcmSwitchHgHdrErrToCpu: 17808 case bcmSwitchTunnelErrToCpu: 17809 if (SOC_REG_IS_VALID(unit, EGR_CPU_CONTROLr) && 17810 soc_feature(unit, soc_feature_internal_loopback)) { 17811 return _bcm_tr2_ep_redirect_action_get(unit, port, type, arg); 17812 } 17813 break; 17814 case bcmSwitchStgInvalidToCpu: 17815 case bcmSwitchVlanTranslateEgressMissToCpu: 17816 case bcmSwitchL3PktErrToCpu: 17817 case bcmSwitchMtuFailureToCpu: 17818 case bcmSwitchSrcKnockoutToCpu: 17819 return _bcm_tr2_ep_redirect_action_get(unit, port, type, arg); 17820 break; 17821 case bcmSwitchWlanTunnelMismatchToCpu: 17822 case bcmSwitchWlanTunnelMismatchDrop: 17823 case bcmSwitchWlanPortMissToCpu: 17824 if (soc_feature(unit, soc_feature_wlan)) { 17825 return _bcm_tr2_ep_redirect_action_get(unit, port, type, arg); 17826 } 17827 break; 17828 case bcmSwitchUnknownVlanToCpuCosq: 17829 case bcmSwitchStgInvalidToCpuCosq: 17830 case bcmSwitchVlanTranslateEgressMissToCpuCosq: 17831 case bcmSwitchTunnelErrToCpuCosq: 17832 case bcmSwitchL3HeaderErrToCpuCosq: 17833 case bcmSwitchL3PktErrToCpuCosq: 17834 case bcmSwitchIpmcTtlErrToCpuCosq: 17835 case bcmSwitchMtuFailureToCpuCosq: 17836 case bcmSwitchHgHdrErrToCpuCosq: 17837 case bcmSwitchSrcKnockoutToCpuCosq: 17838 case bcmSwitchWlanTunnelMismatchToCpuCosq: 17839 case bcmSwitchWlanPortMissToCpuCosq: 17840 return _bcm_tr2_ep_redirect_action_cosq_get(unit, port, type, arg); 17841 break; 17842 case bcmSwitchLayeredQoSResolution: 17843 #ifdef BCM_TOMAHAWK3_SUPPORT 17844 if (SOC_IS_TOMAHAWK3(unit)) { 17845 return BCM_E_UNAVAIL; 17846 } 17847 #endif 17848 return _bcm_tr2_layered_qos_resolution_get(unit, port, type, arg); 17849 break; 17850 case bcmSwitchEncapErrorToCpu: 17851 return _bcm_tr2_ehg_error2cpu_get(unit, port, arg); 17852 break; 17853 case bcmSwitchMirrorEgressTrueColorSelect: 17854 case bcmSwitchMirrorEgressTruePriority: 17855 return _bcm_tr2_mirror_egress_true_get(unit, port, type, arg); 17856 break; 17857 #endif /* BCM_TRIUMPH2_SUPPORT */ 17858 17859 #if defined(BCM_ENDURO_SUPPORT) 17860 case bcmSwitchL3UrpfRouteEnableExternal: 17861 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANEX(unit) || 17862 SOC_IS_GREYHOUND(unit)) { 17863 return BCM_E_UNAVAIL; 17864 } 17865 break; 17866 #endif /* BCM_ENDURO_SUPPORT */ 17867 case bcmSwitchLinkDownInfoSkip: 17868 return _bcm_esw_link_port_info_skip_get(unit, port, arg); 17869 break; 17870 17871 #if defined(BCM_SABER2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 17872 case bcmSwitchDropSobmhOnLinkDown: 17873 if (SOC_IS_SABER2(unit) || SOC_IS_TOMAHAWK(unit)) { 17874 int rv = BCM_E_NONE; 17875 epc_link_bmap_entry_t epc_link_bmap_entry={{0}}; 17876 _bcm_esw_lc_lock(unit); 17877 17878 rv = READ_EPC_LINK_BMAPm( 17879 unit, MEM_BLOCK_ANY, 0, &epc_link_bmap_entry); 17880 17881 if (BCM_FAILURE(rv)) { 17882 _bcm_esw_lc_unlock(unit); 17883 _SHR_ERROR_TRACE(rv); 17884 return rv; 17885 } 17886 17887 *arg = soc_mem_field32_get(unit, EPC_LINK_BMAPm, 17888 &epc_link_bmap_entry, ENABLE_SOBMH_BLOCKINGf); 17889 17890 _bcm_esw_lc_unlock(unit); 17891 return BCM_E_NONE; 17892 } 17893 return BCM_E_UNAVAIL; 17894 break; 17895 #endif 17896 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 17897 case bcmSwitchCongestionNotificationIdLow: 17898 if (soc_feature(unit, soc_feature_qcn)) { 17899 egr_port_entry_t entry; 17900 BCM_IF_ERROR_RETURN 17901 (soc_mem_read(unit, EGR_PORTm, MEM_BLOCK_ANY, port, 17902 &entry)); 17903 *arg = soc_mem_field32_get(unit, EGR_PORTm, &entry, 17904 QCN_CNM_CPID_PORT_PREFIXf); 17905 return BCM_E_NONE; 17906 } else { 17907 return BCM_E_UNAVAIL; 17908 } 17909 break; 17910 #endif /* defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) */ 17911 17912 #if defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) || \ 17913 defined(BCM_HURRICANE2_SUPPORT) 17914 case bcmSwitchMeterAdjust: 17915 #if defined(BCM_TRIDENT3_SUPPORT) 17916 if (soc_feature(unit, soc_feature_flexible_higig_hdr)) { 17917 return _bcm_td3_meter_adjust_get(unit, port, arg); 17918 } 17919 #endif 17920 #if defined(BCM_TOMAHAWK_SUPPORT) 17921 if (soc_feature(unit, soc_feature_field_multi_pipe_support)) { 17922 return bcm_th_xgs3_meter_adjust_get(unit, port, arg); 17923 } 17924 #endif 17925 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 17926 if (soc_feature(unit, soc_feature_meter_control_is_memory)) { 17927 return _bcm_xgs3_meter_adjust_get(unit, port, arg); 17928 } 17929 #endif 17930 #if defined(BCM_HURRICANE2_SUPPORT) 17931 if (soc_feature(unit, soc_feature_meter_adjust)) { 17932 return _bcm_hr2_meter_adjust_get(unit, port, arg); 17933 } 17934 #endif /* BCM_HURRICANE2_SUPPORT */ 17935 break; 17936 #endif 17937 #if defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 17938 case bcmSwitchShaperAdjust: 17939 #if defined(BCM_TRIDENT3_SUPPORT) 17940 if (soc_feature(unit, soc_feature_flexible_higig_hdr)) { 17941 return _bcm_td3_shaper_adjust_get(unit, port, arg); 17942 } 17943 #endif 17944 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 17945 if (soc_feature(unit, soc_feature_shaper_control_is_memory)) { 17946 return _bcm_xgs3_shaper_adjust_get(unit, port, arg); 17947 } 17948 #endif 17949 #if defined(BCM_HURRICANE2_SUPPORT) 17950 if (soc_feature(unit, soc_feature_meter_adjust)) { 17951 return _bcm_hr2_shaper_adjust_get(unit, port, arg); 17952 } 17953 #endif /* BCM_HURRICANE2_SUPPORT */ 17954 break; 17955 #endif 17956 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 17957 defined(BCM_GREYHOUND_SUPPORT) 17958 case bcmSwitchPFCClass0Queue: 17959 case bcmSwitchPFCClass1Queue: 17960 case bcmSwitchPFCClass2Queue: 17961 case bcmSwitchPFCClass3Queue: 17962 case bcmSwitchPFCClass4Queue: 17963 case bcmSwitchPFCClass5Queue: 17964 case bcmSwitchPFCClass6Queue: 17965 case bcmSwitchPFCClass7Queue: 17966 case bcmSwitchPFCClass0McastQueue: 17967 case bcmSwitchPFCClass1McastQueue: 17968 case bcmSwitchPFCClass2McastQueue: 17969 case bcmSwitchPFCClass3McastQueue: 17970 case bcmSwitchPFCClass4McastQueue: 17971 case bcmSwitchPFCClass5McastQueue: 17972 case bcmSwitchPFCClass6McastQueue: 17973 case bcmSwitchPFCClass7McastQueue: 17974 case bcmSwitchPFCClass0DestmodQueue: 17975 case bcmSwitchPFCClass1DestmodQueue: 17976 case bcmSwitchPFCClass2DestmodQueue: 17977 case bcmSwitchPFCClass3DestmodQueue: 17978 case bcmSwitchPFCClass4DestmodQueue: 17979 case bcmSwitchPFCClass5DestmodQueue: 17980 case bcmSwitchPFCClass6DestmodQueue: 17981 case bcmSwitchPFCClass7DestmodQueue: 17982 if (SOC_IS_HELIX5(unit)) { 17983 #if defined(BCM_HELIX5_SUPPORT) 17984 int count; 17985 return bcm_hx5_cosq_port_pfc_get(unit, port, type, 17986 (bcm_gport_t *)arg, 1, &count); 17987 #endif 17988 } else if (SOC_IS_TRIDENT3X(unit)) { 17989 #if defined(BCM_TRIDENT3_SUPPORT) 17990 int count; 17991 return bcm_td3_cosq_port_pfc_get(unit, port, type, 17992 (bcm_gport_t *)arg, 1, &count); 17993 #endif 17994 } else if (SOC_IS_TOMAHAWKX(unit)) { 17995 #if defined(BCM_TOMAHAWK3_SUPPORT) 17996 if (SOC_IS_TOMAHAWK3(unit)) { 17997 return BCM_E_UNAVAIL; 17998 } else 17999 #endif 18000 { 18001 #if defined(BCM_TOMAHAWK_SUPPORT) 18002 int count; 18003 return bcm_th_cosq_port_pfc_get(unit, port, type, 18004 (bcm_gport_t *)arg, 1, &count); 18005 #endif 18006 } 18007 } else if (SOC_IS_APACHE(unit)) { 18008 #if defined(BCM_APACHE_SUPPORT) 18009 int count; 18010 return bcm_ap_cosq_port_pfc_get(unit, port, type, 18011 (bcm_gport_t *)arg, 1, &count); 18012 #endif 18013 } else if (SOC_IS_TD2_TT2(unit)) { 18014 #if defined(BCM_TRIDENT2_SUPPORT) 18015 int count; 18016 return bcm_td2_cosq_port_pfc_get(unit, port, type, 18017 (bcm_gport_t *)arg, 1, &count); 18018 #endif 18019 } else if (SOC_IS_TD_TT(unit)) { 18020 #if defined(BCM_TRIDENT_SUPPORT) 18021 int count; 18022 return bcm_td_cosq_port_pfc_get(unit, port, type, 18023 (bcm_gport_t *)arg, 1, &count); 18024 #endif 18025 } else if (SOC_IS_TRIUMPH3(unit)) { 18026 #if defined(BCM_TRIUMPH3_SUPPORT) 18027 int count; 18028 return bcm_tr3_cosq_port_pfc_get(unit, port, type, 18029 (bcm_gport_t *)arg, 1, &count); 18030 #endif 18031 } else if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 18032 #if defined(BCM_GREYHOUND_SUPPORT) 18033 return bcm_gh_cosq_port_pfc_get(unit, port, type, arg); 18034 #endif 18035 }else if(SOC_IS_KATANA2(unit)) { 18036 #ifdef BCM_KATANA2_SUPPORT 18037 int count; 18038 return bcm_kt2_cosq_port_pfc_get(unit, port, type, 18039 (bcm_gport_t *)arg, 1, &count); 18040 #endif 18041 } 18042 return BCM_E_UNAVAIL; 18043 break; 18044 #endif /* defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) */ 18045 18046 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 18047 case bcmSwitchEntropyHashSet1Offset: 18048 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 18049 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TRIDENT2X(unit) || 18050 SOC_IS_TOMAHAWKX(unit)) { 18051 /* Previous devices had two hash config sets(Set0 & Set1), 18052 * which each port can select. 18053 * In Triumph3 each port can be configured with its 18054 * own hash configs. 18055 */ 18056 return BCM_E_UNAVAIL; 18057 } else 18058 #endif /* BCM_TRIUMPH3_SUPPORT */ 18059 if (SOC_IS_KATANAX(unit)) { 18060 return _bcm_xgs3_fieldoffset_get(unit, port, type, arg); 18061 } 18062 return BCM_E_UNAVAIL; 18063 break; 18064 #endif /* BCM_KATANA_SUPPORT */ 18065 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 18066 case bcmSwitchEntropyHashSet0Offset: 18067 if (SOC_IS_KATANAX(unit)|| SOC_IS_TRIUMPH3(unit) || 18068 SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit)) { 18069 return _bcm_xgs3_fieldoffset_get(unit, port, type, arg); 18070 } 18071 return BCM_E_UNAVAIL; 18072 break; 18073 #endif /* BCM_KATANA_SUPPORT */ 18074 18075 #ifdef BCM_TRIDENT_SUPPORT 18076 case bcmSwitchMiMDefaultSVP: 18077 if (SOC_IS_TRIDENT(unit) || SOC_IS_TRIDENT2X(unit) || 18078 SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 18079 SOC_IS_TOMAHAWKX(unit)) { 18080 return _bcm_esw_port_tab_get(unit, port, 18081 MIM_ENABLE_DEFAULT_NETWORK_SVPf, arg); 18082 } 18083 break; 18084 #endif 18085 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 18086 case bcmSwitchAlternateStoreForward: 18087 #ifdef BCM_APACHE_SUPPORT 18088 if (SOC_IS_APACHE(unit) && soc_feature(unit, soc_feature_asf)) { 18089 return soc_apache_is_cut_thru_enabled(unit, port, arg); 18090 } else 18091 #endif 18092 if (SOC_IS_TRIDENT2X(unit) 18093 && soc_feature(unit, soc_feature_asf)) { 18094 return _bcm_td2_port_asf_enable_get(unit, port, arg); 18095 } 18096 #if defined(BCM_TOMAHAWK_SUPPORT) 18097 else if (soc_feature(unit, soc_feature_asf_multimode)) { 18098 return bcm_esw_port_asf_mode_get(unit, port, arg); 18099 } 18100 #endif 18101 break; 18102 #endif 18103 case bcmSwitchMcQueueSchedMode: 18104 #if defined(BCM_TOMAHAWK3_SUPPORT) 18105 if (SOC_IS_TOMAHAWK3(unit)) { 18106 return BCM_E_UNAVAIL; 18107 } else 18108 #endif 18109 #if defined(BCM_TRIDENT2_SUPPORT) 18110 if (SOC_IS_TD2_TT2(unit)) { 18111 18112 if (!SOC_PORT_VALID(unit, port)) { 18113 return BCM_E_PORT; 18114 } 18115 #ifdef BCM_MONTEREY_SUPPORT 18116 if (SOC_IS_MONTEREY(unit)) { 18117 return BCM_E_NONE; 18118 } else 18119 #endif 18120 #ifdef BCM_APACHE_SUPPORT 18121 if (SOC_IS_APACHE(unit)) { 18122 soc_apache_sched_type_t sched_type; 18123 sched_type = _soc_apache_port_sched_type_get(unit, port); 18124 if (sched_type != SOC_APACHE_SCHED_HSP) { 18125 return BCM_E_PORT; 18126 } 18127 } else 18128 #endif 18129 { 18130 soc_trident2_sched_type_t sched_type; 18131 sched_type = _soc_trident2_port_sched_type_get(unit, port); 18132 if (sched_type != SOC_TD2_SCHED_HSP) { 18133 return BCM_E_PORT; 18134 } 18135 } 18136 18137 } else 18138 #endif 18139 { 18140 return BCM_E_UNAVAIL; 18141 } 18142 break; 18143 case bcmSwitchTimesyncEgressTimestampingMode: 18144 #if defined(BCM_TIMESYNC_V3_SUPPORT) || \ 18145 defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 18146 defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 18147 if (soc_feature(unit, soc_feature_timesync_support) && 18148 soc_feature(unit, soc_feature_timesync_timestampingmode)) { 18149 return _bcm_esw_port_timesync_timestamping_mode_get(unit, port, 18150 (bcm_switch_timesync_timestamping_mode_t*)arg); 18151 } 18152 #endif 18153 return BCM_E_UNAVAIL; 18154 default : 18155 break; 18156 } 18157 18158 #ifdef BCM_GREYHOUND_SUPPORT 18159 if(SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 18160 int found = 0; 18161 _bcm_gh_switch_control_port_binding_get(unit, port, type, arg, &found); 18162 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 18163 } 18164 #endif /* BCM_GREYHOUND_SUPPORT */ 18165 18166 #ifdef BCM_TRIDENT3_SUPPORT 18167 if (SOC_IS_TRIDENT3X(unit)) { 18168 int found = 0; 18169 _bcm_td3_switch_control_port_binding_get(unit, port, type, arg, &found); 18170 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 18171 } 18172 #endif /* BCM_TRIDENT3_SUPPORT */ 18173 18174 #ifdef BCM_TOMAHAWK3_SUPPORT 18175 if (SOC_IS_TOMAHAWK3(unit)) { 18176 int found = 0; 18177 BCM_IF_ERROR_RETURN( 18178 _bcm_th3_switch_control_port_binding_get(unit, port, 18179 type, arg, &found)); 18180 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 18181 } 18182 #endif 18183 #ifdef BCM_TOMAHAWK2_SUPPORT 18184 if (SOC_IS_TOMAHAWK2(unit)) { 18185 int found = 0; 18186 BCM_IF_ERROR_RETURN( 18187 _bcm_th2_switch_control_port_binding_get(unit, port, 18188 type, arg, &found)); 18189 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 18190 } 18191 #endif 18192 #ifdef BCM_APACHE_SUPPORT 18193 if(SOC_IS_APACHE(unit)) { 18194 int found = 0; 18195 _bcm_apache_switch_control_port_binding_get(unit, port, 18196 type, arg, &found); 18197 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 18198 } 18199 #endif /* BCM_APACHE_SUPPORT */ 18200 18201 for (i = 0; i < COUNTOF(xgs3_bindings); i++) { 18202 bcm_switch_binding_t *b = &xgs3_bindings[i]; 18203 int prt, idx; 18204 18205 if (b->type==type && (((SOC_INFO(unit).chip & b->chip)!=0) 18206 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 18207 || ((TD2P & b->chip) && SOC_IS_TITAN2PLUS(unit)) 18208 #endif 18209 )) { 18210 18211 if (b->feature && !soc_feature(unit, b->feature)) { 18212 continue; 18213 } 18214 if (!SOC_REG_IS_VALID(unit, b->reg)) { 18215 continue; 18216 } 18217 18218 if (!soc_reg_field_valid(unit, b->reg, b->field)) { 18219 continue; 18220 } 18221 if ((SOC_REG_INFO(unit, b->reg).regtype == soc_portreg) || 18222 (SOC_REG_INFO(unit, b->reg).regtype == soc_ppportreg)) { 18223 #ifdef BCM_TRIUMPH2_SUPPORT 18224 if (soc_mem_field_valid(unit, PORT_TABm, 18225 PROTOCOL_PKT_INDEXf) && 18226 ((b->reg == PROTOCOL_PKT_CONTROLr) || 18227 (b->reg == IGMP_MLD_PKT_CONTROLr))) { 18228 int index; 18229 18230 BCM_IF_ERROR_RETURN 18231 (_bcm_tr2_protocol_pkt_index_get(unit, port, 18232 &index)); 18233 prt = index; 18234 idx = 0; 18235 } else 18236 #endif 18237 { 18238 prt = port; 18239 idx = 0; 18240 } 18241 } else { 18242 #ifdef BCM_TRIUMPH2_SUPPORT 18243 if (soc_mem_field_valid(unit, PORT_TABm, 18244 PROTOCOL_PKT_INDEXf) && 18245 ((b->reg == PROTOCOL_PKT_CONTROLr) || 18246 (b->reg == IGMP_MLD_PKT_CONTROLr))) { 18247 int index; 18248 18249 BCM_IF_ERROR_RETURN 18250 (_bcm_tr2_protocol_pkt_index_get(unit, port, 18251 &index)); 18252 prt = REG_PORT_ANY; 18253 idx = index; 18254 } else 18255 #endif 18256 { 18257 prt = REG_PORT_ANY; 18258 idx = 0; 18259 } 18260 } 18261 18262 SOC_IF_ERROR_RETURN(soc_reg_get(unit, b->reg, prt, idx, &val64)); 18263 *arg = soc_reg64_field32_get(unit, b->reg, val64, b->field); 18264 18265 if (b->xlate_arg) { 18266 *arg = (b->xlate_arg)(unit, *arg, 0); 18267 } 18268 return BCM_E_NONE; 18269 } 18270 } 18271 } 18272 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 18273 18274 return BCM_E_UNAVAIL; 18275 } 18276 18277 #define _BCM_SWITCH_ETHERTYPE_VLAN_TAG_MASK 0xFFFF 18278 18279 /* 18280 * Function: 18281 * bcm_switch_control_set 18282 * Description: 18283 * Specify general switch behaviors. 18284 * Parameters: 18285 * unit - Device unit number 18286 * type - The desired configuration parameter to modify 18287 * arg - The value with which to set the parameter 18288 * Returns: 18289 * BCM_E_xxx 18290 * Notes: 18291 * For behaviors which are port-specific, all non-stack ports 18292 * will be set. 18293 */ 18294 18295 int 18296 bcm_esw_switch_control_set(int unit, 18297 bcm_switch_control_t type, 18298 int arg) 18299 { 18300 bcm_port_t port; 18301 int rv, found; 18302 soc_reg_t tmp_reg; 18303 #if defined(BCM_ESW_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) && \ 18304 (defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT)) 18305 soc_field_t field = 0; 18306 #endif 18307 #if defined(BCM_WARM_BOOT_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 18308 int stable_select; 18309 #endif 18310 18311 #ifdef BCM_GREYHOUND2_SUPPORT 18312 if (SOC_IS_GREYHOUND2(unit)) { 18313 return bcm_gh2_switch_control_set( unit, type, arg); 18314 } 18315 #endif /* BCM_GREYHOUND2_SUPPORT */ 18316 18317 #ifdef BCM_SHADOW_SUPPORT 18318 if (SOC_IS_SHADOW(unit)) { 18319 return BCM_E_UNAVAIL; 18320 } 18321 #endif /* BCM_SHADOW_SUPPORT */ 18322 18323 /* Check for device wide, non port specific controls */ 18324 switch (type) { 18325 case bcmSwitchWarmBoot: 18326 /* If true, set the Warm Boot state; clear otherwise */ 18327 if (arg) { 18328 #ifdef BCM_WARM_BOOT_SUPPORT 18329 /* Cannot be set to anything but FALSE */ 18330 return BCM_E_PARAM; 18331 #else 18332 return SOC_E_UNAVAIL; 18333 #endif 18334 } else { 18335 #ifdef BCM_WARM_BOOT_SUPPORT 18336 SOC_WARM_BOOT_DONE(unit); 18337 #else 18338 return SOC_E_UNAVAIL; 18339 #endif 18340 } 18341 return BCM_E_NONE; 18342 break; 18343 case bcmSwitchStableSelect: 18344 /* Cannot be called once bcm_init is complete */ 18345 return SOC_E_UNAVAIL; 18346 break; 18347 case bcmSwitchStableSize: 18348 /* Cannot be called once bcm_init is complete */ 18349 return SOC_E_UNAVAIL; 18350 break; 18351 case bcmSwitchControlSync: 18352 #if defined(BCM_WARM_BOOT_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 18353 rv = _bcm_switch_control_sync(unit, arg); 18354 return rv; 18355 #else 18356 return SOC_E_UNAVAIL; 18357 #endif 18358 break; 18359 case bcmSwitchControlAutoSync: 18360 #if defined(BCM_WARM_BOOT_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 18361 BCM_IF_ERROR_RETURN 18362 (bcm_esw_switch_control_get(unit, bcmSwitchStableSelect, 18363 &stable_select)); 18364 if (BCM_SWITCH_STABLE_NONE != stable_select) { 18365 SOC_CONTROL_LOCK(unit); 18366 SOC_CONTROL(unit)->autosync = arg ? 1 : 0; 18367 SOC_CONTROL_UNLOCK(unit); 18368 return BCM_E_NONE; 18369 } else { 18370 return BCM_E_NOT_FOUND; 18371 } 18372 #else 18373 return SOC_E_UNAVAIL; 18374 #endif 18375 break; 18376 case bcmSwitchModuleType: 18377 return(_bcm_switch_module_type_set(unit, 18378 BCM_SWITCH_CONTROL_MODID_UNPACK(arg), 18379 BCM_SWITCH_CONTROL_MODTYPE_UNPACK(arg))); 18380 break; 18381 #ifdef BCM_CB_ABORT_ON_ERR 18382 case bcmSwitchCallbackAbortOnError: 18383 if (arg >= 0) { 18384 SOC_CB_ABORT_ON_ERR(unit) = arg ? 1 : 0; 18385 return BCM_E_NONE; 18386 } else { 18387 return BCM_E_PARAM; 18388 } 18389 break; 18390 #endif 18391 case bcmSwitchIpmcGroupMtu: 18392 if (soc_feature(unit, soc_feature_ipmc_group_mtu)) { 18393 uint32 val; 18394 18395 if (arg <= 0 || arg > 0x3fff) { 18396 return BCM_E_PARAM; 18397 } 18398 18399 rv = READ_IPMC_L3_MTUr(unit, 0, &val); 18400 if (rv >= 0) { 18401 soc_reg_field_set(unit, IPMC_L3_MTUr, &val, MTU_LENf, arg); 18402 rv = WRITE_IPMC_L3_MTUr(unit, 0, val); 18403 } 18404 return rv; 18405 } 18406 return BCM_E_UNAVAIL; 18407 break; 18408 18409 case bcmSwitchLoopbackMtuSize: 18410 #if defined(BCM_TRIUMPH3_SUPPORT) 18411 if (SOC_IS_TRIUMPH3(unit)) { 18412 uint32 val; 18413 18414 if (arg <= 0 || arg > 0x3fff) { 18415 return BCM_E_PARAM; 18416 } 18417 18418 rv = READ_PASSTHRU_NLF_MTU_CHECKr(unit, &val); 18419 if (rv >= 0) { 18420 soc_reg_field_set(unit, PASSTHRU_NLF_MTU_CHECKr, &val, 18421 MTU_IN_BYTESf, arg); 18422 rv = WRITE_PASSTHRU_NLF_MTU_CHECKr(unit, val); 18423 } 18424 return rv; 18425 } 18426 #endif 18427 return BCM_E_UNAVAIL; 18428 break; 18429 18430 case bcmSwitchMcastFloodDefault: 18431 return(_bcm_esw_vlan_flood_default_set(unit, arg)); 18432 break; 18433 18434 case bcmSwitchUseGport: 18435 SOC_USE_GPORT_SET(unit, arg); 18436 return BCM_E_NONE; 18437 break; 18438 18439 case bcmSwitchHgHdrMcastFlood: 18440 return(_bcm_esw_higig_flood_l2_set(unit, arg)); 18441 break; 18442 18443 case bcmSwitchHgHdrIpMcastFlood: 18444 return BCM_E_UNAVAIL; 18445 break; 18446 18447 case bcmSwitchFailoverStackTrunk: 18448 case bcmSwitchFailoverEtherTrunk: 18449 return BCM_E_UNAVAIL; 18450 break; 18451 18452 case bcmSwitchMcastL2Range: 18453 #ifdef BCM_BRADLEY_SUPPORT 18454 if (SOC_IS_HBX(unit) || SOC_IS_SC_CQ(unit) || SOC_IS_TRIDENT2(unit)) { 18455 return(soc_hbx_mcast_size_set(unit, arg)); 18456 } 18457 #endif 18458 return BCM_E_UNAVAIL; 18459 break; 18460 18461 case bcmSwitchMcastL3Range: 18462 #ifdef BCM_BRADLEY_SUPPORT 18463 if (SOC_IS_HBX(unit) || SOC_IS_SC_CQ(unit) || SOC_IS_TRIDENT2(unit)) { 18464 return(soc_hbx_ipmc_size_set(unit, arg)); 18465 } 18466 #endif 18467 return BCM_E_UNAVAIL; 18468 break; 18469 18470 /* coverity[equality_cond] */ 18471 case bcmSwitchHgHdrMcastVlanRange: 18472 case bcmSwitchHgHdrMcastL2Range: 18473 case bcmSwitchHgHdrMcastL3Range: 18474 #if defined(BCM_TOMAHAWK3_SUPPORT) 18475 if (SOC_IS_TOMAHAWK3(unit)) { 18476 return BCM_E_UNAVAIL; 18477 } 18478 #endif 18479 #ifdef BCM_BRADLEY_SUPPORT 18480 if (SOC_IS_HBX(unit) || SOC_IS_TRX(unit)) { 18481 int bc_size, mc_size, ipmc_size; 18482 BCM_IF_ERROR_RETURN 18483 (soc_hbx_higig2_mcast_sizes_get(unit, &bc_size, 18484 &mc_size, &ipmc_size)); 18485 switch (type) { 18486 case bcmSwitchHgHdrMcastVlanRange: 18487 bc_size = arg; 18488 break; 18489 case bcmSwitchHgHdrMcastL2Range: 18490 mc_size = arg; 18491 break; 18492 case bcmSwitchHgHdrMcastL3Range: 18493 ipmc_size = arg; 18494 break; 18495 /* Defensive Default */ 18496 /* coverity[dead_error_begin] */ 18497 default: 18498 return BCM_E_PARAM; 18499 } 18500 return soc_hbx_higig2_mcast_sizes_set(unit, bc_size, 18501 mc_size, ipmc_size); 18502 } 18503 #endif 18504 return BCM_E_UNAVAIL; 18505 break; 18506 18507 case bcmSwitchHashSeed0: 18508 #ifdef BCM_BRADLEY_SUPPORT 18509 if ((SOC_IS_HBX(unit) || SOC_IS_TRX(unit)) && 18510 (!(SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)))) { 18511 return soc_reg_field32_modify 18512 (unit, RTAG7_HASH_SEED_Ar, REG_PORT_ANY, HASH_SEED_Af, arg); 18513 } 18514 #endif /* BCM_BRADLEY_SUPPORT */ 18515 return BCM_E_UNAVAIL; 18516 break; 18517 18518 case bcmSwitchHashSeed1: 18519 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 18520 defined(BCM_TRIDENT_SUPPORT) 18521 if ((SOC_IS_HBX(unit) || SOC_IS_TD_TT(unit) || SOC_IS_TRX(unit) || 18522 SOC_IS_TRIUMPH3(unit)) && 18523 (!(SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)))) { 18524 return soc_reg_field32_modify 18525 (unit, RTAG7_HASH_SEED_Br, REG_PORT_ANY, HASH_SEED_Bf, arg); 18526 } 18527 #endif /* BCM_BRADLEY_SUPPORT */ 18528 return BCM_E_UNAVAIL; 18529 break; 18530 18531 #if defined(BCM_TRIDENT_SUPPORT) 18532 case bcmSwitchMacroFlowHashMinOffset: 18533 case bcmSwitchMacroFlowHashMaxOffset: 18534 case bcmSwitchMacroFlowHashStrideOffset: 18535 return _bcm_td_macroflow_offset_set(unit, type, arg); 18536 break; 18537 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 18538 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 18539 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 18540 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 18541 case bcmSwitchMacroFlowTrunkHashMinOffset: 18542 case bcmSwitchMacroFlowTrunkHashMaxOffset: 18543 case bcmSwitchMacroFlowTrunkHashStrideOffset: 18544 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 18545 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 18546 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 18547 /* RTAG7 Macro Flow Concatenation */ 18548 case bcmSwitchMacroFlowEcmpHashConcatEnable: 18549 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 18550 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 18551 case bcmSwitchMacroFlowTrunkHashConcatEnable: 18552 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 18553 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || 18554 SOC_IS_TRIDENT3X(unit) || 18555 SOC_IS_TRIUMPH3(unit) || SOC_IS_KATANA2(unit)) { 18556 return _bcm_td_macroflow_offset_set(unit, type, arg); 18557 } else 18558 #endif /* BCM_TRIDENT2_SUPPORT */ 18559 { 18560 return BCM_E_UNAVAIL; 18561 } 18562 break; 18563 18564 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 18565 case bcmSwitchMacroFlowHashOverlayMinOffset: 18566 case bcmSwitchMacroFlowHashOverlayMaxOffset: 18567 case bcmSwitchMacroFlowHashOverlayStrideOffset: 18568 case bcmSwitchMacroFlowEcmpHashOverlayConcatEnable: 18569 if (soc_feature(unit, soc_feature_riot) || 18570 soc_feature(unit, soc_feature_multi_level_ecmp)) { 18571 return _bcm_td_macroflow_offset_set(unit, type, arg); 18572 } else { 18573 return BCM_E_UNAVAIL; 18574 } 18575 break; 18576 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 18577 #endif /* BCM_TRIDENT_SUPPORT */ 18578 /* RTAG7 Macro Flow Hash Seed */ 18579 case bcmSwitchMacroFlowECMPHashSeed: 18580 case bcmSwitchMacroFlowECMPUnderlayHashSeed: 18581 case bcmSwitchMacroFlowLoadBalanceHashSeed: 18582 case bcmSwitchMacroFlowTrunkHashSeed: 18583 case bcmSwitchMacroFlowHigigTrunkHashSeed: 18584 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 18585 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || 18586 SOC_IS_TRIUMPH3(unit) || SOC_IS_TRIDENT3X(unit) || SOC_IS_KATANA2(unit)) { 18587 return _bcm_td2_macroflow_hash_set(unit, type, arg); 18588 } 18589 #endif /* BCM_TRIDENT2_SUPPORT */ 18590 return BCM_E_UNAVAIL; 18591 break; 18592 18593 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 18594 case bcmSwitchMacroFlowECMPOverlayHashSeed: 18595 if (soc_feature(unit, soc_feature_riot) || 18596 soc_feature(unit, soc_feature_multi_level_ecmp)) { 18597 return _bcm_td2_macroflow_hash_set(unit, type, arg); 18598 } 18599 return BCM_E_UNAVAIL; 18600 break; 18601 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 18602 /* Hash Field select controls */ 18603 case bcmSwitchHashTrillPayloadSelect0: 18604 case bcmSwitchHashTrillPayloadSelect1: 18605 case bcmSwitchHashTrillTunnelSelect0: 18606 case bcmSwitchHashTrillTunnelSelect1: 18607 #if defined(BCM_TRIDENT_SUPPORT) 18608 if ((SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) && 18609 soc_feature(unit, soc_feature_trill)) { 18610 return _bcm_xgs3_field_control_set(unit, type, arg); 18611 } 18612 #endif /* BCM_TRIDENT_SUPPORT */ 18613 return BCM_E_UNAVAIL; 18614 break; 18615 18616 case bcmSwitchHashVxlanPayloadSelect0: 18617 case bcmSwitchHashVxlanPayloadSelect1: 18618 #if defined(BCM_TRIDENT2_SUPPORT) 18619 if (SOC_IS_TD2_TT2(unit) 18620 && (soc_feature(unit, soc_feature_vxlan) 18621 || soc_feature(unit, soc_feature_flex_flow))) { 18622 return _bcm_xgs3_field_control_set(unit, type, arg); 18623 } 18624 #endif /* BCM_TRIDENT2_SUPPORT */ 18625 return BCM_E_UNAVAIL; 18626 break; 18627 18628 case bcmSwitchHashIP6AddrCollapseSelect0: 18629 case bcmSwitchHashIP6AddrCollapseSelect1: 18630 #if defined(BCM_TRIDENT_SUPPORT) 18631 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 18632 SOC_IS_KATANAX(unit)) { 18633 return _bcm_xgs3_field_control_set(unit, type, arg); 18634 } 18635 #endif /* BCM_TRIDENT_SUPPORT */ 18636 return BCM_E_UNAVAIL; 18637 break; 18638 case bcmSwitchHashIP6NextHeaderUseExtensionHeader0: 18639 #if defined(BCM_TRIDENT2_SUPPORT) 18640 if (SOC_IS_TD2_TT2(unit)) { 18641 if (SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROLr, 18642 DISABLE_HASH_IP_EXTENSION_HEADERSf)) { 18643 return soc_reg_field32_modify 18644 (unit, RTAG7_HASH_CONTROLr, REG_PORT_ANY, 18645 DISABLE_HASH_IP_EXTENSION_HEADERSf, (arg) ? 0 : 1); 18646 } 18647 } 18648 #endif 18649 return BCM_E_UNAVAIL; 18650 break; 18651 case bcmSwitchHashIP6NextHeaderUseExtensionHeader1: 18652 return BCM_E_UNAVAIL; 18653 case bcmSwitchHashL2MPLSPayloadSelect0: 18654 case bcmSwitchHashL2MPLSPayloadSelect1: 18655 case bcmSwitchHashIPSecSelect0: 18656 case bcmSwitchHashIPSecSelect1: 18657 case bcmSwitchHashMiMPayloadSelect0: 18658 case bcmSwitchHashMiMPayloadSelect1: 18659 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 18660 || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 18661 if ((SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 18662 SOC_IS_HELIX4(unit) || SOC_IS_KATANA2(unit)) && !SOC_IS_TOMAHAWK3(unit)) { 18663 return _bcm_xgs3_field_control_set(unit, type, arg); 18664 } 18665 #endif /* BCM_TRIDENT2_SUPPORT */ 18666 return BCM_E_UNAVAIL; 18667 break; 18668 18669 case bcmSwitchL2McastAllRouterPortsAddEnable: 18670 SOC_MCAST_ADD_ALL_ROUTER_PORTS(unit) = arg ? 1 : 0; 18671 return BCM_E_NONE; 18672 break; 18673 18674 case bcmSwitchPFCClass0Queue: 18675 case bcmSwitchPFCClass1Queue: 18676 case bcmSwitchPFCClass2Queue: 18677 case bcmSwitchPFCClass3Queue: 18678 case bcmSwitchPFCClass4Queue: 18679 case bcmSwitchPFCClass5Queue: 18680 case bcmSwitchPFCClass6Queue: 18681 case bcmSwitchPFCClass7Queue: 18682 #if defined(BCM_SCORPION_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) 18683 if (SOC_IS_SC_CQ(unit) || SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 18684 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit)) { 18685 return _bcm_tr2_sc_pfc_priority_to_cos_set(unit, type, arg); 18686 } 18687 #endif /* BCM_SCORPION_SUPPORT || BCM_TRIUMPH2_SUPPORT */ 18688 return BCM_E_UNAVAIL; 18689 break; 18690 18691 case bcmSwitchL2HitClear: 18692 case bcmSwitchL2SrcHitClear: 18693 case bcmSwitchL2DstHitClear: 18694 case bcmSwitchL3HostHitClear: 18695 case bcmSwitchL3RouteHitClear: 18696 return _bcm_esw_switch_hit_clear_set(unit, type, arg); 18697 break; 18698 18699 /* This swithc control should be supported only per port. */ 18700 case bcmSwitchEncapErrorToCpu: 18701 return BCM_E_UNAVAIL; 18702 break; 18703 18704 case bcmSwitchSnapNonZeroOui: 18705 #if defined(BCM_TRX_SUPPORT) 18706 if (SOC_IS_TRX(unit)) { 18707 if (!SOC_IS_TRIDENT3X(unit)) { 18708 SOC_IF_ERROR_RETURN 18709 (soc_reg_field32_modify(unit, ING_CONFIG_64r, REG_PORT_ANY, 18710 SNAP_OTHER_DECODE_ENABLEf, 18711 arg ? 1 : 0)); 18712 18713 SOC_IF_ERROR_RETURN 18714 (soc_reg_field32_modify(unit, EGR_CONFIGr, REG_PORT_ANY, 18715 SNAP_OTHER_DECODE_ENABLEf, 18716 arg ? 1 : 0)); 18717 return BCM_E_NONE; 18718 } 18719 } else 18720 #endif /* BCM_TRX_SUPPORT */ 18721 #if defined(BCM_FIREBOLT_SUPPORT) 18722 if (SOC_IS_FB(unit) || SOC_IS_FX_HX(unit) || SOC_IS_HB_GW(unit)) { 18723 SOC_IF_ERROR_RETURN 18724 (soc_reg_field32_modify(unit, ING_CONFIGr, REG_PORT_ANY, 18725 SNAP_OTHER_DECODE_ENABLEf, 18726 arg ? 1 : 0)); 18727 if (SOC_IS_FIREBOLT2(unit)) { 18728 SOC_IF_ERROR_RETURN 18729 (soc_reg_field32_modify(unit, EGR_CONFIGr, REG_PORT_ANY, 18730 SNAP_OTHER_DECODE_ENABLEf, 18731 arg ? 1 : 0)); 18732 } 18733 return BCM_E_NONE; 18734 } 18735 #endif /* BCM_FIREBOLT_SUPPORT */ 18736 18737 return BCM_E_UNAVAIL; 18738 break; 18739 18740 case bcmSwitchL2McIdxRetType: 18741 return _bcm_esw_mcast_idx_ret_type_set(unit, arg); 18742 break; 18743 #ifdef BCM_TRIUMPH3_SUPPORT 18744 case bcmSwitchL2ExtLearn: 18745 if (soc_feature(unit, soc_feature_esm_support) && 18746 (soc_reg_field_valid(unit, LEARN_CONTROLr, EXTERNAL_L2_ENTRYf))) { 18747 if ((arg >= bcmSwitchL2LocInternal) && 18748 (arg < bcmSwitchL2LocIntAndExt)) { 18749 uint32 regval; 18750 BCM_IF_ERROR_RETURN(READ_LEARN_CONTROLr(unit, ®val)); 18751 soc_reg_field_set(unit, LEARN_CONTROLr, ®val, 18752 EXTERNAL_L2_ENTRYf, arg); 18753 18754 return WRITE_LEARN_CONTROLr(unit, regval); 18755 } else { 18756 return BCM_E_PARAM; 18757 } 18758 } else { 18759 return BCM_E_UNAVAIL; 18760 } 18761 #endif 18762 case bcmSwitchL3McIdxRetType: 18763 #ifdef INCLUDE_L3 18764 return _bcm_esw_ipmc_idx_ret_type_set(unit, arg); 18765 #endif 18766 return BCM_E_UNAVAIL; 18767 break; 18768 case bcmSwitchL2SourceDiscardMoveToCpu: 18769 { 18770 soc_reg_t reg; 18771 18772 if (SOC_REG_FIELD_VALID(unit, ING_CONFIGr, STNMOVE_ON_L2SRC_DISCf)){ 18773 reg = ING_CONFIGr; 18774 } else if (SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, 18775 STNMOVE_ON_L2SRC_DISCf)) { 18776 reg = ING_CONFIG_64r; 18777 } else { 18778 return BCM_E_UNAVAIL; 18779 } 18780 18781 BCM_IF_ERROR_RETURN( 18782 soc_reg_field32_modify(unit, reg, REG_PORT_ANY, 18783 STNMOVE_ON_L2SRC_DISCf, arg ? 1: 0)); 18784 return BCM_E_NONE; 18785 } 18786 break; 18787 18788 #ifdef BCM_TRIDENT_SUPPORT 18789 case bcmSwitchFabricTrunkDynamicSampleRate: 18790 case bcmSwitchFabricTrunkDynamicEgressBytesExponent: 18791 case bcmSwitchFabricTrunkDynamicQueuedBytesExponent: 18792 case bcmSwitchFabricTrunkDynamicEgressBytesDecreaseReset: 18793 case bcmSwitchFabricTrunkDynamicQueuedBytesDecreaseReset: 18794 case bcmSwitchFabricTrunkDynamicEgressBytesMinThreshold: 18795 case bcmSwitchFabricTrunkDynamicEgressBytesMaxThreshold: 18796 case bcmSwitchFabricTrunkDynamicQueuedBytesMinThreshold: 18797 case bcmSwitchFabricTrunkDynamicQueuedBytesMaxThreshold: 18798 if (!soc_feature(unit, soc_feature_hg_dlb)) { 18799 return BCM_E_UNAVAIL; 18800 } 18801 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 18802 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 18803 return bcm_th2_hgt_lag_dlb_config_set(unit, type, arg); 18804 } 18805 #endif /* BCM_TOMAHAWK2_SUPPORT */ 18806 return _bcm_trident_hg_dlb_config_set(unit, type, arg); 18807 break; 18808 #endif /* BCM_TRIDENT_SUPPORT */ 18809 18810 #ifdef BCM_TRIUMPH3_SUPPORT 18811 case bcmSwitchTrunkDynamicSampleRate: 18812 case bcmSwitchTrunkDynamicEgressBytesExponent: 18813 case bcmSwitchTrunkDynamicQueuedBytesExponent: 18814 case bcmSwitchTrunkDynamicEgressBytesDecreaseReset: 18815 case bcmSwitchTrunkDynamicQueuedBytesDecreaseReset: 18816 case bcmSwitchTrunkDynamicEgressBytesMinThreshold: 18817 case bcmSwitchTrunkDynamicEgressBytesMaxThreshold: 18818 case bcmSwitchTrunkDynamicQueuedBytesMinThreshold: 18819 case bcmSwitchTrunkDynamicQueuedBytesMaxThreshold: 18820 if (!soc_feature(unit, soc_feature_lag_dlb)) { 18821 return BCM_E_UNAVAIL; 18822 } 18823 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 18824 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 18825 return bcm_th2_hgt_lag_dlb_config_set(unit, type, arg); 18826 } 18827 #endif /* BCM_TOMAHAWK2_SUPPORT */ 18828 return bcm_tr3_lag_dlb_config_set(unit, type, arg); 18829 18830 case bcmSwitchTrunkDynamicAccountingSelect: 18831 case bcmSwitchTrunkDynamicExpectedLoadMinThreshold: 18832 case bcmSwitchTrunkDynamicExpectedLoadMaxThreshold: 18833 case bcmSwitchTrunkDynamicImbalanceMinThreshold: 18834 case bcmSwitchTrunkDynamicImbalanceMaxThreshold: 18835 if (!soc_feature(unit, soc_feature_lag_dlb)) { 18836 return BCM_E_UNAVAIL; 18837 } 18838 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 18839 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 18840 return BCM_E_UNAVAIL; 18841 } 18842 #endif /* BCM_TOMAHAWK2_SUPPORT */ 18843 return bcm_tr3_lag_dlb_config_set(unit, type, arg); 18844 #endif /* BCM_TRIUMPH3_SUPPORT */ 18845 18846 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 18847 case bcmSwitchTrunkDynamicPhysicalQueuedBytesExponent: 18848 case bcmSwitchTrunkDynamicPhysicalQueuedBytesDecreaseReset: 18849 case bcmSwitchTrunkDynamicPhysicalQueuedBytesMinThreshold: 18850 case bcmSwitchTrunkDynamicPhysicalQueuedBytesMaxThreshold: 18851 case bcmSwitchTrunkDynamicRandomSeed: 18852 if (!soc_feature(unit, soc_feature_lag_dlb) || 18853 !soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 18854 return BCM_E_UNAVAIL; 18855 } 18856 return bcm_th2_hgt_lag_dlb_config_set(unit, type, arg); 18857 18858 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesExponent: 18859 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesDecreaseReset: 18860 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesMinThreshold: 18861 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesMaxThreshold: 18862 case bcmSwitchFabricTrunkDynamicRandomSeed: 18863 if (!soc_feature(unit, soc_feature_hg_dlb) || 18864 !soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 18865 return BCM_E_UNAVAIL; 18866 } 18867 return bcm_th2_hgt_lag_dlb_config_set(unit, type, arg); 18868 #endif /* BCM_TOMAHAWK2_SUPPORT */ 18869 18870 #if defined(BCM_TRIUMPH3_SUPPORT) && defined(INCLUDE_L3) 18871 case bcmSwitchEcmpDynamicSampleRate: 18872 case bcmSwitchEcmpDynamicEgressBytesExponent: 18873 case bcmSwitchEcmpDynamicQueuedBytesExponent: 18874 case bcmSwitchEcmpDynamicEgressBytesDecreaseReset: 18875 case bcmSwitchEcmpDynamicQueuedBytesDecreaseReset: 18876 case bcmSwitchEcmpDynamicEgressBytesMinThreshold: 18877 case bcmSwitchEcmpDynamicEgressBytesMaxThreshold: 18878 case bcmSwitchEcmpDynamicQueuedBytesMinThreshold: 18879 case bcmSwitchEcmpDynamicQueuedBytesMaxThreshold: 18880 if (!soc_feature(unit, soc_feature_ecmp_dlb)) { 18881 return BCM_E_UNAVAIL; 18882 } 18883 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 18884 if (soc_feature(unit, soc_feature_ecmp_dlb_optimized)) { 18885 return _bcm_th2_ecmp_dlb_config_set(unit, type, arg); 18886 } 18887 #endif /* BCM_TOMAHAWK2_SUPPORT || BCM_TRIDENT3_SUPPORT*/ 18888 return _bcm_tr3_ecmp_dlb_config_set(unit, type, arg); 18889 case bcmSwitchEcmpDynamicAccountingSelect: 18890 case bcmSwitchEcmpDynamicExpectedLoadMinThreshold: 18891 case bcmSwitchEcmpDynamicExpectedLoadMaxThreshold: 18892 case bcmSwitchEcmpDynamicImbalanceMinThreshold: 18893 case bcmSwitchEcmpDynamicImbalanceMaxThreshold: 18894 if (!soc_feature(unit, soc_feature_ecmp_dlb)) { 18895 return BCM_E_UNAVAIL; 18896 } 18897 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 18898 if (soc_feature(unit, soc_feature_ecmp_dlb_optimized)) { 18899 return BCM_E_UNAVAIL; 18900 } 18901 #endif /* BCM_TOMAHAWK2_SUPPORT || BCM_TRIDENT3_SUPPORT*/ 18902 { 18903 return _bcm_tr3_ecmp_dlb_config_set(unit, type, arg); 18904 } 18905 break; 18906 #endif /* BCM_TRIUMPH3_SUPPORT && INCLUDE_L3 */ 18907 18908 #if defined(INCLUDE_L3) && (defined(BCM_TOMAHAWK2_SUPPORT) || \ 18909 defined(BCM_TRIDENT3_SUPPORT)) 18910 case bcmSwitchEcmpDynamicPhysicalQueuedBytesExponent: 18911 case bcmSwitchEcmpDynamicPhysicalQueuedBytesDecreaseReset: 18912 case bcmSwitchEcmpDynamicPhysicalQueuedBytesMinThreshold: 18913 case bcmSwitchEcmpDynamicPhysicalQueuedBytesMaxThreshold: 18914 case bcmSwitchEcmpDynamicRandomSeed: 18915 if (!soc_feature(unit, soc_feature_ecmp_dlb_optimized)) { 18916 return BCM_E_UNAVAIL; 18917 } 18918 return _bcm_th2_ecmp_dlb_config_set(unit, type, arg); 18919 18920 #endif /* INCLUDE_L3 && BCM_TOMAHAWK2_SUPPORT || BCM_TRIDENT3_SUPPORT */ 18921 18922 #if (defined(BCM_RCPU_SUPPORT) || defined(BCM_OOB_RCPU_SUPPORT)) && \ 18923 defined(BCM_XGS3_SWITCH_SUPPORT) 18924 case bcmSwitchRemoteCpuSchanEnable: 18925 if (soc_feature(unit, soc_feature_rcpu_1)) { 18926 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CMIC_PKT_CTRLr, 18927 REG_PORT_ANY, ENABLE_SCHAN_REQUESTf, arg)); 18928 return BCM_E_NONE; 18929 } else { 18930 return BCM_E_UNAVAIL; 18931 } 18932 break; 18933 case bcmSwitchRemoteCpuMatchLocalMac: 18934 if (soc_feature(unit, soc_feature_rcpu_1)) { 18935 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 18936 CMIC_PKT_CTRLr, REG_PORT_ANY, LMAC0_MATCHf, arg)); 18937 return BCM_E_NONE; 18938 } else { 18939 return BCM_E_UNAVAIL; 18940 } 18941 break; 18942 case bcmSwitchRemoteCpuFromCpuEnable: 18943 if (soc_feature(unit, soc_feature_rcpu_1)) { 18944 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 18945 CMIC_PKT_CTRLr, REG_PORT_ANY, ENABLE_FROMCPU_PACKETf, arg)); 18946 return BCM_E_NONE; 18947 } else { 18948 return BCM_E_UNAVAIL; 18949 } 18950 break; 18951 case bcmSwitchRemoteCpuToCpuEnable: 18952 if (soc_feature(unit, soc_feature_rcpu_1)) { 18953 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 18954 CMIC_PKT_CTRLr, REG_PORT_ANY, ENABLE_TOCPU_PACKETf, arg)); 18955 return BCM_E_NONE; 18956 } else { 18957 return BCM_E_UNAVAIL; 18958 } 18959 break; 18960 case bcmSwitchRemoteCpuCmicEnable: 18961 #ifdef BCM_CMICM_SUPPORT 18962 if (soc_feature(unit, soc_feature_cmicm)) { 18963 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 18964 CMIC_PKT_CTRLr, REG_PORT_ANY, ENABLE_CMIC_REQUESTf, arg)); 18965 return BCM_E_NONE; 18966 } else 18967 #endif 18968 { 18969 return BCM_E_UNAVAIL; 18970 } 18971 break; 18972 case bcmSwitchRemoteCpuMatchVlan: 18973 if (soc_feature(unit, soc_feature_rcpu_1)) { 18974 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 18975 CMIC_PKT_CTRLr, REG_PORT_ANY, VLAN_MATCHf, arg)); 18976 return BCM_E_NONE; 18977 } else { 18978 return BCM_E_UNAVAIL; 18979 } 18980 break; 18981 case bcmSwitchRemoteCpuForceScheduling: 18982 if (soc_feature(unit, soc_feature_rcpu_1)) { 18983 #ifdef BCM_CMICM_SUPPORT 18984 if (soc_feature(unit, soc_feature_cmicm) && 18985 (SOC_IS_KATANAX(unit) || 18986 SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 18987 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE2(unit) || 18988 SOC_IS_HURRICANE3(unit))) { 18989 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_COS_0r, COSf)) { 18990 BCM_IF_ERROR_RETURN( 18991 _bcm_rcpu_switch_regall_set(unit, CMIC_PKT_COS_0r, 18992 COSf, arg)); 18993 } 18994 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_COS_1r, COSf)) { 18995 BCM_IF_ERROR_RETURN( 18996 _bcm_rcpu_switch_regall_set(unit, CMIC_PKT_COS_1r, 18997 COSf, arg)); 18998 } 18999 } else 19000 #endif 19001 { 19002 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_COSr, COSf)) { 19003 BCM_IF_ERROR_RETURN( 19004 _bcm_rcpu_switch_regall_set(unit, CMIC_PKT_COSr, 19005 COSf, arg)); 19006 } 19007 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_COS_HIr, COSf)) { 19008 BCM_IF_ERROR_RETURN( 19009 _bcm_rcpu_switch_regall_set(unit, CMIC_PKT_COS_HIr, 19010 COSf, arg)); 19011 } 19012 } 19013 return BCM_E_NONE; 19014 } else { 19015 return BCM_E_UNAVAIL; 19016 } 19017 break; 19018 case bcmSwitchRemoteCpuToCpuDestPortAllReasons: 19019 if (soc_feature(unit, soc_feature_rcpu_1)) { 19020 #ifdef BCM_CMICM_SUPPORT 19021 if (soc_feature(unit, soc_feature_cmicm) 19022 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19023 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19024 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19025 19026 int i; 19027 19028 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr) && 19029 SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, REASONSf)) { 19030 19031 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr); i++) { 19032 BCM_IF_ERROR_RETURN( 19033 _bcm_rcpu_switch_regall_idx_set(unit, 19034 CMIC_PKT_REASON_DIRECT_0_TYPEr, 19035 i, REASONSf, arg)); 19036 } 19037 } 19038 19039 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr) && 19040 SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr, REASONSf)) { 19041 19042 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr); i++) { 19043 BCM_IF_ERROR_RETURN( 19044 _bcm_rcpu_switch_regall_idx_set(unit, 19045 CMIC_PKT_REASON_DIRECT_1_TYPEr, 19046 i, REASONSf, arg)); 19047 } 19048 } 19049 19050 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_DIRECT_2_TYPEr) && 19051 SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_2_TYPEr, REASONSf)) { 19052 19053 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_2_TYPEr); i++) { 19054 BCM_IF_ERROR_RETURN( 19055 _bcm_rcpu_switch_regall_idx_set(unit, 19056 CMIC_PKT_REASON_DIRECT_2_TYPEr, 19057 i, REASONSf, arg)); 19058 } 19059 } 19060 19061 } else 19062 #endif 19063 { 19064 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECTr, 19065 REASONSf)) { 19066 BCM_IF_ERROR_RETURN( 19067 _bcm_rcpu_switch_regall_set(unit, 19068 CMIC_PKT_REASON_DIRECTr, 19069 REASONSf, arg)); 19070 } 19071 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_HIr, 19072 REASONSf)) { 19073 BCM_IF_ERROR_RETURN( 19074 _bcm_rcpu_switch_regall_set(unit, 19075 CMIC_PKT_REASON_DIRECT_HIr, 19076 REASONSf,arg)); 19077 } 19078 } 19079 return BCM_E_NONE; 19080 } else { 19081 return BCM_E_UNAVAIL; 19082 } 19083 break; 19084 case bcmSwitchRemoteCpuToCpuDestMacAllReasons: 19085 if (soc_feature(unit, soc_feature_rcpu_1)) { 19086 #ifdef BCM_CMICM_SUPPORT 19087 int i; 19088 19089 if (soc_feature(unit, soc_feature_cmicm) 19090 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19091 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19092 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19093 19094 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_0_TYPEr) && 19095 SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_0_TYPEr, REASONSf)) { 19096 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_0_TYPEr); i++) { 19097 BCM_IF_ERROR_RETURN( 19098 _bcm_rcpu_switch_regall_idx_set(unit, 19099 CMIC_PKT_REASON_0_TYPEr, 19100 i, REASONSf, arg)); 19101 } 19102 } 19103 19104 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_1_TYPEr) && 19105 SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_1_TYPEr, REASONSf)) { 19106 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_1_TYPEr); i++) { 19107 BCM_IF_ERROR_RETURN( 19108 _bcm_rcpu_switch_regall_idx_set(unit, 19109 CMIC_PKT_REASON_1_TYPEr, 19110 i, REASONSf, arg)); 19111 } 19112 } 19113 19114 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_2_TYPEr) && 19115 SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_2_TYPEr, REASONSf)) { 19116 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_2_TYPEr); i++) { 19117 BCM_IF_ERROR_RETURN( 19118 _bcm_rcpu_switch_regall_idx_set(unit, 19119 CMIC_PKT_REASON_2_TYPEr, 19120 i, REASONSf, arg)); 19121 } 19122 } 19123 } else 19124 #endif 19125 { 19126 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASONr, REASONSf)) { 19127 BCM_IF_ERROR_RETURN( 19128 _bcm_rcpu_switch_regall_set(unit, CMIC_PKT_REASONr, 19129 REASONSf, arg)); 19130 } 19131 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_HIr, REASONSf)) { 19132 BCM_IF_ERROR_RETURN( 19133 _bcm_rcpu_switch_regall_set(unit, 19134 CMIC_PKT_REASON_HIr, 19135 REASONSf, arg)); 19136 } 19137 } 19138 return BCM_E_NONE; 19139 } else { 19140 return BCM_E_UNAVAIL; 19141 } 19142 break; 19143 case bcmSwitchRxRedirectPktReasons: 19144 if (soc_feature(unit, soc_feature_rcpu_1)) { 19145 #ifdef BCM_CMICM_SUPPORT 19146 if (soc_feature(unit, soc_feature_cmicm) 19147 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19148 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19149 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19150 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_0_TYPEr, REASONSf)) { 19151 uint32 raddr; 19152 int i; 19153 19154 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_0_TYPEr); i++) { 19155 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_0_TYPEr, 19156 REG_PORT_ANY, i); 19157 /* coverity[result_independent_of_operands] */ 19158 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19159 } 19160 } 19161 } else 19162 #endif 19163 { 19164 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASONr, REASONSf)) { 19165 uint32 raddr; 19166 raddr = soc_reg_addr(unit, CMIC_PKT_REASONr, 19167 REG_PORT_ANY, 0); 19168 /* coverity[result_independent_of_operands] */ 19169 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19170 } 19171 } 19172 return BCM_E_NONE; 19173 } 19174 return BCM_E_UNAVAIL; 19175 break; 19176 case bcmSwitchRxRedirectPktReasonsExtended: 19177 if (soc_feature(unit, soc_feature_rcpu_1)) { 19178 #ifdef BCM_CMICM_SUPPORT 19179 if (soc_feature(unit, soc_feature_cmicm) 19180 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19181 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19182 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19183 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_1_TYPEr, REASONSf)) { 19184 uint32 raddr; 19185 int i; 19186 19187 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_1_TYPEr); i++) { 19188 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_1_TYPEr, 19189 REG_PORT_ANY, i); 19190 /* coverity[result_independent_of_operands] */ 19191 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19192 } 19193 return BCM_E_NONE; 19194 } 19195 } else 19196 #endif 19197 { 19198 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_HIr, REASONSf)) { 19199 uint32 raddr; 19200 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_HIr, 19201 REG_PORT_ANY, 0); 19202 /* coverity[result_independent_of_operands] */ 19203 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19204 return BCM_E_NONE; 19205 } 19206 } 19207 } 19208 return BCM_E_UNAVAIL; 19209 break; 19210 case bcmSwitchRxRedirectHigigPktReasons: 19211 if (soc_feature(unit, soc_feature_rcpu_1)) { 19212 #ifdef BCM_CMICM_SUPPORT 19213 if (soc_feature(unit, soc_feature_cmicm) 19214 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19215 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19216 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19217 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, REASONSf)) { 19218 uint32 raddr; 19219 int i; 19220 19221 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr); i++) { 19222 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, 19223 REG_PORT_ANY, i); 19224 /* coverity[result_independent_of_operands] */ 19225 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19226 } 19227 } 19228 } else 19229 #endif 19230 { 19231 if (SOC_REG_FIELD_VALID(unit, 19232 CMIC_PKT_REASON_DIRECTr, REASONSf)) { 19233 uint32 raddr; 19234 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECTr, 19235 REG_PORT_ANY, 0); 19236 /* coverity[result_independent_of_operands] */ 19237 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19238 } 19239 } 19240 return BCM_E_NONE; 19241 } 19242 return BCM_E_UNAVAIL; 19243 break; 19244 case bcmSwitchRxRedirectHigigPktReasonsExtended: 19245 if (soc_feature(unit, soc_feature_rcpu_1)) { 19246 #ifdef BCM_CMICM_SUPPORT 19247 if (soc_feature(unit, soc_feature_cmicm) 19248 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19249 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19250 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19251 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr, 19252 REASONSf)) { 19253 uint32 raddr; 19254 int i; 19255 19256 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr); i++) { 19257 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr, 19258 REG_PORT_ANY, i); 19259 /* coverity[result_independent_of_operands] */ 19260 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19261 } 19262 return BCM_E_NONE; 19263 } 19264 } else 19265 #endif 19266 { 19267 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_HIr, 19268 REASONSf)) { 19269 uint32 raddr; 19270 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_HIr, 19271 REG_PORT_ANY, 0); 19272 /* coverity[result_independent_of_operands] */ 19273 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19274 return BCM_E_NONE; 19275 } 19276 } 19277 } 19278 return BCM_E_UNAVAIL; 19279 break; 19280 case bcmSwitchRxRedirectTruncatedPktReasons: 19281 if (soc_feature(unit, soc_feature_rcpu_1)) { 19282 #ifdef BCM_CMICM_SUPPORT 19283 if (soc_feature(unit, soc_feature_cmicm) 19284 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19285 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19286 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19287 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_MINI_0_TYPEr, 19288 REASONSf)) { 19289 uint32 raddr; 19290 int i; 19291 19292 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_MINI_0_TYPEr); i++) { 19293 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_0_TYPEr, 19294 REG_PORT_ANY, i); 19295 /* coverity[result_independent_of_operands] */ 19296 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19297 } 19298 } 19299 } else 19300 #endif 19301 { 19302 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_MINIr, 19303 REASONSf)) { 19304 uint32 raddr; 19305 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINIr, 19306 REG_PORT_ANY, 0); 19307 /* coverity[result_independent_of_operands] */ 19308 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19309 } 19310 } 19311 return BCM_E_NONE; 19312 } 19313 return BCM_E_UNAVAIL; 19314 break; 19315 case bcmSwitchRxRedirectTruncatedPktReasonsExtended: 19316 if (soc_feature(unit, soc_feature_rcpu_1)) { 19317 #ifdef BCM_CMICM_SUPPORT 19318 if (soc_feature(unit, soc_feature_cmicm) 19319 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 19320 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 19321 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 19322 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_MINI_1_TYPEr, 19323 REASONSf)) { 19324 uint32 raddr; 19325 int i; 19326 19327 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_MINI_1_TYPEr); i++) { 19328 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_1_TYPEr, 19329 REG_PORT_ANY, i); 19330 /* coverity[result_independent_of_operands] */ 19331 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19332 } 19333 return BCM_E_NONE; 19334 } 19335 } else 19336 #endif 19337 { 19338 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_MINI_HIr, 19339 REASONSf)) { 19340 uint32 raddr; 19341 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_HIr, 19342 REG_PORT_ANY, 0); 19343 /* coverity[result_independent_of_operands] */ 19344 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19345 return BCM_E_NONE; 19346 } 19347 } 19348 } 19349 return BCM_E_UNAVAIL; 19350 break; 19351 case bcmSwitchRxRedirectPktCos: 19352 #ifdef BCM_CMICM_SUPPORT 19353 if (soc_feature(unit, soc_feature_cmicm) && 19354 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_LOr)) { 19355 uint32 raddr; 19356 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_LOr, 19357 REG_PORT_ANY, 0); 19358 /* coverity[result_independent_of_operands] */ 19359 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19360 return BCM_E_NONE; 19361 } else 19362 #endif 19363 { 19364 return BCM_E_UNAVAIL; 19365 } 19366 break; 19367 case bcmSwitchRxRedirectPktCosExtended: 19368 #ifdef BCM_CMICM_SUPPORT 19369 if (soc_feature(unit, soc_feature_cmicm) && 19370 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_HIr)) { 19371 uint32 raddr; 19372 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_HIr, 19373 REG_PORT_ANY, 0); 19374 /* coverity[result_independent_of_operands] */ 19375 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 19376 return BCM_E_NONE; 19377 } else 19378 #endif 19379 { 19380 return BCM_E_UNAVAIL; 19381 } 19382 break; 19383 case bcmSwitchRemoteCpuLocalMacOui: 19384 case bcmSwitchRemoteCpuDestMacOui: 19385 if (soc_feature(unit, soc_feature_rcpu_1)) { 19386 return _bcm_rcpu_switch_mac_hi_set(unit, type, arg); 19387 } else { 19388 return BCM_E_UNAVAIL; 19389 } 19390 break; 19391 case bcmSwitchRemoteCpuTcMappingMacOui: 19392 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 19393 uint32 fieldval, regval; 19394 BCM_IF_ERROR_RETURN( 19395 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 19396 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 19397 DAf); 19398 fieldval = (arg << 24); 19399 soc_reg_field_set(unit, REMOTE_CPU_DA_LSr, ®val, DAf, fieldval); 19400 BCM_IF_ERROR_RETURN( 19401 WRITE_REMOTE_CPU_DA_LSr(unit, regval)); 19402 BCM_IF_ERROR_RETURN( 19403 READ_REMOTE_CPU_DA_MSr(unit, ®val)); 19404 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_MSr, regval, 19405 DAf); 19406 fieldval = (arg >> 8) & 0xffff; 19407 soc_reg_field_set(unit, REMOTE_CPU_DA_MSr, ®val, DAf, fieldval); 19408 BCM_IF_ERROR_RETURN( 19409 WRITE_REMOTE_CPU_DA_MSr(unit, regval)); 19410 return BCM_E_NONE; 19411 } else { 19412 return BCM_E_UNAVAIL; 19413 } 19414 break; 19415 case bcmSwitchRemoteCpuLocalMacNonOui: 19416 case bcmSwitchRemoteCpuDestMacNonOui: 19417 if (soc_feature(unit, soc_feature_rcpu_1)) { 19418 return _bcm_rcpu_switch_mac_lo_set(unit, type, arg); 19419 } else { 19420 return BCM_E_UNAVAIL; 19421 } 19422 break; 19423 case bcmSwitchRemoteCpuTcMappingMacNonOui: 19424 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 19425 uint32 fieldval, regval; 19426 BCM_IF_ERROR_RETURN( 19427 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 19428 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 19429 DAf); 19430 fieldval &= 0xff000000; 19431 fieldval |= ((arg << 8) >> 8); 19432 soc_reg_field_set(unit, REMOTE_CPU_DA_LSr, ®val, DAf, fieldval); 19433 BCM_IF_ERROR_RETURN( 19434 WRITE_REMOTE_CPU_DA_LSr(unit, regval)); 19435 return BCM_E_NONE; 19436 } else { 19437 return BCM_E_UNAVAIL; 19438 } 19439 break; 19440 case bcmSwitchRemoteCpuEthertype: 19441 case bcmSwitchRemoteCpuVlan: 19442 case bcmSwitchRemoteCpuTpid: 19443 case bcmSwitchRemoteCpuSignature: 19444 if (soc_feature(unit, soc_feature_rcpu_1)) { 19445 return _bcm_rcpu_switch_vlan_tpid_sig_set(unit, type, arg); 19446 } else { 19447 return BCM_E_UNAVAIL; 19448 } 19449 break; 19450 case bcmSwitchRemoteCpuTcMappingEthertype: 19451 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 19452 BCM_IF_ERROR_RETURN(WRITE_REMOTE_CPU_LENGTH_TYPEr(unit, arg)); 19453 return BCM_E_NONE; 19454 } else { 19455 return BCM_E_UNAVAIL; 19456 } 19457 break; 19458 case bcmSwitchRemoteCpuDestPort: 19459 if (soc_feature(unit, soc_feature_rcpu_1)) { 19460 return _bcm_rcpu_pipe_bypass_header_set(unit, type, arg); 19461 } else { 19462 return BCM_E_UNAVAIL; 19463 } 19464 break; 19465 case bcmSwitchRemoteCpuHigigDestPort: 19466 if (soc_feature(unit, soc_feature_rcpu_1)) { 19467 return _bcm_rcpu_higig_header_set(unit, arg); 19468 } else { 19469 return BCM_E_UNAVAIL; 19470 } 19471 break; 19472 #endif 19473 #if defined(BCM_TRIUMPH2_SUPPORT) \ 19474 || defined(BCM_ENDURO_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 19475 case bcmSwitchServiceTpidReplace: 19476 if (SOC_IS_TRIUMPH2(unit) 19477 || SOC_IS_ENDURO(unit) || SOC_IS_TRIDENT(unit)) { 19478 /* Register settings requires "0" to enable TPID Replace and 19479 * "1" to disable TPID Modifications, for "NOP" SD Action. 19480 */ 19481 BCM_IF_ERROR_RETURN( 19482 soc_reg_field32_modify(unit, EGR_SD_TAG_CONTROLr, 19483 REG_PORT_ANY, DO_NOT_MOD_TPID_ENABLEf, (arg) ? 0 : 1)); 19484 return BCM_E_NONE; 19485 } else { 19486 return BCM_E_UNAVAIL; 19487 } 19488 break; 19489 19490 #endif /* TRIUMPH2 | ENDURO | TRIDENT */ 19491 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 19492 case bcmSwitchCongestionCntag: 19493 case bcmSwitchCongestionCntagEthertype: 19494 case bcmSwitchCongestionCnm: 19495 case bcmSwitchCongestionCnmEthertype: 19496 case bcmSwitchCongestionNotificationIdHigh: 19497 case bcmSwitchCongestionNotificationIdQueue: 19498 case bcmSwitchCongestionUseOuterTpid: 19499 case bcmSwitchCongestionUseOuterVlan: 19500 case bcmSwitchCongestionUseOuterPktPri: 19501 case bcmSwitchCongestionUseOuterCfi: 19502 case bcmSwitchCongestionUseInnerPktPri: 19503 case bcmSwitchCongestionUseInnerCfi: 19504 case bcmSwitchCongestionMissingCntag: 19505 case bcmSwitchCongestionCnmSrcMacNonOui: 19506 case bcmSwitchCongestionCnmSrcMacOui: 19507 return _bcm_switch_qcn_set(unit, type, arg); 19508 break; 19509 #endif /* BCM_TRIDENT_SUPPORT */ 19510 19511 case bcmSwitchLoadBalanceHashSelect: 19512 { 19513 soc_reg_t reg; 19514 19515 if (SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, LBID_RTAGf)){ 19516 reg = ING_CONFIG_64r; 19517 } else if (SOC_REG_FIELD_VALID(unit, ING_CONFIGr, LBID_RTAGf)) { 19518 reg = ING_CONFIGr; 19519 } else { 19520 return BCM_E_UNAVAIL; 19521 } 19522 19523 return soc_reg_field32_modify(unit, reg, REG_PORT_ANY, 19524 LBID_RTAGf, arg); 19525 19526 } 19527 break; 19528 #if defined(BCM_TRIDENT_SUPPORT) && defined(INCLUDE_L3) 19529 case bcmSwitchTrillEthertype: 19530 if (soc_feature(unit, soc_feature_trill)) { 19531 return bcm_td_trill_ethertype_set(unit, arg); 19532 } 19533 break; 19534 19535 case bcmSwitchTrillISISEthertype: 19536 if (soc_feature(unit, soc_feature_trill)) { 19537 return bcm_td_trill_ISIS_ethertype_set(unit, arg); 19538 } 19539 break; 19540 19541 case bcmSwitchTrillISISDestMacOui: 19542 case bcmSwitchTrillBroadcastDestMacOui: 19543 case bcmSwitchTrillEndStationDestMacOui: 19544 if (soc_feature(unit, soc_feature_trill)) { 19545 return bcm_td_trill_mac_set(unit, type, arg, 1); 19546 } 19547 break; 19548 19549 case bcmSwitchTrillISISDestMacNonOui: 19550 case bcmSwitchTrillBroadcastDestMacNonOui: 19551 case bcmSwitchTrillEndStationDestMacNonOui: 19552 if (soc_feature(unit, soc_feature_trill)) { 19553 return bcm_td_trill_mac_set(unit, type, arg, 0); 19554 } 19555 break; 19556 19557 case bcmSwitchTrillMinTtl: 19558 if (soc_feature(unit, soc_feature_trill)) { 19559 return bcm_td_trill_MinTtl_set(unit, arg); 19560 } 19561 break; 19562 19563 case bcmSwitchTrillTtlCheckEnable: 19564 if (soc_feature(unit, soc_feature_trill)) { 19565 return bcm_td_trill_TtlCheckEnable_set(unit, arg); 19566 } 19567 break; 19568 19569 #endif /* BCM_TRIDENT_SUPPORT && INCLUDE_L3 */ 19570 #ifdef BCM_TRIDENT_SUPPORT 19571 case bcmSwitchFcoeEtherType: 19572 #if defined(BCM_TOMAHAWK3_SUPPORT) 19573 if (SOC_IS_TOMAHAWK3(unit)) { 19574 return BCM_E_UNAVAIL; 19575 } else 19576 #endif 19577 if (SOC_IS_TD_TT(unit) || 19578 SOC_IS_TRIUMPH3(unit)) { 19579 rv = _bcm_switch_fcoe_ing_ethertype_set(unit, arg); 19580 19581 #if defined(BCM_TRIDENT2_SUPPORT) 19582 if ((rv == BCM_E_NONE) && 19583 (SOC_IS_TRIDENT2X(unit))) { 19584 /* set egress fcoe ethertype register */ 19585 return _bcm_switch_fcoe_egr_ethertype_set(unit, arg); 19586 } 19587 #endif 19588 return rv; 19589 } 19590 break; 19591 #endif 19592 #if defined(BCM_FIREBOLT_SUPPORT) 19593 #if defined(INCLUDE_L3) 19594 case bcmSwitchL3TunnelIpV4ModeOnly: 19595 return soc_tunnel_term_block_size_set (unit, arg); 19596 break; 19597 case bcmSwitchL3SrcHitEnable: 19598 if (SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, L3SRC_HIT_ENABLEf)) { 19599 return soc_reg_field32_modify(unit, ING_CONFIG_64r, 19600 REG_PORT_ANY, L3SRC_HIT_ENABLEf, 19601 (uint32)arg); 19602 } else if (SOC_REG_FIELD_VALID(unit, ING_CONFIGr, 19603 L3SRC_HIT_ENABLEf)){ 19604 return soc_reg_field32_modify(unit, ING_CONFIGr, REG_PORT_ANY, 19605 L3SRC_HIT_ENABLEf, (uint32)arg); 19606 } else { 19607 return BCM_E_UNAVAIL; 19608 } 19609 break; 19610 #endif /* INCLUDE_L3*/ 19611 #endif /* BCM_FIREBOLT_SUPPORT */ 19612 case bcmSwitchL2DstHitEnable: 19613 if (SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, L2DST_HIT_ENABLEf)) { 19614 return soc_reg_field32_modify(unit, ING_CONFIG_64r, 19615 REG_PORT_ANY, L2DST_HIT_ENABLEf, 19616 (uint32)arg); 19617 } else if (SOC_REG_FIELD_VALID(unit, ING_CONFIGr, 19618 L2DST_HIT_ENABLEf)){ 19619 return soc_reg_field32_modify(unit, ING_CONFIGr, REG_PORT_ANY, 19620 L2DST_HIT_ENABLEf, (uint32)arg); 19621 } else { 19622 return BCM_E_UNAVAIL; 19623 } 19624 break; 19625 case bcmSwitchHashDualMoveDepth: 19626 if (soc_feature(unit, soc_feature_dual_hash)) { 19627 if (arg >= 0) { 19628 SOC_DUAL_HASH_MOVE_MAX(unit) = arg; 19629 return BCM_E_NONE; 19630 } else { 19631 return BCM_E_PARAM; 19632 } 19633 } 19634 return BCM_E_UNAVAIL; 19635 break; 19636 case bcmSwitchHashDualMoveDepthL2: 19637 if (soc_feature(unit, soc_feature_dual_hash)) { 19638 if (arg >= 0) { 19639 SOC_DUAL_HASH_MOVE_MAX_L2X(unit) = arg; 19640 return BCM_E_NONE; 19641 } else { 19642 return BCM_E_PARAM; 19643 } 19644 } 19645 return BCM_E_UNAVAIL; 19646 break; 19647 case bcmSwitchHashDualMoveDepthMpls: 19648 if (soc_feature(unit, soc_feature_dual_hash)) { 19649 if (arg >= 0) { 19650 SOC_DUAL_HASH_MOVE_MAX_MPLS(unit) = arg; 19651 return BCM_E_NONE; 19652 } else { 19653 return BCM_E_PARAM; 19654 } 19655 } 19656 return BCM_E_UNAVAIL; 19657 break; 19658 case bcmSwitchHashDualMoveDepthVlan: 19659 if (soc_feature(unit, soc_feature_dual_hash)) { 19660 if (arg >= 0) { 19661 SOC_DUAL_HASH_MOVE_MAX_VLAN(unit) = arg; 19662 return BCM_E_NONE; 19663 } else { 19664 return BCM_E_PARAM; 19665 } 19666 } 19667 return BCM_E_UNAVAIL; 19668 break; 19669 case bcmSwitchHashDualMoveDepthEgressVlan: 19670 if (soc_feature(unit, soc_feature_dual_hash)) { 19671 if (arg >= 0) { 19672 SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit) = arg; 19673 return BCM_E_NONE; 19674 } else { 19675 return BCM_E_PARAM; 19676 } 19677 } 19678 return BCM_E_UNAVAIL; 19679 break; 19680 case bcmSwitchHashDualMoveDepthIngVpVlanMember: 19681 if (soc_feature(unit, soc_feature_dual_hash)) { 19682 if (arg >= 0) { 19683 SOC_DUAL_HASH_MOVE_MAX_ING_VP_VLAN_MEMBER(unit) = arg; 19684 return BCM_E_NONE; 19685 } else { 19686 return BCM_E_PARAM; 19687 } 19688 } 19689 return BCM_E_UNAVAIL; 19690 break; 19691 case bcmSwitchHashDualMoveDepthEgrVpVlanMember: 19692 if (soc_feature(unit, soc_feature_dual_hash)) { 19693 if (arg >= 0) { 19694 SOC_DUAL_HASH_MOVE_MAX_EGR_VP_VLAN_MEMBER(unit) = arg; 19695 return BCM_E_NONE; 19696 } else { 19697 return BCM_E_PARAM; 19698 } 19699 } 19700 return BCM_E_UNAVAIL; 19701 break; 19702 #if defined(BCM_TRIUMPH3_SUPPORT) 19703 case bcmSwitchHashDualMoveDepthWlanPort: 19704 if (soc_feature(unit, soc_feature_dual_hash)) { 19705 if (arg >= 0) { 19706 SOC_DUAL_HASH_MOVE_MAX_WLAN_PORT(unit) = arg; 19707 return BCM_E_NONE; 19708 } else { 19709 return BCM_E_PARAM; 19710 } 19711 } 19712 return BCM_E_UNAVAIL; 19713 break; 19714 case bcmSwitchHashDualMoveDepthWlanClient: 19715 if (soc_feature(unit, soc_feature_dual_hash)) { 19716 if (arg >= 0) { 19717 SOC_DUAL_HASH_MOVE_MAX_WLAN_CLIENT(unit) = arg; 19718 return BCM_E_NONE; 19719 } else { 19720 return BCM_E_PARAM; 19721 } 19722 } 19723 return BCM_E_UNAVAIL; 19724 break; 19725 case bcmSwitchL2GreProtocolType: 19726 /* Set protocol-type for L2-GRE */ 19727 if ((soc_feature(unit, soc_feature_l2gre) 19728 #if defined(BCM_TRIDENT3_SUPPORT) 19729 || soc_feature(unit, soc_feature_flex_flow) 19730 #endif 19731 ) && SOC_REG_FIELD_VALID(unit, L2GRE_CONTROLr, ETHERTYPEf)) { 19732 return soc_reg_field32_modify(unit, L2GRE_CONTROLr, 19733 REG_PORT_ANY, 19734 ETHERTYPEf, arg); 19735 } else { 19736 return BCM_E_UNAVAIL; 19737 } 19738 break; 19739 19740 case bcmSwitchL2GreVpnIdSizeSet: 19741 /* Set bit-size of VPNID within L2-GRE key */ 19742 if (soc_feature(unit, soc_feature_l2gre) 19743 #if defined(BCM_TRIDENT3_SUPPORT) 19744 || soc_feature(unit, soc_feature_flex_flow) 19745 #endif 19746 ) { 19747 uint32 regval; 19748 switch (arg) { 19749 case 16: 19750 regval = 3; 19751 break; 19752 case 20: 19753 regval = 2; 19754 break; 19755 case 24: 19756 regval = 1; 19757 break; 19758 case 32: 19759 regval = 0; 19760 break; 19761 default: 19762 return BCM_E_PARAM; 19763 } 19764 BCM_IF_ERROR_RETURN 19765 (soc_reg_field32_modify(unit, L2GRE_CONTROLr, 19766 REG_PORT_ANY, 19767 GRE_KEY_ENTROPY_SIZEf, regval)); 19768 BCM_IF_ERROR_RETURN 19769 (soc_reg_field32_modify(unit, EGR_L2GRE_CONTROLr, 19770 REG_PORT_ANY, 19771 GRE_KEY_ENTROPY_SIZEf, regval)); 19772 return BCM_E_NONE; 19773 } else { 19774 return BCM_E_UNAVAIL; 19775 } 19776 break; 19777 case bcmSwitchRemoteEncapsulationMode: 19778 #if defined(BCM_TOMAHAWK3_SUPPORT) 19779 if (SOC_IS_TOMAHAWK3(unit)) { 19780 return BCM_E_UNAVAIL; 19781 } else 19782 #endif 19783 if (SOC_IS_TRIDENT3X(unit)) { 19784 return BCM_E_UNAVAIL; 19785 } 19786 /* We set this mode even if the device doesn't support 19787 * remote encap natively so that TX packets may use the 19788 * Higig2 encoding to a remote system that does. */ 19789 SOC_REMOTE_ENCAP_SET(unit, (arg) ? 1 : 0); 19790 if (soc_feature(unit, soc_feature_remote_encap)) { 19791 return soc_reg_field32_modify(unit, ING_CONFIG_64r, 19792 REG_PORT_ANY, 19793 REPLICATION_MODEf, 19794 (arg) ? 1 : 0); 19795 } 19796 return BCM_E_NONE; 19797 break; 19798 19799 #endif 19800 #if defined(BCM_TRIDENT2_SUPPORT) && defined(INCLUDE_L3) 19801 case bcmSwitchVxlanUdpDestPortSet: 19802 /* Set UDP Dest port for VXLAN */ 19803 if ((soc_feature(unit, soc_feature_vxlan)) || 19804 (soc_feature(unit, soc_feature_flex_flow))) { 19805 return bcm_td2_vxlan_udpDestPort_set(unit, arg); 19806 } else { 19807 return BCM_E_UNAVAIL; 19808 } 19809 break; 19810 19811 case bcmSwitchVxlanEntropyEnable: 19812 /* Enable UDP Source Port Hash for VXLAN */ 19813 if ((soc_feature(unit, soc_feature_vxlan)) || 19814 (soc_feature(unit, soc_feature_flex_flow))) { 19815 return bcm_td2_vxlan_udpSourcePort_set(unit, arg); 19816 } else { 19817 return BCM_E_UNAVAIL; 19818 } 19819 break; 19820 #endif /* BCM_TRIDENT2_SUPPORT && INCLUDE_L3 */ 19821 19822 #if defined(INCLUDE_L3) 19823 case bcmSwitchHashDualMoveDepthL3: 19824 if (soc_feature(unit, soc_feature_dual_hash)) { 19825 if (arg >= 0) { 19826 SOC_DUAL_HASH_MOVE_MAX_L3X(unit) = arg; 19827 return BCM_E_NONE; 19828 } else { 19829 return BCM_E_PARAM; 19830 } 19831 } 19832 return BCM_E_UNAVAIL; 19833 break; 19834 case bcmSwitchHashL3DualLeastFull: 19835 if (soc_feature(unit, soc_feature_dual_hash)) { 19836 if (arg >= 0) { 19837 if (SOC_REG_FIELD_VALID(unit, L3_AUX_HASH_CONTROLr, 19838 INSERT_LEAST_FULL_HALFf)) { 19839 BCM_IF_ERROR_RETURN 19840 (soc_reg_field32_modify(unit, L3_AUX_HASH_CONTROLr, 19841 REG_PORT_ANY, 19842 INSERT_LEAST_FULL_HALFf, 19843 (arg ? 1 : 0))); 19844 return BCM_E_NONE; 19845 } 19846 } else { 19847 return BCM_E_PARAM; 19848 } 19849 } 19850 return BCM_E_UNAVAIL; 19851 break; 19852 #endif 19853 case bcmSwitchHashMultiMoveDepth: 19854 if (soc_feature(unit, soc_feature_ism_memory) || 19855 soc_feature(unit, soc_feature_shared_hash_mem)) { 19856 if (arg >= 0) { 19857 SOC_MULTI_HASH_MOVE_MAX(unit) = arg; 19858 return BCM_E_NONE; 19859 } else { 19860 return BCM_E_PARAM; 19861 } 19862 } 19863 return BCM_E_UNAVAIL; 19864 break; 19865 case bcmSwitchHashMultiMoveDepthL2: 19866 if (soc_feature(unit, soc_feature_ism_memory) || 19867 soc_feature(unit, soc_feature_shared_hash_mem)) { 19868 if (arg >= 0) { 19869 SOC_MULTI_HASH_MOVE_MAX_L2(unit) = arg; 19870 return BCM_E_NONE; 19871 } else { 19872 return BCM_E_PARAM; 19873 } 19874 } 19875 return BCM_E_UNAVAIL; 19876 break; 19877 case bcmSwitchHashMultiMoveDepthL3: 19878 if (soc_feature(unit, soc_feature_ism_memory) || 19879 soc_feature(unit, soc_feature_shared_hash_mem)) { 19880 if (arg >= 0) { 19881 SOC_MULTI_HASH_MOVE_MAX_L3(unit) = arg; 19882 return BCM_E_NONE; 19883 } else { 19884 return BCM_E_PARAM; 19885 } 19886 } 19887 return BCM_E_UNAVAIL; 19888 break; 19889 case bcmSwitchHashMultiMoveDepthMpls: 19890 if (soc_feature(unit, soc_feature_ism_memory) || 19891 (soc_feature(unit, soc_feature_shared_hash_mem) && 19892 SOC_IS_TRIDENT3X(unit)) || SOC_IS_TOMAHAWK3(unit)) { 19893 if (arg >= 0) { 19894 SOC_MULTI_HASH_MOVE_MAX_MPLS(unit) = arg; 19895 return BCM_E_NONE; 19896 } else { 19897 return BCM_E_PARAM; 19898 } 19899 } 19900 return BCM_E_UNAVAIL; 19901 break; 19902 case bcmSwitchHashMultiMoveDepthVlan: 19903 if (soc_feature(unit, soc_feature_ism_memory) || 19904 (soc_feature(unit, soc_feature_shared_hash_mem) && 19905 SOC_IS_TRIDENT3X(unit))) { 19906 if (arg >= 0) { 19907 SOC_MULTI_HASH_MOVE_MAX_VLAN(unit) = arg; 19908 return BCM_E_NONE; 19909 } else { 19910 return BCM_E_PARAM; 19911 } 19912 } 19913 return BCM_E_UNAVAIL; 19914 break; 19915 case bcmSwitchHashMultiMoveDepthVlanTranslate1: 19916 if (soc_feature(unit, soc_feature_ism_memory) || 19917 (soc_feature(unit, soc_feature_shared_hash_mem) && 19918 SOC_IS_TRIDENT3X(unit))) { 19919 if (arg >= 0) { 19920 SOC_MULTI_HASH_MOVE_MAX_VLAN_1(unit) = arg; 19921 return BCM_E_NONE; 19922 } else { 19923 return BCM_E_PARAM; 19924 } 19925 } 19926 return BCM_E_UNAVAIL; 19927 break; 19928 case bcmSwitchHashMultiMoveDepthVlanTranslate2: 19929 if (soc_feature(unit, soc_feature_ism_memory) || 19930 (soc_feature(unit, soc_feature_shared_hash_mem) && 19931 SOC_IS_TRIDENT3X(unit))) { 19932 if (arg >= 0) { 19933 SOC_MULTI_HASH_MOVE_MAX_VLAN_2(unit) = arg; 19934 return BCM_E_NONE; 19935 } else { 19936 return BCM_E_PARAM; 19937 } 19938 } 19939 return BCM_E_UNAVAIL; 19940 break; 19941 case bcmSwitchHashMultiMoveDepthEgressVlan: 19942 if (soc_feature(unit, soc_feature_ism_memory) || 19943 (soc_feature(unit, soc_feature_shared_hash_mem) && 19944 SOC_IS_TRIDENT3X(unit))) { 19945 if (arg >= 0) { 19946 SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN(unit) = arg; 19947 return BCM_E_NONE; 19948 } else { 19949 return BCM_E_PARAM; 19950 } 19951 } 19952 return BCM_E_UNAVAIL; 19953 break; 19954 case bcmSwitchHashMultiMoveDepthEgressVlanTranslate1: 19955 if (soc_feature(unit, soc_feature_ism_memory) || 19956 (soc_feature(unit, soc_feature_shared_hash_mem) && 19957 SOC_IS_TRIDENT3X(unit))) { 19958 if (arg >= 0) { 19959 SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_1(unit) = arg; 19960 return BCM_E_NONE; 19961 } else { 19962 return BCM_E_PARAM; 19963 } 19964 } 19965 return BCM_E_UNAVAIL; 19966 break; 19967 case bcmSwitchHashMultiMoveDepthEgressVlanTranslate2: 19968 if (soc_feature(unit, soc_feature_ism_memory) || 19969 (soc_feature(unit, soc_feature_shared_hash_mem) && 19970 SOC_IS_TRIDENT3X(unit))) { 19971 if (arg >= 0) { 19972 SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_2(unit) = arg; 19973 return BCM_E_NONE; 19974 } else { 19975 return BCM_E_PARAM; 19976 } 19977 } 19978 return BCM_E_UNAVAIL; 19979 break; 19980 case bcmSwitchHashMultiMoveDepthExactMatch: 19981 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 19982 if (arg >= 0) { 19983 SOC_MULTI_HASH_MOVE_MAX_FPEM(unit) = arg; 19984 return BCM_E_NONE; 19985 } else { 19986 return BCM_E_PARAM; 19987 } 19988 } 19989 return BCM_E_UNAVAIL; 19990 break; 19991 #ifdef BCM_TOMAHAWK3_SUPPORT 19992 case bcmSwitchHashMultiMoveDepthL3Tunnel: 19993 if (SOC_IS_TOMAHAWK3(unit)) { 19994 if (arg >= 0) { 19995 SOC_MULTI_HASH_MOVE_MAX_L3_TUNNEL(unit) = arg; 19996 return BCM_E_NONE; 19997 } else { 19998 return BCM_E_PARAM; 19999 } 20000 } 20001 return BCM_E_UNAVAIL; 20002 break; 20003 #endif /* BCM_TOMAHAWK3_SUPPORT */ 20004 case bcmSwitchHashL2DualLeastFull: 20005 if (soc_feature(unit, soc_feature_dual_hash)) { 20006 if (arg >= 0) { 20007 if (SOC_REG_FIELD_VALID(unit, L2_AUX_HASH_CONTROLr, 20008 INSERT_LEAST_FULL_HALFf)) { 20009 BCM_IF_ERROR_RETURN 20010 (soc_reg_field32_modify(unit, L2_AUX_HASH_CONTROLr, 20011 REG_PORT_ANY, 20012 INSERT_LEAST_FULL_HALFf, 20013 (arg ? 1 : 0))); 20014 return BCM_E_NONE; 20015 } 20016 } else { 20017 return BCM_E_PARAM; 20018 } 20019 } 20020 return BCM_E_UNAVAIL; 20021 break; 20022 case bcmSwitchHashMPLSDualLeastFull: 20023 if (soc_feature(unit, soc_feature_dual_hash)) { 20024 if (arg >= 0) { 20025 if (SOC_REG_FIELD_VALID(unit, MPLS_ENTRY_HASH_CONTROLr, 20026 INSERT_LEAST_FULL_HALFf)) { 20027 BCM_IF_ERROR_RETURN 20028 (soc_reg_field32_modify(unit, MPLS_ENTRY_HASH_CONTROLr, 20029 REG_PORT_ANY, 20030 INSERT_LEAST_FULL_HALFf, 20031 (arg ? 1 : 0))); 20032 return BCM_E_NONE; 20033 } 20034 } else { 20035 return BCM_E_PARAM; 20036 } 20037 } 20038 return BCM_E_UNAVAIL; 20039 break; 20040 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) || \ 20041 defined(BCM_VALKYRIE2_SUPPORT) || defined(BCM_ENDURO_SUPPORT) || \ 20042 defined(BCM_HURRICANE_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 20043 defined(BCM_KATANA_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 20044 defined(BCM_KATANA2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 20045 case bcmSwitchSynchronousPortClockSource: 20046 if (soc_feature(unit, soc_feature_gmii_clkout)) { 20047 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || \ 20048 defined(BCM_KATANA_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 20049 defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 20050 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit) || 20051 SOC_IS_KATANA(unit) || SOC_IS_GREYHOUND(unit) || 20052 SOC_IS_HURRICANE2(unit) || SOC_IS_KATANA2(unit) || 20053 SOC_IS_HURRICANE3(unit)) { 20054 return _bcm_switch_sync_port_select_set(unit, (uint32)arg); 20055 } else 20056 #endif 20057 { 20058 uint32 mask = soc_reg_field_length(unit, EGR_L1_CLK_RECOVERY_CTRLr, 20059 PRI_PORT_SELf); 20060 mask = (1 << mask) - 1; 20061 return soc_reg_field32_modify(unit, EGR_L1_CLK_RECOVERY_CTRLr, 20062 REG_PORT_ANY, PRI_PORT_SELf, 20063 (uint32)arg & mask); 20064 } 20065 } else { 20066 return BCM_E_UNAVAIL; 20067 } 20068 break; 20069 case bcmSwitchSynchronousPortClockSourceBkup: 20070 if (soc_feature(unit, soc_feature_gmii_clkout)) { 20071 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || \ 20072 defined(BCM_KATANA_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 20073 defined(BCM_HURRICANE2_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 20074 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit)) { 20075 return _bcm_switch_sync_port_select_set(unit, (uint32)arg); 20076 } else if (SOC_IS_KATANA(unit) || SOC_IS_GREYHOUND(unit) || 20077 SOC_IS_HURRICANE2(unit) || SOC_IS_KATANA2(unit) || 20078 SOC_IS_HURRICANE3(unit)) { 20079 return _bcm_switch_sync_port_backup_select_set(unit,(uint32)arg); 20080 } else 20081 #endif 20082 { 20083 uint32 mask = soc_reg_field_length(unit, EGR_L1_CLK_RECOVERY_CTRLr, 20084 BKUP_PORT_SELf); 20085 mask = (1 << mask) - 1; 20086 return soc_reg_field32_modify(unit, EGR_L1_CLK_RECOVERY_CTRLr, 20087 REG_PORT_ANY, BKUP_PORT_SELf, 20088 (uint32)arg & mask); 20089 } 20090 } else { 20091 return BCM_E_UNAVAIL; 20092 } 20093 break; 20094 20095 case bcmSwitchSynchronousPortClockSourceDivCtrl: 20096 if (soc_feature(unit, soc_feature_gmii_clkout)) { 20097 #if defined(BCM_HURRICANE_SUPPORT) || defined(BCM_KATANA_SUPPORT) || \ 20098 defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 20099 defined(BCM_KATANA2_SUPPORT) 20100 if (SOC_IS_HURRICANE(unit) || SOC_IS_KATANA(unit) || 20101 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE2(unit) || 20102 SOC_IS_KATANA2(unit) || SOC_IS_HURRICANE3(unit)) { 20103 return _bcm_switch_div_ctrl_select_set(unit, (uint32)arg); 20104 } else { 20105 return BCM_E_UNAVAIL; 20106 } 20107 #else 20108 { 20109 return BCM_E_UNAVAIL; 20110 } 20111 #endif 20112 } else { 20113 return BCM_E_UNAVAIL; 20114 } 20115 break; 20116 20117 case bcmSwitchSynchronousPortClockSourceBkupDivCtrl: 20118 if (soc_feature(unit, soc_feature_gmii_clkout)) { 20119 #if defined(BCM_HURRICANE_SUPPORT) || defined(BCM_KATANA_SUPPORT) || \ 20120 defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 20121 defined(BCM_KATANA2_SUPPORT) 20122 if (SOC_IS_HURRICANE(unit) || SOC_IS_KATANA(unit) || 20123 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE2(unit) || 20124 SOC_IS_KATANA2(unit) || SOC_IS_HURRICANE3(unit)) { 20125 return _bcm_switch_div_ctrl_backup_select_set(unit, (uint32)arg); 20126 } else { 20127 return BCM_E_UNAVAIL; 20128 } 20129 #else 20130 { 20131 return BCM_E_UNAVAIL; 20132 } 20133 20134 #endif 20135 } else { 20136 return BCM_E_UNAVAIL; 20137 } 20138 #endif 20139 break; 20140 #if (defined(BCM_TRIDENT_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT)) && \ 20141 defined(INCLUDE_L3) 20142 case bcmSwitchNivEthertype: 20143 if (soc_feature(unit, soc_feature_niv)) { 20144 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 20145 #if defined(BCM_GREYHOUND_SUPPORT) 20146 return bcm_gh_niv_ethertype_set(unit, arg); 20147 #endif /* BCM_GREYHOUND_SUPPORT */ 20148 } 20149 #if defined(BCM_TRIDENT_SUPPORT) 20150 else { 20151 return bcm_trident_niv_ethertype_set(unit, arg); 20152 } 20153 #endif /* BCM_TRIDENT_SUPPORT */ 20154 } 20155 return BCM_E_UNAVAIL; 20156 break; 20157 #endif /* (BCM_TRIDENT_SUPPORT || BCM_GREYHOUND_SUPPORT) && INCLUDE_L3 */ 20158 #if defined(BCM_KATANA2_SUPPORT) 20159 case bcmSwitchSubportPktTagEthertype: 20160 if (soc_feature(unit, soc_feature_lltag)) { 20161 return _bcm_switch_subportpkttag_ethertype_set(unit, arg); 20162 } 20163 return BCM_E_UNAVAIL; 20164 break; 20165 #endif 20166 #if (defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT)) && defined(INCLUDE_L3) 20167 case bcmSwitchEtagEthertype: 20168 if (soc_feature(unit, soc_feature_port_extension)) { 20169 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 20170 #if defined(BCM_GREYHOUND_SUPPORT) 20171 return bcm_gh_etag_ethertype_set(unit, arg); 20172 #endif /* BCM_GREYHOUND_SUPPORT */ 20173 } 20174 #if defined(BCM_TRIUMPH3_SUPPORT) 20175 else { 20176 return bcm_tr3_etag_ethertype_set(unit, arg); 20177 } 20178 #endif /* BCM_TRIUMPH3_SUPPORT */ 20179 } 20180 return BCM_E_UNAVAIL; 20181 break; 20182 case bcmSwitchExtenderMulticastLowerThreshold: 20183 if (soc_feature(unit, soc_feature_port_extension)) { 20184 BCM_IF_ERROR_RETURN( 20185 soc_reg_field32_modify(unit, ETAG_MULTICAST_RANGEr, 20186 REG_PORT_ANY, 20187 ETAG_VID_MULTICAST_LOWERf, arg)); 20188 if (SOC_REG_FIELD_VALID( 20189 unit, EGR_ETAG_MULTICAST_RANGEr, ETAG_VID_MULTICAST_LOWERf)) { 20190 BCM_IF_ERROR_RETURN( 20191 soc_reg_field32_modify(unit, EGR_ETAG_MULTICAST_RANGEr, 20192 REG_PORT_ANY, 20193 ETAG_VID_MULTICAST_LOWERf, arg)); 20194 } 20195 return BCM_E_NONE; 20196 } 20197 return BCM_E_UNAVAIL; 20198 break; 20199 case bcmSwitchExtenderMulticastHigherThreshold: 20200 if (soc_feature(unit, soc_feature_port_extension)) { 20201 BCM_IF_ERROR_RETURN( 20202 soc_reg_field32_modify(unit, ETAG_MULTICAST_RANGEr, 20203 REG_PORT_ANY, 20204 ETAG_VID_MULTICAST_UPPERf, arg)); 20205 if (SOC_REG_FIELD_VALID( 20206 unit, EGR_ETAG_MULTICAST_RANGEr, ETAG_VID_MULTICAST_UPPERf)) { 20207 BCM_IF_ERROR_RETURN( 20208 soc_reg_field32_modify(unit, EGR_ETAG_MULTICAST_RANGEr, 20209 REG_PORT_ANY, 20210 ETAG_VID_MULTICAST_UPPERf, arg)); 20211 } 20212 return BCM_E_NONE; 20213 } 20214 return BCM_E_UNAVAIL; 20215 break; 20216 #endif /* (BCM_TRIUMPH3_SUPPORT || BCM_GREYHOUND_SUPPORT) && INCLUDE_L3 */ 20217 20218 case bcmSwitchWESPProtocolEnable: 20219 if (soc_feature(unit, soc_feature_wesp)) { 20220 BCM_IF_ERROR_RETURN 20221 (soc_reg_field32_modify(unit, ING_WESP_PROTO_CONTROLr, 20222 REG_PORT_ANY, 20223 WESP_PROTO_NUMBER_ENABLEf, 20224 arg ? 1 : 0)); 20225 BCM_IF_ERROR_RETURN 20226 (soc_reg_field32_modify(unit, EGR_WESP_PROTO_CONTROLr, 20227 REG_PORT_ANY, 20228 WESP_PROTO_NUMBER_ENABLEf, 20229 arg ? 1 : 0)); 20230 return BCM_E_NONE; 20231 } 20232 return BCM_E_UNAVAIL; 20233 break; 20234 case bcmSwitchWESPProtocol: 20235 if (soc_feature(unit, soc_feature_wesp)) { 20236 if (arg < 0 || arg > 255) { 20237 return BCM_E_PARAM; 20238 } 20239 BCM_IF_ERROR_RETURN 20240 (soc_reg_field32_modify(unit, ING_WESP_PROTO_CONTROLr, 20241 REG_PORT_ANY, WESP_PROTO_NUMBERf, 20242 arg)); 20243 BCM_IF_ERROR_RETURN 20244 (soc_reg_field32_modify(unit, EGR_WESP_PROTO_CONTROLr, 20245 REG_PORT_ANY, WESP_PROTO_NUMBERf, 20246 arg)); 20247 return BCM_E_NONE; 20248 } 20249 return BCM_E_UNAVAIL; 20250 break; 20251 20252 #if defined(BCM_TRIDENT_SUPPORT) 20253 case bcmSwitchIp6CompressEnable: 20254 if (SOC_REG_FIELD_VALID(unit, ING_MISC_CONFIG2r, 20255 IPV6_TO_IPV4_ADDRESS_MAP_ENABLEf)) { 20256 BCM_IF_ERROR_RETURN 20257 (soc_reg_field32_modify(unit, ING_MISC_CONFIG2r, REG_PORT_ANY, 20258 IPV6_TO_IPV4_ADDRESS_MAP_ENABLEf, arg ? 1 : 0)); 20259 return BCM_E_NONE; 20260 } 20261 return BCM_E_UNAVAIL; 20262 break; 20263 20264 case bcmSwitchIp6CompressDefaultOffset: 20265 if (SOC_REG_FIELD_VALID(unit, ING_MISC_CONFIG2r, 20266 IPV6_TO_IPV4_MAP_OFFSET_DEFAULTf)) { 20267 if (arg < 0 || arg > 63) { 20268 return BCM_E_PARAM; 20269 } 20270 BCM_IF_ERROR_RETURN 20271 (soc_reg_field32_modify(unit, ING_MISC_CONFIG2r, REG_PORT_ANY, 20272 IPV6_TO_IPV4_MAP_OFFSET_DEFAULTf, arg)); 20273 return BCM_E_NONE; 20274 } 20275 return BCM_E_UNAVAIL; 20276 break; 20277 #endif /* !BCM_TRIDENT_SUPPORT */ 20278 case bcmSwitchMirrorPktChecksEnable: 20279 tmp_reg = EGR_CONFIG_1r; 20280 #if defined(BCM_TRIDENT3_SUPPORT) 20281 if (SOC_REG_IS_VALID(unit,EGR_CONFIG_1_64r)) { 20282 tmp_reg = EGR_CONFIG_1_64r; 20283 } 20284 #endif 20285 if (SOC_REG_FIELD_VALID(unit, tmp_reg, 20286 DISABLE_MIRROR_CHECKSf)) { 20287 BCM_IF_ERROR_RETURN 20288 (soc_reg_field32_modify(unit, tmp_reg, REG_PORT_ANY, 20289 DISABLE_MIRROR_CHECKSf, arg ? 0 : 1)); 20290 return BCM_E_NONE; 20291 } 20292 return BCM_E_UNAVAIL; 20293 break; 20294 20295 case bcmSwitchStableSaveLongIds: 20296 #if defined(BCM_FIELD_SUPPORT) && defined(BCM_WARM_BOOT_SUPPORT) 20297 { 20298 _field_control_t *fc; 20299 20300 rv = _field_control_get(unit, &fc); 20301 if (BCM_FAILURE(rv)) { 20302 return BCM_E_UNAVAIL; 20303 } 20304 20305 if (arg) { 20306 fc->flags |= _FP_STABLE_SAVE_LONG_IDS; 20307 } else { 20308 fc->flags &= ~_FP_STABLE_SAVE_LONG_IDS; 20309 } 20310 } 20311 return (BCM_E_NONE); 20312 #else 20313 return (BCM_E_UNAVAIL); 20314 #endif 20315 break; 20316 20317 #if defined(BCM_TRIUMPH_SUPPORT) 20318 case bcmSwitchGportAnyDefaultL2Learn: 20319 case bcmSwitchGportAnyDefaultL2Move: 20320 if (soc_feature(unit, soc_feature_virtual_switching)) { 20321 return _bcm_switch_default_cml_set(unit, type, arg); 20322 } 20323 return BCM_E_UNAVAIL; 20324 break; 20325 #endif /* BCM_TRIUMPH_SUPPORT */ 20326 20327 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 20328 case bcmSwitchOamCcmToCpu: 20329 if (soc_feature(unit, soc_feature_oam)) { 20330 if (soc_reg_field_valid(unit, CCM_COPYTO_CPU_CONTROLr, 20331 ERROR_CCM_COPY_TOCPUf)) { 20332 BCM_IF_ERROR_RETURN 20333 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 20334 REG_PORT_ANY, 20335 ERROR_CCM_COPY_TOCPUf, (arg ? 1 : 0))); 20336 return BCM_E_NONE; 20337 } 20338 } 20339 return BCM_E_UNAVAIL; 20340 break; 20341 20342 case bcmSwitchOamXconCcmToCpu: 20343 if (soc_feature(unit, soc_feature_oam)) { 20344 if (soc_reg_field_valid(unit, CCM_COPYTO_CPU_CONTROLr, 20345 XCON_CCM_COPY_TOCPUf)) { 20346 BCM_IF_ERROR_RETURN 20347 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 20348 REG_PORT_ANY, 20349 XCON_CCM_COPY_TOCPUf, (arg ? 1 : 0))); 20350 return BCM_E_NONE; 20351 } 20352 } 20353 return BCM_E_UNAVAIL; 20354 break; 20355 20356 case bcmSwitchOamXconOtherToCpu: 20357 if (soc_feature(unit, soc_feature_oam)) { 20358 if (soc_reg_field_valid(unit, CCM_COPYTO_CPU_CONTROLr, 20359 XCON_OTHER_COPY_TOCPUf)) { 20360 BCM_IF_ERROR_RETURN 20361 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 20362 REG_PORT_ANY, 20363 XCON_OTHER_COPY_TOCPUf, (arg ? 1 : 0))); 20364 return BCM_E_NONE; 20365 } 20366 } 20367 return BCM_E_UNAVAIL; 20368 break; 20369 #endif /* !BCM_TRIUMPH3_SUPPORT*/ 20370 #if (defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT)) 20371 case bcmSwitchSetMplsEntropyLabelTtl: 20372 if (soc_feature(unit, soc_feature_mpls_entropy) && 20373 soc_reg_field_valid(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, TTLf)) { 20374 BCM_IF_ERROR_RETURN 20375 (soc_reg_field32_modify(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, 20376 REG_PORT_ANY, TTLf, 20377 arg)); 20378 return BCM_E_NONE; 20379 } 20380 return BCM_E_UNAVAIL; 20381 break; 20382 case bcmSwitchSetMplsEntropyLabelPri: 20383 if (soc_feature(unit, soc_feature_mpls_entropy) && 20384 soc_reg_field_valid(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, TCf)) { 20385 BCM_IF_ERROR_RETURN 20386 (soc_reg_field32_modify(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, 20387 REG_PORT_ANY, TCf, 20388 arg)); 20389 return BCM_E_NONE; 20390 } 20391 return BCM_E_UNAVAIL; 20392 break; 20393 20394 case bcmSwitchSetMplsEntropyLabelOffset: 20395 if (soc_feature(unit, soc_feature_mpls_entropy) && 20396 soc_reg_field_valid(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, 20397 LABEL_OFFSETf)) { 20398 BCM_IF_ERROR_RETURN 20399 (soc_reg_field32_modify(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, 20400 REG_PORT_ANY, LABEL_OFFSETf, 20401 arg)); 20402 return BCM_E_NONE; 20403 } 20404 return BCM_E_UNAVAIL; 20405 break; 20406 #endif 20407 20408 #if defined(BCM_TRIUMPH2_SUPPORT) && defined(INCLUDE_L3) 20409 case bcmSwitchMultipathCompress: 20410 if (soc_feature(unit, soc_feature_l3) && 20411 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 20412 return bcm_tr2_l3_ecmp_defragment(unit); 20413 } 20414 break; 20415 20416 case bcmSwitchMultipathCompressBuffer: 20417 if (soc_feature(unit, soc_feature_l3) && 20418 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 20419 return bcm_tr2_l3_ecmp_defragment_buffer_set(unit, arg); 20420 } 20421 break; 20422 #endif /* BCM_TRIUMPH2_SUPPORT && INCLUDE_L3 */ 20423 20424 case bcmSwitchBstEnable: 20425 #if defined(BCM_TRIUMPH3_SUPPORT) 20426 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 20427 return _bcm_bst_cmn_control_set(unit, bcmSwitchBstEnable, arg); 20428 } 20429 #endif /* BCM_TRIUMPH3_SUPPORT */ 20430 return BCM_E_UNAVAIL; 20431 break; 20432 20433 case bcmSwitchBstTrackingMode: 20434 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 20435 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 20436 return _bcm_bst_cmn_control_set(unit, bcmSwitchBstTrackingMode, arg); 20437 } 20438 #endif /* BCM_TRIUMPH3_SUPPORT */ 20439 return BCM_E_UNAVAIL; 20440 break; 20441 case bcmSwitchBstSnapshotEnable: 20442 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 20443 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 20444 return _bcm_bst_cmn_control_set(unit, bcmSwitchBstSnapshotEnable, arg); 20445 } 20446 #endif /* BCM_TRIDENT2_SUPPORT */ 20447 return BCM_E_UNAVAIL; 20448 break; 20449 20450 #ifdef BCM_TRIDENT_SUPPORT 20451 case bcmSwitchFabricTrunkAutoIncludeDisable: 20452 if (!soc_feature(unit, soc_feature_modport_map_dest_is_port_or_trunk)) { 20453 return BCM_E_UNAVAIL; 20454 } 20455 return bcm_td_modport_map_mode_set(unit, type, arg); 20456 break; 20457 #endif /* BCM_TRIDENT_SUPPORT */ 20458 20459 case bcmSwitchL2OverflowEvent: 20460 #ifdef BCM_TRIDENT2_SUPPORT 20461 if ((SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIDENT3X(unit) || 20462 (SOC_IS_TOMAHAWKX(unit) && (!SOC_IS_TOMAHAWK3(unit)))) && 20463 soc_feature(unit, soc_feature_l2_overflow)) { 20464 if (arg) { 20465 SOC_CONTROL_LOCK(unit); 20466 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 20467 SOC_CONTROL_UNLOCK(unit); 20468 return soc_td2_l2_overflow_start(unit); 20469 } else { 20470 rv = soc_td2_l2_overflow_stop(unit); 20471 SOC_CONTROL_LOCK(unit); 20472 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 20473 SOC_CONTROL_UNLOCK(unit); 20474 return rv; 20475 } 20476 } else 20477 #endif/*BCM_TRIDENT2_SUPPORT*/ 20478 #ifdef BCM_TRIUMPH3_SUPPORT 20479 if (SOC_IS_TRIUMPH3(unit) && 20480 soc_feature(unit, soc_feature_l2_overflow)) { 20481 if (arg) { 20482 SOC_CONTROL_LOCK(unit); 20483 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 20484 SOC_CONTROL_UNLOCK(unit); 20485 return soc_tr3_l2_overflow_start(unit); 20486 } else { 20487 SOC_CONTROL_LOCK(unit); 20488 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 20489 SOC_CONTROL_UNLOCK(unit); 20490 return soc_tr3_l2_overflow_stop(unit); 20491 } 20492 } else 20493 #endif /* BCM_TRIUMPH3_SUPPORT */ 20494 #ifdef BCM_HURRICANE3_SUPPORT 20495 if ((SOC_IS_HURRICANE3(unit)) && 20496 soc_feature(unit, soc_feature_l2_overflow)) { 20497 if (arg) { 20498 SOC_CONTROL_LOCK(unit); 20499 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 20500 SOC_CONTROL_UNLOCK(unit); 20501 return soc_hr3_l2_overflow_start(unit); 20502 } else { 20503 SOC_CONTROL_LOCK(unit); 20504 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 20505 SOC_CONTROL_UNLOCK(unit); 20506 return soc_hr3_l2_overflow_stop(unit); 20507 } 20508 } else 20509 #endif /* BCM_HURRICANE3_SUPPORT */ 20510 #ifdef BCM_SCORPION_SUPPORT 20511 if (SOC_IS_SCORPION(unit) && 20512 soc_feature(unit, soc_feature_l2_overflow)) { 20513 if (arg) { 20514 SOC_CONTROL_LOCK(unit); 20515 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 20516 SOC_CONTROL_UNLOCK(unit); 20517 return soc_scorpion_l2_overflow_start(unit); 20518 } else { 20519 SOC_CONTROL_LOCK(unit); 20520 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 20521 SOC_CONTROL_UNLOCK(unit); 20522 return soc_scorpion_l2_overflow_stop(unit); 20523 } 20524 } else 20525 #endif /* BCM_SCORPION_SUPPORT */ 20526 20527 { 20528 return BCM_E_UNAVAIL; 20529 } 20530 break; 20531 20532 #if (defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_TRIDENT_SUPPORT)) \ 20533 && defined(INCLUDE_L3) 20534 case bcmSwitchMiMDefaultSVPValue: 20535 { 20536 int mim_svp = 0; 20537 if (BCM_GPORT_IS_SET(arg)) { 20538 if((mim_svp = BCM_GPORT_MIM_PORT_ID_GET(arg)) == -1) { 20539 return BCM_E_PARAM; 20540 } 20541 } 20542 else { 20543 mim_svp = arg; 20544 } 20545 if (SOC_REG_IS_VALID(unit, MIM_DEFAULT_NETWORK_SVPr)) { 20546 SOC_IF_ERROR_RETURN( 20547 soc_reg_field32_modify(unit, MIM_DEFAULT_NETWORK_SVPr, 20548 REG_PORT_ANY, SVPf, mim_svp)); 20549 #if defined(BCM_TRIDENT3_SUPPORT) 20550 if (SOC_REG_IS_VALID(unit, DEFAULT_SVP_ENABLEr)) { 20551 rv = soc_reg_field32_modify 20552 (unit, DEFAULT_SVP_ENABLEr, REG_PORT_ANY, 20553 MIM_ENABLE_DEFAULT_NETWORK_SVPf, mim_svp?1:0); 20554 if (!(rv == BCM_E_NONE || rv == BCM_E_NOT_FOUND)) { 20555 return rv; 20556 } 20557 } 20558 #endif 20559 return BCM_E_NONE; 20560 } else if (soc_feature(unit, 20561 soc_feature_mim_reserve_default_port)) { 20562 SOC_IF_ERROR_RETURN( 20563 soc_reg_field32_modify(unit, ING_Q_BEGINr, 20564 REG_PORT_ANY, ENABLE_DEFAULT_NETWORK_SVPf, 20565 mim_svp ? 1: 0)); 20566 return BCM_E_NONE; 20567 } 20568 else { 20569 return BCM_E_UNAVAIL; 20570 } 20571 } 20572 break; 20573 #endif 20574 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 20575 case bcmSwitchIpmcSameVlanPruning: 20576 #ifdef BCM_TOMAHAWK3_SUPPORT 20577 if(SOC_IS_TOMAHAWK3(unit)) { 20578 BCM_IF_ERROR_RETURN( 20579 soc_reg_field32_modify(unit, MMU_RQE_REPL_CONFIGr, REG_PORT_ANY, 20580 IPMC_IND_MODEf, (arg ? 0 : 1))); 20581 return BCM_E_NONE; 20582 } else 20583 #endif 20584 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_HELIX4(unit) || 20585 SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit)) { 20586 BCM_IF_ERROR_RETURN( 20587 soc_reg_field32_modify(unit, ING_MISC_CONFIGr, REG_PORT_ANY, 20588 IPMC_IND_MODEf, (arg ? 0 : 1))); 20589 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_HELIX4(unit)) { 20590 BCM_IF_ERROR_RETURN( 20591 soc_reg_field32_modify(unit, MCQ_CONFIGr, REG_PORT_ANY, 20592 IPMC_IND_MODEf, (arg ? 0 : 1))); 20593 } else if (SOC_IS_TRIDENT2X(unit)) { 20594 BCM_IF_ERROR_RETURN( 20595 soc_reg_field32_modify(unit, TOQ_MC_CFG0r, REG_PORT_ANY, 20596 IPMC_IND_MODEf, (arg ? 0 : 1))); 20597 } else if (SOC_IS_TOMAHAWKX(unit)) { 20598 BCM_IF_ERROR_RETURN( 20599 soc_reg_field32_modify(unit, MMU_SCFG_TOQ_MC_CFG0r, REG_PORT_ANY, 20600 IPMC_IND_MODEf, (arg ? 0 : 1))); 20601 } 20602 return BCM_E_NONE; 20603 } 20604 break; 20605 #endif 20606 #if defined(BCM_KATANA2_SUPPORT) 20607 case bcmSwitchOamHeaderErrorToCpu: 20608 if (soc_feature(unit, soc_feature_oam)) { 20609 if (SOC_IS_SABER2(unit)){ 20610 BCM_IF_ERROR_RETURN 20611 (soc_reg_field32_modify(unit, OAM_COPYTO_CPU_CONTROLr, 20612 REG_PORT_ANY, 20613 OAM_HEADER_ERROR_TOCPUf, 20614 (arg ? 1 : 0))); 20615 BCM_IF_ERROR_RETURN 20616 (soc_reg_field32_modify(unit, 20617 OAM_COPYTO_CPU_CONTROL_FP_MEPSr, 20618 REG_PORT_ANY, 20619 OAM_HEADER_ERROR_TOCPUf, 20620 (arg ? 1 : 0))); 20621 BCM_IF_ERROR_RETURN 20622 (soc_reg_field32_modify(unit, 20623 EGR_OAM_COPYTO_CPU_CONTROLr, 20624 REG_PORT_ANY, 20625 OAM_HEADER_ERROR_TOCPUf, 20626 (arg ? 1 : 0))); 20627 return BCM_E_NONE; 20628 } else if (SOC_IS_KATANA2(unit)) { 20629 BCM_IF_ERROR_RETURN 20630 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 20631 REG_PORT_ANY, 20632 OAM_HEADER_ERROR_TOCPUf, 20633 (arg ? 1 : 0))); 20634 BCM_IF_ERROR_RETURN 20635 (soc_reg_field32_modify(unit, EGR_CPU_CONTROLr, 20636 REG_PORT_ANY, 20637 OAM_HEADER_ERROR_TOCPUf, 20638 (arg ? 1 : 0))); 20639 return BCM_E_NONE; 20640 } 20641 } 20642 break; 20643 20644 case bcmSwitchOamUnknownVersionToCpu: 20645 if (soc_feature(unit, soc_feature_oam)) { 20646 if (SOC_IS_SABER2(unit)){ 20647 BCM_IF_ERROR_RETURN 20648 (soc_reg_field32_modify(unit, OAM_COPYTO_CPU_CONTROLr, 20649 REG_PORT_ANY, 20650 OAM_UNKNOWN_OPCODE_VERSION_TOCPUf, 20651 (arg ? 1 : 0))); 20652 BCM_IF_ERROR_RETURN 20653 (soc_reg_field32_modify(unit, 20654 OAM_COPYTO_CPU_CONTROL_FP_MEPSr, 20655 REG_PORT_ANY, 20656 OAM_UNKNOWN_OPCODE_VERSION_TOCPUf, 20657 (arg ? 1 : 0))); 20658 BCM_IF_ERROR_RETURN 20659 (soc_reg_field32_modify(unit, 20660 EGR_OAM_COPYTO_CPU_CONTROLr, 20661 REG_PORT_ANY, 20662 OAM_UNKNOWN_OPCODE_VERSION_TOCPUf, 20663 (arg ? 1 : 0))); 20664 return BCM_E_NONE; 20665 } else if (SOC_IS_KATANA2(unit)) { 20666 BCM_IF_ERROR_RETURN 20667 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 20668 REG_PORT_ANY, 20669 OAM_UNKNOWN_OPCODE_VERSION_TOCPUf, 20670 (arg ? 1 : 0))); 20671 BCM_IF_ERROR_RETURN 20672 (soc_reg_field32_modify(unit, EGR_CPU_CONTROLr, 20673 REG_PORT_ANY, 20674 OAM_UNKNOWN_VERSION_TOCPUf, 20675 (arg ? 1 : 0))); 20676 return BCM_E_NONE; 20677 } 20678 } 20679 break; 20680 20681 case bcmSwitchOamUnknownVersionDrop: 20682 if (SOC_IS_KATANA2(unit) && (soc_feature(unit, soc_feature_oam))) { 20683 BCM_IF_ERROR_RETURN 20684 (soc_reg_field32_modify(unit, OAM_DROP_CONTROLr, 20685 REG_PORT_ANY, 20686 IFP_OAM_UNKNOWN_OPCODE_VERSION_DROPf, (arg ? 1 : 0))); 20687 return BCM_E_NONE; 20688 } 20689 break; 20690 20691 case bcmSwitchOamUnexpectedPktToCpu: 20692 if (soc_feature(unit, soc_feature_oam)) { 20693 if (SOC_IS_SABER2(unit)){ 20694 BCM_IF_ERROR_RETURN 20695 (soc_reg_field32_modify(unit, OAM_COPYTO_CPU_CONTROLr, 20696 REG_PORT_ANY, 20697 OAM_UNEXPECTED_PKT_TOCPUf, 20698 (arg ? 1 : 0))); 20699 BCM_IF_ERROR_RETURN 20700 (soc_reg_field32_modify(unit, 20701 OAM_COPYTO_CPU_CONTROL_FP_MEPSr, 20702 REG_PORT_ANY, 20703 OAM_UNEXPECTED_PKT_TOCPUf, 20704 (arg ? 1 : 0))); 20705 BCM_IF_ERROR_RETURN 20706 (soc_reg_field32_modify(unit, 20707 EGR_OAM_COPYTO_CPU_CONTROLr, 20708 REG_PORT_ANY, 20709 OAM_UNEXPECTED_PKT_TOCPUf, 20710 (arg ? 1 : 0))); 20711 return BCM_E_NONE; 20712 } else if (SOC_IS_KATANA2(unit)) { 20713 BCM_IF_ERROR_RETURN 20714 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 20715 REG_PORT_ANY, 20716 OAM_UNEXPECTED_PKT_TOCPUf, 20717 (arg ? 1 : 0))); 20718 BCM_IF_ERROR_RETURN 20719 (soc_reg_field32_modify(unit, EGR_CPU_CONTROLr, 20720 REG_PORT_ANY, 20721 OAM_UNEXPECTED_PKT_TOCPUf, 20722 (arg ? 1 : 0))); 20723 return BCM_E_NONE; 20724 } 20725 } 20726 break; 20727 20728 case bcmSwitchOamVersionCheckDisable: 20729 if (soc_feature(unit, soc_feature_oam)) { 20730 if (SOC_IS_SABER2(unit)){ 20731 BCM_IF_ERROR_RETURN 20732 (soc_reg_field32_modify(unit, OAM_ERROR_CONTROLr, 20733 REG_PORT_ANY, 20734 OAM_VER_CHECK_DISABLEf, 20735 (arg ? 1 : 0))); 20736 BCM_IF_ERROR_RETURN 20737 (soc_reg_field32_modify(unit, 20738 OAM_ERROR_CONTROL_FP_MEPSr, 20739 REG_PORT_ANY, 20740 OAM_VER_CHECK_DISABLEf, 20741 (arg ? 1 : 0))); 20742 BCM_IF_ERROR_RETURN 20743 (soc_reg_field32_modify(unit, 20744 EGR_OAM_ERROR_CONTROLr, 20745 REG_PORT_ANY, 20746 OAM_VER_CHECK_DISABLEf, 20747 (arg ? 1 : 0))); 20748 return BCM_E_NONE; 20749 } else if (SOC_IS_KATANA2(unit)) { 20750 BCM_IF_ERROR_RETURN 20751 (soc_reg_field32_modify(unit, OAM_CONTROL_1r, 20752 REG_PORT_ANY, 20753 OAM_VER_CHECK_DISABLEf, 20754 (arg ? 1 : 0))); 20755 BCM_IF_ERROR_RETURN 20756 (soc_reg_field32_modify(unit, EGR_OAM_ERROR_CONTROLr, 20757 REG_PORT_ANY, 20758 OAM_VER_CHECK_DISABLEf, 20759 (arg ? 1 : 0))); 20760 return BCM_E_NONE; 20761 } 20762 } 20763 return BCM_E_UNAVAIL; 20764 break; 20765 #endif 20766 #if defined(BCM_OLP_SUPPORT) 20767 case bcmSwitchOamOlpChipEtherType: 20768 if (soc_feature(unit, soc_feature_olp)) { 20769 arg &= _BCM_SWITCH_ETHERTYPE_VLAN_TAG_MASK; 20770 BCM_IF_ERROR_RETURN 20771 (soc_reg_field32_modify(unit, IARB_OLP_CONFIGr, 20772 REG_PORT_ANY, ETHERTYPEf, arg)); 20773 #if defined (BCM_APACHE_SUPPORT) 20774 if (soc_feature(unit, soc_feature_ep_redirect_v2) || SOC_IS_MONTEREY(unit)) { 20775 BCM_IF_ERROR_RETURN 20776 (soc_mem_field32_modify(unit, EGR_OLP_CONFIG_1m, 20777 0, ETHERTYPEf, arg)); 20778 BCM_IF_ERROR_RETURN 20779 (soc_mem_field32_modify(unit, EGR_OLP_CONFIG_2m, 20780 0, ETHERTYPEf, arg)); 20781 20782 } else 20783 #endif 20784 { 20785 BCM_IF_ERROR_RETURN 20786 (soc_mem_field32_modify(unit, EGR_OLP_CONFIGm, 20787 0, ETHERTYPEf, arg)); 20788 } 20789 return BCM_E_NONE; 20790 } 20791 20792 return BCM_E_UNAVAIL; 20793 break; 20794 20795 20796 case bcmSwitchOamOlpChipTpid: 20797 if (soc_feature(unit, soc_feature_olp)) { 20798 arg &= _BCM_SWITCH_ETHERTYPE_VLAN_TAG_MASK; 20799 BCM_IF_ERROR_RETURN 20800 (soc_reg_field32_modify(unit, IARB_OLP_CONFIG_1r, 20801 REG_PORT_ANY, VLAN_TPIDf, arg)); 20802 #if defined (BCM_APACHE_SUPPORT) 20803 if (soc_feature(unit, soc_feature_ep_redirect_v2) || SOC_IS_MONTEREY(unit)) { 20804 BCM_IF_ERROR_RETURN 20805 (soc_mem_field32_modify(unit, EGR_OLP_CONFIG_1m, 20806 0, VLAN_TPIDf, arg)); 20807 BCM_IF_ERROR_RETURN 20808 (soc_mem_field32_modify(unit, EGR_OLP_CONFIG_2m, 20809 0, VLAN_TPIDf, arg)); 20810 20811 } else 20812 #endif 20813 { 20814 BCM_IF_ERROR_RETURN 20815 (soc_mem_field32_modify(unit, EGR_OLP_CONFIGm, 20816 0, VLAN_TPIDf, arg)); 20817 } 20818 20819 return BCM_E_NONE; 20820 } 20821 return BCM_E_UNAVAIL; 20822 break; 20823 20824 20825 case bcmSwitchOamOlpChipVlan: 20826 if (soc_feature(unit, soc_feature_olp)) { 20827 arg &= _BCM_SWITCH_ETHERTYPE_VLAN_TAG_MASK; 20828 BCM_IF_ERROR_RETURN 20829 (soc_reg_field32_modify(unit, EGR_OLP_VLANr, 20830 REG_PORT_ANY, VLAN_TAGf, arg)); 20831 BCM_IF_ERROR_RETURN 20832 (soc_reg_field32_modify(unit, IARB_OLP_CONFIG_1r, 20833 REG_PORT_ANY, VLAN_IDf, arg)); 20834 #if defined (BCM_APACHE_SUPPORT) 20835 if (soc_feature(unit, soc_feature_ep_redirect_v2) || SOC_IS_MONTEREY(unit)) { 20836 BCM_IF_ERROR_RETURN 20837 (soc_reg_field32_modify(unit, EGR_OLP_VLAN_1r, 20838 REG_PORT_ANY, VLAN_TAGf, arg)); 20839 } 20840 #endif 20841 return BCM_E_NONE; 20842 } 20843 return BCM_E_UNAVAIL; 20844 break; 20845 20846 case bcmSwitchOamOlpStationMacNonOui: 20847 case bcmSwitchOamOlpStationMacOui: 20848 if (soc_feature(unit, soc_feature_olp)) { 20849 if (_BCM_SWITCH_OLP_APIV(unit) != _BCM_SWITCH_OLP_L2_STATION_API) { 20850 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_TRUE_API); 20851 return _bcm_switch_xgs_mac_set(unit, type, arg); 20852 } 20853 } 20854 return BCM_E_UNAVAIL; 20855 break; 20856 #endif /* BCM_OLP_SUPPORT*/ 20857 #if defined(BCM_SABER2_SUPPORT) 20858 case bcmSwitchOamStackingSupport: 20859 if (SOC_IS_SABER2(unit)) { 20860 BCM_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 20861 EGR_HG_PPD0_RX_VC_LABEL_OVERLAY_CONTROLr, 20862 REG_PORT_ANY, VC_LABEL_OVERLAY_TYPEf, arg)); 20863 return BCM_E_NONE; 20864 } 20865 return BCM_E_UNAVAIL; 20866 break; 20867 #endif /* BCM_SABER2_SUPPORT */ 20868 case bcmSwitchFieldStageEgressToCpu: 20869 if (soc_feature(unit, soc_feature_field_egress_tocpu)) { 20870 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, EGR_CPU_CONTROLr, 20871 REG_PORT_ANY, EFP_TOCPUf, arg)); 20872 return BCM_E_NONE; 20873 } 20874 return BCM_E_UNAVAIL; 20875 break; 20876 case bcmSwitchSystemReservedVlan: 20877 return _bcm_esw_vlan_system_reserved_set(unit, arg); 20878 #if defined(BCM_KATANA2_SUPPORT) 20879 case bcmSwitchHashOamEgress: 20880 case bcmSwitchHashOamEgressDual: 20881 if (SOC_IS_KATANA2(unit)) { 20882 return _bcm_fb_er_hashselect_set(unit, type, arg); 20883 } 20884 return BCM_E_UNAVAIL; 20885 break; 20886 #endif /* BCM_KATANA2_SUPPORT */ 20887 #if defined (BCM_SABER2_SUPPORT) 20888 case bcmSwitchHashOam: 20889 case bcmSwitchHashOamDual: 20890 if (SOC_IS_SABER2(unit)) { 20891 return _bcm_fb_er_hashselect_set(unit, type, arg); 20892 } 20893 return BCM_E_UNAVAIL; 20894 break; 20895 #endif /* BCM_SABER2_SUPPORT */ 20896 case bcmSwitchHashOamLeastFull: 20897 case bcmSwitchHashDualMoveDepthOam: 20898 /* Not supported for now */ 20899 return BCM_E_UNAVAIL; 20900 break; 20901 #if defined(BCM_ENDURO_SUPPORT) 20902 case bcmSwitchWredForAllPkts: 20903 if(SOC_IS_ENDURO(unit)) { 20904 BCM_IF_ERROR_RETURN 20905 (soc_reg_field32_modify(unit, ING_MISC_CONFIGr, 20906 REG_PORT_ANY, TREAT_ALL_PKTS_AS_TCPf, arg ? 1 : 0)); 20907 return BCM_E_NONE; 20908 } 20909 return BCM_E_UNAVAIL; 20910 break; 20911 #endif /* BCM_ENDURO_SUPPORT */ 20912 #if defined(BCM_TRIDENT2_SUPPORT) 20913 20914 case bcmSwitchFcoeNpvModeEnable: 20915 if (soc_feature(unit, soc_feature_fcoe)) { 20916 #ifdef BCM_TRIDENT3_SUPPORT 20917 if (SOC_IS_TRIDENT3X(unit)) { 20918 int port; 20919 PBMP_E_ITER(unit, port) { 20920 BCM_IF_ERROR_RETURN( 20921 _bcm_esw_port_tab_set(unit, port, _BCM_CPU_TABS_BOTH, 20922 FCOE_NPV_MODEf, (arg) ? 1 : 0)); 20923 } 20924 } else 20925 #endif 20926 { 20927 return soc_reg_field32_modify(unit, FCOE_ING_CONTROLr, 20928 REG_PORT_ANY, FCOE_NPV_MODEf, 20929 (arg) ? 1 : 0); 20930 } 20931 } 20932 break; 20933 20934 case bcmSwitchFcoeDomainRoutePrefixLength: 20935 if (soc_feature(unit, soc_feature_fcoe)) { 20936 20937 /* 5 bits value but only 1-24 is valid */ 20938 if ((arg >= 1) && (arg <= 24)) { 20939 return soc_reg_field32_modify(unit, FCOE_ING_CONTROLr, 20940 REG_PORT_ANY, 20941 FCOE_DOMAIN_ROUTE_PREFIXf, 20942 arg); 20943 } else { 20944 return BCM_E_PARAM; 20945 } 20946 } 20947 break; 20948 20949 case bcmSwitchFcoeCutThroughEnable: 20950 if (soc_feature(unit, soc_feature_fcoe)) { 20951 return soc_reg_field32_modify(unit, FCOE_ING_CONTROLr, 20952 REG_PORT_ANY, 20953 FCOE_CUT_THROUGH_ENABLEf, 20954 (arg) ? 1 : 0); 20955 } 20956 break; 20957 20958 case bcmSwitchFcoeSourceBindCheckAction: 20959 if (soc_feature(unit, soc_feature_fcoe)) { 20960 return soc_reg_field32_modify(unit, FCOE_ING_CONTROLr, 20961 REG_PORT_ANY, 20962 FCOE_SRC_BIND_CHECK_ACTIONf, 20963 (arg) ? 1 : 0); 20964 } 20965 break; 20966 20967 case bcmSwitchFcoeSourceFpmaPrefixCheckAction: 20968 if (soc_feature(unit, soc_feature_fcoe)) { 20969 return soc_reg_field32_modify( 20970 unit, FCOE_ING_CONTROLr, 20971 REG_PORT_ANY, 20972 FCOE_SRC_FPMA_PREFIX_CHECK_ACTIONf, 20973 (arg) ? 1 : 0); 20974 } 20975 break; 20976 20977 case bcmSwitchFcoeVftHopCountExpiryToCpu: 20978 if (soc_feature(unit, soc_feature_fcoe)) { 20979 #ifdef BCM_TRIDENT3_SUPPORT 20980 if (SOC_IS_TRIDENT3X(unit)) { 20981 return (BCM_E_UNAVAIL); 20982 } else 20983 #endif /* BCM_TRIDENT3_SUPPORT */ 20984 { 20985 return soc_reg_field32_modify(unit, CPU_CONTROL_0r, 20986 REG_PORT_ANY, 20987 FCOE_VFT_HOPCOUNT_TOCPUf, 20988 (arg) ? 1 : 0); 20989 } 20990 } 20991 break; 20992 20993 case bcmSwitchFcoeVftHopCountExpiryAction: 20994 if (soc_feature(unit, soc_feature_fcoe)) { 20995 #ifdef BCM_TRIDENT3_SUPPORT 20996 if (SOC_IS_TRIDENT3X(unit)) { 20997 uint64 r_val64; 20998 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1_64r(unit, &r_val64)); 20999 soc_reg64_field32_set(unit, EGR_CONFIG_1_64r, &r_val64, 21000 FCOE_VFT_HOPCOUNT_EXPIRE_CONTROLf, 21001 (arg) ? 1 : 0); 21002 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1_64r(unit, r_val64)); 21003 } else 21004 #endif 21005 { 21006 BCM_IF_ERROR_RETURN( 21007 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21008 FCOE_VFT_HOPCOUNT_EXPIRE_CONTROLf, 21009 (arg) ? 1 : 0)); 21010 } 21011 return BCM_E_NONE; 21012 } 21013 break; 21014 21015 case bcmSwitchFcoeFcEofT1Value: 21016 if (soc_feature(unit, soc_feature_fcoe)) { 21017 #ifdef BCM_TRIDENT3_SUPPORT 21018 if (SOC_IS_TRIDENT3X(unit)) { 21019 BCM_IF_ERROR_RETURN( 21020 soc_reg_field32_modify(unit, EGR_FCOE_EOFr, REG_PORT_ANY, 21021 FCOE_FC_EOF_T_1f, arg)); 21022 } else 21023 #endif 21024 { 21025 BCM_IF_ERROR_RETURN( 21026 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21027 FCOE_FC_EOF_T_1f, arg)); 21028 } 21029 return BCM_E_NONE; 21030 } 21031 break; 21032 21033 case bcmSwitchFcoeFcEofT2Value: 21034 if (soc_feature(unit, soc_feature_fcoe)) { 21035 #ifdef BCM_TRIDENT3_SUPPORT 21036 if (SOC_IS_TRIDENT3X(unit)) { 21037 BCM_IF_ERROR_RETURN( 21038 soc_reg_field32_modify(unit, EGR_FCOE_EOFr, REG_PORT_ANY, 21039 FCOE_FC_EOF_T_2f, arg)); 21040 } else 21041 #endif 21042 { 21043 BCM_IF_ERROR_RETURN( 21044 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21045 FCOE_FC_EOF_T_2f, arg)); 21046 } 21047 return BCM_E_NONE; 21048 } 21049 break; 21050 21051 case bcmSwitchFcoeFcEofA1Value: 21052 if (soc_feature(unit, soc_feature_fcoe)) { 21053 #ifdef BCM_TRIDENT3_SUPPORT 21054 if (SOC_IS_TRIDENT3X(unit)) { 21055 uint64 r_val64; 21056 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &r_val64)); 21057 soc_reg64_field32_set(unit, EGR_FCOE_EOFr, &r_val64, 21058 FCOE_FC_EOF_A_1f, arg); 21059 SOC_IF_ERROR_RETURN(WRITE_EGR_FCOE_EOFr(unit, r_val64)); 21060 } else 21061 #endif 21062 { 21063 BCM_IF_ERROR_RETURN( 21064 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21065 FCOE_FC_EOF_A_1f, arg)); 21066 } 21067 return BCM_E_NONE; 21068 } 21069 break; 21070 21071 case bcmSwitchFcoeFcEofA2Value: 21072 if (soc_feature(unit, soc_feature_fcoe)) { 21073 #ifdef BCM_TRIDENT3_SUPPORT 21074 if (SOC_IS_TRIDENT3X(unit)) { 21075 uint64 r_val64; 21076 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &r_val64)); 21077 soc_reg64_field32_set(unit, EGR_FCOE_EOFr, &r_val64, 21078 FCOE_FC_EOF_A_2f, arg); 21079 SOC_IF_ERROR_RETURN(WRITE_EGR_FCOE_EOFr(unit, r_val64)); 21080 } else 21081 #endif 21082 { 21083 BCM_IF_ERROR_RETURN( 21084 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21085 FCOE_FC_EOF_A_2f, arg)); 21086 } 21087 return BCM_E_NONE; 21088 } 21089 break; 21090 21091 case bcmSwitchFcoeFcEofN1Value: 21092 if (soc_feature(unit, soc_feature_fcoe)) { 21093 #ifdef BCM_TRIDENT3_SUPPORT 21094 if (SOC_IS_TRIDENT3X(unit)) { 21095 uint64 r_val64; 21096 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &r_val64)); 21097 soc_reg64_field32_set(unit, EGR_FCOE_EOFr, &r_val64, 21098 FCOE_FC_EOF_N_1f, arg); 21099 SOC_IF_ERROR_RETURN(WRITE_EGR_FCOE_EOFr(unit, r_val64)); 21100 } else 21101 #endif 21102 { 21103 BCM_IF_ERROR_RETURN( 21104 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21105 FCOE_FC_EOF_N_1f, arg)); 21106 } 21107 return BCM_E_NONE; 21108 } 21109 break; 21110 21111 case bcmSwitchFcoeFcEofN2Value: 21112 if (soc_feature(unit, soc_feature_fcoe)) { 21113 #ifdef BCM_TRIDENT3_SUPPORT 21114 if (SOC_IS_TRIDENT3X(unit)) { 21115 uint64 r_val64; 21116 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &r_val64)); 21117 soc_reg64_field32_set(unit, EGR_FCOE_EOFr, &r_val64, 21118 FCOE_FC_EOF_N_2f, arg); 21119 SOC_IF_ERROR_RETURN(WRITE_EGR_FCOE_EOFr(unit, r_val64)); 21120 } else 21121 #endif 21122 { 21123 BCM_IF_ERROR_RETURN( 21124 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21125 FCOE_FC_EOF_N_2f, arg)); 21126 } 21127 return BCM_E_NONE; 21128 } 21129 break; 21130 21131 case bcmSwitchFcoeFcEofNI1Value: 21132 if (soc_feature(unit, soc_feature_fcoe)) { 21133 #ifdef BCM_TRIDENT3_SUPPORT 21134 if (SOC_IS_TRIDENT3X(unit)) { 21135 uint64 r_val64; 21136 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &r_val64)); 21137 soc_reg64_field32_set(unit, EGR_FCOE_EOFr, &r_val64, 21138 FCOE_FC_EOF_NI_1f, arg); 21139 SOC_IF_ERROR_RETURN(WRITE_EGR_FCOE_EOFr(unit, r_val64)); 21140 } else 21141 #endif 21142 { 21143 BCM_IF_ERROR_RETURN( 21144 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21145 FCOE_FC_EOF_NI_1f, arg)); 21146 } 21147 return BCM_E_NONE; 21148 } 21149 break; 21150 21151 case bcmSwitchFcoeFcEofNI2Value: 21152 if (soc_feature(unit, soc_feature_fcoe)) { 21153 #ifdef BCM_TRIDENT3_SUPPORT 21154 if (SOC_IS_TRIDENT3X(unit)) { 21155 uint64 r_val64; 21156 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &r_val64)); 21157 soc_reg64_field32_set(unit, EGR_FCOE_EOFr, &r_val64, 21158 FCOE_FC_EOF_NI_2f, arg); 21159 SOC_IF_ERROR_RETURN(WRITE_EGR_FCOE_EOFr(unit, r_val64)); 21160 } else 21161 #endif 21162 { 21163 BCM_IF_ERROR_RETURN( 21164 soc_mem_field32_modify(unit, EGR_FCOE_CONTROL_1m, 0, 21165 FCOE_FC_EOF_NI_2f, arg)); 21166 } 21167 return BCM_E_NONE; 21168 } 21169 break; 21170 21171 case bcmSwitchFcoeZoneCheckFailToCpu: 21172 if (soc_feature(unit, soc_feature_fcoe)) { 21173 return soc_reg_field32_modify(unit, CPU_CONTROL_Mr, 21174 REG_PORT_ANY, 21175 FCOE_ZONE_CHECK_FAIL_COPY_TOCPUf, 21176 (arg) ? 1 : 0); 21177 } 21178 break; 21179 21180 case bcmSwitchFcoeZoneCheckMissDrop: 21181 if (soc_feature(unit, soc_feature_fcoe)) { 21182 return soc_reg_field32_modify(unit, ING_MISC_CONFIG2r, 21183 REG_PORT_ANY, 21184 FCOE_ZONE_CHECK_MISS_DROPf, 21185 (arg) ? 1 : 0); 21186 } 21187 break; 21188 case bcmSwitchHWL2Freeze: 21189 if (SOC_IS_TD2_TT2(unit)) { 21190 if (arg == 0) { 21191 return soc_l2x_selective_thaw(unit, SOC_L2X_FROZEN_WITHOUT_LOCK); 21192 } else { 21193 return soc_l2x_selective_freeze(unit, SOC_L2X_FROZEN_WITHOUT_LOCK); 21194 } 21195 } 21196 break; 21197 #endif /* BCM_TRIDENT2_SUPPORT */ 21198 case bcmSwitchUnknownSubportPktTagToCpu: 21199 if (soc_feature(unit, soc_feature_subtag_coe) || 21200 soc_feature(unit, soc_feature_hgproxy_subtag_coe)) { 21201 if (soc_reg_field_valid(unit, CPU_CONTROL_1r, 21202 UNKNOWN_SUBTENDING_PORT_TOCPUf)) { 21203 return soc_reg_field32_modify(unit, CPU_CONTROL_1r, 21204 REG_PORT_ANY, 21205 UNKNOWN_SUBTENDING_PORT_TOCPUf, 21206 (arg) ? 1 : 0); 21207 } 21208 } 21209 break; 21210 21211 #ifdef BCM_TRIDENT_SUPPORT 21212 case bcmSwitchMirrorUnicastCosq: 21213 if (soc_feature(unit, soc_feature_mirror_cos)) { 21214 return _bcm_td_mirror_uc_cos_set(unit, arg); 21215 } 21216 break; 21217 21218 case bcmSwitchMirrorMulticastCosq: 21219 if (soc_feature(unit, soc_feature_mirror_cos)) { 21220 return _bcm_td_mirror_mc_cos_set(unit, arg); 21221 } 21222 break; 21223 #ifdef BCM_TOMAHAWK3_SUPPORT 21224 case bcmSwitchMirrorCpuCosq: 21225 if (soc_feature(unit, soc_feature_mirror_cos)) { 21226 return _bcm_th3_mirror_cpu_cos_set(unit, arg); 21227 } 21228 break; 21229 #endif /* BCM_TOMAHAWK3_SUPPORT */ 21230 #endif 21231 21232 case bcmSwitchEEEQueueThresholdProfile0: 21233 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21234 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_0r, 21235 REG_PORT_ANY, 21236 EEE_QUEUE_THRESHOLDf, 21237 arg); 21238 } 21239 break; 21240 case bcmSwitchEEEQueueThresholdProfile1: 21241 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21242 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_1r, 21243 REG_PORT_ANY, 21244 EEE_QUEUE_THRESHOLDf, 21245 arg); 21246 } 21247 break; 21248 case bcmSwitchEEEQueueThresholdProfile2: 21249 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21250 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_2r, 21251 REG_PORT_ANY, 21252 EEE_QUEUE_THRESHOLDf, 21253 arg); 21254 } 21255 break; 21256 case bcmSwitchEEEQueueThresholdProfile3: 21257 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21258 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_3r, 21259 REG_PORT_ANY, 21260 EEE_QUEUE_THRESHOLDf, 21261 arg); 21262 } 21263 break; 21264 case bcmSwitchEEEPacketLatencyProfile0: 21265 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21266 uint32 fval = 0; 21267 fval = arg; 21268 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_0r, 21269 REG_PORT_ANY, 21270 EEE_MAX_PKT_LATENCYf, 21271 fval); 21272 } 21273 break; 21274 case bcmSwitchEEEPacketLatencyProfile1: 21275 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21276 uint32 fval = 0; 21277 fval = arg; 21278 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_1r, 21279 REG_PORT_ANY, 21280 EEE_MAX_PKT_LATENCYf, 21281 fval); 21282 } 21283 break; 21284 case bcmSwitchEEEPacketLatencyProfile2: 21285 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21286 uint32 fval = 0; 21287 fval = arg; 21288 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_2r, 21289 REG_PORT_ANY, 21290 EEE_MAX_PKT_LATENCYf, 21291 fval); 21292 } 21293 break; 21294 case bcmSwitchEEEPacketLatencyProfile3: 21295 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21296 uint32 fval = 0; 21297 fval = arg; 21298 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_3r, 21299 REG_PORT_ANY, 21300 EEE_MAX_PKT_LATENCYf, 21301 fval); 21302 } 21303 break; 21304 case bcmSwitchEEEGlobalCongestionThreshold: 21305 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 21306 return soc_reg_field32_modify(unit, EEE_GLOBAL_BUF_THRESHr, 21307 REG_PORT_ANY, 21308 EEE_GLOBAL_BUFFER_THREHSOLDf, 21309 arg); 21310 } 21311 break; 21312 21313 #if defined(BCM_KATANA2_SUPPORT) 21314 case bcmSwitchUnknownVlanToCpu: 21315 case bcmSwitchStgInvalidToCpu: 21316 case bcmSwitchVlanTranslateEgressMissToCpu: 21317 case bcmSwitchTunnelErrToCpu: 21318 case bcmSwitchL3HeaderErrToCpu: 21319 case bcmSwitchL3PktErrToCpu: 21320 case bcmSwitchIpmcTtlErrToCpu: 21321 case bcmSwitchMtuFailureToCpu: 21322 case bcmSwitchHgHdrErrToCpu: 21323 case bcmSwitchSrcKnockoutToCpu: 21324 if (SOC_REG_IS_VALID(unit, EGR_CPU_CONTROLr)) { 21325 if (SOC_IS_KATANA2(unit)) { 21326 BCM_IF_ERROR_RETURN( 21327 _bcm_tr2_ep_redirect_action_set(unit, REG_PORT_ANY, type, arg)); 21328 } 21329 } 21330 break; 21331 #endif /* BCM_KATANA2_SUPPORT */ 21332 case bcmSwitchSymmetricHashControl: 21333 #if defined(BCM_TRIUMPH3_SUPPORT) 21334 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 21335 SOC_IS_KATANA2(unit)) { 21336 return _bcm_tr3_symmetric_hash_control_set(unit, arg); 21337 } 21338 #endif /* BCM_TRIUMPH3_SUPPORT */ 21339 return BCM_E_UNAVAIL; 21340 break; 21341 21342 case bcmSwitchHigigCongestionClassEnable: 21343 #if defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 21344 #if defined(BCM_TOMAHAWK3_SUPPORT) 21345 if (SOC_IS_TOMAHAWK3(unit)) { 21346 return BCM_E_UNAVAIL; 21347 } else 21348 #endif 21349 if (soc_feature(unit, soc_feature_ecn_wred)) { 21350 soc_reg_t egr_reg = EGR_CONFIG_1r; 21351 21352 if (SOC_REG_IS_VALID(unit, EGR_CONFIG_1_64r)) { 21353 egr_reg = EGR_CONFIG_1_64r; 21354 } 21355 BCM_IF_ERROR_RETURN( 21356 soc_reg_field32_modify(unit, egr_reg, REG_PORT_ANY, 21357 HIGIG2_ECN_IN_CC_ENABLEf, 21358 (arg) ? 1 : 0)); 21359 return soc_reg_field32_modify(unit, ING_CONFIG_64r, 21360 REG_PORT_ANY, 21361 HIGIG2_ECN_IN_CC_ENABLEf, 21362 (arg) ? 1 : 0); 21363 } 21364 #endif 21365 return BCM_E_UNAVAIL; 21366 break; 21367 case bcmSwitchEcnNonIpResponsive: 21368 #if defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 21369 if (soc_feature(unit, soc_feature_ecn_wred)) { 21370 return soc_reg_field32_modify(unit, ECN_CONTROLr, 21371 REG_PORT_ANY, 21372 RESPONSIVE_DEFAULTf, 21373 (arg) ? 1 : 0); 21374 } 21375 #endif 21376 return BCM_E_UNAVAIL; 21377 break; 21378 case bcmSwitchEcnIpPayloadResponsive: 21379 #if defined(BCM_TOMAHAWK_SUPPORT) 21380 if (soc_feature(unit, soc_feature_ecn_wred)) { 21381 return soc_reg_field32_modify(unit, ECN_CONTROLr, 21382 REG_PORT_ANY, 21383 USE_PAYLOAD_L4_FOR_RESPONSIVEf, 21384 (arg) ? 1 : 0); 21385 } 21386 #endif 21387 return BCM_E_UNAVAIL; 21388 break; 21389 case bcmSwitchMplsNonIpPayloadDefaultEcn: 21390 #ifdef BCM_TOMAHAWK2_SUPPORT 21391 if (soc_feature(unit, soc_feature_mpls_ecn) && 21392 !(soc_feature(unit, soc_feature_td3_style_mpls))) { 21393 return soc_reg_field32_modify(unit, ECN_CONTROLr, 21394 REG_PORT_ANY, 21395 NON_IP_DEFAULT_ECNf, 21396 arg & 0x3); 21397 } 21398 #endif 21399 return BCM_E_UNAVAIL; 21400 break; 21401 case bcmSwitchEcnNonIpIntCongestionNotification: 21402 #if defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 21403 if (soc_feature(unit, soc_feature_ecn_wred)) { 21404 uint32 reg_val = 0, responsive; 21405 soc_field_t fld_idx; 21406 BCM_IF_ERROR_RETURN( 21407 READ_ECN_CONTROLr(unit, ®_val)); 21408 responsive = soc_reg_field_get(unit, ECN_CONTROLr, 21409 reg_val, RESPONSIVE_DEFAULTf); 21410 if (responsive) { 21411 fld_idx = RESPONSIVE_DEFAULT_INT_CNf; 21412 } else { 21413 fld_idx = NON_RESPONSIVE_DEFAULT_INT_CNf; 21414 } 21415 return soc_reg_field32_modify(unit, ECN_CONTROLr, 21416 REG_PORT_ANY, 21417 fld_idx, 21418 arg); 21419 } 21420 #endif 21421 return BCM_E_UNAVAIL; 21422 break; 21423 case bcmSwitchECMPHashBitCountSelect: 21424 #if (defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HELIX4_SUPPORT)) 21425 if (soc_feature(unit, soc_feature_ecmp_hash_bit_count_select)) { 21426 if ((arg & 0x7) == 0x7) { 21427 return BCM_E_PARAM; 21428 } 21429 return soc_reg_field32_modify(unit, HASH_CONTROLr, 21430 REG_PORT_ANY, 21431 ECMP_HASH_FIELD_UPPER_BITS_COUNTf, 21432 arg & 0x7); 21433 } 21434 #endif 21435 return BCM_E_UNAVAIL; 21436 break; 21437 case bcmSwitchL3RouteCache: 21438 if (NUM_PIPE(unit) == 1) { 21439 /* For single-pipe devices, this feature doesn't take effect, so return 21440 * BCM_E_UNAVAIL, then the behavior is same as previous 21441 */ 21442 return BCM_E_UNAVAIL; 21443 } 21444 21445 /* Cache is always on when using alpm2 */ 21446 if (soc_feature(unit, soc_feature_alpm2) && 21447 soc_property_get(unit, spn_L3_ALPM_ENABLE, 0)) { 21448 if (arg == 0) { 21449 LOG_CLI(("Can't disable cache when alpm2 is used.\n")); 21450 } 21451 return BCM_E_NONE; 21452 } 21453 #ifdef BCM_TRIDENT2_SUPPORT 21454 if (SOC_IS_TD2_TT2(unit)) { 21455 #ifdef INCLUDE_L3 21456 if (soc_feature(unit, soc_feature_l3)) { 21457 if (soc_feature(unit, soc_feature_alpm) && 21458 soc_property_get(unit, spn_L3_ALPM_ENABLE, 0)) { 21459 if (soc_feature(unit, soc_feature_alpm_flex_stat)) { 21460 BCM_IF_ERROR_RETURN( 21461 soc_mem_cache_set(unit, L3_DEFIP_ALPM_IPV4_1m, 21462 MEM_BLOCK_ALL, arg ? TRUE : FALSE)); 21463 BCM_IF_ERROR_RETURN( 21464 soc_mem_cache_set(unit, L3_DEFIP_ALPM_IPV6_64_1m, 21465 MEM_BLOCK_ALL, arg ? TRUE : FALSE)); 21466 } else { 21467 BCM_IF_ERROR_RETURN( 21468 soc_mem_cache_set(unit, L3_DEFIP_ALPM_IPV4m, 21469 MEM_BLOCK_ALL, arg ? TRUE : FALSE)); 21470 BCM_IF_ERROR_RETURN( 21471 soc_mem_cache_set(unit, L3_DEFIP_ALPM_IPV6_64m, 21472 MEM_BLOCK_ALL, arg ? TRUE : FALSE)); 21473 } 21474 BCM_IF_ERROR_RETURN( 21475 soc_mem_cache_set(unit, L3_DEFIP_ALPM_IPV6_128m, 21476 MEM_BLOCK_ALL, arg ? TRUE : FALSE)); 21477 return BCM_E_NONE; 21478 } else if (soc_feature(unit, soc_feature_lpm_tcam)) { 21479 soc_mem_t mem = L3_DEFIPm, mem64 = L3_DEFIP_PAIR_128m; 21480 if (SOC_MEM_IS_VALID(unit, L3_DEFIP_LEVEL1m)) { 21481 mem = L3_DEFIP_LEVEL1m; 21482 mem64 = L3_DEFIP_PAIR_LEVEL1m; 21483 } 21484 BCM_IF_ERROR_RETURN(soc_mem_cache_set(unit, mem, 21485 MEM_BLOCK_ALL, arg ? TRUE : FALSE)); 21486 if (SOC_MEM_IS_VALID(unit, mem64)) { 21487 BCM_IF_ERROR_RETURN( 21488 soc_mem_cache_set(unit, mem64, 21489 MEM_BLOCK_ALL, arg ? TRUE : FALSE)); 21490 } 21491 return BCM_E_NONE; 21492 } 21493 } 21494 #endif 21495 return BCM_E_UNAVAIL; 21496 } 21497 #endif 21498 break; 21499 21500 case bcmSwitchL3Max128BV6Entries: 21501 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 21502 #ifdef INCLUDE_L3 21503 if (soc_feature(unit, soc_feature_l3) && 21504 soc_feature(unit, soc_feature_l3_shared_defip_table)) { 21505 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit) 21506 || SOC_IS_TRIDENT3X(unit)) { 21507 #ifdef BCM_TRX_SUPPORT 21508 /* not supported on devices with ext L3 memory enabled.*/ 21509 if (EXT_TCAM_IS_L3_ENABLED(unit)) { 21510 return BCM_E_UNAVAIL; 21511 } 21512 #endif 21513 return bcm_xgs3_route_tables_resize(unit, arg); 21514 } 21515 } 21516 #endif 21517 #endif 21518 return BCM_E_UNAVAIL; 21519 case bcmSwitchECMPLevel1RandomSeed: 21520 case bcmSwitchECMPLevel2RandomSeed: 21521 #ifdef BCM_TOMAHAWK_SUPPORT 21522 if (soc_feature(unit, soc_feature_ecmp_random)) { 21523 return _bcm_th_ecmp_random_hash_seed_set(unit, type, arg); 21524 } 21525 #endif 21526 break; 21527 case bcmSwitchSubportCoEEtherType: 21528 case bcmSwitchSubportEgressTpid: 21529 #ifdef BCM_TOMAHAWK3_SUPPORT 21530 if (SOC_IS_TOMAHAWK3(unit)) { 21531 return BCM_E_UNAVAIL; 21532 } 21533 #endif 21534 #ifdef BCM_HGPROXY_COE_SUPPORT 21535 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 21536 SOC_REG_IS_VALID(unit, SUBPORT_TAG_TPIDr)) { /* TD3TBD */ 21537 return bcmi_xgs5_subport_coe_ether_type_size_set(unit, type, arg); 21538 } else { 21539 return BCM_E_UNAVAIL; 21540 } 21541 #endif 21542 21543 case bcmSwitchSubportEgressWideTpid: 21544 return BCM_E_UNAVAIL; 21545 21546 case bcmSwitchIpmcSameVlanPruningOverride: 21547 if(soc_feature(unit, soc_feature_same_vlan_pruning_override)) { 21548 tmp_reg = EGR_CONFIG_1r; 21549 #if defined(BCM_TRIDENT3_SUPPORT) 21550 if (SOC_REG_IS_VALID(unit,EGR_CONFIG_1_64r)) { 21551 tmp_reg = EGR_CONFIG_1_64r; 21552 } 21553 #endif 21554 return soc_reg_field32_modify(unit, tmp_reg, 21555 REG_PORT_ANY, 21556 ALLOW_L2_SWITCH_IN_IPMC_IND_MODEf, 21557 ((arg) ? 1 : 0)); 21558 } 21559 21560 return BCM_E_UNAVAIL; 21561 case bcmSwitchMimBvidInsertionControl: 21562 #ifdef BCM_TRIDENT2PLUS_SUPPORT 21563 if (soc_feature(unit, soc_feature_mim) && 21564 soc_feature(unit, soc_feature_mim_bvid_insertion_control)) { 21565 return soc_reg_field32_modify(unit, EGR_CONFIGr, REG_PORT_ANY, 21566 HONOR_NEXTHOP_BVID_VALIDf, 21567 (arg) ? 1 : 0); 21568 } 21569 #endif 21570 return BCM_E_UNAVAIL; 21571 #if defined(BCM_ESW_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) && \ 21572 (defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT)) 21573 case bcmSwitchL2CpuDeleteEvent: 21574 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit)) { 21575 #if defined(BCM_TOMAHAWK3_SUPPORT) 21576 if (SOC_IS_TOMAHAWK3(unit)) { 21577 /* Mod Fifo not implemented in TH3 h/w */ 21578 return BCM_E_UNAVAIL; 21579 } 21580 #endif 21581 field = L2_DELETEf; 21582 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21583 } else if (soc_feature(unit, soc_feature_cmicm)) { 21584 field = L2_MOD_FIFO_ENABLE_L2_DELETEf; 21585 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 21586 SOC_IS_GREYHOUND(unit) || SOC_IS_KATANA2(unit)) { 21587 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21588 } 21589 } else if (soc_feature(unit, soc_feature_cmicx)) { 21590 field = L2_DELETEf; 21591 } 21592 return soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21593 case bcmSwitchL2LearnEvent: 21594 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit)) { 21595 #if defined(BCM_TOMAHAWK3_SUPPORT) 21596 if (SOC_IS_TOMAHAWK3(unit)) { 21597 /* Mod Fifo not implemented in TH3 h/w */ 21598 return BCM_E_UNAVAIL; 21599 } 21600 #endif 21601 field = L2_LEARNf; 21602 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21603 } else if (soc_feature(unit, soc_feature_cmicm)) { 21604 field = L2_MOD_FIFO_ENABLE_LEARNf; 21605 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 21606 SOC_IS_GREYHOUND(unit)) { 21607 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21608 } 21609 } else if (soc_feature(unit, soc_feature_cmicx)) { 21610 field = L2_LEARNf; 21611 } 21612 return soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21613 case bcmSwitchL2CpuAddEvent: 21614 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit)) { 21615 #if defined(BCM_TOMAHAWK3_SUPPORT) 21616 if (SOC_IS_TOMAHAWK3(unit)) { 21617 /* Mod Fifo not implemented in TH3 h/w */ 21618 return BCM_E_UNAVAIL; 21619 } 21620 #endif 21621 field = L2_INSERTf; 21622 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21623 } else if (soc_feature(unit, soc_feature_cmicm)) { 21624 field = L2_MOD_FIFO_ENABLE_L2_INSERTf; 21625 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 21626 SOC_IS_GREYHOUND(unit) || SOC_IS_KATANA2(unit)) { 21627 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21628 } 21629 } else if (soc_feature(unit, soc_feature_cmicx)) { 21630 field = L2_INSERTf; 21631 } 21632 return soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21633 case bcmSwitchL2AgingEvent: 21634 if (SOC_IS_TOMAHAWKX(unit)) { 21635 #if defined(BCM_TOMAHAWK3_SUPPORT) 21636 if (SOC_IS_TOMAHAWK3(unit)) { 21637 /* Mod Fifo not implemented in TH3 h/w */ 21638 return BCM_E_UNAVAIL; 21639 } 21640 #endif 21641 field = L2_AGEf; 21642 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21643 } else if (soc_feature(unit, soc_feature_cmicm)) { 21644 field = L2_MOD_FIFO_ENABLE_AGEf; 21645 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 21646 SOC_IS_GREYHOUND(unit)) { 21647 return _soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21648 } 21649 } else if (SOC_IS_TRIUMPH3(unit) || soc_feature(unit, soc_feature_cmicx)) { 21650 return BCM_E_UNAVAIL; 21651 } 21652 return soc_l2mod_sbus_fifo_field_set(unit, field, arg); 21653 #else 21654 case bcmSwitchL2CpuDeleteEvent: 21655 case bcmSwitchL2LearnEvent: 21656 case bcmSwitchL2CpuAddEvent: 21657 case bcmSwitchL2AgingEvent: 21658 return BCM_E_UNAVAIL; 21659 #endif 21660 case bcmSwitchUdfHashEnable: 21661 #if defined(BCM_TRIDENT2_SUPPORT) 21662 if (soc_feature(unit, soc_feature_udf_hashing)) { 21663 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 21664 if (SOC_IS_TOMAHAWK2(unit) || SOC_IS_TOMAHAWK3(unit)) { 21665 return _bcm_th2_switch_udf_hash_set(unit, arg); 21666 } else 21667 #endif 21668 { 21669 return _bcm_td2_switch_udf_hash_set(unit, arg); 21670 } 21671 } 21672 #endif 21673 return BCM_E_UNAVAIL; 21674 case bcmSwitchOlpMatchRule: 21675 #if defined BCM_TRIDENT2PLUS_SUPPORT 21676 if (SOC_IS_TRIDENT2PLUS(unit)) { 21677 return _bcm_esw_rx_olp_match_rule_set (unit, arg); 21678 } 21679 #endif 21680 return BCM_E_UNAVAIL; 21681 case bcmSwitchNonUcVlanShapingEnable: 21682 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 21683 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || SOC_IS_TRIDENT(unit)){ 21684 return soc_reg_field32_modify(unit, ING_MISC_CONFIGr, 21685 REG_PORT_ANY, 21686 NONUC_VLAN_SHAPING_ENABLEf, (arg ? 1 : 0)); 21687 } 21688 #endif 21689 #if defined(BCM_TRIDENT2_SUPPORT) 21690 if (SOC_IS_TRIDENT2(unit) || SOC_IS_TRIDENT2PLUS(unit)) { 21691 if (!SOC_REG_IS_VALID(unit, ING_MISC_CONFIGr)) { 21692 return BCM_E_UNAVAIL; 21693 } 21694 return soc_reg_field32_modify(unit, ING_MISC_CONFIGr, 21695 REG_PORT_ANY, 21696 NONUC_SERVICE_QUEUING_ENABLEf, (arg ? 1 : 0)); 21697 } 21698 #endif 21699 return BCM_E_UNAVAIL; 21700 case bcmSwitchRangeCheckersAPIType: 21701 #if defined BCM_TOMAHAWK_SUPPORT 21702 if (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 21703 if (soc_feature(unit, soc_feature_range_check_group_support)) { 21704 return BCM_E_UNAVAIL; 21705 } 21706 return bcmi_xgs5_range_RangeCheckersAPIType_set(unit, arg); 21707 } 21708 #endif 21709 return BCM_E_UNAVAIL; 21710 break; 21711 21712 case bcmSwitchCustomHeaderEncapPriorityOffset: 21713 #ifdef BCM_HURRICANE3_SUPPORT 21714 if (soc_feature(unit, soc_feature_custom_header)) { 21715 /* The offset should be 4-bit aligned */ 21716 if (arg % 4 != 0) { 21717 return BCM_E_PARAM; 21718 } 21719 return soc_reg_field32_modify(unit, 21720 CUSTOM_PACKET_HEADER_OVERRIDEr, 21721 REG_PORT_ANY, 21722 OFFSETf, 21723 arg >> 2); 21724 } 21725 #endif 21726 return BCM_E_UNAVAIL; 21727 case bcmSwitchIngCapwapEnable: 21728 #if defined BCM_HURRICANE3_SUPPORT 21729 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 21730 return soc_reg_field32_modify(unit, CAPWAP_ENABLEr, 21731 REG_PORT_ANY, 21732 ENABLEf, 21733 (arg) ? 1 : 0); 21734 } 21735 #endif 21736 return BCM_E_UNAVAIL; 21737 case bcmSwitchCapwapDataUdpDstPort: 21738 #if defined BCM_HURRICANE3_SUPPORT 21739 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 21740 if ((arg < 0) || (arg > 0xffff)) { 21741 return BCM_E_PARAM; 21742 } 21743 return soc_reg_field32_modify(unit, CAPWAP_ENABLEr, 21744 REG_PORT_ANY, 21745 UDP_PORT_NUMf, 21746 arg); 21747 } 21748 #endif 21749 return BCM_E_UNAVAIL; 21750 case bcmSwitchCountCapwapPayloadBytesOnly: 21751 #if defined BCM_HURRICANE3_SUPPORT 21752 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 21753 return soc_reg_field32_modify(unit, CAPWAP_ENABLEr, 21754 REG_PORT_ANY, 21755 COUNT_PAYLOAD_BYTESf, 21756 (arg) ? 1 : 0); 21757 } 21758 #endif 21759 return BCM_E_UNAVAIL; 21760 21761 #ifdef BCM_TRIDENT_SUPPORT 21762 case bcmSwitchEcmpGroupMemberMode: 21763 if (SOC_IS_TRIDENT(unit) && 21764 soc_feature(unit, soc_feature_l3_ecmp_1k_groups)) { 21765 uint32 ing_config_2, ecmp_hash_16bits; 21766 21767 if (arg == BCM_SWITCH_ECMP_GROUP_MEMBER_MODE_1K) { 21768 ecmp_hash_16bits = 1; 21769 } else if (arg == BCM_SWITCH_ECMP_GROUP_MEMBER_MODE_256) { 21770 ecmp_hash_16bits = 0; 21771 } else { 21772 return BCM_E_PARAM; 21773 } 21774 21775 SOC_IF_ERROR_RETURN 21776 (READ_ING_CONFIG_2r(unit, &ing_config_2)); 21777 soc_reg_field_set(unit, ING_CONFIG_2r, &ing_config_2, 21778 ECMP_HASH_16BITSf, ecmp_hash_16bits); 21779 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_2r(unit, ing_config_2)); 21780 21781 return BCM_E_NONE; 21782 } else { 21783 return BCM_E_UNAVAIL; 21784 } 21785 break; 21786 #endif 21787 case bcmSwitchPFCDeadlockDetectionTimeInterval: 21788 case bcmSwitchPFCDeadlockRecoveryAction: 21789 if (soc_feature(unit, soc_feature_pfc_deadlock)) { 21790 #ifdef BCM_TOMAHAWK3_SUPPORT 21791 if(SOC_IS_TOMAHAWK3(unit)) { 21792 return _bcm_th3_pfc_switch_control_set(unit, type, arg); 21793 } 21794 #endif 21795 return _bcm_pfc_deadlock_control_set(unit, type, arg); 21796 } 21797 return BCM_E_UNAVAIL; 21798 break; 21799 case bcmSwitchMirrorPsampFormat2Epoch: 21800 #ifdef BCM_TOMAHAWK3_SUPPORT 21801 if (SOC_IS_TOMAHAWK3(unit)) { 21802 int max_val; 21803 max_val = (1 << soc_reg_field_length(unit, 21804 EGR_MIRROR_PSAMP_FORMAT_2_MONITORr, EPOCHf)) - 1; 21805 if ((arg < 0) || (arg > max_val)) { 21806 return BCM_E_PARAM; 21807 } 21808 SOC_IF_ERROR_RETURN(WRITE_EGR_MIRROR_PSAMP_FORMAT_2_MONITORr(unit, 21809 arg)); 21810 return BCM_E_NONE; 21811 } 21812 #endif 21813 return BCM_E_UNAVAIL; 21814 break; 21815 21816 case bcmSwitchDlbMonitorIngressRandomSeed: 21817 #ifdef BCM_TOMAHAWK3_SUPPORT 21818 if(SOC_IS_TOMAHAWK3(unit)) { 21819 int max_seed; 21820 max_seed = (1 << soc_reg_field_length(unit, 21821 DLB_ECMP_MONITOR_CONTROLr, SEEDf)) - 1; 21822 if ((arg < 1) || (arg >= max_seed)) { 21823 return BCM_E_PARAM; 21824 } 21825 SOC_IF_ERROR_RETURN(WRITE_DLB_ECMP_MONITOR_CONTROLr(unit, 21826 arg)); 21827 return BCM_E_NONE; 21828 } 21829 #endif 21830 return BCM_E_UNAVAIL; 21831 break; 21832 #if defined(BCM_TOMAHAWK_SUPPORT) 21833 case bcmSwitchSampleFlexRandomSeed: 21834 if(soc_feature(unit, soc_feature_sflow_flex)) { 21835 int max_seed; 21836 max_seed = (1 << soc_reg_field_length(unit, 21837 SFLOW_ING_FLEX_RAND_SEEDr, SEEDf)) - 1; 21838 if ((arg < 1) || (arg > max_seed)) { 21839 return BCM_E_PARAM; 21840 } 21841 SOC_IF_ERROR_RETURN(WRITE_SFLOW_ING_FLEX_RAND_SEEDr(unit, 21842 arg)); 21843 return BCM_E_NONE; 21844 } else { 21845 return BCM_E_UNAVAIL; 21846 } 21847 break; 21848 case bcmSwitchHashSetTflowMode: 21849 if (soc_feature(unit, soc_feature_th_tflow)) { 21850 if (arg == 1) { 21851 _bcm_switch_tflow_mode_info[unit].enabled = 1; 21852 return BCM_E_NONE; 21853 } else if (arg == 0) { 21854 _bcm_switch_tflow_mode_info[unit].enabled = 0; 21855 return BCM_E_NONE; 21856 } else { 21857 return BCM_E_PARAM; 21858 } 21859 } else { 21860 return BCM_E_UNAVAIL; 21861 } 21862 break; 21863 #endif /* BCM_TOMAHAWK_SUPPORT */ 21864 case bcmSwitchFlexIP6ExtHdr: 21865 if (soc_feature(unit, soc_feature_l3_ip6) && 21866 SOC_REG_IS_VALID(unit, FLEXIBLE_IPV6_EXT_HDRr)) { 21867 int max_ext_hdr_id; 21868 max_ext_hdr_id = (1 << soc_reg_field_length(unit, 21869 FLEXIBLE_IPV6_EXT_HDRr, PROTOCOL_IDf)) - 1; 21870 if ((arg < 0) || (arg > max_ext_hdr_id)) { 21871 return BCM_E_PARAM; 21872 } 21873 SOC_IF_ERROR_RETURN(WRITE_FLEXIBLE_IPV6_EXT_HDRr(unit, arg)); 21874 return BCM_E_NONE; 21875 } else { 21876 return BCM_E_UNAVAIL; 21877 } 21878 break; 21879 case bcmSwitchFlexIP6ExtHdrEgress: 21880 if (soc_feature(unit, soc_feature_l3_ip6) && 21881 SOC_REG_IS_VALID(unit, EGR_FLEXIBLE_IPV6_EXT_HDRr)) { 21882 int max_egr_ext_hdr_id; 21883 max_egr_ext_hdr_id = (1 << soc_reg_field_length(unit, 21884 EGR_FLEXIBLE_IPV6_EXT_HDRr, PROTOCOL_IDf)) - 1; 21885 if ((arg < 0) || (arg > max_egr_ext_hdr_id)) { 21886 return BCM_E_PARAM; 21887 } 21888 SOC_IF_ERROR_RETURN(WRITE_EGR_FLEXIBLE_IPV6_EXT_HDRr(unit, arg)); 21889 return BCM_E_NONE; 21890 } 21891 break; 21892 #ifdef BCM_EP_REDIRECT_VERSION_2 21893 case bcmSwitchRedirectBufferThresholdPriorityLow: 21894 case bcmSwitchRedirectBufferThresholdPriorityMedium: 21895 case bcmSwitchRedirectBufferThresholdPriorityHigh: 21896 if (soc_feature(unit, soc_feature_ep_redirect_v2)) { 21897 21898 int cells = 0, reg = INVALIDf; 21899 uint32 reg_val = 0; 21900 /* Check the sanity of the value passed in */ 21901 /* Total cells are (2048*108=221184 bytes)*/ 21902 if ((arg < 0) || (arg > 221184 )) { 21903 return BCM_E_PARAM; 21904 } 21905 21906 /* Convert bytes to cells */ 21907 if(arg < 108) { 21908 cells = 1; 21909 } else if(!(arg % 108)) { 21910 /* Aligned to the cell boundary */ 21911 cells = (arg % 108); 21912 } else if(arg % 108) { 21913 /* Not-aligned to the cell boundary, move to next */ 21914 cells = (arg / 108) + 1; 21915 } 21916 21917 /* Set the register to program */ 21918 if(type == bcmSwitchRedirectBufferThresholdPriorityLow) { 21919 reg = RDB_THRESHOLD_LOr; 21920 } else if(type == bcmSwitchRedirectBufferThresholdPriorityMedium) { 21921 reg = RDB_THRESHOLD_MEDr; 21922 } else { 21923 reg = RDB_THRESHOLD_HIr; 21924 } 21925 21926 /* Set the computed value in relevant fields */ 21927 soc_reg_field_set(unit, reg, ®_val, LIMITf, cells); 21928 soc_reg_field_set(unit, reg, ®_val, RESUMEf, cells); 21929 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, 21930 REG_PORT_ANY, 0, reg_val)); 21931 21932 return BCM_E_NONE; 21933 21934 } else { 21935 return BCM_E_UNAVAIL; 21936 } 21937 break; 21938 #endif 21939 #if defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 21940 case bcmSwitchL3ClassIdForL2Enable: 21941 if (soc_feature(unit, soc_feature_l2_use_l3_class_id)) { 21942 return soc_reg_field32_modify(unit, 21943 ING_CONFIG_64r, 21944 REG_PORT_ANY, 21945 ENABLE_L3_CLASSID_FOR_L2PKTSf, 21946 (arg) ? 1 : 0); 21947 } else { 21948 return BCM_E_UNAVAIL; 21949 } 21950 break; 21951 #endif 21952 #if defined(BCM_TOMAHAWK_SUPPORT) 21953 /* Tomahawk SKUs support multimode cut-thru. Using global switch to apply same cut-through */ 21954 /* settings to all ports (e.g Trident2) has been discontinued. In Tomahawk, the cut-through */ 21955 /* configuration (to be determined based on speed limits) has to be per port and is */ 21956 /* supported only through bcm_switch_control_port_set()/get() interfaces. */ 21957 case bcmSwitchAlternateStoreForward: 21958 if (soc_feature(unit, soc_feature_asf_multimode)) { 21959 return BCM_E_UNAVAIL; 21960 } 21961 break; 21962 #endif 21963 #if defined(BCM_TRIDENT3_SUPPORT) 21964 case bcmSwitchSourceRouteToCpu: 21965 if (SOC_IS_TRIDENT3X(unit)) { 21966 (void)soc_reg_field32_modify(unit, ING_MISC_CONFIG2r, 21967 REG_PORT_ANY, MACSA_MULTICAST_DROPf, (arg) ? 1 : 0); 21968 } 21969 break; 21970 #endif 21971 #if defined(BCM_TRIDENT3_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 21972 case bcmSwitchIpmcSameFwdDmnThreshold: 21973 if (soc_feature(unit, soc_feature_td3_style_riot)) { 21974 (void)soc_reg_field32_modify(unit, EGR_FWD_DOMAIN_MATCHr, 21975 REG_PORT_ANY, THRESHOLDf, arg); 21976 return BCM_E_NONE; 21977 } else { 21978 return BCM_E_UNAVAIL; 21979 } 21980 break; 21981 #endif 21982 21983 case bcmSwitchDowngrade: 21984 #if defined(BCM_WARM_BOOT_SUPPORT) 21985 SOC_CONTROL(unit)->downgrade_version = arg; 21986 rv = _bcm_switch_downgrade(unit, arg); 21987 return rv; 21988 #else 21989 return SOC_E_UNAVAIL; 21990 #endif 21991 break; 21992 #ifdef BCM_TRIDENT2_SUPPORT 21993 case bcmSwitchGtpDetectEnable: 21994 if (SOC_REG_IS_VALID(unit, ING_GTP_CONTROLr)) { 21995 return soc_reg_field32_modify(unit, ING_GTP_CONTROLr, 21996 REG_PORT_ANY, GTP_ENABLEf, 21997 (arg) ? 1 : 0); 21998 } else { 21999 return BCM_E_UNAVAIL; 22000 } 22001 break; 22002 case bcmSwitchGtpHdrFirstByte: 22003 if (SOC_REG_IS_VALID(unit, ING_GTP_CONTROLr)) { 22004 if ((arg < 0) || (arg > 0xFF)) { 22005 return BCM_E_PARAM; 22006 } 22007 return soc_reg_field32_modify(unit, ING_GTP_CONTROLr, 22008 REG_PORT_ANY, GTP_HDR_FIRST_BYTEf, 22009 arg); 22010 } else { 22011 return BCM_E_UNAVAIL; 22012 } 22013 break; 22014 case bcmSwitchGtpHdrFirstByteMask: 22015 if (SOC_REG_IS_VALID(unit, ING_GTP_CONTROLr)) { 22016 if ((arg < 0) || (arg > 0xFF)) { 22017 return BCM_E_PARAM; 22018 } 22019 return soc_reg_field32_modify(unit, ING_GTP_CONTROLr, 22020 REG_PORT_ANY, GTP_HDR_FIRST_BYTE_MASKf, 22021 arg); 22022 } else { 22023 return BCM_E_UNAVAIL; 22024 } 22025 break; 22026 case bcmSwitchHashGtpTeidEnable0: 22027 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2r) && 22028 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2r, ENABLE_GTP_Af)) { 22029 return soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_2r, 22030 REG_PORT_ANY, ENABLE_GTP_Af, 22031 (arg) ? 1 : 0); 22032 } else if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2_64r) && 22033 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2_64r, ENABLE_GTP_Af)) { 22034 uint64 rtag7_hash_control_2_64; 22035 SOC_IF_ERROR_RETURN( 22036 READ_RTAG7_HASH_CONTROL_2_64r(unit, &rtag7_hash_control_2_64)); 22037 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_2_64r, 22038 &rtag7_hash_control_2_64, ENABLE_GTP_Af, 22039 (arg) ? 1 : 0); 22040 SOC_IF_ERROR_RETURN( 22041 WRITE_RTAG7_HASH_CONTROL_2_64r(unit, rtag7_hash_control_2_64)); 22042 return BCM_E_NONE; 22043 } else { 22044 return BCM_E_UNAVAIL; 22045 } 22046 break; 22047 case bcmSwitchHashGtpTeidEnable1: 22048 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2r) && 22049 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2r, ENABLE_GTP_Bf)) { 22050 return soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_2r, 22051 REG_PORT_ANY, ENABLE_GTP_Bf, 22052 (arg) ? 1 : 0); 22053 } else if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2_64r) && 22054 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2_64r, ENABLE_GTP_Bf)) { 22055 uint64 rtag7_hash_control_2_64; 22056 SOC_IF_ERROR_RETURN( 22057 READ_RTAG7_HASH_CONTROL_2_64r(unit, &rtag7_hash_control_2_64)); 22058 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROL_2_64r, 22059 &rtag7_hash_control_2_64, ENABLE_GTP_Bf, 22060 (arg) ? 1 : 0); 22061 SOC_IF_ERROR_RETURN( 22062 WRITE_RTAG7_HASH_CONTROL_2_64r(unit, rtag7_hash_control_2_64)); 22063 return BCM_E_NONE; 22064 } else { 22065 return BCM_E_UNAVAIL; 22066 } 22067 break; 22068 #endif /* BCM_TRIDENT2_SUPPORT */ 22069 #ifdef BCM_TRIDENT2_SUPPORT 22070 case bcmSwitchEccSingleBitErrorEvent: 22071 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TITAN2X(unit)) { 22072 return soc_td2x_ser_single_bit_error_enable_set(unit, arg); 22073 } 22074 #if defined(BCM_TOMAHAWK_SUPPORT) 22075 else if (SOC_IS_TOMAHAWKX(unit)) { 22076 return soc_th_ser_single_bit_error_enable_set(unit, arg); 22077 } 22078 #endif 22079 break; 22080 #endif /* BCM_TOMAHAWK_SUPPORT */ 22081 case bcmSwitchIntL4DestPort1: 22082 case bcmSwitchIntL4DestPort2: 22083 case bcmSwitchIntProbeMarker1: 22084 case bcmSwitchIntProbeMarker2: 22085 case bcmSwitchIntVersion: 22086 case bcmSwitchIntRequestVectorValue: 22087 case bcmSwitchIntRequestVectorMask: 22088 case bcmSwitchIntSwitchId: 22089 case bcmSwitchIntEgressTimeDelta: 22090 case bcmSwitchIntHopLimitCpuEnable: 22091 case bcmSwitchIntTurnAroundCpuEnable: 22092 case bcmSwitchIntMaxPayloadLength: 22093 case bcmSwitchIntL4DestPortEnable: 22094 case bcmSwitchIntProbeMarkerEnable: 22095 return bcmi_esw_int_switch_control_set(unit,type,arg); 22096 break; 22097 22098 case bcmSwitchE2EFCReceiveDestMacOui: 22099 case bcmSwitchE2EFCReceiveDestMacNonOui: 22100 case bcmSwitchE2EFCReceiveEtherType: 22101 case bcmSwitchE2EFCReceiveOpcode: 22102 #ifdef BCM_KATANA2_SUPPORT 22103 if (SOC_IS_KATANA2(unit)) { 22104 return bcm_kt2_switch_control_set( unit, type, arg); 22105 } 22106 #endif /* BCM_KATANA2_SUPPORT */ 22107 break; 22108 #ifdef BCM_MONTEREY_SUPPORT 22109 case bcmSwitchRoeEthertype: 22110 if (soc_feature(unit, soc_feature_roe)) { 22111 uint32 reg32; 22112 /* RoE protocal ethertype valid range */ 22113 if ((arg < 0) || (arg > 0xffff)) { 22114 return BCM_E_PARAM; 22115 } else { 22116 SOC_IF_ERROR_RETURN(READ_EGR_ROE_ETHERTYPEr(unit, ®32)); 22117 if (SOC_REG_FIELD_VALID(unit, EGR_ROE_ETHERTYPEr, 22118 ROE_ETHERTYPEf)) { 22119 soc_reg_field_set(unit, EGR_ROE_ETHERTYPEr, ®32, 22120 ROE_ETHERTYPEf, arg); 22121 } 22122 SOC_IF_ERROR_RETURN(WRITE_EGR_ROE_ETHERTYPEr(unit, reg32)); 22123 return BCM_E_NONE; 22124 } 22125 } else { 22126 return BCM_E_UNAVAIL; 22127 } 22128 break; 22129 case bcmSwitchRoeCustomEthertype: 22130 if (soc_feature(unit, soc_feature_roe_custom)) { 22131 uint32 reg32; 22132 /* RoE Custom protocal ethertype valid range */ 22133 if ((arg < 0) || (arg > 0xffff)) { 22134 return BCM_E_PARAM; 22135 } else { 22136 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_EP_1r(unit, ®32)); 22137 if (SOC_REG_FIELD_VALID(unit, BRCM_RESERVED_EP_1r, 22138 BRCM_RESERVED_EP_1_1f)) { 22139 soc_reg_field_set(unit, BRCM_RESERVED_EP_1r, ®32, 22140 BRCM_RESERVED_EP_1_1f, arg); 22141 } 22142 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_EP_1r(unit, reg32)); 22143 return BCM_E_NONE; 22144 } 22145 } else { 22146 return BCM_E_UNAVAIL; 22147 } 22148 break; 22149 case bcmSwitchRoeUdpDestPort: 22150 if (soc_feature(unit, soc_feature_roe)) { 22151 uint32 reg32; 22152 if ((arg < 0) || (arg > 0xffff)) { 22153 return BCM_E_PARAM; 22154 } else { 22155 SOC_IF_ERROR_RETURN(READ_ROE_UDP_PORTr(unit, ®32)); 22156 if (SOC_REG_FIELD_VALID(unit, ROE_UDP_PORTr, 22157 VALUEf)) { 22158 soc_reg_field_set(unit, ROE_UDP_PORTr, ®32, 22159 VALUEf, arg); 22160 } 22161 SOC_IF_ERROR_RETURN(WRITE_ROE_UDP_PORTr(unit, reg32)); 22162 return BCM_E_NONE; 22163 } 22164 } else { 22165 return BCM_E_UNAVAIL; 22166 } 22167 break; 22168 case bcmSwitchRoeCustomUdpDestPort: 22169 if (soc_feature(unit, soc_feature_roe_custom)) { 22170 uint32 reg32; 22171 if ((arg < 0) || (arg > 0xffff)) { 22172 return BCM_E_PARAM; 22173 } else { 22174 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_IP_1r(unit, ®32)); 22175 if (SOC_REG_FIELD_VALID(unit, BRCM_RESERVED_IP_1r, 22176 BRCM_RESERVED_IP_1_1f)) { 22177 soc_reg_field_set(unit, BRCM_RESERVED_IP_1r, ®32, 22178 BRCM_RESERVED_IP_1_1f, arg); 22179 } 22180 SOC_IF_ERROR_RETURN(WRITE_BRCM_RESERVED_IP_1r(unit, reg32)); 22181 return BCM_E_NONE; 22182 } 22183 } else { 22184 return BCM_E_UNAVAIL; 22185 } 22186 break; 22187 #endif 22188 case bcmSwitchOamOlpHeaderAdd: 22189 #if defined (BCM_SABER2_SUPPORT) || defined (BCM_METROLITE_SUPPORT) 22190 if ((SOC_IS_SABER2(unit)) || (SOC_IS_METROLITE(unit))) { 22191 if (arg == 0 || arg == 1) { 22192 BCM_IF_ERROR_RETURN(WRITE_EGR_OAM_RX_MODE_FOR_CPUr(unit, arg)); 22193 return BCM_E_NONE; 22194 } else { 22195 return BCM_E_PARAM; 22196 } 22197 } else { 22198 return BCM_E_UNAVAIL; 22199 } 22200 #else 22201 return BCM_E_UNAVAIL; 22202 #endif 22203 break; 22204 case bcmSwitchL2FreezeMode: 22205 return bcmi_esw_l2x_freeze_mode_set(unit, arg); 22206 break; 22207 case bcmSwitchVxlanEvpnEnable: 22208 #if defined (BCM_TRIDENT3_SUPPORT) 22209 if (soc_feature(unit, soc_feature_vxlan_evpn)) { 22210 uint32 reg32; 22211 22212 SOC_IF_ERROR_RETURN(READ_VXLAN_EVPN_CONTROLr(unit, ®32)); 22213 if (SOC_REG_FIELD_VALID(unit, VXLAN_EVPN_CONTROLr, 22214 ESI_FILTER_ENABLEf)) { 22215 soc_reg_field_set(unit, VXLAN_EVPN_CONTROLr, ®32, 22216 ESI_FILTER_ENABLEf, (arg ? 1 : 0)); 22217 } 22218 if (SOC_REG_FIELD_VALID(unit, VXLAN_EVPN_CONTROLr, 22219 SET_BUM_FLAGf)) { 22220 soc_reg_field_set(unit, VXLAN_EVPN_CONTROLr, ®32, 22221 SET_BUM_FLAGf, (arg ? 1 : 0)); 22222 } 22223 if (SOC_REG_FIELD_VALID(unit, VXLAN_EVPN_CONTROLr, 22224 USE_BUM_FLAGf)) { 22225 soc_reg_field_set(unit, VXLAN_EVPN_CONTROLr, ®32, 22226 USE_BUM_FLAGf, (arg ? 1 : 0)); 22227 } 22228 rv = WRITE_VXLAN_EVPN_CONTROLr(unit, reg32); 22229 22230 if (rv == BCM_E_NOT_FOUND) { 22231 /*The reg is covered by CCH, not found in some version CANCUN*/ 22232 return BCM_E_UNAVAIL; 22233 } else { 22234 return rv; 22235 } 22236 } else 22237 #endif 22238 { 22239 return BCM_E_UNAVAIL; 22240 } 22241 break; 22242 case bcmSwitchBfdRxDisable: 22243 return bcmi_esw_bfd_rx_disable(unit, arg); 22244 break; 22245 #if defined(BCM_TRIDENT3_SUPPORT) 22246 case bcmSwitchDosAttackIcmpPktOversize: 22247 case bcmSwitchDosAttackMinTcpHdrSize: 22248 case bcmSwitchDosAttackIcmpV6PingSize: 22249 case bcmSwitchDosAttackV6MinFragSize: 22250 if (SOC_IS_TRIDENT3X(unit)) { 22251 return _bcm_td3_dosattack_pkt_size_set(unit, type, arg); 22252 } 22253 break; 22254 case bcmSwitchGbpEtherType: 22255 if (SOC_IS_TRIDENT3X(unit)) { 22256 uint32 ver; 22257 22258 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &ver)); 22259 /* Applies to post 5.1.8 CANCUN for TD3 and in-general for MV2/HX5 */ 22260 if (!((SOC_IS_TRIDENT3(unit)) && 22261 (SOC_CANCUN_VERSION_5_2_UNDER_SERIES(ver)))) { 22262 return _bcm_td3_gbp_ethertype_set(unit, arg); 22263 } 22264 } 22265 break; 22266 #ifdef BCM_HELIX5_SUPPORT 22267 case bcmSwitchGbpSidDidMcastLookupMissClassid: 22268 if (SOC_IS_HELIX5(unit)) { 22269 if (soc_feature(unit, soc_feature_flex_flow)) { 22270 return _bcm_mcastgbp_default_classid_set(unit, arg); 22271 } else { 22272 return BCM_E_UNAVAIL; 22273 } 22274 } 22275 break; 22276 #endif 22277 case bcmSwitchPreserveOtagBeforeItag: 22278 if (soc_feature(unit, soc_feature_preserve_otag_before_itag)) { 22279 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, EGR_FLEX_CONFIGr, 22280 REG_PORT_ANY, PRESERVE_OTAG_BEFORE_ITAGf, arg)); 22281 return BCM_E_NONE; 22282 } else { 22283 return BCM_E_UNAVAIL; 22284 } 22285 break; 22286 22287 case bcmSwitchVxlanUdpSrcPortSelect: 22288 if ((soc_feature(unit, soc_feature_vxlan)) || 22289 (soc_feature(unit, soc_feature_flex_flow))) { 22290 return _bcm_td3_vxlan_udp_source_port_sel_set(unit, arg); 22291 } else { 22292 return BCM_E_UNAVAIL; 22293 } 22294 break; 22295 22296 case bcmSwitchGeneveUdpSrcPortSelect: 22297 if (soc_feature(unit, soc_feature_flex_flow)) { 22298 return _bcm_td3_geneve_udp_source_port_sel_set(unit, arg); 22299 } else { 22300 return BCM_E_UNAVAIL; 22301 } 22302 break; 22303 22304 case bcmSwitchGpeUdpSrcPortSelect: 22305 if (soc_feature(unit, soc_feature_flex_flow)) { 22306 return _bcm_td3_gpe_udp_source_port_sel_set(unit, arg); 22307 } else { 22308 return BCM_E_UNAVAIL; 22309 } 22310 break; 22311 case bcmSwitchCustomOuterEthertype1: 22312 case bcmSwitchCustomOuterEthertype2: 22313 case bcmSwitchCustomInnerEthertype1: 22314 case bcmSwitchCustomInnerEthertype2: 22315 case bcmSwitchCustomOuterProtocolId1: 22316 case bcmSwitchCustomOuterProtocolId2: 22317 case bcmSwitchCustomInnerProtocolId1: 22318 case bcmSwitchCustomInnerProtocolId2: 22319 case bcmSwitchCustomOuterUdpDstPort1: 22320 case bcmSwitchCustomOuterUdpDstPort2: 22321 case bcmSwitchCustomInnerUdpDstPort1: 22322 case bcmSwitchCustomInnerUdpDstPort2: 22323 if (SOC_IS_TRIDENT3X(unit)) { 22324 uint32 version; 22325 22326 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &version)); 22327 /* Applies to post 5.3.0 CANCUN for TD3 22328 * post 3.0.0 CANCUN for MV2 and 22329 * in-general for HX5 */ 22330 if (!(((SOC_IS_TRIDENT3(unit)) && (version <= SOC_CANCUN_VERSION_DEF_5_3_0)) || 22331 ((SOC_IS_MAVERICK2(unit)) && (version <= SOC_CANCUN_VERSION_DEF_3_0_0)))) { 22332 return _bcm_td3_custom_fields_set(unit, type, arg); 22333 } else { 22334 return BCM_E_UNAVAIL; 22335 } 22336 } 22337 break; 22338 #endif /* BCM_TRIDENT3_SUPPORT */ 22339 #if defined(BCM_TRIDENT3_SUPPORT) && defined(INCLUDE_L3) 22340 case bcmSwitchReservedEgressNextHop: 22341 if (SOC_REG_FIELD_VALID(unit, EGR_SYS_RSVD_OBJECTSr, 22342 NHOPf)) { 22343 uint32 mpath_flag = 0; 22344 int old_nh_index = 0; 22345 int new_nh_index = 0; 22346 int ref_count = 0; 22347 uint32 reg32_val = 0; 22348 22349 BCM_IF_ERROR_RETURN 22350 (READ_EGR_SYS_RSVD_OBJECTSr(unit, ®32_val)); 22351 old_nh_index = soc_reg_field_get(unit, EGR_SYS_RSVD_OBJECTSr, 22352 reg32_val, NHOPf); 22353 22354 if (arg == BCM_XGS3_L3_INVALID_INDEX) { 22355 new_nh_index = 0; 22356 } else { 22357 if (!BCM_XGS3_L3_EGRESS_IDX_VALID(unit, arg)) { 22358 return BCM_E_PARAM; 22359 } 22360 BCM_IF_ERROR_RETURN 22361 (bcm_xgs3_get_nh_from_egress_object(unit, arg, 22362 &mpath_flag, 1, &new_nh_index)); 22363 } 22364 22365 BCM_IF_ERROR_RETURN 22366 (soc_reg_field32_modify(unit, EGR_SYS_RSVD_OBJECTSr, 22367 REG_PORT_ANY, NHOPf, new_nh_index)); 22368 22369 if (old_nh_index != 0) { 22370 /* Decrement reference count */ 22371 BCM_IF_ERROR_RETURN 22372 (bcm_xgs3_get_ref_count_from_nhi( 22373 unit, mpath_flag, &ref_count, old_nh_index)); 22374 } 22375 22376 return BCM_E_NONE; 22377 } else { 22378 return BCM_E_UNAVAIL; 22379 } 22380 break; 22381 case bcmSwitchL3UcLargeDNAT: 22382 case bcmSwitchL3UcLargeSNAT: 22383 case bcmSwitchL3UcLargeDNATSNAT: 22384 case bcmSwitchL3UcLargeDNAPT: 22385 case bcmSwitchL3UcLargeSNAPT: 22386 case bcmSwitchL3UcLargeDNAPTSNAPT: 22387 if (soc_feature(unit, soc_feature_large_scale_nat)) { 22388 if (!SOC_REG_IS_VALID(unit, LARGE_SCALE_NAT_CONTROLr)) { 22389 return BCM_E_UNAVAIL; 22390 } 22391 22392 return _bcm_td3_large_scale_nat_uc_set(unit, type, arg); 22393 } 22394 else { 22395 return BCM_E_UNAVAIL; 22396 } 22397 break; 22398 case bcmSwitchL3McLargeNATRewriteType0: 22399 case bcmSwitchL3McLargeNATRewriteType1: 22400 case bcmSwitchL3McLargeNATRewriteType2: 22401 if (soc_feature(unit, soc_feature_large_scale_nat)) { 22402 if (!SOC_REG_IS_VALID(unit, LARGE_SCALE_NAT_CONTROLr)) { 22403 return BCM_E_UNAVAIL; 22404 } 22405 22406 return _bcm_td3_large_scale_nat_mc_set(unit, type, arg); 22407 } 22408 else { 22409 return BCM_E_UNAVAIL; 22410 } 22411 break; 22412 case bcmSwitchIPv4DoNotVerifyIncomingChecksum: 22413 if (SOC_IS_TRIDENT3X(unit)) { 22414 uint32 ver; 22415 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &ver)); 22416 if ((SOC_IS_TRIDENT3(unit) && (ver >= SOC_CANCUN_VERSION_DEF_6_1_3)) || 22417 (SOC_IS_MAVERICK2(unit) && (ver >= SOC_CANCUN_VERSION_DEF_4_1_2))) { 22418 if (arg < 0 || arg > 1) { 22419 return BCM_E_PARAM; 22420 } 22421 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, EGR_FLEX_CONFIGr, 22422 REG_PORT_ANY, IPV4_INCR_CHECKSUM_ORIGINAL_VALUE_VERIFYf, !arg)); 22423 return BCM_E_NONE; 22424 } 22425 } 22426 return BCM_E_UNAVAIL; 22427 break; 22428 #endif /* BCM_TRIDENT3_SUPPORT && INCLUDE_L3 */ 22429 22430 #if defined(BCM_KATANA2_SUPPORT) 22431 case bcmSwitchSystemPortOverride: 22432 if (soc_feature(unit, soc_feature_egr_vxlate_supports_dgpp)) { 22433 22434 uint64 rval64; 22435 if (arg < 0 || arg > 1) { 22436 return BCM_E_PARAM; 22437 } 22438 22439 COMPILER_64_ZERO(rval64); 22440 BCM_IF_ERROR_RETURN(soc_reg_get(unit, EGR_CONFIG_1r, 22441 0, 0, &rval64)); 22442 soc_reg64_field32_set(unit, EGR_CONFIG_1r, &rval64, 22443 VT_SYS_PORT_OVERRIDEf, arg); 22444 return soc_reg_set(unit, EGR_CONFIG_1r, 0, 0, rval64); 22445 } else { 22446 return BCM_E_UNAVAIL; 22447 } 22448 #endif 22449 22450 case bcmSwitchPcieHotSwapDisable: 22451 if (arg == 1) { 22452 rv = soc_pcie_hot_swap_disable(unit); 22453 } else { 22454 rv = BCM_E_PARAM; 22455 } 22456 return rv; 22457 break; 22458 22459 default: 22460 break; 22461 } 22462 22463 /* Iterate over all ports for port specific controls */ 22464 found = 0; 22465 PBMP_E_ITER(unit, port) { 22466 if (SOC_IS_STACK_PORT(unit, port)) { 22467 continue; 22468 } 22469 /* coverity[stack_use_callee] */ 22470 /* coverity[stack_use_overflow] */ 22471 rv = bcm_esw_switch_control_port_set(unit, port, type, arg); 22472 if (rv == BCM_E_NONE) { 22473 found = 1; 22474 } else if (rv != BCM_E_UNAVAIL) { 22475 return rv; 22476 } 22477 } 22478 22479 PBMP_ST_ITER(unit, port) { 22480 if (SOC_IS_STACK_PORT(unit, port) && 22481 (type != bcmSwitchDirectedMirroring)) { 22482 continue; 22483 } 22484 rv = bcm_esw_switch_control_port_set(unit, port, type, arg); 22485 if (rv == BCM_E_NONE) { 22486 found = 1; 22487 } else if (rv != BCM_E_UNAVAIL) { 22488 return rv; 22489 } 22490 } 22491 22492 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 22493 } 22494 22495 /* 22496 * Function: 22497 * bcm_switch_control_get 22498 * Description: 22499 * Retrieve general switch behaviors. 22500 * Parameters: 22501 * unit - Device unit number 22502 * type - The desired configuration parameter to retrieve. 22503 * arg - Pointer to where the retrieved value will be written. 22504 * Returns: 22505 * BCM_E_xxx 22506 * Notes: 22507 * For behaviors which are port-specific, retrieves the setting 22508 * for one port arbitrarily chosen from those which support the 22509 * setting and are non-stack. 22510 */ 22511 22512 int 22513 bcm_esw_switch_control_get(int unit, 22514 bcm_switch_control_t type, 22515 int *arg) 22516 { 22517 bcm_port_t port; 22518 int rv, found; 22519 uint32 rval; 22520 uint64 rval64; 22521 #if defined(BCM_ESW_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) && \ 22522 (defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT)) 22523 soc_field_t field = 0; 22524 #endif 22525 22526 #ifdef BCM_GREYHOUND2_SUPPORT 22527 if (SOC_IS_GREYHOUND2(unit)) { 22528 return bcm_gh2_switch_control_get(unit, type, arg); 22529 } 22530 #endif /* BCM_GREYHOUND2_SUPPORT */ 22531 22532 if (arg == NULL) { 22533 return BCM_E_PARAM; 22534 } 22535 #ifdef BCM_SHADOW_SUPPORT 22536 if (SOC_IS_SHADOW(unit)) { 22537 return BCM_E_UNAVAIL; 22538 } 22539 #endif /* BCM_SHADOW_SUPPORT */ 22540 /* Check for device wide, non port specific controls */ 22541 switch (type) { 22542 case bcmSwitchStableSelect: 22543 #ifdef BCM_WARM_BOOT_SUPPORT 22544 { 22545 uint32 flags; 22546 return soc_stable_get(unit, arg, &flags); 22547 } 22548 #else 22549 return SOC_E_UNAVAIL; 22550 #endif 22551 break; 22552 case bcmSwitchStableSize: 22553 #ifdef BCM_WARM_BOOT_SUPPORT 22554 return soc_stable_size_get(unit, arg); 22555 #else 22556 return SOC_E_UNAVAIL; 22557 #endif 22558 break; 22559 case bcmSwitchStableUsed: 22560 #ifdef BCM_WARM_BOOT_SUPPORT 22561 return soc_stable_used_get(unit, arg); 22562 #else 22563 return SOC_E_UNAVAIL; 22564 #endif 22565 break; 22566 case bcmSwitchControlSync: 22567 #ifdef BCM_WARM_BOOT_SUPPORT 22568 *arg = SOC_CONTROL(unit)->scache_dirty; 22569 return BCM_E_NONE; 22570 #else 22571 return SOC_E_UNAVAIL; 22572 #endif 22573 break; 22574 case bcmSwitchControlAutoSync: 22575 #ifdef BCM_WARM_BOOT_SUPPORT 22576 *arg = SOC_CONTROL(unit)->autosync; 22577 return BCM_E_NONE; 22578 #else 22579 return SOC_E_UNAVAIL; 22580 #endif 22581 break; 22582 case bcmSwitchModuleType: { 22583 bcm_module_t modid; 22584 uint32 mod_type; 22585 22586 BCM_IF_ERROR_RETURN(bcm_esw_stk_my_modid_get(unit, &modid)); 22587 BCM_IF_ERROR_RETURN(_bcm_switch_module_type_get(unit, modid, 22588 &mod_type)); 22589 *arg = BCM_SWITCH_CONTROL_MOD_TYPE_PACK(modid, mod_type); 22590 return BCM_E_NONE; 22591 } 22592 break; 22593 #ifdef BCM_CB_ABORT_ON_ERR 22594 case bcmSwitchCallbackAbortOnError: 22595 *arg = SOC_CB_ABORT_ON_ERR(unit); 22596 return BCM_E_NONE; 22597 break; 22598 #endif 22599 case bcmSwitchIpmcGroupMtu: 22600 if (soc_feature(unit, soc_feature_ipmc_group_mtu)) { 22601 uint32 val; 22602 22603 rv = READ_IPMC_L3_MTUr(unit, 0, &val); 22604 if (rv >= 0) { 22605 *arg = soc_reg_field_get(unit, IPMC_L3_MTUr, val, MTU_LENf); 22606 } 22607 return rv; 22608 } 22609 return BCM_E_UNAVAIL; 22610 break; 22611 22612 case bcmSwitchLoopbackMtuSize: 22613 #if defined(BCM_TRIUMPH3_SUPPORT) 22614 if (SOC_IS_TRIUMPH3(unit)) { 22615 uint32 val; 22616 22617 rv = READ_PASSTHRU_NLF_MTU_CHECKr(unit, &val); 22618 if (rv >= 0) { 22619 *arg = soc_reg_field_get(unit, PASSTHRU_NLF_MTU_CHECKr, val, 22620 MTU_IN_BYTESf); 22621 } 22622 return rv; 22623 } 22624 #endif 22625 return BCM_E_UNAVAIL; 22626 break; 22627 22628 case bcmSwitchMcastFloodDefault: { 22629 bcm_vlan_mcast_flood_t mode; 22630 BCM_IF_ERROR_RETURN(_bcm_esw_vlan_flood_default_get(unit, &mode)); 22631 *arg = mode; 22632 return BCM_E_NONE; 22633 } 22634 break; 22635 22636 case bcmSwitchHgHdrMcastFlood: { 22637 bcm_vlan_mcast_flood_t mode; 22638 BCM_IF_ERROR_RETURN(_bcm_esw_higig_flood_l2_get(unit, &mode)); 22639 *arg = mode; 22640 return BCM_E_NONE; 22641 } 22642 break; 22643 22644 case bcmSwitchHgHdrIpMcastFlood: { 22645 return BCM_E_UNAVAIL; 22646 } 22647 break; 22648 22649 case bcmSwitchUseGport: 22650 *arg = SOC_USE_GPORT(unit); 22651 return BCM_E_NONE; 22652 break; 22653 22654 case bcmSwitchFailoverStackTrunk: 22655 *arg = (SOC_IS_XGS3_SWITCH(unit) || SOC_IS_XGS3_FABRIC(unit)) ? 1 : 0; 22656 return BCM_E_NONE; 22657 break; 22658 22659 case bcmSwitchFailoverEtherTrunk: 22660 *arg = 0; 22661 return BCM_E_NONE; 22662 break; 22663 22664 case bcmSwitchMcastL2Range: 22665 #ifdef BCM_BRADLEY_SUPPORT 22666 if (SOC_IS_HBX(unit) || SOC_IS_SC_CQ(unit) || SOC_IS_TRIDENT2(unit)) { 22667 int mc_base, mc_size; 22668 BCM_IF_ERROR_RETURN 22669 (soc_hbx_mcast_size_get(unit, &mc_base, &mc_size)); 22670 *arg = mc_size; 22671 return BCM_E_NONE; 22672 } 22673 #endif 22674 return BCM_E_UNAVAIL; 22675 break; 22676 22677 case bcmSwitchMcastL3Range: 22678 #ifdef BCM_BRADLEY_SUPPORT 22679 if (SOC_IS_HBX(unit) || SOC_IS_SC_CQ(unit) || SOC_IS_TRIDENT2(unit)) { 22680 int ipmc_base, ipmc_size; 22681 BCM_IF_ERROR_RETURN 22682 (soc_hbx_ipmc_size_get(unit, &ipmc_base, &ipmc_size)); 22683 *arg = ipmc_size; 22684 return BCM_E_NONE; 22685 } 22686 #endif 22687 return BCM_E_UNAVAIL; 22688 break; 22689 /* coverity[equality_cond] */ 22690 22691 case bcmSwitchHgHdrMcastVlanRange: 22692 case bcmSwitchHgHdrMcastL2Range: 22693 case bcmSwitchHgHdrMcastL3Range: 22694 #if defined(BCM_TOMAHAWK3_SUPPORT) 22695 if (SOC_IS_TOMAHAWK3(unit)) { 22696 return BCM_E_UNAVAIL; 22697 } 22698 #endif 22699 #ifdef BCM_BRADLEY_SUPPORT 22700 if (SOC_IS_HBX(unit) || SOC_IS_TRX(unit)) { 22701 int bc_size, mc_size, ipmc_size; 22702 BCM_IF_ERROR_RETURN 22703 (soc_hbx_higig2_mcast_sizes_get(unit, &bc_size, 22704 &mc_size, &ipmc_size)); 22705 switch (type) { 22706 case bcmSwitchHgHdrMcastVlanRange: 22707 *arg = bc_size; 22708 break; 22709 case bcmSwitchHgHdrMcastL2Range: 22710 *arg = mc_size; 22711 break; 22712 case bcmSwitchHgHdrMcastL3Range: 22713 *arg = ipmc_size; 22714 break; 22715 /* Defensive Default */ 22716 /* coverity[dead_error_begin] */ 22717 default: 22718 return BCM_E_PARAM; 22719 } 22720 return BCM_E_NONE; 22721 } 22722 #endif 22723 return BCM_E_UNAVAIL; 22724 break; 22725 22726 case bcmSwitchHashSeed0: 22727 #ifdef BCM_BRADLEY_SUPPORT 22728 if ((SOC_IS_HBX(unit) || SOC_IS_TRX(unit)) && 22729 (!(SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)))) { 22730 rval = 0; 22731 SOC_IF_ERROR_RETURN(READ_RTAG7_HASH_SEED_Ar(unit, &rval)); 22732 *arg = soc_reg_field_get(unit, RTAG7_HASH_SEED_Ar, rval, 22733 HASH_SEED_Af); 22734 return BCM_E_NONE; 22735 } 22736 #endif /* BCM_BRADLEY_SUPPORT */ 22737 return BCM_E_UNAVAIL; 22738 break; 22739 22740 case bcmSwitchHashSeed1: 22741 #if defined(BCM_BRADLEY_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || \ 22742 defined(BCM_TRIDENT_SUPPORT) 22743 if ((SOC_IS_HBX(unit) || SOC_IS_TD_TT(unit) || SOC_IS_TRX(unit) || 22744 SOC_IS_TRIUMPH3(unit)) && 22745 (!(SOC_IS_HURRICANEX(unit) || SOC_IS_GREYHOUND(unit)))) { 22746 rval = 0; 22747 SOC_IF_ERROR_RETURN(READ_RTAG7_HASH_SEED_Br(unit, &rval)); 22748 *arg = soc_reg_field_get(unit, RTAG7_HASH_SEED_Br, rval, 22749 HASH_SEED_Bf); 22750 return BCM_E_NONE; 22751 } 22752 #endif /* BCM_BRADLEY_SUPPORT */ 22753 return BCM_E_UNAVAIL; 22754 break; 22755 22756 #if defined(BCM_TRIDENT_SUPPORT) 22757 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 22758 case bcmSwitchMacroFlowHashOverlayMinOffset: 22759 if (soc_feature(unit, soc_feature_riot) || 22760 soc_feature(unit, soc_feature_multi_level_ecmp)) { 22761 return _bcm_td_macroflow_param_get(unit, type, NULL, arg, 22762 NULL, NULL, NULL); 22763 } else { 22764 return BCM_E_UNAVAIL; 22765 } 22766 break; 22767 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 22768 case bcmSwitchMacroFlowHashMinOffset: 22769 return _bcm_td_macroflow_param_get(unit, type, NULL, arg, 22770 NULL, NULL, NULL); 22771 break; 22772 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 22773 case bcmSwitchMacroFlowTrunkHashMinOffset: 22774 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 22775 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 22776 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIUMPH3(unit) || 22777 SOC_IS_TRIDENT3X(unit) || 22778 SOC_IS_TOMAHAWKX(unit) || SOC_IS_KATANA2(unit)) { 22779 return _bcm_td_macroflow_param_get(unit, type, NULL, arg, 22780 NULL, NULL, NULL); 22781 } else 22782 #endif /* BCM_TRIDENT2_SUPPORT */ 22783 { 22784 return BCM_E_UNAVAIL; 22785 } 22786 break; 22787 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 22788 case bcmSwitchMacroFlowHashOverlayMaxOffset: 22789 if (soc_feature(unit, soc_feature_riot) || 22790 soc_feature(unit, soc_feature_multi_level_ecmp)) { 22791 return _bcm_td_macroflow_param_get(unit, type, NULL, NULL, 22792 arg, NULL, NULL); 22793 } else { 22794 return BCM_E_UNAVAIL; 22795 } 22796 break; 22797 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 22798 case bcmSwitchMacroFlowHashMaxOffset: 22799 return _bcm_td_macroflow_param_get(unit, type, NULL, NULL, arg, 22800 NULL, NULL); 22801 break; 22802 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 22803 case bcmSwitchMacroFlowTrunkHashMaxOffset: 22804 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 22805 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 22806 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIUMPH3(unit) || 22807 SOC_IS_TRIDENT3X(unit) || 22808 SOC_IS_TOMAHAWKX(unit) || SOC_IS_KATANA2(unit)) { 22809 return _bcm_td_macroflow_param_get(unit, type, NULL, NULL, 22810 arg, NULL, NULL); 22811 } else 22812 #endif /* BCM_TRIDENT2_SUPPORT */ 22813 { 22814 return BCM_E_UNAVAIL; 22815 } 22816 break; 22817 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 22818 case bcmSwitchMacroFlowHashOverlayStrideOffset: 22819 if (soc_feature(unit, soc_feature_riot) || 22820 soc_feature(unit, soc_feature_multi_level_ecmp)) { 22821 return _bcm_td_macroflow_param_get(unit, type, NULL, NULL, 22822 NULL, arg, NULL); 22823 } else { 22824 return BCM_E_UNAVAIL; 22825 } 22826 break; 22827 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 22828 case bcmSwitchMacroFlowHashStrideOffset: 22829 return _bcm_td_macroflow_param_get(unit, type, NULL, NULL, NULL, 22830 arg, NULL); 22831 break; 22832 #endif /* BCM_TRIDENT_SUPPORT */ 22833 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 22834 case bcmSwitchMacroFlowTrunkHashStrideOffset: 22835 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 22836 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 22837 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIUMPH3(unit) || 22838 SOC_IS_TRIDENT3X(unit) || 22839 SOC_IS_TOMAHAWKX(unit) || SOC_IS_KATANA2(unit)) { 22840 return _bcm_td_macroflow_param_get(unit, type, NULL, NULL, 22841 NULL, arg, NULL); 22842 } else 22843 #endif /* BCM_TRIDENT2_SUPPORT */ 22844 { 22845 return BCM_E_UNAVAIL; 22846 } 22847 break; 22848 /* RTAG7 Macro Flow Concatenation */ 22849 case bcmSwitchMacroFlowEcmpHashConcatEnable: 22850 case bcmSwitchMacroFlowEcmpHashOverlayConcatEnable: 22851 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 22852 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 22853 case bcmSwitchMacroFlowTrunkHashConcatEnable: 22854 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 22855 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 22856 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIUMPH3(unit) || 22857 SOC_IS_TRIDENT3X(unit) || 22858 SOC_IS_TOMAHAWKX(unit) || SOC_IS_KATANA2(unit)) { 22859 return _bcm_td_macroflow_param_get(unit, type, NULL, NULL, NULL, 22860 NULL, arg); 22861 } else 22862 #endif /* BCM_TRIDENT2_SUPPORT */ 22863 { 22864 return BCM_E_UNAVAIL; 22865 } 22866 break; 22867 22868 /* RTAG7 Macro Flow Hash Seed */ 22869 case bcmSwitchMacroFlowECMPHashSeed: 22870 case bcmSwitchMacroFlowECMPUnderlayHashSeed: 22871 case bcmSwitchMacroFlowLoadBalanceHashSeed: 22872 case bcmSwitchMacroFlowTrunkHashSeed: 22873 case bcmSwitchMacroFlowHigigTrunkHashSeed: 22874 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 22875 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIUMPH3(unit) || 22876 SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 22877 return _bcm_td2_macroflow_hash_get(unit, type, arg); 22878 } 22879 #endif /* BCM_TRIDENT2_SUPPORT */ 22880 return BCM_E_UNAVAIL; 22881 break; 22882 #if defined(BCM_RIOT_SUPPORT) || defined(BCM_MULTI_LEVEL_ECMP_SUPPORT) 22883 case bcmSwitchMacroFlowECMPOverlayHashSeed: 22884 return BCM_E_PARAM; 22885 break; 22886 #endif /* BCM_RIOT_SUPPORT || BCM_MULTI_LEVEL_ECMP_SUPPORT */ 22887 22888 /* Hash Field select controls */ 22889 case bcmSwitchHashTrillPayloadSelect0: 22890 case bcmSwitchHashTrillPayloadSelect1: 22891 case bcmSwitchHashTrillTunnelSelect0: 22892 case bcmSwitchHashTrillTunnelSelect1: 22893 #if defined(BCM_TRIDENT_SUPPORT) 22894 if ((SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit)) && 22895 soc_feature(unit, soc_feature_trill)) { 22896 return _bcm_xgs3_field_control_get(unit, type, arg); 22897 } 22898 #endif /* BCM_TRIDENT_SUPPORT */ 22899 return BCM_E_UNAVAIL; 22900 break; 22901 22902 case bcmSwitchHashVxlanPayloadSelect0: 22903 case bcmSwitchHashVxlanPayloadSelect1: 22904 #if defined(BCM_TRIDENT2_SUPPORT) 22905 if (SOC_IS_TD2_TT2(unit) 22906 && (soc_feature(unit, soc_feature_vxlan) 22907 || soc_feature(unit, soc_feature_flex_flow))) { 22908 return _bcm_xgs3_field_control_get(unit, type, arg); 22909 } 22910 #endif /* BCM_TRIDENT2_SUPPORT */ 22911 return BCM_E_UNAVAIL; 22912 break; 22913 22914 case bcmSwitchHashIP6AddrCollapseSelect0: 22915 case bcmSwitchHashIP6AddrCollapseSelect1: 22916 #if defined(BCM_TRIDENT_SUPPORT) 22917 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || 22918 SOC_IS_KATANAX(unit)) { 22919 return _bcm_xgs3_field_control_get(unit, type, arg); 22920 } 22921 #endif /* BCM_TRIDENT_SUPPORT */ 22922 return BCM_E_UNAVAIL; 22923 break; 22924 case bcmSwitchHashIP6NextHeaderUseExtensionHeader0: 22925 #if defined(BCM_TRIDENT2_SUPPORT) 22926 if (SOC_IS_TD2_TT2(unit)) { 22927 if (SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROLr, 22928 DISABLE_HASH_IP_EXTENSION_HEADERSf)) { 22929 COMPILER_64_ZERO(rval64); 22930 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &rval64)); 22931 rval = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, rval64, 22932 DISABLE_HASH_IP_EXTENSION_HEADERSf); 22933 if (rval) { 22934 *arg = FALSE; 22935 } else { 22936 *arg = TRUE; 22937 } 22938 return BCM_E_NONE; 22939 } 22940 } 22941 #endif 22942 return BCM_E_UNAVAIL; 22943 break; 22944 case bcmSwitchHashIP6NextHeaderUseExtensionHeader1: 22945 return BCM_E_UNAVAIL; 22946 case bcmSwitchHashL2MPLSPayloadSelect0: 22947 case bcmSwitchHashL2MPLSPayloadSelect1: 22948 case bcmSwitchHashIPSecSelect0: 22949 case bcmSwitchHashIPSecSelect1: 22950 case bcmSwitchHashMiMPayloadSelect0: 22951 case bcmSwitchHashMiMPayloadSelect1: 22952 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 22953 || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 22954 if ((SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 22955 SOC_IS_HELIX4(unit) || SOC_IS_KATANA2(unit)) && !SOC_IS_TOMAHAWK3(unit)) { 22956 return _bcm_xgs3_field_control_get(unit, type, arg); 22957 } 22958 #endif /* BCM_TRIDENT2_SUPPORT */ 22959 return BCM_E_UNAVAIL; 22960 break; 22961 22962 case bcmSwitchL2McastAllRouterPortsAddEnable: 22963 *arg = SOC_MCAST_ADD_ALL_ROUTER_PORTS(unit); 22964 return BCM_E_NONE; 22965 break; 22966 22967 case bcmSwitchBypassMode: 22968 *arg = SOC_SWITCH_BYPASS_MODE(unit); 22969 return BCM_E_NONE; 22970 break; 22971 22972 case bcmSwitchPFCClass0Queue: 22973 case bcmSwitchPFCClass1Queue: 22974 case bcmSwitchPFCClass2Queue: 22975 case bcmSwitchPFCClass3Queue: 22976 case bcmSwitchPFCClass4Queue: 22977 case bcmSwitchPFCClass5Queue: 22978 case bcmSwitchPFCClass6Queue: 22979 case bcmSwitchPFCClass7Queue: 22980 #if defined(BCM_SCORPION_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) 22981 if (SOC_IS_SC_CQ(unit) || SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 22982 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit)) { 22983 return _bcm_tr2_sc_pfc_priority_to_cos_get(unit, type, arg); 22984 } 22985 #endif /* BCM_SCORPION_SUPPORT || BCM_TRIUMPH2_SUPPORT */ 22986 return BCM_E_UNAVAIL; 22987 break; 22988 22989 case bcmSwitchL2HitClear: 22990 case bcmSwitchL2SrcHitClear: 22991 case bcmSwitchL2DstHitClear: 22992 case bcmSwitchL3HostHitClear: 22993 case bcmSwitchL3RouteHitClear: 22994 return _bcm_esw_switch_hit_clear_get(unit, type, arg); 22995 break; 22996 22997 /* This swithc control should be supported only per port. */ 22998 case bcmSwitchEncapErrorToCpu: 22999 return BCM_E_UNAVAIL; 23000 break; 23001 23002 case bcmSwitchSnapNonZeroOui: 23003 #if defined(BCM_TRX_SUPPORT) 23004 if (SOC_IS_TRX(unit)) { 23005 if (!SOC_IS_TRIDENT3X(unit)) { 23006 rval = 0; 23007 23008 COMPILER_64_ZERO(rval64); 23009 SOC_IF_ERROR_RETURN(READ_EGR_CONFIGr(unit, &rval)); 23010 *arg = soc_reg_field_get(unit, EGR_CONFIGr, rval, 23011 SNAP_OTHER_DECODE_ENABLEf); 23012 return BCM_E_NONE; 23013 } 23014 } else 23015 #endif /* BCM_TRX_SUPPORT */ 23016 #if defined(BCM_FIREBOLT_SUPPORT) 23017 if (SOC_IS_FB(unit) || SOC_IS_FX_HX(unit) || SOC_IS_HB_GW(unit)) { 23018 rval = 0; 23019 SOC_IF_ERROR_RETURN(READ_ING_CONFIGr(unit, &rval)); 23020 *arg = soc_reg_field_get(unit, ING_CONFIGr, rval, 23021 SNAP_OTHER_DECODE_ENABLEf); 23022 if (SOC_IS_FIREBOLT2(unit)) { 23023 SOC_IF_ERROR_RETURN(READ_EGR_CONFIGr(unit, &rval)); 23024 *arg = soc_reg_field_get(unit, EGR_CONFIGr, rval, 23025 SNAP_OTHER_DECODE_ENABLEf); 23026 } 23027 return BCM_E_NONE; 23028 } 23029 #endif /* BCM_FIREBOLT_SUPPORT */ 23030 break; 23031 23032 case bcmSwitchL2McIdxRetType: 23033 return _bcm_esw_mcast_idx_ret_type_get(unit, arg); 23034 break; 23035 23036 #ifdef BCM_TRIUMPH3_SUPPORT 23037 case bcmSwitchL2ExtLearn: 23038 if (soc_feature(unit, soc_feature_esm_support) && 23039 soc_reg_field_valid(unit, LEARN_CONTROLr, EXTERNAL_L2_ENTRYf)) { 23040 rval = 0; 23041 BCM_IF_ERROR_RETURN(READ_LEARN_CONTROLr(unit, &rval)); 23042 *arg = soc_reg_field_get(unit, LEARN_CONTROLr, rval, 23043 EXTERNAL_L2_ENTRYf); 23044 return BCM_E_NONE; 23045 } else { 23046 return BCM_E_UNAVAIL; 23047 } 23048 break; 23049 #endif /*BCM_TRIUMPH3_SUPPORT */ 23050 23051 case bcmSwitchL3McIdxRetType: 23052 #ifdef INCLUDE_L3 23053 return _bcm_esw_ipmc_idx_ret_type_get(unit, arg); 23054 #endif 23055 return BCM_E_UNAVAIL; 23056 break; 23057 case bcmSwitchL2SourceDiscardMoveToCpu: 23058 { 23059 soc_reg_t reg; 23060 uint64 regval, f_val; 23061 23062 if (SOC_REG_IS_VALID(unit, ING_CONFIGr)){ 23063 reg = ING_CONFIGr; 23064 } else if (SOC_REG_IS_VALID(unit, ING_CONFIG_64r)) { 23065 reg = ING_CONFIG_64r; 23066 } else { 23067 return BCM_E_UNAVAIL; 23068 } 23069 23070 if (soc_reg_field_valid(unit, reg, STNMOVE_ON_L2SRC_DISCf)) { 23071 BCM_IF_ERROR_RETURN( 23072 soc_reg_get(unit, reg, REG_PORT_ANY, 0, ®val)); 23073 f_val = soc_reg64_field_get(unit, reg, regval, 23074 STNMOVE_ON_L2SRC_DISCf); 23075 COMPILER_64_TO_32_LO(*arg, f_val); 23076 return BCM_E_NONE; 23077 } else { 23078 return BCM_E_UNAVAIL; 23079 } 23080 } 23081 break; 23082 23083 #ifdef BCM_TRIDENT_SUPPORT 23084 case bcmSwitchFabricTrunkDynamicSampleRate: 23085 case bcmSwitchFabricTrunkDynamicEgressBytesExponent: 23086 case bcmSwitchFabricTrunkDynamicQueuedBytesExponent: 23087 case bcmSwitchFabricTrunkDynamicEgressBytesDecreaseReset: 23088 case bcmSwitchFabricTrunkDynamicQueuedBytesDecreaseReset: 23089 case bcmSwitchFabricTrunkDynamicEgressBytesMinThreshold: 23090 case bcmSwitchFabricTrunkDynamicEgressBytesMaxThreshold: 23091 case bcmSwitchFabricTrunkDynamicQueuedBytesMinThreshold: 23092 case bcmSwitchFabricTrunkDynamicQueuedBytesMaxThreshold: 23093 if (!soc_feature(unit, soc_feature_hg_dlb)) { 23094 return BCM_E_UNAVAIL; 23095 } 23096 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 23097 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 23098 return bcm_th2_hgt_lag_dlb_config_get(unit, type, arg); 23099 } 23100 #endif /* BCM_TOMAHAWK2_SUPPORT */ 23101 return _bcm_trident_hg_dlb_config_get(unit, type, arg); 23102 break; 23103 #endif /* BCM_TRIDENT_SUPPORT */ 23104 23105 #ifdef BCM_TRIUMPH3_SUPPORT 23106 case bcmSwitchTrunkDynamicSampleRate: 23107 case bcmSwitchTrunkDynamicEgressBytesExponent: 23108 case bcmSwitchTrunkDynamicQueuedBytesExponent: 23109 case bcmSwitchTrunkDynamicEgressBytesDecreaseReset: 23110 case bcmSwitchTrunkDynamicQueuedBytesDecreaseReset: 23111 case bcmSwitchTrunkDynamicEgressBytesMinThreshold: 23112 case bcmSwitchTrunkDynamicEgressBytesMaxThreshold: 23113 case bcmSwitchTrunkDynamicQueuedBytesMinThreshold: 23114 case bcmSwitchTrunkDynamicQueuedBytesMaxThreshold: 23115 if (!soc_feature(unit, soc_feature_lag_dlb)) { 23116 return BCM_E_UNAVAIL; 23117 } 23118 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 23119 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 23120 return bcm_th2_hgt_lag_dlb_config_get(unit, type, arg); 23121 } 23122 #endif /* BCM_TOMAHAWK2_SUPPORT */ 23123 return bcm_tr3_lag_dlb_config_get(unit, type, arg); 23124 case bcmSwitchTrunkDynamicAccountingSelect: 23125 case bcmSwitchTrunkDynamicExpectedLoadMinThreshold: 23126 case bcmSwitchTrunkDynamicExpectedLoadMaxThreshold: 23127 case bcmSwitchTrunkDynamicImbalanceMinThreshold: 23128 case bcmSwitchTrunkDynamicImbalanceMaxThreshold: 23129 if (!soc_feature(unit, soc_feature_lag_dlb)) { 23130 return BCM_E_UNAVAIL; 23131 } 23132 #if defined(BCM_TOMAHAWK2_SUPPORT) 23133 if (soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 23134 return BCM_E_UNAVAIL; 23135 } 23136 #endif /* BCM_TOMAHAWK2_SUPPORT */ 23137 return bcm_tr3_lag_dlb_config_get(unit, type, arg); 23138 #endif /* BCM_TRIUMPH3_SUPPORT */ 23139 23140 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 23141 case bcmSwitchTrunkDynamicPhysicalQueuedBytesExponent: 23142 case bcmSwitchTrunkDynamicPhysicalQueuedBytesDecreaseReset: 23143 case bcmSwitchTrunkDynamicPhysicalQueuedBytesMinThreshold: 23144 case bcmSwitchTrunkDynamicPhysicalQueuedBytesMaxThreshold: 23145 case bcmSwitchTrunkDynamicRandomSeed: 23146 if (!soc_feature(unit, soc_feature_lag_dlb) || 23147 !soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 23148 return BCM_E_UNAVAIL; 23149 } 23150 return bcm_th2_hgt_lag_dlb_config_get(unit, type, arg); 23151 23152 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesExponent: 23153 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesDecreaseReset: 23154 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesMinThreshold: 23155 case bcmSwitchFabricTrunkDynamicPhysicalQueuedBytesMaxThreshold: 23156 case bcmSwitchFabricTrunkDynamicRandomSeed: 23157 if (!soc_feature(unit, soc_feature_hg_dlb) || 23158 !soc_feature(unit, soc_feature_hgt_lag_dlb_optimized)) { 23159 return BCM_E_UNAVAIL; 23160 } 23161 return bcm_th2_hgt_lag_dlb_config_get(unit, type, arg); 23162 23163 #endif /* BCM_TOMAHAWK2_SUPPORT */ 23164 #if defined(BCM_TRIUMPH3_SUPPORT) && defined(INCLUDE_L3) 23165 case bcmSwitchEcmpDynamicSampleRate: 23166 case bcmSwitchEcmpDynamicEgressBytesExponent: 23167 case bcmSwitchEcmpDynamicQueuedBytesExponent: 23168 case bcmSwitchEcmpDynamicEgressBytesDecreaseReset: 23169 case bcmSwitchEcmpDynamicQueuedBytesDecreaseReset: 23170 case bcmSwitchEcmpDynamicEgressBytesMinThreshold: 23171 case bcmSwitchEcmpDynamicEgressBytesMaxThreshold: 23172 case bcmSwitchEcmpDynamicQueuedBytesMinThreshold: 23173 case bcmSwitchEcmpDynamicQueuedBytesMaxThreshold: 23174 if (!soc_feature(unit, soc_feature_ecmp_dlb)) { 23175 return BCM_E_UNAVAIL; 23176 } 23177 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 23178 if (soc_feature(unit, soc_feature_ecmp_dlb_optimized)) { 23179 return _bcm_th2_ecmp_dlb_config_get(unit, type, arg); 23180 } 23181 #endif /* BCM_TOMAHAWK2_SUPPORT */ 23182 return _bcm_tr3_ecmp_dlb_config_get(unit, type, arg); 23183 case bcmSwitchEcmpDynamicAccountingSelect: 23184 case bcmSwitchEcmpDynamicExpectedLoadMinThreshold: 23185 case bcmSwitchEcmpDynamicExpectedLoadMaxThreshold: 23186 case bcmSwitchEcmpDynamicImbalanceMinThreshold: 23187 case bcmSwitchEcmpDynamicImbalanceMaxThreshold: 23188 if (!soc_feature(unit, soc_feature_ecmp_dlb)) { 23189 return BCM_E_UNAVAIL; 23190 } 23191 #if defined(INCLUDE_L3) && (defined(BCM_TOMAHAWK2_SUPPORT) || \ 23192 defined(BCM_TRIDENT3_SUPPORT)) 23193 if (soc_feature(unit, soc_feature_ecmp_dlb_optimized)) { 23194 return BCM_E_UNAVAIL; 23195 } 23196 #endif /* INCLUDE_L3 && BCM_TOMAHAWK2_SUPPORT || BCM_TRIDENT3_SUPPORT*/ 23197 { 23198 return _bcm_tr3_ecmp_dlb_config_get(unit, type, arg); 23199 } 23200 break; 23201 #endif /* BCM_TRIUMPH3_SUPPORT && INCLUDE_L3 */ 23202 23203 #if defined(INCLUDE_L3) && (defined(BCM_TOMAHAWK2_SUPPORT) || \ 23204 defined(BCM_TRIDENT3_SUPPORT)) 23205 case bcmSwitchEcmpDynamicPhysicalQueuedBytesExponent: 23206 case bcmSwitchEcmpDynamicPhysicalQueuedBytesDecreaseReset: 23207 case bcmSwitchEcmpDynamicPhysicalQueuedBytesMinThreshold: 23208 case bcmSwitchEcmpDynamicPhysicalQueuedBytesMaxThreshold: 23209 case bcmSwitchEcmpDynamicRandomSeed: 23210 if (!soc_feature(unit, soc_feature_ecmp_dlb_optimized)) { 23211 return BCM_E_UNAVAIL; 23212 } 23213 return _bcm_th2_ecmp_dlb_config_get(unit, type, arg); 23214 #endif /* INCLUDE_L3 && BCM_TOMAHAWK2_SUPPORT || BCM_TRIDENT3_SUPPORT*/ 23215 23216 #if (defined(BCM_RCPU_SUPPORT) || defined(BCM_OOB_RCPU_SUPPORT)) && \ 23217 defined(BCM_XGS3_SWITCH_SUPPORT) 23218 case bcmSwitchRemoteCpuSchanEnable: 23219 if (soc_feature(unit, soc_feature_rcpu_1)) { 23220 rval = 0; 23221 23222 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 23223 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 23224 ENABLE_SCHAN_REQUESTf); 23225 return BCM_E_NONE; 23226 } else { 23227 return BCM_E_UNAVAIL; 23228 } 23229 break; 23230 case bcmSwitchRemoteCpuMatchLocalMac: 23231 if (soc_feature(unit, soc_feature_rcpu_1)) { 23232 rval = 0; 23233 23234 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 23235 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 23236 LMAC0_MATCHf); 23237 return BCM_E_NONE; 23238 } else { 23239 return BCM_E_UNAVAIL; 23240 } 23241 break; 23242 case bcmSwitchRemoteCpuFromCpuEnable: 23243 if (soc_feature(unit, soc_feature_rcpu_1)) { 23244 rval = 0; 23245 23246 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 23247 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 23248 ENABLE_FROMCPU_PACKETf); 23249 return BCM_E_NONE; 23250 } else { 23251 return BCM_E_UNAVAIL; 23252 } 23253 break; 23254 case bcmSwitchRemoteCpuToCpuEnable: 23255 if (soc_feature(unit, soc_feature_rcpu_1)) { 23256 rval = 0; 23257 23258 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 23259 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 23260 ENABLE_TOCPU_PACKETf); 23261 return BCM_E_NONE; 23262 } else { 23263 return BCM_E_UNAVAIL; 23264 } 23265 break; 23266 case bcmSwitchRemoteCpuCmicEnable: 23267 #ifdef BCM_CMICM_SUPPORT 23268 if (soc_feature(unit, soc_feature_cmicm)) { 23269 rval = 0; 23270 23271 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 23272 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 23273 ENABLE_CMIC_REQUESTf); 23274 return BCM_E_NONE; 23275 } else 23276 #endif 23277 { 23278 return BCM_E_UNAVAIL; 23279 } 23280 break; 23281 case bcmSwitchRemoteCpuMatchVlan: 23282 if (soc_feature(unit, soc_feature_rcpu_1)) { 23283 rval = 0; 23284 23285 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 23286 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 23287 VLAN_MATCHf); 23288 return BCM_E_NONE; 23289 } else { 23290 return BCM_E_UNAVAIL; 23291 } 23292 break; 23293 case bcmSwitchRemoteCpuForceScheduling: 23294 if (soc_feature(unit, soc_feature_rcpu_1)) { 23295 int l_arg, h_arg; 23296 23297 l_arg = h_arg = 0; 23298 #ifdef BCM_CMICM_SUPPORT 23299 if (soc_feature(unit, soc_feature_cmicm)) { 23300 if (SOC_REG_IS_VALID(unit, CMIC_PKT_COS_0r)) { 23301 BCM_IF_ERROR_RETURN( 23302 _bcm_rcpu_switch_regall_get(unit, CMIC_PKT_COS_0r, 23303 &l_arg)); 23304 } 23305 if (SOC_REG_IS_VALID(unit, CMIC_PKT_COS_1r)) { 23306 BCM_IF_ERROR_RETURN( 23307 _bcm_rcpu_switch_regall_get(unit, CMIC_PKT_COS_1r, &h_arg)); 23308 } 23309 } else 23310 #endif 23311 { 23312 BCM_IF_ERROR_RETURN( 23313 _bcm_rcpu_switch_regall_get(unit, CMIC_PKT_COSr, &l_arg)); 23314 if (SOC_REG_IS_VALID(unit, CMIC_PKT_COS_HIr)) { 23315 BCM_IF_ERROR_RETURN( 23316 _bcm_rcpu_switch_regall_get(unit, CMIC_PKT_COS_HIr, &h_arg)); 23317 } 23318 } 23319 *arg = l_arg | h_arg; 23320 23321 return BCM_E_NONE; 23322 } else { 23323 return BCM_E_UNAVAIL; 23324 } 23325 break; 23326 case bcmSwitchRemoteCpuToCpuDestPortAllReasons: 23327 if (soc_feature(unit, soc_feature_rcpu_1)) { 23328 int l_arg, h_arg; 23329 23330 l_arg = h_arg = 0; 23331 #ifdef BCM_CMICM_SUPPORT 23332 if (soc_feature(unit, soc_feature_cmicm) 23333 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23334 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 23335 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 23336 /* In Katana only Index 0 of the reasoning code register is used */ 23337 BCM_IF_ERROR_RETURN( 23338 _bcm_rcpu_switch_regall_idx_get(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, 0, 23339 &l_arg)); 23340 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr)) { 23341 BCM_IF_ERROR_RETURN( 23342 _bcm_rcpu_switch_regall_idx_get(unit, 23343 CMIC_PKT_REASON_DIRECT_1_TYPEr, 0, &h_arg)); 23344 } 23345 } else 23346 #endif 23347 { 23348 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_DIRECTr)) { 23349 BCM_IF_ERROR_RETURN( 23350 _bcm_rcpu_switch_regall_get(unit, CMIC_PKT_REASON_DIRECTr, 23351 &l_arg)); 23352 } 23353 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_DIRECT_HIr)) { 23354 BCM_IF_ERROR_RETURN( 23355 _bcm_rcpu_switch_regall_get(unit, 23356 CMIC_PKT_REASON_DIRECT_HIr, &h_arg)); 23357 } 23358 } 23359 *arg = l_arg | h_arg; 23360 return BCM_E_NONE; 23361 } else { 23362 return BCM_E_UNAVAIL; 23363 } 23364 break; 23365 case bcmSwitchRemoteCpuToCpuDestMacAllReasons: 23366 if (soc_feature(unit, soc_feature_rcpu_1)) { 23367 int l_arg, h_arg; 23368 23369 l_arg = h_arg = 0; 23370 #ifdef BCM_CMICM_SUPPORT 23371 if (soc_feature(unit, soc_feature_cmicm) 23372 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23373 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 23374 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 23375 /* In Katana only Index 0 of the reasoning code register is used */ 23376 BCM_IF_ERROR_RETURN( 23377 _bcm_rcpu_switch_regall_idx_get(unit, CMIC_PKT_REASON_0_TYPEr, 0, 23378 &l_arg)); 23379 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_1_TYPEr)) { 23380 BCM_IF_ERROR_RETURN( 23381 _bcm_rcpu_switch_regall_idx_get(unit, 23382 CMIC_PKT_REASON_1_TYPEr, 0, &h_arg)); 23383 } 23384 } else 23385 #endif 23386 { 23387 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASONr)) { 23388 BCM_IF_ERROR_RETURN( 23389 _bcm_rcpu_switch_regall_get(unit, CMIC_PKT_REASONr, &l_arg)); 23390 } 23391 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_HIr)) { 23392 BCM_IF_ERROR_RETURN( 23393 _bcm_rcpu_switch_regall_get(unit, 23394 CMIC_PKT_REASON_HIr, &h_arg)); 23395 } 23396 } 23397 *arg = l_arg | h_arg; 23398 return BCM_E_NONE; 23399 } else { 23400 return BCM_E_UNAVAIL; 23401 } 23402 break; 23403 case bcmSwitchRxRedirectPktReasons: 23404 if (soc_feature(unit, soc_feature_rcpu_1)) { 23405 uint32 raddr; 23406 rval = 0; 23407 #ifdef BCM_CMICM_SUPPORT 23408 if (soc_feature(unit, soc_feature_cmicm) 23409 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23410 SOC_IS_TD2_TT2(unit) || SOC_IS_HURRICANE2(unit) || 23411 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit))) { 23412 /* Only Idx 0 is used in Katana */ 23413 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_0_TYPEr, REG_PORT_ANY, 0); 23414 } else 23415 #endif 23416 { 23417 raddr = soc_reg_addr(unit, CMIC_PKT_REASONr, REG_PORT_ANY, 0); 23418 } 23419 /* coverity[result_independent_of_operands] */ 23420 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23421 *arg = rval; 23422 return BCM_E_NONE; 23423 } else { 23424 return BCM_E_UNAVAIL; 23425 } 23426 break; 23427 case bcmSwitchRxRedirectPktReasonsExtended: 23428 if (soc_feature(unit, soc_feature_rcpu_1)) { 23429 #ifdef BCM_CMICM_SUPPORT 23430 if (soc_feature(unit, soc_feature_cmicm) 23431 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23432 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 23433 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 23434 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_1_TYPEr, REASONSf)) { 23435 uint32 raddr; 23436 rval = 0; 23437 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_1_TYPEr, REG_PORT_ANY, 0); 23438 /* coverity[result_independent_of_operands] */ 23439 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23440 *arg = rval; 23441 return BCM_E_NONE; 23442 } 23443 } else 23444 #endif 23445 { 23446 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_HIr, REASONSf)) { 23447 uint32 raddr; 23448 rval = 0; 23449 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_HIr, REG_PORT_ANY, 0); 23450 /* coverity[result_independent_of_operands] */ 23451 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23452 *arg = rval; 23453 return BCM_E_NONE; 23454 } 23455 } 23456 } 23457 return BCM_E_UNAVAIL; 23458 break; 23459 case bcmSwitchRxRedirectHigigPktReasons: 23460 if (soc_feature(unit, soc_feature_rcpu_1)) { 23461 uint32 raddr; 23462 rval = 0; 23463 #ifdef BCM_CMICM_SUPPORT 23464 if (soc_feature(unit, soc_feature_cmicm) 23465 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23466 SOC_IS_TD2_TT2(unit) || SOC_IS_HURRICANE2(unit) || 23467 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit))) { 23468 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, REG_PORT_ANY, 0); 23469 } else 23470 #endif 23471 { 23472 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECTr, REG_PORT_ANY, 0); 23473 } 23474 /* coverity[result_independent_of_operands] */ 23475 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23476 *arg = rval; 23477 return BCM_E_NONE; 23478 } else { 23479 return BCM_E_UNAVAIL; 23480 } 23481 break; 23482 case bcmSwitchRxRedirectHigigPktReasonsExtended: 23483 if (soc_feature(unit, soc_feature_rcpu_1)) { 23484 #ifdef BCM_CMICM_SUPPORT 23485 if (soc_feature(unit, soc_feature_cmicm) 23486 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23487 SOC_IS_TD2_TT2(unit) || SOC_IS_HURRICANE2(unit) || 23488 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit))) { 23489 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr, REASONSf)) { 23490 uint32 raddr; 23491 rval = 0; 23492 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr, REG_PORT_ANY, 0); 23493 /* coverity[result_independent_of_operands] */ 23494 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23495 *arg = rval; 23496 return BCM_E_NONE; 23497 } 23498 } else 23499 #endif 23500 { 23501 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_DIRECT_HIr, REASONSf)) { 23502 uint32 raddr; 23503 rval = 0; 23504 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_HIr, REG_PORT_ANY, 0); 23505 /* coverity[result_independent_of_operands] */ 23506 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23507 *arg = rval; 23508 return BCM_E_NONE; 23509 } 23510 } 23511 } 23512 return BCM_E_UNAVAIL; 23513 break; 23514 case bcmSwitchRxRedirectTruncatedPktReasons: 23515 if (soc_feature(unit, soc_feature_rcpu_1)) { 23516 uint32 raddr; 23517 rval = 0; 23518 #ifdef BCM_CMICM_SUPPORT 23519 if (soc_feature(unit, soc_feature_cmicm) 23520 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23521 SOC_IS_TD2_TT2(unit) || SOC_IS_HURRICANE2(unit) || 23522 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit))) { 23523 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_0_TYPEr, REG_PORT_ANY, 0); 23524 } else 23525 #endif 23526 { 23527 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINIr, REG_PORT_ANY, 0); 23528 } 23529 /* coverity[result_independent_of_operands] */ 23530 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23531 *arg = rval; 23532 return BCM_E_NONE; 23533 } else { 23534 return BCM_E_UNAVAIL; 23535 } 23536 break; 23537 case bcmSwitchRxRedirectTruncatedPktReasonsExtended: 23538 if (soc_feature(unit, soc_feature_rcpu_1)) { 23539 #ifdef BCM_CMICM_SUPPORT 23540 if (soc_feature(unit, soc_feature_cmicm) 23541 && (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 23542 SOC_IS_TD2_TT2(unit) || SOC_IS_GREYHOUND(unit) || 23543 SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit))) { 23544 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_MINI_1_TYPEr, REASONSf)) { 23545 uint32 raddr; 23546 rval = 0; 23547 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_1_TYPEr, REG_PORT_ANY, 0); 23548 /* coverity[result_independent_of_operands] */ 23549 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23550 *arg = rval; 23551 return BCM_E_NONE; 23552 } 23553 } else 23554 #endif 23555 { 23556 if (SOC_REG_FIELD_VALID(unit, CMIC_PKT_REASON_MINI_HIr, REASONSf)) { 23557 uint32 raddr; 23558 rval = 0; 23559 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_HIr, REG_PORT_ANY, 0); 23560 /* coverity[result_independent_of_operands] */ 23561 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23562 *arg = rval; 23563 return BCM_E_NONE; 23564 } 23565 } 23566 } 23567 return BCM_E_UNAVAIL; 23568 break; 23569 case bcmSwitchRxRedirectPktCos: 23570 #ifdef BCM_CMICM_SUPPORT 23571 if (soc_feature(unit, soc_feature_cmicm) && 23572 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_LOr)) { 23573 uint32 raddr; 23574 rval = 0; 23575 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_LOr, REG_PORT_ANY, 0); 23576 /* coverity[result_independent_of_operands] */ 23577 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23578 *arg = rval; 23579 return BCM_E_NONE; 23580 } else 23581 #endif 23582 { 23583 return BCM_E_UNAVAIL; 23584 } 23585 break; 23586 case bcmSwitchRxRedirectPktCosExtended: 23587 #ifdef BCM_CMICM_SUPPORT 23588 if (soc_feature(unit, soc_feature_cmicm) && 23589 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_HIr)) { 23590 uint32 raddr; 23591 rval = 0; 23592 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_HIr, REG_PORT_ANY, 0); 23593 /* coverity[result_independent_of_operands] */ 23594 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 23595 *arg = rval; 23596 return BCM_E_NONE; 23597 } else 23598 #endif 23599 { 23600 return BCM_E_UNAVAIL; 23601 } 23602 break; 23603 case bcmSwitchRemoteCpuLocalMacOui: 23604 case bcmSwitchRemoteCpuDestMacOui: 23605 if (soc_feature(unit, soc_feature_rcpu_1)) { 23606 return _bcm_rcpu_switch_mac_hi_get(unit, type, arg); 23607 } else { 23608 return BCM_E_UNAVAIL; 23609 } 23610 break; 23611 case bcmSwitchRemoteCpuTcMappingMacOui: 23612 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 23613 uint32 fieldval, regval; 23614 BCM_IF_ERROR_RETURN( 23615 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 23616 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 23617 DAf); 23618 *arg = fieldval >> 24; 23619 BCM_IF_ERROR_RETURN( 23620 READ_REMOTE_CPU_DA_MSr(unit, ®val)); 23621 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_MSr, regval, 23622 DAf); 23623 *arg |= (fieldval << 8 ); 23624 return BCM_E_NONE; 23625 } else { 23626 return BCM_E_UNAVAIL; 23627 } 23628 break; 23629 case bcmSwitchRemoteCpuLocalMacNonOui: 23630 case bcmSwitchRemoteCpuDestMacNonOui: 23631 if (soc_feature(unit, soc_feature_rcpu_1)) { 23632 return _bcm_rcpu_switch_mac_lo_get(unit, type, arg); 23633 } else { 23634 return BCM_E_UNAVAIL; 23635 } 23636 break; 23637 case bcmSwitchRemoteCpuTcMappingMacNonOui: 23638 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 23639 uint32 fieldval, regval; 23640 BCM_IF_ERROR_RETURN( 23641 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 23642 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 23643 DAf); 23644 *arg = ((fieldval << 8) >> 8); 23645 return BCM_E_NONE; 23646 } else { 23647 return BCM_E_UNAVAIL; 23648 } 23649 break; 23650 case bcmSwitchRemoteCpuEthertype: 23651 case bcmSwitchRemoteCpuVlan: 23652 case bcmSwitchRemoteCpuTpid: 23653 case bcmSwitchRemoteCpuSignature: 23654 if (soc_feature(unit, soc_feature_rcpu_1)) { 23655 return _bcm_rcpu_switch_vlan_tpid_sig_get(unit, type, arg); 23656 } else { 23657 return BCM_E_UNAVAIL; 23658 } 23659 break; 23660 case bcmSwitchRemoteCpuTcMappingEthertype: 23661 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 23662 uint32 regval; 23663 BCM_IF_ERROR_RETURN( 23664 READ_REMOTE_CPU_LENGTH_TYPEr(unit, ®val)); 23665 *arg = soc_reg_field_get(unit, REMOTE_CPU_LENGTH_TYPEr, regval, 23666 LENGTH_TYPEf); 23667 return BCM_E_NONE; 23668 } else { 23669 return BCM_E_UNAVAIL; 23670 } 23671 break; 23672 case bcmSwitchRemoteCpuDestPort: 23673 if (soc_feature(unit, soc_feature_rcpu_1)) { 23674 return _bcm_rcpu_pipe_bypass_header_get(unit, type, arg); 23675 } else { 23676 return BCM_E_UNAVAIL; 23677 } 23678 break; 23679 case bcmSwitchRemoteCpuHigigDestPort: 23680 if (soc_feature(unit, soc_feature_rcpu_1)) { 23681 return _bcm_rcpu_higig_header_get(unit, arg); 23682 } else { 23683 return BCM_E_UNAVAIL; 23684 } 23685 break; 23686 #endif 23687 #if defined(BCM_TRIUMPH2_SUPPORT) \ 23688 || defined(BCM_ENDURO_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 23689 case bcmSwitchServiceTpidReplace: 23690 if (SOC_IS_TRIUMPH2(unit) 23691 || SOC_IS_ENDURO(unit) || SOC_IS_TRIDENT(unit)) { 23692 rval = 0; 23693 /* Register settings requires "0" to enable TPID Replace and 23694 * "1" to disable TPID Modifications, when SD Action is "NOP" 23695 */ 23696 SOC_IF_ERROR_RETURN(READ_EGR_SD_TAG_CONTROLr(unit, &rval)); 23697 *arg = soc_reg_field_get (unit, 23698 EGR_SD_TAG_CONTROLr, rval, DO_NOT_MOD_TPID_ENABLEf); 23699 *arg = (*arg) ? 0 : 1; 23700 return BCM_E_NONE; 23701 } else { 23702 return BCM_E_UNAVAIL; 23703 } 23704 break; 23705 #endif /* TRIUMPH2 | ENDURO | TRIDENT */ 23706 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 23707 case bcmSwitchCongestionCntag: 23708 case bcmSwitchCongestionCntagEthertype: 23709 case bcmSwitchCongestionCnm: 23710 case bcmSwitchCongestionCnmEthertype: 23711 case bcmSwitchCongestionNotificationIdHigh: 23712 case bcmSwitchCongestionNotificationIdQueue: 23713 case bcmSwitchCongestionUseOuterTpid: 23714 case bcmSwitchCongestionUseOuterVlan: 23715 case bcmSwitchCongestionUseOuterPktPri: 23716 case bcmSwitchCongestionUseOuterCfi: 23717 case bcmSwitchCongestionUseInnerPktPri: 23718 case bcmSwitchCongestionUseInnerCfi: 23719 case bcmSwitchCongestionMissingCntag: 23720 case bcmSwitchCongestionCnmSrcMacNonOui: 23721 case bcmSwitchCongestionCnmSrcMacOui: 23722 return _bcm_switch_qcn_get(unit, type, arg); 23723 break; 23724 #endif /* defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) */ 23725 case bcmSwitchLoadBalanceHashSelect: 23726 { 23727 soc_reg_t reg; 23728 23729 COMPILER_64_ZERO(rval64); 23730 if (SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, LBID_RTAGf)){ 23731 reg = ING_CONFIG_64r; 23732 } else if (SOC_REG_FIELD_VALID(unit, ING_CONFIGr, LBID_RTAGf)) { 23733 reg = ING_CONFIGr; 23734 } else { 23735 return BCM_E_UNAVAIL; 23736 } 23737 23738 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, 23739 &rval64)); 23740 *arg = soc_reg64_field32_get(unit, reg, rval64, LBID_RTAGf); 23741 return (BCM_E_NONE); 23742 } 23743 break; 23744 #if defined(BCM_TRIDENT_SUPPORT) && defined(INCLUDE_L3) 23745 case bcmSwitchTrillEthertype: 23746 if (soc_feature(unit, soc_feature_trill)) { 23747 return bcm_td_trill_ethertype_get(unit, arg); 23748 } 23749 break; 23750 23751 case bcmSwitchTrillISISEthertype: 23752 if (soc_feature(unit, soc_feature_trill)) { 23753 return bcm_td_trill_ISIS_ethertype_get(unit, arg); 23754 } 23755 break; 23756 23757 case bcmSwitchTrillISISDestMacOui: 23758 case bcmSwitchTrillBroadcastDestMacOui: 23759 case bcmSwitchTrillEndStationDestMacOui: 23760 if (soc_feature(unit, soc_feature_trill)) { 23761 return bcm_td_trill_mac_get(unit, type, (uint32 *)arg, 1); 23762 } 23763 break; 23764 23765 case bcmSwitchTrillISISDestMacNonOui: 23766 case bcmSwitchTrillBroadcastDestMacNonOui: 23767 case bcmSwitchTrillEndStationDestMacNonOui: 23768 if (soc_feature(unit, soc_feature_trill)) { 23769 return bcm_td_trill_mac_get(unit, type, (uint32 *)arg, 0); 23770 } 23771 break; 23772 23773 case bcmSwitchTrillMinTtl: 23774 if (soc_feature(unit, soc_feature_trill)) { 23775 return bcm_td_trill_MinTtl_get(unit, arg); 23776 } 23777 break; 23778 23779 case bcmSwitchTrillTtlCheckEnable: 23780 if (soc_feature(unit, soc_feature_trill)) { 23781 return bcm_td_trill_TtlCheckEnable_get(unit, arg); 23782 } 23783 break; 23784 #endif /* BCM_TRIDENT_SUPPORT && INCLUDE_L3 */ 23785 #ifdef BCM_TRIDENT_SUPPORT 23786 case bcmSwitchFcoeEtherType: 23787 #if defined(BCM_TOMAHAWK3_SUPPORT) 23788 if (SOC_IS_TOMAHAWK3(unit)) { 23789 return BCM_E_UNAVAIL; 23790 } else 23791 #endif 23792 if (SOC_IS_TD_TT(unit) || 23793 SOC_IS_TRIUMPH3(unit)) { 23794 return _bcm_switch_fcoe_ing_ethertype_get(unit, arg); 23795 } 23796 break; 23797 #endif 23798 #if defined(BCM_FIREBOLT_SUPPORT) 23799 #if defined(INCLUDE_L3) 23800 case bcmSwitchL3TunnelIpV4ModeOnly: 23801 return soc_tunnel_term_block_size_get (unit, arg); 23802 break; 23803 case bcmSwitchL3SrcHitEnable: 23804 { 23805 soc_reg_t reg; 23806 23807 COMPILER_64_ZERO(rval64); 23808 if (SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, 23809 L3SRC_HIT_ENABLEf)){ 23810 reg = ING_CONFIG_64r; 23811 } else if (SOC_REG_FIELD_VALID(unit, ING_CONFIGr, 23812 L3SRC_HIT_ENABLEf)) { 23813 reg = ING_CONFIGr; 23814 } else { 23815 return BCM_E_UNAVAIL; 23816 } 23817 23818 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &rval64)); 23819 *arg = soc_reg64_field32_get(unit, reg, rval64, L3SRC_HIT_ENABLEf); 23820 return (BCM_E_NONE); 23821 } 23822 break; 23823 #endif /* INCLUDE_L3*/ 23824 #endif /* BCM_FIREBOLT_SUPPORT */ 23825 case bcmSwitchL2DstHitEnable: 23826 { 23827 soc_reg_t reg; 23828 23829 COMPILER_64_ZERO(rval64); 23830 if (SOC_REG_FIELD_VALID(unit, ING_CONFIG_64r, 23831 L2DST_HIT_ENABLEf)){ 23832 reg = ING_CONFIG_64r; 23833 } else if (SOC_REG_FIELD_VALID(unit, ING_CONFIGr, 23834 L2DST_HIT_ENABLEf)) { 23835 reg = ING_CONFIGr; 23836 } else { 23837 return BCM_E_UNAVAIL; 23838 } 23839 23840 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &rval64)); 23841 *arg = soc_reg64_field32_get(unit, reg, rval64, L2DST_HIT_ENABLEf); 23842 return (BCM_E_NONE); 23843 } 23844 break; 23845 case bcmSwitchHashDualMoveDepth: 23846 if (soc_feature(unit, soc_feature_dual_hash)) { 23847 *arg = SOC_DUAL_HASH_MOVE_MAX(unit); 23848 return BCM_E_NONE; 23849 } 23850 return BCM_E_UNAVAIL; 23851 break; 23852 case bcmSwitchHashDualMoveDepthL2: 23853 if (soc_feature(unit, soc_feature_dual_hash)) { 23854 *arg = SOC_DUAL_HASH_MOVE_MAX_L2X(unit); 23855 return BCM_E_NONE; 23856 } 23857 return BCM_E_UNAVAIL; 23858 break; 23859 case bcmSwitchHashDualMoveDepthMpls: 23860 if (soc_feature(unit, soc_feature_dual_hash)) { 23861 *arg = SOC_DUAL_HASH_MOVE_MAX_MPLS(unit); 23862 return BCM_E_NONE; 23863 } 23864 return BCM_E_UNAVAIL; 23865 break; 23866 case bcmSwitchHashDualMoveDepthVlan: 23867 if (soc_feature(unit, soc_feature_dual_hash)) { 23868 *arg = SOC_DUAL_HASH_MOVE_MAX_VLAN(unit); 23869 return BCM_E_NONE; 23870 } 23871 return BCM_E_UNAVAIL; 23872 case bcmSwitchHashDualMoveDepthEgressVlan: 23873 if (soc_feature(unit, soc_feature_dual_hash)) { 23874 *arg = SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit); 23875 return BCM_E_NONE; 23876 } 23877 return BCM_E_UNAVAIL; 23878 break; 23879 case bcmSwitchHashDualMoveDepthIngVpVlanMember: 23880 if (soc_feature(unit, soc_feature_dual_hash)) { 23881 *arg = SOC_DUAL_HASH_MOVE_MAX_ING_VP_VLAN_MEMBER(unit); 23882 return BCM_E_NONE; 23883 } 23884 return BCM_E_UNAVAIL; 23885 case bcmSwitchHashDualMoveDepthEgrVpVlanMember: 23886 if (soc_feature(unit, soc_feature_dual_hash)) { 23887 *arg = SOC_DUAL_HASH_MOVE_MAX_EGR_VP_VLAN_MEMBER(unit); 23888 return BCM_E_NONE; 23889 } 23890 return BCM_E_UNAVAIL; 23891 #if defined(BCM_TRIUMPH3_SUPPORT) 23892 case bcmSwitchHashDualMoveDepthWlanPort: 23893 if (soc_feature(unit, soc_feature_dual_hash)) { 23894 *arg = SOC_DUAL_HASH_MOVE_MAX_WLAN_PORT(unit); 23895 return BCM_E_NONE; 23896 } 23897 return BCM_E_UNAVAIL; 23898 break; 23899 case bcmSwitchHashDualMoveDepthWlanClient: 23900 if (soc_feature(unit, soc_feature_dual_hash)) { 23901 *arg = SOC_DUAL_HASH_MOVE_MAX_WLAN_CLIENT(unit); 23902 return BCM_E_NONE; 23903 } 23904 return BCM_E_UNAVAIL; 23905 break; 23906 23907 case bcmSwitchL2GreProtocolType: 23908 /* Get protocol-type for L2-GRE */ 23909 if ((soc_feature(unit, soc_feature_l2gre) 23910 #if defined(BCM_TRIDENT3_SUPPORT) 23911 || soc_feature(unit, soc_feature_flex_flow) 23912 #endif 23913 ) && SOC_REG_FIELD_VALID(unit, L2GRE_CONTROLr, ETHERTYPEf)) { 23914 rval = 0; 23915 23916 SOC_IF_ERROR_RETURN(READ_L2GRE_CONTROLr(unit, &rval)); 23917 *arg = soc_reg_field_get(unit, L2GRE_CONTROLr, rval, 23918 ETHERTYPEf); 23919 return BCM_E_NONE; 23920 } else { 23921 return BCM_E_UNAVAIL; 23922 } 23923 break; 23924 23925 case bcmSwitchL2GreVpnIdSizeSet: 23926 /* Get bit-size of VPNID within L2-GRE key */ 23927 if (soc_feature(unit, soc_feature_l2gre) 23928 #if defined(BCM_TRIDENT3_SUPPORT) 23929 || soc_feature(unit, soc_feature_flex_flow) 23930 #endif 23931 ) { 23932 uint32 regval; 23933 rval = 0; 23934 23935 SOC_IF_ERROR_RETURN(READ_L2GRE_CONTROLr(unit, &rval)); 23936 regval = soc_reg_field_get(unit, L2GRE_CONTROLr, rval, 23937 GRE_KEY_ENTROPY_SIZEf); 23938 switch (regval) { 23939 case 3: 23940 *arg = 16; 23941 break; 23942 case 2: 23943 *arg = 20; 23944 break; 23945 case 1: 23946 *arg = 24; 23947 break; 23948 case 0: 23949 *arg = 32; 23950 break; 23951 default: 23952 return BCM_E_PARAM; 23953 } 23954 return BCM_E_NONE; 23955 } else { 23956 return BCM_E_UNAVAIL; 23957 } 23958 break; 23959 23960 case bcmSwitchRemoteEncapsulationMode: 23961 #if defined(BCM_TOMAHAWK3_SUPPORT) 23962 if (SOC_IS_TOMAHAWK3(unit)) { 23963 return BCM_E_UNAVAIL; 23964 } else 23965 #endif 23966 if (SOC_IS_TRIDENT3X(unit)) { 23967 return BCM_E_UNAVAIL; 23968 } 23969 *arg = SOC_REMOTE_ENCAP(unit); 23970 return BCM_E_NONE; 23971 break; 23972 23973 #endif 23974 23975 #if defined(BCM_TRIDENT2_SUPPORT) && defined(INCLUDE_L3) 23976 case bcmSwitchVxlanUdpDestPortSet: 23977 /* Get UDP Dest port for VXLAN */ 23978 if ((soc_feature(unit, soc_feature_vxlan)) || 23979 (soc_feature(unit, soc_feature_flex_flow))) { 23980 23981 return bcm_td2_vxlan_udpDestPort_get(unit, arg); 23982 } else { 23983 return BCM_E_UNAVAIL; 23984 } 23985 break; 23986 23987 case bcmSwitchVxlanEntropyEnable: 23988 /* Enable UDP Source Port Hash for VXLAN */ 23989 if ((soc_feature(unit, soc_feature_vxlan)) || 23990 (soc_feature(unit, soc_feature_flex_flow))) { 23991 23992 return bcm_td2_vxlan_udpSourcePort_get(unit, arg); 23993 } else { 23994 return BCM_E_UNAVAIL; 23995 } 23996 break; 23997 #endif /* defined(BCM_TRIDENT2_SUPPORT) && defined(INCLUDE_L3) */ 23998 23999 #if defined(INCLUDE_L3) 24000 case bcmSwitchHashDualMoveDepthL3: 24001 if (soc_feature(unit, soc_feature_dual_hash)) { 24002 *arg = SOC_DUAL_HASH_MOVE_MAX_L3X(unit); 24003 return BCM_E_NONE; 24004 } 24005 return BCM_E_UNAVAIL; 24006 break; 24007 case bcmSwitchHashL3DualLeastFull: 24008 if (soc_feature(unit, soc_feature_dual_hash)) { 24009 if (SOC_REG_FIELD_VALID(unit, L3_AUX_HASH_CONTROLr, 24010 INSERT_LEAST_FULL_HALFf)) { 24011 rval = 0; 24012 BCM_IF_ERROR_RETURN(READ_L3_AUX_HASH_CONTROLr(unit, &rval)); 24013 *arg = soc_reg_field_get(unit, L3_AUX_HASH_CONTROLr, 24014 rval, INSERT_LEAST_FULL_HALFf); 24015 return BCM_E_NONE; 24016 } 24017 } 24018 return BCM_E_UNAVAIL; 24019 break; 24020 #endif 24021 case bcmSwitchHashMultiMoveDepth: 24022 if (soc_feature(unit, soc_feature_ism_memory) || 24023 soc_feature(unit, soc_feature_shared_hash_mem)) { 24024 *arg = SOC_MULTI_HASH_MOVE_MAX(unit); 24025 return BCM_E_NONE; 24026 } 24027 return BCM_E_UNAVAIL; 24028 break; 24029 case bcmSwitchHashMultiMoveDepthL2: 24030 if (soc_feature(unit, soc_feature_ism_memory) || 24031 soc_feature(unit, soc_feature_shared_hash_mem)) { 24032 *arg = SOC_MULTI_HASH_MOVE_MAX_L2(unit); 24033 return BCM_E_NONE; 24034 } 24035 return BCM_E_UNAVAIL; 24036 break; 24037 case bcmSwitchHashMultiMoveDepthL3: 24038 if (soc_feature(unit, soc_feature_ism_memory) || 24039 soc_feature(unit, soc_feature_shared_hash_mem)) { 24040 *arg = SOC_MULTI_HASH_MOVE_MAX_L3(unit); 24041 return BCM_E_NONE; 24042 } 24043 return BCM_E_UNAVAIL; 24044 break; 24045 case bcmSwitchHashMultiMoveDepthMpls: 24046 if (soc_feature(unit, soc_feature_ism_memory) || 24047 (soc_feature(unit, soc_feature_shared_hash_mem) && 24048 SOC_IS_TRIDENT3X(unit)) || SOC_IS_TOMAHAWK3(unit)) { 24049 *arg = SOC_MULTI_HASH_MOVE_MAX_MPLS(unit); 24050 return BCM_E_NONE; 24051 } 24052 return BCM_E_UNAVAIL; 24053 break; 24054 case bcmSwitchHashMultiMoveDepthVlan: 24055 if (soc_feature(unit, soc_feature_ism_memory) || 24056 (soc_feature(unit, soc_feature_shared_hash_mem) && 24057 SOC_IS_TRIDENT3X(unit))) { 24058 *arg = SOC_MULTI_HASH_MOVE_MAX_VLAN(unit); 24059 return BCM_E_NONE; 24060 } 24061 return BCM_E_UNAVAIL; 24062 break; 24063 case bcmSwitchHashMultiMoveDepthVlanTranslate1: 24064 if (soc_feature(unit, soc_feature_ism_memory) || 24065 (soc_feature(unit, soc_feature_shared_hash_mem) && 24066 SOC_IS_TRIDENT3X(unit))) { 24067 *arg = SOC_MULTI_HASH_MOVE_MAX_VLAN_1(unit); 24068 return BCM_E_NONE; 24069 } 24070 return BCM_E_UNAVAIL; 24071 break; 24072 case bcmSwitchHashMultiMoveDepthVlanTranslate2: 24073 if (soc_feature(unit, soc_feature_ism_memory) || 24074 (soc_feature(unit, soc_feature_shared_hash_mem) && 24075 SOC_IS_TRIDENT3X(unit))) { 24076 *arg = SOC_MULTI_HASH_MOVE_MAX_VLAN_2(unit); 24077 return BCM_E_NONE; 24078 } 24079 return BCM_E_UNAVAIL; 24080 break; 24081 case bcmSwitchHashMultiMoveDepthEgressVlan: 24082 if (soc_feature(unit, soc_feature_ism_memory) || 24083 (soc_feature(unit, soc_feature_shared_hash_mem) && 24084 SOC_IS_TRIDENT3X(unit))) { 24085 *arg = SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN(unit); 24086 return BCM_E_NONE; 24087 } 24088 return BCM_E_UNAVAIL; 24089 break; 24090 case bcmSwitchHashMultiMoveDepthEgressVlanTranslate1: 24091 if (soc_feature(unit, soc_feature_ism_memory) || 24092 (soc_feature(unit, soc_feature_shared_hash_mem) && 24093 SOC_IS_TRIDENT3X(unit))) { 24094 *arg = SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_1(unit); 24095 return BCM_E_NONE; 24096 } 24097 return BCM_E_UNAVAIL; 24098 break; 24099 case bcmSwitchHashMultiMoveDepthEgressVlanTranslate2: 24100 if (soc_feature(unit, soc_feature_ism_memory) || 24101 (soc_feature(unit, soc_feature_shared_hash_mem) && 24102 SOC_IS_TRIDENT3X(unit))) { 24103 *arg = SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_2(unit); 24104 return BCM_E_NONE; 24105 } 24106 return BCM_E_UNAVAIL; 24107 break; 24108 case bcmSwitchHashMultiMoveDepthExactMatch: 24109 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 24110 *arg = SOC_MULTI_HASH_MOVE_MAX_FPEM(unit); 24111 return BCM_E_NONE; 24112 } 24113 return BCM_E_UNAVAIL; 24114 break; 24115 24116 #ifdef BCM_TOMAHAWK3_SUPPORT 24117 case bcmSwitchHashMultiMoveDepthL3Tunnel: 24118 if (SOC_IS_TOMAHAWK3(unit)) { 24119 *arg = SOC_MULTI_HASH_MOVE_MAX_L3_TUNNEL(unit); 24120 return BCM_E_NONE; 24121 } 24122 return BCM_E_UNAVAIL; 24123 break; 24124 #endif /* BCM_TOMAHAWK3_SUPPORT */ 24125 case bcmSwitchHashL2DualLeastFull: 24126 if (soc_feature(unit, soc_feature_dual_hash)) { 24127 if (SOC_REG_FIELD_VALID(unit, L2_AUX_HASH_CONTROLr, 24128 INSERT_LEAST_FULL_HALFf)) { 24129 rval = 0; 24130 BCM_IF_ERROR_RETURN(READ_L2_AUX_HASH_CONTROLr(unit, &rval)); 24131 *arg = soc_reg_field_get(unit, L2_AUX_HASH_CONTROLr, 24132 rval, INSERT_LEAST_FULL_HALFf); 24133 return BCM_E_NONE; 24134 } 24135 } 24136 return BCM_E_UNAVAIL; 24137 break; 24138 case bcmSwitchHashMPLSDualLeastFull: 24139 if (soc_feature(unit, soc_feature_dual_hash)) { 24140 if (SOC_REG_FIELD_VALID(unit, MPLS_ENTRY_HASH_CONTROLr, 24141 INSERT_LEAST_FULL_HALFf)) { 24142 rval = 0; 24143 BCM_IF_ERROR_RETURN(READ_MPLS_ENTRY_HASH_CONTROLr(unit, &rval)); 24144 *arg = soc_reg_field_get(unit, MPLS_ENTRY_HASH_CONTROLr, 24145 rval, INSERT_LEAST_FULL_HALFf); 24146 return BCM_E_NONE; 24147 } 24148 } 24149 return BCM_E_UNAVAIL; 24150 break; 24151 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) || \ 24152 defined(BCM_VALKYRIE2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 24153 defined(BCM_KATANA2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 24154 case bcmSwitchSynchronousPortClockSource: 24155 { 24156 uint32 val = 0; 24157 if (soc_feature(unit, soc_feature_gmii_clkout)) { 24158 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || \ 24159 defined(BCM_KATANA_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 24160 defined(BCM_KATANA2_SUPPORT) 24161 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANEX(unit) || 24162 SOC_IS_KATANA(unit) || SOC_IS_GREYHOUND(unit) || 24163 SOC_IS_KATANA2(unit)) { 24164 return _bcm_switch_sync_port_select_get(unit, 1, (uint32 *)arg); 24165 } else 24166 #endif 24167 { 24168 SOC_IF_ERROR_RETURN(READ_EGR_L1_CLK_RECOVERY_CTRLr(unit, &val)); 24169 *arg = soc_reg_field_get(unit, EGR_L1_CLK_RECOVERY_CTRLr, 24170 val, PRI_PORT_SELf); 24171 return (BCM_E_NONE); 24172 } 24173 } else { 24174 return BCM_E_UNAVAIL; 24175 } 24176 } 24177 break; 24178 case bcmSwitchSynchronousPortClockSourceBkup: 24179 { 24180 uint32 val = 0; 24181 if (soc_feature(unit, soc_feature_gmii_clkout)) { 24182 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_HURRICANE_SUPPORT) || \ 24183 defined(BCM_KATANA_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) || \ 24184 defined(BCM_KAATANA2_SUPPORT) 24185 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANEX(unit) || 24186 SOC_IS_KATANA(unit) || SOC_IS_GREYHOUND(unit) || 24187 SOC_IS_KATANA2(unit)) { 24188 return _bcm_switch_sync_port_select_get(unit, 0, (uint32 *)arg); 24189 } else 24190 #endif 24191 { 24192 SOC_IF_ERROR_RETURN(READ_EGR_L1_CLK_RECOVERY_CTRLr(unit, &val)); 24193 *arg = soc_reg_field_get(unit, EGR_L1_CLK_RECOVERY_CTRLr, 24194 val, BKUP_PORT_SELf); 24195 return (BCM_E_NONE); 24196 } 24197 } else { 24198 return BCM_E_UNAVAIL; 24199 } 24200 } 24201 break; 24202 24203 case bcmSwitchSynchronousPortClockSourceDivCtrl: 24204 if (soc_feature(unit, soc_feature_gmii_clkout)) { 24205 #if defined(BCM_HURRICANE_SUPPORT) || defined(BCM_KATANA_SUPPORT) || \ 24206 defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 24207 if (SOC_IS_HURRICANE(unit) || SOC_IS_KATANA(unit) || 24208 SOC_IS_GREYHOUND(unit) || SOC_IS_KATANA2(unit) || 24209 SOC_IS_HURRICANE3(unit)) { 24210 return _bcm_switch_div_ctrl_select_get(unit, 1, (uint32 *)arg); 24211 } else { 24212 return BCM_E_UNAVAIL; 24213 } 24214 #else 24215 { 24216 return BCM_E_UNAVAIL; 24217 } 24218 #endif 24219 } else { 24220 return BCM_E_UNAVAIL; 24221 } 24222 break; 24223 24224 case bcmSwitchSynchronousPortClockSourceBkupDivCtrl: 24225 if (soc_feature(unit, soc_feature_gmii_clkout)) { 24226 #if defined(BCM_HURRICANE_SUPPORT) || defined(BCM_KATANA_SUPPORT) || \ 24227 defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 24228 if (SOC_IS_HURRICANE(unit) || SOC_IS_KATANA(unit) || 24229 SOC_IS_GREYHOUND(unit) || SOC_IS_KATANA2(unit) || 24230 SOC_IS_HURRICANE3(unit)) { 24231 return _bcm_switch_div_ctrl_select_get(unit, 0, (uint32 *)arg); 24232 } else { 24233 return BCM_E_UNAVAIL; 24234 } 24235 #else 24236 { 24237 return BCM_E_UNAVAIL; 24238 } 24239 #endif 24240 } else { 24241 return BCM_E_UNAVAIL; 24242 } 24243 #endif 24244 break; 24245 24246 #if (defined(BCM_TRIDENT_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT)) && \ 24247 defined(INCLUDE_L3) 24248 case bcmSwitchNivEthertype: 24249 if (soc_feature(unit, soc_feature_niv)) { 24250 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 24251 #if defined(BCM_GREYHOUND_SUPPORT) 24252 return bcm_gh_niv_ethertype_get(unit, arg); 24253 #endif /* BCM_GREYHOUND_SUPPORT */ 24254 } 24255 #if defined(BCM_TRIDENT_SUPPORT) 24256 else { 24257 return bcm_trident_niv_ethertype_get(unit, arg); 24258 } 24259 #endif /* BCM_TRIDENT_SUPPORT */ 24260 } 24261 return BCM_E_UNAVAIL; 24262 break; 24263 #endif /* (BCM_TRIDENT_SUPPORT || BCM_GREYHOUND_SUPPORT) && INCLUDE_L3 */ 24264 #if defined(BCM_KATANA2_SUPPORT) 24265 case bcmSwitchSubportPktTagEthertype: 24266 if (soc_feature(unit, soc_feature_lltag)) { 24267 return _bcm_switch_subportpkttag_ethertype_get(unit, arg); 24268 } 24269 return BCM_E_UNAVAIL; 24270 break; 24271 #endif 24272 #if (defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT)) && \ 24273 defined(INCLUDE_L3) 24274 case bcmSwitchEtagEthertype: 24275 if (soc_feature(unit, soc_feature_port_extension)) { 24276 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 24277 #if defined(BCM_GREYHOUND_SUPPORT) 24278 return bcm_gh_etag_ethertype_get(unit, arg); 24279 #endif /* BCM_GREYHOUND_SUPPORT */ 24280 } 24281 #if defined(BCM_TRIUMPH3_SUPPORT) 24282 else { 24283 return bcm_tr3_etag_ethertype_get(unit, arg); 24284 } 24285 #endif /* BCM_TRIUMPH3_SUPPORT */ 24286 } 24287 return BCM_E_UNAVAIL; 24288 break; 24289 case bcmSwitchExtenderMulticastLowerThreshold: 24290 if (soc_feature(unit, soc_feature_port_extension)) { 24291 uint32 etag_range = 0; 24292 SOC_IF_ERROR_RETURN(READ_ETAG_MULTICAST_RANGEr(unit, &etag_range)); 24293 *arg = soc_reg_field_get(unit, ETAG_MULTICAST_RANGEr, etag_range, 24294 ETAG_VID_MULTICAST_LOWERf); 24295 return BCM_E_NONE; 24296 } 24297 return BCM_E_UNAVAIL; 24298 break; 24299 case bcmSwitchExtenderMulticastHigherThreshold: 24300 if (soc_feature(unit, soc_feature_port_extension)) { 24301 uint32 etag_range = 0; 24302 SOC_IF_ERROR_RETURN(READ_ETAG_MULTICAST_RANGEr(unit, &etag_range)); 24303 *arg = soc_reg_field_get(unit, ETAG_MULTICAST_RANGEr, etag_range, 24304 ETAG_VID_MULTICAST_UPPERf); 24305 return BCM_E_NONE; 24306 } 24307 return BCM_E_UNAVAIL; 24308 break; 24309 #endif /* (BCM_TRIUMPH3_SUPPORT || BCM_GREYHOUND_SUPPORT) && INCLUDE_L3 */ 24310 24311 case bcmSwitchWESPProtocolEnable: 24312 if (soc_feature(unit, soc_feature_wesp)) { 24313 rval = 0;; 24314 BCM_IF_ERROR_RETURN(READ_ING_WESP_PROTO_CONTROLr(unit, &rval)); 24315 *arg = soc_reg_field_get(unit, ING_WESP_PROTO_CONTROLr, rval, 24316 WESP_PROTO_NUMBER_ENABLEf); 24317 return BCM_E_NONE; 24318 } 24319 return BCM_E_UNAVAIL; 24320 break; 24321 case bcmSwitchWESPProtocol: 24322 if (soc_feature(unit, soc_feature_wesp)) { 24323 rval = 0; 24324 BCM_IF_ERROR_RETURN(READ_ING_WESP_PROTO_CONTROLr(unit, &rval)); 24325 *arg = soc_reg_field_get(unit, ING_WESP_PROTO_CONTROLr, rval, 24326 WESP_PROTO_NUMBERf); 24327 return BCM_E_NONE; 24328 } 24329 return BCM_E_UNAVAIL; 24330 break; 24331 24332 #if defined(BCM_TRIDENT_SUPPORT) 24333 case bcmSwitchIp6CompressEnable: 24334 if (SOC_REG_FIELD_VALID(unit, ING_MISC_CONFIG2r, 24335 IPV6_TO_IPV4_ADDRESS_MAP_ENABLEf)) { 24336 rval = 0; 24337 BCM_IF_ERROR_RETURN(READ_ING_MISC_CONFIG2r(unit, &rval)); 24338 *arg = soc_reg_field_get(unit, ING_MISC_CONFIG2r, rval, 24339 IPV6_TO_IPV4_ADDRESS_MAP_ENABLEf); 24340 return BCM_E_NONE; 24341 } 24342 return BCM_E_UNAVAIL; 24343 break; 24344 24345 case bcmSwitchIp6CompressDefaultOffset: 24346 if (SOC_REG_FIELD_VALID(unit, ING_MISC_CONFIG2r, 24347 IPV6_TO_IPV4_MAP_OFFSET_DEFAULTf)) { 24348 rval = 0; 24349 BCM_IF_ERROR_RETURN(READ_ING_MISC_CONFIG2r(unit, &rval)); 24350 *arg = soc_reg_field_get(unit, ING_MISC_CONFIG2r, rval, 24351 IPV6_TO_IPV4_MAP_OFFSET_DEFAULTf); 24352 return BCM_E_NONE; 24353 } 24354 return BCM_E_UNAVAIL; 24355 break; 24356 #endif 24357 case bcmSwitchMirrorPktChecksEnable: 24358 #if defined(BCM_TRIDENT3_SUPPORT) 24359 if (SOC_REG_IS_VALID(unit,EGR_CONFIG_1_64r)) { 24360 if (SOC_REG_FIELD_VALID(unit, EGR_CONFIG_1_64r, 24361 DISABLE_MIRROR_CHECKSf)) { 24362 COMPILER_64_ZERO(rval64); 24363 BCM_IF_ERROR_RETURN(soc_reg_get(unit, EGR_CONFIG_1_64r, 24364 REG_PORT_ANY, 0, &rval64)); 24365 *arg = soc_reg64_field32_get(unit, EGR_CONFIG_1_64r, rval64, 24366 DISABLE_MIRROR_CHECKSf)? 0 : 1; 24367 return BCM_E_NONE; 24368 } 24369 } else 24370 #endif 24371 { 24372 if (SOC_REG_FIELD_VALID(unit, EGR_CONFIG_1r, 24373 DISABLE_MIRROR_CHECKSf)) { 24374 rval = 0; 24375 BCM_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 24376 if (soc_reg_field_get(unit, EGR_CONFIG_1r, rval, 24377 DISABLE_MIRROR_CHECKSf)) { 24378 *arg = 0; 24379 } else { 24380 *arg = 1; 24381 } 24382 return BCM_E_NONE; 24383 } 24384 } 24385 return BCM_E_UNAVAIL; 24386 break; 24387 24388 case bcmSwitchStableSaveLongIds: 24389 #if defined(BCM_FIELD_SUPPORT) && defined(BCM_WARM_BOOT_SUPPORT) 24390 { 24391 _field_control_t *fc; 24392 24393 rv = _field_control_get(unit, &fc); 24394 if (BCM_FAILURE(rv)) { 24395 return BCM_E_UNAVAIL; 24396 } 24397 24398 *arg = ((fc->flags & _FP_STABLE_SAVE_LONG_IDS) != 0); 24399 } 24400 return (BCM_E_NONE); 24401 #else 24402 return (BCM_E_UNAVAIL); 24403 #endif 24404 break; 24405 24406 #if defined(BCM_TRIUMPH_SUPPORT) 24407 case bcmSwitchGportAnyDefaultL2Learn: 24408 case bcmSwitchGportAnyDefaultL2Move: 24409 if (soc_feature(unit, soc_feature_virtual_switching)) { 24410 return _bcm_switch_default_cml_get(unit, type, arg); 24411 } 24412 return BCM_E_UNAVAIL; 24413 break; 24414 #endif /* BCM_TRIUMPH_SUPPORT */ 24415 24416 #if (defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT)) 24417 case bcmSwitchSetMplsEntropyLabelTtl: 24418 if (soc_feature(unit, soc_feature_mpls_entropy) && 24419 soc_reg_field_valid(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, TTLf)) { 24420 rval = 0; 24421 24422 SOC_IF_ERROR_RETURN(READ_EGR_MPLS_ENTROPY_LABEL_CONTROLr(unit, &rval)); 24423 *arg = soc_reg_field_get(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, rval, TTLf); 24424 return BCM_E_NONE; 24425 } 24426 return BCM_E_UNAVAIL; 24427 break; 24428 24429 case bcmSwitchSetMplsEntropyLabelPri: 24430 if (soc_feature(unit, soc_feature_mpls_entropy) && 24431 soc_reg_field_valid(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, TCf)) { 24432 rval = 0; 24433 24434 SOC_IF_ERROR_RETURN(READ_EGR_MPLS_ENTROPY_LABEL_CONTROLr(unit, &rval)); 24435 *arg = soc_reg_field_get(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, rval, TCf); 24436 return BCM_E_NONE; 24437 } 24438 return BCM_E_UNAVAIL; 24439 break; 24440 24441 case bcmSwitchSetMplsEntropyLabelOffset: 24442 if (soc_feature(unit, soc_feature_mpls_entropy) && 24443 soc_reg_field_valid(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, LABEL_OFFSETf)) { 24444 rval = 0; 24445 24446 SOC_IF_ERROR_RETURN(READ_EGR_MPLS_ENTROPY_LABEL_CONTROLr(unit, &rval)); 24447 *arg = soc_reg_field_get(unit, EGR_MPLS_ENTROPY_LABEL_CONTROLr, rval, LABEL_OFFSETf); 24448 return BCM_E_NONE; 24449 } 24450 return BCM_E_UNAVAIL; 24451 break; 24452 #endif 24453 24454 #if defined(BCM_TRIUMPH2_SUPPORT) && defined(INCLUDE_L3) 24455 case bcmSwitchMultipathCompress: 24456 if (soc_feature(unit, soc_feature_l3) && 24457 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 24458 *arg = TRUE; 24459 return BCM_E_NONE; 24460 } 24461 break; 24462 24463 case bcmSwitchMultipathCompressBuffer: 24464 if (soc_feature(unit, soc_feature_l3) && 24465 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 24466 return bcm_tr2_l3_ecmp_defragment_buffer_get(unit, arg); 24467 } 24468 break; 24469 #endif /* BCM_TRIUMPH2_SUPPORT && INCLUDE_L3 */ 24470 24471 case bcmSwitchBstEnable: 24472 #if defined(BCM_TRIUMPH3_SUPPORT) 24473 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 24474 return _bcm_bst_cmn_control_get(unit, bcmSwitchBstEnable, arg); 24475 } 24476 #endif /* BCM_TRIUMPH3_SUPPORT */ 24477 24478 return BCM_E_UNAVAIL; 24479 break; 24480 24481 case bcmSwitchBstTrackingMode: 24482 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 24483 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 24484 return _bcm_bst_cmn_control_get(unit, bcmSwitchBstTrackingMode, arg); 24485 } 24486 #endif /* BCM_TRIUMPH3_SUPPORT */ 24487 24488 return BCM_E_UNAVAIL; 24489 break; 24490 24491 case bcmSwitchBstSnapshotEnable: 24492 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 24493 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 24494 return _bcm_bst_cmn_control_get(unit, bcmSwitchBstSnapshotEnable, arg); 24495 } 24496 #endif /* BCM_TRIUMPH3_SUPPORT */ 24497 24498 return BCM_E_UNAVAIL; 24499 break; 24500 24501 #ifdef BCM_TRIDENT_SUPPORT 24502 case bcmSwitchFabricTrunkAutoIncludeDisable: 24503 if (!soc_feature(unit, soc_feature_modport_map_dest_is_port_or_trunk)) { 24504 return BCM_E_UNAVAIL; 24505 } 24506 return bcm_td_modport_map_mode_get(unit, type, arg); 24507 break; 24508 #endif /* BCM_TRIDENT_SUPPORT */ 24509 24510 case bcmSwitchL2OverflowEvent: 24511 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || \ 24512 defined(BCM_HURRICANE3_SUPPORT) || defined(BCM_SCORPION_SUPPORT) 24513 if (soc_feature(unit, soc_feature_l2_overflow)) { 24514 *arg = SOC_CONTROL(unit)->l2_overflow_enable ? 1 : 0; 24515 return BCM_E_NONE; 24516 } 24517 #endif /* BCM_TRIUMPH3_SUPPORT */ 24518 24519 return BCM_E_UNAVAIL; 24520 break; 24521 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) 24522 case bcmSwitchMiMDefaultSVPValue: 24523 { 24524 int mim_svp = 0, isgport = 0; 24525 24526 BCM_IF_ERROR_RETURN(bcm_esw_switch_control_get(unit, 24527 bcmSwitchUseGport, &isgport)); 24528 24529 if (SOC_REG_IS_VALID(unit, MIM_DEFAULT_NETWORK_SVPr)) { 24530 rval = 0; 24531 BCM_IF_ERROR_RETURN(READ_MIM_DEFAULT_NETWORK_SVPr(unit, &rval)); 24532 mim_svp = soc_reg_field_get(unit, MIM_DEFAULT_NETWORK_SVPr, 24533 rval, SVPf); 24534 if (isgport) { 24535 BCM_GPORT_MIM_PORT_ID_SET(*arg, mim_svp); 24536 } else { 24537 *arg = mim_svp; 24538 } 24539 return BCM_E_NONE; 24540 } else if (soc_feature(unit, 24541 soc_feature_mim_reserve_default_port)) { 24542 rval = 0; 24543 SOC_IF_ERROR_RETURN(READ_ING_Q_BEGINr(unit, &rval)); 24544 mim_svp = soc_reg_field_get(unit, ING_Q_BEGINr, rval, 24545 ENABLE_DEFAULT_NETWORK_SVPf); 24546 if (isgport) { 24547 BCM_GPORT_MIM_PORT_ID_SET(*arg, mim_svp); 24548 } else { 24549 *arg = mim_svp; 24550 } 24551 return BCM_E_NONE; 24552 } 24553 else { 24554 return BCM_E_UNAVAIL; 24555 } 24556 } 24557 break; 24558 #endif 24559 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 24560 case bcmSwitchIpmcSameVlanPruning: 24561 if (SOC_IS_TOMAHAWK3(unit)) { 24562 rval = 0; 24563 SOC_IF_ERROR_RETURN(READ_MMU_RQE_REPL_CONFIGr(unit, &rval)); 24564 *arg = soc_reg_field_get(unit, MMU_RQE_REPL_CONFIGr, rval, 24565 IPMC_IND_MODEf); 24566 *arg = (*arg ? 0 : 1); 24567 return BCM_E_NONE; 24568 } 24569 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_HELIX4(unit) || 24570 SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit)) { 24571 rval = 0; 24572 SOC_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 24573 *arg = soc_reg_field_get(unit, ING_MISC_CONFIGr, rval, IPMC_IND_MODEf); 24574 *arg = (*arg ? 0 : 1); 24575 return BCM_E_NONE; 24576 } 24577 break; 24578 #endif 24579 24580 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 24581 case bcmSwitchOamCcmToCpu: 24582 if (soc_feature(unit, soc_feature_oam)) { 24583 if (soc_reg_field_valid(unit, CCM_COPYTO_CPU_CONTROLr, 24584 ERROR_CCM_COPY_TOCPUf)) { 24585 rval = 0; 24586 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 24587 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 24588 ERROR_CCM_COPY_TOCPUf); 24589 return BCM_E_NONE; 24590 } 24591 } 24592 return BCM_E_UNAVAIL; 24593 break; 24594 24595 case bcmSwitchOamXconCcmToCpu: 24596 if (soc_feature(unit, soc_feature_oam)) { 24597 if (soc_reg_field_valid(unit, CCM_COPYTO_CPU_CONTROLr, 24598 XCON_CCM_COPY_TOCPUf)) { 24599 rval = 0; 24600 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 24601 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 24602 XCON_CCM_COPY_TOCPUf); 24603 return BCM_E_NONE; 24604 } 24605 } 24606 return BCM_E_UNAVAIL; 24607 break; 24608 case bcmSwitchOamXconOtherToCpu: 24609 if (soc_feature(unit, soc_feature_oam)) { 24610 if (soc_reg_field_valid(unit, CCM_COPYTO_CPU_CONTROLr, 24611 XCON_OTHER_COPY_TOCPUf)) { 24612 rval = 0; 24613 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 24614 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 24615 XCON_OTHER_COPY_TOCPUf); 24616 return BCM_E_NONE; 24617 } 24618 } 24619 return BCM_E_UNAVAIL; 24620 break; 24621 #endif 24622 24623 #if defined(BCM_KATANA2_SUPPORT) 24624 case bcmSwitchOamHeaderErrorToCpu: 24625 if (soc_feature(unit, soc_feature_oam)) { 24626 rval = 0; 24627 if (SOC_IS_SABER2(unit)) { 24628 SOC_IF_ERROR_RETURN(READ_OAM_COPYTO_CPU_CONTROLr(unit, &rval)); 24629 *arg = soc_reg_field_get(unit, OAM_COPYTO_CPU_CONTROLr, rval, 24630 OAM_HEADER_ERROR_TOCPUf); 24631 return BCM_E_NONE; 24632 } else if (SOC_IS_KATANA2(unit)) { 24633 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 24634 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 24635 OAM_HEADER_ERROR_TOCPUf); 24636 return BCM_E_NONE; 24637 } 24638 } 24639 break; 24640 24641 case bcmSwitchOamUnknownVersionToCpu: 24642 if (soc_feature(unit, soc_feature_oam)) { 24643 rval = 0; 24644 if (SOC_IS_SABER2(unit)) { 24645 SOC_IF_ERROR_RETURN(READ_OAM_COPYTO_CPU_CONTROLr(unit, &rval)); 24646 *arg = soc_reg_field_get(unit, OAM_COPYTO_CPU_CONTROLr, rval, 24647 OAM_UNKNOWN_OPCODE_VERSION_TOCPUf); 24648 return BCM_E_NONE; 24649 } else if (SOC_IS_KATANA2(unit)) { 24650 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 24651 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 24652 OAM_UNKNOWN_OPCODE_VERSION_TOCPUf); 24653 return BCM_E_NONE; 24654 } 24655 } 24656 break; 24657 24658 case bcmSwitchOamUnknownVersionDrop: 24659 if (SOC_IS_KATANA2(unit) && (soc_feature(unit, soc_feature_oam))) { 24660 rval = 0; 24661 SOC_IF_ERROR_RETURN(READ_OAM_DROP_CONTROLr(unit, &rval)); 24662 *arg = soc_reg_field_get(unit, OAM_DROP_CONTROLr, rval, 24663 IFP_OAM_UNKNOWN_OPCODE_VERSION_DROPf); 24664 return BCM_E_NONE; 24665 } 24666 break; 24667 24668 case bcmSwitchOamUnexpectedPktToCpu: 24669 if (soc_feature(unit, soc_feature_oam)) { 24670 rval = 0; 24671 if (SOC_IS_SABER2(unit)) { 24672 SOC_IF_ERROR_RETURN(READ_OAM_COPYTO_CPU_CONTROLr(unit, &rval)); 24673 *arg = soc_reg_field_get(unit, OAM_COPYTO_CPU_CONTROLr, rval, 24674 OAM_UNEXPECTED_PKT_TOCPUf); 24675 return BCM_E_NONE; 24676 } else if (SOC_IS_KATANA2(unit)) { 24677 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 24678 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 24679 OAM_UNEXPECTED_PKT_TOCPUf); 24680 return BCM_E_NONE; 24681 } 24682 } 24683 break; 24684 24685 case bcmSwitchOamVersionCheckDisable: 24686 if (soc_feature(unit, soc_feature_oam)) { 24687 rval = 0; 24688 if (SOC_IS_SABER2(unit)) { 24689 SOC_IF_ERROR_RETURN(READ_OAM_ERROR_CONTROLr(unit, &rval)); 24690 *arg = soc_reg_field_get(unit, OAM_ERROR_CONTROLr, rval, 24691 OAM_VER_CHECK_DISABLEf); 24692 return BCM_E_NONE; 24693 } else if (SOC_IS_KATANA2(unit)) { 24694 SOC_IF_ERROR_RETURN(READ_OAM_CONTROL_1r(unit, &rval)); 24695 *arg = soc_reg_field_get(unit, OAM_CONTROL_1r, rval, 24696 OAM_VER_CHECK_DISABLEf); 24697 return BCM_E_NONE; 24698 } 24699 } 24700 return BCM_E_UNAVAIL; 24701 break; 24702 #endif 24703 #if defined (BCM_OLP_SUPPORT) 24704 case bcmSwitchOamOlpChipEtherType: 24705 if (soc_feature(unit, soc_feature_olp)) { 24706 COMPILER_64_ZERO(rval64); 24707 SOC_IF_ERROR_RETURN(READ_IARB_OLP_CONFIGr(unit, &rval64)); 24708 *arg = soc_reg64_field32_get(unit, IARB_OLP_CONFIGr, rval64, 24709 ETHERTYPEf); 24710 return BCM_E_NONE; 24711 } 24712 return BCM_E_UNAVAIL; 24713 break; 24714 24715 24716 case bcmSwitchOamOlpChipTpid: 24717 if (soc_feature(unit, soc_feature_olp)) { 24718 COMPILER_64_ZERO(rval64); 24719 SOC_IF_ERROR_RETURN(READ_IARB_OLP_CONFIG_1r(unit, &rval64)); 24720 *arg = soc_reg64_field32_get(unit, IARB_OLP_CONFIG_1r, rval64, 24721 VLAN_TPIDf); 24722 return BCM_E_NONE; 24723 } 24724 return BCM_E_UNAVAIL; 24725 break; 24726 24727 24728 case bcmSwitchOamOlpChipVlan: 24729 if (soc_feature(unit, soc_feature_olp)) { 24730 rval = 0; 24731 SOC_IF_ERROR_RETURN(READ_EGR_OLP_VLANr(unit, &rval)); 24732 *arg = soc_reg_field_get(unit, EGR_OLP_VLANr, rval, VLAN_TAGf); 24733 return BCM_E_NONE; 24734 } 24735 return BCM_E_UNAVAIL; 24736 break; 24737 24738 case bcmSwitchOamOlpStationMacNonOui: 24739 case bcmSwitchOamOlpStationMacOui: 24740 if (soc_feature(unit, soc_feature_olp)) { 24741 if (_BCM_SWITCH_OLP_APIV(unit) != _BCM_SWITCH_OLP_L2_STATION_API) { 24742 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_TRUE_API); 24743 return _bcm_switch_xgs_mac_get(unit, type, arg); 24744 } 24745 } 24746 return BCM_E_UNAVAIL; 24747 break; 24748 #endif /* BCM_OLP_SUPPORT */ 24749 #if defined(BCM_SABER2_SUPPORT) 24750 case bcmSwitchOamStackingSupport: 24751 if (SOC_IS_SABER2(unit)) { 24752 BCM_IF_ERROR_RETURN( 24753 READ_EGR_HG_PPD0_RX_VC_LABEL_OVERLAY_CONTROLr(unit, 24754 &rval)); 24755 *arg = soc_reg_field_get(unit, 24756 EGR_HG_PPD0_RX_VC_LABEL_OVERLAY_CONTROLr, 24757 rval, VC_LABEL_OVERLAY_TYPEf); 24758 return BCM_E_NONE; 24759 } 24760 return BCM_E_UNAVAIL; 24761 break; 24762 #endif /* BCM_SABER2_SUPPORT */ 24763 case bcmSwitchFieldStageEgressToCpu: 24764 if (soc_feature(unit, soc_feature_field_egress_tocpu)) { 24765 rval = 0; 24766 SOC_IF_ERROR_RETURN(READ_EGR_CPU_CONTROLr(unit, &rval)); 24767 *arg = soc_reg_field_get(unit, EGR_CPU_CONTROLr, 24768 rval, EFP_TOCPUf); 24769 return BCM_E_NONE; 24770 } 24771 return BCM_E_UNAVAIL; 24772 break; 24773 24774 case bcmSwitchSystemReservedVlan: 24775 return _bcm_esw_vlan_system_reserved_get(unit, arg); 24776 24777 #if defined(BCM_KATANA2_SUPPORT) 24778 case bcmSwitchHashOamEgress: 24779 case bcmSwitchHashOamEgressDual: 24780 if (SOC_IS_KATANA2(unit)) { 24781 return _bcm_fb_er_hashselect_get(unit, type, arg); 24782 } 24783 return BCM_E_UNAVAIL; 24784 break; 24785 #endif /* BCM_KATANA2_SUPPORT */ 24786 #if defined (BCM_SABER2_SUPPORT) 24787 case bcmSwitchHashOam: 24788 case bcmSwitchHashOamDual: 24789 if (SOC_IS_SABER2(unit)) { 24790 return _bcm_fb_er_hashselect_get(unit, type, arg); 24791 } 24792 return BCM_E_UNAVAIL; 24793 break; 24794 #endif /* BCM_SABER2_SUPPORT */ 24795 case bcmSwitchHashOamLeastFull: 24796 case bcmSwitchHashDualMoveDepthOam: 24797 /* Not supported for now */ 24798 return BCM_E_UNAVAIL; 24799 break; 24800 #if defined(BCM_ENDURO_SUPPORT) 24801 case bcmSwitchWredForAllPkts: 24802 if(SOC_IS_ENDURO(unit)) { 24803 rval = 0; 24804 SOC_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 24805 *arg = soc_reg_field_get(unit, ING_MISC_CONFIGr, 24806 rval, TREAT_ALL_PKTS_AS_TCPf); 24807 return BCM_E_NONE; 24808 } 24809 return BCM_E_UNAVAIL; 24810 break; 24811 #endif /* BCM_ENDURO_SUPPORT */ 24812 #if defined(BCM_TRIDENT2_SUPPORT) 24813 24814 case bcmSwitchFcoeNpvModeEnable: 24815 if (soc_feature(unit, soc_feature_fcoe)) { 24816 uint32 rval; 24817 24818 #ifdef BCM_TRIDENT3_SUPPORT 24819 if (SOC_IS_TRIDENT3X(unit)) { 24820 int port; 24821 PBMP_E_ITER(unit, port) { 24822 return(_bcm_esw_port_tab_get(unit, port, FCOE_NPV_MODEf, arg)); 24823 } 24824 } else 24825 #endif 24826 { 24827 SOC_IF_ERROR_RETURN(READ_FCOE_ING_CONTROLr(unit, &rval)); 24828 *arg = soc_reg_field_get(unit, FCOE_ING_CONTROLr, rval, 24829 FCOE_NPV_MODEf); 24830 } 24831 return BCM_E_NONE; 24832 } 24833 break; 24834 24835 case bcmSwitchFcoeDomainRoutePrefixLength: 24836 if (soc_feature(unit, soc_feature_fcoe)) { 24837 uint32 rval; 24838 24839 SOC_IF_ERROR_RETURN(READ_FCOE_ING_CONTROLr(unit, &rval)); 24840 *arg = soc_reg_field_get(unit, FCOE_ING_CONTROLr, rval, 24841 FCOE_DOMAIN_ROUTE_PREFIXf); 24842 return BCM_E_NONE; 24843 } 24844 break; 24845 24846 case bcmSwitchFcoeCutThroughEnable: 24847 if (soc_feature(unit, soc_feature_fcoe)) { 24848 uint32 rval; 24849 24850 SOC_IF_ERROR_RETURN(READ_FCOE_ING_CONTROLr(unit, &rval)); 24851 *arg = soc_reg_field_get(unit, FCOE_ING_CONTROLr, rval, 24852 FCOE_CUT_THROUGH_ENABLEf); 24853 return BCM_E_NONE; 24854 } 24855 break; 24856 24857 case bcmSwitchFcoeSourceBindCheckAction: 24858 if (soc_feature(unit, soc_feature_fcoe)) { 24859 uint32 rval; 24860 24861 SOC_IF_ERROR_RETURN(READ_FCOE_ING_CONTROLr(unit, &rval)); 24862 *arg = soc_reg_field_get(unit, FCOE_ING_CONTROLr, rval, 24863 FCOE_SRC_BIND_CHECK_ACTIONf); 24864 return BCM_E_NONE; 24865 } 24866 break; 24867 24868 case bcmSwitchFcoeSourceFpmaPrefixCheckAction: 24869 if (soc_feature(unit, soc_feature_fcoe)) { 24870 uint32 rval; 24871 24872 SOC_IF_ERROR_RETURN(READ_FCOE_ING_CONTROLr(unit, &rval)); 24873 *arg = soc_reg_field_get(unit, FCOE_ING_CONTROLr, rval, 24874 FCOE_SRC_FPMA_PREFIX_CHECK_ACTIONf); 24875 return BCM_E_NONE; 24876 } 24877 break; 24878 24879 case bcmSwitchFcoeVftHopCountExpiryToCpu: 24880 if (soc_feature(unit, soc_feature_fcoe)) { 24881 #ifdef BCM_TRIDENT3_SUPPORT 24882 if (SOC_IS_TRIDENT3X(unit)) { 24883 return BCM_E_UNAVAIL; 24884 } else 24885 #endif /* BCM_TRIDENT3_SUPPORT */ 24886 { 24887 uint32 rval; 24888 24889 SOC_IF_ERROR_RETURN(READ_CPU_CONTROL_0r(unit, &rval)); 24890 *arg = soc_reg_field_get(unit, CPU_CONTROL_0r, rval, 24891 FCOE_VFT_HOPCOUNT_TOCPUf); 24892 } 24893 return BCM_E_NONE; 24894 } 24895 break; 24896 24897 case bcmSwitchFcoeVftHopCountExpiryAction: 24898 if (soc_feature(unit, soc_feature_fcoe)) { 24899 #ifdef BCM_TRIDENT3_SUPPORT 24900 if (SOC_IS_TRIDENT3X(unit)) { 24901 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1_64r(unit, &rval64)); 24902 *arg = soc_reg64_field32_get(unit, EGR_CONFIG_1_64r, rval64, 24903 FCOE_VFT_HOPCOUNT_EXPIRE_CONTROLf); 24904 return BCM_E_NONE; 24905 } else 24906 #endif 24907 { 24908 egr_fcoe_control_1_entry_t egr_fcoe_control; 24909 24910 SOC_IF_ERROR_RETURN( 24911 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 24912 0, &egr_fcoe_control)); 24913 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 24914 &egr_fcoe_control, 24915 FCOE_VFT_HOPCOUNT_EXPIRE_CONTROLf); 24916 } 24917 return BCM_E_NONE; 24918 } 24919 break; 24920 24921 case bcmSwitchFcoeFcEofT1Value: 24922 if (soc_feature(unit, soc_feature_fcoe)) { 24923 #ifdef BCM_TRIDENT3_SUPPORT 24924 if (SOC_IS_TRIDENT3X(unit)) { 24925 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 24926 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 24927 FCOE_FC_EOF_T_1f); 24928 } else 24929 #endif 24930 { 24931 egr_fcoe_control_1_entry_t egr_fcoe_control; 24932 24933 SOC_IF_ERROR_RETURN( 24934 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 24935 0, &egr_fcoe_control)); 24936 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 24937 &egr_fcoe_control, FCOE_FC_EOF_T_1f); 24938 } 24939 return BCM_E_NONE; 24940 } 24941 break; 24942 24943 case bcmSwitchFcoeFcEofT2Value: 24944 if (soc_feature(unit, soc_feature_fcoe)) { 24945 #ifdef BCM_TRIDENT3_SUPPORT 24946 if (SOC_IS_TRIDENT3X(unit)) { 24947 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 24948 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 24949 FCOE_FC_EOF_T_2f); 24950 } else 24951 #endif 24952 { 24953 egr_fcoe_control_1_entry_t egr_fcoe_control; 24954 24955 SOC_IF_ERROR_RETURN( 24956 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 24957 0, &egr_fcoe_control)); 24958 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 24959 &egr_fcoe_control, FCOE_FC_EOF_T_2f); 24960 } 24961 return BCM_E_NONE; 24962 } 24963 break; 24964 24965 case bcmSwitchFcoeFcEofA1Value: 24966 if (soc_feature(unit, soc_feature_fcoe)) { 24967 #ifdef BCM_TRIDENT3_SUPPORT 24968 if (SOC_IS_TRIDENT3X(unit)) { 24969 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 24970 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 24971 FCOE_FC_EOF_A_1f); 24972 } else 24973 #endif 24974 { 24975 egr_fcoe_control_1_entry_t egr_fcoe_control; 24976 24977 SOC_IF_ERROR_RETURN( 24978 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 24979 0, &egr_fcoe_control)); 24980 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 24981 &egr_fcoe_control, FCOE_FC_EOF_A_1f); 24982 } 24983 return BCM_E_NONE; 24984 } 24985 break; 24986 24987 case bcmSwitchFcoeFcEofA2Value: 24988 if (soc_feature(unit, soc_feature_fcoe)) { 24989 #ifdef BCM_TRIDENT3_SUPPORT 24990 if (SOC_IS_TRIDENT3X(unit)) { 24991 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 24992 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 24993 FCOE_FC_EOF_A_2f); 24994 } else 24995 #endif 24996 { 24997 egr_fcoe_control_1_entry_t egr_fcoe_control; 24998 24999 SOC_IF_ERROR_RETURN( 25000 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 25001 0, &egr_fcoe_control)); 25002 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 25003 &egr_fcoe_control, FCOE_FC_EOF_A_2f); 25004 } 25005 return BCM_E_NONE; 25006 } 25007 break; 25008 25009 case bcmSwitchFcoeFcEofN1Value: 25010 if (soc_feature(unit, soc_feature_fcoe)) { 25011 #ifdef BCM_TRIDENT3_SUPPORT 25012 if (SOC_IS_TRIDENT3X(unit)) { 25013 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 25014 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 25015 FCOE_FC_EOF_N_1f); 25016 } else 25017 #endif 25018 { 25019 egr_fcoe_control_1_entry_t egr_fcoe_control; 25020 25021 SOC_IF_ERROR_RETURN( 25022 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 25023 0, &egr_fcoe_control)); 25024 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 25025 &egr_fcoe_control, FCOE_FC_EOF_N_1f); 25026 } 25027 return BCM_E_NONE; 25028 } 25029 break; 25030 25031 case bcmSwitchFcoeFcEofN2Value: 25032 if (soc_feature(unit, soc_feature_fcoe)) { 25033 #ifdef BCM_TRIDENT3_SUPPORT 25034 if (SOC_IS_TRIDENT3X(unit)) { 25035 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 25036 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 25037 FCOE_FC_EOF_N_2f); 25038 } else 25039 #endif 25040 { 25041 egr_fcoe_control_1_entry_t egr_fcoe_control; 25042 25043 SOC_IF_ERROR_RETURN( 25044 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 25045 0, &egr_fcoe_control)); 25046 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 25047 &egr_fcoe_control, FCOE_FC_EOF_N_2f); 25048 } 25049 return BCM_E_NONE; 25050 } 25051 break; 25052 25053 case bcmSwitchFcoeFcEofNI1Value: 25054 if (soc_feature(unit, soc_feature_fcoe)) { 25055 #ifdef BCM_TRIDENT3_SUPPORT 25056 if (SOC_IS_TRIDENT3X(unit)) { 25057 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 25058 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 25059 FCOE_FC_EOF_NI_1f); 25060 } else 25061 #endif 25062 { 25063 egr_fcoe_control_1_entry_t egr_fcoe_control; 25064 25065 SOC_IF_ERROR_RETURN( 25066 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 25067 0, &egr_fcoe_control)); 25068 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 25069 &egr_fcoe_control, FCOE_FC_EOF_NI_1f); 25070 } 25071 return BCM_E_NONE; 25072 } 25073 break; 25074 25075 case bcmSwitchFcoeFcEofNI2Value: 25076 if (soc_feature(unit, soc_feature_fcoe)) { 25077 #ifdef BCM_TRIDENT3_SUPPORT 25078 if (SOC_IS_TRIDENT3X(unit)) { 25079 SOC_IF_ERROR_RETURN(READ_EGR_FCOE_EOFr(unit, &rval64)); 25080 *arg = soc_reg64_field32_get(unit, EGR_FCOE_EOFr, rval64, 25081 FCOE_FC_EOF_NI_2f); 25082 } else 25083 #endif 25084 { 25085 egr_fcoe_control_1_entry_t egr_fcoe_control; 25086 25087 SOC_IF_ERROR_RETURN( 25088 READ_EGR_FCOE_CONTROL_1m(unit, MEM_BLOCK_ANY, 25089 0, &egr_fcoe_control)); 25090 *arg = soc_mem_field32_get(unit, EGR_FCOE_CONTROL_1m, 25091 &egr_fcoe_control, FCOE_FC_EOF_NI_2f); 25092 } 25093 return BCM_E_NONE; 25094 } 25095 break; 25096 25097 case bcmSwitchFcoeZoneCheckFailToCpu: 25098 if (soc_feature(unit, soc_feature_fcoe)) { 25099 uint32 rval; 25100 25101 SOC_IF_ERROR_RETURN(READ_CPU_CONTROL_Mr(unit, &rval)); 25102 *arg = soc_reg_field_get(unit, CPU_CONTROL_Mr, rval, 25103 FCOE_ZONE_CHECK_FAIL_COPY_TOCPUf); 25104 return BCM_E_NONE; 25105 } 25106 break; 25107 25108 case bcmSwitchFcoeZoneCheckMissDrop: 25109 if (soc_feature(unit, soc_feature_fcoe)) { 25110 uint32 rval; 25111 25112 SOC_IF_ERROR_RETURN(READ_ING_MISC_CONFIG2r(unit, &rval)); 25113 *arg = soc_reg_field_get(unit, ING_MISC_CONFIG2r, rval, 25114 FCOE_ZONE_CHECK_MISS_DROPf); 25115 return BCM_E_NONE; 25116 } 25117 break; 25118 case bcmSwitchHWL2Freeze: 25119 if (SOC_IS_TD2_TT2(unit)) { 25120 return soc_l2x_is_frozen(unit, SOC_L2X_FROZEN_WITHOUT_LOCK, arg); 25121 } 25122 break; 25123 #endif /* BCM_TRIDENT2_SUPPORT */ 25124 case bcmSwitchNetworkGroupDepth: 25125 if (soc_feature(unit, soc_feature_multiple_split_horizon_group)) { 25126 *arg = soc_mem_index_count(unit, ING_NETWORK_PRUNE_CONTROLm); 25127 return BCM_E_NONE; 25128 } 25129 break; 25130 case bcmSwitchUnknownSubportPktTagToCpu: 25131 if (soc_feature(unit, soc_feature_subtag_coe) || 25132 soc_feature(unit, soc_feature_hgproxy_subtag_coe)) { 25133 if (soc_reg_field_valid(unit, CPU_CONTROL_1r, 25134 UNKNOWN_SUBTENDING_PORT_TOCPUf)) { 25135 uint32 rval; 25136 SOC_IF_ERROR_RETURN(READ_CPU_CONTROL_1r(unit, &rval)); 25137 *arg = soc_reg_field_get(unit, CPU_CONTROL_1r, rval, 25138 UNKNOWN_SUBTENDING_PORT_TOCPUf); 25139 return BCM_E_NONE; 25140 } 25141 } 25142 break; 25143 25144 #ifdef BCM_TRIDENT_SUPPORT 25145 case bcmSwitchMirrorUnicastCosq: 25146 if (soc_feature(unit, soc_feature_mirror_cos)) { 25147 return _bcm_td_mirror_uc_cos_get(unit, arg); 25148 } 25149 break; 25150 25151 case bcmSwitchMirrorMulticastCosq: 25152 if (soc_feature(unit, soc_feature_mirror_cos)) { 25153 return _bcm_td_mirror_mc_cos_get(unit, arg); 25154 } 25155 break; 25156 25157 #ifdef BCM_TOMAHAWK3_SUPPORT 25158 case bcmSwitchMirrorCpuCosq: 25159 if (soc_feature(unit, soc_feature_mirror_cos)) { 25160 return _bcm_th3_mirror_cpu_cos_get(unit, arg); 25161 } 25162 break; 25163 #endif /* BCM_TOMAHAWK3_SUPPORT */ 25164 #endif 25165 25166 case bcmSwitchL3Max128BV6Entries: 25167 #ifdef INCLUDE_L3 25168 if (soc_feature(unit, soc_feature_l3) && 25169 soc_feature(unit, soc_feature_l3_shared_defip_table)) { 25170 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit) 25171 || SOC_IS_TRIDENT3X(unit)) { 25172 #ifdef BCM_TRX_SUPPORT 25173 if (EXT_TCAM_IS_L3_ENABLED(unit)) { 25174 return BCM_E_UNAVAIL; 25175 } 25176 #endif /* BCM_TRX_SUPPORT */ 25177 *arg = SOC_L3_DEFIP_MAX_128B_ENTRIES(unit); 25178 return BCM_E_NONE; 25179 } 25180 } 25181 #endif 25182 return BCM_E_UNAVAIL; 25183 25184 case bcmSwitchEEEQueueThresholdProfile0: 25185 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25186 uint32 rval; 25187 25188 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_0r(unit, &rval)); 25189 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_0r, rval, 25190 EEE_QUEUE_THRESHOLDf); 25191 return BCM_E_NONE; 25192 } 25193 break; 25194 case bcmSwitchEEEQueueThresholdProfile1: 25195 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25196 uint32 rval; 25197 25198 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_1r(unit, &rval)); 25199 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_1r, rval, 25200 EEE_QUEUE_THRESHOLDf); 25201 return BCM_E_NONE; 25202 } 25203 break; 25204 case bcmSwitchEEEQueueThresholdProfile2: 25205 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25206 uint32 rval; 25207 25208 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_2r(unit, &rval)); 25209 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_2r, rval, 25210 EEE_QUEUE_THRESHOLDf); 25211 return BCM_E_NONE; 25212 } 25213 break; 25214 case bcmSwitchEEEQueueThresholdProfile3: 25215 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25216 uint32 rval; 25217 25218 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_3r(unit, &rval)); 25219 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_3r, rval, 25220 EEE_QUEUE_THRESHOLDf); 25221 return BCM_E_NONE; 25222 } 25223 break; 25224 case bcmSwitchEEEPacketLatencyProfile0: 25225 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25226 uint32 rval; 25227 uint32 fval; 25228 25229 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_0r(unit, &rval)); 25230 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_0r, rval, 25231 EEE_MAX_PKT_LATENCYf); 25232 *arg = fval; 25233 return BCM_E_NONE; 25234 } 25235 break; 25236 case bcmSwitchEEEPacketLatencyProfile1: 25237 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25238 uint32 rval; 25239 uint32 fval; 25240 25241 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_1r(unit, &rval)); 25242 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_1r, rval, 25243 EEE_MAX_PKT_LATENCYf); 25244 *arg = fval; 25245 return BCM_E_NONE; 25246 } 25247 break; 25248 case bcmSwitchEEEPacketLatencyProfile2: 25249 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25250 uint32 rval; 25251 uint32 fval; 25252 25253 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_2r(unit, &rval)); 25254 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_2r, rval, 25255 EEE_MAX_PKT_LATENCYf); 25256 *arg = fval; 25257 return BCM_E_NONE; 25258 } 25259 break; 25260 case bcmSwitchEEEPacketLatencyProfile3: 25261 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25262 uint32 rval; 25263 uint32 fval; 25264 25265 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_3r(unit, &rval)); 25266 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_3r, rval, 25267 EEE_MAX_PKT_LATENCYf); 25268 *arg = fval; 25269 return BCM_E_NONE; 25270 } 25271 break; 25272 case bcmSwitchEEEGlobalCongestionThreshold: 25273 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 25274 uint32 rval; 25275 25276 SOC_IF_ERROR_RETURN(READ_EEE_GLOBAL_BUF_THRESHr(unit, &rval)); 25277 *arg = soc_reg_field_get(unit, EEE_GLOBAL_BUF_THRESHr, rval, 25278 EEE_GLOBAL_BUFFER_THREHSOLDf); 25279 return BCM_E_NONE; 25280 } 25281 break; 25282 #if defined(BCM_KATANA2_SUPPORT) 25283 case bcmSwitchUnknownVlanToCpu: 25284 case bcmSwitchStgInvalidToCpu: 25285 case bcmSwitchVlanTranslateEgressMissToCpu: 25286 case bcmSwitchTunnelErrToCpu: 25287 case bcmSwitchL3HeaderErrToCpu: 25288 case bcmSwitchL3PktErrToCpu: 25289 case bcmSwitchIpmcTtlErrToCpu: 25290 case bcmSwitchMtuFailureToCpu: 25291 case bcmSwitchHgHdrErrToCpu: 25292 case bcmSwitchSrcKnockoutToCpu: 25293 if (SOC_REG_IS_VALID(unit, EGR_CPU_CONTROLr)) { 25294 if (SOC_IS_KATANA2(unit)) { 25295 BCM_IF_ERROR_RETURN( 25296 _bcm_tr2_ep_redirect_action_get(unit, REG_PORT_ANY, type, arg)); 25297 } 25298 } 25299 break; 25300 #endif /* BCM_KATANA2_SUPPORT */ 25301 case bcmSwitchSymmetricHashControl: 25302 #if defined(BCM_TRIUMPH3_SUPPORT) 25303 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || 25304 SOC_IS_KATANA2(unit)) { 25305 return _bcm_tr3_symmetric_hash_control_get(unit, arg); 25306 } 25307 #endif /* BCM_TRIUMPH3_SUPPORT */ 25308 return BCM_E_UNAVAIL; 25309 break; 25310 25311 case bcmSwitchHigigCongestionClassEnable: 25312 #if defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 25313 #if defined(BCM_TOMAHAWK3_SUPPORT) 25314 if (SOC_IS_TOMAHAWK3(unit)) { 25315 return BCM_E_UNAVAIL; 25316 } else 25317 #endif 25318 if (soc_feature(unit, soc_feature_ecn_wred)) { 25319 COMPILER_64_ZERO(rval64); 25320 BCM_IF_ERROR_RETURN( 25321 READ_ING_CONFIG_64r(unit, &rval64)); 25322 *arg = soc_reg64_field32_get(unit, ING_CONFIG_64r, 25323 rval64, HIGIG2_ECN_IN_CC_ENABLEf); 25324 return BCM_E_NONE; 25325 } 25326 #endif 25327 return BCM_E_UNAVAIL; 25328 break; 25329 case bcmSwitchEcnNonIpResponsive: 25330 #if defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 25331 if (soc_feature(unit, soc_feature_ecn_wred)) { 25332 BCM_IF_ERROR_RETURN( 25333 READ_ECN_CONTROLr(unit, &rval)); 25334 *arg = soc_reg_field_get(unit, ECN_CONTROLr, 25335 rval, RESPONSIVE_DEFAULTf); 25336 return BCM_E_NONE; 25337 } 25338 #endif 25339 return BCM_E_UNAVAIL; 25340 break; 25341 case bcmSwitchEcnIpPayloadResponsive: 25342 #if defined(BCM_TOMAHAWK_SUPPORT) 25343 if (soc_feature(unit, soc_feature_ecn_wred)) { 25344 BCM_IF_ERROR_RETURN( 25345 READ_ECN_CONTROLr(unit, &rval)); 25346 *arg = soc_reg_field_get(unit, ECN_CONTROLr, 25347 rval, USE_PAYLOAD_L4_FOR_RESPONSIVEf); 25348 return BCM_E_NONE; 25349 } 25350 #endif 25351 return BCM_E_UNAVAIL; 25352 break; 25353 case bcmSwitchMplsNonIpPayloadDefaultEcn: 25354 #if defined(BCM_TOMAHAWK2_SUPPORT) 25355 if (soc_feature(unit, soc_feature_mpls_ecn) && 25356 !(soc_feature(unit, soc_feature_td3_style_mpls))) { 25357 BCM_IF_ERROR_RETURN( 25358 READ_ECN_CONTROLr(unit, &rval)); 25359 *arg = soc_reg_field_get(unit, ECN_CONTROLr, 25360 rval, NON_IP_DEFAULT_ECNf); 25361 return BCM_E_NONE; 25362 } 25363 #endif 25364 return BCM_E_UNAVAIL; 25365 break; 25366 case bcmSwitchEcnNonIpIntCongestionNotification: 25367 #if defined(BCM_GREYHOUND_SUPPORT) || defined(BCM_TOMAHAWK_SUPPORT) 25368 if (soc_feature(unit, soc_feature_ecn_wred)) { 25369 uint32 responsive; 25370 soc_field_t fld_idx; 25371 BCM_IF_ERROR_RETURN( 25372 READ_ECN_CONTROLr(unit, &rval)); 25373 responsive = soc_reg_field_get(unit, ECN_CONTROLr, 25374 rval, RESPONSIVE_DEFAULTf); 25375 if (responsive) { 25376 fld_idx = RESPONSIVE_DEFAULT_INT_CNf; 25377 } else { 25378 fld_idx = NON_RESPONSIVE_DEFAULT_INT_CNf; 25379 } 25380 *arg = soc_reg_field_get(unit, ECN_CONTROLr, 25381 rval, fld_idx); 25382 return BCM_E_NONE; 25383 } 25384 #endif 25385 return BCM_E_UNAVAIL; 25386 break; 25387 case bcmSwitchECMPHashBitCountSelect: 25388 #if (defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HELIX4_SUPPORT)) 25389 if (soc_feature(unit, soc_feature_ecmp_hash_bit_count_select)) { 25390 BCM_IF_ERROR_RETURN( 25391 READ_HASH_CONTROLr(unit, &rval)); 25392 *arg = soc_reg_field_get(unit, HASH_CONTROLr, 25393 rval, ECMP_HASH_FIELD_UPPER_BITS_COUNTf); 25394 return BCM_E_NONE; 25395 } 25396 #endif 25397 return BCM_E_UNAVAIL; 25398 break; 25399 25400 case bcmSwitchL3RouteCache: 25401 if (NUM_PIPE(unit) == 1) { 25402 /* For single-pipe devices, this feature doesn't take effect, so return 25403 * BCM_E_UNAVAIL, then the behavior is same as previous 25404 */ 25405 return BCM_E_UNAVAIL; 25406 } 25407 25408 /* Cache is always on when using alpm2 */ 25409 if (soc_feature(unit, soc_feature_alpm2) && 25410 soc_property_get(unit, spn_L3_ALPM_ENABLE, 0)) { 25411 *arg = 1; 25412 return BCM_E_NONE; 25413 } 25414 25415 #ifdef BCM_TRIDENT2_SUPPORT 25416 if (SOC_IS_TD2_TT2(unit)) { 25417 soc_mem_t mem; 25418 if (soc_feature(unit, soc_feature_alpm) && 25419 soc_property_get(unit, spn_L3_ALPM_ENABLE, 0)) { 25420 mem = L3_DEFIP_ALPM_IPV4m; 25421 } else { 25422 mem = L3_DEFIPm; 25423 if (SOC_MEM_IS_VALID(unit, L3_DEFIP_LEVEL1m)) { 25424 mem = L3_DEFIP_LEVEL1m; 25425 } 25426 } 25427 *arg = soc_mem_cache_get(unit, mem, MEM_BLOCK_ALL); 25428 return BCM_E_NONE; 25429 } 25430 #endif 25431 break; 25432 case bcmSwitchECMPLevel1RandomSeed: 25433 case bcmSwitchECMPLevel2RandomSeed: 25434 #ifdef BCM_TOMAHAWK_SUPPORT 25435 if (soc_feature(unit, soc_feature_ecmp_random)) { 25436 return _bcm_th_ecmp_random_hash_seed_get(unit, type, arg); 25437 } 25438 #endif 25439 return BCM_E_UNAVAIL; 25440 25441 case bcmSwitchSynchronousPortClockSourceValid: 25442 #if defined(BCM_KATANA2_SUPPORT) 25443 if (SOC_IS_KATANA2(unit)) { 25444 uint32 rval; 25445 SOC_IF_ERROR_RETURN(READ_TOP_L1_SYNCE_CLK_LINK_STATUS_2r(unit, &rval)); 25446 *arg = soc_reg_field_get(unit, TOP_L1_SYNCE_CLK_LINK_STATUS_2r, 25447 rval, L1_SYNCE_MUXED_CLK0_VALIDf); 25448 return BCM_E_NONE; 25449 } 25450 #endif 25451 return BCM_E_UNAVAIL; 25452 break; 25453 case bcmSwitchSynchronousPortClockSourceBkupValid: 25454 #if defined(BCM_KATANA2_SUPPORT) 25455 if (SOC_IS_KATANA2(unit)) { 25456 uint32 rval; 25457 SOC_IF_ERROR_RETURN(READ_TOP_L1_SYNCE_CLK_LINK_STATUS_2r(unit, &rval)); 25458 *arg = soc_reg_field_get(unit, TOP_L1_SYNCE_CLK_LINK_STATUS_2r, 25459 rval, L1_SYNCE_MUXED_CLK1_VALIDf); 25460 return BCM_E_NONE; 25461 } 25462 #endif 25463 break; 25464 25465 case bcmSwitchSubportCoEEtherType: 25466 case bcmSwitchSubportEgressTpid: 25467 #ifdef BCM_TOMAHAWK3_SUPPORT 25468 if (SOC_IS_TOMAHAWK3(unit)) { 25469 return BCM_E_UNAVAIL; 25470 } 25471 #endif 25472 #ifdef BCM_HGPROXY_COE_SUPPORT 25473 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 25474 SOC_REG_IS_VALID(unit, SUBPORT_TAG_TPIDr)) { /* TD3TBD */ 25475 return bcmi_xgs5_subport_coe_ether_type_size_get(unit, type, arg); 25476 } else { 25477 return BCM_E_UNAVAIL; 25478 } 25479 #endif 25480 25481 case bcmSwitchSubportEgressWideTpid: 25482 return BCM_E_UNAVAIL; 25483 25484 case bcmSwitchIpmcSameVlanPruningOverride: 25485 if (soc_feature(unit, soc_feature_same_vlan_pruning_override)) { 25486 BCM_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 25487 *arg = soc_reg_field_get(unit, EGR_CONFIG_1r, 25488 rval, ALLOW_L2_SWITCH_IN_IPMC_IND_MODEf); 25489 return BCM_E_NONE; 25490 } 25491 25492 return BCM_E_UNAVAIL; 25493 break; 25494 case bcmSwitchMimBvidInsertionControl: 25495 #ifdef BCM_TRIDENT2PLUS_SUPPORT 25496 if (soc_feature(unit, soc_feature_mim_bvid_insertion_control)) { 25497 uint32 rval; 25498 SOC_IF_ERROR_RETURN(READ_EGR_CONFIGr(unit, &rval)); 25499 *arg = soc_reg_field_get(unit, EGR_CONFIGr, rval, 25500 HONOR_NEXTHOP_BVID_VALIDf); 25501 return BCM_E_NONE; 25502 } 25503 #endif 25504 return BCM_E_UNAVAIL; 25505 break; 25506 #if defined(BCM_ESW_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) && \ 25507 (defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT)) 25508 case bcmSwitchL2CpuDeleteEvent: 25509 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit)) { 25510 #if defined(BCM_TOMAHAWK3_SUPPORT) 25511 if (SOC_IS_TOMAHAWK3(unit)) { 25512 /* Mod Fifo not implemented in TH3 h/w */ 25513 return BCM_E_UNAVAIL; 25514 } 25515 #endif 25516 field = L2_DELETEf; 25517 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25518 } else if (soc_feature(unit, soc_feature_cmicm)) { 25519 field = L2_MOD_FIFO_ENABLE_L2_DELETEf; 25520 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 25521 SOC_IS_GREYHOUND(unit) || SOC_IS_KATANA2(unit)) { 25522 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25523 } 25524 } else if (soc_feature(unit, soc_feature_cmicx)) { 25525 field = L2_DELETEf; 25526 } 25527 return soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25528 case bcmSwitchL2LearnEvent: 25529 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit)) { 25530 #if defined(BCM_TOMAHAWK3_SUPPORT) 25531 if (SOC_IS_TOMAHAWK3(unit)) { 25532 /* Mod Fifo not implemented in TH3 h/w */ 25533 return BCM_E_UNAVAIL; 25534 } 25535 #endif 25536 field = L2_LEARNf; 25537 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25538 } else if (soc_feature(unit, soc_feature_cmicm)) { 25539 field = L2_MOD_FIFO_ENABLE_LEARNf; 25540 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 25541 SOC_IS_GREYHOUND(unit)) { 25542 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25543 } 25544 } else if (soc_feature(unit, soc_feature_cmicx)) { 25545 field = L2_LEARNf; 25546 } 25547 return soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25548 case bcmSwitchL2CpuAddEvent: 25549 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit)) { 25550 #if defined(BCM_TOMAHAWK3_SUPPORT) 25551 if (SOC_IS_TOMAHAWK3(unit)) { 25552 /* Mod Fifo not implemented in TH3 h/w */ 25553 return BCM_E_UNAVAIL; 25554 } 25555 #endif 25556 field = L2_INSERTf; 25557 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25558 } else if (soc_feature(unit, soc_feature_cmicm)) { 25559 field = L2_MOD_FIFO_ENABLE_L2_INSERTf; 25560 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 25561 SOC_IS_GREYHOUND(unit) || SOC_IS_KATANA2(unit)) { 25562 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25563 } 25564 } else if (soc_feature(unit, soc_feature_cmicx)) { 25565 field = L2_INSERTf; 25566 } 25567 return soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25568 case bcmSwitchL2AgingEvent: 25569 if (SOC_IS_TOMAHAWKX(unit)) { 25570 #if defined(BCM_TOMAHAWK3_SUPPORT) 25571 if (SOC_IS_TOMAHAWK3(unit)) { 25572 /* Mod Fifo not implemented in TH3 h/w */ 25573 return BCM_E_UNAVAIL; 25574 } 25575 #endif 25576 field = L2_AGEf; 25577 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25578 } else if (soc_feature(unit, soc_feature_cmicm)) { 25579 field = L2_MOD_FIFO_ENABLE_AGEf; 25580 if (SOC_IS_HURRICANE2(unit) || SOC_IS_HURRICANE3(unit) || 25581 SOC_IS_GREYHOUND(unit)) { 25582 return _soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25583 } 25584 } else if (SOC_IS_TRIUMPH3(unit) || soc_feature(unit, soc_feature_cmicx)) { 25585 return BCM_E_UNAVAIL; 25586 } 25587 return soc_l2mod_sbus_fifo_field_get(unit, field, arg); 25588 #else 25589 case bcmSwitchL2CpuDeleteEvent: 25590 case bcmSwitchL2LearnEvent: 25591 case bcmSwitchL2CpuAddEvent: 25592 case bcmSwitchL2AgingEvent: 25593 return BCM_E_UNAVAIL; 25594 #endif 25595 case bcmSwitchUdfHashEnable: 25596 #if defined(BCM_TRIDENT2_SUPPORT) 25597 if (soc_feature(unit, soc_feature_udf_hashing)) { 25598 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 25599 if (SOC_IS_TOMAHAWK2(unit) || SOC_IS_TOMAHAWK3(unit)) { 25600 return _bcm_th2_switch_udf_hash_get(unit, arg); 25601 } else 25602 #endif 25603 { 25604 return _bcm_td2_switch_udf_hash_get(unit, arg); 25605 } 25606 } 25607 #endif 25608 return BCM_E_UNAVAIL; 25609 case bcmSwitchOlpMatchRule: 25610 #if defined BCM_TRIDENT2PLUS_SUPPORT 25611 if (SOC_IS_TRIDENT2PLUS(unit)) { 25612 return _bcm_esw_rx_olp_match_rule_get (unit, arg); 25613 } 25614 #endif 25615 return BCM_E_UNAVAIL; 25616 case bcmSwitchNonUcVlanShapingEnable: 25617 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 25618 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || SOC_IS_TRIDENT(unit)){ 25619 if (!SOC_REG_IS_VALID(unit, ING_MISC_CONFIGr)) { 25620 return BCM_E_UNAVAIL; 25621 } 25622 if (!soc_reg_field_valid(unit, ING_MISC_CONFIGr, NONUC_VLAN_SHAPING_ENABLEf)) { 25623 return SOC_E_UNAVAIL; 25624 } 25625 BCM_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 25626 *arg = soc_reg_field_get(unit, ING_MISC_CONFIGr, 25627 rval, NONUC_VLAN_SHAPING_ENABLEf); 25628 return BCM_E_NONE; 25629 } 25630 #endif 25631 #if defined(BCM_TRIDENT2_SUPPORT) 25632 if (SOC_IS_TRIDENT2(unit) || SOC_IS_TRIDENT2PLUS(unit)) { 25633 if (!SOC_REG_IS_VALID(unit, ING_MISC_CONFIGr)) { 25634 return BCM_E_UNAVAIL; 25635 } 25636 BCM_IF_ERROR_RETURN(READ_ING_MISC_CONFIGr(unit, &rval)); 25637 *arg = soc_reg_field_get(unit, ING_MISC_CONFIGr, 25638 rval, NONUC_SERVICE_QUEUING_ENABLEf); 25639 return BCM_E_NONE; 25640 } 25641 #endif 25642 return BCM_E_UNAVAIL; 25643 case bcmSwitchRangeCheckersAPIType: 25644 #if defined BCM_TOMAHAWK_SUPPORT 25645 if (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 25646 return bcmi_xgs5_range_RangeCheckersAPIType_get(unit, arg); 25647 } 25648 #endif 25649 return BCM_E_UNAVAIL; 25650 break; 25651 case bcmSwitchCustomHeaderEncapPriorityOffset: 25652 #ifdef BCM_HURRICANE3_SUPPORT 25653 if (soc_feature(unit, soc_feature_custom_header)) { 25654 uint32 rval; 25655 SOC_IF_ERROR_RETURN 25656 (READ_CUSTOM_PACKET_HEADER_OVERRIDEr(unit, &rval)); 25657 25658 /* The offset is 4-bit aligned */ 25659 *arg = soc_reg_field_get(unit, CUSTOM_PACKET_HEADER_OVERRIDEr, rval, 25660 OFFSETf) * 4; 25661 25662 return BCM_E_NONE; 25663 } 25664 #endif 25665 return BCM_E_UNAVAIL; 25666 case bcmSwitchIngCapwapEnable: 25667 #if defined BCM_HURRICANE3_SUPPORT 25668 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 25669 BCM_IF_ERROR_RETURN( 25670 READ_CAPWAP_ENABLEr(unit, &rval)); 25671 *arg = soc_reg_field_get(unit, CAPWAP_ENABLEr, 25672 rval, ENABLEf); 25673 return BCM_E_NONE; 25674 } 25675 #endif 25676 return BCM_E_UNAVAIL; 25677 case bcmSwitchCapwapDataUdpDstPort: 25678 #if defined BCM_HURRICANE3_SUPPORT 25679 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 25680 BCM_IF_ERROR_RETURN( 25681 READ_CAPWAP_ENABLEr(unit, &rval)); 25682 *arg = soc_reg_field_get(unit, CAPWAP_ENABLEr, 25683 rval, UDP_PORT_NUMf); 25684 return BCM_E_NONE; 25685 } 25686 #endif 25687 return BCM_E_UNAVAIL; 25688 case bcmSwitchCountCapwapPayloadBytesOnly: 25689 #if defined BCM_HURRICANE3_SUPPORT 25690 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 25691 BCM_IF_ERROR_RETURN( 25692 READ_CAPWAP_ENABLEr(unit, &rval)); 25693 *arg = soc_reg_field_get(unit, CAPWAP_ENABLEr, 25694 rval, COUNT_PAYLOAD_BYTESf); 25695 return BCM_E_NONE; 25696 } 25697 #endif 25698 return BCM_E_UNAVAIL; 25699 #ifdef BCM_TRIDENT_SUPPORT 25700 case bcmSwitchEcmpGroupMemberMode: 25701 if (SOC_IS_TRIDENT(unit) && 25702 soc_feature(unit, soc_feature_l3_ecmp_1k_groups)) { 25703 uint32 ing_config_2, ecmp_hash_16bits; 25704 25705 SOC_IF_ERROR_RETURN 25706 (READ_ING_CONFIG_2r(unit, &ing_config_2)); 25707 ecmp_hash_16bits = 25708 soc_reg_field_get(unit, ING_CONFIG_2r, ing_config_2, 25709 ECMP_HASH_16BITSf); 25710 25711 if (ecmp_hash_16bits == 1) { 25712 *arg = BCM_SWITCH_ECMP_GROUP_MEMBER_MODE_1K; 25713 } else { 25714 *arg = BCM_SWITCH_ECMP_GROUP_MEMBER_MODE_256; 25715 } 25716 25717 return BCM_E_NONE; 25718 } else { 25719 return BCM_E_UNAVAIL; 25720 } 25721 break; 25722 #endif 25723 25724 case bcmSwitchPFCDeadlockDetectionTimeInterval: 25725 case bcmSwitchPFCDeadlockRecoveryAction: 25726 if (soc_feature(unit, soc_feature_pfc_deadlock)) { 25727 #ifdef BCM_TOMAHAWK3_SUPPORT 25728 if(SOC_IS_TOMAHAWK3(unit)) { 25729 return _bcm_th3_pfc_switch_control_get(unit, type, arg); 25730 } 25731 #endif 25732 return _bcm_pfc_deadlock_control_get(unit, type, arg); 25733 } 25734 return BCM_E_UNAVAIL; 25735 break; 25736 25737 case bcmSwitchMirrorPsampFormat2Epoch: 25738 #ifdef BCM_TOMAHAWK3_SUPPORT 25739 if (SOC_IS_TOMAHAWK3(unit)) { 25740 uint32 val; 25741 SOC_IF_ERROR_RETURN(READ_EGR_MIRROR_PSAMP_FORMAT_2_MONITORr(unit, 25742 &val)); 25743 *arg = soc_reg_field_get(unit, EGR_MIRROR_PSAMP_FORMAT_2_MONITORr, 25744 val, EPOCHf); 25745 return BCM_E_NONE; 25746 } 25747 #endif 25748 return BCM_E_UNAVAIL; 25749 break; 25750 25751 case bcmSwitchDlbMonitorIngressRandomSeed: 25752 #ifdef BCM_TOMAHAWK3_SUPPORT 25753 if(SOC_IS_TOMAHAWK3(unit)) { 25754 uint32 random_seed; 25755 SOC_IF_ERROR_RETURN 25756 (READ_DLB_ECMP_MONITOR_CONTROLr(unit, &random_seed)); 25757 *arg = soc_reg_field_get(unit, DLB_ECMP_MONITOR_CONTROLr, 25758 random_seed, SEEDf); 25759 return BCM_E_NONE; 25760 } 25761 #endif 25762 return BCM_E_UNAVAIL; 25763 break; 25764 #ifdef BCM_TOMAHAWK_SUPPORT 25765 case bcmSwitchSampleFlexRandomSeed: 25766 if(soc_feature(unit, soc_feature_sflow_flex)) { 25767 uint32 random_seed; 25768 SOC_IF_ERROR_RETURN 25769 (READ_SFLOW_ING_FLEX_RAND_SEEDr(unit, &random_seed)); 25770 *arg = soc_reg_field_get(unit, SFLOW_ING_FLEX_RAND_SEEDr, 25771 random_seed, SEEDf); 25772 return BCM_E_NONE; 25773 } else { 25774 return BCM_E_UNAVAIL; 25775 } 25776 break; 25777 case bcmSwitchHashSetTflowMode: 25778 if (soc_feature(unit, soc_feature_th_tflow)) { 25779 *arg = _bcm_switch_tflow_mode_info[unit].enabled; 25780 return BCM_E_NONE; 25781 } else { 25782 return BCM_E_UNAVAIL; 25783 } 25784 break; 25785 #endif /* BCM_TOMAHAWK_SUPPORT */ 25786 case bcmSwitchFlexIP6ExtHdr: 25787 if (soc_feature(unit, soc_feature_l3_ip6) && 25788 SOC_REG_IS_VALID(unit, FLEXIBLE_IPV6_EXT_HDRr)) { 25789 uint32 protocol_id; 25790 SOC_IF_ERROR_RETURN 25791 (READ_FLEXIBLE_IPV6_EXT_HDRr(unit, &protocol_id)); 25792 *arg = soc_reg_field_get(unit, FLEXIBLE_IPV6_EXT_HDRr, 25793 protocol_id, PROTOCOL_IDf); 25794 return BCM_E_NONE; 25795 } else { 25796 return BCM_E_UNAVAIL; 25797 } 25798 break; 25799 case bcmSwitchFlexIP6ExtHdrEgress: 25800 if (soc_feature(unit, soc_feature_l3_ip6) && 25801 SOC_REG_IS_VALID(unit, EGR_FLEXIBLE_IPV6_EXT_HDRr)) { 25802 uint32 protocol_id; 25803 SOC_IF_ERROR_RETURN 25804 (READ_EGR_FLEXIBLE_IPV6_EXT_HDRr(unit, &protocol_id)); 25805 *arg = soc_reg_field_get(unit, EGR_FLEXIBLE_IPV6_EXT_HDRr, 25806 protocol_id, PROTOCOL_IDf); 25807 return BCM_E_NONE; 25808 } 25809 break; 25810 #ifdef BCM_EP_REDIRECT_VERSION_2 25811 case bcmSwitchRedirectBufferThresholdPriorityLow: 25812 case bcmSwitchRedirectBufferThresholdPriorityMedium: 25813 case bcmSwitchRedirectBufferThresholdPriorityHigh: 25814 if(soc_feature(unit, soc_feature_ep_redirect_v2)) { 25815 25816 soc_field_t reg = INVALIDf; 25817 25818 /* Set the register to program */ 25819 if(type == bcmSwitchRedirectBufferThresholdPriorityLow) { 25820 reg = RDB_THRESHOLD_LOr; 25821 } else if(type == bcmSwitchRedirectBufferThresholdPriorityMedium) { 25822 reg = RDB_THRESHOLD_MEDr; 25823 } else { 25824 reg = RDB_THRESHOLD_HIr; 25825 } 25826 25827 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, 25828 REG_PORT_ANY, 0, (uint32*)arg)); 25829 *arg = soc_reg_field_get(unit, reg, *arg, LIMITf); 25830 25831 /* Convert cells to bytes, each cell is 108 bytes long */ 25832 *arg *= 108; 25833 25834 return BCM_E_NONE; 25835 25836 } else { 25837 return BCM_E_UNAVAIL; 25838 } 25839 break; 25840 #endif 25841 #if defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 25842 case bcmSwitchL3ClassIdForL2Enable: 25843 if (soc_feature(unit, soc_feature_l2_use_l3_class_id)) { 25844 COMPILER_64_ZERO(rval64); 25845 BCM_IF_ERROR_RETURN( 25846 READ_ING_CONFIG_64r(unit, &rval64)); 25847 *arg = soc_reg64_field32_get(unit, ING_CONFIG_64r, rval64, 25848 ENABLE_L3_CLASSID_FOR_L2PKTSf); 25849 return BCM_E_NONE; 25850 } else { 25851 return BCM_E_UNAVAIL; 25852 } 25853 break; 25854 #endif 25855 #if defined(BCM_TOMAHAWK_SUPPORT) 25856 /* Tomahawk SKUs support multimode cut-thru. Using global switch to apply same cut-through */ 25857 /* settings to all ports (e.g Trident2) has been discontinued. In Tomahawk, the cut-through */ 25858 /* configuration (to be determined based on speed limits) has to be per port and is */ 25859 /* supported only through bcm_switch_control_port_set()/get() interfaces. */ 25860 case bcmSwitchAlternateStoreForward: 25861 if (soc_feature(unit, soc_feature_asf_multimode)) { 25862 return BCM_E_UNAVAIL; 25863 } 25864 break; 25865 #endif 25866 case bcmSwitchDowngrade: 25867 #ifdef BCM_WARM_BOOT_SUPPORT 25868 *arg = SOC_CONTROL(unit)->downgrade_version; 25869 return BCM_E_NONE; 25870 #else 25871 return SOC_E_UNAVAIL; 25872 #endif 25873 break; 25874 #ifdef BCM_TRIDENT2_SUPPORT 25875 case bcmSwitchGtpDetectEnable: 25876 if (SOC_REG_IS_VALID(unit, ING_GTP_CONTROLr)) { 25877 SOC_IF_ERROR_RETURN( 25878 READ_ING_GTP_CONTROLr(unit, &rval)); 25879 *arg = soc_reg_field_get(unit, ING_GTP_CONTROLr, 25880 rval, GTP_ENABLEf); 25881 return BCM_E_NONE; 25882 } else { 25883 return BCM_E_UNAVAIL; 25884 } 25885 break; 25886 case bcmSwitchGtpHdrFirstByte: 25887 if (SOC_REG_IS_VALID(unit, ING_GTP_CONTROLr)) { 25888 SOC_IF_ERROR_RETURN( 25889 READ_ING_GTP_CONTROLr(unit, &rval)); 25890 *arg = soc_reg_field_get(unit, ING_GTP_CONTROLr, 25891 rval, GTP_HDR_FIRST_BYTEf); 25892 return BCM_E_NONE; 25893 } else { 25894 return BCM_E_UNAVAIL; 25895 } 25896 break; 25897 case bcmSwitchGtpHdrFirstByteMask: 25898 if (SOC_REG_IS_VALID(unit, ING_GTP_CONTROLr)) { 25899 SOC_IF_ERROR_RETURN( 25900 READ_ING_GTP_CONTROLr(unit, &rval)); 25901 *arg = soc_reg_field_get(unit, ING_GTP_CONTROLr, 25902 rval, GTP_HDR_FIRST_BYTE_MASKf); 25903 return BCM_E_NONE; 25904 } else { 25905 return BCM_E_UNAVAIL; 25906 } 25907 break; 25908 case bcmSwitchHashGtpTeidEnable0: 25909 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2r) && 25910 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2r, ENABLE_GTP_Af)) { 25911 SOC_IF_ERROR_RETURN( 25912 READ_RTAG7_HASH_CONTROL_2r(unit, &rval)); 25913 *arg = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_2r, 25914 rval, ENABLE_GTP_Af); 25915 return BCM_E_NONE; 25916 } else if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2_64r) && 25917 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2_64r, ENABLE_GTP_Af)) { 25918 uint64 rtag7_hash_control_2_64; 25919 SOC_IF_ERROR_RETURN( 25920 READ_RTAG7_HASH_CONTROL_2_64r(unit, &rtag7_hash_control_2_64)); 25921 *arg = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_2_64r, 25922 rtag7_hash_control_2_64, ENABLE_GTP_Af); 25923 return BCM_E_NONE; 25924 } else { 25925 return BCM_E_UNAVAIL; 25926 } 25927 break; 25928 case bcmSwitchHashGtpTeidEnable1: 25929 if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2r) && 25930 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2r, ENABLE_GTP_Bf)) { 25931 SOC_IF_ERROR_RETURN( 25932 READ_RTAG7_HASH_CONTROL_2r(unit, &rval)); 25933 *arg = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_2r, 25934 rval, ENABLE_GTP_Bf); 25935 return BCM_E_NONE; 25936 } else if (SOC_REG_IS_VALID(unit, RTAG7_HASH_CONTROL_2_64r) && 25937 SOC_REG_FIELD_VALID(unit, RTAG7_HASH_CONTROL_2_64r, ENABLE_GTP_Bf)) { 25938 uint64 rtag7_hash_control_2_64; 25939 SOC_IF_ERROR_RETURN( 25940 READ_RTAG7_HASH_CONTROL_2_64r(unit, &rtag7_hash_control_2_64)); 25941 *arg = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROL_2_64r, 25942 rtag7_hash_control_2_64, ENABLE_GTP_Bf); 25943 25944 return BCM_E_NONE; 25945 } else { 25946 return BCM_E_UNAVAIL; 25947 } 25948 break; 25949 #endif /* BCM_TRIDENT2_SUPPORT */ 25950 #ifdef BCM_TRIDENT2_SUPPORT 25951 case bcmSwitchEccSingleBitErrorEvent: 25952 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TITAN2X(unit)) { 25953 return soc_td2x_ser_single_bit_error_enable_get(unit, arg); 25954 } 25955 #if defined(BCM_TOMAHAWK_SUPPORT) 25956 else if (SOC_IS_TOMAHAWKX(unit)) { 25957 return soc_th_ser_single_bit_error_enable_get(unit, arg); 25958 } 25959 #endif 25960 break; 25961 #endif /* BCM_TRIDENT2_SUPPORT */ 25962 25963 case bcmSwitchIntL4DestPort1: 25964 case bcmSwitchIntL4DestPort2: 25965 case bcmSwitchIntProbeMarker1: 25966 case bcmSwitchIntProbeMarker2: 25967 case bcmSwitchIntVersion: 25968 case bcmSwitchIntRequestVectorValue: 25969 case bcmSwitchIntRequestVectorMask: 25970 case bcmSwitchIntSwitchId: 25971 case bcmSwitchIntEgressTimeDelta: 25972 case bcmSwitchIntHopLimitCpuEnable: 25973 case bcmSwitchIntTurnAroundCpuEnable: 25974 case bcmSwitchIntMaxPayloadLength: 25975 case bcmSwitchIntL4DestPortEnable: 25976 case bcmSwitchIntProbeMarkerEnable: 25977 return bcmi_esw_int_switch_control_get(unit,type,arg); 25978 break; 25979 25980 #if defined(BCM_TRIDENT3_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 25981 case bcmSwitchIpmcSameFwdDmnThreshold: 25982 if (soc_feature(unit, soc_feature_td3_style_riot)) { 25983 BCM_IF_ERROR_RETURN(READ_EGR_FWD_DOMAIN_MATCHr(unit, &rval)); 25984 *arg = soc_reg_field_get(unit, EGR_FWD_DOMAIN_MATCHr, 25985 rval, THRESHOLDf); 25986 return BCM_E_NONE; 25987 } else { 25988 return BCM_E_UNAVAIL; 25989 } 25990 #endif 25991 case bcmSwitchE2EFCReceiveDestMacOui: 25992 case bcmSwitchE2EFCReceiveDestMacNonOui: 25993 case bcmSwitchE2EFCReceiveEtherType: 25994 case bcmSwitchE2EFCReceiveOpcode: 25995 #ifdef BCM_KATANA2_SUPPORT 25996 if (SOC_IS_KATANA2(unit)) { 25997 return bcm_kt2_switch_control_get( unit, type, arg); 25998 } 25999 #endif /* BCM_KATANA2_SUPPORT */ 26000 break; 26001 #ifdef BCM_MONTEREY_SUPPORT 26002 case bcmSwitchRoeEthertype: 26003 if (soc_feature(unit, soc_feature_roe)) { 26004 uint32 reg32 = 0; 26005 SOC_IF_ERROR_RETURN(READ_EGR_ROE_ETHERTYPEr(unit, ®32)); 26006 *arg = soc_reg_field_get(unit, EGR_ROE_ETHERTYPEr, 26007 reg32, ROE_ETHERTYPEf); 26008 return BCM_E_NONE; 26009 } else { 26010 return BCM_E_UNAVAIL; 26011 } 26012 break; 26013 case bcmSwitchRoeCustomEthertype: 26014 if (soc_feature(unit, soc_feature_roe_custom)) { 26015 uint32 reg32 = 0; 26016 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_EP_1r(unit, ®32)); 26017 *arg = soc_reg_field_get(unit, BRCM_RESERVED_EP_1r, 26018 reg32, BRCM_RESERVED_EP_1_1f); 26019 return BCM_E_NONE; 26020 } else { 26021 return BCM_E_UNAVAIL; 26022 } 26023 break; 26024 case bcmSwitchRoeUdpDestPort: 26025 if (soc_feature(unit, soc_feature_roe)) { 26026 uint32 reg32 = 0; 26027 SOC_IF_ERROR_RETURN(READ_ROE_UDP_PORTr(unit, ®32)); 26028 *arg = soc_reg_field_get(unit, ROE_UDP_PORTr, 26029 reg32, VALUEf); 26030 return BCM_E_NONE; 26031 } else { 26032 return BCM_E_UNAVAIL; 26033 } 26034 break; 26035 case bcmSwitchRoeCustomUdpDestPort: 26036 if (soc_feature(unit, soc_feature_roe_custom)) { 26037 uint32 reg32 = 0; 26038 SOC_IF_ERROR_RETURN(READ_BRCM_RESERVED_IP_1r(unit, ®32)); 26039 *arg = soc_reg_field_get(unit, BRCM_RESERVED_IP_1r, 26040 reg32, BRCM_RESERVED_IP_1_1f); 26041 return BCM_E_NONE; 26042 } else { 26043 return BCM_E_UNAVAIL; 26044 } 26045 break; 26046 #endif 26047 case bcmSwitchOamOlpHeaderAdd: 26048 #if defined (BCM_SABER2_SUPPORT) || defined (BCM_METROLITE_SUPPORT) 26049 if ((SOC_IS_SABER2(unit)) || (SOC_IS_METROLITE(unit))) { 26050 BCM_IF_ERROR_RETURN(READ_EGR_OAM_RX_MODE_FOR_CPUr(unit, &rval)); 26051 *arg = rval; 26052 return BCM_E_NONE; 26053 } else { 26054 return BCM_E_UNAVAIL; 26055 } 26056 #else 26057 return BCM_E_UNAVAIL; 26058 #endif 26059 break; 26060 case bcmSwitchL2FreezeMode: 26061 return bcmi_esw_l2x_freeze_mode_get(unit, arg); 26062 break; 26063 case bcmSwitchVxlanEvpnEnable: 26064 #if defined (BCM_TRIDENT3_SUPPORT) 26065 if (soc_feature(unit, soc_feature_vxlan_evpn)) { 26066 uint32 reg32 = 0; 26067 26068 SOC_IF_ERROR_RETURN(READ_VXLAN_EVPN_CONTROLr(unit, ®32)); 26069 *arg = soc_reg_field_get(unit, VXLAN_EVPN_CONTROLr, 26070 reg32, USE_BUM_FLAGf); 26071 return BCM_E_NONE; 26072 } else 26073 #endif 26074 { 26075 return BCM_E_UNAVAIL; 26076 } 26077 break; 26078 case bcmSwitchBfdRxDisable: 26079 26080 /* 26081 * Coverity 26082 * 26083 * Coverity complains that expression is always true 26084 * irrespective of its value for ROBO version of 26085 * SOC_REG_IS_VALID 26086 */ 26087 /* coverity[constant expression result */ 26088 26089 if(SOC_REG_IS_VALID(unit, BFD_RX_UDP_CONTROLr)) { 26090 uint32 val; 26091 BCM_IF_ERROR_RETURN(READ_BFD_RX_UDP_CONTROLr(unit,&val)); 26092 *arg = !val; 26093 return BCM_E_NONE; 26094 /* coverity[constant expression result */ 26095 } else if (SOC_REG_IS_VALID(unit, BFD_RX_UDP_CONTROL_64r)) { 26096 uint64 val64; 26097 uint64 zero; 26098 COMPILER_64_ZERO(zero); 26099 26100 BCM_IF_ERROR_RETURN(READ_BFD_RX_UDP_CONTROL_64r(unit,&val64)); 26101 *arg = (COMPILER_64_EQ(val64,zero))?1:0; 26102 return BCM_E_NONE; 26103 } else { 26104 return BCM_E_UNAVAIL; 26105 } 26106 break; 26107 #if defined(BCM_TRIDENT3_SUPPORT) 26108 case bcmSwitchDosAttackIcmpPktOversize: 26109 case bcmSwitchDosAttackMinTcpHdrSize: 26110 case bcmSwitchDosAttackIcmpV6PingSize: 26111 case bcmSwitchDosAttackV6MinFragSize: 26112 if (SOC_IS_TRIDENT3X(unit)) { 26113 return _bcm_td3_dosattack_pkt_size_get(unit, type, arg); 26114 } 26115 break; 26116 case bcmSwitchGbpEtherType: 26117 if (SOC_IS_TRIDENT3X(unit)) { 26118 uint32 ver; 26119 26120 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &ver)); 26121 /* Applies to post 5.1.8 CANCUN for TD3 and in-general for MV2/HX5 */ 26122 if (!((SOC_IS_TRIDENT3(unit)) && 26123 (SOC_CANCUN_VERSION_5_2_UNDER_SERIES(ver)))) { 26124 return _bcm_td3_ing_gbp_ethertype_get(unit, arg); 26125 } 26126 } 26127 break; 26128 #ifdef BCM_HELIX5_SUPPORT 26129 case bcmSwitchGbpSidDidMcastLookupMissClassid: 26130 if (SOC_IS_HELIX5(unit)) { 26131 if (soc_feature(unit, soc_feature_flex_flow)) { 26132 return _bcm_mcastgbp_default_classid_get(unit, arg); 26133 } else { 26134 return BCM_E_UNAVAIL; 26135 } 26136 } 26137 break; 26138 #endif 26139 case bcmSwitchPreserveOtagBeforeItag: 26140 if (soc_feature(unit, soc_feature_preserve_otag_before_itag)) { 26141 uint32 reg32 = 0; 26142 SOC_IF_ERROR_RETURN(READ_EGR_FLEX_CONFIGr(unit, ®32)); 26143 *arg = soc_reg_field_get(unit, EGR_FLEX_CONFIGr, 26144 reg32, PRESERVE_OTAG_BEFORE_ITAGf); 26145 return BCM_E_NONE; 26146 } else { 26147 return BCM_E_UNAVAIL; 26148 } 26149 break; 26150 26151 case bcmSwitchVxlanUdpSrcPortSelect: 26152 if ((soc_feature(unit, soc_feature_vxlan)) || 26153 (soc_feature(unit, soc_feature_flex_flow))) { 26154 return _bcm_td3_vxlan_udp_source_port_sel_get(unit, arg); 26155 } else { 26156 return BCM_E_UNAVAIL; 26157 } 26158 break; 26159 26160 case bcmSwitchGeneveUdpSrcPortSelect: 26161 if (soc_feature(unit, soc_feature_flex_flow)) { 26162 return _bcm_td3_geneve_udp_source_port_sel_get(unit, arg); 26163 } else { 26164 return BCM_E_UNAVAIL; 26165 } 26166 break; 26167 26168 case bcmSwitchGpeUdpSrcPortSelect: 26169 if (soc_feature(unit, soc_feature_flex_flow)) { 26170 return _bcm_td3_gpe_udp_source_port_sel_get(unit, arg); 26171 } else { 26172 return BCM_E_UNAVAIL; 26173 } 26174 break; 26175 26176 case bcmSwitchCustomOuterEthertype1: 26177 case bcmSwitchCustomOuterEthertype2: 26178 case bcmSwitchCustomInnerEthertype1: 26179 case bcmSwitchCustomInnerEthertype2: 26180 case bcmSwitchCustomOuterProtocolId1: 26181 case bcmSwitchCustomOuterProtocolId2: 26182 case bcmSwitchCustomInnerProtocolId1: 26183 case bcmSwitchCustomInnerProtocolId2: 26184 case bcmSwitchCustomOuterUdpDstPort1: 26185 case bcmSwitchCustomOuterUdpDstPort2: 26186 case bcmSwitchCustomInnerUdpDstPort1: 26187 case bcmSwitchCustomInnerUdpDstPort2: 26188 if (SOC_IS_TRIDENT3X(unit)) { 26189 uint32 version; 26190 26191 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &version)); 26192 /* Applies to post 5.3.0 CANCUN for TD3 26193 * post 3.0.0 CANCUN for MV2 and 26194 * in-general for HX5 */ 26195 if (!(((SOC_IS_TRIDENT3(unit)) && (version <= SOC_CANCUN_VERSION_DEF_5_3_0)) || 26196 ((SOC_IS_MAVERICK2(unit)) && (version <= SOC_CANCUN_VERSION_DEF_3_0_0)))) { 26197 return _bcm_td3_custom_fields_get(unit, type, arg); 26198 } else { 26199 return BCM_E_UNAVAIL; 26200 } 26201 } 26202 break; 26203 #endif /* BCM_TRIDENT3_SUPPORT */ 26204 #if defined(BCM_TRIDENT3_SUPPORT) && defined(INCLUDE_L3) 26205 case bcmSwitchReservedEgressNextHop: 26206 if (SOC_REG_FIELD_VALID(unit, EGR_SYS_RSVD_OBJECTSr, 26207 NHOPf)) { 26208 int nh_index = 0; 26209 uint32 reg32_val = 0; 26210 26211 BCM_IF_ERROR_RETURN 26212 (READ_EGR_SYS_RSVD_OBJECTSr(unit, ®32_val)); 26213 nh_index = soc_reg_field_get(unit, EGR_SYS_RSVD_OBJECTSr, 26214 reg32_val, NHOPf); 26215 if (nh_index != 0) { 26216 *arg = nh_index + BCM_XGS3_EGRESS_IDX_MIN(unit); 26217 } else { 26218 *arg = BCM_XGS3_L3_INVALID_INDEX; 26219 } 26220 26221 return BCM_E_NONE; 26222 } else { 26223 return BCM_E_UNAVAIL; 26224 } 26225 break; 26226 case bcmSwitchL3UcLargeDNAT: 26227 case bcmSwitchL3UcLargeSNAT: 26228 case bcmSwitchL3UcLargeDNATSNAT: 26229 case bcmSwitchL3UcLargeDNAPT: 26230 case bcmSwitchL3UcLargeSNAPT: 26231 case bcmSwitchL3UcLargeDNAPTSNAPT: 26232 if (soc_feature(unit, soc_feature_large_scale_nat)) { 26233 uint32 ver; 26234 26235 if (!SOC_REG_IS_VALID(unit, LARGE_SCALE_NAT_CONTROLr)) { 26236 return BCM_E_UNAVAIL; 26237 } 26238 26239 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &ver)); 26240 26241 if (ver < SOC_CANCUN_VERSION_DEF_6_0_0) { 26242 return BCM_E_UNAVAIL; 26243 } 26244 26245 return _bcm_td3_large_scale_nat_uc_get(unit, type, arg); 26246 } 26247 break; 26248 case bcmSwitchL3McLargeNATRewriteType0: 26249 case bcmSwitchL3McLargeNATRewriteType1: 26250 case bcmSwitchL3McLargeNATRewriteType2: 26251 if (soc_feature(unit, soc_feature_large_scale_nat)) { 26252 uint32 ver; 26253 26254 if (!SOC_REG_IS_VALID(unit, LARGE_SCALE_NAT_CONTROLr)) { 26255 return BCM_E_UNAVAIL; 26256 } 26257 26258 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &ver)); 26259 26260 if (ver < SOC_CANCUN_VERSION_DEF_6_0_0) { 26261 return BCM_E_UNAVAIL; 26262 } 26263 26264 return _bcm_td3_large_scale_nat_mc_get(unit, type, arg); 26265 } 26266 break; 26267 case bcmSwitchIPv4DoNotVerifyIncomingChecksum: 26268 if (SOC_IS_TRIDENT3X(unit)) { 26269 uint32 ver; 26270 BCM_IF_ERROR_RETURN(soc_cancun_version_get(unit, &ver)); 26271 if ((SOC_IS_TRIDENT3(unit) && (ver >= SOC_CANCUN_VERSION_DEF_6_1_3)) || 26272 (SOC_IS_MAVERICK2(unit) && (ver >= SOC_CANCUN_VERSION_DEF_4_1_2))) { 26273 uint32 reg32 = 0; 26274 SOC_IF_ERROR_RETURN(READ_EGR_FLEX_CONFIGr(unit, ®32)); 26275 *arg = !soc_reg_field_get(unit, EGR_FLEX_CONFIGr, 26276 reg32, IPV4_INCR_CHECKSUM_ORIGINAL_VALUE_VERIFYf); 26277 return BCM_E_NONE; 26278 } 26279 } 26280 return BCM_E_UNAVAIL; 26281 break; 26282 #endif /* BCM_TRIDENT3_SUPPORT && INCLUDE_L3 */ 26283 26284 #if defined(BCM_KATANA2_SUPPORT) 26285 case bcmSwitchSystemPortOverride: 26286 if (soc_feature(unit, soc_feature_egr_vxlate_supports_dgpp)) { 26287 26288 uint64 rval64; 26289 26290 COMPILER_64_ZERO(rval64); 26291 BCM_IF_ERROR_RETURN(soc_reg_get(unit, EGR_CONFIG_1r, 26292 0, 0, &rval64)); 26293 *arg = soc_reg64_field32_get(unit, EGR_CONFIG_1r, rval64, 26294 VT_SYS_PORT_OVERRIDEf); 26295 return BCM_E_NONE; 26296 } else { 26297 return BCM_E_UNAVAIL; 26298 } 26299 #endif 26300 26301 case bcmSwitchPcieHotSwapDisable: 26302 #ifdef BCM_CMICX_SUPPORT 26303 if (soc_feature(unit, soc_feature_cmicx) && 26304 (soc_cm_get_bus_type(unit) & SOC_PCI_DEV_TYPE)) { 26305 uint32 rval; 26306 if (SOC_REG_IS_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr) && 26307 SOC_REG_FIELD_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr, ENABLEf)) { 26308 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_CTRLr(unit, &rval)); 26309 *arg = soc_reg_field_get( 26310 unit, PAXB_0_PAXB_HOTSWAP_CTRLr, rval, ENABLEf); 26311 *arg ^= 1; 26312 return BCM_E_NONE; 26313 } else { 26314 return BCM_E_UNAVAIL; 26315 } 26316 } else 26317 #endif 26318 { 26319 return BCM_E_UNAVAIL; 26320 } 26321 break; 26322 26323 default: 26324 break; 26325 } 26326 26327 /* Iterate over all ports for port specific controls */ 26328 found = 0; 26329 26330 PBMP_E_ITER(unit, port) { 26331 if (SOC_IS_STACK_PORT(unit, port)) { 26332 continue; 26333 } 26334 /* coverity[stack_use_callee] */ 26335 /* coverity[stack_use_overflow] */ 26336 rv = bcm_esw_switch_control_port_get(unit, port, type, arg); 26337 if (rv == BCM_E_NONE) { 26338 found = 1; 26339 } else if (rv != BCM_E_UNAVAIL) { 26340 return rv; 26341 } 26342 } 26343 26344 PBMP_ST_ITER(unit, port) { 26345 if (SOC_IS_STACK_PORT(unit, port) && 26346 (type != bcmSwitchDirectedMirroring)) { 26347 continue; 26348 } 26349 rv = bcm_esw_switch_control_port_get(unit, port, type, arg); 26350 if (rv == BCM_E_NONE) { 26351 found = 1; 26352 } else if (rv != BCM_E_UNAVAIL) { 26353 return rv; 26354 } 26355 } 26356 26357 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 26358 } 26359 26360 /* 26361 * Function: 26362 * _bcm_switch_init 26363 * Description: 26364 * Initialize switch controls to their different values. 26365 * Parameters: 26366 * unit - Device unit number 26367 * Returns: 26368 * BCM_E_xxx 26369 */ 26370 int 26371 _bcm_esw_switch_init(int unit) 26372 { 26373 #ifdef BCM_RCPU_SUPPORT 26374 int cos = 0; 26375 #endif 26376 #if defined(BCM_XGS3_SWITCH_SUPPORT) 26377 int mod = 0; 26378 #endif 26379 26380 /* Unit validation check */ 26381 if (!SOC_UNIT_VALID(unit)) { 26382 return BCM_E_UNIT; 26383 } 26384 26385 BCM_IF_ERROR_RETURN(_bcm_esw_switch_detach(unit)); 26386 26387 #if defined(BCM_SWITCH_MATCH_SUPPORT) 26388 if (soc_feature(unit, soc_feature_switch_match)) { 26389 bcmi_switch_match_init(unit); 26390 } 26391 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 26392 26393 #ifdef BCM_GREYHOUND2_SUPPORT 26394 if (SOC_IS_GREYHOUND2(unit)) { 26395 return _bcm_gh2_switch_init(unit); 26396 } 26397 #endif /* BCM_GREYHOUND2_SUPPORT */ 26398 26399 if (SOC_IS_RCPU_ONLY(unit)) { 26400 return BCM_E_NONE; 26401 } 26402 26403 #ifdef BCM_RCPU_SUPPORT 26404 /* Clear encapsulation priority mappings */ 26405 if (soc_feature(unit, soc_feature_rcpu_priority)) { 26406 for (cos = 0; cos < NUM_CPU_COSQ(unit); cos++) { 26407 BCM_IF_ERROR_RETURN( 26408 bcm_esw_switch_rcpu_encap_priority_map_set(unit, 0, cos, 0)); 26409 } 26410 } 26411 #endif 26412 26413 #if defined(BCM_HAWKEYE_SUPPORT) || defined(BCM_TRIUMPH2_SUPPORT) || \ 26414 defined(BCM_APOLLO_SUPPORT) || defined(BCM_SABER2_SUPPORT) 26415 /* Initialize tymesync MMRP and SRP switch controls to default values */ 26416 if (soc_feature(unit, soc_feature_timesync_support) && 26417 !SOC_WARM_BOOT(unit) && 26418 (!SOC_IS_GREYHOUND(unit) && (!SOC_IS_SABER2(unit)) && 26419 (!SOC_IS_HURRICANE3(unit)) && (!SOC_IS_HURRICANE2(unit))) && 26420 !SOC_IS_TRIDENT3X(unit)) { 26421 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_KATANA_SUPPORT) 26422 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANEX(unit) || 26423 SOC_IS_KATANAX(unit)) { 26424 BCM_IF_ERROR_RETURN( 26425 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncEthertype, 26426 TS_ETHERTYPE_DEFAULT)); 26427 BCM_IF_ERROR_RETURN( 26428 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncDestMacOui, 26429 TS_MAC_OUI_DEFAULT)); 26430 BCM_IF_ERROR_RETURN( 26431 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncDestMacNonOui, 26432 TS_MAC_NONOUI_DEFAULT)); 26433 BCM_IF_ERROR_RETURN( 26434 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncMessageTypeBitmap, 26435 TS_MAC_MSGBITMAP_DEFAULT)); 26436 } else 26437 #endif /* BCM_ENDURO_SUPPORT || BCM_KATANA_SUPPORT*/ 26438 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 26439 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit)) { 26440 #if 0 26441 BCM_IF_ERROR_RETURN( 26442 bcm_esw_switch_control_set(unit, bcmSwitchMMRPEthertype, 26443 MMRP_ETHERTYPE_DEFAULT)); 26444 BCM_IF_ERROR_RETURN( 26445 bcm_esw_switch_control_set(unit, bcmSwitchSRPEthertype, 26446 SRP_ETHERTYPE_DEFAULT)); 26447 BCM_IF_ERROR_RETURN( 26448 bcm_esw_switch_control_set(unit, bcmSwitchMMRPDestMacOui, 26449 MMRP_MAC_OUI_DEFAULT)); 26450 BCM_IF_ERROR_RETURN( 26451 bcm_esw_switch_control_set(unit, bcmSwitchSRPDestMacOui, 26452 SRP_MAC_OUI_DEFAULT)); 26453 BCM_IF_ERROR_RETURN( 26454 bcm_esw_switch_control_set(unit, bcmSwitchMMRPDestMacNonOui, 26455 MMRP_MAC_NONOUI_DEFAULT)); 26456 BCM_IF_ERROR_RETURN( 26457 bcm_esw_switch_control_set(unit, bcmSwitchSRPDestMacNonOui, 26458 SRP_MAC_NONOUI_DEFAULT)); 26459 #endif 26460 } else 26461 #endif 26462 { 26463 BCM_IF_ERROR_RETURN( 26464 bcm_esw_switch_control_set(unit, bcmSwitchMMRPEthertype, 26465 MMRP_ETHERTYPE_DEFAULT)); 26466 BCM_IF_ERROR_RETURN( 26467 bcm_esw_switch_control_set(unit, bcmSwitchSRPEthertype, 26468 SRP_ETHERTYPE_DEFAULT)); 26469 BCM_IF_ERROR_RETURN( 26470 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncEthertype, 26471 TS_ETHERTYPE_DEFAULT)); 26472 BCM_IF_ERROR_RETURN( 26473 bcm_esw_switch_control_set(unit, bcmSwitchMMRPDestMacOui, 26474 MMRP_MAC_OUI_DEFAULT)); 26475 BCM_IF_ERROR_RETURN( 26476 bcm_esw_switch_control_set(unit, bcmSwitchSRPDestMacOui, 26477 SRP_MAC_OUI_DEFAULT)); 26478 BCM_IF_ERROR_RETURN( 26479 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncDestMacOui, 26480 TS_MAC_OUI_DEFAULT)); 26481 BCM_IF_ERROR_RETURN( 26482 bcm_esw_switch_control_set(unit, bcmSwitchMMRPDestMacNonOui, 26483 MMRP_MAC_NONOUI_DEFAULT)); 26484 BCM_IF_ERROR_RETURN( 26485 bcm_esw_switch_control_set(unit, bcmSwitchSRPDestMacNonOui, 26486 SRP_MAC_NONOUI_DEFAULT)); 26487 BCM_IF_ERROR_RETURN( 26488 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncDestMacNonOui, 26489 TS_MAC_NONOUI_DEFAULT)); 26490 BCM_IF_ERROR_RETURN( 26491 bcm_esw_switch_control_set(unit, bcmSwitchTimeSyncMessageTypeBitmap, 26492 TS_MAC_MSGBITMAP_DEFAULT)); 26493 } 26494 } 26495 #endif 26496 #if defined(BCM_TRIDENT2_SUPPORT) 26497 if (SOC_IS_TD2_TT2(unit) && !SOC_WARM_BOOT(unit) && !SOC_IS_TRIDENT3X(unit)) { 26498 BCM_IF_ERROR_RETURN( 26499 bcm_td2_switch_hash_entry_init(unit)); 26500 } 26501 #endif /* BCM_TRIDENT2_SUPPORT */ 26502 26503 /* Egress copy-to-cpu Enable */ 26504 if (soc_feature(unit, soc_feature_field_egress_tocpu)) { 26505 BCM_IF_ERROR_RETURN(bcm_esw_switch_control_set(unit, 26506 bcmSwitchFieldStageEgressToCpu, EP_COPY_TOCPU_DEFAULT)); 26507 } 26508 26509 /* bcmSwitchModuleType will eventually be deprecated, 26510 * as pre-xgs3 devices are phased out. 26511 * Once deprecated, this switch control default init will be deleted. 26512 */ 26513 #if defined(BCM_XGS3_SWITCH_SUPPORT) 26514 for(mod = 0; mod < SOC_MODID_MAX(unit); mod++) { 26515 BCM_IF_ERROR_RETURN( 26516 bcm_esw_switch_control_set(unit,bcmSwitchModuleType, 26517 BCM_SWITCH_CONTROL_MOD_TYPE_PACK(mod,BCM_SWITCH_MODULE_XGS3))); 26518 26519 } 26520 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 26521 26522 #if defined(BCM_TOMAHAWK_SUPPORT) 26523 if (soc_feature(unit, soc_feature_agm)) { 26524 if (!SOC_WARM_BOOT(unit)) { 26525 BCM_IF_ERROR_RETURN(bcm_th_switch_agm_init(unit)); 26526 } 26527 } 26528 if (soc_feature(unit, soc_feature_th_tflow)) { 26529 _bcm_switch_tflow_mode_info[unit].enabled = 0; 26530 } 26531 #endif /* BCM_TOMAHAWK_SUPPORT */ 26532 26533 #if defined (BCM_WARM_BOOT_SUPPORT) 26534 if (SOC_WARM_BOOT(unit)) { 26535 BCM_IF_ERROR_RETURN(_bcm_esw_switch_reinit(unit)); 26536 } else { 26537 BCM_IF_ERROR_RETURN(_bcm_esw_switch_wb_alloc(unit)); 26538 } 26539 #endif /* BCM_WARM_BOOT_SUPPORT */ 26540 if (soc_feature(unit, soc_feature_miml) || 26541 soc_feature(unit, soc_feature_custom_header)) { 26542 #ifdef BCM_HURRICANE3_SUPPORT 26543 BCM_IF_ERROR_RETURN(bcm_hr3_switch_encap_init(unit)); 26544 #endif /* BCM_HURRICANE3_SUPPORT */ 26545 26546 #if defined (BCM_WARM_BOOT_SUPPORT) 26547 if (SOC_WARM_BOOT(unit)) { 26548 BCM_IF_ERROR_RETURN(_bcm_esw_switch_encap_reinit(unit)); 26549 } else { 26550 BCM_IF_ERROR_RETURN(_bcm_esw_switch_encap_wb_alloc(unit)); 26551 } 26552 #endif /* BCM_WARM_BOOT_SUPPORT */ 26553 } 26554 26555 26556 #ifdef BCM_TRIDENT2_SUPPORT 26557 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || 26558 SOC_IS_TRIDENT3X(unit)) { 26559 BCM_IF_ERROR_RETURN(bcm_td2_switch_match_init(unit)); 26560 } 26561 if (SOC_IS_TD2_TT2(unit) && !SOC_WARM_BOOT(unit)) { 26562 BCM_IF_ERROR_RETURN(bcm_td2_switch_l2_freeze_mode_init(unit)); 26563 } 26564 #endif /* BCM_TRIDENT2_SUPPORT */ 26565 26566 #ifdef BCM_HELIX5_SUPPORT 26567 if (soc_feature(unit, soc_feature_broadscan_dos_ctrl)) { 26568 BCM_IF_ERROR_RETURN(_bcm_hx5_switch_dosattack_events_init(unit)); 26569 } 26570 #endif 26571 26572 return BCM_E_NONE; 26573 } 26574 26575 /* 26576 * Function: 26577 * _bcm_switch_detach 26578 * Description: 26579 * Detach switch control module, free all dynamically allocated memories 26580 * Parameters: 26581 * unit - Device unit number 26582 * Returns: 26583 * BCM_E_xxx 26584 */ 26585 int 26586 _bcm_esw_switch_detach(int unit) 26587 { 26588 26589 if (_mod_type_table[unit] != NULL) { 26590 sal_free((void *)_mod_type_table[unit]); 26591 _mod_type_table[unit] = NULL; 26592 } 26593 #if defined(BCM_SWITCH_MATCH_SUPPORT) 26594 if (soc_feature(unit, soc_feature_switch_match)) { 26595 bcmi_switch_match_detach(unit); 26596 } 26597 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 26598 26599 #if defined(BCM_TRIDENT2_SUPPORT) 26600 if (SOC_IS_TD2_TT2(unit) && !SOC_WARM_BOOT(unit)) { 26601 BCM_IF_ERROR_RETURN( 26602 bcm_td2_switch_hash_entry_detach(unit)); 26603 } 26604 #endif /* BCM_TRIDENT2_SUPPORT */ 26605 26606 #ifdef BCM_HURRICANE3_SUPPORT 26607 if (soc_feature(unit, soc_feature_miml) || 26608 soc_feature(unit, soc_feature_custom_header)) { 26609 BCM_IF_ERROR_RETURN(bcm_hr3_switch_encap_detach(unit)); 26610 } 26611 #endif /* BCM_HURRICANE3_SUPPORT */ 26612 26613 #ifdef BCM_TRIDENT2_SUPPORT 26614 if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TOMAHAWKX(unit) || 26615 SOC_IS_TRIDENT3X(unit)) { 26616 BCM_IF_ERROR_RETURN(bcm_td2_switch_match_detach(unit)); 26617 } 26618 #endif /* BCM_TRIDENT2_SUPPORT */ 26619 26620 26621 return BCM_E_NONE; 26622 } 26623 26624 /* 26625 * Function: 26626 * bcm_switch_stable_register 26627 * Description: 26628 * Register read/write functions for the application provided stable for 26629 * Level 2 Warm Boot 26630 * Parameters: 26631 * unit - Device unit number 26632 * rf - Read function signature to register for the application provided 26633 * stable for Level 2 Warm Boot. 26634 * wf - Write function signature to register for the application provided 26635 * stable for Level 2 Warm Boot. 26636 * Returns: 26637 * BCM_E_xxx 26638 */ 26639 int 26640 bcm_esw_switch_stable_register(int unit, bcm_switch_read_func_t rf, 26641 bcm_switch_write_func_t wf) 26642 { 26643 #ifdef BCM_WARM_BOOT_SUPPORT 26644 return soc_switch_stable_register(unit, (soc_read_func_t)rf, 26645 (soc_write_func_t)wf, 26646 NULL, NULL); 26647 #else 26648 return BCM_E_UNAVAIL; 26649 #endif 26650 } 26651 26652 26653 /* 26654 * Function: 26655 * bcm_switch_event_register 26656 * Description: 26657 * Registers a call back function for switch critical events 26658 * Parameters: 26659 * unit - Device unit number 26660 * cb - The desired call back function to register for critical events. 26661 * userdata - Pointer to any user data to carry on. 26662 * Returns: 26663 * BCM_E_xxx 26664 * Notes: 26665 * 26666 * Several call back functions could be registered, they all will be called upon 26667 * critical event. If registered callback is called it is adviced to log the 26668 * information and reset the chip. 26669 * Same call back function with different userdata is allowed to be registered. 26670 */ 26671 int 26672 bcm_esw_switch_event_register(int unit, bcm_switch_event_cb_t cb, 26673 void *userdata) 26674 { 26675 return soc_event_register(unit, (soc_event_cb_t)cb, userdata); 26676 } 26677 26678 26679 /* 26680 * Function: 26681 * bcm_switch_event_unregister 26682 * Description: 26683 * Unregisters a call back function for switch critical events 26684 * Parameters: 26685 * unit - Device unit number 26686 * cb - The desired call back function to unregister for critical events. 26687 * userdata - Pointer to any user data associated with a call back function 26688 * Returns: 26689 * BCM_E_xxx 26690 * Notes: 26691 * 26692 * If userdata = NULL then all matched call back functions will be unregistered, 26693 */ 26694 int 26695 bcm_esw_switch_event_unregister(int unit, bcm_switch_event_cb_t cb, 26696 void *userdata) 26697 { 26698 return soc_event_unregister(unit, (soc_event_cb_t)cb, userdata); 26699 } 26700 26701 #if defined(BCM_RCPU_SUPPORT) 26702 /* 26703 * Function: 26704 * _bcm_esw_switch_rcpu_encap_input_validate 26705 * Description: 26706 * Helper function to validate input of API calls 26707 * Parameters: 26708 * unit - Device unit number 26709 * flags - RCPU encapsulation flags BCM_SWITCH_REMOTE_CPU_ENCAP_XXX 26710 * internal_cpu_pri - Priority to set 26711 * Returns: 26712 * BCM_E_xxx 26713 */ 26714 STATIC int 26715 _bcm_esw_switch_rcpu_encap_input_validate(int unit, uint32 flags, 26716 int internal_cpu_pri) 26717 { 26718 if (!soc_feature(unit, soc_feature_rcpu_priority)) { 26719 return BCM_E_UNAVAIL; 26720 } 26721 /* Priority mapping is mutual exclusive */ 26722 if ((flags & BCM_SWITCH_REMOTE_CPU_ENCAP_IEEE) && 26723 (flags & BCM_SWITCH_REMOTE_CPU_ENCAP_HIGIG2)) { 26724 return BCM_E_PARAM; 26725 } 26726 26727 if (internal_cpu_pri < 0 || internal_cpu_pri > NUM_CPU_COSQ(unit)) { 26728 return BCM_E_PARAM; 26729 } 26730 26731 return BCM_E_NONE; 26732 } 26733 #endif /* BCM_RCPU_SUPPORT */ 26734 /* 26735 * Function: 26736 * bcm_esw_switch_rcpu_encap_priority_map_set 26737 * Description: 26738 * Configure encapsulation priority for the internal priority queue. 26739 * Parameters: 26740 * unit -(IN) Device unit number 26741 * flags -(IN) Flags BCM_SWITCH_REMOTE_CPU_ENCAP_XXX 26742 * interntal_cpu_pri -(IN) Internal CPU priority queue 26743 * encap_pri -(IN) Encapsulation priority 26744 * Returns: 26745 * BCM_E_xxx 26746 * Notes: 26747 * 26748 * flags = 0 means disable priority mapping 26749 */ 26750 int 26751 bcm_esw_switch_rcpu_encap_priority_map_set(int unit, uint32 flags, 26752 int internal_cpu_pri, 26753 int encap_pri) 26754 { 26755 int rv = BCM_E_UNAVAIL; 26756 #if defined(BCM_RCPU_SUPPORT) 26757 26758 soc_field_t efields[3] = {IEEE_802_1_PRI_MAP_ENABLEf, MH_TC_MAP_ENABLEf, CPU_TC_ENABLEf}; 26759 soc_field_t fields[3] = {IEEE_802_1_Pf, MH_TCf, CPU_TCf}; 26760 uint32 values[3] = {0,0,0}, evalues[3] = {0,0,0}; 26761 int ieee_idx = 0, hg2_idx = 1, cpu_tc_idx = 2; /* index to values array */ 26762 soc_reg_t read_reg = CMIC_PKT_PRI_MAP_TABLEr; 26763 soc_reg_t regs[] = { 26764 CMIC_PKT_PRI_MAP_TABLE_ENTRY_0r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_1r, 26765 CMIC_PKT_PRI_MAP_TABLE_ENTRY_2r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_3r, 26766 CMIC_PKT_PRI_MAP_TABLE_ENTRY_4r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_5r, 26767 CMIC_PKT_PRI_MAP_TABLE_ENTRY_6r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_7r, 26768 CMIC_PKT_PRI_MAP_TABLE_ENTRY_8r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_9r, 26769 CMIC_PKT_PRI_MAP_TABLE_ENTRY_10r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_11r, 26770 CMIC_PKT_PRI_MAP_TABLE_ENTRY_12r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_13r, 26771 CMIC_PKT_PRI_MAP_TABLE_ENTRY_14r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_15r, 26772 CMIC_PKT_PRI_MAP_TABLE_ENTRY_16r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_17r, 26773 CMIC_PKT_PRI_MAP_TABLE_ENTRY_18r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_19r, 26774 CMIC_PKT_PRI_MAP_TABLE_ENTRY_20r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_21r, 26775 CMIC_PKT_PRI_MAP_TABLE_ENTRY_22r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_23r, 26776 CMIC_PKT_PRI_MAP_TABLE_ENTRY_24r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_25r, 26777 CMIC_PKT_PRI_MAP_TABLE_ENTRY_26r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_27r, 26778 CMIC_PKT_PRI_MAP_TABLE_ENTRY_28r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_29r, 26779 CMIC_PKT_PRI_MAP_TABLE_ENTRY_30r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_31r, 26780 CMIC_PKT_PRI_MAP_TABLE_ENTRY_32r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_33r, 26781 CMIC_PKT_PRI_MAP_TABLE_ENTRY_34r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_35r, 26782 CMIC_PKT_PRI_MAP_TABLE_ENTRY_36r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_37r, 26783 CMIC_PKT_PRI_MAP_TABLE_ENTRY_38r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_39r, 26784 CMIC_PKT_PRI_MAP_TABLE_ENTRY_40r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_41r, 26785 CMIC_PKT_PRI_MAP_TABLE_ENTRY_42r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_43r, 26786 CMIC_PKT_PRI_MAP_TABLE_ENTRY_44r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_45r, 26787 CMIC_PKT_PRI_MAP_TABLE_ENTRY_46r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_47r, 26788 CMIC_PKT_PRI_MAP_TABLE_ENTRY_48r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_49r, 26789 CMIC_PKT_PRI_MAP_TABLE_ENTRY_50r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_51r, 26790 CMIC_PKT_PRI_MAP_TABLE_ENTRY_52r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_53r, 26791 CMIC_PKT_PRI_MAP_TABLE_ENTRY_54r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_55r, 26792 CMIC_PKT_PRI_MAP_TABLE_ENTRY_56r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_57r, 26793 CMIC_PKT_PRI_MAP_TABLE_ENTRY_58r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_59r, 26794 CMIC_PKT_PRI_MAP_TABLE_ENTRY_60r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_61r, 26795 CMIC_PKT_PRI_MAP_TABLE_ENTRY_62r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_63r 26796 }; 26797 26798 BCM_IF_ERROR_RETURN( 26799 _bcm_esw_switch_rcpu_encap_input_validate(unit, flags, internal_cpu_pri)); 26800 26801 if (encap_pri < 0) { 26802 return BCM_E_PARAM; 26803 } 26804 26805 if (soc_feature(unit, soc_feature_cmicm)) { 26806 read_reg = regs[0]; 26807 } 26808 26809 if (!flags) { /* Empty flags mean disable mapping */ 26810 26811 values[ieee_idx] = evalues[ieee_idx] = 0 ; 26812 values[hg2_idx] = evalues[hg2_idx] = 0; 26813 values[cpu_tc_idx] = evalues[cpu_tc_idx] = 0; 26814 26815 } else if (flags & BCM_SWITCH_REMOTE_CPU_ENCAP_IEEE) { 26816 int max_flen = (1 << soc_reg_field_length(unit, read_reg, IEEE_802_1_Pf)) - 1; 26817 26818 if (encap_pri > max_flen) { 26819 return BCM_E_PARAM; 26820 } 26821 values[hg2_idx] = evalues[hg2_idx] = 0; 26822 values[cpu_tc_idx] = evalues[cpu_tc_idx] = 0; 26823 values[ieee_idx] = encap_pri; 26824 evalues[ieee_idx] = 1; 26825 26826 } else if (flags & BCM_SWITCH_REMOTE_CPU_ENCAP_HIGIG2) { 26827 int max_flen = (1 << soc_reg_field_length(unit, read_reg, MH_TCf)) - 1; 26828 26829 if (encap_pri > max_flen) { 26830 return BCM_E_PARAM; 26831 } 26832 values[ieee_idx] = evalues[ieee_idx] = 0; 26833 values[cpu_tc_idx] = evalues[cpu_tc_idx] = 0 ; 26834 values[hg2_idx] = encap_pri; 26835 evalues[hg2_idx] = 1; 26836 } else if (flags & BCM_SWITCH_REMOTE_CPU_ENCAP_IEEE_CPU_TC) { 26837 int max_flen = (1 << soc_reg_field_length(unit, read_reg, CPU_TCf)) - 1; 26838 26839 if (encap_pri > max_flen) { 26840 return BCM_E_PARAM; 26841 } 26842 values[ieee_idx] = evalues[ieee_idx] = 0 ; 26843 values[hg2_idx] = evalues[hg2_idx] = 0; 26844 values[cpu_tc_idx] = encap_pri; 26845 evalues[cpu_tc_idx] = 1; 26846 } else { /* Some illegal combination passed */ 26847 return BCM_E_PARAM; 26848 } 26849 26850 BCM_IF_ERROR_RETURN( 26851 soc_reg_fields32_modify(unit, CMIC_PKT_CTRLr, REG_PORT_ANY, 26852 COUNTOF(efields), efields, evalues)); 26853 if (soc_feature(unit, soc_feature_cmicm)) { 26854 BCM_IF_ERROR_RETURN 26855 (soc_reg_fields32_modify(unit, regs[internal_cpu_pri], 26856 REG_PORT_ANY, COUNTOF(fields), fields, 26857 values)); 26858 } else { 26859 BCM_IF_ERROR_RETURN( 26860 soc_reg_fields32_modify(unit, CMIC_PKT_PRI_MAP_TABLEr, 26861 internal_cpu_pri, COUNTOF(fields), 26862 fields, values)); 26863 } 26864 rv = BCM_E_NONE; 26865 26866 #endif /* BCM_RCPU_SUPPORT */ 26867 26868 return rv; 26869 } 26870 #ifdef INCLUDE_L3 26871 STATIC int 26872 _bcm_esw_l3_route_info_get(int u, bcm_switch_object_t object, int *entries) 26873 { 26874 int v4_count = 0; 26875 int v6_64_count = 0; 26876 int v6_128_count = 0; 26877 int reserved_v4_entries = 0; 26878 int reserved_v6_64_entries = 0; 26879 int reserved_v6_128_entries = 0; 26880 26881 if (entries == NULL) { 26882 return BCM_E_PARAM; 26883 } 26884 26885 #ifdef ALPM_ENABLE 26886 if (soc_feature(u, soc_feature_alpm) && 26887 soc_property_get(u, spn_L3_ALPM_ENABLE, 0)) { 26888 if (SOC_IS_TD2_TT2(u)){ 26889 int rv = BCM_E_NONE; 26890 int alpm_128b_enable = SOC_ALPM_128B_ENABLE(u); 26891 26892 int (* soc_alpm_capacity_get)(int, int, int *, int *) = NULL; 26893 #if defined(BCM_TOMAHAWK_SUPPORT) || defined(BCM_APACHE_SUPPORT) 26894 #if defined(BCM_TOMAHAWK_SUPPORT) 26895 if (soc_feature(u, soc_feature_alpm2)) { 26896 soc_alpm_capacity_get = alpm_util_route_capacity_get; 26897 } else 26898 #endif 26899 if (SOC_IS_TOMAHAWKX(u) || SOC_IS_APACHE(u) || SOC_IS_TRIDENT3X(u)) { 26900 soc_alpm_capacity_get = soc_th_alpm_route_capacity_get; 26901 } else 26902 #endif 26903 { 26904 soc_alpm_capacity_get = soc_alpm_route_capacity_get; 26905 } 26906 26907 switch(object) { 26908 case bcmSwitchObjectL3RouteV4RoutesMax: 26909 rv = (* soc_alpm_capacity_get)(u, 26910 L3_DEFIP_ALPM_IPV4m, entries, NULL); 26911 return rv; 26912 break; 26913 26914 case bcmSwitchObjectL3RouteV6Routes64bMax: 26915 if (alpm_128b_enable) { 26916 *entries = 0; 26917 } else { 26918 rv = (* soc_alpm_capacity_get)(u, 26919 L3_DEFIP_ALPM_IPV6_64m, entries, NULL); 26920 } 26921 return rv; 26922 break; 26923 26924 case bcmSwitchObjectL3RouteV6Routes128bMax: 26925 if (alpm_128b_enable) { 26926 rv = (* soc_alpm_capacity_get)(u, 26927 L3_DEFIP_ALPM_IPV6_128m, entries, NULL); 26928 } else { 26929 *entries = 0; 26930 } 26931 return rv; 26932 break; 26933 26934 case bcmSwitchObjectL3RouteV4RoutesMinGuaranteed : 26935 rv = (* soc_alpm_capacity_get)(u, 26936 L3_DEFIP_ALPM_IPV4m, NULL, entries); 26937 return rv; 26938 break; 26939 26940 case bcmSwitchObjectL3RouteV6Routes64bMinGuaranteed : 26941 if (alpm_128b_enable) { 26942 *entries = 0; 26943 } else { 26944 rv = (* soc_alpm_capacity_get)(u, 26945 L3_DEFIP_ALPM_IPV6_64m, NULL, entries); 26946 } 26947 return rv; 26948 break; 26949 26950 case bcmSwitchObjectL3RouteV6Routes128bMinGuaranteed: 26951 if (alpm_128b_enable) { 26952 rv = (* soc_alpm_capacity_get)(u, 26953 L3_DEFIP_ALPM_IPV6_128m, NULL, entries); 26954 } else { 26955 *entries = 0; 26956 } 26957 return rv; 26958 break; 26959 26960 case bcmSwitchObjectL3RouteV4RoutesFree: 26961 if (alpm_128b_enable && 26962 soc_property_get(u, spn_L3_ALPM_IPV6_128B_BKT_RSVD, 0) && 26963 SOC_IS_TOMAHAWKX(u)) { 26964 26965 rv = (* soc_alpm_capacity_get)(u, 26966 L3_DEFIP_ALPM_IPV4m, NULL, entries); 26967 26968 /* Coarse estimate: FreeRoutes = MinGuraranteed - UsedRoutes; 26969 Only applicable when V6_128B_RSVD is enabled and for TOMAHAWKX */ 26970 *entries -= BCM_XGS3_L3_DEFIP_IP4_CNT(u); 26971 if (BCM_SUCCESS(rv) && *entries < 0) { 26972 *entries = 0; 26973 } 26974 return rv; 26975 } else { 26976 return BCM_E_UNAVAIL; 26977 } 26978 break; 26979 26980 case bcmSwitchObjectL3RouteV6Routes64bFree: 26981 if (alpm_128b_enable && 26982 soc_property_get(u, spn_L3_ALPM_IPV6_128B_BKT_RSVD, 0) && 26983 SOC_IS_TOMAHAWKX(u)) { 26984 26985 *entries = 0; /* no V6Routes64bFree in V6_128B mode */ 26986 return rv; 26987 } else { 26988 return BCM_E_UNAVAIL; 26989 } 26990 break; 26991 26992 case bcmSwitchObjectL3RouteV6Routes128bFree: 26993 if (alpm_128b_enable && 26994 soc_property_get(u, spn_L3_ALPM_IPV6_128B_BKT_RSVD, 0) && 26995 SOC_IS_TOMAHAWKX(u)) { 26996 26997 rv = (* soc_alpm_capacity_get)(u, 26998 L3_DEFIP_ALPM_IPV6_128m, NULL, entries); 26999 27000 /* Coarse estimate: FreeRoutes = MinGuraranteed - UsedRoutes; 27001 Only applicable when V6_128B_RSVD is enabled and for TOMAHAWKX */ 27002 *entries -= BCM_XGS3_L3_DEFIP_IP6_CNT(u); 27003 if (BCM_SUCCESS(rv) && *entries < 0) { 27004 *entries = 0; 27005 } 27006 return rv; 27007 } else { 27008 return BCM_E_UNAVAIL; 27009 } 27010 break; 27011 27012 case bcmSwitchObjectL3RouteV4RoutesUsed: 27013 *entries = BCM_XGS3_L3_DEFIP_IP4_CNT(u); 27014 break; 27015 27016 case bcmSwitchObjectL3RouteV6Routes64bUsed: 27017 if (alpm_128b_enable) { 27018 *entries = 0; 27019 } else { 27020 *entries = BCM_XGS3_L3_DEFIP_IP6_CNT(u); 27021 } 27022 break; 27023 27024 case bcmSwitchObjectL3RouteV6Routes128bUsed: 27025 if (alpm_128b_enable) { 27026 *entries = BCM_XGS3_L3_DEFIP_IP6_CNT(u); 27027 } else { 27028 *entries = 0; 27029 } 27030 break; 27031 27032 case bcmSwitchObjectL3RouteTotalUsedRoutes: 27033 *entries = BCM_XGS3_L3_DEFIP_IP4_CNT(u) + 27034 BCM_XGS3_L3_DEFIP_IP6_CNT(u); 27035 break; 27036 27037 default: 27038 return BCM_E_UNAVAIL; 27039 } 27040 return BCM_E_NONE; 27041 27042 } else { 27043 return BCM_E_UNAVAIL; 27044 } 27045 } 27046 #endif /* ALPM_ENABLE */ 27047 27048 #ifdef BCM_TRX_SUPPORT 27049 /* Route info is not setup for external tcam devices. 27050 return BCM_E_UNAVAIL */ 27051 if ((!SOC_IS_TRIUMPH3(u)) && EXT_TCAM_IS_L3_ENABLED(u)) { 27052 return BCM_E_UNAVAIL; 27053 } 27054 #endif /* BCM_TRX_SUPPORT */ 27055 27056 SOC_IF_ERROR_RETURN(soc_lpm_reserved_route_get(u, &reserved_v4_entries, 27057 &reserved_v6_64_entries, 27058 &reserved_v6_128_entries)); 27059 switch(object) { 27060 case bcmSwitchObjectL3RouteV4RoutesMax: 27061 SOC_IF_ERROR_RETURN(soc_lpm_max_v4_route_get(u, entries)); 27062 *entries -= reserved_v4_entries; 27063 #ifdef BCM_TOMAHAWK2_SUPPORT 27064 if (soc_feature(u, soc_feature_half_of_l3_defip_ipv4_capacity)) { 27065 *entries /= 2; 27066 } 27067 #endif 27068 return BCM_E_NONE; 27069 case bcmSwitchObjectL3RouteV6Routes64bMax: 27070 SOC_IF_ERROR_RETURN(soc_lpm_max_64bv6_route_get(u, entries)); 27071 *entries -= reserved_v6_64_entries; 27072 return BCM_E_NONE; 27073 case bcmSwitchObjectL3RouteV6Routes128bMax: 27074 SOC_IF_ERROR_RETURN(soc_lpm_max_128bv6_route_get(u, entries)); 27075 *entries -= reserved_v6_128_entries; 27076 return BCM_E_NONE; 27077 case bcmSwitchObjectL3RouteV4RoutesFree: 27078 SOC_IF_ERROR_RETURN(soc_lpm_free_v4_route_get(u, entries)); 27079 *entries -= reserved_v4_entries; 27080 #ifdef BCM_TOMAHAWK2_SUPPORT 27081 if (soc_feature(u, soc_feature_half_of_l3_defip_ipv4_capacity)) { 27082 *entries /= 2; 27083 } 27084 #endif 27085 return BCM_E_NONE; 27086 case bcmSwitchObjectL3RouteV6Routes64bFree: 27087 SOC_IF_ERROR_RETURN(soc_lpm_free_64bv6_route_get(u, entries)); 27088 *entries -= reserved_v6_64_entries; 27089 return BCM_E_NONE; 27090 case bcmSwitchObjectL3RouteV6Routes128bFree: 27091 SOC_IF_ERROR_RETURN(soc_lpm_free_128bv6_route_get(u, entries)); 27092 *entries -= reserved_v6_128_entries; 27093 return BCM_E_NONE; 27094 case bcmSwitchObjectL3RouteV4RoutesUsed: 27095 return soc_lpm_used_v4_route_get(u, entries); 27096 case bcmSwitchObjectL3RouteV6Routes64bUsed: 27097 return soc_lpm_used_64bv6_route_get(u, entries); 27098 case bcmSwitchObjectL3RouteV6Routes128bUsed: 27099 return soc_lpm_used_128bv6_route_get(u, entries); 27100 case bcmSwitchObjectL3RouteTotalUsedRoutes: 27101 SOC_IF_ERROR_RETURN(soc_lpm_used_v4_route_get(u, &v4_count)); 27102 SOC_IF_ERROR_RETURN(soc_lpm_used_64bv6_route_get(u, &v6_64_count)); 27103 SOC_IF_ERROR_RETURN(soc_lpm_used_128bv6_route_get(u, &v6_128_count)); 27104 *entries = v4_count + v6_64_count + v6_128_count; 27105 break; 27106 default: 27107 return BCM_E_UNAVAIL; 27108 } 27109 return BCM_E_NONE; 27110 } 27111 #endif 27112 27113 /* 27114 * Function: 27115 * bcm_esw_switch_rcpu_encap_priority_map_get 27116 * Description: 27117 * Retrieve encapsulation priority of the internal priority queue. 27118 * Parameters: 27119 * unit -(IN) Device unit number 27120 * flags -(IN) Flags BCM_SWITCH_REMOTE_CPU_ENCAP_XXX 27121 * interntal_cpu_pri -(IN) Internal CPU priority queue 27122 * encap_pri -(OUT) Encapsulation priority 27123 * Returns: 27124 * BCM_E_xxx 27125 * Notes: 27126 * 27127 * encap_pri = -1 means disabled priority mapping 27128 */ 27129 27130 int 27131 bcm_esw_switch_rcpu_encap_priority_map_get(int unit, uint32 flags, 27132 int internal_cpu_pri, 27133 int *encap_pri) 27134 { 27135 27136 int rv = BCM_E_UNAVAIL; 27137 #if defined(BCM_RCPU_SUPPORT) 27138 uint32 regval, pkt_ctrl; 27139 soc_reg_t read_reg = CMIC_PKT_PRI_MAP_TABLEr; 27140 soc_reg_t regs[] = { 27141 CMIC_PKT_PRI_MAP_TABLE_ENTRY_0r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_1r, 27142 CMIC_PKT_PRI_MAP_TABLE_ENTRY_2r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_3r, 27143 CMIC_PKT_PRI_MAP_TABLE_ENTRY_4r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_5r, 27144 CMIC_PKT_PRI_MAP_TABLE_ENTRY_6r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_7r, 27145 CMIC_PKT_PRI_MAP_TABLE_ENTRY_8r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_9r, 27146 CMIC_PKT_PRI_MAP_TABLE_ENTRY_10r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_11r, 27147 CMIC_PKT_PRI_MAP_TABLE_ENTRY_12r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_13r, 27148 CMIC_PKT_PRI_MAP_TABLE_ENTRY_14r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_15r, 27149 CMIC_PKT_PRI_MAP_TABLE_ENTRY_16r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_17r, 27150 CMIC_PKT_PRI_MAP_TABLE_ENTRY_18r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_19r, 27151 CMIC_PKT_PRI_MAP_TABLE_ENTRY_20r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_21r, 27152 CMIC_PKT_PRI_MAP_TABLE_ENTRY_22r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_23r, 27153 CMIC_PKT_PRI_MAP_TABLE_ENTRY_24r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_25r, 27154 CMIC_PKT_PRI_MAP_TABLE_ENTRY_26r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_27r, 27155 CMIC_PKT_PRI_MAP_TABLE_ENTRY_28r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_29r, 27156 CMIC_PKT_PRI_MAP_TABLE_ENTRY_30r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_31r, 27157 CMIC_PKT_PRI_MAP_TABLE_ENTRY_32r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_33r, 27158 CMIC_PKT_PRI_MAP_TABLE_ENTRY_34r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_35r, 27159 CMIC_PKT_PRI_MAP_TABLE_ENTRY_36r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_37r, 27160 CMIC_PKT_PRI_MAP_TABLE_ENTRY_38r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_39r, 27161 CMIC_PKT_PRI_MAP_TABLE_ENTRY_40r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_41r, 27162 CMIC_PKT_PRI_MAP_TABLE_ENTRY_42r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_43r, 27163 CMIC_PKT_PRI_MAP_TABLE_ENTRY_44r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_45r, 27164 CMIC_PKT_PRI_MAP_TABLE_ENTRY_46r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_47r, 27165 CMIC_PKT_PRI_MAP_TABLE_ENTRY_48r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_49r, 27166 CMIC_PKT_PRI_MAP_TABLE_ENTRY_50r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_51r, 27167 CMIC_PKT_PRI_MAP_TABLE_ENTRY_52r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_53r, 27168 CMIC_PKT_PRI_MAP_TABLE_ENTRY_54r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_55r, 27169 CMIC_PKT_PRI_MAP_TABLE_ENTRY_56r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_57r, 27170 CMIC_PKT_PRI_MAP_TABLE_ENTRY_58r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_59r, 27171 CMIC_PKT_PRI_MAP_TABLE_ENTRY_60r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_61r, 27172 CMIC_PKT_PRI_MAP_TABLE_ENTRY_62r, CMIC_PKT_PRI_MAP_TABLE_ENTRY_63r 27173 }; 27174 27175 BCM_IF_ERROR_RETURN( 27176 _bcm_esw_switch_rcpu_encap_input_validate(unit, flags, internal_cpu_pri)); 27177 27178 if (NULL == encap_pri) { 27179 return BCM_E_PARAM; 27180 } 27181 27182 BCM_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &pkt_ctrl)); 27183 27184 if (soc_feature(unit, soc_feature_cmicm)) { 27185 /* coverity[result_independent_of_operands] */ 27186 BCM_IF_ERROR_RETURN( 27187 soc_pci_getreg(unit, soc_reg_addr(unit, regs[internal_cpu_pri], 27188 REG_PORT_ANY, 0), ®val)); 27189 read_reg = regs[internal_cpu_pri]; 27190 } else { 27191 /* coverity[result_independent_of_operands] */ 27192 BCM_IF_ERROR_RETURN( 27193 READ_CMIC_PKT_PRI_MAP_TABLEr(unit, internal_cpu_pri, ®val)); 27194 } 27195 27196 if (flags & BCM_SWITCH_REMOTE_CPU_ENCAP_IEEE) { 27197 if (!soc_reg_field_get(unit, CMIC_PKT_CTRLr, pkt_ctrl, 27198 IEEE_802_1_PRI_MAP_ENABLEf)) { 27199 *encap_pri = -1; 27200 } else { 27201 *encap_pri = soc_reg_field_get(unit, read_reg, regval, IEEE_802_1_Pf); 27202 } 27203 } else if (flags & BCM_SWITCH_REMOTE_CPU_ENCAP_HIGIG2) { 27204 if (!soc_reg_field_get(unit, CMIC_PKT_CTRLr, pkt_ctrl, MH_TC_MAP_ENABLEf)) { 27205 *encap_pri = -1; 27206 } else { 27207 *encap_pri = soc_reg_field_get(unit, read_reg, regval, MH_TCf); 27208 } 27209 } else if (flags & BCM_SWITCH_REMOTE_CPU_ENCAP_IEEE_CPU_TC) { 27210 if (!soc_reg_field_get(unit, CMIC_PKT_CTRLr, pkt_ctrl, CPU_TC_ENABLEf)) { 27211 *encap_pri = -1; 27212 } else { 27213 *encap_pri = soc_reg_field_get(unit, read_reg, regval, CPU_TCf); 27214 } 27215 } else { /* Some illegal combination passed, on get empty flags illegal */ 27216 return BCM_E_PARAM; 27217 } 27218 27219 rv = BCM_E_NONE; 27220 27221 #endif /* BCM_RCPU_SUPPORT */ 27222 27223 return rv; 27224 } 27225 27226 /* 27227 * Function: 27228 * bcm_esw_switch_rcpu_decap_priority_map_set 27229 * Description: 27230 * Configure decapsulation priority for the internal priority queue. 27231 * Parameters: 27232 * unit -(IN) Device unit number 27233 * decap_pri -(IN) CPU traffic class in CMIC header 27234 * interntal_cpu_pri -(IN) Internal CPU priority queue 27235 27236 * Returns: 27237 * BCM_E_xxx 27238 * Notes: 27239 * 27240 * flags = 0 means disable priority mapping 27241 */ 27242 int 27243 bcm_esw_switch_rcpu_decap_priority_map_set(int unit, 27244 int decap_pri, 27245 int internal_cpu_pri) 27246 { 27247 int rv = BCM_E_UNAVAIL; 27248 #if defined(BCM_RCPU_SUPPORT) 27249 cpu_ts_map_entry_t cpu_ts_map_entry; 27250 27251 if (!soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 27252 return BCM_E_UNAVAIL; 27253 } 27254 27255 if (decap_pri < 0 || decap_pri >= soc_mem_index_count(unit, CPU_TS_MAPm)) { 27256 return BCM_E_PARAM; 27257 } 27258 27259 if (internal_cpu_pri < 0 || internal_cpu_pri >= NUM_CPU_COSQ(unit)) { 27260 return BCM_E_PARAM; 27261 } 27262 27263 sal_memset(&cpu_ts_map_entry, 0, sizeof(cpu_ts_map_entry_t)); 27264 27265 soc_CPU_TS_MAPm_field32_set(unit, &cpu_ts_map_entry, CPU_QUEUE_IDf, internal_cpu_pri); 27266 27267 BCM_IF_ERROR_RETURN( 27268 WRITE_CPU_TS_MAPm(unit, MEM_BLOCK_ALL, decap_pri, &cpu_ts_map_entry)); 27269 27270 rv = BCM_E_NONE; 27271 #endif /* BCM_RCPU_SUPPORT */ 27272 return rv; 27273 } 27274 27275 /* 27276 * Function: 27277 * bcm_esw_switch_rcpu_decap_priority_map_get 27278 * Description: 27279 * Retrieve decapsulation priority of the internal priority queue. 27280 * Parameters: 27281 * unit -(IN) Device unit number 27282 * decap_pri -(IN) CPU traffic class in CMIC header 27283 * interntal_cpu_pri -(OUT) Internal CPU priority queue 27284 * Returns: 27285 * BCM_E_xxx 27286 * Notes: 27287 * 27288 * encap_pri = -1 means disabled priority mapping 27289 */ 27290 27291 int 27292 bcm_esw_switch_rcpu_decap_priority_map_get(int unit, 27293 int decap_pri, 27294 int *internal_cpu_pri) 27295 { 27296 int rv = BCM_E_UNAVAIL; 27297 #if defined(BCM_RCPU_SUPPORT) 27298 cpu_ts_map_entry_t cpu_ts_map_entry; 27299 27300 if (!soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 27301 return BCM_E_UNAVAIL; 27302 } 27303 27304 if (decap_pri < 0 || decap_pri >= soc_mem_index_count(unit, CPU_TS_MAPm)) { 27305 return BCM_E_PARAM; 27306 } 27307 27308 if (NULL == internal_cpu_pri) { 27309 return BCM_E_PARAM; 27310 } 27311 27312 BCM_IF_ERROR_RETURN( 27313 READ_CPU_TS_MAPm(unit, MEM_BLOCK_ALL, decap_pri, &cpu_ts_map_entry)); 27314 27315 *internal_cpu_pri = soc_CPU_TS_MAPm_field32_get(unit, &cpu_ts_map_entry, 27316 CPU_QUEUE_IDf); 27317 27318 rv = BCM_E_NONE; 27319 #endif /* BCM_RCPU_SUPPORT */ 27320 return rv; 27321 } 27322 27323 /* 27324 * Function: 27325 * bcm_esw_switch_agm_create 27326 * Purpose: 27327 * Creates an aggregation monitoring entry which collects bandwidth and 27328 * packet distribution information among members of a trunk group or 27329 * an ecmp group. 27330 * Parameters: 27331 * unit - (IN) bcm device 27332 * options - (IN) reserved 27333 * agm_info->type - (IN) aggregation group type 27334 * agm_info->num_members - (IN) number of members for an aggregation group 27335 * agm_info->period_interval - (IN) single period stat gathering length 27336 * agm_info->period_num - (IN) number of period that stats will be gathered 27337 * (max 16), if period_num passed is 0, 27338 * monitoring will continue counting traffic 27339 * indefinitely. 27340 * agm_info->agm_id - (OUT) id of an aggregation group monitoring entry 27341 * created via this api. 27342 * 27343 * Returns: 27344 * BCM_E_NONE: If the aggregation group monitor creation is success. 27345 * BCM_E_PARAM: If passed scale or period is out of its range. 27346 * BCM_E_UNAVAIL: If there is no monitor entry available or no 27347 * monitoring pool available. 27348 * BCM_E_FULL: When all the monitor entries are used 27349 * Notes: 27350 * at this point, one monitor entry is reserved and ready to be used 27351 */ 27352 int 27353 bcm_esw_switch_agm_create(int unit, 27354 uint32 options, 27355 bcm_switch_agm_info_t *agm_info) 27356 { 27357 #if defined(BCM_TOMAHAWK_SUPPORT) 27358 if (soc_feature(unit, soc_feature_agm)) { 27359 return bcm_th_switch_agm_create(unit, options, agm_info); 27360 } else 27361 #endif /* BCM_TOMAHAWK_SUPPORT */ 27362 return BCM_E_UNAVAIL; 27363 } 27364 27365 /* 27366 * Function: 27367 * bcm_esw_switch_agm_enable_set 27368 * Purpose: 27369 * Enable or disable the aggregation group monitoring. 27370 * Parameters: 27371 * unit - (IN) bcm device 27372 * agm_id - (IN) Id of aggregation group monitoring entry created 27373 * via the bcm_switch_agm_create api 27374 * enable - (IN) TRUE: monitoring is enabled, FALSE: monitoring is disabled 27375 * 27376 * Returns: 27377 * BCM_E_NONE: if the enable or disable is succeed 27378 * BCM_E_PARAM: if the monitoring_entry_id is not valid or the monitor 27379 * entry is not created. 27380 * Notes: 27381 * Enable: program enable field to 1 and startTS to the current 1588 27382 * timestamp value in agg_monitor_table Monitoring will continue until 27383 * the end of the period programmed If period is not specified, 27384 * the monitoring will continue counting traffic indefinitely 27385 * Disable: program enable field to 0 and set starts to 0 in 27386 * agg_monitor_table Disable monitoring on the aggregation_group, 27387 * if period_num is specified, monitoring will be disabled automatically 27388 * after period_num If monitoring is running indefinitely, 27389 * the monitoring will be stopped 27390 */ 27391 int 27392 bcm_esw_switch_agm_enable_set(int unit, 27393 bcm_switch_agm_id_t agm_id, 27394 int enable) 27395 { 27396 #if defined(BCM_TOMAHAWK_SUPPORT) 27397 if (soc_feature(unit, soc_feature_agm)) { 27398 return bcm_th_switch_agm_enable_set(unit, agm_id, enable); 27399 } else 27400 #endif /* BCM_TOMAHAWK_SUPPORT */ 27401 return BCM_E_UNAVAIL; 27402 } 27403 27404 /* 27405 * Function: 27406 * bcm_esw_switch_agm_stat_get 27407 * Purpose: 27408 * Retrieve bandwidth and packet distribution information that were 27409 * collected via aggregation group monitoring 27410 * Parameters: 27411 * unit - (IN) bcm device 27412 * agm_id - (IN) aggregation group monitoring entry 27413 * nstat - (IN) number of elements on the stat_arr (array size must 27414 * be number of members * period) 27415 * stat_arr - (IN/OUT) bandwidth and packet distribution information 27416 * per member port per period 27417 * 27418 * Returns: 27419 * BCM_E_NONE: if the collection is succeed 27420 * BCM_E_PARAM: if the monitor_entry_id is not valid or the monitor 27421 * entry is not created. If the stat_arr is not 27422 * allocated properly. 27423 * Notes: 27424 */ 27425 int 27426 bcm_esw_switch_agm_stat_get(int unit, 27427 bcm_switch_agm_id_t agm_id, 27428 int nstat, 27429 bcm_switch_agm_stat_t *stat_arr) 27430 { 27431 #if defined(BCM_TOMAHAWK_SUPPORT) 27432 if (soc_feature(unit, soc_feature_agm)) { 27433 #if defined(BCM_TOMAHAWK3_SUPPORT) 27434 if (SOC_IS_TOMAHAWK3(unit)) { 27435 return bcm_th3_switch_agm_stat_get(unit, agm_id, nstat, stat_arr); 27436 } else 27437 #endif /* BCM_TOMAHAWK3_SUPPORT */ 27438 return bcm_th_switch_agm_stat_get(unit, agm_id, nstat, stat_arr); 27439 } else 27440 #endif /* BCM_TOMAHAWK_SUPPORT */ 27441 return BCM_E_UNAVAIL; 27442 } 27443 27444 /* 27445 * Function: 27446 * bcm_esw_switch_agm_stat_clear 27447 * Purpose: 27448 * Clear stats of counter entries attached to the aggregation monitor (id) 27449 * Parameters: 27450 * unit - (IN) bcm device 27451 * agm_id - (IN) aggregation group monitoring entry 27452 * 27453 * Returns: 27454 * BCM_E_NONE: if clearing is succeed 27455 * BCM_E_PARAM: if the monitor_entry_id is not valid or the monitor 27456 * entry is not created. 27457 * Notes: 27458 */ 27459 int 27460 bcm_esw_switch_agm_stat_clear(int unit, bcm_switch_agm_id_t agm_id) 27461 { 27462 #if defined(BCM_TOMAHAWK_SUPPORT) 27463 if (soc_feature(unit, soc_feature_agm)) { 27464 #if defined(BCM_TOMAHAWK3_SUPPORT) 27465 if (SOC_IS_TOMAHAWK3(unit)) { 27466 return bcm_th3_switch_agm_stat_clear(unit, agm_id); 27467 } else 27468 #endif /* BCM_TOMAHAWK3_SUPPORT */ 27469 return bcm_th_switch_agm_stat_clear(unit, agm_id); 27470 } else 27471 #endif /* BCM_TOMAHAWK_SUPPORT */ 27472 return BCM_E_UNAVAIL; 27473 } 27474 27475 /* 27476 * Function: 27477 * bcm_esw_switch_agm_destroy 27478 * Purpose: 27479 * Destroy an existing aggregation monitoring entry 27480 * Parameters: 27481 * unit - (IN) bcm device 27482 * agm_id - (IN) aggregation group monitoring entry created via 27483 * the bcm_switch_agm_create api 27484 * 27485 * Returns: 27486 * BCM_E_NONE: if the deletion is succeed 27487 * BCM_E_PARAM: if the monitoring_entry_id is not valid or the monitor 27488 * entry is not created. 27489 * Notes: 27490 * BCME_BUSY The AGM object is currently in use and needs to be 27491 * detached first. 27492 * Reverse steps of bcm_switch_agm_create. 27493 */ 27494 int 27495 bcm_esw_switch_agm_destroy(int unit, bcm_switch_agm_id_t agm_id) 27496 { 27497 #if defined(BCM_TOMAHAWK_SUPPORT) 27498 if (soc_feature(unit, soc_feature_agm)) { 27499 return bcm_th_switch_agm_destroy(unit, agm_id); 27500 } else 27501 #endif /* BCM_TOMAHAWK_SUPPORT */ 27502 return BCM_E_UNAVAIL; 27503 } 27504 27505 /* 27506 * Function: 27507 * bcm_esw_switch_agm_trunk_attach_get 27508 * Purpose: 27509 * Retrieve a (fabric) trunk_id where the monitor entry is attached 27510 * Parameters: 27511 * unit - (IN) bcm device 27512 * agm_id - (IN) aggregation group monitoring entry 27513 * trunk_id - (IN/OUT) (fabric) trunk id 27514 * 27515 * Returns: 27516 * BCM_E_NONE: if (fabric) trunk id is found where the monitor entry 27517 * is attached 27518 * BCM_E_NOT_FOUND: if the monitor entry is not attached to any of 27519 * aggregation group. 27520 * Notes: 27521 */ 27522 int 27523 bcm_esw_switch_agm_trunk_attach_get(int unit, bcm_switch_agm_id_t agm_id, 27524 bcm_trunk_t *trunk_id) 27525 { 27526 #if defined(BCM_TOMAHAWK_SUPPORT) 27527 if (soc_feature(unit, soc_feature_agm)) { 27528 return bcm_th_switch_agm_trunk_attach_get(unit, agm_id, trunk_id); 27529 } else 27530 #endif /* BCM_TOMAHAWK_SUPPORT */ 27531 return BCM_E_UNAVAIL; 27532 } 27533 27534 /* 27535 * Function: 27536 * bcm_esw_switch_agm_l3_ecmp_attach_get 27537 * Purpose: 27538 * Retrieve a l3 ecmp group id where the monitor entry is attached 27539 * Parameters: 27540 * unit - (IN) bcm device 27541 * agm_id - (IN) aggregation group monitoring entry 27542 * l3_ecmp_id - (IN/OUT) l3 ecmp group id 27543 * 27544 * Returns: 27545 * BCM_E_NONE: if l3 ecmp id is found where the monitor entry is attached 27546 * BCM_E_NOT_FOUND: if the monitor entry is not attached to any of 27547 * aggregation group. 27548 * Notes: 27549 */ 27550 int 27551 bcm_esw_switch_agm_l3_ecmp_attach_get(int unit, bcm_switch_agm_id_t agm_id, 27552 bcm_if_t *l3_ecmp_id) 27553 { 27554 #if defined(BCM_TOMAHAWK_SUPPORT) 27555 #if defined(INCLUDE_L3) 27556 if (soc_feature(unit, soc_feature_agm) && 27557 soc_feature(unit, soc_feature_l3)) { 27558 return bcm_th_switch_agm_l3_ecmp_attach_get(unit, agm_id, l3_ecmp_id); 27559 } else 27560 #endif 27561 #endif /* BCM_TOMAHAWK_SUPPORT */ 27562 return BCM_E_UNAVAIL; 27563 } 27564 27565 /* 27566 * Function: 27567 * bcm_esw_switch_agm_get 27568 * Purpose: 27569 * Retrieve the AGM monitor info of the specified AGM id 27570 * Parameters: 27571 * unit - (IN) bcm device 27572 * agm_info->agm_id - (IN) aggregation group monitoring entry 27573 * agm_info->type - (IN/OUT) type of an aggregation group 27574 * agm_info->num_members - (IN/OUT) 27575 * agm_info->period_num - (IN/OUT) 27576 * agm_info->period_interval - (IN/OUT) 27577 * 27578 * Returns: 27579 * BCM_E_NONE: if l3 ecmp id is found where the monitor entry is attached 27580 * BCM_E_NOT_FOUND: if the AGM monitor is not created. 27581 * Notes: 27582 */ 27583 int 27584 bcm_esw_switch_agm_get(int unit, bcm_switch_agm_info_t *agm_info) 27585 { 27586 #if defined(BCM_TOMAHAWK_SUPPORT) 27587 if (soc_feature(unit, soc_feature_agm)) { 27588 return bcm_th_switch_agm_get(unit, agm_info); 27589 } else 27590 #endif /* BCM_TOMAHAWK_SUPPORT */ 27591 return BCM_E_UNAVAIL; 27592 } 27593 27594 /* 27595 * Function: 27596 * bcm_esw_switch_agm_enable_get 27597 * Purpose: 27598 * Return a monitor entry's enable status 27599 * Parameters: 27600 * unit - (IN) bcm device 27601 * agm_id - (IN) aggregation group monitoring entry 27602 * enable - (IN/OUT) monitor entry enable/disable state 27603 * 27604 * Returns: 27605 * BCM_E_NONE: if the deletion is succeed 27606 * BCM_E_PARAM: invalid monitor_id 27607 * Notes: 27608 */ 27609 int 27610 bcm_esw_switch_agm_enable_get(int unit, bcm_switch_agm_id_t agm_id, 27611 int *enable) 27612 { 27613 #if defined(BCM_TOMAHAWK_SUPPORT) 27614 if (soc_feature(unit, soc_feature_agm)) { 27615 return bcm_th_switch_agm_enable_get(unit, agm_id, enable); 27616 } else 27617 #endif /* BCM_TOMAHAWK_SUPPORT */ 27618 return BCM_E_UNAVAIL; 27619 } 27620 27621 /* 27622 * Function: 27623 * bcm_esw_switch_agm_traverse 27624 * Purpose: 27625 * Traverse over the aggregation monitor table (63 total entries) 27626 * and run callback at each entry. 27627 * Parameters: 27628 * unit - (IN) bcm device 27629 * flags - (IN) reserved 27630 * trav_fn - (IN) The callback to be called on entries that match 27631 * the given entry 27632 * user_data - (IN) Pointer to any data provided by API caller. 27633 * 27634 * Returns: 27635 * BCM_E_NONE: if the traverse is succeed 27636 * BCM_E_XXX 27637 * Notes: 27638 */ 27639 int 27640 bcm_esw_switch_agm_traverse(int unit, int flags, 27641 bcm_switch_agm_traverse_cb trav_fn, 27642 void *user_data) 27643 { 27644 #if defined(BCM_TOMAHAWK_SUPPORT) 27645 if (soc_feature(unit, soc_feature_agm)) { 27646 return bcm_th_switch_agm_traverse(unit, flags, trav_fn, user_data); 27647 } else 27648 #endif /* BCM_TOMAHAWK_SUPPORT */ 27649 return BCM_E_UNAVAIL; 27650 } 27651 27652 /* 27653 * Function: 27654 * bcm_esw_switch_hash_entry_create 27655 * Purpose: 27656 * Create a blank flex hash entry. 27657 * Parameters: 27658 * unit - (IN) bcm device 27659 * group - (IN) BCM field group 27660 * *entry - (OUT) BCM hash entry 27661 * 27662 * Returns: 27663 * BCM_E_NONE - Success 27664 * BCM_E_XXX 27665 * Notes: 27666 */ 27667 int 27668 bcm_esw_switch_hash_entry_create (int unit, 27669 bcm_field_group_t group, 27670 bcm_hash_entry_t *entry) 27671 { 27672 #if defined(BCM_TRIDENT2_SUPPORT) 27673 if (soc_feature(unit, soc_feature_flex_hashing)) { 27674 return bcm_td2_switch_hash_entry_create (unit, group, entry); 27675 } else 27676 #endif /* BCM_TRIDENT2_SUPPORT */ 27677 return BCM_E_UNAVAIL; 27678 } 27679 27680 /* 27681 * Function: 27682 * bcm_esw_switch_hash_entry_create_qset 27683 * Purpose: 27684 * Create a blank flex hash entry. 27685 * Parameters: 27686 * unit - (IN) Unit number. 27687 * qset - (IN) <UNDEF> 27688 * entry - (OUT) <UNDEF> 27689 * Returns: 27690 * BCM_E_xxx 27691 * Notes: 27692 */ 27693 int 27694 bcm_esw_switch_hash_entry_create_qset( 27695 int unit, 27696 bcm_field_qset_t qset, 27697 bcm_hash_entry_t *entry) 27698 { 27699 #if defined(BCM_TRIDENT2_SUPPORT) 27700 if (soc_feature(unit, soc_feature_flex_hashing)) { 27701 return bcm_td2_switch_hash_entry_create_qset(unit, qset, entry); 27702 } else 27703 #endif /* BCM_TRIDENT2_SUPPORT */ 27704 return BCM_E_UNAVAIL; 27705 } 27706 27707 /* 27708 * Function: 27709 * bcm_esw_switch_hash_entry_destroy 27710 * Purpose: 27711 * Destroy a flex hash entry. 27712 * Parameters: 27713 * unit - (IN) bcm device 27714 * entry - (IN) BCM hash entry 27715 * 27716 * Returns: 27717 * BCM_E_NONE - Success 27718 * BCM_E_XXX 27719 * Notes: 27720 */ 27721 int 27722 bcm_esw_switch_hash_entry_destroy (int unit, 27723 bcm_hash_entry_t entry) 27724 { 27725 #if defined(BCM_TRIDENT2_SUPPORT) 27726 if (soc_feature(unit, soc_feature_flex_hashing)) { 27727 return bcm_td2_switch_hash_entry_destroy (unit, entry); 27728 } else 27729 #endif /* BCM_TRIDENT2_SUPPORT */ 27730 return BCM_E_UNAVAIL; 27731 } 27732 27733 /* 27734 * Function: 27735 * bcm_esw_switch_hash_entry_set 27736 * Purpose: 27737 * Set a flex hash entry configuration information. 27738 * Parameters: 27739 * unit - (IN) BCM device 27740 * entry - (IN) BCM hash entry 27741 * config - (IN) BCM hash configure information 27742 * 27743 * Returns: 27744 * BCM_E_NONE - Success 27745 * BCM_E_XXX 27746 * Notes: 27747 */ 27748 int 27749 bcm_esw_switch_hash_entry_set(int unit, 27750 bcm_hash_entry_t entry, 27751 bcm_switch_hash_entry_config_t *config) 27752 { 27753 #if defined(BCM_TRIDENT2_SUPPORT) 27754 if (soc_feature(unit, soc_feature_flex_hashing)) { 27755 return bcm_td2_switch_hash_entry_set(unit, entry, config); 27756 } 27757 #endif /* BCM_TRIDENT2_SUPPORT */ 27758 return BCM_E_UNAVAIL; 27759 } 27760 27761 /* 27762 * Function: 27763 * bcm_esw_switch_hash_entry_get 27764 * Purpose: 27765 * Get a flex hash entry configure information. 27766 * Parameters: 27767 * unit - (IN) BCM device 27768 * entry - (IN) BCM hash entry 27769 * config - (IN/OUT) BCM hash configure information 27770 * 27771 * Returns: 27772 * BCM_E_NONE - Success 27773 * BCM_E_XXX 27774 * Notes: 27775 */ 27776 int 27777 bcm_esw_switch_hash_entry_get(int unit, 27778 bcm_hash_entry_t entry, 27779 bcm_switch_hash_entry_config_t *config) 27780 { 27781 #if defined(BCM_TRIDENT2_SUPPORT) 27782 if (soc_feature(unit, soc_feature_flex_hashing)) { 27783 return bcm_td2_switch_hash_entry_get(unit, entry, config); 27784 } 27785 #endif /* BCM_TRIDENT2_SUPPORT */ 27786 return BCM_E_UNAVAIL; 27787 } 27788 27789 /* 27790 * Function: 27791 * bcm_esw_switch_hash_entry_traverse 27792 * Purpose: 27793 * Traverse flex hash entry tables. 27794 * Parameters: 27795 * unit - (IN) BCM device 27796 * cb_fn - (IN) BCM traverse call back function 27797 * user_data - (IN) BCM user data 27798 * 27799 * Returns: 27800 * BCM_E_NONE - Success 27801 * BCM_E_XXX 27802 * Notes: 27803 */ 27804 int 27805 bcm_esw_switch_hash_entry_traverse(int unit, int flags, 27806 bcm_switch_hash_entry_traverse_cb cb_fn, 27807 void *user_data) 27808 { 27809 #if defined(BCM_TRIDENT2_SUPPORT) 27810 if (soc_feature(unit, soc_feature_flex_hashing)) { 27811 return bcm_td2_switch_hash_entry_traverse(unit, flags, 27812 cb_fn, user_data); 27813 } 27814 #endif /* BCM_TRIDENT2_SUPPORT */ 27815 return BCM_E_UNAVAIL; 27816 } 27817 27818 /* 27819 * Function: 27820 * bcm_esw_switch_hash_entry_install 27821 * Purpose: 27822 * Install a flex hash entry into hardware tables. 27823 * Parameters: 27824 * unit - (IN) bcm device 27825 * entry - (IN) BCM hash entry 27826 * offset - (IN) BCM hash offset 27827 * 27828 * Returns: 27829 * BCM_E_NONE - Success 27830 * BCM_E_XXX 27831 * Notes: 27832 */ 27833 int 27834 bcm_esw_switch_hash_entry_install (int unit, 27835 bcm_hash_entry_t entry, 27836 uint32 offset) 27837 { 27838 #if defined(BCM_TRIDENT2_SUPPORT) 27839 if (soc_feature(unit, soc_feature_flex_hashing)) { 27840 return bcm_td2_switch_hash_entry_install(unit, entry, offset, 0xffff); 27841 } 27842 #endif /* BCM_TRIDENT2_SUPPORT */ 27843 return BCM_E_UNAVAIL; 27844 } 27845 27846 /* 27847 * Function: 27848 * bcm_esw_switch_hash_entry_reinstall 27849 * Purpose: 27850 * Re-install a flex hash entry into hardware tables. 27851 * Parameters: 27852 * unit - (IN) bcm device 27853 * entry - (IN) BCM hash entry 27854 * offset - (IN) BCM hash offset 27855 * 27856 * Returns: 27857 * BCM_E_NONE - Success 27858 * BCM_E_XXX 27859 * Notes: 27860 */ 27861 int 27862 bcm_esw_switch_hash_entry_reinstall (int unit, 27863 bcm_hash_entry_t entry, 27864 uint32 offset) 27865 { 27866 #if defined(BCM_TRIDENT2_SUPPORT) 27867 if (soc_feature(unit, soc_feature_flex_hashing)) { 27868 return bcm_td2_switch_hash_entry_reinstall(unit, entry, offset, 0xffff); 27869 } 27870 #endif /* BCM_TRIDENT2_SUPPORT */ 27871 return BCM_E_UNAVAIL; 27872 } 27873 27874 /* 27875 * Function: 27876 * bcm_esw_switch_hash_entry_remove 27877 * Purpose: 27878 * Remove a flex hash entry from hardware tables. 27879 * Parameters: 27880 * unit - (IN) bcm device 27881 * entry - (IN) BCM hash entry 27882 * 27883 * Returns: 27884 * BCM_E_NONE - Success 27885 * BCM_E_XXX 27886 * Notes: 27887 */ 27888 int 27889 bcm_esw_switch_hash_entry_remove (int unit, 27890 bcm_hash_entry_t entry) 27891 { 27892 #if defined(BCM_TRIDENT2_SUPPORT) 27893 if (soc_feature(unit, soc_feature_flex_hashing)) { 27894 return bcm_td2_switch_hash_entry_remove (unit, entry); 27895 } else 27896 #endif /* BCM_TRIDENT2_SUPPORT */ 27897 return BCM_E_UNAVAIL; 27898 } 27899 27900 /* 27901 * Function: 27902 * bcm_esw_switch_hash_qualify_data 27903 * Purpose: 27904 * Add flex hash field qualifiers into hardware tables. 27905 * Parameters: 27906 * unit - (IN) bcm device 27907 * entry - (IN) BCM hash entry 27908 * qual_id - (IN) BCM qualifier id 27909 * data - (IN) BCM hash field qualifier 27910 * mask - (IN) BCM hash field mask 27911 * Returns: 27912 * BCM_E_NONE - Success 27913 * BCM_E_XXX 27914 * Notes: 27915 */ 27916 27917 int 27918 bcm_esw_switch_hash_qualify_data (int unit, 27919 bcm_hash_entry_t entry, 27920 int qual_id, 27921 uint32 data, 27922 uint32 mask) 27923 { 27924 #if defined(BCM_TRIDENT2_SUPPORT) 27925 if (soc_feature(unit, soc_feature_flex_hashing)) { 27926 return bcm_td2_switch_hash_qualify_data (unit, entry, 27927 qual_id, data, mask); 27928 } else 27929 #endif /* BCM_TRIDENT2_SUPPORT */ 27930 return BCM_E_UNAVAIL; 27931 } 27932 27933 /* 27934 * Function: 27935 * bcm_esw_switch_hash_qualify_udf 27936 * Purpose: 27937 * Add flex hash field qualifiers into hardware tables. 27938 * Parameters: 27939 * unit - (IN) bcm device 27940 * entry - (IN) BCM hash entry 27941 * udf_id - (IN) BCM udf id 27942 * length - (IN) BCM data length 27943 * data - (IN) BCM hash udf qualifier data 27944 * mask - (IN) BCM hash field mask 27945 * Returns: 27946 * BCM_E_NONE - Success 27947 * BCM_E_XXX 27948 * Notes: 27949 */ 27950 int 27951 bcm_esw_switch_hash_qualify_udf(int unit, 27952 bcm_hash_entry_t entry, 27953 bcm_udf_id_t udf_id, 27954 int length, 27955 uint8 *data, 27956 uint8 *mask) 27957 { 27958 #if defined(BCM_TRIDENT2_SUPPORT) 27959 if (soc_feature(unit, soc_feature_flex_hashing)) { 27960 return bcm_td2_switch_hash_qualify_udf(unit, entry, 27961 udf_id, length, data, mask); 27962 } else 27963 #endif /* BCM_TRIDENT2_SUPPORT */ 27964 return BCM_E_UNAVAIL; 27965 } 27966 27967 /* 27968 * Function: 27969 * bcm_esw_switch_hash_qualify_udf_get 27970 * Purpose: 27971 * Get flex hash field qualifiers from hardware tables. 27972 * Parameters: 27973 * unit - (IN) bcm device 27974 * entry - (IN) BCM hash entry 27975 * udf_id - (IN) BCM udf id 27976 * length - (OUT) BCM data length 27977 * data - (OUT) BCM hash udf qualifier data 27978 * mask - (OUT) BCM hash field mask 27979 * Returns: 27980 * BCM_E_NONE - Success 27981 * BCM_E_XXX 27982 * Notes: 27983 */ 27984 int 27985 bcm_esw_switch_hash_qualify_udf_get(int unit, 27986 bcm_hash_entry_t entry, 27987 bcm_udf_id_t udf_id, 27988 int max_length, 27989 uint8 *data, 27990 uint8 *mask, 27991 int *actual_length) 27992 { 27993 #if defined(BCM_TRIDENT2_SUPPORT) 27994 if (soc_feature(unit, soc_feature_flex_hashing)) { 27995 return bcm_td2_switch_hash_qualify_udf_get(unit, entry, udf_id, 27996 max_length, data, mask, 27997 actual_length); 27998 } else 27999 #endif /* BCM_TRIDENT2_SUPPORT */ 28000 return BCM_E_UNAVAIL; 28001 } 28002 28003 /* 28004 * Gets the maximum number of banks associated with a particular hash 28005 * memory. 28006 */ 28007 int 28008 bcm_esw_switch_hash_banks_max_get(int unit, 28009 bcm_switch_hash_table_t hash_table, 28010 uint32 *bank_count) 28011 { 28012 #ifdef BCM_TRIDENT2_SUPPORT 28013 if (soc_feature(unit, soc_feature_shared_hash_mem) ) { 28014 soc_mem_t mem; 28015 int num_banks; 28016 switch (hash_table) { 28017 case bcmHashTableL2: 28018 mem = L2Xm; 28019 break; 28020 case bcmHashTableL3: 28021 #ifdef BCM_TRIDENT3_SUPPORT 28022 if (SOC_IS_TRIDENT3X(unit)) { 28023 mem = L3_ENTRY_ONLY_SINGLEm; 28024 } else 28025 #endif /* BCM_TRIDENT3_SUPPORT */ 28026 #ifdef BCM_TOMAHAWK3_SUPPORT 28027 if (SOC_IS_TOMAHAWK3(unit)) { 28028 mem = L3_ENTRY_SINGLEm; 28029 } else 28030 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28031 { 28032 mem = L3_ENTRY_ONLYm; 28033 } 28034 break; 28035 case bcmHashTableVlanTranslate: 28036 if (SOC_IS_TRIDENT3X(unit)) { 28037 mem = VLAN_XLATE_1_SINGLEm; 28038 } else { 28039 return BCM_E_PARAM; 28040 } 28041 break; 28042 case bcmHashTableEgressVlanTranslate: 28043 if (SOC_IS_TRIDENT3X(unit)) { 28044 mem = EGR_VLAN_XLATE_1_SINGLEm; 28045 } else { 28046 return BCM_E_PARAM; 28047 } 28048 break; 28049 case bcmHashTableMPLS: 28050 #ifdef BCM_TRIDENT3_SUPPORT 28051 if (SOC_IS_TRIDENT3X(unit)) { 28052 mem = MPLS_ENTRYm; 28053 } else 28054 #endif /* BCM_TRIDENT3_SUPPORT */ 28055 #ifdef BCM_TOMAHAWK3_SUPPORT 28056 if (SOC_IS_TOMAHAWK3(unit)) { 28057 mem = MPLS_ENTRY_SINGLEm; 28058 } else 28059 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28060 { 28061 mem = L3_ENTRY_ONLYm; 28062 } 28063 default: 28064 return BCM_E_PARAM; 28065 } 28066 #ifdef BCM_HELIX5_SUPPORT 28067 if (SOC_IS_HELIX5(unit)) { 28068 BCM_IF_ERROR_RETURN 28069 (soc_helix5_hash_bank_count_get(unit, mem, &num_banks)); 28070 } else 28071 #endif /* BCM_HELIX5_SUPPORT */ 28072 #ifdef BCM_TRIDENT3_SUPPORT 28073 if (SOC_IS_TRIDENT3X(unit)) { 28074 BCM_IF_ERROR_RETURN 28075 (soc_trident3_hash_bank_count_get(unit, mem, &num_banks)); 28076 } else 28077 #endif /* BCM_TRIDENT3_SUPPORT */ 28078 #ifdef BCM_TOMAHAWK_SUPPORT 28079 if (SOC_IS_TOMAHAWKX(unit)) { 28080 #ifdef BCM_TOMAHAWK3_SUPPORT 28081 if (SOC_IS_TOMAHAWK3(unit)) { 28082 BCM_IF_ERROR_RETURN 28083 (soc_tomahawk3_hash_bank_count_get(unit, mem, &num_banks)); 28084 } else 28085 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28086 { 28087 BCM_IF_ERROR_RETURN 28088 (soc_tomahawk_hash_bank_count_get(unit, mem, &num_banks)); 28089 } 28090 } else 28091 #endif /* BCM_TOMAHAWK_SUPPORT */ 28092 #ifdef BCM_APACHE_SUPPORT 28093 if (SOC_IS_APACHE(unit)) { 28094 BCM_IF_ERROR_RETURN 28095 (soc_apache_hash_bank_count_get(unit, mem, &num_banks)); 28096 } else 28097 #endif /* BCM_APACHE_SUPPORT */ 28098 { 28099 BCM_IF_ERROR_RETURN 28100 (soc_trident2_hash_bank_count_get(unit, mem, &num_banks)); 28101 } 28102 *bank_count = num_banks; 28103 return BCM_E_NONE; 28104 } else 28105 #endif /* BCM_TRIDENT2_SUPPORT */ 28106 #ifdef BCM_ISM_SUPPORT 28107 if (soc_feature(unit, soc_feature_ism_memory)) { 28108 soc_ism_mem_type_t table; 28109 uint8 count; 28110 switch (hash_table) { 28111 case bcmHashTableL2: 28112 table = SOC_ISM_MEM_L2_ENTRY; 28113 break; 28114 case bcmHashTableL3: 28115 table = SOC_ISM_MEM_L3_ENTRY; 28116 break; 28117 case bcmHashTableVlanTranslate: 28118 table = SOC_ISM_MEM_VLAN_XLATE; 28119 break; 28120 case bcmHashTableEgressVlanTranslate: 28121 table = SOC_ISM_MEM_EP_VLAN_XLATE; 28122 break; 28123 case bcmHashTableMPLS: 28124 table = SOC_ISM_MEM_MPLS; 28125 break; 28126 default: 28127 return BCM_E_PARAM; 28128 } 28129 if (soc_ism_get_banks(unit, table, NULL, NULL, &count)) { 28130 return BCM_E_INTERNAL; 28131 } 28132 *bank_count = count; 28133 return BCM_E_NONE; 28134 } else 28135 #endif 28136 { 28137 return BCM_E_UNAVAIL; 28138 } 28139 } 28140 28141 /* Configure the hash type for a bank of the particular hash memory. */ 28142 int 28143 bcm_esw_switch_hash_banks_config_set(int unit, 28144 bcm_switch_hash_table_t hash_table, 28145 uint32 bank_num, int hash_type, 28146 uint32 hash_offset) 28147 { 28148 #ifdef BCM_ISM_SUPPORT 28149 if (soc_feature(unit, soc_feature_ism_memory)) { 28150 uint8 count, banks[_SOC_ISM_MAX_BANKS]; 28151 uint8 zero = FALSE, offset; 28152 uint32 bank_size[_SOC_ISM_MAX_BANKS]; 28153 int ofs; 28154 soc_ism_mem_type_t table; 28155 switch (hash_table) { 28156 case bcmHashTableL2: 28157 table = SOC_ISM_MEM_L2_ENTRY; 28158 break; 28159 case bcmHashTableL3: 28160 table = SOC_ISM_MEM_L3_ENTRY; 28161 break; 28162 case bcmHashTableVlanTranslate: 28163 table = SOC_ISM_MEM_VLAN_XLATE; 28164 break; 28165 case bcmHashTableEgressVlanTranslate: 28166 table = SOC_ISM_MEM_EP_VLAN_XLATE; 28167 break; 28168 case bcmHashTableMPLS: 28169 table = SOC_ISM_MEM_MPLS; 28170 break; 28171 default: 28172 return BCM_E_PARAM; 28173 } 28174 if (soc_ism_get_banks(unit, table, banks, bank_size, &count)) { 28175 return BCM_E_INTERNAL; 28176 } 28177 if (bank_num >= count) { 28178 return BCM_E_PARAM; 28179 } 28180 switch (hash_type) { 28181 case BCM_HASH_ZERO: 28182 offset = 48; 28183 zero = TRUE; 28184 break; 28185 case BCM_HASH_LSB: 28186 offset = 48; 28187 break; 28188 case BCM_HASH_CRC16L: 28189 offset = 32; 28190 break; 28191 case BCM_HASH_CRC16U: 28192 ofs = soc_ism_get_hash_bits(bank_size[bank_num]); 28193 if (ofs == SOC_E_PARAM) { 28194 return BCM_E_INTERNAL; 28195 } 28196 offset = 48 - ofs; 28197 break; 28198 case BCM_HASH_CRC32L: 28199 offset = 0; 28200 break; 28201 case BCM_HASH_CRC32U: 28202 ofs = soc_ism_get_hash_bits(bank_size[bank_num]); 28203 if (ofs == SOC_E_PARAM) { 28204 return BCM_E_INTERNAL; 28205 } 28206 offset = 32 - ofs; 28207 break; 28208 case BCM_HASH_OFFSET: 28209 if (hash_offset > 63) { 28210 return BCM_E_PARAM; 28211 } 28212 offset = (uint8)hash_offset; 28213 break; 28214 default: 28215 return BCM_E_PARAM; 28216 } 28217 if (soc_ism_hash_offset_config(unit, banks[bank_num], offset)) { 28218 return BCM_E_INTERNAL; 28219 } 28220 if (zero || (offset == 63)) { 28221 /* Clear lsb_zero for the table */ 28222 if (soc_ism_table_hash_config(unit, table, 0)) { 28223 return BCM_E_INTERNAL; 28224 } 28225 } else { 28226 /* Set lsb_zero for the table */ 28227 if (soc_ism_table_hash_config(unit, table, 1)) { 28228 return BCM_E_INTERNAL; 28229 } 28230 } 28231 return BCM_E_NONE; 28232 } else 28233 #endif /* BCM_ISM_SUPPORT */ 28234 #ifdef BCM_TRIDENT2_SUPPORT 28235 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 28236 int ofs = 14, use_lsb = 1, offset; 28237 uint8 zero = FALSE; 28238 soc_mem_t mem; 28239 int phy_bank_num; 28240 int rv = BCM_E_UNAVAIL; 28241 28242 switch (hash_table) { 28243 case bcmHashTableL2: 28244 mem = L2Xm; 28245 break; 28246 case bcmHashTableL3: 28247 #ifdef BCM_TRIDENT3_SUPPORT 28248 if (SOC_IS_TRIDENT3X(unit)) { 28249 mem = L3_ENTRY_ONLY_SINGLEm; 28250 } else 28251 #endif /* BCM_TRIDENT3_SUPPORT */ 28252 #ifdef BCM_TOMAHAWK3_SUPPORT 28253 if (SOC_IS_TOMAHAWK3(unit)) { 28254 mem = L3_ENTRY_SINGLEm; 28255 } else 28256 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28257 { 28258 mem = L3_ENTRY_ONLYm; 28259 } 28260 break; 28261 default: 28262 return BCM_E_PARAM; 28263 } 28264 #ifdef BCM_APACHE_SUPPORT 28265 if (SOC_IS_APACHE(unit)) { 28266 SOC_IF_ERROR_RETURN 28267 (soc_apache_hash_bank_number_get(unit, mem, bank_num, 28268 &phy_bank_num)); 28269 } else 28270 #endif /* BCM_APACHE_SUPPORT */ 28271 #ifdef BCM_TOMAHAWK3_SUPPORT 28272 if (SOC_IS_TOMAHAWK3(unit)) { 28273 BCM_IF_ERROR_RETURN 28274 (soc_tomahawk3_hash_bank_number_get(unit, mem,bank_num, 28275 &phy_bank_num)); 28276 } else 28277 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28278 #ifdef BCM_TOMAHAWK_SUPPORT 28279 if (SOC_IS_TOMAHAWKX(unit)) { 28280 SOC_IF_ERROR_RETURN 28281 (soc_tomahawk_hash_bank_number_get(unit, mem, bank_num, 28282 &phy_bank_num)); 28283 } else 28284 #endif /* BCM_TOMAHAWK_SUPPORT */ 28285 #ifdef BCM_HELIX5_SUPPORT 28286 if (SOC_IS_HELIX5(unit)) { 28287 SOC_IF_ERROR_RETURN 28288 (soc_hx5_hash_bank_number_get(unit, mem, bank_num, 28289 &phy_bank_num)); 28290 } else 28291 #endif /* BCM_HELIX5_SUPPORT */ 28292 #ifdef BCM_TRIDENT3_SUPPORT 28293 if (SOC_IS_TRIDENT3X(unit)) { 28294 SOC_IF_ERROR_RETURN 28295 (soc_td3_hash_bank_number_get(unit, mem, bank_num, 28296 &phy_bank_num)); 28297 } else 28298 #endif /* BCM_TRIDENT3_SUPPORT */ 28299 { 28300 SOC_IF_ERROR_RETURN 28301 (soc_trident2_hash_bank_number_get(unit, mem, bank_num, 28302 &phy_bank_num)); 28303 } 28304 #ifdef BCM_TOMAHAWK3_SUPPORT 28305 if (SOC_IS_TOMAHAWK3(unit)) { 28306 if ((hash_type != BCM_HASH_CRC32L) && 28307 (hash_type != BCM_HASH_OFFSET)) { 28308 return BCM_E_PARAM; 28309 } 28310 } 28311 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28312 switch (hash_type) { 28313 case BCM_HASH_ZERO: 28314 offset = 48; 28315 zero = TRUE; 28316 break; 28317 case BCM_HASH_LSB: 28318 offset = 48; 28319 /* In TD3/TH3/HX5/MV2, Hash Vector is defined as 28320 if HASH_TABLE_TEST_MODEf is set 28321 {zero[15:0], hash_lsb[15:0], crc32_A[31:0]} 28322 else 28323 {crc32_B[31:0], crc32_A[31:0]}. 28324 */ 28325 #ifdef BCM_TRIDENT3_SUPPORT 28326 if (SOC_IS_TRIDENT3X(unit)) { 28327 offset = 32; 28328 zero = TRUE; 28329 } 28330 #endif /* BCM_TRIDENT3_SUPPORT */ 28331 break; 28332 case BCM_HASH_CRC16L: 28333 offset = 32; 28334 break; 28335 case BCM_HASH_CRC32L: 28336 #ifdef BCM_TOMAHAWK3_SUPPORT 28337 if (SOC_IS_TOMAHAWK3(unit)) { 28338 if (hash_offset > 63) { 28339 return BCM_E_PARAM; 28340 } 28341 offset = hash_offset; 28342 } else 28343 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28344 { 28345 offset = 0; 28346 } 28347 break; 28348 case BCM_HASH_OFFSET: 28349 if (hash_offset > 63) { 28350 return BCM_E_PARAM; 28351 } 28352 offset = hash_offset; 28353 break; 28354 case BCM_HASH_CRC16U: 28355 case BCM_HASH_CRC32U: 28356 if (mem == L2Xm) { 28357 if (phy_bank_num < 2) { 28358 ofs = 12; 28359 } 28360 } else { 28361 if (phy_bank_num > 5) { 28362 ofs = 10; 28363 } 28364 } 28365 if (hash_type == BCM_HASH_CRC16U) { 28366 offset = 48 - ofs; 28367 } else { 28368 offset = 32 - ofs; 28369 } 28370 break; 28371 default: 28372 return BCM_E_PARAM; 28373 } 28374 if (zero || (offset == 63)) { 28375 use_lsb = 0; 28376 } 28377 #ifdef BCM_APACHE_SUPPORT 28378 if (SOC_IS_APACHE(unit)) { 28379 rv = soc_ap_hash_offset_set(unit, mem, phy_bank_num, offset, 28380 use_lsb); 28381 } else 28382 #endif /* BCM_APACHE_SUPPORT */ 28383 #ifdef BCM_TOMAHAWK3_SUPPORT 28384 if (SOC_IS_TOMAHAWK3(unit)) { 28385 use_lsb = (zero || (offset == 63)) ? 1 : 0; 28386 rv = soc_tomahawk3_hash_offset_set(unit, mem, phy_bank_num, offset, 28387 use_lsb); 28388 } else 28389 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28390 #ifdef BCM_TOMAHAWK_SUPPORT 28391 if (SOC_IS_TOMAHAWKX(unit)) { 28392 rv = soc_th_hash_offset_set(unit, mem, phy_bank_num, offset, 28393 use_lsb); 28394 } else 28395 #endif /* BCM_TOMAHAWK_SUPPORT */ 28396 #ifdef BCM_HELIX5_SUPPORT 28397 if (SOC_IS_HELIX5(unit)) { 28398 use_lsb = (zero || (offset == 63)) ? 1 : 0; 28399 rv = soc_hx5_hash_offset_set(unit, mem, phy_bank_num, offset, 28400 use_lsb); 28401 } else 28402 #endif /* BCM_HELIX5_SUPPORT */ 28403 #ifdef BCM_TRIDENT3_SUPPORT 28404 if (SOC_IS_TRIDENT3X(unit)) { 28405 use_lsb = (zero || (offset == 63)) ? 1 : 0; 28406 rv = soc_td3_hash_offset_set(unit, mem, phy_bank_num, offset, 28407 use_lsb); 28408 } else 28409 #endif /* BCM_TRIDENT3_SUPPORT */ 28410 { 28411 rv = soc_td2_hash_offset_set(unit, mem, phy_bank_num, offset, 28412 use_lsb); 28413 } 28414 return rv; 28415 } else 28416 #endif /* BCM_TRIDENT2_SUPPORT */ 28417 { 28418 return BCM_E_UNAVAIL; 28419 } 28420 } 28421 28422 /* 28423 * Gets the configured hash type for a bank of the particular hash 28424 * memory. 28425 */ 28426 int 28427 bcm_esw_switch_hash_banks_config_get(int unit, 28428 bcm_switch_hash_table_t hash_table, 28429 uint32 bank_num, int *hash_type, 28430 uint32 *hash_offset) 28431 { 28432 #ifdef BCM_ISM_SUPPORT 28433 if (soc_feature(unit, soc_feature_ism_memory)) { 28434 uint8 count, banks[_SOC_ISM_MAX_BANKS]; 28435 uint8 offset; 28436 uint32 bank_size[_SOC_ISM_MAX_BANKS]; 28437 int ofs; 28438 soc_ism_mem_type_t table; 28439 28440 switch (hash_table) { 28441 case bcmHashTableL2: 28442 table = SOC_ISM_MEM_L2_ENTRY; 28443 break; 28444 case bcmHashTableL3: 28445 table = SOC_ISM_MEM_L3_ENTRY; 28446 break; 28447 case bcmHashTableVlanTranslate: 28448 table = SOC_ISM_MEM_VLAN_XLATE; 28449 break; 28450 case bcmHashTableEgressVlanTranslate: 28451 table = SOC_ISM_MEM_EP_VLAN_XLATE; 28452 break; 28453 case bcmHashTableMPLS: 28454 table = SOC_ISM_MEM_MPLS; 28455 break; 28456 default: 28457 return BCM_E_PARAM; 28458 } 28459 if (soc_ism_get_banks(unit, table, banks, bank_size, &count)) { 28460 return BCM_E_INTERNAL; 28461 } 28462 if (bank_num >= count) { 28463 return BCM_E_PARAM; 28464 } 28465 if (soc_ism_hash_offset_config_get(unit, banks[bank_num], &offset)) { 28466 return BCM_E_INTERNAL; 28467 } 28468 switch (offset) { 28469 case 0: *hash_type = BCM_HASH_CRC32L; 28470 break; 28471 case 32: *hash_type = BCM_HASH_CRC16L; 28472 break; 28473 case 63: *hash_type = BCM_HASH_ZERO; 28474 break; 28475 case 48: *hash_type = BCM_HASH_LSB; 28476 break; 28477 default: 28478 ofs = soc_ism_get_hash_bits(bank_size[bank_num]); 28479 if (ofs == SOC_E_PARAM) { 28480 return BCM_E_INTERNAL; 28481 } 28482 if (32 - ofs == offset) { 28483 *hash_type = BCM_HASH_CRC32U; 28484 } else if (48 - ofs == offset) { 28485 *hash_type = BCM_HASH_CRC16U; 28486 } else { 28487 *hash_type = BCM_HASH_OFFSET; 28488 } 28489 } 28490 *hash_offset = offset; 28491 return BCM_E_NONE; 28492 } else 28493 #endif /* BCM_ISM_SUPPORT */ 28494 #ifdef BCM_TRIDENT2_SUPPORT 28495 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 28496 soc_mem_t mem; 28497 int ofs = 14, offset, use_lsb; 28498 int phy_bank_num; 28499 28500 switch (hash_table) { 28501 case bcmHashTableL2: 28502 mem = L2Xm; 28503 break; 28504 case bcmHashTableL3: 28505 #ifdef BCM_TRIDENT3_SUPPORT 28506 if (SOC_IS_TRIDENT3X(unit)) { 28507 mem = L3_ENTRY_ONLY_SINGLEm; 28508 } else 28509 #endif /* BCM_TRIDENT3_SUPPORT */ 28510 #ifdef BCM_TOMAHAWK3_SUPPORT 28511 if (SOC_IS_TOMAHAWK3(unit)) { 28512 mem = L3_ENTRY_SINGLEm; 28513 } else 28514 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28515 { 28516 mem = L3_ENTRY_ONLYm; 28517 } 28518 break; 28519 default: 28520 return BCM_E_PARAM; 28521 } 28522 #ifdef BCM_APACHE_SUPPORT 28523 if (SOC_IS_APACHE(unit)) { 28524 SOC_IF_ERROR_RETURN 28525 (soc_apache_hash_bank_number_get(unit, mem, bank_num, 28526 &phy_bank_num)); 28527 SOC_IF_ERROR_RETURN 28528 (soc_ap_hash_offset_get(unit, mem, phy_bank_num, &offset, 28529 &use_lsb)); 28530 } else 28531 #endif /* BCM_APACHE_SUPPORT */ 28532 #ifdef BCM_TOMAHAWK_SUPPORT 28533 if (SOC_IS_TOMAHAWKX(unit)) { 28534 #ifdef BCM_TOMAHAWK3_SUPPORT 28535 if (SOC_IS_TOMAHAWK3(unit)) { 28536 SOC_IF_ERROR_RETURN 28537 (soc_tomahawk3_hash_bank_number_get(unit, mem, bank_num, 28538 &phy_bank_num)); 28539 SOC_IF_ERROR_RETURN 28540 (soc_tomahawk3_hash_offset_get(unit, mem, phy_bank_num, &offset, 28541 &use_lsb)); 28542 /* All tables in TH3 use CRC-32 with Robust Hash*/ 28543 *hash_type = BCM_HASH_CRC32L; 28544 *hash_offset = offset; 28545 return BCM_E_NONE; 28546 } else 28547 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28548 { 28549 SOC_IF_ERROR_RETURN 28550 (soc_tomahawk_hash_bank_number_get(unit, mem, bank_num, 28551 &phy_bank_num)); 28552 SOC_IF_ERROR_RETURN 28553 (soc_th_hash_offset_get(unit, mem, phy_bank_num, &offset, 28554 &use_lsb)); 28555 } 28556 } else 28557 #endif /* BCM_TOMAHAWK_SUPPORT */ 28558 #ifdef BCM_HELIX5_SUPPORT 28559 if (SOC_IS_HELIX5(unit)) { 28560 SOC_IF_ERROR_RETURN 28561 (soc_hx5_hash_bank_number_get(unit, mem, bank_num, &phy_bank_num)); 28562 SOC_IF_ERROR_RETURN 28563 (soc_hx5_hash_offset_get(unit, mem, phy_bank_num, &offset, 28564 &use_lsb)); 28565 /* All tables in HX5 use CRC-32 with Robust Hash*/ 28566 *hash_type = BCM_HASH_CRC32L; 28567 *hash_offset = offset; 28568 return BCM_E_NONE; 28569 } else 28570 #endif /* BCM_HELIX5_SUPPORT */ 28571 #ifdef BCM_TRIDENT3_SUPPORT 28572 if (SOC_IS_TRIDENT3X(unit)) { 28573 SOC_IF_ERROR_RETURN 28574 (soc_td3_hash_bank_number_get(unit, mem, bank_num, &phy_bank_num)); 28575 SOC_IF_ERROR_RETURN 28576 (soc_td3_hash_offset_get(unit, mem, phy_bank_num, &offset, 28577 &use_lsb)); 28578 /* All tables in Trident3 use CRC-32 with Robust Hash*/ 28579 *hash_type = BCM_HASH_CRC32L; 28580 *hash_offset = offset; 28581 return BCM_E_NONE; 28582 } else 28583 #endif /* BCM_TRIDENT3_SUPPORT */ 28584 { 28585 SOC_IF_ERROR_RETURN 28586 (soc_trident2_hash_bank_number_get(unit, mem, bank_num, 28587 &phy_bank_num)); 28588 SOC_IF_ERROR_RETURN 28589 (soc_td2_hash_offset_get(unit, mem, phy_bank_num, &offset, 28590 &use_lsb)); 28591 } 28592 switch (offset) { 28593 case 0: *hash_type = BCM_HASH_CRC32L; 28594 break; 28595 case 32: *hash_type = BCM_HASH_CRC16L; 28596 break; 28597 case 63: *hash_type = BCM_HASH_ZERO; 28598 break; 28599 case 48: *hash_type = BCM_HASH_LSB; 28600 break; 28601 default: 28602 if (mem == L2Xm) { 28603 if (phy_bank_num < 2) { 28604 ofs = 12; 28605 } 28606 } else { 28607 if (phy_bank_num > 5) { 28608 ofs = 10; 28609 } 28610 } 28611 if (32 - ofs == offset) { 28612 *hash_type = BCM_HASH_CRC32U; 28613 } else if (48 - ofs == offset) { 28614 *hash_type = BCM_HASH_CRC16U; 28615 } else { 28616 *hash_type = BCM_HASH_OFFSET; 28617 } 28618 } 28619 *hash_offset = offset; 28620 return BCM_E_NONE; 28621 } else 28622 #endif /* BCM_TRIDENT2_SUPPORT */ 28623 { 28624 return BCM_E_UNAVAIL; 28625 } 28626 } 28627 28628 /* 28629 * Function: 28630 * bcm_esw_switch_pkt_info_hash_get 28631 * Purpose: 28632 * Gets the hash result for the specified link aggregation method 28633 * using provided packet parameters and device configuration. 28634 * Parameters: 28635 * unit - (IN) Unit number. 28636 * pkt_info - (IN) Packet parameter information for hash calculation. 28637 * dst_gport - (OUT) Destination module and port. 28638 * dst_intf - (OUT) Destination L3 interface ID egress object. 28639 * Returns: 28640 * BCM_E_xxx 28641 * Notes: 28642 */ 28643 int 28644 bcm_esw_switch_pkt_info_hash_get(int unit, bcm_switch_pkt_info_t *pkt_info, 28645 bcm_gport_t *dst_gport, bcm_if_t *dst_intf) 28646 { 28647 #ifdef BCM_TOMAHAWK_SUPPORT 28648 if (SOC_IS_TOMAHAWK3(unit)) { 28649 return BCM_E_UNAVAIL; 28650 } 28651 if (SOC_IS_TOMAHAWKX(unit)) { 28652 return _bcm_th_switch_pkt_info_hash_get(unit, pkt_info, 28653 dst_gport, dst_intf); 28654 } else 28655 #endif 28656 if (SOC_IS_TRIDENT(unit)) { 28657 return _bcm_switch_pkt_info_ecmp_hash_get(unit, pkt_info, 28658 dst_gport, dst_intf); 28659 } 28660 else if (SOC_IS_TRIDENT2X(unit) || SOC_IS_TRIDENT3X(unit)) { 28661 return _bcm_td2_switch_pkt_info_hash_get(unit, pkt_info, 28662 dst_gport, dst_intf); 28663 } 28664 else if (SOC_IS_TRIUMPH3(unit)) { 28665 return _bcm_tr3_switch_pkt_info_hash_get(unit, pkt_info, 28666 dst_gport, dst_intf); 28667 } 28668 else if (SOC_IS_KATANA2(unit)) { 28669 return _bcm_kt2_switch_pkt_info_hash_get(unit, pkt_info, 28670 dst_gport, dst_intf); 28671 } 28672 #ifdef BCM_ENDURO_SUPPORT 28673 else if (SOC_IS_ENDURO(unit)) { 28674 return _bcm_en_switch_pkt_info_hash_get(unit, pkt_info, 28675 dst_gport, dst_intf); 28676 } 28677 #endif /* BCM_ENDURO_SUPPORT */ 28678 #ifdef BCM_GREYHOUND2_SUPPORT 28679 else if (soc_feature(unit, soc_feature_gh2_rtag7)) { 28680 return _bcm_gh2_switch_pkt_info_hash_get(unit, pkt_info, 28681 dst_gport, dst_intf); 28682 } 28683 #endif /* BCM_GREYHOUND2_SUPPORT */ 28684 return BCM_E_UNAVAIL; 28685 } 28686 28687 /* 28688 * Function: 28689 * bcm_esw_switch_temperature_monitor_get 28690 * Purpose: 28691 * There are temperature monitors embedded on the various points of the 28692 * switch chip for the purpose of monitoring the health of the chip. 28693 * This routine retrieves each temperature monitor's current value and 28694 * peak value. The unit is 0.1 celsius degree. 28695 * Parameters: 28696 * unit - (IN) Unit number. 28697 * temperature_max - (IN) max number of entries of the temperature_array. 28698 * temperature_array - (OUT) the buffer array to hold the retrived values. 28699 * temperature_count - (OUT) number of actual entries retrieved. 28700 * Returns: 28701 * BCM_E_xxx 28702 * Notes: 28703 */ 28704 int 28705 bcm_esw_switch_temperature_monitor_get(int unit, 28706 int temperature_max, 28707 bcm_switch_temperature_monitor_t *temperature_array, 28708 int *temperature_count) 28709 { 28710 int rv = BCM_E_UNAVAIL; 28711 28712 #ifdef BCM_TOMAHAWK3_SUPPORT 28713 if (SOC_IS_TOMAHAWK3(unit)) { 28714 rv = soc_tomahawk3_temperature_monitor_get(unit, 28715 temperature_max,temperature_array,temperature_count); 28716 } else 28717 #endif /* BCM_TOMAHAWK3_SUPPORT */ 28718 #ifdef BCM_TOMAHAWK_SUPPORT 28719 if (SOC_IS_TOMAHAWKX(unit)) { 28720 rv = soc_tomahawk_temperature_monitor_get(unit, 28721 temperature_max,temperature_array,temperature_count); 28722 } else 28723 #endif /* BCM_TOMAHAWK_SUPPORT */ 28724 #ifdef BCM_MONTEREY_SUPPORT 28725 if (SOC_IS_MONTEREY(unit)) { 28726 rv = soc_monterey_temperature_monitor_get(unit, 28727 temperature_max,temperature_array,temperature_count); 28728 } else 28729 #endif /* BCM_APACHE_SUPPORT */ 28730 #ifdef BCM_APACHE_SUPPORT 28731 if (SOC_IS_APACHE(unit)) { 28732 rv = soc_apache_temperature_monitor_get(unit, 28733 temperature_max,temperature_array,temperature_count); 28734 } else 28735 #endif /* BCM_APACHE_SUPPORT */ 28736 #ifdef BCM_HELIX5_SUPPORT 28737 if (SOC_IS_HELIX5(unit)) { 28738 rv = soc_helix5_temperature_monitor_get(unit, 28739 temperature_max,temperature_array,temperature_count); 28740 } else 28741 #endif /* BCM_HELIX5_SUPPORT */ 28742 #ifdef BCM_TRIDENT3_SUPPORT 28743 if (SOC_IS_TRIDENT3X(unit)) { 28744 rv = soc_trident3_temperature_monitor_get(unit, 28745 temperature_max,temperature_array,temperature_count); 28746 } else 28747 #endif /* BCM_TRIDENT3_SUPPORT */ 28748 #ifdef BCM_TRIDENT2_SUPPORT 28749 if (SOC_IS_TD2_TT2(unit)) { 28750 rv = soc_trident2_temperature_monitor_get(unit, 28751 temperature_max,temperature_array,temperature_count); 28752 } else 28753 #endif /* BCM_TRIDENT_SUPPORT */ 28754 #ifdef BCM_TRIDENT_SUPPORT 28755 if (SOC_IS_TD_TT(unit)) { 28756 rv = soc_trident_temperature_monitor_get(unit, 28757 temperature_max,temperature_array,temperature_count); 28758 } else 28759 #endif /* BCM_TRIDENT_SUPPORT */ 28760 #ifdef BCM_TRIUMPH3_SUPPORT 28761 if (SOC_IS_TRIUMPH3(unit)) { 28762 rv = soc_tr3_temperature_monitor_get(unit, 28763 temperature_max,temperature_array,temperature_count); 28764 } else 28765 #endif /* BCM_TRIUMPH3_SUPPORT */ 28766 #ifdef BCM_KATANA_SUPPORT 28767 if (SOC_IS_KATANA(unit)) { 28768 rv = soc_katana_temperature_monitor_get(unit, 28769 temperature_max,temperature_array,temperature_count); 28770 } else 28771 #endif /* BCM_KATANA_SUPPORT */ 28772 #ifdef BCM_SABER2_SUPPORT 28773 if (SOC_IS_SABER2(unit)) { 28774 rv = soc_sb2_temperature_monitor_get(unit, 28775 temperature_max,temperature_array,temperature_count); 28776 } else 28777 #endif 28778 #ifdef BCM_KATANA2_SUPPORT 28779 if (SOC_IS_KATANA2(unit)) { 28780 rv = soc_kt2_temperature_monitor_get(unit, 28781 temperature_max,temperature_array,temperature_count); 28782 } else 28783 #endif /* BCM_KATANA_SUPPORT */ 28784 #ifdef BCM_SHADOW_SUPPORT 28785 if (SOC_IS_SHADOW(unit)) { 28786 rv = soc_shadow_temperature_monitor_get(unit, 28787 temperature_max,temperature_array,temperature_count); 28788 } else 28789 #endif 28790 #ifdef BCM_HURRICANE2_SUPPORT 28791 if (SOC_IS_HURRICANE2(unit)) { 28792 rv = soc_hu2_temperature_monitor_get(unit, 28793 temperature_max,temperature_array,temperature_count); 28794 } else 28795 #endif 28796 #ifdef BCM_GREYHOUND_SUPPORT 28797 if (SOC_IS_GREYHOUND(unit)) { 28798 rv = soc_gh_temperature_monitor_get(unit, 28799 temperature_max,temperature_array,temperature_count); 28800 } else 28801 #endif 28802 #ifdef BCM_HURRICANE3_SUPPORT 28803 if (SOC_IS_HURRICANE3(unit)) { 28804 rv = soc_hr3_temperature_monitor_get(unit, 28805 temperature_max,temperature_array,temperature_count); 28806 } else 28807 #endif 28808 #ifdef BCM_GREYHOUND2_SUPPORT 28809 if (SOC_IS_GREYHOUND2(unit)) { 28810 rv = soc_gh2_temperature_monitor_get(unit, 28811 temperature_max,temperature_array,temperature_count); 28812 } else 28813 #endif 28814 {} 28815 28816 return rv; 28817 } 28818 28819 /* 28820 * Function: 28821 * bcm_esw_switch_network_group_config_get 28822 * Parameters: 28823 * unit (IN)device number 28824 * source_network_group_id (IN) source split horizon group ID 28825 * config (IN/OUT) network group config information 28826 * Purpose: 28827 * This API is used for enable/disable ingress pruning, egress pruning and 28828 * ingress IPMC group remap for a given pair of 28829 * source split horizon group and destination split horizon group. 28830 * Split horizon group 0 is reserved for default case. 28831 * Katana2 (BCM5645x) family of devices support 8 split horizon group. 28832 * Returns: 28833 * BCM_E_XXX 28834 */ 28835 28836 int 28837 bcm_esw_switch_network_group_config_get(int unit, 28838 bcm_switch_network_group_t source_network_group_id, 28839 bcm_switch_network_group_config_t *config) 28840 { 28841 int rv = BCM_E_NONE; 28842 int network_group_depth = 0; 28843 soc_mem_t mem; 28844 soc_field_t field; 28845 bcm_pbmp_t prune_pbmp; 28846 ing_network_prune_control_entry_t ing_entry; 28847 egr_network_prune_control_entry_t egr_entry; 28848 28849 if (!soc_feature(unit, soc_feature_multiple_split_horizon_group)) { 28850 return BCM_E_UNAVAIL; 28851 } 28852 28853 if (config == NULL) { 28854 return BCM_E_PARAM; 28855 } 28856 28857 BCM_IF_ERROR_RETURN(bcm_esw_switch_control_get(unit, 28858 bcmSwitchNetworkGroupDepth, &network_group_depth)); 28859 28860 if (network_group_depth <= 0) { 28861 return BCM_E_UNAVAIL; 28862 } 28863 28864 if ((source_network_group_id >= network_group_depth) || 28865 (source_network_group_id < 0)) { 28866 return BCM_E_PARAM; 28867 } 28868 28869 if ((config->dest_network_group_id >= network_group_depth) || 28870 (config->dest_network_group_id < 0)) { 28871 return BCM_E_PARAM; 28872 } 28873 28874 config->config_flags &= 28875 ~(BCM_SWITCH_NETWORK_GROUP_MCAST_REMAP_ENABLE | 28876 BCM_SWITCH_NETWORK_GROUP_INGRESS_PRUNE_ENABLE | 28877 BCM_SWITCH_NETWORK_GROUP_EGRESS_PRUNE_ENABLE); 28878 28879 BCM_PBMP_CLEAR(prune_pbmp); 28880 mem = ING_NETWORK_PRUNE_CONTROLm; 28881 if (SOC_MEM_IS_VALID(unit, mem)) { 28882 BCM_IF_ERROR_RETURN(soc_mem_read(unit, mem, COPYNO_ALL, 28883 source_network_group_id, &ing_entry)); 28884 field = REMAP_IPMC_GROUPf; 28885 if (SOC_MEM_FIELD_VALID(unit, mem, field)) { 28886 if (soc_mem_field32_get(unit, mem, &ing_entry, field)) { 28887 config->config_flags |= 28888 BCM_SWITCH_NETWORK_GROUP_MCAST_REMAP_ENABLE; 28889 } 28890 } 28891 28892 field = PRUNE_ENABLE_BITMAPf; 28893 if (SOC_MEM_FIELD_VALID(unit, mem, field)) { 28894 soc_mem_pbmp_field_get(unit, mem, &ing_entry, field, &prune_pbmp); 28895 if (BCM_PBMP_MEMBER(prune_pbmp, config->dest_network_group_id)) { 28896 config->config_flags |= 28897 BCM_SWITCH_NETWORK_GROUP_INGRESS_PRUNE_ENABLE; 28898 } 28899 } 28900 } 28901 28902 BCM_PBMP_CLEAR(prune_pbmp); 28903 mem = EGR_NETWORK_PRUNE_CONTROLm; 28904 if (SOC_MEM_IS_VALID(unit, mem)) { 28905 BCM_IF_ERROR_RETURN(soc_mem_read(unit, mem, COPYNO_ALL, 28906 source_network_group_id, &egr_entry)); 28907 field = PRUNE_ENABLE_BITMAPf; 28908 if (SOC_MEM_FIELD_VALID(unit, mem, field)) { 28909 soc_mem_pbmp_field_get(unit, mem, &egr_entry, field, &prune_pbmp); 28910 if (BCM_PBMP_MEMBER(prune_pbmp, config->dest_network_group_id)) { 28911 config->config_flags |= 28912 BCM_SWITCH_NETWORK_GROUP_EGRESS_PRUNE_ENABLE; 28913 } 28914 } 28915 } 28916 return rv; 28917 } 28918 28919 /* 28920 * Function: 28921 * bcm_esw_switch_network_group_config_set 28922 * Parameters: 28923 * unit (IN)device number 28924 * source_network_group_id (IN) source split horizon group ID 28925 * config (IN) network group config information 28926 * Purpose: 28927 * This API is used to get the enable/disable status of ingress pruning, egress pruning and 28928 * ingress IPMC group remap for a given pair of 28929 * source split horizon group and destination split horizon group. 28930 * Katana2 (BCM5645x) family of devices support 8 split horizon group. 28931 * Returns: 28932 * BCM_E_XXX 28933 */ 28934 int 28935 bcm_esw_switch_network_group_config_set(int unit, 28936 bcm_switch_network_group_t source_network_group_id, 28937 bcm_switch_network_group_config_t *config) 28938 { 28939 int rv = BCM_E_NONE; 28940 int network_group_depth = 0; 28941 28942 if (!soc_feature(unit, soc_feature_multiple_split_horizon_group)) { 28943 return BCM_E_UNAVAIL; 28944 } 28945 28946 if (config == NULL) { 28947 return BCM_E_PARAM; 28948 } 28949 28950 BCM_IF_ERROR_RETURN(bcm_esw_switch_control_get(unit, 28951 bcmSwitchNetworkGroupDepth, &network_group_depth)); 28952 28953 if (network_group_depth <= 0) { 28954 return BCM_E_UNAVAIL; 28955 } 28956 28957 if (soc_property_get(unit, spn_USE_ALL_SPLITHORIZON_GROUPS, 0)) { 28958 if ((source_network_group_id >= network_group_depth) || 28959 (source_network_group_id < 0)) { 28960 return BCM_E_PARAM; 28961 } 28962 28963 if ((config->dest_network_group_id >= network_group_depth) || 28964 (config->dest_network_group_id < 0)) { 28965 return BCM_E_PARAM; 28966 } 28967 } else { 28968 if (soc_feature(unit,soc_feature_reserve_shg_network_port)) { 28969 /* network group id 0 and 1 is reserved */ 28970 if ((source_network_group_id >= network_group_depth) || 28971 (source_network_group_id <= 1)) { 28972 return BCM_E_PARAM; 28973 } 28974 28975 if ((config->dest_network_group_id >= network_group_depth) || 28976 (config->dest_network_group_id <= 1)) { 28977 return BCM_E_PARAM; 28978 } 28979 28980 } else { 28981 /* network group id 0 is reserved */ 28982 if ((source_network_group_id >= network_group_depth) || 28983 (source_network_group_id <= 0)) { 28984 return BCM_E_PARAM; 28985 } 28986 28987 if ((config->dest_network_group_id >= network_group_depth) || 28988 (config->dest_network_group_id <= 0)) { 28989 return BCM_E_PARAM; 28990 } 28991 } 28992 } 28993 #if defined(BCM_TRX_SUPPORT) && defined(INCLUDE_L3) 28994 rv = _bcm_switch_network_group_pruning(unit,source_network_group_id,config); 28995 #endif 28996 return rv; 28997 } 28998 28999 /* 29000 * Function: 29001 * bcm_switch_ipv6_reserved_multicast_addr_set 29002 * Description: 29003 * Set ipv6 reserved multicast address and mask. 29004 * 29005 * Parameters: 29006 * unit - (IN) unit number 29007 * ip6_addr - (IN) ipv6 address 29008 * ip6_mask - (IN) ipv6 addres mask 29009 * 29010 * Return Value: 29011 * BCM_E_XXX 29012 * Notes: 29013 */ 29014 int 29015 bcm_esw_switch_ipv6_reserved_multicast_addr_set(int unit, 29016 bcm_ip6_t ip6_addr, 29017 bcm_ip6_t ip6_mask) 29018 { 29019 #if defined(BCM_TRIDENT2_SUPPORT) && defined(INCLUDE_L3) 29020 if (SOC_IS_TD2_TT2(unit)) { 29021 return _bcm_td2_ipv6_reserved_multicast_addr_set(unit, ip6_addr, ip6_mask); 29022 } else 29023 #endif 29024 { 29025 return BCM_E_UNAVAIL; 29026 } 29027 } 29028 29029 /* 29030 * Function: 29031 * bcm_switch_ipv6_reserved_multicast_addr_get 29032 * Description: 29033 * get ipv6 reserved multicast address and mask. 29034 * 29035 * Parameters: 29036 * unit - (IN) unit number 29037 * ip6_addr - (IN) ipv6 address 29038 * ip6_mask - (IN) ipv6 addres mask 29039 * 29040 * Return Value: 29041 * BCM_E_XXX 29042 * Notes: 29043 */ 29044 int bcm_esw_switch_ipv6_reserved_multicast_addr_get(int unit, 29045 bcm_ip6_t *ip6_addr, 29046 bcm_ip6_t *ip6_mask) 29047 { 29048 #if defined(BCM_TRIDENT2_SUPPORT) && defined(INCLUDE_L3) 29049 if (SOC_IS_TD2_TT2(unit)) { 29050 return _bcm_td2_ipv6_reserved_multicast_addr_get(unit, ip6_addr, ip6_mask); 29051 } else 29052 #endif 29053 { 29054 return BCM_E_UNAVAIL; 29055 } 29056 } 29057 29058 /* 29059 * Function: 29060 * bcm_switch_ipv6_reserved_multicast_addr_multi_set 29061 * Description: 29062 * Set multiple ipv6 reserved multicast address and mask. 29063 * 29064 * Parameters: 29065 * unit - (IN) unit number 29066 * inner - (IN) inner or outer ipv6 header 29067 * num - (IN) number of ipv6 address/mask pairs 29068 * ip6_addr - (IN) ipv6 addresses 29069 * ip6_mask - (IN) ipv6 addres masks 29070 * 29071 * Return Value: 29072 * BCM_E_XXX 29073 * Notes: 29074 */ 29075 int 29076 bcm_esw_switch_ipv6_reserved_multicast_addr_multi_set(int unit, 29077 int inner, 29078 int num, 29079 bcm_ip6_t* ip6_addr, 29080 bcm_ip6_t* ip6_mask) 29081 { 29082 int rv = BCM_E_UNAVAIL; 29083 #if defined(BCM_TRIDENT3_SUPPORT) && defined(INCLUDE_L3) 29084 int i; 29085 if (SOC_IS_TRIDENT3(unit)) { 29086 if (num <= 0 || num > 2) { 29087 return BCM_E_PARAM; 29088 } 29089 if (inner < 0 || inner > 1) { 29090 return BCM_E_PARAM; 29091 } 29092 if (!ip6_addr || !ip6_mask) { 29093 return BCM_E_PARAM; 29094 } 29095 for (i=0; i<num; i++) { 29096 rv = _bcm_td3_ipv6_reserved_multicast_addr_multi_set(unit, 29097 inner, 29098 i, 29099 ip6_addr[i], 29100 ip6_mask[i]); 29101 if (BCM_FAILURE(rv)) { 29102 return rv; 29103 } 29104 } 29105 } 29106 #endif 29107 return rv; 29108 } 29109 29110 /* 29111 * Function: 29112 * bcm_switch_ipv6_reserved_multicast_addr_multi_get 29113 * Description: 29114 * get multiple ipv6 reserved multicast address and mask. 29115 * 29116 * Parameters: 29117 * unit - (IN) unit number 29118 * inner - (IN) inner or outer ipv6 header 29119 * num - (IN) number of ipv6 address/mask pairs 29120 * ip6_addr - (OUT) ipv6 addresses 29121 * ip6_mask - (OUT) ipv6 addres masks 29122 * 29123 * Return Value: 29124 * BCM_E_XXX 29125 * Notes: 29126 */ 29127 int bcm_esw_switch_ipv6_reserved_multicast_addr_multi_get(int unit, 29128 int inner, 29129 int num, 29130 bcm_ip6_t *ip6_addr, 29131 bcm_ip6_t *ip6_mask) 29132 { 29133 int rv = BCM_E_UNAVAIL; 29134 #if defined(BCM_TRIDENT3_SUPPORT) && defined(INCLUDE_L3) 29135 int i; 29136 if (SOC_IS_TRIDENT3(unit)) { 29137 if (num <= 0 || num > 2) { 29138 return BCM_E_PARAM; 29139 } 29140 if (inner < 0 || inner > 1) { 29141 return BCM_E_PARAM; 29142 } 29143 if (!ip6_addr || !ip6_mask) { 29144 return BCM_E_PARAM; 29145 } 29146 for (i=0; i<num; i++) { 29147 rv = _bcm_td3_ipv6_reserved_multicast_addr_multi_get(unit, 29148 inner, 29149 i, 29150 &ip6_addr[i], 29151 &ip6_mask[i]); 29152 if (BCM_FAILURE(rv)) { 29153 return rv; 29154 } 29155 } 29156 } 29157 #endif 29158 return rv; 29159 } 29160 /* 29161 * Function: 29162 * _bcm_esw_l3_object_count_get 29163 * Parameters: 29164 * unit (IN) device number 29165 * object_size (IN) Size of the object array 29166 * object (IN) Object type for which the count is to be get 29167 * entries (OUT) Reference count 29168 * Purpose: 29169 * This function retrieves the count for L3 objects 29170 * Returns: 29171 * BCM_E_XXX 29172 */ 29173 STATIC int 29174 _bcm_esw_l3_object_count_get (int unit, 29175 int object_size, 29176 bcm_switch_object_t * object_array, 29177 int *entries) 29178 { 29179 int rv = BCM_E_NONE; 29180 #ifdef INCLUDE_L3 29181 bcm_l3_info_t l3info; 29182 int iter = 0; 29183 29184 rv = bcm_esw_l3_info (unit, &l3info); 29185 BCM_IF_ERROR_RETURN (rv); 29186 29187 for (iter = 0; iter < object_size; iter++) { 29188 29189 switch (object_array[iter]) { 29190 29191 case bcmSwitchObjectL3HostCurrent: 29192 29193 entries[iter] = l3info.l3info_used_host; 29194 break; 29195 29196 case bcmSwitchObjectL3HostV4Used: 29197 29198 entries[iter] = l3info.l3info_used_host_ip4; 29199 break; 29200 29201 case bcmSwitchObjectL3HostV6Used: 29202 29203 entries[iter] = l3info.l3info_used_host_ip6; 29204 break; 29205 29206 case bcmSwitchObjectL3RouteCurrent: 29207 29208 entries[iter] = l3info.l3info_used_route; 29209 break; 29210 29211 case bcmSwitchObjectL3EgressCurrent: 29212 29213 entries[iter] = l3info.l3info_used_nexthop; 29214 break; 29215 29216 case bcmSwitchObjectIpmcCurrent: 29217 29218 entries[iter] = BCM_XGS3_L3_IP4_IPMC_CNT(unit) + 29219 BCM_XGS3_L3_IP6_IPMC_CNT(unit); 29220 break; 29221 29222 case bcmSwitchObjectEcmpCurrent: 29223 29224 entries[iter] = BCM_XGS3_L3_ECMP_GRP_CNT(unit); 29225 break; 29226 29227 case bcmSwitchObjectEcmpMax: 29228 #ifdef BCM_TRIUMPH2_SUPPORT 29229 entries[iter] = BCM_XGS3_L3_ECMP_MAX_GROUPS(unit); 29230 #endif 29231 break; 29232 29233 case bcmSwitchObjectL3HostV4Max: 29234 entries[iter] = l3info.l3info_max_host; 29235 break; 29236 29237 case bcmSwitchObjectL3HostV6Max: 29238 entries[iter] = l3info.l3info_max_host; 29239 break; 29240 29241 case bcmSwitchObjectL3EgressMax: 29242 entries[iter] = l3info.l3info_max_nexthop; 29243 break; 29244 29245 case bcmSwitchObjectIpmcV4Used: 29246 entries[iter] = BCM_XGS3_L3_IP4_IPMC_CNT(unit); 29247 break; 29248 29249 case bcmSwitchObjectIpmcV6Used: 29250 entries[iter] = BCM_XGS3_L3_IP6_IPMC_CNT(unit); 29251 break; 29252 29253 case bcmSwitchObjectIpmcV4Max: 29254 entries[iter] = l3info.l3info_max_host / 2; 29255 break; 29256 29257 case bcmSwitchObjectIpmcV6Max: 29258 entries[iter] = l3info.l3info_max_host / 4; 29259 break; 29260 29261 default: 29262 break; 29263 } 29264 } 29265 #else 29266 rv = BCM_E_UNAVAIL; 29267 #endif 29268 29269 return rv; 29270 } 29271 29272 STATIC int 29273 bcmint_l2_cb(int unit, bcm_l2_addr_t *l2addr, void *user_data) 29274 { 29275 int cnt = 0; 29276 int *count; 29277 29278 count = (int *)user_data; 29279 if (l2addr != NULL && user_data != NULL) { 29280 cnt++; 29281 *count += cnt; 29282 } 29283 29284 return BCM_E_NONE; 29285 } 29286 29287 STATIC int 29288 bcmint_switch_l2_entry_get(int unit, int *count) 29289 { 29290 int l2cnt = 0; 29291 int rv; 29292 29293 rv = bcm_esw_l2_traverse(unit, bcmint_l2_cb, &l2cnt); 29294 if (rv == BCM_E_NONE) { 29295 *count = l2cnt; 29296 } 29297 29298 return rv; 29299 } 29300 29301 /* 29302 * Function: 29303 * bcm_esw_switch_object_count_get 29304 * Parameters: 29305 * unit (IN) device number 29306 * object (IN) Object type for which the count is to be get 29307 * entries (OUT) Reference count 29308 * Purpose: 29309 * This API is used to get the statistics of the number of objects 29310 * currently residing in the system 29311 * Returns: 29312 * BCM_E_XXX 29313 */ 29314 int 29315 bcm_esw_switch_object_count_get (int unit, 29316 bcm_switch_object_t object, 29317 int *entries) 29318 { 29319 soc_control_t *soc = SOC_CONTROL(unit); 29320 int rv = BCM_E_NONE; 29321 29322 if (entries == NULL) { 29323 return (BCM_E_PARAM); 29324 } 29325 29326 *entries = 0; 29327 29328 switch (object) 29329 { 29330 case bcmSwitchObjectL2EntryCurrent: 29331 29332 if (soc->arlShadow != NULL) { 29333 *entries = soc->arlShadow->count; 29334 29335 if (soc->arlShadow_ext1 != NULL) { 29336 *entries += soc->arlShadow_ext1->count; 29337 } 29338 if (soc->arlShadow_ext2 != NULL) { 29339 *entries += soc->arlShadow_ext2->count; 29340 } 29341 } else { 29342 rv = bcmint_switch_l2_entry_get(unit, entries); 29343 } 29344 break; 29345 29346 case bcmSwitchObjectVlanCurrent: 29347 29348 /* This includes default vlan also. Hence, vlan entries will never 29349 * be 0 29350 */ 29351 rv = _bcm_vlan_count_get (unit, entries); 29352 break; 29353 29354 case bcmSwitchObjectL3HostCurrent: 29355 case bcmSwitchObjectL3RouteCurrent: 29356 case bcmSwitchObjectL3EgressCurrent: 29357 case bcmSwitchObjectIpmcCurrent: 29358 case bcmSwitchObjectEcmpCurrent: 29359 case bcmSwitchObjectEcmpMax: 29360 case bcmSwitchObjectL3HostV4Used: 29361 case bcmSwitchObjectL3HostV6Used: 29362 29363 case bcmSwitchObjectL3HostV4Max: 29364 case bcmSwitchObjectL3HostV6Max: 29365 case bcmSwitchObjectL3EgressMax: 29366 case bcmSwitchObjectIpmcV4Used: 29367 case bcmSwitchObjectIpmcV6Used: 29368 case bcmSwitchObjectIpmcV4Max: 29369 case bcmSwitchObjectIpmcV6Max: 29370 rv = _bcm_esw_l3_object_count_get(unit, 1, &object, entries); 29371 break; 29372 29373 #ifdef INCLUDE_L3 29374 case bcmSwitchObjectL3RouteV4RoutesMax: 29375 case bcmSwitchObjectL3RouteV4RoutesFree: 29376 case bcmSwitchObjectL3RouteV4RoutesUsed: 29377 case bcmSwitchObjectL3RouteV6Routes64bMax: 29378 case bcmSwitchObjectL3RouteV6Routes64bFree: 29379 case bcmSwitchObjectL3RouteV6Routes64bUsed: 29380 case bcmSwitchObjectL3RouteV6Routes128bMax: 29381 case bcmSwitchObjectL3RouteV6Routes128bFree: 29382 case bcmSwitchObjectL3RouteV6Routes128bUsed: 29383 case bcmSwitchObjectL3RouteTotalUsedRoutes: 29384 case bcmSwitchObjectL3RouteV4RoutesMinGuaranteed: 29385 case bcmSwitchObjectL3RouteV6Routes64bMinGuaranteed: 29386 case bcmSwitchObjectL3RouteV6Routes128bMinGuaranteed: 29387 if (!soc_feature(unit, soc_feature_l3)) { 29388 return BCM_E_UNAVAIL; 29389 } 29390 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TRIDENT2X(unit) || 29391 SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit) || 29392 soc_feature(unit, soc_feature_shared_defip_stat_support)) { 29393 return _bcm_esw_l3_route_info_get(unit, object, entries); 29394 } 29395 return BCM_E_UNAVAIL; 29396 break; 29397 29398 case bcmSwitchObjectIpmcHeadTableFree: 29399 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_KATANA2(unit)||SOC_IS_TRIDENT2X(unit)){ 29400 return _bcm_tr3_repl_head_entry_info_get(unit, entries); 29401 } 29402 return BCM_E_UNAVAIL; 29403 break; 29404 #endif 29405 case bcmSwitchObjectPFCDeadlockCosMax: 29406 if (soc_feature(unit, soc_feature_pfc_deadlock)) { 29407 return _bcm_pfc_deadlock_max_cos_get(unit, entries); 29408 } 29409 return BCM_E_UNAVAIL; 29410 case bcmSwitchObjectL2EntryMax: 29411 if (SOC_IS_TRIDENT2(unit) || SOC_IS_TRIDENT2PLUS(unit) || 29412 SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 29413 *entries = soc_mem_index_count(unit, L2Xm); 29414 } else { 29415 rv = BCM_E_UNAVAIL; 29416 } 29417 break; 29418 default: 29419 rv = BCM_E_UNAVAIL; 29420 29421 } 29422 29423 return (rv); 29424 } 29425 29426 /* 29427 * Function: 29428 * bcm_esw_switch_object_count_multi_get 29429 * Parameters: 29430 * unit (IN) device number 29431 * object_size (IN) Size of the object array 29432 * object (IN) Object type array 29433 * entries (OUT) Reference count array 29434 * Purpose: 29435 * This API is used to get the statistics of the numbe rof objects 29436 * currently residing in the system. This is the multi version get 29437 * of the fn bcm_esw_switch_object_count_get 29438 * Returns: 29439 * BCM_E_XXX 29440 */ 29441 int 29442 bcm_esw_switch_object_count_multi_get (int unit, 29443 int object_size, 29444 bcm_switch_object_t *object_array, 29445 int *entries) 29446 { 29447 soc_control_t *soc = SOC_CONTROL(unit); 29448 int rv = BCM_E_NONE; 29449 int index = 0; 29450 int first_l3_obj = 0; 29451 29452 if ((object_size <= 0) || (object_array == NULL) || (entries == NULL)) { 29453 return (BCM_E_PARAM); 29454 } 29455 29456 for (index = 0; index < object_size; index++) { 29457 29458 switch (object_array[index]) { 29459 case bcmSwitchObjectL2EntryCurrent: 29460 29461 if (soc->arlShadow != NULL) { 29462 entries[index] = soc->arlShadow->count; 29463 29464 if (soc->arlShadow_ext1 != NULL) { 29465 entries[index] += soc->arlShadow_ext1->count; 29466 } 29467 if (soc->arlShadow_ext2 != NULL) { 29468 entries[index] += soc->arlShadow_ext2->count; 29469 } 29470 } else { 29471 rv = BCM_E_UNAVAIL; 29472 } 29473 break; 29474 29475 case bcmSwitchObjectVlanCurrent: 29476 29477 /* This includes default vlan also. Hence, vlan entries will 29478 * never be 0 29479 */ 29480 rv = _bcm_vlan_count_get (unit, &entries[index]); 29481 break; 29482 29483 case bcmSwitchObjectL3HostCurrent: 29484 case bcmSwitchObjectL3RouteCurrent: 29485 case bcmSwitchObjectL3EgressCurrent: 29486 case bcmSwitchObjectIpmcCurrent: 29487 case bcmSwitchObjectEcmpCurrent: 29488 case bcmSwitchObjectEcmpMax: 29489 case bcmSwitchObjectL3HostV4Used: 29490 case bcmSwitchObjectL3HostV6Used: 29491 29492 case bcmSwitchObjectL3HostV4Max: 29493 case bcmSwitchObjectL3HostV6Max: 29494 case bcmSwitchObjectL3EgressMax: 29495 case bcmSwitchObjectIpmcV4Used: 29496 case bcmSwitchObjectIpmcV6Used: 29497 case bcmSwitchObjectIpmcV4Max: 29498 case bcmSwitchObjectIpmcV6Max: 29499 if (!first_l3_obj) { 29500 rv = _bcm_esw_l3_object_count_get(unit, object_size, 29501 object_array, entries); 29502 first_l3_obj = 1; 29503 } 29504 break; 29505 29506 #ifdef INCLUDE_L3 29507 case bcmSwitchObjectL3RouteV4RoutesMax: 29508 case bcmSwitchObjectL3RouteV4RoutesFree: 29509 case bcmSwitchObjectL3RouteV4RoutesUsed: 29510 case bcmSwitchObjectL3RouteV6Routes64bMax: 29511 case bcmSwitchObjectL3RouteV6Routes64bFree: 29512 case bcmSwitchObjectL3RouteV6Routes64bUsed: 29513 case bcmSwitchObjectL3RouteV6Routes128bMax: 29514 case bcmSwitchObjectL3RouteV6Routes128bFree: 29515 case bcmSwitchObjectL3RouteV6Routes128bUsed: 29516 case bcmSwitchObjectL3RouteTotalUsedRoutes: 29517 case bcmSwitchObjectL3RouteV4RoutesMinGuaranteed: 29518 case bcmSwitchObjectL3RouteV6Routes64bMinGuaranteed: 29519 case bcmSwitchObjectL3RouteV6Routes128bMinGuaranteed: 29520 if (!soc_feature(unit, soc_feature_l3)) { 29521 return BCM_E_UNAVAIL; 29522 } 29523 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TRIDENT2X(unit) || 29524 SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit) || 29525 soc_feature(unit, soc_feature_shared_defip_stat_support)) { 29526 BCM_IF_ERROR_RETURN(_bcm_esw_l3_route_info_get(unit, 29527 object_array[index], 29528 &entries[index])); 29529 } else { 29530 return BCM_E_UNAVAIL; 29531 } 29532 break; 29533 29534 case bcmSwitchObjectIpmcHeadTableFree: 29535 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_KATANA2(unit)||SOC_IS_TRIDENT2X(unit)){ 29536 return _bcm_tr3_repl_head_entry_info_get(unit, &entries[index]); 29537 } 29538 return BCM_E_UNAVAIL; 29539 break; 29540 #endif 29541 case bcmSwitchObjectL2EntryMax: 29542 if (SOC_IS_TRIDENT2(unit) || SOC_IS_TRIDENT2PLUS(unit) || 29543 SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 29544 entries[index] = soc_mem_index_count(unit, L2Xm); 29545 } else { 29546 rv = BCM_E_UNAVAIL; 29547 } 29548 break; 29549 default: 29550 rv = BCM_E_UNAVAIL; 29551 } 29552 29553 BCM_IF_ERROR_RETURN (rv); 29554 } 29555 29556 return rv; 29557 } 29558 29559 /* 29560 * Function: 29561 * bcm_esw_switch_pkt_trace_info_get 29562 * Purpose: 29563 * Read visibility packet process data from PTR_RESULTS_BUFFER_IVP, ISW1, 29564 * and ISW2 and store into bcm_switch_pkt_trace_info_s * 29565 * Parameters: 29566 * unit - (IN) Unit number. 29567 * pkt_trace_info - (INOUT) visibility pkt trace prcoess result 29568 * Returns: 29569 * BCM_E_xxx 29570 * Notes: 29571 */ 29572 int bcm_esw_switch_pkt_trace_info_get(int unit, 29573 uint32 options, uint8 port, 29574 int len, uint8 *data, 29575 bcm_switch_pkt_trace_info_t *pkt_trace_info) 29576 { 29577 int rv = BCM_E_UNAVAIL; 29578 #ifdef BCM_INSTRUMENTATION_SUPPORT 29579 #if defined(BCM_MAVERICK2_SUPPORT) 29580 if (SOC_IS_MAVERICK2(unit) && (!soc_property_get(unit, spn_IPEP_CLOCK_GATING_DISABLE, 0))) { 29581 LOG_ERROR(BSL_LS_BCM_COMMON, 29582 (BSL_META_U(unit, 29583 "\n Visibility cannot be used with IPEP clock gating enabled! Set ipep_clock_gating_disable=1\n"))); 29584 return BCM_E_CONFIG; 29585 } 29586 #endif 29587 #if defined(BCM_TOMAHAWK3_SUPPORT) 29588 if (SOC_IS_TOMAHAWK3(unit)) { 29589 rv = _bcm_th3_pkt_trace_info_get(unit, options, port, len, data, 29590 pkt_trace_info); 29591 } else 29592 #endif 29593 { 29594 rv = _bcm_esw_pkt_trace_info_get(unit, options, port, len, data, 29595 pkt_trace_info); 29596 } 29597 #endif 29598 return rv; 29599 } 29600 29601 /* 29602 * Function: 29603 * bcm_esw_switch_pkt_trace_raw_data_get 29604 * Purpose: 29605 * Read visibility packet debug information as raw data. 29606 * Parameters: 29607 * unit - (IN) Unit number. 29608 * options - (IN) CPU packet profile options for loopback port. 29609 * port - (IN) Source Masquered port. 29610 * len - (IN) Visibility packet data buffer length. 29611 * data - (IN) Visibility packet data buffer. 29612 * raw_data_size - (INOUT) Raw data length. 29613 * raw_data - (INOUT) Visibility pkt trace raw data. 29614 * Returns: 29615 * BCM_E_xxx 29616 * Notes: 29617 */ 29618 int bcm_esw_switch_pkt_trace_raw_data_get(int unit, 29619 uint32 options, 29620 uint8 port, 29621 int len, 29622 uint8 *data, 29623 uint32 raw_data_buf_size, 29624 uint8 *raw_data, 29625 uint32 *raw_data_size) 29626 { 29627 int rv = BCM_E_UNAVAIL; 29628 #ifdef BCM_INSTRUMENTATION_SUPPORT 29629 #if defined(BCM_MAVERICK2_SUPPORT) 29630 if (SOC_IS_MAVERICK2(unit) && (!soc_property_get(unit, spn_IPEP_CLOCK_GATING_DISABLE, 0))) { 29631 LOG_ERROR(BSL_LS_BCM_COMMON, 29632 (BSL_META_U(unit, 29633 "\n Visibility cannot be used with IPEP clock gating enabled! Set ipep_clock_gating_disable=1\n"))); 29634 return BCM_E_CONFIG; 29635 } 29636 #endif 29637 rv = _bcm_esw_pkt_trace_raw_data_get(unit, 29638 options, port, 29639 len, data, 29640 raw_data_buf_size, 29641 raw_data, 29642 raw_data_size); 29643 #endif 29644 return rv; 29645 } 29646 29647 #if defined(BCM_OLP_SUPPORT) 29648 29649 #define DGLP_MODULE_ID_MASK 0x7f80 29650 #define DGLP_PORT_NO_MASK 0x7f 29651 #define DGLP_MODULE_ID_SHIFT_BITS 7 29652 #define DGLP_LAG_ID_INDICATOR_SHIFT_BITS 15 29653 29654 STATIC int 29655 _bcm_switch_olp_empty_slot_get(int unit, int *Index) 29656 { 29657 egr_olp_dgpp_config_entry_t eolp_dgpp_cfg; 29658 int index = 0; 29659 int max_entries = 0; 29660 soc_field_t field; 29661 bcm_mac_t mac; 29662 29663 max_entries = soc_mem_index_count(unit, EGR_OLP_DGPP_CONFIGm); 29664 29665 for (; index < max_entries; index++) { 29666 SOC_IF_ERROR_RETURN( 29667 READ_EGR_OLP_DGPP_CONFIGm(unit, MEM_BLOCK_ANY, 29668 index, &eolp_dgpp_cfg)); 29669 29670 if (SOC_MEM_FIELD_VALID(unit, EGR_OLP_DGPP_CONFIGm, VALIDf)) { 29671 field = soc_mem_field32_get(unit, EGR_OLP_DGPP_CONFIGm, 29672 &eolp_dgpp_cfg, VALIDf); 29673 if(!field) { 29674 *Index = index; 29675 return BCM_E_NONE; 29676 } 29677 continue; 29678 } 29679 soc_mem_mac_addr_get(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, 29680 MACDAf, mac); 29681 29682 if (BCM_MAC_IS_ZERO(mac)) { 29683 *Index = index; 29684 return BCM_E_NONE; 29685 } 29686 } /* end of for */ 29687 return BCM_E_FULL; 29688 } 29689 29690 int _bcm_switch_olp_dglp_get(int unit, int dglp, bcm_mac_t *mac,int *Index) 29691 { 29692 egr_olp_dgpp_config_entry_t eolp_dgpp_cfg; 29693 int index = 0; 29694 int max_entries = 0; 29695 soc_field_t field; 29696 29697 max_entries = soc_mem_index_count(unit, EGR_OLP_DGPP_CONFIGm); 29698 29699 for (; index < max_entries; index++) { 29700 SOC_IF_ERROR_RETURN( 29701 READ_EGR_OLP_DGPP_CONFIGm(unit, MEM_BLOCK_ANY, 29702 index, &eolp_dgpp_cfg)); 29703 29704 if (SOC_MEM_FIELD_VALID(unit, EGR_OLP_DGPP_CONFIGm, VALIDf)) { 29705 field = soc_mem_field32_get(unit, EGR_OLP_DGPP_CONFIGm, 29706 &eolp_dgpp_cfg, VALIDf); 29707 if(!field) { 29708 continue; 29709 } 29710 } 29711 field = soc_mem_field32_get(unit, EGR_OLP_DGPP_CONFIGm, 29712 &eolp_dgpp_cfg, DGLPf); 29713 if (field == dglp) { 29714 soc_mem_mac_addr_get(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, 29715 MACDAf, *mac); 29716 *Index = index; 29717 29718 if (dglp == 0) { 29719 /* CPU port 29720 Check if its a zero mac. If yes, dont return BCM_E_NONE */ 29721 if (!BCM_MAC_IS_ZERO(*mac)) { 29722 return BCM_E_NONE; 29723 } 29724 } else { 29725 return BCM_E_NONE; 29726 } 29727 } 29728 } /* end of for */ 29729 return BCM_E_NOT_FOUND; 29730 } 29731 29732 int _bcm_switch_olp_port_mac_get(int unit, bcm_port_t port, bcm_mac_t *mac) 29733 { 29734 int dglp; 29735 int rv = BCM_E_NONE; 29736 int index; 29737 bcm_module_t modid; 29738 29739 BCM_IF_ERROR_RETURN(bcm_esw_stk_my_modid_get(unit, &modid)); 29740 29741 dglp = port + (modid << DGLP_MODULE_ID_SHIFT_BITS); 29742 rv = _bcm_switch_olp_dglp_get(unit, dglp, mac, &index); 29743 29744 return rv; 29745 } 29746 29747 #endif /* BCM_OLP_SUPPORT */ 29748 /* 29749 * This API configures MAC address which is used by BCM device as 29750 * destination MAC address 29751 * of L2 header sent towards OLP from BCM device 29752 */ 29753 int bcm_esw_switch_olp_l2_addr_add( 29754 int unit, 29755 uint32 options, 29756 bcm_switch_olp_l2_addr_t *l2_addr) 29757 { 29758 #if defined(BCM_OLP_SUPPORT) 29759 egr_olp_dgpp_config_entry_t eolp_dgpp_cfg; 29760 bcm_module_t module_id = 0; 29761 bcm_module_t my_modid; 29762 bcm_port_t port_id; 29763 bcm_trunk_t trunk_id = BCM_TRUNK_INVALID; 29764 int local_id; 29765 int dglp = 0; 29766 uint32 rval; 29767 bcm_mac_t old_mac = { 0, 0, 0, 0, 0, 0}; 29768 int index; 29769 29770 if(l2_addr == NULL) { 29771 return BCM_E_PARAM; 29772 } 29773 29774 if (soc_feature(unit, soc_feature_olp)) { 29775 if (_BCM_SWITCH_OLP_APIV(unit) == _BCM_SWITCH_OLP_L2_STATION_API) { 29776 LOG_VERBOSE(BSL_LS_BCM_COMMON, 29777 (BSL_META_U(unit, 29778 "use bcm_l2_station_xxx API\n"))); 29779 return BCM_E_UNAVAIL; 29780 } 29781 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_TRUE_API); 29782 29783 BCM_IF_ERROR_RETURN(bcm_esw_stk_my_modid_get(unit, &my_modid)); 29784 29785 if (BCM_GPORT_IS_SET(l2_addr->port)) { 29786 SOC_IF_ERROR_RETURN(_bcm_esw_gport_resolve(unit, l2_addr->port, &module_id, 29787 &port_id, &trunk_id, &local_id)); 29788 if (BCM_GPORT_IS_TRUNK(l2_addr->port) && (trunk_id != BCM_TRUNK_INVALID)) { 29789 /* Set LAG ID indicator bit */ 29790 dglp |= (1 << DGLP_LAG_ID_INDICATOR_SHIFT_BITS); 29791 dglp |= trunk_id; 29792 #if defined(BCM_KATANA2_SUPPORT) 29793 } else if (SOC_IS_KATANA2(unit) && 29794 (BCM_GPORT_IS_SUBPORT_PORT(l2_addr->port)) && 29795 ((_BCM_KT2_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, l2_addr->port)) || 29796 (_BCM_KT2_GPORT_IS_LINKPHY_SUBPORT_PORT(unit, l2_addr->port)))) { 29797 LOG_ERROR(BSL_LS_BCM_L2, 29798 (BSL_META_U(unit, 29799 "OLP is not allowed on SUBPORT. \ 29800 \n"))); 29801 return BCM_E_PARAM; 29802 #endif 29803 } else { 29804 dglp |= ((module_id << DGLP_MODULE_ID_SHIFT_BITS) + port_id); 29805 } 29806 } else { 29807 port_id = l2_addr->port; 29808 dglp |= ((my_modid << DGLP_MODULE_ID_SHIFT_BITS) + l2_addr->port); 29809 } 29810 if (!soc_feature(unit, soc_feature_cpu_as_olp)) { 29811 if (IS_CPU_PORT(unit, port_id)) { 29812 LOG_ERROR(BSL_LS_BCM_L2, 29813 (BSL_META_U(unit, 29814 "_bcm_l2_olp_mac_set: OLP is not allowed on CPU port. \n"))); 29815 return BCM_E_PARAM; 29816 } 29817 } 29818 29819 rval = _bcm_switch_olp_dglp_get(unit, dglp, &old_mac, &index); 29820 29821 if (options & BCM_SWITCH_OLP_L2_ADDR_REPLACE) { 29822 if(rval != BCM_E_NONE) { 29823 LOG_ERROR(BSL_LS_BCM_COMMON, 29824 (BSL_META_U(unit, 29825 "OLP MAC entry not found for this DGLP 0x%x (port 0x%x)\n"), 29826 dglp, l2_addr->port )); 29827 return BCM_E_NOT_FOUND; 29828 } 29829 } else { 29830 if (rval == BCM_E_NONE) { 29831 LOG_ERROR(BSL_LS_BCM_COMMON, 29832 (BSL_META_U(unit, 29833 "OLP MAC is already configured for this DGLP 0x%x (port 0x%x)\n"), 29834 dglp, l2_addr->port )); 29835 return BCM_E_PARAM; 29836 } 29837 BCM_IF_ERROR_RETURN(_bcm_switch_olp_empty_slot_get(unit, &index)); 29838 } 29839 SOC_IF_ERROR_RETURN( 29840 READ_EGR_OLP_DGPP_CONFIGm(unit, MEM_BLOCK_ANY, 29841 index, &eolp_dgpp_cfg)); 29842 29843 soc_mem_mac_addr_set(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, 29844 MACDAf, l2_addr->mac); 29845 29846 soc_mem_field32_set(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, DGLPf, dglp); 29847 if (SOC_MEM_FIELD_VALID(unit, EGR_OLP_DGPP_CONFIGm, VALIDf)) { 29848 soc_mem_field32_set(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, 29849 VALIDf, 1); 29850 } 29851 SOC_IF_ERROR_RETURN(WRITE_EGR_OLP_DGPP_CONFIGm(unit, MEM_BLOCK_ALL, 29852 index, &eolp_dgpp_cfg)); 29853 #if defined (BCM_APACHE_SUPPORT) 29854 if (soc_feature(unit, soc_feature_ep_redirect_v2)) { 29855 SOC_IF_ERROR_RETURN(WRITE_EGR_OLP_DGPP_CONFIG_1m(unit, MEM_BLOCK_ALL, 29856 index, &eolp_dgpp_cfg)); 29857 } 29858 #endif 29859 29860 return BCM_E_NONE; 29861 } 29862 #endif /* BCM_OLP_SUPPORT */ 29863 return BCM_E_UNAVAIL; 29864 } 29865 29866 /* 29867 * This API deletes previously configured MAC address by 29868 * bcm_switch_olp_l2_addr_add 29869 */ 29870 int bcm_esw_switch_olp_l2_addr_delete( 29871 int unit, 29872 bcm_switch_olp_l2_addr_t *l2_addr) 29873 { 29874 #if defined(BCM_OLP_SUPPORT) 29875 if (soc_feature(unit, soc_feature_olp)) { 29876 egr_olp_dgpp_config_entry_t eolp_dgpp_cfg; 29877 bcm_module_t module_id = 0; 29878 bcm_module_t my_modid; 29879 bcm_port_t port_id; 29880 bcm_trunk_t trunk_id = BCM_TRUNK_INVALID; 29881 int local_id; 29882 int dglp = 0; 29883 uint32 rval; 29884 bcm_mac_t zero_mac = { 0, 0, 0, 0, 0, 0}; 29885 bcm_mac_t old_mac = { 0, 0, 0, 0, 0, 0}; 29886 int index; 29887 29888 if(l2_addr == NULL) { 29889 return BCM_E_PARAM; 29890 } 29891 if (_BCM_SWITCH_OLP_APIV(unit) == _BCM_SWITCH_OLP_L2_STATION_API) { 29892 LOG_VERBOSE(BSL_LS_BCM_COMMON, 29893 (BSL_META_U(unit, 29894 "use bcm_l2_station_xxx API\n"))); 29895 return BCM_E_UNAVAIL; 29896 } 29897 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_TRUE_API); 29898 29899 BCM_IF_ERROR_RETURN(bcm_esw_stk_my_modid_get(unit, &my_modid)); 29900 29901 if (BCM_GPORT_IS_SET(l2_addr->port)) { 29902 SOC_IF_ERROR_RETURN(_bcm_esw_gport_resolve(unit, l2_addr->port, &module_id, 29903 &port_id, &trunk_id, &local_id)); 29904 if (BCM_GPORT_IS_TRUNK(l2_addr->port) && (trunk_id != BCM_TRUNK_INVALID)) { 29905 /* Set LAG ID indicator bit */ 29906 dglp |= (1 << DGLP_LAG_ID_INDICATOR_SHIFT_BITS); 29907 #if defined(BCM_KATANA2_SUPPORT) 29908 } else if (SOC_IS_KATANA2(unit) && 29909 (BCM_GPORT_IS_SUBPORT_PORT(l2_addr->port)) && 29910 ((_BCM_KT2_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, l2_addr->port)) || 29911 (_BCM_KT2_GPORT_IS_LINKPHY_SUBPORT_PORT(unit, l2_addr->port)))) { 29912 LOG_ERROR(BSL_LS_BCM_L2, 29913 (BSL_META_U(unit, 29914 "OLP is not allowed on SUBPORT. \ 29915 \n"))); 29916 return BCM_E_PARAM; 29917 #endif 29918 } else { 29919 dglp |= ((module_id << DGLP_MODULE_ID_SHIFT_BITS) + port_id); 29920 } 29921 } else { 29922 port_id = l2_addr->port; 29923 dglp |= ((my_modid << DGLP_MODULE_ID_SHIFT_BITS) + l2_addr->port); 29924 } 29925 if (!SOC_IS_SABER2(unit) && 29926 !soc_feature(unit, soc_feature_fp_based_oam)) { 29927 if (IS_CPU_PORT(unit, port_id)) { 29928 LOG_ERROR(BSL_LS_BCM_L2, 29929 (BSL_META_U(unit, 29930 "_bcm_l2_olp_mac_set: OLP is not allowed on CPU port. \n"))); 29931 return BCM_E_PARAM; 29932 } 29933 } 29934 29935 rval = _bcm_switch_olp_dglp_get(unit, dglp, &old_mac, &index); 29936 29937 if(rval != BCM_E_NONE) { 29938 LOG_ERROR(BSL_LS_BCM_COMMON, 29939 (BSL_META_U(unit, 29940 "OLP MAC entry not found for this DGLP 0x%x (port 0x%x)\n"), 29941 dglp, l2_addr->port )); 29942 return BCM_E_NOT_FOUND; 29943 } 29944 29945 SOC_IF_ERROR_RETURN( 29946 READ_EGR_OLP_DGPP_CONFIGm(unit, MEM_BLOCK_ANY, 29947 index, &eolp_dgpp_cfg)); 29948 29949 soc_mem_mac_addr_set(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, 29950 MACDAf, zero_mac); 29951 29952 soc_mem_field32_set(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, DGLPf, 0); 29953 29954 if (SOC_MEM_FIELD_VALID(unit, EGR_OLP_DGPP_CONFIGm, VALIDf)) { 29955 soc_mem_field32_set(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, 29956 VALIDf, 0); 29957 } 29958 SOC_IF_ERROR_RETURN(WRITE_EGR_OLP_DGPP_CONFIGm(unit, MEM_BLOCK_ALL, 29959 index, &eolp_dgpp_cfg)); 29960 #if defined (BCM_APACHE_SUPPORT) 29961 if (soc_feature(unit, soc_feature_ep_redirect_v2)) { 29962 SOC_IF_ERROR_RETURN( 29963 WRITE_EGR_OLP_DGPP_CONFIG_1m(unit, 29964 MEM_BLOCK_ALL, 29965 index, 29966 &eolp_dgpp_cfg)); 29967 } 29968 #endif 29969 29970 return BCM_E_NONE; 29971 } 29972 #endif /* BCM_OLP_SUPPORT */ 29973 return BCM_E_UNAVAIL; 29974 } 29975 29976 /* 29977 * Get previously configured MAC address of OLP connected to the BCM 29978 * device port 29979 */ 29980 int bcm_esw_switch_olp_l2_addr_get( 29981 int unit, 29982 bcm_switch_olp_l2_addr_t *l2_addr) 29983 { 29984 #if defined(BCM_OLP_SUPPORT) 29985 if (soc_feature(unit, soc_feature_olp)) { 29986 bcm_module_t module_id = 0; 29987 bcm_module_t my_modid; 29988 bcm_port_t port_id; 29989 bcm_trunk_t trunk_id = BCM_TRUNK_INVALID; 29990 int local_id; 29991 int dglp = 0; 29992 uint32 rval; 29993 int index; 29994 29995 if(l2_addr == NULL) { 29996 return BCM_E_PARAM; 29997 } 29998 if (_BCM_SWITCH_OLP_APIV(unit) == _BCM_SWITCH_OLP_L2_STATION_API) { 29999 LOG_VERBOSE(BSL_LS_BCM_COMMON, 30000 (BSL_META_U(unit, 30001 "use bcm_l2_station_xxx API\n"))); 30002 return BCM_E_UNAVAIL; 30003 } 30004 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_TRUE_API); 30005 30006 BCM_IF_ERROR_RETURN(bcm_esw_stk_my_modid_get(unit, &my_modid)); 30007 30008 if (BCM_GPORT_IS_SET(l2_addr->port)) { 30009 SOC_IF_ERROR_RETURN(_bcm_esw_gport_resolve(unit, l2_addr->port, &module_id, 30010 &port_id, &trunk_id, &local_id)); 30011 if (BCM_GPORT_IS_TRUNK(l2_addr->port) && (trunk_id != BCM_TRUNK_INVALID)) { 30012 /* Set LAG ID indicator bit */ 30013 dglp |= (1 << DGLP_LAG_ID_INDICATOR_SHIFT_BITS); 30014 dglp |= trunk_id; 30015 #if defined(BCM_KATANA2_SUPPORT) 30016 } else if (SOC_IS_KATANA2(unit) && 30017 (BCM_GPORT_IS_SUBPORT_PORT(l2_addr->port)) && 30018 ((_BCM_KT2_GPORT_IS_SUBTAG_SUBPORT_PORT(unit, l2_addr->port)) || 30019 (_BCM_KT2_GPORT_IS_LINKPHY_SUBPORT_PORT(unit, l2_addr->port)))) { 30020 LOG_ERROR(BSL_LS_BCM_L2, 30021 (BSL_META_U(unit, 30022 "OLP is not allowed on SUBPORT. \ 30023 \n"))); 30024 return BCM_E_PARAM; 30025 #endif 30026 } else { 30027 dglp |= ((module_id << DGLP_MODULE_ID_SHIFT_BITS) + port_id); 30028 } 30029 } else { 30030 port_id = l2_addr->port; 30031 dglp |= ((my_modid << DGLP_MODULE_ID_SHIFT_BITS) + l2_addr->port); 30032 } 30033 if (!soc_feature(unit, soc_feature_cpu_as_olp)) { 30034 if (IS_CPU_PORT(unit, port_id)) { 30035 LOG_ERROR(BSL_LS_BCM_L2, 30036 (BSL_META_U(unit, 30037 "_bcm_l2_olp_mac_set: OLP is not allowed on CPU port. \n"))); 30038 return BCM_E_PARAM; 30039 } 30040 } 30041 30042 rval = _bcm_switch_olp_dglp_get(unit, dglp, &(l2_addr->mac), &index); 30043 30044 if(rval != BCM_E_NONE) { 30045 LOG_ERROR(BSL_LS_BCM_COMMON, 30046 (BSL_META_U(unit, 30047 "OLP MAC entry not found for this DGLP 0x%x (port 0x%x)\n"), 30048 dglp, l2_addr->port )); 30049 return BCM_E_NOT_FOUND; 30050 } 30051 return BCM_E_NONE; 30052 } 30053 #endif /* BCM_OLP_SUPPORT */ 30054 return BCM_E_UNAVAIL; 30055 } 30056 30057 /* Traverse configured OLP MAC address database */ 30058 int bcm_esw_switch_olp_l2_addr_traverse( 30059 int unit, 30060 bcm_switch_olp_l2_addr_traverse_cb cb_fn, 30061 void *user_data) 30062 { 30063 #if defined(BCM_OLP_SUPPORT) 30064 if (soc_feature(unit, soc_feature_olp)) { 30065 egr_olp_dgpp_config_entry_t eolp_dgpp_cfg; 30066 int index = 0; 30067 int max_entries = 0; 30068 soc_field_t field; 30069 int rv = BCM_E_NONE; 30070 bcm_switch_olp_l2_addr_t l2_addr; 30071 int dglp, module_id, port_id, lag; 30072 30073 if (_BCM_SWITCH_OLP_APIV(unit) == _BCM_SWITCH_OLP_L2_STATION_API) { 30074 LOG_VERBOSE(BSL_LS_BCM_COMMON, 30075 (BSL_META_U(unit, 30076 "use bcm_l2_station_xxx API\n"))); 30077 return BCM_E_UNAVAIL; 30078 } 30079 _BCM_SWITCH_OLP_APIV_SET(unit, _BCM_SWITCH_OLP_TRUE_API); 30080 30081 max_entries = soc_mem_index_count(unit, EGR_OLP_DGPP_CONFIGm); 30082 30083 for (; index < max_entries; index++) { 30084 bcm_switch_olp_l2_addr_t_init(&l2_addr); 30085 30086 SOC_IF_ERROR_RETURN( 30087 READ_EGR_OLP_DGPP_CONFIGm(unit, MEM_BLOCK_ANY, 30088 index, &eolp_dgpp_cfg)); 30089 30090 if (SOC_MEM_FIELD_VALID(unit, EGR_OLP_DGPP_CONFIGm, VALIDf)) { 30091 field = soc_mem_field32_get(unit, EGR_OLP_DGPP_CONFIGm, 30092 &eolp_dgpp_cfg, VALIDf); 30093 if(!field) { 30094 continue; 30095 } 30096 } 30097 soc_mem_mac_addr_get(unit, EGR_OLP_DGPP_CONFIGm, &eolp_dgpp_cfg, 30098 MACDAf, l2_addr.mac); 30099 30100 /* Check if its a zero mac. If yes, its invalid entry */ 30101 if (BCM_MAC_IS_ZERO(l2_addr.mac)) { 30102 continue; 30103 } 30104 dglp = soc_mem_field32_get(unit, EGR_OLP_DGPP_CONFIGm, 30105 &eolp_dgpp_cfg, DGLPf); 30106 30107 /* Convert dglp to port */ 30108 module_id = (dglp & DGLP_MODULE_ID_MASK) >> DGLP_MODULE_ID_SHIFT_BITS; 30109 port_id = dglp & DGLP_PORT_NO_MASK; 30110 lag = ((dglp >> DGLP_LAG_ID_INDICATOR_SHIFT_BITS) & 0x1) ? 1 : 0; 30111 30112 if (lag) { 30113 SOC_GPORT_TRUNK_SET(l2_addr.port, dglp & (~(1 << DGLP_LAG_ID_INDICATOR_SHIFT_BITS))); 30114 } else { 30115 SOC_GPORT_MODPORT_SET(l2_addr.port, module_id, port_id); 30116 } 30117 30118 rv = cb_fn(unit, &l2_addr, user_data); 30119 30120 if (BCM_FAILURE(rv)) { 30121 LOG_DEBUG(BSL_LS_BCM_COMMON, 30122 (BSL_META_U(unit, 30123 "OLP (unit %d) Info: Traverse (idx=%d) entry failed.\n"), 30124 unit, index)); 30125 break; 30126 } 30127 } /* end of for */ 30128 return rv; 30129 } 30130 #endif /* BCM_OLP_SUPPORT */ 30131 return BCM_E_UNAVAIL; 30132 } 30133 30134 int _bcm_switch_olp_l2_addr_delete_all_cb( 30135 int unit, 30136 bcm_switch_olp_l2_addr_t *l2_addr, 30137 void *user_data) 30138 { 30139 int rv = BCM_E_NONE; 30140 #if defined(BCM_OLP_SUPPORT) 30141 rv = bcm_esw_switch_olp_l2_addr_delete( unit, l2_addr); 30142 #endif 30143 return rv; 30144 } 30145 30146 /* 30147 * Delete ALL previously configured MAC address of OLP by 30148 * bcm_switch_olp_l2_addr_add() API 30149 */ 30150 int bcm_esw_switch_olp_l2_addr_delete_all(int unit) 30151 { 30152 #if defined(BCM_OLP_SUPPORT) 30153 if (soc_feature(unit, soc_feature_olp)) { 30154 30155 if (_BCM_SWITCH_OLP_APIV(unit) == _BCM_SWITCH_OLP_L2_STATION_API) { 30156 LOG_VERBOSE(BSL_LS_BCM_COMMON, 30157 (BSL_META_U(unit, 30158 "use bcm_l2_station_xxx API\n"))); 30159 return BCM_E_UNAVAIL; 30160 } 30161 return bcm_esw_switch_olp_l2_addr_traverse( unit, 30162 _bcm_switch_olp_l2_addr_delete_all_cb, NULL); 30163 } 30164 #endif 30165 return BCM_E_UNAVAIL; 30166 } 30167 30168 #ifdef BCM_HURRICANE3_SUPPORT 30169 int 30170 bcmi_esw_switch_capwap_payload_outer_tpid_add( 30171 int unit, 30172 uint16 tpid_value) 30173 { 30174 int rv = BCM_E_NONE; 30175 int tpid_enable, index; 30176 int remove_tpid = FALSE; 30177 uint32 reg_val; 30178 30179 _bcm_fb2_outer_tpid_tab_lock(unit); 30180 30181 /* Check if this tpid value is existed */ 30182 rv = READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val); 30183 if (BCM_FAILURE(rv)) { 30184 _bcm_fb2_outer_tpid_tab_unlock(unit); 30185 return rv; 30186 } 30187 30188 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30189 reg_val, PAYLOAD_OUTER_TPID_ENABLEf); 30190 30191 rv = _bcm_fb2_outer_tpid_lkup(unit, tpid_value, &index); 30192 if (BCM_FAILURE(rv) && (rv != BCM_E_NOT_FOUND)) { 30193 _bcm_fb2_outer_tpid_tab_unlock(unit); 30194 return rv; 30195 } 30196 30197 if (rv == BCM_E_NOT_FOUND || !(tpid_enable & (1 << index))) { 30198 rv = _bcm_fb2_outer_tpid_entry_add(unit, tpid_value, &index); 30199 if (BCM_FAILURE(rv)) { 30200 _bcm_fb2_outer_tpid_tab_unlock(unit); 30201 return rv; 30202 } 30203 remove_tpid = TRUE; 30204 } 30205 30206 tpid_enable |= (1 << index); 30207 soc_reg_field_set(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30208 ®_val, PAYLOAD_OUTER_TPID_ENABLEf, tpid_enable); 30209 rv = WRITE_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, reg_val); 30210 if (BCM_FAILURE(rv)) { 30211 if (remove_tpid) { 30212 _bcm_fb2_outer_tpid_entry_delete(unit, index); 30213 } 30214 } 30215 30216 _bcm_fb2_outer_tpid_tab_unlock(unit); 30217 30218 return (rv); 30219 30220 } 30221 30222 int 30223 bcmi_esw_switch_capwap_payload_inner_tpid_add( 30224 int unit, 30225 uint16 tpid_value) 30226 { 30227 int rv = BCM_E_NONE; 30228 int tpid_enable; 30229 uint32 reg_val, tpid_rval; 30230 30231 /* Check if this tpid value is existed */ 30232 BCM_IF_ERROR_RETURN(READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val)); 30233 30234 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30235 reg_val, PAYLOAD_INNER_TPID_ENABLEf); 30236 30237 BCM_IF_ERROR_RETURN(READ_VLAN_CTRLr(unit, &tpid_rval)); 30238 if (tpid_enable) { 30239 rv = (BCM_E_RESOURCE); 30240 } else { 30241 /* Set new TPID value */ 30242 soc_reg_field_set(unit, VLAN_CTRLr, &tpid_rval, 30243 INNER_TPIDf, tpid_value); 30244 BCM_IF_ERROR_RETURN(WRITE_VLAN_CTRLr(unit, tpid_rval)); 30245 30246 soc_reg_field_set(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30247 ®_val, PAYLOAD_INNER_TPID_ENABLEf, 1); 30248 BCM_IF_ERROR_RETURN( 30249 WRITE_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, reg_val)); 30250 } 30251 30252 return (rv); 30253 30254 } 30255 30256 30257 int 30258 bcmi_esw_switch_capwap_payload_outer_tpid_delete( 30259 int unit, 30260 uint16 tpid_value) 30261 { 30262 int rv = BCM_E_NONE; 30263 int index, tpid_enable; 30264 uint32 reg_val; 30265 30266 _bcm_fb2_outer_tpid_tab_lock(unit); 30267 30268 rv = _bcm_fb2_outer_tpid_lkup(unit, tpid_value, &index); 30269 if (BCM_FAILURE(rv)) { 30270 _bcm_fb2_outer_tpid_tab_unlock(unit); 30271 return rv; 30272 } 30273 30274 rv = READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val); 30275 if (BCM_FAILURE(rv)) { 30276 _bcm_fb2_outer_tpid_tab_unlock(unit); 30277 return rv; 30278 } 30279 30280 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30281 reg_val, PAYLOAD_OUTER_TPID_ENABLEf); 30282 30283 if (tpid_enable & (1 << index)) { 30284 tpid_enable &= ~(1 << index); 30285 soc_reg_field_set(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30286 ®_val, PAYLOAD_OUTER_TPID_ENABLEf, tpid_enable); 30287 rv = WRITE_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, reg_val); 30288 } else { 30289 rv = BCM_E_NOT_FOUND; 30290 } 30291 if (BCM_FAILURE(rv)) { 30292 _bcm_fb2_outer_tpid_tab_unlock(unit); 30293 return rv; 30294 } 30295 30296 rv = _bcm_fb2_outer_tpid_entry_delete(unit, index); 30297 _bcm_fb2_outer_tpid_tab_unlock(unit); 30298 30299 return (rv); 30300 30301 } 30302 30303 int 30304 bcmi_esw_switch_capwap_payload_inner_tpid_delete( 30305 int unit, 30306 uint16 tpid_value) 30307 { 30308 int rv = BCM_E_NONE; 30309 int tpid_enable; 30310 uint32 reg_val, tpid_rval, tpid; 30311 30312 /* Check if this tpid value is existed */ 30313 BCM_IF_ERROR_RETURN(READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val)); 30314 30315 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30316 reg_val, PAYLOAD_INNER_TPID_ENABLEf); 30317 30318 30319 if (tpid_enable) { 30320 30321 BCM_IF_ERROR_RETURN(READ_VLAN_CTRLr(unit, &tpid_rval)); 30322 30323 /* Get TPID value */ 30324 tpid = soc_reg_field_get(unit, VLAN_CTRLr, tpid_rval, 30325 INNER_TPIDf); 30326 30327 if (tpid_value == tpid) { 30328 /* Disable */ 30329 soc_reg_field_set(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30330 ®_val, PAYLOAD_INNER_TPID_ENABLEf, 0); 30331 BCM_IF_ERROR_RETURN( 30332 WRITE_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, reg_val)); 30333 } 30334 } 30335 30336 return (rv); 30337 30338 } 30339 30340 int 30341 bcmi_esw_switch_capwap_payload_outer_tpid_delete_all(int unit) 30342 { 30343 int rv = BCM_E_NONE; 30344 int tpid_enable, tpid_index; 30345 uint32 reg_val; 30346 30347 _bcm_fb2_outer_tpid_tab_lock(unit); 30348 30349 rv = READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val); 30350 if (BCM_FAILURE(rv)) { 30351 _bcm_fb2_outer_tpid_tab_unlock(unit); 30352 return rv; 30353 } 30354 30355 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30356 reg_val, PAYLOAD_OUTER_TPID_ENABLEf); 30357 30358 soc_reg_field_set(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30359 ®_val, PAYLOAD_OUTER_TPID_ENABLEf, 0); 30360 rv = WRITE_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, reg_val); 30361 if (BCM_FAILURE(rv)) { 30362 _bcm_fb2_outer_tpid_tab_unlock(unit); 30363 return rv; 30364 } 30365 30366 tpid_index = 0; 30367 while (tpid_enable) { 30368 if (tpid_enable & 1) { 30369 rv = _bcm_fb2_outer_tpid_entry_delete(unit, tpid_index); 30370 if (BCM_FAILURE(rv)) { 30371 _bcm_fb2_outer_tpid_tab_unlock(unit); 30372 return rv; 30373 } 30374 } 30375 tpid_enable = tpid_enable >> 1; 30376 tpid_index++; 30377 } 30378 30379 _bcm_fb2_outer_tpid_tab_unlock(unit); 30380 return rv; 30381 30382 } 30383 30384 int 30385 bcmi_esw_switch_capwap_payload_inner_tpid_delete_all(int unit) 30386 { 30387 int rv = BCM_E_NONE; 30388 uint32 reg_val; 30389 30390 30391 rv = READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val); 30392 if (BCM_FAILURE(rv)) { 30393 return rv; 30394 } 30395 30396 soc_reg_field_set(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30397 ®_val, PAYLOAD_OUTER_TPID_ENABLEf, 0); 30398 rv = WRITE_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, reg_val); 30399 if (BCM_FAILURE(rv)) { 30400 return rv; 30401 } 30402 30403 return rv; 30404 30405 } 30406 30407 30408 int 30409 bcmi_esw_switch_capwap_payload_outer_tpid_get( 30410 int unit, 30411 uint16 *tpid_value) 30412 { 30413 int tpid_enable, tpid_index; 30414 uint32 reg_val; 30415 30416 BCM_IF_ERROR_RETURN( 30417 READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val)); 30418 30419 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30420 reg_val, PAYLOAD_OUTER_TPID_ENABLEf); 30421 30422 tpid_index = 0; 30423 while (tpid_enable) { 30424 if (tpid_enable & 1) { 30425 return _bcm_fb2_outer_tpid_entry_get(unit, tpid_value, tpid_index); 30426 } 30427 tpid_enable = tpid_enable >> 1; 30428 tpid_index++; 30429 } 30430 30431 return BCM_E_NOT_FOUND; 30432 30433 } 30434 30435 int 30436 bcmi_esw_switch_capwap_payload_inner_tpid_get( 30437 int unit, 30438 uint16 *tpid_value) 30439 { 30440 int rv = BCM_E_NONE; 30441 int tpid_enable; 30442 uint32 reg_val; 30443 30444 /* Check if this tpid value is existed */ 30445 BCM_IF_ERROR_RETURN(READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val)); 30446 30447 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 30448 reg_val, PAYLOAD_INNER_TPID_ENABLEf); 30449 30450 if (tpid_enable) { 30451 BCM_IF_ERROR_RETURN(READ_VLAN_CTRLr(unit, ®_val)); 30452 /* Set new TPID value */ 30453 *tpid_value = soc_reg_field_get(unit, VLAN_CTRLr, reg_val, 30454 INNER_TPIDf); 30455 return rv; 30456 } 30457 30458 return BCM_E_NOT_FOUND; 30459 30460 } 30461 30462 30463 #endif /* BCM_HURRICANE3_SUPPORT */ 30464 30465 #if defined(BCM_GREYHOUND2_SUPPORT) 30466 /* 30467 * Function: 30468 * bcmi_esw_switch_vxlan_payload_tpid_add 30469 * Purpose: 30470 * Add a global TPID for VXLAN payload (Inner/Outer). 30471 * Parameters: 30472 * unit - (IN) Unit number. 30473 * tpid_info - (IN) TPID info includes key: {tpid_type, tpid_value} 30474 * and Associated value(s): {flags, color}. 30475 * Returns: 30476 * BCM_E_xxx 30477 * Notes: 30478 */ 30479 int 30480 bcmi_esw_switch_vxlan_payload_tpid_add( 30481 int unit, 30482 bcm_switch_tpid_info_t *tpid_info) 30483 { 30484 int rv = BCM_E_NONE; /* Operation return status. */ 30485 int tpid_index = 0; 30486 uint64 reg_val64; 30487 uint32 reg_val = 0, tpid_value = 0; 30488 uint8 tpid_enable = 0; 30489 30490 if (NULL == tpid_info) { 30491 return BCM_E_PARAM; 30492 } 30493 30494 COMPILER_64_ZERO(reg_val64); 30495 30496 if (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter) { 30497 /* Add Outer TPID value (index = 0 ~ 3) */ 30498 BCM_IF_ERROR_RETURN( 30499 _bcm_fb2_outer_tpid_entry_add(unit, tpid_info->tpid_value, &tpid_index)); 30500 30501 /* VXLAN Payload Outer TPID enable bits[0~3] */ 30502 BCM_IF_ERROR_RETURN( 30503 READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 30504 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 30505 reg_val64, PAYLOAD_OUTER_TPID_ENABLEf); 30506 30507 if (tpid_enable & (0x1 << tpid_index)) { 30508 BCM_IF_ERROR_RETURN( 30509 _bcm_fb2_outer_tpid_entry_delete(unit, tpid_index)); 30510 return BCM_E_EXISTS; 30511 } else { 30512 tpid_enable |= (0x1 << tpid_index); 30513 soc_reg64_field32_set(unit, ING_VXLAN_CONTROLr, 30514 ®_val64, PAYLOAD_OUTER_TPID_ENABLEf, tpid_enable); 30515 rv = WRITE_ING_VXLAN_CONTROLr(unit, reg_val64); 30516 } 30517 } else if (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadInner) { 30518 /* Current Inner TPID value */ 30519 BCM_IF_ERROR_RETURN( 30520 READ_VLAN_CTRLr(unit, ®_val)); 30521 tpid_value = soc_reg_field_get(unit, VLAN_CTRLr, 30522 reg_val, INNER_TPIDf); 30523 30524 /* VXLAN Payload Inner TPID enable bit[0] */ 30525 BCM_IF_ERROR_RETURN( 30526 READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 30527 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 30528 reg_val64, PAYLOAD_INNER_TPID_ENABLEf); 30529 30530 if (tpid_enable) { 30531 if (tpid_info->tpid_value == tpid_value) { 30532 return BCM_E_EXISTS; 30533 } else { 30534 return BCM_E_RESOURCE; 30535 } 30536 } else { 30537 /* 30538 * Use corresponding TPID to parse inner VLAN programmed in 30539 * INNER_TPID in VLAN_CTRL. 30540 */ 30541 if ((tpid_info->tpid_value == tpid_value) && (tpid_value != 0)) { 30542 tpid_enable = 0x1; 30543 soc_reg64_field32_set(unit, ING_VXLAN_CONTROLr, 30544 ®_val64, PAYLOAD_INNER_TPID_ENABLEf, tpid_enable); 30545 rv = WRITE_ING_VXLAN_CONTROLr(unit, reg_val64); 30546 } else { 30547 return BCM_E_RESOURCE; 30548 } 30549 } 30550 } else { 30551 return BCM_E_PARAM; 30552 } 30553 30554 return rv; 30555 } 30556 30557 /* 30558 * Function: 30559 * bcmi_esw_switch_vxlan_payload_tpid_delete 30560 * Purpose: 30561 * Delete a global TPID for VXLAN payload (Inner/Outer). 30562 * Parameters: 30563 * unit - (IN) Unit number. 30564 * tpid_info - (IN) TPID info includes key: {tpid_type, tpid_value} 30565 * and Associated value(s): {flags, color}. 30566 * Returns: 30567 * BCM_E_xxx 30568 * Notes: 30569 */ 30570 int 30571 bcmi_esw_switch_vxlan_payload_tpid_delete( 30572 int unit, 30573 bcm_switch_tpid_info_t *tpid_info) 30574 { 30575 int rv = BCM_E_NONE; /* Operation return status. */ 30576 int tpid_index = 0; 30577 uint64 reg_val64; 30578 uint32 reg_val = 0, tpid_value = 0; 30579 uint8 tpid_enable = 0; 30580 30581 if (NULL == tpid_info) { 30582 return BCM_E_PARAM; 30583 } 30584 30585 COMPILER_64_ZERO(reg_val64); 30586 30587 if (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter) { 30588 /* Lookup Outer TPID value (index = 0 ~ 3) */ 30589 BCM_IF_ERROR_RETURN( 30590 _bcm_fb2_outer_tpid_lkup(unit, tpid_info->tpid_value, &tpid_index)); 30591 30592 /* VXLAN Payload Outer TPID enable bits[0~3] */ 30593 BCM_IF_ERROR_RETURN( 30594 READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 30595 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 30596 reg_val64, PAYLOAD_OUTER_TPID_ENABLEf); 30597 30598 if (tpid_enable & (0x1 << tpid_index)) { 30599 BCM_IF_ERROR_RETURN( 30600 _bcm_fb2_outer_tpid_entry_delete(unit, tpid_index)); 30601 30602 tpid_enable &= ~(0x1 << tpid_index); 30603 soc_reg64_field32_set(unit, ING_VXLAN_CONTROLr, 30604 ®_val64, PAYLOAD_OUTER_TPID_ENABLEf, tpid_enable); 30605 rv = WRITE_ING_VXLAN_CONTROLr(unit, reg_val64); 30606 } else { 30607 return BCM_E_NOT_FOUND; 30608 } 30609 } else if (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadInner) { 30610 /* Current Inner TPID value */ 30611 BCM_IF_ERROR_RETURN( 30612 READ_VLAN_CTRLr(unit, ®_val)); 30613 tpid_value = soc_reg_field_get(unit, VLAN_CTRLr, 30614 reg_val, INNER_TPIDf); 30615 30616 /* VXLAN Payload Inner TPID enable bit[0] */ 30617 BCM_IF_ERROR_RETURN( 30618 READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 30619 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 30620 reg_val64, PAYLOAD_INNER_TPID_ENABLEf); 30621 30622 if (!tpid_enable || (tpid_info->tpid_value != tpid_value)) { 30623 return BCM_E_NOT_FOUND; 30624 } 30625 30626 tpid_enable = 0x0; 30627 soc_reg64_field32_set(unit, ING_VXLAN_CONTROLr, 30628 ®_val64, PAYLOAD_INNER_TPID_ENABLEf, tpid_enable); 30629 rv = WRITE_ING_VXLAN_CONTROLr(unit, reg_val64); 30630 } else { 30631 return BCM_E_PARAM; 30632 } 30633 30634 return rv; 30635 } 30636 30637 /* 30638 * Function: 30639 * bcmi_esw_switch_vxlan_payload_tpid_delete_all 30640 * Purpose: 30641 * Delete all global TPIDs for VXLAN payload (Inner/Outer). 30642 * Parameters: 30643 * unit - (IN) Unit number. 30644 * Returns: 30645 * BCM_E_xxx 30646 * Notes: 30647 */ 30648 int 30649 bcmi_esw_switch_vxlan_payload_tpid_delete_all(int unit) 30650 { 30651 int rv = BCM_E_NONE; /* Operation return status. */ 30652 int tpid_index; 30653 uint64 reg_val64; 30654 uint8 tpid_enable = 0; 30655 30656 COMPILER_64_ZERO(reg_val64); 30657 30658 /* Delete all TPID for Outer (bits[0~3]) */ 30659 BCM_IF_ERROR_RETURN( 30660 READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 30661 30662 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 30663 reg_val64, PAYLOAD_OUTER_TPID_ENABLEf); 30664 30665 tpid_index = 0; 30666 while (tpid_enable) { 30667 if (tpid_enable & 0x1) { 30668 BCM_IF_ERROR_RETURN( 30669 _bcm_fb2_outer_tpid_entry_delete(unit, tpid_index)); 30670 } 30671 tpid_enable >>= 1; 30672 tpid_index++; 30673 } 30674 30675 soc_reg64_field32_set(unit, ING_VXLAN_CONTROLr, 30676 ®_val64, PAYLOAD_OUTER_TPID_ENABLEf, 0); 30677 30678 /* Delete TPID for Inner (bits[0]) */ 30679 soc_reg64_field32_set(unit, ING_VXLAN_CONTROLr, 30680 ®_val64, PAYLOAD_INNER_TPID_ENABLEf, 0); 30681 30682 rv = WRITE_ING_VXLAN_CONTROLr(unit, reg_val64); 30683 30684 return rv; 30685 } 30686 #endif /* BCM_GREYHOUND2_SUPPORT */ 30687 30688 /* 30689 * Function: 30690 * bcm_esw_switch_tpid_add 30691 * Purpose: 30692 * Add a global TPID. 30693 * BCM5616x family of devices support 5 global TPIDs for 30694 * identifying the outer and inner tags in CAPWAP wirless payload. Four 30695 * global TPIDs are for outer TPID parsing and one global TPID for inner 30696 * TPID parsing in CAPWAP wireless payload. 30697 * The device supports only one global TPID which is from the 30698 * ingress inner TPID matching register for identifying the inner tag in 30699 * L2 Tunnel payload. The global TPID is initialized to 0x8100 by default. 30700 * Old global L2 Tunnel TPID must be deleted before adding a new one. 30701 * Parameters: 30702 * unit - (IN) Unit number. 30703 * options - (IN) Future expansion i.e, REPLACE option. 30704 * tpid_info - (IN) TPID info includes key: {tpid_type, tpid_value} 30705 * and Associated value(s): {flags, color}. 30706 * Returns: 30707 * BCM_E_xxx 30708 * Notes: 30709 */ 30710 30711 int 30712 bcm_esw_switch_tpid_add(int unit, uint32 options, 30713 bcm_switch_tpid_info_t *tpid_info) 30714 { 30715 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 30716 30717 if (tpid_info == NULL) { 30718 return (BCM_E_PARAM); 30719 } 30720 #ifdef BCM_TOMAHAWK2_SUPPORT 30721 if (SOC_IS_TOMAHAWK2(unit) && 30722 (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter || 30723 tpid_info->tpid_type == bcmTpidTypeL2grePayloadOuter)) { 30724 return BCM_E_UNAVAIL; 30725 } 30726 #endif /* BCM_TOMAHAWK2_SUPPORT */ 30727 #ifdef BCM_HURRICANE3_SUPPORT 30728 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 30729 if (tpid_info->tpid_type == bcmTpidTypeCapwapPayloadOuter) { 30730 rv = bcmi_esw_switch_capwap_payload_outer_tpid_add(unit, 30731 tpid_info->tpid_value); 30732 if (BCM_FAILURE(rv)) { 30733 return rv; 30734 } 30735 } else if (tpid_info->tpid_type == bcmTpidTypeCapwapPayloadInner) { 30736 rv = bcmi_esw_switch_capwap_payload_inner_tpid_add(unit, 30737 tpid_info->tpid_value); 30738 if (BCM_FAILURE(rv)) { 30739 return rv; 30740 } 30741 } 30742 } 30743 #endif /* BCM_HURRICANE3_SUPPORT */ 30744 30745 #if defined(BCM_GREYHOUND2_SUPPORT) 30746 if (soc_feature(unit, soc_feature_vxlan_lite)) { 30747 if ((tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter) || 30748 (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadInner)) { 30749 rv = bcmi_esw_switch_vxlan_payload_tpid_add(unit, tpid_info); 30750 if (BCM_FAILURE(rv)) { 30751 return rv; 30752 } 30753 } 30754 } 30755 #endif /* BCM_GREYHOUND2_SUPPORT */ 30756 30757 #ifdef BCM_TRIUMPH_SUPPORT 30758 if (soc_feature(unit, soc_feature_ing_l2tunnel_tpid_parser) && 30759 (tpid_info->tpid_type == bcmTpidTypeL2TunnelPayloadInner)) { 30760 uint32 tpid_value; 30761 30762 BCM_IF_ERROR_RETURN(READ_ING_MPLS_INNER_TPIDr(unit, &tpid_value)); 30763 if (0 != tpid_value) { 30764 return BCM_E_RESOURCE; 30765 } 30766 30767 rv = WRITE_ING_MPLS_INNER_TPIDr(unit, tpid_info->tpid_value); 30768 } 30769 #endif /* BCM_TRIUMPH_SUPPORT */ 30770 30771 #ifdef BCM_TOMAHAWK_SUPPORT 30772 if (soc_feature(unit, soc_feature_l2_tunnel_transit_payload_tpid_parser)) { 30773 int tpid_index = 0; 30774 soc_field_t tpid_enable_field = INVALIDf; 30775 uint32 l2_tunnel_parse_control = 0; 30776 uint8 tpid_enable = 0; 30777 30778 if (tpid_info->tpid_type == bcmTpidTypeMimPayloadOuter) { 30779 tpid_enable_field = MIM_PAYLOAD_TPID_ENABLEf; 30780 } else if (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter) { 30781 tpid_enable_field = VXLAN_PAYLOAD_TPID_ENABLEf; 30782 } else if (tpid_info->tpid_type == bcmTpidTypeL2grePayloadOuter) { 30783 tpid_enable_field = L2GRE_PAYLOAD_TPID_ENABLEf; 30784 } 30785 30786 if (tpid_enable_field != INVALIDf) { 30787 BCM_IF_ERROR_RETURN( 30788 _bcm_fb2_outer_tpid_entry_add(unit, tpid_info->tpid_value, 30789 &tpid_index)); 30790 BCM_IF_ERROR_RETURN( 30791 READ_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 30792 &l2_tunnel_parse_control)); 30793 tpid_enable = soc_reg_field_get(unit, 30794 ING_L2_TUNNEL_PARSE_CONTROLr, 30795 l2_tunnel_parse_control, 30796 tpid_enable_field); 30797 if (tpid_enable & (0x1 << tpid_index)) { 30798 BCM_IF_ERROR_RETURN( 30799 _bcm_fb2_outer_tpid_entry_delete(unit, tpid_index)); 30800 return BCM_E_EXISTS; 30801 } else { 30802 tpid_enable |= (0x1 << tpid_index); 30803 30804 soc_reg_field_set(unit, ING_L2_TUNNEL_PARSE_CONTROLr, 30805 &l2_tunnel_parse_control, 30806 tpid_enable_field, tpid_enable); 30807 30808 rv = WRITE_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 30809 l2_tunnel_parse_control); 30810 } 30811 } 30812 } 30813 #endif /* BCM_TOMAHAWK_SUPPORT */ 30814 30815 return (rv); 30816 } 30817 30818 /* 30819 * Function: 30820 * bcm_esw_switch_tpid_delete 30821 * Purpose: 30822 * Delete a global TPID. 30823 * BCM5616x family of devices support deleting global TPID 30824 * via bcmTpidTypeCapwapPayloadOuter and bcmTpidTypeCapwapPayloadInner. 30825 * The device supports deleting global L2 Tunnel TPID from 30826 * the ingress inner TPID matching register via bcmTpidTypeL2TunnelPayloadInner. 30827 * Parameters: 30828 * unit - (IN) Unit number. 30829 * tpid_info - (IN) TPID info includes key: {tpid_type, tpid_value} 30830 * and Associated value(s): {flags, color}. 30831 * Returns: 30832 * BCM_E_xxx 30833 * Notes: 30834 */ 30835 int 30836 bcm_esw_switch_tpid_delete(int unit, bcm_switch_tpid_info_t *tpid_info) 30837 { 30838 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 30839 30840 if (tpid_info == NULL) { 30841 return (BCM_E_PARAM); 30842 } 30843 #ifdef BCM_TOMAHAWK2_SUPPORT 30844 if (SOC_IS_TOMAHAWK2(unit) && 30845 (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter || 30846 tpid_info->tpid_type == bcmTpidTypeL2grePayloadOuter)) { 30847 return BCM_E_UNAVAIL; 30848 } 30849 #endif /* BCM_TOMAHAWK2_SUPPORT */ 30850 #ifdef BCM_HURRICANE3_SUPPORT 30851 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 30852 if (tpid_info->tpid_type == bcmTpidTypeCapwapPayloadOuter) { 30853 rv = bcmi_esw_switch_capwap_payload_outer_tpid_delete(unit, 30854 tpid_info->tpid_value); 30855 if (BCM_FAILURE(rv)) { 30856 return rv; 30857 } 30858 } else if (tpid_info->tpid_type == bcmTpidTypeCapwapPayloadInner) { 30859 rv = bcmi_esw_switch_capwap_payload_inner_tpid_delete(unit, 30860 tpid_info->tpid_value); 30861 if (BCM_FAILURE(rv)) { 30862 return rv; 30863 } 30864 } 30865 } 30866 #endif /* BCM_HURRICANE3_SUPPORT */ 30867 30868 #if defined(BCM_GREYHOUND2_SUPPORT) 30869 if (soc_feature(unit, soc_feature_vxlan_lite)) { 30870 if ((tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter) || 30871 (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadInner)) { 30872 rv = bcmi_esw_switch_vxlan_payload_tpid_delete(unit, tpid_info); 30873 if (BCM_FAILURE(rv)) { 30874 return rv; 30875 } 30876 } 30877 } 30878 #endif /* BCM_GREYHOUND2_SUPPORT */ 30879 30880 #ifdef BCM_TRIUMPH_SUPPORT 30881 if (soc_feature(unit, soc_feature_ing_l2tunnel_tpid_parser) && 30882 (tpid_info->tpid_type == bcmTpidTypeL2TunnelPayloadInner)) { 30883 uint32 tpid_value; 30884 30885 BCM_IF_ERROR_RETURN(READ_ING_MPLS_INNER_TPIDr(unit, &tpid_value)); 30886 if (tpid_value != tpid_info->tpid_value) { 30887 return BCM_E_NOT_FOUND; 30888 } 30889 rv = WRITE_ING_MPLS_INNER_TPIDr(unit, 0x0); 30890 } 30891 #endif /* BCM_TRIUMPH_SUPPORT */ 30892 30893 #ifdef BCM_TOMAHAWK_SUPPORT 30894 if (soc_feature(unit, soc_feature_l2_tunnel_transit_payload_tpid_parser)) { 30895 int tpid_index = 0; 30896 soc_field_t tpid_enable_field = INVALIDf; 30897 uint32 l2_tunnel_parse_control = 0; 30898 uint8 tpid_enable = 0; 30899 30900 if (tpid_info->tpid_type == bcmTpidTypeMimPayloadOuter) { 30901 tpid_enable_field = MIM_PAYLOAD_TPID_ENABLEf; 30902 } else if (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter) { 30903 tpid_enable_field = VXLAN_PAYLOAD_TPID_ENABLEf; 30904 } else if (tpid_info->tpid_type == bcmTpidTypeL2grePayloadOuter) { 30905 tpid_enable_field = L2GRE_PAYLOAD_TPID_ENABLEf; 30906 } 30907 30908 if (tpid_enable_field != INVALIDf) { 30909 BCM_IF_ERROR_RETURN( 30910 _bcm_fb2_outer_tpid_lkup(unit, tpid_info->tpid_value, 30911 &tpid_index)); 30912 BCM_IF_ERROR_RETURN( 30913 READ_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 30914 &l2_tunnel_parse_control)); 30915 tpid_enable = soc_reg_field_get(unit, 30916 ING_L2_TUNNEL_PARSE_CONTROLr, 30917 l2_tunnel_parse_control, 30918 tpid_enable_field); 30919 30920 if (tpid_enable & (0x1 << tpid_index)) { 30921 BCM_IF_ERROR_RETURN( 30922 _bcm_fb2_outer_tpid_entry_delete(unit, tpid_index)); 30923 30924 tpid_enable &= ~(0x1 << tpid_index); 30925 30926 soc_reg_field_set(unit, ING_L2_TUNNEL_PARSE_CONTROLr, 30927 &l2_tunnel_parse_control, 30928 tpid_enable_field, tpid_enable); 30929 30930 rv = WRITE_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 30931 l2_tunnel_parse_control); 30932 } else { 30933 return BCM_E_NOT_FOUND; 30934 } 30935 } 30936 } 30937 #endif /* BCM_TOMAHAWK_SUPPORT */ 30938 30939 return rv; 30940 } 30941 30942 /* 30943 * Function: 30944 * bcm_esw_switch_tpid_delete_all 30945 * Purpose: 30946 * Delete all global TPIDs. 30947 * Parameters: 30948 * unit - (IN) Unit number. 30949 * Returns: 30950 * BCM_E_xxx 30951 * Notes: 30952 */ 30953 int 30954 bcm_esw_switch_tpid_delete_all(int unit) 30955 { 30956 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 30957 30958 #ifdef BCM_HURRICANE3_SUPPORT 30959 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 30960 rv = bcmi_esw_switch_capwap_payload_outer_tpid_delete_all(unit); 30961 if (BCM_FAILURE(rv)) { 30962 return rv; 30963 } 30964 rv = bcmi_esw_switch_capwap_payload_inner_tpid_delete_all(unit); 30965 if (BCM_FAILURE(rv)) { 30966 return rv; 30967 } 30968 } 30969 #endif /* BCM_HURRICANE3_SUPPORT */ 30970 30971 #if defined(BCM_GREYHOUND2_SUPPORT) 30972 if (soc_feature(unit, soc_feature_vxlan_lite)) { 30973 rv = bcmi_esw_switch_vxlan_payload_tpid_delete_all(unit); 30974 if (BCM_FAILURE(rv)) { 30975 return rv; 30976 } 30977 } 30978 #endif /* BCM_GREYHOUND2_SUPPORT */ 30979 30980 #ifdef BCM_TRIUMPH_SUPPORT 30981 if (soc_feature(unit, soc_feature_ing_l2tunnel_tpid_parser)) { 30982 rv = WRITE_ING_MPLS_INNER_TPIDr(unit, 0x0); 30983 } 30984 #endif /* BCM_TRIUMPH_SUPPORT */ 30985 30986 #ifdef BCM_TOMAHAWK_SUPPORT 30987 if (soc_feature(unit, soc_feature_l2_tunnel_transit_payload_tpid_parser)) { 30988 int i = 0; 30989 int tpid_index = 0; 30990 uint32 l2_tunnel_parse_control = 0; 30991 uint8 tpid_enable = 0; 30992 soc_field_t tpid_enable_field[] = { 30993 MIM_PAYLOAD_TPID_ENABLEf, 30994 VXLAN_PAYLOAD_TPID_ENABLEf, 30995 L2GRE_PAYLOAD_TPID_ENABLEf}; 30996 30997 BCM_IF_ERROR_RETURN( 30998 READ_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 30999 &l2_tunnel_parse_control)); 31000 for (i = 0; i < 3; i++) { 31001 tpid_index = 0; 31002 if (!soc_reg_field_valid(unit, 31003 ING_L2_TUNNEL_PARSE_CONTROLr,tpid_enable_field[i])) { 31004 continue; 31005 } 31006 tpid_enable = soc_reg_field_get(unit, 31007 ING_L2_TUNNEL_PARSE_CONTROLr, 31008 l2_tunnel_parse_control, 31009 tpid_enable_field[i]); 31010 while (tpid_enable) { 31011 if (tpid_enable & 0x1) { 31012 BCM_IF_ERROR_RETURN( 31013 _bcm_fb2_outer_tpid_entry_delete(unit, tpid_index)); 31014 } 31015 tpid_enable >>= 1; 31016 tpid_index++; 31017 } 31018 31019 soc_reg_field_set(unit, ING_L2_TUNNEL_PARSE_CONTROLr, 31020 &l2_tunnel_parse_control, 31021 tpid_enable_field[i], 0); 31022 } 31023 31024 rv = WRITE_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 31025 l2_tunnel_parse_control); 31026 } 31027 #endif /* BCM_TOMAHAWK_SUPPORT */ 31028 31029 return (rv); 31030 } 31031 31032 /* 31033 * Function: 31034 * bcm_esw_switch_tpid_get 31035 * Purpose: 31036 * Get a global TPID. 31037 * BCM5616x family of devices support 5 global TPIDs for 31038 * identifying the outer and inner tags in CAPWAP wirless payload. 31039 * The device supports getting one global L2 Tunnel TPID 31040 * for identifying the outer and inner tags in L2 Tunnel payload from 31041 * the ingress inner TPID matching register. 31042 * Parameters: 31043 * unit - (IN) Unit number. 31044 * tpid_info - (IN/OUT) TPID info includes key: {tpid_type, tpid_value} 31045 * and Associated value(s): {flags, color}. 31046 * Returns: 31047 * BCM_E_xxx 31048 * Notes: 31049 */ 31050 int 31051 bcm_esw_switch_tpid_get(int unit, 31052 bcm_switch_tpid_info_t *tpid_info) 31053 { 31054 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31055 31056 if (tpid_info == NULL) { 31057 return (BCM_E_PARAM); 31058 } 31059 #ifdef BCM_TOMAHAWK2_SUPPORT 31060 if (SOC_IS_TOMAHAWK2(unit) && 31061 (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadOuter || 31062 tpid_info->tpid_type == bcmTpidTypeL2grePayloadOuter)) { 31063 return BCM_E_UNAVAIL; 31064 } 31065 #endif /* BCM_TOMAHAWK2_SUPPORT */ 31066 #ifdef BCM_HURRICANE3_SUPPORT 31067 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 31068 if (tpid_info->tpid_type == bcmTpidTypeCapwapPayloadOuter) { 31069 rv = bcmi_esw_switch_capwap_payload_outer_tpid_get(unit, 31070 &tpid_info->tpid_value); 31071 if (BCM_FAILURE(rv)) { 31072 return rv; 31073 } 31074 } else if (tpid_info->tpid_type == bcmTpidTypeCapwapPayloadInner) { 31075 rv = bcmi_esw_switch_capwap_payload_inner_tpid_get(unit, 31076 &tpid_info->tpid_value); 31077 if (BCM_FAILURE(rv)) { 31078 return rv; 31079 } 31080 } 31081 } 31082 #endif /* BCM_HURRICANE3_SUPPORT */ 31083 31084 #if defined(BCM_GREYHOUND2_SUPPORT) 31085 /* 31086 * Return BCM_E_UNAVAIL for bcmTpidTypeVxlanPayloadOuter 31087 * since total there are four TPID sets. 31088 */ 31089 if (soc_feature(unit, soc_feature_vxlan_lite)) { 31090 if (tpid_info->tpid_type == bcmTpidTypeVxlanPayloadInner) { 31091 uint64 reg_val64; 31092 uint32 reg_val = 0; 31093 uint8 tpid_enable = 0; 31094 31095 COMPILER_64_ZERO(reg_val64); 31096 31097 /* VXLAN Payload Inner TPID enable bit[0] */ 31098 BCM_IF_ERROR_RETURN( 31099 READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 31100 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 31101 reg_val64, PAYLOAD_INNER_TPID_ENABLEf); 31102 31103 if (tpid_enable) { 31104 /* Current Inner TPID value */ 31105 BCM_IF_ERROR_RETURN( 31106 READ_VLAN_CTRLr(unit, ®_val)); 31107 tpid_info->tpid_value = soc_reg_field_get(unit, VLAN_CTRLr, 31108 reg_val, INNER_TPIDf); 31109 } else { 31110 tpid_info->tpid_value = 0; 31111 } 31112 31113 rv = BCM_E_NONE; 31114 } 31115 } 31116 #endif /* BCM_GREYHOUND2_SUPPORT */ 31117 31118 #ifdef BCM_TRIUMPH_SUPPORT 31119 if (soc_feature(unit, soc_feature_ing_l2tunnel_tpid_parser) && 31120 (tpid_info->tpid_type == bcmTpidTypeL2TunnelPayloadInner)) { 31121 uint32 tpid_value; 31122 31123 BCM_IF_ERROR_RETURN(READ_ING_MPLS_INNER_TPIDr(unit, &tpid_value)); 31124 tpid_info->tpid_value = tpid_value; 31125 rv = BCM_E_NONE; 31126 } 31127 #endif /* BCM_TRIUMPH_SUPPORT */ 31128 31129 return rv; 31130 } 31131 31132 /* 31133 * Function: 31134 * bcm_esw_switch_tpid_get_all 31135 * Purpose: 31136 * Get global TPID count or TPIDs. if (size==0), get TPID count of all 31137 * global TPIDs, else, get global TPIDs based on size. 31138 * BCM5616x family of device support getting the global 31139 * TPIDs. 31140 * Parameters: 31141 * unit - (IN) Unit number. 31142 * size - (IN) Size of tpid_info_array to be got. 31143 * tpid_info - (OUT) TPID info array. 31144 * count - (IN) Item count of tpid_info_array. 31145 * Returns: 31146 * BCM_E_xxx 31147 * Notes: 31148 */ 31149 int 31150 bcm_esw_switch_tpid_get_all(int unit, int size, 31151 bcm_switch_tpid_info_t *tpid_info_array, int *count) 31152 { 31153 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31154 31155 if (count == NULL) { 31156 return BCM_E_PARAM; 31157 } 31158 *count = 0; 31159 31160 #ifdef BCM_HURRICANE3_SUPPORT 31161 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 31162 int tpid_enable, tpid_index; 31163 uint16 tpid; 31164 uint32 reg_val; 31165 31166 /* CAPWAP payload outer TPIDs */ 31167 BCM_IF_ERROR_RETURN( 31168 READ_CAPWAP_PAYLOAD_PARSING_CONTROLr(unit, ®_val)); 31169 31170 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 31171 reg_val, PAYLOAD_OUTER_TPID_ENABLEf); 31172 31173 tpid_index = 0; 31174 while (tpid_enable) { 31175 if (tpid_enable & 0x1) { 31176 if (size == 0) { 31177 (*count)++; 31178 } else if (*count < size) { 31179 BCM_IF_ERROR_RETURN( 31180 _bcm_fb2_outer_tpid_entry_get(unit, &tpid, tpid_index)); 31181 tpid_info_array[*count].tpid_type = bcmTpidTypeCapwapPayloadOuter; 31182 tpid_info_array[*count].tpid_value = tpid; 31183 (*count)++; 31184 } 31185 } 31186 tpid_enable >>= 1; 31187 tpid_index++; 31188 } 31189 31190 /* CAPWAP payload inner TPID */ 31191 tpid_enable = soc_reg_field_get(unit, CAPWAP_PAYLOAD_PARSING_CONTROLr, 31192 reg_val, PAYLOAD_INNER_TPID_ENABLEf); 31193 31194 if (tpid_enable) { 31195 if (size == 0) { 31196 (*count)++; 31197 } else if (*count < size) { 31198 BCM_IF_ERROR_RETURN( 31199 READ_VLAN_CTRLr(unit, ®_val)); 31200 31201 tpid = soc_reg_field_get(unit, VLAN_CTRLr, 31202 reg_val, INNER_TPIDf); 31203 tpid_info_array[*count].tpid_type = bcmTpidTypeCapwapPayloadInner; 31204 tpid_info_array[*count].tpid_value = tpid; 31205 (*count)++; 31206 } 31207 } 31208 31209 rv = BCM_E_NONE; 31210 } 31211 #endif /* BCM_HURRICANE3_SUPPORT */ 31212 31213 #if defined(BCM_GREYHOUND2_SUPPORT) 31214 if (soc_feature(unit, soc_feature_vxlan_lite)) { 31215 int tpid_enable, tpid_index; 31216 uint16 tpid; 31217 uint32 reg_val; 31218 uint64 reg_val64; 31219 31220 COMPILER_64_ZERO(reg_val64); 31221 31222 /* VXLAN payload outer TPIDs */ 31223 BCM_IF_ERROR_RETURN( 31224 READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 31225 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 31226 reg_val64, PAYLOAD_OUTER_TPID_ENABLEf); 31227 31228 tpid_index = 0; 31229 while (tpid_enable) { 31230 if (tpid_enable & 0x1) { 31231 if (size == 0) { 31232 (*count)++; 31233 } else if (*count < size) { 31234 BCM_IF_ERROR_RETURN( 31235 _bcm_fb2_outer_tpid_entry_get(unit, &tpid, tpid_index)); 31236 tpid_info_array[*count].tpid_type = bcmTpidTypeVxlanPayloadOuter; 31237 tpid_info_array[*count].tpid_value = tpid; 31238 (*count)++; 31239 } 31240 } 31241 tpid_enable >>= 1; 31242 tpid_index++; 31243 } 31244 31245 /* VXLAN payload inner TPID */ 31246 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 31247 reg_val64, PAYLOAD_INNER_TPID_ENABLEf); 31248 31249 if (tpid_enable) { 31250 if (size == 0) { 31251 (*count)++; 31252 } else if (*count < size) { 31253 BCM_IF_ERROR_RETURN( 31254 READ_VLAN_CTRLr(unit, ®_val)); 31255 31256 tpid = soc_reg_field_get(unit, VLAN_CTRLr, 31257 reg_val, INNER_TPIDf); 31258 tpid_info_array[*count].tpid_type = bcmTpidTypeVxlanPayloadInner; 31259 tpid_info_array[*count].tpid_value = tpid; 31260 (*count)++; 31261 } 31262 } 31263 31264 rv = BCM_E_NONE; 31265 } 31266 #endif /* BCM_GREYHOUND2_SUPPORT */ 31267 31268 #ifdef BCM_TRIUMPH_SUPPORT 31269 if (soc_feature(unit, soc_feature_ing_l2tunnel_tpid_parser)) { 31270 if (size != 0) { 31271 uint32 tpid_value; 31272 31273 BCM_IF_ERROR_RETURN(READ_ING_MPLS_INNER_TPIDr(unit, &tpid_value)); 31274 tpid_info_array[0].tpid_type = bcmTpidTypeL2TunnelPayloadInner; 31275 tpid_info_array[0].tpid_value = tpid_value; 31276 } 31277 31278 *count = 1; 31279 rv = BCM_E_NONE; 31280 } 31281 #endif /* BCM_TRIUMPH_SUPPORT */ 31282 31283 #ifdef BCM_TOMAHAWK_SUPPORT 31284 if (soc_feature(unit, soc_feature_l2_tunnel_transit_payload_tpid_parser)) { 31285 int i = 0; 31286 int tpid_index = 0; 31287 uint32 l2_tunnel_parse_control = 0; 31288 uint8 tpid_enable = 0; 31289 soc_field_t tpid_enable_field[] = { 31290 MIM_PAYLOAD_TPID_ENABLEf, 31291 VXLAN_PAYLOAD_TPID_ENABLEf, 31292 L2GRE_PAYLOAD_TPID_ENABLEf}; 31293 bcm_switch_tpid_type_t tpid_type[] = { 31294 bcmTpidTypeMimPayloadOuter, 31295 bcmTpidTypeVxlanPayloadOuter, 31296 bcmTpidTypeL2grePayloadOuter}; 31297 31298 BCM_IF_ERROR_RETURN( 31299 READ_ING_L2_TUNNEL_PARSE_CONTROLr(unit, 31300 &l2_tunnel_parse_control)); 31301 for (i = 0; i < 3; i++) { 31302 tpid_index = 0; 31303 if (!soc_reg_field_valid(unit, 31304 ING_L2_TUNNEL_PARSE_CONTROLr,tpid_enable_field[i])) { 31305 continue; 31306 } 31307 tpid_enable = soc_reg_field_get(unit, 31308 ING_L2_TUNNEL_PARSE_CONTROLr, 31309 l2_tunnel_parse_control, 31310 tpid_enable_field[i]); 31311 while (tpid_enable) { 31312 if (tpid_enable & 0x1) { 31313 if (size == 0) { 31314 (*count)++; 31315 } else if (*count < size) { 31316 BCM_IF_ERROR_RETURN( 31317 _bcm_fb2_outer_tpid_entry_get( 31318 unit, &(tpid_info_array[*count].tpid_value), 31319 tpid_index)); 31320 tpid_info_array[*count].tpid_type = tpid_type[i]; 31321 (*count)++; 31322 } 31323 } 31324 tpid_enable >>= 1; 31325 tpid_index++; 31326 } 31327 } 31328 rv = BCM_E_NONE; 31329 } 31330 #endif /* BCM_TOMAHAWK_SUPPORT */ 31331 31332 return rv; 31333 } 31334 31335 #if defined(BCM_TOMAHAWK_SUPPORT) 31336 /** 31337 * Function: 31338 * bcm_esw_switch_latency_deinit 31339 * Purpose: 31340 * Switch Latency Bypass feature - Deinit 31341 * Parameters: 31342 * unit - (IN) Unit number 31343 * Returns: 31344 * BCM_E_xxx 31345 */ 31346 int 31347 bcm_esw_switch_latency_deinit(int unit) 31348 { 31349 return soc_th_latency_deinit(unit); 31350 } 31351 31352 /** 31353 * Function: 31354 * bcmi_esw_switch_latency_show 31355 * Purpose: 31356 * display latency bypass mode configured on the switch 31357 * Parameters: 31358 * unit - (IN) Unit number 31359 * Returns: 31360 * BCM_E_xxx 31361 */ 31362 int 31363 bcmi_esw_switch_latency_show(int unit) 31364 { 31365 return soc_th_latency_show(unit); 31366 } 31367 31368 /** 31369 * Function: 31370 * bcmi_esw_switch_latency_diag 31371 * Purpose: 31372 * switch latency bypass diagnostics 31373 * Parameters: 31374 * unit - (IN) Unit number 31375 * Returns: 31376 * BCM_E_xxx 31377 */ 31378 int 31379 bcmi_esw_switch_latency_diag(int unit) 31380 { 31381 return soc_th_latency_diag(unit); 31382 } 31383 31384 /** 31385 * Function: 31386 * bcmi_esw_switch_latency_mem_avail 31387 * Purpose: 31388 * returns if the specified memory / table is available or supported for the 31389 * current latency bypass mode configured on the switch 31390 * Parameters: 31391 * unit - (IN) Unit number 31392 * mem - (IN) memory/table 31393 * Returns: 31394 * TRUE / FALSE 31395 */ 31396 int 31397 bcmi_esw_switch_latency_mem_avail(int unit, soc_mem_t mem) 31398 { 31399 int latency; 31400 SOC_IF_ERROR_RETURN(soc_th_latency_get(unit, &latency)); 31401 return soc_th_latency_mem_avail(unit, mem, latency); 31402 } 31403 31404 /** 31405 * Function: 31406 * bcmi_esw_switch_latency_reg_avail 31407 * Purpose: 31408 * returns if the specified register is available or supported for the 31409 * current latency bypass mode configured on the switch 31410 * Parameters: 31411 * unit - (IN) Unit number 31412 * Returns: 31413 * TRUE / FALSE 31414 */ 31415 int 31416 bcmi_esw_switch_latency_reg_avail(int unit, soc_reg_t reg) 31417 { 31418 int latency; 31419 SOC_IF_ERROR_RETURN(soc_th_latency_get(unit, &latency)); 31420 return soc_th_latency_reg_avail(unit, reg, latency); 31421 } 31422 31423 #ifdef BCM_WARM_BOOT_SUPPORT 31424 /** 31425 * Function: 31426 * bcm_esw_latency_wb_memsz_get 31427 * Purpose: 31428 * Returns the WB Memory requirement from Switch Latency Bypass feature 31429 * Parameters: 31430 * unit - (IN) Unit number 31431 * mem_sz - (OUT) WB Memory required in bytes 31432 * Returns: 31433 * BCM_E_xxx 31434 */ 31435 int 31436 bcmi_esw_switch_latency_wb_memsz_get( 31437 int unit, 31438 OUT uint32* const mem_sz, 31439 uint16 scache_ver) 31440 { 31441 if (SOC_IS_TOMAHAWKX(unit)) { 31442 return soc_th_latency_wb_memsz_get(unit, mem_sz, scache_ver); 31443 } else { 31444 *mem_sz = 0; 31445 return BCM_E_NONE; 31446 } 31447 } 31448 31449 /** 31450 * Function: 31451 * bcmi_esw_switch_latency_wb_sync 31452 * Purpose: 31453 * Switch Latency Bypass feature - Warmboot Sync 31454 * Parameters: 31455 * unit - (IN) Unit number 31456 * wb_data - (IN/OUT) ptr to ASF WB data area 31457 * Returns: 31458 * BCM_E_xxx 31459 */ 31460 int 31461 bcmi_esw_switch_latency_wb_sync( 31462 int unit, 31463 IN_OUT uint8* wb_data) 31464 { 31465 if (SOC_IS_TOMAHAWKX(unit)) { 31466 return soc_th_latency_wb_sync(unit, wb_data); 31467 } else { 31468 return BCM_E_NONE; 31469 } 31470 } 31471 31472 /** 31473 * Function: 31474 * bcmi_esw_switch_latency_wb_recover 31475 * Purpose: 31476 * Switch Latency Bypass feature - Warmboot Recovery 31477 * Parameters: 31478 * unit - (IN) Unit number 31479 * wb_data - (IN) pointer to ASF WB data area 31480 * Returns: 31481 * BCM_E_xxx 31482 */ 31483 int 31484 bcmi_esw_switch_latency_wb_recover( 31485 int unit, 31486 uint8* const wb_data, 31487 uint16 scache_ver) 31488 { 31489 if (SOC_IS_TOMAHAWKX(unit)) { 31490 return soc_th_latency_wb_recover(unit, wb_data, scache_ver); 31491 } else { 31492 return BCM_E_NONE; 31493 } 31494 } 31495 #endif /* BCM_WARMBOOT_SUPPORT */ 31496 #endif 31497 31498 /* 31499 * Function: 31500 * bcm_esw_switch_match_config_add 31501 * Purpose: 31502 * Add a match config, match_id will be returned after match 31503 * config created. 31504 * Parameters: 31505 * unit - (IN) Unit number 31506 * match_service - (IN) Match service type 31507 * config_info - (IN) Match configuration 31508 * match_id - (OUT) Match ID 31509 * Returns: 31510 * BCM_E_xxx 31511 */ 31512 int 31513 bcm_esw_switch_match_config_add( 31514 int unit, 31515 bcm_switch_match_service_t match_service, 31516 bcm_switch_match_config_info_t *config_info, 31517 int *match_id) 31518 { 31519 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31520 if (soc_feature(unit, soc_feature_switch_match)) { 31521 return bcmi_switch_match_config_add(unit, 31522 match_service, 31523 config_info, 31524 match_id); 31525 } 31526 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31527 31528 #ifdef BCM_TRIDENT2_SUPPORT 31529 /* TD2 should move into above generic code (soc_feature_switch_match). */ 31530 if (match_service == bcmSwitchMatchServiceGtp) { 31531 return bcm_td2_switch_match_config_add(unit, match_service, 31532 config_info, match_id); 31533 } 31534 #endif /* BCM_TRIDENT2_SUPPORT */ 31535 31536 return BCM_E_UNAVAIL; 31537 } 31538 31539 /* 31540 * Function: 31541 * bcm_esw_switch_match_config_delete 31542 * Purpose: 31543 * Delete a match config with the given match_id. 31544 * Parameters: 31545 * unit - (IN) Unit number 31546 * match_service - (IN) Match service type 31547 * match_id - (IN) Match ID 31548 * Returns: 31549 * BCM_E_xxx 31550 */ 31551 int 31552 bcm_esw_switch_match_config_delete( 31553 int unit, 31554 bcm_switch_match_service_t match_service, 31555 int match_id) 31556 { 31557 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31558 if (soc_feature(unit, soc_feature_switch_match)) { 31559 return bcmi_switch_match_config_delete(unit, 31560 match_service, 31561 match_id); 31562 } 31563 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31564 31565 #ifdef BCM_TRIDENT2_SUPPORT 31566 /* TD2 should move into above generic code (soc_feature_switch_match). */ 31567 if (match_service == bcmSwitchMatchServiceGtp) { 31568 return bcm_td2_switch_match_config_delete(unit, match_service, 31569 match_id); 31570 } 31571 #endif /* BCM_TRIDENT2_SUPPORT */ 31572 31573 return BCM_E_UNAVAIL; 31574 } 31575 31576 /* 31577 * Function: 31578 * bcm_esw_switch_match_config_delete_all 31579 * Purpose: 31580 * Delete all match config with the given match_service. 31581 * Parameters: 31582 * unit - (IN) Unit number 31583 * match_service - (IN) Match service type 31584 * Returns: 31585 * BCM_E_xxx 31586 */ 31587 int 31588 bcm_esw_switch_match_config_delete_all( 31589 int unit, 31590 bcm_switch_match_service_t match_service) 31591 { 31592 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31593 if (soc_feature(unit, soc_feature_switch_match)) { 31594 return bcmi_switch_match_config_delete_all(unit, 31595 match_service); 31596 } 31597 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31598 31599 #ifdef BCM_TRIDENT2_SUPPORT 31600 /* TD2 should move into above generic code (soc_feature_switch_match). */ 31601 if (match_service == bcmSwitchMatchServiceGtp) { 31602 return bcm_td2_switch_match_config_delete_all(unit, match_service); 31603 } 31604 #endif /* BCM_TRIDENT2_SUPPORT */ 31605 31606 return BCM_E_UNAVAIL; 31607 } 31608 31609 /* 31610 * Function: 31611 * bcm_esw_switch_match_config_get 31612 * Purpose: 31613 * Get the configuration of the match with the given match_id. 31614 * Parameters: 31615 * unit - (IN) Unit number 31616 * match_service - (IN) Match service type 31617 * match_id - (IN) Match ID 31618 * config_info - (OUT) Match configuration 31619 * Returns: 31620 * BCM_E_xxx 31621 */ 31622 int 31623 bcm_esw_switch_match_config_get( 31624 int unit, 31625 bcm_switch_match_service_t match_service, 31626 int match_id, 31627 bcm_switch_match_config_info_t *config_info) 31628 { 31629 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31630 if (soc_feature(unit, soc_feature_switch_match)) { 31631 return bcmi_switch_match_config_get(unit, 31632 match_service, 31633 match_id, 31634 config_info); 31635 } 31636 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31637 31638 #ifdef BCM_TRIDENT2_SUPPORT 31639 /* TD2 should move into above generic code (soc_feature_switch_match). */ 31640 if (match_service == bcmSwitchMatchServiceGtp) { 31641 return bcm_td2_switch_match_config_get(unit, match_service, 31642 match_id, config_info); 31643 } 31644 #endif /* BCM_TRIDENT2_SUPPORT */ 31645 31646 return BCM_E_UNAVAIL; 31647 } 31648 31649 /* 31650 * Function: 31651 * bcm_esw_switch_match_config_set 31652 * Purpose: 31653 * Set the configuration of the match with the given match_id. 31654 * Parameters: 31655 * unit - (IN) Unit number 31656 * match_service - (IN) Match service type 31657 * match_id - (IN) Match ID 31658 * config_info - (IN) Match configuration 31659 * Returns: 31660 * BCM_E_xxx 31661 */ 31662 int 31663 bcm_esw_switch_match_config_set( 31664 int unit, 31665 bcm_switch_match_service_t match_service, 31666 int match_id, 31667 bcm_switch_match_config_info_t *config_info) 31668 { 31669 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31670 if (soc_feature(unit, soc_feature_switch_match)) { 31671 return bcmi_switch_match_config_set(unit, 31672 match_service, 31673 match_id, 31674 config_info); 31675 } 31676 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31677 31678 #ifdef BCM_TRIDENT2_SUPPORT 31679 /* TD2 should move into above generic code (soc_feature_switch_match). */ 31680 if (match_service == bcmSwitchMatchServiceGtp) { 31681 return bcm_td2_switch_match_config_set(unit, match_service, 31682 match_id, config_info); 31683 } 31684 #endif /* BCM_TRIDENT2_SUPPORT */ 31685 31686 return BCM_E_UNAVAIL; 31687 } 31688 31689 /* 31690 * Function: 31691 * bcm_esw_switch_match_config_traverse 31692 * Purpose: 31693 * Traverse the created match config. 31694 * Parameters: 31695 * unit - (IN) Unit number 31696 * match_service - (IN) Match service type 31697 * cb_fn - (IN) Traverse call back function 31698 * user_data - (IN) User data 31699 * Returns: 31700 * BCM_E_xxx 31701 */ 31702 int 31703 bcm_esw_switch_match_config_traverse( 31704 int unit, 31705 bcm_switch_match_service_t match_service, 31706 bcm_switch_match_config_traverse_cb cb_fn, 31707 void *user_data) 31708 { 31709 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31710 if (soc_feature(unit, soc_feature_switch_match)) { 31711 return bcmi_switch_match_config_traverse(unit, 31712 match_service, 31713 cb_fn, 31714 user_data); 31715 } 31716 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31717 31718 #ifdef BCM_TRIDENT2_SUPPORT 31719 /* TD2 should move into above generic code (soc_feature_switch_match). */ 31720 if (match_service == bcmSwitchMatchServiceGtp) { 31721 return bcm_td2_switch_match_config_traverse(unit, match_service, 31722 cb_fn, user_data); 31723 } 31724 #endif /* BCM_TRIDENT2_SUPPORT */ 31725 31726 return BCM_E_UNAVAIL; 31727 } 31728 31729 /* 31730 * Function: 31731 * bcm_esw_switch_match_control_get 31732 * Purpose: 31733 * Get the match related control information with given control type. 31734 * Parameters: 31735 * unit - (IN) Unit number 31736 * match_service - (IN) Match service type 31737 * control_type - (IN) Match control type 31738 * gport - (IN) gport number for port basis control. Otherwise, BCM_GPORT_INVALID. 31739 * control_info - (OUT) Match control information 31740 * Returns: 31741 * BCM_E_xxx 31742 */ 31743 int 31744 bcm_esw_switch_match_control_get( 31745 int unit, 31746 bcm_switch_match_service_t match_service, 31747 bcm_switch_match_control_type_t control_type, 31748 bcm_gport_t gport, 31749 bcm_switch_match_control_info_t *control_info) 31750 { 31751 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31752 if (soc_feature(unit, soc_feature_switch_match)) { 31753 return bcmi_switch_match_control_get(unit, 31754 match_service, 31755 control_type, 31756 gport, 31757 control_info); 31758 } 31759 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31760 31761 return BCM_E_UNAVAIL; 31762 } 31763 31764 /* 31765 * Function: 31766 * bcm_esw_switch_match_control_set 31767 * Purpose: 31768 * Set the match related control information with given control type. 31769 * Parameters: 31770 * unit - (IN) Unit number 31771 * match_service - (IN) Match service type 31772 * control_type - (IN) Match control type 31773 * gport - (IN) gport number for port basis control. Otherwise, BCM_GPORT_INVALID. 31774 * control_info - (IN) Match control information 31775 * Returns: 31776 * BCM_E_xxx 31777 */ 31778 int 31779 bcm_esw_switch_match_control_set( 31780 int unit, 31781 bcm_switch_match_service_t match_service, 31782 bcm_switch_match_control_type_t control_type, 31783 bcm_gport_t gport, 31784 bcm_switch_match_control_info_t *control_info) 31785 { 31786 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31787 if (soc_feature(unit, soc_feature_switch_match)) { 31788 return bcmi_switch_match_control_set(unit, 31789 match_service, 31790 control_type, 31791 gport, 31792 control_info); 31793 } 31794 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31795 31796 return BCM_E_UNAVAIL; 31797 } 31798 31799 /* 31800 * Function: 31801 * bcm_esw_switch_match_control_traverse 31802 * Purpose: 31803 * Traverse the match control information. 31804 * Parameters: 31805 * unit - (IN) Unit number 31806 * match_service - (IN) Match service type 31807 * cb_fn - (IN) Traverse call back function 31808 * user_data - (IN) User data 31809 * Returns: 31810 * BCM_E_xxx 31811 */ 31812 int 31813 bcm_esw_switch_match_control_traverse( 31814 int unit, 31815 bcm_switch_match_service_t match_service, 31816 bcm_switch_match_control_traverse_cb cb_fn, 31817 void *user_data) 31818 { 31819 #if defined(BCM_SWITCH_MATCH_SUPPORT) 31820 if (soc_feature(unit, soc_feature_switch_match)) { 31821 return bcmi_switch_match_control_traverse(unit, 31822 match_service, 31823 cb_fn, 31824 user_data); 31825 } 31826 #endif /* BCM_SWITCH_MATCH_SUPPORT */ 31827 31828 return BCM_E_UNAVAIL; 31829 } 31830 31831 /* 31832 * Function: 31833 * bcm_esw_switch_encap_create 31834 * Purpose: 31835 * Create an encapuslation object, encap_id will be returned after the 31836 * encapsulation object created. The encap_id will be used by FP. 31837 * Parameters: 31838 * unit - (IN) Unit number. 31839 * encap_info - (IN) Encapsulation info data structure. 31840 * encap_id - (OUT) Encapsulation object id. 31841 * Returns: 31842 * BCM_E_xxx 31843 * Notes: 31844 */ 31845 int 31846 bcm_esw_switch_encap_create(int unit, 31847 bcm_switch_encap_info_t *encap_info, bcm_if_t *encap_id) 31848 { 31849 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31850 31851 #ifdef BCM_HURRICANE3_SUPPORT 31852 if (soc_feature(unit, soc_feature_miml) || 31853 soc_feature(unit, soc_feature_custom_header)) { 31854 rv = bcm_hr3_switch_encap_create(unit, encap_info, encap_id); 31855 } 31856 #endif /* BCM_HURRICANE3_SUPPORT */ 31857 31858 return rv; 31859 } 31860 31861 /* 31862 * Function: 31863 * bcm_esw_switch_encap_destroy 31864 * Purpose: 31865 * Destroy the encap object with the given encap_id. 31866 * Parameters: 31867 * unit - (IN) Unit number. 31868 * encap_id - (IN) Encapsulation object id. 31869 * Returns: 31870 * BCM_E_xxx 31871 * Notes: 31872 */ 31873 int 31874 bcm_esw_switch_encap_destroy(int unit, bcm_if_t encap_id) 31875 { 31876 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31877 31878 #ifdef BCM_HURRICANE3_SUPPORT 31879 if (soc_feature(unit, soc_feature_miml) || 31880 soc_feature(unit, soc_feature_custom_header)) { 31881 rv = bcm_hr3_switch_encap_destroy(unit, encap_id); 31882 } 31883 #endif /* BCM_HURRICANE3_SUPPORT */ 31884 31885 return rv; 31886 } 31887 31888 /* 31889 * Function: 31890 * bcm_esw_switch_encap_destroy_all 31891 * Purpose: 31892 * Destroy all encap objects. 31893 * Parameters: 31894 * unit - (IN) Unit number. 31895 * Returns: 31896 * BCM_E_xxx 31897 * Notes: 31898 */ 31899 int 31900 bcm_esw_switch_encap_destroy_all(int unit) 31901 { 31902 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31903 31904 #ifdef BCM_HURRICANE3_SUPPORT 31905 if (soc_feature(unit, soc_feature_miml) || 31906 soc_feature(unit, soc_feature_custom_header)) { 31907 rv = bcm_hr3_switch_encap_destroy_all(unit); 31908 } 31909 #endif /* BCM_HURRICANE3_SUPPORT */ 31910 31911 return rv; 31912 } 31913 31914 /* 31915 * Function: 31916 * bcm_esw_switch_encap_set 31917 * Purpose: 31918 * Modify the configuration of the encap object with the given encap_id. 31919 * Parameters: 31920 * unit - (IN) Unit number. 31921 * encap_id - (IN) Encapsulation object id. 31922 * encap_info - (IN) Encapsulation info data structure. 31923 * Returns: 31924 * BCM_E_xxx 31925 * Notes: 31926 */ 31927 int 31928 bcm_esw_switch_encap_set(int unit, 31929 bcm_if_t encap_id, bcm_switch_encap_info_t *encap_info) 31930 { 31931 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31932 31933 #ifdef BCM_HURRICANE3_SUPPORT 31934 if (soc_feature(unit, soc_feature_miml) || 31935 soc_feature(unit, soc_feature_custom_header)) { 31936 rv = bcm_hr3_switch_encap_set(unit, encap_id, encap_info); 31937 } 31938 #endif /* BCM_HURRICANE3_SUPPORT */ 31939 31940 return rv; 31941 } 31942 31943 /* 31944 * Function: 31945 * bcm_esw_switch_encap_get 31946 * Purpose: 31947 * Get the configuration of the encap object with the given encap_id. 31948 * Parameters: 31949 * unit - (IN) Unit number. 31950 * encap_id - (IN) Encapsulation object id. 31951 * encap_info - (OUT) Encapsulation info data structure. 31952 * Returns: 31953 * BCM_E_xxx 31954 * Notes: 31955 */ 31956 int 31957 bcm_esw_switch_encap_get(int unit, 31958 bcm_if_t encap_id, bcm_switch_encap_info_t *encap_info) 31959 { 31960 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31961 31962 #ifdef BCM_HURRICANE3_SUPPORT 31963 if (soc_feature(unit, soc_feature_miml) || 31964 soc_feature(unit, soc_feature_custom_header)) { 31965 rv = bcm_hr3_switch_encap_get(unit, encap_id, encap_info); 31966 } 31967 #endif /* BCM_HURRICANE3_SUPPORT */ 31968 31969 return rv; 31970 } 31971 31972 /* 31973 * Function: 31974 * bcm_esw_switch_encap_traverse 31975 * Purpose: 31976 * To traverse all created encapsulation entries and call provided callback function 31977 * with matched entry. 31978 * Parameters: 31979 * unit - (IN) Unit number. 31980 * cb_fn - (IN) User specified callback function. 31981 * user_data - (IN) User specified cookie. 31982 * Returns: 31983 * BCM_E_xxx 31984 * Notes: 31985 */ 31986 int 31987 bcm_esw_switch_encap_traverse(int unit, 31988 bcm_switch_encap_traverse_cb cb_fn, void *user_data) 31989 { 31990 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 31991 31992 #ifdef BCM_HURRICANE3_SUPPORT 31993 if (soc_feature(unit, soc_feature_miml) || 31994 soc_feature(unit, soc_feature_custom_header)) { 31995 rv = bcm_hr3_switch_encap_traverse(unit, cb_fn, user_data); 31996 } 31997 #endif /* BCM_HURRICANE3_SUPPORT */ 31998 31999 return rv; 32000 } 32001 32002 /* 32003 * Function: 32004 * bcm_esw_switch_chip_info_get 32005 * Purpose: 32006 * Get the chip info of the specified type defined in the 32007 * bcm_switch_chip_info_t. 32008 * If the caller-allocated data_buf is non NULL with size specified in 32009 * max_size (in bytes), the chip info will be filled in the data_buf. If 32010 * data_buf is NULL, the API returns the required size for the chip info 32011 * (in bytes) in actual_size. 32012 * Parameters: 32013 * unit - (IN) Unit number. 32014 * info_type - (IN) chip info type. 32015 * max_size - (IN) size in bytes of the data_buf. 32016 * data_buf - (OUT) buffer to carry the chip info specified. 32017 * actual_size - (OUT) actual data_buf size in bytes. 32018 * Returns: 32019 * BCM_E_xxx 32020 * Notes: 32021 */ 32022 int 32023 bcm_esw_switch_chip_info_get(int unit, 32024 bcm_switch_chip_info_t info_type, 32025 int max_size, 32026 void *data_buf, 32027 int *actual_size) 32028 { 32029 int rv = BCM_E_UNAVAIL; 32030 32031 #if defined(BCM_GREYHOUND2_SUPPORT) 32032 if (SOC_IS_GREYHOUND2(unit)) { 32033 return bcmi_gh2_switch_chip_info_get(unit, info_type, max_size, 32034 data_buf, actual_size); 32035 } 32036 #endif /* BCM_GREYHOUND2_SUPPORT */ 32037 32038 #if defined(BCM_HELIX5_SUPPORT) 32039 if (SOC_IS_HELIX5(unit)) { 32040 return bcmi_hx5_switch_chip_info_get(unit, info_type, max_size, 32041 data_buf, actual_size); 32042 } 32043 #endif 32044 32045 return rv; 32046 } 32047 32048 /* 32049 * Function: 32050 * bcm_esw_switch_ser_log_info_get 32051 * Purpose: 32052 * To get ser log info. 32053 * Parameters: 32054 * unit - (IN) Unit number. 32055 * id - (IN) log id. 32056 * info - (OUT) ser log info. 32057 * Returns: 32058 * BCM_E_xxx 32059 * Notes: 32060 */ 32061 int 32062 bcm_esw_switch_ser_log_info_get(int unit, 32063 int id, bcm_switch_ser_log_info_t *info) 32064 { 32065 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 32066 32067 #if defined(BCM_TRIDENT2_SUPPORT) 32068 if (soc_feature(unit, soc_feature_ser_log_info)) { 32069 rv = bcm_td2_switch_ser_log_info_get(unit, id, info); 32070 } 32071 #endif 32072 32073 return rv; 32074 } 32075 32076 /* 32077 * Function: 32078 * bcm_esw_switch_ser_log_info_get 32079 * Purpose: 32080 * Get SER error statistics for specified statistics type. 32081 * Parameters: 32082 * unit - (IN) Unit number. 32083 * stat_type - (IN) SER error statistics type. 32084 * value - (OUT) Number of errors 32085 * Returns: 32086 * BCM_E_xxx 32087 * Notes: 32088 */ 32089 int 32090 bcm_esw_switch_ser_error_stat_get(int unit, 32091 bcm_switch_ser_error_stat_type_t stat_type, 32092 uint32 *value) 32093 { 32094 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 32095 32096 #if defined(BCM_TRIDENT2_SUPPORT) 32097 if (soc_feature(unit, soc_feature_ser_error_stat)) { 32098 rv = bcm_td2_switch_ser_error_stat_get(unit, stat_type, value); 32099 } 32100 #endif 32101 32102 return rv; 32103 } 32104 32105 /* 32106 * Function: 32107 * bcm_esw_switch_ser_log_info_clear 32108 * Purpose: 32109 * Clear SER error statistics for specified statistics type. 32110 * Parameters: 32111 * unit - (IN) Unit number. 32112 * stat_type - (IN) SER error statistics type. 32113 * Returns: 32114 * BCM_E_xxx 32115 * Notes: 32116 */ 32117 int 32118 bcm_esw_switch_ser_error_stat_clear(int unit, 32119 bcm_switch_ser_error_stat_type_t stat_type) 32120 { 32121 int rv = BCM_E_UNAVAIL; /* Operation return status. */ 32122 32123 #if defined(BCM_TRIDENT2_SUPPORT) 32124 if (soc_feature(unit, soc_feature_ser_error_stat)) { 32125 rv = bcm_td2_switch_ser_error_stat_clear(unit, stat_type); 32126 } 32127 #endif 32128 32129 return rv; 32130 } 32131 32132 /* 32133 * Function: 32134 * bcm_esw_switch_opaque_tag_config_get 32135 * Purpose: 32136 * This function reads from hardware the values of opaque tag parameters 32137 * programmed. Note we read values from OPAQUE_TAG_CONFIG_0 or 32138 * OPAQUE_TAG_CONFIG_1 register (depending on 'index' argument). That's because 32139 * all registers in opaque tag reg set are programmed identically in the 'set' 32140 * API, and OPAQUE_TAG_CONFIG_0, or OPAQUE_TAG_CONFIG_1 has one more configured 32141 * value (opaque_tag_type) than the other registers. 32142 * Parameters: 32143 * unit - (IN) BCM device number 32144 * index - (IN) Register set values to read from (0 or 1) 32145 * opaque_tag_config - (OUT) Buffer used to fill opaque tag parameters read 32146 * from hardware 32147 * Returns: 32148 * BCM_E_XXX 32149 * Notes: 32150 */ 32151 int bcm_esw_switch_opaque_tag_config_get(int unit, int index, 32152 bcm_switch_opaque_tag_params_t *opaque_tag_config) 32153 { 32154 #if defined(BCM_TOMAHAWK3_SUPPORT) 32155 soc_reg_t reg; 32156 uint32 regval; 32157 32158 if ((index < 0) || (index >= BCM_SWITCH_MAX_NUM_OPAQUE_TAGS)) { 32159 return BCM_E_PARAM; 32160 } 32161 32162 if (opaque_tag_config == NULL) { 32163 return BCM_E_PARAM; 32164 } 32165 32166 switch (index) { 32167 case 0: 32168 reg = OPAQUE_TAG_CONFIG_0r; 32169 break; 32170 32171 case 1: 32172 default: 32173 reg = OPAQUE_TAG_CONFIG_1r; 32174 break; 32175 } 32176 32177 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, ®val)); 32178 32179 opaque_tag_config->ethertype = soc_reg_field_get(unit, reg, regval, 32180 ETHERTYPEf); 32181 opaque_tag_config->tag_size = soc_reg_field_get(unit, reg, regval, 32182 TAG_SIZEf); 32183 opaque_tag_config->tag_type = soc_reg_field_get(unit, reg, regval, 32184 OPAQUE_TAG_TYPEf); 32185 opaque_tag_config->valid = soc_reg_field_get(unit, reg, regval, 32186 VALIDf); 32187 32188 return BCM_E_NONE; 32189 #else /* BCM_TOMAHAWK3_SUPPORT */ 32190 return BCM_E_UNAVAIL; 32191 #endif /* BCM_TOMAHAWK3_SUPPORT */ 32192 } 32193 32194 /* 32195 * Function: 32196 * bcm_esw_switch_opaque_tag_config_set 32197 * Purpose: 32198 * This function programs values of opaque tag parameters provided by 32199 * application in to hardware register set specified by argument 'index'. 32200 * Note all registers in the set have identical values (as needed by h/w 32201 * implementation) 32202 * Parameters: 32203 * unit - (IN) BCM device number 32204 * index - (IN) Register set to program (0 or 1) 32205 * opaque_tag_config - (IN) Buffer containing opaque tag parameters 32206 * Returns: 32207 * BCM_E_XXX 32208 * Notes: 32209 */ 32210 int bcm_esw_switch_opaque_tag_config_set(int unit, int index, 32211 bcm_switch_opaque_tag_params_t *opaque_tag_config) 32212 { 32213 #if defined(BCM_TOMAHAWK3_SUPPORT) 32214 /* Do not change order of registers below. Add any new regs at the end */ 32215 static const soc_reg_t reg_set0[] = { 32216 OPAQUE_TAG_CONFIG_0r, 32217 EGR_EFPPARS_OPAQUE_TAG_CONFIG_0r, 32218 EGR_EPARS_OPAQUE_TAG_CONFIG_0r 32219 }; 32220 /* Do not change order of registers below. Add any new regs at the end */ 32221 static const soc_reg_t reg_set1[] = { 32222 OPAQUE_TAG_CONFIG_1r, 32223 EGR_EFPPARS_OPAQUE_TAG_CONFIG_1r, 32224 EGR_EPARS_OPAQUE_TAG_CONFIG_1r 32225 }; 32226 soc_reg_t const *reg; 32227 soc_reg_t obm_reg_base, obm_reg; 32228 int i, pipe, num_elems, fld_len; 32229 uint32 regval; 32230 soc_info_t *si; 32231 32232 if ((index < 0) || (index >= BCM_SWITCH_MAX_NUM_OPAQUE_TAGS)) { 32233 return BCM_E_PARAM; 32234 } 32235 32236 if (opaque_tag_config == NULL) { 32237 return BCM_E_PARAM; 32238 } 32239 32240 si = &SOC_INFO(unit); 32241 32242 switch (index) { 32243 case 0: 32244 reg = reg_set0; 32245 num_elems = COUNTOF(reg_set0); 32246 obm_reg_base = IDB_OBM0_OPAQUE_TAG_CONFIG_0r; 32247 break; 32248 32249 case 1: 32250 default: 32251 reg = reg_set1; 32252 num_elems = COUNTOF(reg_set1); 32253 obm_reg_base = IDB_OBM0_OPAQUE_TAG_CONFIG_1r; 32254 break; 32255 } 32256 32257 /* We use OPAQUE_TAG_CONFIG_x register; the field lengths are identical for 32258 * all other registers 32259 */ 32260 fld_len = soc_reg_field_length(unit, reg[0], OPAQUE_TAG_TYPEf); 32261 /* Opaque tag type of 0 is not valid for h/w programming */ 32262 if ((opaque_tag_config->tag_type == 0) || 32263 (opaque_tag_config->tag_type >= (1 << fld_len))) { 32264 return BCM_E_CONFIG; 32265 } 32266 32267 fld_len = soc_reg_field_length(unit, reg[0], TAG_SIZEf); 32268 /* Tag size values of 0 and 3 are not legal for h/w programming */ 32269 if ((opaque_tag_config->tag_size == 0) || 32270 (opaque_tag_config->tag_size == 3) || 32271 (opaque_tag_config->tag_size >= (1 << fld_len))) { 32272 return BCM_E_CONFIG; 32273 } 32274 32275 for (i = 0; i < num_elems; i++) { 32276 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg[i], REG_PORT_ANY, 0, 32277 ®val)); 32278 if (i == 0) { 32279 /* Write opaque tag type in OPAQUE_TAG_CONFIG_x reg */ 32280 soc_reg_field_set(unit, reg[i], ®val, OPAQUE_TAG_TYPEf, 32281 opaque_tag_config->tag_type); 32282 } 32283 32284 soc_reg_field_set(unit, reg[i], ®val, ETHERTYPEf, 32285 opaque_tag_config->ethertype); 32286 soc_reg_field_set(unit, reg[i], ®val, TAG_SIZEf, 32287 opaque_tag_config->tag_size); 32288 soc_reg_field_set(unit, reg[i], ®val, VALIDf, 32289 opaque_tag_config->valid ? 1 : 0); 32290 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg[i], REG_PORT_ANY, 0, 32291 regval)); 32292 } 32293 32294 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 32295 if (SOC_PBMP_IS_NULL(si->pipe_pbm[pipe])) { 32296 continue; 32297 } 32298 obm_reg = SOC_REG_UNIQUE_ACC(unit, obm_reg_base)[pipe]; 32299 32300 /* 4 copies of obm_reg per pipe */ 32301 for (i = 0; i < 4; i++) { 32302 regval = 0; 32303 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, obm_reg, REG_PORT_ANY, i, 32304 ®val)); 32305 soc_reg_field_set(unit, obm_reg, ®val, ETHERTYPEf, 32306 opaque_tag_config->ethertype); 32307 soc_reg_field_set(unit, obm_reg, ®val, TAG_SIZEf, 32308 opaque_tag_config->tag_size); 32309 soc_reg_field_set(unit, obm_reg, ®val, VALIDf, 32310 opaque_tag_config->valid ? 1 : 0); 32311 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, obm_reg, REG_PORT_ANY, i, 32312 regval)); 32313 } 32314 } 32315 32316 /* Program IDB regs here */ 32317 32318 return BCM_E_NONE; 32319 #else /* BCM_TOMAHAWK3_SUPPORT */ 32320 return BCM_E_UNAVAIL; 32321 #endif /* BCM_TOMAHAWK3_SUPPORT */ 32322 } 32323 32324 /******************************************************************/ 32325 /* OBM CLASSIFIER START */ 32326 /******************************************************************/ 32327 /* 32328 * Function: 32329 * bcm_esw_switch_obm_classifier_mapping_multi_set 32330 * Purpose: 32331 * Set the mapping of bcm_obm_code_point to bcm_obm_priority 32332 * for multiple entries of same type of classifier. Maximum 32333 * number of entries to be programmed are different depending 32334 * type of classifier. For type bcmSwitchObmClassifierField 32335 * bcm_obm_code_point will not be used and mapping will happen 32336 * based on destination_mac/mask and ethertype/mask. 32337 * Parameters: 32338 * unit - (IN) Unit number. 32339 * gport - (IN) gport for a given port. 32340 * array_count - (IN) Number of elements in switch_obm_classifier. 32341 * switch_obm_classifier - (IN) Array of bcm_switch_obm_classifier_t. 32342 * Returns: 32343 * BCM_E_xxx 32344 */ 32345 int 32346 bcm_esw_switch_obm_classifier_mapping_multi_set( 32347 int unit, 32348 bcm_gport_t gport, 32349 bcm_switch_obm_classifier_type_t switch_obm_classifier_type, 32350 int array_count, 32351 bcm_switch_obm_classifier_t *switch_obm_classifier) 32352 32353 { 32354 if (array_count <= 0) { 32355 return BCM_E_PARAM; 32356 } 32357 32358 if (NULL == switch_obm_classifier) { 32359 return BCM_E_PARAM; 32360 } 32361 32362 #ifdef BCM_MONTEREY_SUPPORT 32363 if (SOC_IS_MONTEREY(unit)) { 32364 return bcm_mn_switch_obm_classifier_mapping_multi_set( 32365 unit, 32366 gport, 32367 switch_obm_classifier_type, 32368 array_count, 32369 switch_obm_classifier); 32370 } 32371 #endif /* BCM_MONTEREY_SUPPORT */ 32372 #ifdef BCM_APACHE_SUPPORT 32373 if (SOC_IS_APACHE(unit)) { 32374 return bcm_apache_switch_obm_classifier_mapping_multi_set( 32375 unit, 32376 gport, 32377 switch_obm_classifier_type, 32378 array_count, 32379 switch_obm_classifier); 32380 } 32381 #endif 32382 return BCM_E_UNAVAIL; 32383 } 32384 /* 32385 * Function: 32386 * bcm_esw_switch_obm_classifier_mapping_multi_get 32387 * Purpose: 32388 * Get the mapping of bcm_obm_code_point to bcm_obm_priority 32389 * for multiple entries of same type of classifier. Maximum 32390 * number of entries to be programmed are different depending 32391 * type of classifier. For type bcmSwitchObmClassifierField 32392 * bcm_obm_code_point will not be used and mapping will happen 32393 * based on destination_mac/mask and ethertype/mask. 32394 * Parameters: 32395 * unit - (IN) Unit number. 32396 * gport - (IN) gport for a given port. 32397 * array_max - (IN) Maximum number of elements in switch_obm_classifier. 32398 * switch_obm_classifier - (IN/OUT) Array of bcm_switch_obm_classifier_t. 32399 * array_count - (OUT) Number of elements in switch_obm_classifier. 32400 * Returns: 32401 * BCM_E_xxx 32402 */ 32403 int 32404 bcm_esw_switch_obm_classifier_mapping_multi_get( 32405 int unit, 32406 bcm_gport_t gport, 32407 bcm_switch_obm_classifier_type_t switch_obm_classifier_type, 32408 int array_max, 32409 bcm_switch_obm_classifier_t *switch_obm_classifier, 32410 int *array_count) 32411 { 32412 if (array_count == NULL) { 32413 return BCM_E_PARAM; 32414 } 32415 32416 if (NULL == switch_obm_classifier) { 32417 return BCM_E_PARAM; 32418 } 32419 32420 #ifdef BCM_MONTEREY_SUPPORT 32421 if (SOC_IS_MONTEREY(unit)) { 32422 return bcm_mn_switch_obm_classifier_mapping_multi_get( 32423 unit, 32424 gport, 32425 switch_obm_classifier_type, 32426 array_max, 32427 switch_obm_classifier, 32428 array_count); 32429 } 32430 #endif /* BCM_MONTEREY_SUPPORT */ 32431 #ifdef BCM_APACHE_SUPPORT 32432 if (SOC_IS_APACHE(unit)) { 32433 return bcm_apache_switch_obm_classifier_mapping_multi_get( 32434 unit, 32435 gport, 32436 switch_obm_classifier_type, 32437 array_max, 32438 switch_obm_classifier, 32439 array_count); 32440 } 32441 #endif /* BCM_APACHE_SUPPORT */ 32442 return BCM_E_UNAVAIL; 32443 } 32444 /* 32445 * Function: 32446 * bcm_esw_switch_obm_classifier_mapping_set 32447 * Purpose: 32448 * Set the mapping of bcm_obm_code_point to bcm_obm_priority 32449 * for one entry of a given type of classifier.For type 32450 * bcmSwitchObmClassifierField bcm_obm_code_point will not 32451 * used and mapping will happen based on destination_mac/mask 32452 * and ethertype/mask. 32453 * Parameters: 32454 * unit - (IN) Unit number. 32455 * gport - (IN) gport for a given port. 32456 * switch_obm_classifier - (IN) Array of bcm_switch_obm_classifier_t. 32457 * Returns: 32458 * BCM_E_xxx 32459 */ 32460 32461 int 32462 bcm_esw_switch_obm_classifier_mapping_set( 32463 int unit, 32464 bcm_gport_t gport, 32465 bcm_switch_obm_classifier_type_t switch_obm_classifier_type, 32466 bcm_switch_obm_classifier_t *switch_obm_classifier) 32467 { 32468 return bcm_esw_switch_obm_classifier_mapping_multi_set( 32469 unit, 32470 gport, 32471 switch_obm_classifier_type, 32472 1, 32473 switch_obm_classifier); 32474 } 32475 /* 32476 * Function: 32477 * bcm_esw_switch_obm_classifier_mapping_set 32478 * Purpose: 32479 * Get the mapping of bcm_obm_code_point to bcm_obm_priority 32480 * for one entry of a given type of classifier. For type 32481 * bcmSwitchObmClassifierField bcm_obm_code_point will not 32482 * used and mapping will happen based on destination_mac/mask 32483 * and ethertype/mask. 32484 * Parameters: 32485 * unit - (IN) Unit number. 32486 * gport - (IN) gport for a given port. 32487 * switch_obm_classifier - (IN) Array of bcm_switch_obm_classifier_t. 32488 * Returns: 32489 * BCM_E_xxx 32490 */ 32491 int 32492 bcm_esw_switch_obm_classifier_mapping_get( 32493 int unit, 32494 bcm_gport_t gport, 32495 bcm_switch_obm_classifier_type_t switch_obm_classifier_type, 32496 bcm_switch_obm_classifier_t *switch_obm_classifier) 32497 { 32498 int array_count = 1; 32499 32500 return bcm_esw_switch_obm_classifier_mapping_multi_get( 32501 unit, 32502 gport, 32503 switch_obm_classifier_type, 32504 1, 32505 switch_obm_classifier, 32506 &array_count); 32507 } 32508 /******************************************************************/ 32509 /* OBM CLASSIFIER END */ 32510 /******************************************************************/ 32511 32512 #define _BCM_SWITCH_DOSATTACK_HDR \ 32513 (BCM_SWITCH_DOSATTACK_OUTER_HDR | \ 32514 BCM_SWITCH_DOSATTACK_INNER_HDR) 32515 32516 #define _BCM_SWITCH_DOSATTACK_VALID_FLAGS \ 32517 (BCM_SWITCH_DOSATTACK_FLOWTRACKER_PRESEL | \ 32518 _BCM_SWITCH_DOSATTACK_HDR) 32519 32520 /* 32521 * Function: 32522 * _bcm_esw_switch_dosattack_event_fmt_field_get 32523 * Purpose: 32524 * Get corresponding format and format field for dos attack event. 32525 * Parameters: 32526 * unit - (IN) BCM device number 32527 * event - (IN) Dos attack event 32528 * fmt - (OUT) Format 32529 * fmt_field - (OUT) Format field 32530 * Returns: 32531 * BCM_E_NONE - Operation successful 32532 * BCM_E_PARAM - Invalid input parameter value 32533 */ 32534 int 32535 _bcm_esw_switch_dosattack_event_fmt_field_get( 32536 int unit, 32537 bcm_switch_dosattack_event_t event, 32538 soc_format_t *fmt, 32539 soc_field_t *fmt_field) 32540 { 32541 switch(event) { 32542 case bcmSwitchDosAttackEventMACSAEqualMACDA: 32543 *fmt_field = MACSA_EQ_MACDAf; 32544 break; 32545 32546 case bcmSwitchDosAttackEventIpFragOffset: 32547 *fmt_field = IP_FRAG_OFFSET_VALUE_OF_1f; 32548 break; 32549 32550 case bcmSwitchDosAttackEventV6Type0RoutingHdr: 32551 *fmt_field = TYPE_ZERO_ROUTING_HDR_PRESENTf; 32552 break; 32553 32554 case bcmSwitchDosAttackEventV6NonLastFragLT1280: 32555 *fmt_field = V6_NON_LAST_FRAGMENT_SIZE_TOO_SMALLf; 32556 break; 32557 32558 case bcmSwitchDosAttackEventTcpIpFirstFragSmall: 32559 *fmt_field = TCP_HDR_TOO_SMALLf; 32560 break; 32561 32562 case bcmSwitchDosAttackEventTcpOffset: 32563 *fmt_field = TCP_FRAG_OFFSET_EQ_ONEf; 32564 break; 32565 32566 case bcmSwitchDosAttackEventSynFrag: 32567 *fmt_field = TCP_FLAGS_SYN_EQ_ONE_ACK_EQ_ZERO_AND_SRC_PORT_LT_1024f; 32568 break; 32569 32570 case bcmSwitchDosAttackEventFlagZeroSeqZero: 32571 *fmt_field = TCP_ALL_FLAGS_EQ_ZERO_AND_SEQNUM_EQ_ZEROf; 32572 break; 32573 32574 case bcmSwitchDosAttackEventTcpFlagsFUP: 32575 *fmt_field = TCP_FLAGS_FIN_URG_AND_PSH_EQ_ONE_AND_SEQNUM_EQ_ZEROf; 32576 break; 32577 32578 case bcmSwitchDosAttackEventTcpFlagsSF: 32579 *fmt_field = TCP_FLAGS_FIN_AND_SYN_EQ_ONEf; 32580 break; 32581 32582 case bcmSwitchDosAttackEventTcpPortsEqual: 32583 *fmt_field = TCP_SPORT_EQ_DPORTf; 32584 break; 32585 32586 case bcmSwitchDosAttackEventUdpPortsEqual: 32587 *fmt_field = UDP_SPORT_EQ_DPORTf; 32588 break; 32589 32590 case bcmSwitchDosAttackEventIcmp: 32591 *fmt_field = ICMP_ECHO_PKT_SIZE_TOO_BIGf; 32592 break; 32593 32594 case bcmSwitchDosAttackEventIcmpFragments: 32595 *fmt_field = ICMP_FRAGMENTED_PKTf; 32596 break; 32597 32598 case bcmSwitchDosAttackEventTcpFlagsSR: 32599 *fmt_field = TCP_SYN_RSTf; 32600 break; 32601 32602 case bcmSwitchDosAttackEventTcpFlagsSynFirstFrag: 32603 *fmt_field = TCP_SYN_FIRST_FRAGMENTf; 32604 break; 32605 32606 case bcmSwitchDosAttackEventTcpFlagsFinNoAck: 32607 *fmt_field = TCP_FIN_NO_ACKf; 32608 break; 32609 32610 case bcmSwitchDosAttackEventTcpFlagsRstNoAck: 32611 *fmt_field = TCP_RST_NO_ACKf; 32612 break; 32613 32614 case bcmSwitchDosAttackEventTcpFlagsNoSFRA: 32615 *fmt_field = TCP_NO_SYN_FIN_RST_ACKf; 32616 break; 32617 32618 case bcmSwitchDosAttackEventTcpDstPortZero: 32619 *fmt_field = TCP_DPORT_ZEROf; 32620 break; 32621 32622 case bcmSwitchDosAttackEventTcpSrcPortZero: 32623 *fmt_field = TCP_SPORT_ZEROf; 32624 break; 32625 32626 case bcmSwitchDosAttackEventTcpIpDstBcast: 32627 *fmt_field = TCP_IP_BROADCAST_CHECKf; 32628 break; 32629 32630 case bcmSwitchDosAttackEventTcpFlagsZero: 32631 *fmt_field = TCP_FLAG_ZEROf; 32632 break; 32633 32634 case bcmSwitchDosAttackEventTcpFlagsResvdNonZero: 32635 *fmt_field = TCP_RESERVED_NON_ZEROf; 32636 break; 32637 32638 case bcmSwitchDosAttackEventTcpFlagsAck: 32639 *fmt_field = TCP_ACK_ACKNUMBER_ZEROf; 32640 break; 32641 32642 case bcmSwitchDosAttackEventTcpFlagsUrgNoUrgPtr: 32643 *fmt_field = TCP_URG_NO_URG_POINTERf; 32644 break; 32645 32646 case bcmSwitchDosAttackEventTcpFlagsNoUrgWithUrgPtr: 32647 *fmt_field = TCP_NO_URG_URG_POINTERf; 32648 break; 32649 32650 case bcmSwitchDosAttackEventTcpFlagsSynOption: 32651 *fmt_field = TCP_SYN_WITH_DATA_PAYLOADf; 32652 break; 32653 32654 default: 32655 *fmt = INVALIDfmt; 32656 *fmt_field = INVALIDf; 32657 LOG_ERROR(BSL_LS_BCM_COMMON, (BSL_META_U(unit, 32658 "Wrong Input arguments\n\r"))); 32659 return BCM_E_PARAM; 32660 } 32661 32662 *fmt = HVE_DOS_ATTACK_RESULTS_FORMATfmt; 32663 32664 return BCM_E_NONE; 32665 } 32666 32667 /* 32668 * Function: 32669 * bcm_esw_switch_dosattack_event_set 32670 * Purpose: 32671 * Configure dos attack events for tracking purpose. 32672 * Parameters: 32673 * unit - (IN) BCM device number 32674 * flags - (IN) flags. 32675 * event - (IN) Dos attack event 32676 * arg - (IN) arg 32677 * Returns: 32678 * BCM_E_NONE - Operation successful 32679 * BCM_E_PARAM - Invalid input parameter value 32680 * BCM_E_UNAVAIL - Feature Not supported 32681 */ 32682 int 32683 bcm_esw_switch_dosattack_event_set( 32684 int unit, 32685 uint32 flags, 32686 bcm_switch_dosattack_event_t event, 32687 int arg) 32688 { 32689 int i = 0; 32690 int rv = BCM_E_NONE; 32691 uint32 enable = 0; 32692 uint32 dos_attack_fmt_buf[10]; 32693 uint32 data_buf[SOC_MAX_MEM_FIELD_WORDS] = {0}; 32694 soc_mem_t mem = INVALIDm; 32695 soc_field_t fmt_field = INVALIDf; 32696 soc_field_t mem_field[2] = {INVALIDf, INVALIDf}; 32697 soc_format_t fmt = INVALIDfmt; 32698 32699 if (!soc_feature(unit, soc_feature_broadscan_dos_ctrl)) { 32700 return BCM_E_UNAVAIL; 32701 } 32702 32703 /* Validate inputs */ 32704 if ((flags & ~(_BCM_SWITCH_DOSATTACK_VALID_FLAGS)) || 32705 (!(flags & BCM_SWITCH_DOSATTACK_FLOWTRACKER_PRESEL)) || 32706 (!(flags & _BCM_SWITCH_DOSATTACK_HDR))) { 32707 LOG_ERROR(BSL_LS_BCM_COMMON, (BSL_META_U(unit, 32708 "Wrong Input arguments\n\r"))); 32709 return BCM_E_PARAM; 32710 } 32711 32712 mem = HVE_DOS_ATTACK_MASKm; 32713 if (flags & BCM_SWITCH_DOSATTACK_OUTER_HDR) { 32714 mem_field[0] = PARSER1_FIXED_HVE_DOS_ATTACK_MASKf; 32715 } 32716 if (flags & BCM_SWITCH_DOSATTACK_INNER_HDR) { 32717 mem_field[1] = PARSER2_FIXED_HVE_DOS_ATTACK_MASKf; 32718 } 32719 32720 /* Get Format and format field */ 32721 rv = _bcm_esw_switch_dosattack_event_fmt_field_get(unit, 32722 event, &fmt, &fmt_field); 32723 if (BCM_FAILURE(rv)) { 32724 return rv; 32725 } 32726 enable = (arg > 0) ? 1 : 0; 32727 32728 rv = soc_mem_read(unit, mem, MEM_BLOCK_ANY, 0, data_buf); 32729 if (BCM_FAILURE(rv)) { 32730 return rv; 32731 } 32732 32733 for (i = 0; i < 2; i++) { 32734 if (mem_field[i] == INVALIDf) { 32735 continue; 32736 } 32737 sal_memset(&dos_attack_fmt_buf[0], 0, 10 * sizeof(uint32)); 32738 if (SOC_MEM_FIELD_VALID(unit, mem, mem_field[i])) { 32739 soc_mem_field_get(unit, mem, (void *) data_buf, 32740 mem_field[i], &dos_attack_fmt_buf[0]); 32741 32742 soc_format_field32_set(unit, fmt, 32743 &dos_attack_fmt_buf[0], fmt_field, enable); 32744 32745 soc_mem_field_set(unit, mem, (void *) data_buf, 32746 mem_field[i], &dos_attack_fmt_buf[0]); 32747 } 32748 } 32749 rv = soc_mem_write(unit, mem, MEM_BLOCK_ALL, 0, data_buf); 32750 32751 return rv; 32752 } 32753 32754 /* 32755 * Function: 32756 * bcm_esw_switch_dosattack_event_get 32757 * Purpose: 32758 * Get dos attack events for tracking purpose. 32759 * Parameters: 32760 * unit - (IN) BCM device number 32761 * flags - (IN) flags. 32762 * event - (IN) Dos attack event 32763 * arg - (OUT) arg 32764 * Returns: 32765 * BCM_E_NONE - Operation successful 32766 * BCM_E_PARAM - Invalid input parameter value 32767 * BCM_E_UNAVAIL - Feature Not supported 32768 */ 32769 int 32770 bcm_esw_switch_dosattack_event_get( 32771 int unit, 32772 uint32 flags, 32773 bcm_switch_dosattack_event_t event, 32774 int *arg) 32775 { 32776 int rv = BCM_E_NONE; 32777 uint32 enable = 0; 32778 uint32 dos_attack_fmt_buf[10]; 32779 uint32 data_buf[SOC_MAX_MEM_FIELD_WORDS] = {0}; 32780 uint32 hdr_flags_bits = 0; 32781 soc_mem_t mem = INVALIDm; 32782 soc_field_t fmt_field = INVALIDf; 32783 soc_field_t mem_field = INVALIDf; 32784 soc_format_t fmt = INVALIDfmt; 32785 32786 hdr_flags_bits = _shr_popcount(flags & _BCM_SWITCH_DOSATTACK_HDR); 32787 32788 if (!soc_feature(unit, soc_feature_broadscan_dos_ctrl)) { 32789 return BCM_E_UNAVAIL; 32790 } 32791 32792 /* Validate inputs */ 32793 if ((flags & ~(_BCM_SWITCH_DOSATTACK_VALID_FLAGS)) || 32794 (!(flags & BCM_SWITCH_DOSATTACK_FLOWTRACKER_PRESEL)) || 32795 (hdr_flags_bits != 1)) { 32796 LOG_ERROR(BSL_LS_BCM_COMMON, (BSL_META_U(unit, 32797 "Wrong Input arguments\n\r"))); 32798 return BCM_E_PARAM; 32799 } 32800 32801 mem = HVE_DOS_ATTACK_MASKm; 32802 if (flags & BCM_SWITCH_DOSATTACK_OUTER_HDR) { 32803 mem_field = PARSER1_FIXED_HVE_DOS_ATTACK_MASKf; 32804 } else if (flags & BCM_SWITCH_DOSATTACK_INNER_HDR) { 32805 mem_field = PARSER2_FIXED_HVE_DOS_ATTACK_MASKf; 32806 } 32807 32808 /* Get Format and format field */ 32809 rv = _bcm_esw_switch_dosattack_event_fmt_field_get(unit, 32810 event, &fmt, &fmt_field); 32811 if (BCM_FAILURE(rv)) { 32812 return rv; 32813 } 32814 32815 rv = soc_mem_read(unit, mem, MEM_BLOCK_ANY, 0, data_buf); 32816 if (BCM_FAILURE(rv)) { 32817 return rv; 32818 } 32819 sal_memset(&dos_attack_fmt_buf[0], 0, 10 * sizeof(uint32)); 32820 if (SOC_MEM_FIELD_VALID(unit, mem, mem_field)) { 32821 soc_mem_field_get(unit, mem, (void *) data_buf, 32822 mem_field, &dos_attack_fmt_buf[0]); 32823 32824 enable = soc_format_field32_get(unit, fmt, 32825 &dos_attack_fmt_buf[0], fmt_field); 32826 } 32827 32828 *arg = enable; 32829 32830 return rv; 32831 } 32832 32833 #if defined(BCM_HELIX5_SUPPORT) 32834 /* 32835 * Function: 32836 * _bcm_hx5_switch_dosattack_events_init 32837 * Purpose: 32838 * Set default as enable for dos attack event. 32839 * Parameters: 32840 * unit - (IN) BCM device number 32841 * Returns: 32842 * BCM_E_NONE - Operation successful 32843 */ 32844 int 32845 _bcm_hx5_switch_dosattack_events_init(int unit) 32846 { 32847 int event = 0; 32848 32849 for (event = bcmSwitchDosAttackEventMACSAEqualMACDA; 32850 event < bcmSwitchDosAttackEventCount; event++) { 32851 BCM_IF_ERROR_RETURN( 32852 bcm_esw_switch_dosattack_event_set(unit, 32853 (BCM_SWITCH_DOSATTACK_OUTER_HDR | 32854 BCM_SWITCH_DOSATTACK_INNER_HDR | 32855 BCM_SWITCH_DOSATTACK_FLOWTRACKER_PRESEL), 32856 event, TRUE)); 32857 } 32858 32859 BCM_IF_ERROR_RETURN( 32860 bcm_esw_switch_control_set(unit, bcmSwitchDosAttackTcpFlagsMask, 32861 TCP_FLAGS_MASK_DEFAULT)); 32862 BCM_IF_ERROR_RETURN( 32863 bcm_esw_switch_control_set(unit, bcmSwitchDosAttackInnerTcpFlagsMask, 32864 TCP_FLAGS_MASK_DEFAULT)); 32865 32866 return BCM_E_NONE; 32867 } 32868 #endif 32869