port.c (134907B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 #include <soc/defs.h> 10 #include <soc/debug.h> 11 #include <soc/drv.h> 12 #include <soc/mem.h> 13 14 #include <sal/core/time.h> 15 #include <shared/bsl.h> 16 #include <bcm/port.h> 17 #include <bcm/tx.h> 18 #include <bcm/error.h> 19 #include <bcm_int/esw/stack.h> 20 #include <bcm_int/esw/katana2.h> 21 #include <bcm_int/esw/saber2.h> 22 #include <bcm_int/esw/cosq.h> 23 #include <bcm_int/esw/triumph3.h> 24 #include <soc/katana2.h> 25 #include <soc/saber2.h> 26 #include <soc/phyreg.h> 27 #include <soc/ll.h> 28 29 #if defined(BCM_METROLITE_SUPPORT) 30 #include <soc/metrolite.h> 31 #endif 32 33 #if defined(BCM_SABER2_SUPPORT) 34 #include <bcm_int/esw_dispatch.h> 35 #include <bcm_int/esw/katana.h> 36 #include <bcm_int/esw/katana2.h> 37 #include <bcm_int/esw/virtual.h> 38 #include <bcm_int/common/sat.h> 39 40 static uint32 sb2_port_lanes_unchanged; 41 static uint32 new_tdm[SB2_TDM_MAX_SIZE] = {0}; 42 extern int block_max_startaddr[SB2_MAX_BLOCKS]; 43 extern int block_max_endaddr[SB2_MAX_BLOCKS]; 44 extern sb2_port_to_block_subports_t *sb2_port_to_block_subports[SOC_MAX_NUM_DEVICES]; 45 extern int _sb2_config_id[SOC_MAX_NUM_DEVICES]; 46 extern sb2_speed_t *bcm56260_speed[SOC_MAX_NUM_DEVICES]; 47 extern int eagle_n4s_mode; 48 extern int eagle_n2_mode; 49 extern int eagle_4ge_mode; 50 51 #if defined(BCM_METROLITE_SUPPORT) 52 extern ml_speed_t *bcm56270_speed[SOC_MAX_NUM_DEVICES]; 53 #endif 54 extern int _bcm_sb2_ipmc_port_ext_queue_count(int unit, int ipmc_id, bcm_port_t port); 55 extern int _bcm_kt2_ipmc_subscriber_egress_queue_ext_set(int unit, int port, int ipmc_id, int ext_mem_enable); 56 57 #define SB2_SPEED_MODE_LINK_1G 2 58 #define SB2_SPEED_MODE_LINK_2G5 3 59 #define SB2_SPEED_MODE_LINK_10G_PLUS 4 60 61 int 62 _bcm_sb2_port_sw_info_display(int unit, bcm_port_t port) { 63 64 int rv = 0; 65 soc_info_t *si = &SOC_INFO(unit); 66 int lanes; 67 uint8 block; 68 int enable; 69 int speed; 70 int link; 71 int autoneg; 72 int discard_mode; 73 int loopback_mode; 74 int master_mode; 75 int encap_mode = BCM_PORT_ENCAP_COUNT; 76 char *discard[] = {"NONE", "ALL", "UNTAG", "TAG"}; 77 char *loopback[] = {"NONE", "MAC", "PHY", "RMT", "C57"}; 78 char *master[] = {"SLAVE", "MASTER", "AUTO", "NONE"}; 79 char *encap[] = {"IEEE", "HIGIG", "B5632", "HIGIG2", "HIGIG-Lite"}; 80 81 rv += (_bcm_sb2_port_lanes_get(unit, port, &lanes)); 82 rv += (soc_saber2_get_port_block(unit,port,&block)); 83 rv += (bcm_esw_port_enable_get(unit, port, &enable)); 84 rv += (bcm_esw_port_autoneg_get(unit, port, &autoneg)); 85 rv += (bcm_esw_port_speed_get(unit, port, &speed)); 86 rv += (bcm_esw_port_link_status_get(unit, port, &link)); 87 rv += (bcm_esw_port_discard_get(unit, port, &discard_mode)); 88 rv += (bcm_esw_port_loopback_get(unit, port, &loopback_mode)); 89 rv += (bcm_esw_port_master_get(unit, port, &master_mode)); 90 rv += (bcm_esw_port_encap_get(unit, port, &encap_mode)); 91 92 if (rv < 0) { 93 LOG_CLI((BSL_META_U(unit, "\n\n Some parameters not set properly !!"))); 94 } 95 LOG_CLI((BSL_META_U(unit, "\n\n SOFTWARE PORT CONFIGURATION :\n"))); 96 LOG_CLI((BSL_META_U(unit, "------------------------------------"))); 97 LOG_CLI((BSL_META_U(unit, "\n Port Name\t\t:\t%s"),si->port_name[port])); 98 LOG_CLI((BSL_META_U(unit, "\n Block ID\t\t:\t%d"), block)); 99 LOG_CLI((BSL_META_U(unit, "\n Lane Number\t\t:\t%d "),lanes)); 100 LOG_CLI((BSL_META_U(unit, "\n Current Speed\t\t:\t%d"), speed)); 101 LOG_CLI((BSL_META_U(unit, "\n Max speed\t\t:\t%d"),si->port_speed_max[port])); 102 LOG_CLI((BSL_META_U(unit, "\n Speed\t\t\t:\t%d"),((* 103 sb2_port_speeds[unit])[block][lanes-1]))); 104 LOG_CLI((BSL_META_U(unit, "\n Port status \t\t:\t%s"),(enable ? "ENABLED" : "DISABLED"))); 105 LOG_CLI((BSL_META_U(unit, "\n Link status\t\t:\t%s"),(link ? "UP" : "DOWN"))); 106 LOG_CLI((BSL_META_U(unit, "\n Autoneg status\t\t:\t%s"),(autoneg ? "TRUE" : "FALSE"))); 107 LOG_CLI((BSL_META_U(unit, "\n Discard Type\t\t:\t%s"),(discard_mode <= 3 ? discard[discard_mode] : "INVALID"))); 108 LOG_CLI((BSL_META_U(unit, "\n Loopback Mode\t\t:\t%s"),(loopback_mode <= 4 ? loopback[loopback_mode] : "INVALID"))); 109 LOG_CLI((BSL_META_U(unit, "\n Master Status\t\t:\t%s"),(master_mode <= 3 ? master[master_mode] : "INVALID"))); 110 LOG_CLI((BSL_META_U(unit, "\n Encapsulation \t\t:\t%s"),(encap_mode <= 4 ? encap[encap_mode] : "INVALID"))); 111 LOG_CLI((BSL_META_U(unit, "\n\n*********************************************** \n\n"))); 112 113 return BCM_E_NONE; 114 115 } 116 117 int 118 _bcm_sb2_port_hw_info_display(int unit, bcm_port_t port) { 119 120 uint32 rval = 0; 121 uint64 rval_64; 122 int lanes = 0; 123 uint8 mxqblock; 124 int port0, port1, port2, port3; 125 int higig, higig2; 126 int core_mode, phy_mode; 127 int tx_en, rx_en, ipg_check_disable, lpbk_leak; 128 int soft_reset, rs_soft_reset, sw_link, link_status_select; 129 int hdr_mode, sop_crc, speed_mode; 130 int port_enable; 131 egr_enable_entry_t egr_en; 132 133 char *phy[] = {"Single", "Dual", "Quad"}; 134 char *core[] = {"Single", "Dual", "Quad"}; 135 char *enable[] = {"DISABLED", "ENABLED"}; 136 char *active[] = {"INACTIVE", "ACTIVE"}; 137 char *link_sel[] = {"SOFTWARE", "STRAP-PIN"}; 138 char *hdr[] = {"IEEE", "HG+", "HG2", "CLH", "SCH", "SOP ONLY IEEE"}; 139 char *speed[] = {"10Mpbps", "100Mbps", "1Gbps", "2.5Gbps", ">=10Gbps"}; 140 141 BCM_IF_ERROR_RETURN(_bcm_sb2_port_lanes_get(unit, port, &lanes)); 142 BCM_IF_ERROR_RETURN(soc_saber2_get_port_block(unit, port, &mxqblock)); 143 144 LOG_CLI((BSL_META_U(unit, "\n\n HARDWARE PORT CONFIGURATION : \n"))); 145 LOG_CLI((BSL_META_U(unit, "--------------------------------------\n"))); 146 147 /* XPORT_MODE_REG */ 148 if (SOC_REG_PORT_VALID(unit, XPORT_MODE_REGr, port)) { 149 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, port, &rval)); 150 phy_mode = soc_reg_field_get(unit, XPORT_MODE_REGr, rval, PHY_PORT_MODEf); 151 LOG_CLI((BSL_META_U(unit, "\n XPORT MODE "))); 152 LOG_CLI((BSL_META_U(unit, "\n Phy Mode\t:\t%s"), phy[phy_mode])); 153 } 154 155 /* XLPORT_MODE_REG */ 156 if (SOC_REG_PORT_VALID(unit, XLPORT_MODE_REGr, port)) { 157 SOC_IF_ERROR_RETURN(READ_XLPORT_MODE_REGr(unit, port, &rval)); 158 core_mode = soc_reg_field_get(unit, XLPORT_MODE_REGr, rval, 159 XPORT0_CORE_PORT_MODEf); 160 phy_mode = soc_reg_field_get(unit, XLPORT_MODE_REGr, rval, 161 XPORT0_PHY_PORT_MODEf); 162 LOG_CLI((BSL_META_U(unit, "\n XPORT MODE "))); 163 LOG_CLI((BSL_META_U(unit, "\n Core Mode\t:\t%s"), core[core_mode])); 164 LOG_CLI((BSL_META_U(unit, "\n Phy Mode\t:\t%s"), phy[phy_mode])); 165 } 166 167 /* XPORT_PORT_ENABLE */ 168 if (SOC_REG_PORT_VALID(unit, XPORT_PORT_ENABLEr, port)) { 169 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr(unit, port, &rval)); 170 port0 = soc_reg_field_get(unit, XPORT_PORT_ENABLEr, rval, PORT0f); 171 port1 = soc_reg_field_get(unit, XPORT_PORT_ENABLEr, rval, PORT1f); 172 port2 = soc_reg_field_get(unit, XPORT_PORT_ENABLEr, rval, PORT2f); 173 port3 = soc_reg_field_get(unit, XPORT_PORT_ENABLEr, rval, PORT3f); 174 LOG_CLI((BSL_META_U(unit, "\n\n XPORT PORT ENABLE "))); 175 LOG_CLI((BSL_META_U(unit, "\n MxQBlock\t:\t%d\n Port0\t\t:\t%s\n Port1\t\t:\t%s" 176 "\n Port2\t\t:\t%s\n Port3\t\t:\t%s"), mxqblock, \ 177 enable[port0], enable[port1], enable[port2], enable[port3])); 178 } 179 180 /* XLPORT_ENABLE_REG */ 181 if (SOC_REG_PORT_VALID(unit, XLPORT_ENABLE_REGr, port)) { 182 SOC_IF_ERROR_RETURN(READ_XLPORT_ENABLE_REGr(unit, port, &rval)); 183 port0 = soc_reg_field_get(unit, XLPORT_ENABLE_REGr, rval, PORT0f); 184 port1 = soc_reg_field_get(unit, XLPORT_ENABLE_REGr, rval, PORT1f); 185 port2 = soc_reg_field_get(unit, XLPORT_ENABLE_REGr, rval, PORT2f); 186 port3 = soc_reg_field_get(unit, XLPORT_ENABLE_REGr, rval, PORT3f); 187 LOG_CLI((BSL_META_U(unit, "\n\n XLPORT PORT ENABLE "))); 188 LOG_CLI((BSL_META_U(unit, "\n MxQBlock\t:\t%d\n Port0\t\t:\t%s\n Port1\t\t:\t%s" 189 "\n Port2\t\t:\t%s\n Port3\t\t:\t%s"), mxqblock, \ 190 enable[port0], enable[port1], enable[port2], enable[port3])); 191 } 192 193 /* XPORT_CONFIG */ 194 if (SOC_REG_PORT_VALID(unit, XPORT_CONFIGr, port)) { 195 SOC_IF_ERROR_RETURN(READ_XPORT_CONFIGr(unit, port, &rval)); 196 higig = soc_reg_field_get(unit, XPORT_CONFIGr, rval, HIGIG_MODEf); 197 higig2 = soc_reg_field_get(unit, XPORT_CONFIGr, rval, HIGIG2_MODEf); 198 LOG_CLI((BSL_META_U(unit, "\n\n XPORT CONFIG "))); 199 LOG_CLI((BSL_META_U(unit, "\n HiGig\t\t:\t%s"), enable[higig])); 200 LOG_CLI((BSL_META_U(unit, "\n HiGig2\t\t:\t%s"), enable[higig2])); 201 } 202 203 /* XLPORT_CONFIG */ 204 if (SOC_REG_PORT_VALID(unit, XLPORT_CONFIGr, port)) { 205 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 206 higig = soc_reg_field_get(unit, XLPORT_CONFIGr, rval, HIGIG_MODEf); 207 higig2 = soc_reg_field_get(unit, XLPORT_CONFIGr, rval, HIGIG2_MODEf); 208 LOG_CLI((BSL_META_U(unit, "\n\n XLPORT CONFIG "))); 209 LOG_CLI((BSL_META_U(unit, "\n HiGig\t\t:\t%s"), enable[higig])); 210 LOG_CLI((BSL_META_U(unit, "\n HiGig2\t\t:\t%s"), enable[higig2])); 211 } 212 213 /* XLMAC_CTRL */ 214 SOC_IF_ERROR_RETURN(READ_XLMAC_CTRLr(unit, port, &rval_64)); 215 tx_en = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, TX_ENf); 216 rx_en = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, RX_ENf); 217 soft_reset = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, SOFT_RESETf); 218 rs_soft_reset = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, RS_SOFT_RESETf); 219 lpbk_leak = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, LOCAL_LPBK_LEAK_ENBf); 220 sw_link = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, SW_LINK_STATUSf); 221 link_status_select = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, 222 LINK_STATUS_SELECTf); 223 ipg_check_disable = soc_reg64_field32_get(unit, XLMAC_CTRLr, rval_64, 224 XGMII_IPG_CHECK_DISABLEf); 225 LOG_CLI((BSL_META_U(unit, "\n\n XMAC CTRL"))); 226 LOG_CLI((BSL_META_U(unit, "\n Tx\t \t\t:\t%s"), enable[tx_en])); 227 LOG_CLI((BSL_META_U(unit, "\n Rx \t\t\t:\t%s"), enable[rx_en])); 228 LOG_CLI((BSL_META_U(unit, "\n Soft Reset\t\t:\t%s"),enable[soft_reset])); 229 LOG_CLI((BSL_META_U(unit, "\n RS Soft Reset\t\t:\t%s"), enable[rs_soft_reset])); 230 LOG_CLI((BSL_META_U(unit, "\n RS Soft Reset\t\t:\t%s"), enable[rs_soft_reset])); 231 LOG_CLI((BSL_META_U(unit, "\n Lpbk Leak(Local)\t:\t%s"), enable[lpbk_leak])); 232 LOG_CLI((BSL_META_U(unit, "\n SW Link Status\t\t:\t%s"), active[sw_link])); 233 LOG_CLI((BSL_META_U(unit, "\n Link Status Select\t:\t%s"), link_sel[link_status_select])); 234 LOG_CLI((BSL_META_U(unit, "\n ipg check disable\t:\t%s"), enable[ipg_check_disable])); 235 236 /* XLMAC_MODE*/ 237 SOC_IF_ERROR_RETURN(READ_XLMAC_MODEr(unit, port, &rval_64)); 238 hdr_mode = soc_reg64_field32_get(unit, XLMAC_MODEr, rval_64, HDR_MODEf); 239 sop_crc = soc_reg64_field32_get(unit, XLMAC_MODEr, rval_64, NO_SOP_FOR_CRC_HGf); 240 speed_mode = soc_reg64_field32_get(unit, XLMAC_MODEr, rval_64, SPEED_MODEf); 241 LOG_CLI((BSL_META_U(unit, "\n\n XMAC MODE"))); 242 LOG_CLI((BSL_META_U(unit, "\n Header Mode\t\t:\t%s"),hdr[hdr_mode])); 243 LOG_CLI((BSL_META_U(unit, "\n SOP for CRC in HG\t:\t%s"), 244 (sop_crc ? "EXCLUDE" : "INCLUDE"))); 245 LOG_CLI((BSL_META_U(unit, "\n Speed Mode\t\t:\t%s"), speed[speed_mode])); 246 247 /* EGR_ENABLE */ 248 SOC_IF_ERROR_RETURN(READ_EGR_ENABLEm(unit, SOC_BLOCK_ANY, port, &egr_en)); 249 port_enable = soc_EGR_ENABLEm_field32_get(unit, &egr_en, PRT_ENABLEf); 250 LOG_CLI((BSL_META_U(unit, "\n\n EGR ENABLE"))); 251 LOG_CLI((BSL_META_U(unit, "\n Port\t\t:\t%s\n\n"),enable[port_enable])); 252 253 return BCM_E_NONE; 254 255 } 256 257 /* 258 * Feature implementation is based on KT2 approach. 259 * So changing the lanes convention as per the implementation. 260 * lanes = 4 --> 4 active ports in the port block.(Eg : 4 ge ports) 261 * lanes = 1 --> 1 active port in the port block.(Eg : 1 xe port) 262 */ 263 int 264 _bcm_kt2_lanes_convention(int *lanes) { 265 266 switch(*lanes) { 267 case 1 : *lanes = 4; 268 break; 269 case 2 : *lanes = 2; 270 break; 271 case 4 : *lanes = 1; 272 break; 273 default : return BCM_E_PARAM; 274 } 275 return BCM_E_NONE; 276 } 277 278 int 279 _bcm_sb2_port_lanes_set_post_operation(int unit, bcm_port_t port) 280 { 281 soc_error_t rv = BCM_E_NONE; 282 uint8 loop = 0; 283 uint8 block = 0; 284 uint8 block_port = 0; 285 int mode = 0; 286 int new_lanes = 0; 287 int port_enable = 0; 288 int speed=0, max_speed=0; 289 290 if (sb2_port_lanes_unchanged) { 291 return BCM_E_NONE; 292 } 293 294 SOC_IF_ERROR_RETURN(soc_saber2_get_port_block( 295 unit, port, &block)); 296 SOC_IF_ERROR_RETURN(_bcm_sb2_port_lanes_get( 297 unit, port,&new_lanes)); 298 BCM_IF_ERROR_RETURN(_bcm_kt2_lanes_convention(&new_lanes)); 299 300 #ifdef BCM_PORT_DEFAULT_DISABLE 301 port_enable = FALSE; 302 #else 303 port_enable = TRUE; 304 #endif /* BCM_PORT_DEFAULT_DISABLE */ 305 306 for (loop = 0;loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 307 block_port=(*sb2_block_ports[unit])[block][loop]; 308 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 309 SOC_IF_ERROR_RETURN(bcm_esw_linkscan_mode_get( 310 unit, block_port, &mode)); 311 312 if (mode == BCM_LINKSCAN_MODE_NONE) { 313 BCM_IF_ERROR_RETURN(bcm_esw_linkscan_mode_set( 314 unit, block_port, BCM_LINKSCAN_MODE_SW)); 315 } 316 317 BCM_IF_ERROR_RETURN(bcm_esw_port_enable_set(unit, 318 block_port, port_enable)); 319 320 if (block < 6) { 321 speed = (*sb2_port_speeds[unit])[block][new_lanes-1]; 322 } else { 323 /* Add exception for eagle port due to mixed mode */ 324 soc_saber2_xl_port_speed_get(unit, block_port, &speed); 325 } 326 327 BCM_IF_ERROR_RETURN(bcm_esw_port_speed_max(unit, 328 block_port, &max_speed)); 329 speed = speed > max_speed ? max_speed : speed; 330 rv = bcm_esw_port_speed_set(unit, block_port, speed); 331 SOC_IF_ERROR_RETURN(rv); 332 333 BCM_IF_ERROR_RETURN(bcm_esw_port_learn_set(unit, 334 block_port, 335 BCM_PORT_LEARN_ARL | BCM_PORT_LEARN_FWD)); 336 BCM_IF_ERROR_RETURN(bcm_esw_port_stp_set( 337 unit, block_port, BCM_STG_STP_FORWARD)); 338 339 BCM_IF_ERROR_RETURN(bcm_esw_port_loopback_set(unit, 340 block_port, BCM_PORT_LOOPBACK_NONE)); 341 } /* if SOC_PBMP_MEMBER */ 342 } /* For loop */ 343 344 return BCM_E_NONE; 345 } 346 347 void soc_saber2_pbmp_add(int unit,soc_port_t port,int block, 348 int speed, int new_lanes) { 349 int blk=0; 350 soc_info_t *si = &SOC_INFO(unit); 351 soc_pbmp_t my_pbmp_xport_xe; 352 soc_pbmp_t my_pbmp_xport_ge; 353 354 blk = SOC_DRIVER(unit)->port_info[port].blk; 355 SOC_PBMP_PORT_ADD(si->block_bitmap[blk],port); 356 357 if (block < 6) { 358 /* mxq ports */ 359 if (speed == 10000) { 360 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 361 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, port); 362 } else { 363 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 364 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, port); 365 } 366 SOC_PBMP_PORT_ADD(si->ether.bitmap, port); 367 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, port); 368 369 SOC_PBMP_PORT_ADD(si->mxq.bitmap, port); 370 SOC_PBMP_PORT_REMOVE(si->mxq.disabled_bitmap, port); 371 372 SOC_PBMP_PORT_ADD(si->port.bitmap, port); 373 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, port); 374 375 SOC_PBMP_PORT_ADD(si->all.bitmap, port); 376 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, port); 377 378 SOC_PORT_TYPE(unit,port)=SOC_BLK_MXQPORT; 379 si->port_speed_max[port] = speed; 380 } else if (block == 6) { 381 /* xl ports */ 382 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 383 SOC_PBMP_CLEAR(my_pbmp_xport_ge); 384 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 385 my_pbmp_xport_xe); 386 my_pbmp_xport_ge = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_GE, 387 my_pbmp_xport_ge); 388 389 si->port_speed_max[port] = speed; 390 SOC_PBMP_PORT_ADD(si->xl.bitmap, port); 391 SOC_PBMP_PORT_REMOVE(si->xl.disabled_bitmap, port); 392 393 /* On XL port speed 2.5G can mean pbmp_xport_ge config or HGL port */ 394 if (SOC_PBMP_MEMBER(my_pbmp_xport_ge, port) && 395 (new_lanes == 4)) { 396 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 397 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, port); 398 si->port_speed_max[port] = 2500; 399 } else if (SOC_PBMP_MEMBER(my_pbmp_xport_xe, port) || 400 (speed < 2500) || (eagle_n4s_mode && (new_lanes == 4))) { 401 if (speed == 10000) { 402 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 403 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, port); 404 } else if (SOC_PBMP_MEMBER(my_pbmp_xport_xe, port) && 405 (new_lanes != 4)) { 406 if(speed <= 2500) { 407 si->port_speed_max[port] = 11000; 408 } 409 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 410 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, port); 411 } else { 412 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 413 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, port); 414 } 415 } else if (SOC_PBMP_MEMBER(my_pbmp_xport_ge, port) && 416 (new_lanes == 4)) { 417 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 418 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, port); 419 si->port_speed_max[port] = 2500; 420 } else { 421 if(speed <= 2500) { 422 /* The port has been migrated from ge to hg. 423 * Change speed accordingly. 424 */ 425 si->port_speed_max[port] = 11000; 426 } 427 SOC_PBMP_PORT_ADD(si->hg.bitmap, port); 428 SOC_PBMP_PORT_ADD(si->st.bitmap, port); 429 SOC_PBMP_PORT_REMOVE(si->hg.disabled_bitmap, port); 430 SOC_PBMP_PORT_REMOVE(si->st.disabled_bitmap, port); 431 } 432 433 SOC_PBMP_PORT_ADD(si->ether.bitmap, port); 434 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, port); 435 436 SOC_PBMP_PORT_ADD(si->port.bitmap, port); 437 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, port); 438 439 SOC_PBMP_PORT_ADD(si->all.bitmap, port); 440 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, port); 441 442 SOC_PORT_TYPE(unit,port)=SOC_BLK_XLPORT; 443 } 444 } 445 446 int _bcm_sb2_update_port_mode(int unit,uint8 port,int speed) { 447 uint32 rval; 448 uint8 block; 449 bcmMxqPhyPortMode_t phy_mode = -1; 450 bcmXlCorePortMode_t core_mode_xl = -1; 451 bcmXlPhyPortMode_t phy_mode_xl = -1; 452 453 SOC_IF_ERROR_RETURN(soc_saber2_get_port_block( 454 unit, port, &block)); 455 456 if(IS_MXQ_PORT(unit, port)) { 457 SOC_IF_ERROR_RETURN(soc_saber2_get_mxq_phy_port_mode( 458 unit, port, speed, &phy_mode)); 459 if(phy_mode == -1) { 460 return BCM_E_FAIL; 461 } 462 } 463 if (SOC_REG_PORT_VALID(unit, XPORT_MODE_REGr, port)) { 464 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, port, &rval)); 465 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, PHY_PORT_MODEf, phy_mode); 466 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 467 PORT_GMII_MII_ENABLEf, (speed >= 10000) ? 0 : 1); 468 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, port, rval)); 469 } 470 471 if(IS_XL_PORT(unit, port)) { 472 SOC_IF_ERROR_RETURN(soc_saber2_get_xl_phy_core_port_mode(unit, port, 473 &phy_mode_xl, &core_mode_xl)); 474 if((phy_mode_xl == -1) || (core_mode_xl == -1)){ 475 return BCM_E_FAIL; 476 } 477 } 478 if (SOC_REG_PORT_VALID(unit, XLPORT_MODE_REGr, port)) { 479 SOC_IF_ERROR_RETURN(READ_XLPORT_MODE_REGr(unit, port, &rval)); 480 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 481 EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1); 482 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 483 XPORT0_CORE_PORT_MODEf,core_mode_xl); 484 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 485 XPORT0_PHY_PORT_MODEf, phy_mode_xl); 486 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 487 } 488 489 return BCM_E_NONE; 490 } 491 492 soc_error_t soc_saber2_port_detach(int unit,uint8 block_port) { 493 494 soc_linkscan_pause(unit); 495 496 SOC_IF_ERROR_CLEAN_RETURN((soc_phyctrl_enable_set(unit, block_port, 1)), 497 soc_linkscan_continue(unit)); 498 499 SOC_IF_ERROR_CLEAN_RETURN((soc_phyctrl_detach(unit, block_port)), 500 soc_linkscan_continue(unit)); 501 502 PHY_FLAGS_CLR_ALL(unit, block_port); 503 504 soc_linkscan_continue(unit); 505 return BCM_E_NONE; 506 } 507 508 soc_error_t soc_saber2_port_attach( 509 int unit, uint8 block, uint8 block_port ) { 510 uint16 phy_addr=0; 511 uint16 phy_addr_int=0; 512 int okay = 0; 513 uint64 rval64; 514 515 soc_linkscan_pause(unit); 516 517 #ifdef BCM_METROLITE_SUPPORT 518 if (SOC_IS_METROLITE(unit)){ 519 _ml_phy_addr_default(unit, block_port, 520 &phy_addr, &phy_addr_int); 521 }else 522 #endif 523 { 524 _saber2_phy_addr_default(unit, block_port, 525 &phy_addr, &phy_addr_int); 526 } 527 SOC_IF_ERROR_CLEAN_RETURN 528 (soc_phy_cfg_addr_set(unit,block_port,0, phy_addr), 529 soc_linkscan_continue(unit)); 530 SOC_IF_ERROR_CLEAN_RETURN 531 (soc_phy_cfg_addr_set(unit,block_port,SOC_PHY_INTERNAL, 532 phy_addr_int), soc_linkscan_continue(unit)); 533 PHY_ADDR(unit, block_port) = phy_addr; 534 PHY_ADDR_INT(unit, block_port) = phy_addr_int; 535 SOC_IF_ERROR_CLEAN_RETURN(_bcm_port_probe(unit, block_port, &okay), 536 soc_linkscan_continue(unit)); 537 if (!okay) { 538 soc_linkscan_continue(unit); 539 return BCM_E_INTERNAL; 540 } 541 542 SOC_IF_ERROR_CLEAN_RETURN(_bcm_port_mode_setup(unit, block_port, FALSE), 543 soc_linkscan_continue(unit)); 544 545 /* _bcm_port_probe() sets the encap only on MAC and not on PHY. 546 * Resetting the mac encap to allow 547 * bcm_esw_port_encap() function to set encap on both MAC and PHY 548 */ 549 if (IS_HG_PORT(unit, block_port)) { 550 SOC_IF_ERROR_CLEAN_RETURN(READ_XLMAC_MODEr(unit,block_port, &rval64), 551 soc_linkscan_continue(unit)); 552 soc_reg64_field32_set(unit, XLMAC_MODEr, &rval64, HDR_MODEf, 0); 553 SOC_IF_ERROR_CLEAN_RETURN(WRITE_XLMAC_MODEr(unit,block_port, rval64), 554 soc_linkscan_continue(unit)); 555 bcm_esw_port_encap_set(unit, block_port, BCM_PORT_ENCAP_HIGIG); 556 } else { 557 SOC_IF_ERROR_CLEAN_RETURN(READ_XLMAC_MODEr(unit,block_port, &rval64), 558 soc_linkscan_continue(unit)); 559 soc_reg64_field32_set(unit, XLMAC_MODEr, &rval64, HDR_MODEf, 1); 560 SOC_IF_ERROR_CLEAN_RETURN(WRITE_XLMAC_MODEr(unit,block_port, rval64), 561 soc_linkscan_continue(unit)); 562 bcm_esw_port_encap_set(unit, block_port, BCM_PORT_ENCAP_IEEE); 563 } 564 565 if (BCM_FAILURE(_soc_linkscan_hw_port_init(unit, block_port))) { 566 LOG_ERROR(BSL_LS_BCM_PORT, 567 (BSL_META_U(unit, 568 "HW linkscan port init failed for port[%d]\n"), block_port)); 569 } 570 soc_linkscan_continue(unit); 571 572 return BCM_E_NONE; 573 } 574 575 int _bcm_sb2_port_lanes_set(int unit, bcm_port_t port, int lanes) 576 { 577 uint32 start_addr=0; 578 uint32 end_addr=0; 579 soc_pbmp_t link_pbmp; 580 uint32 time_multiplier=1; 581 uint64 rval64 ; 582 uint32 rval = 0, rval1 = 0; 583 uint32 cell_cnt = 0; 584 uint32 try = 0 , try_count = 0; 585 soc_timeout_t to = {0}; 586 sal_usecs_t timeout_usec = 100000; 587 int min_polls = 100; 588 uint32 pfc_enable=0; 589 uint8 old_ports[][SB2_MAX_PORTS_PER_BLOCK]= 590 {{1,0,0,0},{1,0,3,0},{0,0,0,0},{1,2,3,4}}; 591 uint8 new_ports[][SB2_MAX_PORTS_PER_BLOCK]= 592 {{1,0,0,0},{1,0,3,0},{0,0,0,0},{1,2,3,4}}; 593 uint8 new_port_mode[5]={0,1,2,0,3}; 594 soc_info_t *si = &SOC_INFO(unit); 595 uint8 block = 0; 596 uint8 block_port = 0, first_port = 0; 597 uint8 try_loop = 0; 598 uint8 loop = 0; 599 int old_lanes = 0; 600 int new_lanes; 601 int config_lanes = lanes; 602 soc_field_t port_intf_reset_fld[] = { 603 XQ1_PORT_INTF_RESETf, 604 XQ2_PORT_INTF_RESETf, XQ3_PORT_INTF_RESETf, 605 XQ4_PORT_INTF_RESETf, XQ5_PORT_INTF_RESETf, 606 XQ6_PORT_INTF_RESETf, XQ7_PORT_INTF_RESETf, 607 XQ8_PORT_INTF_RESETf, XQ9_PORT_INTF_RESETf}; 608 soc_field_t mmu_intf_reset_fld[] = { 609 XQ1_MMU_INTF_RESETf, 610 XQ2_MMU_INTF_RESETf, XQ3_MMU_INTF_RESETf, 611 XQ4_MMU_INTF_RESETf, XQ5_MMU_INTF_RESETf, 612 XQ6_MMU_INTF_RESETf, XQ7_MMU_INTF_RESETf, 613 XQ8_MMU_INTF_RESETf, XQ9_MMU_INTF_RESETf}; 614 soc_field_t new_port_mode_fld[] = { 615 XQ1_NEW_PORT_MODEf, 616 XQ2_NEW_PORT_MODEf, XQ3_NEW_PORT_MODEf, 617 XQ4_NEW_PORT_MODEf, XQ5_NEW_PORT_MODEf, 618 XQ6_NEW_PORT_MODEf, XQ7_NEW_PORT_MODEf, 619 XQ8_NEW_PORT_MODEf, XQ9_NEW_PORT_MODEf}; 620 int port_speed = 0; 621 uint8 tdm_ports[4] = {0}; 622 uint8 index = 0; 623 uint32 pos = 0; 624 uint32 egr_fifo_depth = 0; 625 int threshold; 626 int port_bw, start_threshold = 0; 627 int block_max_nxtaddr; 628 #if defined(SABER2_DEBUG) 629 char config_str[80]; 630 uint8 lane_incr[SB2_MAX_PORTS_PER_BLOCK]={4,2,0,1}; 631 int auto_portgroup=0; 632 int portgroup=0; 633 #endif 634 soc_field_t port_enable_field[SB2_MAX_PORTS_PER_BLOCK]= 635 {PORT0f, PORT1f, PORT2f , PORT3f}; 636 int init_mode = 0; 637 int port_enable = 0; 638 egr_enable_entry_t egr_enable_entry = {{0}}; 639 int block_speed=0, max_speed=0, length_check; 640 uint64 xlmac_ctrl; 641 epc_link_bmap_entry_t epc_link_bmap_entry={{0}}; 642 txlp_port_addr_map_table_entry_t txlp_port_addr_map_table_entry={{0}}; 643 uint64 ctr_val; 644 645 sb2_port_lanes_unchanged = FALSE; 646 647 if (!SOC_PORT_VALID(unit, port)) { 648 return BCM_E_PORT; 649 } 650 if (SAL_BOOT_QUICKTURN) { 651 time_multiplier=1000; 652 } 653 654 BCM_IF_ERROR_RETURN(_bcm_kt2_lanes_convention(&lanes)); 655 new_lanes = lanes; 656 if (IS_MXQ_PORT(unit, port)) { 657 if ((new_lanes != 1) && (new_lanes != 4)) { 658 return BCM_E_PARAM; 659 } 660 } else if(IS_XL_PORT(unit, port)) { 661 if ((new_lanes != 1) && (new_lanes != 2) && (new_lanes != 4)) { 662 return BCM_E_PARAM; 663 } 664 if (eagle_4ge_mode) { 665 LOG_ERROR(BSL_LS_BCM_PORT, 666 (BSL_META_U(unit, 667 "Flex operation not supported port %d cfg %d\n"), 668 port, _sb2_config_id[unit])); 669 return BCM_E_PARAM; 670 } 671 if ((new_lanes == 4) && (eagle_n2_mode)) { 672 LOG_ERROR(BSL_LS_BCM_PORT, 673 (BSL_META_U(unit, 674 "Lane 4 not supported on N2 flex unit %d: port %d cfg %d\n"), 675 unit, port, _sb2_config_id[unit])); 676 return BCM_E_PARAM; 677 } 678 } 679 680 SOC_IF_ERROR_RETURN(soc_saber2_get_port_block( 681 unit,port,&block)); 682 SOC_IF_ERROR_RETURN(_bcm_sb2_port_lanes_get( 683 unit,port,&old_lanes)); 684 BCM_IF_ERROR_RETURN(_bcm_kt2_lanes_convention(&old_lanes)); 685 686 if(old_lanes == new_lanes) { 687 sb2_port_lanes_unchanged = TRUE; 688 return BCM_E_NONE; 689 } 690 691 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 692 if ((IS_LP_PORT(unit, (*sb2_block_ports[unit])[block][loop])) || 693 (IS_SUBTAG_PORT(unit, (*sb2_block_ports[unit])[block][loop]))) { 694 LOG_CLI((BSL_META_U(unit, 695 "HotSwap is not supported for \ 696 Subport Coe/LinkPhy Ports\n Disable CoE and run the API again.\n"))); 697 return BCM_E_PARAM; 698 } 699 } 700 701 block_speed = 0; 702 for (loop = 0;loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 703 block_port=(*sb2_block_ports[unit])[block][loop]; 704 max_speed = bcm56260_speed[unit][_sb2_config_id[unit]][block_port - 1]; 705 if((IS_HG_PORT(unit, block_port)) && (max_speed == 10000)) { 706 max_speed = 11000; 707 } 708 block_speed += max_speed; 709 } 710 if (block_speed < (*sb2_port_speeds[unit])[block][new_lanes-1]) { 711 LOG_CLI((BSL_META_U(unit, 712 "Total BW of block %d is less than %d\n"),block_speed, 713 (*sb2_port_speeds[unit])[block][new_lanes-1])); 714 return BCM_E_PARAM; 715 } 716 717 if (new_lanes == 1) { 718 if(!(IS_XL_PORT(unit, port))) { 719 tdm_ports[0] = (*sb2_block_ports[unit])[block][0]; 720 tdm_ports[1] = (*sb2_block_ports[unit])[block][0]; 721 tdm_ports[2] = (*sb2_block_ports[unit])[block][0]; 722 tdm_ports[3] = (*sb2_block_ports[unit])[block][0]; 723 } 724 } 725 726 if (new_lanes == 2) { 727 if(!(IS_XL_PORT(unit, port))) { 728 tdm_ports[0] = (*sb2_block_ports[unit])[block][0]; 729 tdm_ports[1] = (*sb2_block_ports[unit])[block][2]; 730 tdm_ports[2] = (*sb2_block_ports[unit])[block][0]; 731 tdm_ports[3] = (*sb2_block_ports[unit])[block][2]; 732 } 733 } 734 735 if (new_lanes == 4) { 736 tdm_ports[0] = (*sb2_block_ports[unit])[block][0]; 737 tdm_ports[1] = (*sb2_block_ports[unit])[block][1]; 738 tdm_ports[2] = (*sb2_block_ports[unit])[block][2]; 739 tdm_ports[3] = (*sb2_block_ports[unit])[block][3]; 740 } 741 742 sal_memcpy(&new_tdm[0],&sb2_current_tdm[0], 743 sb2_current_tdm_size *sizeof(sb2_current_tdm[0])); 744 745 if(!(IS_XL_PORT(unit, port))) { 746 for (index=0,loop=0; loop < sb2_tdm_pos_info[block].total_slots; loop++) { 747 pos = sb2_tdm_pos_info[block].pos[loop]; 748 new_tdm[pos]=tdm_ports[index]; 749 index = (index + 1) % 4 ; 750 } 751 } 752 753 BCM_IF_ERROR_RETURN(bcm_esw_linkscan_mode_get(unit, port, &init_mode)); 754 755 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 756 block_port=(*sb2_block_ports[unit])[block][loop]; 757 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 758 /* 1. Stop linkscan on the port */ 759 bcm_esw_kt2_port_unlock(unit); 760 BCM_IF_ERROR_RETURN(bcm_esw_linkscan_mode_set( 761 unit, block_port, BCM_LINKSCAN_MODE_NONE)); 762 bcm_esw_kt2_port_lock(unit); 763 764 /* 2. To stop the incoming traffic, disable XLMAC Rx */ 765 SOC_IF_ERROR_RETURN(READ_XLMAC_CTRLr( 766 unit, block_port, &xlmac_ctrl)); 767 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, TX_ENf, 1); 768 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, RX_ENf, 0); 769 SOC_IF_ERROR_RETURN(WRITE_XLMAC_CTRLr( 770 unit, block_port, xlmac_ctrl)); 771 sal_udelay((10*time_multiplier)); 772 773 } 774 } 775 776 sal_udelay((10 * time_multiplier)); 777 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 778 block_port=(*sb2_block_ports[unit])[block][loop]; 779 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 780 /* serdes requires autoneg to be False before flex operation */ 781 BCM_IF_ERROR_RETURN(bcm_esw_port_autoneg_set(unit, block_port, 782 FALSE)); 783 /* 3. Brings the port down. */ 784 BCM_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm( 785 unit, MEM_BLOCK_ANY, 0, &epc_link_bmap_entry)); 786 soc_mem_pbmp_field_get(unit, EPC_LINK_BMAPm, 787 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 788 BCM_PBMP_PORT_REMOVE(link_pbmp,block_port); 789 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, 790 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 791 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 792 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 793 } 794 } 795 796 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 797 block_port=(*sb2_block_ports[unit])[block][loop]; 798 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 799 800 #ifdef PORT_FLUSH_DEBUG 801 /* 4. Issues MMU port flush command */ 802 /* PortFlushing creating some issue with L0 node movement. 803 * So moving to Q Flush. 804 */ 805 BCM_IF_ERROR_RETURN(READ_TOQ_FLUSH0r(unit, &flush_reg)); 806 soc_reg_field_set(unit, TOQ_FLUSH0r, &flush_reg, 807 FLUSH_ACTIVEf,1); 808 /* PORT FLUSHING not QUEUE FLUSHING */ 809 soc_reg_field_set(unit, TOQ_FLUSH0r, &flush_reg, FLUSH_TYPEf,1); 810 soc_reg_field_set(unit, TOQ_FLUSH0r, &flush_reg, FLUSH_NUMf,1); 811 soc_reg_field_set(unit, TOQ_FLUSH0r, &flush_reg, 812 FLUSH_ID0f, block_port); 813 BCM_IF_ERROR_RETURN(WRITE_TOQ_FLUSH0r(unit, flush_reg)); 814 #endif 815 816 817 /* 5. Save the current configuration of PAUSE/PFC flow control */ 818 BCM_IF_ERROR_RETURN(bcm_esw_port_speed_get( 819 unit, block_port, &port_speed)); 820 if (!(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 821 if (port_speed == 10000) { 822 BCM_IF_ERROR_RETURN(READ_XPORT_TO_MMU_BKPr( 823 unit, block, &pfc_enable)); 824 BCM_IF_ERROR_RETURN(WRITE_XPORT_TO_MMU_BKPr( 825 unit, block, 0)); 826 } 827 } 828 829 /* 6. flushes any pending egress packets in MXQPORT */ 830 if (SOC_REG_PORT_VALID(unit, IECELL_TXFIFO_PKT_DROP_CTLr, block_port)) { 831 READ_IECELL_TXFIFO_PKT_DROP_CTLr(unit, block_port, &rval); 832 soc_reg_field_set(unit, IECELL_TXFIFO_PKT_DROP_CTLr, &rval, 833 DROP_ENf, 1); 834 WRITE_IECELL_TXFIFO_PKT_DROP_CTLr(unit, block_port, rval); 835 } 836 837 if (SOC_REG_PORT_VALID(unit, XP_TXFIFO_PKT_DROP_CTLr, block_port)) { 838 READ_XP_TXFIFO_PKT_DROP_CTLr(unit, block_port, &rval); 839 soc_reg_field_set(unit, XP_TXFIFO_PKT_DROP_CTLr, &rval, 840 DROP_ENf, 1); 841 WRITE_XP_TXFIFO_PKT_DROP_CTLr(unit, block_port, rval); 842 } 843 844 #ifndef PORT_FLUSH_DEBUG 845 BCM_IF_ERROR_RETURN(bcm_kt2_cosq_port_flush( 846 unit, block_port, bcmCosqFlushTypeQueue)); 847 #endif 848 849 #ifdef PORT_FLUSH_DEBUG 850 /* 7. Waits until all egress port packets are drained. */ 851 try_count=0; 852 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 853 BCM_IF_ERROR_RETURN(READ_TOQ_FLUSH0r(unit, &rval)); 854 soc_reg_field_set(unit, TOQ_FLUSH0r, &rval, FLUSH_ACTIVEf, 0); 855 BCM_IF_ERROR_RETURN(WRITE_TOQ_FLUSH0r(unit, rval)); 856 } 857 858 do { 859 soc_timeout_init(&to, timeout_usec, min_polls); 860 if(soc_timeout_check(&to)) { 861 LOG_ERROR(BSL_LS_BCM_PORT, 862 (BSL_META_U(unit, 863 "%s:%d:TimeOut InternalError\n"), 864 FUNCTION_NAME(),__LINE__)); 865 return BCM_E_INTERNAL; 866 } 867 try_count++; 868 BCM_IF_ERROR_RETURN(READ_TOQ_FLUSH0r(unit, &rval)); 869 if (soc_reg_field_get( 870 unit, TOQ_FLUSH0r, rval, FLUSH_ACTIVEf) == 0) { 871 break; 872 } 873 } while (try_count != 3); 874 875 if (try_count == 3) { 876 LOG_ERROR(BSL_LS_BCM_PORT, 877 (BSL_META_U(unit, 878 "%s:%d: TimeOut - TOQ Flush\n"), 879 FUNCTION_NAME(),__LINE__)); 880 return BCM_E_TIMEOUT; 881 } 882 #endif 883 884 try_count=0; 885 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 886 if (SOC_REG_PORT_VALID(unit, XP_TXFIFO_CELL_CNTr, block_port)) { 887 BCM_IF_ERROR_RETURN(READ_XP_TXFIFO_CELL_CNTr( 888 unit, block_port, &rval)); 889 soc_reg_field_set(unit, XP_TXFIFO_CELL_CNTr, 890 &rval, CELL_CNTf, 0); 891 BCM_IF_ERROR_RETURN(WRITE_XP_TXFIFO_CELL_CNTr( 892 unit, block_port, rval)); 893 } 894 895 if (SOC_REG_PORT_VALID(unit, IECELL_TXFIFO_CELL_CNTr, block_port)) { 896 BCM_IF_ERROR_RETURN(READ_IECELL_TXFIFO_CELL_CNTr( 897 unit, block_port, &rval)); 898 soc_reg_field_set(unit, IECELL_TXFIFO_CELL_CNTr, 899 &rval, CELL_CNTf, 0); 900 BCM_IF_ERROR_RETURN(WRITE_IECELL_TXFIFO_CELL_CNTr( 901 unit, block_port, rval)); 902 } 903 904 } 905 soc_timeout_init(&to, timeout_usec, min_polls); 906 for (try=0; try<100 && try_count < 10 ; try++) { 907 if(soc_timeout_check(&to)) { 908 LOG_ERROR(BSL_LS_BCM_PORT, 909 (BSL_META_U(unit, 910 "%s:%d:TimeOut InternalError\n"), 911 FUNCTION_NAME(),__LINE__)); 912 return BCM_E_INTERNAL; 913 } 914 915 BCM_IF_ERROR_RETURN(READ_XP_TXFIFO_CELL_CNTr ( 916 unit,block_port, &rval)); 917 cell_cnt=soc_reg_field_get(unit, XP_TXFIFO_CELL_CNTr, 918 rval, CELL_CNTf); 919 if (cell_cnt == 0) { 920 try_count++; 921 break; 922 } 923 } 924 925 if (try == 100) { 926 LOG_ERROR(BSL_LS_BCM_PORT, 927 (BSL_META_U(unit, 928 "%s:%d: TimeOut - Drain Egress packets\n"), 929 FUNCTION_NAME(),__LINE__)); 930 return BCM_E_TIMEOUT; 931 } 932 } 933 } 934 935 /* Disable port before detaching phy */ 936 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 937 block_port=(*sb2_block_ports[unit])[block][loop]; 938 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 939 BCM_IF_ERROR_RETURN( 940 bcm_esw_port_enable_set(unit, block_port, 0)); 941 } 942 } 943 944 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 945 block_port=(*sb2_block_ports[unit])[block][loop]; 946 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 947 948 /* 8. Powerdown Vipercore/Eaglecore serdes */ 949 if (SOC_REG_PORT_VALID(unit, XPORT_XGXS_CTRLr, block_port)) { 950 SOC_IF_ERROR_RETURN(READ_XPORT_XGXS_CTRLr(unit, block_port, &rval)); 951 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, 952 IDDQf,1); 953 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, 954 PWRDWNf,1); 955 WRITE_XPORT_XGXS_CTRLr(unit, block_port,rval); 956 } 957 958 959 if (SOC_REG_PORT_VALID(unit, XLPORT_XGXS0_CTRL_REGr, block_port)) { 960 SOC_IF_ERROR_RETURN(READ_XLPORT_XGXS0_CTRL_REGr(unit, 961 block_port, &rval)); 962 soc_reg_field_set(unit, XLPORT_XGXS0_CTRL_REGr, &rval, 963 PWRDWNf, 1); 964 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XGXS0_CTRL_REGr(unit, 965 block_port, rval)); 966 } 967 968 /* 9. Disable egress cell request generation. */ 969 if(block > 0) { 970 sal_memset(&egr_enable_entry, 0, sizeof(egr_enable_entry_t)); 971 soc_mem_field32_set(unit, EGR_ENABLEm, &egr_enable_entry, PRT_ENABLEf, 0); 972 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, block_port, 973 &egr_enable_entry)); 974 } else { 975 SOC_IF_ERROR_RETURN(READ_TXLP_PORT_ENABLEr(unit, port, 976 &rval)); 977 port_enable = soc_reg_field_get(unit, TXLP_PORT_ENABLEr, rval, 978 PORT_ENABLEf); 979 port_enable &= ~(1 << (loop)); 980 soc_reg_field_set(unit, TXLP_PORT_ENABLEr, &rval, 981 PORT_ENABLEf, port_enable); 982 BCM_IF_ERROR_RETURN(WRITE_TXLP_PORT_ENABLEr(unit, port, rval)); 983 } 984 985 /* 10. disable the MXQPORT flush. */ 986 if (SOC_REG_PORT_VALID(unit, XP_TXFIFO_PKT_DROP_CTLr, block_port)) { 987 READ_XP_TXFIFO_PKT_DROP_CTLr(unit, block_port,&rval); 988 soc_reg_field_set(unit, XP_TXFIFO_PKT_DROP_CTLr, &rval, 989 DROP_ENf,0); 990 WRITE_XP_TXFIFO_PKT_DROP_CTLr(unit, block_port,rval); 991 } 992 993 if (SOC_REG_PORT_VALID(unit, IECELL_TXFIFO_PKT_DROP_CTLr, block_port)) { 994 READ_IECELL_TXFIFO_PKT_DROP_CTLr(unit, block_port,&rval); 995 soc_reg_field_set(unit, IECELL_TXFIFO_PKT_DROP_CTLr, &rval, 996 DROP_ENf,0); 997 WRITE_IECELL_TXFIFO_PKT_DROP_CTLr(unit, block_port,rval); 998 } 999 /* 11. Restore PFC */ 1000 if (!(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 1001 if (port_speed >= 10000) { 1002 BCM_IF_ERROR_RETURN(WRITE_XPORT_TO_MMU_BKPr( 1003 unit, block, pfc_enable)); 1004 } 1005 } 1006 /* PLEASE NOTE THAT PORT IS STILL DOWN */ 1007 1008 } /* If SOC_PBMP_MEMBER */ 1009 } /* for loop */ 1010 1011 /* Update local pbmp's */ 1012 soc_linkscan_pause(unit); 1013 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1014 block_port=(*sb2_block_ports[unit])[block][loop]; 1015 if ((old_ports[old_lanes-1][loop] == 0) && 1016 (new_ports[new_lanes-1][loop] == 0)) { 1017 /* Either not used */ 1018 continue; 1019 } 1020 1021 if (block < 6) { 1022 si->port_speed_max[block_port]=(*sb2_port_speeds[unit])[block] 1023 [new_lanes-1]; 1024 } else { 1025 /* Add exception for eagle port due to mixed mode */ 1026 soc_saber2_xl_port_speed_get(unit, block_port, 1027 &(si->port_speed_max[block_port])); 1028 } 1029 1030 if (old_ports[old_lanes-1][loop] == new_ports[new_lanes-1][loop] ) { 1031 /* same port was used so only speed change */ 1032 soc_katana2_pbmp_remove(unit,block_port); 1033 soc_saber2_pbmp_add(unit,block_port,block, 1034 si->port_speed_max[block_port], new_lanes); 1035 } 1036 if (old_ports[old_lanes-1][loop] > new_ports[new_lanes-1][loop]) { 1037 /* This port is not applicable so remove it from pbmp list */ 1038 soc_katana2_pbmp_remove(unit,block_port); 1039 #if defined(INCLUDE_L3) 1040 bcm_sb2_ipmc_repl_extq_port_free(unit, block_port); 1041 #endif 1042 continue; 1043 } 1044 if (new_ports[new_lanes-1][loop] > old_ports[old_lanes-1][loop]) { 1045 /* This port is new so add it in pbmp list first */ 1046 soc_saber2_pbmp_add(unit,block_port, block, 1047 si->port_speed_max[block_port], new_lanes); 1048 #if defined(INCLUDE_L3) 1049 BCM_IF_ERROR_RETURN(bcm_sb2_ipmc_repl_extq_port_alloc(unit, block_port)); 1050 #endif 1051 } 1052 BCM_IF_ERROR_RETURN(bcm_katana2_cosq_reconfigure_flexio(unit, block_port, config_lanes)); 1053 } 1054 1055 soc_katana2_pbmp_all_resync(unit) ; 1056 soc_esw_dport_init(unit); 1057 soc_linkscan_continue(unit); 1058 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1059 block_port=(*sb2_block_ports[unit])[block][loop]; 1060 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1061 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_reconfigure(unit, block_port)); 1062 } 1063 } 1064 /* ReConfigure H/W */ 1065 /* 1. Soft-reset relevant MXQPORT(s) */ 1066 if (block < 6) { 1067 soc_saber2_block_reset(unit, block, 0); 1068 } 1069 1070 /* ReConfigure TDM */ 1071 soc_saber2_reconfigure_tdm(unit, sb2_current_tdm_size, new_tdm); 1072 sal_memcpy(&sb2_current_tdm[0],&new_tdm[0], 1073 sb2_current_tdm_size *sizeof(sb2_current_tdm[0])); 1074 1075 block_max_nxtaddr = block_max_startaddr[block]; 1076 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1077 block_port=(*sb2_block_ports[unit])[block][loop]; 1078 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1079 BCM_IF_ERROR_RETURN(READ_DEQ_EFIFO_CFGr(unit,block_port,&rval)); 1080 1081 if (si->port_speed_max[block_port] <= 1000) { 1082 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, block_port)) ? 10 : 2; 1083 threshold = (IS_EXT_MEM_PORT(unit, block_port)) ? 8 : 1; 1084 port_bw = 25; 1085 start_threshold = 7; 1086 } else if (si->port_speed_max[block_port] <= 2500) { 1087 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, block_port)) ? 19 : 2; 1088 threshold = (IS_EXT_MEM_PORT(unit, block_port)) ? 15 : 1; 1089 port_bw = 63; 1090 start_threshold = 14; 1091 } else if (si->port_speed_max[block_port] <= 13000) { 1092 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, block_port)) ? 53 : 10; 1093 threshold = (IS_EXT_MEM_PORT(unit, block_port)) ? 49 : 1; 1094 port_bw = 325; 1095 start_threshold = 48; 1096 } else { 1097 LOG_ERROR(BSL_LS_BCM_PORT, 1098 (BSL_META_U(unit, "Invalid Speed config\n"))); 1099 return BCM_E_FAIL; 1100 } 1101 1102 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 1103 EGRESS_FIFO_START_ADDRESSf, 1104 block_max_nxtaddr); 1105 1106 if ((block_max_nxtaddr + egr_fifo_depth) > block_max_endaddr[block]) { 1107 egr_fifo_depth = (block_max_endaddr[block] - 1108 block_max_nxtaddr)+1; 1109 block_max_nxtaddr = block_max_endaddr[block]; 1110 } else { 1111 block_max_nxtaddr += egr_fifo_depth; 1112 } 1113 if (egr_fifo_depth == 1) { 1114 LOG_CLI((BSL_META_U(unit, 1115 "WARN: EGR_FIFO_DEPTH IS ZERO for port=%d\n"), 1116 block_port)); 1117 } 1118 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 1119 EGRESS_FIFO_DEPTHf, egr_fifo_depth); 1120 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 1121 EGRESS_FIFO_XMIT_THRESHOLDf, threshold); 1122 BCM_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr( 1123 unit,block_port,rval)); 1124 1125 /* Port BW Ctrl */ 1126 SOC_IF_ERROR_RETURN(READ_TOQ_PORT_BW_CTRLr(unit, 1127 block_port, &rval)); 1128 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 1129 PORT_BWf, port_bw); 1130 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 1131 START_THRESHOLDf, start_threshold); 1132 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, 1133 block_port, rval)); 1134 1135 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 1136 "DEQ_EFIFO_CFG values: " 1137 "port:%d depth:%d new_block_max_nxtaddr=%d\n"), 1138 port, egr_fifo_depth, block_max_nxtaddr)); 1139 } /* if SOC_PBMP_MEMBER ... block_port */ 1140 } /* for loop */ 1141 1142 /* WORK-AROUND for port-flushing i.e. need to repeat below step twice */ 1143 for (try_loop = 0; try_loop < 2; try_loop++) { 1144 /* EP Reset */ 1145 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 1146 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 1147 unit, 0)); 1148 } 1149 1150 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1151 block_port=(*sb2_block_ports[unit])[block][loop]; 1152 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1153 rval1 |= (1 << block_port); 1154 } 1155 } 1156 1157 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 1158 unit, rval1)); 1159 1160 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 1161 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 1162 unit, 0)); 1163 } 1164 1165 try_count = 0; 1166 do { 1167 soc_timeout_init(&to, timeout_usec, min_polls); 1168 if(soc_timeout_check(&to)) { 1169 LOG_ERROR(BSL_LS_BCM_PORT, 1170 (BSL_META_U(unit, 1171 "%s:%d:TimeOut InternalError\n"), 1172 FUNCTION_NAME(),__LINE__)); 1173 return BCM_E_INTERNAL; 1174 } 1175 try_count++; 1176 1177 BCM_IF_ERROR_RETURN(READ_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 1178 unit, &rval1)); 1179 if (rval1 == 0 ) { 1180 break; 1181 } 1182 } while (try_count != 5); 1183 1184 if (try_count == 5) { 1185 LOG_ERROR(BSL_LS_BCM_PORT, 1186 (BSL_META_U(unit, 1187 "%s:%d: TimeOut - Port reconfig vector\n"), 1188 FUNCTION_NAME(),__LINE__)); 1189 return BCM_E_TIMEOUT; 1190 } 1191 1192 sal_usleep(1000); 1193 } /* for try_loop */ 1194 1195 if ((block > 0) && (block < 6)) { 1196 READ_EDATABUF_DBG_PORT_INTF_RESETr(unit, &rval); 1197 soc_reg_field_set(unit, EDATABUF_DBG_PORT_INTF_RESETr, 1198 &rval, port_intf_reset_fld[block - 1], 1); 1199 WRITE_EDATABUF_DBG_PORT_INTF_RESETr(unit, rval); 1200 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 1201 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 1202 &rval, mmu_intf_reset_fld[block - 1], 1); 1203 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 1204 &rval, new_port_mode_fld[block - 1], 1205 new_port_mode[new_lanes]); 1206 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 1207 } else if (block == 6) { 1208 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1209 READ_EDATABUF_DBG_PORT_INTF_RESETr(unit, &rval); 1210 soc_reg_field_set(unit, EDATABUF_DBG_PORT_INTF_RESETr, 1211 &rval, port_intf_reset_fld[block + loop - 1], 1); 1212 WRITE_EDATABUF_DBG_PORT_INTF_RESETr(unit, rval); 1213 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 1214 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 1215 &rval, mmu_intf_reset_fld[block + loop - 1], 1); 1216 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 1217 &rval, new_port_mode_fld[block + loop - 1], 1218 new_port_mode[new_lanes]); 1219 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 1220 } 1221 } else if (block == 0){ 1222 WRITE_TXLP_PORT_CREDIT_RESETr(unit, port,0xf); 1223 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1224 sal_memset(&txlp_port_addr_map_table_entry,0, 1225 sizeof(txlp_port_addr_map_table_entry_t)); 1226 block_port=(*sb2_block_ports[unit])[block][loop]; 1227 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1228 1229 if (si->port_speed_max[port] <= 2500) { 1230 end_addr = start_addr + (( 8 * 4) - 1); /* 8 cells */ 1231 } else if(si->port_speed_max[port] <= 10000) { 1232 end_addr = start_addr + (( 16 * 4) - 1); 1233 } else { 1234 return BCM_E_PARAM; 1235 } 1236 1237 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 1238 &txlp_port_addr_map_table_entry,START_ADDRf,&start_addr); 1239 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 1240 &txlp_port_addr_map_table_entry,END_ADDRf,&end_addr); 1241 start_addr = end_addr+1; 1242 } 1243 1244 BCM_IF_ERROR_RETURN(WRITE_TXLP_PORT_ADDR_MAP_TABLEm( 1245 unit,SOC_INFO(unit).txlp_block[block], 1246 loop, &txlp_port_addr_map_table_entry)); 1247 } /* for loop */ 1248 } /* if else block != 0 */ 1249 1250 1251 /* Begin: Link up sequence */ 1252 sal_udelay((10*time_multiplier)); 1253 1254 /* 1. Bring edatabuf port and mmu intf out of reset */ 1255 if ((block > 0) && (block < 6)) { 1256 READ_EDATABUF_DBG_PORT_INTF_RESETr(unit, &rval); 1257 soc_reg_field_set(unit, EDATABUF_DBG_PORT_INTF_RESETr, 1258 &rval, port_intf_reset_fld[block - 1], 0); 1259 WRITE_EDATABUF_DBG_PORT_INTF_RESETr(unit, rval); 1260 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 1261 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 1262 &rval, mmu_intf_reset_fld[block - 1], 0); 1263 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 1264 } else if(block == 6) { 1265 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1266 READ_EDATABUF_DBG_PORT_INTF_RESETr(unit, &rval); 1267 soc_reg_field_set(unit, EDATABUF_DBG_PORT_INTF_RESETr, 1268 &rval, port_intf_reset_fld[block + loop - 1], 0); 1269 WRITE_EDATABUF_DBG_PORT_INTF_RESETr(unit, rval); 1270 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 1271 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 1272 &rval, mmu_intf_reset_fld[block + loop - 1], 0); 1273 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 1274 } 1275 } 1276 1277 if (block == 0) { 1278 WRITE_TXLP_PORT_CREDIT_RESETr(unit, port,0); 1279 } 1280 1281 /* 2. Enable port */ 1282 BCM_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm( 1283 unit, MEM_BLOCK_ANY, 0, &epc_link_bmap_entry)); 1284 soc_mem_pbmp_field_get(unit, EPC_LINK_BMAPm, 1285 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 1286 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1287 block_port=(*sb2_block_ports[unit])[block][loop]; 1288 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1289 BCM_PBMP_PORT_ADD(link_pbmp,block_port); 1290 } 1291 } 1292 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, 1293 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 1294 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 1295 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 1296 1297 sal_udelay((10*time_multiplier)); 1298 1299 /* Bring out of reset */ 1300 if (block < 6) { 1301 soc_saber2_block_reset(unit, block, 1); 1302 } 1303 1304 first_port = (*sb2_block_ports[unit])[block][0]; 1305 if (SOC_REG_PORT_VALID(unit, XLPORT_XGXS0_CTRL_REGr, first_port)) { 1306 SOC_IF_ERROR_RETURN(READ_XLPORT_XGXS0_CTRL_REGr(unit, first_port, &rval)); 1307 1308 soc_reg_field_set(unit, XLPORT_XGXS0_CTRL_REGr, &rval, PWRDWNf, 0); 1309 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XGXS0_CTRL_REGr(unit, first_port, rval)); 1310 1311 soc_reg_field_set(unit, XLPORT_XGXS0_CTRL_REGr, &rval, IDDQf, 0); 1312 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XGXS0_CTRL_REGr(unit, first_port, rval)); 1313 1314 soc_reg_field_set(unit, XLPORT_XGXS0_CTRL_REGr, &rval, RSTB_HWf, 1); 1315 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XGXS0_CTRL_REGr(unit, first_port, rval)); 1316 1317 } else if (SOC_REG_PORT_VALID(unit, XPORT_XGXS_CTRLr, first_port)) { 1318 SOC_IF_ERROR_RETURN(READ_XPORT_XGXS_CTRLr(unit, first_port, &rval)); 1319 1320 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, PWRDWNf, 0); 1321 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, first_port, rval)); 1322 1323 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, IDDQf, 0); 1324 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, first_port, rval)); 1325 1326 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, RSTB_HWf, 1); 1327 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, first_port, rval)); 1328 1329 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, RSTB_MDIOREGSf, 1); 1330 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, first_port, rval)); 1331 1332 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, RSTB_PLLf, 1); 1333 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, first_port, rval)); 1334 1335 for (loop=0;loop<SB2_MAX_PORTS_PER_BLOCK;loop++) { 1336 block_port=(*sb2_block_ports[unit])[block][loop]; 1337 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1338 SOC_IF_ERROR_RETURN(READ_XPORT_XGXS_CTRLr( 1339 unit, block_port, &rval)); 1340 if (si->port_speed_max[block_port] > 2500) { 1341 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, 1342 TXD10G_FIFO_RSTBf, 1); 1343 } else { 1344 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, 1345 TXD10G_FIFO_RSTBf,0); 1346 } 1347 soc_reg_field_set(unit,XPORT_XGXS_CTRLr, &rval, 1348 TXD1G_FIFO_RSTBf, 0xF); 1349 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr( 1350 unit,block_port, rval)); 1351 } 1352 } 1353 } 1354 1355 if (block == 6) { 1356 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1357 block_port=(*sb2_block_ports[unit])[block][loop]; 1358 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1359 if(SOC_REG_PORT_VALID(unit, XLPORT_MAC_CONTROLr, block_port)) { 1360 SOC_IF_ERROR_RETURN(READ_XLPORT_MAC_CONTROLr(unit, block_port, &rval)); 1361 1362 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 1); 1363 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, block_port, rval)); 1364 1365 sal_usleep(1000); 1366 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 0); 1367 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, block_port, rval)); 1368 } 1369 } 1370 } 1371 1372 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1373 block_port=(*sb2_block_ports[unit])[block][loop]; 1374 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1375 if (SOC_REG_PORT_VALID(unit, IECELL_CONFIGr, block_port)) { 1376 SOC_IF_ERROR_RETURN(READ_IECELL_CONFIGr(unit, block_port, &rval)); 1377 1378 soc_reg_field_set(unit, IECELL_CONFIGr, &rval, SOFT_RESETf, 1); 1379 SOC_IF_ERROR_RETURN(WRITE_IECELL_CONFIGr(unit, block_port, rval)); 1380 1381 sal_usleep(1000); 1382 soc_reg_field_set(unit, IECELL_CONFIGr, &rval, SOFT_RESETf, 0); 1383 SOC_IF_ERROR_RETURN(WRITE_IECELL_CONFIGr(unit, block_port, rval)); 1384 } 1385 } 1386 } 1387 } 1388 1389 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1390 block_port=(*sb2_block_ports[unit])[block][loop]; 1391 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1392 BCM_IF_ERROR_RETURN(_bcm_sb2_update_port_mode( 1393 unit,block_port, 1394 si->port_speed_max[block_port])); 1395 break; 1396 } 1397 } 1398 1399 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1400 block_port=(*sb2_block_ports[unit])[block][loop]; 1401 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1402 if(SOC_REG_PORT_VALID(unit, XPORT_XMAC_CONTROLr, block_port)) { 1403 SOC_IF_ERROR_RETURN(READ_XPORT_XMAC_CONTROLr(unit, block_port, &rval)); 1404 soc_reg_field_set(unit, XPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 1); 1405 SOC_IF_ERROR_RETURN(WRITE_XPORT_XMAC_CONTROLr(unit, block_port, rval)); 1406 } 1407 } 1408 } 1409 sal_udelay(10); 1410 1411 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1412 block_port=(*sb2_block_ports[unit])[block][loop]; 1413 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1414 if(SOC_REG_PORT_VALID(unit, XPORT_XMAC_CONTROLr, block_port)) { 1415 SOC_IF_ERROR_RETURN(READ_XPORT_XMAC_CONTROLr(unit, block_port, &rval)); 1416 soc_reg_field_set(unit, XPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 0); 1417 SOC_IF_ERROR_RETURN(WRITE_XPORT_XMAC_CONTROLr(unit, block_port, rval)); 1418 } 1419 } 1420 } 1421 1422 length_check = soc_property_get(unit, spn_MAC_LENGTH_CHECK_ENABLE, 0); 1423 1424 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1425 block_port=(*sb2_block_ports[unit])[block][loop]; 1426 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1427 if(SOC_REG_PORT_VALID(unit, MAC_RSV_MASKr, block_port)) { 1428 SOC_IF_ERROR_RETURN(READ_MAC_RSV_MASKr(unit, block_port, &rval)); 1429 1430 if (length_check) { 1431 rval |= 0x20; /* set bit 5 to enable frame length check */ 1432 } else { 1433 rval &= ~0x20; /* clear bit 5 to disable frame length check */ 1434 } 1435 SOC_IF_ERROR_RETURN(WRITE_MAC_RSV_MASKr(unit,block_port, rval)); 1436 } /* SOC_REG_PORT_VALID MAC_RSV_MASK */ 1437 1438 if(SOC_REG_PORT_VALID(unit, XLPORT_MAC_RSV_MASKr, block_port)) { 1439 SOC_IF_ERROR_RETURN(READ_XLPORT_MAC_RSV_MASKr(unit, 1440 block_port, &rval)); 1441 1442 if (IS_ST_PORT(unit, block_port)) { 1443 /* No frame length for stack */ 1444 soc_reg_field_set(unit, XLPORT_MAC_RSV_MASKr, 1445 &rval, MASKf, 0x58); 1446 } else { 1447 if (length_check) { 1448 rval |= 0x20; /* set bit 5 to enable frame length check */ 1449 } else { 1450 rval &= ~0x20; /* clear bit 5 to disable frame length check */ 1451 } 1452 } 1453 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_RSV_MASKr(unit, 1454 block_port, rval)); 1455 } /* SOC_REG_PORT_VALID MAC_RSV_MASK */ 1456 } /* if SOC_PBMP_MEMBER */ 1457 } /* for loop */ 1458 1459 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1460 block_port=(*sb2_block_ports[unit])[block][loop]; 1461 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1462 1463 if (SOC_REG_PORT_VALID(unit, XPORT_MIB_RESETr, block_port)) { 1464 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, block_port, 0xf)); 1465 sal_usleep(1000); 1466 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, block_port, 0x0)); 1467 } 1468 1469 if (SOC_REG_PORT_VALID(unit, XLPORT_MIB_RESETr, block_port)) { 1470 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, block_port, 0xf)); 1471 sal_usleep(1000); 1472 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, block_port, 0x0)); 1473 } 1474 } 1475 } 1476 1477 1478 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1479 block_port=(*sb2_block_ports[unit])[block][loop]; 1480 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1481 if (SOC_REG_PORT_VALID(unit, XLMAC_RX_CTRLr, block_port)) { 1482 SOC_IF_ERROR_RETURN(READ_XLMAC_RX_CTRLr( 1483 unit,block_port, &rval64)); 1484 if (IS_ST_PORT(unit, block_port)) { 1485 soc_reg64_field32_set(unit, XLMAC_RX_CTRLr, &rval64, 1486 RUNT_THRESHOLDf, 76); 1487 } else { 1488 soc_reg64_field32_set(unit, XLMAC_RX_CTRLr, &rval64, 1489 RUNT_THRESHOLDf, 64); 1490 } 1491 soc_reg64_field32_set(unit, XLMAC_RX_CTRLr, &rval64, 1492 STRIP_CRCf, 0); 1493 SOC_IF_ERROR_RETURN(WRITE_XLMAC_RX_CTRLr( 1494 unit,block_port, rval64)); 1495 } /* if SOC_REG_PORT_VALID XLMAC_RX_CTRL */ 1496 } /* if SOC_PBMP_MEMBER block_port */ 1497 } /* for loop */ 1498 1499 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1500 block_port=(*sb2_block_ports[unit])[block][loop]; 1501 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1502 if (SOC_REG_PORT_VALID(unit, XLMAC_TX_CTRLr, block_port)) { 1503 SOC_IF_ERROR_RETURN(READ_XLMAC_TX_CTRLr( 1504 unit, block_port, &rval64)); 1505 soc_reg64_field32_set(unit, XLMAC_TX_CTRLr, &rval64, 1506 CRC_MODEf,3); 1507 SOC_IF_ERROR_RETURN(WRITE_XLMAC_TX_CTRLr( 1508 unit,block_port, rval64)); 1509 } /* if SOC_REG_PORT_VALID XLMAC_TX_CTRL */ 1510 } /* if SOC_PBMP_MEMBER block_port */ 1511 } /* for loop */ 1512 1513 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1514 block_port=(*sb2_block_ports[unit])[block][loop]; 1515 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1516 if (SOC_REG_PORT_VALID(unit, XLMAC_RX_MAX_SIZEr, block_port)) { 1517 SOC_IF_ERROR_RETURN(READ_XLMAC_RX_MAX_SIZEr( 1518 unit,block_port, &rval64)); 1519 soc_reg64_field32_set(unit, XLMAC_RX_MAX_SIZEr, &rval64, 1520 RX_MAX_SIZEf,(12*1024)); 1521 SOC_IF_ERROR_RETURN(WRITE_XLMAC_RX_MAX_SIZEr( 1522 unit,block_port, rval64)); 1523 } /* if SOC_REG_PORT_VALID XLMAC_RX_MAX_SIZE */ 1524 } /* if SOC_PBMP_MEMBER block_port */ 1525 } /* for loop */ 1526 1527 if (SOC_REG_PORT_VALID(unit, XLPORT_ECC_CONTROLr, port)) { 1528 SOC_IF_ERROR_RETURN(READ_XLPORT_ECC_CONTROLr(unit, port, &rval)); 1529 soc_reg_field_set(unit, XLPORT_ECC_CONTROLr, &rval, 1530 MIB_TSC_MEM_ENf, 1); 1531 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ECC_CONTROLr(unit, port, rval)); 1532 } 1533 1534 /* detach phy from old port */ 1535 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1536 block_port=(*sb2_block_ports[unit])[block][loop]; 1537 if ((old_ports[old_lanes-1][loop] == 0) && 1538 (new_ports[new_lanes-1][loop] == 0)) { 1539 continue; 1540 } 1541 if (old_ports[old_lanes-1][loop] == new_ports[new_lanes-1][loop] ) { 1542 /* same port was used so only speed change */ 1543 SOC_IF_ERROR_RETURN(soc_saber2_port_detach(unit,block_port)); 1544 } 1545 if (old_ports[old_lanes-1][loop] > new_ports[new_lanes-1][loop]) { 1546 /* This port is not applicable so remove it from pbmp list */ 1547 SOC_IF_ERROR_RETURN(soc_saber2_port_detach(unit,block_port)); 1548 continue; 1549 } 1550 if (new_ports[new_lanes-1][loop] > old_ports[old_lanes-1][loop]) { 1551 /* This port is new continue */ 1552 continue; 1553 } 1554 } 1555 1556 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1557 block_port=(*sb2_block_ports[unit])[block][loop]; 1558 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1559 1560 if (SOC_REG_PORT_VALID(unit, XPORT_PORT_ENABLEr, block_port)) { 1561 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr(unit, block_port, 1562 &rval)); 1563 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval, 1564 port_enable_field[loop], 1); 1565 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, block_port, 1566 rval)); 1567 } 1568 1569 if (SOC_REG_PORT_VALID(unit, XLPORT_ENABLE_REGr, block_port)) { 1570 SOC_IF_ERROR_RETURN(READ_XLPORT_ENABLE_REGr(unit, block_port, 1571 &rval)); 1572 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, 1573 port_enable_field[loop], 1); 1574 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ENABLE_REGr(unit, block_port, 1575 rval)); 1576 } 1577 1578 }/* if SOC_PBMP_MEMBER block_port */ 1579 } /* for loop */ 1580 1581 sal_udelay((10*time_multiplier)); 1582 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1583 block_port=(*sb2_block_ports[unit])[block][loop]; 1584 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1585 BCM_IF_ERROR_RETURN(soc_mac_xl.md_enable_set( 1586 unit, block_port, TRUE)); 1587 } /* if SOC_PBMP_MEMBER block_port */ 1588 } /* for loop */ 1589 1590 if (SOC_REG_PORT_VALID(unit, THDO_PORT_DISABLE_CFG1r, port)) { 1591 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1592 block_port=(*sb2_block_ports[unit])[block][loop]; 1593 SOC_IF_ERROR_RETURN(READ_THDO_PORT_DISABLE_CFG1r(unit,&rval)); 1594 1595 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 1596 PORT_WRf,1); 1597 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 1598 PORT_WR_TYPEf,0); 1599 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 1600 PORT_IDf,block_port); 1601 SOC_IF_ERROR_RETURN(WRITE_THDO_PORT_DISABLE_CFG1r(unit,rval)); 1602 1603 sal_udelay(10*time_multiplier); 1604 1605 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 1606 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 1607 PORT_WRf,0); 1608 SOC_IF_ERROR_RETURN(WRITE_THDO_PORT_DISABLE_CFG1r( 1609 unit,rval)); 1610 } 1611 SOC_IF_ERROR_RETURN(READ_THDO_PORT_DISABLE_CFG1r(unit,&rval)); 1612 1613 if (soc_reg_field_get(unit, THDO_PORT_DISABLE_CFG1r, rval, 1614 PORT_WRf) != 0) { 1615 LOG_ERROR(BSL_LS_BCM_PORT, 1616 (BSL_META_U(unit, 1617 "%s:%d: TimeOut - THDO port disable cfg\n"), 1618 FUNCTION_NAME(),__LINE__)); 1619 return BCM_E_TIMEOUT; 1620 } 1621 } /* for loop */ 1622 } /* if SOC_REG_PORT_VALID THDO_PORT_DISABLE_CFG1 */ 1623 1624 sal_udelay((10*time_multiplier)); 1625 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1626 block_port=(*sb2_block_ports[unit])[block][loop]; 1627 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1628 if(block > 0) { 1629 sal_memset(&egr_enable_entry, 0, sizeof(egr_enable_entry_t)); 1630 soc_mem_field32_set(unit, EGR_ENABLEm, &egr_enable_entry, PRT_ENABLEf, 1); 1631 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, block_port, 1632 &egr_enable_entry)); 1633 } else { 1634 SOC_IF_ERROR_RETURN(READ_TXLP_PORT_ENABLEr( 1635 unit, port, &rval)); 1636 port_enable = soc_reg_field_get(unit, TXLP_PORT_ENABLEr, 1637 rval, PORT_ENABLEf); 1638 port_enable |= ( 1<< ((*sb2_port_to_block_subports[unit]) 1639 [block_port-1])); 1640 soc_reg_field_set(unit, TXLP_PORT_ENABLEr, 1641 &rval, PORT_ENABLEf, port_enable); 1642 SOC_IF_ERROR_RETURN(WRITE_TXLP_PORT_ENABLEr( 1643 unit, port, rval)); 1644 } 1645 } 1646 } 1647 1648 /* Update port_num_lanes in soc_info_config */ 1649 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1650 block_port=(*sb2_block_ports[unit])[block][loop]; 1651 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1652 /* Not a valid port. So set num_lanes to 0 */ 1653 si->port_num_lanes[block_port] = 0; 1654 si->port_speed_max[block_port] = 0; 1655 sal_snprintf(si->port_name[block_port], sizeof(si->port_name[block_port]), 1656 "?%d", block_port); 1657 } 1658 } 1659 1660 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1661 block_port=(*sb2_block_ports[unit])[block][loop]; 1662 if ((old_ports[old_lanes-1][loop] == 0) && 1663 (new_ports[new_lanes-1][loop] == 0)) { 1664 continue; 1665 } 1666 if (old_ports[old_lanes-1][loop] == new_ports[new_lanes-1][loop] ) { 1667 /* same port was used so only speed change */ 1668 SOC_IF_ERROR_RETURN(soc_saber2_port_attach( 1669 unit,block ,block_port)); 1670 } 1671 if (old_ports[old_lanes-1][loop] > new_ports[new_lanes-1][loop]) { 1672 /* This port is not applicable so remove it from pbmp list */ 1673 continue; 1674 } 1675 if (new_ports[new_lanes-1][loop] > old_ports[old_lanes-1][loop]) { 1676 /* This port is new so add it in pbmp list first */ 1677 SOC_IF_ERROR_RETURN(soc_saber2_port_attach( 1678 unit,block ,block_port)); 1679 } 1680 } 1681 1682 /* Clear counters for the new ports */ 1683 SOC_PBMP_CLEAR(link_pbmp); 1684 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1685 block_port=(*sb2_block_ports[unit])[block][loop]; 1686 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 1687 BCM_PBMP_PORT_ADD(link_pbmp,block_port); 1688 } 1689 } 1690 1691 COMPILER_64_ZERO(ctr_val); 1692 BCM_IF_ERROR_RETURN(soc_counter_set_by_port(unit, link_pbmp, ctr_val)); 1693 1694 bcm_esw_kt2_port_unlock(unit); 1695 BCM_IF_ERROR_RETURN(bcm_esw_linkscan_mode_set(unit, port, init_mode)); 1696 bcm_esw_kt2_port_lock(unit); 1697 1698 #ifdef BCM_WARM_BOOT_SUPPORT 1699 SOC_CONTROL_LOCK(unit); 1700 SOC_CONTROL(unit)->scache_dirty = 1; 1701 SOC_CONTROL_UNLOCK(unit); 1702 #endif 1703 1704 /* End: Link up sequence */ 1705 1706 return BCM_E_NONE; 1707 } 1708 1709 int 1710 _bcm_sb2_port_lanes_get(int unit, bcm_port_t port, int *active_lanes) 1711 { 1712 uint8 loop=0, block=0; 1713 int lanes = 0; 1714 1715 *active_lanes = lanes; 1716 1717 SOC_IF_ERROR_RETURN(soc_saber2_get_port_block( 1718 unit, port, &block)); 1719 1720 for (loop = 0;loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 1721 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), 1722 (*sb2_block_ports[unit])[block][loop])) { 1723 lanes++; 1724 } 1725 } 1726 1727 /* active_lanes refer to the number of active lanes per port. */ 1728 /* lanes refer to number of valid lanes in the port block. */ 1729 switch (lanes) { 1730 case 1 : *active_lanes = 4; 1731 break; 1732 case 2 : *active_lanes = 2; 1733 break; 1734 case 4 :*active_lanes = 1; 1735 break; 1736 default : return BCM_E_INTERNAL; 1737 } 1738 1739 return BCM_E_NONE; 1740 } 1741 1742 #if defined(BCM_WARM_BOOT_SUPPORT) 1743 int 1744 _bcm_sb2_wb_v1_flexio_pbmp_update(int unit, bcm_pbmp_t *pbmp) 1745 { 1746 bcm_port_t blk_port; 1747 int blk, blk_idx; 1748 uint16 dev_id = 0; 1749 uint8 rev_id = 0; 1750 1751 soc_cm_get_id(unit, &dev_id, &rev_id); 1752 1753 if (NULL == pbmp) { 1754 return BCM_E_PORT; 1755 } 1756 1757 if(dev_id == BCM56233_DEVICE_ID) { 1758 /* Dagger2 does not support flex operation. So no need of pbmp update */ 1759 return SOC_E_NONE; 1760 } 1761 1762 for (blk = 0; blk < SB2_MAX_BLOCKS; blk++) { 1763 1764 if (blk < 6) { 1765 /* Add the port at index 1, 2, & 3 to gven pbmp and update the 1766 * port_type so that it is treated as valid port 1767 */ 1768 for (blk_idx = 1; 1769 blk_idx < SB2_MAX_PORTS_PER_BLOCK; blk_idx++) { 1770 1771 blk_port = (*sb2_block_ports[unit])[blk][blk_idx]; 1772 if (blk_port < SOC_INFO(unit).lb_port) { 1773 BCM_PBMP_PORT_ADD(*pbmp, blk_port); 1774 SOC_PORT_TYPE(unit, blk_port) = SOC_BLK_MXQPORT; 1775 } 1776 1777 } /* for blk_idx */ 1778 } else if (blk == 6) { 1779 1780 for (blk_idx = 1; 1781 blk_idx < SB2_MAX_PORTS_PER_BLOCK; blk_idx++) { 1782 1783 blk_port = (*sb2_block_ports[unit])[blk][blk_idx]; 1784 if (blk_port < SOC_INFO(unit).lb_port) { 1785 BCM_PBMP_PORT_ADD(*pbmp, blk_port); 1786 SOC_PORT_TYPE(unit, blk_port) = SOC_BLK_XLPORT; 1787 } 1788 1789 } /* for blk_idx */ 1790 } /* if SOC_PORT_TYPE */ 1791 } /* For blk */ 1792 return BCM_E_NONE; 1793 } /* _bcm_sb2_flexio_pbmp_update */ 1794 #endif 1795 1796 int 1797 bcm_sb2_flexio_pbmp_update(int unit, bcm_pbmp_t *pbmp) 1798 { 1799 bcm_port_t blk_port; 1800 bcm_port_t first_port; 1801 int blk, blk_idx; 1802 uint16 dev_id = 0; 1803 uint8 rev_id = 0; 1804 1805 soc_cm_get_id(unit, &dev_id, &rev_id); 1806 1807 if (NULL == pbmp) { 1808 return BCM_E_PORT; 1809 } 1810 1811 if(dev_id == BCM56233_DEVICE_ID) { 1812 /* Dagger2 does not support flex operation. So no need of pbmp update */ 1813 return SOC_E_NONE; 1814 } 1815 1816 for (blk = 0; blk < SB2_MAX_BLOCKS; blk++) { 1817 1818 /* If the first port is invalid, then skip the block */ 1819 first_port = (*sb2_block_ports[unit])[blk][0]; 1820 if (!SOC_PORT_VALID(unit, first_port)) { 1821 continue; 1822 } 1823 if (blk < 6) { 1824 /* Add the port at index 1, 2, & 3 to gven pbmp and update the 1825 * port_type so that it is treated as valid port 1826 */ 1827 for (blk_idx = 1; 1828 blk_idx < SB2_MAX_PORTS_PER_BLOCK; blk_idx++) { 1829 1830 blk_port = (*sb2_block_ports[unit])[blk][blk_idx]; 1831 if (blk_port < SOC_INFO(unit).lb_port) { 1832 BCM_PBMP_PORT_ADD(*pbmp, blk_port); 1833 SOC_PORT_TYPE(unit, blk_port) = SOC_BLK_MXQPORT; 1834 } 1835 1836 } /* for blk_idx */ 1837 } else if (blk == 6) { 1838 1839 for (blk_idx = 1; 1840 blk_idx < SB2_MAX_PORTS_PER_BLOCK; blk_idx++) { 1841 1842 blk_port = (*sb2_block_ports[unit])[blk][blk_idx]; 1843 if (blk_port < SOC_INFO(unit).lb_port) { 1844 BCM_PBMP_PORT_ADD(*pbmp, blk_port); 1845 SOC_PORT_TYPE(unit, blk_port) = SOC_BLK_XLPORT; 1846 } 1847 1848 } /* for blk_idx */ 1849 } /* if SOC_PORT_TYPE */ 1850 } /* For blk */ 1851 return BCM_E_NONE; 1852 } /* _bcm_sb2_flexio_pbmp_update */ 1853 1854 int 1855 _bcm_sb2_port_oamp_enable(int unit, bcm_port_t port, int enable) 1856 { 1857 uint32 rval = 0; 1858 uint32 time_multiplier=1; 1859 uint8 block; 1860 uint8 first_port = 0; 1861 uint8 rev_id = 0; 1862 #if defined(BCM_METROLITE_SUPPORT) 1863 uint8 loop = 0; 1864 int cfg_num = 0; 1865 #endif 1866 uint16 dev_id = 0; 1867 int init_mode = 0, oamp_status = 0; 1868 uint32 cell_cnt = 0; 1869 uint32 try = 0 , try_count = 0; 1870 int min_polls = 100; 1871 uint32 pfc_enable=0; 1872 int rv = 0; 1873 int port_enable = 0; 1874 int port_speed = 0, max_speed = 0; 1875 uint64 xlmac_ctrl; 1876 soc_info_t *si = &SOC_INFO(unit); 1877 epc_link_bmap_entry_t epc_link_bmap_entry={{0}}; 1878 soc_pbmp_t link_pbmp; 1879 soc_timeout_t to = {0}; 1880 sal_usecs_t timeout_usec = 100000; 1881 egr_enable_entry_t egr_enable_entry = {{0}}; 1882 1883 soc_cm_get_id(unit, &dev_id, &rev_id); 1884 if ((rev_id == BCM56260_A0_REV_ID) && 1885 (!(SOC_IS_METROLITE(unit)))){ 1886 /* OAMP hotswap not supported in Saber2 A0 device */ 1887 return BCM_E_UNAVAIL; 1888 } 1889 1890 if(dev_id == BCM56233_DEVICE_ID) { 1891 /* Dagger2 does not support OAMP hostswap */ 1892 return SOC_E_UNAVAIL; 1893 } 1894 1895 if (!SOC_PORT_VALID(unit, port)) { 1896 return BCM_E_PORT; 1897 } 1898 1899 /* Corner case : enable is neither TRUE nor FALSE */ 1900 if(!((enable == TRUE) || (enable == FALSE))) { 1901 return BCM_E_PARAM; 1902 } 1903 1904 if (SAL_BOOT_QUICKTURN) { 1905 time_multiplier=1000; 1906 } 1907 1908 #if defined(BCM_METROLITE_SUPPORT) 1909 /* Retreive internal configuration no. */ 1910 BCM_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 1911 #endif 1912 1913 /* In saber2 HW design supports OAMP only on port 5 */ 1914 if (port != _BCM_SB2_SAT_OAMP_PHY_PORT_NUMBER) { 1915 LOG_CLI((BSL_META_U(unit, 1916 "OAMP HotSwap is not supported for port %d.\n"), port)); 1917 return BCM_E_PORT; 1918 } 1919 1920 #if defined(BCM_METROLITE_SUPPORT) 1921 if (SOC_IS_METROLITE(unit)){ 1922 SOC_IF_ERROR_RETURN(soc_metrolite_get_port_block( 1923 unit,port,&block)); 1924 1925 for (loop = 0; loop < ML_MAX_PORTS_PER_BLOCK; loop++) { 1926 if ((IS_LP_PORT(unit, (*ml_block_ports[unit])[block][loop])) || 1927 (IS_SUBTAG_PORT(unit, (*ml_block_ports[unit])[block][loop]))) { 1928 LOG_CLI((BSL_META_U(unit, 1929 "HotSwap is not supported for \ 1930 Subport Coe/LinkPhy Ports\n Disable CoE and run the API again.\n"))); 1931 return BCM_E_PARAM; 1932 } 1933 } 1934 }else 1935 #endif 1936 { 1937 SOC_IF_ERROR_RETURN(soc_saber2_get_port_block( 1938 unit,port,&block)); 1939 1940 /* CoE ports cannot be hotswapped */ 1941 if (IS_SUBTAG_PORT(unit, port)) { 1942 LOG_CLI((BSL_META_U(unit, 1943 "HotSwap is not supported for CoE port\n"))); 1944 return BCM_E_PARAM; 1945 } 1946 } 1947 1948 /* Check whether SAT is initialized */ 1949 BCM_IF_ERROR_RETURN(bcm_sb2_sat_init_check(unit)); 1950 1951 SOC_IF_ERROR_RETURN(READ_OAMP_ENABLEr(unit, &rval)); 1952 oamp_status = soc_reg_field_get(unit, OAMP_ENABLEr, rval, ENABLEf); 1953 if(oamp_status == enable) { 1954 /* Status already met the requirement */ 1955 return BCM_E_NONE; 1956 } 1957 1958 rv = bcm_esw_linkscan_mode_get(unit, port, &init_mode); 1959 if(rv == BCM_E_PORT) { 1960 /* port not available. Maybe in oamp mode. */ 1961 init_mode = BCM_LINKSCAN_MODE_NONE; 1962 } 1963 1964 if (enable == TRUE) { 1965 /* Ethernet to OAMP sequence */ 1966 1967 /* 1. Stop linkscan */ 1968 bcm_esw_kt2_port_unlock(unit); 1969 BCM_IF_ERROR_RETURN(bcm_esw_linkscan_mode_set( 1970 unit, port, BCM_LINKSCAN_MODE_NONE)); 1971 bcm_esw_kt2_port_lock(unit); 1972 1973 /* 2. To stop the incoming traffic, disable XLMAC Rx */ 1974 SOC_IF_ERROR_RETURN(READ_XLMAC_CTRLr( 1975 unit, port, &xlmac_ctrl)); 1976 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, TX_ENf, 1); 1977 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, RX_ENf, 0); 1978 SOC_IF_ERROR_RETURN(WRITE_XLMAC_CTRLr( 1979 unit, port, xlmac_ctrl)); 1980 sal_udelay((10*time_multiplier)); 1981 1982 /* 3. Bring the port down. */ 1983 BCM_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm( 1984 unit, MEM_BLOCK_ANY, 0, &epc_link_bmap_entry)); 1985 soc_mem_pbmp_field_get(unit, EPC_LINK_BMAPm, 1986 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 1987 BCM_PBMP_PORT_REMOVE(link_pbmp, port); 1988 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, 1989 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 1990 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 1991 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 1992 1993 /* 4. Save the current configuration of PAUSE/PFC flow control */ 1994 BCM_IF_ERROR_RETURN(bcm_esw_port_speed_get( 1995 unit, port, &port_speed)); 1996 if (!(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 1997 if (port_speed == 10000) { 1998 BCM_IF_ERROR_RETURN(READ_XPORT_TO_MMU_BKPr( 1999 unit, block, &pfc_enable)); 2000 BCM_IF_ERROR_RETURN(WRITE_XPORT_TO_MMU_BKPr( 2001 unit, block, 0)); 2002 } 2003 } 2004 2005 /* 5. Flush any pending egress packets */ 2006 READ_XP_TXFIFO_PKT_DROP_CTLr(unit, port, &rval); 2007 soc_reg_field_set(unit, XP_TXFIFO_PKT_DROP_CTLr, &rval, 2008 DROP_ENf, 1); 2009 WRITE_XP_TXFIFO_PKT_DROP_CTLr(unit, port, rval); 2010 2011 BCM_IF_ERROR_RETURN(bcm_kt2_cosq_port_flush( 2012 unit, port, bcmCosqFlushTypeQueue)); 2013 2014 /* 6. Wait until all egress port packets are drained. */ 2015 try_count=0; 2016 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 2017 BCM_IF_ERROR_RETURN(READ_XP_TXFIFO_CELL_CNTr( 2018 unit, port, &rval)); 2019 soc_reg_field_set(unit, XP_TXFIFO_CELL_CNTr, 2020 &rval, CELL_CNTf, 0); 2021 BCM_IF_ERROR_RETURN(WRITE_XP_TXFIFO_CELL_CNTr( 2022 unit, port, rval)); 2023 } 2024 2025 soc_timeout_init(&to, timeout_usec, min_polls); 2026 for (try=0; try<100 && try_count < 10 ; try++) { 2027 if(soc_timeout_check(&to)) { 2028 LOG_ERROR(BSL_LS_BCM_PORT, 2029 (BSL_META_U(unit, 2030 "%s:%d:TimeOut InternalError\n"), 2031 FUNCTION_NAME(),__LINE__)); 2032 return BCM_E_INTERNAL; 2033 } 2034 2035 BCM_IF_ERROR_RETURN(READ_XP_TXFIFO_CELL_CNTr ( 2036 unit,port, &rval)); 2037 cell_cnt=soc_reg_field_get(unit, XP_TXFIFO_CELL_CNTr, 2038 rval, CELL_CNTf); 2039 if (cell_cnt == 0) { 2040 try_count++; 2041 break; 2042 } 2043 } 2044 2045 /* 6a. Disable Flush */ 2046 READ_XP_TXFIFO_PKT_DROP_CTLr(unit, port, &rval); 2047 soc_reg_field_set(unit, XP_TXFIFO_PKT_DROP_CTLr, &rval, 2048 DROP_ENf, 0); 2049 WRITE_XP_TXFIFO_PKT_DROP_CTLr(unit, port, rval); 2050 2051 2052 if (try == 100) { 2053 LOG_ERROR(BSL_LS_BCM_PORT, 2054 (BSL_META_U(unit, 2055 "%s:%d: TimeOut - Drain Egress packets\n"), 2056 FUNCTION_NAME(),__LINE__)); 2057 return BCM_E_TIMEOUT; 2058 } 2059 2060 /* 7. Disable XLMAC Tx and put XLMAC in reset */ 2061 SOC_IF_ERROR_RETURN(READ_XLMAC_CTRLr( 2062 unit, port, &xlmac_ctrl)); 2063 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, TX_ENf, 0); 2064 SOC_IF_ERROR_RETURN(WRITE_XLMAC_CTRLr( 2065 unit, port, xlmac_ctrl)); 2066 sal_udelay((10*time_multiplier)); 2067 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, SOFT_RESETf, 1); 2068 SOC_IF_ERROR_RETURN(WRITE_XLMAC_CTRLr( 2069 unit, port, xlmac_ctrl)); 2070 sal_udelay((10*time_multiplier)); 2071 2072 /* 8. Disable port 5 */ 2073 if (SOC_IS_METROLITE(unit)){ 2074 SOC_IF_ERROR_RETURN(READ_XLPORT_ENABLE_REGr(unit, port, &rval)); 2075 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, PORT0f, 0); 2076 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ENABLE_REGr(unit, port, rval)); 2077 } else{ 2078 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr(unit, port, &rval)); 2079 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval, PORT0f, 0); 2080 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, port, rval)); 2081 } 2082 2083 /* 8a. Detach PHY */ 2084 BCM_IF_ERROR_RETURN(soc_saber2_port_detach(unit, port)); 2085 2086 /* 9. Enable OAMP */ 2087 BCM_IF_ERROR_RETURN(bcm_sb2_sat_oamp_enable_set(unit, enable)); 2088 BCM_IF_ERROR_RETURN(bcm_katana2_cosq_reconfigure_flexio(unit, port, 0)); 2089 #if defined(BCM_METROLITE_SUPPORT) 2090 if (SOC_IS_METROLITE(unit)){ 2091 SOC_IF_ERROR_RETURN(_soc_ml_mmu_reconfigure(unit, port)); 2092 }else 2093 #endif 2094 { 2095 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_reconfigure(unit, port)); 2096 } 2097 2098 /* 10. Bring the port back up. */ 2099 BCM_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm( 2100 unit, MEM_BLOCK_ANY, 0, &epc_link_bmap_entry)); 2101 soc_mem_pbmp_field_get(unit, EPC_LINK_BMAPm, 2102 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 2103 BCM_PBMP_PORT_ADD(link_pbmp, port); 2104 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, 2105 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 2106 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 2107 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 2108 2109 /* Keep PORT in STP FWD state w.r.t OAMP engine */ 2110 BCM_IF_ERROR_RETURN(bcm_esw_port_stp_set(unit, port, 2111 BCM_STG_STP_FORWARD)); 2112 2113 /* Enable Egress */ 2114 sal_memset(&egr_enable_entry, 0, sizeof(egr_enable_entry_t)); 2115 soc_mem_field32_set(unit, EGR_ENABLEm, &egr_enable_entry, 2116 PRT_ENABLEf, 1); 2117 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, 2118 &egr_enable_entry)); 2119 2120 /* Update port bitmaps */ 2121 #if defined(BCM_METROLITE_SUPPORT) 2122 if (SOC_IS_METROLITE(unit)){ 2123 first_port = (*ml_block_ports[unit])[block][0]; 2124 port_speed = bcm56270_speed[unit][cfg_num][first_port]; 2125 } else 2126 #endif 2127 { 2128 first_port = (*sb2_block_ports[unit])[block][0]; 2129 port_speed = bcm56260_speed[unit][_sb2_config_id[unit]][first_port]; 2130 } 2131 if (port_speed <= 2500) { 2132 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, port); 2133 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, port); 2134 } else { 2135 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 2136 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, port); 2137 } 2138 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 2139 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, port); 2140 2141 SOC_PBMP_PORT_REMOVE(si->port.bitmap, port); 2142 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port); 2143 2144 SOC_PBMP_PORT_ADD(si->intp.bitmap, port); 2145 SOC_PBMP_PORT_REMOVE(si->intp.disabled_bitmap, port); 2146 2147 soc_katana2_pbmp_all_resync(unit) ; 2148 soc_esw_dport_init(unit); 2149 2150 } else { 2151 /* OAMP to Ethernet sequence */ 2152 2153 /* 1. Check whether the GTFs and CTFs are destroyed */ 2154 if((bcm_common_sat_gtf_inuse(unit)) || 2155 (bcm_common_sat_ctf_inuse(unit))) { 2156 LOG_ERROR(BSL_LS_BCM_PORT, 2157 (BSL_META_U(unit, 2158 "GTFs and CTFs not cleaned up\n"))); 2159 return BCM_E_FAIL; 2160 } 2161 2162 /* 2. Disable SAT redirection to OAMP from ingress and egress pipe */ 2163 BCM_IF_ERROR_RETURN( 2164 bcm_sb2_sat_endpoint_destroy_all(unit, BCM_SAT_ENDPOINT_UPMEP)); 2165 BCM_IF_ERROR_RETURN( 2166 bcm_sb2_sat_endpoint_destroy_all(unit, BCM_SAT_ENDPOINT_DOWNMEP)); 2167 2168 /* 3. Bring the port down */ 2169 BCM_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm( 2170 unit, MEM_BLOCK_ANY, 0, &epc_link_bmap_entry)); 2171 soc_mem_pbmp_field_get(unit, EPC_LINK_BMAPm, 2172 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 2173 BCM_PBMP_PORT_REMOVE(link_pbmp, port); 2174 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, 2175 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 2176 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 2177 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 2178 2179 /* 4. Flush any pending egress packets */ 2180 READ_XP_TXFIFO_PKT_DROP_CTLr(unit, port, &rval); 2181 soc_reg_field_set(unit, XP_TXFIFO_PKT_DROP_CTLr, &rval, 2182 DROP_ENf, 1); 2183 WRITE_XP_TXFIFO_PKT_DROP_CTLr(unit, port, rval); 2184 2185 BCM_IF_ERROR_RETURN(bcm_kt2_cosq_port_flush( 2186 unit, port, bcmCosqFlushTypeQueue)); 2187 2188 /* 5. Wait until all egress port packets are drained. */ 2189 try_count=0; 2190 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 2191 BCM_IF_ERROR_RETURN(READ_XP_TXFIFO_CELL_CNTr( 2192 unit, port, &rval)); 2193 soc_reg_field_set(unit, XP_TXFIFO_CELL_CNTr, 2194 &rval, CELL_CNTf, 0); 2195 BCM_IF_ERROR_RETURN(WRITE_XP_TXFIFO_CELL_CNTr( 2196 unit, port, rval)); 2197 } 2198 2199 soc_timeout_init(&to, timeout_usec, min_polls); 2200 for (try=0; try<100 && try_count < 10 ; try++) { 2201 if(soc_timeout_check(&to)) { 2202 LOG_ERROR(BSL_LS_BCM_PORT, 2203 (BSL_META_U(unit, 2204 "%s:%d:TimeOut InternalError\n"), 2205 FUNCTION_NAME(),__LINE__)); 2206 return BCM_E_INTERNAL; 2207 } 2208 2209 BCM_IF_ERROR_RETURN(READ_XP_TXFIFO_CELL_CNTr ( 2210 unit,port, &rval)); 2211 cell_cnt=soc_reg_field_get(unit, XP_TXFIFO_CELL_CNTr, 2212 rval, CELL_CNTf); 2213 if (cell_cnt == 0) { 2214 try_count++; 2215 break; 2216 } 2217 } 2218 2219 /* 5a. Disable Flush */ 2220 READ_XP_TXFIFO_PKT_DROP_CTLr(unit, port, &rval); 2221 soc_reg_field_set(unit, XP_TXFIFO_PKT_DROP_CTLr, &rval, 2222 DROP_ENf, 0); 2223 WRITE_XP_TXFIFO_PKT_DROP_CTLr(unit, port, rval); 2224 2225 if (try == 100) { 2226 LOG_ERROR(BSL_LS_BCM_PORT, 2227 (BSL_META_U(unit, 2228 "%s:%d: TimeOut - Drain Egress packets\n"), 2229 FUNCTION_NAME(),__LINE__)); 2230 return BCM_E_TIMEOUT; 2231 } 2232 2233 /* 6. Disable OAMP */ 2234 BCM_IF_ERROR_RETURN(bcm_sb2_sat_oamp_enable_set(unit, enable)); 2235 #if defined(BCM_METROLITE_SUPPORT) 2236 if (SOC_IS_METROLITE(unit)){ 2237 SOC_IF_ERROR_RETURN(_soc_ml_mmu_reconfigure(unit, port)); 2238 }else 2239 #endif 2240 { 2241 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_reconfigure(unit, port)); 2242 } 2243 2244 /* 7. Enable port 5 */ 2245 if (SOC_IS_METROLITE(unit)){ 2246 SOC_IF_ERROR_RETURN(READ_XLPORT_ENABLE_REGr(unit, port, &rval)); 2247 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, PORT0f, 1); 2248 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ENABLE_REGr(unit, port, rval)); 2249 }else{ 2250 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr(unit, port, &rval)); 2251 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval, PORT0f, 1); 2252 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, port, rval)); 2253 } 2254 2255 /* 8. Enable XLMAC Tx and Rx and being XLMAC out of reset */ 2256 SOC_IF_ERROR_RETURN(READ_XLMAC_CTRLr( 2257 unit, port, &xlmac_ctrl)); 2258 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, SOFT_RESETf, 0); 2259 SOC_IF_ERROR_RETURN(WRITE_XLMAC_CTRLr( 2260 unit, port, xlmac_ctrl)); 2261 sal_udelay((10*time_multiplier)); 2262 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, TX_ENf, 1); 2263 soc_reg64_field32_set(unit, XLMAC_CTRLr, &xlmac_ctrl, RX_ENf, 1); 2264 SOC_IF_ERROR_RETURN(WRITE_XLMAC_CTRLr( 2265 unit, port, xlmac_ctrl)); 2266 sal_udelay((10*time_multiplier)); 2267 2268 /* 9. Bring the port back up. */ 2269 BCM_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm( 2270 unit, MEM_BLOCK_ANY, 0, &epc_link_bmap_entry)); 2271 soc_mem_pbmp_field_get(unit, EPC_LINK_BMAPm, 2272 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 2273 BCM_PBMP_PORT_ADD(link_pbmp, port); 2274 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, 2275 &epc_link_bmap_entry, PORT_BITMAPf,&link_pbmp); 2276 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 2277 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 2278 2279 /* Update port bitmaps */ 2280 #if defined(BCM_METROLITE_SUPPORT) 2281 if (SOC_IS_METROLITE(unit)){ 2282 first_port = (*ml_block_ports[unit])[block][0]; 2283 port_speed = bcm56270_speed[unit][cfg_num][first_port]; 2284 } else 2285 #endif 2286 { 2287 first_port = (*sb2_block_ports[unit])[block][0]; 2288 port_speed = bcm56260_speed[unit][_sb2_config_id[unit]][first_port]; 2289 } 2290 if (port_speed <= 2500) { 2291 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, port); 2292 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 2293 } else { 2294 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, port); 2295 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 2296 } 2297 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, port); 2298 SOC_PBMP_PORT_ADD(si->ether.bitmap, port); 2299 2300 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, port); 2301 SOC_PBMP_PORT_ADD(si->port.bitmap, port); 2302 2303 SOC_PBMP_PORT_ADD(si->intp.disabled_bitmap, port); 2304 SOC_PBMP_PORT_REMOVE(si->intp.bitmap, port); 2305 2306 soc_katana2_pbmp_all_resync(unit) ; 2307 soc_esw_dport_init(unit); 2308 2309 SOC_IF_ERROR_RETURN(soc_saber2_port_attach(unit, block , port)); 2310 2311 /* 10. Enable linkscan */ 2312 if (init_mode == BCM_LINKSCAN_MODE_NONE) { 2313 init_mode = BCM_LINKSCAN_MODE_SW; 2314 } 2315 bcm_esw_kt2_port_unlock(unit); 2316 2317 #ifdef BCM_PORT_DEFAULT_DISABLE 2318 port_enable = FALSE; 2319 #else 2320 port_enable = TRUE; 2321 #endif /* BCM_PORT_DEFAULT_DISABLE */ 2322 2323 BCM_IF_ERROR_RETURN(bcm_esw_port_enable_set(unit, port, port_enable)); 2324 #if defined(BCM_METROLITE_SUPPORT) 2325 if (SOC_IS_METROLITE(unit)){ 2326 port_speed = (*ml_port_speeds[unit])[block][0]; 2327 }else 2328 #endif 2329 { 2330 port_speed = (*sb2_port_speeds[unit])[block][0]; 2331 } 2332 BCM_IF_ERROR_RETURN(bcm_esw_port_speed_max(unit, port, &max_speed)); 2333 port_speed = port_speed > max_speed ? max_speed : port_speed; 2334 BCM_IF_ERROR_RETURN(bcm_esw_port_speed_set(unit, port, port_speed)); 2335 2336 BCM_IF_ERROR_RETURN(bcm_esw_port_learn_set(unit, port, 2337 BCM_PORT_LEARN_ARL | BCM_PORT_LEARN_FWD)); 2338 BCM_IF_ERROR_RETURN(bcm_esw_port_stp_set(unit, port, 2339 BCM_STG_STP_FORWARD)); 2340 BCM_IF_ERROR_RETURN(bcm_esw_port_loopback_set(unit, port, 2341 BCM_PORT_LOOPBACK_NONE)); 2342 2343 /* if sat is enabled with sat_enable config, then tpid would not set */ 2344 rv = bcm_esw_port_tpid_set(unit, port, 2345 _bcm_fb2_outer_tpid_default_get(unit)); 2346 if (BCM_FAILURE(rv)) { 2347 LOG_WARN(BSL_LS_BCM_PORT, 2348 (BSL_META_U(unit, 2349 "Failed to set default TPID: %s\n"), 2350 bcm_errmsg(rv))); 2351 } 2352 if (soc_feature(unit, soc_feature_inner_tpid_enable)) { 2353 /* Enable the default inner TPID. */ 2354 rv = bcm_esw_port_inner_tpid_set(unit, port, 2355 _bcm_fb2_outer_tpid_default_get(unit)); 2356 if (BCM_FAILURE(rv)) { 2357 LOG_WARN(BSL_LS_BCM_PORT, 2358 (BSL_META_U(unit, 2359 "Failed to set default Inner TPID: %s\n"), 2360 bcm_errmsg(rv))); 2361 } 2362 } 2363 2364 BCM_IF_ERROR_RETURN(bcm_esw_linkscan_mode_set(unit, port, init_mode)); 2365 bcm_esw_kt2_port_lock(unit); 2366 } 2367 2368 #ifdef BCM_WARM_BOOT_SUPPORT 2369 SOC_CONTROL_LOCK(unit); 2370 SOC_CONTROL(unit)->scache_dirty = 1; 2371 SOC_CONTROL_UNLOCK(unit); 2372 #endif 2373 2374 return BCM_E_NONE; 2375 } 2376 2377 int _bcm_saber2_mmu_dest_port_cfg_init(int unit, int port) 2378 { 2379 uint32 rval, rval1, rval2, rval3; 2380 int start_pp_port, end_pp_port, pp_port; 2381 soc_info_t *si= &SOC_INFO(unit); 2382 2383 if (IS_EXT_MEM_PORT(unit, port)) { 2384 2385 SOC_IF_ERROR_RETURN(READ_DEST_PORT_CFG_0r(unit, &rval)); 2386 rval |= (1 << port); 2387 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_0r(unit, rval)); 2388 2389 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &rval)); 2390 rval |= (1 << port); 2391 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, rval)); 2392 2393 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, port, &rval3)); 2394 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval3, BUFF_TYPEf, 1); 2395 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, port, rval3)); 2396 2397 if (si->port_num_subport[port] > 0) { 2398 start_pp_port = si->port_subport_base[port]; 2399 end_pp_port = si->port_subport_base[port] + 2400 si->port_num_subport[port]; 2401 2402 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &rval)); 2403 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_1r(unit, &rval1)); 2404 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_2r(unit, &rval2)); 2405 for (pp_port = start_pp_port; pp_port < end_pp_port; pp_port++) { 2406 if (( pp_port <= 31 )){ 2407 rval |= (1 << pp_port); 2408 } else if (( pp_port >31 ) && (pp_port <= 63) ){ 2409 rval1 |= (1 << (pp_port - 32)); 2410 } else if (( pp_port > 63 ) && (pp_port <= 95) ){ 2411 rval2 |= (1 << (pp_port - 64)); 2412 } 2413 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, pp_port, &rval3)); 2414 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval3, BUFF_TYPEf, 1); 2415 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, pp_port, rval3)); 2416 /* Add subport in ext_pbmp */ 2417 SOC_PBMP_PORT_ADD(PBMP_EXT_MEM(unit), pp_port); 2418 } 2419 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, rval)); 2420 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_1r(unit, rval1)); 2421 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_2r(unit, rval2)); 2422 } 2423 } else { 2424 SOC_IF_ERROR_RETURN(READ_DEST_PORT_CFG_0r(unit, &rval)); 2425 rval &= ~(1 << port); 2426 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_0r(unit, rval)); 2427 2428 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &rval)); 2429 rval &= ~(1 << port); 2430 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, rval)); 2431 2432 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, port, &rval3)); 2433 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval3, BUFF_TYPEf, 0); 2434 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, port, rval3)); 2435 2436 if (si->port_num_subport[port] > 0) { 2437 start_pp_port = si->port_subport_base[port]; 2438 end_pp_port = si->port_subport_base[port] + 2439 si->port_num_subport[port]; 2440 2441 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &rval)); 2442 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_1r(unit, &rval1)); 2443 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_2r(unit, &rval2)); 2444 for (pp_port = start_pp_port; pp_port < end_pp_port; pp_port++) { 2445 if (( pp_port <= 31 )){ 2446 rval &= ~(1 << pp_port); 2447 } else if (( pp_port >31 ) && (pp_port <= 63) ){ 2448 rval1 &= ~(1 << (pp_port - 32)); 2449 } else if (( pp_port > 63 ) && (pp_port <= 95) ){ 2450 rval2 &= ~(1 << (pp_port - 64)); 2451 } 2452 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, pp_port, &rval3)); 2453 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval, BUFF_TYPEf, 0); 2454 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, pp_port, rval3)); 2455 /* Remove subport from ext_pbmp */ 2456 SOC_PBMP_PORT_REMOVE(PBMP_EXT_MEM(unit), pp_port); 2457 } 2458 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, rval)); 2459 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_1r(unit, rval1)); 2460 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_2r(unit, rval2)); 2461 } 2462 } 2463 return SOC_E_NONE; 2464 } 2465 2466 int _bcm_saber2_mmu_credit_reset_ext_mem(int unit, int port) 2467 { 2468 uint32 rval = 0; 2469 soc_info_t *si= &SOC_INFO(unit); 2470 uint8 block=0; 2471 uint8 loop; 2472 uint8 try_loop; 2473 int block_port; 2474 uint32 rval1 = 0; 2475 uint32 start_addr = 0, end_addr = 0; 2476 uint32 try_count = 0; 2477 soc_timeout_t to = {0}; 2478 sal_usecs_t timeout_usec = 100000; 2479 int min_polls = 100; 2480 uint32 egr_fifo_depth = 0; 2481 int threshold; 2482 int port_bw, start_threshold = 0; 2483 int block_max_nxtaddr = 0; 2484 soc_field_t mmu_intf_reset_fld[] = { 2485 XQ1_MMU_INTF_RESETf, 2486 XQ2_MMU_INTF_RESETf, XQ3_MMU_INTF_RESETf, 2487 XQ4_MMU_INTF_RESETf, XQ5_MMU_INTF_RESETf, 2488 XQ6_MMU_INTF_RESETf, XQ7_MMU_INTF_RESETf, 2489 XQ8_MMU_INTF_RESETf, XQ9_MMU_INTF_RESETf}; 2490 txlp_port_addr_map_table_entry_t txlp_port_addr_map_table_entry={{0}}; 2491 2492 BCM_IF_ERROR_RETURN(soc_saber2_get_port_block(unit,port,&block)); 2493 2494 block_max_nxtaddr = block_max_startaddr[block]; 2495 for (loop = 0;loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 2496 block_port=(*sb2_block_ports[unit])[block][loop]; 2497 2498 /* For block 6, we only update current port and not all 2499 ports in the block */ 2500 if(block == 6) { 2501 if (block_port != port) { 2502 continue; 2503 } 2504 BCM_IF_ERROR_RETURN(READ_DEQ_EFIFO_CFGr(unit,block_port,&rval)); 2505 block_max_nxtaddr = soc_reg_field_get(unit, DEQ_EFIFO_CFGr, 2506 rval, EGRESS_FIFO_START_ADDRESSf); 2507 } 2508 2509 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 2510 2511 /* Reconfigure DEQ FIFO depth based on ext mem configuration */ 2512 BCM_IF_ERROR_RETURN(READ_DEQ_EFIFO_CFGr(unit,block_port,&rval)); 2513 2514 if (si->port_speed_max[block_port] <= 1000) { 2515 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, block_port)) ? 10 : 2; 2516 threshold = (IS_EXT_MEM_PORT(unit, block_port)) ? 8 : 1; 2517 port_bw = 25; 2518 start_threshold = 7; 2519 } else if (si->port_speed_max[block_port] <= 2500) { 2520 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, block_port)) ? 19 : 2; 2521 threshold = (IS_EXT_MEM_PORT(unit, block_port)) ? 15 : 1; 2522 port_bw = 63; 2523 start_threshold = 14; 2524 } else if (si->port_speed_max[block_port] <= 13000) { 2525 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, block_port)) ? 53 : 10; 2526 threshold = (IS_EXT_MEM_PORT(unit, block_port)) ? 49 : 1; 2527 port_bw = 325; 2528 start_threshold = 48; 2529 } else { 2530 LOG_ERROR(BSL_LS_BCM_PORT, 2531 (BSL_META_U(unit, "Invalid Speed config\n"))); 2532 return BCM_E_FAIL; 2533 } 2534 2535 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 2536 EGRESS_FIFO_START_ADDRESSf, block_max_nxtaddr); 2537 2538 if ((block_max_nxtaddr + egr_fifo_depth) > block_max_endaddr[block]) { 2539 egr_fifo_depth = (block_max_endaddr[block] - 2540 block_max_nxtaddr)+1; 2541 block_max_nxtaddr = block_max_endaddr[block]; 2542 } else { 2543 block_max_nxtaddr += egr_fifo_depth; 2544 } 2545 if (egr_fifo_depth == 1) { 2546 LOG_CLI((BSL_META_U(unit, 2547 "WARN: EGR_FIFO_DEPTH IS ZERO for port=%d\n"), 2548 block_port)); 2549 } 2550 2551 if ((IS_EXT_MEM_PORT(unit, block_port)) && 2552 !(PBMP_MEMBER(si->linkphy_pbm, block_port))) { 2553 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 2554 EGRESS_FIFO_XMIT_OVERSPEED_RATE_LIMITERf, 1); 2555 } else { 2556 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 2557 EGRESS_FIFO_XMIT_OVERSPEED_RATE_LIMITERf, 0); 2558 } 2559 2560 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 2561 EGRESS_FIFO_DEPTHf, egr_fifo_depth); 2562 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 2563 EGRESS_FIFO_XMIT_THRESHOLDf, threshold); 2564 BCM_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr( 2565 unit,block_port,rval)); 2566 2567 BCM_IF_ERROR_RETURN(_bcm_saber2_mmu_dest_port_cfg_init(unit, port)); 2568 2569 /* Port BW Ctrl */ 2570 SOC_IF_ERROR_RETURN(READ_TOQ_PORT_BW_CTRLr(unit, 2571 block_port, &rval)); 2572 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 2573 PORT_BWf, port_bw); 2574 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 2575 START_THRESHOLDf, start_threshold); 2576 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, 2577 block_port, rval)); 2578 2579 } /* If SOC_PBMP_MEMBER */ 2580 if(block == 6) { 2581 break; 2582 } 2583 } /* for loop */ 2584 2585 2586 /* WORK-AROUND for port-flushing i.e. need to repeat below step twice */ 2587 /* Refer Flexio hotswap sequence */ 2588 for (try_loop = 0; try_loop < 2; try_loop++) { 2589 /* EP Reset */ 2590 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 2591 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 2592 unit, 0)); 2593 } 2594 2595 if(block == 6) { 2596 rval1 |= (1 << port); 2597 } else { 2598 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 2599 block_port=(*sb2_block_ports[unit])[block][loop]; 2600 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 2601 rval1 |= (1 << block_port); 2602 } 2603 } 2604 } 2605 2606 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 2607 unit, rval1)); 2608 2609 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 2610 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 2611 unit, 0)); 2612 } 2613 2614 try_count = 0; 2615 do { 2616 soc_timeout_init(&to, timeout_usec, min_polls); 2617 if(soc_timeout_check(&to)) { 2618 LOG_ERROR(BSL_LS_BCM_PORT, 2619 (BSL_META_U(unit, 2620 "%s:%d:TimeOut InternalError\n"), 2621 FUNCTION_NAME(),__LINE__)); 2622 return BCM_E_INTERNAL; 2623 } 2624 try_count++; 2625 2626 BCM_IF_ERROR_RETURN(READ_DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00r( 2627 unit, &rval1)); 2628 if (rval1 == 0 ) { 2629 break; 2630 } 2631 } while (try_count != 5); 2632 2633 if (try_count == 5) { 2634 LOG_ERROR(BSL_LS_BCM_PORT, 2635 (BSL_META_U(unit, 2636 "%s:%d: TimeOut - Port reconfig vector\n"), 2637 FUNCTION_NAME(),__LINE__)); 2638 return BCM_E_TIMEOUT; 2639 } 2640 2641 sal_usleep(1000); 2642 } /* for try_loop */ 2643 2644 /* Flush existing MMU credits */ 2645 if ((block > 0) && (block < 6)) { 2646 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 2647 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 2648 &rval, mmu_intf_reset_fld[block - 1], 1); 2649 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 2650 } else if (block == 6) { 2651 loop = (port-1) % 4; 2652 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 2653 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 2654 &rval, mmu_intf_reset_fld[block + loop - 1], 1); 2655 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 2656 } else if (block == 0){ 2657 WRITE_TXLP_PORT_CREDIT_RESETr(unit, port,0xf); 2658 for (loop = 0; loop < SB2_MAX_PORTS_PER_BLOCK; loop++) { 2659 sal_memset(&txlp_port_addr_map_table_entry,0, 2660 sizeof(txlp_port_addr_map_table_entry_t)); 2661 block_port=(*sb2_block_ports[unit])[block][loop]; 2662 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port)) { 2663 2664 if (si->port_speed_max[port] <= 2500) { 2665 end_addr = start_addr + (( 8 * 4) - 1); /* 8 cells */ 2666 } else if(si->port_speed_max[port] <= 10000) { 2667 end_addr = start_addr + (( 16 * 4) - 1); 2668 } else { 2669 return BCM_E_PARAM; 2670 } 2671 2672 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 2673 &txlp_port_addr_map_table_entry,START_ADDRf,&start_addr); 2674 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 2675 &txlp_port_addr_map_table_entry,END_ADDRf,&end_addr); 2676 start_addr = end_addr+1; 2677 } 2678 2679 BCM_IF_ERROR_RETURN(WRITE_TXLP_PORT_ADDR_MAP_TABLEm( 2680 unit,SOC_INFO(unit).txlp_block[block], 2681 loop, &txlp_port_addr_map_table_entry)); 2682 } /* for loop */ 2683 } /* if else block != 0 */ 2684 2685 /* Bring Edatabuf MMU intf out of reset to get fresh credits */ 2686 if ((block > 0) && (block < 6)) { 2687 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 2688 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 2689 &rval, mmu_intf_reset_fld[block - 1], 0); 2690 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 2691 } else if(block == 6) { 2692 loop = (port-1) % 4; 2693 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 2694 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 2695 &rval, mmu_intf_reset_fld[block + loop - 1], 0); 2696 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 2697 } else if (block == 0) { 2698 WRITE_TXLP_PORT_CREDIT_RESETr(unit, port,0); 2699 } 2700 2701 return BCM_E_NONE; 2702 } 2703 2704 STATIC 2705 int _bcm_saber2_reset_toq(int unit, int queue) 2706 { 2707 mmu_toq_state_mem0_entry_t mmu_toq_state_mem0_entry = {{0}}; 2708 SOC_IF_ERROR_RETURN(READ_MMU_TOQ_STATE_MEM0m(unit, 2709 MEM_BLOCK_ANY, queue, 2710 &mmu_toq_state_mem0_entry)); 2711 if (soc_mem_field32_get(unit, MMU_TOQ_STATE_MEM0m, 2712 &mmu_toq_state_mem0_entry, 2713 EMPTYf) && 2714 soc_mem_field32_get(unit, MMU_TOQ_STATE_MEM0m, 2715 &mmu_toq_state_mem0_entry, 2716 QBLOCK_NEXT_VLDf)) { 2717 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2718 &mmu_toq_state_mem0_entry, WS_VLDf, 0); 2719 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2720 &mmu_toq_state_mem0_entry, WHITESPACEf, 0); 2721 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2722 &mmu_toq_state_mem0_entry, TAIL_OFFSETf, 0); 2723 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2724 &mmu_toq_state_mem0_entry, TAIL_BUFFERf, 0); 2725 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2726 &mmu_toq_state_mem0_entry, Q_WRPTRf, 0); 2727 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2728 &mmu_toq_state_mem0_entry, Q_RDPTRf, 0); 2729 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2730 &mmu_toq_state_mem0_entry, QBLOCK_NEXT_VLDf, 0); 2731 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2732 &mmu_toq_state_mem0_entry, QBLOCK_NEXTf, 0); 2733 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2734 &mmu_toq_state_mem0_entry, PQ_DISABLEDf, 0); 2735 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2736 &mmu_toq_state_mem0_entry, HEAD_OFFSETf, 0); 2737 soc_mem_field32_set(unit, MMU_TOQ_STATE_MEM0m, 2738 &mmu_toq_state_mem0_entry, HEAD_BUFFERf, 0); 2739 SOC_IF_ERROR_RETURN(WRITE_MMU_TOQ_STATE_MEM0m(unit, 2740 MEM_BLOCK_ANY, queue, 2741 &mmu_toq_state_mem0_entry)); 2742 } 2743 return SOC_E_NONE; 2744 } 2745 2746 /* Dynamic Helper function for MMU settings based on 2747 * memory selection (internal/external) 2748 * The memory selection is done using port config property bcmPortControlBufferExternalEnable 2749 * For Threshold values refer _soc_saber2_mmu_init_helper() 2750 */ 2751 int _bcm_saber2_mmu_init_helper_dyn(int unit, int port, int ext_mem_enable) 2752 { 2753 uint32 op_node=0; 2754 uint32 port_max_opnodes = 0; 2755 uint8 port_index = 0; 2756 soc_pbmp_t valid_port_cpu_pbmp; 2757 uint8 port_list[]={SB2_CMIC, SB2_LPBK , 2758 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 2759 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 2760 21, 22, 23, 24, 25, 26, 27, 28}; 2761 soc_port_t port_iter=0; 2762 soc_info_t *si= &SOC_INFO(unit); 2763 uint32 op_node_offset=0; 2764 mmu_thdo_opnconfig_cell_entry_t mmu_thdo_opnconfig_cell_entry={{0}}; 2765 uint32 temp_val; 2766 uint32 queue; 2767 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 2768 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 2769 _sb2_output_port_threshold_t *output_port_threshold = 2770 &_soc_sb2_mmu_intermediate_results.output_port_threshold; 2771 _sb2_general_info_t *general_info = 2772 &_soc_sb2_mmu_intermediate_results.general_info; 2773 #if defined (INCLUDE_L3) 2774 uint32 entry[SOC_MAX_MEM_FIELD_WORDS]; 2775 int ipmc_id; 2776 #endif 2777 uint32 *bmap; 2778 int word, word_count, bit; 2779 SOC_PBMP_CLEAR (valid_port_cpu_pbmp); 2780 SOC_PBMP_ASSIGN(valid_port_cpu_pbmp, PBMP_ALL(unit)); 2781 2782 /* 2.1 Internal Buffer */ 2783 if (!ext_mem_enable) { 2784 if (SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port)) { 2785 SOC_PBMP_PORT_REMOVE(PBMP_EXT_MEM (unit), port); 2786 } else { 2787 return SOC_E_NONE; 2788 } 2789 2790 op_node = 0; 2791 port_max_opnodes = 0; 2792 for(port_index = 0, op_node = 0 ; 2793 port_index < COUNTOF(port_list); 2794 port_index++, op_node += port_max_opnodes ) { 2795 2796 port_iter = port_list[port_index]; 2797 port_max_opnodes = sal_ceil_func(si->port_num_uc_cosq[port_iter],8); 2798 2799 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port_iter)) { 2800 continue; 2801 } 2802 if (port != port_iter) { 2803 continue; 2804 } 2805 if (!SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter) && 2806 (port_iter >= SB2_CMIC) && (port_iter <= SB2_LPBK)) { 2807 for (op_node_offset = 0; 2808 op_node_offset < port_max_opnodes ; 2809 op_node_offset++) { 2810 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 2811 MEM_BLOCK_ANY,op_node + op_node_offset, 2812 &mmu_thdo_opnconfig_cell_entry)); 2813 /* THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL */ 2814 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 2815 &mmu_thdo_opnconfig_cell_entry, 2816 OPN_SHARED_LIMIT_CELLf, 2817 output_port_threshold-> 2818 min_grntd_tot_shr_queue_cells_int_buff); 2819 2820 /* THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL */ 2821 temp_val = output_port_threshold-> 2822 min_grntd_tot_shr_queue_cells_int_buff - 2823 (2 * general_info->ether_mtu_cells_for_int_buff); 2824 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 2825 &mmu_thdo_opnconfig_cell_entry, 2826 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 2827 /* THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL */ 2828 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 2829 &mmu_thdo_opnconfig_cell_entry, 2830 PORT_LIMIT_ENABLE_CELLf, 0); 2831 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 2832 MEM_BLOCK_ALL,op_node + op_node_offset, 2833 &mmu_thdo_opnconfig_cell_entry)); 2834 } 2835 bmap = SOC_CONTROL(unit)->port_lls_l2_bmap[port_iter]; 2836 word_count = _SHR_BITDCLSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 2837 for (word = 0; word < word_count; word++) { 2838 if (bmap[word] == 0) { 2839 continue; 2840 } 2841 for (bit = 0; bit < SHR_BITWID; bit++) { 2842 if (!(bmap[word] & (1 << bit))) { 2843 continue; 2844 } 2845 queue = word * SHR_BITWID + bit; 2846 2847 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 2848 MEM_BLOCK_ANY,queue, 2849 &mmu_thdo_qconfig_cell_entry)); 2850 /* THDO_QCONFIG_CELL.Q_MIN_CELL */ 2851 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2852 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 2853 output_port_threshold->min_grntd_res_queue_cells_int_buff); 2854 2855 /* THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL */ 2856 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 2857 temp_val = output_port_threshold-> 2858 min_grntd_tot_shr_queue_cells_int_buff; 2859 } else { 2860 temp_val = _soc_sb2_mmu_params. 2861 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 2862 } 2863 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2864 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 2865 temp_val); 2866 2867 /* THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL */ 2868 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2869 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 2870 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 2871 2872 /* THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL */ 2873 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2874 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 2875 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 2876 2877 /* THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL = 0 */ 2878 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2879 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 2880 2881 /* THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL */ 2882 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2883 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 2884 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 2885 2886 /* THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL */ 2887 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 2888 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 2889 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2890 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 2891 _soc_sb2_mmu_params.lossless_mode_d_c ? 2892 sal_ceil_func(temp_val, 8) : temp_val); 2893 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 2894 MEM_BLOCK_ALL,queue, 2895 &mmu_thdo_qconfig_cell_entry)); 2896 2897 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 2898 MEM_BLOCK_ANY,queue, 2899 &mmu_thdo_qoffset_cell_entry)); 2900 2901 /* THDO_QOFFSET_CELL.RESET_OFFSET_CELL */ 2902 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 2903 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 2904 2905 /* THDO_QOFFSET_CELL.LIMIT_RED_CELL */ 2906 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 2907 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 2908 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 2909 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 2910 _soc_sb2_mmu_params.lossless_mode_d_c ? 2911 sal_ceil_func(temp_val, 8) : temp_val); 2912 2913 /* THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL */ 2914 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 2915 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 2916 /* THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL */ 2917 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 2918 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 2919 2920 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 2921 MEM_BLOCK_ALL,queue, 2922 &mmu_thdo_qoffset_cell_entry)); 2923 SOC_IF_ERROR_RETURN(_bcm_saber2_reset_toq(unit, queue)); 2924 } 2925 } 2926 } 2927 } 2928 2929 SOC_IF_ERROR_RETURN(_bcm_saber2_mmu_dest_port_cfg_init(unit, port)); 2930 } else { 2931 /* 2.2 External Buffer */ 2932 if (SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port)) { 2933 return SOC_E_NONE; 2934 } 2935 SOC_PBMP_PORT_ADD(PBMP_EXT_MEM (unit), port); 2936 for(port_index = 0, op_node = 0 ; 2937 port_index < COUNTOF(port_list); 2938 port_index++, op_node += port_max_opnodes ) { 2939 2940 port_iter = port_list[port_index]; 2941 port_max_opnodes = sal_ceil_func(si->port_num_uc_cosq[port_iter],8); 2942 2943 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port_iter)) { 2944 continue; 2945 } 2946 if (port != port_iter) { 2947 continue; 2948 } 2949 2950 if (!IS_CPU_PORT(unit, port_iter) && 2951 (port_iter > SB2_CMIC) && (port_iter <= SB2_LPBK) && 2952 SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter)) { 2953 2954 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 2955 MEM_BLOCK_ANY,op_node , &mmu_thdo_opnconfig_cell_entry)); 2956 2957 /* THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL */ 2958 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 2959 &mmu_thdo_opnconfig_cell_entry, 2960 OPN_SHARED_LIMIT_CELLf, 2961 output_port_threshold-> 2962 min_grntd_tot_shr_queue_cells_ext_buff); 2963 2964 /* THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL */ 2965 temp_val = output_port_threshold-> 2966 min_grntd_tot_shr_queue_cells_ext_buff - 2967 (2 * general_info->ether_mtu_cells_for_ext_buff); 2968 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 2969 &mmu_thdo_opnconfig_cell_entry, 2970 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 2971 2972 /* THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL */ 2973 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 2974 &mmu_thdo_opnconfig_cell_entry, 2975 PORT_LIMIT_ENABLE_CELLf, 0); 2976 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 2977 MEM_BLOCK_ALL,op_node, 2978 &mmu_thdo_opnconfig_cell_entry)); 2979 bmap = SOC_CONTROL(unit)->port_lls_l2_bmap[port_iter]; 2980 word_count = _SHR_BITDCLSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 2981 for (word = 0; word < word_count; word++) { 2982 if (bmap[word] == 0) { 2983 continue; 2984 } 2985 for (bit = 0; bit < SHR_BITWID; bit++) { 2986 if (!(bmap[word] & (1 << bit))) { 2987 continue; 2988 } 2989 queue = word * SHR_BITWID + bit; 2990 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 2991 MEM_BLOCK_ANY,queue, 2992 &mmu_thdo_qconfig_cell_entry)); 2993 /* THDO_QCONFIG_CELL.Q_MIN_CELL */ 2994 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 2995 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 2996 output_port_threshold->min_grntd_res_queue_cells_ext_buff); 2997 2998 /* THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL */ 2999 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 3000 temp_val = output_port_threshold-> 3001 min_grntd_tot_shr_queue_cells_ext_buff; 3002 } else { 3003 temp_val = _soc_sb2_mmu_params. 3004 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 3005 } 3006 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3007 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 3008 temp_val); 3009 3010 /* THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL */ 3011 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3012 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 3013 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 3014 3015 /* THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL */ 3016 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3017 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 3018 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 3019 3020 /* THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL */ 3021 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3022 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 3023 3024 /* THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL */ 3025 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3026 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 3027 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 3028 3029 /* THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL */ 3030 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 3031 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 3032 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3033 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 3034 _soc_sb2_mmu_params.lossless_mode_d_c ? 3035 sal_ceil_func(temp_val, 8) : temp_val); 3036 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 3037 MEM_BLOCK_ALL,queue, 3038 &mmu_thdo_qconfig_cell_entry)); 3039 3040 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 3041 MEM_BLOCK_ANY,queue, 3042 &mmu_thdo_qoffset_cell_entry)); 3043 /* THDO_QOFFSET_CELL.RESET_OFFSET_CELL */ 3044 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3045 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 3046 3047 /* THDO_QOFFSET_CELL.LIMIT_RED_CELL */ 3048 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 3049 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 3050 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3051 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 3052 _soc_sb2_mmu_params.lossless_mode_d_c ? 3053 sal_ceil_func(temp_val, 8) : temp_val); 3054 3055 /* THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL */ 3056 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3057 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 3058 /* THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL */ 3059 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3060 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 3061 3062 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 3063 MEM_BLOCK_ALL,queue, 3064 &mmu_thdo_qoffset_cell_entry)); 3065 SOC_IF_ERROR_RETURN(_bcm_saber2_reset_toq(unit, queue)); 3066 } 3067 } 3068 } 3069 } 3070 3071 SOC_IF_ERROR_RETURN(_bcm_saber2_mmu_credit_reset_ext_mem(unit, port)) ; 3072 } 3073 3074 #if defined (INCLUDE_L3) 3075 /* IPMC configuration */ 3076 soc_mem_lock(unit, L3_IPMCm); 3077 for (ipmc_id = soc_mem_index_min(unit, L3_IPMCm); 3078 ipmc_id <= soc_mem_index_max(unit, L3_IPMCm); 3079 ipmc_id++) { 3080 if (_bcm_sb2_ipmc_port_ext_queue_count(unit, ipmc_id, port)) { 3081 BCM_IF_ERROR_RETURN(soc_mem_read(unit, L3_IPMCm, MEM_BLOCK_ANY, 3082 ipmc_id, entry)); 3083 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_INTERNALf, 0); 3084 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_EXTERNALf, 0); 3085 if (!ext_mem_enable) { 3086 SOC_PBMP_ITER (PBMP_EXT_MEM (unit), port_iter) { 3087 if (port_iter < SB2_LPBK) { 3088 if (_bcm_sb2_ipmc_port_ext_queue_count( 3089 unit, ipmc_id, port_iter)) { 3090 soc_mem_field32_set(unit, L3_IPMCm, entry, 3091 EXT_Q_EXTERNALf, 1); 3092 } 3093 } 3094 } 3095 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_INTERNALf, 1); 3096 } else { 3097 PBMP_ITER(PBMP_PORT_ALL(unit), port_iter){ 3098 if (port_iter < SB2_LPBK) { 3099 if (!SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter) && 3100 _bcm_sb2_ipmc_port_ext_queue_count( 3101 unit, ipmc_id, port_iter)) { 3102 soc_mem_field32_set(unit, L3_IPMCm, entry, 3103 EXT_Q_INTERNALf, 1); 3104 } 3105 } 3106 } 3107 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_EXTERNALf, 1); 3108 } 3109 BCM_IF_ERROR_RETURN(soc_mem_write(unit, L3_IPMCm, 3110 MEM_BLOCK_ALL, ipmc_id, &entry)); 3111 BCM_IF_ERROR_RETURN(_bcm_kt2_ipmc_subscriber_egress_queue_ext_set 3112 (unit, port, ipmc_id, ext_mem_enable)); 3113 } 3114 } 3115 soc_mem_unlock(unit, L3_IPMCm); 3116 #endif 3117 return BCM_E_NONE; 3118 } 3119 3120 #endif