port.c (24550B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: port.c 8 * Purpose: Port Management for MAVERICK 2 9 * 10 * The purpose is to set port management implementation specified 11 * to MAVERICK 2 in this file. 12 */ 13 14 #include <soc/defs.h> 15 16 #if defined(BCM_MAVERICK2_SUPPORT) 17 #include <soc/trident3.h> 18 #include <soc/maverick2.h> 19 #include <bcm_int/esw/tomahawk.h> 20 #include <bcm_int/esw/trident3.h> 21 #include <bcm_int/esw/maverick2.h> 22 23 #include <bcm_int/esw/xgs5.h> 24 #include <bcm_int/esw/portctrl.h> 25 26 #include <soc/flexport/maverick2/maverick2_flexport.h> 27 #include <soc/flexport/maverick2/maverick2_flexport_defines.h> 28 29 static bcmi_xgs5_dev_info_t *bcmi_mv2_dev_info[SOC_MAX_NUM_DEVICES]; 30 31 /* HW Definitions */ 32 static bcmi_xgs5_port_drv_t bcmi_mv2_port_drv; 33 34 /* 35 * Function: 36 * bcmi_mv2_port_dev_info_init 37 * Purpose: 38 * Initialize the device info. 39 * Parameters: 40 * unit - (IN) Unit number. 41 * Returns: 42 * BCM_E_xxx 43 * Notes: 44 */ 45 STATIC int 46 bcmi_mv2_port_dev_info_init(int unit) 47 { 48 bcmi_xgs5_dev_info_t *dev_info; 49 soc_info_t *si = &SOC_INFO(unit); 50 int alloc_size; 51 int pipe = 0, phy_port, blk, bindex; 52 int i, cntmaxsize; 53 54 /* Free bcmi_td3_dev_info[unit] if already allocated */ 55 if (bcmi_mv2_dev_info[unit]) { 56 sal_free(bcmi_mv2_dev_info[unit]); 57 bcmi_mv2_dev_info[unit] = NULL; 58 } 59 60 /* Allocate memory for main SW data structure */ 61 alloc_size = sizeof(bcmi_xgs5_dev_info_t) + 62 (sizeof(bcmi_xgs5_phy_port_t) * MAVERICK2_PHY_PORTS_PER_DEV); 63 dev_info = sal_alloc(alloc_size, "bcmi_mv2_dev_info"); 64 if (dev_info == NULL) { 65 return BCM_E_MEMORY; 66 } 67 sal_memset(dev_info, 0, alloc_size); 68 dev_info->phy_port_info = (bcmi_xgs5_phy_port_t *)&dev_info[1]; 69 bcmi_mv2_dev_info[unit] = dev_info; 70 71 /* Clear data structure */ 72 73 /* Device information init */ 74 dev_info = bcmi_mv2_dev_info[unit]; 75 dev_info->phy_ports_max = MAVERICK2_PHY_PORTS_PER_DEV + 1; 76 dev_info->mmu_lossless = 0; 77 dev_info->asf_prof_default = _SOC_ASF_MEM_PROFILE_SIMILAR; 78 dev_info->pipe_bound = 1; 79 /* First logical port in pipe */ 80 dev_info->pipe_log_port_base[pipe] = 0; 81 82 /* First physical port in pipe */ 83 dev_info->pipe_phy_port_base[pipe] = 0; 84 85 dev_info->ports_pipe_max[pipe] = MAVERICK2_PHY_PORTS_PER_PIPE; 86 87 /* 10G is the min speed in TDM calculations */ 88 dev_info->tdm_pipe_lr_bw_limit_checker_speed_min = SPEED_10G; 89 90 /* 10G is the min speed in TDM calendar program. 91 * TDM eventually sets minimum speed to 10G in TDM calendar. 92 */ 93 dev_info->tdm_speed_min = SPEED_1G; 94 95 cntmaxsize = soc_property_get(unit, spn_BCM_STAT_JUMBO, 1518); 96 if (cntmaxsize > si->max_mtu) { 97 cntmaxsize = si->max_mtu; 98 } 99 dev_info->cntmaxsize_xl = cntmaxsize; 100 dev_info->cntmaxsize_cl = cntmaxsize; 101 102 dev_info->restriction_mask = BCMI_XGS5_FLEXPORT_RESTRICTION_MIX_LR_OVS_DEV | 103 BCMI_XGS5_FLEXPORT_RESTRICTION_SPEED_CLASS | 104 BCMI_XGS5_FLEXPORT_RESTRICTION_PM_OVS_MIX_SISTER | 105 BCMI_XGS5_FLEXPORT_RESTRICTION_PM_SINGLE_PLL; 106 107 dev_info->encap_mask = BCM_PA_ENCAP_IEEE | BCM_PA_ENCAP_HIGIG2; 108 109 /* 110 * Restriction 13:No port configurations with more than 5 port speed 111 * classes are supported. 112 */ 113 dev_info->speed_class.speed_class_num = _MV2_TDM_SPEED_CLASS_MAX; 114 115 /* Restriction 15: Port configurations that contain both 20G and 25G port 116 * speeds are not supported 117 */ 118 dev_info->speed_class.no_mix_speed_mask = SOC_PA_SPEED_20GB | 119 SOC_PA_SPEED_25GB; 120 121 dev_info->port_ratio_mask = BCMI_XGS5_PORT_RATIO_SINGLE | 122 BCMI_XGS5_PORT_RATIO_DUAL_1_1 | 123 BCMI_XGS5_PORT_RATIO_DUAL_2_1 | 124 BCMI_XGS5_PORT_RATIO_DUAL_1_2 | 125 BCMI_XGS5_PORT_RATIO_TRI_023_2_1_1 | 126 BCMI_XGS5_PORT_RATIO_TRI_023_4_1_1 | 127 BCMI_XGS5_PORT_RATIO_TRI_012_1_1_2 | 128 BCMI_XGS5_PORT_RATIO_TRI_012_1_1_4 | 129 BCMI_XGS5_PORT_RATIO_QUAD; 130 131 dev_info->pipe_lr_bw = 2000000; 132 133 /* Set valid speeds for 1/2/4 Lanes */ 134 BCM_IF_ERROR_RETURN 135 (soc_td3_support_speeds(unit, 1, &dev_info->speed_valid[1])); 136 BCM_IF_ERROR_RETURN 137 (soc_td3_support_speeds(unit, 2, &dev_info->speed_valid[2])); 138 BCM_IF_ERROR_RETURN 139 (soc_td3_support_speeds(unit, 4, &dev_info->speed_valid[4])); 140 141 /* 142 * Set physical port info: 143 * - Port lane capability 144 * - Port is enabled for flexport 145 * - pipe 146 */ 147 for (phy_port = 0; phy_port < MAVERICK2_PHY_PORTS_PER_DEV; phy_port++) { 148 /* Set information to invalid */ 149 dev_info->phy_port_info[phy_port].pipe = -1; 150 } 151 152 /* Flexport is not supported for CPU/LB/MNG ports, so skip CPU/LB/MNG */ 153 for (phy_port = 1; phy_port < MAVERICK2_PHY_PORTS_PER_DEV; phy_port++) { 154 int lanes; 155 156 /* Check for end of port list */ 157 if (SOC_PORT_BLOCK(unit, phy_port) < 0 && 158 SOC_PORT_BINDEX(unit, phy_port) < 0) { 159 break; 160 } 161 /* Set pipe information */ 162 dev_info->phy_port_info[phy_port].pipe = 0; 163 164 for (i = 0; i < SOC_DRIVER(unit)->port_num_blktype; i++) { 165 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, i); 166 bindex = SOC_PORT_IDX_BINDEX(unit, phy_port, i); 167 168 if ((blk < 0) || (bindex < 0)) { 169 continue; 170 } 171 172 if (SOC_BLOCK_TYPE(unit, blk) == SOC_BLK_CLPORT) { 173 /* Set port lane capabilites */ 174 dev_info->phy_port_info[phy_port].lanes_valid = 175 BCMI_XGS5_PORT_LANES_1; 176 if (bindex == 0) { 177 dev_info->phy_port_info[phy_port].lanes_valid |= 178 BCMI_XGS5_PORT_LANES_2 | BCMI_XGS5_PORT_LANES_4; 179 } else if (bindex == 2) { 180 dev_info->phy_port_info[phy_port].lanes_valid |= 181 BCMI_XGS5_PORT_LANES_2; 182 } 183 184 if (SHR_BITGET(si->flexible_pm_bitmap,blk)) { 185 dev_info->phy_port_info[phy_port].flex = 1; 186 } 187 } 188 } /* for port_num_blktype */ 189 dev_info->phy_port_info[phy_port].max_lane_speed = 27000; 190 191 (void)soc_mv2_port_lanes_set(unit, phy_port, &lanes, 192 &dev_info->phy_port_info[phy_port].max_lane_speed); 193 if (dev_info->phy_port_info[phy_port].max_lane_speed == 11000) { 194 dev_info->phy_port_info[phy_port].lanes_valid = BCMI_XGS5_PORT_LANES_1; 195 } 196 } 197 198 /* Init condition */ 199 _bcmi_td3_init_condition_set(unit, dev_info); 200 201 return BCM_E_NONE; 202 } 203 204 /* 205 * Function: 206 * bcmi_mv2_port_soc_resource_init 207 * Purpose: 208 * Initialize SOC Port Structure. 209 * This includes: 210 * Copy Port information from BCM port resource array. 211 * Set correct pipe, MMU port, IDB port for new logical port. 212 * Parameters: 213 * unit - (IN) Unit number. 214 * nport - (IN) Number of elements in array resource. 215 * resource - (IN) BCM Port resource configuration array. 216 * soc_resource - (OUT) SOC Port resource array. 217 * Returns: 218 * BCM_E_xxx 219 * Notes: 220 */ 221 STATIC int 222 bcmi_mv2_port_soc_resource_init(int unit, int nport, 223 bcm_port_resource_t *resource, 224 soc_port_resource_t *soc_resource) 225 { 226 int i; 227 int logic_port, idb_port, phy_port; 228 229 /* 230 * SOC Port Structure initialization 231 */ 232 233 /* Clear data structure */ 234 sal_memset(soc_resource, 0, sizeof(soc_port_resource_t) * nport); 235 236 /* Copy initial information */ 237 for (i = 0; i < nport; i++) { 238 logic_port = resource[i].port; 239 phy_port = resource[i].physical_port; 240 idb_port = logic_port - 1; 241 242 if (logic_port > MAVERICK2_LOG_PORT_MNG0) { 243 /* Last valid logical port number */ 244 LOG_CLI((BSL_META_U(unit, 245 "Logical port %d: is not valid\n"), 246 logic_port)); 247 return BCM_E_CONFIG; 248 } 249 250 if ((phy_port > 1) && (phy_port <= 40) && (logic_port >= 33)) { 251 /* Half Pipe 0 */ 252 LOG_CLI((BSL_META_U(unit, 253 "Physical port %d: mapped to Half Pipe 1\n"), 254 phy_port)); 255 return BCM_E_CONFIG; 256 } else if ((phy_port >= 41) && (phy_port <= 80) && (logic_port <= 32)) { 257 /* Half Pipe 1 */ 258 LOG_CLI((BSL_META_U(unit, 259 "Physical port %d: mapped to Half Pipe 0\n"), 260 phy_port)); 261 return BCM_E_CONFIG; 262 } 263 264 soc_resource[i].flags = resource[i].flags; 265 soc_resource[i].logical_port = logic_port; 266 soc_resource[i].physical_port = resource[i].physical_port; 267 soc_resource[i].speed = resource[i].speed; 268 soc_resource[i].num_lanes = resource[i].lanes; 269 soc_resource[i].encap = resource[i].encap; 270 soc_resource[i].idb_port = idb_port; 271 soc_resource[i].mmu_port = idb_port; 272 /* MV2 does NOT support port configuration with a mix of line-rate ports 273 * and oversubscribed ports. */ 274 soc_resource[i].oversub = 1; 275 276 if (resource[i].speed >= 40000) { 277 soc_resource[i].hsp = 1; 278 } 279 } 280 281 return BCM_E_NONE; 282 } 283 284 /* Function: 285 * bcmi_mv2_port_resource_validate 286 * Purpose: 287 * Validate that the given FlexPort operations is valid. 288 * Parameters: 289 * unit - (IN) Unit number. 290 * port_schedule_state - (OUT) Port resource state. 291 * Returns: 292 * BCM_E_xxx 293 * Notes: 294 */ 295 STATIC int 296 bcmi_mv2_port_resource_validate(int unit, soc_port_schedule_state_t 297 *port_schedule_state) 298 { 299 int phy_port, logic_port; 300 int hpipe_bw[2] = {0}; 301 soc_port_map_type_t *post_pi = &port_schedule_state->out_port_map; 302 303 for (phy_port = 1; phy_port <= MAVERICK2_GPHY_PORTS_PER_PIPE; phy_port++) { 304 if (post_pi->port_p2l_mapping[phy_port] == -1) { 305 continue; 306 } 307 logic_port = post_pi->port_p2l_mapping[phy_port]; 308 hpipe_bw[(phy_port - 1) / 40] += MV2_TDM_SPEED_ADJUST(post_pi->log_port_speed[logic_port]); 309 } 310 if (hpipe_bw[0] > SOC_INFO(unit).io_bandwidth / 2) { 311 LOG_CLI((BSL_META_U(unit, 312 "Hpipe0 Bandwidth %dGb exceeds Max Hpipe Bandwidth %dGb\n"), 313 hpipe_bw[0] / 1000, (SOC_INFO(unit).io_bandwidth / 2) / 1000)); 314 return BCM_E_PARAM; 315 } 316 317 if (hpipe_bw[1] > SOC_INFO(unit).io_bandwidth / 2) { 318 LOG_CLI((BSL_META_U(unit, 319 "Hpipe1 Bandwidth %dGb exceeds Max Hpipe Bandwidth %dGb\n"), 320 hpipe_bw[1] / 1000, (SOC_INFO(unit).io_bandwidth / 2) / 1000)); 321 return BCM_E_PARAM; 322 } 323 324 for (phy_port = 1; phy_port <= MAVERICK2_GPHY_PORTS_PER_PIPE; phy_port += MAVERICK2_PORTS_PER_PBLK) { 325 if (post_pi->port_p2l_mapping[phy_port] == -1 && 326 (post_pi->port_p2l_mapping[phy_port + 1] != -1 || 327 post_pi->port_p2l_mapping[phy_port + 2] != -1 || 328 post_pi->port_p2l_mapping[phy_port + 3] != -1)) { 329 return BCM_E_PARAM; 330 } 331 } 332 333 return BCM_E_NONE; 334 } 335 336 /* 337 * Function: 338 * bcmi_mv2_pre_flexport_tdm 339 * Purpose: 340 * Pass TDM information pre FlexPort to DV FlexPort API 341 * Parameters: 342 * unit - (IN) Unit number. 343 * port_schedule_state - (OUT) Port resource state. 344 * Returns: 345 * BCM_E_xxx 346 * Notes: 347 */ 348 STATIC int 349 bcmi_mv2_pre_flexport_tdm(int unit, 350 soc_port_schedule_state_t *port_schedule_state) 351 { 352 port_schedule_state->is_flexport = 1; 353 354 BCM_IF_ERROR_RETURN 355 (soc_mv2_port_schedule_tdm_init(unit, port_schedule_state)); 356 return BCM_E_NONE; 357 } 358 359 /* 360 * Function: 361 * bcmi_mv2_post_flexport_tdm 362 * Purpose: 363 * Update TDM information in SOC with post FlexPort TDM state return from 364 * DV FlexPort API. 365 * Parameters: 366 * unit - (IN) Unit number. 367 * port_schedule_state - (IN) Port resource state. 368 * Returns: 369 * BCM_E_xxx 370 * Notes: 371 */ 372 STATIC int 373 bcmi_mv2_post_flexport_tdm(int unit, 374 soc_port_schedule_state_t *port_schedule_state) 375 { 376 BCM_IF_ERROR_RETURN 377 (soc_mv2_soc_tdm_update(unit, port_schedule_state)); 378 return BCM_E_NONE; 379 } 380 381 /* 382 * Function: 383 * bcmi_mv2_port_enable 384 * Purpose: 385 * Enable port. 386 * Parameters: 387 * unit - (IN) Unit number. 388 * port_schedule_state - (IN) Port resource state. 389 * Returns: 390 * BCM_E_xxx 391 * Notes: 392 * This function should only be called with PORTMOD enabled 393 */ 394 STATIC int 395 bcmi_mv2_port_enable(int unit, soc_port_schedule_state_t *port_schedule_state) 396 { 397 int i, nport, rv = BCM_E_NONE; 398 bcm_port_t *port; 399 400 nport = port_schedule_state->nport; 401 402 port = sal_alloc(nport * sizeof(bcm_port_t), "port array"); 403 if (port == NULL) { 404 return BCM_E_MEMORY; 405 } 406 for (i = 0; i < nport; i++) { 407 port[i] = port_schedule_state->resource[i].logical_port; 408 } 409 410 rv = soc_maverick2_flex_mmu_port_up(unit, port_schedule_state); 411 if (BCM_SUCCESS(rv)) { 412 rv = soc_maverick2_flex_ep_port_up(unit, port_schedule_state); 413 } 414 if (BCM_SUCCESS(rv)) { 415 rv = soc_maverick2_flex_idb_port_up(unit, port_schedule_state); 416 } 417 if (BCM_SUCCESS(rv)) { 418 rv = bcmi_esw_portctrl_mac_up(unit, nport, port); 419 } 420 sal_free(port); 421 return rv; 422 } 423 424 /* 425 * Function: 426 * bcmi_mv2_port_disable 427 * Purpose: 428 * Disable port. 429 * Parameters: 430 * unit - (IN) Unit number. 431 * port_schedule_state - (IN) Port resource state. 432 * Returns: 433 * BCM_E_xxx 434 * Notes: 435 * This function should only be called with PORTMOD enabled 436 */ 437 STATIC int 438 bcmi_mv2_port_disable(int unit, soc_port_schedule_state_t *port_schedule_state) 439 { 440 int i, nport, rv = BCM_E_NONE; 441 bcm_port_t *port; 442 443 nport = port_schedule_state->nport; 444 445 port = sal_alloc(nport * sizeof(bcm_port_t), "port array"); 446 if (port == NULL) { 447 return BCM_E_MEMORY; 448 } 449 for (i = 0; i < nport; i++) { 450 port[i] = port_schedule_state->resource[i].logical_port; 451 } 452 rv = bcmi_esw_portctrl_mac_rx_down(unit, nport, port); 453 if (BCM_SUCCESS(rv)) { 454 rv = soc_maverick2_flex_idb_port_down(unit, port_schedule_state); 455 } 456 if (BCM_SUCCESS(rv)) { 457 rv = soc_maverick2_flex_mmu_port_down(unit, port_schedule_state); 458 } 459 if (BCM_SUCCESS(rv)) { 460 rv = soc_maverick2_flex_ep_port_down(unit, port_schedule_state); 461 } 462 if (BCM_SUCCESS(rv)) { 463 rv = bcmi_esw_portctrl_mac_tx_down(unit, nport, port); 464 } 465 466 sal_free(port); 467 468 return rv; 469 } 470 471 /* 472 * Function: 473 * bcmi_mv2_port_speed_1g_update 474 * Purpose: 475 * Special operations for 1G speed. 476 * Parameters: 477 * unit - (IN) Unit number. 478 * port - (IN) Logical port number. 479 * speed - (IN) port speed (Mbps). 480 * Returns: 481 * BCM_E_xxx 482 * Notes: 483 * In the PRD, nothing below 10G is officially supported. 484 * We enable customers with limited 1G support in Maverick 2. 485 * 1G is not a support speed class in TDM calculation, thus treated same as 486 * 10G in TDM calculation. 1G port does NOT support cut through, flow 487 * control. 488 */ 489 int 490 bcmi_mv2_port_speed_1g_update(int unit, bcm_port_t port, int speed) 491 { 492 if (speed != SPEED_1G) { 493 return BCM_E_NONE; 494 } 495 496 /* Update port speed info in soc_info */ 497 SOC_INFO(unit).port_init_speed[port] = speed; 498 499 /* Set asf mode to SAF */ 500 if (soc_feature(unit, soc_feature_asf_multimode)) { 501 BCM_IF_ERROR_RETURN 502 (soc_mv2_port_asf_mode_set(unit, port, speed, 503 _SOC_TD3_ASF_MODE_SAF)); 504 } 505 506 /* Disable Pause */ 507 BCM_IF_ERROR_RETURN 508 (bcm_esw_port_pause_set(unit, port, 0, 0)); 509 510 /* Disable PFC */ 511 if (soc_feature(unit, soc_feature_priority_flow_control)) { 512 BCM_IF_ERROR_RETURN 513 (bcm_esw_port_control_set(unit, port, 514 bcmPortControlPFCReceive, 0)); 515 BCM_IF_ERROR_RETURN 516 (bcm_esw_port_control_set(unit, port, 517 bcmPortControlPFCTransmit, 0)); 518 } 519 520 return BCM_E_NONE; 521 } 522 523 STATIC int 524 bcmi_mv2_port_attach_mmu(int unit, int port) 525 { 526 if (IS_CPU_PORT(unit, port) || IS_LB_PORT(unit, port) || 527 IS_MANAGEMENT_PORT(unit, port)) { 528 return BCM_E_PARAM; 529 } 530 531 /* Assign the base queues and number of queues for the specified port. */ 532 BCM_IF_ERROR_RETURN 533 (soc_maverick2_num_cosq_init_port(unit, port)); 534 535 /* Enable enqueing packets to the port */ 536 SOC_IF_ERROR_RETURN( 537 soc_td3_port_mmu_tx_enable_set(unit, port, 1)); 538 SOC_IF_ERROR_RETURN( 539 soc_td3_port_mmu_rx_enable_set(unit, port, 1)); 540 541 /* Reconfigure THDI, THDO settings */ 542 BCM_IF_ERROR_RETURN 543 (soc_mv2_mmu_config_init_port(unit, port)); 544 545 return BCM_E_NONE; 546 } 547 548 /* 549 * Function: 550 * bcmi_mv2_port_detach_asf 551 * Purpose: 552 * Update ASF when port deleted during Flexport operations. 553 * Parameters: 554 * unit - (IN) Unit number. 555 * port - (IN) Logical port number. 556 * Returns: 557 * BCM_E_xxx 558 * Notes: 559 */ 560 STATIC int 561 bcmi_mv2_port_detach_asf(int unit, bcm_port_t port) 562 { 563 BCM_IF_ERROR_RETURN 564 (soc_mv2_port_asf_detach(unit, port)); 565 566 return BCM_E_NONE; 567 } 568 569 570 /* 571 * Function Vectors 572 */ 573 574 static bcm_esw_port_drv_t bcm_mv2_port_drv = { 575 /* fn_drv_init */ bcmi_mv2_port_fn_drv_init, 576 /* resource_set */ bcmi_xgs5_port_resource_set, 577 /* resource_get */ bcmi_xgs5_port_resource_get, 578 /* resource_multi_set */ bcmi_xgs5_port_resource_multi_set, 579 /* resource_speed_set */ bcmi_xgs5_port_speed_set, 580 /* resource_traverse */ bcmi_xgs5_port_resource_traverse, 581 /* port_redirect_set */ NULL, 582 /* port_redirect_get */ NULL, 583 /* port_enable_set */ bcmi_xgs5_port_enable_set, 584 /* encap_speed_check */ bcmi_xgs5_port_encap_speed_check, 585 /* force_lb_set */ NULL, 586 /* force_lb_check */ NULL, 587 /* resource_status_update */ bcmi_xgs5_port_resource_status_update, 588 /* port_resource_speed_multi_set */ bcmi_xgs5_port_resource_speed_multi_set, 589 /* device_speed_check */ NULL, 590 }; 591 592 /* Device programming routines */ 593 static bcmi_xgs5_port_func_t bcmi_mv2_port_calls = { 594 /* reconfigure_ports */ soc_maverick2_reconfigure_ports, 595 /* soc_resource_init */ bcmi_mv2_port_soc_resource_init, 596 /* port_resource_validate */ bcmi_mv2_port_resource_validate, 597 /* pre_flexport_tdm */ bcmi_mv2_pre_flexport_tdm, 598 /* post_flexport_tdm */ bcmi_mv2_post_flexport_tdm, 599 /* port_macro_update */ bcmi_td3_clport_update, 600 /* port_enable */ bcmi_mv2_port_enable, 601 /* port_disable */ bcmi_mv2_port_disable, 602 /* no_tdm_speed_update */ bcmi_mv2_port_speed_1g_update, 603 /* speed_ability_get */ bcmi_td3_speed_ability_get, 604 /* speed_mix_validate */ bcmi_td3_speed_mix_validate, 605 /* cos_map_update */ bcmi_td3_port_cosmap_update, 606 }; 607 608 static 609 int (*mv2_port_attach_exec[PORT_ATTACH_EXEC__MAX])(int unit, bcm_port_t port) = { 610 /* MMU config init */ 611 &bcmi_mv2_port_attach_mmu, 612 613 /* PORT module (bcm_esw_port_init) */ 614 &bcmi_xgs5_port_attach_dscp, 615 &bcmi_xgs5_port_attach_software, 616 &bcmi_xgs5_port_attach_egr_vlan_action, 617 &bcmi_xgs5_port_cfg_init, 618 &bcmi_xgs5_port_attach_port_probe, 619 &bcmi_xgs5_port_attach_frame_length_check, 620 &bcmi_xgs5_port_attach_rcpu_mtu, 621 &bcmi_xgs5_port_attach_outer_tpid, 622 &bcmi_xgs5_port_egr_block_profile_init, 623 &bcmi_xgs5_port_attach_vlan_protocol, 624 &bcmi_xgs5_port_attach_eee, 625 &bcmi_xgs5_port_attach_higig, 626 &bcmi_xgs5_port_attach_port_info_cfg, 627 &bcmi_xgs5_port_attach_egr_link_delay, 628 629 /* Other modules related to port */ 630 &bcmi_xgs5_port_attach_stg, 631 &bcmi_xgs5_port_attach_vlan, 632 &bcmi_xgs5_port_attach_trunk, 633 &bcm_td3_cosq_port_attach, 634 &bcmi_xgs5_port_attach_linkscan, 635 &bcmi_xgs5_port_attach_stat, 636 &bcmi_td3_port_attach_stack, 637 &bcmi_xgs5_port_attach_rate, 638 &bcmi_xgs5_port_attach_field, 639 &bcmi_xgs5_port_attach_mirror, 640 &bcmi_td3_port_attach_l3, 641 &bcmi_xgs5_port_attach_ipmc, 642 #if defined(INCLUDE_L3) 643 &bcm_th_ipmc_repl_port_attach, 644 #else 645 NULL, 646 #endif 647 &bcmi_xgs5_port_attach_mpls, 648 &bcmi_xgs5_port_attach_mim, 649 }; 650 651 static 652 int (*mv2_port_detach_exec[PORT_DETACH_EXEC__MAX])(int unit, bcm_port_t port) = { 653 /* Other modules related to port */ 654 #if defined(INCLUDE_L3) 655 &bcm_th_ipmc_repl_port_detach, 656 #else 657 NULL, 658 #endif 659 &bcmi_xgs5_port_detach_ipmc, 660 &bcmi_xgs5_port_detach_mpls, 661 &bcmi_xgs5_port_detach_mim, 662 &bcmi_td3_port_detach_l3, 663 &bcmi_xgs5_port_detach_mirror, 664 &bcmi_xgs5_port_detach_field, 665 &bcmi_xgs5_port_detach_rate, 666 &bcmi_td3_port_detach_stack, 667 &bcm_td3_cosq_port_detach, 668 &bcmi_xgs5_port_detach_trunk, 669 &bcmi_xgs5_port_detach_vlan, 670 &bcmi_xgs5_port_detach_stg, 671 672 /* PORT module (_bcm_esw_port_deinit) */ 673 &bcmi_mv2_port_detach_asf, 674 &bcmi_xgs5_port_detach_egr_link_delay, 675 &bcmi_xgs5_port_detach_higig, 676 &bcmi_xgs5_port_detach_eee, 677 &bcmi_xgs5_port_detach_vlan_protocol, 678 &bcmi_xgs5_port_egr_block_profile_init, 679 &bcmi_xgs5_port_detach_phy, 680 &bcmi_xgs5_port_detach_dscp, 681 &bcmi_xgs5_port_cfg_init, 682 &bcmi_xgs5_port_detach_egr_vlan_action, 683 &bcmi_xgs5_port_detach_software, 684 }; 685 686 /* 687 * Function: 688 * bcmi_mv2_port_fn_drv_init 689 * Purpose: 690 * Initialize the Port function driver. 691 * Parameters: 692 * unit - (IN) Unit number. 693 * Returns: 694 * BCM_E_xxx 695 * Notes: 696 */ 697 int 698 bcmi_mv2_port_fn_drv_init(int unit) 699 { 700 int phase_pos, present; 701 702 BCM_IF_ERROR_RETURN 703 (bcmi_mv2_port_dev_info_init(unit)); 704 705 /* BCMI Driver init */ 706 bcmi_mv2_port_drv.port_calls = &bcmi_mv2_port_calls; 707 bcmi_mv2_port_drv.dev_info[unit] = bcmi_mv2_dev_info[unit]; 708 709 710 sal_memcpy(bcmi_mv2_port_drv.port_calls->port_attach_exec, 711 mv2_port_attach_exec, 712 sizeof(bcmi_mv2_port_drv.port_calls->port_attach_exec)); 713 714 sal_memcpy(bcmi_mv2_port_drv.port_calls->port_detach_exec, 715 mv2_port_detach_exec, 716 sizeof(bcmi_mv2_port_drv.port_calls->port_detach_exec)); 717 718 /* Initialize Common XGS5 Port module */ 719 BCM_IF_ERROR_RETURN 720 (bcmi_xgs5_port_fn_drv_init(unit, 721 &bcm_mv2_port_drv, 722 &bcmi_mv2_port_drv, 723 NULL)); 724 725 726 BCM_IF_ERROR_RETURN(soc_check_flex_phase(unit, mv2_flexport_phases, 727 soc_maverick2_flex_top_port_down, 728 &present)); 729 /* Detach port enable/disable in DV Flexport */ 730 if (present) { 731 BCM_IF_ERROR_RETURN 732 (soc_detach_flex_phase(unit, mv2_flexport_phases, 733 soc_maverick2_flex_top_port_down, 734 &phase_pos)); 735 } 736 BCM_IF_ERROR_RETURN(soc_check_flex_phase(unit, mv2_flexport_phases, 737 soc_maverick2_flex_top_port_up, 738 &present)); 739 if (present) { 740 BCM_IF_ERROR_RETURN 741 (soc_detach_flex_phase(unit, mv2_flexport_phases, 742 soc_maverick2_flex_top_port_up, 743 &phase_pos)); 744 } 745 746 return BCM_E_NONE; 747 } 748 749 #else /* BCM_MAVERICK2_SUPPORT */ 750 int _mv2_port_not_empty; 751 752 #endif /* BCM_MAVERICK2_SUPPORT */