port.c (25464B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 10 #include <soc/defs.h> 11 #include <soc/debug.h> 12 #include <soc/drv.h> 13 14 #include <sal/core/time.h> 15 #include <shared/bsl.h> 16 #include <bcm/port.h> 17 #include <bcm/tx.h> 18 #include <bcm/error.h> 19 20 #include <soc/katana.h> 21 #include <bcm_int/esw_dispatch.h> 22 #include <bcm_int/esw/katana.h> 23 24 #if defined(BCM_KATANA_SUPPORT) 25 26 27 #define BCM_KT_MAX_BURST_VALUE 16711 28 29 /* 30 * Function: 31 * bcm_kt_port_rate_egress_set 32 * Purpose: 33 * Set egress rate limiting parameters for the Katana chip. 34 * Parameters: 35 * unit - (IN)SOC unit number 36 * port - (IN)Port number 37 * kbits_sec - (IN)Rate in kilobits (1000 bits) per second. 38 * Rate of 0 disables rate limiting. 39 * kbits_burst -(IN)Maximum burst size in kilobits (1000 bits). 40 * Returns: 41 * BCM_E_XXX 42 */ 43 int 44 _bcm_kt_port_rate_egress_set(int unit, bcm_port_t port, 45 uint32 kbits_sec, uint32 kbits_burst) 46 { 47 int rv = BCM_E_NONE; 48 uint32 rate_exp, rate_mantissa; 49 uint32 burst_exp, burst_mantissa; 50 uint32 cycle_sel = 0; 51 uint32 temp_burst_exp, temp_burst_mantissa; 52 lls_port_shaper_config_c_entry_t port_entry; 53 lls_port_shaper_config_c_entry_t port_null_entry; 54 lls_port_shaper_bucket_c_entry_t port_bucket_entry; 55 56 soc_field_t rate_exp_f = C_MAX_REF_RATE_EXPf; 57 soc_field_t rate_mant_f = C_MAX_REF_RATE_MANTf; 58 soc_field_t burst_exp_f = C_MAX_THLD_EXPf; 59 soc_field_t burst_mant_f = C_MAX_THLD_MANTf; 60 soc_field_t cycle_sel_f = C_MAX_CYCLE_SELf; 61 62 if (kbits_burst > BCM_KT_MAX_BURST_VALUE) { 63 LOG_ERROR(BSL_LS_SOC_COMMON, 64 (BSL_META_U(unit, 65 "Invalid Burst value %d\n"), kbits_burst)); 66 return BCM_E_PARAM; 67 } 68 69 /* compute exp and mantissa and program the registers */ 70 rv = soc_katana_get_shaper_rate_info(unit, kbits_sec, 71 &rate_mantissa, &rate_exp); 72 if (BCM_FAILURE(rv)) { 73 return(rv); 74 } 75 76 rv = soc_katana_get_shaper_burst_info(unit, kbits_burst, 77 &burst_mantissa, &burst_exp, 0); 78 if (BCM_FAILURE(rv)) { 79 return(rv); 80 } 81 82 /* compute recommended minimum burst and cycle_sel */ 83 if (rate_exp < 10) { 84 temp_burst_exp = 5; 85 temp_burst_mantissa = 0; 86 } else { 87 temp_burst_exp = rate_exp - 4; 88 temp_burst_mantissa = (rate_mantissa >> 3); 89 } 90 91 if (rate_exp > 4) { 92 cycle_sel = 0; 93 } else if (rate_exp > 1) { 94 cycle_sel = 5 - rate_exp; 95 } else { 96 cycle_sel = 4; 97 } 98 99 if (burst_exp < temp_burst_exp) { 100 burst_exp = temp_burst_exp; 101 burst_mantissa = temp_burst_mantissa; 102 } else { 103 if ((burst_exp == temp_burst_exp) && 104 (burst_mantissa == temp_burst_mantissa)) { 105 burst_exp = temp_burst_exp; 106 burst_mantissa = temp_burst_mantissa; 107 } else if ((burst_exp >= 14) && 108 (burst_mantissa >= 127)) { 109 /* maximum supported is 2064384 byte */ 110 burst_exp = 14; 111 burst_mantissa = 127; 112 cycle_sel = 9; 113 } else { 114 rv = soc_katana_compute_refresh_rate(unit, rate_exp, 115 rate_mantissa, burst_exp, burst_mantissa, 116 &cycle_sel); 117 if (BCM_FAILURE(rv)) { 118 return(rv); 119 } 120 } 121 } 122 123 rv = soc_katana_compute_burst_rate_check(unit, rate_exp, 124 rate_mantissa, burst_exp, burst_mantissa, 125 cycle_sel); 126 if (BCM_FAILURE(rv)) { 127 LOG_ERROR(BSL_LS_SOC_COMMON, 128 (BSL_META_U(unit, 129 "Burst value %d is not supported for given rate %d\n"), 130 kbits_burst, kbits_sec)); 131 return BCM_E_PARAM; 132 } 133 134 SOC_EGRESS_METERING_LOCK(unit); 135 rv = soc_mem_read(unit, LLS_PORT_SHAPER_CONFIG_Cm, MEM_BLOCK_ALL, 136 port, &port_entry); 137 if (BCM_FAILURE(rv)) { 138 SOC_EGRESS_METERING_UNLOCK(unit); 139 return rv; 140 } 141 soc_mem_field32_set(unit, LLS_PORT_SHAPER_CONFIG_Cm, &port_entry, 142 rate_exp_f, rate_exp); 143 soc_mem_field32_set(unit, LLS_PORT_SHAPER_CONFIG_Cm, &port_entry, 144 rate_mant_f, rate_mantissa); 145 soc_mem_field32_set(unit, LLS_PORT_SHAPER_CONFIG_Cm, &port_entry, 146 burst_exp_f, burst_exp); 147 soc_mem_field32_set(unit, LLS_PORT_SHAPER_CONFIG_Cm, &port_entry, 148 burst_mant_f, burst_mantissa); 149 soc_mem_field32_set(unit, LLS_PORT_SHAPER_CONFIG_Cm, &port_entry, 150 cycle_sel_f, cycle_sel); 151 if (soc_feature(unit, soc_feature_dynamic_shaper_update)) { 152 sal_memset(&port_null_entry, 0, sizeof(lls_port_shaper_config_c_entry_t)); 153 sal_memset(&port_bucket_entry, 0, sizeof(lls_port_shaper_bucket_c_entry_t)); 154 rv = soc_mem_write(unit, LLS_PORT_SHAPER_CONFIG_Cm, 155 MEM_BLOCK_ALL, port, &port_null_entry); 156 if (BCM_FAILURE(rv)) { 157 SOC_EGRESS_METERING_UNLOCK(unit); 158 return rv; 159 } 160 soc_mem_field32_set(unit, LLS_PORT_SHAPER_BUCKET_Cm, &port_bucket_entry, 161 NOT_ACTIVE_IN_LLSf, 1); 162 rv = soc_mem_write(unit, LLS_PORT_SHAPER_BUCKET_Cm, 163 MEM_BLOCK_ALL, port, &port_bucket_entry); 164 if (BCM_FAILURE(rv)) { 165 SOC_EGRESS_METERING_UNLOCK(unit); 166 return rv; 167 } 168 } 169 rv = soc_mem_write(unit, LLS_PORT_SHAPER_CONFIG_Cm, 170 MEM_BLOCK_ALL, port, &port_entry); 171 if (BCM_FAILURE(rv)) { 172 SOC_EGRESS_METERING_UNLOCK(unit); 173 return rv; 174 } 175 176 SOC_EGRESS_METERING_UNLOCK(unit); 177 return BCM_E_NONE; 178 } 179 180 /* 181 * Function: 182 * bcm_kt_port_rate_egress_get 183 * Purpose: 184 * Get egress rate limiting parameters for the Katana chip. 185 * Parameters: 186 * unit - (IN)SOC unit number 187 * port - (IN)Port number 188 * kbits_sec - (OUT)Rate in kilobits (1000 bits) per second. 189 * Rate of 0 disables rate limiting. 190 * kbits_burst -(OUT)Maximum burst size in kilobits (1000 bits). 191 * Returns: 192 * BCM_E_XXX 193 */ 194 int 195 _bcm_kt_port_rate_egress_get(int unit, bcm_port_t port, 196 uint32 *kbits_sec, uint32 *kbits_burst) 197 { 198 int rv = BCM_E_NONE; 199 uint32 rate_exp, rate_mantissa; 200 uint32 burst_exp, burst_mantissa; 201 lls_port_shaper_config_c_entry_t port_entry; 202 203 soc_field_t rate_exp_f = C_MAX_REF_RATE_EXPf; 204 soc_field_t rate_mant_f = C_MAX_REF_RATE_MANTf; 205 soc_field_t burst_exp_f = C_MAX_THLD_EXPf; 206 soc_field_t burst_mant_f = C_MAX_THLD_MANTf; 207 208 /* Input parameters check. */ 209 if (!kbits_sec || !kbits_burst) { 210 return (BCM_E_PARAM); 211 } 212 SOC_EGRESS_METERING_LOCK(unit); 213 rv = soc_mem_read(unit, LLS_PORT_SHAPER_CONFIG_Cm, MEM_BLOCK_ALL, 214 port, &port_entry); 215 SOC_EGRESS_METERING_UNLOCK(unit); 216 if (BCM_FAILURE(rv)) { 217 return(rv); 218 } 219 220 rate_exp = soc_mem_field32_get(unit, LLS_PORT_SHAPER_CONFIG_Cm, 221 &port_entry, rate_exp_f); 222 rate_mantissa = soc_mem_field32_get(unit, LLS_PORT_SHAPER_CONFIG_Cm, 223 &port_entry, rate_mant_f); 224 burst_exp = soc_mem_field32_get(unit, LLS_PORT_SHAPER_CONFIG_Cm, 225 &port_entry, burst_exp_f); 226 burst_mantissa = soc_mem_field32_get(unit, LLS_PORT_SHAPER_CONFIG_Cm, 227 &port_entry, burst_mant_f); 228 229 /* convert exp and mantissa to bps */ 230 rv = soc_katana_compute_shaper_rate(unit, rate_mantissa, rate_exp, 231 kbits_sec); 232 if (BCM_FAILURE(rv)) { 233 return(rv); 234 } 235 236 rv = soc_katana_compute_shaper_burst(unit, burst_mantissa, burst_exp, 237 kbits_burst); 238 if (BCM_FAILURE(rv)) { 239 return(rv); 240 } 241 242 243 return BCM_E_NONE; 244 245 } 246 247 /* 248 * Function: 249 * bcm_kt_port_rate_egress_set 250 * Purpose: 251 * Set egress rate limiting parameters for the Katana chip. 252 * Parameters: 253 * unit - (IN)SOC unit number 254 * port - (IN)Port number 255 * kbits_sec - (IN)Rate in kilobits (1000 bits) per second. 256 * Rate of 0 disables rate limiting. 257 * kbits_burst -(IN)Maximum burst size in kilobits (1000 bits). 258 * Returns: 259 * BCM_E_XXX 260 */ 261 int 262 bcm_kt_port_rate_egress_set(int unit, bcm_port_t port, 263 uint32 kbits_sec, uint32 kbits_burst, uint32 mode) 264 { 265 if (mode == _BCM_PORT_RATE_PPS_MODE) { 266 return bcm_kt_port_pps_rate_egress_set(unit, port, kbits_sec, kbits_burst); 267 } else { 268 return _bcm_kt_port_rate_egress_set(unit, port, kbits_sec, kbits_burst); 269 } 270 } 271 272 /* 273 * Function: 274 * bcm_kt_port_rate_egress_get 275 * Purpose: 276 * Get egress rate limiting parameters for the Katana chip. 277 * Parameters: 278 * unit - (IN)SOC unit number 279 * port - (IN)Port number 280 * kbits_sec - (OUT)Rate in kilobits (1000 bits) per second. 281 * Rate of 0 disables rate limiting. 282 * kbits_burst -(OUT)Maximum burst size in kilobits (1000 bits). 283 * Returns: 284 * BCM_E_XXX 285 */ 286 int 287 bcm_kt_port_rate_egress_get(int unit, bcm_port_t port, 288 uint32 *kbits_sec, uint32 *kbits_burst, uint32 *mode) 289 { 290 return _bcm_kt_port_rate_egress_get(unit, port, kbits_sec, kbits_burst); 291 } 292 293 /* 294 * Function: 295 * bcm_kt_port_pps_rate_egress_set 296 * Purpose: 297 * Set egress rate limiting parameters for the Katana chip. 298 * Parameters: 299 * unit - (IN)SOC unit number 300 * port - (IN)Port number 301 * pps - (IN)Rate in packets per second 302 * Rate of 0 disables rate limiting. 303 * burst -(IN)Maximum burst size in kilobits (1000 bits). 304 * Returns: 305 * BCM_E_XXX 306 */ 307 int 308 bcm_kt_port_pps_rate_egress_set(int unit, bcm_port_t port, 309 uint32 pps, uint32 burst) 310 { 311 lls_port_config_entry_t port_cfg; 312 int packet_mode, new_mode; 313 314 SOC_IF_ERROR_RETURN 315 (READ_LLS_PORT_CONFIGm(unit, MEM_BLOCK_ALL, port, &port_cfg)); 316 packet_mode = soc_mem_field32_get(unit, LLS_PORT_CONFIGm, &port_cfg, 317 PACKET_MODE_WRR_ACCOUNTING_ENABLEf); 318 if (pps == 0) { 319 /* Packet mode shaper is being cleared */ 320 new_mode = 0; 321 } else { 322 /* Packet mode shaper is being enabled */ 323 new_mode = 1; 324 } 325 if (packet_mode != new_mode) { 326 soc_mem_field32_set(unit, LLS_PORT_CONFIGm, &port_cfg, 327 PACKET_MODE_WRR_ACCOUNTING_ENABLEf, new_mode); 328 soc_mem_field32_set(unit, LLS_PORT_CONFIGm, &port_cfg, 329 PACKET_MODE_SHAPER_ACCOUNTING_ENABLEf, new_mode); 330 SOC_IF_ERROR_RETURN 331 (WRITE_LLS_PORT_CONFIGm(unit, MEM_BLOCK_ALL, port, &port_cfg)); 332 } 333 334 return _bcm_kt_port_rate_egress_set(unit, port, pps, burst); 335 } 336 337 int 338 _bcm_kt_port_downsizer_check_port(int unit, int port, bcm_pkt_t *pkt) { 339 int i,rv; 340 int enable; 341 uint64 tpok, rfcs, rpok; 342 uint32 entry[SOC_MAX_MEM_WORDS]; 343 344 SOC_IF_ERROR_RETURN(READ_ING_EGRMSKBMAPm(unit, MEM_BLOCK_ANY, port,entry)); 345 soc_mem_field32_set(unit, ING_EGRMSKBMAPm, entry, BITMAP_W0f, 0xffffffff); 346 soc_mem_field32_set(unit, ING_EGRMSKBMAPm, entry, BITMAP_W1f, 0x7f); 347 SOC_IF_ERROR_RETURN(WRITE_ING_EGRMSKBMAPm(unit, MEM_BLOCK_ANY, port, entry)); 348 349 /* Setup */ 350 rv = bcm_esw_port_enable_get(unit, port, &enable); 351 if(!enable) { 352 #ifdef BCM_PORT_DEFAULT_DISABLE 353 if (bcm_esw_port_enable_set(unit, port, TRUE) < 0) { 354 LOG_ERROR(BSL_LS_BCM_PORT, 355 (BSL_META_U(unit, 356 "Port %d could not be enabled\n"), port)); 357 } 358 #endif 359 } 360 if (bcm_esw_port_loopback_set(unit, port, BCM_PORT_LOOPBACK_PHY) < 0) { 361 LOG_ERROR(BSL_LS_BCM_PORT, 362 (BSL_META_U(unit, 363 "Port %d LoopBack Set Failed\n"), port)); 364 } 365 /* Send Packets */ 366 for (i = 0; i < 10; i++) { 367 BCM_PBMP_CLEAR(pkt->tx_pbmp); 368 BCM_PBMP_PORT_ADD(pkt->tx_pbmp, port); 369 rv = bcm_esw_tx(unit, pkt, NULL); 370 if (rv < 0) { 371 LOG_ERROR(BSL_LS_BCM_PORT, 372 (BSL_META_U(unit, 373 "Tx Error %d\n"), rv)); 374 return BCM_E_FAIL; 375 } 376 sal_udelay(SAL_BOOT_SIMULATION ? 100000 : 100); 377 } 378 sal_udelay(SAL_BOOT_SIMULATION ? 1000000 : 10000); 379 /* Verify Counters */ 380 SOC_IF_ERROR_RETURN(READ_TPOKr(unit, port, &tpok)); 381 SOC_IF_ERROR_RETURN(READ_RFCSr(unit, port, &rfcs)); 382 SOC_IF_ERROR_RETURN(READ_RPOKr(unit, port, &rpok)); 383 if ((COMPILER_64_HI(tpok) != 0) || (COMPILER_64_LO(tpok) != 10) || 384 (COMPILER_64_HI(rpok) != 0) || (COMPILER_64_LO(rpok) != 10) || 385 (COMPILER_64_HI(rfcs) != 0) || (COMPILER_64_LO(rfcs) != 0) ) { 386 LOG_VERBOSE(BSL_LS_SOC_COMMON, 387 (BSL_META_U(unit, 388 "Port %d Stat Mismatch\n"), port)); 389 rv = BCM_E_FAIL; 390 } else { 391 rv = BCM_E_NONE; 392 } 393 /* Cleanup */ 394 soc_mem_field32_set(unit, ING_EGRMSKBMAPm, entry, BITMAP_W0f, 0); 395 soc_mem_field32_set(unit, ING_EGRMSKBMAPm, entry, BITMAP_W1f, 0); 396 SOC_IF_ERROR_RETURN(WRITE_ING_EGRMSKBMAPm(unit, MEM_BLOCK_ANY, port, entry)); 397 if (bcm_esw_l2_addr_delete_by_port(unit, -1, port, 0) < 0) { 398 LOG_ERROR(BSL_LS_BCM_PORT, 399 (BSL_META_U(unit, 400 "Port %d L2 entry delete Failed\n"), port)); 401 } 402 if (bcm_esw_port_loopback_set(unit, port, BCM_PORT_LOOPBACK_NONE) < 0) { 403 LOG_ERROR(BSL_LS_BCM_PORT, 404 (BSL_META_U(unit, 405 "Port %d LoopBack Set Failed\n"), port)); 406 } 407 if(!enable) { 408 #ifdef BCM_PORT_DEFAULT_DISABLE 409 if (bcm_esw_port_enable_set(unit, port, FALSE) < 0) { 410 LOG_ERROR(BSL_LS_BCM_PORT, 411 (BSL_META_U(unit, 412 "Port %d could not be disabled\n"), port)); 413 } 414 415 #endif 416 } 417 if (bcm_esw_stat_clear(unit, port) < 0) { 418 LOG_ERROR(BSL_LS_BCM_PORT, 419 (BSL_META_U(unit, 420 "Port %d Stat Clear Failed\n"), port)); 421 } 422 return rv; 423 } 424 425 int _bcm_kt_port_downsizer_blk_reinit(int unit, int blk_num, int blk_port, bcm_pbmp_t blk_pbmp, int hotswap) 426 { 427 uint32 rval, en_bkp, xctrl_bkp, xcfg; 428 uint64 ctrl_bkp; 429 int rv, port_enable; 430 bcm_port_t port; 431 pbmp_t okay_ports; 432 soc_field_t hs_rst_fld[4] = {TOP_MXQ0_HOTSWAP_RST_Lf, TOP_MXQ1_HOTSWAP_RST_Lf, 433 TOP_MXQ2_HOTSWAP_RST_Lf, TOP_MXQ3_HOTSWAP_RST_Lf}; 434 soc_field_t rst_fld[4] = {TOP_MXQ0_RST_Lf, TOP_MXQ1_RST_Lf, 435 TOP_MXQ2_RST_Lf, TOP_MXQ3_RST_Lf}; 436 437 if (hotswap) { 438 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 439 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, hs_rst_fld[blk_num], 0); 440 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 441 sal_udelay(1000); 442 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, hs_rst_fld[blk_num], 1); 443 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 444 } else { 445 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr(unit, blk_port, &en_bkp)); 446 SOC_IF_ERROR_RETURN(READ_XPORT_XGXS_CTRLr(unit, blk_port, &xctrl_bkp)); 447 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, blk_port, &ctrl_bkp)); 448 SOC_IF_ERROR_RETURN(READ_XPORT_CONFIGr(unit, blk_port, &xcfg)); 449 450 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 451 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, rst_fld[blk_num], 0); 452 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 453 sal_udelay(1000); 454 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, rst_fld[blk_num], 1); 455 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 456 457 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, blk_port, en_bkp)); 458 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, blk_port, xctrl_bkp)); 459 rval = 0; 460 soc_reg_field_set(unit, XPORT_XGXS_NEWCTL_REGr, &rval, TXD1G_FIFO_RSTBf, 461 0xf); 462 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_NEWCTL_REGr(unit, blk_port, rval)); 463 rval = 0; 464 SOC_IF_ERROR_RETURN(WRITE_XPORT_XMAC_CONTROLr(unit, blk_port, rval)); 465 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, blk_port, ctrl_bkp)); 466 SOC_IF_ERROR_RETURN(WRITE_XPORT_CONFIGr(unit, blk_port, xcfg)); 467 468 /* Probe for ports */ 469 SOC_PBMP_CLEAR(okay_ports); 470 if ((rv = bcm_esw_port_probe(unit, blk_pbmp, &okay_ports)) != 471 BCM_E_NONE) { 472 return rv; 473 } 474 475 /* Probe and initialize MAC and PHY drivers for ports that were OK */ 476 PBMP_ITER(blk_pbmp, port) { 477 if ((rv = _bcm_port_mode_setup(unit, port, TRUE)) < 0) { 478 LOG_WARN(BSL_LS_BCM_PORT, 479 (BSL_META_U(unit, 480 "Warning: Port %s: " 481 "Failed to set initial mode: %s\n"), 482 SOC_PORT_NAME(unit, port), bcm_errmsg(rv))); 483 } 484 #ifdef BCM_RCPU_SUPPORT 485 if (SOC_IS_RCPU_ONLY(unit) && IS_RCPU_PORT(unit, port)) { 486 if ((rv = soc_phyctrl_enable_set(unit, port, TRUE)) < 0) { 487 LOG_WARN(BSL_LS_BCM_PORT, 488 (BSL_META_U(unit, 489 "Warning: Port %s: " 490 "Failed to set Phyctrl Enable: %s\n"), 491 SOC_PORT_NAME(unit, port), bcm_errmsg(rv))); 492 } 493 continue; 494 } 495 #endif 496 497 #ifdef BCM_PORT_DEFAULT_DISABLE 498 port_enable = FALSE; 499 #else 500 port_enable = TRUE; 501 #endif 502 if ((rv = bcm_esw_port_enable_set(unit, port, port_enable)) < 0) { 503 LOG_WARN(BSL_LS_BCM_PORT, 504 (BSL_META_U(unit, 505 "Warning: Port %s: " 506 "Failed to %s port: %s\n"), 507 SOC_PORT_NAME(unit, port),(port_enable) ? \ 508 "enable" : "disable" ,bcm_errmsg(rv))); 509 } 510 511 #ifdef BCM_RCPU_SUPPORT 512 if ((uint32)port == soc_property_get(unit, spn_RCPU_PORT, -1)) { 513 if ((rv = bcm_esw_port_frame_max_set(unit, port, BCM_PORT_JUMBO_MAXSZ)) < 0) { 514 LOG_WARN(BSL_LS_BCM_PORT, 515 (BSL_META_U(unit, 516 "Warning: Port %s: " 517 "Failed to set Max Frame: %s\n"), 518 SOC_PORT_NAME(unit, port), bcm_errmsg(rv))); 519 } 520 } 521 #endif 522 } 523 } 524 return BCM_E_NONE; 525 } 526 527 int _bcm_kt_port_downsizer_chk_reinit(int unit, uint32 *tx_pkt) 528 { 529 bcm_pkt_t *pkt_info; 530 bcm_pbmp_t blk_pbmp; 531 bcm_port_t port; 532 int blk, i; 533 int blk_num, blk_port, fail=0; 534 uint32 mask; 535 int ports_in_block[4][4] = { 536 {25,-1,-1,-1}, 537 {26,-1,-1,-1}, 538 {27,32,33,34}, 539 {28,29,30,31} 540 }; 541 soc_pbmp_t all_pbmp; 542 int local_port = 0; 543 int mxq2cnt = 4; 544 int mxq3cnt = 4; 545 546 pkt_info = sal_alloc(sizeof(bcm_pkt_t), "pkt_info"); 547 if (NULL == pkt_info) { 548 return BCM_E_MEMORY; 549 } 550 sal_memset(pkt_info, 0, sizeof(bcm_pkt_t)); 551 pkt_info->unit = unit; 552 pkt_info->_pkt_data.data = (uint8 *) tx_pkt; 553 pkt_info->pkt_data = &pkt_info->_pkt_data; 554 pkt_info->blk_count = 1; 555 pkt_info->_pkt_data.len = 68; 556 pkt_info->call_back = NULL; 557 pkt_info->flags = 0x00230020; 558 559 560 BCM_PBMP_CLEAR(all_pbmp); 561 BCM_PBMP_ASSIGN(all_pbmp, PBMP_ALL(unit)); 562 PBMP_ITER(all_pbmp, local_port) { 563 if ((local_port == 27) || (local_port == 32) || 564 (local_port == 33) || (local_port == 34)) { 565 mxq2cnt--; 566 } 567 if ((local_port == 28) || (local_port == 29) || 568 (local_port == 30) || (local_port == 31)) { 569 mxq3cnt--; 570 } 571 } 572 if (((mxq2cnt != 4) && (!SOC_PORT_VALID(unit, 27))) || 573 ((mxq3cnt != 4) && (!SOC_PORT_VALID(unit, 28)))) { 574 LOG_VERBOSE(BSL_LS_SOC_COMMON, 575 (BSL_META_U(unit, 576 "Skipping Downsizer logic \n"))); 577 if (pkt_info != NULL) { 578 sal_free(pkt_info); 579 } 580 return BCM_E_NONE; 581 } 582 583 584 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 585 blk_num = SOC_BLOCK_INFO(unit, blk).number; 586 blk_port = SOC_BLOCK_PORT(unit, blk); 587 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr(unit,blk_port,&mask)); 588 BCM_PBMP_CLEAR(blk_pbmp); 589 /* enumerate all valid ports in this block */ 590 for (i=0; i<4; i++) { 591 if (mask & (1<<i)) { 592 BCM_PBMP_PORT_ADD(blk_pbmp, ports_in_block[blk_num][i]); 593 } 594 } 595 596 /* Validate all ports in this block */ 597 fail = 0; 598 PBMP_ITER(blk_pbmp, port) { 599 if (_bcm_kt_port_downsizer_check_port(unit, port, pkt_info) == BCM_E_FAIL) { 600 fail = 1; 601 break; 602 } 603 } 604 605 if (fail) { 606 LOG_VERBOSE(BSL_LS_SOC_COMMON, 607 (BSL_META_U(unit, 608 "Block MXQPORT%d failed.. Trying HotSwap Reset\n"), 609 blk_num)); 610 (void)_bcm_kt_port_downsizer_blk_reinit(unit, blk_num, blk_port, blk_pbmp, TRUE); 611 /* Re-Validate all ports in this block */ 612 fail = 0; 613 PBMP_ITER(blk_pbmp, port) { 614 if (_bcm_kt_port_downsizer_check_port(unit, port, pkt_info) == BCM_E_FAIL) { 615 fail = 1; 616 break; 617 } 618 } 619 if (fail) { 620 LOG_VERBOSE(BSL_LS_SOC_COMMON, 621 (BSL_META_U(unit, 622 "Block MXQPORT%d failed.. " 623 "Trying Full Block Reset\n"), blk_num)); 624 BCM_IF_ERROR_RETURN( 625 _bcm_kt_port_downsizer_blk_reinit(unit, blk_num, blk_port, blk_pbmp, FALSE)); 626 /* Re-Re-Validate all ports in this block */ 627 fail = 0; 628 PBMP_ITER(blk_pbmp, port) { 629 if (_bcm_kt_port_downsizer_check_port(unit, port, pkt_info) == BCM_E_FAIL) { 630 fail = 1; 631 break; 632 } 633 } 634 if (fail) { 635 LOG_VERBOSE(BSL_LS_SOC_COMMON, 636 (BSL_META_U(unit, 637 "Block MXQPORT%d failed after WAR\n"), 638 blk_num)); 639 if (pkt_info != NULL) { 640 sal_free(pkt_info); 641 } 642 return BCM_E_FAIL; 643 } 644 } 645 LOG_VERBOSE(BSL_LS_SOC_COMMON, 646 (BSL_META_U(unit, 647 "Block MXQPORT%d OK\n"), blk_num)); 648 } 649 } 650 if (pkt_info != NULL) { 651 sal_free(pkt_info); 652 } 653 return BCM_E_NONE; 654 } 655 656 #define KT_WAR_BUF_SIZE 256 657 658 int 659 bcm_kt_port_downsizer_chk_reinit(int unit) { 660 uint32 *tx_pkt; 661 uint32 *buff; 662 int rv,i; 663 sal_usecs_t stime = sal_time_usecs(); 664 665 uint32 pkt[17] = {0x66778899, 0xaabb0011, 0x22334455, 0x81000001, 666 0x002e0000, 0x56761234, 0x56771234, 0x56781234, 667 0x56791234, 0x567a1234, 0x567b1234, 0x567c1234, 668 0x567d1234, 0x567e1234, 0x567f1234, 0x56801234, 669 0x00000000}; 670 671 /* Applicable only for MXQ ports. */ 672 if (SOC_PBMP_IS_NULL(PBMP_MXQ_ALL(unit))) { 673 return BCM_E_NONE; 674 } 675 676 tx_pkt = soc_cm_salloc(unit, KT_WAR_BUF_SIZE, "tx_pkt"); 677 if (tx_pkt == NULL) { 678 return BCM_E_MEMORY; 679 } 680 buff = tx_pkt; 681 for(i = 0; i < 17; i++) { 682 *buff = pkt[i]; 683 buff++; 684 } 685 soc_cm_sflush(unit, tx_pkt, KT_WAR_BUF_SIZE); 686 rv = _bcm_kt_port_downsizer_chk_reinit(unit, tx_pkt); 687 if (rv < 0) { 688 LOG_ERROR(BSL_LS_BCM_PORT, 689 (BSL_META_U(unit, 690 "Port Downsizer WAR Failed\n"))); 691 } 692 693 soc_cm_sfree(unit, tx_pkt); 694 LOG_VERBOSE(BSL_LS_SOC_COMMON, 695 (BSL_META_U(unit, 696 "Port Downsizer WAR: took %d usec\n"), 697 SAL_USECS_SUB(sal_time_usecs(), stime))); 698 /* Always return OK so that further init can go on */ 699 return BCM_E_NONE; 700 } 701 702 #endif /* BCM_KATANA_SUPPORT */