port.c (21198B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: port.c 8 * Purpose: Port Management for HELIX 5 9 * 10 * The purpose is to set port management implementation specified 11 * to HELIX 5 in this file. 12 */ 13 14 #include <soc/defs.h> 15 16 #if defined(BCM_HELIX5_SUPPORT) 17 #include <soc/trident3.h> 18 #include <soc/helix5.h> 19 20 #include <bcm_int/esw/tomahawk.h> 21 #include <bcm_int/esw/trident3.h> 22 #include <bcm_int/esw/helix5.h> 23 24 #include <bcm_int/esw/xgs5.h> 25 #include <bcm_int/esw/portctrl.h> 26 27 #include <soc/flexport/helix5/helix5_flexport.h> 28 #include <soc/flexport/helix5/helix5_flexport_defines.h> 29 30 static bcmi_xgs5_dev_info_t *bcmi_hx5_dev_info[SOC_MAX_NUM_DEVICES]; 31 32 /* HW Definitions */ 33 static bcmi_xgs5_port_drv_t bcmi_hx5_port_drv; 34 35 36 /* 37 * Function: 38 * bcmi_hx5_port_dev_info_init 39 * Purpose: 40 * Initialize the device info. 41 * Parameters: 42 * unit - (IN) Unit number. 43 * Returns: 44 * BCM_E_xxx 45 * Notes: 46 */ 47 int 48 bcmi_hx5_port_dev_info_init(int unit) 49 { 50 bcmi_xgs5_dev_info_t *dev_info; 51 soc_info_t *si = &SOC_INFO(unit); 52 int alloc_size; 53 int pipe = 0, phy_port, blk, bindex; 54 int i, cntmaxsize; 55 56 /* Free bcmi_hx5_dev_info[unit] if already allocated */ 57 if (bcmi_hx5_dev_info[unit]) { 58 sal_free(bcmi_hx5_dev_info[unit]); 59 bcmi_hx5_dev_info[unit] = NULL; 60 } 61 62 /* Allocate memory for main SW data structure */ 63 alloc_size = sizeof(bcmi_xgs5_dev_info_t) + 64 (sizeof(bcmi_xgs5_phy_port_t) * (HELIX5_PHY_PORTS_PER_DEV)); 65 dev_info = sal_alloc(alloc_size, "bcmi_hx5_dev_info"); 66 if (dev_info == NULL) { 67 return BCM_E_MEMORY; 68 } 69 sal_memset(dev_info, 0, alloc_size); 70 dev_info->phy_port_info = (bcmi_xgs5_phy_port_t *)&dev_info[1]; 71 bcmi_hx5_dev_info[unit] = dev_info; 72 73 /* Clear data structure */ 74 75 /* Device information init */ 76 dev_info = bcmi_hx5_dev_info[unit]; 77 dev_info->phy_ports_max = HELIX5_PHY_PORTS_PER_DEV; 78 dev_info->mmu_lossless = 0; 79 dev_info->asf_prof_default = _SOC_ASF_MEM_PROFILE_EXTREME; 80 dev_info->pipe_bound = 1; 81 /* First logical port in pipe */ 82 dev_info->pipe_log_port_base[pipe] = 0; 83 84 /* First physical port in pipe */ 85 dev_info->pipe_phy_port_base[pipe] = 0; 86 87 dev_info->ports_pipe_max[pipe] = HELIX5_PHY_PORTS_PER_PIPE; 88 89 /* 10G is the min speed in TDM calendar program. 90 * TDM eventually sets minimum speed to 10G in TDM calendar. 91 */ 92 dev_info->tdm_speed_min = SPEED_1G; 93 94 /* 10G is the min speed in TDM calculations */ 95 dev_info->tdm_pipe_lr_bw_limit_checker_speed_min = SPEED_10G; 96 97 cntmaxsize = soc_property_get(unit, spn_BCM_STAT_JUMBO, 1518); 98 if (cntmaxsize > si->max_mtu) { 99 cntmaxsize = si->max_mtu; 100 } 101 dev_info->cntmaxsize_xl = cntmaxsize; 102 dev_info->cntmaxsize_cl = cntmaxsize; 103 104 dev_info->restriction_mask = BCMI_XGS5_FLEXPORT_RESTRICTION_SPEED_CLASS | 105 BCMI_XGS5_FLEXPORT_RESTRICTION_PM_OVS_MIX_SISTER | 106 BCMI_XGS5_FLEXPORT_RESTRICTION_PM_SINGLE_PLL; 107 108 dev_info->encap_mask = BCM_PA_ENCAP_IEEE | BCM_PA_ENCAP_HIGIG2; 109 110 /* 111 * Restriction 13:No port configurations with more than 5 port speed 112 * classes are supported. 113 */ 114 dev_info->speed_class.speed_class_num = _HX5_TDM_SPEED_CLASS_MAX; 115 dev_info->speed_class.no_mix_speed_mask = 0; 116 117 dev_info->port_ratio_mask = BCMI_XGS5_PORT_RATIO_SINGLE | 118 BCMI_XGS5_PORT_RATIO_DUAL_1_1 | 119 BCMI_XGS5_PORT_RATIO_DUAL_2_1 | 120 BCMI_XGS5_PORT_RATIO_DUAL_1_2 | 121 BCMI_XGS5_PORT_RATIO_TRI_023_2_1_1 | 122 BCMI_XGS5_PORT_RATIO_TRI_023_4_1_1 | 123 BCMI_XGS5_PORT_RATIO_TRI_012_1_1_2 | 124 BCMI_XGS5_PORT_RATIO_TRI_012_1_1_4 | 125 BCMI_XGS5_PORT_RATIO_QUAD; 126 127 /* Set max line rate bandwidth per pipeline */ 128 dev_info->pipe_lr_bw = 560000; 129 130 /* Set valid speeds for 1/2/4 Lanes */ 131 dev_info->speed_valid[1] = SOC_PA_SPEED_10MB | SOC_PA_SPEED_100MB | 132 SOC_PA_SPEED_1000MB | SOC_PA_SPEED_2500MB | 133 SOC_PA_SPEED_5000MB | SOC_PA_SPEED_10GB | 134 SOC_PA_SPEED_11GB | SOC_PA_SPEED_25GB | SOC_PA_SPEED_27GB; 135 136 dev_info->speed_valid[2] = SOC_PA_SPEED_10GB | SOC_PA_SPEED_11GB | 137 SOC_PA_SPEED_20GB | SOC_PA_SPEED_21GB | 138 SOC_PA_SPEED_40GB | SOC_PA_SPEED_42GB | 139 SOC_PA_SPEED_50GB | SOC_PA_SPEED_53GB; 140 141 dev_info->speed_valid[4] = SOC_PA_SPEED_40GB | SOC_PA_SPEED_42GB | SOC_PA_SPEED_100GB; 142 143 /* 144 * Set physical port info: 145 * - Port lane capability 146 * - Port is enabled for flexport 147 * - pipe 148 */ 149 for (phy_port = 0; phy_port < HELIX5_PHY_PORTS_PER_DEV; phy_port++) { 150 /* Set information to invalid */ 151 dev_info->phy_port_info[phy_port].pipe = -1; 152 } 153 154 /* Flexport is not supported for CPU/LB/MNG ports, so skip CPU/LB/MNG */ 155 for (phy_port = 1; phy_port < HELIX5_PHY_PORTS_PER_DEV; phy_port++) { 156 /* Check for end of port list */ 157 if (SOC_PORT_BLOCK(unit, phy_port) < 0 && 158 SOC_PORT_BINDEX(unit, phy_port) < 0) { 159 break; 160 } 161 /* Set pipe information */ 162 dev_info->phy_port_info[phy_port].pipe = 0; 163 164 for (i = 0; i < SOC_DRIVER(unit)->port_num_blktype; i++) { 165 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, i); 166 bindex = SOC_PORT_IDX_BINDEX(unit, phy_port, i); 167 168 if ((blk < 0) || (bindex < 0)) { 169 continue; 170 } 171 172 if ((SOC_BLOCK_TYPE(unit, blk) == SOC_BLK_CLPORT) || 173 (SOC_BLOCK_TYPE(unit, blk) == SOC_BLK_XLPORT) || 174 (SOC_BLOCK_TYPE(unit, blk) == SOC_BLK_GXPORT)) { 175 /* Set port lane capabilites */ 176 dev_info->phy_port_info[phy_port].lanes_valid = 177 BCMI_XGS5_PORT_LANES_1; 178 if (bindex == 0) { 179 dev_info->phy_port_info[phy_port].lanes_valid |= 180 BCMI_XGS5_PORT_LANES_2 | BCMI_XGS5_PORT_LANES_4; 181 } else if (bindex == 2) { 182 dev_info->phy_port_info[phy_port].lanes_valid |= 183 BCMI_XGS5_PORT_LANES_2; 184 } 185 186 if (SHR_BITGET(si->flexible_pm_bitmap,blk)) { 187 dev_info->phy_port_info[phy_port].flex = 1; 188 } 189 } 190 } /* for port_num_blktype */ 191 dev_info->phy_port_info[phy_port].max_lane_speed = 27000; 192 } 193 194 /* Init condition */ 195 _bcmi_td3_init_condition_set(unit, dev_info); 196 197 return BCM_E_NONE; 198 } 199 200 /* 201 * Function: 202 * bcmi_hx5_port_soc_resource_init 203 * Purpose: 204 * Initialize SOC Port Structure. 205 * This includes: 206 * Copy Port information from BCM port resource array. 207 * Set correct pipe, MMU port, IDB port for new logical port. 208 * Parameters: 209 * unit - (IN) Unit number. 210 * nport - (IN) Number of elements in array resource. 211 * resource - (IN) BCM Port resource configuration array. 212 * soc_resource - (OUT) SOC Port resource array. 213 * Returns: 214 * BCM_E_xxx 215 * Notes: 216 */ 217 STATIC int 218 bcmi_hx5_port_soc_resource_init(int unit, int nport, 219 bcm_port_resource_t *resource, 220 soc_port_resource_t *soc_resource) 221 { 222 int i, oversub; 223 int phy_port, logic_port, idb_port, mmu_port, pipe; 224 int free_mmu_port[HELIX5_GDEV_PORTS_PER_PIPE] = {0}; 225 soc_info_t *si = &SOC_INFO(unit); 226 227 /* 228 * SOC Port Structure initialization 229 */ 230 231 /* Clear data structure */ 232 sal_memset(soc_resource, 0, sizeof(soc_port_resource_t) * nport); 233 mmu_port = 16; 234 235 /* Copy initial information */ 236 for (i = 0; i < nport; i++) { 237 logic_port = resource[i].port; 238 phy_port = resource[i].physical_port; 239 idb_port = si->port_l2i_mapping[logic_port]; 240 oversub = soc_hx5_port_oversub_get(unit, phy_port, logic_port); 241 242 pipe = 0; 243 if (phy_port <= 60 && !oversub && 244 !(resource[i].flags & SOC_PORT_RESOURCE_SPEED)) { 245 if (phy_port < 0 && idb_port >= 16) { 246 /* Delete mapping - Add assigned idb/mmu port in free list */ 247 free_mmu_port[idb_port] = 1; 248 } 249 250 if (phy_port > 0) { 251 /* Search for first unused mmu_port */ 252 for (; mmu_port < HELIX5_GDEV_PORTS_PER_PIPE; mmu_port++) { 253 if ((si->port_m2p_mapping[mmu_port] == -1) || 254 (free_mmu_port[mmu_port] == 1)){ 255 idb_port = mmu_port; 256 break; 257 } 258 } 259 if (mmu_port >= HELIX5_GDEV_PORTS_PER_PIPE) { 260 LOG_ERROR(BSL_LS_BCM_PORT, (BSL_META_U 261 (unit,"Cannot find free MMU port\n"))); 262 263 return BCM_E_RESOURCE; 264 } 265 mmu_port++; 266 } 267 } else if (phy_port > 0) { 268 /* Fixed mapping */ 269 idb_port = si->port_p2m_mapping[phy_port]; 270 } 271 272 soc_resource[i].flags = resource[i].flags; 273 soc_resource[i].logical_port = logic_port; 274 soc_resource[i].physical_port = phy_port; 275 /* Pass less than 1g speeds as 1g */ 276 soc_resource[i].speed = resource[i].speed < 1000 ? 1000 : resource[i].speed; 277 soc_resource[i].num_lanes = resource[i].lanes; 278 soc_resource[i].encap = resource[i].encap; 279 soc_resource[i].pipe = pipe; 280 soc_resource[i].idb_port = idb_port; 281 soc_resource[i].mmu_port = idb_port; 282 soc_resource[i].oversub = oversub; 283 284 if (resource[i].speed >= 40000) { 285 soc_resource[i].hsp = 1; 286 } 287 } 288 289 return BCM_E_NONE; 290 } 291 292 /* Function: 293 * bcmi_hx5_port_resource_validate 294 * Purpose: 295 * Validate that the given FlexPort operations is valid. 296 * Parameters: 297 * unit - (IN) Unit number. 298 * port_schedule_state - (OUT) Port resource state. 299 * Returns: 300 * BCM_E_xxx 301 * Notes: 302 */ 303 STATIC int 304 bcmi_hx5_port_resource_validate(int unit, 305 soc_port_schedule_state_t *port_schedule_state) 306 { 307 int phy_port; 308 soc_port_map_type_t *post_pi = &port_schedule_state->out_port_map; 309 310 for (phy_port = 1; phy_port <= HELIX5_GPHY_PORTS_PER_PIPE; phy_port++) { 311 /* Front Panel Ports */ 312 if (post_pi->port_p2l_mapping[phy_port] > 64) { 313 LOG_CLI((BSL_META_U(unit, "Invalid logical port number %d\n"), 314 post_pi->port_p2l_mapping[phy_port])); 315 return BCM_E_PARAM; 316 } 317 } 318 return BCM_E_NONE; 319 } 320 321 /* 322 * Function: 323 * bcmi_hx5_pre_flexport_tdm 324 * Purpose: 325 * Pass TDM information pre FlexPort to DV FlexPort API 326 * Parameters: 327 * unit - (IN) Unit number. 328 * port_schedule_state - (OUT) Port resource state. 329 * Returns: 330 * BCM_E_xxx 331 * Notes: 332 */ 333 STATIC int 334 bcmi_hx5_pre_flexport_tdm(int unit, 335 soc_port_schedule_state_t *port_schedule_state) 336 { 337 port_schedule_state->is_flexport = 1; 338 339 BCM_IF_ERROR_RETURN 340 (soc_hx5_port_schedule_tdm_init(unit, port_schedule_state)); 341 return BCM_E_NONE; 342 } 343 344 /* 345 * Function: 346 * bcmi_hx5_post_flexport_tdm 347 * Purpose: 348 * Update TDM information in SOC with post FlexPort TDM state return from 349 * DV FlexPort API. 350 * Parameters: 351 * unit - (IN) Unit number. 352 * port_schedule_state - (IN) Port resource state. 353 * Returns: 354 * BCM_E_xxx 355 * Notes: 356 */ 357 STATIC int 358 bcmi_hx5_post_flexport_tdm(int unit, 359 soc_port_schedule_state_t *port_schedule_state) 360 { 361 BCM_IF_ERROR_RETURN 362 (soc_hx5_soc_tdm_update(unit, port_schedule_state)); 363 return BCM_E_NONE; 364 } 365 366 /* 367 * Function: 368 * bcmi_hx5_port_enable 369 * Purpose: 370 * Enable port. 371 * Parameters: 372 * unit - (IN) Unit number. 373 * port_schedule_state - (IN) Port resource state. 374 * Returns: 375 * BCM_E_xxx 376 * Notes: 377 * This function should only be called with PORTMOD enabled 378 */ 379 STATIC int 380 bcmi_hx5_port_enable(int unit, soc_port_schedule_state_t *port_schedule_state) 381 { 382 return soc_helix5_flex_top_port_up(unit, port_schedule_state); 383 } 384 385 /* 386 * Function: 387 * bcmi_hx5_port_disable 388 * Purpose: 389 * Disable port. 390 * Parameters: 391 * unit - (IN) Unit number. 392 * port_schedule_state - (IN) Port resource state. 393 * Returns: 394 * BCM_E_xxx 395 * Notes: 396 * This function should only be called with PORTMOD enabled 397 */ 398 STATIC int 399 bcmi_hx5_port_disable(int unit, soc_port_schedule_state_t *port_schedule_state) 400 { 401 return soc_helix5_flex_top_port_down(unit, port_schedule_state); 402 } 403 404 /* 405 * Function: 406 * bcmi_hx5_speed_ability_get 407 * Purpose: 408 * Retrieve the local port abilities. 409 * Parameters: 410 * unit - Unit. 411 * port - Logical port num. 412 * mask - (OUT) Mask of BCM_PORT_ABILITY_ values indicating the 413 * supported speeds of the port. 414 * Returns: 415 * BCM_E_NONE 416 * BCM_E_XXX 417 */ 418 STATIC int 419 bcmi_hx5_speed_ability_get(int unit, bcm_port_t port, bcm_port_abil_t *mask) 420 { 421 BCM_IF_ERROR_RETURN(soc_hx5_support_speeds(unit, port, mask)); 422 return BCM_E_NONE; 423 } 424 425 STATIC int 426 bcmi_hx5_port_attach_mmu(int unit, int port) 427 { 428 if (IS_CPU_PORT(unit, port) || IS_LB_PORT(unit, port) || 429 IS_FAE_PORT(unit, port)) { 430 return BCM_E_PARAM; 431 } 432 433 /* Assign the base queues and number of queues for the specified port. */ 434 BCM_IF_ERROR_RETURN 435 (soc_helix5_num_cosq_init_port(unit, port)); 436 437 /* Enable enqueing packets to the port */ 438 SOC_IF_ERROR_RETURN( 439 soc_td3_port_mmu_tx_enable_set(unit, port, 1)); 440 SOC_IF_ERROR_RETURN( 441 soc_td3_port_mmu_rx_enable_set(unit, port, 1)); 442 443 /* Reconfigure THDI, THDO settings */ 444 BCM_IF_ERROR_RETURN 445 (soc_hx5_mmu_config_init_port(unit, port)); 446 447 return BCM_E_NONE; 448 } 449 450 /* 451 * Function: 452 * bcmi_hx5_port_detach_asf 453 * Purpose: 454 * Update ASF when port deleted during Flexport operations. 455 * Parameters: 456 * unit - (IN) Unit number. 457 * port - (IN) Logical port number. 458 * Returns: 459 * BCM_E_xxx 460 * Notes: 461 */ 462 STATIC int 463 bcmi_hx5_port_detach_asf(int unit, bcm_port_t port) 464 { 465 return BCM_E_NONE; 466 } 467 468 469 /* 470 * Function Vectors 471 */ 472 473 static bcm_esw_port_drv_t bcm_hx5_port_drv = { 474 /* fn_drv_init */ bcmi_hx5_port_fn_drv_init, 475 /* resource_set */ bcmi_xgs5_port_resource_set, 476 /* resource_get */ bcmi_xgs5_port_resource_get, 477 /* resource_multi_set */ bcmi_xgs5_port_resource_multi_set, 478 /* resource_speed_set */ bcmi_xgs5_port_speed_set, 479 /* resource_traverse */ bcmi_xgs5_port_resource_traverse, 480 /* port_redirect_set */ NULL, 481 /* port_redirect_get */ NULL, 482 /* port_enable_set */ bcmi_xgs5_port_enable_set, 483 /* encap_speed_check */ bcmi_xgs5_port_encap_speed_check, 484 /* force_lb_set */ NULL, 485 /* force_lb_check */ NULL, 486 /* resource_status_update */ bcmi_xgs5_port_resource_status_update, 487 /* port_resource_speed_multi_set */ bcmi_xgs5_port_resource_speed_multi_set, 488 /* device_speed_check */ NULL 489 }; 490 491 /* Device programming routines */ 492 static bcmi_xgs5_port_func_t bcmi_hx5_port_calls = { 493 /* reconfigure_ports */ soc_helix5_reconfigure_ports, 494 /* soc_resource_init */ bcmi_hx5_port_soc_resource_init, 495 /* port_resource_validate */ bcmi_hx5_port_resource_validate, 496 /* pre_flexport_tdm */ bcmi_hx5_pre_flexport_tdm, 497 /* post_flexport_tdm */ bcmi_hx5_post_flexport_tdm, 498 /* port_macro_update */ NULL, 499 /* port_enable */ bcmi_hx5_port_enable, 500 /* port_disable */ bcmi_hx5_port_disable, 501 /* no_tdm_speed_update */ bcmi_td3_port_speed_1g_update, 502 /* speed_ability_get */ bcmi_hx5_speed_ability_get, 503 /* speed_mix_validate */ NULL, 504 /* cos_map_update */ bcmi_hx5_port_cosmap_update, 505 }; 506 507 static 508 int (*hx5_port_attach_exec[PORT_ATTACH_EXEC__MAX])(int unit, bcm_port_t port) = { 509 /* MMU config init */ 510 &bcmi_hx5_port_attach_mmu, 511 512 /* PORT module (bcm_esw_port_init) */ 513 &bcmi_xgs5_port_attach_dscp, 514 &bcmi_xgs5_port_attach_software, 515 &bcmi_xgs5_port_attach_egr_vlan_action, 516 &bcmi_xgs5_port_cfg_init, 517 &bcmi_xgs5_port_attach_port_probe, 518 &bcmi_xgs5_port_attach_frame_length_check, 519 &bcmi_xgs5_port_attach_rcpu_mtu, 520 &bcmi_xgs5_port_attach_outer_tpid, 521 &bcmi_xgs5_port_egr_block_profile_init, 522 &bcmi_xgs5_port_attach_vlan_protocol, 523 &bcmi_xgs5_port_attach_eee, 524 &bcmi_xgs5_port_attach_higig, 525 &bcmi_xgs5_port_attach_port_info_cfg, 526 &bcmi_xgs5_port_attach_egr_link_delay, 527 528 /* Other modules related to port */ 529 &bcmi_xgs5_port_attach_stg, 530 &bcmi_xgs5_port_attach_vlan, 531 &bcmi_xgs5_port_attach_trunk, 532 &bcm_hx5_cosq_port_attach, 533 &bcmi_xgs5_port_attach_linkscan, 534 &bcmi_xgs5_port_attach_stat, 535 &bcmi_td3_port_attach_stack, 536 &bcmi_xgs5_port_attach_rate, 537 &bcmi_xgs5_port_attach_field, 538 &bcmi_xgs5_port_attach_mirror, 539 &bcmi_td3_port_attach_l3, 540 &bcmi_xgs5_port_attach_ipmc, 541 #if defined(INCLUDE_L3) 542 &bcm_th_ipmc_repl_port_attach, 543 #else 544 NULL, 545 #endif 546 &bcmi_xgs5_port_attach_mpls, 547 &bcmi_xgs5_port_attach_mim, 548 }; 549 550 static 551 int (*hx5_port_detach_exec[PORT_DETACH_EXEC__MAX])(int unit, bcm_port_t port) = { 552 /* Other modules related to port */ 553 #if defined(INCLUDE_L3) 554 &bcm_th_ipmc_repl_port_detach, 555 #else 556 NULL, 557 #endif 558 &bcmi_xgs5_port_detach_ipmc, 559 &bcmi_xgs5_port_detach_mpls, 560 &bcmi_xgs5_port_detach_mim, 561 &bcmi_td3_port_detach_l3, 562 &bcmi_xgs5_port_detach_mirror, 563 &bcmi_xgs5_port_detach_field, 564 &bcmi_xgs5_port_detach_rate, 565 &bcmi_td3_port_detach_stack, 566 &bcm_hx5_cosq_port_detach, 567 &bcmi_xgs5_port_detach_trunk, 568 &bcmi_xgs5_port_detach_vlan, 569 &bcmi_xgs5_port_detach_stg, 570 571 /* PORT module (_bcm_esw_port_deinit) */ 572 &bcmi_hx5_port_detach_asf, 573 &bcmi_xgs5_port_detach_egr_link_delay, 574 &bcmi_xgs5_port_detach_higig, 575 &bcmi_xgs5_port_detach_eee, 576 &bcmi_xgs5_port_detach_vlan_protocol, 577 &bcmi_xgs5_port_egr_block_profile_init, 578 &bcmi_xgs5_port_detach_phy, 579 &bcmi_xgs5_port_detach_dscp, 580 &bcmi_xgs5_port_cfg_init, 581 &bcmi_xgs5_port_detach_egr_vlan_action, 582 &bcmi_xgs5_port_detach_software, 583 }; 584 585 /* 586 * Function: 587 * bcmi_hx5_port_fn_drv_init 588 * Purpose: 589 * Initialize the Port function driver. 590 * Parameters: 591 * unit - (IN) Unit number. 592 * Returns: 593 * BCM_E_xxx 594 * Notes: 595 */ 596 int 597 bcmi_hx5_port_fn_drv_init(int unit) 598 { 599 int phase_pos, present; 600 601 BCM_IF_ERROR_RETURN 602 (bcmi_hx5_port_dev_info_init(unit)); 603 604 /* BCMI Driver init */ 605 bcmi_hx5_port_drv.port_calls = &bcmi_hx5_port_calls; 606 bcmi_hx5_port_drv.dev_info[unit] = bcmi_hx5_dev_info[unit]; 607 608 609 sal_memcpy(bcmi_hx5_port_drv.port_calls->port_attach_exec, 610 hx5_port_attach_exec, 611 sizeof(bcmi_hx5_port_drv.port_calls->port_attach_exec)); 612 613 sal_memcpy(bcmi_hx5_port_drv.port_calls->port_detach_exec, 614 hx5_port_detach_exec, 615 sizeof(bcmi_hx5_port_drv.port_calls->port_detach_exec)); 616 617 /* Initialize Common XGS5 Port module */ 618 BCM_IF_ERROR_RETURN 619 (bcmi_xgs5_port_fn_drv_init(unit, 620 &bcm_hx5_port_drv, 621 &bcmi_hx5_port_drv, 622 NULL)); 623 624 BCM_IF_ERROR_RETURN(soc_check_flex_phase(unit, hx5_flexport_phases, 625 soc_helix5_flex_top_port_down, 626 &present)); 627 /* Detach port enable/disable in DV Flexport */ 628 if (present) { 629 BCM_IF_ERROR_RETURN 630 (soc_detach_flex_phase(unit, hx5_flexport_phases, 631 soc_helix5_flex_top_port_down, 632 &phase_pos)); 633 } 634 BCM_IF_ERROR_RETURN(soc_check_flex_phase(unit, hx5_flexport_phases, 635 soc_helix5_flex_top_port_up, 636 &present)); 637 if (present) { 638 BCM_IF_ERROR_RETURN 639 (soc_detach_flex_phase(unit, hx5_flexport_phases, 640 soc_helix5_flex_top_port_up, 641 &phase_pos)); 642 } 643 644 return BCM_E_NONE; 645 } 646 647 #endif /* BCM_HELIX5_SUPPORT */