bst.c (29115B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * BST - Buffer Statistics Tracking 8 * Purpose: API to set and manage various BST resources for TH 9 */ 10 11 #include <shared/bsl.h> 12 #include <soc/defs.h> 13 #include <sal/core/libc.h> 14 #include <shared/alloc.h> 15 #include <sal/core/spl.h> 16 #include <sal/core/boot.h> 17 18 #include <soc/drv.h> 19 #include <soc/error.h> 20 #include <soc/ll.h> 21 #include <soc/debug.h> 22 #include <soc/mem.h> 23 #include <soc/profile_mem.h> 24 #include <soc/trident3.h> 25 #include <soc/helix5.h> 26 27 #include <bcm/switch.h> 28 #include <bcm/types.h> 29 #include <bcm/cosq.h> 30 #include <bcm_int/bst.h> 31 #include <bcm_int/esw/port.h> 32 33 #if defined(BCM_HELIX5_SUPPORT) 34 extern int _bcm_bst_td3_byte_to_cell(int unit, uint32 bytes); 35 extern int _bcm_bst_td3_cell_to_byte(int unit, uint32 cells); 36 extern int _bcm_td3_bst_control_set(int unit, bcm_switch_control_t type, int arg, 37 _bcm_bst_thread_oper_t operation); 38 extern int _bcm_td3_bst_control_get(int unit, bcm_switch_control_t type, int *arg); 39 extern int _bcm_bst_td3_intr_to_resources(int unit, uint32 *flags); 40 extern int _bcm_bst_td3_sync_hw_snapshot(int unit, bcm_bst_stat_id_t bid, 41 int port, int index); 42 extern int _bcm_bst_td3_hw_stat_clear(int unit, _bcm_bst_resource_info_t *resInfo, 43 bcm_bst_stat_id_t bid, int port, int index); 44 extern int _bcm_bst_td3_intr_enable_set(int unit, int enable); 45 extern int _bst_td3_port_to_mmu_inst_map_get(int unit, bcm_bst_stat_id_t bid, 46 bcm_gport_t gport, uint32 *mmu_inst_map); 47 extern int _bcm_bst_td3_sbusdma_desc_init(int unit); 48 extern int _bcm_bst_td3_sbusdma_desc_deinit(int unit); 49 extern int _bcm_bst_td3_sw_sbusdma_desc_sync(int unit, int bid); 50 extern int _bcm_bst_td3_sbusdma_desc_sync(int unit); 51 52 53 STATIC int 54 soc_hx5_set_hw_intr_cb(int unit) 55 { 56 BCM_IF_ERROR_RETURN(soc_td3_set_bst_callback(unit, &_bcm_bst_hw_event_cb)); 57 return BCM_E_NONE; 58 } 59 60 int _bcm_bst_hx5_thd_reg_index_get(int unit, bcm_bst_stat_id_t bid, int pipe, 61 int hw_index, int *inst, int *index) 62 { 63 if (bid == bcmBstStatIdEgrPortPoolSharedMcast) { 64 int phy_port, mmu_port; 65 soc_info_t *si = &SOC_INFO(unit); 66 mmu_port = hw_index / _HX5_MMU_NUM_POOL; 67 phy_port = si->port_m2p_mapping[mmu_port]; 68 *inst = si->port_p2l_mapping[phy_port]; 69 *index = hw_index % _HX5_MMU_NUM_POOL; 70 } 71 72 return BCM_E_NONE; 73 } 74 75 int _bcm_bst_hx5_cmn_io_op(int unit, int op, int pipe, int hw_index, 76 bcm_bst_stat_id_t bid, soc_mem_t mem, soc_reg_t reg, 77 soc_field_t field, uint32 *resval) 78 { 79 uint32 entry[SOC_MAX_MEM_WORDS], rval; 80 int port = REG_PORT_ANY, reg_index = hw_index; 81 _bcm_bst_resource_info_t *resInfo; 82 83 resInfo = _BCM_BST_RESOURCE(unit, bid); 84 if ((resInfo->flags & _BCM_BST_CMN_RES_F_PORTED) && 85 (op & BST_OP_THD)) { 86 BCM_IF_ERROR_RETURN( 87 _bcm_bst_hx5_thd_reg_index_get(unit, bid, pipe, hw_index, 88 &port, ®_index)); 89 } 90 if (port != -1) { 91 if (mem != INVALIDm) { 92 SOC_IF_ERROR_RETURN( 93 soc_mem_read(unit, mem, MEM_BLOCK_ALL, hw_index, entry)); 94 if (op & BST_OP_GET) { 95 *resval = soc_mem_field32_get(unit, mem, entry, field); 96 } else if (op & BST_OP_SET) { 97 soc_mem_field32_set(unit, mem, entry, field, *resval); 98 SOC_IF_ERROR_RETURN( 99 soc_mem_write(unit, mem, MEM_BLOCK_ALL, hw_index, entry)); 100 } 101 } else if (reg != INVALIDr) { 102 SOC_IF_ERROR_RETURN( 103 soc_reg32_get(unit, reg, port, reg_index, &rval)); 104 if (op & BST_OP_GET) { 105 *resval = soc_reg_field_get(unit, reg, rval, field); 106 } else if (op & BST_OP_SET) { 107 if (*resval >= (1 << soc_reg_field_length(unit, reg, field))) { 108 return BCM_E_PARAM; 109 } 110 soc_reg_field_set(unit, reg, &rval, field, *resval); 111 SOC_IF_ERROR_RETURN( 112 soc_reg32_set(unit, reg, port, reg_index, rval)); 113 } 114 } 115 } 116 117 return BCM_E_NONE; 118 } 119 120 int 121 bcm_bst_hx5_init(int unit) 122 { 123 _bcm_bst_cmn_unit_info_t *bst_info; 124 _bcm_bst_resource_info_t *pres; 125 int idx_count, i; 126 /* stat count and thd count need not be same. 127 * stat_count - Acc Type of stat are Non Dup, hence stat is for all ACC type 128 * thd_count - Acc Type of Thd are Dup(except CFAP), hence 1 copy. 129 */ 130 int total_stat_count, total_thd_count; 131 soc_mem_t stat_mem = INVALIDm, child_mem = INVALIDm, thd_mem = INVALIDm; 132 soc_reg_t stat_reg = INVALIDr, thd_reg = INVALIDr, prof_reg = INVALIDr; 133 soc_field_t stat_field = INVALIDf, thd_field = INVALIDf, prof_field = INVALIDf; 134 int layer = 0, granularity = 1; 135 uint32 rval; 136 137 bst_info = _BCM_UNIT_BST_INFO(unit); 138 if (!bst_info) { 139 return BCM_E_MEMORY; 140 } 141 142 bst_info->max_bytes = 0x500000; 143 bst_info->to_cell = _bcm_bst_td3_byte_to_cell; 144 bst_info->to_byte = _bcm_bst_td3_cell_to_byte; 145 bst_info->control_set = _bcm_td3_bst_control_set; 146 bst_info->control_get = _bcm_td3_bst_control_get; 147 bst_info->intr_to_resources = _bcm_bst_td3_intr_to_resources; 148 bst_info->hw_stat_snapshot = _bcm_bst_td3_sync_hw_snapshot; 149 bst_info->hw_stat_clear = _bcm_bst_td3_hw_stat_clear; 150 bst_info->intr_enable_set = _bcm_bst_td3_intr_enable_set; 151 bst_info->pre_sync = NULL; 152 bst_info->post_sync = NULL; 153 bst_info->hw_intr_cb = soc_hx5_set_hw_intr_cb; 154 bst_info->port_to_mmu_inst_map = _bst_td3_port_to_mmu_inst_map_get; 155 bst_info->bst_cmn_io_op = _bcm_bst_hx5_cmn_io_op; 156 bst_info->hw_sbusdma_desc_init = _bcm_bst_td3_sbusdma_desc_init; 157 bst_info->hw_sbusdma_desc_deinit = _bcm_bst_td3_sbusdma_desc_deinit; 158 bst_info->hw_sbusdma_desc_sync = _bcm_bst_td3_sbusdma_desc_sync; 159 if(soc_property_get(unit, spn_PROFILE_PG_1HDRM_8SHARED, 1)) { 160 bst_info->mode = 1; 161 } else { 162 bst_info->mode = 0; 163 } 164 165 /* DEVICE - Resources begin */ 166 /* bcmBstStatIdDevice */ 167 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdDevice); 168 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 169 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_RES_DEV); 170 pres->num_instance = NUM_XPE(unit); 171 idx_count = 1; 172 stat_mem = INVALIDm; 173 stat_reg = CFAPBSTSTATr; 174 stat_field = BST_STATf; 175 176 /* Threshold info count and Resource allocation */ 177 granularity = 1; 178 total_thd_count = NUM_XPE(unit) * idx_count; 179 _BCM_BST_THRESHOLD_INFO(pres, INVALIDm, CFAPBSTTHRSr, BST_THRESHOLDf, 180 granularity); 181 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst cfap"); 182 /* Stat info count and Resource allocation */ 183 total_stat_count = total_thd_count; /* No per pipe copy */ 184 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 185 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst cfap"); 186 pres->index_min = 0; 187 pres->index_max = total_stat_count - 1; 188 /* DEVICE - Resources end */ 189 190 /* INGRESS - Resources begin */ 191 /* bcmBstStatIdHeadroomPool */ 192 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdHeadroomPool); 193 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 194 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_RES_ING); 195 pres->num_instance = NUM_XPE(unit); 196 /* There are 4 HDRM POOL per XPE */ 197 idx_count = _HX5_MMU_NUM_POOL; 198 stat_mem = INVALIDm; 199 BCM_IF_ERROR_RETURN(READ_MMU_GCFG_MISCCONFIGr(unit, &rval)); 200 bst_info->track_mode = soc_reg_field_get(unit, MMU_GCFG_MISCCONFIGr, 201 rval, BST_TRACKING_MODEf); 202 /* 203 * As Headroom Pool has two different stats resource 204 * for tracking current usage count and peak usage count 205 * we set up the respective resource accordingly based on 206 * BST Tracking Mode 207 */ 208 if (bst_info->track_mode) { 209 /* Peak Mode */ 210 stat_reg = THDI_HDRM_POOL_PEAK_COUNT_HPr; 211 stat_field = PEAK_BUFFER_COUNTf; 212 } else { 213 /* Current Mode */ 214 stat_reg = THDI_HDRM_POOL_COUNT_HPr; 215 stat_field = TOTAL_BUFFER_COUNTf; 216 } 217 218 /* Disabling the headroom Pool monitoring during init */ 219 for (layer = 0; layer < NUM_LAYER(unit); layer++) { 220 BCM_IF_ERROR_RETURN 221 (soc_reg32_set(unit, THDI_HDRM_POOL_CFGr, layer, 0, 0x0)); 222 } 223 224 /* Stat info count and Resource allocation */ 225 total_stat_count = NUM_XPE(unit) * idx_count; /* No per pipe copy */ 226 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 227 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst ing headroom pool"); 228 pres->index_min = 0; 229 pres->index_max = total_stat_count - 1; 230 231 232 /* bcmBstStatIdIngPool */ 233 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdIngPool); 234 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 235 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_RES_ING); 236 pres->num_instance = NUM_XPE(unit); 237 idx_count = 4; 238 stat_mem = INVALIDm; 239 stat_reg = THDI_BST_SP_GLOBAL_SHARED_CNTr; 240 stat_field = SP_GLOBAL_SHARED_CNTf; 241 242 /* Threshold info count and Resource allocation */ 243 granularity = 1; 244 total_thd_count = idx_count; /* Acc type is Duplicate, hence 1 copy */ 245 _BCM_BST_THRESHOLD_INFO(pres, INVALIDm, 246 THDI_BST_SP_GLOBAL_SHARED_PROFILEr, 247 SP_GLOBAL_SHARED_PROFILEf, granularity); 248 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst ing pool"); 249 /* Stat info count and Resource allocation */ 250 total_stat_count = NUM_XPE(unit) * total_thd_count; /* No per pipe copy */ 251 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 252 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst ing pool"); 253 pres->index_min = 0; 254 pres->index_max = total_stat_count - 1; 255 256 /* bcmBstStatIdPortPool */ 257 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdPortPool); 258 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 259 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 260 _BCM_BST_CMN_RES_F_PIPED | 261 _BCM_BST_CMN_RES_F_RES_ING); 262 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_ALL(unit)); 263 pres->num_instance = NUM_XPE(unit); 264 stat_mem = THDI_PORT_SP_BSTm; 265 stat_reg = INVALIDr; 266 stat_field = SP_BST_STAT_PORT_COUNTf; 267 268 /* Get the mem attributes(Max idx) from the first child, 269 * which could be used for other instances. 270 * Note: In TH, XPE 0/Pipe 0 instance valid for all memories(Ing/Egr). 271 */ 272 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 273 idx_count = soc_mem_index_max(unit, child_mem) + 1; 274 275 /* Threshold info count and Resource allocation */ 276 granularity = 1; 277 total_thd_count = NUM_PIPE(unit) * idx_count; 278 thd_mem = THDI_PORT_SP_CONFIGm; 279 thd_field = SP_BST_PROFILE_SHAREDf; 280 for (i = 0; i < NUM_PIPE(unit); i++) { 281 _BCM_BST_THRESHOLD_INFO_N(pres, SOC_MEM_UNIQUE_ACC(unit, thd_mem)[i], 282 INVALIDr, thd_field, granularity, i); 283 } 284 _BCM_BST_PROFILE_INFO(pres, INVALIDm, THDI_BST_SP_SHARED_PROFILEr, 285 BST_SP_SHARED_THRESHf); 286 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst port pool"); 287 /* Stat info count and Resource allocation */ 288 total_stat_count = NUM_XPE(unit) * total_thd_count; 289 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 290 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst port pool"); 291 pres->index_min = 0; 292 pres->index_max = total_stat_count - 1; 293 294 /* bcmBstStatIdPriGroupShared */ 295 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdPriGroupShared); 296 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 297 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 298 _BCM_BST_CMN_RES_F_PIPED | 299 _BCM_BST_CMN_RES_F_RES_ING); 300 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_ALL(unit)); 301 pres->num_instance = NUM_XPE(unit); 302 stat_mem = THDI_PORT_PG_BSTm; 303 stat_reg = INVALIDr; 304 stat_field = PG_BST_STAT_SHAREDf; 305 idx_count = NUM_PORT(unit) * 8; 306 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 307 idx_count = soc_mem_index_max(unit, child_mem) + 1; 308 309 /* Threshold info count and Resource allocation */ 310 granularity = 1; 311 total_thd_count = idx_count * NUM_PIPE(unit); 312 thd_mem = THDI_PORT_PG_CONFIGm; 313 thd_field = PG_BST_PROFILE_SHAREDf; 314 for (i = 0; i < NUM_PIPE(unit); i++) { 315 _BCM_BST_THRESHOLD_INFO_N(pres, SOC_MEM_UNIQUE_ACC(unit, thd_mem)[i], 316 INVALIDr, thd_field, granularity, i); 317 } 318 _BCM_BST_PROFILE_INFO(pres, INVALIDm, 319 THDI_BST_PG_SHARED_PROFILEr, BST_PG_SHARED_THRESHf); 320 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst pg"); 321 /* Stat info count and Resource allocation */ 322 /* Stat res - THDI_PORT_PG_BST : (Num Ports (32/pipe) * 4 pipes) * 8(PGs) */ 323 total_stat_count = NUM_XPE(unit) * total_thd_count; 324 _BCM_BST_STAT_INFO2(pres, stat_mem, stat_mem, 325 stat_reg, stat_reg, stat_field); 326 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst pg"); 327 pres->index_min = 0; 328 pres->index_max = total_stat_count - 1; 329 330 /* bcmBstStatIdPriGroupHeadroom */ 331 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdPriGroupHeadroom); 332 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 333 pres->num_instance = NUM_XPE(unit); 334 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 335 _BCM_BST_CMN_RES_F_PIPED | 336 _BCM_BST_CMN_RES_F_RES_ING); 337 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_ALL(unit)); 338 stat_mem = THDI_PORT_PG_BSTm; 339 stat_reg = INVALIDr; 340 stat_field = PG_BST_STAT_HDRMf; 341 idx_count = NUM_PORT(unit) * 8; 342 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 343 idx_count = soc_mem_index_max(unit, child_mem) + 1; 344 345 /* Threshold info count and Resource allocation */ 346 granularity = 1; 347 total_thd_count = idx_count * NUM_PIPE(unit); 348 thd_mem = THDI_PORT_PG_CONFIGm; 349 thd_field = PG_BST_PROFILE_HDRMf; 350 for (i = 0; i < NUM_PIPE(unit); i++) { 351 _BCM_BST_THRESHOLD_INFO_N(pres, SOC_MEM_UNIQUE_ACC(unit, thd_mem)[i], 352 INVALIDr, thd_field, granularity, i); 353 } 354 _BCM_BST_PROFILE_INFO(pres, INVALIDm, THDI_BST_PG_HDRM_PROFILEr, 355 BST_PG_HDRM_THRESHf); 356 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst pg hdrm"); 357 /* Stat info count and Resource allocation */ 358 /* Stat res - THDI_PORT_PG_BST : (Num Ports (32/pipe) * 4 pipes) * 8(PGs) */ 359 total_stat_count = NUM_XPE(unit) * total_thd_count; 360 _BCM_BST_STAT_INFO2(pres, stat_mem, stat_mem, 361 stat_reg, stat_reg, stat_field); 362 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst pg hdrm"); 363 pres->index_min = 0; 364 pres->index_max = total_stat_count - 1; 365 /* INGRESS - Resources end */ 366 367 /* EGRESS - Resources begin */ 368 /* bcmBstStatIdEgrPool */ 369 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdEgrPool); 370 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 371 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_RES_EGR); 372 pres->num_instance = NUM_XPE(unit); 373 idx_count = 4; 374 pres->threshold_adj = -1; 375 stat_mem = INVALIDm; 376 stat_reg = MMU_THDM_DB_POOL_MCUC_BST_STATr; 377 stat_field = BST_STATf; 378 379 /* Threshold info count and Resource allocation */ 380 granularity = 1; 381 total_thd_count = idx_count; /* No per pipe copy */ 382 _BCM_BST_THRESHOLD_INFO(pres, INVALIDm, 383 MMU_THDM_DB_POOL_MCUC_BST_THRESHOLDr, BST_STATf, 384 granularity); 385 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst egrpool"); 386 /* Stat info count and Resource allocation */ 387 total_stat_count = NUM_XPE(unit) * total_thd_count; /* No per pipe copy */ 388 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 389 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst egrpool"); 390 pres->index_min = 0; 391 pres->index_max = total_stat_count - 1; 392 393 /* bcmBstStatIdEgrMCastPool */ 394 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdEgrMCastPool); 395 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 396 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_RES_EGR); 397 pres->num_instance = NUM_XPE(unit); 398 idx_count = 4; 399 pres->threshold_adj = -1; 400 stat_mem = INVALIDm; 401 stat_reg = MMU_THDM_DB_POOL_MC_BST_STATr; 402 stat_field = BST_STATf; 403 404 /* Threshold info count and Resource allocation */ 405 granularity = 1; 406 total_thd_count = idx_count; /* No per pipe copy */ 407 _BCM_BST_THRESHOLD_INFO(pres, INVALIDm, 408 MMU_THDM_DB_POOL_MC_BST_THRESHOLDr, BST_STATf, 409 granularity); 410 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst egr mcpool"); 411 /* Stat info count and Resource allocation */ 412 total_stat_count = NUM_XPE(unit) * total_thd_count; /* No per pipe copy */ 413 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 414 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst egr mcpool"); 415 pres->index_min = 0; 416 pres->index_max = total_stat_count - 1; 417 418 /* bcmBstStatIdMcast */ 419 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdMcast); 420 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 421 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 422 _BCM_BST_CMN_RES_F_PIPED | 423 _BCM_BST_CMN_RES_F_RES_EGR); 424 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_CMIC(unit)); 425 pres->num_instance = NUM_XPE(unit); 426 stat_mem = MMU_THDM_DB_QUEUE_BSTm; 427 stat_reg = INVALIDr; 428 stat_field = Q_COUNTf; 429 430 /* Get the mem attributes(Max idx) from the first child, 431 * which could be used for other instances. 432 * Note: In TH, XPE 0/Pipe 0 instance valid for all memories(Ing/Egr). 433 */ 434 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 435 idx_count = soc_mem_index_max(unit, child_mem) + 1; 436 437 /* Threshold info count and Resource allocation */ 438 granularity = 1; 439 total_thd_count = NUM_PIPE(unit) * idx_count; 440 thd_mem = MMU_THDM_DB_QUEUE_CONFIGm; 441 thd_field = BST_THRESHOLD_PROFILEf; 442 for (i = 0; i < NUM_PIPE(unit); i++) { 443 _BCM_BST_THRESHOLD_INFO_N(pres, SOC_MEM_UNIQUE_ACC(unit, thd_mem)[i], 444 INVALIDr, thd_field, granularity, i); 445 } 446 _BCM_BST_PROFILE_INFO(pres, INVALIDm, 447 MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILEr, BST_STATf); 448 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst mcast"); 449 /* Stat info count and Resource allocation */ 450 total_stat_count = NUM_XPE(unit) * total_thd_count; 451 _BCM_BST_STAT_INFO2(pres, stat_mem, stat_mem, 452 stat_reg, stat_reg, stat_field); 453 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst mcast"); 454 pres->index_min = 0; 455 pres->index_max = total_stat_count - 1; 456 457 /* bcmBstStatIdEgrPortPoolSharedMcast */ 458 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdEgrPortPoolSharedMcast); 459 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 460 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 461 _BCM_BST_CMN_RES_F_PIPED | 462 _BCM_BST_CMN_RES_F_RES_EGR | 463 _BCM_BST_CMN_RES_F_PORTED); 464 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_ALL(unit)); 465 pres->num_instance = NUM_XPE(unit); 466 stat_mem = MMU_THDM_DB_PORTSP_BSTm; 467 stat_reg = INVALIDr; 468 stat_field = P_COUNTf; 469 470 /* Get the mem attributes(Max idx) from the first child, 471 * which could be used for other instances. 472 * Note: In TH, XPE 0/Pipe 0 instance valid for all memories(Ing/Egr). 473 */ 474 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 475 idx_count = soc_mem_index_max(unit, child_mem) + 1; 476 477 /* Threshold info count and Resource allocation */ 478 granularity = 1; 479 total_thd_count = NUM_XPE(unit) * NUM_PIPE(unit) * idx_count; 480 thd_reg = MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SELr; 481 thd_field = BST_THRESHOLD_PROFILEf; 482 for (i = 0; i < 8; i++) { 483 _BCM_BST_THRESHOLD_INFO_N(pres, INVALIDm, 484 thd_reg, thd_field, granularity, i); 485 } 486 487 prof_reg = MMU_THDM_DB_PORTSP_BST_THRESHOLDr; 488 prof_field = BST_STATf; 489 for (i = 0; i < NUM_XPE(unit); i++) { 490 _BCM_BST_PROFILE_INFO_N(pres, INVALIDm, 491 prof_reg, prof_field, i); 492 } 493 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, 494 "bst egr port pool shared mcast"); 495 /* Stat info count and Resource allocation */ 496 total_stat_count = total_thd_count; 497 _BCM_BST_STAT_INFO2(pres, stat_mem, stat_mem, 498 stat_reg, stat_reg, stat_field); 499 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, 500 "bst egr port pool shared mcast"); 501 pres->index_min = 0; 502 pres->index_max = total_stat_count - 1; 503 504 /* bcmBstStatIdUcast */ 505 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdUcast); 506 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 507 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 508 _BCM_BST_CMN_RES_F_PIPED | 509 _BCM_BST_CMN_RES_F_RES_EGR); 510 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_PORT_ALL(unit)); 511 pres->num_instance = NUM_XPE(unit); 512 stat_mem = MMU_THDU_BST_QUEUEm; 513 stat_reg = INVALIDr; 514 stat_field = Q_COUNTf; 515 516 /* Get the mem attributes(Max idx) from the first child, 517 * which could be used for other instances. 518 * Note: In TH, XPE 0/Pipe 0 instance valid for all memories(Ing/Egr). 519 */ 520 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 521 idx_count = soc_mem_index_max(unit, child_mem) + 1; 522 523 /* Threshold info count and Resource allocation */ 524 granularity = 8; /* UC Queue Thd is 8 cell granularity */ 525 total_thd_count = NUM_PIPE(unit) * idx_count; 526 thd_mem = MMU_THDU_CONFIG_QUEUEm; 527 thd_field = Q_WM_MAX_THRESHOLDf; 528 for (i = 0; i < NUM_PIPE(unit); i++) { 529 _BCM_BST_THRESHOLD_INFO_N(pres, SOC_MEM_UNIQUE_ACC(unit, thd_mem)[i], 530 INVALIDr, thd_field, granularity, i); 531 } 532 _BCM_BST_PROFILE_INFO(pres, INVALIDm, OP_UC_QUEUE_BST_THRESHOLDr, BST_STATf); 533 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst ucast"); 534 /* Stat info count and Resource allocation */ 535 total_stat_count = NUM_XPE(unit) * total_thd_count; 536 _BCM_BST_STAT_INFO2(pres, stat_mem, stat_mem, 537 stat_reg, stat_reg, stat_field); 538 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst ucast"); 539 pres->index_min = 0; 540 pres->index_max = total_stat_count - 1; 541 542 /* bcmBstStatIdEgrPortPoolSharedUcast */ 543 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdEgrPortPoolSharedUcast); 544 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 545 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 546 _BCM_BST_CMN_RES_F_PIPED | 547 _BCM_BST_CMN_RES_F_RES_EGR); 548 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_PORT_ALL(unit)); 549 pres->num_instance = NUM_XPE(unit); 550 stat_mem = MMU_THDU_BST_PORTm; 551 stat_reg = INVALIDr; 552 stat_field = Q_COUNTf; 553 554 /* Get the mem attributes(Max idx) from the first child, 555 * which could be used for other instances. 556 * Note: In HX5, XPE 0/Pipe 0 instance valid for all memories(Ing/Egr). 557 */ 558 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 559 idx_count = soc_mem_index_max(unit, child_mem) + 1; 560 561 stat_reg = INVALIDr; 562 /* Threshold info count and Resource allocation */ 563 granularity = 8; /* UC Port Shared Thd is 8 cell granularity */ 564 total_thd_count = NUM_XPE(unit) * NUM_PIPE(unit) * idx_count; 565 thd_mem = MMU_THDU_CONFIG_PORTm; 566 thd_field = WM_MAX_THRESHOLDf; 567 for (i = 0; i < NUM_PIPE(unit); i++) { 568 _BCM_BST_THRESHOLD_INFO_N(pres, SOC_MEM_UNIQUE_ACC(unit, thd_mem)[i], 569 INVALIDr, thd_field, granularity, i); 570 } 571 _BCM_BST_PROFILE_INFO(pres, INVALIDm, OP_UC_PORT_BST_THRESHOLDr, BST_STATf); 572 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, 573 "bst egr port pool shared ucast"); 574 /* Stat info count and Resource allocation */ 575 total_stat_count = total_thd_count; 576 _BCM_BST_STAT_INFO2(pres, stat_mem, stat_mem, 577 stat_reg, stat_reg, stat_field); 578 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, 579 "bst egr port pool shared ucast"); 580 pres->index_min = 0; 581 pres->index_max = total_stat_count - 1; 582 /* EGRESS - Resources end */ 583 584 /* bcmBstStatIdRQEQueue */ 585 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdRQEQueue); 586 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 587 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_RES_EGR); 588 pres->num_instance = NUM_XPE(unit); 589 idx_count = 11; 590 pres->threshold_adj = -1; 591 stat_mem = INVALIDm; 592 stat_reg = MMU_THDR_DB_BST_STAT_PRIQr; 593 stat_field = BST_STATf; 594 595 /* Threshold info count and Resource allocation */ 596 granularity = 1; 597 total_thd_count = NUM_XPE(unit) * idx_count; /* No per pipe copy */ 598 thd_reg = MMU_THDR_DB_BST_THRESHOLD_PRIQr; 599 thd_field = BST_THRf; 600 _BCM_BST_THRESHOLD_INFO(pres, INVALIDm, thd_reg, thd_field, granularity); 601 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst RQE queue"); 602 /* Stat info count and Resource allocation */ 603 total_stat_count = total_thd_count; /* No per pipe copy */ 604 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 605 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst RQE queue"); 606 pres->index_min = 0; 607 pres->index_max = total_stat_count - 1; 608 609 /* bcmBstStatIdRQEPool */ 610 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdRQEPool); 611 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 612 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_RES_EGR); 613 pres->num_instance = NUM_XPE(unit); 614 idx_count = 4; 615 pres->threshold_adj = -1; 616 stat_mem = INVALIDm; 617 stat_reg = MMU_THDR_DB_BST_STAT_SPr; 618 stat_field = BST_STATf; 619 620 /* Threshold info count and Resource allocation */ 621 granularity = 1; 622 total_thd_count = NUM_XPE(unit) * idx_count; /* No per pipe copy */ 623 thd_reg = MMU_THDR_DB_BST_THRESHOLD_SPr; 624 thd_field = BST_THRf; 625 _BCM_BST_THRESHOLD_INFO(pres, INVALIDm, thd_reg, thd_field, granularity); 626 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, "bst RQE pool"); 627 /* Stat info count and Resource allocation */ 628 total_stat_count = total_thd_count; /* No per pipe copy */ 629 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 630 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, "bst RQE pool"); 631 pres->index_min = 0; 632 pres->index_max = total_stat_count - 1; 633 634 /* bcmBstStatIdUCQueueGroup */ 635 pres = _BCM_BST_RESOURCE(unit, bcmBstStatIdUCQueueGroup); 636 _BCM_BST_STAT_THRESHOLD_INFO_INIT(pres); 637 _BCM_BST_RESOURCE_FLAG_SET(pres, _BCM_BST_CMN_RES_F_PROFILEID | 638 _BCM_BST_CMN_RES_F_PIPED | 639 _BCM_BST_CMN_RES_F_RES_EGR | 640 _BCM_BST_CMN_RES_F_PORTED); 641 _BCM_BST_RESOURCE_PBMP_SET(pres, PBMP_PORT_ALL(unit)); 642 pres->num_instance = NUM_XPE(unit); 643 stat_mem = MMU_THDU_BST_QGROUPm; 644 stat_reg = INVALIDr; 645 stat_field = Q_COUNTf; 646 647 /* Get the mem attributes(Max idx) from the first child, 648 * * which could be used for other instances. 649 * * Note: In TH, XPE 0/Pipe 0 instance valid for all memories(Ing/Egr). 650 */ 651 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, stat_mem, 0, 0); 652 idx_count = soc_mem_index_max(unit, child_mem) + 1; 653 654 /* Threshold info count and Resource allocation */ 655 granularity = 8; /* UC queue group Thd is 8 cell granularity */ 656 total_thd_count = NUM_XPE(unit) * NUM_PIPE(unit) * idx_count; 657 thd_mem = MMU_THDU_CONFIG_QGROUPm; 658 thd_field = Q_WM_MAX_THRESHOLDf; 659 for (i = 0; i < NUM_PIPE(unit); i++) { 660 _BCM_BST_THRESHOLD_INFO_N(pres, SOC_MEM_UNIQUE_ACC(unit, thd_mem)[i], 661 INVALIDr, thd_field, granularity, i); 662 } 663 _BCM_BST_PROFILE_INFO(pres, INVALIDm, OP_UC_QGROUP_BST_THRESHOLDr, 664 BST_STATf); 665 _BCM_BST_RESOURCE_THRESHOLD_INIT(pres, total_thd_count, 666 "bst unicast queue group"); 667 /* Stat info count and Resource allocation */ 668 total_stat_count = total_thd_count; 669 _BCM_BST_STAT_INFO(pres, stat_mem, stat_reg, stat_field); 670 _BCM_BST_RESOURCE_STAT_INIT(pres, total_stat_count, 671 "bst unicast queue group"); 672 pres->index_min = 0; 673 pres->index_max = total_stat_count - 1; 674 /* EGRESS - Resources end */ 675 return BCM_E_NONE; 676 } 677 #endif /* BCM_HELIX5_SUPPORT */ 678