switch.c (375347B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 #include <soc/debug.h> 8 #include <soc/drv.h> 9 #include <soc/mem.h> 10 #include <bcm/switch.h> 11 #include <bcm/error.h> 12 #include <bcm_int/esw/switch.h> 13 #include <bcm_int/esw/port.h> 14 #include <bcm_int/esw/greyhound.h> 15 #include <bcm_int/esw/greyhound2.h> 16 #include <bcm_int/esw/hurricane3.h> 17 #include <soc/greyhound2.h> 18 19 #if defined(BCM_XGS3_SWITCH_SUPPORT) 20 #include <bcm_int/esw/firebolt.h> 21 #include <bcm_int/esw/trx.h> 22 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 23 #include <bcm_int/esw/triumph.h> 24 #include <bcm_int/esw/link.h> 25 #include <bcm_int/esw/timesync.h> 26 #include <bcm_int/esw/vlan.h> 27 #include <bcm_int/esw/mcast.h> 28 #include <bcm_int/esw/field.h> 29 #include <bcm_int/esw/triumph2.h> 30 #include <bcm_int/esw_dispatch.h> 31 #include <soc/higig.h> 32 #include <soc/scache.h> 33 #include <shared/shr_bprof.h> 34 #include <soc/pbsmh.h> 35 #include <bcm_int/esw/ipmc.h> 36 #include <soc/bradley.h> 37 #include <soc/hurricane3.h> 38 39 #ifdef BCM_WARM_BOOT_SUPPORT 40 #include <bcm_int/esw/stg.h> 41 #include <bcm_int/esw/mpls.h> 42 #include <bcm_int/esw/qos.h> 43 #include <bcm_int/esw/subport.h> 44 #include <bcm_int/esw/tsn.h> 45 #endif 46 #include <bcm_int/esw/stack.h> 47 #include <bcm_int/esw/mirror.h> 48 #include <bcm_int/esw/rx.h> 49 #include <bcm_int/esw/virtual.h> 50 #include <bcm_int/esw/multicast.h> 51 #include <bcm_int/common/time.h> 52 #include <bcm_int/esw/niv.h> 53 #include <bcm_int/esw/stat.h> 54 55 /* Valid RTAG7 hash field selection disable controls */ 56 #define GH2_RTAG7_HASH_CONTROL_IS_VALID(flags) \ 57 ((flags & BCM_HASH_FIELD0_DISABLE_IP4) || \ 58 (flags & BCM_HASH_FIELD1_DISABLE_IP4) || \ 59 (flags & BCM_HASH_FIELD0_DISABLE_IP6) || \ 60 (flags & BCM_HASH_FIELD1_DISABLE_IP6) || \ 61 (flags & BCM_HASH_FIELD0_DISABLE_VXLAN) || \ 62 (flags & BCM_HASH_FIELD1_DISABLE_VXLAN)) 63 64 #define GH2_ICID_LENGTH_BYTES 32 /* ICID length in bytes */ 65 66 /* Helper routines for argument translation */ 67 68 static int 69 _bool_invert(int unit, int arg, int set) 70 { 71 /* Same for both set/get */ 72 return !arg; 73 } 74 75 bcm_switch_binding_t greyhound2_bindings[] = 76 { 77 { bcmSwitchOamHeaderErrorToCpu, 0, 78 CPU_CONTROL_Mr, OAM_HEADER_ERROR_TOCPUf, 79 NULL, 0 }, 80 { bcmSwitchOamUnknownVersionToCpu, 0, 81 CPU_CONTROL_Mr, OAM_UNKNOWN_OPCODE_VERSION_TOCPUf, 82 NULL, 0 }, 83 { bcmSwitchL3SrcBindFailToCpu, 0, 84 CPU_CONTROL_Mr, MAC_BIND_FAILf, 85 NULL, 0}, 86 { bcmSwitchOamUnknownVersionDrop, 0, 87 OAM_DROP_CONTROLr, OAM_UNKNOWN_OPCODE_VERSION_DROPf, 88 NULL, 0}, 89 { bcmSwitchOamUnexpectedPktToCpu, 0, 90 CPU_CONTROL_Mr, OAM_UNEXPECTED_PKT_TOCPUf, 91 NULL, 0}, 92 { bcmSwitchOamCcmToCpu, 0, 93 CCM_COPYTO_CPU_CONTROLr, ERROR_CCM_COPY_TOCPUf, 94 NULL, 0}, 95 { bcmSwitchOamXconCcmToCpu, 0, 96 CCM_COPYTO_CPU_CONTROLr, XCON_CCM_COPY_TOCPUf, 97 NULL, 0}, 98 { bcmSwitchOamXconOtherToCpu, 0, 99 CCM_COPYTO_CPU_CONTROLr, XCON_OTHER_COPY_TOCPUf, 100 NULL, 0}, 101 102 { bcmSwitchSTPBlockedFieldBypass, 0, 103 ING_MISC_CONFIG2r, BLOCKED_PORTS_FP_DISABLEf, 104 NULL, 0 }, 105 { bcmSwitchRemoteLearnTrust, 0, 106 ING_CONFIG_64r, IGNORE_HG_HDR_DONOT_LEARNf, 107 _bool_invert, 0 }, 108 { bcmSwitchRemoteLearnTrust, 0, 109 EGR_CONFIG_1r, IGNORE_HG_HDR_DONOT_LEARNf, 110 _bool_invert, 0 }, 111 { bcmSwitchMldDirectAttachedOnly, 0, 112 ING_CONFIG_64r, MLD_CHECKS_ENABLEf, 113 NULL, soc_feature_igmp_mld_support }, 114 { bcmSwitchSharedVlanL2McastEnable, 0, 115 ING_CONFIG_64r, LOOKUP_L2MC_WITH_FID_IDf, 116 NULL, 0 }, 117 { bcmSwitchMldUcastEnable, 0, 118 ING_CONFIG_64r, MLD_PKTS_UNICAST_IGNOREf, 119 _bool_invert, soc_feature_igmp_mld_support }, 120 { bcmSwitchSharedVlanEnable, 0, 121 ING_CONFIG_64r, SVL_ENABLEf, 122 NULL, 0 }, 123 { bcmSwitchIgmpReservedMcastEnable, 0, 124 ING_CONFIG_64r, IPV4_RESERVED_MC_ADDR_IGMP_ENABLEf, 125 NULL, soc_feature_igmp_mld_support }, 126 { bcmSwitchMldReservedMcastEnable, 0, 127 ING_CONFIG_64r, IPV6_RESERVED_MC_ADDR_MLD_ENABLEf, 128 NULL, soc_feature_igmp_mld_support }, 129 { bcmSwitchIgmpUcastEnable, 0, 130 ING_CONFIG_64r, IGMP_PKTS_UNICAST_IGNOREf, 131 _bool_invert, soc_feature_igmp_mld_support }, 132 { bcmSwitchPortEgressBlockL3, 0, 133 ING_CONFIG_64r, APPLY_EGR_MASK_ON_L3f, 134 NULL, 0 }, 135 { bcmSwitchPortEgressBlockL2, 0, 136 ING_CONFIG_64r, APPLY_EGR_MASK_ON_L2f, 137 NULL, 0 }, 138 { bcmSwitchHgHdrExtLengthEnable, 0, 139 ING_CONFIG_64r, IGNORE_HG_HDR_HDR_EXT_LENf, 140 _bool_invert, 0 }, 141 { bcmSwitchIp4McastL2DestCheck, 0, 142 ING_CONFIG_64r, IPV4_MC_MACDA_CHECK_ENABLEf, 143 NULL, 0 }, 144 { bcmSwitchIp6McastL2DestCheck, 0, 145 ING_CONFIG_64r, IPV6_MC_MACDA_CHECK_ENABLEf, 146 NULL, 0 }, 147 { bcmSwitchMirrorStackMode, 0, 148 ING_CONFIG_64r, STACK_MODEf, 149 NULL, soc_feature_src_modid_blk }, 150 { bcmSwitchMirrorStackMode, 0, 151 EGR_CONFIG_1r, STACK_MODEf, 152 NULL, soc_feature_src_modid_blk }, 153 { bcmSwitchMirrorSrcModCheck, 0, 154 ING_CONFIG_64r, FB_A0_COMPATIBLEf, 155 NULL, soc_feature_src_modid_blk }, 156 157 { bcmSwitchDosAttackToCpu, 0, 158 CPU_CONTROL_0r, DOSATTACK_TOCPUf, 159 NULL, 0 }, 160 { bcmSwitchParityErrorToCpu, 0, 161 CPU_CONTROL_0r, PARITY_ERR_TOCPUf, 162 NULL, soc_feature_parity_err_tocpu }, 163 { bcmSwitchUnknownVlanToCpu, 0, 164 CPU_CONTROL_0r, UVLAN_TOCPUf, 165 NULL, 0 }, 166 { bcmSwitchSourceMacZeroDrop, 0, 167 CPU_CONTROL_0r, MACSA_ALL_ZERO_DROPf, 168 NULL, 0}, 169 { bcmSwitchSharedVlanMismatchToCpu, 0, 170 CPU_CONTROL_0r, PVLAN_VID_MISMATCH_TOCPUf, 171 NULL, 0 }, 172 { bcmSwitchForceForwardFabricTrunk, 0, 173 ING_MISC_CONFIGr, LOCAL_SW_DISABLE_HGTRUNK_RES_ENf, 174 NULL, 0 }, 175 { bcmSwitchFieldMultipathHashSeed, 0, 176 FP_ECMP_HASH_CONTROLr, ECMP_HASH_SALTf, 177 NULL, 0 }, 178 { bcmSwitchCpuToCpuEnable, 0, 179 ING_MISC_CONFIGr, DO_NOT_COPY_FROM_CPU_TO_CPUf, 180 _bool_invert, 0 }, 181 182 { bcmSwitchStationMoveOverLearnLimitToCpu, 0, 183 CPU_CONTROL_1r, MACLMT_STNMV_TOCPUf, 184 NULL, soc_feature_mac_learn_limit }, 185 186 { bcmSwitchBpduInvalidVlanDrop, 0, 187 EGR_CONFIG_1r, BPDU_INVALID_VLAN_DROPf, 188 NULL, soc_feature_igmp_mld_support }, 189 { bcmSwitchMirrorInvalidVlanDrop, 0, 190 EGR_CONFIG_1r, MIRROR_INVALID_VLAN_DROPf, 191 NULL, soc_feature_igmp_mld_support }, 192 { bcmSwitchMcastFloodBlocking, 0, 193 IGMP_MLD_PKT_CONTROLr, PFM_RULE_APPLYf, 194 NULL, soc_feature_igmp_mld_support }, 195 196 { bcmSwitchIpmcTtl1ToCpu, 0, 197 CPU_CONTROL_1r, IPMC_TTL1_ERR_TOCPUf, 198 NULL, 0 }, 199 { bcmSwitchL3UcastTtl1ToCpu, 0, 200 CPU_CONTROL_1r, L3UC_TTL1_ERR_TOCPUf, 201 NULL, 0 }, 202 { bcmSwitchDhcpLearn, 0, 203 ING_MISC_CONFIG2r, DO_NOT_LEARN_DHCPf, 204 NULL, 0 }, 205 { bcmSwitchUnknownIpmcAsMcast, 0, 206 ING_MISC_CONFIG2r, IPMC_MISS_AS_L2MCf, 207 NULL, 0 }, 208 209 { bcmSwitchMcastUnknownErrToCpu, 0, 210 CPU_CONTROL_1r, MC_INDEX_ERROR_TOCPUf, 211 NULL, 0 }, 212 213 { bcmSwitchDosAttackMACSAEqualMACDA, 0, 214 DOS_CONTROLr, MACSA_EQUALS_MACDA_DROPf, 215 NULL, soc_feature_enhanced_dos_ctrl }, 216 { bcmSwitchDosAttackFlagZeroSeqZero, 0, 217 DOS_CONTROLr, TCP_FLAGS_CTRL0_SEQ0_ENABLEf, 218 NULL, 0 }, 219 { bcmSwitchDosAttackSynFrag, 0, 220 DOS_CONTROLr, TCP_FLAGS_SYN_FRAG_ENABLEf, 221 NULL, 0}, 222 { bcmSwitchDosAttackIcmp, 0, 223 DOS_CONTROL_2r, ICMP_V4_PING_SIZE_ENABLEf, 224 NULL, 0 }, 225 { bcmSwitchDosAttackIcmp, 0, 226 DOS_CONTROL_2r, ICMP_V6_PING_SIZE_ENABLEf, 227 NULL, 0 }, 228 { bcmSwitchDosAttackIcmpV4, 0, 229 DOS_CONTROL_2r, ICMP_V4_PING_SIZE_ENABLEf, 230 NULL, 0 }, 231 { bcmSwitchDosAttackIcmpV6, 0, 232 DOS_CONTROL_2r, ICMP_V6_PING_SIZE_ENABLEf, 233 NULL, 0 }, 234 { bcmSwitchDosAttackIcmpFragments, 0, 235 DOS_CONTROL_2r, ICMP_FRAG_PKTS_ENABLEf, 236 NULL, soc_feature_enhanced_dos_ctrl }, 237 { bcmSwitchDosAttackTcpOffset, 0, 238 DOS_CONTROL_2r, TCP_HDR_OFFSET_EQ1_ENABLEf, 239 NULL, soc_feature_enhanced_dos_ctrl }, 240 { bcmSwitchDosAttackUdpPortsEqual, 0, 241 DOS_CONTROL_2r, UDP_SPORT_EQ_DPORT_ENABLEf, 242 NULL, soc_feature_enhanced_dos_ctrl }, 243 { bcmSwitchDosAttackTcpPortsEqual, 0, 244 DOS_CONTROL_2r, TCP_SPORT_EQ_DPORT_ENABLEf, 245 NULL, soc_feature_enhanced_dos_ctrl }, 246 { bcmSwitchDosAttackTcpFlagsSF, 0, 247 DOS_CONTROL_2r, TCP_FLAGS_SYN_FIN_ENABLEf, 248 NULL, soc_feature_enhanced_dos_ctrl }, 249 { bcmSwitchDosAttackTcpFlagsFUP, 0, 250 DOS_CONTROL_2r, TCP_FLAGS_FIN_URG_PSH_SEQ0_ENABLEf, 251 NULL, soc_feature_enhanced_dos_ctrl }, 252 { bcmSwitchDosAttackTcpHdrPartial, 0, 253 DOS_CONTROL_2r, TCP_HDR_PARTIAL_ENABLEf, 254 NULL, soc_feature_enhanced_dos_ctrl }, 255 { bcmSwitchDosAttackIcmpPktOversize, 0, 256 DOS_CONTROLr, BIG_ICMP_PKT_SIZEf, 257 NULL, 0 }, 258 { bcmSwitchDosAttackIcmpV6PingSize, 0, 259 DOS_CONTROL_2r, BIG_ICMPV6_PKT_SIZEf, 260 NULL, soc_feature_big_icmpv6_ping_check }, 261 { bcmSwitchDosAttackMinTcpHdrSize, 0, 262 DOS_CONTROLr, MIN_TCPHDR_SIZEf, 263 NULL, 0 }, 264 265 { bcmSwitchSrcModBlockMirrorCopy, 0, 266 MIRROR_CONTROLr, SRC_MODID_BLOCK_MIRROR_COPYf, 267 NULL, soc_feature_src_modid_blk }, 268 { bcmSwitchSrcModBlockMirrorOnly, 0, 269 MIRROR_CONTROLr, SRC_MODID_BLOCK_MIRROR_ONLY_PKTf, 270 NULL, soc_feature_src_modid_blk }, 271 272 { bcmSwitchDestPortHGTrunk, 0, 273 ING_MISC_CONFIGr, USE_DEST_PORTf, 274 NULL, soc_feature_port_trunk_index }, 275 276 { bcmSwitchMirrorUnmarked, 0, 277 EGR_CONFIG_1r, RING_MODEf, 278 _bool_invert, 0 }, 279 { bcmSwitchMeterAdjust, 0, 280 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf, 281 NULL, soc_feature_meter_adjust }, 282 { bcmSwitchMeterAdjust, 0, 283 FP_METER_CONTROLr, PACKET_IFG_BYTESf, 284 NULL, soc_feature_meter_adjust }, 285 { bcmSwitchMeterAdjust, 0, 286 EFP_METER_CONTROL_2r, PACKET_IFG_BYTESf, 287 NULL, soc_feature_meter_adjust }, 288 { bcmSwitchMeterAdjust, 0, 289 EGR_COUNTER_CONTROLr, PACKET_IFG_BYTESf, 290 NULL, soc_feature_meter_adjust }, 291 { bcmSwitchMeterAdjust, 0, 292 EGR_COUNTER_CONTROLr, PACKET_IFG_BYTES_2f, 293 NULL, soc_feature_meter_adjust }, 294 { bcmSwitchEgressBlockUcast, 0, 295 ING_MISC_CONFIGr, APPLY_EGR_MASK_ON_UC_ONLYf, 296 NULL, soc_feature_egress_blk_ucast_override }, 297 { bcmSwitchSourceModBlockUcast, 0, 298 ING_MISC_CONFIGr, APPLY_SRCMOD_BLOCK_ON_UC_ONLYf, 299 NULL, soc_feature_src_modid_blk_ucast_override }, 300 { bcmSwitchHgHdrMcastFloodOverride, 0, 301 EGR_CONFIG_1r, FORCE_STATIC_MH_PFMf, 302 NULL, soc_feature_static_pfm }, 303 { bcmSwitchShaperAdjust, 0, 304 EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf, 305 NULL, soc_feature_meter_adjust }, 306 307 { bcmSwitchHgHdrErrToCpu, 0, 308 CPU_CONTROL_1r, HG_HDR_ERROR_TOCPUf, 309 NULL, soc_feature_cpu_proto_prio}, 310 { bcmSwitchClassTagPacketsToCpu, 0, 311 CPU_CONTROL_1r, HG_HDR_TYPE1_TOCPUf, 312 NULL, soc_feature_cpu_proto_prio}, 313 { bcmSwitchSourceModBlockControlOpcode, 0, 314 ING_MISC_CONFIGr, DO_NOT_APPLY_SRCMOD_BLOCK_ON_SCf, 315 _bool_invert, soc_feature_src_modid_blk_opcode_override }, 316 { bcmSwitchUnknownMcastToCpu, 0, 317 CPU_CONTROL_1r, UMC_TOCPUf, 318 NULL, 0 }, 319 { bcmSwitchUnknownUcastToCpu, 0, 320 CPU_CONTROL_1r, UUCAST_TOCPUf, 321 NULL, 0 }, 322 { bcmSwitchL2StaticMoveToCpu, 0, 323 CPU_CONTROL_1r, STATICMOVE_TOCPUf, 324 NULL, 0 }, 325 { bcmSwitchL3HeaderErrToCpu, 0, /* compat */ 326 CPU_CONTROL_1r, V4L3ERR_TOCPUf, 327 NULL, 0 }, 328 { bcmSwitchUnknownL3SrcToCpu, 0, 329 CPU_CONTROL_1r, UNRESOLVEDL3SRC_TOCPUf, 330 NULL, 0 }, 331 { bcmSwitchUnknownL3DestToCpu, 0, /* compat */ 332 CPU_CONTROL_1r, V4L3DSTMISS_TOCPUf, 333 NULL, 0 }, 334 { bcmSwitchIpmcPortMissToCpu, 0, 335 CPU_CONTROL_1r, IPMCPORTMISS_TOCPUf, 336 NULL, 0 }, 337 { bcmSwitchIpmcErrorToCpu, 0, 338 CPU_CONTROL_1r, IPMCERR_TOCPUf, 339 NULL, 0 }, 340 { bcmSwitchL2NonStaticMoveToCpu, 0, 341 CPU_CONTROL_1r, NONSTATICMOVE_TOCPUf, 342 NULL, 0 }, 343 { bcmSwitchV6L3ErrToCpu, 0, 344 CPU_CONTROL_1r, V6L3ERR_TOCPUf, 345 NULL, 0 }, 346 { bcmSwitchV6L3DstMissToCpu, 0, 347 CPU_CONTROL_1r, V6L3DSTMISS_TOCPUf, 348 NULL, 0 }, 349 { bcmSwitchV4L3ErrToCpu, 0, 350 CPU_CONTROL_1r, V4L3ERR_TOCPUf, 351 NULL, 0 }, 352 { bcmSwitchV4L3DstMissToCpu, 0, 353 CPU_CONTROL_1r, V4L3DSTMISS_TOCPUf, 354 NULL, 0 }, 355 { bcmSwitchTunnelErrToCpu, 0, 356 CPU_CONTROL_1r, TUNNEL_ERR_TOCPUf, 357 NULL, 0 }, 358 { bcmSwitchMartianAddrToCpu, 0, 359 CPU_CONTROL_1r, MARTIAN_ADDR_TOCPUf, 360 NULL, 0 }, 361 { bcmSwitchL3UcTtlErrToCpu, 0, 362 CPU_CONTROL_1r, L3UC_TTL_ERR_TOCPUf, 363 NULL, 0 }, 364 { bcmSwitchL3SlowpathToCpu, 0, 365 CPU_CONTROL_1r, L3_SLOWPATH_TOCPUf, 366 NULL, 0 }, 367 { bcmSwitchIpmcTtlErrToCpu, 0, 368 CPU_CONTROL_1r, IPMC_TTL_ERR_TOCPUf, 369 NULL, 0 }, 370 { bcmSwitchSampleIngressRandomSeed, 0, 371 SFLOW_ING_RAND_SEEDr, SEEDf, 372 NULL, 0 }, 373 { bcmSwitchSampleEgressRandomSeed, 0, 374 SFLOW_EGR_RAND_SEEDr, SEEDf, 375 NULL, 0 }, 376 { bcmSwitchArpReplyToCpu, 0, 377 PROTOCOL_PKT_CONTROLr, ARP_REPLY_TO_CPUf, 378 NULL, 0 }, 379 { bcmSwitchArpReplyDrop, 0, 380 PROTOCOL_PKT_CONTROLr, ARP_REPLY_DROPf, 381 NULL, 0 }, 382 { bcmSwitchArpRequestToCpu, 0, 383 PROTOCOL_PKT_CONTROLr, ARP_REQUEST_TO_CPUf, 384 NULL, 0 }, 385 { bcmSwitchArpRequestDrop, 0, 386 PROTOCOL_PKT_CONTROLr, ARP_REQUEST_DROPf, 387 NULL, 0 }, 388 { bcmSwitchNdPktToCpu, 0, 389 PROTOCOL_PKT_CONTROLr, ND_PKT_TO_CPUf, 390 NULL, 0 }, 391 { bcmSwitchNdPktDrop, 0, 392 PROTOCOL_PKT_CONTROLr, ND_PKT_DROPf, 393 NULL, 0 }, 394 { bcmSwitchDhcpPktToCpu, 0, 395 PROTOCOL_PKT_CONTROLr, DHCP_PKT_TO_CPUf, 396 NULL, 0 }, 397 { bcmSwitchDhcpPktDrop, 0, 398 PROTOCOL_PKT_CONTROLr, DHCP_PKT_DROPf, 399 NULL, 0 }, 400 { bcmSwitchDosAttackSipEqualDip, 0, 401 DOS_CONTROLr, DROP_IF_SIP_EQUALS_DIPf, 402 NULL, 0 }, 403 { bcmSwitchDosAttackV4FirstFrag, 0, 404 DOS_CONTROLr, IPV4_FIRST_FRAG_CHECK_ENABLEf, 405 NULL, 0 }, 406 { bcmSwitchNonIpL3ErrToCpu, 0, 407 CPU_CONTROL_1r, NIP_L3ERR_TOCPUf, 408 NULL, soc_feature_nip_l3_err_tocpu }, 409 { bcmSwitchSourceRouteToCpu, 0, 410 CPU_CONTROL_1r, SRCROUTE_TOCPUf, 411 NULL, 0 }, 412 413 { bcmSwitchL3MtuFailToCpu, 0, 414 CPU_CONTROL_1r, L3_MTU_FAIL_TOCPUf, 415 NULL, soc_feature_l3mtu_fail_tocpu }, 416 { bcmSwitchIpmcSameVlanL3Route, 0, 417 EGR_CONFIG_1r, IPMC_ROUTE_SAME_VLANf, 418 NULL, soc_feature_l3}, 419 { bcmSwitchIpmcSameVlanPruning, 0, 420 MISCCONFIGr, IPMC_IND_MODEf, 421 _bool_invert, 0 }, 422 423 { bcmSwitchPrioDropToCpu, 0, 424 CPU_CONTROL_0r, DOT1P_ADMITTANCE_DROP_TOCPUf, 425 NULL, soc_feature_niv}, 426 { bcmSwitchNivPrioDropToCpu, 0, 427 CPU_CONTROL_0r, DOT1P_ADMITTANCE_DROP_TOCPUf, 428 NULL, soc_feature_niv}, 429 { bcmSwitchNivInterfaceMissToCpu, 0, 430 CPU_CONTROL_0r, NIV_FORWARDING_DROP_TOCPUf, 431 NULL, soc_feature_niv}, 432 { bcmSwitchNivRpfFailToCpu, 0, 433 CPU_CONTROL_0r, NIV_RPF_CHECK_FAIL_TOCPUf, 434 NULL, soc_feature_niv}, 435 { bcmSwitchNivTagInvalidToCpu, 0, 436 CPU_CONTROL_0r, VNTAG_FORMAT_DROP_TOCPUf, 437 NULL, soc_feature_niv}, 438 { bcmSwitchNivTagDropToCpu, 0, 439 CPU_CONTROL_0r, DISCARD_VNTAG_PRESENT_TOCPUf, 440 NULL, soc_feature_niv}, 441 { bcmSwitchNivUntagDropToCpu, 0, 442 CPU_CONTROL_0r, DISCARD_VNTAG_NOT_PRESENT_TOCPUf, 443 NULL, soc_feature_niv}, 444 { bcmSwitchV6L3LocalLinkDrop, 0, 445 ING_MISC_CONFIG2r, IPV6_SIP_LINK_LOCAL_DROPf, 446 NULL, 0}, 447 448 { bcmSwitchExtenderInterfaceMissToCpu, 0, 449 CPU_CONTROL_0r, NIV_FORWARDING_DROP_TOCPUf, 450 NULL, soc_feature_port_extension}, 451 { bcmSwitchExtenderRpfFailToCpu, 0, 452 CPU_CONTROL_0r, NIV_RPF_CHECK_FAIL_TOCPUf, 453 NULL, soc_feature_port_extension}, 454 { bcmSwitchEtagDropToCpu, 0, 455 CPU_CONTROL_0r, DISCARD_VNTAG_PRESENT_TOCPUf, 456 NULL, soc_feature_port_extension}, 457 { bcmSwitchNonEtagDropToCpu, 0, 458 CPU_CONTROL_0r, DISCARD_VNTAG_NOT_PRESENT_TOCPUf, 459 NULL, soc_feature_port_extension}, 460 461 { bcmSwitchL3SrcBindMissToCpu, 0, 462 CPU_CONTROL_Mr, MAC_IP_BIND_LOOKUP_MISS_TOCPUf, 463 NULL, 0}, 464 { bcmSwitchTimesyncUnknownVersionToCpu, 0, 465 CPU_CONTROL_Mr, UNKNOWN_1588_VERSION_TO_CPUf, 466 NULL, 0}, 467 { bcmSwitchTimesyncIngressVersion, 0, 468 ING_1588_PARSING_CONTROLr, VERSION_CONTROLf, 469 NULL, 0}, 470 { bcmSwitchTimesyncEgressVersion, 0, 471 EGR_1588_PARSING_CONTROLr, VERSION_CONTROLf, 472 NULL, 0}, 473 { bcmSwitchProxySrcKnockout, 0, 474 IHG_LOOKUPr, REMOVE_MH_SRC_PORTf, 475 NULL, soc_feature_proxy_port_property}, 476 { bcmSwitchDosAttackV6MinFragEnable, 0, 477 DOS_CONTROL_2r, IPV6_MIN_FRAG_SIZE_ENABLEf, 478 NULL, soc_feature_enhanced_dos_ctrl}, 479 { bcmSwitchDosAttackV6MinFragSize, 0, 480 IPV6_MIN_FRAG_SIZEr, PKT_LENGTHf, 481 NULL, soc_feature_enhanced_dos_ctrl}, 482 483 { bcmSwitchL3InterfaceUrpfEnable, 0, 484 ING_CONFIG_64r, L3IIF_URPF_SELECTf, 485 NULL, soc_feature_urpf}, 486 { bcmSwitchL3UrpfFailToCpu, 0, 487 CPU_CONTROL_1r, URPF_MISS_TOCPUf, 488 NULL, soc_feature_urpf}, 489 { bcmSwitchL3UrpfRouteEnable, 0, 490 L3_DEFIP_RPF_CONTROLr, DEFIP_RPF_ENABLEf, 491 NULL, soc_feature_urpf}, 492 493 { bcmSwitchMimlEncapInnerEthertype, 0, 494 EGR_MIML_ETHERTYPEr, ETHERTYPEf, 495 NULL, soc_feature_miml}, 496 { bcmSwitchSTPDisabledFieldBypass, 0, 497 ING_MISC_CONFIG2r, DISABLED_PORTS_FP_DISABLEf, 498 NULL, 0 }, 499 500 /* RTAG7 related control setting */ 501 { bcmSwitchHashField0Ip6FlowLabel, 0, 502 RTAG7_HASH_CONTROLr, ENABLE_FLOW_LABEL_IPV6_Af, 503 NULL, 0}, 504 { bcmSwitchHashField1Ip6FlowLabel, 0, 505 RTAG7_HASH_CONTROLr, ENABLE_FLOW_LABEL_IPV6_Bf, 506 NULL, 0}, 507 { bcmSwitchHashNivSrcIfEtagSvidSelect0, 0, 508 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_0_SELECT_Af, 509 NULL, 0 }, 510 { bcmSwitchHashNivSrcIfEtagSvidSelect1, 0, 511 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_0_SELECT_Bf, 512 NULL, 0 }, 513 { bcmSwitchHashNivDstIfEtagVidSelect0, 0, 514 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_1_SELECT_Af, 515 NULL, 0 }, 516 { bcmSwitchHashNivDstIfEtagVidSelect1, 0, 517 RTAG7_HASH_CONTROL_2r, RTAG7_HASH_BIN_1_SELECT_Bf, 518 NULL, 0 }, 519 { bcmSwitchHashField0OverlayCntagRpidEnable, 0, 520 RTAG7_HASH_CONTROL_2r, ENABLE_BIN_12_OVERLAY_Af, 521 NULL, 0}, 522 { bcmSwitchHashField1OverlayCntagRpidEnable, 0, 523 RTAG7_HASH_CONTROL_2r, ENABLE_BIN_12_OVERLAY_Bf, 524 NULL, 0}, 525 { bcmSwitchMacroFlowHashUseMSB, 0, 526 RTAG7_HASH_CONTROL_2r, MACRO_FLOW_HASH_BYTE_SELf, 527 NULL, 0}, 528 { bcmSwitchHashSctpL4Port, 0, 529 ING_SCTP_CONTROLr, PARSE_SCTPf, 530 NULL, 0}, 531 { bcmSwitchEcmpMacroFlowHashEnable, 0, 532 RTAG7_HASH_SELr, USE_FLOW_SEL_ECMPf, 533 NULL, 0}, 534 /*Doing the same config as bcmSwitchEcmpMacroFlowHashEnable*/ 535 { bcmSwitchHashUseFlowSelEcmp, 0, 536 RTAG7_HASH_SELr, USE_FLOW_SEL_ECMPf, 537 NULL, 0}, 538 { bcmSwitchHashUseFlowSelTrunkUc , 0, 539 RTAG7_HASH_SELr, USE_FLOW_SEL_TRUNK_UCf, 540 NULL, 0}, 541 { bcmSwitchHashUseFlowSelLbidNonUnicast, 0, 542 RTAG7_HASH_SELr, USE_FLOW_SEL_LBID_NONUCf, 543 NULL, soc_feature_gh2_rtag7}, 544 { bcmSwitchHashUseFlowSelLbidUnicast, 0, 545 RTAG7_HASH_SELr, USE_FLOW_SEL_LBID_UCf, 546 NULL, soc_feature_gh2_rtag7}, 547 { bcmSwitchHashUseFlowSelHigigTrunkNonUnicast, 0, 548 RTAG7_HASH_SELr, USE_FLOW_SEL_HG_TRUNK_NONUCf, 549 NULL, soc_feature_gh2_rtag7}, 550 { bcmSwitchHashUseFlowSelHigigTrunkUnicast, 0, 551 RTAG7_HASH_SELr, USE_FLOW_SEL_HG_TRUNK_UCf, 552 NULL, soc_feature_gh2_rtag7}, 553 { bcmSwitchHashUseFlowSelHigigTrunkFailover, 0, 554 RTAG7_HASH_SELr, USE_FLOW_SEL_HG_TRUNK_FAILOVERf, 555 NULL, soc_feature_gh2_rtag7}, 556 { bcmSwitchHashUseFlowSelTrunkNonUnicast, 0, 557 RTAG7_HASH_SELr, USE_FLOW_SEL_TRUNK_NONUCf, 558 NULL, soc_feature_gh2_rtag7}, 559 { bcmSwitchHashUseFlowSelEntropy, 0, 560 RTAG7_HASH_SELr, USE_FLOW_SEL_ENTROPYf, 561 NULL, soc_feature_gh2_rtag7}, 562 { bcmSwitchHashUseFlowSelVxlanEcmp, 0, 563 RTAG7_HASH_SELr, USE_FLOW_SEL_VXLAN_ECMPf, 564 NULL, soc_feature_gh2_rtag7}, 565 { bcmSwitchHashUseFlowSelRoce2Ecmp, 0, 566 RTAG7_HASH_SELr, USE_FLOW_SEL_ROCEV2_ECMPf, 567 NULL, soc_feature_rroce}, 568 { bcmSwitchHashField0Roce1FlowLabel, 0, 569 RTAG7_HASH_CONTROLr, ENABLE_ROCEV1_GRH_FLOW_LABEL_Af, 570 NULL, soc_feature_rroce}, 571 { bcmSwitchHashField1Roce1FlowLabel, 0, 572 RTAG7_HASH_CONTROLr, ENABLE_ROCEV1_GRH_FLOW_LABEL_Bf, 573 NULL, soc_feature_rroce}, 574 { bcmSwitchHashField0Roce2FlowLabel, 0, 575 RTAG7_HASH_CONTROLr, ENABLE_ROCEV2_FLOW_LABEL_Af, 576 NULL, soc_feature_rroce}, 577 { bcmSwitchHashField1Roce2FlowLabel, 0, 578 RTAG7_HASH_CONTROLr, ENABLE_ROCEV2_FLOW_LABEL_Bf, 579 NULL, soc_feature_rroce}, 580 { bcmSwitchTunnelIp4IdShared, 0, 581 EGR_TUNNEL_ID_MASKr, SHARED_FRAG_ID_ENABLEf, 582 NULL, 0}, 583 }; 584 585 586 int 587 bcm_gh2_switch_control_port_binding_set(int unit, 588 bcm_port_t port, 589 bcm_switch_control_t type, 590 int arg, int *found) 591 { 592 uint64 oval64, val64; 593 int i; 594 bcm_switch_binding_t *b; 595 uint32 max; 596 int fval, fwidth, prt, idx; 597 598 *found = 0; 599 for (i = 0; i < COUNTOF(greyhound2_bindings); i++) { 600 b = &greyhound2_bindings[i]; 601 if (b->type == type) { 602 /* We don't check the b->chip here since the table is specific for Greyhound*/ 603 if (b->feature && !soc_feature(unit, b->feature)) { 604 continue; 605 } 606 if (!soc_reg_field_valid(unit, b->reg, b->field)) { 607 continue; 608 } 609 if (b->xlate_arg) { 610 if ((fval = (b->xlate_arg)(unit, arg, 1)) < 0) { 611 return fval; 612 } 613 } else { 614 fval = arg; 615 } 616 /* Negative values should be treated as errors */ 617 if (fval < 0) { 618 return BCM_E_PARAM; 619 } 620 if ((b->reg == PROTOCOL_PKT_CONTROLr) || 621 (b->reg == IGMP_MLD_PKT_CONTROLr)) { 622 int index; 623 624 BCM_IF_ERROR_RETURN 625 (_bcm_esw_port_tab_get(unit, port, 626 PROTOCOL_PKT_INDEXf, &index)); 627 prt = index; 628 idx = 0; 629 } else { 630 prt = port; 631 idx = 0; 632 } 633 634 fwidth = soc_reg_field_length(unit, b->reg, b->field); 635 if (fwidth < 32) { 636 max = (1 << fwidth) - 1; 637 } else { 638 max = -1; 639 } 640 BCM_IF_ERROR_RETURN(soc_reg_get(unit, b->reg, prt, idx, &val64)); 641 oval64 = val64; 642 soc_reg64_field32_set(unit, b->reg, &val64, b->field, 643 ((uint32)fval > max) ? max : (uint32)fval); 644 if (COMPILER_64_NE(val64, oval64)) { 645 BCM_IF_ERROR_RETURN(soc_reg_set(unit, b->reg, prt, idx, val64)); 646 } 647 648 *found = 1; 649 } 650 } 651 return BCM_E_NONE; 652 } 653 654 int 655 bcm_gh2_switch_control_port_binding_get(int unit, 656 bcm_port_t port, 657 bcm_switch_control_t type, 658 int *arg, int *found) 659 { 660 uint64 val64; 661 int i; 662 bcm_switch_binding_t *b; 663 int prt, idx; 664 665 *found = 0; 666 667 for (i = 0; i < COUNTOF(greyhound2_bindings); i++) { 668 b = &greyhound2_bindings[i]; 669 if (b->type == type) { 670 if (b->feature && !soc_feature(unit, b->feature)) { 671 continue; 672 } 673 if (!SOC_REG_IS_VALID(unit, b->reg)) { 674 continue; 675 } 676 677 if (!soc_reg_field_valid(unit, b->reg, b->field)) { 678 continue; 679 } 680 if ((b->reg == PROTOCOL_PKT_CONTROLr) || 681 (b->reg == IGMP_MLD_PKT_CONTROLr)) { 682 int index; 683 684 BCM_IF_ERROR_RETURN 685 (_bcm_esw_port_tab_get(unit, port, 686 PROTOCOL_PKT_INDEXf, &index)); 687 prt = index; 688 idx = 0; 689 } else { 690 prt = port; 691 idx = 0; 692 } 693 BCM_IF_ERROR_RETURN(soc_reg_get(unit, b->reg, prt, idx, &val64)); 694 *arg = soc_reg64_field32_get(unit, b->reg, val64, b->field); 695 696 if (b->xlate_arg) { 697 *arg = (b->xlate_arg)(unit, *arg, 0); 698 } 699 *found = 1; 700 break; 701 } 702 } 703 return BCM_E_NONE; 704 } 705 706 /* 707 * Function: 708 * bcm_gh2_switch_rtag7_selectcontrol_set 709 * Description: 710 * Set the enhanced (aka rtag 7) hash select control. 711 * Parameters: 712 * unit - StrataSwitch PCI device unit number (driver internal). 713 * arg - BCM_HASH_CONTROL* 714 * Returns: 715 * BCM_E_xxxx 716 */ 717 int 718 bcm_gh2_switch_rtag7_selectcontrol_set(int unit, int arg) 719 { 720 uint64 hash_control; 721 uint32 val; 722 723 /* 724 * GH2 only supports IPv4, IPv6 and VXLAN hash field selection disable 725 * control. IP over IP, GRE, MPLS and MIM are not supported. 726 */ 727 if (arg) { 728 if (!GH2_RTAG7_HASH_CONTROL_IS_VALID(arg)) { 729 return BCM_E_PARAM; 730 } 731 } 732 733 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &hash_control)); 734 735 /* IPv4 for hash block A/B */ 736 val = (arg & BCM_HASH_FIELD0_DISABLE_IP4 ) ? 1 : 0; 737 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 738 DISABLE_HASH_IPV4_Af, val); 739 740 val = (arg & BCM_HASH_FIELD1_DISABLE_IP4) ? 1 : 0; 741 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 742 DISABLE_HASH_IPV4_Bf, val); 743 744 /* IPv6 for hash block A/B */ 745 val = (arg & BCM_HASH_FIELD0_DISABLE_IP6) ? 1 : 0; 746 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 747 DISABLE_HASH_IPV6_Af, val); 748 749 val = (arg & BCM_HASH_FIELD1_DISABLE_IP6) ? 1 : 0; 750 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 751 DISABLE_HASH_IPV6_Bf, val); 752 753 /* VXLAN for hash block A/B */ 754 val = (arg & BCM_HASH_FIELD0_DISABLE_VXLAN ) ? 1 : 0; 755 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 756 DISABLE_HASH_VXLAN_Af, val); 757 758 val = (arg & BCM_HASH_FIELD1_DISABLE_VXLAN) ? 1 : 0; 759 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 760 DISABLE_HASH_VXLAN_Bf, val); 761 762 BCM_IF_ERROR_RETURN(WRITE_RTAG7_HASH_CONTROLr(unit, hash_control)); 763 764 return BCM_E_NONE; 765 } 766 767 /* 768 * Function: 769 * bcm_gh2_switch_rtag7_selectcontrol_get 770 * Description: 771 * Get the current enhanced (aka rtag 7) hash control settings. 772 * Parameters: 773 * unit - StrataSwitch PCI device unit number (driver internal). 774 * arg - Pointer to where the retrieved value will be written. 775 * Returns: 776 * BCM_E_xxxx 777 */ 778 int 779 bcm_gh2_switch_rtag7_selectcontrol_get(int unit, int *arg) 780 { 781 uint64 hash_control; 782 uint32 val; 783 784 *arg = 0; 785 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &hash_control)); 786 787 /* IPv4 for hash block A/B */ 788 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 789 DISABLE_HASH_IPV4_Af); 790 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_IP4; 791 792 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 793 DISABLE_HASH_IPV4_Bf); 794 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_IP4; 795 796 /* IPv6 for hash block A/B */ 797 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 798 DISABLE_HASH_IPV6_Af); 799 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_IP6; 800 801 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 802 DISABLE_HASH_IPV6_Bf); 803 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_IP6; 804 805 /* VXLAN for hash block A/B */ 806 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 807 DISABLE_HASH_VXLAN_Af); 808 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_VXLAN; 809 810 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 811 DISABLE_HASH_VXLAN_Bf); 812 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_VXLAN; 813 814 return BCM_E_NONE; 815 } 816 817 /* 818 * Function: 819 * bcmi_gh2_switch_rtag7_extended_roce_selectcontrol_set 820 * Description: 821 * Set the enhanced (aka rtag 7) hash select control. 822 * Parameters: 823 * unit - StrataSwitch PCI device unit number (driver internal). 824 * arg - BCM_HASH_CONTROL* 825 * Returns: 826 * BCM_E_xxxx 827 */ 828 int 829 bcmi_gh2_switch_rtag7_extended_roce_selectcontrol_set(int unit, int arg) 830 { 831 uint64 hash_control; 832 uint32 val; 833 834 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &hash_control)); 835 836 val = (arg & BCM_HASH_FIELD0_DISABLE_ROCE1) ? 1 : 0; 837 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 838 DISABLE_HASH_ROCEV1_Af, val); 839 840 val = (arg & BCM_HASH_FIELD1_DISABLE_ROCE1) ? 1 : 0; 841 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 842 DISABLE_HASH_ROCEV1_Bf, val); 843 844 val = (arg & BCM_HASH_FIELD0_DISABLE_ROCE2_IP4) ? 1 : 0; 845 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 846 DISABLE_HASH_ROCEV2_IPV4_Af, val); 847 848 val = (arg & BCM_HASH_FIELD1_DISABLE_ROCE2_IP4) ? 1 : 0; 849 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 850 DISABLE_HASH_ROCEV2_IPV4_Bf, val); 851 852 val = (arg & BCM_HASH_FIELD0_DISABLE_ROCE2_IP6) ? 1 : 0; 853 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 854 DISABLE_HASH_ROCEV2_IPV6_Af, val); 855 856 val = (arg & BCM_HASH_FIELD1_DISABLE_ROCE2_IP6) ? 1 : 0; 857 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 858 DISABLE_HASH_ROCEV2_IPV6_Bf, val); 859 860 861 BCM_IF_ERROR_RETURN(WRITE_RTAG7_HASH_CONTROLr(unit, hash_control)); 862 863 return BCM_E_NONE; 864 } 865 866 867 /* 868 * Function: 869 * bcmi_gh2_switch_rtag7_extended_roce_selectcontrol_get 870 * Description: 871 * Get the current enhanced (aka rtag 7) hash control settings. 872 * Parameters: 873 * unit - StrataSwitch PCI device unit number (driver internal). 874 * arg - Pointer to where the retrieved value will be written. 875 * Returns: 876 * BCM_E_xxxx 877 */ 878 int 879 bcmi_gh2_switch_rtag7_extended_roce_selectcontrol_get(int unit, int *arg) 880 { 881 uint64 hash_control; 882 uint32 val; 883 884 *arg = 0; 885 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &hash_control)); 886 887 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 888 DISABLE_HASH_ROCEV1_Af); 889 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_ROCE1; 890 891 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 892 DISABLE_HASH_ROCEV1_Bf); 893 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_ROCE1; 894 895 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 896 DISABLE_HASH_ROCEV2_IPV4_Af); 897 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_ROCE2_IP4; 898 899 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 900 DISABLE_HASH_ROCEV2_IPV4_Bf); 901 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_ROCE2_IP4; 902 903 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 904 DISABLE_HASH_ROCEV2_IPV6_Af); 905 if (val) *arg |= BCM_HASH_FIELD0_DISABLE_ROCE2_IP6; 906 907 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 908 DISABLE_HASH_ROCEV2_IPV6_Bf); 909 if (val) *arg |= BCM_HASH_FIELD1_DISABLE_ROCE2_IP6; 910 911 return BCM_E_NONE; 912 } 913 914 915 /* 916 * Function: 917 * bcm_gh2_switch_rtag7_fieldconfig_set 918 * Description: 919 * Set the enhanced (aka rtag 7) hash mode (A0/A1/B0/B1) config settings. 920 * Parameters: 921 * unit - StrataSwitch PCI device unit number (driver internal). 922 * type - The desired configuration parameter to set. 923 * arg - BCM_HASH_CONTROL* 924 * Returns: 925 * BCM_E_xxxx 926 */ 927 int 928 bcm_gh2_switch_rtag7_fieldconfig_set(int unit, 929 bcm_switch_control_t type, int arg) 930 { 931 soc_reg_t reg; 932 soc_field_t field; 933 uint64 hash_control; 934 uint32 val; 935 936 reg = RTAG7_HASH_CONTROL_3r; 937 switch (type) { 938 case bcmSwitchHashField0Config: 939 field = HASH_A0_FUNCTION_SELECTf; 940 break; 941 case bcmSwitchHashField0Config1: 942 field = HASH_A1_FUNCTION_SELECTf; 943 break; 944 case bcmSwitchHashField1Config: 945 field = HASH_B0_FUNCTION_SELECTf; 946 break; 947 case bcmSwitchHashField1Config1: 948 field = HASH_B1_FUNCTION_SELECTf; 949 break; 950 case bcmSwitchMacroFlowHashFieldConfig: 951 reg = RTAG7_HASH_CONTROL_2r; 952 field = MACRO_FLOW_HASH_FUNC_SELf; 953 break; 954 default: 955 return BCM_E_UNAVAIL; 956 } 957 switch (arg) { 958 case BCM_HASH_FIELD_CONFIG_CRC16XOR8: 959 val = ENHANCE_XGS3_HASH_CRC16XOR8; 960 break; 961 case BCM_HASH_FIELD_CONFIG_CRC16XOR4: 962 val = ENHANCE_XGS3_HASH_CRC16XOR4; 963 break; 964 case BCM_HASH_FIELD_CONFIG_CRC16XOR2: 965 val = ENHANCE_XGS3_HASH_CRC16XOR2; 966 break; 967 case BCM_HASH_FIELD_CONFIG_CRC16XOR1: 968 val = ENHANCE_XGS3_HASH_CRC16XOR1; 969 break; 970 case BCM_HASH_FIELD_CONFIG_CRC16: 971 val = ENHANCE_XGS3_HASH_CRC16; 972 break; 973 case BCM_HASH_FIELD_CONFIG_XOR16: 974 val = ENHANCE_XGS3_HASH_XOR16; 975 break; 976 case BCM_HASH_FIELD_CONFIG_CRC16CCITT: 977 val = ENHANCE_XGS3_HASH_CRC16CCITT; 978 break; 979 case BCM_HASH_FIELD_CONFIG_CRC32LO: 980 val = ENHANCE_XGS3_HASH_CRC32LO; 981 break; 982 case BCM_HASH_FIELD_CONFIG_CRC32HI: 983 val = ENHANCE_XGS3_HASH_CRC32HI; 984 break; 985 default: 986 val = 0; 987 break; 988 } 989 990 if (!SOC_REG_FIELD_VALID(unit, reg, field)) { 991 return BCM_E_UNAVAIL; 992 } 993 994 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &hash_control)); 995 soc_reg64_field32_set(unit, reg, &hash_control, field, val); 996 BCM_IF_ERROR_RETURN(soc_reg_set(unit, reg, REG_PORT_ANY, 0, hash_control)); 997 998 return BCM_E_NONE; 999 } 1000 1001 /* 1002 * Function: 1003 * bcm_gh2_switch_rtag7_fieldconfig_get 1004 * Description: 1005 * Get the current enhanced (aka rtag 7) hash mode (A0/A1/B0/B1) config settings. 1006 * Parameters: 1007 * unit - StrataSwitch PCI device unit number (driver internal). 1008 * type - The desired configuration parameter to retrieve. 1009 * arg - Pointer to where the retrieved value will be written. 1010 * Returns: 1011 * BCM_E_xxxx 1012 */ 1013 int 1014 bcm_gh2_switch_rtag7_fieldconfig_get(int unit, 1015 bcm_switch_control_t type, int *arg) 1016 { 1017 soc_reg_t reg; 1018 soc_field_t field; 1019 uint64 hash_control; 1020 uint32 val; 1021 1022 reg = RTAG7_HASH_CONTROL_3r; 1023 switch (type) { 1024 case bcmSwitchHashField0Config: 1025 field = HASH_A0_FUNCTION_SELECTf; 1026 break; 1027 case bcmSwitchHashField0Config1: 1028 field = HASH_A1_FUNCTION_SELECTf; 1029 break; 1030 case bcmSwitchHashField1Config: 1031 field = HASH_B0_FUNCTION_SELECTf; 1032 break; 1033 case bcmSwitchHashField1Config1: 1034 field = HASH_B1_FUNCTION_SELECTf; 1035 break; 1036 case bcmSwitchMacroFlowHashFieldConfig: 1037 reg = RTAG7_HASH_CONTROL_2r; 1038 field = MACRO_FLOW_HASH_FUNC_SELf; 1039 break; 1040 default: 1041 return BCM_E_UNAVAIL; 1042 } 1043 1044 if (!SOC_REG_FIELD_VALID(unit, reg, field)) { 1045 return BCM_E_UNAVAIL; 1046 } 1047 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &hash_control)); 1048 val = soc_reg64_field32_get(unit, reg, hash_control, field); 1049 1050 switch (val) { 1051 case ENHANCE_XGS3_HASH_CRC16XOR8: 1052 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR8; 1053 break; 1054 case ENHANCE_XGS3_HASH_CRC16XOR4: 1055 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR4; 1056 break; 1057 case ENHANCE_XGS3_HASH_CRC16XOR2: 1058 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR2; 1059 break; 1060 case ENHANCE_XGS3_HASH_CRC16XOR1: 1061 *arg = BCM_HASH_FIELD_CONFIG_CRC16XOR1; 1062 break; 1063 case ENHANCE_XGS3_HASH_CRC16: 1064 *arg = BCM_HASH_FIELD_CONFIG_CRC16; 1065 break; 1066 case ENHANCE_XGS3_HASH_XOR16: 1067 *arg = BCM_HASH_FIELD_CONFIG_XOR16; 1068 break; 1069 case ENHANCE_XGS3_HASH_CRC16CCITT: 1070 *arg = BCM_HASH_FIELD_CONFIG_CRC16CCITT; 1071 break; 1072 case ENHANCE_XGS3_HASH_CRC32LO: 1073 *arg = BCM_HASH_FIELD_CONFIG_CRC32LO; 1074 break; 1075 case ENHANCE_XGS3_HASH_CRC32HI: 1076 *arg = BCM_HASH_FIELD_CONFIG_CRC32HI; 1077 break; 1078 default: 1079 *arg = 0; 1080 break; 1081 } 1082 1083 return BCM_E_NONE; 1084 } 1085 1086 _hash_bmap_t hash_select_gh2_common[] = 1087 { 1088 { BCM_HASH_FIELD_DSTMOD, 0x0001 }, 1089 { BCM_HASH_FIELD_DSTPORT, 0x0002 }, 1090 { BCM_HASH_FIELD_SRCMOD, 0x0004 }, 1091 { BCM_HASH_FIELD_SRCPORT, 0x0008 } 1092 }; 1093 1094 _hash_bmap_t hash_select_ip4_gh2[] = 1095 { 1096 { BCM_HASH_FIELD_PROTOCOL, 0x0010 }, 1097 { BCM_HASH_FIELD_DSTL4, 0x0020 }, 1098 { BCM_HASH_FIELD_SRCL4, 0x0040 }, 1099 { BCM_HASH_FIELD_VLAN, 0x0080 }, 1100 { BCM_HASH_FIELD_IP4DST_LO, 0x0100 }, 1101 { BCM_HASH_FIELD_IP4DST_HI, 0x0200 }, 1102 { BCM_HASH_FIELD_IP4SRC_LO, 0x0400 }, 1103 { BCM_HASH_FIELD_IP4SRC_HI, 0x0800 } 1104 }; 1105 1106 _hash_bmap_t hash_select_ip6_gh2[] = 1107 { 1108 { BCM_HASH_FIELD_NXT_HDR, 0x0010 }, 1109 { BCM_HASH_FIELD_DSTL4, 0x0020 }, 1110 { BCM_HASH_FIELD_SRCL4, 0x0040 }, 1111 { BCM_HASH_FIELD_VLAN, 0x0080 }, 1112 { BCM_HASH_FIELD_IP6DST_LO, 0x0100 }, 1113 { BCM_HASH_FIELD_IP6DST_HI, 0x0200 }, 1114 { BCM_HASH_FIELD_IP6SRC_LO, 0x0400 }, 1115 { BCM_HASH_FIELD_IP6SRC_HI, 0x0800 } 1116 }; 1117 1118 _hash_bmap_t hash_select_l2_gh2[] = 1119 { 1120 { BCM_HASH_FIELD_VLAN, 0x0010 }, 1121 { BCM_HASH_FIELD_ETHER_TYPE,0x0020 }, 1122 { BCM_HASH_FIELD_MACDA_LO, 0x0040 }, 1123 { BCM_HASH_FIELD_MACDA_MI, 0x0080 }, 1124 { BCM_HASH_FIELD_MACDA_HI, 0x0100 }, 1125 { BCM_HASH_FIELD_MACSA_LO, 0x0200 }, 1126 { BCM_HASH_FIELD_MACSA_MI, 0x0400 }, 1127 { BCM_HASH_FIELD_MACSA_HI, 0x0800 } 1128 }; 1129 1130 _hash_bmap_t hash_select_unknown_gh2[] = 1131 { 1132 { BCM_HASH_FIELD_LOAD_BALANCE,0x0010 } 1133 }; 1134 1135 _hash_bmap_t hash_field_payload_control_gh2[] = 1136 { 1137 { BCM_HASH_SELECT_INNER_L2, 0x0000 }, 1138 { BCM_HASH_SELECT_INNER_L3, 0x0001 } 1139 }; 1140 1141 _hash_bmap_t hash_field_ipv6_collapse_control_gh2[] = 1142 { 1143 { BCM_HASH_IP6_COLLAPSE_XOR, 0x0000}, 1144 { BCM_HASH_IP6_COLLAPSE_LSB, 0x0001} 1145 }; 1146 1147 _hash_bmap_t hash_select_roce1_gh2[] = 1148 { 1149 { BCM_HASH_ROCE_FIELD_BTH_DSTQP_COLLAPSED, 0x0010 }, 1150 { BCM_HASH_ROCE_FIELD_BTH_PARTITION_KEY, 0x0020 }, 1151 { BCM_HASH_ROCE_FIELD_VLAN, 0x0040 }, 1152 { BCM_HASH_ROCE_FIELD_MACDA_LO, 0x0080 }, 1153 { BCM_HASH_ROCE_FIELD_MACDA_MI, 0x0100 }, 1154 { BCM_HASH_ROCE_FIELD_MACDA_HI, 0x0200 }, 1155 { BCM_HASH_ROCE_FIELD_MACSA_LO, 0x0400 }, 1156 { BCM_HASH_ROCE_FIELD_MACSA_MI, 0x0800 }, 1157 { BCM_HASH_ROCE_FIELD_MACSA_HI, 0x1000 } 1158 }; 1159 1160 _hash_bmap_t hash_select_roce2_ip4_gh2[] = 1161 { 1162 { BCM_HASH_ROCE_FIELD_BTH_DSTQP_COLLAPSED, 0x0010 }, 1163 { BCM_HASH_ROCE_FIELD_BTH_PARTITION_KEY, 0x0020 }, 1164 { BCM_HASH_ROCE_FIELD_DSTL4, 0x0040 }, 1165 { BCM_HASH_ROCE_FIELD_SRCL4, 0x0080 }, 1166 { BCM_HASH_ROCE_FIELD_VLAN, 0x0100 }, 1167 { BCM_HASH_ROCE_FIELD_IP4DST_LO, 0x0200 }, 1168 { BCM_HASH_ROCE_FIELD_IP4DST_HI, 0x0400 }, 1169 { BCM_HASH_ROCE_FIELD_IP4SRC_LO, 0x0800 }, 1170 { BCM_HASH_ROCE_FIELD_IP4SRC_HI, 0x1000 } 1171 }; 1172 1173 _hash_bmap_t hash_select_roce2_ip6_gh2[] = 1174 { 1175 { BCM_HASH_ROCE_FIELD_BTH_DSTQP_COLLAPSED, 0x0010 }, 1176 { BCM_HASH_ROCE_FIELD_BTH_PARTITION_KEY, 0x0020 }, 1177 { BCM_HASH_ROCE_FIELD_DSTL4, 0x0040 }, 1178 { BCM_HASH_ROCE_FIELD_SRCL4, 0x0080 }, 1179 { BCM_HASH_ROCE_FIELD_VLAN, 0x0100 }, 1180 { BCM_HASH_ROCE_FIELD_IP6DST_LO, 0x0200 }, 1181 { BCM_HASH_ROCE_FIELD_IP6DST_HI, 0x0400 }, 1182 { BCM_HASH_ROCE_FIELD_IP6SRC_LO, 0x0800 }, 1183 { BCM_HASH_ROCE_FIELD_IP6SRC_HI, 0x1000 } 1184 }; 1185 1186 1187 1188 _hash_fieldselect_t hash_select_info_gh2[] = 1189 { 1190 { bcmSwitchHashIP4Field0, 1191 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1192 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Af}, 1193 { bcmSwitchHashIP4Field1, 1194 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1195 RTAG7_HASH_FIELD_BMAP_1r, IPV4_FIELD_BITMAP_Bf}, 1196 { bcmSwitchHashIP4TcpUdpField0, 1197 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1198 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_2r, IPV4_TCP_UDP_FIELD_BITMAP_Af}, 1199 { bcmSwitchHashIP4TcpUdpField1, 1200 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1201 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_2r, IPV4_TCP_UDP_FIELD_BITMAP_Bf}, 1202 { bcmSwitchHashIP4TcpUdpPortsEqualField0, 1203 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1204 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_1r, 1205 IPV4_TCP_UDP_SRC_EQ_DST_FIELD_BITMAP_Af}, 1206 { bcmSwitchHashIP4TcpUdpPortsEqualField1, 1207 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1208 RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_1r, 1209 IPV4_TCP_UDP_SRC_EQ_DST_FIELD_BITMAP_Bf}, 1210 { bcmSwitchHashIP6Field0, 1211 hash_select_ip6_gh2, COUNTOF(hash_select_ip6_gh2), 1212 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Af}, 1213 { bcmSwitchHashIP6Field1, 1214 hash_select_ip6_gh2, COUNTOF(hash_select_ip6_gh2), 1215 RTAG7_HASH_FIELD_BMAP_2r, IPV6_FIELD_BITMAP_Bf}, 1216 { bcmSwitchHashIP6TcpUdpField0, 1217 hash_select_ip6_gh2, COUNTOF(hash_select_ip6_gh2), 1218 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_2r, IPV6_TCP_UDP_SCTP_FIELD_BITMAP_Af}, 1219 { bcmSwitchHashIP6TcpUdpField1, 1220 hash_select_ip6_gh2, COUNTOF(hash_select_ip6_gh2), 1221 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_2r, IPV6_TCP_UDP_SCTP_FIELD_BITMAP_Bf}, 1222 { bcmSwitchHashIP6TcpUdpPortsEqualField0, 1223 hash_select_ip6_gh2, COUNTOF(hash_select_ip6_gh2), 1224 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_1r, 1225 IPV6_TCP_UDP_SCTP_SRC_EQ_DST_FIELD_BITMAP_Af}, 1226 { bcmSwitchHashIP6TcpUdpPortsEqualField1, 1227 hash_select_ip6_gh2, COUNTOF(hash_select_ip6_gh2), 1228 RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_1r, 1229 IPV6_TCP_UDP_SCTP_SRC_EQ_DST_FIELD_BITMAP_Bf}, 1230 { bcmSwitchHashL2Field0, 1231 hash_select_l2_gh2, COUNTOF(hash_select_l2_gh2), 1232 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Af}, 1233 { bcmSwitchHashL2Field1, 1234 hash_select_l2_gh2, COUNTOF(hash_select_l2_gh2), 1235 RTAG7_HASH_FIELD_BMAP_3r, L2_FIELD_BITMAP_Bf}, 1236 { bcmSwitchHashHG2UnknownField0, 1237 hash_select_unknown_gh2, COUNTOF(hash_select_unknown_gh2), 1238 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Af}, 1239 { bcmSwitchHashHG2UnknownField1, 1240 hash_select_unknown_gh2, COUNTOF(hash_select_unknown_gh2), 1241 RTAG7_HASH_FIELD_BMAP_5r, UNKNOWN_PPD_FIELD_BITMAP_Bf}, 1242 { bcmSwitchHashL2VxlanField0, 1243 hash_select_l2_gh2, COUNTOF(hash_select_l2_gh2), 1244 RTAG7_VXLAN_PAYLOAD_L2_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L2_BITMAP_Af}, 1245 { bcmSwitchHashL2VxlanField1, 1246 hash_select_l2_gh2, COUNTOF(hash_select_l2_gh2), 1247 RTAG7_VXLAN_PAYLOAD_L2_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L2_BITMAP_Bf}, 1248 { bcmSwitchHashL3VxlanField0, 1249 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1250 RTAG7_VXLAN_PAYLOAD_L3_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L3_BITMAP_Af}, 1251 { bcmSwitchHashL3VxlanField1, 1252 hash_select_ip4_gh2, COUNTOF(hash_select_ip4_gh2), 1253 RTAG7_VXLAN_PAYLOAD_L3_HASH_FIELD_BMAPr, VXLAN_PAYLOAD_L3_BITMAP_Bf}, 1254 { bcmSwitchHashRoce1Field0, 1255 hash_select_roce1_gh2, COUNTOF(hash_select_roce1_gh2), 1256 RTAG7_ROCEV1_HASH_FIELD_BMAPr, ROCEV1_FIELD_BITMAP_Af}, 1257 { bcmSwitchHashRoce1Field1, 1258 hash_select_roce1_gh2, COUNTOF(hash_select_roce1_gh2), 1259 RTAG7_ROCEV1_HASH_FIELD_BMAPr, ROCEV1_FIELD_BITMAP_Bf}, 1260 { bcmSwitchHashRoce2IP4Field0, 1261 hash_select_roce2_ip4_gh2, COUNTOF(hash_select_roce2_ip4_gh2), 1262 RTAG7_ROCEV2_HASH_FIELD_BMAPr, ROCEV2_IPV4_FIELD_BITMAP_Af}, 1263 { bcmSwitchHashRoce2IP4Field1, 1264 hash_select_roce2_ip4_gh2, COUNTOF(hash_select_roce2_ip4_gh2), 1265 RTAG7_ROCEV2_HASH_FIELD_BMAPr, ROCEV2_IPV4_FIELD_BITMAP_Bf}, 1266 { bcmSwitchHashRoce2IP6Field0, 1267 hash_select_roce2_ip6_gh2, COUNTOF(hash_select_roce2_ip6_gh2), 1268 RTAG7_ROCEV2_HASH_FIELD_BMAPr, ROCEV2_IPV6_FIELD_BITMAP_Af}, 1269 { bcmSwitchHashRoce2IP6Field1, 1270 hash_select_roce2_ip6_gh2, COUNTOF(hash_select_roce2_ip6_gh2), 1271 RTAG7_ROCEV2_HASH_FIELD_BMAPr, ROCEV2_IPV6_FIELD_BITMAP_Bf}, 1272 { 0 } 1273 }; 1274 1275 _hash_fieldselect_t hash_select_control_gh2[] = 1276 { 1277 { bcmSwitchHashVxlanPayloadSelect0, 1278 hash_field_payload_control_gh2, COUNTOF(hash_field_payload_control_gh2), 1279 RTAG7_HASH_CONTROLr, VXLAN_PAYLOAD_HASH_SELECT_Af}, 1280 { bcmSwitchHashVxlanPayloadSelect1, 1281 hash_field_payload_control_gh2, COUNTOF(hash_field_payload_control_gh2), 1282 RTAG7_HASH_CONTROLr, VXLAN_PAYLOAD_HASH_SELECT_Bf}, 1283 { bcmSwitchHashIP6AddrCollapseSelect0, 1284 hash_field_ipv6_collapse_control_gh2, COUNTOF(hash_field_ipv6_collapse_control_gh2), 1285 RTAG7_HASH_CONTROL_2r, IPV6_COLLAPSED_ADDR_SELECT_Af}, 1286 { bcmSwitchHashIP6AddrCollapseSelect1, 1287 hash_field_ipv6_collapse_control_gh2, COUNTOF(hash_field_ipv6_collapse_control_gh2), 1288 RTAG7_HASH_CONTROL_2r, IPV6_COLLAPSED_ADDR_SELECT_Bf}, 1289 { 0 } 1290 }; 1291 1292 /* 1293 * Function: 1294 * bcm_gh2_switch_rtag7_fieldselect_set 1295 * Description: 1296 * Set the enhanced (aka rtag 7) field select settings. 1297 * Parameters: 1298 * unit - StrataSwitch PCI device unit number (driver internal). 1299 * type - The desired configuration parameter to set. 1300 * arg - BCM_HASH_CONTROL* 1301 * Returns: 1302 * BCM_E_xxxx 1303 */ 1304 int 1305 bcm_gh2_switch_rtag7_fieldselect_set(int unit, 1306 bcm_switch_control_t type, int arg) 1307 { 1308 uint32 hash_control; 1309 uint64 hash_control_64; 1310 int i, j, count, common_count; 1311 uint32 flags = 0; 1312 _hash_fieldselect_t *info, *base_info; 1313 _hash_bmap_t *common_bmap; 1314 1315 common_bmap = hash_select_gh2_common; 1316 common_count = COUNTOF(hash_select_gh2_common); 1317 base_info = hash_select_info_gh2; 1318 count = COUNTOF(hash_select_info_gh2); 1319 1320 for (i = 0; i < count; i++) { 1321 info = base_info + i; 1322 if (info->type != type) { 1323 continue; 1324 } 1325 1326 for (j = 0; j < common_count; j++) { 1327 if (common_bmap[j].flag & arg) { 1328 flags |= common_bmap[j].hw_map; 1329 } 1330 } 1331 1332 for (j = 0; j < info->size; j++) { 1333 if (info->map[j].flag & arg) { 1334 flags |= info->map[j].hw_map; 1335 } 1336 } 1337 if (SOC_REG_IS_ABOVE_32(unit, info->reg)) { 1338 COMPILER_64_ZERO(hash_control_64); 1339 BCM_IF_ERROR_RETURN(soc_reg64_get(unit, info->reg, 1340 REG_PORT_ANY, 0, 1341 &hash_control_64)); 1342 soc_reg64_field32_set(unit, info->reg, 1343 &hash_control_64, info->field, flags); 1344 BCM_IF_ERROR_RETURN 1345 (soc_reg64_set(unit, info->reg, REG_PORT_ANY, 1346 0, hash_control_64)); 1347 } else { 1348 BCM_IF_ERROR_RETURN 1349 (soc_reg32_get(unit, info->reg, 1350 REG_PORT_ANY, 0, &hash_control)); 1351 soc_reg_field_set(unit, info->reg, 1352 &hash_control, info->field, flags); 1353 BCM_IF_ERROR_RETURN 1354 (soc_reg32_set(unit, info->reg, REG_PORT_ANY, 1355 0, hash_control)); 1356 } 1357 } 1358 1359 return BCM_E_NONE; 1360 } 1361 1362 /* 1363 * Function: 1364 * bcm_gh2_switch_rtag7_fieldselect_get 1365 * Description: 1366 * Get the current enhanced (aka rtag 7) field select settings. 1367 * Parameters: 1368 * unit - StrataSwitch PCI device unit number (driver internal). 1369 * type - The desired configuration parameter to retrieve. 1370 * arg - Pointer to where the retrieved value will be written. 1371 * Returns: 1372 * BCM_E_xxxx 1373 */ 1374 int 1375 bcm_gh2_switch_rtag7_fieldselect_get(int unit, 1376 bcm_switch_control_t type, int *arg) 1377 { 1378 uint32 hash_control; 1379 uint64 hash_control_64; 1380 int i, j, count, common_count; 1381 uint32 flags; 1382 _hash_fieldselect_t *info, *base_info; 1383 _hash_bmap_t *common_bmap; 1384 1385 common_bmap = hash_select_gh2_common; 1386 common_count = COUNTOF(hash_select_gh2_common); 1387 base_info = hash_select_info_gh2; 1388 count = COUNTOF(hash_select_info_gh2); 1389 1390 for (i = 0; i < count; i++) { 1391 info = base_info + i; 1392 if (info->type != type) { 1393 continue; 1394 } 1395 1396 if (SOC_REG_IS_ABOVE_32(unit, info->reg)) { 1397 COMPILER_64_ZERO(hash_control_64); 1398 BCM_IF_ERROR_RETURN 1399 (soc_reg64_get(unit, info->reg, 1400 REG_PORT_ANY, 0, &hash_control_64)); 1401 flags = soc_reg64_field32_get(unit, info->reg, 1402 hash_control_64, info->field); 1403 } else { 1404 BCM_IF_ERROR_RETURN 1405 (soc_reg32_get(unit, info->reg, 1406 REG_PORT_ANY, 0, &hash_control)); 1407 flags = soc_reg_field_get(unit, info->reg, 1408 hash_control, info->field); 1409 } 1410 1411 *arg = 0; 1412 for (j = 0; j < common_count; j++) { 1413 if (common_bmap[j].hw_map & flags) { 1414 *arg |= common_bmap[j].flag; 1415 } 1416 } 1417 1418 for (j = 0; j < info->size; j++) { 1419 if (info->map[j].hw_map & flags) { 1420 *arg |= info->map[j].flag; 1421 } 1422 } 1423 } 1424 1425 return BCM_E_NONE; 1426 } 1427 1428 /* 1429 * Function: 1430 * bcm_gh2_switch_rtag7_field_control_set 1431 * Description: 1432 * Set RTAG7 field controls for hash blocks. 1433 * Parameters: 1434 * unit - unit no. 1435 * type - switch control enum type. 1436 * arg - BCM_HASH_CONTROL* 1437 * Returns: 1438 * BCM_E_xxxx 1439 */ 1440 int 1441 bcm_gh2_switch_rtag7_field_control_set(int unit, 1442 bcm_switch_control_t type, int arg) 1443 { 1444 uint64 hash_control; 1445 int cnt, i; 1446 uint32 count = 0; 1447 _hash_fieldselect_t *base_info = NULL, *info; 1448 1449 base_info = hash_select_control_gh2; 1450 count = COUNTOF(hash_select_control_gh2) - 1; 1451 1452 if (0 == count) { 1453 return BCM_E_UNAVAIL; 1454 } 1455 1456 for (i = 0; i < count; i++) { 1457 info = base_info + i; 1458 if (info->type != type) { 1459 continue; 1460 } 1461 1462 for (cnt = 0; cnt < info->size; cnt++) { 1463 if (info->map[cnt].flag == arg) { 1464 break; 1465 } 1466 } 1467 if (info->size == cnt) { 1468 return BCM_E_PARAM; 1469 } 1470 1471 BCM_IF_ERROR_RETURN( 1472 soc_reg_get(unit, info->reg, REG_PORT_ANY, 0, &hash_control)); 1473 soc_reg64_field32_set(unit, info->reg, 1474 &hash_control, info->field, info->map[cnt].hw_map); 1475 BCM_IF_ERROR_RETURN( 1476 soc_reg_set(unit, info->reg, REG_PORT_ANY, 0, hash_control)); 1477 } 1478 1479 return BCM_E_NONE; 1480 } 1481 1482 /* 1483 * Function: 1484 * bcm_gh2_switch_rtag7_field_control_get 1485 * Description: 1486 * Get RTAG7 field controls for hash blocks. 1487 * Parameters: 1488 * unit - unit no. 1489 * type - switch control enum type. 1490 * arg - Pointer to where the retrieved value will be written. 1491 * Returns: 1492 * BCM_E_xxxx 1493 */ 1494 int 1495 bcm_gh2_switch_rtag7_field_control_get(int unit, 1496 bcm_switch_control_t type, int *arg) 1497 { 1498 uint64 hash_control; 1499 uint32 val; 1500 int cnt, i; 1501 uint32 count = 0; 1502 _hash_fieldselect_t *base_info = NULL, *info; 1503 1504 base_info = hash_select_control_gh2; 1505 count = COUNTOF(hash_select_control_gh2) - 1; 1506 1507 if (0 == count) { 1508 return BCM_E_UNAVAIL; 1509 } 1510 1511 for (i = 0; i < count; i++) { 1512 info = base_info + i; 1513 if (info->type != type) { 1514 continue; 1515 } 1516 1517 BCM_IF_ERROR_RETURN( 1518 soc_reg_get(unit, info->reg, REG_PORT_ANY, 0, &hash_control)); 1519 1520 val = soc_reg64_field32_get(unit, info->reg, hash_control, info->field); 1521 1522 for (cnt = 0; cnt < info->size; cnt++) { 1523 if (info->map[cnt].hw_map == val) { 1524 break; 1525 } 1526 } 1527 if (info->size == cnt) { 1528 return BCM_E_INTERNAL; 1529 } 1530 1531 *arg = info->map[cnt].flag; 1532 1533 } 1534 1535 return BCM_E_NONE; 1536 } 1537 1538 /* 1539 * Function: 1540 * bcm_gh2_switch_rtag7_symmetric_hash_control_set 1541 * Description: 1542 * Set the current symmetric (aka rtag 7) hash control settings for Ip4, Ip6 packet. 1543 * Parameters: 1544 * unit - StrataSwitch PCI device unit number (driver internal). 1545 * arg - Symmetric hash control setting values (BCM_SYMMETRIC_HASH_XXX). 1546 * Returns: 1547 * BCM_E_xxxx 1548 */ 1549 int 1550 bcm_gh2_switch_rtag7_symmetric_hash_control_set(int unit, int arg) 1551 { 1552 uint64 hash_control; 1553 uint32 valid_bit_mask, val; 1554 1555 valid_bit_mask = (BCM_SYMMETRIC_HASH_0_IP4_ENABLE | 1556 BCM_SYMMETRIC_HASH_1_IP4_ENABLE | 1557 BCM_SYMMETRIC_HASH_0_IP6_ENABLE | 1558 BCM_SYMMETRIC_HASH_1_IP6_ENABLE | 1559 BCM_SYMMETRIC_HASH_0_SUPPRESS_UNIDIR_FIELD_ENABLE | 1560 BCM_SYMMETRIC_HASH_1_SUPPRESS_UNIDIR_FIELD_ENABLE); 1561 1562 if (arg & (~valid_bit_mask)) { 1563 return BCM_E_PARAM; 1564 } 1565 1566 BCM_IF_ERROR_RETURN( 1567 soc_reg_get(unit, RTAG7_HASH_CONTROLr, REG_PORT_ANY, 0, &hash_control)); 1568 1569 val = (arg & BCM_SYMMETRIC_HASH_0_IP4_ENABLE ) ? 1 : 0; 1570 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 1571 SYMMETRIC_HASH_IPV4_Af, val); 1572 1573 val = (arg & BCM_SYMMETRIC_HASH_1_IP4_ENABLE) ? 1 : 0; 1574 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 1575 SYMMETRIC_HASH_IPV4_Bf, val); 1576 1577 val = (arg & BCM_SYMMETRIC_HASH_0_IP6_ENABLE) ? 1 : 0; 1578 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 1579 SYMMETRIC_HASH_IPV6_Af, val); 1580 1581 val = (arg & BCM_SYMMETRIC_HASH_1_IP6_ENABLE) ? 1 : 0; 1582 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 1583 SYMMETRIC_HASH_IPV6_Bf, val); 1584 1585 val = (arg & BCM_SYMMETRIC_HASH_0_SUPPRESS_UNIDIR_FIELD_ENABLE) ? 1 : 0; 1586 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 1587 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Af, val); 1588 1589 val = (arg & BCM_SYMMETRIC_HASH_1_SUPPRESS_UNIDIR_FIELD_ENABLE) ? 1 : 0; 1590 soc_reg64_field32_set(unit, RTAG7_HASH_CONTROLr, &hash_control, 1591 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Bf, val); 1592 1593 BCM_IF_ERROR_RETURN( 1594 soc_reg_set(unit, RTAG7_HASH_CONTROLr, REG_PORT_ANY, 0, hash_control)); 1595 1596 return BCM_E_NONE; 1597 } 1598 1599 /* 1600 * Function: 1601 * bcm_gh2_switch_rtag7_symmetric_hash_control_get 1602 * Description: 1603 * Get the current symmetric (aka rtag 7) hash control settings for Ip4, Ip6 packet. 1604 * Parameters: 1605 * unit - StrataSwitch PCI device unit number (driver internal). 1606 * arg - Pointer to the symmetric hash control setting values (BCM_SYMMETRIC_HASH_XXX). 1607 * Returns: 1608 * BCM_E_xxxx 1609 */ 1610 int 1611 bcm_gh2_switch_rtag7_symmetric_hash_control_get(int unit, int *arg) 1612 { 1613 uint64 hash_control; 1614 uint32 val; 1615 1616 *arg = 0; 1617 BCM_IF_ERROR_RETURN( 1618 soc_reg_get(unit, RTAG7_HASH_CONTROLr, REG_PORT_ANY, 0, &hash_control)); 1619 1620 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 1621 SYMMETRIC_HASH_IPV4_Af); 1622 if (val) *arg |= BCM_SYMMETRIC_HASH_0_IP4_ENABLE; 1623 1624 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 1625 SYMMETRIC_HASH_IPV4_Bf); 1626 if (val) *arg |= BCM_SYMMETRIC_HASH_1_IP4_ENABLE; 1627 1628 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 1629 SYMMETRIC_HASH_IPV6_Af); 1630 if (val) *arg |= BCM_SYMMETRIC_HASH_0_IP6_ENABLE; 1631 1632 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 1633 SYMMETRIC_HASH_IPV6_Bf); 1634 if (val) *arg |= BCM_SYMMETRIC_HASH_1_IP6_ENABLE; 1635 1636 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 1637 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Af); 1638 if (val) *arg |= BCM_SYMMETRIC_HASH_0_SUPPRESS_UNIDIR_FIELD_ENABLE; 1639 1640 val = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, hash_control, 1641 SYMMETRIC_HASH_SUPPRESS_UNIDIR_FIELDS_Bf); 1642 if (val) *arg |= BCM_SYMMETRIC_HASH_1_SUPPRESS_UNIDIR_FIELD_ENABLE; 1643 1644 return BCM_E_NONE; 1645 } 1646 1647 /* 1648 * Enhanced hash bit selection/offset helper function 1649 */ 1650 STATIC int 1651 _bcm_gh2_hash_offset(int unit, bcm_port_t port, bcm_switch_control_t type, 1652 hash_offset_info_t *info) 1653 { 1654 int index = -1; 1655 1656 /* 1657 * For gh2, the index is got from PORT_TAB.RTAG7_PORT_PROFILE_INDEX or from 1658 * LPORT_PROFILE_TABLE.RTAG7_PORT_PROFILE_INDEX 1659 * 1660 * The index field will be ignored for LPORTs. 1661 */ 1662 if (BCM_GPORT_IS_SET(port)) { 1663 info->idx = -1; 1664 } else { 1665 BCM_IF_ERROR_RETURN( 1666 _bcm_esw_port_tab_get(unit, port, RTAG7_PORT_PROFILE_INDEXf, &index)); 1667 info->idx = index; 1668 } 1669 1670 switch (type) { 1671 case bcmSwitchTrunkHashSet0UnicastOffset: 1672 info->hash_concat = 0; 1673 info->sub_f = SUB_SEL_TRUNK_UCf; 1674 info->offset_f = OFFSET_TRUNK_UCf; 1675 info->concat_f = CONCATENATE_HASH_FIELDS_TRUNK_UCf; 1676 info->regmem = RTAG7_PORT_BASED_HASHm; 1677 break; 1678 case bcmSwitchTrunkHashSet0NonUnicastOffset: 1679 info->hash_concat = 0; 1680 info->sub_f = SUB_SEL_TRUNK_NONUCf; 1681 info->offset_f = OFFSET_TRUNK_NONUCf; 1682 info->concat_f = CONCATENATE_HASH_FIELDS_TRUNK_NONUCf; 1683 info->regmem = RTAG7_PORT_BASED_HASHm; 1684 break; 1685 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 1686 info->hash_concat = 0; 1687 info->sub_f = SUB_SEL_HG_TRUNK_UCf; 1688 info->offset_f = OFFSET_HG_TRUNK_UCf; 1689 info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNK_UCf; 1690 info->regmem = RTAG7_PORT_BASED_HASHm; 1691 break; 1692 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 1693 info->hash_concat = 0; 1694 info->sub_f = SUB_SEL_HG_TRUNK_NONUCf; 1695 info->offset_f = OFFSET_HG_TRUNK_NONUCf; 1696 info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNK_NONUCf; 1697 info->regmem = RTAG7_PORT_BASED_HASHm; 1698 break; 1699 case bcmSwitchFabricTrunkFailoverHashOffset: 1700 info->hash_concat = 0; 1701 info->sub_f = SUB_SEL_HG_TRUNK_FAILOVERf; 1702 info->offset_f = OFFSET_HG_TRUNK_FAILOVERf; 1703 info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNK_FAILOVERf; 1704 info->regmem = RTAG7_PORT_BASED_HASHm; 1705 break; 1706 case bcmSwitchECMPVxlanHashOffset: 1707 info->hash_concat = 0; 1708 info->sub_f = SUB_SEL_VXLAN_ECMPf; 1709 info->offset_f = OFFSET_VXLAN_ECMPf; 1710 info->concat_f = CONCATENATE_HASH_FIELDS_VXLAN_ECMPf; 1711 info->regmem = RTAG7_PORT_BASED_HASHm; 1712 break; 1713 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 1714 info->hash_concat = 0; 1715 info->sub_f = SUB_SEL_LBID_UCf; 1716 info->offset_f = OFFSET_LBID_UCf; 1717 info->concat_f = CONCATENATE_HASH_FIELDS_LBID_UCf; 1718 info->regmem = RTAG7_PORT_BASED_HASHm; 1719 break; 1720 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 1721 info->hash_concat = 0; 1722 info->sub_f = SUB_SEL_LBID_NONUCf; 1723 info->offset_f = OFFSET_LBID_NONUCf; 1724 info->concat_f = CONCATENATE_HASH_FIELDS_LBID_NONUCf; 1725 info->regmem = RTAG7_PORT_BASED_HASHm; 1726 break; 1727 case bcmSwitchECMPHashSet0Offset: 1728 info->hash_concat = 0; 1729 info->sub_f = SUB_SEL_ECMPf; 1730 info->offset_f = OFFSET_ECMPf; 1731 info->concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 1732 info->regmem = RTAG7_PORT_BASED_HASHm; 1733 break; 1734 case bcmSwitchEntropyHashSet0Offset: 1735 info->hash_concat = 0; 1736 info->sub_f = SUB_SEL_ENTROPYf; 1737 info->offset_f = OFFSET_ENTROPYf; 1738 info->concat_f = CONCATENATE_HASH_FIELDS_ENTROPYf; 1739 info->regmem = RTAG7_PORT_BASED_HASHm; 1740 break; 1741 case bcmSwitchEcmpRoce2HashOffset: 1742 info->hash_concat = 0; 1743 info->sub_f = SUB_SEL_ROCEV2_ECMPf; 1744 info->offset_f = OFFSET_ROCEV2_ECMPf; 1745 info->concat_f = CONCATENATE_HASH_FIELDS_ROCEV2_ECMPf; 1746 info->regmem = RTAG7_PORT_BASED_HASHm; 1747 break; 1748 case bcmSwitchTrunkFailoverHashOffset: 1749 case bcmSwitchFabricTrunkDynamicHashOffset: 1750 case bcmSwitchTrunkDynamicHashOffset: 1751 case bcmSwitchEcmpDynamicHashOffset: 1752 case bcmSwitchFabricTrunkResilientHashOffset: 1753 case bcmSwitchTrunkResilientHashOffset: 1754 case bcmSwitchEcmpResilientHashOffset: 1755 case bcmSwitchECMPUnderlayVxlanHashOffset: 1756 case bcmSwitchECMPL2GreHashOffset: 1757 case bcmSwitchECMPUnderlayL2GreHashOffset: 1758 case bcmSwitchECMPTrillHashOffset: 1759 case bcmSwitchECMPUnderlayTrillHashOffset: 1760 case bcmSwitchECMPMplsHashOffset: 1761 case bcmSwitchVirtualPortDynamicHashOffset: 1762 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 1763 case bcmSwitchECMPOverlayHashOffset: 1764 case bcmSwitchECMPUnderlayHashSet0Offset: 1765 default: 1766 return BCM_E_UNAVAIL; 1767 } 1768 return BCM_E_NONE; 1769 } 1770 1771 /* 1772 * Function: 1773 * bcm_gh2_switch_rtag7_fieldoffset_set 1774 * Description: 1775 * Set the enhanced (aka rtag 7) bits selection offset. 1776 * Parameters: 1777 * unit - StrataSwitch PCI device unit number (driver internal). 1778 * port - port 1779 * type - The desired configuration parameter to set. 1780 * arg - BCM_HASH_CONTROL* 1781 * Returns: 1782 * BCM_E_xxxx 1783 */ 1784 int 1785 bcm_gh2_switch_rtag7_fieldoffset_set(int unit, bcm_port_t port, 1786 bcm_switch_control_t type, int arg) 1787 { 1788 int sub_field_width[8]; 1789 int total_width, offset = -1, i; 1790 hash_offset_info_t info; 1791 uint32 hash_control_entry[SOC_MAX_MEM_WORDS]; 1792 int field_count = 0; 1793 soc_field_t fields[3]; 1794 uint32 values[3]; 1795 1796 if (arg < 0) { 1797 return BCM_E_PARAM; 1798 } 1799 1800 BCM_IF_ERROR_RETURN(_bcm_gh2_hash_offset(unit, port, type, &info)); 1801 1802 /* Hash Bits Sub-field Selection - not concatenated */ 1803 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 1804 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 1805 sub_field_width[2] = 4; /* LBN (4bit) */ 1806 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 1807 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 1808 sub_field_width[5] = 8; /* SW1 LBID ( 8 bit) */ 1809 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 1810 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 1811 1812 /* Get hash bits width */ 1813 total_width = 0; 1814 for (i = 0; i < 8; i++) { 1815 total_width += sub_field_width[i]; 1816 } 1817 /* Concatenate if offset value exceeds total hash width */ 1818 if (arg >= total_width) { 1819 info.hash_concat = 1; 1820 } 1821 1822 /* Concatenate if enforced or if offset value exceeds total hash width */ 1823 if ((info.hash_concat == 1) && (info.concat_f != -1)) { 1824 /* Concatenation hash computation order is referenced from 1825 * fb_Irsel1_arch::compute_rtag7_hash 1826 */ 1827 1828 /* Hash Bits Sub-field Selection - concatenated */ 1829 sub_field_width[0] = 64; /* Concat B1,B0,A1,A0(64bit) */ 1830 sub_field_width[1] = 0; /* 0 (Reserved) */ 1831 sub_field_width[2] = 4; /* LBN (4bit) */ 1832 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 1833 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 1834 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 1835 sub_field_width[6] = 0; /* 0 (Reserved) */ 1836 sub_field_width[7] = 0; /* 0 (Reserved) */ 1837 1838 /* Get concatenated hash bits width */ 1839 total_width = 0; 1840 for (i = 0; i < 8; i++) { 1841 total_width += sub_field_width[i]; 1842 } 1843 } 1844 1845 /* Select hash sub select and hash bit offset */ 1846 offset = arg % total_width; 1847 for (i = 0; i < 8; i++) { 1848 offset -= sub_field_width[i]; 1849 if (offset < 0) { 1850 offset += sub_field_width[i]; 1851 break; 1852 } 1853 } 1854 1855 if (SOC_MEM_IS_VALID(unit, info.regmem)) { 1856 /* LPORT Profile */ 1857 if (BCM_GPORT_IS_PROXY(port)) { 1858 fields[0] = info.sub_f; 1859 values[0] = i; 1860 field_count++; 1861 fields[1] = info.offset_f; 1862 values[1] = offset; 1863 field_count++; 1864 if (info.concat_f != -1) { 1865 fields[2] = info.concat_f; 1866 values[2] = info.hash_concat; 1867 field_count++; 1868 } 1869 BCM_IF_ERROR_RETURN 1870 (bcm_esw_port_lport_fields_set(unit, port, 1871 LPORT_PROFILE_RTAG7_TAB, 1872 field_count, fields, values)); 1873 } else { 1874 SOC_IF_ERROR_RETURN 1875 (soc_mem_read(unit, info.regmem, 1876 MEM_BLOCK_ANY, info.idx, hash_control_entry)); 1877 soc_mem_field32_set(unit, 1878 info.regmem, hash_control_entry, info.sub_f, i); 1879 soc_mem_field32_set(unit, 1880 info.regmem, hash_control_entry, 1881 info.offset_f, offset); 1882 if (info.concat_f != -1) { 1883 soc_mem_field32_set(unit, 1884 info.regmem, hash_control_entry, 1885 info.concat_f, info.hash_concat); 1886 } 1887 SOC_IF_ERROR_RETURN 1888 (soc_mem_write(unit, 1889 info.regmem, MEM_BLOCK_ALL, info.idx, 1890 hash_control_entry)); 1891 } 1892 } else { 1893 return BCM_E_PARAM; 1894 } 1895 1896 return BCM_E_NONE; 1897 } 1898 1899 /* 1900 * Function: 1901 * bcm_gh2_switch_rtag7_fieldoffset_get 1902 * Description: 1903 * Get the current enhanced (aka rtag 7) bit selection offset. 1904 * Parameters: 1905 * unit - StrataSwitch PCI device unit number (driver internal). 1906 * type - The desired configuration parameter to retrieve. 1907 * arg - Pointer to where the retrieved value will be written. 1908 * Returns: 1909 * BCM_E_xxxx 1910 */ 1911 int 1912 bcm_gh2_switch_rtag7_fieldoffset_get(int unit, bcm_port_t port, 1913 bcm_switch_control_t type, int *arg) 1914 { 1915 int sub_field_width[8]; 1916 int idx = 0, i; 1917 hash_offset_info_t info; 1918 int total_width = 0; 1919 int concat = 0; 1920 uint32 hash_control_entry[SOC_MAX_MEM_WORDS]; 1921 int field_count = 0; 1922 soc_field_t fields[3]; 1923 uint32 values[3]; 1924 1925 BCM_IF_ERROR_RETURN(_bcm_gh2_hash_offset(unit, port, type, &info)); 1926 1927 if (SOC_MEM_IS_VALID(unit, info.regmem)) { 1928 /* LPORT Profile */ 1929 if (BCM_GPORT_IS_PROXY(port)) { 1930 fields[0] = info.sub_f; 1931 field_count++; 1932 fields[1] = info.offset_f; 1933 field_count++; 1934 if (info.concat_f != -1) { 1935 fields[2] = info.concat_f; 1936 field_count++; 1937 } 1938 BCM_IF_ERROR_RETURN 1939 (bcm_esw_port_lport_fields_get(unit, port, 1940 LPORT_PROFILE_RTAG7_TAB, 1941 field_count, fields, values)); 1942 idx = values[0]; 1943 *arg = values[1]; 1944 if (info.concat_f != -1) { 1945 concat = values[2]; 1946 } 1947 } else { 1948 SOC_IF_ERROR_RETURN 1949 (soc_mem_read(unit, info.regmem, 1950 MEM_BLOCK_ANY, info.idx, hash_control_entry)); 1951 idx = soc_mem_field32_get(unit, info.regmem, 1952 hash_control_entry, info.sub_f); 1953 *arg = soc_mem_field32_get(unit, info.regmem, 1954 hash_control_entry, info.offset_f); 1955 if (info.concat_f != -1) { 1956 concat = soc_mem_field32_get(unit, info.regmem, 1957 hash_control_entry, info.concat_f); 1958 } 1959 } 1960 } else { 1961 return BCM_E_PARAM; 1962 } 1963 1964 sub_field_width[0] = 16; /* HASH_A0 (16bit) */ 1965 sub_field_width[1] = 16; /* HASH_B0 (16bit) */ 1966 sub_field_width[2] = 4; /* LBN (4bit) */ 1967 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 1968 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 1969 sub_field_width[5] = 8; /* SW1 LBID ( 8 bit)*/ 1970 sub_field_width[6] = 16; /* HASH_A1 (16 bit) */ 1971 sub_field_width[7] = 16; /* HASH_B1 (16 bit) */ 1972 1973 if (concat) { 1974 /* Get hash bits width */ 1975 for (i = 0; i < 8; i++) { 1976 total_width += sub_field_width[i]; 1977 } 1978 1979 /* Concatenation hash computation order is referenced from 1980 * fb_Irsel1_arch::compute_rtag7_hash 1981 */ 1982 sub_field_width[0] = 64; /* Concat B1,B0,A1,A0(64bit) */ 1983 sub_field_width[1] = 0; /* 0 (Reserved) */ 1984 sub_field_width[2] = 4; /* LBN (4bit) */ 1985 sub_field_width[3] = 16; /* MH.DPORT/ HASH_A0(16bit) */ 1986 sub_field_width[4] = 8; /* MH.LBID / IRSEL local LBID (8 bit) */ 1987 sub_field_width[5] = 8; /* SW1 LBID (8 bit) */ 1988 sub_field_width[6] = 0; /* 0 (Reserved) */ 1989 sub_field_width[7] = 0; /* 0 (Reserved) */ 1990 1991 *arg += total_width; 1992 } 1993 1994 for (i = 0; i < idx; i++) { 1995 *arg += sub_field_width[i]; 1996 } 1997 1998 return BCM_E_NONE; 1999 } 2000 2001 STATIC int 2002 bcm_gh2_switch_rtag7_macroflow_hash_info_get( 2003 int unit, 2004 bcm_switch_control_t type, 2005 hash_offset_info_t *hash_info) 2006 { 2007 /* Input parameter check */ 2008 if (NULL == hash_info) { 2009 return BCM_E_PARAM; 2010 } 2011 2012 hash_info->regmem = RTAG7_FLOW_BASED_HASHm; 2013 2014 switch (type) { 2015 case bcmSwitchMacroFlowEcmpHashConcatEnable: 2016 hash_info->sub_f = SUB_SEL_ECMPf; 2017 hash_info->offset_f = OFFSET_ECMPf; 2018 hash_info->concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 2019 hash_info->hash_concat = 1; 2020 break; 2021 case bcmSwitchMacroFlowHashMinOffset: 2022 case bcmSwitchMacroFlowHashMaxOffset: 2023 case bcmSwitchMacroFlowHashStrideOffset: 2024 hash_info->sub_f = SUB_SEL_ECMPf; 2025 hash_info->offset_f = OFFSET_ECMPf; 2026 hash_info->concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 2027 hash_info->hash_concat = 0; 2028 break; 2029 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 2030 hash_info->sub_f = SUB_SEL_LBIDf; 2031 hash_info->offset_f = OFFSET_LBIDf; 2032 hash_info->concat_f = CONCATENATE_HASH_FIELDS_LBIDf; 2033 hash_info->hash_concat = 1; 2034 break; 2035 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 2036 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 2037 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 2038 hash_info->sub_f = SUB_SEL_LBIDf; 2039 hash_info->offset_f = OFFSET_LBIDf; 2040 hash_info->concat_f = CONCATENATE_HASH_FIELDS_LBIDf; 2041 hash_info->hash_concat = 0; 2042 break; 2043 case bcmSwitchMacroFlowTrunkHashConcatEnable: 2044 hash_info->sub_f = SUB_SEL_TRUNKf; 2045 hash_info->offset_f = OFFSET_TRUNKf; 2046 hash_info->concat_f = CONCATENATE_HASH_FIELDS_TRUNKf; 2047 hash_info->hash_concat = 1; 2048 break; 2049 case bcmSwitchMacroFlowTrunkHashMinOffset: 2050 case bcmSwitchMacroFlowTrunkHashMaxOffset: 2051 case bcmSwitchMacroFlowTrunkHashStrideOffset: 2052 hash_info->sub_f = SUB_SEL_TRUNKf; 2053 hash_info->offset_f = OFFSET_TRUNKf; 2054 hash_info->concat_f = CONCATENATE_HASH_FIELDS_TRUNKf; 2055 hash_info->hash_concat = 0; 2056 break; 2057 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 2058 hash_info->sub_f = SUB_SEL_HG_TRUNKf; 2059 hash_info->offset_f = OFFSET_HG_TRUNKf; 2060 hash_info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNKf; 2061 hash_info->hash_concat = 1; 2062 break; 2063 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 2064 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 2065 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 2066 hash_info->sub_f = SUB_SEL_HG_TRUNKf; 2067 hash_info->offset_f = OFFSET_HG_TRUNKf; 2068 hash_info->concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNKf; 2069 hash_info->hash_concat = 0; 2070 break; 2071 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 2072 default: 2073 return BCM_E_UNAVAIL; 2074 } 2075 2076 return BCM_E_NONE; 2077 } 2078 2079 STATIC int 2080 bcm_gh2_switch_rtag7_macroflow_param_get( 2081 int unit, 2082 bcm_switch_control_t type, 2083 int **sub_field_base, 2084 int *min_offset, 2085 int *max_offset, 2086 int *stride_offset, 2087 int *concat_enable) 2088 { 2089 /* sub field width: 16, 16, 4, 16, 8, 8, 16, 16 */ 2090 static int base[] = {0, 16, 32, 36, 52, 60, 68, 84, 100}; 2091 rtag7_flow_based_hash_entry_t entry; 2092 int min, max, stride; 2093 int index, offset; 2094 uint32 fval, sub_sel; 2095 hash_offset_info_t hash_info; 2096 int concat_value = 0; 2097 2098 sal_memset(&hash_info, 0, sizeof(hash_offset_info_t)); 2099 BCM_IF_ERROR_RETURN( 2100 bcm_gh2_switch_rtag7_macroflow_hash_info_get(unit, type, &hash_info)); 2101 2102 if (!SOC_MEM_IS_VALID(unit, hash_info.regmem)) { 2103 return BCM_E_UNAVAIL; 2104 } 2105 2106 BCM_IF_ERROR_RETURN( 2107 soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 0, &entry)); 2108 sub_sel = soc_mem_field32_get(unit, hash_info.regmem, &entry, 2109 hash_info.sub_f); 2110 fval = soc_mem_field32_get(unit, hash_info.regmem, &entry, 2111 hash_info.offset_f); 2112 if (hash_info.concat_f != -1) { 2113 concat_value = soc_mem_field32_get(unit, hash_info.regmem, &entry, 2114 hash_info.concat_f); 2115 if (hash_info.hash_concat || concat_value) { 2116 /* sub field width: 64, 0, 4, 64, 8, 8, 0, 0 */ 2117 base[0] = 0; 2118 base[1] = 64; /* base[1] = base[0] + width of base[0] */ 2119 base[2] = 64; /* base[2] = base[1] + width of base[1] */ 2120 base[3] = 68; /* base[3] = base[2] + width of base[2] */ 2121 base[4] = 132; /* base[4] = base[3] + width of base[3] */ 2122 base[5] = 140; /* base[5] = base[4] + width of base[4] */ 2123 base[6] = 148; /* base[6] = base[5] + width of base[5] */ 2124 base[7] = 148; /* base[7] = base[6] + width of base[6] */ 2125 base[8] = 148; /* base[8] = base[7] + width of base[7] */ 2126 } else { 2127 /* sub field width: 16, 16, 4, 16, 8, 8, 16, 16 */ 2128 base[0] = 0; 2129 base[1] = 16; /* base[1] = base[0] + width of base[0] */ 2130 base[2] = 32; /* base[2] = base[1] + width of base[1] */ 2131 base[3] = 36; /* base[3] = base[2] + width of base[2] */ 2132 base[4] = 52; /* base[4] = base[3] + width of base[3] */ 2133 base[5] = 60; /* base[5] = base[4] + width of base[4] */ 2134 base[6] = 68; /* base[6] = base[5] + width of base[5] */ 2135 base[7] = 84; /* base[7] = base[6] + width of base[6] */ 2136 base[8] = 100; /* base[8] = base[7] + width of base[7] */ 2137 } 2138 } 2139 min = base[sub_sel] + fval; 2140 2141 BCM_IF_ERROR_RETURN( 2142 soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 1, &entry)); 2143 sub_sel = soc_mem_field32_get(unit, hash_info.regmem, &entry, 2144 hash_info.sub_f); 2145 fval = soc_mem_field32_get(unit, hash_info.regmem, &entry, 2146 hash_info.offset_f); 2147 max = base[sub_sel] + fval; 2148 stride = max - min; 2149 2150 if (stride != 0) { 2151 for (index = 2; 2152 index <= soc_mem_index_max(unit, hash_info.regmem); 2153 index++) { 2154 BCM_IF_ERROR_RETURN( 2155 soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 2156 index, &entry)); 2157 sub_sel = soc_mem_field32_get(unit, hash_info.regmem, &entry, 2158 hash_info.sub_f); 2159 fval = soc_mem_field32_get(unit, hash_info.regmem, &entry, 2160 hash_info.offset_f); 2161 offset = base[sub_sel] + fval; 2162 if (offset != max + stride) { 2163 break; 2164 } 2165 max = offset; 2166 } 2167 } 2168 2169 if (sub_field_base != NULL) { 2170 *sub_field_base = base; 2171 } 2172 if (min_offset != NULL) { 2173 *min_offset = min; 2174 } 2175 if (max_offset != NULL) { 2176 *max_offset = max; 2177 } 2178 if (stride_offset != NULL) { 2179 *stride_offset = stride; 2180 } 2181 if (concat_enable != NULL) { 2182 *concat_enable = concat_value; 2183 } 2184 2185 return BCM_E_NONE; 2186 } 2187 2188 STATIC int 2189 bcm_gh2_switch_rtag7_macroflow_offset_set( 2190 int unit, 2191 bcm_switch_control_t type, 2192 int arg) 2193 { 2194 int *sub_field_base; 2195 rtag7_flow_based_hash_entry_t entry; 2196 int min_offset, max_offset, stride_offset, concat_enable; 2197 int index, offset; 2198 uint32 sub_sel; 2199 hash_offset_info_t hash_info; 2200 2201 sal_memset(&hash_info, 0, sizeof(hash_offset_info_t)); 2202 /* 2203 * Hash info such as sub_sel field, offset field and concatenate field 2204 * are retrieved using bcm_gh2_switch_rtag7_macroflow_hash_info_get 2205 * based on given type. 2206 */ 2207 BCM_IF_ERROR_RETURN( 2208 bcm_gh2_switch_rtag7_macroflow_hash_info_get(unit, type, &hash_info)); 2209 2210 /* 2211 * bcm_gh2_switch_rtag7_macroflow_param_get fetches sub field base, 2212 * min offset, max offset, stride offset and concatenation values currently 2213 * configured in the hardware for the given type. 2214 */ 2215 BCM_IF_ERROR_RETURN( 2216 bcm_gh2_switch_rtag7_macroflow_param_get(unit, type, &sub_field_base, 2217 &min_offset, &max_offset, &stride_offset, 2218 &concat_enable)); 2219 2220 if (arg < -1 || arg >= sub_field_base[8]) { 2221 return BCM_E_PARAM; 2222 } 2223 2224 switch (type) { 2225 case bcmSwitchMacroFlowHashMinOffset: 2226 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 2227 case bcmSwitchMacroFlowTrunkHashMinOffset: 2228 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 2229 if (arg == min_offset) { 2230 return BCM_E_NONE; 2231 } else if ((max_offset > 0) && (arg > max_offset)) { 2232 return BCM_E_PARAM; 2233 } 2234 min_offset = arg == -1 ? 0 : arg; 2235 break; 2236 case bcmSwitchMacroFlowHashMaxOffset: 2237 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 2238 case bcmSwitchMacroFlowTrunkHashMaxOffset: 2239 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 2240 if (arg == max_offset) { 2241 return BCM_E_NONE; 2242 } else if ((arg < min_offset) && (arg != -1)) { 2243 return BCM_E_PARAM; 2244 } 2245 max_offset = arg == -1 ? sub_field_base[8] - 1 : arg; 2246 break; 2247 case bcmSwitchMacroFlowHashStrideOffset: 2248 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 2249 case bcmSwitchMacroFlowTrunkHashStrideOffset: 2250 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 2251 if (arg == stride_offset) { 2252 return BCM_E_NONE; 2253 } else if (arg < 0) { 2254 return BCM_E_PARAM; 2255 } 2256 stride_offset = arg; 2257 break; 2258 case bcmSwitchMacroFlowEcmpHashConcatEnable: 2259 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 2260 case bcmSwitchMacroFlowTrunkHashConcatEnable: 2261 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 2262 if (arg == concat_enable) { 2263 return BCM_E_NONE; 2264 } else if (!((arg == 0) || (arg == 1))) { 2265 return BCM_E_PARAM; 2266 } 2267 concat_enable = arg; 2268 break; 2269 default: 2270 return BCM_E_INTERNAL; 2271 } 2272 2273 if (stride_offset == 0 && min_offset != max_offset) { 2274 stride_offset = 1; 2275 } 2276 2277 if (((type == bcmSwitchMacroFlowHashStrideOffset) || 2278 (type == bcmSwitchMacroFlowHigigTrunkHashStrideOffset) || 2279 (type == bcmSwitchMacroFlowTrunkHashStrideOffset) || 2280 (type == bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset)) && 2281 (stride_offset == 1) && (min_offset == max_offset)) { 2282 max_offset += stride_offset; 2283 } 2284 2285 offset = min_offset; 2286 for (index = 0; index <= soc_mem_index_max(unit, hash_info.regmem); 2287 index++) { 2288 for (sub_sel = 0; sub_sel < 7; sub_sel++) { 2289 if (offset < sub_field_base[sub_sel + 1]) { 2290 break; 2291 } 2292 } 2293 2294 BCM_IF_ERROR_RETURN( 2295 soc_mem_read(unit, hash_info.regmem, MEM_BLOCK_ANY, 2296 index, &entry)); 2297 2298 soc_mem_field32_set(unit, hash_info.regmem, &entry, 2299 hash_info.sub_f, sub_sel); 2300 soc_mem_field32_set(unit, hash_info.regmem, &entry, 2301 hash_info.offset_f, 2302 (offset - sub_field_base[sub_sel])); 2303 if (hash_info.concat_f != -1) { 2304 soc_mem_field32_set(unit, hash_info.regmem, &entry, 2305 hash_info.concat_f, concat_enable); 2306 } 2307 2308 BCM_IF_ERROR_RETURN( 2309 soc_mem_write(unit, hash_info.regmem, MEM_BLOCK_ANY, 2310 index, &entry)); 2311 offset += stride_offset; 2312 if (offset > max_offset) { 2313 offset = min_offset; 2314 } 2315 } 2316 2317 return BCM_E_NONE; 2318 } 2319 2320 STATIC int 2321 _bcm_gh2_random_hash_seed_get(int unit, hash_offset_info_t *hash_info, 2322 int seed, int *offset, int *subsel) 2323 { 2324 int concat, random; 2325 uint32 hash_entry[SOC_MAX_MEM_WORDS]; 2326 2327 /* Input parameter check */ 2328 if ((NULL == hash_info) || (NULL == offset) || (NULL == subsel)) { 2329 return BCM_E_PARAM; 2330 } 2331 2332 /* Check for hash Concatenation */ 2333 BCM_IF_ERROR_RETURN( 2334 soc_mem_read(unit, hash_info->regmem, MEM_BLOCK_ANY, 0, &hash_entry)); 2335 concat = soc_mem_field32_get(unit, hash_info->regmem, &hash_entry, 2336 hash_info->concat_f); 2337 2338 /* Generate random number for the seed as described in C standards */ 2339 random = seed * 1103515245 + 12345; 2340 /* random_seed / 65536) % 32768 */ 2341 random = (random >> 16) & 0x7FFF; 2342 2343 if (concat) { 2344 *offset = random & 0x3f; 2345 /* Use HASH A0_A1_B0_B1 */ 2346 *subsel = 0; 2347 } else { 2348 *offset = random & 0xf; 2349 /* User any of hash A0, A1, B0, B1 */ 2350 *subsel = (random & 0x30) >> 4; 2351 } 2352 2353 return BCM_E_NONE; 2354 } 2355 2356 /* 2357 * Function: 2358 * bcm_gh2_switch_rtag7_symmetric_hash_control_set 2359 * Description: 2360 * Set the RTAG7 Macro Flow Hash Seed/Concatenation control settings. 2361 * Parameters: 2362 * unit - StrataSwitch PCI device unit number (driver internal). 2363 * type - The desired configuration parameter to set. 2364 * arg - Enable/Disable values 2365 * Returns: 2366 * BCM_E_xxxx 2367 */ 2368 STATIC int 2369 bcm_gh2_switch_rtag7_macroflow_hash_set( 2370 int unit, 2371 bcm_switch_control_t type, 2372 int arg) 2373 { 2374 soc_mem_t hash_sel_regmem; 2375 uint32 hash_entry[SOC_MAX_MEM_WORDS]; 2376 hash_offset_info_t hash_info; 2377 soc_field_t hash_flow_select[5]; 2378 uint32 rval; 2379 int index = 0, min, max; 2380 int offset = 0, subsel = 0; 2381 2382 sal_memset(&hash_info, 0, sizeof(hash_offset_info_t)); 2383 sal_memset(&hash_flow_select, 0, sizeof(hash_flow_select)); 2384 2385 hash_sel_regmem = RTAG7_HASH_SELr; 2386 hash_info.regmem = RTAG7_FLOW_BASED_HASHm; 2387 2388 switch (type) { 2389 /* Set RTAG7 Macro Flow Hash Seed for ECMP */ 2390 case bcmSwitchMacroFlowECMPHashSeed: 2391 hash_info.sub_f = SUB_SEL_ECMPf; 2392 hash_info.offset_f = OFFSET_ECMPf; 2393 hash_info.concat_f = CONCATENATE_HASH_FIELDS_ECMPf; 2394 hash_flow_select[index++] = USE_FLOW_SEL_VXLAN_ECMPf; 2395 hash_flow_select[index++] = USE_FLOW_SEL_ROCEV2_ECMPf; 2396 break; 2397 /* Set RTAG7 Macro Flow Hash Seed for LBID/ENTROPY */ 2398 case bcmSwitchMacroFlowLoadBalanceHashSeed: 2399 hash_info.sub_f = SUB_SEL_LBIDf; 2400 hash_info.offset_f = OFFSET_LBIDf; 2401 hash_info.concat_f = CONCATENATE_HASH_FIELDS_LBIDf; 2402 hash_flow_select[index++] = USE_FLOW_SEL_LBID_UCf; 2403 hash_flow_select[index++] = USE_FLOW_SEL_LBID_NONUCf; 2404 hash_flow_select[index++] = USE_FLOW_SEL_ENTROPYf; 2405 break; 2406 /* Set RTAG7 Macro Flow Hash Seed for TRUNK */ 2407 case bcmSwitchMacroFlowTrunkHashSeed: 2408 hash_info.sub_f = SUB_SEL_TRUNKf; 2409 hash_info.offset_f = OFFSET_TRUNKf; 2410 hash_info.concat_f = CONCATENATE_HASH_FIELDS_TRUNKf; 2411 hash_flow_select[index++] = USE_FLOW_SEL_TRUNK_UCf; 2412 hash_flow_select[index++] = USE_FLOW_SEL_TRUNK_NONUCf; 2413 break; 2414 /* Set RTAG7 Macro Flow Hash Seed for HG TRUNK */ 2415 case bcmSwitchMacroFlowHigigTrunkHashSeed: 2416 hash_info.sub_f = SUB_SEL_HG_TRUNKf; 2417 hash_info.offset_f = OFFSET_HG_TRUNKf; 2418 hash_info.concat_f = CONCATENATE_HASH_FIELDS_HG_TRUNKf; 2419 hash_flow_select[index++] = USE_FLOW_SEL_HG_TRUNK_UCf; 2420 hash_flow_select[index++] = USE_FLOW_SEL_HG_TRUNK_NONUCf; 2421 hash_flow_select[index++] = USE_FLOW_SEL_HG_TRUNK_FAILOVERf; 2422 break; 2423 case bcmSwitchMacroFlowECMPUnderlayHashSeed: 2424 return BCM_E_UNAVAIL; 2425 default: 2426 return BCM_E_PARAM; 2427 } 2428 2429 if (!soc_mem_is_valid(unit, hash_info.regmem)) { 2430 return BCM_E_UNAVAIL; 2431 } 2432 min = soc_mem_index_min(unit, hash_info.regmem); 2433 max = soc_mem_index_max(unit, hash_info.regmem); 2434 2435 /* Set random generated hash offset and sub select */ 2436 BCM_IF_ERROR_RETURN( 2437 _bcm_gh2_random_hash_seed_get(unit, &hash_info, arg, 2438 &offset, &subsel)); 2439 2440 for (index = min; index <= max; index++) { 2441 BCM_IF_ERROR_RETURN( 2442 soc_mem_read(unit, hash_info.regmem, 2443 MEM_BLOCK_ANY, index, &hash_entry)); 2444 soc_mem_field32_set(unit, hash_info.regmem, &hash_entry, 2445 hash_info.sub_f, subsel); 2446 soc_mem_field32_set(unit, hash_info.regmem, &hash_entry, 2447 hash_info.offset_f, offset); 2448 BCM_IF_ERROR_RETURN( 2449 soc_mem_write(unit, hash_info.regmem, 2450 MEM_BLOCK_ALL, index, &hash_entry)); 2451 } 2452 2453 /* Enable Macro flow bits */ 2454 BCM_IF_ERROR_RETURN( 2455 soc_reg32_get(unit, hash_sel_regmem, REG_PORT_ANY, 0, &rval)); 2456 2457 for (index = 0; 2458 index < (sizeof(hash_flow_select) / sizeof(soc_field_t)); 2459 index++) { 2460 if (soc_reg_field_valid(unit, hash_sel_regmem, 2461 hash_flow_select[index])) { 2462 soc_reg_field_set(unit, hash_sel_regmem, &rval, 2463 hash_flow_select[index], 1); 2464 } 2465 } 2466 2467 BCM_IF_ERROR_RETURN( 2468 soc_reg32_set(unit, hash_sel_regmem, REG_PORT_ANY, 0, rval)); 2469 2470 return BCM_E_NONE; 2471 } 2472 2473 /* 2474 * Function: 2475 * _bcm_esw_switch_control_gport_resolve 2476 * Description: 2477 * Decodes local physical port from a gport 2478 * Parameters: 2479 * unit - StrataSwitch PCI device unit number (driver internal). 2480 * gport - a gport to decode 2481 * port - (Out) Local physical port encoded in gport 2482 * Returns: 2483 * BCM_E_xxxx 2484 * Note 2485 * In case of gport contains other then local port error will be returned. 2486 */ 2487 2488 2489 STATIC int 2490 _bcm_gh2_switch_control_gport_resolve(int unit, bcm_gport_t gport, bcm_port_t *port) 2491 { 2492 bcm_module_t modid; 2493 bcm_trunk_t tgid; 2494 bcm_port_t local_port; 2495 int id, isMymodid; 2496 2497 if (NULL == port) { 2498 return BCM_E_PARAM; 2499 } 2500 BCM_IF_ERROR_RETURN( 2501 _bcm_esw_gport_resolve(unit, gport, &modid, &local_port, &tgid, &id)); 2502 2503 if ((BCM_TRUNK_INVALID != tgid) || (-1 != id)) { 2504 return BCM_E_PARAM; 2505 } 2506 /* Check if modid is local */ 2507 BCM_IF_ERROR_RETURN( 2508 _bcm_esw_modid_is_local(unit, modid, &isMymodid)); 2509 2510 if (isMymodid != TRUE) { 2511 return BCM_E_PORT; 2512 } 2513 *port = local_port; 2514 2515 return (BCM_E_NONE); 2516 } 2517 2518 /* 2519 * Function: 2520 * bcm_gh2_switch_control_port_proxy_validate 2521 * Description: 2522 * Checks that switch control is valid for a PROXY GPORT. 2523 * Resolves port to expected port value for the given port control type. 2524 * Parameters: 2525 * unit - (IN) Device number 2526 * port - (IN) Port to resolve 2527 * type - (IN) Switch control type 2528 * port_out - (OUT) Returns port (gport or BCM format) that 2529 * is expected for corresponding switch control type. 2530 * Return Value: 2531 * BCM_E_XXX 2532 */ 2533 STATIC int 2534 bcm_gh2_switch_control_port_proxy_validate(int unit, bcm_port_t port, 2535 bcm_switch_control_t type, 2536 bcm_port_t *port_out) 2537 { 2538 int rv = BCM_E_PORT; 2539 int support = FALSE; 2540 2541 if (!soc_feature(unit, soc_feature_proxy_port_property)) { 2542 return BCM_E_PORT; 2543 } 2544 2545 switch(type) { 2546 case bcmSwitchModuleLoopback: 2547 case bcmSwitchTrunkHashSet0UnicastOffset: 2548 case bcmSwitchTrunkHashSet0NonUnicastOffset: 2549 case bcmSwitchTrunkFailoverHashOffset: 2550 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 2551 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 2552 case bcmSwitchFabricTrunkFailoverHashOffset: 2553 case bcmSwitchFabricTrunkDynamicHashOffset: 2554 case bcmSwitchTrunkDynamicHashOffset: 2555 case bcmSwitchEcmpDynamicHashOffset: 2556 case bcmSwitchFabricTrunkResilientHashOffset: 2557 case bcmSwitchTrunkResilientHashOffset: 2558 case bcmSwitchEcmpResilientHashOffset: 2559 case bcmSwitchECMPVxlanHashOffset: 2560 case bcmSwitchECMPUnderlayVxlanHashOffset: 2561 case bcmSwitchECMPL2GreHashOffset: 2562 case bcmSwitchECMPUnderlayL2GreHashOffset: 2563 case bcmSwitchECMPTrillHashOffset: 2564 case bcmSwitchECMPUnderlayTrillHashOffset: 2565 case bcmSwitchECMPMplsHashOffset: 2566 case bcmSwitchVirtualPortDynamicHashOffset: 2567 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 2568 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 2569 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 2570 case bcmSwitchECMPHashSet0Offset: 2571 case bcmSwitchECMPOverlayHashOffset: 2572 case bcmSwitchECMPUnderlayHashSet0Offset: 2573 case bcmSwitchEntropyHashSet0Offset: 2574 support = TRUE; 2575 break; 2576 default: 2577 support = FALSE; 2578 break; 2579 } 2580 2581 if (support) { 2582 *port_out = port; 2583 rv = BCM_E_NONE; 2584 } 2585 2586 return rv; 2587 } 2588 2589 /* 2590 * Function: 2591 * bcm_gh2_switch_control_port_validate 2592 * Description: 2593 * Checks that port is valid and that control is supported 2594 * for the given port type. Resolves port to expected 2595 * port value for the given switch control type. 2596 * Current valid port types are: 2597 * GPORT PROXY 2598 * GPORT (various types) that resolves to local physical port 2599 * BCM port (non-gport) 2600 * Parameters: 2601 * unit - (IN) Device number 2602 * port - (IN) Port to resolve 2603 * type - (IN) Switch control type 2604 * port_out - (OUT) Returns port (gport or BCM format) that 2605 * is expected for corresponding switch control type. 2606 * Return Value: 2607 * BCM_E_XXX 2608 */ 2609 STATIC int 2610 bcm_gh2_switch_control_port_validate(int unit, bcm_port_t port, 2611 bcm_switch_control_t type, 2612 bcm_port_t *port_out) 2613 { 2614 int rv = BCM_E_PORT; 2615 2616 if (BCM_GPORT_IS_PROXY(port)) { 2617 rv = bcm_gh2_switch_control_port_proxy_validate(unit, port, 2618 type, port_out); 2619 } else { 2620 /* All other types are supported for valid physical local ports */ 2621 rv = _bcm_gh2_switch_control_gport_resolve(unit, port, port_out); 2622 } 2623 2624 return rv; 2625 } 2626 2627 2628 STATIC int 2629 _bcm_gh2_pkt_age_set(int unit, int arg) 2630 { 2631 int aging_ticks = arg; 2632 uint32 pat_val = 0; 2633 2634 if (!arg) { 2635 /* Disable packet aging on all COSQs */ 2636 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 0)); 2637 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT_r(unit, 0, 0)); /* Aesthetic */ 2638 } else if ((arg < 0) || (arg > 7162)) { 2639 return BCM_E_PARAM; 2640 } else { 2641 /* Use 125 us clock pulses */ 2642 soc_reg_field_set(unit, PKTAGINGTIMERr, &pat_val, AGINGTICKSELf, 0); 2643 2644 /* Convert ms request to 125 us pulses */ 2645 aging_ticks *= 8; 2646 2647 /* We want this many pulses to happen before aging, 2648 * but the HW setting is pulses per cycle. 2649 * We need to divide the by the number of cycles before aging.*/ 2650 aging_ticks = 2651 (aging_ticks + NUM_MMU_AGE_CYCLES - 1) / NUM_MMU_AGE_CYCLES; 2652 soc_reg_field_set(unit, PKTAGINGTIMERr, &pat_val, 2653 DURATIONSELECTf, aging_ticks); 2654 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, pat_val)); 2655 2656 /* Set all COSQs to the same value 2657 * - They use the maximum of NUM_MMU_AGE_CYCLES to expire */ 2658 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT_r(unit, 0, 0)); 2659 } 2660 2661 return BCM_E_NONE; 2662 } 2663 2664 2665 STATIC int 2666 _bcm_gh2_pkt_age_get(int unit, int *arg) 2667 { 2668 uint32 timerval, limitval, mask; 2669 int i, loopcount; 2670 2671 /* Check that all COSQs have the same value */ 2672 SOC_IF_ERROR_RETURN(READ_PKTAGINGLIMIT_r(unit, 0, &limitval)); 2673 limitval &= 0xFFFFFF; /* AGINGLIMITCOSn fields only */ 2674 loopcount = mask = soc_reg_field_get(unit, PKTAGINGLIMIT_r, 2675 limitval, AGINGLIMITCOS_X0f); 2676 /* Make mask of eight identical AGINGLIMITCOSn fields */ 2677 for (i = 1; i < 8; i++) { 2678 mask = (mask << 3) | loopcount; 2679 } 2680 2681 if (mask != limitval) { 2682 /* COSQs currently are not programmed identically */ 2683 return BCM_E_CONFIG; 2684 } 2685 2686 /* Return the (common) setting */ 2687 loopcount = NUM_MMU_AGE_CYCLES - loopcount; 2688 SOC_IF_ERROR_RETURN(READ_PKTAGINGTIMERr(unit, &timerval)); 2689 2690 *arg = 2691 (loopcount * 2692 soc_reg_field_get(unit, PKTAGINGTIMERr, timerval, DURATIONSELECTf)) / 8; 2693 2694 return BCM_E_NONE; 2695 } 2696 2697 /* 2698 * Function: 2699 * _bcm_gh2_er_hashselect_set 2700 * Description: 2701 * Set the Hash Select for L2, L3 or Multipath type. 2702 * Parameters: 2703 * unit - StrataSwitch PCI device unit number (driver internal). 2704 * type - The desired configuration parameter to set. 2705 * arg - BCM_HASH_* 2706 * Returns: 2707 * BCM_E_xxxx 2708 */ 2709 2710 STATIC int 2711 _bcm_gh2_er_hashselect_set(int unit, bcm_switch_control_t type, int arg) 2712 { 2713 uint32 hash_control, val=0; 2714 soc_field_t field; 2715 soc_reg_t hash_reg = HASH_CONTROLr; 2716 int dual = FALSE; 2717 2718 switch (type) { 2719 case bcmSwitchHashL2: 2720 field = L2_AND_VLAN_MAC_HASH_SELECTf; 2721 if (!soc_reg_field_valid(unit, hash_reg, field)) { 2722 return BCM_E_UNAVAIL; 2723 } 2724 break; 2725 case bcmSwitchHashL3: 2726 if (soc_reg_field_valid(unit, HASH_CONTROLr, L3_HASH_SELECTf) && 2727 soc_feature(unit, soc_feature_l3)) { 2728 field = L3_HASH_SELECTf; 2729 } else { 2730 return BCM_E_UNAVAIL; 2731 } 2732 break; 2733 case bcmSwitchHashMultipath: 2734 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_SELf) && 2735 soc_feature(unit, soc_feature_l3)) { 2736 field = ECMP_HASH_SELf; 2737 if ((arg == BCM_HASH_CRC16L) || (arg == BCM_HASH_CRC16U)) { 2738 return BCM_E_PARAM; 2739 } 2740 } else { 2741 return BCM_E_UNAVAIL; 2742 } 2743 break; 2744 case bcmSwitchHashL2Dual: 2745 dual = TRUE; 2746 hash_reg = L2_AUX_HASH_CONTROLr; 2747 field = HASH_SELECTf; 2748 if (!soc_reg_field_valid(unit, hash_reg, field)) { 2749 return BCM_E_UNAVAIL; 2750 } 2751 break; 2752 case bcmSwitchHashL3Dual: 2753 if (soc_reg_field_valid(unit, L3_AUX_HASH_CONTROLr, HASH_SELECTf) && 2754 soc_feature(unit, soc_feature_l3)) { 2755 dual = TRUE; 2756 hash_reg = L3_AUX_HASH_CONTROLr; 2757 field = HASH_SELECTf; 2758 } else { 2759 return BCM_E_UNAVAIL; 2760 } 2761 break; 2762 case bcmSwitchHashIpfixIngress: 2763 case bcmSwitchHashIpfixEgress: 2764 case bcmSwitchHashIpfixIngressDual: 2765 case bcmSwitchHashIpfixEgressDual: 2766 case bcmSwitchHashMPLS: 2767 case bcmSwitchHashMPLSDual: 2768 return BCM_E_UNAVAIL; 2769 break; 2770 case bcmSwitchHashVlanTranslate: 2771 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 2772 hash_reg = VLAN_XLATE_HASH_CONTROLr; 2773 field = HASH_SELECT_Af; 2774 } else { 2775 return BCM_E_UNAVAIL; 2776 } 2777 break; 2778 case bcmSwitchHashVlanTranslateDual: 2779 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 2780 hash_reg = VLAN_XLATE_HASH_CONTROLr; 2781 field = HASH_SELECT_Bf; 2782 } else { 2783 return BCM_E_UNAVAIL; 2784 } 2785 break; 2786 case bcmSwitchHashEgressVlanTranslate: 2787 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 2788 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 2789 field = HASH_SELECT_Af; 2790 } else { 2791 return BCM_E_UNAVAIL; 2792 } 2793 break; 2794 case bcmSwitchHashEgressVlanTranslateDual: 2795 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 2796 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 2797 field = HASH_SELECT_Bf; 2798 } else { 2799 return BCM_E_UNAVAIL; 2800 } 2801 break; 2802 case bcmSwitchHashWlanPort: 2803 case bcmSwitchHashWlanPortDual: 2804 case bcmSwitchHashWlanClient: 2805 case bcmSwitchHashWlanClientDual: 2806 case bcmSwitchHashRegexAction: 2807 case bcmSwitchHashRegexActionDual: 2808 return BCM_E_UNAVAIL; 2809 break; 2810 case bcmSwitchHashL3DNATPool: 2811 case bcmSwitchHashL3DNATPoolDual: 2812 case bcmSwitchHashVpVlanMemberIngress: 2813 case bcmSwitchHashVpVlanMemberIngressDual: 2814 case bcmSwitchHashVpVlanMemberEgress: 2815 case bcmSwitchHashVpVlanMemberEgressDual: 2816 case bcmSwitchHashL2Endpoint: 2817 case bcmSwitchHashL2EndpointDual: 2818 case bcmSwitchHashEndpointQueueMap: 2819 case bcmSwitchHashEndpointQueueMapDual: 2820 case bcmSwitchHashOamEgress: 2821 case bcmSwitchHashOamEgressDual: 2822 case bcmSwitchHashOam: 2823 case bcmSwitchHashOamDual: 2824 return BCM_E_UNAVAIL; 2825 break; 2826 default: 2827 return BCM_E_PARAM; 2828 break; 2829 } 2830 2831 switch (arg) { 2832 case BCM_HASH_ZERO: 2833 val = FB_HASH_ZERO; 2834 break; 2835 case BCM_HASH_LSB: 2836 val = FB_HASH_LSB; 2837 break; 2838 case BCM_HASH_CRC16L: 2839 val = FB_HASH_CRC16_LOWER; 2840 break; 2841 case BCM_HASH_CRC16U: 2842 val = FB_HASH_CRC16_UPPER; 2843 break; 2844 case BCM_HASH_CRC32L: 2845 val = FB_HASH_CRC32_LOWER; 2846 break; 2847 case BCM_HASH_CRC32U: 2848 val = FB_HASH_CRC32_UPPER; 2849 break; 2850 default: 2851 return BCM_E_PARAM; 2852 } 2853 2854 SOC_IF_ERROR_RETURN 2855 (soc_reg_read_any_block(unit, hash_reg, &hash_control)); 2856 soc_reg_field_set(unit, hash_reg, &hash_control, field, val); 2857 if (dual) { 2858 uint32 base_hash_control, base_hash; 2859 soc_field_t base_field; 2860 2861 base_field = (type == bcmSwitchHashL2Dual) ? 2862 L2_AND_VLAN_MAC_HASH_SELECTf : L3_HASH_SELECTf; 2863 2864 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &base_hash_control)); 2865 base_hash = soc_reg_field_get(unit, HASH_CONTROLr, 2866 base_hash_control, base_field); 2867 soc_reg_field_set(unit, hash_reg, &hash_control, 2868 ENABLEf, (base_hash == val) ? 0 : 1); 2869 } 2870 SOC_IF_ERROR_RETURN 2871 (soc_reg_write_all_blocks(unit, hash_reg, hash_control)); 2872 2873 return BCM_E_NONE; 2874 } 2875 2876 2877 /* 2878 * Function: 2879 * _bcm_gh2_er_hashselect_get 2880 * Description: 2881 * Get the current Hash Select settings. Value returned 2882 * is of the form BCM_HASH_*. 2883 * All switch chip ports are configured with the same settings. 2884 * Parameters: 2885 * unit - StrataSwitch PCI device unit number (driver internal). 2886 * type - The desired configuration parameter to retrieve. 2887 * arg - Pointer to where the retrieved value will be written. 2888 * Returns: 2889 * BCM_E_xxxx 2890 */ 2891 2892 STATIC int 2893 _bcm_gh2_er_hashselect_get(int unit, bcm_switch_control_t type, int *arg) 2894 { 2895 uint32 hash_control, val=0; 2896 soc_reg_t hash_reg = HASH_CONTROLr; 2897 soc_field_t field; 2898 int dual = FALSE; 2899 2900 switch (type) { 2901 case bcmSwitchHashL2: 2902 field = L2_AND_VLAN_MAC_HASH_SELECTf; 2903 if (!soc_reg_field_valid(unit, hash_reg, field)) { 2904 return BCM_E_UNAVAIL; 2905 } 2906 break; 2907 case bcmSwitchHashL3: 2908 if (soc_reg_field_valid(unit, HASH_CONTROLr, L3_HASH_SELECTf) && 2909 soc_feature(unit, soc_feature_l3)) { 2910 field = L3_HASH_SELECTf; 2911 } else { 2912 return BCM_E_UNAVAIL; 2913 } 2914 break; 2915 case bcmSwitchHashMultipath: 2916 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_SELf) && 2917 soc_feature(unit, soc_feature_l3)) { 2918 field = ECMP_HASH_SELf; 2919 } else { 2920 return BCM_E_UNAVAIL; 2921 } 2922 break; 2923 case bcmSwitchHashL2Dual: 2924 dual = TRUE; 2925 hash_reg = L2_AUX_HASH_CONTROLr; 2926 field = HASH_SELECTf; 2927 if (!soc_reg_field_valid(unit, hash_reg, field)) { 2928 return BCM_E_UNAVAIL; 2929 } 2930 break; 2931 case bcmSwitchHashL3Dual: 2932 if (soc_reg_field_valid(unit, L3_AUX_HASH_CONTROLr, HASH_SELECTf) && 2933 soc_feature(unit, soc_feature_l3)) { 2934 dual = TRUE; 2935 hash_reg = L3_AUX_HASH_CONTROLr; 2936 field = HASH_SELECTf; 2937 } else { 2938 return BCM_E_UNAVAIL; 2939 } 2940 break; 2941 case bcmSwitchHashIpfixIngress: 2942 case bcmSwitchHashIpfixEgress: 2943 case bcmSwitchHashIpfixIngressDual: 2944 case bcmSwitchHashIpfixEgressDual: 2945 case bcmSwitchHashMPLS: 2946 case bcmSwitchHashMPLSDual: 2947 return BCM_E_UNAVAIL; 2948 case bcmSwitchHashVlanTranslate: 2949 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 2950 hash_reg = VLAN_XLATE_HASH_CONTROLr; 2951 field = HASH_SELECT_Af; 2952 } else { 2953 return BCM_E_UNAVAIL; 2954 } 2955 break; 2956 case bcmSwitchHashVlanTranslateDual: 2957 if (soc_reg_field_valid(unit, VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 2958 hash_reg = VLAN_XLATE_HASH_CONTROLr; 2959 field = HASH_SELECT_Bf; 2960 } else { 2961 return BCM_E_UNAVAIL; 2962 } 2963 break; 2964 case bcmSwitchHashEgressVlanTranslate: 2965 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Af)) { 2966 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 2967 field = HASH_SELECT_Af; 2968 } else { 2969 return BCM_E_UNAVAIL; 2970 } 2971 break; 2972 case bcmSwitchHashEgressVlanTranslateDual: 2973 if (soc_reg_field_valid(unit, EGR_VLAN_XLATE_HASH_CONTROLr, HASH_SELECT_Bf)) { 2974 hash_reg = EGR_VLAN_XLATE_HASH_CONTROLr; 2975 field = HASH_SELECT_Bf; 2976 } else { 2977 return BCM_E_UNAVAIL; 2978 } 2979 break; 2980 case bcmSwitchHashWlanPort: 2981 case bcmSwitchHashWlanPortDual: 2982 case bcmSwitchHashWlanClient: 2983 case bcmSwitchHashWlanClientDual: 2984 case bcmSwitchHashRegexAction: 2985 case bcmSwitchHashRegexActionDual: 2986 return BCM_E_UNAVAIL; 2987 break; 2988 case bcmSwitchHashL3DNATPool: 2989 case bcmSwitchHashL3DNATPoolDual: 2990 case bcmSwitchHashVpVlanMemberIngress: 2991 case bcmSwitchHashVpVlanMemberIngressDual: 2992 case bcmSwitchHashVpVlanMemberEgress: 2993 case bcmSwitchHashVpVlanMemberEgressDual: 2994 case bcmSwitchHashL2Endpoint: 2995 case bcmSwitchHashL2EndpointDual: 2996 case bcmSwitchHashEndpointQueueMap: 2997 case bcmSwitchHashEndpointQueueMapDual: 2998 case bcmSwitchHashOamEgress: 2999 case bcmSwitchHashOamEgressDual: 3000 case bcmSwitchHashOam: 3001 case bcmSwitchHashOamDual: 3002 return BCM_E_UNAVAIL; 3003 break; 3004 default: 3005 return BCM_E_PARAM; 3006 } 3007 3008 SOC_IF_ERROR_RETURN 3009 (soc_reg_read_any_block(unit, hash_reg, &hash_control)); 3010 3011 if (dual && 3012 !soc_reg_field_get(unit, hash_reg, hash_control, ENABLEf)) { 3013 /* Dual hash not enabled, just return primary hash */ 3014 field = (type == bcmSwitchHashL2Dual) ? 3015 L2_AND_VLAN_MAC_HASH_SELECTf : L3_HASH_SELECTf; 3016 hash_reg = HASH_CONTROLr; 3017 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 3018 } 3019 val = soc_reg_field_get(unit, hash_reg, hash_control, field); 3020 3021 switch (val) { 3022 case FB_HASH_ZERO: 3023 *arg = BCM_HASH_ZERO; 3024 break; 3025 case FB_HASH_LSB: 3026 *arg = BCM_HASH_LSB; 3027 break; 3028 case FB_HASH_CRC16_LOWER: 3029 *arg = BCM_HASH_CRC16L; 3030 break; 3031 case FB_HASH_CRC16_UPPER: 3032 *arg = BCM_HASH_CRC16U; 3033 break; 3034 case FB_HASH_CRC32_LOWER: 3035 *arg = BCM_HASH_CRC32L; 3036 break; 3037 case FB_HASH_CRC32_UPPER: 3038 *arg = BCM_HASH_CRC32U; 3039 break; 3040 } 3041 return BCM_E_NONE; 3042 } 3043 3044 3045 /* 3046 * Function: 3047 * _bcm_gh2_hashcontrol_set 3048 * Description: 3049 * Set the Hash Control for L2, L3 or Multipath type. 3050 * Parameters: 3051 * unit - StrataSwitch PCI device unit number (driver internal). 3052 * arg - BCM_HASH_CONTROL* 3053 * Returns: 3054 * BCM_E_xxxx 3055 */ 3056 3057 STATIC int 3058 _bcm_gh2_hashcontrol_set(int unit, int arg) 3059 { 3060 uint32 hash_control, val=0; 3061 3062 if (!soc_feature(unit, soc_feature_l3)) { 3063 if ((arg & BCM_HASH_CONTROL_MULTIPATH_L4PORTS) || 3064 (arg & BCM_HASH_CONTROL_MULTIPATH_DIP)) { 3065 return BCM_E_UNAVAIL; 3066 } 3067 } 3068 3069 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 3070 3071 val = (arg & BCM_HASH_CONTROL_MULTIPATH_L4PORTS) ? 1 : 0; 3072 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3073 USE_TCP_UDP_PORTSf, val); 3074 3075 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_USE_DIPf)) { 3076 val = (arg & BCM_HASH_CONTROL_MULTIPATH_DIP) ? 1 : 0; 3077 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3078 ECMP_HASH_USE_DIPf, val); 3079 3080 val = BCM_HASH_CONTROL_MULTIPATH_USERDEF_VAL(arg); 3081 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3082 ECMP_HASH_UDFf, val); 3083 } 3084 3085 val = (arg & BCM_HASH_CONTROL_TRUNK_UC_XGS2) ? 1 : 0; 3086 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3087 ENABLE_DRACO1_5_HASHf, val); 3088 3089 val = (arg & BCM_HASH_CONTROL_TRUNK_UC_SRCPORT) ? 1 : 0; 3090 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3091 UC_TRUNK_HASH_USE_SRC_PORTf, val); 3092 3093 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_DST) ? 1 : 0; 3094 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3095 NON_UC_TRUNK_HASH_DST_ENABLEf, val); 3096 3097 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_SRC) ? 1 : 0; 3098 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3099 NON_UC_TRUNK_HASH_SRC_ENABLEf, val); 3100 3101 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_MODPORT) ? 1 : 0; 3102 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3103 NON_UC_TRUNK_HASH_MOD_PORT_ENABLEf, val); 3104 3105 val = (arg & BCM_HASH_CONTROL_ECMP_ENHANCE) ? 1 : 0; 3106 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3107 ECMP_HASH_USE_RTAG7f, val); 3108 3109 val = (arg & BCM_HASH_CONTROL_TRUNK_NUC_ENHANCE) ? 1 : 0; 3110 soc_reg_field_set(unit, HASH_CONTROLr, &hash_control, 3111 NON_UC_TRUNK_HASH_USE_RTAG7f, val); 3112 3113 3114 BCM_IF_ERROR_RETURN(WRITE_HASH_CONTROLr(unit, hash_control)); 3115 3116 return BCM_E_NONE; 3117 } 3118 3119 3120 /* 3121 * Function: 3122 * _bcm_gh2_hashcontrol_get 3123 * Description: 3124 * Get the current Hash Control settings. 3125 * Parameters: 3126 * unit - StrataSwitch PCI device unit number (driver internal). 3127 * arg - Pointer to where the retrieved value will be written. 3128 * Returns: 3129 * BCM_E_xxxx 3130 */ 3131 3132 STATIC int 3133 _bcm_gh2_hashcontrol_get(int unit, int *arg) 3134 { 3135 uint32 hash_control, val=0; 3136 3137 *arg = 0; 3138 BCM_IF_ERROR_RETURN(READ_HASH_CONTROLr(unit, &hash_control)); 3139 3140 3141 if (soc_feature(unit, soc_feature_l3)) { 3142 if (soc_reg_field_valid(unit, HASH_CONTROLr, USE_TCP_UDP_PORTSf)) { 3143 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3144 USE_TCP_UDP_PORTSf); 3145 if (val) *arg |= BCM_HASH_CONTROL_MULTIPATH_L4PORTS; 3146 } 3147 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_USE_DIPf)) { 3148 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3149 ECMP_HASH_USE_DIPf); 3150 if (val) *arg |= BCM_HASH_CONTROL_MULTIPATH_DIP; 3151 } 3152 3153 if (soc_reg_field_valid(unit, HASH_CONTROLr, ECMP_HASH_UDFf)) { 3154 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3155 ECMP_HASH_UDFf); 3156 *arg |= BCM_HASH_CONTROL_MULTIPATH_USERDEF(val); 3157 } 3158 } 3159 3160 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3161 ENABLE_DRACO1_5_HASHf); 3162 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_UC_XGS2; 3163 3164 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3165 UC_TRUNK_HASH_USE_SRC_PORTf); 3166 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_UC_SRCPORT; 3167 3168 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3169 NON_UC_TRUNK_HASH_DST_ENABLEf); 3170 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_DST; 3171 3172 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3173 NON_UC_TRUNK_HASH_SRC_ENABLEf); 3174 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_SRC; 3175 3176 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3177 NON_UC_TRUNK_HASH_MOD_PORT_ENABLEf); 3178 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_MODPORT; 3179 3180 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3181 ECMP_HASH_USE_RTAG7f); 3182 if (val) *arg |= BCM_HASH_CONTROL_ECMP_ENHANCE; 3183 3184 val = soc_reg_field_get(unit, HASH_CONTROLr, hash_control, 3185 NON_UC_TRUNK_HASH_USE_RTAG7f); 3186 if (val) *arg |= BCM_HASH_CONTROL_TRUNK_NUC_ENHANCE; 3187 3188 return BCM_E_NONE; 3189 } 3190 3191 STATIC int 3192 _bcm_gh2_er_color_mode_set(int unit, bcm_port_t port, int arg) 3193 { 3194 uint32 val, oval, cfi_as_cng; 3195 uint64 rval64; 3196 3197 BCM_IF_ERROR_RETURN 3198 (READ_EGR_VLAN_CONTROL_1r(unit, port, &val)); 3199 3200 oval = val; 3201 3202 switch (arg) { 3203 case BCM_COLOR_PRIORITY: 3204 cfi_as_cng = 0; 3205 break; 3206 case BCM_COLOR_OUTER_CFI: 3207 cfi_as_cng = 0xf; 3208 break; 3209 case BCM_COLOR_INNER_CFI: 3210 if (soc_feature(unit, soc_feature_color_inner_cfi)) { 3211 cfi_as_cng = 0x0; 3212 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 3213 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3214 CFI_AS_CNGf, 0); 3215 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3216 CVLAN_CFI_AS_CNGf, 1); 3217 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, rval64)); 3218 } else { 3219 return BCM_E_UNAVAIL; 3220 } 3221 break; 3222 default: 3223 return BCM_E_PARAM; 3224 } 3225 3226 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &val, 3227 CFI_AS_CNGf, cfi_as_cng); 3228 if (oval != val) { 3229 BCM_IF_ERROR_RETURN 3230 (_bcm_esw_port_config_set(unit, port, 3231 _bcmPortCfiAsCng, 3232 cfi_as_cng)); 3233 BCM_IF_ERROR_RETURN 3234 (WRITE_EGR_VLAN_CONTROL_1r(unit, port, val)); 3235 } 3236 3237 return BCM_E_NONE; 3238 } 3239 3240 STATIC int 3241 _bcm_gh2_er_color_mode_get(int unit, bcm_port_t port, int *arg) 3242 { 3243 uint32 val, cfi_as_cng; 3244 uint64 rval64; 3245 int cvlan_cfi_as_cng = 0; 3246 if (soc_feature(unit, soc_feature_color_inner_cfi)) { 3247 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 3248 cvlan_cfi_as_cng = soc_reg64_field32_get(unit, ING_CONFIG_64r, rval64, 3249 CVLAN_CFI_AS_CNGf); 3250 } 3251 3252 BCM_IF_ERROR_RETURN 3253 (READ_EGR_VLAN_CONTROL_1r(unit, port, &val)); 3254 3255 cfi_as_cng = soc_reg_field_get(unit, EGR_VLAN_CONTROL_1r, val, 3256 CFI_AS_CNGf); 3257 if (cfi_as_cng == 0) { 3258 if (cvlan_cfi_as_cng && soc_feature(unit, soc_feature_color_inner_cfi)) { 3259 *arg = BCM_COLOR_INNER_CFI; 3260 } else { 3261 *arg = BCM_COLOR_PRIORITY; 3262 } 3263 } else { 3264 *arg = BCM_COLOR_OUTER_CFI; 3265 } 3266 return BCM_E_NONE; 3267 } 3268 3269 3270 STATIC int 3271 _bcm_gh2_mod_lb_set(int unit, bcm_port_t port, int arg) 3272 { 3273 if (soc_feature(unit, soc_feature_module_loopback)) { 3274 return _bcm_esw_port_config_set(unit, port, _bcmPortModuleLoopback, 3275 (arg ? 1 : 0)); 3276 } 3277 return BCM_E_UNAVAIL; 3278 } 3279 3280 STATIC int 3281 _bcm_gh2_mod_lb_get(int unit, bcm_port_t port, int *arg) 3282 { 3283 if (soc_feature(unit, soc_feature_module_loopback)) { 3284 return _bcm_esw_port_config_get(unit, port, _bcmPortModuleLoopback, 3285 arg); 3286 } 3287 return BCM_E_UNAVAIL; 3288 } 3289 3290 STATIC int 3291 _bcm_gh2_ing_rate_limit_ifg_set(int unit, bcm_port_t port, int arg) 3292 { 3293 if (arg > BCM_FB2_BMC_IFG_MAX) { 3294 arg = BCM_FB2_BMC_IFG_MAX; 3295 } else if (arg < 0) { 3296 return BCM_E_PARAM; 3297 } 3298 return soc_reg_field32_modify(unit, BKPMETERINGCONFIG_EXTr, port, 3299 IFG_ACCT_SELf, arg); 3300 } 3301 3302 3303 STATIC int 3304 _bcm_gh2_ing_rate_limit_ifg_get(int unit, bcm_port_t port, int *arg) 3305 { 3306 uint32 bmc_reg; 3307 BCM_IF_ERROR_RETURN 3308 (READ_BKPMETERINGCONFIG_EXTr(unit, port, &bmc_reg)); 3309 *arg = soc_reg_field_get(unit, BKPMETERINGCONFIG_EXTr, bmc_reg, 3310 IFG_ACCT_SELf); 3311 return BCM_E_NONE; 3312 } 3313 3314 3315 STATIC int 3316 _bcm_gh2_urpf_route_enable(int unit, int arg) 3317 { 3318 #ifdef INCLUDE_L3 3319 int orig_val, rv = BCM_E_NONE; 3320 uint32 reg_val; 3321 3322 if (!soc_feature(unit, soc_feature_urpf)) { 3323 return (BCM_E_UNAVAIL); 3324 } 3325 3326 BCM_IF_ERROR_RETURN(READ_L3_DEFIP_RPF_CONTROLr(unit, ®_val)); 3327 3328 /* Handle nothing changed case. */ 3329 orig_val = soc_reg_field_get(unit, L3_DEFIP_RPF_CONTROLr, 3330 reg_val, DEFIP_RPF_ENABLEf); 3331 if (orig_val == (arg ? 1 : 0)) { 3332 return (BCM_E_NONE); 3333 } 3334 3335 /* State changed -> Delete all the routes. */ 3336 BCM_IF_ERROR_RETURN(bcm_xgs3_defip_del_all(unit)); 3337 3338 /* Destroy Hash/Avl quick lookup structure. */ 3339 BCM_IF_ERROR_RETURN(bcm_xgs3_l3_fbx_defip_deinit(unit)); 3340 3341 /* Set urpf route enable bit. */ 3342 BCM_IF_ERROR_RETURN 3343 (soc_reg_field32_modify(unit, L3_DEFIP_RPF_CONTROLr, REG_PORT_ANY, 3344 DEFIP_RPF_ENABLEf, (arg ? 1 : 0))); 3345 3346 3347 /* Reinit Hash/Avl quick lookup structure. */ 3348 BCM_IF_ERROR_RETURN(bcm_xgs3_l3_fbx_defip_init(unit)); 3349 3350 /* Lock the DEFIP tables so the SOC TCAM scanning logic doesn't 3351 * trip up on the URPF reconfiguration. 3352 */ 3353 soc_mem_lock(unit, L3_DEFIPm); 3354 if (SOC_MEM_IS_ENABLED(unit, L3_DEFIP_PAIR_128m)) { 3355 soc_mem_lock(unit, L3_DEFIP_PAIR_128m); 3356 } 3357 3358 SOC_CONTROL_LOCK(unit); 3359 SOC_CONTROL(unit)->l3_defip_urpf = arg ? 1 : 0; 3360 SOC_CONTROL_UNLOCK(unit); 3361 3362 /* Clear h/w memory before use */ 3363 if (BCM_SUCCESS(rv)) { 3364 rv = soc_mem_clear(unit, L3_DEFIPm, MEM_BLOCK_ALL, 0); 3365 } 3366 if (SOC_MEM_IS_ENABLED(unit, L3_DEFIP_PAIR_128m)) { 3367 if (BCM_SUCCESS(rv)) { 3368 rv = soc_mem_clear(unit, L3_DEFIP_PAIR_128m, 3369 MEM_BLOCK_ALL, 0); 3370 } 3371 soc_mem_unlock(unit, L3_DEFIP_PAIR_128m); 3372 } 3373 3374 soc_mem_unlock(unit, L3_DEFIPm); 3375 /* Must release the locks before return. */ 3376 3377 return rv; 3378 #endif /* INCLUDE_L3 */ 3379 return (BCM_E_UNAVAIL); 3380 } 3381 3382 STATIC int 3383 _bcm_gh2_urpf_port_mode_set(int unit, bcm_port_t port, int arg) 3384 { 3385 if (!soc_feature(unit, soc_feature_urpf)) { 3386 return (BCM_E_UNAVAIL); 3387 } 3388 3389 switch (arg){ 3390 case BCM_SWITCH_URPF_DISABLE: 3391 case BCM_SWITCH_URPF_LOOSE: 3392 case BCM_SWITCH_URPF_STRICT: 3393 return _bcm_esw_port_config_set(unit, port, _bcmPortL3UrpfMode, arg); 3394 default: 3395 return (BCM_E_PARAM); 3396 } 3397 return (BCM_E_PARAM); 3398 } 3399 3400 STATIC int 3401 _bcm_gh2_urpf_def_gw_enable(int unit, bcm_port_t port, int arg) 3402 { 3403 int enable = (arg) ? TRUE : FALSE; 3404 3405 if (!soc_feature(unit, soc_feature_urpf)) { 3406 return (BCM_E_UNAVAIL); 3407 } 3408 3409 return _bcm_esw_port_config_set(unit, port, 3410 _bcmPortL3UrpfDefaultRoute, enable); 3411 } 3412 3413 STATIC int 3414 _bcm_gh2_prot_pkt_profile_set(int unit, soc_reg_t reg, bcm_port_t port, 3415 int count, soc_field_t *fields, uint32 *values) 3416 { 3417 soc_mem_t mem; 3418 port_tab_entry_t entry; 3419 int port_index, i; 3420 uint32 prot_pkt_ctrl, igmp_mld_pkt_ctrl, *rval_ptr; 3421 uint32 old_index, index; 3422 3423 if (reg == PROTOCOL_PKT_CONTROLr) { 3424 rval_ptr = &prot_pkt_ctrl; 3425 } else if (reg == IGMP_MLD_PKT_CONTROLr) { 3426 rval_ptr = &igmp_mld_pkt_ctrl; 3427 } else { 3428 return BCM_E_INTERNAL; 3429 } 3430 3431 mem = PORT_TABm; 3432 port_index = port; 3433 if (IS_CPU_PORT(unit, port)) { 3434 if (SOC_MEM_IS_VALID(unit, IPORT_TABLEm)) { 3435 mem = IPORT_TABLEm; 3436 } else { 3437 port_index = SOC_INFO(unit).cpu_hg_index; 3438 } 3439 } 3440 BCM_IF_ERROR_RETURN 3441 (soc_mem_read(unit, mem, MEM_BLOCK_ANY, port_index, &entry)); 3442 old_index = soc_mem_field32_get(unit, mem, &entry, PROTOCOL_PKT_INDEXf); 3443 3444 BCM_IF_ERROR_RETURN 3445 (_bcm_prot_pkt_ctrl_get(unit, old_index, &prot_pkt_ctrl, 3446 &igmp_mld_pkt_ctrl)); 3447 for (i = 0; i < count; i++) { 3448 soc_reg_field_set(unit, reg, rval_ptr, fields[i], values[i]); 3449 } 3450 BCM_IF_ERROR_RETURN 3451 (_bcm_prot_pkt_ctrl_add(unit, prot_pkt_ctrl, igmp_mld_pkt_ctrl, 3452 &index)); 3453 BCM_IF_ERROR_RETURN(_bcm_prot_pkt_ctrl_delete(unit, old_index)); 3454 return soc_mem_field32_modify(unit, PORT_TABm, port_index, 3455 PROTOCOL_PKT_INDEXf, index); 3456 } 3457 3458 STATIC int 3459 _bcm_gh2_protocol_pkt_index_get(int unit, bcm_port_t port, int *index) 3460 { 3461 port_tab_entry_t entry; 3462 soc_mem_t mem; 3463 int port_index; 3464 3465 if (!soc_mem_field_valid(unit, PORT_TABm, PROTOCOL_PKT_INDEXf)) { 3466 return BCM_E_INTERNAL; 3467 } 3468 3469 mem = PORT_TABm; 3470 port_index = port; 3471 if (IS_CPU_PORT(unit, port)) { 3472 if (SOC_MEM_IS_VALID(unit, IPORT_TABLEm)) { 3473 mem = IPORT_TABLEm; 3474 } else { 3475 port_index = SOC_INFO(unit).cpu_hg_index; 3476 } 3477 } 3478 BCM_IF_ERROR_RETURN 3479 (soc_mem_read(unit, mem, MEM_BLOCK_ANY, port_index, &entry)); 3480 *index = soc_mem_field32_get(unit, mem, &entry, PROTOCOL_PKT_INDEXf); 3481 return BCM_E_NONE; 3482 } 3483 3484 3485 STATIC int 3486 _bcm_gh2_prot_pkt_action_set(int unit, 3487 bcm_port_t port, 3488 bcm_switch_control_t type, 3489 int arg) 3490 { 3491 soc_field_t field; 3492 uint32 value; 3493 3494 value = arg ? 1 : 0; 3495 3496 switch(type) { 3497 case bcmSwitchArpReplyToCpu: 3498 field = ARP_REPLY_TO_CPUf; 3499 break; 3500 case bcmSwitchArpReplyDrop: 3501 field = ARP_REPLY_DROPf; 3502 break; 3503 case bcmSwitchArpRequestToCpu: 3504 field = ARP_REQUEST_TO_CPUf; 3505 break; 3506 case bcmSwitchArpRequestDrop: 3507 field = ARP_REQUEST_DROPf; 3508 break; 3509 case bcmSwitchNdPktToCpu: 3510 field = ND_PKT_TO_CPUf; 3511 break; 3512 case bcmSwitchNdPktDrop: 3513 field = ND_PKT_DROPf; 3514 break; 3515 case bcmSwitchDhcpPktToCpu: 3516 field = DHCP_PKT_TO_CPUf; 3517 break; 3518 case bcmSwitchDhcpPktDrop: 3519 field = DHCP_PKT_DROPf; 3520 break; 3521 default: 3522 return BCM_E_INTERNAL; 3523 } 3524 3525 return _bcm_gh2_prot_pkt_profile_set(unit, PROTOCOL_PKT_CONTROLr, port, 1, 3526 &field, &value); 3527 } 3528 3529 3530 3531 /* 3532 * Function: 3533 * _bcm_gh2_igmp_action_set 3534 * Description: 3535 * Set the IGMP/MLD registers 3536 * Parameters: 3537 * unit - StrataSwitch PCI device unit number (driver internal). 3538 * type - The desired configuration parameter to set. 3539 * arg - IGMP / MLD actions 3540 * Returns: 3541 * BCM_E_xxxx 3542 */ 3543 3544 STATIC int 3545 _bcm_gh2_igmp_action_set(int unit, 3546 bcm_port_t port, 3547 bcm_switch_control_t type, 3548 int arg) 3549 { 3550 uint32 values[3]; 3551 soc_field_t fields[3]; 3552 int idx; 3553 soc_reg_t reg = INVALIDr ; 3554 int fcount = 1; 3555 int value = (arg) ? 1 : 0; 3556 3557 for (idx = 0; idx < COUNTOF(values); idx++) { 3558 values[idx] = value; 3559 fields[idx] = INVALIDf; 3560 } 3561 3562 if (soc_feature(unit, soc_feature_igmp_mld_support)) { 3563 reg = IGMP_MLD_PKT_CONTROLr; 3564 /* Given control type select register field. */ 3565 switch (type) { 3566 case bcmSwitchIgmpPktToCpu: 3567 fields[0] = IGMP_REP_LEAVE_TO_CPUf; 3568 fields[1] = IGMP_QUERY_TO_CPUf; 3569 fields[2] = IGMP_UNKNOWN_MSG_TO_CPUf; 3570 fcount = 3; 3571 break; 3572 case bcmSwitchIgmpPktDrop: 3573 fields[0] = IGMP_REP_LEAVE_FWD_ACTIONf; 3574 fields[1] = IGMP_QUERY_FWD_ACTIONf; 3575 fields[2] = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 3576 fcount = 3; 3577 values[0] = values[1] = values[2] = 3578 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3579 break; 3580 case bcmSwitchMldPktToCpu: 3581 fields[0] = MLD_REP_DONE_TO_CPUf; 3582 fields[1] = MLD_QUERY_TO_CPUf; 3583 fcount = 2; 3584 break; 3585 case bcmSwitchMldPktDrop: 3586 fields[0] = MLD_REP_DONE_FWD_ACTIONf; 3587 fields[1] = MLD_QUERY_FWD_ACTIONf; 3588 fcount = 2; 3589 values[0] = 3590 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3591 break; 3592 case bcmSwitchV4ResvdMcPktToCpu: 3593 fields[0] = IPV4_RESVD_MC_PKT_TO_CPUf; 3594 break; 3595 case bcmSwitchV4ResvdMcPktFlood: 3596 fields[0] = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 3597 values[0] = 3598 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3599 break; 3600 case bcmSwitchV4ResvdMcPktDrop: 3601 fields[0] = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 3602 values[0] = 3603 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3604 break; 3605 case bcmSwitchV6ResvdMcPktToCpu: 3606 fields[0] = IPV6_RESVD_MC_PKT_TO_CPUf; 3607 break; 3608 case bcmSwitchV6ResvdMcPktFlood: 3609 fields[0] = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 3610 values[0] = 3611 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3612 break; 3613 case bcmSwitchV6ResvdMcPktDrop: 3614 fields[0] = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 3615 values[0] = 3616 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3617 break; 3618 case bcmSwitchIgmpReportLeaveDrop: 3619 fields[0] = IGMP_REP_LEAVE_FWD_ACTIONf; 3620 values[0] = 3621 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3622 break; 3623 case bcmSwitchIgmpReportLeaveFlood: 3624 fields[0] = IGMP_REP_LEAVE_FWD_ACTIONf; 3625 values[0] = 3626 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3627 break; 3628 case bcmSwitchIgmpReportLeaveToCpu: 3629 fields[0] = IGMP_REP_LEAVE_TO_CPUf; 3630 break; 3631 case bcmSwitchIgmpQueryDrop: 3632 fields[0] = IGMP_QUERY_FWD_ACTIONf; 3633 values[0] = 3634 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3635 break; 3636 case bcmSwitchIgmpQueryFlood: 3637 fields[0] = IGMP_QUERY_FWD_ACTIONf; 3638 values[0] = 3639 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3640 break; 3641 case bcmSwitchIgmpQueryToCpu: 3642 fields[0] = IGMP_QUERY_TO_CPUf; 3643 break; 3644 case bcmSwitchIgmpUnknownDrop: 3645 fields[0] = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 3646 values[0] = 3647 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3648 break; 3649 case bcmSwitchIgmpUnknownFlood: 3650 fields[0] = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 3651 values[0] = 3652 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3653 break; 3654 case bcmSwitchIgmpUnknownToCpu: 3655 fields[0] = IGMP_UNKNOWN_MSG_TO_CPUf; 3656 break; 3657 case bcmSwitchMldReportDoneDrop: 3658 fields[0] = MLD_REP_DONE_FWD_ACTIONf; 3659 values[0] = 3660 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3661 break; 3662 case bcmSwitchMldReportDoneFlood: 3663 fields[0] = MLD_REP_DONE_FWD_ACTIONf; 3664 values[0] = 3665 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3666 break; 3667 case bcmSwitchMldReportDoneToCpu: 3668 fields[0] = MLD_REP_DONE_TO_CPUf; 3669 break; 3670 case bcmSwitchMldQueryDrop: 3671 fields[0] = MLD_QUERY_FWD_ACTIONf; 3672 values[0] = 3673 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3674 break; 3675 case bcmSwitchMldQueryFlood: 3676 fields[0] = MLD_QUERY_FWD_ACTIONf; 3677 values[0] = 3678 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3679 break; 3680 case bcmSwitchMldQueryToCpu: 3681 fields[0] = MLD_QUERY_TO_CPUf; 3682 break; 3683 case bcmSwitchIpmcV4RouterDiscoveryDrop: 3684 fields[0] = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3685 values[0] = 3686 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3687 break; 3688 case bcmSwitchIpmcV4RouterDiscoveryFlood: 3689 fields[0] = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3690 values[0] = 3691 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3692 break; 3693 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 3694 fields[0] = IPV4_MC_ROUTER_ADV_PKT_TO_CPUf; 3695 break; 3696 case bcmSwitchIpmcV6RouterDiscoveryDrop: 3697 fields[0] = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3698 values[0] = 3699 (arg) ? BCM_SWITCH_DROP_VALUE : BCM_SWITCH_FORWARD_VALUE; 3700 break; 3701 case bcmSwitchIpmcV6RouterDiscoveryFlood: 3702 fields[0] = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3703 values[0] = 3704 (arg) ? BCM_SWITCH_FLOOD_VALUE : BCM_SWITCH_FORWARD_VALUE; 3705 break; 3706 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 3707 fields[0] = IPV6_MC_ROUTER_ADV_PKT_TO_CPUf; 3708 break; 3709 default: 3710 return (BCM_E_UNAVAIL); 3711 } 3712 } else if (soc_feature(unit, soc_feature_proto_pkt_ctrl)){ 3713 reg = PROTOCOL_PKT_CONTROLr; 3714 switch (type) { 3715 case bcmSwitchIgmpPktToCpu: 3716 fields[0] = IGMP_PKT_TO_CPUf; 3717 break; 3718 case bcmSwitchIgmpPktDrop: 3719 fields[0] = IGMP_PKT_DROPf; 3720 break; 3721 case bcmSwitchV4ResvdMcPktToCpu: 3722 fields[0] = IPV4_RESVD_MC_PKT_TO_CPUf; 3723 break; 3724 case bcmSwitchV4ResvdMcPktDrop: 3725 fields[0] = IPV4_RESVD_MC_PKT_DROPf; 3726 break; 3727 case bcmSwitchV6ResvdMcPktToCpu: 3728 fields[0] = IPV6_RESVD_MC_PKT_TO_CPUf; 3729 break; 3730 case bcmSwitchV6ResvdMcPktDrop: 3731 fields[0] = IPV6_RESVD_MC_PKT_DROPf; 3732 break; 3733 default: 3734 return (BCM_E_UNAVAIL); 3735 } 3736 } else { 3737 return (BCM_E_UNAVAIL); 3738 } 3739 3740 if (SOC_REG_INFO(unit, reg).regtype != soc_portreg) { 3741 return _bcm_gh2_prot_pkt_profile_set(unit, reg, port, fcount, fields, 3742 values); 3743 } else { 3744 return soc_reg_fields32_modify(unit, reg, port, fcount, fields, 3745 values); 3746 } 3747 } 3748 3749 3750 /* 3751 * Function: 3752 * _bcm_gh2_igmp_action_get 3753 * Description: 3754 * Get the IGMP/MLD registers 3755 * Parameters: 3756 * unit - StrataSwitch PCI device unit number (driver internal). 3757 * type - The desired configuration parameter to set. 3758 * *arg - IGMP / MLD actions 3759 * Returns: 3760 * BCM_E_xxxx 3761 */ 3762 3763 STATIC int 3764 _bcm_gh2_igmp_action_get(int unit, 3765 bcm_port_t port, 3766 bcm_switch_control_t type, 3767 int *arg) 3768 { 3769 uint32 igmp; 3770 soc_field_t field = INVALIDf; 3771 soc_reg_t reg = INVALIDr; 3772 int act_value = BCM_SWITCH_RESERVED_VALUE; 3773 int hw_value; 3774 3775 if (soc_feature(unit, soc_feature_igmp_mld_support)) { 3776 reg = IGMP_MLD_PKT_CONTROLr; 3777 /* Given control type select register field. */ 3778 switch (type) { 3779 case bcmSwitchIgmpPktToCpu: 3780 field = IGMP_REP_LEAVE_TO_CPUf; 3781 act_value = 1; 3782 break; 3783 case bcmSwitchIgmpPktDrop: 3784 field = IGMP_REP_LEAVE_FWD_ACTIONf; 3785 act_value = BCM_SWITCH_DROP_VALUE; 3786 break; 3787 case bcmSwitchMldPktToCpu: 3788 field = MLD_REP_DONE_TO_CPUf; 3789 act_value = 1; 3790 break; 3791 case bcmSwitchMldPktDrop: 3792 field = MLD_REP_DONE_FWD_ACTIONf; 3793 act_value = BCM_SWITCH_DROP_VALUE; 3794 break; 3795 case bcmSwitchV4ResvdMcPktToCpu: 3796 field = IPV4_RESVD_MC_PKT_TO_CPUf; 3797 act_value = 1; 3798 break; 3799 case bcmSwitchV4ResvdMcPktFlood: 3800 field = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 3801 act_value = BCM_SWITCH_FLOOD_VALUE; 3802 break; 3803 case bcmSwitchV4ResvdMcPktDrop: 3804 field = IPV4_RESVD_MC_PKT_FWD_ACTIONf; 3805 act_value = BCM_SWITCH_DROP_VALUE; 3806 break; 3807 case bcmSwitchV6ResvdMcPktToCpu: 3808 field = IPV6_RESVD_MC_PKT_TO_CPUf; 3809 act_value = 1; 3810 break; 3811 case bcmSwitchV6ResvdMcPktFlood: 3812 field = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 3813 act_value = BCM_SWITCH_FLOOD_VALUE; 3814 break; 3815 case bcmSwitchV6ResvdMcPktDrop: 3816 field = IPV6_RESVD_MC_PKT_FWD_ACTIONf; 3817 act_value = BCM_SWITCH_DROP_VALUE; 3818 break; 3819 case bcmSwitchIgmpReportLeaveDrop: 3820 field = IGMP_REP_LEAVE_FWD_ACTIONf; 3821 act_value = BCM_SWITCH_DROP_VALUE; 3822 break; 3823 case bcmSwitchIgmpReportLeaveFlood: 3824 field = IGMP_REP_LEAVE_FWD_ACTIONf; 3825 act_value = BCM_SWITCH_FLOOD_VALUE; 3826 break; 3827 case bcmSwitchIgmpReportLeaveToCpu: 3828 field = IGMP_REP_LEAVE_TO_CPUf; 3829 act_value = 1; 3830 break; 3831 case bcmSwitchIgmpQueryDrop: 3832 field = IGMP_QUERY_FWD_ACTIONf; 3833 act_value = BCM_SWITCH_DROP_VALUE; 3834 break; 3835 case bcmSwitchIgmpQueryFlood: 3836 field = IGMP_QUERY_FWD_ACTIONf; 3837 act_value = BCM_SWITCH_FLOOD_VALUE; 3838 break; 3839 case bcmSwitchIgmpQueryToCpu: 3840 field = IGMP_QUERY_TO_CPUf; 3841 act_value = 1; 3842 break; 3843 case bcmSwitchIgmpUnknownDrop: 3844 field = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 3845 act_value = BCM_SWITCH_DROP_VALUE; 3846 break; 3847 case bcmSwitchIgmpUnknownFlood: 3848 field = IGMP_UNKNOWN_MSG_FWD_ACTIONf; 3849 act_value = BCM_SWITCH_FLOOD_VALUE; 3850 break; 3851 case bcmSwitchIgmpUnknownToCpu: 3852 field = IGMP_UNKNOWN_MSG_TO_CPUf; 3853 act_value = 1; 3854 break; 3855 case bcmSwitchMldReportDoneDrop: 3856 field = MLD_REP_DONE_FWD_ACTIONf; 3857 act_value = BCM_SWITCH_DROP_VALUE; 3858 break; 3859 case bcmSwitchMldReportDoneFlood: 3860 field = MLD_REP_DONE_FWD_ACTIONf; 3861 act_value = BCM_SWITCH_FLOOD_VALUE; 3862 break; 3863 case bcmSwitchMldReportDoneToCpu: 3864 field = MLD_REP_DONE_TO_CPUf; 3865 act_value = 1; 3866 break; 3867 case bcmSwitchMldQueryDrop: 3868 field = MLD_QUERY_FWD_ACTIONf; 3869 act_value = BCM_SWITCH_DROP_VALUE; 3870 break; 3871 case bcmSwitchMldQueryFlood: 3872 field = MLD_QUERY_FWD_ACTIONf; 3873 act_value = BCM_SWITCH_FLOOD_VALUE; 3874 break; 3875 case bcmSwitchMldQueryToCpu: 3876 field = MLD_QUERY_TO_CPUf; 3877 act_value = 1; 3878 break; 3879 case bcmSwitchIpmcV4RouterDiscoveryDrop: 3880 field = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3881 act_value = BCM_SWITCH_DROP_VALUE; 3882 break; 3883 case bcmSwitchIpmcV4RouterDiscoveryFlood: 3884 field = IPV4_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3885 act_value = BCM_SWITCH_FLOOD_VALUE; 3886 break; 3887 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 3888 field = IPV4_MC_ROUTER_ADV_PKT_TO_CPUf; 3889 act_value = 1; 3890 break; 3891 case bcmSwitchIpmcV6RouterDiscoveryDrop: 3892 field = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3893 act_value = BCM_SWITCH_DROP_VALUE; 3894 break; 3895 case bcmSwitchIpmcV6RouterDiscoveryFlood: 3896 field = IPV6_MC_ROUTER_ADV_PKT_FWD_ACTIONf; 3897 act_value = BCM_SWITCH_FLOOD_VALUE; 3898 break; 3899 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 3900 field = IPV6_MC_ROUTER_ADV_PKT_TO_CPUf; 3901 act_value = 1; 3902 break; 3903 default: 3904 return (BCM_E_UNAVAIL); 3905 } 3906 } else if (soc_feature(unit, soc_feature_proto_pkt_ctrl)){ 3907 reg = PROTOCOL_PKT_CONTROLr; 3908 switch (type) { 3909 case bcmSwitchIgmpPktToCpu: 3910 field = IGMP_PKT_TO_CPUf; 3911 act_value = 1; 3912 break; 3913 case bcmSwitchIgmpPktDrop: 3914 field = IGMP_PKT_DROPf; 3915 act_value = 1; 3916 break; 3917 case bcmSwitchV4ResvdMcPktToCpu: 3918 field = IPV4_RESVD_MC_PKT_TO_CPUf; 3919 act_value = 1; 3920 break; 3921 case bcmSwitchV4ResvdMcPktDrop: 3922 field = IPV4_RESVD_MC_PKT_DROPf; 3923 act_value = 1; 3924 break; 3925 case bcmSwitchV6ResvdMcPktToCpu: 3926 field = IPV6_RESVD_MC_PKT_TO_CPUf; 3927 act_value = 1; 3928 break; 3929 case bcmSwitchV6ResvdMcPktDrop: 3930 field = IPV6_RESVD_MC_PKT_DROPf; 3931 act_value = 1; 3932 break; 3933 default: 3934 return (BCM_E_UNAVAIL); 3935 } 3936 } else { 3937 return (BCM_E_UNAVAIL); 3938 } 3939 3940 if (soc_reg_field_valid(unit, reg, field)) { 3941 if (soc_mem_field_valid(unit, PORT_TABm, PROTOCOL_PKT_INDEXf)) { 3942 int index; 3943 3944 BCM_IF_ERROR_RETURN 3945 (_bcm_gh2_protocol_pkt_index_get(unit, port, &index)); 3946 if(SOC_REG_INFO(unit, reg).regtype == soc_portreg) { 3947 BCM_IF_ERROR_RETURN(soc_reg32_get(unit, reg, (soc_port_t)index, 3948 0, &igmp)); 3949 } else { 3950 BCM_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 3951 index, &igmp)); 3952 } 3953 } else { 3954 3955 if (IGMP_MLD_PKT_CONTROLr == reg) { 3956 BCM_IF_ERROR_RETURN(READ_IGMP_MLD_PKT_CONTROLr(unit, port, &igmp)); 3957 } else { 3958 BCM_IF_ERROR_RETURN(READ_PROTOCOL_PKT_CONTROLr(unit, port, &igmp)); 3959 } 3960 } 3961 hw_value = soc_reg_field_get(unit, reg, igmp, field); 3962 *arg = (act_value == hw_value) ? 1 : 0; 3963 return (BCM_E_NONE); 3964 } 3965 3966 return (BCM_E_UNAVAIL); 3967 } 3968 3969 STATIC int 3970 _bcm_gh2_layered_qos_resolution_set(int unit, 3971 bcm_port_t port, 3972 bcm_switch_control_t type, 3973 int arg) 3974 { 3975 uint64 rval64; 3976 uint32 rval, value; 3977 3978 value = arg ? 0 : 1; /* layered resolution : serial resolution */ 3979 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 3980 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3981 IGNORE_PPD0_PRESERVE_QOSf, value); 3982 soc_reg64_field32_set(unit, ING_CONFIG_64r, &rval64, 3983 IGNORE_PPD2_PRESERVE_QOSf, value); 3984 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, rval64)); 3985 BCM_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 3986 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, 3987 DISABLE_PPD0_PRESERVE_QOSf, value); 3988 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, 3989 DISABLE_PPD2_PRESERVE_QOSf, value); 3990 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 3991 3992 return BCM_E_NONE; 3993 3994 } 3995 3996 3997 STATIC int 3998 _bcm_gh2_layered_qos_resolution_get(int unit, 3999 bcm_port_t port, 4000 bcm_switch_control_t type, 4001 int *arg) 4002 { 4003 uint64 rval64; 4004 BCM_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 4005 *arg = soc_reg64_field32_get(unit, ING_CONFIG_64r, rval64, 4006 IGNORE_PPD0_PRESERVE_QOSf) ? 0 : 1; 4007 return BCM_E_NONE; 4008 4009 } 4010 4011 /* 4012 * Update following reg/field 4013 * FP_METER_CONTROLr, PACKET_IFG_BYTESf 4014 * EGR_COUNTER_CONTROLr, PACKET_IFG_BYTESf 4015 * EGR_COUNTER_CONTROLr, PACKET_IFG_BYTES_2f 4016 * EFP_METER_CONTROL_2r, PACKET_IFG_BYTESf 4017 * EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf 4018 */ 4019 STATIC int 4020 _bcm_gh2_meter_adjust_set(int unit, bcm_port_t port, int arg) 4021 { 4022 int len, max_val; 4023 int i; 4024 soc_reg_t reg[4] = { FP_METER_CONTROLr, 4025 EGR_COUNTER_CONTROLr, 4026 EFP_METER_CONTROL_2r, 4027 EGR_SHAPING_CONTROLr }; 4028 4029 for (i = 0; i < 4 ; ++i ) { 4030 if (SOC_REG_FIELD_VALID(unit, reg[i], PACKET_IFG_BYTESf)) { 4031 len = soc_reg_field_length(unit, reg[i], PACKET_IFG_BYTESf); 4032 max_val = (1 << len) - 1; 4033 if (arg < 0 || arg > max_val) { 4034 return BCM_E_PARAM; 4035 } 4036 BCM_IF_ERROR_RETURN( 4037 soc_reg_field32_modify(unit, reg[i], port, 4038 PACKET_IFG_BYTESf, arg)); 4039 } 4040 4041 if (SOC_REG_FIELD_VALID(unit, reg[i], PACKET_IFG_BYTES_2f)) { 4042 len = soc_reg_field_length(unit, reg[i], PACKET_IFG_BYTES_2f); 4043 max_val = (1 << len) - 1; 4044 if (arg < 0 || arg > max_val) { 4045 return BCM_E_PARAM; 4046 } 4047 BCM_IF_ERROR_RETURN( 4048 soc_reg_field32_modify(unit, reg[i], port, 4049 PACKET_IFG_BYTES_2f, arg)); 4050 } 4051 } 4052 4053 return BCM_E_NONE; 4054 } 4055 4056 STATIC int 4057 _bcm_gh2_meter_adjust_get(int unit, bcm_port_t port, int *arg) 4058 { 4059 uint32 val; 4060 4061 BCM_IF_ERROR_RETURN( 4062 READ_EGR_COUNTER_CONTROLr(unit, port, &val)); 4063 *arg = soc_reg_field_get(unit, EGR_COUNTER_CONTROLr, val, 4064 PACKET_IFG_BYTESf); 4065 4066 return BCM_E_NONE; 4067 } 4068 4069 /* 4070 * Update following reg/field 4071 * EGR_SHAPING_CONTROLr, PACKET_IFG_BYTESf 4072 */ 4073 STATIC int 4074 _bcm_gh2_shaper_adjust_set(int unit, bcm_port_t port, int arg) 4075 { 4076 int len, max_val; 4077 soc_reg_t reg = EGR_SHAPING_CONTROLr; 4078 4079 len = soc_reg_field_length(unit, reg, PACKET_IFG_BYTESf); 4080 max_val = (1 << len) - 1; 4081 if (arg < 0 || arg > max_val) { 4082 return BCM_E_PARAM; 4083 } 4084 BCM_IF_ERROR_RETURN( 4085 soc_reg_field32_modify(unit, reg, port, 4086 PACKET_IFG_BYTESf, arg)); 4087 return BCM_E_NONE; 4088 } 4089 4090 STATIC int 4091 _bcm_gh2_shaper_adjust_get(int unit, bcm_port_t port, int *arg) 4092 { 4093 uint32 val; 4094 4095 BCM_IF_ERROR_RETURN( 4096 soc_reg32_get(unit, EGR_SHAPING_CONTROLr, port, 0, &val)); 4097 *arg = soc_reg_field_get(unit, EGR_SHAPING_CONTROLr, val, 4098 PACKET_IFG_BYTESf); 4099 4100 return BCM_E_NONE; 4101 } 4102 4103 4104 #ifdef BCM_WARM_BOOT_SUPPORT 4105 /* 4106 * Function: 4107 * _bcm_gh2_switch_encap_scache_sync 4108 * Purpose: 4109 * Syncs switch encap warmboot state to scache 4110 * Parameters: 4111 * unit - (IN) Unit number. 4112 * Returns: 4113 * BCM_E_XXX 4114 * Notes: 4115 */ 4116 int 4117 _bcm_gh2_switch_encap_scache_sync(int unit) 4118 { 4119 uint8 *scache_ptr; 4120 soc_scache_handle_t scache_handle; 4121 4122 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 4123 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_ENCAP); 4124 4125 BCM_IF_ERROR_RETURN 4126 (_bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 4127 0, &scache_ptr, 4128 BCM_SWITCH_WB_ENCAP_DEFAULT_VERSION, NULL)); 4129 if (soc_feature(unit, soc_feature_miml) || 4130 soc_feature(unit, soc_feature_custom_header)) { 4131 4132 BCM_IF_ERROR_RETURN(_bcm_hr3_switch_encap_sync(unit, &scache_ptr)); 4133 4134 } 4135 4136 return BCM_E_NONE; 4137 } 4138 4139 STATIC int 4140 _bcm_gh2_switch_control_sync(int unit, int arg) 4141 { 4142 int rv = BCM_E_NONE; 4143 int backup_size; 4144 uint8 *scache_module_ptr = NULL; 4145 4146 BCM_IF_ERROR_RETURN(soc_scache_module_max_alloc(unit, 4147 &scache_module_ptr, &backup_size)); 4148 { 4149 /* Call each module to write Level 2 Warm Boot info */ 4150 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_VLAN, (&scache_module_ptr), 4151 0, 0, backup_size, soc_scache_module_data_backup, rv); 4152 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_VLAN, 4153 _bcm_esw_vlan_sync, (&scache_module_ptr), rv); 4154 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_VLAN, (&scache_module_ptr), 4155 0, 0, soc_scache_module_dirty_set, rv); 4156 4157 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_STG, (&scache_module_ptr), 4158 0, 0, backup_size, soc_scache_module_data_backup, rv); 4159 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_STG, 4160 _bcm_esw_stg_sync, (&scache_module_ptr), rv); 4161 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_STG, (&scache_module_ptr), 4162 0, 0, soc_scache_module_dirty_set, rv); 4163 4164 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_COSQ, (&scache_module_ptr), 4165 0, 0, backup_size, soc_scache_module_data_backup, rv); 4166 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_COSQ, 4167 _bcm_esw_cosq_sync, (&scache_module_ptr), rv); 4168 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_COSQ, (&scache_module_ptr), 4169 0, 0, soc_scache_module_dirty_set, rv); 4170 4171 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_MIRROR, (&scache_module_ptr), 4172 0, 0, backup_size, soc_scache_module_data_backup, rv); 4173 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_MIRROR, 4174 _bcm_esw_mirror_sync, (&scache_module_ptr), rv); 4175 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_MIRROR, (&scache_module_ptr), 4176 0, 0, soc_scache_module_dirty_set, rv); 4177 4178 if (soc_feature(unit, soc_feature_virtual_switching) || 4179 soc_feature(unit, soc_feature_gport_service_counters) || 4180 soc_feature(unit, soc_feature_fast_init) || 4181 soc_feature(unit, soc_feature_int_common_init)){ 4182 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_COMMON, (&scache_module_ptr), 4183 0, 0, backup_size, soc_scache_module_data_backup, rv); 4184 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_COMMON, 4185 _bcm_common_scache_sync, (&scache_module_ptr), rv); 4186 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_COMMON, (&scache_module_ptr), 4187 0, 0, soc_scache_module_dirty_set, rv); 4188 } 4189 4190 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_UDF, (&scache_module_ptr), 4191 0, 0, backup_size, soc_scache_module_data_backup, rv); 4192 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_UDF, 4193 _bcm_esw_udf_scache_sync, (&scache_module_ptr), rv); 4194 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_UDF, (&scache_module_ptr), 4195 0, 0, soc_scache_module_dirty_set, rv); 4196 4197 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_SWITCH, (&scache_module_ptr), 4198 1, 4, backup_size,soc_scache_module_data_backup, rv); 4199 4200 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_SWITCH, 4201 _bcm_esw_switch_scache_sync, (&scache_module_ptr), rv); 4202 4203 if (soc_feature(unit, soc_feature_miml) || 4204 soc_feature(unit, soc_feature_custom_header)) { 4205 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_SWITCH, 4206 _bcm_gh2_switch_encap_scache_sync, (&scache_module_ptr), rv); 4207 } 4208 4209 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_SWITCH, (&scache_module_ptr), 4210 1, 4, soc_scache_module_dirty_set, rv); 4211 4212 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_FIELD, (&scache_module_ptr), 4213 0, 1, backup_size,soc_scache_module_data_backup, rv); 4214 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_FIELD, 4215 _bcm_esw_field_scache_sync, (&scache_module_ptr), rv); 4216 if (rv == BCM_E_UNAVAIL) { 4217 rv = BCM_E_NONE; 4218 } 4219 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_FIELD, (&scache_module_ptr), 4220 0, 1, soc_scache_module_dirty_set, rv); 4221 4222 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_RX, (&scache_module_ptr), 4223 0, 0, backup_size,soc_scache_module_data_backup, rv); 4224 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_RX, 4225 _bcm_esw_rx_sync, (&scache_module_ptr), rv); 4226 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_RX, (&scache_module_ptr), 4227 0, 0, soc_scache_module_dirty_set, rv); 4228 4229 #ifdef INCLUDE_L3 4230 if (soc_feature(unit, soc_feature_virtual_switching)) { 4231 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_VIRTUAL, (&scache_module_ptr), 4232 0, 0, backup_size,soc_scache_module_data_backup, rv); 4233 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_COMMON, 4234 _bcm_esw_virtual_sync, (&scache_module_ptr), rv); 4235 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_VIRTUAL, (&scache_module_ptr), 4236 0, 0, soc_scache_module_dirty_set, rv); 4237 } 4238 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_L3, (&scache_module_ptr), 4239 0, 0, backup_size,soc_scache_module_data_backup, rv); 4240 4241 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_L3, 4242 _bcm_esw_l3_sync, (&scache_module_ptr), rv); 4243 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_L3, (&scache_module_ptr), 4244 0, 0, soc_scache_module_dirty_set, rv); 4245 4246 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_IPMC, (&scache_module_ptr), 4247 0, 0, backup_size,soc_scache_module_data_backup, rv); 4248 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_IPMC, 4249 _bcm_esw_ipmc_sync, (&scache_module_ptr), rv); 4250 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_IPMC, (&scache_module_ptr), 4251 0, 0, soc_scache_module_dirty_set, rv); 4252 4253 if (soc_feature(unit, soc_feature_mpls)) { 4254 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_MPLS, (&scache_module_ptr), 4255 0, 0, backup_size,soc_scache_module_data_backup, rv); 4256 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_MPLS, 4257 _bcm_esw_mpls_sync, (&scache_module_ptr), rv); 4258 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_MPLS, (&scache_module_ptr), 4259 0, 0, soc_scache_module_dirty_set, rv); 4260 4261 } 4262 4263 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_MULTICAST, (&scache_module_ptr), 4264 0, 0, backup_size,soc_scache_module_data_backup, rv); 4265 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_MULTICAST, 4266 _bcm_esw_multicast_sync, (&scache_module_ptr), rv); 4267 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_MULTICAST, (&scache_module_ptr), 4268 0, 0, soc_scache_module_dirty_set, rv); 4269 4270 4271 #endif /* INCLUDE_L3 */ 4272 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_TRUNK, (&scache_module_ptr), 4273 0, 0, backup_size,soc_scache_module_data_backup, rv); 4274 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_TRUNK, 4275 _bcm_esw_trunk_sync, (&scache_module_ptr), rv); 4276 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_TRUNK, (&scache_module_ptr), 4277 0, 0, soc_scache_module_dirty_set, rv); 4278 4279 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_LINKSCAN, (&scache_module_ptr), 4280 0, 0, backup_size,soc_scache_module_data_backup, rv); 4281 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_LINKSCAN, 4282 _bcm_esw_link_sync,(&scache_module_ptr), rv); 4283 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_LINKSCAN, (&scache_module_ptr), 4284 0, 0, soc_scache_module_dirty_set, rv); 4285 4286 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_PORT, (&scache_module_ptr), 4287 BCM_PORT_WB_SCACHE_PART_MIN, 4288 BCM_PORT_WB_SCACHE_PART_MAX, 4289 backup_size,soc_scache_module_data_backup, rv); 4290 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_PORT, 4291 _bcm_esw_port_sync, (&scache_module_ptr), rv); 4292 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_PORT, (&scache_module_ptr), 4293 BCM_PORT_WB_SCACHE_PART_MIN, 4294 BCM_PORT_WB_SCACHE_PART_MAX, 4295 soc_scache_module_dirty_set, rv); 4296 4297 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_OAM, (&scache_module_ptr), 4298 0, 0, backup_size,soc_scache_module_data_backup, rv); 4299 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_OAM, 4300 _bcm_esw_oam_sync, (&scache_module_ptr), rv); 4301 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_OAM, (&scache_module_ptr), 4302 0, 0, soc_scache_module_dirty_set, rv); 4303 4304 4305 if (soc_feature(unit, soc_feature_time_support)) { 4306 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_TIME, (&scache_module_ptr), 4307 0, 0, backup_size,soc_scache_module_data_backup, rv); 4308 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_TIME, 4309 _bcm_time_scache_sync, (&scache_module_ptr), rv); 4310 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_TIME, (&scache_module_ptr), 4311 0, 0, soc_scache_module_dirty_set, rv); 4312 } 4313 4314 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_QOS, (&scache_module_ptr), 4315 0, 0, backup_size,soc_scache_module_data_backup, rv); 4316 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_QOS, 4317 _bcm_esw_qos_sync, (&scache_module_ptr), rv); 4318 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_QOS, (&scache_module_ptr), 4319 0, 0, soc_scache_module_dirty_set, rv); 4320 4321 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_STACK, (&scache_module_ptr), 4322 0, 0, backup_size,soc_scache_module_data_backup, rv); 4323 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_STK, 4324 _bcm_esw_stk_sync, (&scache_module_ptr), rv); 4325 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_STACK, (&scache_module_ptr), 4326 0, 0, soc_scache_module_dirty_set, rv); 4327 4328 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_SWITCH_CONTROL, (&scache_module_ptr), 4329 0, 0, backup_size,soc_scache_module_data_backup, rv); 4330 rv = _bcm_switch_control_scache_sync(unit); 4331 if (!_BCM_SYNC_SUCCESS(rv)) { 4332 LOG_CLI((BSL_META_U(unit, "Switch_control_sync failed\n"))); 4333 sal_free(scache_module_ptr); 4334 return rv; 4335 } 4336 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_SWITCH_CONTROL, (&scache_module_ptr), 4337 0, 0, soc_scache_module_dirty_set, rv); 4338 4339 #ifdef INCLUDE_L3 4340 if (soc_feature(unit, soc_feature_vxlan_lite)) { 4341 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_VXLAN, 4342 (&scache_module_ptr), 0, 0, backup_size, 4343 soc_scache_module_data_backup, rv); 4344 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_VXLAN, 4345 _bcm_esw_vxlan_sync, (&scache_module_ptr), rv); 4346 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_VXLAN, 4347 (&scache_module_ptr), 0, 0, 4348 soc_scache_module_dirty_set, rv); 4349 } 4350 4351 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_NIV, (&scache_module_ptr), 4352 0, 0, backup_size,soc_scache_module_data_backup, rv); 4353 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_NIV, 4354 _bcm_esw_niv_sync, (&scache_module_ptr), rv); 4355 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_NIV, (&scache_module_ptr), 4356 0, 0, soc_scache_module_dirty_set, rv); 4357 4358 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_SUBPORT, (&scache_module_ptr), 4359 0, 0, backup_size,soc_scache_module_data_backup, rv); 4360 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_SUBPORT, 4361 _bcm_esw_subport_sync, (&scache_module_ptr), rv); 4362 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_SUBPORT, (&scache_module_ptr), 4363 0, 0, soc_scache_module_dirty_set, rv); 4364 #endif /* INCLUDE_L3 */ 4365 4366 #if defined(INCLUDE_REGEX) 4367 /* No WARMBOOT support for REGEX */ 4368 #endif /* INCLUDE_REGEX */ 4369 4370 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_STAT, (&scache_module_ptr), 4371 0, 1, backup_size,soc_scache_module_data_backup, rv); 4372 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_STAT, 4373 _bcm_esw_stat_sync, (&scache_module_ptr), rv); 4374 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_STAT, (&scache_module_ptr), 4375 0, 1, soc_scache_module_dirty_set, rv); 4376 4377 #if defined(BCM_TSN_SUPPORT) 4378 if (soc_feature(unit, soc_feature_tsn)) { 4379 _BCM_SYNC_MODULE_BACKUP( 4380 unit, BCM_MODULE_TSN, (&scache_module_ptr), 4381 BCM_TSN_WB_SCACHE_PART_MIN, 4382 BCM_TSN_WB_SCACHE_PART_MAX, 4383 backup_size, soc_scache_module_data_backup, rv); 4384 _BCM_SYNC_MODULE( 4385 unit, SHR_BPROF_BCM_TSN, 4386 bcm_esw_tsn_sync, (&scache_module_ptr), rv); 4387 _BCM_SYNC_MODULE_DIRTY( 4388 unit, BCM_MODULE_TSN, (&scache_module_ptr), 4389 BCM_TSN_WB_SCACHE_PART_MIN, 4390 BCM_TSN_WB_SCACHE_PART_MAX, 4391 soc_scache_module_dirty_set, rv); 4392 } 4393 #endif /* BCM_TSN_SUPPORT */ 4394 4395 #if defined(BCM_GLOBAL_METER_SUPPORT) 4396 if (soc_feature(unit, soc_feature_global_meter)) { 4397 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_POLICER, (&scache_module_ptr), 4398 0, 0, backup_size,soc_scache_module_data_backup, rv); 4399 _BCM_SYNC_MODULE(unit, SHR_BPROF_BCM_GLB_METER, 4400 _bcm_esw_global_meter_policer_sync, (&scache_module_ptr), rv); 4401 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_POLICER, (&scache_module_ptr), 4402 0, 0, soc_scache_module_dirty_set, rv); 4403 } 4404 #endif /* BCM_GLOBAL_METER_SUPPORT */ 4405 } 4406 4407 if (_BCM_SYNC_SUCCESS(rv)) { 4408 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_MEMCACHE_HANDLE, (&scache_module_ptr), 4409 0, 0, backup_size,soc_scache_module_data_backup, rv); 4410 rv = _bcm_mem_scache_sync(unit); 4411 if (rv == BCM_E_UNAVAIL) { 4412 rv = BCM_E_NONE; 4413 } 4414 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_MEMCACHE_HANDLE, (&scache_module_ptr), 4415 0, 0, soc_scache_module_dirty_set, rv); 4416 } 4417 if (_BCM_SYNC_SUCCESS(rv)) { 4418 _BCM_SYNC_MODULE_BACKUP(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 4419 0, 0, backup_size,soc_scache_module_data_backup, rv); 4420 rv = soc_gh2_port_init_speed_scache_sync(unit); 4421 if (!_BCM_SYNC_SUCCESS(rv)) { 4422 LOG_CLI((BSL_META_U(unit, "soc port init speed sync failed\n"))); 4423 sal_free(scache_module_ptr); 4424 return rv; 4425 } 4426 _BCM_SYNC_MODULE_DIRTY(unit, SOC_SCACHE_FLEXIO_HANDLE, (&scache_module_ptr), 4427 0, 0, soc_scache_module_dirty_set, rv); 4428 } 4429 _BCM_SYNC_MODULE_BACKUP(unit, BCM_MODULE_L2, (&scache_module_ptr), 4430 0, 0, backup_size, soc_scache_module_data_backup, rv); 4431 rv = _bcm_esw_l2_wb_sync(unit); 4432 _BCM_SYNC_MODULE_DIRTY(unit, BCM_MODULE_L2, (&scache_module_ptr), 4433 0, 0, soc_scache_module_dirty_set, rv); 4434 4435 sal_free(scache_module_ptr); 4436 /* Now send all data to the persistent storage */ 4437 if (_BCM_SYNC_SUCCESS(rv)) { 4438 rv = soc_scache_commit(unit); 4439 } 4440 4441 /* Mark scache as clean */ 4442 SOC_CONTROL_LOCK(unit); 4443 SOC_CONTROL(unit)->scache_dirty = 0; 4444 SOC_CONTROL_UNLOCK(unit); 4445 4446 return rv; 4447 } 4448 4449 /* 4450 * Function: 4451 * _bcm_gh2_switch_encap_wb_scache_size_get 4452 * Purpose: 4453 * Returns required scache size for switch encap module 4454 * Parameters: 4455 * unit - (IN) Unit number. 4456 * req_scache_size - (OUT) Request scache size 4457 * Returns: 4458 * BCM_E_XXX 4459 * Notes: 4460 */ 4461 STATIC int 4462 _bcm_gh2_switch_encap_wb_scache_size_get(int unit, 4463 int *req_scache_size) 4464 { 4465 if (soc_feature(unit, soc_feature_miml) || 4466 soc_feature(unit, soc_feature_custom_header)) { 4467 #if defined(BCM_HURRICANE3_SUPPORT) 4468 BCM_IF_ERROR_RETURN( 4469 _bcm_hr3_switch_encap_wb_scache_size_get(unit, req_scache_size)); 4470 #endif 4471 } 4472 return BCM_E_NONE; 4473 } 4474 4475 /* 4476 * Function: 4477 * _bcm_gh2_switch_encap_wb_alloc 4478 * Purpose: 4479 * Allocates required scache size for the switch encap module recovery 4480 * Parameters: 4481 * unit - (IN) Unit number. 4482 * Returns: 4483 * BCM_E_XXX 4484 * Notes: 4485 */ 4486 STATIC int 4487 _bcm_gh2_switch_encap_wb_alloc(int unit) 4488 { 4489 int rv; 4490 uint8 *scache_ptr; 4491 soc_scache_handle_t scache_handle; 4492 int req_scache_size = 0; 4493 4494 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 4495 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_ENCAP); 4496 4497 rv = _bcm_gh2_switch_encap_wb_scache_size_get(unit, &req_scache_size); 4498 BCM_IF_ERROR_RETURN(rv); 4499 4500 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, TRUE, 4501 req_scache_size, &scache_ptr, BCM_SWITCH_WB_ENCAP_DEFAULT_VERSION, NULL); 4502 4503 if (BCM_E_NOT_FOUND == rv) { 4504 /* Proceed with Level 1 Warm Boot */ 4505 rv = BCM_E_NONE; 4506 } 4507 4508 BCM_IF_ERROR_RETURN(rv); 4509 4510 return BCM_E_NONE; 4511 } 4512 4513 /* 4514 * Function: 4515 * _bcm_gh2_switch_encap_reinit 4516 * Purpose: 4517 * Recovers switch encap warmboot state from scache 4518 * Parameters: 4519 * unit - (IN) Unit number. 4520 * Returns: 4521 * BCM_E_XXX 4522 * Notes: 4523 */ 4524 STATIC int 4525 _bcm_gh2_switch_encap_reinit(int unit) 4526 { 4527 int rv = BCM_E_INTERNAL; 4528 uint8 *scache_ptr; 4529 uint16 recovered_ver = 0; 4530 soc_scache_handle_t scache_handle; 4531 4532 SOC_SCACHE_HANDLE_SET(scache_handle, unit, 4533 BCM_MODULE_SWITCH, BCM_SWITCH_WB_SCACHE_PART_ENCAP); 4534 4535 rv = _bcm_esw_scache_ptr_get(unit, scache_handle, FALSE, 4536 0, &scache_ptr, 4537 BCM_SWITCH_WB_ENCAP_DEFAULT_VERSION, &recovered_ver); 4538 4539 if (rv == BCM_E_NOT_FOUND) { 4540 return _bcm_gh2_switch_encap_wb_alloc(unit); 4541 } else if (rv == BCM_E_NONE) { 4542 if (recovered_ver >= BCM_SWITCH_WB_ENCAP_VERSION_1_0) { 4543 #if defined(BCM_HURRICANE3_SUPPORT) 4544 BCM_IF_ERROR_RETURN(_bcm_hr3_switch_encap_reinit(unit, &scache_ptr)); 4545 #endif /* BCM_HURRICANE3_SUPPORT */ 4546 } 4547 } 4548 4549 return rv; 4550 } 4551 4552 /* 4553 * Function: 4554 * bcmi_gh2_switch_vxlan_tpid_reinit 4555 * Description: 4556 * Recovers VXLAN tpid information 4557 * Parameters: 4558 * unit - (IN) Device Number 4559 * Returns: 4560 * BCM_E_xxx 4561 */ 4562 STATIC int 4563 bcmi_gh2_switch_vxlan_tpid_reinit(int unit) 4564 { 4565 uint64 reg_val64; 4566 int tpid_enable, tpid_index; 4567 4568 /* Recover TPID reference count from ING_VXLAN_CONTROLr */ 4569 COMPILER_64_ZERO(reg_val64); 4570 BCM_IF_ERROR_RETURN(READ_ING_VXLAN_CONTROLr(unit, ®_val64)); 4571 4572 tpid_enable = soc_reg64_field32_get(unit, ING_VXLAN_CONTROLr, 4573 reg_val64, 4574 PAYLOAD_OUTER_TPID_ENABLEf); 4575 4576 tpid_index = 0; 4577 while (tpid_enable) { 4578 if (tpid_enable & 0x1) { 4579 BCM_IF_ERROR_RETURN( 4580 _bcm_fb2_outer_tpid_tab_ref_count_add(unit, tpid_index, 1)); 4581 } 4582 tpid_enable >>= 1; 4583 tpid_index++; 4584 } 4585 4586 return BCM_E_NONE; 4587 } 4588 4589 /* 4590 * Function: 4591 * bcmi_gh2_switch_wb_alloc 4592 * Purpose: 4593 * Allocates required scache size for the switch module recovery 4594 * Parameters: 4595 * unit - (IN) Device Number 4596 * Returns: 4597 * BCM_E_XXX 4598 */ 4599 STATIC int 4600 bcmi_gh2_switch_wb_alloc(int unit) 4601 { 4602 if (soc_feature(unit, soc_feature_miml) || 4603 soc_feature(unit, soc_feature_custom_header)) { 4604 BCM_IF_ERROR_RETURN(_bcm_gh2_switch_encap_wb_alloc(unit)); 4605 } 4606 4607 return BCM_E_NONE; 4608 } 4609 4610 /* 4611 * Function: 4612 * bcmi_gh2_switch_reinit 4613 * Purpose: 4614 * Recovers switch warmboot state from scache 4615 * Parameters: 4616 * unit - (IN) Device Number 4617 * Returns: 4618 * BCM_E_XXX 4619 */ 4620 STATIC int 4621 bcmi_gh2_switch_reinit(int unit) 4622 { 4623 if (soc_feature(unit, soc_feature_miml) || 4624 soc_feature(unit, soc_feature_custom_header)) { 4625 BCM_IF_ERROR_RETURN(_bcm_gh2_switch_encap_reinit(unit)); 4626 } 4627 4628 if (soc_feature(unit, soc_feature_vxlan_lite)) { 4629 BCM_IF_ERROR_RETURN(bcmi_gh2_switch_vxlan_tpid_reinit(unit)); 4630 } 4631 4632 return BCM_E_NONE; 4633 } 4634 4635 #endif /* WARM_BOOT_SUPPORT */ 4636 4637 static uint8 *_mod_type_table[BCM_LOCAL_UNITS_MAX]; 4638 STATIC int 4639 _bcm_gh2_switch_module_type_set(int unit, bcm_module_t mod, uint32 mod_type) 4640 { 4641 int modid_cnt; 4642 4643 if ((mod > SOC_MODID_MAX(unit)) || (mod_type != BCM_SWITCH_MODULE_XGS3)) { 4644 return BCM_E_PARAM; 4645 } else { 4646 if (NULL == _mod_type_table[unit]) { 4647 if (SOC_MODID_MAX(unit)) { 4648 modid_cnt = SOC_MODID_MAX(unit); 4649 } else { 4650 modid_cnt = 1; 4651 } 4652 _mod_type_table[unit] = (uint8 *)sal_alloc( 4653 (sizeof(uint8) * modid_cnt), "MOD TYPE"); 4654 if (NULL == _mod_type_table[unit]) { 4655 return BCM_E_MEMORY; 4656 } 4657 sal_memset(_mod_type_table[unit], BCM_SWITCH_MODULE_UNKNOWN, 4658 (sizeof(uint8) * modid_cnt)); 4659 } 4660 _mod_type_table[unit][mod] = mod_type; 4661 } 4662 return BCM_E_NONE; 4663 } 4664 4665 STATIC int 4666 _bcm_gh2_switch_module_type_get(int unit, bcm_module_t mod, uint32 *mod_type) 4667 { 4668 *mod_type = BCM_SWITCH_MODULE_UNKNOWN; 4669 if (mod > SOC_MODID_MAX(unit)) { 4670 return BCM_E_PARAM; 4671 } else { 4672 if (NULL != _mod_type_table[unit]) { 4673 *mod_type = _mod_type_table[unit][mod]; 4674 } 4675 } 4676 return BCM_E_NONE; 4677 } 4678 4679 /* 4680 * Bulk clear of various hit bit tables 4681 */ 4682 STATIC int 4683 _bcm_gh2_switch_hit_clear_set(int unit, bcm_switch_control_t type, int arg) 4684 { 4685 if (arg != 1) { 4686 return BCM_E_PARAM; 4687 } 4688 4689 switch (type) { 4690 case bcmSwitchL2HitClear: 4691 CLEARMEM(unit, L2_HITSA_ONLYm); 4692 CLEARMEM(unit, L2_HITDA_ONLYm); 4693 return BCM_E_NONE; 4694 4695 break; 4696 case bcmSwitchL2SrcHitClear: 4697 CLEARMEM(unit, L2_HITSA_ONLYm); 4698 return BCM_E_NONE; 4699 break; 4700 case bcmSwitchL2DstHitClear: 4701 CLEARMEM(unit, L2_HITDA_ONLYm); 4702 return BCM_E_NONE; 4703 break; 4704 case bcmSwitchL3HostHitClear: 4705 CLEARMEM(unit, L3_ENTRY_HIT_ONLYm); 4706 return BCM_E_NONE; 4707 break; 4708 case bcmSwitchL3RouteHitClear: 4709 CLEARMEM(unit, L3_DEFIP_HIT_ONLYm); 4710 CLEARMEM(unit, L3_DEFIP_128_HIT_ONLYm); 4711 return BCM_E_NONE; 4712 break; 4713 default: 4714 break; 4715 } 4716 4717 return BCM_E_UNAVAIL; 4718 } 4719 4720 #undef CLEARMEM 4721 4722 /* 4723 * Return an error if a hit clear is not supportable on this device 4724 */ 4725 STATIC int 4726 _bcm_gh2_switch_hit_clear_get(int unit, bcm_switch_control_t type, int *arg) 4727 { 4728 int rv; 4729 4730 rv = BCM_E_UNAVAIL; 4731 4732 switch (type) { 4733 case bcmSwitchL2HitClear: 4734 rv = BCM_E_NONE; 4735 break; 4736 case bcmSwitchL2SrcHitClear: 4737 rv = BCM_E_NONE; 4738 break; 4739 case bcmSwitchL2DstHitClear: 4740 rv = BCM_E_NONE; 4741 break; 4742 case bcmSwitchL3HostHitClear: 4743 if (!soc_feature(unit, soc_feature_l3) || 4744 soc_feature(unit, soc_feature_fp_based_routing)) { 4745 break; 4746 } 4747 rv = BCM_E_NONE; 4748 break; 4749 case bcmSwitchL3RouteHitClear: 4750 if (!soc_feature(unit, soc_feature_l3) || 4751 soc_feature(unit, soc_feature_fp_based_routing)) { 4752 break; 4753 } 4754 rv = BCM_E_NONE; 4755 break; 4756 default: 4757 break; 4758 } 4759 if (rv == BCM_E_NONE && arg != NULL) { 4760 *arg = 0; 4761 } 4762 return rv; 4763 } 4764 4765 #if (defined(BCM_RCPU_SUPPORT) || defined(BCM_OOB_RCPU_SUPPORT)) && \ 4766 defined(BCM_XGS3_SWITCH_SUPPORT) 4767 /* 4768 * Function: 4769 * _bcm_gh2_rcpu_switch_regall_idx_set 4770 * Description: 4771 * Helper function to set register to all ones if arg is non zero 4772 * and to all zeros otherwise. 4773 * Parameters: 4774 * unit - Device unit number 4775 * reg - The desired register to program 4776 * idx - The register index 4777 * arg - The value with which decission is made 4778 * Returns: 4779 * BCM_E_xxx 4780 */ 4781 STATIC int 4782 _bcm_gh2_rcpu_switch_regall_idx_set(int unit, 4783 soc_reg_t reg, 4784 int idx, 4785 soc_field_t field, 4786 int arg) 4787 { 4788 uint32 raddr, rval, value, width; 4789 4790 rval = 0; 4791 if (arg) { 4792 width = soc_reg_field_length(unit, reg, field); 4793 if (32 == width) { 4794 value = 0xffffffff; 4795 } else { 4796 value = (1 << width) - 1; 4797 } 4798 soc_reg_field_set(unit, reg, &rval, field, value); 4799 } 4800 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, idx); 4801 return soc_pci_write(unit, raddr, rval); 4802 } 4803 4804 /* 4805 * Function: 4806 * _bcm_gh2_rcpu_switch_regall_idx_get 4807 * Description: 4808 * Helper function to return arg = 1 if register is set to all ones 4809 * and to zero otherwise. 4810 * Parameters: 4811 * unit - Device unit number 4812 * reg - The desired register to read 4813 * arg - The value returnrd 4814 * Returns: 4815 * BCM_E_xxx 4816 */ 4817 STATIC int 4818 _bcm_gh2_rcpu_switch_regall_idx_get(int unit, soc_reg_t reg, int idx, int *arg) 4819 { 4820 uint32 raddr, rval; 4821 4822 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, idx); 4823 /* coverity[result_independent_of_operands] */ 4824 BCM_IF_ERROR_RETURN( 4825 soc_pci_getreg(unit, raddr, &rval)); 4826 4827 *arg = (!rval) ? 0 : 1; 4828 4829 return BCM_E_NONE; 4830 } 4831 4832 4833 /* 4834 * Function: 4835 * _bcm_gh2_rcpu_switch_regall_set 4836 * Description: 4837 * Helper function to set register to all ones if arg is non zero 4838 * and to all zeros otherwise. 4839 * Parameters: 4840 * unit - Device unit number 4841 * reg - The desired register to program 4842 * arg - The value with which decission is made 4843 * Returns: 4844 * BCM_E_xxx 4845 */ 4846 STATIC int 4847 _bcm_gh2_rcpu_switch_regall_set(int unit, soc_reg_t reg, soc_field_t field, int arg) 4848 { 4849 return _bcm_gh2_rcpu_switch_regall_idx_set(unit, reg, 0, field, arg); 4850 } 4851 4852 STATIC int 4853 _bcm_gh2_rcpu_switch_regall_get(int unit, soc_reg_t reg, int *arg) 4854 { 4855 return _bcm_gh2_rcpu_switch_regall_idx_get(unit, reg, 0, arg); 4856 } 4857 4858 /* 4859 * Function: 4860 * _bcm_gh2_rcpu_switch_mac_lo_set 4861 * Description: 4862 * Set the low 24 bits of MAC address field for RCPU MAC registers 4863 * Parameters: 4864 * unit - StrataSwitch PCI device unit number (driver internal). 4865 * port - port number. 4866 * type - The required switch control type to set the mac for 4867 * mac_lo - MAC address 4868 * Returns: 4869 * BCM_E_xxxx 4870 */ 4871 4872 STATIC int 4873 _bcm_gh2_rcpu_switch_mac_lo_set(int unit, 4874 bcm_switch_control_t type, 4875 uint32 mac_lo) 4876 { 4877 uint32 regval, fieldval; 4878 soc_reg_t reg = INVALIDr ; 4879 soc_field_t f_lo = INVALIDf; 4880 4881 4882 /* Given control type select register. */ 4883 switch (type) { 4884 case bcmSwitchRemoteCpuLocalMacNonOui: 4885 reg = CMIC_PKT_LMAC0_LOr; 4886 f_lo = MAC0_LOf; 4887 break; 4888 case bcmSwitchRemoteCpuDestMacNonOui: 4889 reg = CMIC_PKT_RMACr; 4890 f_lo = MAC_LOf; 4891 break; 4892 default: 4893 return BCM_E_PARAM; 4894 } 4895 /* coverity[result_independent_of_operands] */ 4896 SOC_IF_ERROR_RETURN( 4897 soc_pci_getreg(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), 4898 ®val)); 4899 4900 fieldval = soc_reg_field_get(unit, reg, regval, f_lo); 4901 fieldval &= 0xff000000; 4902 fieldval |= ((mac_lo << 8) >> 8); 4903 soc_reg_field_set(unit, reg, ®val, f_lo, fieldval); 4904 4905 return soc_pci_write(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), 4906 regval); 4907 } 4908 4909 /* 4910 * Function: 4911 * _bcm_gh2_rcpu_switch_mac_lo_get 4912 * Description: 4913 * Get the lower 24 bits of MAC address field for RCPU MAC registers 4914 * Parameters: 4915 * unit - StrataSwitch PCI device unit number (driver internal). 4916 * port - port number. 4917 * type - The required switch control type to get MAC for 4918 * arg - arg to get the lower MAC address 4919 * Returns: 4920 * BCM_E_xxxx 4921 */ 4922 4923 STATIC int 4924 _bcm_gh2_rcpu_switch_mac_lo_get(int unit, 4925 bcm_switch_control_t type, 4926 int *arg) 4927 { 4928 soc_reg_t reg = INVALIDr ; 4929 soc_field_t f_lo = INVALIDf; 4930 uint32 regval, mac; 4931 4932 /* Given control type select register. */ 4933 switch (type) { 4934 case bcmSwitchRemoteCpuLocalMacNonOui: 4935 reg = CMIC_PKT_LMAC0_LOr; 4936 f_lo = MAC0_LOf; 4937 break; 4938 case bcmSwitchRemoteCpuDestMacNonOui: 4939 reg = CMIC_PKT_RMACr; 4940 f_lo = MAC_LOf; 4941 break; 4942 default: 4943 return BCM_E_PARAM; 4944 } 4945 /* coverity[result_independent_of_operands] */ 4946 SOC_IF_ERROR_RETURN( 4947 soc_pci_getreg(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), 4948 ®val)); 4949 mac = soc_reg_field_get(unit, reg, regval, f_lo); 4950 4951 *arg = (mac << 8) >> 8; 4952 4953 return BCM_E_NONE; 4954 } 4955 4956 4957 /* 4958 * Function: 4959 * _bcm_gh2_rcpu_switch_mac_hi_set 4960 * Description: 4961 * Set the upper 24 bits of MAC address field for RCPU registers 4962 * Parameters: 4963 * unit - StrataSwitch PCI device unit number (driver internal). 4964 * port - port number. 4965 * type - The required switch control type to set upper MAC for 4966 * mac_hi - MAC address 4967 * Returns: 4968 * BCM_E_xxxx 4969 */ 4970 4971 STATIC int 4972 _bcm_gh2_rcpu_switch_mac_hi_set(int unit, 4973 bcm_switch_control_t type, 4974 uint32 mac_hi) 4975 { 4976 soc_reg_t reg1, reg2; 4977 soc_field_t f_lo, f_hi; 4978 uint32 fieldval, regval1, regval2, raddr1, raddr2; 4979 4980 reg1 = reg2 = INVALIDr; 4981 4982 /* Given control type select register. */ 4983 switch (type) { 4984 case bcmSwitchRemoteCpuLocalMacOui: 4985 reg1 = CMIC_PKT_LMAC0_LOr; 4986 reg2 = CMIC_PKT_LMAC0_HIr; 4987 f_lo = MAC0_LOf; 4988 f_hi = MAC0_HIf; 4989 break; 4990 case bcmSwitchRemoteCpuDestMacOui: 4991 reg1 = CMIC_PKT_RMACr; 4992 reg2 = CMIC_PKT_RMAC_HIr; 4993 f_lo = MAC_LOf; 4994 f_hi = MAC_HIf; 4995 break; 4996 default: 4997 return BCM_E_PARAM; 4998 } 4999 5000 regval1 = regval2 = 0; 5001 5002 raddr1 = soc_reg_addr(unit, reg1, REG_PORT_ANY, 0); 5003 raddr2 = soc_reg_addr(unit, reg2, REG_PORT_ANY, 0); 5004 /* coverity[result_independent_of_operands] */ 5005 BCM_IF_ERROR_RETURN( 5006 soc_pci_getreg(unit, raddr1, ®val1)); 5007 /* coverity[result_independent_of_operands] */ 5008 BCM_IF_ERROR_RETURN( 5009 soc_pci_getreg(unit, raddr2, ®val2)); 5010 5011 fieldval = (mac_hi << 24); 5012 soc_reg_field_set(unit, reg1, ®val1, f_lo, fieldval); 5013 fieldval = (mac_hi >> 8) & 0xffff; 5014 soc_reg_field_set(unit, reg2, ®val2, f_hi, fieldval); 5015 /* coverity[result_independent_of_operands] */ 5016 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr1, regval1)); 5017 /* coverity[result_independent_of_operands] */ 5018 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr2, regval2)); 5019 5020 return BCM_E_NONE; 5021 } 5022 5023 /* 5024 * Function: 5025 * _bcm_gh2_rcpu_switch_mac_hi_get 5026 * Description: 5027 * Get the upper 24 bits of MAC address field for RCPU MAC registers 5028 * Parameters: 5029 * unit - StrataSwitch PCI device unit number (driver internal). 5030 * port - port number. 5031 * type - The required switch control type to get MAC for 5032 * arg - arg to get the upper MAC address 5033 * Returns: 5034 * BCM_E_xxxx 5035 */ 5036 5037 STATIC int 5038 _bcm_gh2_rcpu_switch_mac_hi_get(int unit, 5039 bcm_switch_control_t type, 5040 int *arg) 5041 { 5042 soc_reg_t reg1, reg2; 5043 soc_field_t f_lo, f_hi; 5044 uint32 mac, regval1, regval2; 5045 5046 reg1 = reg2 = INVALIDr; 5047 5048 /* Given control type select register. */ 5049 switch (type) { 5050 case bcmSwitchRemoteCpuLocalMacOui: 5051 reg1 = CMIC_PKT_LMAC0_LOr; 5052 reg2 = CMIC_PKT_LMAC0_HIr; 5053 f_lo = MAC0_LOf; 5054 f_hi = MAC0_HIf; 5055 break; 5056 case bcmSwitchRemoteCpuDestMacOui: 5057 reg1 = CMIC_PKT_RMACr; 5058 reg2 = CMIC_PKT_RMAC_HIr; 5059 f_lo = MAC_LOf; 5060 f_hi = MAC_HIf; 5061 break; 5062 default: 5063 return BCM_E_PARAM; 5064 } 5065 /* coverity[result_independent_of_operands] */ 5066 SOC_IF_ERROR_RETURN( 5067 soc_pci_getreg(unit, soc_reg_addr(unit, reg1, REG_PORT_ANY, 0), 5068 ®val1)); 5069 mac = (soc_reg_field_get(unit, reg1, regval1, f_lo) >> 24); 5070 /* coverity[result_independent_of_operands] */ 5071 SOC_IF_ERROR_RETURN( 5072 soc_pci_getreg(unit, soc_reg_addr(unit, reg2, REG_PORT_ANY, 0), 5073 ®val2)); 5074 5075 mac |= (soc_reg_field_get(unit, reg2, regval2, f_hi) << 8); 5076 5077 *arg = (int)mac; 5078 5079 return BCM_E_NONE; 5080 } 5081 5082 5083 /* 5084 * Function: 5085 * _bcm_gh2_rcpu_switch_vlan_tpid_sig_set 5086 * Description: 5087 * Helper function to set VLAN, TPID ot Signature for RCPU 5088 * Parameters: 5089 * unit - Device unit number 5090 * type - The desired configuration parameter to modify 5091 * arg - The value to set 5092 * Returns: 5093 * BCM_E_xxx 5094 */ 5095 STATIC int 5096 _bcm_gh2_rcpu_switch_vlan_tpid_sig_set(int unit, 5097 bcm_switch_control_t type, 5098 int arg) 5099 { 5100 soc_reg_t reg = INVALIDr; 5101 soc_field_t field = INVALIDf; 5102 uint32 value, raddr, rval; 5103 5104 if (!soc_feature(unit, soc_feature_rcpu_1)) { 5105 return BCM_E_UNAVAIL; 5106 } 5107 5108 switch (type) { 5109 case bcmSwitchRemoteCpuVlan: 5110 reg = CMIC_PKT_VLANr; 5111 field = VLAN_IDf; 5112 value = (arg & 0xffff); 5113 break; 5114 case bcmSwitchRemoteCpuTpid: 5115 reg = CMIC_PKT_VLANr; 5116 field = TPIDf; 5117 value = (arg & 0xffff); 5118 break; 5119 case bcmSwitchRemoteCpuSignature: 5120 reg = CMIC_PKT_ETHER_SIGr; 5121 field = SIGNATUREf; 5122 value = (arg & 0xffff); 5123 break; 5124 case bcmSwitchRemoteCpuEthertype: 5125 reg = CMIC_PKT_ETHER_SIGr; 5126 field = ETHERTYPEf; 5127 value = (arg & 0xffff); 5128 break; 5129 default: 5130 return BCM_E_PARAM; 5131 } 5132 5133 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 5134 /* coverity[result_independent_of_operands] */ 5135 BCM_IF_ERROR_RETURN( 5136 soc_pci_getreg(unit, raddr, &rval)); 5137 soc_reg_field_set(unit, reg, &rval, field, value); 5138 5139 return soc_pci_write(unit, raddr, rval); 5140 } 5141 5142 /* 5143 * Function: 5144 * _bcm_gh2_rcpu_switch_vlan_tpid_sig_get 5145 * Description: 5146 * Helper function to get VLAN, TPID ot Signature for RCPU 5147 * Parameters: 5148 * unit - Device unit number 5149 * type - The desired configuration parameter to get 5150 * arg - The value returned 5151 * Returns: 5152 * BCM_E_xxx 5153 */ 5154 STATIC int 5155 _bcm_gh2_rcpu_switch_vlan_tpid_sig_get(int unit, 5156 bcm_switch_control_t type, 5157 int *arg) 5158 { 5159 soc_reg_t reg; 5160 soc_field_t field; 5161 uint32 raddr, rval; 5162 5163 5164 if (!soc_feature(unit, soc_feature_rcpu_1)) { 5165 return BCM_E_UNAVAIL; 5166 } 5167 5168 switch (type) { 5169 case bcmSwitchRemoteCpuVlan: 5170 reg = CMIC_PKT_VLANr; 5171 field = VLAN_IDf; 5172 break; 5173 case bcmSwitchRemoteCpuTpid: 5174 reg = CMIC_PKT_VLANr; 5175 field = TPIDf; 5176 break; 5177 case bcmSwitchRemoteCpuSignature: 5178 reg = CMIC_PKT_ETHER_SIGr; 5179 field = SIGNATUREf; 5180 break; 5181 case bcmSwitchRemoteCpuEthertype: 5182 reg = CMIC_PKT_ETHER_SIGr; 5183 field = ETHERTYPEf; 5184 break; 5185 default: 5186 return BCM_E_PARAM; 5187 } 5188 5189 raddr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 5190 /* coverity[result_independent_of_operands] */ 5191 BCM_IF_ERROR_RETURN( 5192 soc_pci_getreg(unit, raddr, &rval)); 5193 5194 *arg = soc_reg_field_get(unit, reg, rval, field); 5195 5196 return BCM_E_NONE; 5197 } 5198 5199 5200 /* 5201 * Function: 5202 * _bcm_gh2_rcpu_pipe_bypass_header_set 5203 * Description: 5204 * Prepare and program the SOBMH header for RCPU usage 5205 * Parameters: 5206 * unit - StrataSwitch PCI device unit number (driver internal). 5207 * port - port number. 5208 * type - The required switch control type to get MAC for 5209 * arg - port number to specify in the SOBMH 5210 * Returns: 5211 * BCM_E_xxxx 5212 */ 5213 STATIC int 5214 _bcm_gh2_rcpu_pipe_bypass_header_set(int unit, 5215 bcm_switch_control_t type, 5216 int arg) 5217 { 5218 uint32 pbh[3]; /* 3 words SOBMH header to program */ 5219 soc_pbsmh_hdr_t *p_pbh = (soc_pbsmh_hdr_t *)pbh; 5220 bcm_port_t port; 5221 bcm_module_t modid; 5222 uint32 raddr; 5223 int qnum; 5224 5225 if (BCM_GPORT_IS_SET(arg)) { 5226 bcm_trunk_t tgid; 5227 int id; 5228 5229 BCM_IF_ERROR_RETURN( 5230 _bcm_esw_gport_resolve(unit, arg, &modid, &port, &tgid, &id)); 5231 if ((BCM_TRUNK_INVALID != tgid) || (-1 != id) ) { 5232 return BCM_E_PORT; 5233 } 5234 } else { 5235 port = arg; 5236 modid = SOC_DEFAULT_DMA_SRCMOD_GET(unit); 5237 } 5238 5239 if (!SOC_PORT_VALID(unit, port)) { 5240 return BCM_E_PORT; 5241 } 5242 5243 /* Setup SOBMH header according to supplied argument */ 5244 if (SOC_DCB_TYPE(unit) == 23 || SOC_DCB_TYPE(unit) == 26 || 5245 SOC_DCB_TYPE(unit) == 29 || SOC_DCB_TYPE(unit) == 31 || 5246 SOC_DCB_TYPE(unit) == 30 || SOC_DCB_TYPE(unit) == 34 || 5247 SOC_DCB_TYPE(unit) == 37) { 5248 { 5249 qnum = SOC_INFO(unit).port_uc_cosq_base[port]; 5250 } 5251 PBS_MH_V7_W0_START_SET(pbh); 5252 PBS_MH_V7_W1_DPORT_QNUM_SET(pbh, port, qnum); 5253 PBS_MH_V7_W2_SMOD_COS_QNUM_SET(pbh, modid, 1, 0, qnum, 0); 5254 5255 } else if (SOC_DCB_TYPE(unit) == 32) { 5256 PBS_MH_V9_W0_START_SET(pbh); 5257 PBS_MH_V9_W1_DPORT_SET(pbh, port); 5258 PBS_MH_V9_W2_SMOD_COS_SET(pbh, modid, 1, 0); 5259 } else if (SOC_DCB_TYPE(unit) == 33 || SOC_DCB_TYPE(unit) == 35) { 5260 qnum = SOC_INFO(unit).port_uc_cosq_base[port]; 5261 soc_pbsmh_field_set(unit, p_pbh, PBSMH_start, SOC_PBSMH_START_INTERNAL); 5262 soc_pbsmh_field_set(unit, p_pbh, PBSMH_header_type, SOC_SOBMH_FROM_CPU); 5263 soc_pbsmh_field_set(unit, p_pbh, PBSMH_dst_port, port); 5264 soc_pbsmh_field_set(unit, p_pbh, PBSMH_unicast, 1 ); 5265 soc_pbsmh_field_set(unit, p_pbh, PBSMH_dst_port, port); 5266 soc_pbsmh_field_set(unit, p_pbh, PBSMH_src_mod, modid); 5267 soc_pbsmh_field_set(unit, p_pbh, PBSMH_cos, 0); 5268 soc_pbsmh_field_set(unit, p_pbh, PBSMH_queue_num, qnum); 5269 soc_pbsmh_field_set(unit, p_pbh, PBSMH_pri, 0); 5270 } else { 5271 PBS_MH_W0_START_SET(pbh); 5272 PBS_MH_W1_RSVD_SET(pbh); 5273 if ((SOC_DCB_TYPE(unit) == 11) || (SOC_DCB_TYPE(unit) == 12) || 5274 (SOC_DCB_TYPE(unit) == 15) || (SOC_DCB_TYPE(unit) == 17) || 5275 (SOC_DCB_TYPE(unit) == 18)) { 5276 PBS_MH_V2_W2_SMOD_DPORT_COS_SET(pbh, modid, port, 0, 0, 0); 5277 } else if ((SOC_DCB_TYPE(unit) == 14) || 5278 (SOC_DCB_TYPE(unit) == 19) || 5279 (SOC_DCB_TYPE(unit) == 20)) { 5280 5281 PBS_MH_V3_W2_SMOD_DPORT_COS_SET(pbh, modid, port,0, 0, 0); 5282 } else if (SOC_DCB_TYPE(unit) == 16) { 5283 PBS_MH_V4_W2_SMOD_DPORT_COS_SET(pbh, modid, port,0, 0, 0); 5284 } else if (SOC_DCB_TYPE(unit) == 21) { 5285 PBS_MH_V5_W1_SMOD_SET(pbh, modid, 1, 0, 0); 5286 PBS_MH_V5_W2_DPORT_COS_SET(pbh, port, 0, 0); 5287 } else if (SOC_DCB_TYPE(unit) == 24) { 5288 PBS_MH_V5_W1_SMOD_SET(pbh, modid, 1, 0, 0); 5289 PBS_MH_V6_W2_DPORT_COS_QNUM_SET(pbh, port, 0, 5290 (SOC_INFO(unit).port_cosq_base[port]), 0); 5291 } else { 5292 PBS_MH_V1_W2_SMOD_DPORT_COS_SET(pbh, modid, port, 0, 0, 0); 5293 } 5294 } 5295 5296 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 5297 /* coverity[result_independent_of_operands] */ 5298 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, pbh[0])); 5299 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 5300 /* coverity[result_independent_of_operands] */ 5301 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, pbh[1])); 5302 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 5303 /* coverity[result_independent_of_operands] */ 5304 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, pbh[2])); 5305 5306 return BCM_E_NONE; 5307 } 5308 5309 /* 5310 * Function: 5311 * _bcm_gh2_rcpu_pipe_bypass_header_get 5312 * Description: 5313 * Get the SOBMH header for RCPU usage and retrieve the port numebr 5314 * Parameters: 5315 * unit - StrataSwitch PCI device unit number (driver internal). 5316 * port - port number. 5317 * type - The required switch control type to get MAC for 5318 * arg - port number in the SOBMH header 5319 * Returns: 5320 * BCM_E_xxxx 5321 */ 5322 STATIC int 5323 _bcm_gh2_rcpu_pipe_bypass_header_get(int unit, 5324 bcm_switch_control_t type, 5325 int *arg) 5326 { 5327 soc_pbsmh_hdr_t *pbh; 5328 uint32 hw_buff[3]; /* 3 words SOBMH header */ 5329 uint32 raddr; 5330 int isGport; 5331 5332 if (NULL == arg) { 5333 return BCM_E_PARAM; 5334 } 5335 5336 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 5337 /* coverity[result_independent_of_operands] */ 5338 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hw_buff[0]))); 5339 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 5340 /* coverity[result_independent_of_operands] */ 5341 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hw_buff[1]))); 5342 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 5343 /* coverity[result_independent_of_operands] */ 5344 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hw_buff[2]))); 5345 5346 pbh = (soc_pbsmh_hdr_t *)hw_buff; 5347 5348 BCM_IF_ERROR_RETURN( 5349 bcm_esw_switch_control_get(unit, bcmSwitchUseGport, &isGport)); 5350 5351 if (isGport) { 5352 _bcm_gport_dest_t gport_st; 5353 5354 gport_st.gport_type = BCM_GPORT_TYPE_MODPORT; 5355 gport_st.modid = soc_pbsmh_field_get(unit, pbh, PBSMH_src_mod); 5356 gport_st.port = soc_pbsmh_field_get(unit, pbh, PBSMH_dst_port); 5357 BCM_IF_ERROR_RETURN( 5358 _bcm_esw_gport_construct(unit, &gport_st, arg)); 5359 } else { 5360 *arg = soc_pbsmh_field_get(unit, pbh, PBSMH_dst_port); 5361 } 5362 5363 return BCM_E_NONE; 5364 } 5365 5366 /* 5367 * Function: 5368 * _bcm_gh2_rcpu_higig_header_set 5369 * Description: 5370 * Prepare and program the HIGIG header for RCPU usage 5371 * Parameters: 5372 * unit - StrataSwitch PCI device unit number (driver internal). 5373 * arg - port number to specify in the SOBMH 5374 * Returns: 5375 * BCM_E_xxxx 5376 */ 5377 STATIC int 5378 _bcm_gh2_rcpu_higig_header_set(int unit, int arg) 5379 { 5380 #if defined(BCM_HIGIG2_SUPPORT) 5381 uint32 hghdr[4]; /* 4 words HIGIG2 header to program */ 5382 soc_higig2_hdr_t *xgh = (soc_higig2_hdr_t *)hghdr; 5383 bcm_port_t port; 5384 bcm_module_t modid; 5385 uint32 raddr, rval, vlan_val; 5386 5387 if (BCM_GPORT_IS_SET(arg)) { 5388 bcm_trunk_t tgid; 5389 int id; 5390 5391 BCM_IF_ERROR_RETURN( 5392 _bcm_esw_gport_resolve(unit, arg, &modid, &port, &tgid, &id)); 5393 if ((BCM_TRUNK_INVALID != tgid) || (-1 != id) ) { 5394 return BCM_E_PORT; 5395 } 5396 } else { 5397 port = arg; 5398 modid = SOC_DEFAULT_DMA_SRCMOD_GET(unit); 5399 } 5400 5401 if (!SOC_PORT_VALID(unit, port)) { 5402 return BCM_E_PORT; 5403 } 5404 5405 sal_memset(hghdr, 0, sizeof(soc_higig2_hdr_t)); 5406 soc_higig2_field_set(unit, xgh, HG_start, SOC_HIGIG2_START); 5407 soc_higig2_field_set(unit, xgh, HG_ppd_type, 0); 5408 soc_higig2_field_set(unit, xgh, HG_dst_mod, modid); 5409 soc_higig2_field_set(unit, xgh, HG_dst_port, port); 5410 5411 raddr = soc_reg_addr(unit, CMIC_PKT_VLANr, REG_PORT_ANY, 0); 5412 /* coverity[result_independent_of_operands] */ 5413 BCM_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 5414 vlan_val = soc_reg_field_get(unit, CMIC_PKT_VLANr, rval, VLAN_IDf); 5415 if (0 == vlan_val) { 5416 vlan_val = DEFAULT_RCPU_VLAN; 5417 } 5418 soc_higig2_field_set(unit, xgh, HG_vlan_tag, vlan_val); 5419 soc_higig2_field_set(unit, xgh, HG_opcode, SOC_HIGIG_OP_CPU); 5420 5421 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 5422 /* coverity[result_independent_of_operands] */ 5423 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[0])); 5424 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 5425 /* coverity[result_independent_of_operands] */ 5426 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[1])); 5427 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 5428 /* coverity[result_independent_of_operands] */ 5429 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[2])); 5430 raddr = soc_reg_addr(unit, CMIC_PKT_RMH3r, REG_PORT_ANY, 0); 5431 /* coverity[result_independent_of_operands] */ 5432 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, hghdr[3])); 5433 5434 return BCM_E_NONE; 5435 #else 5436 return BCM_E_UNAVAIL; 5437 #endif /* BCM_HIGIG2_SUPPORT */ 5438 } 5439 5440 /* 5441 * Function: 5442 * _bcm_gh2_rcpu_higig_header_get 5443 * Description: 5444 * Get the SOBMH header for RCPU usage and retrieve the port numebr 5445 * Parameters: 5446 * unit - StrataSwitch PCI device unit number (driver internal). 5447 * type - The required switch control type to get MAC for 5448 * arg - port number in the SOBMH header 5449 * Returns: 5450 * BCM_E_xxxx 5451 */ 5452 STATIC int 5453 _bcm_gh2_rcpu_higig_header_get(int unit, int *arg) 5454 { 5455 #if defined(BCM_HIGIG2_SUPPORT) 5456 uint32 hghdr[4]; /* 4 words HIGIG2 header to program */ 5457 soc_higig2_hdr_t *xgh = (soc_higig2_hdr_t *)hghdr; 5458 uint32 raddr; 5459 int isGport; 5460 5461 if (NULL == arg) { 5462 return BCM_E_PARAM; 5463 } 5464 5465 raddr = soc_reg_addr(unit, CMIC_PKT_RMH0r, REG_PORT_ANY, 0); 5466 /* coverity[result_independent_of_operands] */ 5467 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[0]))); 5468 raddr = soc_reg_addr(unit, CMIC_PKT_RMH1r, REG_PORT_ANY, 0); 5469 /* coverity[result_independent_of_operands] */ 5470 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[1]))); 5471 raddr = soc_reg_addr(unit, CMIC_PKT_RMH2r, REG_PORT_ANY, 0); 5472 /* coverity[result_independent_of_operands] */ 5473 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[2]))); 5474 raddr = soc_reg_addr(unit, CMIC_PKT_RMH3r, REG_PORT_ANY, 0); 5475 /* coverity[result_independent_of_operands] */ 5476 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &(hghdr[3]))); 5477 5478 BCM_IF_ERROR_RETURN( 5479 bcm_esw_switch_control_get(unit, bcmSwitchUseGport, &isGport)); 5480 5481 if (isGport) { 5482 _bcm_gport_dest_t gport_st; 5483 5484 gport_st.gport_type = BCM_GPORT_TYPE_MODPORT; 5485 gport_st.modid = soc_higig2_field_get(unit, xgh, HG_dst_mod); 5486 gport_st.port = soc_higig2_field_get(unit, xgh, HG_dst_port); 5487 BCM_IF_ERROR_RETURN( 5488 _bcm_esw_gport_construct(unit, &gport_st, arg)); 5489 } else { 5490 *arg = soc_higig2_field_get(unit, xgh, HG_dst_port); 5491 } 5492 5493 return BCM_E_NONE; 5494 #else 5495 return BCM_E_UNAVAIL; 5496 #endif 5497 } 5498 #endif 5499 5500 5501 STATIC int 5502 _bcm_gh2_switch_sync_port_select_set(int unit, uint32 val) 5503 { 5504 uint32 rval; 5505 BCM_IF_ERROR_RETURN( 5506 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 5507 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 5508 L1_RCVD_PRI_CLK_PORT_SELf, val); 5509 BCM_IF_ERROR_RETURN( 5510 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 5511 5512 return BCM_E_NONE; 5513 } 5514 5515 5516 STATIC int 5517 _bcm_gh2_switch_sync_port_select_get(int unit, uint8 type, uint32 *val) 5518 { 5519 uint32 rval; 5520 BCM_IF_ERROR_RETURN( 5521 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 5522 if (type) { 5523 /* primary (1) */ 5524 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 5525 L1_RCVD_PRI_CLK_PORT_SELf); 5526 } else { 5527 /* backup (0) */ 5528 *val = soc_reg_field_get(unit, TOP_MISC_CONTROL_2r, rval, 5529 L1_RCVD_BKUP_CLK_PORT_SELf); 5530 } 5531 5532 return BCM_E_NONE; 5533 } 5534 5535 5536 STATIC int 5537 _bcm_gh2_switch_sync_port_backup_select_set(int unit, uint32 val) 5538 { 5539 uint32 rval; 5540 BCM_IF_ERROR_RETURN( 5541 READ_TOP_MISC_CONTROL_2r(unit, &rval)); 5542 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 5543 L1_RCVD_BKUP_CLK_PORT_SELf, val); 5544 BCM_IF_ERROR_RETURN( 5545 WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 5546 return BCM_E_NONE; 5547 } 5548 5549 STATIC int 5550 _bcm_gh2_switch_div_ctrl_select_set(int unit, uint32 val) 5551 { 5552 uint32 rval; 5553 BCM_IF_ERROR_RETURN( 5554 READ_TOP_L1_RCVD_CLK_CONTROLr(unit, &rval)); 5555 if (val == 1) { 5556 soc_reg_field_set(unit, TOP_L1_RCVD_CLK_CONTROLr, &rval, 5557 L1_RCVD_FREQ_SELf, 1); 5558 } else { 5559 soc_reg_field_set(unit, TOP_L1_RCVD_CLK_CONTROLr, &rval, 5560 L1_RCVD_FREQ_SELf, 0); 5561 } 5562 BCM_IF_ERROR_RETURN( 5563 WRITE_TOP_L1_RCVD_CLK_CONTROLr(unit, rval)); 5564 return BCM_E_NONE; 5565 } 5566 5567 STATIC int 5568 _bcm_gh2_switch_div_ctrl_select_get(int unit, uint8 type, uint32 *val) 5569 { 5570 uint32 rval; 5571 BCM_IF_ERROR_RETURN( 5572 READ_TOP_L1_RCVD_CLK_CONTROLr(unit, &rval)); 5573 if (type) { 5574 /* primary (1) */ 5575 *val = soc_reg_field_get(unit, TOP_L1_RCVD_CLK_CONTROLr, rval, 5576 L1_RCVD_FREQ_SELf); 5577 } else { 5578 /* backup (0) */ 5579 *val = soc_reg_field_get(unit, TOP_L1_RCVD_CLK_CONTROLr, rval, 5580 L1_RCVD_BKUP_FREQ_SELf); 5581 } 5582 return BCM_E_NONE; 5583 } 5584 5585 STATIC int 5586 _bcm_gh2_switch_div_ctrl_backup_select_set(int unit, uint32 val) 5587 { 5588 5589 uint32 rval; 5590 BCM_IF_ERROR_RETURN( 5591 READ_TOP_L1_RCVD_CLK_CONTROLr(unit, &rval)); 5592 if (val == 1) { 5593 soc_reg_field_set(unit, TOP_L1_RCVD_CLK_CONTROLr, &rval, 5594 L1_RCVD_BKUP_FREQ_SELf, 1); 5595 } else { 5596 soc_reg_field_set(unit, TOP_L1_RCVD_CLK_CONTROLr, &rval, 5597 L1_RCVD_BKUP_FREQ_SELf, 0); 5598 } 5599 BCM_IF_ERROR_RETURN( 5600 WRITE_TOP_L1_RCVD_CLK_CONTROLr(unit, rval)); 5601 return BCM_E_NONE; 5602 } 5603 5604 5605 /* 5606 * Function: 5607 * bcm_gh2_switch_control_port_set 5608 * Description: 5609 * Specify general switch behaviors on a per-port basis. 5610 * Parameters: 5611 * unit - Device unit number 5612 * port - Port to affect 5613 * type - The desired configuration parameter to modify 5614 * arg - The value with which to set the parameter 5615 * Returns: 5616 * BCM_E_xxx 5617 */ 5618 int 5619 bcm_gh2_switch_control_port_set(int unit, 5620 bcm_port_t port, 5621 bcm_switch_control_t type, 5622 int arg) 5623 { 5624 if ((type == bcmSwitchFailoverStackTrunk) || 5625 (type == bcmSwitchFailoverEtherTrunk)) { 5626 return BCM_E_UNAVAIL; 5627 } 5628 5629 if (BCM_GPORT_IS_SET(port)) { 5630 BCM_IF_ERROR_RETURN 5631 (bcm_gh2_switch_control_port_validate(unit, port, type, &port)); 5632 } 5633 5634 #ifdef BCM_XGS3_SWITCH_SUPPORT 5635 if (SOC_IS_XGS3_SWITCH(unit)) { 5636 int found; 5637 5638 switch(type) { 5639 case bcmSwitchPktAge: 5640 return _bcm_gh2_pkt_age_set(unit, arg); 5641 break; 5642 case bcmSwitchHashL2: 5643 case bcmSwitchHashL3: 5644 case bcmSwitchHashMultipath: 5645 case bcmSwitchHashIpfixIngress: 5646 case bcmSwitchHashIpfixEgress: 5647 case bcmSwitchHashIpfixIngressDual: 5648 case bcmSwitchHashIpfixEgressDual: 5649 case bcmSwitchHashVlanTranslate: 5650 case bcmSwitchHashMPLS: 5651 case bcmSwitchHashWlanPort: 5652 case bcmSwitchHashWlanPortDual: 5653 case bcmSwitchHashWlanClient: 5654 case bcmSwitchHashWlanClientDual: 5655 case bcmSwitchHashRegexAction: 5656 case bcmSwitchHashRegexActionDual: 5657 case bcmSwitchHashL3DNATPool: 5658 case bcmSwitchHashL3DNATPoolDual: 5659 case bcmSwitchHashVpVlanMemberIngress: 5660 case bcmSwitchHashVpVlanMemberIngressDual: 5661 case bcmSwitchHashVpVlanMemberEgress: 5662 case bcmSwitchHashVpVlanMemberEgressDual: 5663 case bcmSwitchHashL2Endpoint: 5664 case bcmSwitchHashL2EndpointDual: 5665 case bcmSwitchHashEndpointQueueMap: 5666 case bcmSwitchHashEndpointQueueMapDual: 5667 return _bcm_gh2_er_hashselect_set(unit, type, arg); 5668 break; 5669 case bcmSwitchHashControl: 5670 return _bcm_gh2_hashcontrol_set(unit, arg); 5671 break; 5672 case bcmSwitchFieldMultipathHashSelect: 5673 return _bcm_field_tr_multipath_hashcontrol_set(unit, arg); 5674 break; 5675 case bcmSwitchL3IngressMode: 5676 #ifdef INCLUDE_L3 5677 if ((soc_feature(unit, soc_feature_l3)) && (soc_feature(unit,soc_feature_l3_ingress_interface))) { 5678 return bcm_xgs3_l3_ingress_mode_set(unit, arg); 5679 } 5680 #endif /* INCLUDE_L3 */ 5681 return BCM_E_UNAVAIL; 5682 break; 5683 case bcmSwitchL3IngressInterfaceMapSet: 5684 #ifdef INCLUDE_L3 5685 if ((soc_feature(unit, soc_feature_l3)) && (soc_feature(unit,soc_feature_l3_ingress_interface))) { 5686 return bcm_xgs3_l3_ingress_intf_map_set(unit, arg); 5687 } 5688 #endif /* INCLUDE_L3 */ 5689 return BCM_E_UNAVAIL; 5690 break; 5691 5692 case bcmSwitchColorSelect: 5693 return _bcm_gh2_er_color_mode_set(unit, port, arg); 5694 break; 5695 case bcmSwitchModuleLoopback: 5696 return _bcm_gh2_mod_lb_set(unit, port, arg); 5697 break; 5698 case bcmSwitchIngressRateLimitIncludeIFG: 5699 return _bcm_gh2_ing_rate_limit_ifg_set(unit, port, arg); 5700 break; 5701 case bcmSwitchVrfMax: 5702 if (soc_feature(unit, soc_feature_l3)) { 5703 return soc_max_vrf_set(unit, arg); 5704 } else { 5705 return BCM_E_UNAVAIL; 5706 } 5707 break; 5708 5709 case bcmSwitchL3UrpfRouteEnable: 5710 if (soc_feature(unit, soc_feature_urpf)) { 5711 /* 5712 * Saber - 56246 has only 2 L3_DEFIP tcams 5713 * Both IPV6 and RPF cannot be supported 5714 * on this device. 5715 */ 5716 if (soc_feature(unit, soc_feature_l3_max_2_defip_tcams)) { 5717 if (soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 0)) { 5718 LOG_ERROR(BSL_LS_BCM_COMMON, 5719 (BSL_META_U(unit, 5720 "Cannot enable IPV6 and URPF " 5721 "only 2 L3_DEFIP tcams present\n"))); 5722 return BCM_E_CONFIG; 5723 } 5724 } 5725 return _bcm_gh2_urpf_route_enable(unit, arg); 5726 } 5727 return BCM_E_UNAVAIL; 5728 break; 5729 5730 case bcmSwitchL3UrpfMode: 5731 if (soc_feature(unit, soc_feature_urpf)) { 5732 return _bcm_gh2_urpf_port_mode_set(unit, port, arg); 5733 } 5734 return BCM_E_UNAVAIL; 5735 break; 5736 case bcmSwitchL3UrpfDefaultRoute: 5737 if (soc_feature(unit, soc_feature_urpf)) { 5738 return _bcm_gh2_urpf_def_gw_enable(unit, port, arg); 5739 } 5740 return BCM_E_UNAVAIL; 5741 break; 5742 case bcmSwitchHashL2Dual: 5743 case bcmSwitchHashL3Dual: 5744 case bcmSwitchHashVlanTranslateDual: 5745 case bcmSwitchHashEgressVlanTranslate: 5746 case bcmSwitchHashEgressVlanTranslateDual: 5747 case bcmSwitchHashMPLSDual: 5748 if (soc_feature(unit, soc_feature_dual_hash)) { 5749 return _bcm_gh2_er_hashselect_set(unit, type, arg); 5750 } 5751 return BCM_E_UNAVAIL; 5752 break; 5753 case bcmSwitchHashSelectControl: 5754 return bcm_gh2_switch_rtag7_selectcontrol_set(unit, arg); 5755 break; 5756 case bcmSwitchHashIP4Field0: 5757 case bcmSwitchHashIP4Field1: 5758 case bcmSwitchHashIP6Field0: 5759 case bcmSwitchHashIP6Field1: 5760 case bcmSwitchHashL2Field0: 5761 case bcmSwitchHashL2Field1: 5762 case bcmSwitchHashHG2UnknownField0: 5763 case bcmSwitchHashHG2UnknownField1: 5764 return bcm_gh2_switch_rtag7_fieldselect_set(unit, type, arg); 5765 break; 5766 case bcmSwitchHashMPLSField0: 5767 case bcmSwitchHashMPLSField1: 5768 case bcmSwitchHashL2MPLSField0: 5769 case bcmSwitchHashL2MPLSField1: 5770 case bcmSwitchHashL3MPLSField0: 5771 case bcmSwitchHashL3MPLSField1: 5772 case bcmSwitchHashMPLSTunnelField0: 5773 case bcmSwitchHashMPLSTunnelField1: 5774 case bcmSwitchHashMIMTunnelField0: 5775 case bcmSwitchHashMIMTunnelField1: 5776 case bcmSwitchHashMIMField0: 5777 case bcmSwitchHashMIMField1: 5778 case bcmSwitchHashL3MiMField0: 5779 case bcmSwitchHashL3MiMField1: 5780 case bcmSwitchHashL3L2MPLSField0: 5781 case bcmSwitchHashL3L2MPLSField1: 5782 return BCM_E_UNAVAIL; 5783 break; 5784 case bcmSwitchHashL2VxlanField0: 5785 case bcmSwitchHashL2VxlanField1: 5786 case bcmSwitchHashL3VxlanField0: 5787 case bcmSwitchHashL3VxlanField1: 5788 return bcm_gh2_switch_rtag7_fieldselect_set(unit, type, arg); 5789 break; 5790 case bcmSwitchHashL2L2GreField0: 5791 case bcmSwitchHashL2L2GreField1: 5792 case bcmSwitchHashL3L2GreField0: 5793 case bcmSwitchHashL3L2GreField1: 5794 case bcmSwitchHashFCOEField0: 5795 case bcmSwitchHashFCOEField1: 5796 case bcmSwitchHashL2TrillField0: 5797 case bcmSwitchHashL2TrillField1: 5798 case bcmSwitchHashL3TrillField0: 5799 case bcmSwitchHashL3TrillField1: 5800 case bcmSwitchHashTrillTunnelField0: 5801 case bcmSwitchHashTrillTunnelField1: 5802 return BCM_E_UNAVAIL; 5803 break; 5804 case bcmSwitchHashIP4TcpUdpField0: 5805 case bcmSwitchHashIP4TcpUdpField1: 5806 case bcmSwitchHashIP4TcpUdpPortsEqualField0: 5807 case bcmSwitchHashIP4TcpUdpPortsEqualField1: 5808 case bcmSwitchHashIP6TcpUdpField0: 5809 case bcmSwitchHashIP6TcpUdpField1: 5810 case bcmSwitchHashIP6TcpUdpPortsEqualField0: 5811 case bcmSwitchHashIP6TcpUdpPortsEqualField1: 5812 return bcm_gh2_switch_rtag7_fieldselect_set(unit, type, arg); 5813 case bcmSwitchHashField0PreProcessEnable: 5814 return (soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_3r, 5815 REG_PORT_ANY, HASH_PRE_PROCESSING_ENABLE_Af, arg)); 5816 case bcmSwitchHashField1PreProcessEnable: 5817 return (soc_reg_field32_modify(unit, RTAG7_HASH_CONTROL_3r, 5818 REG_PORT_ANY, HASH_PRE_PROCESSING_ENABLE_Bf, arg)); 5819 case bcmSwitchHashField0Config: 5820 case bcmSwitchHashField0Config1: 5821 case bcmSwitchHashField1Config: 5822 case bcmSwitchHashField1Config1: 5823 case bcmSwitchMacroFlowHashFieldConfig: 5824 return bcm_gh2_switch_rtag7_fieldconfig_set(unit, type, arg); 5825 break; 5826 case bcmSwitchTrunkHashSet1UnicastOffset: 5827 case bcmSwitchTrunkHashSet1NonUnicastOffset: 5828 case bcmSwitchFabricTrunkHashSet1UnicastOffset: 5829 case bcmSwitchFabricTrunkHashSet1NonUnicastOffset: 5830 case bcmSwitchLoadBalanceHashSet1UnicastOffset: 5831 case bcmSwitchLoadBalanceHashSet1NonUnicastOffset: 5832 case bcmSwitchECMPHashSet1Offset: 5833 return BCM_E_UNAVAIL; 5834 break; 5835 case bcmSwitchTrunkHashSet0UnicastOffset: 5836 case bcmSwitchTrunkHashSet0NonUnicastOffset: 5837 case bcmSwitchECMPHashSet0Offset: 5838 case bcmSwitchECMPVxlanHashOffset: 5839 case bcmSwitchEntropyHashSet0Offset: 5840 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 5841 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 5842 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 5843 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 5844 case bcmSwitchFabricTrunkFailoverHashOffset: 5845 return bcm_gh2_switch_rtag7_fieldoffset_set(unit, port, type, 5846 arg); 5847 break; 5848 case bcmSwitchEcmpRoce2HashOffset: 5849 if (soc_feature(unit, soc_feature_rroce)) { 5850 return bcm_gh2_switch_rtag7_fieldoffset_set(unit, port, 5851 type, arg); 5852 } else { 5853 return BCM_E_UNAVAIL; 5854 } 5855 break; 5856 case bcmSwitchTrunkFailoverHashOffset: 5857 case bcmSwitchFabricTrunkDynamicHashOffset: 5858 case bcmSwitchTrunkDynamicHashOffset: 5859 case bcmSwitchEcmpDynamicHashOffset: 5860 case bcmSwitchFabricTrunkResilientHashOffset: 5861 case bcmSwitchTrunkResilientHashOffset: 5862 case bcmSwitchEcmpResilientHashOffset: 5863 case bcmSwitchECMPUnderlayHashSet0Offset: 5864 case bcmSwitchECMPUnderlayVxlanHashOffset: 5865 case bcmSwitchECMPL2GreHashOffset: 5866 case bcmSwitchECMPUnderlayL2GreHashOffset: 5867 case bcmSwitchECMPTrillHashOffset: 5868 case bcmSwitchECMPUnderlayTrillHashOffset: 5869 case bcmSwitchECMPMplsHashOffset: 5870 case bcmSwitchVirtualPortDynamicHashOffset: 5871 case bcmSwitchECMPOverlayHashOffset: 5872 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 5873 return BCM_E_UNAVAIL; 5874 break; 5875 case bcmSwitchArpReplyToCpu: 5876 case bcmSwitchArpReplyDrop: 5877 case bcmSwitchArpRequestToCpu: 5878 case bcmSwitchArpRequestDrop: 5879 case bcmSwitchNdPktToCpu: 5880 case bcmSwitchNdPktDrop: 5881 case bcmSwitchDhcpPktToCpu: 5882 case bcmSwitchDhcpPktDrop: 5883 if (SOC_REG_INFO(unit, PROTOCOL_PKT_CONTROLr).regtype != 5884 soc_portreg) { 5885 return _bcm_gh2_prot_pkt_action_set(unit, port, type, arg); 5886 } 5887 break; 5888 case bcmSwitchIgmpPktToCpu: 5889 case bcmSwitchIgmpPktDrop: 5890 case bcmSwitchMldPktToCpu: 5891 case bcmSwitchMldPktDrop: 5892 case bcmSwitchV4ResvdMcPktToCpu: 5893 case bcmSwitchV4ResvdMcPktFlood: 5894 case bcmSwitchV4ResvdMcPktDrop: 5895 case bcmSwitchV6ResvdMcPktToCpu: 5896 case bcmSwitchV6ResvdMcPktFlood: 5897 case bcmSwitchV6ResvdMcPktDrop: 5898 case bcmSwitchIgmpReportLeaveDrop: 5899 case bcmSwitchIgmpReportLeaveFlood: 5900 case bcmSwitchIgmpReportLeaveToCpu: 5901 case bcmSwitchIgmpQueryDrop: 5902 case bcmSwitchIgmpQueryFlood: 5903 case bcmSwitchIgmpQueryToCpu: 5904 case bcmSwitchIgmpUnknownDrop: 5905 case bcmSwitchIgmpUnknownFlood: 5906 case bcmSwitchIgmpUnknownToCpu: 5907 case bcmSwitchMldReportDoneDrop: 5908 case bcmSwitchMldReportDoneFlood: 5909 case bcmSwitchMldReportDoneToCpu: 5910 case bcmSwitchMldQueryDrop: 5911 case bcmSwitchMldQueryFlood: 5912 case bcmSwitchMldQueryToCpu: 5913 case bcmSwitchIpmcV4RouterDiscoveryDrop: 5914 case bcmSwitchIpmcV4RouterDiscoveryFlood: 5915 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 5916 case bcmSwitchIpmcV6RouterDiscoveryDrop: 5917 case bcmSwitchIpmcV6RouterDiscoveryFlood: 5918 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 5919 return _bcm_gh2_igmp_action_set(unit, port, type, arg); 5920 break; 5921 case bcmSwitchDirectedMirroring: 5922 if (!soc_feature(unit, soc_feature_xgs1_mirror)) { 5923 /* Directed mirroring cannot be turned off */ 5924 return (arg == 0) ? BCM_E_PARAM : BCM_E_NONE; 5925 } 5926 break; 5927 case bcmSwitchFlexibleMirrorDestinations: 5928 case bcmSwitchMirrorExclusive: 5929 return BCM_E_UNAVAIL; 5930 break; 5931 case bcmSwitchL3EgressMode: 5932 #ifdef INCLUDE_L3 5933 if (soc_feature(unit, soc_feature_l3)) { 5934 return bcm_xgs3_l3_egress_mode_set(unit, arg); 5935 } 5936 #endif /* INCLUDE_L3 */ 5937 return BCM_E_UNAVAIL; 5938 break; 5939 case bcmSwitchL3HostAsRouteReturnValue: 5940 #ifdef INCLUDE_L3 5941 if (soc_feature(unit, soc_feature_l3)) { 5942 return bcm_xgs3_l3_host_as_route_return_set(unit, arg); 5943 } 5944 #endif /* INCLUDE_L3 */ 5945 return BCM_E_UNAVAIL; 5946 break; 5947 case bcmSwitchL3DefipMultipathCountUpdate: 5948 #ifdef INCLUDE_L3 5949 if(soc_feature(unit, soc_feature_l3_defip_ecmp_count)) { 5950 return _bcm_xgs3_l3_multipathCountUpdate(unit, arg); 5951 } 5952 #endif /* INCLUDE_L3 */ 5953 return BCM_E_UNAVAIL; 5954 break; 5955 case bcmSwitchIpmcReplicationSharing: 5956 #ifdef INCLUDE_L3 5957 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 5958 SOC_IPMCREPLSHR_SET(unit, arg); 5959 #ifdef BCM_WARM_BOOT_SUPPORT 5960 { 5961 int rv; 5962 /* Record this value in HW for Warm Boot recovery. */ 5963 rv = _bcm_esw_ipmc_repl_wb_flags_set( 5964 unit, (arg ? _BCM_IPMC_WB_REPL_LIST : 0), 5965 _BCM_IPMC_WB_REPL_LIST); 5966 if (BCM_FAILURE(rv) && (BCM_E_UNAVAIL != rv)) { 5967 return rv; 5968 } 5969 } 5970 #endif /* BCM_WARM_BOOT_SUPPORT */ 5971 return BCM_E_NONE; 5972 } 5973 #endif /* INCLUDE_L3 */ 5974 return BCM_E_UNAVAIL; 5975 break; 5976 case bcmSwitchIpmcReplicationAvailabilityThreshold: 5977 #ifdef INCLUDE_L3 5978 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 5979 return _bcm_esw_ipmc_repl_threshold_set(unit, arg); 5980 } 5981 #endif /* INCLUDE_L3 */ 5982 return BCM_E_UNAVAIL; 5983 break; 5984 case bcmSwitchHashDualMoveDepth: 5985 if (soc_feature(unit, soc_feature_dual_hash)) { 5986 if (arg >= 0) { 5987 SOC_DUAL_HASH_MOVE_MAX(unit) = arg; 5988 return BCM_E_NONE; 5989 } else { 5990 return BCM_E_PARAM; 5991 } 5992 } 5993 return BCM_E_UNAVAIL; 5994 break; 5995 case bcmSwitchHashDualMoveDepthL2: 5996 if (soc_feature(unit, soc_feature_dual_hash)) { 5997 if (arg >= 0) { 5998 SOC_DUAL_HASH_MOVE_MAX_L2X(unit) = arg; 5999 return BCM_E_NONE; 6000 } else { 6001 return BCM_E_PARAM; 6002 } 6003 } 6004 return BCM_E_UNAVAIL; 6005 break; 6006 case bcmSwitchHashDualMoveDepthMpls: 6007 if (soc_feature(unit, soc_feature_dual_hash)) { 6008 if (arg >= 0) { 6009 SOC_DUAL_HASH_MOVE_MAX_MPLS(unit) = arg; 6010 return BCM_E_NONE; 6011 } else { 6012 return BCM_E_PARAM; 6013 } 6014 } 6015 return BCM_E_UNAVAIL; 6016 break; 6017 case bcmSwitchHashDualMoveDepthVlan: 6018 if (soc_feature(unit, soc_feature_dual_hash)) { 6019 if (arg >= 0) { 6020 SOC_DUAL_HASH_MOVE_MAX_VLAN(unit) = arg; 6021 return BCM_E_NONE; 6022 } else { 6023 return BCM_E_PARAM; 6024 } 6025 } 6026 return BCM_E_UNAVAIL; 6027 break; 6028 case bcmSwitchHashDualMoveDepthEgressVlan: 6029 if (soc_feature(unit, soc_feature_dual_hash)) { 6030 if (arg >= 0) { 6031 SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit) = arg; 6032 return BCM_E_NONE; 6033 } else { 6034 return BCM_E_PARAM; 6035 } 6036 } 6037 return BCM_E_UNAVAIL; 6038 break; 6039 #if defined(INCLUDE_L3) 6040 case bcmSwitchHashDualMoveDepthL3: 6041 if (soc_feature(unit, soc_feature_dual_hash)) { 6042 if (arg >= 0) { 6043 SOC_DUAL_HASH_MOVE_MAX_L3X(unit) = arg; 6044 return BCM_E_NONE; 6045 } else { 6046 return BCM_E_PARAM; 6047 } 6048 } 6049 return BCM_E_UNAVAIL; 6050 break; 6051 #endif 6052 case bcmSwitchHashDualMoveDepthWlanPort: 6053 case bcmSwitchHashDualMoveDepthWlanClient: 6054 return BCM_E_UNAVAIL; 6055 break; 6056 case bcmSwitchL2PortBlocking: 6057 if (soc_feature(unit, soc_feature_src_mac_group)) { 6058 SOC_L2X_GROUP_ENABLE_SET(unit, _bool_invert(unit, arg, 0)); 6059 return BCM_E_NONE; 6060 } 6061 return BCM_E_UNAVAIL; 6062 break; 6063 case bcmSwitchTimeSyncPktDrop: 6064 case bcmSwitchTimeSyncPktFlood: 6065 case bcmSwitchTimeSyncPktToCpu: 6066 case bcmSwitchMmrpPktDrop: 6067 case bcmSwitchMmrpPktFlood: 6068 case bcmSwitchMmrpPktToCpu: 6069 case bcmSwitchSrpPktDrop: 6070 case bcmSwitchSrpPktFlood: 6071 case bcmSwitchSrpPktToCpu: 6072 case bcmSwitchSRPEthertype: 6073 case bcmSwitchMMRPEthertype: 6074 case bcmSwitchTimeSyncEthertype: 6075 case bcmSwitchSRPDestMacOui: 6076 case bcmSwitchMMRPDestMacOui: 6077 case bcmSwitchTimeSyncDestMacOui: 6078 case bcmSwitchSRPDestMacNonOui: 6079 case bcmSwitchMMRPDestMacNonOui: 6080 case bcmSwitchTimeSyncDestMacNonOui: 6081 case bcmSwitchTimeSyncMessageTypeBitmap: 6082 case bcmSwitchTimeSyncClassAPktPrio: 6083 case bcmSwitchTimeSyncClassBPktPrio: 6084 case bcmSwitchTimeSyncClassAExeptionPktPrio: 6085 case bcmSwitchTimeSyncClassBExeptionPktPrio: 6086 case bcmSwitchStgInvalidToCpu: 6087 case bcmSwitchVlanTranslateEgressMissToCpu: 6088 case bcmSwitchL3PktErrToCpu: 6089 case bcmSwitchMtuFailureToCpu: 6090 case bcmSwitchSrcKnockoutToCpu: 6091 case bcmSwitchWlanTunnelMismatchToCpu: 6092 case bcmSwitchWlanTunnelMismatchDrop: 6093 case bcmSwitchWlanPortMissToCpu: 6094 case bcmSwitchUnknownVlanToCpuCosq: 6095 case bcmSwitchStgInvalidToCpuCosq: 6096 case bcmSwitchVlanTranslateEgressMissToCpuCosq: 6097 case bcmSwitchTunnelErrToCpuCosq: 6098 case bcmSwitchL3HeaderErrToCpuCosq: 6099 case bcmSwitchL3PktErrToCpuCosq: 6100 case bcmSwitchIpmcTtlErrToCpuCosq: 6101 case bcmSwitchMtuFailureToCpuCosq: 6102 case bcmSwitchHgHdrErrToCpuCosq: 6103 case bcmSwitchSrcKnockoutToCpuCosq: 6104 case bcmSwitchWlanTunnelMismatchToCpuCosq: 6105 case bcmSwitchWlanPortMissToCpuCosq: 6106 return BCM_E_UNAVAIL; 6107 break; 6108 case bcmSwitchLayeredQoSResolution: 6109 return _bcm_gh2_layered_qos_resolution_set(unit, port, type, arg); 6110 break; 6111 case bcmSwitchEncapErrorToCpu: 6112 case bcmSwitchMirrorEgressTrueColorSelect: 6113 case bcmSwitchMirrorEgressTruePriority: 6114 case bcmSwitchL3UrpfRouteEnableExternal: 6115 return BCM_E_UNAVAIL; 6116 break; 6117 case bcmSwitchLinkDownInfoSkip: 6118 return _bcm_esw_link_port_info_skip_set(unit, port, arg); 6119 break; 6120 case bcmSwitchDropSobmhOnLinkDown: 6121 case bcmSwitchCongestionNotificationIdLow: 6122 return BCM_E_UNAVAIL; 6123 break; 6124 case bcmSwitchMeterAdjust: 6125 if (soc_feature(unit, soc_feature_meter_adjust)) { 6126 return _bcm_gh2_meter_adjust_set(unit, port, arg); 6127 } 6128 break; 6129 case bcmSwitchShaperAdjust: 6130 if (soc_feature(unit, soc_feature_meter_adjust)) { 6131 BCM_IF_ERROR_RETURN( 6132 _bcm_gh2_shaper_adjust_set(unit, port, arg)); 6133 } 6134 break; 6135 case bcmSwitchPFCClass0Queue: 6136 case bcmSwitchPFCClass1Queue: 6137 case bcmSwitchPFCClass2Queue: 6138 case bcmSwitchPFCClass3Queue: 6139 case bcmSwitchPFCClass4Queue: 6140 case bcmSwitchPFCClass5Queue: 6141 case bcmSwitchPFCClass6Queue: 6142 case bcmSwitchPFCClass7Queue: 6143 if (arg < 0) { 6144 return bcmi_gh2_cosq_port_pfc_op(unit, port, type, 6145 _BCM_COSQ_OP_CLEAR, arg); 6146 } else { 6147 return bcmi_gh2_cosq_port_pfc_op(unit, port, type, 6148 _BCM_COSQ_OP_ADD, arg); 6149 } 6150 break; 6151 case bcmSwitchPFCClass0McastQueue: 6152 case bcmSwitchPFCClass1McastQueue: 6153 case bcmSwitchPFCClass2McastQueue: 6154 case bcmSwitchPFCClass3McastQueue: 6155 case bcmSwitchPFCClass4McastQueue: 6156 case bcmSwitchPFCClass5McastQueue: 6157 case bcmSwitchPFCClass6McastQueue: 6158 case bcmSwitchPFCClass7McastQueue: 6159 case bcmSwitchPFCClass0DestmodQueue: 6160 case bcmSwitchPFCClass1DestmodQueue: 6161 case bcmSwitchPFCClass2DestmodQueue: 6162 case bcmSwitchPFCClass3DestmodQueue: 6163 case bcmSwitchPFCClass4DestmodQueue: 6164 case bcmSwitchPFCClass5DestmodQueue: 6165 case bcmSwitchPFCClass6DestmodQueue: 6166 case bcmSwitchPFCClass7DestmodQueue: 6167 case bcmSwitchEntropyHashSet1Offset: 6168 case bcmSwitchMiMDefaultSVP: 6169 case bcmSwitchAlternateStoreForward: 6170 case bcmSwitchMcQueueSchedMode: 6171 return BCM_E_UNAVAIL; 6172 break; 6173 case bcmSwitchTimesyncEgressTimestampingMode: 6174 return _bcm_esw_port_timesync_timestamping_mode_set(unit, port, 6175 (bcm_switch_timesync_timestamping_mode_t)arg); 6176 break; 6177 case bcmSwitchHashRoce1Field0: 6178 case bcmSwitchHashRoce1Field1: 6179 case bcmSwitchHashRoce2IP4Field0: 6180 case bcmSwitchHashRoce2IP4Field1: 6181 case bcmSwitchHashRoce2IP6Field0: 6182 case bcmSwitchHashRoce2IP6Field1: 6183 if (soc_feature(unit, soc_feature_rroce)) { 6184 return bcm_gh2_switch_rtag7_fieldselect_set(unit, 6185 type, arg); 6186 } else { 6187 return BCM_E_UNAVAIL; 6188 } 6189 break; 6190 6191 default: 6192 break; 6193 } 6194 6195 found = 0; /* True if one or more matches found */ 6196 BCM_IF_ERROR_RETURN( 6197 bcm_gh2_switch_control_port_binding_set(unit, port, 6198 type, arg, &found)); 6199 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 6200 } 6201 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 6202 return BCM_E_UNAVAIL; 6203 } 6204 6205 6206 6207 /* 6208 * Function: 6209 * bcm_gh2_switch_control_port_get 6210 * Description: 6211 * Retrieve general switch behaviors on a per-port basis 6212 * Parameters: 6213 * unit - Device unit number 6214 * port - Port to check 6215 * type - The desired configuration parameter to retrieve 6216 * arg - Pointer to where the retrieved value will be written 6217 * Returns: 6218 * BCM_E_xxx 6219 */ 6220 6221 int 6222 bcm_gh2_switch_control_port_get(int unit, 6223 bcm_port_t port, 6224 bcm_switch_control_t type, 6225 int *arg) 6226 { 6227 6228 if ((type == bcmSwitchFailoverStackTrunk) || 6229 (type == bcmSwitchFailoverEtherTrunk)) { 6230 return BCM_E_UNAVAIL; 6231 } 6232 6233 if (BCM_GPORT_IS_SET(port)) { 6234 BCM_IF_ERROR_RETURN 6235 (bcm_gh2_switch_control_port_validate(unit, port, type, &port)); 6236 } 6237 6238 #ifdef BCM_XGS3_SWITCH_SUPPORT 6239 if (SOC_IS_XGS3_SWITCH(unit)) { 6240 int found; 6241 switch(type) { 6242 case bcmSwitchPktAge: 6243 return _bcm_gh2_pkt_age_get(unit, arg); 6244 break; 6245 case bcmSwitchHashL2: 6246 case bcmSwitchHashL3: 6247 case bcmSwitchHashMultipath: 6248 case bcmSwitchHashIpfixIngress: 6249 case bcmSwitchHashIpfixEgress: 6250 case bcmSwitchHashIpfixIngressDual: 6251 case bcmSwitchHashIpfixEgressDual: 6252 case bcmSwitchHashVlanTranslate: 6253 case bcmSwitchHashMPLS: 6254 case bcmSwitchHashWlanPort: 6255 case bcmSwitchHashWlanPortDual: 6256 case bcmSwitchHashWlanClient: 6257 case bcmSwitchHashWlanClientDual: 6258 case bcmSwitchHashRegexAction: 6259 case bcmSwitchHashRegexActionDual: 6260 case bcmSwitchHashL3DNATPool: 6261 case bcmSwitchHashL3DNATPoolDual: 6262 case bcmSwitchHashVpVlanMemberIngress: 6263 case bcmSwitchHashVpVlanMemberIngressDual: 6264 case bcmSwitchHashVpVlanMemberEgress: 6265 case bcmSwitchHashVpVlanMemberEgressDual: 6266 case bcmSwitchHashL2Endpoint: 6267 case bcmSwitchHashL2EndpointDual: 6268 case bcmSwitchHashEndpointQueueMap: 6269 case bcmSwitchHashEndpointQueueMapDual: 6270 return _bcm_gh2_er_hashselect_get(unit, type, arg); 6271 break; 6272 case bcmSwitchHashControl: 6273 return _bcm_gh2_hashcontrol_get(unit, arg); 6274 break; 6275 case bcmSwitchFieldMultipathHashSelect: 6276 return _bcm_field_tr_multipath_hashcontrol_get(unit, arg); 6277 break; 6278 6279 case bcmSwitchL3IngressMode: 6280 #ifdef INCLUDE_L3 6281 if ((soc_feature(unit, soc_feature_l3)) && 6282 (soc_feature(unit,soc_feature_l3_ingress_interface))) { 6283 return bcm_xgs3_l3_ingress_mode_get(unit, arg); 6284 } 6285 #endif /* INCLUDE_L3 */ 6286 return BCM_E_UNAVAIL; 6287 break; 6288 case bcmSwitchL3IngressInterfaceMapSet: 6289 #ifdef INCLUDE_L3 6290 if ((soc_feature(unit, soc_feature_l3)) && 6291 (soc_feature(unit,soc_feature_l3_ingress_interface))) { 6292 return bcm_xgs3_l3_ingress_intf_map_get(unit, arg); 6293 } 6294 #endif /* INCLUDE_L3 */ 6295 return BCM_E_UNAVAIL; 6296 break; 6297 case bcmSwitchColorSelect: 6298 return _bcm_gh2_er_color_mode_get(unit, port, arg); 6299 break; 6300 case bcmSwitchModuleLoopback: 6301 return _bcm_gh2_mod_lb_get(unit, port, arg); 6302 break; 6303 case bcmSwitchIngressRateLimitIncludeIFG: 6304 return _bcm_gh2_ing_rate_limit_ifg_get(unit, port, arg); 6305 break; 6306 case bcmSwitchVrfMax: 6307 if (soc_feature(unit, soc_feature_l3)) { 6308 *arg = SOC_VRF_MAX(unit); 6309 return (BCM_E_NONE); 6310 } else { 6311 return BCM_E_UNAVAIL; 6312 } 6313 break; 6314 case bcmSwitchL3UrpfMode: 6315 if (soc_feature(unit, soc_feature_urpf)) { 6316 return _bcm_esw_port_config_get(unit, port, 6317 _bcmPortL3UrpfMode, arg); 6318 } 6319 return BCM_E_UNAVAIL; 6320 break; 6321 case bcmSwitchL3UrpfDefaultRoute: 6322 if (soc_feature(unit, soc_feature_urpf)) { 6323 return _bcm_esw_port_config_get(unit, port, 6324 _bcmPortL3UrpfDefaultRoute, arg); 6325 } 6326 return BCM_E_UNAVAIL; 6327 break; 6328 case bcmSwitchHashL2Dual: 6329 case bcmSwitchHashL3Dual: 6330 case bcmSwitchHashVlanTranslateDual: 6331 case bcmSwitchHashEgressVlanTranslate: 6332 case bcmSwitchHashEgressVlanTranslateDual: 6333 case bcmSwitchHashMPLSDual: 6334 if (soc_feature(unit, soc_feature_dual_hash)) { 6335 return _bcm_gh2_er_hashselect_get(unit, type, arg); 6336 } 6337 return BCM_E_UNAVAIL; 6338 break; 6339 case bcmSwitchHashSelectControl: 6340 return bcm_gh2_switch_rtag7_selectcontrol_get(unit, arg); 6341 break; 6342 case bcmSwitchHashIP4Field0: 6343 case bcmSwitchHashIP4Field1: 6344 case bcmSwitchHashIP6Field0: 6345 case bcmSwitchHashIP6Field1: 6346 case bcmSwitchHashL2Field0: 6347 case bcmSwitchHashL2Field1: 6348 case bcmSwitchHashHG2UnknownField0: 6349 case bcmSwitchHashHG2UnknownField1: 6350 return bcm_gh2_switch_rtag7_fieldselect_get(unit, type, arg); 6351 break; 6352 case bcmSwitchHashMPLSField0: 6353 case bcmSwitchHashMPLSField1: 6354 case bcmSwitchHashL2MPLSField0: 6355 case bcmSwitchHashL2MPLSField1: 6356 case bcmSwitchHashL3MPLSField0: 6357 case bcmSwitchHashL3MPLSField1: 6358 case bcmSwitchHashMPLSTunnelField0: 6359 case bcmSwitchHashMPLSTunnelField1: 6360 case bcmSwitchHashMIMTunnelField0: 6361 case bcmSwitchHashMIMTunnelField1: 6362 case bcmSwitchHashMIMField0: 6363 case bcmSwitchHashMIMField1: 6364 case bcmSwitchHashL3MiMField0: 6365 case bcmSwitchHashL3MiMField1: 6366 case bcmSwitchHashL3L2MPLSField0: 6367 case bcmSwitchHashL3L2MPLSField1: 6368 return BCM_E_UNAVAIL; 6369 break; 6370 case bcmSwitchHashL2VxlanField0: 6371 case bcmSwitchHashL2VxlanField1: 6372 case bcmSwitchHashL3VxlanField0: 6373 case bcmSwitchHashL3VxlanField1: 6374 return bcm_gh2_switch_rtag7_fieldselect_get(unit, type, arg); 6375 break; 6376 case bcmSwitchHashL2L2GreField0: 6377 case bcmSwitchHashL2L2GreField1: 6378 case bcmSwitchHashL3L2GreField0: 6379 case bcmSwitchHashL3L2GreField1: 6380 case bcmSwitchHashFCOEField0: 6381 case bcmSwitchHashFCOEField1: 6382 case bcmSwitchHashL2TrillField0: 6383 case bcmSwitchHashL2TrillField1: 6384 case bcmSwitchHashL3TrillField0: 6385 case bcmSwitchHashL3TrillField1: 6386 case bcmSwitchHashTrillTunnelField0: 6387 case bcmSwitchHashTrillTunnelField1: 6388 return BCM_E_UNAVAIL; 6389 break; 6390 case bcmSwitchHashIP4TcpUdpField0: 6391 case bcmSwitchHashIP4TcpUdpField1: 6392 case bcmSwitchHashIP4TcpUdpPortsEqualField0: 6393 case bcmSwitchHashIP4TcpUdpPortsEqualField1: 6394 case bcmSwitchHashIP6TcpUdpField0: 6395 case bcmSwitchHashIP6TcpUdpField1: 6396 case bcmSwitchHashIP6TcpUdpPortsEqualField0: 6397 case bcmSwitchHashIP6TcpUdpPortsEqualField1: 6398 return bcm_gh2_switch_rtag7_fieldselect_get(unit, type, arg); 6399 break; 6400 case bcmSwitchHashField0PreProcessEnable: 6401 { 6402 uint32 rtag7_hash_control_3; 6403 SOC_IF_ERROR_RETURN 6404 (READ_RTAG7_HASH_CONTROL_3r(unit, &rtag7_hash_control_3)); 6405 *arg = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_3r, 6406 rtag7_hash_control_3, HASH_PRE_PROCESSING_ENABLE_Af); 6407 } 6408 return BCM_E_NONE; 6409 break; 6410 case bcmSwitchHashField1PreProcessEnable: 6411 { 6412 uint32 rtag7_hash_control_3; 6413 SOC_IF_ERROR_RETURN 6414 (READ_RTAG7_HASH_CONTROL_3r(unit, &rtag7_hash_control_3)); 6415 *arg = soc_reg_field_get(unit, RTAG7_HASH_CONTROL_3r, 6416 rtag7_hash_control_3, HASH_PRE_PROCESSING_ENABLE_Bf); 6417 } 6418 return BCM_E_NONE; 6419 break; 6420 case bcmSwitchHashField0Config: 6421 case bcmSwitchHashField0Config1: 6422 case bcmSwitchHashField1Config: 6423 case bcmSwitchHashField1Config1: 6424 case bcmSwitchMacroFlowHashFieldConfig: 6425 return bcm_gh2_switch_rtag7_fieldconfig_get(unit, type, arg); 6426 break; 6427 case bcmSwitchTrunkHashSet1UnicastOffset: 6428 case bcmSwitchTrunkHashSet1NonUnicastOffset: 6429 case bcmSwitchFabricTrunkHashSet1UnicastOffset: 6430 case bcmSwitchFabricTrunkHashSet1NonUnicastOffset: 6431 case bcmSwitchLoadBalanceHashSet1UnicastOffset: 6432 case bcmSwitchLoadBalanceHashSet1NonUnicastOffset: 6433 return BCM_E_UNAVAIL; 6434 break; 6435 case bcmSwitchTrunkHashSet0UnicastOffset: 6436 case bcmSwitchTrunkHashSet0NonUnicastOffset: 6437 case bcmSwitchECMPHashSet0Offset: 6438 case bcmSwitchECMPVxlanHashOffset: 6439 case bcmSwitchEntropyHashSet0Offset: 6440 case bcmSwitchFabricTrunkHashSet0UnicastOffset: 6441 case bcmSwitchFabricTrunkHashSet0NonUnicastOffset: 6442 case bcmSwitchLoadBalanceHashSet0UnicastOffset: 6443 case bcmSwitchLoadBalanceHashSet0NonUnicastOffset: 6444 case bcmSwitchFabricTrunkFailoverHashOffset: 6445 return bcm_gh2_switch_rtag7_fieldoffset_get(unit, port, 6446 type, arg); 6447 break; 6448 case bcmSwitchEcmpRoce2HashOffset: 6449 if (soc_feature(unit, soc_feature_rroce)) { 6450 return bcm_gh2_switch_rtag7_fieldoffset_get(unit, port, 6451 type, arg); 6452 } else { 6453 return BCM_E_UNAVAIL; 6454 } 6455 break; 6456 case bcmSwitchFabricTrunkDynamicHashOffset: 6457 case bcmSwitchTrunkDynamicHashOffset: 6458 case bcmSwitchEcmpDynamicHashOffset: 6459 case bcmSwitchFabricTrunkResilientHashOffset: 6460 case bcmSwitchTrunkResilientHashOffset: 6461 case bcmSwitchEcmpResilientHashOffset: 6462 case bcmSwitchTrunkFailoverHashOffset: 6463 case bcmSwitchECMPUnderlayHashSet0Offset: 6464 case bcmSwitchECMPUnderlayVxlanHashOffset: 6465 case bcmSwitchECMPL2GreHashOffset: 6466 case bcmSwitchECMPUnderlayL2GreHashOffset: 6467 case bcmSwitchECMPTrillHashOffset: 6468 case bcmSwitchECMPUnderlayTrillHashOffset: 6469 case bcmSwitchECMPMplsHashOffset: 6470 case bcmSwitchVirtualPortDynamicHashOffset: 6471 case bcmSwitchECMPOverlayHashOffset: 6472 case bcmSwitchVirtualPortUnderlayDynamicHashOffset: 6473 return BCM_E_UNAVAIL; 6474 break; 6475 case bcmSwitchIgmpPktToCpu: 6476 case bcmSwitchIgmpPktDrop: 6477 case bcmSwitchMldPktToCpu: 6478 case bcmSwitchMldPktDrop: 6479 case bcmSwitchV4ResvdMcPktToCpu: 6480 case bcmSwitchV4ResvdMcPktFlood: 6481 case bcmSwitchV4ResvdMcPktDrop: 6482 case bcmSwitchV6ResvdMcPktToCpu: 6483 case bcmSwitchV6ResvdMcPktFlood: 6484 case bcmSwitchV6ResvdMcPktDrop: 6485 case bcmSwitchIgmpReportLeaveDrop: 6486 case bcmSwitchIgmpReportLeaveFlood: 6487 case bcmSwitchIgmpReportLeaveToCpu: 6488 case bcmSwitchIgmpQueryDrop: 6489 case bcmSwitchIgmpQueryFlood: 6490 case bcmSwitchIgmpQueryToCpu: 6491 case bcmSwitchIgmpUnknownDrop: 6492 case bcmSwitchIgmpUnknownFlood: 6493 case bcmSwitchIgmpUnknownToCpu: 6494 case bcmSwitchMldReportDoneDrop: 6495 case bcmSwitchMldReportDoneFlood: 6496 case bcmSwitchMldReportDoneToCpu: 6497 case bcmSwitchMldQueryDrop: 6498 case bcmSwitchMldQueryFlood: 6499 case bcmSwitchMldQueryToCpu: 6500 case bcmSwitchIpmcV4RouterDiscoveryDrop: 6501 case bcmSwitchIpmcV4RouterDiscoveryFlood: 6502 case bcmSwitchIpmcV4RouterDiscoveryToCpu: 6503 case bcmSwitchIpmcV6RouterDiscoveryDrop: 6504 case bcmSwitchIpmcV6RouterDiscoveryFlood: 6505 case bcmSwitchIpmcV6RouterDiscoveryToCpu: 6506 return _bcm_gh2_igmp_action_get(unit, port, type, arg); 6507 break; 6508 case bcmSwitchDirectedMirroring: 6509 *arg = 1; 6510 return BCM_E_NONE; 6511 break; 6512 case bcmSwitchFlexibleMirrorDestinations: 6513 case bcmSwitchMirrorExclusive: 6514 return BCM_E_UNAVAIL; 6515 break; 6516 case bcmSwitchL3EgressMode: 6517 #ifdef INCLUDE_L3 6518 if (soc_feature(unit, soc_feature_l3)) { 6519 return bcm_xgs3_l3_egress_mode_get(unit, arg); 6520 } 6521 #endif /* INCLUDE_L3 */ 6522 break; 6523 case bcmSwitchL3HostAsRouteReturnValue: 6524 #ifdef INCLUDE_L3 6525 if (soc_feature(unit, soc_feature_l3)) { 6526 return bcm_xgs3_l3_host_as_route_return_get(unit, arg); 6527 } 6528 #endif /* INCLUDE_L3 */ 6529 return BCM_E_UNAVAIL; 6530 break; 6531 6532 case bcmSwitchL3DefipMultipathCountUpdate: 6533 #ifdef INCLUDE_L3 6534 if(soc_feature(unit, soc_feature_l3_defip_ecmp_count)) { 6535 *arg = 1; 6536 return BCM_E_NONE; 6537 } 6538 #endif /* INCLUDE_L3 */ 6539 return BCM_E_UNAVAIL; 6540 break; 6541 case bcmSwitchIpmcReplicationSharing: 6542 #ifdef INCLUDE_L3 6543 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 6544 *arg = SOC_IPMCREPLSHR_GET(unit); 6545 return BCM_E_NONE; 6546 } 6547 #endif /* INCLUDE_L3 */ 6548 return BCM_E_UNAVAIL; 6549 break; 6550 case bcmSwitchIpmcReplicationAvailabilityThreshold: 6551 #ifdef INCLUDE_L3 6552 if (soc_feature(unit, soc_feature_ip_mcast_repl)) { 6553 return _bcm_esw_ipmc_repl_threshold_get(unit, arg); 6554 } 6555 #endif /* INCLUDE_L3 */ 6556 return BCM_E_UNAVAIL; 6557 break; 6558 case bcmSwitchHashDualMoveDepth: 6559 if (soc_feature(unit, soc_feature_dual_hash)) { 6560 *arg = SOC_DUAL_HASH_MOVE_MAX(unit); 6561 return BCM_E_NONE; 6562 } 6563 return BCM_E_UNAVAIL; 6564 break; 6565 case bcmSwitchHashDualMoveDepthL2: 6566 if (soc_feature(unit, soc_feature_dual_hash)) { 6567 *arg = SOC_DUAL_HASH_MOVE_MAX_L2X(unit); 6568 return BCM_E_NONE; 6569 } 6570 return BCM_E_UNAVAIL; 6571 break; 6572 case bcmSwitchHashDualMoveDepthMpls: 6573 if (soc_feature(unit, soc_feature_dual_hash)) { 6574 *arg = SOC_DUAL_HASH_MOVE_MAX_MPLS(unit); 6575 return BCM_E_NONE; 6576 } 6577 return BCM_E_UNAVAIL; 6578 break; 6579 case bcmSwitchHashDualMoveDepthVlan: 6580 if (soc_feature(unit, soc_feature_dual_hash)) { 6581 *arg = SOC_DUAL_HASH_MOVE_MAX_VLAN(unit); 6582 return BCM_E_NONE; 6583 } 6584 return BCM_E_UNAVAIL; 6585 break; 6586 case bcmSwitchHashDualMoveDepthEgressVlan: 6587 if (soc_feature(unit, soc_feature_dual_hash)) { 6588 *arg = SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit); 6589 return BCM_E_NONE; 6590 } 6591 return BCM_E_UNAVAIL; 6592 break; 6593 #if defined(INCLUDE_L3) 6594 case bcmSwitchHashDualMoveDepthL3: 6595 if (soc_feature(unit, soc_feature_dual_hash)) { 6596 *arg = SOC_DUAL_HASH_MOVE_MAX_L3X(unit); 6597 return BCM_E_NONE; 6598 } 6599 return BCM_E_UNAVAIL; 6600 break; 6601 #endif /* INCLUDE_L3 */ 6602 case bcmSwitchHashDualMoveDepthWlanPort: 6603 case bcmSwitchHashDualMoveDepthWlanClient: 6604 return BCM_E_UNAVAIL; 6605 break; 6606 case bcmSwitchL2PortBlocking: 6607 if (soc_feature(unit, soc_feature_src_mac_group)) { 6608 *arg = (!SOC_L2X_GROUP_ENABLE_GET(unit)); 6609 return BCM_E_NONE; 6610 } 6611 return BCM_E_UNAVAIL; 6612 break; 6613 6614 case bcmSwitchTimeSyncPktDrop: 6615 case bcmSwitchTimeSyncPktFlood: 6616 case bcmSwitchTimeSyncPktToCpu: 6617 case bcmSwitchMmrpPktDrop: 6618 case bcmSwitchMmrpPktFlood: 6619 case bcmSwitchMmrpPktToCpu: 6620 case bcmSwitchSrpPktDrop: 6621 case bcmSwitchSrpPktFlood: 6622 case bcmSwitchSrpPktToCpu: 6623 case bcmSwitchSRPEthertype: 6624 case bcmSwitchMMRPEthertype: 6625 case bcmSwitchTimeSyncEthertype: 6626 case bcmSwitchSRPDestMacOui: 6627 case bcmSwitchMMRPDestMacOui: 6628 case bcmSwitchSRPDestMacNonOui: 6629 case bcmSwitchMMRPDestMacNonOui: 6630 case bcmSwitchTimeSyncDestMacNonOui: 6631 case bcmSwitchTimeSyncMessageTypeBitmap: 6632 case bcmSwitchTimeSyncClassAPktPrio: 6633 case bcmSwitchTimeSyncClassBPktPrio: 6634 case bcmSwitchTimeSyncClassAExeptionPktPrio: 6635 case bcmSwitchTimeSyncClassBExeptionPktPrio: 6636 case bcmSwitchStgInvalidToCpu: 6637 case bcmSwitchVlanTranslateEgressMissToCpu: 6638 case bcmSwitchL3PktErrToCpu: 6639 case bcmSwitchMtuFailureToCpu: 6640 case bcmSwitchSrcKnockoutToCpu: 6641 case bcmSwitchWlanTunnelMismatchToCpu: 6642 case bcmSwitchWlanTunnelMismatchDrop: 6643 case bcmSwitchWlanPortMissToCpu: 6644 case bcmSwitchUnknownVlanToCpuCosq: 6645 case bcmSwitchStgInvalidToCpuCosq: 6646 case bcmSwitchVlanTranslateEgressMissToCpuCosq: 6647 case bcmSwitchTunnelErrToCpuCosq: 6648 case bcmSwitchL3HeaderErrToCpuCosq: 6649 case bcmSwitchL3PktErrToCpuCosq: 6650 case bcmSwitchIpmcTtlErrToCpuCosq: 6651 case bcmSwitchMtuFailureToCpuCosq: 6652 case bcmSwitchHgHdrErrToCpuCosq: 6653 case bcmSwitchSrcKnockoutToCpuCosq: 6654 case bcmSwitchWlanTunnelMismatchToCpuCosq: 6655 case bcmSwitchWlanPortMissToCpuCosq: 6656 return BCM_E_UNAVAIL; 6657 break; 6658 case bcmSwitchLayeredQoSResolution: 6659 return _bcm_gh2_layered_qos_resolution_get(unit, port, type, arg); 6660 break; 6661 case bcmSwitchEncapErrorToCpu: 6662 case bcmSwitchMirrorEgressTrueColorSelect: 6663 case bcmSwitchMirrorEgressTruePriority: 6664 case bcmSwitchL3UrpfRouteEnableExternal: 6665 return BCM_E_UNAVAIL; 6666 break; 6667 case bcmSwitchLinkDownInfoSkip: 6668 return _bcm_esw_link_port_info_skip_get(unit, port, arg); 6669 break; 6670 case bcmSwitchDropSobmhOnLinkDown: 6671 case bcmSwitchCongestionNotificationIdLow: 6672 return BCM_E_UNAVAIL; 6673 break; 6674 case bcmSwitchMeterAdjust: 6675 if (soc_feature(unit, soc_feature_meter_adjust)) { 6676 return _bcm_gh2_meter_adjust_get(unit, port, arg); 6677 } 6678 break; 6679 case bcmSwitchShaperAdjust: 6680 if (soc_feature(unit, soc_feature_meter_adjust)) { 6681 return _bcm_gh2_shaper_adjust_get(unit, port, arg); 6682 } 6683 break; 6684 6685 case bcmSwitchPFCClass0Queue: 6686 case bcmSwitchPFCClass1Queue: 6687 case bcmSwitchPFCClass2Queue: 6688 case bcmSwitchPFCClass3Queue: 6689 case bcmSwitchPFCClass4Queue: 6690 case bcmSwitchPFCClass5Queue: 6691 case bcmSwitchPFCClass6Queue: 6692 case bcmSwitchPFCClass7Queue: 6693 case bcmSwitchPFCClass0McastQueue: 6694 case bcmSwitchPFCClass1McastQueue: 6695 case bcmSwitchPFCClass2McastQueue: 6696 case bcmSwitchPFCClass3McastQueue: 6697 case bcmSwitchPFCClass4McastQueue: 6698 case bcmSwitchPFCClass5McastQueue: 6699 case bcmSwitchPFCClass6McastQueue: 6700 case bcmSwitchPFCClass7McastQueue: 6701 case bcmSwitchPFCClass0DestmodQueue: 6702 case bcmSwitchPFCClass1DestmodQueue: 6703 case bcmSwitchPFCClass2DestmodQueue: 6704 case bcmSwitchPFCClass3DestmodQueue: 6705 case bcmSwitchPFCClass4DestmodQueue: 6706 case bcmSwitchPFCClass5DestmodQueue: 6707 case bcmSwitchPFCClass6DestmodQueue: 6708 case bcmSwitchPFCClass7DestmodQueue: 6709 return bcmi_gh2_cosq_port_pfc_get(unit, port, type, arg); 6710 break; 6711 case bcmSwitchEntropyHashSet1Offset: 6712 case bcmSwitchMiMDefaultSVP: 6713 case bcmSwitchAlternateStoreForward: 6714 case bcmSwitchMcQueueSchedMode: 6715 return BCM_E_UNAVAIL; 6716 break; 6717 case bcmSwitchTimesyncEgressTimestampingMode: 6718 if (soc_feature(unit, soc_feature_timesync_support) && 6719 soc_feature(unit, soc_feature_timesync_timestampingmode)) { 6720 return _bcm_esw_port_timesync_timestamping_mode_get(unit, port, 6721 (bcm_switch_timesync_timestamping_mode_t*)arg); 6722 } 6723 return BCM_E_UNAVAIL; 6724 break; 6725 case bcmSwitchHashRoce1Field0: 6726 case bcmSwitchHashRoce1Field1: 6727 case bcmSwitchHashRoce2IP4Field0: 6728 case bcmSwitchHashRoce2IP4Field1: 6729 case bcmSwitchHashRoce2IP6Field0: 6730 case bcmSwitchHashRoce2IP6Field1: 6731 if (soc_feature(unit, soc_feature_rroce)) { 6732 return bcm_gh2_switch_rtag7_fieldselect_get(unit, type, 6733 arg); 6734 } else { 6735 return BCM_E_UNAVAIL; 6736 } 6737 break; 6738 6739 default : 6740 break; 6741 } 6742 6743 found = 0; 6744 bcm_gh2_switch_control_port_binding_get(unit, port, type, arg, &found); 6745 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 6746 6747 } 6748 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 6749 return BCM_E_UNAVAIL; 6750 } 6751 6752 6753 /* 6754 * Function: 6755 * bcm_gh2_switch_control_set 6756 * Description: 6757 * Specify general switch behaviors. 6758 * Parameters: 6759 * unit - Device unit number 6760 * type - The desired configuration parameter to modify 6761 * arg - The value with which to set the parameter 6762 * Returns: 6763 * BCM_E_xxx 6764 * Notes: 6765 * For behaviors which are port-specific, all non-stack ports 6766 * will be set. 6767 */ 6768 6769 int 6770 bcm_gh2_switch_control_set(int unit, 6771 bcm_switch_control_t type, 6772 int arg) 6773 { 6774 bcm_port_t port; 6775 int rv, found; 6776 #if defined(BCM_WARM_BOOT_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 6777 int stable_select; 6778 #endif 6779 6780 /* Check for device wide, non port specific controls */ 6781 switch (type) { 6782 case bcmSwitchWarmBoot: 6783 /* If true, set the Warm Boot state; clear otherwise */ 6784 if (arg) { 6785 #ifdef BCM_WARM_BOOT_SUPPORT 6786 /* Cannot be set to anything but FALSE */ 6787 return BCM_E_PARAM; 6788 #else 6789 return SOC_E_UNAVAIL; 6790 #endif 6791 } else { 6792 #ifdef BCM_WARM_BOOT_SUPPORT 6793 SOC_WARM_BOOT_DONE(unit); 6794 #else 6795 return SOC_E_UNAVAIL; 6796 #endif 6797 } 6798 return BCM_E_NONE; 6799 break; 6800 case bcmSwitchStableSelect: 6801 /* Cannot be called once bcm_init is complete */ 6802 return SOC_E_UNAVAIL; 6803 break; 6804 case bcmSwitchStableSize: 6805 /* Cannot be called once bcm_init is complete */ 6806 return SOC_E_UNAVAIL; 6807 break; 6808 case bcmSwitchControlSync: 6809 #if defined(BCM_WARM_BOOT_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 6810 rv = _bcm_gh2_switch_control_sync(unit, arg); 6811 return rv; 6812 #else 6813 return SOC_E_UNAVAIL; 6814 #endif 6815 break; 6816 case bcmSwitchControlAutoSync: 6817 #if defined(BCM_WARM_BOOT_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 6818 BCM_IF_ERROR_RETURN 6819 (bcm_gh2_switch_control_get(unit, bcmSwitchStableSelect, 6820 &stable_select)); 6821 if (BCM_SWITCH_STABLE_NONE != stable_select) { 6822 SOC_CONTROL_LOCK(unit); 6823 SOC_CONTROL(unit)->autosync = arg ? 1 : 0; 6824 SOC_CONTROL_UNLOCK(unit); 6825 return BCM_E_NONE; 6826 } else { 6827 return BCM_E_NOT_FOUND; 6828 } 6829 #else 6830 return SOC_E_UNAVAIL; 6831 #endif 6832 break; 6833 case bcmSwitchModuleType: 6834 return(_bcm_gh2_switch_module_type_set(unit, 6835 BCM_SWITCH_CONTROL_MODID_UNPACK(arg), 6836 BCM_SWITCH_CONTROL_MODTYPE_UNPACK(arg))); 6837 break; 6838 #ifdef BCM_CB_ABORT_ON_ERR 6839 case bcmSwitchCallbackAbortOnError: 6840 if (arg >= 0) { 6841 SOC_CB_ABORT_ON_ERR(unit) = arg ? 1 : 0; 6842 return BCM_E_NONE; 6843 } else { 6844 return BCM_E_PARAM; 6845 } 6846 break; 6847 #endif 6848 6849 case bcmSwitchIpmcGroupMtu: 6850 case bcmSwitchLoopbackMtuSize: 6851 return BCM_E_UNAVAIL; 6852 break; 6853 case bcmSwitchMcastFloodDefault: 6854 return(_bcm_esw_vlan_flood_default_set(unit, arg)); 6855 break; 6856 case bcmSwitchUseGport: 6857 SOC_USE_GPORT_SET(unit, arg); 6858 return BCM_E_NONE; 6859 break; 6860 case bcmSwitchHgHdrMcastFlood: 6861 return(_bcm_esw_higig_flood_l2_set(unit, arg)); 6862 break; 6863 case bcmSwitchHgHdrIpMcastFlood: 6864 case bcmSwitchFailoverStackTrunk: 6865 case bcmSwitchFailoverEtherTrunk: 6866 case bcmSwitchMcastL2Range: 6867 case bcmSwitchMcastL3Range: 6868 return BCM_E_UNAVAIL; 6869 break; 6870 6871 /* coverity[equality_cond] */ 6872 case bcmSwitchHgHdrMcastVlanRange: 6873 case bcmSwitchHgHdrMcastL2Range: 6874 case bcmSwitchHgHdrMcastL3Range: 6875 { 6876 int bc_size, mc_size, ipmc_size; 6877 BCM_IF_ERROR_RETURN 6878 (soc_hbx_higig2_mcast_sizes_get(unit, &bc_size, 6879 &mc_size, &ipmc_size)); 6880 switch (type) { 6881 case bcmSwitchHgHdrMcastVlanRange: 6882 bc_size = arg; 6883 break; 6884 case bcmSwitchHgHdrMcastL2Range: 6885 mc_size = arg; 6886 break; 6887 case bcmSwitchHgHdrMcastL3Range: 6888 ipmc_size = arg; 6889 break; 6890 /* Defensive Default */ 6891 /* coverity[dead_error_begin] */ 6892 default: 6893 return BCM_E_PARAM; 6894 } 6895 return soc_hbx_higig2_mcast_sizes_set(unit, bc_size, 6896 mc_size, ipmc_size); 6897 } 6898 break; 6899 6900 case bcmSwitchHashSeed0: 6901 return soc_reg_field32_modify 6902 (unit, RTAG7_HASH_SEED_Ar, REG_PORT_ANY, HASH_SEED_Af, arg); 6903 break; 6904 case bcmSwitchHashSeed1: 6905 return soc_reg_field32_modify 6906 (unit, RTAG7_HASH_SEED_Br, REG_PORT_ANY, HASH_SEED_Bf, arg); 6907 break; 6908 case bcmSwitchMacroFlowHashMinOffset: 6909 case bcmSwitchMacroFlowHashMaxOffset: 6910 case bcmSwitchMacroFlowHashStrideOffset: 6911 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 6912 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 6913 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 6914 case bcmSwitchMacroFlowTrunkHashMinOffset: 6915 case bcmSwitchMacroFlowTrunkHashMaxOffset: 6916 case bcmSwitchMacroFlowTrunkHashStrideOffset: 6917 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 6918 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 6919 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 6920 /* RTAG7 Macro Flow Concatenation */ 6921 case bcmSwitchMacroFlowEcmpHashConcatEnable: 6922 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 6923 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 6924 case bcmSwitchMacroFlowTrunkHashConcatEnable: 6925 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 6926 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 6927 return bcm_gh2_switch_rtag7_macroflow_offset_set(unit, 6928 type, arg); 6929 } 6930 return BCM_E_UNAVAIL; 6931 break; 6932 case bcmSwitchMacroFlowHashOverlayMinOffset: 6933 case bcmSwitchMacroFlowHashOverlayMaxOffset: 6934 case bcmSwitchMacroFlowHashOverlayStrideOffset: 6935 case bcmSwitchMacroFlowEcmpHashOverlayConcatEnable: 6936 return BCM_E_UNAVAIL; 6937 break; 6938 /* RTAG7 Macro Flow Hash Seed */ 6939 case bcmSwitchMacroFlowECMPHashSeed: 6940 case bcmSwitchMacroFlowECMPUnderlayHashSeed: 6941 case bcmSwitchMacroFlowLoadBalanceHashSeed: 6942 case bcmSwitchMacroFlowTrunkHashSeed: 6943 case bcmSwitchMacroFlowHigigTrunkHashSeed: 6944 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 6945 return bcm_gh2_switch_rtag7_macroflow_hash_set(unit, 6946 type, arg); 6947 } 6948 return BCM_E_UNAVAIL; 6949 break; 6950 case bcmSwitchMacroFlowECMPOverlayHashSeed: 6951 /* Hash Field select controls */ 6952 case bcmSwitchHashTrillPayloadSelect0: 6953 case bcmSwitchHashTrillPayloadSelect1: 6954 case bcmSwitchHashTrillTunnelSelect0: 6955 case bcmSwitchHashTrillTunnelSelect1: 6956 return BCM_E_UNAVAIL; 6957 break; 6958 6959 case bcmSwitchHashVxlanPayloadSelect0: 6960 case bcmSwitchHashVxlanPayloadSelect1: 6961 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 6962 return bcm_gh2_switch_rtag7_field_control_set(unit, type, arg); 6963 } 6964 return BCM_E_UNAVAIL; 6965 break; 6966 case bcmSwitchHashIP6AddrCollapseSelect0: 6967 case bcmSwitchHashIP6AddrCollapseSelect1: 6968 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 6969 return bcm_gh2_switch_rtag7_field_control_set(unit, type, arg); 6970 } 6971 return BCM_E_UNAVAIL; 6972 break; 6973 case bcmSwitchHashIP6NextHeaderUseExtensionHeader0: 6974 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 6975 return soc_reg_field32_modify 6976 (unit, RTAG7_HASH_CONTROLr, REG_PORT_ANY, 6977 DISABLE_HASH_IP_EXTENSION_HEADERS_Af, (arg) ? 0 : 1); 6978 } 6979 return BCM_E_UNAVAIL; 6980 break; 6981 case bcmSwitchHashIP6NextHeaderUseExtensionHeader1: 6982 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 6983 return soc_reg_field32_modify 6984 (unit, RTAG7_HASH_CONTROLr, REG_PORT_ANY, 6985 DISABLE_HASH_IP_EXTENSION_HEADERS_Bf, (arg) ? 0 : 1); 6986 } 6987 return BCM_E_UNAVAIL; 6988 break; 6989 case bcmSwitchHashL2MPLSPayloadSelect0: 6990 case bcmSwitchHashL2MPLSPayloadSelect1: 6991 case bcmSwitchHashIPSecSelect0: 6992 case bcmSwitchHashIPSecSelect1: 6993 case bcmSwitchHashMiMPayloadSelect0: 6994 case bcmSwitchHashMiMPayloadSelect1: 6995 return BCM_E_UNAVAIL; 6996 break; 6997 case bcmSwitchL2McastAllRouterPortsAddEnable: 6998 SOC_MCAST_ADD_ALL_ROUTER_PORTS(unit) = arg ? 1 : 0; 6999 return BCM_E_NONE; 7000 break; 7001 case bcmSwitchPFCClass0Queue: 7002 case bcmSwitchPFCClass1Queue: 7003 case bcmSwitchPFCClass2Queue: 7004 case bcmSwitchPFCClass3Queue: 7005 case bcmSwitchPFCClass4Queue: 7006 case bcmSwitchPFCClass5Queue: 7007 case bcmSwitchPFCClass6Queue: 7008 case bcmSwitchPFCClass7Queue: 7009 return BCM_E_UNAVAIL; 7010 break; 7011 case bcmSwitchL2HitClear: 7012 case bcmSwitchL2SrcHitClear: 7013 case bcmSwitchL2DstHitClear: 7014 case bcmSwitchL3HostHitClear: 7015 case bcmSwitchL3RouteHitClear: 7016 return _bcm_gh2_switch_hit_clear_set(unit, type, arg); 7017 break; 7018 /* This swithc control should be supported only per port. */ 7019 case bcmSwitchEncapErrorToCpu: 7020 return BCM_E_UNAVAIL; 7021 break; 7022 case bcmSwitchSnapNonZeroOui: 7023 SOC_IF_ERROR_RETURN 7024 (soc_reg_field32_modify(unit, ING_CONFIG_64r, REG_PORT_ANY, 7025 SNAP_OTHER_DECODE_ENABLEf, 7026 arg ? 1 : 0)); 7027 SOC_IF_ERROR_RETURN 7028 (soc_reg_field32_modify(unit, EGR_CONFIGr, REG_PORT_ANY, 7029 SNAP_OTHER_DECODE_ENABLEf, 7030 arg ? 1 : 0)); 7031 return BCM_E_NONE; 7032 break; 7033 case bcmSwitchL2McIdxRetType: 7034 return _bcm_esw_mcast_idx_ret_type_set(unit, arg); 7035 break; 7036 case bcmSwitchL2ExtLearn: 7037 return BCM_E_UNAVAIL; 7038 break; 7039 case bcmSwitchL3McIdxRetType: 7040 #ifdef INCLUDE_L3 7041 return _bcm_esw_ipmc_idx_ret_type_set(unit, arg); 7042 #endif 7043 return BCM_E_UNAVAIL; 7044 break; 7045 case bcmSwitchL2SourceDiscardMoveToCpu: 7046 { 7047 soc_reg_t reg; 7048 reg = ING_CONFIG_64r; 7049 BCM_IF_ERROR_RETURN( 7050 soc_reg_field32_modify(unit, reg, REG_PORT_ANY, 7051 STNMOVE_ON_L2SRC_DISCf, arg ? 1: 0)); 7052 return BCM_E_NONE; 7053 } 7054 break; 7055 case bcmSwitchFabricTrunkDynamicSampleRate: 7056 case bcmSwitchFabricTrunkDynamicEgressBytesExponent: 7057 case bcmSwitchFabricTrunkDynamicQueuedBytesExponent: 7058 case bcmSwitchFabricTrunkDynamicEgressBytesDecreaseReset: 7059 case bcmSwitchFabricTrunkDynamicQueuedBytesDecreaseReset: 7060 case bcmSwitchFabricTrunkDynamicEgressBytesMinThreshold: 7061 case bcmSwitchFabricTrunkDynamicEgressBytesMaxThreshold: 7062 case bcmSwitchFabricTrunkDynamicQueuedBytesMinThreshold: 7063 case bcmSwitchFabricTrunkDynamicQueuedBytesMaxThreshold: 7064 case bcmSwitchTrunkDynamicSampleRate: 7065 case bcmSwitchTrunkDynamicAccountingSelect: 7066 case bcmSwitchTrunkDynamicEgressBytesExponent: 7067 case bcmSwitchTrunkDynamicQueuedBytesExponent: 7068 case bcmSwitchTrunkDynamicEgressBytesDecreaseReset: 7069 case bcmSwitchTrunkDynamicQueuedBytesDecreaseReset: 7070 case bcmSwitchTrunkDynamicEgressBytesMinThreshold: 7071 case bcmSwitchTrunkDynamicEgressBytesMaxThreshold: 7072 case bcmSwitchTrunkDynamicQueuedBytesMinThreshold: 7073 case bcmSwitchTrunkDynamicQueuedBytesMaxThreshold: 7074 case bcmSwitchTrunkDynamicExpectedLoadMinThreshold: 7075 case bcmSwitchTrunkDynamicExpectedLoadMaxThreshold: 7076 case bcmSwitchTrunkDynamicImbalanceMinThreshold: 7077 case bcmSwitchTrunkDynamicImbalanceMaxThreshold: 7078 case bcmSwitchEcmpDynamicSampleRate: 7079 case bcmSwitchEcmpDynamicAccountingSelect: 7080 case bcmSwitchEcmpDynamicEgressBytesExponent: 7081 case bcmSwitchEcmpDynamicQueuedBytesExponent: 7082 case bcmSwitchEcmpDynamicEgressBytesDecreaseReset: 7083 case bcmSwitchEcmpDynamicQueuedBytesDecreaseReset: 7084 case bcmSwitchEcmpDynamicEgressBytesMinThreshold: 7085 case bcmSwitchEcmpDynamicEgressBytesMaxThreshold: 7086 case bcmSwitchEcmpDynamicQueuedBytesMinThreshold: 7087 case bcmSwitchEcmpDynamicQueuedBytesMaxThreshold: 7088 case bcmSwitchEcmpDynamicExpectedLoadMinThreshold: 7089 case bcmSwitchEcmpDynamicExpectedLoadMaxThreshold: 7090 case bcmSwitchEcmpDynamicImbalanceMinThreshold: 7091 case bcmSwitchEcmpDynamicImbalanceMaxThreshold: 7092 return BCM_E_UNAVAIL; 7093 break; 7094 7095 #if (defined(BCM_RCPU_SUPPORT) || defined(BCM_OOB_RCPU_SUPPORT)) && \ 7096 defined(BCM_XGS3_SWITCH_SUPPORT) 7097 case bcmSwitchRemoteCpuSchanEnable: 7098 if (soc_feature(unit, soc_feature_rcpu_1)) { 7099 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CMIC_PKT_CTRLr, 7100 REG_PORT_ANY, ENABLE_SCHAN_REQUESTf, arg)); 7101 return BCM_E_NONE; 7102 } else { 7103 return BCM_E_UNAVAIL; 7104 } 7105 break; 7106 case bcmSwitchRemoteCpuMatchLocalMac: 7107 if (soc_feature(unit, soc_feature_rcpu_1)) { 7108 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7109 CMIC_PKT_CTRLr, REG_PORT_ANY, LMAC0_MATCHf, arg)); 7110 return BCM_E_NONE; 7111 } else { 7112 return BCM_E_UNAVAIL; 7113 } 7114 break; 7115 case bcmSwitchRemoteCpuFromCpuEnable: 7116 if (soc_feature(unit, soc_feature_rcpu_1)) { 7117 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7118 CMIC_PKT_CTRLr, REG_PORT_ANY, ENABLE_FROMCPU_PACKETf, arg)); 7119 return BCM_E_NONE; 7120 } else { 7121 return BCM_E_UNAVAIL; 7122 } 7123 break; 7124 case bcmSwitchRemoteCpuToCpuEnable: 7125 if (soc_feature(unit, soc_feature_rcpu_1)) { 7126 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7127 CMIC_PKT_CTRLr, REG_PORT_ANY, ENABLE_TOCPU_PACKETf, arg)); 7128 return BCM_E_NONE; 7129 } else { 7130 return BCM_E_UNAVAIL; 7131 } 7132 break; 7133 case bcmSwitchRemoteCpuCmicEnable: 7134 #ifdef BCM_CMICM_SUPPORT 7135 if (soc_feature(unit, soc_feature_cmicm)) { 7136 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7137 CMIC_PKT_CTRLr, REG_PORT_ANY, ENABLE_CMIC_REQUESTf, arg)); 7138 return BCM_E_NONE; 7139 } else 7140 #endif 7141 { 7142 return BCM_E_UNAVAIL; 7143 } 7144 break; 7145 case bcmSwitchRemoteCpuMatchVlan: 7146 if (soc_feature(unit, soc_feature_rcpu_1)) { 7147 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7148 CMIC_PKT_CTRLr, REG_PORT_ANY, VLAN_MATCHf, arg)); 7149 return BCM_E_NONE; 7150 } else { 7151 return BCM_E_UNAVAIL; 7152 } 7153 break; 7154 case bcmSwitchRemoteCpuForceScheduling: 7155 if (soc_feature(unit, soc_feature_rcpu_1)) { 7156 #ifdef BCM_CMICM_SUPPORT 7157 BCM_IF_ERROR_RETURN( 7158 _bcm_gh2_rcpu_switch_regall_set(unit, CMIC_PKT_COS_0r, 7159 COSf, arg)); 7160 BCM_IF_ERROR_RETURN( 7161 _bcm_gh2_rcpu_switch_regall_set(unit, CMIC_PKT_COS_1r, 7162 COSf, arg)); 7163 return BCM_E_NONE; 7164 } else 7165 #endif 7166 { 7167 return BCM_E_UNAVAIL; 7168 } 7169 break; 7170 case bcmSwitchRemoteCpuToCpuDestPortAllReasons: 7171 if (soc_feature(unit, soc_feature_rcpu_1)) { 7172 #ifdef BCM_CMICM_SUPPORT 7173 int i; 7174 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr); i++) { 7175 BCM_IF_ERROR_RETURN( 7176 _bcm_gh2_rcpu_switch_regall_idx_set(unit, 7177 CMIC_PKT_REASON_DIRECT_0_TYPEr, 7178 i, REASONSf, arg)); 7179 } 7180 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr); i++) { 7181 BCM_IF_ERROR_RETURN( 7182 _bcm_gh2_rcpu_switch_regall_idx_set(unit, 7183 CMIC_PKT_REASON_DIRECT_1_TYPEr, 7184 i, REASONSf, arg)); 7185 } 7186 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_2_TYPEr); i++) { 7187 BCM_IF_ERROR_RETURN( 7188 _bcm_gh2_rcpu_switch_regall_idx_set(unit, 7189 CMIC_PKT_REASON_DIRECT_2_TYPEr, 7190 i, REASONSf, arg)); 7191 } 7192 return BCM_E_NONE; 7193 } else 7194 #endif 7195 { 7196 return BCM_E_UNAVAIL; 7197 } 7198 break; 7199 case bcmSwitchRemoteCpuToCpuDestMacAllReasons: 7200 if (soc_feature(unit, soc_feature_rcpu_1)) { 7201 #ifdef BCM_CMICM_SUPPORT 7202 int i; 7203 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_0_TYPEr); i++) { 7204 BCM_IF_ERROR_RETURN( 7205 _bcm_gh2_rcpu_switch_regall_idx_set(unit, 7206 CMIC_PKT_REASON_0_TYPEr, 7207 i, REASONSf, arg)); 7208 } 7209 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_1_TYPEr); i++) { 7210 BCM_IF_ERROR_RETURN( 7211 _bcm_gh2_rcpu_switch_regall_idx_set(unit, 7212 CMIC_PKT_REASON_1_TYPEr, 7213 i, REASONSf, arg)); 7214 } 7215 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_2_TYPEr); i++) { 7216 BCM_IF_ERROR_RETURN( 7217 _bcm_gh2_rcpu_switch_regall_idx_set(unit, 7218 CMIC_PKT_REASON_2_TYPEr, 7219 i, REASONSf, arg)); 7220 } 7221 return BCM_E_NONE; 7222 } else 7223 #endif 7224 { 7225 return BCM_E_UNAVAIL; 7226 } 7227 break; 7228 case bcmSwitchRxRedirectPktReasons: 7229 if (soc_feature(unit, soc_feature_rcpu_1)) { 7230 #ifdef BCM_CMICM_SUPPORT 7231 uint32 raddr; 7232 int i; 7233 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_0_TYPEr); i++) { 7234 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_0_TYPEr, 7235 REG_PORT_ANY, i); 7236 /* coverity[result_independent_of_operands] */ 7237 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7238 } 7239 return BCM_E_NONE; 7240 } else 7241 #endif 7242 { 7243 return BCM_E_UNAVAIL; 7244 } 7245 break; 7246 case bcmSwitchRxRedirectPktReasonsExtended: 7247 if (soc_feature(unit, soc_feature_rcpu_1)) { 7248 #ifdef BCM_CMICM_SUPPORT 7249 if (soc_feature(unit, soc_feature_cmicm)) { 7250 uint32 raddr; 7251 int i; 7252 7253 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_1_TYPEr); i++) { 7254 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_1_TYPEr, 7255 REG_PORT_ANY, i); 7256 /* coverity[result_independent_of_operands] */ 7257 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7258 } 7259 return BCM_E_NONE; 7260 } 7261 } else 7262 #endif 7263 { 7264 return BCM_E_UNAVAIL; 7265 } 7266 break; 7267 case bcmSwitchRxRedirectHigigPktReasons: 7268 if (soc_feature(unit, soc_feature_rcpu_1)) { 7269 #ifdef BCM_CMICM_SUPPORT 7270 if (soc_feature(unit, soc_feature_cmicm)) { 7271 uint32 raddr; 7272 int i; 7273 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr); i++) { 7274 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, 7275 REG_PORT_ANY, i); 7276 /* coverity[result_independent_of_operands] */ 7277 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7278 } 7279 return BCM_E_NONE; 7280 } 7281 } else 7282 #endif 7283 { 7284 return BCM_E_UNAVAIL; 7285 } 7286 break; 7287 case bcmSwitchRxRedirectHigigPktReasonsExtended: 7288 if (soc_feature(unit, soc_feature_rcpu_1)) { 7289 #ifdef BCM_CMICM_SUPPORT 7290 if (soc_feature(unit, soc_feature_cmicm)) { 7291 uint32 raddr; 7292 int i; 7293 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr); i++) { 7294 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr, 7295 REG_PORT_ANY, i); 7296 /* coverity[result_independent_of_operands] */ 7297 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7298 } 7299 return BCM_E_NONE; 7300 } 7301 }else 7302 #endif 7303 { 7304 return BCM_E_UNAVAIL; 7305 } 7306 break; 7307 case bcmSwitchRxRedirectTruncatedPktReasons: 7308 if (soc_feature(unit, soc_feature_rcpu_1)) { 7309 #ifdef BCM_CMICM_SUPPORT 7310 if (soc_feature(unit, soc_feature_cmicm)){ 7311 uint32 raddr; 7312 int i; 7313 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_MINI_0_TYPEr); i++) { 7314 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_0_TYPEr, 7315 REG_PORT_ANY, i); 7316 /* coverity[result_independent_of_operands] */ 7317 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7318 } 7319 return BCM_E_NONE; 7320 } 7321 }else 7322 #endif 7323 { 7324 return BCM_E_UNAVAIL; 7325 } 7326 break; 7327 case bcmSwitchRxRedirectTruncatedPktReasonsExtended: 7328 if (soc_feature(unit, soc_feature_rcpu_1)) { 7329 #ifdef BCM_CMICM_SUPPORT 7330 if (soc_feature(unit, soc_feature_cmicm)) { 7331 uint32 raddr; 7332 int i; 7333 for (i = 0; i < SOC_REG_NUMELS(unit, CMIC_PKT_REASON_MINI_1_TYPEr); i++) { 7334 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_1_TYPEr, 7335 REG_PORT_ANY, i); 7336 /* coverity[result_independent_of_operands] */ 7337 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7338 } 7339 return BCM_E_NONE; 7340 } 7341 }else 7342 #endif 7343 { 7344 return BCM_E_UNAVAIL; 7345 } 7346 break; 7347 case bcmSwitchRxRedirectPktCos: 7348 #ifdef BCM_CMICM_SUPPORT 7349 if (soc_feature(unit, soc_feature_cmicm) && 7350 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_LOr)) { 7351 uint32 raddr; 7352 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_LOr, 7353 REG_PORT_ANY, 0); 7354 /* coverity[result_independent_of_operands] */ 7355 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7356 return BCM_E_NONE; 7357 } else 7358 #endif 7359 { 7360 return BCM_E_UNAVAIL; 7361 } 7362 break; 7363 case bcmSwitchRxRedirectPktCosExtended: 7364 #ifdef BCM_CMICM_SUPPORT 7365 if (soc_feature(unit, soc_feature_cmicm) && 7366 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_HIr)) { 7367 uint32 raddr; 7368 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_HIr, 7369 REG_PORT_ANY, 0); 7370 /* coverity[result_independent_of_operands] */ 7371 SOC_IF_ERROR_RETURN(soc_pci_write(unit, raddr, arg)); 7372 return BCM_E_NONE; 7373 } else 7374 #endif 7375 { 7376 return BCM_E_UNAVAIL; 7377 } 7378 break; 7379 case bcmSwitchRemoteCpuLocalMacOui: 7380 case bcmSwitchRemoteCpuDestMacOui: 7381 if (soc_feature(unit, soc_feature_rcpu_1)) { 7382 return _bcm_gh2_rcpu_switch_mac_hi_set(unit, type, arg); 7383 } else { 7384 return BCM_E_UNAVAIL; 7385 } 7386 break; 7387 case bcmSwitchRemoteCpuTcMappingMacOui: 7388 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 7389 uint32 fieldval, regval; 7390 BCM_IF_ERROR_RETURN( 7391 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 7392 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 7393 DAf); 7394 fieldval = (arg << 24); 7395 soc_reg_field_set(unit, REMOTE_CPU_DA_LSr, ®val, DAf, fieldval); 7396 BCM_IF_ERROR_RETURN( 7397 WRITE_REMOTE_CPU_DA_LSr(unit, regval)); 7398 BCM_IF_ERROR_RETURN( 7399 READ_REMOTE_CPU_DA_MSr(unit, ®val)); 7400 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_MSr, regval, 7401 DAf); 7402 fieldval = (arg >> 8) & 0xffff; 7403 soc_reg_field_set(unit, REMOTE_CPU_DA_MSr, ®val, DAf, fieldval); 7404 BCM_IF_ERROR_RETURN( 7405 WRITE_REMOTE_CPU_DA_MSr(unit, regval)); 7406 return BCM_E_NONE; 7407 } else { 7408 return BCM_E_UNAVAIL; 7409 } 7410 break; 7411 case bcmSwitchRemoteCpuLocalMacNonOui: 7412 case bcmSwitchRemoteCpuDestMacNonOui: 7413 if (soc_feature(unit, soc_feature_rcpu_1)) { 7414 return _bcm_gh2_rcpu_switch_mac_lo_set(unit, type, arg); 7415 } else { 7416 return BCM_E_UNAVAIL; 7417 } 7418 break; 7419 case bcmSwitchRemoteCpuTcMappingMacNonOui: 7420 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 7421 uint32 fieldval, regval; 7422 BCM_IF_ERROR_RETURN( 7423 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 7424 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 7425 DAf); 7426 fieldval &= 0xff000000; 7427 fieldval |= ((arg << 8) >> 8); 7428 soc_reg_field_set(unit, REMOTE_CPU_DA_LSr, ®val, DAf, fieldval); 7429 BCM_IF_ERROR_RETURN( 7430 WRITE_REMOTE_CPU_DA_LSr(unit, regval)); 7431 return BCM_E_NONE; 7432 } else { 7433 return BCM_E_UNAVAIL; 7434 } 7435 break; 7436 case bcmSwitchRemoteCpuEthertype: 7437 case bcmSwitchRemoteCpuVlan: 7438 case bcmSwitchRemoteCpuTpid: 7439 case bcmSwitchRemoteCpuSignature: 7440 if (soc_feature(unit, soc_feature_rcpu_1)) { 7441 return _bcm_gh2_rcpu_switch_vlan_tpid_sig_set(unit, type, arg); 7442 } else { 7443 return BCM_E_UNAVAIL; 7444 } 7445 break; 7446 case bcmSwitchRemoteCpuTcMappingEthertype: 7447 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 7448 BCM_IF_ERROR_RETURN(WRITE_REMOTE_CPU_LENGTH_TYPEr(unit, arg)); 7449 return BCM_E_NONE; 7450 } else { 7451 return BCM_E_UNAVAIL; 7452 } 7453 break; 7454 case bcmSwitchRemoteCpuDestPort: 7455 if (soc_feature(unit, soc_feature_rcpu_1)) { 7456 return _bcm_gh2_rcpu_pipe_bypass_header_set(unit, type, arg); 7457 } else { 7458 return BCM_E_UNAVAIL; 7459 } 7460 break; 7461 case bcmSwitchRemoteCpuHigigDestPort: 7462 if (soc_feature(unit, soc_feature_rcpu_1)) { 7463 return _bcm_gh2_rcpu_higig_header_set(unit, arg); 7464 } else { 7465 return BCM_E_UNAVAIL; 7466 } 7467 break; 7468 #endif 7469 case bcmSwitchServiceTpidReplace: 7470 case bcmSwitchCongestionCntag: 7471 case bcmSwitchCongestionCntagEthertype: 7472 case bcmSwitchCongestionCnm: 7473 case bcmSwitchCongestionCnmEthertype: 7474 case bcmSwitchCongestionNotificationIdHigh: 7475 case bcmSwitchCongestionNotificationIdQueue: 7476 case bcmSwitchCongestionUseOuterTpid: 7477 case bcmSwitchCongestionUseOuterVlan: 7478 case bcmSwitchCongestionUseOuterPktPri: 7479 case bcmSwitchCongestionUseOuterCfi: 7480 case bcmSwitchCongestionUseInnerPktPri: 7481 case bcmSwitchCongestionUseInnerCfi: 7482 case bcmSwitchCongestionMissingCntag: 7483 case bcmSwitchCongestionCnmSrcMacNonOui: 7484 case bcmSwitchCongestionCnmSrcMacOui: 7485 return BCM_E_UNAVAIL; 7486 break; 7487 case bcmSwitchLoadBalanceHashSelect: 7488 { 7489 soc_reg_t reg; 7490 reg = ING_CONFIG_64r; 7491 return soc_reg_field32_modify(unit, reg, REG_PORT_ANY, 7492 LBID_RTAGf, arg); 7493 } 7494 break; 7495 case bcmSwitchTrillEthertype: 7496 case bcmSwitchTrillISISEthertype: 7497 case bcmSwitchTrillISISDestMacOui: 7498 case bcmSwitchTrillBroadcastDestMacOui: 7499 case bcmSwitchTrillEndStationDestMacOui: 7500 case bcmSwitchTrillISISDestMacNonOui: 7501 case bcmSwitchTrillBroadcastDestMacNonOui: 7502 case bcmSwitchTrillEndStationDestMacNonOui: 7503 case bcmSwitchTrillMinTtl: 7504 case bcmSwitchTrillTtlCheckEnable: 7505 case bcmSwitchFcoeEtherType: 7506 return BCM_E_UNAVAIL; 7507 break; 7508 #if defined(INCLUDE_L3) 7509 case bcmSwitchL3TunnelIpV4ModeOnly: 7510 return soc_tunnel_term_block_size_set (unit, arg); 7511 break; 7512 case bcmSwitchL3SrcHitEnable: 7513 return soc_reg_field32_modify(unit, ING_CONFIG_64r, 7514 REG_PORT_ANY, L3SRC_HIT_ENABLEf, 7515 (uint32)arg); 7516 break; 7517 #endif /* INCLUDE_L3*/ 7518 case bcmSwitchL2DstHitEnable: 7519 return soc_reg_field32_modify(unit, ING_CONFIG_64r, 7520 REG_PORT_ANY, L2DST_HIT_ENABLEf, 7521 (uint32)arg); 7522 break; 7523 case bcmSwitchHashDualMoveDepth: 7524 if (soc_feature(unit, soc_feature_dual_hash)) { 7525 if (arg >= 0) { 7526 SOC_DUAL_HASH_MOVE_MAX(unit) = arg; 7527 return BCM_E_NONE; 7528 } else { 7529 return BCM_E_PARAM; 7530 } 7531 } 7532 return BCM_E_UNAVAIL; 7533 break; 7534 case bcmSwitchHashDualMoveDepthL2: 7535 if (soc_feature(unit, soc_feature_dual_hash)) { 7536 if (arg >= 0) { 7537 SOC_DUAL_HASH_MOVE_MAX_L2X(unit) = arg; 7538 return BCM_E_NONE; 7539 } else { 7540 return BCM_E_PARAM; 7541 } 7542 } 7543 return BCM_E_UNAVAIL; 7544 break; 7545 case bcmSwitchHashDualMoveDepthMpls: 7546 if (soc_feature(unit, soc_feature_dual_hash)) { 7547 if (arg >= 0) { 7548 SOC_DUAL_HASH_MOVE_MAX_MPLS(unit) = arg; 7549 return BCM_E_NONE; 7550 } else { 7551 return BCM_E_PARAM; 7552 } 7553 } 7554 return BCM_E_UNAVAIL; 7555 break; 7556 case bcmSwitchHashDualMoveDepthVlan: 7557 if (soc_feature(unit, soc_feature_dual_hash)) { 7558 if (arg >= 0) { 7559 SOC_DUAL_HASH_MOVE_MAX_VLAN(unit) = arg; 7560 return BCM_E_NONE; 7561 } else { 7562 return BCM_E_PARAM; 7563 } 7564 } 7565 return BCM_E_UNAVAIL; 7566 break; 7567 case bcmSwitchHashDualMoveDepthEgressVlan: 7568 if (soc_feature(unit, soc_feature_dual_hash)) { 7569 if (arg >= 0) { 7570 SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit) = arg; 7571 return BCM_E_NONE; 7572 } else { 7573 return BCM_E_PARAM; 7574 } 7575 } 7576 return BCM_E_UNAVAIL; 7577 break; 7578 case bcmSwitchHashDualMoveDepthWlanPort: 7579 case bcmSwitchHashDualMoveDepthWlanClient: 7580 case bcmSwitchL2GreProtocolType: 7581 case bcmSwitchL2GreVpnIdSizeSet: 7582 case bcmSwitchRemoteEncapsulationMode: 7583 return BCM_E_UNAVAIL; 7584 break; 7585 #if defined(INCLUDE_L3) 7586 case bcmSwitchVxlanUdpDestPortSet: 7587 case bcmSwitchVxlanUdpDestPortSet1: 7588 /* Set UDP Dest port for VXLAN */ 7589 if (soc_feature(unit, soc_feature_vxlan_lite)) { 7590 return bcmi_gh2_vxlan_udp_dest_port_set(unit, type, arg); 7591 } else { 7592 return BCM_E_UNAVAIL; 7593 } 7594 break; 7595 7596 case bcmSwitchVxlanEntropyEnable: 7597 case bcmSwitchVxlanEntropyEnableIP6: 7598 /* Enable UDP Source Port Hash for VXLAN */ 7599 if (soc_feature(unit, soc_feature_vxlan_lite)) { 7600 return bcmi_gh2_vxlan_udp_source_port_set(unit, type, arg); 7601 } else { 7602 return BCM_E_UNAVAIL; 7603 } 7604 break; 7605 case bcmSwitchHashDualMoveDepthL3: 7606 if (soc_feature(unit, soc_feature_dual_hash)) { 7607 if (arg >= 0) { 7608 SOC_DUAL_HASH_MOVE_MAX_L3X(unit) = arg; 7609 return BCM_E_NONE; 7610 } else { 7611 return BCM_E_PARAM; 7612 } 7613 } 7614 return BCM_E_UNAVAIL; 7615 break; 7616 case bcmSwitchHashL3DualLeastFull: 7617 if (soc_feature(unit, soc_feature_dual_hash)) { 7618 if (arg >= 0) { 7619 BCM_IF_ERROR_RETURN 7620 (soc_reg_field32_modify(unit, L3_AUX_HASH_CONTROLr, 7621 REG_PORT_ANY, 7622 INSERT_LEAST_FULL_HALFf, 7623 (arg ? 1 : 0))); 7624 return BCM_E_NONE; 7625 } 7626 } 7627 return BCM_E_UNAVAIL; 7628 break; 7629 #endif 7630 case bcmSwitchHashMultiMoveDepth: 7631 case bcmSwitchHashMultiMoveDepthL2: 7632 case bcmSwitchHashMultiMoveDepthL3: 7633 case bcmSwitchHashMultiMoveDepthMpls: 7634 case bcmSwitchHashMultiMoveDepthVlan: 7635 case bcmSwitchHashMultiMoveDepthEgressVlan: 7636 return BCM_E_UNAVAIL; 7637 break; 7638 case bcmSwitchHashL2DualLeastFull: 7639 if (soc_feature(unit, soc_feature_dual_hash)) { 7640 if (arg >= 0) { 7641 BCM_IF_ERROR_RETURN 7642 (soc_reg_field32_modify(unit, L2_AUX_HASH_CONTROLr, 7643 REG_PORT_ANY, 7644 INSERT_LEAST_FULL_HALFf, 7645 (arg ? 1 : 0))); 7646 return BCM_E_NONE; 7647 } else { 7648 return BCM_E_PARAM; 7649 } 7650 } else { 7651 return BCM_E_UNAVAIL; 7652 } 7653 break; 7654 case bcmSwitchHashMPLSDualLeastFull: 7655 return BCM_E_UNAVAIL; 7656 break; 7657 case bcmSwitchSynchronousPortClockSource: 7658 if (soc_feature(unit, soc_feature_gmii_clkout)) { 7659 return _bcm_gh2_switch_sync_port_select_set(unit, (uint32)arg); 7660 } else { 7661 return BCM_E_UNAVAIL; 7662 } 7663 break; 7664 case bcmSwitchSynchronousPortClockSourceBkup: 7665 if (soc_feature(unit, soc_feature_gmii_clkout)) { 7666 return _bcm_gh2_switch_sync_port_backup_select_set(unit,(uint32)arg); 7667 } else { 7668 return BCM_E_UNAVAIL; 7669 } 7670 break; 7671 7672 case bcmSwitchSynchronousPortClockSourceDivCtrl: 7673 if (soc_feature(unit, soc_feature_gmii_clkout)) { 7674 return _bcm_gh2_switch_div_ctrl_select_set(unit, (uint32)arg); 7675 } else { 7676 return BCM_E_UNAVAIL; 7677 } 7678 break; 7679 7680 case bcmSwitchSynchronousPortClockSourceBkupDivCtrl: 7681 if (soc_feature(unit, soc_feature_gmii_clkout)) { 7682 return _bcm_gh2_switch_div_ctrl_backup_select_set(unit, (uint32)arg); 7683 } else { 7684 return BCM_E_UNAVAIL; 7685 } 7686 break; 7687 #if defined(INCLUDE_L3) 7688 case bcmSwitchNivEthertype: 7689 if (soc_feature(unit, soc_feature_niv)) { 7690 return bcm_gh_niv_ethertype_set(unit, arg); 7691 } 7692 break; 7693 #endif /* INCLUDE_L3 */ 7694 case bcmSwitchSubportPktTagEthertype: 7695 return BCM_E_UNAVAIL; 7696 break; 7697 #if defined(INCLUDE_L3) 7698 case bcmSwitchEtagEthertype: 7699 if (soc_feature(unit, soc_feature_port_extension)) { 7700 return bcm_gh_etag_ethertype_set(unit, arg); 7701 } 7702 return BCM_E_UNAVAIL; 7703 break; 7704 case bcmSwitchExtenderMulticastLowerThreshold: 7705 if (soc_feature(unit, soc_feature_port_extension)) { 7706 BCM_IF_ERROR_RETURN( 7707 soc_reg_field32_modify(unit, ETAG_MULTICAST_RANGEr, 7708 REG_PORT_ANY, 7709 ETAG_VID_MULTICAST_LOWERf, arg)); 7710 return BCM_E_NONE; 7711 } 7712 return BCM_E_UNAVAIL; 7713 break; 7714 case bcmSwitchExtenderMulticastHigherThreshold: 7715 if (soc_feature(unit, soc_feature_port_extension)) { 7716 BCM_IF_ERROR_RETURN( 7717 soc_reg_field32_modify(unit, ETAG_MULTICAST_RANGEr, 7718 REG_PORT_ANY, 7719 ETAG_VID_MULTICAST_UPPERf, arg)); 7720 return BCM_E_NONE; 7721 } 7722 return BCM_E_UNAVAIL; 7723 break; 7724 #endif /* INCLUDE_L3 */ 7725 case bcmSwitchWESPProtocolEnable: 7726 case bcmSwitchWESPProtocol: 7727 case bcmSwitchIp6CompressEnable: 7728 case bcmSwitchIp6CompressDefaultOffset: 7729 return BCM_E_UNAVAIL; 7730 break; 7731 case bcmSwitchMirrorPktChecksEnable: 7732 BCM_IF_ERROR_RETURN 7733 (soc_reg_field32_modify(unit, EGR_CONFIG_1r, REG_PORT_ANY, 7734 DISABLE_MIRROR_CHECKSf, arg ? 0 : 1)); 7735 return BCM_E_NONE; 7736 7737 break; 7738 7739 case bcmSwitchStableSaveLongIds: 7740 #if defined(BCM_FIELD_SUPPORT) && defined(BCM_WARM_BOOT_SUPPORT) 7741 { 7742 _field_control_t *fc; 7743 7744 BCM_IF_ERROR_RETURN(_field_control_get(unit, &fc)); 7745 7746 if (arg) { 7747 fc->flags |= _FP_STABLE_SAVE_LONG_IDS; 7748 } else { 7749 fc->flags &= ~_FP_STABLE_SAVE_LONG_IDS; 7750 } 7751 } 7752 return (BCM_E_NONE); 7753 #else 7754 return (BCM_E_UNAVAIL); 7755 #endif 7756 break; 7757 case bcmSwitchGportAnyDefaultL2Learn: 7758 case bcmSwitchGportAnyDefaultL2Move: 7759 return BCM_E_UNAVAIL; 7760 break; 7761 case bcmSwitchOamCcmToCpu: 7762 if (soc_feature(unit, soc_feature_oam)) { 7763 BCM_IF_ERROR_RETURN 7764 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 7765 REG_PORT_ANY, ERROR_CCM_COPY_TOCPUf, 7766 (arg ? 1 : 0))); 7767 return BCM_E_NONE; 7768 } 7769 return BCM_E_UNAVAIL; 7770 break; 7771 7772 case bcmSwitchOamXconCcmToCpu: 7773 if (soc_feature(unit, soc_feature_oam)) { 7774 BCM_IF_ERROR_RETURN 7775 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 7776 REG_PORT_ANY, XCON_CCM_COPY_TOCPUf, 7777 (arg ? 1 : 0))); 7778 return BCM_E_NONE; 7779 } 7780 return BCM_E_UNAVAIL; 7781 break; 7782 7783 case bcmSwitchOamXconOtherToCpu: 7784 if (soc_feature(unit, soc_feature_oam)) { 7785 BCM_IF_ERROR_RETURN 7786 (soc_reg_field32_modify(unit, CCM_COPYTO_CPU_CONTROLr, 7787 REG_PORT_ANY, XCON_OTHER_COPY_TOCPUf, 7788 (arg ? 1 : 0))); 7789 return BCM_E_NONE; 7790 } 7791 return BCM_E_UNAVAIL; 7792 break; 7793 case bcmSwitchSetMplsEntropyLabelTtl: 7794 case bcmSwitchSetMplsEntropyLabelPri: 7795 case bcmSwitchSetMplsEntropyLabelOffset: 7796 return BCM_E_UNAVAIL; 7797 break; 7798 #if defined(INCLUDE_L3) 7799 case bcmSwitchMultipathCompress: 7800 if (soc_feature(unit, soc_feature_l3) && 7801 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 7802 return bcm_tr2_l3_ecmp_defragment(unit); 7803 } 7804 break; 7805 7806 case bcmSwitchMultipathCompressBuffer: 7807 if (soc_feature(unit, soc_feature_l3) && 7808 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 7809 return bcm_tr2_l3_ecmp_defragment_buffer_set(unit, arg); 7810 } 7811 break; 7812 #endif /* INCLUDE_L3 */ 7813 case bcmSwitchBstEnable: 7814 case bcmSwitchBstTrackingMode: 7815 case bcmSwitchBstSnapshotEnable: 7816 case bcmSwitchFabricTrunkAutoIncludeDisable: 7817 return BCM_E_UNAVAIL; 7818 break; 7819 7820 case bcmSwitchL2OverflowEvent: 7821 if (soc_feature(unit, soc_feature_l2_overflow)) { 7822 if (arg) { 7823 SOC_CONTROL_LOCK(unit); 7824 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 7825 SOC_CONTROL_UNLOCK(unit); 7826 return soc_hr3_l2_overflow_start(unit); 7827 } else { 7828 SOC_CONTROL_LOCK(unit); 7829 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 7830 SOC_CONTROL_UNLOCK(unit); 7831 return soc_hr3_l2_overflow_stop(unit); 7832 } 7833 } else { 7834 return BCM_E_UNAVAIL; 7835 } 7836 break; 7837 case bcmSwitchMiMDefaultSVPValue: 7838 case bcmSwitchOamVersionCheckDisable: 7839 case bcmSwitchOamOlpChipEtherType: 7840 case bcmSwitchOamOlpChipTpid: 7841 case bcmSwitchOamOlpChipVlan: 7842 case bcmSwitchOamOlpStationMacNonOui: 7843 case bcmSwitchOamOlpStationMacOui: 7844 case bcmSwitchOamStackingSupport: 7845 case bcmSwitchFieldStageEgressToCpu: 7846 return BCM_E_UNAVAIL; 7847 break; 7848 case bcmSwitchSystemReservedVlan: 7849 return _bcm_esw_vlan_system_reserved_set(unit, arg); 7850 break; 7851 case bcmSwitchHashOamEgress: 7852 case bcmSwitchHashOamEgressDual: 7853 case bcmSwitchHashOam: 7854 case bcmSwitchHashOamDual: 7855 case bcmSwitchHashOamLeastFull: 7856 case bcmSwitchHashDualMoveDepthOam: 7857 /* Not supported for now */ 7858 case bcmSwitchWredForAllPkts: 7859 case bcmSwitchFcoeNpvModeEnable: 7860 case bcmSwitchFcoeDomainRoutePrefixLength: 7861 case bcmSwitchFcoeCutThroughEnable: 7862 case bcmSwitchFcoeSourceBindCheckAction: 7863 case bcmSwitchFcoeSourceFpmaPrefixCheckAction: 7864 case bcmSwitchFcoeVftHopCountExpiryToCpu: 7865 case bcmSwitchFcoeVftHopCountExpiryAction: 7866 case bcmSwitchFcoeFcEofT1Value: 7867 case bcmSwitchFcoeFcEofT2Value: 7868 case bcmSwitchFcoeFcEofA1Value: 7869 case bcmSwitchFcoeFcEofA2Value: 7870 case bcmSwitchFcoeFcEofN1Value: 7871 case bcmSwitchFcoeFcEofN2Value: 7872 case bcmSwitchFcoeFcEofNI1Value: 7873 case bcmSwitchFcoeFcEofNI2Value: 7874 case bcmSwitchFcoeZoneCheckFailToCpu: 7875 case bcmSwitchFcoeZoneCheckMissDrop: 7876 case bcmSwitchUnknownSubportPktTagToCpu: 7877 case bcmSwitchMirrorUnicastCosq: 7878 case bcmSwitchMirrorMulticastCosq: 7879 return BCM_E_UNAVAIL; 7880 break; 7881 7882 case bcmSwitchEEEQueueThresholdProfile0: 7883 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7884 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_0r, 7885 REG_PORT_ANY, 7886 EEE_QUEUE_THRESHOLDf, 7887 arg); 7888 } 7889 break; 7890 case bcmSwitchEEEQueueThresholdProfile1: 7891 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7892 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_1r, 7893 REG_PORT_ANY, 7894 EEE_QUEUE_THRESHOLDf, 7895 arg); 7896 } 7897 break; 7898 case bcmSwitchEEEQueueThresholdProfile2: 7899 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7900 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_2r, 7901 REG_PORT_ANY, 7902 EEE_QUEUE_THRESHOLDf, 7903 arg); 7904 } 7905 break; 7906 case bcmSwitchEEEQueueThresholdProfile3: 7907 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7908 return soc_reg_field32_modify(unit, EEE_QUEUE_THRESH_3r, 7909 REG_PORT_ANY, 7910 EEE_QUEUE_THRESHOLDf, 7911 arg); 7912 } 7913 break; 7914 case bcmSwitchEEEPacketLatencyProfile0: 7915 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7916 uint32 fval = 0; 7917 fval = arg; 7918 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_0r, 7919 REG_PORT_ANY, 7920 EEE_MAX_PKT_LATENCYf, 7921 fval); 7922 } 7923 break; 7924 case bcmSwitchEEEPacketLatencyProfile1: 7925 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7926 uint32 fval = 0; 7927 fval = arg; 7928 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_1r, 7929 REG_PORT_ANY, 7930 EEE_MAX_PKT_LATENCYf, 7931 fval); 7932 } 7933 break; 7934 case bcmSwitchEEEPacketLatencyProfile2: 7935 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7936 uint32 fval = 0; 7937 fval = arg; 7938 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_2r, 7939 REG_PORT_ANY, 7940 EEE_MAX_PKT_LATENCYf, 7941 fval); 7942 } 7943 break; 7944 case bcmSwitchEEEPacketLatencyProfile3: 7945 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7946 uint32 fval = 0; 7947 fval = arg; 7948 return soc_reg_field32_modify(unit, EEE_MAX_PKT_LAT_3r, 7949 REG_PORT_ANY, 7950 EEE_MAX_PKT_LATENCYf, 7951 fval); 7952 } 7953 break; 7954 case bcmSwitchEEEGlobalCongestionThreshold: 7955 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 7956 return soc_reg_field32_modify(unit, EEE_GLOBAL_BUF_THRESHr, 7957 REG_PORT_ANY, 7958 EEE_GLOBAL_BUFFER_THREHSOLDf, 7959 arg); 7960 } 7961 break; 7962 case bcmSwitchStgInvalidToCpu: 7963 case bcmSwitchVlanTranslateEgressMissToCpu: 7964 case bcmSwitchL3PktErrToCpu: 7965 case bcmSwitchMtuFailureToCpu: 7966 case bcmSwitchSrcKnockoutToCpu: 7967 return BCM_E_UNAVAIL; 7968 break; 7969 case bcmSwitchSymmetricHashControl: 7970 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 7971 return bcm_gh2_switch_rtag7_symmetric_hash_control_set(unit, arg); 7972 } 7973 return BCM_E_UNAVAIL; 7974 break; 7975 case bcmSwitchHigigCongestionClassEnable: 7976 if (soc_feature(unit, soc_feature_ecn_wred)) { 7977 BCM_IF_ERROR_RETURN( 7978 soc_reg_field32_modify(unit, EGR_CONFIG_1r, 7979 REG_PORT_ANY, 7980 HIGIG2_ECN_IN_CC_ENABLEf, 7981 (arg) ? 1 : 0)); 7982 return soc_reg_field32_modify(unit, ING_CONFIG_64r, 7983 REG_PORT_ANY, 7984 HIGIG2_ECN_IN_CC_ENABLEf, 7985 (arg) ? 1 : 0); 7986 } 7987 break; 7988 case bcmSwitchEcnNonIpResponsive: 7989 if (soc_feature(unit, soc_feature_ecn_wred)) { 7990 return soc_reg_field32_modify(unit, ECN_CONTROLr, 7991 REG_PORT_ANY, 7992 RESPONSIVE_DEFAULTf, 7993 (arg) ? 1 : 0); 7994 } 7995 break; 7996 case bcmSwitchEcnNonIpIntCongestionNotification: 7997 if (soc_feature(unit, soc_feature_ecn_wred)) { 7998 uint32 reg_val = 0, responsive; 7999 soc_field_t fld_idx; 8000 BCM_IF_ERROR_RETURN( 8001 READ_ECN_CONTROLr(unit, ®_val)); 8002 responsive = soc_reg_field_get(unit, ECN_CONTROLr, 8003 reg_val, RESPONSIVE_DEFAULTf); 8004 if (responsive) { 8005 fld_idx = RESPONSIVE_DEFAULT_INT_CNf; 8006 } else { 8007 fld_idx = NON_RESPONSIVE_DEFAULT_INT_CNf; 8008 } 8009 return soc_reg_field32_modify(unit, ECN_CONTROLr, 8010 REG_PORT_ANY, 8011 fld_idx, 8012 arg); 8013 } 8014 break; 8015 case bcmSwitchL3RouteCache: 8016 case bcmSwitchL3Max128BV6Entries: 8017 case bcmSwitchECMPLevel1RandomSeed: 8018 case bcmSwitchECMPLevel2RandomSeed: 8019 case bcmSwitchSubportCoEEtherType: 8020 case bcmSwitchSubportEgressTpid: 8021 case bcmSwitchSubportEgressWideTpid: 8022 case bcmSwitchIpmcSameVlanPruningOverride: 8023 case bcmSwitchMimBvidInsertionControl: 8024 return BCM_E_UNAVAIL; 8025 break; 8026 case bcmSwitchL2CpuDeleteEvent: 8027 return _soc_l2mod_sbus_fifo_field_set(unit, L2_MOD_FIFO_ENABLE_L2_DELETEf, arg); 8028 case bcmSwitchL2LearnEvent: 8029 return _soc_l2mod_sbus_fifo_field_set(unit, L2_MOD_FIFO_ENABLE_LEARNf, arg); 8030 case bcmSwitchL2CpuAddEvent: 8031 return _soc_l2mod_sbus_fifo_field_set(unit, L2_MOD_FIFO_ENABLE_L2_INSERTf, arg); 8032 case bcmSwitchL2AgingEvent: 8033 return _soc_l2mod_sbus_fifo_field_set(unit, L2_MOD_FIFO_ENABLE_AGEf, arg); 8034 break; 8035 case bcmSwitchUdfHashEnable: 8036 case bcmSwitchOlpMatchRule: 8037 case bcmSwitchNonUcVlanShapingEnable: 8038 case bcmSwitchRangeCheckersAPIType: 8039 return BCM_E_UNAVAIL; 8040 break; 8041 case bcmSwitchCustomHeaderEncapPriorityOffset: 8042 if (soc_feature(unit, soc_feature_custom_header)) { 8043 /* The offset should be 4-bit aligned */ 8044 if (arg % 4 != 0) { 8045 return BCM_E_PARAM; 8046 } 8047 return soc_reg_field32_modify(unit, 8048 CUSTOM_PACKET_HEADER_OVERRIDEr, 8049 REG_PORT_ANY, 8050 OFFSETf, 8051 arg >> 2); 8052 } 8053 return BCM_E_UNAVAIL; 8054 break; 8055 case bcmSwitchIngCapwapEnable: 8056 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 8057 return soc_reg_field32_modify(unit, CAPWAP_ENABLEr, 8058 REG_PORT_ANY, 8059 ENABLEf, 8060 (arg) ? 1 : 0); 8061 } 8062 return BCM_E_UNAVAIL; 8063 break; 8064 case bcmSwitchCapwapDataUdpDstPort: 8065 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 8066 if ((arg < 0) || (arg > 0xffff)) { 8067 return BCM_E_PARAM; 8068 } 8069 return soc_reg_field32_modify(unit, CAPWAP_ENABLEr, 8070 REG_PORT_ANY, 8071 UDP_PORT_NUMf, 8072 arg); 8073 } 8074 return BCM_E_UNAVAIL; 8075 break; 8076 case bcmSwitchCountCapwapPayloadBytesOnly: 8077 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 8078 return soc_reg_field32_modify(unit, CAPWAP_ENABLEr, 8079 REG_PORT_ANY, 8080 COUNT_PAYLOAD_BYTESf, 8081 (arg) ? 1 : 0); 8082 } 8083 return BCM_E_UNAVAIL; 8084 break; 8085 case bcmSwitchEcmpGroupMemberMode: 8086 return BCM_E_UNAVAIL; 8087 break; 8088 case bcmSwitchECMPHashBitCountSelect: 8089 if (soc_feature(unit, soc_feature_ecmp_hash_bit_count_select)) { 8090 uint32 field_val; 8091 /* 8092 * Determine the number of bits of the 16-bit ECMP hash value: 8093 * 0: used hash bits are 0-9 8094 * 1: used hash bits are 0-10 8095 * 2: used hash bits are 0-11 8096 * 3: used hash bits are 0-12 8097 * 4: used hash bits are 0-13 8098 * 5: used hash bits are 0-14 8099 * 6: All 16 bits are used (defaul) 8100 * 7: Invalid 8101 */ 8102 field_val = (arg & 0x7); 8103 if (field_val == 0x7) { 8104 return BCM_E_PARAM; 8105 } 8106 8107 return soc_reg_field32_modify( 8108 unit, HASH_CONTROLr, REG_PORT_ANY, 8109 ECMP_HASH_FIELD_UPPER_BITS_COUNTf, field_val); 8110 } else { 8111 return BCM_E_UNAVAIL; 8112 } 8113 break; 8114 case bcmSwitchPFCDeadlockDetectionTimeInterval: 8115 case bcmSwitchPFCDeadlockRecoveryAction: 8116 case bcmSwitchSampleFlexRandomSeed: 8117 return BCM_E_UNAVAIL; 8118 break; 8119 case bcmSwitchFlexIP6ExtHdr: 8120 if (soc_feature(unit, soc_feature_l3_ip6) && 8121 SOC_REG_IS_VALID(unit, FLEXIBLE_IPV6_EXT_HDRr)) { 8122 int max_ext_hdr_id; 8123 max_ext_hdr_id = (1 << soc_reg_field_length(unit, 8124 FLEXIBLE_IPV6_EXT_HDRr, PROTOCOL_IDf)) - 1; 8125 if ((arg < 0) || (arg > max_ext_hdr_id)) { 8126 return BCM_E_PARAM; 8127 } 8128 SOC_IF_ERROR_RETURN(WRITE_FLEXIBLE_IPV6_EXT_HDRr(unit, arg)); 8129 return BCM_E_NONE; 8130 } else { 8131 return BCM_E_UNAVAIL; 8132 } 8133 break; 8134 case bcmSwitchFlexIP6ExtHdrEgress: 8135 if (soc_feature(unit, soc_feature_l3_ip6) && 8136 SOC_REG_IS_VALID(unit, EGR_FLEXIBLE_IPV6_EXT_HDRr)) { 8137 int max_egr_ext_hdr_id; 8138 max_egr_ext_hdr_id = (1 << soc_reg_field_length(unit, 8139 EGR_FLEXIBLE_IPV6_EXT_HDRr, PROTOCOL_IDf)) - 1; 8140 if ((arg < 0) || (arg > max_egr_ext_hdr_id)) { 8141 return BCM_E_PARAM; 8142 } 8143 SOC_IF_ERROR_RETURN(WRITE_EGR_FLEXIBLE_IPV6_EXT_HDRr(unit, arg)); 8144 return BCM_E_NONE; 8145 } 8146 break; 8147 case bcmSwitchRedirectBufferThresholdPriorityLow: 8148 case bcmSwitchRedirectBufferThresholdPriorityMedium: 8149 case bcmSwitchRedirectBufferThresholdPriorityHigh: 8150 case bcmSwitchL3ClassIdForL2Enable: 8151 case bcmSwitchAlternateStoreForward: 8152 return BCM_E_UNAVAIL; 8153 break; 8154 case bcmSwitchRoce2UdpDstPort: 8155 if (soc_feature(unit, soc_feature_rroce)) { 8156 uint32 reg32; 8157 8158 if ((arg < 0) || (arg > 0xffff)) { 8159 return BCM_E_PARAM; 8160 } else { 8161 SOC_IF_ERROR_RETURN(READ_ING_ROCE_CONTROLr(unit, ®32)); 8162 if (SOC_REG_FIELD_VALID(unit, ING_ROCE_CONTROLr, 8163 UDP_DST_PORT_NUMBERf)) { 8164 soc_reg_field_set(unit, ING_ROCE_CONTROLr, ®32, 8165 UDP_DST_PORT_NUMBERf, arg); 8166 } 8167 SOC_IF_ERROR_RETURN(WRITE_ING_ROCE_CONTROLr(unit, reg32)); 8168 return BCM_E_NONE; 8169 } 8170 } else { 8171 return BCM_E_UNAVAIL; 8172 } 8173 break; 8174 case bcmSwitchRoce1Ethertype: 8175 if (soc_feature(unit, soc_feature_rroce)) { 8176 uint32 reg32; 8177 /* Ethernet II protocal ethertype valid range */ 8178 if ((arg < 0x600) || (arg > 0xffff)) { 8179 return BCM_E_PARAM; 8180 } else { 8181 SOC_IF_ERROR_RETURN(READ_ING_ROCE_CONTROLr(unit, ®32)); 8182 if (SOC_REG_FIELD_VALID(unit, ING_ROCE_CONTROLr, 8183 ROCEV1_ETHERTYPEf)) { 8184 soc_reg_field_set(unit, ING_ROCE_CONTROLr, ®32, 8185 ROCEV1_ETHERTYPEf, arg); 8186 } 8187 SOC_IF_ERROR_RETURN(WRITE_ING_ROCE_CONTROLr(unit, reg32)); 8188 return BCM_E_NONE; 8189 } 8190 } else { 8191 return BCM_E_UNAVAIL; 8192 } 8193 break; 8194 case bcmSwitchHashSelectControlExtended: 8195 if (soc_feature(unit, soc_feature_rroce)) { 8196 return 8197 bcmi_gh2_switch_rtag7_extended_roce_selectcontrol_set(unit, 8198 arg); 8199 } else { 8200 return BCM_E_UNAVAIL; 8201 } 8202 break; 8203 case bcmSwitchE2EFCReceiveDestMacOui: 8204 if (soc_feature(unit, soc_feature_e2efc)) { 8205 uint32 val, fval; 8206 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_DA_LSr(unit, &val)); 8207 fval = soc_reg_field_get(unit, E2E_IBP_RX_DA_LSr, 8208 val, DAf); 8209 fval = (fval & 0xffffff) | (arg & 0xff) << 24; 8210 soc_reg_field_set(unit, E2E_IBP_RX_DA_LSr, 8211 &val, DAf, fval); 8212 SOC_IF_ERROR_RETURN(WRITE_E2E_IBP_RX_DA_LSr(unit, val)); 8213 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_DA_MSr(unit, &val)); 8214 fval = (arg >> 8) & 0xffff; 8215 soc_reg_field_set(unit, E2E_IBP_RX_DA_MSr, 8216 &val, DAf, fval); 8217 SOC_IF_ERROR_RETURN(WRITE_E2E_IBP_RX_DA_MSr(unit, val)); 8218 return BCM_E_NONE; 8219 } 8220 break; 8221 case bcmSwitchE2EFCReceiveDestMacNonOui: 8222 if (soc_feature(unit, soc_feature_e2efc)) { 8223 uint32 val, fval; 8224 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_DA_LSr(unit, &val)); 8225 fval = soc_reg_field_get(unit, E2E_IBP_RX_DA_LSr, 8226 val, DAf); 8227 fval = (fval & 0xff000000) | (arg & 0xffffff); 8228 soc_reg_field_set(unit, E2E_IBP_RX_DA_LSr, 8229 &val, DAf, fval); 8230 SOC_IF_ERROR_RETURN(WRITE_E2E_IBP_RX_DA_LSr(unit, val)); 8231 return BCM_E_NONE; 8232 } 8233 break; 8234 case bcmSwitchE2EFCReceiveEtherType: 8235 if (soc_feature(unit, soc_feature_e2efc)) { 8236 uint32 val; 8237 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_LENGTH_TYPEr(unit, &val)); 8238 arg = (arg & 0xffff); 8239 soc_reg_field_set(unit, E2E_IBP_RX_LENGTH_TYPEr, 8240 &val, LENGTH_TYPEf, arg); 8241 SOC_IF_ERROR_RETURN(WRITE_E2E_IBP_RX_LENGTH_TYPEr(unit, val)); 8242 return BCM_E_NONE; 8243 } 8244 break; 8245 case bcmSwitchE2EFCReceiveOpcode: 8246 if (soc_feature(unit, soc_feature_e2efc)) { 8247 uint32 val; 8248 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_OPCODEr(unit, &val)); 8249 arg = (arg & 0xffff); 8250 soc_reg_field_set(unit, E2E_IBP_RX_OPCODEr, 8251 &val, OPCODEf, arg); 8252 SOC_IF_ERROR_RETURN(WRITE_E2E_IBP_RX_OPCODEr(unit, val)); 8253 return BCM_E_NONE; 8254 } 8255 break; 8256 default: 8257 break; 8258 } 8259 8260 /* Iterate over all ports for port specific controls */ 8261 found = 0; 8262 8263 PBMP_E_ITER(unit, port) { 8264 if (SOC_IS_STACK_PORT(unit, port)) { 8265 continue; 8266 } 8267 /* coverity[stack_use_callee] */ 8268 /* coverity[stack_use_overflow] */ 8269 rv = bcm_gh2_switch_control_port_set(unit, port, type, arg); 8270 if (rv == BCM_E_NONE) { 8271 found = 1; 8272 } else if (rv != BCM_E_UNAVAIL) { 8273 return rv; 8274 } 8275 } 8276 8277 PBMP_ST_ITER(unit, port) { 8278 if (SOC_IS_STACK_PORT(unit, port) && 8279 (type != bcmSwitchDirectedMirroring)) { 8280 continue; 8281 } 8282 rv = bcm_gh2_switch_control_port_set(unit, port, type, arg); 8283 if (rv == BCM_E_NONE) { 8284 found = 1; 8285 } else if (rv != BCM_E_UNAVAIL) { 8286 return rv; 8287 } 8288 } 8289 8290 return (found ? BCM_E_NONE : BCM_E_UNAVAIL); 8291 } 8292 8293 8294 /* 8295 * Function: 8296 * bcm_gh2_switch_control_get 8297 * Description: 8298 * Retrieve general switch behaviors. 8299 * Parameters: 8300 * unit - Device unit number 8301 * type - The desired configuration parameter to retrieve. 8302 * arg - Pointer to where the retrieved value will be written. 8303 * Returns: 8304 * BCM_E_xxx 8305 * Notes: 8306 * For behaviors which are port-specific, retrieves the setting 8307 * for one port arbitrarily chosen from those which support the 8308 * setting and are non-stack. 8309 */ 8310 8311 int 8312 bcm_gh2_switch_control_get(int unit, 8313 bcm_switch_control_t type, 8314 int *arg) 8315 { 8316 bcm_port_t port; 8317 int rv; 8318 uint32 rval; 8319 uint64 rval64; 8320 8321 if (arg == NULL) { 8322 return BCM_E_PARAM; 8323 } 8324 8325 /* Check for device wide, non port specific controls */ 8326 switch (type) { 8327 case bcmSwitchStableSelect: 8328 #ifdef BCM_WARM_BOOT_SUPPORT 8329 { 8330 uint32 flags; 8331 return soc_stable_get(unit, arg, &flags); 8332 } 8333 #else 8334 return SOC_E_UNAVAIL; 8335 #endif 8336 break; 8337 case bcmSwitchStableSize: 8338 #ifdef BCM_WARM_BOOT_SUPPORT 8339 return soc_stable_size_get(unit, arg); 8340 #else 8341 return SOC_E_UNAVAIL; 8342 #endif 8343 break; 8344 case bcmSwitchStableUsed: 8345 #ifdef BCM_WARM_BOOT_SUPPORT 8346 return soc_stable_used_get(unit, arg); 8347 #else 8348 return SOC_E_UNAVAIL; 8349 #endif 8350 break; 8351 case bcmSwitchControlSync: 8352 #ifdef BCM_WARM_BOOT_SUPPORT 8353 *arg = SOC_CONTROL(unit)->scache_dirty; 8354 return BCM_E_NONE; 8355 #else 8356 return SOC_E_UNAVAIL; 8357 #endif 8358 break; 8359 case bcmSwitchControlAutoSync: 8360 #ifdef BCM_WARM_BOOT_SUPPORT 8361 *arg = SOC_CONTROL(unit)->autosync; 8362 return BCM_E_NONE; 8363 #else 8364 return SOC_E_UNAVAIL; 8365 #endif 8366 break; 8367 case bcmSwitchModuleType: { 8368 bcm_module_t modid; 8369 uint32 mod_type; 8370 8371 BCM_IF_ERROR_RETURN(bcm_esw_stk_my_modid_get(unit, &modid)); 8372 BCM_IF_ERROR_RETURN(_bcm_gh2_switch_module_type_get(unit, modid, 8373 &mod_type)); 8374 *arg = BCM_SWITCH_CONTROL_MOD_TYPE_PACK(modid, mod_type); 8375 return BCM_E_NONE; 8376 } 8377 break; 8378 #ifdef BCM_CB_ABORT_ON_ERR 8379 case bcmSwitchCallbackAbortOnError: 8380 *arg = SOC_CB_ABORT_ON_ERR(unit); 8381 return BCM_E_NONE; 8382 break; 8383 #endif 8384 case bcmSwitchIpmcGroupMtu: 8385 case bcmSwitchLoopbackMtuSize: 8386 return BCM_E_UNAVAIL; 8387 break; 8388 8389 case bcmSwitchMcastFloodDefault: { 8390 bcm_vlan_mcast_flood_t mode; 8391 BCM_IF_ERROR_RETURN(_bcm_esw_vlan_flood_default_get(unit, &mode)); 8392 *arg = mode; 8393 return BCM_E_NONE; 8394 } 8395 break; 8396 8397 case bcmSwitchHgHdrMcastFlood: { 8398 bcm_vlan_mcast_flood_t mode; 8399 BCM_IF_ERROR_RETURN(_bcm_esw_higig_flood_l2_get(unit, &mode)); 8400 *arg = mode; 8401 return BCM_E_NONE; 8402 } 8403 break; 8404 8405 case bcmSwitchHgHdrIpMcastFlood: { 8406 return BCM_E_UNAVAIL; 8407 } 8408 break; 8409 8410 case bcmSwitchUseGport: 8411 *arg = SOC_USE_GPORT(unit); 8412 return BCM_E_NONE; 8413 break; 8414 8415 case bcmSwitchFailoverStackTrunk: 8416 *arg = 1; 8417 return BCM_E_NONE; 8418 break; 8419 8420 case bcmSwitchFailoverEtherTrunk: 8421 *arg = 0; 8422 return BCM_E_NONE; 8423 break; 8424 8425 case bcmSwitchMcastL2Range: 8426 case bcmSwitchMcastL3Range: 8427 return BCM_E_UNAVAIL; 8428 break; 8429 /* coverity[equality_cond] */ 8430 8431 case bcmSwitchHgHdrMcastVlanRange: 8432 case bcmSwitchHgHdrMcastL2Range: 8433 case bcmSwitchHgHdrMcastL3Range: 8434 { 8435 int bc_size, mc_size, ipmc_size; 8436 BCM_IF_ERROR_RETURN 8437 (soc_hbx_higig2_mcast_sizes_get(unit, &bc_size, 8438 &mc_size, &ipmc_size)); 8439 switch (type) { 8440 case bcmSwitchHgHdrMcastVlanRange: 8441 *arg = bc_size; 8442 break; 8443 case bcmSwitchHgHdrMcastL2Range: 8444 *arg = mc_size; 8445 break; 8446 case bcmSwitchHgHdrMcastL3Range: 8447 *arg = ipmc_size; 8448 break; 8449 /* Defensive Default */ 8450 /* coverity[dead_error_begin] */ 8451 default: 8452 return BCM_E_PARAM; 8453 } 8454 } 8455 return BCM_E_NONE; 8456 break; 8457 case bcmSwitchHashSeed0: 8458 rval = 0; 8459 SOC_IF_ERROR_RETURN(READ_RTAG7_HASH_SEED_Ar(unit, &rval)); 8460 *arg = soc_reg_field_get(unit, RTAG7_HASH_SEED_Ar, rval, 8461 HASH_SEED_Af); 8462 return BCM_E_NONE; 8463 break; 8464 case bcmSwitchHashSeed1: 8465 rval = 0; 8466 SOC_IF_ERROR_RETURN(READ_RTAG7_HASH_SEED_Br(unit, &rval)); 8467 *arg = soc_reg_field_get(unit, RTAG7_HASH_SEED_Br, rval, 8468 HASH_SEED_Bf); 8469 return BCM_E_NONE; 8470 break; 8471 case bcmSwitchMacroFlowHashMinOffset: 8472 case bcmSwitchMacroFlowHigigTrunkHashMinOffset: 8473 case bcmSwitchMacroFlowTrunkHashMinOffset: 8474 case bcmSwitchMacroFlowLoadBalanceEntropyHashMinOffset: 8475 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8476 return bcm_gh2_switch_rtag7_macroflow_param_get(unit, type, 8477 NULL, arg, 8478 NULL, NULL, 8479 NULL); 8480 } 8481 return BCM_E_UNAVAIL; 8482 break; 8483 case bcmSwitchMacroFlowHashMaxOffset: 8484 case bcmSwitchMacroFlowHigigTrunkHashMaxOffset: 8485 case bcmSwitchMacroFlowTrunkHashMaxOffset: 8486 case bcmSwitchMacroFlowLoadBalanceEntropyHashMaxOffset: 8487 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8488 return bcm_gh2_switch_rtag7_macroflow_param_get(unit, type, 8489 NULL, NULL, 8490 arg, NULL, 8491 NULL); 8492 } 8493 return BCM_E_UNAVAIL; 8494 break; 8495 case bcmSwitchMacroFlowHashStrideOffset: 8496 case bcmSwitchMacroFlowHigigTrunkHashStrideOffset: 8497 case bcmSwitchMacroFlowTrunkHashStrideOffset: 8498 case bcmSwitchMacroFlowLoadBalanceEntropyHashStrideOffset: 8499 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8500 return bcm_gh2_switch_rtag7_macroflow_param_get(unit, type, 8501 NULL, NULL, 8502 NULL, arg, 8503 NULL); 8504 } 8505 return BCM_E_UNAVAIL; 8506 break; 8507 case bcmSwitchMacroFlowHashOverlayMinOffset: 8508 case bcmSwitchMacroFlowHashOverlayMaxOffset: 8509 case bcmSwitchMacroFlowHashOverlayStrideOffset: 8510 case bcmSwitchMacroFlowEcmpHashOverlayConcatEnable: 8511 return BCM_E_UNAVAIL; 8512 break; 8513 /* RTAG7 Macro Flow Concatenation */ 8514 case bcmSwitchMacroFlowEcmpHashConcatEnable: 8515 case bcmSwitchMacroFlowEcmpUnderlayHashConcatEnable: 8516 case bcmSwitchMacroFlowLoadBalanceHashConcatEnable: 8517 case bcmSwitchMacroFlowTrunkHashConcatEnable: 8518 case bcmSwitchMacroFlowHigigTrunkHashConcatEnable: 8519 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8520 return bcm_gh2_switch_rtag7_macroflow_param_get(unit, type, 8521 NULL, NULL, 8522 NULL, NULL, 8523 arg); 8524 } 8525 return BCM_E_UNAVAIL; 8526 break; 8527 /* RTAG7 Macro Flow Hash Seed */ 8528 case bcmSwitchMacroFlowECMPHashSeed: 8529 case bcmSwitchMacroFlowECMPUnderlayHashSeed: 8530 case bcmSwitchMacroFlowLoadBalanceHashSeed: 8531 case bcmSwitchMacroFlowTrunkHashSeed: 8532 case bcmSwitchMacroFlowHigigTrunkHashSeed: 8533 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8534 return BCM_E_PARAM; 8535 } 8536 return BCM_E_UNAVAIL; 8537 break; 8538 case bcmSwitchMacroFlowECMPOverlayHashSeed: 8539 /* Hash Field select controls */ 8540 case bcmSwitchHashTrillPayloadSelect0: 8541 case bcmSwitchHashTrillPayloadSelect1: 8542 case bcmSwitchHashTrillTunnelSelect0: 8543 case bcmSwitchHashTrillTunnelSelect1: 8544 return BCM_E_UNAVAIL; 8545 break; 8546 case bcmSwitchHashVxlanPayloadSelect0: 8547 case bcmSwitchHashVxlanPayloadSelect1: 8548 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8549 return bcm_gh2_switch_rtag7_field_control_get(unit, type, arg); 8550 } 8551 return BCM_E_UNAVAIL; 8552 break; 8553 case bcmSwitchHashIP6AddrCollapseSelect0: 8554 case bcmSwitchHashIP6AddrCollapseSelect1: 8555 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8556 return bcm_gh2_switch_rtag7_field_control_get(unit, type, arg); 8557 } 8558 return BCM_E_UNAVAIL; 8559 break; 8560 case bcmSwitchHashIP6NextHeaderUseExtensionHeader0: 8561 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8562 COMPILER_64_ZERO(rval64); 8563 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &rval64)); 8564 rval = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, rval64, 8565 DISABLE_HASH_IP_EXTENSION_HEADERS_Af); 8566 if (rval) { 8567 *arg = FALSE; 8568 } else { 8569 *arg = TRUE; 8570 } 8571 return BCM_E_NONE; 8572 } 8573 return BCM_E_UNAVAIL; 8574 break; 8575 case bcmSwitchHashIP6NextHeaderUseExtensionHeader1: 8576 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 8577 COMPILER_64_ZERO(rval64); 8578 BCM_IF_ERROR_RETURN(READ_RTAG7_HASH_CONTROLr(unit, &rval64)); 8579 rval = soc_reg64_field32_get(unit, RTAG7_HASH_CONTROLr, rval64, 8580 DISABLE_HASH_IP_EXTENSION_HEADERS_Bf); 8581 if (rval) { 8582 *arg = FALSE; 8583 } else { 8584 *arg = TRUE; 8585 } 8586 return BCM_E_NONE; 8587 } 8588 return BCM_E_UNAVAIL; 8589 break; 8590 case bcmSwitchHashL2MPLSPayloadSelect0: 8591 case bcmSwitchHashL2MPLSPayloadSelect1: 8592 case bcmSwitchHashIPSecSelect0: 8593 case bcmSwitchHashIPSecSelect1: 8594 case bcmSwitchHashMiMPayloadSelect0: 8595 case bcmSwitchHashMiMPayloadSelect1: 8596 return BCM_E_UNAVAIL; 8597 break; 8598 8599 case bcmSwitchL2McastAllRouterPortsAddEnable: 8600 *arg = SOC_MCAST_ADD_ALL_ROUTER_PORTS(unit); 8601 return BCM_E_NONE; 8602 break; 8603 8604 case bcmSwitchBypassMode: 8605 *arg = SOC_SWITCH_BYPASS_MODE(unit); 8606 return BCM_E_NONE; 8607 break; 8608 8609 case bcmSwitchPFCClass0Queue: 8610 case bcmSwitchPFCClass1Queue: 8611 case bcmSwitchPFCClass2Queue: 8612 case bcmSwitchPFCClass3Queue: 8613 case bcmSwitchPFCClass4Queue: 8614 case bcmSwitchPFCClass5Queue: 8615 case bcmSwitchPFCClass6Queue: 8616 case bcmSwitchPFCClass7Queue: 8617 return BCM_E_UNAVAIL; 8618 break; 8619 8620 case bcmSwitchL2HitClear: 8621 case bcmSwitchL2SrcHitClear: 8622 case bcmSwitchL2DstHitClear: 8623 case bcmSwitchL3HostHitClear: 8624 case bcmSwitchL3RouteHitClear: 8625 return _bcm_gh2_switch_hit_clear_get(unit, type, arg); 8626 break; 8627 8628 /* This swithc control should be supported only per port. */ 8629 case bcmSwitchEncapErrorToCpu: 8630 return BCM_E_UNAVAIL; 8631 break; 8632 8633 case bcmSwitchSnapNonZeroOui: 8634 rval = 0; 8635 8636 COMPILER_64_ZERO(rval64); 8637 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &rval64)); 8638 *arg = soc_reg64_field32_get(unit, ING_CONFIG_64r, rval64, 8639 SNAP_OTHER_DECODE_ENABLEf); 8640 SOC_IF_ERROR_RETURN(READ_EGR_CONFIGr(unit, &rval)); 8641 *arg = soc_reg_field_get(unit, EGR_CONFIGr, rval, 8642 SNAP_OTHER_DECODE_ENABLEf); 8643 return BCM_E_NONE; 8644 break; 8645 8646 case bcmSwitchL2McIdxRetType: 8647 return _bcm_esw_mcast_idx_ret_type_get(unit, arg); 8648 break; 8649 8650 case bcmSwitchL2ExtLearn: 8651 return BCM_E_NONE; 8652 break; 8653 8654 case bcmSwitchL3McIdxRetType: 8655 #ifdef INCLUDE_L3 8656 return _bcm_esw_ipmc_idx_ret_type_get(unit, arg); 8657 #endif 8658 return BCM_E_UNAVAIL; 8659 break; 8660 8661 case bcmSwitchL2SourceDiscardMoveToCpu: 8662 { 8663 soc_reg_t reg; 8664 uint64 regval, f_val; 8665 reg = ING_CONFIG_64r; 8666 8667 BCM_IF_ERROR_RETURN( 8668 soc_reg_get(unit, reg, REG_PORT_ANY, 0, ®val)); 8669 f_val = soc_reg64_field_get(unit, reg, regval, 8670 STNMOVE_ON_L2SRC_DISCf); 8671 COMPILER_64_TO_32_LO(*arg, f_val); 8672 return BCM_E_NONE; 8673 } 8674 break; 8675 8676 case bcmSwitchFabricTrunkDynamicSampleRate: 8677 case bcmSwitchFabricTrunkDynamicEgressBytesExponent: 8678 case bcmSwitchFabricTrunkDynamicQueuedBytesExponent: 8679 case bcmSwitchFabricTrunkDynamicEgressBytesDecreaseReset: 8680 case bcmSwitchFabricTrunkDynamicQueuedBytesDecreaseReset: 8681 case bcmSwitchFabricTrunkDynamicEgressBytesMinThreshold: 8682 case bcmSwitchFabricTrunkDynamicEgressBytesMaxThreshold: 8683 case bcmSwitchFabricTrunkDynamicQueuedBytesMinThreshold: 8684 case bcmSwitchFabricTrunkDynamicQueuedBytesMaxThreshold: 8685 case bcmSwitchTrunkDynamicSampleRate: 8686 case bcmSwitchTrunkDynamicAccountingSelect: 8687 case bcmSwitchTrunkDynamicEgressBytesExponent: 8688 case bcmSwitchTrunkDynamicQueuedBytesExponent: 8689 case bcmSwitchTrunkDynamicEgressBytesDecreaseReset: 8690 case bcmSwitchTrunkDynamicQueuedBytesDecreaseReset: 8691 case bcmSwitchTrunkDynamicEgressBytesMinThreshold: 8692 case bcmSwitchTrunkDynamicEgressBytesMaxThreshold: 8693 case bcmSwitchTrunkDynamicQueuedBytesMinThreshold: 8694 case bcmSwitchTrunkDynamicQueuedBytesMaxThreshold: 8695 case bcmSwitchTrunkDynamicExpectedLoadMinThreshold: 8696 case bcmSwitchTrunkDynamicExpectedLoadMaxThreshold: 8697 case bcmSwitchTrunkDynamicImbalanceMinThreshold: 8698 case bcmSwitchTrunkDynamicImbalanceMaxThreshold: 8699 case bcmSwitchEcmpDynamicSampleRate: 8700 case bcmSwitchEcmpDynamicAccountingSelect: 8701 case bcmSwitchEcmpDynamicEgressBytesExponent: 8702 case bcmSwitchEcmpDynamicQueuedBytesExponent: 8703 case bcmSwitchEcmpDynamicEgressBytesDecreaseReset: 8704 case bcmSwitchEcmpDynamicQueuedBytesDecreaseReset: 8705 case bcmSwitchEcmpDynamicEgressBytesMinThreshold: 8706 case bcmSwitchEcmpDynamicEgressBytesMaxThreshold: 8707 case bcmSwitchEcmpDynamicQueuedBytesMinThreshold: 8708 case bcmSwitchEcmpDynamicQueuedBytesMaxThreshold: 8709 case bcmSwitchEcmpDynamicExpectedLoadMinThreshold: 8710 case bcmSwitchEcmpDynamicExpectedLoadMaxThreshold: 8711 case bcmSwitchEcmpDynamicImbalanceMinThreshold: 8712 case bcmSwitchEcmpDynamicImbalanceMaxThreshold: 8713 return BCM_E_UNAVAIL; 8714 break; 8715 8716 #if (defined(BCM_RCPU_SUPPORT) || defined(BCM_OOB_RCPU_SUPPORT)) && \ 8717 defined(BCM_XGS3_SWITCH_SUPPORT) 8718 case bcmSwitchRemoteCpuSchanEnable: 8719 if (soc_feature(unit, soc_feature_rcpu_1)) { 8720 rval = 0; 8721 8722 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 8723 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 8724 ENABLE_SCHAN_REQUESTf); 8725 return BCM_E_NONE; 8726 } else { 8727 return BCM_E_UNAVAIL; 8728 } 8729 break; 8730 case bcmSwitchRemoteCpuMatchLocalMac: 8731 if (soc_feature(unit, soc_feature_rcpu_1)) { 8732 rval = 0; 8733 8734 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 8735 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 8736 LMAC0_MATCHf); 8737 return BCM_E_NONE; 8738 } else { 8739 return BCM_E_UNAVAIL; 8740 } 8741 break; 8742 case bcmSwitchRemoteCpuFromCpuEnable: 8743 if (soc_feature(unit, soc_feature_rcpu_1)) { 8744 rval = 0; 8745 8746 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 8747 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 8748 ENABLE_FROMCPU_PACKETf); 8749 return BCM_E_NONE; 8750 } else { 8751 return BCM_E_UNAVAIL; 8752 } 8753 break; 8754 case bcmSwitchRemoteCpuToCpuEnable: 8755 if (soc_feature(unit, soc_feature_rcpu_1)) { 8756 rval = 0; 8757 8758 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 8759 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 8760 ENABLE_TOCPU_PACKETf); 8761 return BCM_E_NONE; 8762 } else { 8763 return BCM_E_UNAVAIL; 8764 } 8765 break; 8766 case bcmSwitchRemoteCpuCmicEnable: 8767 #ifdef BCM_CMICM_SUPPORT 8768 if (soc_feature(unit, soc_feature_cmicm)) { 8769 rval = 0; 8770 8771 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 8772 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 8773 ENABLE_CMIC_REQUESTf); 8774 return BCM_E_NONE; 8775 } else 8776 #endif 8777 { 8778 return BCM_E_UNAVAIL; 8779 } 8780 break; 8781 case bcmSwitchRemoteCpuMatchVlan: 8782 if (soc_feature(unit, soc_feature_rcpu_1)) { 8783 rval = 0; 8784 8785 SOC_IF_ERROR_RETURN(READ_CMIC_PKT_CTRLr(unit, &rval)); 8786 *arg = soc_reg_field_get(unit, CMIC_PKT_CTRLr, rval, 8787 VLAN_MATCHf); 8788 return BCM_E_NONE; 8789 } else { 8790 return BCM_E_UNAVAIL; 8791 } 8792 break; 8793 case bcmSwitchRemoteCpuForceScheduling: 8794 if (soc_feature(unit, soc_feature_rcpu_1)) { 8795 int l_arg, h_arg; 8796 8797 l_arg = h_arg = 0; 8798 #ifdef BCM_CMICM_SUPPORT 8799 if (soc_feature(unit, soc_feature_cmicm)) { 8800 if (SOC_REG_IS_VALID(unit, CMIC_PKT_COS_0r)) { 8801 BCM_IF_ERROR_RETURN( 8802 _bcm_gh2_rcpu_switch_regall_get(unit, CMIC_PKT_COS_0r, 8803 &l_arg)); 8804 } 8805 if (SOC_REG_IS_VALID(unit, CMIC_PKT_COS_1r)) { 8806 BCM_IF_ERROR_RETURN( 8807 _bcm_gh2_rcpu_switch_regall_get(unit, CMIC_PKT_COS_1r, &h_arg)); 8808 } 8809 } else 8810 #endif 8811 { 8812 BCM_IF_ERROR_RETURN( 8813 _bcm_gh2_rcpu_switch_regall_get(unit, CMIC_PKT_COSr, &l_arg)); 8814 if (SOC_REG_IS_VALID(unit, CMIC_PKT_COS_HIr)) { 8815 BCM_IF_ERROR_RETURN( 8816 _bcm_gh2_rcpu_switch_regall_get(unit, CMIC_PKT_COS_HIr, &h_arg)); 8817 } 8818 } 8819 *arg = l_arg | h_arg; 8820 8821 return BCM_E_NONE; 8822 } else { 8823 return BCM_E_UNAVAIL; 8824 } 8825 break; 8826 case bcmSwitchRemoteCpuToCpuDestPortAllReasons: 8827 if (soc_feature(unit, soc_feature_rcpu_1)) { 8828 int l_arg, h_arg; 8829 8830 l_arg = h_arg = 0; 8831 #ifdef BCM_CMICM_SUPPORT 8832 if (soc_feature(unit, soc_feature_cmicm)){ 8833 /* In Katana only Index 0 of the reasoning code register is used */ 8834 BCM_IF_ERROR_RETURN( 8835 _bcm_gh2_rcpu_switch_regall_idx_get(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, 0, 8836 &l_arg)); 8837 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr)) { 8838 BCM_IF_ERROR_RETURN( 8839 _bcm_gh2_rcpu_switch_regall_idx_get(unit, 8840 CMIC_PKT_REASON_DIRECT_1_TYPEr, 0, 8841 &h_arg)); 8842 } 8843 } 8844 #endif 8845 *arg = l_arg | h_arg; 8846 return BCM_E_NONE; 8847 } else { 8848 return BCM_E_UNAVAIL; 8849 } 8850 break; 8851 case bcmSwitchRemoteCpuToCpuDestMacAllReasons: 8852 if (soc_feature(unit, soc_feature_rcpu_1)) { 8853 int l_arg, h_arg; 8854 8855 l_arg = h_arg = 0; 8856 #ifdef BCM_CMICM_SUPPORT 8857 if (soc_feature(unit, soc_feature_cmicm)) { 8858 /* In Katana only Index 0 of the reasoning code register is used */ 8859 BCM_IF_ERROR_RETURN( 8860 _bcm_gh2_rcpu_switch_regall_idx_get(unit, CMIC_PKT_REASON_0_TYPEr, 0, 8861 &l_arg)); 8862 if (SOC_REG_IS_VALID(unit, CMIC_PKT_REASON_1_TYPEr)) { 8863 BCM_IF_ERROR_RETURN( 8864 _bcm_gh2_rcpu_switch_regall_idx_get(unit, 8865 CMIC_PKT_REASON_1_TYPEr, 0, &h_arg)); 8866 } 8867 } 8868 #endif 8869 *arg = l_arg | h_arg; 8870 return BCM_E_NONE; 8871 } else { 8872 return BCM_E_UNAVAIL; 8873 } 8874 break; 8875 case bcmSwitchRxRedirectPktReasons: 8876 if (soc_feature(unit, soc_feature_rcpu_1)) { 8877 #ifdef BCM_CMICM_SUPPORT 8878 uint32 raddr; 8879 rval = 0; 8880 if (soc_feature(unit, soc_feature_cmicm)) { 8881 /* Only Idx 0 is used in Katana */ 8882 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_0_TYPEr, REG_PORT_ANY, 0); 8883 /* coverity[result_independent_of_operands] */ 8884 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 8885 } 8886 *arg = rval; 8887 return BCM_E_NONE; 8888 #endif 8889 } else { 8890 return BCM_E_UNAVAIL; 8891 } 8892 break; 8893 case bcmSwitchRxRedirectPktReasonsExtended: 8894 if (soc_feature(unit, soc_feature_rcpu_1)) { 8895 #ifdef BCM_CMICM_SUPPORT 8896 if (soc_feature(unit, soc_feature_cmicm)) { 8897 uint32 raddr; 8898 rval = 0; 8899 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_1_TYPEr, REG_PORT_ANY, 0); 8900 /* coverity[result_independent_of_operands] */ 8901 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 8902 *arg = rval; 8903 return BCM_E_NONE; 8904 } 8905 #endif 8906 } 8907 return BCM_E_UNAVAIL; 8908 break; 8909 case bcmSwitchRxRedirectHigigPktReasons: 8910 if (soc_feature(unit, soc_feature_rcpu_1)) { 8911 #ifdef BCM_CMICM_SUPPORT 8912 uint32 raddr; 8913 rval = 0; 8914 if (soc_feature(unit, soc_feature_cmicm)) { 8915 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_0_TYPEr, REG_PORT_ANY, 0); 8916 /* coverity[result_independent_of_operands] */ 8917 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 8918 } 8919 *arg = rval; 8920 return BCM_E_NONE; 8921 #endif 8922 } else { 8923 return BCM_E_UNAVAIL; 8924 } 8925 break; 8926 case bcmSwitchRxRedirectHigigPktReasonsExtended: 8927 if (soc_feature(unit, soc_feature_rcpu_1)) { 8928 #ifdef BCM_CMICM_SUPPORT 8929 if (soc_feature(unit, soc_feature_cmicm)) { 8930 uint32 raddr; 8931 rval = 0; 8932 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_DIRECT_1_TYPEr, REG_PORT_ANY, 0); 8933 /* coverity[result_independent_of_operands] */ 8934 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 8935 *arg = rval; 8936 return BCM_E_NONE; 8937 } 8938 #endif 8939 } 8940 return BCM_E_UNAVAIL; 8941 break; 8942 case bcmSwitchRxRedirectTruncatedPktReasons: 8943 if (soc_feature(unit, soc_feature_rcpu_1)) { 8944 #ifdef BCM_CMICM_SUPPORT 8945 uint32 raddr; 8946 rval = 0; 8947 if (soc_feature(unit, soc_feature_cmicm)) { 8948 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_0_TYPEr, REG_PORT_ANY, 0); 8949 /* coverity[result_independent_of_operands] */ 8950 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 8951 } 8952 *arg = rval; 8953 return BCM_E_NONE; 8954 #endif 8955 } else { 8956 return BCM_E_UNAVAIL; 8957 } 8958 break; 8959 case bcmSwitchRxRedirectTruncatedPktReasonsExtended: 8960 if (soc_feature(unit, soc_feature_rcpu_1)) { 8961 #ifdef BCM_CMICM_SUPPORT 8962 if (soc_feature(unit, soc_feature_cmicm)) { 8963 uint32 raddr; 8964 rval = 0; 8965 raddr = soc_reg_addr(unit, CMIC_PKT_REASON_MINI_1_TYPEr, REG_PORT_ANY, 0); 8966 /* coverity[result_independent_of_operands] */ 8967 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 8968 *arg = rval; 8969 return BCM_E_NONE; 8970 } 8971 #endif 8972 } 8973 return BCM_E_UNAVAIL; 8974 break; 8975 case bcmSwitchRxRedirectPktCos: 8976 #ifdef BCM_CMICM_SUPPORT 8977 if (soc_feature(unit, soc_feature_cmicm) && 8978 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_LOr)) { 8979 uint32 raddr; 8980 rval = 0; 8981 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_LOr, REG_PORT_ANY, 0); 8982 /* coverity[result_independent_of_operands] */ 8983 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 8984 *arg = rval; 8985 return BCM_E_NONE; 8986 } else 8987 #endif 8988 { 8989 return BCM_E_UNAVAIL; 8990 } 8991 break; 8992 case bcmSwitchRxRedirectPktCosExtended: 8993 #ifdef BCM_CMICM_SUPPORT 8994 if (soc_feature(unit, soc_feature_cmicm) && 8995 SOC_REG_IS_VALID(unit, CMIC_PKT_COS_QUEUES_HIr)) { 8996 uint32 raddr; 8997 rval = 0; 8998 raddr = soc_reg_addr(unit, CMIC_PKT_COS_QUEUES_HIr, REG_PORT_ANY, 0); 8999 /* coverity[result_independent_of_operands] */ 9000 SOC_IF_ERROR_RETURN(soc_pci_getreg(unit, raddr, &rval)); 9001 *arg = rval; 9002 return BCM_E_NONE; 9003 } else 9004 #endif 9005 { 9006 return BCM_E_UNAVAIL; 9007 } 9008 break; 9009 case bcmSwitchRemoteCpuLocalMacOui: 9010 case bcmSwitchRemoteCpuDestMacOui: 9011 if (soc_feature(unit, soc_feature_rcpu_1)) { 9012 return _bcm_gh2_rcpu_switch_mac_hi_get(unit, type, arg); 9013 } else { 9014 return BCM_E_UNAVAIL; 9015 } 9016 break; 9017 case bcmSwitchRemoteCpuTcMappingMacOui: 9018 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 9019 uint32 fieldval, regval; 9020 BCM_IF_ERROR_RETURN( 9021 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 9022 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 9023 DAf); 9024 *arg = fieldval >> 24; 9025 BCM_IF_ERROR_RETURN( 9026 READ_REMOTE_CPU_DA_MSr(unit, ®val)); 9027 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_MSr, regval, 9028 DAf); 9029 *arg |= (fieldval << 8 ); 9030 return BCM_E_NONE; 9031 } else { 9032 return BCM_E_UNAVAIL; 9033 } 9034 break; 9035 case bcmSwitchRemoteCpuLocalMacNonOui: 9036 case bcmSwitchRemoteCpuDestMacNonOui: 9037 if (soc_feature(unit, soc_feature_rcpu_1)) { 9038 return _bcm_gh2_rcpu_switch_mac_lo_get(unit, type, arg); 9039 } else { 9040 return BCM_E_UNAVAIL; 9041 } 9042 break; 9043 case bcmSwitchRemoteCpuTcMappingMacNonOui: 9044 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 9045 uint32 fieldval, regval; 9046 BCM_IF_ERROR_RETURN( 9047 READ_REMOTE_CPU_DA_LSr(unit, ®val)); 9048 fieldval = soc_reg_field_get(unit, REMOTE_CPU_DA_LSr, regval, 9049 DAf); 9050 *arg = ((fieldval << 8) >> 8); 9051 return BCM_E_NONE; 9052 } else { 9053 return BCM_E_UNAVAIL; 9054 } 9055 break; 9056 case bcmSwitchRemoteCpuEthertype: 9057 case bcmSwitchRemoteCpuVlan: 9058 case bcmSwitchRemoteCpuTpid: 9059 case bcmSwitchRemoteCpuSignature: 9060 if (soc_feature(unit, soc_feature_rcpu_1)) { 9061 return _bcm_gh2_rcpu_switch_vlan_tpid_sig_get(unit, type, arg); 9062 } else { 9063 return BCM_E_UNAVAIL; 9064 } 9065 break; 9066 case bcmSwitchRemoteCpuTcMappingEthertype: 9067 if (soc_feature(unit, soc_feature_rcpu_tc_mapping)) { 9068 uint32 regval; 9069 BCM_IF_ERROR_RETURN( 9070 READ_REMOTE_CPU_LENGTH_TYPEr(unit, ®val)); 9071 *arg = soc_reg_field_get(unit, REMOTE_CPU_LENGTH_TYPEr, regval, 9072 LENGTH_TYPEf); 9073 return BCM_E_NONE; 9074 } else { 9075 return BCM_E_UNAVAIL; 9076 } 9077 break; 9078 case bcmSwitchRemoteCpuDestPort: 9079 if (soc_feature(unit, soc_feature_rcpu_1)) { 9080 return _bcm_gh2_rcpu_pipe_bypass_header_get(unit, type, arg); 9081 } else { 9082 return BCM_E_UNAVAIL; 9083 } 9084 break; 9085 case bcmSwitchRemoteCpuHigigDestPort: 9086 if (soc_feature(unit, soc_feature_rcpu_1)) { 9087 return _bcm_gh2_rcpu_higig_header_get(unit, arg); 9088 } else { 9089 return BCM_E_UNAVAIL; 9090 } 9091 break; 9092 #endif 9093 case bcmSwitchServiceTpidReplace: 9094 return BCM_E_UNAVAIL; 9095 break; 9096 9097 case bcmSwitchCongestionCntag: 9098 case bcmSwitchCongestionCntagEthertype: 9099 case bcmSwitchCongestionCnm: 9100 case bcmSwitchCongestionCnmEthertype: 9101 case bcmSwitchCongestionNotificationIdHigh: 9102 case bcmSwitchCongestionNotificationIdQueue: 9103 case bcmSwitchCongestionUseOuterTpid: 9104 case bcmSwitchCongestionUseOuterVlan: 9105 case bcmSwitchCongestionUseOuterPktPri: 9106 case bcmSwitchCongestionUseOuterCfi: 9107 case bcmSwitchCongestionUseInnerPktPri: 9108 case bcmSwitchCongestionUseInnerCfi: 9109 case bcmSwitchCongestionMissingCntag: 9110 case bcmSwitchCongestionCnmSrcMacNonOui: 9111 case bcmSwitchCongestionCnmSrcMacOui: 9112 return BCM_E_UNAVAIL; 9113 break; 9114 9115 case bcmSwitchLoadBalanceHashSelect: 9116 { 9117 soc_reg_t reg; 9118 9119 COMPILER_64_ZERO(rval64); 9120 reg = ING_CONFIG_64r; 9121 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, 9122 &rval64)); 9123 *arg = soc_reg64_field32_get(unit, reg, rval64, LBID_RTAGf); 9124 return BCM_E_NONE; 9125 } 9126 break; 9127 9128 case bcmSwitchTrillEthertype: 9129 case bcmSwitchTrillISISEthertype: 9130 case bcmSwitchTrillISISDestMacOui: 9131 case bcmSwitchTrillBroadcastDestMacOui: 9132 case bcmSwitchTrillEndStationDestMacOui: 9133 case bcmSwitchTrillISISDestMacNonOui: 9134 case bcmSwitchTrillBroadcastDestMacNonOui: 9135 case bcmSwitchTrillEndStationDestMacNonOui: 9136 case bcmSwitchTrillMinTtl: 9137 case bcmSwitchTrillTtlCheckEnable: 9138 case bcmSwitchFcoeEtherType: 9139 return BCM_E_UNAVAIL; 9140 break; 9141 9142 #if defined(BCM_FIREBOLT_SUPPORT) 9143 #if defined(INCLUDE_L3) 9144 case bcmSwitchL3TunnelIpV4ModeOnly: 9145 return soc_tunnel_term_block_size_get (unit, arg); 9146 break; 9147 case bcmSwitchL3SrcHitEnable: 9148 { 9149 soc_reg_t reg; 9150 9151 COMPILER_64_ZERO(rval64); 9152 reg = ING_CONFIG_64r; 9153 9154 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &rval64)); 9155 *arg = soc_reg64_field32_get(unit, reg, rval64, L3SRC_HIT_ENABLEf); 9156 return BCM_E_NONE; 9157 } 9158 break; 9159 #endif /* INCLUDE_L3*/ 9160 #endif /* BCM_FIREBOLT_SUPPORT */ 9161 case bcmSwitchL2DstHitEnable: 9162 { 9163 soc_reg_t reg; 9164 9165 COMPILER_64_ZERO(rval64); 9166 reg = ING_CONFIG_64r; 9167 9168 BCM_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &rval64)); 9169 *arg = soc_reg64_field32_get(unit, reg, rval64, L2DST_HIT_ENABLEf); 9170 return BCM_E_NONE; 9171 } 9172 break; 9173 case bcmSwitchHashDualMoveDepth: 9174 if (soc_feature(unit, soc_feature_dual_hash)) { 9175 *arg = SOC_DUAL_HASH_MOVE_MAX(unit); 9176 return BCM_E_NONE; 9177 } 9178 return BCM_E_UNAVAIL; 9179 break; 9180 case bcmSwitchHashDualMoveDepthL2: 9181 if (soc_feature(unit, soc_feature_dual_hash)) { 9182 *arg = SOC_DUAL_HASH_MOVE_MAX_L2X(unit); 9183 return BCM_E_NONE; 9184 } 9185 return BCM_E_UNAVAIL; 9186 break; 9187 case bcmSwitchHashDualMoveDepthMpls: 9188 if (soc_feature(unit, soc_feature_dual_hash)) { 9189 *arg = SOC_DUAL_HASH_MOVE_MAX_MPLS(unit); 9190 return BCM_E_NONE; 9191 } 9192 return BCM_E_UNAVAIL; 9193 break; 9194 case bcmSwitchHashDualMoveDepthVlan: 9195 if (soc_feature(unit, soc_feature_dual_hash)) { 9196 *arg = SOC_DUAL_HASH_MOVE_MAX_VLAN(unit); 9197 return BCM_E_NONE; 9198 } 9199 return BCM_E_UNAVAIL; 9200 case bcmSwitchHashDualMoveDepthEgressVlan: 9201 if (soc_feature(unit, soc_feature_dual_hash)) { 9202 *arg = SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit); 9203 return BCM_E_NONE; 9204 } 9205 return BCM_E_UNAVAIL; 9206 break; 9207 9208 case bcmSwitchHashDualMoveDepthWlanPort: 9209 case bcmSwitchHashDualMoveDepthWlanClient: 9210 case bcmSwitchL2GreProtocolType: 9211 case bcmSwitchL2GreVpnIdSizeSet: 9212 case bcmSwitchRemoteEncapsulationMode: 9213 return BCM_E_UNAVAIL; 9214 break; 9215 #if defined(INCLUDE_L3) 9216 case bcmSwitchVxlanUdpDestPortSet: 9217 case bcmSwitchVxlanUdpDestPortSet1: 9218 /* Get UDP Dest port for VXLAN */ 9219 if (soc_feature(unit, soc_feature_vxlan_lite)) { 9220 return bcmi_gh2_vxlan_udp_dest_port_get(unit, type, arg); 9221 } else { 9222 return BCM_E_UNAVAIL; 9223 } 9224 break; 9225 9226 case bcmSwitchVxlanEntropyEnable: 9227 case bcmSwitchVxlanEntropyEnableIP6: 9228 /* Enable UDP Source Port Hash for VXLAN */ 9229 if (soc_feature(unit, soc_feature_vxlan_lite)) { 9230 return bcmi_gh2_vxlan_udp_source_port_get(unit, type, arg); 9231 } else { 9232 return BCM_E_UNAVAIL; 9233 } 9234 break; 9235 case bcmSwitchHashDualMoveDepthL3: 9236 if (soc_feature(unit, soc_feature_dual_hash)) { 9237 *arg = SOC_DUAL_HASH_MOVE_MAX_L3X(unit); 9238 return BCM_E_NONE; 9239 } 9240 return BCM_E_UNAVAIL; 9241 break; 9242 case bcmSwitchHashL3DualLeastFull: 9243 if (soc_feature(unit, soc_feature_dual_hash)) { 9244 rval = 0; 9245 BCM_IF_ERROR_RETURN(READ_L3_AUX_HASH_CONTROLr(unit, &rval)); 9246 *arg = soc_reg_field_get(unit, L3_AUX_HASH_CONTROLr, 9247 rval, INSERT_LEAST_FULL_HALFf); 9248 return BCM_E_NONE; 9249 } 9250 return BCM_E_UNAVAIL; 9251 break; 9252 #endif 9253 case bcmSwitchHashMultiMoveDepth: 9254 case bcmSwitchHashMultiMoveDepthL2: 9255 case bcmSwitchHashMultiMoveDepthL3: 9256 case bcmSwitchHashMultiMoveDepthMpls: 9257 case bcmSwitchHashMultiMoveDepthVlan: 9258 case bcmSwitchHashMultiMoveDepthEgressVlan: 9259 return BCM_E_UNAVAIL; 9260 break; 9261 9262 case bcmSwitchHashL2DualLeastFull: 9263 if (soc_feature(unit, soc_feature_dual_hash)) { 9264 rval = 0; 9265 BCM_IF_ERROR_RETURN(READ_L2_AUX_HASH_CONTROLr(unit, &rval)); 9266 *arg = soc_reg_field_get(unit, L2_AUX_HASH_CONTROLr, 9267 rval, INSERT_LEAST_FULL_HALFf); 9268 return BCM_E_NONE; 9269 } 9270 return BCM_E_UNAVAIL; 9271 break; 9272 case bcmSwitchHashMPLSDualLeastFull: 9273 return BCM_E_UNAVAIL; 9274 break; 9275 9276 case bcmSwitchSynchronousPortClockSource: 9277 if (soc_feature(unit, soc_feature_gmii_clkout)) { 9278 return _bcm_gh2_switch_sync_port_select_get(unit, 1, (uint32 *)arg); 9279 } else { 9280 return BCM_E_UNAVAIL; 9281 } 9282 break; 9283 9284 case bcmSwitchSynchronousPortClockSourceBkup: 9285 if (soc_feature(unit, soc_feature_gmii_clkout)) { 9286 return _bcm_gh2_switch_sync_port_select_get(unit, 0, (uint32 *)arg); 9287 } else { 9288 return BCM_E_UNAVAIL; 9289 } 9290 break; 9291 9292 case bcmSwitchSynchronousPortClockSourceDivCtrl: 9293 if (soc_feature(unit, soc_feature_gmii_clkout)) { 9294 return _bcm_gh2_switch_div_ctrl_select_get(unit, 1, (uint32 *)arg); 9295 } else { 9296 return BCM_E_UNAVAIL; 9297 } 9298 break; 9299 9300 case bcmSwitchSynchronousPortClockSourceBkupDivCtrl: 9301 if (soc_feature(unit, soc_feature_gmii_clkout)) { 9302 return _bcm_gh2_switch_div_ctrl_select_get(unit, 0, (uint32 *)arg); 9303 } else { 9304 return BCM_E_UNAVAIL; 9305 } 9306 break; 9307 9308 #if defined(INCLUDE_L3) 9309 case bcmSwitchNivEthertype: 9310 if (soc_feature(unit, soc_feature_niv)) { 9311 return bcm_gh_niv_ethertype_get(unit, arg); 9312 } 9313 return BCM_E_UNAVAIL; 9314 break; 9315 #endif /* INCLUDE_L3 */ 9316 case bcmSwitchSubportPktTagEthertype: 9317 return BCM_E_UNAVAIL; 9318 break; 9319 9320 #if defined(INCLUDE_L3) 9321 case bcmSwitchEtagEthertype: 9322 if (soc_feature(unit, soc_feature_port_extension)) { 9323 return bcm_gh_etag_ethertype_get(unit, arg); 9324 } 9325 return BCM_E_UNAVAIL; 9326 break; 9327 case bcmSwitchExtenderMulticastLowerThreshold: 9328 if (soc_feature(unit, soc_feature_port_extension)) { 9329 uint32 etag_range = 0; 9330 SOC_IF_ERROR_RETURN(READ_ETAG_MULTICAST_RANGEr(unit, &etag_range)); 9331 *arg = soc_reg_field_get(unit, ETAG_MULTICAST_RANGEr, etag_range, 9332 ETAG_VID_MULTICAST_LOWERf); 9333 return BCM_E_NONE; 9334 } 9335 return BCM_E_UNAVAIL; 9336 break; 9337 #endif /* INCLUDE_L3 */ 9338 9339 case bcmSwitchExtenderMulticastHigherThreshold: 9340 if (soc_feature(unit, soc_feature_port_extension)) { 9341 uint32 etag_range = 0; 9342 SOC_IF_ERROR_RETURN(READ_ETAG_MULTICAST_RANGEr(unit, &etag_range)); 9343 *arg = soc_reg_field_get(unit, ETAG_MULTICAST_RANGEr, etag_range, 9344 ETAG_VID_MULTICAST_UPPERf); 9345 return BCM_E_NONE; 9346 } 9347 return BCM_E_UNAVAIL; 9348 break; 9349 9350 case bcmSwitchWESPProtocolEnable: 9351 case bcmSwitchWESPProtocol: 9352 case bcmSwitchIp6CompressEnable: 9353 case bcmSwitchIp6CompressDefaultOffset: 9354 return BCM_E_UNAVAIL; 9355 break; 9356 9357 case bcmSwitchMirrorPktChecksEnable: 9358 rval = 0; 9359 BCM_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 9360 if (soc_reg_field_get(unit, EGR_CONFIG_1r, rval, 9361 DISABLE_MIRROR_CHECKSf)) { 9362 *arg = 0; 9363 } else { 9364 *arg = 1; 9365 } 9366 return BCM_E_NONE; 9367 break; 9368 9369 case bcmSwitchStableSaveLongIds: 9370 #if defined(BCM_FIELD_SUPPORT) && defined(BCM_WARM_BOOT_SUPPORT) 9371 { 9372 _field_control_t *fc; 9373 BCM_IF_ERROR_RETURN(_field_control_get(unit, &fc)); 9374 *arg = ((fc->flags & _FP_STABLE_SAVE_LONG_IDS) != 0); 9375 } 9376 return (BCM_E_NONE); 9377 #else 9378 return (BCM_E_UNAVAIL); 9379 #endif 9380 break; 9381 9382 case bcmSwitchGportAnyDefaultL2Learn: 9383 case bcmSwitchGportAnyDefaultL2Move: 9384 case bcmSwitchSetMplsEntropyLabelTtl: 9385 case bcmSwitchSetMplsEntropyLabelPri: 9386 case bcmSwitchSetMplsEntropyLabelOffset: 9387 return BCM_E_UNAVAIL; 9388 break; 9389 9390 #if defined(INCLUDE_L3) 9391 case bcmSwitchMultipathCompress: 9392 if (soc_feature(unit, soc_feature_l3) && 9393 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 9394 *arg = TRUE; 9395 return BCM_E_NONE; 9396 } 9397 break; 9398 9399 case bcmSwitchMultipathCompressBuffer: 9400 if (soc_feature(unit, soc_feature_l3) && 9401 !soc_feature(unit, soc_feature_l3_no_ecmp)) { 9402 return bcm_tr2_l3_ecmp_defragment_buffer_get(unit, arg); 9403 } 9404 break; 9405 #endif /* INCLUDE_L3 */ 9406 9407 case bcmSwitchBstEnable: 9408 case bcmSwitchBstTrackingMode: 9409 case bcmSwitchBstSnapshotEnable: 9410 case bcmSwitchFabricTrunkAutoIncludeDisable: 9411 return BCM_E_UNAVAIL; 9412 break; 9413 9414 case bcmSwitchL2OverflowEvent: 9415 if (soc_feature(unit, soc_feature_l2_overflow)) { 9416 *arg = SOC_CONTROL(unit)->l2_overflow_enable ? 1 : 0; 9417 return BCM_E_NONE; 9418 } 9419 return BCM_E_UNAVAIL; 9420 break; 9421 9422 case bcmSwitchMiMDefaultSVPValue: 9423 return BCM_E_UNAVAIL; 9424 break; 9425 9426 case bcmSwitchOamCcmToCpu: 9427 if (soc_feature(unit, soc_feature_oam)) { 9428 rval = 0; 9429 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 9430 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 9431 ERROR_CCM_COPY_TOCPUf); 9432 return BCM_E_NONE; 9433 } 9434 return BCM_E_UNAVAIL; 9435 break; 9436 9437 case bcmSwitchOamXconCcmToCpu: 9438 if (soc_feature(unit, soc_feature_oam)) { 9439 rval = 0; 9440 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 9441 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 9442 XCON_CCM_COPY_TOCPUf); 9443 return BCM_E_NONE; 9444 } 9445 return BCM_E_UNAVAIL; 9446 break; 9447 case bcmSwitchOamXconOtherToCpu: 9448 if (soc_feature(unit, soc_feature_oam)) { 9449 rval = 0; 9450 SOC_IF_ERROR_RETURN(READ_CCM_COPYTO_CPU_CONTROLr(unit, &rval)); 9451 *arg = soc_reg_field_get(unit, CCM_COPYTO_CPU_CONTROLr, rval, 9452 XCON_OTHER_COPY_TOCPUf); 9453 return BCM_E_NONE; 9454 } 9455 return BCM_E_UNAVAIL; 9456 break; 9457 9458 case bcmSwitchOamVersionCheckDisable: 9459 case bcmSwitchOamOlpChipEtherType: 9460 case bcmSwitchOamOlpChipTpid: 9461 case bcmSwitchOamOlpChipVlan: 9462 case bcmSwitchOamOlpStationMacNonOui: 9463 case bcmSwitchOamOlpStationMacOui: 9464 case bcmSwitchOamStackingSupport: 9465 case bcmSwitchFieldStageEgressToCpu: 9466 return BCM_E_UNAVAIL; 9467 break; 9468 9469 case bcmSwitchSystemReservedVlan: 9470 return _bcm_esw_vlan_system_reserved_get(unit, arg); 9471 9472 case bcmSwitchHashOamEgress: 9473 case bcmSwitchHashOamEgressDual: 9474 case bcmSwitchHashOam: 9475 case bcmSwitchHashOamDual: 9476 case bcmSwitchHashOamLeastFull: 9477 case bcmSwitchHashDualMoveDepthOam: 9478 /* Not supported for now */ 9479 case bcmSwitchWredForAllPkts: 9480 case bcmSwitchFcoeNpvModeEnable: 9481 case bcmSwitchFcoeDomainRoutePrefixLength: 9482 case bcmSwitchFcoeCutThroughEnable: 9483 case bcmSwitchFcoeSourceBindCheckAction: 9484 case bcmSwitchFcoeSourceFpmaPrefixCheckAction: 9485 case bcmSwitchFcoeVftHopCountExpiryToCpu: 9486 case bcmSwitchFcoeVftHopCountExpiryAction: 9487 case bcmSwitchFcoeFcEofT1Value: 9488 case bcmSwitchFcoeFcEofT2Value: 9489 case bcmSwitchFcoeFcEofA1Value: 9490 case bcmSwitchFcoeFcEofA2Value: 9491 case bcmSwitchFcoeFcEofN1Value: 9492 case bcmSwitchFcoeFcEofN2Value: 9493 case bcmSwitchFcoeFcEofNI1Value: 9494 case bcmSwitchFcoeFcEofNI2Value: 9495 case bcmSwitchFcoeZoneCheckFailToCpu: 9496 case bcmSwitchFcoeZoneCheckMissDrop: 9497 case bcmSwitchNetworkGroupDepth: 9498 case bcmSwitchUnknownSubportPktTagToCpu: 9499 case bcmSwitchMirrorUnicastCosq: 9500 case bcmSwitchMirrorMulticastCosq: 9501 case bcmSwitchL3Max128BV6Entries: 9502 return BCM_E_UNAVAIL; 9503 break; 9504 9505 case bcmSwitchEEEQueueThresholdProfile0: 9506 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9507 uint32 rval; 9508 9509 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_0r(unit, &rval)); 9510 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_0r, rval, 9511 EEE_QUEUE_THRESHOLDf); 9512 return BCM_E_NONE; 9513 } 9514 break; 9515 case bcmSwitchEEEQueueThresholdProfile1: 9516 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9517 uint32 rval; 9518 9519 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_1r(unit, &rval)); 9520 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_1r, rval, 9521 EEE_QUEUE_THRESHOLDf); 9522 return BCM_E_NONE; 9523 } 9524 break; 9525 case bcmSwitchEEEQueueThresholdProfile2: 9526 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9527 uint32 rval; 9528 9529 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_2r(unit, &rval)); 9530 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_2r, rval, 9531 EEE_QUEUE_THRESHOLDf); 9532 return BCM_E_NONE; 9533 } 9534 break; 9535 case bcmSwitchEEEQueueThresholdProfile3: 9536 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9537 uint32 rval; 9538 9539 SOC_IF_ERROR_RETURN(READ_EEE_QUEUE_THRESH_3r(unit, &rval)); 9540 *arg = soc_reg_field_get(unit, EEE_QUEUE_THRESH_3r, rval, 9541 EEE_QUEUE_THRESHOLDf); 9542 return BCM_E_NONE; 9543 } 9544 break; 9545 case bcmSwitchEEEPacketLatencyProfile0: 9546 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9547 uint32 rval; 9548 uint32 fval; 9549 9550 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_0r(unit, &rval)); 9551 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_0r, rval, 9552 EEE_MAX_PKT_LATENCYf); 9553 *arg = fval; 9554 return BCM_E_NONE; 9555 } 9556 break; 9557 case bcmSwitchEEEPacketLatencyProfile1: 9558 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9559 uint32 rval; 9560 uint32 fval; 9561 9562 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_1r(unit, &rval)); 9563 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_1r, rval, 9564 EEE_MAX_PKT_LATENCYf); 9565 *arg = fval; 9566 return BCM_E_NONE; 9567 } 9568 break; 9569 case bcmSwitchEEEPacketLatencyProfile2: 9570 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9571 uint32 rval; 9572 uint32 fval; 9573 9574 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_2r(unit, &rval)); 9575 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_2r, rval, 9576 EEE_MAX_PKT_LATENCYf); 9577 *arg = fval; 9578 return BCM_E_NONE; 9579 } 9580 break; 9581 case bcmSwitchEEEPacketLatencyProfile3: 9582 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9583 uint32 rval; 9584 uint32 fval; 9585 9586 SOC_IF_ERROR_RETURN(READ_EEE_MAX_PKT_LAT_3r(unit, &rval)); 9587 fval = soc_reg_field_get(unit, EEE_MAX_PKT_LAT_3r, rval, 9588 EEE_MAX_PKT_LATENCYf); 9589 *arg = fval; 9590 return BCM_E_NONE; 9591 } 9592 break; 9593 case bcmSwitchEEEGlobalCongestionThreshold: 9594 if (soc_feature(unit, soc_feature_eee_bb_mode)) { 9595 uint32 rval; 9596 9597 SOC_IF_ERROR_RETURN(READ_EEE_GLOBAL_BUF_THRESHr(unit, &rval)); 9598 *arg = soc_reg_field_get(unit, EEE_GLOBAL_BUF_THRESHr, rval, 9599 EEE_GLOBAL_BUFFER_THREHSOLDf); 9600 return BCM_E_NONE; 9601 } 9602 break; 9603 9604 case bcmSwitchStgInvalidToCpu: 9605 case bcmSwitchVlanTranslateEgressMissToCpu: 9606 case bcmSwitchL3PktErrToCpu: 9607 case bcmSwitchMtuFailureToCpu: 9608 case bcmSwitchSrcKnockoutToCpu: 9609 return BCM_E_UNAVAIL; 9610 break; 9611 9612 case bcmSwitchSymmetricHashControl: 9613 if (soc_feature(unit, soc_feature_gh2_rtag7)) { 9614 return bcm_gh2_switch_rtag7_symmetric_hash_control_get(unit, arg); 9615 } 9616 return BCM_E_UNAVAIL; 9617 break; 9618 9619 case bcmSwitchHigigCongestionClassEnable: 9620 if (soc_feature(unit, soc_feature_ecn_wred)) { 9621 COMPILER_64_ZERO(rval64); 9622 BCM_IF_ERROR_RETURN( 9623 READ_ING_CONFIG_64r(unit, &rval64)); 9624 *arg = soc_reg64_field32_get(unit, ING_CONFIG_64r, 9625 rval64, HIGIG2_ECN_IN_CC_ENABLEf); 9626 return BCM_E_NONE; 9627 } 9628 break; 9629 case bcmSwitchEcnNonIpResponsive: 9630 if (soc_feature(unit, soc_feature_ecn_wred)) { 9631 BCM_IF_ERROR_RETURN( 9632 READ_ECN_CONTROLr(unit, &rval)); 9633 *arg = soc_reg_field_get(unit, ECN_CONTROLr, 9634 rval, RESPONSIVE_DEFAULTf); 9635 return BCM_E_NONE; 9636 } 9637 break; 9638 case bcmSwitchEcnNonIpIntCongestionNotification: 9639 if (soc_feature(unit, soc_feature_ecn_wred)) { 9640 uint32 responsive; 9641 soc_field_t fld_idx; 9642 BCM_IF_ERROR_RETURN( 9643 READ_ECN_CONTROLr(unit, &rval)); 9644 responsive = soc_reg_field_get(unit, ECN_CONTROLr, 9645 rval, RESPONSIVE_DEFAULTf); 9646 if (responsive) { 9647 fld_idx = RESPONSIVE_DEFAULT_INT_CNf; 9648 } else { 9649 fld_idx = NON_RESPONSIVE_DEFAULT_INT_CNf; 9650 } 9651 *arg = soc_reg_field_get(unit, ECN_CONTROLr, 9652 rval, fld_idx); 9653 return BCM_E_NONE; 9654 } 9655 break; 9656 9657 case bcmSwitchL3RouteCache: 9658 case bcmSwitchECMPLevel1RandomSeed: 9659 case bcmSwitchECMPLevel2RandomSeed: 9660 case bcmSwitchSynchronousPortClockSourceValid: 9661 case bcmSwitchSynchronousPortClockSourceBkupValid: 9662 case bcmSwitchSubportCoEEtherType: 9663 case bcmSwitchSubportEgressTpid: 9664 case bcmSwitchSubportEgressWideTpid: 9665 case bcmSwitchIpmcSameVlanPruningOverride: 9666 case bcmSwitchMimBvidInsertionControl: 9667 return BCM_E_UNAVAIL; 9668 break; 9669 9670 #if defined(BCM_ESW_SUPPORT) && defined(BCM_CMICM_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 9671 case bcmSwitchL2CpuDeleteEvent: 9672 return _soc_l2mod_sbus_fifo_field_get(unit, L2_MOD_FIFO_ENABLE_L2_DELETEf, arg); 9673 break; 9674 9675 case bcmSwitchL2LearnEvent: 9676 return _soc_l2mod_sbus_fifo_field_get(unit, L2_MOD_FIFO_ENABLE_LEARNf, arg); 9677 break; 9678 9679 case bcmSwitchL2CpuAddEvent: 9680 return _soc_l2mod_sbus_fifo_field_get(unit, L2_MOD_FIFO_ENABLE_L2_INSERTf, arg); 9681 break; 9682 9683 case bcmSwitchL2AgingEvent: 9684 return _soc_l2mod_sbus_fifo_field_get(unit, L2_MOD_FIFO_ENABLE_AGEf, arg); 9685 break; 9686 #endif 9687 case bcmSwitchUdfHashEnable: 9688 case bcmSwitchOlpMatchRule: 9689 case bcmSwitchNonUcVlanShapingEnable: 9690 case bcmSwitchRangeCheckersAPIType: 9691 return BCM_E_UNAVAIL; 9692 break; 9693 9694 case bcmSwitchCustomHeaderEncapPriorityOffset: 9695 if (soc_feature(unit, soc_feature_custom_header)) { 9696 uint32 rval; 9697 SOC_IF_ERROR_RETURN 9698 (READ_CUSTOM_PACKET_HEADER_OVERRIDEr(unit, &rval)); 9699 9700 /* The offset is 4-bit aligned */ 9701 *arg = soc_reg_field_get(unit, CUSTOM_PACKET_HEADER_OVERRIDEr, rval, 9702 OFFSETf) * 4; 9703 9704 return BCM_E_NONE; 9705 } 9706 return BCM_E_UNAVAIL; 9707 break; 9708 9709 case bcmSwitchIngCapwapEnable: 9710 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 9711 BCM_IF_ERROR_RETURN( 9712 READ_CAPWAP_ENABLEr(unit, &rval)); 9713 *arg = soc_reg_field_get(unit, CAPWAP_ENABLEr, 9714 rval, ENABLEf); 9715 return BCM_E_NONE; 9716 } 9717 return BCM_E_UNAVAIL; 9718 break; 9719 9720 case bcmSwitchCapwapDataUdpDstPort: 9721 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 9722 BCM_IF_ERROR_RETURN( 9723 READ_CAPWAP_ENABLEr(unit, &rval)); 9724 *arg = soc_reg_field_get(unit, CAPWAP_ENABLEr, 9725 rval, UDP_PORT_NUMf); 9726 return BCM_E_NONE; 9727 } 9728 return BCM_E_UNAVAIL; 9729 break; 9730 9731 case bcmSwitchCountCapwapPayloadBytesOnly: 9732 if (soc_feature(unit, soc_feature_ing_capwap_parser)) { 9733 BCM_IF_ERROR_RETURN( 9734 READ_CAPWAP_ENABLEr(unit, &rval)); 9735 *arg = soc_reg_field_get(unit, CAPWAP_ENABLEr, 9736 rval, COUNT_PAYLOAD_BYTESf); 9737 return BCM_E_NONE; 9738 } 9739 return BCM_E_UNAVAIL; 9740 break; 9741 9742 case bcmSwitchEcmpGroupMemberMode: 9743 return BCM_E_UNAVAIL; 9744 break; 9745 case bcmSwitchECMPHashBitCountSelect: 9746 if (soc_feature(unit, soc_feature_ecmp_hash_bit_count_select)) { 9747 /* 9748 * Determine the number of bits of the 16-bit ECMP hash value: 9749 * 0: used hash bits are 0-9 9750 * 1: used hash bits are 0-10 9751 * 2: used hash bits are 0-11 9752 * 3: used hash bits are 0-12 9753 * 4: used hash bits are 0-13 9754 * 5: used hash bits are 0-14 9755 * 6: All 16 bits are used (defaul) 9756 * 7: Invalid 9757 */ 9758 BCM_IF_ERROR_RETURN( 9759 READ_HASH_CONTROLr(unit, &rval)); 9760 *arg = soc_reg_field_get(unit, HASH_CONTROLr, rval, 9761 ECMP_HASH_FIELD_UPPER_BITS_COUNTf); 9762 9763 return BCM_E_NONE; 9764 } else { 9765 return BCM_E_UNAVAIL; 9766 } 9767 break; 9768 case bcmSwitchPFCDeadlockDetectionTimeInterval: 9769 case bcmSwitchPFCDeadlockRecoveryAction: 9770 case bcmSwitchSampleFlexRandomSeed: 9771 return BCM_E_UNAVAIL; 9772 break; 9773 9774 case bcmSwitchFlexIP6ExtHdr: 9775 if (soc_feature(unit, soc_feature_l3_ip6) && 9776 SOC_REG_IS_VALID(unit, FLEXIBLE_IPV6_EXT_HDRr)) { 9777 uint32 protocol_id; 9778 SOC_IF_ERROR_RETURN 9779 (READ_FLEXIBLE_IPV6_EXT_HDRr(unit, &protocol_id)); 9780 *arg = soc_reg_field_get(unit, FLEXIBLE_IPV6_EXT_HDRr, 9781 protocol_id, PROTOCOL_IDf); 9782 return BCM_E_NONE; 9783 } else { 9784 return BCM_E_UNAVAIL; 9785 } 9786 break; 9787 9788 case bcmSwitchFlexIP6ExtHdrEgress: 9789 if (soc_feature(unit, soc_feature_l3_ip6) && 9790 SOC_REG_IS_VALID(unit, EGR_FLEXIBLE_IPV6_EXT_HDRr)) { 9791 uint32 protocol_id; 9792 SOC_IF_ERROR_RETURN 9793 (READ_EGR_FLEXIBLE_IPV6_EXT_HDRr(unit, &protocol_id)); 9794 *arg = soc_reg_field_get(unit, EGR_FLEXIBLE_IPV6_EXT_HDRr, 9795 protocol_id, PROTOCOL_IDf); 9796 return BCM_E_NONE; 9797 } 9798 break; 9799 9800 #ifdef BCM_EP_REDIRECT_VERSION_2 9801 case bcmSwitchRedirectBufferThresholdPriorityLow: 9802 case bcmSwitchRedirectBufferThresholdPriorityMedium: 9803 case bcmSwitchRedirectBufferThresholdPriorityHigh: 9804 return BCM_E_UNAVAIL; 9805 break; 9806 #endif 9807 case bcmSwitchL3ClassIdForL2Enable: 9808 case bcmSwitchAlternateStoreForward: 9809 return BCM_E_UNAVAIL; 9810 break; 9811 9812 case bcmSwitchRoce2UdpDstPort: 9813 if (soc_feature(unit, soc_feature_rroce)) { 9814 uint32 reg32 = 0; 9815 9816 SOC_IF_ERROR_RETURN(READ_ING_ROCE_CONTROLr(unit, ®32)); 9817 *arg = soc_reg_field_get(unit, ING_ROCE_CONTROLr, 9818 reg32, UDP_DST_PORT_NUMBERf); 9819 return BCM_E_NONE; 9820 } else { 9821 return BCM_E_UNAVAIL; 9822 } 9823 break; 9824 case bcmSwitchRoce1Ethertype: 9825 if (soc_feature(unit, soc_feature_rroce)) { 9826 uint32 reg32 = 0; 9827 9828 SOC_IF_ERROR_RETURN(READ_ING_ROCE_CONTROLr(unit, ®32)); 9829 *arg = soc_reg_field_get(unit, ING_ROCE_CONTROLr, 9830 reg32, ROCEV1_ETHERTYPEf); 9831 return BCM_E_NONE; 9832 } else { 9833 return BCM_E_UNAVAIL; 9834 } 9835 break; 9836 case bcmSwitchHashSelectControlExtended: 9837 if (soc_feature(unit, soc_feature_rroce)) { 9838 return 9839 bcmi_gh2_switch_rtag7_extended_roce_selectcontrol_get(unit, 9840 arg); 9841 } else { 9842 return BCM_E_UNAVAIL; 9843 } 9844 break; 9845 case bcmSwitchE2EFCReceiveDestMacOui: 9846 if (soc_feature(unit, soc_feature_e2efc)) { 9847 uint32 val, f_lo, f_hi; 9848 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_DA_LSr(unit, &val)); 9849 f_lo = soc_reg_field_get(unit, E2E_IBP_RX_DA_LSr, 9850 val, DAf); 9851 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_DA_MSr(unit, &val)); 9852 f_hi = soc_reg_field_get(unit, E2E_IBP_RX_DA_MSr, 9853 val, DAf); 9854 *arg = (f_hi & 0xffff) << 8 | ((f_lo >> 24) & 0xff); 9855 return BCM_E_NONE; 9856 } 9857 break; 9858 case bcmSwitchE2EFCReceiveDestMacNonOui: 9859 if (soc_feature(unit, soc_feature_e2efc)) { 9860 uint32 val, fval; 9861 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_DA_LSr(unit, &val)); 9862 fval = soc_reg_field_get(unit, E2E_IBP_RX_DA_LSr, 9863 val, DAf); 9864 *arg = fval & 0Xffffff; 9865 return BCM_E_NONE; 9866 } 9867 break; 9868 case bcmSwitchE2EFCReceiveEtherType: 9869 if (soc_feature(unit, soc_feature_e2efc)) { 9870 uint32 val, fval; 9871 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_LENGTH_TYPEr(unit, &val)); 9872 fval = soc_reg_field_get(unit, E2E_IBP_RX_LENGTH_TYPEr, 9873 val, LENGTH_TYPEf); 9874 *arg = fval & 0xffff; 9875 return BCM_E_NONE; 9876 } 9877 break; 9878 case bcmSwitchE2EFCReceiveOpcode: 9879 if (soc_feature(unit, soc_feature_e2efc)) { 9880 uint32 val, fval; 9881 SOC_IF_ERROR_RETURN(READ_E2E_IBP_RX_OPCODEr(unit, &val)); 9882 fval = soc_reg_field_get(unit, E2E_IBP_RX_OPCODEr, 9883 val, OPCODEf); 9884 *arg = fval & 0xffff; 9885 return BCM_E_NONE; 9886 } 9887 break; 9888 9889 9890 default: 9891 break; 9892 } 9893 9894 /* Stop on first supported port for port specific controls */ 9895 PBMP_E_ITER(unit, port) { 9896 if (SOC_IS_STACK_PORT(unit, port)) { 9897 continue; 9898 } 9899 rv = bcm_esw_switch_control_port_get(unit, port, type, arg); 9900 if (rv != BCM_E_UNAVAIL) { /* Found one, or real error */ 9901 return rv; 9902 } 9903 } 9904 9905 PBMP_ST_ITER(unit, port) { 9906 if (SOC_IS_STACK_PORT(unit, port)) { 9907 continue; 9908 } 9909 rv = bcm_esw_switch_control_port_get(unit, port, type, arg); 9910 if (rv != BCM_E_UNAVAIL) { /* Found one, or real error */ 9911 return rv; 9912 } 9913 } 9914 9915 return BCM_E_UNAVAIL; 9916 } 9917 9918 /* 9919 * Function: 9920 * _bcm_gh2_switch_init 9921 * Description: 9922 * Initialize switch controls to their different values. 9923 * Parameters: 9924 * unit - Device unit number 9925 * Returns: 9926 * BCM_E_xxx 9927 */ 9928 int 9929 _bcm_gh2_switch_init(int unit) 9930 { 9931 int cos = 0; 9932 #if defined(BCM_XGS3_SWITCH_SUPPORT) 9933 int mod = 0; 9934 #endif 9935 9936 /* Unit validation check */ 9937 if (!SOC_UNIT_VALID(unit)) { 9938 return BCM_E_UNIT; 9939 } 9940 9941 if (SOC_IS_RCPU_ONLY(unit)) { 9942 return BCM_E_NONE; 9943 } 9944 9945 /* Clear encapsulation priority mappings */ 9946 if (soc_feature(unit, soc_feature_rcpu_priority)) { 9947 for (cos = 0; cos < NUM_CPU_COSQ(unit); cos++) { 9948 BCM_IF_ERROR_RETURN( 9949 bcm_esw_switch_rcpu_encap_priority_map_set(unit, 0, cos, 0)); 9950 } 9951 } 9952 9953 /* Egress copy-to-cpu Enable */ 9954 if (soc_feature(unit, soc_feature_field_egress_tocpu)) { 9955 BCM_IF_ERROR_RETURN(bcm_gh2_switch_control_set(unit, 9956 bcmSwitchFieldStageEgressToCpu, EP_COPY_TOCPU_DEFAULT)); 9957 } 9958 9959 /* bcmSwitchModuleType will eventually be deprecated, 9960 * as pre-xgs3 devices are phased out. 9961 * Once deprecated, this switch control default init will be deleted. 9962 */ 9963 #if defined(BCM_XGS3_SWITCH_SUPPORT) 9964 for(mod = 0; mod < SOC_MODID_MAX(unit); mod++) { 9965 BCM_IF_ERROR_RETURN( 9966 bcm_gh2_switch_control_set(unit,bcmSwitchModuleType, 9967 BCM_SWITCH_CONTROL_MOD_TYPE_PACK(mod,BCM_SWITCH_MODULE_XGS3))); 9968 9969 } 9970 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 9971 9972 if (soc_feature(unit, soc_feature_miml) || 9973 soc_feature(unit, soc_feature_custom_header)) { 9974 BCM_IF_ERROR_RETURN(bcm_hr3_switch_encap_init(unit)); 9975 } 9976 9977 #if defined (BCM_WARM_BOOT_SUPPORT) 9978 if (SOC_WARM_BOOT(unit)) { 9979 BCM_IF_ERROR_RETURN(bcmi_gh2_switch_reinit(unit)); 9980 } else { 9981 BCM_IF_ERROR_RETURN(bcmi_gh2_switch_wb_alloc(unit)); 9982 } 9983 #endif /* BCM_WARM_BOOT_SUPPORT */ 9984 9985 return BCM_E_NONE; 9986 } 9987 9988 /* 9989 * Function: 9990 * bcm_esw_switch_temperature_monitor_get 9991 * Purpose: 9992 * There are temperature monitors embedded on the various points of the 9993 * switch chip for the purpose of monitoring the health of the chip. 9994 * This routine retrieves each temperature monitor's current value and 9995 * peak value. The unit is 0.1 celsius degree. 9996 * Parameters: 9997 * unit - (IN) Unit number. 9998 * temperature_max - (IN) max number of entries of the temperature_array. 9999 * temperature_array - (OUT) the buffer array to hold the retrived values. 10000 * temperature_count - (OUT) number of actual entries retrieved. 10001 * Returns: 10002 * BCM_E_xxx 10003 * Notes: 10004 */ 10005 int 10006 bcm_gh2_switch_temperature_monitor_get(int unit, 10007 int temperature_max, 10008 bcm_switch_temperature_monitor_t *temperature_array, 10009 int *temperature_count) 10010 { 10011 int rv; 10012 rv = soc_gh2_temperature_monitor_get(unit, 10013 temperature_max,temperature_array,temperature_count); 10014 10015 return rv; 10016 } 10017 10018 int 10019 bcmi_gh2_switch_chip_info_get(int unit, 10020 bcm_switch_chip_info_t info_type, 10021 int max_size, 10022 void *data_buf, 10023 int *actual_size) 10024 { 10025 int rv = BCM_E_UNAVAIL; 10026 10027 switch(info_type) { 10028 case bcmSwitchChipInfoIcid: 10029 if (data_buf == NULL) { 10030 /* return required buffer size of 32 bytes (256 bits) */ 10031 *actual_size = GH2_ICID_LENGTH_BYTES; 10032 return BCM_E_NONE; 10033 } 10034 10035 if (max_size != GH2_ICID_LENGTH_BYTES) { 10036 LOG_VERBOSE(BSL_LS_BCM_COMMON, 10037 (BSL_META_U(unit, 10038 "unit %d : Incorrect buffer size.\n"), 10039 unit)); 10040 return BCM_E_PARAM; 10041 } 10042 10043 if (soc_icid_default_get(unit, (uint8 *)data_buf, max_size) < 0) { 10044 LOG_ERROR(BSL_LS_BCM_COMMON, 10045 (BSL_META_U(unit, 10046 "unit %d : Cannot read ICID data.\n"), 10047 unit)); 10048 return BCM_E_UNAVAIL; 10049 } 10050 *actual_size = GH2_ICID_LENGTH_BYTES; 10051 rv = BCM_E_NONE; 10052 break; 10053 default: 10054 rv = BCM_E_UNAVAIL; 10055 break; 10056 } 10057 10058 return rv; 10059 } 10060