th3_cambist.h (44524B)
1 /* 2 / * 3 / * 4 / * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 / * 6 / * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 #define TH3_UDF_PIPE0 {th3_udf_pipe0_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE0r} 10 #define TH3_UDF_PIPE1 {th3_udf_pipe1_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE1r} 11 #define TH3_UDF_PIPE2 {th3_udf_pipe2_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE2r} 12 #define TH3_UDF_PIPE3 {th3_udf_pipe3_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE3r} 13 #define TH3_UDF_PIPE4 {th3_udf_pipe4_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE4r} 14 #define TH3_UDF_PIPE5 {th3_udf_pipe5_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE5r} 15 #define TH3_UDF_PIPE6 {th3_udf_pipe6_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE6r} 16 #define TH3_UDF_PIPE7 {th3_udf_pipe7_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE7r} 17 18 #define TH3_CPU_COS_PIPE0 {th3_cpu_cos_pipe0_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE0r} 19 #define TH3_CPU_COS_PIPE1 {th3_cpu_cos_pipe1_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE1r} 20 #define TH3_CPU_COS_PIPE2 {th3_cpu_cos_pipe2_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE2r} 21 #define TH3_CPU_COS_PIPE3 {th3_cpu_cos_pipe3_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE3r} 22 #define TH3_CPU_COS_PIPE4 {th3_cpu_cos_pipe4_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE4r} 23 #define TH3_CPU_COS_PIPE5 {th3_cpu_cos_pipe5_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE5r} 24 #define TH3_CPU_COS_PIPE6 {th3_cpu_cos_pipe6_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE6r} 25 #define TH3_CPU_COS_PIPE7 {th3_cpu_cos_pipe7_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE7r} 26 27 #define TH3_EFP_PIPE0_SLICE0 {th3_efp_pipe0_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE0r} 28 #define TH3_EFP_PIPE1_SLICE0 {th3_efp_pipe1_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE1r} 29 #define TH3_EFP_PIPE2_SLICE0 {th3_efp_pipe2_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE2r} 30 #define TH3_EFP_PIPE3_SLICE0 {th3_efp_pipe3_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE3r} 31 #define TH3_EFP_PIPE4_SLICE0 {th3_efp_pipe4_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE4r} 32 #define TH3_EFP_PIPE5_SLICE0 {th3_efp_pipe5_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE5r} 33 #define TH3_EFP_PIPE6_SLICE0 {th3_efp_pipe6_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE6r} 34 #define TH3_EFP_PIPE7_SLICE0 {th3_efp_pipe7_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE7r} 35 36 #define TH3_EFP_PIPE0_SLICE1 {th3_efp_pipe0_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE0r} 37 #define TH3_EFP_PIPE1_SLICE1 {th3_efp_pipe1_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE1r} 38 #define TH3_EFP_PIPE2_SLICE1 {th3_efp_pipe2_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE2r} 39 #define TH3_EFP_PIPE3_SLICE1 {th3_efp_pipe3_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE3r} 40 #define TH3_EFP_PIPE4_SLICE1 {th3_efp_pipe4_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE4r} 41 #define TH3_EFP_PIPE5_SLICE1 {th3_efp_pipe5_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE5r} 42 #define TH3_EFP_PIPE6_SLICE1 {th3_efp_pipe6_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE6r} 43 #define TH3_EFP_PIPE7_SLICE1 {th3_efp_pipe7_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE7r} 44 45 #define TH3_EFP_PIPE0_SLICE2 {th3_efp_pipe0_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE0r} 46 #define TH3_EFP_PIPE1_SLICE2 {th3_efp_pipe1_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE1r} 47 #define TH3_EFP_PIPE2_SLICE2 {th3_efp_pipe2_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE2r} 48 #define TH3_EFP_PIPE3_SLICE2 {th3_efp_pipe3_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE3r} 49 #define TH3_EFP_PIPE4_SLICE2 {th3_efp_pipe4_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE4r} 50 #define TH3_EFP_PIPE5_SLICE2 {th3_efp_pipe5_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE5r} 51 #define TH3_EFP_PIPE6_SLICE2 {th3_efp_pipe6_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE6r} 52 #define TH3_EFP_PIPE7_SLICE2 {th3_efp_pipe7_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE7r} 53 54 #define TH3_EFP_PIPE0_SLICE3 {th3_efp_pipe0_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE0r} 55 #define TH3_EFP_PIPE1_SLICE3 {th3_efp_pipe1_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE1r} 56 #define TH3_EFP_PIPE2_SLICE3 {th3_efp_pipe2_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE2r} 57 #define TH3_EFP_PIPE3_SLICE3 {th3_efp_pipe3_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE3r} 58 #define TH3_EFP_PIPE4_SLICE3 {th3_efp_pipe4_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE4r} 59 #define TH3_EFP_PIPE5_SLICE3 {th3_efp_pipe5_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE5r} 60 #define TH3_EFP_PIPE6_SLICE3 {th3_efp_pipe6_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE6r} 61 #define TH3_EFP_PIPE7_SLICE3 {th3_efp_pipe7_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE7r} 62 63 64 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0 {th3_exact_match_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r} 65 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1 {th3_exact_match_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r} 66 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2 {th3_exact_match_logical_table_select_pipe2_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2r} 67 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3 {th3_exact_match_logical_table_select_pipe3_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3r} 68 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4 {th3_exact_match_logical_table_select_pipe4_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE4r} 69 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5 {th3_exact_match_logical_table_select_pipe5_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE5r} 70 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6 {th3_exact_match_logical_table_select_pipe6_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE6r} 71 #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7 {th3_exact_match_logical_table_select_pipe7_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE7r} 72 73 #define TH3_IFP_TCAM_POOL0_PIPE0 {th3_ifp_tcam_pool0_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE0r} 74 #define TH3_IFP_TCAM_POOL0_PIPE1 {th3_ifp_tcam_pool0_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE1r} 75 #define TH3_IFP_TCAM_POOL0_PIPE2 {th3_ifp_tcam_pool0_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE2r} 76 #define TH3_IFP_TCAM_POOL0_PIPE3 {th3_ifp_tcam_pool0_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE3r} 77 #define TH3_IFP_TCAM_POOL0_PIPE4 {th3_ifp_tcam_pool0_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE4r} 78 #define TH3_IFP_TCAM_POOL0_PIPE5 {th3_ifp_tcam_pool0_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE5r} 79 #define TH3_IFP_TCAM_POOL0_PIPE6 {th3_ifp_tcam_pool0_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE6r} 80 #define TH3_IFP_TCAM_POOL0_PIPE7 {th3_ifp_tcam_pool0_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE7r} 81 82 #define TH3_IFP_TCAM_POOL1_PIPE0 {th3_ifp_tcam_pool1_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE0r} 83 #define TH3_IFP_TCAM_POOL1_PIPE1 {th3_ifp_tcam_pool1_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE1r} 84 #define TH3_IFP_TCAM_POOL1_PIPE2 {th3_ifp_tcam_pool1_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE2r} 85 #define TH3_IFP_TCAM_POOL1_PIPE3 {th3_ifp_tcam_pool1_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE3r} 86 #define TH3_IFP_TCAM_POOL1_PIPE4 {th3_ifp_tcam_pool1_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE4r} 87 #define TH3_IFP_TCAM_POOL1_PIPE5 {th3_ifp_tcam_pool1_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE5r} 88 #define TH3_IFP_TCAM_POOL1_PIPE6 {th3_ifp_tcam_pool1_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE6r} 89 #define TH3_IFP_TCAM_POOL1_PIPE7 {th3_ifp_tcam_pool1_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE7r} 90 91 #define TH3_IFP_TCAM_POOL2_PIPE0 {th3_ifp_tcam_pool2_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE0r} 92 #define TH3_IFP_TCAM_POOL2_PIPE1 {th3_ifp_tcam_pool2_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE1r} 93 #define TH3_IFP_TCAM_POOL2_PIPE2 {th3_ifp_tcam_pool2_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE2r} 94 #define TH3_IFP_TCAM_POOL2_PIPE3 {th3_ifp_tcam_pool2_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE3r} 95 #define TH3_IFP_TCAM_POOL2_PIPE4 {th3_ifp_tcam_pool2_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE4r} 96 #define TH3_IFP_TCAM_POOL2_PIPE5 {th3_ifp_tcam_pool2_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE5r} 97 #define TH3_IFP_TCAM_POOL2_PIPE6 {th3_ifp_tcam_pool2_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE6r} 98 #define TH3_IFP_TCAM_POOL2_PIPE7 {th3_ifp_tcam_pool2_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE7r} 99 100 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE0 {th3_ifp_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r} 101 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE1 {th3_ifp_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r} 102 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE2 {th3_ifp_logical_table_select_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2r} 103 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE3 {th3_ifp_logical_table_select_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3r} 104 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE4 {th3_ifp_logical_table_select_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE4r} 105 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE5 {th3_ifp_logical_table_select_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE5r} 106 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE6 {th3_ifp_logical_table_select_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE6r} 107 #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE7 {th3_ifp_logical_table_select_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE7r} 108 109 #define TH3_L2_USER_ENTRY_PIPE0 {th3_l2_user_entry_pipe0_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE0r} 110 #define TH3_L2_USER_ENTRY_PIPE1 {th3_l2_user_entry_pipe1_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE1r} 111 #define TH3_L2_USER_ENTRY_PIPE2 {th3_l2_user_entry_pipe2_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE2r} 112 #define TH3_L2_USER_ENTRY_PIPE3 {th3_l2_user_entry_pipe3_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE3r} 113 #define TH3_L2_USER_ENTRY_PIPE4 {th3_l2_user_entry_pipe4_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE4r} 114 #define TH3_L2_USER_ENTRY_PIPE5 {th3_l2_user_entry_pipe5_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE5r} 115 #define TH3_L2_USER_ENTRY_PIPE6 {th3_l2_user_entry_pipe6_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE6r} 116 #define TH3_L2_USER_ENTRY_PIPE7 {th3_l2_user_entry_pipe7_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE7r} 117 118 #define TH3_L3_DEFIP_PIPE0_MODE0 {th3_l3_defip_pipe0_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE0r} 119 #define TH3_L3_DEFIP_PIPE1_MODE0 {th3_l3_defip_pipe1_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE1r} 120 #define TH3_L3_DEFIP_PIPE2_MODE0 {th3_l3_defip_pipe2_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE2r} 121 #define TH3_L3_DEFIP_PIPE3_MODE0 {th3_l3_defip_pipe3_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE3r} 122 #define TH3_L3_DEFIP_PIPE4_MODE0 {th3_l3_defip_pipe4_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE4r} 123 #define TH3_L3_DEFIP_PIPE5_MODE0 {th3_l3_defip_pipe5_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE5r} 124 #define TH3_L3_DEFIP_PIPE6_MODE0 {th3_l3_defip_pipe6_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE6r} 125 #define TH3_L3_DEFIP_PIPE7_MODE0 {th3_l3_defip_pipe7_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE7r} 126 127 #define TH3_L3_DEFIP_PIPE0_MODE1 {th3_l3_defip_pipe0_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE0r} 128 #define TH3_L3_DEFIP_PIPE1_MODE1 {th3_l3_defip_pipe1_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE1r} 129 #define TH3_L3_DEFIP_PIPE2_MODE1 {th3_l3_defip_pipe2_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE2r} 130 #define TH3_L3_DEFIP_PIPE3_MODE1 {th3_l3_defip_pipe3_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE3r} 131 #define TH3_L3_DEFIP_PIPE4_MODE1 {th3_l3_defip_pipe4_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE4r} 132 #define TH3_L3_DEFIP_PIPE5_MODE1 {th3_l3_defip_pipe5_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE5r} 133 #define TH3_L3_DEFIP_PIPE6_MODE1 {th3_l3_defip_pipe6_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE6r} 134 #define TH3_L3_DEFIP_PIPE7_MODE1 {th3_l3_defip_pipe7_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE7r} 135 136 #define TH3_L3_DEFIP_PIPE0_MODE2 {th3_l3_defip_pipe0_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE0r} 137 #define TH3_L3_DEFIP_PIPE1_MODE2 {th3_l3_defip_pipe1_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE1r} 138 #define TH3_L3_DEFIP_PIPE2_MODE2 {th3_l3_defip_pipe2_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE2r} 139 #define TH3_L3_DEFIP_PIPE3_MODE2 {th3_l3_defip_pipe3_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE3r} 140 #define TH3_L3_DEFIP_PIPE4_MODE2 {th3_l3_defip_pipe4_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE4r} 141 #define TH3_L3_DEFIP_PIPE5_MODE2 {th3_l3_defip_pipe5_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE5r} 142 #define TH3_L3_DEFIP_PIPE6_MODE2 {th3_l3_defip_pipe6_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE6r} 143 #define TH3_L3_DEFIP_PIPE7_MODE2 {th3_l3_defip_pipe7_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE7r} 144 145 #define TH3_VFP_PIPE0 {th3_vfp_pipe0_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE0r} 146 #define TH3_VFP_PIPE1 {th3_vfp_pipe1_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE1r} 147 #define TH3_VFP_PIPE2 {th3_vfp_pipe2_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE2r} 148 #define TH3_VFP_PIPE3 {th3_vfp_pipe3_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE3r} 149 #define TH3_VFP_PIPE4 {th3_vfp_pipe4_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE4r} 150 #define TH3_VFP_PIPE5 {th3_vfp_pipe5_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE5r} 151 #define TH3_VFP_PIPE6 {th3_vfp_pipe6_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE6r} 152 #define TH3_VFP_PIPE7 {th3_vfp_pipe7_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE7r} 153 154 #define TH3_TOTAL_CAMBIST_COUNT 128 155 156 #define TH3_DONE_BIT_MASK 0x00000001 157 #define TH3_BIST_SUCCESS_MASK 0x00000002 158 159 static char th3_cpu_cos_pipe0_name[] = "CPU_COS_PIPE0"; 160 static char th3_cpu_cos_pipe1_name[] = "CPU_COS_PIPE1"; 161 static char th3_cpu_cos_pipe2_name[] = "CPU_COS_PIPE2"; 162 static char th3_cpu_cos_pipe3_name[] = "CPU_COS_PIPE3"; 163 static char th3_cpu_cos_pipe4_name[] = "CPU_COS_PIPE4"; 164 static char th3_cpu_cos_pipe5_name[] = "CPU_COS_PIPE5"; 165 static char th3_cpu_cos_pipe6_name[] = "CPU_COS_PIPE6"; 166 static char th3_cpu_cos_pipe7_name[] = "CPU_COS_PIPE7"; 167 static char th3_efp_pipe0_slice0_name[] = "EFP_PIPE0_SLICE0"; 168 static char th3_efp_pipe0_slice1_name[] = "EFP_PIPE0_SLICE1"; 169 static char th3_efp_pipe0_slice2_name[] = "EFP_PIPE0_SLICE2"; 170 static char th3_efp_pipe0_slice3_name[] = "EFP_PIPE0_SLICE3"; 171 static char th3_efp_pipe1_slice0_name[] = "EFP_PIPE1_SLICE0"; 172 static char th3_efp_pipe1_slice1_name[] = "EFP_PIPE1_SLICE1"; 173 static char th3_efp_pipe1_slice2_name[] = "EFP_PIPE1_SLICE2"; 174 static char th3_efp_pipe1_slice3_name[] = "EFP_PIPE1_SLICE3"; 175 static char th3_efp_pipe2_slice0_name[] = "EFP_PIPE2_SLICE0"; 176 static char th3_efp_pipe2_slice1_name[] = "EFP_PIPE2_SLICE1"; 177 static char th3_efp_pipe2_slice2_name[] = "EFP_PIPE2_SLICE2"; 178 static char th3_efp_pipe2_slice3_name[] = "EFP_PIPE2_SLICE3"; 179 static char th3_efp_pipe3_slice0_name[] = "EFP_PIPE3_SLICE0"; 180 static char th3_efp_pipe3_slice1_name[] = "EFP_PIPE3_SLICE1"; 181 static char th3_efp_pipe3_slice2_name[] = "EFP_PIPE3_SLICE2"; 182 static char th3_efp_pipe3_slice3_name[] = "EFP_PIPE3_SLICE3"; 183 static char th3_efp_pipe4_slice0_name[] = "EFP_PIPE4_SLICE0"; 184 static char th3_efp_pipe4_slice1_name[] = "EFP_PIPE4_SLICE1"; 185 static char th3_efp_pipe4_slice2_name[] = "EFP_PIPE4_SLICE2"; 186 static char th3_efp_pipe4_slice3_name[] = "EFP_PIPE4_SLICE3"; 187 static char th3_efp_pipe5_slice0_name[] = "EFP_PIPE5_SLICE0"; 188 static char th3_efp_pipe5_slice1_name[] = "EFP_PIPE5_SLICE1"; 189 static char th3_efp_pipe5_slice2_name[] = "EFP_PIPE5_SLICE2"; 190 static char th3_efp_pipe5_slice3_name[] = "EFP_PIPE5_SLICE3"; 191 static char th3_efp_pipe6_slice0_name[] = "EFP_PIPE6_SLICE0"; 192 static char th3_efp_pipe6_slice1_name[] = "EFP_PIPE6_SLICE1"; 193 static char th3_efp_pipe6_slice2_name[] = "EFP_PIPE6_SLICE2"; 194 static char th3_efp_pipe6_slice3_name[] = "EFP_PIPE6_SLICE3"; 195 static char th3_efp_pipe7_slice0_name[] = "EFP_PIPE7_SLICE0"; 196 static char th3_efp_pipe7_slice1_name[] = "EFP_PIPE7_SLICE1"; 197 static char th3_efp_pipe7_slice2_name[] = "EFP_PIPE7_SLICE2"; 198 static char th3_efp_pipe7_slice3_name[] = "EFP_PIPE7_SLICE3"; 199 static char th3_exact_match_logical_table_select_pipe0_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0"; 200 static char th3_exact_match_logical_table_select_pipe1_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1"; 201 static char th3_exact_match_logical_table_select_pipe2_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2"; 202 static char th3_exact_match_logical_table_select_pipe3_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3"; 203 static char th3_exact_match_logical_table_select_pipe4_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4"; 204 static char th3_exact_match_logical_table_select_pipe5_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5"; 205 static char th3_exact_match_logical_table_select_pipe6_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6"; 206 static char th3_exact_match_logical_table_select_pipe7_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7"; 207 static char th3_ifp_tcam_pool0_pipe0_name[] = "IFP_TCAM_POOL0_PIPE0"; 208 static char th3_ifp_tcam_pool1_pipe0_name[] = "IFP_TCAM_POOL1_PIPE0"; 209 static char th3_ifp_tcam_pool2_pipe0_name[] = "IFP_TCAM_POOL2_PIPE0"; 210 static char th3_ifp_tcam_pool0_pipe1_name[] = "IFP_TCAM_POOL0_PIPE1"; 211 static char th3_ifp_tcam_pool1_pipe1_name[] = "IFP_TCAM_POOL1_PIPE1"; 212 static char th3_ifp_tcam_pool2_pipe1_name[] = "IFP_TCAM_POOL2_PIPE1"; 213 static char th3_ifp_tcam_pool0_pipe2_name[] = "IFP_TCAM_POOL0_PIPE2"; 214 static char th3_ifp_tcam_pool1_pipe2_name[] = "IFP_TCAM_POOL1_PIPE2"; 215 static char th3_ifp_tcam_pool2_pipe2_name[] = "IFP_TCAM_POOL2_PIPE2"; 216 static char th3_ifp_tcam_pool0_pipe3_name[] = "IFP_TCAM_POOL0_PIPE3"; 217 static char th3_ifp_tcam_pool1_pipe3_name[] = "IFP_TCAM_POOL1_PIPE3"; 218 static char th3_ifp_tcam_pool2_pipe3_name[] = "IFP_TCAM_POOL2_PIPE3"; 219 static char th3_ifp_tcam_pool0_pipe4_name[] = "IFP_TCAM_POOL0_PIPE4"; 220 static char th3_ifp_tcam_pool1_pipe4_name[] = "IFP_TCAM_POOL1_PIPE4"; 221 static char th3_ifp_tcam_pool2_pipe4_name[] = "IFP_TCAM_POOL2_PIPE4"; 222 static char th3_ifp_tcam_pool0_pipe5_name[] = "IFP_TCAM_POOL0_PIPE5"; 223 static char th3_ifp_tcam_pool1_pipe5_name[] = "IFP_TCAM_POOL1_PIPE5"; 224 static char th3_ifp_tcam_pool2_pipe5_name[] = "IFP_TCAM_POOL2_PIPE5"; 225 static char th3_ifp_tcam_pool0_pipe6_name[] = "IFP_TCAM_POOL0_PIPE6"; 226 static char th3_ifp_tcam_pool1_pipe6_name[] = "IFP_TCAM_POOL1_PIPE6"; 227 static char th3_ifp_tcam_pool2_pipe6_name[] = "IFP_TCAM_POOL2_PIPE6"; 228 static char th3_ifp_tcam_pool0_pipe7_name[] = "IFP_TCAM_POOL0_PIPE7"; 229 static char th3_ifp_tcam_pool1_pipe7_name[] = "IFP_TCAM_POOL1_PIPE7"; 230 static char th3_ifp_tcam_pool2_pipe7_name[] = "IFP_TCAM_POOL2_PIPE7"; 231 static char th3_ifp_logical_table_select_pipe0_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE0"; 232 static char th3_ifp_logical_table_select_pipe1_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE1"; 233 static char th3_ifp_logical_table_select_pipe2_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE2"; 234 static char th3_ifp_logical_table_select_pipe3_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE3"; 235 static char th3_ifp_logical_table_select_pipe4_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE4"; 236 static char th3_ifp_logical_table_select_pipe5_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE5"; 237 static char th3_ifp_logical_table_select_pipe6_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE6"; 238 static char th3_ifp_logical_table_select_pipe7_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE7"; 239 static char th3_l2_user_entry_pipe0_name[] = "L2_USER_ENTRY_PIPE0"; 240 static char th3_l2_user_entry_pipe1_name[] = "L2_USER_ENTRY_PIPE1"; 241 static char th3_l2_user_entry_pipe2_name[] = "L2_USER_ENTRY_PIPE2"; 242 static char th3_l2_user_entry_pipe3_name[] = "L2_USER_ENTRY_PIPE3"; 243 static char th3_l2_user_entry_pipe4_name[] = "L2_USER_ENTRY_PIPE4"; 244 static char th3_l2_user_entry_pipe5_name[] = "L2_USER_ENTRY_PIPE5"; 245 static char th3_l2_user_entry_pipe6_name[] = "L2_USER_ENTRY_PIPE6"; 246 static char th3_l2_user_entry_pipe7_name[] = "L2_USER_ENTRY_PIPE7"; 247 static char th3_l3_defip_pipe0_mode0_name[] = "L3_DEFIP_PIPE0_MODE0"; 248 static char th3_l3_defip_pipe1_mode0_name[] = "L3_DEFIP_PIPE1_MODE0"; 249 static char th3_l3_defip_pipe2_mode0_name[] = "L3_DEFIP_PIPE2_MODE0"; 250 static char th3_l3_defip_pipe3_mode0_name[] = "L3_DEFIP_PIPE3_MODE0"; 251 static char th3_l3_defip_pipe4_mode0_name[] = "L3_DEFIP_PIPE4_MODE0"; 252 static char th3_l3_defip_pipe5_mode0_name[] = "L3_DEFIP_PIPE5_MODE0"; 253 static char th3_l3_defip_pipe6_mode0_name[] = "L3_DEFIP_PIPE6_MODE0"; 254 static char th3_l3_defip_pipe7_mode0_name[] = "L3_DEFIP_PIPE7_MODE0"; 255 static char th3_l3_defip_pipe0_mode1_name[] = "L3_DEFIP_PIPE0_MODE1"; 256 static char th3_l3_defip_pipe1_mode1_name[] = "L3_DEFIP_PIPE1_MODE1"; 257 static char th3_l3_defip_pipe2_mode1_name[] = "L3_DEFIP_PIPE2_MODE1"; 258 static char th3_l3_defip_pipe3_mode1_name[] = "L3_DEFIP_PIPE3_MODE1"; 259 static char th3_l3_defip_pipe4_mode1_name[] = "L3_DEFIP_PIPE4_MODE1"; 260 static char th3_l3_defip_pipe5_mode1_name[] = "L3_DEFIP_PIPE5_MODE1"; 261 static char th3_l3_defip_pipe6_mode1_name[] = "L3_DEFIP_PIPE6_MODE1"; 262 static char th3_l3_defip_pipe7_mode1_name[] = "L3_DEFIP_PIPE7_MODE1"; 263 static char th3_l3_defip_pipe0_mode2_name[] = "L3_DEFIP_PIPE0_MODE2"; 264 static char th3_l3_defip_pipe1_mode2_name[] = "L3_DEFIP_PIPE1_MODE2"; 265 static char th3_l3_defip_pipe2_mode2_name[] = "L3_DEFIP_PIPE2_MODE2"; 266 static char th3_l3_defip_pipe3_mode2_name[] = "L3_DEFIP_PIPE3_MODE2"; 267 static char th3_l3_defip_pipe4_mode2_name[] = "L3_DEFIP_PIPE4_MODE2"; 268 static char th3_l3_defip_pipe5_mode2_name[] = "L3_DEFIP_PIPE5_MODE2"; 269 static char th3_l3_defip_pipe6_mode2_name[] = "L3_DEFIP_PIPE6_MODE2"; 270 static char th3_l3_defip_pipe7_mode2_name[] = "L3_DEFIP_PIPE7_MODE2"; 271 static char th3_udf_pipe0_name[] = "UDF_PIPE0"; 272 static char th3_udf_pipe1_name[] = "UDF_PIPE1"; 273 static char th3_udf_pipe2_name[] = "UDF_PIPE2"; 274 static char th3_udf_pipe3_name[] = "UDF_PIPE3"; 275 static char th3_udf_pipe4_name[] = "UDF_PIPE4"; 276 static char th3_udf_pipe5_name[] = "UDF_PIPE6"; 277 static char th3_udf_pipe6_name[] = "UDF_PIPE6"; 278 static char th3_udf_pipe7_name[] = "UDF_PIPE7"; 279 static char th3_vfp_pipe0_name[] = "VFP_PIPE0"; 280 static char th3_vfp_pipe1_name[] = "VFP_PIPE1"; 281 static char th3_vfp_pipe2_name[] = "VFP_PIPE2"; 282 static char th3_vfp_pipe3_name[] = "VFP_PIPE3"; 283 static char th3_vfp_pipe4_name[] = "VFP_PIPE4"; 284 static char th3_vfp_pipe5_name[] = "VFP_PIPE5"; 285 static char th3_vfp_pipe6_name[] = "VFP_PIPE6"; 286 static char th3_vfp_pipe7_name[] = "VFP_PIPE7"; 287 288 static cambist_t th3_cambist_array[] = { 289 TH3_CPU_COS_PIPE0, 290 TH3_CPU_COS_PIPE1, 291 TH3_CPU_COS_PIPE2, 292 TH3_CPU_COS_PIPE3, 293 TH3_CPU_COS_PIPE4, 294 TH3_CPU_COS_PIPE5, 295 TH3_CPU_COS_PIPE6, 296 TH3_CPU_COS_PIPE7, 297 TH3_EFP_PIPE0_SLICE0, 298 TH3_EFP_PIPE0_SLICE1, 299 TH3_EFP_PIPE0_SLICE2, 300 TH3_EFP_PIPE0_SLICE3, 301 TH3_EFP_PIPE1_SLICE0, 302 TH3_EFP_PIPE1_SLICE1, 303 TH3_EFP_PIPE1_SLICE2, 304 TH3_EFP_PIPE1_SLICE3, 305 TH3_EFP_PIPE2_SLICE0, 306 TH3_EFP_PIPE2_SLICE1, 307 TH3_EFP_PIPE2_SLICE2, 308 TH3_EFP_PIPE2_SLICE3, 309 TH3_EFP_PIPE3_SLICE0, 310 TH3_EFP_PIPE3_SLICE1, 311 TH3_EFP_PIPE3_SLICE2, 312 TH3_EFP_PIPE3_SLICE3, 313 TH3_EFP_PIPE4_SLICE0, 314 TH3_EFP_PIPE4_SLICE1, 315 TH3_EFP_PIPE4_SLICE2, 316 TH3_EFP_PIPE4_SLICE3, 317 TH3_EFP_PIPE5_SLICE0, 318 TH3_EFP_PIPE5_SLICE1, 319 TH3_EFP_PIPE5_SLICE2, 320 TH3_EFP_PIPE5_SLICE3, 321 TH3_EFP_PIPE6_SLICE0, 322 TH3_EFP_PIPE6_SLICE1, 323 TH3_EFP_PIPE6_SLICE2, 324 TH3_EFP_PIPE6_SLICE3, 325 TH3_EFP_PIPE7_SLICE0, 326 TH3_EFP_PIPE7_SLICE1, 327 TH3_EFP_PIPE7_SLICE2, 328 TH3_EFP_PIPE7_SLICE3, 329 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0, 330 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1, 331 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2, 332 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3, 333 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4, 334 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5, 335 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6, 336 TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7, 337 TH3_IFP_TCAM_POOL0_PIPE0, 338 TH3_IFP_TCAM_POOL1_PIPE0, 339 TH3_IFP_TCAM_POOL2_PIPE0, 340 TH3_IFP_TCAM_POOL0_PIPE1, 341 TH3_IFP_TCAM_POOL1_PIPE1, 342 TH3_IFP_TCAM_POOL2_PIPE1, 343 TH3_IFP_TCAM_POOL0_PIPE2, 344 TH3_IFP_TCAM_POOL1_PIPE2, 345 TH3_IFP_TCAM_POOL2_PIPE2, 346 TH3_IFP_TCAM_POOL0_PIPE3, 347 TH3_IFP_TCAM_POOL1_PIPE3, 348 TH3_IFP_TCAM_POOL2_PIPE3, 349 TH3_IFP_TCAM_POOL0_PIPE4, 350 TH3_IFP_TCAM_POOL1_PIPE4, 351 TH3_IFP_TCAM_POOL2_PIPE4, 352 TH3_IFP_TCAM_POOL0_PIPE5, 353 TH3_IFP_TCAM_POOL1_PIPE5, 354 TH3_IFP_TCAM_POOL2_PIPE5, 355 TH3_IFP_TCAM_POOL0_PIPE6, 356 TH3_IFP_TCAM_POOL1_PIPE6, 357 TH3_IFP_TCAM_POOL2_PIPE6, 358 TH3_IFP_TCAM_POOL0_PIPE7, 359 TH3_IFP_TCAM_POOL1_PIPE7, 360 TH3_IFP_TCAM_POOL2_PIPE7, 361 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE0, 362 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE1, 363 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE2, 364 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE3, 365 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE4, 366 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE5, 367 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE6, 368 TH3_IFP_LOGICAL_TABLE_SELECT_PIPE7, 369 TH3_L2_USER_ENTRY_PIPE0, 370 TH3_L2_USER_ENTRY_PIPE1, 371 TH3_L2_USER_ENTRY_PIPE2, 372 TH3_L2_USER_ENTRY_PIPE3, 373 TH3_L2_USER_ENTRY_PIPE4, 374 TH3_L2_USER_ENTRY_PIPE5, 375 TH3_L2_USER_ENTRY_PIPE6, 376 TH3_L2_USER_ENTRY_PIPE7, 377 TH3_L3_DEFIP_PIPE0_MODE0, 378 TH3_L3_DEFIP_PIPE1_MODE0, 379 TH3_L3_DEFIP_PIPE2_MODE0, 380 TH3_L3_DEFIP_PIPE3_MODE0, 381 TH3_L3_DEFIP_PIPE4_MODE0, 382 TH3_L3_DEFIP_PIPE5_MODE0, 383 TH3_L3_DEFIP_PIPE6_MODE0, 384 TH3_L3_DEFIP_PIPE7_MODE0, 385 TH3_L3_DEFIP_PIPE0_MODE1, 386 TH3_L3_DEFIP_PIPE1_MODE1, 387 TH3_L3_DEFIP_PIPE2_MODE1, 388 TH3_L3_DEFIP_PIPE3_MODE1, 389 TH3_L3_DEFIP_PIPE4_MODE1, 390 TH3_L3_DEFIP_PIPE5_MODE1, 391 TH3_L3_DEFIP_PIPE6_MODE1, 392 TH3_L3_DEFIP_PIPE7_MODE1, 393 TH3_L3_DEFIP_PIPE0_MODE2, 394 TH3_L3_DEFIP_PIPE1_MODE2, 395 TH3_L3_DEFIP_PIPE2_MODE2, 396 TH3_L3_DEFIP_PIPE3_MODE2, 397 TH3_L3_DEFIP_PIPE4_MODE2, 398 TH3_L3_DEFIP_PIPE5_MODE2, 399 TH3_L3_DEFIP_PIPE6_MODE2, 400 TH3_L3_DEFIP_PIPE7_MODE2, 401 TH3_UDF_PIPE0, 402 TH3_UDF_PIPE1, 403 TH3_UDF_PIPE2, 404 TH3_UDF_PIPE3, 405 TH3_UDF_PIPE4, 406 TH3_UDF_PIPE5, 407 TH3_UDF_PIPE6, 408 TH3_UDF_PIPE7, 409 TH3_VFP_PIPE0, 410 TH3_VFP_PIPE1, 411 TH3_VFP_PIPE2, 412 TH3_VFP_PIPE3, 413 TH3_VFP_PIPE4, 414 TH3_VFP_PIPE5, 415 TH3_VFP_PIPE6, 416 TH3_VFP_PIPE7 417 };