th2_cambist.h (33323B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 #define TH2_CPU_COS_PIPE0 {th2_cpu_cos_pipe0_name, NO_MODE, NO_MODE_FIELD, CPU_COS_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_CAM_BIST_STATUS_PIPE0r} 8 #define TH2_CPU_COS_PIPE1 {th2_cpu_cos_pipe1_name, NO_MODE, NO_MODE_FIELD, CPU_COS_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_CAM_BIST_STATUS_PIPE1r} 9 #define TH2_CPU_COS_PIPE2 {th2_cpu_cos_pipe2_name, NO_MODE, NO_MODE_FIELD, CPU_COS_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_CAM_BIST_STATUS_PIPE2r} 10 #define TH2_CPU_COS_PIPE3 {th2_cpu_cos_pipe3_name, NO_MODE, NO_MODE_FIELD, CPU_COS_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_CAM_BIST_STATUS_PIPE3r} 11 #define TH2_DST_COMPRESSION_PIPE0 {th2_dst_compression_pipe0_name, NO_MODE, NO_MODE_FIELD, DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, DST_COMPRESSION_CAM_BIST_STATUS_PIPE0r} 12 #define TH2_DST_COMPRESSION_PIPE1 {th2_dst_compression_pipe1_name, NO_MODE, NO_MODE_FIELD, DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, DST_COMPRESSION_CAM_BIST_STATUS_PIPE1r} 13 #define TH2_DST_COMPRESSION_PIPE2 {th2_dst_compression_pipe2_name, NO_MODE, NO_MODE_FIELD, DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, DST_COMPRESSION_CAM_BIST_STATUS_PIPE2r} 14 #define TH2_DST_COMPRESSION_PIPE3 {th2_dst_compression_pipe3_name, NO_MODE, NO_MODE_FIELD, DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, DST_COMPRESSION_CAM_BIST_STATUS_PIPE3r} 15 #define TH2_EFP_PIPE0_SLICE0 {th2_efp_pipe0_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE0r} 16 #define TH2_EFP_PIPE0_SLICE1 {th2_efp_pipe0_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE0r} 17 #define TH2_EFP_PIPE0_SLICE2 {th2_efp_pipe0_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE0r} 18 #define TH2_EFP_PIPE0_SLICE3 {th2_efp_pipe0_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE0r} 19 #define TH2_EFP_PIPE1_SLICE0 {th2_efp_pipe1_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE1r} 20 #define TH2_EFP_PIPE1_SLICE1 {th2_efp_pipe1_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE1r} 21 #define TH2_EFP_PIPE1_SLICE2 {th2_efp_pipe1_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE1r} 22 #define TH2_EFP_PIPE1_SLICE3 {th2_efp_pipe1_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE1r} 23 #define TH2_EFP_PIPE2_SLICE0 {th2_efp_pipe2_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE2r} 24 #define TH2_EFP_PIPE2_SLICE1 {th2_efp_pipe2_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE2r} 25 #define TH2_EFP_PIPE2_SLICE2 {th2_efp_pipe2_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE2r} 26 #define TH2_EFP_PIPE2_SLICE3 {th2_efp_pipe2_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE2r} 27 #define TH2_EFP_PIPE3_SLICE0 {th2_efp_pipe3_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE3r} 28 #define TH2_EFP_PIPE3_SLICE1 {th2_efp_pipe3_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE3r} 29 #define TH2_EFP_PIPE3_SLICE2 {th2_efp_pipe3_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE3r} 30 #define TH2_EFP_PIPE3_SLICE3 {th2_efp_pipe3_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE3r} 31 #define TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0 {th2_exact_match_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r} 32 #define TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1 {th2_exact_match_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r} 33 #define TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2 {th2_exact_match_logical_table_select_pipe2_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2r} 34 #define TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3 {th2_exact_match_logical_table_select_pipe3_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3r} 35 #define TH2_IFP_TCAM_POOL0_PIPE0 {th2_ifp_tcam_pool0_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE0r} 36 #define TH2_IFP_TCAM_POOL1_PIPE0 {th2_ifp_tcam_pool1_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE0r} 37 #define TH2_IFP_TCAM_POOL2_PIPE0 {th2_ifp_tcam_pool2_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE0r} 38 #define TH2_IFP_TCAM_POOL3_PIPE0 {th2_ifp_tcam_pool3_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL3_BIST_STATUS_PIPE0r} 39 #define TH2_IFP_TCAM_POOL0_PIPE1 {th2_ifp_tcam_pool0_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE1r} 40 #define TH2_IFP_TCAM_POOL1_PIPE1 {th2_ifp_tcam_pool1_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE1r} 41 #define TH2_IFP_TCAM_POOL2_PIPE1 {th2_ifp_tcam_pool2_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE1r} 42 #define TH2_IFP_TCAM_POOL3_PIPE1 {th2_ifp_tcam_pool3_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL3_BIST_STATUS_PIPE1r} 43 #define TH2_IFP_TCAM_POOL0_PIPE2 {th2_ifp_tcam_pool0_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE2r} 44 #define TH2_IFP_TCAM_POOL1_PIPE2 {th2_ifp_tcam_pool1_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE2r} 45 #define TH2_IFP_TCAM_POOL2_PIPE2 {th2_ifp_tcam_pool2_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE2r} 46 #define TH2_IFP_TCAM_POOL3_PIPE2 {th2_ifp_tcam_pool3_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL3_BIST_STATUS_PIPE2r} 47 #define TH2_IFP_TCAM_POOL0_PIPE3 {th2_ifp_tcam_pool0_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE3r} 48 #define TH2_IFP_TCAM_POOL1_PIPE3 {th2_ifp_tcam_pool1_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE3r} 49 #define TH2_IFP_TCAM_POOL2_PIPE3 {th2_ifp_tcam_pool2_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE3r} 50 #define TH2_IFP_TCAM_POOL3_PIPE3 {th2_ifp_tcam_pool3_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL3_BIST_STATUS_PIPE3r} 51 #define TH2_IFP_LOGICAL_TABLE_SELECT_PIPE0 {th2_ifp_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r} 52 #define TH2_IFP_LOGICAL_TABLE_SELECT_PIPE1 {th2_ifp_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r} 53 #define TH2_IFP_LOGICAL_TABLE_SELECT_PIPE2 {th2_ifp_logical_table_select_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2r} 54 #define TH2_IFP_LOGICAL_TABLE_SELECT_PIPE3 {th2_ifp_logical_table_select_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3r} 55 #define TH2_ING_SNAT_PIPE0 {th2_ing_snat_pipe0_name, NO_MODE, NO_MODE_FIELD, ING_SNAT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, ING_SNAT_CAM_BIST_STATUS_PIPE0r} 56 #define TH2_ING_SNAT_PIPE1 {th2_ing_snat_pipe1_name, NO_MODE, NO_MODE_FIELD, ING_SNAT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, ING_SNAT_CAM_BIST_STATUS_PIPE1r} 57 #define TH2_ING_SNAT_PIPE2 {th2_ing_snat_pipe2_name, NO_MODE, NO_MODE_FIELD, ING_SNAT_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, ING_SNAT_CAM_BIST_STATUS_PIPE2r} 58 #define TH2_ING_SNAT_PIPE3 {th2_ing_snat_pipe3_name, NO_MODE, NO_MODE_FIELD, ING_SNAT_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, ING_SNAT_CAM_BIST_STATUS_PIPE3r} 59 #define TH2_IP_MULTICAST_PIPE0 {th2_ip_multicast_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_MULTICAST_CAM_BIST_STATUS_PIPE0r} 60 #define TH2_IP_MULTICAST_PIPE1 {th2_ip_multicast_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_MULTICAST_CAM_BIST_STATUS_PIPE1r} 61 #define TH2_IP_MULTICAST_PIPE2 {th2_ip_multicast_pipe2_name, NO_MODE, NO_MODE_FIELD, IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_MULTICAST_CAM_BIST_STATUS_PIPE2r} 62 #define TH2_IP_MULTICAST_PIPE3 {th2_ip_multicast_pipe3_name, NO_MODE, NO_MODE_FIELD, IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_MULTICAST_CAM_BIST_STATUS_PIPE3r} 63 #define TH2_L2_USER_ENTRY_PIPE0 {th2_l2_user_entry_pipe0_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE0r} 64 #define TH2_L2_USER_ENTRY_PIPE1 {th2_l2_user_entry_pipe1_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE1r} 65 #define TH2_L2_USER_ENTRY_PIPE2 {th2_l2_user_entry_pipe2_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE2r} 66 #define TH2_L2_USER_ENTRY_PIPE3 {th2_l2_user_entry_pipe3_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE3r} 67 #define TH2_L3_DEFIP_PIPE0_MODE0 {th2_l3_defip_pipe0_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE0r} 68 #define TH2_L3_DEFIP_PIPE1_MODE0 {th2_l3_defip_pipe1_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE1r} 69 #define TH2_L3_DEFIP_PIPE2_MODE0 {th2_l3_defip_pipe2_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE2r} 70 #define TH2_L3_DEFIP_PIPE3_MODE0 {th2_l3_defip_pipe3_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE3r} 71 #define TH2_L3_DEFIP_PIPE0_MODE1 {th2_l3_defip_pipe0_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE0r} 72 #define TH2_L3_DEFIP_PIPE1_MODE1 {th2_l3_defip_pipe1_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE1r} 73 #define TH2_L3_DEFIP_PIPE2_MODE1 {th2_l3_defip_pipe2_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE2r} 74 #define TH2_L3_DEFIP_PIPE3_MODE1 {th2_l3_defip_pipe3_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE3r} 75 #define TH2_L3_DEFIP_PIPE0_MODE2 {th2_l3_defip_pipe0_mode2_name, 2, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE0r} 76 #define TH2_L3_DEFIP_PIPE1_MODE2 {th2_l3_defip_pipe1_mode2_name, 2, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE1r} 77 #define TH2_L3_DEFIP_PIPE2_MODE2 {th2_l3_defip_pipe2_mode2_name, 2, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE2r} 78 #define TH2_L3_DEFIP_PIPE3_MODE2 {th2_l3_defip_pipe3_mode2_name, 2, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_CAM_BIST_STATUS_PIPE3r} 79 #define TH2_L3_TUNNEL_PIPE0 {th2_l3_tunnel_pipe0_name, NO_MODE, NO_MODE_FIELD, L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_TUNNEL_CAM_BIST_STATUS_PIPE0r} 80 #define TH2_L3_TUNNEL_PIPE1 {th2_l3_tunnel_pipe1_name, NO_MODE, NO_MODE_FIELD, L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_TUNNEL_CAM_BIST_STATUS_PIPE1r} 81 #define TH2_L3_TUNNEL_PIPE2 {th2_l3_tunnel_pipe2_name, NO_MODE, NO_MODE_FIELD, L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_TUNNEL_CAM_BIST_STATUS_PIPE2r} 82 #define TH2_L3_TUNNEL_PIPE3 {th2_l3_tunnel_pipe3_name, NO_MODE, NO_MODE_FIELD, L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_TUNNEL_CAM_BIST_STATUS_PIPE3r} 83 #define TH2_MY_STATION_CAM_PIPE0 {th2_my_station_cam_pipe0_name, NO_MODE, NO_MODE_FIELD, MY_STATION_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, MY_STATION_CAM_BIST_STATUS_PIPE0r} 84 #define TH2_MY_STATION_CAM_PIPE1 {th2_my_station_cam_pipe1_name, NO_MODE, NO_MODE_FIELD, MY_STATION_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, MY_STATION_CAM_BIST_STATUS_PIPE1r} 85 #define TH2_MY_STATION_CAM_PIPE2 {th2_my_station_cam_pipe2_name, NO_MODE, NO_MODE_FIELD, MY_STATION_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, MY_STATION_CAM_BIST_STATUS_PIPE2r} 86 #define TH2_MY_STATION_CAM_PIPE3 {th2_my_station_cam_pipe3_name, NO_MODE, NO_MODE_FIELD, MY_STATION_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, MY_STATION_CAM_BIST_STATUS_PIPE3r} 87 #define TH2_SRC_COMPRESSION_PIPE0 {th2_src_compression_pipe0_name, NO_MODE, NO_MODE_FIELD, SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, SRC_COMPRESSION_CAM_BIST_STATUS_PIPE0r} 88 #define TH2_SRC_COMPRESSION_PIPE1 {th2_src_compression_pipe1_name, NO_MODE, NO_MODE_FIELD, SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, SRC_COMPRESSION_CAM_BIST_STATUS_PIPE1r} 89 #define TH2_SRC_COMPRESSION_PIPE2 {th2_src_compression_pipe2_name, NO_MODE, NO_MODE_FIELD, SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, SRC_COMPRESSION_CAM_BIST_STATUS_PIPE2r} 90 #define TH2_SRC_COMPRESSION_PIPE3 {th2_src_compression_pipe3_name, NO_MODE, NO_MODE_FIELD, SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, SRC_COMPRESSION_CAM_BIST_STATUS_PIPE3r} 91 #define TH2_UDF_PIPE0 {th2_udf_pipe0_name, NO_MODE, NO_MODE_FIELD, UDF_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_CAM_BIST_STATUS_PIPE0r} 92 #define TH2_UDF_PIPE1 {th2_udf_pipe1_name, NO_MODE, NO_MODE_FIELD, UDF_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_CAM_BIST_STATUS_PIPE1r} 93 #define TH2_UDF_PIPE2 {th2_udf_pipe2_name, NO_MODE, NO_MODE_FIELD, UDF_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_CAM_BIST_STATUS_PIPE2r} 94 #define TH2_UDF_PIPE3 {th2_udf_pipe3_name, NO_MODE, NO_MODE_FIELD, UDF_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_CAM_BIST_STATUS_PIPE3r} 95 #define TH2_VFP_PIPE0 {th2_vfp_pipe0_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE0r} 96 #define TH2_VFP_PIPE1 {th2_vfp_pipe1_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE1r} 97 #define TH2_VFP_PIPE2 {th2_vfp_pipe2_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE2r} 98 #define TH2_VFP_PIPE3 {th2_vfp_pipe3_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE3r} 99 #define TH2_VLAN_SUBNET_PIPE0 {th2_vlan_subnet_pipe0_name, NO_MODE, NO_MODE_FIELD, VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, VLAN_SUBNET_CAM_BIST_STATUS_PIPE0r} 100 #define TH2_VLAN_SUBNET_PIPE1 {th2_vlan_subnet_pipe1_name, NO_MODE, NO_MODE_FIELD, VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, VLAN_SUBNET_CAM_BIST_STATUS_PIPE1r} 101 #define TH2_VLAN_SUBNET_PIPE2 {th2_vlan_subnet_pipe2_name, NO_MODE, NO_MODE_FIELD, VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, VLAN_SUBNET_CAM_BIST_STATUS_PIPE2r} 102 #define TH2_VLAN_SUBNET_PIPE3 {th2_vlan_subnet_pipe3_name, NO_MODE, NO_MODE_FIELD, VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, VLAN_SUBNET_CAM_BIST_STATUS_PIPE3r} 103 104 #define TH2_TOTAL_CAMBIST_COUNT 96 105 106 #define TH2_DONE_BIT_MASK 0x00000001 107 #define TH2_BIST_SUCCESS_MASK 0x00000002 108 109 static char th2_cpu_cos_pipe0_name[] = "CPU_COS_PIPE0"; 110 static char th2_cpu_cos_pipe1_name[] = "CPU_COS_PIPE1"; 111 static char th2_cpu_cos_pipe2_name[] = "CPU_COS_PIPE2"; 112 static char th2_cpu_cos_pipe3_name[] = "CPU_COS_PIPE3"; 113 static char th2_dst_compression_pipe0_name[] = "DST_COMPRESSION_PIPE0"; 114 static char th2_dst_compression_pipe1_name[] = "DST_COMPRESSION_PIPE1"; 115 static char th2_dst_compression_pipe2_name[] = "DST_COMPRESSION_PIPE2"; 116 static char th2_dst_compression_pipe3_name[] = "DST_COMPRESSION_PIPE3"; 117 static char th2_efp_pipe0_slice0_name[] = "EFP_PIPE0_SLICE0"; 118 static char th2_efp_pipe0_slice1_name[] = "EFP_PIPE0_SLICE1"; 119 static char th2_efp_pipe0_slice2_name[] = "EFP_PIPE0_SLICE2"; 120 static char th2_efp_pipe0_slice3_name[] = "EFP_PIPE0_SLICE3"; 121 static char th2_efp_pipe1_slice0_name[] = "EFP_PIPE1_SLICE0"; 122 static char th2_efp_pipe1_slice1_name[] = "EFP_PIPE1_SLICE1"; 123 static char th2_efp_pipe1_slice2_name[] = "EFP_PIPE1_SLICE2"; 124 static char th2_efp_pipe1_slice3_name[] = "EFP_PIPE1_SLICE3"; 125 static char th2_efp_pipe2_slice0_name[] = "EFP_PIPE2_SLICE0"; 126 static char th2_efp_pipe2_slice1_name[] = "EFP_PIPE2_SLICE1"; 127 static char th2_efp_pipe2_slice2_name[] = "EFP_PIPE2_SLICE2"; 128 static char th2_efp_pipe2_slice3_name[] = "EFP_PIPE2_SLICE3"; 129 static char th2_efp_pipe3_slice0_name[] = "EFP_PIPE3_SLICE0"; 130 static char th2_efp_pipe3_slice1_name[] = "EFP_PIPE3_SLICE1"; 131 static char th2_efp_pipe3_slice2_name[] = "EFP_PIPE3_SLICE2"; 132 static char th2_efp_pipe3_slice3_name[] = "EFP_PIPE3_SLICE3"; 133 static char th2_exact_match_logical_table_select_pipe0_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0"; 134 static char th2_exact_match_logical_table_select_pipe1_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1"; 135 static char th2_exact_match_logical_table_select_pipe2_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2"; 136 static char th2_exact_match_logical_table_select_pipe3_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3"; 137 static char th2_ifp_tcam_pool0_pipe0_name[] = "IFP_TCAM_POOL0_PIPE0"; 138 static char th2_ifp_tcam_pool1_pipe0_name[] = "IFP_TCAM_POOL1_PIPE0"; 139 static char th2_ifp_tcam_pool2_pipe0_name[] = "IFP_TCAM_POOL2_PIPE0"; 140 static char th2_ifp_tcam_pool3_pipe0_name[] = "IFP_TCAM_POOL3_PIPE0"; 141 static char th2_ifp_tcam_pool0_pipe1_name[] = "IFP_TCAM_POOL0_PIPE1"; 142 static char th2_ifp_tcam_pool1_pipe1_name[] = "IFP_TCAM_POOL1_PIPE1"; 143 static char th2_ifp_tcam_pool2_pipe1_name[] = "IFP_TCAM_POOL2_PIPE1"; 144 static char th2_ifp_tcam_pool3_pipe1_name[] = "IFP_TCAM_POOL3_PIPE1"; 145 static char th2_ifp_tcam_pool0_pipe2_name[] = "IFP_TCAM_POOL0_PIPE2"; 146 static char th2_ifp_tcam_pool1_pipe2_name[] = "IFP_TCAM_POOL1_PIPE2"; 147 static char th2_ifp_tcam_pool2_pipe2_name[] = "IFP_TCAM_POOL2_PIPE2"; 148 static char th2_ifp_tcam_pool3_pipe2_name[] = "IFP_TCAM_POOL3_PIPE2"; 149 static char th2_ifp_tcam_pool0_pipe3_name[] = "IFP_TCAM_POOL0_PIPE3"; 150 static char th2_ifp_tcam_pool1_pipe3_name[] = "IFP_TCAM_POOL1_PIPE3"; 151 static char th2_ifp_tcam_pool2_pipe3_name[] = "IFP_TCAM_POOL2_PIPE3"; 152 static char th2_ifp_tcam_pool3_pipe3_name[] = "IFP_TCAM_POOL3_PIPE3"; 153 static char th2_ifp_logical_table_select_pipe0_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE0"; 154 static char th2_ifp_logical_table_select_pipe1_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE1"; 155 static char th2_ifp_logical_table_select_pipe2_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE2"; 156 static char th2_ifp_logical_table_select_pipe3_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE3"; 157 static char th2_ing_snat_pipe0_name[] = "ING_SNAT_PIPE0"; 158 static char th2_ing_snat_pipe1_name[] = "ING_SNAT_PIPE1"; 159 static char th2_ing_snat_pipe2_name[] = "ING_SNAT_PIPE2"; 160 static char th2_ing_snat_pipe3_name[] = "ING_SNAT_PIPE3"; 161 static char th2_ip_multicast_pipe0_name[] = "IP_MULTICAST_PIPE0"; 162 static char th2_ip_multicast_pipe1_name[] = "IP_MULTICAST_PIPE1"; 163 static char th2_ip_multicast_pipe2_name[] = "IP_MULTICAST_PIPE2"; 164 static char th2_ip_multicast_pipe3_name[] = "IP_MULTICAST_PIPE3"; 165 static char th2_l2_user_entry_pipe0_name[] = "L2_USER_ENTRY_PIPE0"; 166 static char th2_l2_user_entry_pipe1_name[] = "L2_USER_ENTRY_PIPE1"; 167 static char th2_l2_user_entry_pipe2_name[] = "L2_USER_ENTRY_PIPE2"; 168 static char th2_l2_user_entry_pipe3_name[] = "L2_USER_ENTRY_PIPE3"; 169 static char th2_l3_defip_pipe0_mode0_name[] = "L3_DEFIP_PIPE0_MODE0"; 170 static char th2_l3_defip_pipe1_mode0_name[] = "L3_DEFIP_PIPE1_MODE0"; 171 static char th2_l3_defip_pipe2_mode0_name[] = "L3_DEFIP_PIPE2_MODE0"; 172 static char th2_l3_defip_pipe3_mode0_name[] = "L3_DEFIP_PIPE3_MODE0"; 173 static char th2_l3_defip_pipe0_mode1_name[] = "L3_DEFIP_PIPE0_MODE1"; 174 static char th2_l3_defip_pipe1_mode1_name[] = "L3_DEFIP_PIPE1_MODE1"; 175 static char th2_l3_defip_pipe2_mode1_name[] = "L3_DEFIP_PIPE2_MODE1"; 176 static char th2_l3_defip_pipe3_mode1_name[] = "L3_DEFIP_PIPE3_MODE1"; 177 static char th2_l3_defip_pipe0_mode2_name[] = "L3_DEFIP_PIPE0_MODE2"; 178 static char th2_l3_defip_pipe1_mode2_name[] = "L3_DEFIP_PIPE1_MODE2"; 179 static char th2_l3_defip_pipe2_mode2_name[] = "L3_DEFIP_PIPE2_MODE2"; 180 static char th2_l3_defip_pipe3_mode2_name[] = "L3_DEFIP_PIPE3_MODE2"; 181 static char th2_l3_tunnel_pipe0_name[] = "L3_TUNNEL_PIPE0"; 182 static char th2_l3_tunnel_pipe1_name[] = "L3_TUNNEL_PIPE1"; 183 static char th2_l3_tunnel_pipe2_name[] = "L3_TUNNEL_PIPE2"; 184 static char th2_l3_tunnel_pipe3_name[] = "L3_TUNNEL_PIPE3"; 185 static char th2_my_station_cam_pipe0_name[] = "MY_STATION_CAM_PIPE0"; 186 static char th2_my_station_cam_pipe1_name[] = "MY_STATION_CAM_PIPE1"; 187 static char th2_my_station_cam_pipe2_name[] = "MY_STATION_CAM_PIPE2"; 188 static char th2_my_station_cam_pipe3_name[] = "MY_STATION_CAM_PIPE3"; 189 static char th2_src_compression_pipe0_name[] = "SRC_COMPRESSION_PIPE0"; 190 static char th2_src_compression_pipe1_name[] = "SRC_COMPRESSION_PIPE1"; 191 static char th2_src_compression_pipe2_name[] = "SRC_COMPRESSION_PIPE2"; 192 static char th2_src_compression_pipe3_name[] = "SRC_COMPRESSION_PIPE3"; 193 static char th2_udf_pipe0_name[] = "UDF_PIPE0"; 194 static char th2_udf_pipe1_name[] = "UDF_PIPE1"; 195 static char th2_udf_pipe2_name[] = "UDF_PIPE2"; 196 static char th2_udf_pipe3_name[] = "UDF_PIPE3"; 197 static char th2_vfp_pipe0_name[] = "VFP_PIPE0"; 198 static char th2_vfp_pipe1_name[] = "VFP_PIPE1"; 199 static char th2_vfp_pipe2_name[] = "VFP_PIPE2"; 200 static char th2_vfp_pipe3_name[] = "VFP_PIPE3"; 201 static char th2_vlan_subnet_pipe0_name[] = "VLAN_SUBNET_PIPE0"; 202 static char th2_vlan_subnet_pipe1_name[] = "VLAN_SUBNET_PIPE1"; 203 static char th2_vlan_subnet_pipe2_name[] = "VLAN_SUBNET_PIPE2"; 204 static char th2_vlan_subnet_pipe3_name[] = "VLAN_SUBNET_PIPE3"; 205 206 static cambist_t th2_cambist_array[] = { 207 TH2_CPU_COS_PIPE0, 208 TH2_CPU_COS_PIPE1, 209 TH2_CPU_COS_PIPE2, 210 TH2_CPU_COS_PIPE3, 211 TH2_DST_COMPRESSION_PIPE0, 212 TH2_DST_COMPRESSION_PIPE1, 213 TH2_DST_COMPRESSION_PIPE2, 214 TH2_DST_COMPRESSION_PIPE3, 215 TH2_EFP_PIPE0_SLICE0, 216 TH2_EFP_PIPE0_SLICE1, 217 TH2_EFP_PIPE0_SLICE2, 218 TH2_EFP_PIPE0_SLICE3, 219 TH2_EFP_PIPE1_SLICE0, 220 TH2_EFP_PIPE1_SLICE1, 221 TH2_EFP_PIPE1_SLICE2, 222 TH2_EFP_PIPE1_SLICE3, 223 TH2_EFP_PIPE2_SLICE0, 224 TH2_EFP_PIPE2_SLICE1, 225 TH2_EFP_PIPE2_SLICE2, 226 TH2_EFP_PIPE2_SLICE3, 227 TH2_EFP_PIPE3_SLICE0, 228 TH2_EFP_PIPE3_SLICE1, 229 TH2_EFP_PIPE3_SLICE2, 230 TH2_EFP_PIPE3_SLICE3, 231 TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0, 232 TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1, 233 TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2, 234 TH2_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3, 235 TH2_IFP_TCAM_POOL0_PIPE0, 236 TH2_IFP_TCAM_POOL1_PIPE0, 237 TH2_IFP_TCAM_POOL2_PIPE0, 238 TH2_IFP_TCAM_POOL3_PIPE0, 239 TH2_IFP_TCAM_POOL0_PIPE1, 240 TH2_IFP_TCAM_POOL1_PIPE1, 241 TH2_IFP_TCAM_POOL2_PIPE1, 242 TH2_IFP_TCAM_POOL3_PIPE1, 243 TH2_IFP_TCAM_POOL0_PIPE2, 244 TH2_IFP_TCAM_POOL1_PIPE2, 245 TH2_IFP_TCAM_POOL2_PIPE2, 246 TH2_IFP_TCAM_POOL3_PIPE2, 247 TH2_IFP_TCAM_POOL0_PIPE3, 248 TH2_IFP_TCAM_POOL1_PIPE3, 249 TH2_IFP_TCAM_POOL2_PIPE3, 250 TH2_IFP_TCAM_POOL3_PIPE3, 251 TH2_IFP_LOGICAL_TABLE_SELECT_PIPE0, 252 TH2_IFP_LOGICAL_TABLE_SELECT_PIPE1, 253 TH2_IFP_LOGICAL_TABLE_SELECT_PIPE2, 254 TH2_IFP_LOGICAL_TABLE_SELECT_PIPE3, 255 TH2_ING_SNAT_PIPE0, 256 TH2_ING_SNAT_PIPE1, 257 TH2_ING_SNAT_PIPE2, 258 TH2_ING_SNAT_PIPE3, 259 TH2_IP_MULTICAST_PIPE0, 260 TH2_IP_MULTICAST_PIPE1, 261 TH2_IP_MULTICAST_PIPE2, 262 TH2_IP_MULTICAST_PIPE3, 263 TH2_L2_USER_ENTRY_PIPE0, 264 TH2_L2_USER_ENTRY_PIPE1, 265 TH2_L2_USER_ENTRY_PIPE2, 266 TH2_L2_USER_ENTRY_PIPE3, 267 TH2_L3_DEFIP_PIPE0_MODE0, 268 TH2_L3_DEFIP_PIPE1_MODE0, 269 TH2_L3_DEFIP_PIPE2_MODE0, 270 TH2_L3_DEFIP_PIPE3_MODE0, 271 TH2_L3_DEFIP_PIPE0_MODE1, 272 TH2_L3_DEFIP_PIPE1_MODE1, 273 TH2_L3_DEFIP_PIPE2_MODE1, 274 TH2_L3_DEFIP_PIPE3_MODE1, 275 TH2_L3_DEFIP_PIPE0_MODE2, 276 TH2_L3_DEFIP_PIPE1_MODE2, 277 TH2_L3_DEFIP_PIPE2_MODE2, 278 TH2_L3_DEFIP_PIPE3_MODE2, 279 TH2_L3_TUNNEL_PIPE0, 280 TH2_L3_TUNNEL_PIPE1, 281 TH2_L3_TUNNEL_PIPE2, 282 TH2_L3_TUNNEL_PIPE3, 283 TH2_MY_STATION_CAM_PIPE0, 284 TH2_MY_STATION_CAM_PIPE1, 285 TH2_MY_STATION_CAM_PIPE2, 286 TH2_MY_STATION_CAM_PIPE3, 287 TH2_SRC_COMPRESSION_PIPE0, 288 TH2_SRC_COMPRESSION_PIPE1, 289 TH2_SRC_COMPRESSION_PIPE2, 290 TH2_SRC_COMPRESSION_PIPE3, 291 TH2_UDF_PIPE0, 292 TH2_UDF_PIPE1, 293 TH2_UDF_PIPE2, 294 TH2_UDF_PIPE3, 295 TH2_VFP_PIPE0, 296 TH2_VFP_PIPE1, 297 TH2_VFP_PIPE2, 298 TH2_VFP_PIPE3, 299 TH2_VLAN_SUBNET_PIPE0, 300 TH2_VLAN_SUBNET_PIPE1, 301 TH2_VLAN_SUBNET_PIPE2, 302 TH2_VLAN_SUBNET_PIPE3 303 };