td3_cambist.h (49982B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 #define TD3_EGR_ZONE_2_EDITOR_CONTROL_TCAM_PIPE0 {td3_egr_zone_2_editor_control_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0r} 8 #define TD3_EGR_ZONE_2_EDITOR_CONTROL_TCAM_PIPE1 {td3_egr_zone_2_editor_control_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1r} 9 10 #define TD3_TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_tunnel_adapt_3_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 11 #define TD3_TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_tunnel_adapt_3_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 12 13 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_3_PIPE0 {td3_ip_parser2_hme_stage_tcam_only_3_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_3_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_3_PIPE0r} 14 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_3_PIPE1 {td3_ip_parser2_hme_stage_tcam_only_3_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_3_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_3_PIPE1r} 15 16 #define TD3_PHB_SELECT_TCAM_PIPE0 {td3_phb_select_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, PHB_SELECT_TCAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, PHB_SELECT_TCAM_CAM_BIST_STATUS_PIPE0r} 17 #define TD3_PHB_SELECT_TCAM_PIPE1 {td3_phb_select_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, PHB_SELECT_TCAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, PHB_SELECT_TCAM_CAM_BIST_STATUS_PIPE1r} 18 19 #define TD3_FORWARDING_2_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_forwarding_2_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, FORWARDING_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_2_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 20 #define TD3_FORWARDING_2_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_forwarding_2_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, FORWARDING_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_2_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 21 22 #define TD3_MY_STATION_TCAM_2_PIPE0 {td3_my_station_tcam_2_pipe0_name, NO_MODE, NO_MODE_FIELD, MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_STATUS_PIPE0r} 23 #define TD3_MY_STATION_TCAM_2_PIPE1 {td3_my_station_tcam_2_pipe1_name, NO_MODE, NO_MODE_FIELD, MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_STATUS_PIPE1r} 24 25 #define TD3_EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_PIPE0 {td3_egr_field_extraction_profile_2_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_STATUS_PIPE0r} 26 #define TD3_EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_PIPE1 {td3_egr_field_extraction_profile_2_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_STATUS_PIPE1r} 27 28 #define TD3_EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_PIPE0 {td3_egr_field_extraction_profile_1_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_STATUS_PIPE0r} 29 #define TD3_EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_PIPE1 {td3_egr_field_extraction_profile_1_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_STATUS_PIPE1r} 30 31 #define TD3_L2_USER_ENTRY_PIPE0 {td3_l2_user_entry_pipe0_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_ONLY_CAM_BIST_STATUS_PIPE0r} 32 #define TD3_L2_USER_ENTRY_PIPE1 {td3_l2_user_entry_pipe1_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_ONLY_CAM_BIST_STATUS_PIPE1r} 33 34 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_3_PIPE0 {td3_ip_parser1_hme_stage_tcam_only_3_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_3_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_3_PIPE0r} 35 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_3_PIPE1 {td3_ip_parser1_hme_stage_tcam_only_3_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_3_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_3_PIPE1r} 36 37 #define TD3_PKT_FLOW_SELECT_TCAM_1_PIPE0 {td3_pkt_flow_select_tcam_1_pipe0_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_1_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, PKT_FLOW_SELECT_TCAM_1_BIST_STATUS_PIPE0r} 38 #define TD3_PKT_FLOW_SELECT_TCAM_1_PIPE1 {td3_pkt_flow_select_tcam_1_pipe1_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_1_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, PKT_FLOW_SELECT_TCAM_1_BIST_STATUS_PIPE1r} 39 40 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_4_PIPE0 {td3_ip_parser2_hme_stage_tcam_only_4_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_4_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_4_PIPE0r} 41 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_4_PIPE1 {td3_ip_parser2_hme_stage_tcam_only_4_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_4_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_4_PIPE1r} 42 43 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_0_PIPE0 {td3_ip_parser1_hme_stage_tcam_only_0_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_0_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_0_PIPE0r} 44 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_0_PIPE1 {td3_ip_parser1_hme_stage_tcam_only_0_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_0_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_0_PIPE1r} 45 46 #define TD3_IP_MULTICAST_TCAM_PIPE0 {td3_ip_multicast_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_MULTICAST_TCAM_CAM_BIST_STATUS_PIPE0r} 47 #define TD3_IP_MULTICAST_TCAM_PIPE1 {td3_ip_multicast_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_MULTICAST_TCAM_CAM_BIST_STATUS_PIPE1r} 48 49 #define TD3_IP_PARSER0_HME_STAGE_TCAM_ONLY_0_PIPE0 {td3_ip_parser0_hme_stage_tcam_only_0_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER0_HME_STAGE_CAM_BIST_CONFIG_0_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER0_HME_STAGE_TCAM_BIST_STATUS_0_PIPE0r} 50 #define TD3_IP_PARSER0_HME_STAGE_TCAM_ONLY_0_PIPE1 {td3_ip_parser0_hme_stage_tcam_only_0_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER0_HME_STAGE_CAM_BIST_CONFIG_0_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER0_HME_STAGE_TCAM_BIST_STATUS_0_PIPE1r} 51 52 #define TD3_IFP_LOGICAL_TABLE_SELECT_PIPE0 {td3_ifp_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r} 53 #define TD3_IFP_LOGICAL_TABLE_SELECT_PIPE1 {td3_ifp_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r} 54 55 #define TD3_FLEX_RTAG7_HASH_TCAM_ONLY_PIPE0 {td3_flex_rtag7_hash_tcam_only_pipe0_name, NO_MODE, NO_MODE_FIELD, FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_STATUS_PIPE0r} 56 #define TD3_FLEX_RTAG7_HASH_TCAM_ONLY_PIPE1 {td3_flex_rtag7_hash_tcam_only_pipe1_name, NO_MODE, NO_MODE_FIELD, FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_STATUS_PIPE1r} 57 58 #define TD3_ING_SNAT_PIPE0 {td3_ing_snat_pipe0_name, NO_MODE, NO_MODE_FIELD, ING_SNAT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, ING_SNAT_CAM_BIST_STATUS_PIPE0r} 59 #define TD3_ING_SNAT_PIPE1 {td3_ing_snat_pipe1_name, NO_MODE, NO_MODE_FIELD, ING_SNAT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, ING_SNAT_CAM_BIST_STATUS_PIPE1r} 60 61 #define TD3_EGR_ZONE_0_EDITOR_CONTROL_TCAM_PIPE0 {td3_egr_zone_0_editor_control_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0r} 62 #define TD3_EGR_ZONE_0_EDITOR_CONTROL_TCAM_PIPE1 {td3_egr_zone_0_editor_control_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1r} 63 64 #define TD3_TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_tunnel_adapt_2_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 65 #define TD3_TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_tunnel_adapt_2_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 66 67 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_2_PIPE0 {td3_ip_parser2_hme_stage_tcam_only_2_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_2_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_2_PIPE0r} 68 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_2_PIPE1 {td3_ip_parser2_hme_stage_tcam_only_2_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_2_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_2_PIPE1r} 69 70 #define TD3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0 {td3_exact_match_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r} 71 #define TD3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1 {td3_exact_match_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r} 72 73 #define TD3_FORWARDING_3_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_forwarding_3_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, FORWARDING_3_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_3_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 74 #define TD3_FORWARDING_3_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_forwarding_3_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, FORWARDING_3_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_3_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 75 76 #define TD3_CPU_COS_MAP_PIPE0 {td3_cpu_cos_map_pipe0_name, NO_MODE, NO_MODE_FIELD, CPU_COS_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_CAM_BIST_STATUS_PIPE0r} 77 #define TD3_CPU_COS_MAP_PIPE1 {td3_cpu_cos_map_pipe1_name, NO_MODE, NO_MODE_FIELD, CPU_COS_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_CAM_BIST_STATUS_PIPE1r} 78 79 #define TD3_IP_PARSER1_MICE_TCAM_1_PIPE0 {td3_ip_parser1_mice_tcam_1_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_MICE_CAM_BIST_CONFIG_1_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER1_MICE_TCAM_BIST_STATUS_1_PIPE0r} 80 #define TD3_IP_PARSER1_MICE_TCAM_1_PIPE1 {td3_ip_parser1_mice_tcam_1_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_MICE_CAM_BIST_CONFIG_1_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER1_MICE_TCAM_BIST_STATUS_1_PIPE1r} 81 82 #define TD3_EGR_PKT_FLOW_SELECT_TCAM_PIPE0 {td3_egr_pkt_flow_select_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_PKT_FLOW_SELECT_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, EGR_PKT_FLOW_SELECT_CAM_BIST_STATUS_PIPE0r} 83 #define TD3_EGR_PKT_FLOW_SELECT_TCAM_PIPE1 {td3_egr_pkt_flow_select_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_PKT_FLOW_SELECT_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, EGR_PKT_FLOW_SELECT_CAM_BIST_STATUS_PIPE1r} 84 85 #define TD3_MY_STATION_TCAM_PIPE0 {td3_my_station_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, IVP_MY_STATION_TCAM_1_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, IVP_MY_STATION_TCAM_1_BIST_STATUS_PIPE0r} 86 #define TD3_MY_STATION_TCAM_PIPE1 {td3_my_station_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, IVP_MY_STATION_TCAM_1_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, IVP_MY_STATION_TCAM_1_BIST_STATUS_PIPE1r} 87 88 #define TD3_IP_PARSER2_MICE_TCAM_0_PIPE0 {td3_ip_parser2_mice_tcam_0_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_MICE_CAM_BIST_CONFIG_0_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER2_MICE_TCAM_BIST_STATUS_0_PIPE0r} 89 #define TD3_IP_PARSER2_MICE_TCAM_0_PIPE1 {td3_ip_parser2_mice_tcam_0_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_MICE_CAM_BIST_CONFIG_0_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER2_MICE_TCAM_BIST_STATUS_0_PIPE1r} 90 91 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_4_PIPE0 {td3_ip_parser1_hme_stage_tcam_only_4_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_4_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_4_PIPE0r} 92 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_4_PIPE1 {td3_ip_parser1_hme_stage_tcam_only_4_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_4_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_4_PIPE1r} 93 94 #define TD3_EGR_ZONE_4_EDITOR_CONTROL_TCAM_PIPE0 {td3_egr_zone_4_editor_control_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0r} 95 #define TD3_EGR_ZONE_4_EDITOR_CONTROL_TCAM_PIPE1 {td3_egr_zone_4_editor_control_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1r} 96 97 #define TD3_FORWARDING_1_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_forwarding_1_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, FORWARDING_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_1_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 98 #define TD3_FORWARDING_1_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_forwarding_1_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, FORWARDING_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_1_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 99 100 #define TD3_DST_COMPRESSION_PIPE0 {td3_dst_compression_pipe0_name, NO_MODE, NO_MODE_FIELD, DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, DST_COMPRESSION_CAM_BIST_STATUS_PIPE0r} 101 #define TD3_DST_COMPRESSION_PIPE1 {td3_dst_compression_pipe1_name, NO_MODE, NO_MODE_FIELD, DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, DST_COMPRESSION_CAM_BIST_STATUS_PIPE1r} 102 103 #define TD3_VFP_TCAM_PIPE0 {td3_vfp_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE0r} 104 #define TD3_VFP_TCAM_PIPE1 {td3_vfp_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE1r} 105 106 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_2_PIPE0 {td3_ip_parser1_hme_stage_tcam_only_2_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_2_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_2_PIPE0r} 107 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_2_PIPE1 {td3_ip_parser1_hme_stage_tcam_only_2_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_2_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_2_PIPE1r} 108 109 #define TD3_L3_TUNNEL_PIPE0 {td3_l3_tunnel_pipe0_name, NO_MODE, NO_MODE_FIELD, L3_TUNNEL_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_TUNNEL_BIST_STATUS_PIPE0r} 110 #define TD3_L3_TUNNEL_PIPE1 {td3_l3_tunnel_pipe1_name, NO_MODE, NO_MODE_FIELD, L3_TUNNEL_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_TUNNEL_BIST_STATUS_PIPE1r} 111 112 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_1_PIPE0 {td3_ip_parser1_hme_stage_tcam_only_1_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_1_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_1_PIPE0r} 113 #define TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_1_PIPE1 {td3_ip_parser1_hme_stage_tcam_only_1_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_1_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_1_PIPE1r} 114 115 #define TD3_VLAN_SUBNET_PIPE0 {td3_vlan_subnet_pipe0_name, NO_MODE, NO_MODE_FIELD, VLAN_SUBNET_ONLY_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, VLAN_SUBNET_ONLY_BIST_STATUS_PIPE0r} 116 #define TD3_VLAN_SUBNET_PIPE1 {td3_vlan_subnet_pipe1_name, NO_MODE, NO_MODE_FIELD, VLAN_SUBNET_ONLY_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, VLAN_SUBNET_ONLY_BIST_STATUS_PIPE1r} 117 118 #define TD3_PKT_FLOW_SELECT_TCAM_0_PIPE0 {td3_pkt_flow_select_tcam_0_pipe0_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_0_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, PKT_FLOW_SELECT_TCAM_0_BIST_STATUS_PIPE0r} 119 #define TD3_PKT_FLOW_SELECT_TCAM_0_PIPE1 {td3_pkt_flow_select_tcam_0_pipe1_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_0_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, PKT_FLOW_SELECT_TCAM_0_BIST_STATUS_PIPE1r} 120 121 #define TD3_TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_tunnel_adapt_1_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 122 #define TD3_TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_tunnel_adapt_1_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 123 124 #define TD3_IFP_TCAM_POOL0_PIPE0 {td3_ifp_tcam_pool0_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL0_BIST_STATUS_PIPE0r} 125 #define TD3_IFP_TCAM_POOL1_PIPE0 {td3_ifp_tcam_pool1_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL1_BIST_STATUS_PIPE0r} 126 #define TD3_IFP_TCAM_POOL2_PIPE0 {td3_ifp_tcam_pool2_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL2_BIST_STATUS_PIPE0r} 127 #define TD3_IFP_TCAM_POOL3_PIPE0 {td3_ifp_tcam_pool3_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL3_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL3_BIST_STATUS_PIPE0r} 128 #define TD3_IFP_TCAM_POOL0_PIPE1 {td3_ifp_tcam_pool0_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL0_BIST_STATUS_PIPE1r} 129 #define TD3_IFP_TCAM_POOL1_PIPE1 {td3_ifp_tcam_pool1_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL1_BIST_STATUS_PIPE1r} 130 #define TD3_IFP_TCAM_POOL2_PIPE1 {td3_ifp_tcam_pool2_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL2_BIST_STATUS_PIPE1r} 131 #define TD3_IFP_TCAM_POOL3_PIPE1 {td3_ifp_tcam_pool3_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL3_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 3, IFP_TCAM_POOL3_BIST_STATUS_PIPE1r} 132 133 #define TD3_EFP_TCAM_POOL0_PIPE0 {td3_efp_tcam_pool0_pipe0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_0_CAM_BIST_STATUS_PIPE0r} 134 #define TD3_EFP_TCAM_POOL1_PIPE0 {td3_efp_tcam_pool1_pipe0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_1_CAM_BIST_STATUS_PIPE0r} 135 #define TD3_EFP_TCAM_POOL2_PIPE0 {td3_efp_tcam_pool2_pipe0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_2_CAM_BIST_STATUS_PIPE0r} 136 #define TD3_EFP_TCAM_POOL3_PIPE0 {td3_efp_tcam_pool3_pipe0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_3_CAM_BIST_STATUS_PIPE0r} 137 #define TD3_EFP_TCAM_POOL0_PIPE1 {td3_efp_tcam_pool0_pipe1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_0_CAM_BIST_STATUS_PIPE1r} 138 #define TD3_EFP_TCAM_POOL1_PIPE1 {td3_efp_tcam_pool1_pipe1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_1_CAM_BIST_STATUS_PIPE1r} 139 #define TD3_EFP_TCAM_POOL2_PIPE1 {td3_efp_tcam_pool2_pipe1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_2_CAM_BIST_STATUS_PIPE1r} 140 #define TD3_EFP_TCAM_POOL3_PIPE1 {td3_efp_tcam_pool3_pipe1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, EFP_SLICE_3_CAM_BIST_STATUS_PIPE1r} 141 142 #define TD3_TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_tunnel_adapt_4_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 143 #define TD3_TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_tunnel_adapt_4_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 144 145 #define TD3_EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_egr_adapt_2_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 146 #define TD3_EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_egr_adapt_2_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 147 148 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_0_PIPE0 {td3_ip_parser2_hme_stage_tcam_only_0_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_0_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_0_PIPE0r} 149 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_0_PIPE1 {td3_ip_parser2_hme_stage_tcam_only_0_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_0_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_0_PIPE1r} 150 151 #define TD3_EGR_QOS_CTRL_TCAM_PIPE0 {td3_egr_qos_ctrl_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_QOS_CTRL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_QOS_CTRL_CAM_BIST_STATUS_PIPE0r} 152 #define TD3_EGR_QOS_CTRL_TCAM_PIPE1 {td3_egr_qos_ctrl_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_QOS_CTRL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_QOS_CTRL_CAM_BIST_STATUS_PIPE1r} 153 154 #define TD3_IP_PARSER2_MICE_TCAM_1_PIPE0 {td3_ip_parser2_mice_tcam_1_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_MICE_CAM_BIST_CONFIG_1_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER2_MICE_TCAM_BIST_STATUS_1_PIPE0r} 155 #define TD3_IP_PARSER2_MICE_TCAM_1_PIPE1 {td3_ip_parser2_mice_tcam_1_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_MICE_CAM_BIST_CONFIG_1_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER2_MICE_TCAM_BIST_STATUS_1_PIPE1r} 156 157 #define TD3_EGR_ZONE_3_EDITOR_CONTROL_TCAM_PIPE0 {td3_egr_zone_3_editor_control_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0r} 158 #define TD3_EGR_ZONE_3_EDITOR_CONTROL_TCAM_PIPE1 {td3_egr_zone_3_editor_control_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1r} 159 160 #define TD3_IP_PARSER1_MICE_TCAM_0_PIPE0 {td3_ip_parser1_mice_tcam_0_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_MICE_CAM_BIST_CONFIG_0_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER1_MICE_TCAM_BIST_STATUS_0_PIPE0r} 161 #define TD3_IP_PARSER1_MICE_TCAM_0_PIPE1 {td3_ip_parser1_mice_tcam_0_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_MICE_CAM_BIST_CONFIG_0_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER1_MICE_TCAM_BIST_STATUS_0_PIPE1r} 162 163 #define TD3_L3_DEFIP_PIPE0 {td3_l3_defip_pipe0_name, NO_MODE, NO_MODE_FIELD, L3_DEFIP_ONLY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_ONLY_CAM_BIST_STATUS_PIPE0r} 164 #define TD3_L3_DEFIP_PIPE1 {td3_l3_defip_pipe1_name, NO_MODE, NO_MODE_FIELD, L3_DEFIP_ONLY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 16, L3_DEFIP_ONLY_CAM_BIST_STATUS_PIPE1r} 165 166 #define TD3_SRC_COMPRESSION_PIPE0 {td3_src_compression_pipe0_name, NO_MODE, NO_MODE_FIELD, SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, SRC_COMPRESSION_CAM_BIST_STATUS_PIPE0r} 167 #define TD3_SRC_COMPRESSION_PIPE1 {td3_src_compression_pipe1_name, NO_MODE, NO_MODE_FIELD, SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, SRC_COMPRESSION_CAM_BIST_STATUS_PIPE1r} 168 169 #define TD3_EGR_ZONE_1_EDITOR_CONTROL_TCAM_PIPE0 {td3_egr_zone_1_editor_control_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0r} 170 #define TD3_EGR_ZONE_1_EDITOR_CONTROL_TCAM_PIPE1 {td3_egr_zone_1_editor_control_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1r} 171 172 #define TD3_EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0 {td3_egr_adapt_1_logical_tbl_sel_tcam_pipe0_name, NO_MODE, NO_MODE_FIELD, EGR_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE0r} 173 #define TD3_EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE1 {td3_egr_adapt_1_logical_tbl_sel_tcam_pipe1_name, NO_MODE, NO_MODE_FIELD, EGR_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE1r} 174 175 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_1_PIPE0 {td3_ip_parser2_hme_stage_tcam_only_1_pipe0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_1_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_1_PIPE0r} 176 #define TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_1_PIPE1 {td3_ip_parser2_hme_stage_tcam_only_1_pipe1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_1_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_1_PIPE1r} 177 178 #define TD3_PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY_PIPE0 {td3_pkt_flow_select_tcam_2_entry_only_pipe0_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_STATUS_PIPE0r} 179 #define TD3_PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY_PIPE1 {td3_pkt_flow_select_tcam_2_entry_only_pipe1_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_STATUS_PIPE1r} 180 #define TD3_TOTAL_CAMBIST_COUNT 120 181 #define TD3_DONE_BIT_MASK 0x00000001 182 #define TD3_BIST_SUCCESS_MASK 0x00000002 183 184 static char td3_egr_zone_2_editor_control_tcam_pipe0_name[] = "EGR_ZONE_2_EDITOR_CONTROL_TCAM_PIPE0"; 185 static char td3_egr_zone_2_editor_control_tcam_pipe1_name[] = "EGR_ZONE_2_EDITOR_CONTROL_TCAM_PIPE1"; 186 187 static char td3_tunnel_adapt_3_logical_tbl_sel_tcam_pipe0_name[] = "TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM_PIPE0"; 188 static char td3_tunnel_adapt_3_logical_tbl_sel_tcam_pipe1_name[] = "TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM_PIPE1"; 189 190 static char td3_ip_parser2_hme_stage_tcam_only_3_pipe0_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_3_PIPE0"; 191 static char td3_ip_parser2_hme_stage_tcam_only_3_pipe1_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_3_PIPE1"; 192 193 static char td3_phb_select_tcam_pipe0_name[] = "PHB_SELECT_TCAM_PIPE0"; 194 static char td3_phb_select_tcam_pipe1_name[] = "PHB_SELECT_TCAM_PIPE1"; 195 196 static char td3_forwarding_2_logical_tbl_sel_tcam_pipe0_name[] = "FORWARDING_2_LOGICAL_TBL_SEL_TCAM_PIPE0"; 197 static char td3_forwarding_2_logical_tbl_sel_tcam_pipe1_name[] = "FORWARDING_2_LOGICAL_TBL_SEL_TCAM_PIPE1"; 198 199 static char td3_my_station_tcam_2_pipe0_name[] = "MY_STATION_TCAM_2_PIPE0"; 200 static char td3_my_station_tcam_2_pipe1_name[] = "MY_STATION_TCAM_2_PIPE1"; 201 202 static char td3_egr_field_extraction_profile_2_tcam_pipe0_name[] = "EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_PIPE0"; 203 static char td3_egr_field_extraction_profile_2_tcam_pipe1_name[] = "EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_PIPE1"; 204 205 static char td3_egr_field_extraction_profile_1_tcam_pipe0_name[] = "EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_PIPE0"; 206 static char td3_egr_field_extraction_profile_1_tcam_pipe1_name[] = "EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_PIPE1"; 207 208 static char td3_l2_user_entry_pipe0_name[] = "L2_USER_ENTRY_PIPE0"; 209 static char td3_l2_user_entry_pipe1_name[] = "L2_USER_ENTRY_PIPE1"; 210 211 static char td3_ip_parser1_hme_stage_tcam_only_3_pipe0_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_3_PIPE0"; 212 static char td3_ip_parser1_hme_stage_tcam_only_3_pipe1_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_3_PIPE1"; 213 214 static char td3_pkt_flow_select_tcam_1_pipe0_name[] = "PKT_FLOW_SELECT_TCAM_1_PIPE0"; 215 static char td3_pkt_flow_select_tcam_1_pipe1_name[] = "PKT_FLOW_SELECT_TCAM_1_PIPE1"; 216 217 static char td3_ip_parser2_hme_stage_tcam_only_4_pipe0_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_4_PIPE0"; 218 static char td3_ip_parser2_hme_stage_tcam_only_4_pipe1_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_4_PIPE1"; 219 220 static char td3_ip_parser1_hme_stage_tcam_only_0_pipe0_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_0_PIPE0"; 221 static char td3_ip_parser1_hme_stage_tcam_only_0_pipe1_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_0_PIPE1"; 222 223 static char td3_ip_multicast_tcam_pipe0_name[] = "IP_MULTICAST_TCAM_PIPE0"; 224 static char td3_ip_multicast_tcam_pipe1_name[] = "IP_MULTICAST_TCAM_PIPE1"; 225 226 static char td3_ip_parser0_hme_stage_tcam_only_0_pipe0_name[] = "IP_PARSER0_HME_STAGE_TCAM_ONLY_0_PIPE0"; 227 static char td3_ip_parser0_hme_stage_tcam_only_0_pipe1_name[] = "IP_PARSER0_HME_STAGE_TCAM_ONLY_0_PIPE1"; 228 229 static char td3_ifp_logical_table_select_pipe0_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE0"; 230 static char td3_ifp_logical_table_select_pipe1_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE1"; 231 232 static char td3_flex_rtag7_hash_tcam_only_pipe0_name[] = "FLEX_RTAG7_HASH_TCAM_ONLY_PIPE0"; 233 static char td3_flex_rtag7_hash_tcam_only_pipe1_name[] = "FLEX_RTAG7_HASH_TCAM_ONLY_PIPE1"; 234 235 static char td3_ing_snat_pipe0_name[] = "ING_SNAT_PIPE0"; 236 static char td3_ing_snat_pipe1_name[] = "ING_SNAT_PIPE1"; 237 238 static char td3_egr_zone_0_editor_control_tcam_pipe0_name[] = "EGR_ZONE_0_EDITOR_CONTROL_TCAM_PIPE0"; 239 static char td3_egr_zone_0_editor_control_tcam_pipe1_name[] = "EGR_ZONE_0_EDITOR_CONTROL_TCAM_PIPE1"; 240 241 static char td3_tunnel_adapt_2_logical_tbl_sel_tcam_pipe0_name[] = "TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0"; 242 static char td3_tunnel_adapt_2_logical_tbl_sel_tcam_pipe1_name[] = "TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE1"; 243 244 static char td3_ip_parser2_hme_stage_tcam_only_2_pipe0_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_2_PIPE0"; 245 static char td3_ip_parser2_hme_stage_tcam_only_2_pipe1_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_2_PIPE1"; 246 247 static char td3_exact_match_logical_table_select_pipe0_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0"; 248 static char td3_exact_match_logical_table_select_pipe1_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1"; 249 250 static char td3_forwarding_3_logical_tbl_sel_tcam_pipe0_name[] = "FORWARDING_3_LOGICAL_TBL_SEL_TCAM_PIPE0"; 251 static char td3_forwarding_3_logical_tbl_sel_tcam_pipe1_name[] = "FORWARDING_3_LOGICAL_TBL_SEL_TCAM_PIPE1"; 252 253 static char td3_cpu_cos_map_pipe0_name[] = "CPU_COS_MAP_PIPE0"; 254 static char td3_cpu_cos_map_pipe1_name[] = "CPU_COS_MAP_PIPE1"; 255 256 static char td3_ip_parser1_mice_tcam_1_pipe0_name[] = "IP_PARSER1_MICE_TCAM_1_PIPE0"; 257 static char td3_ip_parser1_mice_tcam_1_pipe1_name[] = "IP_PARSER1_MICE_TCAM_1_PIPE1"; 258 259 static char td3_egr_pkt_flow_select_tcam_pipe0_name[] = "EGR_PKT_FLOW_SELECT_TCAM_PIPE0"; 260 static char td3_egr_pkt_flow_select_tcam_pipe1_name[] = "EGR_PKT_FLOW_SELECT_TCAM_PIPE1"; 261 262 static char td3_my_station_tcam_pipe0_name[] = "MY_STATION_TCAM_PIPE0"; 263 static char td3_my_station_tcam_pipe1_name[] = "MY_STATION_TCAM_PIPE1"; 264 265 static char td3_ip_parser2_mice_tcam_0_pipe0_name[] = "IP_PARSER2_MICE_TCAM_0_PIPE0"; 266 static char td3_ip_parser2_mice_tcam_0_pipe1_name[] = "IP_PARSER2_MICE_TCAM_0_PIPE1"; 267 268 static char td3_ip_parser1_hme_stage_tcam_only_4_pipe0_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_4_PIPE0"; 269 static char td3_ip_parser1_hme_stage_tcam_only_4_pipe1_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_4_PIPE1"; 270 271 static char td3_egr_zone_4_editor_control_tcam_pipe0_name[] = "EGR_ZONE_4_EDITOR_CONTROL_TCAM_PIPE0"; 272 static char td3_egr_zone_4_editor_control_tcam_pipe1_name[] = "EGR_ZONE_4_EDITOR_CONTROL_TCAM_PIPE1"; 273 274 static char td3_forwarding_1_logical_tbl_sel_tcam_pipe0_name[] = "FORWARDING_1_LOGICAL_TBL_SEL_TCAM_PIPE0"; 275 static char td3_forwarding_1_logical_tbl_sel_tcam_pipe1_name[] = "FORWARDING_1_LOGICAL_TBL_SEL_TCAM_PIPE1"; 276 277 static char td3_dst_compression_pipe0_name[] = "DST_COMPRESSION_PIPE0"; 278 static char td3_dst_compression_pipe1_name[] = "DST_COMPRESSION_PIPE1"; 279 280 static char td3_vfp_tcam_pipe0_name[] = "VFP_TCAM_PIPE0"; 281 static char td3_vfp_tcam_pipe1_name[] = "VFP_TCAM_PIPE1"; 282 283 static char td3_ip_parser1_hme_stage_tcam_only_2_pipe0_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_2_PIPE0"; 284 static char td3_ip_parser1_hme_stage_tcam_only_2_pipe1_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_2_PIPE1"; 285 286 static char td3_l3_tunnel_pipe0_name[] = "L3_TUNNEL_PIPE0"; 287 static char td3_l3_tunnel_pipe1_name[] = "L3_TUNNEL_PIPE1"; 288 289 static char td3_ip_parser1_hme_stage_tcam_only_1_pipe0_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_1_PIPE0"; 290 static char td3_ip_parser1_hme_stage_tcam_only_1_pipe1_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_1_PIPE1"; 291 292 static char td3_vlan_subnet_pipe0_name[] = "VLAN_SUBNET_PIPE0"; 293 static char td3_vlan_subnet_pipe1_name[] = "VLAN_SUBNET_PIPE1"; 294 295 static char td3_pkt_flow_select_tcam_0_pipe0_name[] = "PKT_FLOW_SELECT_TCAM_0_PIPE0"; 296 static char td3_pkt_flow_select_tcam_0_pipe1_name[] = "PKT_FLOW_SELECT_TCAM_0_PIPE1"; 297 298 static char td3_tunnel_adapt_1_logical_tbl_sel_tcam_pipe0_name[] = "TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0"; 299 static char td3_tunnel_adapt_1_logical_tbl_sel_tcam_pipe1_name[] = "TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE1"; 300 301 static char td3_ifp_tcam_pool0_pipe0_name[] = "IFP_TCAM_POOL0_PIPE0"; 302 static char td3_ifp_tcam_pool1_pipe0_name[] = "IFP_TCAM_POOL1_PIPE0"; 303 static char td3_ifp_tcam_pool2_pipe0_name[] = "IFP_TCAM_POOL2_PIPE0"; 304 static char td3_ifp_tcam_pool3_pipe0_name[] = "IFP_TCAM_POOL3_PIPE0"; 305 static char td3_ifp_tcam_pool0_pipe1_name[] = "IFP_TCAM_POOL0_PIPE1"; 306 static char td3_ifp_tcam_pool1_pipe1_name[] = "IFP_TCAM_POOL1_PIPE1"; 307 static char td3_ifp_tcam_pool2_pipe1_name[] = "IFP_TCAM_POOL2_PIPE1"; 308 static char td3_ifp_tcam_pool3_pipe1_name[] = "IFP_TCAM_POOL3_PIPE1"; 309 310 static char td3_efp_tcam_pool0_pipe0_name[] = "EFP_TCAM_POOL0_PIPE0"; 311 static char td3_efp_tcam_pool1_pipe0_name[] = "EFP_TCAM_POOL1_PIPE0"; 312 static char td3_efp_tcam_pool2_pipe0_name[] = "EFP_TCAM_POOL2_PIPE0"; 313 static char td3_efp_tcam_pool3_pipe0_name[] = "EFP_TCAM_POOL3_PIPE0"; 314 static char td3_efp_tcam_pool0_pipe1_name[] = "EFP_TCAM_POOL0_PIPE1"; 315 static char td3_efp_tcam_pool1_pipe1_name[] = "EFP_TCAM_POOL1_PIPE1"; 316 static char td3_efp_tcam_pool2_pipe1_name[] = "EFP_TCAM_POOL2_PIPE1"; 317 static char td3_efp_tcam_pool3_pipe1_name[] = "EFP_TCAM_POOL3_PIPE1"; 318 319 static char td3_tunnel_adapt_4_logical_tbl_sel_tcam_pipe0_name[] = "TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM_PIPE0"; 320 static char td3_tunnel_adapt_4_logical_tbl_sel_tcam_pipe1_name[] = "TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM_PIPE1"; 321 322 static char td3_egr_adapt_2_logical_tbl_sel_tcam_pipe0_name[] = "EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0"; 323 static char td3_egr_adapt_2_logical_tbl_sel_tcam_pipe1_name[] = "EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE1"; 324 325 static char td3_ip_parser2_hme_stage_tcam_only_0_pipe0_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_0_PIPE0"; 326 static char td3_ip_parser2_hme_stage_tcam_only_0_pipe1_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_0_PIPE1"; 327 328 static char td3_egr_qos_ctrl_tcam_pipe0_name[] = "EGR_QOS_CTRL_TCAM_PIPE0"; 329 static char td3_egr_qos_ctrl_tcam_pipe1_name[] = "EGR_QOS_CTRL_TCAM_PIPE1"; 330 331 static char td3_ip_parser2_mice_tcam_1_pipe0_name[] = "IP_PARSER2_MICE_TCAM_1_PIPE0"; 332 static char td3_ip_parser2_mice_tcam_1_pipe1_name[] = "IP_PARSER2_MICE_TCAM_1_PIPE1"; 333 334 static char td3_egr_zone_3_editor_control_tcam_pipe0_name[] = "EGR_ZONE_3_EDITOR_CONTROL_TCAM_PIPE0"; 335 static char td3_egr_zone_3_editor_control_tcam_pipe1_name[] = "EGR_ZONE_3_EDITOR_CONTROL_TCAM_PIPE1"; 336 337 static char td3_ip_parser1_mice_tcam_0_pipe0_name[] = "IP_PARSER1_MICE_TCAM_0_PIPE0"; 338 static char td3_ip_parser1_mice_tcam_0_pipe1_name[] = "IP_PARSER1_MICE_TCAM_0_PIPE1"; 339 340 static char td3_l3_defip_pipe0_name[] = "L3_DEFIP_PIPE0"; 341 static char td3_l3_defip_pipe1_name[] = "L3_DEFIP_PIPE1"; 342 343 static char td3_src_compression_pipe0_name[] = "SRC_COMPRESSION_PIPE0"; 344 static char td3_src_compression_pipe1_name[] = "SRC_COMPRESSION_PIPE1"; 345 346 static char td3_egr_zone_1_editor_control_tcam_pipe0_name[] = "EGR_ZONE_1_EDITOR_CONTROL_TCAM_PIPE0"; 347 static char td3_egr_zone_1_editor_control_tcam_pipe1_name[] = "EGR_ZONE_1_EDITOR_CONTROL_TCAM_PIPE1"; 348 349 static char td3_egr_adapt_1_logical_tbl_sel_tcam_pipe0_name[] = "EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0"; 350 static char td3_egr_adapt_1_logical_tbl_sel_tcam_pipe1_name[] = "EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE1"; 351 352 static char td3_ip_parser2_hme_stage_tcam_only_1_pipe0_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_1_PIPE0"; 353 static char td3_ip_parser2_hme_stage_tcam_only_1_pipe1_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_1_PIPE1"; 354 355 static char td3_pkt_flow_select_tcam_2_entry_only_pipe0_name[] = "PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY_PIPE0"; 356 static char td3_pkt_flow_select_tcam_2_entry_only_pipe1_name[] = "PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY_PIPE1"; 357 358 static cambist_t td3_cambist_array[] = { 359 TD3_EGR_ZONE_2_EDITOR_CONTROL_TCAM_PIPE0, 360 TD3_EGR_ZONE_2_EDITOR_CONTROL_TCAM_PIPE1, 361 TD3_TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM_PIPE0, 362 TD3_TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM_PIPE1, 363 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_3_PIPE0, 364 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_3_PIPE1, 365 TD3_PHB_SELECT_TCAM_PIPE0, 366 TD3_PHB_SELECT_TCAM_PIPE1, 367 TD3_FORWARDING_2_LOGICAL_TBL_SEL_TCAM_PIPE0, 368 TD3_FORWARDING_2_LOGICAL_TBL_SEL_TCAM_PIPE1, 369 TD3_MY_STATION_TCAM_2_PIPE0, 370 TD3_MY_STATION_TCAM_2_PIPE1, 371 TD3_EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_PIPE0, 372 TD3_EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_PIPE1, 373 TD3_EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_PIPE0, 374 TD3_EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_PIPE1, 375 TD3_L2_USER_ENTRY_PIPE0, 376 TD3_L2_USER_ENTRY_PIPE1, 377 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_3_PIPE0, 378 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_3_PIPE1, 379 TD3_PKT_FLOW_SELECT_TCAM_1_PIPE0, 380 TD3_PKT_FLOW_SELECT_TCAM_1_PIPE1, 381 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_4_PIPE0, 382 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_4_PIPE1, 383 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_0_PIPE0, 384 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_0_PIPE1, 385 TD3_IP_MULTICAST_TCAM_PIPE0, 386 TD3_IP_MULTICAST_TCAM_PIPE1, 387 TD3_IP_PARSER0_HME_STAGE_TCAM_ONLY_0_PIPE0, 388 TD3_IP_PARSER0_HME_STAGE_TCAM_ONLY_0_PIPE1, 389 TD3_IFP_LOGICAL_TABLE_SELECT_PIPE0, 390 TD3_IFP_LOGICAL_TABLE_SELECT_PIPE1, 391 TD3_FLEX_RTAG7_HASH_TCAM_ONLY_PIPE0, 392 TD3_FLEX_RTAG7_HASH_TCAM_ONLY_PIPE1, 393 TD3_ING_SNAT_PIPE0, 394 TD3_ING_SNAT_PIPE1, 395 TD3_EGR_ZONE_0_EDITOR_CONTROL_TCAM_PIPE0, 396 TD3_EGR_ZONE_0_EDITOR_CONTROL_TCAM_PIPE1, 397 TD3_TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0, 398 TD3_TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE1, 399 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_2_PIPE0, 400 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_2_PIPE1, 401 TD3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0, 402 TD3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1, 403 TD3_FORWARDING_3_LOGICAL_TBL_SEL_TCAM_PIPE0, 404 TD3_FORWARDING_3_LOGICAL_TBL_SEL_TCAM_PIPE1, 405 TD3_CPU_COS_MAP_PIPE0, 406 TD3_CPU_COS_MAP_PIPE1, 407 TD3_IP_PARSER1_MICE_TCAM_1_PIPE0, 408 TD3_IP_PARSER1_MICE_TCAM_1_PIPE1, 409 TD3_EGR_PKT_FLOW_SELECT_TCAM_PIPE0, 410 TD3_EGR_PKT_FLOW_SELECT_TCAM_PIPE1, 411 TD3_MY_STATION_TCAM_PIPE0, 412 TD3_MY_STATION_TCAM_PIPE1, 413 TD3_IP_PARSER2_MICE_TCAM_0_PIPE0, 414 TD3_IP_PARSER2_MICE_TCAM_0_PIPE1, 415 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_4_PIPE0, 416 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_4_PIPE1, 417 TD3_EGR_ZONE_4_EDITOR_CONTROL_TCAM_PIPE0, 418 TD3_EGR_ZONE_4_EDITOR_CONTROL_TCAM_PIPE1, 419 TD3_FORWARDING_1_LOGICAL_TBL_SEL_TCAM_PIPE0, 420 TD3_FORWARDING_1_LOGICAL_TBL_SEL_TCAM_PIPE1, 421 TD3_DST_COMPRESSION_PIPE0, 422 TD3_DST_COMPRESSION_PIPE1, 423 TD3_VFP_TCAM_PIPE0, 424 TD3_VFP_TCAM_PIPE1, 425 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_2_PIPE0, 426 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_2_PIPE1, 427 TD3_L3_TUNNEL_PIPE0, 428 TD3_L3_TUNNEL_PIPE1, 429 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_1_PIPE0, 430 TD3_IP_PARSER1_HME_STAGE_TCAM_ONLY_1_PIPE1, 431 TD3_VLAN_SUBNET_PIPE0, 432 TD3_VLAN_SUBNET_PIPE1, 433 TD3_PKT_FLOW_SELECT_TCAM_0_PIPE0, 434 TD3_PKT_FLOW_SELECT_TCAM_0_PIPE1, 435 TD3_TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0, 436 TD3_TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE1, 437 TD3_IFP_TCAM_POOL0_PIPE0, 438 TD3_IFP_TCAM_POOL1_PIPE0, 439 TD3_IFP_TCAM_POOL2_PIPE0, 440 TD3_IFP_TCAM_POOL3_PIPE0, 441 TD3_IFP_TCAM_POOL0_PIPE1, 442 TD3_IFP_TCAM_POOL1_PIPE1, 443 TD3_IFP_TCAM_POOL2_PIPE1, 444 TD3_IFP_TCAM_POOL3_PIPE1, 445 TD3_EFP_TCAM_POOL0_PIPE0, 446 TD3_EFP_TCAM_POOL1_PIPE0, 447 TD3_EFP_TCAM_POOL2_PIPE0, 448 TD3_EFP_TCAM_POOL3_PIPE0, 449 TD3_EFP_TCAM_POOL0_PIPE1, 450 TD3_EFP_TCAM_POOL1_PIPE1, 451 TD3_EFP_TCAM_POOL2_PIPE1, 452 TD3_EFP_TCAM_POOL3_PIPE1, 453 TD3_TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM_PIPE0, 454 TD3_TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM_PIPE1, 455 TD3_EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0, 456 TD3_EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE1, 457 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_0_PIPE0, 458 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_0_PIPE1, 459 TD3_EGR_QOS_CTRL_TCAM_PIPE0, 460 TD3_EGR_QOS_CTRL_TCAM_PIPE1, 461 TD3_IP_PARSER2_MICE_TCAM_1_PIPE0, 462 TD3_IP_PARSER2_MICE_TCAM_1_PIPE1, 463 TD3_EGR_ZONE_3_EDITOR_CONTROL_TCAM_PIPE0, 464 TD3_EGR_ZONE_3_EDITOR_CONTROL_TCAM_PIPE1, 465 TD3_IP_PARSER1_MICE_TCAM_0_PIPE0, 466 TD3_IP_PARSER1_MICE_TCAM_0_PIPE1, 467 TD3_L3_DEFIP_PIPE0, 468 TD3_L3_DEFIP_PIPE1, 469 TD3_SRC_COMPRESSION_PIPE0, 470 TD3_SRC_COMPRESSION_PIPE1, 471 TD3_EGR_ZONE_1_EDITOR_CONTROL_TCAM_PIPE0, 472 TD3_EGR_ZONE_1_EDITOR_CONTROL_TCAM_PIPE1, 473 TD3_EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0, 474 TD3_EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE1, 475 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_1_PIPE0, 476 TD3_IP_PARSER2_HME_STAGE_TCAM_ONLY_1_PIPE1, 477 TD3_PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY_PIPE0, 478 TD3_PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY_PIPE1 479 };