regtest.c (127591B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Register Tests 8 */ 9 10 #include <shared/bsl.h> 11 12 #include <sal/types.h> 13 #include <shared/bsl.h> 14 #include <soc/defs.h> 15 #include <soc/debug.h> 16 #include <bcm/link.h> 17 #include <soc/register.h> 18 #include <appl/diag/diag.h> 19 #include <appl/diag/system.h> 20 #include <appl/diag/parse.h> 21 #include <appl/diag/test.h> 22 #include <bcm_int/control.h> 23 #ifdef BCM_TRIUMPH2_SUPPORT 24 #include <soc/triumph2.h> 25 #endif 26 #if defined(BCM_TRIUMPH3_SUPPORT) 27 #include <soc/triumph3.h> 28 #endif /* BCM_TRIUMPH3_SUPPORT */ 29 #ifdef BCM_KATANA_SUPPORT 30 #include <soc/katana.h> 31 #endif 32 #if defined(BCM_TOMAHAWK_SUPPORT) 33 #include <soc/tomahawk.h> 34 #endif /* BCM_TOMAHAWK_SUPPORT */ 35 #if defined(BCM_TRIDENT3_SUPPORT) 36 #include <soc/trident3.h> 37 #endif /* BCM_TRIDENT3_SUPPORT */ 38 39 #if defined(BCM_TOMAHAWK3_SUPPORT) 40 #include <soc/tomahawk3.h> 41 #endif /* BCM_TOMAHAWK_SUPPORT */ 42 43 #ifdef BCM_PETRA_SUPPORT 44 #include <soc/dpp/dpp_config_defs.h> 45 #include <soc/dpp/drv.h> 46 #endif 47 #if defined (BCM_DFE_SUPPORT) 48 #include <soc/dfe/cmn/dfe_drv.h> 49 #endif 50 #ifdef BCM_DNX_SUPPORT 51 #include <soc/dnx/drv.h> 52 #include <soc/dnx/legacy/drv.h> 53 #include <soc/dnx/pll/pll.h> 54 #include <bcm_int/dnx/init/init.h> 55 #include <soc/dnx/dnx_data/auto_generated/dnx_data_dram.h> 56 #include <soc/dnx/dnx_data/auto_generated/dnx_data_internal_dev_init.h> 57 #endif 58 #if defined(BCM_DNXF_SUPPORT) 59 #include <soc/dnxf/cmn/dnxf_drv.h> 60 #endif /*BCM_DFE_SUPPORT*/ 61 #ifdef BCM_TRIDENT2_SUPPORT 62 #include <soc/trident2.h> 63 #endif 64 #ifdef BCM_PETRA_SUPPORT 65 #include <appl/dpp/regs_filter.h> 66 #endif 67 #ifdef BCM_JERICHO_SUPPORT 68 #include <soc/dpp/JER/jer_mgmt.h> 69 #endif 70 71 72 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 73 74 75 STATIC int rval_test_proc(int unit, soc_regaddrinfo_t *ainfo, void *data); 76 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 77 static int rval_test_proc_above_64(int unit, soc_regaddrinfo_t *ainfo, void *data); 78 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 79 #ifdef BCM_DNX_SUPPORT 80 extern const dnx_init_step_t dnx_init_deinit_seq[]; 81 extern int test_dnxc_init_test(int unit, args_t *a, void *p); 82 extern int test_dnxc_init_test_init(int unit, args_t *a, void **p); 83 extern int test_dnxc_init_test_done(int unit, void *p); 84 uint32 dnx_tr1_enable[(SOC_MAX_NUM_DEVICES+31)/32] = {0}; 85 #endif 86 /* 87 * this is a special marker that is used in soc_reg_iterate() 88 * to indicate that no more variations of the current register 89 * should be iterated over. 90 */ 91 #define SOC_E_IGNORE -6000 92 #define MAX_NOF_BROADCAST_BLOCKS 40 93 #define BRDC_PREFIX_LEN 5 94 #if defined (BCM_PETRA_SUPPORT) 95 96 int 97 reg_contain_one_of_the_fields(int unit,uint32 reg,uint32 *fields) 98 { 99 100 int i; 101 for (i=0;fields[i]!=NUM_SOC_FIELD;i++) { 102 if (SOC_REG_FIELD_VALID(unit,reg,fields[i])) { 103 return 1; 104 } 105 } 106 return 0; 107 } 108 109 #endif 110 111 /* 112 * reg_test 113 * 114 * Read/write/addressing tests of all SOC internal register R/W bits 115 */ 116 STATIC int 117 try_reg_value(struct reg_data *rd, 118 soc_regaddrinfo_t *ainfo, 119 char *regname, 120 uint32 pattern, 121 uint64 mask) 122 { 123 uint64 pat64, rd64, wr64, rrd64, notmask; 124 char wr_str[20], mask_str[20], pat_str[20], rrd_str[20]; 125 int r, read_only_flag, write_only_flag; 126 127 COMPILER_64_ZERO(pat64); 128 COMPILER_64_ZERO(rd64); 129 COMPILER_64_ZERO(wr64); 130 COMPILER_64_ZERO(rrd64); 131 COMPILER_64_ZERO(notmask); 132 133 read_only_flag = SOC_REG_INFO(rd->unit, ainfo->reg).flags & SOC_REG_FLAG_RO ? 1 : 0; 134 write_only_flag = SOC_REG_INFO(rd->unit, ainfo->reg).flags & SOC_REG_FLAG_WO ? 1 : 0; 135 136 /* skip 64b registers in sim */ 137 if (SAL_BOOT_PLISIM) { 138 if (!SOC_IS_XGS(rd->unit) && !SOC_IS_JERICHO_2_A0(rd->unit) && SOC_REG_IS_64(rd->unit,ainfo->reg)) { 139 LOG_WARN(BSL_LS_APPL_COMMON, 140 (BSL_META("Skipping 64 bit %s register in sim\n"),regname)); 141 return 0; 142 } 143 } 144 { 145 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 146 if ((write_only_flag == 0) && ((r = soc_anyreg_read(rd->unit, ainfo, &rd64)) < 0)) { 147 LOG_ERROR(BSL_LS_APPL_COMMON, 148 (BSL_META("ERROR: read reg %s failed: %s\n"), 149 regname, soc_errmsg(r))); 150 return -1; 151 } 152 #ifdef BCM_APACHE_SUPPORT 153 /* Skipping CFAP registers because we do 154 constrained writes to these registers. 155 27th bit of AVS_REG_PMB_SLAVE_AVS_PWD_ACC_CONTROL register 156 is a DONE bit which needs to be cleared for every new run 157 */ 158 if (SOC_IS_APACHE(rd->unit)) { 159 if (sal_strncasecmp(regname, "CFAPCONFIG", 10) == 0) { 160 COMPILER_64_SET(mask, 0, 0); 161 } else if (sal_strncasecmp(regname, "CFAPFULLRESETPOINT", 18) == 0) { 162 COMPILER_64_SET(mask, 0, 0); 163 } else if (sal_strncasecmp(regname, "CFAPFULLSETPOINT", 16) == 0) { 164 COMPILER_64_SET(mask, 0, 0); 165 } else if (sal_strncasecmp(regname, "AVS_REG_PMB_SLAVE_AVS_PWD_ACC_CONTROL", 37) == 0){ 166 COMPILER_64_SET(mask, 0, 0); 167 } else if (sal_strncasecmp(regname, "MMU_TDM_DEBUG", 13) == 0) { 168 COMPILER_64_SET(mask, 0, 0); 169 } 170 171 } 172 #endif 173 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 174 } 175 176 COMPILER_64_SET(pat64, pattern, pattern); 177 COMPILER_64_AND(pat64, mask); 178 179 notmask = mask; 180 COMPILER_64_NOT(notmask); 181 182 wr64 = rd64; 183 COMPILER_64_AND(wr64, notmask); 184 COMPILER_64_OR(wr64, pat64); 185 186 format_uint64(wr_str, wr64); 187 format_uint64(mask_str, mask); 188 189 LOG_INFO(BSL_LS_APPL_TESTS, 190 (BSL_META("Write %s: value %s mask %s\n"), 191 regname, wr_str, mask_str)); 192 { 193 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 194 if ((read_only_flag == 0) && ((r = soc_anyreg_write(rd->unit, ainfo, wr64)) < 0)) { 195 LOG_ERROR(BSL_LS_APPL_COMMON, 196 (BSL_META("ERROR: write reg %s failed: %s wrote %s (mask %s)\n"), 197 regname, soc_errmsg(r), wr_str, mask_str)); 198 rd->error = r; 199 return -1; 200 } 201 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 202 } 203 204 { 205 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 206 if ((write_only_flag == 0) && ((r = soc_anyreg_read(rd->unit, ainfo, &rrd64)) < 0)) { 207 LOG_ERROR(BSL_LS_APPL_COMMON, 208 (BSL_META("ERROR: reread reg %s failed: %s after wrote %s (mask %s)\n"), 209 regname, soc_errmsg(r), wr_str, mask_str)); 210 rd->error = r; 211 return -1; 212 } 213 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 214 } 215 216 COMPILER_64_AND(rrd64, mask); 217 format_uint64(rrd_str, rrd64); 218 format_uint64(pat_str, pat64); 219 220 LOG_INFO(BSL_LS_APPL_TESTS, 221 (BSL_META("Read %s: value %s expecting %s\n"), 222 regname, rrd_str, pat_str)); 223 if (!(read_only_flag | write_only_flag) && COMPILER_64_NE(rrd64, pat64)) { 224 LOG_ERROR(BSL_LS_APPL_COMMON, 225 (BSL_META("ERROR %s: wrote %s read %s (mask %s)\n"), 226 regname, pat_str, rrd_str, mask_str)); 227 rd->error = SOC_E_FAIL; 228 } 229 230 /* put the register back the way we found it */ 231 { 232 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 233 if ((read_only_flag == 0) && ((r = soc_anyreg_write(rd->unit, ainfo, rd64)) < 0)) { 234 LOG_ERROR(BSL_LS_APPL_COMMON, 235 (BSL_META("ERROR: rewrite reg %s failed: %s\n"), 236 regname, soc_errmsg(r))); 237 rd->error = r; 238 return -1; 239 } 240 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 241 } 242 243 return 0; 244 } 245 246 /** 247 * since the nbih/nbil port macros block can be in reset mode 248 * we give the oportunity to skip them at tr1-8 249 * 250 * @author elem (16/12/2014) 251 * 252 * @param blocks 253 * 254 * @return uint8 255 */ 256 uint8 block_can_be_disabled(soc_block_type_t block) 257 { 258 switch (block) { 259 case SOC_BLK_KAPS: 260 case SOC_BLK_XLP: 261 case SOC_BLK_CLP: 262 case SOC_BLK_ILKN_PMH: 263 case SOC_BLK_ILKN_PML: 264 return 1; /* Skip these blocks can be in reset state*/ 265 default: 266 break; 267 } 268 return 0; 269 270 } 271 272 uint8 blocks_can_be_disabled(soc_block_types_t blocks) 273 { 274 soc_block_type_t block = SOC_REG_FIRST_BLK_TYPE(blocks); 275 return block_can_be_disabled(block); 276 277 } 278 279 280 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 281 /* 282 * Test a register above 64 bit 283 * If reg_data.flag can control a minimal test 284 */ 285 STATIC int 286 try_reg_above_64_value(struct reg_data *rd, 287 soc_regaddrinfo_t *ainfo, 288 char *regname, 289 uint32 pattern, 290 soc_reg_above_64_val_t mask) 291 { 292 char wr_str[256], mask_str[256], pat_str[256], rrd_str[256]; 293 int r; 294 soc_reg_above_64_val_t rd_val, pat, notmask, wr_val, rrd_val; 295 296 /* skip 64b registers in sim */ 297 if (SAL_BOOT_PLISIM) { 298 if (SOC_REG_IS_64(rd->unit,ainfo->reg)) { 299 LOG_WARN(BSL_LS_APPL_COMMON, 300 (BSL_META("Skipping 64 bit %s register in sim\n"),regname)); 301 return 0; 302 } 303 } 304 305 if ((r = soc_reg_above_64_get(rd->unit, ainfo->reg, (ainfo->port >= 0) ? ainfo->port : REG_PORT_ANY, ainfo->idx, rd_val)) < 0) { 306 LOG_ERROR(BSL_LS_APPL_COMMON, 307 (BSL_META("ERROR: read reg %s failed: %s\n"), 308 regname, soc_errmsg(r))); 309 return -1; 310 } 311 312 SOC_REG_ABOVE_64_SET_PATTERN(pat, pattern); 313 SOC_REG_ABOVE_64_AND(pat, mask); 314 315 SOC_REG_ABOVE_64_COPY(notmask, mask); 316 SOC_REG_ABOVE_64_NOT(notmask); 317 318 SOC_REG_ABOVE_64_COPY(wr_val, rd_val); 319 SOC_REG_ABOVE_64_AND(wr_val, notmask); 320 SOC_REG_ABOVE_64_OR(wr_val, pat); 321 322 format_long_integer(wr_str, wr_val, SOC_REG_ABOVE_64_MAX_SIZE_U32); 323 format_long_integer(mask_str, mask, SOC_REG_ABOVE_64_MAX_SIZE_U32); 324 325 LOG_INFO(BSL_LS_APPL_TESTS, 326 (BSL_META("Write %s: value %s mask %s\n"), 327 regname, wr_str, mask_str)); 328 329 if ((r = soc_reg_above_64_set(rd->unit, ainfo->reg, (ainfo->port >= 0) ? ainfo->port : REG_PORT_ANY, ainfo->idx, wr_val)) < 0) { 330 LOG_ERROR(BSL_LS_APPL_COMMON, 331 (BSL_META("ERROR: write reg %s failed: %s wrote %s (mask %s)\n"), 332 regname, soc_errmsg(r), wr_str, mask_str)); 333 rd->error = r; 334 return -1; 335 } 336 337 if ((r = soc_reg_above_64_get(rd->unit, ainfo->reg, (ainfo->port >= 0) ? ainfo->port : REG_PORT_ANY, ainfo->idx, rrd_val)) < 0) { 338 LOG_ERROR(BSL_LS_APPL_COMMON, 339 (BSL_META("ERROR: reread reg %s failed: %s after wrote %s (mask %s)\n"), 340 regname, soc_errmsg(r), wr_str, mask_str)); 341 rd->error = r; 342 return -1; 343 } 344 345 SOC_REG_ABOVE_64_AND(rrd_val, mask); 346 format_long_integer(rrd_str, rrd_val, SOC_REG_ABOVE_64_MAX_SIZE_U32); 347 format_long_integer(pat_str, pat, SOC_REG_ABOVE_64_MAX_SIZE_U32); 348 349 LOG_INFO(BSL_LS_APPL_TESTS, 350 (BSL_META("Read %s: value %s expecting %s\n"), 351 regname, rrd_str, pat_str)); 352 if (!SOC_REG_ABOVE_64_IS_EQUAL(rrd_val, pat)) { 353 LOG_ERROR(BSL_LS_APPL_COMMON, 354 (BSL_META("ERROR %s: wrote %s read %s (mask %s)\n"), 355 regname, pat_str, rrd_str, mask_str)); 356 rd->error = SOC_E_FAIL; 357 } 358 359 /* put the register back the way we found it */ 360 if ((r = soc_reg_above_64_set(rd->unit, ainfo->reg, (ainfo->port >= 0) ? ainfo->port : REG_PORT_ANY, ainfo->idx, rd_val)) < 0) { 361 LOG_ERROR(BSL_LS_APPL_COMMON, 362 (BSL_META("ERROR: rewrite reg %s failed: %s\n"), 363 regname, soc_errmsg(r))); 364 rd->error = r; 365 return -1; 366 } 367 368 return 0; 369 } 370 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 371 372 /* 373 * Test a register 374 * If reg_data.flag can control a minimal test 375 */ 376 STATIC int 377 try_reg(int unit, soc_regaddrinfo_t *ainfo, void *data) 378 { 379 struct reg_data *rd = data; 380 uint64 mask, mask2, mask3; 381 uint32 temp_mask_hi, temp_mask_lo; 382 char regname[80]; 383 uint32 access_flag = 0; 384 #ifdef BCM_HAWKEYE_SUPPORT 385 uint32 miscconfig; 386 int meter = 0; 387 #endif 388 389 #ifdef BCM_TOMAHAWK3_SUPPORT 390 soc_reg_t reg = ainfo->reg; 391 int acc_type = SOC_REG_ACC_TYPE(unit, reg); 392 uint16 dev_id; 393 uint8 rev_id; 394 395 soc_cm_get_id(unit, &dev_id, &rev_id); 396 if (dev_id == BCM56983_DEVICE_ID && 397 (acc_type == 2 || acc_type == 3 || acc_type == 4 || acc_type == 5)) { 398 return SOC_E_IGNORE; 399 } 400 #endif 401 if (!SOC_REG_IS_VALID(unit, ainfo->reg)) { 402 return SOC_E_IGNORE; /* invalid register */ 403 } 404 405 if (rd->flags & REGTEST_FLAG_ACCESS_ONLY) { 406 access_flag = 1; 407 } 408 409 if ((SOC_REG_INFO(unit, ainfo->reg).flags & 410 (SOC_REG_FLAG_RO | SOC_REG_FLAG_WO | SOC_REG_FLAG_INTERRUPT | SOC_REG_FLAG_GENERAL_COUNTER | SOC_REG_FLAG_SIGNAL)) && 411 !access_flag) { 412 return SOC_E_IGNORE; /* no testable bits */ 413 } 414 415 if (SOC_REG_INFO(unit, ainfo->reg).regtype == soc_portreg && !SOC_PORT_VALID(unit, ainfo->port)) { 416 return 0; /* skip invalid ports */ 417 } 418 419 #ifdef BCM_ENDURO_SUPPORT 420 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit) || SOC_IS_KATANA(unit)) { 421 if (ainfo->reg == OAM_SEC_NS_COUNTER_64r) { 422 LOG_WARN(BSL_LS_APPL_COMMON, 423 (BSL_META_U(unit, 424 "Skipping OAM_SEC_NS_COUNTER_64 register\n"))); 425 return 0; /* skip OAM_SEC_NS_COUNTER_64 register */ 426 } 427 } 428 #endif 429 #ifdef BCM_KATANA_SUPPORT 430 if (SOC_IS_KATANA(unit)) { 431 if ( !soc_feature(unit,soc_feature_ces) && (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_CES)) ) { 432 return 0; 433 } 434 if ( !soc_feature(unit,soc_feature_ddr3) && (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_CI)) ) { 435 return 0; 436 } 437 } 438 #endif 439 440 /* 441 * set mask to read-write bits fields 442 * (those that are not marked untestable, reserved, read-only, 443 * or write-only) 444 */ 445 if (rd->flags & REGTEST_FLAG_MASK64) { 446 mask = soc_reg64_datamask(unit, ainfo->reg, 0); 447 if (!access_flag) { 448 mask2 = soc_reg64_datamask(unit, ainfo->reg, SOCF_RES); 449 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_RO); 450 COMPILER_64_OR(mask2, mask3); 451 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_SIG); 452 COMPILER_64_OR(mask2, mask3); 453 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_WO); 454 COMPILER_64_OR(mask2, mask3); 455 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_INTR); 456 COMPILER_64_OR(mask2, mask3); 457 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_W1TC); 458 COMPILER_64_OR(mask2, mask3); 459 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_COR); 460 COMPILER_64_OR(mask2, mask3); 461 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_PUNCH); 462 COMPILER_64_OR(mask2, mask3); 463 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_WVTC); 464 COMPILER_64_OR(mask2, mask3); 465 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_RWBW); 466 COMPILER_64_OR(mask2, mask3); 467 468 COMPILER_64_NOT(mask2); 469 COMPILER_64_AND(mask, mask2); 470 } 471 } else { 472 473 volatile uint32 m32; 474 475 m32 = soc_reg_datamask(unit, ainfo->reg, 0); 476 if (!access_flag) { 477 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_RES); 478 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_RO); 479 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_WO); 480 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_W1TC); 481 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_COR); 482 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_SIG); 483 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_INTR); 484 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_PUNCH); 485 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_WVTC); 486 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_RWBW); 487 } 488 COMPILER_64_SET(mask, 0, m32); 489 490 } 491 492 /* if (mask == 0) { 493 return SOC_E_IGNORE;; 494 }*/ 495 COMPILER_64_TO_32_HI(temp_mask_hi,mask); 496 COMPILER_64_TO_32_LO(temp_mask_lo,mask); 497 498 if ((temp_mask_hi == 0) && (temp_mask_lo == 0)) { 499 return SOC_E_IGNORE; 500 } 501 502 #ifdef BCM_HAWKEYE_SUPPORT 503 if (SOC_IS_HAWKEYE(unit) && soc_feature(unit, soc_feature_eee)) { 504 if (ainfo->reg == EEE_DELAY_ENTRY_TIMERr) { 505 /* The register r/w test should skip bit20 for register 506 * EEE_DELAY_ENTRY_TIMER. 507 * Because bit20 is a constant value before H/W one second delay 508 * for EEE feature. 509 */ 510 COMPILER_64_SET(mask2, 0, ~0x100000); 511 COMPILER_64_AND(mask, mask2); 512 } 513 } 514 #endif /* BCM_HAWKEYE_SUPPORT */ 515 516 if (COMPILER_64_IS_ZERO(mask)) { 517 return SOC_E_IGNORE; /* no testable bits */ 518 } 519 520 /* 521 * Check if this register is actually implemented in HW for the 522 * specified port/cos. If so, the mask is adjusted for the 523 * specified port/cos based on what is acutually in HW. 524 */ 525 if (reg_mask_subset(unit, ainfo, &mask)) { 526 /* Skip this register. Returning SOC_E_NONE, instead of 527 * SOC_E_IGNORE since we may not want to skip this register 528 * all the time (only for certain ports/cos) 529 */ 530 return SOC_E_NONE; 531 } 532 533 { 534 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 535 soc_reg_sprint_addr(unit, regname, ainfo); 536 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 537 } 538 539 #ifdef BCM_HAWKEYE_SUPPORT 540 if (SOC_IS_HAWKEYE(unit) && (ainfo->reg != MISCCONFIGr)) { 541 if (READ_MISCCONFIGr(unit, &miscconfig) < 0) { 542 test_error(unit, "Miscconfig read failed\n"); 543 return SOC_E_IGNORE; 544 } 545 546 meter = soc_reg_field_get(unit, MISCCONFIGr, 547 miscconfig, METERING_CLK_ENf); 548 549 if(meter){ 550 soc_reg_field_set(unit, MISCCONFIGr, 551 &miscconfig, METERING_CLK_ENf, 0); 552 553 if (WRITE_MISCCONFIGr(unit, miscconfig) < 0) { 554 test_error(unit, "Miscconfig setting failed\n"); 555 return SOC_E_IGNORE; 556 } 557 } 558 } 559 #endif 560 561 /* 562 * minimal test 563 * just Fs and 5s 564 * only do first instance of each register 565 * (only first port, cos, array index, and/or block) 566 */ 567 if (rd->flags & REGTEST_FLAG_MINIMAL) { 568 if (try_reg_value(rd, ainfo, regname, 0xffffffff, mask) < 0) { 569 return SOC_E_IGNORE; 570 } 571 572 if (try_reg_value(rd, ainfo, regname, 0x55555555, mask) < 0) { 573 return SOC_E_IGNORE; 574 } 575 return SOC_E_IGNORE; /* skip other than first instance */ 576 } 577 578 /* 579 * full test 580 */ 581 if (try_reg_value(rd, ainfo, regname, 0x00000000, mask) < 0) { 582 return SOC_E_IGNORE; 583 } 584 585 if (try_reg_value(rd, ainfo, regname, 0xffffffff, mask) < 0) { 586 return SOC_E_IGNORE; 587 } 588 589 if (try_reg_value(rd, ainfo, regname, 0x55555555, mask) < 0) { 590 return SOC_E_IGNORE; 591 } 592 593 if (try_reg_value(rd, ainfo, regname, 0xaaaaaaaa, mask) < 0) { 594 return SOC_E_IGNORE; 595 } 596 597 #ifdef BCM_HAWKEYE_SUPPORT 598 if (SOC_IS_HAWKEYE(unit) && (ainfo->reg != MISCCONFIGr)) { 599 if (WRITE_MISCCONFIGr(unit, miscconfig) < 0) { 600 test_error(unit, "Miscconfig setting failed\n"); 601 return SOC_E_IGNORE; 602 } 603 } 604 #endif 605 606 return 0; 607 } 608 609 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 610 STATIC int 611 try_reg_above_64(int unit, soc_regaddrinfo_t *ainfo, void *data) 612 { 613 struct reg_data *rd = data; 614 char regname[80]; 615 soc_reg_above_64_val_t mask, mask2, mask3; 616 uint32 access_flag = 0; 617 618 if (!SOC_REG_IS_VALID(unit, ainfo->reg)) { 619 return SOC_E_IGNORE; /* invalid register */ 620 } 621 622 if (rd->flags & REGTEST_FLAG_ACCESS_ONLY) { 623 access_flag = 1; 624 } 625 626 if ((SOC_REG_INFO(unit, ainfo->reg).flags & 627 (SOC_REG_FLAG_RO | SOC_REG_FLAG_WO | SOC_REG_FLAG_INTERRUPT | SOC_REG_FLAG_GENERAL_COUNTER | SOC_REG_FLAG_SIGNAL)) && 628 !access_flag) { 629 return SOC_E_IGNORE; /* no testable bits */ 630 } 631 632 if(SOC_REG_IS_ABOVE_64(unit, ainfo->reg)) { 633 if(SOC_REG_ABOVE_64_INFO(unit, ainfo->reg).size + 2 > CMIC_SCHAN_WORDS(unit)) { 634 return SOC_E_IGNORE; /* size + header larget than CMIC buffer */ 635 } 636 } 637 638 if (SOC_REG_INFO(unit, ainfo->reg).regtype == soc_portreg && 639 !SOC_PORT_VALID(unit, ainfo->port)) { 640 return 0; /* skip invalid ports */ 641 } 642 643 /* 644 * set mask to read-write bits fields 645 * (those that are not marked untestable, reserved, read-only, 646 * or write-only) 647 */ 648 soc_reg_above_64_datamask(unit, ainfo->reg, 0, mask); 649 if (SOC_REG_ABOVE_64_IS_ZERO(mask)) { 650 return SOC_E_IGNORE; /* no testable bits */ 651 } 652 653 if(SOC_REG_IS_ABOVE_64(unit, ainfo->reg)) { 654 if(SOC_REG_ABOVE_64_INFO(unit, ainfo->reg).size + 2 > CMIC_SCHAN_WORDS(unit)) { 655 return SOC_E_IGNORE; /* size + header larget than CMIC buffer */ 656 } 657 } 658 659 soc_reg_sprint_addr(unit, regname, ainfo); 660 661 soc_reg_above_64_datamask(unit, ainfo->reg, 0, mask); 662 if (!access_flag) { 663 soc_reg_above_64_datamask(unit, ainfo->reg, SOCF_RES, mask2); 664 soc_reg_above_64_datamask(unit, ainfo->reg, SOCF_RO, mask3); 665 SOC_REG_ABOVE_64_OR(mask2, mask3); 666 soc_reg_above_64_datamask(unit, ainfo->reg, SOCF_SIG, mask3); 667 SOC_REG_ABOVE_64_OR(mask2, mask3); 668 soc_reg_above_64_datamask(unit, ainfo->reg, SOCF_WO,mask3); 669 SOC_REG_ABOVE_64_OR(mask2, mask3); 670 soc_reg_above_64_datamask(unit, ainfo->reg, SOCF_INTR,mask3); 671 SOC_REG_ABOVE_64_OR(mask2, mask3); 672 soc_reg_above_64_datamask(unit, ainfo->reg, SOCF_WVTC,mask3); 673 SOC_REG_ABOVE_64_OR(mask2, mask3); 674 675 SOC_REG_ABOVE_64_NOT(mask2); 676 SOC_REG_ABOVE_64_AND(mask, mask2); 677 } 678 679 if (SOC_REG_ABOVE_64_IS_ZERO(mask) == TRUE) { 680 return SOC_E_IGNORE; 681 } 682 683 /* 684 * minimal test 685 * just Fs and 5s 686 * only do first instance of each register 687 * (only first port, cos, array index, and/or block) 688 */ 689 if (rd->flags & REGTEST_FLAG_MINIMAL) { 690 if (try_reg_above_64_value(rd, ainfo, regname, 0xffffffff, mask) < 0) { 691 return SOC_E_IGNORE; 692 } 693 694 if (try_reg_above_64_value(rd, ainfo, regname, 0x55555555, mask) < 0) { 695 return SOC_E_IGNORE; 696 } 697 698 return SOC_E_IGNORE; /* skip other than first instance */ 699 } 700 701 /* 702 * full test 703 */ 704 if (try_reg_above_64_value(rd, ainfo, regname, 0x00000000, mask) < 0) { 705 return SOC_E_IGNORE; 706 } 707 708 if (try_reg_above_64_value(rd, ainfo, regname, 0xffffffff, mask) < 0) { 709 return SOC_E_IGNORE; 710 } 711 712 if (try_reg_above_64_value(rd, ainfo, regname, 0x55555555, mask) < 0) { 713 return SOC_E_IGNORE; 714 } 715 716 if (try_reg_above_64_value(rd, ainfo, regname, 0xaaaaaaaa, mask) < 0) { 717 return SOC_E_IGNORE; 718 } 719 720 return 0; 721 } 722 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 723 724 STATIC int 725 try_reg_dispatch(int unit, soc_regaddrinfo_t *ainfo, void *data) 726 { 727 #if defined (BCM_PETRA_SUPPORT) 728 reg_data_t *rd = data; 729 #endif /*BCM_PETRA_SUPPORT*/ 730 731 #if defined (BCM_DFE_SUPPORT) 732 if(SOC_IS_DFE(unit)) { 733 int rv; 734 int is_filtered = 0; 735 736 rv = MBCM_DFE_DRIVER_CALL(unit, mbcm_dfe_drv_test_reg_filter, (unit, ainfo->reg, &is_filtered)); 737 if (rv != SOC_E_NONE) { 738 return rv; 739 } 740 if (is_filtered) { 741 return SOC_E_IGNORE; 742 } 743 } 744 #endif /*BCM_DFE_SUPPORT*/ 745 #if defined (BCM_PETRA_SUPPORT) 746 if(SOC_IS_ARADPLUS_AND_BELOW(unit)) { 747 switch(ainfo->reg) { 748 case ECI_REG_0001r: 749 case EGQ_INDIRECT_COMMANDr: 750 return SOC_E_IGNORE; 751 default: 752 break; 753 } 754 } 755 if(SOC_IS_JERICHO(unit)) { 756 /* 757 * we skip on the following common regs after checking with noam halevi from the following reasons 758 * 1. XXX_ECC_INTERRUPT_REGISTER_TEST because that the test mask is vary from block to block biut since the register 759 * taken from common we cant know the actual size 760 * 761 * 2. XXX_INDIRECT_COMMAND since INDIRECT_COMMAND_COUNT change by the HW we cant count on what we wrote 762 * 763 * 3. XXX_INDIRECT_COMMAND_WR_DATA since length vary from block to block and its width is like the widest mem in a block 764 * we cant actually know how match bits is realy active for this register while its definition came from common 765 * and its 640 bits 766 */ 767 uint32 disallowed_fields[] = {INDIRECT_COMMAND_COUNTf,INDIRECT_COMMAND_WR_DATAf, INTERRUPT_REGISTER_TESTf,ECC_INTERRUPT_REGISTER_TESTf,NUM_SOC_FIELD}; 768 if (ainfo->reg < rd->start_from || ainfo->reg >rd->start_from + rd->count) { 769 return 1; 770 } 771 if (reg_contain_one_of_the_fields(unit,ainfo->reg,disallowed_fields)) { 772 return 1; 773 } 774 if (!(rd->flags & REGTEST_FLAG_INC_PORT_MACROS)) { 775 soc_block_types_t regblktype = SOC_REG_INFO(unit, ainfo->reg).block; 776 if (blocks_can_be_disabled(regblktype)) { 777 return 1; 778 } 779 780 } 781 782 switch(ainfo->reg) { 783 784 #if defined(PLISIM) 785 /* these global registers vary from block to block, making the expected value wrong */ 786 787 /* Writing to this register migth kill the core clock */ 788 case ECI_OGER_1000r: 789 /* some blocks don't have memories and therfore they don't have these common registers */ 790 case NBIH_ENABLE_DYNAMIC_MEMORY_ACCESSr: 791 case NBIL_ENABLE_DYNAMIC_MEMORY_ACCESSr: 792 case NBIH_INDIRECT_COMMAND_ADDRESSr: 793 case NBIL_INDIRECT_COMMAND_ADDRESSr: 794 case NBIH_INDIRECT_COMMAND_DATA_INCREMENTr: 795 case NBIL_INDIRECT_COMMAND_DATA_INCREMENTr: 796 case NBIH_INDIRECT_COMMAND_WIDE_MEMr: 797 case NBIL_INDIRECT_COMMAND_WIDE_MEMr: 798 case NBIH_INDIRECT_FORCE_BUBBLEr: 799 case NBIL_INDIRECT_FORCE_BUBBLEr: 800 801 /* Unknown errors */ 802 case CLPORT_SGNDET_EARLYCRSr: 803 case MACSEC_PROG_TX_CRCr: 804 case MAC_PFC_CTRLr: 805 case MAC_PFC_REFRESH_CTRLr: 806 case SFD_OFFSETr: 807 808 /* additional regs r/w test at tr 3 failed on emulation*/ 809 case IHB_INTERRUPT_MASK_REGISTERr: 810 case ILKN_PMH_ECC_INTERRUPT_REGISTER_TESTr: 811 case ILKN_PMH_INDIRECT_COMMAND_WR_DATAr: 812 case ILKN_PMH_INDIRECT_COMMANDr: 813 case ILKN_PMH_INTERRUPT_REGISTER_TESTr: 814 case ILKN_PML_ECC_INTERRUPT_REGISTER_TESTr: 815 case ILKN_PML_INDIRECT_COMMAND_WR_DATAr: 816 case ILKN_PML_INDIRECT_COMMANDr: 817 case ILKN_PML_INTERRUPT_REGISTER_TESTr: 818 case ILKN_SLE_RX_CFGr: 819 case ILKN_SLE_RX_DEBUG_0r: 820 case ILKN_SLE_RX_ERRINS_0r: 821 case ILKN_SLE_RX_LANEr: 822 case ILKN_SLE_RX_STATS_WT_ERR_HIGHr: 823 case ILKN_SLE_RX_STATS_WT_ERR_LOWr: 824 case ILKN_SLE_RX_STATS_WT_PARITYr: 825 case ILKN_SLE_RX_STATS_WT_PKT_LOWr: 826 case ILKN_SLE_TX_CFGr: 827 case ILKN_SLE_TX_DEBUG_0r: 828 case ILKN_SLE_TX_ERRINS_0r: 829 case ILKN_SLE_TX_LANEr: 830 case ILKN_SLE_TX_STATS_WT_ERR_HIGHr: 831 case ILKN_SLE_TX_STATS_WT_ERR_LOWr: 832 case ILKN_SLE_TX_STATS_WT_PARITYr: 833 case ILKN_SLE_TX_STATS_WT_PKT_LOWr: 834 835 case ILKN_SLE_RX_AFIFO_WMr: 836 case ILKN_SLE_RX_BURSTr: 837 case ILKN_SLE_RX_CAL_ACCr: 838 case ILKN_SLE_RX_CAL_INBAND_DYNr: 839 case ILKN_SLE_RX_CAL_INBANDr: 840 case ILKN_SLE_RX_CAL_OUTBAND_DYNr: 841 case ILKN_SLE_RX_CAL_OUTBANDr: 842 case ILKN_SLE_RX_CAL_WTr: 843 case ILKN_SLE_RX_CTLr: 844 case ILKN_SLE_RX_DEBUG_1r: 845 case ILKN_SLE_RX_DEBUG_2r: 846 case ILKN_SLE_RX_DEBUG_3r: 847 case ILKN_SLE_RX_DEBUG_HOLD_0r: 848 case ILKN_SLE_RX_DEBUG_HOLD_1r: 849 case ILKN_SLE_RX_DEBUG_HOLD_2r: 850 case ILKN_SLE_RX_DEBUG_HOLD_3r: 851 case ILKN_SLE_RX_ERRINS_1r: 852 case ILKN_SLE_RX_ERRINS_2r: 853 case ILKN_SLE_RX_ERRINS_3r: 854 case ILKN_SLE_RX_EXT_INT_2_ND_MASKr: 855 case ILKN_SLE_RX_EXT_INT_FORCEr: 856 case ILKN_SLE_RX_EXT_INT_MASKr: 857 case ILKN_SLE_RX_FCOB_RETRANSMIT_SLOT_DYr: 858 case ILKN_SLE_RX_FCOB_RETRANSMIT_SLOTr: 859 case ILKN_SLE_RX_INT_2_ND_MASKr: 860 case ILKN_SLE_RX_INT_FORCEr: 861 case ILKN_SLE_RX_INT_MASKr: 862 case ILKN_SLE_RX_LANE_2r: 863 case ILKN_SLE_RX_METAFRAMEr: 864 case ILKN_SLE_RX_REMAP_LANE_14_10r: 865 case ILKN_SLE_RX_REMAP_LANE_19_15r: 866 case ILKN_SLE_RX_REMAP_LANE_24_20r: 867 case ILKN_SLE_RX_REMAP_LANE_29_25r: 868 case ILKN_SLE_RX_REMAP_LANE_34_30r: 869 case ILKN_SLE_RX_REMAP_LANE_39_35r: 870 case ILKN_SLE_RX_REMAP_LANE_44_40r: 871 case ILKN_SLE_RX_REMAP_LANE_47_45r: 872 case ILKN_SLE_RX_REMAP_LANE_4_0r: 873 case ILKN_SLE_RX_REMAP_LANE_9_5r: 874 case ILKN_SLE_RX_RETRANSMIT_CONFIGr: 875 case ILKN_SLE_RX_RETRANSMIT_TIME_CONFIG_2r: 876 case ILKN_SLE_RX_RETRANSMIT_TIME_CONFIGr: 877 case ILKN_SLE_RX_SEGMENT_ENABLEr: 878 case ILKN_SLE_RX_SERDES_TEST_CNTLr: 879 case ILKN_SLE_RX_SERDES_TEST_PATTERNAr: 880 case ILKN_SLE_RX_SERDES_TEST_PATTERNBr: 881 case ILKN_SLE_RX_SERDES_TEST_PATTERNCr: 882 case ILKN_SLE_RX_STATS_ACCr: 883 case ILKN_SLE_RX_STATS_WT_BYTE_LOWr: 884 case ILKN_SLE_TX_AFIFO_WMr: 885 case ILKN_SLE_TX_BURSTr: 886 case ILKN_SLE_TX_CAL_ACCr: 887 case ILKN_SLE_TX_CAL_INBAND_DYNr: 888 case ILKN_SLE_TX_CAL_INBANDr: 889 case ILKN_SLE_TX_CAL_OUTBAND_DYNr: 890 case ILKN_SLE_TX_CAL_OUTBANDr: 891 case ILKN_SLE_TX_CAL_WTr: 892 case ILKN_SLE_TX_CTLr: 893 case ILKN_SLE_TX_DEBUG_1r: 894 case ILKN_SLE_TX_DEBUG_2r: 895 case ILKN_SLE_TX_DEBUG_3r: 896 case ILKN_SLE_TX_DEBUG_HOLD_0r: 897 case ILKN_SLE_TX_DEBUG_HOLD_1r: 898 case ILKN_SLE_TX_DEBUG_HOLD_2r: 899 case ILKN_SLE_TX_DEBUG_HOLD_3r: 900 case ILKN_SLE_TX_ERRINS_1r: 901 case ILKN_SLE_TX_ERRINS_2r: 902 case ILKN_SLE_TX_ERRINS_3r: 903 case ILKN_SLE_TX_FCOB_RETRANSMIT_SLOT_DYr: 904 case ILKN_SLE_TX_FCOB_RETRANSMIT_SLOTr: 905 case ILKN_SLE_TX_FIFO_CFGr: 906 case ILKN_SLE_TX_INT_2_ND_MASKr: 907 case ILKN_SLE_TX_INT_FORCEr: 908 case ILKN_SLE_TX_INT_MASKr: 909 case ILKN_SLE_TX_LANE_2r: 910 case ILKN_SLE_TX_METAFRAMEr: 911 case ILKN_SLE_TX_RATE_1r: 912 case ILKN_SLE_TX_REMAP_LANE_14_10r: 913 case ILKN_SLE_TX_REMAP_LANE_19_15r: 914 case ILKN_SLE_TX_REMAP_LANE_24_20r: 915 case ILKN_SLE_TX_REMAP_LANE_29_25r: 916 case ILKN_SLE_TX_REMAP_LANE_34_30r: 917 case ILKN_SLE_TX_REMAP_LANE_39_35r: 918 case ILKN_SLE_TX_REMAP_LANE_44_40r: 919 case ILKN_SLE_TX_REMAP_LANE_47_45r: 920 case ILKN_SLE_TX_REMAP_LANE_4_0r: 921 case ILKN_SLE_TX_REMAP_LANE_9_5r: 922 case ILKN_SLE_TX_RETRANSMIT_CONFIGr: 923 case ILKN_SLE_TX_SEGMENT_ENABLEr: 924 case ILKN_SLE_TX_SERDES_AFIFO_STALL_SELr: 925 case ILKN_SLE_TX_SERDES_TEST_CNTLr: 926 case ILKN_SLE_TX_SERDES_TEST_PATTERNAr: 927 case ILKN_SLE_TX_SERDES_TEST_PATTERNBr: 928 case ILKN_SLE_TX_SERDES_TEST_PATTERNCr: 929 case ILKN_SLE_TX_STATS_ACCr: 930 case ILKN_SLE_TX_STATS_WT_BYTE_LOWr: 931 932 933 case CFC_INTERRUPT_MASK_REGISTERr: /*tr3 emulation reg=CFC_INTERRUPT_MASK_REGISTERr,value=0x55501,expected0x55555*/ 934 935 936 #endif 937 /*Above registers only failed on emulation. Current only below registers failed on Jericho. Others should be tested.*/ 938 case EDB_PAR_ERR_INITIATEr: 939 case MESH_TOPOLOGY_GLOBAL_MEM_OPTIONSr: 940 case MESH_TOPOLOGY_RESERVED_MTCPr: 941 942 return SOC_E_IGNORE; 943 default: 944 break; 945 } 946 if (SOC_IS_JERICHO_PLUS_A0(unit)) { 947 switch(ainfo->reg) { 948 949 case EDB_INDIRECT_WR_MASKr: 950 case EGQ_INDIRECT_WR_MASKr: 951 case IHB_INDIRECT_WR_MASKr: 952 case KAPS_BBS_INDIRECT_WR_MASKr: 953 case PPDB_A_INDIRECT_WR_MASKr: 954 case PPDB_B_INDIRECT_WR_MASKr: 955 956 957 case IHP_REG_00A4r: 958 case IHP_REG_00A6r: 959 960 961 case IHP_ECC_ERR_1B_MONITOR_MEM_MASKr: 962 case IHP_ECC_ERR_2B_MONITOR_MEM_MASKr: 963 964 return SOC_E_IGNORE; 965 default: 966 break; 967 } 968 } 969 970 971 } 972 #endif 973 #ifdef BCM_DNXF_SUPPORT 974 if(SOC_IS_DNXF(unit)) { 975 if (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "AVS_") != NULL) { 976 return 1; /* Skip broadcast registers (sw only registers)*/ 977 } 978 switch(ainfo->reg) { 979 980 case ECI_INDIRECT_COMMANDr: 981 case FSRD_INDIRECT_COMMANDr: 982 case RTP_INDIRECT_COMMANDr: 983 /*SBUS last in chain*/ 984 case BRDC_CCH_SBUS_BROADCAST_IDr: 985 case BRDC_DCML_SBUS_BROADCAST_IDr: 986 case BRDC_LCM_SBUS_BROADCAST_IDr: 987 case BRDC_QRH_SBUS_BROADCAST_IDr: 988 /*the following registers are filtered temporarily- the length of these registers should be amended according to the block they are in 989 (need to be the longest line of a register that is RW instead of always 640 bit)*/ 990 case MCT_INDIRECT_COMMANDr: 991 case QRH_INDIRECT_COMMANDr: 992 case BRDC_DCML_INDIRECT_COMMANDr: 993 case BRDC_QRH_INDIRECT_COMMANDr: 994 case ECI_ECIC_BLOCKS_RESETr: 995 case ECI_MISC_PLL_0_CONFIGr: 996 case ECI_MISC_PLL_1_CONFIGr: 997 case ECI_MISC_PLL_2_CONFIGr: 998 case ECI_MISC_PLL_3_CONFIGr: 999 case FMAC_ECC_ERR_1B_MONITOR_MEM_MASKr: 1000 case FMAC_ECC_ERR_2B_MONITOR_MEM_MASKr: 1001 case FMAC_ECC_INTERRUPT_REGISTER_MASKr: 1002 case FMAC_FMAL_GENERAL_CONFIGURATIONr: 1003 case FMAC_FMAL_RX_GENERAL_CONFIGURATIONr: 1004 case FMAC_FMAL_STATISTICS_OUTPUT_CONTROLr: 1005 case FMAC_FMAL_TX_COMMA_BURST_CONFIGURATIONr: 1006 case FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATIONr: 1007 case FMAC_FMAL_TX_GENERAL_CONFIGURATIONr: 1008 case FMAC_FPS_CONFIGURATION_RX_SYNCr: 1009 case FMAC_INTERRUPT_MASK_REGISTERr: 1010 case FMAC_LEAKY_BUCKET_CONTROL_REGISTERr: 1011 case FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr: 1012 case FMAC_PAR_ERR_MEM_MASKr: 1013 case FMAC_RECEIVE_RESET_REGISTERr: 1014 case FMAC_FE_GLOBAL_GENERAL_CFG_1r: 1015 case FMAC_RSF_CONFIGURATIONr: 1016 case FMAC_TX_LANE_SWAP_0r: 1017 case FMAC_TX_LANE_SWAP_1r: 1018 case FMAC_TX_LANE_SWAP_2r: 1019 case FMAC_TX_LANE_SWAP_3r: 1020 case DCML_INDIRECT_COMMANDr: 1021 return 1; /* Skip these registers */ 1022 default: 1023 break; 1024 } 1025 } 1026 #endif 1027 1028 #ifdef BCM_DNX_SUPPORT 1029 if(SOC_IS_DNX(unit)) { 1030 if (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "AN_") != NULL) { 1031 return 1; /* Skip broadcast registers (sw only registers)*/ 1032 } 1033 if (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "BRDC_") != NULL) { 1034 return 1; /* Skip broadcast registers (sw only registers)*/ 1035 } 1036 if ((dnx_data_dev_init_general_access_only_get(unit) == 1) && (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "CDPORT_") != NULL)) { 1037 return 1; 1038 } 1039 switch(ainfo->reg) { 1040 1041 /*SBUS last in chain*/ 1042 case BDM_SBUS_BROADCAST_IDr: 1043 case CDUM_SBUS_BROADCAST_IDr: 1044 case CDU_SBUS_BROADCAST_IDr: 1045 case CFC_SBUS_BROADCAST_IDr: 1046 case CGM_SBUS_BROADCAST_IDr: 1047 case CRPS_SBUS_BROADCAST_IDr: 1048 case DDHA_SBUS_BROADCAST_IDr: 1049 case DDHB_SBUS_BROADCAST_IDr: 1050 case DDP_SBUS_BROADCAST_IDr: 1051 case DHC_SBUS_BROADCAST_IDr: 1052 case DQM_SBUS_BROADCAST_IDr: 1053 case ECGM_SBUS_BROADCAST_IDr: 1054 case ECI_SBUS_BROADCAST_IDr: 1055 case EDB_SBUS_BROADCAST_IDr: 1056 case EPNI_SBUS_BROADCAST_IDr: 1057 case EPRE_SBUS_BROADCAST_IDr: 1058 case EPS_SBUS_BROADCAST_IDr: 1059 case ERPP_SBUS_BROADCAST_IDr: 1060 case ETPPA_SBUS_BROADCAST_IDr: 1061 case ETPPB_SBUS_BROADCAST_IDr: 1062 case ETPPC_SBUS_BROADCAST_IDr: 1063 case EVNT_SBUS_BROADCAST_IDr: 1064 case FCR_SBUS_BROADCAST_IDr: 1065 case FCT_SBUS_BROADCAST_IDr: 1066 case FDA_SBUS_BROADCAST_IDr: 1067 case FDR_SBUS_BROADCAST_IDr: 1068 case FDTL_SBUS_BROADCAST_IDr: 1069 case FDT_SBUS_BROADCAST_IDr: 1070 case FMAC_SBUS_BROADCAST_IDr: 1071 case FQP_SBUS_BROADCAST_IDr: 1072 case FSRD_SBUS_BROADCAST_IDr: 1073 case HBC_SBUS_BROADCAST_IDr: 1074 case HBMC_SBUS_BROADCAST_IDr: 1075 case ILE_SBUS_BROADCAST_IDr: 1076 case IPPA_SBUS_BROADCAST_IDr: 1077 case IPPB_SBUS_BROADCAST_IDr: 1078 case IPPC_SBUS_BROADCAST_IDr: 1079 case IPPD_SBUS_BROADCAST_IDr: 1080 case IPPE_SBUS_BROADCAST_IDr: 1081 case IPPF_SBUS_BROADCAST_IDr: 1082 case IPS_SBUS_BROADCAST_IDr: 1083 case IPT_SBUS_BROADCAST_IDr: 1084 case IQM_SBUS_BROADCAST_IDr: 1085 case IRE_SBUS_BROADCAST_IDr: 1086 case ITPPD_SBUS_BROADCAST_IDr: 1087 case ITPP_SBUS_BROADCAST_IDr: 1088 case KAPS_SBUS_BROADCAST_IDr: 1089 case MACT_SBUS_BROADCAST_IDr: 1090 case MCP_SBUS_BROADCAST_IDr: 1091 case MDB_SBUS_BROADCAST_IDr: 1092 case MESH_TOPOLOGY_SBUS_BROADCAST_IDr: 1093 case MRPS_SBUS_BROADCAST_IDr: 1094 case MTM_SBUS_BROADCAST_IDr: 1095 case NMG_SBUS_BROADCAST_IDr: 1096 case OAMP_SBUS_BROADCAST_IDr: 1097 case OCB_SBUS_BROADCAST_IDr: 1098 case OLP_SBUS_BROADCAST_IDr: 1099 case PDM_SBUS_BROADCAST_IDr: 1100 case PEM_SBUS_BROADCAST_IDr: 1101 case PQP_SBUS_BROADCAST_IDr: 1102 case RQP_SBUS_BROADCAST_IDr: 1103 case RTP_SBUS_BROADCAST_IDr: 1104 case SCH_SBUS_BROADCAST_IDr: 1105 case SIF_SBUS_BROADCAST_IDr: 1106 case SPB_SBUS_BROADCAST_IDr: 1107 case SQM_SBUS_BROADCAST_IDr: 1108 case TCAM_SBUS_BROADCAST_IDr: 1109 case TDU_SBUS_BROADCAST_IDr: 1110 /*suspects */ 1111 case ECI_ECIC_MDIO_CONFIGr: 1112 case ECI_ECIC_MISC_RESETr: 1113 case ECI_BLOCKS_POWER_DOWNr: 1114 case ECI_BLOCKS_SBUS_RESETr: 1115 case ECI_BLOCKS_SOFT_INITr: 1116 case ECI_BLOCKS_SOFT_RESETr: 1117 /* Skipping indirrect command registers */ 1118 case CDU_INDIRECT_COMMANDr: 1119 case CDUM_INDIRECT_COMMANDr: 1120 case CFC_INDIRECT_COMMANDr: 1121 case CGM_INDIRECT_COMMANDr: 1122 case CRPS_INDIRECT_COMMANDr: 1123 case DDHA_INDIRECT_COMMANDr: 1124 case DDHB_INDIRECT_COMMANDr: 1125 case DHC_INDIRECT_COMMANDr: 1126 case DQM_INDIRECT_COMMANDr: 1127 case ECGM_INDIRECT_COMMANDr: 1128 case ECI_INDIRECT_COMMANDr: 1129 case EDB_INDIRECT_COMMANDr: 1130 case EPNI_INDIRECT_COMMANDr: 1131 case EPS_INDIRECT_COMMANDr: 1132 case ERPP_INDIRECT_COMMANDr: 1133 case ETPPA_INDIRECT_COMMANDr: 1134 case ETPPB_INDIRECT_COMMANDr: 1135 case ETPPC_INDIRECT_COMMANDr: 1136 case EVNT_INDIRECT_COMMANDr: 1137 case FCR_INDIRECT_COMMANDr: 1138 case FCT_INDIRECT_COMMANDr: 1139 case FDR_INDIRECT_COMMANDr: 1140 case FDT_INDIRECT_COMMANDr: 1141 case FQP_INDIRECT_COMMANDr: 1142 case FSRD_INDIRECT_COMMANDr: 1143 case HBC_INDIRECT_COMMANDr: 1144 case HBMC_INDIRECT_COMMANDr: 1145 case ILE_INDIRECT_COMMANDr: 1146 case IPPA_INDIRECT_COMMANDr: 1147 case IPPB_INDIRECT_COMMANDr: 1148 case IPPC_INDIRECT_COMMANDr: 1149 case IPPD_INDIRECT_COMMANDr: 1150 case IPPE_INDIRECT_COMMANDr: 1151 case IPPF_INDIRECT_COMMANDr: 1152 case IPS_INDIRECT_COMMANDr: 1153 case IPT_INDIRECT_COMMANDr: 1154 case IQM_INDIRECT_COMMANDr: 1155 case IRE_INDIRECT_COMMANDr: 1156 case ITPP_INDIRECT_COMMANDr: 1157 case ITPPD_INDIRECT_COMMANDr: 1158 case KAPS_INDIRECT_COMMANDr: 1159 case MACT_INDIRECT_COMMANDr: 1160 case MCP_INDIRECT_COMMANDr: 1161 case MDB_INDIRECT_COMMANDr: 1162 case MRPS_INDIRECT_COMMANDr: 1163 case MTM_INDIRECT_COMMANDr: 1164 case OAMP_INDIRECT_COMMANDr: 1165 case OCB_INDIRECT_COMMANDr: 1166 case OLP_INDIRECT_COMMANDr: 1167 case PEM_INDIRECT_COMMANDr: 1168 case PQP_INDIRECT_COMMANDr: 1169 case RQP_INDIRECT_COMMANDr: 1170 case RTP_INDIRECT_COMMANDr: 1171 case SCH_INDIRECT_COMMANDr: 1172 case SPB_INDIRECT_COMMANDr: 1173 case SQM_INDIRECT_COMMANDr: 1174 case TCAM_INDIRECT_COMMANDr: 1175 /* Skipping Gtimer registers */ 1176 case BDM_GTIMER_CONFIGURATIONr: 1177 case CDUM_GTIMER_CONFIGURATIONr: 1178 case CDU_GTIMER_CONFIGURATIONr: 1179 case CFC_GTIMER_CONFIGURATIONr: 1180 case CGM_GTIMER_CONFIGURATIONr: 1181 case CRPS_GTIMER_CONFIGURATIONr: 1182 case DDHA_GTIMER_CONFIGURATIONr: 1183 case DDHB_GTIMER_CONFIGURATIONr: 1184 case DDP_GTIMER_CONFIGURATIONr: 1185 case DHC_GTIMER_CONFIGURATIONr: 1186 case DQM_GTIMER_CONFIGURATIONr: 1187 case ECGM_GTIMER_CONFIGURATIONr: 1188 case ECI_GTIMER_CONFIGURATIONr: 1189 case EDB_GTIMER_CONFIGURATIONr: 1190 case EPNI_GTIMER_CONFIGURATIONr: 1191 case EPRE_GTIMER_CONFIGURATIONr: 1192 case EPS_GTIMER_CONFIGURATIONr: 1193 case ERPP_GTIMER_CONFIGURATIONr: 1194 case ETPPA_GTIMER_CONFIGURATIONr: 1195 case ETPPB_GTIMER_CONFIGURATIONr: 1196 case ETPPC_GTIMER_CONFIGURATIONr: 1197 case EVNT_GTIMER_CONFIGURATIONr: 1198 case FCR_GTIMER_CONFIGURATIONr: 1199 case FCT_GTIMER_CONFIGURATIONr: 1200 case FDA_GTIMER_CONFIGURATIONr: 1201 case FDR_GTIMER_CONFIGURATIONr: 1202 case FDTL_GTIMER_CONFIGURATIONr: 1203 case FDT_GTIMER_CONFIGURATIONr: 1204 case FMAC_GTIMER_CONFIGURATIONr: 1205 case FSRD_GTIMER_CONFIGURATIONr: 1206 case FQP_GTIMER_CONFIGURATIONr: 1207 case HBC_GTIMER_CONFIGURATIONr: 1208 case ILE_GTIMER_CONFIGURATIONr: 1209 case IPPA_GTIMER_CONFIGURATIONr: 1210 case IPPB_GTIMER_CONFIGURATIONr: 1211 case IPPC_GTIMER_CONFIGURATIONr: 1212 case IPPC_SPECIAL_CLOCK_CONTROLSr: 1213 case IPPD_GTIMER_CONFIGURATIONr: 1214 case IPPD_SPECIAL_CLOCK_CONTROLSr: 1215 case IPPE_GTIMER_CONFIGURATIONr: 1216 case IPPF_GTIMER_CONFIGURATIONr: 1217 case IPS_GTIMER_CONFIGURATIONr: 1218 case IPT_GTIMER_CONFIGURATIONr: 1219 case IQM_GTIMER_CONFIGURATIONr: 1220 case IRE_GTIMER_CONFIGURATIONr: 1221 case ITPPD_GTIMER_CONFIGURATIONr: 1222 case ITPP_GTIMER_CONFIGURATIONr: 1223 case KAPS_GTIMER_CONFIGURATIONr: 1224 case MACT_GTIMER_CONFIGURATIONr: 1225 case MCP_GTIMER_CONFIGURATIONr: 1226 case MDB_GTIMER_CONFIGURATIONr: 1227 case MESH_TOPOLOGY_GTIMER_CONFIGURATIONr: 1228 case MRPS_GTIMER_CONFIGURATIONr: 1229 case MTM_GTIMER_CONFIGURATIONr: 1230 case NMG_GTIMER_CONFIGURATIONr: 1231 case OAMP_GTIMER_CONFIGURATIONr: 1232 case OCB_GTIMER_CONFIGURATIONr: 1233 case OLP_GTIMER_CONFIGURATIONr: 1234 case PDM_GTIMER_CONFIGURATIONr: 1235 case PEM_GTIMER_CONFIGURATIONr: 1236 case PQP_GTIMER_CONFIGURATIONr: 1237 case RQP_GTIMER_CONFIGURATIONr: 1238 case RTP_GTIMER_CONFIGURATIONr: 1239 case SCH_GTIMER_CONFIGURATIONr: 1240 case SIF_GTIMER_CONFIGURATIONr: 1241 case SPB_GTIMER_CONFIGURATIONr: 1242 case SQM_GTIMER_CONFIGURATIONr: 1243 case TCAM_GTIMER_CONFIGURATIONr: 1244 case TDU_GTIMER_CONFIGURATIONr: 1245 /* Read only register and driven by another registers */ 1246 case MDB_ARM_KAPS_GLOBAL_EVENTr: 1247 case MDB_ARM_KAPS_IBC_COMMAND_WORDr: 1248 case MDB_ARM_KAPS_IBC_FIFO_CORRECTABLE_STATUSr: 1249 case MDB_ARM_KAPS_IBC_FIFO_UNCORRECTABLE_STATUSr: 1250 case MDB_ARM_KAPS_IBC_QUEUE_STATUSr: 1251 case MDB_ARM_KAPS_IBC_RESPONSE_DATAr: 1252 case MDB_ARM_KAPS_MEMORY_A_ERRORr: 1253 case MDB_ARM_KAPS_MEMORY_B_ERRORr: 1254 case MDB_ARM_KAPS_REVISIONr: 1255 case MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_0r: 1256 case MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_1r: 1257 case MDB_ARM_KAPS_R_5_CORE_MEM_CONTROLr: 1258 case MDB_ARM_KAPS_R_5_DAP_APB_CTRLr: 1259 case MDB_ARM_KAPS_R_5_DAP_APB_RDATAr: 1260 case MDB_ARM_KAPS_R_5_DEBUG_STATUSr: 1261 case MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0r: 1262 case MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1r: 1263 case MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_Ar: 1264 case MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_0r: 1265 case MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_1r: 1266 case MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_Ar: 1267 case MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_0r: 1268 case MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_1r: 1269 case MDB_ARM_KAPS_R_5_FIFO_MON_EVENTr: 1270 case MDB_ARM_KAPS_SEARCH_0_A_ERRORr: 1271 case MDB_ARM_KAPS_SEARCH_0_B_ERRORr: 1272 case MDB_ARM_KAPS_SEARCH_1_A_ERRORr: 1273 case MDB_ARM_KAPS_SEARCH_1_B_ERRORr: 1274 case MDB_ARM_KAPS_STATUS_CFIFOr: 1275 case MDB_ARM_KAPS_STATUS_RFIFOr: 1276 case MDB_ARM_REG_0000CF00r: 1277 case MDB_ARM_REG_0000EF00r: 1278 case HBMC_HBM_RESET_CONTROLr: 1279 case ILKN_X4_CONTROL0_ILKN_CONTROL0r: 1280 case CDPORT_INTR_STATUSr: 1281 case CDPORT_LINKSTATUS_DOWNr: 1282 case CDPORT_TSC_PLL_LOCK_STATUSr: 1283 case MAIN0_ECC_1B_ERR_INTERRUPT_ENr: 1284 case MAIN0_ECC_2B_ERR_INTERRUPT_ENr: 1285 case MAIN0_ECC_CORRUPT_CONTROL_0r: 1286 case MAIN0_ECC_CORRUPT_CONTROL_1r: 1287 case MAIN0_ECC_DISABLE_CONTROLr: 1288 case MAIN0_SETUPr: 1289 case MAIN0_TICK_CONTROL_0r: 1290 case MAIN0_TICK_CONTROL_1r: 1291 case MAIN0_TM_CONTROLr: 1292 case PKTGEN0_PCS_SEEDA0r: 1293 case PKTGEN0_PCS_SEEDA1r: 1294 case PKTGEN0_PCS_SEEDA2r: 1295 case PKTGEN0_PCS_SEEDA3r: 1296 case PKTGEN0_PCS_SEEDB0r: 1297 case PKTGEN0_PCS_SEEDB1r: 1298 case PKTGEN0_PCS_SEEDB2r: 1299 case PKTGEN0_PCS_SEEDB3r: 1300 case PKTGEN0_PKTGENCTRL1r: 1301 case PKTGEN0_PRTPCONTROLr: 1302 case PKTGEN1_ERRORMASK0r: 1303 case PKTGEN1_ERRORMASK1r: 1304 case PKTGEN1_ERRORMASK2r: 1305 case PKTGEN1_ERRORMASK3r: 1306 case PKTGEN1_ERRORMASK4r: 1307 case PKTGEN1_GLASTEST_CONTROLr: 1308 case PMD_X1_CONTROLr: 1309 case PMD_X1_FCLK_PERIODr: 1310 case PMD_X1_PM_TIMER_OFFSETr: 1311 case PMD_X4_CONTROLr: 1312 case PMD_X4_MODEr: 1313 case PMD_X4_OVERRIDEr: 1314 case PMD_X4_RX_FIXED_LATENCYr: 1315 case PMD_X4_TX_FIXED_LATENCYr: 1316 case PMD_X4_UI_VALUE_HIr: 1317 case PMD_X4_UI_VALUE_LOr: 1318 case RX_X1_CONTROL0_RS_FEC_CONFIGr: 1319 case RX_X1_CONTROL0_RX_LANE_SWAPr: 1320 case RX_X4_CONTROL0_DECODE_CONTROL_0r: 1321 case RX_X4_CONTROL0_PMA_CONTROL_0r: 1322 case RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0r: 1323 case RX_X4_CONTROL0_RS_FEC_TIMERr: 1324 case RX_X4_CONTROL0_RX_TS_CONTROLr: 1325 case RX_X4_FEC_CONTROL_FEC_0r: 1326 case RX_X4_FEC_CONTROL_FEC_1r: 1327 case RX_X4_FEC_CONTROL_FEC_2r: 1328 case RX_X4_STATUS1_RL_MODE_SW_CONTROLr: 1329 case SC_X1_CONTROL_PIPELINE_RESET_COUNTr: 1330 case SC_X1_CONTROL_TX_RESET_COUNTr: 1331 case SC_X4_CONTROL_CONTROLr: 1332 case SC_X4_CONTROL_SPARE0r: 1333 case SC_X4_CONTROL_SW_SPARE1r: 1334 case SYNCE_X4_FRACTIONAL_DIVr: 1335 case SYNCE_X4_INTEGER_DIVr: 1336 case TX_X1_CONTROL0_GLAS_TPMA_CONTROLr: 1337 case TX_X1_CONTROL0_TX_LANE_SWAPr: 1338 case TX_X4_CONTROL0_MISCr: 1339 case TX_X4_CONTROL0_RS_SYMBOLr: 1340 case TX_X4_CONTROL0_TX_TS_CONTROLr: 1341 case TX_X4_CONTROL0_ERROR_CONTROLr: 1342 return 1; /* Skip these registers */ 1343 default: 1344 break; 1345 } 1346 } 1347 #endif 1348 /* Not Supported for JR 2 B0 C-model */ 1349 #ifdef ADAPTER_SERVER_MODE 1350 if (SOC_IS_JERICHO_2_B(unit)) 1351 { 1352 switch (ainfo->reg) 1353 { 1354 case CFC_REG_00A4r: 1355 case CFC_REG_00A6r: 1356 case MESH_TOPOLOGY_SPECIAL_CLOCK_CONTROLSr: 1357 return 1; 1358 default: 1359 break; 1360 } 1361 } 1362 #endif 1363 1364 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 1365 1366 #ifdef BCM_SABER2_SUPPORT 1367 if (SOC_IS_SABER2(unit)) 1368 { 1369 switch (ainfo->reg) { 1370 case OAMP_INDIRECT_COMMAND_WR_DATAr: 1371 return SOC_E_IGNORE; 1372 default: 1373 break; 1374 } 1375 } 1376 #endif /* BCM_SABER2_SUPPORT */ 1377 #ifdef BCM_TOMAHAWK2_SUPPORT 1378 if (SOC_IS_TOMAHAWK2(unit)) { 1379 switch (ainfo->reg) { 1380 /* CONFIG_ERRORf: HW write */ 1381 /* MIB_RSC_DATA_HI_LVMf and MIB_RSC_DATA_LO_LVMf: Reserved */ 1382 case XLPORT_MIB_RSC_RAM_CONTROLr: 1383 case TOP_CORE_PLL0_CTRL_0r: 1384 case TOP_CORE_PLL0_CTRL_4r: 1385 case TOP_CORE_PLL0_CTRL_6r: 1386 case TOP_CORE_PLL0_CTRL_8r: 1387 case TOP_CORE_PLL0_CTRL_9r: 1388 return SOC_E_IGNORE; 1389 default: 1390 break; 1391 } 1392 } 1393 #endif /* BCM_TOMAHAWK2_SUPPORT */ 1394 1395 #ifdef BCM_TOMAHAWK3_SUPPORT 1396 if(SOC_IS_TOMAHAWK3(unit)) { 1397 switch(ainfo->reg) { 1398 /* This reg changes its states after de-assertion of 1399 reset so skipping this reg */ 1400 case MMU_RQE_INFOTBL_FP_INITr: 1401 /* Reserved fields in this reg */ 1402 case XLPORT_MIB_RSC_RAM_CONTROLr: 1403 /* These regs have hw_write fields */ 1404 case MMU_RQE_QUEUE_SNAPSHOT_ENr: 1405 case IDB_OBM_MONITOR_CONFIGr: 1406 case IDB_OBM_MONITOR_CONFIG_PIPE0r: 1407 case IDB_OBM_MONITOR_CONFIG_PIPE1r: 1408 case IDB_OBM_MONITOR_CONFIG_PIPE2r: 1409 case IDB_OBM_MONITOR_CONFIG_PIPE3r: 1410 case IDB_OBM_MONITOR_CONFIG_PIPE4r: 1411 case IDB_OBM_MONITOR_CONFIG_PIPE5r: 1412 case IDB_OBM_MONITOR_CONFIG_PIPE6r: 1413 case IDB_OBM_MONITOR_CONFIG_PIPE7r: 1414 /* This reg can pertain SW values only when 1415 MMU_INTFO_XPORT_BKP_HW_UPDATE_DIS reg is programmed. 1416 So, skippping it. */ 1417 case MMU_INTFO_TO_XPORT_BKPr: 1418 /* It has DONE field which is readonly . It gets set during the 1419 write operation and it timesout as the DONEf is still set */ 1420 case EGR_HW_RESET_CONTROL_1r: 1421 case EGR_HW_RESET_CONTROL_1_PIPE0r: 1422 case EGR_HW_RESET_CONTROL_1_PIPE1r: 1423 case EGR_HW_RESET_CONTROL_1_PIPE2r: 1424 case EGR_HW_RESET_CONTROL_1_PIPE3r: 1425 case EGR_HW_RESET_CONTROL_1_PIPE4r: 1426 case EGR_HW_RESET_CONTROL_1_PIPE5r: 1427 case EGR_HW_RESET_CONTROL_1_PIPE6r: 1428 case EGR_HW_RESET_CONTROL_1_PIPE7r: 1429 case CDMAC_RX_LSS_STATUSr: 1430 case DLB_ECMP_HW_RESET_CONTROLr: 1431 return SOC_E_IGNORE; 1432 default: 1433 break; 1434 } 1435 } 1436 #endif /* BCM_TOMAHAWK3_SUPPORT */ 1437 #ifdef BCM_HURRICANE3_SUPPORT 1438 if (soc_feature(unit, soc_feature_wh2)) { 1439 /* Skip CHIP_SBUS_CFG.pmq2 */ 1440 if (ainfo->reg == CHIP_SBUS_CFGr) { 1441 if (SOC_BLOCK_NUMBER(unit, ainfo->block) == 2) { 1442 return SOC_E_IGNORE; 1443 } 1444 } 1445 } 1446 #endif /* BCM_HURRICANE3_SUPPORT */ 1447 1448 if(SOC_BLOCK_IS(SOC_REG_INFO(unit, ainfo->reg).block, SOC_BLK_CCH)) { 1449 /* skip test for CANCUN CCH pseudo registers */ 1450 return SOC_E_IGNORE; 1451 } 1452 if(SOC_REG_IS_ABOVE_64(unit, ainfo->reg)) { 1453 return try_reg_above_64(unit, ainfo, data); 1454 } else 1455 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 1456 { /* To work on 64 AND '32' bits regs */ 1457 return try_reg(unit, ainfo, data); 1458 } 1459 } 1460 STATIC int 1461 rval_test_proc_dispatch(int unit, soc_regaddrinfo_t *ainfo, void *data) 1462 { 1463 1464 #ifdef BCM_TRIDENT3_SUPPORT 1465 if(SOC_BLOCK_IS(SOC_REG_INFO(unit, ainfo->reg).block, SOC_BLK_CCH)) { 1466 /* skip test for CCH pseudo registers */ 1467 return 0; 1468 } 1469 #endif /* BCM_TRIDENT3_SUPPORT */ 1470 1471 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 1472 if(SOC_REG_IS_ABOVE_64(unit, ainfo->reg)) { 1473 return rval_test_proc_above_64(unit, ainfo, data); 1474 } else 1475 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 1476 { /* To work on 64 AND '32' bits regs */ 1477 return rval_test_proc(unit, ainfo, data); 1478 } 1479 } 1480 1481 #ifdef BCM_SAND_SUPPORT 1482 /* 1483 * dDisable interrupts and counters for test (tr 3) 1484 */ 1485 int 1486 disable_intr_and_count_reg_test(int unit, args_t *a, void *pa) 1487 { 1488 int rv = 0; 1489 1490 bcm_switch_event_t switch_event; 1491 bcm_switch_event_control_t type; 1492 bcm_switch_service_config_t config; 1493 uint32 value; 1494 switch_event = BCM_SWITCH_EVENT_DEVICE_INTERRUPT; 1495 type.event_id = BCM_SWITCH_EVENT_CONTROL_ALL; 1496 type.index = 0; 1497 type.action = bcmSwitchEventMask; 1498 value = 1; 1499 bcm_switch_event_control_set(unit, switch_event, type, value); 1500 bcm_switch_service_config_t_init(&config); 1501 config.enabled = bcmServiceStateDisabled; 1502 bcm_switch_service_set(unit, bcmServiceCounterCollection, &config); 1503 1504 return rv; 1505 } 1506 #endif 1507 1508 /* 1509 * Register read/write test (tr 3) 1510 */ 1511 int 1512 reg_test(int unit, args_t *a, void *pa) 1513 { 1514 struct reg_data rd; 1515 int r=0; 1516 int rv = 0; 1517 char *s; 1518 #if defined(BCM_HAWKEYE_SUPPORT) || defined (BCM_ESW_SUPPORT) /* DPPCOMPILEENABLE */ 1519 uint32 tem; 1520 #endif /* BCM_HAWKEYE_SUPPORT || BCM_ESW_SUPPORT || DPPCOMPILEENABE */ 1521 #if defined(BCM_HURRICANE3_SUPPORT) 1522 int port; 1523 #endif 1524 #if defined(BCM_HURRICANE3_SUPPORT) 1525 int cosq, idx; 1526 #endif /* BCM_HURRICANE3_SUPPORT */ 1527 1528 COMPILER_REFERENCE(pa); 1529 1530 if (!SOC_UNIT_VALID(unit)) { 1531 return SOC_E_UNIT; 1532 } 1533 LOG_INFO(BSL_LS_APPL_TESTS, 1534 (BSL_META_U(unit, 1535 "Register read/write test\n"))); 1536 1537 rd.unit = unit; 1538 rd.error = SOC_E_NONE; 1539 rd.flags = 0; 1540 rd.start_from = 0; 1541 rd.count = NUM_SOC_REG; 1542 1543 if (a) 1544 { 1545 while ((s = ARG_GET(a)) != NULL) { 1546 if (sal_strcasecmp(s, "mini") == 0 || 1547 sal_strcasecmp(s, "minimal") == 0) { 1548 rd.flags |= REGTEST_FLAG_MINIMAL; 1549 continue; 1550 } 1551 if (sal_strcasecmp(s, "mask64") == 0 || 1552 sal_strcasecmp(s, "datamask64") == 0) { 1553 rd.flags |= REGTEST_FLAG_MASK64; 1554 continue; 1555 } 1556 if (sal_strcasecmp(s, "IncPm") == 0) { 1557 rd.flags |= REGTEST_FLAG_INC_PORT_MACROS; 1558 continue; 1559 } 1560 if (sal_strcasecmp(s, "StartFrom") == 0) { 1561 char *sf = ARG_GET(a); 1562 rd.start_from = sal_ctoi(sf,0); 1563 continue; 1564 } 1565 if (sal_strcasecmp(s, "RegsNo") == 0) { 1566 char *sf = ARG_GET(a); 1567 rd.count = sal_ctoi(sf,0); 1568 continue; 1569 } 1570 if (sal_strcasecmp(s, "AccessOnly") == 0) { 1571 rd.flags |= REGTEST_FLAG_ACCESS_ONLY; 1572 continue; 1573 } 1574 LOG_WARN(BSL_LS_APPL_COMMON, 1575 (BSL_META_U(unit, 1576 "WARNING: unknown argument '%s' ignored\n"), s)); 1577 } 1578 } 1579 1580 if (BCM_UNIT_VALID(unit)) { 1581 rv = bcm_linkscan_enable_set(unit, 0); /* disable linkscan */ 1582 if(rv != SOC_E_UNAVAIL) { /* if unavail - no need to disable */ 1583 BCM_IF_ERROR_RETURN(rv); 1584 } 1585 } 1586 1587 1588 #if defined(BCM_PETRA_SUPPORT) && defined(BCM_JERICHO_SUPPORT) 1589 if(!SAL_BOOT_PLISIM && SOC_IS_JERICHO_PLUS_ONLY(unit)) { 1590 jer_mgmt_pvt_monitor_correction_disable(unit); 1591 } 1592 #endif 1593 { 1594 #if defined (BCM_PETRA_SUPPORT) 1595 if (SOC_IS_ARAD(unit)) { 1596 soc_counter_stop(unit); 1597 if ((r = soc_dpp_device_reset(unit, SOC_DPP_RESET_MODE_REG_ACCESS, SOC_DPP_RESET_ACTION_INOUT_RESET)) < 0) { 1598 LOG_ERROR(BSL_LS_APPL_COMMON, (BSL_META_U(unit, "ERROR: Unable to reinit unit %d: %s\n"), unit, soc_errmsg(r))); 1599 goto done; 1600 } 1601 } else 1602 #endif 1603 #if defined(BCM_SAND_SUPPORT) 1604 if (SOC_IS_DNX(unit) || SOC_IS_DNXF(unit)) { 1605 soc_counter_stop(unit); 1606 sal_sleep(1); 1607 if (SOC_IS_DNXF(unit)) { 1608 if ((r = soc_device_reset(unit, SOC_SAND_RESET_MODE_REG_ACCESS, SOC_SAND_RESET_ACTION_INOUT_RESET)) < 0) { 1609 LOG_ERROR(BSL_LS_APPL_COMMON, 1610 (BSL_META_U(unit, 1611 "ERROR: Unable to reinit unit %d: %s\n"), unit, soc_errmsg(r))); 1612 rv = BCM_E_FAIL; 1613 goto done; 1614 } 1615 sal_sleep(1); 1616 } 1617 } else 1618 #endif 1619 #ifdef BCM_DFE_SUPPORT 1620 if (SOC_IS_DFE(unit)) 1621 { 1622 r = MBCM_DFE_DRIVER_CALL(unit, mbcm_dfe_drv_blocks_reset, (unit, 0 , NULL)); 1623 if (r != SOC_E_NONE) 1624 { 1625 LOG_ERROR(BSL_LS_APPL_COMMON, 1626 (BSL_META_U(unit, 1627 "ERROR: Unable to reinit unit %d: %s\n"), unit, soc_errmsg(r))); 1628 goto done; 1629 } 1630 } else 1631 #endif 1632 { 1633 if(!(SOC_IS_DNXF(unit) || SOC_IS_DNX(unit))) { 1634 if ((r = soc_reset_init(unit)) < 0) { 1635 LOG_ERROR(BSL_LS_APPL_COMMON, 1636 (BSL_META_U(unit, 1637 "ERROR: Unable to reset unit %d: %s\n"), 1638 unit, soc_errmsg(r))); 1639 goto done; 1640 } 1641 } 1642 } 1643 } 1644 1645 if (SOC_IS_HB_GW(unit) && soc_feature(unit, soc_feature_bigmac_rxcnt_bug)) { 1646 /* 1647 * We need to wait for auto-negotiation to complete to ensure 1648 * that the BigMAC Rx counters will respond correctly. 1649 */ 1650 sal_usleep(500000); 1651 } 1652 1653 /* When doing E2EFC register/memory read/write tests, it is strongly recommended to set this parity genrate 1654 * enable bit to 0. This will prevent hardware automatically overwritting the ECC and 1655 * parity field in E2EFC registers/memories contents and failing the tests. 1656 */ 1657 #if defined(BCM_HAWKEYE_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) /* DPPCOMPILEENABLE */ 1658 if (soc_reg_field_valid(unit, MISCCONFIGr, E2EFC_PARITY_GEN_ENf)) { 1659 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &tem)); 1660 soc_reg_field_set(unit, MISCCONFIGr, &tem, E2EFC_PARITY_GEN_ENf, 0); 1661 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, tem)); 1662 } else if (soc_reg_field_valid(unit, MISCCONFIGr, PARITY_CHECK_ENf)) { 1663 /* If there is no E2EFC_PARITY_GEN_EN field, 1664 * try to disable PARITY_ENABLE_EN 1665 */ 1666 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &tem)); 1667 soc_reg_field_set(unit, MISCCONFIGr, &tem, PARITY_CHECK_ENf, 0); 1668 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, tem)); 1669 } 1670 #endif /* DPPCOMPILEENABLE */ 1671 1672 /* When doing REMOTE_PFC_STATE register read/write tests, it is recommended to set 1673 * the REMOTE_PFC_XOFF_TC_TIME_OUT register to zero. 1674 * It will prevent the REMOTE_PFC_STATE register was modified by HW, 1675 * once the timeout event is happened. 1676 */ 1677 #if defined(BCM_HURRICANE3_SUPPORT) 1678 if (SOC_REG_IS_VALID(unit, REMOTE_PFC_STATEr)) { 1679 cosq = NUM_COS(unit); 1680 PBMP_ALL_ITER(unit, port) { 1681 for (idx = 0; idx < cosq; idx++) { 1682 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 1683 REMOTE_PFC_XOFF_TC_TIME_OUTr,port, idx, 0)); 1684 } 1685 } 1686 } 1687 #endif /* BCM_HURRICANE3_SUPPORT */ 1688 1689 #ifdef BCM_TRIUMPH3_SUPPORT 1690 if (SOC_IS_TRIUMPH3(unit)) { 1691 soc_port_t port; 1692 soc_port_t port_max = SOC_INFO(unit).cpu_hg_index; 1693 1694 /* Initialize the MMU port mapping so the backpressure 1695 * registers work properly. 1696 */ 1697 for (port = 0; port < port_max; port++) { 1698 SOC_IF_ERROR_RETURN 1699 (WRITE_MMU_TO_PHY_PORT_MAPPINGr(unit, port, port)); 1700 } 1701 1702 SOC_IF_ERROR_RETURN 1703 (WRITE_MMU_TO_PHY_PORT_MAPPINGr(unit, 0, 59)); 1704 SOC_IF_ERROR_RETURN 1705 (WRITE_MMU_TO_PHY_PORT_MAPPINGr(unit, 59, 0)); 1706 1707 /* Turn off the background MMU processes */ 1708 if ((rv = _soc_triumph3_mem_parity_control(unit, INVALIDm, 1709 SOC_BLOCK_ALL, FALSE)) < 0) { 1710 LOG_ERROR(BSL_LS_APPL_COMMON, 1711 (BSL_META_U(unit, 1712 "ERROR: Unable to stop HW updates on unit %d: %s\n"), 1713 unit, soc_errmsg(r))); 1714 goto done; 1715 } 1716 } else 1717 #endif /* BCM_TRIUMPH3_SUPPORT */ 1718 #ifdef BCM_APACHE_SUPPORT 1719 if (SOC_IS_APACHE(unit)) { 1720 /* Turn off the background h/w updates, enable cpu access */ 1721 if ((rv = soc_td2_reg_cpu_write_control(unit, TRUE)) < 0) { 1722 LOG_ERROR(BSL_LS_APPL_COMMON, 1723 (BSL_META_U(unit, 1724 "ERROR: Unable to stop HW updates on unit %d: %s\n"), 1725 unit, soc_errmsg(r))); 1726 goto done; 1727 } 1728 } else 1729 #endif /* BCM_APACHE_SUPPORT */ 1730 { 1731 #ifdef BCM_TOMAHAWK_SUPPORT 1732 if (SOC_IS_TOMAHAWKX(unit) && !SOC_IS_TOMAHAWK3(unit)) { 1733 /* Turn off the background h/w updates, enable cpu access */ 1734 if ((rv = soc_tomahawk_reg_cpu_write_control(unit, TRUE)) < 0) { 1735 LOG_ERROR(BSL_LS_SOC_COMMON, 1736 (BSL_META_U(unit, 1737 "ERROR: Unable to stop HW updates on unit %d: %s\n"), 1738 unit, soc_errmsg(r))); 1739 goto done; 1740 } 1741 } 1742 #endif 1743 #ifdef BCM_TOMAHAWK3_SUPPORT 1744 if (SOC_IS_TOMAHAWK3(unit)) { 1745 1746 if ((rv = soc_misc_init(unit)) < 0) { 1747 LOG_ERROR(BSL_LS_SOC_COMMON, 1748 (BSL_META_U(unit, 1749 "ERROR: Unable to stop HW updates on unit %d: %s\n"), 1750 unit, soc_errmsg(r))); 1751 goto done; 1752 } 1753 1754 /* Turn off the background h/w updates, enable cpu access */ 1755 if ((rv = soc_tomahawk3_reg_cpu_write_control(unit, TRUE)) < 0) { 1756 LOG_ERROR(BSL_LS_SOC_COMMON, 1757 (BSL_META_U(unit, 1758 "ERROR: Unable to stop HW updates on unit %d: %s\n"), 1759 unit, soc_errmsg(r))); 1760 goto done; 1761 } 1762 } 1763 #endif /* BCM_TOMAHAWK_SUPPORT */ 1764 #ifdef BCM_TRIDENT3_SUPPORT 1765 if (SOC_IS_TRIDENT3X(unit)) { 1766 /* Turn off the background h/w updates, enable cpu access */ 1767 if ((rv = soc_trident3_reg_cpu_write_control(unit, TRUE)) < 0) { 1768 LOG_ERROR(BSL_LS_SOC_COMMON, 1769 (BSL_META_U(unit, 1770 "ERROR: Unable to stop HW updates on unit %d: %s\n"), 1771 unit, soc_errmsg(r))); 1772 goto done; 1773 } 1774 } 1775 #endif /* BCM_TRIDENT3_SUPPORT */ 1776 1777 } 1778 1779 /* 1780 * If try_reg returns -1, there was a register access failure rather 1781 * than a bit error. 1782 * 1783 * If try_reg returns 0, then rd.error is -1 if there was a bit 1784 * error. 1785 */ 1786 #ifdef BCM_SHADOW_SUPPORT 1787 if (SOC_IS_SHADOW(unit)) { 1788 SOC_IF_ERROR_RETURN 1789 (soc_reg_field32_modify(unit, IARB_REGS_DEBUGr, REG_PORT_ANY, 1790 DEBUGf, 1)); 1791 SOC_IF_ERROR_RETURN 1792 (soc_reg_field32_modify(unit, IPARS_REGS_DEBUGr, REG_PORT_ANY, 1793 DEBUGf, 1)); 1794 SOC_IF_ERROR_RETURN 1795 (soc_reg_field32_modify(unit, IVLAN_REGS_DEBUGr, REG_PORT_ANY, 1796 DEBUGf, 1)); 1797 SOC_IF_ERROR_RETURN 1798 (soc_reg_field32_modify(unit, ISW1_REGS_DEBUGr, REG_PORT_ANY, 1799 DEBUGf, 1)); 1800 SOC_IF_ERROR_RETURN 1801 (soc_reg_field32_modify(unit, ISW2_REGS_DEBUGr, REG_PORT_ANY, 1802 DEBUGf, 1)); 1803 SOC_IF_ERROR_RETURN 1804 (soc_reg_field32_modify(unit, IL_DEBUG_CONFIGr, 9, 1805 IL_TREX2_DEBUG_LOCKf, 1)); 1806 SOC_IF_ERROR_RETURN 1807 (soc_reg_field32_modify(unit, IL_DEBUG_CONFIGr, 13, 1808 IL_TREX2_DEBUG_LOCKf, 1)); 1809 SOC_IF_ERROR_RETURN 1810 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1811 WRED_THD_1_ENABLE_ECCf, 0)); 1812 SOC_IF_ERROR_RETURN 1813 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1814 WRED_THD_0_ENABLE_ECCf, 0)); 1815 SOC_IF_ERROR_RETURN 1816 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1817 WRED_PORT_THD_0_ENABLE_ECCf, 0)); 1818 SOC_IF_ERROR_RETURN 1819 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1820 WRED_PORT_THD_1_ENABLE_ECCf, 0)); 1821 SOC_IF_ERROR_RETURN 1822 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1823 WRED_CFG_ENABLE_ECCf, 0)); 1824 SOC_IF_ERROR_RETURN 1825 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1826 WRED_PORT_CFG_ENABLE_ECCf, 0)); 1827 SOC_IF_ERROR_RETURN 1828 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1829 MTRO_SHAPE_G0_BUCKET_ENABLE_ECCf, 0)); 1830 SOC_IF_ERROR_RETURN 1831 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1832 MTRO_SHAPE_G0_CONFIG_ENABLE_ECCf, 0)); 1833 SOC_IF_ERROR_RETURN 1834 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1835 MTRO_SHAPE_G1_BUCKET_ENABLE_ECCf, 0)); 1836 SOC_IF_ERROR_RETURN 1837 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1838 MTRO_SHAPE_G1_CONFIG_ENABLE_ECCf, 0)); 1839 SOC_IF_ERROR_RETURN 1840 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1841 MTRO_SHAPE_G2_BUCKET_ENABLE_ECCf, 0)); 1842 SOC_IF_ERROR_RETURN 1843 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1844 MTRO_SHAPE_G2_CONFIG_ENABLE_ECCf, 0)); 1845 SOC_IF_ERROR_RETURN 1846 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1847 MTRO_SHAPE_G3_BUCKET_ENABLE_ECCf, 0)); 1848 SOC_IF_ERROR_RETURN 1849 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1850 MTRO_SHAPE_G3_CONFIG_ENABLE_ECCf, 0)); 1851 SOC_IF_ERROR_RETURN 1852 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1853 MTRO_CPU_PKT_ENABLE_ECCf, 0)); 1854 } 1855 #endif 1856 { 1857 #ifdef BCM_TRIDENT2_SUPPORT 1858 if (SOC_IS_TD2P_TT2P(unit)) { 1859 /* Turn off the background h/w updates, enable cpu access */ 1860 if ((rv = soc_td2_reg_cpu_write_control (unit, TRUE)) < 0) { 1861 LOG_ERROR(BSL_LS_APPL_COMMON, 1862 (BSL_META_U(unit, 1863 "ERROR: Unable to stop HW updates : %s\n"), 1864 soc_errmsg(r))); 1865 goto done; 1866 } 1867 } 1868 #endif /* BCM_TRIDENT2_SUPPORT */ 1869 } 1870 { 1871 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 1872 if (soc_reg_iterate(unit, try_reg_dispatch, &rd) < 0) { 1873 LOG_INFO(BSL_LS_APPL_TESTS, 1874 (BSL_META_U(unit, 1875 "Continuing test.\n"))); 1876 rv = 0; 1877 } else { 1878 rv = rd.error; 1879 } 1880 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 1881 } 1882 1883 #if defined (BCM_ESW_SUPPORT) 1884 /* Re-Enable Parity Gen */ 1885 if (soc_reg_field_valid(unit, MISCCONFIGr, E2EFC_PARITY_GEN_ENf)) { 1886 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &tem)); 1887 soc_reg_field_set(unit, MISCCONFIGr, &tem, E2EFC_PARITY_GEN_ENf, 1); 1888 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, tem)); 1889 } else if (soc_reg_field_valid(unit, MISCCONFIGr, PARITY_CHECK_ENf)) { 1890 /* Re-enable PARITY_ENABLE */ 1891 if (soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 1892 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &tem)); 1893 soc_reg_field_set(unit, MISCCONFIGr, &tem, PARITY_CHECK_ENf, 1); 1894 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, tem)); 1895 } 1896 } 1897 #endif 1898 1899 #ifdef BCM_TRIUMPH3_SUPPORT 1900 if (SOC_IS_TRIUMPH3(unit)) { 1901 if ((rv = _soc_triumph3_mem_parity_control(unit, INVALIDm, 1902 SOC_BLOCK_ALL, TRUE)) < 0) { 1903 LOG_ERROR(BSL_LS_APPL_COMMON, 1904 (BSL_META_U(unit, 1905 "ERROR: Unable to restart HW updates on unit %d: %s\n"), 1906 unit, soc_errmsg(r))); 1907 goto done; 1908 } 1909 } else 1910 #endif /* BCM_TRIUMPH3_SUPPORT */ 1911 #ifdef BCM_APACHE_SUPPORT 1912 if (SOC_IS_APACHE(unit)) { 1913 /* Turn on the background h/w updates, enable cpu access */ 1914 if ((rv = soc_td2_reg_cpu_write_control(unit, FALSE)) < 0) { 1915 LOG_ERROR(BSL_LS_APPL_COMMON, 1916 (BSL_META_U(unit, 1917 "ERROR: Unable to restart HW updates on unit %d: %s\n"), 1918 unit, soc_errmsg(r))); 1919 goto done; 1920 } 1921 } else 1922 #endif /* BCM_APACHE_SUPPORT */ 1923 { 1924 #ifdef BCM_TOMAHAWK_SUPPORT 1925 if (SOC_IS_TOMAHAWKX(unit) && !SOC_IS_TOMAHAWK3(unit)) { 1926 /* Turn off the background h/w updates, enable cpu access */ 1927 if ((rv = soc_tomahawk_reg_cpu_write_control(unit, FALSE)) < 0) { 1928 LOG_ERROR(BSL_LS_SOC_COMMON, 1929 (BSL_META_U(unit, 1930 "ERROR: Unable to stop HW updates on unit %d: %s\n"), 1931 unit, soc_errmsg(r))); 1932 goto done; 1933 } 1934 } 1935 #endif /* BCM_TOMAHAWK_SUPPORT */ 1936 } 1937 1938 done: 1939 #ifdef BCM_SHADOW_SUPPORT 1940 if (SOC_IS_SHADOW(unit)) { 1941 SOC_IF_ERROR_RETURN 1942 (soc_reg_field32_modify(unit, IARB_REGS_DEBUGr, REG_PORT_ANY, 1943 DEBUGf, 0)); 1944 SOC_IF_ERROR_RETURN 1945 (soc_reg_field32_modify(unit, IPARS_REGS_DEBUGr, REG_PORT_ANY, 1946 DEBUGf, 0)); 1947 SOC_IF_ERROR_RETURN 1948 (soc_reg_field32_modify(unit, IVLAN_REGS_DEBUGr, REG_PORT_ANY, 1949 DEBUGf, 0)); 1950 SOC_IF_ERROR_RETURN 1951 (soc_reg_field32_modify(unit, ISW1_REGS_DEBUGr, REG_PORT_ANY, 1952 DEBUGf, 0)); 1953 SOC_IF_ERROR_RETURN 1954 (soc_reg_field32_modify(unit, ISW2_REGS_DEBUGr, REG_PORT_ANY, 1955 DEBUGf, 0)); 1956 SOC_IF_ERROR_RETURN 1957 (soc_reg_field32_modify(unit, IL_DEBUG_CONFIGr, 9, 1958 IL_TREX2_DEBUG_LOCKf, 0)); 1959 SOC_IF_ERROR_RETURN 1960 (soc_reg_field32_modify(unit, IL_DEBUG_CONFIGr, 13, 1961 IL_TREX2_DEBUG_LOCKf, 0)); 1962 SOC_IF_ERROR_RETURN 1963 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1964 WRED_THD_1_ENABLE_ECCf, 1)); 1965 SOC_IF_ERROR_RETURN 1966 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1967 WRED_THD_0_ENABLE_ECCf, 1)); 1968 SOC_IF_ERROR_RETURN 1969 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1970 WRED_PORT_THD_0_ENABLE_ECCf, 1)); 1971 SOC_IF_ERROR_RETURN 1972 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1973 WRED_PORT_THD_1_ENABLE_ECCf, 1)); 1974 SOC_IF_ERROR_RETURN 1975 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1976 WRED_CFG_ENABLE_ECCf, 1)); 1977 SOC_IF_ERROR_RETURN 1978 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1979 WRED_PORT_CFG_ENABLE_ECCf, 1)); 1980 SOC_IF_ERROR_RETURN 1981 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1982 MTRO_SHAPE_G0_BUCKET_ENABLE_ECCf, 1)); 1983 SOC_IF_ERROR_RETURN 1984 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1985 MTRO_SHAPE_G0_CONFIG_ENABLE_ECCf, 1)); 1986 SOC_IF_ERROR_RETURN 1987 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1988 MTRO_SHAPE_G1_BUCKET_ENABLE_ECCf, 1)); 1989 SOC_IF_ERROR_RETURN 1990 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1991 MTRO_SHAPE_G1_CONFIG_ENABLE_ECCf, 1)); 1992 SOC_IF_ERROR_RETURN 1993 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1994 MTRO_SHAPE_G2_BUCKET_ENABLE_ECCf, 1)); 1995 SOC_IF_ERROR_RETURN 1996 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 1997 MTRO_SHAPE_G2_CONFIG_ENABLE_ECCf, 1)); 1998 SOC_IF_ERROR_RETURN 1999 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 2000 MTRO_SHAPE_G3_BUCKET_ENABLE_ECCf, 1)); 2001 SOC_IF_ERROR_RETURN 2002 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 2003 MTRO_SHAPE_G3_CONFIG_ENABLE_ECCf, 1)); 2004 SOC_IF_ERROR_RETURN 2005 (soc_reg_field32_modify(unit, MMU_ECC_DEBUG1r, REG_PORT_ANY, 2006 MTRO_CPU_PKT_ENABLE_ECCf, 1)); 2007 } 2008 #endif 2009 if (rv < 0) { 2010 test_error(unit, "Register read/write test failed\n"); 2011 return rv; 2012 } 2013 2014 return rv; 2015 } 2016 2017 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 2018 /* 2019 * rval_test 2020 * 2021 * Reset SOC and compare reset values of all SOC registers with regsfile 2022 */ 2023 2024 STATIC int 2025 rval_test_proc_above_64(int unit, soc_regaddrinfo_t *ainfo, void *data) 2026 { 2027 struct reg_data *rd = data; 2028 char buf[80]; 2029 soc_reg_above_64_val_t rmsk, rval, rrd_val; 2030 int r; 2031 char wr_str[256], mask_str[256], rval_str[256], rrd_str[256]; 2032 soc_reg_t reg; 2033 2034 reg = ainfo->reg; 2035 2036 2037 2038 SOC_REG_ABOVE_64_RST_VAL_GET(unit, reg, rval); 2039 SOC_REG_ABOVE_64_RST_MSK_GET(unit, reg, rmsk); 2040 SOC_REG_ABOVE_64_AND(rval, rmsk); 2041 2042 if (rval_test_skip_reg(unit, ainfo, rd)) { 2043 /* soc_reg_sprint_addr(unit, buf, ainfo); 2044 LOG_WARN(BSL_LS_APPL_COMMON, 2045 (BSL_META_U(unit, 2046 "Skipping register %s\n"), buf)); */ 2047 return 0; 2048 } 2049 2050 if (SOC_REG_ABOVE_64_IS_ZERO(rmsk)) { 2051 return 0; /* No reset value */ 2052 } 2053 2054 if(SOC_REG_IS_ABOVE_64(unit, ainfo->reg)) { 2055 if(SOC_REG_ABOVE_64_INFO(unit, ainfo->reg).size + 2 > CMIC_SCHAN_WORDS(unit)) { 2056 return SOC_E_IGNORE; /* size + header larget than CMIC buffer */ 2057 } 2058 } 2059 2060 soc_reg_sprint_addr(unit, buf, ainfo); 2061 2062 2063 if ((r = soc_reg_above_64_get(rd->unit, ainfo->reg, (ainfo->port >= 0) ? ainfo->port : REG_PORT_ANY, (SOC_REG_ARRAY(unit, reg) || SOC_REG_IS_ARRAY(unit, reg)) ? SOC_REG_INFO(unit, reg).first_array_index : 0, rrd_val)) < 0) { 2064 LOG_ERROR(BSL_LS_APPL_COMMON, 2065 (BSL_META_U(unit, 2066 "ERROR: reread reg %s failed: %s after wrote %s (mask %s)\n"), 2067 buf, soc_errmsg(r), wr_str, mask_str)); 2068 rd->error = SOC_E_FAIL; 2069 } 2070 2071 2072 SOC_REG_ABOVE_64_AND(rrd_val, rmsk); 2073 2074 format_long_integer(rrd_str, rrd_val, SOC_REG_ABOVE_64_MAX_SIZE_U32); 2075 format_long_integer(rval_str, rval, SOC_REG_ABOVE_64_MAX_SIZE_U32); 2076 format_long_integer(mask_str, rmsk, SOC_REG_ABOVE_64_MAX_SIZE_U32); 2077 2078 2079 if (!SOC_REG_ABOVE_64_IS_EQUAL(rrd_val, rval)) { 2080 LOG_ERROR(BSL_LS_APPL_COMMON, 2081 (BSL_META_U(unit, 2082 "ERROR %s: default %s read %s (mask %s)\n"), 2083 buf, rval_str, rrd_str, mask_str)); 2084 rd->error = SOC_E_FAIL; 2085 } 2086 2087 return 0; 2088 } 2089 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 2090 2091 /* 2092 * rval_test 2093 * 2094 * Reset SOC and compare reset values of all SOC registers with regsfile 2095 */ 2096 2097 STATIC int 2098 rval_test_proc(int unit, soc_regaddrinfo_t *ainfo, void *data) 2099 { 2100 struct reg_data *rd = data; 2101 char buf[80]; 2102 uint64 value, rmsk, rval, chk; 2103 char val_str[20], rmsk_str[20], rval_str[20]; 2104 int r; 2105 uint64 mask2,mask3; 2106 uint32 temp_mask_hi, temp_mask_lo; 2107 soc_reg_t reg; 2108 2109 reg = ainfo->reg; 2110 #ifdef BCM_TOMAHAWK3_SUPPORT 2111 { 2112 uint16 dev_id; 2113 uint8 rev_id; 2114 int acc_type = SOC_REG_ACC_TYPE(unit, reg); 2115 2116 soc_cm_get_id(unit, &dev_id, &rev_id); 2117 2118 if (dev_id == BCM56983_DEVICE_ID && 2119 (acc_type == 2 || acc_type == 3 || acc_type == 4 || acc_type == 5)) { 2120 return 0; 2121 } 2122 } 2123 #endif 2124 /* NOTE: This is experimental */ 2125 #ifdef BCM_TRIUMPH3_SUPPORT 2126 if (SOC_IS_TRIUMPH3(unit) && 2127 (reg == EGR_OUTER_TPIDr || reg == ING_MPLS_TPIDr || 2128 reg == ING_OUTER_TPIDr)) { 2129 reg = reg+ainfo->idx+1; 2130 } 2131 #endif 2132 SOC_REG_RST_MSK_GET(unit, reg, rmsk); 2133 2134 if (rval_test_skip_reg(unit, ainfo, rd)) { 2135 /* soc_reg_sprint_addr(unit, buf, ainfo); 2136 LOG_WARN(BSL_LS_APPL_COMMON, 2137 (BSL_META_U(unit, 2138 "Skipping register %s\n"), buf));*/ 2139 2140 return 0; 2141 } 2142 2143 #ifdef BCM_ENDURO_SUPPORT 2144 if (SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit)) { 2145 if (ainfo->reg == OAM_SEC_NS_COUNTER_64r) { 2146 LOG_WARN(BSL_LS_APPL_COMMON, 2147 (BSL_META_U(unit, 2148 "Skipping OAM_SEC_NS_COUNTER_64 register\n"))); 2149 return 0; /* skip OAM_SEC_NS_COUNTER_64 register */ 2150 } 2151 } 2152 #endif 2153 2154 #ifdef BCM_HAWKEYE_SUPPORT 2155 if (SOC_IS_HAWKEYE(unit)) { 2156 if (ainfo->reg == MAC_MODEr) { 2157 LOG_WARN(BSL_LS_APPL_COMMON, 2158 (BSL_META_U(unit, 2159 "Skipping MAC_MODE register\n"))); 2160 return 0; /* skip MAC_MODE register */ 2161 } 2162 } 2163 #endif 2164 #ifdef BCM_KATANA_SUPPORT 2165 if (SOC_IS_KATANA(unit)) { 2166 if ( !soc_feature(unit,soc_feature_ces) && (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_CES)) ) { 2167 return 0; 2168 } 2169 if ( !soc_feature(unit,soc_feature_ddr3) && (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_CI)) ) { 2170 return 0; 2171 } 2172 } 2173 #endif 2174 2175 #ifdef BCM_HURRICANE2_SUPPORT 2176 if (SOC_IS_HURRICANE2(unit)) { 2177 if (ainfo->reg == TOP_XG_PLL0_CTRL_3r) { 2178 LOG_WARN(BSL_LS_APPL_COMMON, 2179 (BSL_META_U(unit, 2180 "Skipping TOP_XG_PLL0_CTRL_3 register\n"))); 2181 return 0; 2182 } 2183 } 2184 #endif 2185 2186 if (SAL_BOOT_PLISIM) { 2187 if (!SOC_IS_XGS(rd->unit) && SOC_REG_IS_64(rd->unit,ainfo->reg)) { 2188 { 2189 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 2190 soc_reg_sprint_addr(unit, buf, ainfo); 2191 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 2192 } 2193 LOG_WARN(BSL_LS_APPL_COMMON, 2194 (BSL_META_U(unit, 2195 "Skipping 64 bit %s register in sim\n"),buf)); 2196 return 0; 2197 } 2198 } 2199 2200 if (SOC_IS_SAND(unit)) { /* NOTE: Without this check tr 1 breaks for all XGS chips */ 2201 if (rd->flags & REGTEST_FLAG_MASK64) { 2202 rmsk = soc_reg64_datamask(unit, ainfo->reg, 0); 2203 mask2 = soc_reg64_datamask(unit, ainfo->reg, SOCF_IGNORE_DEFAULT_TEST); 2204 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_WO); 2205 2206 COMPILER_64_OR(mask2, mask3); 2207 2208 /* mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_INTR); 2209 COMPILER_64_OR(mask2, mask3); 2210 2211 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_COR); 2212 COMPILER_64_OR(mask2, mask3); */ 2213 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_W1TC); 2214 COMPILER_64_OR(mask2, mask3); 2215 2216 mask3 = soc_reg64_datamask(unit, ainfo->reg, SOCF_SIG); 2217 COMPILER_64_OR(mask2, mask3); 2218 2219 COMPILER_64_NOT(mask2); 2220 COMPILER_64_AND(rmsk, mask2); 2221 2222 2223 } else { 2224 2225 volatile uint32 m32; 2226 2227 m32 = soc_reg_datamask(unit, ainfo->reg, 0); 2228 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_IGNORE_DEFAULT_TEST); 2229 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_WO); 2230 m32 &= ~soc_reg_datamask(unit, ainfo->reg, SOCF_SIG); 2231 2232 COMPILER_64_SET(rmsk, 0, m32); 2233 2234 } 2235 2236 COMPILER_64_TO_32_HI(temp_mask_hi,rmsk); 2237 COMPILER_64_TO_32_LO(temp_mask_lo,rmsk); 2238 2239 if ((temp_mask_hi == 0) && (temp_mask_lo == 0)) { 2240 return 0; 2241 } 2242 } 2243 2244 /* 2245 * Check if this register is actually implemented in HW for the 2246 * specified port/cos. If so, the mask is adjusted for the 2247 * specified port/cos based on what is acutually in HW. 2248 */ 2249 if (reg_mask_subset(unit, ainfo, &rmsk)) { 2250 return 0; 2251 } 2252 2253 if (COMPILER_64_IS_ZERO(rmsk)) { 2254 return 0; /* No reset value */ 2255 } 2256 2257 SOC_REG_RST_VAL_GET(unit, reg, rval); 2258 { 2259 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 2260 soc_reg_sprint_addr(unit, buf, ainfo); 2261 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 2262 } 2263 2264 { 2265 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 2266 if ((r = soc_anyreg_read(rd->unit, ainfo, &value)) < 0) { 2267 LOG_ERROR(BSL_LS_APPL_COMMON, 2268 (BSL_META_U(unit, 2269 "ERROR: read reg %s (0x%x) failed: %s\n"), 2270 buf, ainfo->addr, soc_errmsg(r))); 2271 rd->error = r; 2272 return -1; } 2273 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 2274 } 2275 2276 format_uint64(val_str, value); 2277 format_uint64(rmsk_str, rmsk); 2278 format_uint64(rval_str, rval); 2279 LOG_INFO(BSL_LS_APPL_TESTS, 2280 (BSL_META_U(unit, 2281 "Read %s: reset mask %s, reset value %s, read %s\n"), 2282 buf, rmsk_str, rval_str, val_str)); 2283 2284 /* Check reset value is correct */ 2285 COMPILER_64_ZERO(chk); 2286 COMPILER_64_ADD_64(chk, value); 2287 COMPILER_64_XOR(chk, rval); 2288 COMPILER_64_AND(chk, rmsk); 2289 2290 if (!COMPILER_64_IS_ZERO(chk)) { 2291 COMPILER_64_AND(rval, rmsk); 2292 format_uint64(rval_str, rval); 2293 COMPILER_64_AND(value, rmsk); 2294 format_uint64(val_str, value); 2295 LOG_ERROR(BSL_LS_APPL_COMMON, 2296 (BSL_META_U(unit, 2297 "ERROR: %s: expected %s, got %s, reset mask %s\n"), 2298 buf, rval_str, val_str, rmsk_str)); 2299 rd->error = SOC_E_FAIL; 2300 } 2301 2302 return 0; 2303 } 2304 2305 #ifdef BCM_DNX_SUPPORT 2306 static int tr1_init_callback(int unit) { 2307 reg_data_t rd; 2308 int rv = 0; 2309 rd.unit = unit; 2310 rd.error = SOC_E_NONE; 2311 rd.flags = 0; 2312 rd.start_from = 0; 2313 rd.count = NUM_SOC_REG; 2314 if (soc_reg_iterate(unit, rval_test_proc_dispatch, &rd) != 0) { 2315 rv = rd.error; 2316 if (rv < 0) 2317 { 2318 test_error(unit, "Register reset value test failed\n"); 2319 } 2320 } 2321 return rv; 2322 } 2323 #endif /* BCM_DNX_SUPPORT */ 2324 2325 /* 2326 * Register reset value test (tr 1) 2327 */ 2328 int 2329 rval_test(int unit, args_t *a, void *pa) 2330 { 2331 struct reg_data rd; 2332 int r, rv = -1; 2333 char *s; 2334 2335 COMPILER_REFERENCE(pa); 2336 2337 LOG_INFO(BSL_LS_APPL_TESTS, 2338 (BSL_META_U(unit, 2339 "Register reset value test\n"))); 2340 2341 rd.unit = unit; 2342 rd.error = SOC_E_NONE; 2343 rd.flags = 0; 2344 rd.start_from = 0; 2345 rd.count = NUM_SOC_REG; 2346 while ((s = ARG_GET(a)) != NULL) { 2347 if (sal_strcasecmp(s, "IncPm") == 0) { 2348 rd.flags |= REGTEST_FLAG_INC_PORT_MACROS; 2349 continue; 2350 } 2351 if (sal_strcasecmp(s, "StartFrom") == 0) { 2352 char *sf = ARG_GET(a); 2353 rd.start_from = sal_ctoi(sf,0); 2354 continue; 2355 } 2356 if (sal_strcasecmp(s, "RegsNo") == 0) { 2357 char *sf = ARG_GET(a); 2358 rd.count = sal_ctoi(sf,0); 2359 continue; 2360 } 2361 LOG_WARN(BSL_LS_APPL_COMMON, 2362 (BSL_META_U(unit, 2363 "WARNING: unknown argument '%s' ignored\n"), s)); 2364 } 2365 2366 if (!SOC_UNIT_VALID(unit)) { 2367 return SOC_E_UNIT; 2368 } 2369 /* if (!SOC_IS_ARAD(unit)) {*/ 2370 if (BCM_UNIT_VALID(unit)) { 2371 rv = bcm_linkscan_enable_set(unit, 0); /* disable linkscan */ 2372 if(rv != SOC_E_UNAVAIL) { /* if unavail - no need to disable */ 2373 BCM_IF_ERROR_RETURN(rv); 2374 } 2375 } 2376 /* } */ 2377 2378 #if defined(BCM_PETRA_SUPPORT) && defined(BCM_JERICHO_SUPPORT) 2379 if(!SAL_BOOT_PLISIM && SOC_IS_JERICHO_PLUS_ONLY(unit)) { 2380 jer_mgmt_pvt_monitor_correction_disable(unit); 2381 } 2382 #endif 2383 2384 #ifdef BCM_TRIUMPH2_SUPPORT 2385 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 2386 SOC_IS_VALKYRIE2(unit)) { 2387 soc_triumph2_pipe_mem_clear(unit); 2388 } 2389 #endif /* BCM_TRIUMPH2_SUPPORT */ 2390 { 2391 #if defined(BCM_DFE_SUPPORT) 2392 if (SOC_IS_FE1600(unit)) 2393 { 2394 soc_counter_stop(unit); 2395 sal_sleep(1); 2396 r = MBCM_DFE_DRIVER_CALL(unit, mbcm_dfe_drv_blocks_reset, (unit, 0 , NULL)); 2397 if (r != SOC_E_NONE) 2398 { 2399 LOG_ERROR(BSL_LS_APPL_COMMON, 2400 (BSL_META_U(unit, 2401 "ERROR: Unable to reinit unit %d: %s\n"), unit, soc_errmsg(r))); 2402 goto done; 2403 } 2404 sal_sleep(1); 2405 } else 2406 #endif 2407 #if defined(BCM_DFE_SUPPORT) || defined(BCM_PETRA_SUPPORT) 2408 if (SOC_IS_DFE(unit) || SOC_IS_ARAD(unit)) 2409 { 2410 soc_counter_stop(unit); 2411 sal_sleep(1); 2412 if ((r = soc_device_reset(unit, SOC_DCMN_RESET_MODE_REG_ACCESS, SOC_DCMN_RESET_ACTION_INOUT_RESET)) < 0) { 2413 LOG_ERROR(BSL_LS_APPL_COMMON, 2414 (BSL_META_U(unit, 2415 "ERROR: Unable to reinit unit %d: %s\n"), unit, soc_errmsg(r))); 2416 rv = BCM_E_FAIL; 2417 goto done; 2418 } 2419 sal_sleep(1); 2420 2421 } else 2422 #endif 2423 #if defined(BCM_SAND_SUPPORT) 2424 if (SOC_IS_DNX(unit) || SOC_IS_DNXF(unit)) { 2425 soc_counter_stop(unit); 2426 sal_sleep(1); 2427 if (SOC_IS_DNXF(unit)){ 2428 if ((r = soc_device_reset(unit, SOC_SAND_RESET_MODE_REG_ACCESS, SOC_SAND_RESET_ACTION_INOUT_RESET)) < 0) { 2429 LOG_ERROR(BSL_LS_APPL_COMMON, 2430 (BSL_META_U(unit, 2431 "ERROR: Unable to reinit unit %d: %s\n"), unit, soc_errmsg(r))); 2432 rv = BCM_E_FAIL; 2433 goto done; 2434 } 2435 sal_sleep(1); 2436 } 2437 #ifdef BCM_DNX_SUPPORT 2438 if (SOC_IS_DNX(unit)) { 2439 dnx_startup_test_functions[unit] = tr1_init_callback; 2440 goto done; 2441 } 2442 #endif 2443 } else 2444 #endif 2445 { 2446 #if defined(BCM_PETRA_SUPPORT) 2447 if (!SOC_IS_ARAD(unit)) 2448 #endif 2449 { 2450 { 2451 if ((r = soc_reset_init(unit)) < 0) { 2452 LOG_ERROR(BSL_LS_APPL_COMMON, 2453 (BSL_META_U(unit, 2454 "ERROR: Unable to reset unit %d: %s\n"), 2455 unit, soc_errmsg(r))); 2456 goto done; 2457 } 2458 } 2459 } 2460 } 2461 } 2462 2463 #ifdef BCM_TRIUMPH2_SUPPORT 2464 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) 2465 || SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) 2466 || SOC_IS_HURRICANE(unit)) { 2467 /* reset the register XQPORT_XGXS_NEWCTL_REG to 0x0 */ 2468 soc_port_t port; 2469 PBMP_PORT_ITER(unit, port) { 2470 switch(port) { 2471 case 26: 2472 case 27: 2473 case 28: 2474 case 29: 2475 if(SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit)) { 2476 SOC_IF_ERROR_RETURN(WRITE_XQPORT_XGXS_NEWCTL_REGr( 2477 unit, port, 0x0)); 2478 } else { 2479 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_NEWCTL_REGr( 2480 unit, port, 0x0)); 2481 } 2482 break; 2483 case 30: 2484 case 34: 2485 case 38: 2486 case 42: 2487 case 46: 2488 case 50: 2489 SOC_IF_ERROR_RETURN(WRITE_XQPORT_XGXS_NEWCTL_REGr(unit, port, 0x0)); 2490 break; 2491 default: 2492 break; 2493 } 2494 } 2495 } 2496 #endif 2497 sal_usleep(10000); 2498 2499 { 2500 #if defined (BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 2501 if (soc_reg_iterate(unit, rval_test_proc_dispatch, &rd) < 0) { 2502 goto done; 2503 } 2504 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 2505 } 2506 2507 rv = rd.error; 2508 2509 done: 2510 if (rv < 0) { 2511 test_error(unit, "Register reset value test failed\n"); 2512 } 2513 { 2514 #ifdef BCM_PETRA_SUPPORT 2515 if (SOC_IS_ARAD(unit)) 2516 { 2517 if ((r = soc_dpp_device_reset(unit, SOC_DPP_RESET_MODE_REG_ACCESS,SOC_DPP_RESET_ACTION_INOUT_RESET)) < 0) { 2518 LOG_ERROR(BSL_LS_APPL_COMMON, 2519 (BSL_META_U(unit, 2520 "ERROR: Unable to reinit unit %d: %s\n"), unit, soc_errmsg(r))); 2521 2522 } 2523 } else 2524 #endif 2525 #if defined (BCM_DFE_SUPPORT) || defined(BCM_DNXF_SUPPORT) 2526 if (SOC_IS_DFE(unit) || SOC_IS_DNXF(unit)) 2527 { 2528 2529 LOG_WARN(BSL_LS_APPL_COMMON, 2530 (BSL_META_U(unit, 2531 "Warning: Run 'tr 141' in order to reset unit %d\n"), unit)); 2532 2533 } else 2534 #endif 2535 #ifdef BCM_DNX_SUPPORT 2536 if (SOC_IS_DNX(unit) && (dnx_data_dev_init_general_access_only_get(unit) == 0)) 2537 { 2538 LOG_WARN(BSL_LS_APPL_COMMON, 2539 (BSL_META_U(unit, 2540 "Warning: Run 'tr 141' in order to reset unit %d\n"), unit)); 2541 test_dnxc_init_test_init(unit, a, pa); 2542 test_dnxc_init_test(unit, a, pa); 2543 test_dnxc_init_test_done(unit, pa); 2544 dnx_startup_test_functions[unit] = NULL; 2545 } else 2546 #endif 2547 if ((r = soc_reset_init(unit)) < 0) { 2548 LOG_ERROR(BSL_LS_APPL_COMMON, 2549 (BSL_META_U(unit, 2550 "ERROR: Unable to reset unit %d: %s\n"), 2551 unit, soc_errmsg(r))); 2552 } 2553 } 2554 2555 return rv; 2556 } 2557 2558 2559 #endif /* BCM_ESW_SUPPORT */ 2560 2561 #if defined(BCM_DFE_SUPPORT) 2562 2563 #define BRDC_BLOCKS_TEST_MAX_BLOCKS (10) 2564 /* 2565 * Function: 2566 * brdc_blk_test_info_get 2567 * Purpose: 2568 * Returns necessary info on device broadcast blocks 2569 * Parameters: 2570 * unit - (IN) Unit number. 2571 * max_size - (IN) max number of broadcast blocks 2572 * brdc_info - (OUT) structure which holds the required info about each broadcast block 2573 * actual_size - (OUT) number of broadcast blocks 2574 * Returns: 2575 * SOC_E_xxx 2576 * Notes: 2577 */ 2578 2579 STATIC int 2580 brdc_blk_test_info_get(int unit, int max_size, soc_reg_brdc_block_info_t *brdc_info, int *actual_size) 2581 { 2582 int rv = BCM_E_UNAVAIL; 2583 2584 *actual_size = 0; 2585 2586 #ifdef BCM_DFE_SUPPORT 2587 if (SOC_IS_DFE(unit)) 2588 { 2589 rv = MBCM_DFE_DRIVER_CALL(unit, mbcm_dfe_drv_test_brdc_blk_info_get, (unit, max_size, brdc_info, actual_size)); 2590 if (rv < 0) 2591 { 2592 LOG_ERROR(BSL_LS_APPL_COMMON, 2593 (BSL_META_U(unit, 2594 "ERROR: unit %d : %s\n"), 2595 unit, soc_errmsg(rv))); 2596 return rv; 2597 } 2598 } 2599 #endif 2600 2601 return rv; 2602 } 2603 2604 /* 2605 * Function: 2606 * brdc_blk_test_reg_filter 2607 * Purpose: 2608 * Special registers should not be tested in broadcast block test 2609 * Parameters: 2610 * unit - (IN) Unit number. 2611 * reg - (IN) relevant reg 2612 * is_filtered - (OUT) if 1 - do not test this reg 2613 * Returns: 2614 * SOC_E_xxx 2615 * Notes: 2616 */ 2617 2618 STATIC int 2619 brdc_blk_test_reg_filter(int unit, soc_reg_t reg, int *is_filter) 2620 { 2621 int rv = BCM_E_NONE; 2622 2623 /*filter read only, interrupt registers, counters and signal*/ 2624 if (SOC_REG_INFO(unit, reg).flags & 2625 (SOC_REG_FLAG_RO | SOC_REG_FLAG_INTERRUPT | SOC_REG_FLAG_GENERAL_COUNTER | SOC_REG_FLAG_SIGNAL)) { 2626 *is_filter = 1; 2627 return rv; 2628 } 2629 2630 /*additional filetr per device*/ 2631 #ifdef BCM_DFE_SUPPORT 2632 if (SOC_IS_DFE(unit)) 2633 { 2634 rv = MBCM_DFE_DRIVER_CALL(unit, mbcm_dfe_drv_test_brdc_blk_filter, (unit, reg, is_filter)); 2635 if (rv < 0) 2636 { 2637 LOG_ERROR(BSL_LS_APPL_COMMON, 2638 (BSL_META_U(unit, "ERROR: unit %d register %d : %s\n"), unit, reg, soc_errmsg(rv))); 2639 return rv; 2640 } 2641 return rv; 2642 } 2643 #endif 2644 2645 return rv; 2646 } 2647 /* 2648 * Function: 2649 * brdc_blk_test_reg_addr_get 2650 * Purpose: 2651 * Reading a register value of any kind: 32, 64, above 64. 2652 * Giving the addr and the schan block number. 2653 * 2654 * Parameters: 2655 * unit - (IN) Unit number 2656 * reg - (IN) relevant register of the broadcast block 2657 * acc_type - (IN) access type 2658 * addr - (IN) register address 2659 * block - (IN) schan block number to read from 2660 * data - (OUT) register value 2661 * Returns: 2662 * BCM_E_xxx 2663 * Notes: 2664 */ 2665 STATIC int 2666 brdc_blk_test_reg_addr_get(int unit, soc_reg_t reg, int acc_type, int addr, int block, soc_reg_above_64_val_t *data) 2667 { 2668 int reg_size; 2669 uint64 data64; 2670 uint32 data32; 2671 int rv; 2672 2673 SOC_REG_ABOVE_64_CLEAR(*data); 2674 2675 if (SOC_REG_IS_ABOVE_64(unit, reg)) 2676 { 2677 reg_size = SOC_REG_ABOVE_64_INFO(unit, reg).size; 2678 return soc_direct_reg_get(unit, block, addr, reg_size, *data); 2679 } else if (SOC_REG_IS_64(unit, reg)) { 2680 2681 rv = _soc_reg64_get(unit, block, acc_type, addr, &data64); 2682 SOC_REG_ABOVE_64_WORD_SET(*data, COMPILER_64_LO(data64), 0); 2683 SOC_REG_ABOVE_64_WORD_SET(*data, COMPILER_64_HI(data64), 1); 2684 return rv; 2685 } else { 2686 rv = _soc_reg32_get(unit, block, acc_type, addr, &data32); 2687 SOC_REG_ABOVE_64_WORD_SET(*data, data32 , 0); 2688 return rv; 2689 } 2690 2691 return BCM_E_NONE; 2692 } 2693 2694 /* 2695 * Function: 2696 * brdc_blk_test 2697 * Purpose: 2698 * Main Broadcast Block test function - 2699 * This test role is to set a specific register in broadcast block, 2700 * And to make sure that all the blocks that controlled by the broadcast block changed. 2701 * 2702 * Parameters: 2703 * unit - (IN) Unit number. 2704 * a - (IN) test args - not used 2705 * pa - (IN) not used 2706 * Returns: 2707 * BCM_E_xxx 2708 * Notes: 2709 */ 2710 int 2711 brdc_blk_test_dfe(int unit, args_t *a, void *pa) 2712 { 2713 int rv = BCM_E_NONE; 2714 soc_block_t brdc_block; 2715 soc_reg_t reg; 2716 soc_reg_above_64_val_t reg_above_64, reg_above_64_get; 2717 int block_dummy; 2718 uint8 acc_type; 2719 uint32 addr; 2720 int index, blk_instance; 2721 soc_reg_brdc_block_info_t *brdc_blk_info = NULL; 2722 int count, test_block; 2723 int is_filter; 2724 int blk_index; 2725 int result = BCM_E_NONE; 2726 char *reg_name; 2727 #if defined(SOC_NO_NAMES) 2728 char buffer[15]; 2729 #endif 2730 2731 /*write value is fixed to 1*/ 2732 SOC_REG_ABOVE_64_CLEAR(reg_above_64); 2733 SOC_REG_ABOVE_64_WORD_SET(reg_above_64, 1, 0); 2734 2735 brdc_blk_info = sal_alloc(sizeof(*brdc_blk_info) * BRDC_BLOCKS_TEST_MAX_BLOCKS, "brdc_blk_test.brdc_blk_info"); 2736 if(brdc_blk_info == NULL) { 2737 cli_out("Memory allocation failure\n"); 2738 return CMD_FAIL; 2739 } 2740 rv = brdc_blk_test_info_get(unit, BRDC_BLOCKS_TEST_MAX_BLOCKS ,brdc_blk_info, &count); 2741 if (rv < 0) 2742 { 2743 LOG_ERROR(BSL_LS_APPL_TESTS, 2744 (BSL_META_U(unit, "brdc_blk_test: ERROR: unit %d : %s\n"), unit, soc_errmsg(rv))); 2745 sal_free(brdc_blk_info); 2746 return rv; 2747 } 2748 2749 for (test_block = 0; test_block < count; test_block++) 2750 { 2751 2752 brdc_block = brdc_blk_info[test_block].blk_type; 2753 2754 /*Iterate over all relevant block registers (brdc_block)*/ 2755 for (reg = 0; reg < NUM_SOC_REG; reg++) 2756 { 2757 if (!SOC_REG_IS_VALID(unit, reg)) 2758 { 2759 continue; 2760 } 2761 2762 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, reg).block, brdc_block)) 2763 { 2764 #if defined(SOC_NO_NAMES) 2765 sal_sprintf(buffer, "%d", reg); 2766 reg_name = buffer; 2767 #else 2768 reg_name = SOC_REG_NAME(unit, reg); 2769 #endif 2770 /*register filter*/ 2771 rv = brdc_blk_test_reg_filter(unit, reg, &is_filter); 2772 if (rv < 0) 2773 { 2774 LOG_ERROR(BSL_LS_APPL_TESTS, 2775 (BSL_META_U(unit, "brdc_blk_test: ERROR: unit %d, register %s : %s\n"), unit, reg_name, soc_errmsg(rv))); 2776 sal_free(brdc_blk_info); 2777 return rv; 2778 } 2779 if (is_filter) 2780 { 2781 LOG_VERBOSE(BSL_LS_APPL_TESTS, 2782 (BSL_META_U(unit, "brdc_blk_test: Filtering unit %d register %s\n"), unit, reg_name)); 2783 continue; 2784 } 2785 2786 LOG_VERBOSE(BSL_LS_APPL_TESTS, 2787 (BSL_META_U(unit, "brdc_blk_test: Testing unit %d register %s \n"), unit, reg_name)); 2788 2789 /*Iterate over all possible indexes*/ 2790 for (index = 0; index < SOC_REG_INFO(unit, reg).numels; index++) 2791 { 2792 /*write to broadcast block*/ 2793 rv = soc_reg_above_64_set(unit, reg, 0, index, reg_above_64); 2794 if (rv < 0) 2795 { 2796 LOG_ERROR(BSL_LS_APPL_TESTS, 2797 (BSL_META_U(unit, "brdc_blk_test: ERROR: unit %d, register %s : %s\n"), unit, reg_name, soc_errmsg(rv))); 2798 sal_free(brdc_blk_info); 2799 return rv; 2800 } 2801 2802 /*read all relevant blocks and make sure equals*/ 2803 addr = soc_reg_addr_get(unit, reg, REG_PORT_ANY, index, 2804 SOC_REG_ADDR_OPTION_NONE, 2805 &block_dummy, &acc_type); 2806 for (blk_index = 0; brdc_blk_info[test_block].blk_ids[blk_index] != -1 ; blk_index++) 2807 { 2808 blk_instance = brdc_blk_info[test_block].blk_ids[blk_index]; /*schan number of the relevant blk*/ 2809 2810 SOC_REG_ABOVE_64_CLEAR(reg_above_64_get); 2811 2812 rv = brdc_blk_test_reg_addr_get(unit, reg, acc_type, addr, SOC_BLOCK2SCH(unit, blk_instance), ®_above_64_get); 2813 if (rv < 0) 2814 { 2815 LOG_ERROR(BSL_LS_APPL_TESTS, 2816 (BSL_META_U(unit, "brdc_blk_test: ERROR: unit %d, register %s : %s\n"), unit, reg_name, soc_errmsg(rv))); 2817 result = BCM_E_FAIL; 2818 continue; 2819 } 2820 2821 if (!SOC_REG_ABOVE_64_IS_EQUAL(reg_above_64_get, reg_above_64)) 2822 { 2823 LOG_ERROR(BSL_LS_APPL_TESTS, 2824 (BSL_META_U(unit, "brdc_blk_test: ERROR: unit %d, register %s : %s\n"), unit, reg_name, soc_errmsg(BCM_E_FAIL))); 2825 result = BCM_E_FAIL; 2826 continue; 2827 } 2828 } /*blk controled by the brdc blk iteration*/ 2829 2830 } /*index iteration*/ 2831 } 2832 2833 } /*reg iteration*/ 2834 2835 } /*brdc blk iteration*/ 2836 2837 sal_free(brdc_blk_info); 2838 return result; 2839 } 2840 2841 #endif /*defined(BCM_DFE_SUPPORT) */ 2842 2843 #if defined(BCM_SAND_SUPPORT) 2844 2845 /* 2846 * Function: 2847 * test_brdc_mem_filter 2848 * Purpose: 2849 * Exclude list for memories very similar to TR 6 and TR 7. 2850 * 2851 * Parameters: 2852 * unit - (IN) Unit number 2853 * mem - (IN) relevant memory of the broadcast block 2854 * is_filtered - (OUT) Shows if the memory is in the exclude list 2855 * Returns: 2856 * BCM_E_xxx 2857 * Notes: 2858 */ 2859 2860 STATIC int 2861 test_brdc_mem_filter(int unit, soc_mem_t mem, int *is_filtered) 2862 { 2863 int rv = BCM_E_NONE; 2864 2865 *is_filtered = 0; 2866 2867 switch(mem) 2868 { 2869 case BRDC_QRH_FFLBm: 2870 case BRDC_QRH_MCLBTm: 2871 case BRDC_QRH_MCSFFm: 2872 case BRDC_QRH_MNOLm: 2873 case FSRD_FSRD_PROM_MEMm: 2874 case QRH_FFLBm: 2875 case QRH_MCLBTm: 2876 case QRH_MCSFFm: 2877 case QRH_MNOLm: 2878 case FSRD_FSRD_WL_EXT_MEMm: 2879 case IPS_CRBALTHm: 2880 *is_filtered = 1; 2881 break; /* Skip these tables */ 2882 default: 2883 break; 2884 } 2885 return rv; 2886 } 2887 2888 /* 2889 * Function: 2890 * brdc_blk_test 2891 * Purpose: 2892 * Main Broadcast Block test function - 2893 * This test role is to set a specific register in broadcast block, 2894 * And to make sure that all the blocks that controlled by the broadcast block changed. 2895 * 2896 * Parameters: 2897 * unit - (IN) Unit number. 2898 * a - (IN) test args - not used 2899 * pa - (IN) not used 2900 * Returns: 2901 * BCM_E_xxx 2902 * Notes: 2903 */ 2904 2905 int 2906 brdc_blk_test(int unit, args_t *a, void *pa) 2907 { 2908 int rv = BCM_E_NONE; 2909 soc_block_t blk; 2910 soc_block_t none_brdc_block_type; 2911 soc_reg_t reg; 2912 soc_reg_t brdc_reg; 2913 2914 soc_mem_t mem; 2915 soc_mem_t brdc_mem; 2916 2917 soc_reg_above_64_val_t reg_above_64, reg_above_64_get; 2918 soc_block_types_t regblktype; 2919 2920 int block_dummy; 2921 uint8 acc_type; 2922 uint32 addr = 0; 2923 int delayed_errors = 0; 2924 int reg_size = 0, reg_size_word = 0; 2925 int mem_size = 0, mem_size_word = 0; 2926 int instance; 2927 int reg_tested = 0, mem_tested = 0; 2928 int data; 2929 int field; 2930 int result = BCM_E_NONE; 2931 int is_filter = 0; 2932 int brdc_count = 0; 2933 int max_number_of_blocks = 0; 2934 int i; 2935 soc_block_t brdc_block[MAX_NOF_BROADCAST_BLOCKS]; /* The soc IDs of the broadcast blocks */ 2936 int blk_first_instance = 0; 2937 /* FOR BRDC set and get regular block */ 2938 char *reg_name = NULL; 2939 char *mem_name = NULL; 2940 2941 /* broadcast block name: SOC_BLOCK_NAME(unit,blk)+BRDC_PREFIX_LEN */ 2942 /* write value is fixed to 1 with setting value 1 in one word only */ 2943 SOC_REG_ABOVE_64_CLEAR(reg_above_64); 2944 SOC_REG_ABOVE_64_WORD_SET(reg_above_64, 1, 0); 2945 /* Calling the old function for old FE's */ 2946 #ifdef BCM_DFE_SUPPORT 2947 if(SOC_IS_DFE(unit)) { 2948 return brdc_blk_test_dfe(unit, a, pa); 2949 } 2950 #endif 2951 /* Loop over all the blocks to find all of the BRDC blocks */ 2952 for (blk = 0; SOC_BLOCK_INFO(unit, blk).type >= 0; blk++) { 2953 max_number_of_blocks++; 2954 if (sal_strncmp(SOC_BLOCK_NAME(unit,blk), "BRDC_", BRDC_PREFIX_LEN) == 0) { 2955 if (!SOC_BLOCK_IS_BROADCAST(unit, blk)) { 2956 LOG_INFO(BSL_LS_APPL_TESTS, 2957 (BSL_META_U(unit, "brdc_blk_test: Found block is not BRDC blocks: %d : %s\n"), 2958 brdc_count, soc_errmsg(rv))); 2959 delayed_errors++; 2960 continue; 2961 } 2962 /* verify SOC_BLOCK_IS_BROADCAST(unit, blk) */ 2963 if (brdc_count >= MAX_NOF_BROADCAST_BLOCKS) { 2964 LOG_INFO(BSL_LS_APPL_TESTS, 2965 (BSL_META_U(unit, "brdc_blk_test: ERROR Reached the max number of BRDC blocks: %d : %s\n"), 2966 brdc_count, soc_errmsg(rv))); 2967 delayed_errors++; 2968 break; 2969 /* Print error if reaching MAX_NOF_BROADCAST_BLOCKS */ 2970 } 2971 #ifdef BCM_DNX_SUPPORT 2972 if ((dnx_data_dram.general_info.dram_info_get(unit)->dram_bitmap == 0) && (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_BRDC_HBC)) 2973 { 2974 continue; 2975 } 2976 else 2977 { 2978 #endif 2979 brdc_block[brdc_count] = blk; 2980 brdc_count++; 2981 #ifdef BCM_DNX_SUPPORT 2982 } 2983 #endif 2984 2985 } else if (SOC_BLOCK_IS_BROADCAST(unit, blk)) { 2986 LOG_INFO(BSL_LS_APPL_TESTS, 2987 (BSL_META_U(unit, "brdc_blk_test: Block: %d is marked as a broadcast block but is not named BRDC_ : %s\n"), 2988 blk, soc_errmsg(rv))); 2989 delayed_errors++; 2990 } 2991 } 2992 2993 /* Looping that data with 0 and 1 to test both values */ 2994 for(data = 0 ; data < 2; data++) { 2995 /* Test each broadcast block */ 2996 for (i = 0; i < brdc_count; i++) { 2997 blk_first_instance = SOC_BLOCK_BROADCAST_MEMBER(unit, brdc_block[i], 0); 2998 reg_tested = 0; 2999 mem_tested = 0; 3000 none_brdc_block_type = SOC_BLOCK_INFO(unit, blk_first_instance).type; 3001 for (reg = 0; reg < NUM_SOC_REG; reg++) { 3002 /*Get a good register for testing */ 3003 if (!SOC_REG_IS_VALID(unit, reg) || !SOC_REG_IS_ENABLED(unit, reg) || (SOC_REG_INFO(unit,reg).flags & 3004 (SOC_REG_FLAG_RO | SOC_REG_FLAG_WO | SOC_REG_FLAG_ARRAY | SOC_REG_FLAG_INTERRUPT | SOC_REG_FLAG_GENERAL_COUNTER | SOC_REG_FLAG_SIGNAL))) { 3005 continue; 3006 } 3007 3008 regblktype = SOC_REG_INFO(unit, reg).block; 3009 /* We found a suitable register in the block for testing. Test it. */ 3010 if (SOC_BLOCK_IS(regblktype, none_brdc_block_type)) { 3011 /* Check the size of the register by counting the fields and storing the number in reg_size */ 3012 reg_size = 0; 3013 for (field = 0; field < (int)(SOC_REG_INFO(unit, reg).nFields); field++) 3014 { 3015 reg_size += soc_reg_field_length(unit, reg, SOC_REG_INFO(unit, reg).fields->field); 3016 } /*getting the size of register*/ 3017 3018 if (SOC_REG_IS_ABOVE_64(unit, reg)) { 3019 reg_size_word = SOC_REG_ABOVE_64_INFO(unit, reg).size; 3020 } else if (SOC_REG_IS_64(unit, reg)) { 3021 reg_size_word = 2; 3022 } else { 3023 reg_size_word = 1; 3024 } 3025 SOC_REG_ABOVE_64_WORD_SET(reg_above_64, data, 0); 3026 addr = soc_reg_addr_get(unit, reg, REG_PORT_ANY, 0, 3027 SOC_REG_ADDR_OPTION_NONE, 3028 &block_dummy, &acc_type); 3029 blk = SOC_BLOCK_BROADCAST_MEMBER(unit, brdc_block[i], 0); 3030 rv = soc_direct_reg_set(unit,SOC_BLOCK2SCH(unit, brdc_block[i]), addr, reg_size_word, reg_above_64); 3031 LOG_INFO(BSL_LS_APPL_TESTS, 3032 (BSL_META("Write using the ADDR reg %s: value %u \n"), 3033 SOC_REG_NAME(unit,reg), *reg_above_64)); 3034 if (rv < 0) 3035 { 3036 LOG_ERROR(BSL_LS_APPL_TESTS, 3037 (BSL_META_U(unit, "brdc_blk_test: ERROR ADDR set: unit %d, register %d : %s\n"), unit, reg, soc_errmsg(rv))); 3038 result = BCM_E_FAIL; 3039 } 3040 for (instance = 0; instance < SOC_BLOCK_BROADCAST_SIZE(unit, brdc_block[i]) ; ++instance) { 3041 /* Read all relevant blocks and make sure equals */ 3042 blk = SOC_BLOCK_BROADCAST_MEMBER(unit, brdc_block[i], instance); 3043 rv = soc_reg_above_64_get(unit, reg, instance, 0, reg_above_64_get); 3044 LOG_INFO(BSL_LS_APPL_TESTS, 3045 (BSL_META("Read reg %s instance %d : value %u \n"), 3046 SOC_REG_NAME(unit,reg), instance, *reg_above_64_get)); 3047 if (rv < 0) 3048 { 3049 LOG_ERROR(BSL_LS_APPL_TESTS, 3050 (BSL_META_U(unit, "brdc_blk_test: ERROR Getting: unit %d, register %d : %s\n"), unit, reg, soc_errmsg(rv))); 3051 result = BCM_E_FAIL; 3052 continue; 3053 } 3054 /* Checking if the written data is the same as the one that we read */ 3055 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, reg_size)) /*Compare only the amount of bits in the register */ 3056 { 3057 LOG_ERROR(BSL_LS_APPL_TESTS, 3058 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing: unit %d, register %d : %s\n"), unit, reg, soc_errmsg(BCM_E_FAIL))); 3059 result = BCM_E_FAIL; 3060 continue; 3061 } 3062 /* Getting the address of the register for another testing */ 3063 addr = soc_reg_addr_get(unit, reg, REG_PORT_ANY, 0, 3064 SOC_REG_ADDR_OPTION_NONE, 3065 &block_dummy, &acc_type); 3066 /* Another way for reading the register is by the Address and the block */ 3067 rv = soc_direct_reg_get(unit, SOC_BLOCK2SCH(unit, blk), addr, reg_size_word, reg_above_64_get); 3068 LOG_INFO(BSL_LS_APPL_TESTS, 3069 (BSL_META("Read addr 0x%x: value %u \n"), 3070 addr, *reg_above_64_get)); 3071 if (rv < 0) 3072 { 3073 LOG_ERROR(BSL_LS_APPL_TESTS, 3074 (BSL_META_U(unit, "brdc_blk_test: ERROR ADDR: unit %d, register %d : %s\n"), unit, reg, soc_errmsg(rv))); 3075 result = BCM_E_FAIL; 3076 continue; 3077 } 3078 /* Checking if the written data is the same as the one that we read */ 3079 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, reg_size)) /*Compare only the amount of bits in the register */ 3080 { 3081 LOG_ERROR(BSL_LS_APPL_TESTS, 3082 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing ADDR: unit %d, register %d : %s\n"), unit, reg, soc_errmsg(BCM_E_FAIL))); 3083 result = BCM_E_FAIL; 3084 continue; 3085 } 3086 3087 } 3088 reg_name = sal_alloc(sizeof(char)*100,"brdc_blk_test.reg_name"); 3089 sal_memset(reg_name, 0, sizeof(char)*100); 3090 sal_strncpy(reg_name,"BRDC_", sizeof(char)*5); 3091 sal_strncat(reg_name, SOC_REG_NAME(unit,reg), sizeof(char)*100); 3092 for (brdc_reg = 0; brdc_reg < NUM_SOC_REG; brdc_reg++) { 3093 if (sal_strcmp(reg_name, SOC_REG_NAME(unit, brdc_reg)) == 0) { 3094 rv = soc_reg_above_64_set(unit, brdc_reg, REG_PORT_ANY, 0 , reg_above_64); 3095 if (rv < 0) 3096 { 3097 LOG_INFO(BSL_LS_APPL_TESTS, 3098 (BSL_META_U(unit, "brdc_blk_test: Register does not exist with BRDC_<reg_name>: unit %d, register %d\n"), unit, reg)); 3099 } 3100 LOG_INFO(BSL_LS_APPL_TESTS, 3101 (BSL_META("Write to BRDC reg %s: value %u \n"), 3102 reg_name, *reg_above_64)); 3103 for (instance = 0; instance < SOC_BLOCK_BROADCAST_SIZE(unit, brdc_block[i]) ; ++instance) { 3104 rv = soc_reg_above_64_get(unit, reg, instance, 0, reg_above_64_get); 3105 LOG_INFO(BSL_LS_APPL_TESTS, 3106 (BSL_META("Read reg %s instance %d : value %u \n"), 3107 SOC_REG_NAME(unit,reg), instance, *reg_above_64_get)); 3108 if (rv < 0) 3109 { 3110 LOG_ERROR(BSL_LS_APPL_TESTS, 3111 (BSL_META_U(unit, "brdc_blk_test: ERROR Getting: unit %d, register %d : %s\n"), unit, reg, soc_errmsg(rv))); 3112 result = BCM_E_FAIL; 3113 continue; 3114 } 3115 /* Checking if the written data is the same as the one that we read */ 3116 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, reg_size)) /*Compare only the amount of bits in the register */ 3117 { 3118 LOG_ERROR(BSL_LS_APPL_TESTS, 3119 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing: unit %d, register %d : %s\n"), unit, reg, soc_errmsg(BCM_E_FAIL))); 3120 result = BCM_E_FAIL; 3121 continue; 3122 } 3123 } 3124 } 3125 } 3126 sal_free(reg_name); 3127 reg_tested++; 3128 break; 3129 } 3130 } 3131 if (reg_tested == 0) { 3132 LOG_ERROR(BSL_LS_APPL_TESTS, 3133 (BSL_META_U(unit, "brdc_blk_test: ERROR NO registers were tested : %s\n"), soc_errmsg(BCM_E_FAIL))); 3134 delayed_errors++; 3135 } 3136 /* TO BE DONE: Add a memory DMA test */ 3137 /* Testing BRDC memories if they exist */ 3138 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 3139 if (!SOC_MEM_IS_VALID(unit, mem)) { 3140 continue; 3141 } 3142 if (soc_mem_index_count(unit, mem) == 0) { 3143 continue; 3144 } 3145 if (!SOC_MEM_IS_ENABLED(unit, mem)) { 3146 continue; 3147 } 3148 if ((SOC_MEM_INFO(unit,mem).flags & 3149 (SOC_MEM_FLAG_READONLY | SOC_MEM_FLAG_WRITEONLY | SOC_MEM_FLAG_SIGNAL))) { 3150 continue; 3151 } 3152 test_brdc_mem_filter(unit, mem, &is_filter); 3153 if (is_filter > 0) { 3154 continue; 3155 } 3156 3157 blk = SOC_MEM_BLOCK_MIN(unit, mem); 3158 /* Checked if the memory is in a BRDC block */ 3159 if(blk == blk_first_instance) { 3160 SOC_REG_ABOVE_64_WORD_SET(reg_above_64, data, 0); 3161 /*Getting the size of the memory*/ 3162 for (field = 0; field < (int)(SOC_MEM_INFO(unit, mem).nFields); field++) 3163 { 3164 mem_size += soc_mem_field_length(unit, mem, SOC_MEM_INFO(unit, mem).fields->field); 3165 } 3166 mem_size_word = BITS2WORDS(SOC_MEM_WORDS(unit, mem)); 3167 rv = soc_mem_write(unit, mem, MEM_BLOCK_ALL, 0, reg_above_64); 3168 LOG_INFO(BSL_LS_APPL_TESTS, 3169 (BSL_META("Write mem %s: value %u \n"), 3170 SOC_MEM_NAME(unit, mem), *reg_above_64)); 3171 if (rv < 0) 3172 { 3173 LOG_ERROR(BSL_LS_APPL_TESTS, 3174 (BSL_META_U(unit, "brdc_blk_test: ERROR ADDR: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(rv))); 3175 result = BCM_E_FAIL; 3176 } 3177 /* Looping all over the instances to preform read and write to a memory */ 3178 for (instance = 0; instance < SOC_BLOCK_BROADCAST_SIZE(unit, brdc_block[i]); instance++) { 3179 rv = soc_mem_read(unit, mem, instance, 0, reg_above_64_get); 3180 LOG_INFO(BSL_LS_APPL_TESTS, 3181 (BSL_META("Read mem %s instance %d : value %u \n"), 3182 SOC_MEM_NAME(unit, mem), instance, *reg_above_64_get)); 3183 if (rv < 0) 3184 { 3185 LOG_ERROR(BSL_LS_APPL_TESTS, 3186 (BSL_META_U(unit, "brdc_blk_test: ERROR Reading: unit %d, memory %d : %s\n"), unit, mem, soc_errmsg(rv))); 3187 return rv; 3188 } 3189 /* Comparing the data from the read with the one from the write */ 3190 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, mem_size)) /*Compare only the amount of bits in the memory */ 3191 { 3192 LOG_ERROR(BSL_LS_APPL_TESTS, 3193 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(BCM_E_FAIL))); 3194 result = BCM_E_FAIL; 3195 } 3196 addr = soc_mem_addr_get(unit, mem, 0, SOC_MEM_BLOCK_ANY(unit, mem), instance, &acc_type); 3197 /* Another way for reading the register is by the Address and the block */ 3198 rv = soc_direct_memreg_get(unit, SOC_BLOCK2SCH(unit, blk), addr, mem_size_word, 1, reg_above_64_get); 3199 LOG_INFO(BSL_LS_APPL_TESTS, 3200 (BSL_META("Read Memory addr 0x%x: value %u \n"), 3201 addr, *reg_above_64_get)); 3202 if (rv < 0) 3203 { 3204 LOG_ERROR(BSL_LS_APPL_TESTS, 3205 (BSL_META_U(unit, "brdc_blk_test: ERROR ADDR: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(rv))); 3206 result = BCM_E_FAIL; 3207 } 3208 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, mem_size)) /*Compare only the amount of bits in the memory */ 3209 { 3210 LOG_ERROR(BSL_LS_APPL_TESTS, 3211 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(BCM_E_FAIL))); 3212 result = BCM_E_FAIL; 3213 } 3214 } 3215 rv = soc_direct_memreg_set(unit, SOC_BLOCK2SCH(unit, brdc_block[i]), addr, mem_size_word, 1, reg_above_64); 3216 LOG_INFO(BSL_LS_APPL_TESTS, 3217 (BSL_META("Write to ADDR of a Memory addr 0x%x: value %u \n"), 3218 addr, *reg_above_64)); 3219 if (rv < 0) 3220 { 3221 LOG_ERROR(BSL_LS_APPL_TESTS, 3222 (BSL_META_U(unit, "brdc_blk_test: ERROR ADDR: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(rv))); 3223 result = BCM_E_FAIL; 3224 } 3225 /* Looping all over the instances to preform read and write to a memory */ 3226 for (instance = 0; instance < SOC_BLOCK_BROADCAST_SIZE(unit, brdc_block[i]); instance++) { 3227 rv = soc_mem_read(unit, mem, instance, 0, reg_above_64_get); 3228 LOG_INFO(BSL_LS_APPL_TESTS, 3229 (BSL_META("Read mem %s instance %d : value %u \n"), 3230 SOC_MEM_NAME(unit, mem), instance, *reg_above_64_get)); 3231 if (rv < 0) 3232 { 3233 LOG_ERROR(BSL_LS_APPL_TESTS, 3234 (BSL_META_U(unit, "brdc_blk_test: ERROR Reading: unit %d, memory %d : %s\n"), unit, mem, soc_errmsg(rv))); 3235 return rv; 3236 } 3237 /* Comparing the data from the read with the one from the write */ 3238 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, mem_size)) /*Compare only the amount of bits in the memory */ 3239 { 3240 LOG_ERROR(BSL_LS_APPL_TESTS, 3241 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(BCM_E_FAIL))); 3242 result = BCM_E_FAIL; 3243 } 3244 addr = soc_mem_addr_get(unit, mem, 0, SOC_MEM_BLOCK_ANY(unit, mem), instance, &acc_type); 3245 /* Another way for reading the register is by the Address and the block */ 3246 rv = soc_direct_memreg_get(unit, SOC_BLOCK2SCH(unit, blk), addr, mem_size_word, 1, reg_above_64_get); 3247 LOG_INFO(BSL_LS_APPL_TESTS, 3248 (BSL_META("Read Memory addr 0x%x: value %u \n"), 3249 addr, *reg_above_64_get)); 3250 if (rv < 0) 3251 { 3252 LOG_ERROR(BSL_LS_APPL_TESTS, 3253 (BSL_META_U(unit, "brdc_blk_test: ERROR ADDR: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(rv))); 3254 result = BCM_E_FAIL; 3255 } 3256 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, mem_size)) /*Compare only the amount of bits in the memory */ 3257 { 3258 LOG_ERROR(BSL_LS_APPL_TESTS, 3259 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(BCM_E_FAIL))); 3260 result = BCM_E_FAIL; 3261 } 3262 } 3263 mem_name = sal_alloc(sizeof(char)*100,"brdc_blk_test.mem_name"); 3264 sal_memset(mem_name, 0, sizeof(char)*100); 3265 sal_strncpy(mem_name,"BRDC_", sizeof(char)*5); 3266 sal_strncat(mem_name, SOC_MEM_NAME(unit, mem), sizeof(char)*100); 3267 for (brdc_mem = 0; brdc_mem < NUM_SOC_MEM; brdc_mem++) { 3268 if (sal_strcmp(mem_name, SOC_MEM_NAME(unit, brdc_mem)) == 0) { 3269 rv = soc_mem_write(unit, brdc_mem, MEM_BLOCK_ALL, 0, reg_above_64); 3270 if (rv < 0) 3271 { 3272 LOG_INFO(BSL_LS_APPL_TESTS, 3273 (BSL_META_U(unit, "brdc_blk_test: Memory does not exist with BRDC_<mem_name>: unit %d, memory %d\n"), unit, brdc_mem)); 3274 } else { 3275 LOG_INFO(BSL_LS_APPL_TESTS, 3276 (BSL_META("Write to BRDC mem %s: value %u \n"), 3277 mem_name, *reg_above_64)); 3278 for (instance = 0; instance < SOC_BLOCK_BROADCAST_SIZE(unit, brdc_block[i]); instance++) { 3279 rv = soc_mem_read(unit, mem, instance, 0, reg_above_64_get); 3280 if (rv < 0) 3281 { 3282 LOG_ERROR(BSL_LS_APPL_TESTS, 3283 (BSL_META_U(unit, "brdc_blk_test: ERROR Reading: unit %d, memory %d : %s\n"), unit, mem, soc_errmsg(rv))); 3284 sal_free(mem_name); 3285 return rv; 3286 } 3287 LOG_INFO(BSL_LS_APPL_TESTS, 3288 (BSL_META("Read mem %s instance %d : value %u \n"), 3289 SOC_MEM_NAME(unit, mem), instance, *reg_above_64_get)); 3290 /* Comparing the data from the read with the one from the write */ 3291 if (!SHR_BITEQ_RANGE(reg_above_64_get, reg_above_64, 0, mem_size)) /*Compare only the amount of bits in the memory */ 3292 { 3293 LOG_ERROR(BSL_LS_APPL_TESTS, 3294 (BSL_META_U(unit, "brdc_blk_test: ERROR Comparing: unit %d, memory %s : %s\n"), unit, SOC_MEM_NAME(unit, mem), soc_errmsg(BCM_E_FAIL))); 3295 result = BCM_E_FAIL; 3296 } 3297 } 3298 } 3299 } 3300 } 3301 sal_free(mem_name); 3302 mem_tested++; 3303 break; 3304 } 3305 } 3306 if (mem_tested == 0) { 3307 LOG_INFO(BSL_LS_APPL_TESTS, 3308 (BSL_META("Warning no memories were found and tested ! \n"))); 3309 } 3310 } 3311 } 3312 if (delayed_errors > 0) { 3313 LOG_ERROR(BSL_LS_APPL_TESTS, 3314 (BSL_META_U(unit, "brdc_blk_test: |The number of the delayed_errors is: %d : %s \n"), delayed_errors, soc_errmsg(BCM_E_FAIL))); 3315 result = BCM_E_FAIL; 3316 } 3317 return result; 3318 } 3319 3320 #endif 3321