memory.c (129912B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Memory Tests implemented via S-Channel table read/write. 8 * These are especially useful for memories without BIST (e.g. QVLAN). 9 */ 10 11 #ifdef _ERR_MSG_MODULE_NAME 12 #error "_ERR_MSG_MODULE_NAME redefined" 13 #endif 14 15 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_MEM 16 17 #include <shared/bsl.h> 18 19 #include <sal/types.h> 20 #include <sal/appl/io.h> 21 #include <shared/bsl.h> 22 #include <sal/appl/pci.h> 23 #include <appl/diag/system.h> 24 #include <appl/diag/parse.h> 25 #include <appl/diag/progress.h> 26 #include <soc/mem.h> 27 #include <soc/l2x.h> 28 #include <soc/soc_ser_log.h> 29 #include <bcm/field.h> 30 #ifdef BCM_TRIUMPH2_SUPPORT 31 #include <soc/triumph2.h> 32 #endif 33 #ifdef BCM_TRIDENT_SUPPORT 34 #include <soc/trident.h> 35 #endif 36 #ifdef BCM_TOMAHAWK_SUPPORT 37 #include <soc/tomahawk.h> 38 #endif 39 #if defined (BCM_PETRA_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 40 #if defined (BCM_PETRA_SUPPORT) 41 #include <soc/dpp/drv.h> 42 #include <bcm_int/dpp/counters.h> 43 #endif 44 #ifndef __KERNEL__ 45 #include <time.h> 46 #else 47 #include <linux/time.h> 48 #endif 49 50 #ifdef BCM_JERICHO_SUPPORT 51 #include <soc/dpp/JER/jer_mgmt.h> 52 #endif 53 #endif 54 55 #ifdef BCM_DFE_SUPPORT 56 #include <soc/dfe/cmn/dfe_drv.h> 57 #endif 58 #ifdef BCM_DNXF_SUPPORT 59 #include <soc/dnxf/cmn/dnxf_drv.h> 60 #endif 61 #ifdef BCM_DNX_SUPPORT 62 #include <soc/dnx/drv.h> 63 #include <sal/appl/config.h> 64 #endif 65 #include "testlist.h" 66 #if defined(CANCUN_SUPPORT) && !defined(NO_SAL_APPL) 67 #include <soc/esw/cancun.h> 68 #endif 69 70 #if defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT) 71 #include <soc/dnxc/legacy/dnxc_mem.h> 72 #endif 73 74 #if defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 75 extern cmd_result_t do_mem_test(int unit, args_t *a); 76 extern cmd_result_t do_mem_test_rw(int unit, tr7_dbase_t, args_t *a); 77 #if defined(BCM_PETRA_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 78 extern cmd_result_t do_mem_test_flipflop(int , tr8_dbase_t, args_t *); 79 int8 tr8_open_dump_file(int unit, char *fname); 80 void tr8_close_dump_file(void); 81 void tr8_write_dump(const char * _Format); 82 int disable_ecc_disable_dynamic_mechanism(int ); 83 #endif 84 #if defined (BCM_PETRA_SUPPORT)|| defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) || defined (BCM_DNX_SUPPORT) 85 extern cmd_result_t do_dump_memories(int unit, args_t *a); 86 extern int bcm_common_linkscan_enable_set(int,int); 87 #endif 88 #endif 89 90 #if defined (BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 91 92 typedef struct { 93 int inited; 94 int was_debug_mode; 95 int orig_enable; 96 int saved_tcam_protect_write; 97 int mem_scan; 98 int scan_rate; 99 sal_usecs_t scan_interval; 100 int sram_scan; 101 int sram_scan_rate; 102 sal_usecs_t sram_scan_interval; 103 int read_count; 104 int pat_zero, pat_one, pat_five, pat_a; 105 int pat_checker, pat_invckr, pat_linear, pat_random; 106 int progress_total; 107 int pat_hex; 108 int hex_byte; 109 int test_by_entry; 110 int reverify_count; 111 int reverify_delay; 112 int continue_on_error; 113 int error_count; 114 int error_max; 115 soc_mem_test_t parm; 116 } mem_testdata_t; 117 118 static mem_testdata_t *mem_work[SOC_MAX_NUM_DEVICES]; 119 120 121 122 /* 123 * Memory Test Support Routines 124 */ 125 126 void 127 mt_status_fn(soc_mem_test_t *parm, char *status_str) 128 { 129 static char buf[120]; 130 131 { 132 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 133 sal_sprintf(buf, 134 "%s on %s.%s", 135 status_str, 136 SOC_MEM_UFNAME(parm->unit, parm->mem), 137 SOC_BLOCK_NAME(parm->unit, parm->copyno)); 138 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 139 } 140 141 progress_status(buf); 142 } 143 144 int 145 mt_write_fn(soc_mem_test_t *parm, unsigned array_index, 146 int copyno, int index, uint32 *entry_data) 147 { 148 int rv = SOC_E_NONE; 149 150 if (parm->report_progress) { 151 progress_report(1); 152 } 153 154 { 155 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 156 rv |= soc_mem_array_write(parm->unit, parm->mem, array_index, copyno, index, entry_data); 157 if (rv != 0) 158 { 159 if (parm->array_index_start != 0 || parm->array_index_end != parm->array_index_start) { 160 cli_out("Write ERROR: table %s[%u].%s[%d]\n", 161 SOC_MEM_UFNAME(parm->unit, parm->mem), 162 array_index, 163 SOC_BLOCK_NAME(parm->unit, copyno), index); 164 } else { 165 cli_out("Write ERROR: table %s.%s[%d]\n", 166 SOC_MEM_UFNAME(parm->unit, parm->mem), 167 SOC_BLOCK_NAME(parm->unit, copyno), index); 168 } 169 return -1; 170 } 171 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 172 } 173 174 return 0; 175 } 176 177 #undef TEST_INJECT_READ_ERROR 178 179 int 180 mt_read_fn(soc_mem_test_t *parm, unsigned array_index, 181 int copyno, int index, uint32 *entry_data) 182 { 183 int rv = SOC_E_NONE; 184 185 if (parm->report_progress) { 186 progress_report(1); 187 } 188 189 { 190 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 191 rv |= soc_mem_array_read(parm->unit, parm->mem, array_index, copyno, index, entry_data); 192 if (rv != 0) 193 { 194 if (parm->array_index_start != 0 || parm->array_index_end != parm->array_index_start) { 195 cli_out("Read ERROR: table %s[%u].%s[%d]\n", 196 SOC_MEM_UFNAME(parm->unit, parm->mem), 197 array_index, 198 SOC_BLOCK_NAME(parm->unit, copyno), index); 199 } else { 200 cli_out("Read ERROR: table %s.%s[%d]\n", 201 SOC_MEM_UFNAME(parm->unit, parm->mem), 202 SOC_BLOCK_NAME(parm->unit, copyno), index); 203 } 204 return -1; 205 } 206 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 207 } 208 209 #ifdef TEST_INJECT_READ_ERROR 210 if (index == 7) 211 entry_data[0] ^= 0x00010000; 212 #endif 213 214 return 0; 215 } 216 217 int 218 mt_miscompare_fn(soc_mem_test_t *parm, unsigned array_index, 219 int copyno, int index, 220 uint32 *read_data, uint32 *wrote_data, uint32 *mask_data) 221 { 222 int unit = parm->unit; 223 int i, dw; 224 uint32 reread_data[SOC_MAX_MEM_WORDS]; 225 226 soc_pci_analyzer_trigger(unit); 227 228 dw = soc_mem_entry_words(unit, parm->mem); 229 230 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 231 if (parm->array_index_start != 0 || parm->array_index_end != parm->array_index_start) { 232 { 233 cli_out("\n\nCompare ERROR: table %s[%u].%s[%d]\n", 234 SOC_MEM_UFNAME(unit, parm->mem), array_index, 235 SOC_BLOCK_NAME(unit, copyno), index); 236 } 237 } else 238 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 239 { 240 { 241 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 242 cli_out("\n\nCompare ERROR: table %s.%s[%d]\n", 243 SOC_MEM_UFNAME(unit, parm->mem), 244 SOC_BLOCK_NAME(unit, copyno), index); 245 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 246 } 247 } 248 cli_out("\n Mask :"); 249 for (i = 0; i < dw; i++) { 250 cli_out(" 0x%08x", mask_data[i]); 251 } 252 253 254 cli_out("\n Read :"); 255 for (i = 0; i < dw; i++) { 256 cli_out(" 0x%08x", read_data[i] & mask_data[i]); 257 } 258 cli_out("\n Wrote :"); 259 for (i = 0; i < dw; i++) { 260 cli_out(" 0x%08x", wrote_data[i] & mask_data[i]); 261 } 262 cli_out("\n Diff :"); 263 for (i = 0; i < dw; i++) { 264 cli_out(" 0x%08x", (read_data[i] ^ wrote_data[i]) & mask_data[i]); 265 } 266 267 { 268 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 269 if (soc_mem_array_read(unit, parm->mem, array_index, 270 copyno, index, reread_data) >= 0) { 271 cli_out("\n Reread:"); 272 for (i = 0; i < dw; i++) { 273 cli_out(" 0x%08x", reread_data[i] & mask_data[i]); 274 } 275 } 276 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 277 } 278 test_error(unit, "\n"); 279 280 return MT_MISCOMPARE_STOP; 281 } 282 283 #ifdef BCM_PETRA_SUPPORT 284 int 285 mt_show_compare_fn(soc_mem_test_t *parm, unsigned array_index, 286 int copyno, int index, 287 uint32 *read_data, uint32 *wrote_data, uint32 *mask_data) 288 { 289 int unit = parm->unit; 290 int i, dw; 291 uint32 reread_data[SOC_MAX_MEM_WORDS]; 292 293 /* soc_pci_analyzer_trigger(unit); */ 294 295 dw = soc_mem_entry_words(unit, parm->mem); 296 297 if (parm->array_index_start != 0 || parm->array_index_end != parm->array_index_start) { 298 cli_out("\n\ntable %s[%u].%s[%d]\n", 299 SOC_MEM_UFNAME(unit, parm->mem), array_index, 300 SOC_BLOCK_NAME(unit, copyno), index); 301 } else { 302 cli_out("\n\ntable %s.%s[%d]\n", 303 SOC_MEM_UFNAME(unit, parm->mem), 304 SOC_BLOCK_NAME(unit, copyno), index); 305 } 306 cli_out("\n Mask :"); 307 for (i = 0; i < dw; i++) { 308 cli_out(" 0x%08x", mask_data[i]); 309 } 310 311 312 cli_out("\n Read :"); 313 for (i = 0; i < dw; i++) { 314 cli_out(" 0x%08x", read_data[i] & mask_data[i]); 315 } 316 cli_out("\n Wrote :"); 317 for (i = 0; i < dw; i++) { 318 cli_out(" 0x%08x", wrote_data[i] & mask_data[i]); 319 } 320 cli_out("\n Diff :"); 321 for (i = 0; i < dw; i++) { 322 cli_out(" 0x%08x", (read_data[i] ^ wrote_data[i]) & mask_data[i]); 323 } 324 if (soc_mem_array_read(unit, parm->mem, array_index, 325 copyno, index, reread_data) >= 0) { 326 cli_out("\n Reread:"); 327 for (i = 0; i < dw; i++) { 328 cli_out(" 0x%08x", reread_data[i] & mask_data[i]); 329 } 330 } 331 332 cli_out("\n"); 333 334 return 0; 335 } 336 #endif 337 338 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) 339 STATIC int 340 mem_test_common_clear(int unit, soc_mem_t mem, int copyno) 341 { 342 #if defined(INCLUDE_MEM_SCAN) || defined(BCM_SRAM_SCAN_SUPPORT) 343 mem_testdata_t *mw = mem_work[unit]; 344 #endif 345 int rv; 346 347 SOC_MEM_TEST_SKIP_CACHE_SET(unit, 1); 348 if ((rv = soc_mem_parity_control(unit, mem, copyno, FALSE)) < 0) { 349 test_error(unit, "Could not disable parity warnings on memory %s\n", 350 SOC_MEM_UFNAME(u, mem)); 351 return -1; 352 } 353 #ifdef INCLUDE_MEM_SCAN 354 if(!SOC_IS_DNX(unit)) { 355 if ((mw->mem_scan = soc_mem_scan_running(unit, &mw->scan_rate, 356 &mw->scan_interval)) > 0) { 357 if (soc_mem_scan_stop(unit)) { 358 return -1; 359 } 360 } 361 } 362 #endif /* INCLUDE_MEM_SCAN */ 363 #ifdef BCM_SRAM_SCAN_SUPPORT 364 if(!SOC_IS_DNX(unit)) { 365 if ((mw->sram_scan = soc_sram_scan_running(unit, &mw->sram_scan_rate, 366 &mw->sram_scan_interval)) > 0) { 367 if (soc_sram_scan_stop(unit)) { 368 return -1; 369 } 370 } 371 } 372 #endif /* BCM_SRAM_SCAN_SUPPORT */ 373 return 0; 374 } 375 376 STATIC int 377 mem_test_common_restore(int unit, soc_mem_t mem, int copyno) 378 { 379 #if defined(INCLUDE_MEM_SCAN) || defined(BCM_SRAM_SCAN_SUPPORT) 380 mem_testdata_t *mw = mem_work[unit]; 381 #endif 382 383 SOC_MEM_TEST_SKIP_CACHE_SET(unit, 0); 384 if (soc_mem_parity_restore(unit, mem, copyno) < 0) { 385 test_error(unit, "Could not enable parity warnings on memory %s\n", 386 SOC_MEM_UFNAME(unit, mem)); 387 return -1; 388 } 389 #ifdef INCLUDE_MEM_SCAN 390 if (mw->mem_scan) { 391 if (soc_mem_scan_start(unit, mw->scan_rate, mw->scan_interval)) { 392 return -1; 393 } 394 } 395 #endif /* INCLUDE_MEM_SCAN */ 396 #ifdef BCM_SRAM_SCAN_SUPPORT 397 if (mw->sram_scan) { 398 if (soc_sram_scan_start(unit, mw->sram_scan_rate, mw->sram_scan_interval)) { 399 return -1; 400 } 401 } 402 #endif /* BCM_SRAM_SCAN_SUPPORT */ 403 404 return 0; 405 } 406 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT */ 407 408 int 409 mem_test_default_init(int u, soc_mem_t mem, void **p) 410 { 411 mem_testdata_t *mw; 412 soc_mem_test_t *parm; 413 char *idx_start_str, *idx_end_str; 414 char *array_idx_start_str, *array_idx_end_str; 415 int copies, blk; 416 int rv = -1; 417 parse_table_t pt; 418 419 420 mw = mem_work[u]; 421 if (mw == NULL) { 422 mw = sal_alloc(sizeof(mem_testdata_t), "memtest"); 423 if (mw == NULL) { 424 cli_out("cannot allocate memory test data\n"); 425 return -1; 426 } 427 sal_memset(mw, 0, sizeof(mem_testdata_t)); 428 mem_work[u] = mw; 429 } 430 parm = &mw->parm; 431 432 parse_table_init(u, &pt); 433 434 435 parse_table_add(&pt, "IndexStart", PQ_STRING, "min", 436 &idx_start_str, NULL); 437 parse_table_add(&pt, "IndexEnd", PQ_STRING, "max", 438 &idx_end_str, NULL); 439 parse_table_add(&pt, "ArrayIndexStart", PQ_STRING, "min", &array_idx_start_str, NULL); 440 parse_table_add(&pt, "ArrayIndexEnd", PQ_STRING, "max", &array_idx_end_str, NULL); 441 parse_table_add(&pt, "IndexInc", PQ_INT, (void *) 1, 442 &parm->index_step, NULL); 443 parse_table_add(&pt, "PatZero", PQ_BOOL|PQ_DFL, 0, 444 &mw->pat_zero, NULL); 445 parse_table_add(&pt, "PatOne", PQ_BOOL|PQ_DFL, 0, 446 &mw->pat_one, NULL); 447 parse_table_add(&pt, "PatFive", PQ_BOOL|PQ_DFL, 0, 448 &mw->pat_five, NULL); 449 parse_table_add(&pt, "PatA", PQ_BOOL|PQ_DFL, 0, 450 &mw->pat_a, NULL); 451 parse_table_add(&pt, "PatChecker", PQ_BOOL|PQ_DFL, 0, 452 &mw->pat_checker, NULL); 453 parse_table_add(&pt, "PatInvckr", PQ_BOOL|PQ_DFL, 0, 454 &mw->pat_invckr, NULL); 455 parse_table_add(&pt, "PatLinear", PQ_BOOL|PQ_DFL, 0, 456 &mw->pat_linear, NULL); 457 parse_table_add(&pt, "PatRandom", PQ_BOOL|PQ_DFL, 0, 458 &mw->pat_random, NULL); 459 parse_table_add(&pt, "PatHex", PQ_BOOL|PQ_DFL, 0, 460 &mw->pat_hex, NULL); 461 parse_table_add(&pt, "HexByte", PQ_INT|PQ_DFL, 0, 462 &mw->hex_byte, NULL); 463 parse_table_add(&pt, "TestByEntry", PQ_BOOL|PQ_DFL, 0, 464 &mw->test_by_entry, NULL); 465 parse_table_add(&pt, "ReVerifyCount", PQ_INT|PQ_DFL, 0, 466 &mw->reverify_count, NULL); 467 parse_table_add(&pt, "ReVerifyDelay", PQ_INT|PQ_DFL, 0, 468 &mw->reverify_delay, NULL); 469 parse_table_add(&pt, "IGnoreErrors", PQ_BOOL|PQ_DFL, 0, 470 &mw->continue_on_error, NULL); 471 parse_table_add(&pt, "ErrorCount", PQ_INT|PQ_DFL, 0, 472 &mw->error_count, NULL); 473 parse_table_add(&pt, "ErrorMax", PQ_INT|PQ_DFL, (void *) 1, 474 &mw->error_max, NULL); 475 parse_table_add(&pt, "ReadCount", PQ_INT|PQ_DFL, (void *) 1, 476 &parm->read_count, NULL); 477 parse_table_add(&pt, "EccAsData", PQ_BOOL|PQ_DFL, (void *)1, 478 &parm->ecc_as_data, NULL); 479 parse_table_add(&pt, "ReportProgress", PQ_BOOL, (void *)1, 480 &parm->report_progress, NULL); 481 482 mw->was_debug_mode = -1; 483 484 if (!mw->inited) { 485 mw->pat_zero = TRUE; 486 mw->pat_one = TRUE; 487 mw->pat_five = TRUE; 488 mw->pat_a = TRUE; 489 mw->pat_checker = TRUE; 490 mw->pat_invckr = TRUE; 491 mw->pat_linear = TRUE; 492 mw->pat_random = TRUE; 493 parm->unit = u; 494 parm->status_cb = mt_status_fn; 495 parm->write_cb = mt_write_fn; 496 parm->read_cb = mt_read_fn; 497 parm->miscompare_cb = mt_miscompare_fn; 498 parm->read_count = 1; 499 parm->ecc_as_data = 1; 500 parm->report_progress = 1; 501 mw->inited = 1; 502 } 503 504 if (parse_default_fill(&pt) < 0) { 505 cli_out("Invalid default fill:\n"); 506 goto done; 507 } 508 509 parm->mem = mem; 510 parm->copyno = COPYNO_ALL; 511 512 if (!soc_mem_is_valid(u, parm->mem) || 513 soc_mem_is_readonly(u, parm->mem)) { 514 { 515 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 516 test_error(u, "Memory %s is invalid or readonly\n", 517 SOC_MEM_UFNAME(u, parm->mem)); 518 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 519 } 520 goto done; 521 } 522 523 if (parm->copyno != COPYNO_ALL && 524 !SOC_MEM_BLOCK_VALID(u, parm->mem, parm->copyno)) { 525 { 526 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 527 test_error(u, 528 "Copy number %d out of range for memory %s\n", 529 parm->copyno, SOC_MEM_UFNAME(u, parm->mem)); 530 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 531 } 532 goto done; 533 } 534 535 parm->index_start = 536 parse_memory_index(parm->unit, parm->mem, idx_start_str); 537 parm->index_end = 538 parse_memory_index(parm->unit, parm->mem, idx_end_str); 539 parm->array_index_start = parse_memory_array_index(parm->unit, parm->mem, array_idx_start_str); 540 parm->array_index_end = parse_memory_array_index(parm->unit, parm->mem, array_idx_end_str); 541 if (parm->array_index_start > parm->array_index_end ) { 542 unsigned temp_ai = parm->array_index_start; 543 parm->array_index_start = parm->array_index_end; 544 parm->array_index_end = temp_ai; 545 } 546 547 { 548 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 549 if (parm->index_start < soc_mem_index_min(parm->unit, parm->mem)) { 550 cli_out("WARNING: Adjust start index from %d to %d " 551 "for memory %s.%s\n", 552 parm->index_start, 553 soc_mem_index_min(parm->unit, parm->mem), 554 SOC_MEM_UFNAME(u, parm->mem), 555 SOC_BLOCK_NAME(u, parm->copyno)); 556 parm->index_start = soc_mem_index_min(parm->unit, parm->mem); 557 } 558 if (parm->index_end > soc_mem_index_max(parm->unit, parm->mem)) { 559 cli_out("WARNING: Adjust end index from %d to %d " 560 "for memory %s.%s\n", 561 parm->index_end, 562 soc_mem_index_max(parm->unit, parm->mem), 563 SOC_MEM_UFNAME(u, parm->mem), 564 SOC_BLOCK_NAME(u, parm->copyno)); 565 parm->index_end = soc_mem_index_max(parm->unit, parm->mem); 566 } 567 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 568 } 569 570 if (parm->index_step == 0 || 571 (parm->index_start < parm->index_end && parm->index_step < 0) || 572 (parm->index_start > parm->index_end && parm->index_step > 0)) { 573 test_error(u, "Illegal index step value\n"); 574 goto done; 575 } 576 577 parm->patterns = 0; 578 if (mw->pat_zero) 579 parm->patterns |= MT_PAT_ZEROES; 580 if (mw->pat_one) 581 parm->patterns |= MT_PAT_ONES; 582 if (mw->pat_five) 583 parm->patterns |= MT_PAT_FIVES; 584 if (mw->pat_a) 585 parm->patterns |= MT_PAT_AS; 586 if (mw->pat_checker) 587 parm->patterns |= MT_PAT_CHECKER; 588 if (mw->pat_invckr) 589 parm->patterns |= MT_PAT_ICHECKER; 590 if (mw->pat_linear) 591 parm->patterns |= MT_PAT_ADDR; 592 if (mw->pat_random) 593 parm->patterns |= MT_PAT_RANDOM; 594 if (mw->pat_hex) { 595 parm->patterns |= MT_PAT_HEX; 596 parm->hex_byte = mw->hex_byte; 597 } 598 parm->test_by_entry = mw->test_by_entry; 599 if (parm->test_by_entry) { 600 /* Not supported unless in fill mode */ 601 mw->reverify_delay = 0; 602 mw->reverify_count = 0; 603 } 604 parm->reverify_delay = mw->reverify_delay; 605 parm->reverify_count = mw->reverify_count; 606 parm->continue_on_error = mw->continue_on_error; 607 parm->error_count = mw->error_count; 608 parm->error_max = mw->error_max; 609 610 /* Place MMU in debug mode if testing an MMU memory */ 611 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 612 if (soc_mem_is_debug(u, parm->mem) && 613 (mw->was_debug_mode = soc_mem_debug_set(u, 0)) < 0) { 614 test_error(u, "Could not put MMU in debug mode\n"); 615 goto done; 616 } 617 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 618 619 #ifdef BCM_DFE_SUPPORT 620 if(SOC_IS_DFE(u)) { 621 parm->frag_index_start[0] = parm->index_start; 622 parm->frag_index_end[0] = parm->index_end; 623 parm->frag_count = 1; 624 SOC_MEM_TEST_SKIP_CACHE_SET(u, 1); 625 /* Disable any parity control */ 626 if ((rv = soc_mem_parity_control(u, parm->mem, parm->copyno, FALSE)) < 0) { 627 test_error(u, "Could not disable parity warnings on memory %s\n", 628 SOC_MEM_UFNAME(u, parm->mem)); 629 goto done; 630 } 631 } else 632 #endif /* BCM_DFE_SUPPORT */ 633 { 634 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) 635 if (mem_test_common_clear(u, parm->mem, parm->copyno)) { 636 goto done; 637 } 638 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT */ 639 } 640 641 { 642 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 643 if (soc_mem_cache_get(u, parm->mem, 644 parm->copyno == COPYNO_ALL ? 645 MEM_BLOCK_ALL : parm->copyno)) { 646 cli_out("WARNING: Caching is enabled on memory %s.%s\n", 647 SOC_MEM_UFNAME(u, parm->mem), 648 SOC_BLOCK_NAME(u, parm->copyno)); 649 } 650 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 651 } 652 653 if (parm->copyno != COPYNO_ALL) { 654 copies = 1; 655 } else { 656 copies = 0; 657 SOC_MEM_BLOCK_ITER(u, parm->mem, blk) { 658 copies += 1; 659 } 660 } 661 mw->progress_total = 662 (_shr_popcount(parm->patterns) * 663 (1 + (parm->read_count * (1 + parm->reverify_count))) * 664 copies * 665 ((parm->index_end > parm->index_start) ? 666 (parm->index_end - parm->index_start + 1) / parm->index_step : 667 (parm->index_end - parm->index_start - 1) / parm->index_step)) * 668 (parm->array_index_end - parm->array_index_start + 1); 669 670 *p = mw; 671 672 rv = 0; 673 674 done: 675 parse_arg_eq_done(&pt); 676 return rv; 677 } 678 679 int 680 mem_test_rw_init(int u, soc_mem_t mem, void **p) 681 { 682 mem_testdata_t *mw; 683 soc_mem_test_t *parm; 684 char *idx_start_str, *idx_end_str; 685 char *array_idx_start_str, *array_idx_end_str; 686 int copies, blk; 687 int rv = -1; 688 parse_table_t pt; 689 690 mw = mem_work[u]; 691 if (mw == NULL) { 692 mw = sal_alloc(sizeof(mem_testdata_t), "memtest"); 693 if (mw == NULL) { 694 cli_out("cannot allocate memory test data\n"); 695 return -1; 696 } 697 sal_memset(mw, 0, sizeof(mem_testdata_t)); 698 mem_work[u] = mw; 699 } 700 parm = &mw->parm; 701 702 parse_table_init(u, &pt); 703 704 705 parse_table_add(&pt, "IndexStart", PQ_STRING, "min", 706 &idx_start_str, NULL); 707 parse_table_add(&pt, "IndexEnd", PQ_STRING, "max", 708 &idx_end_str, NULL); 709 parse_table_add(&pt, "ArrayIndexStart", PQ_STRING, "min", &array_idx_start_str, NULL); 710 parse_table_add(&pt, "ArrayIndexEnd", PQ_STRING, "max", &array_idx_end_str, NULL); 711 parse_table_add(&pt, "IndexInc", PQ_INT, (void *) 1, 712 &parm->index_step, NULL); 713 parse_table_add(&pt, "PatZero", PQ_BOOL|PQ_DFL, 0, 714 &mw->pat_zero, NULL); 715 parse_table_add(&pt, "PatOne", PQ_BOOL|PQ_DFL, 0, 716 &mw->pat_one, NULL); 717 parse_table_add(&pt, "PatFive", PQ_BOOL|PQ_DFL, 0, 718 &mw->pat_five, NULL); 719 parse_table_add(&pt, "PatA", PQ_BOOL|PQ_DFL, 0, 720 &mw->pat_a, NULL); 721 parse_table_add(&pt, "PatChecker", PQ_BOOL|PQ_DFL, 0, 722 &mw->pat_checker, NULL); 723 parse_table_add(&pt, "PatInvckr", PQ_BOOL|PQ_DFL, 0, 724 &mw->pat_invckr, NULL); 725 parse_table_add(&pt, "PatLinear", PQ_BOOL|PQ_DFL, 0, 726 &mw->pat_linear, NULL); 727 parse_table_add(&pt, "PatRandom", PQ_BOOL|PQ_DFL, 0, 728 &mw->pat_random, NULL); 729 parse_table_add(&pt, "PatHex", PQ_BOOL|PQ_DFL, 0, 730 &mw->pat_hex, NULL); 731 parse_table_add(&pt, "HexByte", PQ_INT|PQ_DFL, 0, 732 &mw->hex_byte, NULL); 733 parse_table_add(&pt, "TestByEntry", PQ_BOOL|PQ_DFL, 0, 734 &mw->test_by_entry, NULL); 735 parse_table_add(&pt, "ReVerifyCount", PQ_INT|PQ_DFL, 0, 736 &mw->reverify_count, NULL); 737 parse_table_add(&pt, "ReVerifyDelay", PQ_INT|PQ_DFL, 0, 738 &mw->reverify_delay, NULL); 739 parse_table_add(&pt, "IGnoreErrors", PQ_BOOL|PQ_DFL, 0, 740 &mw->continue_on_error, NULL); 741 parse_table_add(&pt, "ErrorCount", PQ_INT|PQ_DFL, 0, 742 &mw->error_count, NULL); 743 parse_table_add(&pt, "ErrorMax", PQ_INT|PQ_DFL, (void *) 1, 744 &mw->error_max, NULL); 745 parse_table_add(&pt, "ReadCount", PQ_INT|PQ_DFL, (void *) 1, 746 &parm->read_count, NULL); 747 parse_table_add(&pt, "EccAsData", PQ_BOOL|PQ_DFL, (void *)1, 748 &parm->ecc_as_data, NULL); 749 parse_table_add(&pt, "ReportProgress", PQ_BOOL|PQ_DFL, (void *)1, 750 &parm->report_progress, NULL); 751 if (SOC_IS_JERICHO(u) || SOC_IS_DNX(u)) { 752 parse_table_add(&pt, "IncPm", PQ_BOOL, 0, 753 &parm->inc_port_macros, NULL); 754 } 755 mw->was_debug_mode = -1; 756 757 if (!mw->inited) { 758 mw->pat_zero = TRUE; 759 mw->pat_one = TRUE; 760 mw->pat_five = TRUE; 761 mw->pat_a = TRUE; 762 mw->pat_checker = TRUE; 763 mw->pat_invckr = TRUE; 764 mw->pat_linear = TRUE; 765 mw->pat_random = TRUE; 766 parm->unit = u; 767 parm->status_cb = mt_status_fn; 768 parm->write_cb = mt_write_fn; 769 parm->read_cb = mt_read_fn; 770 parm->miscompare_cb = mt_miscompare_fn; 771 parm->read_count = 1; 772 parm->ecc_as_data = 1; 773 parm->report_progress = 1; 774 mw->inited = 1; 775 } 776 /* if (parse_arg_eq(*p, &pt) < 0) { 777 parse_arg_eq_done(&pt); 778 return CMD_USAGE; 779 } */ 780 if (parse_default_fill(&pt) < 0) { 781 cli_out("Invalid default fill:\n"); 782 goto done; 783 } 784 785 786 parm->mem = mem; 787 parm->copyno = COPYNO_ALL; 788 789 if (!soc_mem_is_valid(u, parm->mem) || 790 soc_mem_is_readonly(u, parm->mem)) { 791 { 792 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 793 test_error(u, "Memory %s is invalid or readonly\n", 794 SOC_MEM_UFNAME(u, parm->mem)); 795 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 796 } 797 goto done; 798 } 799 800 if (parm->copyno != COPYNO_ALL && 801 !SOC_MEM_BLOCK_VALID(u, parm->mem, parm->copyno)) { 802 { 803 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 804 test_error(u, 805 "Copy number %d out of range for memory %s\n", 806 parm->copyno, SOC_MEM_UFNAME(u, parm->mem)); 807 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 808 } 809 goto done; 810 } 811 812 parm->index_start = 813 parse_memory_index(parm->unit, parm->mem, idx_start_str); 814 parm->index_end = 815 parse_memory_index(parm->unit, parm->mem, idx_end_str); 816 parm->array_index_start = parse_memory_array_index(parm->unit, parm->mem, array_idx_start_str); 817 parm->array_index_end = parse_memory_array_index(parm->unit, parm->mem, array_idx_end_str); 818 if (parm->array_index_start > parm->array_index_end ) { 819 unsigned temp_ai = parm->array_index_start; 820 parm->array_index_start = parm->array_index_end; 821 parm->array_index_end = temp_ai; 822 } 823 824 { 825 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 826 if (parm->index_start < soc_mem_index_min(parm->unit, parm->mem)) { 827 cli_out("WARNING: Adjust start index from %d to %d " 828 "for memory %s.%s\n", 829 parm->index_start, 830 soc_mem_index_min(parm->unit, parm->mem), 831 SOC_MEM_UFNAME(u, parm->mem), 832 SOC_BLOCK_NAME(u, parm->copyno)); 833 parm->index_start = soc_mem_index_min(parm->unit, parm->mem); 834 } 835 if (parm->index_end > soc_mem_index_max(parm->unit, parm->mem)) { 836 cli_out("WARNING: Adjust end index from %d to %d " 837 "for memory %s.%s\n", 838 parm->index_end, 839 soc_mem_index_max(parm->unit, parm->mem), 840 SOC_MEM_UFNAME(u, parm->mem), 841 SOC_BLOCK_NAME(u, parm->copyno)); 842 parm->index_end = soc_mem_index_max(parm->unit, parm->mem); 843 } 844 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 845 } 846 847 if (parm->index_step == 0 || 848 (parm->index_start < parm->index_end && parm->index_step < 0) || 849 (parm->index_start > parm->index_end && parm->index_step > 0)) { 850 test_error(u, "Illegal index step value\n"); 851 goto done; 852 } 853 854 #ifdef BCM_PETRA_SUPPORT 855 if (SOC_IS_ARAD(u) || SOC_IS_DNX(u)) { 856 parm->frag_index_start[0] = parm->index_start; 857 parm->frag_index_end[0] = parm->index_start; 858 parm->frag_index_start[1] = parm->index_end; 859 parm->frag_index_end[1] = parm->index_end; 860 parm->frag_count = 2; 861 862 } 863 #endif 864 865 parm->patterns = 0; 866 if (mw->pat_zero) 867 parm->patterns |= MT_PAT_ZEROES; 868 if (mw->pat_one) 869 parm->patterns |= MT_PAT_ONES; 870 if (mw->pat_five) 871 parm->patterns |= MT_PAT_FIVES; 872 if (mw->pat_a) 873 parm->patterns |= MT_PAT_AS; 874 if (mw->pat_checker) 875 parm->patterns |= MT_PAT_CHECKER; 876 if (mw->pat_invckr) 877 parm->patterns |= MT_PAT_ICHECKER; 878 if (mw->pat_linear) 879 parm->patterns |= MT_PAT_ADDR; 880 if (mw->pat_random) 881 parm->patterns |= MT_PAT_RANDOM; 882 if (mw->pat_hex) { 883 parm->patterns |= MT_PAT_HEX; 884 parm->hex_byte = mw->hex_byte; 885 } 886 parm->test_by_entry = mw->test_by_entry; 887 if (parm->test_by_entry) { 888 /* Not supported unless in fill mode */ 889 mw->reverify_delay = 0; 890 mw->reverify_count = 0; 891 } 892 parm->reverify_delay = mw->reverify_delay; 893 parm->reverify_count = mw->reverify_count; 894 parm->continue_on_error = mw->continue_on_error; 895 parm->error_count = mw->error_count; 896 parm->error_max = mw->error_max; 897 898 /* Place MMU in debug mode if testing an MMU memory */ 899 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 900 if (soc_mem_is_debug(u, parm->mem) && 901 (mw->was_debug_mode = soc_mem_debug_set(u, 0)) < 0) { 902 test_error(u, "Could not put MMU in debug mode\n"); 903 goto done; 904 } 905 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 906 907 #if defined (BCM_DFE_SUPPORT) || defined(BCM_DNXF_SUPPORT) 908 if(SOC_IS_DFE(u) || SOC_IS_DNXF(u)) { 909 SOC_MEM_TEST_SKIP_CACHE_SET(u, 1); 910 /* Disable any parity control */ 911 if ((rv = soc_mem_parity_control(u, parm->mem, parm->copyno, FALSE)) < 0) { 912 test_error(u, "Could not disable parity warnings on memory %s\n", 913 SOC_MEM_UFNAME(u, parm->mem)); 914 goto done; 915 } 916 } else 917 #endif /* BCM_DFE_SUPPORT */ 918 { 919 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) 920 if (!SOC_IS_DNX(u)) { 921 if (mem_test_common_clear(u, parm->mem, parm->copyno)) { 922 goto done; 923 } 924 } 925 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT */ 926 } 927 928 { 929 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 930 if (soc_mem_cache_get(u, parm->mem, 931 parm->copyno == COPYNO_ALL ? 932 MEM_BLOCK_ALL : parm->copyno)) { 933 cli_out("WARNING: Caching is enabled on memory %s.%s\n", 934 SOC_MEM_UFNAME(u, parm->mem), 935 SOC_BLOCK_NAME(u, parm->copyno)); 936 } 937 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 938 } 939 940 941 if (parm->copyno != COPYNO_ALL) { 942 copies = 1; 943 } else { 944 copies = 0; 945 SOC_MEM_BLOCK_ITER(u, parm->mem, blk) { 946 copies += 1; 947 } 948 } 949 950 mw->progress_total = 951 (_shr_popcount(parm->patterns) * 952 (1 + (parm->read_count * (1 + parm->reverify_count))) * 953 copies * 954 ((parm->index_end > parm->index_start) ? 955 (parm->index_end - parm->index_start + 1) / parm->index_step : 956 (parm->index_end - parm->index_start - 1) / parm->index_step)) * 957 (parm->array_index_end - parm->array_index_start + 1); 958 959 *p = mw; 960 /* adds on for tr 7*/ 961 if (parm->index_end > parm->index_start) { 962 parm->index_step = parm->index_end - parm->index_start ; 963 } 964 965 rv = 0; 966 967 done: 968 parse_arg_eq_done(&pt); 969 return rv; 970 } 971 972 char tr50_test_usage[] = 973 "TR50 (single memory write & read test with a sophisticated patterns) usage:\n" 974 " \n" 975 #ifdef COMPILER_STRING_CONST_LIMIT 976 "\nFull documentation cannot be displayed with -pedantic compiler\n"; 977 #else 978 979 "M=<value> Memory - The memory to be checked\n" 980 "IS=<value> IndexStart - Starting index\n" 981 "IE=<value> IndexEnd - Ending index\n" 982 "AIS=<value> ArrayIndexStart - Array starting index (in case of array memory)\n" 983 "AIE=<value> ArrayIndexEnd - Array ending index (in case of array memory)\n" 984 "II=<value> IndexInc - index increment value \n" 985 "PZ=<value> PatZero - fills memory with 0's\n" 986 "PO=<value> PatOne - fills memory with 1's\n" 987 "PF=<value> PatFive - fills memory with 5's\n" 988 "PA=<value> PatA - fills memory with a's\n" 989 "PC=<value> PatChecker - fills memory with alternating 1010... and 0101... This is useful to detecting horizontally or vertically shorted data lines (in cases where the RAM layout is plain)\n" 990 "PI=<value> PatInvckr - fills memory with alternating 0101... and 1010... This is useful to detecting horizontally or vertically shorted data lines (in cases where the RAM layout is plain)\n" 991 "PL=<value> PatLinear - Write a unique value in every location to make sure all locations are distinct (detect shorted address bits). The unique value used is the address so dumping the failed memory may indicate where the bad data came from.\n" 992 "PR=<value> PatRandom - Write a unique value in every location using pseudo-random data\n" 993 "PH=<value> PatHex - Write a value specified by the user\n" 994 "HB=<value> HexByte - the actual value used in ph option\n" 995 "TBE=<value> TestByEntry - Test each memory line\n" 996 "RVC=<value>\n" 997 "IGE=<value> IGnoreErrors - Do not abort test due to errors\n" 998 "EC=<value> ErrorCount - Count of miss-compares so far\n" 999 "Help=<1/0> - Specifies if tr 7 help is on and exit or off (off by default)\n" 1000 "To enable printing values (write/read) of each memory proceed: debug +test +verb\n" 1001 "\n"; 1002 #endif 1003 1004 1005 int 1006 mem_test_init(int u, args_t *a, void **p) 1007 { 1008 mem_testdata_t *mw; 1009 soc_mem_test_t *parm; 1010 char *mem_name; 1011 char *idx_start_str, *idx_end_str; 1012 char *array_idx_start_str, *array_idx_end_str; 1013 int copies, blk; 1014 int rv = -1; 1015 uint32 help_status_default = 0; 1016 uint32 help_status=0; 1017 parse_table_t pt; 1018 1019 mw = mem_work[u]; 1020 if (mw == NULL) { 1021 mw = sal_alloc(sizeof(mem_testdata_t), "memtest"); 1022 if (mw == NULL) { 1023 cli_out("%s: cannot allocate memory test data\n", ARG_CMD(a)); 1024 return -1; 1025 } 1026 sal_memset(mw, 0, sizeof(mem_testdata_t)); 1027 mem_work[u] = mw; 1028 } 1029 parm = &mw->parm; 1030 1031 parse_table_init(u, &pt); 1032 parse_table_add(&pt, "Memory", PQ_STRING, "", 1033 &mem_name, NULL); 1034 parse_table_add(&pt, "IndexStart", PQ_STRING, "min", 1035 &idx_start_str, NULL); 1036 parse_table_add(&pt, "IndexEnd", PQ_STRING, "max", 1037 &idx_end_str, NULL); 1038 parse_table_add(&pt, "ArrayIndexStart", PQ_STRING, "min", 1039 &array_idx_start_str, NULL); 1040 parse_table_add(&pt, "ArrayIndexEnd", PQ_STRING, "max", 1041 &array_idx_end_str, NULL); 1042 parse_table_add(&pt, "IndexInc", PQ_INT, (void *) 1, 1043 &parm->index_step, NULL); 1044 1045 parse_table_add(&pt, "PatZero", PQ_BOOL|PQ_DFL, 0, 1046 &mw->pat_zero, NULL); 1047 parse_table_add(&pt, "PatOne", PQ_BOOL|PQ_DFL, 0, 1048 &mw->pat_one, NULL); 1049 parse_table_add(&pt, "PatFive", PQ_BOOL|PQ_DFL, 0, 1050 &mw->pat_five, NULL); 1051 parse_table_add(&pt, "PatA", PQ_BOOL|PQ_DFL, 0, 1052 &mw->pat_a, NULL); 1053 parse_table_add(&pt, "PatChecker", PQ_BOOL|PQ_DFL, 0, 1054 &mw->pat_checker, NULL); 1055 parse_table_add(&pt, "PatInvckr", PQ_BOOL|PQ_DFL, 0, 1056 &mw->pat_invckr, NULL); 1057 parse_table_add(&pt, "PatLinear", PQ_BOOL|PQ_DFL, 0, 1058 &mw->pat_linear, NULL); 1059 parse_table_add(&pt, "PatRandom", PQ_BOOL|PQ_DFL, 0, 1060 &mw->pat_random, NULL); 1061 parse_table_add(&pt, "PatHex", PQ_BOOL|PQ_DFL, 0, 1062 &mw->pat_hex, NULL); 1063 parse_table_add(&pt, "HexByte", PQ_INT|PQ_DFL, 0, 1064 &mw->hex_byte, NULL); 1065 parse_table_add(&pt, "TestByEntry", PQ_BOOL|PQ_DFL, 0, 1066 &mw->test_by_entry, NULL); 1067 parse_table_add(&pt, "ReVerifyCount", PQ_INT|PQ_DFL, 0, 1068 &mw->reverify_count, NULL); 1069 parse_table_add(&pt, "ReVerifyDelay", PQ_INT|PQ_DFL, 0, 1070 &mw->reverify_delay, NULL); 1071 parse_table_add(&pt, "IGnoreErrors", PQ_BOOL|PQ_DFL, 0, 1072 &mw->continue_on_error, NULL); 1073 parse_table_add(&pt, "ErrorCount", PQ_INT|PQ_DFL, 0, 1074 &mw->error_count, NULL); 1075 parse_table_add(&pt, "ErrorMax", PQ_INT|PQ_DFL, (void *) 1, 1076 &mw->error_max, NULL); 1077 parse_table_add(&pt, "ReadCount", PQ_INT|PQ_DFL, (void *) 1, 1078 &parm->read_count, NULL); 1079 parse_table_add(&pt, "EccAsData", PQ_BOOL|PQ_DFL, (void *)1, 1080 &parm->ecc_as_data, NULL); 1081 parse_table_add(&pt, "ReportProgress", PQ_BOOL|PQ_DFL, (void *)1, 1082 &parm->report_progress, NULL); 1083 parse_table_add(&pt, "Help", PQ_DFL|PQ_INT, &help_status_default, &help_status, NULL); 1084 1085 mw->was_debug_mode = -1; 1086 1087 if (!mw->inited) { 1088 mw->pat_zero = TRUE; 1089 mw->pat_one = TRUE; 1090 mw->pat_five = TRUE; 1091 mw->pat_a = TRUE; 1092 mw->pat_checker = TRUE; 1093 mw->pat_invckr = TRUE; 1094 mw->pat_linear = TRUE; 1095 mw->pat_random = TRUE; 1096 parm->unit = u; 1097 parm->status_cb = mt_status_fn; 1098 parm->write_cb = mt_write_fn; 1099 parm->read_cb = mt_read_fn; 1100 parm->miscompare_cb = mt_miscompare_fn; 1101 parm->read_count = 1; 1102 parm->ecc_as_data = 1; 1103 parm->report_progress = 1; 1104 mw->inited = 1; 1105 } 1106 1107 if (parse_arg_eq(a, &pt) < 0) { 1108 cli_out("%s: Invalid option: %s\n", 1109 ARG_CMD(a), ARG_CUR(a)); 1110 goto done; 1111 } 1112 1113 if (help_status == 1) { 1114 cli_out("%s\n",tr50_test_usage); 1115 goto done; 1116 } 1117 1118 #ifdef BCM_CMICX_SUPPORT 1119 if (soc_feature(u, soc_feature_cmicx)) { 1120 if (sal_strcasecmp(mem_name,"QSPI_FLASH") == 0) { 1121 *p = mw; 1122 parm->index_start = sal_ctoi(idx_start_str, 0); 1123 parm->index_end = sal_ctoi(idx_end_str, 0); 1124 return (qspi_flash_test_init(u,a,&mw->parm)); 1125 } 1126 } 1127 #endif 1128 if (ARG_CNT(a) != 0) { 1129 cli_out("%s: extra options starting with \"%s\"\n", 1130 ARG_CMD(a), ARG_CUR(a)); 1131 goto done; 1132 } 1133 1134 if (parse_memory_name(u, 1135 &parm->mem, 1136 mem_name, 1137 &parm->copyno, 1138 0) < 0) { 1139 test_error(u, "Memory \"%s\" is invalid or Missing\n", mem_name); 1140 goto done; 1141 } 1142 1143 #if defined(BCM_DFE_SUPPORT) || defined(BCM_PETRA_SUPPORT) 1144 SOC_MEM_ALIAS_TO_ORIG(u, parm->mem); 1145 #endif 1146 1147 if (!soc_mem_is_valid(u, parm->mem) || 1148 soc_mem_is_readonly(u, parm->mem) 1149 #ifdef BCM_SAND_SUPPORT 1150 || 1151 (SOC_IS_SAND(u) && (soc_mem_is_writeonly(u, parm->mem) || soc_mem_is_signal(u, parm->mem))) 1152 #endif 1153 1154 ) { 1155 { 1156 #if defined(BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 1157 test_error(u, "Memory %s is invalid/readonly/writeonly/cannot be compared \n", 1158 SOC_MEM_UFNAME(u, parm->mem)); 1159 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 1160 } 1161 goto done; 1162 } 1163 #if defined (BCM_TOMAHAWK2_SUPPORT) 1164 if (soc_feature(u,soc_feature_no_vfp) && 1165 ((parm->mem >= VFP_TCAMm && parm->mem <= VFP_TCAM_PIPE3m) || 1166 (parm->mem >= VFP_POLICY_TABLEm && parm->mem <= VFP_POLICY_TABLE_PIPE3m))) { 1167 test_msg("VFP is not supported.Cannot test memory %s \n", SOC_MEM_UFNAME(u, parm->mem)); 1168 rv = SOC_E_UNAVAIL; 1169 goto done; 1170 } 1171 #endif /*BCM_TOMAHAWK2_SUPPORT*/ 1172 1173 #ifdef BCM_PETRA_SUPPORT 1174 if(SOC_IS_ARAD(u)) { 1175 switch(parm->mem) { 1176 case BRDC_FSRD_FSRD_WL_EXT_MEMm: 1177 case IQM_MEM_8000000m: 1178 case NBI_TBINS_MEMm: 1179 case NBI_RBINS_MEMm: 1180 case PORT_WC_UCMEM_DATAm: 1181 case ECI_MBU_MEMm: 1182 case EGQ_CBMm: 1183 case EGQ_RDMUCm: 1184 case IHP_MEM_740000m: 1185 case IHP_MEM_9E0000m: 1186 case IHP_MEM_C50000m: 1187 case PPDB_A_OEMA_MANAGEMENT_REQUESTm: 1188 case PPDB_A_OEMB_MANAGEMENT_REQUESTm: 1189 test_error(u, "Memory %s is invalid/readonly/writeonly/signal \n", 1190 SOC_MEM_UFNAME(u, parm->mem)); 1191 goto done; 1192 1193 case PPDB_A_TCAM_BANKm: 1194 case PPDB_A_TCAM_BANK_COMMANDm: 1195 case PPDB_A_TCAM_BANK_REPLYm: 1196 case KAPS_TCMm: 1197 test_error(u, "Memory %s is not supported for this kind of test\n", 1198 SOC_MEM_UFNAME(u, parm->mem)); 1199 goto done; 1200 default: 1201 break; 1202 } 1203 } 1204 1205 if (SOC_IS_JERICHO_PLUS(u)) 1206 { 1207 if ((parm->mem == IHB_FEC_PATH_SELECTm) || (parm->mem == IHP_VTT_PATH_SELECTm)) 1208 { 1209 test_error(u, "Memory %s is not allowed to direct access\n", 1210 SOC_MEM_UFNAME(u, parm->mem)); 1211 goto done; 1212 } 1213 } 1214 #endif 1215 1216 #if defined (BCM_DFE_SUPPORT) 1217 if(SOC_IS_DFE(u)) 1218 { 1219 int rv; 1220 int is_filtered = 0; 1221 1222 rv = MBCM_DFE_DRIVER_CALL(u, mbcm_dfe_drv_test_mem_filter, (u, parm->mem, &is_filtered)); 1223 if (rv != SOC_E_NONE) 1224 { 1225 return rv; 1226 } 1227 if (is_filtered) 1228 { 1229 test_error(u, "Memory %s is invalid/readonly/writeonly/signal \n", 1230 SOC_MEM_UFNAME(u, parm->mem)); 1231 goto done; 1232 } 1233 } 1234 #endif /*BCM_DFE_SUPPORT*/ 1235 1236 if (parm->copyno != COPYNO_ALL && 1237 !SOC_MEM_BLOCK_VALID(u, parm->mem, parm->copyno)) { 1238 { 1239 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 1240 test_error(u, 1241 "Copy number %d out of range for memory %s\n", 1242 parm->copyno, SOC_MEM_UFNAME(u, parm->mem)); 1243 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 1244 } 1245 goto done; 1246 } 1247 1248 parm->index_start = parse_memory_index(parm->unit, parm->mem, idx_start_str); 1249 parm->index_end = parse_memory_index(parm->unit, parm->mem, idx_end_str); 1250 parm->array_index_start = parse_memory_array_index(parm->unit, parm->mem, array_idx_start_str); 1251 parm->array_index_end = parse_memory_array_index(parm->unit, parm->mem, array_idx_end_str); 1252 if (parm->array_index_start > parm->array_index_end ) { 1253 unsigned temp_ai = parm->array_index_start; 1254 parm->array_index_start = parm->array_index_end; 1255 parm->array_index_end = temp_ai; 1256 cli_out("WARNING: switching start and end array indices to %u-%u\n", 1257 parm->array_index_start, parm->array_index_end); 1258 } 1259 1260 { 1261 #if defined(BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 1262 if (parm->index_start < soc_mem_index_min(parm->unit, parm->mem)) { 1263 cli_out("WARNING: Adjust start index from %d to %d " 1264 "for memory %s.%s\n", 1265 parm->index_start, 1266 soc_mem_index_min(parm->unit, parm->mem), 1267 SOC_MEM_UFNAME(u, parm->mem), 1268 SOC_BLOCK_NAME(u, parm->copyno)); 1269 parm->index_start = soc_mem_index_min(parm->unit, parm->mem); 1270 } 1271 1272 if (parm->index_end > soc_mem_index_max(parm->unit, parm->mem)) { 1273 cli_out("WARNING: Adjust end index from %d to %d " 1274 "for memory %s.%s\n", 1275 parm->index_end, 1276 soc_mem_index_max(parm->unit, parm->mem), 1277 SOC_MEM_UFNAME(u, parm->mem), 1278 SOC_BLOCK_NAME(u, parm->copyno)); 1279 parm->index_end = soc_mem_index_max(parm->unit, parm->mem); 1280 } 1281 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 1282 } 1283 1284 if (parm->index_step == 0 || 1285 (parm->index_start < parm->index_end && parm->index_step < 0) || 1286 (parm->index_start > parm->index_end && parm->index_step > 0)) { 1287 if (soc_feature(parm->unit,soc_feature_esm_support)) { 1288 #if defined(BCM_ESW_SUPPORT) 1289 if ((parm->mem == L3_DEFIPm && SOC_MEM_IS_ENABLED(u, L3_DEFIPm)) || 1290 (parm->mem == L3_DEFIP_ONLYm && SOC_MEM_IS_ENABLED(u, L3_DEFIP_ONLYm)) || 1291 (parm->mem == L3_DEFIP_DATA_ONLYm && SOC_MEM_IS_ENABLED(u, L3_DEFIP_DATA_ONLYm)) || 1292 (parm->mem == L3_DEFIP_HIT_ONLYm && SOC_MEM_IS_ENABLED(u, L3_DEFIP_DATA_ONLYm)) || 1293 (parm->mem == L3_DEFIP_PAIR_128_DATA_ONLYm && SOC_MEM_IS_ENABLED(u, L3_DEFIP_PAIR_128_DATA_ONLYm)) || 1294 (parm->mem == L3_DEFIP_PAIR_128_HIT_ONLYm && SOC_MEM_IS_ENABLED(u, L3_DEFIP_PAIR_128_HIT_ONLYm))) { 1295 /* The above internal memories will not be supported if External TCAM is present. 1296 * These memories are set to 0 and hence can not run the test on these memories.*/ 1297 return BCM_E_UNAVAIL; 1298 } else { 1299 test_error(u, "Illegal index step value\n"); 1300 goto done; 1301 } 1302 #endif /* BCM_ESW_SUPPORT */ 1303 } 1304 else { 1305 test_error(u, "Illegal index step value\n"); 1306 goto done; 1307 } 1308 } 1309 1310 parm->patterns = 0; 1311 if (mw->pat_zero) 1312 parm->patterns |= MT_PAT_ZEROES; 1313 if (mw->pat_one) 1314 parm->patterns |= MT_PAT_ONES; 1315 if (mw->pat_five) 1316 parm->patterns |= MT_PAT_FIVES; 1317 if (mw->pat_a) 1318 parm->patterns |= MT_PAT_AS; 1319 if (mw->pat_checker) 1320 parm->patterns |= MT_PAT_CHECKER; 1321 if (mw->pat_invckr) 1322 parm->patterns |= MT_PAT_ICHECKER; 1323 if (mw->pat_linear) 1324 parm->patterns |= MT_PAT_ADDR; 1325 if (mw->pat_random) 1326 parm->patterns |= MT_PAT_RANDOM; 1327 if (mw->pat_hex) { 1328 parm->patterns |= MT_PAT_HEX; 1329 parm->hex_byte = mw->hex_byte; 1330 } 1331 parm->test_by_entry = mw->test_by_entry; 1332 if (parm->test_by_entry) { 1333 /* Not supported unless in fill mode */ 1334 mw->reverify_delay = 0; 1335 mw->reverify_count = 0; 1336 } 1337 parm->reverify_delay = mw->reverify_delay; 1338 parm->reverify_count = mw->reverify_count; 1339 parm->continue_on_error = mw->continue_on_error; 1340 parm->error_count = mw->error_count; 1341 parm->error_max = mw->error_max; 1342 1343 /* Place MMU in debug mode if testing an MMU memory */ 1344 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 1345 if (soc_mem_is_debug(u, parm->mem) && 1346 (mw->was_debug_mode = soc_mem_debug_set(u, 0)) < 0) { 1347 test_error(u, "Could not put MMU in debug mode\n"); 1348 goto done; 1349 } 1350 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 1351 1352 /* Disable non-atomic TCAM write handling */ 1353 mw->saved_tcam_protect_write = SOC_CONTROL(u)->tcam_protect_write; 1354 SOC_CONTROL(u)->tcam_protect_write = FALSE; 1355 1356 #if defined (BCM_DFE_SUPPORT) || defined(BCM_DNXF_SUPPORT) 1357 if(SOC_IS_DFE(u) || SOC_IS_DNXF(u)) { 1358 SOC_MEM_TEST_SKIP_CACHE_SET(u, 1); 1359 /* Disable any parity control */ 1360 if ((rv = soc_mem_parity_control(u, parm->mem, parm->copyno, FALSE)) < 0) { 1361 test_error(u, "Could not disable parity warnings on memory %s\n", 1362 SOC_MEM_UFNAME(u, parm->mem)); 1363 goto done; 1364 } 1365 } else 1366 #endif /* BCM_DFE_SUPPORT */ 1367 { 1368 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DNX_SUPPORT) 1369 if (mem_test_common_clear(u, parm->mem, parm->copyno)) { 1370 goto done; 1371 } 1372 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT */ 1373 } 1374 1375 { 1376 #if defined(BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 1377 if (soc_mem_cache_get(u, parm->mem, 1378 parm->copyno == COPYNO_ALL ? 1379 MEM_BLOCK_ALL : parm->copyno)) { 1380 cli_out("WARNING: Caching is enabled on memory %s.%s\n", 1381 SOC_MEM_UFNAME(u, parm->mem), 1382 SOC_BLOCK_NAME(u, parm->copyno)); 1383 } 1384 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 1385 } 1386 1387 #if defined(BCM_ESW_SUPPORT) || defined (BCM_SAND_SUPPORT) 1388 if ((rv = soc_mem_cpu_write_control(u, parm->mem, parm->copyno, 1389 TRUE, &mw->orig_enable)) < 0) { 1390 test_error(u, "Could not enable exclusive cpu write on memory %s\n", 1391 SOC_MEM_UFNAME(u, parm->mem)); 1392 goto done; 1393 } 1394 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT */ 1395 1396 /* 1397 * Turn off L2 task to keep it from going crazy if L2 memory is 1398 * being tested. 1399 */ 1400 1401 #ifdef BCM_XGS_SWITCH_SUPPORT 1402 if (soc_feature(u, soc_feature_arl_hashed)) { 1403 (void)soc_l2x_stop(u); 1404 } 1405 #endif /* BCM_XGS_SWITCH_SUPPORT */ 1406 #ifdef BCM_SHADOW_SUPPORT 1407 if (SOC_IS_SHADOW(u) && (parm->mem == EGR_PERQ_XMT_COUNTERSm)) { 1408 rv = soc_reg_field32_modify(u, EGR_EDB_HW_CONTROLr, REG_PORT_ANY, 1409 XGS_COUNTER_COMPAT_MODEf, 1); 1410 if (rv != SOC_E_NONE) { 1411 goto done; 1412 } 1413 } 1414 if (SOC_IS_SHADOW(u) && SOC_BLOCK_IS_CMP(u, 1415 SOC_MEM_BLOCK_MIN(u, parm->mem), SOC_BLK_MS_ISEC)) { 1416 rv = soc_reg_field32_modify(u, ISEC_MASTER_CTRLr, 1, 1417 XGS_COUNTER_COMPAT_MODEf, 1); 1418 if (rv != SOC_E_NONE) { 1419 return -1; 1420 } 1421 rv = soc_reg_field32_modify(u, ISEC_MASTER_CTRLr, 5, 1422 XGS_COUNTER_COMPAT_MODEf, 1); 1423 if (rv != SOC_E_NONE) { 1424 return -1; 1425 } 1426 } 1427 /* Disable WRED */ 1428 if (SOC_IS_SHADOW(u)) { 1429 uint32 rval; 1430 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(u, &rval)); 1431 soc_reg_field_set(u, MISCCONFIGr, &rval, 1432 METERING_CLK_ENf, 0); 1433 soc_reg_field_set(u, MISCCONFIGr, &rval, 1434 REFRESH_ENf, 0); 1435 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(u, rval)); 1436 } 1437 if (SOC_IS_SHADOW(u) && SOC_BLOCK_IS_CMP(u, 1438 SOC_MEM_BLOCK_MIN(u, parm->mem), SOC_BLK_MS_ESEC)) { 1439 rv = soc_reg_field32_modify(u, ESEC_MASTER_CTRLr, 1, 1440 XGS_COUNTER_COMPAT_MODEf, 1); 1441 if (rv != SOC_E_NONE) { 1442 return -1; 1443 } 1444 rv = soc_reg_field32_modify(u, ESEC_MASTER_CTRLr, 5, 1445 XGS_COUNTER_COMPAT_MODEf, 1); 1446 if (rv != SOC_E_NONE) { 1447 return -1; 1448 } 1449 } 1450 #endif 1451 1452 /* 1453 * Turn off FP. 1454 * Required when testing FP and METERING memories or tests will fail. 1455 * We don't care about the return value as the BCM layer may not have 1456 * been initialized at all. 1457 */ 1458 (void)bcm_field_detach(u); 1459 1460 #ifdef BCM_TRIUMPH_SUPPORT 1461 if (soc_feature(u, soc_feature_esm_support)) { 1462 /* Some tables have dependency on the content of other table */ 1463 switch (parm->mem) { 1464 case EXT_ACL360_TCAM_DATAm: 1465 case EXT_ACL360_TCAM_DATA_IPV6_SHORTm: 1466 rv = soc_mem_clear(u, EXT_ACL360_TCAM_MASKm, MEM_BLOCK_ALL, TRUE); 1467 break; 1468 case EXT_ACL432_TCAM_DATAm: 1469 case EXT_ACL432_TCAM_DATA_IPV6_LONGm: 1470 case EXT_ACL432_TCAM_DATA_L2_IPV4m: 1471 case EXT_ACL432_TCAM_DATA_L2_IPV6m: 1472 rv = soc_mem_clear(u, EXT_ACL432_TCAM_MASKm, MEM_BLOCK_ALL, TRUE); 1473 break; 1474 default: 1475 break; 1476 } 1477 if (rv != SOC_E_NONE) { 1478 goto done; 1479 } 1480 } 1481 #endif /* BCM_TRIUMPH_SUPPORT */ 1482 #ifdef BCM_TRIUMPH3_SUPPORT 1483 if (soc_feature(u, soc_feature_etu_support)) { 1484 /* Some tables have dependency on the content of other table */ 1485 switch (parm->mem) { 1486 case EXT_ACL480_TCAM_DATAm: 1487 if (SOC_FAILURE(soc_mem_clear(u, EXT_ACL480_TCAM_MASKm, 1488 MEM_BLOCK_ALL, TRUE))) 1489 { 1490 test_error(u, "Failed to clear EXT_ACL360_TCAM_MASKm\n"); 1491 parse_arg_eq_done(&pt); 1492 return -1; 1493 } 1494 break; 1495 default: 1496 break; 1497 } 1498 } 1499 #endif /* BCM_TRIUMPH3_SUPPORT */ 1500 1501 if (parm->copyno != COPYNO_ALL) { 1502 copies = 1; 1503 } else { 1504 copies = 0; 1505 SOC_MEM_BLOCK_ITER(u, parm->mem, blk) { 1506 copies += 1; 1507 } 1508 } 1509 mw->progress_total = 1510 (_shr_popcount(parm->patterns) * 1511 (1 + (parm->read_count * (1 + parm->reverify_count))) * 1512 copies * 1513 ((parm->index_end > parm->index_start) ? 1514 (parm->index_end - parm->index_start + 1) / parm->index_step : 1515 (parm->index_end - parm->index_start - 1) / parm->index_step)) * 1516 (parm->array_index_end - parm->array_index_start + 1); 1517 1518 parm->index_total = parm->index_start < parm->index_end ? 1519 parm->index_end - parm->index_start : 1520 parm->index_start - parm->index_end; 1521 parm->frag_index_start[0] = parm->index_start; 1522 parm->frag_index_end[0] = parm->index_end; 1523 parm->frag_count = 1; 1524 *p = mw; 1525 #ifdef BCM_PETRA_SUPPORT 1526 if (SOC_IS_ARAD(u)) 1527 { 1528 1529 bcm_common_linkscan_enable_set(u,0); 1530 soc_counter_stop(u); 1531 } 1532 #endif 1533 rv = 0; 1534 1535 done: 1536 parse_arg_eq_done(&pt); 1537 return rv; 1538 } 1539 1540 /* 1541 * Memory Test 1542 */ 1543 1544 int 1545 mem_test(int u, args_t *a, void *p) 1546 { 1547 mem_testdata_t *mw = p; 1548 int rv; 1549 1550 #ifdef BCM_CMICX_SUPPORT 1551 if (soc_feature(u, soc_feature_cmicx) && mw->parm.userdata !=NULL) { 1552 if (sal_strcasecmp(mw->parm.userdata,"QSPI_FLASH") == 0) { 1553 return (qspi_flash_test_run(u,a,&mw->parm)); 1554 } 1555 } 1556 #endif 1557 1558 progress_init(mw->progress_total, 3, 0); 1559 1560 rv = soc_mem_test(&mw->parm); 1561 1562 progress_done(); 1563 1564 return rv; 1565 } 1566 1567 int 1568 mem_test_done(int unit, void *p) 1569 { 1570 mem_testdata_t *mw = p; 1571 #ifdef BCM_SHADOW_SUPPORT 1572 int rv = SOC_E_NONE; 1573 #endif 1574 1575 #ifdef BCM_CMICX_SUPPORT 1576 if (soc_feature(unit, soc_feature_cmicx) && mw->parm.userdata !=NULL) { 1577 if (sal_strcasecmp(mw->parm.userdata,"QSPI_FLASH") == 0) { 1578 return (qspi_flash_test_done(unit,&mw->parm)); 1579 } 1580 } 1581 #endif 1582 1583 if (mw) { 1584 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined(BCM_SHADOW_SUPPORT) || defined (BCM_DNXF_SUPPORT) 1585 soc_mem_test_t *parm = &mw->parm; 1586 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT ||| BCM_SHADOW_SUPPORT */ 1587 1588 /* Take MMU out of debug mode if testing a CBP memory */ 1589 1590 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 1591 if (soc_mem_is_debug(parm->unit, parm->mem) && 1592 mw->was_debug_mode >= 0 && 1593 soc_mem_debug_set(unit, mw->was_debug_mode) < 0) { 1594 test_error(unit, "Could not restore previous MMU debug state\n"); 1595 return -1; 1596 } 1597 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 1598 1599 /* Restore non-atomic TCAM write handling status */ 1600 SOC_CONTROL(unit)->tcam_protect_write = mw->saved_tcam_protect_write; 1601 1602 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNXF_SUPPORT) 1603 if (soc_mem_cpu_write_control(unit, parm->mem, parm->copyno, 1604 mw->orig_enable, &mw->orig_enable) < 0) { 1605 test_error(unit, "Could not disable exclusive cpu write on memory " 1606 "%s\n", 1607 SOC_MEM_UFNAME(unit, parm->mem)); 1608 return -1; 1609 } 1610 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DFE_SUPPORT */ 1611 1612 #ifdef BCM_DFE_SUPPORT 1613 if(SOC_IS_DFE(unit)) { 1614 SOC_MEM_TEST_SKIP_CACHE_SET(unit, 0); 1615 if (soc_mem_parity_restore(unit, parm->mem, parm->copyno) < 0) { 1616 test_error(unit, "Could not enable parity warnings on memory %s\n", 1617 SOC_MEM_UFNAME(unit, parm->mem)); 1618 return -1; 1619 } 1620 } else 1621 #endif /* BCM_DFE_SUPPORT */ 1622 { 1623 #if defined(BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) 1624 if (mem_test_common_restore(unit, parm->mem, parm->copyno)) { 1625 return -1; 1626 } 1627 #endif /* BCM_ESW_SUPPORT || BCM_PETRA_SUPPORT || BCM_DNX_SUPPORT */ 1628 } 1629 1630 #ifdef BCM_SHADOW_SUPPORT 1631 if (SOC_IS_SHADOW(unit) && (parm->mem == EGR_PERQ_XMT_COUNTERSm)) { 1632 rv = soc_reg_field32_modify(unit, EGR_EDB_HW_CONTROLr, REG_PORT_ANY, 1633 XGS_COUNTER_COMPAT_MODEf, 0); 1634 if (rv != SOC_E_NONE) { 1635 return -1; 1636 } 1637 } 1638 if (SOC_IS_SHADOW(unit)) { 1639 uint32 rval; 1640 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 1641 soc_reg_field_set(unit, MISCCONFIGr, &rval, 1642 METERING_CLK_ENf, 1); 1643 soc_reg_field_set(unit, MISCCONFIGr, &rval, 1644 REFRESH_ENf, 1); 1645 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 1646 } 1647 1648 if (SOC_IS_SHADOW(unit) && SOC_BLOCK_IS_CMP(unit, 1649 SOC_MEM_BLOCK_MIN(unit, parm->mem), SOC_BLK_MS_ISEC)) { 1650 rv = soc_reg_field32_modify(unit, ISEC_MASTER_CTRLr, 1, 1651 XGS_COUNTER_COMPAT_MODEf, 0); 1652 if (rv != SOC_E_NONE) { 1653 return -1; 1654 } 1655 rv = soc_reg_field32_modify(unit, ISEC_MASTER_CTRLr, 5, 1656 XGS_COUNTER_COMPAT_MODEf, 0); 1657 if (rv != SOC_E_NONE) { 1658 return -1; 1659 } 1660 } 1661 if (SOC_IS_SHADOW(unit) && SOC_BLOCK_IS_CMP(unit, 1662 SOC_MEM_BLOCK_MIN(unit, parm->mem), SOC_BLK_MS_ESEC)) { 1663 rv = soc_reg_field32_modify(unit, ESEC_MASTER_CTRLr, 1, 1664 XGS_COUNTER_COMPAT_MODEf, 0); 1665 if (rv != SOC_E_NONE) { 1666 return -1; 1667 } 1668 rv = soc_reg_field32_modify(unit, ESEC_MASTER_CTRLr, 5, 1669 XGS_COUNTER_COMPAT_MODEf, 0); 1670 if (rv != SOC_E_NONE) { 1671 return -1; 1672 } 1673 } 1674 #endif 1675 1676 } 1677 return 0; 1678 } 1679 1680 #if (defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) || defined (BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT)) 1681 /* 1682 * Memories read/write test (tr 6) 1683 */ 1684 #ifdef BCM_SAND_SUPPORT 1685 int 1686 memories_rw_test(int unit, args_t *a, void *pa) 1687 { 1688 int rv = 0; 1689 1690 COMPILER_REFERENCE(pa); 1691 1692 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Memories read test\n"))); 1693 1694 /* 1695 * If try_reg returns -1, there was a register access failure rather 1696 * than a bit error. 1697 * 1698 * If try_reg returns 0, then rd.error is -1 if there was a bit 1699 * error. 1700 */ 1701 /* soc_memories_bcm88650_a0 */ 1702 #ifdef BCM_PETRA_SUPPORT 1703 if (SOC_IS_ARAD(unit)) 1704 { 1705 bcm_common_linkscan_enable_set(unit,0); 1706 soc_counter_stop(unit); 1707 if (SOC_IS_ARADPLUS_AND_BELOW(unit)){ 1708 if((rv = bcm_dpp_counter_bg_enable_set(unit, FALSE)) < 0) 1709 { 1710 LOG_WARN(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "WARNING: Unable to deactivate counter bg thread, unit %d \n"), unit)); 1711 } 1712 } 1713 1714 #if defined(BCM_JERICHO_SUPPORT) 1715 if(!SAL_BOOT_PLISIM && SOC_IS_JERICHO_PLUS_ONLY(unit)) { 1716 jer_mgmt_pvt_monitor_correction_disable(unit); 1717 } 1718 #endif 1719 1720 if ((rv = soc_dpp_device_reset(unit, SOC_DPP_RESET_MODE_REG_ACCESS, SOC_DPP_RESET_ACTION_INOUT_RESET)) < 0) { 1721 LOG_ERROR(BSL_LS_APPL_COMMON, (BSL_META_U(unit, "ERROR: Unable to access regs, unit %d \n"), unit)); 1722 test_error(unit, "Register read/write test failed\n"); 1723 return rv; 1724 } 1725 1726 rv = enable_dynamic_memories_access(unit); 1727 if(SOC_FAILURE(rv)){ 1728 return rv; 1729 } 1730 } 1731 1732 #endif 1733 #if defined (BCM_DFE_SUPPORT) || defined(BCM_DNXF_SUPPORT) 1734 if (SOC_IS_DFE(unit) || SOC_IS_DNXF(unit)) 1735 { 1736 rv = do_mem_test(unit,a); 1737 } 1738 else 1739 #endif 1740 { 1741 rv = do_dump_memories(unit, a); 1742 } 1743 1744 if (rv < 0) { 1745 test_error(unit, "Memory Read test failed (TR 6)\n"); 1746 } else { 1747 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Memories read test finished successfully\n"))); 1748 } 1749 1750 return rv; 1751 } 1752 #endif /* (defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) */ 1753 1754 STATIC int 1755 enable_dynamic_memories_access_cb(int unit, soc_regaddrinfo_t *ainfo, void *data) 1756 { 1757 uint32 value = *(uint32 *)data; 1758 soc_block_types_t blocks = SOC_REG_INFO(unit, ainfo->reg).block; 1759 soc_block_type_t block = SOC_REG_FIRST_BLK_TYPE(blocks); 1760 int blk,inst=0; 1761 1762 SOC_INIT_FUNC_DEFS; 1763 if ( SOC_IS_JERICHO(unit) ) { 1764 switch (block) { 1765 case SOC_BLK_BRDC_FMAC : 1766 case SOC_BLK_DRCA : 1767 case SOC_BLK_DRCB : 1768 case SOC_BLK_DRCBROADCAST : 1769 case SOC_BLK_DRCC : 1770 case SOC_BLK_DRCD : 1771 case SOC_BLK_DRCE : 1772 case SOC_BLK_DRCF : 1773 case SOC_BLK_DRCG : 1774 case SOC_BLK_DRCH : 1775 case SOC_BLK_FDR : 1776 case SOC_BLK_FMAC : 1777 case SOC_BLK_NBIH : 1778 case SOC_BLK_NBIL : 1779 SOC_EXIT; /* the enable dynamic registers of this blocks is not accessable*/ 1780 default: 1781 break; 1782 } 1783 } 1784 1785 if (!SOC_REG_IS_VALID(unit,ainfo->reg) || 1786 !SOC_REG_FIELD_VALID(unit,ainfo->reg,ENABLE_DYNAMIC_MEMORY_ACCESSf)) { 1787 SOC_EXIT; 1788 } 1789 SOC_BLOCK_ITER(unit, blk, SOC_REG_FIRST_BLK_TYPE(SOC_REG_INFO(unit, ainfo->reg).block)) { 1790 _SOC_IF_ERR_EXIT(soc_reg_field32_modify(unit, ainfo->reg, inst,ENABLE_DYNAMIC_MEMORY_ACCESSf, value)); 1791 inst++; 1792 } 1793 1794 1795 exit: 1796 if (_rv!= SOC_E_NONE) { 1797 cli_out("Skip enable %s\n",SOC_REG_NAME(unit,ainfo->reg)); 1798 _rv=SOC_E_NONE; 1799 1800 } 1801 SOC_FUNC_RETURN; 1802 1803 } 1804 1805 1806 /* 1807 * Enables dynamic memory access 1808 */ 1809 soc_error_t 1810 enable_dynamic_memories_access(int unit) 1811 { 1812 uint32 write_val = 1; 1813 uint64 write_val64; 1814 soc_reg_above_64_val_t write_val_above64; 1815 1816 SOC_INIT_FUNC_DEFS; 1817 1818 if (SOC_IS_DFE(unit)) { 1819 SOC_EXIT; 1820 } 1821 1822 _SOC_IF_ERR_EXIT(soc_reg_iterate(unit, enable_dynamic_memories_access_cb, &write_val)) ; 1823 1824 1825 if ( SOC_IS_JERICHO(unit) ) { 1826 1827 _SOC_IF_ERR_EXIT(soc_reg32_set(unit, EGQ_EGRESS_SHAPER_ENABLE_SETTINGSr, REG_PORT_ANY, 0, 0)); 1828 1829 _SOC_IF_ERR_EXIT(soc_reg_field32_modify(unit, SCH_CIR_SHAPERS_CONFIGURATIONr, REG_PORT_ANY, 1830 CIR_SHAPERS_CAL_ACCESS_PERIODf, 0x0)); 1831 _SOC_IF_ERR_EXIT(soc_reg_field32_modify(unit, SCH_CIR_SHAPERS_CONFIGURATION_1r, REG_PORT_ANY, 1832 CIR_SHAPERS_CAL_ACCESS_PERIOD_1f, 0x0)); 1833 _SOC_IF_ERR_EXIT(soc_reg_field32_modify(unit, SCH_PIR_SHAPERS_CONFIGURATIONr, REG_PORT_ANY, 1834 PIR_SHAPERS_CAL_ACCESS_PERIODf, 0x0)); 1835 _SOC_IF_ERR_EXIT(soc_reg_field32_modify(unit, SCH_PIR_SHAPERS_CONFIGURATION_1r, REG_PORT_ANY, 1836 PIR_SHAPERS_CAL_ACCESS_PERIOD_1f, 0x0)); 1837 COMPILER_64_SET(write_val64, 0x0, 0x0); 1838 _SOC_IF_ERR_EXIT(WRITE_IPS_CREDIT_WATCHDOG_CONFIGURATIONr(unit, REG_PORT_ANY, write_val64)); 1839 } 1840 1841 1842 if (SOC_IS_ARADPLUS_AND_BELOW(unit)) { 1843 1844 COMPILER_64_SET(write_val64, 0xffffffff, 0xffffffff); 1845 if (!SOC_IS_ARDON(unit)) { 1846 _SOC_IF_ERR_EXIT(WRITE_NBI_INDIRECT_WR_MASKr(unit,write_val64));/* 64 */ 1847 1848 _SOC_IF_ERR_EXIT(READ_IDR_GLBL_CFGr(unit, &write_val)); 1849 soc_reg_field_set(unit, IDR_GLBL_CFGr, &write_val, MCDB_INITf, 0); 1850 soc_reg_field_set(unit, IDR_GLBL_CFGr, &write_val, MCDA_INITf, 0); 1851 _SOC_IF_ERR_EXIT(WRITE_IDR_GLBL_CFGr(unit, write_val)); 1852 } 1853 1854 SOC_REG_ABOVE_64_ALLONES(write_val_above64); 1855 _SOC_IF_ERR_EXIT(WRITE_IDR_INDIRECT_WR_MASKr(unit,write_val_above64)); /* 640 */ 1856 1857 _SOC_IF_ERR_EXIT(WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x10000)); 1858 } 1859 1860 exit: 1861 SOC_FUNC_RETURN; 1862 } 1863 1864 1865 1866 /* following macros used to replace usage of wrong macros in disable_ecc_disable_dynamic_mechanism() */ 1867 #define DISABLE_ECC_CHECK_FUNC_RESULT(res, err_num,op, err_val) \ 1868 res = op; \ 1869 if (res != SOC_E_NONE) { \ 1870 res = err_val; \ 1871 exit_place = err_num; \ 1872 soc_sand_set_error_code_into_error_word(res, &rv); \ 1873 LOG_ERROR(BSL_LS_APPL_COMMON, \ 1874 (BSL_META("error in function disable_ecc_dynamic_mechanism()\n"))); \ 1875 goto exit; \ 1876 } 1877 1878 1879 #define DISABLE_ECC_SOC_SAND_IF_ERROR_RETURN(res, err_num,op) \ 1880 DISABLE_ECC_CHECK_FUNC_RESULT(res,err_num,op,SOC_SAND_SOC_ERR) 1881 1882 1883 1884 #define DISABLE_ECC_ARAD_FIELD_SET(reg_desc, fld_desc, fld_value, err_num) \ 1885 DISABLE_ECC_CHECK_FUNC_RESULT(res,err_num,soc_reg_above_64_field32_modify(unit,reg_desc,REG_PORT_ANY,0,fld_desc,fld_value) ,ARAD_REG_ACCESS_ERR); 1886 1887 1888 1889 1890 /* set a field of a register array element */ 1891 #define DISABLE_ECC_ARAD_FIELD_ASET(reg_desc, index,fld_desc, fld_value, err_num) \ 1892 DISABLE_ECC_CHECK_FUNC_RESULT(res,err_num,soc_reg_above_64_field32_modify(unit,reg_desc,REG_PORT_ANY,index,fld_desc,fld_value) ,ARAD_REG_ACCESS_ERR); 1893 1894 /* 1895 #define WRITE_BIT_DISABLE_DYNAMIC(unit,reg,field) \ 1896 { \ 1897 write_val = 0; \ 1898 READ_##reg (unit,&write_val); \ 1899 soc_reg_field_set(unit, reg , &write_val, (field),1); \ 1900 WRITE_##reg (unit,write_val); \ 1901 } 1902 */ 1903 /* 1904 * Enables dynamic memory access 1905 */ 1906 int 1907 disable_ecc_disable_dynamic_mechanism(int unit) 1908 { 1909 #ifdef BCM_PETRA_SUPPORT 1910 uint32 res; 1911 uint32 write_val = 1, rv =0, exit_place =0; 1912 1913 soc_sand_initialize_error_word(0,0,&rv); 1914 1915 DISABLE_ECC_SOC_SAND_IF_ERROR_RETURN(res, 10,soc_reg_iterate(unit, enable_dynamic_memories_access_cb, &write_val)) ; 1916 1917 if (!SOC_IS_ARDON(unit)) { 1918 DISABLE_ECC_ARAD_FIELD_SET(SCH_SCHEDULER_CONFIGURATION_REGISTERr, DISABLE_FABRIC_MSGSf, 1 ,580); 1919 } 1920 1921 if (SOC_IS_ARADPLUS_AND_BELOW(unit)) { 1922 if (!SOC_IS_ARDON(unit)) { 1923 DISABLE_ECC_ARAD_FIELD_SET(NBI_STATISTICSr, STAT_USE_GLOBAL_INDIRECTf, 1, 110); 1924 1925 DISABLE_ECC_ARAD_FIELD_SET(IDR_GLBL_CFGr, MCDA_INITf, 1 ,540); 1926 DISABLE_ECC_ARAD_FIELD_SET(IDR_GLBL_CFGr, MCDB_INITf, 1 ,550); 1927 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_0102r, FIELD_6_6f, 1 ,600); 1928 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_0102r, FIELD_5_5f, 1 ,610); 1929 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_0102r, FIELD_4_4f, 1 ,620); 1930 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_0102r, FIELD_3_3f, 1 ,630); 1931 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_0102r, FIELD_2_2f, 1 ,640); 1932 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_0102r, FIELD_1_1f, 1 ,650); 1933 DISABLE_ECC_ARAD_FIELD_SET(SCH_SYSTEM_RED_CONFIGURATIONr, AGING_TIMER_CFGf, 0 ,560); 1934 DISABLE_ECC_ARAD_FIELD_SET(SCH_DVS_CONFIG_0r, NIF_FORCE_PAUSEf, 0xffffffff ,570); 1935 } 1936 DISABLE_ECC_ARAD_FIELD_SET(CFC_REG_00CFr,FIELD_16_16f, 1 ,120); 1937 DISABLE_ECC_ARAD_FIELD_SET(CRPS_REG_00CEr,FIELD_16_16f, 1 ,130); 1938 DISABLE_ECC_ARAD_FIELD_SET(ECI_GLOBALFr,CPU_BYPASS_ECC_PARf, 1 ,140); 1939 DISABLE_ECC_ARAD_FIELD_SET(EGQ_REG_00CFr,FIELD_16_16f, 1 ,150); 1940 DISABLE_ECC_ARAD_FIELD_SET(EPNI_REG_00CFr,FIELD_16_16f, 1 ,160); 1941 DISABLE_ECC_ARAD_FIELD_SET(FCR_REG_00CFr,FIELD_16_16f, 1 ,170); 1942 DISABLE_ECC_ARAD_FIELD_SET(FDT_REG_00CFr,FIELD_16_16f, 1 ,180); 1943 DISABLE_ECC_ARAD_FIELD_SET(IDR_REG_00CFr,FIELD_16_16f, 1 ,190); 1944 /* WRITE_BIT_DISABLE_DYNAMIC(unit , IDR_REG_00CFr , FIELD_16_16f);*/ 1945 DISABLE_ECC_ARAD_FIELD_SET(IHB_REG_008Ar,FIELD_16_16f, 1 ,200); 1946 DISABLE_ECC_ARAD_FIELD_SET(IHP_REG_00CFr,FIELD_16_16f, 1 ,210); 1947 DISABLE_ECC_ARAD_FIELD_SET(IPS_REG_00C6r,FIELD_16_16f, 1 ,220); 1948 DISABLE_ECC_ARAD_FIELD_SET(IPT_REG_00CFr,FIELD_16_16f, 1 ,230); 1949 DISABLE_ECC_ARAD_FIELD_SET(IQM_REG_00CDr,FIELD_16_16f, 1 ,240); 1950 DISABLE_ECC_ARAD_FIELD_SET(IRE_REG_00CFr,FIELD_16_16f, 1 ,250); 1951 DISABLE_ECC_ARAD_FIELD_SET(IRR_REG_00CFr,FIELD_16_16f, 1 ,260); 1952 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_00CFr,FIELD_16_16f, 1 ,270); 1953 DISABLE_ECC_ARAD_FIELD_SET(NBI_REG_00CFr,FIELD_16_16f, 1 ,280); 1954 if(SOC_IS_ARAD_B0_AND_ABOVE(unit)) { 1955 if (!SOC_IS_ARDON(unit)) { 1956 DISABLE_ECC_ARAD_FIELD_SET(OAMP_GLOBAL_Fr, CPU_BYPASS_ECC_PARf, 1 ,290); 1957 DISABLE_ECC_ARAD_FIELD_SET(OLP_OLP_GLOBAL_REGISTERS_0r, FIELD_16_16f, 1 ,300); 1958 } 1959 } else { 1960 DISABLE_ECC_ARAD_FIELD_SET(OAMP_REG_00CFr,FIELD_16_16f, 1 ,290); 1961 DISABLE_ECC_ARAD_FIELD_SET(OLP_REG_00F0r,FIELD_16_16f, 1 ,300); 1962 } 1963 DISABLE_ECC_ARAD_FIELD_SET(CFC_REG_00CFr,FIELD_15_15f, 1 ,310); 1964 DISABLE_ECC_ARAD_FIELD_SET(CRPS_REG_00CEr,FIELD_15_15f, 1 ,320); 1965 DISABLE_ECC_ARAD_FIELD_SET(ECI_GLOBALFr, DIS_ECCf, 1 ,330); 1966 DISABLE_ECC_ARAD_FIELD_SET(EGQ_REG_00CFr, FIELD_15_15f, 1 ,340); 1967 DISABLE_ECC_ARAD_FIELD_SET(EPNI_REG_00CFr, FIELD_15_15f, 1 ,350); 1968 DISABLE_ECC_ARAD_FIELD_SET(FCR_REG_00CFr, FIELD_15_15f, 1 ,360); 1969 DISABLE_ECC_ARAD_FIELD_SET(FDT_REG_00CFr, FIELD_15_15f, 1 ,370); 1970 DISABLE_ECC_ARAD_FIELD_SET(IDR_REG_00CFr, FIELD_15_15f, 1 ,380); 1971 DISABLE_ECC_ARAD_FIELD_SET(IHB_REG_008Ar, FIELD_15_15f, 1 ,390); 1972 DISABLE_ECC_ARAD_FIELD_SET(IHP_REG_00CFr, FIELD_15_15f, 1 ,400); 1973 DISABLE_ECC_ARAD_FIELD_SET(IPS_REG_00C6r, FIELD_15_15f, 1 ,410); 1974 DISABLE_ECC_ARAD_FIELD_SET(IPT_REG_00CFr, FIELD_15_15f, 1 ,420); 1975 DISABLE_ECC_ARAD_FIELD_SET(IQM_REG_00CDr, FIELD_15_15f, 1 ,430); 1976 DISABLE_ECC_ARAD_FIELD_SET(IRE_REG_00CFr, FIELD_15_15f, 1 ,440); 1977 DISABLE_ECC_ARAD_FIELD_SET(IRR_REG_00CFr, FIELD_15_15f, 1 ,450); 1978 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_00CFr, FIELD_15_15f, 1 ,460); 1979 DISABLE_ECC_ARAD_FIELD_SET(NBI_REG_00CFr, FIELD_15_15f, 1 ,470); 1980 if(SOC_IS_ARAD_B0_AND_ABOVE(unit)) { 1981 if (!SOC_IS_ARDON(unit)) { 1982 DISABLE_ECC_ARAD_FIELD_SET(OAMP_GLOBAL_Fr, DIS_ECCf, 1, 290); 1983 DISABLE_ECC_ARAD_FIELD_SET(OLP_OLP_GLOBAL_REGISTERS_0r, FIELD_15_15f, 1 ,300); 1984 } 1985 } else { 1986 DISABLE_ECC_ARAD_FIELD_SET(OAMP_REG_00CFr, FIELD_15_15f, 1 ,480); 1987 DISABLE_ECC_ARAD_FIELD_SET(OLP_REG_00F0r, FIELD_15_15f, 1 ,490); 1988 } 1989 DISABLE_ECC_ARAD_FIELD_SET(IPS_IPS_GENERAL_CONFIGURATIONSr, DISCARD_ALL_IQM_MSGf, 1 ,500); 1990 DISABLE_ECC_ARAD_FIELD_SET(IPS_IPS_GENERAL_CONFIGURATIONSr, DISCARD_ALL_CRDTf, 1 ,510); 1991 DISABLE_ECC_ARAD_FIELD_SET(IPS_IPS_GENERAL_CONFIGURATIONSr, DISABLE_STATUS_MSG_GENf, 1 ,520); 1992 DISABLE_ECC_ARAD_FIELD_SET(IPS_CREDIT_WATCHDOG_CONFIGURATIONr, CR_WD_MIN_SCAN_CYCLE_PERIODf, 0 ,530); 1993 DISABLE_ECC_ARAD_FIELD_SET(MMU_REG_00C1r, FIELD_2_2f, 0 ,590); 1994 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_CNT_SRC_CFGr, 0, CRPS_N_CNT_SRCf, 0x12, 660 ); 1995 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_CNT_SRC_CFGr, 1, CRPS_N_CNT_SRCf, 0x12, 670 ); 1996 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_CNT_SRC_CFGr, 2, CRPS_N_CNT_SRCf, 0x12, 680 ); 1997 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_CNT_SRC_CFGr, 3, CRPS_N_CNT_SRCf, 0x12, 690 ); 1998 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 0, CRPS_N_CPU_CLEAR_READ_ENf, 0, 700 ); 1999 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 0, CRPS_N_BUBBLE_ENf, 0, 710 ); 2000 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 1, CRPS_N_CPU_CLEAR_READ_ENf, 0, 720 ); 2001 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 1, CRPS_N_BUBBLE_ENf, 0, 730 ); 2002 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 2, CRPS_N_CPU_CLEAR_READ_ENf, 0, 740 ); 2003 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 2, CRPS_N_BUBBLE_ENf, 0, 750 ); 2004 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 3, CRPS_N_CPU_CLEAR_READ_ENf, 0, 760 ); 2005 DISABLE_ECC_ARAD_FIELD_ASET(CRPS_CRPS_GENERAL_CFGr, 3, CRPS_N_BUBBLE_ENf, 0, 770 ); 2006 2007 DISABLE_ECC_SOC_SAND_IF_ERROR_RETURN(res, 780, WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x30000)); 2008 } else { 2009 DISABLE_ECC_ARAD_FIELD_SET(SCH_DVS_CONFIGr, FORCE_PAUSEf, 1 ,570); 2010 } 2011 exit: 2012 if (rv !=0) { 2013 soc_sand_error_handler(res, "error in disable_ecc_disable_dynamic_mechanism()", exit_place,0,0,0,0,0 ); 2014 } 2015 return rv; 2016 #else 2017 return 0; 2018 #endif 2019 } 2020 2021 2022 /* 2023 * Memories read/write for first and last memory index test (tr 7) 2024 */ 2025 char tr7_test_usage[] = 2026 "TR7 memory write & read (first & last) usage:\n" 2027 " \n" 2028 #ifdef COMPILER_STRING_CONST_LIMIT 2029 "\nFull documentation cannot be displayed with -pedantic compiler\n"; 2030 #else 2031 2032 "EnableReset=<1/0> - Specifies if proceed reset (1, default) or not\n" 2033 "EnableSkip=<1/0> - Specifies if to skip registers cannot be compared (1, default) or do not skip(0)\n" 2034 "IncPm=<1/0> - Specifies if to include port macro blocks in tr (1-include 0-exclude(default))\n" 2035 "StartFrom=<integer> - Specifies from what mem id to start the tr(default 0)\n" 2036 "Help=<1/0> - Specifies if tr 7 help is on and exit or off (off by default)\n" 2037 "To enable printing values (write/read) of each memory proceed: debug +test +verb\n" 2038 "\n"; 2039 #endif 2040 2041 2042 int 2043 memories_rw_first_last_test(int unit, args_t *a, void *pa) 2044 { 2045 2046 int rv = 0; 2047 int num_soc_mem = NUM_SOC_MEM; 2048 2049 2050 2051 2052 2053 #if defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) || defined(BCM_DNXF_SUPPORT) || defined(BCM_DNX_SUPPORT) 2054 parse_table_t pt; 2055 uint32 help_status = 0; 2056 uint32 help_status_default = 0; 2057 uint32 enablereset = 1; 2058 uint32 default_enablereset = 1; 2059 tr7_dbase_t tr7_data; 2060 2061 tr7_data.enable_skip = 1; 2062 tr7_data.show_compare = 0; 2063 tr7_data.include_port_macros = 0; 2064 tr7_data.start_from = 0; 2065 tr7_data.count = NUM_SOC_MEM; 2066 #endif 2067 COMPILER_REFERENCE(pa); 2068 #if defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) || defined(BCM_DNXF_SUPPORT) || defined(BCM_DNX_SUPPORT) 2069 parse_table_init(unit, &pt); 2070 parse_table_add(&pt, "EnableReset", PQ_DFL|PQ_INT, &default_enablereset, &enablereset, NULL); 2071 parse_table_add(&pt, "EnableSkip", PQ_DFL|PQ_INT, 0, &tr7_data.enable_skip, NULL); 2072 parse_table_add(&pt, "IncPm", PQ_DFL|PQ_INT, 0, &tr7_data.include_port_macros, NULL); 2073 parse_table_add(&pt, "StartFrom", PQ_DFL|PQ_INT, 0, &tr7_data.start_from, NULL); 2074 parse_table_add(&pt, "MemCount", PQ_DFL|PQ_INT, &num_soc_mem, &tr7_data.count, NULL); 2075 parse_table_add(&pt, "Help", PQ_DFL|PQ_INT, &help_status_default, &help_status, NULL); 2076 2077 if (parse_arg_eq(a, &pt) < 0) { 2078 cli_out("%s: Invalid option: %s\n", ARG_CMD(a), ARG_CUR(a)); 2079 parse_arg_eq_done(&pt); 2080 goto done; 2081 } 2082 parse_arg_eq_done(&pt); 2083 2084 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Memories read/write first and last test\n"))); 2085 2086 if (help_status == 1) { 2087 cli_out("%s\n",tr7_test_usage); 2088 goto done; 2089 } 2090 #endif 2091 2092 COMPILER_REFERENCE(pa); 2093 2094 /* 2095 * If try_reg returns -1, there was a register access failure rather 2096 * than a bit error. 2097 * 2098 * If try_reg returns 0, then rd.error is -1 if there was a bit 2099 * error. 2100 */ 2101 #if defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) || defined(BCM_SAND_SUPPORT) 2102 #if defined(BCM_PETRA_SUPPORT) 2103 if (SOC_IS_ARAD(unit)) { 2104 bcm_common_linkscan_enable_set(unit,0); 2105 soc_counter_stop(unit); 2106 2107 #if defined(BCM_JERICHO_SUPPORT) 2108 if(!SAL_BOOT_PLISIM && SOC_IS_JERICHO_PLUS_ONLY(unit)) { 2109 jer_mgmt_pvt_monitor_correction_disable(unit); 2110 } 2111 #endif 2112 2113 if ((enablereset == 1) && !SOC_IS_JERICHO(unit)) { 2114 if ((rv = soc_dpp_device_reset(unit, SOC_DPP_RESET_MODE_REG_ACCESS,SOC_DPP_RESET_ACTION_INOUT_RESET)) < 0) { 2115 LOG_ERROR(BSL_LS_APPL_COMMON, (BSL_META_U(unit, "ERROR: Unable to reinit unit %d \n"), unit)); 2116 goto done; 2117 } 2118 } else { 2119 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Skip device reset\n"))); 2120 } 2121 2122 rv = enable_dynamic_memories_access(unit); 2123 if(SOC_FAILURE(rv)) { 2124 goto done; 2125 } 2126 } 2127 2128 #endif 2129 rv = do_mem_test_rw(unit, tr7_data, a); 2130 2131 done: 2132 #endif 2133 if (rv < 0) { 2134 test_error(unit, "Register read/write test failed\n"); 2135 } 2136 2137 return rv; 2138 } 2139 2140 2141 2142 #if defined(BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) || defined (BCM_DNXF_SUPPORT) 2143 char tr8_test_usage[] = 2144 "TR8 memory write & periodic read usage:\n" 2145 " \n" 2146 "RunCount=<value> - Specifies number of read all memory cycles after one write (0xffffffff is like while(1)), 0xffffffff by default\n" 2147 "Value=<value> - Specifies write values (32 bits), 0 by default\n" 2148 "Period=<value> - Specifies period of read cycle in seconds, 5 by default\n" 2149 #ifdef COMPILER_STRING_CONST_LIMIT 2150 "\nFull documentation cannot be displayed with -pedantic compiler\n"; 2151 #else 2152 "Help=<1/0> - Specifies if tr 8 help is on and exit or off (off by default)\n" 2153 "File=<file name> - Specifies file name for dump (relevant when UseFile=1)\n" 2154 "UseFile=<1/0> - Specifies if to use file for dump (1- use, 0 - do not use), 0 by default\n" 2155 "faultInject=<1/0> - Specifies if to activate fault inject(non correct write, test should show compare errors(1-enabled, 0-disabled), 0 by default\n" 2156 "SkipResetAndWrite=<1/0> - Specifies if to skip chip reset and memories write(1-skip, 0-do not skip), 0 by default\n" 2157 "IncPm=<1/0> - Specifies if to include port macro blocks in tr (1-include 0-exclude(default))\n" 2158 "StartFrom=<integer> - Specifies from what mem id to start the tr(default 0)\n" 2159 "MemCount=<integer> - Specifies how many memories to test)\n" 2160 "MaxSize=<integer|-1> - table with size in bytes above MaxSize will excluded from the test(default -1 all tables included)\n" 2161 "\n" 2162 ; 2163 #endif 2164 2165 /* 2166 * Memories flip flop test tr 8 2167 */ 2168 int 2169 mem_flipflop_test(int unit, args_t *a, void *pa) 2170 { 2171 2172 int rv = 0; 2173 parse_table_t pt; 2174 tr8_dbase_t tr8_data; 2175 uint32 default_val = 5; 2176 uint32 default_run_count = 0x1; 2177 uint32 help_status; 2178 uint32 help_status_default = 0; 2179 int xd_usefile = 0; 2180 char *file_name=NULL; 2181 int default_include_port_macros = 0; 2182 int default_max_size=-1; 2183 char print_str[250]; 2184 #if defined(BCM_PETRA_SUPPORT) 2185 bcm_switch_event_control_t bcm_switch_event_control; 2186 #endif 2187 #ifndef __KERNEL__ 2188 time_t current_time; 2189 #endif 2190 int default_skip_reset_write = 0; 2191 tr8_data.write_value = 0; 2192 tr8_data.period = 5; 2193 tr8_data.run_count = 0x1; 2194 tr8_data.skip_reset_and_write = 0; 2195 tr8_data.include_port_macros = 0; 2196 tr8_data.start_from = 0; 2197 tr8_data.max_size = -1; 2198 tr8_data.total_count=0; 2199 tr8_data.error_count=0; 2200 tr8_data.unclear_skipped_count=0; 2201 tr8_data.count=NUM_SOC_MEM; 2202 tr8_data.fault_inject = 0; 2203 help_status = 0; 2204 2205 parse_table_init(unit, &pt); 2206 parse_table_add(&pt, "RunCount", PQ_DFL|PQ_INT, &default_run_count, &tr8_data.run_count, NULL); 2207 parse_table_add(&pt, "Value", PQ_DFL|PQ_INT, 0, &tr8_data.write_value, NULL); 2208 parse_table_add(&pt, "Period", PQ_DFL|PQ_INT, &default_val, &tr8_data.period, NULL); 2209 parse_table_add(&pt, "Help", PQ_DFL|PQ_INT, &help_status_default, &help_status, NULL); 2210 parse_table_add(&pt, "UseFile", PQ_DFL|PQ_BOOL , 0, &xd_usefile, NULL); 2211 parse_table_add(&pt, "File", PQ_STRING, 0, &file_name, NULL); 2212 parse_table_add(&pt, "faultInject", PQ_DFL|PQ_INT, 0, &tr8_data.fault_inject, NULL); 2213 parse_table_add(&pt, "SkipResetAndWrite",PQ_DFL|PQ_INT, &default_skip_reset_write, &tr8_data.skip_reset_and_write, NULL); 2214 parse_table_add(&pt, "IncPm", PQ_DFL|PQ_INT, &default_include_port_macros, &tr8_data.include_port_macros, NULL); 2215 parse_table_add(&pt, "StartFrom", PQ_DFL|PQ_INT, 0, &tr8_data.start_from, NULL); 2216 parse_table_add(&pt, "MemsCount", PQ_DFL|PQ_INT, 0, &tr8_data.count, NULL); 2217 parse_table_add(&pt, "MaxSize", PQ_DFL|PQ_INT, &default_max_size, &tr8_data.max_size, NULL); 2218 2219 if (parse_arg_eq(a, &pt) < 0) { 2220 cli_out("%s: Invalid option: %s\n", 2221 ARG_CMD(a), ARG_CUR(a)); 2222 parse_arg_eq_done(&pt); 2223 goto done; 2224 } 2225 if (xd_usefile > 0) { 2226 /* = sal_strdup(xd_file); */ 2227 if (tr8_open_dump_file(unit,file_name ) == -1) { 2228 cli_out("Error open dump file %s, dump file disabled\n", file_name); 2229 } 2230 } 2231 2232 parse_arg_eq_done(&pt); 2233 #ifndef __KERNEL__ 2234 time(¤t_time); 2235 2236 /* COMPILER_REFERENCE(pa); */ 2237 LOG_INFO(BSL_LS_APPL_TESTS, 2238 (BSL_META_U(unit, 2239 "Memories read/write first and last test, %s\n"),ctime((const time_t *)¤t_time))); 2240 2241 sal_sprintf(print_str,"Memories read/write first and last test, %s\n",ctime((const time_t *)¤t_time)); 2242 #endif 2243 tr8_write_dump(print_str); 2244 2245 2246 sal_sprintf(print_str,"write pattern =0x%x, period =%d, total iterations =%d, skip reset & write= %d\n", 2247 tr8_data.write_value, 2248 tr8_data.period, 2249 tr8_data.run_count, 2250 tr8_data.skip_reset_and_write); 2251 cli_out(print_str); 2252 tr8_write_dump(print_str); 2253 2254 if (help_status == 1) { 2255 cli_out("%s\n",tr8_test_usage); 2256 goto done; 2257 } 2258 2259 #if defined(BCM_PETRA_SUPPORT) 2260 /* 2261 * If try_reg returns -1, there was a register access failure rather 2262 * than a bit error. 2263 * 2264 * If try_reg returns 0, then rd.error is -1 if there was a bit 2265 * error. 2266 */ 2267 /* soc_memories_bcm88650_a0 */ 2268 if (SOC_IS_ARAD(unit)) 2269 { 2270 if (tr8_data.skip_reset_and_write != 1) { 2271 bcm_common_linkscan_enable_set(unit,0); 2272 soc_counter_stop(unit); 2273 2274 #if defined(BCM_JERICHO_SUPPORT) 2275 if(!SAL_BOOT_PLISIM && SOC_IS_JERICHO_PLUS_ONLY(unit)) { 2276 jer_mgmt_pvt_monitor_correction_disable(unit); 2277 } 2278 #endif 2279 2280 /* Disable all interrupts*/ 2281 bcm_switch_event_control.index = 0; 2282 bcm_switch_event_control.action = bcmSwitchEventMask; 2283 bcm_switch_event_control.event_id = BCM_SWITCH_EVENT_CONTROL_ALL; 2284 if ((rv = bcm_switch_event_control_set(unit, BCM_SWITCH_EVENT_DEVICE_INTERRUPT, bcm_switch_event_control, 0x1)) < 0) { 2285 LOG_ERROR(BSL_LS_APPL_COMMON, 2286 (BSL_META_U(unit, 2287 "ERROR: Unable to Disable interrupt on unit %d \n"), unit)); 2288 goto done; 2289 } 2290 /* if (BCM_E_NONE == bcm_dpp_counter_bg_enable_set(unit, FALSE)) { 2291 cli_out("unit %d counter processor background accesses suspended\n", unit); 2292 } else { 2293 cli_out("unit %d counter processor background access suspend failed: %d (%s)\n", 2294 unit, 2295 result, 2296 _SHR_ERRMSG(result)); 2297 } */ 2298 2299 if ((rv = soc_dpp_device_reset(unit, SOC_DPP_RESET_MODE_REG_ACCESS,SOC_DPP_RESET_ACTION_INOUT_RESET)) < 0) { 2300 LOG_ERROR(BSL_LS_APPL_COMMON, 2301 (BSL_META_U(unit, 2302 "ERROR: Unable to reinit unit %d \n"), unit)); 2303 goto done; 2304 } 2305 disable_ecc_disable_dynamic_mechanism(unit); 2306 2307 rv = enable_dynamic_memories_access(unit); 2308 if(SOC_FAILURE(rv)){ 2309 return rv; 2310 } 2311 } 2312 2313 rv = do_mem_test_flipflop(unit, tr8_data, a); 2314 tr8_close_dump_file(); 2315 } 2316 #endif 2317 2318 done: 2319 if (rv < 0) { 2320 test_error(unit, "Register read/write test failed\n"); 2321 } 2322 return rv; 2323 } 2324 2325 #ifndef __KERNEL__ 2326 static FILE * pFileTr8; 2327 #endif 2328 2329 int8 tr8_open_dump_file(int unit, char *fname) 2330 { 2331 2332 #ifndef __KERNEL__ 2333 pFileTr8 = sal_fopen(fname,"wt"); 2334 if (pFileTr8==NULL) { 2335 return -1; 2336 } 2337 #endif /* __KERNEL__ */ 2338 return 0; 2339 } 2340 2341 void tr8_close_dump_file(void) 2342 { 2343 #ifndef __KERNEL__ 2344 if (pFileTr8 != NULL) { 2345 fclose (pFileTr8); 2346 } 2347 #endif 2348 } 2349 2350 void tr8_write_dump(const char * _Format) 2351 { 2352 #ifndef __KERNEL__ 2353 if (pFileTr8 != NULL) { 2354 fprintf(pFileTr8,_Format); 2355 } 2356 #endif 2357 } 2358 2359 2360 static uint32 total_processed_bits; 2361 void tr8_reset_bits_counter(void) 2362 { 2363 total_processed_bits = 0; 2364 } 2365 2366 void tr8_increment_bits_counter(uint32 bits_num) 2367 { 2368 total_processed_bits += bits_num; 2369 } 2370 2371 uint32 tr8_bits_counter_get(void) 2372 { 2373 return total_processed_bits; 2374 } 2375 uint32 tr8_get_bits_num(uint32 number) 2376 { 2377 uint32 counter = 0; 2378 uint32 i; 2379 for (i=0;i<32;i++) { 2380 if ((number & (1<<i)) != 0) { 2381 counter++; 2382 } 2383 } 2384 return counter; 2385 } 2386 2387 #endif 2388 2389 #endif /* defined (BCM_PETRA_SUPPORT)|| defined (BCM_DFE_SUPPORT) */ 2390 2391 #if defined (SER_TR_TEST_SUPPORT) 2392 typedef struct ser_test_s { 2393 _soc_ser_test_t test_type; 2394 int verbose_prints; 2395 int error_prints; 2396 int cmd_print; 2397 int inject_only; 2398 soc_mem_t mem; 2399 } ser_test_param_t; 2400 2401 static ser_test_param_t *ser_test_parameters[SOC_MAX_NUM_DEVICES]; 2402 2403 int ser_test_init(int unit, args_t *arg, void **p) { 2404 ser_test_param_t *ser_params; 2405 parse_table_t pt; 2406 soc_block_t copyno; 2407 char *test_type_name; 2408 char *mem_name; 2409 if(ser_test_parameters[unit] == NULL) { 2410 ser_test_parameters[unit] = sal_alloc(sizeof(ser_test_param_t), "ser_test"); 2411 if (ser_test_parameters[unit] == NULL) { 2412 test_error(unit, "ERROR: cannot allocate memory\n"); 2413 return -1; 2414 } 2415 sal_memset(ser_test_parameters[unit],0,sizeof(ser_test_param_t)); 2416 } 2417 ser_params = ser_test_parameters[unit]; 2418 parse_table_init(unit, &pt); 2419 parse_table_add(&pt, "Memory", PQ_STRING, "all", 2420 &(mem_name), NULL); 2421 parse_table_add(&pt, "Cmd", PQ_BOOL, FALSE, 2422 &(ser_params->cmd_print), NULL); 2423 parse_table_add(&pt, "Error", PQ_BOOL, FALSE, 2424 &(ser_params->error_prints), NULL); 2425 parse_table_add(&pt, "Verbose", PQ_BOOL, FALSE, 2426 &(ser_params->verbose_prints), NULL); 2427 parse_table_add(&pt, "testType", PQ_STRING, "single", 2428 &(test_type_name), NULL); 2429 parse_table_add(&pt, "injectOnly", PQ_BOOL, FALSE, 2430 &(ser_params->inject_only),NULL); 2431 if (parse_arg_eq(arg, &pt) < 0) { 2432 cli_out("%s: Invalid option: %s\n", 2433 ARG_CMD(arg), ARG_CUR(arg)); 2434 parse_arg_eq_done(&pt); 2435 return -1; 2436 } 2437 2438 if (!sal_strcasecmp(test_type_name, "single")) { 2439 ser_params->test_type = SER_SINGLE_INDEX; 2440 } else if (!sal_strcasecmp(test_type_name, "spread")) { 2441 ser_params->test_type = SER_FIRST_MID_LAST_INDEX; 2442 } else if (!sal_strcasecmp(test_type_name, "all")) { 2443 ser_params->test_type = SER_ALL_INDEXES; 2444 } else if (!sal_strcasecmp(test_type_name, "1stHalf")) { 2445 ser_params->test_type = SER_FIRST_HALF_PIPES; 2446 } else if (!sal_strcasecmp(test_type_name, "2ndHalf")) { 2447 ser_params->test_type = SER_SECOND_HALF_PIPES; 2448 } else { 2449 cli_out("Invalid test type selected.\n"); 2450 parse_arg_eq_done(&pt); 2451 return -1; 2452 } 2453 2454 if (!sal_strcasecmp(mem_name, "all")) { 2455 ser_params->mem = INVALIDm; 2456 } else if (!(parse_memory_name(unit,&(ser_params->mem),mem_name,©no,0) >=0)) { 2457 cli_out("Invalid memory selected.\n"); 2458 parse_arg_eq_done(&pt); 2459 return -1; 2460 } 2461 *p = ser_params; 2462 parse_arg_eq_done(&pt); 2463 return 0; 2464 } 2465 2466 int ser_test_done(int unit, void *p) 2467 { 2468 return 0; 2469 } 2470 2471 /* 2472 * Function: 2473 * ser_test 2474 * Purpose: 2475 * Entry point and argument parser for SER TR tests. 2476 * Parameters: 2477 * unit - (IN) Device Number 2478 * arg - (IN) A set of passed arguments to this TR test 2479 * p - (IN) Unused. *Required for TR test format. 2480 */ 2481 int ser_test(int unit, args_t *arg, void *p) { 2482 ser_test_param_t *test_params = p; 2483 int rv = SOC_E_NONE; 2484 int force_read_through = SOC_MEM_FORCE_READ_THROUGH(unit); 2485 #ifdef INCLUDE_MEM_SCAN 2486 sal_usecs_t mem_scan_interval = 0; 2487 int mem_scan_rate = 0, mem_scan_running; 2488 #endif 2489 #ifdef BCM_SRAM_SCAN_SUPPORT 2490 sal_usecs_t sram_scan_interval = 0; 2491 int sram_scan_rate = 0, sram_scan_running; 2492 #endif 2493 2494 2495 2496 if (!force_read_through) { 2497 SOC_MEM_FORCE_READ_THROUGH_SET(unit, 1); 2498 } 2499 /*init soc*/ 2500 rv = soc_reset_init(unit); 2501 if (rv != SOC_E_NONE) { 2502 cli_out("Error during soc reset. Aborting.\n"); 2503 return rv; 2504 } 2505 /* Load Cancun files */ 2506 #if defined(CANCUN_SUPPORT) && !defined(NO_SAL_APPL) 2507 if (soc_feature(unit, soc_feature_cancun)) { 2508 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CMH); 2509 if (rv != SOC_E_NONE) { 2510 cli_out("Error during loading cmh. Aborting.\n"); 2511 return rv; 2512 } 2513 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CCH); 2514 if (rv != SOC_E_NONE) { 2515 cli_out("Error during loading cch. Aborting.\n"); 2516 return rv; 2517 } 2518 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CEH); 2519 if (rv != SOC_E_NONE) { 2520 cli_out("Error during loading ceh. Aborting.\n"); 2521 return rv; 2522 } 2523 } 2524 #endif 2525 2526 /*init misc*/ 2527 rv = soc_misc_init(unit); 2528 if (rv != SOC_E_NONE) { 2529 cli_out("Error during misc init. Aborting.\n"); 2530 return rv; 2531 } 2532 /* Load Cancun files */ 2533 #if defined(CANCUN_SUPPORT) && !defined(NO_SAL_APPL) 2534 if (soc_feature(unit, soc_feature_cancun)) { 2535 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CIH); 2536 if (rv != SOC_E_NONE) { 2537 cli_out("Error during loading cih. Aborting.\n"); 2538 return rv; 2539 } 2540 if (soc_feature(unit, soc_feature_flex_flow)) { 2541 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CFH); 2542 if (rv != SOC_E_NONE) { 2543 cli_out("Error during loading cfh. Aborting.\n"); 2544 return rv; 2545 } 2546 } 2547 } 2548 #endif 2549 2550 #if defined(BCM_SABER2_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 2551 if (SOC_IS_SABER2(unit) || SOC_IS_KATANA2(unit)) { 2552 /*init mmu */ 2553 rv = soc_mmu_init(unit); 2554 if (rv != SOC_E_NONE) { 2555 cli_out("Error during mmu init. Aborting.\n"); 2556 return rv; 2557 } 2558 } 2559 #endif 2560 2561 #ifdef INCLUDE_MEM_SCAN 2562 mem_scan_running = soc_mem_scan_running (unit, &mem_scan_rate, 2563 &mem_scan_interval); 2564 if( mem_scan_running > 0){ 2565 if( soc_mem_scan_stop(unit) ) { 2566 return -1; 2567 } 2568 } 2569 #endif 2570 #ifdef BCM_SRAM_SCAN_SUPPORT 2571 sram_scan_running = soc_sram_scan_running (unit, &sram_scan_rate, 2572 &sram_scan_interval); 2573 if (sram_scan_running > 0){ 2574 if (soc_sram_scan_stop(unit)) { 2575 return -1; 2576 } 2577 } 2578 #endif 2579 2580 if (test_params->verbose_prints) { 2581 2582 } 2583 if (test_params->error_prints) { 2584 2585 } 2586 2587 /*Test individual memories and inject individual errors.*/ 2588 if (test_params->mem != INVALIDm) { 2589 if (test_params->inject_only == TRUE) { 2590 soc_ser_inject_error(unit, FALSE, test_params->mem, 0, -1, 0); 2591 } else { 2592 rv = soc_ser_test_mem(unit, test_params->mem, 2593 test_params->test_type, 2594 test_params->cmd_print); 2595 if (SOC_FAILURE(rv)) { 2596 test_error(unit, 2597 "Error during ser test: %s\n", 2598 soc_errmsg(rv)); 2599 } 2600 } 2601 } else { 2602 if (test_params->inject_only == TRUE) { 2603 cli_out("Parameter 'injectOnly' may only be used " 2604 "when 'memory' is also specified.\n"); 2605 } else { 2606 rv = soc_ser_test(unit, test_params->test_type); 2607 if (SOC_FAILURE(rv)) { 2608 test_error(unit, 2609 "Error during ser test: %s\n", 2610 soc_errmsg(rv)); 2611 } 2612 } 2613 } 2614 2615 if (!force_read_through) { 2616 SOC_MEM_FORCE_READ_THROUGH_SET(unit, 0); 2617 } 2618 rv = soc_reset_init(unit); 2619 if (SOC_FAILURE(rv)) { 2620 cli_out("Error during soc reset. Aborting.\n"); 2621 return rv; 2622 } 2623 /* Load Cancun files */ 2624 #if defined(CANCUN_SUPPORT) && !defined(NO_SAL_APPL) 2625 if (soc_feature(unit, soc_feature_cancun)) { 2626 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CMH); 2627 if (rv != SOC_E_NONE) { 2628 cli_out("Error during loading cmh. Aborting.\n"); 2629 return rv; 2630 } 2631 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CCH); 2632 if (rv != SOC_E_NONE) { 2633 cli_out("Error during loading cch. Aborting.\n"); 2634 return rv; 2635 } 2636 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CEH); 2637 if (rv != SOC_E_NONE) { 2638 cli_out("Error during loading ceh. Aborting.\n"); 2639 return rv; 2640 } 2641 } 2642 #endif 2643 /*init misc*/ 2644 rv = soc_misc_init(unit); 2645 if (SOC_FAILURE(rv)) { 2646 cli_out("Error during misc init. Aborting.\n"); 2647 return rv; 2648 } 2649 /* Load Cancun files */ 2650 #if defined(CANCUN_SUPPORT) && !defined(NO_SAL_APPL) 2651 if (soc_feature(unit, soc_feature_cancun)) { 2652 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CIH); 2653 if (rv != SOC_E_NONE) { 2654 cli_out("Error during loading cih. Aborting.\n"); 2655 return rv; 2656 } 2657 if (soc_feature(unit, soc_feature_flex_flow)) { 2658 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CFH); 2659 if (rv != SOC_E_NONE) { 2660 cli_out("Error during loading cfh. Aborting.\n"); 2661 return rv; 2662 } 2663 } 2664 } 2665 #endif 2666 2667 #if defined(BCM_SABER2_SUPPORT) 2668 if (SOC_IS_SABER2(unit)) { 2669 /*init mmu */ 2670 rv = soc_mmu_init(unit); 2671 if (rv != SOC_E_NONE) { 2672 cli_out("Error during mmu init. Aborting.\n"); 2673 return rv; 2674 } 2675 } 2676 #endif 2677 2678 #ifdef INCLUDE_MEM_SCAN 2679 if (mem_scan_running) { 2680 if(soc_mem_scan_start(unit, mem_scan_rate, mem_scan_interval)){ 2681 return -1; 2682 } 2683 } 2684 #endif 2685 #ifdef BCM_SRAM_SCAN_SUPPORT 2686 if (sram_scan_running) { 2687 if(soc_sram_scan_start(unit, sram_scan_rate, sram_scan_interval)){ 2688 return -1; 2689 } 2690 } 2691 #endif 2692 return rv; 2693 } 2694 2695 #if defined(BCM_TOMAHAWK3_SUPPORT) && defined(BCM_56980_A0) 2696 extern _soc_bus_buffer_ser_force_info_t _soc_bcm56980_a0_bus_buffer_ser_force_info[]; 2697 extern uint32 ser_th3_bus_buffer_hwbase[]; 2698 extern _soc_bus_buffer_ser_force_info_t ser_th3_bus_buffer_skip_test[]; 2699 #endif 2700 #if defined(BCM_TOMAHAWK2_SUPPORT) && defined(BCM_56970_A0) 2701 extern _soc_bus_buffer_ser_force_info_t _soc_bcm56970_a0_bus_buffer_ser_force_info[]; 2702 extern uint32 ser_th2_bus_buffer_hwbase[]; 2703 extern _soc_bus_buffer_ser_force_info_t ser_th2_bus_buffer_skip_test[]; 2704 #endif 2705 #if defined(BCM_TRIDENT3_SUPPORT) && defined(BCM_56870_A0) 2706 extern _soc_bus_buffer_ser_force_info_t _soc_bcm56870_a0_bus_buffer_ser_force_info[]; 2707 extern uint32 ser_td3_bus_buffer_hwbase[]; 2708 extern _soc_bus_buffer_ser_force_info_t ser_td3_bus_buffer_skip_test[]; 2709 #endif 2710 #ifdef BCM_TOMAHAWK_SUPPORT 2711 extern _soc_bus_buffer_ser_force_info_t _soc_bcm56960_a0_bus_buffer_ser_force_info[]; 2712 extern uint32 ser_th_bus_buffer_hwbase[]; 2713 #endif 2714 #ifdef BCM_TRIDENT2PLUS_SUPPORT 2715 extern _soc_bus_buffer_ser_force_info_t _soc_bcm56860_a0_bus_buffer_ser_force_info[]; 2716 extern uint32 ser_td2p_bus_buffer_hwbase[]; 2717 extern _soc_bus_buffer_ser_force_info_t ser_td2p_bus_buffer_skip_test[]; 2718 #endif 2719 2720 soc_error_t ser_bus_buffer_inject_error(int unit, soc_reg_t force_reg, 2721 soc_field_t force_fld) 2722 { 2723 uint64 rval64; 2724 uint32 rval = 0; 2725 uint32 value = 1; 2726 2727 if (SOC_REG_IS_VALID(unit, force_reg)) { 2728 #ifdef BCM_TOMAHAWK3_SUPPORT 2729 if (SOC_IS_TOMAHAWK3(unit) && 2730 ((force_fld == EGR_MPB_ECC_FORCE_ERRf) || 2731 (force_fld == PKT_BUF_ECC_CORRUPTf))) { 2732 value = 2; 2733 } 2734 #endif 2735 #ifdef BCM_TRIDENT3_SUPPORT 2736 if (SOC_IS_TRIDENT3(unit) && (force_fld == INITBUF_ECC_CORRUPTf)) { 2737 value = 3; 2738 } 2739 #endif 2740 if (SOC_REG_IS_64(unit,force_reg)) { 2741 COMPILER_64_ZERO(rval64); 2742 SOC_IF_ERROR_RETURN 2743 (soc_reg_get(unit, force_reg, REG_PORT_ANY, 0, &rval64)); 2744 soc_reg64_field32_set(unit, force_reg, &rval64, force_fld, value); 2745 SOC_IF_ERROR_RETURN 2746 (soc_reg_set(unit, force_reg, REG_PORT_ANY, 0, rval64)); 2747 } else { 2748 SOC_IF_ERROR_RETURN 2749 (soc_reg32_get(unit, force_reg, REG_PORT_ANY, 0, &rval)); 2750 soc_reg_field_set(unit, force_reg, &rval, force_fld, value); 2751 SOC_IF_ERROR_RETURN 2752 (soc_reg32_set(unit, force_reg, REG_PORT_ANY, 0, rval)); 2753 } 2754 } 2755 2756 return SOC_E_NONE; 2757 } 2758 2759 soc_error_t ser_bus_buffer_trigger_error(int unit, int count) 2760 { 2761 int rv = SOC_E_NONE; 2762 int pkt_flags; 2763 int i = 0; 2764 bcm_pkt_t *tx_pkt; 2765 bcm_mac_t dstmac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}; 2766 bcm_mac_t srcmac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}; 2767 bcm_port_t lport = 1; 2768 2769 BCM_IF_ERROR_RETURN(bcm_port_loopback_set(unit, lport, BCM_PORT_LOOPBACK_MAC)); 2770 2771 pkt_flags = BCM_TX_CRC_APPEND | BCM_TX_NO_PAD; 2772 rv = bcm_pkt_alloc(unit, 256, pkt_flags, &tx_pkt); 2773 if (rv != BCM_E_NONE) { 2774 LOG_ERROR(BSL_LS_APPL_COMMON, 2775 (BSL_META_U(unit, 2776 "ERROR: Unable to alloc buffer for pkt\n"))); 2777 return rv; 2778 } 2779 2780 tx_pkt->unit = unit; 2781 tx_pkt->call_back = 0; 2782 tx_pkt->blk_count = 1; 2783 BCM_PKT_HDR_SMAC_SET(tx_pkt, srcmac); 2784 BCM_PKT_HDR_DMAC_SET(tx_pkt, dstmac); 2785 BCM_PKT_PORT_SET(tx_pkt, lport, TRUE, FALSE); 2786 for (i = 0; i < count; i ++) { 2787 rv = bcm_tx(unit, tx_pkt, NULL); 2788 if (rv != BCM_E_NONE) { 2789 LOG_ERROR(BSL_LS_APPL_COMMON, 2790 (BSL_META_U(unit, 2791 "ERROR: Unable to send pkt\n"))); 2792 break; 2793 } 2794 } 2795 2796 bcm_pkt_free(unit, tx_pkt); 2797 2798 return rv; 2799 } 2800 2801 soc_error_t ser_bus_buffer_report_check(int unit, uint32 hwbase) 2802 { 2803 soc_error_t rv = SOC_E_NONE; 2804 2805 rv = soc_ser_bus_buffer_log_find(unit, hwbase); 2806 2807 if (rv != SOC_E_NONE) { 2808 return SOC_E_FAIL; 2809 } 2810 2811 return rv; 2812 } 2813 2814 soc_error_t ser_bus_buffer_config_clean(int unit, soc_reg_t force_reg, 2815 soc_field_t force_fld) 2816 { 2817 uint64 rval64; 2818 uint32 rval = 0; 2819 bcm_port_t lport = 1; 2820 2821 if (SOC_REG_IS_VALID(unit, force_reg)) { 2822 if (SOC_REG_IS_64(unit,force_reg)) { 2823 COMPILER_64_ZERO(rval64); 2824 SOC_IF_ERROR_RETURN 2825 (soc_reg_get(unit, force_reg, REG_PORT_ANY, 0, &rval64)); 2826 soc_reg64_field32_set(unit, force_reg, &rval64, force_fld, 0); 2827 SOC_IF_ERROR_RETURN 2828 (soc_reg_set(unit, force_reg, REG_PORT_ANY, 0, rval64)); 2829 } else { 2830 SOC_IF_ERROR_RETURN 2831 (soc_reg32_get(unit, force_reg, REG_PORT_ANY, 0, &rval)); 2832 soc_reg_field_set(unit, force_reg, &rval, force_fld, 0); 2833 SOC_IF_ERROR_RETURN 2834 (soc_reg32_set(unit, force_reg, REG_PORT_ANY, 0, rval)); 2835 } 2836 } 2837 2838 /* trigger again to make sure the error is not exist */ 2839 ser_bus_buffer_trigger_error(unit, 5); 2840 sal_usleep(500000); 2841 BCM_IF_ERROR_RETURN(bcm_port_loopback_set(unit, lport, BCM_PORT_LOOPBACK_NONE)); 2842 2843 return SOC_E_NONE; 2844 } 2845 2846 int ser_bus_buffer_test_perform(int unit) 2847 { 2848 int i, j; 2849 int skip_test; 2850 int count = 1; 2851 soc_error_t rv = SOC_E_NONE; 2852 uint32 test_cnt = 0; 2853 uint32 fail_cnt = 0; 2854 uint32 skip_cnt = 0; 2855 uint32 *hwbase = NULL; 2856 _soc_bus_buffer_ser_force_info_t *ser_bus_buffer_info = NULL; 2857 _soc_bus_buffer_ser_force_info_t *ser_bus_buffer_skip = NULL; 2858 2859 #if defined(BCM_TOMAHAWK3_SUPPORT) && defined(BCM_56980_A0) 2860 if (SOC_IS_TOMAHAWK3(unit)) { 2861 ser_bus_buffer_info = _soc_bcm56980_a0_bus_buffer_ser_force_info; 2862 ser_bus_buffer_skip = ser_th3_bus_buffer_skip_test; 2863 hwbase = ser_th3_bus_buffer_hwbase; 2864 } else 2865 #endif 2866 #if defined(BCM_TOMAHAWK2_SUPPORT) && defined(BCM_56970_A0) 2867 if (SOC_IS_TOMAHAWK2(unit)) { 2868 ser_bus_buffer_info = _soc_bcm56970_a0_bus_buffer_ser_force_info; 2869 ser_bus_buffer_skip = ser_th2_bus_buffer_skip_test; 2870 hwbase = ser_th2_bus_buffer_hwbase; 2871 } else 2872 #endif 2873 #if defined(BCM_TRIDENT3_SUPPORT) && defined(BCM_56870_A0) 2874 if (SOC_IS_TRIDENT3(unit)) { 2875 ser_bus_buffer_info = _soc_bcm56870_a0_bus_buffer_ser_force_info; 2876 ser_bus_buffer_skip = ser_td3_bus_buffer_skip_test; 2877 hwbase = ser_td3_bus_buffer_hwbase; 2878 } else 2879 #endif 2880 #ifdef BCM_TOMAHAWK_SUPPORT 2881 if (SOC_IS_TOMAHAWK(unit)) { 2882 ser_bus_buffer_info = _soc_bcm56960_a0_bus_buffer_ser_force_info; 2883 ser_bus_buffer_skip = NULL; 2884 hwbase = ser_th_bus_buffer_hwbase; 2885 } else 2886 #endif 2887 #ifdef BCM_TRIDENT2PLUS_SUPPORT 2888 if (SOC_IS_TD2P_TT2P(unit)) { 2889 ser_bus_buffer_info = _soc_bcm56860_a0_bus_buffer_ser_force_info; 2890 ser_bus_buffer_skip = ser_td2p_bus_buffer_skip_test; 2891 hwbase = ser_td2p_bus_buffer_hwbase; 2892 } else 2893 #endif 2894 { 2895 ser_bus_buffer_skip = NULL; 2896 hwbase = NULL; 2897 } 2898 2899 /* coverity[Logically dead code] */ 2900 if (hwbase == NULL) { 2901 LOG_CLI((BSL_META_U(unit, "\nTR 143 did not support!\n"))); 2902 return SOC_E_UNAVAIL; 2903 } 2904 for (i = 0; ; i++) { 2905 skip_test = FALSE; 2906 if (ser_bus_buffer_skip != NULL) { 2907 for (j = 0; ; j++) { 2908 if (ser_bus_buffer_skip[j].force_reg == INVALIDr) { 2909 break; 2910 } 2911 if ((ser_bus_buffer_info[i].force_reg == ser_bus_buffer_skip[j].force_reg) && 2912 (ser_bus_buffer_info[i].force_fld == ser_bus_buffer_skip[j].force_fld)) { 2913 skip_cnt++; 2914 skip_test = TRUE; 2915 break; 2916 } 2917 } 2918 } 2919 if (ser_bus_buffer_info[i].force_reg == INVALIDr) { 2920 break; 2921 } 2922 if (skip_test) { 2923 continue; 2924 } 2925 ser_bus_buffer_inject_error(unit, ser_bus_buffer_info[i].force_reg, 2926 ser_bus_buffer_info[i].force_fld); 2927 #ifdef BCM_TRIDENT3_SUPPORT 2928 if (SOC_IS_TRIDENT3(unit) && 2929 (ser_bus_buffer_info[i].force_fld == SW3_EOP_BUFFER_B_ECC_CORRUPTf)) { 2930 count = 6; 2931 } else 2932 #endif 2933 { 2934 count = 1; 2935 } 2936 ser_bus_buffer_trigger_error(unit, count); 2937 sal_usleep(1500000); 2938 rv = ser_bus_buffer_report_check(unit, hwbase[i]); 2939 if (rv != SOC_E_NONE) { 2940 cli_out("failed bus/buffer: %s\r\n", ser_bus_buffer_info[i].name); 2941 fail_cnt++; 2942 } 2943 ser_bus_buffer_config_clean(unit, ser_bus_buffer_info[i].force_reg, 2944 ser_bus_buffer_info[i].force_fld); 2945 test_cnt++; 2946 sal_usleep(1000); 2947 } 2948 2949 LOG_CLI((BSL_META_U(unit, "\nH/W bus/buffer tested on unit %d: %d\n"), 2950 unit, test_cnt)); 2951 LOG_CLI((BSL_META_U(unit, "H/W bus/buffer tests passed:\t%d\n"), 2952 test_cnt - fail_cnt)); 2953 LOG_CLI((BSL_META_U(unit, "H/W bus/buffer tests failed:\t%d\n"), 2954 fail_cnt)); 2955 LOG_CLI((BSL_META_U(unit, "H/W bus/buffer tests skipped:\t%d\n"), 2956 skip_cnt)); 2957 return BCM_E_NONE; 2958 } 2959 2960 int ser_bus_buffer_test_init(int unit, args_t *arg, void **p) 2961 { 2962 return 0; 2963 } 2964 2965 int ser_bus_buffer_test_done(int unit, void *p) 2966 { 2967 return 0; 2968 } 2969 2970 int ser_bus_buffer_test(int unit, args_t *arg, void *p) 2971 { 2972 int rv = SOC_E_NONE; 2973 int force_read_through = SOC_MEM_FORCE_READ_THROUGH(unit); 2974 #ifdef INCLUDE_MEM_SCAN 2975 sal_usecs_t mem_scan_interval = 0; 2976 int mem_scan_rate = 0, mem_scan_running; 2977 #endif 2978 #ifdef BCM_SRAM_SCAN_SUPPORT 2979 sal_usecs_t sram_scan_interval = 0; 2980 int sram_scan_rate = 0, sram_scan_running; 2981 #endif 2982 if (!force_read_through) { 2983 SOC_MEM_FORCE_READ_THROUGH_SET(unit, 1); 2984 } 2985 2986 #ifdef INCLUDE_MEM_SCAN 2987 mem_scan_running = soc_mem_scan_running (unit, &mem_scan_rate, 2988 &mem_scan_interval); 2989 if( mem_scan_running > 0){ 2990 if( soc_mem_scan_stop(unit) ) { 2991 return -1; 2992 } 2993 } 2994 #endif 2995 #ifdef BCM_SRAM_SCAN_SUPPORT 2996 sram_scan_running = soc_sram_scan_running (unit, &sram_scan_rate, 2997 &sram_scan_interval); 2998 if (sram_scan_running > 0){ 2999 if (soc_sram_scan_stop(unit)) { 3000 return -1; 3001 } 3002 } 3003 #endif 3004 3005 /*Test individual memories and inject individual errors.*/ 3006 rv = ser_bus_buffer_test_perform(unit); 3007 if (SOC_FAILURE(rv)) { 3008 test_error(unit, 3009 "Error during ser test: %s\n", 3010 soc_errmsg(rv)); 3011 } 3012 3013 if (!force_read_through) { 3014 SOC_MEM_FORCE_READ_THROUGH_SET(unit, 0); 3015 } 3016 rv = soc_reset_init(unit); 3017 if (SOC_FAILURE(rv)) { 3018 cli_out("Error during soc reset. Aborting.\n"); 3019 return rv; 3020 } 3021 /* Load Cancun files */ 3022 #if defined(CANCUN_SUPPORT) && !defined(NO_SAL_APPL) 3023 if (soc_feature(unit, soc_feature_cancun)) { 3024 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CMH); 3025 if (rv != SOC_E_NONE) { 3026 cli_out("Error during loading cmh. Aborting.\n"); 3027 return rv; 3028 } 3029 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CCH); 3030 if (rv != SOC_E_NONE) { 3031 cli_out("Error during loading cch. Aborting.\n"); 3032 return rv; 3033 } 3034 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CEH); 3035 if (rv != SOC_E_NONE) { 3036 cli_out("Error during loading ceh. Aborting.\n"); 3037 return rv; 3038 } 3039 } 3040 #endif 3041 /*init misc*/ 3042 rv = soc_misc_init(unit); 3043 if (SOC_FAILURE(rv)) { 3044 cli_out("Error during misc init. Aborting.\n"); 3045 return rv; 3046 } 3047 /* Load Cancun files */ 3048 #if defined(CANCUN_SUPPORT) && !defined(NO_SAL_APPL) 3049 if (soc_feature(unit, soc_feature_cancun)) { 3050 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CIH); 3051 if (rv != SOC_E_NONE) { 3052 cli_out("Error during loading cih. Aborting.\n"); 3053 return rv; 3054 } 3055 if (soc_feature(unit, soc_feature_flex_flow)) { 3056 rv = soc_cancun_generic_load(unit, CANCUN_SOC_FILE_TYPE_CFH); 3057 if (rv != SOC_E_NONE) { 3058 cli_out("Error during loading cfh. Aborting.\n"); 3059 return rv; 3060 } 3061 } 3062 } 3063 #endif 3064 3065 #ifdef INCLUDE_MEM_SCAN 3066 if (mem_scan_running) { 3067 if(soc_mem_scan_start(unit, mem_scan_rate, mem_scan_interval)){ 3068 return -1; 3069 } 3070 } 3071 #endif 3072 #ifdef BCM_SRAM_SCAN_SUPPORT 3073 if (sram_scan_running) { 3074 if(soc_sram_scan_start(unit, sram_scan_rate, sram_scan_interval)){ 3075 return -1; 3076 } 3077 } 3078 #endif 3079 return rv; 3080 } 3081 #endif /* defined (SER_TR_TEST_SUPPORT)*/ 3082 3083 #endif /* defined (BCM_ESW_SUPPORT) || defined (BCM_PETRA_SUPPORT) || defined (BCM_DFE_SUPPORT) */ 3084 3085 #ifdef BCM_DNX_SUPPORT 3086 /* Function that is comparing if the write value is equal to the read one. If it is print an error */ 3087 static int compare_mem_entry_clear_test(int unit, soc_mem_t mem, int array_index, int index, uint32 *pattern, uint32 *entry_buf, int nof_data_bits, char *test) { 3088 int rv=0; 3089 if (SHR_BITEQ_RANGE(entry_buf, pattern, 0, nof_data_bits)) { /*Compare only the amount of bits in the memory */ 3090 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "%s: Memory %s[%d]: entry %d read with a same value than the one written to it\n"), 3091 test, SOC_MEM_NAME(unit, mem), array_index, index)); 3092 rv = -1; 3093 } 3094 return rv; 3095 } 3096 /* Function that checks if memory is an alias */ 3097 static int 3098 is_main_mem_read( 3099 int unit, 3100 soc_mem_t mem) 3101 { 3102 soc_mem_t orig_mem = mem; 3103 SOC_MEM_ALIAS_TO_ORIG(unit, mem); 3104 return orig_mem == mem ? 1 : 0; 3105 } 3106 /* Skip function needed when looping over all memories */ 3107 int 3108 test_clear_mem_filter(int unit, soc_mem_t mem) 3109 { 3110 int rv = 0; 3111 3112 if (!is_main_mem_read(unit, mem)) 3113 { 3114 return 1; 3115 } 3116 switch (mem) 3117 { 3118 /* 3119 * The HBM memories are not real memories 3120 */ 3121 case BRDC_HBC_HBM_PHY_CH_REGISTER_ACCESSm: 3122 case BRDC_HBC_HBM_DRAM_CPU_ACCESSm: 3123 case BRDC_FSRD_FSRD_PROM_MEMm: 3124 case HBC_HBM_DRAM_CPU_ACCESSm: 3125 case HBC_HBM_PHY_CH_REGISTER_ACCESSm: 3126 case HBMC_HBM_PHY_CHM_REGISTER_ACCESSm: 3127 /* 3128 * Not a real memory 3129 */ 3130 case FSRD_FSRD_PROM_MEMm: 3131 3132 /* 3133 * The CDU instrumentation and rx/tx memories do not have to be initialized and can not be written by 3134 * DMA 3135 */ 3136 3137 3138 /* 3139 * The {DDHA,DDHB,DHC}_MACRO_* memories are not real and do not need initialization 3140 */ 3141 case DDHB_MACRO_0_ABK_BANK_Am: 3142 case DDHB_MACRO_0_ABK_BANK_Bm: 3143 case DDHB_MACRO_0_ENTRY_BANKm: 3144 case DDHB_MACRO_1_ABK_BANK_Am: 3145 case DDHB_MACRO_1_ABK_BANK_Bm: 3146 case DDHB_MACRO_1_ENTRY_BANKm: 3147 case DDHA_MACRO_0_ABK_BANK_Am: 3148 case DDHA_MACRO_0_ABK_BANK_Bm: 3149 case DDHA_MACRO_0_ENTRY_BANKm: 3150 case DDHA_MACRO_1_ABK_BANK_Am: 3151 case DDHA_MACRO_1_ABK_BANK_Bm: 3152 case DDHA_MACRO_1_ENTRY_BANKm: 3153 case DHC_MACRO_ABK_BANK_Am: 3154 case DHC_MACRO_ABK_BANK_Bm: 3155 case DHC_MACRO_ENTRY_BANKm: 3156 3157 /* 3158 * These are address spaces saved for ilkn memory mapped registers. 3159 */ 3160 case ILE_PORT_0_CPU_ACCESSm: 3161 case ILE_PORT_1_CPU_ACCESSm: 3162 3163 /* 3164 * All below are either not real memories or dont have protection. - Mosi Ravia 3165 */ 3166 case KAPS_RPB_TCAM_CPU_COMMANDm: 3167 case KAPS_TCAM_ECC_MEMORYm: 3168 case MDB_ARM_KAPS_TCMm: 3169 case MDB_EEDB_ABK_BANKm: 3170 case MACT_CPU_REQUESTm: 3171 case ECI_SAM_CTRLm: 3172 3173 /* 3174 * SCH_SCHEDULER_INIT is not a real memory 3175 */ 3176 case SCH_SCHEDULER_INITm: 3177 case SQM_DEQ_QSTATE_PENDING_FIFOm: 3178 case SQM_ENQ_COMMAND_RXIm: 3179 case SQM_PDB_LINK_LISTm: 3180 case SQM_PDMm: 3181 case SQM_QUEUE_DATA_MEMORYm: 3182 case SQM_TX_BUNDLE_MEMORYm: 3183 case SQM_TX_PACKET_DESCRIPTOR_FIFOS_MEMORYm: 3184 case SCH_FORCE_STATUS_MESSAGEm: 3185 case SCH_RESERVED_37m: 3186 case SCH_RESERVED_54m: 3187 case EPS_CAL_CAL_INDX_MUXm: 3188 case EPS_OTM_CALENDAR_CRDT_TABLEm: 3189 case EPS_OTM_HP_CRDT_TABLEm: 3190 case EPS_OTM_LP_CRDT_TABLEm: 3191 case EPS_QP_CREDIT_TABLEm: 3192 case EPS_TCG_CREDIT_TABLEm: 3193 case AM_TABLEm: 3194 case CDPORT_TSC_UCMEM_DATAm: 3195 /* 3196 * The *_DEBUG_UNIT and *_HIT_INDICATION memories are not real 3197 */ 3198 case ERPP_EPMFCS_TCAM_HIT_INDICATIONm: 3199 case IPPA_VTDCS_TCAM_HIT_INDICATIONm: 3200 case IPPA_VTECS_TCAM_HIT_INDICATIONm: 3201 case IPPB_FLPACS_TCAM_HIT_INDICATIONm: 3202 case IPPB_FLPBCS_TCAM_HIT_INDICATIONm: 3203 case IPPC_PMFACSA_TCAM_HIT_INDICATIONm: 3204 case IPPC_PMFACSB_TCAM_HIT_INDICATIONm: 3205 case IPPD_PMFBCS_TCAM_HIT_INDICATIONm: 3206 case IPPD_PMFBCS_TCAM_BANK_COMMANDm: 3207 case IPPD_PMFBCS_TCAM_BANK_REPLYm: 3208 case IPPD_PMFBCS_ACTIONm: 3209 case IPPE_LLRCS_TCAM_BANK_COMMANDm: 3210 case IPPE_PRTCAM_TCAM_HIT_INDICATIONm: 3211 case IPPE_LLRCS_TCAM_HIT_INDICATIONm: 3212 case IPPF_VTACS_TCAM_HIT_INDICATIONm: 3213 case IPPF_VTCCS_TCAM_HIT_INDICATIONm: 3214 case IPPF_VTBCS_TCAM_HIT_INDICATIONm: 3215 case KAPS_RPB_TCAM_HIT_INDICATIONm: 3216 case KAPS_TCAM_HIT_INDICATIONm: 3217 case IPPA_VTDCS_TCAM_BANKm: 3218 case IPPA_VTECS_TCAM_BANKm: 3219 case IPPB_FLPACS_TCAM_BANKm: 3220 case IPPB_FLPBCS_TCAM_BANKm: 3221 case MDB_EEDB_ENTRY_BANKm: 3222 case IPPE_LLRCS_ACTIONm: 3223 case IPPE_LLRCS_TCAM_BANK_REPLYm: 3224 case IPPE_PRTCAM_TCAM_BANK_COMMANDm: 3225 case IPPE_PRTCAM_TCAM_BANK_REPLYm: 3226 /* 3227 * NOT real memories. 3228 */ 3229 case MDB_EOEM_0m: 3230 case MDB_EOEM_1m: 3231 case MDB_ESEMm: 3232 case MDB_EXEM_1m: 3233 case MDB_EXEM_2m: 3234 case MDB_GLEM_0m: 3235 case MDB_GLEM_1m: 3236 case MDB_IOEM_0m: 3237 case MDB_IOEM_1m: 3238 case MDB_ISEM_1m: 3239 case MDB_ISEM_2m: 3240 case MDB_ISEM_3m: 3241 case MDB_MC_IDm: 3242 case MDB_RMEPm: 3243 case MDB_ARM_MEM_0m: 3244 /* 3245 * Dynamic and should be skipped. - ASIC 3246 */ 3247 case EVNT_ASSIGNED_CMIC_ENGINE_TABLEm: 3248 case ERPP_EPMFCS_TCAM_BANKm: 3249 case IPPC_PMFACSA_TCAM_BANKm: 3250 case IPPC_PMFACSB_TCAM_BANKm: 3251 case IPPD_PMFBCS_TCAM_BANKm: 3252 case IPPE_LLRCS_TCAM_BANKm: 3253 case IPPE_PRTCAM_TCAM_BANKm: 3254 case IPPF_VTACS_TCAM_BANKm: 3255 case IPPF_VTBCS_TCAM_BANKm: 3256 case IPPF_VTCCS_TCAM_BANKm: 3257 case IPPB_MPLS_LABEL_TYPES_CAM_0m: 3258 case IPPB_MPLS_LABEL_TYPES_CAM_1m: 3259 case TCAM_TCAM_ACTION_HIT_INDICATIONm: 3260 case TCAM_TCAM_ACTION_HIT_INDICATION_SMALLm: 3261 case TCAM_TCAM_BANKm: 3262 3263 case RX_LKUP_1588_MEM_400Gm: 3264 case RX_LKUP_1588_MEM_MPP0m: 3265 case RX_LKUP_1588_MEM_MPP1m: 3266 case SPEED_ID_TABLEm: 3267 case SPEED_PRIORITY_MAP_TBLm: 3268 case TX_LKUP_1588_MEM_400Gm: 3269 case TX_LKUP_1588_MEM_MPP0m: 3270 case TX_LKUP_1588_MEM_MPP1m: 3271 case UM_TABLEm: 3272 return 1; 3273 default: 3274 break; 3275 } 3276 return rv; 3277 } 3278 /* The function is returning the number of data bits for a given memory */ 3279 uint32 3280 get_memory_nof_data_bits( 3281 int unit, 3282 soc_mem_t mem) 3283 { 3284 int f; 3285 soc_mem_info_t *memp; 3286 uint32 nof_data_bits = 0; 3287 soc_field_info_t *fieldp; 3288 soc_field_info_t *last_field_p = NULL; 3289 uint32 nof_bits_in_mem = 0, last_bit_of_field = 0; /* number of bits in a memory entry */ 3290 memp = &SOC_MEM_INFO(unit, mem); 3291 /* Check the entry width with and without the last ECCf or PARITYf field */ 3292 for (f = 0; f < memp->nFields; f++) 3293 { 3294 fieldp = &(memp->fields[f]); 3295 3296 last_bit_of_field = fieldp->bp + fieldp->len; 3297 if (last_bit_of_field > nof_bits_in_mem) { 3298 nof_bits_in_mem = last_bit_of_field; 3299 last_field_p = fieldp; 3300 } 3301 3302 } 3303 nof_data_bits = nof_bits_in_mem; 3304 if (last_field_p != NULL) 3305 { 3306 if ((last_field_p->field == ECCf) || (last_field_p->field == PARITYf)) 3307 { 3308 nof_data_bits -= last_field_p->len; 3309 } 3310 } 3311 /* Check if the bit numbers are calculated correctly */ 3312 assert(((nof_bits_in_mem + 7) / 8 == soc_mem_entry_bytes(unit, mem)) && nof_data_bits > 0 && nof_data_bits <= nof_bits_in_mem); 3313 3314 return nof_data_bits; 3315 } 3316 3317 /* Function that is used for writting the pattern to a single memory */ 3318 int 3319 memories_clear_test_write( 3320 int unit, 3321 soc_mem_t mem, 3322 uint32 *write_buf) 3323 { 3324 int index = 0, index_min, index_max, array_index_min, array_index_max, array_index; 3325 3326 soc_block_t blk; 3327 uint32 write_low_bit_data = 0; 3328 uint32 nof_data_bits; /* number of bits in a memory entry excluding ECC/parity that may exist in the last 3329 * memory field */ 3330 int rv = -1; 3331 index_min = soc_mem_index_min(unit, mem); 3332 index_max = soc_mem_index_max(unit, mem); 3333 array_index_min = array_index_max = 0; 3334 /* 3335 * Check the entry width with and without the last ECCf or PARITYf field 3336 */ 3337 nof_data_bits = get_memory_nof_data_bits(unit, mem); 3338 3339 if (SOC_MEM_IS_ARRAY(unit, mem)) 3340 { 3341 soc_mem_array_info_t *maip = SOC_MEM_ARRAY_INFOP(unit, mem); 3342 if (maip) 3343 { 3344 array_index_max = (maip->numels - 1) + maip->first_array_index; 3345 array_index_min = maip->first_array_index; 3346 } 3347 } 3348 3349 /* 3350 * Writting the pattern to the first and last index in order for the test to be faster 3351 */ 3352 for (array_index = array_index_min; array_index <= array_index_max; array_index++) 3353 { 3354 for (blk = SOC_MEM_BLOCK_MIN(unit, mem); blk <= SOC_MEM_BLOCK_MAX(unit, mem); blk++) 3355 { 3356 if (nof_data_bits < 4) 3357 { 3358 uint32 bits_range = ((uint32) 1) << nof_data_bits; 3359 for (index = index_min; index <= index_max; index++) 3360 { 3361 write_low_bit_data = ((index + 1) % bits_range); 3362 rv = soc_mem_array_write(unit, mem, array_index, blk, index, &write_low_bit_data); 3363 if (rv < 0) 3364 { 3365 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Write to memory %s[%d].%s entry %d Failed\n"), 3366 SOC_MEM_NAME(unit, mem), array_index, SOC_BLOCK_NAME(unit, blk), 3367 index)); 3368 } 3369 } 3370 } 3371 else 3372 { 3373 rv = soc_mem_array_write(unit, mem, array_index, blk, index_min, write_buf); 3374 if (rv < 0) 3375 { 3376 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Write to memory %s[%d].%s entry %d Failed\n"), 3377 SOC_MEM_NAME(unit, mem), array_index, SOC_BLOCK_NAME(unit, blk), 3378 index_min)); 3379 } 3380 rv = soc_mem_array_write(unit, mem, array_index, blk, index_max, write_buf); 3381 if (rv < 0) 3382 { 3383 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Write to memory %s[%d].%s entry %d Failed\n"), 3384 SOC_MEM_NAME(unit, mem), array_index, SOC_BLOCK_NAME(unit, blk), 3385 index_max)); 3386 } 3387 } 3388 } 3389 } 3390 3391 return rv; 3392 } 3393 3394 /* 3395 * The function is taking a memory and reading the value to it and comparing it with the write value that we already wrote 3396 */ 3397 int 3398 memories_clear_test_read_and_compare( 3399 int unit, 3400 soc_mem_t mem, 3401 uint32 *read_buf, 3402 uint32 *write_buf, 3403 int *nof_memories_failed_read, 3404 int *nof_memories_failed_read_and_test) 3405 { 3406 int index, index_min, index_max, array_index_min, array_index_max, array_index, read_error = 0, test_error = 0; 3407 soc_block_t blk; 3408 int rv = -1; 3409 uint32 nof_data_bits; /* number of bits in a memory entry excluding ECC/parity that may exist in the last memory field */ 3410 index_min = soc_mem_index_min(unit, mem); 3411 index_max = soc_mem_index_max(unit, mem); 3412 array_index_min = array_index_max = 0; 3413 /* Check the entry width with and without the last ECCf or PARITYf field */ 3414 nof_data_bits = get_memory_nof_data_bits(unit, mem); 3415 3416 if (SOC_MEM_IS_ARRAY(unit, mem)) 3417 { 3418 soc_mem_array_info_t *maip = SOC_MEM_ARRAY_INFOP(unit, mem); 3419 if (maip) 3420 { 3421 array_index_max = (maip->numels - 1) + maip->first_array_index; 3422 array_index_min = maip->first_array_index; 3423 } 3424 } 3425 /* Reading and comparing the value from memories */ 3426 for (array_index = array_index_min; array_index <= array_index_max; array_index++) { 3427 for (blk = SOC_MEM_BLOCK_MIN(unit, mem); blk <= SOC_MEM_BLOCK_MAX(unit, mem); blk++) { 3428 if (nof_data_bits < 4) 3429 { 3430 uint32 bits_range = ((uint32)1) << nof_data_bits; 3431 int nof_same_values = 0; 3432 for (index = index_min; index <= index_max; index++) { 3433 rv = soc_mem_array_read(unit, mem, array_index, blk, index, read_buf); 3434 if (rv < 0) 3435 { 3436 LOG_ERROR(BSL_LS_APPL_TESTS, 3437 (BSL_META_U(unit, "ERROR READING: unit %d, memory %s.%s : %s\n"), unit, SOC_MEM_NAME(unit, mem), SOC_BLOCK_NAME(unit, blk),soc_errmsg(rv))); 3438 read_error = 1; 3439 ++nof_same_values; 3440 } else if (read_buf[0] == ((index + 1) % bits_range)) 3441 { 3442 ++nof_same_values; 3443 } 3444 } 3445 /* check that differences >= 50%, or for one bit memories differences >= 25% */ 3446 if (nof_same_values > (index_max - index_min + 1) / 2 && 3447 (nof_data_bits > 1 || nof_same_values > (index_max - index_min + 1) * 3 / 4)) 3448 { 3449 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Memory %s[%d].%s with %u data bits had %u out of %u values not changed\n"), 3450 SOC_MEM_NAME(unit, mem), array_index, SOC_BLOCK_NAME(unit, blk), 3451 (unsigned)nof_data_bits, nof_same_values, index_max - index_min + 1)); 3452 test_error=1; 3453 } 3454 } else { 3455 rv = soc_mem_array_read(unit, mem, array_index, blk, index_min, read_buf); 3456 if (rv < 0) 3457 { 3458 LOG_ERROR(BSL_LS_APPL_TESTS, 3459 (BSL_META_U(unit, "ERROR READING: unit %d, memory %s:%s : %s\n"), unit, SOC_MEM_NAME(unit, mem), SOC_BLOCK_NAME(unit, blk),soc_errmsg(rv))); 3460 read_error = 1; 3461 } else if (compare_mem_entry_clear_test(unit, mem, array_index, index_min, write_buf, read_buf, nof_data_bits, "Regular read")) { 3462 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Memory %s[%d].%s entry %d read with a same value than the one written to it\n"), 3463 SOC_MEM_NAME(unit, mem), array_index, SOC_BLOCK_NAME(unit, blk), 0)); 3464 test_error = 1; 3465 } 3466 rv = soc_mem_array_read(unit, mem, array_index, blk, index_max, read_buf); 3467 if (rv < 0) 3468 { 3469 LOG_ERROR(BSL_LS_APPL_TESTS, 3470 (BSL_META_U(unit, "ERROR READING: unit %d, memory %s:%s : %s\n"), unit, SOC_MEM_NAME(unit, mem), SOC_BLOCK_NAME(unit, blk), soc_errmsg(rv))); 3471 read_error = 1; 3472 } else if (compare_mem_entry_clear_test(unit, mem, array_index, index_min, write_buf, read_buf, nof_data_bits, "Regular read")) { 3473 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Memory %s[%d].%s entry %d read with a same value than the one written to it\n"), 3474 SOC_MEM_NAME(unit, mem), array_index, SOC_BLOCK_NAME(unit, blk), 0)); 3475 test_error = 1; 3476 } 3477 } 3478 } 3479 } 3480 if (read_error) { 3481 ++*nof_memories_failed_read; 3482 if (test_error) { 3483 ++*nof_memories_failed_read_and_test; 3484 } 3485 } 3486 return test_error ? BCM_E_FAIL : BCM_E_NONE; 3487 } 3488 3489 static int tr10_init_callback(int unit) { 3490 soc_mem_t mem; 3491 int i; 3492 int rv = 0; 3493 uint32 write_data[SOC_MAX_MEM_WORDS]; 3494 for (i = 0; i < SOC_MAX_MEM_WORDS; i++) 3495 { 3496 write_data[i] = 0xf234aa55; 3497 } 3498 for (mem = 0; mem < NUM_SOC_MEM; mem++) 3499 { 3500 if (!SOC_MEM_IS_VALID(unit, mem) || (soc_mem_index_count(unit, mem) == 0)) 3501 { 3502 continue; 3503 } 3504 if ((SOC_MEM_INFO(unit, mem).flags & (SOC_MEM_FLAG_READONLY | SOC_MEM_FLAG_WRITEONLY))) 3505 { 3506 continue; 3507 } 3508 if (test_clear_mem_filter(unit, mem)) 3509 { 3510 continue; 3511 } 3512 /* 3513 * Write values to the memory, for later testing that the written values were changed 3514 */ 3515 LOG_VERBOSE(BSL_LS_APPL_TESTS, (BSL_META("Write mem %s \n"), SOC_MEM_NAME(unit, mem))); 3516 rv = memories_clear_test_write(unit, mem, write_data); 3517 } 3518 if (rv < 0) 3519 { 3520 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Write to memory %s Failed\n"), 3521 SOC_MEM_NAME(unit, mem))); 3522 } 3523 return rv; 3524 } 3525 3526 /* The main function for TR 10 test if memories are cleared after init */ 3527 int 3528 memories_clear_test(int unit, args_t *a, void *pa) 3529 { 3530 3531 int rv = 0; 3532 soc_mem_t mem; 3533 int nof_memories_tested = 0, nof_memories_failed_test = 0, nof_memories_failed_read = 0, nof_memories_failed_read_and_test = 0; 3534 int i; 3535 uint32 read_data[SOC_MAX_MEM_WORDS] = {0}; 3536 uint32 write_data[SOC_MAX_MEM_WORDS]; 3537 dnx_startup_test_functions[unit] = tr10_init_callback; 3538 test_dnxc_init_test_init(unit, a, pa); 3539 test_dnxc_init_test(unit, a, pa); 3540 test_dnxc_init_test_done(unit, pa); 3541 dnx_startup_test_functions[unit] = NULL; 3542 for (i = 0; i < SOC_MAX_MEM_WORDS; i++) 3543 { 3544 write_data[i] = 0xf234aa56; 3545 } 3546 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 3547 if (!SOC_MEM_IS_VALID(unit, mem) || (soc_mem_index_count(unit, mem) == 0)) { 3548 continue; 3549 } 3550 if ((SOC_MEM_INFO(unit,mem).flags & 3551 (SOC_MEM_FLAG_READONLY | SOC_MEM_FLAG_WRITEONLY))) { 3552 continue; 3553 } 3554 if (test_clear_mem_filter(unit, mem)) { 3555 continue; 3556 } 3557 LOG_VERBOSE(BSL_LS_APPL_TESTS, 3558 (BSL_META("Read mem %s\n"), 3559 SOC_MEM_NAME(unit, mem))); 3560 if (memories_clear_test_read_and_compare(unit, mem, read_data, write_data, 3561 &nof_memories_failed_read, &nof_memories_failed_read_and_test)!= BCM_E_NONE) { 3562 nof_memories_failed_test++; 3563 } 3564 nof_memories_tested++; 3565 } 3566 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "Total %d memories, %d failed test, %d had read failures, %d both failed test and read\n"), 3567 nof_memories_tested, nof_memories_failed_test, nof_memories_failed_read, nof_memories_failed_read_and_test)); 3568 if (nof_memories_failed_test > 0) 3569 { 3570 rv = BCM_E_FAIL; 3571 } 3572 return rv; 3573 } 3574 3575 #endif /* BCM_DNX_SUPPORT */ 3576 3577 #undef _ERR_MSG_MODULE_NAME