hx5_cambist.h (22490B)
1 2 /* 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 #define HX5_EGR_ZONE_2_EDITOR_CONTROL_TCAM {hx5_egr_zone_2_editor_control_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_STATUSr} 9 10 #define HX5_TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM {hx5_tunnel_adapt_3_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_STATUSr} 11 12 #define HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_3 {hx5_ip_parser2_hme_stage_tcam_only_3_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_3r} 13 14 #define HX5_PHB_SELECT_TCAM {hx5_phb_select_tcam_name, NO_MODE, NO_MODE_FIELD, PHB_SELECT_TCAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, PHB_SELECT_TCAM_CAM_BIST_STATUSr} 15 16 #define HX5_FORWARDING_2_LOGICAL_TBL_SEL_TCAM {hx5_forwarding_2_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, FORWARDING_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_2_KEY_GEN_CAM_BIST_STATUSr} 17 18 #define HX5_MY_STATION_TCAM_2 {hx5_my_station_tcam_2_name, NO_MODE, NO_MODE_FIELD, MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_STATUSr} 19 20 #define HX5_EGR_FIELD_EXTRACTION_PROFILE_2_TCAM {hx5_egr_field_extraction_profile_2_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_STATUSr} 21 22 #define HX5_EGR_FIELD_EXTRACTION_PROFILE_1_TCAM {hx5_egr_field_extraction_profile_1_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_STATUSr} 23 24 #define HX5_L2_USER_ENTRY {hx5_l2_user_entry_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_ONLY_CAM_BIST_STATUSr} 25 26 #define HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_3 {hx5_ip_parser1_hme_stage_tcam_only_3_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_3r} 27 28 #define HX5_PKT_FLOW_SELECT_TCAM_1 {hx5_pkt_flow_select_tcam_1_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_1_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, PKT_FLOW_SELECT_TCAM_1_BIST_STATUSr} 29 30 #define HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_4 {hx5_ip_parser2_hme_stage_tcam_only_4_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_4r} 31 32 #define HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_0 {hx5_ip_parser1_hme_stage_tcam_only_0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_0r} 33 34 #define HX5_IP_MULTICAST_TCAM {hx5_ip_multicast_tcam_name, NO_MODE, NO_MODE_FIELD, IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_MULTICAST_TCAM_CAM_BIST_STATUSr} 35 36 #define HX5_IP_PARSER0_HME_STAGE_TCAM_ONLY_0 {hx5_ip_parser0_hme_stage_tcam_only_0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER0_HME_STAGE_CAM_BIST_CONFIG_0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER0_HME_STAGE_TCAM_BIST_STATUS_0r} 37 38 #define HX5_IFP_LOGICAL_TABLE_SELECT {hx5_ifp_logical_table_select_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUSr} 39 40 #define HX5_FLEX_RTAG7_HASH_TCAM_ONLY {hx5_flex_rtag7_hash_tcam_only_name, NO_MODE, NO_MODE_FIELD, FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_STATUSr} 41 42 #define HX5_EGR_ZONE_0_EDITOR_CONTROL_TCAM {hx5_egr_zone_0_editor_control_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_STATUSr} 43 44 #define HX5_TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM {hx5_tunnel_adapt_2_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_STATUSr} 45 46 #define HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_2 {hx5_ip_parser2_hme_stage_tcam_only_2_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_2r} 47 48 #define HX5_EXACT_MATCH_LOGICAL_TABLE_SELECT {hx5_exact_match_logical_table_select_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUSr} 49 50 #define HX5_FORWARDING_3_LOGICAL_TBL_SEL_TCAM {hx5_forwarding_3_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, FORWARDING_3_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_3_KEY_GEN_CAM_BIST_STATUSr} 51 52 #define HX5_CPU_COS_MAP {hx5_cpu_cos_map_name, NO_MODE, NO_MODE_FIELD, CPU_COS_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_CAM_BIST_STATUSr} 53 54 #define HX5_IP_PARSER1_MICE_TCAM_1 {hx5_ip_parser1_mice_tcam_1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_MICE_CAM_BIST_CONFIG_1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER1_MICE_TCAM_BIST_STATUS_1r} 55 56 #define HX5_EGR_PKT_FLOW_SELECT_TCAM {hx5_egr_pkt_flow_select_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_PKT_FLOW_SELECT_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, EGR_PKT_FLOW_SELECT_CAM_BIST_STATUSr} 57 58 #define HX5_MY_STATION_TCAM {hx5_my_station_tcam_name, NO_MODE, NO_MODE_FIELD, IVP_MY_STATION_TCAM_1_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, IVP_MY_STATION_TCAM_1_BIST_STATUSr} 59 60 #define HX5_IP_PARSER2_MICE_TCAM_0 {hx5_ip_parser2_mice_tcam_0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_MICE_CAM_BIST_CONFIG_0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER2_MICE_TCAM_BIST_STATUS_0r} 61 62 #define HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_4 {hx5_ip_parser1_hme_stage_tcam_only_4_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_4r} 63 64 #define HX5_EGR_ZONE_4_EDITOR_CONTROL_TCAM {hx5_egr_zone_4_editor_control_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_STATUSr} 65 66 #define HX5_FORWARDING_1_LOGICAL_TBL_SEL_TCAM {hx5_forwarding_1_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, FORWARDING_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, FORWARDING_1_KEY_GEN_CAM_BIST_STATUSr} 67 68 #define HX5_DST_COMPRESSION {hx5_dst_compression_name, NO_MODE, NO_MODE_FIELD, DST_COMPRESSION_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, DST_COMPRESSION_CAM_BIST_STATUSr} 69 70 #define HX5_VFP_TCAM {hx5_vfp_tcam_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUSr} 71 72 #define HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_2 {hx5_ip_parser1_hme_stage_tcam_only_2_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_2r} 73 74 #define HX5_L3_TUNNEL {hx5_l3_tunnel_name, NO_MODE, NO_MODE_FIELD, L3_TUNNEL_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, L3_TUNNEL_BIST_STATUSr} 75 76 #define HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_1 {hx5_ip_parser1_hme_stage_tcam_only_1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_1r} 77 78 #define HX5_VLAN_SUBNET {hx5_vlan_subnet_name, NO_MODE, NO_MODE_FIELD, VLAN_SUBNET_ONLY_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, VLAN_SUBNET_ONLY_BIST_STATUSr} 79 80 #define HX5_PKT_FLOW_SELECT_TCAM_0 {hx5_pkt_flow_select_tcam_0_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_0_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, PKT_FLOW_SELECT_TCAM_0_BIST_STATUSr} 81 82 #define HX5_TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM {hx5_tunnel_adapt_1_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr} 83 84 #define HX5_IFP_TCAM_POOL0 {hx5_ifp_tcam_pool0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUSr} 85 #define HX5_IFP_TCAM_POOL1 {hx5_ifp_tcam_pool1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUSr} 86 #define HX5_IFP_TCAM_POOL2 {hx5_ifp_tcam_pool2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUSr} 87 #define HX5_IFP_TCAM_POOL3 {hx5_ifp_tcam_pool3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL3_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL3_BIST_STATUSr} 88 89 #define HX5_EFP_TCAM_POOL0 {hx5_efp_tcam_pool0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUSr} 90 #define HX5_EFP_TCAM_POOL1 {hx5_efp_tcam_pool1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUSr} 91 #define HX5_EFP_TCAM_POOL2 {hx5_efp_tcam_pool2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUSr} 92 #define HX5_EFP_TCAM_POOL3 {hx5_efp_tcam_pool3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUSr} 93 94 #define HX5_TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM {hx5_tunnel_adapt_4_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_STATUSr} 95 96 #define HX5_EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM {hx5_egr_adapt_2_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ADAPT_2_KEY_GEN_CAM_BIST_STATUSr} 97 98 #define HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_0 {hx5_ip_parser2_hme_stage_tcam_only_0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_0r} 99 100 #define HX5_EGR_QOS_CTRL_TCAM {hx5_egr_qos_ctrl_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_QOS_CTRL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_QOS_CTRL_CAM_BIST_STATUSr} 101 102 #define HX5_IP_PARSER2_MICE_TCAM_1 {hx5_ip_parser2_mice_tcam_1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_MICE_CAM_BIST_CONFIG_1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER2_MICE_TCAM_BIST_STATUS_1r} 103 104 #define HX5_EGR_ZONE_3_EDITOR_CONTROL_TCAM {hx5_egr_zone_3_editor_control_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_STATUSr} 105 106 #define HX5_IP_PARSER1_MICE_TCAM_0 {hx5_ip_parser1_mice_tcam_0_name, NO_MODE, NO_MODE_FIELD, IP_PARSER1_MICE_CAM_BIST_CONFIG_0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 2, IP_PARSER1_MICE_TCAM_BIST_STATUS_0r} 107 108 #define HX5_L3_DEFIP {hx5_l3_defip_name, NO_MODE, NO_MODE_FIELD, L3_DEFIP_ONLY_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, L3_DEFIP_ONLY_CAM_BIST_STATUSr} 109 110 #define HX5_SRC_COMPRESSION {hx5_src_compression_name, NO_MODE, NO_MODE_FIELD, SRC_COMPRESSION_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, SRC_COMPRESSION_CAM_BIST_STATUSr} 111 112 #define HX5_EGR_ZONE_1_EDITOR_CONTROL_TCAM {hx5_egr_zone_1_editor_control_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_STATUSr} 113 114 #define HX5_EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM {hx5_egr_adapt_1_logical_tbl_sel_tcam_name, NO_MODE, NO_MODE_FIELD, EGR_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr} 115 116 #define HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_1 {hx5_ip_parser2_hme_stage_tcam_only_1_name, NO_MODE, NO_MODE_FIELD, IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_1r} 117 118 #define HX5_PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY {hx5_pkt_flow_select_tcam_2_entry_only_name, NO_MODE, NO_MODE_FIELD, PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_CONFIG_64r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_STATUSr} 119 #define HX5_TOTAL_CAMBIST_COUNT 59 120 #define HX5_DONE_BIT_MASK 0x00000001 121 #define HX5_BIST_SUCCESS_MASK 0x00000002 122 123 static char hx5_egr_zone_2_editor_control_tcam_name[] = "EGR_ZONE_2_EDITOR_CONTROL_TCAM"; 124 125 static char hx5_tunnel_adapt_3_logical_tbl_sel_tcam_name[] = "TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM"; 126 127 static char hx5_ip_parser2_hme_stage_tcam_only_3_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_3"; 128 129 static char hx5_phb_select_tcam_name[] = "PHB_SELECT_TCAM"; 130 131 static char hx5_forwarding_2_logical_tbl_sel_tcam_name[] = "FORWARDING_2_LOGICAL_TBL_SEL_TCAM"; 132 133 static char hx5_my_station_tcam_2_name[] = "MY_STATION_TCAM_2"; 134 135 static char hx5_egr_field_extraction_profile_2_tcam_name[] = "EGR_FIELD_EXTRACTION_PROFILE_2_TCAM"; 136 137 static char hx5_egr_field_extraction_profile_1_tcam_name[] = "EGR_FIELD_EXTRACTION_PROFILE_1_TCAM"; 138 139 static char hx5_l2_user_entry_name[] = "L2_USER_ENTRY"; 140 141 static char hx5_ip_parser1_hme_stage_tcam_only_3_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_3"; 142 143 static char hx5_pkt_flow_select_tcam_1_name[] = "PKT_FLOW_SELECT_TCAM_1"; 144 145 static char hx5_ip_parser2_hme_stage_tcam_only_4_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_4"; 146 147 static char hx5_ip_parser1_hme_stage_tcam_only_0_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_0"; 148 149 static char hx5_ip_multicast_tcam_name[] = "IP_MULTICAST_TCAM"; 150 151 static char hx5_ip_parser0_hme_stage_tcam_only_0_name[] = "IP_PARSER0_HME_STAGE_TCAM_ONLY_0"; 152 153 static char hx5_ifp_logical_table_select_name[] = "IFP_LOGICAL_TABLE_SELECT"; 154 155 static char hx5_flex_rtag7_hash_tcam_only_name[] = "FLEX_RTAG7_HASH_TCAM_ONLY"; 156 157 static char hx5_egr_zone_0_editor_control_tcam_name[] = "EGR_ZONE_0_EDITOR_CONTROL_TCAM"; 158 159 static char hx5_tunnel_adapt_2_logical_tbl_sel_tcam_name[] = "TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM"; 160 161 static char hx5_ip_parser2_hme_stage_tcam_only_2_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_2"; 162 163 static char hx5_exact_match_logical_table_select_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT"; 164 165 static char hx5_forwarding_3_logical_tbl_sel_tcam_name[] = "FORWARDING_3_LOGICAL_TBL_SEL_TCAM"; 166 167 static char hx5_cpu_cos_map_name[] = "CPU_COS_MAP"; 168 169 static char hx5_ip_parser1_mice_tcam_1_name[] = "IP_PARSER1_MICE_TCAM_1"; 170 171 static char hx5_egr_pkt_flow_select_tcam_name[] = "EGR_PKT_FLOW_SELECT_TCAM"; 172 173 static char hx5_my_station_tcam_name[] = "MY_STATION_TCAM"; 174 175 static char hx5_ip_parser2_mice_tcam_0_name[] = "IP_PARSER2_MICE_TCAM_0"; 176 177 static char hx5_ip_parser1_hme_stage_tcam_only_4_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_4"; 178 179 static char hx5_egr_zone_4_editor_control_tcam_name[] = "EGR_ZONE_4_EDITOR_CONTROL_TCAM"; 180 181 static char hx5_forwarding_1_logical_tbl_sel_tcam_name[] = "FORWARDING_1_LOGICAL_TBL_SEL_TCAM"; 182 183 static char hx5_dst_compression_name[] = "DST_COMPRESSION"; 184 185 static char hx5_vfp_tcam_name[] = "VFP_TCAM"; 186 187 static char hx5_ip_parser1_hme_stage_tcam_only_2_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_2"; 188 189 static char hx5_l3_tunnel_name[] = "L3_TUNNEL"; 190 191 static char hx5_ip_parser1_hme_stage_tcam_only_1_name[] = "IP_PARSER1_HME_STAGE_TCAM_ONLY_1"; 192 193 static char hx5_vlan_subnet_name[] = "VLAN_SUBNET"; 194 195 static char hx5_pkt_flow_select_tcam_0_name[] = "PKT_FLOW_SELECT_TCAM_0"; 196 197 static char hx5_tunnel_adapt_1_logical_tbl_sel_tcam_name[] = "TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM"; 198 199 static char hx5_ifp_tcam_pool0_name[] = "IFP_TCAM_POOL0"; 200 static char hx5_ifp_tcam_pool1_name[] = "IFP_TCAM_POOL1"; 201 static char hx5_ifp_tcam_pool2_name[] = "IFP_TCAM_POOL2"; 202 static char hx5_ifp_tcam_pool3_name[] = "IFP_TCAM_POOL3"; 203 204 static char hx5_efp_tcam_pool0_name[] = "EFP_TCAM_POOL0"; 205 static char hx5_efp_tcam_pool1_name[] = "EFP_TCAM_POOL1"; 206 static char hx5_efp_tcam_pool2_name[] = "EFP_TCAM_POOL2"; 207 static char hx5_efp_tcam_pool3_name[] = "EFP_TCAM_POOL3"; 208 209 static char hx5_tunnel_adapt_4_logical_tbl_sel_tcam_name[] = "TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM"; 210 211 static char hx5_egr_adapt_2_logical_tbl_sel_tcam_name[] = "EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM"; 212 213 static char hx5_ip_parser2_hme_stage_tcam_only_0_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_0"; 214 215 static char hx5_egr_qos_ctrl_tcam_name[] = "EGR_QOS_CTRL_TCAM"; 216 217 static char hx5_ip_parser2_mice_tcam_1_name[] = "IP_PARSER2_MICE_TCAM_1"; 218 219 static char hx5_egr_zone_3_editor_control_tcam_name[] = "EGR_ZONE_3_EDITOR_CONTROL_TCAM"; 220 221 static char hx5_ip_parser1_mice_tcam_0_name[] = "IP_PARSER1_MICE_TCAM_0"; 222 223 static char hx5_l3_defip_name[] = "L3_DEFIP"; 224 225 static char hx5_src_compression_name[] = "SRC_COMPRESSION"; 226 227 static char hx5_egr_zone_1_editor_control_tcam_name[] = "EGR_ZONE_1_EDITOR_CONTROL_TCAM"; 228 229 static char hx5_egr_adapt_1_logical_tbl_sel_tcam_name[] = "EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM"; 230 231 static char hx5_ip_parser2_hme_stage_tcam_only_1_name[] = "IP_PARSER2_HME_STAGE_TCAM_ONLY_1"; 232 233 static char hx5_pkt_flow_select_tcam_2_entry_only_name[] = "PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY"; 234 235 static cambist_t hx5_cambist_array[] = { 236 HX5_EGR_ZONE_2_EDITOR_CONTROL_TCAM, 237 HX5_TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM, 238 HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_3, 239 HX5_PHB_SELECT_TCAM, 240 HX5_FORWARDING_2_LOGICAL_TBL_SEL_TCAM, 241 HX5_MY_STATION_TCAM_2, 242 HX5_EGR_FIELD_EXTRACTION_PROFILE_2_TCAM, 243 HX5_EGR_FIELD_EXTRACTION_PROFILE_1_TCAM, 244 HX5_L2_USER_ENTRY, 245 HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_3, 246 HX5_PKT_FLOW_SELECT_TCAM_1, 247 HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_4, 248 HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_0, 249 HX5_IP_MULTICAST_TCAM, 250 HX5_IP_PARSER0_HME_STAGE_TCAM_ONLY_0, 251 HX5_IFP_LOGICAL_TABLE_SELECT, 252 HX5_FLEX_RTAG7_HASH_TCAM_ONLY, 253 HX5_EGR_ZONE_0_EDITOR_CONTROL_TCAM, 254 HX5_TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM, 255 HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_2, 256 HX5_EXACT_MATCH_LOGICAL_TABLE_SELECT, 257 HX5_FORWARDING_3_LOGICAL_TBL_SEL_TCAM, 258 HX5_CPU_COS_MAP, 259 HX5_IP_PARSER1_MICE_TCAM_1, 260 HX5_EGR_PKT_FLOW_SELECT_TCAM, 261 HX5_MY_STATION_TCAM, 262 HX5_IP_PARSER2_MICE_TCAM_0, 263 HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_4, 264 HX5_EGR_ZONE_4_EDITOR_CONTROL_TCAM, 265 HX5_FORWARDING_1_LOGICAL_TBL_SEL_TCAM, 266 HX5_DST_COMPRESSION, 267 HX5_VFP_TCAM, 268 HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_2, 269 HX5_L3_TUNNEL, 270 HX5_IP_PARSER1_HME_STAGE_TCAM_ONLY_1, 271 HX5_VLAN_SUBNET, 272 HX5_PKT_FLOW_SELECT_TCAM_0, 273 HX5_TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM, 274 HX5_IFP_TCAM_POOL0, 275 HX5_IFP_TCAM_POOL1, 276 HX5_IFP_TCAM_POOL2, 277 HX5_IFP_TCAM_POOL3, 278 HX5_EFP_TCAM_POOL0, 279 HX5_EFP_TCAM_POOL1, 280 HX5_EFP_TCAM_POOL2, 281 HX5_EFP_TCAM_POOL3, 282 HX5_TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM, 283 HX5_EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM, 284 HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_0, 285 HX5_EGR_QOS_CTRL_TCAM, 286 HX5_IP_PARSER2_MICE_TCAM_1, 287 HX5_EGR_ZONE_3_EDITOR_CONTROL_TCAM, 288 HX5_IP_PARSER1_MICE_TCAM_0, 289 HX5_L3_DEFIP, 290 HX5_SRC_COMPRESSION, 291 HX5_EGR_ZONE_1_EDITOR_CONTROL_TCAM, 292 HX5_EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM, 293 HX5_IP_PARSER2_HME_STAGE_TCAM_ONLY_1, 294 HX5_PKT_FLOW_SELECT_TCAM_2_ENTRY_ONLY 295 };