ecc_parity.c (82458B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * This test is intended to be used for in house SER testing. The test writes 8 * all SW accessible memories on chip and reads them back to check for flips. 9 * The assumption is that this test will be run at regular intervals in a loop 10 * that is part of a master soc script as per test requirements. The test 11 * provides information on the total memory tested, total number of flips and 12 * the logical coordinate of each flip. However it does not provide information 13 * about the physical coordinate of each flip. 14 * 15 * Configuration parameters passed from CLI: 16 * TestPat: Test Pattern used to fill the memories 17 * 0: All 0s 18 * 1: All 1s 19 * 2: Logical checker board 20 * 3: Logical inverse checker board 21 * RdWrMode: Whether the test writes or reads the memories 22 * 1: Test only writes all the memories under test 23 * 2: Test only reads back all memories under test and counts flips 24 */ 25 26 #include <shared/bsl.h> 27 #include <appl/diag/system.h> 28 #include <appl/diag/parse.h> 29 #include <soc/mem.h> 30 #include <soc/field.h> 31 #include <soc/chip.h> 32 #include "testlist.h" 33 34 extern int bcm_common_linkscan_enable_set(int, int); 35 36 #if defined(BCM_TOMAHAWK_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) 37 38 #define BIT_IN_UINT32 (sizeof(uint32)*8) 39 40 #define TH_ACC_TYPE_DUPLICATE 9 41 #define TH_ACC_TYPE_DATA_SPLIT 14 42 #define TH_ACC_TYPE_UNIQUE_PIPE0 0 43 #define TH_ACC_TYPE_UNIQUE_PIPE1 1 44 #define TH_ACC_TYPE_UNIQUE_PIPE2 2 45 #define TH_ACC_TYPE_UNIQUE_PIPE3 3 46 #define TH_ACC_TYPE_SINGLE 20 47 #define TH_ACC_TYPE_ADDR_SPLIT_DIST 10 48 #define TH_ACC_TYPE_ADDR_SPLIT_SPLIT 12 49 #define TH_NUM_UNIQUE_ACC_TYPES 4 50 #define TH_NUM_VALID_ACC_TYPES 9 51 #define TH_BASE_TYPE_IPORT 0 52 #define TH_BASE_TYPE_EPORT 1 53 #define TH_BASE_TYPE_IPIPE 2 54 #define TH_BASE_TYPE_EPIPE 3 55 #define TH_BASE_TYPE_CHIP 4 56 #define TH_BASE_TYPE_XPE 5 57 #define TH_BASE_TYPE_SLICE 6 58 #define TH_BASE_TYPE_LAYER 7 59 #define TH_NUM_VALID_BASE_TYPES 8 60 #define SBUS_V4_MMU_MEMIDX_MASK 0x0003ffff 61 #define TH_NUM_BASE_TYPE_BLOCKS 3 62 #define TH_MMU_ACC_TYPE_BOUNDARY 32768 63 #define INVALID_ACC_TYPE 999 64 65 /* 66 * Macro used by memory accessor functions to fix order 67 */ 68 #define FIX_MEM_ORDER_E(v,m) (((m)->flags & SOC_MEM_FLAG_BE) ? \ 69 BYTES2WORDS((m)->bytes)-1-(v) : \ 70 (v)) 71 /* 72 * Macro to generate a pseudo random number 73 */ 74 #define RNUM(x) (1664525L * (x) + 1013904223L) 75 76 typedef void (*get_valid_unique_acc_types_t) (int, soc_mem_t, uint32*); 77 78 typedef struct ecc_par_s { 79 char *mem_str; 80 soc_mem_t mem; 81 uint32 single_entry; 82 _soc_ser_test_t test_type; 83 uint32 total_memories_tested; 84 uint32 total_entries_tested; 85 uint32 test_fail; 86 uint32 num_acc_types; 87 uint32 num_unique_acc_types; 88 uint32 acc_type_duplicate; 89 uint32 acc_type_data_split; 90 uint32 acc_type_single; 91 uint32 acc_type_addr_split_dist; 92 uint32 acc_type_addr_split_split; 93 uint32 *acc_type_unique; 94 uint32 sbus_v4; 95 uint32 num_base_type_blocks; 96 get_valid_unique_acc_types_t get_valid_unique_acc_types; 97 uint32 memidx_mask; 98 uint32 **mask_array; 99 uint32 was_debug_mode; 100 } ecc_par_t; 101 102 static ecc_par_t *ecc_par_parray[SOC_MAX_NUM_DEVICES]; 103 104 /* The do_not_test_list array contains a list of memories not to be tested. This 105 includes memories that are updated continuously by hardware even this test is 106 ran immediately after "init soc". The 'rc.soc" is not executed as it starts 107 more software threads and keeps writing to more memories. The list also 108 includes overlays and aggregates that are missed in the soc_mem_info_t. */ 109 #ifdef BCM_TOMAHAWK2_SUPPORT 110 static soc_mem_t th2_do_not_test_list[] = { 111 SER_RESULT_EXPECTED_0m, 112 FPEM_ECCm, 113 REPLICATION_FIFO_BANK0m, 114 REPLICATION_FIFO_BANK0_XPE0m, 115 REPLICATION_FIFO_BANK0_XPE1m, 116 REPLICATION_FIFO_BANK0_XPE2m, 117 REPLICATION_FIFO_BANK0_XPE3m, 118 REPLICATION_FIFO_BANK1m, 119 REPLICATION_FIFO_BANK1_XPE0m, 120 REPLICATION_FIFO_BANK1_XPE1m, 121 REPLICATION_FIFO_BANK1_XPE2m, 122 REPLICATION_FIFO_BANK1_XPE3m, 123 MMU_INTFO_TC2PRI_MAPPINGm, 124 EGR_IP_TUNNEL_MPLSm, 125 EGR_IP_TUNNEL_IPV6m, 126 MODPORT_MAP_M1m, 127 MODPORT_MAP_M2m, 128 MODPORT_MAP_M3m, 129 IFP_LOGICAL_TABLE_SELECT_DATA_ONLYm, 130 IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE0m, 131 IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE1m, 132 IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE2m, 133 IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE3m, 134 TCB_THRESHOLD_PROFILE_MAP_XPE0m, 135 TCB_THRESHOLD_PROFILE_MAP_XPE1m, 136 TCB_THRESHOLD_PROFILE_MAP_XPE2m, 137 TCB_THRESHOLD_PROFILE_MAP_XPE3m 138 }; 139 #else 140 /* Dummy array to get through preco error for unsupported chips */ 141 static soc_mem_t th2_do_not_test_list[1]; 142 #endif /* BCM_TOMAHAWK2_SUPPORT */ 143 #ifdef BCM_TOMAHAWK_SUPPORT 144 static soc_mem_t th_do_not_test_list[] = { 145 EGR_VLAN_XLATE_ECCm, 146 L2_ENTRY_ONLY_ECCm, 147 L3_ENTRY_ONLY_ECCm, 148 MPLS_ENTRY_ECCm, 149 VLAN_XLATE_ECCm, 150 EGR_1588_SAm, 151 EGR_MAP_MHm, 152 EGR_PORTm, 153 EGR_PRI_CNG_MAPm, 154 EGR_VLANm, 155 EGR_VLAN_STGm, 156 ICONTROL_OPCODE_BITMAPm, 157 IFP_STORM_CONTROL_METERSm, 158 ING_SNAT_DATA_ONLYm, 159 IS_TDM_CALENDAR0m, 160 IS_TDM_CALENDAR1m, 161 L2_MOD_FIFOm, 162 L3_DEFIP_DATA_ONLYm, 163 L3_TUNNEL_DATA_ONLYm, 164 PORT_LAG_FAILOVER_SETm, 165 SER_RESULT_EXPECTED_1m, 166 SFLOW_ING_DATA_SOURCEm, 167 SFLOW_ING_FLEX_DATA_SOURCEm, 168 SRC_MODID_INGRESS_BLOCKm, 169 UNKNOWN_HGI_BITMAPm, 170 VLAN_TABm, 171 CENTRAL_CTR_EVICTION_FIFOm, 172 L3_DEFIP_PAIR_128_DATA_ONLYm, 173 MMU_CCP_MEM_XPE0m, 174 MMU_CCP_MEM_XPE1m, 175 MMU_CCP_MEM_XPE2m, 176 MMU_CCP_MEM_XPE3m, 177 MMU_CCP_RESEQ_MEM_XPE0_PIPE1m, 178 MMU_CCP_RESEQ_MEM_XPE1_PIPE2m, 179 MMU_CCP_RESEQ_MEM_XPE1_PIPE3m, 180 MMU_CCP_RESEQ_MEM_XPE2_PIPE1m, 181 MMU_CCP_RESEQ_MEM_XPE3_PIPE2m, 182 MMU_CCP_RESEQ_MEM_XPE3_PIPE3m, 183 MMU_CELL_LINK_XPE0m, 184 MMU_CELL_LINK_XPE1m, 185 MMU_CELL_LINK_XPE2m, 186 MMU_CELL_LINK_XPE3m, 187 MMU_CFAP_BANK0_XPE0m, 188 MMU_CFAP_BANK0_XPE1m, 189 MMU_CFAP_BANK0_XPE2m, 190 MMU_CFAP_BANK0_XPE3m, 191 MMU_CFAP_BANK10_XPE0m, 192 MMU_CFAP_BANK10_XPE1m, 193 MMU_CFAP_BANK10_XPE2m, 194 MMU_CFAP_BANK10_XPE3m, 195 MMU_CFAP_BANK11_XPE0m, 196 MMU_CFAP_BANK11_XPE1m, 197 MMU_CFAP_BANK11_XPE2m, 198 MMU_CFAP_BANK11_XPE3m, 199 MMU_CFAP_BANK12_XPE0m, 200 MMU_CFAP_BANK12_XPE1m, 201 MMU_CFAP_BANK12_XPE2m, 202 MMU_CFAP_BANK12_XPE3m, 203 MMU_CFAP_BANK13_XPE0m, 204 MMU_CFAP_BANK13_XPE1m, 205 MMU_CFAP_BANK13_XPE2m, 206 MMU_CFAP_BANK13_XPE3m, 207 MMU_CFAP_BANK14_XPE0m, 208 MMU_CFAP_BANK14_XPE1m, 209 MMU_CFAP_BANK14_XPE2m, 210 MMU_CFAP_BANK14_XPE3m, 211 MMU_CFAP_BANK1_XPE0m, 212 MMU_CFAP_BANK1_XPE1m, 213 MMU_CFAP_BANK1_XPE2m, 214 MMU_CFAP_BANK1_XPE3m, 215 MMU_CFAP_BANK2_XPE0m, 216 MMU_CFAP_BANK2_XPE1m, 217 MMU_CFAP_BANK2_XPE2m, 218 MMU_CFAP_BANK2_XPE3m, 219 MMU_CFAP_BANK3_XPE0m, 220 MMU_CFAP_BANK3_XPE1m, 221 MMU_CFAP_BANK3_XPE2m, 222 MMU_CFAP_BANK3_XPE3m, 223 MMU_CFAP_BANK4_XPE0m, 224 MMU_CFAP_BANK4_XPE1m, 225 MMU_CFAP_BANK4_XPE2m, 226 MMU_CFAP_BANK4_XPE3m, 227 MMU_CFAP_BANK5_XPE0m, 228 MMU_CFAP_BANK5_XPE1m, 229 MMU_CFAP_BANK5_XPE2m, 230 MMU_CFAP_BANK5_XPE3m, 231 MMU_CFAP_BANK6_XPE0m, 232 MMU_CFAP_BANK6_XPE1m, 233 MMU_CFAP_BANK6_XPE2m, 234 MMU_CFAP_BANK6_XPE3m, 235 MMU_CFAP_BANK7_XPE0m, 236 MMU_CFAP_BANK7_XPE1m, 237 MMU_CFAP_BANK7_XPE2m, 238 MMU_CFAP_BANK7_XPE3m, 239 MMU_CFAP_BANK8_XPE0m, 240 MMU_CFAP_BANK8_XPE1m, 241 MMU_CFAP_BANK8_XPE2m, 242 MMU_CFAP_BANK8_XPE3m, 243 MMU_CFAP_BANK9_XPE0m, 244 MMU_CFAP_BANK9_XPE1m, 245 MMU_CFAP_BANK9_XPE2m, 246 MMU_CFAP_BANK9_XPE3m, 247 MMU_CTR_COLOR_DROP_MEM_XPE0m, 248 MMU_CTR_COLOR_DROP_MEM_XPE1m, 249 MMU_CTR_COLOR_DROP_MEM_XPE2m, 250 MMU_CTR_COLOR_DROP_MEM_XPE3m, 251 MMU_CTR_ING_DROP_MEM_XPE0_PIPE0m, 252 MMU_CTR_ING_DROP_MEM_XPE0_PIPE3m, 253 MMU_CTR_ING_DROP_MEM_XPE1_PIPE0m, 254 MMU_CTR_ING_DROP_MEM_XPE1_PIPE3m, 255 MMU_CTR_ING_DROP_MEM_XPE2_PIPE1m, 256 MMU_CTR_ING_DROP_MEM_XPE2_PIPE2m, 257 MMU_CTR_ING_DROP_MEM_XPE3_PIPE1m, 258 MMU_CTR_ING_DROP_MEM_XPE3_PIPE2m, 259 MMU_CTR_MC_DROP_MEM_XPE0_PIPE1m, 260 MMU_CTR_MC_DROP_MEM_XPE1_PIPE2m, 261 MMU_CTR_MC_DROP_MEM_XPE1_PIPE3m, 262 MMU_CTR_MC_DROP_MEM_XPE2_PIPE1m, 263 MMU_CTR_MC_DROP_MEM_XPE3_PIPE2m, 264 MMU_CTR_MC_DROP_MEM_XPE3_PIPE3m, 265 MMU_CTR_UC_DROP_MEM_XPE0_PIPE1m, 266 MMU_CTR_UC_DROP_MEM_XPE1_PIPE2m, 267 MMU_CTR_UC_DROP_MEM_XPE1_PIPE3m, 268 MMU_CTR_UC_DROP_MEM_XPE2_PIPE1m, 269 MMU_CTR_UC_DROP_MEM_XPE3_PIPE2m, 270 MMU_CTR_UC_DROP_MEM_XPE3_PIPE3m, 271 MMU_CTR_WRED_DROP_MEM_XPE0_PIPE1m, 272 MMU_CTR_WRED_DROP_MEM_XPE1_PIPE2m, 273 MMU_CTR_WRED_DROP_MEM_XPE1_PIPE3m, 274 MMU_CTR_WRED_DROP_MEM_XPE2_PIPE1m, 275 MMU_CTR_WRED_DROP_MEM_XPE3_PIPE2m, 276 MMU_CTR_WRED_DROP_MEM_XPE3_PIPE3m, 277 MMU_ENQS_CT_FIFO_PIPE0m, 278 MMU_ENQS_CT_FIFO_PIPE1m, 279 MMU_ENQS_CT_FIFO_PIPE2m, 280 MMU_ENQS_CT_FIFO_PIPE3m, 281 MMU_ENQS_PBI_DB_SC0_PIPE1m, 282 MMU_ENQS_PBI_DB_SC0_PIPE2m, 283 MMU_ENQS_PBI_DB_SC0_PIPE3m, 284 MMU_ENQS_PBI_DB_SC1_PIPE1m, 285 MMU_ENQS_PBI_DB_SC1_PIPE2m, 286 MMU_ENQS_PBI_DB_SC1_PIPE3m, 287 MMU_ENQX_PIPEMEM_HI_XPE0_PIPE3m, 288 MMU_ENQX_PIPEMEM_HI_XPE1_PIPE3m, 289 MMU_ENQX_PIPEMEM_HI_XPE2_PIPE1m, 290 MMU_ENQX_PIPEMEM_HI_XPE2_PIPE2m, 291 MMU_ENQX_PIPEMEM_HI_XPE3_PIPE1m, 292 MMU_ENQX_PIPEMEM_HI_XPE3_PIPE2m, 293 MMU_ENQX_PIPEMEM_LO_XPE0_PIPE3m, 294 MMU_ENQX_PIPEMEM_LO_XPE1_PIPE3m, 295 MMU_ENQX_PIPEMEM_LO_XPE2_PIPE1m, 296 MMU_ENQX_PIPEMEM_LO_XPE2_PIPE2m, 297 MMU_ENQX_PIPEMEM_LO_XPE3_PIPE1m, 298 MMU_ENQX_PIPEMEM_LO_XPE3_PIPE2m, 299 MMU_MCFP_XPE0m, 300 MMU_MCFP_XPE1m, 301 MMU_MCFP_XPE2m, 302 MMU_MCFP_XPE3m, 303 MMU_MCQDB_X_A_XPE0m, 304 MMU_MCQDB_X_A_XPE1m, 305 MMU_MCQDB_X_A_XPE2m, 306 MMU_MCQDB_X_A_XPE3m, 307 MMU_MCQDB_X_B_XPE0m, 308 MMU_MCQDB_X_B_XPE1m, 309 MMU_MCQDB_X_B_XPE2m, 310 MMU_MCQDB_X_B_XPE3m, 311 MMU_MCQDB_Y_A_XPE0m, 312 MMU_MCQDB_Y_A_XPE1m, 313 MMU_MCQDB_Y_A_XPE2m, 314 MMU_MCQDB_Y_A_XPE3m, 315 MMU_MCQDB_Y_B_XPE0m, 316 MMU_MCQDB_Y_B_XPE1m, 317 MMU_MCQDB_Y_B_XPE2m, 318 MMU_MCQDB_Y_B_XPE3m, 319 MMU_MCQE_XPE0m, 320 MMU_MCQE_XPE1m, 321 MMU_MCQE_XPE2m, 322 MMU_MCQE_XPE3m, 323 MMU_MCQN_XPE0m, 324 MMU_MCQN_XPE1m, 325 MMU_MCQN_XPE2m, 326 MMU_MCQN_XPE3m, 327 MMU_MTRO_BUCKET_L0_MEM_PIPE0m, 328 MMU_MTRO_BUCKET_L0_MEM_PIPE1m, 329 MMU_MTRO_BUCKET_L0_MEM_PIPE2m, 330 MMU_MTRO_BUCKET_L0_MEM_PIPE3m, 331 MMU_MTRO_BUCKET_L1_MEM_PIPE0m, 332 MMU_MTRO_BUCKET_L1_MEM_PIPE1m, 333 MMU_MTRO_BUCKET_L1_MEM_PIPE2m, 334 MMU_MTRO_BUCKET_L1_MEM_PIPE3m, 335 MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE0m, 336 MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE1m, 337 MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE2m, 338 MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE3m, 339 MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE0m, 340 MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE1m, 341 MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE2m, 342 MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE3m, 343 MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE0m, 344 MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE1m, 345 MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE2m, 346 MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE3m, 347 MMU_MTRO_L0_MEM_PIPE0m, 348 MMU_MTRO_L0_MEM_PIPE1m, 349 MMU_MTRO_L0_MEM_PIPE2m, 350 MMU_MTRO_L0_MEM_PIPE3m, 351 MMU_MTRO_L1_MEM_PIPE0m, 352 MMU_MTRO_L1_MEM_PIPE1m, 353 MMU_MTRO_L1_MEM_PIPE2m, 354 MMU_MTRO_L1_MEM_PIPE3m, 355 MMU_PDB_X_XPE0m, 356 MMU_PDB_X_XPE1m, 357 MMU_PDB_X_XPE2m, 358 MMU_PDB_X_XPE3m, 359 MMU_PDB_Y_XPE0m, 360 MMU_PDB_Y_XPE1m, 361 MMU_PDB_Y_XPE2m, 362 MMU_PDB_Y_XPE3m, 363 MMU_PKTHDR_XPE0m, 364 MMU_PKTHDR_XPE1m, 365 MMU_PKTHDR_XPE2m, 366 MMU_PKTHDR_XPE3m, 367 MMU_PKT_LINK_XPE0m, 368 MMU_PKT_LINK_XPE1m, 369 MMU_PKT_LINK_XPE2m, 370 MMU_PKT_LINK_XPE3m, 371 MMU_PORTCNT_XPE0m, 372 MMU_PORTCNT_XPE1m, 373 MMU_PORTCNT_XPE2m, 374 MMU_PORTCNT_XPE3m, 375 MMU_REPL_GROUP_INFO_TBL_PIPE0m, 376 MMU_REPL_GROUP_INFO_TBL_PIPE1m, 377 MMU_REPL_GROUP_INFO_TBL_PIPE2m, 378 MMU_REPL_GROUP_INFO_TBL_PIPE3m, 379 MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC0m, 380 MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC1m, 381 MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC0m, 382 MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC1m, 383 MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC0m, 384 MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC1m, 385 MMU_REPL_HEAD_TBL_PIPE0m, 386 MMU_REPL_HEAD_TBL_PIPE1m, 387 MMU_REPL_HEAD_TBL_PIPE2m, 388 MMU_REPL_HEAD_TBL_PIPE3m, 389 MMU_REPL_LIST_TBL_PIPE0m, 390 MMU_REPL_LIST_TBL_PIPE1m, 391 MMU_REPL_LIST_TBL_PIPE2m, 392 MMU_REPL_LIST_TBL_PIPE3m, 393 MMU_REPL_STATE_TBL_PIPE0m, 394 MMU_REPL_STATE_TBL_PIPE1m, 395 MMU_REPL_STATE_TBL_PIPE2m, 396 MMU_REPL_STATE_TBL_PIPE3m, 397 MMU_THDM_DB_PORTSP_BST_XPE0_PIPE1m, 398 MMU_THDM_DB_PORTSP_BST_XPE1_PIPE2m, 399 MMU_THDM_DB_PORTSP_BST_XPE1_PIPE3m, 400 MMU_THDM_DB_PORTSP_BST_XPE2_PIPE1m, 401 MMU_THDM_DB_PORTSP_BST_XPE3_PIPE2m, 402 MMU_THDM_DB_PORTSP_BST_XPE3_PIPE3m, 403 MMU_THDM_DB_PORTSP_CONFIG_A_PIPE0m, 404 MMU_THDM_DB_PORTSP_CONFIG_A_PIPE1m, 405 MMU_THDM_DB_PORTSP_CONFIG_A_PIPE2m, 406 MMU_THDM_DB_PORTSP_CONFIG_A_PIPE3m, 407 MMU_THDM_DB_PORTSP_CONFIG_B_PIPE0m, 408 MMU_THDM_DB_PORTSP_CONFIG_B_PIPE1m, 409 MMU_THDM_DB_PORTSP_CONFIG_B_PIPE2m, 410 MMU_THDM_DB_PORTSP_CONFIG_B_PIPE3m, 411 MMU_THDM_DB_PORTSP_CONFIG_C_PIPE0m, 412 MMU_THDM_DB_PORTSP_CONFIG_C_PIPE1m, 413 MMU_THDM_DB_PORTSP_CONFIG_C_PIPE2m, 414 MMU_THDM_DB_PORTSP_CONFIG_C_PIPE3m, 415 MMU_THDM_DB_PORTSP_CONFIG_PIPE0m, 416 MMU_THDM_DB_PORTSP_CONFIG_PIPE1m, 417 MMU_THDM_DB_PORTSP_CONFIG_PIPE2m, 418 MMU_THDM_DB_PORTSP_CONFIG_PIPE3m, 419 MMU_THDM_DB_QUEUE_BST_XPE0_PIPE1m, 420 MMU_THDM_DB_QUEUE_BST_XPE1_PIPE2m, 421 MMU_THDM_DB_QUEUE_BST_XPE1_PIPE3m, 422 MMU_THDM_DB_QUEUE_BST_XPE2_PIPE1m, 423 MMU_THDM_DB_QUEUE_BST_XPE3_PIPE2m, 424 MMU_THDM_DB_QUEUE_BST_XPE3_PIPE3m, 425 MMU_THDM_DB_QUEUE_CONFIG_A_PIPE0m, 426 MMU_THDM_DB_QUEUE_CONFIG_A_PIPE1m, 427 MMU_THDM_DB_QUEUE_CONFIG_A_PIPE2m, 428 MMU_THDM_DB_QUEUE_CONFIG_A_PIPE3m, 429 MMU_THDM_DB_QUEUE_CONFIG_B_PIPE0m, 430 MMU_THDM_DB_QUEUE_CONFIG_B_PIPE1m, 431 MMU_THDM_DB_QUEUE_CONFIG_B_PIPE2m, 432 MMU_THDM_DB_QUEUE_CONFIG_B_PIPE3m, 433 MMU_THDM_DB_QUEUE_CONFIG_C_PIPE0m, 434 MMU_THDM_DB_QUEUE_CONFIG_C_PIPE1m, 435 MMU_THDM_DB_QUEUE_CONFIG_C_PIPE2m, 436 MMU_THDM_DB_QUEUE_CONFIG_C_PIPE3m, 437 MMU_THDM_DB_QUEUE_CONFIG_PIPE0m, 438 MMU_THDM_DB_QUEUE_CONFIG_PIPE1m, 439 MMU_THDM_DB_QUEUE_CONFIG_PIPE2m, 440 MMU_THDM_DB_QUEUE_CONFIG_PIPE3m, 441 MMU_THDM_DB_QUEUE_COUNT_XPE0_PIPE1m, 442 MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE2m, 443 MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE3m, 444 MMU_THDM_DB_QUEUE_COUNT_XPE2_PIPE1m, 445 MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE2m, 446 MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE3m, 447 MMU_THDM_DB_QUEUE_OFFSET_A_PIPE0m, 448 MMU_THDM_DB_QUEUE_OFFSET_A_PIPE1m, 449 MMU_THDM_DB_QUEUE_OFFSET_A_PIPE2m, 450 MMU_THDM_DB_QUEUE_OFFSET_A_PIPE3m, 451 MMU_THDM_DB_QUEUE_OFFSET_B_PIPE0m, 452 MMU_THDM_DB_QUEUE_OFFSET_B_PIPE1m, 453 MMU_THDM_DB_QUEUE_OFFSET_B_PIPE2m, 454 MMU_THDM_DB_QUEUE_OFFSET_B_PIPE3m, 455 MMU_THDM_DB_QUEUE_OFFSET_C_PIPE0m, 456 MMU_THDM_DB_QUEUE_OFFSET_C_PIPE1m, 457 MMU_THDM_DB_QUEUE_OFFSET_C_PIPE2m, 458 MMU_THDM_DB_QUEUE_OFFSET_C_PIPE3m, 459 MMU_THDM_DB_QUEUE_OFFSET_PIPE0m, 460 MMU_THDM_DB_QUEUE_OFFSET_PIPE1m, 461 MMU_THDM_DB_QUEUE_OFFSET_PIPE2m, 462 MMU_THDM_DB_QUEUE_OFFSET_PIPE3m, 463 MMU_THDM_DB_QUEUE_RESUME_XPE0_PIPE1m, 464 MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE2m, 465 MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE3m, 466 MMU_THDM_DB_QUEUE_RESUME_XPE2_PIPE1m, 467 MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE2m, 468 MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE3m, 469 MMU_THDM_MCQE_PORTSP_BST_XPE0_PIPE1m, 470 MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE2m, 471 MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE3m, 472 MMU_THDM_MCQE_PORTSP_BST_XPE2_PIPE1m, 473 MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE2m, 474 MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE3m, 475 MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE0m, 476 MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE1m, 477 MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE2m, 478 MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE3m, 479 MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE0m, 480 MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE1m, 481 MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE2m, 482 MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE3m, 483 MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE0m, 484 MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE1m, 485 MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE2m, 486 MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE3m, 487 MMU_THDM_MCQE_PORTSP_CONFIG_PIPE0m, 488 MMU_THDM_MCQE_PORTSP_CONFIG_PIPE1m, 489 MMU_THDM_MCQE_PORTSP_CONFIG_PIPE2m, 490 MMU_THDM_MCQE_PORTSP_CONFIG_PIPE3m, 491 MMU_THDM_MCQE_QUEUE_BST_XPE0_PIPE1m, 492 MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE2m, 493 MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE3m, 494 MMU_THDM_MCQE_QUEUE_BST_XPE2_PIPE1m, 495 MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE2m, 496 MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE3m, 497 MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE0m, 498 MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE1m, 499 MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE2m, 500 MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE3m, 501 MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE0m, 502 MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE1m, 503 MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE2m, 504 MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE3m, 505 MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE0m, 506 MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE1m, 507 MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE2m, 508 MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE3m, 509 MMU_THDM_MCQE_QUEUE_CONFIG_PIPE0m, 510 MMU_THDM_MCQE_QUEUE_CONFIG_PIPE1m, 511 MMU_THDM_MCQE_QUEUE_CONFIG_PIPE2m, 512 MMU_THDM_MCQE_QUEUE_CONFIG_PIPE3m, 513 MMU_THDM_MCQE_QUEUE_COUNT_XPE0_PIPE1m, 514 MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE2m, 515 MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE3m, 516 MMU_THDM_MCQE_QUEUE_COUNT_XPE2_PIPE1m, 517 MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE2m, 518 MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE3m, 519 MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE0m, 520 MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE1m, 521 MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE2m, 522 MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE3m, 523 MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE0m, 524 MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE1m, 525 MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE2m, 526 MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE3m, 527 MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE0m, 528 MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE1m, 529 MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE2m, 530 MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE3m, 531 MMU_THDM_MCQE_QUEUE_OFFSET_PIPE0m, 532 MMU_THDM_MCQE_QUEUE_OFFSET_PIPE1m, 533 MMU_THDM_MCQE_QUEUE_OFFSET_PIPE2m, 534 MMU_THDM_MCQE_QUEUE_OFFSET_PIPE3m, 535 MMU_THDM_MCQE_QUEUE_RESUME_XPE0_PIPE1m, 536 MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE2m, 537 MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE3m, 538 MMU_THDM_MCQE_QUEUE_RESUME_XPE2_PIPE1m, 539 MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE2m, 540 MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE3m, 541 MMU_THDU_BST_PORT_XPE0_PIPE1m, 542 MMU_THDU_BST_PORT_XPE1_PIPE2m, 543 MMU_THDU_BST_PORT_XPE1_PIPE3m, 544 MMU_THDU_BST_PORT_XPE2_PIPE1m, 545 MMU_THDU_BST_PORT_XPE3_PIPE2m, 546 MMU_THDU_BST_PORT_XPE3_PIPE3m, 547 MMU_THDU_BST_QGROUP_XPE0_PIPE1m, 548 MMU_THDU_BST_QGROUP_XPE1_PIPE2m, 549 MMU_THDU_BST_QGROUP_XPE1_PIPE3m, 550 MMU_THDU_BST_QGROUP_XPE2_PIPE1m, 551 MMU_THDU_BST_QGROUP_XPE3_PIPE2m, 552 MMU_THDU_BST_QGROUP_XPE3_PIPE3m, 553 MMU_THDU_BST_QUEUE_XPE0_PIPE1m, 554 MMU_THDU_BST_QUEUE_XPE1_PIPE2m, 555 MMU_THDU_BST_QUEUE_XPE1_PIPE3m, 556 MMU_THDU_BST_QUEUE_XPE2_PIPE1m, 557 MMU_THDU_BST_QUEUE_XPE3_PIPE2m, 558 MMU_THDU_BST_QUEUE_XPE3_PIPE3m, 559 MMU_THDU_CONFIG_PORT0_PIPE0m, 560 MMU_THDU_CONFIG_PORT0_PIPE1m, 561 MMU_THDU_CONFIG_PORT0_PIPE2m, 562 MMU_THDU_CONFIG_PORT0_PIPE3m, 563 MMU_THDU_CONFIG_PORT1_PIPE0m, 564 MMU_THDU_CONFIG_PORT1_PIPE1m, 565 MMU_THDU_CONFIG_PORT1_PIPE2m, 566 MMU_THDU_CONFIG_PORT1_PIPE3m, 567 MMU_THDU_CONFIG_PORT_PIPE0m, 568 MMU_THDU_CONFIG_PORT_PIPE1m, 569 MMU_THDU_CONFIG_PORT_PIPE2m, 570 MMU_THDU_CONFIG_PORT_PIPE3m, 571 MMU_THDU_CONFIG_QGROUP0_PIPE0m, 572 MMU_THDU_CONFIG_QGROUP0_PIPE1m, 573 MMU_THDU_CONFIG_QGROUP0_PIPE2m, 574 MMU_THDU_CONFIG_QGROUP0_PIPE3m, 575 MMU_THDU_CONFIG_QGROUP1_PIPE0m, 576 MMU_THDU_CONFIG_QGROUP1_PIPE1m, 577 MMU_THDU_CONFIG_QGROUP1_PIPE2m, 578 MMU_THDU_CONFIG_QGROUP1_PIPE3m, 579 MMU_THDU_CONFIG_QGROUP_PIPE0m, 580 MMU_THDU_CONFIG_QGROUP_PIPE1m, 581 MMU_THDU_CONFIG_QGROUP_PIPE2m, 582 MMU_THDU_CONFIG_QGROUP_PIPE3m, 583 MMU_THDU_CONFIG_QUEUE0_PIPE0m, 584 MMU_THDU_CONFIG_QUEUE0_PIPE1m, 585 MMU_THDU_CONFIG_QUEUE0_PIPE2m, 586 MMU_THDU_CONFIG_QUEUE0_PIPE3m, 587 MMU_THDU_CONFIG_QUEUE1_PIPE0m, 588 MMU_THDU_CONFIG_QUEUE1_PIPE1m, 589 MMU_THDU_CONFIG_QUEUE1_PIPE2m, 590 MMU_THDU_CONFIG_QUEUE1_PIPE3m, 591 MMU_THDU_CONFIG_QUEUE_PIPE0m, 592 MMU_THDU_CONFIG_QUEUE_PIPE1m, 593 MMU_THDU_CONFIG_QUEUE_PIPE2m, 594 MMU_THDU_CONFIG_QUEUE_PIPE3m, 595 MMU_THDU_COUNTER_PORT_XPE0_PIPE1m, 596 MMU_THDU_COUNTER_PORT_XPE1_PIPE2m, 597 MMU_THDU_COUNTER_PORT_XPE1_PIPE3m, 598 MMU_THDU_COUNTER_PORT_XPE2_PIPE1m, 599 MMU_THDU_COUNTER_PORT_XPE3_PIPE2m, 600 MMU_THDU_COUNTER_PORT_XPE3_PIPE3m, 601 MMU_THDU_COUNTER_QGROUP_XPE0_PIPE1m, 602 MMU_THDU_COUNTER_QGROUP_XPE1_PIPE2m, 603 MMU_THDU_COUNTER_QGROUP_XPE1_PIPE3m, 604 MMU_THDU_COUNTER_QGROUP_XPE2_PIPE1m, 605 MMU_THDU_COUNTER_QGROUP_XPE3_PIPE2m, 606 MMU_THDU_COUNTER_QGROUP_XPE3_PIPE3m, 607 MMU_THDU_COUNTER_QUEUE_XPE0_PIPE1m, 608 MMU_THDU_COUNTER_QUEUE_XPE1_PIPE2m, 609 MMU_THDU_COUNTER_QUEUE_XPE1_PIPE3m, 610 MMU_THDU_COUNTER_QUEUE_XPE2_PIPE1m, 611 MMU_THDU_COUNTER_QUEUE_XPE3_PIPE2m, 612 MMU_THDU_COUNTER_QUEUE_XPE3_PIPE3m, 613 MMU_THDU_OFFSET_QGROUP0_PIPE0m, 614 MMU_THDU_OFFSET_QGROUP0_PIPE1m, 615 MMU_THDU_OFFSET_QGROUP0_PIPE2m, 616 MMU_THDU_OFFSET_QGROUP0_PIPE3m, 617 MMU_THDU_OFFSET_QGROUP1_PIPE0m, 618 MMU_THDU_OFFSET_QGROUP1_PIPE1m, 619 MMU_THDU_OFFSET_QGROUP1_PIPE2m, 620 MMU_THDU_OFFSET_QGROUP1_PIPE3m, 621 MMU_THDU_OFFSET_QGROUP_PIPE0m, 622 MMU_THDU_OFFSET_QGROUP_PIPE1m, 623 MMU_THDU_OFFSET_QGROUP_PIPE2m, 624 MMU_THDU_OFFSET_QGROUP_PIPE3m, 625 MMU_THDU_OFFSET_QUEUE0_PIPE0m, 626 MMU_THDU_OFFSET_QUEUE0_PIPE1m, 627 MMU_THDU_OFFSET_QUEUE0_PIPE2m, 628 MMU_THDU_OFFSET_QUEUE0_PIPE3m, 629 MMU_THDU_OFFSET_QUEUE1_PIPE0m, 630 MMU_THDU_OFFSET_QUEUE1_PIPE1m, 631 MMU_THDU_OFFSET_QUEUE1_PIPE2m, 632 MMU_THDU_OFFSET_QUEUE1_PIPE3m, 633 MMU_THDU_OFFSET_QUEUE_PIPE0m, 634 MMU_THDU_OFFSET_QUEUE_PIPE1m, 635 MMU_THDU_OFFSET_QUEUE_PIPE2m, 636 MMU_THDU_OFFSET_QUEUE_PIPE3m, 637 MMU_THDU_Q_TO_QGRP_MAP0_PIPE0m, 638 MMU_THDU_Q_TO_QGRP_MAP0_PIPE1m, 639 MMU_THDU_Q_TO_QGRP_MAP0_PIPE2m, 640 MMU_THDU_Q_TO_QGRP_MAP0_PIPE3m, 641 MMU_THDU_Q_TO_QGRP_MAP1_PIPE0m, 642 MMU_THDU_Q_TO_QGRP_MAP1_PIPE1m, 643 MMU_THDU_Q_TO_QGRP_MAP1_PIPE2m, 644 MMU_THDU_Q_TO_QGRP_MAP1_PIPE3m, 645 MMU_THDU_Q_TO_QGRP_MAP2_PIPE0m, 646 MMU_THDU_Q_TO_QGRP_MAP2_PIPE1m, 647 MMU_THDU_Q_TO_QGRP_MAP2_PIPE2m, 648 MMU_THDU_Q_TO_QGRP_MAP2_PIPE3m, 649 MMU_THDU_Q_TO_QGRP_MAP_PIPE0m, 650 MMU_THDU_Q_TO_QGRP_MAP_PIPE1m, 651 MMU_THDU_Q_TO_QGRP_MAP_PIPE2m, 652 MMU_THDU_Q_TO_QGRP_MAP_PIPE3m, 653 MMU_THDU_RESUME_PORT0_PIPE0m, 654 MMU_THDU_RESUME_PORT0_PIPE1m, 655 MMU_THDU_RESUME_PORT0_PIPE2m, 656 MMU_THDU_RESUME_PORT0_PIPE3m, 657 MMU_THDU_RESUME_PORT1_PIPE0m, 658 MMU_THDU_RESUME_PORT1_PIPE1m, 659 MMU_THDU_RESUME_PORT1_PIPE2m, 660 MMU_THDU_RESUME_PORT1_PIPE3m, 661 MMU_THDU_RESUME_PORT2_PIPE0m, 662 MMU_THDU_RESUME_PORT2_PIPE1m, 663 MMU_THDU_RESUME_PORT2_PIPE2m, 664 MMU_THDU_RESUME_PORT2_PIPE3m, 665 MMU_THDU_RESUME_PORT_PIPE0m, 666 MMU_THDU_RESUME_PORT_PIPE1m, 667 MMU_THDU_RESUME_PORT_PIPE2m, 668 MMU_THDU_RESUME_PORT_PIPE3m, 669 MMU_THDU_RESUME_QGROUP_XPE0_PIPE1m, 670 MMU_THDU_RESUME_QGROUP_XPE1_PIPE2m, 671 MMU_THDU_RESUME_QGROUP_XPE1_PIPE3m, 672 MMU_THDU_RESUME_QGROUP_XPE2_PIPE1m, 673 MMU_THDU_RESUME_QGROUP_XPE3_PIPE2m, 674 MMU_THDU_RESUME_QGROUP_XPE3_PIPE3m, 675 MMU_THDU_RESUME_QUEUE_XPE0_PIPE1m, 676 MMU_THDU_RESUME_QUEUE_XPE1_PIPE2m, 677 MMU_THDU_RESUME_QUEUE_XPE1_PIPE3m, 678 MMU_THDU_RESUME_QUEUE_XPE2_PIPE1m, 679 MMU_THDU_RESUME_QUEUE_XPE3_PIPE2m, 680 MMU_THDU_RESUME_QUEUE_XPE3_PIPE3m, 681 MMU_UCQDB_X_XPE0m, 682 MMU_UCQDB_X_XPE1m, 683 MMU_UCQDB_X_XPE2m, 684 MMU_UCQDB_X_XPE3m, 685 MMU_UCQDB_Y_XPE0m, 686 MMU_UCQDB_Y_XPE1m, 687 MMU_UCQDB_Y_XPE2m, 688 MMU_UCQDB_Y_XPE3m, 689 MMU_WRED_AVG_QSIZE_XPE0_PIPE1m, 690 MMU_WRED_AVG_QSIZE_XPE1_PIPE2m, 691 MMU_WRED_AVG_QSIZE_XPE1_PIPE3m, 692 MMU_WRED_AVG_QSIZE_XPE2_PIPE1m, 693 MMU_WRED_AVG_QSIZE_XPE3_PIPE2m, 694 MMU_WRED_AVG_QSIZE_XPE3_PIPE3m, 695 MMU_WRED_CONFIG_XPE0_PIPE1m, 696 MMU_WRED_CONFIG_XPE1_PIPE2m, 697 MMU_WRED_CONFIG_XPE1_PIPE3m, 698 MMU_WRED_CONFIG_XPE2_PIPE1m, 699 MMU_WRED_CONFIG_XPE3_PIPE2m, 700 MMU_WRED_CONFIG_XPE3_PIPE3m, 701 MMU_WRED_PORT_SP_DROP_THD_MARK_XPE0_PIPE1m, 702 MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE2m, 703 MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE3m, 704 MMU_WRED_PORT_SP_DROP_THD_MARK_XPE2_PIPE1m, 705 MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE2m, 706 MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE3m, 707 MMU_WRED_PORT_SP_DROP_THD_XPE0_PIPE1m, 708 MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE2m, 709 MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE3m, 710 MMU_WRED_PORT_SP_DROP_THD_XPE2_PIPE1m, 711 MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE2m, 712 MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE3m, 713 MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1m, 714 MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE2m, 715 MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3m, 716 MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1m, 717 MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE2m, 718 MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3m, 719 MMU_WRED_UC_QUEUE_DROP_THD_0_XPE0_PIPE1m, 720 MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE2m, 721 MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE3m, 722 MMU_WRED_UC_QUEUE_DROP_THD_0_XPE2_PIPE1m, 723 MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE2m, 724 MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE3m, 725 MMU_WRED_UC_QUEUE_DROP_THD_1_XPE0_PIPE1m, 726 MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE2m, 727 MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE3m, 728 MMU_WRED_UC_QUEUE_DROP_THD_1_XPE2_PIPE1m, 729 MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE2m, 730 MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE3m, 731 MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE0_PIPE1m, 732 MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE2m, 733 MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE3m, 734 MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE2_PIPE1m, 735 MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE2m, 736 MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE3m, 737 MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE0_PIPE1m, 738 MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE2m, 739 MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE3m, 740 MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE2_PIPE1m, 741 MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE2m, 742 MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE3m, 743 MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE0_PIPE1m, 744 MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE2m, 745 MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE3m, 746 MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE2_PIPE1m, 747 MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE2m, 748 MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE3m, 749 Q_SCHED_L0_ACCUM_COMP_MEM_PIPE0m, 750 Q_SCHED_L0_ACCUM_COMP_MEM_PIPE1m, 751 Q_SCHED_L0_ACCUM_COMP_MEM_PIPE2m, 752 Q_SCHED_L0_ACCUM_COMP_MEM_PIPE3m, 753 Q_SCHED_L0_CREDIT_MEM_PIPE0m, 754 Q_SCHED_L0_CREDIT_MEM_PIPE1m, 755 Q_SCHED_L0_CREDIT_MEM_PIPE2m, 756 Q_SCHED_L0_CREDIT_MEM_PIPE3m, 757 Q_SCHED_L0_WEIGHT_MEM_PIPE0m, 758 Q_SCHED_L0_WEIGHT_MEM_PIPE1m, 759 Q_SCHED_L0_WEIGHT_MEM_PIPE2m, 760 Q_SCHED_L0_WEIGHT_MEM_PIPE3m, 761 Q_SCHED_L1_ACCUM_COMP_MEM_PIPE0m, 762 Q_SCHED_L1_ACCUM_COMP_MEM_PIPE1m, 763 Q_SCHED_L1_ACCUM_COMP_MEM_PIPE2m, 764 Q_SCHED_L1_ACCUM_COMP_MEM_PIPE3m, 765 Q_SCHED_L1_CREDIT_MEM_PIPE0m, 766 Q_SCHED_L1_CREDIT_MEM_PIPE1m, 767 Q_SCHED_L1_CREDIT_MEM_PIPE2m, 768 Q_SCHED_L1_CREDIT_MEM_PIPE3m, 769 Q_SCHED_L1_WEIGHT_MEM_PIPE0m, 770 Q_SCHED_L1_WEIGHT_MEM_PIPE1m, 771 Q_SCHED_L1_WEIGHT_MEM_PIPE2m, 772 Q_SCHED_L1_WEIGHT_MEM_PIPE3m, 773 Q_SCHED_L2_ACCUM_COMP_MEM_PIPE0m, 774 Q_SCHED_L2_ACCUM_COMP_MEM_PIPE1m, 775 Q_SCHED_L2_ACCUM_COMP_MEM_PIPE2m, 776 Q_SCHED_L2_ACCUM_COMP_MEM_PIPE3m, 777 Q_SCHED_L2_CREDIT_MEM_PIPE0m, 778 Q_SCHED_L2_CREDIT_MEM_PIPE1m, 779 Q_SCHED_L2_CREDIT_MEM_PIPE2m, 780 Q_SCHED_L2_CREDIT_MEM_PIPE3m, 781 REPLICATION_FIFO_BANK1_XPE0m, 782 REPLICATION_FIFO_BANK1_XPE1m, 783 REPLICATION_FIFO_BANK1_XPE2m, 784 REPLICATION_FIFO_BANK1_XPE3m, 785 RQE_FREE_LIST_XPE0m, 786 RQE_FREE_LIST_XPE1m, 787 RQE_FREE_LIST_XPE2m, 788 RQE_FREE_LIST_XPE3m, 789 RQE_LINK_LIST_XPE0m, 790 RQE_LINK_LIST_XPE1m, 791 RQE_LINK_LIST_XPE2m, 792 RQE_LINK_LIST_XPE3m, 793 STATS_INTF_QUEUE_LISTm, 794 TDM_CALENDAR0_PIPE0m, 795 TDM_CALENDAR0_PIPE1m, 796 TDM_CALENDAR0_PIPE2m, 797 TDM_CALENDAR0_PIPE3m, 798 TDM_CALENDAR1_PIPE0m, 799 TDM_CALENDAR1_PIPE1m, 800 TDM_CALENDAR1_PIPE2m, 801 TDM_CALENDAR1_PIPE3m, 802 THDI_PORT_PG_BST_XPE0_PIPE3m, 803 THDI_PORT_PG_BST_XPE1_PIPE3m, 804 THDI_PORT_PG_BST_XPE2_PIPE1m, 805 THDI_PORT_PG_BST_XPE2_PIPE2m, 806 THDI_PORT_PG_BST_XPE3_PIPE1m, 807 THDI_PORT_PG_BST_XPE3_PIPE2m, 808 THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE3m, 809 THDI_PORT_PG_CNTRS_RT1_XPE1_PIPE3m, 810 THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE1m, 811 THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE2m, 812 THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE1m, 813 THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE2m, 814 THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE3m, 815 THDI_PORT_PG_CNTRS_RT2_XPE1_PIPE3m, 816 THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE1m, 817 THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE2m, 818 THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE1m, 819 THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE2m, 820 THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE3m, 821 THDI_PORT_PG_CNTRS_SH1_XPE1_PIPE3m, 822 THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE1m, 823 THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE2m, 824 THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE1m, 825 THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE2m, 826 THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE3m, 827 THDI_PORT_PG_CNTRS_SH2_XPE1_PIPE3m, 828 THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE1m, 829 THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE2m, 830 THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE1m, 831 THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE2m, 832 THDI_PORT_PG_CONFIG_PIPE0m, 833 THDI_PORT_PG_CONFIG_PIPE1m, 834 THDI_PORT_PG_CONFIG_PIPE2m, 835 THDI_PORT_PG_CONFIG_PIPE3m, 836 THDI_PORT_SP_BST_XPE0_PIPE3m, 837 THDI_PORT_SP_BST_XPE1_PIPE3m, 838 THDI_PORT_SP_BST_XPE2_PIPE1m, 839 THDI_PORT_SP_BST_XPE2_PIPE2m, 840 THDI_PORT_SP_BST_XPE3_PIPE1m, 841 THDI_PORT_SP_BST_XPE3_PIPE2m, 842 THDI_PORT_SP_CNTRS_RT_XPE0_PIPE3m, 843 THDI_PORT_SP_CNTRS_RT_XPE1_PIPE3m, 844 THDI_PORT_SP_CNTRS_RT_XPE2_PIPE1m, 845 THDI_PORT_SP_CNTRS_RT_XPE2_PIPE2m, 846 THDI_PORT_SP_CNTRS_RT_XPE3_PIPE1m, 847 THDI_PORT_SP_CNTRS_RT_XPE3_PIPE2m, 848 THDI_PORT_SP_CNTRS_SH_XPE0_PIPE3m, 849 THDI_PORT_SP_CNTRS_SH_XPE1_PIPE3m, 850 THDI_PORT_SP_CNTRS_SH_XPE2_PIPE1m, 851 THDI_PORT_SP_CNTRS_SH_XPE2_PIPE2m, 852 THDI_PORT_SP_CNTRS_SH_XPE3_PIPE1m, 853 THDI_PORT_SP_CNTRS_SH_XPE3_PIPE2m, 854 THDI_PORT_SP_CONFIG0_PIPE0m, 855 THDI_PORT_SP_CONFIG0_PIPE1m, 856 THDI_PORT_SP_CONFIG0_PIPE2m, 857 THDI_PORT_SP_CONFIG0_PIPE3m, 858 THDI_PORT_SP_CONFIG1_PIPE0m, 859 THDI_PORT_SP_CONFIG1_PIPE1m, 860 THDI_PORT_SP_CONFIG1_PIPE2m, 861 THDI_PORT_SP_CONFIG1_PIPE3m, 862 THDI_PORT_SP_CONFIG2_PIPE0m, 863 THDI_PORT_SP_CONFIG2_PIPE1m, 864 THDI_PORT_SP_CONFIG2_PIPE2m, 865 THDI_PORT_SP_CONFIG2_PIPE3m, 866 THDI_PORT_SP_CONFIG_PIPE0m, 867 THDI_PORT_SP_CONFIG_PIPE1m, 868 THDI_PORT_SP_CONFIG_PIPE2m, 869 THDI_PORT_SP_CONFIG_PIPE3m 870 }; 871 #else 872 /* Dummy array to get through preco error for unsupported chips */ 873 static soc_mem_t th_do_not_test_list[1]; 874 #endif /* BCM_TOMAHAWK_SUPPORT */ 875 876 #ifdef BCM_TRIDENT2_SUPPORT 877 static soc_mem_t td2p_do_not_test_list[] = { 878 DLB_HGT_FLOWSETm, 879 DLB_HGT_FLOWSET_Xm, 880 DLB_HGT_FLOWSET_Ym, 881 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_Xm, 882 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_Ym, 883 DLB_HGT_GROUP_STATS_Xm, 884 DLB_HGT_GROUP_STATS_Ym, 885 DLB_HGT_OPTIMAL_CANDIDATE_Xm, 886 DLB_HGT_OPTIMAL_CANDIDATE_Ym, 887 EFP_COUNTER_TABLE_Xm, 888 EFP_COUNTER_TABLE_Ym, 889 EFP_METER_TABLE_Xm, 890 EFP_METER_TABLE_Ym, 891 EGR_FLEX_CTR_COUNTER_TABLE_0_Xm, 892 EGR_FLEX_CTR_COUNTER_TABLE_0_Ym, 893 EGR_FLEX_CTR_COUNTER_TABLE_1_Xm, 894 EGR_FLEX_CTR_COUNTER_TABLE_1_Ym, 895 EGR_FLEX_CTR_COUNTER_TABLE_2_Xm, 896 EGR_FLEX_CTR_COUNTER_TABLE_2_Ym, 897 EGR_FLEX_CTR_COUNTER_TABLE_3_Xm, 898 EGR_FLEX_CTR_COUNTER_TABLE_3_Ym, 899 EGR_FRAGMENT_ID_TABLE_Xm, 900 EGR_FRAGMENT_ID_TABLE_Ym, 901 EGR_IP_TUNNEL_IPV6m, 902 EGR_MMU_CREDIT_LIMIT_Xm, 903 EGR_MMU_CREDIT_LIMIT_Ym, 904 EGR_PERQ_XMT_COUNTERS_Xm, 905 EGR_PERQ_XMT_COUNTERS_Ym, 906 EGR_PW_INIT_COUNTERS_Xm, 907 EGR_PW_INIT_COUNTERS_Ym, 908 EGR_SER_FIFOm, 909 FP_COUNTER_TABLE_Xm, 910 FP_COUNTER_TABLE_Ym, 911 FP_GLOBAL_MASK_TCAMm, 912 FP_STORM_CONTROL_METERS_Xm, 913 FP_STORM_CONTROL_METERS_Ym, 914 IARB_MAIN_TDM_Xm, 915 IARB_MAIN_TDM_Ym, 916 ING_FLEX_CTR_COUNTER_TABLE_0_Xm, 917 ING_FLEX_CTR_COUNTER_TABLE_0_Ym, 918 ING_FLEX_CTR_COUNTER_TABLE_1_Xm, 919 ING_FLEX_CTR_COUNTER_TABLE_1_Ym, 920 ING_FLEX_CTR_COUNTER_TABLE_2_Xm, 921 ING_FLEX_CTR_COUNTER_TABLE_2_Ym, 922 ING_FLEX_CTR_COUNTER_TABLE_3_Xm, 923 ING_FLEX_CTR_COUNTER_TABLE_3_Ym, 924 ING_FLEX_CTR_COUNTER_TABLE_4_Xm, 925 ING_FLEX_CTR_COUNTER_TABLE_4_Ym, 926 ING_FLEX_CTR_COUNTER_TABLE_5_Xm, 927 ING_FLEX_CTR_COUNTER_TABLE_5_Ym, 928 ING_FLEX_CTR_COUNTER_TABLE_6_Xm, 929 ING_FLEX_CTR_COUNTER_TABLE_6_Ym, 930 ING_FLEX_CTR_COUNTER_TABLE_7_Xm, 931 ING_FLEX_CTR_COUNTER_TABLE_7_Ym, 932 ING_PW_TERM_SEQ_NUM_Xm, 933 ING_PW_TERM_SEQ_NUM_Ym, 934 ING_SERVICE_PRI_MAPm, 935 ING_SER_FIFOm, 936 ING_SNAT_HIT_ONLY_Xm, 937 ING_SNAT_HIT_ONLY_Ym, 938 L2_HITDA_ONLY_Xm, 939 L2_HITDA_ONLY_Ym, 940 L2_HITSA_ONLY_Xm, 941 L2_HITSA_ONLY_Ym, 942 L2_ENTRY_LPm, 943 L3_DEFIP_HIT_ONLY_Xm, 944 L3_DEFIP_HIT_ONLY_Ym, 945 L3_DEFIP_PAIR_128_HIT_ONLY_Xm, 946 L3_DEFIP_PAIR_128_HIT_ONLY_Ym, 947 L3_ENTRY_HIT_ONLYm, 948 L3_ENTRY_HIT_ONLY_Xm, 949 L3_ENTRY_HIT_ONLY_Ym, 950 L3_ENTRY_IPV4_MULTICASTm, 951 L3_ENTRY_IPV4_UNICASTm, 952 L3_ENTRY_IPV6_MULTICASTm, 953 L3_ENTRY_IPV6_UNICASTm, 954 L3_ENTRY_LPm, 955 LMEPm, 956 LMEP_DAm, 957 MAID_REDUCTIONm, 958 MA_INDEXm, 959 MA_STATEm, 960 MMU_CFAP_BANK0m, 961 MMU_CFAP_BANK1m, 962 MMU_CFAP_BANK2m, 963 MMU_CFAP_BANK3m, 964 MMU_CFAP_BANK4m, 965 MMU_CFAP_BANK5m, 966 MMU_CFAP_BANK6m, 967 MMU_CFAP_BANK7m, 968 MMU_CFAP_BANK8m, 969 MMU_CFAP_BANK9m, 970 MMU_CFAP_BANK10m, 971 MMU_CFAP_BANK11m, 972 MMU_CFAP_BANK12m, 973 MMU_CFAP_BANK13m, 974 MMU_CFAP_BANK14m, 975 MMU_CFAP_BANK15m, 976 MMU_CFAP_BANK16m, 977 MMU_CFAP_BANK17m, 978 MMU_CFAP_BANK18m, 979 MMU_CFAP_BANK19m, 980 MMU_CFAP_BANK20m, 981 MMU_INTFI_PFC_ST_TBLm, 982 OAM_LM_COUNTERSm, 983 RH_HGT_DROPS_Xm, 984 RH_HGT_DROPS_Ym, 985 RMEPm, 986 SER_MEMORYm, 987 XLPORT_WC_UCMEM_DATAm 988 }; 989 #else 990 /* Dummy array to get through preco error for unsupported chips */ 991 static soc_mem_t td2p_do_not_test_list[1]; 992 #endif /* BCM_TRIDENT2_SUPPORT */ 993 994 /* List of TCAMs to be covered. This list is maintained separately because a lot 995 of memories marked as CAMs are actually aggregates having both an SRAM and a 996 CAM. This list is generated by searching for names with --A flags from the 997 listmem command, duplicates like _[X|Y] and _PIPE[0-3] */ 998 #ifdef BCM_TOMAHAWK_SUPPORT 999 static soc_mem_t th_tcam_test_list[] = { 1000 L3_TUNNEL_ONLYm, 1001 FP_UDF_TCAMm, 1002 VLAN_SUBNET_ONLYm, 1003 VFP_TCAMm, 1004 MY_STATION_TCAM_ENTRY_ONLYm, 1005 IP_MULTICAST_TCAMm, 1006 L2_USER_ENTRY_ONLYm, 1007 L3_DEFIP_ONLYm, 1008 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLYm, 1009 DST_COMPRESSION_TCAM_ONLYm, 1010 SRC_COMPRESSION_TCAM_ONLYm, 1011 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLYm, 1012 IFP_TCAMm, 1013 ING_SNAT_ONLYm, 1014 CPU_COS_MAP_ONLYm, 1015 EFP_TCAMm 1016 }; 1017 #else 1018 /* Dummy array to get through preco error for unsupported chips */ 1019 static soc_mem_t th_tcam_test_list[1]; 1020 #endif /* BCM_TOMAHAWK_SUPPORT */ 1021 1022 #ifdef BCM_TRIDENT2_SUPPORT 1023 static soc_mem_t td2p_tcam_test_list[] = { 1024 CPU_COS_MAP_ONLYm, 1025 EFP_TCAMm, 1026 FP_GM_FIELDSm, 1027 FP_TCAMm, 1028 FP_UDF_TCAMm, 1029 ING_SNAT_ONLYm, 1030 IP_MULTICAST_TCAMm, 1031 L2_USER_ENTRY_ONLYm, 1032 L3_DEFIP_ONLYm, 1033 L3_TUNNEL_ONLYm, 1034 MY_STATION_TCAM_ENTRY_ONLYm, 1035 MY_STATION_TCAM_2_ENTRY_ONLYm, 1036 SUBPORT_TAG_SGPP_MAP_ONLYm, 1037 UDF_CONDITIONAL_CHECK_TABLE_CAMm, 1038 VFP_TCAMm, 1039 VLAN_SUBNET_ONLYm 1040 }; 1041 #else 1042 /* Dummy array to get through preco error for unsupported chips */ 1043 static soc_mem_t td2p_tcam_test_list[1]; 1044 #endif /* BCM_TRIDENT2_SUPPORT */ 1045 1046 static void 1047 th_get_valid_unique_acc_types(int unit, soc_mem_t mem, 1048 uint32 *unique_acc_types) 1049 { 1050 int block; 1051 int base_type; 1052 uint32 memidx; 1053 soc_mem_info_t *meminfo = &SOC_MEM_INFO(unit, mem); 1054 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1055 1056 memidx = meminfo->base & ecc_par_p->memidx_mask; 1057 1058 unique_acc_types[0] = ecc_par_p->acc_type_unique[0]; 1059 unique_acc_types[1] = ecc_par_p->acc_type_unique[1]; 1060 unique_acc_types[2] = ecc_par_p->acc_type_unique[2]; 1061 unique_acc_types[3] = ecc_par_p->acc_type_unique[3]; 1062 1063 base_type = SOC_MEM_BASE_TYPE(unit, mem); 1064 1065 SOC_MEM_BLOCK_ITER(unit, mem, block) { 1066 if (block == MMU_XPE_BLOCK(unit)) { 1067 switch (base_type) { 1068 case TH_BASE_TYPE_IPIPE : 1069 if ((memidx / 32768 == 0) 1070 || (memidx / 32768 == 3)) { 1071 unique_acc_types[2] = INVALID_ACC_TYPE; 1072 unique_acc_types[3] = INVALID_ACC_TYPE; 1073 } else { 1074 unique_acc_types[0] = INVALID_ACC_TYPE; 1075 unique_acc_types[1] = INVALID_ACC_TYPE; 1076 } 1077 break; 1078 case TH_BASE_TYPE_EPIPE : 1079 if ((memidx / 32768 == 0) 1080 || (memidx / 32768 == 1)) { 1081 unique_acc_types[1] = INVALID_ACC_TYPE; 1082 unique_acc_types[3] = INVALID_ACC_TYPE; 1083 } else { 1084 unique_acc_types[0] = INVALID_ACC_TYPE; 1085 unique_acc_types[2] = INVALID_ACC_TYPE; 1086 } 1087 break; 1088 case TH_BASE_TYPE_SLICE : 1089 if (memidx / 32768 == 0) { 1090 unique_acc_types[1] = INVALID_ACC_TYPE; 1091 unique_acc_types[3] = INVALID_ACC_TYPE; 1092 } else { 1093 unique_acc_types[0] = INVALID_ACC_TYPE; 1094 unique_acc_types[2] = INVALID_ACC_TYPE; 1095 } 1096 break; 1097 case TH_BASE_TYPE_LAYER : 1098 if (memidx / 32768 == 0) { 1099 unique_acc_types[2] = INVALID_ACC_TYPE; 1100 unique_acc_types[3] = INVALID_ACC_TYPE; 1101 } else { 1102 unique_acc_types[0] = INVALID_ACC_TYPE; 1103 unique_acc_types[1] = INVALID_ACC_TYPE; 1104 } 1105 break; 1106 default : 1107 unique_acc_types[0] = INVALID_ACC_TYPE; 1108 unique_acc_types[1] = INVALID_ACC_TYPE; 1109 unique_acc_types[2] = INVALID_ACC_TYPE; 1110 unique_acc_types[3] = INVALID_ACC_TYPE; 1111 break; 1112 } 1113 } else if (block == MMU_SC_BLOCK(unit)) { 1114 switch (base_type) { 1115 case TH_BASE_TYPE_IPIPE : 1116 case TH_BASE_TYPE_LAYER: 1117 unique_acc_types[2] = INVALID_ACC_TYPE; 1118 unique_acc_types[3] = INVALID_ACC_TYPE; 1119 break; 1120 default: 1121 unique_acc_types[0] = INVALID_ACC_TYPE; 1122 unique_acc_types[1] = INVALID_ACC_TYPE; 1123 unique_acc_types[2] = INVALID_ACC_TYPE; 1124 unique_acc_types[3] = INVALID_ACC_TYPE; 1125 break; 1126 } 1127 } 1128 } 1129 } 1130 1131 static void 1132 get_chip_specific_data(int unit) 1133 { 1134 uint16 dev_id; 1135 uint8 rev_id; 1136 1137 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1138 1139 soc_cm_get_id (unit, &dev_id, &rev_id); 1140 1141 cli_out("Device ID = 0x%04x, Rev ID = %0d\n", dev_id, rev_id); 1142 1143 if (dev_id == BCM56960_DEVICE_ID || dev_id == BCM56860_DEVICE_ID || 1144 dev_id == BCM56970_DEVICE_ID) { 1145 ecc_par_p->sbus_v4 = 1; 1146 ecc_par_p->memidx_mask = SBUS_V4_MMU_MEMIDX_MASK; 1147 ecc_par_p->num_unique_acc_types = TH_NUM_UNIQUE_ACC_TYPES; 1148 ecc_par_p->num_acc_types = TH_NUM_VALID_ACC_TYPES; 1149 ecc_par_p->acc_type_duplicate = TH_ACC_TYPE_DUPLICATE; 1150 ecc_par_p->acc_type_single = TH_ACC_TYPE_SINGLE; 1151 ecc_par_p->acc_type_data_split = TH_ACC_TYPE_DATA_SPLIT; 1152 ecc_par_p->acc_type_addr_split_dist = TH_ACC_TYPE_ADDR_SPLIT_DIST; 1153 ecc_par_p->acc_type_addr_split_split = TH_ACC_TYPE_ADDR_SPLIT_SPLIT; 1154 1155 ecc_par_p->acc_type_unique = (uint32*) 1156 sal_alloc(ecc_par_p->num_unique_acc_types * 1157 sizeof(uint32), 1158 "acc_type_unique"); 1159 ecc_par_p->acc_type_unique[0] = TH_ACC_TYPE_UNIQUE_PIPE0; 1160 ecc_par_p->acc_type_unique[1] = TH_ACC_TYPE_UNIQUE_PIPE1; 1161 ecc_par_p->acc_type_unique[2] = TH_ACC_TYPE_UNIQUE_PIPE2; 1162 ecc_par_p->acc_type_unique[3] = TH_ACC_TYPE_UNIQUE_PIPE3; 1163 1164 ecc_par_p->memidx_mask = SBUS_V4_MMU_MEMIDX_MASK; 1165 ecc_par_p->get_valid_unique_acc_types = &th_get_valid_unique_acc_types; 1166 1167 } else { 1168 cli_out("\nUnsupported chip"); 1169 ecc_par_p->test_fail = 1; 1170 } 1171 } 1172 1173 static int 1174 is_acc_type_unique(int unit, soc_mem_t mem) 1175 { 1176 int rv = SOC_E_NONE; 1177 int i; 1178 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1179 1180 for (i = 0; i < ecc_par_p->num_unique_acc_types; i++) { 1181 if (SOC_MEM_ACC_TYPE(unit, mem) == ecc_par_p->acc_type_unique[i]) { 1182 rv = 1; 1183 } 1184 } 1185 1186 return rv; 1187 } 1188 1189 1190 static int 1191 do_not_test(int unit, soc_mem_t mem) 1192 { 1193 int i; 1194 int rv = SOC_E_NONE; 1195 int num_do_not_test = 0; 1196 soc_mem_t dummy_list[] = {0}; 1197 soc_mem_t *do_not_test_list; 1198 1199 if (SOC_IS_TOMAHAWKX(unit)) { 1200 num_do_not_test = sizeof(th_do_not_test_list) / 1201 sizeof(th_do_not_test_list[0]); 1202 do_not_test_list = th_do_not_test_list; 1203 } else if (SOC_IS_TRIDENT2PLUS(unit)) { 1204 num_do_not_test = sizeof(td2p_do_not_test_list) / 1205 sizeof(td2p_do_not_test_list[0]); 1206 do_not_test_list = td2p_do_not_test_list; 1207 } else { 1208 do_not_test_list = dummy_list; 1209 } 1210 for (i = 0; i < num_do_not_test; i++) { 1211 if (mem == do_not_test_list[i]) { 1212 rv = 1; 1213 return rv; 1214 } 1215 } 1216 1217 if (SOC_IS_TOMAHAWK2(unit)) { 1218 num_do_not_test = sizeof(th2_do_not_test_list) / 1219 sizeof(th2_do_not_test_list[0]); 1220 do_not_test_list = th2_do_not_test_list; 1221 1222 for (i = 0; i < num_do_not_test; i++) { 1223 if (mem == do_not_test_list[i]) { 1224 rv = 1; 1225 return rv; 1226 } 1227 } 1228 } 1229 1230 return rv; 1231 } 1232 1233 static int 1234 test_tcam(int unit, soc_mem_t mem) { 1235 int i; 1236 int rv = SOC_E_NONE; 1237 int num_tcam_test = 0; 1238 soc_mem_t dummy_list[] = {0}; 1239 soc_mem_t *tcam_test_list; 1240 1241 if (SOC_IS_TOMAHAWKX(unit)) { 1242 num_tcam_test = sizeof(th_tcam_test_list) / 1243 sizeof(th_tcam_test_list[0]); 1244 tcam_test_list = th_tcam_test_list; 1245 } else if (SOC_IS_TRIDENT2PLUS(unit)) { 1246 num_tcam_test = sizeof(td2p_tcam_test_list) / 1247 sizeof(td2p_tcam_test_list[0]); 1248 tcam_test_list = td2p_tcam_test_list; 1249 } else { 1250 tcam_test_list = dummy_list; 1251 } 1252 for (i = 0; i < num_tcam_test; i++) { 1253 if (mem == tcam_test_list[i]) { 1254 rv = 1; 1255 } 1256 } 1257 return rv; 1258 } 1259 1260 static int 1261 parity_field_exists(int unit, soc_mem_t mem) { 1262 return (SOC_MEM_FIELD_VALID(unit, mem, PARITYf) || 1263 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITYf) || 1264 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_0f) || 1265 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_1f) || 1266 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_2f) || 1267 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_3f) || 1268 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_Af) || 1269 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_Bf) || 1270 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_LOWERf) || 1271 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_UPPERf) || 1272 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_P0f) || 1273 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_P1f) || 1274 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_P2f) || 1275 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PARITY_P3f) || 1276 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PBM_PARITY_P0f) || 1277 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PBM_PARITY_P1f) || 1278 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PBM_PARITY_P2f) || 1279 SOC_MEM_FIELD_VALID(unit, mem, EVEN_PBM_PARITY_P3f) || 1280 SOC_MEM_FIELD_VALID(unit, mem, EVEN_EGR_VLAN_STG_PARITY_P0f) || 1281 SOC_MEM_FIELD_VALID(unit, mem, EVEN_EGR_VLAN_STG_PARITY_P1f) || 1282 SOC_MEM_FIELD_VALID(unit, mem, EVEN_EGR_VLAN_STG_PARITY_P2f) || 1283 SOC_MEM_FIELD_VALID(unit, mem, EVEN_EGR_VLAN_STG_PARITY_P3f) || 1284 SOC_MEM_FIELD_VALID(unit, mem, PARITY0f) || 1285 SOC_MEM_FIELD_VALID(unit, mem, PARITY1f) || 1286 SOC_MEM_FIELD_VALID(unit, mem, PARITY2f) || 1287 SOC_MEM_FIELD_VALID(unit, mem, PARITY3f) || 1288 SOC_MEM_FIELD_VALID(unit, mem, PARITY_0f) || 1289 SOC_MEM_FIELD_VALID(unit, mem, PARITY_1f) || 1290 SOC_MEM_FIELD_VALID(unit, mem, PARITY_2f) || 1291 SOC_MEM_FIELD_VALID(unit, mem, PARITY_3f) || 1292 SOC_MEM_FIELD_VALID(unit, mem, PARITY_4f)); 1293 } 1294 1295 static int 1296 ecc_field_exists(int unit, soc_mem_t mem) { 1297 return (SOC_MEM_FIELD_VALID(unit, mem, ECCf) || 1298 SOC_MEM_FIELD_VALID(unit, mem, ECC_0f) || 1299 SOC_MEM_FIELD_VALID(unit, mem, ECC_1f) || 1300 SOC_MEM_FIELD_VALID(unit, mem, ECC_2f) || 1301 SOC_MEM_FIELD_VALID(unit, mem, ECC_3f) || 1302 SOC_MEM_FIELD_VALID(unit, mem, ECC_4f) || 1303 SOC_MEM_FIELD_VALID(unit, mem, ECCPf) || 1304 SOC_MEM_FIELD_VALID(unit, mem, ECCP0f) || 1305 SOC_MEM_FIELD_VALID(unit, mem, ECCP1f) || 1306 SOC_MEM_FIELD_VALID(unit, mem, ECCP2f) || 1307 SOC_MEM_FIELD_VALID(unit, mem, ECCP3f) || 1308 SOC_MEM_FIELD_VALID(unit, mem, ECCP4f) || 1309 SOC_MEM_FIELD_VALID(unit, mem, ECCP5f) || 1310 SOC_MEM_FIELD_VALID(unit, mem, ECCP6f) || 1311 SOC_MEM_FIELD_VALID(unit, mem, ECCP7f) || 1312 SOC_MEM_FIELD_VALID(unit, mem, ECCP_0f) || 1313 SOC_MEM_FIELD_VALID(unit, mem, ECCP_1f) || 1314 SOC_MEM_FIELD_VALID(unit, mem, ECCP_2f) || 1315 SOC_MEM_FIELD_VALID(unit, mem, ECCP_3f) || 1316 SOC_MEM_FIELD_VALID(unit, mem, ECCP_4f) || 1317 SOC_MEM_FIELD_VALID(unit, mem, ECC0f) || 1318 SOC_MEM_FIELD_VALID(unit, mem, ECC1f) || 1319 SOC_MEM_FIELD_VALID(unit, mem, ECC2f) || 1320 SOC_MEM_FIELD_VALID(unit, mem, ECC3f)); 1321 } 1322 1323 static int 1324 test_mem(int unit, soc_mem_t mem) 1325 { 1326 int rv = SOC_E_NONE; 1327 uint32 flags = 0; 1328 1329 if (SOC_MEM_IS_VALID(unit, mem)) { 1330 flags = SOC_MEM_INFO(unit, mem).flags; 1331 if ((!((flags & SOC_MEM_FLAG_AGGR) || (flags & SOC_MEM_FLAG_READONLY))) 1332 && (do_not_test(unit, mem) == 0)) { 1333 if (flags & SOC_MEM_FLAG_CAM) { 1334 if (test_tcam(unit, mem) == 1) { 1335 rv = 1; 1336 } 1337 } else { 1338 rv = 1; 1339 } 1340 } 1341 } 1342 return rv; 1343 } 1344 1345 static int 1346 duplicate_mem(int unit, soc_mem_t mem) { 1347 int i; 1348 int rv = SOC_E_NONE; 1349 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1350 soc_mem_info_t *meminfo = &SOC_MEM_INFO(unit, mem); 1351 1352 if ((test_mem(unit, mem) == 1) 1353 && (is_acc_type_unique(unit, mem) == 1)) { 1354 for (i = 0; i < NUM_SOC_MEM; i++) { 1355 if (test_mem(unit, i) == 1) { 1356 if (meminfo->base == SOC_MEM_INFO(unit, i).base) { 1357 if ((SOC_MEM_ACC_TYPE(unit, i) 1358 == ecc_par_p->acc_type_duplicate) 1359 || (SOC_MEM_ACC_TYPE(unit, i) 1360 == ecc_par_p->acc_type_data_split) 1361 ) { 1362 rv = 1; 1363 } 1364 } 1365 } 1366 } 1367 } 1368 return rv; 1369 } 1370 1371 1372 1373 static int 1374 do_unique_access(int unit, soc_mem_t mem) 1375 { 1376 int rv = SOC_E_NONE; 1377 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1378 1379 if ((SOC_MEM_ACC_TYPE(unit, mem) == ecc_par_p->acc_type_duplicate) && 1380 (SOC_MEM_UNIQUE_ACC(unit, mem) != NULL)) { 1381 rv = 1; 1382 } 1383 1384 return rv; 1385 } 1386 1387 static void 1388 ecc_par_parse_test_params(int unit, args_t *a) 1389 { 1390 int copyno; 1391 parse_table_t parse_table; 1392 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1393 1394 const char tr902_test_usage[] = 1395 #ifdef COMPILER_STRING_CONST_LIMIT 1396 "\nDocumentation too long to be displayed with -pedantic compiler\n"; 1397 #else 1398 "This test checks the parity and ECC based error detection and correction\n" 1399 "circuits. It fills memories with random values. It injects a single bit error\n" 1400 "for parity error detection and ECC error correction. For those memory with ECC\n" 1401 "protection, it injects a two bit error for ECC error detection. The test goes\n" 1402 "through one entry per memory by default. The user may use the following options\n" 1403 "to test one memory instead of all memories and to test all entries instead of\n" 1404 "one entry.\n" 1405 "\n" 1406 "Memory: Name of the memory to be tested; default is all\n" 1407 "Entry: Number of entry to be tested; default is one\n"; 1408 #endif 1409 1410 ecc_par_p->mem_str = sal_strdup("all"); 1411 ecc_par_p->single_entry = TRUE; 1412 1413 /*Parse CLI opts */ 1414 parse_table_init(unit, &parse_table); 1415 parse_table_add(&parse_table, "Memory", PQ_STRING | PQ_DFL, 1416 0, &(ecc_par_p->mem_str), NULL); 1417 parse_table_add(&parse_table, "SingleEntry", PQ_BOOL | PQ_DFL, 1418 0, &(ecc_par_p->single_entry), NULL); 1419 1420 if (ecc_par_p->single_entry) { 1421 ecc_par_p->test_type = SER_SINGLE_INDEX; 1422 } else { 1423 ecc_par_p->test_type = SER_ALL_INDEXES; 1424 } 1425 1426 if (parse_arg_eq(a, &parse_table) < 0 || ARG_CNT(a) != 0) { 1427 test_msg("%s", tr902_test_usage); 1428 test_error(unit, 1429 "%s: Invalid option: %s\n", 1430 ARG_CMD(a), 1431 ARG_CUR(a) ? ARG_CUR(a) : "*"); 1432 ecc_par_p->test_fail = 1; 1433 parse_arg_eq_done(&parse_table); 1434 } else { 1435 cli_out("-----------------\n"); 1436 cli_out(" TEST PARAMETERS \n"); 1437 cli_out("-----------------\n"); 1438 cli_out("Memory = %s\n", ecc_par_p->mem_str); 1439 cli_out("Entry = %s\n", ecc_par_p->single_entry ? "single" : "all"); 1440 cli_out("-----------------\n"); 1441 } 1442 1443 if ((sal_strstr(ecc_par_p->mem_str, "all") == NULL) && 1444 (parse_memory_name(unit, &ecc_par_p->mem, ecc_par_p->mem_str, ©no, 0) < 0)) { 1445 test_error(unit, "Memory \"%s\" is invalid\n", ecc_par_p->mem_str); 1446 ecc_par_p->test_fail = 1; 1447 } 1448 } 1449 1450 static void 1451 eccmask_get(int unit, soc_mem_t mem, uint32 *buf) 1452 { 1453 int f, b, start, end; 1454 soc_mem_info_t *memp; 1455 soc_field_info_t *fieldp; 1456 uint32 tmp; 1457 1458 memp = &SOC_MEM_INFO(unit, mem); 1459 sal_memset(buf, 0, sizeof(*buf) * BYTES2WORDS(memp->bytes)); 1460 1461 for (f = 0; f < memp->nFields; f++) { 1462 fieldp = &(memp->fields[f]); 1463 1464 if (fieldp->flags & SOCF_RES) { 1465 continue; 1466 } 1467 1468 if ((sal_strstr(SOC_FIELD_NAME(unit, fieldp->field), "ECC") != NULL) || 1469 (sal_strstr(SOC_FIELD_NAME(unit, fieldp->field), "PARITY") != NULL) || 1470 (sal_strstr(SOC_FIELD_NAME(unit, fieldp->field), "RESERVED") != NULL)) { 1471 continue; 1472 } 1473 1474 start = fieldp->bp; 1475 end = fieldp->bp + fieldp->len - 1; 1476 1477 for (b = start / 32; b <= end / 32; b++) { 1478 tmp = -1; 1479 1480 if (b == start / 32) { 1481 tmp &= -1 << (start % 32); 1482 } 1483 1484 if (b == end / 32) { 1485 tmp &= (1 << (end % 32) << 1) - 1; 1486 } 1487 1488 buf[FIX_MEM_ORDER_E(b, memp)] |= tmp; 1489 } 1490 } 1491 } 1492 1493 static void 1494 write_one_mem(int unit, soc_mem_t mem) 1495 { 1496 uint32 i, j; 1497 uint32 seed; 1498 uint32 *wr_data; 1499 uint32 entry_words; 1500 uint32 flags = SOC_MEM_DONT_USE_CACHE | SOC_MEM_DONT_CONVERT_XY2DM; 1501 uint32 meminfo_flags; 1502 soc_mem_info_t *meminfo = &SOC_MEM_INFO(unit, mem); 1503 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1504 1505 meminfo_flags = meminfo->flags; 1506 meminfo->flags &= (~SOC_MEM_FLAG_CAM); 1507 1508 for (i = soc_mem_index_min(unit, mem); 1509 i < (soc_mem_index_max(unit, mem) + 1); 1510 i++) { 1511 1512 entry_words = soc_mem_entry_words(unit, mem); 1513 wr_data = (uint32*)sal_alloc(entry_words * sizeof(uint32), "wr_data"); 1514 1515 for (j = 0; j < entry_words; j++) { 1516 seed = i * NUM_SOC_MEM + j; 1517 wr_data[j] = RNUM(seed) & ecc_par_p->mask_array[mem][j]; 1518 } 1519 1520 (void) soc_mem_write_extended(unit, flags, mem, COPYNO_ALL, i, wr_data); 1521 1522 sal_free(wr_data); 1523 if (ecc_par_p->single_entry == 1) break; 1524 } 1525 1526 meminfo->flags = meminfo_flags; 1527 } 1528 1529 static void 1530 write_all_mems(int unit) 1531 { 1532 int i; 1533 soc_mem_t mem; 1534 uint32 acc_type; 1535 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1536 1537 /*init soc*/ 1538 if (SOC_FAILURE(soc_reset_init(unit))) { 1539 cli_out("Error during soc reset. Aborting.\n"); 1540 ecc_par_p->test_fail = 1; 1541 } 1542 1543 /*init misc*/ 1544 if (SOC_FAILURE(soc_misc_init(unit))) { 1545 cli_out("Error during misc init. Aborting.\n"); 1546 ecc_par_p->test_fail = 1; 1547 } 1548 1549 /*init mmu*/ 1550 if (SOC_FAILURE(soc_mmu_init(unit))) { 1551 cli_out("Error during mmu init. Aborting.\n"); 1552 ecc_par_p->test_fail = 1; 1553 } 1554 1555 for (i = 0; i < NUM_SOC_MEM; i++) { 1556 if (sal_strstr(ecc_par_p->mem_str, "all") == NULL) 1557 mem = ecc_par_p->mem; 1558 else 1559 mem = (soc_mem_t)(i); 1560 1561 if (test_mem(unit, mem) == 1 && duplicate_mem(unit, mem) == 0 && 1562 (parity_field_exists(unit, mem) || ecc_field_exists(unit, mem))) { 1563 acc_type = SOC_MEM_ACC_TYPE(unit, mem); 1564 cli_out("Writing %s, acc_type = %0d, base = 0x%08x\n", 1565 SOC_MEM_NAME(unit, mem), acc_type, 1566 SOC_MEM_INFO(unit, mem).base); 1567 write_one_mem(unit, mem); 1568 } 1569 1570 if (sal_strstr(ecc_par_p->mem_str, "all") == NULL) break; 1571 } 1572 } 1573 1574 static void 1575 read_and_check_one_mem(int unit, soc_mem_t mem) 1576 { 1577 uint32 i, j, k; 1578 uint32 seed; 1579 uint32 *rd_data; 1580 uint32 exp_word; 1581 uint32 entry_words; 1582 uint32 flags = SOC_MEM_DONT_USE_CACHE | SOC_MEM_DONT_CONVERT_XY2DM; 1583 uint32 use_unique_access_types = 0; 1584 uint32 mask; 1585 uint32 eccmask[SOC_MAX_MEM_WORDS]; 1586 uint32 meminfo_flags; 1587 uint32 *valid_acc_types; 1588 soc_mem_info_t *meminfo = &SOC_MEM_INFO(unit, mem); 1589 int rv = SOC_E_NONE; 1590 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1591 1592 meminfo_flags = meminfo->flags; 1593 meminfo->flags &= (~SOC_MEM_FLAG_CAM); 1594 1595 use_unique_access_types = do_unique_access(unit, mem); 1596 entry_words = soc_mem_entry_words(unit, mem); 1597 1598 valid_acc_types = (uint32*) sal_alloc(ecc_par_p->num_unique_acc_types * 1599 sizeof(uint32), "acc_type_unique"); 1600 1601 ecc_par_p->get_valid_unique_acc_types(unit, mem, valid_acc_types); 1602 1603 for (i = 0; i < ecc_par_p->num_unique_acc_types; i++) { 1604 1605 if (use_unique_access_types == 0 && i > 0) { 1606 break; 1607 } else if (use_unique_access_types == 0 && i == 0) { 1608 cli_out("Reading and Checking %s\n", SOC_MEM_NAME(unit, mem)); 1609 } else { 1610 if (valid_acc_types[i] != INVALID_ACC_TYPE) { 1611 cli_out("Reading and Checking %s for acc_type %0d\n", 1612 SOC_MEM_NAME(unit, mem), valid_acc_types[i]); 1613 } else { 1614 continue; 1615 } 1616 } 1617 1618 eccmask_get(unit, mem, eccmask); 1619 for (j = soc_mem_index_min(unit, mem); 1620 j < (soc_mem_index_max(unit, mem) + 1); 1621 j++) { 1622 1623 rd_data = (uint32*)sal_alloc(entry_words * sizeof(uint32), 1624 "rd_data"); 1625 if (use_unique_access_types == 0) { 1626 rv = soc_mem_read_extended(unit, flags, mem, 0, 1627 COPYNO_ALL, j, rd_data); 1628 } else { 1629 rv = soc_mem_pipe_select_read(unit, flags, mem, COPYNO_ALL, 1630 valid_acc_types[i], j, rd_data); 1631 } 1632 if (SOC_FAILURE(rv)) { 1633 test_error(unit, "Memory %s read got NACK\n", 1634 SOC_MEM_NAME(unit, mem)); 1635 ecc_par_p->test_fail = 1; 1636 } 1637 1638 for (k = 0; k < entry_words; k++) { 1639 mask = ecc_par_p->mask_array[mem][k] & eccmask[k]; 1640 seed = j * NUM_SOC_MEM + k; 1641 exp_word = RNUM(seed); 1642 if ((rd_data[k] & mask) != (exp_word & mask)) { 1643 test_error(unit, "Memory %s, index %0d, word %0d, mismatched: exp_word = 0x%08x, rd_data = 0x%08x\n", 1644 SOC_MEM_NAME(unit, mem), j, k, exp_word, rd_data[k]); 1645 ecc_par_p->test_fail = 1; 1646 } 1647 } 1648 1649 rv = soc_ser_inject_support(unit, mem, 0); 1650 if ((rv == SOC_E_NONE) && (SOC_MEM_SER_CORRECTION_TYPE(unit, mem) != 0)) { 1651 SOC_MEM_TEST_SKIP_CACHE_SET(unit, 1); 1652 if (SOC_FAILURE(soc_mem_parity_control(unit, mem, COPYNO_ALL, FALSE))) { 1653 test_error(unit, "Could not disable parity warnings on memory %s\n", 1654 SOC_MEM_UFNAME(u, mem)); 1655 ecc_par_p->test_fail = 1; 1656 } 1657 1658 if (ecc_field_exists(unit, mem)) { 1659 flags |= SOC_INJECT_ERROR_2BIT_ECC; 1660 } 1661 1662 rv = soc_ser_inject_error(unit, flags, mem, 0, -1, j); 1663 if (SOC_FAILURE(rv)) { 1664 test_error(unit, "Failed to inject error to memory: %s\n", 1665 SOC_MEM_UFNAME(u, mem)); 1666 ecc_par_p->test_fail = 1; 1667 } 1668 1669 /* Read the memory entry with cache disabled, in order to induce the error */ 1670 flags |= SER_TEST_MEM_F_READ_FUNC_VIEW; 1671 if (use_unique_access_types == 0) { 1672 rv = soc_mem_read_extended(unit, flags, mem, 0, 1673 COPYNO_ALL, j, rd_data); 1674 } else { 1675 rv = soc_mem_pipe_select_read(unit, flags, mem, COPYNO_ALL, 1676 valid_acc_types[i], j, rd_data); 1677 } 1678 #ifdef BCM_TOMAHAWK_SUPPORT 1679 if (SOC_IS_TOMAHAWKX(unit)) { 1680 /* Following assumes that in TH, we have injected 2b error if mem 1681 * was ECC protected. 1682 * For ECC protected mems, if we inject only 1b error, and even if 1b 1683 * error reporting is enabled, then we will see ser event and 1684 * correction but will not get NACK on 1st read 1685 */ 1686 if (!SOC_FAILURE(rv) && valid_acc_types[i] == 0) { 1687 test_error(unit, "Did not receive NACK on 1st Read " 1688 "from memory %s index %d\n", 1689 SOC_MEM_UFNAME(unit, mem), j); 1690 ecc_par_p->test_fail = 1; 1691 } 1692 } 1693 #endif /* BCM_TOMAHAWK_SUPPORT */ 1694 1695 SOC_MEM_TEST_SKIP_CACHE_SET(unit, 0); 1696 if (SOC_FAILURE(soc_mem_parity_restore(unit, mem, COPYNO_ALL))) { 1697 test_error(unit, "Could not enable parity warnings on memory %s\n", 1698 SOC_MEM_UFNAME(unit, mem)); 1699 ecc_par_p->test_fail = 1; 1700 } 1701 1702 ecc_par_p->total_entries_tested++; 1703 } 1704 sal_free(rd_data); 1705 if (ecc_par_p->single_entry == 1) break; 1706 } 1707 } 1708 1709 ecc_par_p->total_memories_tested++; 1710 sal_free(valid_acc_types); 1711 meminfo->flags = meminfo_flags; 1712 } 1713 1714 static void 1715 read_and_check_all_mems(int unit) 1716 { 1717 int i; 1718 soc_mem_t mem; 1719 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1720 int force_read_through = SOC_MEM_FORCE_READ_THROUGH(unit); 1721 #ifdef INCLUDE_MEM_SCAN 1722 sal_usecs_t mem_scan_interval = 0; 1723 int mem_scan_rate = 0, mem_scan_running; 1724 #endif 1725 #ifdef BCM_SRAM_SCAN_SUPPORT 1726 sal_usecs_t sram_scan_interval = 0; 1727 int sram_scan_rate = 0, sram_scan_running; 1728 #endif 1729 1730 if (!force_read_through) { 1731 SOC_MEM_FORCE_READ_THROUGH_SET(unit, 1); 1732 } 1733 1734 #ifdef INCLUDE_MEM_SCAN 1735 mem_scan_running = soc_mem_scan_running (unit, &mem_scan_rate, 1736 &mem_scan_interval); 1737 if (mem_scan_running > 0) { 1738 if (soc_mem_scan_stop(unit)) { 1739 ecc_par_p->test_fail = 1; 1740 } 1741 } 1742 #endif 1743 #ifdef BCM_SRAM_SCAN_SUPPORT 1744 sram_scan_running = soc_sram_scan_running (unit, &sram_scan_rate, 1745 &sram_scan_interval); 1746 if (sram_scan_running > 0) { 1747 if (soc_sram_scan_stop(unit)) { 1748 ecc_par_p->test_fail = 1; 1749 } 1750 } 1751 #endif 1752 1753 for (i = 0; i < NUM_SOC_MEM; i++) { 1754 if (sal_strstr(ecc_par_p->mem_str, "all") == NULL) 1755 mem = ecc_par_p->mem; 1756 else 1757 mem = (soc_mem_t)(i); 1758 1759 if (test_mem(unit, mem) == 1 && duplicate_mem(unit, mem) == 0) { 1760 if (parity_field_exists(unit, mem) || ecc_field_exists(unit, mem)) { 1761 read_and_check_one_mem(unit, mem); 1762 } 1763 } 1764 if (sal_strstr(ecc_par_p->mem_str, "all") == NULL) break; 1765 } 1766 1767 if (!force_read_through) { 1768 SOC_MEM_FORCE_READ_THROUGH_SET(unit, 0); 1769 } 1770 1771 if (SOC_FAILURE(soc_reset_init(unit))) { 1772 cli_out("Error during soc reset. Aborting.\n"); 1773 ecc_par_p->test_fail = 1; 1774 } 1775 /*init misc*/ 1776 if (SOC_FAILURE(soc_misc_init(unit))) { 1777 cli_out("Error during misc init. Aborting.\n"); 1778 ecc_par_p->test_fail = 1; 1779 } 1780 #ifdef INCLUDE_MEM_SCAN 1781 if (mem_scan_running) { 1782 if (soc_mem_scan_start(unit, mem_scan_rate, mem_scan_interval)) { 1783 ecc_par_p->test_fail = 1; 1784 } 1785 } 1786 #endif 1787 #ifdef BCM_SRAM_SCAN_SUPPORT 1788 if (sram_scan_running) { 1789 if (soc_sram_scan_start(unit, sram_scan_rate, sram_scan_interval)) { 1790 ecc_par_p->test_fail = 1; 1791 } 1792 } 1793 #endif 1794 } 1795 1796 int 1797 ecc_par_test_init(int unit, args_t *a, void **pa) 1798 { 1799 int i, j; 1800 soc_mem_t mem; 1801 uint32 datamask[SOC_MAX_MEM_WORDS]; 1802 uint32 eccmask[SOC_MAX_MEM_WORDS]; 1803 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1804 1805 ecc_par_p = sal_alloc(sizeof(ecc_par_t), "ecc_par_test"); 1806 sal_memset(ecc_par_p, 0, sizeof(ecc_par_t)); 1807 ecc_par_parray[unit] = ecc_par_p; 1808 1809 ecc_par_p->test_fail = 0; 1810 ecc_par_p->total_memories_tested = 0; 1811 ecc_par_p->total_entries_tested = 0; 1812 1813 ecc_par_parse_test_params(unit, a); 1814 1815 ecc_par_p->mask_array = (uint32**)sal_alloc(NUM_SOC_MEM * sizeof(uint32*), 1816 "mask_array*"); 1817 1818 for (i = 0; i < NUM_SOC_MEM; i++) { 1819 ecc_par_p->mask_array[i] = (uint32*)sal_alloc(SOC_MAX_MEM_WORDS * 1820 sizeof(uint32), 1821 "mask_array"); 1822 } 1823 1824 for (i = 0; i < NUM_SOC_MEM; i++) { 1825 for (j = 0; j < SOC_MAX_MEM_WORDS; j++) { 1826 ecc_par_p->mask_array[i][j] = 0xffffffff; 1827 } 1828 } 1829 1830 for (i = 0; i < NUM_SOC_MEM; i++) { 1831 mem = (soc_mem_t)(i); 1832 1833 if (SOC_MEM_IS_VALID(unit, mem)) { 1834 soc_mem_datamask_get(unit, mem, datamask); 1835 eccmask_get(unit, mem, eccmask); 1836 for (j = 0; j < SOC_MAX_MEM_WORDS; j++) { 1837 ecc_par_p->mask_array[i][j] = datamask[j] & eccmask[j]; 1838 } 1839 } 1840 } 1841 1842 get_chip_specific_data(unit); 1843 1844 /** Turn off other Threads **/ 1845 bcm_common_linkscan_enable_set(unit,0); 1846 soc_counter_stop(unit); 1847 1848 if (ecc_par_p->test_fail == 1) { 1849 return BCM_E_FAIL; 1850 } else { 1851 return BCM_E_NONE; 1852 } 1853 } 1854 1855 int 1856 ecc_par_test(int unit, args_t *a, void *pa) 1857 { 1858 write_all_mems(unit); 1859 read_and_check_all_mems(unit); 1860 return 0; 1861 } 1862 1863 int 1864 ecc_par_test_cleanup(int unit, void *pa) 1865 { 1866 int i; 1867 ecc_par_t *ecc_par_p = ecc_par_parray[unit]; 1868 1869 cli_out("---------------------------\n"); 1870 if (ecc_par_p->test_fail == 1) 1871 cli_out(" TEST FAILED \n"); 1872 else 1873 cli_out(" TEST PASSED \n"); 1874 cli_out("---------------------------\n"); 1875 cli_out("Total memories tested = %0d\n", ecc_par_p->total_memories_tested); 1876 cli_out("Total entries tested = %0d\n", ecc_par_p->total_entries_tested); 1877 cli_out("---------------------------\n"); 1878 1879 for (i = 0; i < NUM_SOC_MEM; i++) { 1880 sal_free(ecc_par_p->mask_array[i]); 1881 } 1882 1883 sal_free(ecc_par_p->mask_array); 1884 1885 sal_free(ecc_par_p->acc_type_unique); 1886 sal_free(ecc_par_p); 1887 return 0; 1888 } 1889 1890 #endif /* BCM_TOMAHAWK_SUPPORT || BCM_TRIDENT2_SUPPORT */ 1891