cmicxtest.c (31519B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 8 /* 9 * cmicxtest.c 10 * 11 * cmicx test - simple test of the cmicx sim from the sdk. 12 */ 13 14 15 /* includes */ 16 /* #include "cmicx.h"*/ 17 #include <appl/diag/test.h> 18 #include <sal/appl/io.h> 19 #include <shared/bsl.h> 20 #include <appl/diag/system.h> 21 #include "testlist.h" 22 23 #include <soc/drv.h> 24 #include <soc/mem.h> 25 #include <soc/phyctrl.h> 26 27 #ifdef BCM_CMICX_SUPPORT 28 29 #include <../systems/sim/pcid/cmicx_sim.h> 30 31 32 /* defines */ 33 #ifdef PTRS_ARE_64BITS 34 #define CMICX_SIM_64_BIT 1 35 #else 36 #undef CMICX_SIM_64_BITS 37 #endif 38 39 40 /* schan command building function (from opcode, blockid/dport, etc.) */ 41 static void _cmic_schan_command_build(schan_command_opcode opcode,int dport, 42 int dlen,bool err,char ecode,bool dma,char bank,bool nack,reg_t *command) { 43 44 *command = 0; 45 REG_FIELD_SET_TO(*command,CMIC_SCHAN_COMMAND_OPCODE_MSB, CMIC_SCHAN_COMMAND_OPCODE_LSB, (int)opcode); 46 REG_FIELD_SET_TO(*command,CMIC_SCHAN_COMMAND_DPORT_MSB, CMIC_SCHAN_COMMAND_DPORT_LSB, dport); 47 REG_FIELD_SET_TO(*command,CMIC_SCHAN_COMMAND_DLEN_MSB, CMIC_SCHAN_COMMAND_DLEN_LSB, dlen); 48 REG_BIT_SET_TO( *command,CMIC_SCHAN_COMMAND_ERR_BIT, err); 49 REG_FIELD_SET_TO(*command,CMIC_SCHAN_COMMAND_ECODE_MSB, CMIC_SCHAN_COMMAND_ECODE_LSB, ecode); 50 REG_BIT_SET_TO( *command,CMIC_SCHAN_COMMAND_DMA_BIT, dma); 51 REG_FIELD_SET_TO(*command,CMIC_SCHAN_COMMAND_BANK_MSB, CMIC_SCHAN_COMMAND_BANK_LSB, bank); 52 REG_BIT_SET_TO( *command,CMIC_SCHAN_COMMAND_NACK_BIT, nack); 53 54 } 55 56 57 /* initialize the cmicx test */ 58 int cmicx_test_init(int u, args_t *a, void **pa) { 59 60 /* 61 soc_pci_write(unit, addr, data); 62 reg = soc_pci_read(unit, addr); 63 */ 64 65 sal_printf("CMICx Sim Test Init'd\n"); 66 67 return 0; 68 } 69 70 71 /* run the cmicx test */ 72 int cmicx_test_run(int u, args_t *a, void *pa) { 73 74 /* variables */ 75 reg_t schan_command = 0; 76 reg_t ctrl_data = 0; 77 reg_t req_data = 0; 78 reg_t status_data = 0; 79 reg_t descmem[CMIC_SBUS_DMA_WORDS_PER_DESCRIPTOR]; /* memory for descriptors */ 80 reg_t hostmem0[20]; /* memory for sbus acks */ 81 reg_t hostmem1[20]; /* memory for sbus acks */ 82 #define PACKET_DATA_BYTES 66 83 const int packet_data_bytes = PACKET_DATA_BYTES; 84 unsigned char packet_data[] = { 0xBA,0xD0,0xBE,0xEF,0x00,0x00,0x00,0x00, /* byte 8 here needs to be 0 to indicated the proper cos for the packet (0) in case of loopback. */ 85 0xBA,0xBE,0xFA,0xCE,0x01,0x23,0x45,0x67, 86 0x89,0xAB,0xCD,0xEF,0xDE,0xAD,0xFE,0xED, 87 0x01,0x23,0x45,0x67,0x89,0xAB,0xCD,0xEF, 88 0x00,0x00,0x00,0x00,0x00,0x11,0x11,0x00, 89 0x11,0x00,0x00,0x11,0x11,0x00,0x00,0x11, 90 0x00,0x11,0x11,0x00,0x00,0x00,0x00,0x00, 91 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 92 0xFF,0xFF,0x00,0x00,0x00,0x00 }; 93 unsigned char packet_data2[PACKET_DATA_BYTES + 4]; 94 int unit = 0; 95 int i; 96 97 /* zero our host memory to avoid problems */ 98 memset(descmem, 0, sizeof(descmem)); 99 memset(hostmem0, 0, sizeof(hostmem0)); 100 memset(hostmem1, 0, sizeof(hostmem1)); 101 memset(packet_data2, 0, sizeof(packet_data2)); 102 103 sal_printf("CMICx Sim Test Running...\n"); 104 105 106 /*******************************************************/ 107 /*** schan testing *************************************/ 108 /*******************************************************/ 109 110 /* feed some schan commands to the cmicx to test the schan. */ 111 /* build a command opcode first. format: _cmic_schan_command_build 112 * (schan_command_opcode opcode,int dport,int dlen,bool err,char ecode,bool dma,char bank,bool nack,reg_t *command) 113 */ 114 schan_command = 0; 115 _cmic_schan_command_build( SCHAN_MEM_RD,1,0, false,0,false,0,false, &schan_command ); 116 soc_pci_write( unit, CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN_REG_ADDR, 0x111111); /* set all schan weights on the sbus to 1 */ 117 soc_pci_write( unit, CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_ADDR, 0x111111); /* set all sbusdma weights on the sbus to 1 */ 118 soc_pci_write( unit, CMIC_TOP_SBUS_TIMEOUT_REG_ADDR, 0); 119 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_0_7_REG_ADDR, 0x70); /* block id 1 is configured to sbus id 7 */ 120 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_8_15_REG_ADDR, 0); 121 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_16_23_REG_ADDR, 0); 122 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_24_31_REG_ADDR, 0); 123 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_32_39_REG_ADDR, 0); 124 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_40_47_REG_ADDR, 0); 125 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_48_55_REG_ADDR, 0); 126 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_56_63_REG_ADDR, 0); 127 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_64_71_REG_ADDR, 0); 128 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_72_79_REG_ADDR, 0); 129 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_80_87_REG_ADDR, 0); 130 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_88_95_REG_ADDR, 0); 131 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_96_103_REG_ADDR, 0); 132 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_104_111_REG_ADDR, 0); 133 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_112_119_REG_ADDR, 0); 134 soc_pci_write( unit, CMIC_TOP_SBUS_RING_MAP_120_127_REG_ADDR, 0); 135 soc_pci_write( unit, CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE0_REG_ADDR, schan_command); 136 soc_pci_write( unit, CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE1_REG_ADDR, 0xABCD); 137 soc_pci_write( unit, CMIC_COMMON_POOL_SCHAN_CH0_CTRL_REG_ADDR, (reg_t)0x1); /* send a MSG_START */ 138 soc_pci_write( unit, CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT_REG_ADDR, 0); 139 soc_pci_write( unit, CMIC_COMMON_POOL_SCHAN_CH0_ERR_REG_ADDR, 0); 140 141 /* the simulation will be continually updated remotely. just read the schan control register to check the state of the schan access */ 142 ctrl_data = 0; 143 do { 144 ctrl_data = soc_pci_read(unit, CMIC_COMMON_POOL_SCHAN_CH0_CTRL_REG_ADDR); 145 } 146 while (REG_BIT_GET(ctrl_data,CMIC_SCHAN_CTRL_REG_MSG_DONE_BIT)==false); 147 148 /* at this point, we have schan completion, so read the ack data and clear the msg_done bit */ 149 /* expected output: 150 * 151 * [SIM] schan ack command read: 152 * 0x20080200 153 * 0x0000BEEF 154 */ 155 sal_printf("\nschan ack command read: "); 156 schan_command = soc_pci_read(unit, CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE0_REG_ADDR); 157 sal_printf("0x%08X\n",schan_command); 158 schan_command = soc_pci_read(unit, CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE1_REG_ADDR); 159 sal_printf("0x%08X\n\n",schan_command); 160 soc_pci_write( unit, CMIC_COMMON_POOL_SCHAN_CH0_CTRL_REG_ADDR, (reg_t)0); 161 162 163 /*******************************************************/ 164 /*** sbus dma register mode testing ********************/ 165 /*******************************************************/ 166 167 /* test the sbus dma with a simple case (register mode) */ 168 /* build the sbus command for the dma operation: _cmic_schan_command_build 169 * (schan_command_opcode opcode,int dport,int dlen,bool err,char ecode,bool dma,char bank,bool nack,reg_t *command) 170 * and then build the request register with the desired settings. */ 171 schan_command = 0; 172 req_data = 0; 173 _cmic_schan_command_build( SCHAN_MEM_RD,1,0, false,0,true,0,false, &schan_command ); 174 REG_BIT_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_DECR_BIT, false); 175 REG_BIT_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_REQ_SINGLE_BIT, false); 176 REG_BIT_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_INCR_NOADD_BIT, false); 177 REG_FIELD_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_MSB, CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_LSB, 2); /* a shift of 2 means an increment of 4. */ 178 REG_FIELD_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_MSB,CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_LSB, 4); 179 REG_BIT_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_DMA_WR_TO_NULLSPACE_BIT, false); 180 REG_BIT_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_WORDSWAP_IN_64BIT_SBUSDATA_BIT, false); 181 REG_BIT_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_MEMRD_ENDIANNESS_BIT, false); 182 REG_BIT_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_MEMWR_ENDIANNESS_BIT, false); 183 REG_FIELD_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_LSB, 0); 184 REG_FIELD_SET_TO( req_data, CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_LSB, 1); 185 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_TIMER_REG_ADDR, 0); /* disable "timer based mode" for the sbus dma */ 186 soc_pci_write( unit, CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_ADDR, 0x111111); /* set all sbusdma weights on the sbus to 1 */ 187 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_REQUEST_REG_ADDR, req_data); 188 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_COUNT_REG_ADDR, 2); 189 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_OPCODE_REG_ADDR, schan_command); 190 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS_REG_ADDR, 0xABCD); 191 #ifdef CMICX_SIM_64_BIT 192 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_REG_ADDR, (reg_t)( (uint64)hostmem0)); 193 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_REG_ADDR, (reg_t)(((uint64)hostmem0)>>32)); 194 #else 195 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_REG_ADDR, (reg_t)hostmem0); 196 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_REG_ADDR, (reg_t)0); 197 #endif 198 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO_REG_ADDR, 0x0); 199 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI_REG_ADDR, 0x0); 200 soc_pci_write( unit, CMIC_CMC0_SHARED_CONFIG_REG_ADDR, 0x0); 201 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_CONTROL_REG_ADDR, 0x1); /* start the sbus dma transaction */ 202 203 /* update the simulation and check for sbus dma completion */ 204 status_data = 0; 205 do { 206 status_data = soc_pci_read( unit, CMIC_CMC0_SBUSDMA_CH0_STATUS_REG_ADDR ); 207 } 208 while (REG_BIT_GET(status_data,CMIC_SBUSDMA_STATUS_REG_DONE_BIT)==false); /* wait until we get a done confirmation */ 209 210 /* at this point, we have simple sbus dma completion, so check the result (do a mem dump) */ 211 /* expected output: 212 * 213 * hostmem0+0: 0x0000BEEF 214 * hostmem0+4: 0x0000BEEF 215 */ 216 soc_pci_write( unit, CMICX_SIM_CONTROL_REG_ADDR, 0x1 ); 217 for (i=0; i<2; i++) { 218 #ifdef CMICX_SIM_64_BIT 219 sal_printf("0x%016lX: 0x%08X\n",(uint64)&(hostmem0[i]),hostmem0[i]); 220 #else 221 sal_printf("0x%08X: 0x%08X\n",(unsigned)&(hostmem0[i]),hostmem0[i]); 222 #endif 223 } 224 sal_printf("\n"); 225 226 227 /*******************************************************/ 228 /*** sbus dma descriptor mode testing ******************/ 229 /*******************************************************/ 230 231 /* test the sbus dma with a more complicated case (descriptor mode) */ 232 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_CONTROL_REG_ADDR, 0x0); /* clear the start bit (and in fact all bits) from the previous transaction */ 233 REG_BIT_SET_TO( descmem[0], CMIC_SBUSDMA_CONTROL_DESC_LAST_BIT, true); 234 REG_BIT_SET_TO( descmem[0], CMIC_SBUSDMA_CONTROL_DESC_SKIP_BIT, false); 235 REG_BIT_SET_TO( descmem[0], CMIC_SBUSDMA_CONTROL_DESC_JUMP_BIT, false); 236 REG_BIT_SET_TO( descmem[0], CMIC_SBUSDMA_CONTROL_DESC_APPEND_BIT, false); 237 REG_BIT_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_DECR_BIT, false); 238 REG_BIT_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_REQ_SINGLE_BIT, false); 239 REG_BIT_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_INCR_NOADD_BIT, false); 240 REG_FIELD_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_MSB, CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_LSB, 2); /* a shift of 2 means an increment of 4. */ 241 REG_FIELD_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_MSB,CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_LSB, 4); 242 REG_BIT_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_DMA_WR_TO_NULLSPACE_BIT, false); 243 REG_BIT_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_WORDSWAP_IN_64BIT_SBUSDATA_BIT, false); 244 REG_BIT_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_MEMRD_ENDIANNESS_BIT, false); 245 REG_BIT_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_MEMWR_ENDIANNESS_BIT, false); 246 REG_FIELD_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_LSB, 0); 247 REG_FIELD_SET_TO( descmem[1], CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_LSB, 1); 248 descmem[2] = 2; /* count = 2 */ 249 _cmic_schan_command_build( SCHAN_MEM_RD,1,0, false,0,true,0,false, &descmem[3] ); 250 descmem[4] = 0xABCD; /* sbus address */ 251 #ifdef CMICX_SIM_64_BIT 252 descmem[5] = (reg_t)( (uint64)hostmem1); /* hostmem address lo */ 253 descmem[6] = (reg_t)(((uint64)hostmem1)>>32); /* hostmem address hi */ 254 #else 255 descmem[5] = (reg_t)hostmem1; /* hostmem address lo */ 256 descmem[6] = (reg_t)0; /* hostmem address hi */ 257 #endif 258 descmem[7] = 0x0; /* unused */ 259 soc_pci_write( unit, CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_ADDR, 0x111111); /* set all sbusdma weights on the sbus to 1 */ 260 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_REQUEST_REG_ADDR, 0); 261 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_COUNT_REG_ADDR, 0); 262 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_OPCODE_REG_ADDR, 0); 263 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS_REG_ADDR, 0x0); 264 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_REG_ADDR, 0x0); 265 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_REG_ADDR, 0x0); 266 #ifdef CMICX_SIM_64_BIT 267 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO_REG_ADDR, (reg_t)( (uint64)descmem)); /* desc start adress is necessary to point to descriptor in host memory */ 268 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI_REG_ADDR, (reg_t)(((uint64)descmem)>>32)); /* desc start adress is necessary to point to descriptor in host memory */ 269 #else 270 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO_REG_ADDR, (reg_t)descmem); /* desc start adress is necessary to point to descriptor in host memory */ 271 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI_REG_ADDR, (reg_t)0); /* desc start adress is necessary to point to descriptor in host memory */ 272 #endif 273 soc_pci_write( unit, CMIC_CMC0_SHARED_CONFIG_REG_ADDR, 0x0); 274 soc_pci_write( unit, CMIC_CMC0_SBUSDMA_CH0_CONTROL_REG_ADDR, 0x5); /* start the sbus dma transaction - descriptor mode */ 275 276 /* update the simulation and check for sbus dma completion */ 277 do { 278 status_data = soc_pci_read( unit, CMIC_CMC0_SBUSDMA_CH0_STATUS_REG_ADDR ); 279 } 280 while (REG_BIT_GET(status_data,CMIC_SBUSDMA_STATUS_REG_DONE_BIT)==false); /* wait until we get a done confirmation */ 281 282 /* at this point, we have completion of the sbus dma operation, so print the memory out to see the results */ 283 /* expected output: 284 * 285 * hostmem1+0: 0x0000BEEF 286 * hostmem1+4: 0x0000BEEF 287 */ 288 soc_pci_write( unit, CMICX_SIM_CONTROL_REG_ADDR, 0x5 ); 289 for (i=0; i<2; i++) { 290 #ifdef CMICX_SIM_64_BIT 291 sal_printf("0x%016lX: 0x%08X\n",(uint64)&(hostmem1[i]),hostmem1[i]); 292 #else 293 sal_printf("0x%08X: 0x%08X\n",(unsigned)&(hostmem1[i]),hostmem1[i]); 294 #endif 295 } 296 sal_printf("\n"); 297 298 299 /*******************************************************/ 300 /*** test packet dma ***********************************/ 301 /*******************************************************/ 302 303 /* write to packet dma registers to start simple packet dma test case - transmit and then recieve a single packet in loop back. */ 304 /* the packet will be split in half and described with a continuous descriptor chain on both the rx and tx end. */ 305 ctrl_data = 0; 306 REG_BIT_SET_TO(ctrl_data,CMIC_TOP_CONFIG_REG_ENABLE_PIO_WRITE_NON_POSTED_BIT, false); 307 REG_BIT_SET_TO(ctrl_data,CMIC_TOP_CONFIG_REG_IP_2_EP_LOOPBACK_ENABLE_BIT, true); /* enable hardware packet loopback. */ 308 soc_pci_write( unit, CMIC_TOP_CONFIG_REG_ADDR, ctrl_data); 309 soc_pci_write( unit, CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS_REG_ADDR, 0x0); 310 soc_pci_write( unit, CMIC_CMC0_SHARED_IRQ_STAT0_REG_ADDR, 0x0); 311 soc_pci_write( unit, CMIC_CMC0_SHARED_IRQ_STAT_CLR0_REG_ADDR, 0x0); 312 for (i=0; i<CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR*2; i++) { 313 descmem[i] = 0; 314 } 315 #ifdef CMICX_SIM_64_BIT 316 descmem[0] = (reg_t)( (uint64)packet_data); /* location of the start of the packet */ 317 descmem[1] = (reg_t)(((uint64)packet_data)>>32); 318 #else 319 descmem[0] = (reg_t)packet_data; /* location of the start of the packet */ 320 descmem[1] = (reg_t)0; 321 #endif 322 REG_FIELD_SET_TO(descmem[2],CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_MSB,CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_LSB, 32); /* first descriptor points to 32 bytes of the packet. */ 323 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_CHAIN_BIT, true); 324 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_GATHER_BIT, true); 325 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_RELOAD_BIT, false); 326 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_HIGIG_PKT_BIT, false); 327 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_PURGE_PACKET_BIT, false); 328 REG_FIELD_SET_TO(descmem[2],CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_MSB,CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_LSB, 0); 329 REG_FIELD_SET_TO(descmem[2],CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_MSB,CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_LSB, 1); 330 #ifdef CMICX_SIM_64_BIT 331 descmem[4] = (reg_t)( (uint64)(packet_data+32)); /* the rest of the packet will follow after the first half of the packet, but we still need to tell the dma engine where it is */ 332 descmem[5] = (reg_t)(((uint64)(packet_data+32))>>32); 333 #else 334 descmem[4] = (reg_t)(packet_data+32); /* the rest of the packet will follow after the first half of the packet, but we still need to tell the dma engine where it is */ 335 descmem[5] = (reg_t)0; 336 #endif 337 REG_FIELD_SET_TO(descmem[6],CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_MSB,CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_LSB, (packet_data_bytes-32)); /* the remainder of the packet bytes will be pointed to by this desc. */ 338 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_CHAIN_BIT, false); 339 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_GATHER_BIT, false); 340 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_RELOAD_BIT, false); 341 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_HIGIG_PKT_BIT, false); 342 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_PURGE_PACKET_BIT, false); 343 REG_FIELD_SET_TO(descmem[6],CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_MSB,CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_LSB, 0); 344 REG_FIELD_SET_TO(descmem[6],CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_MSB,CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_LSB, 0); 345 #ifdef CMICX_SIM_64_BIT 346 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR, (reg_t)( (uint64)descmem)); 347 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR, (reg_t)(((uint64)descmem)>>32)); 348 #else 349 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR, (reg_t)descmem); 350 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR, (reg_t)0); 351 #endif 352 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO_REG_ADDR, 0x0); 353 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI_REG_ADDR, 0x0); 354 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0_REG_ADDR, 0x0); 355 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1_REG_ADDR, 0x0); 356 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_INTR_COAL_REG_ADDR, 0x0); 357 ctrl_data = 0x0; 358 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DIRECTION_BIT, true); /* tx transmission */ 359 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DMA_EN_BIT, true); /* start dma */ 360 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_ABORT_DMA_BIT, false); 361 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_PKTDMA_ENDIANNESS_BIT, false); 362 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DESC_ENDIANNESS_BIT, false); 363 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DROP_RX_PKT_ON_CHAIN_END_BIT, false); 364 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_RLD_STS_UPD_DIS_BIT, false); 365 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DESC_DONE_INTR_MODE_BIT, true); /* we expect interrupts on packet completion */ 366 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_ENABLE_CONTINUOUS_DMA_BIT, false); 367 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_CONTIGUOUS_DESCRIPTORS_BIT, false); 368 REG_FIELD_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_LSB, 0); 369 REG_FIELD_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_LSB, 0); 370 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_ENDIANNESS_BIT, false); 371 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_CTRL_REG_ADDR, ctrl_data); /* start the packet dma */ 372 373 /* check for packet dma completion on the tx */ 374 status_data = 0; 375 do { 376 status_data = soc_pci_read( unit, CMIC_CMC0_PKTDMA_CH0_STAT_REG_ADDR ); 377 } 378 while (REG_BIT_GET(status_data,CMIC_PKTDMA_STAT_REG_CHAIN_DONE_BIT)==false); 379 380 /* set up packet dma for rx of single packet over two descriptors. */ 381 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DMA_EN_BIT, false); /* clear the dma enable bit to set up for a new transfer. */ 382 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_CTRL_REG_ADDR, ctrl_data); 383 for (i=0; i<CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR*2; i++) { 384 descmem[i] = 0; 385 } 386 #ifdef CMICX_SIM_64_BIT 387 descmem[0] = (reg_t)( (uint64)packet_data2); /* location of the start of the packet */ 388 descmem[1] = (reg_t)(((uint64)packet_data2)>>32); 389 #else 390 descmem[0] = (reg_t)packet_data2; /* location of the start of the packet */ 391 descmem[1] = (reg_t)0; 392 #endif 393 REG_FIELD_SET_TO(descmem[2],CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_MSB,CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_LSB, 32); /* first descriptor accepts 32 bytes of the packet. */ 394 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_CHAIN_BIT, true); 395 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_SCATTER_BIT, true); 396 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_RELOAD_BIT, false); 397 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_HIGIG_PKT_BIT, false); 398 REG_BIT_SET_TO( descmem[2],CMIC_PKTDMA_DESC_DWORD2_PURGE_PACKET_BIT, false); 399 REG_FIELD_SET_TO(descmem[2],CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_MSB,CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_LSB, 0); 400 REG_FIELD_SET_TO(descmem[2],CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_MSB,CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_LSB, 1); 401 #ifdef CMICX_SIM_64_BIT 402 descmem[4] = (reg_t)( (uint64)(packet_data2+32)); /* the rest of the packet will follow after the first half of the packet, but we still need to tell the dma engine where it is */ 403 descmem[5] = (reg_t)(((uint64)(packet_data2+32))>>32); 404 #else 405 descmem[4] = (reg_t)(packet_data2+32); /* the rest of the packet will follow after the first half of the packet, but we still need to tell the dma engine where it is */ 406 descmem[5] = (reg_t)0; 407 #endif 408 REG_FIELD_SET_TO(descmem[6],CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_MSB,CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_LSB, (packet_data_bytes-32)); /* the remainder of the packet bytes will be pointed to by this desc. */ 409 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_CHAIN_BIT, false); 410 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_SCATTER_BIT, false); 411 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_RELOAD_BIT, false); 412 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_HIGIG_PKT_BIT, false); 413 REG_BIT_SET_TO( descmem[6],CMIC_PKTDMA_DESC_DWORD2_PURGE_PACKET_BIT, false); 414 REG_FIELD_SET_TO(descmem[6],CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_MSB,CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_LSB, 0); 415 REG_FIELD_SET_TO(descmem[6],CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_MSB,CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_LSB, 0); 416 #ifdef CMICX_SIM_64_BIT 417 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR, (reg_t)( (uint64)descmem)); 418 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR, (reg_t)(((uint64)descmem)>>32)); 419 #else 420 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR, (reg_t)descmem); 421 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR, (reg_t)0); 422 #endif 423 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO_REG_ADDR, 0x0); 424 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI_REG_ADDR, 0x0); 425 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0_REG_ADDR, 0x1); /* set up cos map to direct cos 0 to this channel. */ 426 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1_REG_ADDR, 0x0); 427 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_INTR_COAL_REG_ADDR, 0x0); 428 ctrl_data = 0x0; 429 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DIRECTION_BIT, false); /* rx transmission */ 430 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DMA_EN_BIT, true); /* start dma */ 431 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_ABORT_DMA_BIT, false); 432 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_PKTDMA_ENDIANNESS_BIT, false); 433 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DESC_ENDIANNESS_BIT, false); 434 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DROP_RX_PKT_ON_CHAIN_END_BIT, false); 435 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_RLD_STS_UPD_DIS_BIT, false); 436 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_DESC_DONE_INTR_MODE_BIT, true); /* we expect interrupts on packet completion */ 437 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_ENABLE_CONTINUOUS_DMA_BIT, false); 438 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_CONTIGUOUS_DESCRIPTORS_BIT, false); 439 REG_FIELD_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_LSB, 0); 440 REG_FIELD_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_LSB, 0); 441 REG_BIT_SET_TO(ctrl_data,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_ENDIANNESS_BIT, false); 442 soc_pci_write( unit, CMIC_CMC0_PKTDMA_CH0_CTRL_REG_ADDR, ctrl_data); /* start the packet dma */ 443 444 /* check for packet dma completion on the rx */ 445 status_data = 0; 446 do { 447 status_data = soc_pci_read( unit, CMIC_CMC0_PKTDMA_CH0_STAT_REG_ADDR ); 448 } 449 while (REG_BIT_GET(status_data,CMIC_PKTDMA_STAT_REG_CHAIN_DONE_BIT)==false); 450 451 /* print the packet 2 memory. should reveal the original packet, which was read through the packet dma rx mechanism. */ 452 /* expected output: 453 * 454 * BA D0 BE EF 00 00 00 00 455 * BA BE FA CE 01 23 45 67 456 * 89 AB CD EF DE AD FE ED 457 * 01 23 45 67 89 AB CD EF 458 * 00 00 00 00 00 11 11 00 459 * 11 00 00 11 11 00 00 11 460 * 00 11 11 00 00 00 00 00 461 * 00 00 00 00 00 00 00 00 462 * FF FF 463 */ 464 soc_pci_write( unit, CMICX_SIM_CONTROL_REG_ADDR, 0x1 ); 465 for (i=0; i<packet_data_bytes; i++) { 466 sal_printf("%02X ",(unsigned)packet_data2[i]); 467 if ((i%8)==7) { 468 sal_printf("\n"); 469 } 470 } 471 sal_printf("\n\n"); 472 473 474 sal_printf("CMICx Sim Test Done.\n"); 475 return 0; 476 } 477 478 479 /* end the cmicx test */ 480 int cmicx_test_done(int u, void *pa) { 481 482 sal_printf("CMICx Sim Test Done.\n"); 483 484 return 0; 485 } 486 487 #endif /* BCM_CMICX_SUPPORT */