cache_mem_test.c (43684B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 #ifdef _ERR_MSG_MODULE_NAME 8 #error "_ERR_MSG_MODULE_NAME redefined" 9 #endif 10 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_MEM 11 12 /* we need this junk function only to avoid building error of pedantic compilation */ 13 void ___junk_function_cache_mem_test(void){ 14 } 15 16 #if defined(BCM_ESW_SUPPORT) || defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) || defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT) 17 #include <shared/bsl.h> 18 #include <sal/types.h> 19 #include <sal/compiler.h> 20 #include <sal/core/libc.h> 21 #include <soc/defs.h> 22 #include <soc/mcm/memregs.h> 23 #include <soc/mem.h> 24 #include <soc/mcm/allenum.h> 25 26 #include <soc/shared/sat.h> 27 #include <appl/diag/system.h> 28 29 #ifdef BCM_PETRA_SUPPORT 30 #include <soc/dpp/drv.h> 31 #include <soc/dpp/ARAD/arad_tbl_access.h> 32 #include <bcm_int/dpp/counters.h> 33 #endif 34 35 #if defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT) 36 #include <soc/dnxc/legacy/dnxc_mem.h> 37 #endif 38 39 #ifdef BCM_SAND_SUPPORT 40 #include <soc/sand/sand_mem.h> 41 #endif 42 #ifdef BCM_DNX_SUPPORT 43 #include <bcm/error.h> 44 #endif 45 #include "cache_mem_test.h" 46 #include "testlist.h" 47 48 /* EXTERN Definitions */ 49 extern int bcm_common_linkscan_enable_set(int,int); 50 51 /* MACRO Definitions */ 52 #define SOC_MEM_ENTRY_LENGTH_MAX 120 53 /* FUNCTION Definitions */ 54 int cache_mem_test_read_and_compare(SOC_SAND_IN int unit, SOC_SAND_IN soc_mem_t mem, void* data); 55 uint32 cache_mem_test_generate_value(uint32 unit, soc_mem_t mem, uint32 array_index, uint32 index, cache_mem_test_write_value_pattern_t pattern); 56 void cache_mem_test_create_mask(SOC_SAND_IN uint32 unit,SOC_SAND_IN soc_mem_t mem, SOC_SAND_IN size_t mask_len, SOC_SAND_OUT uint32* mask); 57 void do_cache_mem_test_print_usage(void); 58 59 60 61 uint32 62 cache_mem_test_generate_value(uint32 unit, soc_mem_t mem, uint32 array_index, uint32 index, cache_mem_test_write_value_pattern_t pattern) 63 { 64 switch (pattern) 65 { 66 case cache_mem_test_write_value_pattern_all_ones: 67 return 0xFFFFFFFF; 68 case cache_mem_test_write_value_pattern_all_zeroes: 69 return 0; 70 case cache_mem_test_write_value_pattern_incremental: 71 return index; 72 case cache_mem_test_write_value_pattern_smart: 73 return (unit + mem + array_index + index); 74 } 75 return 0; 76 } 77 78 #ifdef BCM_SAND_SUPPORT 79 static int cache_mem_dynamic_check(uint32 unit,soc_mem_t mem) 80 { 81 switch (mem) 82 { 83 case KAPS_TCAM_HIT_INDICATIONm: 84 case OAMP_CLS_FLEX_CRC_TCAMm: 85 case OAMP_CLS_TRAP_CODE_TCAMm: 86 case OAMP_PE_0_PROG_TCAMm: 87 case OAMP_PE_1_PROG_TCAMm: 88 case OAMP_RSP_TCAMm: 89 case OAMP_RX_OAM_ID_TCAMm: 90 case EDB_EEDB_TOP_BANKm: 91 case EDB_EEDB_BANKm: 92 case PPDB_B_LIF_TABLEm: 93 case PPDB_B_LIF_TABLE_AC_2_EEIm: 94 case PPDB_B_LIF_TABLE_AC_2_OUT_LIFm: 95 case PPDB_B_LIF_TABLE_AC_MPm: 96 case PPDB_B_LIF_TABLE_IP_TTm: 97 case PPDB_B_LIF_TABLE_ISID_MPm: 98 case PPDB_B_LIF_TABLE_ISID_P2Pm: 99 case PPDB_B_LIF_TABLE_LABEL_PROTOCOL_OR_LSPm: 100 case PPDB_B_LIF_TABLE_LABEL_PWE_MPm: 101 case PPDB_B_LIF_TABLE_LABEL_PWE_P2Pm: 102 case PPDB_B_LIF_TABLE_TRILLm: 103 case KAPS_BUCKET_MEMORYm: 104 case KAPS_BUCKET_MAP_MEMORYm: 105 return 1; 106 } 107 return 0; 108 } 109 110 static int cache_mem_cache_check_skip(int unit, soc_mem_t mem) 111 { 112 int rc = 0; 113 if (SOC_IS_DNX(unit)) 114 { 115 switch (mem) 116 { 117 118 case MDB_ARM_MEM_0m: 119 120 case FSRD_FSRD_PROM_MEMm: 121 { 122 rc = 1; 123 break; 124 } 125 126 /* EEDB bank HW access bug at jer2 B0 */ 127 case MDB_EEDB_ENTRY_BANKm: 128 /* alias define bug at Jer2 B0 */ 129 case ETPPB_ENC_3_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEXm: 130 case ETPPB_ENC_3_PEMA_LOAD_SELECT_CHUNK_LITERARYm: 131 { 132 133 if (SOC_IS_JERICHO_2_B(unit)) 134 { 135 rc = 1; 136 break; 137 } 138 } 139 default: 140 { 141 break; 142 } 143 } 144 } 145 146 return rc; 147 } 148 149 150 int cache_memory_test_result_dump(int unit, tr_do_cache_mem_test_t* test_params) 151 { 152 soc_mem_t mem; 153 154 /* list skip memory */ 155 cli_out("Force skipped memory:\n"); 156 for (mem=0; mem<NUM_SOC_MEM; mem++) 157 { 158 if (test_params->mem_test_result_flag[mem] & CACHE_MEM_TEST_FORCE_SKIP_FLAG) 159 { 160 cli_out(" %-8d%s\n", mem, SOC_MEM_NAME(unit, mem)); 161 } 162 } 163 164 /* list read failure memory */ 165 cli_out("\nRead failure memory:\n"); 166 for (mem=0; mem<NUM_SOC_MEM; mem++) 167 { 168 if (test_params->mem_test_result_flag[mem] & CACHE_MEM_TEST_READ_FAILUE_FLAG) 169 { 170 cli_out(" %-8d%s\n", mem, SOC_MEM_NAME(unit, mem)); 171 } 172 } 173 174 /* list compare failure memory */ 175 cli_out("\nCompare failure memory:\n"); 176 for (mem=0; mem<NUM_SOC_MEM; mem++) 177 { 178 if (test_params->mem_test_result_flag[mem] & CACHE_MEM_TEST_COMPARE_FAILUE_FLAG) 179 { 180 cli_out(" %-8d%-50s", mem, SOC_MEM_NAME(unit, mem)); 181 if (SOC_MEM_FIELD_VALID(unit, mem, PARITYf)) 182 { 183 cli_out("PARITY\n"); 184 } 185 else if (SOC_MEM_FIELD_VALID(unit, mem, ECCf)) 186 { 187 cli_out("ECC\n"); 188 } 189 else 190 { 191 cli_out("\n"); 192 } 193 } 194 } 195 196 return SOC_E_NONE; 197 } 198 #endif 199 200 void cache_mem_test_create_mask( 201 SOC_SAND_IN uint32 unit, 202 SOC_SAND_IN soc_mem_t mem, 203 SOC_SAND_IN size_t mask_len, 204 SOC_SAND_OUT uint32 *mask) 205 { 206 int i; 207 uint32 entry_dw = soc_mem_entry_words(unit, mem); 208 soc_mem_info_t *meminfo; 209 sal_memset(mask, 0, mask_len); 210 211 meminfo = &SOC_MEM_INFO(unit, mem); 212 213 for ( i = 0; i < meminfo->nFields; i++) 214 { 215 /* Skip the Read-only/Write-Only/Signal/Reserved fields */ 216 if ((meminfo->fields[i].flags & SOCF_RO) || (meminfo->fields[i].flags & SOCF_WO) || (meminfo->fields[i].flags & SOCF_SIG) || (meminfo->fields[i].flags & SOCF_RES) ) 217 continue; 218 SHR_BITSET_RANGE(mask, meminfo->fields[i].bp, meminfo->fields[i].len); 219 } 220 221 /* Print the Mask */ 222 LOG_DEBUG(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: Mask for memory %d %s, nFields %d mask 0x"), 223 mem, SOC_MEM_NAME(unit, mem), meminfo->nFields)); 224 225 for ( i = entry_dw - 1; i >= 0; i--) 226 { 227 LOG_DEBUG(BSL_LS_APPL_TESTS, (BSL_META("%X"), mask[i])); 228 } 229 230 } 231 232 uint32 cache_mem_test_fill_values_soc_mem_write_callback(uint32 unit, soc_mem_t mem, uint32 i_array, tr_do_cache_mem_test_t *test_params) 233 { 234 uint32 start_index, end_index, index; 235 uint32 entry_index = 0; 236 uint32 write_value[SOC_MEM_ENTRY_LENGTH_MAX]; 237 uint32 mem_field_mask[SOC_MEM_ENTRY_LENGTH_MAX]; 238 uint32 entry_dw = soc_mem_entry_words(unit, mem); 239 soc_error_t rv = SOC_E_NONE; 240 soc_mem_t mem_orig = mem; 241 SOC_MEM_ALIAS_TO_ORIG(unit, mem_orig); 242 243 start_index = parse_memory_index(unit, mem, "min"); 244 end_index = parse_memory_index(unit, mem, "max"); 245 246 cache_mem_test_create_mask(unit, mem, sizeof(mem_field_mask), mem_field_mask); 247 248 LOG_INFO(BSL_LS_APPL_TESTS, 249 (BSL_META("CACHE_MEM_TEST: WRITE SOC: mem %d %s, num_of_entries %d, entry_dw %d\n"), 250 mem, SOC_MEM_NAME(unit, mem), end_index - start_index + 1/*table_size*/, entry_dw)); 251 252 for (index = start_index; index <= end_index; index++ ) 253 { 254 for (entry_index = 0; entry_index < entry_dw; entry_index++) 255 { 256 write_value[entry_index] = cache_mem_test_generate_value(unit, mem_orig, i_array, index, test_params->write_value_pattern) & mem_field_mask[entry_index]; 257 } 258 rv = soc_mem_array_write(unit, mem, i_array, MEM_BLOCK_ALL, index, write_value); 259 LOG_VERBOSE(BSL_LS_APPL_TESTS, 260 (BSL_META("CACHE_MEM_TEST: WRITE SOC: mem %d %s, array %d, index=%d, write_value=%08X %08X\n"), 261 mem, SOC_MEM_NAME(unit, mem), i_array, index, write_value[0], write_value[1])); 262 if (rv != SOC_E_NONE) 263 { 264 LOG_WARN(BSL_LS_APPL_TESTS, 265 (BSL_META("CACHE_MEM_TEST: WRITE SOC: mem %d %s, array %d, index %d failed\n"), 266 mem, SOC_MEM_NAME(unit, mem), i_array, index)); 267 break; 268 } 269 } 270 271 if (rv != SOC_E_NONE) 272 test_params->result |= rv; 273 274 return rv; 275 } 276 277 278 279 int cache_mem_test_fill_values_dma_callback( 280 SOC_SAND_IN int unit, 281 SOC_SAND_IN int copyno, 282 SOC_SAND_IN int array_index, 283 SOC_SAND_IN int index, 284 SOC_SAND_OUT uint32 *value, 285 SOC_SAND_IN int entry_sz, 286 SOC_SAND_IN void *opaque) 287 { 288 uint32 i = 0; 289 uint32 entry_size = entry_sz; 290 uint32 mem_field_mask[SOC_MEM_ENTRY_LENGTH_MAX]; 291 tr_do_cache_mem_test_t *test_params= ((tr_do_cache_mem_test_t *)opaque); 292 soc_mem_t mem = test_params->mem_id; 293 soc_mem_t mem_orig = mem; 294 SOC_MEM_ALIAS_TO_ORIG(unit, mem_orig); 295 *value = 0; 296 297 cache_mem_test_create_mask(unit, mem, sizeof(mem_field_mask), mem_field_mask); 298 299 for (i = 0; i < entry_size; i++) 300 { 301 value[i] = cache_mem_test_generate_value(unit, mem_orig, array_index, index, test_params->write_value_pattern) & mem_field_mask[i]; 302 LOG_DEBUG(BSL_LS_APPL_TESTS, 303 (BSL_META("CACHE_MEM_TEST: WRITE DMA: mem %d %s i %d value 0x%X mask 0x%X \n"), 304 mem, SOC_MEM_NAME(unit, mem), i, value[i], mem_field_mask[i])); 305 306 } 307 308 return SOC_E_NONE; 309 } 310 311 int 312 cache_mem_test_write_iter_callback(int unit, soc_mem_t mem, void* data) 313 { 314 uint32 rv = SOC_E_NONE; 315 uint32 start_array_index = 0, end_array_index = 0; 316 uint32 i_array; 317 tr_do_cache_mem_test_t *test_params = (tr_do_cache_mem_test_t *)data; 318 319 SOC_INIT_FUNC_DEFS; 320 321 test_params->stat_mem_total_cnt++; 322 323 #if defined(BCM_SAND_SUPPORT) 324 if ((SOC_IS_ARAD(unit)) || (SOC_IS_DNXF(unit)) || (SOC_IS_DNX(unit))) 325 { 326 if(!soc_mem_is_cachable(unit, mem)) 327 { 328 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: WRITE: non-cachable memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 329 test_params->stat_mem_not_tested_cnt++; 330 SOC_EXIT; 331 } 332 } 333 #endif 334 335 if (SOC_MEM_IS_ARRAY(unit,mem)) 336 { 337 start_array_index = parse_memory_array_index(unit, mem, "min"); 338 end_array_index = parse_memory_array_index(unit, mem, "max"); 339 } 340 341 /*The following statement will be removed after SDK-91354 will be fixed.*/ 342 if (mem == EDB_LINK_LAYER_OR_ARP_NEW_FORMATm || mem == EDB_PROTECTION_ENTRYm || mem == EDB_TRILL_FORMAT_FULL_ENTRYm || mem == EDB_TRILL_FORMAT_HALF_ENTRYm || mem == KAPS_TCMm || mem == SER_ACC_TYPE_MAPm) 343 { 344 SOC_EXIT; 345 } 346 347 #ifdef BCM_SAND_SUPPORT 348 if (SOC_MEM_IS_ALIAS(unit, mem)) { 349 SOC_EXIT; 350 } 351 352 353 if (mem == KAPS_RPB_TCAM_CPU_COMMANDm || 354 mem == KAPS_RPB_TCAM_HIT_INDICATIONm || 355 mem == OAMP_FLEX_VER_MASK_TEMPm || 356 mem == PPDB_B_LARGE_EM_FORMAT_0_TYPE_0m || 357 mem == SCH_FORCE_STATUS_MESSAGEm || 358 mem == SCH_SCHEDULER_INITm) 359 { 360 SOC_EXIT; 361 } 362 363 364 if(test_params->write_type == cache_mem_test_write_type_dma && 365 soc_mem_entry_words(unit, mem) + 2 > CMIC_SCHAN_WORDS(unit)) { 366 SOC_EXIT; 367 } 368 369 /* The following memories are Dynamic memory in QUX, we will skip them */ 370 if (cache_mem_dynamic_check(unit,mem)){ 371 SOC_EXIT; 372 } 373 374 /* Table IPSEC_TUNNEL_DATA is not SERrable and has no cache */ 375 if (SOC_IS_QUX(unit)) 376 { 377 if (mem == IPSEC_TUNNEL_DATAm) 378 { 379 SOC_EXIT; 380 } 381 } 382 383 if (test_params->test_type == cache_mem_test_type_all_mems) 384 { 385 if (cache_mem_cache_check_skip(unit, mem)) 386 { 387 test_params->stat_mem_not_tested_cnt++; 388 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: WRITE: force skipped memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 389 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_FORCE_SKIP_FLAG; 390 SOC_EXIT; 391 } 392 } 393 #endif 394 395 switch (test_params->write_type) 396 { 397 case cache_mem_test_write_type_dma: 398 { 399 for (i_array = start_array_index; i_array <= end_array_index; i_array++) 400 { 401 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: WRITE DMA: write memory %d %s \n"), mem, SOC_MEM_NAME(unit, mem))); 402 test_params->mem_id = mem; 403 #ifdef BCM_PETRA_SUPPORT 404 /* DMA write via caching currently Implemented only in Arad.*/ 405 rv = arad_fill_table_with_variable_values_by_caching(unit, mem, i_array, MEM_BLOCK_ALL, -1, -1, 406 cache_mem_test_fill_values_dma_callback, test_params); 407 #else 408 /* Fill the values in the non-dma way - as we do for schan writes */ 409 410 rv = cache_mem_test_fill_values_soc_mem_write_callback( unit, mem, i_array, data); 411 #endif 412 } 413 break; 414 } 415 case cache_mem_test_write_type_schan: 416 { 417 for (i_array = start_array_index; i_array <= end_array_index; i_array++) 418 { 419 rv = cache_mem_test_fill_values_soc_mem_write_callback( unit, mem, i_array, data); 420 } 421 } 422 } 423 424 if (rv != SOC_E_NONE) { 425 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_WRITE_FAILUE_FLAG; 426 test_params->stat_mem_fail_cnt++; 427 test_params->result |= rv; 428 } else { 429 test_params->stat_mem_succeed_cnt++; 430 } 431 432 exit: 433 SOC_FUNC_RETURN; 434 } 435 436 int cache_check_mem_SCH_PORT_SCHEDULER_WEIGHTS_PSW(int unit, int flag) 437 { 438 int rv; 439 soc_mem_t mem = SCH_PORT_SCHEDULER_WEIGHTS_PSWm; 440 uint32 entry_dw; 441 uint32 ii, array = 0, index = 0; 442 uint32 read_value[SOC_MEM_ENTRY_LENGTH_MAX]; 443 uint32 read_cache_value[SOC_MEM_ENTRY_LENGTH_MAX]; 444 uint32 mem_field_mask[SOC_MEM_ENTRY_LENGTH_MAX]; 445 int cache_error; 446 447 cache_mem_test_create_mask(unit, mem, sizeof(mem_field_mask), mem_field_mask); 448 entry_dw = soc_mem_entry_words(unit, mem); 449 rv = soc_mem_array_read(unit, mem, array, MEM_BLOCK_ANY, index, read_cache_value); 450 rv |= soc_mem_array_read_flags(unit, mem, array, MEM_BLOCK_ANY, index, read_value, SOC_MEM_DONT_USE_CACHE); 451 452 cache_error = 0; 453 for (ii = 0; ii < entry_dw; ii++) 454 { 455 if ((read_value[ii] & mem_field_mask[ii]) == (read_cache_value[ii] & mem_field_mask[ii])) 456 { 457 cache_error = 1; 458 break; 459 } 460 } 461 462 463 if (cache_error) 464 { 465 cli_out("%-8d%-12s", flag, "ERROR"); 466 } 467 else 468 { 469 cli_out("%-8d%-12s", flag, "OK"); 470 } 471 472 for (ii = 0; ii < entry_dw; ii++) 473 { 474 cli_out("%08X/%08X ", read_value[ii], read_cache_value[ii]); 475 } 476 cli_out("\n"); 477 478 return rv; 479 } 480 481 482 int 483 cache_mem_test_read_and_compare_wo_expected(int unit, soc_mem_t mem, void* data) 484 { 485 soc_error_t rv = SOC_E_NONE; 486 uint32 start_array_index = 0, end_array_index = 0, i_array; 487 uint32 start_index, end_index, index; 488 uint32 entry_index = 0; 489 uint32 read_value[SOC_MEM_ENTRY_LENGTH_MAX]; 490 uint32 read_cache_value[SOC_MEM_ENTRY_LENGTH_MAX]; 491 uint32 mem_field_mask[SOC_MEM_ENTRY_LENGTH_MAX]; 492 tr_do_cache_mem_test_t *test_params = (tr_do_cache_mem_test_t *)data; 493 uint32 entry_dw; 494 495 test_params->stat_mem_total_cnt++; 496 497 #ifdef BCM_SAND_SUPPORT 498 if ((SOC_IS_ARAD(unit)) || (SOC_IS_DNXF(unit)) || (SOC_IS_DNX(unit))) 499 { 500 if (SOC_MEM_IS_ALIAS(unit, mem)) 501 { 502 test_params->stat_mem_not_tested_cnt++; 503 test_params->stat_mem_succeed_cnt--; 504 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_ALIAS_SKIP_FLAG; 505 goto done; 506 } 507 508 if(!soc_mem_is_cachable(unit, mem)) 509 { 510 /* skip memory*/ 511 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ: non-cachable memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 512 test_params->stat_mem_not_tested_cnt++; 513 test_params->stat_mem_succeed_cnt--; 514 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_NON_CACHEABLE_SKIP_FLAG; 515 goto done; 516 } 517 if (!soc_mem_cache_get(unit, mem, MEM_BLOCK_ALL)) { 518 test_params->stat_mem_not_tested_cnt++; 519 test_params->stat_mem_succeed_cnt--; 520 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ: uncached memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 521 522 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_NOT_SHADOWED_SKIP_FLAG; 523 goto done; 524 } 525 526 if (test_params->test_type == cache_mem_test_type_all_mems) 527 { 528 if (cache_mem_cache_check_skip(unit, mem)) 529 { 530 test_params->stat_mem_not_tested_cnt++; 531 test_params->stat_mem_succeed_cnt--; 532 533 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ: force skipped memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 534 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_FORCE_SKIP_FLAG; 535 goto done; 536 } 537 } 538 } 539 SOC_MEM_ALIAS_TO_ORIG(unit, mem); 540 #endif 541 542 entry_dw = soc_mem_entry_words(unit, mem); 543 start_index = parse_memory_index(unit, mem, "min"); 544 end_index = parse_memory_index(unit, mem, "max"); 545 cache_mem_test_create_mask(unit, mem, sizeof(mem_field_mask), mem_field_mask); 546 547 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ read memory %d %s, num_of_entries %d \n"), 548 mem, SOC_MEM_NAME(unit, mem), end_index - start_index + 1/*table_size*/)); 549 550 if (SOC_MEM_IS_ARRAY(unit,mem)) { 551 start_array_index = parse_memory_array_index(unit, mem, "min"); 552 end_array_index = parse_memory_array_index(unit, mem, "max"); 553 } 554 555 /*The following statement will be removed after SDK-91354 will be fixed.*/ 556 if (mem == EDB_LINK_LAYER_OR_ARP_NEW_FORMATm || mem == EDB_PROTECTION_ENTRYm || mem == EDB_TRILL_FORMAT_FULL_ENTRYm || mem == EDB_TRILL_FORMAT_HALF_ENTRYm || mem == KAPS_TCMm || mem == SER_ACC_TYPE_MAPm) 557 { 558 return 0; 559 } 560 561 for (i_array = start_array_index; i_array <= end_array_index; i_array++) 562 { 563 for (index = start_index; index <= end_index; index++ ) 564 { 565 rv = soc_mem_array_read(unit, mem, i_array, MEM_BLOCK_ANY, index, read_cache_value); 566 rv |= soc_mem_array_read_flags(unit, mem, i_array, MEM_BLOCK_ANY, index, read_value, SOC_MEM_DONT_USE_CACHE); 567 if (rv != SOC_E_NONE) 568 { 569 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST:Read FAILED rv %d: read_value 0x%X cache_value 0x%X mask 0x%X mem %d %s, index %d, array %d\n"), 570 rv, read_value[entry_index], read_cache_value[entry_index], mem_field_mask[entry_index], mem, SOC_MEM_NAME(unit, mem), index, i_array)); 571 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_READ_FAILUE_FLAG; 572 goto done; 573 } 574 575 for (entry_index = 0; entry_index < entry_dw; entry_index++) 576 { 577 if ((read_value[entry_index] & mem_field_mask[entry_index]) == (read_cache_value[entry_index] & mem_field_mask[entry_index])) 578 { 579 LOG_DEBUG(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ: read_value 0x%X cache_value 0x%X, mask 0x%X, mem %d, index %d, entry_index, %d array %d, len %d\n"), 580 read_value[entry_index] & mem_field_mask[entry_index], 581 read_cache_value[entry_index] & mem_field_mask[entry_index], 582 mem_field_mask[entry_index], 583 mem, index, entry_index, i_array, entry_dw)); 584 } 585 else 586 { 587 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: COMPARE FAILED: read_value 0x%X, cache_value 0x%X, (0x%X != 0x%X), mask 0x%X mem %d, index %d, entry_index %d array %d\n"), 588 read_value[entry_index] & mem_field_mask[entry_index], 589 read_cache_value[entry_index] & mem_field_mask[entry_index], 590 read_value[entry_index], read_cache_value[entry_index], 591 mem_field_mask[entry_index], 592 mem, index, entry_index, i_array)); 593 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_COMPARE_FAILUE_FLAG; 594 rv = SOC_E_LIMIT /* Unknown error */; 595 goto done; 596 } 597 } 598 } 599 } 600 601 done: 602 if (rv != SOC_E_NONE) { 603 test_params->stat_mem_fail_cnt++; 604 test_params->result |= rv; 605 } else { 606 test_params->stat_mem_succeed_cnt++; 607 } 608 609 return rv; 610 611 } 612 613 int 614 cache_mem_test_read_and_compare(SOC_SAND_IN int unit, SOC_SAND_IN soc_mem_t mem, void* data) 615 { 616 soc_error_t rv = SOC_E_NONE; 617 uint32 start_array_index = 0, end_array_index = 0, i_array; 618 uint32 start_index, end_index, index; 619 uint32 entry_index = 0; 620 uint32 read_value[SOC_MEM_ENTRY_LENGTH_MAX]; 621 uint32 read_cache_value[SOC_MEM_ENTRY_LENGTH_MAX]; 622 uint32 expected_value[SOC_MEM_ENTRY_LENGTH_MAX]; 623 uint32 mem_field_mask[SOC_MEM_ENTRY_LENGTH_MAX]; 624 tr_do_cache_mem_test_t *test_params = (tr_do_cache_mem_test_t *)data; 625 uint32 entry_dw; 626 soc_mem_t mem_orig = mem; 627 SOC_MEM_ALIAS_TO_ORIG(unit, mem_orig); 628 629 SOC_REG_ABOVE_64_CLEAR(read_value); 630 SOC_REG_ABOVE_64_CLEAR(read_cache_value); 631 SOC_REG_ABOVE_64_CLEAR(expected_value); 632 SOC_REG_ABOVE_64_CLEAR(mem_field_mask); 633 634 if (test_params->test_part != cache_mem_test_full) { 635 test_params->stat_mem_total_cnt++; 636 } 637 638 /*The following statement will be removed after SDK-91354 will be fixed.*/ 639 if (mem == EDB_LINK_LAYER_OR_ARP_NEW_FORMATm || mem == EDB_PROTECTION_ENTRYm || mem == EDB_TRILL_FORMAT_FULL_ENTRYm || mem == EDB_TRILL_FORMAT_HALF_ENTRYm || mem == KAPS_TCMm || mem == SER_ACC_TYPE_MAPm) 640 { 641 return 0; 642 } 643 644 #ifdef BCM_SAND_SUPPORT 645 if (SOC_MEM_IS_ALIAS(unit, mem)) { 646 return 0; 647 } 648 649 650 if (mem == KAPS_RPB_TCAM_CPU_COMMANDm || 651 mem == KAPS_RPB_TCAM_HIT_INDICATIONm || 652 mem == OAMP_FLEX_VER_MASK_TEMPm || 653 mem == PPDB_B_LARGE_EM_FORMAT_0_TYPE_0m || 654 mem == SCH_FORCE_STATUS_MESSAGEm || 655 mem == SCH_SCHEDULER_INITm) 656 { 657 return 0; 658 } 659 660 661 if(test_params->write_type == cache_mem_test_write_type_dma && 662 soc_mem_entry_words(unit, mem) + 2 > CMIC_SCHAN_WORDS(unit)) { 663 return 0; 664 } 665 666 667 if (SOC_IS_ARADPLUS_AND_BELOW(unit) && 668 (mem == SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR__CALm || 669 mem == SCH_SHAPER_DESCRIPTOR_MEMORY_STATIC_SHDSm || 670 mem == SCH_SHAPER_DESCRIPTOR_MEMORY_STATIC__SHDSm)) 671 { 672 return 0; 673 } 674 675 /* The following memories are Dynamic memory in QUX, we will skip them */ 676 if (cache_mem_dynamic_check(unit,mem)){ 677 return 0; 678 } 679 680 /* Table IPSEC_TUNNEL_DATA is not SERrable and has no cache */ 681 if (SOC_IS_QUX(unit)) 682 { 683 if (mem == IPSEC_TUNNEL_DATAm) 684 { 685 return 0; 686 } 687 } 688 689 if (test_params->test_type == cache_mem_test_type_all_mems) 690 { 691 if (cache_mem_cache_check_skip(unit, mem)) 692 { 693 test_params->stat_mem_not_tested_cnt++; 694 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: WRITE: force skipped memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 695 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_FORCE_SKIP_FLAG; 696 return 0; 697 } 698 } 699 #endif 700 701 702 #if defined(BCM_SAND_SUPPORT) 703 if ((SOC_IS_ARAD(unit)) || (SOC_IS_DNXF(unit)) || (SOC_IS_DNX(unit))) 704 { 705 if(!soc_mem_is_cachable(unit, mem)) 706 { 707 /* skip memory*/ 708 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ: uncachable memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 709 if (test_params->test_part != cache_mem_test_full) { 710 test_params->stat_mem_not_tested_cnt++; 711 test_params->stat_mem_succeed_cnt--; 712 } 713 goto done; 714 } 715 716 if (!soc_mem_cache_get(unit, mem, MEM_BLOCK_ALL)) { 717 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ: uncached memory %d %s\n"), mem, SOC_MEM_NAME(unit, mem))); 718 if (test_params->test_part != cache_mem_test_full) { 719 test_params->stat_mem_not_tested_cnt++; 720 test_params->stat_mem_succeed_cnt--; 721 } 722 goto done; 723 } 724 } 725 #endif 726 727 entry_dw = soc_mem_entry_words(unit, mem); 728 start_index = parse_memory_index(unit, mem, "min"); 729 end_index = parse_memory_index(unit, mem, "max"); 730 cache_mem_test_create_mask(unit, mem, sizeof(mem_field_mask), mem_field_mask); 731 732 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ read memory %d %s, num_of_entries %d \n"), 733 mem, SOC_MEM_NAME(unit, mem), end_index - start_index + 1/*table_size*/)); 734 735 if (SOC_MEM_IS_ARRAY(unit,mem)) { 736 start_array_index = parse_memory_array_index(unit, mem, "min"); 737 end_array_index = parse_memory_array_index(unit, mem, "max"); 738 } 739 740 for (i_array = start_array_index; i_array <= end_array_index; i_array++) 741 { 742 for (index = start_index; index <= end_index; index++ ) 743 { 744 rv = soc_mem_array_read(unit, mem, i_array, MEM_BLOCK_ANY, index, read_cache_value); 745 rv |= soc_mem_array_read_flags(unit, mem, i_array, MEM_BLOCK_ANY, index, read_value, SOC_MEM_DONT_USE_CACHE); 746 if (rv != SOC_E_NONE) 747 { 748 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST:Read FAILED rv %d: mem(%d : %s) read_value 0x%X cache_value 0x%X mask 0x%X, index %d, array %d\n"), 749 rv, mem, SOC_MEM_NAME(unit, mem), read_value[entry_index], read_cache_value[entry_index], mem_field_mask[entry_index], index, i_array)); 750 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_READ_FAILUE_FLAG; 751 goto done; 752 } 753 754 for (entry_index = 0; entry_index < entry_dw; entry_index++) 755 { 756 expected_value[entry_index] = cache_mem_test_generate_value(unit, mem_orig, i_array, index, test_params->write_value_pattern) & mem_field_mask[entry_index]; 757 758 if ((read_value[entry_index] & mem_field_mask[entry_index] ) == (expected_value[entry_index] & mem_field_mask[entry_index]) && 759 (read_cache_value[entry_index] & mem_field_mask[entry_index] ) == (expected_value[entry_index] & mem_field_mask[entry_index])) 760 { 761 LOG_DEBUG(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: READ: read_value 0x%X cache_value 0x%X == expected_value 0x%X, (0x%X == 0x%X), mask 0x%X, mem %d, index %d, entry_index, %d array %d, len %d\n"), 762 read_value[entry_index] & mem_field_mask[entry_index], 763 read_cache_value[entry_index] & mem_field_mask[entry_index], 764 expected_value[entry_index] & mem_field_mask[entry_index], 765 read_value[entry_index], expected_value[entry_index], 766 mem_field_mask[entry_index], 767 mem, index, entry_index, i_array, entry_dw)); 768 } 769 else 770 { 771 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: COMPARE FAILED: mem(%d : %s) read_value 0x%X, cache_value 0x%X, expected_value 0x%X, (0x%X != 0x%X != 0x%X), mask 0x%X, index %d, entry_index %d array %d\n"), 772 mem, SOC_MEM_NAME(unit, mem), read_value[entry_index] & mem_field_mask[entry_index], 773 read_cache_value[entry_index] & mem_field_mask[entry_index], 774 expected_value[entry_index] & mem_field_mask[entry_index], 775 read_value[entry_index], read_cache_value[entry_index], expected_value[entry_index], 776 mem_field_mask[entry_index], 777 index, entry_index, i_array)); 778 test_params->mem_test_result_flag[mem] |= CACHE_MEM_TEST_COMPARE_FAILUE_FLAG; 779 rv = SOC_E_LIMIT /* Unknown error */; 780 goto done; 781 } 782 } 783 } 784 } 785 done: 786 if (rv != SOC_E_NONE) { 787 test_params->stat_mem_fail_cnt++; 788 test_params->stat_mem_succeed_cnt--; 789 test_params->result |= rv; 790 } else { 791 if (test_params->test_part != cache_mem_test_full) { 792 test_params->stat_mem_succeed_cnt++; 793 } 794 } 795 796 return rv; 797 798 } 799 800 int 801 cache_mem_test_write_read_and_compare(SOC_SAND_IN int unit, SOC_SAND_IN soc_mem_t mem, void* data) { 802 if (cache_mem_test_write_iter_callback(unit, mem, data) < 0) { 803 return BCM_E_INTERNAL; 804 } 805 if (cache_mem_test_read_and_compare(unit, mem, data) < 0) { 806 return BCM_E_INTERNAL; 807 } 808 return BCM_E_NONE; 809 } 810 811 void do_cache_mem_test_print_usage(void) 812 { 813 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("Usage for Cache Memory Test: \n" 814 "test_type=X where X=0 for specific memory, X=1 for all memories\n" 815 "write_type=X where X=0 for DMA write, X=1 for SCHAN write\n" 816 "pattern=X where X=0 for All-Ones, X=1 for All-Zeroes, X=2 for Incremental, X=3 for Smart pattern\n" 817 "part=X where X=0 for Full-Test, X=1 for Only-Write-Part, X=2 for Only-Read-Part, X=3 for Cache VS HW test\n"))); 818 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("mem_id=X where X is memory id for specific memory test (applicable with test_type=0)\n"))); 819 } 820 821 int 822 do_cache_mem_test_init(int unit, args_t *a, void **p) 823 { 824 825 cmd_result_t rv = CMD_OK; 826 tr_do_cache_mem_test_t *test_params; 827 parse_table_t parse_table; 828 char *mem; 829 830 *p = NULL; 831 if ((test_params = sal_alloc(sizeof (tr_do_cache_mem_test_t), "cache_mem_test")) == 0) 832 { 833 rv = SOC_E_MEMORY; 834 goto done; 835 } 836 memset(test_params, 0, sizeof (*test_params)); 837 *p = (void *) test_params; 838 839 /* Set default params */ 840 test_params->test_type = cache_mem_test_type_single; 841 test_params->write_type = cache_mem_test_write_type_schan; 842 test_params->write_value_pattern = cache_mem_test_write_value_pattern_incremental; 843 test_params->test_part = cache_mem_test_full; 844 test_params->mem_id = INVALIDm; 845 test_params->result = CMD_OK; 846 847 /** seting default values **/ 848 parse_table_init(unit, &parse_table); 849 parse_table_add(&parse_table, "test_type", PQ_INT, (void *)(test_params->test_type), &(test_params->test_type), NULL); 850 parse_table_add(&parse_table, "write_type", PQ_INT, (void *)(test_params->write_type), &(test_params->write_type), NULL); 851 parse_table_add(&parse_table, "pattern", PQ_INT, (void *)(test_params->write_value_pattern), &(test_params->write_value_pattern), NULL); 852 parse_table_add(&parse_table, "part", PQ_INT | PQ_DFL, (void *)(test_params->test_part), &(test_params->test_part), NULL); 853 parse_table_add(&parse_table, "mem_id", PQ_STRING, "", &mem, NULL); 854 855 856 /** parsing arguments and checking seting needed values, checking validity of given options **/ 857 if (parse_arg_eq(a, &parse_table) < 0) 858 { 859 LOG_INFO(BSL_LS_APPL_TESTS,(BSL_META_U(unit,"%s: Invalid option: %s\n"), ARG_CMD(a), ARG_CUR(a))); 860 /* print usage */ 861 goto usage; 862 } 863 864 /** making sure no extra options were given **/ 865 if (ARG_CNT(a) != 0) 866 { 867 LOG_INFO(BSL_LS_APPL_TESTS,(BSL_META_U(unit,"%s: extra options starting with \"%s\"\n"), ARG_CMD(a), ARG_CUR(a))); 868 /* print usage */ 869 goto usage; 870 } 871 872 /* Get Test Type */ 873 if (test_params->test_type > cache_mem_test_type_all_mems || test_params->test_type < cache_mem_test_type_single) 874 { 875 goto usage; 876 } 877 878 /* Get Write Type */ 879 if (test_params->write_type > cache_mem_test_write_type_schan || test_params->write_type < cache_mem_test_write_type_dma) 880 { 881 goto usage;; 882 } 883 884 /* Get Pattern */ 885 if (test_params->write_value_pattern > cache_mem_test_write_value_pattern_smart || test_params->write_value_pattern < cache_mem_test_write_value_pattern_all_ones) 886 { 887 goto usage; 888 } 889 890 if (test_params->test_part > cache_mem_test_cache_only || test_params->test_part < cache_mem_test_full) 891 { 892 goto usage; 893 } 894 895 /* Get Memory ID */ 896 if (test_params->test_type != cache_mem_test_type_all_mems) 897 { 898 if (parse_memory_name(unit, (soc_mem_t *)&(test_params->mem_id), mem, NULL, NULL) < 0) 899 { 900 /* check memory if memory id */ 901 test_params->mem_id = sal_ctoi(mem, NULL); 902 } 903 if (!SOC_MEM_IS_VALID(unit, test_params->mem_id)) 904 { 905 LOG_INFO(BSL_LS_APPL_TESTS,(BSL_META_U(unit,"Memory %s is invalid\n"), mem)); 906 test_params->mem_id = INVALIDm; 907 goto usage; 908 } 909 } 910 #ifdef BCM_PETRA_SUPPORT 911 if (SOC_IS_ARAD(unit)) 912 { 913 bcm_common_linkscan_enable_set(unit,0); 914 soc_counter_stop(unit); 915 rv = bcm_dpp_counter_bg_enable_set(unit, FALSE); 916 if (CMD_OK == rv) 917 { 918 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST:unit %d counter processor background accesses suspended\n"), unit)); 919 } 920 else 921 { 922 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META("CACHE_MEM_TEST: unit %d counter processor background access suspend failed: %d (%s)\n"), 923 unit, rv, _SHR_ERRMSG(rv))); 924 } 925 926 if (test_params->test_part != cache_mem_test_cache_only) 927 { 928 if ((rv |= soc_dpp_device_reset(unit, SOC_DPP_RESET_MODE_REG_ACCESS, SOC_DPP_RESET_ACTION_INOUT_RESET)) < 0) 929 { 930 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "CACHE_MEM_TEST: unit %d ERROR: Unable to reinit \n"), unit)); 931 } 932 } 933 goto done; 934 } 935 #endif 936 937 #ifdef BCM_DNXF_SUPPORT 938 if (SOC_IS_DNXF(unit)) 939 { 940 goto done; 941 } 942 #endif 943 944 #ifdef BCM_DNX_SUPPORT 945 if (SOC_IS_DNX(unit)) 946 { 947 bcm_common_linkscan_enable_set(unit,0); 948 soc_counter_stop(unit); 949 950 if (test_params->test_part != cache_mem_test_cache_only && test_params->test_part != cache_mem_test_read_only) 951 { 952 /** mask all interrupts */ 953 bcm_switch_event_control_t type; 954 955 type.action = bcmSwitchEventMask; 956 type.event_id = BCM_SWITCH_EVENT_CONTROL_ALL; 957 type.index = 0; 958 959 if ((rv = bcm_switch_event_control_set(unit, BCM_SWITCH_EVENT_DEVICE_INTERRUPT, type, 1)) < 0) 960 { 961 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "CACHE_MEM_TEST: unit %d ERROR: Unable to mask all interrupts\n"), unit)); 962 } 963 } 964 goto done; 965 } 966 #endif 967 968 usage: 969 do_cache_mem_test_print_usage(); 970 rv = CMD_USAGE; 971 972 done: 973 if (rv != CMD_OK && test_params != NULL) 974 if (test_params) 975 test_params->result |= rv; 976 977 return rv; 978 } 979 980 981 982 int 983 do_cache_mem_test_done(int unit, void *p) 984 { 985 soc_error_t rv; 986 tr_do_cache_mem_test_t *test_params = (tr_do_cache_mem_test_t*)p; 987 988 rv = test_params->result; 989 LOG_INFO(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "CACHE_MEM_TEST: unit %d Done: Total %u, Failed %u, Not tested %u, Succeeded %u\n"), 990 unit, 991 test_params->stat_mem_total_cnt, 992 test_params->stat_mem_fail_cnt, 993 test_params->stat_mem_not_tested_cnt, 994 test_params->stat_mem_succeed_cnt)); 995 sal_free (p); 996 return rv; 997 } 998 999 int 1000 do_cache_mem_test(int unit, args_t *a, void* tr_do_cache_mem_test) 1001 { 1002 soc_error_t rv = BCM_E_NONE; 1003 tr_do_cache_mem_test_t *test_params = tr_do_cache_mem_test; 1004 1005 #ifdef BCM_SAND_SUPPORT 1006 int cache_enable = 1; 1007 #endif 1008 1009 #ifdef BCM_PETRA_SUPPORT 1010 uint32 val_bak; 1011 #endif 1012 1013 #ifdef BCM_PETRA_SUPPORT 1014 if (SOC_IS_JERICHO(unit) && 1015 (SOC_REG_IS_VALID(unit, FDA_ENABLE_DYNAMIC_MEMORY_ACCESSr)) && 1016 ((test_params->test_type == cache_mem_test_type_all_mems) || (test_params->mem_id == FDA_FDA_MCm))) { 1017 READ_FDA_ENABLE_DYNAMIC_MEMORY_ACCESSr(unit, &val_bak); 1018 /* Allow writes to FDA_FDA_MCm, and stay with this configuration for later writes to this memory */ 1019 WRITE_FDA_ENABLE_DYNAMIC_MEMORY_ACCESSr(unit, 1); 1020 } 1021 #endif 1022 1023 switch(test_params->test_type) 1024 { 1025 case cache_mem_test_type_all_mems: /* Run tests for all memories */ 1026 { 1027 #ifdef BCM_SAND_SUPPORT 1028 /* Turn on cache memory for all tables */ 1029 if (test_params->test_part == cache_mem_test_full || test_params->test_part == cache_mem_test_write_only) 1030 { 1031 cache_enable = TRUE; 1032 if (soc_mem_iterate(unit, sand_tbl_mem_cache_mem_set, &cache_enable) < 0) 1033 { 1034 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "CACHE_MEM_TEST: unit %d cache enable failed\n"), unit)); 1035 } 1036 } 1037 #endif 1038 1039 /* Do the write/read part of the test */ 1040 if (test_params->test_part == cache_mem_test_full) 1041 { 1042 if ((soc_mem_iterate(unit, cache_mem_test_write_read_and_compare, tr_do_cache_mem_test)) < 0) { 1043 rv = BCM_E_INTERNAL; 1044 } 1045 if (test_params->result) { 1046 break; 1047 } 1048 } 1049 if (test_params->test_part == cache_mem_test_write_only) 1050 { 1051 if ((soc_mem_iterate(unit, cache_mem_test_write_iter_callback, tr_do_cache_mem_test)) < 0) { 1052 rv = BCM_E_INTERNAL; 1053 } 1054 if (test_params->result) { 1055 break; 1056 } 1057 } 1058 /* Do the read part of the test */ 1059 if (test_params->test_part == cache_mem_test_read_only) 1060 { 1061 if ((soc_mem_iterate(unit, cache_mem_test_read_and_compare, tr_do_cache_mem_test)) < 0) { 1062 rv = BCM_E_INTERNAL; 1063 } 1064 if (test_params->result) { 1065 break; 1066 } 1067 } 1068 /* Do the HW vs Cache part of the test */ 1069 if (test_params->test_part == cache_mem_test_cache_only) 1070 { 1071 if ((soc_mem_iterate(unit, cache_mem_test_read_and_compare_wo_expected, tr_do_cache_mem_test)) < 0) { 1072 rv = BCM_E_INTERNAL; 1073 } 1074 if (test_params->result) { 1075 break; 1076 } 1077 } 1078 1079 #ifdef BCM_SAND_SUPPORT 1080 /* Turn off cache memory for all tables */ 1081 if (test_params->test_part == cache_mem_test_full || test_params->test_part == cache_mem_test_read_only) 1082 { 1083 cache_enable = FALSE; 1084 if (soc_mem_iterate(unit, sand_tbl_mem_cache_mem_set, &cache_enable) < 0) 1085 LOG_ERROR(BSL_LS_APPL_TESTS, (BSL_META_U(unit, "CACHE_MEM_TEST: unit %d cache disable failed\n"), unit)); 1086 } 1087 #endif 1088 break; 1089 1090 } 1091 case cache_mem_test_type_single: /* Run test for specific memory */ 1092 { 1093 #ifdef BCM_SAND_SUPPORT 1094 /* Turn on cache memory for all tables */ 1095 if (test_params->test_part != cache_mem_test_cache_only) 1096 { 1097 cache_enable = TRUE; 1098 sand_tbl_mem_cache_mem_set(unit, test_params->mem_id, &cache_enable); 1099 } 1100 #endif 1101 /* Do the write part of the test */ 1102 if (test_params->test_part == cache_mem_test_full || test_params->test_part == cache_mem_test_write_only) 1103 { 1104 rv = cache_mem_test_write_iter_callback(unit, test_params->mem_id, tr_do_cache_mem_test); 1105 if (rv) { 1106 break; 1107 } 1108 } 1109 /* Do the read part of the test */ 1110 if (test_params->test_part == cache_mem_test_full || test_params->test_part == cache_mem_test_read_only) 1111 { 1112 rv = cache_mem_test_read_and_compare(unit, test_params->mem_id, tr_do_cache_mem_test); 1113 if (rv) { 1114 break; 1115 } 1116 } 1117 /* Do the HW vs Cache part of the test */ 1118 if (test_params->test_part == cache_mem_test_cache_only) 1119 { 1120 rv = cache_mem_test_read_and_compare_wo_expected(unit, test_params->mem_id, tr_do_cache_mem_test); 1121 if (rv) { 1122 break; 1123 } 1124 } 1125 #ifdef BCM_SAND_SUPPORT 1126 /* Turn off cache memory for all tables */ 1127 if (test_params->test_part != cache_mem_test_cache_only) 1128 { 1129 cache_enable = FALSE; 1130 sand_tbl_mem_cache_mem_set(unit, test_params->mem_id, &cache_enable); 1131 } 1132 #endif 1133 break; 1134 } 1135 } 1136 1137 #ifdef BCM_PETRA_SUPPORT 1138 /* restore the value*/ 1139 if (SOC_IS_JERICHO(unit) && 1140 (SOC_REG_IS_VALID(unit, FDA_ENABLE_DYNAMIC_MEMORY_ACCESSr)) && 1141 ((test_params->test_type == cache_mem_test_type_all_mems) || (test_params->mem_id == FDA_FDA_MCm))) { 1142 WRITE_FDA_ENABLE_DYNAMIC_MEMORY_ACCESSr(unit, val_bak); 1143 } 1144 #endif 1145 1146 if (rv != SOC_E_NONE) 1147 test_params->result |= rv; 1148 1149 if (test_params->result) { 1150 test_error(unit, "Cache Memory Test Failed!\n"); 1151 } 1152 1153 #ifdef BCM_SAND_SUPPORT 1154 if (SOC_IS_SAND(unit) && (test_params->test_type == cache_mem_test_type_all_mems)) 1155 { 1156 cache_memory_test_result_dump(unit, test_params); 1157 } 1158 #endif 1159 1160 return rv; 1161 } 1162 1163 int soc_mem_single_test(int unit, soc_mem_t mem) 1164 { 1165 soc_error_t rv = BCM_E_NONE; 1166 1167 tr_do_cache_mem_test_t *test_params = NULL; 1168 1169 if ((test_params = sal_alloc(sizeof (tr_do_cache_mem_test_t), "cache_mem_test_single")) == 0) 1170 { 1171 rv = SOC_E_MEMORY; 1172 goto done; 1173 } 1174 memset(test_params, 0, sizeof (*test_params)); 1175 1176 test_params->mem_id = mem; 1177 test_params->test_type = cache_mem_test_type_single; 1178 test_params->write_type = cache_mem_test_write_type_schan; 1179 test_params->write_value_pattern = cache_mem_test_write_value_pattern_smart; 1180 test_params->test_part = cache_mem_test_full; 1181 1182 rv = do_cache_mem_test(unit, NULL, test_params); 1183 1184 rv = do_cache_mem_test_done(unit, test_params); 1185 done: 1186 return rv; 1187 1188 } 1189 #endif /*(BCM_ESW_SUPPORT) || (BCM_PETRA_SUPPORT) || (BCM_DFE_SUPPORT) */