bench.c (31956B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Benchmark tests 8 */ 9 10 #include <shared/bsl.h> 11 12 #include <sal/core/libc.h> 13 #include <stdarg.h> 14 15 #include <sal/types.h> 16 #include <soc/mem.h> 17 #include <soc/cm.h> 18 19 #include <sal/appl/pci.h> 20 #include <sal/appl/sal.h> 21 #include <sal/core/boot.h> 22 #include <sal/core/time.h> 23 24 #include <soc/l2x.h> 25 #include <soc/l3x.h> 26 #include <soc/phyctrl.h> 27 #include <soc/phy.h> 28 #include <soc/error.h> 29 30 #include <bcm/error.h> 31 #include <bcm/link.h> 32 33 #if defined(BCM_ESW_SUPPORT) 34 #include <bcm_int/esw/mbcm.h> 35 #endif 36 37 #include <appl/diag/system.h> 38 #include <appl/diag/parse.h> 39 #include <appl/diag/test.h> 40 #include <appl/diag/progress.h> 41 42 #include "testlist.h" 43 44 /* Decimal point formatting */ 45 #define INT_FRAC_2PT(x) (x) / 100, (x) % 100 46 47 typedef struct benchmark_s { 48 uint32 testMask; 49 int testNum; 50 int sizeMem; 51 char *bufMem; 52 int sizeDMA; 53 char *bufDMA; 54 char *testName; 55 sal_usecs_t stime, etime; 56 uint32 dataSize; 57 char *dataUnit; 58 } benchmark_t; 59 60 #define BENCH_BUFMEM_SIZE 0x100000 61 #define BENCH_BUFDMA_SIZE 0x200000 62 63 int 64 benchmark_done(int u, void *pa) 65 { 66 benchmark_t *b = (benchmark_t *) pa; 67 68 if (b) { 69 if (b->bufMem) 70 sal_free(b->bufMem); 71 if (b->bufDMA) 72 soc_cm_sfree(u, b->bufDMA); 73 74 sal_free(b); 75 } 76 77 return 0; 78 } 79 80 int 81 benchmark_init(int u, args_t *a, void **pa) 82 { 83 benchmark_t *b = 0; 84 int rv = -1; 85 parse_table_t pt; 86 87 *pa = NULL; 88 89 if ((b = sal_alloc(sizeof (benchmark_t), "benchmark")) == 0) 90 goto done; 91 92 memset(b, 0, sizeof (*b)); 93 94 *pa = (void *) b; 95 96 b->testMask = ~0; 97 b->testNum = 0; 98 99 b->sizeMem = BENCH_BUFMEM_SIZE; 100 101 if ((b->bufMem = sal_alloc(b->sizeMem, "benchmark")) == 0) { 102 cli_out("Not enough host memory\n"); 103 goto done; 104 } 105 106 b->sizeDMA = BENCH_BUFDMA_SIZE; 107 108 if ((b->bufDMA = soc_cm_salloc(u, b->sizeDMA, "benchmark")) == 0) { 109 cli_out("Not enough DMA memory\n"); 110 goto done; 111 } 112 113 parse_table_init(u, &pt); 114 parse_table_add(&pt, "TestMask", PQ_HEX|PQ_DFL, 0, 115 &b->testMask, NULL); 116 117 if (parse_arg_eq(a, &pt) < 0 || ARG_CNT(a) != 0) { 118 test_error(u, 119 "%s: Invalid option: %s\n", 120 ARG_CMD(a), 121 ARG_CUR(a) ? ARG_CUR(a) : "*"); 122 parse_arg_eq_done(&pt); 123 goto done; 124 } 125 126 parse_arg_eq_done(&pt); 127 128 rv = 0; 129 130 done: 131 if (rv < 0) 132 benchmark_done(u, *pa); 133 134 return rv; 135 } 136 137 static int 138 benchmark_begin(benchmark_t *b, 139 char *testName, 140 char *dataUnit, 141 uint32 dataSize) 142 { 143 assert(b->testName == 0); 144 145 if ((b->testMask & (1U << b->testNum)) == 0) { 146 return 0; 147 } 148 149 b->testName = testName; 150 b->dataSize = dataSize; 151 b->dataUnit = dataUnit; 152 b->stime = sal_time_usecs(); 153 154 return 1; 155 } 156 157 static void 158 benchmark_end(benchmark_t *b) 159 { 160 if (b->testName) { 161 int per_sec, usec_per; 162 sal_usecs_t td; 163 char plus = ' ', lessthan = ' '; 164 165 b->etime = sal_time_usecs(); 166 td = SAL_USECS_SUB(b->etime, b->stime); 167 if (td == 0) { 168 td = 1; /* Non-zero value */ 169 plus = '+'; 170 lessthan = '<'; 171 } 172 173 per_sec = _shr_div_exp10(b->dataSize, td, 8); 174 usec_per = b->dataSize ? _shr_div_exp10(td, b->dataSize, 2) : 0; 175 176 cli_out("%2d) %-28s%7d.%02d%c %5s/sec ; %c%7d.%02d usec/%s\n", 177 b->testNum, 178 b->testName, 179 INT_FRAC_2PT(per_sec), 180 plus, 181 b->dataUnit, 182 lessthan, 183 INT_FRAC_2PT(usec_per), 184 b->dataUnit); 185 186 b->testName = 0; 187 } 188 189 b->testNum++; 190 } 191 192 #if defined BCM_TRIUMPH_SUPPORT || defined BCM_SCORPION_SUPPORT 193 static int 194 _gen_l2x_insert(int unit, l2x_entry_t *entry) 195 { 196 return soc_mem_insert(unit, L2Xm, MEM_BLOCK_ANY, (void *)entry); 197 } 198 199 static int 200 _gen_l2x_delete(int unit, l2x_entry_t *entry) 201 { 202 return soc_mem_delete(unit, L2Xm, MEM_BLOCK_ANY, (void *)entry); 203 } 204 205 static int 206 _gen_l2x_lookup(int unit, l2x_entry_t *key, 207 l2x_entry_t *result, int *index_ptr) 208 { 209 return soc_mem_search(unit, L2Xm, MEM_BLOCK_ANY, index_ptr, 210 (void *)key, (void *)result, 0); 211 } 212 #endif /* BCM_TRIUMPH_SUPPORT */ 213 214 #ifdef BCM_TRIUMPH3_SUPPORT 215 static int 216 _ism_l2_mem_insert(int unit, soc_mem_t mem, void *entry) 217 { 218 return soc_mem_insert(unit, mem, MEM_BLOCK_ANY, (void *)entry); 219 } 220 221 static int 222 _ism_l2_mem_delete(int unit, soc_mem_t mem, void *entry) 223 { 224 return soc_mem_delete(unit, mem, MEM_BLOCK_ANY, (void *)entry); 225 } 226 227 static int 228 _ism_l2_mem_lookup(int unit, soc_mem_t mem, void *key, 229 void *result, int *index_ptr) 230 { 231 return soc_mem_search(unit, mem, MEM_BLOCK_ANY, index_ptr, 232 (void *)key, (void *)result, 0); 233 } 234 #endif /* BCM_TRIUMPH3_SUPPORT */ 235 236 int 237 benchmark_test(int unit, args_t *a, void *pa) 238 { 239 benchmark_t *b = (benchmark_t *) pa; 240 int rv = 0; 241 uint16 phy_data; 242 int iter_mem, iter_cmic, iter_miim; 243 int quickturn, i, test_p; 244 245 #if defined(BCM_ESW_SUPPORT) 246 int iter_dma, iter_pci; 247 uint32 reg = 0; 248 uint32 entry[SOC_MAX_MEM_WORDS]; 249 soc_reg_t test_register; 250 #endif 251 252 #if defined(BCM_XGS_SWITCH_SUPPORT) 253 sal_mac_addr_t mac = { 0x00, 0x01, 0x10, 0x55, 0x66, 0x77 }; 254 sal_mac_addr_t maclkup = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55}; 255 #endif /* BCM_XGS_SWITCH_SUPPORT */ 256 257 #ifdef BCM_ESW_SUPPORT 258 int blk = 0, port = 0, phy_port = 0; 259 #endif /* BCM_ESW_SUPPORT */ 260 261 262 quickturn = (SAL_BOOT_QUICKTURN != 0); 263 264 if (quickturn) { 265 iter_mem = 100; 266 iter_cmic = 200; 267 iter_miim = 200; 268 #if defined(BCM_ESW_SUPPORT) 269 iter_dma = 1; 270 iter_pci = 2000; 271 #endif 272 } else if (NULL != SOC_CONTROL(unit)->soc_rcpu_schan_op){ 273 iter_mem = 10; 274 iter_cmic = 5000; 275 iter_miim = 0; 276 #if defined(BCM_ESW_SUPPORT) 277 iter_dma = 0; 278 iter_pci = 0; 279 #endif 280 } else { 281 iter_mem = 10; 282 iter_cmic = 5000; 283 iter_miim = 5000; 284 #if defined(BCM_ESW_SUPPORT) 285 iter_dma = 100; 286 iter_pci = 50000; 287 #endif 288 } 289 290 SOC_MEM_TEST_SKIP_CACHE_SET(unit, TRUE); 291 292 if (benchmark_begin(b, "memset sys mem", "MB", 293 iter_mem * (b->sizeMem / 0x100000))) { 294 for (i = 0; i < iter_mem; i++) { 295 memset(b->bufMem, 0, b->sizeMem); 296 } 297 } 298 benchmark_end(b); 299 300 if (benchmark_begin(b, "memcpy sys mem", "MB", 301 iter_mem / 2 * (b->sizeMem / 0x100000))) { 302 for (i = 0; i < iter_mem; i++) { 303 memcpy(b->bufMem + b->sizeMem / 2, b->bufMem, b->sizeMem / 2); 304 } 305 } 306 benchmark_end(b); 307 308 309 if (benchmark_begin(b, "memset dma mem", "MB", 310 iter_mem * (b->sizeDMA / 0x100000))) { 311 for (i = 0; i < iter_mem; i++) { 312 memset(b->bufDMA, 0, b->sizeDMA); 313 } 314 } 315 benchmark_end(b); 316 317 if (benchmark_begin(b, "memcpy dma mem", "MB", 318 iter_mem / 2 * (b->sizeDMA / 0x100000 ))) { 319 for (i = 0; i < iter_mem; i++) { 320 memcpy(b->bufDMA + b->sizeDMA / 2, b->bufDMA, b->sizeDMA / 2); 321 } 322 } 323 benchmark_end(b); 324 325 #ifdef BCM_ESW_SUPPORT 326 if (SOC_IS_ESW(unit)) { 327 #ifdef BCM_CMICX_SUPPORT 328 if (soc_feature(unit, soc_feature_cmicx)) { 329 test_register = SOC_REG_IS_VALID(unit, CMIC_TOP_SBUS_TIMEOUTr); 330 test_register = SOC_REG_IS_VALID(unit, CMIC_TOP_SBUS_TIMEOUTr) ? \ 331 CMIC_TOP_SBUS_TIMEOUTr : 0; 332 } else 333 #endif 334 { 335 test_register = SOC_REG_IS_VALID(unit, CMIC_DEV_REV_IDr) ? \ 336 CMIC_DEV_REV_IDr : CMIC_I2C_DATAr; 337 } 338 if (test_register) { 339 if (benchmark_begin(b, "read pci reg", "read", iter_pci)) { 340 for (i = 0; i < iter_pci; i++) { 341 soc_pci_getreg(unit, soc_reg_addr(unit, test_register, 342 REG_PORT_ANY, 0), ®); 343 } 344 } 345 346 benchmark_end(b); 347 348 if (benchmark_begin(b, "write pci reg", "write", iter_pci)) { 349 for (i = 0; i < iter_pci; i++) { 350 soc_pci_write(unit, soc_reg_addr(unit, test_register, 351 REG_PORT_ANY, 0), reg); 352 } 353 } 354 benchmark_end(b); 355 } 356 } 357 #endif /* BCM_ESW_SUPPORT */ 358 359 #ifdef BCM_ESW_SUPPORT 360 if (SOC_IS_ESW(unit)) { 361 /* find an appropriate block to read and write */ 362 if (SOC_PORT_NUM(unit, fe) > 0) { 363 port = SOC_PORT(unit, fe, 0); 364 } else if (SOC_PORT_NUM(unit, ge) > 0) { 365 port = SOC_PORT(unit, ge, 0); 366 } else if (SOC_PORT_NUM(unit, xe) > 0) { 367 port = SOC_PORT(unit, xe, 0); 368 } else { 369 port = SOC_PORT(unit, hg, 0); 370 } 371 if (soc_feature(unit, soc_feature_logical_port_num)) { 372 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 373 } else { 374 phy_port = port; 375 } 376 blk = SOC_PORT_BLOCK(unit, phy_port); 377 } 378 #endif /* BCM_ESW_SUPPORT */ 379 380 if (benchmark_begin(b, "read soc reg", "read", 381 iter_cmic)) { 382 if (SOC_IS_ESW(unit)) { 383 #ifdef BCM_ESW_SUPPORT 384 #ifdef BCM_HERCULES_SUPPORT 385 if (SOC_IS_HERCULES(unit)) { 386 for (i = 0; i < iter_cmic; i++) { 387 /* coverity[unchecked_value] */ 388 READ_ING_COS_MAPr(unit, port, ®); 389 } 390 } else 391 #endif /* BCM_HERCULES_SUPPORT */ 392 #ifdef BCM_TRX_SUPPORT 393 if (SOC_IS_TRX(unit)) { 394 for (i = 0; i < iter_cmic; i++) { 395 /* coverity[unchecked_value] */ 396 READ_EGR_CONFIGr(unit, ®); 397 } 398 } else 399 #endif /* BCM_TRX_SUPPORT */ 400 #ifdef BCM_FIREBOLT_SUPPORT 401 if (SOC_IS_FBX(unit)) { 402 for (i = 0; i < iter_cmic; i++) { 403 /* coverity[unchecked_value] */ 404 READ_EMIRROR_CONTROLr(unit, port, ®); 405 } 406 } else 407 #endif /* BCM_FIREBOLT_SUPPORT */ 408 { 409 /* Do Nothing */ 410 } 411 #endif /* BCM_ESW_SUPPORT */ 412 } else { 413 } 414 } 415 benchmark_end(b); 416 if (benchmark_begin(b, "write soc reg", "write", 417 iter_cmic)) { 418 if (SOC_IS_ESW(unit)) { 419 #ifdef BCM_ESW_SUPPORT 420 #ifdef BCM_HERCULES_SUPPORT 421 if (SOC_IS_HERCULES(unit)) { 422 for (i = 0; i < iter_cmic; i++) { 423 WRITE_ING_COS_MAPr(unit, port, reg); 424 } 425 } else 426 #endif /* BCM_HERCULES_SUPPORT */ 427 #ifdef BCM_TRX_SUPPORT 428 if (SOC_IS_TRX(unit)) { 429 for (i = 0; i < iter_cmic; i++) { 430 WRITE_EGR_CONFIGr(unit, reg); 431 } 432 } else 433 #endif /* BCM_TRX_SUPPORT */ 434 #ifdef BCM_FIREBOLT_SUPPORT 435 if (SOC_IS_FBX(unit)) { 436 for (i = 0; i < iter_cmic; i++) { 437 WRITE_EMIRROR_CONTROLr(unit, port, reg); 438 } 439 } else 440 #endif /* BCM_FIREBOLT_SUPPORT */ 441 { 442 /* Do Nothing */ 443 } 444 #endif /* BCM_ESW_SUPPORT */ 445 } else { 446 } 447 } 448 benchmark_end(b); 449 450 if (SOC_IS_ESW(unit)) { 451 #ifdef BCM_ESW_SUPPORT 452 #ifdef BCM_HERCULES_SUPPORT 453 if (SOC_IS_HERCULES(unit)) { 454 if (benchmark_begin(b, "read mc table entry", "read", 455 iter_cmic)) { 456 for (i = 0; i < iter_cmic; i++) { 457 /* coverity[unchecked_value] */ 458 READ_MEM_MCm(unit, blk, 10, entry); 459 } 460 } 461 benchmark_end(b); 462 463 if (benchmark_begin(b, "write mc table entry", "write", 464 iter_cmic)) { 465 for (i = 0; i < iter_cmic; i++) { 466 /* coverity[unchecked_value] */ 467 WRITE_MEM_MCm(unit, blk, 10, entry); 468 } 469 } 470 benchmark_end(b); 471 } else 472 #endif /* BCM_HERCULES_SUPPORT */ 473 #ifdef BCM_BRADLEY_SUPPORT 474 if (SOC_IS_XGS3_FABRIC(unit)) { 475 blk = SOC_MEM_BLOCK_ANY(unit, L2MCm); 476 if (benchmark_begin(b, "read l2mc table entry", "read", 477 iter_cmic)) { 478 for (i = 0; i < iter_cmic; i++) { 479 /* coverity[unchecked_value] */ 480 READ_L2MCm(unit, blk, 10, entry); 481 } 482 } 483 benchmark_end(b); 484 485 if (benchmark_begin(b, "write l2mc table entry", "write", 486 iter_cmic)) { 487 for (i = 0; i < iter_cmic; i++) { 488 WRITE_L2MCm(unit, blk, 10, entry); 489 } 490 } 491 benchmark_end(b); 492 } else 493 #endif /* BCM_BRADLEY_SUPPORT */ 494 #ifdef BCM_RAPTOR_SUPPORT 495 if (SOC_IS_RAPTOR(unit) || SOC_IS_RAVEN(unit) || SOC_IS_HAWKEYE(unit)) { 496 blk = SOC_MEM_BLOCK_ANY(unit, FP_POLICY_TABLEm); 497 if (benchmark_begin(b, "read FP Policy table entry", "read", 498 iter_cmic)) { 499 for (i = 0; i < iter_cmic; i++) 500 READ_FP_POLICY_TABLEm(unit, blk, 10, entry); 501 } 502 benchmark_end(b); 503 504 if (benchmark_begin(b, "write FP Policy table entry", "write", 505 iter_cmic)) { 506 for (i = 0; i < iter_cmic; i++) { 507 /* coverity[unchecked_value] */ 508 WRITE_FP_POLICY_TABLEm(unit, blk, 10, entry); 509 } 510 } 511 benchmark_end(b); 512 } else 513 #endif /* BCM_RAPTOR_SUPPORT */ 514 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) 515 if (SOC_IS_FIREBOLT2(unit) || SOC_IS_TRX(unit)) { 516 soc_mem_t mem = FP_POLICY_TABLEm; 517 518 if (SOC_MEM_IS_VALID(unit, IFP_POLICY_TABLEm)) { 519 mem = IFP_POLICY_TABLEm; 520 } 521 blk = SOC_MEM_BLOCK_ANY(unit, mem); 522 if (benchmark_begin(b, "read FP Policy table entry", "read", 523 iter_cmic)) { 524 for (i = 0; i < iter_cmic; i++) { 525 /* coverity[unchecked_value] */ 526 soc_mem_read(unit, mem, blk, 10, entry); 527 } 528 } 529 benchmark_end(b); 530 531 532 /* No further testing for RCPU_ONLY units */ 533 if(SOC_IS_RCPU_ONLY(unit)) { 534 SOC_MEM_TEST_SKIP_CACHE_SET(unit, FALSE); 535 return rv; 536 } 537 538 #if defined(BCM_TRIUMPH3_SUPPORT) 539 if (soc_feature(unit, soc_feature_ism_memory)) { 540 if (benchmark_begin(b, "Clear L2_ENTRY_1 table", "clear", 541 iter_mem)) { 542 for (i = 0; i < iter_mem; i++) { 543 /* coverity[unchecked_value] */ 544 soc_mem_clear(unit, L2_ENTRY_1m, MEM_BLOCK_ALL, TRUE); 545 } 546 } 547 benchmark_end(b); 548 } else 549 #endif /* BCM_TRIUMPH3_SUPPORT */ 550 { 551 if (benchmark_begin(b, "Clear L2X table", "clear", 552 iter_mem)) { 553 for (i = 0; i < iter_mem; i++) { 554 /* coverity[unchecked_value] */ 555 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, L2Xm, MEM_BLOCK_ALL, TRUE)); 556 } 557 } 558 benchmark_end(b); 559 } 560 561 if (benchmark_begin(b, "write FP Policy table entry", "write", 562 iter_cmic)) { 563 soc_mem_t mem = FP_POLICY_TABLEm; 564 565 if (SOC_MEM_IS_VALID(unit, IFP_POLICY_TABLEm)) { 566 mem = IFP_POLICY_TABLEm; 567 } 568 569 for (i = 0; i < iter_cmic; i++) { 570 /* coverity[unchecked_value] */ 571 soc_mem_write(unit, mem, blk, 10, entry); 572 } 573 } 574 benchmark_end(b); 575 } else 576 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT */ 577 #ifdef BCM_FIREBOLT_SUPPORT 578 if (SOC_IS_FBX(unit)) { 579 blk = SOC_MEM_BLOCK_ANY(unit, FP_TCAM_PLUS_POLICYm); 580 if (benchmark_begin(b, "read FP Policy table entry", "read", 581 iter_cmic)) { 582 for (i = 0; i < iter_cmic; i++) { 583 /* coverity[unchecked_value] */ 584 READ_FP_TCAM_PLUS_POLICYm(unit, blk, 10, entry); 585 } 586 } 587 benchmark_end(b); 588 589 if (benchmark_begin(b, "write FP Policy table entry", "write", 590 iter_cmic)) { 591 for (i = 0; i < iter_cmic; i++) { 592 /* coverity[unchecked_value] */ 593 WRITE_FP_TCAM_PLUS_POLICYm(unit, blk, 10, entry); 594 } 595 } 596 benchmark_end(b); 597 } else 598 #endif /* BCM_FIREBOLT_SUPPORT */ 599 { 600 /* Do Nothing */ 601 } 602 #endif /* BCM_ESW_SUPPORT */ 603 } else { 604 } 605 606 /* Since TH3 supports MDIO operation only for ATE, 607 skipping the below phy read/write as it involves 608 MDIO operation 609 */ 610 if(!SOC_IS_TOMAHAWK3(unit)) { 611 test_p = 2; 612 if(!IS_E_PORT(unit, test_p)) { 613 /* If port 2 is invalid, change the test port to port 0 */ 614 test_p = 0; 615 } 616 617 if (IS_E_PORT(unit, test_p)) { 618 if (! quickturn) { 619 if (benchmark_begin(b, "read phy reg", "read", 620 iter_miim)) { 621 622 for (i = 0; i < iter_miim; i++) 623 soc_miim_read(unit, PORT_TO_PHY_ADDR(unit, test_p), 624 MII_PHY_ID0_REG, &phy_data); 625 } 626 benchmark_end(b); 627 628 if (benchmark_begin(b, "write phy reg", "write", 629 iter_miim)) { 630 for (i = 0; i < iter_miim; i++) 631 soc_miim_write(unit, PORT_TO_PHY_ADDR(unit, test_p), 632 MII_PHY_ID0_REG, phy_data); 633 } 634 benchmark_end(b); 635 } 636 }/* IS_E_PORT */ 637 } 638 639 #ifdef BCM_ESW_SUPPORT 640 #if defined(BCM_TRIUMPH3_SUPPORT) 641 if (soc_feature(unit, soc_feature_ism_memory)) { 642 uint32 l2_entry[SOC_MAX_MEM_WORDS], l2_result[SOC_MAX_MEM_WORDS]; 643 soc_mem_t mem; 644 int mem_ix, index; 645 char buffer[100]; 646 647 for (mem_ix = 0; mem_ix < 4; mem_ix++) { 648 switch(mem_ix) { 649 case 0: 650 mem = L2_ENTRY_1m; 651 break; 652 case 1: 653 mem = L2_ENTRY_2m; 654 break; 655 case 2: 656 if (soc_feature(unit, soc_feature_esm_support)) { 657 mem = EXT_L2_ENTRY_1m; 658 break; 659 } else { 660 continue; 661 } 662 case 3: 663 if (soc_feature(unit, soc_feature_esm_support)) { 664 mem = EXT_L2_ENTRY_2m; 665 break; 666 } else { 667 continue; 668 } 669 default: 670 rv = -1; 671 SOC_MEM_TEST_SKIP_CACHE_SET(unit, FALSE); 672 /* break; */ return rv; 673 674 } 675 676 if (0 >= soc_mem_index_count(unit, mem)) { 677 /* No entries for this memory type. */ 678 continue; 679 } 680 681 memset(&l2_entry, 0, 682 WORDS2BYTES(soc_mem_entry_words(unit, mem))); 683 soc_mem_mac_addr_set(unit, mem, &l2_entry, MAC_ADDRf, mac); 684 soc_mem_field32_set(unit, mem, &l2_entry, VLAN_IDf, 1); 685 686 switch(mem_ix) { 687 case 0: 688 soc_mem_field32_set(unit, mem, &l2_entry, VALIDf, 1); 689 soc_mem_field32_set(unit, mem, &l2_entry, KEY_TYPEf, 690 SOC_MEM_KEY_L2_ENTRY_1_L2_BRIDGE); 691 break; 692 case 1: 693 soc_mem_field32_set(unit, mem, &l2_entry, KEY_TYPE_0f, 694 SOC_MEM_KEY_L2_ENTRY_2_L2_BRIDGE); 695 soc_mem_field32_set(unit, mem, &l2_entry, KEY_TYPE_1f, 696 SOC_MEM_KEY_L2_ENTRY_2_L2_BRIDGE); 697 soc_mem_field32_set(unit, mem, &l2_entry, WIDE_0f, 1); 698 soc_mem_field32_set(unit, mem, &l2_entry, WIDE_1f, 1); 699 soc_mem_field32_set(unit, mem, &l2_entry, VALID_0f, 1); 700 soc_mem_field32_set(unit, mem, &l2_entry, VALID_1f, 1); 701 break; 702 default: 703 soc_mem_field32_set(unit, mem, &l2_entry, KEY_TYPEf, 0); 704 break; 705 } 706 707 /* Cache the entry for use in second step */ 708 memcpy(&l2_result, &l2_entry, 709 WORDS2BYTES(soc_mem_entry_words(unit, mem))); 710 711 sal_sprintf(buffer, "ISM %s insert/delete", 712 SOC_MEM_NAME(unit, mem)); 713 if (benchmark_begin(b, buffer, "i+d", 714 iter_cmic)) { 715 for (i = 0; i < iter_cmic; i++) { 716 _ism_l2_mem_insert(unit, mem, &l2_entry); 717 _ism_l2_mem_delete(unit, mem, &l2_entry); 718 } 719 } 720 benchmark_end(b); 721 722 memcpy(&l2_entry, &l2_result, 723 WORDS2BYTES(soc_mem_entry_words(unit, mem))); 724 soc_mem_mac_addr_set(unit, mem, &l2_entry, MAC_ADDRf, maclkup); 725 726 sal_sprintf(buffer, "ISM %s lookup", 727 SOC_MEM_NAME(unit, mem)); 728 if (benchmark_begin(b, buffer, "lkup", iter_cmic)) { 729 for (i = 0; i < iter_cmic; i++) { 730 _ism_l2_mem_lookup(unit, mem, &l2_entry, 731 &l2_result, &index); 732 } 733 } 734 benchmark_end(b); 735 736 sal_sprintf(buffer, "DMA ISM %s table", 737 SOC_MEM_NAME(unit, mem)); 738 if (benchmark_begin(b, buffer, "xfer", 739 iter_dma)) { 740 for (i = 0; i < iter_dma; i++) 741 if (soc_mem_read_range(unit, mem, MEM_BLOCK_ANY, 742 soc_mem_index_min(unit, mem), 743 soc_mem_index_max(unit, mem), 744 b->bufDMA) < 0) { 745 rv = -1; 746 break; 747 } 748 } 749 benchmark_end(b); 750 } 751 752 /* IP tests for ESM analysis*/ 753 mem = PORT_TABm; 754 sal_sprintf(buffer, "DMA %s table", SOC_MEM_NAME(unit, mem)); 755 if (benchmark_begin(b, buffer, "xfer", iter_dma)) { 756 for (i = 0; i < iter_dma; i++) 757 if (soc_mem_read_range(unit, mem, MEM_BLOCK_ANY, 758 soc_mem_index_min(unit, mem), 759 soc_mem_index_max(unit, mem), 760 b->bufDMA) < 0) { 761 rv = -1; 762 break; 763 } 764 } 765 benchmark_end(b); 766 767 if ((-1 == soc_mem_index_max(unit, VRFm))) 768 { 769 mem = VLAN_PROTOCOL_DATAm; 770 } 771 else 772 { 773 mem = VRFm; 774 } 775 776 sal_sprintf(buffer, "DMA %s table", SOC_MEM_NAME(unit, mem)); 777 if (benchmark_begin(b, buffer, "xfer", iter_dma)) { 778 for (i = 0; i < iter_dma; i++) 779 if (soc_mem_read_range(unit, mem, MEM_BLOCK_ANY, 780 soc_mem_index_min(unit, mem), 781 soc_mem_index_max(unit, mem), 782 b->bufDMA) < 0) { 783 rv = -1; 784 break; 785 } 786 } 787 benchmark_end(b); 788 SOC_MEM_TEST_SKIP_CACHE_SET(unit, FALSE); 789 return rv; /* END OF ISM BENCHMARKS */ 790 } 791 #endif /* BCM_TRIUMPH3_SUPPORT */ 792 #if defined(BCM_FIREBOLT_SUPPORT) 793 if (SOC_IS_XGS_SWITCH(unit)) { 794 l2x_entry_t l2xent; 795 #if defined(BCM_XGS3_SWITCH_SUPPORT) && defined(INCLUDE_L3) 796 char *l3_dma_buf; 797 int alloc_size; 798 #endif /* BCM_XGS3_SWITCH_SUPPORT && INCLUDE_L3 */ 799 int (*l2x_ins)(int unit, l2x_entry_t *entry); 800 int (*l2x_del)(int unit, l2x_entry_t *entry); 801 int (*l2x_lkup)(int unit, l2x_entry_t *key, l2x_entry_t *result, 802 int *index_ptr); 803 804 #ifdef BCM_TRX_SUPPORT 805 if (soc_feature(unit, soc_feature_generic_table_ops)) { 806 l2x_ins = _gen_l2x_insert; 807 l2x_del = _gen_l2x_delete; 808 l2x_lkup = _gen_l2x_lookup; 809 } else 810 #endif /* BCM_TRX_SUPPORT */ 811 #ifdef BCM_FIREBOLT_SUPPORT 812 if (SOC_IS_FBX(unit)) { 813 l2x_ins = soc_fb_l2x_insert; 814 l2x_del = soc_fb_l2x_delete; 815 l2x_lkup = soc_fb_l2x_lookup; 816 } else 817 #endif /* BCM_FIREBOLT_SUPPORT */ 818 { 819 l2x_ins = NULL; 820 l2x_del = NULL; 821 l2x_lkup = NULL; 822 } 823 824 memset(&l2xent, 0, sizeof(l2xent)); 825 soc_L2Xm_mac_addr_set(unit, &l2xent, MAC_ADDRf, mac); 826 soc_L2Xm_field32_set(unit, &l2xent, VLAN_IDf, 1); 827 828 if (benchmark_begin(b, "L2 insert/delete", "i+d", 829 iter_cmic)) { 830 for (i = 0; i < iter_cmic; i++) { 831 l2x_ins(unit, &l2xent); 832 l2x_del(unit, &l2xent); 833 } 834 } 835 benchmark_end(b); 836 837 memset(&l2xent, 0, sizeof(l2xent)); 838 soc_L2Xm_mac_addr_set(unit, &l2xent, MAC_ADDRf, maclkup); 839 soc_L2Xm_field32_set(unit, &l2xent, VLAN_IDf, 1); 840 841 if (benchmark_begin(b, "L2 lookup", "lkup", 842 iter_cmic)) { 843 for (i = 0; i < iter_cmic; i++) { 844 l2x_entry_t l2xresult; 845 int index; 846 l2x_lkup(unit, &l2xent, &l2xresult, &index); 847 } 848 } 849 benchmark_end(b); 850 851 if (benchmark_begin(b, "DMA L2 table", "xfer", 852 iter_dma)) { 853 for (i = 0; i < iter_dma; i++) { 854 int min, max, step; 855 step = (b->sizeDMA / (sizeof(l2x_entry_t) * 1024)) * 1024; 856 for (min = soc_mem_index_min(unit, L2Xm), 857 max = soc_mem_index_max(unit, L2Xm); 858 min < max; min += step) { 859 if (soc_mem_read_range(unit, L2Xm, MEM_BLOCK_ANY, 860 min, 861 (min + step - 1) < max ? (min + step - 1) : max, 862 b->bufDMA) < 0) { 863 rv = -1; 864 break; 865 } 866 } 867 } 868 } 869 benchmark_end(b); 870 871 #if defined(BCM_XGS3_SWITCH_SUPPORT) && defined(INCLUDE_L3) 872 if (SOC_IS_FBX(unit) && 873 !SOC_IS_HAWKEYE(unit) && 874 SOC_MEM_IS_VALID(unit, L3_ENTRY_ONLYm) && 875 (soc_mem_index_count(unit,L3_ENTRY_ONLYm) > 0)) { 876 877 if (benchmark_begin(b, "Read L3_ENTRY_V4 table ", "xfer", 878 iter_cmic)) { 879 for (i = 0; i < iter_cmic; i++) { 880 /* coverity[unchecked_value] */ 881 SOC_IF_ERROR_RETURN(READ_L3_ENTRY_ONLYm(unit, blk, 10, entry)); 882 } 883 } 884 benchmark_end(b); 885 886 alloc_size = (SOC_L3X_BUCKET_SIZE(unit) / 2) * 887 WORDS2BYTES(soc_mem_entry_words(unit, L3_ENTRY_ONLYm)); 888 l3_dma_buf = soc_cm_salloc(unit, alloc_size, "L3 bucket dma"); 889 if (NULL != l3_dma_buf) { 890 sal_memset(l3_dma_buf, 0, alloc_size); 891 892 if (benchmark_begin(b, "Dma read L3_ENTRY bucket", "xfer", 893 iter_cmic)) { 894 for (i = 0; i < iter_cmic; i++) { 895 if (soc_mem_read_range(unit, L3_ENTRY_ONLYm, MEM_BLOCK_ANY, 896 10 * SOC_L3X_BUCKET_SIZE(unit), 897 10 * SOC_L3X_BUCKET_SIZE(unit) + 898 (SOC_L3X_BUCKET_SIZE(unit) / 2) - 1, 899 l3_dma_buf) < 0) { 900 rv = -1; 901 break; 902 } 903 } 904 } 905 benchmark_end(b); 906 907 soc_cm_sfree(unit, l3_dma_buf); 908 } else { 909 rv = -1; 910 } 911 } 912 #endif /* BCM_XGS3_SWITCH_SUPPORT && INCLUDE_L3 */ 913 SOC_MEM_TEST_SKIP_CACHE_SET(unit, FALSE); 914 } 915 #endif /* BCM_FIREBOLT_SUPPORT */ 916 #endif /* BCM_ESW_SUPPORT */ 917 918 919 { 920 sal_mutex_t m; 921 922 m = sal_mutex_create("bench"); 923 924 if (benchmark_begin(b, "mutex lock/unlock", "lock", 925 iter_cmic)) { 926 for (i = 0; i < iter_cmic; i++) { 927 sal_mutex_take(m, sal_mutex_FOREVER); 928 sal_mutex_give(m); 929 } 930 } 931 benchmark_end(b); 932 sal_mutex_destroy(m); 933 } 934 #ifdef BCM_ESW_SUPPORT 935 if (SOC_IS_TRIDENT(unit)) { /* only For Trident or TD+ */ 936 #if defined(INCLUDE_L3) 937 int rv = 0, j = 0; 938 bcm_mac_t nh_mac = {0,0xbb,0,0,0,0}; 939 bcm_l3_intf_t intf; 940 bcm_l3_route_t route; 941 bcm_l3_info_t l3_info; 942 int c; 943 944 bcm_l3_info_t_init(&l3_info); 945 rv = bcm_l3_info(unit, &l3_info); 946 947 bcm_l3_intf_t_init(&intf); 948 intf.l3a_vid = 1; 949 intf.l3a_flags = BCM_L3_ADD_TO_ARL | BCM_L3_WITH_ID; 950 sal_memcpy(intf.l3a_mac_addr, &nh_mac, sizeof(intf.l3a_mac_addr)); 951 952 rv = bcm_l3_intf_create(unit, &intf); 953 bcm_l3_route_t_init(&route); 954 955 route.l3a_vrf = 10; 956 route.l3a_subnet = 0x00000000; 957 route.l3a_ip_mask = 0xffff0000; 958 route.l3a_nexthop_ip = 0x0b0b0b0b; 959 route.l3a_intf = intf.l3a_intf_id; 960 sal_memcpy(&route.l3a_nexthop_mac, b, sizeof(route.l3a_nexthop_mac)); 961 962 if (benchmark_begin(b, "L3 DEFIP IPV4 Routes Add", "i+d", l3_info.l3info_max_route)) { 963 for (c = 1; c <= l3_info.l3info_max_route; c++) { 964 route.l3a_subnet = 0x0000000a + (c << 16); 965 rv = bcm_l3_route_add(unit, &route); 966 if (BCM_FAILURE(rv)) { 967 cli_out("bcm_l3_route_add: c = %d %s\n", c, bcm_errmsg(rv)); 968 break; 969 } 970 if (c % 4096 == 0) { 971 route.l3a_ip_mask = 0xfffff000; 972 route.l3a_subnet = 0xb000000a + (c << 16); 973 j = j + 1; 974 if (j == 2) { 975 route.l3a_ip_mask = 0xffffff00; 976 route.l3a_subnet = 0xc000000a + (c << 16); 977 } 978 if (j == 3) { 979 route.l3a_ip_mask = 0xfffffff0; 980 route.l3a_subnet = 0xd000000a + (c << 16); 981 } 982 if (j == 4) { 983 route.l3a_ip_mask = 0xffffffff; 984 route.l3a_subnet = 0xe000000a + (c << 16); 985 } 986 987 route.l3a_vrf += c % 10; 988 } 989 } 990 } 991 benchmark_end(b); 992 #endif /* INCLUDE_L3 */ 993 } /* SOC_IS_TD_TT() */ 994 #endif /* BCM_ESW_SUPPORT */ 995 996 /* Time config var get */ 997 if (benchmark_begin(b, "ConfigVar Get", "get", iter_cmic)) { 998 for (i = 0; i < iter_cmic; i++) { 999 soc_cm_config_var_get(unit, "p_abracadabra"); 1000 } 1001 } 1002 benchmark_end(b); 1003 1004 SOC_MEM_TEST_SKIP_CACHE_SET(unit, FALSE); 1005 return rv; 1006 }