brd_chassis.c (13462B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: brd_chassis.c 8 * Purpose: BCM956000 Chassis top level board programming 9 */ 10 11 #include <shared/bsl.h> 12 13 #include <bcm/error.h> 14 #include <appl/stktask/topology.h> 15 #include <appl/stktask/topo_brd.h> 16 17 #include "brd_chassis_int.h" 18 19 #if defined(INCLUDE_CHASSIS) 20 21 #if defined(INCLUDE_ATPTRANS_SOCKET) 22 23 #include <appl/cputrans/atptrans_socket.h> 24 #include <appl/stktask/stktask.h> 25 #include "topo_int.h" 26 27 28 /************** ATP over Sockets Support ***********/ 29 30 /* Config variable for ATP over Sockets installation */ 31 #define ATPTRANS_SOCKET "atptrans_socket" 32 33 /*********************************************************************** 34 * 35 * Chassis Default IP Addresses and Interfaces 36 * 37 * In a chassis based system, there will be one interface or subnet 38 * defined for each CFM. Each fabric or line module will 39 * have one unique IP address per interface. 40 */ 41 42 /* Default chassis IP addresses */ 43 #define CHASSIS_IP_DEF_B0 192 /* IP addr 1st byte */ 44 #define CHASSIS_IP_DEF_B1 168 /* IP addr 2nd byte */ 45 #define CHASSIS_IP_DEF_B2_IF0 0 /* IP addr 3rd byte, interface to CFM 0 */ 46 #define CHASSIS_IP_DEF_B2_IF1 1 /* IP addr 3rd byte, interface to CFM 1 */ 47 48 #define CHASSIS_IP_DEF_B3_S0 1 /* IP addr 4th byte, slot 0 */ 49 #define CHASSIS_IP_DEF_B3_S1 1 /* IP addr 4th byte, slot 1 */ 50 #define CHASSIS_IP_DEF_B3_S2 10 51 #define CHASSIS_IP_DEF_B3_S3 11 52 #define CHASSIS_IP_DEF_B3_S4 12 53 #define CHASSIS_IP_DEF_B3_S5 13 54 55 #define CHASSIS_IPADDR_DEF_MASK_IF0 \ 56 ( (CHASSIS_IP_DEF_B0 << 24) | \ 57 (CHASSIS_IP_DEF_B1 << 16) | \ 58 (CHASSIS_IP_DEF_B2_IF0 << 8) ) 59 60 #define CHASSIS_IPADDR_DEF_MASK_IF1 \ 61 ( (CHASSIS_IP_DEF_B0 << 24) | \ 62 (CHASSIS_IP_DEF_B1 << 16) | \ 63 (CHASSIS_IP_DEF_B2_IF1 << 8) ) 64 65 STATIC int 66 bcm_board_chassis_get_ip(cpudb_ref_t new_db, 67 cpudb_base_t *cpudb_base_ptr, bcm_ip_t *ip_addr) 68 { 69 /* CFM0 Interface */ 70 static bcm_ip_t chassis_ip_default_if0[] = { 71 CHASSIS_IPADDR_DEF_MASK_IF0 | CHASSIS_IP_DEF_B3_S0, 72 CHASSIS_IPADDR_DEF_MASK_IF0 | CHASSIS_IP_DEF_B3_S1, 73 CHASSIS_IPADDR_DEF_MASK_IF0 | CHASSIS_IP_DEF_B3_S2, 74 CHASSIS_IPADDR_DEF_MASK_IF0 | CHASSIS_IP_DEF_B3_S3, 75 CHASSIS_IPADDR_DEF_MASK_IF0 | CHASSIS_IP_DEF_B3_S4, 76 CHASSIS_IPADDR_DEF_MASK_IF0 | CHASSIS_IP_DEF_B3_S5 77 }; 78 79 /* CFM1 Interface */ 80 static bcm_ip_t chassis_ip_default_if1[] = { 81 CHASSIS_IPADDR_DEF_MASK_IF1 | CHASSIS_IP_DEF_B3_S0, 82 CHASSIS_IPADDR_DEF_MASK_IF1 | CHASSIS_IP_DEF_B3_S1, 83 CHASSIS_IPADDR_DEF_MASK_IF1 | CHASSIS_IP_DEF_B3_S2, 84 CHASSIS_IPADDR_DEF_MASK_IF1 | CHASSIS_IP_DEF_B3_S3, 85 CHASSIS_IPADDR_DEF_MASK_IF1 | CHASSIS_IP_DEF_B3_S4, 86 CHASSIS_IPADDR_DEF_MASK_IF1 | CHASSIS_IP_DEF_B3_S5 87 }; 88 89 int slot; 90 int max_slots; 91 cpudb_entry_t *local_entry; 92 cpudb_entry_t *master_entry; 93 bcm_ip_t *ip_addr_tbl; 94 95 if ((local_entry = new_db->local_entry) == NULL) { 96 return BCM_E_PARAM; 97 } 98 99 /* Interface */ 100 101 /* Determine interface to use based on local CPU information as follows: 102 * - For a local CPU that is part of a CFM, the interface is 103 * determined by the local CPU type. 104 * - For a local CPU that is part of a LM, the interface is 105 * determined by the master CPU. 106 * 107 * NOTE: The type of module (CFM or LM) is currently derived from 108 * the slot id. 109 */ 110 111 if (local_entry->base.slot_id == 0) { /* CFM0-CFM1, CFM0-LMx */ 112 ip_addr_tbl = &chassis_ip_default_if0[0]; 113 } else if (local_entry->base.slot_id == 1) { /* CFM1-CFM0, CFM1-LMx */ 114 ip_addr_tbl = &chassis_ip_default_if1[0]; 115 } else { 116 if ((master_entry = new_db->master_entry) == NULL) { 117 return BCM_E_PARAM; 118 } 119 120 /* For LMs, interface depends on destination */ 121 if (cpudb_base_ptr->slot_id == 0) { /* LMx-CFM0 */ 122 ip_addr_tbl = &chassis_ip_default_if0[0]; 123 } else if (cpudb_base_ptr->slot_id == 1) { /* LMx-CFM1 */ 124 ip_addr_tbl = &chassis_ip_default_if1[0]; 125 } else { /* LMx-LMx, use Master */ 126 if (master_entry->base.slot_id == 0) { 127 ip_addr_tbl = &chassis_ip_default_if0[0]; 128 } else { 129 ip_addr_tbl = &chassis_ip_default_if1[0]; 130 } 131 } 132 } 133 134 /* Get destination slot */ 135 max_slots = COUNTOF(chassis_ip_default_if0); 136 slot = cpudb_base_ptr->slot_id; 137 if ((slot < 0) || (slot >= max_slots )) { 138 LOG_ERROR(BSL_LS_TKS_TOPOLOGY, 139 (BSL_META("ATP-Socket ERROR: Invalid destination slot %d\n"), 140 slot)); 141 return BCM_E_FAIL; 142 } 143 144 *ip_addr = ip_addr_tbl[slot]; 145 146 return BCM_E_NONE; 147 } 148 149 150 STATIC void 151 bcm_board_chassis_atptrans_socket_update(cpudb_ref_t new_db, cpudb_ref_t old_db) 152 { 153 int rv; 154 cpudb_entry_t *old_cpu_ptr; 155 cpudb_entry_t *new_cpu_ptr; 156 bcm_ip_t ip_addr; 157 158 159 LOG_VERBOSE(BSL_LS_TKS_TOPOLOGY, 160 (BSL_META("TKS ATP-Socket Update: new_db %p. old_db %p\n"), 161 new_db, old_db)); 162 163 if ((new_db == NULL) && (old_db == NULL)) { 164 return; 165 } 166 167 /* 168 * Uninstall socket interface from ATP transport 169 * for each CPU no longer in DB 170 */ 171 if (old_db != NULL) { 172 new_cpu_ptr = NULL; 173 174 CPUDB_FOREACH_ENTRY(old_db, old_cpu_ptr) { 175 /* If local CPU, do nothing */ 176 if (old_cpu_ptr->flags & CPUDB_F_IS_LOCAL) { 177 continue; 178 } 179 180 /* Check if CPU is no longer in DB */ 181 if (new_db != NULL) { 182 CPUDB_KEY_SEARCH(new_db, old_cpu_ptr->base.key, new_cpu_ptr); 183 } 184 if (new_cpu_ptr != NULL) { /* CPU is still present */ 185 continue; 186 } 187 188 atptrans_socket_uninstall(old_cpu_ptr->base.key); 189 } 190 } 191 192 /* Install socket interface in ATP transport for CPU in new DB */ 193 if (new_db != NULL) { 194 195 /* Local CPU must be set first */ 196 CPUDB_FOREACH_ENTRY(new_db, new_cpu_ptr) { 197 if (new_cpu_ptr->flags & CPUDB_F_IS_LOCAL) { 198 atptrans_socket_local_cpu_key_set(new_cpu_ptr->base.key); 199 break; 200 } 201 } 202 203 /* Install socket interface on non-local CPUs */ 204 CPUDB_FOREACH_ENTRY(new_db, new_cpu_ptr) { 205 if (new_cpu_ptr->flags & CPUDB_F_IS_LOCAL) { 206 continue; 207 } 208 rv = bcm_board_chassis_get_ip(new_db, &new_cpu_ptr->base, &ip_addr); 209 if (BCM_SUCCESS(rv)) { 210 atptrans_socket_install(new_cpu_ptr->base.key, ip_addr, 0x0); 211 } else { 212 LOG_ERROR(BSL_LS_TKS_TOPOLOGY, 213 (BSL_META("Invalid IP address. Cannot install ATP over " 214 "Sockets for CPU key" CPUDB_KEY_FMT_EOLN), 215 CPUDB_KEY_DISP(new_cpu_ptr->base.key))); 216 } 217 } 218 } 219 220 return; 221 } 222 223 int 224 bcm_board_chassis_atptrans_socket_transition(bcm_st_state_t from, 225 bcm_st_event_t event, 226 bcm_st_state_t to, 227 cpudb_ref_t disc_db, 228 cpudb_ref_t cur_db) 229 { 230 int rv; 231 232 rv = bcm_st_transition(from, event, to, disc_db, cur_db); 233 234 if (!atptrans_socket_server_running()) { 235 atptrans_socket_server_start(); 236 } 237 238 if (to == BCM_STS_ATTACH) { 239 bcm_board_chassis_atptrans_socket_update(disc_db, cur_db); 240 } 241 242 return rv; 243 } 244 245 #endif /* defined(INCLUDE_ATPTRANS_SOCKET) */ 246 247 248 STATIC bcm_board_program_f prog[cpudb_board_id_count]; 249 250 /* 251 * Chassis Module ID Assignment 252 * 253 * The following table contains the base (start) mod ID assigned for 254 * each slot in a chassis based system. The entries are indexed by 255 * the slot numbers 0 - 9. 256 * 257 * Following assumptions are made 258 * - CFMs slot start at 0 259 * - LMs slot start at slot 2 260 * - There is 1 mod ID per CFM 261 * - There are 6 mod IDs per LM 262 */ 263 int topo_chassis_slot_to_mod_base[NUM_SLOT] = { 264 2, 3, /* CFMs get 1 mod-id */ 265 4, 10, 16, 22, /* All LMs get 6 mod-ids */ 266 28, 34, 40, 46 /* LMs 6-9: 10-slot chassis only */ 267 }; 268 269 int 270 bcm_board_cfm_info(cpudb_ref_t db_ref, bcm_board_cfm_info_t *info) 271 { 272 int count = 0; 273 cpudb_entry_t *cur; 274 int master_slot; 275 276 master_slot = db_ref->master_entry ? 277 db_ref->master_entry->base.slot_id : -1; 278 279 info->is_master = FALSE; 280 if (master_slot < 0) { 281 info->master = -1; 282 } else { 283 CPUDB_FOREACH_ENTRY(db_ref, cur) { 284 if (cur->base.slot_id < LM_SLOT_ID) { 285 info->cfm[count].slot = cur->base.slot_id; 286 info->cfm[count].modid = cur->dest_mod; 287 if (cur->base.slot_id == master_slot) { 288 info->master = count; 289 } 290 count++; 291 if (count >= NUM_CFM) { 292 break; 293 } 294 } 295 } 296 info->is_master = (master_slot == db_ref->local_entry->base.slot_id); 297 } 298 info->count = count; 299 return BCM_E_NONE; 300 } 301 302 303 STATIC int 304 chassis_run(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 305 { 306 int rv = BCM_E_PARAM; 307 int board_id = db_ref->local_entry->base.board_id; 308 309 if (board_id > cpudb_board_id_unknown && 310 board_id < cpudb_board_id_count) { 311 312 if (prog[board_id]) { 313 rv = (prog[board_id])(tp_cpu, db_ref); 314 } 315 } 316 317 return rv; 318 } 319 320 int 321 bcm_board_chassis_setup(cpudb_ref_t db_ref) 322 { 323 int flags = db_ref->local_entry->base.flags; 324 325 if (CHASSIS_AST(flags)) { 326 prog[cpudb_board_id_cfm_xgs2] = chassis_ast_cfm_xgs2; 327 prog[cpudb_board_id_lm_xgs2_6x] = chassis_ast_xgs2_6x; 328 prog[cpudb_board_id_lm_xgs2_48g] = chassis_ast_xgs2_48g; 329 prog[cpudb_board_id_lm_xgs3_12x] = chassis_ast_xgs3_12x; 330 prog[cpudb_board_id_lm_xgs3_48g] = chassis_ast_xgs3_48g; 331 prog[cpudb_board_id_cfm_xgs3] = chassis_ast_cfm_xgs3; 332 prog[cpudb_board_id_lm_56800_12x] = chassis_ast_56800_12x; 333 } else if (CHASSIS_SM(flags)) { 334 prog[cpudb_board_id_cfm_xgs2] = chassis_smlb_cfm_xgs2; 335 prog[cpudb_board_id_lm_xgs2_6x] = chassis_smlb_xgs2_6x; 336 prog[cpudb_board_id_lm_xgs2_48g] = chassis_smlb_xgs2_48g; 337 prog[cpudb_board_id_lm_xgs3_12x] = chassis_smlb_xgs3_12x; 338 prog[cpudb_board_id_lm_xgs3_48g] = chassis_smlb_xgs3_48g; 339 prog[cpudb_board_id_cfm_xgs3] = chassis_smlb_cfm_xgs3; 340 prog[cpudb_board_id_lm_56800_12x] = chassis_smlb_56800_12x; 341 } else { 342 prog[cpudb_board_id_cfm_xgs2] = chassis_cfm_xgs2; 343 prog[cpudb_board_id_lm_xgs2_6x] = chassis_lm6x; 344 prog[cpudb_board_id_lm_xgs2_48g] = chassis_lm_xgs2_48g; 345 prog[cpudb_board_id_lm_xgs3_12x] = chassis_lm_xgs3_12x; 346 prog[cpudb_board_id_lm_xgs3_48g] = chassis_lm_xgs3_48g; 347 prog[cpudb_board_id_cfm_xgs3] = chassis_cfm_xgs3; 348 prog[cpudb_board_id_lm_56800_12x] = chassis_lm_56800_12x; 349 } 350 351 return BCM_E_NONE; 352 } 353 354 int 355 bcm_board_topo_cfm_xgs2(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 356 { 357 return chassis_run(tp_cpu, db_ref); 358 } 359 360 int 361 bcm_board_topo_lm6x(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 362 { 363 return chassis_run(tp_cpu, db_ref); 364 } 365 366 int 367 bcm_board_topo_lm_xgs2_48g(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 368 { 369 return chassis_run(tp_cpu, db_ref); 370 } 371 372 int 373 bcm_board_topo_lm_xgs3_48g(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 374 { 375 return chassis_run(tp_cpu, db_ref); 376 } 377 378 int 379 bcm_board_topo_cfm_xgs3(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 380 { 381 return chassis_run(tp_cpu, db_ref); 382 } 383 384 int 385 bcm_board_topo_lm_56800_12x(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 386 { 387 return chassis_run(tp_cpu, db_ref); 388 } 389 390 #else 391 392 int 393 bcm_board_topo_cfm_xgs2(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 394 { 395 COMPILER_REFERENCE(tp_cpu); 396 COMPILER_REFERENCE(db_ref); 397 return BCM_E_UNAVAIL; 398 } 399 400 int 401 bcm_board_topo_cfm_xgs3(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 402 { 403 COMPILER_REFERENCE(tp_cpu); 404 COMPILER_REFERENCE(db_ref); 405 return BCM_E_UNAVAIL; 406 } 407 408 int 409 bcm_board_topo_lm6x(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 410 { 411 COMPILER_REFERENCE(tp_cpu); 412 COMPILER_REFERENCE(db_ref); 413 return BCM_E_UNAVAIL; 414 } 415 416 int 417 bcm_board_topo_lm_xgs2_48g(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 418 { 419 COMPILER_REFERENCE(tp_cpu); 420 COMPILER_REFERENCE(db_ref); 421 return BCM_E_UNAVAIL; 422 } 423 424 int 425 bcm_board_topo_lm_xgs3_48g(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 426 { 427 COMPILER_REFERENCE(tp_cpu); 428 COMPILER_REFERENCE(db_ref); 429 return BCM_E_UNAVAIL; 430 } 431 432 int 433 bcm_board_topo_lm2x(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 434 { 435 COMPILER_REFERENCE(tp_cpu); 436 COMPILER_REFERENCE(db_ref); 437 return BCM_E_UNAVAIL; 438 } 439 440 int 441 bcm_board_topo_lm_56800_12x(topo_cpu_t *tp_cpu, cpudb_ref_t db_ref) 442 { 443 COMPILER_REFERENCE(tp_cpu); 444 COMPILER_REFERENCE(db_ref); 445 return BCM_E_UNAVAIL; 446 } 447 448 #endif /* INCLUDE_CHASSIS */ 449