dscdump.h (10702B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: dscdump.h 8 */ 9 10 #ifndef _DSCDUMP_H_ 11 #define _DSCDUMP_H_ 12 13 #include "types.h" 14 15 16 /*------------------------------*/ 17 /** Serdes Core State Structure */ 18 /*------------------------------*/ 19 typedef struct { 20 /** Core DP Reset State */ 21 uint8 core_reset; 22 /** PLL Powerdown enable */ 23 uint8 pll_pwrdn; 24 /** Micro active enable */ 25 uint8 uc_active; 26 /** Comclk Frequency in Mhz */ 27 uint16 comclk_mhz; 28 /** uCode Major Version number */ 29 uint16 ucode_version; 30 /** uCode Minor Version number */ 31 uint8 ucode_minor_version; 32 /** AFE Hardware version */ 33 uint8 afe_hardware_version; 34 /** uC Die Temperature Index */ 35 uint8 temp_idx; 36 /** Average Die Temperature (13-bit format) */ 37 uint16 avg_tmon; 38 /** Analog Resistor Calibration value */ 39 uint8 rescal; 40 /** VCO Rate in MHz */ 41 uint16 vco_rate_mhz; 42 /** Analog VCO Range */ 43 uint8 analog_vco_range; 44 /** PLL Divider value */ 45 uint8 pll_div; 46 /** PLL Lock */ 47 uint8 pll_lock; 48 /** PLL Lock Change */ 49 uint8 pll_lock_chg; 50 /** Live die temperature in Celsius */ 51 int16 die_temp; 52 /** Core Status Variable */ 53 uint8 core_status; 54 } bcm_core_state_st; 55 56 /*------------------------------*/ 57 /** Serdes OSR Mode Structure */ 58 /*------------------------------*/ 59 typedef struct { 60 /** TX OSR Mode */ 61 uint8 tx; 62 /** RX OSR Mode */ 63 uint8 rx; 64 /** OSR Mode for TX and RX (used when both TX and RX should have same OSR Mode) */ 65 uint8 tx_rx; 66 } bcm_osr_mode_st; 67 68 /*------------------------------*/ 69 /** Serdes Lane State Structure */ 70 /*------------------------------*/ 71 typedef struct { 72 /** uC lane configuration */ 73 uint16 ucv_config; 74 /** Frequency offset of local reference clock with respect to RX data in ppm */ 75 int16 rx_ppm; 76 /** Vertical threshold voltage of p1 slicer (mV) */ 77 int16 p1_lvl; 78 /** Vertical threshold voltage of m1 slicer (mV) */ 79 int16 m1_lvl; 80 /** Link time in milliseconds */ 81 uint16 link_time; 82 /** OSR Mode */ 83 bcm_osr_mode_st osr_mode; 84 /** Signal Detect */ 85 uint8 sig_det; 86 /** Signal Detect Change */ 87 uint8 sig_det_chg; 88 /** PMD RX Lock */ 89 uint8 rx_lock; 90 /** PMD RX Lock Change */ 91 uint8 rx_lock_chg; 92 /** Delay of zero crossing slicer, m1, wrt to data in PI codes */ 93 int8 clk90; 94 /** Delay of diagnostic/lms slicer, p1, wrt to data in PI codes */ 95 int8 clkp1; 96 /** Peaking Filter Main Settings */ 97 int8 pf_main; 98 /** Peaking Filter Hiz mode enable */ 99 int8 pf_hiz; 100 /** Peaking Filter DC gain adjustment for CTLE */ 101 int8 pf_bst; 102 /** Low Frequency Peaking filter control */ 103 int8 pf2_ctrl; 104 /** Variable Gain Amplifier settings */ 105 int8 vga; 106 /** DC offset DAC control value */ 107 int8 dc_offset; 108 /** P1 eyediag status */ 109 int8 p1_lvl_ctrl; 110 /** DFE tap 1 value */ 111 int8 dfe1; 112 /** DFE tap 2 value */ 113 int8 dfe2; 114 /** DFE tap 3 value */ 115 int8 dfe3; 116 /** DFE tap 4 value */ 117 int8 dfe4; 118 /** DFE tap 5 value */ 119 int8 dfe5; 120 /** DFE tap 6 value */ 121 int8 dfe6; 122 /** DFE tap 1 Duty Cycle Distortion */ 123 int8 dfe1_dcd; 124 /** DFE tap 2 Duty Cycle Distortion */ 125 int8 dfe2_dcd; 126 /** Slicer calibration control codes (p1 even) */ 127 int8 pe; 128 /** Slicer calibration control codes (data even) */ 129 int8 ze; 130 /** Slicer calibration control codes (m1 even) */ 131 int8 me; 132 /** Slicer calibration control codes (p1 odd) */ 133 int8 po; 134 /** Slicer calibration control codes (data odd) */ 135 int8 zo; 136 /** Slicer calibration control codes (m1 odd) */ 137 int8 mo; 138 /** Frequency offset of local reference clock with respect to TX data in ppm */ 139 int16 tx_ppm; 140 /** TX equalization FIR pre tap weight */ 141 int8 txfir_pre; 142 /** TX equalization FIR main tap weight */ 143 int8 txfir_main; 144 /** TX equalization FIR post1 tap weight */ 145 int8 txfir_post1; 146 /** TX equalization FIR post2 tap weight */ 147 int8 txfir_post2; 148 /** TX equalization FIR post3 tap weight */ 149 int8 txfir_post3; 150 /** Horizontal left eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 151 uint16 heye_left; 152 /** Horizontal right eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 153 uint16 heye_right; 154 /** Vertical upper eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 155 uint16 veye_upper; 156 /** Vertical lower eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 157 uint16 veye_lower; 158 /** Baud Rate Phase Detector enable */ 159 uint8 br_pd_en; 160 /** lane_reset_state **/ 161 uint8 reset_state; 162 /** uC stopped state **/ 163 uint8 stop_state; 164 } bcm_lane_state_st; 165 166 #ifdef SERDES_API_FLOATING_POINT 167 #define USR_DOUBLE double 168 #else 169 #define USR_DOUBLE int 170 #endif 171 172 /* Lane status Struct */ 173 struct bcm_detailed_lane_status_st { 174 /** Frequency offset of local reference clock with respect to RX data in ppm */ 175 USR_DOUBLE ppm; 176 /** Estimate for Main tap */ 177 USR_DOUBLE main_tap_est; 178 /** PRBS Error Count */ 179 uint32 prbs_chk_errcnt; 180 /** One Hot DSC State */ 181 uint16 dsc_sm[2]; 182 /** Horizontal left eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 183 uint16 heye_left; 184 /** Horizontal right eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 185 uint16 heye_right; 186 /** Vertical upper eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 187 uint16 veye_upper; 188 /** Vertical lower eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 189 uint16 veye_lower; 190 /** Link time in milliseconds */ 191 uint16 link_time; 192 /** Temperature Index */ 193 uint8 temp_idx; 194 /** TX driver to disable high voltage control */ 195 uint8 ams_tx_drv_hv_disable; 196 /** Analog Resistor Calibration value */ 197 uint8 ams_tx_ana_rescal; 198 /* Analog Amplitude control */ 199 uint8 amp_ctrl; 200 /** TX equalization FIR pre tap weight */ 201 uint8 pre_tap; 202 /** TX equalization FIR main tap weight */ 203 uint8 main_tap; 204 /** TX equalization FIR post1 tap weight */ 205 uint8 post1_tap; 206 /** TX equalization FIR post2 tap weight */ 207 int8 post2_tap; 208 /** TX equalization FIR post3 tap weight */ 209 int8 post3_tap; 210 /** Signal Detect */ 211 uint8 sigdet; 212 /** PMD RX Lock */ 213 uint8 pmd_lock; 214 /** PLL Select */ 215 uint8 pmd_pll_select; 216 /** Variable Gain Amplifier settings */ 217 uint8 vga; 218 /** Main Peaking Filter setting */ 219 uint8 pf; 220 /** Low Frequency Peaking Filter settings */ 221 uint8 pf2; 222 /** Data Slicer Threshold */ 223 int8 data_thresh; 224 /** Phase Slicer Threshold */ 225 int8 phase_thresh; 226 /** LMS Slicer Threshold */ 227 int8 lms_thresh; 228 /** Horizontal offset between data and dataq */ 229 uint8 ddq_hoffset; 230 /** Horizontal offset between phase and phaseq */ 231 uint8 ppq_hoffset; 232 /** Horizontal offset between lms and lmsq */ 233 uint8 llq_hoffset; 234 /** Horizontal offset between data and phase */ 235 uint8 dp_hoffset; 236 /** Horizontal offset between data and lms */ 237 uint8 dl_hoffset; 238 /** DFE tap values */ 239 int8 dfe[26][4]; 240 /** DC offset DAC control value */ 241 int8 dc_offset; 242 /** Slicer calibration control codes (datap) */ 243 int8 thctrl_dp[4]; 244 /** Slicer calibration control codes (datan) */ 245 int8 thctrl_dn[4]; 246 /** Slicer calibration control codes (phasep) */ 247 int8 thctrl_zp[4]; 248 /** Slicer calibration control codes (phasen) */ 249 int8 thctrl_zn[4]; 250 /** Slicer calibration control codes (lms) */ 251 int8 thctrl_l[4]; 252 /** PRBS Checker Enable */ 253 uint8 prbs_chk_en; 254 /** Order of PRBS Checker */ 255 uint8 prbs_chk_order; 256 /** PRBS Checker Lock */ 257 uint8 prbs_chk_lock; 258 /** lane_reset_state **/ 259 uint8 reset_state; 260 /** uC stopped state **/ 261 uint8 stop_state; 262 }; 263 264 /** TX AFE Settings Enum */ 265 enum srds_tx_afe_settings_enum { 266 TX_AFE_PRE, 267 TX_AFE_MAIN, 268 TX_AFE_POST1, 269 TX_AFE_POST2, 270 TX_AFE_POST3, 271 TX_AFE_AMP, 272 TX_AFE_DRIVERMODE 273 }; 274 275 /** Evenet Log Display Mode Enum */ 276 enum srds_event_log_display_mode_enum { 277 EVENT_LOG_HEX, 278 EVENT_LOG_DECODED, 279 EVENT_LOG_HEX_AND_DECODED, 280 EVENT_LOG_MODE_MAX 281 }; 282 283 /** Event Log Code Enum */ 284 enum srds_event_code_enum { 285 EVENT_CODE_UNKNOWN = 0, 286 EVENT_CODE_ENTRY_TO_DSC_RESET, 287 EVENT_CODE_RELEASE_USER_RESET, 288 EVENT_CODE_EXIT_FROM_DSC_RESET, 289 EVENT_CODE_ENTRY_TO_CORE_RESET, 290 EVENT_CODE_RELEASE_USER_CORE_RESET, 291 EVENT_CODE_ACTIVE_RESTART_CONDITION, 292 EVENT_CODE_EXIT_FROM_RESTART, 293 EVENT_CODE_WRITE_TR_COARSE_LOCK, 294 EVENT_CODE_CL72_READY_FOR_COMMAND, 295 EVENT_CODE_EACH_WRITE_TO_CL72_TX_CHANGE_REQUEST, 296 EVENT_CODE_FRAME_LOCK, 297 EVENT_CODE_LOCAL_RX_TRAINED, 298 EVENT_CODE_DSC_LOCK, 299 EVENT_CODE_FIRST_RX_PMD_LOCK, 300 EVENT_CODE_PMD_RESTART_FROM_CL72_CMD_INTF_TIMEOUT, 301 EVENT_CODE_LP_RX_READY, 302 EVENT_CODE_STOP_EVENT_LOG, 303 EVENT_CODE_GENERAL_EVENT_0, 304 EVENT_CODE_GENERAL_EVENT_1, 305 EVENT_CODE_GENERAL_EVENT_2, 306 EVENT_CODE_ERROR_EVENT, 307 EVENT_CODE_NUM_TIMESTAMP_WRAPAROUND_MAXOUT, 308 EVENT_CODE_RESTART_PMD_ON_CDR_LOCK_LOST, 309 EVENT_CODE_SM_STATUS_RESTART, 310 EVENT_CODE_CORE_PROGRAMMING, 311 EVENT_CODE_LANE_PROGRAMMING, 312 EVENT_CODE_RESTART_PMD_ON_CLOSE_EYE, 313 EVENT_CODE_RESTART_PMD_ON_DFE_TAP_CONFIG, 314 EVENT_CODE_CL72_AUTO_POLARITY_CHANGE, 315 EVENT_CODE_RESTART_FROM_CL72_MAX_TIMEOUT, 316 EVENT_CODE_CL72_LOCAL_TX_CHANGED, 317 EVENT_CODE_FIRST_WRITE_TO_CL72_TX_CHANGE_REQUEST, 318 EVENT_CODE_FRAME_UNLOCK, 319 EVENT_CODE_ENTRY_TO_CORE_PLL1_RESET, 320 EVENT_CODE_RELEASE_USER_CORE_PLL1_RESET, 321 322 /* !!! add new event code above this line !!! */ 323 EVENT_CODE_MAX, 324 EVENT_CODE_TIMESTAMP_WRAP_AROUND = 255 325 }; 326 327 /** uC Event Error Enum */ 328 enum srds_event_err_code_enum { 329 GENERIC_UC_ERROR = 0, 330 INVALID_REENTRY_ID, 331 DSC_CONFIG_INVALID_REENTRY_ID, 332 INVALID_OTP_CONFIG, 333 INVALID_CORE_TEMP_IDX 334 }; 335 336 /** Core Config Variable Structure in Microcode */ 337 struct bcm_uc_core_config_field_st { 338 uint8 vco_rate; 339 uint8 core_cfg_from_pcs; 340 uint8 reserved; 341 }; 342 343 /** Core Config Struct */ 344 struct bcm_uc_core_config_st { 345 struct bcm_uc_core_config_field_st field; 346 uint16 word; 347 int vco_rate_in_Mhz; /* if >0 then will get converted and replace field.vco_rate when update is called */ 348 }; 349 350 extern int bcm_do_dscdump(phy_ctrl_t *pc, int sys_port); 351 352 353 #endif /* _DSCDUMP_H_ */