reg_skip.c - openbcm - Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM

reg_skip.c (205026B)
      1 /*
      2  * 
      3  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4  * 
      5  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6  *
      7  * Diag routines to identify registers that are only implemented
      8  * on a subset of ports/cos.
      9  */
     10 
     11 #include <appl/diag/system.h>
     12 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT)
     13 #include <soc/mcm/memregs.h>
     14 #endif
     15 #ifdef BCM_TRIDENT2_SUPPORT
     16 #include <soc/trident2.h>
     17 #endif /* BCM_TRIDENT2_SUPPORT */
     18 #ifdef BCM_TOMAHAWK_SUPPORT
     19 #include <soc/tomahawk.h>
     20 #include <shared/bsl.h>
     21 #endif /* BCM_TOMAHAWK_SUPPORT */
     22 #ifdef BCM_TOMAHAWK2_SUPPORT
     23 #include <soc/tomahawk2.h>
     24 #endif /* BCM_TOMAHAWK2_SUPPORT */
     25 #ifdef BCM_TOMAHAWK3_SUPPORT
     26 #include <soc/tomahawk3.h>
     27 #endif /* BCM_TOMAHAWK3_SUPPORT */
     28 #ifdef BCM_DFE_SUPPORT
     29 #include <soc/dfe/cmn/dfe_drv.h>
     30 #endif /*BCM_DFE_SUPPORT*/
     31 #define _MAP_REG_MASK_SUBSETS(unit, i, count, arr) \
     32     for (i = 0; i < count; i++) {\
     33         *arr[i] = SOC_REG_MASK_SUBSET(unit)[i];\
     34     }
     35 
     36 #define _INIT_REG_MASK_SUBSETS(unit, i, count, arr) \
     37     SOC_REG_MASK_SUBSET(unit) = sal_alloc(count * sizeof(pbmp_t *),\
     38                                           "per unit reg mask subsets");\
     39     if (NULL == SOC_REG_MASK_SUBSET(unit)) {\
     40         return SOC_E_MEMORY;\
     41     }\
     42     sal_memset(SOC_REG_MASK_SUBSET(unit), 0, count * sizeof(pbmp_t *));\
     43     for (i = 0; i < count; i++) {\
     44         SOC_REG_MASK_SUBSET(unit)[i] = sal_alloc(sizeof(pbmp_t),\
     45                                                  "reg mask subsets");\
     46         if (NULL == SOC_REG_MASK_SUBSET(unit)[i]) {\
     47             return SOC_E_MEMORY;\
     48         }\
     49         *mask_map_arr[i] = SOC_REG_MASK_SUBSET(unit)[i];\
     50     }
     51 
     52 #define CHECK_FEATURE_BLK(feat, blk) \
     53     (SOC_REG_BLOCK_IS(unit, ainfo->reg, blk) && \
     54     (!soc_feature(unit, feat)))
     55 
     56 /*
     57  * Description:
     58  *  There are many per-port registers in Triumph which only exist on
     59  *  a subset of ports as described by PORTLIST and PERPORT_MASKBITS
     60  *  attributes in the regsfile. There are also several indexed registers
     61  *  with different number of elements depending on the port as described
     62  *  by the NUMELS_PERPORT attribute. These routines identify whether
     63  *  a register should be skipped for a given port/cos index. These routines 
     64  *  also adjust the mask for these special registers so unimplemented
     65  *  bits get skipped during register tests. 
     66  */
     67 
     68 
     69 
     70 #ifdef BCM_TRIUMPH_SUPPORT
     71 STATIC int
     72 reg_mask_subset_tr(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
     73 {
     74     pbmp_t *tr_8pg_ports;
     75     pbmp_t *tr_higig_ports;
     76     pbmp_t *tr_24q_ports;
     77     pbmp_t *tr_non_cpu_ports;
     78     pbmp_t *tr_all_ports;
     79 #define _REG_MASK_SUBSET_MAX_TR 5
     80     pbmp_t **mask_map_arr[_REG_MASK_SUBSET_MAX_TR];
     81     int i, count = _REG_MASK_SUBSET_MAX_TR;
     82     uint64 temp_mask;
     83     pbmp_t *pbmp;
     84 
     85     mask_map_arr[0] = &tr_8pg_ports;
     86     mask_map_arr[1] = &tr_higig_ports;
     87     mask_map_arr[2] = &tr_24q_ports;
     88     mask_map_arr[3] = &tr_non_cpu_ports;
     89     mask_map_arr[4] = &tr_all_ports;
     90     if (NULL == SOC_REG_MASK_SUBSET(unit)) {
     91         _INIT_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
     92         
     93         /* 8PG_PORTS = [2,14,26..31] */
     94         SOC_PBMP_CLEAR(*tr_8pg_ports);
     95         if (IS_XE_PORT(unit, 2) || IS_HG_PORT(unit, 2)) {
     96             SOC_PBMP_PORT_ADD(*tr_8pg_ports, 2);
     97         }
     98         if (IS_XE_PORT(unit, 14) || IS_HG_PORT(unit, 14)) {
     99             SOC_PBMP_PORT_ADD(*tr_8pg_ports, 14);
    100         }
    101         if (IS_XE_PORT(unit, 26) || IS_HG_PORT(unit, 26)) {
    102             SOC_PBMP_PORT_ADD(*tr_8pg_ports, 26);
    103         }
    104         if (IS_XE_PORT(unit, 27) || IS_HG_PORT(unit, 27)) {
    105             SOC_PBMP_PORT_ADD(*tr_8pg_ports, 27);
    106         }
    107         SOC_PBMP_PORT_ADD(*tr_8pg_ports, 28);
    108         SOC_PBMP_PORT_ADD(*tr_8pg_ports, 29);
    109         SOC_PBMP_PORT_ADD(*tr_8pg_ports, 30); 
    110         SOC_PBMP_PORT_ADD(*tr_8pg_ports, 31);
    111 
    112         /* Higig ports [0,2,14,26,27,28,29,30,31] */
    113         SOC_PBMP_CLEAR(*tr_higig_ports);
    114         SOC_PBMP_PORT_ADD(*tr_higig_ports, 0);
    115         SOC_PBMP_PORT_ADD(*tr_higig_ports, 2);
    116         SOC_PBMP_PORT_ADD(*tr_higig_ports, 14);
    117         SOC_PBMP_PORT_ADD(*tr_higig_ports, 26);
    118         SOC_PBMP_PORT_ADD(*tr_higig_ports, 27);
    119         SOC_PBMP_PORT_ADD(*tr_higig_ports, 28);
    120         SOC_PBMP_PORT_ADD(*tr_higig_ports, 29);
    121         SOC_PBMP_PORT_ADD(*tr_higig_ports, 30);
    122         SOC_PBMP_PORT_ADD(*tr_higig_ports, 31);
    123 
    124         /*  24Q_PORTS = [2,3,14,15,26..32,43] */
    125         SOC_PBMP_CLEAR(*tr_24q_ports);
    126         SOC_PBMP_PORT_ADD(*tr_24q_ports, 2);
    127         SOC_PBMP_PORT_ADD(*tr_24q_ports, 3);
    128         SOC_PBMP_PORT_ADD(*tr_24q_ports, 14);
    129         SOC_PBMP_PORT_ADD(*tr_24q_ports, 15);
    130         SOC_PBMP_PORT_ADD(*tr_24q_ports, 26);
    131         SOC_PBMP_PORT_ADD(*tr_24q_ports, 27);
    132         SOC_PBMP_PORT_ADD(*tr_24q_ports, 28);
    133         SOC_PBMP_PORT_ADD(*tr_24q_ports, 29);
    134         SOC_PBMP_PORT_ADD(*tr_24q_ports, 30);
    135         SOC_PBMP_PORT_ADD(*tr_24q_ports, 31);
    136         SOC_PBMP_PORT_ADD(*tr_24q_ports, 32);
    137         SOC_PBMP_PORT_ADD(*tr_24q_ports, 43);
    138 
    139         /* all port except CMIC */
    140         SOC_PBMP_CLEAR(*tr_non_cpu_ports);
    141         SOC_PBMP_ASSIGN(*tr_non_cpu_ports, PBMP_ALL(unit));
    142         SOC_PBMP_PORT_REMOVE(*tr_non_cpu_ports, 0);
    143  
    144         /* All ports */
    145         SOC_PBMP_CLEAR(*tr_all_ports); 
    146         SOC_PBMP_ASSIGN(*tr_all_ports, PBMP_ALL(unit)); 
    147     }
    148     if (!SOC_PORT_VALID(unit, ainfo->port)) {
    149         return 0;
    150     }
    151     _MAP_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
    152  
    153     switch(ainfo->reg) {
    154         case MAC_CTRLr:
    155         case MAC_XGXS_CTRLr:
    156         case MAC_XGXS_STATr:
    157         case MAC_TXMUXCTRLr:
    158         case MAC_CNTMAXSZr:
    159         case MAC_CORESPARE0r:
    160         case MAC_TXCTRLr:
    161         case MAC_TXMACSAr:
    162         case MAC_TXMAXSZr:
    163         case MAC_TXPSETHRr:
    164         case MAC_TXSPARE0r:
    165         case ITPOKr:
    166         case ITXPFr: 
    167         case ITFCSr:
    168         case ITUCr:
    169         case ITMCAr:
    170         case ITBCAr:
    171         case ITOVRr:
    172         case ITFRGr:
    173         case ITPKTr:
    174         case IT64r:
    175         case IT127r:
    176         case IT255r:
    177         case IT511r:
    178         case IT1023r:
    179         case IT1518r:
    180         case IT2047r:
    181         case IT4095r:
    182         case IT9216r:
    183         case IT16383r:
    184         case ITMAXr:
    185         case ITUFLr:
    186         case ITERRr:
    187         case ITBYTr:
    188         case MAC_RXCTRLr:
    189         case MAC_RXMACSAr:
    190         case MAC_RXMAXSZr:
    191         case MAC_RXLSSCTRLr:
    192         case MAC_RXLSSSTATr:
    193         case MAC_RXSPARE0r:
    194         case IR64r:
    195         case IR127r:
    196         case IR255r:
    197         case IR511r:
    198         case IR1023r:
    199         case IR1518r:
    200         case IR2047r:
    201         case IR4095r:
    202         case IR9216r:
    203         case IR16383r:
    204         case IRMAXr:
    205         case IRPKTr:
    206         case IRFCSr:
    207         case IRUCr:
    208         case IRMCAr:
    209         case IRBCAr:
    210         case IRXCFr:
    211         case IRXPFr:
    212         case IRXUOr:
    213         case IRJBRr:
    214         case IROVRr:
    215         case IRFLRr:
    216         case IRPOKr:
    217         case IRMEGr:
    218         case IRMEBr:
    219         case IRBYTr:
    220         case IRUNDr:
    221         case IRFRGr:
    222         case IRERBYTr:
    223         case IRERPKTr:
    224         case IRJUNKr:
    225         case MAC_TXLLFCCTRLr:
    226         case MAC_TXLLFCMSGFLDSr:
    227         case MAC_RXLLFCMSGFLDSr:
    228         case MAC_RXLLFCMSGCNTr:
    229             if (IS_GE_PORT(unit, ainfo->port)) {
    230                 goto skip;
    231             }
    232             break;
    233         default:
    234             break;
    235     }
    236 
    237     switch(ainfo->reg) {
    238         case IE2E_CONTROLr:
    239         case ING_MODMAP_CTRLr:
    240         case IHG_LOOKUPr:
    241         case ICONTROL_OPCODE_BITMAPr:
    242         case UNKNOWN_HGI_BITMAPr:
    243         case IUNHGIr:
    244         case ICTRLr:
    245         case IBCASTr:
    246         case ILTOMCr:
    247         case IIPMCr:
    248         case IUNKOPCr:
    249             pbmp = tr_higig_ports;
    250             break;
    251         case PG_THRESH_SELr:
    252         case PORT_PRI_GRP0r:
    253         case PORT_PRI_GRP1r:
    254         case PORT_PRI_XON_ENABLEr:
    255             pbmp = tr_8pg_ports;
    256             break;
    257         case ECN_CONFIGr:
    258         case HOL_STAT_PORTr:
    259         case PORT_WREDPARAM_CELLr:
    260         case PORT_WREDPARAM_YELLOW_CELLr:
    261         case PORT_WREDPARAM_RED_CELLr:
    262         case PORT_WREDPARAM_NONTCP_CELLr:
    263         case PORT_WREDCONFIG_CELLr:
    264         case PORT_WREDAVGQSIZE_CELLr:
    265         case PORT_WREDPARAM_PACKETr:
    266         case PORT_WREDPARAM_YELLOW_PACKETr:
    267         case PORT_WREDPARAM_RED_PACKETr:
    268         case PORT_WREDPARAM_NONTCP_PACKETr:
    269         case PORT_WREDCONFIG_PACKETr:
    270         case PORT_WREDAVGQSIZE_PACKETr:
    271         case ESCONFIGr:
    272         case COSMASKr:
    273         case MINSPCONFIGr:
    274             pbmp = tr_non_cpu_ports;
    275             break;
    276         /* ING_PORTS_24Q */
    277         case ING_COS_MODEr:
    278         /* MMU_24Q_PORTS */
    279         case COS_MODEr:
    280         case S1V_CONFIGr:
    281         case S1V_COSWEIGHTSr:
    282         case S1V_COSMASKr:
    283         case S1V_MINSPCONFIGr:
    284         case S1V_WDRRCOUNTr:
    285             pbmp = tr_24q_ports;
    286             break;
    287         /* MMU_PERPORTPERCOS_REGS */
    288         case OP_QUEUE_CONFIG_CELLr:
    289         case OP_QUEUE_CONFIG1_CELLr:
    290         case OP_QUEUE_CONFIG_PACKETr:
    291         case OP_QUEUE_CONFIG1_PACKETr:
    292         case OP_QUEUE_LIMIT_YELLOW_CELLr:
    293         case OP_QUEUE_LIMIT_YELLOW_PACKETr:
    294         case OP_QUEUE_LIMIT_RED_CELLr:
    295         case OP_QUEUE_LIMIT_RED_PACKETr:
    296         case OP_QUEUE_RESET_OFFSET_CELLr:
    297         case OP_QUEUE_RESET_OFFSET_PACKETr:
    298         case OP_QUEUE_MIN_COUNT_CELLr:
    299         case OP_QUEUE_MIN_COUNT_PACKETr:
    300         case OP_QUEUE_SHARED_COUNT_CELLr:
    301         case OP_QUEUE_SHARED_COUNT_PACKETr:
    302         case OP_QUEUE_TOTAL_COUNT_CELLr:
    303         case OP_QUEUE_TOTAL_COUNT_PACKETr:
    304         case OP_QUEUE_RESET_VALUE_CELLr:
    305         case OP_QUEUE_RESET_VALUE_PACKETr:
    306         case DROP_PKT_CNTr:
    307         case DROP_BYTE_CNTr:
    308             if (ainfo->port == 0) {
    309                 return 0;
    310             } else if (ainfo->idx < 8) {
    311                 pbmp = tr_all_ports;
    312             } else if (ainfo->idx < 24) {
    313                 pbmp = tr_24q_ports;
    314             } else {
    315                 goto skip;
    316             }
    317             break;
    318         /* MMU_PERPORTPERCOS_NOCPU_REGS */
    319         case WREDPARAM_CELLr:
    320         case WREDPARAM_YELLOW_CELLr:
    321         case WREDPARAM_RED_CELLr:
    322         case WREDPARAM_NONTCP_CELLr:
    323         case WREDCONFIG_CELLr:
    324         case WREDAVGQSIZE_CELLr:
    325         case WREDPARAM_PACKETr:
    326         case WREDPARAM_YELLOW_PACKETr:
    327         case WREDPARAM_RED_PACKETr:
    328         case WREDPARAM_NONTCP_PACKETr:
    329         case WREDCONFIG_PACKETr:
    330         case WREDAVGQSIZE_PACKETr:
    331         /* MMU_MTRO_REGS */
    332         case MINBUCKETCONFIG_64r:
    333         case MINBUCKETr:
    334         case MAXBUCKETCONFIG_64r:
    335         case MAXBUCKETr:
    336         /* MMU_ES_REGS */
    337         case COSWEIGHTSr:
    338         case WDRRCOUNTr:
    339             if (ainfo->port == 0) {
    340                 goto skip;
    341             } else if (ainfo->idx < 8) {
    342                 pbmp = tr_all_ports;
    343             } else {
    344                 pbmp = tr_24q_ports;
    345             }
    346             break;
    347         /* MMU_PERPORTPERPRI_REGS */
    348         case PG_RESET_OFFSET_CELLr:
    349         case PG_RESET_OFFSET_PACKETr:
    350         case PG_RESET_FLOOR_CELLr:
    351         case PG_MIN_CELLr:
    352         case PG_MIN_PACKETr:
    353         case PG_HDRM_LIMIT_CELLr:
    354         case PG_HDRM_LIMIT_PACKETr:
    355         case PG_COUNT_CELLr:
    356         case PG_COUNT_PACKETr:
    357         case PG_MIN_COUNT_CELLr:
    358         case PG_MIN_COUNT_PACKETr:
    359         case PG_PORT_MIN_COUNT_CELLr:
    360         case PG_PORT_MIN_COUNT_PACKETr:
    361         case PG_SHARED_COUNT_CELLr:
    362         case PG_SHARED_COUNT_PACKETr:
    363         case PG_HDRM_COUNT_CELLr:
    364         case PG_HDRM_COUNT_PACKETr:
    365         case PG_GBL_HDRM_COUNTr:
    366         case PG_RESET_VALUE_CELLr:
    367         case PG_RESET_VALUE_PACKETr:
    368             if (ainfo->idx == 0) {
    369                 pbmp = tr_all_ports;
    370             } else {
    371                 pbmp = tr_8pg_ports;
    372             }
    373             break;
    374         default:
    375             pbmp = tr_all_ports;
    376             break; 
    377     }
    378 
    379     if (!SOC_PBMP_MEMBER(*pbmp, ainfo->port)) {
    380         goto skip; 
    381     }
    382 
    383     if (mask != NULL) {
    384         switch(ainfo->reg) {
    385             case HOL_STAT_PORTr:
    386             case ECN_CONFIGr:
    387                 if (!SOC_PBMP_MEMBER(*tr_24q_ports, ainfo->port)) {
    388                     /* adjust mask for ports without 24 queues */
    389                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
    390                     COMPILER_64_AND(*mask, temp_mask);
    391                 }
    392                 break;
    393             case TOQ_QUEUESTAT_64r:
    394             case TOQ_ACTIVATEQ_64r:
    395             case TOQEMPTY_64r:
    396             case DEQ_AGINGMASK_64r:
    397                 if (SOC_PBMP_MEMBER(*tr_24q_ports, ainfo->port)) {
    398                     /* adjust mask for ports with 24 queues */
    399                     COMPILER_64_SET(temp_mask, 0, 0x00ffffff);
    400                     COMPILER_64_AND(*mask, temp_mask);
    401                 } else if (ainfo->port != 0) {
    402                     /* remaining ports only have 8 queues */
    403                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
    404                     COMPILER_64_AND(*mask, temp_mask);
    405                 }
    406                 break;
    407         }
    408     }
    409     return 0; 
    410 skip:
    411     /* set mask to all 0's so test will skip it */
    412     if (mask != NULL) {
    413         COMPILER_64_SET(*mask, 0, 0);
    414     }
    415     return 1;
    416 }
    417 #endif /* BCM_TRIUMPH_SUPPORT */
    418 
    419 #ifdef BCM_SHADOW_SUPPORT
    420 STATIC int
    421 reg_mask_subset_sh(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
    422 {
    423     pbmp_t *sh_non_cpu_ports;
    424     pbmp_t *sh_non_il_non_cpu_ports;
    425     pbmp_t *sh_port_link_ports;
    426     pbmp_t *sh_il_ports;
    427     pbmp_t *sh_all_ports;
    428 #define _REG_MASK_SUBSET_MAX_SH 5
    429     pbmp_t **mask_map_arr[_REG_MASK_SUBSET_MAX_SH];
    430     int i, count = _REG_MASK_SUBSET_MAX_SH;
    431     pbmp_t *pbmp;
    432 
    433     mask_map_arr[0] = &sh_non_cpu_ports;
    434     mask_map_arr[1] = &sh_non_il_non_cpu_ports;
    435     mask_map_arr[2] = &sh_port_link_ports;
    436     mask_map_arr[3] = &sh_il_ports;
    437     mask_map_arr[4] = &sh_all_ports;
    438     if (NULL == SOC_REG_MASK_SUBSET(unit)) {
    439         _INIT_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
    440         
    441         /* all port except CMIC */
    442         SOC_PBMP_CLEAR(*sh_non_cpu_ports);
    443         SOC_PBMP_ASSIGN(*sh_non_cpu_ports, PBMP_ALL(unit));
    444         SOC_PBMP_PORT_REMOVE(*sh_non_cpu_ports, 0);
    445 
    446         /* All ports except Interlaken and CPU */
    447         SOC_PBMP_CLEAR(*sh_non_il_non_cpu_ports);
    448         SOC_PBMP_ASSIGN(*sh_non_il_non_cpu_ports, PBMP_PORT_ALL(unit));
    449         SOC_PBMP_REMOVE(*sh_non_il_non_cpu_ports, PBMP_IL_ALL(unit));
    450 
    451         /* All port link ports */
    452         SOC_PBMP_CLEAR(*sh_port_link_ports);
    453         SOC_PBMP_ASSIGN(*sh_port_link_ports, PBMP_ALL(unit));
    454         SOC_PBMP_PORT_REMOVE(*sh_port_link_ports, 0);
    455         SOC_PBMP_WORD_SET(*sh_port_link_ports, 0, 
    456                           (SOC_PBMP_WORD_GET(*sh_port_link_ports, 0) & 0x1ff));
    457 
    458         /* All Interlaken ports */
    459         SOC_PBMP_CLEAR(*sh_il_ports);
    460         SOC_PBMP_ASSIGN(*sh_il_ports, PBMP_PORT_ALL(unit));
    461         SOC_PBMP_REMOVE(*sh_il_ports, *sh_port_link_ports);
    462 
    463         /* All ports */
    464         SOC_PBMP_CLEAR(*sh_all_ports);
    465         SOC_PBMP_ASSIGN(*sh_all_ports, PBMP_ALL(unit));
    466     }
    467     if (!SOC_PORT_VALID(unit, ainfo->port)) {
    468         return 0;
    469     }
    470     _MAP_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
    471 
    472     switch(ainfo->reg) {
    473         case BUCKET_ECCr:
    474         case CONFIG_ECCr:
    475         case HOL_STAT_PORTr:
    476         case TOQ_QUEUESTATr:
    477         case TOQ_ACTIVATEQr:
    478         case TOQEMPTYr:
    479         case ECN_CONFIGr:
    480         case ES_PORTGRP_WDRR_WEIGHTSr:
    481         case MTRO_SHAPE_MINMASKr:
    482         case MMU_TO_XLP_BKP_STATUSr:
    483         case XLP_TO_MMU_BKP_STATUSr:
    484         case PORT_WREDPARAM_CELLr:
    485         case PORT_WREDPARAM_YELLOW_CELLr:
    486         case PORT_WREDPARAM_RED_CELLr:
    487         case PORT_WREDPARAM_NONTCP_CELLr:
    488         case PORT_WREDCONFIG_CELLr:
    489         case PORT_WREDAVGQSIZE_CELLr:
    490         case PORT_LB_WREDAVGQSIZE_CELLr:
    491         case PORT_WREDCONFIG_ECCPr:
    492         case PORT_WREDPARAM_END_CELLr:
    493         case PORT_WREDPARAM_PRI0_END_CELLr:
    494         case PORT_WREDPARAM_PRI0_START_CELLr:
    495         case PORT_WREDPARAM_RED_END_CELLr:
    496         case PORT_WREDPARAM_RED_START_CELLr:
    497         case PORT_WREDPARAM_START_CELLr:
    498         case PORT_WREDPARAM_YELLOW_END_CELLr:
    499         case PORT_WREDPARAM_YELLOW_START_CELLr:
    500         case PORT_WRED_THD_0_ECCPr:
    501         case PORT_WRED_THD_1_ECCPr:
    502         case WREDPARAM_CELLr:
    503         case WREDPARAM_YELLOW_CELLr:
    504         case WREDPARAM_RED_CELLr:
    505         case WREDPARAM_NONTCP_CELLr:
    506         case WREDCONFIG_CELLr:
    507         case WREDAVGQSIZE_CELLr:
    508         case WREDPARAM_END_CELLr:
    509         case WREDPARAM_PRI0_END_CELLr:
    510         case WREDPARAM_PRI0_START_CELLr:
    511         case WREDPARAM_RED_END_CELLr:
    512         case WREDPARAM_RED_START_CELLr:
    513         case WREDPARAM_START_CELLr:
    514         case WREDPARAM_YELLOW_END_CELLr:
    515         case WREDPARAM_YELLOW_START_CELLr:
    516         case WREDCONFIG_ECCPr:
    517         case WRED_DEBUG_ENQ_DROP_PORTr:
    518         case WRED_THD_0_ECCPr:
    519         case WRED_THD_1_ECCPr:
    520         case COSWEIGHTSr:
    521         case MINSPCONFIGr:
    522         case WDRRCOUNTr:
    523         case MINBUCKETCONFIGr:
    524         case MINBUCKETCONFIG1r:
    525         case MINBUCKETr:
    526         case MAXBUCKETCONFIGr:
    527         case MAXBUCKETCONFIG1r:
    528         case MAXBUCKETr:
    529         case MMU_TO_XPORT_BKPr:
    530         case DEQ_AGINGMASKr:
    531         case MMU_LLFC_RX_CONFIGr:
    532         case XPORT_TO_MMU_BKPr:
    533         case UNIMAC_PFC_CTRLr:
    534         case MAC_PFC_REFRESH_CTRLr:
    535         case MAC_PFC_TYPEr:
    536         case MAC_PFC_OPCODEr:
    537         case MAC_PFC_DA_0r:
    538         case MAC_PFC_DA_1r:
    539         case MACSEC_PROG_TX_CRCr:
    540         case MACSEC_CNTRLr:
    541         case TS_STATUS_CNTRLr:
    542         case TX_TS_DATAr:
    543         case BMAC_PFC_CTRLr:
    544         case BMAC_PFC_TYPEr:
    545         case BMAC_PFC_OPCODEr:
    546         case BMAC_PFC_DA_LOr:
    547         case BMAC_PFC_DA_HIr:
    548         case BMAC_PFC_COS0_XOFF_CNTr:
    549         case BMAC_PFC_COS1_XOFF_CNTr:
    550         case BMAC_PFC_COS2_XOFF_CNTr:
    551         case BMAC_PFC_COS3_XOFF_CNTr:
    552         case BMAC_PFC_COS4_XOFF_CNTr:
    553         case BMAC_PFC_COS5_XOFF_CNTr:
    554         case BMAC_PFC_COS6_XOFF_CNTr:
    555         case BMAC_PFC_COS7_XOFF_CNTr:
    556         case BMAC_PFC_COS8_XOFF_CNTr:
    557         case BMAC_PFC_COS9_XOFF_CNTr:
    558         case BMAC_PFC_COS10_XOFF_CNTr:
    559         case BMAC_PFC_COS11_XOFF_CNTr:
    560         case BMAC_PFC_COS12_XOFF_CNTr:
    561         case BMAC_PFC_COS13_XOFF_CNTr:
    562         case BMAC_PFC_COS14_XOFF_CNTr:
    563         case BMAC_PFC_COS15_XOFF_CNTr:
    564         case PFC_COS0_XOFF_CNTr:
    565         case PFC_COS1_XOFF_CNTr:
    566         case PFC_COS2_XOFF_CNTr:
    567         case PFC_COS3_XOFF_CNTr:
    568         case PFC_COS4_XOFF_CNTr:
    569         case PFC_COS5_XOFF_CNTr:
    570         case PFC_COS6_XOFF_CNTr:
    571         case PFC_COS7_XOFF_CNTr:
    572         case PFC_COS8_XOFF_CNTr:
    573         case PFC_COS9_XOFF_CNTr:
    574         case PFC_COS10_XOFF_CNTr:
    575         case PFC_COS11_XOFF_CNTr:
    576         case PFC_COS12_XOFF_CNTr:
    577         case PFC_COS13_XOFF_CNTr:
    578         case PFC_COS14_XOFF_CNTr:
    579         case PFC_COS15_XOFF_CNTr:
    580             pbmp = sh_non_cpu_ports;
    581             break;
    582         default:
    583             pbmp = sh_all_ports;
    584             break;
    585     }
    586 
    587     switch(ainfo->reg) {
    588         /* EP_PERPORTPERCOS_REGS */
    589         case EGR_PERQ_XMT_COUNTERSr:
    590         /* MMU_PERPORTPERCOS_REGS */
    591         case OP_QUEUE_CONFIGr:
    592         case OP_QUEUE_RESET_OFFSETr:
    593         case OP_QUEUE_MIN_COUNTr:
    594         case OP_QUEUE_SHARED_COUNTr:
    595         case OP_QUEUE_TOTAL_COUNTr:
    596         case OP_QUEUE_RESET_VALUEr:
    597         case OP_QUEUE_LIMIT_YELLOWr:
    598         case OP_QUEUE_LIMIT_REDr:
    599         case HOLDROP_PKT_CNTr:
    600             if (ainfo->port == 0) {
    601                 return 0;
    602             } else if (ainfo->idx < 10) { 
    603                 pbmp = sh_all_ports;
    604             } else {
    605                 goto skip;
    606             }
    607             break;
    608         default:
    609             break;
    610     }
    611 
    612     if (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_XLPORT)) {
    613         pbmp = sh_non_il_non_cpu_ports;
    614     } else if ((SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_MS_ISEC)) ||
    615                (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_MS_ESEC))) { 
    616         pbmp = sh_port_link_ports;
    617     } else if (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_IL)) {
    618         pbmp = sh_il_ports;
    619     }
    620 
    621     if (!SOC_PBMP_MEMBER(*pbmp, ainfo->port)) {
    622         goto skip;
    623     }
    624     return 0;
    625 
    626 skip:
    627     /* set mask to all 0's so test will skip it */
    628     if (mask != NULL) {
    629         COMPILER_64_SET(*mask, 0, 0);
    630     }
    631     return 1;
    632 }
    633 #endif /* BCM_SHADOW_SUPPORT */
    634 
    635 #ifdef BCM_SCORPION_SUPPORT
    636 STATIC int
    637 reg_mask_subset_sc(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
    638 {
    639     pbmp_t *sc_no_ports;
    640     pbmp_t *sc_xports;
    641     pbmp_t *sc_non_cpu_ports;
    642     pbmp_t *sc_all_ports;
    643 #define _REG_MASK_SUBSET_MAX_SC 4
    644     pbmp_t **mask_map_arr[_REG_MASK_SUBSET_MAX_SC];
    645     int i, count = _REG_MASK_SUBSET_MAX_SC;
    646     pbmp_t *pbmp;
    647 
    648     mask_map_arr[0] = &sc_no_ports;
    649     mask_map_arr[1] = &sc_xports;
    650     mask_map_arr[2] = &sc_non_cpu_ports;
    651     mask_map_arr[3] = &sc_all_ports;
    652     if (NULL == SOC_REG_MASK_SUBSET(unit)) {
    653         _INIT_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
    654         
    655         /* all port except CMIC */
    656         SOC_PBMP_CLEAR(*sc_non_cpu_ports);
    657         SOC_PBMP_ASSIGN(*sc_non_cpu_ports, PBMP_ALL(unit));
    658         SOC_PBMP_PORT_REMOVE(*sc_non_cpu_ports, 0);
    659 
    660         SOC_PBMP_CLEAR(*sc_xports);
    661         SOC_PBMP_ASSIGN(*sc_xports, PBMP_GX_ALL(unit));
    662         SOC_PBMP_PORT_REMOVE(*sc_xports, 0);
    663 
    664         /* All ports */
    665         SOC_PBMP_CLEAR(*sc_all_ports);
    666         SOC_PBMP_ASSIGN(*sc_all_ports, PBMP_ALL(unit));
    667 
    668         /* No ports */
    669         SOC_PBMP_CLEAR(*sc_no_ports);
    670     }
    671     if (!SOC_PORT_VALID(unit, ainfo->port)) {
    672         return 0;
    673     }
    674     _MAP_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
    675 
    676     switch(ainfo->reg) {
    677         case HOL_STAT_PORTr:
    678         case TOQ_QUEUESTATr:
    679         case TOQ_ACTIVATEQr:
    680         case TOQEMPTYr:
    681         case ECN_CONFIGr:
    682         case PORT_WREDPARAM_CELLr:
    683         case PORT_WREDPARAM_YELLOW_CELLr:
    684         case PORT_WREDPARAM_RED_CELLr:
    685         case PORT_WREDPARAM_NONTCP_CELLr:
    686         case PORT_WREDCONFIG_CELLr:
    687         case PORT_WREDAVGQSIZE_CELLr:
    688         case WREDPARAM_CELLr:
    689         case WREDPARAM_YELLOW_CELLr:
    690         case WREDPARAM_RED_CELLr:
    691         case WREDPARAM_NONTCP_CELLr:
    692         case WREDCONFIG_CELLr:
    693         case WREDAVGQSIZE_CELLr:
    694         case COSWEIGHTSr:
    695         case MINSPCONFIGr:
    696         case WDRRCOUNTr:
    697         case MINBUCKETCONFIGr:
    698         case MINBUCKETCONFIG1r:
    699         case MINBUCKETr:
    700         case MAXBUCKETCONFIGr:
    701         case MAXBUCKETCONFIG1r:
    702         case MAXBUCKETr:
    703         case MMU_TO_XPORT_BKPr:
    704         case DEQ_AGINGMASKr:
    705             pbmp = sc_non_cpu_ports;
    706             break;
    707         case MMU_LLFC_RX_CONFIGr:
    708         case XPORT_TO_MMU_BKPr:
    709             pbmp = sc_xports;
    710             break;
    711         case UNIMAC_PFC_CTRLr:
    712         case MAC_PFC_REFRESH_CTRLr:
    713         case MAC_PFC_TYPEr:
    714         case MAC_PFC_OPCODEr:
    715         case MAC_PFC_DA_0r:
    716         case MAC_PFC_DA_1r:
    717         case MACSEC_PROG_TX_CRCr:
    718         case MACSEC_CNTRLr:
    719         case TS_STATUS_CNTRLr:
    720         case TX_TS_DATAr:
    721             if (soc_feature(unit, soc_feature_priority_flow_control)) {
    722                 pbmp = sc_non_cpu_ports;
    723             } else {
    724                 pbmp = sc_no_ports;
    725             }
    726             break;
    727         case BMAC_PFC_CTRLr:
    728         case BMAC_PFC_TYPEr:
    729         case BMAC_PFC_OPCODEr:
    730         case BMAC_PFC_DA_LOr:
    731         case BMAC_PFC_DA_HIr:
    732         case BMAC_PFC_COS0_XOFF_CNTr:
    733         case BMAC_PFC_COS1_XOFF_CNTr:
    734         case BMAC_PFC_COS2_XOFF_CNTr:
    735         case BMAC_PFC_COS3_XOFF_CNTr:
    736         case BMAC_PFC_COS4_XOFF_CNTr:
    737         case BMAC_PFC_COS5_XOFF_CNTr:
    738         case BMAC_PFC_COS6_XOFF_CNTr:
    739         case BMAC_PFC_COS7_XOFF_CNTr:
    740         case BMAC_PFC_COS8_XOFF_CNTr:
    741         case BMAC_PFC_COS9_XOFF_CNTr:
    742         case BMAC_PFC_COS10_XOFF_CNTr:
    743         case BMAC_PFC_COS11_XOFF_CNTr:
    744         case BMAC_PFC_COS12_XOFF_CNTr:
    745         case BMAC_PFC_COS13_XOFF_CNTr:
    746         case BMAC_PFC_COS14_XOFF_CNTr:
    747         case BMAC_PFC_COS15_XOFF_CNTr:
    748         case PFC_COS0_XOFF_CNTr:
    749         case PFC_COS1_XOFF_CNTr:
    750         case PFC_COS2_XOFF_CNTr:
    751         case PFC_COS3_XOFF_CNTr:
    752         case PFC_COS4_XOFF_CNTr:
    753         case PFC_COS5_XOFF_CNTr:
    754         case PFC_COS6_XOFF_CNTr:
    755         case PFC_COS7_XOFF_CNTr:
    756         case PFC_COS8_XOFF_CNTr:
    757         case PFC_COS9_XOFF_CNTr:
    758         case PFC_COS10_XOFF_CNTr:
    759         case PFC_COS11_XOFF_CNTr:
    760         case PFC_COS12_XOFF_CNTr:
    761         case PFC_COS13_XOFF_CNTr:
    762         case PFC_COS14_XOFF_CNTr:
    763         case PFC_COS15_XOFF_CNTr:
    764             if (soc_feature(unit, soc_feature_priority_flow_control)) {
    765                 pbmp = sc_xports;
    766             } else {
    767                 pbmp = sc_no_ports;
    768             }
    769             break;
    770         default:
    771             pbmp = sc_all_ports;
    772             break;
    773     }
    774 
    775     switch(ainfo->reg) {
    776         /* EP_PERPORTPERCOS_REGS */
    777         case EGR_PERQ_XMT_COUNTERSr:
    778         /* MMU_PERPORTPERCOS_REGS */
    779         case OP_QUEUE_CONFIGr:
    780         case OP_QUEUE_RESET_OFFSETr:
    781         case OP_QUEUE_MIN_COUNTr:
    782         case OP_QUEUE_SHARED_COUNTr:
    783         case OP_QUEUE_TOTAL_COUNTr:
    784         case OP_QUEUE_RESET_VALUEr:
    785         case OP_QUEUE_LIMIT_YELLOWr:
    786         case OP_QUEUE_LIMIT_REDr:
    787         case HOLDROP_PKT_CNTr:
    788             if (ainfo->port == 0) {
    789                 return 0;
    790             } else if (ainfo->idx < 10) { 
    791                 pbmp = sc_all_ports;
    792             } else {
    793                 goto skip;
    794             }
    795             break;
    796         default:
    797             break;
    798     }
    799     
    800     if (!SOC_PBMP_MEMBER(*pbmp, ainfo->port)) {
    801         goto skip;
    802     }
    803     return 0;
    804 
    805 skip:
    806     /* set mask to all 0's so test will skip it */
    807     if (mask != NULL) {
    808         COMPILER_64_SET(*mask, 0, 0);
    809     }
    810     return 1;
    811 }
    812 #endif /* BCM_SCORPION_SUPPORT */
    813 
    814 #ifdef BCM_TRIUMPH2_SUPPORT
    815 STATIC int
    816 reg_mask_subset_tr2(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
    817 {
    818     pbmp_t *ch_2pg_ports;
    819     pbmp_t *ch_8pg_ports;
    820     pbmp_t *ch_24q_ports;
    821     pbmp_t *ch_24q_ports_with_cpu;
    822     pbmp_t *ch_ext_ports;
    823     pbmp_t *ch_non_cpu_ports;
    824     pbmp_t *ch_all_ports;
    825     pbmp_t *ch_lb_ports;
    826     pbmp_t *ch_all_ports_with_mmu;
    827     pbmp_t *ch_gxports;
    828     pbmp_t *ch_cmic;
    829 #define _REG_MASK_SUBSET_MAX_TR2 11
    830     pbmp_t **mask_map_arr[_REG_MASK_SUBSET_MAX_TR2];
    831     int i, count = _REG_MASK_SUBSET_MAX_TR2;
    832     uint64 temp_mask;
    833     pbmp_t *pbmp;
    834 
    835     mask_map_arr[0] = &ch_2pg_ports;
    836     mask_map_arr[1] = &ch_8pg_ports;
    837     mask_map_arr[2] = &ch_24q_ports;
    838     mask_map_arr[3] = &ch_24q_ports_with_cpu;
    839     mask_map_arr[4] = &ch_ext_ports;
    840     mask_map_arr[5] = &ch_non_cpu_ports;
    841     mask_map_arr[6] = &ch_all_ports;
    842     mask_map_arr[7] = &ch_lb_ports;
    843     mask_map_arr[8] = &ch_all_ports_with_mmu;
    844     mask_map_arr[9] = &ch_gxports;
    845     mask_map_arr[10] = &ch_cmic;
    846     if (NULL == SOC_REG_MASK_SUBSET(unit)) {
    847         _INIT_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
    848 
    849         /* 8PG_PORTS = [26..30,34,38,42,46,50,54] */
    850         SOC_PBMP_CLEAR(*ch_8pg_ports);
    851         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 26);
    852         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 27);
    853         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 28);
    854         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 29);
    855         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 30); 
    856         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 34);
    857         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 38);
    858         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 42);
    859         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 46);
    860         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 50);
    861         SOC_PBMP_PORT_ADD(*ch_8pg_ports, 54);
    862 
    863         /*  24Q_PORTS = [26..31,34,38,39,42,43,46,50,51,54] */
    864         SOC_PBMP_CLEAR(*ch_24q_ports);
    865         SOC_PBMP_PORT_ADD(*ch_24q_ports, 26);
    866         SOC_PBMP_PORT_ADD(*ch_24q_ports, 27);
    867         SOC_PBMP_PORT_ADD(*ch_24q_ports, 28);
    868         SOC_PBMP_PORT_ADD(*ch_24q_ports, 29);
    869         SOC_PBMP_PORT_ADD(*ch_24q_ports, 30);
    870         SOC_PBMP_PORT_ADD(*ch_24q_ports, 31);
    871         SOC_PBMP_PORT_ADD(*ch_24q_ports, 34);
    872         SOC_PBMP_PORT_ADD(*ch_24q_ports, 38);
    873         SOC_PBMP_PORT_ADD(*ch_24q_ports, 39);
    874         SOC_PBMP_PORT_ADD(*ch_24q_ports, 42);
    875         SOC_PBMP_PORT_ADD(*ch_24q_ports, 43);
    876         SOC_PBMP_PORT_ADD(*ch_24q_ports, 46);
    877         SOC_PBMP_PORT_ADD(*ch_24q_ports, 50);
    878         SOC_PBMP_PORT_ADD(*ch_24q_ports, 51);
    879         SOC_PBMP_PORT_ADD(*ch_24q_ports, 54);
    880         SOC_PBMP_ASSIGN(*ch_24q_ports_with_cpu, *ch_24q_ports);
    881         SOC_PBMP_PORT_ADD(*ch_24q_ports_with_cpu, 0);
    882 
    883         /* 2PG_PORTS = [0,1..25,31..33,35..37,39..41,43..45,47..49,51..53,55,56] */
    884         SOC_PBMP_CLEAR(*ch_2pg_ports);
    885         SOC_PBMP_ASSIGN(*ch_2pg_ports, PBMP_ALL(unit));
    886         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 26);
    887         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 27);
    888         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 28);
    889         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 29);
    890         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 30); 
    891         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 34);
    892         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 38);
    893         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 42);
    894         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 46);
    895         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 50);
    896         SOC_PBMP_PORT_REMOVE(*ch_2pg_ports, 54);
    897         SOC_PBMP_PORT_ADD(*ch_2pg_ports, 55);
    898         SOC_PBMP_PORT_ADD(*ch_2pg_ports, 56);
    899 
    900         /* GXPORTS = [26, 27, 28, 29] */
    901         SOC_PBMP_CLEAR(*ch_gxports);
    902         SOC_PBMP_PORT_ADD(*ch_gxports, 26);
    903         SOC_PBMP_PORT_ADD(*ch_gxports, 27);
    904         SOC_PBMP_PORT_ADD(*ch_gxports, 28);
    905         SOC_PBMP_PORT_ADD(*ch_gxports, 29);
    906        
    907         /* Loopback pbmp */
    908         SOC_PBMP_CLEAR(*ch_lb_ports);
    909         SOC_PBMP_ASSIGN(*ch_lb_ports, PBMP_LB(unit));
    910 
    911         /* All ports except CMIC */
    912         SOC_PBMP_CLEAR(*ch_non_cpu_ports);
    913         SOC_PBMP_ASSIGN(*ch_non_cpu_ports, PBMP_ALL(unit));
    914         SOC_PBMP_PORT_REMOVE(*ch_non_cpu_ports, 0);
    915 
    916         /* All ports except CMIC and loopback - external ports */
    917         SOC_PBMP_CLEAR(*ch_ext_ports);
    918         SOC_PBMP_ASSIGN(*ch_ext_ports, PBMP_ALL(unit));
    919         SOC_PBMP_PORT_REMOVE(*ch_ext_ports, 0);
    920         SOC_PBMP_PORT_REMOVE(*ch_ext_ports, 54);
    921  
    922         /* All ports (excluding the internal MMU ports) */
    923         SOC_PBMP_CLEAR(*ch_all_ports); 
    924         SOC_PBMP_ASSIGN(*ch_all_ports, PBMP_ALL(unit)); 
    925 
    926         /* All ports (including the internal MMU ports) */
    927         SOC_PBMP_CLEAR(*ch_all_ports_with_mmu); 
    928         SOC_PBMP_ASSIGN(*ch_all_ports_with_mmu, PBMP_ALL(unit)); 
    929         SOC_PBMP_PORT_ADD(*ch_all_ports_with_mmu, 55);
    930         SOC_PBMP_PORT_ADD(*ch_all_ports_with_mmu, 56);
    931 
    932         /* CPU port */
    933         SOC_PBMP_CLEAR(*ch_cmic); 
    934         SOC_PBMP_ASSIGN(*ch_cmic, PBMP_CMIC(unit));
    935     }
    936     if (!SOC_PORT_VALID(unit, ainfo->port)) {
    937         return 0;
    938     }
    939     _MAP_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
    940  
    941     switch(ainfo->reg) {
    942         case MAC_CTRLr:
    943         case MAC_XGXS_CTRLr:
    944         case MAC_XGXS_STATr:
    945         case MAC_TXMUXCTRLr:
    946         case MAC_CNTMAXSZr:
    947         case MAC_CORESPARE0r:
    948         case MAC_TXCTRLr:
    949         case MAC_TXMACSAr:
    950         case MAC_TXMAXSZr:
    951         case MAC_TXPSETHRr:
    952         case MAC_TXSPARE0r:
    953         case MAC_TXPPPCTRLr:
    954         case ITPOKr:
    955         case ITXPFr: 
    956         case ITFCSr:
    957         case ITXPPr:
    958         case ITUCr:
    959         case ITMCAr:
    960         case ITBCAr:
    961         case ITOVRr:
    962         case ITFRGr:
    963         case ITPKTr:
    964         case IT64r:
    965         case IT127r:
    966         case IT255r:
    967         case IT511r:
    968         case IT1023r:
    969         case IT1518r:
    970         case IT2047r:
    971         case IT4095r:
    972         case IT9216r:
    973         case IT16383r:
    974         case ITMAXr:
    975         case ITUFLr:
    976         case ITERRr:
    977         case ITBYTr:
    978         case MAC_RXCTRLr:
    979         case MAC_RXMACSAr:
    980         case MAC_RXMAXSZr:
    981         case MAC_RXLSSCTRLr:
    982         case MAC_RXLSSSTATr:
    983         case MAC_RXSPARE0r:
    984         case IR64r:
    985         case IR127r:
    986         case IR255r:
    987         case IR511r:
    988         case IR1023r:
    989         case IR1518r:
    990         case IR2047r:
    991         case IR4095r:
    992         case IR9216r:
    993         case IR16383r:
    994         case IRMAXr:
    995         case IRPKTr:
    996         case IRFCSr:
    997         case IRUCr:
    998         case IRMCAr:
    999         case IRBCAr:
   1000         case IRXCFr:
   1001         case IRXPFr:
   1002         case IRXPPr:
   1003         case IRXUOr:
   1004         case IRJBRr:
   1005         case IROVRr:
   1006         case IRFLRr:
   1007         case IRPOKr:
   1008         case IRMEGr:
   1009         case IRMEBr:
   1010         case IRBYTr:
   1011         case IRUNDr:
   1012         case IRFRGr:
   1013         case IRERBYTr:
   1014         case IRERPKTr:
   1015         case IRJUNKr:
   1016         case MAC_TXLLFCCTRLr:
   1017         case MAC_TXLLFCMSGFLDSr:
   1018         case MAC_RXLLFCMSGFLDSr:
   1019         case MAC_RXLLFCMSGCNTr:
   1020             if (IS_GE_PORT(unit, ainfo->port)) {
   1021                 goto skip;
   1022             }
   1023             break;
   1024         case EGR_PORT_REQUESTSr:
   1025             if (IS_LB_PORT(unit, ainfo->port)) {
   1026                 goto skip;
   1027             }
   1028             break;
   1029         case MAC_PFC_COS0_XOFF_CNTr:
   1030         case MAC_PFC_COS1_XOFF_CNTr:
   1031         case MAC_PFC_COS2_XOFF_CNTr:
   1032         case MAC_PFC_COS3_XOFF_CNTr:
   1033         case MAC_PFC_COS4_XOFF_CNTr:
   1034         case MAC_PFC_COS5_XOFF_CNTr:
   1035         case MAC_PFC_COS6_XOFF_CNTr:
   1036         case MAC_PFC_COS7_XOFF_CNTr:
   1037         case MAC_PFC_COS8_XOFF_CNTr:
   1038         case MAC_PFC_COS9_XOFF_CNTr:
   1039         case MAC_PFC_COS10_XOFF_CNTr:
   1040         case MAC_PFC_COS11_XOFF_CNTr:
   1041         case MAC_PFC_COS12_XOFF_CNTr:
   1042         case MAC_PFC_COS13_XOFF_CNTr:
   1043         case MAC_PFC_COS14_XOFF_CNTr:
   1044         case MAC_PFC_COS15_XOFF_CNTr:
   1045             /* Not implemented in HW */
   1046             goto skip;
   1047             break;
   1048         default:
   1049             break;
   1050     }
   1051 
   1052     switch(ainfo->reg) {
   1053         case PG_THRESH_SELr:
   1054         case PORT_PRI_GRP0r:
   1055         case PORT_PRI_GRP1r:
   1056         case PORT_PRI_XON_ENABLEr:
   1057             pbmp = ch_8pg_ports;
   1058             break;
   1059         case PG_THRESH_SEL2r:
   1060         case PORT_PRI_GRP2r:
   1061             pbmp = ch_2pg_ports;
   1062             break;
   1063         case ECN_CONFIGr:
   1064         case HOL_STAT_PORTr:
   1065         case PORT_WREDPARAM_CELLr:
   1066         case PORT_WREDPARAM_YELLOW_CELLr:
   1067         case PORT_WREDPARAM_RED_CELLr:
   1068         case PORT_WREDPARAM_NONTCP_CELLr:
   1069         case PORT_WREDCONFIG_CELLr:
   1070         case PORT_WREDAVGQSIZE_CELLr:
   1071         case PORT_WREDPARAM_PACKETr:
   1072         case PORT_WREDPARAM_YELLOW_PACKETr:
   1073         case PORT_WREDPARAM_RED_PACKETr:
   1074         case PORT_WREDPARAM_NONTCP_PACKETr:
   1075         case PORT_WREDCONFIG_PACKETr:
   1076         case PORT_WREDAVGQSIZE_PACKETr:
   1077         case BKPMETERINGCONFIG_64r:
   1078         case BKPMETERINGBUCKETr:
   1079         case MTRI_IFGr:
   1080             pbmp = ch_ext_ports;
   1081             break;
   1082         case COSMASKr:
   1083         case MINSPCONFIGr:
   1084             pbmp = ch_non_cpu_ports;
   1085             break;
   1086         case S1V_CONFIGr:
   1087         case S1V_COSWEIGHTSr:
   1088         case S1V_COSMASKr:
   1089         case S1V_MINSPCONFIGr:
   1090         case S1V_WDRRCOUNTr:
   1091             pbmp = ch_24q_ports;
   1092             break;
   1093         /* MMU_WLP_PERCOS_REGS */
   1094         case OP_QUEUE_FIRST_FRAGMENT_CONFIG_CELLr:
   1095         case OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_CELLr:
   1096         case OP_QUEUE_FIRST_FRAGMENT_CONFIG_PACKETr:
   1097         case OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_PACKETr:
   1098         case OP_QUEUE_FIRST_FRAGMENT_COUNT_CELLr:
   1099         case OP_QUEUE_FIRST_FRAGMENT_COUNT_PACKETr:
   1100         case OP_QUEUE_REDIRECT_CONFIG_CELLr:
   1101         case OP_QUEUE_REDIRECT_RESET_OFFSET_CELLr:
   1102         case OP_QUEUE_REDIRECT_CONFIG_PACKETr:
   1103         case OP_QUEUE_REDIRECT_RESET_OFFSET_PACKETr:
   1104         case OP_QUEUE_REDIRECT_COUNT_CELLr:
   1105         case OP_QUEUE_REDIRECT_COUNT_PACKETr:
   1106         case OP_QUEUE_REDIRECT_XQ_CONFIG_PACKETr:
   1107         case OP_QUEUE_REDIRECT_XQ_RESET_OFFSET_PACKETr:
   1108         case OP_QUEUE_REDIRECT_XQ_COUNT_PACKETr:
   1109         case OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_CELLr:
   1110         case OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_PACKETr:
   1111         case OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_CELLr:
   1112         case OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_PACKETr:
   1113         case OP_PORT_FIRST_FRAGMENT_COUNT_CELLr:
   1114         case OP_PORT_FIRST_FRAGMENT_COUNT_PACKETr:
   1115         case FIRST_FRAGMENT_DROP_STATE_CELLr:
   1116         case FIRST_FRAGMENT_DROP_STATE_PACKETr:
   1117         case OP_PORT_REDIRECT_COUNT_CELLr:
   1118         case OP_PORT_REDIRECT_COUNT_PACKETr:
   1119         case REDIRECT_DROP_STATE_CELLr:
   1120         case REDIRECT_DROP_STATE_PACKETr:
   1121         case REDIRECT_XQ_DROP_STATE_PACKETr: 
   1122         case OP_PORT_REDIRECT_DISC_RESUME_THD_CELLr:
   1123         case OP_PORT_REDIRECT_DISC_RESUME_THD_PACKETr:
   1124         case OP_PORT_REDIRECT_DISC_SET_THD_CELLr:
   1125         case OP_PORT_REDIRECT_DISC_SET_THD_PACKETr:
   1126         case OP_PORT_REDIRECT_XQ_DISC_RESUME_THD_PACKETr:
   1127         case OP_PORT_REDIRECT_XQ_DISC_SET_THD_PACKETr:
   1128         case OP_PORT_REDIRECT_XQ_COUNT_PACKETr:
   1129             pbmp = ch_lb_ports;
   1130             break;
   1131         case PORT_MIN_CELLr:
   1132         case PORT_MIN_PACKETr:
   1133         case PORT_SHARED_LIMIT_CELLr:
   1134         case PORT_SHARED_LIMIT_PACKETr:
   1135         case PORT_COUNT_CELLr:
   1136         case PORT_COUNT_PACKETr:
   1137         case PORT_MIN_COUNT_CELLr:
   1138         case PORT_MIN_COUNT_PACKETr:
   1139         case PORT_SHARED_COUNT_CELLr:
   1140         case PORT_SHARED_COUNT_PACKETr:
   1141             pbmp = ch_all_ports_with_mmu;
   1142             break;
   1143         default:
   1144             pbmp = ch_all_ports;
   1145             break;
   1146     }
   1147 
   1148     switch(ainfo->reg) {
   1149         /* MMU_PERPORTPERCOS_REGS */
   1150         case OP_QUEUE_CONFIG_CELLr:
   1151         case OP_QUEUE_CONFIG1_CELLr:
   1152         case OP_QUEUE_CONFIG_PACKETr:
   1153         case OP_QUEUE_CONFIG1_PACKETr:
   1154         case OP_QUEUE_LIMIT_YELLOW_CELLr:
   1155         case OP_QUEUE_LIMIT_YELLOW_PACKETr:
   1156         case OP_QUEUE_LIMIT_RED_CELLr:
   1157         case OP_QUEUE_LIMIT_RED_PACKETr:
   1158         case OP_QUEUE_RESET_OFFSET_CELLr:
   1159         case OP_QUEUE_RESET_OFFSET_PACKETr:
   1160         case OP_QUEUE_MIN_COUNT_CELLr:
   1161         case OP_QUEUE_MIN_COUNT_PACKETr:
   1162         case OP_QUEUE_SHARED_COUNT_CELLr:
   1163         case OP_QUEUE_SHARED_COUNT_PACKETr:
   1164         case OP_QUEUE_TOTAL_COUNT_CELLr:
   1165         case OP_QUEUE_TOTAL_COUNT_PACKETr:
   1166         case OP_QUEUE_RESET_VALUE_CELLr:
   1167         case OP_QUEUE_RESET_VALUE_PACKETr:
   1168         case OP_QUEUE_LIMIT_RESUME_COLOR_CELLr:
   1169         case OP_QUEUE_LIMIT_RESUME_COLOR_PACKETr:
   1170         /* MMU_PERPORTPERCOS_REGS_CTR */
   1171         case DROP_PKT_CNTr:
   1172         case DROP_BYTE_CNTr:
   1173             if (ainfo->port == 0) {
   1174                 return 0;
   1175             } else if (ainfo->idx < 8) {
   1176                 pbmp = ch_all_ports;
   1177             } else if ((ainfo->idx < 24) && (ainfo->port == 54)) {
   1178                 goto skip;
   1179             } else if ((ainfo->idx < 24)) {
   1180                 pbmp = ch_24q_ports;
   1181             } else {
   1182                 pbmp = ch_cmic;
   1183             }
   1184             break;
   1185 
   1186         /* MMU_PERPORTPERCOS_NOCPU_REGS */
   1187         case WREDPARAM_CELLr:
   1188         case WREDPARAM_YELLOW_CELLr:
   1189         case WREDPARAM_RED_CELLr:
   1190         case WREDPARAM_NONTCP_CELLr:
   1191         case WREDCONFIG_CELLr:
   1192         case WREDAVGQSIZE_CELLr:
   1193         case WREDPARAM_PACKETr:
   1194         case WREDPARAM_YELLOW_PACKETr:
   1195         case WREDPARAM_RED_PACKETr:
   1196         case WREDPARAM_NONTCP_PACKETr:
   1197         case WREDCONFIG_PACKETr:
   1198         case WREDAVGQSIZE_PACKETr:
   1199             if (ainfo->port == 0) {
   1200                 goto skip;
   1201             } else if (ainfo->idx < 8) {
   1202                 pbmp = ch_non_cpu_ports;
   1203             } else {
   1204                 pbmp = ch_24q_ports;
   1205             }
   1206             break;
   1207 
   1208         /* MMU_MTRO_REGS */
   1209         case MINBUCKETCONFIG_64r:
   1210         case MINBUCKETr:
   1211         case MAXBUCKETCONFIG_64r:
   1212         case MAXBUCKETr:
   1213             if (ainfo->idx < 8) {
   1214                 pbmp = ch_all_ports;
   1215             } else if (ainfo->idx < 26) {
   1216                 pbmp = ch_24q_ports_with_cpu;
   1217             } else {
   1218                 pbmp = ch_cmic;
   1219             }
   1220             break;
   1221 
   1222         /* MMU_ES_REGS */
   1223         case COSWEIGHTSr:
   1224         case WDRRCOUNTr:
   1225             if (ainfo->idx < 8) {
   1226                 pbmp = ch_all_ports;
   1227             } else if (ainfo->idx < 10) {
   1228                 pbmp = ch_24q_ports_with_cpu;
   1229             } else {
   1230                 pbmp = ch_cmic;
   1231             }
   1232             break;
   1233 
   1234         /* MMU_PERPORTPERPRI_REGS */
   1235         case PG_RESET_OFFSET_CELLr:
   1236         case PG_RESET_OFFSET_PACKETr:
   1237         case PG_RESET_FLOOR_CELLr:
   1238         
   1239         case PG_MIN_CELLr:
   1240         case PG_MIN_PACKETr:
   1241         case PG_HDRM_LIMIT_CELLr:
   1242         case PG_HDRM_LIMIT_PACKETr:
   1243         case PG_COUNT_CELLr:
   1244         case PG_COUNT_PACKETr:
   1245         case PG_MIN_COUNT_CELLr:
   1246         case PG_MIN_COUNT_PACKETr:
   1247         case PG_PORT_MIN_COUNT_CELLr:
   1248         case PG_PORT_MIN_COUNT_PACKETr:
   1249         case PG_SHARED_COUNT_CELLr:
   1250         case PG_SHARED_COUNT_PACKETr:
   1251         case PG_HDRM_COUNT_CELLr:
   1252         case PG_HDRM_COUNT_PACKETr:
   1253         case PG_GBL_HDRM_COUNTr:
   1254         case PG_RESET_VALUE_CELLr:
   1255         case PG_RESET_VALUE_PACKETr:
   1256             if (ainfo->idx < 2) {
   1257                 pbmp = ch_all_ports_with_mmu;
   1258             } else {
   1259                 pbmp = ch_8pg_ports;
   1260             }
   1261             break;
   1262  
   1263         default:
   1264             break; 
   1265     }
   1266 
   1267     if (!SOC_PBMP_MEMBER(*pbmp, ainfo->port)) {
   1268         goto skip; 
   1269     }
   1270 
   1271     if (mask != NULL) {
   1272         switch(ainfo->reg) {
   1273             case HOL_STAT_PORTr:
   1274             case ECN_CONFIGr:
   1275                 if (!SOC_PBMP_MEMBER(*ch_24q_ports, ainfo->port)) {
   1276                     /* adjust mask for ports without 24 queues */
   1277                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
   1278                     COMPILER_64_AND(*mask, temp_mask);
   1279                 }
   1280                 break;
   1281             case TOQ_QUEUESTAT_64r:
   1282             case TOQ_ACTIVATEQ_64r:
   1283             case TOQEMPTY_64r:
   1284             case DEQ_AGINGMASK_64r:
   1285             case SHAPING_MODEr:
   1286             case EAV_MAXBUCKET_64r:
   1287             case EAV_MINBUCKET_64r:
   1288                 if (SOC_PBMP_MEMBER(*ch_24q_ports, ainfo->port)) {
   1289                     /* adjust mask for ports with 24 queues */
   1290                     COMPILER_64_SET(temp_mask, 0, 0x00ffffff);
   1291                     COMPILER_64_AND(*mask, temp_mask);
   1292                 } else if (ainfo->port != 0) {
   1293                     /* remaining ports only have 8 queues */
   1294                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
   1295                     COMPILER_64_AND(*mask, temp_mask);
   1296                 }
   1297                 break;
   1298         }
   1299     }
   1300     return 0; 
   1301 skip:
   1302     /* set mask to all 0's so test will skip it */
   1303     if (mask != NULL) {
   1304         COMPILER_64_SET(*mask, 0, 0);
   1305     }
   1306     return 1;
   1307 }
   1308 #endif /* BCM_TRIUMPH2_SUPPORT */
   1309 
   1310 #ifdef BCM_ENDURO_SUPPORT
   1311 STATIC int
   1312 reg_mask_subset_en(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   1313 {
   1314     pbmp_t *en_8pg_ports;
   1315     pbmp_t *en_higig_ports;
   1316     pbmp_t *en_24q_ports;
   1317     pbmp_t *en_24q_ports_with_cpu;
   1318     pbmp_t *en_non_cpu_ports;
   1319     pbmp_t *en_all_ports;
   1320     pbmp_t *en_cmic;
   1321 #define _REG_MASK_SUBSET_MAX_EN 7
   1322     pbmp_t **mask_map_arr[_REG_MASK_SUBSET_MAX_EN];
   1323     int i, count = _REG_MASK_SUBSET_MAX_EN;
   1324     uint64 temp_mask;
   1325     pbmp_t *pbmp;
   1326 
   1327     mask_map_arr[0] = &en_8pg_ports;
   1328     mask_map_arr[1] = &en_higig_ports;
   1329     mask_map_arr[2] = &en_24q_ports;
   1330     mask_map_arr[3] = &en_24q_ports_with_cpu;
   1331     mask_map_arr[4] = &en_non_cpu_ports;
   1332     mask_map_arr[5] = &en_all_ports;
   1333     mask_map_arr[6] = &en_cmic;
   1334     if (NULL == SOC_REG_MASK_SUBSET(unit)) {
   1335         _INIT_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
   1336 
   1337         /* Higig ports [0,26,27,28,29] */
   1338         SOC_PBMP_CLEAR(*en_higig_ports);
   1339         SOC_PBMP_PORT_ADD(*en_higig_ports, 0);
   1340         SOC_PBMP_PORT_ADD(*en_higig_ports, 26);
   1341         SOC_PBMP_PORT_ADD(*en_higig_ports, 27);
   1342         SOC_PBMP_PORT_ADD(*en_higig_ports, 28);
   1343         SOC_PBMP_PORT_ADD(*en_higig_ports, 29);
   1344 
   1345         /*  24Q_PORTS = [26,27,28,29] */
   1346         SOC_PBMP_CLEAR(*en_24q_ports);
   1347         SOC_PBMP_PORT_ADD(*en_24q_ports, 26);
   1348         SOC_PBMP_PORT_ADD(*en_24q_ports, 27);
   1349         SOC_PBMP_PORT_ADD(*en_24q_ports, 28);
   1350         SOC_PBMP_PORT_ADD(*en_24q_ports, 29);
   1351         SOC_PBMP_ASSIGN(*en_24q_ports_with_cpu, *en_24q_ports);
   1352         SOC_PBMP_PORT_ADD(*en_24q_ports_with_cpu, 0);
   1353 
   1354         SOC_PBMP_CLEAR(*en_8pg_ports);
   1355         SOC_PBMP_PORT_ADD(*en_8pg_ports, 26);
   1356         SOC_PBMP_PORT_ADD(*en_8pg_ports, 27);
   1357         SOC_PBMP_PORT_ADD(*en_8pg_ports, 28);
   1358         SOC_PBMP_PORT_ADD(*en_8pg_ports, 29);
   1359 
   1360         /* all port except CMIC */
   1361         SOC_PBMP_CLEAR(*en_non_cpu_ports);
   1362         SOC_PBMP_ASSIGN(*en_non_cpu_ports, PBMP_ALL(unit));
   1363         SOC_PBMP_PORT_REMOVE(*en_non_cpu_ports, 0);
   1364  
   1365         /* All ports */
   1366         SOC_PBMP_CLEAR(*en_all_ports); 
   1367         SOC_PBMP_ASSIGN(*en_all_ports, PBMP_ALL(unit)); 
   1368  
   1369         /* CPU port */
   1370         SOC_PBMP_CLEAR(*en_cmic); 
   1371         SOC_PBMP_ASSIGN(*en_cmic, PBMP_CMIC(unit));
   1372     }
   1373     if (!SOC_PORT_VALID(unit, ainfo->port)) {
   1374         return 0;
   1375     }
   1376     _MAP_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
   1377  
   1378     switch(ainfo->reg) {
   1379         case MAC_CTRLr:
   1380         case MAC_XGXS_CTRLr:
   1381         case MAC_XGXS_STATr:
   1382         case MAC_TXMUXCTRLr:
   1383         case MAC_CNTMAXSZr:
   1384         case MAC_CORESPARE0r:
   1385         case MAC_TXCTRLr:
   1386         case MAC_TXMACSAr:
   1387         case MAC_TXMAXSZr:
   1388         case MAC_TXPSETHRr:
   1389         case MAC_TXSPARE0r:
   1390         case MAC_TXPPPCTRLr:
   1391         case ITPOKr:
   1392         case ITXPFr: 
   1393         case ITFCSr:
   1394         case ITUCr:
   1395         case ITUCAr:
   1396         case ITMCAr:
   1397         case ITBCAr:
   1398         case ITOVRr:
   1399         case ITFRGr:
   1400         case ITPKTr:
   1401         case IT64r:
   1402         case IT127r:
   1403         case IT255r:
   1404         case IT511r:
   1405         case IT1023r:
   1406         case IT1518r:
   1407         case IT2047r:
   1408         case IT4095r:
   1409         case IT9216r:
   1410         case IT16383r:
   1411         case ITMAXr:
   1412         case ITUFLr:
   1413         case ITERRr:
   1414         case ITBYTr:
   1415         case MAC_RXCTRLr:
   1416         case MAC_RXMACSAr:
   1417         case MAC_RXMAXSZr:
   1418         case MAC_RXLSSCTRLr:
   1419         case MAC_RXLSSSTATr:
   1420         case MAC_RXSPARE0r:
   1421         case IR64r:
   1422         case IR127r:
   1423         case IR255r:
   1424         case IR511r:
   1425         case IR1023r:
   1426         case IR1518r:
   1427         case IR2047r:
   1428         case IR4095r:
   1429         case IR9216r:
   1430         case IR16383r:
   1431         case IRMAXr:
   1432         case IRPKTr:
   1433         case IRFCSr:
   1434         case IRUCAr:
   1435         case IRMCAr:
   1436         case IRBCAr:
   1437         case IRXCFr:
   1438         case IRXPFr:
   1439         case IRXUOr:
   1440         case IRJBRr:
   1441         case IROVRr:
   1442         case IRFLRr:
   1443         case IRPOKr:
   1444         case IRMEGr:
   1445         case IRMEBr:
   1446         case IRBYTr:
   1447         case IRUNDr:
   1448         case IRFRGr:
   1449         case IRERBYTr:
   1450         case IRERPKTr:
   1451         case IRJUNKr:
   1452         case MAC_TXLLFCCTRLr:
   1453         case MAC_TXLLFCMSGFLDSr:
   1454         case MAC_RXLLFCMSGFLDSr:
   1455         case MAC_RXLLFCMSGCNTr:
   1456             if (IS_GE_PORT(unit, ainfo->port)) {
   1457                 goto skip;
   1458             }
   1459             break;
   1460         default:
   1461             break;
   1462     }
   1463 
   1464     switch(ainfo->reg) {
   1465         case IE2E_CONTROLr:
   1466         case ING_MODMAP_CTRLr:
   1467         case IHG_LOOKUPr:
   1468         case ICONTROL_OPCODE_BITMAPr:
   1469         case UNKNOWN_HGI_BITMAPr:
   1470         case IUNHGIr:
   1471         case ICTRLr:
   1472         case IBCASTr:
   1473         case ILTOMCr:
   1474         case IIPMCr:
   1475         case IUNKOPCr:
   1476             pbmp = en_higig_ports;
   1477             break;
   1478         case PG_THRESH_SELr:
   1479         case PORT_PRI_GRP0r:
   1480         case PORT_PRI_GRP1r:
   1481         case PORT_PRI_XON_ENABLEr:
   1482             pbmp = en_8pg_ports;
   1483             break;
   1484         case ECN_CONFIGr:
   1485         case HOL_STAT_PORTr:
   1486         case PORT_WREDPARAM_CELLr:
   1487         case PORT_WREDPARAM_YELLOW_CELLr:
   1488         case PORT_WREDPARAM_RED_CELLr:
   1489         case PORT_WREDPARAM_NONTCP_CELLr:
   1490         case PORT_WREDCONFIG_CELLr:
   1491         case PORT_WREDAVGQSIZE_CELLr:
   1492         case PORT_WREDPARAM_PACKETr:
   1493         case PORT_WREDPARAM_YELLOW_PACKETr:
   1494         case PORT_WREDPARAM_RED_PACKETr:
   1495         case PORT_WREDPARAM_NONTCP_PACKETr:
   1496         case PORT_WREDCONFIG_PACKETr:
   1497         case PORT_WREDAVGQSIZE_PACKETr:
   1498         case COSMASKr:
   1499         case MINSPCONFIGr:
   1500         case EGRMETERINGCONFIG_64r:
   1501         case EGRMETERINGBUCKETr:
   1502             pbmp = en_non_cpu_ports;
   1503             break;
   1504         case ING_COS_MODEr:
   1505         case COS_MODEr:
   1506         case S1V_CONFIGr:
   1507         case S1V_COSWEIGHTSr:
   1508         case S1V_COSMASKr:
   1509         case S1V_MINSPCONFIGr:
   1510         case S1V_WDRRCOUNTr:
   1511             pbmp = en_24q_ports;
   1512             break;
   1513         default:
   1514             pbmp = en_all_ports;
   1515             break;
   1516     }
   1517 
   1518     switch(ainfo->reg) {
   1519         /* MMU_PERPORTPERCOS_REGS */
   1520         case OP_QUEUE_CONFIG_CELLr:
   1521         case OP_QUEUE_CONFIG1_CELLr:
   1522         case OP_QUEUE_CONFIG_PACKETr:
   1523         case OP_QUEUE_CONFIG1_PACKETr:
   1524         case OP_QUEUE_LIMIT_YELLOW_CELLr:
   1525         case OP_QUEUE_LIMIT_YELLOW_PACKETr:
   1526         case OP_QUEUE_LIMIT_RED_CELLr:
   1527         case OP_QUEUE_LIMIT_RED_PACKETr:
   1528         case OP_QUEUE_RESET_OFFSET_CELLr:
   1529         case OP_QUEUE_RESET_OFFSET_PACKETr:
   1530         case OP_QUEUE_MIN_COUNT_CELLr:
   1531         case OP_QUEUE_MIN_COUNT_PACKETr:
   1532         case OP_QUEUE_SHARED_COUNT_CELLr:
   1533         case OP_QUEUE_SHARED_COUNT_PACKETr:
   1534         case OP_QUEUE_TOTAL_COUNT_CELLr:
   1535         case OP_QUEUE_TOTAL_COUNT_PACKETr:
   1536         case OP_QUEUE_RESET_VALUE_CELLr:
   1537         case OP_QUEUE_RESET_VALUE_PACKETr:
   1538         case OP_QUEUE_LIMIT_RESUME_COLOR_CELLr:
   1539         case OP_QUEUE_LIMIT_RESUME_COLOR_PACKETr:
   1540         /* MMU_PERPORTPERCOS_REGS_CTR */
   1541         case DROP_PKT_CNTr:
   1542         case DROP_BYTE_CNTr:
   1543             if (ainfo->port == 0) {
   1544                 return 0;
   1545             } else if (ainfo->idx < 8) {
   1546                 pbmp = en_all_ports;
   1547             } else if (ainfo->idx < 24) {
   1548                 pbmp = en_24q_ports;
   1549             } else {
   1550                 pbmp = en_cmic;
   1551             }
   1552             break;
   1553         /* MMU_PERPORTPERCOS_NOCPU_REGS */
   1554         case WREDPARAM_CELLr:
   1555         case WREDPARAM_YELLOW_CELLr:
   1556         case WREDPARAM_RED_CELLr:
   1557         case WREDPARAM_NONTCP_CELLr:
   1558         case WREDCONFIG_CELLr:
   1559         case WREDAVGQSIZE_CELLr:
   1560         case WREDPARAM_PACKETr:
   1561         case WREDPARAM_YELLOW_PACKETr:
   1562         case WREDPARAM_RED_PACKETr:
   1563         case WREDPARAM_NONTCP_PACKETr:
   1564         case WREDCONFIG_PACKETr:
   1565         case WREDAVGQSIZE_PACKETr:
   1566             if (ainfo->port == 0) {
   1567                 goto skip;
   1568             } else if (ainfo->idx < 8) {
   1569                 pbmp = en_non_cpu_ports;
   1570             } else {
   1571                 pbmp = en_24q_ports;
   1572             }
   1573             break;
   1574 
   1575 
   1576         /* MMU_MTRO_REGS */
   1577         case MINBUCKETCONFIG_64r:
   1578         case MINBUCKETr:
   1579         case MAXBUCKETCONFIG_64r:
   1580         case MAXBUCKETr:
   1581             if (ainfo->port == 0) {
   1582                 goto skip;
   1583             } else if (ainfo->idx < 8) {
   1584                 pbmp = en_all_ports;
   1585             } else if (ainfo->idx < 26) {
   1586                 pbmp = en_24q_ports_with_cpu;
   1587             } else {
   1588                 pbmp = en_cmic;
   1589             }
   1590             break;
   1591 
   1592         /* MMU_ES_REGS */
   1593         case COSWEIGHTSr:
   1594         case WDRRCOUNTr:
   1595             if (ainfo->idx < 8) {
   1596                 pbmp = en_all_ports;
   1597             } else if (ainfo->idx < 10) {
   1598                 pbmp = en_24q_ports_with_cpu;
   1599             } else {
   1600                 pbmp = en_cmic;
   1601             }
   1602             break;
   1603         /* MMU_PERPORTPERPRI_REGS */
   1604         case PG_RESET_OFFSET_CELLr:
   1605         case PG_RESET_OFFSET_PACKETr:
   1606         case PG_RESET_FLOOR_CELLr:
   1607         
   1608         case PG_MIN_CELLr:
   1609         case PG_MIN_PACKETr:
   1610         case PG_HDRM_LIMIT_CELLr:
   1611         case PG_HDRM_LIMIT_PACKETr:
   1612         case PG_COUNT_CELLr:
   1613         case PG_COUNT_PACKETr:
   1614         case PG_MIN_COUNT_CELLr:
   1615         case PG_MIN_COUNT_PACKETr:
   1616         case PG_PORT_MIN_COUNT_CELLr:
   1617         case PG_PORT_MIN_COUNT_PACKETr:
   1618         case PG_SHARED_COUNT_CELLr:
   1619         case PG_SHARED_COUNT_PACKETr:
   1620         case PG_HDRM_COUNT_CELLr:
   1621         case PG_HDRM_COUNT_PACKETr:
   1622         case PG_GBL_HDRM_COUNTr:
   1623         case PG_RESET_VALUE_CELLr:
   1624         case PG_RESET_VALUE_PACKETr:
   1625             if (ainfo->idx != 0) {
   1626                 pbmp = en_8pg_ports;
   1627             }
   1628             break;
   1629         default:
   1630             break; 
   1631     }
   1632 
   1633     if (!SOC_PBMP_MEMBER(*pbmp, ainfo->port)) {
   1634         goto skip; 
   1635     }
   1636 
   1637     if (mask != NULL) {
   1638         switch(ainfo->reg) {
   1639             case HOL_STAT_PORTr:
   1640             case ECN_CONFIGr:
   1641                 if (!SOC_PBMP_MEMBER(*en_24q_ports, ainfo->port)) {
   1642                     /* adjust mask for ports without 24 queues */
   1643                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
   1644                     COMPILER_64_AND(*mask, temp_mask);
   1645                 }
   1646                 break;
   1647             case TOQ_QUEUESTAT_64r:
   1648             case TOQ_ACTIVATEQ_64r:
   1649             case TOQEMPTY_64r:
   1650             case DEQ_AGINGMASK_64r:
   1651                 if (SOC_PBMP_MEMBER(*en_24q_ports, ainfo->port)) {
   1652                     /* adjust mask for ports with 24 queues */
   1653                     COMPILER_64_SET(temp_mask, 0, 0x00ffffff);
   1654                     COMPILER_64_AND(*mask, temp_mask);
   1655                 } else if (ainfo->port != 0) {
   1656                     /* remaining ports only have 8 queues */
   1657                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
   1658                     COMPILER_64_AND(*mask, temp_mask);
   1659                 }
   1660                 break;
   1661         }
   1662     }
   1663     return 0; 
   1664 skip:
   1665     /* set mask to all 0's so test will skip it */
   1666     if (mask != NULL) {
   1667         COMPILER_64_SET(*mask, 0, 0);
   1668     }
   1669     return 1;
   1670 }
   1671 #endif /* BCM_ENDURO_SUPPORT */
   1672 
   1673 #ifdef BCM_HURRICANE1_SUPPORT
   1674 STATIC int
   1675 reg_mask_subset_hu(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   1676 {
   1677     pbmp_t *hu_8pg_ports;
   1678     pbmp_t *hu_24q_ports;
   1679     pbmp_t *hu_24q_ports_with_cpu;
   1680     pbmp_t *hu_higig_ports;
   1681     pbmp_t *hu_non_cpu_ports;
   1682     pbmp_t *hu_all_ports;
   1683 #define _REG_MASK_SUBSET_MAX_HU 6
   1684     pbmp_t **mask_map_arr[_REG_MASK_SUBSET_MAX_HU];
   1685     int i, count = _REG_MASK_SUBSET_MAX_HU;
   1686     uint64 temp_mask;
   1687     pbmp_t *pbmp;
   1688 
   1689     mask_map_arr[0] = &hu_8pg_ports;
   1690     mask_map_arr[1] = &hu_24q_ports;
   1691     mask_map_arr[2] = &hu_24q_ports_with_cpu;
   1692     mask_map_arr[3] = &hu_higig_ports;
   1693     mask_map_arr[4] = &hu_non_cpu_ports;
   1694     mask_map_arr[5] = &hu_all_ports;
   1695     if (NULL == SOC_REG_MASK_SUBSET(unit)) {
   1696         _INIT_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
   1697 
   1698         /* Higig ports [0,26,27,28,29] */
   1699         SOC_PBMP_CLEAR(*hu_higig_ports);
   1700         SOC_PBMP_PORT_ADD(*hu_higig_ports, 0);
   1701         SOC_PBMP_PORT_ADD(*hu_higig_ports, 26);
   1702         SOC_PBMP_PORT_ADD(*hu_higig_ports, 27);
   1703         SOC_PBMP_PORT_ADD(*hu_higig_ports, 28);
   1704         SOC_PBMP_PORT_ADD(*hu_higig_ports, 29);
   1705 
   1706         /*  24Q_PORTS = NONE */
   1707         SOC_PBMP_CLEAR(*hu_24q_ports);
   1708         SOC_PBMP_ASSIGN(*hu_24q_ports_with_cpu, *hu_24q_ports);
   1709         SOC_PBMP_PORT_ADD(*hu_24q_ports_with_cpu, 0);
   1710 
   1711         SOC_PBMP_CLEAR(*hu_8pg_ports);
   1712         SOC_PBMP_PORT_ADD(*hu_8pg_ports, 26);
   1713         SOC_PBMP_PORT_ADD(*hu_8pg_ports, 27);
   1714         SOC_PBMP_PORT_ADD(*hu_8pg_ports, 28);
   1715         SOC_PBMP_PORT_ADD(*hu_8pg_ports, 29);
   1716 
   1717         /* all port except CMIC */
   1718         SOC_PBMP_CLEAR(*hu_non_cpu_ports);
   1719         SOC_PBMP_ASSIGN(*hu_non_cpu_ports, PBMP_ALL(unit));
   1720         SOC_PBMP_PORT_REMOVE(*hu_non_cpu_ports, 0);
   1721  
   1722         /* All ports */
   1723         SOC_PBMP_CLEAR(*hu_all_ports); 
   1724         SOC_PBMP_ASSIGN(*hu_all_ports, PBMP_ALL(unit)); 
   1725     }
   1726     if (!SOC_PORT_VALID(unit, ainfo->port)) {
   1727         return 0;
   1728     }
   1729     if (!SOC_REG_IS_VALID(unit, ainfo->reg)) {
   1730         goto skip;
   1731     }
   1732     _MAP_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
   1733  
   1734     switch(ainfo->reg) {
   1735         case MAC_CTRLr:
   1736         case MAC_XGXS_CTRLr:
   1737         case MAC_XGXS_STATr:
   1738         case MAC_TXMUXCTRLr:
   1739         case MAC_CNTMAXSZr:
   1740         case MAC_CORESPARE0r:
   1741         case MAC_TXCTRLr:
   1742         case MAC_TXMACSAr:
   1743         case MAC_TXMAXSZr:
   1744         case MAC_TXPSETHRr:
   1745         case MAC_TXSPARE0r:
   1746         case MAC_TXPPPCTRLr:
   1747         case ITPOKr:
   1748         case ITXPFr: 
   1749         case ITFCSr:
   1750         case ITUCr:
   1751         case ITUCAr:
   1752         case ITMCAr:
   1753         case ITBCAr:
   1754         case ITOVRr:
   1755         case ITFRGr:
   1756         case ITPKTr:
   1757         case IT64r:
   1758         case IT127r:
   1759         case IT255r:
   1760         case IT511r:
   1761         case IT1023r:
   1762         case IT1518r:
   1763         case IT2047r:
   1764         case IT4095r:
   1765         case IT9216r:
   1766         case IT16383r:
   1767         case ITMAXr:
   1768         case ITUFLr:
   1769         case ITERRr:
   1770         case ITBYTr:
   1771         case MAC_RXCTRLr:
   1772         case MAC_RXMACSAr:
   1773         case MAC_RXMAXSZr:
   1774         case MAC_RXLSSCTRLr:
   1775         case MAC_RXLSSSTATr:
   1776         case MAC_RXSPARE0r:
   1777         case IR64r:
   1778         case IR127r:
   1779         case IR255r:
   1780         case IR511r:
   1781         case IR1023r:
   1782         case IR1518r:
   1783         case IR2047r:
   1784         case IR4095r:
   1785         case IR9216r:
   1786         case IR16383r:
   1787         case IRMAXr:
   1788         case IRPKTr:
   1789         case IRFCSr:
   1790         case IRUCAr:
   1791         case IRMCAr:
   1792         case IRBCAr:
   1793         case IRXCFr:
   1794         case IRXPFr:
   1795         case IRXUOr:
   1796         case IRJBRr:
   1797         case IROVRr:
   1798         case IRFLRr:
   1799         case IRPOKr:
   1800         case IRMEGr:
   1801         case IRMEBr:
   1802         case IRBYTr:
   1803         case IRUNDr:
   1804         case IRFRGr:
   1805         case IRERBYTr:
   1806         case IRERPKTr:
   1807         case IRJUNKr:
   1808         case ITXPPr:
   1809         case IRXPPr:
   1810         case MAC_TXLLFCCTRLr:
   1811         case MAC_TXLLFCMSGFLDSr:
   1812         case MAC_RXLLFCMSGFLDSr:
   1813         case MAC_RXLLFCMSGCNTr:
   1814             if (IS_GE_PORT(unit, ainfo->port)) {
   1815                 goto skip;
   1816             }
   1817             break;
   1818         default:
   1819             break;
   1820     }
   1821 
   1822     switch(ainfo->reg) {
   1823         case IE2E_CONTROLr:
   1824         case ING_MODMAP_CTRLr:
   1825         case IHG_LOOKUPr:
   1826         case ICONTROL_OPCODE_BITMAPr:
   1827         case UNKNOWN_HGI_BITMAPr:
   1828         case IUNHGIr:
   1829         case ICTRLr:
   1830         case IBCASTr:
   1831         case ILTOMCr:
   1832         case IIPMCr:
   1833         case IUNKOPCr:
   1834             pbmp = hu_higig_ports;
   1835             break;
   1836         case HOL_STAT_PORTr:
   1837             pbmp = hu_non_cpu_ports;
   1838             break;
   1839         case ING_COS_MODEr:
   1840             pbmp = hu_24q_ports;
   1841             break;
   1842         default:
   1843             pbmp = hu_all_ports;
   1844             break;
   1845     }
   1846 
   1847     if (!SOC_PBMP_MEMBER(*pbmp, ainfo->port)) {
   1848         goto skip; 
   1849     }
   1850 
   1851 
   1852     if (mask != NULL) {
   1853         switch(ainfo->reg) {
   1854             case HOL_STAT_PORTr:
   1855                 if (!SOC_PBMP_MEMBER(*hu_24q_ports, ainfo->port)) {
   1856                     /* adjust mask for ports without 24 queues */
   1857                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
   1858                     COMPILER_64_AND(*mask, temp_mask);
   1859                 }
   1860                 break;
   1861             case TOQ_QUEUESTAT_64r:
   1862             case TOQ_ACTIVATEQ_64r:
   1863             case TOQEMPTY_64r:
   1864             case DEQ_AGINGMASK_64r:
   1865                 if (SOC_PBMP_MEMBER(*hu_24q_ports, ainfo->port)) {
   1866                     /* adjust mask for ports with 24 queues */
   1867                     COMPILER_64_SET(temp_mask, 0, 0x00ffffff);
   1868                     COMPILER_64_AND(*mask, temp_mask);
   1869                 } else if (ainfo->port != 0) {
   1870                     /* remaining ports only have 8 queues */
   1871                     COMPILER_64_SET(temp_mask, 0, 0x000000ff);
   1872                     COMPILER_64_AND(*mask, temp_mask);
   1873                 }
   1874                 break;
   1875             case MAC_MODEr:
   1876                 /* skip LINK_STATUS bit */
   1877                 COMPILER_64_SET(temp_mask, 0, 0x0000000f);
   1878                 COMPILER_64_AND(*mask, temp_mask);
   1879                 break;
   1880         }
   1881     }
   1882     return 0; 
   1883 skip:
   1884     /* set mask to all 0's so test will skip it */
   1885     if (mask != NULL) {
   1886         COMPILER_64_SET(*mask, 0, 0);
   1887     }
   1888     return 1;
   1889 }
   1890 #endif /* BCM_HURRICANE_SUPPORT */
   1891 
   1892 #ifdef BCM_TRIDENT_SUPPORT
   1893 STATIC int
   1894 reg_mask_subset_trident(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   1895 {
   1896     soc_info_t *si;
   1897     uint64 temp_mask;
   1898 
   1899     switch (ainfo->reg) {
   1900     case PQEPARITYERRORADRr:
   1901     case PQ_C0_PORT_A_CMDr:
   1902     case PQ_C0_PORT_A_DATA_0r:
   1903     case PQ_C0_PORT_A_DATA_1r:
   1904     case PQ_C0_PORT_A_DATA_2r:
   1905     case PQ_C0_PORT_A_DATA_3r:
   1906     case PQ_C0_PORT_A_RADDRr:
   1907     case PQ_C0_PORT_A_WADDRr:
   1908     case PQ_C0_PORT_B_CMDr:
   1909     case PQ_C0_PORT_B_DATA_0r:
   1910     case PQ_C0_PORT_B_DATA_1r:
   1911     case PQ_C0_PORT_B_DATA_2r:
   1912     case PQ_C0_PORT_B_DATA_3r:
   1913     case PQ_C0_PORT_B_RADDRr:
   1914     case PQ_C0_PORT_B_WADDRr:
   1915     case PQ_C1_PORT_A_CMDr:
   1916     case PQ_C1_PORT_A_DATA_0r:
   1917     case PQ_C1_PORT_A_DATA_1r:
   1918     case PQ_C1_PORT_A_DATA_2r:
   1919     case PQ_C1_PORT_A_DATA_3r:
   1920     case PQ_C1_PORT_A_RADDRr:
   1921     case PQ_C1_PORT_A_WADDRr:
   1922     case PQ_C1_PORT_B_CMDr:
   1923     case PQ_C1_PORT_B_DATA_0r:
   1924     case PQ_C1_PORT_B_DATA_1r:
   1925     case PQ_C1_PORT_B_DATA_2r:
   1926     case PQ_C1_PORT_B_DATA_3r:
   1927     case PQ_C1_PORT_B_RADDRr:
   1928     case PQ_C1_PORT_B_WADDRr:
   1929     case PQ_C2_PORT_A_CMDr:
   1930     case PQ_C2_PORT_A_DATA_0r:
   1931     case PQ_C2_PORT_A_DATA_1r:
   1932     case PQ_C2_PORT_A_DATA_2r:
   1933     case PQ_C2_PORT_A_DATA_3r:
   1934     case PQ_C2_PORT_A_RADDRr:
   1935     case PQ_C2_PORT_A_WADDRr:
   1936     case PQ_C2_PORT_B_CMDr:
   1937     case PQ_C2_PORT_B_DATA_0r:
   1938     case PQ_C2_PORT_B_DATA_1r:
   1939     case PQ_C2_PORT_B_DATA_2r:
   1940     case PQ_C2_PORT_B_DATA_3r:
   1941     case PQ_C2_PORT_B_RADDRr:
   1942     case PQ_C2_PORT_B_WADDRr:
   1943     case PQ_C3_PORT_A_CMDr:
   1944     case PQ_C3_PORT_A_DATA_0r:
   1945     case PQ_C3_PORT_A_DATA_1r:
   1946     case PQ_C3_PORT_A_DATA_2r:
   1947     case PQ_C3_PORT_A_DATA_3r:
   1948     case PQ_C3_PORT_A_RADDRr:
   1949     case PQ_C3_PORT_A_WADDRr:
   1950     case PQ_C3_PORT_B_CMDr:
   1951     case PQ_C3_PORT_B_DATA_0r:
   1952     case PQ_C3_PORT_B_DATA_1r:
   1953     case PQ_C3_PORT_B_DATA_2r:
   1954     case PQ_C3_PORT_B_DATA_3r:
   1955     case PQ_C3_PORT_B_RADDRr:
   1956     case PQ_C3_PORT_B_WADDRr:
   1957     case PQ_MODULE_CONTROLr:
   1958     case PQ_PROGRAM_GOr:
   1959         goto skip;
   1960         break;
   1961     default:
   1962         break;
   1963     }
   1964 
   1965     if (!SOC_PORT_VALID(unit, ainfo->port)) {
   1966         return 0;
   1967     }
   1968 
   1969     si = &SOC_INFO(unit);
   1970 
   1971     switch (ainfo->reg) {
   1972     case XMAC_CTRLr:
   1973     case XMAC_MODEr:
   1974     case XMAC_SPARE0r:
   1975     case XMAC_SPARE1r:
   1976     case XMAC_TX_CTRLr:
   1977     case XMAC_TX_MAC_SAr:
   1978     case XMAC_RX_CTRLr:
   1979     case XMAC_RX_MAC_SAr:
   1980     case XMAC_RX_MAX_SIZEr:
   1981     case XMAC_RX_VLAN_TAGr:
   1982     case XMAC_RX_LSS_CTRLr:
   1983     case XMAC_RX_LSS_STATUSr:
   1984     case XMAC_CLEAR_RX_LSS_STATUSr:
   1985     case XMAC_PAUSE_CTRLr:
   1986     case XMAC_PFC_CTRLr:
   1987     case XMAC_PFC_TYPEr:
   1988     case XMAC_PFC_OPCODEr:
   1989     case XMAC_PFC_DAr:
   1990     case XMAC_LLFC_CTRLr:
   1991     case XMAC_TX_LLFC_MSG_FIELDSr:
   1992     case XMAC_RX_LLFC_MSG_FIELDSr:
   1993     case XMAC_HCFC_CTRLr:
   1994     case XMAC_TX_TIMESTAMP_FIFO_DATAr:
   1995     case XMAC_TX_TIMESTAMP_FIFO_STATUSr:
   1996     case XMAC_FIFO_STATUSr:
   1997     case XMAC_CLEAR_FIFO_STATUSr:
   1998     case XMAC_TX_FIFO_CREDITSr:
   1999     case XMAC_EEE_CTRLr:
   2000     case XMAC_EEE_TIMERSr:
   2001         /* Skip Xmac registers when the XLPORT is used as GE port */
   2002         if (IS_GE_PORT(unit, ainfo->port)) {
   2003             goto skip;
   2004         }
   2005         break;
   2006 
   2007 
   2008     case DROP_PKT_CNT_OVQr:
   2009         /* @OVQ_PORT_DROP_REGS (all ports except cpu port) */
   2010     case DEQ_AGINGMASKr:
   2011     case MCQ_FIFO_BASE_REGr:
   2012     case MCQ_FIFO_EMPTY_REGr:
   2013         /* PORTLIST => [1..65] */
   2014     case COSMASKr:
   2015     case MINSPCONFIGr:
   2016     case S3_CONFIGr:
   2017     case S3_CONFIG_MCr:
   2018     case S3_COSMASKr:
   2019     case S3_COSMASK_MCr:
   2020     case S3_MINSPCONFIGr:
   2021     case S3_MINSPCONFIG_MCr:
   2022     case S2_CONFIGr:
   2023     case S2_COSWEIGHTSr:
   2024     case S2_COSMASKr:
   2025     case S2_MINSPCONFIGr:
   2026     case S2_WERRCOUNTr:
   2027     case S2_S3_ROUTINGr:
   2028         /* @MMU_NO_CPU_PORTS (all ports except cpu port) */
   2029     case PORT_LLFC_CFGr:
   2030         /* @PFC_PORT_CFG_REGS (all ports except cpu port) */
   2031     case S3_MINBUCKETCONFIG_64r:
   2032     case S3_MINBUCKETr:
   2033     case S3_MAXBUCKETCONFIG_64r:
   2034     case S3_MAXBUCKETr:
   2035         /* @MMU_MTRO_S3_REG (all ports except cpu port) */
   2036     case S2_MINBUCKETCONFIG_64r:
   2037     case S2_MINBUCKETr:
   2038     case S2_MAXBUCKETCONFIG_64r:
   2039     case S2_MAXBUCKETr:
   2040         /* @MMU_MTRO_S2_REG (all ports except cpu port) */
   2041     case OVQ_MCQ_CREDITSr:
   2042     case OVQ_MCQ_STATEr:
   2043         /* @OVQ_PORT_COS_REGS (all ports except cpu port) */
   2044         if (IS_CPU_PORT(unit, ainfo->port)) {
   2045             goto skip;
   2046         }
   2047         break;
   2048 
   2049     case XPORT_TO_MMU_BKPr:
   2050         /* @PFC_PORT_STS_REGS (all ports except cpu and lb port) */
   2051     case BKPMETERINGCONFIG_64r:
   2052     case BKPMETERINGBUCKETr:
   2053     case MTRI_IFGr:
   2054         /* @MMU_MTRI_PORTS (all ports except cpu and lb port) */
   2055     case OP_UC_PORT_CONFIG_CELLr:
   2056     case OP_UC_PORT_CONFIG1_CELLr:
   2057     case OP_UC_PORT_LIMIT_COLOR_CELLr:
   2058     case OP_UC_PORT_SHARED_COUNT_CELLr:
   2059     case OP_UC_PORT_LIMIT_RESUME_COLOR_CELLr:
   2060     case UCQ_COS_EMPTY_REGr:
   2061     case PORT_SP_WRED_CONFIGr:
   2062     case PORT_SP_WRED_AVG_QSIZEr:
   2063         /* PORTLIST => [1..32,34..65] */
   2064     case OP_UC_QUEUE_MIN_COUNT_CELLr:
   2065     case OP_UC_QUEUE_SHARED_COUNT_CELLr:
   2066     case OP_UC_QUEUE_TOTAL_COUNT_CELLr:
   2067     case OP_UC_QUEUE_RESET_VALUE_CELLr:
   2068         /* @THDO_UC_PORT_COS_REGS (all ports except cpu and lb port) */
   2069     case WRED_CONFIGr:
   2070     case WRED_AVG_QSIZEr:
   2071         /* @MMU_PERPORTPERCOS_NOCPU_REGS (all ports except cpu and lb port) */
   2072         if (IS_CPU_PORT(unit, ainfo->port) || IS_LB_PORT(unit, ainfo->port)) {
   2073             goto skip;
   2074         }
   2075         break;
   2076 
   2077     case OP_EX_QUEUE_MIN_COUNT_CELLr:
   2078     case OP_EX_QUEUE_SHARED_COUNT_CELLr:
   2079     case OP_EX_QUEUE_TOTAL_COUNT_CELLr:
   2080     case OP_EX_QUEUE_RESET_VALUE_CELLr:
   2081         /* @THDO_EX_PORT_COS_REGS (extended queue ports) */
   2082     case OP_EX_PORT_CONFIG_SPID_0r:
   2083     case OP_EX_PORT_CONFIG_SPID_1r:
   2084     case OP_EX_PORT_CONFIG_SPID_2r:
   2085     case OP_EX_PORT_CONFIG_SPID_3r:
   2086     case OP_EX_PORT_CONFIG_SPID_4r:
   2087     case OP_EX_PORT_CONFIG_COS_MIN_0r:
   2088     case OP_EX_PORT_CONFIG_COS_MIN_1r:
   2089     case OP_EX_PORT_CONFIG_COS_MIN_2r:
   2090     case UCQ_EXTCOS1_EMPTY_REGr:
   2091         /* PORTLIST => [1..4,34..37] */
   2092     case DMVOQ_WRED_CONFIGr:
   2093     case VOQ_WRED_AVG_QSIZEr:
   2094         /* @MMU_PERPORTPERVOQ_NOCPU_REGS (extended queue ports) */
   2095         if (!si->port_num_ext_cosq[ainfo->port]) {
   2096             goto skip;
   2097         }
   2098         break;
   2099 
   2100     case COSWEIGHTSr:
   2101     case WERRCOUNTr:
   2102         /* @MMU_ES_REGS */
   2103         if (!IS_CPU_PORT(unit, ainfo->port)) {
   2104             if (ainfo->idx >= 7) {
   2105                 goto skip;
   2106             }
   2107         }
   2108         break;
   2109 
   2110     case S3_COSWEIGHTSr:
   2111     case S3_WERRCOUNTr:
   2112         /* @MMU_ES_S3_REGS */
   2113         if (!si->port_num_ext_cosq[ainfo->port]) {
   2114             if (IS_CPU_PORT(unit, ainfo->port) || ainfo->idx >= 8) {
   2115                 goto skip;
   2116             }
   2117         }
   2118         break;
   2119 
   2120     case MINBUCKETCONFIG_64r:
   2121     case MINBUCKETr:
   2122     case MAXBUCKETCONFIG_64r:
   2123     case MAXBUCKETr:
   2124         /* @MMU_MTRO_REGS */
   2125         if (IS_CPU_PORT(unit, ainfo->port)) {
   2126             if (ainfo->idx >= 48) {
   2127                 goto skip;
   2128             }
   2129         } else if (IS_LB_PORT(unit, ainfo->port)) {
   2130             if (ainfo->idx >= 5) {
   2131                 goto skip;
   2132             }
   2133         } else if (!si->port_num_ext_cosq[ainfo->port]) {
   2134             if (ainfo->idx >= 15) {
   2135                 goto skip;
   2136             }
   2137         }
   2138         break;
   2139 
   2140     case OP_QUEUE_CONFIG_CELLr:
   2141     case OP_QUEUE_CONFIG1_CELLr:
   2142     case OP_QUEUE_LIMIT_COLOR_CELLr:
   2143     case OP_QUEUE_RESET_OFFSET_CELLr:
   2144     case OP_QUEUE_MIN_COUNT_CELLr:
   2145     case OP_QUEUE_SHARED_COUNT_CELLr:
   2146     case OP_QUEUE_TOTAL_COUNT_CELLr:
   2147     case OP_QUEUE_RESET_VALUE_CELLr:
   2148     case OP_QUEUE_LIMIT_RESUME_COLOR_CELLr:
   2149         /* @THDO_PORT_COS_REGS */
   2150         if (!IS_CPU_PORT(unit, ainfo->port)) {
   2151             if (ainfo->idx >= 5) {
   2152                 goto skip;
   2153             }
   2154         }
   2155         break;
   2156     default:
   2157         break;
   2158     }
   2159 
   2160     if (mask != NULL) {
   2161         switch (ainfo->reg) {
   2162         case SHAPING_CONTROLr:
   2163         case RESET_ON_EMPTY_MAX_64r:
   2164             if (!si->port_num_ext_cosq[ainfo->port]) {
   2165                 COMPILER_64_SET(temp_mask, 0, 0x007fffff);
   2166                 COMPILER_64_AND(*mask, temp_mask);
   2167             }
   2168             break;
   2169         default:
   2170             break;
   2171         }
   2172     }
   2173 
   2174     return 0;
   2175 skip:
   2176     /* set mask to all 0's so test will skip it */
   2177     if (mask != NULL) {
   2178         COMPILER_64_SET(*mask, 0, 0);
   2179     }
   2180     return 1;
   2181 }
   2182 #endif /* BCM_TRIDENT_SUPPORT */
   2183 
   2184 #ifdef BCM_TRIDENT2_SUPPORT
   2185 STATIC int
   2186 reg_mask_subset_trident2(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   2187 {
   2188     soc_info_t *si;
   2189     int port, phy_port = 0, mmu_port = 0;
   2190     int pgw, xlp, blk, index;
   2191     int instance_mask = 0;
   2192 
   2193     port = ainfo->port;
   2194     if (REG_PORT_ANY != port) {
   2195         instance_mask = port & SOC_REG_ADDR_INSTANCE_MASK;
   2196         port &= (~SOC_REG_ADDR_INSTANCE_MASK);
   2197     }
   2198 
   2199     if (!instance_mask) {
   2200         if (!SOC_PORT_VALID(unit, port)) {
   2201             return 0;
   2202         }
   2203         si = &SOC_INFO(unit);
   2204         phy_port = si->port_l2p_mapping[ainfo->port];
   2205         mmu_port = si->port_p2m_mapping[phy_port];
   2206     }
   2207 
   2208     if ((ainfo->block >= 0) && !SOC_INFO(unit).block_valid[ainfo->block]) {
   2209         goto skip;
   2210     }
   2211 
   2212     switch (ainfo->reg) {
   2213     case PORT_INITIAL_COPY_COUNT_WIDTHr:
   2214     case MMU_PORT_TO_LOGIC_PORT_MAPPINGr:
   2215     case MMU_PORT_TO_PHY_PORT_MAPPINGr:
   2216     case MMU_TO_XPORT_BKPr:
   2217     case CHFC2PFC_STATEr:
   2218     case QCN_PFC_STATEr:
   2219         /* @MMU_PORT_LIST */
   2220     case XPORT_TO_MMU_BKPr:
   2221         /* @PFC_PORT_STS_REGS */
   2222     case MTRI_IFGr:
   2223         /* @MMU_MTRI_PORTS */
   2224     case THDI_INPUT_PORT_XON_ENABLESr:
   2225     case THDI_PORT_PRI_GRP0r:
   2226     case THDI_PORT_PRI_GRP1r:
   2227     case THDI_PORT_PG_SPIDr:
   2228     case THDI_PORT_LIMIT_STATESr:
   2229     case THDI_FLOW_CONTROL_XOFF_STATEr:
   2230         /* MMU_THDI_PORTS */
   2231     case THDU_PORT_E2ECC_COS_SPIDr:
   2232         /* THDU_UC_PORT_LIST */
   2233     case ASF_PORT_CFGr:
   2234     case ENQ_ASF_ERRORr:
   2235         /* @ENQ_PORT_LIST */
   2236         break;
   2237     case HSP_SCHED_PORT_CONFIGr:
   2238     case HSP_SCHED_L0_NODE_CONFIGr:
   2239     case HSP_SCHED_L0_NODE_WEIGHTr:
   2240     case HSP_SCHED_L0_NODE_CONNECTION_CONFIGr:
   2241     case HSP_SCHED_L1_NODE_CONFIGr:
   2242     case HSP_SCHED_L1_NODE_WEIGHTr:
   2243     case HSP_SCHED_L2_UC_QUEUE_CONFIGr:
   2244     case HSP_SCHED_L2_MC_QUEUE_CONFIGr:
   2245     case HSP_SCHED_L2_UC_QUEUE_WEIGHTr:
   2246     case HSP_SCHED_L2_MC_QUEUE_WEIGHTr:
   2247         /* @HSP_PORT_LIST => [0..15,64..79] */
   2248         if (!(mmu_port >= 0 && mmu_port <= 15) &&
   2249             !(mmu_port >= 64 && mmu_port <= 79)) {
   2250             goto skip;
   2251         }
   2252         break;
   2253     case MMU_THDM_DB_PORTSP_SHARED_COUNTr:
   2254     case MMU_THDM_DB_PORTSP_TOTAL_COUNTr:
   2255     case MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SELr:
   2256     case MMU_THDM_MCQE_PORTSP_SHARED_COUNTr:
   2257     case MMU_THDM_MCQE_PORTSP_TOTAL_COUNTr:
   2258     case MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SELr:
   2259         /* @THDM_PORT_LIST */
   2260         break;
   2261     case PGW_OBM0_CONTROLr:
   2262     case PGW_OBM0_SHARED_CONFIGr:
   2263     case PGW_OBM0_NIV_ETHERTYPEr:
   2264     case PGW_OBM0_PE_ETHERTYPEr:
   2265     case PGW_OBM0_OUTER_TPIDr:
   2266     case PGW_OBM0_INNER_TPIDr:
   2267     case PGW_OBM0_PRIORITY_MAPr:
   2268     case PGW_OBM0_THRESHOLDr:
   2269     case PGW_OBM0_THRESHOLD2r:
   2270     case PGW_OBM0_LOW_PRI_DROP_PROBr:
   2271     case PGW_OBM0_TM_CONTROLr:
   2272     case PGW_OBM0_ECC_ENABLEr:
   2273     case PGW_OBM0_ECC_STATUSr:
   2274     case PGW_OBM0_USE_COUNTERr:
   2275     case PGW_OBM0_MAX_USAGEr:
   2276     case PGW_OBM0_LOW_PRI_PKT_DROPr:
   2277     case PGW_OBM0_LOW_PRI_BYTE_DROPr:
   2278     case PGW_OBM0_HIGH_PRI_PKT_DROPr:
   2279     case PGW_OBM0_HIGH_PRI_BYTE_DROPr:
   2280     case PGW_OBM1_CONTROLr:
   2281     case PGW_OBM1_SHARED_CONFIGr:
   2282     case PGW_OBM1_NIV_ETHERTYPEr:
   2283     case PGW_OBM1_PE_ETHERTYPEr:
   2284     case PGW_OBM1_OUTER_TPIDr:
   2285     case PGW_OBM1_INNER_TPIDr:
   2286     case PGW_OBM1_PRIORITY_MAPr:
   2287     case PGW_OBM1_THRESHOLDr:
   2288     case PGW_OBM1_THRESHOLD2r:
   2289     case PGW_OBM1_LOW_PRI_DROP_PROBr:
   2290     case PGW_OBM1_TM_CONTROLr:
   2291     case PGW_OBM1_ECC_ENABLEr:
   2292     case PGW_OBM1_ECC_STATUSr:
   2293     case PGW_OBM1_USE_COUNTERr:
   2294     case PGW_OBM1_MAX_USAGEr:
   2295     case PGW_OBM1_LOW_PRI_PKT_DROPr:
   2296     case PGW_OBM1_LOW_PRI_BYTE_DROPr:
   2297     case PGW_OBM1_HIGH_PRI_PKT_DROPr:
   2298     case PGW_OBM1_HIGH_PRI_BYTE_DROPr:
   2299     case PGW_OBM2_CONTROLr:
   2300     case PGW_OBM2_SHARED_CONFIGr:
   2301     case PGW_OBM2_NIV_ETHERTYPEr:
   2302     case PGW_OBM2_PE_ETHERTYPEr:
   2303     case PGW_OBM2_OUTER_TPIDr:
   2304     case PGW_OBM2_INNER_TPIDr:
   2305     case PGW_OBM2_PRIORITY_MAPr:
   2306     case PGW_OBM2_THRESHOLDr:
   2307     case PGW_OBM2_THRESHOLD2r:
   2308     case PGW_OBM2_LOW_PRI_DROP_PROBr:
   2309     case PGW_OBM2_TM_CONTROLr:
   2310     case PGW_OBM2_ECC_ENABLEr:
   2311     case PGW_OBM2_ECC_STATUSr:
   2312     case PGW_OBM2_USE_COUNTERr:
   2313     case PGW_OBM2_MAX_USAGEr:
   2314     case PGW_OBM2_LOW_PRI_PKT_DROPr:
   2315     case PGW_OBM2_LOW_PRI_BYTE_DROPr:
   2316     case PGW_OBM2_HIGH_PRI_PKT_DROPr:
   2317     case PGW_OBM2_HIGH_PRI_BYTE_DROPr:
   2318     case PGW_OBM3_CONTROLr:
   2319     case PGW_OBM3_SHARED_CONFIGr:
   2320     case PGW_OBM3_NIV_ETHERTYPEr:
   2321     case PGW_OBM3_PE_ETHERTYPEr:
   2322     case PGW_OBM3_OUTER_TPIDr:
   2323     case PGW_OBM3_INNER_TPIDr:
   2324     case PGW_OBM3_PRIORITY_MAPr:
   2325     case PGW_OBM3_THRESHOLDr:
   2326     case PGW_OBM3_THRESHOLD2r:
   2327     case PGW_OBM3_LOW_PRI_DROP_PROBr:
   2328     case PGW_OBM3_TM_CONTROLr:
   2329     case PGW_OBM3_ECC_ENABLEr:
   2330     case PGW_OBM3_ECC_STATUSr:
   2331     case PGW_OBM3_USE_COUNTERr:
   2332     case PGW_OBM3_MAX_USAGEr:
   2333     case PGW_OBM3_LOW_PRI_PKT_DROPr:
   2334     case PGW_OBM3_LOW_PRI_BYTE_DROPr:
   2335     case PGW_OBM3_HIGH_PRI_PKT_DROPr:
   2336     case PGW_OBM3_HIGH_PRI_BYTE_DROPr:
   2337         switch (ainfo->reg) {
   2338         case PGW_OBM0_CONTROLr:
   2339         case PGW_OBM0_SHARED_CONFIGr:
   2340         case PGW_OBM0_NIV_ETHERTYPEr:
   2341         case PGW_OBM0_PE_ETHERTYPEr:
   2342         case PGW_OBM0_OUTER_TPIDr:
   2343         case PGW_OBM0_INNER_TPIDr:
   2344         case PGW_OBM0_PRIORITY_MAPr:
   2345         case PGW_OBM0_THRESHOLDr:
   2346         case PGW_OBM0_THRESHOLD2r:
   2347         case PGW_OBM0_LOW_PRI_DROP_PROBr:
   2348         case PGW_OBM0_TM_CONTROLr:
   2349         case PGW_OBM0_ECC_ENABLEr:
   2350         case PGW_OBM0_ECC_STATUSr:
   2351         case PGW_OBM0_USE_COUNTERr:
   2352         case PGW_OBM0_MAX_USAGEr:
   2353         case PGW_OBM0_LOW_PRI_PKT_DROPr:
   2354         case PGW_OBM0_LOW_PRI_BYTE_DROPr:
   2355         case PGW_OBM0_HIGH_PRI_PKT_DROPr:
   2356         case PGW_OBM0_HIGH_PRI_BYTE_DROPr:
   2357             xlp = 0;
   2358             break;
   2359         case PGW_OBM1_CONTROLr:
   2360         case PGW_OBM1_SHARED_CONFIGr:
   2361         case PGW_OBM1_NIV_ETHERTYPEr:
   2362         case PGW_OBM1_PE_ETHERTYPEr:
   2363         case PGW_OBM1_OUTER_TPIDr:
   2364         case PGW_OBM1_INNER_TPIDr:
   2365         case PGW_OBM1_PRIORITY_MAPr:
   2366         case PGW_OBM1_THRESHOLDr:
   2367         case PGW_OBM1_THRESHOLD2r:
   2368         case PGW_OBM1_LOW_PRI_DROP_PROBr:
   2369         case PGW_OBM1_TM_CONTROLr:
   2370         case PGW_OBM1_ECC_ENABLEr:
   2371         case PGW_OBM1_ECC_STATUSr:
   2372         case PGW_OBM1_USE_COUNTERr:
   2373         case PGW_OBM1_MAX_USAGEr:
   2374         case PGW_OBM1_LOW_PRI_PKT_DROPr:
   2375         case PGW_OBM1_LOW_PRI_BYTE_DROPr:
   2376         case PGW_OBM1_HIGH_PRI_PKT_DROPr:
   2377         case PGW_OBM1_HIGH_PRI_BYTE_DROPr:
   2378             xlp = 1;
   2379             break;
   2380         case PGW_OBM2_CONTROLr:
   2381         case PGW_OBM2_SHARED_CONFIGr:
   2382         case PGW_OBM2_NIV_ETHERTYPEr:
   2383         case PGW_OBM2_PE_ETHERTYPEr:
   2384         case PGW_OBM2_OUTER_TPIDr:
   2385         case PGW_OBM2_INNER_TPIDr:
   2386         case PGW_OBM2_PRIORITY_MAPr:
   2387         case PGW_OBM2_THRESHOLDr:
   2388         case PGW_OBM2_THRESHOLD2r:
   2389         case PGW_OBM2_LOW_PRI_DROP_PROBr:
   2390         case PGW_OBM2_TM_CONTROLr:
   2391         case PGW_OBM2_ECC_ENABLEr:
   2392         case PGW_OBM2_ECC_STATUSr:
   2393         case PGW_OBM2_USE_COUNTERr:
   2394         case PGW_OBM2_MAX_USAGEr:
   2395         case PGW_OBM2_LOW_PRI_PKT_DROPr:
   2396         case PGW_OBM2_LOW_PRI_BYTE_DROPr:
   2397         case PGW_OBM2_HIGH_PRI_PKT_DROPr:
   2398         case PGW_OBM2_HIGH_PRI_BYTE_DROPr:
   2399             xlp = 2;
   2400             break;
   2401         case PGW_OBM3_CONTROLr:
   2402         case PGW_OBM3_SHARED_CONFIGr:
   2403         case PGW_OBM3_NIV_ETHERTYPEr:
   2404         case PGW_OBM3_PE_ETHERTYPEr:
   2405         case PGW_OBM3_OUTER_TPIDr:
   2406         case PGW_OBM3_INNER_TPIDr:
   2407         case PGW_OBM3_PRIORITY_MAPr:
   2408         case PGW_OBM3_THRESHOLDr:
   2409         case PGW_OBM3_THRESHOLD2r:
   2410         case PGW_OBM3_LOW_PRI_DROP_PROBr:
   2411         case PGW_OBM3_TM_CONTROLr:
   2412         case PGW_OBM3_ECC_ENABLEr:
   2413         case PGW_OBM3_ECC_STATUSr:
   2414         case PGW_OBM3_USE_COUNTERr:
   2415         case PGW_OBM3_MAX_USAGEr:
   2416         case PGW_OBM3_LOW_PRI_PKT_DROPr:
   2417         case PGW_OBM3_LOW_PRI_BYTE_DROPr:
   2418         case PGW_OBM3_HIGH_PRI_PKT_DROPr:
   2419         case PGW_OBM3_HIGH_PRI_BYTE_DROPr:
   2420             xlp = 3;
   2421             break;
   2422         default:
   2423             return SOC_E_INTERNAL;
   2424         }
   2425         pgw = port;
   2426         index = pgw * 4 + xlp;
   2427         for (blk = 0; SOC_BLOCK_TYPE(unit, blk) >= 0; blk++) {
   2428             if (SOC_BLOCK_TYPE(unit, blk) != SOC_BLK_XLPORT) {
   2429                 continue;
   2430             }
   2431             if (SOC_BLOCK_NUMBER(unit, blk) == index) {
   2432                 if (!SOC_INFO(unit).block_valid[blk]) {
   2433                     goto skip;
   2434                 }
   2435             }
   2436         }
   2437         break;
   2438     default:
   2439         break;
   2440     }
   2441 
   2442     return 0;
   2443 skip:
   2444     /* set mask to all 0's so test will skip it */
   2445     if (mask != NULL) {
   2446         COMPILER_64_SET(*mask, 0, 0);
   2447     }
   2448     return 1;
   2449 }
   2450 #endif /* BCM_TRIDENT2_SUPPORT */
   2451 #ifdef BCM_TOMAHAWK3_SUPPORT
   2452 STATIC int
   2453 reg_mask_subset_tomahawk3(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   2454 {
   2455     /* Enable all register accesses */
   2456     soc_info_t *si;
   2457     int phy_port, port_value;
   2458     soc_reg_t reg=ainfo->reg;
   2459     soc_reg_t reg_excep_list[]={MMU_CRB_DEVICE_PORT_TO_MMU_PORT_MAPPINGr,
   2460                                 MMU_RQE_REPL_PORT_AGG_MAPr};
   2461     int reg_index, num_regs, add_exception = 0;
   2462 
   2463 
   2464     if (!SOC_PORT_VALID(unit, ainfo->port)) {
   2465            return 0;
   2466     }
   2467     si = &SOC_INFO(unit);
   2468     if (SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_GLB) ||
   2469         SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_ITM) ||
   2470         SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_EB)) {
   2471         num_regs = sizeof(reg_excep_list) / sizeof(soc_reg_t);
   2472         for(reg_index = 0;reg_index < num_regs;reg_index++) {
   2473             if (reg_excep_list[reg_index] == reg) {
   2474                 add_exception = 1;
   2475                 break;
   2476             }
   2477         }
   2478         if (add_exception) {
   2479             port_value = ainfo->port;
   2480         } else {
   2481             phy_port = si->port_l2p_mapping[ainfo->port];
   2482             port_value = si->port_p2m_mapping[phy_port];
   2483         }
   2484     } else {
   2485         port_value = ainfo->port;
   2486     }
   2487     if (!SOC_REG_PORT_IDX_VALID(unit, reg, port_value, ainfo->idx)) {
   2488         goto skip;
   2489     }
   2490 
   2491     return 0;
   2492 
   2493 skip:
   2494     /* set mask to all 0's so test will skip it */
   2495     if (mask != NULL) {
   2496         COMPILER_64_SET(*mask, 0, 0);
   2497     }
   2498     return 1;
   2499 
   2500 }
   2501 #endif
   2502 
   2503 #ifdef BCM_TOMAHAWK_SUPPORT
   2504 
   2505 STATIC int
   2506 reg_mask_subset_tomahawk(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   2507 {
   2508     soc_info_t *si;
   2509     soc_reg_t reg;
   2510     int phy_port, port_value, inst;
   2511     int instance_mask = 0;
   2512     int xpe, acc_type, base_type;
   2513     soc_reg_info_t *reginfo;
   2514 
   2515     reg = ainfo->reg;
   2516     reginfo = &SOC_REG_INFO(unit, reg);
   2517 
   2518     if (REG_PORT_ANY != ainfo->port) {
   2519         instance_mask = ainfo->port & SOC_REG_ADDR_INSTANCE_MASK;
   2520         if (instance_mask) {
   2521             inst = ainfo->port & ~SOC_REG_ADDR_INSTANCE_MASK;
   2522             if (SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_XPE)) {
   2523                 if (SOC_REG_UNIQUE_ACC(unit, reg) != NULL) {
   2524                     switch (reginfo->regtype) {
   2525                     case soc_layerreg:
   2526                         break;
   2527                     default:
   2528                         reg = SOC_REG_UNIQUE_ACC(unit, reg)[0];
   2529                         break;
   2530                     }
   2531                 }
   2532                 acc_type = SOC_REG_ACC_TYPE(unit, reg);
   2533                 xpe = acc_type < SOC_MAX_NUM_PIPES ? acc_type : -1;
   2534                 base_type = SOC_REG_BASE_TYPE(unit, reg);
   2535                 if (soc_tomahawk_xpe_base_index_check(unit, base_type, xpe,
   2536                                                       inst, NULL) < 0) {
   2537                     goto skip;
   2538                 }
   2539             } else if (SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_SC)) {
   2540                 if (SOC_REG_UNIQUE_ACC(unit, reg) != NULL) {
   2541                     reg = SOC_REG_UNIQUE_ACC(unit, reg)[0];
   2542                 }
   2543                 acc_type = SOC_REG_ACC_TYPE(unit, reg);
   2544                 xpe = acc_type < SOC_MAX_NUM_PIPES ? acc_type : -1;
   2545                 base_type = SOC_REG_BASE_TYPE(unit, reg);
   2546                 if (soc_tomahawk_sc_base_index_check(unit, base_type, xpe,
   2547                                                      inst, NULL) < 0) {
   2548                     goto skip;
   2549                 }
   2550 #ifdef BCM_TOMAHAWK2_SUPPORT
   2551             } else if (SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_SED)) {
   2552                 if (SOC_REG_UNIQUE_ACC(unit, reg) != NULL) {
   2553                     reg = SOC_REG_UNIQUE_ACC(unit, reg)[0];
   2554                 }
   2555                 acc_type = SOC_REG_ACC_TYPE(unit, reg);
   2556                 xpe = acc_type < SOC_MAX_NUM_PIPES ? acc_type : -1;
   2557                 base_type = SOC_REG_BASE_TYPE(unit, reg);
   2558                 if (soc_tomahawk2_sed_base_index_check(unit, base_type, xpe,
   2559                                                        inst, NULL) < 0) {
   2560                     goto skip;
   2561                 }
   2562 #endif /* BCM_TOMAHAWK2_SUPPORT */
   2563             }
   2564         } else {
   2565             if (!SOC_PORT_VALID(unit, ainfo->port)) {
   2566                 return 0;
   2567             }
   2568             si = &SOC_INFO(unit);
   2569             if (SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_GLB) ||
   2570                 SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_XPE) ||
   2571                 SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_SED) ||
   2572                 SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_MMU_SC)) {
   2573                 phy_port = si->port_l2p_mapping[ainfo->port];
   2574                 port_value = si->port_p2m_mapping[phy_port];
   2575             } else {
   2576                 port_value = ainfo->port;
   2577             }
   2578             if (!SOC_REG_PORT_IDX_VALID(unit, reg, port_value, ainfo->idx)) {
   2579                 goto skip;
   2580             }
   2581         }
   2582     } else {
   2583 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT)
   2584         if (SOC_IS_TOMAHAWK2(unit) || SOC_IS_TRIDENT3X(unit)) {
   2585             if (SOC_REG_BLOCK_IN_LIST(unit, reg, SOC_BLK_OTPC)) {
   2586                 inst = SOC_BLOCK_NUMBER(unit, ainfo->block);
   2587                 /* Can not read OTPC1 registers */
   2588                 if (inst == 1) {
   2589                     goto skip;
   2590                 }
   2591             }
   2592         }
   2593 #endif /* BCM_TOMAHAWK2_SUPPORT || BCM_TRIDENT3_SUPPORT*/
   2594     }
   2595 
   2596     if (SOC_IS_TRIDENT3X(unit)) {
   2597         switch (ainfo->reg) {
   2598             case XLPORT_MIB_RSC_RAM_CONTROLr:
   2599             /* RH_DLB_SELECTION field in ENHANCED_HASHING_CONTROL needs to be set to 1
   2600              *  in oder to use RH. This can't be set by default to 1 in init time.
   2601              *  Hence skip RH related following registers during test.
   2602              */
   2603             case RH_ECMP1_DROPSr:
   2604             case RH_ECMP1_DROPS_PIPE0r:
   2605             case RH_ECMP1_DROPS_PIPE1r:
   2606             case RH_ECMP2_DROPSr:
   2607             case RH_ECMP2_DROPS_PIPE0r:
   2608             case RH_ECMP2_DROPS_PIPE1r:
   2609             case RH_HGT_DROPSr:
   2610             case RH_HGT_DROPS_PIPE0r:
   2611             case RH_HGT_DROPS_PIPE1r:
   2612             case RH_LAG_DROPSr:
   2613             case RH_LAG_DROPS_PIPE0r:
   2614             case RH_LAG_DROPS_PIPE1r:
   2615             /* CCH psuedo registers need to be skipped */
   2616             case FLEXIBLE_IPV6_EXT_HDRr:
   2617             case ING_FCOE_ETHERTYPEr:
   2618             case ING_L2_TUNNEL_PARSE_CONTROLr:
   2619             case MIM_ETHERTYPEr:
   2620             case ING_PACKET_PROCESSING_CONTROL_0r:
   2621             case ING_PACKET_PROCESSING_CONTROL_1r:
   2622 #ifdef BCM_HELIX5_SUPPORT
   2623            case TOP_XG_PLL0_CTRL_0r:
   2624            case TOP_XG_PLL0_CTRL_1r:
   2625            case TOP_XG_PLL0_CTRL_2r:
   2626            case TOP_XG_PLL0_CTRL_3r:
   2627            case TOP_XG_PLL0_CTRL_4r:
   2628            case TOP_XG_PLL0_CTRL_5r:
   2629            case TOP_XG_PLL0_CTRL_6r:
   2630            case TOP_XG_PLL0_CTRL_7r:
   2631            case TOP_XG_PLL0_CTRL_8r:
   2632            case TOP_XG_PLL0_CTRL_9r:
   2633            case TOP_XG_PLL0_CTRL_10r:
   2634            case TOP_XG_PLL0_CTRL_11r:
   2635            case TOP_XG_PLL0_CTRL_12r:
   2636            case TOP_XG_PLL0_CTRL_13r:
   2637            case TOP_XG_PLL0_STATUSr:
   2638            case TOP_XG_PLL1_CTRL_0r:
   2639            case TOP_XG_PLL1_CTRL_1r:
   2640            case TOP_XG_PLL1_CTRL_2r:
   2641            case TOP_XG_PLL1_CTRL_3r:
   2642            case TOP_XG_PLL1_CTRL_4r:
   2643            case TOP_XG_PLL1_CTRL_5r:
   2644            case TOP_XG_PLL1_CTRL_6r:
   2645            case TOP_XG_PLL1_CTRL_7r:
   2646            case TOP_XG_PLL1_CTRL_8r:
   2647            case TOP_XG_PLL1_CTRL_9r:
   2648            case TOP_XG_PLL1_CTRL_10r:
   2649            case TOP_XG_PLL1_CTRL_11r:
   2650            case TOP_XG_PLL1_CTRL_12r:
   2651            case TOP_XG_PLL1_CTRL_13r:
   2652            case TOP_XG_PLL1_STATUSr:
   2653            case TOP_HW_TAP_CONTROLr:
   2654 #endif
   2655                 goto skip;
   2656             default:
   2657                 if (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_AVS)) {
   2658                     /* Skip AVS block registers */
   2659                    goto skip;
   2660                 }
   2661                 break;
   2662         }
   2663     }
   2664  
   2665     return 0;
   2666 
   2667 skip:
   2668     /* set mask to all 0's so test will skip it */
   2669     if (mask != NULL) {
   2670         COMPILER_64_SET(*mask, 0, 0);
   2671     }
   2672     return 1;
   2673 }
   2674 #endif /* BCM_TOMAHAWK_SUPPORT */
   2675 
   2676 #ifdef BCM_APACHE_SUPPORT
   2677 STATIC int
   2678 reg_mask_subset_apache(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   2679 {
   2680     int port, instance_mask = 0;
   2681 
   2682     port = ainfo->port;
   2683 
   2684     if (REG_PORT_ANY != port) {
   2685 
   2686         instance_mask = port & SOC_REG_ADDR_INSTANCE_MASK;
   2687         if (instance_mask) {
   2688             port &= (~SOC_REG_ADDR_INSTANCE_MASK);
   2689         }
   2690 
   2691         /* CLPORT registers - Only CL and CLG2 ports */
   2692         if (((ainfo->reg >= CLPORT_CNTMAXSIZEr) &&
   2693              (ainfo->reg <= CLPORT_XGXS_COUNTER_MODEr)) &&
   2694             (!(IS_CL_PORT(unit, port) || IS_CLG2_PORT(unit, port)))) {
   2695 
   2696             goto skip;
   2697         }
   2698 
   2699         /* CLMAC registers - Only CL ports */
   2700         if (((ainfo->reg >= CLMAC_CLEAR_ECC_STATUSr) &&
   2701              (ainfo->reg <= CLMAC_TX_MAC_SAr)) &&
   2702             (!IS_CL_PORT(unit, port))) {
   2703 
   2704             goto skip;
   2705         }
   2706 
   2707         /* CLG2MAC registers - Only CLG2 ports */
   2708         if (((ainfo->reg >= CLG2MAC_CLEAR_ECC_STATUSr) &&
   2709              (ainfo->reg <= CLG2MAC_TX_MAC_SAr)) &&
   2710             (!IS_CLG2_PORT(unit, port))) {
   2711 
   2712             goto skip;
   2713         }
   2714 
   2715 
   2716         /* XLPORT registers - Only XL, XLB0 and CXX ports */
   2717         if (((ainfo->reg >= XLPORT_CNTMAXSIZEr) &&
   2718              (ainfo->reg <= XLPORT_XGXS_COUNTER_MODEr)) &&
   2719             (!(IS_XL_PORT(unit, port) || IS_XLB0_PORT(unit, port) || IS_CXX_PORT(unit, port)))) {
   2720 
   2721             goto skip;
   2722         }
   2723 
   2724         /* XLMAC registers - Only XL ports */
   2725         if (((ainfo->reg >= XLMAC_CLEAR_ECC_STATUSr) &&
   2726              (ainfo->reg <= XLMAC_TX_MAC_SAr)) &&
   2727             (!IS_XL_PORT(unit, port))) {
   2728 
   2729             goto skip;
   2730         }
   2731 
   2732         /* XLMAC_B0 registers - Only XLB0 ports */
   2733         if (((ainfo->reg >= XLMAC_B0_CLEAR_ECC_STATUSr) &&
   2734              (ainfo->reg <= XLMAC_B0_TX_MAC_SAr)) &&
   2735             (!IS_XLB0_PORT(unit, port))) {
   2736 
   2737             goto skip;
   2738         }
   2739 
   2740         /* SOC_REG_PORT_IDX_VALID check should be done with appropriate
   2741          * port type; mmu port for mmu block registers. phy port for port registers
   2742  */
   2743         if (SOC_REG_BLOCK_IN_LIST(unit, ainfo->reg, SOC_BLK_MMU)) {
   2744             /* mmu port */
   2745             port = SOC_INFO(unit).port_p2m_mapping[SOC_INFO(unit).port_l2p_mapping[port]];
   2746         } else if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, ainfo->reg).block, SOC_BLK_PORT)) {
   2747             /* phy port */
   2748             port = SOC_INFO(unit).port_l2p_mapping[port];
   2749         }
   2750 
   2751         /* Per-Port register is not implemented in the regsiter array */
   2752         if (!SOC_REG_PORT_IDX_VALID(unit,ainfo->reg, port, ainfo->idx)) {
   2753             goto skip;
   2754         }
   2755 
   2756     } else {
   2757         if (!SOC_INFO(unit).block_valid[ainfo->block]) {
   2758             goto skip;
   2759         }
   2760     }
   2761 
   2762     switch (ainfo->reg) {
   2763 
   2764 #ifdef TR_TESTS_EXCLUDE
   2765     case CFAPCONFIGr:
   2766     case CFAPFULLSETPOINTr:
   2767     case CFAPFULLRESETPOINTr:
   2768         /* Only a few values (See regsfile) can be set. Skip. */
   2769         goto skip;
   2770 #endif
   2771     case AVS_REG_PMB_SLAVE_AVS_PWD_ACC_CONTROLr:
   2772     case AVS_REG_PMB_SLAVE_AVS_PWD_CONTROLr:
   2773     case AVS_REG_PMB_SLAVE_AVS_ROSC_CONTROLr:
   2774     case AVS_REG_PMB_SLAVE_AVS_ROSC_H_THRESHOLDr:
   2775     case AVS_REG_PMB_SLAVE_AVS_ROSC_S_THRESHOLDr:
   2776     case AVS_REG_PMB_SLAVE_BPCM_CONTROLr:
   2777         /* ARS wrappers stubbed out in QT. Register access will fail */
   2778          if (SAL_BOOT_QUICKTURN) {
   2779              goto skip;
   2780          }
   2781          break;  
   2782 #if defined(BCM_MONTEREY_SUPPORT) 
   2783      case SP_GLB_MIB_CTRLr :
   2784      case XLPORT_TXPI_CSR_CTRL1r :
   2785               if (SOC_IS_MONTEREY(unit)) { 
   2786                   goto skip;
   2787                } 
   2788 #endif 
   2789     default:
   2790         break;
   2791     }
   2792 
   2793     return 0;
   2794 
   2795 skip:
   2796 
   2797     /* set mask to all 0's so test will skip it */
   2798     if (mask != NULL) {
   2799         COMPILER_64_SET(*mask, 0, 0);
   2800     }
   2801     return 1;
   2802 }
   2803 #endif /* BCM_APACHE_SUPPORT */
   2804 
   2805 #ifdef BCM_TRIUMPH3_SUPPORT
   2806 STATIC int
   2807 reg_mask_subset_tr3(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   2808 {
   2809     pbmp_t *tr3_8mcq_ports_32_35;
   2810     pbmp_t *tr3_8mcq_ports_36_39;
   2811     pbmp_t *tr3_10mcq_ports_40_47;
   2812     pbmp_t *tr3_10mcq_ports_48_55;
   2813     pbmp_t *tr3_wlan_encap_ports;
   2814     pbmp_t *tr3_pass_thru_ports;
   2815     pbmp_t *tr3_cpu_ports;
   2816     pbmp_t *tr3_high_speed_ports;
   2817     pbmp_t *tr3_all_ports;
   2818     pbmp_t *tr3_cl_ports;
   2819     pbmp_t *tr3_repl_head_ports;
   2820     pbmp_t *tr3_ports_none;
   2821 #define _REG_MASK_SUBSET_MAX_TR3 12
   2822     pbmp_t **mask_map_arr[_REG_MASK_SUBSET_MAX_TR3];
   2823     int i, count = _REG_MASK_SUBSET_MAX_TR3;
   2824     uint64 temp_mask;
   2825     pbmp_t *pbmp;
   2826     soc_port_t port;
   2827     uint16 dev_id;
   2828     uint8 rev_id;
   2829 
   2830     mask_map_arr[0] = &tr3_8mcq_ports_32_35;
   2831     mask_map_arr[1] = &tr3_8mcq_ports_36_39;
   2832     mask_map_arr[2] = &tr3_10mcq_ports_40_47;
   2833     mask_map_arr[3] = &tr3_10mcq_ports_48_55;
   2834     mask_map_arr[4] = &tr3_wlan_encap_ports;
   2835     mask_map_arr[5] = &tr3_pass_thru_ports;
   2836     mask_map_arr[6] = &tr3_cpu_ports;
   2837     mask_map_arr[7] = &tr3_high_speed_ports;
   2838     mask_map_arr[8] = &tr3_all_ports;
   2839     mask_map_arr[9] = &tr3_cl_ports;
   2840     mask_map_arr[10] = &tr3_repl_head_ports;
   2841     mask_map_arr[11] = &tr3_ports_none;
   2842     if (NULL == SOC_REG_MASK_SUBSET(unit)) {
   2843         soc_info_t *si = &SOC_INFO(unit);
   2844         soc_port_t mmu_port, phy_port;
   2845         
   2846         _INIT_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
   2847 
   2848         /* 8MCQ = MMU[32-35] */
   2849         SOC_PBMP_CLEAR(*tr3_8mcq_ports_32_35);
   2850         for (mmu_port = 32; mmu_port < 36; mmu_port++) {
   2851             phy_port = si->port_m2p_mapping[mmu_port];
   2852             port = (phy_port == -1) ? -1 : si->port_p2l_mapping[phy_port];
   2853             if (-1 != port) {
   2854                 SOC_PBMP_PORT_ADD(*tr3_8mcq_ports_32_35, port);
   2855             }
   2856         }
   2857 
   2858         /* 8MCQ = MMU[36-39] */
   2859         SOC_PBMP_CLEAR(*tr3_8mcq_ports_36_39);
   2860         for (mmu_port = 36; mmu_port < 40; mmu_port++) {
   2861             phy_port = si->port_m2p_mapping[mmu_port];
   2862             port = (phy_port == -1) ? -1 : si->port_p2l_mapping[phy_port];
   2863             if (-1 != port) {
   2864                 SOC_PBMP_PORT_ADD(*tr3_8mcq_ports_36_39, port);
   2865             }
   2866         }
   2867 
   2868         /* 10MCQ = MMU[40-55] */
   2869         SOC_PBMP_CLEAR(*tr3_10mcq_ports_40_47);
   2870         for (mmu_port = 40; mmu_port < 48; mmu_port++) {
   2871             phy_port = si->port_m2p_mapping[mmu_port];
   2872             port = (phy_port == -1) ? -1 : si->port_p2l_mapping[phy_port];
   2873             if (-1 != port) {
   2874                 SOC_PBMP_PORT_ADD(*tr3_10mcq_ports_40_47, port);
   2875             }
   2876         }
   2877 
   2878         SOC_PBMP_CLEAR(*tr3_10mcq_ports_48_55);
   2879         for (mmu_port = 48; mmu_port < 56; mmu_port++) {
   2880             phy_port = si->port_m2p_mapping[mmu_port];
   2881             port = (phy_port == -1) ? -1 : si->port_p2l_mapping[phy_port];
   2882             if (-1 != port) {
   2883                 SOC_PBMP_PORT_ADD(*tr3_10mcq_ports_48_55, port);
   2884             }
   2885         }
   2886 
   2887         /* CPU port = MMU[59] */
   2888         SOC_PBMP_CLEAR(*tr3_cpu_ports);
   2889         SOC_PBMP_PORT_ADD(*tr3_cpu_ports, CMIC_PORT(unit));
   2890 
   2891         /* WLAN Encap = MMU[56] */
   2892         SOC_PBMP_CLEAR(*tr3_wlan_encap_ports);
   2893         SOC_PBMP_PORT_ADD(*tr3_wlan_encap_ports,
   2894                           AXP_PORT(unit, SOC_AXP_NLF_WLAN_ENCAP));
   2895 
   2896         /* Pass thru = MMU[58] */
   2897         SOC_PBMP_CLEAR(*tr3_pass_thru_ports);
   2898         SOC_PBMP_PORT_ADD(*tr3_pass_thru_ports,
   2899                           AXP_PORT(unit, SOC_AXP_NLF_PASSTHRU));
   2900 
   2901         /* High speed ports = MMU[48,52] */
   2902         SOC_PBMP_CLEAR(*tr3_high_speed_ports);
   2903         phy_port = si->port_m2p_mapping[48];
   2904         port = (phy_port == -1) ? -1 : si->port_p2l_mapping[phy_port];
   2905         if (-1 != port) {
   2906             SOC_PBMP_PORT_ADD(*tr3_high_speed_ports, port);
   2907         }
   2908         phy_port = si->port_m2p_mapping[52];
   2909         port = (phy_port == -1) ? -1 : si->port_p2l_mapping[phy_port];
   2910         if (-1 != port) {
   2911             SOC_PBMP_PORT_ADD(*tr3_high_speed_ports, port);
   2912         }
   2913 
   2914         /* CE ports */
   2915         SOC_PBMP_CLEAR(*tr3_cl_ports);
   2916         PBMP_CE_ITER(unit, port) {
   2917             SOC_PBMP_PORT_ADD(*tr3_cl_ports, port);
   2918         }
   2919         PBMP_HG_ITER(unit, port) {
   2920             if (si->port_speed_max[port] >= 100000) {
   2921                 SOC_PBMP_PORT_ADD(*tr3_cl_ports, port);
   2922             }
   2923         }
   2924 
   2925         /* All ports */
   2926         SOC_PBMP_CLEAR(*tr3_all_ports); 
   2927         SOC_PBMP_ASSIGN(*tr3_all_ports, PBMP_ALL(unit)); 
   2928 
   2929         /* Ports for REPL_HEAD_PTR_REPLACE */
   2930         SOC_PBMP_ASSIGN(*tr3_repl_head_ports, *tr3_all_ports);
   2931         SOC_PBMP_PORT_REMOVE(*tr3_repl_head_ports, CMIC_PORT(unit));
   2932 
   2933         SOC_PBMP_CLEAR(*tr3_ports_none);
   2934     }
   2935 
   2936     /* Non-port register */
   2937     if (mask != NULL) {
   2938         switch(ainfo->reg) {
   2939         case ETU_CONFIG0r:
   2940             if (!soc_feature(unit, soc_feature_esm_support)) {
   2941                  goto skip;
   2942 	    }
   2943             if (!soc_feature(unit, soc_feature_etu_support)) {
   2944                 /* HBIT_MEM_PSM_VDD bits are stuck without ESM */
   2945                 COMPILER_64_SET(temp_mask, 0, 0x00027fff);
   2946                 COMPILER_64_AND(*mask, temp_mask);
   2947 	     }
   2948             break;
   2949         case TOP_XG_PLL0_CTRL_0r:
   2950         case TOP_XG_PLL1_CTRL_0r:
   2951         case TOP_XG_PLL2_CTRL_0r:
   2952         case TOP_XG_PLL3_CTRL_0r:
   2953         case AUX_ARB_CONTROL_2r:
   2954         case TOP_TAP_CONTROLr:
   2955             
   2956             goto skip;
   2957        case ESMIF_CNP_SEARCH_REQ_COUNTr:
   2958        case ESMIF_CUR_PENDING_COST0r:
   2959        case ESMIF_CUR_PENDING_COST1r:
   2960        case ESMIF_CUR_PENDING_COST2r:
   2961        case ESMIF_DROP_COUNTr:
   2962        case ESMIF_INIT_CONFIGr:
   2963        case ESMIF_MAX_PENDING_COST0r:
   2964        case ESMIF_MAX_PENDING_COST1r:
   2965        case ESMIF_MAX_PENDING_COST2r:
   2966        case ESMIF_MULTI_ECC_PARITY_ERROR_LOGr:
   2967        case ESM_ADM_CTRL_FIFO_STATUSr:
   2968        case ESM_ADM_THR_DROP_ALL_COST0r:
   2969        case ESM_ADM_THR_DROP_ALL_COST1r:
   2970        case ESM_ADM_THR_DROP_ALL_COST2r:
   2971        case ESM_ADM_THR_DROP_ALL_RESET_COST0r:
   2972        case ESM_ADM_THR_DROP_ALL_RESET_COST1r:
   2973        case ESM_ADM_THR_DROP_ALL_RESET_COST2r:
   2974        case ESM_ADM_THR_DROP_OPT_COST0r:
   2975        case ESM_ADM_THR_DROP_OPT_COST1r:
   2976        case ESM_ADM_THR_DROP_OPT_COST2r:
   2977        case ESM_ADM_THR_DROP_OPT_RESET_COST0r:
   2978        case ESM_ADM_THR_DROP_OPT_RESET_COST1r:
   2979        case ESM_ADM_THR_DROP_OPT_RESET_COST2r:
   2980        case ESM_AGE_CNTr:
   2981        case ESM_AXP_THR_XOFF_COST0r:
   2982        case ESM_AXP_THR_XOFF_COST1r:
   2983        case ESM_AXP_THR_XOFF_COST2r:
   2984        case ESM_AXP_THR_XOFF_RESET_COST0r:
   2985        case ESM_AXP_THR_XOFF_RESET_COST1r:
   2986        case ESM_AXP_THR_XOFF_RESET_COST2r:
   2987        case ESM_CONTAINER_SELECTr:
   2988        case ESM_CTLr:
   2989        case ESM_ERR_CTLr:
   2990        case ESM_ET_HWTL_CONTROLr:
   2991        case ESM_ET_HWTL_EVENT_ERR_INFOr:
   2992        case ESM_ET_HWTL_MM_INFOr:
   2993        case ESM_ET_HWTL_STATUS_0r:
   2994        case ESM_ET_HWTL_STATUS_1r:
   2995        case ESM_ET_RSP_CBA_MM_INFOr:
   2996        case ESM_ET_RSP_FIFO_STATUSr:
   2997        case ESM_EVENT_ERR_STATUS_INTRr:
   2998        case ESM_EVENT_ERR_STATUS_INTR_ENABLEr:
   2999        case ESM_EXT_HITBIT_CONTROLr:
   3000        case ESM_FIFO_MAX_COUNTSr:
   3001        case ESM_KEYGEN_CTLr:
   3002        case ESM_L2_AGE_CTLr:
   3003        case ESM_L2_AGE_STATUSr:
   3004        case ESM_MAX_LATENCY_RECORDEDr:
   3005        case ESM_MEMORY_DBGCTRL_0r:
   3006        case ESM_MEMORY_DBGCTRL_1r:
   3007        case ESM_MEMORY_DBGCTRL_2r:
   3008        case ESM_MEMORY_DBGCTRL_3r:
   3009        case ESM_MEMORY_DBGCTRL_4r:
   3010        case ESM_MISC_CONTROLr:
   3011        case ESM_MISC_STATUSr:
   3012        case ESM_MODE_PER_PORTr:
   3013        case ESM_OPT_REQ_INTERVALr:
   3014        case ESM_PER_PORT_AGE_CONTROLr:
   3015        case ESM_PER_PORT_REPL_CONTROLr:
   3016        case ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr:
   3017        case ESM_PKT_TYPE_ID_CAM_BIST_DBGCTRLr:
   3018        case ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr:
   3019        case ESM_PKT_TYPE_ID_CAM_BIST_STATUSr:
   3020        case ESM_PKT_TYPE_ID_CAM_DBGCTRLr:
   3021        case ESM_PPA_STATUSr:
   3022        case ESM_REQUEST_LANE_MAPr:
   3023        case ESM_REUSE_COUNTER_0r:
   3024        case ESM_REUSE_COUNTER_1r:
   3025        case ESM_REUSE_COUNTER_2r:
   3026        case ESM_REUSE_COUNTER_3r:
   3027        case ESM_SEARCH_PROFILE_BASEr:
   3028        case ETU_CONFIG1r:
   3029        case ETU_CONFIG2r:
   3030        case ETU_CONFIG4r:
   3031             if (!soc_feature(unit, soc_feature_esm_support)) {
   3032             goto skip;
   3033             }
   3034        /*coverity[unterminated_case:FALSE]*/	    
   3035         case ICFG_EN_COR_ERR_RPTr:
   3036         case IPARS_EN_COR_ERR_RPTr:
   3037         case IESMIF_EN_COR_ERR_RPTr:
   3038         case EGR_EL3_EN_COR_ERR_RPTr:
   3039         case EGR_EHCPM_EN_COR_ERR_RPTr:
   3040         case EGR_1588_TIMER_VALUEr:
   3041         case EGR_1588_EGRESS_CTRLr:
   3042         case EGR_1588_TIMER_DEBUGr:
   3043         case EGR_1588_PARSING_CONTROLr:
   3044         case LLS_CONFIG0r:
   3045         case LLS_SP_WERR_DYN_CHANGE_0r:
   3046         case LLS_SP_WERR_DYN_CHANGE_1r:
   3047         case LLS_SP_WERR_DYN_CHANGE_2r:
   3048         case LLS_SP_WERR_DYN_CHANGE_3r:
   3049         case LLS_SP_WERR_DYN_CHANGE_0Ar:
   3050         case LLS_SP_WERR_DYN_CHANGE_1Ar:
   3051         case LLS_SP_WERR_DYN_CHANGE_2Ar:
   3052         case LLS_SP_WERR_DYN_CHANGE_3Ar:
   3053         case LLS_SP_WERR_DYN_CHANGE_0Br:
   3054         case LLS_SP_WERR_DYN_CHANGE_1Br:
   3055         case LLS_SP_WERR_DYN_CHANGE_2Br:
   3056         case LLS_SP_WERR_DYN_CHANGE_3Br:
   3057         case LLS_TDM_CAL_CFGr:
   3058         case LLS_FC_CONFIGr:   
   3059         case ISM_INTR_MASKr:
   3060         case PORT_MODE_REGr:
   3061         case PORT_TS_TIMER_31_0_REGr:
   3062         case PORT_TS_TIMER_47_32_REGr:
   3063         case XMAC_OSTS_TIMESTAMP_ADJUSTr:
   3064             soc_cm_get_id(unit, &dev_id, &rev_id);
   3065             if (rev_id < BCM56640_B0_REV_ID) {
   3066                 goto skip;
   3067             }
   3068         default:
   3069             break;
   3070         }
   3071     }
   3072 
   3073     if (!SOC_PORT_VALID(unit, ainfo->port)) {
   3074         return 0;
   3075     }
   3076     _MAP_REG_MASK_SUBSETS(unit, i, count, mask_map_arr);
   3077 
   3078     switch (ainfo->reg) {
   3079     case MCQ_FIFO_BASE_REG_32_35r:
   3080         /* PORTLIST => MMU[32..35] 8 MCQ (High-speed) */
   3081         pbmp = tr3_8mcq_ports_32_35;
   3082         break;
   3083     case MCQ_FIFO_BASE_REG_36_39r:
   3084         /* PORTLIST => MMU[36..39] 8 MCQ (High-speed) */
   3085         pbmp = tr3_8mcq_ports_36_39;
   3086         break;
   3087     case MCQ_FIFO_BASE_REGr:
   3088         /* PORTLIST => MMU[40..55] 10 MCQ (High-speed) */
   3089         pbmp = tr3_10mcq_ports_40_47;
   3090         break;
   3091     case MCQ_FIFO_BASE_REG_48_55r:
   3092         /* PORTLIST => MMU[40..55] 10 MCQ (High-speed) */
   3093         pbmp = tr3_10mcq_ports_48_55;
   3094         break;
   3095     case MCQ_FIFO_BASE_REG_56r:
   3096         /* PORTLIST => [56] */
   3097         pbmp = tr3_wlan_encap_ports;
   3098         break;
   3099     case MCQ_FIFO_BASE_REG_PASSTHRUr:
   3100         /* PORTLIST => [58] */
   3101         pbmp = tr3_pass_thru_ports;
   3102         break;
   3103     case MCQ_FIFO_BASE_REG_CPUr:
   3104         /* PORTLIST => [59] */
   3105         pbmp = tr3_cpu_ports;
   3106         break;
   3107 
   3108     case HES_PORT_CONFIGr:
   3109     case HES_L0_CONFIGr:
   3110     case HES_Q_MINSPr:
   3111     case HES_Q_COSMASKr:
   3112     case HES_Q_COSWEIGHTSr:
   3113     case HES_Q_WERRCOUNTr:
   3114         /* @MMU_HSP_PORT_NUMBERS (High-speed ports [48,52])*/
   3115         pbmp = tr3_high_speed_ports;
   3116         break;
   3117 
   3118     case CMAC_CTRLr:
   3119     case CMAC_MODEr:
   3120     case CMAC_SPARE0r:
   3121     case CMAC_SPARE1r:
   3122     case CMAC_TX_CTRLr:
   3123     case CMAC_TX_MAC_SAr:
   3124     case CMAC_RX_CTRLr:
   3125     case CMAC_RX_MAC_SAr:
   3126     case CMAC_RX_MAX_SIZEr:
   3127     case CMAC_RX_VLAN_TAGr:
   3128     case CMAC_RX_LSS_CTRLr:
   3129     case CMAC_RX_LSS_STATUSr:
   3130     case CMAC_CLEAR_RX_LSS_STATUSr:
   3131     case CMAC_PAUSE_CTRLr:
   3132     case CMAC_PFC_CTRLr:
   3133     case CMAC_PFC_TYPEr:
   3134     case CMAC_PFC_OPCODEr:
   3135     case CMAC_PFC_DAr:
   3136     case CMAC_LLFC_CTRLr:
   3137     case CMAC_TX_LLFC_MSG_FIELDSr:
   3138     case CMAC_RX_LLFC_MSG_FIELDSr:
   3139     case CMAC_HCFC_CTRLr:
   3140     case CMAC_TX_TIMESTAMP_FIFO_DATAr:
   3141     case CMAC_TX_TIMESTAMP_FIFO_STATUSr:
   3142     case CMAC_FIFO_STATUSr:
   3143     case CMAC_CLEAR_FIFO_STATUSr:
   3144     case CMAC_TX_FIFO_CREDITSr:
   3145     case CMAC_EEE_CTRLr:
   3146     case CMAC_EEE_TIMERSr:
   3147     case CMAC_EEE_1_SEC_LINK_STATUS_TIMERr:
   3148     case CMAC_TIMESTAMP_ADJUSTr:
   3149     case CMAC_MACSEC_CTRLr:
   3150     case CMAC_ECC_CTRLr:
   3151     case CMAC_ECC_STATUSr:
   3152     case CMAC_CLEAR_ECC_STATUSr:
   3153     case CMAC_VERSION_IDr:
   3154         /* CMAC registers (Only CL configured ports)*/
   3155         pbmp = tr3_cl_ports;
   3156         break;
   3157 
   3158     case REPL_HEAD_PTR_REPLACEr:
   3159         if (!soc_feature(unit, soc_feature_repl_head_ptr_replace)) {
   3160             pbmp = tr3_ports_none;
   3161             break;
   3162         }
   3163         /* [0..56,58,60,61] */
   3164         pbmp = tr3_repl_head_ports;
   3165         break;
   3166     
   3167     case THDO_PORT_E2ECC_COS_SPIDr:
   3168     case PORT_SW_FLOW_CONTROLr:
   3169         soc_cm_get_id(unit, &dev_id, &rev_id);
   3170         if ((rev_id < BCM56640_B0_REV_ID) && !SOC_IS_HELIX4(unit)) {
   3171             pbmp = tr3_ports_none;
   3172             break;
   3173         }
   3174         /* Fall through */
   3175 
   3176     default:
   3177         pbmp = tr3_all_ports;
   3178         break;
   3179     }
   3180 
   3181     if ((soc_portreg == SOC_REG_INFO(unit, ainfo->reg).regtype) &&
   3182         (!SOC_PBMP_MEMBER(*pbmp, ainfo->port))) {
   3183         goto skip; 
   3184     }
   3185 
   3186     switch (ainfo->reg) {
   3187 
   3188     case DEQ_AGINGMASKr:
   3189         /* PORTLIST => MMU[0..58,60..62] Non-CPU */
   3190     case XPORT_TO_MMU_BKPr:
   3191         /* @PFC_PORT_STS_REGS Non-CPU */
   3192     case BKPMETERINGCONFIG_64r:
   3193     case BKPMETERINGBUCKETr:
   3194     case MTRI_IFGr:
   3195         /* @MMU_MTRI_PORTS = MMU[0..58,60..62] */
   3196         if (IS_CPU_PORT(unit, ainfo->port)) {
   3197             goto skip;
   3198         }
   3199         break;
   3200     case OP_PORT_CONFIG_CELLr:
   3201     case OP_PORT_CONFIG1_CELLr:
   3202     case OP_PORT_LIMIT_COLOR_CELLr:
   3203     case OP_PORT_SHARED_COUNT_CELLr:
   3204     case OP_PORT_TOTAL_COUNT_CELLr:
   3205     case OP_PORT_LIMIT_RESUME_COLOR_CELLr:
   3206         /* @THDO_MC_PORT_LIST = MMU[0..56,58..62] */
   3207         if (ainfo->port > AXP_PORT(unit, SOC_AXP_NLF_SM)) {
   3208             goto skip;
   3209         }
   3210         break;
   3211 
   3212     case MCQ_FIFO_BASE_REG_CPUr:
   3213         /* PORTLIST => [59] */
   3214     case OP_CPU_QUEUE_BST_STATr:
   3215     case OP_CPU_QUEUE_BST_THRESHOLDr:
   3216         /* @THDO_CPU_BST_REGS */
   3217         if (!IS_CPU_PORT(unit, ainfo->port)) {
   3218             goto skip;
   3219         }
   3220         break;
   3221 
   3222     case L0_COSWEIGHTSr:
   3223     case L0_WERRCOUNTr:
   3224         /* @MMU_ES_REGS[0-9]=[48,52] */
   3225         if (!SOC_PBMP_MEMBER(*tr3_high_speed_ports, ainfo->port)) {
   3226             goto skip;
   3227         }
   3228         break;
   3229 
   3230     case OVQ_MCQ_CREDITSr:
   3231     case OVQ_MCQ_STATEr:
   3232         /* @OVQ_PORT_COS_REGS (all ports except cpu and lb port) */
   3233         if (ainfo->port == AXP_PORT(unit, SOC_AXP_NLF_WLAN_DECAP)) {
   3234             goto skip;
   3235         }
   3236         /* Fall thru */
   3237     case OP_QUEUE_CONFIG_CELLr:
   3238     case OP_QUEUE_CONFIG1_CELLr:
   3239     case OP_QUEUE_LIMIT_COLOR_CELLr:
   3240     case OP_QUEUE_RESET_OFFSET_CELLr:
   3241     case OP_QUEUE_MIN_COUNT_CELLr:
   3242     case OP_QUEUE_SHARED_COUNT_CELLr:
   3243     case OP_QUEUE_TOTAL_COUNT_CELLr:
   3244     case OP_QUEUE_RESET_VALUE_CELLr:
   3245     case OP_QUEUE_LIMIT_RESUME_COLOR_CELLr:
   3246         /* @THDO_PORT_COS_REGS */
   3247         if ((ainfo->port == AXP_PORT(unit, SOC_AXP_NLF_SM)) || 
   3248             (ainfo->port == AXP_PORT(unit, SOC_AXP_NLF_WLAN_DECAP))) {
   3249              if (ainfo->idx >= 1) {
   3250                 goto skip;
   3251             }
   3252         } else if (SOC_PBMP_MEMBER(*tr3_10mcq_ports_40_47, ainfo->port) ||
   3253                    SOC_PBMP_MEMBER(*tr3_10mcq_ports_48_55, ainfo->port)) {
   3254              if (ainfo->idx >= 10) {
   3255                 goto skip;
   3256             }
   3257         } else if (!IS_CPU_PORT(unit, ainfo->port)) {
   3258              if (ainfo->idx >= 8) {
   3259                 goto skip;
   3260             }
   3261         }
   3262         /* Else CPU port, all queues allowed */
   3263         break;
   3264     case TOP_HW_TAP_MEM_ECC_CTRLr:
   3265         if (SOC_IS_HELIX4(unit)) {
   3266             goto skip;
   3267         }
   3268     default:
   3269         break;
   3270     }
   3271 
   3272     return 0;
   3273 skip:
   3274     /* set mask to all 0's so test will skip it */
   3275     if (mask != NULL) {
   3276         COMPILER_64_SET(*mask, 0, 0);
   3277     }
   3278     return 1;
   3279 }
   3280 #endif /* BCM_TRIUMPH3_SUPPORT */
   3281 
   3282 #if 0 /* #ifdef BCM_KATANA_SUPPORT */
   3283 /* Remove this completely once the new function is fully verified */
   3284 STATIC int
   3285 reg_mask_subset_katana(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   3286 {
   3287     soc_info_t *si;
   3288     int i;
   3289     static int kt_port_init = 0;
   3290     static pbmp_t kt_ipipe_higig_ports;
   3291     static pbmp_t kt_epipe_ports_subports;
   3292     static pbmp_t kt_ports_0_35;
   3293     static pbmp_t kt_ports_25_28;
   3294     static pbmp_t kt_mmu_mtri_ports;
   3295     static pbmp_t kt_all_ports;
   3296     uint64 temp_mask;
   3297     pbmp_t *pbmp;
   3298 
   3299     if (!kt_port_init) {
   3300 
   3301         /* IPIPE_HIGIG_PORTS = [0,25,26,27,28,29,30,31] */
   3302         SOC_PBMP_CLEAR(kt_ipipe_higig_ports);
   3303         SOC_PBMP_PORT_ADD(kt_ipipe_higig_ports, 0);
   3304         for (i = 25; i <= 31; i++) {
   3305             SOC_PBMP_PORT_ADD(kt_ipipe_higig_ports, i);
   3306         }
   3307 
   3308         /* EPIPE_PORTS_SUBPORTS = [0..38] */
   3309         SOC_PBMP_CLEAR(kt_epipe_ports_subports);
   3310         for (i = 0; i <= 38; i++) {
   3311             SOC_PBMP_PORT_ADD(kt_epipe_ports_subports, i);
   3312         }
   3313 
   3314         /* [0..35] */
   3315         /*  @MMU_THDO_PORTS = [0..35] */
   3316         /*  @MMU_RQE_PORTS = [0..35]; */
   3317         SOC_PBMP_CLEAR(kt_ports_0_35);
   3318         for (i = 0; i <= 35; i++) {
   3319             SOC_PBMP_PORT_ADD(kt_ports_0_35, i);
   3320         }
   3321 
   3322         /* PFC_PORT_STS_REGS = [25..28] */
   3323         SOC_PBMP_CLEAR(kt_ports_25_28);
   3324         for (i = 25; i <= 28; i++) {
   3325             SOC_PBMP_PORT_ADD(kt_ports_25_28, i);
   3326         }
   3327         /* @MMU_MTRI_PORTS = [1..35] */
   3328         SOC_PBMP_CLEAR(kt_mmu_mtri_ports);
   3329         for (i = 1; i <= 35; i++) {
   3330             SOC_PBMP_PORT_ADD(kt_mmu_mtri_ports, i);
   3331         }
   3332                 
   3333         /* All ports */
   3334         SOC_PBMP_CLEAR(kt_all_ports); 
   3335         SOC_PBMP_ASSIGN(kt_all_ports, PBMP_ALL(unit)); 
   3336  
   3337         kt_port_init = 1; 
   3338     }
   3339 
   3340 
   3341     if (!SOC_PORT_VALID(unit, ainfo->port)) {
   3342         return 0;
   3343     }
   3344 
   3345     si = &SOC_INFO(unit);
   3346 
   3347     switch (ainfo->reg) {
   3348         /* IPIPE_HIGIG_PORTS = [0,25,26,27,28,29,30,31] */
   3349         case IUNHGIr:
   3350         case ICTRLr:
   3351         case IBCASTr:
   3352         case ILTOMCr:
   3353         case IIPMCr:
   3354         case IUNKOPCr:
   3355             pbmp = &kt_ipipe_higig_ports;
   3356             break;
   3357 
   3358         /* EPIPE_PORTS_SUBPORTS = [0..38] */
   3359         case EGR_VLAN_CONTROL_1r:
   3360         case EGR_IPMC_CFG2r:
   3361         case EGR_PORT_TO_NHI_MAPPINGr:
   3362         case EGR_VLAN_CONTROL_2r:
   3363         case EGR_VLAN_CONTROL_3r:
   3364         case EGR_PVLAN_EPORT_CONTROLr:
   3365         case EGR_INGRESS_PORT_TPID_SELECTr:
   3366         case EGR_VLAN_LOGICAL_TO_PHYSICAL_MAPPINGr:
   3367         case EGR_DBGr:
   3368         case EGR_MODMAP_CTRLr:
   3369         case EGR_SF_SRC_MODID_CHECKr:
   3370         case EGR_SHAPING_CONTROLr:
   3371         case EGR_COUNTER_CONTROLr:
   3372         case EGR_MTUr:
   3373         case EGR_PORT_1r:
   3374         case EGR_1588_INGRESS_CTRLr:
   3375         case EGR_1588_EGRESS_CTRLr:
   3376         case EGR_1588_LINK_DELAYr:
   3377         case EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr:
   3378         case TDBGC0r:
   3379         case TDBGC1r:
   3380         case TDBGC2r:
   3381         case TDBGC3r:
   3382         case TDBGC4r:
   3383         case TDBGC5r:
   3384         case TDBGC6r:
   3385         case TDBGC7r:
   3386         case TDBGC8r:
   3387         case TDBGC9r:
   3388         case TDBGC10r:
   3389         case TDBGC11r:
   3390             pbmp = &kt_epipe_ports_subports;
   3391             break;
   3392 
   3393         /* [0..35] */
   3394         case DEQ_EFIFO_CFGr:
   3395         case DEQ_EFIFO_STATUS_DEBUGr:
   3396         case DEQ_EFIFO_EMPTY_FULL_STATUS_DEBUGr:
   3397         case DEQ_EFIFO_WATERMARK_DEBUGr:
   3398         case MMU_TO_XPORT_BKPr:
   3399         case PORT_MAX_SHARED_CELLr:
   3400         case THDIEMA_PORT_MAX_SHARED_CELLr:
   3401         case THDIEXT_PORT_MAX_SHARED_CELLr:
   3402         case THDIQEN_PORT_MAX_SHARED_CELLr:
   3403         case THDIRQE_PORT_MAX_SHARED_CELLr:
   3404         case PORT_MAX_PKT_SIZEr:
   3405         case THDIEMA_PORT_MAX_PKT_SIZEr:
   3406         case THDIEXT_PORT_MAX_PKT_SIZEr:
   3407         case THDIQEN_PORT_MAX_PKT_SIZEr:
   3408         case THDIRQE_PORT_MAX_PKT_SIZEr:
   3409         case PORT_RESUME_LIMIT_CELLr:
   3410         case THDIEMA_PORT_RESUME_LIMIT_CELLr:
   3411         case THDIEXT_PORT_RESUME_LIMIT_CELLr:
   3412         case THDIQEN_PORT_RESUME_LIMIT_CELLr:
   3413         case THDIRQE_PORT_RESUME_LIMIT_CELLr:
   3414         case PORT_PG_SPIDr:
   3415         case THDIEMA_PORT_PG_SPIDr:
   3416         case THDIEXT_PORT_PG_SPIDr:
   3417         case THDIQEN_PORT_PG_SPIDr:
   3418         case THDIRQE_PORT_PG_SPIDr:
   3419         case PG_PORT_MIN_COUNT_CELLr:
   3420         case THDIEMA_PG_PORT_MIN_COUNT_CELLr:
   3421         case THDIEXT_PG_PORT_MIN_COUNT_CELLr:
   3422         case THDIQEN_PG_PORT_MIN_COUNT_CELLr:
   3423         case THDIRQE_PG_PORT_MIN_COUNT_CELLr:
   3424         case PORT_FC_STATUSr:
   3425         case THDIEMA_PORT_FC_STATUSr:
   3426         case THDIEXT_PORT_FC_STATUSr:
   3427         case THDIQEN_PORT_FC_STATUSr:
   3428         case THDIRQE_PORT_FC_STATUSr:
   3429         case FLOW_CONTROL_XOFF_STATEr:
   3430         case THDIEMA_FLOW_CONTROL_XOFF_STATEr:
   3431         case THDIEXT_FLOW_CONTROL_XOFF_STATEr:
   3432         case THDIQEN_FLOW_CONTROL_XOFF_STATEr:
   3433         case THDIRQE_FLOW_CONTROL_XOFF_STATEr:
   3434         case TOQ_EG_CREDITr:
   3435         case TOQ_PORT_BW_CTRLr:
   3436         case E2EFC_PORT_MAPPINGr:
   3437             pbmp = &kt_ports_0_35;
   3438             break;
   3439 
   3440         case PG_SHARED_LIMIT_CELLr:
   3441         case THDIEMA_PG_SHARED_LIMIT_CELLr:
   3442         case THDIEXT_PG_SHARED_LIMIT_CELLr:
   3443         case THDIQEN_PG_SHARED_LIMIT_CELLr:
   3444         case THDIRQE_PG_SHARED_LIMIT_CELLr:
   3445         case PG_RESET_OFFSET_CELLr:
   3446         case THDIEMA_PG_RESET_OFFSET_CELLr:
   3447         case THDIEXT_PG_RESET_OFFSET_CELLr:
   3448         case THDIQEN_PG_RESET_OFFSET_CELLr:
   3449         case THDIRQE_PG_RESET_OFFSET_CELLr:
   3450         case PG_RESET_FLOOR_CELLr:
   3451         case THDIEMA_PG_RESET_FLOOR_CELLr:
   3452         case THDIEXT_PG_RESET_FLOOR_CELLr:
   3453         case THDIQEN_PG_RESET_FLOOR_CELLr:
   3454         case THDIRQE_PG_RESET_FLOOR_CELLr:
   3455         case PG_MIN_CELLr:
   3456         case THDIEMA_PG_MIN_CELLr:
   3457         case THDIEXT_PG_MIN_CELLr:
   3458         case THDIQEN_PG_MIN_CELLr:
   3459         case THDIRQE_PG_MIN_CELLr:
   3460         case PG_HDRM_LIMIT_CELLr:
   3461         case THDIEMA_PG_HDRM_LIMIT_CELLr:
   3462         case THDIEXT_PG_HDRM_LIMIT_CELLr:
   3463         case THDIQEN_PG_HDRM_LIMIT_CELLr:
   3464         case THDIRQE_PG_HDRM_LIMIT_CELLr:
   3465         case PG_MIN_COUNT_CELLr:
   3466         case THDIEMA_PG_MIN_COUNT_CELLr:
   3467         case THDIEXT_PG_MIN_COUNT_CELLr:
   3468         case THDIQEN_PG_MIN_COUNT_CELLr:
   3469         case THDIRQE_PG_MIN_COUNT_CELLr:
   3470         case PG_SHARED_COUNT_CELLr:
   3471         case THDIEMA_PG_SHARED_COUNT_CELLr:
   3472         case THDIEXT_PG_SHARED_COUNT_CELLr:
   3473         case THDIQEN_PG_SHARED_COUNT_CELLr:
   3474         case THDIRQE_PG_SHARED_COUNT_CELLr:
   3475         case PG_HDRM_COUNT_CELLr:
   3476         case THDIEMA_PG_HDRM_COUNT_CELLr:
   3477         case THDIEXT_PG_HDRM_COUNT_CELLr:
   3478         case THDIQEN_PG_HDRM_COUNT_CELLr:
   3479         case THDIRQE_PG_HDRM_COUNT_CELLr:
   3480         case PG_GBL_HDRM_COUNTr:
   3481         case THDIEMA_PG_GBL_HDRM_COUNTr:
   3482         case THDIEXT_PG_GBL_HDRM_COUNTr:
   3483         case THDIQEN_PG_GBL_HDRM_COUNTr:
   3484         case THDIRQE_PG_GBL_HDRM_COUNTr:
   3485         case PG_RESET_VALUE_CELLr:
   3486         case THDIEMA_PG_RESET_VALUE_CELLr:
   3487         case THDIEXT_PG_RESET_VALUE_CELLr:
   3488         case THDIQEN_PG_RESET_VALUE_CELLr:
   3489         case THDIRQE_PG_RESET_VALUE_CELLr:
   3490             if (ainfo->idx == 0) {
   3491                 pbmp = &kt_ports_0_35;
   3492             } else {
   3493                 pbmp = &kt_ports_25_28;
   3494             }
   3495             break;
   3496 
   3497         /* PFC_PORT_STS/CFG_REGS = [25..28] */
   3498         case XPORT_TO_MMU_BKPr:
   3499         case PORT_LLFC_CFGr:
   3500         case INTFI_PORT_CFGr:
   3501         case PORT_MIN_CELLr:
   3502         case THDIEMA_PORT_MIN_CELLr:
   3503         case THDIEXT_PORT_MIN_CELLr:
   3504         case THDIQEN_PORT_MIN_CELLr:
   3505         case THDIRQE_PORT_MIN_CELLr:
   3506         case PORT_PRI_GRP0r:
   3507         case THDIEMA_PORT_PRI_GRP0r:
   3508         case THDIEXT_PORT_PRI_GRP0r:
   3509         case THDIQEN_PORT_PRI_GRP0r:
   3510         case THDIRQE_PORT_PRI_GRP0r:
   3511         case PORT_PRI_GRP1r:
   3512         case THDIEMA_PORT_PRI_GRP1r:
   3513         case THDIEXT_PORT_PRI_GRP1r:
   3514         case THDIQEN_PORT_PRI_GRP1r:
   3515         case THDIRQE_PORT_PRI_GRP1r:
   3516         case PORT_PRI_XON_ENABLEr:
   3517         case THDIEMA_PORT_PRI_XON_ENABLEr:
   3518         case THDIEXT_PORT_PRI_XON_ENABLEr:
   3519         case THDIQEN_PORT_PRI_XON_ENABLEr:
   3520         case THDIRQE_PORT_PRI_XON_ENABLEr:
   3521         case PORT_COUNT_CELLr:
   3522         case THDIEMA_PORT_COUNT_CELLr:
   3523         case THDIEXT_PORT_COUNT_CELLr:
   3524         case THDIQEN_PORT_COUNT_CELLr:
   3525         case THDIRQE_PORT_COUNT_CELLr:
   3526         case PORT_MIN_COUNT_CELLr:
   3527         case THDIEMA_PORT_MIN_COUNT_CELLr:
   3528         case THDIEXT_PORT_MIN_COUNT_CELLr:
   3529         case THDIQEN_PORT_MIN_COUNT_CELLr:
   3530         case THDIRQE_PORT_MIN_COUNT_CELLr:
   3531         case PORT_SHARED_COUNT_CELLr:
   3532         case THDIEMA_PORT_SHARED_COUNT_CELLr:
   3533         case THDIEXT_PORT_SHARED_COUNT_CELLr:
   3534         case THDIQEN_PORT_SHARED_COUNT_CELLr:
   3535         case THDIRQE_PORT_SHARED_COUNT_CELLr:
   3536         case PORT_SHARED_MAX_PG_ENABLEr:
   3537         case THDIEMA_PORT_SHARED_MAX_PG_ENABLEr:
   3538         case THDIEXT_PORT_SHARED_MAX_PG_ENABLEr:
   3539         case THDIQEN_PORT_SHARED_MAX_PG_ENABLEr:
   3540         case THDIRQE_PORT_SHARED_MAX_PG_ENABLEr:
   3541         case PORT_MIN_PG_ENABLEr:
   3542         case THDIEMA_PORT_MIN_PG_ENABLEr:
   3543         case THDIEXT_PORT_MIN_PG_ENABLEr:
   3544         case THDIQEN_PORT_MIN_PG_ENABLEr:
   3545         case THDIRQE_PORT_MIN_PG_ENABLEr:
   3546             pbmp = &kt_ports_25_28;
   3547             break;
   3548 
   3549         /* @MMU_MTRI_PORTS = [1..35] */
   3550         case BKPMETERINGCONFIG_64r:
   3551         case BKPMETERINGBUCKETr:
   3552         case MTRI_IFGr:
   3553             pbmp = &kt_mmu_mtri_ports;
   3554             break;
   3555 
   3556         /*  @MMU_THDO_PORTS = [0..35] */
   3557         case OP_E2ECC_PORT_CONFIGr:
   3558             pbmp = &kt_ports_0_35;
   3559             break;
   3560 
   3561         /*  @MMU_RQE_PORTS = [0..35]; */
   3562         case RQE_PORT_CONFIGr:
   3563         case RQE_MIRROR_CONFIGr:
   3564             pbmp = &kt_ports_0_35;
   3565             break;
   3566 
   3567         case MAC_PFC_CTRLr:
   3568             /* These are not implemented in Katana */
   3569             goto skip;
   3570 
   3571         default:
   3572             pbmp = &kt_all_ports;
   3573             break;
   3574     }
   3575 
   3576     if ((soc_portreg == SOC_REG_INFO(unit, ainfo->reg).regtype) &&
   3577         (!SOC_PBMP_MEMBER(*pbmp, ainfo->port))) {
   3578         goto skip; 
   3579     }
   3580 
   3581     if (mask != NULL) {
   3582         switch (ainfo->reg) {
   3583         case SHAPING_CONTROLr:
   3584         case RESET_ON_EMPTY_MAX_64r:
   3585             if (!si->port_num_ext_cosq[ainfo->port]) {
   3586                 COMPILER_64_SET(temp_mask, 0, 0x007fffff);
   3587                 COMPILER_64_AND(*mask, temp_mask);
   3588             }
   3589             break;
   3590         default:
   3591             break;
   3592         }
   3593     }
   3594 
   3595     return 0;
   3596 
   3597 skip:
   3598     /* set mask to all 0's so test will skip it */
   3599     if (mask != NULL) {
   3600         COMPILER_64_SET(*mask, 0, 0);
   3601     }
   3602     return 1;
   3603 }
   3604 #endif /* BCM_KATANA_SUPPORT */
   3605 
   3606 #ifdef BCM_KATANA_SUPPORT
   3607 STATIC int
   3608 reg_mask_subset_katanax(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   3609 {
   3610     soc_info_t *si;
   3611     uint64 temp_mask;
   3612     uint16 dev_id;
   3613     uint8  rev_id;
   3614     int rv = 0;
   3615     soc_cm_get_id(unit, &dev_id, &rev_id);
   3616 
   3617     si = &SOC_INFO(unit);
   3618 
   3619     if (!SOC_REG_PORT_IDX_VALID(unit,ainfo->reg, ainfo->port, ainfo->idx)) {
   3620         /* set mask to all 0's so test will skip it */
   3621         if (mask != NULL) {
   3622             COMPILER_64_SET(*mask, 0, 0);
   3623         }
   3624         return 1;
   3625     }
   3626 
   3627     /* Validate block accesses against variant features */
   3628     if (CHECK_FEATURE_BLK(soc_feature_ces, SOC_BLK_CES) ||
   3629         CHECK_FEATURE_BLK(soc_feature_ddr3, SOC_BLK_CI)) {
   3630         if (mask != NULL) {
   3631             COMPILER_64_SET(*mask, 0, 0);
   3632         }
   3633         return 1;
   3634     }
   3635 
   3636     if (mask != NULL) {
   3637         switch (ainfo->reg) {
   3638         case SHAPING_CONTROLr:
   3639         case RESET_ON_EMPTY_MAX_64r:
   3640             if (!si->port_num_ext_cosq[ainfo->port]) {
   3641                 COMPILER_64_SET(temp_mask, 0, 0x007fffff);
   3642                 COMPILER_64_AND(*mask, temp_mask);
   3643             }
   3644             break;
   3645         case CFAPIFULLRESETPOINTr:
   3646         case CFAPEFULLRESETPOINTr:
   3647         case CFAPIFULLSETPOINTr:
   3648         case CFAPEFULLSETPOINTr:
   3649         case MAC_PFC_CTRLr:
   3650         case CFAPICONFIGr:
   3651         case CHFC_TC2PRI_TBL_ECC_CONFIGr:
   3652         case MMU_INTFO_CONGST_STr:
   3653         case RXLP_DFC_CPU_UPDATE_REFRESHr:
   3654         case RXLP_DFC_STATUS_HIr:
   3655         case RXLP_DFC_STATUS_LOr:
   3656         case THDI_TO_OOBFC_SP_STr:
   3657         case THDO_TO_OOBFC_SP_STr:
   3658         case CFAPIOTPCONFIGr:
   3659             COMPILER_64_SET(*mask, 0, 0);
   3660             rv = 1;
   3661             break;
   3662         case CFAPECONFIGr:
   3663         case CFAPEOTPCONFIGr:
   3664         case EMC_CFGr:
   3665         case EMC_CSDB_MEM_DEBUGr:
   3666         case EMC_ECC_DEBUG_0r:
   3667         case EMC_ECC_DEBUG_1r:
   3668         case EMC_ERRB_0_MEM_DEBUGr:
   3669         case EMC_ERRB_1_MEM_DEBUGr:
   3670         case EMC_ERRB_FIFO_NFULL_THRESHOLDr:
   3671         case EMC_ERROR_MASK_0r:
   3672         case EMC_ERROR_MASK_1r:
   3673         case EMC_ERROR_MASK_2r:
   3674         case EMC_ERROR_MASK_3r:
   3675         case EMC_EWRB_0_MEM_DEBUGr:
   3676         case EMC_EWRB_1_MEM_DEBUGr:
   3677         case EMC_EWRB_FIFO_NFULL_THRESHOLDr:
   3678         case EMC_FREE_POOL_SIZESr:
   3679         case EMC_IRRB_THRESHOLDSr:
   3680         case EMC_IWRB_MEM_DEBUGr:
   3681         case EMC_IWRB_SIZEr:
   3682         case EMC_RFCQ_MEM_DEBUGr:
   3683         case EMC_RSFP_MEM_DEBUGr:
   3684         case EMC_SWAT_MEM_DEBUGr:
   3685         case EMC_WCMT_MEM_DEBUGr:
   3686         case EMC_WLCT_MEM_DEBUGr:
   3687         case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_MEM_DEBUGr:
   3688         case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_NFULL_THRESHOLDr:
   3689         case EMC_WTFP_MEM_DEBUGr:
   3690         case EMC_WTOQ_MEM_DEBUGr:
   3691         case EMC_WTOQ_BUFFER_ECC_STATUS_DEBUGr:
   3692         case GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0r:
   3693         case GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL1r:
   3694         case GLOBAL_WRED_AVG_QSIZE_BUFFERIr:
   3695         case GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0r:
   3696         case GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL1r:
   3697         case GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERIr:
   3698         case GLOBAL_WRED_AVG_QSIZE_FRACTION_QENTRYr:
   3699         case GLOBAL_WRED_AVG_QSIZE_QENTRYr:
   3700         case GLOBAL_WRED_CONFIG_BUFFERE_POOL0r:
   3701         case GLOBAL_WRED_CONFIG_BUFFERE_POOL1r:
   3702         case GLOBAL_WRED_CONFIG_BUFFERIr:
   3703         case GLOBAL_WRED_CONFIG_QENTRYr:
   3704         case GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0r:
   3705         case GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL1r:
   3706         case GLOBAL_WRED_DROP_THD_NONTCP_BUFFERIr:
   3707         case GLOBAL_WRED_DROP_THD_NONTCP_QENTRYr:
   3708         case GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0r:
   3709         case GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL1r:
   3710         case GLOBAL_WRED_DROP_THD_TCP_BUFFERIr:
   3711         case GLOBAL_WRED_DROP_THD_TCP_QENTRYr:
   3712         case HCFC_ERRr:
   3713         case INTFI_CFGr:
   3714         case INTFI_DEBUGr:
   3715         case INTFI_ECC_CONTROLr:
   3716         case INTFI_ECC_INTR_MASKr:
   3717         case INTFI_MAP_L0_TBL_ADDRr:
   3718         case INTFI_MAP_L1_TBL_ADDRr:
   3719         case INTFI_MAP_L2_TBL_ADDRr:
   3720         case INTFI_OOBFC_MSG_RX_FAILED_CNTr:
   3721         case INTFO_FCN_ENr:
   3722         case INTFO_HW_UPDATE_DISr:
   3723         case INTFO_OOBFC_MSG_RX_FAILED_CNTr:
   3724         case ITE_CONFIGr:
   3725         case ITE_SCHED_WRR_WEIGHT_COS0r:
   3726         case ITE_SCHED_WRR_WEIGHT_COS1r:
   3727         case ITE_SCHED_WRR_WEIGHT_COS2r:
   3728         case ITE_SCHED_WRR_WEIGHT_COS3r:
   3729         case ITE_SCHED_WRR_WEIGHT_COS4r:
   3730         case ITE_SCHED_WRR_WEIGHT_COS5r:
   3731         case ITE_SCHED_WRR_WEIGHT_COS6r:
   3732         case ITE_SCHED_WRR_WEIGHT_COS7r:
   3733         case MMU1_PLL_DEBUGr:
   3734         case MMU2_PLL_DEBUGr:
   3735         case MMU_ADM_ECC_COUNTERSr:
   3736         case MMU_ADM_ECC_DEBUG_0r:
   3737         case MMU_ADM_ECC_ERROR_0_MASKr:
   3738         case MMU_ADM_QUEUE_DB_DEBUGr:
   3739         case MMU_E2EFC_CNT_DEBUG_STATUS_0r:
   3740         case MMU_E2EFC_CNT_DEBUG_STATUS_1r:
   3741         case MMU_E2EFC_ERROR_0_MASKr:
   3742         case MMU_ENQ_CBP_STORE_DEBUG_0r:
   3743         case MMU_ENQ_CFAPI_INTERNAL_RECYCLE_DEBUG_0r:
   3744         case MMU_ENQ_CFG_ECC_DEBUG_0r:
   3745         case MMU_ENQ_CFG_ECC_ERROR_0_MASKr:
   3746         case MMU_ENQ_CONFIG_0r:
   3747         case MMU_ENQ_DEST_PPP_CFG_0r:
   3748         case MMU_ENQ_DEST_PPP_CFG_1r:
   3749         case MMU_ENQ_DEST_PPP_CFG_2r:
   3750         case MMU_ENQ_DEST_PPP_CFG_3r:
   3751         case MMU_ENQ_DEST_PPP_CFG_4r:
   3752         case MMU_ENQ_DEST_PPP_CFG_5r:
   3753         case MMU_ENQ_ECC_COUNTERSr:
   3754         case MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_0r:
   3755         case MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_2r:
   3756         case MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_3r:
   3757         case MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_1r:
   3758         case MMU_ENQ_EMA_COS_TO_FIFO_PROFILE_1r:
   3759         case MMU_ENQ_EMA_COS_TO_FIFO_PROFILE_2r:
   3760         case MMU_ENQ_EMA_QUEUE_SELECT_0r:
   3761         case MMU_ENQ_EMA_QUEUE_SELECT_1r:
   3762         case MMU_ENQ_ERROR_0_MASKr:
   3763         case MMU_ENQ_FAPCONFIG_0r:
   3764         case MMU_ENQ_FAPINIT_0r:
   3765         case MMU_ENQ_FAP_ECC_DEBUG_0r:
   3766         case MMU_ENQ_FAP_ECC_ERROR_0_MASKr:
   3767         case MMU_ENQ_ILLEGAL_CELL_TYPE_0r:
   3768         case MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r:
   3769         case MMU_ENQ_ITE_REORDER_DEBUG_0r:
   3770         case MMU_ENQ_MISSING_START_ERR_STAT_0r:
   3771         case MMU_ENQ_MISSING_START_ERR_STAT_1r:
   3772         case MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr:
   3773         case MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_0r:
   3774         case MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_1r:
   3775         case MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_2r:
   3776         case MMU_ENQ_PACK_PKT_LEN_FIFO_DEBUG_0r:
   3777         case MMU_ENQ_PACK_SRC_CTXT_FIFO_DEBUG_0r:
   3778         case MMU_ENQ_PROFILE_0_PRI_GRP0r:
   3779         case MMU_ENQ_PROFILE_0_PRI_GRP1r:
   3780         case MMU_ENQ_PROFILE_1_PRI_GRP0r:
   3781         case MMU_ENQ_PROFILE_1_PRI_GRP1r:
   3782         case MMU_ENQ_PROFILE_2_PRI_GRP0r:
   3783         case MMU_ENQ_PROFILE_2_PRI_GRP1r:
   3784         case MMU_ENQ_PROFILE_3_PRI_GRP0r:
   3785         case MMU_ENQ_PROFILE_3_PRI_GRP1r:
   3786         case MMU_ENQ_RQE_QUEUE_SELECT_0r:
   3787         case MMU_ENQ_RQE_QUEUE_SELECT_1r:
   3788         case MMU_ENQ_RQE_WR_COMPLETE_DEBUG_0r:
   3789         case MMU_ENQ_SOP_STORE_DEBUG_0r:
   3790         case MMU_ENQ_SRC_PORT_STATE_DEBUG_0r:
   3791         case MMU_ENQ_START_BY_START_ERR_STAT_0r:
   3792         case MMU_ENQ_START_BY_START_ERR_STAT_1r:
   3793         case MMU_ENQ_TRACE_IF_CONTROLr:
   3794         case MMU_IPCTR_CONFIG_0r:
   3795         case MMU_IPCTR_COUNTER1_SNAPr:
   3796         case MMU_IPCTR_ECC_COUNTERSr:
   3797         case MMU_IPCTR_ECC_DEBUG_0r:
   3798         case MMU_IPCTR_ECC_ERROR_0_MASKr:
   3799         case MMU_ITE_CFG_ECC_DEBUG_0r:
   3800         case TOP_MISC_CONTROL_0r:
   3801              if (!soc_feature(unit, soc_feature_ddr3) ||
   3802                               (SOC_DDR3_NUM_MEMORIES(unit) == 0)) {
   3803                  COMPILER_64_SET(*mask, 0, 0);
   3804                  rv = 1;
   3805               }
   3806               break;
   3807         default:
   3808             break;
   3809         }
   3810     }
   3811 
   3812     return rv;
   3813 }
   3814 #endif /* BCM_KATANAX_SUPPORT */
   3815 #ifdef BCM_SABER2_SUPPORT
   3816 STATIC int
   3817 reg_mask_subset_saber2(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   3818 {
   3819     int rv = 0;
   3820 #if 0
   3821     soc_info_t *si;
   3822     si = &SOC_INFO(unit);
   3823 #endif
   3824 
   3825    if (!SOC_REG_PORT_IDX_VALID(unit,ainfo->reg, ainfo->port, ainfo->idx)) {
   3826       /* set mask to all 0's so test will skip it */
   3827        if (mask != NULL) {
   3828            COMPILER_64_SET(*mask, 0, 0);
   3829        }
   3830        return 1;
   3831    }
   3832 
   3833 
   3834     /* Validate block accesses against variant features */
   3835     if (CHECK_FEATURE_BLK(soc_feature_ddr3, SOC_BLK_CI)) {
   3836         if (mask != NULL) {
   3837             COMPILER_64_SET(*mask, 0, 0);
   3838         }
   3839         return 1;
   3840     }
   3841 
   3842     if (!soc_feature(unit,soc_feature_ddr3)) {
   3843         switch(ainfo->reg) {
   3844         case CI0_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   3845         case CI0_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   3846         case CI1_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   3847         case CI1_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   3848         case EMC_CFGr:
   3849         case EMC_BUFFER_EMPTY_FULL_STATUS_DEBUGr:
   3850         case EMC_CI_FULL_STATUS_DEBUGr:
   3851         case EMC_CSDB_0_BUFFER_PAR_STATUS_DEBUGr:
   3852         case EMC_CSDB_1_BUFFER_PAR_STATUS_DEBUGr:
   3853         case EMC_CSDB_MEM_DEBUGr:
   3854         case EMC_ECC_DEBUG_0r:
   3855         case EMC_ECC_DEBUG_1r:
   3856         case EMC_ERRORr:
   3857         case EMC_ERROR_0r:
   3858         case EMC_ERROR_MASK_0r:
   3859         case EMC_ERROR_1r:
   3860         case EMC_ERROR_MASK_1r:
   3861         case EMC_ERROR_2r:
   3862         case EMC_ERROR_MASK_2r:
   3863         case EMC_ERROR_3r:
   3864         case EMC_ERROR_MASK_3r:
   3865         case EMC_FIXED_PATTERN_DEBUGr:
   3866         case EMC_FREE_POOL_SIZESr:
   3867         case EMC_GLOBAL_1B_ECC_ERROR_COUNT_DEBUGr:
   3868         case EMC_GLOBAL_2B_ECC_ERROR_COUNT_DEBUGr:
   3869         case EMC_IRRB_BUFFER_ECC_STATUS_DEBUGr:
   3870         case EMC_IRRB_BUFFER_FILL_LEVEL_DEBUGr:
   3871         case EMC_IRRB_BUFFER_WATERMARK_DEBUGr:
   3872         case EMC_IRRB_MEM_DEBUGr:
   3873         case EMC_IRRB_THRESHOLDSr:
   3874         case EMC_RFCQ_BUFFER_ECC_STATUS_DEBUGr:
   3875 	case EMC_RFCQ_BUFFER_FILL_LEVEL_DEBUGr:
   3876 	case EMC_RFCQ_BUFFER_WATERMARK_DEBUGr: 
   3877         case EMC_RFCQ_MEM_DEBUGr: 
   3878   	case EMC_RSFP_BUFFER_ECC_STATUS_DEBUGr: 
   3879 	case EMC_RSFP_BUFFER_FILL_LEVEL_DEBUGr: 
   3880 	case EMC_RSFP_MEM_DEBUGr: 
   3881         case EMC_SWAT_BUFFER_ECC_STATUS_DEBUGr: 
   3882   	case EMC_SWAT_MEM_DEBUGr: 
   3883 	case EMC_TO_CI0_RD_REQ_COUNT_DEBUGr: 
   3884   	case EMC_TO_CI0_WR_REQ_COUNT_DEBUGr: 
   3885 	case EMC_TO_CI1_RD_REQ_COUNT_DEBUGr: 
   3886   	case EMC_TO_CI1_WR_REQ_COUNT_DEBUGr: 
   3887   	case EMC_TO_ITE_WR_REQ_PKT_COMPLETE_COUNT_DEBUGr: 
   3888   	case EMC_WLCT_BUFFER_ECC_STATUS_DEBUGr: 
   3889 	case EMC_WLCT_MEM_DEBUGr: 
   3890   	case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUGr: 
   3891   	case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_FILL_LEVEL_DEBUGr: 
   3892   	case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_MEM_DEBUGr: 
   3893   	case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_NFULL_THRESHOLDr: 
   3894   	case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_WATERMARK_DEBUGr: 
   3895   	case EMC_WTFP_BUFFER_ECC_STATUS_DEBUGr: 
   3896 	case EMC_WTFP_BUFFER_FILL_LEVEL_DEBUGr: 
   3897   	case EMC_WTFP_MEM_DEBUGr: 
   3898 	case EMC_WTOQ_BUFFER_ECC_STATUS_DEBUGr: 
   3899   	case EMC_WTOQ_BUFFER_FILL_LEVEL_DEBUGr: 
   3900 	case EMC_WTOQ_MEM_DEBUGr: 
   3901   	case ITE_TO_EMC_WR_REQ_EOP_COUNT_DEBUGr: 
   3902 	case ITE_TO_EMC_WR_REQ_SOP_COUNT_DEBUGr: 
   3903   	case MMU_ITE_EMC_BACKPRESSURE_DEBUG_CONFIGr: 
   3904   	case MMU_ITE_EMC_BACKPRESSURE_DEBUG_STATUSr:
   3905              if (mask != NULL) {
   3906                  COMPILER_64_SET(*mask, 0, 0);
   3907              }
   3908              return 1;
   3909         }
   3910     }
   3911     
   3912     if (mask != NULL) {
   3913         switch (ainfo->reg) {
   3914 #if 0 
   3915         case AVS_REG_PVT_MNTR_CONFIG_PVT_MNTR_SW_RESETBr:
   3916 #endif
   3917 /* Shouldn't touch Controlling registers :-) */
   3918 	case CMIC_XGXS0_PLL_CONTROL_1r:
   3919 	case CMIC_XGXS0_PLL_CONTROL_2r:
   3920 	case CMIC_XGXS0_PLL_CONTROL_3r:
   3921 	case CMIC_XGXS0_PLL_CONTROL_4r:
   3922 	case CMIC_XGXS1_PLL_CONTROL_1r:
   3923 	case CMIC_XGXS1_PLL_CONTROL_2r:
   3924 	case CMIC_XGXS1_PLL_CONTROL_3r:
   3925 	case CMIC_XGXS1_PLL_CONTROL_4r:
   3926 	case CMIC_XGXS2_PLL_CONTROL_1r:
   3927 	case CMIC_XGXS2_PLL_CONTROL_2r:
   3928 	case CMIC_XGXS2_PLL_CONTROL_3r:
   3929 	case CMIC_XGXS2_PLL_CONTROL_4r:
   3930 	case CMIC_XGXS3_PLL_CONTROL_1r:
   3931 	case CMIC_XGXS3_PLL_CONTROL_2r:
   3932 	case CMIC_XGXS3_PLL_CONTROL_3r:
   3933 	case CMIC_XGXS3_PLL_CONTROL_4r:
   3934 	case CMIC_MISC_CONTROLr:
   3935 	case CMIC_SBUS_RING_MAP_0_7r:
   3936 	case CMIC_SBUS_RING_MAP_8_15r:
   3937 	case CMIC_SBUS_RING_MAP_16_23r:
   3938 	case CMIC_SBUS_RING_MAP_24_31r:
   3939 	case TOP_SOFT_RESET_REGr:
   3940 	case TOP_SOFT_RESET_REG_2r:
   3941 	case TOP_SOFT_RESET_REG_3r:
   3942 	case TOP_XGXS0_PLL_STATUSr:
   3943 	case TOP_XGXS1_PLL_STATUSr:
   3944 	case TOP_MISC_CONTROL_0r:
   3945 	case TOP_MISC_CONTROL_1r:
   3946 	case TOP_MISC_CONTROL_2r:
   3947 	case TOP_MISC_CONTROL_3r:
   3948 	case TOP_TIME_SYNC_PLL_STATUSr:
   3949 	case TOP_BROAD_SYNC0_PLL_STATUSr:
   3950 	case TOP_BROAD_SYNC1_PLL_STATUSr:
   3951 	case TOP_CORE_PLL0_CTRL_REGISTER_0r:
   3952 	case TOP_CORE_PLL0_CTRL_REGISTER_1r:
   3953 	case TOP_CORE_PLL0_CTRL_REGISTER_2r:
   3954 	case TOP_CORE_PLL0_CTRL_REGISTER_3r:
   3955 	case TOP_CORE_PLL0_CTRL_REGISTER_4r:
   3956 	case TOP_CORE_PLL0_CTRL_REGISTER_5r:
   3957 	case TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r:
   3958 	case TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r:
   3959 	case TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r:
   3960 	case TOP_TIME_SYNC_PLL_CTRL_REGISTER_4r:
   3961 	case TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r:
   3962 	case TOP_XGXS0_PLL_CONTROL_1r:
   3963 	case TOP_XGXS0_PLL_CONTROL_2r:
   3964 	case TOP_XGXS0_PLL_CONTROL_3r:
   3965 	case TOP_XGXS0_PLL_CONTROL_4r:
   3966 	case TOP_XGXS0_PLL_CONTROL_5r:
   3967 	case TOP_XGXS0_PLL_CONTROL_6r:
   3968 	case TOP_XGXS0_PLL_CONTROL_7r:
   3969 	case TOP_XGXS0_PLL_CONTROL_8r:
   3970 	case TOP_XGXS1_PLL_CONTROL_1r:
   3971 	case TOP_XGXS1_PLL_CONTROL_2r:
   3972 	case TOP_XGXS1_PLL_CONTROL_3r:
   3973 	case TOP_XGXS1_PLL_CONTROL_4r:
   3974 	case TOP_XGXS1_PLL_CONTROL_5r:
   3975 	case TOP_XGXS1_PLL_CONTROL_6r:
   3976 	case TOP_XGXS1_PLL_CONTROL_7r:
   3977 	case TOP_XGXS1_PLL_CONTROL_8r:
   3978 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r:
   3979 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_1r:
   3980 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_2r:
   3981 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r:
   3982 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_4r:
   3983 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_5r:
   3984 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_6r:
   3985 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_7r:
   3986 	case IPROC_WRAP_IPROC_DDR_PLL_CTRL_8r:
   3987 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_0r:
   3988 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r:
   3989 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_2r:
   3990 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r:
   3991 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r:
   3992 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_5r:
   3993 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r:
   3994 	case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_7r:
   3995 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_0r:
   3996 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r:
   3997 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_2r:
   3998 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r:
   3999 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r:
   4000 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_5r:
   4001 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r:
   4002 	case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_7r:
   4003 	case CMIC_SBUS_TIMEOUTr:
   4004 	case TOP_MMU_DDR_PHY_CTRLr:
   4005 	case TOP_CI_PHY_CONTROLr:
   4006 	case XPORT_XGXS_CTRLr:
   4007 	case CI_RESETr:
   4008 	case EGR_HW_RESET_CONTROL_1r:
   4009 	case ING_HW_RESET_CONTROL_2r:
   4010 	case IP0_INTR_STATUSr:
   4011 
   4012 	/* Special Registers */
   4013 	case CFAPEFULLRESETPOINTr:
   4014 	case CFAPEFULLSETPOINTr:
   4015 	case CFAPICONFIGr:
   4016 	case CFAPIFULLRESETPOINTr:
   4017 	case CFAPIFULLSETPOINTr:
   4018 	case CHFC_TC2PRI_TBL_ECC_CONFIGr:
   4019 	case MMU_INTFO_CONGST_STr:
   4020 	case OAMP_ERROR_INITIATION_DATAr:
   4021 	case OAMP_INDIRECT_COMMANDr:
   4022 	case OAMP_INDIRECT_COMMAND_WR_DATAr:
   4023 	case OAMP_INTERRUPT_REGISTER_TESTr:
   4024 	case OAMP_SAT_RX_STATr:
   4025 	case PARITY_ERROR_STATUS_0r:
   4026 	case THDIEMA_PARITY_ERROR_STATUS_0r:
   4027 	case THDIEXT_PARITY_ERROR_STATUS_0r:
   4028 	case THDIQEN_PARITY_ERROR_STATUS_0r:
   4029 	case THDIRQE_PARITY_ERROR_STATUS_0r:
   4030 	case THDI_TO_OOBFC_SP_STr:
   4031 	case THDO_TO_OOBFC_SP_STr:
   4032 	case RXLP_DFC_CPU_UPDATE_REFRESHr:
   4033 	case RXLP_DFC_STATUS_HIr:
   4034 	case RXLP_DFC_STATUS_LOr:
   4035 
   4036  
   4037 	case BKPMETERINGBUCKETr:
   4038 	case BKPMETERINGCONFIG_64r:
   4039 	case MTRI_IFGr:
   4040 	case OP_E2ECC_PORT_CONFIGr:
   4041                  COMPILER_64_SET(*mask, 0, 0);
   4042                  rv = 1;
   4043                  break;
   4044         default:
   4045              /* Cannot play with AVS block related registers :-). 
   4046                 Better to ignore as system might retaliate */
   4047              if (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_AVS)) {
   4048                  COMPILER_64_SET(*mask, 0, 0);
   4049                  rv = 1;
   4050                  break;
   4051              }
   4052              break;
   4053         }
   4054     }
   4055     return rv;
   4056 }
   4057 #endif /* BCM_SABER2_SUPPORT */
   4058 
   4059 #ifdef BCM_HURRICANE2_SUPPORT
   4060 STATIC int
   4061 reg_mask_subset_hurricane2(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   4062 {
   4063     if (!SOC_REG_PORT_IDX_VALID(unit,ainfo->reg, ainfo->port, ainfo->idx)) {
   4064         /* set mask to all 0's so test will skip it */
   4065         if (mask != NULL) {
   4066             COMPILER_64_SET(*mask, 0, 0);
   4067         }
   4068         return 1;
   4069     }
   4070 
   4071     if (mask != NULL) {
   4072         switch (ainfo->reg) {
   4073         case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r:
   4074         case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r:
   4075         case TOP_BS_PLL0_CTRL_0r:
   4076         case TOP_BS_PLL0_CTRL_1r:
   4077         case TOP_BS_PLL1_CTRL_0r:
   4078         case TOP_BS_PLL1_CTRL_1r:
   4079         case TOP_TS_PLL_CTRL_4r:
   4080             COMPILER_64_SET(*mask, 0, 0);
   4081             return 1;
   4082         default:
   4083             break;
   4084         }
   4085     }
   4086 
   4087     return 0;
   4088 }
   4089 #endif /* BCM_HURRICANE2_SUPPORT */
   4090 
   4091 #ifdef BCM_GREYHOUND_SUPPORT
   4092 STATIC int
   4093 reg_mask_subset_greyhound(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   4094 {
   4095     int rv = 0;
   4096 
   4097     if (!SOC_REG_PORT_IDX_VALID(unit,ainfo->reg, ainfo->port, ainfo->idx)) {
   4098         /* set mask to all 0's so test will skip it */
   4099         if (mask != NULL) {
   4100             COMPILER_64_SET(*mask, 0, 0);
   4101         }
   4102         return 1;
   4103     }
   4104 
   4105     if (mask != NULL) {
   4106         switch (ainfo->reg) {
   4107         case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r:
   4108         case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r:
   4109         case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r:
   4110         case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r:
   4111         case TOP_XG0_LCPLL_FBDIV_CTRL_0r:
   4112         case TOP_XG0_LCPLL_FBDIV_CTRL_1r:
   4113         case TOP_XG1_LCPLL_FBDIV_CTRL_0r:
   4114         case TOP_XG1_LCPLL_FBDIV_CTRL_1r:
   4115             COMPILER_64_SET(*mask, 0, 0);
   4116             rv = 1;
   4117             break;
   4118         default:
   4119             break;
   4120         }
   4121     }
   4122 
   4123     return rv;
   4124 }
   4125 #endif /* BCM_GREYHOUND_SUPPORT */
   4126 
   4127 #ifdef BCM_HURRICANE3_SUPPORT
   4128 STATIC int
   4129 reg_mask_subset_hurricane3(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   4130 {
   4131     if (!SOC_REG_PORT_IDX_VALID(unit,ainfo->reg, ainfo->port, ainfo->idx)) {
   4132         /* set mask to all 0's so test will skip it */
   4133         if (mask != NULL) {
   4134             COMPILER_64_SET(*mask, 0, 0);
   4135         }
   4136         return 1;
   4137     }
   4138 
   4139     if (mask != NULL) {
   4140         switch (ainfo->reg) {
   4141         case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r:
   4142         case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r:
   4143         case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r:
   4144         case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r:
   4145         case TOP_BS_PLL0_CTRL_0r:
   4146         case TOP_BS_PLL0_CTRL_1r:
   4147         case TOP_BS_PLL1_CTRL_0r:
   4148         case TOP_BS_PLL1_CTRL_1r:
   4149         case TOP_TS_PLL_CTRL_4r:
   4150         case TOP_XG0_LCPLL_FBDIV_CTRL_0r:
   4151         case TOP_XG0_LCPLL_FBDIV_CTRL_1r:
   4152         case TOP_XG1_LCPLL_FBDIV_CTRL_0r:
   4153         case TOP_XG1_LCPLL_FBDIV_CTRL_1r:
   4154         case AVS_REG_PVT_MNTR_CONFIG_PVT_MNTR_CTRLr:
   4155         case AVS_REG_PMB_SLAVE_AVS_PWD_ACC_CONTROLr:
   4156                 /* 
   4157                  * The bit 27 of register, AVS_REG_PMB_SLAVE_AVS_PWD_ACC_CONTROL,
   4158                  * is a DONE bit. The "NOTEST" should be added for this register in the regprofile.
   4159                  * Once the regfile is updated, this register should be removed from here.
   4160                  */
   4161             COMPILER_64_SET(*mask, 0, 0);
   4162             return 1;
   4163         default:
   4164             break;
   4165         }
   4166     }
   4167 
   4168     return 0;
   4169 }
   4170 #endif /* BCM_HURRICANE3_SUPPORT */
   4171 
   4172 
   4173 /*
   4174  * Function: reg_mask_subset
   4175  * 
   4176  * Description: 
   4177  *   Returns 1 if the register is not implemented in HW for the 
   4178  *   specified port/cos. Returns 0 if the register is implemented
   4179  *   in HW. If "mask" argument is supplied, the mask is modified
   4180  *   to only include bits that are implemented in HW for the specified
   4181  *   port/cos index.
   4182  */
   4183 int
   4184 reg_mask_subset(int unit, soc_regaddrinfo_t *ainfo, uint64 *mask)
   4185 {
   4186 #ifdef BCM_TRIUMPH2_SUPPORT
   4187     if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) ||
   4188         SOC_IS_VALKYRIE2(unit)) {
   4189         return (reg_mask_subset_tr2(unit, ainfo, mask));
   4190     }
   4191 #endif
   4192 #ifdef BCM_HURRICANE1_SUPPORT
   4193     if (SOC_IS_HURRICANE(unit)) {
   4194         return (reg_mask_subset_hu(unit, ainfo, mask));
   4195     }
   4196 #endif
   4197 #ifdef BCM_ENDURO_SUPPORT
   4198     if (SOC_IS_ENDURO(unit)) {
   4199         return (reg_mask_subset_en(unit, ainfo, mask));
   4200     }
   4201 #endif
   4202 #ifdef BCM_TRIUMPH3_SUPPORT
   4203     if (SOC_IS_TRIUMPH3(unit)) {
   4204         return (reg_mask_subset_tr3(unit, ainfo, mask));
   4205     }
   4206 #endif
   4207 #ifdef BCM_TOMAHAWK3_SUPPORT
   4208     if (SOC_IS_TOMAHAWK3(unit)) {
   4209         return (reg_mask_subset_tomahawk3(unit, ainfo, mask));
   4210     }
   4211 #endif
   4212 #ifdef BCM_TOMAHAWK_SUPPORT
   4213     if (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) {
   4214         return (reg_mask_subset_tomahawk(unit, ainfo, mask));
   4215     }
   4216 #endif
   4217 #ifdef BCM_APACHE_SUPPORT
   4218     if (SOC_IS_APACHE(unit)) {
   4219         return (reg_mask_subset_apache(unit, ainfo, mask));
   4220     }
   4221 #endif
   4222 #ifdef BCM_TRIDENT2_SUPPORT
   4223     if (SOC_IS_TD2_TT2(unit)) {
   4224         return (reg_mask_subset_trident2(unit, ainfo, mask));
   4225     }
   4226 #endif
   4227 #ifdef BCM_TRIDENT_SUPPORT
   4228     if (SOC_IS_TD_TT(unit)) {
   4229         return (reg_mask_subset_trident(unit, ainfo, mask));
   4230     }
   4231 #endif
   4232 
   4233 #ifdef BCM_SABER2_SUPPORT
   4234     if (SOC_IS_SABER2(unit)) {
   4235         return (reg_mask_subset_saber2(unit, ainfo, mask));
   4236     }
   4237 #endif
   4238 #ifdef BCM_KATANA_SUPPORT
   4239     if (SOC_IS_KATANA(unit)) {
   4240         return (reg_mask_subset_katanax(unit, ainfo, mask));
   4241     }
   4242 #endif
   4243 #ifdef BCM_KATANA2_SUPPORT
   4244     if (SOC_IS_KATANA2(unit)) {
   4245         return (reg_mask_subset_katanax(unit, ainfo, mask));
   4246     }
   4247 #endif
   4248 #ifdef BCM_HURRICANE2_SUPPORT
   4249     if (SOC_IS_HURRICANE2(unit)) {
   4250         return (reg_mask_subset_hurricane2(unit, ainfo, mask));
   4251     }
   4252 #endif
   4253 #ifdef BCM_HURRICANE3_SUPPORT
   4254     if (SOC_IS_HURRICANE3(unit)||SOC_IS_GREYHOUND2(unit)) {
   4255         return (reg_mask_subset_hurricane3(unit, ainfo, mask));
   4256     }
   4257 #endif
   4258 #ifdef BCM_GREYHOUND_SUPPORT
   4259     if (SOC_IS_GREYHOUND(unit)) {
   4260         return (reg_mask_subset_greyhound(unit, ainfo, mask));
   4261     }
   4262 #endif
   4263 #ifdef BCM_TRIUMPH_SUPPORT
   4264     /* This case is a sort of 'catch-All" for triumph Family. So
   4265      * Make sure this comes after others like Hu, En, Kt, Kt2 etc */
   4266     if (SOC_IS_TR_VL(unit)) {
   4267         return (reg_mask_subset_tr(unit, ainfo, mask));
   4268     }
   4269 #endif
   4270 #ifdef BCM_SHADOW_SUPPORT
   4271     if (SOC_IS_SHADOW(unit)) {
   4272         return (reg_mask_subset_sh(unit, ainfo, mask));
   4273     }
   4274 #endif
   4275 #ifdef BCM_SCORPION_SUPPORT
   4276     if (SOC_IS_SC_CQ(unit)) {
   4277         return (reg_mask_subset_sc(unit, ainfo, mask));
   4278     }
   4279 #endif
   4280     return 0;
   4281 }
   4282 
   4283 /* Some registers need to be skipped only in reset value test,
   4284  * -Not- in RW test. So, we can't use the NOTEST flag. List those regs here
   4285  * For RW test, use the reg_mask_subset
   4286  */
   4287 int
   4288 rval_test_skip_reg(int unit, soc_regaddrinfo_t *ainfo, reg_data_t *rd)
   4289 {
   4290 #ifdef BCM_KATANA_SUPPORT
   4291     if (SOC_IS_KATANA(unit)) {
   4292         switch (ainfo->reg) {
   4293             case TOP_MISC_STATUSr:
   4294             case TOP_SWITCH_FEATURE_ENABLE_1r:
   4295             case TOP_SWITCH_FEATURE_ENABLE_2r:
   4296             case TOP_SWITCH_FEATURE_ENABLE_4r:
   4297             case TOP_THERMAL_PVTMON_RESULT_0r:
   4298             case TOP_THERMAL_PVTMON_RESULT_1r:
   4299             case TOP_THERMAL_PVTMON_RESULT_2r:
   4300             case TOP_THERMAL_PVTMON_RESULT_3r:
   4301             case TOP_XGXS_MDIO_CONFIG_0r:
   4302             case TOP_XGXS_MDIO_CONFIG_1r:
   4303             case TOP_XGXS_MDIO_CONFIG_2r:
   4304             case TOP_XGXS_MDIO_CONFIG_3r:
   4305             case TOP_MMU_PLL1_CTRL1r:
   4306             case TOP_MMU_PLL1_CTRL3r:
   4307             case TOP_MMU_PLL2_CTRL1r:
   4308             case TOP_MMU_PLL2_CTRL3r:
   4309             case TOP_MMU_PLL3_CTRL1r:
   4310             case TOP_MMU_PLL3_CTRL3r:
   4311             case TOP_MMU_PLL_STATUS0r:
   4312             case TOP_MMU_PLL_STATUS1r:
   4313             case QUAD0_SERDES_STATUS0r:
   4314             case QUAD0_SERDES_STATUS1r:
   4315             case QUAD1_SERDES_STATUS0r:
   4316             case QUAD0_SERDES_CTRLr:
   4317             case QUAD1_SERDES_CTRLr:
   4318             case MAC_MODEr:
   4319             case OAM_SEC_NS_COUNTER_64r:
   4320             case MMU_ITE_DEBUG_STATUS_0r:
   4321             case TOP_MISC_CONTROL_2r:
   4322             case XPORT_XGXS_NEWCTL_REGr:
   4323             case CI0_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4324             case CI0_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4325             case CI1_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4326             case CI1_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4327             case CI2_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4328             case CI2_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4329             case EMC_BUFFER_EMPTY_FULL_STATUS_DEBUGr:
   4330             case EMC_CFGr:
   4331             case EMC_CI_FULL_STATUS_DEBUGr:
   4332             case EMC_CSDB_0_BUFFER_PAR_STATUS_DEBUGr:
   4333             case EMC_CSDB_1_BUFFER_PAR_STATUS_DEBUGr:
   4334             case EMC_CSDB_2_BUFFER_PAR_STATUS_DEBUGr:
   4335             case EMC_CSDB_MEM_DEBUGr:
   4336             case EMC_ECC_DEBUGr:
   4337             case EMC_ERRB_BUFFER_ECC_STATUS_DEBUGr:
   4338             case EMC_ERRB_BUFFER_FILL_LEVEL_DEBUGr:
   4339             case EMC_ERRB_BUFFER_WATERMARK_DEBUGr:
   4340             case EMC_ERRB_MEM_DEBUGr:
   4341             case EMC_ERRORr:
   4342             case EMC_ERROR_0r:
   4343             case EMC_ERROR_1r:
   4344             case EMC_ERROR_2r:
   4345             case EMC_ERROR_MASK_0r:
   4346             case EMC_ERROR_MASK_1r:
   4347             case EMC_ERROR_MASK_2r:
   4348             case EMC_EWRB_BUFFER_0_ECC_STATUS_DEBUGr:
   4349             case EMC_EWRB_BUFFER_1_ECC_STATUS_DEBUGr:
   4350             case EMC_EWRB_BUFFER_FILL_LEVEL_DEBUGr:
   4351             case EMC_EWRB_BUFFER_WATERMARK_DEBUGr:
   4352             case EMC_EWRB_MEM_DEBUGr:
   4353             case EMC_FREE_POOL_SIZESr:
   4354             case EMC_GLOBAL_1B_ECC_ERROR_COUNT_DEBUGr:
   4355             case EMC_GLOBAL_2B_ECC_ERROR_COUNT_DEBUGr:
   4356             case EMC_IRRB_BUFFER_ECC_STATUS_DEBUGr:
   4357             case EMC_IRRB_BUFFER_FILL_LEVEL_DEBUGr:
   4358             case EMC_IRRB_BUFFER_WATERMARK_DEBUGr:
   4359             case EMC_IRRB_THRESHOLDSr:
   4360             case EMC_IWRB_BUFFER_ECC_STATUS_DEBUGr:
   4361             case EMC_IWRB_BUFFER_FILL_LEVEL_DEBUGr:
   4362             case EMC_IWRB_BUFFER_WATERMARK_DEBUGr:
   4363             case EMC_IWRB_MEM_DEBUGr:
   4364             case EMC_IWRB_SIZEr:
   4365             case EMC_RFCQ_BUFFER_ECC_STATUS_DEBUGr:
   4366             case EMC_RFCQ_BUFFER_FILL_LEVEL_DEBUGr:
   4367             case EMC_RFCQ_BUFFER_WATERMARK_DEBUGr:
   4368             case EMC_RFCQ_MEM_DEBUGr:
   4369             case EMC_RSFP_BUFFER_ECC_STATUS_DEBUGr:
   4370             case EMC_RSFP_BUFFER_FILL_LEVEL_DEBUGr:
   4371             case EMC_RSFP_MEM_DEBUGr:
   4372             case EMC_SWAT_BUFFER_ECC_STATUS_DEBUGr:
   4373             case EMC_SWAT_MEM_DEBUGr:
   4374             case EMC_TO_CI0_RD_REQ_COUNT_DEBUGr:
   4375             case EMC_TO_CI0_WR_REQ_COUNT_DEBUGr:
   4376             case EMC_TO_CI1_RD_REQ_COUNT_DEBUGr:
   4377             case EMC_TO_CI1_WR_REQ_COUNT_DEBUGr:
   4378             case EMC_TO_CI2_RD_REQ_COUNT_DEBUGr:
   4379             case EMC_TO_CI2_WR_REQ_COUNT_DEBUGr:
   4380             case EMC_WCMT_BUFFER_ECC_STATUS_DEBUGr:
   4381             case EMC_WCMT_MEM_DEBUGr:
   4382             case EMC_WLCT0_LOWER_A_BUFFER_ECC_STATUS_DEBUGr:
   4383             case EMC_WLCT0_LOWER_B_BUFFER_ECC_STATUS_DEBUGr:
   4384             case EMC_WLCT0_UPPER_A_BUFFER_ECC_STATUS_DEBUGr:
   4385             case EMC_WLCT0_UPPER_B_BUFFER_ECC_STATUS_DEBUGr:
   4386             case EMC_WLCT1_LOWER_A_BUFFER_ECC_STATUS_DEBUGr:
   4387             case EMC_WLCT1_LOWER_B_BUFFER_ECC_STATUS_DEBUGr:
   4388             case EMC_WLCT1_UPPER_A_BUFFER_ECC_STATUS_DEBUGr:
   4389             case EMC_WLCT1_UPPER_B_BUFFER_ECC_STATUS_DEBUGr:
   4390             case EMC_WLCT2_LOWER_A_BUFFER_ECC_STATUS_DEBUGr:
   4391             case EMC_WLCT2_LOWER_B_BUFFER_ECC_STATUS_DEBUGr:
   4392             case EMC_WLCT2_UPPER_A_BUFFER_ECC_STATUS_DEBUGr:
   4393             case EMC_WLCT2_UPPER_B_BUFFER_ECC_STATUS_DEBUGr:
   4394             case EMC_WLCT_MEM_DEBUGr:
   4395             case EMC_WTFP_BUFFER_ECC_STATUS_DEBUGr:
   4396             case EMC_WTFP_BUFFER_FILL_LEVEL_DEBUGr:
   4397             case EMC_WTFP_MEM_DEBUGr:
   4398             case EMC_WTOQ_BUFFER_ECC_STATUS_DEBUGr:
   4399             case EMC_WTOQ_BUFFER_FILL_LEVEL_DEBUGr:
   4400             case EMC_WTOQ_MEM_DEBUGr:
   4401             case TOP_SWITCH_FEATURE_ENABLE_3r:
   4402             case QSTRUCT_FAPOTPCONFIG_0r:
   4403             case QSTRUCT_FAPOTPCONFIG_1r:
   4404             case QSTRUCT_FAPOTPCONFIG_2r:
   4405             case QSTRUCT_FAPOTPCONFIG_3r:
   4406             case QSTRUCT_FAPCONFIG_0r:
   4407             case QSTRUCT_FAPCONFIG_1r:
   4408             case QSTRUCT_FAPCONFIG_2r:
   4409             case QSTRUCT_FAPCONFIG_3r:
   4410             case CFAPEOTPCONFIGr:
   4411                 return 1;   /* Skip these registers */
   4412             default:
   4413                 return 0;
   4414         }
   4415     }
   4416 #endif 
   4417 #ifdef BCM_SABER2_SUPPORT
   4418     if(SOC_IS_SABER2(unit)) {
   4419         switch (ainfo->reg) {
   4420             case OAMP_GLOBAL_SYS_HEADER_CFGr:
   4421             case OAMP_INDIRECT_WR_MASKr:
   4422             case OAMP_REG_0086r:
   4423             case OAMP_REG_0090r:
   4424             case OAMP_REG_0091r:
   4425             case OAMP_REG_00ADr:
   4426 #ifdef BCM_METROLITE_SUPPORT
   4427             case OAMP_PE_CONSTr:
   4428             case OAMP_PE_PTRr:
   4429             case XLPORT_XGXS_COUNTER_MODEr:
   4430 #endif
   4431                 if (SAL_BOOT_QUICKTURN) {
   4432 #ifdef SABER2_DEBUG
   4433                     LOG_WARN(BSL_LS_APPL_COMMON,
   4434                             (BSL_META_U(unit, "Skipping register %s\n"), 
   4435                              SOC_REG_NAME(unit, ainfo->reg)));
   4436 #endif
   4437                     return 1;
   4438                 } else {
   4439                     return 0;
   4440                 }
   4441             case TOP_CI_PHY_CONTROLr:
   4442             case AVS_REG_HW_MNTR_LAST_MEASURED_SENSORr:
   4443             case AVS_REG_PMB_SLAVE_BPCM_IDr:
   4444             case AVS_REG_RO_REGISTERS_0_CEN_ROSC_STATUSr:
   4445             case AVS_REG_RO_REGISTERS_0_PVT_0P85V_0_MNTR_STATUSr:
   4446             case AVS_REG_RO_REGISTERS_0_PVT_0P85V_1_MNTR_STATUSr:
   4447             case AVS_REG_RO_REGISTERS_0_PVT_1P8V_MNTR_STATUSr:
   4448             case AVS_REG_RO_REGISTERS_0_PVT_1V_0_MNTR_STATUSr:
   4449             case AVS_REG_RO_REGISTERS_0_PVT_1V_1_MNTR_STATUSr:
   4450             case AVS_REG_RO_REGISTERS_0_PVT_3P3V_MNTR_STATUSr:
   4451             case AVS_REG_RO_REGISTERS_0_PVT_TEMPERATURE_MNTR_STATUSr:
   4452             case AVS_REG_TEMPERATURE_MONITOR_TEMPERATURE_MEASUREMENT_STATUSr:
   4453             case AVS_REG_TOP_CTRL_VTRAP_STATUSr:
   4454             case XLMAC_RX_LSS_STATUSr:
   4455             case XLPORT_LED_CHAIN_CONFIGr:
   4456             case CI_ERRORr:
   4457             case CI_RESETr:
   4458             case MMU_ITE_DEBUG_STATUS_0r:
   4459             case TOP_SWITCH_FEATURE_ENABLE_0r:
   4460             case TOP_SWITCH_FEATURE_ENABLE_1r:
   4461             case TOP_SWITCH_FEATURE_ENABLE_2r:
   4462             case TOP_SWITCH_FEATURE_ENABLE_3r:
   4463             case TOP_SWITCH_FEATURE_ENABLE_4r:
   4464             case TOP_SWITCH_FEATURE_ENABLE_5r:
   4465             case TOP_SWITCH_FEATURE_ENABLE_6r:
   4466             case TOP_SWITCH_FEATURE_ENABLE_7r:
   4467             case TOP_XGXS_MDIO_CONFIG_0r:
   4468             case TOP_PVTMON_RESULT_0r:
   4469             case TOP_PVTMON_RESULT_1r:
   4470             case OAMP_ECC_1B_ERR_CNTr:
   4471             case OAMP_ECC_2B_ERR_CNTr:
   4472             case OAMP_GTIMER_CONFIGURATIONr:
   4473             case OAMP_INDIRECT_COMMANDr:
   4474             case OAMP_REG_0087r:
   4475             case OAMP_REG_00AEr:
   4476             case TOP_CI_DDR_PHY_REG_CTRLr:
   4477             case TOP_CI_DDR_PHY_REG_DATAr:
   4478             case TOP_HW_TAP_MEM_ECC_CTRLr:
   4479             case TOP_HW_TAP_MEM_ECC_STATUSr:
   4480             case TOP_MISC_STATUS_0r:
   4481             case TOP_MMU_DDR_PHY_CTRLr:
   4482             case TOP_RESCAL_STATUS_0r:
   4483             case TOP_UC_TAP_READ_DATAr:
   4484             case TOP_XGXS0_PLL_CONTROL_3r:
   4485             case TOP_XGXS0_PLL_CONTROL_4r:
   4486             case TOP_XGXS1_PLL_CONTROL_3r:
   4487             case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r:
   4488             case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r:
   4489             case OAMP_STAT_INTERRUPT_MESSAGEr: 
   4490             case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r:
   4491             case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r:
   4492             case TOP_MASTER_LCPLL_FBDIV_CTRL_0r:
   4493             case TOP_MASTER_LCPLL_FBDIV_CTRL_1r:
   4494             case TOP_SERDES_LCPLL_FBDIV_CTRL_0r:
   4495             case TOP_SERDES_LCPLL_FBDIV_CTRL_1r:
   4496             case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r:
   4497             case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r:
   4498             case CFAPIOTPCONFIGr:
   4499             case TOP_TAP_CONTROLr:
   4500 
   4501                 return 1;  /* Skip these registers */
   4502             default:
   4503                 if ((SAL_BOOT_QUICKTURN) && 
   4504                         (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_AVS))) {
   4505                     /* Skip AVS block registers */
   4506 #ifdef SABER2_DEBUG
   4507                     LOG_WARN(BSL_LS_APPL_COMMON,
   4508                             (BSL_META_U(unit, "Skipping register %s\n"), 
   4509                              SOC_REG_NAME(unit, ainfo->reg)));
   4510 #endif
   4511                     return 1;
   4512                 }
   4513                 return 0;
   4514         }
   4515     }
   4516 #endif
   4517 
   4518 #ifdef BCM_KATANA2_SUPPORT
   4519     if (SOC_IS_KATANA2(unit)) {
   4520         uint16 dev_id;
   4521         uint8  rev_id;
   4522         soc_cm_get_id(unit, &dev_id, &rev_id);
   4523         switch (ainfo->reg) {
   4524             case TOP_HW_TAP_MEM_ECC_CTRLr:
   4525             case TOP_MISC_CONTROL_1r:
   4526             case TOP_MISC_STATUS_0r:
   4527             case TOP_MMU_PLL_INITr:
   4528             case TOP_MMU_PLL_STATUS0r:
   4529             case TOP_MMU_PLL_STATUS1r:
   4530             case TOP_PVTMON_RESULT_0r:
   4531             case TOP_PVTMON_RESULT_1r:
   4532             case TOP_PVTMON_RESULT_2r:
   4533             case TOP_PVTMON_RESULT_3r:
   4534             case TOP_SWITCH_FEATURE_ENABLE_0r:
   4535             case TOP_SWITCH_FEATURE_ENABLE_1r:
   4536             case TOP_SWITCH_FEATURE_ENABLE_2r:
   4537             case TOP_SWITCH_FEATURE_ENABLE_3r:
   4538             case TOP_SWITCH_FEATURE_ENABLE_4r:
   4539             case TOP_SWITCH_FEATURE_ENABLE_5r:
   4540             case TOP_SWITCH_FEATURE_ENABLE_6r:
   4541             case TOP_SW_BOND_OVRD_CTRL0r:
   4542             case TOP_SW_BOND_OVRD_CTRL1r:
   4543             case TOP_UC_TAP_READ_DATAr:
   4544             case MMU_ITE_DEBUG_STATUS_0r:
   4545             case XMAC_RX_LSS_STATUSr:
   4546             case TOP_MISC_CONTROL_2r:
   4547             case TOP_XGXS_MDIO_CONFIG_0r:
   4548             case TOP_XGXS_MDIO_CONFIG_1r:
   4549             case TOP_XGXS_MDIO_CONFIG_2r:
   4550             case TOP_XGXS_MDIO_CONFIG_3r:
   4551             case TOP_MMU_PLL1_CTRL1r:
   4552             case TOP_MMU_PLL1_CTRL3r:
   4553             case TOP_MMU_PLL2_CTRL1r:
   4554             case TOP_MMU_PLL2_CTRL3r:
   4555             case TOP_MMU_PLL3_CTRL1r:
   4556             case TOP_MMU_PLL3_CTRL3r:
   4557             case XPORT_XGXS_NEWCTL_REGr:
   4558             case TOP_TAP_CONTROLr:
   4559             case TOP_MEM_PWR_DWN_BITMAP1_STATUSr:
   4560             case TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r:
   4561             case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_0r:
   4562             case TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r:
   4563             case TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r:
   4564             case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_0r:
   4565             case TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r:
   4566                 return 1;   /* Skip these registers */
   4567             case CFAPECONFIGr:
   4568             case CFAPEOTPCONFIGr:
   4569             case CI0_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4570             case CI0_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4571             case CI1_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4572             case CI1_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4573             case CI2_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4574             case CI2_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4575             case CI3_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4576             case CI3_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4577             case CI4_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4578             case CI4_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4579             case CI5_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUGr:
   4580             case CI5_TO_EMC_WTAG_RETURN_COUNT_DEBUGr:
   4581             case EMC_BUFFER_EMPTY_FULL_STATUS_DEBUGr:
   4582             case EMC_CFGr:
   4583             case EMC_CI_FULL_STATUS_DEBUGr:
   4584             case EMC_CSDB_0_BUFFER_PAR_STATUS_DEBUGr:
   4585             case EMC_CSDB_1_BUFFER_PAR_STATUS_DEBUGr:
   4586             case EMC_CSDB_2_BUFFER_PAR_STATUS_DEBUGr:
   4587             case EMC_CSDB_3_BUFFER_PAR_STATUS_DEBUGr:
   4588             case EMC_CSDB_4_BUFFER_PAR_STATUS_DEBUGr:
   4589             case EMC_CSDB_5_BUFFER_PAR_STATUS_DEBUGr:
   4590             case EMC_CSDB_MEM_DEBUGr:
   4591             case EMC_ECC_DEBUG_0r:
   4592             case EMC_ECC_DEBUG_1r:
   4593             case EMC_ERRB_0_BUFFER_ECC_STATUS_DEBUGr:
   4594             case EMC_ERRB_0_BUFFER_FILL_LEVEL_DEBUGr:
   4595             case EMC_ERRB_0_BUFFER_WATERMARK_DEBUGr:
   4596             case EMC_ERRB_0_MEM_DEBUGr:
   4597             case EMC_ERRB_1_BUFFER_ECC_STATUS_DEBUGr:
   4598             case EMC_ERRB_1_BUFFER_FILL_LEVEL_DEBUGr:
   4599             case EMC_ERRB_1_BUFFER_WATERMARK_DEBUGr:
   4600             case EMC_ERRB_1_MEM_DEBUGr:
   4601             case EMC_ERRB_FIFO_NFULL_THRESHOLDr:
   4602             case EMC_ERRORr:
   4603             case EMC_ERROR_0r:
   4604             case EMC_ERROR_1r:
   4605             case EMC_ERROR_2r:
   4606             case EMC_ERROR_3r:
   4607             case EMC_ERROR_MASK_0r:
   4608             case EMC_ERROR_MASK_1r:
   4609             case EMC_ERROR_MASK_2r:
   4610             case EMC_ERROR_MASK_3r:
   4611             case EMC_EWRB_0_BUFFER_0_ECC_STATUS_DEBUGr:
   4612             case EMC_EWRB_0_BUFFER_1_ECC_STATUS_DEBUGr:
   4613             case EMC_EWRB_0_BUFFER_FILL_LEVEL_DEBUGr:
   4614             case EMC_EWRB_0_BUFFER_WATERMARK_DEBUGr:
   4615             case EMC_EWRB_0_MEM_DEBUGr:
   4616             case EMC_EWRB_1_BUFFER_0_ECC_STATUS_DEBUGr:
   4617             case EMC_EWRB_1_BUFFER_1_ECC_STATUS_DEBUGr:
   4618             case EMC_EWRB_1_BUFFER_FILL_LEVEL_DEBUGr:
   4619             case EMC_EWRB_1_BUFFER_WATERMARK_DEBUGr:
   4620             case EMC_EWRB_1_MEM_DEBUGr:
   4621             case EMC_EWRB_FIFO_NFULL_THRESHOLDr:
   4622             case EMC_FREE_POOL_SIZESr:
   4623             case EMC_GLOBAL_1B_ECC_ERROR_COUNT_DEBUGr:
   4624             case EMC_GLOBAL_2B_ECC_ERROR_COUNT_DEBUGr:
   4625             case EMC_IRRB_BUFFER_ECC_STATUS_DEBUGr:
   4626             case EMC_IRRB_BUFFER_FILL_LEVEL_DEBUGr:
   4627             case EMC_IRRB_BUFFER_WATERMARK_DEBUGr:
   4628             case EMC_IRRB_THRESHOLDSr:
   4629             case EMC_IWRB_BUFFER_ECC_STATUS_DEBUGr:
   4630             case EMC_IWRB_BUFFER_FILL_LEVEL_DEBUGr:
   4631             case EMC_IWRB_BUFFER_WATERMARK_DEBUGr:
   4632             case EMC_IWRB_MEM_DEBUGr:
   4633             case EMC_IWRB_SIZEr:
   4634             case EMC_RFCQ_BUFFER_ECC_STATUS_DEBUGr:
   4635             case EMC_RFCQ_BUFFER_FILL_LEVEL_DEBUGr:
   4636             case EMC_RFCQ_BUFFER_WATERMARK_DEBUGr:
   4637             case EMC_RFCQ_MEM_DEBUGr:
   4638             case EMC_RSFP_BUFFER_ECC_STATUS_DEBUGr:
   4639             case EMC_RSFP_BUFFER_FILL_LEVEL_DEBUGr:
   4640             case EMC_RSFP_MEM_DEBUGr:
   4641             case EMC_SWAT_BUFFER_ECC_STATUS_DEBUGr:
   4642             case EMC_SWAT_MEM_DEBUGr:
   4643             case EMC_TO_CI0_RD_REQ_COUNT_DEBUGr:
   4644             case EMC_TO_CI0_WR_REQ_COUNT_DEBUGr:
   4645             case EMC_TO_CI1_RD_REQ_COUNT_DEBUGr:
   4646             case EMC_TO_CI1_WR_REQ_COUNT_DEBUGr:
   4647             case EMC_TO_CI2_RD_REQ_COUNT_DEBUGr:
   4648             case EMC_TO_CI2_WR_REQ_COUNT_DEBUGr:
   4649             case EMC_TO_CI3_RD_REQ_COUNT_DEBUGr:
   4650             case EMC_TO_CI3_WR_REQ_COUNT_DEBUGr:
   4651             case EMC_TO_CI4_RD_REQ_COUNT_DEBUGr:
   4652             case EMC_TO_CI4_WR_REQ_COUNT_DEBUGr:
   4653             case EMC_TO_CI5_RD_REQ_COUNT_DEBUGr:
   4654             case EMC_TO_CI5_WR_REQ_COUNT_DEBUGr:
   4655             case EMC_WCMT_BUFFER_ECC_STATUS_DEBUGr:
   4656             case EMC_WCMT_MEM_DEBUGr:
   4657             case EMC_WLCT0_LOWER_A_BUFFER_ECC_STATUS_DEBUGr:
   4658             case EMC_WLCT0_LOWER_B_BUFFER_ECC_STATUS_DEBUGr:
   4659             case EMC_WLCT0_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUGr:
   4660             case EMC_WLCT0_UPPER_A_BUFFER_ECC_STATUS_DEBUGr:
   4661             case EMC_WLCT0_UPPER_B_BUFFER_ECC_STATUS_DEBUGr:
   4662             case EMC_WLCT1_LOWER_A_BUFFER_ECC_STATUS_DEBUGr:
   4663             case EMC_WLCT1_LOWER_B_BUFFER_ECC_STATUS_DEBUGr:
   4664             case EMC_WLCT1_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUGr:
   4665             case EMC_WLCT1_UPPER_A_BUFFER_ECC_STATUS_DEBUGr:
   4666             case EMC_WLCT1_UPPER_B_BUFFER_ECC_STATUS_DEBUGr:
   4667             case EMC_WLCT2_LOWER_A_BUFFER_ECC_STATUS_DEBUGr:
   4668             case EMC_WLCT2_LOWER_B_BUFFER_ECC_STATUS_DEBUGr:
   4669             case EMC_WLCT2_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUGr:
   4670             case EMC_WLCT2_UPPER_A_BUFFER_ECC_STATUS_DEBUGr:
   4671             case EMC_WLCT2_UPPER_B_BUFFER_ECC_STATUS_DEBUGr:
   4672             case EMC_WLCT_MEM_DEBUGr:
   4673             case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_MEM_DEBUGr:
   4674             case EMC_WLCT_MERGED_RETURN_WTAG_FIFO_NFULL_THRESHOLDr:
   4675             case EMC_WTFP_BUFFER_ECC_STATUS_DEBUGr:
   4676             case EMC_WTFP_BUFFER_FILL_LEVEL_DEBUGr:
   4677             case EMC_WTFP_MEM_DEBUGr:
   4678             case EMC_WTOQ_BUFFER_ECC_STATUS_DEBUGr:
   4679             case EMC_WTOQ_BUFFER_FILL_LEVEL_DEBUGr:
   4680             case EMC_WTOQ_MEM_DEBUGr:
   4681             case EXT_BUFFER_POOL_CONG_STATEr:
   4682             case FC_MAP_TBL2_ECC_ERR1r:
   4683             case FC_MAP_TBL2_ECC_ERR2r:
   4684             case GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0r:
   4685             case GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL1r:
   4686             case GLOBAL_WRED_AVG_QSIZE_BUFFERIr:
   4687             case GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0r:
   4688             case GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL1r:
   4689             case TOP_MEM_PWR_DWN_BITMAP0_STATUSr:
   4690             case QSTRUCT_FAPCONFIG_0r:
   4691             case QSTRUCT_FAPCONFIG_1r:
   4692             case QSTRUCT_FAPCONFIG_2r:
   4693             case QSTRUCT_FAPCONFIG_3r:
   4694             case QSTRUCT_FAPOTPCONFIG_0r:
   4695             case QSTRUCT_FAPOTPCONFIG_1r:
   4696             case QSTRUCT_FAPOTPCONFIG_2r:
   4697             case QSTRUCT_FAPOTPCONFIG_3r:
   4698             if ((dev_id == BCM56248_DEVICE_ID) ||
   4699                 (dev_id == BCM56456_DEVICE_ID) ||
   4700                 (dev_id == BCM55455_DEVICE_ID))
   4701                 return 1;
   4702             default:
   4703                 return 0;
   4704         }
   4705     }
   4706 #endif
   4707 #ifdef BCM_HURRICANE2_SUPPORT
   4708     if (SOC_IS_HURRICANE2(unit)) {
   4709         switch (ainfo->reg) {
   4710             case TOP_MISC_CONTROL_3r:
   4711             case CMICTXCOSMASKr:
   4712             case MAC_MODEr:
   4713             case TOP_UC_TAP_READ_DATAr:
   4714             case XLMAC_RX_LSS_STATUSr:
   4715                 return 1;   /* Skip these registers */
   4716             default:
   4717                 return 0;
   4718         }
   4719     }
   4720 #endif
   4721 #ifdef BCM_GREYHOUND_SUPPORT
   4722     if(SOC_IS_GREYHOUND(unit)) {
   4723         uint16 dev_id;
   4724         uint8  rev_id;
   4725         soc_cm_get_id(unit, &dev_id, &rev_id);
   4726         switch (ainfo->reg) {
   4727             case CMICTXCOSMASKr:
   4728             case PGW_CTRL_0r:
   4729             case XLPORT_LED_CHAIN_CONFIGr:
   4730             case TOP_XG1_LCPLL_FBDIV_CTRL_1r:
   4731             case TOP_XG_PLL0_CTRL_5r:
   4732             case TOP_XG_PLL0_CTRL_6r:
   4733             case TOP_XG_PLL0_CTRL_7r:
   4734             case TOP_XG_PLL1_CTRL_1r:
   4735             case TOP_XG_PLL1_CTRL_5r: 
   4736             case TOP_XG_PLL1_CTRL_6r:
   4737             case TOP_XG_PLL1_CTRL_7r:
   4738             case TOP_BS_PLL0_CTRL_0r:
   4739             case TOP_BS_PLL0_CTRL_1r:
   4740             case TOP_BS_PLL0_CTRL_5r:
   4741             case TOP_BS_PLL0_CTRL_6r:
   4742             case TOP_BS_PLL0_CTRL_7r:
   4743             case TOP_BS_PLL1_CTRL_0r:
   4744             case TOP_BS_PLL1_CTRL_1r:
   4745             case TOP_BS_PLL1_CTRL_5r:
   4746             case TOP_BS_PLL1_CTRL_6r:
   4747             case TOP_BS_PLL1_CTRL_7r:
   4748             case SPEED_LIMIT_ENTRY0_PHYSICAL_PORT_NUMBERr:
   4749             case SPEED_LIMIT_ENTRY1_PHYSICAL_PORT_NUMBERr:
   4750             case SPEED_LIMIT_ENTRY2_PHYSICAL_PORT_NUMBERr:
   4751             case SPEED_LIMIT_ENTRY3_PHYSICAL_PORT_NUMBERr:                
   4752             case SPEED_LIMIT_ENTRY4_PHYSICAL_PORT_NUMBERr:
   4753             case SPEED_LIMIT_ENTRY8_PHYSICAL_PORT_NUMBERr:
   4754             case SPEED_LIMIT_ENTRY9_PHYSICAL_PORT_NUMBERr:
   4755             case SPEED_LIMIT_ENTRY10_PHYSICAL_PORT_NUMBERr:
   4756             case SPEED_LIMIT_ENTRY11_PHYSICAL_PORT_NUMBERr:
   4757             case SPEED_LIMIT_ENTRY13_PHYSICAL_PORT_NUMBERr:
   4758             case SPEED_LIMIT_ENTRY14_PHYSICAL_PORT_NUMBERr:
   4759             case SPEED_LIMIT_ENTRY15_PHYSICAL_PORT_NUMBERr:
   4760             case SPEED_LIMIT_ENTRY16_PHYSICAL_PORT_NUMBERr:
   4761             case SPEED_LIMIT_ENTRY18_PHYSICAL_PORT_NUMBERr:
   4762             case SPEED_LIMIT_ENTRY22_PHYSICAL_PORT_NUMBERr:
   4763             case SPEED_LIMIT_ENTRY23_PHYSICAL_PORT_NUMBERr:
   4764             case TOP_PVTMON_CTRL_0r:
   4765             case AVS_REG_HW_MNTR_SEQUENCER_MASK_PVT_MNTRr:
   4766                 return 1;
   4767             case CFAPFULLTHRESHOLDr:
   4768                 if ((dev_id == BCM53422_DEVICE_ID) || (dev_id == BCM53424_DEVICE_ID) ||
   4769                     (dev_id == BCM53426_DEVICE_ID)) {
   4770                     return 1;
   4771                 }
   4772                 break;
   4773             default:
   4774                 break;
   4775         }
   4776     }
   4777 #endif
   4778 #ifdef BCM_HURRICANE3_SUPPORT
   4779     if(SOC_IS_HURRICANE3(unit)) {
   4780         if (soc_feature(unit, soc_feature_wh2)) {
   4781             switch (ainfo->reg) {
   4782                 case CMICTXCOSMASKr:
   4783                 case GPORT_SGMII0_CTRL_REGr:
   4784                 case GPORT_SGMII1_CTRL_REGr:
   4785                 case TOP_SOFT_RESET_REGr:
   4786                 case TOP_QGPHY_CTRL_0r:
   4787                 case TOP_SGMII_CTRL_REGr:
   4788                 case TOP_QGPHY_CTRL_2r:
   4789                 case TOP_XG_PLL0_CTRL_3r:
   4790                 case GPORT_XGXS0_CTRL_REGr:
   4791                 case TOP_BS_PLL0_CTRL_3r:
   4792                 case TOP_BS_PLL0_CTRL_5r:
   4793                 case TOP_BS_PLL0_CTRL_6r:
   4794                 case TOP_BS_PLL0_CTRL_7r:
   4795                 case TOP_XG_PLL0_CTRL_5r:
   4796                 case TOP_XG_PLL0_CTRL_6r:
   4797                 case TOP_XG_PLL0_CTRL_7r:
   4798                     return 1;
   4799                 default:
   4800                     break;
   4801             }
   4802         } else {
   4803             uint16 dev_id;
   4804             uint8  rev_id;
   4805             soc_cm_get_id(unit, &dev_id, &rev_id);
   4806             switch (ainfo->reg) {
   4807                 case CMICTXCOSMASKr:
   4808                 case PGW_CTRL_0r:
   4809                 case XLPORT_LED_CHAIN_CONFIGr:
   4810                 case TOP_BS_PLL0_CTRL_0r:
   4811                 case TOP_BS_PLL0_CTRL_1r:
   4812                 case TOP_BS_PLL0_CTRL_3r:
   4813                 case TOP_BS_PLL0_CTRL_5r:
   4814                 case TOP_BS_PLL0_CTRL_6r:
   4815                 case TOP_BS_PLL0_CTRL_7r:
   4816                 case TOP_BS_PLL1_CTRL_0r:
   4817                 case TOP_BS_PLL1_CTRL_1r:
   4818                 case TOP_BS_PLL1_CTRL_3r:
   4819                 case TOP_BS_PLL1_CTRL_5r:
   4820                 case TOP_BS_PLL1_CTRL_6r:
   4821                 case TOP_BS_PLL1_CTRL_7r:
   4822                 case TOP_XG1_LCPLL_FBDIV_CTRL_1r:
   4823                 case TOP_XG_PLL0_CTRL_1r:
   4824                 case TOP_XG_PLL0_CTRL_5r:
   4825                 case TOP_XG_PLL0_CTRL_6r:
   4826                 case TOP_XG_PLL0_CTRL_7r:
   4827                 case TOP_XG_PLL1_CTRL_1r:
   4828                 case TOP_XG_PLL1_CTRL_5r:
   4829                 case TOP_XG_PLL1_CTRL_6r:
   4830                 case TOP_XG_PLL1_CTRL_7r:
   4831                 case SPEED_LIMIT_ENTRY0_PHYSICAL_PORT_NUMBERr:
   4832                 case SPEED_LIMIT_ENTRY4_PHYSICAL_PORT_NUMBERr:
   4833                 case SPEED_LIMIT_ENTRY8_PHYSICAL_PORT_NUMBERr:
   4834                 case SPEED_LIMIT_ENTRY13_PHYSICAL_PORT_NUMBERr:
   4835                 case SPEED_LIMIT_ENTRY14_PHYSICAL_PORT_NUMBERr:
   4836                 case SPEED_LIMIT_ENTRY15_PHYSICAL_PORT_NUMBERr:
   4837                 case SPEED_LIMIT_ENTRY16_PHYSICAL_PORT_NUMBERr:
   4838                 case SPEED_LIMIT_ENTRY18_PHYSICAL_PORT_NUMBERr:
   4839                 case SPEED_LIMIT_ENTRY22_PHYSICAL_PORT_NUMBERr:
   4840                 case SPEED_LIMIT_ENTRY23_PHYSICAL_PORT_NUMBERr:
   4841                 case TOP_PVTMON_CTRL_0r:
   4842                 case AVS_REG_HW_MNTR_SEQUENCER_MASK_PVT_MNTRr:
   4843                 case GPORT_XGXS0_CTRL_REGr:
   4844                 case TPCEr:
   4845                     return 1;
   4846                 case CFAPFULLTHRESHOLDr:
   4847                     if (dev_id == BCM53434_DEVICE_ID) {
   4848                         return 1;
   4849                     }
   4850                     break;
   4851                 default:
   4852                     break;
   4853             }
   4854         }
   4855     }
   4856 #endif
   4857 #ifdef BCM_GREYHOUND2_SUPPORT
   4858     if(SOC_IS_GREYHOUND2(unit)) {
   4859         uint16 dev_id;
   4860         uint8  rev_id;
   4861         soc_cm_get_id(unit, &dev_id, &rev_id);
   4862         switch (ainfo->reg) {
   4863             case CMICTXCOSMASKr:
   4864             case PGW_CTRL_0r:
   4865             case PGW_CL_LED_CHAIN_CONFIGr:
   4866             case PGW_GE_LED_CHAIN_CONFIGr:
   4867             case PGW_XL_LED_CHAIN_CONFIGr:
   4868             case XLPORT_LED_CHAIN_CONFIGr:
   4869             case CLPORT_LED_CHAIN_CONFIGr:
   4870             case TOP_XG1_LCPLL_FBDIV_CTRL_1r:
   4871             case TOP_XG_PLL0_CTRL_6r:
   4872             case TOP_XG_PLL0_CTRL_3r:
   4873             case TOP_XG_PLL0_CTRL_7r:
   4874             case TOP_XG_PLL1_CTRL_1r:
   4875             case TOP_XG_PLL1_CTRL_3r:
   4876             case TOP_XG_PLL1_CTRL_6r:
   4877             case SPEED_LIMIT_ENTRY0_PHYSICAL_PORT_NUMBERr:
   4878             case SPEED_LIMIT_ENTRY4_PHYSICAL_PORT_NUMBERr:
   4879             case SPEED_LIMIT_ENTRY8_PHYSICAL_PORT_NUMBERr:
   4880             case SPEED_LIMIT_ENTRY13_PHYSICAL_PORT_NUMBERr:
   4881             case SPEED_LIMIT_ENTRY14_PHYSICAL_PORT_NUMBERr:
   4882             case SPEED_LIMIT_ENTRY15_PHYSICAL_PORT_NUMBERr:
   4883             case SPEED_LIMIT_ENTRY16_PHYSICAL_PORT_NUMBERr:
   4884             case SPEED_LIMIT_ENTRY18_PHYSICAL_PORT_NUMBERr:
   4885             case SPEED_LIMIT_ENTRY22_PHYSICAL_PORT_NUMBERr:
   4886             case SPEED_LIMIT_ENTRY23_PHYSICAL_PORT_NUMBERr:
   4887             case TOP_PVTMON_CTRL_0r:
   4888             case AVS_REG_HW_MNTR_SEQUENCER_MASK_PVT_MNTRr:
   4889             case GPORT_XGXS0_CTRL_REGr:
   4890             case XLPORT_XGXS0_CTRL_REGr:
   4891             case CLPORT_XGXS0_CTRL_REGr:
   4892             case GPORT_SGMII0_CTRL_REGr:
   4893             case GPORT_SGMII1_CTRL_REGr:
   4894             case SR_RX_FLOW_ID_CONTROLr:
   4895             case SR_TX_FLOW_ID_CONTROLr:
   4896                 return 1;
   4897             default:
   4898                 break;
   4899         }
   4900     }
   4901 #endif
   4902 #ifdef BCM_DFE_SUPPORT
   4903     if(SOC_IS_DFE(unit)) {
   4904         int rv, is_filtered = 0;
   4905 
   4906         rv =  MBCM_DFE_DRIVER_CALL(unit, mbcm_dfe_drv_test_reg_default_val_filter, (unit, ainfo->reg, &is_filtered));
   4907         if (rv == BCM_E_NONE && is_filtered)
   4908         {
   4909             return 1; /* Skip these registers */
   4910         }
   4911     }
   4912 #endif
   4913 #ifdef BCM_DNXF_SUPPORT
   4914     if(SOC_IS_DNXF(unit)) {
   4915 		if (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "AVS_") != NULL) {
   4916 			return 1; /* Skip broadcast registers (sw only registers)*/
   4917 		}
   4918         switch(ainfo->reg) {
   4919 	   case MESH_TOPOLOGY_GLOBAL_MEM_OPTIONSr:
   4920 	   case MESH_TOPOLOGY_RESERVED_MTCPr:
   4921 
   4922 	   case ECI_BLOCKS_POWER_DOWNr:
   4923 	   case CMIC_CPS_RESETr:
   4924 	   case ECI_BLOCKS_SOFT_RESETr:
   4925 	   case ECI_BLOCKS_SOFT_INITr:
   4926 	   case ECI_BLOCKS_SBUS_RESETr:
   4927 	   case ECI_AUTO_DOC_NAME_20r:
   4928 	   case ECI_ECC_ERR_1B_MONITOR_MEM_MASKr:
   4929 	   case ECI_ECC_ERR_2B_MONITOR_MEM_MASKr:
   4930 	   case ECI_ECC_INTERRUPT_REGISTER_MASKr:
   4931 	   case ECI_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4932 	   case ECI_FAP_GLOBAL_GENERAL_CFG_2r:
   4933 	   case ECI_FE_GLOBAL_GENERAL_CFG_1r:
   4934 	   case ECI_INTERRUPT_MASK_REGISTERr:
   4935        case ECI_INDIRECT_COMMAND_ADDRESSr:
   4936        case ECI_TAP_CPU_INTERFACE_COMMANDr:
   4937 	   case FMAC_ASYNC_FIFO_CONFIGURATIONr:
   4938 	   case FMAC_RETIMERr:
   4939 	   /*In these registers the read value
   4940 		  will always be different than write value by design*/
   4941 	   case ECI_INDIRECT_COMMANDr:
   4942 	   case FSRD_INDIRECT_COMMANDr:
   4943 	   case RTP_INDIRECT_COMMANDr:
   4944 	   case DCL_INDIRECT_COMMANDr:
   4945 	   /*SBUS last in chain*/
   4946 	   case QRH_SBUS_BROADCAST_IDr:
   4947 	   case LCM_SBUS_BROADCAST_IDr:
   4948 	   case FSRD_SBUS_BROADCAST_IDr:
   4949 	   case CCH_SBUS_BROADCAST_IDr:
   4950 	   case FMAC_SBUS_BROADCAST_IDr:
   4951 	   case DCML_SBUS_BROADCAST_IDr:
   4952 	   case DCH_SBUS_BROADCAST_IDr:
   4953 	   case FMAC_SBUS_LAST_IN_CHAINr:
   4954 	   case FSRD_SBUS_LAST_IN_CHAINr:
   4955 	   case DCH_SBUS_LAST_IN_CHAINr:
   4956 	   case DCML_SBUS_LAST_IN_CHAINr:
   4957 	   case LCM_SBUS_LAST_IN_CHAINr:
   4958 	   case QRH_SBUS_LAST_IN_CHAINr:
   4959 	   case CCS_SBUS_LAST_IN_CHAINr:
   4960 	   case CCH_SBUS_LAST_IN_CHAINr:
   4961 	   case RTP_SBUS_LAST_IN_CHAINr:
   4962 	   case MESH_TOPOLOGY_SBUS_LAST_IN_CHAINr:
   4963 	   case ECI_SBUS_LAST_IN_CHAINr:
   4964 	   case OCCG_REG_0087r:
   4965 	   case BRDC_CCH_SBUS_BROADCAST_IDr:
   4966 	   case BRDC_DCML_SBUS_BROADCAST_IDr:
   4967 	   case BRDC_LCM_SBUS_BROADCAST_IDr:
   4968 	   case BRDC_QRH_SBUS_BROADCAST_IDr:
   4969 	   /*the following registers are filtered temporarily- the length of these registers should be amended according to the block they are in 
   4970 	   (need to be the longest line of a register that is RW instead of always 640 bit)*/
   4971 	   case DCL_INDIRECT_COMMAND_WR_DATAr:
   4972 	   case ECI_INDIRECT_COMMAND_WR_DATAr:
   4973 	   case FSRD_INDIRECT_COMMAND_WR_DATAr:
   4974 	   case RTP_INDIRECT_COMMAND_WR_DATAr:
   4975 	   /*the following registers should not exist in data base and therefore filtered*/
   4976 					
   4977 	   /*the following registers are filtered because they relate to Pll*/ 
   4978 	   case ECI_REG_0172r:
   4979 	   case ECI_AUTO_DOC_NAME_19r:
   4980 	   case ECI_REG_016Cr:
   4981 	   case ECI_PRM_PLL_CONTROL_STATUSr:
   4982 	   case RTP_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4983 	   case QRH_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4984 	   case MCT_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4985 	   case DCML_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4986 	   case FSRD_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4987 	   case BRDC_DCML_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4988 	   case BRDC_QRH_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   4989        case ECI_ECIC_BLOCKS_RESETr:
   4990        case ECI_MISC_PLL_0_CONFIGr:
   4991        case ECI_MISC_PLL_1_CONFIGr:
   4992        case ECI_MISC_PLL_2_CONFIGr:
   4993        case ECI_MISC_PLL_3_CONFIGr:
   4994        case FMAC_ECC_ERR_1B_MONITOR_MEM_MASKr:
   4995        case FMAC_ECC_ERR_2B_MONITOR_MEM_MASKr:
   4996        case FMAC_ECC_INTERRUPT_REGISTER_MASKr:
   4997        case FMAC_FMAL_GENERAL_CONFIGURATIONr:
   4998        case FMAC_FMAL_RX_GENERAL_CONFIGURATIONr:
   4999        case FMAC_FMAL_STATISTICS_OUTPUT_CONTROLr:
   5000        case FMAC_FMAL_TX_COMMA_BURST_CONFIGURATIONr:
   5001        case FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATIONr:
   5002        case FMAC_FMAL_TX_GENERAL_CONFIGURATIONr:
   5003        case FMAC_FPS_CONFIGURATION_RX_SYNCr:
   5004        case FMAC_INTERRUPT_MASK_REGISTERr:
   5005        case FMAC_LEAKY_BUCKET_CONTROL_REGISTERr:
   5006        case FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr:
   5007        case FMAC_PAR_ERR_MEM_MASKr:
   5008        case FMAC_RECEIVE_RESET_REGISTERr:
   5009        case FMAC_FE_GLOBAL_GENERAL_CFG_1r:
   5010        case FMAC_RSF_CONFIGURATIONr:
   5011        case FMAC_TX_LANE_SWAP_0r:
   5012        case FMAC_TX_LANE_SWAP_1r:
   5013        case FMAC_TX_LANE_SWAP_2r:
   5014        case FMAC_TX_LANE_SWAP_3r:
   5015        case DCML_INDIRECT_COMMANDr:
   5016                return 1; /* Skip these registers */
   5017             default:
   5018                 break;
   5019 		}
   5020     }
   5021 #endif
   5022 
   5023 #ifdef BCM_DNX_SUPPORT
   5024     if(SOC_IS_DNX(unit)) {
   5025 		if (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "AN_") != NULL) {
   5026 			return 1; /* Skip broadcast registers (sw only registers)*/
   5027 		}
   5028 		if (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "BRDC_") != NULL) {
   5029 			return 1; /* Skip broadcast registers (sw only registers)*/
   5030 		}
   5031         switch(ainfo->reg) {
   5032 
   5033             /*SBUS last in chain*/
   5034             case CDMAC_ECC_STATUSr:
   5035             case CDPORT_INTR_STATUSr:
   5036             case CDPORT_LINKSTATUS_DOWNr:
   5037             case CDPORT_TSC_PLL_LOCK_STATUSr:
   5038             case CDPORT_GENERAL_SPARE0_REGr:
   5039             case CDPORT_GENERAL_SPARE1_REGr:
   5040             case CDPORT_GENERAL_SPARE2_REGr:
   5041             case CDPORT_SBUS_CONTROLr:
   5042             case CDPORT_GENERAL_SPARE3_REGr:
   5043             case CDPORT_INTR_ENABLEr:
   5044             case CDPORT_MAC_CONTROLr:
   5045             case CDPORT_MODE_REGr:
   5046             case CDPORT_TSC_MEM_CTRLr:
   5047             case CDPORT_XGXS0_CTRL_REGr:
   5048             case BDM_SBUS_BROADCAST_IDr:
   5049             case CDUM_SBUS_BROADCAST_IDr:
   5050             case CDU_SBUS_BROADCAST_IDr:
   5051             case CFC_SBUS_BROADCAST_IDr:
   5052             case CGM_SBUS_BROADCAST_IDr:
   5053             case CRPS_SBUS_BROADCAST_IDr:
   5054             case DDHA_SBUS_BROADCAST_IDr:
   5055             case DDHB_SBUS_BROADCAST_IDr:
   5056             case DDP_SBUS_BROADCAST_IDr:
   5057             case DHC_SBUS_BROADCAST_IDr:
   5058             case DQM_SBUS_BROADCAST_IDr:
   5059             case ECGM_SBUS_BROADCAST_IDr:
   5060             case ECI_SBUS_BROADCAST_IDr:
   5061             case EDB_SBUS_BROADCAST_IDr:
   5062             case EPNI_SBUS_BROADCAST_IDr:
   5063             case EPRE_SBUS_BROADCAST_IDr:
   5064             case EPS_SBUS_BROADCAST_IDr:
   5065             case ERPP_SBUS_BROADCAST_IDr:
   5066             case ETPPA_SBUS_BROADCAST_IDr:
   5067             case ETPPB_SBUS_BROADCAST_IDr:
   5068             case ETPPC_SBUS_BROADCAST_IDr:
   5069             case EVNT_SBUS_BROADCAST_IDr:
   5070             case FCR_SBUS_BROADCAST_IDr:
   5071             case FCT_SBUS_BROADCAST_IDr:
   5072             case FDA_SBUS_BROADCAST_IDr:
   5073             case FDR_SBUS_BROADCAST_IDr:
   5074             case FDTL_SBUS_BROADCAST_IDr:
   5075             case FDT_SBUS_BROADCAST_IDr:
   5076             case FMAC_SBUS_BROADCAST_IDr:
   5077             case FQP_SBUS_BROADCAST_IDr:
   5078             case FSRD_SBUS_BROADCAST_IDr:
   5079             case HBC_SBUS_BROADCAST_IDr:
   5080             case HBMC_SBUS_BROADCAST_IDr:
   5081             case ILE_SBUS_BROADCAST_IDr:
   5082             case IPPA_SBUS_BROADCAST_IDr:
   5083             case IPPB_SBUS_BROADCAST_IDr:
   5084             case IPPC_SBUS_BROADCAST_IDr:
   5085             case IPPD_SBUS_BROADCAST_IDr:
   5086             case IPPE_SBUS_BROADCAST_IDr:
   5087             case IPPF_SBUS_BROADCAST_IDr:
   5088             case IPS_SBUS_BROADCAST_IDr:
   5089             case IPT_SBUS_BROADCAST_IDr:
   5090             case IQM_SBUS_BROADCAST_IDr:
   5091             case IRE_SBUS_BROADCAST_IDr:
   5092             case ITPPD_SBUS_BROADCAST_IDr:
   5093             case ITPP_SBUS_BROADCAST_IDr:
   5094             case KAPS_SBUS_BROADCAST_IDr:
   5095             case MACT_SBUS_BROADCAST_IDr:
   5096             case MCP_SBUS_BROADCAST_IDr:
   5097             case MDB_SBUS_BROADCAST_IDr:
   5098             case MESH_TOPOLOGY_SBUS_BROADCAST_IDr:
   5099             case MRPS_SBUS_BROADCAST_IDr:
   5100             case MTM_SBUS_BROADCAST_IDr:
   5101             case NMG_SBUS_BROADCAST_IDr:
   5102             case OAMP_SBUS_BROADCAST_IDr:
   5103             case OCB_SBUS_BROADCAST_IDr:
   5104             case OLP_SBUS_BROADCAST_IDr:
   5105             case PDM_SBUS_BROADCAST_IDr:
   5106             case PEM_SBUS_BROADCAST_IDr:
   5107             case PQP_SBUS_BROADCAST_IDr:
   5108             case RQP_SBUS_BROADCAST_IDr:
   5109             case RTP_SBUS_BROADCAST_IDr:
   5110             case SCH_SBUS_BROADCAST_IDr:
   5111             case SIF_SBUS_BROADCAST_IDr:
   5112             case SPB_SBUS_BROADCAST_IDr:
   5113             case SQM_SBUS_BROADCAST_IDr:
   5114             case TCAM_SBUS_BROADCAST_IDr:
   5115             case TDU_SBUS_BROADCAST_IDr:
   5116             /*suspects */
   5117             case ECI_ECIC_MDIO_CONFIGr:
   5118             case ECI_ECIC_MISC_RESETr:
   5119             case ECI_BLOCKS_POWER_DOWNr:
   5120             case ECI_BLOCKS_SBUS_RESETr:
   5121             case ECI_BLOCKS_SOFT_INITr:
   5122             case ECI_BLOCKS_SOFT_RESETr:
   5123             case ECI_TAP_CPU_INTERFACE_COMMANDr:
   5124             case ECI_TS_PLL_CONFIGURATIONSr:
   5125             /* Skipping indirrect command registers */
   5126             case CDU_INDIRECT_COMMANDr:
   5127             case CDUM_INDIRECT_COMMANDr:
   5128             case CFC_INDIRECT_COMMANDr:
   5129             case CGM_INDIRECT_COMMANDr:
   5130             case CRPS_INDIRECT_COMMANDr:
   5131             case DDHA_INDIRECT_COMMANDr:
   5132             case DDHB_INDIRECT_COMMANDr:
   5133             case DHC_INDIRECT_COMMANDr:
   5134             case DQM_INDIRECT_COMMANDr:
   5135             case ECGM_INDIRECT_COMMANDr:
   5136             case ECI_INDIRECT_COMMANDr:
   5137             case EDB_INDIRECT_COMMANDr:
   5138             case EPNI_INDIRECT_COMMANDr:
   5139             case EPS_INDIRECT_COMMANDr:
   5140             case ERPP_INDIRECT_COMMANDr:
   5141             case ETPPA_INDIRECT_COMMANDr:
   5142             case ETPPB_INDIRECT_COMMANDr:
   5143             case ETPPC_INDIRECT_COMMANDr:
   5144             case EVNT_INDIRECT_COMMANDr:
   5145             case FCR_INDIRECT_COMMANDr:
   5146             case FCT_INDIRECT_COMMANDr:
   5147             case FDR_INDIRECT_COMMANDr:
   5148             case FDT_INDIRECT_COMMANDr:
   5149             case FQP_INDIRECT_COMMANDr:
   5150             case FSRD_INDIRECT_COMMANDr:
   5151             case HBC_INDIRECT_COMMANDr:
   5152             case HBMC_INDIRECT_COMMANDr:
   5153             case ILE_INDIRECT_COMMANDr:
   5154             case IPPA_INDIRECT_COMMANDr:
   5155             case IPPB_INDIRECT_COMMANDr:
   5156             case IPPC_INDIRECT_COMMANDr:
   5157             case IPPD_INDIRECT_COMMANDr:
   5158             case IPPE_INDIRECT_COMMANDr:
   5159             case IPPF_INDIRECT_COMMANDr:
   5160             case IPS_INDIRECT_COMMANDr:
   5161             case IPT_INDIRECT_COMMANDr:
   5162             case IQM_INDIRECT_COMMANDr:
   5163             case IRE_INDIRECT_COMMANDr:
   5164             case ITPP_INDIRECT_COMMANDr:
   5165             case ITPPD_INDIRECT_COMMANDr:
   5166             case KAPS_INDIRECT_COMMANDr:
   5167             case MACT_INDIRECT_COMMANDr:
   5168             case MCP_INDIRECT_COMMANDr:
   5169             case MDB_INDIRECT_COMMANDr:
   5170             case MRPS_INDIRECT_COMMANDr:
   5171             case MTM_INDIRECT_COMMANDr:
   5172             case OAMP_INDIRECT_COMMANDr:
   5173             case OCB_INDIRECT_COMMANDr:
   5174             case OLP_INDIRECT_COMMANDr:
   5175             case PEM_INDIRECT_COMMANDr:
   5176             case PQP_INDIRECT_COMMANDr:
   5177             case RQP_INDIRECT_COMMANDr:
   5178             case RTP_INDIRECT_COMMANDr:
   5179             case SCH_INDIRECT_COMMANDr:
   5180             case SPB_INDIRECT_COMMANDr:
   5181             case SQM_INDIRECT_COMMANDr:
   5182             case TCAM_INDIRECT_COMMANDr:
   5183             /* Read only register and driven by another registers */
   5184             case MDB_ARM_KAPS_GLOBAL_EVENTr:
   5185             case MDB_ARM_KAPS_IBC_COMMAND_WORDr:
   5186             case MDB_ARM_KAPS_IBC_FIFO_CORRECTABLE_STATUSr:
   5187             case MDB_ARM_KAPS_IBC_FIFO_UNCORRECTABLE_STATUSr:
   5188             case MDB_ARM_KAPS_IBC_QUEUE_STATUSr:
   5189             case MDB_ARM_KAPS_IBC_RESPONSE_DATAr:
   5190             case MDB_ARM_KAPS_MEMORY_A_ERRORr:
   5191             case MDB_ARM_KAPS_MEMORY_B_ERRORr:
   5192             case MDB_ARM_KAPS_REVISIONr:
   5193             case MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_0r:
   5194             case MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_1r:
   5195             case MDB_ARM_KAPS_R_5_CORE_MEM_CONTROLr:
   5196             case MDB_ARM_KAPS_R_5_DAP_APB_CTRLr:
   5197             case MDB_ARM_KAPS_R_5_DAP_APB_RDATAr:
   5198             case MDB_ARM_KAPS_R_5_DEBUG_STATUSr:
   5199             case MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0r:
   5200             case MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1r:
   5201             case MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_Ar:
   5202             case MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_0r:
   5203             case MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_1r:
   5204             case MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_Ar:
   5205             case MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_0r:
   5206             case MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_1r:
   5207             case MDB_ARM_KAPS_R_5_FIFO_MON_EVENTr:
   5208             case MDB_ARM_KAPS_SEARCH_0_A_ERRORr:
   5209             case MDB_ARM_KAPS_SEARCH_0_B_ERRORr:
   5210             case MDB_ARM_KAPS_SEARCH_1_A_ERRORr:
   5211             case MDB_ARM_KAPS_SEARCH_1_B_ERRORr:
   5212             case MDB_ARM_KAPS_STATUS_CFIFOr:
   5213             case MDB_ARM_KAPS_STATUS_RFIFOr:
   5214             
   5215             case CDMAC_ECC_CTRLr:
   5216             case CDMAC_LINK_INTR_CTRLr:
   5217             case CDMAC_MEM_CTRLr:
   5218             case CDMAC_MIB_COUNTER_MODEr:
   5219             case CDMAC_MIB_COUNTER_PROG_RANGE_CNTR0r:
   5220             case CDMAC_MIB_COUNTER_PROG_RANGE_CNTR1r:
   5221             case CDMAC_MIB_COUNTER_PROG_RANGE_CNTR2r:
   5222             case CDMAC_MIB_COUNTER_PROG_RANGE_CNTR3r:
   5223             case ILKN_X4_CONTROL0_ILKN_CONTROL0r:
   5224             case MAIN0_ECC_1B_ERR_INTERRUPT_ENr:
   5225             case MAIN0_ECC_2B_ERR_INTERRUPT_ENr:
   5226             case MAIN0_ECC_CORRUPT_CONTROL_0r:
   5227             case MAIN0_ECC_CORRUPT_CONTROL_1r:
   5228             case MAIN0_ECC_DISABLE_CONTROLr:
   5229             case MAIN0_SETUPr:
   5230             case MAIN0_TICK_CONTROL_0r:
   5231             case MAIN0_TICK_CONTROL_1r:
   5232             case MAIN0_TM_CONTROLr:
   5233             case PKTGEN0_PCS_SEEDA0r:
   5234             case PKTGEN0_PCS_SEEDA1r:
   5235             case PKTGEN0_PCS_SEEDA2r:
   5236             case PKTGEN0_PCS_SEEDA3r:
   5237             case PKTGEN0_PCS_SEEDB0r:
   5238             case PKTGEN0_PCS_SEEDB1r:
   5239             case PKTGEN0_PCS_SEEDB2r:
   5240             case PKTGEN0_PCS_SEEDB3r:
   5241             case PKTGEN0_PKTGENCTRL1r:
   5242             case PKTGEN0_PRTPCONTROLr:
   5243             case PKTGEN1_ERRORMASK0r:
   5244             case PKTGEN1_ERRORMASK1r:
   5245             case PKTGEN1_ERRORMASK2r:
   5246             case PKTGEN1_ERRORMASK3r:
   5247             case PKTGEN1_ERRORMASK4r:
   5248             case PKTGEN1_GLASTEST_CONTROLr:
   5249             case PMD_X1_CONTROLr:
   5250             case PMD_X1_FCLK_PERIODr:
   5251             case PMD_X1_PM_TIMER_OFFSETr:
   5252             case PMD_X4_CONTROLr:
   5253             case PMD_X4_MODEr:
   5254             case PMD_X4_OVERRIDEr:
   5255             case PMD_X4_RX_FIXED_LATENCYr:
   5256             case PMD_X4_TX_FIXED_LATENCYr:
   5257             case PMD_X4_UI_VALUE_HIr:
   5258             case PMD_X4_UI_VALUE_LOr:
   5259             case RX_X1_CONTROL0_RS_FEC_CONFIGr:
   5260             case RX_X1_CONTROL0_RX_LANE_SWAPr:
   5261             case RX_X4_CONTROL0_DECODE_CONTROL_0r:
   5262             case RX_X4_CONTROL0_PMA_CONTROL_0r:
   5263             case RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0r:
   5264             case RX_X4_CONTROL0_RS_FEC_TIMERr:
   5265             case RX_X4_CONTROL0_RX_TS_CONTROLr:
   5266             case RX_X4_FEC_CONTROL_FEC_0r:
   5267             case RX_X4_FEC_CONTROL_FEC_1r:
   5268             case RX_X4_FEC_CONTROL_FEC_2r:
   5269             case RX_X4_STATUS1_RL_MODE_SW_CONTROLr:
   5270             case SC_X1_CONTROL_PIPELINE_RESET_COUNTr:
   5271             case SC_X1_CONTROL_TX_RESET_COUNTr:
   5272             case SC_X4_CONTROL_CONTROLr:
   5273             case SC_X4_CONTROL_SPARE0r:
   5274             case SC_X4_CONTROL_SW_SPARE1r:
   5275             case SYNCE_X4_FRACTIONAL_DIVr:
   5276             case SYNCE_X4_INTEGER_DIVr:
   5277             case TX_X1_CONTROL0_GLAS_TPMA_CONTROLr:
   5278             case TX_X1_CONTROL0_TX_LANE_SWAPr:
   5279             case TX_X4_CONTROL0_MISCr:
   5280             case TX_X4_CONTROL0_RS_SYMBOLr:
   5281             case TX_X4_CONTROL0_TX_TS_CONTROLr:
   5282             case TX_X4_CONTROL0_ERROR_CONTROLr:
   5283             /* Skipped after consultin with ASIC */
   5284             case IPT_SHAPER_STATUSr:
   5285             case MACT_RESERVED_SPARE_0r:
   5286             case MESH_TOPOLOGY_SPECIAL_CLOCK_CONTROLSr:
   5287             case FMAC_GTIMER_CONFIGURATIONr:
   5288             case FSRD_GTIMER_CONFIGURATIONr:
   5289             /* Registers filled during init */
   5290 
   5291             case CDUM_INDIRECT_FORCE_BUBBLEr:
   5292             case CDU_INDIRECT_FORCE_BUBBLEr:
   5293             case CFC_INDIRECT_FORCE_BUBBLEr:
   5294             case CGM_INDIRECT_FORCE_BUBBLEr:
   5295             case CRPS_INDIRECT_FORCE_BUBBLEr:
   5296             case DDHA_INDIRECT_FORCE_BUBBLEr:
   5297             case DDHA_INDIRECT_WR_MASKr:
   5298             case DDHB_INDIRECT_FORCE_BUBBLEr:
   5299             case DDHB_INDIRECT_WR_MASKr:
   5300             case DHC_INDIRECT_FORCE_BUBBLEr:
   5301             case DHC_INDIRECT_WR_MASKr:
   5302             case DQM_INDIRECT_FORCE_BUBBLEr:
   5303             case ECGM_INDIRECT_FORCE_BUBBLEr:
   5304             case ECI_FAB_0_PLL_CONFIGURATIONSr:
   5305             case ECI_FAB_1_PLL_CONFIGURATIONSr:
   5306             case ECI_INDIRECT_FORCE_BUBBLEr:
   5307             case ECI_NIF_0_PLL_CONFIGURATIONSr:
   5308             case ECI_NIF_1_PLL_CONFIGURATIONSr:
   5309             case ECI_PIR_CONFIGURATIONSr:
   5310             case ECI_RESERVED_20r:
   5311             case ECI_RESERVED_22r:
   5312             case ECI_SBUS_LAST_IN_CHAINr:
   5313             case EDB_INDIRECT_FORCE_BUBBLEr:
   5314             case EPNI_INDIRECT_FORCE_BUBBLEr:
   5315             case EPS_INDIRECT_FORCE_BUBBLEr:
   5316             case ERPP_INDIRECT_FORCE_BUBBLEr:
   5317             case ERPP_INDIRECT_WR_MASKr:
   5318             case ETPPA_INDIRECT_FORCE_BUBBLEr:
   5319             case ETPPB_INDIRECT_FORCE_BUBBLEr:
   5320             case ETPPC_INDIRECT_FORCE_BUBBLEr:
   5321             case EVNT_INDIRECT_FORCE_BUBBLEr:
   5322             case FCR_INDIRECT_FORCE_BUBBLEr:
   5323             case FCT_INDIRECT_FORCE_BUBBLEr:
   5324             case FDR_INDIRECT_FORCE_BUBBLEr:
   5325             case FDT_INDIRECT_FORCE_BUBBLEr:
   5326             case FMAC_RETIMERr:
   5327             case FMAC_SBUS_LAST_IN_CHAINr:
   5328             case FQP_INDIRECT_FORCE_BUBBLEr:
   5329             case FSRD_INDIRECT_FORCE_BUBBLEr:
   5330             case FSRD_SBUS_LAST_IN_CHAINr:
   5331             case HBC_DATA_SOURCE_CONFIGr:
   5332             case HBC_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   5333             case HBC_HBM_COLUMN_ACCESS_TIMINGSr:
   5334             case HBC_HBM_CONFIGr:
   5335             case HBC_HBM_CPU_CONTROLr:
   5336             case HBC_HBM_MODE_REGISTERSr:
   5337             case HBC_HBM_MODE_REGISTER_MANAGER_CONFIGr:
   5338             case HBC_HBM_REFRESH_INTERVALSr:
   5339             case HBC_HBM_REFRESH_TIMINGSr:
   5340             case HBC_HBM_ROW_ACCESS_TIMINGSr:
   5341             case HBC_INDIRECT_COMMAND_ADDRESSr:
   5342             case HBC_INDIRECT_COMMAND_WR_DATAr:
   5343             case HBC_PIPELINES_CONFIGr:
   5344             case HBC_SBUS_LAST_IN_CHAINr:
   5345             case HBC_TSM_CONFIGr:
   5346             case HBMC_ENABLE_DYNAMIC_MEMORY_ACCESSr:
   5347             case HBMC_HBM_PHY_CHANNEL_CONTROLr:
   5348             case HBMC_HBM_PHY_CONTROLr:
   5349             case HBMC_HBM_PLL_CONFIGr:
   5350             case HBMC_HBM_RESET_CONTROLr:
   5351             case HBMC_INDIRECT_COMMAND_ADDRESSr:
   5352             case HBMC_INDIRECT_COMMAND_WR_DATAr:
   5353             case HBMC_INDIRECT_FORCE_BUBBLEr:
   5354             case ILE_INDIRECT_FORCE_BUBBLEr:
   5355             case IPPA_INDIRECT_FORCE_BUBBLEr:
   5356             case IPPA_INDIRECT_WR_MASKr:
   5357             case IPPB_FLPACS_TCAM_PROTECTION_MACHINE_CONFIGURATIONr:
   5358             case IPPB_FLPBCS_TCAM_PROTECTION_MACHINE_CONFIGURATIONr:
   5359             case IPPB_INDIRECT_FORCE_BUBBLEr:
   5360             case IPPB_INDIRECT_WR_MASKr:
   5361             case IPPC_INDIRECT_FORCE_BUBBLEr:
   5362             case IPPC_INDIRECT_WR_MASKr:
   5363             case IPPC_SPECIAL_CLOCK_CONTROLSr:
   5364             case IPPD_INDIRECT_FORCE_BUBBLEr:
   5365             case IPPD_SPECIAL_CLOCK_CONTROLSr:
   5366             case IPPE_INDIRECT_FORCE_BUBBLEr:
   5367             case IPPF_INDIRECT_FORCE_BUBBLEr:
   5368             case IPS_INDIRECT_FORCE_BUBBLEr:
   5369             case IPT_FLOW_CONTROL_DEBUGr:
   5370             case IPT_INDIRECT_FORCE_BUBBLEr:
   5371             case IQM_INDIRECT_FORCE_BUBBLEr:
   5372             case IRE_INDIRECT_FORCE_BUBBLEr:
   5373             case ITPPD_INDIRECT_FORCE_BUBBLEr:
   5374             case ITPP_INDIRECT_FORCE_BUBBLEr:
   5375             case KAPS_INDIRECT_FORCE_BUBBLEr:
   5376             case MACT_INDIRECT_FORCE_BUBBLEr:
   5377             case MCP_INDIRECT_FORCE_BUBBLEr:
   5378             case MDB_INDIRECT_FORCE_BUBBLEr:
   5379             case MRPS_INDIRECT_FORCE_BUBBLEr:
   5380             case MTM_INDIRECT_FORCE_BUBBLEr:
   5381             case OAMP_INDIRECT_FORCE_BUBBLEr:
   5382             case OCB_INDIRECT_FORCE_BUBBLEr:
   5383             case OLP_INDIRECT_FORCE_BUBBLEr:
   5384             case PEM_INDIRECT_FORCE_BUBBLEr:
   5385             case PQP_INDIRECT_FORCE_BUBBLEr:
   5386             case RQP_INDIRECT_FORCE_BUBBLEr:
   5387             case RTP_INDIRECT_FORCE_BUBBLEr:
   5388             case SCH_INDIRECT_FORCE_BUBBLEr:
   5389             case SPB_INDIRECT_FORCE_BUBBLEr:
   5390             case SQM_INDIRECT_FORCE_BUBBLEr:
   5391             case TCAM_INDIRECT_FORCE_BUBBLEr:
   5392             case TDU_ADDRESS_TRANSLATION_CONFIGr:
   5393             case TDU_ADDRESS_TRANSLATION_MATRIXr:
   5394             case TDU_DRAM_BLOCKED_CONFIGr:
   5395             case TDU_READ_DATA_PATH_CONFIGr:
   5396             case TDU_READ_REQUEST_PATH_CONFIGr:
   5397             case TDU_SBUS_LAST_IN_CHAINr:
   5398             case TDU_WRITE_REQUEST_PATH_CONFIGr:
   5399             case SCH_INDIRECT_COMMAND_ADDRESSr:
   5400             case SCH_DVS_NIF_CONFIGr:
   5401             case SCH_DVS_CONFIGr:
   5402                return 1; /* Skip these registers */
   5403             default:
   5404                 break;
   5405 		}
   5406     }
   5407 #endif
   5408 
   5409 #ifdef BCM_PETRA_SUPPORT
   5410     if(SOC_IS_ARAD(unit) && !SOC_IS_JERICHO(unit)) {
   5411         switch(ainfo->reg) {
   5412             case ECI_VERSION_REGISTERr:
   5413                return 1; /* Skip these registers */
   5414             default:
   5415                 break;
   5416         }
   5417     }
   5418     if(SOC_IS_ARDON(unit)) {
   5419         switch(ainfo->reg) {
   5420             case ECI_AVSr:
   5421             case FMAC_ASYNC_FIFO_CONFIGURATIONr:
   5422             case EDB_ESEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTERr:
   5423             case EPNI_ESEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTERr:
   5424                return 1; /* Skip these registers */
   5425             default:
   5426                 break;
   5427         }
   5428     }
   5429     if (SOC_IS_JERICHO_PLUS_ONLY(unit)) {
   5430         switch(ainfo->reg) {
   5431        
   5432         /* clk time changed - Witing for MCM release*/
   5433         case CFC_GTIMER_CONFIGURATIONr:
   5434         case DRCA_GTIMER_CONFIGURATIONr:
   5435         case DRCB_GTIMER_CONFIGURATIONr:
   5436         case DRCC_GTIMER_CONFIGURATIONr:
   5437         case DRCD_GTIMER_CONFIGURATIONr:
   5438         case DRCE_GTIMER_CONFIGURATIONr:
   5439         case DRCF_GTIMER_CONFIGURATIONr:
   5440         case DRCG_GTIMER_CONFIGURATIONr:
   5441         case DRCH_GTIMER_CONFIGURATIONr:
   5442         case OAMP_GTIMER_CONFIGURATIONr:
   5443 
   5444         /* we configure these on init */
   5445             /* Broadcast */
   5446         case CGM_SBUS_BROADCAST_IDr:
   5447         case EGQ_SBUS_BROADCAST_IDr:
   5448         case IHB_SBUS_BROADCAST_IDr:
   5449         case IHP_SBUS_BROADCAST_IDr:
   5450         case IPS_SBUS_BROADCAST_IDr:
   5451         case IQM_SBUS_BROADCAST_IDr:
   5452         case EPNI_SBUS_BROADCAST_IDr:
   5453         case FSRD_SBUS_BROADCAST_IDr:
   5454         case SCH_SBUS_BROADCAST_IDr:
   5455         case KAPS_BBS_SBUS_BROADCAST_IDr:
   5456         case FMAC_SBUS_BROADCAST_IDr:
   5457             /* Last in chain */
   5458         case EPNI_SBUS_LAST_IN_CHAINr:
   5459         case ECI_SBUS_LAST_IN_CHAINr: 
   5460         case EGQ_SBUS_LAST_IN_CHAINr:
   5461         case KAPS_BBS_SBUS_LAST_IN_CHAINr:
   5462         case CGM_SBUS_LAST_IN_CHAINr:
   5463         case FMAC_SBUS_LAST_IN_CHAINr:
   5464         case IHB_SBUS_LAST_IN_CHAINr:
   5465         case IHP_SBUS_LAST_IN_CHAINr:
   5466         case IPS_SBUS_LAST_IN_CHAINr:
   5467         case IQM_SBUS_LAST_IN_CHAINr:
   5468         case SCH_SBUS_LAST_IN_CHAINr:
   5469         case DRCH_REG_0087r:
   5470 
   5471         /* INDIRECT_COMMAND register is a special register and there is no meaning for the "default value". */
   5472         case CFC_INDIRECT_COMMANDr:
   5473         case OAMP_INDIRECT_COMMANDr:
   5474 
   5475         case EPNI_INDIRECT_WR_MASKr:
   5476         case EPNI_ECC_ERR_2B_MONITOR_MEM_MASKr:
   5477         case FCR_ECC_ERR_1B_MONITOR_MEM_MASKr:
   5478         case FCR_ECC_ERR_2B_MONITOR_MEM_MASKr:
   5479         case FDA_ECC_ERR_1B_MONITOR_MEM_MASKr:
   5480         case FDA_ECC_ERR_2B_MONITOR_MEM_MASKr:
   5481         case KAPS_BBS_INDIRECT_WR_MASKr:
   5482         case KAPS_BBS_KAPS_BB_ERROR_REGISTER_MASKr:
   5483         case MESH_TOPOLOGY_GLOBAL_GENERAL_CFG_1r:
   5484         case ECI_BLOCKS_SBUS_RESETr:
   5485         case ECI_BLOCKS_SOFT_RESETr:
   5486         case EDB_INDIRECT_WR_MASKr:
   5487         case IHP_PROTOCOL_TRAPS_PROGRAM_SELECTr:
   5488        
   5489         /* read error */
   5490         case EGQ_INDIRECT_WR_MASKr:
   5491         /* default value should be 0 */
   5492         case FDT_ECC_ERR_1B_MONITOR_MEM_MASKr:
   5493         case FDT_ECC_ERR_2B_MONITOR_MEM_MASKr:
   5494             return 1; /* Skip these registers */
   5495 
   5496             default:
   5497                 break;
   5498         }
   5499     }
   5500     if(SOC_IS_JERICHO(unit)) {
   5501         if (ainfo->reg<rd->start_from || ainfo->reg > rd->start_from + rd->count ) {
   5502             return 1;
   5503         }
   5504         if (!(rd->flags & REGTEST_FLAG_INC_PORT_MACROS)) {
   5505             soc_block_types_t regblktype = SOC_REG_INFO(unit, ainfo->reg).block; 
   5506             if (blocks_can_be_disabled(regblktype)) {
   5507                 return 1;
   5508             }
   5509         }
   5510 
   5511         switch(ainfo->reg) {
   5512 
   5513             case EPNI_CFG_LINK_FIFOS_FIXED_LATENCY_SETTINGr:
   5514             case ECI_CM_PLL_CONFIGr:
   5515             case ECI_UC_PLL_CONFIGr:
   5516             case ECI_NIF_PMH_PLL_CONFIGr:
   5517             case ECI_NIF_PML_0_PLL_CONFIGr:
   5518             case ECI_NIF_PML_1_PLL_CONFIGr:
   5519             case FSRD_SBUS_LAST_IN_CHAINr:
   5520             case ECI_ECIC_BLOCKS_RESETr:
   5521             case ECI_FAB_1_PLL_CONFIGr:
   5522             case MESH_TOPOLOGY_GLOBAL_MEM_OPTIONSr:
   5523             case MESH_TOPOLOGY_RESERVED_MTCPr:
   5524             case ECI_FAB_0_PLL_CONFIGr:
   5525 		    case MRPS_SBUS_BROADCAST_IDr:
   5526 			case MRPS_SBUS_LAST_IN_CHAINr:
   5527 			case MTRPS_EM_SBUS_BROADCAST_IDr:
   5528 			case MTRPS_EM_SBUS_LAST_IN_CHAINr:
   5529 			case SCH_SBUS_BROADCAST_IDr:
   5530 			case SCH_SBUS_LAST_IN_CHAINr:
   5531 			case CFC_GTIMER_CONFIGURATIONr:
   5532 			case CFC_INDIRECT_COMMANDr:
   5533 			case OAMP_GTIMER_CONFIGURATIONr:
   5534 			case OAMP_INDIRECT_COMMANDr:
   5535 			case CGM_SBUS_LAST_IN_CHAINr:
   5536 			case DRCA_GTIMER_CONFIGURATIONr:
   5537 			case DRCB_GTIMER_CONFIGURATIONr:
   5538 			case DRCC_GTIMER_CONFIGURATIONr:
   5539 			case DRCD_GTIMER_CONFIGURATIONr:
   5540 			case DRCE_GTIMER_CONFIGURATIONr:
   5541 			case DRCF_GTIMER_CONFIGURATIONr:
   5542 			case DRCG_GTIMER_CONFIGURATIONr:
   5543 			case DRCH_GTIMER_CONFIGURATIONr:
   5544 			case DRCH_REG_0087r:
   5545 			case ECI_SBUS_LAST_IN_CHAINr:
   5546 			case EGQ_SBUS_LAST_IN_CHAINr:
   5547 			case EPNI_SBUS_LAST_IN_CHAINr:
   5548 			case FMAC_SBUS_BROADCAST_IDr:
   5549 			case FMAC_SBUS_LAST_IN_CHAINr:
   5550 			case FSRD_SBUS_BROADCAST_IDr:
   5551 			case IHB_SBUS_LAST_IN_CHAINr:
   5552 			case IHP_PROTOCOL_TRAPS_PROGRAM_SELECTr:
   5553 			case IHP_SBUS_LAST_IN_CHAINr:
   5554 			case IPS_SBUS_LAST_IN_CHAINr:
   5555 			case IQM_SBUS_LAST_IN_CHAINr:
   5556 			case MESH_TOPOLOGY_GLOBAL_GENERAL_CFG_1r:
   5557 
   5558 #if defined(PLISIM)
   5559                 /* list that we dont get the reset values back from the registers on jer pcid*/
   5560 
   5561             case ILKN_SLE_RX_AFIFO_WMr:
   5562             case ILKN_SLE_RX_BURSTr:
   5563             case ILKN_SLE_RX_CAL_INBANDr:
   5564             case ILKN_SLE_RX_CAL_INBAND_DYNr:
   5565             case ILKN_SLE_RX_CAL_OUTBANDr:
   5566             case ILKN_SLE_RX_CAL_OUTBAND_DYNr:
   5567             case ILKN_SLE_RX_DEBUG_HOLD_0r:
   5568             case ILKN_SLE_RX_DEBUG_HOLD_1r:
   5569             case ILKN_SLE_RX_DEBUG_HOLD_2r:
   5570             case ILKN_SLE_RX_DEBUG_HOLD_3r:
   5571             case ILKN_SLE_RX_EXT_INT_2_ND_MASKr:
   5572             case ILKN_SLE_RX_EXT_INT_FORCEr:
   5573             case ILKN_SLE_RX_EXT_INT_MASKr:
   5574             case ILKN_SLE_RX_INT_2_ND_MASKr:
   5575             case ILKN_SLE_RX_INT_FORCEr:
   5576             case ILKN_SLE_RX_INT_MASKr:
   5577             case ILKN_SLE_RX_LANE_2r:
   5578             case ILKN_SLE_RX_METAFRAMEr:
   5579             case ILKN_SLE_RX_REMAP_LANE_14_10r:
   5580             case ILKN_SLE_RX_REMAP_LANE_19_15r:
   5581             case ILKN_SLE_RX_REMAP_LANE_24_20r:
   5582             case ILKN_SLE_RX_REMAP_LANE_29_25r:
   5583             case ILKN_SLE_RX_REMAP_LANE_34_30r:
   5584             case ILKN_SLE_RX_REMAP_LANE_39_35r:
   5585             case ILKN_SLE_RX_REMAP_LANE_44_40r:
   5586             case ILKN_SLE_RX_REMAP_LANE_47_45r:
   5587             case ILKN_SLE_RX_REMAP_LANE_4_0r:
   5588             case ILKN_SLE_RX_REMAP_LANE_9_5r:
   5589             case ILKN_SLE_RX_RETRANSMIT_CONFIGr:
   5590             case ILKN_SLE_RX_RETRANSMIT_TIME_CONFIGr:
   5591             case ILKN_SLE_RX_RETRANSMIT_TIME_CONFIG_2r:
   5592             case ILKN_SLE_RX_SERDES_TEST_CNTLr:
   5593             case ILKN_SLE_RX_SERDES_TEST_PATTERNAr:
   5594             case ILKN_SLE_RX_SERDES_TEST_PATTERNBr:
   5595             case ILKN_SLE_RX_SERDES_TEST_PATTERNCr:
   5596             case ILKN_SLE_TX_AFIFO_WMr:
   5597             case ILKN_SLE_TX_BURSTr:
   5598             case ILKN_SLE_TX_CAL_INBANDr:
   5599             case ILKN_SLE_TX_CAL_INBAND_DYNr:
   5600             case ILKN_SLE_TX_CAL_OUTBANDr:
   5601             case ILKN_SLE_TX_CAL_OUTBAND_DYNr:
   5602             case ILKN_SLE_TX_DEBUG_HOLD_0r:
   5603             case ILKN_SLE_TX_DEBUG_HOLD_1r:
   5604             case ILKN_SLE_TX_DEBUG_HOLD_2r:
   5605             case ILKN_SLE_TX_DEBUG_HOLD_3r:
   5606             case ILKN_SLE_TX_FIFO_CFGr:
   5607             case ILKN_SLE_TX_INT_2_ND_MASKr:
   5608             case ILKN_SLE_TX_INT_FORCEr:
   5609             case ILKN_SLE_TX_INT_MASKr:
   5610             case ILKN_SLE_TX_LANE_2r:
   5611             case ILKN_SLE_TX_METAFRAMEr:
   5612             case ILKN_SLE_TX_REMAP_LANE_14_10r:
   5613             case ILKN_SLE_TX_REMAP_LANE_19_15r:
   5614             case ILKN_SLE_TX_REMAP_LANE_24_20r:
   5615             case ILKN_SLE_TX_REMAP_LANE_29_25r:
   5616             case ILKN_SLE_TX_REMAP_LANE_34_30r:
   5617             case ILKN_SLE_TX_REMAP_LANE_39_35r:
   5618             case ILKN_SLE_TX_REMAP_LANE_44_40r:
   5619             case ILKN_SLE_TX_REMAP_LANE_47_45r:
   5620             case ILKN_SLE_TX_REMAP_LANE_4_0r:
   5621             case ILKN_SLE_TX_REMAP_LANE_9_5r:
   5622             case ILKN_SLE_TX_RETRANSMIT_CONFIGr:
   5623             case ILKN_SLE_TX_SERDES_TEST_CNTLr:
   5624             case ILKN_SLE_TX_SERDES_TEST_PATTERNAr:
   5625             case ILKN_SLE_TX_SERDES_TEST_PATTERNBr:
   5626             case ILKN_SLE_TX_SERDES_TEST_PATTERNCr:
   5627 #endif   /*(PLISIM) */
   5628 
   5629                 return 1; /* Skip these registers */
   5630             default:
   5631                 break;
   5632         }
   5633         if (SOC_IS_QUX(unit)) {
   5634             /* XLMAC registers cannot access when reset, need confirm(Nir) */
   5635             if ((ainfo->addr & 0xffff0000) == 0x60000) {
   5636                 /* chip reset cannot reset it */
   5637                return 1;
   5638             }
   5639             switch (ainfo->reg) {
   5640                 /* reset chip cannot reach */
   5641                 case CGM_REG_0501r:
   5642                 case EDB_SBUS_LAST_IN_CHAINr:
   5643                 case EPNI_CHICKEN_BIT_VECTORr:
   5644 				    return 1;
   5645                 default:
   5646                     break;
   5647             }
   5648         }
   5649         if(SOC_IS_QAX(unit)) {
   5650 
   5651             if (sal_strstr(SOC_REG_NAME(unit, ainfo->reg), "BROADCAST") != NULL) {
   5652                 return 1; /* Skip broadcast registers (sw only registers)*/
   5653             }
   5654             switch (ainfo->reg) {
   5655              /**
   5656               * DQM - need to review further 
   5657               * regarding other registers 
   5658               * pem,mmu,ipsec_wrapper_b,eci is indeed last in his sbus 
   5659               * chainYaar/Nir - can you comment if that's ok ? 
   5660               * (Tomer) 
   5661               */
   5662                 case  IPSEC_SPU_WRAPPER_TOP_SBUS_LAST_IN_CHAINr:
   5663                 case  MMU_SBUS_LAST_IN_CHAINr:
   5664                 case  PEM_SBUS_LAST_IN_CHAINr:
   5665                 case  ECI_SBUS_LAST_IN_CHAINr:
   5666                 case  DQM_SBUS_LAST_IN_CHAINr:
   5667 
   5668               /**
   5669                * default of this registers is reset(0) but when reset chip 
   5670                * cant be access 
   5671                */
   5672                 case  ECI_BLOCKS_SBUS_RESETr:
   5673                 case  ECI_BLOCKS_SOFT_RESETr:
   5674 
   5675              /**
   5676               * the reset of this values does not apear at excel 
   5677               * and its not 0's 
   5678               */
   5679                 case  ECI_OGER_1027r:
   5680                 case  ECI_OGER_1028r:
   5681                 /* need confirm (Yael) */
   5682                 case ILB_LBRG_CONFIGURATIONr:
   5683                 /**
   5684                  * following registers are not set to default values after init 
   5685                  * (mirror registers) tomer & ariel
   5686                  * CGM_RRP_MIRROR,DQM_DEQ_DRX_DCC_MIRROR,SQM_DEQ_DRX_DCC_MIRROR 
   5687                  */
   5688                 case  CGM_REG_0504r:
   5689                 case  DQM_REG_0119r:
   5690                 case  SQM_REG_0122r:
   5691 
   5692 
   5693                 /**
   5694                  * The PRGE_DEBUG_DATA can be updated by the block - the 
   5695                  * differentce here is OK. (Ofer landau)
   5696                  */
   5697                 case  IPSEC_REG_014Ar:
   5698 
   5699                     return 1; /* Skip these registers */
   5700                 default:
   5701                     break;
   5702             }
   5703         }
   5704     }
   5705 #endif    
   5706 #ifdef BCM_APACHE_SUPPORT
   5707     if (SOC_IS_APACHE(unit)) {
   5708         switch (ainfo->reg) {
   5709             case TOP_TSC_AFE_PLL_STATUSr: 
   5710             case TOP_MISC_CONTROLr:
   5711             case TOP_MISC_CONTROL_2r:
   5712                 /* registers have different values then their reset values */
   5713                 return 1;
   5714             case TOP_TSC_ENABLEr:
   5715             case TOP_CORE_CLK_FREQ_SELr: 
   5716                 /* Overwritten by init soc */
   5717             case XLPORT_TSC_PLL_LOCK_STATUSr:
   5718             case CLPORT_TSC_PLL_LOCK_STATUSr:
   5719             case XLPORT_LED_CHAIN_CONFIGr:
   5720             case CLPORT_LED_CHAIN_CONFIGr:
   5721             case CXXPORT_LED_CHAIN_CONFIGr:
   5722                 /* Changes depending on chip top level integration. */
   5723                 return 1;
   5724             case CFAPCONFIGr:
   5725             case CFAPFULLSETPOINTr:
   5726             case CFAPFULLRESETPOINTr:
   5727                 /* registers have different values then their reset values */
   5728                 return 1;
   5729             case AVS_REG_PMB_SLAVE_AVS_PWD_ACC_CONTROLr:
   5730             case AVS_REG_PMB_SLAVE_AVS_PWD_CONTROLr:
   5731             case AVS_REG_PMB_SLAVE_AVS_ROSC_CONTROLr:
   5732             case AVS_REG_PMB_SLAVE_AVS_ROSC_H_THRESHOLDr:
   5733             case AVS_REG_PMB_SLAVE_AVS_ROSC_S_THRESHOLDr:
   5734             case AVS_REG_PMB_SLAVE_BPCM_CONTROLr:
   5735                 /* ARS wrappers stubbed out in QT. Register access will fail */
   5736                 if (SAL_BOOT_QUICKTURN) {
   5737                     return 1;
   5738                 } else {
   5739                     break;
   5740                 }
   5741             case L2_ISS_BANK_CONFIGr:
   5742             case L3_ISS_BANK_CONFIGr:
   5743             case L2_ISS_LOG_TO_PHY_BANK_MAPr:
   5744             case L3_ISS_LOG_TO_PHY_BANK_MAPr:
   5745                 /* Changes dependent on config properties set during initialization */
   5746                 return 1;
   5747             case TOP_HW_TAP_MEM_IF_ECC_CTRLr:
   5748             case TOP_HW_TAP_MEM_OTP_ECC_CTRLr:
   5749             case TOP_TAP_CONTROLr:
   5750                 /*Following registers are capturing the ECC for chip level memories,
   5751                 so reset value of 0x0 will not match*/
   5752                 return 1;
   5753             case TOP_UC_TAP_CONTROLr:
   5754             case TOP_UC_TAP_WRITE_DATAr:
   5755                 /* OVSTB toggle sequence run during soc init  */
   5756                 return (soc_feature(unit, soc_feature_apache_ovst_toggle));
   5757 
   5758             case TOP_PVTMON_0_INTR_THRESHOLDr:
   5759             case TOP_PVTMON_1_INTR_THRESHOLDr:
   5760             case TOP_PVTMON_2_INTR_THRESHOLDr:
   5761             case TOP_PVTMON_3_INTR_THRESHOLDr:
   5762             case TOP_PVTMON_4_INTR_THRESHOLDr:
   5763             case TOP_PVTMON_5_INTR_THRESHOLDr:
   5764             case TOP_PVTMON_6_INTR_THRESHOLDr:
   5765             case TOP_PVTMON_7_INTR_THRESHOLDr:
   5766             case TOP_PVTMON_MASKr:
   5767                 /*  Registers programmed to non-default value during SOC init */
   5768                 return 1;
   5769             default:
   5770                 break;
   5771         }
   5772     }
   5773 #endif /* BCM_APACHE_SUPPORT */
   5774 
   5775 #ifdef BCM_MONTEREY_SUPPORT
   5776     if (SOC_IS_MONTEREY(unit)) {
   5777         switch (ainfo->reg) {
   5778             case XLPORT_PMD_PLL_CTRL_CONFIGr:
   5779                 /*  Registers programmed to non-default value during SOC init */
   5780                 return 1;
   5781             default:
   5782                 break;
   5783         }
   5784     }
   5785 #endif /* BCM_MONTEREY_SUPPORT */
   5786 #ifdef BCM_TRIDENT2_SUPPORT
   5787     if (SOC_IS_TRIDENT2(unit)) {
   5788         uint16 dev_id;
   5789         uint8  rev_id;
   5790         int    skew_id;
   5791         uint32 rval;
   5792 
   5793         READ_TOP_DEV_REV_IDr(unit, &rval);
   5794         skew_id = soc_reg_field_get(unit, TOP_DEV_REV_IDr, rval, DEVICE_SKEWf);
   5795         soc_cm_get_id(unit, &dev_id, &rev_id);
   5796         switch (ainfo->reg) {
   5797             case TOP_CORE_CLK_FREQ_SELr: 
   5798                 if (rev_id == BCM56850_A0_REV_ID || 
   5799                     (BCM56851_DEVICE_ID == dev_id && skew_id == 2)) { /*56851P*/
   5800                     return 1;
   5801                 }
   5802                 break;
   5803             default:
   5804                 break;
   5805         }
   5806     }
   5807 #endif
   5808 #ifdef BCM_TRIDENT2PLUS_SUPPORT
   5809     if (SOC_IS_TD2P_TT2P(unit)) {
   5810         uint16 dev_id;
   5811         uint8  rev_id;
   5812 
   5813         soc_cm_get_id(unit, &dev_id, &rev_id);
   5814 
   5815         switch (ainfo->reg) {
   5816             case TOP_CORE_CLK_FREQ_SELr:
   5817                 if (BCM56833_DEVICE_ID == dev_id 
   5818                         || BCM56861_DEVICE_ID == dev_id
   5819                         || BCM56864_DEVICE_ID == dev_id
   5820                         || BCM56832_DEVICE_ID == dev_id) {
   5821                     /*
   5822                      * Register has different value than it's reset default
   5823                      * value.
   5824                      */
   5825                     return 1;
   5826                 }
   5827                 break;
   5828             case TOP_MISC_CONTROLr: 
   5829             case TOP_TSC_DISABLEr: 
   5830                 /* registers have different values than their reset values */
   5831                 return 1;
   5832             default:
   5833                 break;
   5834         }
   5835     }
   5836 #endif /* !BCM_TRIDENT2PLUS_SUPPORT */
   5837 #ifdef BCM_TOMAHAWKPLUS_SUPPORT
   5838     if (SOC_IS_TOMAHAWKPLUS(unit)) {
   5839         switch (ainfo->reg) {
   5840             /* registers have different read-only values then their default values */
   5841             case TOP_HW_TAP_MEM_ECC_CTRL_0r:
   5842             case TOP_HW_TAP_MEM_ECC_CTRL_1r:
   5843             case TOP_TAP_CONTROLr:
   5844                 return 1;
   5845             default:
   5846                 break;
   5847         }
   5848     }
   5849 #endif /* !BCM_TOMAHAWKPLUS_SUPPORT */
   5850 
   5851 #ifdef BCM_TOMAHAWK2_SUPPORT
   5852     if (SOC_IS_TOMAHAWK2(unit)) {
   5853         switch (ainfo->reg) {
   5854             case IS_OPP_SCHED_CFGr:
   5855             case IS_OPP_SCHED_CFG_PIPE0r:
   5856             case IS_OPP_SCHED_CFG_PIPE1r:
   5857             case IS_OPP_SCHED_CFG_PIPE2r:
   5858             case IS_OPP_SCHED_CFG_PIPE3r:
   5859             case IS_TDM_CONFIGr:
   5860             case IS_TDM_CONFIG_PIPE0r:
   5861             case IS_TDM_CONFIG_PIPE1r:
   5862             case IS_TDM_CONFIG_PIPE2r:
   5863             case IS_TDM_CONFIG_PIPE3r:
   5864             case TOP_XG_PLL0_CTRL_5r:
   5865             /* registers have different read-only values then their default values */
   5866             case TOP_HW_TAP_MEM_ECC_CTRL_0r:
   5867             case TOP_HW_TAP_MEM_ECC_CTRL_1r:
   5868             case TOP_TAP_CONTROLr:
   5869             /* This register would be modified during init soc */
   5870             case IDB_SER_CONTROLr:
   5871                 /* Skip these registers */
   5872                 return 1;
   5873             default:
   5874                 break;
   5875         }
   5876     }
   5877 #endif
   5878 
   5879 #ifdef BCM_TOMAHAWK3_SUPPORT
   5880     if (SOC_IS_TOMAHAWK3(unit)) {
   5881         switch (ainfo->reg) {
   5882             /* this reg has read-only fields */
   5883             case CDMAC_FIFO_STATUSr:
   5884             case CDMAC_RX_LSS_STATUSr:
   5885             /* This reg has different value for diff dpr clock freq */
   5886             case EPOST_SLOT_PIPELINE_CONFIGr:
   5887             case SLOT_PIPELINE_CONFIGr:
   5888             /* This reg changes its state after deassertion of reset
   5889                so skipping the register */
   5890             case MMU_RQE_INFOTBL_FP_INITr:
   5891                 return 1;
   5892             default:
   5893                 break;
   5894         }
   5895     }
   5896 #endif
   5897 
   5898 #ifdef BCM_TRIDENT3_SUPPORT
   5899             if (SOC_IS_TRIDENT3X(unit)) {
   5900                 switch (ainfo->reg) {
   5901                     /* Ingress Scheduler registers need to be programmed during init to get access to IP/EP block
   5902                      * skip following IS_* registers from TR1 test
   5903                      */
   5904                     case IS_OPP_SCHED_CFGr:
   5905                     case IS_OPP_SCHED_CFG_PIPE0r:
   5906                     case IS_OPP_SCHED_CFG_PIPE1r:
   5907                     case IS_TDM_CONFIGr:
   5908                     case IS_TDM_CONFIG_PIPE0r:
   5909                     case IS_TDM_CONFIG_PIPE1r:
   5910                     case TOP_XG_PLL0_CTRL_5r:
   5911                     /* registers have different read-only values then their default values */
   5912                     case TOP_HW_TAP_MEM_ECC_CTRL_0r:
   5913                     case TOP_HW_TAP_MEM_ECC_CTRL_1r:
   5914                     case TOP_TAP_CONTROLr:
   5915                     /* RH_DLB_SELECTION field in ENHANCED_HASHING_CONTROL needs to be set to 1
   5916                      *  in oder to use RH. This can't be set by default to 1 in init time.
   5917                      *  Hence skip RH related following registers during test.
   5918                      */
   5919                     case RH_ECMP1_DROPSr:
   5920                     case RH_ECMP1_DROPS_PIPE0r:
   5921                     case RH_ECMP1_DROPS_PIPE1r:
   5922                     case RH_ECMP2_DROPSr:
   5923                     case RH_ECMP2_DROPS_PIPE0r:
   5924                     case RH_ECMP2_DROPS_PIPE1r:
   5925                     /* This register would be modified during init soc */
   5926                     case IDB_SER_CONTROLr:
   5927                     case IDB_SER_CONTROL_64r:
   5928                     case TOP_MISC_GENERIC_CONTROLr:
   5929                     case CHIP_CONFIGr:
   5930                         /* Skip these registers */
   5931                         return 1;
   5932                     default:
   5933                         if (SOC_REG_BLOCK_IS(unit, ainfo->reg, SOC_BLK_AVS)) {
   5934                             /* Skip AVS block registers */
   5935                             return 1;
   5936                         }
   5937                         break;
   5938                 }
   5939             }
   5940 #endif
   5941 
   5942     if (SOC_REG_INFO(unit, ainfo->reg).flags &
   5943         (SOC_REG_FLAG_IGNORE_DEFAULT | SOC_REG_FLAG_RO | SOC_REG_FLAG_WO | SOC_REG_FLAG_INTERRUPT | SOC_REG_FLAG_GENERAL_COUNTER | SOC_REG_FLAG_SIGNAL)) {
   5944         return 1;   /* no testable bits */
   5945     }
   5946 
   5947     return 0;
   5948 }
   5949
	openbcm Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
	git clone git://git.finwo.net/mirror/broadcom/openbcm
	Log \| Files \| Refs \| README