i2c_cmds.c (344417B)
1 /* 2 * 3 * 4 * I2C specific commands. 5 * These commands are specific to the I2C driver and or I2C slave 6 * devices which use that driver. See drv/i2c/ for more details. 7 * 8 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 9 * 10 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 11 */ 12 #ifndef NO_SAL_APPL 13 14 #ifdef INCLUDE_I2C 15 16 #include <sal/core/libc.h> 17 #include <sal/core/boot.h> 18 #include <shared/bsl.h> 19 #include <sal/appl/sal.h> 20 #include <sal/appl/io.h> 21 #include <sal/appl/config.h> 22 #include <shared/bsl.h> 23 #include <soc/cmext.h> 24 #include <soc/drv.h> 25 #include <soc/debug.h> 26 #include <soc/i2c.h> 27 #include <soc/mem.h> 28 29 #include <bcm/error.h> 30 #include <bcm/bcmi2c.h> 31 #include <bcm/init.h> 32 #include <bcm/error.h> 33 34 #include <appl/diag/system.h> 35 #ifdef COMPILER_HAS_DOUBLE 36 #include <stdlib.h> 37 #endif 38 39 /* Decimal point formatting */ 40 #define INT_FRAC_1PT(x) (x) / 10, (x) % 10 41 #define INT_FRAC_3PT(x) (x) / 1000, (x) % 1000 42 #define INT_FRAC_3PT_3(x) (x) / 1000000, ((x) / 1000) % 1000 43 #define INT_FRAC_2PT_4(x) (x) / 1000000, ((x) / 10000) % 100 44 45 #define I2C_MUX_VOLTAGE_CONTROL 0 46 STATIC char * _i2c_mux_default_dev_name_get(void); 47 STATIC int dac_devs_init (int unit,int bx, char *mux_dev); 48 49 /* 50 * Function: cmd_pcie 51 * Purpose: Display/Modify pcie config registers via I2C debug BUS 52 */ 53 char cmd_pcie_usage[] = 54 "Usages:\n\t" 55 " pcie r4 [off] [nbytes]\n\t" 56 " - show specified number of pcie bytes starting at offset.\n\t" 57 " pcie w4 [off] [data] \n\t" 58 " - write data byte to specified pcie offset.\n\t" 59 "\n"; 60 61 cmd_result_t 62 cmd_pcie(int unit, args_t *a) 63 { 64 char *function = ARG_GET(a); 65 char *offset = ARG_GET(a); 66 char *dw = ARG_GET(a); 67 uint32 addr, data, i ; 68 uint8* ptr, *dpb; 69 int fd, rv = SOC_E_NONE; 70 71 if (! sh_check_attached(ARG_CMD(a), unit)) 72 return CMD_FAIL; 73 74 if (!function || !offset || !dw) 75 return CMD_USAGE ; 76 77 if ( (fd = bcm_i2c_open(unit, I2C_PCIE_0, 0,0)) < 0) { 78 cli_out("%s: cannot open I2C device %s: %s\n", 79 ARG_CMD(a), I2C_PCIE_0, bcm_errmsg(fd)); 80 return CMD_FAIL; 81 } 82 83 /* NOTE: will use first NVM device found : pcie0*/ 84 cli_out("%s: using device %s\n", ARG_CMD(a), soc_i2c_devname(unit, fd)); 85 addr = parse_integer(offset); 86 data = parse_integer(dw); 87 if ( ! sal_strncasecmp(function, "r4", 2) ){ 88 ptr = (uint8*)sal_alloc(4, "cmd_pcie"); 89 if(!ptr) 90 return CMD_USAGE; 91 /* Pretty print data : one 32-byte page at a time*/ 92 for(i = 0; i < data; i++) { 93 unsigned int r_len =4; 94 if( (rv = bcm_i2c_read(unit, fd, addr + i * 4, ptr, &r_len)) < 0){ 95 cli_out("ERROR: read of %d bytes failed:%s\n", 96 parse_integer(dw), bcm_errmsg(rv)); 97 } 98 cli_out("%04x 0x%02x%02x%02x%02x\n", 99 addr + i * 4, 100 ptr[0], 101 ptr[1], 102 ptr[2], 103 ptr[3]); 104 } 105 cli_out("\nRead %d bytes total\n", data); 106 sal_free(ptr); 107 } else if ( ! sal_strncasecmp(function,"w4",2) ){ 108 dpb = (uint8 *)&data; 109 if( (rv = bcm_i2c_write(unit, fd, addr, dpb, 4)) < 0){ 110 cli_out("ERROR: write of byte at 0x%x failed:%s\n", 111 addr, bcm_errmsg(rv)); 112 } 113 } else { 114 return CMD_USAGE; 115 } 116 return CMD_OK; 117 } 118 119 /* 120 * Function: cmd_nvram 121 * Purpose: Display/Modify NVRAM via Atmel 24C64 64K I2C EEPROM chip. 122 */ 123 char cmd_nvram_usage[] = 124 "Usages:\n\t" 125 " nvram r [off] [nbytes]\n\t" 126 " - show specified number of NVRAM bytes starting at offset.\n\t" 127 " nvram w [off] [data] \n\t" 128 " - write data byte to specified NVRAM offset.\n\t" 129 "\n"; 130 131 cmd_result_t 132 cmd_nvram(int unit, args_t *a) 133 { 134 char *function = ARG_GET(a); 135 char *offset = ARG_GET(a); 136 char *dw = ARG_GET(a); 137 uint32 addr, data, i ; 138 uint8* ptr, db; 139 int fd, rv = SOC_E_NONE; 140 141 if (! sh_check_attached(ARG_CMD(a), unit)) 142 return CMD_FAIL; 143 144 if (!function || !offset || !dw) 145 return CMD_USAGE ; 146 147 if ( (fd = bcm_i2c_open(unit, I2C_NVRAM_0, 0,0)) < 0) { 148 cli_out("%s: cannot open I2C device %s: %s\n", 149 ARG_CMD(a), I2C_NVRAM_0, bcm_errmsg(fd)); 150 return CMD_FAIL; 151 } 152 153 /* NOTE: will use first NVM device found : nvram0*/ 154 cli_out("%s: using device %s\n", ARG_CMD(a), soc_i2c_devname(unit, fd)); 155 addr = parse_integer(offset); 156 data = parse_integer(dw); 157 if ( ! sal_strncasecmp(function, "r", 1) ){ 158 ptr = (uint8*)sal_alloc(data, "cmd_nvram"); 159 if(!ptr) 160 return CMD_USAGE; 161 cli_out("Reading %d bytes at address 0x%x\n\t", data,addr); 162 if( (rv = bcm_i2c_read(unit, fd, addr, ptr, &data)) < 0){ 163 cli_out("ERROR: read of %d bytes failed:%s\n", 164 parse_integer(dw), bcm_errmsg(rv)); 165 } 166 /* Pretty print data : one 32-byte page at a time*/ 167 for(i = 0; i < data; i++){ 168 cli_out("0x%02x ", ptr[i]); 169 if( (i < (data-1)) && ((i % 8) == 7)) 170 cli_out("\n\t"); 171 } 172 cli_out("\nRead %d bytes total\n", data); 173 sal_free(ptr); 174 } else if ( ! sal_strncasecmp(function,"w",1) ){ 175 db = (uint8)data; 176 if( (rv = bcm_i2c_write(unit, fd, addr, &db, 1)) < 0){ 177 cli_out("ERROR: write of byte at 0x%x failed:%s\n", 178 addr, bcm_errmsg(rv)); 179 } 180 } else { 181 return CMD_USAGE; 182 } 183 return CMD_OK; 184 } 185 186 /* 187 * Function: cmd_adc 188 * Purpose: Show MAX127 A/D Conversions for boards with the chip. 189 */ 190 char cmd_adc_usage[] = 191 "Usages:\n\t" 192 " adc show num\n\t" 193 " - show MAX127 A/D Conversions (num = 0,1).\n\t" 194 " adc samples num\n\t" 195 " - set MAX127 A/D Conversions sample count.\n\t" 196 "\n"; 197 cmd_result_t 198 cmd_adc(int unit, args_t *a) 199 { 200 int fd; 201 uint32 num; 202 char dev[25]; 203 char *function = ARG_GET(a); 204 char *chip = ARG_GET(a); 205 206 if (! sh_check_attached(ARG_CMD(a), unit)) 207 return CMD_FAIL; 208 209 if ((! function) || (!chip)) 210 return CMD_USAGE ; 211 num = parse_integer(chip); 212 213 if(!sal_strncasecmp(function,"samples",sal_strlen(function))){ 214 if ( (fd = bcm_i2c_open(unit, I2C_ADC_0,0,0)) < 0) { 215 cli_out("%s: cannot open I2C device %s: %s\n", 216 ARG_CMD(a), dev, bcm_errmsg(fd)); 217 return CMD_FAIL; 218 } 219 if ( (bcm_i2c_ioctl(unit, fd, I2C_ADC_SET_SAMPLES, &num, 0) < 0)) { 220 cli_out("ERROR: failed to set samples count.\n"); 221 } 222 return CMD_OK; 223 } 224 225 /* coverity[secure_coding] */ 226 sprintf(dev,"%s%d","adc",num); 227 228 if ( (fd = bcm_i2c_open(unit, dev,0,0)) < 0) { 229 cli_out("%s: cannot open I2C device %s: %s\n", 230 ARG_CMD(a), dev, bcm_errmsg(fd)); 231 return CMD_FAIL; 232 } 233 234 if ( (bcm_i2c_ioctl(unit, fd, I2C_ADC_DUMP_ALL, NULL, 0) < 0)) { 235 cli_out("ERROR: failed to perform A/D conversions.\n"); 236 } 237 return CMD_OK ; 238 } 239 240 /* 241 * Function: cmd_xclk 242 * Purpose: Set W2239x clock speed for PCI, SDRAM, or core clocks 243 */ 244 char cmd_xclk_usage[] = 245 "Usages:\n\t" 246 #ifdef COMPILER_STRING_CONST_LIMIT 247 " xclocks dump | r | w | core | sdram | pci [...]\n" 248 #else 249 " xclocks dump \n\t" 250 " - display all registers on CY22393x.\n\t" 251 " xclocks r <address> \n\t" 252 " - read CY2239x register at address.\n\t" 253 " xclocks w <address> <data> \n\t" 254 " - write CY22393 register data at address.\n\t" 255 " xclocks core [speed] \n\t" 256 " - set BCM56xx core clock speed.\n\t" 257 " xclocks sdram [speed] \n\t" 258 " - set BCM56xx SDRAM clock speed.\n\t" 259 " xclocks pci [speed] \n\t" 260 " - set BCM56xx PCI clock speed.\n" 261 "In all cases, if a speed is not specified, the current is shown\n" 262 #endif 263 ; 264 265 cmd_result_t 266 cmd_xclk(int unit, args_t *a) 267 { 268 char *source = ARG_GET(a); 269 char *speed = ARG_GET(a); 270 #ifdef COMPILER_HAS_DOUBLE 271 double clockFVal = 0; 272 #else 273 int clockFVal = 0; 274 #endif 275 int cmd = 0; 276 int fd ; 277 278 if (! sh_check_attached(ARG_CMD(a), unit)) 279 return CMD_FAIL; 280 281 if (!source ) { 282 cli_out("Error: no operation or source (core, etc.) specified!\n"); 283 return CMD_FAIL; 284 } 285 /* NOTE: on 5625 BB, MUX (lpt0)=1 */ 286 287 /* Setup ioctl command code */ 288 if(!sal_strcmp(source,"core")){ 289 cmd = (speed != NULL) ? I2C_XPLL_SET_CORE : I2C_XPLL_GET_CORE; 290 } else if (!sal_strcmp(source, "pci")){ 291 cmd = (speed != NULL) ? I2C_XPLL_SET_PCI : I2C_XPLL_GET_PCI; 292 } else if (!sal_strcmp(source, "sdram")){ 293 cmd = (speed != NULL) ? I2C_XPLL_SET_SDRAM : I2C_XPLL_GET_SDRAM; 294 } else if (!sal_strcmp(source, "r") || !sal_strcmp(source, "dump")){ 295 cmd = I2C_XPLL_GET_REG; 296 } else if (!sal_strcmp(source, "w")){ 297 cmd = I2C_XPLL_SET_REG; 298 } else { 299 cli_out("Invalid subcommand or clock source (%s)\n", source); 300 return CMD_USAGE; 301 } 302 /* Open PLL. This should be a CY22393, but could be an older CY22150 */ 303 if ( (fd = bcm_i2c_open(unit, I2C_XPLL_0, 0, 0)) < 0) { 304 cli_out("%s: cannot open I2C device %s: %s\n", 305 ARG_CMD(a), I2C_XPLL_0, bcm_errmsg(fd)); 306 return CMD_FAIL; 307 } 308 if ( I2C_XPLL_GET_REG == cmd ) { 309 /* Read register */ 310 char* addr = speed; 311 uint8 x; 312 uint32 nbytes = 0; 313 314 if( addr) { 315 uint8 off = parse_integer(addr); 316 cli_out("Read register @%s\n", addr); 317 bcm_i2c_read(unit, fd, off, &x, &nbytes); 318 cli_out("pll[%x] = 0x%x\n", off, x); 319 } 320 else { 321 int i; 322 /* Assume the CY22393 driver */ 323 cli_out("Read all registers ...\n"); 324 for( i = 0x08; i <= 0x17; i++) { 325 bcm_i2c_read(unit, fd, i, &x, &nbytes); 326 cli_out("pll[%x] = 0x%x\n", i, x); 327 } 328 for( i = 0x40; i <= 0x57; i++) { 329 bcm_i2c_read(unit, fd, i, &x, &nbytes); 330 cli_out("pll[%x] = 0x%x\n", i, x); 331 } 332 } 333 } else if (I2C_XPLL_SET_REG == cmd ) { 334 /* Write register */ 335 char* addr = speed; 336 char* data = ARG_GET(a); 337 uint8 off,val; 338 cli_out("Write register\n"); 339 if ( !addr || !data) { 340 return CMD_USAGE; 341 } else { 342 off = parse_integer(addr); 343 val = (uint8)parse_integer(data); 344 bcm_i2c_write(unit, fd, off, &val, 1); 345 cli_out("0x%x => pll[%x]\n", val, off); 346 } 347 } else { /* IOCTL's */ 348 /* Set clock speed */ 349 if ( speed) { 350 #ifdef COMPILER_HAS_DOUBLE 351 clockFVal = atof( speed ) ; 352 #else 353 /* Parse input in MHz and convert to Hz */ 354 clockFVal = _shr_atof_exp10(speed, 6); 355 #endif 356 /* Set speed */ 357 if ( (bcm_i2c_ioctl(unit, fd, cmd, &clockFVal, 0) < 0)) { 358 cli_out("ERROR: failed to perform " 359 "clock speed configuration.\n"); 360 return CMD_FAIL; 361 } 362 #ifdef COMPILER_HAS_DOUBLE 363 cli_out("%s: %s clock set to %2.2fMhz\n", 364 I2C_XPLL_0, source, clockFVal ) ; 365 #else 366 cli_out("%s: %s clock set to %d.%02dMhz\n", 367 I2C_XPLL_0, source, 368 INT_FRAC_2PT_4(clockFVal)); 369 #endif 370 } else { 371 /* Get clock speed */ 372 if ( (bcm_i2c_ioctl(unit, fd, cmd,&clockFVal, 0) < 0)){ 373 cli_out("ERROR: failed to retrieve clock configuration.\n"); 374 } 375 #ifdef COMPILER_HAS_DOUBLE 376 cli_out("%s: %s clock is %2.2fMhz\n", 377 I2C_XPLL_0, source, clockFVal ) ; 378 #else 379 cli_out("%s: %s clock is %d.%02dMhz\n", 380 I2C_XPLL_0, source, 381 INT_FRAC_2PT_4(clockFVal)); 382 #endif 383 } 384 } 385 return CMD_OK; 386 } 387 388 /* 389 * Function: cmd_poe 390 * Purpose: Read and write registers in the LTC4258 chip. 391 */ 392 char cmd_poe_usage[] = 393 "Usages:\n\t" 394 #ifdef COMPILER_STRING_CONST_LIMIT 395 " poe poe_num dump | status | clear | r | w\n" 396 #else 397 " poe poe_num dump \n\t" 398 " - display all registers on LTC4258[poe_num].\n\t" 399 " poe poe_num status \n\t" 400 " - display port status on LTC4258[poe_num].\n\t" 401 " poe poe_num clear \n\t" 402 " - clear interrupt bits on LTC4258[poe_num].\n\t" 403 " poe poe_num r <address> \n\t" 404 " - read LTC4258[poe_num] register at address.\n\t" 405 " poe poe_num w <address> <data> \n\t" 406 " - write LTC4258[poe_num] register data at address.\n" 407 "In all cases, poe_num = [1..6]. MuxSel may also be necessary.\n" 408 #endif 409 ; 410 411 cmd_result_t 412 cmd_poe(int unit, args_t *a) 413 { 414 #define I2C_POE_GET_REG 0x10 415 #define I2C_POE_SET_REG 0x20 416 #define TEXTBUFFER_SIZE 1024 417 418 char *num_text = ARG_GET(a); 419 char *op_text = ARG_GET(a); 420 char *addr_text = ARG_GET(a); 421 char *device[6] = { 422 I2C_POE_1, I2C_POE_2, I2C_POE_3, 423 I2C_POE_4, I2C_POE_5, I2C_POE_6 424 }; 425 char* data_text; 426 int poe_num, cmd = 0; 427 int fd ; 428 429 if (! sh_check_attached(ARG_CMD(a), unit)) 430 return CMD_FAIL; 431 432 if (!num_text) { 433 cli_out("ERROR: no PoE index specified!\n"); 434 return CMD_FAIL; 435 } 436 437 if ( ((poe_num = parse_integer(num_text)) < 1) || 438 (poe_num > 6) ) { 439 cli_out("ERROR: invalid PoE poe_num!\n"); 440 return CMD_FAIL; 441 } 442 443 if (!op_text ) { 444 cli_out("ERROR: no operation specified!\n"); 445 return CMD_FAIL; 446 } 447 448 /* Setup ioctl command code */ 449 if (!sal_strcmp(op_text, "dump") || !sal_strcmp(op_text, "r")) { 450 cmd = I2C_POE_GET_REG; 451 } else if (!sal_strcmp(op_text, "status")) { 452 cmd = I2C_POE_IOC_STATUS; 453 } else if (!sal_strcmp(op_text, "clear")) { 454 cmd = I2C_POE_IOC_CLEAR; 455 } else if (!sal_strcmp(op_text, "rescan")) { 456 cmd = I2C_POE_IOC_RESCAN; 457 } else if (!sal_strcmp(op_text, "w")) { 458 cmd = I2C_POE_SET_REG; 459 } else { 460 cli_out("Invalid operation (%s)\n", op_text); 461 return CMD_USAGE; 462 } 463 464 /* Open the LTC4258. */ 465 if ( (fd = bcm_i2c_open(unit, device[poe_num-1], 0, 0)) < 0) { 466 cli_out("%s: cannot open I2C device %s: %s\n", 467 ARG_CMD(a), device[poe_num-1], bcm_errmsg(fd)); 468 return CMD_FAIL; 469 } 470 if ( I2C_POE_GET_REG == cmd ) { 471 /* Read register */ 472 uint8 x; 473 uint32 nbytes = 0; 474 475 if( addr_text) { 476 uint8 off = parse_integer(addr_text); 477 cli_out("Read register [0x%02x]\n", off); 478 bcm_i2c_read(unit, fd, off, &x, &nbytes); 479 cli_out("%s[0x%02x] = 0x%02X\n", device[poe_num-1], off, x); 480 } 481 else { 482 data_text = (char *)sal_alloc(TEXTBUFFER_SIZE, "cmd_poe"); 483 cmd = I2C_POE_IOC_REG_DUMP; 484 if ( (bcm_i2c_ioctl(unit, fd, cmd, data_text, TEXTBUFFER_SIZE) < 0)) { 485 cli_out("ERROR: failed to dump PoE chip registers.\n"); 486 if (data_text) 487 sal_free(data_text); 488 return CMD_FAIL; 489 } 490 cli_out("%s\n", data_text); 491 sal_free(data_text); 492 } 493 } 494 else if (I2C_POE_SET_REG == cmd ) { 495 /* Write register */ 496 uint8 off,val; 497 data_text = ARG_GET(a); 498 cli_out("Write register\n"); 499 500 if ( !addr_text || !data_text) { 501 return CMD_USAGE; 502 } else { 503 off = parse_integer(addr_text); 504 val = (uint8)parse_integer(data_text); 505 bcm_i2c_write(unit, fd, off, &val, 1); 506 cli_out("0x%02X => %s[0x%02x]\n", val, device[poe_num-1], off); 507 } 508 } 509 510 else if (I2C_POE_IOC_CLEAR == cmd ) { 511 /* Clear any PoE interrupts */ 512 if ( (bcm_i2c_ioctl(unit, fd, cmd, NULL, 0) < 0)) { 513 cli_out("ERROR: %s Clear_Interrupts IOCTL failed.\n", 514 device[poe_num-1]); 515 return CMD_FAIL; 516 } 517 } 518 519 else if (I2C_POE_IOC_RESCAN == cmd ) { 520 /* Re-scan (detection and class) */ 521 if ( (bcm_i2c_ioctl(unit, fd, cmd, NULL, 0) < 0)) { 522 cli_out("ERROR: %s ReScan IOCTL failed.\n", device[poe_num-1]); 523 return CMD_FAIL; 524 } 525 } 526 527 else if (I2C_POE_IOC_STATUS == cmd ) { 528 /* Use new IOCTL method to get text information */ 529 data_text = (char *)sal_alloc(TEXTBUFFER_SIZE, "cmd_poe"); 530 if ( (bcm_i2c_ioctl(unit, fd, cmd, data_text, TEXTBUFFER_SIZE) < 0)) { 531 cli_out("ERROR: %s Status IOCTL failed.\n", device[poe_num-1]); 532 if (data_text) 533 sal_free(data_text); 534 return CMD_FAIL; 535 } 536 cli_out("%s\n", data_text); 537 sal_free(data_text); 538 } 539 540 else { /* other IOCTL's */ 541 542 /* Fancy Shmancy IOCTLs under construction 543 * I2C_POE_IOC_ENABLE_PORT 544 * I2C_POE_IOC_AUTO 545 * I2C_POE_IOC_DISABLE_PORT 546 * I2C_POE_IOC_SHUTDOWN 547 */ 548 549 } 550 return CMD_OK; 551 } /* end cmd_poe() */ 552 553 typedef enum { 554 /* Legacy PD was detected */ 555 POE_PD_PSTAT_ON_C = 0, 556 557 /* 802.3af-compliant PD was detected */ 558 POE_PD_PSTAT_ON_R = 1, 559 560 /* Mains voltage is higher than limits; all ports shut down */ 561 POE_PD_PSTAT_OFF_HI = 6, 562 563 /* Mains voltage is lower than limits; all ports shut down */ 564 POE_PD_PSTAT_OFF_LO = 7, 565 566 /* Hardware pin disables all ports */ 567 POE_PD_PSTAT_OFF_HW = 8, 568 569 /* There are fewer ports available than set */ 570 POE_PD_PSTAT_OFF_NULL = 12, 571 572 /* Interim state during power up */ 573 POE_PD_PSTAT_OFF_POWER_UP = 17, 574 575 /* Port does not respond or hardware is at fault */ 576 POE_PD_PSTAT_OFF_HW_INT = 18, 577 578 /* User command set port to off */ 579 POE_PD_PSTAT_OFF_USER_CMD = 26, 580 581 /* Interim state during line detection */ 582 POE_PD_PSTAT_OFF_DET = 27, 583 584 /* Non-standard PD connected */ 585 POE_PD_PSTAT_OFF_NON_PD = 28, 586 587 /* Succession of under/over load states caused port shutdown */ 588 POE_PD_PSTAT_OFF_UNDER_OVER = 29, 589 590 /* Underload state according to 802.3af or Signature capacitor < 22uF */ 591 POE_PD_PSTAT_OFF_UNDER_CAP = 30, 592 593 /* Overload state accourding to 802.3af or Signature capacitor > 1000uF */ 594 POE_PD_PSTAT_OFF_OVER_CAP = 31, 595 596 /* Power management fn shut down port due to lack of power */ 597 POE_PD_PSTAT_OFF_LACK = 32, 598 599 /* Hardware problems preventing port operation */ 600 POE_PD_PSTAT_OFF_INT_HW = 33, 601 602 /* Port fails capacitor detection due to voltage being applied */ 603 POE_PD_PSTAT_OFF_VOL_INJ = 36, 604 605 /* Port fails capacitor detection due to out-out-range capacitor value */ 606 POE_PD_PSTAT_OFF_CAP_OUT = 37, 607 608 /* Port fails capacitor detection due to discharged capacitor */ 609 POE_PD_PSTAT_OFF_CAP_DET = 38, 610 611 /* Port is forced on, unless systems error occurs */ 612 POE_PD_PSTAT_ON_FORCE = 43, 613 614 /* Underfined error during force on */ 615 POE_PD_PSTAT_ON_UNDEF = 44, 616 617 /* Supply voltage higher than settings */ 618 /* (error appears only after port is forced on) */ 619 POE_PD_PSTAT_ON_VOL_HI = 45, 620 621 /* Supply voltage lower than settings */ 622 POE_PD_PSTAT_ON_VOL_LO = 46, 623 624 /* Disable_PDU flags was raised during force on */ 625 POE_PD_PSTAT_ON_PDU_FLAG = 47, 626 627 /* Disabling is done by "Set on/off" command */ 628 POE_PD_PSTAT_ON_OFF_CMD = 48, 629 630 /* Overload condition according to 802.3af */ 631 POE_PD_PSTAT_OFF_OVERLOAD = 49, 632 633 /* Power management mechanism detects out of power budget */ 634 POE_PD_PSTAT_OFF_BUDGET = 50, 635 636 /* Communication error with ASIC, after force on command */ 637 POE_PD_PSTAT_ON_ERR_ASIC = 51 638 } poe_pd_port_status_t; 639 640 STATIC char* 641 poe_pd_decode_port_status(poe_pd_port_status_t status) 642 { 643 switch (status) { 644 case POE_PD_PSTAT_ON_C: 645 return "On (valid capacitor detected)"; 646 case POE_PD_PSTAT_ON_R: 647 return "On (valid resistor detected)"; 648 case POE_PD_PSTAT_OFF_HI: 649 return "Off (main supply voltage higher than permitted)"; 650 case POE_PD_PSTAT_OFF_LO: 651 return "Off (main supply voltage lower than permitted)"; 652 case POE_PD_PSTAT_OFF_HW: 653 return "Off ('disable all ports' pin is active)"; 654 case POE_PD_PSTAT_OFF_NULL: 655 return "Off (non-existing port number)"; 656 case POE_PD_PSTAT_OFF_POWER_UP: 657 return "Off (power-up is in process)"; 658 case POE_PD_PSTAT_OFF_HW_INT: 659 return "Off (internal hardware fault)"; 660 case POE_PD_PSTAT_OFF_USER_CMD: 661 return "Off (user setting)"; 662 case POE_PD_PSTAT_OFF_DET: 663 return "Off (detection is in process)"; 664 case POE_PD_PSTAT_OFF_NON_PD: 665 return "Off (non-802.3af powered device)"; 666 case POE_PD_PSTAT_OFF_UNDER_OVER: 667 return "Off (overload & underload states)"; 668 case POE_PD_PSTAT_OFF_UNDER_CAP: 669 return "Off (underload state or capacitor value is too samll)"; 670 case POE_PD_PSTAT_OFF_OVER_CAP: 671 return "Off (overload state or capacitor value is too large)"; 672 case POE_PD_PSTAT_OFF_LACK: 673 return "Off (power budget exceeded)"; 674 case POE_PD_PSTAT_OFF_INT_HW: 675 return "Off (internal hardware fault)"; 676 case POE_PD_PSTAT_OFF_VOL_INJ: 677 return "Off (voltage injection into the port)"; 678 case POE_PD_PSTAT_OFF_CAP_OUT: 679 return "Off (improper capacitor detection result)"; 680 case POE_PD_PSTAT_OFF_CAP_DET: 681 return "Off (discharged load)"; 682 case POE_PD_PSTAT_ON_FORCE: 683 return "On (force on, unless systems error occurs)"; 684 case POE_PD_PSTAT_ON_UNDEF: 685 return "Undefined error during force on"; 686 case POE_PD_PSTAT_ON_VOL_HI: 687 return "Supply voltage higher than settings"; 688 case POE_PD_PSTAT_ON_VOL_LO : 689 return "Supply voltage lower than settings"; 690 case POE_PD_PSTAT_ON_PDU_FLAG: 691 return "Disable_PDU flag was raised during force on"; 692 case POE_PD_PSTAT_ON_OFF_CMD: 693 return "Port is forced on then disabled or disabled then forced on"; 694 case POE_PD_PSTAT_OFF_OVERLOAD: 695 return "Off (overload condition accouding to 802.3af)"; 696 case POE_PD_PSTAT_OFF_BUDGET: 697 return "Off (out of power budget while in forced power state)"; 698 case POE_PD_PSTAT_ON_ERR_ASIC: 699 return "Communication error with ASIC after force on command"; 700 default: 701 return "Unknown status ?"; 702 } 703 } 704 705 STATIC void 706 poe_pd_pkt_dump(uint8 *src, int len, char *msg) 707 { 708 int i; 709 710 if (msg || !len) 711 cli_out("%s (%d):\n", msg, len ); 712 for (i = 0; i < len; i++) { 713 cli_out("0x%02x ", src[i]); 714 if (!((i + 1) % 16)) 715 cli_out("\n"); 716 } 717 cli_out("\n"); 718 } 719 720 STATIC void 721 poe_pd_pkt_cksum(unsigned char *data) 722 { 723 int i; 724 uint16 sum=0; 725 for (i = 0; i < 13; i++) { 726 sum += data[i]; 727 } 728 data[13] = (sum & 0xff00) >> 8; 729 data[14] = sum & 0xff; 730 } 731 732 STATIC int 733 poe_pd_pkt_txrx(int unit, int fd, unsigned char *data, 734 int seq, int debug) 735 { 736 int rv; 737 uint32 len; 738 soc_timeout_t to; 739 740 if ((rv = bcm_i2c_write(unit, fd, 0, data, 15)) < 0) { 741 cli_out("ERROR: write byte failed: %s\n", 742 bcm_errmsg(rv)); 743 return CMD_FAIL; 744 } 745 746 if (debug) { 747 poe_pd_pkt_dump(data, 15, "Tx to PD63000"); 748 } 749 750 memset(data, 0x0, 15); 751 soc_timeout_init(&to, 100000, 0); 752 for (;;) { 753 if (soc_timeout_check(&to)) { 754 break; 755 } 756 } 757 758 if((rv = bcm_i2c_read(unit, fd, 0, data, &len)) < 0){ 759 cli_out("ERROR: read byte failed: %s\n", 760 bcm_errmsg(rv)); 761 return CMD_FAIL; 762 } 763 764 if (debug) { 765 poe_pd_pkt_dump(data, 15, "Rx from PD63000"); 766 } 767 768 if (data[1] != seq) { 769 seq++; 770 cli_out("ERROR: read from PD630000 out of sync.\n"); 771 cli_out(" use 'xpoe read' to flush data.\n"); 772 poe_pd_pkt_dump(data, 15, "Rx from PD63000"); 773 return CMD_FAIL; 774 } 775 776 return CMD_OK; 777 } 778 779 #define PD63000_KEY_COMMAND 0x00 780 #define PD63000_KEY_PROGRAM 0x01 781 #define PD63000_KEY_REQUEST 0x02 782 #define PD63000_KEY_TELEMETRY 0x03 783 #define PD63000_KEY_REPORT 0x52 784 #define PD63000_NULL_DATA 0x4e 785 #define PD63000_SUB_GLOBAL 0x07 786 #define PD63000_SUB_SW 0x21 787 #define PD63000_SUB_VERZ 0x1e 788 #define PD63000_SUB_STATUS 0x3d 789 #define PD63000_SUB_SUPPLY 0x0b 790 #define PD63000_SUB_SUPPLY1 0x15 791 #define PD63000_SUB_MAIN 0x17 792 #define PD63000_SUB_CHANNEL 0x05 793 #define PD63000_SUB_PARAMZ 0x25 794 #define PD63000_SUB_PORTSTATUS 0x0e 795 796 /* 797 * Function: cmd_xpoe 798 * Purpose: Communication with PowerDsine PD63000 799 * 8-bit PoE Microcontroller Unit 800 */ 801 char cmd_xpoe_usage[] = 802 "Usages:\n\t" 803 #ifdef COMPILER_STRING_CONST_LIMIT 804 " xpoe ver | status | power | port | measure | raw | read | debug\n" 805 #else 806 " xpoe ver\n\t" 807 " - Get PD63000 software version.\n\t" 808 " xpoe status\n\t" 809 " - Get System Status.\n\t" 810 " xpoe power <value>\n\t" 811 " - Get/Set power supply parameters.\n\t" 812 " xpoe power status\n\t" 813 " - Get main power source supply parameters.\n\t" 814 " xpoe port <port_num>\n\t" 815 " - Get port status (use * for all ports).\n\t" 816 " xpoe measure <port_num>\n\t" 817 " - Get port measurements (use * for all ports).\n\t" 818 " xpoe raw <byte0> ... <byte14> \n\t" 819 " - Send raw data to PD63000.\n\t" 820 " xpoe read\n\t" 821 " - Read one packet from PD63000.\n\t" 822 " xpoe debug on/off\n\t" 823 " - Turn packet dump to/from PD63000 on/off.\n\t" 824 " xpoe verbose on/off\n\t" 825 " - Turn on/off verbose output (default is on).\n" 826 #endif 827 ; 828 829 cmd_result_t 830 cmd_xpoe(int unit, args_t *a) 831 { 832 char *subcmd, *s; 833 int port, i, fd, rv, no_cksum=0; 834 uint8 data[15], echo; 835 uint32 len; 836 uint16 val; 837 static uint8 seq=0; 838 static int debug=0; 839 static int verbose=1; 840 841 if (!sh_check_attached(ARG_CMD(a), unit)) { 842 return CMD_FAIL; 843 } 844 845 if ((subcmd = ARG_GET(a)) == NULL) { 846 return CMD_USAGE; 847 } 848 849 if ( (fd = bcm_i2c_open(unit, I2C_POE_0, 0,0)) < 0) { 850 cli_out("%s: cannot open I2C device %s: %s\n", 851 ARG_CMD(a), I2C_POE_0, bcm_errmsg(fd)); 852 return CMD_FAIL; 853 } 854 855 if (sal_strcasecmp(subcmd, "verbose") == 0) { 856 if ((subcmd = ARG_GET(a)) == NULL) { 857 return CMD_USAGE; 858 } 859 if (sal_strcasecmp(subcmd, "on") == 0) { 860 verbose = 1; 861 } else { 862 verbose = 0; 863 } 864 return CMD_OK; 865 } 866 867 if (sal_strcasecmp(subcmd, "debug") == 0) { 868 if ((subcmd = ARG_GET(a)) == NULL) { 869 return CMD_USAGE; 870 } 871 if (sal_strcasecmp(subcmd, "on") == 0) { 872 debug = 1; 873 } else { 874 debug = 0; 875 } 876 return CMD_OK; 877 } 878 879 memset(data, 0x0, 15); 880 881 if (sal_strcasecmp(subcmd, "ver") == 0) { 882 memset(data, PD63000_NULL_DATA, 15); 883 data[0] = PD63000_KEY_REQUEST; 884 data[1] = seq; 885 data[2] = PD63000_SUB_GLOBAL; 886 data[3] = PD63000_SUB_VERZ; 887 data[4] = PD63000_SUB_SW; 888 poe_pd_pkt_cksum(data); 889 890 if ((rv = poe_pd_pkt_txrx(unit, fd, data, seq, debug)) < 0) { 891 return rv; 892 } 893 894 if (data[0] == PD63000_KEY_TELEMETRY) { 895 if (verbose) { 896 cli_out("H.W. Version %d (0x%x)\n", data[2], data[2]); 897 cli_out("S.W. Version %d (0x%x)\n", ((data[5]<<8)|data[6]), 898 ((data[5]<<8)|data[6])); 899 } 900 } 901 seq++; 902 return CMD_OK; 903 } 904 905 if (sal_strcasecmp(subcmd, "status") == 0) { 906 memset(data, PD63000_NULL_DATA, 15); 907 data[0] = PD63000_KEY_REQUEST; 908 data[1] = seq; 909 data[2] = PD63000_SUB_GLOBAL; 910 data[3] = PD63000_SUB_STATUS; 911 poe_pd_pkt_cksum(data); 912 913 if ((rv = poe_pd_pkt_txrx(unit, fd, data, seq, debug)) < 0) { 914 return rv; 915 } 916 917 if (data[0] == PD63000_KEY_TELEMETRY) { 918 cli_out("%s%s",(data[2] & 0x1) ? "CPU error; " : "" 919 ,(data[2] & 0x2) ? "Programming required; " : ""); 920 cli_out("%s%s",(data[3] & 0x1) ? "EEPROM error; " : "" 921 ,((data[3] & 0x2) && (data[8] != 0xfe)) ? "ASIC error; " : ""); 922 cli_out("%s",(data[4] & 0x1) ? "Factory default set; " : ""); 923 cli_out("%s",(data[5] != 0) ? "Internal error; " : ""); 924 if ((data[2]|data[3]|data[4]|data[5]) && (data[8] != 0xfe)) { 925 926 cli_out("\n"); 927 cli_out("ASIC fail = 0x%x\n",data[8]); 928 } else { 929 if (verbose) 930 cli_out("No system status error.\n"); 931 } 932 if (verbose) { 933 cli_out("General use = %d\n",data[6]); 934 cli_out("User byte = 0x%x\n",data[7]); 935 } 936 } 937 seq++; 938 return CMD_OK; 939 } 940 941 if (sal_strcasecmp(subcmd, "power") == 0) { 942 if ((s = ARG_GET(a)) == NULL) { 943 memset(data, PD63000_NULL_DATA, 15); 944 data[0] = PD63000_KEY_REQUEST; 945 data[1] = seq; 946 data[2] = PD63000_SUB_GLOBAL; 947 data[3] = PD63000_SUB_SUPPLY; 948 data[4] = PD63000_SUB_SUPPLY1; 949 poe_pd_pkt_cksum(data); 950 951 if ((rv = poe_pd_pkt_txrx(unit, fd, data, seq, debug)) < 0) { 952 return rv; 953 } 954 955 if (data[0] == PD63000_KEY_TELEMETRY) { 956 if (verbose) { 957 cli_out("Power permitted %d W\n", (data[2]<<8)|data[3]); 958 cli_out("Max Voltage %4d.%01d V\n", 959 INT_FRAC_1PT((data[4]<<8)|data[5])); 960 cli_out("Min Voltage %4d.%01d V\n", 961 INT_FRAC_1PT((data[6]<<8)|data[7])); 962 } 963 } 964 seq++; 965 } else { 966 if (sal_strcasecmp(s, "status") == 0) { 967 memset(data, PD63000_NULL_DATA, 15); 968 data[0] = PD63000_KEY_REQUEST; 969 data[1] = seq; 970 data[2] = PD63000_SUB_GLOBAL; 971 data[3] = PD63000_SUB_SUPPLY; 972 data[4] = PD63000_SUB_MAIN; 973 poe_pd_pkt_cksum(data); 974 975 if ((rv = poe_pd_pkt_txrx(unit, fd, data, seq, debug)) < 0) { 976 return rv; 977 } 978 979 if (data[0] == PD63000_KEY_TELEMETRY) { 980 if (verbose) { 981 cli_out("Power Consumption %d W\n", (data[2]<<8)|data[3]); 982 cli_out("Max Shutdown Voltage %4d.%01d V\n", 983 INT_FRAC_1PT((data[4]<<8)|data[5])); 984 cli_out("Min Shutdown Voltage %4d.%01d V\n", 985 INT_FRAC_1PT((data[6]<<8)|data[7])); 986 cli_out("Internal Power Loss %d W\n", data[8]); 987 cli_out("Power Source %s\n",(data[9] ? "PS1" : "PS2")); 988 } 989 } 990 seq++; 991 } else { 992 int i2c_poe_power; 993 i2c_poe_power = soc_property_get(unit, spn_I2C_POE_POWER, 0); 994 /* set power source 1 */ 995 memset(data, PD63000_NULL_DATA, 15); 996 data[0] = PD63000_KEY_COMMAND; 997 data[1] = seq; 998 data[2] = PD63000_SUB_GLOBAL; 999 data[3] = PD63000_SUB_SUPPLY; 1000 data[4] = PD63000_SUB_SUPPLY1; 1001 if (i2c_poe_power) { 1002 data[7] = 0x2; 1003 data[8] = 0x39; 1004 data[9] = 0x1; 1005 data[10] = 0xb7; 1006 data[11] = 0x13; 1007 } else { 1008 data[7] = 0x2; 1009 data[8] = 0x49; 1010 data[9] = 0x1; 1011 data[10] = 0xb8; 1012 data[11] = 0x1; 1013 } 1014 val = parse_integer(s); 1015 data[5] = val>>8; 1016 data[6] = val&0xff; 1017 poe_pd_pkt_cksum(data); 1018 1019 if ((rv = poe_pd_pkt_txrx(unit, fd, data, seq, debug)) < 0) { 1020 return rv; 1021 } 1022 1023 if (data[0] == PD63000_KEY_REPORT) { 1024 val = (data[2] << 8) | data[3]; 1025 if (val) { 1026 cli_out("Return error 0x%x\n", val); 1027 if ((val > 0) && (val <= 0x7fff)) { 1028 cli_out("\tFailed execution (conflict in subject bytes).\n"); 1029 } 1030 if ((val > 0x8000) && (val <= 0x8fff)) { 1031 cli_out("\tFailed execution (wrong data byte value).\n"); 1032 } 1033 if (val == 0xffff) { 1034 cli_out("\tFailed execution (undefined key value).\n"); 1035 } 1036 } else { 1037 if (verbose) 1038 cli_out("Command received and correctly executed.\n"); 1039 } 1040 } 1041 seq++; 1042 } 1043 } 1044 return CMD_OK; 1045 } 1046 1047 if (sal_strcasecmp(subcmd, "port") == 0) { 1048 if ((s = ARG_GET(a)) != NULL) { 1049 if (sal_strcasecmp(s, "*") == 0) { 1050 port = 24; 1051 } else { 1052 port = 1; 1053 } 1054 1055 for (i = 0; i < port; i++) { 1056 memset(data, PD63000_NULL_DATA, 15); 1057 data[0] = PD63000_KEY_REQUEST; 1058 data[1] = seq; 1059 data[2] = PD63000_SUB_CHANNEL; 1060 data[3] = PD63000_SUB_PORTSTATUS; 1061 if (port == 1) 1062 data[4] = parse_integer(s); 1063 else 1064 data[4] = i; 1065 if (data[4] > 24) { 1066 cli_out("Channel number: 0 ~ 23.\n"); 1067 return CMD_FAIL; 1068 } 1069 poe_pd_pkt_cksum(data); 1070 1071 if ((rv = poe_pd_pkt_txrx(unit, fd, data, seq, debug)) < 0) { 1072 return rv; 1073 } 1074 1075 if (data[0] == PD63000_KEY_TELEMETRY) { 1076 if (port != 1 && verbose) 1077 cli_out("Port %d:\n", i); 1078 if (verbose) 1079 cli_out("Port %s\n", (data[2] ? "enable" : "disable")); 1080 s = poe_pd_decode_port_status(data[3]); 1081 if (verbose) { 1082 cli_out("Actual port status %s\n",s); 1083 cli_out("Port in %s\n",(data[4] ? "test mode" : "auto mode")); 1084 cli_out("Latch 0x%x\n",data[5]); 1085 cli_out("Class %d\n",data[6]); 1086 } 1087 } 1088 seq++; 1089 } 1090 } else { 1091 return CMD_USAGE; 1092 } 1093 return CMD_OK; 1094 } 1095 1096 if (sal_strcasecmp(subcmd, "measure") == 0) { 1097 if ((s = ARG_GET(a)) != NULL) { 1098 if (sal_strcasecmp(s, "*") == 0) { 1099 port = 24; 1100 } else { 1101 port = 1; 1102 } 1103 1104 for (i = 0; i < port; i++) { 1105 memset(data, PD63000_NULL_DATA, 15); 1106 data[0] = PD63000_KEY_REQUEST; 1107 data[1] = seq; 1108 data[2] = PD63000_SUB_CHANNEL; 1109 data[3] = PD63000_SUB_PARAMZ; 1110 if (port == 1) 1111 data[4] = parse_integer(s); 1112 else 1113 data[4] = i; 1114 if (data[4] > 24) { 1115 cli_out("Channel number: 0 ~ 23.\n"); 1116 return CMD_FAIL; 1117 } 1118 poe_pd_pkt_cksum(data); 1119 1120 if ((rv = poe_pd_pkt_txrx(unit, fd, data, seq, debug)) < 0) { 1121 return rv; 1122 } 1123 1124 if (data[0] == PD63000_KEY_TELEMETRY) { 1125 if (port != 1 && verbose) 1126 cli_out("Port %d:\n", i); 1127 if (verbose) { 1128 cli_out("Voltage = %4d.%01d V\t", 1129 INT_FRAC_1PT((data[2]<<8)|data[3])); 1130 cli_out("Current = %d mA\t\t", (data[4]<<8)|data[5]); 1131 cli_out("Power = %4d.%03d W\n", 1132 INT_FRAC_3PT((data[6]<<8)|data[7])); 1133 } 1134 } 1135 seq++; 1136 } 1137 } else { 1138 return CMD_USAGE; 1139 } 1140 return CMD_OK; 1141 } 1142 1143 if (sal_strcasecmp(subcmd, "raw") == 0) { 1144 for (i = 0; i < 15; i++) { 1145 if ((s = ARG_GET(a)) == NULL) { 1146 if (i == 13) { 1147 no_cksum = 1; 1148 break; 1149 } else { 1150 cli_out("Not enough data values (have %d, " 1151 "need 15 or 13 (for auto check-sum))\n", i); 1152 return CMD_FAIL; 1153 } 1154 } 1155 data[i] = parse_integer(s); 1156 } 1157 1158 if (no_cksum) { 1159 poe_pd_pkt_cksum(data); 1160 } 1161 1162 echo = data[1]; 1163 if ((rv = poe_pd_pkt_txrx(unit, fd, data, echo, 1)) < 0) { 1164 return rv; 1165 } 1166 1167 return CMD_OK; 1168 } 1169 1170 if (sal_strcasecmp(subcmd, "read") == 0) { 1171 if ((rv = bcm_i2c_read(unit, fd, 0, data, &len)) < 0){ 1172 cli_out("ERROR: read byte failed: %s\n", 1173 bcm_errmsg(rv)); 1174 return CMD_FAIL; 1175 } 1176 poe_pd_pkt_dump(data, 15, "Rx from PD63000"); 1177 return CMD_OK; 1178 } 1179 1180 return CMD_USAGE; 1181 } /* end cmd_xpoe() */ 1182 1183 /* 1184 * Pretty-print a byte in binary format. 1185 */ 1186 char * 1187 get_bits(uint8 byte) 1188 { 1189 static char buf[12]; 1190 int i; 1191 int cat_len; 1192 memset(buf,0x0,12); 1193 cat_len = 2; 1194 strncat(buf,"0b",cat_len); 1195 cat_len = 1; 1196 for(i = 7; i >= 0;i--){ 1197 if( byte & (1 << i)){ 1198 cli_out("bit %d set\n",i); 1199 strncat(buf,"1",cat_len); 1200 } 1201 else 1202 strncat(buf,"0",cat_len); 1203 } 1204 return buf; 1205 } 1206 1207 #if defined(SHADOW_SVK) 1208 #define I2C_MUX_F_OPEN (1 << 0) 1209 #define I2C_MUX_F_MAP (1 << 1) /* MUX must be mapped to bit */ 1210 /* corresponding to channel */ 1211 1212 STATIC struct mux_ctrl { 1213 const char *mux_name; 1214 uint32 flags; 1215 } i2c_mux_info; 1216 1217 STATIC 1218 int _i2c_mux_info_set(int unit, const char *name, uint32 flags) 1219 { 1220 i2c_mux_info.mux_name = name; 1221 i2c_mux_info.flags |= flags; 1222 return 0; 1223 } 1224 1225 STATIC 1226 int _i2c_mux_info_get(int unit, const char **name, uint32 *flags) 1227 { 1228 int rv = 0; 1229 1230 if (i2c_mux_info.flags & I2C_MUX_F_OPEN) { 1231 *name = i2c_mux_info.mux_name; 1232 *flags = i2c_mux_info.flags; 1233 } else { 1234 rv = -1; 1235 } 1236 return rv; 1237 } 1238 1239 /* 1240 * On most boards, there is a single MUX accessed with I2C_LPT_0 1241 * (PCF8574, address 0x20). However, some boards can have multiple MUXes 1242 * implemented with PCA9548 parts. The Shadow SVKs have 1243 * two MUXes: I2C_MUX_6, address 0x76, and I2C_MUX_7, address 0x77. 1244 * This function should be called by all code that programs 1245 * the MUX to access devices behind the MUX, instead of assuming 1246 * I2C_LPT_0 is always the MUX. 1247 * 1248 * Upon success, this function returns the descriptor for the mux 1249 * and the MUX name 1250 */ 1251 1252 int _i2c_mux_open(int unit, uint32 flags, int speed, 1253 char *name) 1254 { 1255 int fd = -1; 1256 1257 fd = bcm_i2c_open(unit, name, flags, speed); 1258 if (fd >= 0) { 1259 if (sal_strncmp(name, "mux", 3)==0) { 1260 _i2c_mux_info_set(unit, name, I2C_MUX_F_OPEN|I2C_MUX_F_MAP); 1261 } else { 1262 _i2c_mux_info_set(unit, name, I2C_MUX_F_OPEN); 1263 } 1264 } 1265 return fd; 1266 } 1267 1268 1269 uint8 _i2c_mux_channel_get(int unit, int mux) 1270 { 1271 int rv; 1272 const char *name; 1273 uint8 channel; 1274 uint32 flags; 1275 1276 channel = mux; 1277 rv = _i2c_mux_info_get(unit, &name, &flags); 1278 if (rv == 0) { 1279 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1280 (BSL_META_U(unit, 1281 "name = %s flags %x\n"), name, flags)); 1282 if (flags & I2C_MUX_F_MAP) { 1283 channel = (1 << mux); 1284 } 1285 } 1286 1287 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1288 (BSL_META_U(unit, 1289 "mux %d -> channel %d\n"), mux, channel)); 1290 return channel; 1291 } 1292 1293 1294 #endif /* SHADOW_SVK */ 1295 1296 /* 1297 * Use lpt0 (PCF8574 Parallel port) to select a MUX line 1298 * for multi-clock and multi-dac boards. Some boards have 1299 * multiple devices at the same slave address, the lpt0 outputs 1300 * will function in this case as a chip-select. 1301 */ 1302 char cmd_muxsel_usage[] = 1303 "Usages:\n\t" 1304 " muxsel <mux_device> [<channel>]\n\t" 1305 " - show muxsel, if channel specified, enable that channel.\n\t" 1306 " - mux_device = lpt0, mux0, mux1\n\t" 1307 "\n"; 1308 1309 cmd_result_t 1310 cmd_muxsel(int unit, args_t *a) 1311 { 1312 char *dataByte; 1313 int fd, rv = SOC_E_NONE; 1314 uint32 len; 1315 uint8 lptVal; 1316 char * dev_name; 1317 1318 dev_name = ARG_GET(a); 1319 dataByte = ARG_GET(a); 1320 if (! sh_check_attached(ARG_CMD(a), unit)) 1321 return CMD_FAIL; 1322 1323 #ifdef SHADOW_SVK 1324 if ((dev_name == NULL) || (sal_strncmp(dev_name, "mux6", 4) != 0) || 1325 (sal_strncmp(dev_name, "mux7", 4) != 0)) { 1326 cli_out("Valid devices are mux6, mux7 \n"); 1327 return CMD_FAIL; 1328 } 1329 1330 if ( (fd = _i2c_mux_open(unit, 0, 0, dev_name)) < 0) { 1331 cli_out("%s: cannot open I2C device %s: %s\n", 1332 ARG_CMD(a), dev_name, bcm_errmsg(fd)); 1333 return CMD_FAIL; 1334 } 1335 #else 1336 if (dev_name == NULL) { 1337 dev_name = _i2c_mux_default_dev_name_get(); 1338 } 1339 if ( (fd = bcm_i2c_open(unit, dev_name, 0,0)) < 0) { 1340 cli_out("%s: cannot open I2C device %s: %s\n", 1341 ARG_CMD(a), dev_name, bcm_errmsg(fd)); 1342 return CMD_FAIL; 1343 } 1344 1345 #endif 1346 if (! dataByte ){ 1347 /* Show LPT bits */ 1348 if( (rv = bcm_i2c_read(unit, fd, 0, &lptVal, &len)) < 0){ 1349 cli_out("ERROR: read byte failed: %s\n", 1350 bcm_errmsg(rv)); 1351 return CMD_FAIL; 1352 } 1353 cli_out("Read I2C MuxSel = 0x%x (%s)\n", lptVal, get_bits(lptVal)); 1354 } else { 1355 /* Write LPT bits */ 1356 lptVal = (uint8)parse_integer(dataByte); 1357 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 1358 cli_out("ERROR: write byte failed: %s\n", 1359 bcm_errmsg(rv)); 1360 return CMD_FAIL; 1361 } 1362 cli_out("Write I2C MuxSel = 0x%x (%s)\n", lptVal, get_bits(lptVal)); 1363 } 1364 return CMD_OK ; 1365 } 1366 1367 /* 1368 * Use lpt2 (PCF8574 Parallel port) to select a MUX line 1369 * for multi-clock. 1370 */ 1371 char cmd_hclksel_usage[] = 1372 "Usages:\n\t" 1373 " hclksel [value]\n\t" 1374 " - show hclksel, if value specified, set to that value.\n\t" 1375 "\n"; 1376 1377 cmd_result_t 1378 cmd_hclksel(int unit, args_t *a) 1379 { 1380 char *dataByte = ARG_GET(a); 1381 int fd, rv = SOC_E_NONE; 1382 uint32 len; 1383 uint8 lptVal; 1384 1385 if (! sh_check_attached(ARG_CMD(a), unit)) 1386 return CMD_FAIL; 1387 1388 if ( (fd = bcm_i2c_open(unit, I2C_LPT_2, 0,0)) < 0) { 1389 cli_out("%s: cannot open I2C device %s: %s\n", 1390 ARG_CMD(a), I2C_LPT_2, bcm_errmsg(fd)); 1391 return CMD_FAIL; 1392 } 1393 1394 if (! dataByte ){ 1395 /* Show LPT bits */ 1396 if( (rv = bcm_i2c_read(unit, fd, 0, &lptVal, &len)) < 0){ 1397 cli_out("ERROR: read byte failed: %s\n", 1398 bcm_errmsg(rv)); 1399 return CMD_FAIL; 1400 } 1401 cli_out("Read I2C HClkSel = 0x%x (%s)\n", lptVal, get_bits(lptVal)); 1402 } else { 1403 /* Write LPT bits */ 1404 lptVal = (uint8)parse_integer(dataByte); 1405 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 1406 cli_out("ERROR: write byte failed: %s\n", 1407 bcm_errmsg(rv)); 1408 return CMD_FAIL; 1409 } 1410 cli_out("Write I2C HClkSel = 0x%x (%s)\n", lptVal, get_bits(lptVal)); 1411 } 1412 return CMD_OK ; 1413 } 1414 1415 /* 1416 * Use lpt3 (PCF8574 Parallel port) for PoE I2C expander. 1417 */ 1418 char cmd_poesel_usage[] = 1419 "Usages:\n\t" 1420 " poesel enable\n\t" 1421 " - Enable POE controller.\n\t" 1422 " poesel disble\n\t" 1423 " - Disable POE controller.\n\t" 1424 " poesel reset\n\t" 1425 " - Reset POE controller.\n\t" 1426 " poesel [value] \n\t" 1427 " - show poesel, if value specified, set to that value.\n\t" 1428 "\n"; 1429 1430 cmd_result_t 1431 cmd_poesel(int unit, args_t *a) 1432 { 1433 char *subcmd; 1434 int subcmd_s = 0; 1435 int fd, rv = SOC_E_NONE; 1436 uint32 len; 1437 uint8 lptVal; 1438 #define I2C_POE_ENABLE 1 1439 #define I2C_POE_DISABLE 2 1440 #define I2C_POE_RESET 3 1441 1442 if (! sh_check_attached(ARG_CMD(a), unit)) 1443 return CMD_FAIL; 1444 1445 if ( (fd = bcm_i2c_open(unit, I2C_LPT_3, 0,0)) < 0) { 1446 cli_out("%s: cannot open I2C device %s: %s\n", 1447 ARG_CMD(a), I2C_LPT_3, bcm_errmsg(fd)); 1448 return CMD_FAIL; 1449 } 1450 1451 if ((subcmd = ARG_GET(a)) == NULL) { 1452 if( (rv = bcm_i2c_read(unit, fd, 0, &lptVal, &len)) < 0){ 1453 cli_out("ERROR: read byte failed: %s\n", 1454 bcm_errmsg(rv)); 1455 return CMD_FAIL; 1456 } 1457 cli_out("Read I2C PoeSel = 0x%x (%s)\n", lptVal, get_bits(lptVal)); 1458 return CMD_OK ; 1459 } 1460 1461 if (sal_strcasecmp(subcmd, "enable") == 0) { 1462 subcmd_s = I2C_POE_ENABLE; 1463 lptVal = 0x8c; 1464 } else if (sal_strcasecmp(subcmd, "disable") == 0) { 1465 subcmd_s = I2C_POE_DISABLE; 1466 lptVal = 0x8e; 1467 } else if (sal_strcasecmp(subcmd, "reset") == 0) { 1468 subcmd_s = I2C_POE_RESET; 1469 lptVal = 0x8d; 1470 } else { 1471 lptVal = (uint8)parse_integer(subcmd); 1472 } 1473 1474 if ((rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 1475 cli_out("ERROR: write byte failed: %s\n", 1476 bcm_errmsg(rv)); 1477 return CMD_FAIL; 1478 } 1479 1480 if (subcmd_s == I2C_POE_RESET) { 1481 sal_sleep(5); 1482 } 1483 1484 if (subcmd_s == 0) { 1485 cli_out("Write I2C PoeSel = 0x%x (%s)\n", lptVal, get_bits(lptVal)); 1486 } 1487 1488 return CMD_OK ; 1489 } 1490 1491 1492 1493 #ifdef BCM_ESW_SUPPORT 1494 #define SYN_DELAY 200000 1495 /* 1496 * Use lpt4 and lpt5 (PCF8574 Parallel port) to select a 1497 * synthesizer frequency. 1498 */ 1499 char cmd_synth_usage[] = 1500 "\n\t" 1501 "synth [value]\n\t" 1502 " - show synth freq, if value specified, set frequency.\n\t" 1503 "\n"; 1504 1505 cmd_result_t 1506 cmd_synth(int unit, args_t *a) 1507 { 1508 #ifdef COMPILER_HAS_DOUBLE 1509 char *value = ARG_GET(a); 1510 char *syndbg = ARG_GET(a); 1511 double cur_freq, freq, m_div, n_div; 1512 double n_div_map[8] = { 1, 1.5, 2, 3, 4, 6, 8, 12 }; 1513 double freq_min[8] = { 250.0, 166.7, 125.0, 83.3, 62.5, 41.7, 31.3, 20.8 }; 1514 double freq_max[8] = { 500.0, 333.3, 250.0, 166.7, 125.0, 83.3, 62.5, 41.7 }; 1515 int adj[8] = { 9, 6, 3, 3, 2, 1, 1, 1 }; 1516 int rv, sel1, sel2, m, n, cur_n, inc; 1517 uint8 lptVal; 1518 uint32 reg, len; 1519 char *str; 1520 1521 if (!sh_check_attached(ARG_CMD(a), unit)) 1522 return CMD_FAIL; 1523 1524 if ((sel1 = bcm_i2c_open(unit, I2C_LPT_4, 0,0)) < 0) { 1525 cli_out("%s: cannot open I2C device %s: %s\n", 1526 ARG_CMD(a), I2C_LPT_4, bcm_errmsg(sel1)); 1527 return CMD_FAIL; 1528 } 1529 1530 if ((sel2 = bcm_i2c_open(unit, I2C_LPT_5, 0,0)) < 0) { 1531 cli_out("%s: cannot open I2C device %s: %s\n", 1532 ARG_CMD(a), I2C_LPT_5, bcm_errmsg(sel2)); 1533 return CMD_FAIL; 1534 } 1535 1536 /* Read current frequency */ 1537 if ((rv = bcm_i2c_read(unit, sel1, 0, &lptVal, &len)) < 0) { 1538 cli_out("ERROR: read byte failed: %s\n", 1539 bcm_errmsg(rv)); 1540 return CMD_FAIL; 1541 } 1542 m = lptVal; 1543 if ((rv = bcm_i2c_read(unit, sel2, 0, &lptVal, &len)) < 0) { 1544 cli_out("ERROR: read byte failed: %s\n", 1545 bcm_errmsg(rv)); 1546 return CMD_FAIL; 1547 } 1548 if (lptVal & 0x80) m |= 0x100; 1549 n = lptVal & 0x7; 1550 m_div = m; 1551 n_div = n_div_map[n]; 1552 cur_freq = m_div / n_div; 1553 1554 if (!value) { 1555 /* Show frequency */ 1556 freq = cur_freq; 1557 str = ""; 1558 } else { 1559 /* Set frequency */ 1560 freq = atof(value); 1561 if (freq > freq_max[0] || freq < freq_min[7]) { 1562 cli_out("%s: valid frequency range: %.1f MHz to %.1f MHz\n", 1563 ARG_CMD(a), freq_min[7], freq_max[0]); 1564 return CMD_FAIL; 1565 } 1566 1567 if (syndbg) { 1568 cli_out("Change from %.1f MHz to %.1f MHz\n", 1569 cur_freq, freq); 1570 } 1571 1572 /* 1573 * Since the I2C clock is derived from the core clock and the 1574 * I2C access only works within a certain frequency range, we 1575 * need to take precautions when changing the core clock in 1576 * order not to lock ourselves out from the I2C bus. This 1577 * means that for large changes in core clock frequency we 1578 * will have to change the core clock in smaller steps and 1579 * adjust the CMIC divider in between the steps. 1580 */ 1581 for (cur_n = 0; cur_n < 8; cur_n++) { 1582 if (cur_freq >= freq_min[cur_n]) { 1583 break; 1584 } 1585 } 1586 for (n = 0; n < 8; n++) { 1587 if (freq >= freq_min[n]) { 1588 break; 1589 } 1590 } 1591 1592 if (cur_n >= 8 || n >= 8) { 1593 /* should never get here */ 1594 cli_out("ERROR: internal error\n"); 1595 return CMD_FAIL; 1596 } 1597 1598 inc = cur_n > n ? -1 : 1; 1599 do { 1600 if (n == cur_n) { 1601 cur_freq = freq; 1602 inc = 0; 1603 } else { 1604 if((cur_n+inc) < 0 || (cur_n+inc) > 7) { 1605 cli_out("ERROR: Internal error\n"); 1606 return CMD_FAIL; 1607 /* coverity[overrun-local : FALSE] */ 1608 } else { 1609 /* coverity[overrun-local] */ 1610 cur_freq = (inc < 0) ? freq_min[cur_n+inc] : freq_max[cur_n+inc]; 1611 } 1612 } 1613 if (syndbg) { 1614 cli_out("Adjust to %.1f/%d\n", 1615 cur_freq, adj[cur_n+inc]); 1616 } 1617 n_div = n_div_map[cur_n+inc]; 1618 m = cur_freq * n_div; 1619 lptVal = (uint8)(m & 0xff); 1620 if ((rv = bcm_i2c_write(unit, sel1, 0, &lptVal, 1)) < 0) { 1621 cli_out("ERROR: write byte failed: %s\n", 1622 bcm_errmsg(rv)); 1623 return CMD_FAIL; 1624 } 1625 sal_usleep(SYN_DELAY); 1626 lptVal = (uint8)cur_n; 1627 if (m & 0x100) lptVal |= 0x80; 1628 if ((rv = bcm_i2c_write(unit, sel2, 0, &lptVal, 1)) < 0) { 1629 cli_out("ERROR: write byte failed: %s\n", 1630 bcm_errmsg(rv)); 1631 return CMD_FAIL; 1632 } 1633 sal_usleep(SYN_DELAY); 1634 READ_CMIC_RATE_ADJUSTr(unit, ®); 1635 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, ®, 1636 DIVISORf, adj[cur_n]); 1637 WRITE_CMIC_RATE_ADJUSTr(unit, reg); 1638 sal_usleep(SYN_DELAY); 1639 if (n == cur_n) { 1640 break; 1641 } 1642 cur_n = cur_n + inc; 1643 if (cur_n < 0 || cur_n > 7) { 1644 cli_out("ERROR: Internal error\n"); 1645 return CMD_FAIL; 1646 } 1647 } while (1); 1648 /* Dummy read */ 1649 if ((rv = bcm_i2c_read(unit, sel1, 0, &lptVal, &len)) < 0) { 1650 cli_out("ERROR: dummy read byte failed: %s\n", 1651 bcm_errmsg(rv)); 1652 return CMD_FAIL; 1653 } 1654 str = "Write I2C "; 1655 } 1656 cli_out("%sSynth Freq = %.1f MHz", str, freq); 1657 cli_out(" [ 0%c%c%c%c%c%c%c%c%c 0%c%c%c ]\n", 1658 m & 0x100 ? '1' : '0', 1659 m & 0x080 ? '1' : '0', 1660 m & 0x040 ? '1' : '0', 1661 m & 0x020 ? '1' : '0', 1662 m & 0x010 ? '1' : '0', 1663 m & 0x008 ? '1' : '0', 1664 m & 0x004 ? '1' : '0', 1665 m & 0x002 ? '1' : '0', 1666 m & 0x001 ? '1' : '0', 1667 n & 0x4 ? '1' : '0', 1668 n & 0x2 ? '1' : '0', 1669 n & 0x1 ? '1' : '0'); 1670 #endif 1671 1672 return CMD_OK ; 1673 } 1674 1675 /* 1676 * Use lpt6 (PCF8574 Parallel port) to set PPD clock delay. 1677 */ 1678 char cmd_ppdclk_usage[] = 1679 "\n\t" 1680 "ppdclk\n\t" 1681 " - show PPD clock delay and core clock divider\n\t" 1682 "ppdclk delay value\n\t" 1683 " - set PPD clock delay in ps (0-1270)\n\t" 1684 "ppdclk div value\n\t" 1685 " - set core clock divider enable (0 or 1)\n\t" 1686 "\n"; 1687 1688 cmd_result_t 1689 cmd_ppdclk(int unit, args_t *a) 1690 { 1691 char *source = ARG_GET(a); 1692 char *value = ARG_GET(a); 1693 int fd, fd2, rv = SOC_E_NONE; 1694 uint32 len, ppd_delay; 1695 uint8 lptVal, lptVal2; 1696 1697 if (! sh_check_attached(ARG_CMD(a), unit)) 1698 return CMD_FAIL; 1699 1700 if ((fd = bcm_i2c_open(unit, I2C_LPT_6, 0,0)) < 0) { 1701 cli_out("%s: cannot open I2C device %s: %s\n", 1702 ARG_CMD(a), I2C_LPT_6, bcm_errmsg(fd)); 1703 return CMD_FAIL; 1704 } 1705 1706 if( (rv = bcm_i2c_read(unit, fd, 0, &lptVal, &len)) < 0){ 1707 cli_out("ERROR: read byte failed: %s\n", 1708 bcm_errmsg(rv)); 1709 return CMD_FAIL; 1710 } 1711 1712 if ((fd2 = bcm_i2c_open(unit, I2C_LPT_7, 0,0)) < 0) { 1713 cli_out("%s: cannot open I2C device %s: %s\n", 1714 ARG_CMD(a), I2C_LPT_6, bcm_errmsg(fd)); 1715 return CMD_FAIL; 1716 } 1717 1718 if( (rv = bcm_i2c_read(unit, fd2, 0, &lptVal2, &len)) < 0){ 1719 cli_out("ERROR: read byte failed: %s\n", 1720 bcm_errmsg(rv)); 1721 return CMD_FAIL; 1722 } 1723 1724 if (!source){ 1725 /* Show PPD clock delay and core clock divider */ 1726 ppd_delay = lptVal2 & 0x03; 1727 ppd_delay <<= 8; 1728 ppd_delay |= lptVal; 1729 cli_out("PPD Clock Delay = %d0 ps\n", ppd_delay); 1730 cli_out("Core Clock Divider = %sabled\n", 1731 lptVal2 & 0x80 ? "en" : "dis"); 1732 } else if (!sal_strcmp(source, "delay") && value) { 1733 /* Write PPD clock delay */ 1734 ppd_delay = parse_integer(value) / 10; 1735 lptVal = (uint8)(ppd_delay & 0xff); 1736 lptVal2 &= ~0x03; 1737 lptVal2 |= (uint8)(ppd_delay >> 8); 1738 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 1739 cli_out("ERROR: write byte failed: %s\n", 1740 bcm_errmsg(rv)); 1741 return CMD_FAIL; 1742 } 1743 if( (rv = bcm_i2c_write(unit, fd2, 0, &lptVal2, 1)) < 0){ 1744 cli_out("ERROR: write byte failed: %s\n", 1745 bcm_errmsg(rv)); 1746 return CMD_FAIL; 1747 } 1748 cli_out("Write I2C PPD Clock Delay = %d0 ps\n", ppd_delay); 1749 } else if (!sal_strcmp(source, "div") && value) { 1750 /* Enable/disable core clock divider */ 1751 lptVal &= ~0x80; 1752 if (parse_integer(value)) lptVal |= 0x80; 1753 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 1754 cli_out("ERROR: write byte failed: %s\n", 1755 bcm_errmsg(rv)); 1756 return CMD_FAIL; 1757 } 1758 cli_out("Write I2C Core Clock Divider = %sabled\n", 1759 lptVal & 0x80 ? "en" : "dis"); 1760 } else { 1761 return CMD_USAGE ; 1762 } 1763 return CMD_OK ; 1764 } 1765 #endif /* BCM_ESW_SUPPORT */ 1766 1767 /* 1768 * Configure a DAC chip. 1769 */ 1770 char cmd_dac_usage[] = 1771 "Usages:\n\t" 1772 " dac [chipnum] [value]\n\t" 1773 " - set DAC chip number to specified value.\n\t" 1774 "\n"; 1775 1776 cmd_result_t 1777 cmd_dac(int unit, args_t *a) 1778 { 1779 1780 1781 int fd, num, rv = SOC_E_NONE; 1782 uint16 dacVal; 1783 char dev[25]; 1784 char *chip = ARG_GET(a); 1785 char *dataWord = ARG_GET(a); 1786 1787 if (! sh_check_attached(ARG_CMD(a), unit)) 1788 return CMD_FAIL; 1789 1790 if ( (! dataWord) || (!chip) ) 1791 return CMD_USAGE ; 1792 1793 /* Select ADC chip number */ 1794 num = parse_integer(chip); 1795 /* coverity[secure_coding] */ 1796 sprintf(dev,"%s%d","dac",num); 1797 1798 dacVal = (uint16)parse_integer(dataWord); 1799 1800 if ( (fd = bcm_i2c_open(unit, dev, 0, 0)) < 0) { 1801 cli_out("%s: cannot open I2C device %s: %s\n", 1802 ARG_CMD(a), dev, bcm_errmsg(fd)); 1803 return CMD_FAIL; 1804 } 1805 /* Write command and data bytes to DAC */ 1806 if( (rv = bcm_i2c_write(unit, fd, 0, (uint8*)&dacVal, 2)) < 0){ 1807 cli_out("ERROR:write of DAC word failed:%s\n", 1808 bcm_errmsg(rv)); 1809 return CMD_FAIL; 1810 } 1811 1812 return CMD_OK ; 1813 } 1814 1815 1816 /* 1817 * Use Matrix Orbital LCD to display messages. 1818 */ 1819 char cmd_lcdmsg_usage[] = 1820 "Usages:\n\t" 1821 " lcdmsg [string]\n\t" 1822 " - print string on lcd\n\t" 1823 " lcdmsg -x [0-255]\n\t" 1824 " - set contrast (0-255)\n\t" 1825 " lcdmsg -c\n\t" 1826 " - clear screen\n\t" 1827 " lcdmsg -n\n\t" 1828 " - scroll down one line\n\t" 1829 "\n"; 1830 1831 cmd_result_t 1832 cmd_lcdmsg(int unit, args_t *a) 1833 { 1834 char *msg = ARG_GET(a); 1835 char *dat = ARG_GET(a); 1836 uint8 db; 1837 int fd, rv = SOC_E_NONE; 1838 1839 if( ! msg) 1840 return CMD_USAGE; 1841 1842 if (! sh_check_attached(ARG_CMD(a), unit)) 1843 return CMD_FAIL; 1844 1845 if ( (fd = bcm_i2c_open(unit, I2C_LCD_0, 0,0)) < 0) { 1846 cli_out("%s: cannot open I2C device %s: %s\n", 1847 ARG_CMD(a), I2C_LCD_0, bcm_errmsg(fd)); 1848 return CMD_FAIL; 1849 } 1850 /* Echo a newline */ 1851 if(!sal_strncasecmp(msg, "-n", 2)){ 1852 if( (rv = bcm_i2c_write(unit, fd, 0, (uint8 *)"\n",1)) < 0){ 1853 cli_out("ERROR: I2C write failed: %s\n", 1854 bcm_errmsg(rv)); 1855 return CMD_FAIL; 1856 } 1857 } 1858 /* Set contrast level */ 1859 else if(!sal_strncasecmp(msg,"-x",2)){ 1860 if(!dat) 1861 return CMD_USAGE; 1862 1863 db = (uint8) parse_integer(dat); 1864 1865 if( (rv = bcm_i2c_ioctl(unit, fd, I2C_LCD_CONTRAST, 1866 (void*)&db,1)) < 0){ 1867 cli_out("ERROR: I2C ioctl failed: %s\n", 1868 bcm_errmsg(rv)); 1869 return CMD_FAIL; 1870 } 1871 } 1872 /* Clear screen */ 1873 else if(!sal_strncasecmp(msg, "-c",2)){ 1874 if( (rv = bcm_i2c_ioctl(unit, fd, I2C_LCD_CLS, 0,0)) < 0){ 1875 cli_out("ERROR: I2C ioctl failed: %s\n", 1876 bcm_errmsg(rv)); 1877 return CMD_FAIL; 1878 } 1879 } 1880 else { 1881 /* Display text */ 1882 if( (rv = bcm_i2c_write(unit, fd, 0, (uint8 *)msg, sal_strlen(msg))) < 0){ 1883 cli_out("ERROR: I2C ioctl failed: %s\n", 1884 bcm_errmsg(rv)); 1885 return CMD_FAIL; 1886 } 1887 } 1888 return CMD_OK ; 1889 } 1890 1891 1892 /* 1893 * XGS/StrataSwitch board level support. 1894 * On Broadcom SDK Systems, the internal I2C controller is used to 1895 * determine board configuration and configurable options. 1896 * 1897 * Some boards have configurable options, other's don't and for 1898 * those which do, we provide additional support for the SDK 1899 * with the following tools: 1900 * 1901 * G1 - I2C NVRAM for SAL configuration, I2C Temperature monitoring, 1902 * W229n clock speed configuration (Core). 1903 * G2 - All of G1, plus configurable Core Voltage, and PCI, SDRAM amd 1904 * core clocks. 1905 * G3 - All of G1, pluse Turbo clock, Power, Temperature, and Thickness. 1906 * In addition, PHY and 2.5V power supplies configurable. 1907 * 1908 * See also: "baseboard" or "bb" command. 1909 */ 1910 /* 1911 * NOTE: To add new boards, edit board_type definition above 1912 * and be certain that this is used for indexing to work 1913 * (these tables commented as "INDEXED_BY_BOARD_TYPE"). 1914 */ 1915 1916 /* 1917 * Board identifiers. 1918 */ 1919 typedef enum{ 1920 G5, /* BCM5670 */ 1921 G13, /* BCM56504P24_00 */ 1922 G15, /* BCM56580K16 */ 1923 G16, /* BCM56800K20C */ 1924 G17, /* BCM56600K20 */ 1925 G18, /* BCM56218k48 */ 1926 G19, /* BCM56224k24 */ 1927 G20, /* BCM56624K49S, BCM56680K24TS, BCM56628K8XG, BCM56624K49DV */ 1928 G21, /* BCM56820K24XG, BCM56820K24C, BCM56820K24DV */ 1929 G22, /* BCM56524/BCM56685 */ 1930 G23, /* BCM88230 */ 1931 G24, /* BCM56840 */ 1932 G25, /* BCM56740 */ 1933 G26, /* BCM56142 */ 1934 G27, /* BCM88732 */ 1935 G28, /* BCM56440, BCM56150, BCM56340 */ 1936 G29, /* BCM56445K */ 1937 G30, /* BCM56444 */ 1938 G31, /* BCM56445D */ 1939 G33, /* BCM56844 */ 1940 G34, /* BCM56644K */ 1941 G35, /* BCM56640K */ 1942 G36, /* BCM988030K */ 1943 G37, /* BCM988030KC */ 1944 G38, /* BCM56850K */ 1945 G39, /* BCM56850D */ 1946 G40, /* BCM56450k, BCM56450d, BCM56456k, BCM56456d */ 1947 G41, /* BCM956062K, BCM956064K, BCM953411K, BCM953467K */ 1948 G42, /* BCM56960k */ 1949 G43, /* BCM56860 */ 1950 G44, /* BCM56860 100G */ 1951 G45, /* BCM953456K */ 1952 G46, /* BCM953416K, BCM956060K */ 1953 G47, /* BCM953406K */ 1954 G48, /* BCM56260, BCM56460 */ 1955 G49, /* BCM56960 PVT */ 1956 G50, /* BCM956560K, BCM956760K */ 1957 G51, /* BCM956565K */ 1958 G52, /* BCM56160K */ 1959 G53, /* BCM53444K */ 1960 G54, /* BCM53434K */ 1961 G55, /* BCM56160D */ 1962 G56, /* BCM56270K */ 1963 G57, /* BCM56970K */ 1964 G58, /* BCM53570K */ 1965 G59, /* BCM53570S */ 1966 G60, /* BCM56870K */ 1967 G61, /* BCM56670K */ 1968 G62, /* BCM53547K */ 1969 G63, /* BCM53549K */ 1970 G64, /* BCM56980K */ 1971 G65, /* BCM56370K */ 1972 ENG, /* Special */ 1973 UNK /* Unknown */ 1974 } board_type_t; 1975 1976 /* Board information structure */ 1977 1978 typedef struct 1979 bb_type_s{ 1980 int type; 1981 int bbcmd_flags; /* Supported baseboard commands */ 1982 char *name_text; 1983 } bb_type_t; 1984 1985 static char *BaseboardName = NULL; 1986 1987 /* Defines for bbcmd_flags field */ 1988 #define BB_NONE 0x00000000 1989 #define BB_CLK 0x00000001 1990 #define BB_VOLT 0x00000002 1991 #define BB_PWR 0x00000004 1992 #define BB_CURR 0x00000008 1993 #define BB_SEQ 0x00000010 1994 #define BB_REGULATOR 0x00000020 1995 1996 /* Currently supported platforms 1997 * INDEXED_BY_BOARD_TYPE */ 1998 1999 bb_type_t 2000 baseboards[] = { 2001 { G5, BB_CLK | BB_VOLT | BB_PWR, 2002 "XGS Hercules BCM5670_P8_00 Platform" }, 2003 { G13, BB_CLK | BB_VOLT | BB_PWR, 2004 "XGS Firebolt BCM56504P24_00 Platform" }, 2005 { G15, BB_VOLT | BB_PWR, 2006 "XGS Goldwing BCM56580K16 Platform" }, 2007 { G16, BB_VOLT | BB_PWR, 2008 "XGS Bradley BCM56800K20C Platform" }, 2009 { G17, BB_VOLT | BB_PWR, 2010 "XGS Bradley BCM56800K20 Platform" }, 2011 { G18, BB_VOLT | BB_PWR, 2012 "XGS raptor BCM56218k48 Platform" }, 2013 { G19, BB_VOLT, 2014 "XGS Raven BCM56224k24 Platform" }, 2015 { G20, BB_CLK | BB_VOLT, 2016 "XGS Triumph Platform"}, 2017 { G21, BB_CLK | BB_VOLT, 2018 "XGS Scorpion Platform"}, 2019 { G22, BB_CLK | BB_VOLT, 2020 "XGS Apollo Platform"}, 2021 { G23, BB_CLK | BB_VOLT, 2022 "Obsolete: SBX Sirius Platform"}, 2023 { G24, BB_CLK | BB_VOLT, 2024 "XGS Trident Platform"}, 2025 { G25, BB_CLK | BB_VOLT, 2026 "XGS Titan Platform"}, 2027 { G26, BB_VOLT, 2028 "XGS Hurricane Platform"}, 2029 { G27, BB_VOLT, 2030 "Shadow Platform"}, 2031 { G28, BB_VOLT, 2032 "XGS Katana / Hurricane2 / Helix4 Platform"}, 2033 { G29, BB_VOLT, 2034 "XGS Enduro-2 Platform"}, 2035 { G30, BB_VOLT, 2036 "XGS Stardust-2 Platform"}, 2037 { G31, BB_VOLT, 2038 "XGS Enduro-2 Platform"}, 2039 { G33, BB_CLK | BB_VOLT, 2040 "XGS Trident Platform"}, 2041 { G34, BB_VOLT, 2042 "XGS Triumph3 Legacy Platform"}, 2043 { G35, BB_VOLT, 2044 "XGS Triumph3 Platform"}, 2045 { G36, BB_VOLT | BB_CURR, 2046 "Caladan3 48G Platform"}, 2047 { G37, BB_VOLT | BB_CURR, 2048 "Caladan3 100G Platform"}, 2049 { G38, BB_VOLT, 2050 "Trident2 Platform"}, 2051 { G39, BB_VOLT, 2052 "Trident2 DVT Platform" }, 2053 { G40, BB_VOLT | BB_CURR, 2054 "Katana2 Platform" }, 2055 { G41, BB_VOLT | BB_SEQ, 2056 "Greyhound/Elkhound/Ranger2 27x27 QSGMII Platform"}, 2057 { G42, BB_VOLT | BB_SEQ, 2058 "Tomahawk Platform" }, 2059 { G43, BB_VOLT, 2060 "Trident2+ Platform"}, 2061 { G44, BB_VOLT | BB_SEQ, 2062 "Trident2+ 100G Platform"}, 2063 { G45, BB_VOLT, 2064 "Greyhound/Elkhound 25x25 QSGMII Platform"}, 2065 { G46, BB_VOLT, 2066 "Greyhound/Ranger2 27x27 Platform"}, 2067 { G47, BB_VOLT, 2068 "Greyhound/Ranger2 25x25 Platform"}, 2069 { G48, BB_VOLT | BB_SEQ, 2070 "Saber2 Platform" }, 2071 { G49, BB_VOLT | BB_SEQ, 2072 "Tomahawk PVT Platform"}, 2073 { G50, BB_VOLT, 2074 "Apache/Maverick Platform"}, 2075 { G51, BB_VOLT, 2076 "FireBolt5 Platform"}, 2077 { G52, BB_VOLT | BB_SEQ, 2078 "Hurricane3 29x29 Platform"}, 2079 { G53, BB_VOLT | BB_SEQ, 2080 "Hurricane3 25x25 Platform"}, 2081 { G54, BB_VOLT | BB_SEQ, 2082 "Hurricane3 21x21 Platform"}, 2083 { G55, BB_VOLT | BB_SEQ, 2084 "Hurricane3 29x29 D-Platform"}, 2085 { G56, BB_VOLT, 2086 "Metrolite Platform" }, 2087 { G57, BB_VOLT, 2088 "Tomahawk2 Platform" }, 2089 { G58, BB_VOLT | BB_SEQ, 2090 "Greyhound2 31x31 Platform"}, 2091 { G59, BB_VOLT | BB_SEQ, 2092 "Greyhound2 31x31 Platform"}, 2093 { G60, BB_VOLT, 2094 "Trident3/Maverick2 Platform"}, 2095 { G61, BB_VOLT, 2096 "Monterey Platform"}, 2097 { G62, BB_VOLT | BB_SEQ, 2098 "Wolfhound2 Platform"}, 2099 { G63, BB_VOLT | BB_SEQ, 2100 "Wolfhound2 Platform"}, 2101 { G64, BB_VOLT, 2102 "Tomahawk3 Platform"}, 2103 { G65, BB_VOLT, 2104 "Helix5 Platform"}, 2105 { ENG, BB_NONE, 2106 "ENG Version" }, 2107 { UNK, BB_NONE, 2108 "No Info or I2C unavailable on this platform" } 2109 }; 2110 2111 /* Number of possible board types */ 2112 #define NUM_BOARD_TYPES COUNTOF(baseboards) 2113 2114 #define MAX_VS_CONFIG_PER_BOARD 12 2115 2116 /* Max number of clocks per board */ 2117 #define MAX_CLOCKS_PER_BOARD 10 2118 2119 /* Max number of voltages per board */ 2120 #define MAX_VOLTAGES_PER_BOARD 32 2121 2122 /* Set once at bootup */ 2123 static int soc_board_idx = -1; 2124 2125 /* 2126 * If the board_id is not supported in board, get the board type by 2127 * soc property. 2128 */ 2129 STATIC int 2130 bb_get_board_type_by_board_name(int unit) 2131 { 2132 char *board_name = soc_property_get_str(unit, spn_BOARD_NAME); 2133 int board_type = -1; 2134 2135 if (board_name != NULL) { 2136 if (sal_strcmp(board_name, "BCM953406K") == 0) { 2137 board_type = G47; 2138 } else if (sal_strcmp(board_name, "BCM953411K") == 0) { 2139 board_type = G41; 2140 } else if (sal_strcmp(board_name, "BCM953416K") == 0) { 2141 board_type = G46; 2142 } else if (sal_strcmp(board_name, "BCM956160D") == 0) { 2143 board_type = G55; 2144 } else if (sal_strcmp(board_name, "BCM953570S") == 0) { 2145 board_type = G59; 2146 } else { 2147 cli_out("board_name = %s, supported board names are BCM953406K, " 2148 "BCM953411K, BCM953416K, BCM56160D and BCM953570S.\n" 2149 "Please define board_name in config.bcm\n", board_name); 2150 } 2151 } 2152 2153 return board_type; 2154 } 2155 2156 2157 /* 2158 * Get system baseboard info, either by reading it 2159 * from EEPROM or by probing the PCI and I2C buses. 2160 * This routine attempts to determine "board type", 2161 * which is used subsequently as an index by tables 2162 * commented with INDEXED_BY_BOARD_TYPE. 2163 */ 2164 bb_type_t* 2165 soc_i2c_detect_board(void) 2166 { 2167 int bd_idx; 2168 uint32 id_detected =0; 2169 uint8 board_id =0; 2170 int id, dev; 2171 int n_adc=0, n_dac=0, n_pll=0, n_temp=0, n_eeprom=0, n_poe=0; 2172 i2c_device_t* i2c_dev = NULL; 2173 int found = 0, board_type = -1; 2174 2175 2176 dev = 0; 2177 if (soc_ndev > 0) { 2178 if (!soc_i2c_is_attached(dev)) { 2179 if (soc_i2c_attach(dev, 0, 0) < 0) { 2180 cli_out("unit %d soc_i2c_detect_board: " 2181 "error attaching to I2C bus\n", 2182 dev); 2183 return NULL; 2184 } 2185 } 2186 2187 if (soc_i2c_probe(dev) < 0) { 2188 cli_out("unit %d soc_i2c_detect_board: " 2189 "error probing the I2C bus\n", 2190 dev); 2191 return NULL; 2192 } 2193 2194 for( id = 0; id < soc_i2c_device_count(dev); id++) { 2195 i2c_dev = soc_i2c_device(dev, id) ; 2196 if ( i2c_dev ) { 2197 /* Board ID register */ 2198 if ( ( i2c_dev->driver->id == PCF8574_DEVICE_TYPE ) && 2199 ( i2c_dev->saddr == I2C_LPT_SADDR1 ) ) { 2200 /* id_detected will be set to 1 by the following call (length) */ 2201 /* Read the board ID register */ 2202 i2c_dev->driver->read(dev, id, 0, &board_id, &id_detected); 2203 } 2204 #ifdef SHADOW_SVK 2205 /* 2206 * In Shadow SVK, board id is read from port 1 in PCA9505 2207 * at I2C_IOP_SADDR1 2208 */ 2209 if ( ( i2c_dev->driver->id == PCA9505_DEVICE_TYPE ) && 2210 ( i2c_dev->saddr == I2C_IOP_SADDR1 ) ) { 2211 /* Read the board ID register */ 2212 /* cli_out("reading id from 9505\n"); */ 2213 i2c_dev->driver->read(dev, id, 0, &board_id, &id_detected); 2214 } 2215 #endif /* SHADOW_SVK */ 2216 /* ADC */ 2217 if (( i2c_dev->driver->id == MAX127_DEVICE_TYPE) || 2218 ( i2c_dev->driver->id == LTC2974_DEVICE_TYPE)) { 2219 n_adc++; 2220 } 2221 /* DAC */ 2222 if (( i2c_dev->driver->id == LTC1427_DEVICE_TYPE) || 2223 (i2c_dev->driver->id == LTC3880_DEVICE_TYPE) || 2224 (i2c_dev->driver->id == LTC3884_DEVICE_TYPE) || 2225 (i2c_dev->driver->id == LTC3882_DEVICE_TYPE)) { 2226 n_dac++; 2227 } 2228 2229 /* W229B PLL */ 2230 if ( i2c_dev->driver->id == W229B_DEVICE_TYPE ) { 2231 n_pll++; 2232 } 2233 2234 /* EEPROM */ 2235 if ( i2c_dev->driver->id == LC24C64_DEVICE_TYPE){ 2236 n_eeprom++; 2237 2238 } 2239 2240 /* LM75/LM63 Temp */ 2241 if (( i2c_dev->driver->id == LM75_DEVICE_TYPE ) || 2242 (i2c_dev->driver->id == LM63_DEVICE_TYPE)) { 2243 n_temp++; 2244 } 2245 2246 /* POE controller */ 2247 if ( i2c_dev->driver->id == LTC4258_DEVICE_TYPE ){ 2248 n_poe++; 2249 } 2250 } 2251 } 2252 } 2253 2254 2255 2256 /* Here if we did not find any board-specific info in the EEPROM. */ 2257 /* We know what the soc_ndev devices are, and what exists on the */ 2258 /* I2C bus. Use this information to identify the hardware platform. */ 2259 2260 /**********************************************************/ 2261 /* Specific, uniquely populated, or valid board_id boards */ 2262 /**********************************************************/ 2263 if (id_detected && (board_id == 0x26)) { 2264 /* Firebolt */ 2265 board_type = G13; 2266 } 2267 2268 #ifdef BCM_RAPTOR_SUPPORT 2269 else if ((soc_ndev > 0) && SOC_IS_RAPTOR(0)) { 2270 /* Raptor */ 2271 board_type = G18; 2272 } 2273 2274 else if ((soc_ndev > 0) && SOC_IS_RAVEN(0)) { 2275 /* Raven */ 2276 board_type = G19; 2277 } 2278 #endif 2279 2280 #ifdef SHADOW_SVK 2281 else if ((soc_ndev > 0) && SOC_IS_SHADOW(0)) { 2282 /* Alternatively, can check 2283 * if (id_detected && (board_id == (RadianSVK Id)) { 2284 * 2285 * Shadow SVK 2286 */ 2287 board_type = G27; 2288 } 2289 #endif /* SHADOW_SVK */ 2290 2291 #ifdef BCM_FIREBOLT_SUPPORT 2292 else if ((soc_ndev > 0) && SOC_IS_FB_FX_HX(0)) { /* Fallback */ 2293 /* Firebolt/Helix/Felix */ 2294 board_type = G13; 2295 } 2296 #endif 2297 else if (id_detected && (board_id == 0x34)) { 2298 /* Goldwing */ 2299 board_type = G15; 2300 } 2301 2302 else if (id_detected && (board_id == 0x39)) { 2303 /* Bradley 1G */ 2304 board_type = G16; 2305 } 2306 2307 else if (id_detected && (board_id == 0x3a)) { 2308 /* Bradley */ 2309 board_type = G17; 2310 } 2311 2312 else if (id_detected && (board_id == 0x53)){ 2313 /* Triumph */ 2314 board_type = G20; 2315 } 2316 2317 else if (id_detected && (board_id == 0x52)){ 2318 /* Scorpion */ 2319 board_type = G21; 2320 } 2321 2322 else if (id_detected && (board_id == 0x55 || board_id == 0x49)){ 2323 /* Apollo */ 2324 board_type = G22; 2325 } 2326 2327 else if (id_detected && (board_id == 0x5D)){ 2328 /* Trident */ 2329 board_type = G24; 2330 /* make sure all I2C devices behind the I2C mux device are initialized */ 2331 if (dac_devs_init(0,G24,I2C_MUX_3) < 0) { 2332 LOG_ERROR(BSL_LS_APPL_I2C, 2333 (BSL_META("ERROR: dac_devs_init fail\n"))); 2334 return NULL; 2335 } 2336 } 2337 2338 else if (id_detected && (board_id == 0x6A)){ 2339 /* Trident */ 2340 board_type = G33; 2341 /* make sure all I2C devices behind the I2C mux device are initialized */ 2342 if (dac_devs_init(0,G33,I2C_MUX_3) < 0) { 2343 LOG_ERROR(BSL_LS_APPL_I2C, 2344 (BSL_META("ERROR: dac_devs_init fail\n"))); 2345 return NULL; 2346 } 2347 } 2348 2349 else if (id_detected && (board_id == 0x60 || board_id == 0x61)){ 2350 /* Titan */ 2351 board_type = G25; 2352 } 2353 2354 else if (id_detected && (board_id == 0x5E || board_id == 0x5F)){ 2355 /* Hurricane */ 2356 board_type = G26; 2357 } 2358 2359 else if (id_detected && ((board_id == 0x65) || (board_id == 0x67) || (board_id == 0x72))){ 2360 /* Katana / Hurricane2 / Helix4*/ 2361 board_type = G28; 2362 } 2363 2364 else if (id_detected && (board_id == 0x64)){ 2365 /* Enduro-2 */ 2366 board_type = G29; 2367 } 2368 2369 else if (id_detected && (board_id == 0x68)){ 2370 /* Stardust-2 */ 2371 board_type = G30; 2372 } 2373 2374 else if (id_detected && (board_id == 0x6D)){ 2375 /* Enduro-2 */ 2376 board_type = G31; 2377 } 2378 2379 else if (id_detected && (board_id == 0x69)){ 2380 /* Triumph3 Legacy */ 2381 board_type = G34; 2382 /* make sure all I2C devices behind the I2C mux device 2383 * are initialized */ 2384 if (dac_devs_init(0,G34,I2C_MUX_3) < 0) { 2385 LOG_ERROR(BSL_LS_APPL_I2C, 2386 (BSL_META("ERROR: dac_devs_init fail\n"))); 2387 return NULL; 2388 } 2389 } 2390 2391 else if (id_detected && (board_id == 0x6e)){ 2392 /* Triumph3 Legacy */ 2393 board_type = G35; 2394 /* make sure all I2C devices behind the I2C mux device 2395 * are initialized */ 2396 if (dac_devs_init(0,G35,I2C_MUX_3) < 0) { 2397 LOG_ERROR(BSL_LS_APPL_I2C, 2398 (BSL_META("ERROR: dac_devs_init fail\n"))); 2399 return NULL; 2400 } 2401 } 2402 2403 else if (id_detected && (board_id == 0x6f)){ 2404 /* Tomahawk */ 2405 if (soc_property_get(0, "th_i2c_test_board", 0)) { 2406 board_type = G42; 2407 } else if (SOC_IS_TD2P_TT2P(0) || SOC_IS_APACHE(0)) { 2408 /* Trident2+ or TD2+ compatible BCM956765K (Maverick) */ 2409 board_type = G43; 2410 } else { 2411 /* Trident2 */ 2412 board_type = G38; 2413 } 2414 /* make sure all I2C devices behind the I2C mux device 2415 * are initialized */ 2416 if (dac_devs_init(0, board_type, I2C_MUX_3) < 0) { 2417 LOG_ERROR(BSL_LS_APPL_I2C, 2418 (BSL_META("ERROR: dac_devs_init fail\n"))); 2419 return NULL; 2420 } 2421 } 2422 2423 else if (id_detected && board_id == 0x70) { 2424 /* Trident2 DVT */ 2425 board_type = G39; 2426 /* make sure all I2C devices behind the I2C mux device 2427 * are initialized */ 2428 if (dac_devs_init(0, G39, I2C_MUX_3) < 0) { 2429 LOG_ERROR(BSL_LS_APPL_I2C, 2430 (BSL_META("ERROR: dac_devs_init fail\n"))); 2431 return NULL; 2432 } 2433 } 2434 2435 else if (id_detected && (board_id == 0x87)) { 2436 /* Saber2 Boards */ 2437 board_type = G48; 2438 2439 /* make sure all I2C devices behind the I2C mux device 2440 * are initialized */ 2441 if (dac_devs_init(0, G48, I2C_MUX_3) < 0) { 2442 LOG_ERROR(BSL_LS_APPL_I2C, 2443 (BSL_META("ERROR: dac_devs_init fail\n"))); 2444 return NULL; 2445 } 2446 } 2447 2448 else if (id_detected && (board_id == 0x98)) { 2449 /* Metrolite Boards */ 2450 board_type = G56; 2451 } 2452 2453 else if (id_detected && ((board_id == 0x77) || (board_id == 0x78) || 2454 (board_id == 0x79) || (board_id == 0x80))){ 2455 /* Katana2 Boards */ 2456 board_type = G40; 2457 } 2458 2459 else if (id_detected && ((board_id == 0x8c) || (board_id == 0x8e))){ 2460 /* BCM953457K, BCM956062K, BCM953411K, BCM956064K */ 2461 board_type = G41; 2462 } 2463 else if (id_detected && (board_id == 0x8d)){ 2464 /* BCM953456K */ 2465 board_type = G45; 2466 } 2467 else if (id_detected && (board_id == 0x83)) { 2468 /* Tomahawk */ 2469 board_type = G42; 2470 /* make sure all I2C devices behind the I2C mux device 2471 * are initialized */ 2472 if (dac_devs_init(0, G42, I2C_MUX_3) < 0) { 2473 LOG_ERROR(BSL_LS_APPL_I2C, 2474 (BSL_META("ERROR: dac_devs_init fail\n"))); 2475 return NULL; 2476 } 2477 } 2478 2479 else if (id_detected && board_id == 0x8B) { 2480 /* Trident2+ 100G board */ 2481 board_type = G44; 2482 /* make sure all I2C devices behind the I2C mux device 2483 * are initialized */ 2484 if (dac_devs_init(0, board_type, I2C_MUX_3) < 0) { 2485 LOG_ERROR(BSL_LS_APPL_I2C, 2486 (BSL_META("ERROR: dac_devs_init fail\n"))); 2487 return NULL; 2488 } 2489 } 2490 2491 else if (id_detected && (board_id == 0x88)) { 2492 /* Tomahawk PVT */ 2493 board_type = G49; 2494 /* make sure all I2C devices behind the I2C mux device 2495 * are initialized */ 2496 if (dac_devs_init(0, G49, I2C_MUX_70) < 0) { 2497 LOG_ERROR(BSL_LS_APPL_I2C, 2498 (BSL_META("ERROR: dac_devs_init fail\n"))); 2499 return NULL; 2500 } 2501 } else if (id_detected && (board_id == 0x94)) { 2502 /* Apache/Maverick */ 2503 board_type = G50; 2504 } else if (id_detected && (board_id == 0x96)) { 2505 /* FireBolt5 */ 2506 board_type = G51; 2507 } 2508 2509 else if (id_detected && ((board_id == 0x8F) || 2510 (board_id == 0x90) || (board_id == 0x91))) { 2511 /* HR3 SVK */ 2512 if (board_id == 0x8F) { 2513 board_type = G52; 2514 } else if (board_id == 0x90) { 2515 board_type = G53; 2516 } else { 2517 board_type = G54; 2518 } 2519 } 2520 2521 else if (id_detected && ((board_id == 0x9F) || 2522 (board_id == 0x9E) || (board_id == 0x9D) || 2523 (board_id == 0xA3))) { 2524 /* Tomahawk2 */ 2525 board_type = G57; 2526 } 2527 2528 else if (id_detected && (board_id == 0xA0)) { 2529 /* GH2 SVK */ 2530 board_type = G58; 2531 } 2532 2533 else if (id_detected && ((board_id == 0xA4) || 2534 (board_id == 0xA5) || (board_id == 0xA6) || 2535 (board_id == 0xA7) || (board_id == 0xB5))) { 2536 /* Trident3/Maverick2 */ 2537 board_type = G60; 2538 2539 } else if (id_detected && (board_id == 0xAA)) { 2540 /* Monterey */ 2541 board_type = G61; 2542 } 2543 2544 else if (id_detected && ((board_id == 0xA8) || 2545 (board_id == 0xA9))) { 2546 /* Wolfhound2 */ 2547 if (board_id == 0xA8) { 2548 board_type = G62; 2549 } else { 2550 board_type = G63; 2551 } 2552 } 2553 2554 else if (id_detected && ((board_id == 0xAC) || (board_id == 0xDE) || 2555 (board_id == 0xB1) || (board_id == 0xAD) || (board_id == 0xAF))) { 2556 /* TH3 SVK */ 2557 board_type = G64; 2558 } 2559 2560 else if (id_detected && ((board_id == 0xB0) || (board_id == 0xB3) || 2561 (board_id == 0xB6))) { 2562 /* Helix-5 */ 2563 board_type = G65; 2564 } 2565 2566 /**************************/ 2567 /* Other multi-SOC boards */ 2568 /**************************/ 2569 2570 else if (soc_ndev > 1) { 2571 /***************************************/ 2572 /* Other unidentified multi-soc boards */ 2573 /***************************************/ 2574 board_type = ENG; 2575 } /* soc_ndev > 1 */ 2576 2577 /*****************************/ 2578 /* Other (single) SOC boards */ 2579 /*****************************/ 2580 2581 else { 2582 if (SOC_IS_XGS12_FABRIC(0)) { 2583 /* Hercules */ 2584 board_type = G5; 2585 } 2586 else{ 2587 board_type = bb_get_board_type_by_board_name(0); 2588 if(board_type == -1) { 2589 /****************************************/ 2590 /* Other unidentified single-soc boards */ 2591 /****************************************/ 2592 board_type = ENG; 2593 cli_out("Using generic board type\n"); 2594 } 2595 } 2596 } 2597 for( bd_idx = 0; bd_idx < NUM_BOARD_TYPES; bd_idx++ ) { 2598 if (baseboards[bd_idx].type == board_type){ 2599 found=1; 2600 break; 2601 } 2602 } 2603 /* Probably know Board */ 2604 if ( found ) { 2605 if (BaseboardName == NULL) 2606 BaseboardName = baseboards[bd_idx].name_text; 2607 /* cli_out("Detected: %s\n", BaseboardName); */ 2608 return &baseboards[bd_idx]; 2609 } 2610 BaseboardName = NULL; 2611 return NULL; 2612 } /* end soc_i2c_detect_board() */ 2613 2614 2615 /* 2616 * Use I2C to detect the correct type of board */ 2617 void 2618 soc_i2c_board_probe(void) 2619 { 2620 bb_type_t* board = soc_i2c_detect_board(); 2621 if ( board ) { 2622 soc_board_idx = board->type; 2623 } else { 2624 cli_out("NOTICE: board type unknown.\n"); 2625 soc_board_idx = UNK; 2626 } 2627 } 2628 2629 /* 2630 * Return number of possible boards. 2631 */ 2632 int 2633 soc_num_boards(void) 2634 { 2635 return NUM_BOARD_TYPES; 2636 } 2637 2638 /* 2639 * Possibly probe, but always return correct 2640 * known index. 2641 */ 2642 int 2643 soc_get_board_id(void) 2644 { 2645 if ((soc_board_idx < 0) || (soc_board_idx == UNK)) { 2646 soc_i2c_board_probe(); 2647 } 2648 return soc_board_idx; 2649 } 2650 2651 /* 2652 * Return raw board info struct. 2653 */ 2654 bb_type_t* 2655 soc_get_board(void) 2656 { 2657 int inx; 2658 inx = soc_get_board_id(); 2659 2660 if ((inx < 0) || (inx >= NUM_BOARD_TYPES)) { 2661 return NULL; 2662 } 2663 return &baseboards[inx]; 2664 } 2665 2666 2667 /* 2668 * Function: cmd_temperature 2669 * Purpose: Temperature and Temperature monitoring commands. 2670 */ 2671 char cmd_temperature_usage[] = 2672 "Usages:\n\t" 2673 " temperature [show]\n\t" 2674 " - show current temperature on all devices.\n\t" 2675 " temperature [watch|nowatch] [delay]\n\t" 2676 " - monitor temperatures in background, reporting changes.\n\t" 2677 "\n"; 2678 2679 cmd_result_t 2680 cmd_temperature(int unit, args_t *a) 2681 { 2682 char *function = ARG_GET(a); 2683 char *interval = ARG_GET(a); 2684 uint32 delay = 5; /* Report stats every 5 seconds */ 2685 2686 if (! sh_check_attached(ARG_CMD(a), unit)) { 2687 return CMD_FAIL; 2688 } 2689 2690 if (! function || 2691 ! sal_strncasecmp(function, "show", sal_strlen(function)) ){ 2692 switch (soc_get_board_id()) 2693 { 2694 case G50: 2695 case G51: 2696 case G61: 2697 soc_i2c_lm63_temperature_show(unit); 2698 2699 break; 2700 2701 case G23: 2702 soc_i2c_max664x_temperature_show(unit); 2703 2704 break; 2705 2706 case G64: 2707 soc_i2c_max669x_temperature_show(unit); 2708 2709 break; 2710 2711 default: 2712 soc_i2c_lm75_temperature_show(unit); 2713 2714 break; 2715 } 2716 } else if ( ! sal_strncasecmp(function,"watch",sal_strlen(function)) ){ 2717 if ( interval ) 2718 delay = parse_integer(interval); 2719 switch (soc_get_board_id()) 2720 { 2721 case G50: 2722 case G51: 2723 case G61: 2724 soc_i2c_lm63_monitor(unit, TRUE, delay); 2725 2726 break; 2727 2728 case G23: 2729 soc_i2c_max664x_monitor(unit, TRUE, delay); 2730 2731 break; 2732 2733 case G64: 2734 soc_i2c_max669x_monitor(unit, TRUE, delay); 2735 2736 break; 2737 2738 default: 2739 soc_i2c_lm75_monitor(unit, TRUE, delay); 2740 2741 break; 2742 } 2743 } else if ( ! sal_strncasecmp(function,"nowatch",sal_strlen(function)) ){ 2744 switch (soc_get_board_id()) 2745 { 2746 case G50: 2747 case G51: 2748 case G61: 2749 soc_i2c_lm63_monitor(unit, FALSE, 0); 2750 2751 break; 2752 2753 case G23: 2754 soc_i2c_max664x_monitor(unit, FALSE, 0); 2755 2756 break; 2757 2758 case G64: 2759 soc_i2c_max669x_monitor(unit, FALSE, 0); 2760 2761 break; 2762 2763 default: 2764 soc_i2c_lm75_monitor(unit, FALSE, 0); 2765 2766 break; 2767 } 2768 } else { 2769 return CMD_USAGE; 2770 } 2771 2772 return CMD_OK; 2773 } 2774 2775 2776 STATIC char * 2777 _i2c_mux_default_dev_name_get(void) 2778 { 2779 /* Default device locates the DAC */ 2780 char *dev_name = NULL; 2781 2782 if (soc_get_board_id() == G27) { 2783 dev_name = I2C_MUX_6; 2784 } else if (soc_get_board_id() == G49) { 2785 dev_name = I2C_MUX_70; 2786 } else if ((soc_get_board_id() == G25) || (soc_get_board_id() == G24) || 2787 (soc_get_board_id() == G28) || (soc_get_board_id() == G29) || 2788 (soc_get_board_id() == G30) || (soc_get_board_id() == G31) || 2789 (soc_get_board_id() == G33) || (soc_get_board_id() == G34) || 2790 (soc_get_board_id() == G35) || (soc_get_board_id() == G38) || 2791 (soc_get_board_id() == G39) || (soc_get_board_id() == G40) || 2792 (soc_get_board_id() == G41) || (soc_get_board_id() == G42) || 2793 (soc_get_board_id() == G43) || (soc_get_board_id() == G44) || 2794 (soc_get_board_id() == G48) || (soc_get_board_id() == G50) || 2795 (soc_get_board_id() == G51) || (soc_get_board_id() == G56) || 2796 (soc_get_board_id() == G57) || (soc_get_board_id() == G60) || 2797 (soc_get_board_id() == G61) || (soc_get_board_id() == G64) || 2798 (soc_get_board_id() == G65)) { 2799 dev_name = I2C_MUX_3; 2800 } else { 2801 dev_name = I2C_LPT_0; 2802 } 2803 return dev_name; 2804 } 2805 2806 /* 2807 * Function: cmd_i2c 2808 * Purpose: I2C probe/attach/show, configuration commands. 2809 * Also sets up board index and configures I2C drivers 2810 * based on the inferred system board type. 2811 */ 2812 char cmd_i2c_usage[] = 2813 "Usages:\n\t" 2814 #ifdef COMPILER_STRING_CONST_LIMIT 2815 "i2c probe | log | backlog | clearlog | reset | speeds | show\n" 2816 #else 2817 "i2c probe [pio|intr] [speed] [quiet]\n\t" 2818 " - probe devices on I2C bus and build device tree.\n\t" 2819 " If \"intr\" or \"pio\" is specified, change to that bus mode.\n\t" 2820 " If a valid speed is specified, change the bus to that speed.\n\t" 2821 " If \"quiet\" is specified, suppresses probe output.\n\t" 2822 #ifdef SHADOW_SVK 2823 "i2c test board_type\n\t" 2824 " - Test presence of I2C devices in the SVK.\n\t" 2825 " Supported board types are shadow_40GSVK and shadow_10GSVK\n\t" 2826 #endif 2827 "i2c scan [pio|intr] [saddr] [quiet]\n\t" 2828 " - Scan devices on I2C bus and display the device list.\n\t" 2829 "i2c log \n\t" 2830 " - show I2C bus transaction log.\n\t" 2831 "i2c backlog \n\t" 2832 " - show I2C bus transaction log (in reverse order).\n\t" 2833 "i2c clearlog \n\t" 2834 " - reset I2C bus transaction log.\n\t" 2835 "i2c reset\n\t" 2836 " - reset I2C bus controller core.\n\t" 2837 "i2c speeds\n\t" 2838 " - show supported I2C bus controller clock rates.\n\t" 2839 "i2c show\n\t" 2840 " - show devices found and their attributes.\n\t" 2841 "i2c read saddr comm len \n\t" 2842 " - generic interface to read devices, do probe first \n\t" 2843 "i2c readw saddr comm \n\t" 2844 " - generic interface to read one word from devices, do probe first \n\t" 2845 "i2c readb saddr len \n\t" 2846 " - generic interface to read devices without register based access, do probe first\n\t" 2847 "i2c write saddr comm [data] \n\t" 2848 " - generic interface to write a byte to devices, do probe first\n\t" 2849 " - comm is data when writing directly otherwise command register\n" 2850 "i2c writew saddr comm [word_data] \n\t" 2851 " - generic interface to write a word to devices, do probe first\n\t" 2852 " - comm is data when writing directly otherwise command register\n" 2853 "i2c device add <dev_name> <saddr> <drv_name> \n\t" 2854 " - add device to custom device descriptor.\n\t" 2855 " i2c probe will probe the deivce existed in the custom device \n\t" 2856 " descriptor\n" 2857 "i2c device remove <dev_name> <saddr> <drv_name> \n\t" 2858 " - remove device to custom device descriptor.\n\t" 2859 #endif 2860 ; 2861 2862 cmd_result_t 2863 cmd_i2c(int unit, args_t *a) 2864 { 2865 char *function, *op; 2866 uint32 flags; 2867 int rv, quiet, speed; 2868 int i, parsedata; 2869 uint8 saddr=0, data=0, comm=0; 2870 int len=0; 2871 uint8 buffer[256]; 2872 uint16 buffer_w; 2873 #ifdef SHADOW_SVK 2874 int svk_40g = 0; 2875 int svk_10g = 0; 2876 #endif /* SHADOW_SVK */ 2877 2878 if (! sh_check_attached(ARG_CMD(a), unit)) 2879 return CMD_FAIL; 2880 2881 function = ARG_GET(a); 2882 if (! function ) { 2883 return CMD_USAGE; 2884 } else if (! sal_strncasecmp(function, "show", sal_strlen(function)) ){ 2885 soc_i2c_show(unit); 2886 } else if ( ! sal_strncasecmp(function,"reset", sal_strlen(function))) { 2887 soc_i2c_reset(unit); 2888 } else if ( !sal_strncasecmp(function, "speeds", sal_strlen(function))) { 2889 soc_i2c_show_speeds(unit); 2890 } else if ( !sal_strncasecmp(function, "log", 3)) { 2891 soc_i2c_show_log(unit, FALSE); 2892 } else if ( !sal_strncasecmp(function, "clearlog", sal_strlen(function))) { 2893 soc_i2c_clear_log(unit); 2894 } else if ( !sal_strncasecmp(function, "backlog", 7)) { 2895 soc_i2c_show_log(unit, TRUE); 2896 } else if ( !sal_strncasecmp(function, "readb", 5)) { 2897 if (!soc_i2c_is_attached(unit)) { 2898 cli_out("i2c raw read/write commands require probe to be called first\n"); 2899 return CMD_USAGE; 2900 } 2901 op = ARG_GET(a); 2902 if (op == NULL) { 2903 return CMD_USAGE; 2904 } else { 2905 parsedata = parse_integer(op); 2906 if (parsedata == 0) { 2907 cli_out("\nNeed Slave address"); 2908 return CMD_FAIL; 2909 } 2910 saddr = parsedata; 2911 } 2912 op = ARG_GET(a); 2913 if (op == NULL) { 2914 return CMD_USAGE; 2915 } else { 2916 len = parse_integer(op); 2917 } 2918 for(i=0; i<len; i++) { 2919 rv = soc_i2c_read_byte(unit, saddr, &data); 2920 if (SOC_FAILURE(rv)) { 2921 break; 2922 } 2923 if (i%16 == 0) { 2924 cli_out("\n%02x:", i); 2925 } 2926 cli_out(" %02x", data); 2927 } 2928 cli_out("\n"); 2929 return CMD_OK; 2930 } else if (!sal_strncasecmp(function, "readw", 5)) { 2931 if (!soc_i2c_is_attached(unit)) { 2932 cli_out("i2c raw read/write commands require probe to be called first\n"); 2933 return CMD_USAGE; 2934 } 2935 op = ARG_GET(a); 2936 if (op == NULL) { 2937 return CMD_USAGE; 2938 } else { 2939 parsedata = parse_integer(op); 2940 if (parsedata == 0) { 2941 2942 cli_out("\nNeed Slave address"); 2943 return CMD_FAIL; 2944 } 2945 saddr = parsedata; 2946 } 2947 2948 op = ARG_GET(a); 2949 if (op == NULL) { 2950 return CMD_USAGE; 2951 } else { 2952 comm = parse_integer(op); 2953 } 2954 2955 op = ARG_GET(a); 2956 if (op != NULL) { 2957 len = parse_integer(op); 2958 if (len != 1) { 2959 return CMD_USAGE; 2960 } 2961 } 2962 2963 rv = soc_i2c_read_word_data(unit, saddr, comm, &buffer_w); 2964 if (SOC_FAILURE(rv)) { 2965 cli_out("\n"); 2966 return CMD_OK; 2967 } 2968 cli_out("\n%02x:", comm); 2969 cli_out("%02x", buffer_w); 2970 cli_out("\n"); 2971 return CMD_OK; 2972 2973 } else if ( !sal_strncasecmp(function, "read", 4)) { 2974 if (!soc_i2c_is_attached(unit)) { 2975 cli_out("i2c raw read/write commands require probe to be called first\n"); 2976 return CMD_USAGE; 2977 } 2978 op = ARG_GET(a); 2979 if (op == NULL) { 2980 return CMD_USAGE; 2981 } else { 2982 parsedata = parse_integer(op); 2983 if (parsedata == 0) { 2984 cli_out("\nNeed Slave address"); 2985 return CMD_FAIL; 2986 } 2987 saddr = parsedata; 2988 } 2989 op = ARG_GET(a); 2990 if (op == NULL) { 2991 return CMD_USAGE; 2992 } else { 2993 comm = parse_integer(op); 2994 } 2995 op = ARG_GET(a); 2996 if (op == NULL) { 2997 return CMD_USAGE; 2998 } else { 2999 len = parse_integer(op); 3000 /*if (len > 256) { 3001 cli_out("\nlen too big, Buffer is limited to 256 bytes"); 3002 return CMD_FAIL; 3003 }*/ 3004 } 3005 for(i=0; i<len; i++) { 3006 rv = soc_i2c_read_byte_data(unit, saddr, comm + i, &buffer[i]); 3007 if (SOC_FAILURE(rv)) { 3008 break; 3009 } 3010 if (i%16 == 0) { 3011 cli_out("\n%02x:", i); 3012 } 3013 cli_out(" %02x", buffer[i]); 3014 } 3015 cli_out("\n"); 3016 return CMD_OK; 3017 } else if (!sal_strncasecmp(function, "writew", 6)) { 3018 if (!soc_i2c_is_attached(unit)) { 3019 cli_out("i2c raw read/write commands require probe to be called first\n"); 3020 return CMD_USAGE; 3021 } 3022 op = ARG_GET(a); 3023 if (op == NULL) { 3024 return CMD_USAGE; 3025 } else { 3026 parsedata = parse_integer(op); 3027 if (parsedata == 0) { 3028 cli_out("\nNeed Slave address"); 3029 return CMD_FAIL; 3030 } 3031 saddr = parsedata; 3032 } 3033 3034 op = ARG_GET(a); 3035 if (op == NULL) { 3036 return CMD_USAGE; 3037 } else { 3038 comm = parse_integer(op); 3039 } 3040 3041 op = ARG_GET(a); 3042 if (op != NULL) { 3043 buffer_w = parse_integer(op); 3044 } 3045 else { 3046 return CMD_FAIL; 3047 } 3048 rv = soc_i2c_write_word_data(unit, saddr, comm, buffer_w); 3049 if (SOC_FAILURE(rv)) { 3050 cli_out(" Writew Failed \n"); 3051 return CMD_OK; 3052 } 3053 return CMD_OK; 3054 3055 } else if (!sal_strncasecmp(function, "write", 4)) { 3056 if (!soc_i2c_is_attached(unit)) { 3057 cli_out("i2c raw read/write commands require probe to be called first\n"); 3058 return CMD_USAGE; 3059 } 3060 op = ARG_GET(a); 3061 if (op == NULL) { 3062 return CMD_USAGE; 3063 } else { 3064 parsedata = parse_integer(op); 3065 if (parsedata == 0) { 3066 cli_out("\nNeed Slave address"); 3067 return CMD_FAIL; 3068 } 3069 saddr = parsedata; 3070 } 3071 op = ARG_GET(a); 3072 if (op == NULL) { 3073 return CMD_USAGE; 3074 } else { 3075 comm = parse_integer(op); 3076 } 3077 op = ARG_GET(a); 3078 if (op == NULL) { 3079 rv = soc_i2c_write_byte(unit, saddr, comm); 3080 } else { 3081 data = parse_integer(op); 3082 rv = soc_i2c_write_byte_data(unit, saddr, comm, data); 3083 } 3084 if (SOC_SUCCESS(rv)) { 3085 return CMD_OK; 3086 } else { 3087 return CMD_FAIL; 3088 } 3089 3090 } else if (!sal_strncasecmp(function,"device", sal_strlen(function))){ 3091 i2c_device_t i2c_dev; 3092 char *dev_name, *drv_name; 3093 i2c_driver_t *drv; 3094 3095 sal_memset(&i2c_dev, 0, sizeof(i2c_device_t)); 3096 op = ARG_GET(a); 3097 if (sal_strncasecmp(op, "add", sal_strlen(op)) == 0) { 3098 if ((dev_name = ARG_GET(a)) == NULL) { 3099 return CMD_USAGE; 3100 } 3101 if (sal_strlen(dev_name) >= SOC_I2C_DEV_NAME_MAX) { 3102 cli_out("Exceed device name maximum length."); 3103 return CMD_FAIL; 3104 } 3105 i2c_dev.devname = sal_alloc(sal_strlen(dev_name), "custom dev name"); 3106 sal_strcpy(i2c_dev.devname, dev_name); 3107 3108 if ((op = ARG_GET(a)) == NULL) { 3109 return CMD_USAGE; 3110 } 3111 parsedata = parse_integer(op); 3112 if (parsedata == 0) { 3113 cli_out("\nNeed Slave address"); 3114 return CMD_FAIL; 3115 } 3116 i2c_dev.saddr = parsedata; 3117 if ((drv_name = ARG_GET(a)) == NULL) { 3118 return CMD_USAGE; 3119 } 3120 soc_i2c_dev_driver_get(unit, drv_name, &drv); 3121 i2c_dev.driver = drv; 3122 rv = soc_i2c_custom_device_add(unit, &i2c_dev); 3123 if (SOC_FAILURE(rv)) { 3124 return CMD_FAIL; 3125 } 3126 } else if (sal_strncasecmp(op, "remove", sal_strlen(op)) == 0) { 3127 if ((dev_name = ARG_GET(a)) == NULL) { 3128 return CMD_USAGE; 3129 } 3130 i2c_dev.devname = sal_alloc(sal_strlen(dev_name), "custom dev name"); 3131 sal_strcpy(i2c_dev.devname, dev_name); 3132 3133 if ((op = ARG_GET(a)) == NULL) { 3134 return CMD_USAGE; 3135 } 3136 parsedata = parse_integer(op); 3137 if (parsedata == 0) { 3138 cli_out("\nNeed Slave address"); 3139 return CMD_FAIL; 3140 } 3141 i2c_dev.saddr = parsedata; 3142 if ((drv_name = ARG_GET(a)) == NULL) { 3143 return CMD_USAGE; 3144 } 3145 soc_i2c_dev_driver_get(unit, drv_name, &drv); 3146 i2c_dev.driver = drv; 3147 rv = soc_i2c_custom_device_remove(unit, &i2c_dev); 3148 if (SOC_FAILURE(rv)) { 3149 return CMD_FAIL; 3150 } 3151 3152 } else { 3153 return CMD_USAGE; 3154 } 3155 3156 } else if ( ( !sal_strncasecmp(function,"probe", sal_strlen(function))) || 3157 #ifdef SHADOW_SVK 3158 ( !sal_strncasecmp(function,"test", sal_strlen(function))) || 3159 #endif 3160 ( !sal_strncasecmp(function,"scan", sal_strlen(function)))) { 3161 quiet = 0; 3162 flags = SOC_I2C_MODE_INTR; 3163 speed = -1; /* Use current speed, or default initially. */ 3164 3165 while ((op = ARG_GET(a)) != NULL) { 3166 if (sal_strncasecmp(op, "quiet", sal_strlen(op)) == 0) { 3167 quiet = 1; 3168 continue; 3169 } 3170 if (sal_strncasecmp(op, "pio", sal_strlen(op)) == 0) { 3171 flags = SOC_I2C_MODE_PIO; 3172 continue; 3173 } 3174 if (sal_strncasecmp(op, "intr", sal_strlen(op)) == 0) { 3175 flags = SOC_I2C_MODE_INTR; 3176 continue; 3177 } 3178 #ifdef SHADOW_SVK 3179 if (sal_strncasecmp(op, "shadow_40GSVK", sal_strlen(op)) == 0) { 3180 svk_40g = 1; 3181 continue; 3182 } 3183 if (sal_strncasecmp(op, "shadow_10GSVK", sal_strlen(op)) == 0) { 3184 svk_10g = 1; 3185 continue; 3186 } 3187 #endif /* SHADOW_SVK */ 3188 if (isdigit((unsigned)op[0])) { 3189 speed = parse_integer(op); 3190 continue; 3191 } 3192 cli_out("%s: Error: unknown probe argument: %s\n", 3193 ARG_CMD(a), op); 3194 return CMD_FAIL; 3195 } 3196 #ifdef SHADOW_SVK 3197 if ( !sal_strncasecmp(function,"test", sal_strlen(function))) { 3198 int i = 0; 3199 uint8 lptVal = 0; 3200 int fd; 3201 char *name; 3202 rv = soc_i2c_probe(unit); /* Will attach if not yet attached */ 3203 if (rv < 0) { 3204 cli_out("I2C Test Failed: I2C probe Failed\n"); 3205 return CMD_FAIL; 3206 } 3207 if (svk_40g) { 3208 i2c_saddr_t saddr[5] = {0x77, 0x76, 0x25, 0x20, 0x24}; 3209 for(i = 0; i < 5; i++) { 3210 if (soc_i2c_device_present(unit, saddr[i]) < 0) { 3211 cli_out("I2C Test Failed: Device NOT at slave address 0X%02X (%s)\n", 3212 saddr[i], soc_i2c_saddr_to_string(unit, saddr[i])); 3213 return CMD_FAIL; 3214 } 3215 } 3216 name = I2C_MUX_6; 3217 if ( (fd = _i2c_mux_open(unit, 0, 0, name)) < 0) { 3218 cli_out("I2C Test Failed: MUX at 0x76 Failed\n"); 3219 return CMD_FAIL; 3220 } 3221 3222 /* Go through Mux */ 3223 for(i = 0; i < 4; i++) { 3224 lptVal = (1 << i); 3225 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 3226 cli_out("I2C Test Failed:MUX Channel%d couldn't be selected\n", i); 3227 return CMD_FAIL; 3228 } 3229 if (soc_i2c_device_present(unit, 0x50) < 0) { 3230 cli_out("QSP not present in Channel %d \n", i); 3231 } 3232 } 3233 cli_out("I2C Test Passed\n"); 3234 return CMD_OK; 3235 } else if (svk_10g) { 3236 i2c_saddr_t saddr[8] = {0x77, 0x76, 0x22, 0x24, 0x27, 0x28, 3237 0x49, 0x6A}; 3238 for(i = 0; i < 8; i++) { 3239 if (soc_i2c_device_present(unit, saddr[i]) < 0) { 3240 cli_out("I2C Test Failed: Device NOT at slave address 0X%02X (%s)\n", 3241 saddr[i], soc_i2c_saddr_to_string(unit, saddr[i])); 3242 return CMD_FAIL; 3243 } 3244 } 3245 name = I2C_MUX_6; 3246 if ( (fd = _i2c_mux_open(unit, 0, 0, name)) < 0) { 3247 cli_out("I2C Test: Failed: MUX at 0x76 Failed\n"); 3248 return CMD_FAIL; 3249 } 3250 /* Go through Mux */ 3251 for(i = 0; i < 4; i++) { 3252 lptVal = (1 << i); 3253 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 3254 cli_out("I2C Test: Failed:MUX Channel%d couldn't be selected\n", i); 3255 return CMD_FAIL; 3256 } 3257 if (soc_i2c_device_present(unit, 0x50) < 0) { 3258 cli_out("QSP not present in Channel %d \n", i); 3259 } 3260 } 3261 /* Go through Mux */ 3262 for(i = 5; i < 8; i++) { 3263 lptVal = (1 << i); 3264 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 3265 cli_out("I2C Test: Failed:MUX Channel%d couldn't be selected\n", i); 3266 return CMD_FAIL; 3267 } 3268 if (soc_i2c_device_present(unit, 0x2C) < 0) { 3269 cli_out("DAC not present at Channel %d \n", i); 3270 } 3271 } 3272 name = I2C_MUX_7; 3273 if ( (fd = _i2c_mux_open(unit, 0, 0, name)) < 0) { 3274 cli_out("I2C Test Failed: MUX at 0x77 Failed\n"); 3275 return CMD_FAIL; 3276 } 3277 3278 /* Go through Mux */ 3279 for(i = 0; i < 8; i++) { 3280 lptVal = (1 << i); 3281 if( (rv = bcm_i2c_write(unit, fd, 0, &lptVal, 1)) < 0){ 3282 cli_out("I2C Test: Failed:MUX Channel%d couldn't be selected\n", i); 3283 return CMD_FAIL; 3284 } 3285 if (soc_i2c_device_present(unit, 0x50) < 0) { 3286 cli_out("SFP+ not present in Channel %d \n", i); 3287 } 3288 } 3289 cli_out("I2C Test: Passed\n"); 3290 return CMD_OK; 3291 } else { 3292 cli_out("I2C Test: Unknown Board type\n"); 3293 return CMD_FAIL; 3294 } 3295 } 3296 #endif 3297 3298 if ( !sal_strncasecmp(function,"probe", sal_strlen(function))) { 3299 /* 3300 * (Re-)attach to the I2C bus if the INTR/PIO mode or 3301 * bus speed has been specified (presumably new setting). 3302 */ 3303 if ((rv=soc_i2c_attach(unit, flags | SOC_I2C_NO_PROBE, speed)) < 0) { 3304 cli_out("%s: Error: attach failed: %s\n", 3305 ARG_CMD(a), bcm_errmsg(rv)); 3306 } 3307 3308 rv = soc_i2c_probe(unit); /* Will attach if not yet attached */ 3309 if (rv < 0) { 3310 cli_out("%s: Error: probe failed: %s\n", 3311 ARG_CMD(a), bcm_errmsg(rv)); 3312 } else if (!quiet) { 3313 cli_out("%s: detected %d device%s\n", 3314 ARG_CMD(a), rv, rv==1 ? "" : "s"); 3315 } 3316 } else { 3317 i2c_saddr_t saddr = 0x00; 3318 int saddr_start = 0x00; 3319 int saddr_end = 0x7F; 3320 /* 3321 * (Re-)attach to the I2C bus if the INTR/PIO mode or 3322 * bus speed has been specified (presumably new setting). 3323 */ 3324 if (!soc_i2c_is_attached(unit) || (flags != SOC_I2C_MODE_INTR)) { 3325 if ((rv=soc_i2c_attach(unit, flags, -1)) < 0) { 3326 cli_out("%s: Error: attach failed: %s\n", 3327 ARG_CMD(a), bcm_errmsg(rv)); 3328 } 3329 } 3330 3331 if (speed > 0) { 3332 saddr_start = saddr_end = speed & 0x7F; 3333 } 3334 for(;saddr_start <= saddr_end; saddr_start++) { 3335 saddr = saddr_start & 0x7F; 3336 if (soc_i2c_device_present(unit, saddr) >= 0) { 3337 cli_out("I2C device found at slave address 0X%02X (%s)\n", 3338 saddr_start, soc_i2c_saddr_to_string(unit, saddr)); 3339 } 3340 } 3341 } 3342 } 3343 else { 3344 return CMD_USAGE; 3345 } 3346 return CMD_OK; 3347 } 3348 3349 /* 3350 * Function: cmd_clk 3351 * Purpose: Set W229b/W311 clock speed for core clocks 3352 */ 3353 char cmd_clk_usage[] = 3354 "Usages:\n\t" 3355 " clocks w311mode \n\t" 3356 " - enable Cypress W311 clock chip driver mode.\n\t" 3357 " clocks [speed] \n\t" 3358 " - set BCM56xx core clock speed.\n\t" 3359 "\n"; 3360 3361 cmd_result_t 3362 cmd_clk(int unit, args_t *a) 3363 { 3364 char *speed = ARG_GET(a); 3365 uint32 clockval = 0; 3366 #ifdef COMPILER_HAS_DOUBLE 3367 double clockFVal = 0; 3368 #else 3369 int clockFVal = 0; 3370 #endif 3371 static int isInW311Mode = 0; 3372 int fd; 3373 int rv; 3374 3375 if (! sh_check_attached(ARG_CMD(a), unit)) 3376 return CMD_FAIL; 3377 3378 /* Open PLL */ 3379 if ((fd = bcm_i2c_open(unit, I2C_PLL_0, 0,0)) < 0) { 3380 cli_out("%s: cannot open I2C device %s: %s\n", 3381 ARG_CMD(a), I2C_PLL_0, bcm_errmsg(fd)); 3382 return CMD_FAIL; 3383 } 3384 3385 /* When detecting P48, set clock mode automagically 3386 * to W311 3387 */ 3388 cli_out("Clock configuration: %s mode\n", 3389 isInW311Mode ? "W311" : "W229b"); 3390 3391 if (speed && !sal_strncasecmp(speed, "w311mode", sal_strlen(speed))) { 3392 isInW311Mode = 1; 3393 cli_out("Set W311 mode enable\n"); 3394 return CMD_OK; 3395 } 3396 if (isInW311Mode) { 3397 if(!speed){ 3398 cli_out("ERROR: no speed specified!\n"); 3399 return CMD_FAIL; 3400 } 3401 #ifdef COMPILER_HAS_DOUBLE 3402 clockFVal = atof( speed ) ; 3403 #else 3404 clockFVal = _shr_atof_exp10(speed, 6); 3405 #endif 3406 3407 /* Enable W311 mode */ 3408 rv = bcm_i2c_ioctl(unit, fd, I2C_PLL_SETW311, 3409 &isInW311Mode, sizeof(isInW311Mode)); 3410 if (rv < 0) { 3411 cli_out("ERROR: clock mode configuration failed: %s\n", 3412 bcm_errmsg(rv)); 3413 } 3414 3415 /* Set speed */ 3416 rv = bcm_i2c_ioctl(unit, fd, 0, &clockFVal, 0); 3417 if (rv < 0) { 3418 cli_out("ERROR: clock speed configuration failed: %s\n", 3419 bcm_errmsg(rv)); 3420 return CMD_FAIL; 3421 } 3422 #ifdef COMPILER_HAS_DOUBLE 3423 cli_out("Set %s clock to %2.2fMhz\n", 3424 I2C_PLL_0, clockFVal); 3425 #else 3426 cli_out("Set %s clock to %d.%02dMhz\n", 3427 I2C_PLL_0, 3428 INT_FRAC_2PT_4(clockFVal)); 3429 #endif 3430 } else { 3431 /* Use W229b access mode */ 3432 /* ioctl: will print out all values on bad speed value */ 3433 if (! speed ){ 3434 clockval = -1; 3435 } else{ 3436 clockval = parse_integer(speed) ; 3437 } 3438 3439 rv = bcm_i2c_ioctl(unit, fd, I2C_PLL_SETW311, 3440 &isInW311Mode, sizeof(isInW311Mode)); 3441 if (rv < 0) { 3442 cli_out("ERROR: clock mode configuration failed: %s\n", 3443 bcm_errmsg(rv)); 3444 } 3445 rv = bcm_i2c_ioctl(unit, fd, clockval, NULL, 0); 3446 if (rv < 0) { 3447 cli_out("ERROR: clock speed configuration failed: %s\n", 3448 bcm_errmsg(rv)); 3449 } 3450 } 3451 return CMD_OK ; 3452 } 3453 3454 3455 #ifdef SHADOW_SVK 3456 #define _SHADOW_OPEN_TEST(_u, _nm, _fl, _sp, _fd, _pf) \ 3457 do { \ 3458 if ((_fd = bcm_i2c_open(_u, _nm, _fl, _sp)) < 0) { \ 3459 _pf = 0; \ 3460 LOG_VERBOSE(BSL_LS_SOC_COMMON, \ 3461 (BSL_META_U(_u, \ 3462 "Could not open %s: %s\n"), \ 3463 _nm, bcm_errmsg(_fd))); \ 3464 } \ 3465 } while(0) 3466 3467 3468 #define _SHADOW_WRITE_TEST(_u, _f, _r, _d, _l, _nm, _rv, _pf) \ 3469 do { \ 3470 _rv = bcm_i2c_write(_u, _f, _r, &_d, _l); \ 3471 if (_rv < 0) { \ 3472 _pf = 0; \ 3473 LOG_VERBOSE(BSL_LS_SOC_COMMON, \ 3474 (BSL_META_U(_u, \ 3475 "%s writing failed: %s\n"), \ 3476 _nm, bcm_errmsg(_rv))); \ 3477 } \ 3478 } while (0) 3479 3480 3481 #define _SHADOW_READ_TEST(_u, _f, _r, _d, _l, _nm, _rv, _pf) \ 3482 do { \ 3483 _rv = bcm_i2c_read(_u, _f, _r, &_d, &_l); \ 3484 if (_rv < 0) { \ 3485 _pf = 0; \ 3486 LOG_VERBOSE(BSL_LS_SOC_COMMON, \ 3487 (BSL_META_U(_u, \ 3488 "%s reading failed: %s\n"), \ 3489 _nm, bcm_errmsg(_rv))); \ 3490 } \ 3491 } while (0) 3492 3493 #define _SHADOW_IOCTL_TEST(_u, _f, _op, _d, _l, _nm, _rv, _pf) \ 3494 do { \ 3495 _rv = bcm_i2c_ioctl(_u, _f, _op, &_d, _l); \ 3496 if (_rv < 0) { \ 3497 _pf = 0; \ 3498 LOG_VERBOSE(BSL_LS_SOC_COMMON, \ 3499 (BSL_META_U(_u, \ 3500 "%s ioctl failed: %s\n"), \ 3501 _nm, bcm_errmsg(_rv))); \ 3502 } \ 3503 } while (0) 3504 3505 #define _SHADOW_BIT_SET(_b) (1 << _b) 3506 3507 3508 #define _SHADOW_TEST_STATUS_PRINT(_pf) \ 3509 cli_out("%s\n", (_pf == 1) ? "PASSED" : "FAILED") 3510 3511 3512 STATIC cmd_result_t 3513 _bb_shadow_test(int unit, bb_type_t *baseboard) 3514 { 3515 int fd, dev, pass, rv = SOC_E_NONE; 3516 uint8 wrval, rdval; 3517 uint32 len; 3518 char *name; 3519 3520 pass = 1; 3521 cli_out(" Checking board id: "); 3522 _SHADOW_OPEN_TEST(unit, I2C_IOP_1, 0, 0, fd, pass); 3523 if (fd >= 0) { 3524 _SHADOW_READ_TEST(unit, fd, I2C_IOP_1_BRD_ID, 3525 rdval, len, I2C_IOP_1, rv, pass); 3526 } 3527 #if 0 3528 if (rv == SOC_E_NONE) { 3529 if (rdval != /* expected board id(s) */) { 3530 pass = 0; 3531 LOG_VERBOSE(BSL_LS_SOC_COMMON_I2C, 3532 (BSL_META_U(unit, 3533 "....Invalid board ID %x\n"), buf[0])); 3534 } 3535 } 3536 #endif 3537 _SHADOW_TEST_STATUS_PRINT(pass); 3538 cli_out(" Checking MAX127: "); 3539 pass = 1; 3540 _SHADOW_OPEN_TEST(unit, I2C_ADC_0, 0, 0, fd, pass); 3541 if (fd >= 0) { 3542 int i; 3543 int pass = 1; 3544 i2c_adc_t adc_data; 3545 for (i = 0; i < 8; i++) { 3546 _SHADOW_IOCTL_TEST(unit, fd, I2C_ADC_QUERY_CHANNEL, adc_data, i, 3547 I2C_ADC_0, rv, pass); 3548 } 3549 } 3550 _SHADOW_TEST_STATUS_PRINT(pass); 3551 for (dev = 0; dev < 2; dev++) { 3552 char *name; 3553 /* REMOVE THIS -testing only 3554 * name = (dev == 0) ? I2C_LPT_0 : I2C_LPT_1; */ 3555 name = (dev == 0) ? I2C_MUX_6 : I2C_MUX_7; 3556 pass = 1; 3557 cli_out(" Checking %s: ", name); 3558 _SHADOW_OPEN_TEST(unit, name, 0, 0, fd, pass); 3559 if (fd >= 0) { 3560 int i; 3561 /* 3562 * 5N bit march 3563 * Bit(0) -> Bit(7): write 0 3564 * Bit(0) -> Bit(7): read 0, write 1 3565 * Bit(7) -> Bit(0): read 1, write 0 3566 */ 3567 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3568 (BSL_META_U(unit, 3569 "\n1. Bit(0) -> Bit(7) write 0\n"))); 3570 for (i = 0; i < 8; i++) { 3571 wrval &= ~(_SHADOW_BIT_SET(i)); 3572 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3573 (BSL_META_U(unit, 3574 "writing 0x%02x "), wrval)); 3575 _SHADOW_WRITE_TEST(unit, fd, 0, wrval, 1, name, rv, pass); 3576 } 3577 wrval = 0; 3578 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3579 (BSL_META_U(unit, 3580 "2. Bit(0) -> Bit(7) read 0 write 1\n"))); 3581 for (i = 0; i < 8; i++) { 3582 _SHADOW_READ_TEST(unit, fd, 0, rdval, len, name, rv, pass); 3583 if (rv == SOC_E_NONE) { 3584 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3585 (BSL_META_U(unit, 3586 "read 0x%02x\n"), rdval)); 3587 if ((rdval & _SHADOW_BIT_SET(i)) != 3588 (wrval & _SHADOW_BIT_SET(i))) { 3589 pass = 0; 3590 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3591 (BSL_META_U(unit, 3592 "%s bit check failed 0x%02x 0x%02x\n"), 3593 name, (rdval & _SHADOW_BIT_SET(i)), 3594 (wrval & _SHADOW_BIT_SET(i)))); 3595 } 3596 } 3597 wrval |= _SHADOW_BIT_SET(i); 3598 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3599 (BSL_META_U(unit, 3600 "writing 0x%02x "), wrval)); 3601 _SHADOW_WRITE_TEST(unit, fd, 0, wrval, 1, name, rv, pass); 3602 } 3603 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3604 (BSL_META_U(unit, 3605 "3. Bit(7) -> Bit(0) read 1 write 0\n"))); 3606 for (i = 7; i > 0 ; i--) { 3607 _SHADOW_READ_TEST(unit, fd, 0, rdval, len, name, rv, pass); 3608 if (rv == SOC_E_NONE) { 3609 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3610 (BSL_META_U(unit, 3611 "read 0x%02x\n"), rdval)); 3612 if ((rdval & _SHADOW_BIT_SET(i)) != 3613 (wrval & _SHADOW_BIT_SET(i))) { 3614 pass = 0; 3615 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3616 (BSL_META_U(unit, 3617 "%s bit check failed 0x%02x 0x%02x\n"), 3618 name, (rdval & _SHADOW_BIT_SET(i)), 3619 (wrval & _SHADOW_BIT_SET(i)))); 3620 } 3621 } 3622 wrval &= ~(_SHADOW_BIT_SET(i)); 3623 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3624 (BSL_META_U(unit, 3625 "writing 0x%02x "), wrval)); 3626 _SHADOW_WRITE_TEST(unit, fd, 0, wrval, 1, name, rv, pass); 3627 _SHADOW_READ_TEST(unit, fd, 0, rdval, len, name, rv, pass); 3628 if (rv == SOC_E_NONE) { 3629 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3630 (BSL_META_U(unit, 3631 "read 0x%02x\n"), rdval)); 3632 if ((rdval & ~(_SHADOW_BIT_SET(i))) != 3633 (wrval & ~(_SHADOW_BIT_SET(i)))) { 3634 pass = 0; 3635 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3636 (BSL_META_U(unit, 3637 "%s bit check failed 0x%02x 0x%02x\n"), 3638 name, (rdval & _SHADOW_BIT_SET(i)), 3639 (wrval & _SHADOW_BIT_SET(i)))); 3640 } 3641 } 3642 } 3643 } 3644 _SHADOW_TEST_STATUS_PRINT(pass); 3645 } 3646 pass = 1; 3647 for (dev = 0; dev < 2; dev++) { 3648 name = (dev == 0) ? I2C_IOP_1 : I2C_IOP_0; 3649 3650 cli_out(" Checking %s: ", name); 3651 _SHADOW_OPEN_TEST(unit, name, 0, 0, fd, pass); 3652 if (fd >= 0) { 3653 int i; 3654 /* 3655 * Just verify the ports are readable as several ports 3656 * are read only. Special care is required for the XON_XOFF 3657 * pins, which are overloaded onto EB_ADDR. These pins are 3658 * connected to both the FPGA and one of the 9505 ports 3659 * (addr 0x25 port 0). This port can only drive these pins 3660 * while the device is in PCIE or VLI mode. The FPGA will 3661 * tri-state these pins when in PCIE or VLI. Make sure not 3662 * to drive these pins from the 9505 while in EB3 mode in 3663 * order to avoid potential damage to the FPGA I/0. 3664 */ 3665 for (i = 0; i < 5; i++) { 3666 _SHADOW_READ_TEST(unit, fd, i, rdval, len, name, rv, pass); 3667 } 3668 } 3669 _SHADOW_TEST_STATUS_PRINT(pass); 3670 } 3671 3672 return CMD_OK; 3673 } 3674 3675 STATIC cmd_result_t 3676 _bb_test(int unit, bb_type_t *baseboard) 3677 { 3678 if (!baseboard) { 3679 return CMD_FAIL; 3680 } 3681 if (!SOC_IS_SHADOW(unit)) { 3682 return CMD_NOTIMPL; 3683 } 3684 3685 return _bb_shadow_test(unit, baseboard); 3686 } 3687 #endif /* SHADOW_SVK */ 3688 3689 /* 3690 * I2C specific commands for Baseboards which allow for control of 3691 * clocks, voltages and provide other measurements like power, 3692 * temperature, thickness, etc. 3693 */ 3694 3695 /* 3696 * Tunable voltage parameters for P48 and Gen2 baseboards 3697 * This table encodes DAC/ADC VCC chip control and comm data. 3698 */ 3699 typedef 3700 struct bb_vconfig_params{ 3701 int cal_idx; /* DAC calibration table index: See ltc1427.c */ 3702 char *function; /* Voltage source to configure */ 3703 uint8 mux; /* MUXSEL (lpt0) value */ 3704 char *adc; /* ADC device name */ 3705 int chan; /* A/D channel # */ 3706 char *dac; /* DAC Device name */ 3707 int flags; /* DAC calibrated, power computation IDs */ 3708 } bb_vparams_t; 3709 3710 /* Defines for the bb_vparams_t flags field */ 3711 #define DAC_UNCALIBRATED 0x00000000 3712 #define DAC_CALIBRATED 0x00000001 3713 #define PWR_CORE_A_SRC 0x00000002 3714 #define PWR_CORE_A_DROP 0x00000004 3715 #define PWR_CORE_B_SRC 0x00000008 3716 #define PWR_CORE_B_DROP 0x00000010 3717 #define PWR_PHY_SRC 0x00000020 3718 #define PWR_PHY_DROP 0x00000040 3719 #define PWR_CORECAL_SRC 0x00000080 3720 #define PWR_CORECAL_DROP 0x00000100 3721 #define PWR_PHYCAL_SRC 0x00000200 3722 #define PWR_PHYCAL_DROP 0x00000400 3723 #define PWR_IOCAL_SRC 0x00000800 3724 #define PWR_IOCAL_DROP 0x00001000 3725 #define PWR_IO_SRC 0x00002000 3726 #define PWR_IO_DROP 0x00004000 3727 #define PWR_CORE_A_LOAD 0x00008000 3728 #define PWR_CORE_B_LOAD 0x00010000 3729 #define PWR_PHY_LOAD 0x00020000 3730 #define PWR_DAC_IO_SRC (0x40000|DAC_CALIBRATED) /*LTC ADC/DAC Device */ 3731 #define PWR_DAC_IO_PMBUS (0x80000|DAC_CALIBRATED) /*PMBUS ADC/DAC Device */ 3732 3733 /* 3734 * Current configuration table 3735 */ 3736 typedef 3737 struct bb_current_config_s{ 3738 char *function; /* Current sourec to measure. */ 3739 char *adc; /* ADC device name */ 3740 int chan; /* A/D channel # */ 3741 int sens; /* Sensitivity in mV/A */ 3742 int flags; /* Flags for expansion */ 3743 } bb_current_config_t; 3744 3745 /* 3746 * Current configuration table 3747 */ 3748 typedef 3749 struct bb_sequence_config_s{ 3750 char *function; /* Voltage source to configure sequence*/ 3751 uint8 mux; /* MUXSEL (lpt0) value */ 3752 char *dac; /* DAC Device name */ 3753 int chan; /* A/D channel # */ 3754 int max; /* maximum sequence value in ms */ 3755 int min; /* minimum sequence value in ms */ 3756 int flags; /* Status ID:Future Use */ 3757 } bb_sequence_config_t; 3758 3759 3760 /* 3761 * Clock chip configuration table for all clock sources. 3762 * This table encodes the necessary data to communicate with every w311 3763 */ 3764 typedef struct bb_clock_config_s{ 3765 char *name; /* Clock output name */ 3766 char *alias; /* Clock output name (alias) */ 3767 char *device; /* I2C device name */ 3768 int unit; /* PCI Device */ 3769 uint8 mux; /* BBMUX (lpt0) value; 0xFF means no MUX control needed */ 3770 int xpll; /* For CY22393 (& CY22150), the PLL (or clock) to modify */ 3771 } bb_clock_config_t; 3772 3773 3774 3775 /* For P48 (G3) and BaseBoard/P48 command, we have a separate 3776 * Clock chip table since we are using W311's in a Mux'd fashion 3777 * which is specific to just this board. Other boards use the new 3778 * Cypress CY22393 clock chip and should use the "xclocks" command. 3779 * INDEXED_BY_BOARD_TYPE 3780 */ 3781 bb_clock_config_t 3782 bb_clocks[NUM_BOARD_TYPES][MAX_CLOCKS_PER_BOARD] = { 3783 /* G5, Single (non-MUXed) CY22150, 2 clocks */ 3784 {{"Core", NULL, "clk0", 0, 0xFF,I2C_XPLL_CORE}, 3785 {"PCI", NULL, "clk0", 0, 0xFF,I2C_XPLL_PCI}, 3786 }, 3787 /* G13, Single (non-MUXed) CY22393, 3 clocks */ 3788 {{"Test", NULL, "clk0", 0, 0xFF,I2C_XPLL_PLL3}, 3789 {"Core", "Ref133", "clk0", 0, 0xFF,I2C_XPLL_PLL2}, 3790 {"PCI", NULL, "clk0", 0, 0xFF,I2C_XPLL_PLL1}, 3791 }, 3792 {{0}}, /* G15, uses synth command for clock control */ 3793 {{0}}, /* G16, uses synth command for clock control */ 3794 {{0}}, /* G17, uses synth command for clock control */ 3795 {{0}}, /* G18, uses synth command for clock control */ 3796 {{0}}, /* G19, uses synth command for clock control */ 3797 {{0}}, /* G20, uses synth command for clock control */ 3798 {{0}}, /* G21, uses synth command for clock control */ 3799 {{0}}, /* G22, uses synth command for clock control */ 3800 {{0}}, /* G23, uses synth command for clock control */ 3801 {{0}}, /* G24, uses synth command for clock control */ 3802 {{0}}, /* G25, uses synth command for clock control */ 3803 {{0}}, /* G26, uses synth command for clock control */ 3804 {{0}}, /* G27, uses synth command for clock control */ 3805 {{0}}, /* G28, uses synth command for clock control */ 3806 {{0}}, /* G29, uses synth command for clock control */ 3807 {{0}}, /* G30, uses synth command for clock control */ 3808 {{0}}, /* G31, uses synth command for clock control */ 3809 {{0}}, /* G33, uses synth command for clock control */ 3810 {{0}}, /* G34, uses synth command for clock control */ 3811 {{0}}, /* G35, uses synth command for clock control */ 3812 {{0}}, /* ENG */ 3813 {{0}} /* UNK */ 3814 }; 3815 3816 /* 3817 * bb_clock_len[] table contains the number of configurable 3818 * clocks available for each board type. 3819 * Used by cmd_bb() for "Baseboard" and "P48" commands. 3820 * A zero disables the clock function for Baseboard/P48. 3821 * INDEXED_BY_BOARD_TYPE 3822 */ 3823 int bb_clock_len[NUM_BOARD_TYPES] = { 3824 2, /* G5 */ 3825 3, /* G13 */ 3826 0, /* G15 */ /* Uses synth command */ 3827 0, /* G16 */ /* Uses synth command */ 3828 0, /* G17 */ /* Uses synth command */ 3829 0, /* G18 */ /* Uses synth command */ 3830 0, /* G19 */ /* Uses synth command */ 3831 0, /* G20 */ /* Uses synth command */ 3832 0, /* G21 */ /* Uses synth command */ 3833 0, /* G22 */ /* Uses synth command */ 3834 0, /* G23 */ /* Uses synth command */ 3835 0, /* G24 */ /* Uses synth command */ 3836 0, /* G25 */ /* Uses synth command */ 3837 0, /* G26 */ /* Uses synth command */ 3838 0, /* G27 */ /* Uses synth command */ 3839 0, /* G28 */ /* Uses synth command */ 3840 0, /* G29 */ /* Uses synth command */ 3841 0, /* G30 */ /* Uses synth command */ 3842 0, /* G31 */ /* Uses synth command */ 3843 0, /* G33 */ /* Uses synth command */ 3844 0, /* G34 */ /* Uses synth command */ 3845 0, /* G35 */ /* Uses synth command */ 3846 0, /* ENG */ 3847 0 /* UNK */ 3848 }; 3849 3850 3851 /* Calibration table for DAC/ADC Voltage parameters. 3852 * Used to calibrate the DAC->PowerSupply->ADC loop. 3853 * NOTE: Turbo is special (MAX dacval = min voltage) 3854 * INDEXED_BY_BOARD_TYPE 3855 * NOTE: For each board type, the order of each DAC entry 3856 * must match that of their associated entries in 3857 * the bb_vs_config table. 3858 */ 3859 /* On HUMV/Bradley/GW slow part, max and min should be set to 960 and 3860 * 64 to prevent the system crashes during voltage calibration. 3861 */ 3862 #define HVSPO 64 /* HUMV Slow Part Offset */ 3863 /* Triumph3 56640 board core voltage calibration tweak 3864 */ 3865 #define TR3_640_MAX_ADJUST 0x3 /* TR3 56640 board core voltage limit */ 3866 #define TR3_TCAM_ADJUST 0x10 /* TR3 56640 board TCAM voltage is .9V, not 1V */ 3867 /* Trident2+ board core voltage calibration tweak 3868 */ 3869 #define TD2P_MAX_ADJUST -0x1 3870 #define TD2P_MAX_ANALOG_ADJUST -0x2 3871 3872 /* idx, name, max, min, step, dac_last, dac_min, dac_max, dac_mid, dac_use_max */ 3873 static dac_calibrate_t 3874 dac_params[NUM_BOARD_TYPES][MAX_VS_CONFIG_PER_BOARD] = { 3875 /* Hercules: aka G5 */ 3876 {{0,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3877 {1,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3878 {2,"Core",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3879 {0},{0}}, 3880 /* Firebolt SDK design: aka G13 */ 3881 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3882 {1,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3883 {2,"3.3",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3884 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3885 {0}}, 3886 /* Goldwing SDK design: aka G15 */ 3887 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3888 {1,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3889 {0},{0},{0}}, 3890 /* Bradley 1G SDK design: aka G16 */ 3891 {{0,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3892 {1,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3893 {2,"Core",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3894 {3,"1.2",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3895 {0}}, 3896 /* Bradley SDK design: aka G17 */ 3897 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3898 {1,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3899 {0},{0},{0}}, 3900 /* Raptor SDK design: aka G18 */ 3901 {{0,"1.2",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3902 {1,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3903 {2,"PHY",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3904 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3905 {0}}, 3906 /* Raven SDK design: aka G19 */ 3907 {{0,"1.2",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3908 {1,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3909 {2,"PHY",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3910 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3911 {0}}, 3912 /* Triumph SDK design: aka G20 */ 3913 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3914 {1,"1.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3915 {2,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3916 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3917 {0}}, 3918 /* Scorpion SDK design : aka G21 */ 3919 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3920 {1,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3921 {0},{0},{0}}, 3922 /* Apollo SDK design: aka G22 */ 3923 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3924 {1,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3925 {2,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3926 {0},{0}}, 3927 3928 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3929 {1,"1.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3930 {2,"2.5",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3931 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3932 {0}}, 3933 /* Trident SDK design: aka G24 */ 3934 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3935 {1,"PHY",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3936 {2,"Analog",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3937 {0},{0}}, 3938 /* Titan SDK design: aka G25 */ 3939 {{0,"Core",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3940 {1,"3.3",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3941 {2,"5.0",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3942 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3943 {0}}, 3944 /* Hurricane SDK design: aka G26 */ 3945 {{0,"Core", -1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3946 {1,"PHY", -1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3947 {2,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL+HVSPO,LTC1427_MAX_DACVAL-HVSPO,LTC1427_MID_DACVAL,1}, 3948 {0},{0}}, 3949 /* Shadow SDK design: aka G27*/ 3950 /* Shadow the voltage calibration window is reduced, 128 to 896, A2 parts 3951 * were failing when Hurricane based calibration windown (64 to 960) was 3952 * used */ 3953 {{0,"Core",1.198,.805,0,0,LTC1427_MIN_DACVAL+((5*HVSPO)+50),LTC1427_MAX_DACVAL-((5*HVSPO)+50),LTC1427_MID_DACVAL,1}, 3954 {1,"1.0",1.198,.805,0,0,LTC1427_MIN_DACVAL+((5*HVSPO)+50),LTC1427_MAX_DACVAL-((5*HVSPO)+50),LTC1427_MID_DACVAL,1}, 3955 {2,"1.8",2.063,1.538,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3956 {3,"3.3",3.645,2.980,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3957 {0}}, 3958 /* Katana SDK design: aka G28 */ 3959 {{0,"Core", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3960 {1,"3.3", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3961 {2,"1.5", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3962 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3963 {0}}, 3964 /* Enduro-2 SDK design: aka G29 */ 3965 {{0,"Core", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3966 {1,"Analog", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3967 {3,"3.3",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3968 {0},{0}}, 3969 /* Stardust-2 SDK design: aka G30 */ 3970 {{0,"Core", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3971 {1,"3.3",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3972 {3,"Analog", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3973 {0},{0}}, 3974 /* Enduro-2 SDK design: aka G31 */ 3975 {{0,"Core", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3976 {1,"3.3", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3977 {2,"1.5", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3978 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3979 {0}}, 3980 /* Trident SDK design: aka G33 */ 3981 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3982 {1,"PHY",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3983 {2,"Analog",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3984 {0},{0}}, 3985 /* Triumph3 Legacy SDK design: aka G34 */ 3986 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3987 {1,"3.3", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3988 {2,"Analog",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3989 {0},{0}}, 3990 /* Triumph3 SDK design: aka G35 */ 3991 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL-TR3_640_MAX_ADJUST,ADP4000_MID_DACVAL,1}, 3992 {1,"3.3", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3993 {2,"1.8", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 3994 {3,"Analog",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 3995 {4,"TCAM",-1,1,0,0,ADP4000_MIN_DACVAL+TR3_TCAM_ADJUST,ADP4000_MAX_DACVAL+TR3_TCAM_ADJUST,ADP4000_MID_DACVAL+TR3_TCAM_ADJUST,1}, {0}}, 3996 3997 /* Caladan3 48G SVK : aka G36 */ 3998 {{0,"Core",-1,1,0,0,SMM665_CORE_MIN,SMM665_CORE_MAX, SMM665_CORE_MID,1}, 3999 {1,"Analog",-1,1,0,0,SMM665_ANLG_MIN,SMM665_ANLG_MAX,SMM665_ANLG_MID,1}, 4000 {2,"1.5", -1,1,0,0,SMM665_1_5_MIN,SMM665_1_5_MAX,SMM665_1_5_MID,1}, 4001 {3,"3.3", -1,1,0,0,SMM665_3_3_MIN,SMM665_3_3_MAX,SMM665_3_3_MID,1}, 4002 {4,"1.2", -1,1,0,0,SMM665_1_2_MIN,SMM665_1_2_MAX,SMM665_1_2_MID,1}, 4003 {5,"Tcam", -1,1,0,0,SMM665_TCAM_MIN,SMM665_TCAM_MAX,SMM665_TCAM_MID,1}, 4004 }, 4005 4006 /* Caladan3 100G SVK : aka G37 */ 4007 {{0,"Core",-1,1,0,0,SMM665_CORE_MIN,SMM665_CORE_MAX, SMM665_CORE_MID,1}, 4008 {1,"Analog",-1,1,0,0,SMM665_ANLG_MIN,SMM665_ANLG_MAX,SMM665_ANLG_MID,1}, 4009 {2,"1.5", -1,1,0,0,SMM665_1_5_MIN,SMM665_1_5_MAX,SMM665_1_5_MID,1}, 4010 {3,"3.3", -1,1,0,0,SMM665_3_3_MIN,SMM665_3_3_MAX,SMM665_3_3_MID,1}, 4011 {4,"1.2", -1,1,0,0,SMM665_1_2_MIN,SMM665_1_2_MAX,SMM665_1_2_MID,1}, 4012 {5,"Tcam", -1,1,0,0,SMM665_TCAM_MIN,SMM665_TCAM_MAX,SMM665_TCAM_MID,1}, 4013 }, 4014 4015 /* Trident2 SVK : aka G38 */ 4016 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL-TR3_640_MAX_ADJUST,ADP4000_MID_DACVAL,1}, 4017 {1,"Analog",-1,1,0,0,ADP4000_ANLG_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 4018 {2,"3.3",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 4019 }, 4020 /* Trident2 DVT : aka G39 */ 4021 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL-TR3_640_MAX_ADJUST,ADP4000_MID_DACVAL,1}, 4022 {1,"Analog",-1,1,0,0,ADP4000_ANLG_MIN_DACVAL,ADP4000_MAX_DACVAL,ADP4000_MID_DACVAL,1}, 4023 {2,"3.3", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 4024 }, 4025 /* Katana2 design: aka G40 */ 4026 {{0,"Core", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 4027 {1,"3.3", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 4028 {2,"1.5", -1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 4029 {3,"Analog",-1,1,0,0,LTC1427_MIN_DACVAL,LTC1427_MAX_DACVAL,LTC1427_MID_DACVAL,1}, 4030 {0}}, 4031 /* Greyhound SVK : aka G41 */ 4032 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4033 {1,"2.5V",-1,1,0,0,LTC3880_2_5V_MAX_DACVAL,LTC3880_2_5V_MIN_DACVAL,LTC3880_2_5V_MID_DACVAL,1}, 4034 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4035 {3,"1.5V",-1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_5V_MID_DACVAL,1}, 4036 {4,"Core",-1,1,0,0,LTC3880_MIN_DACVAL,LTC3880_MAX_DACVAL,LTC3880_MID_DACVAL,1}, 4037 {5,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4038 }, 4039 /* Tomahawk SVK : aka G42 */ 4040 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL-TR3_640_MAX_ADJUST,ADP4000_MID_DACVAL,1}, 4041 {1,"Analog",-1,1,0,0,LTC3882_ANLG_MAX_DACVAL,LTC3882_ANLG_MIN_DACVAL,LTC3882_ANLG_MID_DACVAL,1}, 4042 {2,"3.3",-1,1,0,0,LTC3882_3_3V_MAX_DACVAL,LTC3882_3_3V_MIN_DACVAL,LTC3882_3_3V_MID_DACVAL,1}, 4043 {3,"1.25",-1,1,0,0,LTC3880_1_25V_MAX_DACVAL,LTC3880_1_25V_MIN_DACVAL,LTC3880_1_25V_MID_DACVAL,1}, 4044 {4,"1.8",-1,1,0,0,LTC3880_1_8V_MAX_DACVAL,LTC3880_1_8V_MIN_DACVAL,LTC3880_1_8V_MID_DACVAL,1}, 4045 }, 4046 /* Trident2+ : aka G43 */ 4047 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL+TD2P_MAX_ADJUST,ADP4000_MID_DACVAL,1}, 4048 {1,"Analog",-1,1,0,0,ADP4000_ANLG_MIN_DACVAL,ADP4000_MAX_DACVAL+TD2P_MAX_ANALOG_ADJUST,ADP4000_MID_DACVAL,1}, 4049 {2,"3.3",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL+TD2P_MAX_ADJUST,ADP4000_MID_DACVAL,1}, 4050 }, 4051 4052 /* Trident2+ 100G: aka G44 */ 4053 {{0,"Core",-1,1,0,0,ADP4000_MIN_DACVAL,ADP4000_MAX_DACVAL-TR3_640_MAX_ADJUST,ADP4000_MID_DACVAL,1}, 4054 {1,"Analog",-1,1,0,0,LTC3882_ANLG_MAX_DACVAL,LTC3882_ANLG_MIN_DACVAL,LTC3882_ANLG_MID_DACVAL,1}, 4055 {2,"3.3",-1,1,0,0,LTC3882_3_3V_MAX_DACVAL,LTC3882_3_3V_MIN_DACVAL,LTC3882_3_3V_MID_DACVAL,1}, 4056 {3,"1.25",-1,1,0,0,LTC3880_1_25V_MAX_DACVAL,LTC3880_1_25V_MIN_DACVAL,LTC3880_1_25V_MID_DACVAL,1}, 4057 {4,"1.8",-1,1,0,0,LTC3880_1_8V_MAX_DACVAL,LTC3880_1_8V_MIN_DACVAL,LTC3880_1_8V_MID_DACVAL,1}, 4058 }, 4059 /* Greyhound SVK : aka G45 */ 4060 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4061 {1,"2.5V",-1,1,0,0,LTC3880_2_5V_MAX_DACVAL,LTC3880_2_5V_MIN_DACVAL,LTC3880_2_5V_MID_DACVAL,1}, 4062 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4063 {3,"1.5V",-1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_5V_MID_DACVAL,1}, 4064 {4,"Core",-1,1,0,0,LTC3880_MIN_DACVAL,LTC3880_MAX_DACVAL,LTC3880_MID_DACVAL,1}, 4065 {5,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4066 }, 4067 /* Greyhound SVK : aka G46 */ 4068 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4069 {1,"2.5V",-1,1,0,0,LTC3880_2_5V_MAX_DACVAL,LTC3880_2_5V_MIN_DACVAL,LTC3880_2_5V_MID_DACVAL,1}, 4070 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4071 {3,"1.5V",-1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_5V_MID_DACVAL,1}, 4072 {4,"Core",-1,1,0,0,LTC3880_MIN_DACVAL,LTC3880_MAX_DACVAL,LTC3880_MID_DACVAL,1}, 4073 {5,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4074 }, 4075 /* Greyhound SVK : aka G47 */ 4076 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4077 {1,"2.5V",-1,1,0,0,LTC3880_2_5V_MAX_DACVAL,LTC3880_2_5V_MIN_DACVAL,LTC3880_2_5V_MID_DACVAL,1}, 4078 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4079 {3,"1.5V",-1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_5V_MID_DACVAL,1}, 4080 {4,"Core",-1,1,0,0,LTC3880_MIN_DACVAL,LTC3880_MAX_DACVAL,LTC3880_MID_DACVAL,1}, 4081 {5,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4082 }, 4083 /* Saber2 design: aka G48 */ 4084 {{0,"Core", -1,1,0,0,LTC3880_0_6V_MIN_DACVAL,LTC3880_0_6V_MAX_DACVAL,LTC3880_0_6V_MID_DACVAL,1}, 4085 {1,"DDR", -1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_5V_MID_DACVAL,1}, 4086 {2,"IPROC_CORE",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4087 {3,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL, LTC3880_1V_MID_DACVAL,1}, 4088 {4,"3.3", -1,1,0,0,LTC3882_3_3V_MAX_DACVAL,LTC3882_3_3V_MIN_DACVAL, LTC3882_3_3V_MID_DACVAL,1}, 4089 {5,"1.8", -1,1,0,0,LTC3880_1_8V_MAX_DACVAL,LTC3880_1_8V_MIN_DACVAL, LTC3880_1_8V_MID_DACVAL,1}, 4090 }, 4091 /* Tomahawk PVT : aka G49 */ 4092 {{0,"Core",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4093 {1,"ANA1",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4094 {2,"ANA2",-1,1,0,0,LTC388x_2_5V_DACVAL,LTC388x_1_2V_DACVAL,LTC388x_1_8V_DACVAL,1}, 4095 {3,"3.3V",-1,1,0,0,LTC388x_3_6V_DACVAL,LTC388x_1_2V_DACVAL,LTC388x_2_5V_DACVAL,1}, 4096 {4,"DDR_15",-1,1,0,0,LTC388x_2_5V_DACVAL,LTC388x_1_2V_DACVAL,LTC388x_1_5V_DACVAL,1}, 4097 {5,"SP1",-1,1,0,0,LTC388x_3_6V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4098 {6,"SP2",-1,1,0,0,LTC388x_3_6V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_3_3V_DACVAL,1}, 4099 {7,"DDR_Core",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4100 {8,"SP3",-1,1,0,0,LTC388x_3_6V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_3_3V_DACVAL,1}, 4101 }, 4102 /* Apache/Maverick aka G50 */ 4103 {{0,"Core",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4104 {1,"Analog",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4105 {2,"3.3V",-1,1,0,0,LTC388x_3_6V_DACVAL,LTC388x_3_0V_DACVAL,LTC388x_3_3V_DACVAL,1}, 4106 }, 4107 /* FireBolt5 aka G51 */ 4108 {{0,"Core",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4109 {1,"Analog",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4110 {2,"1.0V_PHY",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4111 {3,"3.3V",-1,1,0,0,LTC388x_3_4V_DACVAL,LTC388x_3_2V_DACVAL,LTC388x_3_3V_DACVAL,1}, 4112 }, 4113 /* HR3 SVK(BCM56160K) : aka G52 */ 4114 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4115 {1,"1.0V",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4116 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4117 {3,"1.2V",-1,1,0,0,LTC3880_1_2V_MAX_DACVAL,LTC3880_1_2V_MIN_DACVAL,LTC3880_1_2V_MID_DACVAL,1}, 4118 {4,"Core",-1,1,0,0,LTC3880_0_549V_MAX_DACVAL,LTC3880_0_549V_MIN_DACVAL,LTC3880_0_549V_MID_DACVAL,1}, 4119 {5,"Analog",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4120 }, 4121 /* HR3 SVK(BCM53444K) : aka G53 */ 4122 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4123 {1,"1.0V",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4124 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4125 {3,"1.5V",-1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_25V_MID_DACVAL,1}, 4126 {4,"Core",-1,1,0,0,LTC3880_0_549V_MAX_DACVAL,LTC3880_0_549V_MIN_DACVAL,LTC3880_0_549V_MID_DACVAL,1}, 4127 {5,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4128 }, 4129 /* HR3 SVK(BCM53434K) : aka G54 */ 4130 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4131 {1,"1.0V",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4132 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4133 {3,"1.5V",-1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_5V_MID_DACVAL,1}, 4134 {4,"Core",-1,1,0,0,LTC3880_0_549V_MAX_DACVAL,LTC3880_0_549V_MIN_DACVAL,LTC3880_0_549V_MID_DACVAL,1}, 4135 {5,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4136 }, 4137 /* BCM56160D : aka G55 */ 4138 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4139 {1,"1.0V",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4140 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4141 {3,"1.5V",-1,1,0,0,LTC3880_1_5V_MIN_DACVAL,LTC3880_1_5V_MAX_DACVAL,LTC3880_1_5V_MID_DACVAL,1}, 4142 {4,"Core",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_0_549V_MID_DACVAL,1}, 4143 {5,"Analog",-1,1,0,0,LTC3880_1V_MIN_DACVAL,LTC3880_1V_MAX_DACVAL,LTC3880_1V_MID_DACVAL,1}, 4144 }, 4145 /* Metrolite design: aka G56 */ 4146 {{0,"Core", -1,1,0,0,LTC2974_1_5V_DACVAL, LTC2974_0_6V_DACVAL, LTC2974_1V_DACVAL,1}, 4147 {1,"Analog",-1,1,0,0,LTC2974_1_1V_DACVAL, LTC2974_0_9V_DACVAL, LTC2974_1V_DACVAL,1}, 4148 {2,"3.3", -1,1,0,0,LTC2974_3_63V_DACVAL, LTC2974_2_97V_DACVAL, LTC2974_3_3V_DACVAL,1}, 4149 {3,"1.8", -1,1,0,0,LTC2974_1_98V_DACVAL, LTC2974_1_62V_DACVAL, LTC2974_1_8V_DACVAL,1}, 4150 }, 4151 /* Tomahawk2 design: aka G57 */ 4152 {{0,"Analog",-1,1,0,0,LTC2974_1V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_0_8V_DACVAL,1}, 4153 {1,"1.2",-1,1,0,0,LTC2974_1_35V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_1_2V_DACVAL,1}, 4154 {2,"1.8",-1,1,0,0,LTC2974_1_95V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_1_8V_DACVAL,1}, 4155 {3,"3.3",-1,1,0,0,LTC2974_3_4V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_3_3V_DACVAL,1}, 4156 }, 4157 /* Greyhound2 design: aka G58 */ 4158 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4159 {1,"1.25V",-1,1,0,0,LTC3880_1_250V_MAX_DACVAL,LTC3880_1_250V_MIN_DACVAL,LTC3880_1_250V_MID_DACVAL,1}, 4160 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4161 {3,"1.2V",-1,1,0,0,LTC3880_1_2V_MAX_DACVAL,LTC3880_1_2V_MIN_DACVAL,LTC3880_1_2V_MID_DACVAL,1}, 4162 {4,"Core",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4163 {5,"Analog",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4164 }, 4165 /* Greyhound2 design: aka G59 */ 4166 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4167 {1,"1.25V",-1,1,0,0,LTC3880_1_250V_MAX_DACVAL,LTC3880_1_250V_MIN_DACVAL,LTC3880_1_250V_MID_DACVAL,1}, 4168 {2,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4169 {3,"1.5V",-1,1,0,0,LTC3880_1_50V_MAX_DACVAL,LTC3880_1_50V_MIN_DACVAL,LTC3880_1_50V_MID_DACVAL,1}, 4170 {4,"Core",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4171 {5,"Analog",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4172 }, 4173 /* Trident3/Maverick2 design: aka G60 */ 4174 {{0,"Analog",-1,1,0,0,LTC2974_1V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_0_8V_DACVAL,1}, 4175 {1,"1.2",-1,1,0,0,LTC2974_1_35V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_1_2V_DACVAL,1}, 4176 {2,"1.8",-1,1,0,0,LTC2974_1_95V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_1_8V_DACVAL,1}, 4177 {3,"3.3",-1,1,0,0,LTC2974_3_4V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_3_3V_DACVAL,1}, 4178 }, 4179 /* MONTEREY aka G61 */ 4180 {{0,"Core",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4181 {1,"Analog",-1,1,0,0,LTC388x_1_5V_DACVAL,LTC388x_0_6V_DACVAL,LTC388x_1V_DACVAL,1}, 4182 {2,"3.3V",-1,1,0,0,LTC388x_3_6V_DACVAL,LTC388x_3_0V_DACVAL,LTC388x_3_3V_DACVAL,1}, 4183 {3,"1.2V",-1,1,0,0,LTC2974_1_35V_DACVAL,LTC2974_1_1V_DACVAL,LTC2974_1_2V_DACVAL,1}, 4184 {4,"3.3dut",-1,1,0,0,LTC2974_3_63V_DACVAL,LTC2974_2_97V_DACVAL,LTC2974_3_3V_DACVAL,1}, 4185 {5,"1.8V",-1,1,0,0,LTC2974_1_98V_DACVAL,LTC2974_1_62V_DACVAL,LTC2974_1_8V_DACVAL,1}, 4186 {6,"1.2mdio",-1,1,0,0,LTC2974_1_35V_DACVAL,LTC2974_1_1V_DACVAL,LTC2974_1_2V_DACVAL,1}, 4187 }, 4188 /* Wolfhound2 design: aka G62 */ 4189 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4190 {1,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4191 {2,"1.2V",-1,1,0,0,LTC3880_1_2V_MAX_DACVAL,LTC3880_1_2V_MIN_DACVAL,LTC3880_1_2V_MID_DACVAL,1}, 4192 {3,"Core",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4193 {4,"Analog",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4194 }, 4195 /* Wolfhound2 design: aka G63 */ 4196 {{0,"3.3V",-1,1,0,0,LTC3880_3_3V_MIN_DACVAL,LTC3880_3_3V_MAX_DACVAL,LTC3880_3_3V_MID_DACVAL,1}, 4197 {1,"1.8V",-1,1,0,0,LTC3880_1_80V_MAX_DACVAL,LTC3880_1_80V_MIN_DACVAL,LTC3880_1_80V_MID_DACVAL,1}, 4198 {2,"1.5V",-1,1,0,0,LTC3880_1_50V_MAX_DACVAL,LTC3880_1_50V_MIN_DACVAL,LTC3880_1_50V_MID_DACVAL,1}, 4199 {3,"Core",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4200 {4,"Analog",-1,1,0,0,LTC3880_1_0V_MAX_DACVAL,LTC3880_1_0V_MIN_DACVAL,LTC3880_1_0V_MID_DACVAL,1}, 4201 }, 4202 /* Tomahawk3 design: aka G64 */ 4203 {{0,"MDIO",-1,1,0,0,LTC2974_1V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_0_8V_DACVAL,1}, 4204 {1,"1.2",-1,1,0,0,LTC2974_1_35V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_1_2V_DACVAL,1}, 4205 {2,"1.8",-1,1,0,0,LTC2974_1_95V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_1_8V_DACVAL,1}, 4206 {3,"3.3",-1,1,0,0,LTC2974_3_4V_DACVAL,LTC2974_0_6V_DACVAL,LTC2974_3_3V_DACVAL,1}, 4207 }, 4208 /* Helix5 design: aka G65 */ 4209 {{0,"Core",-1,1,0,0,LTC388x_1_04V_DACVAL,LTC388x_0_72V_DACVAL,LTC388x_0_88V_DACVAL,1}, 4210 {1,"Analog",-1,1,0,0,LTC388x_0_94V_DACVAL,LTC388x_0_66V_DACVAL,LTC388x_0_80V_DACVAL,1}, 4211 {2,"0.88V",-1,1,0,0,LTC2974_0_97V_DACVAL,LTC2974_0_79V_DACVAL,LTC2974_0_88V_DACVAL,1}, 4212 {3,"3.3V_Dut",-1,1,0,0,LTC2974_3_63V_DACVAL,LTC2974_2_97V_DACVAL,LTC2974_3_3V_DACVAL,1}, 4213 {4,"2.5V",-1,1,0,0,LTC2974_2_75V_DACVAL,LTC2974_2_25V_DACVAL,LTC2974_2_50V_DACVAL,1}, 4214 {5,"VDD_MDIO",-1,1,0,0,LTC2974_1_32V_DACVAL,LTC2974_1_08V_DACVAL,LTC2974_1_2V_DACVAL,1}, 4215 {6,"1.8V",-1,1,0,0,LTC2974_1_98V_DACVAL,LTC2974_1_62V_DACVAL,LTC2974_1_8V_DACVAL,1}, 4216 {7,"1.2V",-1,1,0,0,LTC2974_1_32V_DACVAL,LTC2974_1_08V_DACVAL,LTC2974_1_2V_DACVAL,1}, 4217 {8,"3.3V_Dut",-1,1,0,0,LTC2974_3_80V_DACVAL,LTC2974_2_71V_DACVAL,LTC2974_3_3V_DACVAL,1}, 4218 {9,"5.0V",-1,1,0,0,LTC2974_5_50V_DACVAL,LTC2974_4_50V_DACVAL,LTC2974_5_0V_DACVAL,1}, 4219 }, 4220 4221 {{0},{0},{0},{0},{0}}, /* ENG */ 4222 {{0},{0},{0},{0},{0}} /* UNK */ 4223 }; 4224 4225 /* Each DAC parameter table, has a number of entries. 4226 * This value must be set for each board entry for the above table 4227 * to work correctly. 4228 * INDEXED_BY_BOARD_TYPE 4229 */ 4230 static int dac_param_len[NUM_BOARD_TYPES] = { 4231 3, /* G5 */ 4232 4, /* G13 */ 4233 2, /* G15 */ 4234 4, /* G16 */ 4235 2, /* G17 */ 4236 4, /* G18 */ 4237 4, /* G19 */ 4238 4, /* G20 */ 4239 2, /* G21 */ 4240 4, /* G22 */ 4241 4, /* G23 */ 4242 3, /* G24 */ 4243 3, /* G25 */ 4244 3, /* G26 */ 4245 4, /* G27 */ 4246 4, /* G28 */ 4247 3, /* G29 */ 4248 3, /* G30 */ 4249 4, /* G31 */ 4250 3, /* G33 */ 4251 3, /* G34 */ 4252 5, /* G35 */ 4253 6, /* G36 */ 4254 6, /* G37 */ 4255 3, /* G38 */ 4256 3, /* G39 */ 4257 4, /* G40 */ 4258 6, /* G41 */ 4259 5, /* G42 */ 4260 3, /* G43 */ 4261 5, /* G44 */ 4262 6, /* G45 */ 4263 6, /* G46 */ 4264 6, /* G47 */ 4265 6, /* G48 */ 4266 9, /* G49 */ 4267 3, /* G50 */ 4268 4, /* G51 */ 4269 6, /* G52 */ 4270 6, /* G53 */ 4271 6, /* G54 */ 4272 6, /* G55 */ 4273 4, /* G56 */ 4274 4, /* G57 */ 4275 6, /* G58 */ 4276 6, /* G59 */ 4277 4, /* G60 */ 4278 3, /* G61 */ 4279 5, /* G62 */ 4280 5, /* G63 */ 4281 4, /* G64 */ 4282 10, /* G65 */ 4283 0, /* ENG */ 4284 0 /* UNK */ 4285 }; 4286 4287 #define MUX_0 0 4288 #define MUX_1 1 4289 #define MUX_2 2 4290 #define MUX_3 3 4291 #define MUX_4 4 4292 #define MUX_5 5 4293 #define MUX_6 6 4294 #define MUX_7 7 4295 #define MUX_8 8 4296 #define MUX_C 0x0C 4297 #define NO_MUX 0xFF 4298 4299 /* Adjustable Voltage Sources parameters. */ 4300 /* Idx: Index of each table entry (per board) */ 4301 /* Muxsel: MUX control value needed to access the DAC */ 4302 /* associated with the desired voltage */ 4303 /* (0xFF = No MUX control needed) */ 4304 /* NOTE: For each board type, the order of each voltage entry */ 4305 /* must match that of their associated entries in the */ 4306 /* dac_params table. */ 4307 /* INDEXED_BY_BOARD_TYPE */ 4308 bb_vparams_t 4309 bb_vs_config[NUM_BOARD_TYPES][MAX_VS_CONFIG_PER_BOARD] = { 4310 /* Idx, Name, Muxsel, ADC Device Name, ADC Channel, DAC Device, Calibrated */ 4311 /* G5: Hercules */ 4312 {{0, "Analog",MUX_0, "adc1", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4313 {1, "2.5", MUX_1, "adc1", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4314 {2, "Core", MUX_2, "adc1", I2C_ADC_CH2, "dac0", DAC_UNCALIBRATED}, 4315 {0},{0}}, 4316 /* Firebolt SDK design: aka G13 */ 4317 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4318 {1, "2.5", MUX_1, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4319 {2, "3.3", MUX_2, "adc0", I2C_ADC_CH2, "dac0", DAC_UNCALIBRATED}, 4320 {3, "Analog",MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4321 {0}}, 4322 /* Goldwing SDK design: aka G15 */ 4323 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4324 {1, "Analog",MUX_2, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4325 {0},{0},{0}}, 4326 /* Bradley 1G SDK design: aka G16 */ 4327 {{0, "Analog",MUX_0, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4328 {1, "2.5", MUX_1, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4329 {2, "1.2", MUX_3, "adc0", I2C_ADC_CH2, "dac0", DAC_UNCALIBRATED}, 4330 {3, "Core", MUX_2, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4331 {0}}, 4332 /* Bradley SDK design: aka G17 */ 4333 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4334 {1, "Analog",MUX_2, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4335 {0},{0},{0}}, /* Note: MUX_3 is used for clock control on this board */ 4336 /* Raptor SDK G18 */ 4337 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4338 {1, "VDD2.5",MUX_1, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4339 {2, "PHY", MUX_2, "adc0", I2C_ADC_CH2, "dac0", DAC_UNCALIBRATED}, 4340 {3, "Analog",MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4341 {0}}, 4342 /* Raven SDK G19 */ 4343 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4344 {1, "VDD2.5",MUX_1, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4345 {2, "PHY", MUX_2, "adc0", I2C_ADC_CH2, "dac0", DAC_UNCALIBRATED}, 4346 {3, "Analog",MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4347 {0}}, 4348 /* Triumph SDK G20 */ 4349 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4350 {1, "2.5", MUX_2, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4351 {2, "1.5", MUX_1, "adc0", I2C_ADC_CH4, "dac0", DAC_UNCALIBRATED}, 4352 {3, "Analog",MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4353 {0}}, 4354 /* Scorpion SDK G21 */ 4355 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4356 {1, "Analog",MUX_2, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4357 {0},{0},{0}}, /* Note: MUX_3 is used for clock control on this board */ 4358 /* Apollo SDK G22 */ 4359 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4360 {1, "2.5", MUX_1, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4361 {2, "Analog",MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4362 {0},{0}}, 4363 /* Sirius SDK G23 */ 4364 {{0, "Core", MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4365 {1, "2.5", MUX_2, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4366 {2, "1.5", MUX_1, "adc0", I2C_ADC_CH4, "dac0", DAC_UNCALIBRATED}, 4367 {3, "Analog",MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4368 {0}}, 4369 /* Trident SDK G24 */ 4370 {{0, "Core", 1<<MUX_0, "adc0", I2C_ADC_CH0, "pwctrl0", DAC_UNCALIBRATED}, 4371 {1, "PHY", 1<<MUX_2, "adc0", I2C_ADC_CH2, "pwctrl0", DAC_UNCALIBRATED}, 4372 {2, "Analog",1<<MUX_3, "adc0", I2C_ADC_CH3, "pwctrl0", DAC_UNCALIBRATED}, 4373 {0},{0}}, 4374 /* Titan SDK G25 */ 4375 {{0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4376 {1, "3.3", 1 << MUX_1, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4377 {2, "5.0", 1 << MUX_2, "adc0", I2C_ADC_CH6, "dac0", DAC_UNCALIBRATED}, 4378 {3, "Analog",1 << MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4379 {0}}, 4380 /* Hurricane SDK G26 */ 4381 {{0, "Core", 1<<MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4382 {1, "PHY", 1<<MUX_2, "adc0", I2C_ADC_CH2, "dac0", DAC_UNCALIBRATED}, 4383 {2, "Analog",MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4384 {0},{0}}, 4385 /* SHADOW SVK G27 */ 4386 {{0, "Core", 4, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4387 {1, "1.0", 5, "adc0", I2C_ADC_CH1, "dac0", DAC_UNCALIBRATED}, 4388 {2, "1.8", 7, "adc0", I2C_ADC_CH2, "dac0", DAC_UNCALIBRATED}, 4389 {3, "3.3", 6, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4390 {0}}, 4391 /* Katana SDK G28 */ 4392 {{0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4393 {1, "3.3", 1 << MUX_1, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4394 {2, "1.5", 1 << MUX_2, "adc0", I2C_ADC_CH4, "dac0", DAC_UNCALIBRATED}, 4395 {3, "Analog",1 << MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4396 {0}}, 4397 /* Enduro-2 SDK G29 */ 4398 {{0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4399 {1, "Analog",1 << MUX_1, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4400 {2, "3.3", 1 << MUX_3, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4401 {0},{0}}, 4402 /* Stardust-2 SDK G30 */ 4403 {{0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4404 {1, "3.3", 1 << MUX_1, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4405 {2, "Analog",1 << MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4406 {0},{0}}, 4407 /* Enduro-2 SDK G31 */ 4408 {{0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "dac0", DAC_UNCALIBRATED}, 4409 {1, "3.3", 1 << MUX_1, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4410 {2, "1.5", 1 << MUX_2, "adc0", I2C_ADC_CH4, "dac0", DAC_UNCALIBRATED}, 4411 {3, "Analog",1 << MUX_3, "adc0", I2C_ADC_CH3, "dac0", DAC_UNCALIBRATED}, 4412 {0}}, 4413 /* Trident SDK G33 */ 4414 {{0, "Core", 1<<MUX_0, "adc0", I2C_ADC_CH0, "pwctrl0", DAC_UNCALIBRATED}, 4415 {1, "PHY", 1<<MUX_2, "adc0", I2C_ADC_CH2, "pwctrl0", DAC_UNCALIBRATED}, 4416 {2, "Analog",1<<MUX_3, "adc0", I2C_ADC_CH3, "pwctrl0", DAC_UNCALIBRATED}, 4417 {0},{0}}, 4418 /* Triumph3 Legacy SDK G34 */ 4419 {{0, "Core", 1 << MUX_1, "adc0", I2C_ADC_CH0, "pwctrl0", DAC_UNCALIBRATED}, 4420 {1, "3.3", 1 << MUX_2, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4421 {2, "Analog",1 << MUX_3, "adc0", I2C_ADC_CH3, "pwctrl0", DAC_UNCALIBRATED}, 4422 {0},{0}}, 4423 /* Triumph3 SDK G35 */ 4424 {{0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "pwctrl0", DAC_UNCALIBRATED}, 4425 {1, "3.3", 1 << MUX_1, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4426 {2, "1.8", 1 << MUX_2, "adc0", I2C_ADC_CH7, "dac0", DAC_UNCALIBRATED}, 4427 {3, "Analog",1 << MUX_3, "adc0", I2C_ADC_CH3, "pwctrl0", DAC_UNCALIBRATED}, 4428 {4, "TCAM", 1 << MUX_7, "adc0", I2C_ADC_CH2, "pwctrl0", DAC_UNCALIBRATED}, 4429 {0}}, 4430 /* Caladan3 48G SVK design: aka G37 */ 4431 {{ 0,"1V_Core", NO_MUX, "adoc0", I2C_ADC_CH0, "adoc0", 0}, 4432 { 0,"1V_Analog", NO_MUX, "adoc0", I2C_ADC_CH1, "adoc0", 0}, 4433 { 0,"1.5", NO_MUX, "adoc0", I2C_ADC_CH2, "adoc0", 0}, 4434 { 0,"3.3", NO_MUX, "adoc0", I2C_ADC_CH3, "adoc0", 0}, 4435 { 0,"1.2", NO_MUX, "adoc0", I2C_ADC_CH4, "adoc0", 0}, 4436 { 0,"Tcam", NO_MUX, "adoc0", I2C_ADC_CH5, "adoc0", 0}, 4437 }, 4438 /* Caladan3 100G SVK design: aka G37 */ 4439 {{ 0,"1V_Core", NO_MUX, "adoc0", I2C_ADC_CH0, "adoc0", 0}, 4440 { 0,"1V_Analog", NO_MUX, "adoc0", I2C_ADC_CH1, "adoc0", 0}, 4441 { 0,"1.5", NO_MUX, "adoc0", I2C_ADC_CH2, "adoc0", 0}, 4442 { 0,"3.3", NO_MUX, "adoc0", I2C_ADC_CH3, "adoc0", 0}, 4443 { 0,"1.2", NO_MUX, "adoc0", I2C_ADC_CH4, "adoc0", 0}, 4444 { 0,"Tcam", NO_MUX, "adoc0", I2C_ADC_CH5, "adoc0", 0}, 4445 }, 4446 /* Trident2 SVK G38 */ 4447 {{0, "Core", 1<<MUX_0, "adc0", I2C_ADC_CH0, "pwctrl2", DAC_UNCALIBRATED}, 4448 {1, "Analog",1<<MUX_1, "adc0", I2C_ADC_CH3, "pwctrl2", DAC_UNCALIBRATED}, 4449 {2, "3.3", 1<<MUX_2, "adc0", I2C_ADC_CH5, "pwctrl2", DAC_UNCALIBRATED}, 4450 }, 4451 /* Trident2 DVT G39 */ 4452 {{0, "Core", 1<<MUX_0, "adc0", I2C_ADC_CH0, "pwctrl2", DAC_UNCALIBRATED}, 4453 {1, "Analog",1<<MUX_1, "adc0", I2C_ADC_CH3, "pwctrl2", DAC_UNCALIBRATED}, 4454 {2, "3.3", 1<<MUX_2, "adc0", I2C_ADC_CH5, "pwctrl2", DAC_UNCALIBRATED}, 4455 }, 4456 /* Katana2 G40 */ 4457 {{0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH6, "dac0", DAC_UNCALIBRATED}, 4458 {1, "3.3", 1 << MUX_1, "adc0", I2C_ADC_CH5, "dac0", DAC_UNCALIBRATED}, 4459 {2, "1.5", 1 << MUX_2, "adc0", I2C_ADC_CH4, "dac0", DAC_UNCALIBRATED}, 4460 {3, "Analog",1 << MUX_3, "adc0", I2C_ADC_CH7, "dac0", DAC_UNCALIBRATED}, 4461 {0}}, 4462 /* Greyhound G41 */ 4463 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4464 {1, "2.5V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4465 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4466 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4467 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 4468 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED} 4469 }, 4470 /* Tomahawk design: aka G42 */ 4471 {{ 0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "pwctrl2", DAC_UNCALIBRATED }, 4472 { 1, "Analog", 1 << MUX_3, "ltc3882-1", I2C_BOTH_CH, "ltc3882-1", PWR_DAC_IO_SRC }, 4473 { 2, "3.3", 1 << MUX_3, "ltc3882-0", I2C_BOTH_CH, "ltc3882-0", PWR_DAC_IO_SRC }, 4474 { 3, "1.25", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH0, "ltc3880", PWR_DAC_IO_SRC }, 4475 { 4, "1.8", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH1, "ltc3880", PWR_DAC_IO_SRC }, 4476 {0}, 4477 }, 4478 /* Trident2+ G43 */ 4479 {{0, "Core", 1<<MUX_0, "adc0", I2C_ADC_CH0, "pwctrl2", DAC_UNCALIBRATED}, 4480 {1, "Analog",1<<MUX_1, "adc0", I2C_ADC_CH3, "pwctrl2", DAC_UNCALIBRATED}, 4481 {2, "3.3", 1<<MUX_2, "adc0", I2C_ADC_CH5, "pwctrl2", DAC_UNCALIBRATED}, 4482 }, 4483 /* Trident2+ 100G G44 */ 4484 {{ 0, "Core", 1 << MUX_0, "adc0", I2C_ADC_CH0, "pwctrl2", DAC_UNCALIBRATED }, 4485 { 1, "Analog", 1 << MUX_3, "ltc3882-1", I2C_BOTH_CH, "ltc3882-1", PWR_DAC_IO_SRC }, 4486 { 2, "3.3", 1 << MUX_3, "ltc3882-0", I2C_BOTH_CH, "ltc3882-0", PWR_DAC_IO_SRC }, 4487 { 3, "1.25", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH0, "ltc3880", PWR_DAC_IO_SRC }, 4488 { 4, "1.8", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH1, "ltc3880", PWR_DAC_IO_SRC }, 4489 {0}, 4490 }, 4491 /* Greyhound G45 */ 4492 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4493 {1, "2.5V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4494 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4495 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4496 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 4497 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED} 4498 }, 4499 /* Greyhound G46 */ 4500 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4501 {1, "2.5V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4502 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4503 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4504 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 4505 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED} 4506 }, 4507 /* Greyhound G47 */ 4508 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4509 {1, "2.5V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 4510 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4511 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 4512 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 4513 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED} 4514 }, 4515 /* Saber2 design: aka G48 */ 4516 {{0,"Core", 1 << MUX_7, I2C_LTC3880_41, I2C_LTC3880_CH0, I2C_LTC3880_41, PWR_DAC_IO_SRC }, 4517 {1,"DDR", 1 << MUX_7, I2C_LTC3880_41, I2C_LTC3880_CH1, I2C_LTC3880_41, PWR_DAC_IO_SRC }, 4518 {2,"IPROC_CORE",1 << MUX_7, I2C_LTC3880_42, I2C_LTC3880_CH0, I2C_LTC3880_42, PWR_DAC_IO_SRC }, 4519 {3,"Analog",1 << MUX_7, I2C_LTC3880_42, I2C_LTC3880_CH1, I2C_LTC3880_42, PWR_DAC_IO_SRC }, 4520 {4,"3.3", 1 << MUX_7, I2C_LTM4676_43, I2C_LTC3880_CH0, I2C_LTM4676_43, PWR_DAC_IO_SRC }, 4521 {5,"1.8", 1 << MUX_7, I2C_LTM4676_43, I2C_LTC3880_CH1, I2C_LTM4676_43, PWR_DAC_IO_SRC }, 4522 }, 4523 /* Tomahawk PVT: aka G49 */ 4524 {{ 0, "Core", 1 << MUX_2, I2C_LTC3882_55, I2C_BOTH_CH, I2C_LTC3882_55, PWR_DAC_IO_SRC }, 4525 { 1, "ANA1", 1 << MUX_2, I2C_LTC3880_41, I2C_BOTH_CH, I2C_LTC3880_41, PWR_DAC_IO_SRC }, 4526 { 2, "ANA2", 1 << MUX_2, I2C_LTC3880_42, I2C_LTC3880_CH0, I2C_LTC3880_42, PWR_DAC_IO_SRC }, 4527 { 3, "3.3V", 1 << MUX_2, I2C_LTC3880_42, I2C_LTC3880_CH1, I2C_LTC3880_42, PWR_DAC_IO_SRC }, 4528 { 4, "DDR_15", 1 << MUX_2, I2C_LTC3880_43, I2C_BOTH_CH, I2C_LTC3880_43, PWR_DAC_IO_SRC }, 4529 { 5, "SP1", 1 << MUX_2, I2C_LTC3880_47, I2C_LTC3880_CH0, I2C_LTC3880_47, PWR_DAC_IO_SRC }, 4530 { 6, "SP2", 1 << MUX_2, I2C_LTC3880_47, I2C_LTC3880_CH1, I2C_LTC3880_47, PWR_DAC_IO_SRC }, 4531 { 7, "DDR_Core", 1 << MUX_2, I2C_LTC3880_45, I2C_LTC3880_CH0, I2C_LTC3880_45, PWR_DAC_IO_SRC }, 4532 { 8, "SP3", 1 << MUX_2, I2C_LTC3880_45, I2C_LTC3880_CH1, I2C_LTC3880_45, PWR_DAC_IO_SRC }, 4533 }, 4534 /* Apache/Maverick aka G50 */ 4535 {{ 0, "Core", 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, I2C_LTC3884_42, DAC_UNCALIBRATED }, 4536 { 1, "Analog", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, I2C_LTC3884_43, DAC_UNCALIBRATED }, 4537 { 2, "3.3V", 1 << MUX_4, I2C_LTC3880_45, I2C_BOTH_CH, I2C_LTC3880_45, DAC_UNCALIBRATED }, 4538 }, 4539 /* FireBolt5 aka G51 */ 4540 {{ 0, "Core", 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, I2C_LTC3884_42, DAC_UNCALIBRATED }, 4541 { 1, "Analog", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, I2C_LTC3884_43, DAC_UNCALIBRATED }, 4542 { 2, "1.0V_PHY", 1 << MUX_4, I2C_LTC3884_46, I2C_BOTH_CH, I2C_LTC3884_46, DAC_UNCALIBRATED }, 4543 { 3, "3.3V", 1 << MUX_4, I2C_LTM4676_47, I2C_BOTH_CH, I2C_LTM4676_47, DAC_UNCALIBRATED }, 4544 }, 4545 /* HR3 SVK(BCM56160K): G52 */ 4546 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4547 {1, "1.0V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4548 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4549 {3, "1.2V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4550 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4551 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4552 }, 4553 /* HR3 SVK(BCM53444K): G53 */ 4554 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4555 {1, "1.0V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4556 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4557 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4558 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4559 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC} 4560 }, 4561 /* HR3 SVK(BCM53434K): G54 */ 4562 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4563 {1, "1.0V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4564 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4565 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4566 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4567 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC} 4568 }, 4569 /* HR3 BCM56160D: G55 */ 4570 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4571 {1, "1.0V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4572 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4573 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4574 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4575 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC} 4576 }, 4577 /* Metrolite design: aka G56 */ 4578 {{0,"Core", 1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH0, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 4579 {1,"Analog",1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH1, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 4580 {2,"3.3", 1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH2, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 4581 {3,"1.8", 1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH3, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 4582 }, 4583 /* Tomahawk2 design: aka G57 */ 4584 {{0,"Analog",1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH0, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4585 {1,"1.2", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH1, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4586 {2,"1.8", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH2, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4587 {3,"3.3", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH3, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4588 {4,"Core", 1 << MUX_3, I2C_NCP81233_0, I2C_NCP81233_CH0, I2C_NCP81233_0, PWR_DAC_IO_PMBUS}, 4589 }, 4590 /* GH2 SVK(BCM53570K): G58 */ 4591 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4592 {1, "1.25V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4593 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4594 {3, "1.2V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4595 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4596 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4597 }, 4598 /* GH2 SVK(BCM53570S): G59 */ 4599 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4600 {1, "1.25V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4601 {2, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4602 {3, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4603 {4, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4604 {5, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4605 }, 4606 /* Trident3/Maverick2 design: aka G60 */ 4607 {{0,"Analog",1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH0, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4608 {1,"1.2", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH1, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4609 {2,"1.8", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH2, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4610 {3,"3.3", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH3, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4611 {4,"Core", 1 << MUX_3, I2C_NCP81233_0, I2C_NCP81233_CH0, I2C_NCP81233_0, PWR_DAC_IO_PMBUS}, 4612 }, 4613 /* MONTEREY aka G61 */ 4614 {{ 0, "Core", 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, I2C_LTC3884_42, DAC_UNCALIBRATED }, 4615 { 1, "Analog", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, I2C_LTC3884_43, DAC_UNCALIBRATED }, 4616 { 2, "3.3V", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH0, I2C_LTC3880_43, DAC_UNCALIBRATED }, 4617 { 3, "1.2V", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH0, I2C_LTC2974_64, PWR_DAC_IO_SRC }, 4618 { 4, "3.3dut", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH1, I2C_LTC2974_64, PWR_DAC_IO_SRC }, 4619 { 5, "1.8V", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH2, I2C_LTC2974_64, PWR_DAC_IO_SRC }, 4620 { 6, "1.2mdio", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH3, I2C_LTC2974_64, PWR_DAC_IO_SRC }, 4621 }, 4622 /* WH2 SVK(BCM53547K): G62 */ 4623 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4624 {1, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4625 {2, "1.2V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4626 {3, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4627 {4, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4628 }, 4629 /* WH2 SVK(BCM53549K): G63 */ 4630 {{0, "3.3V", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 4631 {1, "1.8V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4632 {2, "1.5V", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 4633 {3, "Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4634 {4, "Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 4635 }, 4636 /* Tomahawk3 design: aka G64 */ 4637 {{0,"MDIO", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH0, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4638 {1,"1.2", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH1, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4639 {2,"1.8", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH2, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4640 {3,"3.3", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH3, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 4641 {4,"Analog00", 1 << MUX_3, I2C_LTM4678_40, I2C_LTM4678_CH0, I2C_LTM4678_40, PWR_DAC_IO_SRC}, 4642 {5,"Analog01", 1 << MUX_3, I2C_LTM4678_40, I2C_LTM4678_CH1, I2C_LTM4678_40, PWR_DAC_IO_SRC}, 4643 {6,"Analog10", 1 << MUX_3, I2C_LTM4678_41, I2C_LTM4678_CH0, I2C_LTM4678_41, PWR_DAC_IO_SRC}, 4644 {7,"Analog11", 1 << MUX_3, I2C_LTM4678_41, I2C_LTM4678_CH1, I2C_LTM4678_41, PWR_DAC_IO_SRC}, 4645 {8,"Core", 1 << MUX_3, I2C_ISL68127_60, I2C_ISL68127_CH1, I2C_ISL68127_60, PWR_DAC_IO_PMBUS}, 4646 /* {9,"QSFP", 1 << MUX_3, I2C_ISL68127_61, I2C_ISL68127_CH0, I2C_ISL68127_61, PWR_DAC_IO_PMBUS}, */ 4647 }, 4648 /* Helix5 design: aka G65 */ 4649 {{0,"Core", 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, I2C_LTC3884_42, DAC_UNCALIBRATED }, 4650 {1,"Analog", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, I2C_LTC3884_43, DAC_UNCALIBRATED }, 4651 {2,"0.88V", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH0, I2C_LTC2974_63, DAC_UNCALIBRATED }, 4652 {3,"3.3V_Dut", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH1, I2C_LTC2974_63, DAC_UNCALIBRATED }, 4653 {4,"2.5V", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH2, I2C_LTC2974_63, DAC_UNCALIBRATED }, 4654 {5,"VDD_MDIO", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH3, I2C_LTC2974_63, DAC_UNCALIBRATED }, 4655 {6,"1.8V", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH0, I2C_LTC2974_64, DAC_UNCALIBRATED }, 4656 {7,"1.2V", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH1, I2C_LTC2974_64, DAC_UNCALIBRATED }, 4657 {8,"3.3V_Dut", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH2, I2C_LTC2974_64, DAC_UNCALIBRATED }, 4658 {9,"5.0V", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH3, I2C_LTC2974_64, DAC_UNCALIBRATED }, 4659 }, 4660 4661 {{0},{0},{0},{0},{0}}, /* ENG */ 4662 {{0},{0},{0},{0},{0}} /* UNK */ 4663 }; 4664 4665 /* Map of number of configurable voltages, one per board. 4666 * Each one of these is the number of voltage parameters 4667 * (from above) for each table entry for each board. 4668 * INDEXED_BY_BOARD_TYPE 4669 */ 4670 int bb_vs_config_len[NUM_BOARD_TYPES] = { 4671 3, /* G5 */ 4672 4, /* G13 */ 4673 2, /* G15 */ 4674 4, /* G16 */ 4675 2, /* G17 */ 4676 4, /* G18 */ 4677 4, /* G19 */ 4678 4, /* G20 */ 4679 2, /* G21 */ 4680 4, /* G22 */ 4681 4, /* G23 */ 4682 3, /* G24 */ 4683 4, /* G25 */ 4684 3, /* G26 */ 4685 4, /* G27 */ 4686 4, /* G28 */ 4687 3, /* G29 */ 4688 3, /* G30 */ 4689 4, /* G31 */ 4690 3, /* G33 */ 4691 3, /* G34 */ 4692 5, /* G35 */ 4693 6, /* G36 */ 4694 6, /* G37 */ 4695 3, /* G38 */ 4696 3, /* G39 */ 4697 4, /* G40 */ 4698 6, /* G41 */ 4699 5, /* G42 */ 4700 3, /* G43 */ 4701 5, /* G44 */ 4702 6, /* G45 */ 4703 6, /* G46 */ 4704 6, /* G47 */ 4705 6, /* G48 */ 4706 9, /* G49 */ 4707 3, /* G50 */ 4708 4, /* G51 */ 4709 6, /* G52 */ 4710 6, /* G53 */ 4711 6, /* G54 */ 4712 6, /* G55 */ 4713 4, /* G56 */ 4714 5, /* G57 */ 4715 6, /* G58 */ 4716 6, /* G59 */ 4717 5, /* G60 */ 4718 7, /* G61 */ 4719 5, /* G62 */ 4720 5, /* G63 */ 4721 9, /* G64 */ 4722 10,/* G65 */ 4723 0, /* ENG */ 4724 0 /* UNK */ 4725 }; 4726 4727 /* All (non-configurable and configurable) voltages, per board. 4728 * For display only (only name, adc device and channel used). 4729 * NOTE: The text names which include an asterisk denote a 4730 * configurable voltage source. The name in parentheses 4731 * should match the name field in the corresponding entry 4732 * in the bb_vs_config[] table. 4733 * INDEXED_BY_BOARD_TYPE 4734 */ 4735 bb_vparams_t 4736 bb_vs_all[NUM_BOARD_TYPES][MAX_VOLTAGES_PER_BOARD] = { 4737 /* Hercules: aka G5 */ 4738 {{ 0,"VDD_5.0V ", 0, "adc1", I2C_ADC_CH5, NULL, 0}, 4739 { 0,"VDD_3.3V ", 0, "adc1", I2C_ADC_CH4, NULL, 0}, 4740 { 0,"VDD_Core (Core) * ", 0, "adc1", I2C_ADC_CH2, NULL, PWR_CORE_A_SRC | PWR_CORECAL_SRC}, 4741 { 0,"VDD_1.2 (Analog) *", 0, "adc1", I2C_ADC_CH0, NULL, PWR_PHY_SRC}, 4742 { 0,"VDD_2.5 (2.5) * ", 0, "adc1", I2C_ADC_CH1, NULL, 0}, 4743 { 0,"IVDD_Core ", 0, "adc0", I2C_ADC_CH0, NULL, PWR_CORE_A_DROP}, 4744 { 0,"IVDD_1.2 ", 0, "adc0", I2C_ADC_CH2, NULL, PWR_PHY_DROP}, 4745 { 0,"ICAL_Core ", 0, "adc0", I2C_ADC_CH1, NULL, PWR_CORECAL_DROP}, 4746 {0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}, 4747 {0},{0},{0},{0},{0},{0},{0},{0}}, 4748 /* Firebolt SDK design: aka G13 */ 4749 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, PWR_CORE_A_LOAD}, 4750 { 0,"VDD_2.5V (2.5)* ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4751 { 0,"VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4752 { 0,"VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, PWR_PHY_LOAD | PWR_PHY_SRC | PWR_PHYCAL_SRC}, 4753 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4754 { 0,"VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4755 { 0,"TP4003 ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4756 { 0,"TP4002 ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4757 { 0,"ICal_Core ", 0, "adc1", I2C_ADC_CH0, NULL, PWR_CORECAL_DROP}, 4758 { 0,"IVDD_Core ", 0, "adc1", I2C_ADC_CH1, NULL, PWR_CORE_A_DROP}, 4759 { 0,"ICal_Analog ", 0, "adc1", I2C_ADC_CH2, NULL, PWR_PHYCAL_DROP}, 4760 { 0,"IVDD_Analog ", 0, "adc1", I2C_ADC_CH3, NULL, PWR_PHY_DROP}, 4761 { 0,"Core_SRC ", 0, "adc1", I2C_ADC_CH5, NULL, PWR_CORE_A_SRC | PWR_CORECAL_SRC}, 4762 { 0,"VDD_2.5 ", 0, "adc1", I2C_ADC_CH6, NULL, 0}, 4763 }, 4764 /* Goldwing SDK design: aka G15 */ 4765 {{ 0,"VDD_1.0V (Analog)*", 0, "adc0", I2C_ADC_CH0, NULL, PWR_PHY_LOAD}, 4766 { 0,"VDD_2.5V ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4767 { 0,"VDD_3.3V ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4768 { 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH3, NULL, PWR_CORE_A_LOAD}, 4769 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4770 { 0,"VDD_3.3V_B ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4771 { 0,"ICal_Core ", 0, "adc1", I2C_ADC_CH0, NULL, PWR_CORECAL_DROP}, 4772 { 0,"IVDD_Core ", 0, "adc1", I2C_ADC_CH1, NULL, PWR_CORE_A_DROP}, 4773 { 0,"ICal_Analog ", 0, "adc1", I2C_ADC_CH2, NULL, PWR_PHYCAL_DROP}, 4774 { 0,"IVDD_Analog ", 0, "adc1", I2C_ADC_CH3, NULL, PWR_PHY_DROP}, 4775 { 0,"VDD_1.0V_PS ", 0, "adc1", I2C_ADC_CH5, NULL, PWR_PHY_SRC | PWR_PHYCAL_SRC}, 4776 { 0,"CORE_PS ", 0, "adc1", I2C_ADC_CH6, NULL, PWR_CORE_A_SRC | PWR_CORECAL_SRC}, 4777 }, 4778 /* Bradley 1G SDK design: aka G16 */ 4779 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, PWR_CORE_A_LOAD}, 4780 { 0,"VDD_2.5V (2.5)* ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4781 { 0,"VDD_1.2V (1.2)* ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4782 { 0,"VDD_1.0V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, PWR_PHY_LOAD}, 4783 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4784 { 0,"VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4785 { 0,"ICal_Core ", 0, "adc1", I2C_ADC_CH0, NULL, PWR_CORECAL_DROP}, 4786 { 0,"IVDD_Core ", 0, "adc1", I2C_ADC_CH1, NULL, PWR_CORE_A_DROP}, 4787 { 0,"ICal_Analog ", 0, "adc1", I2C_ADC_CH2, NULL, PWR_PHYCAL_DROP}, 4788 { 0,"IVDD_Analog ", 0, "adc1", I2C_ADC_CH3, NULL, PWR_PHY_DROP}, 4789 { 0,"VDD_1.0V_PS ", 0, "adc1", I2C_ADC_CH4, NULL, PWR_PHY_SRC | PWR_PHYCAL_SRC}, 4790 { 0,"CORE_PS ", 0, "adc1", I2C_ADC_CH5, NULL, PWR_CORE_A_SRC | PWR_CORECAL_SRC}, 4791 { 0,"VDD_2.5V_PS ", 0, "adc1", I2C_ADC_CH6, NULL, 0}, 4792 }, 4793 /* Bradley SDK design: aka G17 */ 4794 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, PWR_CORE_A_LOAD}, 4795 { 0,"VDD_2.5V ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4796 { 0,"VDD_3.3V ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4797 { 0,"VDD_1.0V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, PWR_PHY_LOAD}, 4798 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4799 { 0,"VDD_3.3V_B ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4800 { 0,"ICal_Core ", 0, "adc1", I2C_ADC_CH0, NULL, PWR_CORECAL_DROP}, 4801 { 0,"IVDD_Core ", 0, "adc1", I2C_ADC_CH1, NULL, PWR_CORE_A_DROP}, 4802 { 0,"ICal_Analog ", 0, "adc1", I2C_ADC_CH2, NULL, PWR_PHYCAL_DROP}, 4803 { 0,"IVDD_Analog ", 0, "adc1", I2C_ADC_CH3, NULL, PWR_PHY_DROP}, 4804 { 0,"CORE_PS ", 0, "adc1", I2C_ADC_CH5, NULL, PWR_CORE_A_SRC | PWR_CORECAL_SRC}, 4805 { 0,"VDD_1.0V_PS ", 0, "adc1", I2C_ADC_CH6, NULL, PWR_PHY_SRC | PWR_PHYCAL_SRC}, 4806 }, 4807 /* Raptor SDK design: aka G18 */ 4808 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, PWR_CORE_A_SRC | PWR_CORECAL_SRC}, 4809 { 0,"VDD_2.5V (VDD2.5)*", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4810 { 0,"VDD_1.2V/1.8V (Phy)*", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4811 { 0,"VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, PWR_PHY_SRC | PWR_PHYCAL_SRC}, 4812 { 0,"VDD_3.3V_B ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4813 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4814 { 0,"ICal_Core ", 0, "adc1", I2C_ADC_CH0, NULL, PWR_CORECAL_DROP}, 4815 { 0,"IVDD_Core ", 0, "adc1", I2C_ADC_CH1, NULL, PWR_CORE_A_DROP}, 4816 { 0,"ICal_Analog ", 0, "adc1", I2C_ADC_CH2, NULL, PWR_PHYCAL_DROP}, 4817 { 0,"IVDD_Analog ", 0, "adc1", I2C_ADC_CH3, NULL, PWR_PHY_DROP}, 4818 }, 4819 /* Raven SDK design: aka G19 */ 4820 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4821 { 0,"VDD_2.5V (VDD2.5)*", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4822 { 0,"VDD_1.0V/1.8V(Phy)*", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4823 { 0,"VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4824 { 0,"VDD_3.3V_B ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4825 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4826 }, 4827 /* Triumph SDK design : aka G20 */ 4828 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4829 { 0, "VDD_2.5V (2.5)* ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4830 { 0, "VDD_1.8V ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4831 { 0, "VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4832 { 0, "VDD_1.5V (1.5)* ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4833 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4834 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4835 }, 4836 /* Scorpion SDK design : aka G21 */ 4837 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4838 { 0, "VDD_2.5V ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4839 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4840 { 0, "VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4841 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4842 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4843 }, 4844 /* Apollo SDK design : aka G22 */ 4845 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4846 { 0, "VDD_2.5V (2.5)* ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4847 { 0, "VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4848 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4849 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4850 }, 4851 /* Sirius SDK design : aka G23 */ 4852 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4853 { 0, "VDD_2.5V (2.5)* ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4854 { 0, "VDD_1.8V ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4855 { 0, "VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4856 { 0, "VDD_1.5V (1.5)* ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4857 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4858 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4859 }, 4860 /* Trident SDK design : aka G24 */ 4861 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4862 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4863 { 0, "PHY* ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4864 { 0, "VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4865 { 0, "VDD_1.5V (1.5) ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4866 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4867 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4868 { 0, "VDD_1.8V ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4869 }, 4870 /* Titan SDK design : aka G25 */ 4871 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4872 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4873 { 0, "NC ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4874 { 0, "VDD_1.0V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4875 { 0, "NC ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4876 { 0, "VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4877 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4878 { 0, "NC ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4879 }, 4880 /* Hurricane SDK design: aka G26 */ 4881 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4882 { 0,"VDD_1.2V (Phy)* ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4883 { 0,"VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4884 { 0,"VDD_3.3V_B ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4885 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4886 }, 4887 /* Shadow SDK design : aka G26 */ 4888 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4889 { 0, "SERDES1.0V (1.0)* ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4890 { 0, "SHAD_1P8 (1.8)* ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4891 { 0, "SHAD_3P3 (3.3)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4892 { 0, "VDD_2.5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4893 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4894 { 0, "VDD_5.0V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4895 { 0, "VDD_1.2V ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4896 }, 4897 /* Katana SDK design: aka G28 */ 4898 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4899 { 0,"VDD_1V (Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4900 { 0,"VDD_1.5V (1.5)* ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4901 { 0,"VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4902 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4903 }, 4904 /* Enduro-2 SDK design: aka G29 */ 4905 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4906 { 0,"VDD_1V (Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4907 { 0,"VDD_1.5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4908 { 0,"VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4909 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4910 }, 4911 /* Stardust-2 SDK design: aka G30 */ 4912 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4913 { 0,"VDD_2.5V ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4914 { 0,"VDD_1V (Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4915 { 0,"VDD_1.5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4916 { 0,"VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4917 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4918 }, 4919 /* Enduro-2 SDK design: aka G31 */ 4920 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4921 { 0,"VDD_1V (Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4922 { 0,"VDD_1.5V (1.5)* ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4923 { 0,"VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4924 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4925 }, 4926 /* Trident SDK design : aka G33 */ 4927 {{ 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4928 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4929 { 0, "PHY* ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4930 { 0, "VDD_1.2V (Analog)*", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4931 { 0, "VDD_1.5V (1.5) ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4932 { 0, "VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4933 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4934 { 0, "VDD_1.8V ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4935 }, 4936 /* Triumph3 Legacy SDK design: aka G34 */ 4937 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4938 { 0,"VDD_1V (Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4939 { 0,"VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4940 { 0,"VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4941 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4942 }, 4943 /* Triumph3 SDK design: aka G35 */ 4944 {{ 0,"CORE (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4945 { 0,"TCAM_0.9V (Tcam)* ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4946 { 0,"VDD_1V (Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4947 { 0,"VDD_1.8V (1.8)* ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4948 { 0,"VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4949 { 0,"VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4950 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4951 }, 4952 /* Caladan3 48G SVK design: aka G36 */ 4953 {{ 0,"DUT_1VD (1V_Core)* ", 0, "adoc0", I2C_ADC_CH0, NULL, 0}, 4954 { 0,"DUT_1VA (1V_Analog)* ", 0, "adoc0", I2C_ADC_CH1, NULL, 0}, 4955 { 0,"DUT_1.5V (1.5)* ", 0, "adoc0", I2C_ADC_CH2, NULL, 0}, 4956 { 0,"DUT_3.3V (3.3)* ", 0, "adoc0", I2C_ADC_CH3, NULL, 0}, 4957 { 0,"DUT_1.2V (1.2)* ", 0, "adoc0", I2C_ADC_CH4, NULL, 0}, 4958 { 0,"TCAM (Tcam)* ", 0, "adoc0", I2C_ADC_CH5, NULL, 0}, 4959 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4960 { 0,"VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4961 { 0,"VDD_1.2V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4962 }, 4963 /* Caladan3 100G SVK design: aka G37 */ 4964 {{ 0,"DUT_1VD (1V_Core)* ", 0, "adoc0", I2C_ADC_CH0, NULL, 0}, 4965 { 0,"DUT_1VA (1V_Analog)* ", 0, "adoc0", I2C_ADC_CH1, NULL, 0}, 4966 { 0,"DUT_1.5V (1.5)* ", 0, "adoc0", I2C_ADC_CH2, NULL, 0}, 4967 { 0,"DUT_3.3V (3.3)* ", 0, "adoc0", I2C_ADC_CH3, NULL, 0}, 4968 { 0,"DUT_1.2V (1.2)* ", 0, "adoc0", I2C_ADC_CH4, NULL, 0}, 4969 { 0,"TCAM (Tcam)* ", 0, "adoc0", I2C_ADC_CH5, NULL, 0}, 4970 { 0,"VDD_5V ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4971 { 0,"VDD_3.3V ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4972 }, 4973 /* Trident2 SVK design : aka G38 */ 4974 {{ 0, "VDD_1V (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4975 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4976 { 0, "NC ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4977 { 0, "VDD_ANA(Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4978 { 0, "NC ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4979 { 0, "VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4980 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4981 { 0, "NC ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4982 }, 4983 /* Trident2 DVT design : aka G39 */ 4984 {{ 0, "VDD_1V (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 4985 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4986 { 0, "NC ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 4987 { 0, "VDD_ANA(Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 4988 { 0, "NC ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4989 { 0, "VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4990 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4991 { 0, "NC ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4992 }, 4993 /* Katana2 design : aka G40 */ 4994 {{ 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 4995 { 0, "VDD_1.5V (1.5)* ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 4996 { 0, "VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 4997 { 0, "CORE (Core)* ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 4998 { 0, "VDD_1V (Analog)* ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 4999 }, 5000 /* Greyhound design : aka G41 */ 5001 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5002 {0, "2.5V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5003 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5004 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5005 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5006 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5007 {0, "3.3V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH0, I2C_LTC3880_64, DAC_UNCALIBRATED}, 5008 {0, "5V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH1, I2C_LTC3880_64, DAC_UNCALIBRATED}, 5009 {0, "DDR_CORE", 0, I2C_LTC3880_65, I2C_LTC3880_CH0, I2C_LTC3880_65, DAC_UNCALIBRATED}, 5010 {0, "1.0V(EXTPHY_CORE)", 0, I2C_LTC3880_65, I2C_LTC3880_CH1, I2C_LTC3880_65, DAC_UNCALIBRATED} 5011 }, 5012 /* Tomahawk design : aka G42 */ 5013 {{ 0, "VDD_1V (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 5014 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 5015 { 0, "VDD_1.25V (1.25)* ", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH0, NULL, PWR_DAC_IO_SRC}, 5016 { 0, "VDD_ANA(Analog)* ", 1 << MUX_3, "ltc3882-1", I2C_BOTH_CH, NULL, PWR_DAC_IO_SRC}, 5017 { 0, "NC ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 5018 { 0, "VDD_3.3V (3.3)* ", 1 << MUX_3, "ltc3882-0", I2C_BOTH_CH, NULL, PWR_DAC_IO_SRC}, 5019 { 0, "VDD_5V (5) ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 5020 { 0, "VDD_1.8V (1.8)* ", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH1, NULL, PWR_DAC_IO_SRC}, 5021 { 0, "LCPLL0_PVDD ", 0, "ltc2974", I2C_LTC2974_CH0, NULL, PWR_DAC_IO_SRC}, 5022 { 0, "FC28 & 29 T/RVDD ", 0, "ltc2974", I2C_LTC2974_CH1, NULL, PWR_DAC_IO_SRC}, 5023 { 0, "FC28_PVDD/3.3V ", 0, "ltc2974", I2C_LTC2974_CH2, NULL, PWR_DAC_IO_SRC}, 5024 { 0, "FC9_TVDD ", 0, "ltc2974", I2C_LTC2974_CH3, NULL, PWR_DAC_IO_SRC}, 5025 }, 5026 /* Trident2+ design : aka G41 */ 5027 {{ 0, "VDD_1V (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 5028 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 5029 { 0, "NC ", 0, "adc0", I2C_ADC_CH2, NULL, 0}, 5030 { 0, "VDD_ANA(Analog)* ", 0, "adc0", I2C_ADC_CH3, NULL, 0}, 5031 { 0, "NC ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 5032 { 0, "VDD_3.3V (3.3)* ", 0, "adc0", I2C_ADC_CH5, NULL, 0}, 5033 { 0, "VDD_5V ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 5034 { 0, "NC ", 0, "adc0", I2C_ADC_CH7, NULL, 0}, 5035 }, 5036 /* Trident2+ 100G design : aka G42 */ 5037 {{ 0, "VDD_1V (Core)* ", 0, "adc0", I2C_ADC_CH0, NULL, 0}, 5038 { 0, "VDD_2.5V (2.5) ", 0, "adc0", I2C_ADC_CH1, NULL, 0}, 5039 { 0, "VDD_1.25V (1.25)* ", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH0, NULL, PWR_DAC_IO_SRC}, 5040 { 0, "VDD_ANA(Analog)* ", 1 << MUX_3, "ltc3882-1", I2C_BOTH_CH, NULL, PWR_DAC_IO_SRC}, 5041 { 0, "NC ", 0, "adc0", I2C_ADC_CH4, NULL, 0}, 5042 { 0, "VDD_3.3V (3.3)* ", 1 << MUX_3, "ltc3882-0", I2C_BOTH_CH, NULL, PWR_DAC_IO_SRC}, 5043 { 0, "VDD_5V (5) ", 0, "adc0", I2C_ADC_CH6, NULL, 0}, 5044 { 0, "VDD_1.8V (1.8)* ", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH1, NULL, PWR_DAC_IO_SRC}, 5045 { 0, "LCPLL0_PVDD ", 0, "ltc2974", I2C_LTC2974_CH0, NULL, PWR_DAC_IO_SRC}, 5046 { 0, "FC28 & 29 T/RVDD ", 0, "ltc2974", I2C_LTC2974_CH1, NULL, PWR_DAC_IO_SRC}, 5047 { 0, "FC28_PVDD/3.3V ", 0, "ltc2974", I2C_LTC2974_CH2, NULL, PWR_DAC_IO_SRC}, 5048 { 0, "FC9_TVDD ", 0, "ltc2974", I2C_LTC2974_CH3, NULL, PWR_DAC_IO_SRC}, 5049 }, 5050 /* Greyhound design : aka G45 */ 5051 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5052 {0, "2.5V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5053 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5054 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5055 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5056 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5057 {0, "3.3V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH0, I2C_LTC3880_64, DAC_UNCALIBRATED}, 5058 {0, "5V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH1, I2C_LTC3880_64, DAC_UNCALIBRATED}, 5059 {0, "1.0V(EXTPHY_CORE)", 0, I2C_LTC3880_65, I2C_LTC3880_CH1, I2C_LTC3880_65, DAC_UNCALIBRATED} 5060 }, 5061 /* Greyhound design : aka G46 */ 5062 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5063 {0, "2.5V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5064 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5065 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5066 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5067 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5068 {0, "3.3V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH0, I2C_LTC3880_64, DAC_UNCALIBRATED}, 5069 {0, "5V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH1, I2C_LTC3880_64, DAC_UNCALIBRATED}, 5070 {0, "DDR_CORE", 0, I2C_LTC3880_65, I2C_LTC3880_CH0, I2C_LTC3880_65, DAC_UNCALIBRATED} 5071 }, 5072 /* Greyhound design : aka G47 */ 5073 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5074 {0, "2.5V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, DAC_UNCALIBRATED}, 5075 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5076 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, DAC_UNCALIBRATED}, 5077 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5078 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, DAC_UNCALIBRATED}, 5079 {0, "3.3V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH0, I2C_LTC3880_64, DAC_UNCALIBRATED}, 5080 {0, "5V(EXT_IO)", 0, I2C_LTC3880_64, I2C_LTC3880_CH1, I2C_LTC3880_64, DAC_UNCALIBRATED} 5081 }, 5082 /* Saber2 design : aka G48 */ 5083 {{0,"Core", 1 << MUX_7, I2C_LTC3880_41, I2C_LTC3880_CH0, I2C_LTC3880_41, PWR_DAC_IO_SRC }, 5084 {1,"DDR", 1 << MUX_7, I2C_LTC3880_41, I2C_LTC3880_CH1, I2C_LTC3880_41, PWR_DAC_IO_SRC }, 5085 {2,"IPROC_CORE",1 << MUX_7, I2C_LTC3880_42, I2C_LTC3880_CH0, I2C_LTC3880_42, PWR_DAC_IO_SRC }, 5086 {3,"Analog",1 << MUX_7, I2C_LTC3880_42, I2C_LTC3880_CH1, I2C_LTC3880_42, PWR_DAC_IO_SRC }, 5087 {4,"3.3", 1 << MUX_7, I2C_LTM4676_43, I2C_LTC3880_CH0, I2C_LTM4676_43, PWR_DAC_IO_SRC }, 5088 {5,"1.8", 1 << MUX_7, I2C_LTM4676_43, I2C_LTC3880_CH1, I2C_LTM4676_43, PWR_DAC_IO_SRC }, 5089 }, 5090 /* Tomahawk PVT : aka G49 */ 5091 {{ 0, "Core* ", 1 << MUX_2, I2C_LTC3882_55, I2C_BOTH_CH, NULL, PWR_DAC_IO_SRC}, 5092 { 0, "ANA1 (Analog 1V)* ", 1 << MUX_2, I2C_LTC3880_41, I2C_BOTH_CH, NULL, PWR_DAC_IO_SRC}, 5093 { 0, "ANA2 (Analog 1.8V)*", 1 << MUX_2, I2C_LTC3880_42, I2C_LTC3880_CH0, NULL, PWR_DAC_IO_SRC}, 5094 { 0, "3.3V* ", 1 << MUX_2, I2C_LTC3880_42, I2C_LTC3880_CH1, NULL, PWR_DAC_IO_SRC}, 5095 { 0, "DDR_15 (1.5V)* ", 1 << MUX_2, I2C_LTC3880_43, I2C_BOTH_CH, NULL, PWR_DAC_IO_SRC}, 5096 { 0, "SP1* ", 1 << MUX_2, I2C_LTC3880_47, I2C_LTC3880_CH0, NULL, PWR_DAC_IO_SRC}, 5097 { 0, "SP2* ", 1 << MUX_2, I2C_LTC3880_47, I2C_LTC3880_CH1, NULL, PWR_DAC_IO_SRC}, 5098 { 0, "DDR_CORE (1V)* ", 1 << MUX_2, I2C_LTC3880_45, I2C_LTC3880_CH0, NULL, PWR_DAC_IO_SRC}, 5099 { 0, "SP3* ", 1 << MUX_2, I2C_LTC3880_45, I2C_LTC3880_CH1, NULL, PWR_DAC_IO_SRC}, 5100 }, 5101 /* Apache/Maverick aka G50 */ 5102 {{ 0, "Core*" , 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, NULL, DAC_UNCALIBRATED}, 5103 { 0, "Analog*", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, NULL, DAC_UNCALIBRATED}, 5104 { 0, "3.3V*" , 1 << MUX_4, I2C_LTC3880_45, I2C_BOTH_CH, NULL, DAC_UNCALIBRATED}, 5105 }, 5106 /* FireBolt5 aka G51 */ 5107 {{ 0, "Core*" , 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, NULL, DAC_UNCALIBRATED}, 5108 { 0, "Analog*" , 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, NULL, DAC_UNCALIBRATED}, 5109 { 0, "1.0V_PHY*",1 << MUX_4, I2C_LTC3884_46, I2C_BOTH_CH, NULL, DAC_UNCALIBRATED}, 5110 { 0, "3.3V*" , 1 << MUX_4, I2C_LTM4676_47, I2C_BOTH_CH, NULL, DAC_UNCALIBRATED}, 5111 }, 5112 /* HR3 SVK(BCM56160K) : aka G52 */ 5113 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5114 {0, "1.0V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5115 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5116 {0, "1.2V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5117 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5118 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5119 }, 5120 /* HR3 SVK(BCM53444K) : aka G53 */ 5121 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5122 {0, "1.0V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5123 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5124 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5125 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5126 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5127 }, 5128 /* HR3 SVK(BCM53434K) : aka G54 */ 5129 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5130 {0, "1.0V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5131 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5132 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5133 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5134 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5135 }, 5136 /* HR3 BCM56160D : aka G55 */ 5137 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5138 {0, "1.0V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5139 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5140 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5141 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5142 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5143 }, 5144 /* Metrolite design : aka G56 */ 5145 {{0,"Core", 1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH0, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 5146 {1,"Analog",1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH1, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 5147 {2,"3.3", 1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH2, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 5148 {3,"1.8", 1 << MUX_3, I2C_LTC2974_0, I2C_LTC2974_CH3, I2C_LTC2974_0, PWR_DAC_IO_SRC }, 5149 }, 5150 /* Tomahawk2 design: aka G57 */ 5151 {{0,"Analog",1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH0, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5152 {1,"1.2", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH1, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5153 {2,"1.8", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH2, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5154 {3,"3.3", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH3, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5155 {4,"Core", 1 << MUX_3, I2C_NCP81233_0, I2C_NCP81233_CH0, I2C_NCP81233_0, PWR_DAC_IO_PMBUS }, 5156 }, 5157 /* GH2 SVK(BCM53570K) : aka G58 */ 5158 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5159 {0, "1.25V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5160 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5161 {0, "1.2V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5162 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5163 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5164 }, 5165 /* GH2 SVK(BCM53570S) : aka G59 */ 5166 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5167 {0, "1.25V", 0, I2C_LTC3880_60, I2C_LTC3880_CH1, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5168 {0, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5169 {0, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5170 {0, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5171 {0, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5172 }, 5173 /* Trident3/Maverick2 design: aka G60 */ 5174 {{0,"Analog",1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH0, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5175 {1,"1.2", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH1, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5176 {2,"1.8", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH2, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5177 {3,"3.3", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH3, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5178 {4,"Core", 1 << MUX_3, I2C_NCP81233_0, I2C_NCP81233_CH0, I2C_NCP81233_0, PWR_DAC_IO_PMBUS }, 5179 }, 5180 /* Monterey BB aka G61 */ 5181 {{ 0, "Core*" , 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, NULL, DAC_UNCALIBRATED}, 5182 { 0, "Analog*", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, NULL, DAC_UNCALIBRATED}, 5183 { 0, "3.3V*" , 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH0, NULL, DAC_UNCALIBRATED}, 5184 { 0, "1.2*", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH0, I2C_LTC2974_64, PWR_DAC_IO_SRC }, 5185 { 0, "3.3dut*",1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH1,I2C_LTC2974_64, PWR_DAC_IO_SRC}, 5186 { 0, "1.8*" ,1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH2, I2C_LTC2974_64, PWR_DAC_IO_SRC}, 5187 { 0, "1.2mdio*", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH3, I2C_LTC2974_64, PWR_DAC_IO_SRC}, 5188 }, 5189 /* WH2 SVK(BCM53547K) : aka G62 */ 5190 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5191 {1, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5192 {2, "1.2V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5193 {3, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5194 {4, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5195 }, 5196 /* WH2 SVK(BCM53549K) : aka G63 */ 5197 {{0, "3.3V", 0, I2C_LTC3880_60, I2C_LTC3880_CH0, I2C_LTC3880_60, PWR_DAC_IO_SRC}, 5198 {1, "1.8V", 0, I2C_LTC3880_61, I2C_LTC3880_CH0, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5199 {2, "1.5V", 0, I2C_LTC3880_61, I2C_LTC3880_CH1, I2C_LTC3880_61, PWR_DAC_IO_SRC}, 5200 {3, "Core", 0, I2C_LTC3880_62, I2C_LTC3880_CH0, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5201 {4, "Analog", 0, I2C_LTC3880_62, I2C_LTC3880_CH1, I2C_LTC3880_62, PWR_DAC_IO_SRC}, 5202 }, 5203 /* Tomahawk3 design: aka G64 */ 5204 {{0,"MDIO", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH0, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5205 {1,"1.2", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH1, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5206 {2,"1.8", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH2, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5207 {3,"3.3", 1 << MUX_3, I2C_LTC2974_5C, I2C_LTC2974_CH3, I2C_LTC2974_5C, PWR_DAC_IO_SRC }, 5208 {4,"Analog00", 1 << MUX_3, I2C_LTM4678_40, I2C_LTM4678_CH0, I2C_LTM4678_40, PWR_DAC_IO_SRC}, 5209 {5,"Analog01", 1 << MUX_3, I2C_LTM4678_40, I2C_LTM4678_CH1, I2C_LTM4678_40, PWR_DAC_IO_SRC}, 5210 {6,"Analog10", 1 << MUX_3, I2C_LTM4678_41, I2C_LTM4678_CH0, I2C_LTM4678_41, PWR_DAC_IO_SRC}, 5211 {7,"Analog11", 1 << MUX_3, I2C_LTM4678_41, I2C_LTM4678_CH1, I2C_LTM4678_41, PWR_DAC_IO_SRC}, 5212 {8,"Core", 1 << MUX_3, I2C_ISL68127_60, I2C_ISL68127_CH1, I2C_ISL68127_60, PWR_DAC_IO_PMBUS}, 5213 /* {9,"QSFP", 1 << MUX_3, I2C_ISL68127_61, I2C_ISL68127_CH0, I2C_ISL68127_61, PWR_DAC_IO_PMBUS}, */ 5214 }, 5215 /* Helix5 design: aka G65 */ 5216 {{0,"Core*", 1 << MUX_4, I2C_LTC3884_42, I2C_BOTH_CH, NULL, DAC_UNCALIBRATED }, 5217 {0,"Analog*", 1 << MUX_4, I2C_LTC3884_43, I2C_LTC3880_CH1, NULL, DAC_UNCALIBRATED }, 5218 {0,"0.88V*", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH0, NULL, DAC_UNCALIBRATED }, 5219 {0,"3.3V_Dut*", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH1, NULL, DAC_UNCALIBRATED }, 5220 {0,"2.5V*", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH2, NULL, DAC_UNCALIBRATED }, 5221 {0,"VDD_MDIO*", 1 << MUX_4, I2C_LTC2974_63, I2C_LTC2974_CH3, NULL, DAC_UNCALIBRATED }, 5222 {0,"1.8V*", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH0, NULL, DAC_UNCALIBRATED }, 5223 {0,"1.2V*", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH1, NULL, DAC_UNCALIBRATED }, 5224 {0,"3.3V*", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH2, NULL, DAC_UNCALIBRATED }, 5225 {0,"5.0V*", 1 << MUX_4, I2C_LTC2974_64, I2C_LTC2974_CH3, NULL, DAC_UNCALIBRATED }, 5226 }, 5227 /* ENG */ 5228 {{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}, 5229 {0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}}, 5230 /* UNK */ 5231 {{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}, 5232 {0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}} 5233 }; 5234 5235 /* MAP of voltage display table lengths. 5236 * One per board, each one is the number of table entries in the 5237 * table above. 5238 * INDEXED_BY_BOARD_TYPE 5239 */ 5240 int bb_vs_all_len[] = { 5241 8, /* G5 */ 5242 14, /* G13 */ 5243 12, /* G15 */ 5244 13, /* G16 */ 5245 12, /* G17 */ 5246 10, /* G18 */ 5247 6, /* G19 */ 5248 7, /* G20 */ 5249 6, /* G21 */ 5250 5, /* G22 */ 5251 7, /* G23 */ 5252 8, /* G24 */ 5253 8, /* G25 */ 5254 5, /* G26 */ 5255 8, /* G27 */ 5256 5, /* G28 */ 5257 5, /* G29 */ 5258 6, /* G30 */ 5259 5, /* G31 */ 5260 8, /* G33 */ 5261 5, /* G34 */ 5262 7, /* G35 */ 5263 9, /* G36 */ 5264 8, /* G37 */ 5265 8, /* G38 */ 5266 8, /* G39 */ 5267 5, /* G40 */ 5268 10, /* G41 */ 5269 12, /* G42 */ 5270 8, /* G43 */ 5271 12, /* G44 */ 5272 9, /* G45 */ 5273 9, /* G46 */ 5274 8, /* G47 */ 5275 6, /* G48 */ 5276 9, /* G49 */ 5277 3, /* G50 */ 5278 4, /* G51 */ 5279 6, /* G52 */ 5280 6, /* G53 */ 5281 6, /* G54 */ 5282 6, /* G55 */ 5283 4, /* G56 */ 5284 5, /* G57 */ 5285 6, /* G58 */ 5286 6, /* G59 */ 5287 5, /* G60 */ 5288 7, /* G61*/ 5289 5, /* G62 */ 5290 5, /* G63 */ 5291 9, /* G64 */ 5292 10, /* G65 */ 5293 0, /* ENG */ 5294 0 /* UNK */ 5295 }; 5296 5297 5298 /* All Currents, per board. 5299 * For display only (only name, adc device and channel used). 5300 * The first element *Must* be the Reference voltage. 5301 * INDEXED_BY_BOARD_TYPE 5302 */ 5303 bb_current_config_t 5304 bb_current[NUM_BOARD_TYPES][MAX_VOLTAGES_PER_BOARD] = { 5305 /* Hercules: aka G5 */ 5306 {{0}}, 5307 /* Firebolt SDK design: aka G13 */ 5308 {{0}}, 5309 /* Goldwing SDK design: aka G15 */ 5310 {{0}}, 5311 /* Bradley 1G SDK design: aka G16 */ 5312 {{0}}, 5313 /* Bradley SDK design: aka G17 */ 5314 {{0}}, 5315 /* Raptor SDK design: aka G18 */ 5316 {{0}}, 5317 /* Raven SDK design: aka G19 */ 5318 {{0}}, 5319 /* Triumph SDK design : aka G20 */ 5320 {{0}}, 5321 /* Scorpion SDK design : aka G21 */ 5322 {{0}}, 5323 /* Apollo SDK design : aka G22 */ 5324 {{0}}, 5325 /* Sirius SDK design : aka G23 */ 5326 {{0}}, 5327 /* Trident SDK design : aka G24 */ 5328 {{0}}, 5329 /* Titan SDK design : aka G25 */ 5330 {{0}}, 5331 /* Hurricane SDK design: aka G26 */ 5332 {{0}}, 5333 /* Shadow SDK design : aka G26 */ 5334 {{0}}, 5335 /* Katana SDK design: aka G28 */ 5336 {{0}}, 5337 /* Enduro-2 SDK design: aka G29 */ 5338 {{0}}, 5339 /* Stardust-2 SDK design: aka G30 */ 5340 {{0}}, 5341 /* Enduro-2 SDK design: aka G31 */ 5342 {{0}}, 5343 /* Trident SDK design : aka G33 */ 5344 {{0}}, 5345 /* Triumph3 Legacy SDK design: aka G34 */ 5346 {{0}}, 5347 /* Triumph3 SDK design: aka G35 */ 5348 {{0}}, 5349 /* Caladan3 48G SVK design: aka G36 */ 5350 {{0}}, 5351 /* Caladan3 100G SVK design: aka G37 */ 5352 {{0}}, 5353 /* Trident2 SVK design : aka G38 */ 5354 {{0}}, 5355 /* Trident2 DVT design : aka G39 */ 5356 {{0}}, 5357 /* Katana2 design : aka G40 */ 5358 {{ "VDD_5V ", "adc0", I2C_ADC_CH1, 0, 0}, 5359 { "CURR_1.5 ", "adc0", I2C_ADC_CH0, 175, 0}, 5360 { "CURR_CORE ", "adc0", I2C_ADC_CH2, 66, 0}, 5361 { "CURR_ANALOG ", "adc0", I2C_ADC_CH3, 175, 0}, 5362 }, 5363 /* Greyhound design : aka G41 */ 5364 {{0}}, 5365 /* Tomahawk design : aka G42 */ 5366 {{0}}, 5367 /* Trident2+ design : aka G43 */ 5368 {{0}}, 5369 /* Trident2+ 100G design : aka G44 */ 5370 {{0}}, 5371 /* Greyhound design : aka G45 */ 5372 {{0}}, 5373 /* Greyhound design : aka G46 */ 5374 {{0}}, 5375 /* Greyhound design : aka G47 */ 5376 {{0}}, 5377 /* Saber2 design : aka G48 */ 5378 {{0}}, 5379 /* Tomahawk PVT design : aka G49 */ 5380 {{0}}, 5381 /* Apache/Maverick aka G50 */ 5382 {{0}}, 5383 /* FireBolt5 aka G51 */ 5384 {{0}}, 5385 /* HR3 SVK(BCM56160K) : aka G52 */ 5386 {{0}}, 5387 /* HR3 SVK(BCM53444K) : aka G53 */ 5388 {{0}}, 5389 /* HR3 SVK(BCM53434K) : aka G54 */ 5390 {{0}}, 5391 /* HR3 BCM56160D : aka G55 */ 5392 {{0}}, 5393 /* Metrolite design : aka G56 */ 5394 {{0}}, 5395 /* Tomahawk2 design : aka G57 */ 5396 {{0}}, 5397 /* GH2 SVK(BCM53570K) : aka G58 */ 5398 {{0}}, 5399 /* GH2 SVK(BCM53570S) : aka G59 */ 5400 {{0}}, 5401 /* Trident3/Maverick2 design : aka G60 */ 5402 {{0}}, 5403 /* Monterey aka G61 */ 5404 {{0}}, 5405 /* WH2 SVK(BCM53547K) : aka G62 */ 5406 {{0}}, 5407 /* WH2 SVK(BCM53549K) : aka G63 */ 5408 {{0}}, 5409 /* Tomahawk3 design : aka G64 */ 5410 {{0}}, 5411 /* Helix5 design : aka G65 */ 5412 {{0}}, 5413 /* ENG */ 5414 {{0}}, 5415 /* UNK */ 5416 {{0}} 5417 }; 5418 5419 5420 /* MAP of Current display table lengths. 5421 * One per board, each one is the number of table entries in the 5422 * table above. 5423 * INDEXED_BY_BOARD_TYPE 5424 */ 5425 int bb_current_len[] = { 5426 0, /* G5 */ 5427 0, /* G13 */ 5428 0, /* G15 */ 5429 0, /* G16 */ 5430 0, /* G17 */ 5431 0, /* G18 */ 5432 0, /* G19 */ 5433 0, /* G20 */ 5434 0, /* G21 */ 5435 0, /* G22 */ 5436 0, /* G23 */ 5437 0, /* G24 */ 5438 0, /* G25 */ 5439 0, /* G26 */ 5440 0, /* G27 */ 5441 0, /* G28 */ 5442 0, /* G29 */ 5443 0, /* G30 */ 5444 0, /* G31 */ 5445 0, /* G33 */ 5446 0, /* G34 */ 5447 0, /* G35 */ 5448 0, /* G36 */ 5449 0, /* G37 */ 5450 0, /* G38 */ 5451 0, /* G39 */ 5452 4, /* G40 */ 5453 0, /* G41 */ 5454 0, /* G42 */ 5455 0, /* G43 */ 5456 0, /* G44 */ 5457 0, /* G45 */ 5458 0, /* G46 */ 5459 0, /* G47 */ 5460 0, /* G48 */ 5461 0, /* G49 */ 5462 0, /* G50 */ 5463 0, /* G51 */ 5464 0, /* G52 */ 5465 0, /* G53 */ 5466 0, /* G54 */ 5467 0, /* G55 */ 5468 0, /* G56 */ 5469 0, /* G57 */ 5470 0, /* G58 */ 5471 0, /* G59 */ 5472 0, /* G60 */ 5473 0, /* G61 */ 5474 0, /* G62 */ 5475 0, /* G63 */ 5476 0, /* G64 */ 5477 0, /* G65 */ 5478 0, /* ENG */ 5479 0 /* UNK */ 5480 }; 5481 5482 bb_sequence_config_t 5483 bb_sequence[NUM_BOARD_TYPES][MAX_VOLTAGES_PER_BOARD] = { 5484 /* Hercules: aka G5 */ 5485 {{0}}, 5486 /* Firebolt SDK design: aka G13 */ 5487 {{0}}, 5488 /* Goldwing SDK design: aka G15 */ 5489 {{0}}, 5490 /* Bradley 1G SDK design: aka G16 */ 5491 {{0}}, 5492 /* Bradley SDK design: aka G17 */ 5493 {{0}}, 5494 /* Raptor SDK design: aka G18 */ 5495 {{0}}, 5496 /* Raven SDK design: aka G19 */ 5497 {{0}}, 5498 /* Triumph SDK design : aka G20 */ 5499 {{0}}, 5500 /* Scorpion SDK design : aka G21 */ 5501 {{0}}, 5502 /* Apollo SDK design : aka G22 */ 5503 {{0}}, 5504 /* Sirius SDK design : aka G23 */ 5505 {{0}}, 5506 /* Trident SDK design : aka G24 */ 5507 {{0}}, 5508 /* Titan SDK design : aka G25 */ 5509 {{0}}, 5510 /* Hurricane SDK design: aka G26 */ 5511 {{0}}, 5512 /* Shadow SDK design : aka G26 */ 5513 {{0}}, 5514 /* Katana SDK design: aka G28 */ 5515 {{0}}, 5516 /* Enduro-2 SDK design: aka G29 */ 5517 {{0}}, 5518 /* Stardust-2 SDK design: aka G30 */ 5519 {{0}}, 5520 /* Enduro-2 SDK design: aka G31 */ 5521 {{0}}, 5522 /* Trident SDK design : aka G33 */ 5523 {{0}}, 5524 /* Triumph3 Legacy SDK design: aka G34 */ 5525 {{0}}, 5526 /* Triumph3 SDK design: aka G35 */ 5527 {{0}}, 5528 /* Caladan3 48G SVK design: aka G36 */ 5529 {{0}}, 5530 /* Caladan3 100G SVK design: aka G37 */ 5531 {{0}}, 5532 /* Trident2 SVK design : aka G38 */ 5533 {{0}}, 5534 /* Trident2 DVT design : aka G39 */ 5535 {{0}}, 5536 /* Katana2 design : aka G40 */ 5537 {{0}}, 5538 /* Greyhound Design : aka G41 */ 5539 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5540 {"2.5", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5541 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5542 {"1.5", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5543 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5544 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5545 {"3.3_EXT", NO_MUX, I2C_LTC3880_64, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5546 {"2.5_EXT", NO_MUX, I2C_LTC3880_64, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5547 {"1.1_DDR", NO_MUX, I2C_LTC3880_65, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5548 {"1.1_EXTPHY", NO_MUX, I2C_LTC3880_65, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5549 }, 5550 /* Tomahawk Design : aka G42 */ 5551 {{"Analog", 1 << MUX_3, "ltc3882-1", I2C_BOTH_CH, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5552 {"3.3", 1 << MUX_3, "ltc3882-0", I2C_BOTH_CH, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5553 {"1.25", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5554 {"1.8", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5555 }, 5556 /* Trident2+ : aka G43 */ 5557 {{0}}, 5558 /* Trident2+ 100G: aka G44 */ 5559 {{"Analog", 1 << MUX_3, "ltc3882-1", I2C_BOTH_CH, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5560 {"3.3", 1 << MUX_3, "ltc3882-0", I2C_BOTH_CH, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5561 {"1.25", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5562 {"1.8", 1 << MUX_3, "ltc3880", I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5563 }, 5564 /* Greyhound Design : aka G45 */ 5565 {{0}}, 5566 /* Greyhound Design : aka G46 */ 5567 {{0}}, 5568 /* Greyhound Design : aka G47 */ 5569 {{0}}, 5570 /* Saber2 Design : aka G48 */ 5571 {{"Core", 1 << MUX_7, I2C_LTC3880_41, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5572 {"DDR", 1 << MUX_7, I2C_LTC3880_41, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5573 {"IPROC_CORE", 1 << MUX_7, I2C_LTC3880_42, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5574 {"Analog", 1 << MUX_7, I2C_LTC3880_42, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5575 {"3.3", 1 << MUX_7, I2C_LTM4676_43, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5576 {"1.8", 1 << MUX_7, I2C_LTM4676_43, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5577 }, 5578 /* Tomahawk PVT Design : aka G49 */ 5579 {{"Core", 1 << MUX_2, I2C_LTC3882_55, I2C_BOTH_CH, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5580 {"ANA1", 1 << MUX_2, I2C_LTC3880_41, I2C_BOTH_CH, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5581 {"ANA2", 1 << MUX_2, I2C_LTC3880_42, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5582 {"3.3V", 1 << MUX_2, I2C_LTC3880_42, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5583 {"DDR_15", 1 << MUX_2, I2C_LTC3880_43, I2C_BOTH_CH, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5584 {"SP1", 1 << MUX_2, I2C_LTC3880_47, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5585 {"SP2", 1 << MUX_2, I2C_LTC3880_47, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5586 {"DDR_Core", 1 << MUX_2, "ltc3880", I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5587 {"SP3", 1 << MUX_2, "ltc3880", I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5588 }, 5589 /* Apache/Maverick aka G50 */ 5590 {{0}}, 5591 /* FireBolt5 aka G51 */ 5592 {{0}}, 5593 /* HR3 SVK(BCM56160K) : aka G52 */ 5594 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5595 {"1.0", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5596 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5597 {"1.2_DDR4", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5598 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5599 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5600 }, 5601 /* HR3 SVK(BCM53444K) : aka G53 */ 5602 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5603 {"1.0", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5604 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5605 {"1.5_DDR3", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5606 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5607 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5608 }, 5609 /* HR3 SVK(BCM53434K) : aka G54 */ 5610 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5611 {"1.0", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5612 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5613 {"1.5_DDR3", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5614 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5615 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5616 }, 5617 /* HR3 BCM56160D : aka G55 */ 5618 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5619 {"1.0", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5620 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5621 {"1.5_DDR3", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5622 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5623 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5624 }, 5625 /* Metrolite aka G56 */ 5626 {{0}}, 5627 /* Tomahawk2 aka G57 */ 5628 {{0}}, 5629 /* GH2 SVK(BCM53570K) : aka G58 */ 5630 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5631 {"1.25", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5632 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5633 {"1.2_DDR4", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5634 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5635 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5636 }, 5637 /* GH2 SVK(BCM53570S) : aka G59 */ 5638 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5639 {"1.25", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5640 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5641 {"1.5_DDR3", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5642 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5643 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5644 }, 5645 /* Trident3/Maverick2 aka G60 */ 5646 {{0}}, 5647 /* Monterey aka G61 */ 5648 {{0}}, 5649 /* WH2 SVK(BCM53547K) : aka G62 */ 5650 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5651 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5652 {"1.2_DDR4", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5653 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5654 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5655 }, 5656 /* WH2 SVK(BCM53549K) : aka G63 */ 5657 {{"3.3", NO_MUX, I2C_LTC3880_60, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5658 {"1.8", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5659 {"1.5_DDR3", NO_MUX, I2C_LTC3880_61, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5660 {"Core", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH0, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5661 {"Analog", NO_MUX, I2C_LTC3880_62, I2C_LTC3880_CH1, LTC_SEQ_MAX, LTC_SEQ_MIN, 0}, 5662 }, 5663 /* Tomahawk3 aka G64 */ 5664 {{0}}, 5665 /* Helix5 aka G65 */ 5666 {{0}}, 5667 /* ENG */ 5668 {{0}}, 5669 /* UNK */ 5670 {{0}} 5671 }; 5672 5673 5674 /* MAP of Current display table lengths. 5675 * One per board, each one is the number of table entries in the 5676 * table above. 5677 * INDEXED_BY_BOARD_TYPE 5678 */ 5679 int bb_sequence_len[] = { 5680 0, /* G5 */ 5681 0, /* G13 */ 5682 0, /* G15 */ 5683 0, /* G16 */ 5684 0, /* G17 */ 5685 0, /* G18 */ 5686 0, /* G19 */ 5687 0, /* G20 */ 5688 0, /* G21 */ 5689 0, /* G22 */ 5690 0, /* G23 */ 5691 0, /* G24 */ 5692 0, /* G25 */ 5693 0, /* G26 */ 5694 0, /* G27 */ 5695 0, /* G28 */ 5696 0, /* G29 */ 5697 0, /* G30 */ 5698 0, /* G31 */ 5699 0, /* G33 */ 5700 0, /* G34 */ 5701 0, /* G35 */ 5702 0, /* G36 */ 5703 0, /* G37 */ 5704 0, /* G38 */ 5705 0, /* G39 */ 5706 0, /* G40 */ 5707 10, /* G41 */ 5708 4, /* G42 */ 5709 0, /* G43 */ 5710 4, /* G44 */ 5711 0, /* G45 */ 5712 0, /* G46 */ 5713 0, /* G47 */ 5714 6, /* G48 */ 5715 9, /* G49 */ 5716 0, /* G50 */ 5717 0, /* G51 */ 5718 6, /* G52 */ 5719 6, /* G53 */ 5720 6, /* G54 */ 5721 6, /* G55 */ 5722 0, /* G56 */ 5723 0, /* G57 */ 5724 6, /* G58 */ 5725 6, /* G59 */ 5726 0, /* G60 */ 5727 0, /* G61 */ 5728 5, /* G62 */ 5729 5, /* G63 */ 5730 0, /* G64 */ 5731 0, /* G65 */ 5732 0, /* ENG */ 5733 0 /* UNK */ 5734 }; 5735 5736 5737 /* 5738 * Tc=0.000000 5739 * 5740 * Tp=0.000000 5741 * 5742 * Rp = (10.000000) - Resistor for calibration current measurement 5743 * XXX measures voltage drop across 5744 * this resistor 5745 * 5746 * TCoeff=0.003900 - Temperature Coefficient 5747 * 5748 * Rcu=0.0000006787 - Resistivity 5749 * 5750 * Lcal=1.000000 - Length of calibration strip 5751 * 5752 * Lpwr=1.000000 - Length of Power Strip 5753 * 5754 * Wcal=0.300000 - Width of calibration strip 5755 * 5756 * Wpwr=0.700000 - Width of Power Strip 5757 * 5758 * Vdrop_cal_core - Voltage Drop across calibration strip 5759 * 5760 * Vdrop_cal_phy - Voltage Drop across calibration strip 5761 * 5762 * Vdrop_cal_io - Voltage Drop across calibration strip 5763 * 5764 * Vdrop_coreA/Vdrop_coreB - Voltage Drop at the core calibration strip. 5765 * 5766 * Vcal_core - Core Voltage measured at the source. 5767 * 5768 * Vcal_phy - Phy voltage measured at the source 5769 * 5770 * Vcal_io - IO voltage measured at the source. 5771 * 5772 * Ical_core - Calculated using Vcal_core and Resistance 5773 * value of Rp 5774 * 5775 * Ical_phy - Calculated using Vcal_core and Resistance 5776 * value of Rp 5777 * 5778 * Ical_io - Calculated using Vcal_core and Resistance 5779 * value of Rp 5780 * 5781 * Rseg_coreA/Rseg_coreB - Resistance value of calibration strip is 5782 * Rseg_phy estimated using the geometry of the 5783 * calibration strip and the resistance 5784 * computed for the Core calibration strip. 5785 * 5786 * IcoreA - Calculated using Vdrop_coreA and Resistance 5787 * value of the calibration strip. 5788 * Resistance value of calibration strip is 5789 * estimated using the geometry of the 5790 * calibration strip and the resistance 5791 * computed for the Core calibration strip. 5792 * 5793 * Rcal_core - Resistance of calibration strip calculated 5794 * using the drop measured across the 5795 * calibration strip and the current flowing 5796 * through it. 5797 * Can also be extimated using the Resistivity 5798 * of copper, temprature and geometry of the 5799 * calibration strip. 5800 * 5801 * Rcal_phy - Resistance of calibration strip calculated 5802 * using the drop measured across the 5803 * calibration strip and the current flowing 5804 * through it. 5805 * Can also be extimated using the Resistivity 5806 * of copper, temprature and geometry of the 5807 * calibration strip. 5808 */ 5809 5810 #ifdef COMPILER_HAS_DOUBLE 5811 5812 /* Power computation definitions */ 5813 #define STD_RP 10.00 /* 10 Ohms, defines cal currents */ 5814 #define STD_LENGTH 2.00 /* Inches, length of CAL/PWR strips */ 5815 #define STD_WC 0.100 /* Inches, width of CAL strip */ 5816 #define STD_WP 0.700 /* Inches, width of PWR strip */ 5817 #define STD_RGAIN_PWR 130.0 /* RGp, sets gain of LT1167A amp */ 5818 #define STD_RGAIN_CAL 49.90 /* RGc, sets gain of LT1167A amp */ 5819 5820 /* The LT1167s are configured to output 100s of milliamps. */ 5821 /* Lower than this (or negative) indicates a probable empty */ 5822 /* socket. */ 5823 #define MIN_AMPLIFIED_VOLTAGE_DROP 0.050 5824 5825 /* Computes actual voltage drop from (amplified) value at LT1167A's output */ 5826 #define GAIN(v,r) ( (v) / (1 + (49900.0/(r))) ) 5827 5828 #define VNULL -9.99 /* Uninitialized voltage value */ 5829 #define RNULL 999.999 /* Uninitialized resistance value */ 5830 5831 /* Thickness constants, based on PCB manufacturing parameters */ 5832 #define RCu 6.787E-07 /* Resistivity of Copper (Ohms * Inches) */ 5833 #define TCoeff 0.0039 /* Thermal Coefficient (1 / C) */ 5834 5835 #else /* !COMPILER_HAS_DOUBLE */ 5836 5837 /* Power computation definitions */ 5838 #define STD_RP 10000 /* mOhms, defines cal currents */ 5839 #define STD_LENGTH 2000 /* 1/1000 Inches, length of CAL/PWR strips */ 5840 #define STD_WC 100 /* 1/1000 Inches, width of CAL strip */ 5841 #define STD_WP 700 /* 1/1000 Inches, width of PWR strip */ 5842 #define STD_RGAIN_PWR 130000 /* RGp, sets gain of LT1167A amp */ 5843 #define STD_RGAIN_CAL 49900 /* RGc, sets gain of LT1167A amp */ 5844 5845 /* The LT1167s are configured to output 100s of milliamps. */ 5846 /* Lower than this (or negative) indicates a probable empty */ 5847 /* socket. */ 5848 #define MIN_AMPLIFIED_VOLTAGE_DROP 50000 5849 5850 /* Computes actual voltage drop from (amplified) value at LT1167A's output */ 5851 #define GAIN(v,r) ( (v) / (1 + (49900000/(r))) ) 5852 5853 #define VNULL -9990000 /* Uninitialized voltage value */ 5854 #define RNULL 999999 /* Uninitialized resistance value */ 5855 5856 /* Thickness constants, based on PCB manufacturing parameters */ 5857 #define RCu 6787 /* Resistivity of Copper (Ohms * Inches) * 1e-10 */ 5858 #define TCoeff 39 /* Thermal Coefficient (1 / C) * 1e-4 */ 5859 5860 #define RCAL_MUL 100 /* Rcal mulyiplier for better precision */ 5861 5862 #endif /* COMPILER_HAS_DOUBLE */ 5863 5864 /* 5865 * Control Voltage, and SDRAM/Core Clocks on P48 integrated board. 5866 */ 5867 char cmd_bb_usage[] = 5868 "Baseboard commands (bb) for I2C satellite devices\n" 5869 "Usages:\n\t" 5870 #ifdef COMPILER_STRING_CONST_LIMIT 5871 " bb board | clock | spread | voltage | power | temperature\n" 5872 #else 5873 " bb board\n\t" 5874 " - show board type detected\n\t" 5875 " bb clock [Core_A SDRAM_A Core_B SDRAM_B Turbo] value\n\t" 5876 " - set specified clock speed.\n\t" 5877 " bb spread [Core_A SDRAM_A Core_B SDRAM_B Turbo] value\n\t" 5878 " - value: 0=normal,1=-0.5%,2=+/-0.5%,3=+/-0.25%,4=+/-0.38%\n\t" 5879 " bb voltage [A B TRef PHY] [<volts>|calibrate|nominal]\n\t" 5880 " - set voltage output, if not specified, value is displayed.\n\t" 5881 " - if \"calibrate\" is specified, calibrate specified DAC.\n\t" 5882 " - if \"nominal\" is specified, DAC set to mid-range.\n\t" 5883 " bb sequence [source|all] [=time_ms>]\n\t" 5884 " - Set power-up sequence timing, if not specified, set value is displayed.\n\t" 5885 " - if \"all\" \"time_ms\" is specified, all the sequences are configured.\n\t" 5886 " bb power\n\t" 5887 " - computer power utilization.\n\t" 5888 " bb temperature Tp Tc\n\t" 5889 " - trace temperature computation.\n\t" 5890 " - Tp :PHY trace thickness.\n\t" 5891 " - Tc :Core trace thickness.\n\t" 5892 " bb thickness Tp Tc\n\t" 5893 " - trace thickness computation.\n\t" 5894 " - Tp :PHY trace temperature.\n\t" 5895 " - Tc :Core trace temperature.\n\t" 5896 " bb pot number value\n\t" 5897 " - set potentiometer.\n\t" 5898 " - number: potentiometer number 0..7\n\t" 5899 " - value : value to set 0..255\n\t" 5900 "NOTE: calibration of DAC is performed (automatically) only once.\n" 5901 #endif 5902 ; 5903 5904 5905 cmd_result_t 5906 cmd_bb(int unit, args_t *a) 5907 { 5908 int i, bx, clk_unit, pll, adc, dac = -1, mux, rv = SOC_E_NONE; 5909 char *function = ARG_GET(a); 5910 char *source = ARG_GET(a); 5911 char *value = ARG_GET(a); 5912 uint32 flags = 0; 5913 #ifdef COMPILER_HAS_DOUBLE 5914 double volts, clockval, curr_zero = 1.0, curr_sens; 5915 double dac_op_data=0, current=0, power=0, total_power=0, time_ms; 5916 #else 5917 int volts, clockval, curr_zero = 1, curr_sens; 5918 int dac_op_data=0, current=0, power=0, total_power=0, time_ms; 5919 #endif 5920 int show_cal = 0; 5921 i2c_adc_t adc_data; 5922 bb_type_t* baseboard = NULL; 5923 5924 COMPILER_REFERENCE(curr_sens); 5925 COMPILER_REFERENCE(curr_zero); 5926 if (! sh_check_attached(ARG_CMD(a), unit)) 5927 return CMD_FAIL; 5928 5929 if ( (! function) ) 5930 return CMD_USAGE ; 5931 5932 /* Get board type */ 5933 baseboard = soc_get_board(); 5934 if(!baseboard || (baseboard->bbcmd_flags == BB_NONE)){ 5935 cli_out("Error: baseboard command unavailable on %s\n", 5936 BaseboardName); 5937 return CMD_FAIL; 5938 } 5939 5940 if (!sal_strcasecmp(function, "board")) { 5941 cli_out("Baseboard: %s (type %d)\n", 5942 BaseboardName, baseboard->type); 5943 return CMD_OK; 5944 } 5945 5946 /* Get board index */ 5947 bx = baseboard->type; 5948 5949 /* Configure or display clock frequency or spread-spectrum */ 5950 if(!sal_strcasecmp(function,"clock") || 5951 !sal_strcasecmp(function,"spread") ){ 5952 /* Check for supported clock chips (W311, CY22393, CY22150) */ 5953 if ( !(baseboard->bbcmd_flags & BB_CLK) ) { 5954 cli_out("Baseboard clock configuration function not supported.\n"); 5955 cli_out("use clocks or xclocks command instead.\n"); 5956 return CMD_FAIL; 5957 } 5958 /* Set clock speed or spread spectrum */ 5959 if( source && value ) { 5960 /* First, find clock table entry ... */ 5961 for( i = 0; i < bb_clock_len[bx]; i++) { 5962 if ( !sal_strcasecmp(bb_clocks[bx][i].name, source)) 5963 break; 5964 if ( (bb_clocks[bx][i].alias != NULL) && 5965 !sal_strcasecmp(bb_clocks[bx][i].alias, source)) 5966 break; 5967 } 5968 if (i == bb_clock_len[bx]) { /* unknown board clock */ 5969 cli_out("ERROR: unknown clock source: %s\n", source); 5970 cli_out("ERROR: valid clocks are"); 5971 for(i = 0; i < bb_clock_len[bx]; i++) { 5972 cli_out(" %s", bb_clocks[bx][i].name); 5973 } 5974 cli_out("\n"); 5975 return CMD_FAIL; 5976 } 5977 5978 /* If indicated, set the MUX appropriately */ 5979 if (bb_clocks[bx][i].mux != NO_MUX) { 5980 /* Open MUX (lpt0) device */ 5981 #ifdef SHADOW_SVK 5982 char *name; 5983 uint8 channel; 5984 /* Open MUX device */ 5985 name = _i2c_mux_default_dev_name_get(); 5986 if ( (mux = _i2c_mux_open(unit, flags, 0, name)) < 0) { 5987 cli_out("%s: cannot open I2C device %s: %s\n", 5988 ARG_CMD(a), name, bcm_errmsg(mux)); 5989 return CMD_FAIL; 5990 } 5991 5992 /* Set mux value so we can see the device when we try to open it*/ 5993 channel = _i2c_mux_channel_get(unit, bb_clocks[bx][i].mux); 5994 if( (rv = bcm_i2c_write(unit, mux, 0, 5995 &channel, 1)) < 0){ 5996 5997 cli_out("ERROR: I2C write failed: %s\n", 5998 bcm_errmsg(rv)); 5999 return CMD_FAIL; 6000 } 6001 #else 6002 if ( (mux = bcm_i2c_open(unit, _i2c_mux_default_dev_name_get(), flags, 0)) < 0) { 6003 cli_out("%s: cannot open I2C device %s: %s\n", 6004 ARG_CMD(a), I2C_LPT_0, bcm_errmsg(mux)); 6005 return CMD_FAIL; 6006 } 6007 6008 /* Set mux value so we can see the device when we try to open it*/ 6009 if( (rv = bcm_i2c_write(unit, mux, 0, 6010 &bb_clocks[bx][i].mux, 1)) < 0){ 6011 cli_out("ERROR: I2C write failed: %s\n", 6012 bcm_errmsg(rv)); 6013 return CMD_FAIL; 6014 } 6015 #endif /* SHADOW_SVK */ 6016 } /* Need to set MUX for the clock chip */ 6017 6018 /* Open clock chip, this could be on the second bus, 6019 * so we need to check for that here .. 6020 */ 6021 if ( bb_clocks[bx][i].unit != unit){ 6022 clk_unit = bb_clocks[bx][i].unit; 6023 cli_out("NOTICE: clock chip on i2c%d\n", clk_unit); 6024 } 6025 else 6026 clk_unit = unit; 6027 6028 /* Open clock chip, this will cause a probe to happen 6029 * if not already done. 6030 */ 6031 if ( (pll = bcm_i2c_open(clk_unit, 6032 bb_clocks[bx][i].device, flags, 0)) < 0) { 6033 cli_out("%s: cannot open I2C device %s: %s\n", 6034 ARG_CMD(a), bb_clocks[bx][i].device, bcm_errmsg(pll)); 6035 return CMD_FAIL; 6036 } 6037 6038 /* 6039 * Use Cypress CY22393x (or CY22150) 6040 * Both devices are named "clk0" 6041 */ 6042 #ifdef COMPILER_HAS_DOUBLE 6043 clockval = atof( value ) ; 6044 #else 6045 /* Parse input in MHz and convert to Hz */ 6046 clockval = _shr_atof_exp10(value, 6); 6047 #endif 6048 /* Set speed */ 6049 if(!sal_strncasecmp(function,"clock",sal_strlen(function))){ 6050 if (!sal_strcasecmp(bb_clocks[bx][i].name, "CPU")) { 6051 cli_out("NOTICE: changing CPU clock requires removal" 6052 " of jumper JP302.\n"); 6053 } 6054 /* Set speed */ 6055 if ( (bcm_i2c_ioctl(clk_unit, pll, 6056 bb_clocks[bx][i].xpll, 6057 &clockval, 0) < 0)) { 6058 #ifdef COMPILER_HAS_DOUBLE 6059 cli_out("ERROR: failed to set %s clock to %2.2fMHz\n", 6060 bb_clocks[bx][i].name, clockval); 6061 #else 6062 cli_out("ERROR: failed to set %s clock to %d.%02dMHz\n", 6063 bb_clocks[bx][i].name, INT_FRAC_2PT_4(clockval)); 6064 #endif 6065 return CMD_FAIL; 6066 } 6067 } 6068 else{ 6069 /* Spread spectrum mode */ 6070 cli_out("ERROR: CY22xxx does not have spread spectrum.\n"); 6071 return CMD_FAIL; 6072 } 6073 return CMD_OK; 6074 6075 } /* (source && value), set a clock */ 6076 else { 6077 /* Display single clock or all clocks */ 6078 i = 0; /* Top of table unless a specific clock is requested */ 6079 if (source) { 6080 /* Request to show a single clock. Find it first... */ 6081 for( ; i < bb_clock_len[bx]; i++) { 6082 if ( !sal_strcasecmp(bb_clocks[bx][i].name, source)) 6083 break; 6084 if ( (bb_clocks[bx][i].alias != NULL) && 6085 !sal_strcasecmp(bb_clocks[bx][i].alias, source)) 6086 break; 6087 } 6088 if (i == bb_clock_len[bx]) { /* unknown board clock */ 6089 cli_out("ERROR: unknown clock source: %s\n", source); 6090 6091 cli_out("ERROR: valid clocks are"); 6092 for(i = 0; i < bb_clock_len[bx]; i++) { 6093 6094 cli_out(" %s", bb_clocks[bx][i].name); 6095 } 6096 6097 cli_out("\n"); 6098 return CMD_FAIL; 6099 } 6100 } /* Requested a single clock display */ 6101 6102 /* Already have entry number (single clock), or we'll go */ 6103 /* through the whole clock table entry (all clocks)... */ 6104 for( ; i < bb_clock_len[bx]; i++) { 6105 6106 /* If indicated, set the MUX appropriately */ 6107 if (bb_clocks[bx][i].mux != 0xFF) { 6108 #ifdef SHADOW_SVK 6109 char *name = I2C_LPT_0; 6110 uint8 channel; 6111 mux = _i2c_mux_open(unit, flags, 0, name); 6112 if (mux < 0) { 6113 name = I2C_MUX_6; 6114 } 6115 if ( (mux = _i2c_mux_open(unit, flags, 0, name)) < 0) { 6116 cli_out("Could not open %s for mux selection:%s\n", 6117 name, bcm_errmsg(mux)); 6118 return CMD_FAIL; 6119 } 6120 6121 /* Set mux value so we can see the device ...*/ 6122 channel = _i2c_mux_channel_get(unit, bb_clocks[bx][i].mux); 6123 if( (rv = bcm_i2c_write(unit, mux, 0, 6124 &channel, 1)) < 0){ 6125 cli_out("Error: write of %s byte failed:%s\n", 6126 name, bcm_errmsg(rv)); 6127 return CMD_FAIL; 6128 } 6129 #else 6130 /* Open MUX (lpt0) device */ 6131 if ( (mux = bcm_i2c_open(unit, I2C_LPT_0, flags, 0)) < 0) { 6132 cli_out("Could not open %s for mux selection:%s\n", 6133 I2C_LPT_0, bcm_errmsg(mux)); 6134 return CMD_FAIL; 6135 } 6136 /* Set mux value so we can see the device ...*/ 6137 if( (rv = bcm_i2c_write(unit, 6138 mux, 0, 6139 &bb_clocks[bx][i].mux, 1)) < 0){ 6140 cli_out("Error: write of lpt byte failed:%s\n", 6141 bcm_errmsg(rv)); 6142 return CMD_FAIL; 6143 } 6144 #endif /* SHADOW_SVK */ 6145 } /* Need to set MUX for the clock chip */ 6146 if ( bb_clocks[bx][i].unit != unit){ 6147 clk_unit = bb_clocks[bx][i].unit; 6148 cli_out("NOTICE: clock chip on i2c%d\n", clk_unit); 6149 } 6150 else 6151 clk_unit = unit; 6152 6153 /* Open clock chip */ 6154 if ( (pll = bcm_i2c_open(clk_unit, 6155 bb_clocks[bx][i].device, 6156 flags, 0)) < 0) { 6157 cli_out("Could not open %s for PLL speed selection:%s\n", 6158 I2C_PLL_0, bcm_errmsg(pll)); 6159 return CMD_FAIL; 6160 } 6161 6162 /* CY2239x or CY22150 clock chip */ 6163 /* Get clock speed */ 6164 clockval = 0; 6165 if ( (bcm_i2c_ioctl(clk_unit, pll, 6166 I2C_XPLL_GET_OP(bb_clocks[bx][i].xpll), 6167 &clockval, 0) < 0)){ 6168 cli_out("Error: failed to retrieve clock speed.\n"); 6169 } 6170 #ifdef COMPILER_HAS_DOUBLE 6171 cli_out("\t\"%s\" clock running at %2.2fMhz\n", 6172 bb_clocks[bx][i].name, clockval); 6173 #else 6174 cli_out("\t\"%s\" clock running at %d.%02dMhz\n", 6175 bb_clocks[bx][i].name, INT_FRAC_2PT_4(clockval)); 6176 #endif 6177 if (source) 6178 break; /* ... if showing single clock only */ 6179 } /* For each entry in the bb_clocks[] table */ 6180 return CMD_OK; 6181 } /* display clock(s) */ 6182 } /* function is "clock" or "spread" */ 6183 6184 /* Power, Thickness, and Temperature computations */ 6185 if(!sal_strncasecmp(function,"power",sal_strlen(function)) || 6186 (!sal_strncasecmp(function,"thickness",sal_strlen(function))) || 6187 (!sal_strncasecmp(function,"temperature",sal_strlen(function)))){ 6188 /* Check for support of these functions... */ 6189 if ((baseboard->bbcmd_flags & BB_PWR)) { 6190 int op = 0; 6191 #define BB_OP_POWER 1 6192 #define BB_OP_TEMP 2 6193 #define BB_OP_THICK 3 6194 6195 #ifdef COMPILER_HAS_DOUBLE 6196 double Rp, l_cal, l_pwr, w_cal, w_pwr, RGp, RGc; 6197 double VcoreA= VNULL, Vdrop_coreA= VNULL; 6198 double VcoreB= VNULL, Vdrop_coreB= VNULL; 6199 double Vphy= VNULL, Vdrop_phy= VNULL; 6200 double Vio= VNULL, Vdrop_io= VNULL; 6201 double Vcal_core= VNULL, Vdrop_cal_core= VNULL; 6202 double Vcal_phy= VNULL, Vdrop_cal_phy= VNULL; 6203 double Vcal_io= VNULL, Vdrop_cal_io= VNULL; 6204 double Ical_core = 0, Rcal_core = 0; 6205 double Ical_phy = 0, Rcal_phy = 0; 6206 double Ical_io = 0, Rcal_io = 0; 6207 double Rseg_coreA, IcoreA, PcoreA; 6208 double Rseg_coreB, IcoreB, PcoreB; 6209 double Rseg_phy, Iphy, Pphy; 6210 double Rseg_io, Iio, Pio; 6211 double tCore, tPhy, Tp, Tc; 6212 #else 6213 int Rp, l_cal, l_pwr, w_cal, w_pwr, RGp, RGc; 6214 int VcoreA= VNULL, Vdrop_coreA= VNULL; 6215 int VcoreB= VNULL, Vdrop_coreB= VNULL; 6216 int Vphy= VNULL, Vdrop_phy= VNULL; 6217 int Vio= VNULL, Vdrop_io= VNULL; 6218 int Vcal_core= VNULL, Vdrop_cal_core= VNULL; 6219 int Vcal_phy= VNULL, Vdrop_cal_phy= VNULL; 6220 int Vcal_io= VNULL, Vdrop_cal_io= VNULL; 6221 int Ical_core = 0, Rcal_core = 0; 6222 int Ical_phy = 0, Rcal_phy = 0; 6223 int Ical_io = 0, Rcal_io = 0; 6224 int Rseg_coreA, IcoreA, PcoreA; 6225 int Rseg_coreB, IcoreB, PcoreB; 6226 int Rseg_phy, Iphy, Pphy; 6227 int Rseg_io, Iio, Pio; 6228 int tCore, tPhy, Tp, Tc; 6229 int t1; 6230 char *s1; 6231 6232 COMPILER_REFERENCE(Rseg_coreB); 6233 if (SOC_IS_XGS(unit)) { 6234 s1 = "Analog"; 6235 } else { 6236 s1 = "Phy"; 6237 } 6238 #endif 6239 6240 /* Define the geometries and gains of the */ 6241 /* calibration and power measurement strips. */ 6242 6243 Rp = STD_RP; /* Calibration current resistor */ 6244 l_cal = STD_LENGTH; /* Length of calibration strip */ 6245 l_pwr = STD_LENGTH; /* Length of power strip */ 6246 w_cal = STD_WC; /* Width of calibration strip */ 6247 w_pwr = STD_WP; /* Width of power strip */ 6248 RGc = STD_RGAIN_CAL; /* Gain of calibration strip voltage amp */ 6249 RGp = STD_RGAIN_PWR; /* Gain of power strip voltage amp */ 6250 6251 /* Special case boards with different dimensions/parameters */ 6252 6253 #ifdef COMPILER_HAS_DOUBLE 6254 if (bx == G13) { 6255 /* Firebolt, Easyrider SDKs */ 6256 l_cal = 1.0; 6257 l_pwr = 1.0; 6258 w_cal = 0.3; 6259 } 6260 else if ((bx == G15) || (bx == G16) || (bx == G17)) { 6261 /* Goldwing, Bradley SDKs */ 6262 l_cal = 1.0; 6263 l_pwr = 1.0; 6264 w_cal = 0.3; 6265 } else if ((bx == G18) || (bx == G19)) { 6266 /* Raptor and Raven */ 6267 Rp = 5.0; 6268 l_cal = 1.0; 6269 l_pwr = 1.0; 6270 w_cal = 0.3; 6271 } 6272 #else 6273 if (bx == G13) { 6274 /* Firebolt, Easyrider SDKs */ 6275 l_cal = 1000; 6276 l_pwr = 1000; 6277 w_cal = 300; 6278 } else if ((bx == G15) || (bx == G16) || (bx == G17)) { 6279 /* Goldwing, Bradley SDKs */ 6280 l_cal = 1000; 6281 l_pwr = 1000; 6282 w_cal = 300; 6283 } else if ((bx == G18) || (bx == G19)) { 6284 /* Raptor and Raven */ 6285 Rp = 5.0; 6286 l_cal = 1.0; 6287 l_pwr = 1.0; 6288 w_cal = 0.3; 6289 } 6290 #endif 6291 /* Select computation */ 6292 if(!sal_strncasecmp(function,"thickness",sal_strlen(function))){ 6293 op = BB_OP_THICK; 6294 if( !source || !value) 6295 return CMD_USAGE; 6296 #ifdef COMPILER_HAS_DOUBLE 6297 Tp = atof(source); 6298 Tc = atof(value); 6299 #else 6300 /* Temperature is 1/10 C */ 6301 Tp = _shr_atof_exp10(source, 1); 6302 Tc = _shr_atof_exp10(value, 1); 6303 #endif 6304 } else if(!sal_strncasecmp(function,"temperature", 6305 sal_strlen(function))){ 6306 op = BB_OP_TEMP; 6307 if( !source || !value) 6308 return CMD_USAGE; 6309 #ifdef COMPILER_HAS_DOUBLE 6310 Tp = atof(source); 6311 Tc = atof(value); 6312 #else 6313 Tp = _shr_atof_exp10(source, 6); 6314 Tc = _shr_atof_exp10(value, 6); 6315 #endif 6316 } else { 6317 op = BB_OP_POWER; 6318 Tp = Tc = 0; 6319 } 6320 6321 /* Collect all voltages */ 6322 for(i = 0; i < bb_vs_all_len[bx]; i++){ 6323 if ( (adc = bcm_i2c_open(unit, 6324 bb_vs_all[bx][i].adc, 6325 flags, 0)) < 0) { 6326 cli_out("Could not open %s:%s\n", 6327 bb_vs_all[bx][i].adc, 6328 bcm_errmsg(adc)); 6329 return CMD_FAIL; 6330 } 6331 /* Display voltage */ 6332 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 6333 &adc_data, bb_vs_all[bx][i].chan) < 0)) { 6334 cli_out("Error: failed to perform A/D conversions.\n"); 6335 } 6336 6337 /* Assign each voltage to the proper Vxxx variable 6338 * based upon bb_vs_all[bx][i].flags. 6339 * VcoreA PWR_CORE_A_SRC 6340 * Vdrop_coreA PWR_CORE_A_DROP 6341 * VcoreB PWR_CORE_B_SRC 6342 * Vdrop_coreB PWR_CORE_B_DROP 6343 * Vphy PWR_PHY_SRC 6344 * Vdrop_phy PWR_PHY_DROP 6345 * Vcal_core PWR_CORECAL_SRC 6346 * Vdrop_cal_core PWR_CORECAL_DROP 6347 * Vcal_phy PWR_PHYCAL_SRC 6348 * Vdrop_cal_phy PWR_PHYCAL_DROP 6349 */ 6350 6351 /* 6352 * PWR_CORE_A_SRC is the voltage at the power supply, and 6353 * PWR_CORE_A_LOAD is the voltage at the chip, however, 6354 * PWR_CORE_A_LOAD is not available in all designs. 6355 * 6356 * For the most accurate measurement, PWR_CORE_A_LOAD 6357 * should be used if it is available. 6358 */ 6359 if (bb_vs_all[bx][i].flags & PWR_CORE_A_LOAD) { 6360 VcoreA = adc_data.val; 6361 } else if ((bb_vs_all[bx][i].flags & PWR_CORE_A_SRC) && 6362 VcoreA == VNULL) { 6363 VcoreA = adc_data.val; 6364 } 6365 if (bb_vs_all[bx][i].flags & PWR_CORE_A_DROP) { 6366 if (adc_data.val < 0) adc_data.val *= -1; 6367 if (adc_data.val > MIN_AMPLIFIED_VOLTAGE_DROP) 6368 Vdrop_coreA = GAIN(adc_data.val,RGp); 6369 else 6370 Vdrop_coreA = 0; 6371 } 6372 if (bb_vs_all[bx][i].flags & PWR_CORE_B_SRC) 6373 VcoreB = adc_data.val; 6374 if (bb_vs_all[bx][i].flags & PWR_CORE_B_DROP) { 6375 if (adc_data.val < 0) adc_data.val *= -1; 6376 if (adc_data.val > MIN_AMPLIFIED_VOLTAGE_DROP) 6377 Vdrop_coreB = GAIN(adc_data.val,RGp); 6378 else 6379 Vdrop_coreB = 0; 6380 } 6381 /* 6382 * PWR_PHY_SRC is the voltage at the power supply, and 6383 * PWR_PHY_LOAD is the voltage at the chip, however, 6384 * PWR_PHY_LOAD is not available in all designs. 6385 * 6386 * For the most accurate measurement, PWR_PHY_LOAD 6387 * should be used if it is available. 6388 */ 6389 if (bb_vs_all[bx][i].flags & PWR_PHY_LOAD) { 6390 Vphy = adc_data.val; 6391 } else if ((bb_vs_all[bx][i].flags & PWR_PHY_SRC) && 6392 Vphy == VNULL) { 6393 Vphy = adc_data.val; 6394 } 6395 if (bb_vs_all[bx][i].flags & PWR_PHY_DROP) { 6396 if (adc_data.val < 0) adc_data.val *= -1; 6397 if (adc_data.val > MIN_AMPLIFIED_VOLTAGE_DROP) 6398 Vdrop_phy = GAIN(adc_data.val,RGp); 6399 else 6400 Vdrop_phy = 0; 6401 } 6402 if (bb_vs_all[bx][i].flags & PWR_IO_SRC) 6403 Vio = adc_data.val; 6404 if (bb_vs_all[bx][i].flags & PWR_IO_DROP) { 6405 if (adc_data.val < 0) adc_data.val *= -1; 6406 if (adc_data.val > MIN_AMPLIFIED_VOLTAGE_DROP) 6407 Vdrop_io = GAIN(adc_data.val,RGp); 6408 else 6409 Vdrop_io = 0; 6410 } 6411 if (bb_vs_all[bx][i].flags & PWR_CORECAL_SRC) 6412 Vcal_core = adc_data.val; 6413 if (bb_vs_all[bx][i].flags & PWR_CORECAL_DROP) { 6414 if (adc_data.val < 0) adc_data.val *= -1; 6415 Vdrop_cal_core = GAIN(adc_data.val,RGc); 6416 } 6417 6418 if (bb_vs_all[bx][i].flags & PWR_PHYCAL_SRC) 6419 Vcal_phy = adc_data.val; 6420 if (bb_vs_all[bx][i].flags & PWR_PHYCAL_DROP) { 6421 if (adc_data.val < 0) adc_data.val *= -1; 6422 Vdrop_cal_phy = GAIN(adc_data.val,RGc); 6423 } 6424 6425 if (bb_vs_all[bx][i].flags & PWR_IOCAL_SRC) 6426 Vcal_io = adc_data.val; 6427 if (bb_vs_all[bx][i].flags & PWR_IOCAL_DROP) { 6428 if (adc_data.val < 0) adc_data.val *= -1; 6429 Vdrop_cal_io = GAIN(adc_data.val,RGc); 6430 } 6431 } 6432 6433 /* calculations */ 6434 6435 /* There is at least one calibration strip. If there are multiple */ 6436 /* strips, it is assumed that they have the same geometry. */ 6437 6438 if (Vdrop_cal_core != VNULL) { 6439 /* Current flowing through Rp and core cal strip to ground */ 6440 Ical_core = Vcal_core/Rp; 6441 /* Resistance of core calibration strip */ 6442 #ifdef COMPILER_HAS_DOUBLE 6443 Rcal_core = Vdrop_cal_core/Ical_core; 6444 #else 6445 Rcal_core = (RCAL_MUL * Vdrop_cal_core) / Ical_core; 6446 #endif 6447 } 6448 6449 if (Vdrop_cal_phy != VNULL) { 6450 /* Current flowing through Rp and phy cal strip to ground */ 6451 Ical_phy = Vcal_phy/Rp; 6452 /* Resistance of phy calibration strip */ 6453 #ifdef COMPILER_HAS_DOUBLE 6454 Rcal_phy = Vdrop_cal_phy/Ical_phy; 6455 #else 6456 Rcal_phy = (RCAL_MUL * Vdrop_cal_phy) / Ical_phy; 6457 #endif 6458 } 6459 6460 if (Vdrop_cal_io != VNULL) { 6461 /* Current flowing through Rp and IO cal strip to ground */ 6462 Ical_io = Vcal_io/Rp; 6463 /* Resistance of IO calibration strip */ 6464 #ifdef COMPILER_HAS_DOUBLE 6465 Rcal_io = Vdrop_cal_io/Ical_io; 6466 #else 6467 Rcal_io = (RCAL_MUL * Vdrop_cal_io) / Ical_io; 6468 #endif 6469 } 6470 6471 if (Vdrop_cal_core == VNULL) { 6472 /* No separate core calibration strip. */ 6473 /* Use PHY calibration strip. */ 6474 Ical_core = Ical_phy; 6475 Rcal_core = Rcal_phy; 6476 } 6477 6478 if (Vdrop_cal_phy == VNULL) { 6479 /* No separate PHY calibration strip. */ 6480 /* Use core calibration strip. */ 6481 Ical_phy = Ical_core; 6482 Rcal_phy = Rcal_core; 6483 } 6484 6485 if (Vdrop_cal_io == VNULL) { 6486 /* No separate IO calibration strip. */ 6487 /* Use phy calibration strip. */ 6488 Ical_io = Ical_phy; 6489 Rcal_io = Rcal_phy; 6490 } 6491 6492 6493 if (Vdrop_coreA != VNULL) { 6494 /* Power : Core A */ 6495 #ifdef COMPILER_HAS_DOUBLE 6496 Rseg_coreA = Rcal_core * (w_cal/w_pwr) * (l_pwr/l_cal); 6497 IcoreA = Vdrop_coreA/Rseg_coreA; 6498 PcoreA = IcoreA * VcoreA; 6499 #else 6500 Rseg_coreA = (((Rcal_core * w_cal) / w_pwr) * l_pwr) / l_cal; 6501 IcoreA = ((RCAL_MUL * Vdrop_coreA * w_pwr) / l_pwr) * l_cal; 6502 IcoreA /= (Rcal_core * w_cal); 6503 PcoreA = (IcoreA * (VcoreA / 1000)) / 1000; /* mW */ 6504 #endif 6505 } 6506 else { 6507 IcoreA = PcoreA = 0; 6508 Rseg_coreA = RNULL; 6509 } 6510 6511 if (Vdrop_coreB != VNULL) { 6512 /* Power: Core B */ 6513 #ifdef COMPILER_HAS_DOUBLE 6514 Rseg_coreB = Rcal_core * (w_cal/w_pwr) * (l_pwr/l_cal); 6515 IcoreB = Vdrop_coreB/Rseg_coreB; 6516 PcoreB = IcoreB * VcoreB; 6517 #else 6518 Rseg_coreB = (((Rcal_core * w_cal) / w_pwr) * l_pwr) / l_cal; 6519 IcoreB = ((RCAL_MUL * Vdrop_coreB * w_pwr) / l_pwr) * l_cal; 6520 IcoreB /= (Rcal_core * w_cal); 6521 PcoreB = (IcoreB * (VcoreB / 1000)) / 1000; /* mW */ 6522 #endif 6523 } 6524 else { 6525 IcoreB = PcoreB = 0; 6526 Rseg_coreB = RNULL; 6527 } 6528 6529 if (Vdrop_phy != VNULL) { 6530 /* Power: Phy */ 6531 #ifdef COMPILER_HAS_DOUBLE 6532 Rseg_phy = Rcal_phy * (w_cal / w_pwr) * (l_pwr / l_cal); 6533 Iphy = Vdrop_phy / Rseg_phy; 6534 Pphy = Iphy * Vphy; 6535 #else 6536 Rseg_phy = (((Rcal_phy * w_cal) / w_pwr) * l_pwr) / l_cal; 6537 Iphy = ((RCAL_MUL * Vdrop_phy * w_pwr) / l_pwr) * l_cal; 6538 Iphy /= (Rcal_phy * w_cal); 6539 Pphy = (Iphy * (Vphy / 1000)) / 1000; /* mW */ 6540 #endif 6541 } 6542 else { 6543 Iphy = Pphy = 0; 6544 Rseg_phy = RNULL; 6545 } 6546 6547 if (Vdrop_io != VNULL) { 6548 /* Power: IO */ 6549 #ifdef COMPILER_HAS_DOUBLE 6550 Rseg_io = Rcal_io * (w_cal / w_pwr) * (l_pwr / l_cal); 6551 Iio = Vdrop_io / Rseg_io; 6552 Pio = Iio * Vio; 6553 #else 6554 Rseg_io = (((Rcal_io * w_cal) / w_pwr) * l_pwr) / l_cal; 6555 Iio = ((RCAL_MUL * Vdrop_io * w_pwr) / l_pwr) * l_cal; 6556 Iio /= (Rcal_io * w_cal); 6557 Pio = (Iphy * (Vphy / 1000)) / 1000; /* mW */ 6558 #endif 6559 } 6560 else { 6561 Iio = Pio = 0; 6562 Rseg_io = RNULL; 6563 } 6564 6565 if (bx == G5) { 6566 /* For this board, the calibration strip was placed on 6567 * a different PCB plane than the measurement strips. 6568 * Adjust current and power values to compensate for 6569 * the difference in plane thicknesses. 6570 */ 6571 PcoreA = (PcoreA * 540) / 1000; /* PcoreA * 0.54 */ 6572 IcoreA = (IcoreA * 540) / 1000; /* IcoreA * 0.54 */ 6573 Pphy = (Pphy * 540) / 1000; /* Pphy * 0.54 */ 6574 Iphy = (Iphy * 540) / 1000; /* Iphy * 0.54 */ 6575 } 6576 6577 #define BB_DEBUG 6578 #ifdef BB_DEBUG 6579 /* Debugging */ 6580 #ifdef COMPILER_HAS_DOUBLE 6581 #define PFMT "%f" 6582 #else 6583 #define PFMT "%d" 6584 #endif 6585 /* Constants */ 6586 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6587 (BSL_META_U(unit, 6588 "\nConstants\n"))); 6589 #ifdef COMPILER_HAS_DOUBLE 6590 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6591 (BSL_META_U(unit, 6592 "Rcu=%1.10f\n"), RCu)); 6593 #else 6594 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6595 (BSL_META_U(unit, 6596 "Rcu=%d\n"), RCu)); 6597 #endif 6598 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6599 (BSL_META_U(unit, 6600 "Lcal=" PFMT "\n"), l_cal)); 6601 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6602 (BSL_META_U(unit, 6603 "Lpwr=" PFMT "\n"), l_pwr)); 6604 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6605 (BSL_META_U(unit, 6606 "Wcal=" PFMT "\n"), w_cal)); 6607 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6608 (BSL_META_U(unit, 6609 "Wpwr=" PFMT "\n"), w_pwr)); 6610 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6611 (BSL_META_U(unit, 6612 "Rp=" PFMT "\n"), Rp)); 6613 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6614 (BSL_META_U(unit, 6615 "\nMeasured Voltage Values\n"))); 6616 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6617 (BSL_META_U(unit, 6618 "Vdrop_cal_core=" PFMT "\n"), Vdrop_cal_core)); 6619 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6620 (BSL_META_U(unit, 6621 "Vdrop_cal_phy=" PFMT "\n"), Vdrop_cal_phy)); 6622 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6623 (BSL_META_U(unit, 6624 "Vdrop_cal_io=" PFMT "\n"), Vdrop_cal_io)); 6625 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6626 (BSL_META_U(unit, 6627 "Vcal_core=" PFMT "\n"), Vcal_core)); 6628 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6629 (BSL_META_U(unit, 6630 "Vcal_phy=" PFMT "\n"), Vcal_phy)); 6631 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6632 (BSL_META_U(unit, 6633 "Vcal_io=" PFMT "\n"), Vcal_io)); 6634 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6635 (BSL_META_U(unit, 6636 "Vdrop_coreA=" PFMT "\n"), Vdrop_coreA)); 6637 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6638 (BSL_META_U(unit, 6639 "\nCalculated Current Values\n"))); 6640 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6641 (BSL_META_U(unit, 6642 "Ical_core=" PFMT "\n"), Ical_core)); 6643 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6644 (BSL_META_U(unit, 6645 "Ical_phy=" PFMT "\n"), Ical_phy)); 6646 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6647 (BSL_META_U(unit, 6648 "Ical_io=" PFMT "\n"), Ical_io)); 6649 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6650 (BSL_META_U(unit, 6651 "\nCalculated Resistance Values\n"))); 6652 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6653 (BSL_META_U(unit, 6654 "Rcal_core=" PFMT "\n"), Rcal_core)); 6655 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6656 (BSL_META_U(unit, 6657 "Rcal_phy=" PFMT "\n"), Rcal_phy)); 6658 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6659 (BSL_META_U(unit, 6660 "Rcal_io=" PFMT "\n"), Rcal_io)); 6661 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6662 (BSL_META_U(unit, 6663 "Rseg_coreA=" PFMT "\n"), Rseg_coreA)); 6664 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6665 (BSL_META_U(unit, 6666 "Rseg_phy=" PFMT "\n"), Rseg_phy)); 6667 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6668 (BSL_META_U(unit, 6669 "Rseg_io=" PFMT "\n"), Rseg_io)); 6670 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6671 (BSL_META_U(unit, 6672 "Tc=" PFMT "\n"), Tc)); 6673 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6674 (BSL_META_U(unit, 6675 "Tp=" PFMT "\n"), Tp)); 6676 #endif 6677 #undef BB_DEBUG 6678 /* Show power */ 6679 if( op == BB_OP_POWER) { 6680 cli_out("Power Measurement\n"); 6681 if (Vdrop_coreA == VNULL) { 6682 /* 6683 * Only 1 core power measurement (Core B) 6684 */ 6685 #ifdef COMPILER_HAS_DOUBLE 6686 cli_out("PCore = %2.3fW ICore = %2.3fA VCore = %2.3fV\n", 6687 PcoreB, IcoreB, VcoreB); 6688 #else 6689 cli_out("PCore = %d.%03dW ICore = %d.%03dA VCore = %d.%03dV\n", 6690 INT_FRAC_3PT(PcoreB), INT_FRAC_3PT(IcoreB), 6691 INT_FRAC_3PT(VcoreB)); 6692 #endif 6693 } 6694 else if (Vdrop_coreB == VNULL) { 6695 /* 6696 * Only 1 core power measurement (Core A) 6697 */ 6698 #ifdef COMPILER_HAS_DOUBLE 6699 cli_out("PCore = %2.3fW ICore = %2.3fA VCore = %2.3fV\n", 6700 PcoreA, IcoreA, VcoreA); 6701 #else 6702 cli_out("PCore = %d.%03dW ICore = %d.%03dA VCore = %d.%03dV\n", 6703 INT_FRAC_3PT(PcoreA), INT_FRAC_3PT(IcoreA), 6704 INT_FRAC_3PT(VcoreA)); 6705 #endif 6706 } 6707 else { 6708 /* 6709 * Both core power measurements 6710 */ 6711 #ifdef COMPILER_HAS_DOUBLE 6712 cli_out("PCoreA = %2.3fW ICoreA = %2.3fA VCoreA = %2.3fV\n", 6713 PcoreA, IcoreA, VcoreA); 6714 cli_out("PCoreB = %2.3fW ICoreB = %2.3fA VCoreB = %2.3fV\n", 6715 PcoreB, IcoreB, VcoreB); 6716 #else 6717 cli_out("PCoreA = %d.%03dW ICoreA = %d.%03dA VCoreA = %d.%03dV\n", 6718 INT_FRAC_3PT(PcoreA), INT_FRAC_3PT(IcoreA), 6719 INT_FRAC_3PT(VcoreA)); 6720 cli_out("PCoreB = %d.%03dW ICoreB = %d.%03dA VCoreB = %d.%03dV\n", 6721 INT_FRAC_3PT(PcoreB), INT_FRAC_3PT(IcoreB), 6722 INT_FRAC_3PT(VcoreB)); 6723 #endif 6724 } 6725 6726 if (Vdrop_phy != VNULL) { 6727 /* 6728 * PHY (analog) power measurement 6729 */ 6730 #ifdef COMPILER_HAS_DOUBLE 6731 cli_out("PPhy = %2.3fW IPhy = %2.3fA VPhy = %2.3fV\n", 6732 Pphy, Iphy, Vphy); 6733 #else 6734 cli_out("PPhy = %d.%03dW IPhy = %d.%03dA VPhy = %d.%03dV\n", 6735 INT_FRAC_3PT(Pphy), INT_FRAC_3PT(Iphy), 6736 INT_FRAC_3PT(Vphy)); 6737 #endif 6738 } 6739 6740 if (Vdrop_io != VNULL) { 6741 /* 6742 * IO power measurement 6743 */ 6744 #ifdef COMPILER_HAS_DOUBLE 6745 cli_out("P_IO = %2.3fW I_IO = %2.3fA V_IO = %2.3fV\n", 6746 Pio, Iio, Vio); 6747 #else 6748 cli_out("P_IO = %d.%03dW I_IO = %d.%03dA V_IO = %d.%03dV\n", 6749 INT_FRAC_3PT(Pio), INT_FRAC_3PT(Iio), INT_FRAC_3PT(Vio)); 6750 #endif 6751 } 6752 6753 #ifdef COMPILER_HAS_DOUBLE 6754 cli_out("%2.3f Watts Total\n", 6755 (PcoreA + PcoreB + Pphy + Pio)); 6756 #else 6757 cli_out("%d.%03d Watts Total\n", 6758 INT_FRAC_3PT(PcoreA + PcoreB + Pphy + Pio)); 6759 #endif 6760 } else if (op == BB_OP_THICK) { 6761 /* Thickness : Tp/Tc are temperatures */ 6762 #ifdef COMPILER_HAS_DOUBLE 6763 tCore = tPhy = (l_cal * RCu); 6764 tCore /= (Rcal_core * w_cal)/ (1.0 + (Tc - 20.0) * TCoeff); 6765 tPhy /= (Rcal_phy * w_cal)/ (1.0 + (Tp - 20.0) * TCoeff); 6766 6767 if (SOC_IS_XGS(unit)){ 6768 cli_out("Thickness Core (mil) = %2.3f\n",1000*tCore); 6769 cli_out("Thickness Analog (mil) = %2.3f\n",1000*tPhy); 6770 } else { 6771 cli_out("Thickness Core (mil) = %2.3f\n",1000*tCore); 6772 cli_out("Thickness Phy (mil) = %2.3f\n",1000*tPhy); 6773 } 6774 #else 6775 t1 = l_cal * RCu * RCAL_MUL; 6776 tCore = t1 / (Rcal_core * w_cal); 6777 tCore *= 10000 + (((Tc - 200) * TCoeff) / 10); 6778 tCore /= 100000; 6779 tPhy = t1 / (Rcal_phy * w_cal); 6780 tPhy *= 10000 + (((Tp - 200) * TCoeff) / 10); 6781 tPhy /= 100000; 6782 6783 cli_out("Thickness Core (mil) = %d.%03d\n", INT_FRAC_3PT(tCore)); 6784 cli_out("Thickness %s (mil) = %d.%03d\n", s1, INT_FRAC_3PT(tPhy)); 6785 #endif 6786 } else { 6787 /* Temperature */ 6788 #ifdef COMPILER_HAS_DOUBLE 6789 tCore = (((Rcal_core * w_cal * Tc) / 6790 (l_cal * RCu) - 1.0) / TCoeff) + 20.0; 6791 tPhy = (((Rcal_phy * w_cal * Tp) / 6792 (l_cal * RCu) - 1.0) / TCoeff) + 20.0; 6793 6794 if (SOC_IS_HERCULES1(unit) || SOC_IS_DRACO(unit)){ 6795 cli_out("Temperature Core = %2.3fC/%2.3fF\n",tCore, 6796 (9.0/5.0) * tCore + 32); 6797 cli_out("Temperature Analog = %2.3fC/%2.3fF\n",tPhy, 6798 (9.0/5.0) * tPhy + 32); 6799 } else { 6800 cli_out("Temperature Core = %2.3fC/%2.3fF\n",tCore, 6801 (9.0/5.0) * tCore + 32); 6802 cli_out("Temperature Phy = %2.3fC/%2.3fF\n",tPhy, 6803 (9.0/5.0) * tPhy + 32); 6804 } 6805 #else 6806 t1 = (l_cal * RCu) / (100000 / RCAL_MUL); 6807 tCore = (Rcal_core * w_cal * Tc) / t1; 6808 tCore = ((10 * (tCore - 10000)) / TCoeff) + 200; 6809 tPhy = (Rcal_phy * w_cal * Tc) / t1; 6810 tPhy = ((10 * (tPhy - 10000)) / TCoeff) + 200; 6811 t1 = (tCore * 9) / 5 + 32; 6812 cli_out("Temperature Core = %d.%01dC/%d.%01dF\n", 6813 INT_FRAC_1PT(tCore), INT_FRAC_1PT(t1)); 6814 t1 = (tPhy * 9) / 5 + 32; 6815 cli_out("Temperature %s = %d.%01dC/%d.%01dF\n", s1, 6816 INT_FRAC_1PT(tPhy), INT_FRAC_1PT(t1)); 6817 #endif 6818 } 6819 } /* Power calculation functions supported */ 6820 else { 6821 cli_out("Platform[%s] does not support the power features.\n", 6822 BaseboardName); 6823 return CMD_FAIL; 6824 } 6825 return CMD_OK; 6826 } /* function is "power", "thickness" or "temperature" */ 6827 6828 if(!sal_strncasecmp(function,"pot",sal_strlen(function))){ 6829 int pot_num, val, pot; 6830 uint8 p8, v8; 6831 max5478_t cmd; 6832 6833 if (!source || !value) { 6834 return CMD_USAGE; 6835 } 6836 pot_num = sal_ctoi(source, 0); 6837 if ((pot_num < 0) || (pot_num > 7)) { 6838 return CMD_USAGE; 6839 } 6840 val = sal_ctoi(value, 0); 6841 if ((val < 0) || (val > 255)) { 6842 return CMD_USAGE; 6843 } 6844 /* Select device in mux */ 6845 if ( (mux = bcm_i2c_open(unit, I2C_LPT_0, flags, 0)) < 0) { 6846 cli_out("Could not open %s for mux selection:%s\n", 6847 I2C_LPT_0, bcm_errmsg(mux)); 6848 return CMD_FAIL; 6849 } 6850 /* 6851 * Set mux value so we can see the device when we try to open it 6852 * Device is specified pot_num / 2 6853 */ 6854 p8 = pot_num / 2; 6855 if( (rv = bcm_i2c_write(unit, mux, 0, &p8, 1)) < 0){ 6856 cli_out("Error: write of lpt byte failed:%s\n", 6857 bcm_errmsg(rv)); 6858 return CMD_FAIL; 6859 } 6860 if ( (pot = bcm_i2c_open(unit, I2C_POT_0, flags, 0)) < 0) { 6861 6862 cli_out("Could not open %s :%s\n", 6863 I2C_POT_0, bcm_errmsg(pot)); 6864 return CMD_FAIL; 6865 } 6866 v8 = (uint8) val; 6867 /* Now set potentiometer */ 6868 cmd.wiper = pot_num % 2; 6869 cmd.value = v8; 6870 rv = bcm_i2c_ioctl(unit, pot, I2C_POT_IOC_SET, (void *)&cmd, 0); 6871 if (rv < 0) { 6872 cli_out("Error: failed setting pot(%d, %d): %s\n", 6873 pot_num, val, bcm_errmsg(rv)); 6874 return CMD_FAIL; 6875 } 6876 return CMD_OK; 6877 } /* pot */ 6878 #ifdef SHADOW_SVK 6879 if(!sal_strncasecmp(function, "test", sal_strlen(function))){ 6880 return _bb_test(unit, baseboard); 6881 } 6882 #endif 6883 if(!sal_strncasecmp(function, "current", sal_strlen(function))){ 6884 if( !(baseboard->bbcmd_flags & BB_CURR) || bb_vs_config_len[bx] == 0) { 6885 cli_out("Error: %s does not support Current Measurement subsystem.\n", 6886 BaseboardName); 6887 return CMD_FAIL; 6888 } 6889 6890 /* Show all voltages, note that ADC's are always visible, 6891 * hence we do not need to set the BBMUX value 6892 */ 6893 for(i = 0; i < bb_current_len[bx]; i++){ 6894 if ( (adc = bcm_i2c_open(unit, 6895 bb_current[bx][i].adc, 6896 flags, 0)) < 0) { 6897 cli_out("Could not open %s:%s\n", 6898 bb_current[bx][i].adc, 6899 bcm_errmsg(adc)); 6900 return CMD_FAIL; 6901 } 6902 /* Display Current */ 6903 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 6904 &adc_data, bb_current[bx][i].chan) < 0)) { 6905 cli_out("Error: failed to perform A/D conversions.\n"); 6906 } 6907 if (i == 0) { /* This is Reference Voltage */ 6908 #ifdef COMPILER_HAS_DOUBLE 6909 curr_zero = adc_data.val * 0.5; 6910 #else 6911 curr_zero = adc_data.val / 2; 6912 #endif 6913 continue; 6914 } 6915 6916 #ifdef COMPILER_HAS_DOUBLE 6917 curr_sens = bb_current[bx][i].sens * 0.001; 6918 6919 cli_out("%s%s%2.3f Amps " 6920 "(Raw=%2.3f min=%2.3f max=%2.3f samples=%d)\n", 6921 bb_current[bx][i].function, 6922 adc_data.val >= 0 ? " " : " ", 6923 (adc_data.val - curr_zero) / curr_sens, 6924 adc_data.val, 6925 (adc_data.min - curr_zero) / curr_sens, 6926 (adc_data.max - curr_zero) / curr_sens, 6927 adc_data.nsamples); 6928 #else 6929 curr_sens = bb_current[bx][i].sens; 6930 6931 cli_out("%s%s%d.%03d Amps " 6932 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n", 6933 bb_current[bx][i].function, 6934 adc_data.val >= 0 ? " " : " ", 6935 INT_FRAC_3PT_3(adc_data.val), 6936 INT_FRAC_3PT_3(adc_data.min), 6937 INT_FRAC_3PT_3(adc_data.max), 6938 INT_FRAC_3PT_3(adc_data.delta), 6939 adc_data.nsamples); 6940 #endif 6941 } 6942 return CMD_OK; 6943 } 6944 6945 /* Configure or display voltage for any or all BB voltage 6946 * sources, abbreviate to "v" 6947 */ 6948 if(!sal_strncasecmp(function,"voltage",sal_strlen(function))) { 6949 /* Check Board Index, which should have voltage config 6950 * parameters. 6951 */ 6952 if( !(baseboard->bbcmd_flags & BB_VOLT) || bb_vs_config_len[bx] == 0) { 6953 cli_out("Error: %s does not support voltage control subsystem.\n", 6954 BaseboardName); 6955 return CMD_FAIL; 6956 6957 } 6958 6959 #if defined BCM_APACHE_SUPPORT || defined BCM_HELIX5_SUPPORT 6960 if ((soc_get_board_id() == G50) || (soc_get_board_id() == G51) || 6961 soc_get_board_id() == G61 || (soc_get_board_id() == G65)) { 6962 char *dev_name; 6963 /* Configure the mux */ 6964 for (i = 0; i < bb_vs_all_len[bx]; i++) { 6965 dev_name = _i2c_mux_default_dev_name_get(); 6966 if ((mux = bcm_i2c_open(unit, dev_name, flags, 0)) < 0) { 6967 cli_out("Could not open %s for mux selection:%s\n", 6968 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 6969 return CMD_FAIL; 6970 } 6971 if ((rv = bcm_i2c_write(unit, mux, 0, &bb_vs_config[bx][i].mux, 1)) < 0) { 6972 cli_out("Error: write of lpt byte failed:%s\n", 6973 bcm_errmsg(rv)); 6974 return CMD_FAIL; 6975 } 6976 } 6977 6978 if (!source) { 6979 for (i = 0; i < bb_vs_all_len[bx]; i++) { 6980 /* Open the ADC Device */ 6981 if ((adc = bcm_i2c_open(unit, bb_vs_all[bx][i].adc, flags, 0)) < 0) { 6982 cli_out("Could not open %s:%s\n", 6983 bb_vs_all[bx][i].adc, 6984 bcm_errmsg(adc)); 6985 return CMD_FAIL; 6986 } 6987 /* Display voltage */ 6988 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_VOUT, 6989 &adc_data, bb_vs_all[bx][i].chan) < 0)) { 6990 cli_out("Error: failed to perform A/D conversions.\n"); 6991 return CMD_FAIL; 6992 } 6993 #ifdef COMPILER_HAS_DOUBLE 6994 cli_out("VDD_%s = %2.3f Volts " 6995 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 6996 bb_vs_all[bx][i].function, 6997 adc_data.val, 6998 adc_data.min, adc_data.max, adc_data.delta, 6999 adc_data.nsamples); 7000 #else 7001 cli_out("VDD_%s = %d.%03d Volts " 7002 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d\n)", 7003 bb_vs_all[bx][i].function, 7004 INT_FRAC_3PT_3(adc_data.val), 7005 INT_FRAC_3PT_3(adc_data.min), 7006 INT_FRAC_3PT_3(adc_data.max), 7007 INT_FRAC_3PT_3(adc_data.delta), 7008 adc_data.nsamples); 7009 #endif 7010 7011 /* Invoke I2C_LTC_IOC_SET_RCONFIG for Helix5 to setup sense_resistor_data */ 7012 if (soc_get_board_id() == G65) { 7013 /* Setting offset: (bx-42) index from TH chip which supports RCONFIG */ 7014 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_SET_RCONFIG, 7015 &dac_op_data, ( bx - G42 ))) < 0) { 7016 cli_out("Failed to load resistor table of VDD_%s LTC device \n ", 7017 bb_vs_all[bx][i].function); 7018 return CMD_FAIL; 7019 7020 } 7021 } 7022 7023 /* Display Current */ 7024 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_IOUT, 7025 &adc_data, bb_vs_all[bx][i].chan) < 0)) { 7026 cli_out("Error: failed to perform A/D conversions.\n"); 7027 return CMD_FAIL; 7028 } 7029 #ifdef COMPILER_HAS_DOUBLE 7030 cli_out("Current = %2.3f mA " 7031 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 7032 adc_data.val, 7033 adc_data.min, adc_data.max, adc_data.delta, 7034 adc_data.nsamples); 7035 #else 7036 cli_out("Current = %d.%03d mA " 7037 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d\n)", 7038 INT_FRAC_3PT_3(adc_data.val), 7039 INT_FRAC_3PT_3(adc_data.min), 7040 INT_FRAC_3PT_3(adc_data.max), 7041 INT_FRAC_3PT_3(adc_data.delta), 7042 adc_data.nsamples); 7043 #endif 7044 /* Display Power */ 7045 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_POUT, 7046 &adc_data, bb_vs_all[bx][i].chan) < 0)) { 7047 cli_out("Error: failed to perform A/D conversions.\n"); 7048 return CMD_FAIL; 7049 } 7050 #ifdef COMPILER_HAS_DOUBLE 7051 cli_out("Power = %2.3f mW " 7052 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n\n", 7053 adc_data.val, 7054 adc_data.min, adc_data.max, adc_data.delta, 7055 adc_data.nsamples); 7056 #else 7057 cli_out("Power = %d.%03d mW " 7058 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d\n\n)", 7059 INT_FRAC_3PT_3(adc_data.val), 7060 INT_FRAC_3PT_3(adc_data.min), 7061 INT_FRAC_3PT_3(adc_data.max), 7062 INT_FRAC_3PT_3(adc_data.delta), 7063 adc_data.nsamples); 7064 #endif 7065 7066 } 7067 return CMD_OK; 7068 } 7069 7070 /* Here if a Voltage Source was specified. 7071 * Show or configure just that one voltage. 7072 */ 7073 /* First, find voltage table entry ... */ 7074 for (i = 0; i < bb_vs_config_len[bx]; i++) { 7075 if (!sal_strcasecmp(bb_vs_config[bx][i].function, source)) 7076 break; 7077 } 7078 /* Not found - ERROR! */ 7079 if(i == bb_vs_config_len[bx]) { 7080 cli_out("Unknown Voltage source: %s\n", source); 7081 return CMD_USAGE; 7082 } 7083 7084 /* Open the ADC Device*/ 7085 if ((adc = bcm_i2c_open(unit, bb_vs_config[bx][i].adc, flags, 0)) < 0) { 7086 cli_out("Could not open %s:%s\n", 7087 bb_vs_config[bx][i].adc, 7088 bcm_errmsg(adc)); 7089 return CMD_FAIL; 7090 } 7091 7092 if (value) { 7093 /* Going to calibrate and/or set a voltage; open the correct DAC */ 7094 if ((dac = bcm_i2c_open(unit, bb_vs_config[bx][i].dac, flags, 0)) < 0) { 7095 cli_out("Could not open %s:%s\n", 7096 bb_vs_config[bx][i].dac, 7097 bcm_errmsg(dac)); 7098 return CMD_FAIL; 7099 } 7100 7101 /* Always designate the DAC calibration table. This info 7102 * is needed for any voltage setting operations. If 7103 * a calibration is performed, the table is updated. 7104 */ 7105 if ((bcm_i2c_ioctl(unit, dac, 7106 I2C_DAC_IOC_SET_CALTAB, 7107 (void*)dac_params[bx], 7108 dac_param_len[bx]) < 0)) { 7109 cli_out("Error: failed to set DAC calibration table.\n"); 7110 return CMD_FAIL; 7111 } 7112 /* Set min-max voltage limits and set sense resistor data */ 7113 if ((bcm_i2c_ioctl(unit, dac, I2C_LTC_IOC_SET_CONFIG, &dac_op_data, 7114 bb_vs_config[bx][i].cal_idx) < 0)) { 7115 cli_out("Error: failed to configure max and min of device .\n"); 7116 return CMD_FAIL; 7117 } 7118 #ifdef COMPILER_HAS_DOUBLE 7119 volts = atof(value); 7120 #else 7121 volts = _shr_atof_exp10(value, 6); 7122 #endif 7123 if(volts > 0) { 7124 cli_out("Configuring voltage on [%s]\n", bb_vs_config[bx][i].function); 7125 /* Configuring Voltage Controllers for LTC 3880/3882/3884 device */ 7126 if ((bcm_i2c_ioctl(unit, dac, 7127 I2C_LTC_IOC_SET_VOUT, 7128 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7129 #ifdef COMPILER_HAS_DOUBLE 7130 cli_out("Error: failed to set VDD_%s to %2.3fV.\n", 7131 bb_vs_config[bx][i].function, volts); 7132 #else 7133 cli_out("Error: failed to set VDD_%s to %d.%03dV.\n", 7134 bb_vs_config[bx][i].function, INT_FRAC_3PT_3(volts)); 7135 #endif 7136 return CMD_FAIL; 7137 } 7138 } 7139 } 7140 7141 /* Display Single Voltage */ 7142 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_VOUT, 7143 &adc_data, bb_vs_config[bx][i].chan) < 0)) { 7144 cli_out("Error: failed to perform A/D conversions.\n"); 7145 return CMD_FAIL; 7146 } 7147 #ifdef COMPILER_HAS_DOUBLE 7148 cli_out("VDD_%s = %2.3f Volts " 7149 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 7150 bb_vs_config[bx][i].function, 7151 adc_data.val, 7152 adc_data.min, adc_data.max, adc_data.delta, 7153 adc_data.nsamples); 7154 #else 7155 cli_out("VDD_%s = %d.%03d Volts " 7156 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n", 7157 bb_vs_config[bx][i].function, 7158 INT_FRAC_3PT_3(adc_data.val), 7159 INT_FRAC_3PT_3(adc_data.min), 7160 INT_FRAC_3PT_3(adc_data.max), 7161 INT_FRAC_3PT_3(adc_data.delta), 7162 adc_data.nsamples); 7163 #endif 7164 /* Display Current */ 7165 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_IOUT, 7166 &adc_data, bb_vs_all[bx][i].chan) < 0)) { 7167 cli_out("Error: failed to perform A/D conversions.\n"); 7168 return CMD_FAIL; 7169 } 7170 #ifdef COMPILER_HAS_DOUBLE 7171 cli_out("Current = %2.3f mA " 7172 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 7173 adc_data.val, 7174 adc_data.min, adc_data.max, adc_data.delta, 7175 adc_data.nsamples); 7176 #else 7177 cli_out("Current = %d.%03d mA " 7178 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n", 7179 INT_FRAC_3PT_3(adc_data.val), 7180 INT_FRAC_3PT_3(adc_data.min), 7181 INT_FRAC_3PT_3(adc_data.max), 7182 INT_FRAC_3PT_3(adc_data.delta), 7183 adc_data.nsamples); 7184 #endif 7185 /* Display Power */ 7186 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_POUT, 7187 &adc_data, bb_vs_all[bx][i].chan) < 0)) { 7188 cli_out("Error: failed to perform A/D conversions.\n"); 7189 return CMD_FAIL; 7190 } 7191 #ifdef COMPILER_HAS_DOUBLE 7192 cli_out("Power = %2.3f mW " 7193 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n\n", 7194 adc_data.val, 7195 adc_data.min, adc_data.max, adc_data.delta, 7196 adc_data.nsamples); 7197 #else 7198 cli_out("Power = %d.%03d mW " 7199 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n\n", 7200 INT_FRAC_3PT_3(adc_data.val), 7201 INT_FRAC_3PT_3(adc_data.min), 7202 INT_FRAC_3PT_3(adc_data.max), 7203 INT_FRAC_3PT_3(adc_data.delta), 7204 adc_data.nsamples); 7205 #endif 7206 7207 return CMD_OK; 7208 } 7209 #endif/* BCM_APACHE_SUPPORT*/ 7210 7211 /* Show all voltages, note that ADC's are always visible, 7212 * hence we do not need to set the BBMUX value 7213 */ 7214 if( ! source){ 7215 for(i = 0; i < bb_vs_all_len[bx]; i++){ 7216 if ( (adc = bcm_i2c_open(unit, 7217 bb_vs_all[bx][i].adc, 7218 flags, 0)) < 0) { 7219 cli_out("Could not open %s:%s\n", 7220 bb_vs_all[bx][i].adc, 7221 bcm_errmsg(adc)); 7222 return CMD_FAIL; 7223 } 7224 /* Setting the Mux if needed */ 7225 if (bb_vs_all[bx][i].mux != 0) { 7226 char *dev_name; 7227 /* Open MUX (lpt0) device */ 7228 dev_name = _i2c_mux_default_dev_name_get(); 7229 if ( (mux = bcm_i2c_open(unit, dev_name, flags, 0)) < 0) { 7230 cli_out("Could not open %s for mux selection:%s\n", 7231 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 7232 return CMD_FAIL; 7233 } 7234 /* Set mux value so we can see the device when we try to open it*/ 7235 if( (rv = bcm_i2c_write(unit, mux, 0, 7236 &bb_vs_all[bx][i].mux, 1)) < 0){ 7237 cli_out("Error: write of lpt byte failed:%s\n", 7238 bcm_errmsg(rv)); 7239 return CMD_FAIL; 7240 } 7241 } 7242 /* Displaying voltge,current and power for LTC 3880/3882/2974 devices */ 7243 if (bb_vs_all[bx][i].flags == PWR_DAC_IO_SRC) { 7244 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_VOUT, 7245 &dac_op_data, bb_vs_all[bx][i].chan)) < 0) { 7246 cli_out("Failed to read Voltage of VDD_%s LTC device \n ", 7247 bb_vs_all[bx][i].function); 7248 return CMD_FAIL; 7249 } 7250 /* Setting offset: (bx-42) index from TH chip which supports RCONFIG */ 7251 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_SET_RCONFIG, 7252 &dac_op_data, ( bx - G42 ))) < 0) { 7253 cli_out("Failed to load resistor table of VDD_%s LTC device \n ", 7254 bb_vs_all[bx][i].function); 7255 return CMD_FAIL; 7256 7257 } 7258 7259 if (soc_get_board_id() == G48) { 7260 /* Refer Saber2 platform */ 7261 /* Calulating voltage based on feedback ratio. */ 7262 /* For 1V output, feedback voltage is 0.549 volts */ 7263 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 7264 dac_op_data = dac_op_data * 1000 / 549; 7265 } 7266 } 7267 if (soc_get_board_id() == G51) { 7268 /* Refer FireBolt5 platform */ 7269 /* Calulating voltage based on feedback ratio. */ 7270 /* For 1V output, feedback voltage is 0.549 volts */ 7271 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 7272 dac_op_data = dac_op_data * 1000 / 549; 7273 } 7274 } 7275 if ((soc_get_board_id() == G52) || (soc_get_board_id() == G53) || 7276 (soc_get_board_id() == G54)) { 7277 /* Refer HR3 SVK platform */ 7278 /* Calulating voltage based on feedback ratio. */ 7279 /* For 1V output, feedback voltage is 0.549 volts */ 7280 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 7281 dac_op_data = dac_op_data * 1000 / 549; 7282 } 7283 } 7284 7285 /* TO retrieve the current from ltc device. 7286 * Used in determining sense resistor value */ 7287 current = bx - G42; 7288 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_IOUT, 7289 ¤t, bb_vs_all[bx][i].chan)) < 0) { 7290 cli_out("Failed to read Current of VDD_%s LTC device \n ", 7291 bb_vs_all[bx][i].function); 7292 return CMD_FAIL; 7293 7294 } 7295 7296 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_POUT, 7297 &power, bb_vs_all[bx][i].chan)) < 0) { 7298 cli_out("Failed to read Power of VDD_%s LTC device \n ", 7299 bb_vs_all[bx][i].function); 7300 return CMD_FAIL; 7301 } 7302 #ifdef COMPILER_HAS_DOUBLE 7303 cli_out("VDD_%s = %2.3f Volts " 7304 " Current = %2.3f mA Power = %2.3f mW \n", 7305 bb_vs_all[bx][i].function, dac_op_data, 7306 current,power); 7307 #else 7308 cli_out("VDD_%s = %d.%03d Volts " 7309 " Current = %d.%03d mA Power = %d.%03d mW\n", 7310 bb_vs_all[bx][i].function, 7311 INT_FRAC_3PT_3(dac_op_data), 7312 INT_FRAC_3PT(current), 7313 INT_FRAC_3PT(power)); 7314 #endif 7315 total_power += power; 7316 } else if (bb_vs_all[bx][i].flags == PWR_DAC_IO_PMBUS) { 7317 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_VOUT, 7318 &dac_op_data, bb_vs_all[bx][i].chan)) < 0) { 7319 cli_out("Failed to read Voltage of VDD_%s NCP device \n ", 7320 bb_vs_all[bx][i].function); 7321 return CMD_FAIL; 7322 } 7323 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_IOUT, 7324 ¤t, bb_vs_all[bx][i].chan)) < 0) { 7325 cli_out("Failed to read Current of VDD_%s NCP device \n ", 7326 bb_vs_all[bx][i].function); 7327 return CMD_FAIL; 7328 } 7329 if ((soc_get_board_id() == G57) || (soc_get_board_id() == G60)) { 7330 /* NCP81233 does not support READ_POUT */ 7331 power = dac_op_data * current; 7332 } else if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_POUT, 7333 &power, bb_vs_all[bx][i].chan)) < 0) { 7334 cli_out("Failed to read Power of VDD_%s NCP device \n ", 7335 bb_vs_all[bx][i].function); 7336 return CMD_FAIL; 7337 } 7338 #ifdef COMPILER_HAS_DOUBLE 7339 cli_out("VDD_%s = %2.3f Volts " 7340 " Current = %2.3f mA Power = %2.3f mW \n", 7341 bb_vs_all[bx][i].function, dac_op_data, 7342 current, power); 7343 #else 7344 cli_out("VDD_%s = %d.%03d Volts " 7345 " Current = %d.%03d mA Power = %d.%03d mW\n", 7346 bb_vs_all[bx][i].function, 7347 INT_FRAC_3PT_3(dac_op_data), 7348 INT_FRAC_3PT(current), 7349 INT_FRAC_3PT(power)); 7350 #endif 7351 total_power += power; 7352 } else { 7353 /* Display voltage */ 7354 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 7355 &adc_data, bb_vs_all[bx][i].chan) < 0)) { 7356 cli_out("Error: failed to perform A/D conversions.\n"); 7357 } 7358 #ifdef COMPILER_HAS_DOUBLE 7359 cli_out("%s%s%2.3f Volts " 7360 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 7361 bb_vs_all[bx][i].function, 7362 adc_data.val >= 0 ? " " : " ", 7363 adc_data.val, 7364 adc_data.min,adc_data.max, adc_data.delta, 7365 adc_data.nsamples); 7366 #else 7367 cli_out("%s%s%d.%03d Volts " 7368 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n", 7369 bb_vs_all[bx][i].function, 7370 adc_data.val >= 0 ? " " : " ", 7371 INT_FRAC_3PT_3(adc_data.val), 7372 INT_FRAC_3PT_3(adc_data.min), 7373 INT_FRAC_3PT_3(adc_data.max), 7374 INT_FRAC_3PT_3(adc_data.delta), 7375 adc_data.nsamples); 7376 #endif 7377 } 7378 7379 } 7380 7381 #ifdef COMPILER_HAS_DOUBLE 7382 cli_out("Total Device Power = %2.3f W \n", (total_power / 1000)); 7383 #else 7384 cli_out("Total Device Power = %d.%03d W \n", 7385 INT_FRAC_3PT(total_power)); 7386 #endif 7387 return CMD_OK; 7388 } /* Show all voltages */ 7389 7390 /* Here if a Voltage Source was specified. 7391 * Show or configure just that one voltage. 7392 * This currently works only for configurable voltages. 7393 */ 7394 /* First, find voltage table entry ... */ 7395 for( i = 0; i < bb_vs_config_len[bx]; i++) { 7396 if ( !sal_strcasecmp(bb_vs_config[bx][i].function, source)) 7397 break; 7398 } 7399 /* Not found - ERROR! */ 7400 if(i == bb_vs_config_len[bx]){ 7401 cli_out("Unknown Voltage source: %s\n", source); 7402 return CMD_USAGE; 7403 } 7404 7405 if (SOC_IS_TOMAHAWK(unit)) { 7406 int j; 7407 char *bbv_str; 7408 uint32 bbv_min; 7409 uint32 bbv_max; 7410 uint32 bbv_mid; 7411 bbv_str = soc_property_get_str(unit, "bb_voltage_source"); 7412 7413 if (bbv_str != NULL) { 7414 for (j = 0; j < bb_vs_config_len[bx]; j++) { 7415 if (!sal_strcasecmp(bb_vs_config[bx][j].function, 7416 bbv_str)) { 7417 break; 7418 } 7419 } 7420 if (j != bb_vs_config_len[bx]) { 7421 bbv_min = soc_property_get(unit, "bb_voltage_min", 7422 ADP4000_MIN_DACVAL); 7423 bbv_max = soc_property_get(unit, "bb_voltage_max", 7424 ADP4000_MAX_DACVAL); 7425 bbv_mid = soc_property_get(unit, "bb_voltage_mid", 7426 ADP4000_MID_DACVAL); 7427 dac_params[bx][j].dac_min_hwval = (short)bbv_min; 7428 dac_params[bx][j].dac_max_hwval = (short)bbv_max; 7429 dac_params[bx][j].dac_mid_hwval = (short)bbv_mid; 7430 } 7431 } 7432 } 7433 7434 if (value && (bb_vs_config[bx][i].mux != 0xFF)) { 7435 char *dev_name; 7436 #ifdef SHADOW_SVK 7437 uint8 channel; 7438 /* Going to set a voltage (need DAC), and the DAC is MUXed */ 7439 /* Open MUX (lpt0) device */ 7440 dev_name = _i2c_mux_default_dev_name_get(); 7441 if ( (mux = _i2c_mux_open(unit, flags, 0, dev_name)) < 0) { 7442 cli_out("Could not open %s for mux selection:%s\n", 7443 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 7444 return CMD_FAIL; 7445 } 7446 channel = _i2c_mux_channel_get(unit, bb_vs_config[bx][i].mux); 7447 if( (rv = bcm_i2c_write(unit, mux, 0, &channel, 1)) < 0){ 7448 cli_out("Error: write of lpt byte failed:%s\n", 7449 bcm_errmsg(rv)); 7450 return CMD_FAIL; 7451 } 7452 #else 7453 /* Going to set a voltage (need DAC), and the DAC is MUXed */ 7454 /* Open MUX (lpt0) device */ 7455 dev_name = _i2c_mux_default_dev_name_get(); 7456 if ( (mux = bcm_i2c_open(unit, dev_name, flags, 0)) < 0) { 7457 cli_out("Could not open %s for mux selection:%s\n", 7458 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 7459 return CMD_FAIL; 7460 } 7461 /* Set mux value so we can see the device when we try to open it*/ 7462 if( (rv = bcm_i2c_write(unit, mux, 0, &bb_vs_config[bx][i].mux, 1)) < 0){ 7463 cli_out("Error: write of lpt byte failed:%s\n", 7464 bcm_errmsg(rv)); 7465 return CMD_FAIL; 7466 } 7467 #endif /* SHADOW_SVK */ 7468 } /* Setting a voltage, needed to manipulate MUX for the DACs */ 7469 7470 if (value) { 7471 /* Going to calibrate and/or set a voltage; open the correct DAC */ 7472 if ( (dac = bcm_i2c_open(unit, bb_vs_config[bx][i].dac, 7473 flags, 0)) < 0) { 7474 7475 cli_out("Could not open %s:%s\n", 7476 bb_vs_config[bx][i].dac, 7477 bcm_errmsg(dac)); 7478 return CMD_FAIL; 7479 } 7480 } 7481 7482 /* Open the ADC Device (either adc0 or adc1) */ 7483 if ( (adc = bcm_i2c_open(unit, bb_vs_config[bx][i].adc, 7484 flags, 0)) < 0) { 7485 cli_out("Could not open %s:%s\n", 7486 bb_vs_config[bx][i].adc, 7487 bcm_errmsg(adc)); 7488 return CMD_FAIL; 7489 } 7490 7491 /* From this point on, we have an ADC (and possibly its 7492 * associated DAC) open and ready for commands. 7493 */ 7494 7495 if (value) { 7496 /* Going to calibrate and/or set a voltage; open the correct DAC */ 7497 if ( (dac = bcm_i2c_open(unit, bb_vs_config[bx][i].dac, 7498 flags, 0)) < 0) { 7499 7500 cli_out("Could not open %s:%s\n", 7501 bb_vs_config[bx][i].dac, 7502 bcm_errmsg(dac)); 7503 return CMD_FAIL; 7504 } 7505 } 7506 7507 /* Open the ADC Device (either adc0 or adc1) */ 7508 if ( (adc = bcm_i2c_open(unit, bb_vs_config[bx][i].adc, 7509 flags, 0)) < 0) { 7510 cli_out("Could not open %s:%s\n", 7511 bb_vs_config[bx][i].adc, 7512 bcm_errmsg(adc)); 7513 return CMD_FAIL; 7514 } 7515 7516 /* From this point on, we have an ADC (and possibly its 7517 * associated DAC) open and ready for commands. 7518 */ 7519 7520 /* Set and/or possibly calibrate voltage, we need to do this 7521 * at least once (the first time), and possibly later if the 7522 * user requests a calibration of a source ... 7523 */ 7524 if( value ) { 7525 /* cli_out("calibration: board %d: subsys%d\n",bx, i); */ 7526 7527 /* Always designate the DAC calibration table. This info 7528 * is needed for any voltage setting operations. If 7529 * a calibration is performed, the table is updated. 7530 */ 7531 if (bb_vs_config[bx][i].flags != PWR_DAC_IO_PMBUS) { 7532 if ( (bcm_i2c_ioctl(unit, dac, 7533 I2C_DAC_IOC_SET_CALTAB, 7534 (void*)dac_params[bx], 7535 dac_param_len[bx]) < 0)) { 7536 cli_out("Error: failed to set DAC calibration table.\n"); 7537 } 7538 } 7539 7540 /* Configuration for LTC 3880/3882 device */ 7541 if (bb_vs_config[bx][i].flags == PWR_DAC_IO_SRC) { 7542 /* Setting offset: (bx-42) index from TH chip 7543 * which supports RCONFIG */ 7544 dac_op_data= bx - G42; 7545 if ((bcm_i2c_ioctl(unit, dac, I2C_LTC_IOC_SET_CONFIG, &dac_op_data, 7546 bb_vs_config[bx][i].cal_idx) < 0)) { 7547 cli_out("Error: failed to configure max and min of device .\n"); 7548 return CMD_FAIL; 7549 } 7550 } 7551 /* Calibrate the DAC->ADC loop 7552 * (if not yet done, or explicitly requested). */ 7553 if ( (show_cal = !sal_strcasecmp(value,"calibrate")) || 7554 (show_cal = !sal_strcasecmp(value,"cal")) || 7555 !(show_cal = bb_vs_config[bx][i].flags & DAC_CALIBRATED) ) { 7556 if (show_cal) 7557 cli_out("calibration: board %d: subsys%d\n",bx, i); 7558 /* Reading the Voltages in calibrate command for LTC 3880/3882 devices */ 7559 if( bb_vs_config[bx][i].flags == PWR_DAC_IO_SRC ) { 7560 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_VOUT, 7561 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 7562 cli_out("Failed to read Voltage of VDD_%s's LTC device \n ", 7563 bb_vs_config[bx][i].function); 7564 return CMD_FAIL; 7565 } 7566 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_IOUT, 7567 ¤t, bb_vs_config[bx][i].chan)) < 0) { 7568 cli_out("Failed to read Current of VDD_%s's LTC device \n ", 7569 bb_vs_config[bx][i].function); 7570 return CMD_FAIL; 7571 } 7572 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_POUT, 7573 &power, bb_vs_config[bx][i].chan)) < 0) { 7574 cli_out("Failed to read Power of VDD_%s's ADC device \n ", 7575 bb_vs_config[bx][i].function); 7576 return CMD_FAIL; 7577 } 7578 #ifdef COMPILER_HAS_DOUBLE 7579 cli_out("VDD_%s = %2.3f Volts " 7580 " Current = %2.3f mA Power = %2.3f mW \n", 7581 bb_vs_config[bx][i].function, dac_op_data, 7582 current,power); 7583 #else 7584 cli_out("VDD_%s = %d.%03d Volts " 7585 " Current = %d.%03d mA Power = %d.%03d mW \n", 7586 bb_vs_config[bx][i].function, 7587 INT_FRAC_3PT_3(dac_op_data), 7588 INT_FRAC_3PT(current), 7589 INT_FRAC_3PT(power)); 7590 #endif 7591 return CMD_OK ; 7592 7593 } else if (bb_vs_config[bx][i].flags == PWR_DAC_IO_PMBUS) { 7594 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_VOUT, 7595 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 7596 cli_out("Failed to read Voltage of VDD_%s NCP device \n ", 7597 bb_vs_config[bx][i].function); 7598 return CMD_FAIL; 7599 } 7600 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_IOUT, 7601 ¤t, bb_vs_config[bx][i].chan)) < 0) { 7602 cli_out("Failed to read Current of VDD_%s NCP device \n ", 7603 bb_vs_config[bx][i].function); 7604 return CMD_FAIL; 7605 } 7606 if ((soc_get_board_id() == G57) || (soc_get_board_id() == G60) || (soc_get_board_id() == G64)) { 7607 /* NCP81233 does not support READ_POUT */ 7608 power = dac_op_data * current; 7609 } 7610 #ifdef COMPILER_HAS_DOUBLE 7611 cli_out("VDD_%s = %2.3f Volts " 7612 " Current = %2.3f mA Power = %2.3f mW \n", 7613 bb_vs_config[bx][i].function, dac_op_data, 7614 current, power); 7615 #else 7616 cli_out("VDD_%s = %d.%03d Volts " 7617 " Current = %d.%03d mA Power = %d.%03d mW\n", 7618 bb_vs_config[bx][i].function, 7619 INT_FRAC_3PT_3(dac_op_data), 7620 INT_FRAC_3PT(current), 7621 INT_FRAC_3PT(power)); 7622 #endif 7623 return CMD_OK ; 7624 } else { 7625 /* We need to calibrate the DAC to compute the min, 7626 * max, and the Volts/step values that result at the 7627 * associated ADC. */ 7628 /* Set the DAC to the (digital) value which */ 7629 /* generates the minimum analog voltage at the ADC. */ 7630 if ( (bcm_i2c_ioctl(unit, dac, 7631 I2C_DAC_IOC_SETDAC_MIN, 7632 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7633 cli_out("Error: failed to set min DAC Vout.\n"); 7634 } 7635 7636 /* Read the resultant (minimum) voltage at the ADC. */ 7637 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 7638 &adc_data, bb_vs_config[bx][i].chan) < 0)) { 7639 cli_out("Error: failed to read A/D min voltage:VDD_%s.\n", 7640 bb_vs_config[bx][i].function); 7641 } 7642 volts = adc_data.val; 7643 #ifdef SHADOW_SVK 7644 if (SOC_IS_SHADOW(unit)) { 7645 /* Hard code the min and Max as the voltage rails are 7646 * clamped */ 7647 volts = dac_params[bx][i].min; 7648 } 7649 #endif 7650 if (show_cal) 7651 #ifdef COMPILER_HAS_DOUBLE 7652 cli_out("Min=%2.3fV, ", volts); 7653 #else 7654 cli_out("Min=%d.%03dV, ", INT_FRAC_3PT_3(volts)); 7655 #endif 7656 7657 /* Update DAC calibration table with this minimum voltage. */ 7658 if ( (bcm_i2c_ioctl(unit, dac, 7659 I2C_DAC_IOC_CALIBRATE_MIN, 7660 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7661 cli_out("Error: failed to update min DAC Vout.\n"); 7662 } 7663 7664 /* Set the DAC to the (digital) value which */ 7665 /* generates the maximum analog voltage at the ADC. */ 7666 if ( (bcm_i2c_ioctl(unit, dac, 7667 I2C_DAC_IOC_SETDAC_MAX, 7668 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7669 cli_out("Error: failed to set max DAC Vout.\n"); 7670 } 7671 7672 /* Read the resultant (maximum) voltage at the ADC. */ 7673 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 7674 &adc_data, bb_vs_config[bx][i].chan) < 0)) { 7675 cli_out("Error: failed to read A/D max voltage:VDD_%s.\n", 7676 bb_vs_config[bx][i].function); 7677 } 7678 volts = adc_data.val; 7679 #ifdef SHADOW_SVK 7680 if (SOC_IS_SHADOW(unit)) { 7681 /* Hard code the min and Max as the voltage rails are 7682 * clamped */ 7683 volts = dac_params[bx][i].min; 7684 } 7685 #endif 7686 if (show_cal) 7687 #ifdef COMPILER_HAS_DOUBLE 7688 cli_out("Max=%2.3fV\n", volts); 7689 #else 7690 cli_out("Max=%d.%03dV\n", INT_FRAC_3PT_3(volts)); 7691 #endif 7692 /* Update DAC calibration table with this maximum voltage. */ 7693 if ( (bcm_i2c_ioctl(unit, dac, 7694 I2C_DAC_IOC_CALIBRATE_MAX, 7695 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7696 cli_out("Error: failed to update max DAC Vout.\n"); 7697 } 7698 7699 /* Very important, set the DAC back to nominal 7700 * (bootup midscale). 7701 */ 7702 if( (rv = bcm_i2c_ioctl(unit, dac, 7703 I2C_DAC_IOC_SETDAC_MID, 7704 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7705 cli_out("Error: resetting of DAC to nominal value failed:%s\n", 7706 bcm_errmsg(rv)); 7707 return CMD_FAIL; 7708 } 7709 7710 /* Now, update the calibration table with the 7711 * analog voltage step per DAC digital step. 7712 * (also displays all of the calibration table info) 7713 */ 7714 if ( (bcm_i2c_ioctl(unit, dac, 7715 I2C_DAC_IOC_CALIBRATE_STEP, 7716 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7717 cli_out("Error: failed to calibrate DAC VDD_%s.\n", 7718 bb_vs_config[bx][i].function); 7719 } 7720 /* Indicate that this DAC-ADC pair is calibrated */ 7721 bb_vs_config[bx][i].flags = DAC_CALIBRATED; 7722 } 7723 } /* DAC->ADC not yet calibrated or calibration was requested */ 7724 7725 /* Get the user's desired analog voltage value to set. */ 7726 7727 if (!sal_strncasecmp(value,"nominal",sal_strlen(value))) { 7728 cli_out("Resetting %s voltage to nominal\n", source); 7729 /* setting and Reading nominal voltage for LTC 3880/3882 Devices */ 7730 if( bb_vs_config[bx][i].flags == PWR_DAC_IO_SRC ) { 7731 if ( (bcm_i2c_ioctl(unit, dac, I2C_LTC_IOC_NOMINAL, 7732 &bb_vs_config[bx][i].chan, bb_vs_config[bx][i].cal_idx)) < 0) { 7733 cli_out("Failed to set nominal Voltage of VDD_%s's LTC device \n ", 7734 bb_vs_config[bx][i].function); 7735 return CMD_FAIL; 7736 } 7737 7738 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_VOUT, 7739 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 7740 cli_out("Failed to read Voltage of VDD_%s's LTC device \n ", 7741 bb_vs_config[bx][i].function); 7742 return CMD_FAIL; 7743 } 7744 7745 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_IOUT, 7746 ¤t, bb_vs_config[bx][i].chan)) < 0) { 7747 cli_out("Failed to read Current of VDD_%s's LTC device \n ", 7748 bb_vs_config[bx][i].function); 7749 return CMD_FAIL; 7750 } 7751 7752 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_POUT, 7753 &power, bb_vs_config[bx][i].chan)) < 0) { 7754 cli_out("Failed to read Power of VDD_%s's ADC device \n ", 7755 bb_vs_config[bx][i].function); 7756 return CMD_FAIL; 7757 } 7758 #ifdef COMPILER_HAS_DOUBLE 7759 cli_out("VDD_%s = %2.3f Volts " 7760 " Current = %2.3f mA Power = %2.3f mW \n", 7761 bb_vs_config[bx][i].function, dac_op_data, 7762 current,power); 7763 #else 7764 cli_out("VDD_%s = %d.%03d Volts " 7765 " Current = %d.%03d mA Power = %d.%03d mW \n", 7766 bb_vs_config[bx][i].function, 7767 INT_FRAC_3PT_3(dac_op_data), 7768 INT_FRAC_3PT(current), 7769 INT_FRAC_3PT(power)); 7770 #endif 7771 return CMD_OK ; 7772 } else if (bb_vs_config[bx][i].flags == PWR_DAC_IO_PMBUS) { 7773 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_VOUT, 7774 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 7775 cli_out("Failed to read Voltage of VDD_%s NCP device \n ", 7776 bb_vs_config[bx][i].function); 7777 return CMD_FAIL; 7778 } 7779 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_IOUT, 7780 ¤t, bb_vs_config[bx][i].chan)) < 0) { 7781 cli_out("Failed to read Current of VDD_%s NCP device \n ", 7782 bb_vs_config[bx][i].function); 7783 return CMD_FAIL; 7784 } 7785 if ((soc_get_board_id() == G57) || (soc_get_board_id() == G60) || (soc_get_board_id() == G64)) { 7786 /* NCP81233 does not support READ_POUT */ 7787 power = dac_op_data * current; 7788 } 7789 #ifdef COMPILER_HAS_DOUBLE 7790 cli_out("VDD_%s = %2.3f Volts " 7791 " Current = %2.3f mA Power = %2.3f mW \n", 7792 bb_vs_config[bx][i].function, dac_op_data, 7793 current, power); 7794 #else 7795 cli_out("VDD_%s = %d.%03d Volts " 7796 " Current = %d.%03d mA Power = %d.%03d mW\n", 7797 bb_vs_config[bx][i].function, 7798 INT_FRAC_3PT_3(dac_op_data), 7799 INT_FRAC_3PT(current), 7800 INT_FRAC_3PT(power)); 7801 #endif 7802 return CMD_OK ; 7803 } else { 7804 if ( (bcm_i2c_ioctl(unit, dac, 7805 I2C_DAC_IOC_SETDAC_MID, 7806 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7807 cli_out("Error: failed to reset VDD_%s DAC to mid-range value.\n", 7808 bb_vs_config[bx][i].function); 7809 return CMD_FAIL; 7810 } 7811 7812 /* Read the ADC to get the actual resultant voltage value. */ 7813 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 7814 &adc_data, bb_vs_config[bx][i].chan) < 0)) { 7815 cli_out("Error: failed to perform A/D conversions.\n"); 7816 } 7817 /* Display the recently configured voltage */ 7818 #ifdef COMPILER_HAS_DOUBLE 7819 cli_out("VDD_%s = %2.3f Volts " 7820 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 7821 bb_vs_config[bx][i].function, adc_data.val, 7822 adc_data.min,adc_data.max, adc_data.delta, 7823 adc_data.nsamples); 7824 #else 7825 cli_out("VDD_%s = %d.%03d Volts " 7826 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n", 7827 bb_vs_config[bx][i].function, 7828 INT_FRAC_3PT_3(adc_data.val), 7829 INT_FRAC_3PT_3(adc_data.min), 7830 INT_FRAC_3PT_3(adc_data.max), 7831 INT_FRAC_3PT_3(adc_data.delta), 7832 adc_data.nsamples); 7833 #endif 7834 return CMD_OK ; 7835 } 7836 7837 } 7838 7839 /* Here if a voltage level was specified */ 7840 7841 #ifdef COMPILER_HAS_DOUBLE 7842 volts = atof(value); 7843 #else 7844 /* Parse input in V and convert to uV */ 7845 volts = _shr_atof_exp10(value, 6); 7846 #endif 7847 7848 if (soc_get_board_id() == G48) { 7849 /* Refer Saber2 platform */ 7850 /* Calulating voltage based on feedback ratio. */ 7851 /* For 1V output, feedback voltage is 0.549 volts */ 7852 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 7853 volts = volts * 549 / 1000; 7854 } 7855 } 7856 if ((soc_get_board_id() == G52) || (soc_get_board_id() == G53) || 7857 (soc_get_board_id() == G54)) { 7858 /* Refer HR3 SVK platform */ 7859 /* Calulating voltage based on feedback ratio. */ 7860 /* For 1V output, feedback voltage is 0.549 volts */ 7861 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 7862 volts = volts * 549 / 1000; 7863 } 7864 } 7865 7866 if(volts > 0) { 7867 cli_out("Configuring voltage on [%s]\n", source); 7868 /* Configuring Voltage Controllers for LTC 3880/3882 device */ 7869 if( bb_vs_config[bx][i].flags == PWR_DAC_IO_SRC ) { 7870 if ( (bcm_i2c_ioctl(unit, dac,I2C_LTC_IOC_SET_VOUT, 7871 &volts, bb_vs_config[bx][i].cal_idx)) < 0) { 7872 cli_out("Failed to set Voltage of VDD_%s's LTC device \n ", 7873 bb_vs_config[bx][i].function); 7874 return CMD_FAIL; 7875 } 7876 /* Duration required for LTC deviec to set output voltage */ 7877 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_VOUT, 7878 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 7879 cli_out("Failed to read Voltage of VDD_%s's LTC device \n ", 7880 bb_vs_config[bx][i].function); 7881 return CMD_FAIL; 7882 } 7883 7884 if (soc_get_board_id() == G48) { 7885 /* Refer Saber2 platform */ 7886 /* Calulating voltage based on feedback ratio. */ 7887 /* For 1V output, feedback voltage is 0.549 volts */ 7888 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 7889 dac_op_data = dac_op_data * 1000 / 549; 7890 } 7891 } 7892 if ((soc_get_board_id() == G52) || (soc_get_board_id() == G53) || 7893 (soc_get_board_id() == G54)) { 7894 /* Refer HR3 SVK platform */ 7895 /* Calulating voltage based on feedback ratio. */ 7896 /* For 1V output, feedback voltage is 0.549 volts */ 7897 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 7898 dac_op_data = dac_op_data * 1000 / 549; 7899 } 7900 } 7901 7902 current = bx - G42; 7903 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_IOUT, 7904 ¤t, bb_vs_config[bx][i].chan)) < 0) { 7905 cli_out("Failed to read Current of VDD_%s's LTC device \n ", 7906 bb_vs_config[bx][i].function); 7907 return CMD_FAIL; 7908 } 7909 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_POUT, 7910 &power, bb_vs_config[bx][i].chan)) < 0) { 7911 cli_out("Failed to read Power of VDD_%s's ADC device \n ", 7912 bb_vs_config[bx][i].function); 7913 return CMD_FAIL; 7914 } 7915 #ifdef COMPILER_HAS_DOUBLE 7916 cli_out("VDD_%s = %2.3f Volts " 7917 " Current = %2.3f mA Power = %2.3f mW \n", 7918 bb_vs_config[bx][i].function, dac_op_data, 7919 current,power); 7920 #else 7921 cli_out("VDD_%s = %d.%03d Volts " 7922 "Current = %d.%03d mA Power = %d.%03d mW \n", 7923 bb_vs_config[bx][i].function, 7924 INT_FRAC_3PT_3(dac_op_data), 7925 INT_FRAC_3PT(current), 7926 INT_FRAC_3PT(power)); 7927 #endif 7928 return CMD_OK ; 7929 7930 } else if (bb_vs_config[bx][i].flags == PWR_DAC_IO_PMBUS) { 7931 /* Finally, set the actual voltage ... */ 7932 if ( (bcm_i2c_ioctl(unit, dac, PMBUS_IOC_SET_VOUT, 7933 &volts, bb_vs_config[bx][i].chan) < 0)) { 7934 #ifdef COMPILER_HAS_DOUBLE 7935 cli_out("Error: failed to set VDD_%s to %2.3fV.\n", 7936 bb_vs_config[bx][i].function, volts); 7937 #else 7938 cli_out("Error: failed to set VDD_%s to %d.%03dV.\n", 7939 bb_vs_config[bx][i].function, INT_FRAC_3PT_3(volts)); 7940 #endif 7941 cli_out("Run \"bb voltage %s calibrate\" to view allowable range.\n", 7942 bb_vs_config[bx][i].function); 7943 7944 return CMD_FAIL; 7945 } 7946 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_VOUT, 7947 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 7948 cli_out("Failed to read Voltage of VDD_%s NCP device \n ", 7949 bb_vs_config[bx][i].function); 7950 return CMD_FAIL; 7951 } 7952 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_IOUT, 7953 ¤t, bb_vs_config[bx][i].chan)) < 0) { 7954 cli_out("Failed to read Current of VDD_%s NCP device \n ", 7955 bb_vs_config[bx][i].function); 7956 return CMD_FAIL; 7957 7958 } 7959 if ((soc_get_board_id() == G57) || (soc_get_board_id() == G60) || (soc_get_board_id() == G64)) { 7960 /* NCP81233 does not support READ_POUT */ 7961 power = dac_op_data * current; 7962 } 7963 #ifdef COMPILER_HAS_DOUBLE 7964 cli_out("VDD_%s = %2.3f Volts " 7965 " Current = %2.3f mA Power = %2.3f mW \n", 7966 bb_vs_config[bx][i].function, dac_op_data, 7967 current, power); 7968 #else 7969 cli_out("VDD_%s = %d.%03d Volts " 7970 " Current = %d.%03d mA Power = %d.%03d mW\n", 7971 bb_vs_config[bx][i].function, 7972 INT_FRAC_3PT_3(dac_op_data), 7973 INT_FRAC_3PT(current), 7974 INT_FRAC_3PT(power)); 7975 #endif 7976 return CMD_OK ; 7977 } else { 7978 /* Finally, set the actual voltage ... */ 7979 if ( (bcm_i2c_ioctl(unit, dac, 7980 I2C_DAC_IOC_SET_VOUT, 7981 &volts, bb_vs_config[bx][i].cal_idx) < 0)) { 7982 #ifdef COMPILER_HAS_DOUBLE 7983 cli_out("Error: failed to set VDD_%s to %2.3fV.\n", 7984 bb_vs_config[bx][i].function, volts); 7985 #else 7986 cli_out("Error: failed to set VDD_%s to %d.%03dV.\n", 7987 bb_vs_config[bx][i].function, INT_FRAC_3PT_3(volts)); 7988 #endif 7989 cli_out("Run \"bb voltage %s calibrate\" to view allowable range.\n", 7990 bb_vs_config[bx][i].function); 7991 7992 return CMD_FAIL; 7993 } 7994 7995 /* Read the ADC to get the actual resultant voltage value. */ 7996 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 7997 &adc_data, bb_vs_config[bx][i].chan) < 0)) { 7998 cli_out("Error: failed to perform A/D conversions.\n"); 7999 } 8000 /* Display the recently configured voltage */ 8001 #ifdef COMPILER_HAS_DOUBLE 8002 cli_out("VDD_%s = %2.3f Volts " 8003 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 8004 bb_vs_config[bx][i].function, adc_data.val, 8005 adc_data.min,adc_data.max, adc_data.delta, 8006 adc_data.nsamples); 8007 #else 8008 cli_out("VDD_%s = %d.%03d Volts " 8009 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n", 8010 bb_vs_config[bx][i].function, 8011 INT_FRAC_3PT_3(adc_data.val), 8012 INT_FRAC_3PT_3(adc_data.min), 8013 INT_FRAC_3PT_3(adc_data.max), 8014 INT_FRAC_3PT_3(adc_data.delta), 8015 adc_data.nsamples); 8016 #endif 8017 } 8018 } 8019 } /* Set a single voltage */ 8020 else { 8021 if (bb_vs_config[bx][i].mux != NO_MUX) { 8022 char *dev_name; 8023 /* Open MUX (lpt0) device */ 8024 dev_name = _i2c_mux_default_dev_name_get(); 8025 if ( (mux = bcm_i2c_open(unit, dev_name, flags, 0)) < 0) { 8026 cli_out("Could not open %s for mux selection:%s\n", 8027 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 8028 return CMD_FAIL; 8029 } 8030 /* Set mux value so we can see the device when we try to open it*/ 8031 if( (rv = bcm_i2c_write(unit, mux, 0, 8032 &bb_vs_config[bx][i].mux, 1)) < 0){ 8033 cli_out("Error: write of lpt byte failed:%s\n", 8034 bcm_errmsg(rv)); 8035 return CMD_FAIL; 8036 } 8037 } 8038 8039 /* Reading voltage, current and power on LTC 3880/3882 deivce */ 8040 if( bb_vs_config[bx][i].flags == PWR_DAC_IO_SRC ) { 8041 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_VOUT, 8042 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 8043 cli_out("Failed to read Voltage of VDD_%s's LTC device \n ", 8044 bb_vs_config[bx][i].function); 8045 return CMD_FAIL; 8046 } 8047 8048 if (soc_get_board_id() == G48) { 8049 /* Refer Saber2 platform */ 8050 /* Calulating voltage based on feedback ratio. */ 8051 /* For 1V output, feedback voltage is 0.549 volts */ 8052 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 8053 dac_op_data = dac_op_data * 1000 / 549; 8054 } 8055 } 8056 if ((soc_get_board_id() == G52) || (soc_get_board_id() == G53) || 8057 (soc_get_board_id() == G54)) { 8058 /* Refer HR3 SVK platform */ 8059 /* Calulating voltage based on feedback ratio. */ 8060 /* For 1V output, feedback voltage is 0.549 volts */ 8061 if (sal_strcmp(bb_vs_all[bx][i].function, "Core") == 0) { 8062 dac_op_data = dac_op_data * 1000 / 549; 8063 } 8064 } 8065 8066 current = bx - G42; 8067 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_IOUT, 8068 ¤t, bb_vs_config[bx][i].chan)) < 0) { 8069 cli_out("Failed to read Current of VDD_%s's LTC device \n ", 8070 bb_vs_config[bx][i].function); 8071 return CMD_FAIL; 8072 } 8073 if ((bcm_i2c_ioctl(unit, adc, I2C_LTC_IOC_READ_POUT, 8074 &power, bb_vs_config[bx][i].chan)) < 0) { 8075 cli_out("Failed to read Power of VDD_%s's ADC device \n ", 8076 bb_vs_config[bx][i].function); 8077 return CMD_FAIL; 8078 } 8079 #ifdef COMPILER_HAS_DOUBLE 8080 cli_out("VDD_%s = %2.3f Volts " 8081 " Current = %2.3f mA Power = %2.3f mW \n", 8082 bb_vs_config[bx][i].function, dac_op_data, 8083 current,power); 8084 #else 8085 cli_out("VDD_%s = %d.%03d Volts " 8086 "Current = %d.%03d mA Power = %d.%03d mW\n", 8087 bb_vs_config[bx][i].function, 8088 INT_FRAC_3PT_3(dac_op_data), 8089 INT_FRAC_3PT(current), 8090 INT_FRAC_3PT(power)); 8091 #endif 8092 return CMD_OK ; 8093 } else if (bb_vs_config[bx][i].flags == PWR_DAC_IO_PMBUS) { 8094 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_VOUT, 8095 &dac_op_data, bb_vs_config[bx][i].chan)) < 0) { 8096 cli_out("Failed to read Voltage of VDD_%s NCP device \n ", 8097 bb_vs_config[bx][i].function); 8098 return CMD_FAIL; 8099 } 8100 if ((bcm_i2c_ioctl(unit, adc, PMBUS_IOC_READ_IOUT, 8101 ¤t, bb_vs_config[bx][i].chan)) < 0) { 8102 cli_out("Failed to read Current of VDD_%s NCP device \n ", 8103 bb_vs_config[bx][i].function); 8104 return CMD_FAIL; 8105 } 8106 if ((soc_get_board_id() == G57) || (soc_get_board_id() == G60) || (soc_get_board_id() == G64)) { 8107 /* NCP81233 does not support READ_POUT */ 8108 power = dac_op_data * current; 8109 } 8110 #ifdef COMPILER_HAS_DOUBLE 8111 cli_out("VDD_%s = %2.3f Volts " 8112 " Current = %2.3f mA Power = %2.3f mW \n", 8113 bb_vs_config[bx][i].function, dac_op_data, 8114 current, power); 8115 #else 8116 cli_out("VDD_%s = %d.%03d Volts " 8117 " Current = %d.%03d mA Power = %d.%03d mW\n", 8118 bb_vs_config[bx][i].function, 8119 INT_FRAC_3PT_3(dac_op_data), 8120 INT_FRAC_3PT(current), 8121 INT_FRAC_3PT(power)); 8122 #endif 8123 return CMD_OK ; 8124 } else { 8125 /* Display a single voltage */ 8126 if ( (bcm_i2c_ioctl(unit, adc, I2C_ADC_QUERY_CHANNEL, 8127 &adc_data, bb_vs_config[bx][i].chan) < 0)) { 8128 cli_out("Error: failed to perform A/D conversions.\n"); 8129 8130 } 8131 8132 #ifdef COMPILER_HAS_DOUBLE 8133 cli_out("VDD_%s = %2.3f Volts " 8134 "(min=%2.3f max=%2.3f delta=%2.3f samples=%d)\n", 8135 bb_vs_config[bx][i].function, adc_data.val, 8136 adc_data.min,adc_data.max, adc_data.delta, 8137 adc_data.nsamples); 8138 #else 8139 cli_out("VDD_%s = %d.%03d Volts " 8140 "(min=%d.%03d max=%d.%03d delta=%d.%03d samples=%d)\n", 8141 bb_vs_config[bx][i].function, 8142 INT_FRAC_3PT_3(adc_data.val), 8143 INT_FRAC_3PT_3(adc_data.min), 8144 INT_FRAC_3PT_3(adc_data.max), 8145 INT_FRAC_3PT_3(adc_data.delta), 8146 adc_data.nsamples); 8147 #endif 8148 } 8149 } /* Display a single voltage */ 8150 return CMD_OK; 8151 } /* function is "voltage" */ 8152 8153 /* Configure sequencing of device supported 8154 * with bb sequence command 8155 */ 8156 if(!sal_strncasecmp(function,"sequence",sal_strlen(function))) { 8157 /* Check Board Index, which should have sequence config 8158 * parameters. 8159 */ 8160 if(!(baseboard->bbcmd_flags & BB_SEQ ) || bb_sequence_len[bx] == 0) { 8161 cli_out("Error: %s does not support sequence command.\n", 8162 BaseboardName); 8163 return CMD_FAIL; 8164 } 8165 /* Show all timing sequences */ 8166 if(!source || (!sal_strcasecmp("all", source) && value)) { 8167 for(i = 0; i < bb_sequence_len[bx]; i++) { 8168 if (bb_sequence[bx][i].mux != 0xFF) { 8169 char *dev_name; 8170 /* Open MUX (lpt0) device */ 8171 dev_name = _i2c_mux_default_dev_name_get(); 8172 if ((mux = bcm_i2c_open(unit, dev_name, flags, 0)) < 0) { 8173 cli_out("Could not open %s for mux selection:%s\n", 8174 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 8175 return CMD_FAIL; 8176 } 8177 8178 /* Set mux value so we can see the device when we try to open it*/ 8179 if((rv = bcm_i2c_write(unit, mux, 0, &bb_sequence[bx][i].mux, 1)) < 0) { 8180 cli_out("Error: write of lpt byte failed:%s\n", 8181 bcm_errmsg(rv)); 8182 return CMD_FAIL; 8183 } 8184 } 8185 /* Going to open the correct DAC */ 8186 if ( (dac = bcm_i2c_open(unit, bb_sequence[bx][i].dac, 8187 flags, 0)) < 0) { 8188 8189 cli_out("Could not open %s:%s\n",bb_sequence[bx][i].dac, 8190 bcm_errmsg(dac)); 8191 return CMD_FAIL; 8192 } 8193 8194 if (source && value ) { 8195 #ifdef COMPILER_HAS_DOUBLE 8196 dac_op_data = atof( value ) ; 8197 if(dac_op_data <= bb_sequence[bx][i].max) 8198 #else 8199 /* Parse input in ms and convert to ns */ 8200 dac_op_data = _shr_atof_exp10(value, 6); 8201 if(dac_op_data <= bb_sequence[bx][i].max*1000000) 8202 #endif 8203 { 8204 if ((bcm_i2c_ioctl(unit, dac, I2C_SET_SEQ, 8205 &dac_op_data, bb_sequence[bx][i].chan)) < 0) { 8206 cli_out("Failed to set sequence for VDD_%s LTC device \n ", 8207 bb_sequence[bx][i].function); 8208 return CMD_FAIL; 8209 } 8210 } else { 8211 cli_out("Error:value is out of range for VDD_%s LTC device \n ", 8212 bb_sequence[bx][i].function); 8213 return CMD_FAIL; 8214 } 8215 } 8216 8217 if ((bcm_i2c_ioctl(unit, dac, I2C_READ_SEQ, 8218 &time_ms, bb_sequence[bx][i].chan)) < 0) { 8219 cli_out("Failed to read sequence for VDD_%s LTC device \n ", 8220 bb_sequence[bx][i].function); 8221 return CMD_FAIL; 8222 } 8223 8224 #ifdef COMPILER_HAS_DOUBLE 8225 cli_out("VDD_%s(%s) = %2.3f ms " 8226 "Range (Min=%d ms Max=%d ms)\n", 8227 bb_sequence[bx][i].function, 8228 bb_sequence[bx][i].function, 8229 time_ms, 8230 bb_sequence[bx][i].min, 8231 bb_sequence[bx][i].max); 8232 #else 8233 cli_out("VDD_%s(%s) = %d.%03d ms " 8234 "Range (Min=%d ms Max=%d ms)\n", 8235 bb_sequence[bx][i].function, 8236 bb_sequence[bx][i].function, 8237 INT_FRAC_3PT_3(time_ms), 8238 bb_sequence[bx][i].min, 8239 bb_sequence[bx][i].max); 8240 #endif 8241 } 8242 8243 return CMD_OK; 8244 } /* Show all voltages */ 8245 /* First, find sequence table entry ... */ 8246 for( i = 0; i < bb_sequence_len[bx]; i++) { 8247 if (!sal_strcasecmp(bb_sequence[bx][i].function, source)) 8248 break; 8249 } 8250 /* Not found - ERROR! */ 8251 if(i == bb_sequence_len[bx]){ 8252 cli_out("Unknown Voltage source: %s\n for sequencing", source); 8253 return CMD_USAGE; 8254 } 8255 8256 if (bb_sequence[bx][i].mux != 0xFF) { 8257 char *dev_name; 8258 /* Open MUX (lpt0) device */ 8259 dev_name = _i2c_mux_default_dev_name_get(); 8260 if ((mux = bcm_i2c_open(unit, dev_name, flags, 0)) < 0) { 8261 cli_out("Could not open %s for mux selection:%s\n", 8262 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 8263 return CMD_FAIL; 8264 } 8265 8266 /* Set mux value so we can see the device when we try to open it*/ 8267 if((rv = bcm_i2c_write(unit, mux, 0, &bb_sequence[bx][i].mux, 1)) < 0){ 8268 cli_out("Error: write of lpt byte failed:%s\n", 8269 bcm_errmsg(rv)); 8270 return CMD_FAIL; 8271 } 8272 } 8273 /* Going to open the correct DAC */ 8274 if ((dac = bcm_i2c_open(unit, bb_sequence[bx][i].dac, 8275 flags, 0)) < 0) { 8276 8277 cli_out("Could not open %s:%s\n",bb_sequence[bx][i].dac, 8278 bcm_errmsg(dac)); 8279 return CMD_FAIL; 8280 } 8281 if (value) { 8282 #ifdef COMPILER_HAS_DOUBLE 8283 dac_op_data = atof(value) ; 8284 if(dac_op_data <= bb_sequence[bx][i].max) 8285 #else 8286 /* Parse input in ms and convert to ns */ 8287 dac_op_data = _shr_atof_exp10(value, 6); 8288 if(dac_op_data <= bb_sequence[bx][i].max * 1000000 ) 8289 #endif 8290 { if ((bcm_i2c_ioctl(unit, dac, I2C_SET_SEQ, 8291 &dac_op_data, bb_sequence[bx][i].chan)) < 0) { 8292 cli_out("Failed to set sequence for VDD_%s LTC device \n ", 8293 bb_sequence[bx][i].function); 8294 return CMD_FAIL; 8295 } 8296 } else { 8297 cli_out("Error:value is out of range for VDD_%s LTC device \n ", 8298 bb_sequence[bx][i].function); 8299 return CMD_FAIL; 8300 } 8301 } 8302 if ((bcm_i2c_ioctl(unit, dac, I2C_READ_SEQ, 8303 &time_ms, bb_sequence[bx][i].chan)) < 0) { 8304 cli_out("Failed to read sequence for VDD_%s LTC device \n ", 8305 bb_sequence[bx][i].function); 8306 return CMD_FAIL; 8307 } 8308 #ifdef COMPILER_HAS_DOUBLE 8309 cli_out("VDD_%s(%s) = %2.3f ms " 8310 "Range (Min=%d ms Max=%d ms)\n", 8311 bb_sequence[bx][i].function, 8312 bb_sequence[bx][i].function, 8313 time_ms, 8314 bb_sequence[bx][i].min, 8315 bb_sequence[bx][i].max); 8316 #else 8317 cli_out("VDD_%s(%s) = %d.%03d ms " 8318 "Range (Min=%d ms Max=%d ms)\n", 8319 bb_sequence[bx][i].function, 8320 bb_sequence[bx][i].function, 8321 INT_FRAC_3PT_3(time_ms), 8322 bb_sequence[bx][i].min, 8323 bb_sequence[bx][i].max); 8324 #endif 8325 } 8326 else { 8327 return CMD_USAGE; 8328 } /* Unknown function */ 8329 8330 return CMD_OK ; 8331 } /* end cmd_bb() */ 8332 8333 STATIC int dac_devs_init (int unit,int bx,char *dev_name) 8334 { 8335 int mux; 8336 int i; 8337 int dac; 8338 int rv = 0; 8339 int flags = 0; 8340 8341 /* open mux device used for all channel's DAC devices 8342 * DAC devices behind the mux device need not be the same device. 8343 */ 8344 if ( (mux = bcm_i2c_open(unit, dev_name, flags, 0)) < 0) { 8345 cli_out("Could not open %s for mux selection:%s\n", 8346 dev_name?dev_name:"MUX_DEV", bcm_errmsg(mux)); 8347 return CMD_FAIL; 8348 } 8349 8350 /* initialize each dac device behind the I2C mux device */ 8351 for (i = 0; i < bb_vs_config_len[bx]; i++) { 8352 if (bb_vs_config[bx][i].dac == NULL) { 8353 break; 8354 } 8355 if( (rv = bcm_i2c_write(unit, mux, 0, 8356 &bb_vs_config[bx][i].mux, 1)) < 0) { 8357 cli_out("Error: write of mux device byte failed:%s\n", 8358 bcm_errmsg(rv)); 8359 return CMD_FAIL; 8360 } 8361 8362 /* get dac diver's device id */ 8363 if ((dac = bcm_i2c_open(unit, bb_vs_config[bx][i].dac, 8364 flags, 0)) < 0) { 8365 cli_out("Could not open %s:%s\n", 8366 bb_vs_config[bx][i].dac, bcm_errmsg(dac)); 8367 return CMD_FAIL; 8368 } 8369 soc_i2c_device(unit, dac)->driver->load(unit,dac,NULL,0); 8370 } 8371 8372 return SOC_E_NONE; 8373 } 8374 8375 #if defined(SHADOW_SVK) 8376 8377 #define PIO_PORT_0 (1<<0) 8378 #define PIO_PORT_1 (1<<1) 8379 8380 /* 8381 */ 8382 char cmd_pio_usage[] = 8383 "Usages:\n\t" 8384 " pio dev port [data]\n\t" 8385 " - show and change contents of parallel IO ports\n\t" 8386 "\n"; 8387 8388 cmd_result_t 8389 cmd_pio(int unit, args_t *a) 8390 { 8391 int dev, port, data; 8392 int dev_mask, port_mask; 8393 parse_table_t pt; 8394 int i, max; 8395 int fd, rv; 8396 uint32 len; 8397 int banner; 8398 uint8 rd_data, wr_data; 8399 char *name; 8400 8401 #ifdef SHADOW_SVK 8402 max = 2; 8403 #endif 8404 dev = port = data = -1; 8405 dev_mask = 1 << max; 8406 port_mask = 0xff; 8407 8408 parse_table_init(0, &pt); 8409 parse_table_add(&pt, "DEv", PQ_DFL|PQ_INT, 0, 8410 &dev, NULL); 8411 parse_table_add(&pt, "Port", PQ_DFL|PQ_INT, 0, 8412 &port, NULL); 8413 parse_table_add(&pt, "Data", PQ_DFL|PQ_INT, 0, 8414 &data, NULL); 8415 if (parse_arg_eq(a, &pt) < 0) { 8416 cli_out("%s: Invalid argument: %s\n", ARG_CMD(a), ARG_CUR(a)); 8417 parse_arg_eq_done(&pt); 8418 return(CMD_FAIL); 8419 } 8420 parse_arg_eq_done(&pt); 8421 8422 if (dev != -1) { 8423 if (dev >= 0 && dev < max) { 8424 dev_mask = (1 << dev); 8425 } else { 8426 cli_out("Valid dev 0..%d\n", max); 8427 return CMD_FAIL; 8428 } 8429 } 8430 if (port != -1) { 8431 if (port >= 0 && port <= 4) { 8432 port_mask = (1 << port); 8433 } else { 8434 cli_out("Valid port 0..4\n"); 8435 return CMD_FAIL; 8436 } 8437 } 8438 8439 for (dev = 0; dev < max; dev++) { 8440 pio_devname(dev, &name); 8441 if (!((1<<dev) & dev_mask)) { 8442 continue; 8443 } 8444 { 8445 fd = bcm_i2c_open(unit, name, 0, 0); 8446 if (fd < 0) { 8447 cli_out("Failed opening %s\n", name); 8448 continue; 8449 } 8450 } 8451 8452 banner = 0; 8453 for (port = 0; port < 5; port++) { 8454 int bit; 8455 if (!((1<<port) & port_mask)) { 8456 continue; 8457 } 8458 if (data != -1) { 8459 if (data > 255) { 8460 cli_out("Data must be 0..255\n"); 8461 break; 8462 } 8463 wr_data = data; 8464 /*cli_out("writing port dev %d %d <- %d\n", dev, port, 8465 * wr_data);*/ 8466 8467 rv = bcm_i2c_write(unit, fd, I2C_IOP_OUT(port), (uint8 *)&wr_data, 1); 8468 if (rv != SOC_E_NONE) { 8469 cli_out("%s:Port%d Is INPUT Port\n", name, port); 8470 } 8471 } else { 8472 for(i = 0; i < 2; i++) { 8473 rv = bcm_i2c_read(unit, fd, 0x8 * i + port, 8474 (uint8 *)&rd_data, &len); 8475 if (rv != SOC_E_NONE) { 8476 cli_out("Failed reading %s: %s\n", name, bcm_errmsg(rv)); 8477 } 8478 if (! banner) { 8479 banner++; 8480 cli_out("PIO %s:", name); 8481 } 8482 cli_out("%s Port[%d]: ", 8483 (i == 0) ? "\n Input:": " Output:",port); 8484 for (bit = 7; bit >= 0; bit--) { 8485 if (bit == 3) { 8486 cli_out(" "); 8487 } 8488 cli_out("%c", (rd_data & (1 << bit)) ? '1' : '0'); 8489 } 8490 } 8491 } 8492 } 8493 cli_out("\n"); 8494 } 8495 return CMD_OK ; 8496 } 8497 #endif /* SHADOW_SVK */ 8498 8499 8500 8501 #endif /* INCLUDE_I2C */ 8502 8503 8504 #endif /* NO_SAL_APPL */