tm_show.c (70144B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Diag CLI TMCheck command 8 */ 9 10 #include <soc/defs.h> 11 #if defined(BCM_TOMAHAWK3_SUPPORT) 12 13 #include <appl/diag/system.h> 14 #include <appl/diag/parse.h> 15 #include <shared/bsl.h> 16 #include <bcm/error.h> 17 18 #include <soc/tomahawk3.h> 19 #include <soc/init/tomahawk3_idb_init.h> 20 21 #define _TH3_EGR_Q_RESUME_LMT_GRAN 8 22 #define _TH3_EGR_Q_DROP_STATE_OFFSET_GREEN 2 23 #define UINT64_HEXA_STR_MAX_SIZE 20 24 #define _TH3_IDB_THD_GRAN 64 25 #define _TH3_NUM_MTR_GRAN 8 26 27 #ifdef __KERNEL__ 28 #define atoi _shr_ctoi 29 #endif 30 31 32 char cmd_tm_show_usage[] = 33 " tmshow ing_buf_debug <port> <pri_grp> \n" 34 " tmshow ing_buf_debug <port> <queue> \n"; 35 36 37 typedef enum _soc_th3_ing_config_type_e { 38 _SOC_TH3_ING_INPPRI_PROFILE = 0, 39 _SOC_TH3_ING_PG_PROFILE, 40 _SOC_TH3_ING_ERROR 41 } _soc_th3_ing_config_type_t; 42 43 STATIC int 44 _soc_th3_ing_port_cfg_profile_get (int unit, int port, 45 _soc_th3_ing_config_type_t th3_ing_cfg, int *profile) { 46 soc_reg_t port_prof_reg = MMU_THDI_ING_PORT_CONFIGr; 47 soc_field_t port_prof_fld; 48 uint32 rval = 0; 49 50 switch(th3_ing_cfg) { 51 case _SOC_TH3_ING_INPPRI_PROFILE: 52 port_prof_fld = INPPRI_PROFILE_SELf; 53 break; 54 case _SOC_TH3_ING_PG_PROFILE: 55 port_prof_fld = PG_PROFILE_SELf; 56 break; 57 default: 58 port_prof_fld = INVALIDf; 59 break; 60 } 61 if (port_prof_fld != INVALIDf) { 62 SOC_IF_ERROR_RETURN 63 (soc_reg32_get(unit, port_prof_reg, port, 0, &rval)); 64 *profile = soc_reg_field_get(unit, port_prof_reg, rval, port_prof_fld); 65 return SOC_E_NONE; 66 } 67 return SOC_E_INTERNAL; 68 } 69 70 static const soc_field_t pg_sp_flds[_TH3_MMU_NUM_PG] = {PG0_SPIDf, PG1_SPIDf, 71 PG2_SPIDf, PG3_SPIDf, PG4_SPIDf, PG5_SPIDf, PG6_SPIDf, PG7_SPIDf}; 72 73 static const soc_field_t pg_hp_flds[_TH3_MMU_NUM_PG] = {PG0_HPIDf, PG1_HPIDf, 74 PG2_HPIDf, PG3_HPIDf, PG4_HPIDf, PG5_HPIDf, PG6_HPIDf, PG7_HPIDf}; 75 76 STATIC int 77 _soc_th3_ing_pg_pools_get(int unit, int port, int pg, int *spid, int *hpid) { 78 int port_profile; 79 uint64 rval64; 80 soc_reg_t pg_pool_reg = MMU_THDI_PG_PROFILEr; 81 82 SOC_IF_ERROR_RETURN 83 (_soc_th3_ing_port_cfg_profile_get(unit, port, 84 _SOC_TH3_ING_PG_PROFILE, 85 &port_profile)); 86 COMPILER_64_ZERO(rval64); 87 SOC_IF_ERROR_RETURN 88 (soc_reg_get(unit, pg_pool_reg, port_profile, 0, &rval64)); 89 *spid = soc_reg64_field32_get(unit, pg_pool_reg, rval64, pg_sp_flds[pg]); 90 *hpid = soc_reg64_field32_get(unit, pg_pool_reg, rval64, pg_hp_flds[pg]); 91 return SOC_E_NONE; 92 } 93 94 static const soc_field_t pg_min_limit_flds[_TH3_MMU_NUM_PG] = {PG0_MIN_LIMITf, 95 PG1_MIN_LIMITf, PG2_MIN_LIMITf, PG3_MIN_LIMITf, PG4_MIN_LIMITf, 96 PG5_MIN_LIMITf, PG6_MIN_LIMITf, PG7_MIN_LIMITf}; 97 98 static const soc_field_t pg_min_en_flds[_TH3_MMU_NUM_PG] = {PG0_USE_PORTSP_MINf, 99 PG1_USE_PORTSP_MINf, PG2_USE_PORTSP_MINf, PG3_USE_PORTSP_MINf, 100 PG4_USE_PORTSP_MINf, PG5_USE_PORTSP_MINf, PG6_USE_PORTSP_MINf, 101 PG7_USE_PORTSP_MINf}; 102 103 static const soc_field_t pg_min_count_flds[_TH3_MMU_NUM_PG] = {PG0_MIN_COUNTf, 104 PG1_MIN_COUNTf, PG2_MIN_COUNTf, PG3_MIN_COUNTf, PG4_MIN_COUNTf, 105 PG5_MIN_COUNTf, PG6_MIN_COUNTf, PG7_MIN_COUNTf}; 106 107 static const soc_field_t ing_portsp_min_limit_flds[_TH3_MMU_NUM_POOL] = 108 {PORTSP0_MIN_LIMITf, PORTSP1_MIN_LIMITf, PORTSP2_MIN_LIMITf, PORTSP3_MIN_LIMITf}; 109 110 static const soc_field_t ing_portsp_min_count_flds[_TH3_MMU_NUM_POOL] = 111 {PORTSP0_MIN_COUNTf, PORTSP1_MIN_COUNTf, PORTSP2_MIN_COUNTf, 112 PORTSP3_MIN_COUNTf}; 113 114 STATIC int 115 _soc_th3_port_pg_min_debug_print(int unit, int port, int pg) { 116 int pipe, mmu_local_port, enable; 117 int limit_cells, usage_cells; 118 soc_info_t *si = &SOC_INFO(unit); 119 soc_mem_t usage_mem = MMU_THDI_PORT_PG_MIN_COUNTERm; 120 soc_mem_t config_mem = MMU_THDI_PORT_PG_MIN_CONFIGm; 121 uint32 entry[SOC_MAX_MEM_WORDS]; 122 soc_mem_t read_mem = INVALIDm; 123 124 pipe = si->port_pipe[port]; 125 mmu_local_port = si->port_l2i_mapping[port]; 126 127 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, config_mem, pipe); 128 SOC_IF_ERROR_RETURN 129 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 130 /*PG min vs portsp Min*/ 131 enable = !(soc_mem_field32_get(unit, read_mem, &entry, pg_min_en_flds[pg])); 132 /*PG min limit*/ 133 limit_cells = soc_mem_field32_get(unit, read_mem, &entry, 134 pg_min_limit_flds[pg]); 135 136 /*PG min counter*/ 137 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, usage_mem, pipe); 138 SOC_IF_ERROR_RETURN 139 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 140 usage_cells = soc_mem_field32_get(unit, read_mem, &entry, 141 pg_min_count_flds[pg]); 142 143 cli_out("PG Min: Enable: %1d, Limit: %7d, Usage: %13d \n", 144 enable, limit_cells, usage_cells); 145 146 return SOC_E_NONE; 147 } 148 149 static const soc_field_t pg_hdrm_limit_flds[_TH3_MMU_NUM_PG] = {PG0_HDRM_LIMITf, 150 PG1_HDRM_LIMITf, PG2_HDRM_LIMITf, PG3_HDRM_LIMITf, PG4_HDRM_LIMITf, 151 PG5_HDRM_LIMITf, PG6_HDRM_LIMITf, PG7_HDRM_LIMITf}; 152 153 static const soc_field_t pg_hdrm_count_flds[_TH3_MMU_NUM_PG] = {PG0_HDRM_COUNTf, 154 PG1_HDRM_COUNTf, PG2_HDRM_COUNTf, PG3_HDRM_COUNTf, PG4_HDRM_COUNTf, 155 PG5_HDRM_COUNTf, PG6_HDRM_COUNTf, PG7_HDRM_COUNTf}; 156 157 158 STATIC int 159 _soc_th3_port_pg_hdrm_debug_print(int unit, int port, int pg) { 160 int pipe, mmu_local_port; 161 int limit_cells, usage_cells; 162 soc_info_t *si = &SOC_INFO(unit); 163 soc_mem_t usage_mem = MMU_THDI_PORT_PG_HDRM_COUNTERm; 164 soc_mem_t config_mem = MMU_THDI_PORT_PG_HDRM_CONFIGm; 165 uint32 entry[SOC_MAX_MEM_WORDS]; 166 soc_mem_t read_mem = INVALIDm; 167 168 pipe = si->port_pipe[port]; 169 mmu_local_port = si->port_l2i_mapping[port]; 170 171 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, config_mem, pipe); 172 SOC_IF_ERROR_RETURN 173 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 174 /* PG hdrm limit */ 175 limit_cells = soc_mem_field32_get(unit, read_mem, &entry, 176 pg_hdrm_limit_flds[pg]); 177 178 /* PG hdrm counter */ 179 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, usage_mem, pipe); 180 SOC_IF_ERROR_RETURN 181 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 182 usage_cells = soc_mem_field32_get(unit, read_mem, &entry, 183 pg_hdrm_count_flds[pg]); 184 185 cli_out("PG Headroom: Limit: %7d, Usage: %13d \n", 186 limit_cells, usage_cells); 187 188 return SOC_E_NONE; 189 } 190 191 STATIC int 192 _soc_th3_port_ing_portsp_min_debug_print(int unit, int port, int pg) { 193 int pipe, mmu_local_port, enable, spid, hpid; 194 int limit_cells, usage_cells; 195 soc_info_t *si = &SOC_INFO(unit); 196 soc_mem_t usage_mem = MMU_THDI_PORTSP_COUNTERm; 197 soc_mem_t pg_config_mem = MMU_THDI_PORT_PG_MIN_CONFIGm; 198 soc_mem_t config_mem = MMU_THDI_PORTSP_CONFIGm; 199 uint32 entry[SOC_MAX_MEM_WORDS]; 200 soc_mem_t read_mem = INVALIDm; 201 202 pipe = si->port_pipe[port]; 203 mmu_local_port = si->port_l2i_mapping[port]; 204 SOC_IF_ERROR_RETURN( 205 _soc_th3_ing_pg_pools_get(unit, port, pg, &spid, &hpid)); 206 207 /*Port SP min enable*/ 208 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, pg_config_mem, pipe); 209 SOC_IF_ERROR_RETURN 210 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 211 enable = (soc_mem_field32_get(unit, read_mem, &entry, pg_min_en_flds[pg])); 212 213 214 /*Port SP min limit*/ 215 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, config_mem, pipe); 216 SOC_IF_ERROR_RETURN 217 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 218 limit_cells = soc_mem_field32_get(unit, read_mem, &entry, 219 ing_portsp_min_limit_flds[spid]); 220 221 /*Port SP Min Count*/ 222 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, usage_mem, pipe); 223 SOC_IF_ERROR_RETURN 224 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 225 usage_cells = soc_mem_field32_get(unit, read_mem, &entry, 226 ing_portsp_min_count_flds[spid]); 227 228 cli_out("PortSP Min: Enable: %1d, Limit: %7d, Usage: %13d \n", 229 enable, limit_cells, usage_cells); 230 231 return SOC_E_NONE; 232 } 233 234 static const soc_field_t pg_shr_limit_flds[_TH3_MMU_NUM_PG] = {PG0_SHARED_LIMITf, 235 PG1_SHARED_LIMITf, PG2_SHARED_LIMITf, PG3_SHARED_LIMITf, PG4_SHARED_LIMITf, 236 PG5_SHARED_LIMITf, PG6_SHARED_LIMITf, PG7_SHARED_LIMITf}; 237 238 static const soc_field_t pg_shr_count_flds[_TH3_MMU_NUM_PG] = {PG0_SHARED_COUNTf, 239 PG1_SHARED_COUNTf, PG2_SHARED_COUNTf, PG3_SHARED_COUNTf, PG4_SHARED_COUNTf, 240 PG5_SHARED_COUNTf, PG6_SHARED_COUNTf, PG7_SHARED_COUNTf}; 241 242 static const soc_field_t pg_shr_dyn_flds[_TH3_MMU_NUM_PG] = {PG0_SHARED_DYNAMICf, 243 PG1_SHARED_DYNAMICf, PG2_SHARED_DYNAMICf, PG3_SHARED_DYNAMICf, PG4_SHARED_DYNAMICf, 244 PG5_SHARED_DYNAMICf, PG6_SHARED_DYNAMICf, PG7_SHARED_DYNAMICf}; 245 246 static const soc_field_t pg_reset_offset_flds[_TH3_MMU_NUM_PG] = 247 {PG0_RESET_OFFSETf, PG1_RESET_OFFSETf, PG2_RESET_OFFSETf, PG3_RESET_OFFSETf, 248 PG4_RESET_OFFSETf, PG5_RESET_OFFSETf, PG6_RESET_OFFSETf, PG7_RESET_OFFSETf}; 249 250 static const soc_field_t pg_reset_floor_flds[_TH3_MMU_NUM_PG] = 251 {PG0_RESET_FLOORf, PG1_RESET_FLOORf, PG2_RESET_FLOORf, PG3_RESET_FLOORf, 252 PG4_RESET_FLOORf, PG5_RESET_FLOORf, PG6_RESET_FLOORf, PG7_RESET_FLOORf}; 253 254 STATIC int 255 _soc_th3_port_pg_shr_debug_print(int unit, int port, int pg) { 256 int pipe, mmu_local_port, dynamic; 257 int limit_cells, usage_cells, reset_offset, reset_floor; 258 soc_info_t *si = &SOC_INFO(unit); 259 soc_mem_t usage_mem = MMU_THDI_PORT_PG_SHARED_COUNTERm; 260 soc_mem_t config_mem = MMU_THDI_PORT_PG_SHARED_CONFIGm; 261 soc_mem_t resume_mem = MMU_THDI_PORT_PG_RESUME_CONFIGm; 262 uint32 entry[SOC_MAX_MEM_WORDS]; 263 soc_mem_t read_mem = INVALIDm; 264 soc_reg_t xoff_state_reg = MMU_THDI_FLOW_CONTROL_XOFF_STATEr; 265 soc_field_t xoff_state_field = PG_XOFF_FCf; 266 uint32 rval = 0; 267 int port_xoff = 0, pg_xoff = 0; 268 269 pipe = si->port_pipe[port]; 270 mmu_local_port = si->port_l2i_mapping[port]; 271 272 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, config_mem, pipe); 273 SOC_IF_ERROR_RETURN 274 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 275 /* PG share dynamic enable */ 276 dynamic = (soc_mem_field32_get(unit, read_mem, &entry, pg_shr_dyn_flds[pg])); 277 /* PG shared limit */ 278 limit_cells = soc_mem_field32_get(unit, read_mem, &entry, 279 pg_shr_limit_flds[pg]); 280 281 /* PG shared counter */ 282 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, usage_mem, pipe); 283 SOC_IF_ERROR_RETURN 284 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 285 usage_cells = soc_mem_field32_get(unit, read_mem, &entry, 286 pg_shr_count_flds[pg]); 287 288 /* PG XOFF state */ 289 SOC_IF_ERROR_RETURN 290 (soc_reg32_get(unit, xoff_state_reg, port, 0, &rval)); 291 port_xoff = soc_reg_field_get(unit, xoff_state_reg, rval, xoff_state_field); 292 if (port_xoff & (1 << pg)) { 293 pg_xoff = 1; 294 } 295 296 /* PG Reset Offset */ 297 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, resume_mem, pipe); 298 SOC_IF_ERROR_RETURN 299 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 300 reset_offset = soc_mem_field32_get(unit, read_mem, &entry, 301 pg_reset_offset_flds[pg]); 302 /* PG Reset Floor */ 303 reset_floor = soc_mem_field32_get(unit, read_mem, &entry, 304 pg_reset_floor_flds[pg]); 305 306 if (dynamic == 1) { 307 cli_out("PG Shared: Dynamic: %1d, Alpha: %7d, Usage: %13d Xoff State:" 308 " %1d\n", dynamic, limit_cells, usage_cells, pg_xoff); 309 } else { 310 cli_out("PG Shared: Dynamic: %1d, Limit: %7d, Usage: %13d Xoff State:" 311 " %1d\n", dynamic, limit_cells, usage_cells, pg_xoff); 312 } 313 cli_out(" ResumeOffset: %7d, Floor: %13d\n", reset_offset, 314 reset_floor); 315 return SOC_E_NONE; 316 } 317 318 319 static const soc_field_t ing_portsp_shr_limit_flds[_TH3_MMU_NUM_POOL] = { 320 PORTSP0_SHARED_LIMITf, PORTSP1_SHARED_LIMITf, PORTSP2_SHARED_LIMITf, 321 PORTSP3_SHARED_LIMITf}; 322 323 324 static const soc_field_t ing_portsp_resume_limit_flds[_TH3_MMU_NUM_POOL] = { 325 PORTSP0_RESUME_LIMITf, PORTSP1_RESUME_LIMITf, PORTSP2_RESUME_LIMITf, 326 PORTSP3_RESUME_LIMITf}; 327 328 static const soc_field_t ing_portsp_shr_count_flds[_TH3_MMU_NUM_POOL] = { 329 PORTSP0_SHARED_COUNTf, PORTSP1_SHARED_COUNTf, PORTSP2_SHARED_COUNTf, 330 PORTSP3_SHARED_COUNTf}; 331 332 333 STATIC int 334 _soc_th3_ing_portsp_shr_debug_print(int unit, int port, int pg) { 335 int pipe, mmu_local_port; 336 int limit_cells, usage_cells, resume_lmt; 337 soc_info_t *si = &SOC_INFO(unit); 338 soc_mem_t usage_mem = MMU_THDI_PORTSP_COUNTERm; 339 soc_mem_t config_mem = MMU_THDI_PORTSP_CONFIGm; 340 uint32 entry[SOC_MAX_MEM_WORDS]; 341 soc_mem_t read_mem = INVALIDm; 342 soc_reg_t limit_state_reg = MMU_THDI_PORT_LIMIT_STATESr; 343 soc_field_t portsp_lmt = PORTSP_LIMIT_STATEf; 344 uint32 rval; 345 int spid, hpid, limit_state, sp_limit_state = 0; 346 347 pipe = si->port_pipe[port]; 348 mmu_local_port = si->port_l2i_mapping[port]; 349 SOC_IF_ERROR_RETURN( 350 _soc_th3_ing_pg_pools_get(unit, port, pg, &spid, &hpid)); 351 352 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, config_mem, pipe); 353 SOC_IF_ERROR_RETURN 354 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 355 /* PortSP shared limit */ 356 limit_cells = soc_mem_field32_get(unit, read_mem, &entry, 357 ing_portsp_shr_limit_flds[spid]); 358 /* PortSP Reusme Limit */ 359 resume_lmt = soc_mem_field32_get(unit, read_mem, &entry, 360 ing_portsp_resume_limit_flds[spid]); 361 362 /* PortSP shared counter */ 363 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, usage_mem, pipe); 364 SOC_IF_ERROR_RETURN 365 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 366 usage_cells = soc_mem_field32_get(unit, read_mem, &entry, 367 ing_portsp_shr_count_flds[spid]); 368 369 /* PortSP Limit State */ 370 rval = 0; 371 SOC_IF_ERROR_RETURN 372 (soc_reg32_get(unit, limit_state_reg, port, 0, &rval)); 373 limit_state = soc_reg_field_get(unit, limit_state_reg, rval, portsp_lmt); 374 if(limit_state & (1 << spid)) { 375 sp_limit_state = 1; 376 } 377 378 cli_out("PortSP Shared: Limit: %7d, Usage: %13d, Limit Hit: %1d \n", 379 limit_cells, usage_cells, sp_limit_state); 380 cli_out(" Reset Limit: %7d\n", resume_lmt); 381 return SOC_E_NONE; 382 } 383 384 STATIC int 385 _soc_th3_ing_service_pool_print(int unit, int pool) { 386 soc_reg_t sp_limit_reg = MMU_THDI_BUFFER_CELL_LIMIT_SPr; 387 soc_field_t sp_limit_fld = LIMITf; 388 soc_reg_t sp_count_reg = MMU_THDI_POOL_SHARED_COUNT_SPr; 389 soc_field_t sp_count_fld = TOTAL_BUFFER_COUNTf; 390 soc_reg_t sp_reset_reg = MMU_THDI_CELL_RESET_LIMIT_OFFSET_SPr; 391 soc_field_t sp_reset_offset_fld = OFFSETf; 392 soc_reg_t sp_drop_state_reg = MMU_THDI_POOL_DROP_STATEr; 393 soc_field_t sp_drop_state_flds[_TH3_MMU_NUM_POOL] = {POOL_0f, POOL_1f, 394 POOL_2f, POOL_3f}; 395 uint32 rval = 0; 396 int sp_limit, sp_count, sp_offset, drop_state, green_drop_state; 397 if (pool >= _TH3_MMU_NUM_POOL) { 398 return SOC_E_PARAM; 399 } 400 401 SOC_IF_ERROR_RETURN 402 (soc_reg32_get(unit, sp_limit_reg, pool, 0, &rval)); 403 sp_limit = soc_reg_field_get(unit, sp_limit_reg, rval, sp_limit_fld); 404 405 rval = 0; 406 SOC_IF_ERROR_RETURN 407 (soc_reg32_get(unit, sp_count_reg, pool, 0, &rval)); 408 sp_count = soc_reg_field_get(unit, sp_count_reg, rval, sp_count_fld); 409 410 rval = 0; 411 SOC_IF_ERROR_RETURN 412 (soc_reg32_get(unit, sp_reset_reg , pool, 0, &rval)); 413 sp_offset = soc_reg_field_get(unit, sp_reset_reg, rval, sp_reset_offset_fld); 414 415 rval = 0; 416 SOC_IF_ERROR_RETURN 417 (soc_reg32_get(unit, sp_drop_state_reg, 0, 0, &rval)); 418 drop_state = soc_reg_field_get(unit, sp_drop_state_reg, rval, 419 sp_drop_state_flds[pool]); 420 /* The 3 bits [2:0] are organized as {green, yellow, red} drop state */ 421 green_drop_state = (drop_state >> 2); 422 423 cli_out("Ing Service Pool: %1d Limit: %7d, Usage: %13d" 424 " Drop State: %1d\n", 425 pool, sp_limit, sp_count, green_drop_state); 426 cli_out("Ing Service Pool Reset Limit: %7d \n", (sp_limit - sp_offset)); 427 428 return SOC_E_NONE; 429 } 430 431 STATIC int 432 _soc_th3_ing_headroom_pool_print(int unit, int hdrm_pool) { 433 434 soc_reg_t hp_lmt_reg = MMU_THDI_HDRM_BUFFER_CELL_LIMIT_HPr; 435 soc_field_t hp_lmt_fld = LIMITf; 436 soc_reg_t hp_count_reg = MMU_THDI_HDRM_POOL_COUNT_HPr; 437 soc_field_t hp_count_fld = TOTAL_BUFFER_COUNTf; 438 soc_reg_t hp_state_reg = MMU_THDI_HDRM_POOL_STATUSr; 439 soc_field_t hp_state_fld = HDRM_POOL_LIMIT_STATE_HPf; 440 soc_reg_t hp_drop_reg = MMU_THDI_POOL_DROP_COUNT_HPr; 441 soc_field_t hp_drop_fld = PACKET_DROP_COUNTf; 442 uint32 rval = 0; 443 int hp_limit, hp_count, hp_state; 444 uint64 rval64, hp_drop; 445 char tmp[UINT64_HEXA_STR_MAX_SIZE]; 446 447 if (hdrm_pool >= _TH3_MMU_NUM_POOL) { 448 return SOC_E_PARAM; 449 } 450 451 SOC_IF_ERROR_RETURN 452 (soc_reg32_get(unit, hp_lmt_reg, hdrm_pool, 0, &rval)); 453 hp_limit = soc_reg_field_get(unit, hp_lmt_reg, rval, hp_lmt_fld); 454 455 rval = 0; 456 SOC_IF_ERROR_RETURN 457 (soc_reg32_get(unit, hp_count_reg, hdrm_pool, 0, &rval)); 458 hp_count = soc_reg_field_get(unit, hp_count_reg, rval, hp_count_fld); 459 460 rval = 0; 461 SOC_IF_ERROR_RETURN 462 (soc_reg32_get(unit, hp_state_reg, 0, 0, &rval)); 463 hp_state = soc_reg_field_get(unit, hp_state_reg, rval, hp_state_fld); 464 465 COMPILER_64_ZERO(rval64); 466 SOC_IF_ERROR_RETURN 467 (soc_reg_get(unit, hp_drop_reg, hdrm_pool, 0, &rval64)); 468 hp_drop = soc_reg64_field_get(unit, hp_drop_reg, rval64, hp_drop_fld); 469 _shr_format_uint64_hexa_string (hp_drop, tmp); 470 471 cli_out("Headroom Pool: %1d Limit: %7d, Usage: %13d Limit Hit: %1d \n", 472 hdrm_pool, hp_limit, hp_count, 473 ((hp_state >> hdrm_pool) & 1)); 474 475 476 return SOC_E_NONE; 477 } 478 479 STATIC int 480 _soc_th3_pg_debug_print(int unit, int port, int pg) { 481 int spid, hpid; 482 483 if (pg >= _TH3_MMU_NUM_PG) { 484 return SOC_E_PARAM; 485 } 486 487 SOC_IF_ERROR_RETURN 488 (_soc_th3_ing_pg_pools_get(unit, port, pg, &spid, &hpid)); 489 cli_out("### Ingress Buffer Usage Debug Info for Port: %d, PriGrp: %d " 490 "###\n", port, pg); 491 SOC_IF_ERROR_RETURN 492 (_soc_th3_port_pg_min_debug_print(unit, port, pg)); 493 SOC_IF_ERROR_RETURN 494 (_soc_th3_port_pg_shr_debug_print(unit, port, pg)); 495 SOC_IF_ERROR_RETURN 496 (_soc_th3_port_pg_hdrm_debug_print(unit, port, pg)); 497 SOC_IF_ERROR_RETURN 498 (_soc_th3_port_ing_portsp_min_debug_print(unit, port, pg)); 499 SOC_IF_ERROR_RETURN 500 (_soc_th3_ing_portsp_shr_debug_print(unit, port, pg)); 501 SOC_IF_ERROR_RETURN 502 (_soc_th3_ing_service_pool_print(unit, spid)); 503 SOC_IF_ERROR_RETURN 504 (_soc_th3_ing_headroom_pool_print(unit, hpid)); 505 506 return SOC_E_NONE; 507 } 508 509 static int 510 _soc_th3_cpu_queue_debug_print(int unit, int port, int queue) { 511 int min_en, shr_en, shr_dyn; 512 int min_limit, shr_limit, resume_offset; 513 int min_usage, shr_usage; 514 soc_mem_t q_limit_mem = MMU_THDO_QUEUE_CONFIGm; 515 soc_mem_t q_resume_mem = MMU_THDO_QUEUE_RESUME_OFFSETm; 516 soc_mem_t q_usage_mem = MMU_THDO_COUNTER_QUEUEm; 517 soc_reg_t cpu_q_drop_regs[4] = {MMU_THDO_CPU_QUEUE_DROP_STATES_11_00r, 518 MMU_THDO_CPU_QUEUE_DROP_STATES_23_12r, 519 MMU_THDO_CPU_QUEUE_DROP_STATES_35_24r, 520 MMU_THDO_CPU_QUEUE_DROP_STATES_47_36r}; 521 522 soc_field_t cpu_q_drop_flds[SOC_TH3_NUM_CPU_QUEUES] = {DS_QUEUE0f, 523 DS_QUEUE1f, DS_QUEUE2f, DS_QUEUE3f, DS_QUEUE4f, DS_QUEUE5f, DS_QUEUE6f, 524 DS_QUEUE7f, DS_QUEUE8f, DS_QUEUE9f, DS_QUEUE10f, DS_QUEUE11f, DS_QUEUE12f, 525 DS_QUEUE13f, DS_QUEUE14f, DS_QUEUE15f, DS_QUEUE16f, DS_QUEUE17f, 526 DS_QUEUE18f, DS_QUEUE19f, DS_QUEUE20f, DS_QUEUE21f, DS_QUEUE22f, 527 DS_QUEUE23f, DS_QUEUE24f, DS_QUEUE25f, DS_QUEUE26f, DS_QUEUE27f, 528 DS_QUEUE28f, DS_QUEUE29f, DS_QUEUE30f, DS_QUEUE31f, DS_QUEUE32f, 529 DS_QUEUE33f, DS_QUEUE34f, DS_QUEUE35f, DS_QUEUE36f, DS_QUEUE37f, 530 DS_QUEUE38f, DS_QUEUE39f, DS_QUEUE40f, DS_QUEUE41f, DS_QUEUE42f, 531 DS_QUEUE43f, DS_QUEUE44f, DS_QUEUE45f, DS_QUEUE46f, DS_QUEUE47f}; 532 uint32 entry[SOC_MAX_MEM_WORDS]; 533 int itm; 534 soc_mem_t read_mem; 535 int voq, drop_state_fld, drop_state; 536 int q_drop_mem_idx; 537 soc_info_t *si = &SOC_INFO(unit); 538 uint32 rval = 0; 539 540 voq = si->port_cosq_base[port] + queue; 541 q_drop_mem_idx = queue / SOC_TH3_NUM_GP_QUEUES; 542 SOC_IF_ERROR_RETURN 543 (soc_mem_read(unit, q_limit_mem, MEM_BLOCK_ALL, voq, &entry)); 544 min_en = !(soc_mem_field32_get(unit, q_limit_mem, &entry, USE_QGROUP_MINf)); 545 shr_en = soc_mem_field32_get(unit, q_limit_mem, &entry, LIMIT_ENABLEf); 546 shr_dyn = soc_mem_field32_get(unit, q_limit_mem, &entry, LIMIT_DYNAMICf); 547 min_limit = soc_mem_field32_get(unit, q_limit_mem, &entry, MIN_LIMITf); 548 shr_limit = soc_mem_field32_get(unit, q_limit_mem, &entry, SHARED_LIMITf); 549 550 SOC_IF_ERROR_RETURN 551 (soc_mem_read(unit, q_resume_mem, MEM_BLOCK_ALL, voq, &entry)); 552 resume_offset = _TH3_EGR_Q_RESUME_LMT_GRAN * 553 soc_mem_field32_get(unit, q_resume_mem, &entry, RESUME_OFFSETf); 554 555 cli_out("Queue Min: Enable:%1d, Limit: %7d \n", 556 min_en, min_limit); 557 for (itm = 0; itm < NUM_ITM(unit); itm++) { 558 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, q_usage_mem, itm); 559 SOC_IF_ERROR_RETURN 560 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, voq, &entry)); 561 min_usage = soc_mem_field32_get(unit, q_usage_mem, &entry, MIN_COUNTf); 562 563 cli_out(" ITM:%1d, Usage: %7d" 564 "\n", itm, min_usage); 565 } 566 567 if (shr_dyn) { 568 cli_out("Queue Shared: Enable:%1d, Alpha: %7d, ResumeOffset: %7d \n", 569 shr_en, shr_limit, resume_offset); 570 } else { 571 cli_out("Queue Shared: Enable:%1d, Limit: %7d, Reset Limit: %7d\n", 572 shr_en, shr_limit, (shr_limit - resume_offset)); 573 } 574 for (itm = 0; itm < NUM_ITM(unit); itm++) { 575 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, q_usage_mem, itm); 576 SOC_IF_ERROR_RETURN 577 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, voq, &entry)); 578 shr_usage = soc_mem_field32_get(unit, q_usage_mem, &entry, SHARED_COUNTf); 579 580 SOC_IF_ERROR_RETURN 581 (soc_tomahawk3_itm_reg32_get(unit, cpu_q_drop_regs[q_drop_mem_idx], 582 itm, itm, 0, &rval)); 583 drop_state_fld = soc_reg_field_get(unit, 584 cpu_q_drop_regs[q_drop_mem_idx], rval, cpu_q_drop_flds[queue]); 585 drop_state = (drop_state_fld >> _TH3_EGR_Q_DROP_STATE_OFFSET_GREEN) & 1; 586 cli_out(" ITM:%1d, Usage: %7d, DropState: %7d" 587 "\n", itm, shr_usage, drop_state); 588 } 589 590 return SOC_E_NONE; 591 592 } 593 static const soc_field_t q_drop_flds[SOC_TH3_NUM_GP_QUEUES] = {DS_QUEUE0f, 594 DS_QUEUE1f, DS_QUEUE2f, DS_QUEUE3f, DS_QUEUE4f, DS_QUEUE5f, DS_QUEUE6f, 595 DS_QUEUE7f, DS_QUEUE8f, DS_QUEUE9f, DS_QUEUE10f, DS_QUEUE11f}; 596 static int 597 _soc_th3_port_queue_limit_debug_print(int unit, int port, int queue) 598 { 599 int min_en, shr_en, shr_dyn; 600 int min_limit, shr_limit, resume_offset; 601 int min_usage, shr_usage; 602 soc_mem_t q_limit_mem = MMU_THDO_QUEUE_CONFIGm; 603 soc_mem_t q_resume_mem = MMU_THDO_QUEUE_RESUME_OFFSETm; 604 soc_mem_t q_usage_mem = MMU_THDO_COUNTER_QUEUEm; 605 soc_mem_t q_drop_mem = MMU_THDO_PORT_Q_DROP_STATEm; 606 uint32 entry[SOC_MAX_MEM_WORDS]; 607 int itm; 608 soc_mem_t read_mem; 609 int voq, drop_state_fld, drop_state; 610 soc_info_t *si = &SOC_INFO(unit); 611 612 613 voq = si->port_uc_cosq_base[port] + queue; 614 SOC_IF_ERROR_RETURN 615 (soc_mem_read(unit, q_limit_mem, MEM_BLOCK_ALL, voq, &entry)); 616 min_en = !(soc_mem_field32_get(unit, q_limit_mem, &entry, USE_QGROUP_MINf)); 617 shr_en = soc_mem_field32_get(unit, q_limit_mem, &entry, LIMIT_ENABLEf); 618 shr_dyn = soc_mem_field32_get(unit, q_limit_mem, &entry, LIMIT_DYNAMICf); 619 min_limit = soc_mem_field32_get(unit, q_limit_mem, &entry, MIN_LIMITf); 620 shr_limit = soc_mem_field32_get(unit, q_limit_mem, &entry, SHARED_LIMITf); 621 622 SOC_IF_ERROR_RETURN 623 (soc_mem_read(unit, q_resume_mem, MEM_BLOCK_ALL, voq, &entry)); 624 resume_offset = _TH3_EGR_Q_RESUME_LMT_GRAN * 625 soc_mem_field32_get(unit, q_resume_mem, &entry, RESUME_OFFSETf); 626 627 cli_out("Queue Min: Enable:%1d, Limit: %7d \n", 628 min_en, min_limit); 629 for (itm = 0; itm < NUM_ITM(unit); itm++) { 630 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, q_usage_mem, itm); 631 SOC_IF_ERROR_RETURN 632 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, voq, &entry)); 633 min_usage = soc_mem_field32_get(unit, q_usage_mem, &entry, MIN_COUNTf); 634 cli_out(" ITM:%1d, Usage: %7d" 635 "\n", itm, min_usage); 636 } 637 638 if (shr_dyn) { 639 cli_out("Queue Shared: Enable:%1d, Alpha: %7d, ResumeOffset: %7d \n", 640 shr_en, shr_limit, resume_offset); 641 } else { 642 cli_out("Queue Shared: Enable:%1d, Limit: %7d, Reset Limit: %7d\n", 643 shr_en, shr_limit, (shr_limit - resume_offset)); 644 } 645 for (itm = 0; itm < NUM_ITM(unit); itm++) { 646 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, q_usage_mem, itm); 647 SOC_IF_ERROR_RETURN 648 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, voq, &entry)); 649 shr_usage = soc_mem_field32_get(unit, q_usage_mem, &entry, SHARED_COUNTf); 650 651 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, q_drop_mem, itm); 652 SOC_IF_ERROR_RETURN 653 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, voq, &entry)); 654 drop_state_fld = soc_mem_field32_get(unit, q_drop_mem, &entry, 655 q_drop_flds[queue]); 656 drop_state = (drop_state_fld >> _TH3_EGR_Q_DROP_STATE_OFFSET_GREEN) & 1; 657 cli_out(" ITM:%1d, Usage: %7d, DropState: %7d" 658 "\n", itm, shr_usage, drop_state); 659 } 660 661 return SOC_E_NONE; 662 } 663 664 static const soc_mem_t qgrp_mems[2][2] = { 665 {MMU_THDO_CONFIG_UC_QGROUP0m, MMU_THDO_COUNTER_UC_QGROUPm}, 666 {MMU_THDO_CONFIG_MC_QGROUPm, MMU_THDO_COUNTER_MC_QGROUPm}}; 667 668 static int 669 _soc_th3_port_qgroup_limit_debug_print(int unit, int port, int uc_mc, int 670 qgrp_min_en) { 671 soc_mem_t qgrp_cfg_mem = qgrp_mems[uc_mc][0]; 672 soc_mem_t qgrp_cntr_mem = qgrp_mems[uc_mc][1]; 673 int itm, min_lmt, min_usage; 674 soc_mem_t read_mem; 675 uint32 entry[SOC_MAX_MEM_WORDS]; 676 int mmu_chip_port; 677 678 mmu_chip_port = soc_th3_mmu_chip_port_num(unit, port); 679 SOC_IF_ERROR_RETURN 680 (soc_mem_read(unit, qgrp_cfg_mem, MEM_BLOCK_ALL, mmu_chip_port, &entry)); 681 min_lmt = 682 soc_mem_field32_get(unit, qgrp_cfg_mem, &entry, MIN_LIMITf); 683 cli_out("QGroup Min: Enable:%1d, Limit: %7d \n", 684 qgrp_min_en, min_lmt); 685 686 for (itm = 0; itm < NUM_ITM(unit); itm++) { 687 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, qgrp_cntr_mem, itm); 688 SOC_IF_ERROR_RETURN 689 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_chip_port, &entry)); 690 min_usage = soc_mem_field32_get(unit, qgrp_cntr_mem, &entry, MIN_COUNTf); 691 cli_out(" ITM:%1d, Usage: %7d\n", 692 itm, min_usage); 693 } 694 return SOC_E_NONE; 695 } 696 697 static const soc_field_t egr_portsp_lmt_flds[_TH3_MMU_NUM_POOL] = 698 {SP0_SHARED_LIMITf, SP1_SHARED_LIMITf, SP2_SHARED_LIMITf, SP3_SHARED_LIMITf}; 699 700 static const soc_field_t egr_portsp_usage_flds[_TH3_MMU_NUM_POOL] = 701 {SP0_SHARED_COUNTf, SP1_SHARED_COUNTf, SP2_SHARED_COUNTf, SP3_SHARED_COUNTf}; 702 703 static const soc_field_t egr_uc_portsp_drop_flds[_TH3_MMU_NUM_POOL] = {DS_SP0f, 704 DS_SP1f, DS_SP2f, DS_SP3f}; 705 706 static int 707 _soc_th3_egr_portsp_limit_debug_print(int unit, int port, int spid) { 708 soc_mem_t portsp_cfg_mem = MMU_THDO_CONFIG_PORT_UC0m; 709 soc_mem_t resume_mem = MMU_THDO_RESUME_PORT_UC0m; 710 soc_mem_t portsp_cntr_mem = MMU_THDO_COUNTER_PORT_UCm; 711 soc_mem_t drop_mem = MMU_THDO_PORT_SP_DROP_STATE_UCm; 712 soc_mem_t read_mem; 713 uint32 entry[SOC_MAX_MEM_WORDS]; 714 int shr_lmt, itm, shr_usage; 715 uint32 mmu_chip_port; 716 int resume_index, resume_lmt, drop_state_fld, drop_state; 717 718 mmu_chip_port = soc_th3_mmu_chip_port_num(unit, port); 719 resume_index = (mmu_chip_port * _TH3_MMU_NUM_POOL) + spid; 720 721 SOC_IF_ERROR_RETURN 722 (soc_mem_read(unit, portsp_cfg_mem, MEM_BLOCK_ALL, mmu_chip_port, 723 &entry)); 724 shr_lmt = 725 soc_mem_field32_get(unit, portsp_cfg_mem, &entry, 726 egr_portsp_lmt_flds[spid]); 727 SOC_IF_ERROR_RETURN 728 (soc_mem_read(unit, resume_mem, MEM_BLOCK_ALL, resume_index, &entry)); 729 resume_lmt = 730 soc_mem_field32_get(unit, resume_mem, &entry, SHARED_RESUMEf); 731 cli_out("PortSP Shared: Limit: %7d, ResetLimit: %7d \n", 732 shr_lmt, (shr_lmt - resume_lmt)); 733 734 for (itm = 0; itm < NUM_ITM(unit); itm++) { 735 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, portsp_cntr_mem, itm); 736 SOC_IF_ERROR_RETURN 737 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_chip_port, &entry)); 738 shr_usage = soc_mem_field32_get(unit, portsp_cntr_mem, &entry, 739 egr_portsp_usage_flds[spid]); 740 741 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, drop_mem, itm); 742 SOC_IF_ERROR_RETURN 743 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_chip_port, &entry)); 744 drop_state_fld = soc_mem_field32_get(unit, drop_mem, &entry, 745 egr_uc_portsp_drop_flds[spid]); 746 drop_state = (drop_state_fld >> _TH3_EGR_Q_DROP_STATE_OFFSET_GREEN) & 1; 747 cli_out(" ITM:%1d, Usage: %7d, DropState: %7d\n", 748 itm, shr_usage, drop_state); 749 } 750 751 return SOC_E_NONE; 752 } 753 754 static const soc_field_t egr_sp_drop_flds[_TH3_MMU_NUM_POOL] = {GREEN_SP0f, 755 GREEN_SP1f, GREEN_SP2f, GREEN_SP3f}; 756 757 static int 758 _soc_th3_egr_sp_limit_debug_print(int unit, int spid) { 759 soc_reg_t sp_limit_reg = MMU_THDO_SHARED_DB_POOL_SHARED_LIMITr; 760 soc_reg_t sp_usage_reg = MMU_THDO_SHARED_DB_POOL_SHARED_COUNTr; 761 soc_reg_t sp_resume_limit_reg = MMU_THDO_SHARED_DB_POOL_RESUME_LIMITr; 762 soc_reg_t sp_drop_state_reg = MMU_THDO_SHARED_DB_POOL_DROP_STATESr; 763 uint32 rval = 0; 764 int sp_limit, sp_resume; 765 int itm, usage, drop_state; 766 767 rval = 0; 768 SOC_IF_ERROR_RETURN 769 (soc_reg32_get(unit, sp_limit_reg, spid, 0, &rval)); 770 sp_limit = soc_reg_field_get(unit, sp_limit_reg, rval, SHARED_LIMITf); 771 772 rval = 0; 773 SOC_IF_ERROR_RETURN 774 (soc_reg32_get(unit, sp_resume_limit_reg, spid, 0, &rval)); 775 sp_resume = 776 soc_reg_field_get(unit, sp_resume_limit_reg, rval, RESUME_LIMITf); 777 778 cli_out("ServicePool: %1d: Limit: %7d, ResetLimit: %7d\n", 779 spid, sp_limit, (sp_limit - sp_resume)); 780 781 for (itm = 0; itm < NUM_ITM(unit); itm++) { 782 rval = 0; 783 SOC_IF_ERROR_RETURN 784 (soc_tomahawk3_itm_reg32_get(unit, sp_usage_reg, itm, itm, 785 spid, &rval)); 786 usage = soc_reg_field_get(unit, sp_usage_reg, rval, COUNTf); 787 788 rval = 0; 789 SOC_IF_ERROR_RETURN 790 (soc_tomahawk3_itm_reg32_get(unit, sp_drop_state_reg, itm, itm, 0, 791 &rval)); 792 drop_state = soc_reg_field_get(unit, sp_drop_state_reg, rval, 793 egr_sp_drop_flds[spid]); 794 795 cli_out(" ITM:%1d, Usage: %7d, DropState: %7d\n", 796 itm, usage, drop_state); 797 798 } 799 800 return SOC_E_NONE; 801 } 802 803 804 static int 805 _soc_th3_egr_mc_portsp_limit_debug_print(int unit, int port, int spid) { 806 soc_mem_t portsp_cfg_mem = MMU_THDO_CONFIG_PORTSP_MCm; 807 soc_mem_t resume_mem = MMU_THDO_RESUME_PORT_MC0m; 808 soc_mem_t portsp_cntr_mem = MMU_THDO_COUNTER_PORTSP_MCm; 809 soc_mem_t drop_mem = MMU_THDO_PORT_SP_DROP_STATE_MCm; 810 soc_mem_t read_mem; 811 uint32 entry[SOC_MAX_MEM_WORDS]; 812 int shr_lmt, itm, shr_usage; 813 uint32 mmu_chip_port; 814 int mem_index, resume_lmt, drop_state_fld, drop_state; 815 816 mmu_chip_port = soc_th3_mmu_chip_port_num(unit, port); 817 mem_index = (mmu_chip_port * _TH3_MMU_NUM_POOL) + spid; 818 819 SOC_IF_ERROR_RETURN 820 (soc_mem_read(unit, portsp_cfg_mem, MEM_BLOCK_ALL, mem_index, &entry)); 821 shr_lmt = 822 soc_mem_field32_get(unit, portsp_cfg_mem, &entry, SP_SHARED_LIMITf); 823 SOC_IF_ERROR_RETURN 824 (soc_mem_read(unit, resume_mem, MEM_BLOCK_ALL, mem_index, &entry)); 825 resume_lmt = 826 soc_mem_field32_get(unit, resume_mem, &entry, SHARED_RESUMEf); 827 cli_out("MC PortSP Shared: Limit: %7d, ResetLimit: %7d \n", 828 shr_lmt, (shr_lmt - resume_lmt)); 829 830 for (itm = 0; itm < NUM_ITM(unit); itm++) { 831 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, portsp_cntr_mem, itm); 832 SOC_IF_ERROR_RETURN 833 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mem_index, &entry)); 834 shr_usage = soc_mem_field32_get(unit, portsp_cntr_mem, &entry, 835 SHARED_COUNTf); 836 837 read_mem = SOC_MEM_UNIQUE_ACC_ITM(unit, drop_mem, itm); 838 SOC_IF_ERROR_RETURN 839 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_chip_port, &entry)); 840 drop_state_fld = soc_mem_field32_get(unit, drop_mem, &entry, 841 egr_uc_portsp_drop_flds[spid]); 842 drop_state = (drop_state_fld >> _TH3_EGR_Q_DROP_STATE_OFFSET_GREEN) & 1; 843 cli_out(" ITM:%1d, Usage: %7d, DropState: %7d\n", 844 itm, shr_usage, drop_state); 845 } 846 847 return SOC_E_NONE; 848 } 849 850 static int 851 _soc_th3_egr_mc_sp_limit_debug_print(int unit, int spid) { 852 soc_reg_t sp_limit_reg = MMU_THDO_MC_SHARED_CQE_POOL_SHARED_LIMITr; 853 soc_reg_t sp_usage_reg = MMU_THDO_MC_SHARED_CQE_POOL_SHARED_COUNTr; 854 soc_reg_t sp_resume_limit_reg = MMU_THDO_MC_SHARED_CQE_POOL_RESUME_LIMITr; 855 soc_reg_t sp_drop_state_reg = MMU_THDO_MC_SHARED_CQE_POOL_DROP_STATESr; 856 uint32 rval = 0; 857 int sp_limit, sp_resume; 858 int itm, usage, drop_state; 859 860 rval = 0; 861 SOC_IF_ERROR_RETURN 862 (soc_reg32_get(unit, sp_limit_reg, spid, 0, &rval)); 863 sp_limit = soc_reg_field_get(unit, sp_limit_reg, rval, SHARED_LIMITf); 864 865 rval = 0; 866 SOC_IF_ERROR_RETURN 867 (soc_reg32_get(unit, sp_resume_limit_reg, spid, 0, &rval)); 868 sp_resume = 869 soc_reg_field_get(unit, sp_resume_limit_reg, rval, RESUME_LIMITf); 870 871 cli_out("MC ServicePool: %1d: Limit: %7d, ResetLimit: %7d\n", 872 spid, sp_limit, (sp_limit - sp_resume)); 873 874 for (itm = 0; itm < NUM_ITM(unit); itm++) { 875 rval = 0; 876 SOC_IF_ERROR_RETURN 877 (soc_tomahawk3_itm_reg32_get(unit, sp_usage_reg, itm, itm, spid, 878 &rval)); 879 usage = soc_reg_field_get(unit, sp_usage_reg, rval, COUNTf); 880 881 rval = 0; 882 SOC_IF_ERROR_RETURN 883 (soc_tomahawk3_itm_reg32_get(unit, sp_drop_state_reg, itm, itm, 0, 884 &rval)); 885 drop_state = soc_reg_field_get(unit, sp_drop_state_reg, rval, 886 egr_sp_drop_flds[spid]); 887 888 cli_out(" ITM:%1d, Usage: %7d, DropState: %7d\n", 889 itm, usage, drop_state); 890 891 } 892 893 return SOC_E_NONE; 894 } 895 896 897 static int 898 _soc_th3_egr_queue_debug_print(int unit, int port, int queue) { 899 int uc_mc = 0, qgrp_en, spid, num_ucq, voq; 900 soc_mem_t q_cfg_mem = MMU_THDO_Q_TO_QGRP_MAPD0m; 901 uint32 entry[SOC_MAX_MEM_WORDS]; 902 int qgrp_vld, use_qgrp_min; 903 soc_info_t *si; 904 905 si = &SOC_INFO(unit); 906 num_ucq = _soc_th3_get_num_ucq(unit); 907 if (IS_CPU_PORT(unit, port)) { 908 if (queue >= SOC_TH3_NUM_CPU_QUEUES) { 909 return SOC_E_PARAM; 910 } 911 /* CPU only has MC queues */ 912 uc_mc = 1; 913 voq = si->port_cosq_base[port] + queue; 914 } else { 915 if (queue >= SOC_TH3_NUM_GP_QUEUES) { 916 return SOC_E_PARAM; 917 } 918 /* Lower queues are UC, upper queues are MC */ 919 if (queue >= num_ucq) { 920 uc_mc = 1; 921 } 922 voq = si->port_uc_cosq_base[port] + queue; 923 } 924 if (uc_mc) { 925 /* Print for MC queues */ 926 if (!IS_CPU_PORT(unit, port)) { 927 cli_out("### Egress Buffer Usage Debug Info for Port: %d, Queue: %d " 928 " MC Cos: %d ###\n", port, queue, (queue - num_ucq)); 929 } else { 930 cli_out("### Egress Buffer Usage Debug Info for Port: %d, Queue: %d " 931 " MC Cos: %d ###\n", port, queue, queue); 932 } 933 } else { 934 /* Print for UC queues */ 935 cli_out("### Egress Buffer Usage Debug Info for Port: %d, Queue: %d " 936 " UC Cos: %d ###\n", port, queue, queue); 937 } 938 939 /* Queue basic config */ 940 SOC_IF_ERROR_RETURN 941 (soc_mem_read(unit, q_cfg_mem, MEM_BLOCK_ALL, voq, &entry)); 942 spid = soc_mem_field32_get(unit, q_cfg_mem, &entry, SPIDf); 943 qgrp_vld = soc_mem_field32_get(unit, q_cfg_mem, &entry, QGROUP_VALIDf); 944 use_qgrp_min = soc_mem_field32_get(unit, q_cfg_mem, &entry, 945 USE_QGROUP_MINf); 946 qgrp_en = (qgrp_vld & use_qgrp_min); 947 948 if (!IS_CPU_PORT(unit, port)) { 949 SOC_IF_ERROR_RETURN 950 (_soc_th3_port_queue_limit_debug_print(unit, port, queue)); 951 } else { 952 SOC_IF_ERROR_RETURN 953 (_soc_th3_cpu_queue_debug_print(unit, port, queue)); 954 } 955 SOC_IF_ERROR_RETURN 956 (_soc_th3_port_qgroup_limit_debug_print(unit, port, uc_mc, qgrp_en)); 957 SOC_IF_ERROR_RETURN 958 (_soc_th3_egr_portsp_limit_debug_print(unit, port, spid)); 959 SOC_IF_ERROR_RETURN 960 (_soc_th3_egr_sp_limit_debug_print(unit, spid)); 961 962 if (uc_mc) { 963 SOC_IF_ERROR_RETURN 964 (_soc_th3_egr_mc_portsp_limit_debug_print(unit, port, spid)); 965 SOC_IF_ERROR_RETURN 966 (_soc_th3_egr_mc_sp_limit_debug_print(unit, spid)); 967 } 968 969 return SOC_E_NONE; 970 } 971 972 static const soc_reg_t obm_thresh_pp[_TH3_PIPES_PER_DEV][_TH3_PBLKS_PER_PIPE][2] = 973 { 974 {{IDB_OBM0_THRESHOLD_PIPE0r, IDB_OBM0_THRESHOLD_1_PIPE0r}, 975 {IDB_OBM1_THRESHOLD_PIPE0r, IDB_OBM1_THRESHOLD_1_PIPE0r}, 976 {IDB_OBM2_THRESHOLD_PIPE0r, IDB_OBM2_THRESHOLD_1_PIPE0r}, 977 {IDB_OBM3_THRESHOLD_PIPE0r, IDB_OBM3_THRESHOLD_1_PIPE0r}}, 978 {{IDB_OBM0_THRESHOLD_PIPE1r, IDB_OBM0_THRESHOLD_1_PIPE1r}, 979 {IDB_OBM1_THRESHOLD_PIPE1r, IDB_OBM1_THRESHOLD_1_PIPE1r}, 980 {IDB_OBM2_THRESHOLD_PIPE1r, IDB_OBM2_THRESHOLD_1_PIPE1r}, 981 {IDB_OBM3_THRESHOLD_PIPE1r, IDB_OBM3_THRESHOLD_1_PIPE1r}}, 982 {{IDB_OBM0_THRESHOLD_PIPE2r, IDB_OBM0_THRESHOLD_1_PIPE2r}, 983 {IDB_OBM1_THRESHOLD_PIPE2r, IDB_OBM1_THRESHOLD_1_PIPE2r}, 984 {IDB_OBM2_THRESHOLD_PIPE2r, IDB_OBM2_THRESHOLD_1_PIPE2r}, 985 {IDB_OBM3_THRESHOLD_PIPE2r, IDB_OBM3_THRESHOLD_1_PIPE2r}}, 986 {{IDB_OBM0_THRESHOLD_PIPE3r, IDB_OBM0_THRESHOLD_1_PIPE3r}, 987 {IDB_OBM1_THRESHOLD_PIPE3r, IDB_OBM1_THRESHOLD_1_PIPE3r}, 988 {IDB_OBM2_THRESHOLD_PIPE3r, IDB_OBM2_THRESHOLD_1_PIPE3r}, 989 {IDB_OBM3_THRESHOLD_PIPE3r, IDB_OBM3_THRESHOLD_1_PIPE3r}}, 990 {{IDB_OBM0_THRESHOLD_PIPE4r, IDB_OBM0_THRESHOLD_1_PIPE4r}, 991 {IDB_OBM1_THRESHOLD_PIPE4r, IDB_OBM1_THRESHOLD_1_PIPE4r}, 992 {IDB_OBM2_THRESHOLD_PIPE4r, IDB_OBM2_THRESHOLD_1_PIPE4r}, 993 {IDB_OBM3_THRESHOLD_PIPE4r, IDB_OBM3_THRESHOLD_1_PIPE4r}}, 994 {{IDB_OBM0_THRESHOLD_PIPE5r, IDB_OBM0_THRESHOLD_1_PIPE5r}, 995 {IDB_OBM1_THRESHOLD_PIPE5r, IDB_OBM1_THRESHOLD_1_PIPE5r}, 996 {IDB_OBM2_THRESHOLD_PIPE5r, IDB_OBM2_THRESHOLD_1_PIPE5r}, 997 {IDB_OBM3_THRESHOLD_PIPE5r, IDB_OBM3_THRESHOLD_1_PIPE5r}}, 998 {{IDB_OBM0_THRESHOLD_PIPE6r, IDB_OBM0_THRESHOLD_1_PIPE6r}, 999 {IDB_OBM1_THRESHOLD_PIPE6r, IDB_OBM1_THRESHOLD_1_PIPE6r}, 1000 {IDB_OBM2_THRESHOLD_PIPE6r, IDB_OBM2_THRESHOLD_1_PIPE6r}, 1001 {IDB_OBM3_THRESHOLD_PIPE6r, IDB_OBM3_THRESHOLD_1_PIPE6r}}, 1002 {{IDB_OBM0_THRESHOLD_PIPE7r, IDB_OBM0_THRESHOLD_1_PIPE7r}, 1003 {IDB_OBM1_THRESHOLD_PIPE7r, IDB_OBM1_THRESHOLD_1_PIPE7r}, 1004 {IDB_OBM2_THRESHOLD_PIPE7r, IDB_OBM2_THRESHOLD_1_PIPE7r}, 1005 {IDB_OBM3_THRESHOLD_PIPE7r, IDB_OBM3_THRESHOLD_1_PIPE7r}} 1006 }; 1007 1008 static const soc_reg_t obm_usage_pp[_TH3_PIPES_PER_DEV][_TH3_PBLKS_PER_PIPE][2] = 1009 { 1010 {{IDB_OBM0_USAGE_PIPE0r, IDB_OBM0_USAGE_1_PIPE0r}, 1011 {IDB_OBM1_USAGE_PIPE0r, IDB_OBM1_USAGE_1_PIPE0r}, 1012 {IDB_OBM2_USAGE_PIPE0r, IDB_OBM2_USAGE_1_PIPE0r}, 1013 {IDB_OBM3_USAGE_PIPE0r, IDB_OBM3_USAGE_1_PIPE0r}}, 1014 {{IDB_OBM0_USAGE_PIPE1r, IDB_OBM0_USAGE_1_PIPE1r}, 1015 {IDB_OBM1_USAGE_PIPE1r, IDB_OBM1_USAGE_1_PIPE1r}, 1016 {IDB_OBM2_USAGE_PIPE1r, IDB_OBM2_USAGE_1_PIPE1r}, 1017 {IDB_OBM3_USAGE_PIPE1r, IDB_OBM3_USAGE_1_PIPE1r}}, 1018 {{IDB_OBM0_USAGE_PIPE2r, IDB_OBM0_USAGE_1_PIPE2r}, 1019 {IDB_OBM1_USAGE_PIPE2r, IDB_OBM1_USAGE_1_PIPE2r}, 1020 {IDB_OBM2_USAGE_PIPE2r, IDB_OBM2_USAGE_1_PIPE2r}, 1021 {IDB_OBM3_USAGE_PIPE2r, IDB_OBM3_USAGE_1_PIPE2r}}, 1022 {{IDB_OBM0_USAGE_PIPE3r, IDB_OBM0_USAGE_1_PIPE3r}, 1023 {IDB_OBM1_USAGE_PIPE3r, IDB_OBM1_USAGE_1_PIPE3r}, 1024 {IDB_OBM2_USAGE_PIPE3r, IDB_OBM2_USAGE_1_PIPE3r}, 1025 {IDB_OBM3_USAGE_PIPE3r, IDB_OBM3_USAGE_1_PIPE3r}}, 1026 {{IDB_OBM0_USAGE_PIPE4r, IDB_OBM0_USAGE_1_PIPE4r}, 1027 {IDB_OBM1_USAGE_PIPE4r, IDB_OBM1_USAGE_1_PIPE4r}, 1028 {IDB_OBM2_USAGE_PIPE4r, IDB_OBM2_USAGE_1_PIPE4r}, 1029 {IDB_OBM3_USAGE_PIPE4r, IDB_OBM3_USAGE_1_PIPE4r}}, 1030 {{IDB_OBM0_USAGE_PIPE5r, IDB_OBM0_USAGE_1_PIPE5r}, 1031 {IDB_OBM1_USAGE_PIPE5r, IDB_OBM1_USAGE_1_PIPE5r}, 1032 {IDB_OBM2_USAGE_PIPE5r, IDB_OBM2_USAGE_1_PIPE5r}, 1033 {IDB_OBM3_USAGE_PIPE5r, IDB_OBM3_USAGE_1_PIPE5r}}, 1034 {{IDB_OBM0_USAGE_PIPE6r, IDB_OBM0_USAGE_1_PIPE6r}, 1035 {IDB_OBM1_USAGE_PIPE6r, IDB_OBM1_USAGE_1_PIPE6r}, 1036 {IDB_OBM2_USAGE_PIPE6r, IDB_OBM2_USAGE_1_PIPE6r}, 1037 {IDB_OBM3_USAGE_PIPE6r, IDB_OBM3_USAGE_1_PIPE6r}}, 1038 {{IDB_OBM0_USAGE_PIPE7r, IDB_OBM0_USAGE_1_PIPE7r}, 1039 {IDB_OBM1_USAGE_PIPE7r, IDB_OBM1_USAGE_1_PIPE7r}, 1040 {IDB_OBM2_USAGE_PIPE7r, IDB_OBM2_USAGE_1_PIPE7r}, 1041 {IDB_OBM3_USAGE_PIPE7r, IDB_OBM3_USAGE_1_PIPE7r}} 1042 }; 1043 1044 static const soc_reg_t 1045 obm_fc_thresh_pp[_TH3_PIPES_PER_DEV][_TH3_PBLKS_PER_PIPE][2] = 1046 { 1047 {{IDB_OBM0_FC_THRESHOLD_PIPE0r, IDB_OBM0_FC_THRESHOLD_1_PIPE0r}, 1048 {IDB_OBM1_FC_THRESHOLD_PIPE0r, IDB_OBM1_FC_THRESHOLD_1_PIPE0r}, 1049 {IDB_OBM2_FC_THRESHOLD_PIPE0r, IDB_OBM2_FC_THRESHOLD_1_PIPE0r}, 1050 {IDB_OBM3_FC_THRESHOLD_PIPE0r, IDB_OBM3_FC_THRESHOLD_1_PIPE0r}}, 1051 {{IDB_OBM0_FC_THRESHOLD_PIPE1r, IDB_OBM0_FC_THRESHOLD_1_PIPE1r}, 1052 {IDB_OBM1_FC_THRESHOLD_PIPE1r, IDB_OBM1_FC_THRESHOLD_1_PIPE1r}, 1053 {IDB_OBM2_FC_THRESHOLD_PIPE1r, IDB_OBM2_FC_THRESHOLD_1_PIPE1r}, 1054 {IDB_OBM3_FC_THRESHOLD_PIPE1r, IDB_OBM3_FC_THRESHOLD_1_PIPE1r}}, 1055 {{IDB_OBM0_FC_THRESHOLD_PIPE2r, IDB_OBM0_FC_THRESHOLD_1_PIPE2r}, 1056 {IDB_OBM1_FC_THRESHOLD_PIPE2r, IDB_OBM1_FC_THRESHOLD_1_PIPE2r}, 1057 {IDB_OBM2_FC_THRESHOLD_PIPE2r, IDB_OBM2_FC_THRESHOLD_1_PIPE2r}, 1058 {IDB_OBM3_FC_THRESHOLD_PIPE2r, IDB_OBM3_FC_THRESHOLD_1_PIPE2r}}, 1059 {{IDB_OBM0_FC_THRESHOLD_PIPE3r, IDB_OBM0_FC_THRESHOLD_1_PIPE3r}, 1060 {IDB_OBM1_FC_THRESHOLD_PIPE3r, IDB_OBM1_FC_THRESHOLD_1_PIPE3r}, 1061 {IDB_OBM2_FC_THRESHOLD_PIPE3r, IDB_OBM2_FC_THRESHOLD_1_PIPE3r}, 1062 {IDB_OBM3_FC_THRESHOLD_PIPE3r, IDB_OBM3_FC_THRESHOLD_1_PIPE3r}}, 1063 {{IDB_OBM0_FC_THRESHOLD_PIPE4r, IDB_OBM0_FC_THRESHOLD_1_PIPE4r}, 1064 {IDB_OBM1_FC_THRESHOLD_PIPE4r, IDB_OBM1_FC_THRESHOLD_1_PIPE4r}, 1065 {IDB_OBM2_FC_THRESHOLD_PIPE4r, IDB_OBM2_FC_THRESHOLD_1_PIPE4r}, 1066 {IDB_OBM3_FC_THRESHOLD_PIPE4r, IDB_OBM3_FC_THRESHOLD_1_PIPE4r}}, 1067 {{IDB_OBM0_FC_THRESHOLD_PIPE5r, IDB_OBM0_FC_THRESHOLD_1_PIPE5r}, 1068 {IDB_OBM1_FC_THRESHOLD_PIPE5r, IDB_OBM1_FC_THRESHOLD_1_PIPE5r}, 1069 {IDB_OBM2_FC_THRESHOLD_PIPE5r, IDB_OBM2_FC_THRESHOLD_1_PIPE5r}, 1070 {IDB_OBM3_FC_THRESHOLD_PIPE5r, IDB_OBM3_FC_THRESHOLD_1_PIPE5r}}, 1071 {{IDB_OBM0_FC_THRESHOLD_PIPE6r, IDB_OBM0_FC_THRESHOLD_1_PIPE6r}, 1072 {IDB_OBM1_FC_THRESHOLD_PIPE6r, IDB_OBM1_FC_THRESHOLD_1_PIPE6r}, 1073 {IDB_OBM2_FC_THRESHOLD_PIPE6r, IDB_OBM2_FC_THRESHOLD_1_PIPE6r}, 1074 {IDB_OBM3_FC_THRESHOLD_PIPE6r, IDB_OBM3_FC_THRESHOLD_1_PIPE6r}}, 1075 {{IDB_OBM0_FC_THRESHOLD_PIPE7r, IDB_OBM0_FC_THRESHOLD_1_PIPE7r}, 1076 {IDB_OBM1_FC_THRESHOLD_PIPE7r, IDB_OBM1_FC_THRESHOLD_1_PIPE7r}, 1077 {IDB_OBM2_FC_THRESHOLD_PIPE7r, IDB_OBM2_FC_THRESHOLD_1_PIPE7r}, 1078 {IDB_OBM3_FC_THRESHOLD_PIPE7r, IDB_OBM3_FC_THRESHOLD_1_PIPE7r}} 1079 }; 1080 1081 static const soc_reg_t obm_fc_en_regs[_TH3_PBLKS_PER_PIPE] = 1082 {IDB_OBM0_FLOW_CONTROL_CONFIGr, IDB_OBM1_FLOW_CONTROL_CONFIGr, 1083 IDB_OBM2_FLOW_CONTROL_CONFIGr, IDB_OBM3_FLOW_CONTROL_CONFIGr}; 1084 1085 static int 1086 _soc_th3_obm_debug_print(int unit, int port) { 1087 soc_info_t *si; 1088 int phy_port, pipe, pm, subp; 1089 uint64 rval64; 1090 soc_reg_t reg; 1091 uint32 limit, usage, pri_bmp, xoff, xon, fc_en, pfc; 1092 1093 si = &SOC_INFO(unit); 1094 phy_port = si->port_l2p_mapping[port]; 1095 pipe = si->port_pipe[port]; 1096 pm = soc_tomahawk3_get_pipe_pm_from_phy_port(phy_port); 1097 subp = soc_tomahawk3_get_subp_from_phy_port(phy_port); 1098 1099 cli_out("######### OBM Limits(Bytes) for Port: %d #########\n", port); 1100 1101 /* Port FC enable */ 1102 reg = obm_fc_en_regs[pm]; 1103 COMPILER_64_SET(rval64, 0, 0); 1104 SOC_IF_ERROR_RETURN 1105 (soc_reg_get(unit, reg, pipe, subp, &rval64)); 1106 fc_en = soc_reg64_field32_get(unit, reg, rval64, PORT_FC_ENf); 1107 pfc = soc_reg64_field32_get(unit, reg, rval64, FC_TYPEf); 1108 if (pfc) { 1109 cli_out(" Port FC Enable: %7d Mode: PFC \n", fc_en); 1110 } else { 1111 cli_out(" Port FC Enable: %7d Mode: Pause \n", fc_en); 1112 } 1113 1114 /* Port Xoff, Xon */ 1115 reg = obm_fc_thresh_pp[pipe][pm][1]; 1116 COMPILER_64_SET(rval64, 0, 0); 1117 SOC_IF_ERROR_RETURN 1118 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1119 xoff = soc_reg64_field32_get(unit, reg, rval64, PORT_XOFFf) * 1120 _TH3_IDB_THD_GRAN; 1121 xon = soc_reg64_field32_get(unit, reg, rval64, PORT_XONf) * 1122 _TH3_IDB_THD_GRAN; 1123 cli_out(" Xoff Limit: %7d Xon Limit: %7d \n", xoff, xon); 1124 1125 /* Port discard limit */ 1126 reg = obm_thresh_pp[pipe][pm][1]; 1127 COMPILER_64_SET(rval64, 0, 0); 1128 SOC_IF_ERROR_RETURN 1129 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1130 limit = soc_reg64_field32_get(unit, reg, rval64, DISCARD_LIMITf) * 1131 _TH3_IDB_THD_GRAN; 1132 cli_out(" Discard Limit: %7d \n", limit); 1133 1134 /* Port current usage */ 1135 reg = obm_usage_pp[pipe][pm][1]; 1136 COMPILER_64_SET(rval64, 0, 0); 1137 SOC_IF_ERROR_RETURN 1138 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1139 usage = soc_reg64_field32_get(unit, reg, rval64, TOTAL_COUNTf); 1140 cli_out(" Total Usage: %7d \n", usage); 1141 1142 /* Lossless 0 */ 1143 reg = obm_fc_en_regs[pm]; 1144 COMPILER_64_SET(rval64, 0, 0); 1145 SOC_IF_ERROR_RETURN 1146 (soc_reg_get(unit, reg, pipe, subp, &rval64)); 1147 fc_en = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS0_FC_ENf); 1148 if (!pfc) { 1149 cli_out(" Lossless0 FC Enable: %7d \n", fc_en); 1150 } else { 1151 pri_bmp = soc_reg64_field32_get(unit, reg, rval64, 1152 LOSSLESS0_PRIORITY_PROFILEf); 1153 cli_out(" Lossless0 FC Enable: %7d Pri_bmp: %7x \n", fc_en, 1154 pri_bmp); 1155 } 1156 1157 reg = obm_fc_thresh_pp[pipe][pm][0]; 1158 COMPILER_64_SET(rval64, 0, 0); 1159 SOC_IF_ERROR_RETURN 1160 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1161 xoff = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS0_XOFFf) * 1162 _TH3_IDB_THD_GRAN; 1163 xon = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS0_XONf) * 1164 _TH3_IDB_THD_GRAN; 1165 cli_out(" Xoff Limit: %7d Xon Limit: %7d \n", xoff, xon); 1166 1167 reg = obm_thresh_pp[pipe][pm][0]; 1168 COMPILER_64_SET(rval64, 0, 0); 1169 SOC_IF_ERROR_RETURN 1170 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1171 limit = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS0_DISCARDf) * 1172 _TH3_IDB_THD_GRAN; 1173 cli_out(" Discard Limit: %7d \n", limit); 1174 1175 reg = obm_usage_pp[pipe][pm][0]; 1176 COMPILER_64_SET(rval64, 0, 0); 1177 SOC_IF_ERROR_RETURN 1178 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1179 usage = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS0_COUNTf); 1180 cli_out(" Usage: %7d \n", usage); 1181 1182 /* Lossless 1 */ 1183 reg = obm_fc_en_regs[pm]; 1184 COMPILER_64_SET(rval64, 0, 0); 1185 SOC_IF_ERROR_RETURN 1186 (soc_reg_get(unit, reg, pipe, subp, &rval64)); 1187 fc_en = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS1_FC_ENf); 1188 if (!pfc) { 1189 cli_out(" Lossless1 FC Enable: %7d \n", fc_en); 1190 } else { 1191 pri_bmp = soc_reg64_field32_get(unit, reg, rval64, 1192 LOSSLESS1_PRIORITY_PROFILEf); 1193 cli_out(" Lossless1 FC Enable: %7d Pri_bmp: %7x \n", fc_en, 1194 pri_bmp); 1195 } 1196 reg = obm_fc_thresh_pp[pipe][pm][0]; 1197 COMPILER_64_SET(rval64, 0, 0); 1198 SOC_IF_ERROR_RETURN 1199 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1200 xoff = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS1_XOFFf) * 1201 _TH3_IDB_THD_GRAN; 1202 xon = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS1_XONf) * 1203 _TH3_IDB_THD_GRAN; 1204 cli_out(" Xoff Limit: %7d Xon Limit: %7d \n", xoff, xon); 1205 1206 reg = obm_thresh_pp[pipe][pm][1]; 1207 COMPILER_64_SET(rval64, 0, 0); 1208 SOC_IF_ERROR_RETURN 1209 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1210 limit = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS1_DISCARDf) * 1211 _TH3_IDB_THD_GRAN; 1212 cli_out(" Discard Limit: %7d \n", limit); 1213 1214 reg = obm_usage_pp[pipe][pm][1]; 1215 COMPILER_64_SET(rval64, 0, 0); 1216 SOC_IF_ERROR_RETURN 1217 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1218 usage = soc_reg64_field32_get(unit, reg, rval64, LOSSLESS1_COUNTf); 1219 cli_out(" Usage: %7d \n", usage); 1220 1221 1222 /* Lossy High */ 1223 reg = obm_thresh_pp[pipe][pm][0]; 1224 COMPILER_64_SET(rval64, 0, 0); 1225 SOC_IF_ERROR_RETURN 1226 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1227 limit = soc_reg64_field32_get(unit, reg, rval64, LOSSY_DISCARDf) * 1228 _TH3_IDB_THD_GRAN; 1229 cli_out(" Lossy Hi Discard Limit: %7d \n", limit); 1230 1231 reg = obm_thresh_pp[pipe][pm][0]; 1232 COMPILER_64_SET(rval64, 0, 0); 1233 SOC_IF_ERROR_RETURN 1234 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1235 limit = soc_reg64_field32_get(unit, reg, rval64, LOSSY_LOW_PRIf) * 1236 _TH3_IDB_THD_GRAN; 1237 cli_out(" Lossy Lo Discard Limit: %7d \n", limit); 1238 1239 /* Lossy current usage */ 1240 reg = obm_usage_pp[pipe][pm][0]; 1241 COMPILER_64_SET(rval64, 0, 0); 1242 SOC_IF_ERROR_RETURN 1243 (soc_reg_get(unit, reg, REG_PORT_ANY, subp, &rval64)); 1244 usage = soc_reg64_field32_get(unit, reg, rval64, LOSSY_COUNTf); 1245 cli_out(" Lossy Usage: %7d \n", usage); 1246 1247 1248 return SOC_E_NONE; 1249 } 1250 1251 static int 1252 _soc_th3_get_bw_from_ref_gran(int unit, uint32 refresh, int gran, int mode, 1253 uint32 *bw) { 1254 1255 /* Byte shaping granularity in Kbps*/ 1256 static const uint32 byte_gran[_TH3_NUM_MTR_GRAN] = {32, 64, 128, 256, 512, 1257 1024, 2048, 4096}; 1258 /* Packet shaping granularity in pps*/ 1259 static const uint32 pkt_gran[_TH3_NUM_MTR_GRAN] = {2, 4, 8, 32, 128, 512, 1260 2048, 8192}; 1261 1262 if (refresh == 0) { 1263 *bw = 0; 1264 return SOC_E_NONE; 1265 } 1266 if (mode) { 1267 /*Packet shaping*/ 1268 *bw = refresh * pkt_gran[gran]; 1269 } else { 1270 /* Byte shaping */ 1271 *bw = refresh * byte_gran[gran]; 1272 } 1273 return SOC_E_NONE; 1274 } 1275 1276 static int 1277 _soc_th3_fp_l0_bw_print(int unit, int port, int l0) { 1278 soc_info_t *si = &SOC_INFO(unit); 1279 int pipe, mmu_local_port; 1280 soc_mem_t mem; 1281 uint32 entry[SOC_MAX_MEM_WORDS]; 1282 uint32 refresh, bw; 1283 int gran, mode, oop; 1284 int l0_index; 1285 1286 pipe = si->port_pipe[port]; 1287 mmu_local_port = si->port_l2i_mapping[port]; 1288 l0_index = (mmu_local_port * SOC_TH3_NUM_GP_QUEUES) + l0; 1289 1290 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_L0_Am, pipe); 1291 SOC_IF_ERROR_RETURN 1292 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l0_index, &entry)); 1293 refresh = soc_mem_field32_get(unit, mem, &entry, MAX_REFRESHf); 1294 mode = soc_mem_field32_get(unit, mem, &entry, PACKET_SHAPINGf); 1295 gran = soc_mem_field32_get(unit, mem, &entry, MAX_METER_GRANf); 1296 SOC_IF_ERROR_RETURN 1297 (_soc_th3_get_bw_from_ref_gran(unit, refresh, gran, mode, &bw)); 1298 1299 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_BUCKET_L0m, pipe); 1300 SOC_IF_ERROR_RETURN 1301 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l0_index, &entry)); 1302 oop = soc_mem_field32_get(unit, mem, &entry, MAX_PROFILE_EXCEEDED_FLAGf); 1303 1304 if (!mode) { 1305 cli_out(" Max Bw: %u Kbps Max Exceeded: %d\n", 1306 bw, oop); 1307 } else { 1308 cli_out(" Max Bw: %u pps Max Exceeded: %d\n", 1309 bw, oop); 1310 } 1311 1312 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_L0_Am, pipe); 1313 SOC_IF_ERROR_RETURN 1314 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l0_index, &entry)); 1315 refresh = soc_mem_field32_get(unit, mem, &entry, MIN_REFRESHf); 1316 mode = soc_mem_field32_get(unit, mem, &entry, PACKET_SHAPINGf); 1317 gran = soc_mem_field32_get(unit, mem, &entry, MIN_METER_GRANf); 1318 SOC_IF_ERROR_RETURN 1319 (_soc_th3_get_bw_from_ref_gran(unit, refresh, gran, mode, &bw)); 1320 1321 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_BUCKET_L0m, pipe); 1322 SOC_IF_ERROR_RETURN 1323 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l0_index, &entry)); 1324 oop = soc_mem_field32_get(unit, mem, &entry, MIN_PROFILE_SATISFIED_FLAGf); 1325 1326 if (!mode) { 1327 cli_out(" Min Bw: %u Kbps Min Satisfied: %d\n", 1328 bw, oop); 1329 } else { 1330 cli_out(" Min Bw: %u pps Min Satisfied: %d\n", 1331 bw, oop); 1332 } 1333 1334 1335 return SOC_E_NONE; 1336 } 1337 1338 1339 static const soc_field_t schq_flds[SOC_TH3_NUM_GP_QUEUES] = {SCH_Q_NUM_0f, 1340 SCH_Q_NUM_1f, SCH_Q_NUM_2f, SCH_Q_NUM_3f, SCH_Q_NUM_4f, SCH_Q_NUM_5f, 1341 SCH_Q_NUM_6f, SCH_Q_NUM_7f, SCH_Q_NUM_8f, SCH_Q_NUM_9f, SCH_Q_NUM_10f, 1342 SCH_Q_NUM_11f}; 1343 1344 static int 1345 _soc_th3_queue_sched_shap_print(int unit, int port, int queue) { 1346 soc_info_t *si = &SOC_INFO(unit); 1347 int num_ucq; 1348 int l1_node, l1_weight; 1349 int l0_node, l0_weight; 1350 int l0_index, l1_index; 1351 soc_reg_t reg; 1352 uint64 rval64; 1353 uint32 l1_l0_map, rval; 1354 int q_profile, l1_l0_mux; 1355 soc_mem_t mem; 1356 uint32 entry[SOC_MAX_MEM_WORDS]; 1357 int pipe, mmu_local_port; 1358 1359 if (IS_CPU_PORT(unit, port)) { 1360 return SOC_E_PARAM; 1361 } 1362 num_ucq = _soc_th3_get_num_ucq(unit); 1363 pipe = si->port_pipe[port]; 1364 mmu_local_port = si->port_l2i_mapping[port]; 1365 if (queue >= num_ucq) { 1366 /* MC queue */ 1367 cli_out ("Queue: %2d, MC queue \n", queue); 1368 } else { 1369 /*UC Queue */ 1370 cli_out ("Queue: %2d, UC queue \n", queue); 1371 } 1372 1373 reg = MMU_PORT_MMUQ_SCHQ_CFGr; 1374 rval = 0; 1375 SOC_IF_ERROR_RETURN 1376 (soc_reg32_get(unit, reg, port, 0, &rval)); 1377 q_profile = soc_reg_field_get(unit, reg, rval, Q_PROFILE_SELf); 1378 1379 reg = MMU_MTRO_MMUQ_SCHQ_PROFILEr; 1380 COMPILER_64_SET(rval64, 0, 0); 1381 SOC_IF_ERROR_RETURN 1382 (soc_reg_get(unit, reg, REG_PORT_ANY, q_profile, &rval64)); 1383 l1_node = soc_reg64_field32_get(unit, reg, rval64, schq_flds[queue]); 1384 1385 l1_index = (mmu_local_port * SOC_TH3_NUM_GP_QUEUES) + l1_node; 1386 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_QSCH_L1_WEIGHT_MEMm, pipe); 1387 SOC_IF_ERROR_RETURN 1388 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l1_index, &entry)); 1389 l1_weight = soc_mem_field32_get(unit, mem, &entry, WEIGHTf); 1390 1391 cli_out(" L1: %2d Weight: %d\n", l1_node, l1_weight); 1392 1393 1394 /* 1395 * bit0 specifies the L0 node that the L1 node 0 is mapped to 1396 => 0: maps to L0 node 0; 1: maps to L0 node 1. 1397 * bit1 specifies the L0 node that the L1 node 1 is mapped to 1398 => 0: maps to L0 node 1; 1: maps to L0 node 2. 1399 * bit2 specifies the L0 node that the L1 node 2 is mapped to 1400 => 0: maps to L0 node 2; 1: maps to L0 node 3. 1401 * bit3 specifies the L0 node that the L1 node 3 is mapped to 1402 => 0: maps to L0 node 3; 1: maps to L0 node 4. 1403 * bit4 specifies the L0 node that the L1 node 4 is mapped to 1404 => 0: maps to L0 node 4; 1: maps to L0 node 5. 1405 * bit5 specifies the L0 node that the L1 node 5 is mapped to 1406 => 0: maps to L0 node 5; 1: maps to L0 node 6. 1407 * bit6 specifies the L0 node that the L1 node 6 is mapped to 1408 => 0: maps to L0 node 6; 1: maps to L0 node 7. 1409 * bit7 specifies the L0 node that the L1 node 7 is mapped to 1410 => 0: maps to L0 node 7; 1: maps to L0 node 8. 1411 * bit8 specifies the L0 node that the L1 node 8 is mapped to 1412 => 0: maps to L0 node 8; 1: maps to L0 node 9. 1413 * bit9 specifies the L0 node that the L1 node 9 is mapped to 1414 => 0: maps to L0 node 9; 1: maps to L0 node 10. 1415 * bit10 specifies the L0 node that the L1 node 10 is mapped to 1416 => 0: maps to L0 node 10; 1: maps to L0 node 11. 1417 * bit11 specifies the L0 node that the L1 node 11 is mapped to 1418 => 0: maps to L0 node 11; 1: maps to L0 node 11. 1419 * Note that L1 node 11 always maps to L0 node 11. 1420 */ 1421 1422 reg = MMU_QSCH_PORT_CONFIGr; 1423 COMPILER_64_SET(rval64, 0, 0); 1424 SOC_IF_ERROR_RETURN 1425 (soc_reg_get(unit, reg, port, 0, &rval64)); 1426 l1_l0_map = soc_reg64_field32_get(unit, reg, rval64, L1_TO_L0_MAPPINGf); 1427 l1_l0_mux = (l1_l0_map >> l1_node) & 1; 1428 if (l1_node == 11) { 1429 l0_node = 11; 1430 } else { 1431 if (l1_l0_mux) { 1432 l0_node = l1_node + 1; 1433 } else { 1434 l0_node = l1_node; 1435 } 1436 } 1437 1438 l0_index = (mmu_local_port * SOC_TH3_NUM_GP_QUEUES) + l0_node; 1439 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_QSCH_L0_WEIGHT_MEMm, pipe); 1440 SOC_IF_ERROR_RETURN 1441 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l0_index, &entry)); 1442 l0_weight = soc_mem_field32_get(unit, mem, &entry, WEIGHTf); 1443 cli_out(" L0: %d Weight: %d\n", l0_node, l0_weight); 1444 1445 SOC_IF_ERROR_RETURN(_soc_th3_fp_l0_bw_print(unit, port, l0_node)); 1446 1447 return SOC_E_NONE; 1448 1449 } 1450 1451 static int 1452 _soc_th3_cpu_l0_bw_wt_print(int unit, int l0) { 1453 int weight; 1454 int wt_mem_index, mmu_local_port, pipe; 1455 soc_info_t *si = &SOC_INFO(unit); 1456 soc_mem_t mem; 1457 uint32 entry[SOC_MAX_MEM_WORDS]; 1458 int mode, gran, oop; 1459 uint32 refresh, bw; 1460 int port = 0; /* CPU port */ 1461 1462 pipe = si->port_pipe[port]; 1463 mmu_local_port = si->port_l2i_mapping[port]; 1464 wt_mem_index = (mmu_local_port * SOC_TH3_NUM_GP_QUEUES) + l0; 1465 1466 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_QSCH_L0_WEIGHT_MEMm, pipe); 1467 SOC_IF_ERROR_RETURN 1468 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, wt_mem_index, &entry)); 1469 weight = soc_mem_field32_get(unit, mem, &entry, WEIGHTf); 1470 1471 cli_out(" L0: %2d Weight: %d\n", l0, weight); 1472 1473 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_L0_Am, pipe); 1474 SOC_IF_ERROR_RETURN 1475 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, wt_mem_index, &entry)); 1476 mode = soc_mem_field32_get(unit, mem, &entry, PACKET_SHAPINGf); 1477 /* Max BW */ 1478 gran = soc_mem_field32_get(unit, mem, &entry, MAX_METER_GRANf); 1479 refresh = soc_mem_field32_get(unit, mem, &entry, MAX_REFRESHf); 1480 SOC_IF_ERROR_RETURN 1481 (_soc_th3_get_bw_from_ref_gran(unit, refresh, gran, mode, &bw)); 1482 1483 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_BUCKET_L0m, pipe); 1484 SOC_IF_ERROR_RETURN 1485 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, wt_mem_index, &entry)); 1486 oop = soc_mem_field32_get(unit, mem, &entry, MAX_PROFILE_EXCEEDED_FLAGf); 1487 1488 if (!mode) { 1489 cli_out(" Max Bw: %u Kbps Max Exceeded: %d\n", 1490 bw, oop); 1491 } else { 1492 cli_out(" Max Bw: %u pps Max Exceeded: %d\n", 1493 bw, oop); 1494 } 1495 1496 /*Min BW */ 1497 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_L0_Am, pipe); 1498 SOC_IF_ERROR_RETURN 1499 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, wt_mem_index, &entry)); 1500 refresh = soc_mem_field32_get(unit, mem, &entry, MIN_REFRESHf); 1501 mode = soc_mem_field32_get(unit, mem, &entry, PACKET_SHAPINGf); 1502 gran = soc_mem_field32_get(unit, mem, &entry, MIN_METER_GRANf); 1503 SOC_IF_ERROR_RETURN 1504 (_soc_th3_get_bw_from_ref_gran(unit, refresh, gran, mode, &bw)); 1505 1506 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_BUCKET_L0m, pipe); 1507 SOC_IF_ERROR_RETURN 1508 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, wt_mem_index, &entry)); 1509 oop = soc_mem_field32_get(unit, mem, &entry, MIN_PROFILE_SATISFIED_FLAGf); 1510 1511 if (!mode) { 1512 cli_out(" Min Bw: %u Kbps Min Satisfied: %d\n", 1513 bw, oop); 1514 } else { 1515 cli_out(" Min Bw: %u pps Min Satisfied: %d\n", 1516 bw, oop); 1517 } 1518 1519 1520 return SOC_E_NONE; 1521 } 1522 1523 static int 1524 _soc_th3_cpu_l1_bw_wt_print(int unit, int l1) { 1525 int weight; 1526 int wt_mem_index, mmu_local_port, pipe; 1527 soc_info_t *si = &SOC_INFO(unit); 1528 soc_mem_t mem; 1529 uint32 entry[SOC_MAX_MEM_WORDS]; 1530 int mode, gran, oop; 1531 uint32 refresh, bw; 1532 int port = 0; /* CPU port */ 1533 1534 pipe = si->port_pipe[port]; 1535 mmu_local_port = si->port_l2i_mapping[port]; 1536 wt_mem_index = (mmu_local_port * SOC_TH3_NUM_GP_QUEUES) + l1; 1537 1538 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_QSCH_L1_WEIGHT_MEMm, pipe); 1539 SOC_IF_ERROR_RETURN 1540 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, wt_mem_index, &entry)); 1541 weight = soc_mem_field32_get(unit, mem, &entry, WEIGHTf); 1542 1543 cli_out(" L1: %2d Weight: %d\n", l1, weight); 1544 1545 mem = MMU_MTRO_CPU_L1_Am; 1546 SOC_IF_ERROR_RETURN 1547 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l1, &entry)); 1548 mode = soc_mem_field32_get(unit, mem, &entry, PACKET_SHAPINGf); 1549 /* Max BW */ 1550 gran = soc_mem_field32_get(unit, mem, &entry, MAX_METER_GRANf); 1551 refresh = soc_mem_field32_get(unit, mem, &entry, MAX_REFRESHf); 1552 SOC_IF_ERROR_RETURN 1553 (_soc_th3_get_bw_from_ref_gran(unit, refresh, gran, mode, &bw)); 1554 1555 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_BUCKET_CPU_L1m, pipe); 1556 SOC_IF_ERROR_RETURN 1557 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l1, &entry)); 1558 oop = soc_mem_field32_get(unit, mem, &entry, MAX_PROFILE_EXCEEDED_FLAGf); 1559 1560 if (!mode) { 1561 cli_out(" Max Bw: %u Kbps Max Exceeded: %d\n", 1562 bw, oop); 1563 } else { 1564 cli_out(" Max Bw: %u pps Max Exceeded: %d\n", 1565 bw, oop); 1566 } 1567 1568 /*Min BW */ 1569 mem = MMU_MTRO_CPU_L1_Am; 1570 SOC_IF_ERROR_RETURN 1571 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l1, &entry)); 1572 refresh = soc_mem_field32_get(unit, mem, &entry, MIN_REFRESHf); 1573 mode = soc_mem_field32_get(unit, mem, &entry, PACKET_SHAPINGf); 1574 gran = soc_mem_field32_get(unit, mem, &entry, MIN_METER_GRANf); 1575 SOC_IF_ERROR_RETURN 1576 (_soc_th3_get_bw_from_ref_gran(unit, refresh, gran, mode, &bw)); 1577 1578 mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_BUCKET_CPU_L1m, pipe); 1579 SOC_IF_ERROR_RETURN 1580 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, l1, &entry)); 1581 oop = soc_mem_field32_get(unit, mem, &entry, MIN_PROFILE_SATISFIED_FLAGf); 1582 1583 if (!mode) { 1584 cli_out(" Min Bw: %u Kbps Min Satisfied: %d\n", 1585 bw, oop); 1586 } else { 1587 cli_out(" Min Bw: %u pps Min Satisfied: %d\n", 1588 bw, oop); 1589 } 1590 1591 1592 return SOC_E_NONE; 1593 } 1594 1595 1596 static int 1597 _soc_th3_cpu_queue_sched_shap_print(int unit, int port) { 1598 soc_reg_t cpu_map_reg = MMU_MTRO_CPU_L1_TO_L0_MAPPINGr; 1599 int cpu_l1, cpu_l0; 1600 uint32 rval; 1601 1602 if (!IS_CPU_PORT(unit, port)) { 1603 return SOC_E_PARAM; 1604 } 1605 for (cpu_l1 = 0; cpu_l1 < SOC_TH3_NUM_CPU_QUEUES; cpu_l1++) { 1606 cli_out ("Queue: %2d, MC queue \n", cpu_l1); 1607 SOC_IF_ERROR_RETURN 1608 (_soc_th3_cpu_l1_bw_wt_print(unit, cpu_l1)); 1609 1610 rval = 0; 1611 SOC_IF_ERROR_RETURN 1612 (soc_reg32_get(unit, cpu_map_reg, REG_PORT_ANY, cpu_l1, &rval)); 1613 cpu_l0 = soc_reg_field_get(unit, cpu_map_reg, rval, SELECTf); 1614 SOC_IF_ERROR_RETURN 1615 (_soc_th3_cpu_l0_bw_wt_print(unit, cpu_l0)); 1616 1617 } 1618 return SOC_E_NONE; 1619 } 1620 1621 static int 1622 _soc_th3_mmu_scheduler_print(int unit, int port) { 1623 uint32 refresh, bw; 1624 int gran, mode, oop, queue; 1625 soc_mem_t read_mem; 1626 int pipe, mmu_local_port; 1627 soc_info_t *si = &SOC_INFO(unit); 1628 uint32 entry[SOC_MAX_MEM_WORDS]; 1629 1630 pipe = si->port_pipe[port]; 1631 mmu_local_port = si->port_l2i_mapping[port]; 1632 cli_out("######### Scheduling/Shaping debug for Port: %d #########\n", port); 1633 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_EGRMETERINGCONFIGm, pipe); 1634 SOC_IF_ERROR_RETURN 1635 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 1636 refresh = soc_mem_field32_get(unit, read_mem, &entry, REFRESHf); 1637 mode = soc_mem_field32_get(unit, read_mem, &entry, PACKET_SHAPINGf); 1638 gran = soc_mem_field32_get(unit, read_mem, &entry, METER_GRANf); 1639 1640 SOC_IF_ERROR_RETURN 1641 (_soc_th3_get_bw_from_ref_gran(unit, refresh, gran, mode, &bw)); 1642 1643 read_mem = SOC_MEM_UNIQUE_ACC_PIPE(unit, MMU_MTRO_EGRMETERINGBUCKETm, pipe); 1644 SOC_IF_ERROR_RETURN 1645 (soc_mem_read(unit, read_mem, MEM_BLOCK_ALL, mmu_local_port, &entry)); 1646 oop = soc_mem_field32_get(unit, read_mem, &entry, MAX_PROFILE_EXCEEDED_FLAGf); 1647 1648 if (!mode) { 1649 cli_out("Egress Meter Bw: %u Kbps Metering Satisfied: %d\n", bw, oop); 1650 } else { 1651 cli_out("Egress Meter Bw: %u pps Metering Satisfied: %d\n", bw, oop); 1652 } 1653 1654 if (!(IS_CPU_PORT(unit, port))) { 1655 for (queue = 0; queue < SOC_TH3_NUM_GP_QUEUES; queue++) { 1656 _soc_th3_queue_sched_shap_print(unit, port, queue); 1657 } 1658 } else { 1659 _soc_th3_cpu_queue_sched_shap_print(unit, port); 1660 } 1661 1662 return SOC_E_NONE; 1663 } 1664 1665 1666 cmd_result_t 1667 cmd_tm_show_hw_config(int unit, args_t *arg) 1668 { 1669 char *component, *sub_comp, *buf_ent; 1670 pbmp_t pbm; 1671 int port; 1672 int pg, queue, q_max; 1673 int rv = 0; 1674 1675 component = ARG_GET(arg); 1676 if (component == NULL) { 1677 return CMD_USAGE; 1678 } 1679 if (!sal_strcasecmp(component, "ing_buf_debug")) { 1680 sub_comp = ARG_GET(arg); 1681 if (sub_comp == NULL) { 1682 return CMD_USAGE; 1683 } 1684 if (parse_bcm_pbmp(unit, sub_comp, &pbm) < 0) { 1685 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1686 ARG_CMD(arg), sub_comp); 1687 return CMD_FAIL; 1688 } 1689 if (BCM_PBMP_IS_NULL(pbm)) { 1690 ARG_DISCARD(arg); 1691 return CMD_OK; 1692 } 1693 SOC_PBMP_ITER(pbm, port) { 1694 buf_ent = ARG_GET(arg); 1695 if(buf_ent == NULL) { 1696 for (pg = 0; pg < _TH3_MMU_NUM_PG; pg++) { 1697 rv = _soc_th3_pg_debug_print(unit, port, pg); 1698 if (rv < 0) { 1699 return CMD_FAIL; 1700 } 1701 } 1702 } else { 1703 pg = sal_atoi(buf_ent); 1704 rv = _soc_th3_pg_debug_print(unit, port, pg); 1705 if (rv < 0) { 1706 return CMD_FAIL; 1707 } 1708 } 1709 } 1710 } else if (!sal_strcasecmp(component, "egr_buf_debug")) { 1711 sub_comp = ARG_GET(arg); 1712 if (sub_comp == NULL) { 1713 return CMD_USAGE; 1714 } 1715 if (parse_bcm_pbmp(unit, sub_comp, &pbm) < 0) { 1716 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1717 ARG_CMD(arg), sub_comp); 1718 return CMD_FAIL; 1719 } 1720 if (BCM_PBMP_IS_NULL(pbm)) { 1721 ARG_DISCARD(arg); 1722 return CMD_OK; 1723 } 1724 SOC_PBMP_ITER(pbm, port) { 1725 buf_ent = ARG_GET(arg); 1726 if (IS_CPU_PORT(unit, port)) { 1727 q_max = SOC_TH3_NUM_CPU_QUEUES; 1728 } else { 1729 q_max = SOC_TH3_NUM_GP_QUEUES; 1730 } 1731 if(buf_ent == NULL) { 1732 for (queue = 0; queue < q_max; queue++) { 1733 rv = _soc_th3_egr_queue_debug_print(unit, port, queue); 1734 if (rv < 0) { 1735 return CMD_FAIL; 1736 } 1737 } 1738 } else { 1739 queue = sal_atoi(buf_ent); 1740 rv = _soc_th3_egr_queue_debug_print(unit, port, queue); 1741 if (rv < 0) { 1742 return CMD_FAIL; 1743 } 1744 } 1745 } 1746 } else if (!sal_strcasecmp(component, "idb_buf_debug")) { 1747 sub_comp = ARG_GET(arg); 1748 if (sub_comp == NULL) { 1749 return CMD_USAGE; 1750 } 1751 if (parse_bcm_pbmp(unit, sub_comp, &pbm) < 0) { 1752 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1753 ARG_CMD(arg), sub_comp); 1754 return CMD_FAIL; 1755 } 1756 if (BCM_PBMP_IS_NULL(pbm)) { 1757 ARG_DISCARD(arg); 1758 return CMD_OK; 1759 } 1760 SOC_PBMP_ITER(pbm, port) { 1761 if (((IS_MANAGEMENT_PORT(unit, port)) || 1762 (IS_CPU_PORT(unit, port)) || 1763 (IS_LB_PORT(unit, port)))) { 1764 cli_out("OBM buffers not used for port: %d\n", port); 1765 continue; 1766 } 1767 rv = _soc_th3_obm_debug_print(unit, port); 1768 if (rv < 0) { 1769 return CMD_FAIL; 1770 } 1771 } 1772 } else if (!sal_strcasecmp(component, "cosq_debug")) { 1773 sub_comp = ARG_GET(arg); 1774 if (sub_comp == NULL) { 1775 return CMD_USAGE; 1776 } 1777 if (parse_bcm_pbmp(unit, sub_comp, &pbm) < 0) { 1778 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1779 ARG_CMD(arg), sub_comp); 1780 return CMD_FAIL; 1781 } 1782 if (BCM_PBMP_IS_NULL(pbm)) { 1783 ARG_DISCARD(arg); 1784 return CMD_OK; 1785 } 1786 SOC_PBMP_ITER(pbm, port) { 1787 rv = _soc_th3_mmu_scheduler_print(unit, port); 1788 if (rv < 0) { 1789 return CMD_FAIL; 1790 } 1791 } 1792 } else { 1793 return CMD_USAGE; 1794 } 1795 1796 return CMD_OK; 1797 } 1798 1799 #endif /* BCM_TOMAHAWK3_SUPPORT */