check_tm.c (60169B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Diag CLI TMCheck command 8 */ 9 10 #include <soc/defs.h> 11 #if defined(BCM_TOMAHAWK3_SUPPORT) 12 13 #include <appl/diag/system.h> 14 #include <appl/diag/parse.h> 15 #include <shared/bsl.h> 16 #include <bcm/error.h> 17 18 #include <soc/tomahawk3.h> 19 20 #ifdef __KERNEL__ 21 #define atoi _shr_ctoi 22 #endif 23 24 #define _TH3_SPEED_TYPES 7 25 26 char cmd_check_tm_usage[] = 27 " tmcheck <idb | mmu> <portmap | drops> <port> \n" 28 " tmcheck mmu scheduler \n" 29 " tmcheck settings <file>\n" 30 " tmcheck health <all | port> \n"; 31 32 #if !defined(NO_SAL_APPL) && (!defined(NO_FILEIO)) 33 static 34 void chomp(char *str) 35 { 36 while (*str && *str != '\n' && *str != '\r') { 37 str++; 38 } 39 *str = 0; 40 } 41 #endif /* !defined(NO_SAL_APPL) && (!defined(NO_FILEIO)) */ 42 43 STATIC int 44 compare_reg_value (int unit, soc_reg_t reg, int index, int inst, uint64 exp_value) { 45 #define UINT64_HEXA_STR_MAX_SIZE 20 46 uint64 rval; 47 int index_min, index_max, index_loop; 48 char tmp[UINT64_HEXA_STR_MAX_SIZE]; 49 char tm1[UINT64_HEXA_STR_MAX_SIZE]; 50 COMPILER_64_ZERO(rval); 51 52 if ((index < -1 || index >= SOC_REG_NUMELS(unit, reg)) && 53 (SOC_REG_INFO(unit, reg).regtype != soc_portreg)) { 54 LOG_CLI((BSL_META_U(unit, 55 "ERROR: register:%s index:%d is out of range\n"), 56 SOC_REG_NAME(unit, reg), index)); 57 return SOC_E_PARAM; 58 } 59 if (index == -1) { 60 index_min = 0; 61 index_max = SOC_REG_NUMELS(unit, reg); 62 } else { 63 index_min = index; 64 index_max = index; 65 } 66 for (index_loop = index_min; index_loop <= index_max; index_loop++) { 67 if (SOC_REG_INFO(unit, reg).regtype == soc_portreg) { 68 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, index, inst, &rval)); 69 } else { 70 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, inst, index, &rval)); 71 } 72 _shr_format_uint64_hexa_string (rval, tmp); 73 _shr_format_uint64_hexa_string (exp_value, tm1); 74 if(!COMPILER_64_EQ(exp_value, rval)) { 75 LOG_CLI((BSL_META_U(unit, 76 "ERROR: register:%s index:%d exp value:%s " 77 " actual value:%s\n"), 78 SOC_REG_NAME(unit, reg), index_loop, tm1, tmp)); 79 } 80 } 81 #undef UINT64_HEXA_STR_MAX_SIZE 82 return SOC_E_NONE; 83 } 84 85 STATIC int 86 compare_reg_field_value (int unit, soc_reg_t reg, 87 soc_field_info_t* fld, int index, int inst, uint64 exp_value) { 88 #define UINT64_HEXA_STR_MAX_SIZE 20 89 uint64 rval; 90 uint64 act_value; 91 soc_field_t field = fld->field; 92 int index_min, index_max, index_loop; 93 char tmp[UINT64_HEXA_STR_MAX_SIZE]; 94 char tm1[UINT64_HEXA_STR_MAX_SIZE]; 95 COMPILER_64_ZERO(rval); 96 97 if ((index < -1 || index >= SOC_REG_NUMELS(unit, reg)) && 98 (SOC_REG_INFO(unit, reg).regtype != soc_portreg)) { 99 LOG_CLI((BSL_META_U(unit, 100 "ERROR: register:%s index:%d is out of range\n"), 101 SOC_REG_NAME(unit, reg), index)); 102 return SOC_E_PARAM; 103 } 104 if (index == -1) { 105 index_min = 0; 106 index_max = SOC_REG_NUMELS(unit, reg); 107 } else { 108 index_min = index; 109 index_max = index; 110 } 111 for (index_loop = index_min; index_loop <= index_max; index_loop++) { 112 if (SOC_REG_INFO(unit, reg).regtype == soc_portreg) { 113 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, index, inst, &rval)); 114 } else { 115 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, inst, index, &rval)); 116 } 117 act_value = soc_reg64_field_get(unit, reg, rval, field); 118 _shr_format_uint64_hexa_string (act_value, tmp); 119 _shr_format_uint64_hexa_string (exp_value, tm1); 120 if(!COMPILER_64_EQ(exp_value, act_value)) { 121 LOG_CLI((BSL_META_U(unit, 122 "ERROR: register:%s index:%d field_name : %s exp value:%s " 123 " actual value:%s\n"), 124 SOC_REG_NAME(unit, reg), index_loop, SOC_FIELD_NAME(unit, 125 fld->field), tm1, tmp)); 126 } 127 } 128 #undef UINT64_HEXA_STR_MAX_SIZE 129 return SOC_E_NONE; 130 } 131 132 STATIC int 133 compare_mem_field_value (int unit, soc_mem_t mem, 134 soc_field_info_t* fld, int index, uint64 exp_value) { 135 #define UINT64_HEXA_STR_MAX_SIZE 20 136 uint32 read_entry[SOC_MAX_MEM_WORDS]; 137 uint64 act_value; 138 char tmp[UINT64_HEXA_STR_MAX_SIZE]; 139 char tm1[UINT64_HEXA_STR_MAX_SIZE]; 140 soc_field_t field = fld->field; 141 142 SOC_IF_ERROR_RETURN(soc_mem_read(unit, mem, MEM_BLOCK_ANY, index, 143 read_entry)); 144 soc_mem_field64_get(unit, mem, read_entry, field, &act_value); 145 _shr_format_uint64_hexa_string (act_value, tmp); 146 _shr_format_uint64_hexa_string (exp_value, tm1); 147 148 if(!COMPILER_64_EQ(exp_value, act_value)) { 149 LOG_CLI((BSL_META_U(unit, 150 "ERROR: memory:%s index:%d field_name:%s, exp value:%s" 151 " actual value:%s\n"), 152 SOC_MEM_UFNAME(unit, mem), index, SOC_FIELD_NAME(unit, fld->field), 153 tm1, tmp)); 154 } 155 #undef UINT64_HEXA_STR_MAX_SIZE 156 return SOC_E_NONE; 157 } 158 159 STATIC int 160 exp_value_field_len_check (int unit, soc_field_info_t* fld, 161 uint64 exp_value) { 162 163 #define UINT64_HEXA_STR_MAX_SIZE 20 164 uint64 tmask; 165 char tm1[UINT64_HEXA_STR_MAX_SIZE]; 166 COMPILER_64_MASK_CREATE(tmask, fld->len, 0); 167 COMPILER_64_NOT(tmask); 168 COMPILER_64_AND(tmask, exp_value); 169 170 _shr_format_uint64_hexa_string (exp_value, tm1); 171 if (!COMPILER_64_IS_ZERO(tmask)) { 172 cli_out("Value : %s too large for %d-bit field \"%s\".\n", 173 tm1, fld->len, SOC_FIELD_NAME(unit, fld->field)); 174 #undef UINT64_HEXA_STR_MAX_SIZE 175 return SOC_E_PARAM; 176 } 177 #undef UINT64_HEXA_STR_MAX_SIZE 178 return SOC_E_NONE; 179 } 180 181 STATIC int 182 th3_override_index_based_on_port (int unit, soc_mem_t mem, int port) { 183 int mem_index; 184 int block_info_index; 185 int mem_depth; 186 187 block_info_index = SOC_MEM_BLOCK_ANY(unit, mem); 188 if ((SOC_BLOCK_TYPE(unit, block_info_index) != SOC_BLK_MMU_ITM) && 189 (SOC_BLOCK_TYPE(unit, block_info_index) != SOC_BLK_MMU_EB) && 190 (SOC_BLOCK_TYPE(unit, block_info_index) != SOC_BLK_MMU_GLB)) { 191 /*index transformation not applicable for non-MMU memories*/ 192 return -1; 193 } else { 194 /*Index transformation for MMU memories based on port number*/ 195 mem_depth = soc_mem_index_max(unit, mem) + 1; 196 if (mem_depth == 20) { 197 /*Mem indexed by local MMU port number*/ 198 mem_index = SOC_TH3_MMU_LOCAL_PORT(unit, port); 199 } else if (mem_depth == 160) { 200 /*MMU mem indexed by MMU chip port number*/ 201 mem_index = SOC_TH3_MMU_CHIP_PORT(unit, port); 202 } else { 203 mem_index = -1; 204 } 205 } 206 return mem_index; 207 } 208 209 STATIC int 210 memory_field_check (int unit, soc_mem_t mem, int index, soc_field_t field, 211 uint64 exp_value, int port_num, int override_index) { 212 soc_field_info_t *fld; 213 soc_mem_info_t *m; 214 int mem_tot = 1, mem_idx, new_index = -1, memory_index; 215 soc_mem_t *mem_list; 216 int rv = SOC_E_NONE; 217 218 /*Reserving array of length 64 for max combinations of EB/IPIPE in TH3*/ 219 mem_list = sal_alloc(64 * sizeof(soc_mem_t), "List of MMU logicla views"); 220 if (mem_list == NULL) { 221 return SOC_E_MEMORY; 222 } 223 224 if (port_num != -1) { 225 /*Expand based on port only if it is per-port memory*/ 226 rv = soc_th3_retrieve_mmu_mem_list_for_port(unit, port_num, mem, -1, 227 mem_list, 64, &mem_tot); 228 if (rv) { 229 mem_list[0] = mem; 230 } 231 } else { 232 mem_list[0] = mem; 233 } 234 235 if (override_index == 1) { 236 new_index = th3_override_index_based_on_port(unit, mem_list[0], 237 port_num); 238 } 239 if (new_index != -1) { 240 memory_index = new_index; 241 } else { 242 memory_index = index; 243 } 244 245 for(mem_idx = 0; mem_idx < mem_tot; mem_idx++) { 246 mem = mem_list[mem_idx]; 247 if (mem != INVALIDm) { 248 m = &SOC_MEM_INFO(unit, mem); 249 for (fld = &m->fields[0]; fld < &m->fields[m->nFields]; fld++) { 250 if (fld->field == field) { 251 break; 252 } 253 } 254 if (fld == &m->fields[m->nFields]) { 255 cli_out("No such field \"%s\" in memory \"%s\".\n", 256 SOC_FIELD_NAME(unit, fld->field), SOC_MEM_UFNAME(unit, mem)); 257 sal_free(mem_list); 258 return SOC_E_PARAM; 259 } else { 260 rv = exp_value_field_len_check(unit, fld, 261 exp_value); 262 if (rv) { 263 cli_out ("Field length check failed in memory:%s \n", 264 SOC_MEM_UFNAME(unit, mem)); 265 sal_free(mem_list); 266 return rv; 267 } 268 rv = compare_mem_field_value (unit, mem, 269 fld, memory_index, exp_value); 270 } 271 } 272 } 273 sal_free(mem_list); 274 return rv; 275 } 276 277 #if !defined(NO_SAL_APPL) && (!defined(NO_FILEIO)) 278 STATIC int 279 memory_params_parse_check (int unit, char* mem_name, int index, char* 280 field_name, uint64 exp_value, int port_num, int override_index) { 281 soc_mem_t mem = INVALIDm; 282 soc_field_info_t *fld; 283 soc_mem_info_t *m; 284 int copyno; 285 int mem_tot = 1, mem_idx, new_index = -1, memory_index; 286 soc_mem_t *mem_list; 287 int rv = SOC_E_NONE; 288 289 /*Reserving array of length 64 for max combinations of EB/IPIPE in TH3*/ 290 mem_list = sal_alloc(64 * sizeof(soc_mem_t), "List of MMU logicla views"); 291 if (mem_list == NULL) { 292 return SOC_E_MEMORY; 293 } 294 295 if (parse_memory_name(unit, &mem, mem_name, ©no, 0) < 0) { 296 cli_out("ERROR: unknown table \"%s\"\n", mem_name); 297 sal_free(mem_list); 298 return SOC_E_PARAM; 299 } 300 if (port_num != -1) { 301 /*Expand based on port only if it is per-port memory*/ 302 rv = soc_th3_retrieve_mmu_mem_list_for_port(unit, port_num, mem, -1, 303 mem_list, 64, &mem_tot); 304 if (rv) { 305 mem_list[0] = mem; 306 } 307 } else { 308 mem_list[0] = mem; 309 } 310 311 if (override_index == 1) { 312 new_index = th3_override_index_based_on_port(unit, mem_list[0], 313 port_num); 314 } 315 if (new_index != -1) { 316 memory_index = new_index; 317 } else { 318 memory_index = index; 319 } 320 321 for(mem_idx = 0; mem_idx < mem_tot; mem_idx++) { 322 mem = mem_list[mem_idx]; 323 if (mem != INVALIDm) { 324 m = &SOC_MEM_INFO(unit, mem); 325 for (fld = &m->fields[0]; fld < &m->fields[m->nFields]; fld++) { 326 if (!sal_strcasecmp(field_name, SOC_FIELD_NAME(unit, 327 fld->field))) { 328 break; 329 } 330 } 331 if (fld == &m->fields[m->nFields]) { 332 cli_out("No such field \"%s\" in memory \"%s\".\n", 333 field_name, SOC_MEM_UFNAME(unit, mem)); 334 sal_free(mem_list); 335 return SOC_E_PARAM; 336 } else { 337 rv = exp_value_field_len_check(unit, fld, 338 exp_value); 339 if (rv) { 340 cli_out ("Field length check failed in memory:%s \n", 341 mem_name); 342 sal_free(mem_list); 343 return rv; 344 } 345 rv = compare_mem_field_value (unit, mem, 346 fld, memory_index, exp_value); 347 } 348 } 349 } 350 sal_free(mem_list); 351 return rv; 352 } 353 354 STATIC int 355 register_params_parse_check (int unit, char* reg_name, int index, char* 356 field_name, uint64 exp_value) { 357 soc_reg_t reg = INVALIDr; 358 soc_regaddrlist_t alist; 359 soc_regaddrinfo_t *ainfo; 360 soc_reg_info_t *reg_info; 361 soc_field_info_t *fld; 362 int rv; 363 364 if (soc_regaddrlist_alloc(&alist) < 0) { 365 cli_out("Could not allocate address list. Memory error.\n"); 366 } 367 368 if (parse_symbolic_reference(unit, &alist, reg_name) < 0) { 369 cli_out("Unknown register name \"%s\"\n", reg_name); 370 soc_regaddrlist_free(&alist); 371 return SOC_E_PARAM; 372 } 373 ainfo = &alist.ainfo[0]; 374 reg = ainfo->reg; 375 reg_info = &SOC_REG_INFO(unit, reg); 376 for (fld = ®_info->fields[0]; fld < 377 ®_info->fields[reg_info->nFields]; fld++) { 378 if (!sal_strcasecmp(field_name, SOC_FIELD_NAME(unit, fld->field))) { 379 break; 380 } 381 } 382 if (fld == ®_info->fields[reg_info->nFields]) { 383 cli_out("No such field \"%s\" in register \"%s\".\n", 384 field_name, SOC_REG_NAME(unit, reg)); 385 soc_regaddrlist_free(&alist); 386 return SOC_E_PARAM; 387 } else { 388 rv = exp_value_field_len_check(unit, fld, exp_value); 389 if (!rv) { 390 compare_reg_field_value (unit, reg, fld, index, REG_PORT_ANY, exp_value); 391 } else { 392 soc_regaddrlist_free(&alist); 393 return rv; 394 } 395 } 396 soc_regaddrlist_free(&alist); 397 return SOC_E_NONE; 398 } 399 #endif 400 401 void 402 th3_check_settings_from_file(int unit, char* file_name) { 403 #if !defined(NO_SAL_APPL) && (!defined(NO_FILEIO)) 404 FILE* fp; 405 char line[1024]; 406 char *split1 = NULL; 407 char *check_args[32] = {NULL}; 408 int arg_idx; 409 int is_mem = -1, reg_mem_idx; 410 uint64 exp_value; 411 char *reg_mem_name = NULL, *field_name = NULL; 412 int port_num = -1, override_index = -1; 413 int err = 0; 414 int port; 415 416 fp = sal_fopen(file_name, "r"); 417 if (fp == NULL) { 418 cli_out("*ERROR: Cannot open bcm config file: '%s'\n", file_name); 419 } else { 420 cli_out("\nRetrieveing expected settings from: '%s'", file_name); 421 while (sal_fgets(line, sizeof(line), fp)) { 422 split1 = sal_strtok(line,","); 423 arg_idx = 0; 424 while (split1) { 425 check_args[arg_idx++] = split1; 426 split1 = sal_strtok(NULL,","); 427 } 428 429 /*Expected input format (required args): 430 * 1-bit to indicate reg/mem; (0-reg; 1-mem) 431 * reg/memory name 432 * index 433 * field name 434 * expected value 435 */ 436 for (arg_idx = 0; arg_idx < 5; arg_idx++) { 437 if (check_args[arg_idx] == NULL) { 438 cli_out("Fail: insufficient number of args in input file line"); 439 err = 1; 440 } 441 } 442 if (err == 0) { 443 is_mem = sal_atoi(check_args[0]); 444 reg_mem_name = check_args[1]; 445 reg_mem_idx = sal_atoi(check_args[2]); 446 field_name = check_args[3]; 447 chomp(check_args[4]); 448 exp_value = parse_uint64(check_args[4]); 449 /*Additional optional args (only for memories) 450 *logical port num 451 *MMU queue num for a per-queue memory 452 */ 453 if (check_args[5] != NULL) { 454 chomp(check_args[5]); 455 port_num = sal_atoi(check_args[5]); 456 } 457 /*Optional param to indicate index override based on port number for 458 * MMU memories*/ 459 if (check_args[6] != NULL) { 460 chomp(check_args[6]); 461 override_index = sal_atoi(check_args[6]); 462 } 463 if (is_mem == 1) { 464 /*Process for memory*/ 465 if (port_num != -1) { 466 memory_params_parse_check (unit, reg_mem_name, reg_mem_idx, 467 field_name, exp_value, port_num, override_index); 468 } else { 469 PBMP_ALL_ITER(unit, port) { 470 memory_params_parse_check (unit, reg_mem_name, reg_mem_idx, 471 field_name, exp_value, port, override_index); 472 } 473 } 474 } else if (is_mem == 0) { 475 /*Process for register*/ 476 register_params_parse_check (unit, reg_mem_name, reg_mem_idx, 477 field_name, exp_value); 478 } else { 479 cli_out("Invalid input in register/memory indication"); 480 continue; 481 } 482 } 483 } 484 sal_fclose(fp); 485 } 486 #endif /*ifndef NO_SAL_APPL*/ 487 } 488 489 STATIC void 490 th3_check_global_health_regs (int unit) { 491 int reg_idx = 0; 492 static const struct { 493 soc_reg_t ref_reg; 494 uint32 exp_value; 495 } reg_val_list[] = { 496 {MMU_GLBCFG_MEM_FAIL_INT_CTRr, 0x0}, 497 {MMU_GLBCFG_ECC_SINGLE_BIT_ERRORSr, 0x0}, 498 {MMU_GLBCFG_MEM_SER_FIFO_STSr, 0x1}, 499 {MMU_GLBCFG_CPU_INT_STATr, 0x0}, 500 {MMU_INTFO_THDR_TO_OOBFC_SP_STr, 0x0}, 501 {MMU_INTFO_THDI_TO_OOBFC_SP_STr, 0x0}, 502 {MMU_INTFO_THDO_TO_OOBFC_SP_STr, 0x0}, 503 {MMU_INTFO_THDO_TO_OOBFC_SP_MC_STr, 0x0}, 504 {MMU_INTFO_OOBFC_STSr, 0x0}, 505 {MMU_INTFO_TO_XPORT_BKPr, 0x0}, 506 {EDB_INTR_STATUSr, 0x0}, 507 {EDB_SER_FIFO_STATUSr, 0x0}, 508 {MMU_CFAP_STATUSr, 0x0}, 509 {INVALIDr, 0x0} 510 }; 511 uint64 value; 512 513 for (reg_idx = 0; reg_val_list[reg_idx].ref_reg != INVALIDr; reg_idx++) { 514 COMPILER_64_ZERO(value); 515 COMPILER_64_SET(value, 0x0, reg_val_list[reg_idx].exp_value); 516 compare_reg_value (unit, reg_val_list[reg_idx].ref_reg, 0, 0, 517 value); 518 } 519 520 } 521 522 STATIC void 523 th3_check_per_pool_regs(int unit, int itm) { 524 int reg_idx, pool; 525 static const struct { 526 soc_reg_t ref_reg; 527 uint32 exp_value; 528 } reg_val_list[] = { 529 {MMU_THDO_SHARED_DB_POOL_SHARED_COUNT_DEBUG_MCr, 0x0}, 530 {MMU_THDI_POOL_SHARED_COUNT_SPr, 0x0}, 531 {MMU_THDO_SHARED_DB_POOL_SHARED_COUNTr, 0x0}, 532 {MMU_THDO_SHARED_DB_POOL_SHARED_COUNT_DEBUG_LOSSLESSr, 0x0}, 533 {MMU_THDO_MC_SHARED_CQE_POOL_SHARED_COUNTr, 0x0}, 534 {MMU_THDI_HDRM_POOL_COUNT_HPr, 0x0}, 535 {INVALIDr, 0x0} 536 }; 537 uint64 value; 538 for (reg_idx = 0; reg_val_list[reg_idx].ref_reg != INVALIDr; reg_idx++) { 539 for (pool = 0; pool < _TH3_MMU_NUM_POOL; pool++) { 540 COMPILER_64_ZERO(value); 541 COMPILER_64_SET(value, 0x0, reg_val_list[reg_idx].exp_value); 542 compare_reg_value (unit, reg_val_list[reg_idx].ref_reg, pool, itm, 543 value); 544 } 545 } 546 } 547 548 STATIC void 549 th3_check_per_rqe_queue_regs(int unit, int itm) { 550 int reg_idx, rqe_q; 551 static const struct { 552 soc_reg_t ref_reg; 553 uint32 exp_value; 554 } reg_val_list[] = { 555 {MMU_THDR_QE_SHARED_COUNT_PRIQr, 0x0}, 556 {MMU_THDR_QE_STATUS_PRIQr, 0x0}, 557 {MMU_THDR_QE_MIN_COUNT_PRIQr, 0x0}, 558 {MMU_THDR_QE_TOTAL_COUNT_PRIQr, 0x0}, 559 {INVALIDr, 0x0} 560 }; 561 uint64 value; 562 for (reg_idx = 0; reg_val_list[reg_idx].ref_reg != INVALIDr; reg_idx++) { 563 for (rqe_q = 0; rqe_q < _TH3_MMU_NUM_RQE_QUEUES; rqe_q++) { 564 COMPILER_64_ZERO(value); 565 COMPILER_64_SET(value, 0x0, reg_val_list[reg_idx].exp_value); 566 compare_reg_value (unit, reg_val_list[reg_idx].ref_reg, rqe_q, itm, 567 value); 568 } 569 } 570 } 571 572 573 STATIC void 574 th3_check_per_itm_health_regs (int unit, int itm) { 575 int reg_idx; 576 static const struct { 577 soc_reg_t ref_reg; 578 uint32 exp_value; 579 } reg_val_list[] = { 580 {MMU_THDO_SHARED_DB_POOL_DROP_STATESr, 0x0}, 581 {MMU_THDI_POOL_DROP_STATEr, 0x0}, 582 {MMU_THDO_CPU_QUEUE_DROP_STATES_47_36r, 0x0}, 583 {MMU_THDO_CPU_QUEUE_DROP_STATES_23_12r, 0x0}, 584 {MMU_THDO_CPU_QUEUE_DROP_STATES_35_24r, 0x0}, 585 {MMU_THDO_CPU_QUEUE_DROP_STATES_11_00r, 0x0}, 586 {MMU_THDR_QE_STATUS_SPr, 0x0}, 587 {MMU_THDO_MC_SHARED_CQE_POOL_DROP_STATESr, 0x0}, 588 {MMU_CFAP_INT_STATr, 0x0}, 589 {MMU_RL_CPU_INT_STATr, 0x0}, 590 {MMU_RL_DEBUG_PKT_CNTr, 0x0}, 591 {MMU_CRB_CPU_INT_STATr, 0x0}, 592 {MMU_ITMCFG_CPU_INT_STATr, 0x0}, 593 {MMU_ITMCFG_MEM_SER_FIFO_STSr, 0x1}, 594 {MMU_CFAP_STATUSr, 0x0}, 595 {MMU_CFAP_DROP_CBPr, 0x0}, 596 {MMU_CFAP_DROP_FULLr, 0x0}, 597 {MMU_CFAP_DROP_COLLISIONr, 0x0}, 598 {MMU_SCB_CPU_INT_STATr, 0x0}, 599 {MMU_RQE_INT_STATr, 0x0}, 600 {MMU_ITMCFG_ECC_SINGLE_BIT_ERRORSr, 0x0}, 601 {MMU_THDR_QE_CPU_INT_STATr, 0x0}, 602 {MMU_RQE_L3_PURGE_STATr, 0x0}, 603 {MMU_CRB_CPU_INT_STAT_LOGr, 0x0}, 604 {MMU_THDI_HDRM_POOL_STATUSr, 0x0}, 605 {MMU_THDR_QE_SHARED_COUNT_SPr, 0x0}, 606 {MMU_TOQ_CPU_INT_STATr, 0x0}, 607 {MMU_THDO_CPU_INT_STATr, 0x0}, 608 {MMU_ITMCFG_MEM_FAIL_INT_CTRr, 0x0}, 609 {MMU_OQS_CPU_INT_STATr, 0x0}, 610 {MMU_THDR_QE_COUNTER_OVERFLOWr, 0x0}, 611 {MMU_THDR_QE_COUNTER_UNDERFLOWr, 0x0}, 612 {MMU_THDO_COUNTER_UNDERFLOW_IDr, 0x0}, 613 {MMU_THDO_COUNTER_OVERFLOW_IDr, 0x0}, 614 {MMU_TOQ_STATUSr, 0x1}, 615 {INVALIDr, 0x0} 616 }; 617 uint64 value; 618 for (reg_idx = 0; reg_val_list[reg_idx].ref_reg != INVALIDr; reg_idx++) { 619 COMPILER_64_ZERO(value); 620 COMPILER_64_SET(value, 0x0, reg_val_list[reg_idx].exp_value); 621 compare_reg_value (unit, reg_val_list[reg_idx].ref_reg, 0, itm, 622 value); 623 } 624 th3_check_per_pool_regs(unit, itm); 625 th3_check_per_rqe_queue_regs(unit, itm); 626 } 627 628 629 STATIC void 630 th3_check_per_pipe_health_regs (int unit, int pipe) { 631 int reg_idx; 632 static const struct { 633 soc_reg_t ref_reg; 634 uint32 exp_value; 635 } reg_val_list[] = { 636 {IDB_CA_CPU_ECC_STATUSr, 0x0}, 637 {IDB_CA_LPBK_ECC_STATUSr, 0x0}, 638 {CELL_QUEUE_ECC_STATUS_INTRr, 0x0}, 639 {EVENT_FIFO_ECC_STATUS_INTRr, 0x0}, 640 {SLOT_PIPELINE_ECC_STATUS_INTRr, 0x0}, 641 {MMU_EBCFG_MEM_FAIL_INT_CTRr, 0x0}, 642 {MMU_EBTOQ_CPU_INT_STATr, 0x0}, 643 {MMU_QSCH_PORT_EMPTY_STATUSr, 0xfffff}, 644 {MMU_EBCFG_ECC_SINGLE_BIT_ERRORSr, 0x0}, 645 {MMU_EBCFG_CPU_INT_STATr, 0x0}, 646 {MMU_INTFI_PORT_FC_BKPr, 0x0}, 647 {MMU_EBCFP_CPU_INT_STATr, 0x0}, 648 {MMU_EBCTM_PORT_EMPTY_STSr, 0xfffff}, 649 {MMU_EBCFG_MEM_SER_FIFO_STSr, 0x1}, 650 {MMU_EBPCC_COUNTER_OVERFLOWr, 0x1ff}, 651 {MMU_EBPCC_COUNTER_UNDERFLOWr, 0x1ff}, 652 {MMU_SCB_SCQE_CNT_OVERFLOWr, 0x0}, 653 {MMU_SCB_SCQE_CNT_UNDERFLOWr, 0x0}, 654 {MMU_SCB_SCQ_HP_FIFO_UNDERFLOWr, 0x0}, 655 {MMU_EBCFP_MTU_VIOLATION_STATUSr, 0x1ff}, 656 {MMU_EBCFP_POOL_COUNTERr, 0x0}, 657 {MMU_SCB_SCQ_PKT_CELL_CNT_STATUSr, 0x0}, 658 {MMU_SCB_SCQ_HP_FIFO_OVERFLOWr, 0x0}, 659 {MMU_SCB_SCQ_CELL_CNT_STATUSr, 0x0}, 660 {MMU_EBPCC_CPU_INT_STATr, 0x0}, 661 {MMU_MTRO_CPU_INT_STATr, 0x0}, 662 {MMU_EBCTM_CPU_INT_STATr, 0x0}, 663 {MMU_EBQS_CPU_INT_STATr, 0x0}, 664 {INVALIDr, 0x0} 665 }; 666 uint64 value; 667 for (reg_idx = 0; reg_val_list[reg_idx].ref_reg != INVALIDr; reg_idx++) { 668 COMPILER_64_ZERO(value); 669 COMPILER_64_SET(value, 0x0, reg_val_list[reg_idx].exp_value); 670 compare_reg_value (unit, reg_val_list[reg_idx].ref_reg, 0, pipe, 671 value); 672 } 673 674 } 675 676 STATIC int 677 th3_get_pm_from_phy_port(int phy_port) { 678 return (((phy_port - 1) & 0x1f) >> 3); 679 } 680 681 STATIC int 682 th3_get_subp_from_phy_port(int phy_port) { 683 return ((phy_port - 1) & 0x7); 684 } 685 686 STATIC void 687 th3_check_idb_port_regs(int unit, int port) { 688 689 static const soc_reg_t obm_usage_regs[][_TH3_PBLKS_PER_PIPE] = { 690 {IDB_OBM0_USAGEr, IDB_OBM1_USAGEr, IDB_OBM2_USAGEr, IDB_OBM3_USAGEr}, 691 {IDB_OBM0_USAGE_1r, IDB_OBM1_USAGE_1r, IDB_OBM2_USAGE_1r, 692 IDB_OBM3_USAGE_1r}, 693 {INVALIDr, INVALIDr, INVALIDr, INVALIDr} 694 }; 695 static const soc_reg_t obm_hw_status_regs[_TH3_PBLKS_PER_PIPE] = { 696 IDB_OBM0_HW_STATUSr, IDB_OBM1_HW_STATUSr, IDB_OBM2_HW_STATUSr, 697 IDB_OBM3_HW_STATUSr 698 }; 699 static const soc_field_t obm_hw_status_fields[_TH3_PORTS_PER_PBLK] = { 700 RESIDUE_EMPTY_PORT0f, RESIDUE_EMPTY_PORT1f, RESIDUE_EMPTY_PORT2f, 701 RESIDUE_EMPTY_PORT3f, RESIDUE_EMPTY_PORT4f, RESIDUE_EMPTY_PORT5f, 702 RESIDUE_EMPTY_PORT6f, RESIDUE_EMPTY_PORT7f 703 }; 704 static const soc_reg_t ca_hw_status_regs[_TH3_PBLKS_PER_PIPE] = { 705 IDB_CA0_HW_STATUSr, IDB_CA1_HW_STATUSr, IDB_CA2_HW_STATUSr, 706 IDB_CA3_HW_STATUSr 707 }; 708 static const soc_field_t ca_fifo_full_fields[_TH3_PORTS_PER_PBLK] = { 709 FIFO_FULL_PORT0f, FIFO_FULL_PORT1f, FIFO_FULL_PORT2f, 710 FIFO_FULL_PORT3f, FIFO_FULL_PORT4f, FIFO_FULL_PORT5f, 711 FIFO_FULL_PORT6f, FIFO_FULL_PORT7f 712 }; 713 static const soc_field_t ca_fifo_ovrrun_fields[_TH3_PORTS_PER_PBLK] = { 714 FIFO_OVERRUN_ERR_PORT0f, FIFO_OVERRUN_ERR_PORT1f, FIFO_OVERRUN_ERR_PORT2f, 715 FIFO_OVERRUN_ERR_PORT3f, FIFO_OVERRUN_ERR_PORT4f, FIFO_OVERRUN_ERR_PORT5f, 716 FIFO_OVERRUN_ERR_PORT6f, FIFO_OVERRUN_ERR_PORT7f 717 }; 718 static const soc_reg_t ca_hw_status_2_regs[_TH3_PBLKS_PER_PIPE] = { 719 IDB_CA0_HW_STATUS_2r, IDB_CA1_HW_STATUS_2r, IDB_CA2_HW_STATUS_2r, 720 IDB_CA3_HW_STATUS_2r 721 }; 722 static const soc_field_t ca_cell_len_err_fields[_TH3_PORTS_PER_PBLK] = { 723 CELL_LEN_ERR_PORT0f, CELL_LEN_ERR_PORT1f, CELL_LEN_ERR_PORT2f, 724 CELL_LEN_ERR_PORT3f, CELL_LEN_ERR_PORT4f, CELL_LEN_ERR_PORT5f, 725 CELL_LEN_ERR_PORT6f, CELL_LEN_ERR_PORT7f 726 }; 727 static const soc_field_t ca_sop_eop_err_fields[_TH3_PORTS_PER_PBLK] = { 728 SOP_EOP_ERR_PORT0f, SOP_EOP_ERR_PORT1f, SOP_EOP_ERR_PORT2f, 729 SOP_EOP_ERR_PORT3f, SOP_EOP_ERR_PORT4f, SOP_EOP_ERR_PORT5f, 730 SOP_EOP_ERR_PORT6f, SOP_EOP_ERR_PORT7f 731 }; 732 static const soc_field_t ca_fifo_underrun_fields[_TH3_PORTS_PER_PBLK] = { 733 FIFO_UNDERRUN_ERR_PORT0f, FIFO_UNDERRUN_ERR_PORT1f, FIFO_UNDERRUN_ERR_PORT2f, 734 FIFO_UNDERRUN_ERR_PORT3f, FIFO_UNDERRUN_ERR_PORT4f, FIFO_UNDERRUN_ERR_PORT5f, 735 FIFO_UNDERRUN_ERR_PORT6f, FIFO_UNDERRUN_ERR_PORT7f 736 }; 737 soc_info_t *si = &SOC_INFO(unit); 738 int phy_port = si->port_l2p_mapping[port]; 739 int pipe = si->port_pipe[port]; 740 int pm_num = th3_get_pm_from_phy_port(phy_port); 741 int subp = th3_get_subp_from_phy_port(phy_port); 742 int reg_idx; 743 soc_reg_t reg; 744 soc_field_t field; 745 soc_reg_info_t *reg_info; 746 soc_field_info_t *fld; 747 uint64 value; 748 749 for (reg_idx = 0; obm_usage_regs[reg_idx][0] != INVALIDr; reg_idx++) { 750 reg = obm_usage_regs[reg_idx][pm_num]; 751 COMPILER_64_ZERO(value); 752 compare_reg_value(unit, reg, subp, pipe, value); 753 } 754 755 reg = obm_hw_status_regs[pm_num]; 756 field = obm_hw_status_fields[subp]; 757 reg_info = &SOC_REG_INFO(unit, reg); 758 for (fld = ®_info->fields[0]; fld < 759 ®_info->fields[reg_info->nFields]; fld++) { 760 if (field == fld->field) { 761 break; 762 } 763 } 764 COMPILER_64_SET(value, 0x0, 0x1); 765 compare_reg_field_value(unit, reg, fld, 0, pipe, value); 766 767 reg = ca_hw_status_regs[pm_num]; 768 reg_info = &SOC_REG_INFO(unit, reg); 769 field = ca_fifo_full_fields[subp]; 770 for (fld = ®_info->fields[0]; fld < 771 ®_info->fields[reg_info->nFields]; fld++) { 772 if (field == fld->field) { 773 break; 774 } 775 } 776 COMPILER_64_ZERO(value); 777 compare_reg_field_value(unit, reg, fld, 0, pipe, value); 778 field = ca_fifo_ovrrun_fields[subp]; 779 for (fld = ®_info->fields[0]; fld < 780 ®_info->fields[reg_info->nFields]; fld++) { 781 if (field == fld->field) { 782 break; 783 } 784 } 785 COMPILER_64_ZERO(value); 786 compare_reg_field_value(unit, reg, fld, 0, pipe, value); 787 788 reg = ca_hw_status_2_regs[pm_num]; 789 reg_info = &SOC_REG_INFO(unit, reg); 790 field = ca_cell_len_err_fields[subp]; 791 for (fld = ®_info->fields[0]; fld < 792 ®_info->fields[reg_info->nFields]; fld++) { 793 if (field == fld->field) { 794 break; 795 } 796 } 797 COMPILER_64_ZERO(value); 798 compare_reg_field_value(unit, reg, fld, 0, pipe, value); 799 field = ca_sop_eop_err_fields[subp]; 800 for (fld = ®_info->fields[0]; fld < 801 ®_info->fields[reg_info->nFields]; fld++) { 802 if (field == fld->field) { 803 break; 804 } 805 } 806 COMPILER_64_ZERO(value); 807 compare_reg_field_value(unit, reg, fld, 0, pipe, value); 808 field = ca_fifo_underrun_fields[subp]; 809 for (fld = ®_info->fields[0]; fld < 810 ®_info->fields[reg_info->nFields]; fld++) { 811 if (field == fld->field) { 812 break; 813 } 814 } 815 COMPILER_64_ZERO(value); 816 compare_reg_field_value(unit, reg, fld, 0, pipe, value); 817 } 818 819 STATIC void 820 th3_check_mmu_port_regs(int unit, int port) { 821 int reg_idx; 822 static const struct { 823 soc_reg_t ref_reg; 824 uint32 exp_value; 825 } reg_val_list[] = { 826 {MMU_INTFI_PORT_PFC_STATEr, 0x0}, 827 {MMU_EBCTM_CNTR_1_STSr, 0x0}, 828 {MMU_THDI_PORT_LIMIT_STATESr, 0x0}, 829 {MMU_THDI_FLOW_CONTROL_XOFF_STATEr, 0x0}, 830 {MMU_THDI_SCR_CNT_STATUSr, 0x0}, 831 {MMU_INTFI_MMU_PORT_TO_MMU_QUEUES_FC_BKPr, 0x0}, 832 {MMU_EBPTS_PKSCH_CREDIT_STSr, 0x1}, 833 {IS_PKSCH_CREDIT_STSr, 0x1}, 834 {INVALIDr, 0x0} 835 }; 836 uint64 value; 837 for (reg_idx = 0; reg_val_list[reg_idx].ref_reg != INVALIDr; reg_idx++) { 838 COMPILER_64_ZERO(value); 839 COMPILER_64_SET(value, 0x0, reg_val_list[reg_idx].exp_value); 840 compare_reg_value (unit, reg_val_list[reg_idx].ref_reg, 0, port, 841 value); 842 } 843 if ((!IS_MANAGEMENT_PORT(unit, port)) && 844 (!IS_CPU_PORT(unit, port)) && 845 (!IS_LB_PORT(unit, port))) { 846 /* Reg valid only for front panel ports */ 847 COMPILER_64_ZERO(value); 848 compare_reg_value (unit, MMU_EBCTM_CNTR_0_STSr, port, 0, 849 value); 850 } 851 } 852 853 STATIC void 854 th3_check_mmu_port_pool_mems(int unit, int port) { 855 int mem_idx; 856 static const struct { 857 soc_mem_t mem; 858 soc_field_t field; 859 uint32 exp_value; 860 } mem_val_list[] = { 861 {MMU_WRED_PORT_SP_SHARED_COUNTm, SHARED_COUNTf, 0x0}, 862 {MMU_THDO_COUNTER_PORTSP_MCm, SHARED_COUNTf, 0x0}, 863 {INVALIDm, INVALIDf, 0x0} 864 }; 865 int mmu_chip_port = soc_th3_mmu_chip_port_num(unit, port); 866 int pool, portsp_idx; 867 uint64 value; 868 869 for (mem_idx = 0; mem_val_list[mem_idx].mem != INVALIDm; mem_idx++) { 870 for (pool = 0; pool < _TH3_MMU_NUM_POOL; pool++) { 871 portsp_idx = (mmu_chip_port * _TH3_MMU_NUM_POOL) + pool; 872 COMPILER_64_ZERO(value); 873 COMPILER_64_SET(value, 0x0, mem_val_list[mem_idx].exp_value); 874 memory_field_check(unit, mem_val_list[mem_idx].mem, portsp_idx, 875 mem_val_list[mem_idx].field, value, port, 0); 876 } 877 } 878 879 } 880 881 STATIC void 882 th3_check_mmu_port_queue_mems(int unit, int port) { 883 int mem_idx; 884 static const struct { 885 soc_mem_t mem; 886 soc_field_t field; 887 uint32 exp_value; 888 } mem_val_list[] = { 889 {MMU_WRED_UC_QUEUE_TOTAL_COUNTm, TOTAL_COUNTf, 0x0}, 890 {MMU_THDO_COUNTER_QUEUEm, TOTALCOUNTf, 0x0}, 891 {MMU_THDO_COUNTER_QUEUEm, SHARED_COUNTf, 0x0}, 892 {MMU_THDO_COUNTER_QUEUEm, MIN_COUNTf, 0x0}, 893 {INVALIDm, INVALIDf, 0x0} 894 }; 895 soc_info_t *si = &SOC_INFO(unit); 896 int q_loop, voq, num_queues; 897 uint64 value; 898 899 if (IS_CPU_PORT(unit, port)) { 900 num_queues = SOC_TH3_NUM_CPU_QUEUES; 901 } else { 902 num_queues = SOC_TH3_NUM_GP_QUEUES; 903 } 904 905 for (mem_idx = 0; mem_val_list[mem_idx].mem != INVALIDm; mem_idx++) { 906 for (q_loop = 0; q_loop < num_queues; q_loop++) { 907 voq = si->port_uc_cosq_base[port] + q_loop; 908 COMPILER_64_ZERO(value); 909 COMPILER_64_SET(value, 0x0, mem_val_list[mem_idx].exp_value); 910 memory_field_check(unit, mem_val_list[mem_idx].mem, voq, 911 mem_val_list[mem_idx].field, value, port, 0); 912 } 913 } 914 915 } 916 917 STATIC void 918 th3_check_mmu_port_mems(int unit, int port) { 919 int mem_idx; 920 static const struct { 921 soc_mem_t mem; 922 soc_field_t field; 923 uint32 exp_value; 924 } mem_val_list[] = { 925 {MMU_THDO_TOTAL_PORT_COUNTERm, TOTAL_COUNTf, 0x0}, 926 {MMU_THDO_TOTAL_PORT_COUNTER_MCm, TOTAL_COUNTf, 0x0}, 927 {MMU_THDO_TOTAL_PORT_COUNTER_MC_SHm, TOTAL_COUNTf, 0x0}, 928 {MMU_THDO_TOTAL_PORT_COUNTER_SHm, TOTAL_COUNTf, 0x0}, 929 {MMU_THDO_COUNTER_UC_QGROUPm, MIN_COUNTf, 0x0}, 930 {MMU_THDO_COUNTER_MC_QGROUPm, MIN_COUNTf, 0x0}, 931 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE0f, 0x0}, 932 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE1f, 0x0}, 933 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE2f, 0x0}, 934 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE3f, 0x0}, 935 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE4f, 0x0}, 936 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE5f, 0x0}, 937 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE6f, 0x0}, 938 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE7f, 0x0}, 939 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE8f, 0x0}, 940 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE9f, 0x0}, 941 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE10f, 0x0}, 942 {MMU_THDO_PORT_Q_DROP_STATEm, DS_QUEUE11f, 0x0}, 943 {MMU_THDO_PORT_Q_DROP_STATE_MCm, DS_QUEUE0f, 0x0}, 944 {MMU_THDO_PORT_Q_DROP_STATE_MCm, DS_QUEUE1f, 0x0}, 945 {MMU_THDO_PORT_Q_DROP_STATE_MCm, DS_QUEUE2f, 0x0}, 946 {MMU_THDO_PORT_Q_DROP_STATE_MCm, DS_QUEUE3f, 0x0}, 947 {MMU_THDO_PORT_Q_DROP_STATE_MCm, DS_QUEUE4f, 0x0}, 948 {MMU_THDO_PORT_Q_DROP_STATE_MCm, DS_QUEUE5f, 0x0}, 949 {MMU_THDO_PORT_SP_DROP_STATE_UCm,DATAf, 0x0}, 950 {MMU_THDO_PORT_SP_DROP_STATE_MCm,DATAf, 0x0}, 951 {MMU_THDO_COUNTER_PORT_UCm, SP0_SHARED_COUNTf, 0x0}, 952 {MMU_THDO_COUNTER_PORT_UCm, SP1_SHARED_COUNTf, 0x0}, 953 {MMU_THDO_COUNTER_PORT_UCm, SP2_SHARED_COUNTf, 0x0}, 954 {MMU_THDO_COUNTER_PORT_UCm, SP3_SHARED_COUNTf, 0x0}, 955 {MMU_THDO_COUNTER_PORT_UCm, SP0_TOTAL_COUNTf, 0x0}, 956 {MMU_THDO_COUNTER_PORT_UCm, SP1_TOTAL_COUNTf, 0x0}, 957 {MMU_THDO_COUNTER_PORT_UCm, SP2_TOTAL_COUNTf, 0x0}, 958 {MMU_THDO_COUNTER_PORT_UCm, SP3_TOTAL_COUNTf, 0x0}, 959 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG0_MIN_COUNTf, 0x0}, 960 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG1_MIN_COUNTf, 0x0}, 961 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG2_MIN_COUNTf, 0x0}, 962 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG3_MIN_COUNTf, 0x0}, 963 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG4_MIN_COUNTf, 0x0}, 964 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG5_MIN_COUNTf, 0x0}, 965 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG6_MIN_COUNTf, 0x0}, 966 {MMU_THDI_PORT_PG_MIN_COUNTERm, PG7_MIN_COUNTf, 0x0}, 967 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG0_SHARED_COUNTf, 0x0}, 968 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG1_SHARED_COUNTf, 0x0}, 969 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG2_SHARED_COUNTf, 0x0}, 970 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG3_SHARED_COUNTf, 0x0}, 971 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG4_SHARED_COUNTf, 0x0}, 972 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG5_SHARED_COUNTf, 0x0}, 973 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG6_SHARED_COUNTf, 0x0}, 974 {MMU_THDI_PORT_PG_SHARED_COUNTERm, PG7_SHARED_COUNTf, 0x0}, 975 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG0_HDRM_COUNTf, 0x0}, 976 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG1_HDRM_COUNTf, 0x0}, 977 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG2_HDRM_COUNTf, 0x0}, 978 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG3_HDRM_COUNTf, 0x0}, 979 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG4_HDRM_COUNTf, 0x0}, 980 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG5_HDRM_COUNTf, 0x0}, 981 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG6_HDRM_COUNTf, 0x0}, 982 {MMU_THDI_PORT_PG_HDRM_COUNTERm, PG7_HDRM_COUNTf, 0x0}, 983 {MMU_THDI_PORTSP_COUNTERm, PORTSP0_MIN_COUNTf, 0x0}, 984 {MMU_THDI_PORTSP_COUNTERm, PORTSP1_MIN_COUNTf, 0x0}, 985 {MMU_THDI_PORTSP_COUNTERm, PORTSP2_MIN_COUNTf, 0x0}, 986 {MMU_THDI_PORTSP_COUNTERm, PORTSP3_MIN_COUNTf, 0x0}, 987 {MMU_THDI_PORTSP_COUNTERm, PORTSP0_SHARED_COUNTf, 0x0}, 988 {MMU_THDI_PORTSP_COUNTERm, PORTSP1_SHARED_COUNTf, 0x0}, 989 {MMU_THDI_PORTSP_COUNTERm, PORTSP2_SHARED_COUNTf, 0x0}, 990 {MMU_THDI_PORTSP_COUNTERm, PORTSP3_SHARED_COUNTf, 0x0}, 991 {INVALIDm, INVALIDf, 0x0} 992 }; 993 uint64 value; 994 995 for (mem_idx = 0; mem_val_list[mem_idx].mem != INVALIDm; mem_idx++) { 996 COMPILER_64_ZERO(value); 997 COMPILER_64_SET(value, 0x0, mem_val_list[mem_idx].exp_value); 998 memory_field_check(unit, mem_val_list[mem_idx].mem, port, 999 mem_val_list[mem_idx].field, value, port, 1); 1000 } 1001 1002 th3_check_mmu_port_pool_mems(unit, port); 1003 th3_check_mmu_port_queue_mems(unit, port); 1004 1005 } 1006 1007 static const struct _soc_th3_port_ep_mmu_request_s { 1008 int port_speed; 1009 /*EP - MMU requests */ 1010 int ep_mmu_req; 1011 /*EP - MMU PFC optimized setting */ 1012 int ep_mmu_pfc_opt; 1013 } _soc_th3_req_grant_tbl[_TH3_SPEED_TYPES] = { 1014 /* port_speed general optimized settings*/ 1015 { 10000, 8, 7}, /* 10GE */ 1016 { 25000, 15, 11}, /* 25GE */ 1017 { 40000, 20, 14}, /* 40GE */ 1018 { 50000, 28, 20}, /* 50GE */ 1019 {100000, 57, 42}, /* 100GE */ 1020 {200000, 100, 71}, /* 200GE */ 1021 {400000, 142, 110}, /* 400GE */ 1022 }; 1023 1024 STATIC void 1025 th3_check_req_grant_per_port(int unit, int port) { 1026 int i; 1027 int phy_port; 1028 uint32 ep_mmu_req, port_ep_req = -1; 1029 uint32 mmu_credit, ep_credit; 1030 soc_info_t *si = &SOC_INFO(unit); 1031 uint32 read_entry[SOC_MAX_MEM_WORDS]; 1032 soc_reg_t reg; 1033 uint64 rval; 1034 uint32 rval_1 = 0; 1035 int speed_tbl_index = -1, port_speed = -1; 1036 int exp_port_ep_credit = 0, exp_ep_mmu_credit = 0; 1037 int num_lanes = si->port_num_lanes[port]; 1038 int core_freq, dpr_freq; 1039 1040 COMPILER_64_ZERO(rval); 1041 1042 phy_port = si->port_l2p_mapping[port]; 1043 port_speed = si->port_speed_max[port]; 1044 1045 dpr_freq = soc_property_get(unit, spn_DPR_CLOCK_FREQUENCY, -1); 1046 core_freq = soc_property_get(unit, spn_CORE_CLOCK_FREQUENCY, -1); 1047 for (i = 0; i < _TH3_SPEED_TYPES; i++) { 1048 if (_soc_th3_req_grant_tbl[i].port_speed == port_speed) { 1049 speed_tbl_index = i; 1050 break; 1051 } 1052 } 1053 if ((!IS_CPU_PORT(unit, port)) && (!IS_LB_PORT(unit, port))) { 1054 if (IS_MANAGEMENT_PORT(unit, port)) { 1055 reg = XLMAC_TXFIFO_CELL_REQ_CNTr; 1056 exp_port_ep_credit = 8; 1057 } else { 1058 reg = CDMAC_TXFIFO_CELL_REQ_CNTr; 1059 exp_port_ep_credit = num_lanes * 16; 1060 } 1061 if (speed_tbl_index != -1) { 1062 if ((core_freq == 1325) && (dpr_freq == 1000)) { 1063 /* PFC optimized mode settings */ 1064 exp_ep_mmu_credit = 1065 _soc_th3_req_grant_tbl[speed_tbl_index].ep_mmu_pfc_opt; 1066 } else { 1067 exp_ep_mmu_credit = 1068 _soc_th3_req_grant_tbl[speed_tbl_index].ep_mmu_req; 1069 } 1070 } 1071 /* coverity[checked_return:FALSE]*/ 1072 soc_reg_get(unit, reg, port, REG_PORT_ANY, &rval); 1073 /* coverity[checked_return:FALSE]*/ 1074 port_ep_req = soc_reg64_field32_get(unit, reg, rval, REQ_CNTf); 1075 /* coverity[checked_return:FALSE]*/ 1076 soc_mem_read(unit, EGR_PORT_REQUESTSm, MEM_BLOCK_ANY, phy_port, read_entry); 1077 /* coverity[checked_return:FALSE]*/ 1078 ep_credit = soc_mem_field32_get(unit, EGR_PORT_REQUESTSm, read_entry, 1079 OUTSTANDING_PORT_REQUESTSf); 1080 if (ep_credit != port_ep_req) { 1081 cli_out("ERROR: Mac to EP request credit mismatch for port:%d Mac" 1082 "requests:%d EP credit:%d\n", port, port_ep_req, ep_credit); 1083 } else if (ep_credit == 0 && port_ep_req == 0) { 1084 cli_out("WARNING: MAc to EP requests credit 0 for port: %d" 1085 " Please check if port is up\n", port); 1086 } else if (ep_credit != exp_port_ep_credit) { 1087 cli_out("ERROR: Mac to EP request credit not right for speed" 1088 " port:%d speed:%d Mbps Mac requests:%d Expected:%d\n", 1089 port, port_speed, ep_credit, exp_port_ep_credit); 1090 } 1091 } 1092 /* coverity[checked_return:FALSE]*/ 1093 soc_reg32_get(unit, MMU_EBPTS_EDB_CREDIT_COUNTERr, port, REG_PORT_ANY, 1094 &rval_1); 1095 /* coverity[checked_return:FALSE]*/ 1096 mmu_credit = soc_reg_field_get(unit, MMU_EBPTS_EDB_CREDIT_COUNTERr, rval_1, 1097 NUM_EDB_CREDITSf); 1098 /* coverity[checked_return:FALSE]*/ 1099 soc_mem_read(unit, EGR_MMU_REQUESTSm, MEM_BLOCK_ANY, phy_port, read_entry); 1100 /* coverity[checked_return:FALSE]*/ 1101 ep_mmu_req = soc_mem_field32_get(unit, EGR_MMU_REQUESTSm, read_entry, 1102 OUTSTANDING_MMU_REQUESTSf); 1103 if (mmu_credit != ep_mmu_req) { 1104 cli_out("ERROR: EP to MMU request credit mismatch for port:%d EP" 1105 "requests:%d MMU credit:%d\n", port, ep_mmu_req, mmu_credit); 1106 } else if (ep_mmu_req != exp_ep_mmu_credit) { 1107 if ((!IS_CPU_PORT(unit, port)) && (!IS_LB_PORT(unit, port)) && 1108 port_ep_req != 0) { 1109 /*Do the check if port to Ep requests are non-zero for Front 1110 * panel port*/ 1111 cli_out("ERROR: EP to MMU request credit not right for speed" 1112 " port:%d speed:%d Mbps EP requests:%d Expected:%d\n", 1113 port, port_speed, ep_mmu_req, exp_ep_mmu_credit); 1114 } 1115 } 1116 } 1117 1118 STATIC void 1119 th3_check_port_health(int unit, int port) { 1120 th3_check_mmu_port_regs(unit, port); 1121 th3_check_mmu_port_mems(unit, port); 1122 th3_check_req_grant_per_port(unit, port); 1123 if ((!IS_MANAGEMENT_PORT(unit, port)) && 1124 (!IS_CPU_PORT(unit, port)) && 1125 (!IS_LB_PORT(unit, port))) { 1126 th3_check_idb_port_regs(unit, port); 1127 } 1128 } 1129 1130 STATIC void 1131 th3_check_health(int unit) { 1132 int itm, pipe; 1133 soc_info_t *si = &SOC_INFO(unit); 1134 uint32 itm_map = si->itm_map; 1135 th3_check_global_health_regs(unit); 1136 1137 for (itm = 0; itm < NUM_ITM(unit); itm++) { 1138 if (itm_map & (1 << itm)) { 1139 th3_check_per_itm_health_regs(unit, itm); 1140 } 1141 } 1142 1143 for (pipe = 0; pipe < _TH3_PIPES_PER_DEV; pipe++) { 1144 if (!SOC_PBMP_IS_NULL(si->pipe_pbm[pipe])) { 1145 th3_check_per_pipe_health_regs(unit, pipe); 1146 } 1147 } 1148 } 1149 1150 STATIC int 1151 th3_check_idb_drops(int unit, int port) { 1152 #define UINT64_HEXA_STR_MAX_SIZE 20 1153 soc_ctr_control_info_t ctrl_info; 1154 soc_reg_t ctr_reg; 1155 uint64 value, zero; 1156 int sync = 0; /*sync mode should be 0 for OBM counters*/ 1157 char tmp[UINT64_HEXA_STR_MAX_SIZE]; 1158 COMPILER_64_ZERO(zero); 1159 1160 ctrl_info.instance_type = SOC_CTR_INSTANCE_TYPE_PORT; 1161 ctrl_info.instance = port; 1162 1163 /*OBM lossy hi drops*/ 1164 COMPILER_64_ZERO(value); 1165 ctr_reg = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI; 1166 SOC_IF_ERROR_RETURN(soc_counter_generic_get(unit, ctr_reg, ctrl_info, sync, 1167 0, &value)); 1168 _shr_format_uint64_hexa_string (value, tmp); 1169 if (!COMPILER_64_EQ(zero, value)) { 1170 LOG_CLI((BSL_META_U(unit, 1171 "Non-zero Lossy hi IDB drops found for port :%d, pkt drop count : " 1172 "%s\n"), port, tmp)); 1173 } 1174 1175 /*OBM lossy lo drops*/ 1176 COMPILER_64_ZERO(value); 1177 ctr_reg = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO; 1178 SOC_IF_ERROR_RETURN( 1179 soc_counter_generic_get(unit, ctr_reg, ctrl_info, sync, 1180 0, &value)); 1181 _shr_format_uint64_hexa_string (value, tmp); 1182 if (!COMPILER_64_EQ(zero, value)) { 1183 LOG_CLI((BSL_META_U(unit, 1184 "Non-zero Lossy lo IDB drops found for port :%d, pkt drop count : " 1185 "%s\n"), port, tmp)); 1186 } 1187 1188 /*OBM lossless0 drops*/ 1189 COMPILER_64_ZERO(value); 1190 ctr_reg = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0; 1191 SOC_IF_ERROR_RETURN(soc_counter_generic_get(unit, ctr_reg, ctrl_info, sync, 1192 0, &value)); 1193 _shr_format_uint64_hexa_string (value, tmp); 1194 if (!COMPILER_64_EQ(zero, value)) { 1195 LOG_CLI((BSL_META_U(unit, 1196 "Non-zero Lossless 0 IDB drops found for port :%d, pkt drop count : " 1197 "%s \n"), port, tmp)); 1198 } 1199 1200 /*OBM lossless1 drops*/ 1201 COMPILER_64_ZERO(value); 1202 ctr_reg = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1; 1203 SOC_IF_ERROR_RETURN( 1204 soc_counter_generic_get(unit, ctr_reg, ctrl_info, sync, 1205 0, &value)); 1206 _shr_format_uint64_hexa_string (value, tmp); 1207 if (!COMPILER_64_EQ(zero, value)) { 1208 LOG_CLI((BSL_META_U(unit, 1209 "Non-zero Lossless 1 IDB drops found for port :%d, pkt drop count : " 1210 "%s \n"), port, tmp)); 1211 } 1212 #undef UINT64_HEXA_STR_MAX_SIZE 1213 return SOC_E_NONE; 1214 } 1215 1216 STATIC int 1217 th3_check_mmu_per_port_drops(int unit, int port) { 1218 #define UINT64_HEXA_STR_MAX_SIZE 20 1219 soc_ctr_control_info_t ctrl_info; 1220 soc_reg_t ctr_reg, ctr_reg_yel, ctr_reg_red; 1221 int sync = 0; 1222 uint64 value, red_drop, yel_drop, zero; 1223 char tmp[UINT64_HEXA_STR_MAX_SIZE], tmp_yel[UINT64_HEXA_STR_MAX_SIZE], 1224 tmp_red[UINT64_HEXA_STR_MAX_SIZE]; 1225 int cosq; 1226 soc_info_t *si = &SOC_INFO(unit); 1227 COMPILER_64_ZERO(zero); 1228 1229 /* Source port dropped packets*/ 1230 COMPILER_64_ZERO(value); 1231 ctr_reg = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING; 1232 ctrl_info.instance_type = SOC_CTR_INSTANCE_TYPE_ITM; 1233 ctrl_info.instance = port; 1234 SOC_IF_ERROR_RETURN 1235 (soc_counter_generic_get(unit, ctr_reg, 1236 ctrl_info, sync, -1, &value)); 1237 _shr_format_uint64_hexa_string (value, tmp); 1238 if (!COMPILER_64_EQ(zero, value)) { 1239 LOG_CLI((BSL_META_U(unit, 1240 "Non-zero Ingress admission drops found for source port :%d," 1241 " pkt drop count : %s \n"), port, tmp)); 1242 } 1243 1244 /*UC Egress Admission drops*/ 1245 ctr_reg = SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC; 1246 ctr_reg_yel = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW_UC; 1247 ctr_reg_red = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED_UC; 1248 ctrl_info.instance_type = SOC_CTR_INSTANCE_TYPE_ITM; 1249 ctrl_info.instance = port; 1250 for (cosq = 0; cosq < si->port_num_uc_cosq[port] ; cosq++) { 1251 COMPILER_64_ZERO(value); 1252 SOC_IF_ERROR_RETURN 1253 (soc_counter_generic_get(unit, ctr_reg, 1254 ctrl_info, sync, cosq, &value)); 1255 _shr_format_uint64_hexa_string (value, tmp); 1256 if (!COMPILER_64_EQ(zero, value)) { 1257 LOG_CLI((BSL_META_U(unit, 1258 "Non-zero Egress admission drops found for port :%d," 1259 " UC cos: %d, pkt drop count : %s \n"), port, cosq, tmp)); 1260 } 1261 } 1262 COMPILER_64_ZERO(red_drop); 1263 SOC_IF_ERROR_RETURN 1264 (soc_counter_generic_get(unit, ctr_reg_red, 1265 ctrl_info, sync, 0, &red_drop)); 1266 _shr_format_uint64_hexa_string (red_drop, tmp_red); 1267 if (!COMPILER_64_EQ(zero, red_drop)) { 1268 LOG_CLI((BSL_META_U(unit, 1269 "Non-zero Red Egress admission UC drops found for port :%d," 1270 " pkt drop count : %s \n"), port, tmp_red)); 1271 } 1272 COMPILER_64_ZERO(yel_drop); 1273 SOC_IF_ERROR_RETURN 1274 (soc_counter_generic_get(unit, ctr_reg_yel, 1275 ctrl_info, sync, 0, &yel_drop)); 1276 _shr_format_uint64_hexa_string (yel_drop, tmp_yel); 1277 if (!COMPILER_64_EQ(zero, yel_drop)) { 1278 LOG_CLI((BSL_META_U(unit, 1279 "Non-zero Yellow Egress admission UC drops found for port :%d," 1280 " pkt drop count : %s \n"), port, tmp_yel)); 1281 } 1282 1283 /*MC Egress Admission drops*/ 1284 ctr_reg = SOC_COUNTER_NON_DMA_COSQ_DROP_PKT; 1285 ctr_reg_yel = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW; 1286 ctr_reg_red = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED; 1287 ctrl_info.instance_type = SOC_CTR_INSTANCE_TYPE_ITM; 1288 ctrl_info.instance = port; 1289 for (cosq = 0; cosq < si->port_num_cosq[port] ; cosq++) { 1290 COMPILER_64_ZERO(value); 1291 SOC_IF_ERROR_RETURN 1292 (soc_counter_generic_get(unit, ctr_reg, 1293 ctrl_info, sync, cosq, &value)); 1294 _shr_format_uint64_hexa_string (value, tmp); 1295 if (!COMPILER_64_EQ(zero, value)) { 1296 LOG_CLI((BSL_META_U(unit, 1297 "Non-zero Egress admission drops found for port :%d," 1298 " MC cos: %d, Total pkt drop count : %s \n"), port, cosq, tmp)); 1299 } 1300 } 1301 COMPILER_64_ZERO(red_drop); 1302 SOC_IF_ERROR_RETURN 1303 (soc_counter_generic_get(unit, ctr_reg_red, 1304 ctrl_info, sync, 0, &red_drop)); 1305 _shr_format_uint64_hexa_string (red_drop, tmp_red); 1306 if (!COMPILER_64_EQ(zero, red_drop)) { 1307 LOG_CLI((BSL_META_U(unit, 1308 "Non-zero Red Egress admission MC drops found for port :%d," 1309 " pkt drop count : %s \n"), port, tmp_red)); 1310 } 1311 COMPILER_64_ZERO(yel_drop); 1312 SOC_IF_ERROR_RETURN 1313 (soc_counter_generic_get(unit, ctr_reg_yel, 1314 ctrl_info, sync, 0, &yel_drop)); 1315 _shr_format_uint64_hexa_string (yel_drop, tmp_yel); 1316 if (!COMPILER_64_EQ(zero, yel_drop)) { 1317 LOG_CLI((BSL_META_U(unit, 1318 "Non-zero Yellow Egress admission MC drops found for port :%d," 1319 " pkt drop count : %s \n"), port, tmp_yel)); 1320 } 1321 1322 /*WRED drops*/ 1323 ctr_reg = SOC_COUNTER_NON_DMA_COSQ_DROP_WRED_PKT; 1324 ctr_reg_yel = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW; 1325 ctr_reg_red = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED; 1326 ctrl_info.instance_type = SOC_CTR_INSTANCE_TYPE_ITM; 1327 ctrl_info.instance = port; 1328 for (cosq = 0; cosq < si->port_num_uc_cosq[port] ; cosq++) { 1329 COMPILER_64_ZERO(value); 1330 SOC_IF_ERROR_RETURN 1331 (soc_counter_generic_get(unit, ctr_reg, 1332 ctrl_info, sync, cosq, &value)); 1333 _shr_format_uint64_hexa_string (value, tmp); 1334 if (!COMPILER_64_EQ(zero, value)) { 1335 LOG_CLI((BSL_META_U(unit, 1336 "Non-zero WRED drops found for port :%d," 1337 " UC cos: %d, Total pkt drop count : %s \n"), port, cosq, tmp)); 1338 } 1339 } 1340 COMPILER_64_ZERO(red_drop); 1341 SOC_IF_ERROR_RETURN 1342 (soc_counter_generic_get(unit, ctr_reg_red, 1343 ctrl_info, sync, 0, &red_drop)); 1344 _shr_format_uint64_hexa_string (red_drop, tmp_red); 1345 if (!COMPILER_64_EQ(zero, red_drop)) { 1346 LOG_CLI((BSL_META_U(unit, 1347 "Non-zero Red Egress admission MC drops found for port :%d," 1348 " pkt drop count : %s \n"), port, tmp_red)); 1349 } 1350 COMPILER_64_ZERO(yel_drop); 1351 SOC_IF_ERROR_RETURN 1352 (soc_counter_generic_get(unit, ctr_reg_yel, 1353 ctrl_info, sync, 0, &yel_drop)); 1354 _shr_format_uint64_hexa_string (yel_drop, tmp_yel); 1355 if (!COMPILER_64_EQ(zero, yel_drop)) { 1356 LOG_CLI((BSL_META_U(unit, 1357 "Non-zero Yellow Egress admission MC drops found for port :%d," 1358 " pkt drop count : %s \n"), port, tmp_yel)); 1359 } 1360 1361 #undef UINT64_HEXA_STR_MAX_SIZE 1362 return SOC_E_NONE; 1363 } 1364 1365 STATIC int 1366 th3_check_mmu_global_drops(int unit) { 1367 #define UINT64_HEXA_STR_MAX_SIZE 20 1368 soc_ctr_control_info_t ctrl_info; 1369 soc_reg_t ctr_reg, ctr_reg_yel, ctr_reg_red; 1370 int sync = 0; 1371 soc_info_t *si = &SOC_INFO(unit); 1372 uint32 itm_map = si->itm_map; 1373 uint64 value64, sum, red_drop, yel_drop, zero; 1374 int itm, hdrm_pool_id, rqe_q_id; 1375 char tmp[UINT64_HEXA_STR_MAX_SIZE], tmp_gr[UINT64_HEXA_STR_MAX_SIZE], 1376 tmp_yel[UINT64_HEXA_STR_MAX_SIZE], tmp_red[UINT64_HEXA_STR_MAX_SIZE]; 1377 COMPILER_64_ZERO(zero); 1378 1379 /* Headroom pool drops*/ 1380 ctrl_info.instance_type = SOC_CTR_INSTANCE_TYPE_ITM; 1381 ctr_reg = SOC_COUNTER_NON_DMA_HDRM_POOL_DROP_PKT; 1382 for (hdrm_pool_id = 0; hdrm_pool_id < _TH3_MMU_NUM_POOL; hdrm_pool_id++) { 1383 COMPILER_64_ZERO(value64); 1384 ctrl_info.instance = 0; 1385 SOC_IF_ERROR_RETURN 1386 (soc_counter_generic_get(unit, ctr_reg, 1387 ctrl_info, sync, hdrm_pool_id, &value64)); 1388 _shr_format_uint64_hexa_string (value64, tmp); 1389 if (!COMPILER_64_EQ(zero, value64)) { 1390 LOG_CLI((BSL_META_U(unit, 1391 "Non-zero Headroom Pool drops found for pool :%d," 1392 " pkt drop count : %s \n"), hdrm_pool_id, tmp)); 1393 } 1394 } 1395 1396 /*RQE drops*/ 1397 ctr_reg = SOC_COUNTER_NON_DMA_PRIQ_DROP_PKT; 1398 ctr_reg_yel = SOC_COUNTER_NON_DMA_PRIQ_DROP_PKT_YELLOW; 1399 ctr_reg_red = SOC_COUNTER_NON_DMA_PRIQ_DROP_PKT_RED; 1400 ctrl_info.instance_type = SOC_CTR_INSTANCE_TYPE_ITM; 1401 for (rqe_q_id = 0; rqe_q_id < _TH3_MMU_NUM_RQE_QUEUES; rqe_q_id++) { 1402 COMPILER_64_ZERO(value64); 1403 COMPILER_64_ZERO(red_drop); 1404 COMPILER_64_ZERO(yel_drop); 1405 ctrl_info.instance = 0; 1406 SOC_IF_ERROR_RETURN 1407 (soc_counter_generic_get(unit, ctr_reg, 1408 ctrl_info, sync, rqe_q_id, &value64)); 1409 SOC_IF_ERROR_RETURN 1410 (soc_counter_generic_get(unit, ctr_reg_yel, 1411 ctrl_info, sync, rqe_q_id, &yel_drop)); 1412 SOC_IF_ERROR_RETURN 1413 (soc_counter_generic_get(unit, ctr_reg_red, 1414 ctrl_info, sync, rqe_q_id, &red_drop)); 1415 COMPILER_64_ZERO(sum); 1416 COMPILER_64_ADD_64(sum, value64); 1417 COMPILER_64_SUB_64(sum, yel_drop); 1418 COMPILER_64_SUB_64(sum, red_drop); 1419 _shr_format_uint64_hexa_string (value64, tmp); 1420 _shr_format_uint64_hexa_string (yel_drop, tmp_yel); 1421 _shr_format_uint64_hexa_string (red_drop, tmp_red); 1422 _shr_format_uint64_hexa_string (sum, tmp_gr); 1423 if (!COMPILER_64_EQ(zero, value64)) { 1424 LOG_CLI((BSL_META_U(unit, 1425 "Non-zero RQE queue drops found for queue :%d, " 1426 "Total pkt drop count: %s \n"), rqe_q_id, tmp)); 1427 LOG_CLI((BSL_META_U(unit, 1428 "Color drops green : %s, yellow: %s, red: %s \n"), 1429 tmp_gr, tmp_red, tmp_yel)); 1430 } 1431 } 1432 1433 /*CRB drops*/ 1434 for (itm = 0; itm < NUM_ITM(unit); itm++) { 1435 if (itm_map & (1 << itm)) { 1436 COMPILER_64_ZERO(sum); 1437 COMPILER_64_ZERO(value64); 1438 SOC_IF_ERROR_RETURN( 1439 soc_reg_get(unit, MMU_CRB_PKT_DROP_CNTR_STATr, itm, 0, &value64)); 1440 COMPILER_64_ADD_64(sum, value64); 1441 SOC_IF_ERROR_RETURN( 1442 soc_reg_get(unit, MMU_CRB_INVALID_DESTINATION_PKT_COUNTr, itm, 0, &value64)); 1443 COMPILER_64_ADD_64(sum, value64); 1444 if (!COMPILER_64_EQ(zero, sum)) { 1445 _shr_format_uint64_hexa_string (sum, tmp); 1446 LOG_CLI((BSL_META_U(unit, 1447 "Non-zero drops found for itm: %d due to invalid destination" 1448 "port from IP, pkt drop count : %s\n"), itm, tmp)); 1449 } 1450 } 1451 } 1452 1453 #undef UINT64_HEXA_STR_MAX_SIZE 1454 return SOC_E_NONE; 1455 } 1456 1457 cmd_result_t 1458 cmd_check_tm_settings(int unit, args_t *arg) 1459 { 1460 char *subcmd, *component, *sub_comp; 1461 int port; 1462 int rv = 0; 1463 pbmp_t pbm; 1464 soc_info_t *si = &SOC_INFO(unit); 1465 1466 subcmd = ARG_GET(arg); 1467 component = ARG_GET(arg); 1468 if (subcmd == NULL) { 1469 return CMD_USAGE; 1470 } 1471 1472 if (!sal_strcasecmp(subcmd, "idb")) { 1473 if (!sal_strcasecmp(component, "portmap")) { 1474 soc_th3_check_idb_portmap(unit); 1475 } else if (!sal_strcasecmp(component, "drops")) { 1476 sub_comp = ARG_GET(arg); 1477 if(sub_comp == NULL) { 1478 PBMP_E_ITER(unit, port) { 1479 if (!SOC_PBMP_MEMBER(si->management_pbm, port)) { 1480 rv = th3_check_idb_drops(unit, port); 1481 if (rv < 0) { 1482 return CMD_FAIL; 1483 } 1484 } 1485 } 1486 } else { 1487 if (parse_bcm_pbmp(unit, sub_comp, &pbm) < 0) { 1488 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1489 ARG_CMD(arg), sub_comp); 1490 return CMD_FAIL; 1491 } 1492 if (BCM_PBMP_IS_NULL(pbm)) { 1493 ARG_DISCARD(arg); 1494 return CMD_OK; 1495 } 1496 SOC_PBMP_ITER(pbm, port) { 1497 if (IS_CPU_PORT(unit, port) || IS_LB_PORT(unit, port) || 1498 (SOC_PBMP_MEMBER(si->management_pbm, port))) { 1499 cli_out ("Port :%d not valid for IDB drops \n", port); 1500 } else { 1501 rv = th3_check_idb_drops(unit, port); 1502 if (rv < 0) { 1503 return CMD_FAIL; 1504 } 1505 } 1506 } 1507 } 1508 } else { 1509 return CMD_USAGE; 1510 } 1511 } else if (!sal_strcasecmp(subcmd, "mmu")) { 1512 if (!sal_strcasecmp(component, "portmap")) { 1513 soc_th3_check_mmu_portmap(unit); 1514 } else if (!sal_strcasecmp(component, "drops")) { 1515 sub_comp = ARG_GET(arg); 1516 rv = th3_check_mmu_global_drops(unit); 1517 if (rv < 0) { 1518 return CMD_FAIL; 1519 } 1520 1521 if(sub_comp == NULL) { 1522 PBMP_ALL_ITER(unit, port) { 1523 rv = th3_check_mmu_per_port_drops(unit, port); 1524 if (rv < 0) { 1525 return CMD_FAIL; 1526 } 1527 } 1528 } else { 1529 if (parse_bcm_pbmp(unit, sub_comp, &pbm) < 0) { 1530 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1531 ARG_CMD(arg), sub_comp); 1532 return CMD_FAIL; 1533 } 1534 if (BCM_PBMP_IS_NULL(pbm)) { 1535 ARG_DISCARD(arg); 1536 return CMD_OK; 1537 } 1538 SOC_PBMP_ITER(pbm, port) { 1539 rv = th3_check_mmu_per_port_drops(unit, port); 1540 if (rv < 0) { 1541 return CMD_FAIL; 1542 } 1543 } 1544 } 1545 1546 } else if (!sal_strcasecmp(component, "scheduler")) { 1547 sub_comp = ARG_GET(arg); 1548 if (sub_comp == NULL) { 1549 PBMP_ALL_ITER(unit, port) { 1550 rv = soc_tomahawk3_schduler_hier_show(unit, port); 1551 if (rv < 0) { 1552 return CMD_FAIL; 1553 } 1554 } 1555 } else { 1556 if (parse_bcm_pbmp(unit, sub_comp, &pbm) < 0) { 1557 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1558 ARG_CMD(arg), sub_comp); 1559 return CMD_FAIL; 1560 } 1561 if (BCM_PBMP_IS_NULL(pbm)) { 1562 ARG_DISCARD(arg); 1563 return CMD_OK; 1564 } 1565 SOC_PBMP_ITER(pbm, port) { 1566 rv = soc_tomahawk3_schduler_hier_show(unit, port); 1567 if (rv < 0) { 1568 return CMD_FAIL; 1569 } 1570 } 1571 } 1572 } else { 1573 return CMD_USAGE; 1574 } 1575 } else if (!sal_strcasecmp(subcmd, "settings")) { 1576 /*Expect file name as seconf argument*/ 1577 if (component == NULL) { 1578 cli_out("%s: ERROR: missing file name\n", ARG_CMD(arg)); 1579 return CMD_USAGE; 1580 } 1581 1582 th3_check_settings_from_file(unit, component); 1583 1584 } else if (!sal_strcasecmp(subcmd, "health")) { 1585 if (component == NULL ) { 1586 th3_check_health(unit); 1587 PBMP_ALL_ITER(unit, port) { 1588 th3_check_port_health(unit, port); 1589 } 1590 } else { 1591 if (parse_bcm_pbmp(unit, component, &pbm) < 0) { 1592 cli_out("%s: Error: unrecognized port bitmap: %s\n", 1593 ARG_CMD(arg), component); 1594 return CMD_FAIL; 1595 } 1596 if (BCM_PBMP_IS_NULL(pbm)) { 1597 ARG_DISCARD(arg); 1598 return CMD_OK; 1599 } 1600 SOC_PBMP_ITER(pbm, port) { 1601 if (SOC_PORT_VALID(unit, port)) { 1602 th3_check_port_health(unit, port); 1603 } 1604 } 1605 } 1606 } else { 1607 return CMD_USAGE; 1608 } 1609 1610 return CMD_OK; 1611 } 1612 1613 #endif /* BCM_TOMAHAWK3_SUPPORT */