celldata.c (73875B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: celldata.c 8 * Purpose: Diagnostic helper routines 9 * Notes: Perform various MCU DDR tuning tasks on Easyrider. 10 */ 11 12 #ifndef NO_MEMTUNE 13 14 #include <soc/defs.h> 15 #include <shared/bsl.h> 16 #if defined(BCM_TRIUMPH_SUPPORT) 17 #include <soc/triumph.h> 18 #include <soc/error.h> 19 #include <soc/mem.h> 20 #include <soc/er_tcam.h> 21 #include <soc/memtune.h> 22 23 #include <appl/diag/cmdlist.h> 24 #include <appl/diag/system.h> 25 #include <sal/appl/config.h> 26 27 #include <bcm/pkt.h> 28 #include <bcm/stack.h> 29 #include <bcm/tx.h> 30 #include <bcm/vlan.h> 31 32 /* 33 * convert hex string to multiple groups of 72-bit binary 34 * each 72-bit binary group is padded and stored in a 128-bit unit 35 * for multiple 72-bit group, LS bit is in highest offset unit 36 * for example: convert following 128-bit string to 144-bit binary 37 * hex: [0x]1234567890abcdef1357924680acebdf 38 * bin: 00000000 00000000 00123456 7890abcd 00000000 000000ef 13579246 80acebdf 39 */ 40 STATIC int 41 _extt_hex_to_72bit_unit_bin(char *hex_str, uint32 *bin_str, int num_unit) 42 { 43 int len, len_per_unit, len_per_word, unit_idx, word_idx, nibble_idx; 44 uint32 value; 45 char hex_nibble; 46 47 if (hex_str[0] == '0' && (hex_str[1] | 0x20) == 'x') { 48 hex_str += 2; 49 } 50 51 len = sal_strlen(hex_str); 52 for (unit_idx = num_unit - 1; unit_idx >= 0; unit_idx--) { 53 len_per_unit = len > 18 ? 18 : len; 54 len -= len_per_unit; 55 for (word_idx = 3; word_idx >= 0; word_idx--) { 56 len_per_word = len_per_unit > 8 ? 8 : len_per_unit; 57 len_per_unit -= len_per_word; 58 value = 0; 59 for (nibble_idx = 0; nibble_idx < len_per_word; nibble_idx++) { 60 value <<= 4; 61 hex_nibble = hex_str[len + len_per_unit + nibble_idx]; 62 if (hex_nibble >= '0' && hex_nibble <= '9') { 63 value |= hex_nibble - '0'; 64 } else { 65 hex_nibble |= 0x20; 66 if (hex_nibble >= 'a' && hex_nibble <= 'f') { 67 value |= hex_nibble - 'a' + 0x0a; 68 } else { 69 return CMD_FAIL; 70 } 71 } 72 } 73 bin_str[unit_idx * 4 + word_idx] = value; 74 } 75 } 76 77 return CMD_OK; 78 } 79 80 /* 81 * convert hex string to 2 groups of 18-bit binary 82 * each 18-bit binary group is padded and stored in a 32-bit unit 83 * hex: [0x]123456789 84 * hi_18-bit: 000048d1 85 * lo_18-bit: 00016789 86 */ 87 STATIC int 88 _extt_hex_to_18bit_unit_bin(char *hex_str, uint32 *lo_18bit, uint32 *hi_18bit) 89 { 90 int len, len_per_word, word_idx, nibble_idx; 91 uint32 value, bin_str[2]; 92 char hex_nibble; 93 94 if (hex_str[0] == '0' && (hex_str[1] | 0x20) == 'x') { 95 hex_str += 2; 96 } 97 98 len = sal_strlen(hex_str); 99 for (word_idx = 1; word_idx >= 0; word_idx--) { 100 len_per_word = len > 8 ? 8 : len; 101 len -= len_per_word; 102 value = 0; 103 for (nibble_idx = 0; nibble_idx < len_per_word; nibble_idx++) { 104 value <<= 4; 105 hex_nibble = hex_str[len + nibble_idx]; 106 if (hex_nibble >= '0' && hex_nibble <= '9') { 107 value |= hex_nibble - '0'; 108 } else { 109 hex_nibble |= 0x20; 110 if (hex_nibble >= 'a' && hex_nibble <= 'f') { 111 value |= hex_nibble - 'a' + 0x0a; 112 } else { 113 return CMD_FAIL; 114 } 115 } 116 } 117 bin_str[word_idx] = value; 118 } 119 120 *hi_18bit = ((bin_str[0] & 0xf) << 14) | ((bin_str[1] & 0xfffc0000) >> 18); 121 *lo_18bit = bin_str[1] & 0x3ffff; 122 123 return CMD_OK; 124 } 125 126 #if defined(INCLUDE_L3) && defined(BCM_FIELD_SUPPORT) 127 STATIC void 128 _extt_do_checksum(unsigned char *stream, int length, int checksumOffset) 129 { 130 unsigned short value; 131 unsigned long checksum; 132 int i; 133 134 checksum = 0; 135 for (i = 0; i < length; i += 2) { 136 value = stream[i]; 137 if (i + 1 < length) { 138 value |= stream[i + 1] << 8; 139 } 140 if (i == checksumOffset) { 141 value = 0; 142 } 143 checksum += value; 144 } 145 checksum = (checksum & 0xffff) + (checksum >> 16); 146 checksum ^= 0xffff; 147 148 stream[checksumOffset] = checksum & 0xff; 149 stream[checksumOffset + 1] = (checksum >> 8) & 0xff; 150 } 151 #endif /* INCLUDE_L3 && BCM_FIELD_SUPPORT */ 152 153 STATIC int 154 _extt_l3_activities(int unit, int enable, int num_ge_pkt, int num_xe_pkt) 155 { 156 #if defined(INCLUDE_L3) && defined(BCM_FIELD_SUPPORT) 157 static int l3_activities_running = FALSE; 158 bcm_vlan_t vid = 2; 159 bcm_mac_t router_mac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}; 160 bcm_mac_t mac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 161 bcm_if_t intf_id = 10; 162 int pkt_size = 64; 163 pbmp_t pbmp, ubmp; 164 static int l3_egress_mode; 165 static bcm_l3_intf_t l3_intf; 166 bcm_l3_egress_t l3_egress; 167 static bcm_if_t egr_if_id; 168 bcm_module_t my_modid; 169 bcm_field_qset_t qset; 170 static bcm_field_group_t group; 171 static bcm_field_entry_t entry[SOC_MAX_NUM_PORTS]; 172 bcm_port_t port, prev_port; 173 bcm_pkt_t *pkt; 174 enet_hdr_t *enet_hdr; 175 unsigned char *ipv4_hdr; 176 int rv, i; 177 178 vid = 2; 179 intf_id = 10; 180 181 if (enable) { 182 if (l3_activities_running) { 183 return CMD_OK; 184 } 185 186 /* Create a vlan */ 187 rv = bcm_vlan_create(unit, vid); 188 if (rv < 0) { 189 cli_out("fail to create Vlan %d : %s\n", vid, soc_errmsg(rv)); 190 return CMD_FAIL; 191 } 192 193 /* Add all ports to the vlan */ 194 SOC_PBMP_ASSIGN(pbmp, PBMP_PORT_ALL(unit)); 195 SOC_PBMP_OR(pbmp, PBMP_CMIC(unit)); 196 SOC_PBMP_ASSIGN(ubmp, PBMP_PORT_ALL(unit)); 197 rv = bcm_vlan_port_add(unit, vid, pbmp, ubmp); 198 if (rv < 0) { 199 cli_out("fail to add ports to Vlan %d : %s\n", 200 vid, soc_errmsg(rv)); 201 return CMD_FAIL; 202 } 203 204 /* Save the current L3 mode then enable L3 */ 205 rv = bcm_switch_control_get(unit, bcmSwitchL3EgressMode, 206 &l3_egress_mode); 207 if (rv < 0) { 208 cli_out("fail to get current L3 egress mode : %s\n", 209 soc_errmsg(rv)); 210 return CMD_FAIL; 211 } 212 rv = bcm_switch_control_set(unit, bcmSwitchL3EgressMode, TRUE); 213 if (rv < 0) { 214 cli_out("fail to enable L3 egress mode : %s\n", 215 soc_errmsg(rv)); 216 return CMD_FAIL; 217 } 218 219 /* Create L3 interface */ 220 bcm_l3_intf_t_init(&l3_intf); 221 l3_intf.l3a_flags = BCM_L3_WITH_ID | BCM_L3_ADD_TO_ARL; 222 l3_intf.l3a_intf_id = intf_id; 223 sal_memcpy(&l3_intf.l3a_mac_addr, &router_mac, sizeof(router_mac)); 224 l3_intf.l3a_vid = vid; 225 rv = bcm_l3_intf_create(unit, &l3_intf); 226 if (rv < 0) { 227 cli_out("fail to create L3 interface : %s\n", 228 soc_errmsg(rv)); 229 return CMD_FAIL; 230 } 231 232 rv = bcm_stk_my_modid_get(unit, &my_modid); 233 if (rv < 0) { 234 cli_out("fail to get my modid :%s\n", 235 soc_errmsg(rv)); 236 return CMD_FAIL; 237 } 238 239 /* Create L3 egress object, using router_mac as next hop mac address */ 240 bcm_l3_egress_t_init(&l3_egress); 241 l3_egress.intf = intf_id; 242 sal_memcpy(&l3_egress.mac_addr, &router_mac, sizeof(router_mac)); 243 l3_egress.module = my_modid; 244 l3_egress.port = 0; 245 rv = bcm_l3_egress_create(unit, 0, &l3_egress, &egr_if_id); 246 if (rv < 0) { 247 cli_out("fail to create egress L3 object : %s\n", 248 soc_errmsg(rv)); 249 return CMD_FAIL; 250 } 251 252 /* Create field group to qualify ingress port on ingress stage */ 253 BCM_FIELD_QSET_INIT(qset); 254 BCM_FIELD_QSET_ADD(qset, bcmFieldQualifyInPort); 255 BCM_FIELD_QSET_ADD(qset, bcmFieldQualifyStageIngress); 256 rv = bcm_field_group_create(unit, qset, BCM_FIELD_GROUP_PRIO_ANY, 257 &group); 258 if (rv < 0) { 259 cli_out("fail to create field group : %s\n", 260 soc_errmsg(rv)); 261 return CMD_FAIL; 262 } 263 264 PBMP_E_ITER(unit, port) { 265 /* Create field entry */ 266 rv = bcm_field_entry_create (unit, group, &entry[port]); 267 if (rv < 0) { 268 cli_out("fail to create field entry : %s\n", 269 soc_errmsg(rv)); 270 return CMD_FAIL; 271 } 272 } 273 274 prev_port = SOC_PORT_MAX(unit, ge); 275 PBMP_GE_ITER(unit, port) { 276 /* Setup the ingress port qualifier */ 277 rv = bcm_field_qualify_InPort(unit, entry[port], prev_port, 278 BCM_FIELD_EXACT_MATCH_MASK); 279 if (rv < 0) { 280 cli_out("fail to add field port qualifier : %s\n", 281 soc_errmsg(rv)); 282 return CMD_FAIL; 283 } 284 285 /* Setup the action to redirect the packet to the next GE port */ 286 rv = bcm_field_action_add(unit, entry[port], 287 bcmFieldActionRedirect, my_modid, port); 288 if (rv < 0) { 289 cli_out("fail to add field action : %s\n", 290 soc_errmsg(rv)); 291 return CMD_FAIL; 292 } 293 prev_port = port; 294 } 295 296 prev_port = SOC_PORT_MAX(unit, xe); 297 PBMP_XE_ITER(unit, port) { 298 /* Setup the ingress port qualifier */ 299 rv = bcm_field_qualify_InPort(unit, entry[port], prev_port, 300 BCM_FIELD_EXACT_MATCH_MASK); 301 if (rv < 0) { 302 cli_out("fail to add field port qualifier : %s\n", 303 soc_errmsg(rv)); 304 return CMD_FAIL; 305 } 306 307 /* Setup the action to redirect the packet to the next XE port */ 308 rv = bcm_field_action_add(unit, entry[port], 309 bcmFieldActionRedirect, my_modid, port); 310 if (rv < 0) { 311 cli_out("fail to add field action : %s\n", 312 soc_errmsg(rv)); 313 return CMD_FAIL; 314 } 315 prev_port = port; 316 } 317 318 PBMP_E_ITER(unit, port) { 319 /* Setup the action to not change TTL in IP header */ 320 rv = bcm_field_action_add(unit, entry[port], 321 bcmFieldActionDoNotChangeTtl, 0, 0); 322 if (rv < 0) { 323 cli_out("fail to add field action : %s\n", 324 soc_errmsg(rv)); 325 return CMD_FAIL; 326 } 327 328 /* Install the FP entry to hardware */ 329 rv = bcm_field_entry_install(unit, entry[port]); 330 if (rv < 0) { 331 cli_out("fail to install field entry to hardware : %s\n", 332 soc_errmsg(rv)); 333 return CMD_FAIL; 334 } 335 } 336 337 l3_activities_running = TRUE; 338 339 PBMP_E_ITER(unit, port) { 340 /* Put port to PHY loopback */ 341 rv = bcm_port_loopback_set(unit, port, BCM_PORT_LOOPBACK_PHY); 342 if (rv < 0) { 343 cli_out("fail to set port %d to MAC loopback : %s\n", 344 port, soc_errmsg(rv)); 345 return CMD_FAIL; 346 } 347 } 348 349 /* Send 1 routable packet (MAC_DA == router_mac) to any port */ 350 rv = bcm_pkt_alloc(unit, pkt_size + 4, 0, &pkt); 351 if (rv < 0) { 352 cli_out("Error, bcm_pkt_alloc failed $rv\n"); 353 return rv; 354 } 355 if (pkt == NULL) { 356 cli_out("fail to allocate packet : %s\n", soc_errmsg(rv)); 357 return CMD_FAIL; 358 } 359 360 pkt->unit = unit; 361 pkt->flags = BCM_TX_CRC_APPEND; 362 BCM_PKT_TX_LEN_SET(pkt, pkt_size); 363 364 enet_hdr = (enet_hdr_t *)pkt->_pkt_data.data; 365 ENET_SET_MACADDR(&enet_hdr->en_dhost, router_mac); 366 enet_hdr->en_tag_tpid = soc_htons(0x0800); /* IP protocol */ 367 368 ipv4_hdr = &pkt->_pkt_data.data[ENET_UNTAGGED_HDR_LEN]; 369 ipv4_hdr[0] = 0x45; /* IPv4, length 5 x 32-bit words */ 370 ipv4_hdr[2] = 0x0; /* total length pkt_size - 18 bytes */ 371 ipv4_hdr[3] = pkt_size - 18; 372 ipv4_hdr[8] = 0xff; /* time to live */ 373 ipv4_hdr[9] = 0; /* L4 protocol */ 374 ipv4_hdr[12] = 10; /* source IP address 10.1.1.1 */ 375 ipv4_hdr[13] = 1; 376 ipv4_hdr[14] = 1; 377 ipv4_hdr[15] = 1; 378 ipv4_hdr[16] = 10; /* destination IP address 10.2.1.1 */ 379 ipv4_hdr[17] = 2; 380 ipv4_hdr[18] = 1; 381 ipv4_hdr[19] = 1; 382 _extt_do_checksum(ipv4_hdr, 20, 10); /* fill in header check sum */ 383 384 if (SOC_PORT_MIN(unit, ge) >= 0) { 385 BCM_PKT_PORT_SET(pkt, SOC_PORT_MIN(unit, ge), TRUE, FALSE); 386 mac[5] = 0x10; 387 ENET_SET_MACADDR(&enet_hdr->en_shost, mac); 388 for (i = 0; i < num_ge_pkt; i ++) { 389 rv = bcm_tx(unit, pkt, NULL); 390 if (rv < 0) { 391 cli_out("fail to send packet : %s\n", soc_errmsg(rv)); 392 return CMD_FAIL; 393 } 394 } 395 } 396 397 if (SOC_PORT_MIN(unit, xe) >= 0) { 398 BCM_PKT_PORT_SET(pkt, SOC_PORT_MIN(unit, xe), TRUE, FALSE); 399 mac[5] = 0x11; 400 ENET_SET_MACADDR(&enet_hdr->en_shost, mac); 401 for (i = 0; i < num_xe_pkt; i ++) { 402 rv = bcm_tx(unit, pkt, NULL); 403 if (rv < 0) { 404 cli_out("fail to send packet : %s\n", soc_errmsg(rv)); 405 return CMD_FAIL; 406 } 407 } 408 } 409 410 bcm_pkt_free(unit, pkt); 411 } else { 412 PBMP_E_ITER(unit, port) { 413 rv = bcm_field_entry_remove(unit, entry[port]); 414 if (rv < 0) { 415 cli_out("fail to remove field entry from hardware : %s\n", 416 soc_errmsg(rv)); 417 return CMD_FAIL; 418 } 419 420 rv = bcm_field_entry_destroy(unit, entry[port]); 421 if (rv < 0) { 422 cli_out("fail to destroy field entry : %s\n", 423 soc_errmsg(rv)); 424 return CMD_FAIL; 425 } 426 } 427 428 rv = bcm_field_group_destroy(unit, group); 429 if (rv < 0) { 430 cli_out("fail to destroy field group : %s\n", 431 soc_errmsg(rv)); 432 return CMD_FAIL; 433 } 434 435 rv = bcm_l3_egress_destroy(unit, egr_if_id); 436 if (rv < 0) { 437 cli_out("fail to destroy egress L3 object : %s\n", 438 soc_errmsg(rv)); 439 return CMD_FAIL; 440 } 441 442 rv = bcm_l3_intf_delete(unit, &l3_intf); 443 if (rv < 0) { 444 cli_out("fail to delete L3 interface : %s\n", 445 soc_errmsg(rv)); 446 return CMD_FAIL; 447 } 448 449 rv = bcm_switch_control_set(unit, bcmSwitchL3EgressMode, 450 l3_egress_mode); 451 if (rv < 0) { 452 cli_out("fail to restore L3 egress mode : %s\n", 453 soc_errmsg(rv)); 454 return CMD_FAIL; 455 } 456 457 rv = bcm_vlan_destroy(unit, vid); 458 if (rv < 0) { 459 cli_out("fail to destroy Vlan %d : %s\n", 460 vid, soc_errmsg(rv)); 461 return CMD_FAIL; 462 } 463 464 /* Remove all ports from MAC loopback */ 465 PBMP_E_ITER(unit, port) { 466 rv = bcm_port_loopback_set(unit, port, BCM_PORT_LOOPBACK_NONE); 467 if (rv < 0) { 468 cli_out("fail to remove port %d from loopback : %s\n", 469 port, soc_errmsg(rv)); 470 return CMD_FAIL; 471 } 472 } 473 474 l3_activities_running = FALSE; 475 } 476 #endif /* INCLUDE_L3 && BCM_FIELD_SUPPORT */ 477 478 return CMD_OK; 479 } 480 481 const char *cmd_extt_parse_interface[] = { 482 "RLDRAM.Ch0", 483 "RLDRAM.Ch1", 484 "SRAM", 485 "QDR", 486 "TCAM", 487 "UnknownInterface", 488 NULL 489 }; 490 491 char cmd_extt_usage[] = 492 "Parameters:\n\t" 493 "[Interface=<extif>] [RandSeed=<rseed>] [InstallConfig=true|false]\n\t" 494 "[TestCount=<num>] [SliceMask=<mask>] [FullTest=true|false] [Verbose=true|false]\n\t" 495 "[DdrLatency=<num>] [EmLatency=<num>] [RxPhase=<num>] [TxPhase=<num>]\n\t" 496 "\tPerforms a BIST analysis of common tuning parameters to find the\n\t" 497 "\toptimal set. Sets interface to successful parameters.\n\t" 498 "\tIf FullTest is false, BIST testing will stop on first failure (for that setting).\n\t" 499 "\tUse DdrLatency, EmLatency, RxPhase, TxPhase for manual settings.\n"; 500 cmd_result_t 501 cmd_extt(int unit, args_t *a) 502 { 503 parse_table_t pt; 504 soc_memtune_data_t mt_data; 505 int rv; 506 soc_mem_interfaces interface; 507 int sub_interface; 508 int rseed; 509 int dump_config, make_config; 510 int summary; 511 int test_count; 512 int full_test; 513 int freq; 514 char *d0f_str, *d0r_str, *d1f_str, *d1r_str; 515 char *mask_str, *data_str, *bg_data_str[8]; 516 char *bg_d0f_str, *bg_d0r_str, *bg_d1f_str, *bg_d1r_str; 517 int bg_l3, bg_l3_num_ge_pkt, bg_l3_num_xe_pkt; 518 int phase_sel, em_latency, ddr_latency; 519 int tx_offset, rx_offset, w2r_nops, r2w_nops; 520 int rbus_sync_dly, dpeo_sync_dly; 521 int fcd_dpeo, fcd_rbus, use_midl; 522 int invert_txclk, invert_rxclk; 523 uint32 rval, fval; 524 int i, first_si, last_si; 525 char name_str[24], val_str[11], *prefix; 526 527 parse_table_init(unit, &pt); 528 529 parse_table_add(&pt, "Interface", PQ_MULTI, 530 (void *)SOC_MEM_INTERFACE_COUNT, &interface, 531 cmd_extt_parse_interface); 532 parse_table_add(&pt, "SubInterface", PQ_INT, (void *)-1, &sub_interface, 533 0); 534 parse_table_add(&pt, "RandSeed", PQ_INT, (void *)0x12345678, &rseed, 0); 535 parse_table_add(&pt, "InstallConfig", PQ_BOOL, (void *)TRUE, 536 &mt_data.config, 0); 537 parse_table_add(&pt, "DumpConfig", PQ_BOOL, 0, &dump_config, 0); 538 parse_table_add(&pt, "MakeConfig", PQ_BOOL, 0, &make_config, 0); 539 parse_table_add(&pt, "Verbose", PQ_BOOL, 0, &mt_data.verbose, 0); 540 parse_table_add(&pt, "SuppressFail", PQ_BOOL, (void *)TRUE, 541 &mt_data.suppress_fail, 0); 542 parse_table_add(&pt, "SUmmary", PQ_BOOL, (void *)TRUE, &summary, 0); 543 parse_table_add(&pt, "ShowMatrix", PQ_BOOL, 0, &mt_data.show_matrix, 0); 544 parse_table_add(&pt, "ShowProgres", PQ_BOOL, 0, &mt_data.show_progress, 0); 545 parse_table_add(&pt, "TestCount", PQ_INT, (void *)10, &test_count, 0); 546 parse_table_add(&pt, "FullTest", PQ_BOOL, (void *)TRUE, &full_test, 0); 547 parse_table_add(&pt, "DoPvtComp", PQ_BOOL, 0, &mt_data.do_pvt_comp, 0); 548 parse_table_add(&pt, "FreQuency", PQ_INT, (void *)-1, &freq, 0); 549 parse_table_add(&pt, "PhaseSelOvrd", PQ_BOOL, (void *)TRUE, 550 &mt_data.phase_sel_ovrd, 0); 551 parse_table_add(&pt, "TestAllLatency", PQ_BOOL, 552 soc_feature(unit, soc_feature_esm_support) ? 553 (void *)TRUE : (void *)FALSE, 554 &mt_data.test_all_latency, 0); 555 parse_table_add(&pt, "DoTxRxFirst", PQ_BOOL, 556 soc_feature(unit, soc_feature_esm_rxfifo_resync) ? 557 (void *)TRUE : (void *)FALSE, &mt_data.do_txrx_first, 0); 558 parse_table_add(&pt, "D0F", PQ_STRING, 0, &d0f_str, 0); 559 parse_table_add(&pt, "D0R", PQ_STRING, 0, &d0r_str, 0); 560 parse_table_add(&pt, "D1F", PQ_STRING, 0, &d1f_str, 0); 561 parse_table_add(&pt, "D1R", PQ_STRING, 0, &d1r_str, 0); 562 parse_table_add(&pt, "Adr0", PQ_INT, (void *)-1, &mt_data.adr0, 0); 563 parse_table_add(&pt, "Adr1", PQ_INT, (void *)-1, &mt_data.adr1, 0); 564 parse_table_add(&pt, "AdrMode", PQ_INT, (void *)-1, &mt_data.adr_mode, 0); 565 parse_table_add(&pt, "Mask", PQ_STRING, 0, &mask_str, 0); 566 parse_table_add(&pt, "Data", PQ_STRING, 0, &data_str, 0); 567 parse_table_add(&pt, "TcamLoopCount", PQ_INT, (void *)100, 568 &mt_data.tcam_loop_count, 0); 569 570 parse_table_add(&pt, "BGSramBist", PQ_BOOL, 0, &mt_data.bg_sram_bist, 0); 571 parse_table_add(&pt, "BGSramD0F", PQ_STRING, 0, &bg_d0f_str, 0); 572 parse_table_add(&pt, "BGSramD0R", PQ_STRING, 0, &bg_d0r_str, 0); 573 parse_table_add(&pt, "BGSramD1F", PQ_STRING, 0, &bg_d1f_str, 0); 574 parse_table_add(&pt, "BGSramD1R", PQ_STRING, 0, &bg_d1r_str, 0); 575 parse_table_add(&pt, "BGSramAdr0", PQ_INT, (void *)-1, &mt_data.bg_adr0, 576 0); 577 parse_table_add(&pt, "BGSramAdr1", PQ_INT, (void *)-1, &mt_data.bg_adr1, 578 0); 579 parse_table_add(&pt, "BGSramTestMode", PQ_INT, (void *)3, 580 &mt_data.bg_loop_mode, 0); 581 parse_table_add(&pt, "BGSramAdrMode", PQ_INT, (void *)-1, 582 &mt_data.bg_adr_mode, 0); 583 parse_table_add(&pt, "BGTcamBist", PQ_BOOL, 0, &mt_data.bg_tcam_bist, 0); 584 parse_table_add(&pt, "BGTcamLoopCount", PQ_INT, (void *)1000, 585 &mt_data.bg_tcam_loop_count, 0); 586 parse_table_add(&pt, "BGTcamData0", PQ_STRING, 0, &bg_data_str[0], 0); 587 parse_table_add(&pt, "BGTcamData1", PQ_STRING, 0, &bg_data_str[1], 0); 588 parse_table_add(&pt, "BGTcamData2", PQ_STRING, 0, &bg_data_str[2], 0); 589 parse_table_add(&pt, "BGTcamData3", PQ_STRING, 0, &bg_data_str[3], 0); 590 parse_table_add(&pt, "BGTcamData4", PQ_STRING, 0, &bg_data_str[4], 0); 591 parse_table_add(&pt, "BGTcamData5", PQ_STRING, 0, &bg_data_str[5], 0); 592 parse_table_add(&pt, "BGTcamData6", PQ_STRING, 0, &bg_data_str[6], 0); 593 parse_table_add(&pt, "BGTcamData7", PQ_STRING, 0, &bg_data_str[7], 0); 594 parse_table_add(&pt, "BGTcamOeMap", PQ_INT, 0, &mt_data.bg_tcam_oemap, 0); 595 parse_table_add(&pt, "BGL3", PQ_BOOL, 0, &bg_l3, 0); 596 parse_table_add(&pt, "BGL3NumGePkt", PQ_INT, (void *)300, 597 &bg_l3_num_ge_pkt, 0); 598 parse_table_add(&pt, "BGL3NumXePkt", PQ_INT, (void *)80, 599 &bg_l3_num_xe_pkt, 0); 600 601 parse_table_add(&pt, "PhaseSel", PQ_INT, (void *) -1, &phase_sel, 0); 602 parse_table_add(&pt, "EmLatency", PQ_INT, (void *)-1, &em_latency, 0); 603 parse_table_add(&pt, "DdrLatency", PQ_INT, (void *)-1, &ddr_latency, 0); 604 parse_table_add(&pt, "TxPhase", PQ_INT, (void *)-1, &tx_offset, 0); 605 parse_table_add(&pt, "RxPhase", PQ_INT, (void *)-1, &rx_offset, 0); 606 parse_table_add(&pt, "W2RNops", PQ_INT, (void *)-1, &w2r_nops, 0); 607 parse_table_add(&pt, "R2WNops", PQ_INT, (void *)-1, &r2w_nops, 0); 608 parse_table_add(&pt, "RbusSyncDly", PQ_INT, (void *)-1, &rbus_sync_dly, 0); 609 parse_table_add(&pt, "DpeoSyncDly", PQ_INT, (void *)-1, &dpeo_sync_dly, 0); 610 parse_table_add(&pt, "FcdDpeo", PQ_INT, (void *)-1, &fcd_dpeo, 0); 611 parse_table_add(&pt, "FcdRbus", PQ_INT, (void *)-1, &fcd_rbus, 0); 612 parse_table_add(&pt, "UseMidl", PQ_INT, (void *)-1, &use_midl, 0); 613 parse_table_add(&pt, "InvertTxclk", PQ_INT, (void *)-1, &invert_txclk, 0); 614 parse_table_add(&pt, "InvertRxclk", PQ_INT, (void *)-1, &invert_rxclk, 0); 615 616 if (parse_arg_eq(a, &pt) < 0) { 617 cli_out("%s: Invalid argument: %s\n", ARG_CMD(a), ARG_CUR(a)); 618 parse_arg_eq_done(&pt); 619 return(CMD_FAIL); 620 } 621 622 mt_data.d0f_0 = mt_data.d0f_1 = 0xffffffff; 623 mt_data.d0r_0 = mt_data.d0r_1 = 0xffffffff; 624 mt_data.d1f_0 = mt_data.d1f_1 = 0xffffffff; 625 mt_data.d1r_0 = mt_data.d1r_1 = 0xffffffff; 626 if (d0f_str[0] && d0r_str[0] && d1f_str[0] && d1r_str[0]) { 627 _extt_hex_to_18bit_unit_bin(d0f_str, &mt_data.d0f_0, &mt_data.d0f_1); 628 _extt_hex_to_18bit_unit_bin(d0r_str, &mt_data.d0r_0, &mt_data.d0r_1); 629 _extt_hex_to_18bit_unit_bin(d1f_str, &mt_data.d1f_0, &mt_data.d1f_1); 630 _extt_hex_to_18bit_unit_bin(d1r_str, &mt_data.d1r_0, &mt_data.d1r_1); 631 } 632 633 mt_data.bg_d0f_0 = mt_data.bg_d0f_1 = 0xffffffff; 634 mt_data.bg_d0r_0 = mt_data.bg_d0r_1 = 0xffffffff; 635 mt_data.bg_d1f_0 = mt_data.bg_d1f_1 = 0xffffffff; 636 mt_data.bg_d1r_0 = mt_data.bg_d1r_1 = 0xffffffff; 637 if (bg_d0f_str[0] && bg_d0r_str[0] && bg_d1f_str[0] && bg_d1r_str[0]) { 638 _extt_hex_to_18bit_unit_bin(bg_d0f_str, &mt_data.bg_d0f_0, 639 &mt_data.bg_d0f_1); 640 _extt_hex_to_18bit_unit_bin(bg_d0r_str, &mt_data.bg_d0r_0, 641 &mt_data.bg_d0r_1); 642 _extt_hex_to_18bit_unit_bin(bg_d1f_str, &mt_data.bg_d1f_0, 643 &mt_data.bg_d1f_1); 644 _extt_hex_to_18bit_unit_bin(bg_d1r_str, &mt_data.bg_d1r_0, 645 &mt_data.bg_d1r_1); 646 } 647 648 sal_memset(mt_data.mask, 0xff, sizeof(mt_data.mask)); 649 sal_memset(mt_data.data, 0, sizeof(mt_data.data)); 650 if (mask_str[0] && data_str[0]) { 651 _extt_hex_to_72bit_unit_bin(mask_str, mt_data.mask, 2); 652 _extt_hex_to_72bit_unit_bin(data_str, mt_data.data, 2); 653 } 654 655 sal_memset(mt_data.bg_tcam_data, 0, sizeof(mt_data.bg_tcam_data)); 656 for (i = 0; i < 8; i++) { 657 if (bg_data_str[i]) { 658 _extt_hex_to_72bit_unit_bin(bg_data_str[i], 659 &mt_data.bg_tcam_data[i * 4], 1); 660 mt_data.bg_tcam_data[i * 4] = mt_data.bg_tcam_data[i * 4 + 3]; 661 mt_data.bg_tcam_data[i * 4 + 3] = mt_data.bg_tcam_data[i * 4 + 1]; 662 mt_data.bg_tcam_data[i * 4 + 1] = mt_data.bg_tcam_data[i * 4 + 2]; 663 mt_data.bg_tcam_data[i * 4 + 2] = mt_data.bg_tcam_data[i * 4 + 3]; 664 mt_data.bg_tcam_data[i * 4 + 3] = 0; 665 } 666 } 667 668 /* Don't need strings anymore */ 669 parse_arg_eq_done(&pt); 670 671 if (dump_config) { 672 if (soc_feature(unit, soc_feature_esm_support)) { 673 for (i = 0; i < 2; i++) { /* ES0 and ES1 */ 674 sal_sprintf(name_str, "%s%d", spn_EXT_SRAM_TUNING, i); 675 rval = soc_property_get(unit, name_str, 0); 676 cli_out("Tuning parameter (%s) for ES%d", name_str, i); 677 if (!rval) { 678 cli_out(" is not in config\n"); 679 continue; 680 } 681 prefix = i ? "SRAM1" : "SRAM0"; 682 cli_out("\n"); 683 cli_out(" %s, PhaseSelOvrd, %d\n", 684 prefix, 685 (rval >> SOC_TR_MEMTUNE_OVRD_SM_SHIFT) & 686 SOC_TR_MEMTUNE_OVRD_SM_MASK); 687 cli_out(" %s, PhaseSel, %d\n", 688 prefix, 689 (rval >> SOC_TR_MEMTUNE_PHASE_SEL_SHIFT) & 690 SOC_TR_MEMTUNE_PHASE_SEL_MASK); 691 fval = (rval >> SOC_TR_MEMTUNE_EM_LATENCY_SHIFT) & 692 SOC_TR_MEMTUNE_EM_LATENCY_MASK; 693 cli_out(" %s, EmLatency, %d\n", 694 prefix, fval ? fval : 8); 695 cli_out(" %s, DdrLatency, %d\n", 696 prefix, 697 (rval >> SOC_TR_MEMTUNE_DDR_LATENCY_SHIFT) & 698 SOC_TR_MEMTUNE_DDR_LATENCY_MASK); 699 cli_out(" %s, TxPhase, %d\n", 700 prefix, 701 (rval >> SOC_TR_MEMTUNE_DDR_TX_OFFSET_SHIFT) & 702 SOC_TR_MEMTUNE_DDR_TX_OFFSET_MASK); 703 cli_out(" %s, RxPhase, %d\n", 704 prefix, 705 (rval >> SOC_TR_MEMTUNE_DDR_RX_OFFSET_SHIFT) & 706 SOC_TR_MEMTUNE_DDR_RX_OFFSET_MASK); 707 cli_out(" %s, W2RNops, %d\n", 708 prefix, 709 (rval >> SOC_TR_MEMTUNE_W2R_NOPS_SHIFT) & 710 SOC_TR_MEMTUNE_W2R_NOPS_MASK); 711 cli_out(" %s, R2WNops, %d\n", 712 prefix, 713 (rval >> SOC_TR_MEMTUNE_R2W_NOPS_SHIFT) & 714 SOC_TR_MEMTUNE_R2W_NOPS_MASK); 715 cli_out(" %s, FreQuency, %d\n", 716 prefix, 717 (rval >> SOC_TR_MEMTUNE_DDR_FREQ_SHIFT) & 718 SOC_TR_MEMTUNE_DDR_FREQ_MASK); 719 720 sal_sprintf(name_str, "%s%d", spn_EXT_SRAM_PVT, i); 721 rval = soc_property_get(unit, name_str, 0); 722 if (rval) { 723 cli_out(" %s, OvrdOdtRes, %d\n", 724 prefix, 725 ((rval >> SOC_TR_MEMTUNE_OVRD_ODTRES_SHIFT) & 726 SOC_TR_MEMTUNE_OVRD_ODTRES_MASK)); 727 cli_out(" %s, OdtRes, %d\n", 728 prefix, 729 ((rval >> SOC_TR_MEMTUNE_ODTRES_SHIFT) & 730 SOC_TR_MEMTUNE_ODTRES_MASK)); 731 cli_out(" %s, OvrdDriver, %d\n", 732 prefix, 733 ((rval >> SOC_TR_MEMTUNE_OVRD_DRIVER_SHIFT) & 734 SOC_TR_MEMTUNE_OVRD_DRIVER_MASK)); 735 cli_out(" %s, PDRive, %d\n", 736 prefix, 737 ((rval >> SOC_TR_MEMTUNE_PDRIVE_SHIFT) & 738 SOC_TR_MEMTUNE_PDRIVE_MASK)); 739 cli_out(" %s, NDRive, %d\n", 740 prefix, 741 ((rval >> SOC_TR_MEMTUNE_NDRIVE_SHIFT) & 742 SOC_TR_MEMTUNE_NDRIVE_MASK)); 743 cli_out(" %s, OvrdSLew, %d\n", 744 prefix, 745 ((rval >> SOC_TR_MEMTUNE_OVRD_SLEW_SHIFT) & 746 SOC_TR_MEMTUNE_OVRD_SLEW_MASK)); 747 cli_out(" %s, SLew, %d\n", 748 prefix, 749 ((rval >> SOC_TR_MEMTUNE_SLEW_SHIFT) & 750 SOC_TR_MEMTUNE_SLEW_MASK)); 751 } 752 753 sal_sprintf(name_str, "%s%d", spn_EXT_SRAM_TUNING_STATS, i); 754 rval = soc_property_get(unit, name_str, 0); 755 if (rval) { 756 cli_out(" %s, (STATS) Area, %d\n", 757 prefix, 758 ((rval >> SOC_TR_MEMTUNE_STATS_WIDTH_SHIFT) & 759 SOC_TR_MEMTUNE_STATS_WIDTH_MASK) * 760 ((rval >> SOC_TR_MEMTUNE_STATS_HEIGHT_SHIFT) & 761 SOC_TR_MEMTUNE_STATS_HEIGHT_MASK)); 762 cli_out(" %s, (STATS) Width, %d\n", 763 prefix, 764 (rval >> SOC_TR_MEMTUNE_STATS_WIDTH_SHIFT) & 765 SOC_TR_MEMTUNE_STATS_WIDTH_MASK); 766 cli_out(" %s, (STATS) Height, %d\n", 767 prefix, 768 (rval >> SOC_TR_MEMTUNE_STATS_HEIGHT_SHIFT) & 769 SOC_TR_MEMTUNE_STATS_HEIGHT_MASK); 770 cli_out(" %s, (STATS) FailCount, %d\n", 771 prefix, 772 (rval >> SOC_TR_MEMTUNE_STATS_FAIL_SHIFT) & 773 SOC_TR_MEMTUNE_STATS_FAIL_MASK); 774 } 775 sal_sprintf(name_str, "%s%d", spn_EXT_SRAM_TUNING2_STATS, i); 776 rval = soc_property_get(unit, name_str, 0); 777 if (rval) { 778 cli_out(" %s, (STATS2) Area, %d\n", 779 prefix, 780 ((rval >> SOC_TR_MEMTUNE_STATS_WIDTH_SHIFT) & 781 SOC_TR_MEMTUNE_STATS_WIDTH_MASK) * 782 ((rval >> SOC_TR_MEMTUNE_STATS_HEIGHT_SHIFT) & 783 SOC_TR_MEMTUNE_STATS_HEIGHT_MASK)); 784 cli_out(" %s, (STATS2) Width, %d\n", 785 prefix, 786 (rval >> SOC_TR_MEMTUNE_STATS_WIDTH_SHIFT) & 787 SOC_TR_MEMTUNE_STATS_WIDTH_MASK); 788 cli_out(" %s, (STATS2) Height, %d\n", 789 prefix, 790 (rval >> SOC_TR_MEMTUNE_STATS_HEIGHT_SHIFT) & 791 SOC_TR_MEMTUNE_STATS_HEIGHT_MASK); 792 cli_out(" %s, (STATS2) FailCount, %d\n", 793 prefix, 794 (rval >> SOC_TR_MEMTUNE_STATS_FAIL_SHIFT) & 795 SOC_TR_MEMTUNE_STATS_FAIL_MASK); 796 } 797 } 798 799 sal_sprintf(name_str, "%s0", spn_EXT_TCAM_TUNING); 800 rval = soc_property_get(unit, name_str, 0); 801 cli_out("Tuning parameter (%s) for TCAM (part 1)", name_str); 802 if (!rval) { 803 cli_out(" is not in config\n"); 804 return CMD_OK; 805 } 806 prefix = "TCAM"; 807 cli_out("\n"); 808 cli_out(" %s, RbusSyncDly, %d\n", 809 prefix, 810 (rval >> SOC_TR_MEMTUNE_RBUS_SYNC_DLY_SHIFT) & 811 SOC_TR_MEMTUNE_RBUS_SYNC_DLY_MASK); 812 cli_out(" %s, DpeoSyncDly, %d\n", 813 prefix, 814 (rval >> SOC_TR_MEMTUNE_DPEO_SYNC_DLY_SHIFT) & 815 SOC_TR_MEMTUNE_DPEO_SYNC_DLY_MASK); 816 cli_out(" %s, FcdDpeo, %d\n", 817 prefix, 818 (rval >> SOC_TR_MEMTUNE_FCD_DPEO_SHIFT) & 819 SOC_TR_MEMTUNE_FCD_DPEO_MASK); 820 cli_out(" %s, FcdRbus, %d\n", 821 prefix, 822 (rval >> SOC_TR_MEMTUNE_FCD_RBUS_SHIFT) & 823 SOC_TR_MEMTUNE_FCD_RBUS_MASK); 824 825 sal_sprintf(name_str, "%s1", spn_EXT_TCAM_TUNING); 826 rval = soc_property_get(unit, name_str, 0); 827 cli_out("Tuning parameter (%s) for TCAM (part 2)", name_str); 828 if (!rval) { 829 cli_out(" is not in config\n"); 830 return CMD_OK; 831 } 832 cli_out("\n"); 833 cli_out(" %s, TxPhase, %d\n", 834 prefix, 835 (rval >> SOC_TR_MEMTUNE_TCAM_TX_OFFSET_SHIFT) & 836 SOC_TR_MEMTUNE_TCAM_TX_OFFSET_MASK); 837 cli_out(" %s, RxPhase, %d\n", 838 prefix, 839 (rval >> SOC_TR_MEMTUNE_TCAM_RX_OFFSET_SHIFT) & 840 SOC_TR_MEMTUNE_TCAM_RX_OFFSET_MASK); 841 cli_out(" %s, FreQuency, %d\n", 842 prefix, 843 (rval >> SOC_TR_MEMTUNE_TCAM_FREQ_SHIFT) & 844 SOC_TR_MEMTUNE_TCAM_FREQ_MASK); 845 cli_out(" %s, UseMidl, %d\n", 846 prefix, 847 (rval >> SOC_TR_MEMTUNE_USE_MIDL_SHIFT) & 848 SOC_TR_MEMTUNE_USE_MIDL_MASK); 849 cli_out(" %s, InvertTxclk, %d\n", 850 prefix, 851 (rval >> SOC_TR_MEMTUNE_INVERT_TXCLK_SHIFT) & 852 SOC_TR_MEMTUNE_INVERT_TXCLK_MASK); 853 cli_out(" %s, InvertRxclk, %d\n", 854 prefix, 855 (rval >> SOC_TR_MEMTUNE_INVERT_RXCLK_SHIFT) & 856 SOC_TR_MEMTUNE_INVERT_RXCLK_MASK); 857 858 sal_sprintf(name_str, "%s", spn_EXT_TCAM_PVT); 859 rval = soc_property_get(unit, name_str, 0); 860 if (rval) { 861 cli_out(" %s, OvrdOdtRes, %d\n", 862 prefix, 863 ((rval >> SOC_TR_MEMTUNE_OVRD_ODTRES_SHIFT) & 864 SOC_TR_MEMTUNE_OVRD_ODTRES_MASK)); 865 cli_out(" %s, OdtRes, %d\n", 866 prefix, 867 ((rval >> SOC_TR_MEMTUNE_ODTRES_SHIFT) & 868 SOC_TR_MEMTUNE_ODTRES_MASK)); 869 cli_out(" %s, OvrdDriver, %d\n", 870 prefix, 871 ((rval >> SOC_TR_MEMTUNE_OVRD_DRIVER_SHIFT) & 872 SOC_TR_MEMTUNE_OVRD_DRIVER_MASK)); 873 cli_out(" %s, PDRive, %d\n", 874 prefix, 875 ((rval >> SOC_TR_MEMTUNE_PDRIVE_SHIFT) & 876 SOC_TR_MEMTUNE_PDRIVE_MASK)); 877 cli_out(" %s, NDRive, %d\n", 878 prefix, 879 ((rval >> SOC_TR_MEMTUNE_NDRIVE_SHIFT) & 880 SOC_TR_MEMTUNE_NDRIVE_MASK)); 881 cli_out(" %s, OvrdSLew, %d\n", 882 prefix, 883 ((rval >> SOC_TR_MEMTUNE_OVRD_SLEW_SHIFT) & 884 SOC_TR_MEMTUNE_OVRD_SLEW_MASK)); 885 cli_out(" %s, SLew, %d\n", 886 prefix, 887 ((rval >> SOC_TR_MEMTUNE_SLEW_SHIFT) & 888 SOC_TR_MEMTUNE_SLEW_MASK)); 889 } 890 891 sal_sprintf(name_str, "%s", spn_EXT_TCAM_TUNING_STATS); 892 rval = soc_property_get(unit, name_str, 0); 893 if (rval) { 894 cli_out(" %s, (STATS) Ares, %d\n", 895 prefix, 896 ((rval >> SOC_TR_MEMTUNE_STATS_WIDTH_SHIFT) & 897 SOC_TR_MEMTUNE_STATS_WIDTH_MASK) * 898 ((rval >> SOC_TR_MEMTUNE_STATS_HEIGHT_SHIFT) & 899 SOC_TR_MEMTUNE_STATS_HEIGHT_MASK)); 900 cli_out(" %s, (STATS) Width, %d\n", 901 prefix, 902 (rval >> SOC_TR_MEMTUNE_STATS_WIDTH_SHIFT) & 903 SOC_TR_MEMTUNE_STATS_WIDTH_MASK); 904 cli_out(" %s, (STATS) Height, %d\n", 905 prefix, 906 (rval >> SOC_TR_MEMTUNE_STATS_HEIGHT_SHIFT) & 907 SOC_TR_MEMTUNE_STATS_HEIGHT_MASK); 908 cli_out(" %s, (STATS) FailCount, %d\n", 909 prefix, 910 (rval >> SOC_TR_MEMTUNE_STATS_FAIL_SHIFT) & 911 SOC_TR_MEMTUNE_STATS_FAIL_MASK); 912 } 913 return CMD_OK; 914 } 915 return CMD_FAIL; 916 } 917 if (make_config) { 918 if (soc_feature(unit, soc_feature_esm_support)) { 919 switch (interface) { 920 case SOC_MEM_INTERFACE_SRAM: 921 if (sub_interface == -1) { 922 first_si = 0; 923 last_si = 1; 924 } else if (sub_interface == 0 || sub_interface == 1) { 925 first_si = last_si = sub_interface; 926 } else { 927 cli_out("Invalid SubInterface\n"); 928 return CMD_FAIL; 929 } 930 for (i = first_si; i <= last_si; i++) { /* ES0 and/or ES1 */ 931 sal_sprintf(name_str, "%s%d", spn_EXT_SRAM_TUNING, i); 932 rval = soc_property_get(unit, name_str, 0); 933 if (phase_sel != -1) { 934 rval |= (SOC_TR_MEMTUNE_OVRD_SM_MASK << 935 SOC_TR_MEMTUNE_OVRD_SM_SHIFT); 936 rval &= ~(SOC_TR_MEMTUNE_PHASE_SEL_MASK << 937 SOC_TR_MEMTUNE_PHASE_SEL_SHIFT); 938 rval |= ((phase_sel & SOC_TR_MEMTUNE_PHASE_SEL_MASK) << 939 SOC_TR_MEMTUNE_PHASE_SEL_SHIFT); 940 } 941 if (em_latency != -1) { 942 rval &= ~(SOC_TR_MEMTUNE_EM_LATENCY_MASK << 943 SOC_TR_MEMTUNE_EM_LATENCY_SHIFT); 944 rval |= ((em_latency & 945 SOC_TR_MEMTUNE_EM_LATENCY_MASK) << 946 SOC_TR_MEMTUNE_EM_LATENCY_SHIFT); 947 } 948 if (ddr_latency != -1) { 949 rval &= ~(SOC_TR_MEMTUNE_DDR_LATENCY_MASK << 950 SOC_TR_MEMTUNE_DDR_LATENCY_SHIFT); 951 rval |= ((ddr_latency & 952 SOC_TR_MEMTUNE_DDR_LATENCY_MASK) << 953 SOC_TR_MEMTUNE_DDR_LATENCY_SHIFT); 954 } 955 if (tx_offset != -1) { 956 rval &= ~(SOC_TR_MEMTUNE_DDR_TX_OFFSET_MASK << 957 SOC_TR_MEMTUNE_DDR_TX_OFFSET_SHIFT); 958 rval |= ((tx_offset & 959 SOC_TR_MEMTUNE_DDR_TX_OFFSET_MASK) << 960 SOC_TR_MEMTUNE_DDR_TX_OFFSET_SHIFT); 961 } 962 if (rx_offset != -1) { 963 rval &= ~(SOC_TR_MEMTUNE_DDR_RX_OFFSET_MASK << 964 SOC_TR_MEMTUNE_DDR_RX_OFFSET_SHIFT); 965 rval |= ((rx_offset & 966 SOC_TR_MEMTUNE_DDR_RX_OFFSET_MASK) << 967 SOC_TR_MEMTUNE_DDR_RX_OFFSET_SHIFT); 968 } 969 if (w2r_nops != -1) { 970 rval &= ~(SOC_TR_MEMTUNE_W2R_NOPS_MASK << 971 SOC_TR_MEMTUNE_W2R_NOPS_SHIFT); 972 rval |= ((w2r_nops & SOC_TR_MEMTUNE_W2R_NOPS_MASK) << 973 SOC_TR_MEMTUNE_W2R_NOPS_SHIFT); 974 } 975 if (r2w_nops != -1) { 976 rval &= ~(SOC_TR_MEMTUNE_R2W_NOPS_MASK << 977 SOC_TR_MEMTUNE_R2W_NOPS_SHIFT); 978 rval |= ((r2w_nops & SOC_TR_MEMTUNE_R2W_NOPS_MASK) << 979 SOC_TR_MEMTUNE_R2W_NOPS_SHIFT); 980 } 981 if (freq != -1) { 982 rval &= ~(SOC_TR_MEMTUNE_DDR_FREQ_MASK << 983 SOC_TR_MEMTUNE_DDR_FREQ_SHIFT); 984 rval |= ((freq & SOC_TR_MEMTUNE_DDR_FREQ_MASK) << 985 SOC_TR_MEMTUNE_DDR_FREQ_SHIFT); 986 } 987 sal_sprintf(val_str, "0x%08x", rval); 988 if (sal_config_set(name_str, val_str) < 0) { 989 cli_out("Write config fail"); 990 return CMD_FAIL; 991 } 992 } 993 return CMD_OK; 994 case SOC_MEM_INTERFACE_TCAM: 995 sal_sprintf(name_str, "%s0", spn_EXT_TCAM_TUNING); 996 rval = soc_property_get(unit, name_str, 0); 997 if (rbus_sync_dly != -1) { 998 rval &= ~(SOC_TR_MEMTUNE_RBUS_SYNC_DLY_MASK << 999 SOC_TR_MEMTUNE_RBUS_SYNC_DLY_SHIFT); 1000 rval |= ((rbus_sync_dly & 1001 SOC_TR_MEMTUNE_RBUS_SYNC_DLY_MASK) << 1002 SOC_TR_MEMTUNE_RBUS_SYNC_DLY_SHIFT); 1003 } 1004 if (dpeo_sync_dly != -1) { 1005 rval &= ~(SOC_TR_MEMTUNE_DPEO_SYNC_DLY_MASK << 1006 SOC_TR_MEMTUNE_DPEO_SYNC_DLY_SHIFT); 1007 rval |= ((dpeo_sync_dly & 1008 SOC_TR_MEMTUNE_DPEO_SYNC_DLY_MASK) << 1009 SOC_TR_MEMTUNE_DPEO_SYNC_DLY_SHIFT); 1010 } 1011 if (fcd_dpeo != -1) { 1012 rval &= ~(SOC_TR_MEMTUNE_FCD_DPEO_MASK << 1013 SOC_TR_MEMTUNE_FCD_DPEO_SHIFT); 1014 rval |= ((fcd_dpeo & SOC_TR_MEMTUNE_FCD_DPEO_MASK) << 1015 SOC_TR_MEMTUNE_FCD_DPEO_SHIFT); 1016 } 1017 if (fcd_rbus != -1) { 1018 rval &= ~(SOC_TR_MEMTUNE_FCD_RBUS_MASK << 1019 SOC_TR_MEMTUNE_FCD_RBUS_SHIFT); 1020 rval |= ((fcd_rbus & SOC_TR_MEMTUNE_FCD_RBUS_MASK) << 1021 SOC_TR_MEMTUNE_FCD_RBUS_SHIFT); 1022 } 1023 sal_sprintf(val_str, "0x%08x", rval); 1024 if (sal_config_set(name_str, val_str) < 0) { 1025 cli_out("Write config fail"); 1026 return CMD_FAIL; 1027 } 1028 sal_sprintf(name_str, "%s1", spn_EXT_TCAM_TUNING); 1029 rval = soc_property_get(unit, name_str, 0); 1030 if (tx_offset != -1) { 1031 rval &= ~(SOC_TR_MEMTUNE_TCAM_TX_OFFSET_MASK << 1032 SOC_TR_MEMTUNE_TCAM_TX_OFFSET_SHIFT); 1033 rval |= ((tx_offset & 1034 SOC_TR_MEMTUNE_TCAM_TX_OFFSET_MASK) << 1035 SOC_TR_MEMTUNE_TCAM_TX_OFFSET_SHIFT); 1036 } 1037 if (rx_offset != -1) { 1038 rval &= ~(SOC_TR_MEMTUNE_TCAM_RX_OFFSET_MASK << 1039 SOC_TR_MEMTUNE_TCAM_RX_OFFSET_SHIFT); 1040 rval |= ((rx_offset & 1041 SOC_TR_MEMTUNE_TCAM_RX_OFFSET_MASK) << 1042 SOC_TR_MEMTUNE_TCAM_RX_OFFSET_SHIFT); 1043 } 1044 if (freq != -1) { 1045 rval &= ~(SOC_TR_MEMTUNE_TCAM_FREQ_MASK << 1046 SOC_TR_MEMTUNE_TCAM_FREQ_SHIFT); 1047 rval |= ((freq & SOC_TR_MEMTUNE_TCAM_FREQ_MASK) << 1048 SOC_TR_MEMTUNE_TCAM_FREQ_SHIFT); 1049 } 1050 if (use_midl != -1) { 1051 rval &= ~(SOC_TR_MEMTUNE_USE_MIDL_MASK << 1052 SOC_TR_MEMTUNE_USE_MIDL_SHIFT); 1053 rval |= ((use_midl & SOC_TR_MEMTUNE_USE_MIDL_MASK) << 1054 SOC_TR_MEMTUNE_USE_MIDL_SHIFT); 1055 } 1056 if (invert_txclk != -1) { 1057 rval &= ~(SOC_TR_MEMTUNE_INVERT_TXCLK_MASK << 1058 SOC_TR_MEMTUNE_INVERT_TXCLK_SHIFT); 1059 rval |= ((invert_txclk & 1060 SOC_TR_MEMTUNE_INVERT_TXCLK_MASK) << 1061 SOC_TR_MEMTUNE_INVERT_TXCLK_SHIFT); 1062 } 1063 if (invert_rxclk != -1) { 1064 rval &= ~(SOC_TR_MEMTUNE_INVERT_RXCLK_MASK << 1065 SOC_TR_MEMTUNE_INVERT_RXCLK_SHIFT); 1066 rval |= ((invert_rxclk & 1067 SOC_TR_MEMTUNE_INVERT_RXCLK_MASK) << 1068 SOC_TR_MEMTUNE_INVERT_RXCLK_SHIFT); 1069 } 1070 sal_sprintf(val_str, "0x%08x", rval); 1071 if (sal_config_set(name_str, val_str) < 0) { 1072 cli_out("Write config fail"); 1073 return CMD_FAIL; 1074 } 1075 return CMD_OK; 1076 default: 1077 break; 1078 } 1079 } 1080 return CMD_FAIL; 1081 } 1082 1083 mt_data.interface = interface; 1084 mt_data.sub_interface = sub_interface; 1085 mt_data.rseed = rseed; 1086 mt_data.summary = summary; 1087 mt_data.summary_header = summary; 1088 mt_data.test_count = test_count; 1089 mt_data.max_fail_count = full_test ? test_count : 1; 1090 mt_data.freq = freq; 1091 1092 mt_data.manual_settings = 0; 1093 mt_data.man_em_latency = em_latency; 1094 mt_data.man_ddr_latency = ddr_latency; 1095 mt_data.man_tx_offset = tx_offset; 1096 mt_data.man_rx_offset = rx_offset; 1097 1098 if (soc_feature(unit, soc_feature_esm_support)) { 1099 if (mt_data.interface == SOC_MEM_INTERFACE_SRAM) { 1100 mt_data.slice_mask = SOC_TR_SRAM_SLICE_MASK; 1101 } 1102 } 1103 1104 if (soc_feature(unit, soc_feature_esm_support)) { 1105 if (mt_data.interface == SOC_MEM_INTERFACE_TCAM) { 1106 if (tx_offset != -1 && rx_offset != -1) { 1107 mt_data.verbose = TRUE; 1108 mt_data.suppress_fail = FALSE; 1109 mt_data.manual_settings = 1; 1110 } 1111 } else if (mt_data.interface == SOC_MEM_INTERFACE_SRAM) { 1112 if (ddr_latency != -1 &&em_latency != -1 && 1113 rx_offset != -1 && tx_offset != -1) { 1114 mt_data.verbose = TRUE; 1115 mt_data.suppress_fail = FALSE; 1116 mt_data.manual_settings = 1; 1117 mt_data.man_phase_sel = phase_sel; 1118 mt_data.man_w2r_nops = w2r_nops; 1119 mt_data.man_r2w_nops = r2w_nops; 1120 } 1121 } 1122 } else if ((ddr_latency != -1) || (em_latency != -1) || 1123 (rx_offset != -1) || (tx_offset != -1)) { 1124 1125 if ((ddr_latency == -1) || (rx_offset == -1) || (tx_offset == -1)) { 1126 cli_out("%s: Must specify %s %s %s parameter(s).\n", 1127 ARG_CMD(a), 1128 (ddr_latency == -1) ? "DdrLatency" : "", 1129 (rx_offset == -1) ? "RxPhase" : "", 1130 (tx_offset == -1) ? "TxPhase" : ""); 1131 goto fail; 1132 } 1133 1134 mt_data.verbose = TRUE; 1135 mt_data.suppress_fail = FALSE; 1136 mt_data.manual_settings = 1; 1137 mt_data.man_phase_sel = phase_sel; 1138 mt_data.man_w2r_nops = w2r_nops; 1139 mt_data.man_r2w_nops = r2w_nops; 1140 } 1141 1142 if (bg_l3) { 1143 _extt_l3_activities(unit, TRUE, bg_l3_num_ge_pkt, bg_l3_num_xe_pkt); 1144 } 1145 1146 if ((rv = soc_mem_interface_tune(unit, &mt_data)) < 0) { 1147 cli_out("ERROR: unit %d, tuning %s: %s\n", 1148 unit, cmd_extt_parse_interface[interface], soc_errmsg(rv)); 1149 } 1150 1151 if (bg_l3) { 1152 _extt_l3_activities(unit, FALSE, 0, 0); 1153 } 1154 1155 #if defined(BCM_TRIUMPH_SUPPORT) 1156 if (soc_feature(unit, soc_feature_esm_support) && 1157 mt_data.interface == SOC_MEM_INTERFACE_TCAM) { 1158 if (soc_triumph_esm_init_read_config(unit) < 0) { 1159 cli_out("ERROR: unit %d, restore TCAM config fail\n", unit); 1160 goto fail; 1161 } 1162 if (soc_tcam_init(unit) < 0) { 1163 cli_out("ERROR: unit %d, re-init TCAM fail\n", unit); 1164 goto fail; 1165 } 1166 } 1167 #endif /* BCM_TRIUMPH_SUPPORT */ 1168 1169 return rv >= 0 ? CMD_OK : CMD_FAIL; 1170 1171 fail: 1172 parse_arg_eq_done(&pt); 1173 return CMD_FAIL; 1174 1175 } 1176 1177 char cmd_extts_usage[] = 1178 "Parameters:\n\t" 1179 "[TestCount=<num>] [InstallConfig=true|false]\n\t" 1180 "[PhaseSelOvrd=true|false]\n"; 1181 cmd_result_t 1182 cmd_extts(int unit, args_t *a) 1183 { 1184 int test_count = SOC_ER_DDR_BIST_COUNT; 1185 int phase_sel_ovrd = TRUE; 1186 int config = FALSE; 1187 parse_table_t pt; 1188 int i, rv; 1189 soc_memtune_data_t mt_data; 1190 1191 parse_table_init(unit, &pt); 1192 1193 parse_table_add(&pt, "TestCount", PQ_INT | PQ_DFL, 0, &test_count, 0); 1194 parse_table_add(&pt, "InstallConfig", PQ_BOOL | PQ_DFL, 0, &config, 0); 1195 parse_table_add(&pt, "PhaseSelOvrd", PQ_BOOL | PQ_DFL, 0, &phase_sel_ovrd, 0); 1196 1197 if (parse_arg_eq(a, &pt) < 0) { 1198 cli_out("%s: Invalid argument: %s\n", ARG_CMD(a), ARG_CUR(a)); 1199 parse_arg_eq_done(&pt); 1200 return(CMD_FAIL); 1201 } 1202 1203 /* Don't need strings anymore */ 1204 parse_arg_eq_done(&pt); 1205 1206 cli_out("Running external memory tuning on all interfaces. Test count = %d.\n", 1207 test_count); 1208 1209 for (i=0; i < SOC_MEM_INTERFACE_COUNT; i++) { 1210 mt_data.interface = i; 1211 mt_data.rseed = 0x12345678; 1212 mt_data.config = config; 1213 mt_data.test_count = test_count; 1214 mt_data.max_fail_count = test_count; 1215 mt_data.slice_mask = (i == SOC_MEM_INTERFACE_QDR) ? 1216 SOC_ER_QDR_SLICE_MASK : SOC_ER_RLDRAM_SLICE_MASK; 1217 mt_data.verbose = 0; 1218 mt_data.suppress_fail = 0; 1219 mt_data.manual_settings = 0; 1220 mt_data.summary = TRUE; 1221 mt_data.summary_header = i == 0 ? TRUE : FALSE; 1222 mt_data.phase_sel_ovrd = phase_sel_ovrd; 1223 1224 rv = soc_mem_interface_tune(unit, &mt_data); 1225 if (rv < 0 && rv != SOC_E_UNAVAIL) { 1226 cli_out("ERROR: unit %d, tuning %s: %s\n", 1227 unit, cmd_extt_parse_interface[i], soc_errmsg(rv)); 1228 } 1229 } 1230 1231 return CMD_OK; 1232 } 1233 1234 char cmd_extt2_usage[] = 1235 "Parameters:\n\t" 1236 "[InstallConfig=true|false] [Verbose=true|false] [SUmmary=true|false]\n\t" 1237 "[TestCount=<num>] [UseTestList=true|false] [TestListID=<num>]\n\t" 1238 "[DeLTa0=<num>][DeLTa1=<num>]\n"; 1239 1240 #define EXTT2_START_ACCUMULATE 0x01 1241 #define EXTT2_INSTALL_CONFIG 0x02 1242 #define EXTT2_ENABLE_TCAM_ODT 0x04 1243 #define EXTT2_DISABLE_TCAM_ODT 0x08 1244 #define EXTT2_START_L3_TRAFFIC 0x10 1245 #define EXTT2_STOP_L3_TRAFFIC 0x20 1246 1247 typedef struct extt2_test_list_s { 1248 char *test_name; 1249 int loop_mode[2]; 1250 int alt_adr; 1251 int tcam_data_choice; 1252 int sram_data_choice; 1253 uint32 event; 1254 } extt2_test_list_t; 1255 1256 /* Test list ID 0 : full test */ 1257 extt2_test_list_t extt2_full_test_list[] = { 1258 /* test_name ,loop_mode,aa, tdc,sdc, event */ 1259 { "10" , { 3, 3 }, 1, 1, 1, EXTT2_START_ACCUMULATE }, 1260 { "10_SDC2" , { 3, 3 }, 1, 1, 2, 0 }, 1261 { "10_SDC3" , { 3, 3 }, 1, 1, 3, 0 }, 1262 { "10_SDC7" , { 3, 3 }, 1, 1, 7, 0 }, 1263 { "10_SDC8" , { 3, 3 }, 1, 1, 8, 0 }, 1264 { "10_SDC3_AA3" , { 3, 3 }, 3, 1, 3, 0 }, 1265 { "10_SDC7_AA3" , { 3, 3 }, 3, 1, 7, 0 }, 1266 { "10_SDC8_AA3" , { 3, 3 }, 3, 1, 8, 0 }, 1267 { "11" , { 3, 4 }, 1, 1, 1, 0 }, 1268 { "11_SDC2" , { 3, 4 }, 1, 1, 2, 0 }, 1269 { "11_SDC3" , { 3, 4 }, 1, 1, 3, 0 }, 1270 { "11_SDC7" , { 3, 4 }, 1, 1, 7, 0 }, 1271 { "11_SDC8" , { 3, 4 }, 1, 1, 8, 0 }, 1272 { "11_SDC3_AA3" , { 3, 4 }, 3, 1, 3, 0 }, 1273 { "11_SDC7_AA3" , { 3, 4 }, 3, 1, 7, 0 }, 1274 { "11_SDC8_AA3" , { 3, 4 }, 3, 1, 8, 0 }, 1275 { "12" , { 4, 3 }, 1, 1, 1, 0 }, 1276 { "12_SDC2" , { 4, 3 }, 1, 1, 2, 0 }, 1277 { "12_SDC3" , { 4, 3 }, 1, 1, 3, 0 }, 1278 { "12_SDC7" , { 4, 3 }, 1, 1, 7, 0 }, 1279 { "12_SDC8" , { 4, 3 }, 1, 1, 8, 0 }, 1280 { "12_SDC3_AA3" , { 4, 3 }, 3, 1, 3, 0 }, 1281 { "12_SDC7_AA3" , { 4, 3 }, 3, 1, 7, 0 }, 1282 { "12_SDC8_AA3" , { 4, 3 }, 3, 1, 8, 0 }, 1283 { "14_1" , { 1, 1 }, 1, 6, 1, 0 }, 1284 { "14_1_SDC2" , { 1, 1 }, 1, 6, 2, 0 }, 1285 { "14_1_SDC3" , { 1, 1 }, 1, 6, 3, 0 }, 1286 { "14_1_SDC7" , { 1, 1 }, 1, 6, 7, 0 }, 1287 { "14_1_SDC8" , { 1, 1 }, 1, 6, 8, 0 }, 1288 { "14_1_SDC3_AA3" , { 1, 1 }, 3, 6, 3, 0 }, 1289 { "14_1_SDC7_AA3" , { 1, 1 }, 3, 6, 7, 0 }, 1290 { "14_1_SDC8_AA3" , { 1, 1 }, 3, 6, 8, 0 }, 1291 { "140_1" , { 1, 1 }, 1, 7, 1, 0 }, 1292 { "140_1_SDC2" , { 1, 1 }, 1, 7, 2, 0 }, 1293 { "140_1_SDC3" , { 1, 1 }, 1, 7, 3, 0 }, 1294 { "140_1_SDC7" , { 1, 1 }, 1, 7, 7, 0 }, 1295 { "140_1_SDC8" , { 1, 1 }, 1, 7, 8, 0 }, 1296 { "140_1_SDC3_AA3" , { 1, 1 }, 3, 7, 3, 0 }, 1297 { "140_1_SDC7_AA3" , { 1, 1 }, 3, 7, 7, 0 }, 1298 { "140_1_SDC8_AA3" , { 1, 1 }, 3, 7, 8, 0 }, 1299 { "13" , { 3, 3 }, 1, 2000, 1, 0 }, 1300 { "13_SDC2" , { 3, 3 }, 1, 2000, 2, 0 }, 1301 { "13_SDC3" , { 3, 3 }, 1, 2000, 3, 0 }, 1302 { "13_SDC7" , { 3, 3 }, 1, 2000, 7, 0 }, 1303 { "13_SDC8" , { 3, 3 }, 1, 2000, 8, 0 }, 1304 { "13_SDC3_AA3" , { 3, 3 }, 3, 2000, 3, 0 }, 1305 { "13_SDC7_AA3" , { 3, 3 }, 3, 2000, 7, 0 }, 1306 { "13_SDC8_AA3" , { 3, 3 }, 3, 2000, 8, 0 }, 1307 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_START_L3_TRAFFIC }, 1308 { "13_1" , { 3, 3 }, 1, 2000, 1, 0 }, 1309 { "13_1_SDC2" , { 3, 3 }, 1, 2000, 2, 0 }, 1310 { "13_1_SDC3" , { 3, 3 }, 1, 2000, 3, 0 }, 1311 { "13_1_SDC7" , { 3, 3 }, 1, 2000, 7, 0 }, 1312 { "13_1_SDC8" , { 3, 3 }, 1, 2000, 8, 0 }, 1313 { "13_1_SDC3_AA3" , { 3, 3 }, 3, 2000, 3, 0 }, 1314 { "13_1_SDC7_AA3" , { 3, 3 }, 3, 2000, 7, 0 }, 1315 { "13_1_SDC8_AA3" , { 3, 3 }, 3, 2000, 8, 0 }, 1316 { "15_RR" , { 1, 1 }, 1, 1, 1, 0 }, 1317 { "15_S0_RR" , { 1, 3 }, 1, 1, 1, 0 }, 1318 { "15_S1_RR" , { 3, 1 }, 1, 1, 1, 0 }, 1319 { "15" , { 3, 3 }, 1, 1, 1, 0 }, 1320 { "15_SDC2" , { 3, 3 }, 1, 1, 2, 0 }, 1321 { "15_SDC3" , { 3, 3 }, 1, 1, 3, 0 }, 1322 { "15_SDC7" , { 3, 3 }, 1, 1, 7, 0 }, 1323 { "15_SDC8" , { 3, 3 }, 1, 1, 8, 0 }, 1324 { "15_SDC3_AA3" , { 3, 3 }, 3, 1, 3, 0 }, 1325 { "15_SDC7_AA3" , { 3, 3 }, 3, 1, 7, 0 }, 1326 { "15_SDC8_AA3" , { 3, 3 }, 3, 1, 8, EXTT2_INSTALL_CONFIG }, 1327 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_STOP_L3_TRAFFIC }, 1328 }; 1329 1330 extt2_test_list_t extt2_old_full_test_list[] = { 1331 /* test_name ,loop_mode,aa, tdc,sdc, event */ 1332 { "10" , { 3, 3 }, 1, 1, 1, EXTT2_START_ACCUMULATE }, 1333 { "10_SDC2" , { 3, 3 }, 1, 1, 2, 0 }, 1334 { "10_SDC3" , { 3, 3 }, 1, 1, 3, 0 }, 1335 { "10_SDC3_AA3" , { 3, 3 }, 3, 1, 3, 0 }, 1336 { "11" , { 3, 4 }, 1, 1, 1, 0 }, 1337 { "11_SDC2" , { 3, 4 }, 1, 1, 2, 0 }, 1338 { "11_SDC3" , { 3, 4 }, 1, 1, 3, 0 }, 1339 { "11_SDC3_AA3" , { 3, 4 }, 3, 1, 3, 0 }, 1340 { "12" , { 4, 3 }, 1, 1, 1, 0 }, 1341 { "12_SDC2" , { 4, 3 }, 1, 1, 2, 0 }, 1342 { "12_SDC3" , { 4, 3 }, 1, 1, 3, 0 }, 1343 { "12_SDC3_AA3" , { 4, 3 }, 3, 1, 3, 0 }, 1344 { "14_1" , { 1, 1 }, 1, 6, 1, 0 }, 1345 { "14_1_SDC2" , { 1, 1 }, 1, 6, 2, 0 }, 1346 { "14_1_SDC3" , { 1, 1 }, 1, 6, 3, 0 }, 1347 { "14_1_SDC3_AA3" , { 1, 1 }, 3, 6, 3, 0 }, 1348 { "140_1" , { 1, 1 }, 1, 7, 1, 0 }, 1349 { "140_1_SDC2" , { 1, 1 }, 1, 7, 2, 0 }, 1350 { "140_1_SDC3" , { 1, 1 }, 1, 7, 3, 0 }, 1351 { "140_1_SDC3_AA3" , { 1, 1 }, 3, 7, 3, 0 }, 1352 { "13" , { 3, 3 }, 1, 2000, 1, 0 }, 1353 { "13_SDC2" , { 3, 3 }, 1, 2000, 2, 0 }, 1354 { "13_SDC3" , { 3, 3 }, 1, 2000, 3, 0 }, 1355 { "13_SDC3_AA3" , { 3, 3 }, 3, 2000, 3, 0 }, 1356 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_START_L3_TRAFFIC }, 1357 { "13_1" , { 3, 3 }, 1, 2000, 1, 0 }, 1358 { "13_1_SDC2" , { 3, 3 }, 1, 2000, 2, 0 }, 1359 { "13_1_SDC3" , { 3, 3 }, 1, 2000, 3, 0 }, 1360 { "13_1_SDC3_AA3" , { 3, 3 }, 3, 2000, 3, 0 }, 1361 { "15_RR" , { 1, 1 }, 1, 1, 1, 0 }, 1362 { "15_S0_RR" , { 1, 3 }, 1, 1, 1, 0 }, 1363 { "15_S1_RR" , { 3, 1 }, 1, 1, 1, 0 }, 1364 { "15" , { 3, 3 }, 1, 1, 1, 0 }, 1365 { "15_SDC2" , { 3, 3 }, 1, 1, 2, 0 }, 1366 { "15_SDC3" , { 3, 3 }, 1, 1, 3, 0 }, 1367 { "15_SDC3_AA3" , { 3, 3 }, 3, 1, 3, EXTT2_INSTALL_CONFIG }, 1368 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_STOP_L3_TRAFFIC }, 1369 }; 1370 1371 /* Test list ID 1 : short test */ 1372 extt2_test_list_t extt2_short_test_list[] = { 1373 /* test_name ,loop_mode,aa, tdc,sdc, event */ 1374 { "14_1" , { 1, 1 }, 1, 6, 1, EXTT2_START_ACCUMULATE }, 1375 { "14_1_SDC2" , { 1, 1 }, 1, 6, 2, 0 }, 1376 { "14_1_SDC3" , { 1, 1 }, 1, 6, 3, 0 }, 1377 { "14_1_SDC3_AA3" , { 1, 1 }, 3, 6, 3, 0 }, 1378 { "140_1" , { 1, 1 }, 1, 7, 1, 0 }, 1379 { "140_1_SDC2" , { 1, 1 }, 1, 7, 2, 0 }, 1380 { "140_1_SDC3" , { 1, 1 }, 1, 7, 3, 0 }, 1381 { "140_1_SDC3_AA3" , { 1, 1 }, 3, 7, 3, 0 }, 1382 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_START_L3_TRAFFIC }, 1383 { "15_RR" , { 1, 1 }, 1, 1, 1, 0 }, 1384 { "15_S0_RR" , { 1, 3 }, 1, 1, 1, 0 }, 1385 { "15_S1_RR" , { 3, 1 }, 1, 1, 1, 0 }, 1386 { "15" , { 3, 3 }, 1, 1, 1, 0 }, 1387 { "15_SDC2" , { 3, 3 }, 1, 1, 2, 0 }, 1388 { "15_SDC3" , { 3, 3 }, 1, 1, 3, 0 }, 1389 { "15_SDC3_AA3" , { 3, 3 }, 3, 1, 3, EXTT2_INSTALL_CONFIG }, 1390 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_STOP_L3_TRAFFIC }, 1391 }; 1392 1393 extt2_test_list_t extt2_full_test_list_sram0[] = { 1394 /* test_name ,loop_mode,aa, tdc,sdc, event */ 1395 { "11" , { 3, 4 }, 1, 1, 1, EXTT2_START_ACCUMULATE }, 1396 { "11_SDC2" , { 3, 4 }, 1, 1, 2, 0 }, 1397 { "11_SDC3" , { 3, 4 }, 1, 1, 3, 0 }, 1398 { "11_SDC3_AA3" , { 3, 4 }, 3, 1, 3, 0 }, 1399 { "14_1" , { 1, 4 }, 1, 6, 1, 0 }, 1400 { "14_1_SDC2" , { 1, 4 }, 1, 6, 2, 0 }, 1401 { "14_1_SDC3" , { 1, 4 }, 1, 6, 3, 0 }, 1402 { "14_1_SDC3_AA3" , { 1, 4 }, 3, 6, 3, 0 }, 1403 { "140_1" , { 1, 4 }, 1, 7, 1, 0 }, 1404 { "140_1_SDC2" , { 1, 4 }, 1, 7, 2, 0 }, 1405 { "140_1_SDC3" , { 1, 4 }, 1, 7, 3, 0 }, 1406 { "140_1_SDC3_AA3" , { 1, 4 }, 3, 7, 3, 0 }, 1407 { "13" , { 3, 4 }, 1, 2000, 1, 0 }, 1408 { "13_SDC2" , { 3, 4 }, 1, 2000, 2, 0 }, 1409 { "13_SDC3" , { 3, 4 }, 1, 2000, 3, 0 }, 1410 { "13_SDC3_AA3" , { 3, 4 }, 3, 2000, 3, 0 }, 1411 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_START_L3_TRAFFIC }, 1412 { "13_1" , { 3, 4 }, 1, 2000, 1, 0 }, 1413 { "13_1_SDC2" , { 3, 4 }, 1, 2000, 2, 0 }, 1414 { "13_1_SDC3" , { 3, 4 }, 1, 2000, 3, 0 }, 1415 { "13_1_SDC3_AA3" , { 3, 4 }, 3, 2000, 3, 0 }, 1416 { "15_RR" , { 1, 4 }, 1, 1, 1, 0 }, 1417 { "15" , { 3, 4 }, 1, 1, 1, 0 }, 1418 { "15_SDC2" , { 3, 4 }, 1, 1, 2, 0 }, 1419 { "15_SDC3" , { 3, 4 }, 1, 1, 3, 0 }, 1420 { "15_SDC3_AA3" , { 3, 4 }, 3, 1, 3, EXTT2_INSTALL_CONFIG }, 1421 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_STOP_L3_TRAFFIC }, 1422 }; 1423 1424 extt2_test_list_t extt2_full_test_list_sram1[] = { 1425 /* test_name ,loop_mode,aa, tdc,sdc, event */ 1426 { "12" , { 4, 3 }, 1, 1, 1, EXTT2_START_ACCUMULATE }, 1427 { "12_SDC2" , { 4, 3 }, 1, 1, 2, 0 }, 1428 { "12_SDC3" , { 4, 3 }, 1, 1, 3, 0 }, 1429 { "12_SDC3_AA3" , { 4, 3 }, 3, 1, 3, 0 }, 1430 { "14_1" , { 4, 1 }, 1, 6, 1, 0 }, 1431 { "14_1_SDC2" , { 4, 1 }, 1, 6, 2, 0 }, 1432 { "14_1_SDC3" , { 4, 1 }, 1, 6, 3, 0 }, 1433 { "14_1_SDC3_AA3" , { 4, 1 }, 3, 6, 3, 0 }, 1434 { "140_1" , { 4, 1 }, 1, 7, 1, 0 }, 1435 { "140_1_SDC2" , { 4, 1 }, 1, 7, 2, 0 }, 1436 { "140_1_SDC3" , { 4, 1 }, 1, 7, 3, 0 }, 1437 { "140_1_SDC3_AA3" , { 4, 1 }, 3, 7, 3, 0 }, 1438 { "13" , { 4, 3 }, 1, 2000, 1, 0 }, 1439 { "13_SDC2" , { 4, 3 }, 1, 2000, 2, 0 }, 1440 { "13_SDC3" , { 4, 3 }, 1, 2000, 3, 0 }, 1441 { "13_SDC3_AA3" , { 4, 3 }, 3, 2000, 3, 0 }, 1442 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_START_L3_TRAFFIC }, 1443 { "13_1" , { 4, 3 }, 1, 2000, 1, 0 }, 1444 { "13_1_SDC2" , { 4, 3 }, 1, 2000, 2, 0 }, 1445 { "13_1_SDC3" , { 4, 3 }, 1, 2000, 3, 0 }, 1446 { "13_1_SDC3_AA3" , { 4, 3 }, 3, 2000, 3, 0 }, 1447 { "15_RR" , { 4, 1 }, 1, 1, 1, 0 }, 1448 { "15" , { 4, 3 }, 1, 1, 1, 0 }, 1449 { "15_SDC2" , { 4, 3 }, 1, 1, 2, 0 }, 1450 { "15_SDC3" , { 4, 3 }, 1, 1, 3, 0 }, 1451 { "15_SDC3_AA3" , { 4, 3 }, 3, 1, 3, EXTT2_INSTALL_CONFIG }, 1452 { NULL , { 0, 0 }, 0, 0, 0, EXTT2_STOP_L3_TRAFFIC }, 1453 }; 1454 1455 STATIC int 1456 _extt2_do_test_list(int unit, soc_memtune_data_t *mt_data, int test_list_id, 1457 int config, int show_matrix, int restore_txrx_after_test, 1458 int delta0, int delta1, 1459 int bg_l3_num_ge_pkt, int bg_l3_num_xe_pkt) 1460 { 1461 extt2_test_list_t *list; 1462 int rv, list_len, alloc_size, i; 1463 uint32 rval; 1464 1465 alloc_size = (SOC_TR_SRAM_TX_OFFSET_MAX - SOC_TR_SRAM_TX_OFFSET_MIN + 1) * 1466 (SOC_TR_SRAM_RX_OFFSET_MAX - SOC_TR_SRAM_RX_OFFSET_MIN + 1) * 1467 sizeof(int); 1468 1469 switch (test_list_id) { 1470 case 0: 1471 list_len = sizeof(extt2_full_test_list) / 1472 sizeof(extt2_full_test_list[0]); 1473 list = extt2_full_test_list; 1474 break; 1475 case 1: 1476 list_len = sizeof(extt2_short_test_list) / 1477 sizeof(extt2_short_test_list[0]); 1478 list = extt2_short_test_list; 1479 break; 1480 case 3: 1481 list_len = sizeof(extt2_full_test_list_sram0) / 1482 sizeof(extt2_full_test_list_sram0[0]); 1483 list = extt2_full_test_list_sram0; 1484 break; 1485 case 4: 1486 list_len = sizeof(extt2_full_test_list_sram1) / 1487 sizeof(extt2_full_test_list_sram1[0]); 1488 list = extt2_full_test_list_sram1; 1489 break; 1490 case 5: 1491 list_len = sizeof(extt2_old_full_test_list) / 1492 sizeof(extt2_old_full_test_list[0]); 1493 list = extt2_old_full_test_list; 1494 break; 1495 default: 1496 cli_out("Invalid TestListID %d\n", test_list_id); 1497 return CMD_FAIL; 1498 } 1499 1500 rv = CMD_OK; 1501 for (i = 0; i < list_len; i++) { 1502 if (list[i].test_name == NULL) { 1503 if (list[i].event & EXTT2_ENABLE_TCAM_ODT) { 1504 if (READ_ETU_DDR72_CONFIG_REG1_ISr(unit, &rval) < 0) { 1505 return CMD_FAIL; 1506 } 1507 soc_reg_field_set(unit, ETU_DDR72_CONFIG_REG1_ISr, &rval, 1508 ENABLE_ODTf, 1); 1509 soc_reg_field_set(unit, ETU_DDR72_CONFIG_REG1_ISr, &rval, 1510 ENABLE_ODT_CKf, 1); 1511 if (WRITE_ETU_DDR72_CONFIG_REG1_ISr(unit, rval) < 0) { 1512 return CMD_FAIL; 1513 } 1514 cli_out("=== Enable ODT\n"); 1515 } 1516 if (list[i].event & EXTT2_DISABLE_TCAM_ODT) { 1517 if (READ_ETU_DDR72_CONFIG_REG1_ISr(unit, &rval) < 0) { 1518 return CMD_FAIL; 1519 } 1520 soc_reg_field_set(unit, ETU_DDR72_CONFIG_REG1_ISr, &rval, 1521 ENABLE_ODTf, 0); 1522 soc_reg_field_set(unit, ETU_DDR72_CONFIG_REG1_ISr, &rval, 1523 ENABLE_ODT_CKf, 0); 1524 if (WRITE_ETU_DDR72_CONFIG_REG1_ISr(unit, rval) < 0) { 1525 return CMD_FAIL; 1526 } 1527 cli_out("=== Disable ODT\n"); 1528 } 1529 if (list[i].event & EXTT2_START_L3_TRAFFIC) { 1530 cli_out("=== Starting L3 and FP activities\n"); 1531 if (_extt_l3_activities(unit, TRUE, bg_l3_num_ge_pkt, 1532 bg_l3_num_xe_pkt) < 0) { 1533 return CMD_FAIL; 1534 } 1535 } 1536 if (list[i].event & EXTT2_STOP_L3_TRAFFIC) { 1537 cli_out("=== Stopping L3 and FP activities\n"); 1538 if (_extt_l3_activities(unit, FALSE, 0, 0) < 0) { 1539 return CMD_FAIL; 1540 } 1541 } 1542 continue; 1543 } 1544 mt_data->config = 1545 list[i].event & EXTT2_INSTALL_CONFIG ? config : FALSE; 1546 mt_data->show_matrix = 1547 list[i].event & EXTT2_INSTALL_CONFIG ? TRUE : show_matrix; 1548 mt_data->delta[0] = delta0; 1549 mt_data->delta[1] = delta1; 1550 mt_data->loop_mode[0] = list[i].loop_mode[0]; 1551 mt_data->loop_mode[1] = list[i].loop_mode[1]; 1552 mt_data->alt_adr = list[i].alt_adr; 1553 mt_data->tcam_data_choice = list[i].tcam_data_choice; 1554 mt_data->sram_data_choice = list[i].sram_data_choice; 1555 mt_data->restore_txrx_after_test = 1556 list[i].event & EXTT2_INSTALL_CONFIG ? 1557 restore_txrx_after_test : TRUE; 1558 if (list[i].event & EXTT2_START_ACCUMULATE) { 1559 sal_memset(mt_data->fail_array[0], 0, alloc_size); 1560 sal_memset(mt_data->fail_array[1], 0, alloc_size); 1561 } 1562 1563 cli_out("TEST:%s LoopMode0=%d LoopMode1=%d AltAdr=%d " 1564 "TcamDataChoice=%d SramDataChoice=%d\n", 1565 list[i].test_name, 1566 list[i].loop_mode[0], 1567 list[i].loop_mode[1], 1568 list[i].alt_adr, 1569 list[i].tcam_data_choice, 1570 list[i].sram_data_choice); 1571 1572 rv = soc_mem_interface_tune_lvl2(unit, mt_data); 1573 if (rv < 0) { 1574 cli_out("ERROR: unit %d, extt2: %s\n", unit, soc_errmsg(rv)); 1575 } 1576 } 1577 1578 return rv; 1579 } 1580 1581 cmd_result_t 1582 cmd_extt2(int unit, args_t *a) 1583 { 1584 parse_table_t pt; 1585 soc_memtune_data_t mt_data; 1586 int rv; 1587 int config; 1588 int show_matrix; 1589 int use_test_list, test_list_id; 1590 int loop_mode0, loop_mode1, alt_adr; 1591 int tcam_data_choice, sram_data_choice; 1592 int delta0, delta1; 1593 int tx_offset0, rx_offset0, tx_offset1,rx_offset1; 1594 int ok_on_both_pass, restore_txrx_after_test; 1595 int bg_l3_num_ge_pkt, bg_l3_num_xe_pkt; 1596 int alloc_size; 1597 1598 sal_memset(&mt_data, 0, sizeof(mt_data)); 1599 1600 parse_table_init(unit, &pt); 1601 1602 parse_table_add(&pt, "InstallConfig", PQ_BOOL, (void *)TRUE, &config, 0); 1603 parse_table_add(&pt, "Verbose", PQ_BOOL, 0, &mt_data.verbose, 0); 1604 parse_table_add(&pt, "SUmmary", PQ_BOOL, (void *)TRUE, &mt_data.summary, 1605 0); 1606 parse_table_add(&pt, "ShowSetting", PQ_BOOL, 0, &mt_data.show_setting, 0); 1607 parse_table_add(&pt, "ShowMatrix", PQ_BOOL, 0, &show_matrix, 0); 1608 parse_table_add(&pt, "TestCount", PQ_INT, (void *)20, &mt_data.test_count, 1609 0); 1610 parse_table_add(&pt, "MaxFailCount", PQ_INT, (void *)1, 1611 &mt_data.max_fail_count, 0); 1612 parse_table_add(&pt, "TestAllLatency", PQ_BOOL, 1613 soc_feature(unit, soc_feature_esm_rxfifo_resync) ? 1614 (void *)TRUE : (void *)FALSE, 1615 &mt_data.test_all_latency, 0); 1616 parse_table_add(&pt, "UseTestList", PQ_BOOL, (void *)TRUE, &use_test_list, 1617 0); 1618 parse_table_add(&pt, "TestListID", PQ_INT, (void *)2, &test_list_id, 0); 1619 parse_table_add(&pt, "LoopMode0", PQ_INT, (void *)-1, &loop_mode0, 0); 1620 parse_table_add(&pt, "LoopMode1", PQ_INT, (void *)-1, &loop_mode1, 0); 1621 parse_table_add(&pt, "AltAdr", PQ_INT, (void *)-1, &alt_adr, 0); 1622 parse_table_add(&pt, "TcamDataChoice", PQ_INT, (void *)-1, 1623 &tcam_data_choice, 0); 1624 parse_table_add(&pt, "SramDataChoice", PQ_INT, (void *)-1, 1625 &sram_data_choice, 0); 1626 parse_table_add(&pt, "TcamLoopCount", PQ_INT, (void *)1000, 1627 &mt_data.tcam_loop_count, 0); 1628 parse_table_add(&pt, "DeLTa0", PQ_INT, (void *)28, &delta0, 0); 1629 parse_table_add(&pt, "DeLTa1", PQ_INT, (void *)28, &delta1, 0); 1630 parse_table_add(&pt, "TxOffset0", PQ_INT, (void *)-1, &tx_offset0, 0); 1631 parse_table_add(&pt, "RxOffset0", PQ_INT, (void *)-1, &rx_offset0, 0); 1632 parse_table_add(&pt, "TxOffset1", PQ_INT, (void *)-1, &tx_offset1, 0); 1633 parse_table_add(&pt, "RxOffset1", PQ_INT, (void *)-1, &rx_offset1, 0); 1634 parse_table_add(&pt, "OkOnBothPass", PQ_INT, 0, &ok_on_both_pass, 0); 1635 parse_table_add(&pt, "RestoreTxRxAfterTest", PQ_BOOL, 0, 1636 &restore_txrx_after_test, 0); 1637 parse_table_add(&pt, "BGL3NumGePkt", PQ_INT, (void *)300, 1638 &bg_l3_num_ge_pkt, 0); 1639 parse_table_add(&pt, "BGL3NumXePkt", PQ_INT, (void *)80, 1640 &bg_l3_num_xe_pkt, 0); 1641 1642 if (parse_arg_eq(a, &pt) < 0) { 1643 cli_out("%s: Invalid argument: %s\n", ARG_CMD(a), ARG_CUR(a)); 1644 parse_arg_eq_done(&pt); 1645 return CMD_FAIL; 1646 } 1647 1648 /* Don't need strings anymore */ 1649 parse_arg_eq_done(&pt); 1650 1651 alloc_size = (SOC_TR_SRAM_TX_OFFSET_MAX - SOC_TR_SRAM_TX_OFFSET_MIN + 1) * 1652 (SOC_TR_SRAM_RX_OFFSET_MAX - SOC_TR_SRAM_RX_OFFSET_MIN + 1) * 1653 sizeof(int); 1654 1655 mt_data.fail_array[0] = sal_alloc(alloc_size, "memtune fail array"); 1656 if (mt_data.fail_array[0] == NULL) { 1657 return SOC_E_MEMORY; 1658 } 1659 mt_data.fail_array[1] = sal_alloc(alloc_size, "memtune fail array"); 1660 if (mt_data.fail_array[1] == NULL) { 1661 sal_free(mt_data.fail_array[0]); 1662 return SOC_E_MEMORY; 1663 } 1664 1665 if (use_test_list) { 1666 mt_data.tx_offset[0] = -1; 1667 mt_data.rx_offset[0] = -1; 1668 mt_data.tx_offset[1] = -1; 1669 mt_data.rx_offset[1] = -1; 1670 mt_data.ok_on_both_pass = ok_on_both_pass; 1671 1672 if (test_list_id == 2 || test_list_id == 6) { 1673 if (test_list_id == 2) { 1674 test_list_id = 0; 1675 } else if (test_list_id == 6) { 1676 test_list_id = 5; 1677 } 1678 mt_data.ok_on_both_pass = FALSE; 1679 rv = _extt2_do_test_list(unit, &mt_data, test_list_id, config, 1680 show_matrix, restore_txrx_after_test, 28, 1681 0, bg_l3_num_ge_pkt, bg_l3_num_xe_pkt); 1682 if (rv >= 0) { 1683 mt_data.ok_on_both_pass = TRUE; 1684 rv = _extt2_do_test_list(unit, &mt_data, test_list_id, config, 1685 show_matrix, restore_txrx_after_test, 1686 0, 28, bg_l3_num_ge_pkt, 1687 bg_l3_num_xe_pkt); 1688 } 1689 } else { 1690 rv = _extt2_do_test_list(unit, &mt_data, test_list_id, config, 1691 show_matrix, restore_txrx_after_test, 1692 delta0, delta1, 1693 bg_l3_num_ge_pkt, bg_l3_num_xe_pkt); 1694 } 1695 } else { 1696 mt_data.config = config; 1697 mt_data.show_matrix = show_matrix; 1698 mt_data.loop_mode[0] = loop_mode0; 1699 mt_data.loop_mode[1] = loop_mode1; 1700 mt_data.alt_adr = alt_adr; 1701 mt_data.tcam_data_choice = tcam_data_choice; 1702 mt_data.sram_data_choice = sram_data_choice; 1703 mt_data.delta[0] = delta0; 1704 mt_data.delta[1] = delta1; 1705 mt_data.tx_offset[0] = tx_offset0; 1706 mt_data.rx_offset[0] = rx_offset0; 1707 mt_data.tx_offset[1] = tx_offset1; 1708 mt_data.rx_offset[1] = rx_offset1; 1709 mt_data.ok_on_both_pass = ok_on_both_pass; 1710 mt_data.restore_txrx_after_test = restore_txrx_after_test; 1711 sal_memset(mt_data.fail_array[0], 0, alloc_size); 1712 sal_memset(mt_data.fail_array[1], 0, alloc_size); 1713 1714 rv = soc_mem_interface_tune_lvl2(unit, &mt_data); 1715 } 1716 1717 if (rv < 0) { 1718 cli_out("ERROR: unit %d, extt2: %s\n", unit, soc_errmsg(rv)); 1719 } 1720 1721 if (mt_data.fail_array[0] != NULL) { 1722 sal_free(mt_data.fail_array[0]); 1723 } 1724 if (mt_data.fail_array[1] != NULL) { 1725 sal_free(mt_data.fail_array[1]); 1726 } 1727 1728 return CMD_OK; 1729 } 1730 #endif /* BCM_TRIUMPH_SUPPORT */ 1731 1732 #endif /* NO_MEMTUNE */