cpri_diag.c (8219B)
1 /**************************************************************************** 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 */ 8 9 #include <shared/bsl.h> 10 #include <bcm/types.h> 11 #include <soc/drv.h> 12 #include <soc/error.h> 13 #include <soc/debug.h> 14 #include <soc/mem.h> 15 #include <soc/monterey.h> 16 #include <soc/mcm/memregs.h> 17 #include <soc/iproc.h> 18 #include <bcm/cpri.h> 19 #include <sal/compiler.h> 20 21 #ifdef CPRI_DIAG_SUPPORT 22 int 23 cpri_timesync_reset(int unit) 24 { 25 uint32 rval=0; 26 SOC_IF_ERROR_RETURN 27 (READ_NS_TIMESYNC_TS1_FREQ_CTRL_FRAC_LOWERr(unit, &rval)); 28 soc_reg_field_set(unit, NS_TIMESYNC_TS1_FREQ_CTRL_FRAC_LOWERr, &rval, LINCf, 0x0); 29 SOC_IF_ERROR_RETURN 30 (WRITE_NS_TIMESYNC_TS1_FREQ_CTRL_FRAC_LOWERr(unit, rval)); 31 32 SOC_IF_ERROR_RETURN 33 (READ_NS_TIMESYNC_TS1_COUNTER_ENABLEr(unit, &rval)); 34 soc_reg_field_set(unit, NS_TIMESYNC_TS1_COUNTER_ENABLEr, &rval, ENABLEf, 1); 35 SOC_IF_ERROR_RETURN 36 (WRITE_NS_TIMESYNC_TS1_COUNTER_ENABLEr(unit, rval)); 37 return SOC_E_NONE; 38 39 } 40 41 int sv_testing_cb(int unit, 42 bcm_port_t port, 43 bcm_cpri_interrupt_data_t *data, 44 void *userdata) 45 46 { 47 uint64 offset ; 48 uint32 lo, lo1, lo2; 49 uint32 hi, hi1, hi2; 50 bcm_cpri_tx_frame_tgen_config_t tgen_config; 51 bcm_cpri_1588_timestamp_ts_config_t cmic_config; 52 53 cpri_timesync_reset(unit); 54 cmic_config.modulo_count = 1; 55 cmic_config.enable = 1; 56 bcm_cpri_port_1588_timestamp_ts_config_set(unit, port, BCM_CPRI_DIR_TX, BCM_CPRI_1588_TS_TYPE_CMIC, &cmic_config); 57 bcm_cpri_port_1588_timestamp_ts_config_set(unit, port, BCM_CPRI_DIR_RX, BCM_CPRI_1588_TS_TYPE_CMIC, &cmic_config); 58 59 hi2 = 0x25; 60 lo2 = 0x373B3100; 61 lo1 = COMPILER_64_LO(data->data64[0]); 62 hi1 = COMPILER_64_HI(data->data64[0]); 63 lo = lo1 + lo2; 64 if (lo < lo1) { 65 hi = hi1 + hi2 + 1; 66 } else { 67 hi = hi1 + hi2; 68 } 69 70 COMPILER_64_SET(offset, hi, lo); 71 72 tgen_config.tx_tgen_ts_offset = offset ; 73 bcm_cpri_port_tx_frame_tgen_config_set(unit, port, 1, &tgen_config); 74 75 return 0; 76 } 77 78 int sv_testing_polling(int unit, 79 bcm_port_t port) 80 81 { 82 bcm_cpri_1588_timestamp_ts_config_t cmic_config; 83 bcm_cpri_1588_timestamp_t config; 84 int count =0; 85 86 while (count==0) { 87 bcm_cpri_port_1588_timestamp_get(unit, port,BCM_CPRI_DIR_RX, 88 BCM_CPRI_1588_TS_TYPE_SW, 89 1, &count, &config); 90 } 91 cpri_timesync_reset(unit); 92 cmic_config.modulo_count = 1; 93 cmic_config.enable = 1; 94 bcm_cpri_port_1588_timestamp_ts_config_set(unit, port, BCM_CPRI_DIR_RX, BCM_CPRI_1588_TS_TYPE_CMIC, &cmic_config); 95 bcm_cpri_port_1588_timestamp_ts_config_set(unit, port, BCM_CPRI_DIR_TX, BCM_CPRI_1588_TS_TYPE_CMIC, &cmic_config); 96 97 return 0; 98 } 99 100 void cpri_diag_test_interrupt_cb(int unit, 101 bcm_port_t port, 102 bcm_cpri_interrupt_data_t *data, 103 void *user_data) 104 105 { 106 uint32 user_info = 0xDADADADA; 107 108 if (user_data != NULL) { 109 user_info = *(uint32*)user_data ; 110 } 111 LOG_CLI((" cpri_diag_test_interrupt_CN u=%d port=%d user_data=0x%x",unit,port,user_info)); 112 LOG_CLI(("\n Interrupt is Served ID = %d %d %d 0x%x ....\n",data->cpri_intr_type, data->axc_id, data->queue_num, user_info)); 113 114 return ; 115 } 116 117 void cpri_diag_test_interrupt_cb2(int unit, 118 bcm_port_t port, 119 bcm_cpri_interrupt_data_t *data, 120 void *user_data) 121 122 { 123 uint32 user_info = 0xDADADADA; 124 125 if (user_data != NULL) { 126 user_info = *(uint32*)user_data ; 127 } 128 LOG_CLI((" cpri_diag_test_interrupt_cb2 u=%d port=%d user_data=0x%x",unit,port,user_info)); 129 LOG_CLI(("\n Interrupt is Served ID = %d %d %d 0x%x ....\n",data->cpri_intr_type, data->axc_id, data->queue_num, user_info)); 130 131 return ; 132 } 133 134 void cpri_diag_test_capture_interrupt_cb(int unit, 135 bcm_port_t port, 136 bcm_cpri_interrupt_data_t *data, 137 void *user_data) 138 139 { 140 #if 0 141 uint32 user_info = 0xDADADADA; 142 bcm_cpri_1588_timestamp_ts_config_t cmic_config; 143 144 cpri_timesync_reset(unit); 145 cmic_config.modulo_count = 1; 146 cmic_config.enable = 1; 147 bcm_cpri_port_1588_timestamp_ts_config_set(unit, port, BCM_CPRI_DIR_RX, BCM_CPRI_1588_TS_TYPE_CMIC, &cmic_config); 148 bcm_cpri_port_1588_timestamp_ts_config_set(unit, port, BCM_CPRI_DIR_TX, BCM_CPRI_1588_TS_TYPE_CMIC, &cmic_config); 149 if (user_data != NULL) { 150 user_info = *(uint32*)user_data ; 151 } 152 LOG_CLI(("capture_interrupt_cb u=%d port=%d user_data=0x%x\n",unit,port,user_info)); 153 LOG_CLI(("Interrupt is Served ID = %d ....\n",data->cpri_intr_type)); 154 #endif 155 LOG_CLI(("CAP %d 0x%x 0x%x\n",data->data, 156 COMPILER_64_HI(data->data64[0]), 157 COMPILER_64_LO(data->data64[0]))); 158 159 return ; 160 } 161 int fifo_counter =0; 162 void cpri_diag_test_fifo_interrupt_cb(int unit, 163 bcm_port_t port, 164 bcm_cpri_interrupt_data_t *data, 165 void *user_data) 166 167 { 168 int index; 169 #if 0 170 uint32 user_info = 0xABABABAB; 171 172 if (user_data != NULL) { 173 user_info = *(uint32*)user_data ; 174 } 175 LOG_CLI((" fifo_interrupt_cb u=%d port=%d user_data=0x%x",unit,port,user_info)); 176 LOG_CLI(("\n Interrupt is Served ID = %d ....\n",data->cpri_intr_type)); 177 #endif 178 for (index = 0; index < data->data; index++) { 179 LOG_CLI(("FI %d 0x%x 0x%x\n",data->data, 180 COMPILER_64_HI(data->data64[index]), 181 COMPILER_64_LO(data->data64[index]))); 182 } 183 if (fifo_counter++ > 10){ 184 bcm_cpri_port_interrupt_enable_set(0,port, 185 BCM_CPRI_INTR_RX_1588_TS_FIFO, 186 0, 187 0); /* enable/disable */ 188 fifo_counter =0; 189 } 190 191 return ; 192 } 193 194 uint32 user_int_data = 0xDEADBEEF; 195 int cpri_diag_test_register_interrupt_callback( int unit, int port) 196 { 197 bcm_cpri_port_interrupt_callback_register(unit, 198 BCM_CPRI_INTR_RX_PCS_LINK_STATUS_LH, 199 cpri_diag_test_interrupt_cb, 200 &user_int_data); 201 202 bcm_cpri_port_interrupt_callback_register(0, 203 BCM_CPRI_INTR_RX_ENCAP_CTRL_Q_OVERFLOW, 204 cpri_diag_test_interrupt_cb2, 205 &user_int_data); 206 #if 0 207 bcm_cpri_port_interrupt_callback_register(unit, 208 BCM_CPRI_INTR_RX_PCS_LINK_STATUS_LL, 209 cpri_diag_test_interrupt_cb, 210 &user_int_data); 211 212 bcm_cpri_port_interrupt_callback_register(unit, 213 BCM_CPRI_INTR_RX_1588_CAPTURED_TS, 214 cpri_diag_test_capture_interrupt_cb, 215 &user_int_data); 216 217 bcm_cpri_port_interrupt_callback_register(unit, 218 BCM_CPRI_INTR_TX_1588_CAPTURED_TS, 219 cpri_diag_test_capture_interrupt_cb, 220 &user_int_data); 221 222 bcm_cpri_port_interrupt_callback_register(unit, 223 BCM_CPRI_INTR_RX_1588_TS_FIFO, 224 cpri_diag_test_fifo_interrupt_cb, 225 &user_int_data); 226 227 bcm_cpri_port_interrupt_callback_register(unit, 228 BCM_CPRI_INTR_TX_1588_TS_FIFO, 229 cpri_diag_test_fifo_interrupt_cb, 230 &user_int_data); 231 #endif 232 return 0; 233 } 234 235 #endif /* CPRI_DIAG_SUPPORT */ 236