soc_cint_data.c (79028B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * soc_cint_data.c 9 * 10 * Hand-coded support for a few SAL core routines. 11 */ 12 int soc_core_cint_data_not_empty; 13 #include <sdk_config.h> 14 15 #if defined(INCLUDE_LIB_CINT) 16 17 #include <cint_config.h> 18 #include <cint_types.h> 19 #include <cint_porting.h> 20 #include <soc/property.h> 21 #include <soc/drv.h> 22 #include <soc/intr.h> 23 #include <soc/i2c.h> 24 #include <soc/cmic.h> 25 #include <soc/sbusdma.h> 26 #include <shared/util.h> 27 #include <shared/bitop.h> 28 #if defined(BCM_PETRA_SUPPORT) && defined(INCLUDE_KBP) && !defined(BCM_88030) 29 #include <soc/dpp/ARAD/arad_kbp.h> 30 #include <soc/dpp/ARAD/arad_kbp_rop.h> 31 #endif 32 33 #if defined(BCM_PETRA_SUPPORT) 34 #include <soc/dpp/ARAD/arad_dram.h> 35 #include <soc/dpp/DRC/drc_combo28_init.h> 36 #include <soc/dpp/DRC/drc_combo28_cb.h> 37 #include <soc/dpp/DRC/drc_combo28.h> 38 #endif 39 40 /* cmicx diag additions */ 41 42 static cint_parameter_desc_t __cint_parameters__soc_sbd_dm_cb_f[] = 43 { 44 { 45 "void", 46 "r", 47 0, 48 0 49 }, 50 { 51 "int", 52 "unit", 53 0, 54 0 55 }, 56 { 57 "int", 58 "status", 59 0, 60 0 61 }, 62 { 63 "sbusdma_desc_handle_t", 64 "handle", 65 0, 66 0 67 }, 68 { 69 "void", 70 "data", 71 1, 72 0 73 }, 74 CINT_ENTRY_LAST 75 }; 76 77 static cint_parameter_desc_t __cint_parameters__isr_chain_done_t[] = 78 { 79 { 80 "void", 81 "r", 82 0, 83 0 84 }, 85 { 86 "int", 87 "i", 88 0, 89 0 90 }, 91 { 92 "dv_t*", 93 "dv", 94 1, 95 0 96 }, 97 CINT_ENTRY_LAST 98 }; 99 100 static cint_parameter_desc_t __cint_parameters__isr_reload_done_t[] = 101 { 102 { 103 "void", 104 "r", 105 0, 106 0 107 }, 108 { 109 "int", 110 "i", 111 0, 112 0 113 }, 114 { 115 "dv_t*", 116 "dv", 117 1, 118 0 119 }, 120 CINT_ENTRY_LAST 121 }; 122 123 static cint_parameter_desc_t __cint_parameters__isr_desc_done_t[] = 124 { 125 { 126 "void", 127 "r", 128 0, 129 0 130 }, 131 { 132 "int", 133 "i", 134 0, 135 0 136 }, 137 { 138 "dv_t*", 139 "dv", 140 1, 141 0 142 }, 143 { 144 "dcb_t*", 145 "dcb", 146 1, 147 0 148 }, 149 CINT_ENTRY_LAST 150 }; 151 152 static void 153 __cint_fpointer__soc_sbd_dm_cb_f(int unit, 154 int status, 155 sbusdma_desc_handle_t handle, 156 void *data); 157 158 static void 159 __cint_fpointer__isr_chain_done_t(int i, dv_t *dv); 160 161 static void 162 __cint_fpointer__isr_reload_done_t(int i, dv_t *dv); 163 164 static void 165 __cint_fpointer__isr_desc_done_t(int i,dv_t *dv,dcb_t * dcb); 166 167 /* end cmicx diag additions */ 168 169 170 static cint_function_pointer_t __cint_soc_function_pointers[] = 171 { 172 173 /* cmicx diag additions */ 174 175 { 176 "soc_sbd_dm_cb_f", 177 (cint_fpointer_t) __cint_fpointer__soc_sbd_dm_cb_f, 178 __cint_parameters__soc_sbd_dm_cb_f 179 }, 180 { 181 "isr_chain_done_t", 182 (cint_fpointer_t) __cint_fpointer__isr_chain_done_t, 183 __cint_parameters__isr_chain_done_t 184 }, 185 { 186 "isr_reload_done_t", 187 (cint_fpointer_t) __cint_fpointer__isr_reload_done_t, 188 __cint_parameters__isr_reload_done_t 189 }, 190 { 191 "isr_desc_done_t", 192 (cint_fpointer_t) __cint_fpointer__isr_desc_done_t, 193 __cint_parameters__isr_desc_done_t 194 }, 195 196 /* end cmicx diag additions */ 197 198 CINT_ENTRY_LAST 199 }; 200 201 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 202 soc_init, \ 203 int,int,unit,0,0); 204 205 CINT_FWRAPPER_CREATE_RP2(char*,char,1,0, 206 soc_property_get_str, 207 int,int,unit,0,0, 208 char*,char,name,1,0); 209 210 CINT_FWRAPPER_CREATE_RP3(void*, void, 1, 0, 211 soc_cm_salloc, 212 int,int,unit,0,0, 213 int,int,size,0,0, 214 void*,void,name,1,0); 215 216 CINT_FWRAPPER_CREATE_VP2(soc_cm_sfree, 217 int,int,unit,0,0, 218 void*,void,ptr,1,0); 219 220 CINT_FWRAPPER_CREATE_RP3(uint32,uint32,0,0, 221 soc_property_get, 222 int,int,unit,0,0, 223 char*,char,name,1,0, 224 uint32,uint32,def,0,0); 225 CINT_FWRAPPER_CREATE_RP3(pbmp_t,pbmp_t,0,0, 226 soc_property_get_pbmp, 227 int,int,unit,0,0, 228 char*,char,name,1,0, 229 int,int,defneg,0,0); 230 231 CINT_FWRAPPER_CREATE_RP3(pbmp_t,pbmp_t,0,0, 232 soc_property_get_pbmp_default, 233 int,int,unit,0,0, 234 char*,char,name,1,0, 235 pbmp_t,pbmp_t,def,0,0); 236 237 CINT_FWRAPPER_CREATE_RP3(char*,char,1,0, 238 soc_property_port_get_str, 239 int,int,unit,0,0, 240 int,int,port,0,0, 241 char*,char,name,1,0); 242 243 CINT_FWRAPPER_CREATE_RP4(uint32,uint32,0,0, 244 soc_property_port_get, 245 int,int,unit,0,0, 246 int,int,port,0,0, 247 char*,char,name,1,0, 248 uint32,uint32,def,0,0); 249 250 CINT_FWRAPPER_CREATE_RP5(uint32,uint32,0,0, 251 soc_property_suffix_num_get, 252 int,int,unit,0,0, 253 int,int,tc,0,0, 254 char*,char,name,1,0, 255 char*,char,suffix,1,0, 256 uint32,uint32,def,0,0); 257 258 CINT_FWRAPPER_CREATE_RP4(uint32,uint32,0,0, 259 soc_property_cos_get, 260 int,int,unit,0,0, 261 soc_cos_t,soc_cos_t,cos,0,0, 262 char*,char,name,1,0, 263 uint32,uint32,def,0,0); 264 265 #if defined(BCM_ESW_SUPPORT) 266 /* additions for cmicx diagnostic tests */ 267 268 /* for schan and sbus tests */ 269 CINT_FWRAPPER_CREATE_RP6(int,int,0,0, 270 soc_mem_read_range, 271 int,int,unit,0,0, 272 int,int,mem,0,0, /* actually soc_mem_t */ 273 int,int,copyno,0,0, 274 int,int,index_min,0,0, 275 int,int,index_max,0,0, 276 void *,void,buffer,1,0); 277 278 CINT_FWRAPPER_CREATE_RP6(int,int,0,0, 279 soc_mem_write_range, 280 int,int,unit,0,0, 281 int,int,mem,0,0, /* actually soc_mem_t */ 282 int,int,copyno,0,0, 283 int,int,index_min,0,0, 284 int,int,index_max,0,0, 285 void *,void,buffer,1,0); 286 287 CINT_FWRAPPER_CREATE_RP6(unsigned int,unsigned int,0,0, /* actually uint32 */ 288 soc_mem_addr_get, 289 int,int,unit,0,0, 290 int,int,mem,0,0, /* actually soc_mem_t */ 291 int,int,array_index,0,0, /* actually unsigned */ 292 int,int,block,0,0, /* actually soc_block_t */ 293 int,int,index,0,0, 294 uint8 *,uint8,acc_type,1,0); 295 296 #if defined(BCM_ESW_SUPPORT) || \ 297 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 298 #ifdef BCM_SBUSDMA_SUPPORT 299 300 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 301 soc_sbusdma_desc_create, 302 int,int,unit,0,0, 303 soc_sbusdma_desc_ctrl_t *,soc_sbusdma_desc_ctrl_t,ctrl,1,0, 304 soc_sbusdma_desc_cfg_t *,soc_sbusdma_desc_cfg_t,cfg,1,0, 305 sbusdma_desc_handle_t *,sbusdma_desc_handle_t,desc_handle,1,0); 306 307 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 308 soc_sbusdma_desc_run, 309 int,int,unit,0,0, 310 sbusdma_desc_handle_t,sbusdma_desc_handle_t,desc_handle,0,0); 311 312 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 313 soc_sbusdma_desc_delete, 314 int,int,unit,0,0, 315 sbusdma_desc_handle_t,sbusdma_desc_handle_t,handle,0,0); 316 #endif 317 #endif 318 CINT_FWRAPPER_CREATE_VP9(soc_schan_header_cmd_set, 319 int,int,unit,0,0, 320 void*,void,header,1,0, /* should actually be schan_header_t* */ 321 int,int,opcode,0,0, 322 int,int,dst_blk,0,0, 323 int,int,src_blk,0,0, 324 int,int,acc_type,0,0, 325 int,int,data_byte_len,0,0, 326 int,int,dma,0,0, 327 uint32,uint32,bank_ignore_mask,0,0); 328 329 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 330 soc_schan_op, 331 int,int,unit,0,0, 332 void*,void,msg,1,0, /* should actually be schan_msg_t* */ 333 int,int,dwc_write,0,0, 334 int,int,dwc_read,0,0, 335 int,int,intr,0,0); 336 337 CINT_FWRAPPER_CREATE_VP8(soc_schan_header_status_get, 338 int,int,unit,0,0, 339 void*,void,header,1,0, /* should actually be schan_header_t* */ 340 int *,int,opcode,1,0, 341 int *,int,src_blk,1,0, 342 int *,int,data_byte_len,1,0, 343 int *,int,err,1,0, 344 int *,int,ecode,1,0, 345 int *,int,nack,1,0); 346 347 CINT_FWRAPPER_CREATE_VP3(soc_schan_dump, 348 int,int,unit,0,0, 349 schan_msg_t *,schan_msg_t,msg,1,0, 350 int,int,dwc,0,0); 351 352 CINT_FWRAPPER_CREATE_RP1(int,int,0,0, 353 soc_attach, 354 int,int,unit,0,0); 355 356 CINT_FWRAPPER_CREATE_RP1(int,int,0,0, 357 soc_detach, 358 int,int,unit,0,0); 359 360 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 361 soc_mem_clear, 362 int,int,unit,0,0, 363 soc_mem_t,soc_mem_t,mem,0,0, 364 int,int,copyno,0,0, 365 int,int,force_all,0,0); 366 367 int MACRO_soc_mem_entry_words(int unit,int mem) { 368 return soc_mem_entry_words(unit,mem); 369 } 370 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 371 MACRO_soc_mem_entry_words, 372 int,int,unit,0,0, 373 int,int,mem,0,0); 374 375 int MACRO_SOC_MEM_BLOCK_ANY(int unit,int mem) { 376 return SOC_MEM_BLOCK_ANY(unit,mem); 377 } 378 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 379 MACRO_SOC_MEM_BLOCK_ANY, 380 int,int,unit,0,0, 381 int,int,mem,0,0); 382 383 /* for packet dma tests */ 384 #ifdef SOC_PCI_DEBUG 385 CINT_FWRAPPER_CREATE_RP2(uint32,uint32,0,0, 386 soc_pci_read, 387 int,int,unit,0,0, 388 uint32,uint32,addr,0,0); 389 390 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 391 soc_pci_write, 392 int,int,unit,0,0, 393 uint32,uint32,addr,0,0, 394 uint32,uint32,data,0,0); 395 #else 396 uint32 MACRO_soc_pci_read(int unit,uint32 addr) { 397 return soc_pci_read(unit,addr); 398 } 399 CINT_FWRAPPER_CREATE_RP2(uint32,uint32,0,0, 400 MACRO_soc_pci_read, 401 int,int,unit,0,0, 402 uint32,uint32,addr,0,0); 403 404 int MACRO_soc_pci_write(int unit,uint32 addr,uint32 data) { 405 return soc_pci_write(unit,addr,data); 406 } 407 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 408 MACRO_soc_pci_write, 409 int,int,unit,0,0, 410 uint32,uint32,addr,0,0, 411 uint32,uint32,data,0,0); 412 #endif 413 414 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 415 soc_mem_read, 416 int,int,unit,0,0, 417 soc_mem_t,soc_mem_t,mem,0,0, 418 int,int,copyno,0,0, 419 int,int,index,0,0, 420 void*,void,entry_data,1,0); 421 422 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 423 soc_mem_write, 424 int,int,unit,0,0, 425 soc_mem_t,soc_mem_t,mem,0,0, 426 int,int,copyno,0,0, 427 int,int,index,0,0, 428 void*,void,entry_data,1,0); 429 430 CINT_FWRAPPER_CREATE_VP5(soc_mem_field32_set, 431 int,int,unit,0,0, 432 soc_mem_t,soc_mem_t,mem,0,0, 433 void*,void,entbuf,1,0, 434 soc_field_t,soc_field_t,field,0,0, 435 uint32,uint32,value,0,0); 436 437 CINT_FWRAPPER_CREATE_RP1(int,int,0,0, 438 soc_mem_scan_stop, 439 int,int,unit,0,0); 440 441 CINT_FWRAPPER_CREATE_RP6(int,int,0,0, 442 soc_reg_fields32_modify, 443 int,int,unit,0,0, 444 soc_reg_t,soc_reg_t,reg,0,0, 445 soc_port_t,soc_port_t,port,0,0, 446 int,int,field_count,0,0, 447 soc_field_t*,soc_field_t,fields,1,0, 448 uint32*,uint32,values,1,0); 449 450 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 451 soc_reg_field32_modify, 452 int,int,unit,0,0, 453 soc_reg_t,soc_reg_t,reg,0,0, 454 soc_port_t,soc_port_t,port,0,0, 455 soc_field_t,soc_field_t,field,0,0, 456 uint32,uint32,value,0,0); 457 458 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 459 soc_reg_get, 460 int,int,unit,0,0, 461 soc_reg_t,soc_reg_t,reg,0,0, 462 int,int,port,0,0, 463 int,int,index,0,0, 464 uint64*,uint64,data,1,0); 465 466 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 467 soc_reg_set, 468 int,int,unit,0,0, 469 soc_reg_t,soc_reg_t,reg,0,0, 470 int,int,port,0,0, 471 int,int,index,0,0, 472 uint64,uint64,data,0,0); 473 474 #if defined(SAL_HAS_ATOMIC_ALLOC) 475 CINT_FWRAPPER_CREATE_RP3(void*,void,1,0, 476 soc_at_alloc, 477 int,int,dev,0,0, 478 int,int,size,0,0, 479 char*,char,name,1,0); /* should actually be const char * */ 480 CINT_FWRAPPER_CREATE_VP2(soc_at_free, 481 int,int,dev,0,0, 482 void*,void,ptr,1,0); 483 #else 484 void *MACRO_soc_at_alloc(int dev,int size,char *name) { 485 return soc_at_alloc(dev,size,name); 486 } 487 CINT_FWRAPPER_CREATE_RP3(void*,void,1,0, 488 MACRO_soc_at_alloc, 489 int,int,dev,0,0, 490 int,int,size,0,0, 491 char*,char,name,1,0); /* should actually be const char * */ 492 void MACRO_soc_at_free(int dev,void *ptr) { 493 soc_at_free(dev,ptr); 494 } 495 CINT_FWRAPPER_CREATE_VP2(MACRO_soc_at_free, 496 int,int,dev,0,0, 497 void*,void,ptr,1,0); 498 #endif 499 500 CINT_FWRAPPER_CREATE_VP1(soc_linkscan_pause, 501 int,int,unit,0,0); 502 503 CINT_FWRAPPER_CREATE_RP1(int,int,0,0, 504 soc_counter_stop, 505 int,int,unit,0,0); 506 507 CINT_FWRAPPER_CREATE_RP1(int,int,0,0, 508 soc_reset_init, 509 int,int,unit,0,0); 510 #ifdef BCM_CMIC_SUPPORT 511 CINT_FWRAPPER_CREATE_RP1(int,int,0,0, 512 soc_dma_init, 513 int,int,unit,0,0); 514 515 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 516 soc_dma_attach, 517 int,int,unit,0,0, 518 int,int,reset,0,0); 519 520 CINT_FWRAPPER_CREATE_RP1(int,int,0,0, 521 soc_dma_abort, 522 int,int,unit,0,0); 523 524 CINT_FWRAPPER_CREATE_RP8(int,int,0,0, 525 soc_dma_desc_add, 526 dv_t*,dv_t,dv,1,0, 527 sal_vaddr_t,sal_vaddr_t,addr,0,0, 528 uint16,uint16,cnt,0,0, 529 pbmp_t,pbmp_t,pbmp,0,0, 530 pbmp_t,pbmp_t,ubmp,0,0, 531 pbmp_t,pbmp_t,l3pbm,0,0, 532 uint32,uint32,flags,0,0, 533 uint32*,uint32,hgh,1,0); 534 535 CINT_FWRAPPER_CREATE_VP1(soc_dma_desc_end_packet, 536 dv_t*,dv_t,dv,1,0); 537 538 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 539 soc_dma_rld_desc_add, 540 dv_t*,dv_t,dv,1,0, 541 sal_vaddr_t,sal_vaddr_t,addr,0,0); 542 543 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 544 soc_dma_chan_config, 545 int,int,unit,0,0, 546 dma_chan_t,dma_chan_t,chan,0,0, 547 dvt_t,dvt_t,type,0,0, 548 uint32,uint32,flags,0,0); 549 550 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 551 soc_dma_abort_dv, 552 int,int,unit,0,0, 553 dv_t*,dv_t,dv,0,0); 554 555 CINT_FWRAPPER_CREATE_VP2(soc_dma_dv_reset, 556 dvt_t,dvt_t,dvt,0,0, 557 dv_t*,dv_t,dv,1,0); 558 559 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 560 soc_dma_start, 561 int,int,unit,0,0, 562 dma_chan_t,dma_chan_t,chan,0,0, 563 dv_t*,dv_t,dv,1,0); 564 565 CINT_FWRAPPER_CREATE_VP3(soc_dma_dump_dv, 566 int,int,unit,0,0, 567 char*,char,pfx,1,0, 568 dv_t*,dv_t,dv,1,0); 569 570 CINT_FWRAPPER_CREATE_RP3(dv_t*,dv_t,1,0, 571 soc_dma_dv_alloc, 572 int,int,unit,0,0, 573 dvt_t,dvt_t,dvt,0,0, 574 int,int,cnt,0,0); 575 576 CINT_FWRAPPER_CREATE_VP2(soc_dma_dv_free, 577 int,int,unit,0,0, 578 dv_t*,dv_t,dv,1,0); 579 #endif 580 581 int MACRO_soc_mem_index_max(int unit,unsigned mem) { 582 return soc_mem_index_max(unit,mem); 583 } 584 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 585 MACRO_soc_mem_index_max, 586 int,int,unit,0,0, 587 unsigned,unsigned,mem,0,0); 588 589 /* end additions for cmicx diagnostic tests */ 590 #endif /* BCM_ESW_SUPPORT */ 591 592 #if defined(BCM_ESW_SUPPORT) 593 #if defined(INCLUDE_I2C) 594 595 596 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 597 soc_i2c_read_byte, 598 int,int,unit,0,0, 599 uint8,uint8,saddr,0,0, 600 uint8*,uint8,value,1,0); 601 602 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 603 soc_i2c_write_byte, 604 int,int,unit,0,0, 605 uint8,uint8,saddr,0,0, 606 uint8,uint8,value,0,0); 607 608 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 609 soc_i2c_read_word, 610 int,int,unit,0,0, 611 uint8,uint8,saddr,0,0, 612 uint16*,uint16,value,1,0); 613 614 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 615 soc_i2c_write_word, 616 int,int,unit,0,0, 617 uint8,uint8,saddr,0,0, 618 uint16,uint16,value,0,0); 619 620 621 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 622 soc_i2c_read_byte_data, 623 int,int,unit,0,0, 624 uint8,uint8,saddr,0,0, 625 uint8,uint8,com,0,0, 626 uint8*,uint8,value,1,0); 627 628 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 629 soc_i2c_write_byte_data, 630 int,int,unit,0,0, 631 uint8,uint8,saddr,0,0, 632 uint8,uint8,com,0,0, 633 uint8,uint8,value,0,0); 634 635 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 636 soc_i2c_read_word_data, 637 int,int,unit,0,0, 638 uint8,uint8,saddr,0,0, 639 uint8,uint8,com,0,0, 640 uint16*,uint16,value,1,0); 641 642 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 643 soc_i2c_write_word_data, 644 int,int,unit,0,0, 645 uint8,uint8,saddr,0,0, 646 uint8,uint8,com,0,0, 647 uint16,uint16,value,0,0); 648 649 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 650 soc_i2c_block_read, 651 int,int,unit,0,0, 652 uint8,uint8,saddr,0,0, 653 uint8,uint8,com,0,0, 654 uint8*,uint8,n,1,0, 655 uint8*,uint8,d,1,0); 656 657 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 658 soc_i2c_block_write, 659 int,int,unit,0,0, 660 uint8,uint8,saddr,0,0, 661 uint8,uint8,com,0,0, 662 uint8,uint8,n,0,0, 663 uint8*,uint8,d,1,0); 664 665 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 666 soc_i2c_multi_write, 667 int,int,unit,0,0, 668 uint8,uint8,saddr,0,0, 669 uint8,uint8,com,0,0, 670 uint8,uint8,n,0,0, 671 uint8*,uint8,d,1,0); 672 673 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 674 soc_i2c_probe, \ 675 int,int,unit,0,0); 676 #endif 677 CINT_FWRAPPER_CREATE_RP1(uint16, uint16, 0, 0, 678 _shr_swap16, \ 679 uint16,uint16,val,0,0); 680 #endif 681 682 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 683 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 684 soc_reg_bits, 685 int,int,unit,0,0, 686 int,int,reg,0,0); 687 688 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 689 soc_reg_field_length, 690 int,int,unit,0,0, 691 int,int,reg,0,0, 692 int,int,field,0,0); 693 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 694 soc_active_interrupts_get, 695 int,int,unit,0,0, 696 int,int,flags,0,0, 697 int,int,max_interrupts_size,0,0, 698 soc_interrupt_cause_t*,soc_interrupt_cause_t,interrupts,1,0, 699 int*,int,total_interrupts,1,0); 700 701 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 702 soc_nof_interrupts, 703 int,int,unit,0,0, 704 int*,int,nof_interrupts,1,0); 705 706 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 707 soc_interrupt_info_get, 708 int,int,unit,0,0, 709 int,int,interrupt_id,0,0, 710 soc_interrupt_db_t*,soc_interrupt_db_t,inter,1,0); 711 712 CINT_FWRAPPER_CREATE_RP6(int,int,0,0, 713 soc_get_interrupt_id, 714 int,int,unit,0,0, 715 int,int,reg,0,0, 716 int,int,reg_index,0,0, 717 int,int,field,0,0, 718 int,int,bit_in_field,0,0, 719 int*,int,interrupt_id,1,0); 720 721 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 722 soc_get_interrupt_id_specific, 723 int,int,unit,0,0, 724 int,int,reg_adress,0,0, 725 int,int,reg_block,0,0, 726 int,int,field_bit,0,0, 727 int*,int,interrupt_id,1,0); 728 729 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 730 soc_interrupt_is_supported, 731 int,int,unit,0,0, 732 int,int,block_instance,0,0, 733 int,int,inter_id,0,0); 734 735 #if defined(BCM_PETRA_SUPPORT) && defined(INCLUDE_KBP) && !defined(BCM_88030) 736 737 CINT_FWRAPPER_CREATE_RP3(uint32,uint32,0,0, 738 arad_kbp_cpu_lookup_reply, 739 uint32,uint32,core,0,0, 740 int,int,unit,0,0, 741 uint32*,uint32,data,1,0); 742 743 CINT_FWRAPPER_CREATE_RP5(uint32,uint32,0,0, 744 arad_kbp_cpu_record_send, 745 int,int,unit,0,0, 746 uint32,uint32,opcode,0,0, 747 uint32*,uint32,msb_data,1,0, 748 uint32*,uint32,lsb_data,1,0, 749 int,int,lsb_enable,0,0); 750 CINT_FWRAPPER_CREATE_RP7(uint32,uint32,0,0, 751 aradplus_kbp_cpu_record_send, 752 int,int,unit,0,0, 753 uint32,uint32,core,0,0, 754 uint32,uint32,opcode,0,0, 755 uint32*,uint32,msb_data,1,0, 756 uint32*,uint32,lsb_data,1,0, 757 int,int,lsb_enable,0,0, 758 soc_reg_above_64_val_t,soc_reg_above_64_val_t,read_data,0,0); 759 760 CINT_FWRAPPER_CREATE_RP5(uint32,uint32,0,0, 761 arad_kbp_lut_write, 762 int,int,unit,0,0, 763 uint32,uint32,core,0,0, 764 uint8,uint8,addr,0,0, 765 arad_kbp_lut_data_t*,arad_kbp_lut_data_t,lut_data,1,0, 766 uint32*,uint32,lut_data_row,1,0); 767 768 CINT_FWRAPPER_CREATE_RP5(uint32,uint32,0,0, 769 arad_kbp_lut_read, 770 int,int,unit,0,0, 771 uint32,uint32,core,0,0, 772 uint8,uint8,addr,0,0, 773 arad_kbp_lut_data_t*,arad_kbp_lut_data_t,lut_data,1,0, 774 uint32*,uint32,lut_data_row,1,0); 775 776 CINT_FWRAPPER_CREATE_RP3(uint32,uint32,0,0, 777 arad_kbp_rop_write, 778 int,int,unit,0,0, 779 uint32,uint32,core,0,0, 780 arad_kbp_rop_write_t*,arad_kbp_rop_write_t,wr_data,1,0); 781 782 CINT_FWRAPPER_CREATE_RP3(uint32,uint32,0,0, 783 arad_kbp_rop_read, 784 int,int,unit,0,0, 785 uint32,uint32,core,0,0, 786 arad_kbp_rop_read_t*,arad_kbp_rop_read_t,rd_data,1,0); 787 788 CINT_FWRAPPER_CREATE_RP4(uint32,uint32,0,0, 789 arad_kbp_rop_ad_write, 790 int,int,unit,0,0, 791 uint32,uint32,core,0,0, 792 uint8*,uint8,wr_data,1,0, 793 uint16,uint16,length,0,0); 794 795 #endif /* #if defined(BCM_PETRA_SUPPORT) && defined(INCLUDE_KBP) */ 796 797 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 798 soc_port_phy_pll_os_set, 799 int,int,unit,0,0, 800 int,int,port,0,0, 801 uint32,uint32,vco_freq,0,0, 802 uint32,uint32,oversample_mode,0,0, 803 uint32,uint32,pll_divider,0,0); 804 805 #if defined(BCM_PETRA_SUPPORT) 806 /* 807 * Dram user access access functions 808 */ 809 CINT_FWRAPPER_CREATE_RP4(uint32,uint32,0,0, 810 arad_dram_logical2physical_addr_mapping, 811 int,int,unit,0,0, 812 int,int,buf_num,0,0, 813 int,int,index,0,0, 814 uint32*,uint32,phy_addr,1,0); 815 816 CINT_FWRAPPER_CREATE_RP6(int,int,0,0, 817 soc_arad_user_buffer_dram_access, 818 int,int,unit,0,0, 819 uint32,uint32,flags,0,0, 820 uint32,uint32,access_type,0,0, 821 uint8*,uint8,buf,1,0, 822 int,int,offset,0,0, 823 int,int,nbytes,0,0); 824 825 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 826 soc_arad_user_buffer_dram_read, 827 int,int,unit,0,0, 828 uint32,uint32,flags,0,0, 829 uint8*,uint8,buf,1,0, 830 int,int,offset,0,0, 831 int,int,nbytes,0,0); 832 833 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 834 soc_arad_user_buffer_dram_write, 835 int,int,unit,0,0, 836 uint32,uint32,flags,0,0, 837 uint8*,uint8,buf,1,0, 838 int,int,offset,0,0, 839 int,int,nbytes,0,0); 840 841 /* 842 * DRC init functions 843 */ 844 845 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 846 soc_dpp_drc_combo28_dprc_out_of_reset, 847 int,int,unit,0,0, 848 int,int,dram_ndx,0,0); 849 850 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 851 soc_dpp_drc_combo28_drc_clam_shell_cfg, 852 int,int,dram_ndx,0,0, 853 int,int,init,0,0); 854 855 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 856 soc_dpp_drc_combo28_drc_soft_init, 857 int,int,unit,0,0, 858 int,int,dram_ndx,0,0, 859 int,int,init,0,0); 860 /* 861 * Shmoo library functions 862 */ 863 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 864 soc_combo28_shmoo_phy_cfg_pll, 865 int,int,unit,0,0, 866 int,int,dram_ndx,0,0); 867 868 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 869 soc_combo28_shmoo_phy_init, 870 int,int,unit,0,0, 871 int,int,dram_ndx,0,0); 872 873 /* 874 * CallBack Functions 875 */ 876 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 877 soc_dpp_drc_combo28_shmoo_phy_reg_read, 878 int,int,unit,0,0, 879 int,int,dram_ndx,0,0, 880 uint32,uint32,addr,0,0, 881 uint32*,uint32,data,1,0); 882 883 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 884 soc_dpp_drc_combo28_shmoo_phy_reg_write, 885 int,int,unit,0,0, 886 int,int,dram_ndx,0,0, 887 uint32,uint32,addr,0,0, 888 uint32,uint32,data,0,0); 889 890 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 891 soc_dpp_drc_combo28_shmoo_phy_reg_modify, 892 int,int,unit,0,0, 893 int,int,dram_ndx,0,0, 894 uint32,uint32,addr,0,0, 895 uint32,uint32,data,0,0, 896 uint32,uint32,mask,0,0); 897 898 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 899 soc_dpp_drc_combo28_shmoo_drc_trigger_dram_init, 900 int,int,unit,0,0, 901 int,int,dram_ndx,0,0); 902 903 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 904 soc_dpp_drc_combo28_shmoo_wait_dram_init_done, 905 int,int,unit,0,0, 906 int,int,dram_ndx,0,0); 907 908 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 909 soc_dpp_drc_combo28_shmoo_load_mrs, 910 int,int,unit,0,0, 911 int,int,dram_ndx,0,0, 912 uint32,uint32,mrs_num,0,0, 913 uint32,uint32,mrs_opcode,0,0); 914 915 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 916 soc_dpp_drc_combo28_shmoo_drc_enable_adt, 917 int,int,unit,0,0, 918 int,int,dram_ndx,0,0, 919 int,int,action,0,0); 920 921 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 922 soc_dpp_drc_combo28_shmoo_drc_enable_wck2ck_training, 923 int,int,unit,0,0, 924 int,int,dram_ndx,0,0, 925 int,int,action,0,0); 926 927 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 928 soc_dpp_drc_combo28_shmoo_drc_pll_set, 929 int,int,unit,0,0, 930 int,int,dram_ndx,0,0, 931 CONST combo28_drc_pll_t*,combo28_drc_pll_t,pll_info,1,0); 932 933 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 934 soc_dpp_drc_combo28_shmoo_drc_enable_write_leveling, 935 int,int,unit,0,0, 936 int,int,drc_ndx,0,0, 937 uint32,uint32,command_parity_lattency,0,0, 938 int,int,use_continious_gddr5_dqs,0,0, 939 int,int,enable,0,0); 940 941 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 942 soc_dpp_drc_combo28_shmoo_drc_mpr_en, 943 int,int,unit,0,0, 944 int,int,drc_ndx,0,0, 945 int,int,enable,0,0); 946 947 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 948 soc_dpp_drc_combo28_shmoo_drc_enable_gddr5_training_protocol, 949 int,int,unit,0,0, 950 int,int,drc_ndx,0,0, 951 int,int,enable,0,0); 952 953 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 954 soc_dpp_drc_combo28_shmoo_vendor_info_get, 955 int,int,unit,0,0, 956 int,int,drc_ndx,0,0, 957 combo28_vendor_info_t*,combo28_vendor_info_t,info,1,0); 958 959 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 960 soc_dpp_drc_combo28_shmoo_drc_dqs_pulse_gen, 961 int,int,unit,0,0, 962 int,int,drc_ndx,0,0, 963 int, int, use_continious_gddr5_dqs,0 ,0); 964 965 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 966 soc_dpp_drc_combo28_shmoo_dram_init, 967 int,int,unit,0,0, 968 int,int,drc_ndx,0,0, 969 int, int, phase,0 ,0); 970 971 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 972 soc_dpp_drc_combo28_shmoo_modify_mrs, 973 int,int,unit,0,0, 974 int,int,drc_ndx,0,0, 975 uint32, uint32, mr_ndx, 0 ,0, 976 uint32, uint32, data, 0 ,0, 977 uint32, uint32, mask, 0 ,0); 978 979 CINT_FWRAPPER_CREATE_RP8(int,int,0,0, 980 soc_dpp_drc_combo28_dram_cpu_command, 981 int,int,unit,0,0, 982 int,int,drc_ndx,0,0, 983 uint32, uint32, ras_n, 0 ,0, 984 uint32, uint32, cas_n, 0 ,0, 985 uint32, uint32, we_n, 0 ,0, 986 uint32, uint32, act_n, 0 ,0, 987 uint32, uint32, bank, 0 ,0, 988 uint32, uint32, address, 0 ,0); 989 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 990 soc_dpp_drc_combo28_shmoo_drc_bist_conf_set, 991 int,int,unit,0,0, 992 int,int,drc_ndx,0,0, 993 combo28_bist_info_t,combo28_bist_info_t,info,0,0); 994 995 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 996 soc_dpp_drc_combo28_shmoo_drc_bist_err_cnt, 997 int,int,unit,0,0, 998 int,int,drc_ndx,0,0, 999 combo28_bist_err_cnt_t*,combo28_bist_err_cnt_t,info,1,0); 1000 1001 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1002 soc_dpp_drc_combo28_gddr5_shmoo_drc_bist_conf_set, 1003 int,int,unit,0,0, 1004 int,int,drc_ndx,0,0, 1005 combo28_gddr5_bist_info_t,combo28_gddr5_bist_info_t,info,0,0); 1006 1007 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1008 soc_dpp_drc_combo28_gddr5_shmoo_drc_bist_err_cnt, 1009 int,int,unit,0,0, 1010 int,int,drc_ndx,0,0, 1011 combo28_gddr5_bist_err_cnt_t*,combo28_gddr5_bist_err_cnt_t,info,1,0); 1012 1013 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1014 soc_dpp_drc_combo28_gddr5_shmoo_drc_dq_byte_pairs_swap_info_get, 1015 int,int,unit,0,0, 1016 int,int,drc_ndx,0,0, 1017 int*,int, pairs_were_swapped,1,0); 1018 1019 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 1020 soc_dpp_drc_combo28_shmoo_drc_precharge_all, 1021 int,int,unit,0,0, 1022 int,int,drc_ndx,0,0); 1023 1024 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 1025 soc_dpp_drc_combo28_shmoo_drc_active_gddr5_cmd, 1026 int,int,unit,0,0, 1027 int,int,drc_ndx,0,0); 1028 1029 CINT_FWRAPPER_CREATE_RP7(int,int,0,0, 1030 soc_dpp_drc_combo28_shmoo_write_mpr, 1031 int,int,unit,0,0, 1032 int,int,drc_ndx,0,0, 1033 uint32, uint32, intial_calib_mpr_addr, 0 ,0, 1034 uint32, uint32, mpr_mode, 0 ,0, 1035 uint32, uint32, mpr_page, 0 ,0, 1036 uint32, uint32, mrs_readout, 0 ,0, 1037 int, int, enable_mpr, 0 ,0); 1038 1039 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1040 soc_dpp_drc_combo28_shmoo_mpr_load, 1041 int,int,unit,0,0, 1042 int,int,drc_ndx,0,0, 1043 uint8*, uint8, mpr_pattern, 1 ,0); 1044 1045 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1046 soc_dpp_drc_combo28_shmoo_enable_wr_crc, 1047 int,int,unit,0,0, 1048 int,int,drc_ndx,0,0, 1049 int,int,enable,0,0); 1050 1051 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1052 soc_dpp_drc_combo28_shmoo_enable_rd_crc, 1053 int,int,unit,0,0, 1054 int,int,drc_ndx,0,0, 1055 int,int,enable,0,0); 1056 1057 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1058 soc_dpp_drc_combo28_shmoo_enable_wr_dbi, 1059 int,int,unit,0,0, 1060 int,int,drc_ndx,0,0, 1061 int,int,enable,0,0); 1062 1063 CINT_FWRAPPER_CREATE_RP3(int,int,0,0, 1064 soc_dpp_drc_combo28_shmoo_enable_rd_dbi, 1065 int,int,unit,0,0, 1066 int,int,drc_ndx,0,0, 1067 int,int,enable,0,0); 1068 1069 CINT_FWRAPPER_CREATE_RP5(int,int,0,0, 1070 soc_dpp_drc_combo28_shmoo_enable_refresh, 1071 int,int,unit,0,0, 1072 int,int,drc_ndx,0,0, 1073 int,int,enable,0,0, 1074 uint32,uint32,new_trefi,0,0, 1075 uint32*,uint32,curr_refi,1,0); 1076 1077 CINT_FWRAPPER_CREATE_RP4(int,int,0,0, 1078 soc_dpp_drc_combo28_shmoo_force_dqs, 1079 int,int,unit,0,0, 1080 int,int,drc_ndx,0,0, 1081 uint32,uint32,force_dqs_val,0,0, 1082 uint32,uint32,force_dqs_oeb,0,0); 1083 1084 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 1085 soc_dpp_drc_combo28_soft_reset_drc_without_dram, 1086 int,int,unit,0,0, 1087 int,int,drc_ndx,0,0); 1088 1089 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 1090 soc_dpp_drc_combo28_shmoo_dram_info_access, 1091 int,int,unit,0,0, 1092 combo28_shmoo_dram_info_t**,combo28_shmoo_dram_info_t,shmoo_info,0,0); 1093 1094 CINT_FWRAPPER_CREATE_RP2(int,int,0,0, 1095 soc_dpp_drc_combo28_shmoo_vendor_info_access, 1096 int,int,unit,0,0, 1097 combo28_vendor_info_t**,combo28_vendor_info_t,vendor_info,0,0); 1098 1099 #endif /* BCM_PETRA_SUPPORT */ 1100 1101 #endif /* defined(BCM_ESW_SUPPORT) || defined(BCM_DFE_SUPPORT)|| defined(BCM_PETRA_SUPPORT) || defined(BCM_DNXF_SUPPORT) */ 1102 1103 1104 /* cmicx diags additions */ 1105 1106 static void 1107 __cint_fpointer__soc_sbd_dm_cb_f(int unit, 1108 int status, 1109 sbusdma_desc_handle_t handle, 1110 void *data) 1111 { 1112 cint_interpreter_callback(__cint_soc_function_pointers+0, 1113 4, 1114 0, 1115 &unit, 1116 &status, 1117 &handle, 1118 &data); 1119 } 1120 1121 static void 1122 __cint_fpointer__isr_chain_done_t(int i, dv_t *dv) 1123 { 1124 cint_interpreter_callback(__cint_soc_function_pointers+1, 1125 2, 1126 0, 1127 &i, 1128 &dv); 1129 } 1130 1131 static void 1132 __cint_fpointer__isr_reload_done_t(int i, dv_t *dv) 1133 { 1134 cint_interpreter_callback(__cint_soc_function_pointers+2, 1135 2, 1136 0, 1137 &i, 1138 &dv); 1139 } 1140 1141 static void 1142 __cint_fpointer__isr_desc_done_t(int i, dv_t *dv,dcb_t * dcb) 1143 { 1144 cint_interpreter_callback(__cint_soc_function_pointers+3, 1145 3, 1146 0, 1147 &i, 1148 &dv, 1149 &dcb); 1150 } 1151 1152 /* end cmicx diag additions */ 1153 1154 /* additions for cmicx diagnostic tests */ 1155 1156 /* soc_sbusdma_desc_ctrl_t */ 1157 static cint_parameter_desc_t __cint_struct_members__soc_sbusdma_desc_ctrl_t[] = 1158 { 1159 1160 {"uint32","flags",0,0}, 1161 {"char","name",0,16}, 1162 {"uint32","cfg_count",0,0}, 1163 {"void","hw_desc",1,0}, 1164 {"void","buff",1,0}, 1165 {"soc_sbd_dm_cb_f","cb",0,0}, 1166 {"void","data",1,0}, 1167 CINT_ENTRY_LAST 1168 1169 }; 1170 static void* 1171 __cint_maddr__soc_sbusdma_desc_ctrl_t(void* p, int mnum, cint_struct_type_t* parent) 1172 { 1173 soc_sbusdma_desc_ctrl_t* s = (soc_sbusdma_desc_ctrl_t*) p; 1174 1175 switch(mnum) { 1176 case 0: return &(s->flags); 1177 case 1: return &(s->name); 1178 case 2: return &(s->cfg_count); 1179 case 3: return &(s->hw_desc); 1180 case 4: return &(s->buff); 1181 case 5: return &(s->cb); 1182 case 6: return &(s->data); 1183 default: return NULL; 1184 } 1185 } 1186 1187 /* soc_sbusdma_desc_cfg_t */ 1188 static cint_parameter_desc_t __cint_struct_members__soc_sbusdma_desc_cfg_t[] = 1189 { 1190 1191 {"int","acc_type",0,0,}, 1192 {"uint32","blk",0,0}, 1193 {"uint32","addr",0,0}, 1194 {"uint32","width",0,0}, 1195 {"uint32","count",0,0}, 1196 {"uint32","addr_shift",0,0}, 1197 {"void","buff",1,0}, 1198 CINT_ENTRY_LAST 1199 1200 }; 1201 static void* 1202 __cint_maddr__soc_sbusdma_desc_cfg_t(void* p, int mnum, cint_struct_type_t* parent) 1203 { 1204 soc_sbusdma_desc_cfg_t* s = (soc_sbusdma_desc_cfg_t*) p; 1205 1206 switch(mnum) { 1207 case 0: return &(s->acc_type); 1208 case 1: return &(s->blk); 1209 case 2: return &(s->addr); 1210 case 3: return &(s->width); 1211 case 4: return &(s->count); 1212 case 5: return &(s->addr_shift); 1213 case 6: return &(s->buff); 1214 default: return NULL; 1215 } 1216 } 1217 1218 /* dv_t */ 1219 static cint_parameter_desc_t __cint_struct_members__dv_t[] = 1220 { 1221 1222 {"int","dv_unit",0,0,}, 1223 {"int","dv_cnt",0,0}, 1224 {"int","dv_vcnt",0,0}, 1225 {"int","dv_flags",0,0}, 1226 {"void*","dv_dcb",1,0}, 1227 CINT_ENTRY_LAST 1228 1229 }; 1230 static void* 1231 __cint_maddr__dv_t(void* p, int mnum, cint_struct_type_t* parent) 1232 { 1233 dv_t* s = (dv_t*) p; 1234 1235 switch(mnum) { 1236 case 0: return &(s->dv_unit); 1237 case 1: return &(s->dv_cnt); 1238 case 2: return &(s->dv_vcnt); 1239 case 3: return &(s->dv_flags); 1240 case 4: return &(s->dv_dcb); 1241 default: return NULL; 1242 } 1243 } 1244 1245 /* end additions for cmicx diagnostic tests */ 1246 1247 1248 1249 #define TEST_TCAM 1250 1251 #ifdef BCM_PETRA_SUPPORT 1252 #ifdef TEST_TCAM 1253 1254 #include <soc/dpp/ARAD/arad_tbl_access.h> 1255 1256 1257 #include <bcm_int/dpp/error.h> 1258 1259 1260 static uint32 1261 arad_pp_ihb_tcam_tbl_read_unsafe_lcl( 1262 SOC_SAND_IN int unit, 1263 SOC_SAND_IN uint32 bank_ndx, 1264 SOC_SAND_IN uint32 nof_entries_in_line, 1265 SOC_SAND_IN uint32 entry_offset, 1266 SOC_SAND_OUT ARAD_PP_IHB_TCAM_BANK_TBL_DATA *data 1267 ) 1268 { 1269 uint32 1270 soc_sand_rc; 1271 1272 soc_sand_rc = arad_pp_ihb_tcam_tbl_read_unsafe(unit, bank_ndx, nof_entries_in_line, entry_offset, data); 1273 if(SOC_SAND_FAILURE(soc_sand_rc)){ 1274 return -1; 1275 } 1276 return 0; 1277 } 1278 1279 1280 static uint32 1281 arad_pp_ihb_tcam_tbl_write_unsafe_lcl( 1282 SOC_SAND_IN int unit, 1283 SOC_SAND_IN uint32 bank_ndx, 1284 SOC_SAND_IN uint32 nof_entries_in_line, 1285 SOC_SAND_IN uint32 entry_offset, 1286 SOC_SAND_IN ARAD_PP_IHB_TCAM_BANK_TBL_DATA *data 1287 ) 1288 { 1289 uint32 1290 soc_sand_rc; 1291 1292 soc_sand_rc = arad_pp_ihb_tcam_tbl_write_unsafe(unit, bank_ndx, nof_entries_in_line, entry_offset, data); 1293 if(SOC_SAND_FAILURE(soc_sand_rc)){ 1294 return -1; 1295 } 1296 return 0; 1297 } 1298 1299 static uint32 1300 arad_pp_ihb_tcam_tbl_compare_unsafe_lcl( 1301 SOC_SAND_IN int unit, 1302 SOC_SAND_IN uint32 bank_ndx, 1303 SOC_SAND_IN uint32 nof_entries_in_line, 1304 SOC_SAND_IN ARAD_PP_IHB_TCAM_BANK_TBL_DATA *compare_data, 1305 SOC_SAND_OUT ARAD_PP_IHB_TCAM_COMPARE_DATA *found_data 1306 ) 1307 { 1308 uint32 1309 soc_sand_rc; 1310 1311 soc_sand_rc = arad_pp_ihb_tcam_tbl_compare_unsafe(unit, bank_ndx, nof_entries_in_line, compare_data, found_data); 1312 if(SOC_SAND_FAILURE(soc_sand_rc)){ 1313 return -1; 1314 } 1315 return 0; 1316 } 1317 1318 1319 CINT_FWRAPPER_CREATE_RP5(uint32, uint32, 0, 0, 1320 arad_pp_ihb_tcam_tbl_read_unsafe_lcl, 1321 uint32, uint32, unit, 0, 0, 1322 uint32, uint32, bank_ndx, 0, 0, 1323 uint32, uint32, nof_entries_in_line, 0, 0, 1324 uint32, uint32, entry_offset, 0, 0, 1325 ARAD_PP_IHB_TCAM_BANK_TBL_DATA*, ARAD_PP_IHB_TCAM_BANK_TBL_DATA, data, 1, 0); 1326 1327 CINT_FWRAPPER_CREATE_RP5(uint32, uint32, 0, 0, 1328 arad_pp_ihb_tcam_tbl_write_unsafe_lcl, 1329 uint32, uint32, unit, 0, 0, 1330 uint32, uint32, bank_ndx, 0, 0, 1331 uint32, uint32, nof_entries_in_line, 0, 0, 1332 uint32, uint32, entry_offset, 0, 0, 1333 ARAD_PP_IHB_TCAM_BANK_TBL_DATA*, ARAD_PP_IHB_TCAM_BANK_TBL_DATA, data, 1, 0); 1334 1335 CINT_FWRAPPER_CREATE_RP5(uint32, uint32, 0, 0, 1336 arad_pp_ihb_tcam_tbl_compare_unsafe_lcl, 1337 uint32, uint32, unit, 0, 0, 1338 uint32, uint32, bank_ndx, 0, 0, 1339 uint32, uint32, nof_entries_in_line, 0, 0, 1340 ARAD_PP_IHB_TCAM_BANK_TBL_DATA*, ARAD_PP_IHB_TCAM_BANK_TBL_DATA, compare_data, 1, 0, 1341 ARAD_PP_IHB_TCAM_COMPARE_DATA*, ARAD_PP_IHB_TCAM_COMPARE_DATA, found_data, 1, 0); 1342 1343 #endif 1344 #endif /* BCM_PETRA_SUPPORT */ 1345 1346 /* 1347 * bitop macros 1348 */ 1349 static void __SHR_BITSET(uint32* data, int n) { SHR_BITSET(data, n); } 1350 CINT_FWRAPPER_CREATE_VP2(__SHR_BITSET, uint32*,int,data,1,0,int,int,n,0,0); 1351 1352 static void __SHR_BITCLR(uint32* data, int n) { SHR_BITCLR(data, n); } 1353 CINT_FWRAPPER_CREATE_VP2(__SHR_BITCLR, uint32*,int,data,1,0,int,int,n,0,0); 1354 1355 static int __SHR_BITGET(uint32* data, int n) {return SHR_BITGET(data, n); } 1356 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, __SHR_BITGET, uint32*,int,data,1,0,int,int,n,0,0); 1357 1358 static cint_function_t __cint_soc_functions[] = 1359 { 1360 CINT_FWRAPPER_ENTRY(soc_init), 1361 CINT_FWRAPPER_ENTRY(soc_property_get_str), 1362 CINT_FWRAPPER_ENTRY(soc_property_get), 1363 CINT_FWRAPPER_ENTRY(soc_property_get_pbmp), 1364 CINT_FWRAPPER_ENTRY(soc_property_get_pbmp_default), 1365 CINT_FWRAPPER_ENTRY(soc_property_port_get_str), 1366 CINT_FWRAPPER_ENTRY(soc_property_port_get), 1367 CINT_FWRAPPER_ENTRY(soc_property_suffix_num_get), 1368 CINT_FWRAPPER_ENTRY(soc_property_cos_get), 1369 CINT_FWRAPPER_ENTRY(soc_cm_salloc), 1370 CINT_FWRAPPER_ENTRY(soc_cm_sfree), 1371 #if defined(BCM_ESW_SUPPORT) 1372 1373 /* additions for cmicx diagnostic tests */ 1374 1375 /* for schan and sbus tests */ 1376 CINT_FWRAPPER_ENTRY(soc_mem_read_range), 1377 CINT_FWRAPPER_ENTRY(soc_mem_write_range), 1378 CINT_FWRAPPER_ENTRY(soc_mem_addr_get), 1379 #if defined(BCM_ESW_SUPPORT) || \ 1380 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 1381 #ifdef BCM_SBUSDMA_SUPPORT 1382 CINT_FWRAPPER_ENTRY(soc_sbusdma_desc_create), 1383 CINT_FWRAPPER_ENTRY(soc_sbusdma_desc_run), 1384 CINT_FWRAPPER_ENTRY(soc_sbusdma_desc_delete), 1385 #endif 1386 #endif 1387 CINT_FWRAPPER_ENTRY(soc_schan_header_cmd_set), 1388 CINT_FWRAPPER_ENTRY(soc_schan_op), 1389 CINT_FWRAPPER_ENTRY(soc_schan_header_status_get), 1390 CINT_FWRAPPER_ENTRY(soc_schan_dump), 1391 CINT_FWRAPPER_ENTRY(soc_attach), 1392 CINT_FWRAPPER_ENTRY(soc_detach), 1393 CINT_FWRAPPER_ENTRY(soc_mem_clear), 1394 CINT_FWRAPPER_ENTRY(MACRO_soc_mem_entry_words), 1395 CINT_FWRAPPER_ENTRY(MACRO_SOC_MEM_BLOCK_ANY), 1396 1397 /* for packet dma tests */ 1398 #ifdef SOC_PCI_DEBUG 1399 CINT_FWRAPPER_ENTRY(soc_pci_read), 1400 CINT_FWRAPPER_ENTRY(soc_pci_write), 1401 #else 1402 CINT_FWRAPPER_ENTRY(MACRO_soc_pci_read), 1403 CINT_FWRAPPER_ENTRY(MACRO_soc_pci_write), 1404 #endif 1405 CINT_FWRAPPER_ENTRY(soc_mem_read), 1406 CINT_FWRAPPER_ENTRY(soc_mem_write), 1407 CINT_FWRAPPER_ENTRY(soc_mem_field32_set), 1408 CINT_FWRAPPER_ENTRY(soc_mem_scan_stop), 1409 CINT_FWRAPPER_ENTRY(soc_reg_fields32_modify), 1410 CINT_FWRAPPER_ENTRY(soc_reg_field32_modify), 1411 CINT_FWRAPPER_ENTRY(soc_reg_get), 1412 CINT_FWRAPPER_ENTRY(soc_reg_set), 1413 #if defined(SAL_HAS_ATOMIC_ALLOC) 1414 CINT_FWRAPPER_ENTRY(soc_at_alloc), 1415 CINT_FWRAPPER_ENTRY(soc_at_free), 1416 #else 1417 CINT_FWRAPPER_ENTRY(MACRO_soc_at_alloc), 1418 CINT_FWRAPPER_ENTRY(MACRO_soc_at_free), 1419 #endif 1420 CINT_FWRAPPER_ENTRY(soc_linkscan_pause), 1421 CINT_FWRAPPER_ENTRY(soc_counter_stop), 1422 CINT_FWRAPPER_ENTRY(soc_reset_init), 1423 #ifdef BCM_CMIC_SUPPORT 1424 CINT_FWRAPPER_ENTRY(soc_dma_init), 1425 CINT_FWRAPPER_ENTRY(soc_dma_attach), 1426 CINT_FWRAPPER_ENTRY(soc_dma_abort), 1427 CINT_FWRAPPER_ENTRY(soc_dma_desc_add), 1428 CINT_FWRAPPER_ENTRY(soc_dma_desc_end_packet), 1429 CINT_FWRAPPER_ENTRY(soc_dma_rld_desc_add), 1430 CINT_FWRAPPER_ENTRY(soc_dma_chan_config), 1431 CINT_FWRAPPER_ENTRY(soc_dma_abort_dv), 1432 CINT_FWRAPPER_ENTRY(soc_dma_dv_reset), 1433 CINT_FWRAPPER_ENTRY(soc_dma_start), 1434 CINT_FWRAPPER_ENTRY(soc_dma_dump_dv), 1435 CINT_FWRAPPER_ENTRY(soc_dma_dv_alloc), 1436 CINT_FWRAPPER_ENTRY(soc_dma_dv_free), 1437 #endif 1438 CINT_FWRAPPER_ENTRY(MACRO_soc_mem_index_max), 1439 1440 /* end additions for cmicx diagnostic tests */ 1441 #endif /* BCM_ESW_SUPPORT */ 1442 1443 #if defined(BCM_ESW_SUPPORT) 1444 #if defined(INCLUDE_I2C) 1445 1446 CINT_FWRAPPER_ENTRY(soc_i2c_read_byte), 1447 CINT_FWRAPPER_ENTRY(soc_i2c_write_byte), 1448 CINT_FWRAPPER_ENTRY(soc_i2c_read_byte_data), 1449 CINT_FWRAPPER_ENTRY(soc_i2c_write_byte_data), 1450 CINT_FWRAPPER_ENTRY(soc_i2c_read_word), 1451 CINT_FWRAPPER_ENTRY(soc_i2c_write_word), 1452 CINT_FWRAPPER_ENTRY(soc_i2c_read_word_data), 1453 CINT_FWRAPPER_ENTRY(soc_i2c_write_word_data), 1454 CINT_FWRAPPER_ENTRY(soc_i2c_block_read), 1455 CINT_FWRAPPER_ENTRY(soc_i2c_block_write), 1456 CINT_FWRAPPER_ENTRY(soc_i2c_multi_write), 1457 CINT_FWRAPPER_ENTRY(soc_i2c_probe), 1458 #endif 1459 CINT_FWRAPPER_ENTRY(_shr_swap16), 1460 #endif 1461 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 1462 CINT_FWRAPPER_ENTRY(soc_reg_bits), 1463 CINT_FWRAPPER_ENTRY(soc_reg_field_length), 1464 CINT_FWRAPPER_ENTRY(soc_nof_interrupts), 1465 CINT_FWRAPPER_ENTRY(soc_active_interrupts_get), 1466 CINT_FWRAPPER_ENTRY(soc_interrupt_info_get), 1467 CINT_FWRAPPER_ENTRY(soc_get_interrupt_id), 1468 CINT_FWRAPPER_ENTRY(soc_get_interrupt_id_specific), 1469 CINT_FWRAPPER_ENTRY(soc_interrupt_is_supported), 1470 CINT_FWRAPPER_ENTRY(soc_port_phy_pll_os_set), 1471 #ifdef BCM_PETRA_SUPPORT 1472 CINT_FWRAPPER_ENTRY(arad_dram_logical2physical_addr_mapping), 1473 CINT_FWRAPPER_ENTRY(soc_arad_user_buffer_dram_access), 1474 CINT_FWRAPPER_ENTRY(soc_arad_user_buffer_dram_read), 1475 CINT_FWRAPPER_ENTRY(soc_arad_user_buffer_dram_write), 1476 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_dprc_out_of_reset), 1477 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_drc_clam_shell_cfg), 1478 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_drc_soft_init), 1479 CINT_FWRAPPER_ENTRY(soc_combo28_shmoo_phy_cfg_pll), 1480 CINT_FWRAPPER_ENTRY(soc_combo28_shmoo_phy_init), 1481 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_phy_reg_read), 1482 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_phy_reg_write), 1483 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_phy_reg_modify), 1484 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_trigger_dram_init), 1485 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_wait_dram_init_done), 1486 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_load_mrs), 1487 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_enable_adt), 1488 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_enable_wck2ck_training), 1489 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_pll_set), 1490 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_enable_write_leveling), 1491 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_mpr_en), 1492 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_enable_gddr5_training_protocol), 1493 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_vendor_info_get), 1494 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_dqs_pulse_gen), 1495 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_dram_init), 1496 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_modify_mrs), 1497 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_dram_cpu_command), 1498 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_vendor_info_get), 1499 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_bist_conf_set), 1500 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_bist_err_cnt), 1501 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_gddr5_shmoo_drc_bist_conf_set), 1502 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_gddr5_shmoo_drc_bist_err_cnt), 1503 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_gddr5_shmoo_drc_dq_byte_pairs_swap_info_get), 1504 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_precharge_all), 1505 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_drc_active_gddr5_cmd), 1506 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_write_mpr), 1507 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_mpr_load), 1508 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_enable_wr_crc), 1509 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_enable_rd_crc), 1510 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_enable_wr_dbi), 1511 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_enable_rd_dbi), 1512 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_enable_refresh), 1513 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_force_dqs), 1514 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_soft_reset_drc_without_dram), 1515 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_dram_info_access), 1516 CINT_FWRAPPER_ENTRY(soc_dpp_drc_combo28_shmoo_vendor_info_access), 1517 1518 #endif 1519 #endif 1520 #ifdef BCM_PETRA_SUPPORT 1521 #if defined(INCLUDE_KBP) && !defined(BCM_88030) 1522 CINT_FWRAPPER_ENTRY(arad_kbp_cpu_lookup_reply), 1523 CINT_FWRAPPER_ENTRY(arad_kbp_cpu_record_send), 1524 CINT_FWRAPPER_ENTRY(aradplus_kbp_cpu_record_send), 1525 CINT_FWRAPPER_ENTRY(arad_kbp_lut_write), 1526 CINT_FWRAPPER_ENTRY(arad_kbp_lut_read), 1527 CINT_FWRAPPER_ENTRY(arad_kbp_rop_write), 1528 CINT_FWRAPPER_ENTRY(arad_kbp_rop_read), 1529 CINT_FWRAPPER_ENTRY(arad_kbp_rop_ad_write), 1530 #endif 1531 #ifdef TEST_TCAM 1532 CINT_FWRAPPER_ENTRY(arad_pp_ihb_tcam_tbl_read_unsafe_lcl), 1533 CINT_FWRAPPER_ENTRY(arad_pp_ihb_tcam_tbl_write_unsafe_lcl), 1534 CINT_FWRAPPER_ENTRY(arad_pp_ihb_tcam_tbl_compare_unsafe_lcl), 1535 #endif 1536 #endif /* BCM_PETRA_SUPPORT */ 1537 CINT_FWRAPPER_NENTRY("SHR_BITSET", __SHR_BITSET), 1538 CINT_FWRAPPER_NENTRY("SHR_BITGET", __SHR_BITGET), 1539 CINT_FWRAPPER_NENTRY("SHR_BITCLR", __SHR_BITCLR), 1540 1541 CINT_ENTRY_LAST 1542 1543 }; 1544 1545 #ifdef BCM_PETRA_SUPPORT 1546 #ifdef TEST_TCAM 1547 static cint_parameter_desc_t __cint_struct_members__ARAD_PP_IHB_TCAM_BANK_TBL_DATA[] = 1548 { 1549 { 1550 "uint32", 1551 "mask", 1552 0, 1553 ARAD_PP_IHB_TCAM_DATA_WIDTH 1554 }, 1555 { 1556 "uint32", 1557 "value", 1558 0, 1559 ARAD_PP_IHB_TCAM_DATA_WIDTH 1560 }, 1561 { 1562 "uint32", 1563 "valid", 1564 0, 1565 0 1566 }, 1567 { NULL } 1568 }; 1569 1570 static void* 1571 __cint_maddr__ARAD_PP_IHB_TCAM_BANK_TBL_DATA(void* p, int mnum, cint_struct_type_t* parent) 1572 { 1573 void* rv; 1574 ARAD_PP_IHB_TCAM_BANK_TBL_DATA* s = (ARAD_PP_IHB_TCAM_BANK_TBL_DATA*) p; 1575 1576 switch(mnum) 1577 { 1578 case 0: rv = &(s->mask); break; 1579 case 1: rv = &(s->value); break; 1580 case 2: rv = &(s->valid); break; 1581 default: rv = NULL; break; 1582 } 1583 1584 return rv; 1585 } 1586 1587 static cint_parameter_desc_t __cint_struct_members__ARAD_PP_IHB_TCAM_COMPARE_DATA[] = 1588 { 1589 { 1590 "uint32", 1591 "found", 1592 0, 1593 0 1594 }, 1595 { 1596 "uint32", 1597 "address", 1598 0, 1599 0 1600 }, 1601 {NULL} 1602 }; 1603 1604 static void* 1605 __cint_maddr__ARAD_PP_IHB_TCAM_COMPARE_DATA(void* p, int mnum, cint_struct_type_t* parent) 1606 { 1607 void* rv; 1608 ARAD_PP_IHB_TCAM_COMPARE_DATA* s = (ARAD_PP_IHB_TCAM_COMPARE_DATA*) p; 1609 1610 switch(mnum) 1611 { 1612 case 0: rv = &(s->found); break; 1613 case 1: rv = &(s->address); break; 1614 default: rv = NULL; break; 1615 } 1616 1617 return rv; 1618 } 1619 static cint_parameter_desc_t __cint_struct_members__combo28_drc_pll_t[] = 1620 { 1621 { 1622 "uint32", 1623 "iso_in", 1624 0, 1625 0 1626 }, 1627 { 1628 "uint32", 1629 "cp", 1630 0, 1631 0 1632 }, 1633 { 1634 "uint32", 1635 "cp1", 1636 0, 1637 0 1638 }, 1639 { 1640 "uint32", 1641 "cz", 1642 0, 1643 0 1644 }, 1645 { 1646 "uint32", 1647 "icp", 1648 0, 1649 0 1650 }, 1651 { 1652 "uint32", 1653 "rp", 1654 0, 1655 0 1656 }, 1657 { 1658 "uint32", 1659 "rz", 1660 0, 1661 0 1662 }, 1663 { 1664 "uint32", 1665 "ldo_ctrl", 1666 0, 1667 0 1668 }, 1669 { 1670 "uint32", 1671 "msc_ctrl", 1672 0, 1673 0 1674 }, 1675 { 1676 "uint32", 1677 "ndiv_frac", 1678 0, 1679 0 1680 }, 1681 { 1682 "uint32", 1683 "ndiv_int", 1684 0, 1685 0 1686 }, 1687 { 1688 "uint32", 1689 "pdiv", 1690 0, 1691 0 1692 }, 1693 { 1694 "uint32", 1695 "ssc_limit", 1696 0, 1697 0 1698 }, 1699 { 1700 "uint32", 1701 "ssc_mode", 1702 0, 1703 0 1704 }, 1705 { 1706 "uint32", 1707 "ssc_step", 1708 0, 1709 0 1710 }, 1711 { 1712 "uint32", 1713 "vco_gain", 1714 0, 1715 0 1716 }, 1717 { NULL } 1718 }; 1719 1720 static cint_parameter_desc_t __cint_struct_members__combo28_vendor_info_t[] = 1721 { 1722 { 1723 "uint32", 1724 "dram_density", 1725 0, 1726 0 1727 }, 1728 { 1729 "uint32", 1730 "fifo_depth", 1731 0, 1732 0 1733 }, 1734 { 1735 "uint32", 1736 "revision_id", 1737 0, 1738 0 1739 }, 1740 { 1741 "uint32", 1742 "manufacture_id", 1743 0, 1744 0 1745 }, 1746 { NULL } 1747 }; 1748 1749 1750 static cint_parameter_desc_t __cint_struct_members__combo28_bist_info_t[] = 1751 { 1752 { 1753 "uint32", 1754 "write_weight", 1755 0, 1756 0 1757 }, 1758 { 1759 "uint32", 1760 "read_weight", 1761 0, 1762 0 1763 }, 1764 { 1765 "uint32", 1766 "bist_timer_us", 1767 0, 1768 0 1769 }, 1770 { 1771 "uint32", 1772 "bist_num_actions", 1773 0, 1774 0 1775 }, 1776 { 1777 "uint32", 1778 "bist_start_address", 1779 0, 1780 0 1781 }, 1782 { 1783 "uint32", 1784 "bist_end_address", 1785 0, 1786 0 1787 }, 1788 { 1789 "int", 1790 "mpr_mode", 1791 0, 1792 0 1793 }, 1794 { NULL } 1795 }; 1796 1797 1798 1799 static cint_parameter_desc_t __cint_struct_members__combo28_gddr5_bist_info_t[] = 1800 { 1801 { 1802 "uint32", 1803 "fifo_depth", 1804 0, 1805 0 1806 }, 1807 { 1808 "int", 1809 "bist_mode", 1810 0, 1811 0 1812 }, 1813 { 1814 "uint32*", 1815 "data_pattern", 1816 1, 1817 0 1818 }, 1819 { 1820 "uint8*", 1821 "dbi_pattern", 1822 1, 1823 0 1824 }, 1825 { 1826 "uint8*", 1827 "edd_pattern", 1828 1, 1829 0 1830 }, 1831 { NULL } 1832 }; 1833 1834 static cint_parameter_desc_t __cint_struct_members__combo28_bist_err_cnt_t[] = 1835 { 1836 { 1837 "uint32", 1838 "uint32 bist_err_occur", 1839 0, 1840 0 1841 }, 1842 { 1843 "uint32", 1844 "uint32 bist_full_err_cnt", 1845 0, 1846 0 1847 }, 1848 { 1849 "uint32", 1850 "uint32 bist_single_err_cnt", 1851 0, 1852 0 1853 }, 1854 { 1855 "uint32", 1856 "uint32 bist_global_err_cnt", 1857 0, 1858 0 1859 }, 1860 { NULL } 1861 }; 1862 1863 1864 static cint_parameter_desc_t __cint_struct_members__combo28_gddr5_bist_err_cnt_t[] = 1865 { 1866 { 1867 "uint32", 1868 "uint32 bist_data_err_occur", 1869 0, 1870 0 1871 }, 1872 { 1873 "uint32", 1874 "uint32 bist_dbi_err_occur", 1875 0, 1876 0 1877 }, 1878 { 1879 "uint32", 1880 "uint32 bist_edc_err_occur", 1881 0, 1882 0 1883 }, 1884 { 1885 "uint32", 1886 "uint32 bist_adt_err_occur", 1887 0, 1888 0 1889 }, 1890 { NULL } 1891 }; 1892 1893 1894 static void* 1895 __cint_maddr__combo28_drc_pll_t(void* p, int mnum, cint_struct_type_t* parent) 1896 { 1897 void* rv; 1898 combo28_drc_pll_t* s = (combo28_drc_pll_t*) p; 1899 1900 switch(mnum) 1901 { 1902 case 0: rv = &(s->iso_in); break; 1903 case 1: rv = &(s->cp); break; 1904 case 2: rv = &(s->cp1); break; 1905 case 3: rv = &(s->cz); break; 1906 case 4: rv = &(s->icp); break; 1907 case 5: rv = &(s->rp); break; 1908 case 6: rv = &(s->rz); break; 1909 case 7: rv = &(s->ldo_ctrl); break; 1910 case 8: rv = &(s->msc_ctrl); break; 1911 case 9: rv = &(s->ndiv_frac); break; 1912 case 10: rv = &(s->ndiv_int); break; 1913 case 11: rv = &(s->pdiv); break; 1914 case 12: rv = &(s->ssc_limit); break; 1915 case 13: rv = &(s->ssc_mode); break; 1916 case 14: rv = &(s->ssc_step); break; 1917 case 15: rv = &(s->vco_gain); break; 1918 default: rv = NULL; break; 1919 } 1920 1921 return rv; 1922 } 1923 static void* 1924 __cint_maddr__combo28_vendor_info_t(void* p, int mnum, cint_struct_type_t* parent) 1925 { 1926 void* rv; 1927 combo28_vendor_info_t* s = (combo28_vendor_info_t*) p; 1928 1929 switch(mnum) 1930 { 1931 case 0: rv = &(s->dram_density); break; 1932 case 1: rv = &(s->fifo_depth); break; 1933 case 2: rv = &(s->revision_id); break; 1934 case 3: rv = &(s->manufacture_id); break; 1935 default: rv = NULL; break; 1936 } 1937 1938 return rv; 1939 } 1940 1941 static void* 1942 __cint_maddr__combo28_bist_info_t(void* p, int mnum, cint_struct_type_t* parent) 1943 { 1944 void* rv; 1945 combo28_bist_info_t* s = (combo28_bist_info_t*) p; 1946 1947 switch(mnum) 1948 { 1949 case 0: rv = &(s->write_weight); break; 1950 case 1: rv = &(s->read_weight); break; 1951 case 2: rv = &(s->bist_timer_us); break; 1952 case 3: rv = &(s->bist_num_actions); break; 1953 case 4: rv = &(s->bist_start_address); break; 1954 case 5: rv = &(s->bist_end_address); break; 1955 case 6: rv = &(s->mpr_mode); break; 1956 default: rv = NULL; break; 1957 } 1958 1959 return rv; 1960 } 1961 1962 1963 static void* 1964 __cint_maddr__combo28_gddr5_bist_info_t(void* p, int mnum, cint_struct_type_t* parent) 1965 { 1966 void* rv; 1967 combo28_gddr5_bist_info_t* s = (combo28_gddr5_bist_info_t*) p; 1968 1969 switch(mnum) 1970 { 1971 case 0: rv = &(s->fifo_depth); break; 1972 case 1: rv = &(s->bist_mode); break; 1973 case 2: rv = &(s->data_pattern); break; 1974 case 3: rv = &(s->dbi_pattern); break; 1975 case 4: rv = &(s->edc_pattern); break; 1976 default: rv = NULL; break; 1977 } 1978 1979 return rv; 1980 } 1981 1982 static void* 1983 __cint_maddr__combo28_bist_err_cnt_t(void* p, int mnum, cint_struct_type_t* parent) 1984 { 1985 void* rv; 1986 combo28_bist_err_cnt_t* s = (combo28_bist_err_cnt_t*) p; 1987 1988 switch(mnum) 1989 { 1990 case 0: rv = &(s->bist_err_occur); break; 1991 case 1: rv = &(s->bist_full_err_cnt); break; 1992 case 2: rv = &(s->bist_single_err_cnt); break; 1993 case 3: rv = &(s->bist_global_err_cnt); break; 1994 default: rv = NULL; break; 1995 } 1996 1997 return rv; 1998 } 1999 2000 2001 static void* 2002 __cint_maddr__combo28_gddr5_bist_err_cnt_t(void* p, int mnum, cint_struct_type_t* parent) 2003 { 2004 void* rv; 2005 combo28_gddr5_bist_err_cnt_t* s = (combo28_gddr5_bist_err_cnt_t*) p; 2006 2007 switch(mnum) 2008 { 2009 case 0: rv = &(s->bist_data_err_occur); break; 2010 case 1: rv = &(s->bist_dbi_err_occur); break; 2011 case 2: rv = &(s->bist_edc_err_occur); break; 2012 case 3: rv = &(s->bist_adt_err_occur); break; 2013 default: rv = NULL; break; 2014 } 2015 2016 return rv; 2017 } 2018 2019 2020 #endif 2021 #endif /* BCM_PETRA_SUPPORT */ 2022 static cint_parameter_desc_t __cint_struct_members__soc_interrupt_cause_t[] = 2023 { 2024 { 2025 "int", 2026 "id", 2027 0, 2028 0 2029 }, 2030 { 2031 "int", 2032 "index", 2033 0, 2034 0 2035 }, 2036 { NULL } 2037 }; 2038 2039 static cint_parameter_desc_t __cint_struct_members__soc_interrupt_db_t[] = 2040 { 2041 #if !defined(SOC_NO_NAMES) 2042 { 2043 "char", 2044 "name", 2045 1, 2046 0 2047 }, 2048 #endif 2049 { 2050 "int", 2051 "id", 2052 0, 2053 0 2054 }, 2055 { 2056 "int", 2057 "reg", 2058 0, 2059 0 2060 }, 2061 { 2062 "int", 2063 "reg_index", 2064 0, 2065 0 2066 }, 2067 { 2068 "int", 2069 "field", 2070 0, 2071 0 2072 }, 2073 { 2074 "int", 2075 "mask_reg", 2076 0, 2077 0 2078 }, 2079 { 2080 "int", 2081 "mask_reg_index", 2082 0, 2083 0 2084 }, 2085 { 2086 "int", 2087 "mask_field", 2088 0, 2089 0 2090 }, 2091 { 2092 "int", 2093 "vector_id", 2094 0, 2095 0 2096 }, 2097 { 2098 "soc_interrupt_tree_t", 2099 "vector_info", 2100 1, 2101 0 2102 }, 2103 { 2104 "soc_block_type_t", 2105 "block_type", 2106 0, 2107 0 2108 }, 2109 { 2110 "clear_func", 2111 "interrupt_clear", 2112 0, 2113 0 2114 }, 2115 { 2116 "void", 2117 "interrupt_clear_param1", 2118 1, 2119 0 2120 }, 2121 { 2122 "void", 2123 "interrupt_clear_param2", 2124 1, 2125 0 2126 }, 2127 { 2128 "uint32", 2129 "statistics_count", 2130 1, 2131 0 2132 }, 2133 { 2134 "uint32", 2135 "storm_detection_occurrences", 2136 1, 2137 0 2138 }, 2139 { 2140 "uint32", 2141 "storm_detection_start_time", 2142 1, 2143 0 2144 }, 2145 { 2146 "uint32", 2147 "storm_nominal_ct", 2148 1, 2149 0 2150 }, 2151 { 2152 "int", 2153 "bit_in_field", 2154 0, 2155 0 2156 }, 2157 { NULL } 2158 }; 2159 2160 static void* 2161 __cint_maddr__soc_interrupt_cause_t(void* p, int mnum, cint_struct_type_t* parent) 2162 { 2163 void* rv; 2164 soc_interrupt_cause_t* s = (soc_interrupt_cause_t*) p; 2165 2166 switch(mnum) 2167 { 2168 case 0: rv = &(s->id); break; 2169 case 1: rv = &(s->index); break; 2170 default: rv = NULL; break; 2171 } 2172 2173 return rv; 2174 } 2175 2176 static void* 2177 __cint_maddr__soc_interrupt_db_t(void* p, int mnum, cint_struct_type_t* parent) 2178 { 2179 void* rv; 2180 soc_interrupt_db_t* s = (soc_interrupt_db_t*) p; 2181 2182 switch(mnum) 2183 { 2184 #if !defined(SOC_NO_NAMES) 2185 case 0: rv = &(s->name); break; 2186 case 1: rv = &(s->id); break; 2187 case 2: rv = &(s->reg); break; 2188 case 3: rv = &(s->reg_index); break; 2189 case 4: rv = &(s->field); break; 2190 case 5: rv = &(s->mask_reg); break; 2191 case 6: rv = &(s->mask_reg_index); break; 2192 case 7: rv = &(s->mask_field); break; 2193 case 8: rv = &(s->vector_id); break; 2194 case 9: rv = &(s->vector_info); break; 2195 case 10: rv = &(s->block_type); break; 2196 case 11: rv = &(s->interrupt_clear); break; 2197 case 12: rv = &(s->interrupt_clear_param1); break; 2198 case 13: rv = &(s->interrupt_clear_param2); break; 2199 case 14: rv = &(s->statistics_count); break; 2200 case 15: rv = &(s->storm_detection_occurrences); break; 2201 case 16: rv = &(s->storm_detection_start_time); break; 2202 case 17: rv = &(s->storm_nominal_count); break; 2203 case 18: rv = &(s->bit_in_field); break; 2204 #else 2205 case 0: rv = &(s->id); break; 2206 case 1: rv = &(s->reg); break; 2207 case 2: rv = &(s->reg_index); break; 2208 case 3: rv = &(s->field); break; 2209 case 4: rv = &(s->mask_reg); break; 2210 case 5: rv = &(s->mask_reg_index); break; 2211 case 6: rv = &(s->mask_field); break; 2212 case 7: rv = &(s->vector_id); break; 2213 case 8: rv = &(s->vector_info); break; 2214 case 9: rv = &(s->block_type); break; 2215 case 10: rv = &(s->interrupt_clear); break; 2216 case 11: rv = &(s->interrupt_clear_param1); break; 2217 case 12: rv = &(s->interrupt_clear_param2); break; 2218 case 13: rv = &(s->statistics_count); break; 2219 case 14: rv = &(s->storm_detection_occurrences); break; 2220 case 15: rv = &(s->storm_detection_start_time); break; 2221 case 16: rv = &(s->storm_nominal_count); break; 2222 case 17: rv = &(s->bit_in_field); break; 2223 #endif 2224 default: rv = NULL; break; 2225 } 2226 2227 return rv; 2228 } 2229 2230 #if defined(BCM_PETRA_SUPPORT) && defined(INCLUDE_KBP) && !defined(BCM_88030) 2231 static cint_parameter_desc_t __cint_struct_members__arad_kbp_lut_data_t[] = 2232 { 2233 { 2234 "uint32", 2235 "rec_size", 2236 0, 2237 0 2238 }, 2239 { 2240 "uint32", 2241 "rec_type", 2242 0, 2243 0 2244 }, 2245 { 2246 "uint32", 2247 "rec_is_valid", 2248 0, 2249 0 2250 }, 2251 { 2252 "uint32", 2253 "mode", 2254 0, 2255 0 2256 }, 2257 { 2258 "uint32", 2259 "key_config", 2260 0, 2261 0 2262 }, 2263 { 2264 "uint32", 2265 "lut_key_data", 2266 0, 2267 0 2268 }, 2269 { 2270 "uint32", 2271 "instr", 2272 0, 2273 0 2274 }, 2275 { 2276 "uint32", 2277 "key_w_cpd_gt_80", 2278 0, 2279 0 2280 }, 2281 { 2282 "uint32", 2283 "copy_data_cfg", 2284 0, 2285 0 2286 }, 2287 { 2288 "uint32", 2289 "result_idx_ad_cfg[0]", 2290 0, 2291 0 2292 }, 2293 { 2294 "uint32", 2295 "result_idx_or_ad[0]", 2296 0, 2297 0 2298 }, 2299 { 2300 "uint32", 2301 "result_idx_ad_cfg[1]", 2302 0, 2303 0 2304 }, 2305 { 2306 "uint32", 2307 "result_idx_or_ad[1]", 2308 0, 2309 0 2310 }, 2311 { 2312 "uint32", 2313 "result_idx_ad_cfg[2]", 2314 0, 2315 0 2316 }, 2317 { 2318 "uint32", 2319 "result_idx_or_ad[2]", 2320 0, 2321 0 2322 }, 2323 { 2324 "uint32", 2325 "result_idx_ad_cfg[3]", 2326 0, 2327 0 2328 }, 2329 { 2330 "uint32", 2331 "result_idx_or_ad[3]", 2332 0, 2333 0 2334 }, 2335 { 2336 "uint32", 2337 "result_idx_ad_cfg[4]", 2338 0, 2339 0 2340 }, 2341 { 2342 "uint32", 2343 "result_idx_or_ad[4]", 2344 0, 2345 0 2346 }, 2347 { 2348 "uint32", 2349 "result_idx_ad_cfg[5]", 2350 0, 2351 0 2352 }, 2353 { 2354 "uint32", 2355 "result_idx_or_ad[5]", 2356 0, 2357 0 2358 }, 2359 { NULL } 2360 }; 2361 2362 static void* 2363 __cint_maddr__arad_kbp_lut_data_t(void* p, int mnum, cint_struct_type_t* parent) 2364 { 2365 void* rv; 2366 arad_kbp_lut_data_t* s = (arad_kbp_lut_data_t*) p; 2367 2368 switch(mnum) 2369 { 2370 case 0: rv = &(s->rec_size); break; 2371 case 1: rv = &(s->rec_type); break; 2372 case 2: rv = &(s->rec_is_valid); break; 2373 case 3: rv = &(s->mode); break; 2374 case 4: rv = &(s->key_config); break; 2375 case 5: rv = &(s->lut_key_data); break; 2376 case 6: rv = &(s->instr); break; 2377 case 7: rv = &(s->key_w_cpd_gt_80); break; 2378 case 8: rv = &(s->copy_data_cfg); break; 2379 case 9: rv = &(s->result_idx_ad_cfg[0]); break; 2380 case 10: rv = &(s->result_idx_or_ad[0]); break; 2381 case 11: rv = &(s->result_idx_ad_cfg[1]); break; 2382 case 12: rv = &(s->result_idx_or_ad[1]); break; 2383 case 13: rv = &(s->result_idx_ad_cfg[2]); break; 2384 case 14: rv = &(s->result_idx_or_ad[2]); break; 2385 case 15: rv = &(s->result_idx_ad_cfg[3]); break; 2386 case 16: rv = &(s->result_idx_or_ad[3]); break; 2387 case 17: rv = &(s->result_idx_ad_cfg[4]); break; 2388 case 18: rv = &(s->result_idx_or_ad[4]); break; 2389 case 19: rv = &(s->result_idx_ad_cfg[5]); break; 2390 case 20: rv = &(s->result_idx_or_ad[5]); break; 2391 default: rv = NULL; break; 2392 } 2393 2394 return rv; 2395 } 2396 2397 static cint_enum_map_t __cint_enum_map__NlmAradWriteMode[] = 2398 { 2399 { "NLM_ARAD_WRITE_MODE_DATABASE_DM", NLM_ARAD_WRITE_MODE_DATABASE_DM }, 2400 { "NLM_ARAD_WRITE_MODE_DATABASE_XY", NLM_ARAD_WRITE_MODE_DATABASE_XY }, 2401 { NULL } 2402 }; 2403 2404 static cint_parameter_desc_t __cint_struct_members__arad_kbp_rop_write_t[] = 2405 { 2406 { 2407 "uint8", 2408 "addr", 2409 0, 2410 NLMDEV_REG_ADDR_LEN_IN_BYTES 2411 }, 2412 { 2413 "uint8", 2414 "data", 2415 0, 2416 NLM_DATA_WIDTH_BYTES 2417 }, 2418 { 2419 "uint8", 2420 "mask", 2421 0, 2422 NLM_DATA_WIDTH_BYTES 2423 }, 2424 { 2425 "uint8", 2426 "addr_short", 2427 0, 2428 NLMDEV_REG_ADDR_LEN_IN_BYTES 2429 }, 2430 { 2431 "uint8", 2432 "vBit", 2433 0, 2434 0 2435 }, 2436 { 2437 "NlmAradWriteMode", 2438 "writeMode", 2439 0, 2440 0 2441 }, 2442 { NULL } 2443 }; 2444 2445 static void* 2446 __cint_maddr__arad_kbp_rop_write_t(void* p, int mnum, cint_struct_type_t* parent) 2447 { 2448 void* rv; 2449 arad_kbp_rop_write_t* s = (arad_kbp_rop_write_t*) p; 2450 2451 switch(mnum) 2452 { 2453 case 0: rv = &(s->addr); break; 2454 case 1: rv = &(s->data); break; 2455 case 2: rv = &(s->mask); break; 2456 case 3: rv = &(s->addr_short); break; 2457 case 4: rv = &(s->vBit); break; 2458 case 5: rv = &(s->writeMode); break; 2459 default: rv = NULL; break; 2460 } 2461 2462 return rv; 2463 } 2464 2465 static cint_enum_map_t __cint_enum_map__NlmAradReadMode[] = 2466 { 2467 { "NLM_ARAD_READ_MODE_DATA_X", NLM_ARAD_READ_MODE_DATA_X }, 2468 { "NLM_ARAD_READ_MODE_DATA_Y", NLM_ARAD_READ_MODE_DATA_Y }, 2469 { NULL } 2470 }; 2471 2472 static cint_parameter_desc_t __cint_struct_members__arad_kbp_rop_read_t[] = 2473 { 2474 { 2475 "uint8", 2476 "addr", 2477 0, 2478 NLMDEV_REG_ADDR_LEN_IN_BYTES 2479 }, 2480 { 2481 "uint8", 2482 "vBit", 2483 0, 2484 0 2485 }, 2486 { 2487 "NlmAradReadMode", 2488 "dataType", 2489 0, 2490 0 2491 }, 2492 { 2493 "uint8", 2494 "data", 2495 0, 2496 NLM_DATA_WIDTH_BYTES + 1 2497 }, 2498 { NULL } 2499 }; 2500 2501 2502 2503 static void* 2504 __cint_maddr__arad_kbp_rop_read_t(void* p, int mnum, cint_struct_type_t* parent) 2505 { 2506 void* rv; 2507 arad_kbp_rop_read_t* s = (arad_kbp_rop_read_t*) p; 2508 2509 switch(mnum) 2510 { 2511 case 0: rv = &(s->addr); break; 2512 case 1: rv = &(s->vBit); break; 2513 case 2: rv = &(s->dataType); break; 2514 case 3: rv = &(s->data); break; 2515 default: rv = NULL; break; 2516 } 2517 2518 return rv; 2519 } 2520 #endif /* #if defined(BCM_PETRA_SUPPORT) && defined(INCLUDE_KBP) */ 2521 static cint_struct_type_t __cint_soc_structures[] = 2522 { 2523 2524 /* additions for cmicx diagnostic tests */ 2525 2526 { 2527 "soc_sbusdma_desc_ctrl_t", 2528 sizeof(soc_sbusdma_desc_ctrl_t), 2529 __cint_struct_members__soc_sbusdma_desc_ctrl_t, 2530 __cint_maddr__soc_sbusdma_desc_ctrl_t 2531 }, 2532 { 2533 "soc_sbusdma_desc_cfg_t", 2534 sizeof(soc_sbusdma_desc_cfg_t), 2535 __cint_struct_members__soc_sbusdma_desc_cfg_t, 2536 __cint_maddr__soc_sbusdma_desc_cfg_t 2537 }, 2538 { 2539 "dv_t", 2540 sizeof(dv_t), 2541 __cint_struct_members__dv_t, 2542 __cint_maddr__dv_t 2543 }, 2544 2545 /* end additions for cmicx diagnostic tests */ 2546 2547 { 2548 "soc_interrupt_cause_t", 2549 sizeof(soc_interrupt_cause_t), 2550 __cint_struct_members__soc_interrupt_cause_t, 2551 __cint_maddr__soc_interrupt_cause_t 2552 }, 2553 { 2554 "soc_interrupt_db_t", 2555 sizeof(soc_interrupt_db_t), 2556 __cint_struct_members__soc_interrupt_db_t, 2557 __cint_maddr__soc_interrupt_db_t 2558 }, 2559 #ifdef BCM_PETRA_SUPPORT 2560 #if defined(INCLUDE_KBP) && !defined(BCM_88030) 2561 { 2562 "arad_kbp_lut_data_t", 2563 sizeof(arad_kbp_lut_data_t), 2564 __cint_struct_members__arad_kbp_lut_data_t, 2565 __cint_maddr__arad_kbp_lut_data_t 2566 }, 2567 { 2568 "arad_kbp_rop_write_t", 2569 sizeof(arad_kbp_rop_write_t), 2570 __cint_struct_members__arad_kbp_rop_write_t, 2571 __cint_maddr__arad_kbp_rop_write_t 2572 }, 2573 { 2574 "arad_kbp_rop_read_t", 2575 sizeof(arad_kbp_rop_read_t), 2576 __cint_struct_members__arad_kbp_rop_read_t, 2577 __cint_maddr__arad_kbp_rop_read_t 2578 }, 2579 #endif 2580 #ifdef TEST_TCAM 2581 { 2582 "ARAD_PP_IHB_TCAM_BANK_TBL_DATA", 2583 sizeof(ARAD_PP_IHB_TCAM_BANK_TBL_DATA), 2584 __cint_struct_members__ARAD_PP_IHB_TCAM_BANK_TBL_DATA, 2585 __cint_maddr__ARAD_PP_IHB_TCAM_BANK_TBL_DATA 2586 }, 2587 { 2588 "ARAD_PP_IHB_TCAM_COMPARE_DATA", 2589 sizeof(ARAD_PP_IHB_TCAM_COMPARE_DATA), 2590 __cint_struct_members__ARAD_PP_IHB_TCAM_COMPARE_DATA, 2591 __cint_maddr__ARAD_PP_IHB_TCAM_COMPARE_DATA 2592 }, 2593 #endif 2594 { 2595 "combo28_drc_pll_t", 2596 sizeof(combo28_drc_pll_t), 2597 __cint_struct_members__combo28_drc_pll_t, 2598 __cint_maddr__combo28_drc_pll_t 2599 }, 2600 { 2601 "combo28_vendor_info_t", 2602 sizeof(combo28_vendor_info_t), 2603 __cint_struct_members__combo28_vendor_info_t, 2604 __cint_maddr__combo28_vendor_info_t 2605 }, 2606 { 2607 "combo28_bist_info_t", 2608 sizeof(combo28_bist_info_t), 2609 __cint_struct_members__combo28_bist_info_t, 2610 __cint_maddr__combo28_bist_info_t 2611 }, 2612 { 2613 "combo28_gddr5_bist_info_t", 2614 sizeof(combo28_gddr5_bist_info_t), 2615 __cint_struct_members__combo28_gddr5_bist_info_t, 2616 __cint_maddr__combo28_gddr5_bist_info_t 2617 }, 2618 { 2619 "combo28_bist_err_cnt_t", 2620 sizeof(combo28_bist_err_cnt_t), 2621 __cint_struct_members__combo28_bist_err_cnt_t, 2622 __cint_maddr__combo28_bist_err_cnt_t 2623 }, 2624 { 2625 "combo28_gddr5_bist_err_cnt_t", 2626 sizeof(combo28_gddr5_bist_err_cnt_t), 2627 __cint_struct_members__combo28_gddr5_bist_err_cnt_t, 2628 __cint_maddr__combo28_gddr5_bist_err_cnt_t 2629 }, 2630 #endif /* BCM_PETRA_SUPPORT */ 2631 { NULL } 2632 }; 2633 2634 static cint_enum_type_t __cint_soc_enums[] = 2635 { 2636 #if defined(BCM_PETRA_SUPPORT) && defined(INCLUDE_KBP) && !defined(BCM_88030) 2637 { "NlmAradWriteMode", __cint_enum_map__NlmAradWriteMode }, 2638 { "NlmAradReadMode", __cint_enum_map__NlmAradReadMode }, 2639 #endif 2640 CINT_ENTRY_LAST 2641 }; 2642 2643 static cint_parameter_desc_t __cint_soc_typedefs[] = 2644 { 2645 2646 /* additions for cmicx diagnostic tests */ 2647 2648 { "int", "soc_mem_t", 0, 0 }, 2649 { "int", "soc_block_t", 0, 0 }, 2650 { "int", "sbusdma_desc_handle_t", 0, 0 }, 2651 2652 /* end additions for cmicx diagnostic tests */ 2653 2654 { 2655 "int", 2656 "soc_port_t", 2657 0, 2658 0 2659 }, 2660 {NULL} 2661 }; 2662 2663 static cint_constants_t __cint_soc_constants[] = 2664 { 2665 CINT_ENTRY_LAST 2666 }; 2667 2668 cint_data_t soc_cint_data = 2669 { 2670 NULL, 2671 __cint_soc_functions, 2672 __cint_soc_structures, 2673 __cint_soc_enums, 2674 __cint_soc_typedefs, 2675 __cint_soc_constants, 2676 __cint_soc_function_pointers 2677 }; 2678 2679 #endif /* INCLUDE_LIB_CINT */ 2680 2681 2682