portmod_cint_data.c (355274B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 * 9 * 10 * DO NOT EDIT THIS FILE! 11 */ 12 13 #if defined(INCLUDE_LIB_CINT) 14 15 #include <cint_config.h> 16 #include <cint_types.h> 17 #include <cint_porting.h> 18 19 #if defined(PORTMOD_SUPPORT) 20 21 #include <soc/portmod/portmod.h> 22 23 /* Macros section */ 24 25 /* Functions section */ 26 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 27 portmod_port_speed_ability_local_get, 28 int, int, unit, 0, 0, 29 int, int, port, 0, 0, 30 int, int, max_num_abilities, 0, 0, 31 portmod_port_speed_ability_t*, portmod_port_speed_ability_t, abilities, 1, 0, 32 int*, int, num_abilities, 1, 0); 33 34 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 35 portmod_create, 36 int, int, unit, 0, 0, 37 int, int, flags, 0, 0, 38 int, int, max_ports, 0, 0, 39 int, int, max_phys, 0, 0, 40 int, int, nof_pm_instances, 0, 0, 41 portmod_pm_instances_t*, portmod_pm_instances_t, pm_instances, 1, 0); 42 43 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 44 portmod_destroy, 45 int, int, unit, 0, 0); 46 47 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 48 portmod_port_macro_add, 49 int, int, unit, 0, 0, 50 portmod_pm_create_info_t*, portmod_pm_create_info_t, pm_info, 1, 0); 51 52 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 53 portmod_port_add, 54 int, int, unit, 0, 0, 55 int, int, port, 0, 0, 56 portmod_port_add_info_t*, portmod_port_add_info_t, add_info, 1, 0); 57 58 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 59 portmod_port_remove, 60 int, int, unit, 0, 0, 61 int, int, port, 0, 0); 62 63 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 64 portmod_port_first_phy_get, 65 int, int, unit, 0, 0, 66 int, int, port, 0, 0, 67 int*, int, phy, 1, 0, 68 int*, int, sub_phy, 1, 0); 69 70 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 71 portmod_port_phys_get, 72 int, int, unit, 0, 0, 73 int, int, port, 0, 0, 74 portmod_pbmp_t*, portmod_pbmp_t, phys, 1, 0); 75 76 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 77 portmod_port_is_valid, 78 int, int, unit, 0, 0, 79 int, int, port, 0, 0, 80 int*, int, valid, 1, 0); 81 82 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 83 portmod_port_pm_type_get, 84 int, int, unit, 0, 0, 85 int, int, port, 0, 0, 86 int*, int, real_port, 1, 0, 87 portmod_dispatch_type_t*, portmod_dispatch_type_t, pm_type, 1, 0); 88 89 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 90 portmod_port_enable_get, 91 int, int, unit, 0, 0, 92 int, int, port, 0, 0, 93 int, int, flags, 0, 0, 94 int*, int, enable, 1, 0); 95 96 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 97 portmod_port_enable_set, 98 int, int, unit, 0, 0, 99 int, int, port, 0, 0, 100 int, int, flags, 0, 0, 101 int, int, enable, 0, 0); 102 103 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 104 portmod_port_cdr_lock_get, 105 int, int, unit, 0, 0, 106 int, int, port, 0, 0, 107 int*, int, is_locked, 1, 0); 108 109 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 110 portmod_port_interface_config_get, 111 int, int, unit, 0, 0, 112 int, int, port, 0, 0, 113 portmod_port_interface_config_t*, portmod_port_interface_config_t, config, 1, 0, 114 int, int, phy_init_flags, 0, 0); 115 116 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 117 portmod_port_interface_config_set, 118 int, int, unit, 0, 0, 119 int, int, port, 0, 0, 120 portmod_port_interface_config_t*, portmod_port_interface_config_t, config, 1, 0, 121 int, int, phy_init_flags, 0, 0); 122 123 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 124 portmod_port_default_interface_get, 125 int, int, unit, 0, 0, 126 int, int, port, 0, 0, 127 portmod_port_interface_config_t*, portmod_port_interface_config_t, config, 1, 0, 128 soc_port_if_t*, soc_port_if_t, interface, 1, 0); 129 130 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 131 portmod_port_interface_check, 132 int, int, unit, 0, 0, 133 int, int, port, 0, 0, 134 portmod_port_interface_config_t*, portmod_port_interface_config_t, config, 1, 0, 135 int, int, is_ext_phy, 0, 0, 136 soc_port_if_t, soc_port_if_t, interface, 0, 0, 137 int*, int, is_valid, 1, 0); 138 139 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 140 portmod_port_encoding_get, 141 int, int, unit, 0, 0, 142 int, int, port, 0, 0, 143 uint32*, uint32, properties, 1, 0, 144 portmod_port_pcs_t*, portmod_port_pcs_t, encoding, 1, 0); 145 146 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 147 portmod_port_encoding_set, 148 int, int, unit, 0, 0, 149 int, int, port, 0, 0, 150 uint32, uint32, properties, 0, 0, 151 portmod_port_pcs_t, portmod_port_pcs_t, encoding, 0, 0); 152 153 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 154 portmod_port_cl72_get, 155 int, int, unit, 0, 0, 156 int, int, port, 0, 0, 157 uint32*, uint32, enable, 1, 0); 158 159 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 160 portmod_port_cl72_set, 161 int, int, unit, 0, 0, 162 int, int, port, 0, 0, 163 uint32, uint32, enable, 0, 0); 164 165 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 166 portmod_port_cl72_status_get, 167 int, int, unit, 0, 0, 168 int, int, port, 0, 0, 169 phymod_cl72_status_t*, phymod_cl72_status_t, status, 1, 0); 170 171 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 172 portmod_port_loopback_get, 173 int, int, unit, 0, 0, 174 int, int, port, 0, 0, 175 portmod_loopback_mode_t, portmod_loopback_mode_t, loopback_type, 0, 0, 176 int*, int, enable, 1, 0); 177 178 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 179 portmod_port_loopback_set, 180 int, int, unit, 0, 0, 181 int, int, port, 0, 0, 182 portmod_loopback_mode_t, portmod_loopback_mode_t, loopback_type, 0, 0, 183 int, int, enable, 0, 0); 184 185 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 186 portmod_port_pass_through_get, 187 int, int, unit, 0, 0, 188 int, int, port, 0, 0, 189 int*, int, loopback_en, 1, 0, 190 int*, int, enable, 1, 0); 191 192 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 193 portmod_port_pass_through_set, 194 int, int, unit, 0, 0, 195 int, int, port, 0, 0, 196 int, int, loopback_en, 0, 0, 197 int, int, enable, 0, 0); 198 199 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 200 portmod_port_pass_through_calibrate, 201 int, int, unit, 0, 0, 202 int, int, port, 0, 0); 203 204 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 205 portmod_port_pass_through_fec_enable_get, 206 int, int, unit, 0, 0, 207 int, int, port, 0, 0, 208 int*, int, enable, 1, 0); 209 210 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 211 portmod_port_pass_through_fec_enable_set, 212 int, int, unit, 0, 0, 213 int, int, port, 0, 0, 214 int, int, enable, 0, 0); 215 216 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 217 portmod_port_rx_mac_enable_get, 218 int, int, unit, 0, 0, 219 int, int, port, 0, 0, 220 int*, int, enable, 1, 0); 221 222 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 223 portmod_port_rx_mac_enable_set, 224 int, int, unit, 0, 0, 225 int, int, port, 0, 0, 226 int, int, enable, 0, 0); 227 228 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 229 portmod_port_tx_mac_enable_get, 230 int, int, unit, 0, 0, 231 int, int, port, 0, 0, 232 int*, int, enable, 1, 0); 233 234 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 235 portmod_port_tx_mac_enable_set, 236 int, int, unit, 0, 0, 237 int, int, port, 0, 0, 238 int, int, enable, 0, 0); 239 240 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 241 portmod_port_ability_local_get, 242 int, int, unit, 0, 0, 243 int, int, port, 0, 0, 244 uint32, uint32, phy_flags, 0, 0, 245 portmod_port_ability_t*, portmod_port_ability_t, ability, 1, 0); 246 247 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 248 portmod_port_autoneg_get, 249 int, int, unit, 0, 0, 250 int, int, port, 0, 0, 251 uint32, uint32, phy_flags, 0, 0, 252 phymod_autoneg_control_t*, phymod_autoneg_control_t, an, 1, 0); 253 254 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 255 portmod_port_autoneg_set, 256 int, int, unit, 0, 0, 257 int, int, port, 0, 0, 258 uint32, uint32, phy_flags, 0, 0, 259 phymod_autoneg_control_t*, phymod_autoneg_control_t, an, 1, 0); 260 261 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 262 portmod_port_autoneg_status_get, 263 int, int, unit, 0, 0, 264 int, int, port, 0, 0, 265 phymod_autoneg_status_t*, phymod_autoneg_status_t, an_status, 1, 0); 266 267 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 268 portmod_port_link_get, 269 int, int, unit, 0, 0, 270 int, int, port, 0, 0, 271 int, int, flags, 0, 0, 272 int*, int, link, 1, 0); 273 274 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 275 portmod_port_link_latch_down_get, 276 int, int, unit, 0, 0, 277 int, int, port, 0, 0, 278 uint32, uint32, flags, 0, 0, 279 int*, int, link, 1, 0); 280 281 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 282 portmod_port_phy_link_up_event, 283 int, int, unit, 0, 0, 284 int, int, port, 0, 0); 285 286 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 287 portmod_port_phy_link_down_event, 288 int, int, unit, 0, 0, 289 int, int, port, 0, 0); 290 291 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 292 portmod_port_prbs_config_get, 293 int, int, unit, 0, 0, 294 int, int, port, 0, 0, 295 portmod_prbs_mode_t, portmod_prbs_mode_t, mode, 0, 0, 296 int, int, flags, 0, 0, 297 phymod_prbs_t*, phymod_prbs_t, config, 1, 0); 298 299 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 300 portmod_port_prbs_config_set, 301 int, int, unit, 0, 0, 302 int, int, port, 0, 0, 303 portmod_prbs_mode_t, portmod_prbs_mode_t, mode, 0, 0, 304 int, int, flags, 0, 0, 305 phymod_prbs_t*, phymod_prbs_t, config, 1, 0); 306 307 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 308 portmod_port_prbs_enable_get, 309 int, int, unit, 0, 0, 310 int, int, port, 0, 0, 311 portmod_prbs_mode_t, portmod_prbs_mode_t, mode, 0, 0, 312 int, int, flags, 0, 0, 313 int*, int, enable, 1, 0); 314 315 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 316 portmod_port_prbs_enable_set, 317 int, int, unit, 0, 0, 318 int, int, port, 0, 0, 319 portmod_prbs_mode_t, portmod_prbs_mode_t, mode, 0, 0, 320 int, int, flags, 0, 0, 321 int, int, enable, 0, 0); 322 323 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 324 portmod_port_prbs_status_get, 325 int, int, unit, 0, 0, 326 int, int, port, 0, 0, 327 portmod_prbs_mode_t, portmod_prbs_mode_t, mode, 0, 0, 328 int, int, flags, 0, 0, 329 phymod_prbs_status_t*, phymod_prbs_status_t, status, 1, 0); 330 331 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 332 portmod_port_nof_lanes_get, 333 int, int, unit, 0, 0, 334 int, int, port, 0, 0, 335 int*, int, nof_lanes, 1, 0); 336 337 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 338 portmod_port_ilkn_nof_segments_get, 339 int, int, unit, 0, 0, 340 int, int, port, 0, 0, 341 uint32*, uint32, nof_segments, 1, 0); 342 343 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 344 portmod_port_ilkn_nof_segments_set, 345 int, int, unit, 0, 0, 346 int, int, port, 0, 0, 347 uint32, uint32, nof_segments, 0, 0); 348 349 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 350 portmod_ilkn_retranstmit_config_get, 351 int, int, unit, 0, 0, 352 int, int, port, 0, 0, 353 ilkn_retransmit_config_t*, ilkn_retransmit_config_t, retransmit_config, 1, 0); 354 355 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 356 portmod_ilkn_retranstmit_config_set, 357 int, int, unit, 0, 0, 358 int, int, port, 0, 0, 359 ilkn_retransmit_config_t*, ilkn_retransmit_config_t, retransmit_config, 1, 0); 360 361 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 362 portmod_port_lanes_assign, 363 int, int, unit, 0, 0, 364 int, int, port, 0, 0, 365 portmod_lanes_assign_info_t*, portmod_lanes_assign_info_t, assign_map, 1, 0); 366 367 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 368 portmod_port_lanes_retrieve, 369 int, int, unit, 0, 0, 370 int, int, port, 0, 0, 371 portmod_lanes_assign_info_t*, portmod_lanes_assign_info_t, assign_map, 1, 0); 372 373 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 374 portmod_port_firmware_mode_get, 375 int, int, unit, 0, 0, 376 int, int, port, 0, 0, 377 phymod_firmware_mode_t*, phymod_firmware_mode_t, fw_mode, 1, 0); 378 379 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 380 portmod_port_firmware_mode_set, 381 int, int, unit, 0, 0, 382 int, int, port, 0, 0, 383 phymod_firmware_mode_t, phymod_firmware_mode_t, fw_mode, 0, 0); 384 385 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 386 portmod_port_runt_threshold_get, 387 int, int, unit, 0, 0, 388 int, int, port, 0, 0, 389 int*, int, value, 1, 0); 390 391 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 392 portmod_port_runt_threshold_set, 393 int, int, unit, 0, 0, 394 int, int, port, 0, 0, 395 int, int, value, 0, 0); 396 397 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 398 portmod_port_max_packet_size_get, 399 int, int, unit, 0, 0, 400 int, int, port, 0, 0, 401 int*, int, value, 1, 0); 402 403 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 404 portmod_port_max_packet_size_set, 405 int, int, unit, 0, 0, 406 int, int, port, 0, 0, 407 int, int, value, 0, 0); 408 409 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 410 portmod_port_pad_size_get, 411 int, int, unit, 0, 0, 412 int, int, port, 0, 0, 413 int*, int, value, 1, 0); 414 415 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 416 portmod_port_pad_size_set, 417 int, int, unit, 0, 0, 418 int, int, port, 0, 0, 419 int, int, value, 0, 0); 420 421 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 422 portmod_port_tx_mac_sa_get, 423 int, int, unit, 0, 0, 424 int, int, port, 0, 0, 425 sal_mac_addr_t, sal_mac_addr_t, mac_sa, 0, 0); 426 427 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 428 portmod_port_tx_mac_sa_set, 429 int, int, unit, 0, 0, 430 int, int, port, 0, 0, 431 sal_mac_addr_t, sal_mac_addr_t, mac_sa, 0, 0); 432 433 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 434 portmod_port_rx_mac_sa_get, 435 int, int, unit, 0, 0, 436 int, int, port, 0, 0, 437 sal_mac_addr_t, sal_mac_addr_t, mac_sa, 0, 0); 438 439 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 440 portmod_port_rx_mac_sa_set, 441 int, int, unit, 0, 0, 442 int, int, port, 0, 0, 443 sal_mac_addr_t, sal_mac_addr_t, mac_sa, 0, 0); 444 445 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 446 portmod_port_tx_average_ipg_get, 447 int, int, unit, 0, 0, 448 int, int, port, 0, 0, 449 int*, int, value, 1, 0); 450 451 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 452 portmod_port_tx_average_ipg_set, 453 int, int, unit, 0, 0, 454 int, int, port, 0, 0, 455 int, int, value, 0, 0); 456 457 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 458 portmod_port_tx_preamble_length_get, 459 int, int, unit, 0, 0, 460 int, int, port, 0, 0, 461 int*, int, value, 1, 0); 462 463 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 464 portmod_port_tx_preamble_length_set, 465 int, int, unit, 0, 0, 466 int, int, port, 0, 0, 467 int, int, value, 0, 0); 468 469 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 470 portmod_port_local_fault_control_get, 471 int, int, unit, 0, 0, 472 int, int, port, 0, 0, 473 portmod_local_fault_control_t*, portmod_local_fault_control_t, control, 1, 0); 474 475 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 476 portmod_port_local_fault_control_set, 477 int, int, unit, 0, 0, 478 int, int, port, 0, 0, 479 portmod_local_fault_control_t*, portmod_local_fault_control_t, control, 1, 0); 480 481 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 482 portmod_port_remote_fault_control_get, 483 int, int, unit, 0, 0, 484 int, int, port, 0, 0, 485 portmod_remote_fault_control_t*, portmod_remote_fault_control_t, control, 1, 0); 486 487 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 488 portmod_port_remote_fault_control_set, 489 int, int, unit, 0, 0, 490 int, int, port, 0, 0, 491 portmod_remote_fault_control_t*, portmod_remote_fault_control_t, control, 1, 0); 492 493 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 494 portmod_port_local_fault_status_get, 495 int, int, unit, 0, 0, 496 int, int, port, 0, 0, 497 int*, int, value, 1, 0); 498 499 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 500 portmod_port_remote_fault_status_get, 501 int, int, unit, 0, 0, 502 int, int, port, 0, 0, 503 int*, int, value, 1, 0); 504 505 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 506 portmod_port_local_fault_status_clear, 507 int, int, unit, 0, 0, 508 int, int, port, 0, 0); 509 510 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 511 portmod_port_remote_fault_status_clear, 512 int, int, unit, 0, 0, 513 int, int, port, 0, 0); 514 515 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 516 portmod_port_pause_control_get, 517 int, int, unit, 0, 0, 518 int, int, port, 0, 0, 519 portmod_pause_control_t*, portmod_pause_control_t, control, 1, 0); 520 521 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 522 portmod_port_pause_control_set, 523 int, int, unit, 0, 0, 524 int, int, port, 0, 0, 525 portmod_pause_control_t*, portmod_pause_control_t, control, 1, 0); 526 527 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 528 portmod_port_pfc_control_get, 529 int, int, unit, 0, 0, 530 int, int, port, 0, 0, 531 portmod_pfc_control_t*, portmod_pfc_control_t, control, 1, 0); 532 533 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 534 portmod_port_pfc_control_set, 535 int, int, unit, 0, 0, 536 int, int, port, 0, 0, 537 portmod_pfc_control_t*, portmod_pfc_control_t, control, 1, 0); 538 539 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 540 portmod_port_llfc_control_get, 541 int, int, unit, 0, 0, 542 int, int, port, 0, 0, 543 portmod_llfc_control_t*, portmod_llfc_control_t, control, 1, 0); 544 545 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 546 portmod_port_llfc_control_set, 547 int, int, unit, 0, 0, 548 int, int, port, 0, 0, 549 portmod_llfc_control_t*, portmod_llfc_control_t, control, 1, 0); 550 551 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 552 portmod_port_update, 553 int, int, unit, 0, 0, 554 int, int, port, 0, 0, 555 portmod_port_update_control_t*, portmod_port_update_control_t, update_control, 1, 0); 556 557 CINT_FWRAPPER_CREATE_RP7(int, int, 0, 0, 558 portmod_port_core_access_get, 559 int, int, unit, 0, 0, 560 int, int, port, 0, 0, 561 int, int, phyn, 0, 0, 562 int, int, max_cores, 0, 0, 563 phymod_core_access_t*, phymod_core_access_t, core_access_arr, 1, 0, 564 int*, int, nof_cores, 1, 0, 565 int*, int, is_most_ext, 1, 0); 566 567 CINT_FWRAPPER_CREATE_RP7(int, int, 0, 0, 568 portmod_port_phy_lane_access_get, 569 int, int, unit, 0, 0, 570 int, int, port, 0, 0, 571 portmod_access_get_params_t*, portmod_access_get_params_t, params, 1, 0, 572 int, int, max_phys, 0, 0, 573 phymod_phy_access_t*, phymod_phy_access_t, access, 1, 0, 574 int*, int, nof_phys, 1, 0, 575 int*, int, is_most_ext, 1, 0); 576 577 CINT_FWRAPPER_CREATE_RP7(int, int, 0, 0, 578 portmod_pm_phy_lane_access_get, 579 int, int, unit, 0, 0, 580 int, int, pm_id, 0, 0, 581 portmod_access_get_params_t*, portmod_access_get_params_t, params, 1, 0, 582 int, int, max_phys, 0, 0, 583 phymod_phy_access_t*, phymod_phy_access_t, access, 1, 0, 584 int*, int, nof_phys, 1, 0, 585 int*, int, is_most_ext, 1, 0); 586 587 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 588 portmod_pm_diag_info_get, 589 int, int, unit, 0, 0, 590 int, int, pm_id, 0, 0, 591 portmod_pm_diag_info_t*, portmod_pm_diag_info_t, diag_info, 1, 0); 592 593 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 594 portmod_port_diag_info_get, 595 int, int, unit, 0, 0, 596 int, int, port, 0, 0, 597 portmod_port_diag_info_t*, portmod_port_diag_info_t, diag_info, 1, 0); 598 599 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 600 portmod_port_duplex_get, 601 int, int, unit, 0, 0, 602 int, int, port, 0, 0, 603 int*, int, enable, 1, 0); 604 605 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 606 portmod_port_duplex_set, 607 int, int, unit, 0, 0, 608 int, int, port, 0, 0, 609 int, int, enable, 0, 0); 610 611 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 612 portmod_port_phy_reg_read, 613 int, int, unit, 0, 0, 614 int, int, port, 0, 0, 615 int, int, lane, 0, 0, 616 int, int, flags, 0, 0, 617 int, int, reg_addr, 0, 0, 618 uint32*, uint32, value, 1, 0); 619 620 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 621 portmod_port_phy_reg_write, 622 int, int, unit, 0, 0, 623 int, int, port, 0, 0, 624 int, int, lane, 0, 0, 625 int, int, flags, 0, 0, 626 int, int, reg_addr, 0, 0, 627 uint32, uint32, value, 0, 0); 628 629 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 630 portmod_port_reset_get, 631 int, int, unit, 0, 0, 632 int, int, port, 0, 0, 633 int, int, mode, 0, 0, 634 int, int, opcode, 0, 0, 635 int*, int, value, 1, 0); 636 637 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 638 portmod_port_reset_set, 639 int, int, unit, 0, 0, 640 int, int, port, 0, 0, 641 int, int, mode, 0, 0, 642 int, int, opcode, 0, 0, 643 int, int, value, 0, 0); 644 645 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 646 portmod_port_adv_remote_get, 647 int, int, unit, 0, 0, 648 int, int, port, 0, 0, 649 int*, int, value, 1, 0); 650 651 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 652 portmod_port_drv_name, 653 int, int, unit, 0, 0, 654 int, int, port, 0, 0); 655 656 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 657 portmod_port_drv_name_get, 658 int, int, unit, 0, 0, 659 int, int, port, 0, 0, 660 char*, char, name, 1, 0, 661 int, int, len, 0, 0); 662 663 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 664 portmod_port_fec_enable_get, 665 int, int, unit, 0, 0, 666 int, int, port, 0, 0, 667 uint32, uint32, phy_flags, 0, 0, 668 uint32_t*, uint32_t, enable, 1, 0); 669 670 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 671 portmod_port_fec_enable_set, 672 int, int, unit, 0, 0, 673 int, int, port, 0, 0, 674 uint32, uint32, phy_flags, 0, 0, 675 uint32_t, uint32_t, enable, 0, 0); 676 677 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 678 portmod_port_ability_advert_get, 679 int, int, unit, 0, 0, 680 int, int, port, 0, 0, 681 uint32, uint32, phy_flags, 0, 0, 682 portmod_port_ability_t*, portmod_port_ability_t, ability, 1, 0); 683 684 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 685 portmod_port_ability_advert_set, 686 int, int, unit, 0, 0, 687 int, int, port, 0, 0, 688 uint32, uint32, phy_flags, 0, 0, 689 portmod_port_ability_t*, portmod_port_ability_t, ability, 1, 0); 690 691 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 692 portmod_port_ability_remote_get, 693 int, int, unit, 0, 0, 694 int, int, port, 0, 0, 695 uint32, uint32, phy_flags, 0, 0, 696 portmod_port_ability_t*, portmod_port_ability_t, ability, 1, 0); 697 698 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 699 portmod_port_frame_spacing_stretch_get, 700 int, int, unit, 0, 0, 701 int, int, port, 0, 0, 702 int*, int, spacing, 1, 0); 703 704 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 705 portmod_port_frame_spacing_stretch_set, 706 int, int, unit, 0, 0, 707 int, int, port, 0, 0, 708 int, int, spacing, 0, 0); 709 710 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 711 portmod_port_diag_fifo_status_get, 712 int, int, unit, 0, 0, 713 int, int, port, 0, 0, 714 portmod_fifo_status_t*, portmod_fifo_status_t, diag_info, 1, 0); 715 716 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 717 portmod_port_rx_control_get, 718 int, int, unit, 0, 0, 719 int, int, port, 0, 0, 720 portmod_rx_control_t*, portmod_rx_control_t, rx_ctrl, 1, 0); 721 722 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 723 portmod_port_rx_control_set, 724 int, int, unit, 0, 0, 725 int, int, port, 0, 0, 726 portmod_rx_control_t*, portmod_rx_control_t, rx_ctrl, 1, 0); 727 728 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 729 portmod_port_pfc_config_get, 730 int, int, unit, 0, 0, 731 int, int, port, 0, 0, 732 portmod_pfc_config_t*, portmod_pfc_config_t, pfc_cfg, 1, 0); 733 734 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 735 portmod_port_pfc_config_set, 736 int, int, unit, 0, 0, 737 int, int, port, 0, 0, 738 portmod_pfc_config_t*, portmod_pfc_config_t, pfc_cfg, 1, 0); 739 740 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 741 portmod_port_eee_get, 742 int, int, unit, 0, 0, 743 int, int, port, 0, 0, 744 portmod_eee_t*, portmod_eee_t, eee, 1, 0); 745 746 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 747 portmod_port_eee_set, 748 int, int, unit, 0, 0, 749 int, int, port, 0, 0, 750 portmod_eee_t*, portmod_eee_t, eee, 1, 0); 751 752 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 753 portmod_port_eee_clock_get, 754 int, int, unit, 0, 0, 755 int, int, port, 0, 0, 756 portmod_eee_clock_t*, portmod_eee_clock_t, eee_clk, 1, 0); 757 758 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 759 portmod_port_eee_clock_set, 760 int, int, unit, 0, 0, 761 int, int, port, 0, 0, 762 portmod_eee_clock_t*, portmod_eee_clock_t, eee_clk, 1, 0); 763 764 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 765 portmod_port_vlan_tag_get, 766 int, int, unit, 0, 0, 767 int, int, port, 0, 0, 768 portmod_vlan_tag_t*, portmod_vlan_tag_t, vlan_tag, 1, 0); 769 770 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 771 portmod_port_vlan_tag_set, 772 int, int, unit, 0, 0, 773 int, int, port, 0, 0, 774 portmod_vlan_tag_t*, portmod_vlan_tag_t, vlan_tag, 1, 0); 775 776 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 777 portmod_port_to_phyaddr, 778 int, int, unit, 0, 0, 779 int, int, port, 0, 0); 780 781 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 782 portmod_port_to_phyaddr_int, 783 int, int, unit, 0, 0, 784 int, int, port, 0, 0); 785 786 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 787 portmod_port_modid_set, 788 int, int, unit, 0, 0, 789 int, int, port, 0, 0, 790 int, int, value, 0, 0); 791 792 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 793 portmod_port_led_chain_config, 794 int, int, unit, 0, 0, 795 int, int, port, 0, 0, 796 int, int, value, 0, 0); 797 798 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 799 portmod_port_clear_rx_lss_status_get, 800 int, int, unit, 0, 0, 801 int, int, port, 0, 0, 802 int*, int, lcl_fault, 1, 0, 803 int*, int, rmt_fault, 1, 0); 804 805 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 806 portmod_port_clear_rx_lss_status_set, 807 int, int, unit, 0, 0, 808 int, int, port, 0, 0, 809 int, int, lcl_fault, 0, 0, 810 int, int, rmt_fault, 0, 0); 811 812 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 813 portmod_xphy_lane_attach, 814 int, int, unit, 0, 0, 815 int, int, iphy, 0, 0, 816 int, int, phyn, 0, 0, 817 portmod_xphy_lane_connection_t*, portmod_xphy_lane_connection_t, lane_conn, 1, 0); 818 819 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 820 portmod_xphy_lane_detach, 821 int, int, unit, 0, 0, 822 int, int, iphy, 0, 0, 823 int, int, phyn, 0, 0); 824 825 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 826 portmod_xphy_add, 827 int, int, unit, 0, 0, 828 int, int, xphy_addr, 0, 0, 829 phymod_core_access_t*, phymod_core_access_t, core_access, 1, 0, 830 int*, int, xphy_idx, 1, 0); 831 832 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 833 portmod_xphy_delete, 834 int, int, unit, 0, 0, 835 int, int, xphy_addr, 0, 0); 836 837 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 838 portmod_xphy_wb_db_restore, 839 int, int, unit, 0, 0, 840 int, int, xphy_idx, 0, 0, 841 int, int, xphy_addr, 0, 0, 842 phymod_core_access_t*, phymod_core_access_t, core_access, 1, 0); 843 844 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 845 portmod_ext_phy_lane_attach, 846 int, int, unit, 0, 0, 847 int, int, iphy, 0, 0, 848 int, int, phyn, 0, 0, 849 portmod_lane_connection_t*, portmod_lane_connection_t, lane_connection, 1, 0); 850 851 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 852 portmod_ext_phy_lane_detach, 853 int, int, unit, 0, 0, 854 int, int, iphy, 0, 0, 855 int, int, phyn, 0, 0); 856 857 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 858 portmod_port_lag_failover_status_toggle, 859 int, int, unit, 0, 0, 860 int, int, port, 0, 0); 861 862 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 863 portmod_port_lag_failover_loopback_get, 864 int, int, unit, 0, 0, 865 int, int, port, 0, 0, 866 int*, int, value, 1, 0); 867 868 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 869 portmod_port_lag_failover_loopback_set, 870 int, int, unit, 0, 0, 871 int, int, port, 0, 0, 872 int, int, value, 0, 0); 873 874 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 875 portmod_port_mode_get, 876 int, int, unit, 0, 0, 877 int, int, port, 0, 0, 878 portmod_port_mode_info_t*, portmod_port_mode_info_t, mode, 1, 0); 879 880 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 881 portmod_port_mode_set, 882 int, int, unit, 0, 0, 883 int, int, port, 0, 0, 884 portmod_port_mode_info_t*, portmod_port_mode_info_t, mode, 1, 0); 885 886 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 887 portmod_port_encap_get, 888 int, int, unit, 0, 0, 889 int, int, port, 0, 0, 890 int*, int, flags, 1, 0, 891 portmod_encap_t*, portmod_encap_t, encap, 1, 0); 892 893 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 894 portmod_port_encap_set, 895 int, int, unit, 0, 0, 896 int, int, port, 0, 0, 897 int, int, flags, 0, 0, 898 portmod_encap_t, portmod_encap_t, encap, 0, 0); 899 900 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 901 portmod_port_higig_mode_get, 902 int, int, unit, 0, 0, 903 int, int, port, 0, 0, 904 int*, int, mode, 1, 0); 905 906 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 907 portmod_port_higig_mode_set, 908 int, int, unit, 0, 0, 909 int, int, port, 0, 0, 910 int, int, mode, 0, 0); 911 912 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 913 portmod_port_higig2_mode_get, 914 int, int, unit, 0, 0, 915 int, int, port, 0, 0, 916 int*, int, mode, 1, 0); 917 918 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 919 portmod_port_higig2_mode_set, 920 int, int, unit, 0, 0, 921 int, int, port, 0, 0, 922 int, int, mode, 0, 0); 923 924 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 925 portmod_port_config_port_type_get, 926 int, int, unit, 0, 0, 927 int, int, port, 0, 0, 928 int*, int, type, 1, 0); 929 930 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 931 portmod_port_config_port_type_set, 932 int, int, unit, 0, 0, 933 int, int, port, 0, 0, 934 int, int, type, 0, 0); 935 936 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 937 portmod_port_trunk_hwfailover_config_get, 938 int, int, unit, 0, 0, 939 int, int, port, 0, 0, 940 int*, int, enable, 1, 0); 941 942 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 943 portmod_port_trunk_hwfailover_config_set, 944 int, int, unit, 0, 0, 945 int, int, port, 0, 0, 946 int, int, hw_count, 0, 0); 947 948 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 949 portmod_port_trunk_hwfailover_status_get, 950 int, int, unit, 0, 0, 951 int, int, port, 0, 0, 952 int*, int, loopback, 1, 0); 953 954 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 955 portmod_port_diag_ctrl, 956 int, int, unit, 0, 0, 957 int, int, port, 0, 0, 958 uint32, uint32, inst, 0, 0, 959 int, int, op_type, 0, 0, 960 int, int, op_cmd, 0, 0, 961 void*, void, arg, 1, 0); 962 963 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 964 portmod_port_ref_clk_get, 965 int, int, unit, 0, 0, 966 int, int, port, 0, 0, 967 int*, int, ref_clk, 1, 0); 968 969 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 970 portmod_port_lag_failover_disable, 971 int, int, unit, 0, 0, 972 int, int, port, 0, 0); 973 974 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 975 portmod_port_lag_remove_failover_lpbk_get, 976 int, int, unit, 0, 0, 977 int, int, port, 0, 0, 978 int*, int, val, 1, 0); 979 980 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 981 portmod_port_lag_remove_failover_lpbk_set, 982 int, int, unit, 0, 0, 983 int, int, port, 0, 0, 984 int, int, val, 0, 0); 985 986 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 987 portmod_port_cntmaxsize_get, 988 int, int, unit, 0, 0, 989 int, int, port, 0, 0, 990 int*, int, val, 1, 0); 991 992 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 993 portmod_port_cntmaxsize_set, 994 int, int, unit, 0, 0, 995 int, int, port, 0, 0, 996 int, int, val, 0, 0); 997 998 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 999 portmod_port_multi_get, 1000 int, int, unit, 0, 0, 1001 int, int, port, 0, 0, 1002 portmod_multi_get_t*, portmod_multi_get_t, multi_get, 1, 0); 1003 1004 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1005 portmod_port_drain_cell_get, 1006 int, int, unit, 0, 0, 1007 int, int, port, 0, 0, 1008 portmod_drain_cells_t*, portmod_drain_cells_t, drain_cells, 1, 0); 1009 1010 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1011 portmod_port_drain_cell_stop, 1012 int, int, unit, 0, 0, 1013 int, int, port, 0, 0, 1014 portmod_drain_cells_t*, portmod_drain_cells_t, drain_cells, 1, 0); 1015 1016 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1017 portmod_port_drain_cell_start, 1018 int, int, unit, 0, 0, 1019 int, int, port, 0, 0); 1020 1021 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1022 portmod_port_drain_cells_rx_enable, 1023 int, int, unit, 0, 0, 1024 int, int, port, 0, 0, 1025 int, int, rx_en, 0, 0); 1026 1027 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1028 portmod_port_egress_queue_drain_rx_en, 1029 int, int, unit, 0, 0, 1030 int, int, port, 0, 0, 1031 int, int, rx_en, 0, 0); 1032 1033 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1034 portmod_port_mac_ctrl_set, 1035 int, int, unit, 0, 0, 1036 int, int, port, 0, 0, 1037 uint64, uint64, ctrl, 0, 0); 1038 1039 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1040 portmod_port_txfifo_cell_cnt_get, 1041 int, int, unit, 0, 0, 1042 int, int, port, 0, 0, 1043 uint32*, uint32, cnt, 1, 0); 1044 1045 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1046 portmod_port_egress_queue_drain_get, 1047 int, int, unit, 0, 0, 1048 int, int, port, 0, 0, 1049 uint64*, uint64, ctrl, 1, 0, 1050 int*, int, rxen, 1, 0); 1051 1052 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1053 portmod_port_mac_reset_get, 1054 int, int, unit, 0, 0, 1055 int, int, port, 0, 0, 1056 int*, int, val, 1, 0); 1057 1058 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1059 portmod_port_mac_reset_set, 1060 int, int, unit, 0, 0, 1061 int, int, port, 0, 0, 1062 int, int, val, 0, 0); 1063 1064 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1065 portmod_port_soft_reset_toggle, 1066 int, int, unit, 0, 0, 1067 int, int, port, 0, 0, 1068 int, int, idx, 0, 0); 1069 1070 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1071 portmod_port_mac_reset_check, 1072 int, int, unit, 0, 0, 1073 int, int, port, 0, 0, 1074 int, int, enable, 0, 0, 1075 int*, int, reset, 1, 0); 1076 1077 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1078 portmod_port_core_num_get, 1079 int, int, unit, 0, 0, 1080 int, int, port, 0, 0, 1081 int*, int, core_num, 1, 0); 1082 1083 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1084 portmod_port_e2ecc_hdr_get, 1085 int, int, unit, 0, 0, 1086 int, int, port, 0, 0, 1087 portmod_port_higig_e2ecc_hdr_t*, portmod_port_higig_e2ecc_hdr_t, e2ecc_hdr, 1, 0); 1088 1089 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1090 portmod_port_e2ecc_hdr_set, 1091 int, int, unit, 0, 0, 1092 int, int, port, 0, 0, 1093 portmod_port_higig_e2ecc_hdr_t*, portmod_port_higig_e2ecc_hdr_t, e2ecc_hdr, 1, 0); 1094 1095 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1096 portmod_port_e2e_enable_get, 1097 int, int, unit, 0, 0, 1098 int, int, port, 0, 0, 1099 int*, int, enable, 1, 0); 1100 1101 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1102 portmod_port_e2e_enable_set, 1103 int, int, unit, 0, 0, 1104 int, int, port, 0, 0, 1105 int, int, enable, 0, 0); 1106 1107 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1108 portmod_port_fallback_lane_get, 1109 int, int, unit, 0, 0, 1110 int, int, port, 0, 0, 1111 int*, int, fallback_lane, 1, 0); 1112 1113 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1114 portmod_port_speed_get, 1115 int, int, unit, 0, 0, 1116 int, int, port, 0, 0, 1117 int*, int, speed, 1, 0); 1118 1119 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1120 portmod_port_tsc_refclock_get, 1121 int, int, unit, 0, 0, 1122 int, int, port, 0, 0, 1123 int*, int, ref_in, 1, 0, 1124 int*, int, ref_out, 1, 0); 1125 1126 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1127 portmod_port_tsc_refclock_set, 1128 int, int, unit, 0, 0, 1129 int, int, port, 0, 0, 1130 int, int, ref_in, 0, 0, 1131 int, int, ref_out, 0, 0); 1132 1133 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1134 portmod_port_discard_set, 1135 int, int, unit, 0, 0, 1136 int, int, port, 0, 0, 1137 int, int, discard, 0, 0); 1138 1139 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1140 portmod_port_soft_reset_set, 1141 int, int, unit, 0, 0, 1142 int, int, port, 0, 0, 1143 int, int, idx, 0, 0, 1144 int, int, val, 0, 0, 1145 int, int, flags, 0, 0); 1146 1147 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1148 portmod_port_tx_down, 1149 int, int, unit, 0, 0, 1150 int, int, port, 0, 0); 1151 1152 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1153 portmod_port_logical_lane_order_get, 1154 int, int, unit, 0, 0, 1155 int, int, port, 0, 0, 1156 int, int, lane_order_max_size, 0, 0, 1157 int*, int, lane_order, 1, 0, 1158 int*, int, lane_order_actual_size, 1, 0); 1159 1160 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1161 portmod_port_logical_lane_order_set, 1162 int, int, unit, 0, 0, 1163 int, int, port, 0, 0, 1164 int*, int, lane_order, 1, 0, 1165 int, int, lane_order_size, 0, 0); 1166 1167 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1168 portmod_port_pgw_reconfig, 1169 int, int, unit, 0, 0, 1170 int, int, port, 0, 0, 1171 portmod_port_mode_info_t*, portmod_port_mode_info_t, pmode, 1, 0, 1172 int, int, phy_port, 0, 0, 1173 int, int, flags, 0, 0); 1174 1175 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1176 portmod_port_notify, 1177 int, int, unit, 0, 0, 1178 int, int, port, 0, 0, 1179 int, int, link, 0, 0); 1180 1181 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1182 portmod_port_control_phy_timesync_get, 1183 int, int, unit, 0, 0, 1184 int, int, port, 0, 0, 1185 portmod_port_control_phy_timesync_t, portmod_port_control_phy_timesync_t, config, 0, 0, 1186 uint64*, uint64, value, 1, 0); 1187 1188 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1189 portmod_port_control_phy_timesync_set, 1190 int, int, unit, 0, 0, 1191 int, int, port, 0, 0, 1192 portmod_port_control_phy_timesync_t, portmod_port_control_phy_timesync_t, config, 0, 0, 1193 uint64, uint64, value, 0, 0); 1194 1195 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1196 portmod_port_timesync_config_get, 1197 int, int, unit, 0, 0, 1198 int, int, port, 0, 0, 1199 portmod_phy_timesync_config_t*, portmod_phy_timesync_config_t, config, 1, 0); 1200 1201 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1202 portmod_port_timesync_config_set, 1203 int, int, unit, 0, 0, 1204 int, int, port, 0, 0, 1205 portmod_phy_timesync_config_t*, portmod_phy_timesync_config_t, config, 1, 0); 1206 1207 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1208 portmod_port_timesync_enable_get, 1209 int, int, unit, 0, 0, 1210 int, int, port, 0, 0, 1211 uint32*, uint32, enable, 1, 0); 1212 1213 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1214 portmod_port_timesync_enable_set, 1215 int, int, unit, 0, 0, 1216 int, int, port, 0, 0, 1217 uint32, uint32, enable, 0, 0); 1218 1219 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1220 portmod_port_timesync_nco_addend_get, 1221 int, int, unit, 0, 0, 1222 int, int, port, 0, 0, 1223 uint32*, uint32, freq_step, 1, 0); 1224 1225 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1226 portmod_port_timesync_nco_addend_set, 1227 int, int, unit, 0, 0, 1228 int, int, port, 0, 0, 1229 uint32, uint32, freq_step, 0, 0); 1230 1231 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1232 portmod_port_timesync_framesync_mode_get, 1233 int, int, unit, 0, 0, 1234 int, int, port, 0, 0, 1235 portmod_timesync_framesync_t*, portmod_timesync_framesync_t, framesync, 1, 0); 1236 1237 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1238 portmod_port_timesync_framesync_mode_set, 1239 int, int, unit, 0, 0, 1240 int, int, port, 0, 0, 1241 portmod_timesync_framesync_t*, portmod_timesync_framesync_t, framesync, 1, 0); 1242 1243 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1244 portmod_port_timesync_local_time_get, 1245 int, int, unit, 0, 0, 1246 int, int, port, 0, 0, 1247 uint64*, uint64, local_time, 1, 0); 1248 1249 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1250 portmod_port_timesync_local_time_set, 1251 int, int, unit, 0, 0, 1252 int, int, port, 0, 0, 1253 uint64, uint64, local_time, 0, 0); 1254 1255 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1256 portmod_port_timesync_load_ctrl_get, 1257 int, int, unit, 0, 0, 1258 int, int, port, 0, 0, 1259 uint32*, uint32, load_once, 1, 0, 1260 uint32*, uint32, load_always, 1, 0); 1261 1262 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1263 portmod_port_timesync_load_ctrl_set, 1264 int, int, unit, 0, 0, 1265 int, int, port, 0, 0, 1266 uint32, uint32, load_once, 0, 0, 1267 uint32, uint32, load_always, 0, 0); 1268 1269 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1270 portmod_port_timesync_tx_timestamp_offset_get, 1271 int, int, unit, 0, 0, 1272 int, int, port, 0, 0, 1273 uint32*, uint32, ts_offset, 1, 0); 1274 1275 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1276 portmod_port_timesync_tx_timestamp_offset_set, 1277 int, int, unit, 0, 0, 1278 int, int, port, 0, 0, 1279 uint32, uint32, ts_offset, 0, 0); 1280 1281 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1282 portmod_port_timesync_rx_timestamp_offset_get, 1283 int, int, unit, 0, 0, 1284 int, int, port, 0, 0, 1285 uint32*, uint32, ts_offset, 1, 0); 1286 1287 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1288 portmod_port_timesync_rx_timestamp_offset_set, 1289 int, int, unit, 0, 0, 1290 int, int, port, 0, 0, 1291 uint32, uint32, ts_offset, 0, 0); 1292 1293 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1294 portmod_port_timestamp_adjust_get, 1295 int, int, unit, 0, 0, 1296 int, int, port, 0, 0, 1297 soc_port_timestamp_adjust_t*, soc_port_timestamp_adjust_t, ts_adjust, 1, 0); 1298 1299 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1300 portmod_port_timestamp_adjust_set, 1301 int, int, unit, 0, 0, 1302 int, int, port, 0, 0, 1303 soc_port_timestamp_adjust_t*, soc_port_timestamp_adjust_t, ts_adjust, 1, 0); 1304 1305 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1306 portmod_port_phy_intr_enable_get, 1307 int, int, unit, 0, 0, 1308 int, int, port, 0, 0, 1309 uint32*, uint32, intr_enable, 1, 0); 1310 1311 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1312 portmod_port_phy_intr_enable_set, 1313 int, int, unit, 0, 0, 1314 int, int, port, 0, 0, 1315 uint32, uint32, intr_enable, 0, 0); 1316 1317 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1318 portmod_port_phy_intr_status_get, 1319 int, int, unit, 0, 0, 1320 int, int, port, 0, 0, 1321 uint32*, uint32, intr_status, 1, 0); 1322 1323 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1324 portmod_port_phy_intr_status_clear, 1325 int, int, unit, 0, 0, 1326 int, int, port, 0, 0); 1327 1328 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1329 portmod_port_phy_timesync_do_sync, 1330 int, int, unit, 0, 0, 1331 int, int, port, 0, 0); 1332 1333 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1334 portmod_port_timesync_capture_timestamp_get, 1335 int, int, unit, 0, 0, 1336 int, int, port, 0, 0, 1337 uint64*, uint64, cap_ts, 1, 0); 1338 1339 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1340 portmod_port_timesync_heartbeat_timestamp_get, 1341 int, int, unit, 0, 0, 1342 int, int, port, 0, 0, 1343 uint64*, uint64, hb_ts, 1, 0); 1344 1345 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1346 portmod_port_edc_config_get, 1347 int, int, unit, 0, 0, 1348 int, int, port, 0, 0, 1349 portmod_edc_config_t*, portmod_edc_config_t, config, 1, 0); 1350 1351 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1352 portmod_port_edc_config_set, 1353 int, int, unit, 0, 0, 1354 int, int, port, 0, 0, 1355 portmod_edc_config_t*, portmod_edc_config_t, config, 1, 0); 1356 1357 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1358 portmod_port_interrupt_enable_get, 1359 int, int, unit, 0, 0, 1360 int, int, port, 0, 0, 1361 int, int, intr_type, 0, 0, 1362 uint32*, uint32, val, 1, 0); 1363 1364 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1365 portmod_port_interrupt_enable_set, 1366 int, int, unit, 0, 0, 1367 int, int, port, 0, 0, 1368 int, int, intr_type, 0, 0, 1369 uint32, uint32, val, 0, 0); 1370 1371 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1372 portmod_port_interrupt_get, 1373 int, int, unit, 0, 0, 1374 int, int, port, 0, 0, 1375 int, int, intr_type, 0, 0, 1376 uint32*, uint32, val, 1, 0); 1377 1378 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1379 portmod_port_interrupts_get, 1380 int, int, unit, 0, 0, 1381 int, int, port, 0, 0, 1382 int, int, arr_max_size, 0, 0, 1383 uint32*, uint32, intr_arr, 1, 0, 1384 uint32*, uint32, size, 1, 0); 1385 1386 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1387 portmod_port_stats_read, 1388 int, int, unit, 0, 0, 1389 int, int, port, 0, 0, 1390 portmod_stat_val_t, portmod_stat_val_t, cntr_type, 0, 0, 1391 uint64*, uint64, value, 1, 0); 1392 1393 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1394 portmod_port_stats_clear, 1395 int, int, unit, 0, 0, 1396 int, int, port, 0, 0, 1397 portmod_stat_val_t, portmod_stat_val_t, cntr_type, 0, 0); 1398 1399 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1400 portmod_port_check_legacy_phy, 1401 int, int, unit, 0, 0, 1402 int, int, port, 0, 0, 1403 int*, int, legacy_phy, 1, 0); 1404 1405 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1406 portmod_port_failover_mode_get, 1407 int, int, unit, 0, 0, 1408 int, int, port, 0, 0, 1409 phymod_failover_mode_t*, phymod_failover_mode_t, failover, 1, 0); 1410 1411 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1412 portmod_port_failover_mode_set, 1413 int, int, unit, 0, 0, 1414 int, int, port, 0, 0, 1415 phymod_failover_mode_t, phymod_failover_mode_t, failover, 0, 0); 1416 1417 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1418 portmod_port_warmboot_db_restore, 1419 int, int, unit, 0, 0, 1420 int, int, port, 0, 0, 1421 portmod_port_interface_config_t*, portmod_port_interface_config_t, intf_config, 1, 0, 1422 portmod_port_init_config_t*, portmod_port_init_config_t, init_config, 1, 0, 1423 phymod_operation_mode_t, phymod_operation_mode_t, phy_op_mode, 0, 0); 1424 1425 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1426 portmod_port_flow_control_set, 1427 int, int, unit, 0, 0, 1428 int, int, port, 0, 0, 1429 int, int, merge_mode_en, 0, 0, 1430 int, int, parallel_fc_en, 0, 0); 1431 1432 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1433 portmod_port_update_dynamic_state, 1434 int, int, unit, 0, 0, 1435 int, int, port, 0, 0, 1436 uint32_t, uint32_t, port_dynamic_state, 0, 0); 1437 1438 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1439 portmod_port_phy_op_mode_get, 1440 int, int, unit, 0, 0, 1441 int, int, port, 0, 0, 1442 phymod_operation_mode_t*, phymod_operation_mode_t, val, 1, 0); 1443 1444 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1445 portmod_port_lane_map_get, 1446 int, int, unit, 0, 0, 1447 int, int, port, 0, 0, 1448 uint32, uint32, flags, 0, 0, 1449 phymod_lane_map_t*, phymod_lane_map_t, lane_map, 1, 0); 1450 1451 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1452 portmod_port_lane_map_set, 1453 int, int, unit, 0, 0, 1454 int, int, port, 0, 0, 1455 uint32, uint32, flags, 0, 0, 1456 phymod_lane_map_t*, phymod_lane_map_t, lane_map, 1, 0); 1457 1458 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1459 portmod_port_polarity_get, 1460 int, int, unit, 0, 0, 1461 int, int, port, 0, 0, 1462 phymod_polarity_t*, phymod_polarity_t, polarity, 1, 0); 1463 1464 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1465 portmod_port_polarity_set, 1466 int, int, unit, 0, 0, 1467 int, int, port, 0, 0, 1468 phymod_polarity_t*, phymod_polarity_t, polarity, 1, 0); 1469 1470 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1471 portmod_port_medium_config_get, 1472 int, int, unit, 0, 0, 1473 int, int, port, 0, 0, 1474 soc_port_medium_t, soc_port_medium_t, medium, 0, 0, 1475 soc_phy_config_t*, soc_phy_config_t, config, 1, 0); 1476 1477 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1478 portmod_port_medium_config_set, 1479 int, int, unit, 0, 0, 1480 int, int, port, 0, 0, 1481 soc_port_medium_t, soc_port_medium_t, medium, 0, 0, 1482 soc_phy_config_t*, soc_phy_config_t, config, 1, 0); 1483 1484 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1485 portmod_port_medium_get, 1486 int, int, unit, 0, 0, 1487 int, int, port, 0, 0, 1488 soc_port_medium_t*, soc_port_medium_t, medium, 1, 0); 1489 1490 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1491 portmod_pm_port_pll_div_get, 1492 int, int, unit, 0, 0, 1493 int, int, port, 0, 0, 1494 int, int, phy_port, 0, 0, 1495 portmod_port_resources_t*, portmod_port_resources_t, port_resource, 1, 0, 1496 uint32_t*, uint32_t, pll_div, 1, 0); 1497 1498 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1499 portmod_port_master_get, 1500 int, int, unit, 0, 0, 1501 int, int, port, 0, 0, 1502 int*, int, master_mode, 1, 0); 1503 1504 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1505 portmod_port_master_set, 1506 int, int, unit, 0, 0, 1507 int, int, port, 0, 0, 1508 int, int, master_mode, 0, 0); 1509 1510 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1511 portmod_preemption_control_get, 1512 int, int, unit, 0, 0, 1513 int, int, port, 0, 0, 1514 portmod_preemption_control_t, portmod_preemption_control_t, type, 0, 0, 1515 uint32*, uint32, value, 1, 0); 1516 1517 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1518 portmod_preemption_control_set, 1519 int, int, unit, 0, 0, 1520 int, int, port, 0, 0, 1521 portmod_preemption_control_t, portmod_preemption_control_t, type, 0, 0, 1522 uint32, uint32, value, 0, 0); 1523 1524 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1525 portmod_preemption_tx_status_get, 1526 int, int, unit, 0, 0, 1527 int, int, port, 0, 0, 1528 uint32*, uint32, value, 1, 0); 1529 1530 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1531 portmod_preemption_verify_status_get, 1532 int, int, unit, 0, 0, 1533 int, int, port, 0, 0, 1534 portmod_preemption_verify_status_type_t, portmod_preemption_verify_status_type_t, type, 0, 0, 1535 uint32*, uint32, value, 1, 0); 1536 1537 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1538 portmod_preemption_force_rx_eop_mode_get, 1539 int, int, unit, 0, 0, 1540 int, int, port, 0, 0, 1541 portmod_preemption_force_rx_eop_mode_t, portmod_preemption_force_rx_eop_mode_t, type, 0, 0, 1542 uint32*, uint32, value, 1, 0); 1543 1544 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1545 portmod_preemption_force_rx_eop_mode_set, 1546 int, int, unit, 0, 0, 1547 int, int, port, 0, 0, 1548 portmod_preemption_force_rx_eop_mode_t, portmod_preemption_force_rx_eop_mode_t, type, 0, 0, 1549 uint32, uint32, value, 0, 0); 1550 1551 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1552 portmod_preemption_rx_timeout_get, 1553 int, int, unit, 0, 0, 1554 int, int, port, 0, 0, 1555 uint32*, uint32, enable, 1, 0, 1556 uint32*, uint32, timeout_cnt, 1, 0); 1557 1558 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1559 portmod_preemption_rx_timeout_set, 1560 int, int, unit, 0, 0, 1561 int, int, port, 0, 0, 1562 uint32, uint32, enable, 0, 0, 1563 uint32, uint32, timeout_cnt, 0, 0); 1564 1565 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1566 portmod_port_timesync_tx_info_get, 1567 int, int, unit, 0, 0, 1568 int, int, port, 0, 0, 1569 portmod_fifo_status_t*, portmod_fifo_status_t, tx_info, 1, 0); 1570 1571 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1572 portmod_core_add, 1573 int, int, unit, 0, 0, 1574 int, int, pm_id, 0, 0, 1575 portmod_port_add_info_t*, portmod_port_add_info_t, add_info, 1, 0); 1576 1577 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1578 portmod_pm_serdes_core_init, 1579 int, int, unit, 0, 0, 1580 int, int, pm_id, 0, 0, 1581 portmod_port_add_info_t*, portmod_port_add_info_t, add_info, 1, 0); 1582 1583 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1584 portmod_pm_is_initialized, 1585 int, int, unit, 0, 0, 1586 int, int, pm_id, 0, 0, 1587 int*, int, is_initialized, 1, 0); 1588 1589 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1590 portmod_port_speed_config_validate, 1591 int, int, unit, 0, 0, 1592 int, int, port, 0, 0, 1593 portmod_speed_config_t*, portmod_speed_config_t, speed_config, 1, 0, 1594 portmod_pbmp_t*, portmod_pbmp_t, affected_pbmp, 1, 0); 1595 1596 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1597 portmod_pm_enable, 1598 int, int, unit, 0, 0, 1599 int, int, pm_id, 0, 0, 1600 int, int, enable, 0, 0); 1601 1602 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1603 portmod_phy_pm_id_get, 1604 int, int, unit, 0, 0, 1605 int, int, pport, 0, 0, 1606 int*, int, pm_id, 1, 0); 1607 1608 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1609 portmod_pm_logical_pbmp_get, 1610 int, int, unit, 0, 0, 1611 int, int, pm_id, 0, 0, 1612 portmod_pbmp_t*, portmod_pbmp_t, logical_pbmp, 1, 0); 1613 1614 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1615 portmod_pm_vco_reconfig, 1616 int, int, unit, 0, 0, 1617 int, int, pm_id, 0, 0, 1618 portmod_vco_type_t*, portmod_vco_type_t, vco, 1, 0); 1619 1620 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1621 portmod_port_speed_config_get, 1622 int, int, unit, 0, 0, 1623 int, int, port, 0, 0, 1624 portmod_speed_config_t*, portmod_speed_config_t, speed_config, 1, 0); 1625 1626 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1627 portmod_port_speed_config_set, 1628 int, int, unit, 0, 0, 1629 int, int, port, 0, 0, 1630 portmod_speed_config_t*, portmod_speed_config_t, speed_config, 1, 0); 1631 1632 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1633 portmod_port_credits_enable_set, 1634 int, int, unit, 0, 0, 1635 int, int, port, 0, 0, 1636 int, int, enable, 0, 0); 1637 1638 #ifdef CPRIMOD_SUPPORT 1639 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1640 portmod_cpri_port_stage_activate, 1641 int, int, unit, 0, 0, 1642 int, int, port, 0, 0, 1643 portmod_cpri_stage_t, portmod_cpri_stage_t, stage, 0, 0); 1644 1645 #endif /* CPRIMOD_SUPPORT */ 1646 #ifdef CPRIMOD_SUPPORT 1647 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1648 portmod_cpri_port_rsvd4_tx_fsm_state_set, 1649 int, int, unit, 0, 0, 1650 int, int, port, 0, 0, 1651 cprimod_rsvd4_tx_fsm_state_t, cprimod_rsvd4_tx_fsm_state_t, state, 0, 0); 1652 1653 #endif /* CPRIMOD_SUPPORT */ 1654 #ifdef CPRIMOD_SUPPORT 1655 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1656 portmod_cpri_port_rsvd4_tx_override_set, 1657 int, int, unit, 0, 0, 1658 int, int, port, 0, 0, 1659 cprimod_rsvd4_tx_overide_t, cprimod_rsvd4_tx_overide_t, parameter, 0, 0, 1660 int, int, enable, 0, 0, 1661 int, int, value, 0, 0); 1662 1663 #endif /* CPRIMOD_SUPPORT */ 1664 #ifdef CPRIMOD_SUPPORT 1665 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1666 portmod_cpri_port_rsvd4_rx_override_set, 1667 int, int, unit, 0, 0, 1668 int, int, port, 0, 0, 1669 cprimod_rsvd4_rx_overide_t, cprimod_rsvd4_rx_overide_t, parameter, 0, 0, 1670 int, int, enable, 0, 0, 1671 int, int, value, 0, 0); 1672 1673 #endif /* CPRIMOD_SUPPORT */ 1674 #ifdef CPRIMOD_SUPPORT 1675 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1676 portmod_cpri_port_rx_axc_frame_add, 1677 int, int, unit, 0, 0, 1678 int, int, port, 0, 0, 1679 uint32, uint32, axc_id, 0, 0, 1680 portmod_cpri_axc_frame_info_t*, portmod_cpri_axc_frame_info_t, frame_info, 1, 0); 1681 1682 #endif /* CPRIMOD_SUPPORT */ 1683 #ifdef CPRIMOD_SUPPORT 1684 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1685 portmod_cpri_port_rx_frame_optional_config_get, 1686 int, int, unit, 0, 0, 1687 int, int, port, 0, 0, 1688 cprimod_rx_config_field_t, cprimod_rx_config_field_t, field, 0, 0, 1689 int*, int, value, 1, 0); 1690 1691 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1692 portmod_cpri_port_rx_frame_optional_config_set, 1693 int, int, unit, 0, 0, 1694 int, int, port, 0, 0, 1695 cprimod_rx_config_field_t, cprimod_rx_config_field_t, field, 0, 0, 1696 int, int, value, 0, 0); 1697 1698 #endif /* CPRIMOD_SUPPORT */ 1699 #ifdef CPRIMOD_SUPPORT 1700 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1701 portmod_cpri_port_tx_frame_optional_config_get, 1702 int, int, unit, 0, 0, 1703 int, int, port, 0, 0, 1704 cprimod_tx_config_field_t, cprimod_tx_config_field_t, field, 0, 0, 1705 uint32*, uint32, value, 1, 0); 1706 1707 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1708 portmod_cpri_port_tx_frame_optional_config_set, 1709 int, int, unit, 0, 0, 1710 int, int, port, 0, 0, 1711 cprimod_tx_config_field_t, cprimod_tx_config_field_t, field, 0, 0, 1712 uint32, uint32, value, 0, 0); 1713 1714 #endif /* CPRIMOD_SUPPORT */ 1715 #ifdef CPRIMOD_SUPPORT 1716 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1717 portmod_port_rsvd4_rx_frame_optional_config_get, 1718 int, int, unit, 0, 0, 1719 int, int, port, 0, 0, 1720 cprimod_rsvd4_rx_config_field_t, cprimod_rsvd4_rx_config_field_t, field, 0, 0, 1721 int*, int, value, 1, 0); 1722 1723 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1724 portmod_port_rsvd4_rx_frame_optional_config_set, 1725 int, int, unit, 0, 0, 1726 int, int, port, 0, 0, 1727 cprimod_rsvd4_rx_config_field_t, cprimod_rsvd4_rx_config_field_t, field, 0, 0, 1728 int, int, value, 0, 0); 1729 1730 #endif /* CPRIMOD_SUPPORT */ 1731 #ifdef CPRIMOD_SUPPORT 1732 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1733 portmod_port_rsvd4_tx_frame_optional_config_get, 1734 int, int, unit, 0, 0, 1735 int, int, port, 0, 0, 1736 cprimod_rsvd4_tx_config_field_t, cprimod_rsvd4_tx_config_field_t, field, 0, 0, 1737 int*, int, value, 1, 0); 1738 1739 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1740 portmod_port_rsvd4_tx_frame_optional_config_set, 1741 int, int, unit, 0, 0, 1742 int, int, port, 0, 0, 1743 cprimod_rsvd4_tx_config_field_t, cprimod_rsvd4_tx_config_field_t, field, 0, 0, 1744 int, int, value, 0, 0); 1745 1746 #endif /* CPRIMOD_SUPPORT */ 1747 #ifdef CPRIMOD_SUPPORT 1748 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1749 portmod_port_rsvd4_rx_speed_get, 1750 int, int, unit, 0, 0, 1751 int, int, port, 0, 0, 1752 cprimod_port_rsvd4_speed_mult_t*, cprimod_port_rsvd4_speed_mult_t, speed, 1, 0); 1753 1754 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1755 portmod_port_rsvd4_rx_speed_set, 1756 int, int, unit, 0, 0, 1757 int, int, port, 0, 0, 1758 cprimod_port_rsvd4_speed_mult_t, cprimod_port_rsvd4_speed_mult_t, speed, 0, 0); 1759 1760 #endif /* CPRIMOD_SUPPORT */ 1761 #ifdef CPRIMOD_SUPPORT 1762 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1763 portmod_port_rsvd4_tx_speed_get, 1764 int, int, unit, 0, 0, 1765 int, int, port, 0, 0, 1766 cprimod_port_rsvd4_speed_mult_t*, cprimod_port_rsvd4_speed_mult_t, speed, 1, 0); 1767 1768 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1769 portmod_port_rsvd4_tx_speed_set, 1770 int, int, unit, 0, 0, 1771 int, int, port, 0, 0, 1772 cprimod_port_rsvd4_speed_mult_t, cprimod_port_rsvd4_speed_mult_t, speed, 0, 0); 1773 1774 #endif /* CPRIMOD_SUPPORT */ 1775 #ifdef CPRIMOD_SUPPORT 1776 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1777 portmod_cpri_port_rx_axc_frame_delete, 1778 int, int, unit, 0, 0, 1779 int, int, port, 0, 0, 1780 uint32, uint32, axc_id, 0, 0); 1781 1782 #endif /* CPRIMOD_SUPPORT */ 1783 #ifdef CPRIMOD_SUPPORT 1784 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1785 portmod_cpri_port_rx_axc_frame_get, 1786 int, int, unit, 0, 0, 1787 int, int, port, 0, 0, 1788 uint32, uint32, axc_id, 0, 0, 1789 uint32, uint32, from_get_all, 0, 0, 1790 portmod_cpri_axc_frame_info_t*, portmod_cpri_axc_frame_info_t, frame_info, 1, 0); 1791 1792 #endif /* CPRIMOD_SUPPORT */ 1793 #ifdef CPRIMOD_SUPPORT 1794 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1795 portmod_cpri_port_rsvd4_rx_fsm_state_set, 1796 int, int, unit, 0, 0, 1797 int, int, port, 0, 0, 1798 cprimod_rsvd4_rx_fsm_state_t, cprimod_rsvd4_rx_fsm_state_t, state, 0, 0); 1799 1800 #endif /* CPRIMOD_SUPPORT */ 1801 #ifdef CPRIMOD_SUPPORT 1802 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1803 portmod_cpri_port_tx_axc_frame_add, 1804 int, int, unit, 0, 0, 1805 int, int, port, 0, 0, 1806 uint32, uint32, axc_id, 0, 0, 1807 portmod_cpri_axc_frame_info_t*, portmod_cpri_axc_frame_info_t, frame_info, 1, 0); 1808 1809 #endif /* CPRIMOD_SUPPORT */ 1810 #ifdef CPRIMOD_SUPPORT 1811 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1812 portmod_cpri_port_tx_axc_frame_delete, 1813 int, int, unit, 0, 0, 1814 int, int, port, 0, 0, 1815 uint32, uint32, axc_id, 0, 0); 1816 1817 #endif /* CPRIMOD_SUPPORT */ 1818 #ifdef CPRIMOD_SUPPORT 1819 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1820 portmod_cpri_port_tx_axc_frame_get, 1821 int, int, unit, 0, 0, 1822 int, int, port, 0, 0, 1823 uint32, uint32, axc_id, 0, 0, 1824 uint32, uint32, from_get_all, 0, 0, 1825 portmod_cpri_axc_frame_info_t*, portmod_cpri_axc_frame_info_t, frame_info, 1, 0); 1826 1827 #endif /* CPRIMOD_SUPPORT */ 1828 #ifdef CPRIMOD_SUPPORT 1829 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1830 portmod_cpri_port_encap_get, 1831 int, int, unit, 0, 0, 1832 int, int, port, 0, 0, 1833 uint32, uint32, queue_num, 0, 0, 1834 cprimod_encap_header_config_t*, cprimod_encap_header_config_t, config, 1, 0); 1835 1836 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1837 portmod_cpri_port_encap_set, 1838 int, int, unit, 0, 0, 1839 int, int, port, 0, 0, 1840 uint32, uint32, queue_num, 0, 0, 1841 cprimod_encap_header_config_t*, cprimod_encap_header_config_t, config, 1, 0); 1842 1843 #endif /* CPRIMOD_SUPPORT */ 1844 #ifdef CPRIMOD_SUPPORT 1845 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1846 portmod_cpri_port_encap_roe_ordering_info_get, 1847 int, int, unit, 0, 0, 1848 int, int, port, 0, 0, 1849 uint32, uint32, index, 0, 0, 1850 cprimod_encap_ordering_info_entry_t*, cprimod_encap_ordering_info_entry_t, config, 1, 0); 1851 1852 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1853 portmod_cpri_port_encap_roe_ordering_info_set, 1854 int, int, unit, 0, 0, 1855 int, int, port, 0, 0, 1856 uint32, uint32, index, 0, 0, 1857 cprimod_encap_ordering_info_entry_t*, cprimod_encap_ordering_info_entry_t, config, 1, 0); 1858 1859 #endif /* CPRIMOD_SUPPORT */ 1860 #ifdef CPRIMOD_SUPPORT 1861 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1862 portmod_cpri_port_encap_roe_ordering_sequence_offset_get, 1863 int, int, unit, 0, 0, 1864 int, int, port, 0, 0, 1865 uint32, uint32, queue_num, 0, 0, 1866 uint32, uint32, control, 0, 0, 1867 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, config, 1, 0); 1868 1869 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1870 portmod_cpri_port_encap_roe_ordering_sequence_offset_set, 1871 int, int, unit, 0, 0, 1872 int, int, port, 0, 0, 1873 uint32, uint32, queue_num, 0, 0, 1874 uint32, uint32, control, 0, 0, 1875 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, config, 1, 0); 1876 1877 #endif /* CPRIMOD_SUPPORT */ 1878 #ifdef CPRIMOD_SUPPORT 1879 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1880 portmod_cpri_port_roe_encap_macda_entry_get, 1881 int, int, unit, 0, 0, 1882 int, int, port, 0, 0, 1883 uint32, uint32, index, 0, 0, 1884 cprimod_mac_addr_t, cprimod_mac_addr_t, mac_addr, 0, 0); 1885 1886 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1887 portmod_cpri_port_roe_encap_macda_entry_set, 1888 int, int, unit, 0, 0, 1889 int, int, port, 0, 0, 1890 uint32, uint32, index, 0, 0, 1891 cprimod_mac_addr_t, cprimod_mac_addr_t, mac_addr, 0, 0); 1892 1893 #endif /* CPRIMOD_SUPPORT */ 1894 #ifdef CPRIMOD_SUPPORT 1895 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1896 portmod_cpri_port_roe_encap_macsa_entry_get, 1897 int, int, unit, 0, 0, 1898 int, int, port, 0, 0, 1899 uint32, uint32, index, 0, 0, 1900 cprimod_mac_addr_t, cprimod_mac_addr_t, mac_addr, 0, 0); 1901 1902 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1903 portmod_cpri_port_roe_encap_macsa_entry_set, 1904 int, int, unit, 0, 0, 1905 int, int, port, 0, 0, 1906 uint32, uint32, index, 0, 0, 1907 cprimod_mac_addr_t, cprimod_mac_addr_t, mac_addr, 0, 0); 1908 1909 #endif /* CPRIMOD_SUPPORT */ 1910 #ifdef CPRIMOD_SUPPORT 1911 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1912 portmod_cpri_port_roe_encap_vlan_entry_get, 1913 int, int, unit, 0, 0, 1914 int, int, port, 0, 0, 1915 uint32, uint32, index, 0, 0, 1916 cprimod_vlan_table_id_t, cprimod_vlan_table_id_t, table_id, 0, 0, 1917 uint32*, uint32, vlan_id, 1, 0); 1918 1919 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1920 portmod_cpri_port_roe_encap_vlan_entry_set, 1921 int, int, unit, 0, 0, 1922 int, int, port, 0, 0, 1923 uint32, uint32, index, 0, 0, 1924 cprimod_vlan_table_id_t, cprimod_vlan_table_id_t, table_id, 0, 0, 1925 uint32, uint32, vlan_id, 0, 0); 1926 1927 #endif /* CPRIMOD_SUPPORT */ 1928 #ifdef CPRIMOD_SUPPORT 1929 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1930 portmod_cpri_port_decap_ethertype_config_get, 1931 int, int, unit, 0, 0, 1932 int, int, port, 0, 0, 1933 cprimod_ethertype_t, cprimod_ethertype_t, pkt_type, 0, 0, 1934 uint16*, uint16, ethtype, 1, 0); 1935 1936 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1937 portmod_cpri_port_decap_ethertype_config_set, 1938 int, int, unit, 0, 0, 1939 int, int, port, 0, 0, 1940 cprimod_ethertype_t, cprimod_ethertype_t, pkt_type, 0, 0, 1941 uint16, uint16, ethtype, 0, 0); 1942 1943 #endif /* CPRIMOD_SUPPORT */ 1944 #ifdef CPRIMOD_SUPPORT 1945 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1946 portmod_cpri_port_encap_ethertype_config_get, 1947 int, int, unit, 0, 0, 1948 int, int, port, 0, 0, 1949 cprimod_ethertype_t, cprimod_ethertype_t, pkt_type, 0, 0, 1950 uint16*, uint16, ethtype, 1, 0); 1951 1952 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1953 portmod_cpri_port_encap_ethertype_config_set, 1954 int, int, unit, 0, 0, 1955 int, int, port, 0, 0, 1956 cprimod_ethertype_t, cprimod_ethertype_t, pkt_type, 0, 0, 1957 uint16, uint16, ethtype, 0, 0); 1958 1959 #endif /* CPRIMOD_SUPPORT */ 1960 #ifdef CPRIMOD_SUPPORT 1961 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1962 portmod_cpri_port_decap_flow_config_get, 1963 int, int, unit, 0, 0, 1964 int, int, port, 0, 0, 1965 uint8, uint8, roe_subtype, 0, 0, 1966 uint32*, uint32, queue_num, 1, 0, 1967 cprimod_cls_option_t*, cprimod_cls_option_t, cls_option, 1, 0, 1968 cprimod_cls_flow_type_t*, cprimod_cls_flow_type_t, flow_type, 1, 0); 1969 1970 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1971 portmod_cpri_port_decap_flow_config_set, 1972 int, int, unit, 0, 0, 1973 int, int, port, 0, 0, 1974 uint8, uint8, roe_subtype, 0, 0, 1975 uint32, uint32, queue_num, 0, 0, 1976 cprimod_cls_option_t, cprimod_cls_option_t, cls_option, 0, 0, 1977 cprimod_cls_flow_type_t, cprimod_cls_flow_type_t, flow_type, 0, 0); 1978 1979 #endif /* CPRIMOD_SUPPORT */ 1980 #ifdef CPRIMOD_SUPPORT 1981 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1982 portmod_cpri_port_decap_queue_to_ordering_info_index_get, 1983 int, int, unit, 0, 0, 1984 int, int, port, 0, 0, 1985 uint32, uint32, queue_num, 0, 0, 1986 uint32*, uint32, ordering_info_index, 1, 0); 1987 1988 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1989 portmod_cpri_port_decap_queue_to_ordering_info_index_set, 1990 int, int, unit, 0, 0, 1991 int, int, port, 0, 0, 1992 uint32, uint32, queue_num, 0, 0, 1993 uint32, uint32, ordering_info_index, 0, 0); 1994 1995 #endif /* CPRIMOD_SUPPORT */ 1996 #ifdef CPRIMOD_SUPPORT 1997 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1998 portmod_cpri_port_decap_flow_to_queue_mapping_get, 1999 int, int, unit, 0, 0, 2000 int, int, port, 0, 0, 2001 uint32, uint32, flow_id, 0, 0, 2002 uint32*, uint32, queue_num, 1, 0); 2003 2004 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2005 portmod_cpri_port_decap_flow_to_queue_mapping_set, 2006 int, int, unit, 0, 0, 2007 int, int, port, 0, 0, 2008 uint32, uint32, flow_id, 0, 0, 2009 uint32, uint32, queue_num, 0, 0); 2010 2011 #endif /* CPRIMOD_SUPPORT */ 2012 #ifdef CPRIMOD_SUPPORT 2013 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2014 portmod_cpri_port_decap_roe_ordering_info_get, 2015 int, int, unit, 0, 0, 2016 int, int, port, 0, 0, 2017 uint32, uint32, index, 0, 0, 2018 cprimod_decap_ordering_info_entry_t*, cprimod_decap_ordering_info_entry_t, config, 1, 0); 2019 2020 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2021 portmod_cpri_port_decap_roe_ordering_info_set, 2022 int, int, unit, 0, 0, 2023 int, int, port, 0, 0, 2024 uint32, uint32, index, 0, 0, 2025 cprimod_decap_ordering_info_entry_t*, cprimod_decap_ordering_info_entry_t, config, 1, 0); 2026 2027 #endif /* CPRIMOD_SUPPORT */ 2028 #ifdef CPRIMOD_SUPPORT 2029 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2030 portmod_cpri_port_decap_roe_ordering_sequence_offset_get, 2031 int, int, unit, 0, 0, 2032 int, int, port, 0, 0, 2033 uint32, uint32, queue_num, 0, 0, 2034 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, config, 1, 0); 2035 2036 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2037 portmod_cpri_port_decap_roe_ordering_sequence_offset_set, 2038 int, int, unit, 0, 0, 2039 int, int, port, 0, 0, 2040 uint32, uint32, queue_num, 0, 0, 2041 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, config, 1, 0); 2042 2043 #endif /* CPRIMOD_SUPPORT */ 2044 #ifdef CPRIMOD_SUPPORT 2045 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2046 portmod_cpri_port_tx_frame_tgen_config_get, 2047 int, int, unit, 0, 0, 2048 int, int, port, 0, 0, 2049 portmod_tx_frame_tgen_config_t*, portmod_tx_frame_tgen_config_t, config, 1, 0); 2050 2051 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2052 portmod_cpri_port_tx_frame_tgen_config_set, 2053 int, int, unit, 0, 0, 2054 int, int, port, 0, 0, 2055 portmod_tx_frame_tgen_config_t*, portmod_tx_frame_tgen_config_t, config, 1, 0); 2056 2057 #endif /* CPRIMOD_SUPPORT */ 2058 #ifdef CPRIMOD_SUPPORT 2059 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2060 portmod_cpri_port_tx_frame_tgen_enable, 2061 int, int, unit, 0, 0, 2062 int, int, port, 0, 0, 2063 uint32, uint32, enable, 0, 0); 2064 2065 #endif /* CPRIMOD_SUPPORT */ 2066 #ifdef CPRIMOD_SUPPORT 2067 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2068 portmod_cpri_port_tx_frame_tgen_ts_offset_get, 2069 int, int, unit, 0, 0, 2070 int, int, port, 0, 0, 2071 uint64*, uint64, offset, 1, 0); 2072 2073 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2074 portmod_cpri_port_tx_frame_tgen_ts_offset_set, 2075 int, int, unit, 0, 0, 2076 int, int, port, 0, 0, 2077 uint64, uint64, offset, 0, 0); 2078 2079 #endif /* CPRIMOD_SUPPORT */ 2080 #ifdef CPRIMOD_SUPPORT 2081 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2082 portmod_cpri_port_tx_frame_next_hfn_get, 2083 int, int, unit, 0, 0, 2084 int, int, port, 0, 0, 2085 uint32*, uint32, hfn, 1, 0); 2086 2087 #endif /* CPRIMOD_SUPPORT */ 2088 #ifdef CPRIMOD_SUPPORT 2089 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2090 portmod_cpri_port_tx_frame_next_bfn_get, 2091 int, int, unit, 0, 0, 2092 int, int, port, 0, 0, 2093 uint32*, uint32, bfn, 1, 0); 2094 2095 #endif /* CPRIMOD_SUPPORT */ 2096 #ifdef CPRIMOD_SUPPORT 2097 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2098 portmod_cpri_port_rsvd4_rx_flow_add, 2099 int, int, unit, 0, 0, 2100 int, int, port, 0, 0, 2101 uint32, uint32, flow_id, 0, 0, 2102 portmod_rsvd4_rx_flow_info_t*, portmod_rsvd4_rx_flow_info_t, info, 1, 0); 2103 2104 #endif /* CPRIMOD_SUPPORT */ 2105 #ifdef CPRIMOD_SUPPORT 2106 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2107 portmod_cpri_port_rsvd4_rx_flow_delete, 2108 int, int, unit, 0, 0, 2109 int, int, port, 0, 0, 2110 uint32, uint32, flow_id, 0, 0); 2111 2112 #endif /* CPRIMOD_SUPPORT */ 2113 #ifdef CPRIMOD_SUPPORT 2114 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2115 portmod_cpri_port_rsvd4_tx_flow_add, 2116 int, int, unit, 0, 0, 2117 int, int, port, 0, 0, 2118 uint32, uint32, flow_id, 0, 0, 2119 portmod_rsvd4_tx_flow_info_t*, portmod_rsvd4_tx_flow_info_t, info, 1, 0); 2120 2121 #endif /* CPRIMOD_SUPPORT */ 2122 #ifdef CPRIMOD_SUPPORT 2123 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2124 portmod_cpri_port_rsvd4_tx_flow_delete, 2125 int, int, unit, 0, 0, 2126 int, int, port, 0, 0, 2127 uint32, uint32, flow_id, 0, 0); 2128 2129 #endif /* CPRIMOD_SUPPORT */ 2130 #ifdef CPRIMOD_SUPPORT 2131 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2132 portmod_cpri_port_rsvd4_dbm_entry_get, 2133 int, int, unit, 0, 0, 2134 int, int, port, 0, 0, 2135 uint32, uint32, profile_id, 0, 0, 2136 cprimod_dbm_rule_entry_t*, cprimod_dbm_rule_entry_t, profile, 1, 0); 2137 2138 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2139 portmod_cpri_port_rsvd4_dbm_entry_set, 2140 int, int, unit, 0, 0, 2141 int, int, port, 0, 0, 2142 uint32, uint32, profile_id, 0, 0, 2143 cprimod_dbm_rule_entry_t*, cprimod_dbm_rule_entry_t, profile, 1, 0); 2144 2145 #endif /* CPRIMOD_SUPPORT */ 2146 #ifdef CPRIMOD_SUPPORT 2147 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2148 portmod_cpri_port_rsvd4_secondary_dbm_entry_get, 2149 int, int, unit, 0, 0, 2150 int, int, port, 0, 0, 2151 uint32, uint32, profile_id, 0, 0, 2152 cprimod_secondary_dbm_rule_entry_t*, cprimod_secondary_dbm_rule_entry_t, profile, 1, 0); 2153 2154 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2155 portmod_cpri_port_rsvd4_secondary_dbm_entry_set, 2156 int, int, unit, 0, 0, 2157 int, int, port, 0, 0, 2158 uint32, uint32, profile_id, 0, 0, 2159 cprimod_secondary_dbm_rule_entry_t*, cprimod_secondary_dbm_rule_entry_t, profile, 1, 0); 2160 2161 #endif /* CPRIMOD_SUPPORT */ 2162 #ifdef CPRIMOD_SUPPORT 2163 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 2164 portmod_cpri_port_rsvd4_modulo_rule_entry_get, 2165 int, int, unit, 0, 0, 2166 int, int, port, 0, 0, 2167 uint32, uint32, modulo_rule_num, 0, 0, 2168 cprimod_transmission_rule_type_t, cprimod_transmission_rule_type_t, modulo_rule_type, 0, 0, 2169 cprimod_modulo_rule_entry_t*, cprimod_modulo_rule_entry_t, modulo_rule, 1, 0); 2170 2171 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 2172 portmod_cpri_port_rsvd4_modulo_rule_entry_set, 2173 int, int, unit, 0, 0, 2174 int, int, port, 0, 0, 2175 uint32, uint32, modulo_rule_num, 0, 0, 2176 cprimod_transmission_rule_type_t, cprimod_transmission_rule_type_t, modulo_rule_type, 0, 0, 2177 cprimod_modulo_rule_entry_t*, cprimod_modulo_rule_entry_t, modulo_rule, 1, 0); 2178 2179 #endif /* CPRIMOD_SUPPORT */ 2180 #ifdef CPRIMOD_SUPPORT 2181 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2182 portmod_cpri_port_rsvd4_dbm_position_entry_get, 2183 int, int, unit, 0, 0, 2184 int, int, port, 0, 0, 2185 uint32, uint32, index, 0, 0, 2186 cprimod_dbm_pos_table_entry_t*, cprimod_dbm_pos_table_entry_t, pos_entry, 1, 0); 2187 2188 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2189 portmod_cpri_port_rsvd4_dbm_position_entry_set, 2190 int, int, unit, 0, 0, 2191 int, int, port, 0, 0, 2192 uint32, uint32, index, 0, 0, 2193 cprimod_dbm_pos_table_entry_t*, cprimod_dbm_pos_table_entry_t, pos_entry, 1, 0); 2194 2195 #endif /* CPRIMOD_SUPPORT */ 2196 #ifdef CPRIMOD_SUPPORT 2197 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2198 portmod_cpri_port_rsvd4_rx_master_frame_sync_config_get, 2199 int, int, unit, 0, 0, 2200 int, int, port, 0, 0, 2201 uint32*, uint32, master_frame_number, 1, 0, 2202 uint64*, uint64, master_frame_start_time, 1, 0); 2203 2204 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2205 portmod_cpri_port_rsvd4_rx_master_frame_sync_config_set, 2206 int, int, unit, 0, 0, 2207 int, int, port, 0, 0, 2208 uint32, uint32, master_frame_number, 0, 0, 2209 uint64, uint64, master_frame_start_time, 0, 0); 2210 2211 #endif /* CPRIMOD_SUPPORT */ 2212 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2213 portmod_pm_supported_vcos_get, 2214 int, int, unit, 0, 0, 2215 int, int, port, 0, 0, 2216 portmod_dispatch_type_t, portmod_dispatch_type_t, pm_type, 0, 0, 2217 portmod_vcos_speed_config_t*, portmod_vcos_speed_config_t, speed_config_list, 1, 0, 2218 int, int, size, 0, 0, 2219 portmod_dual_vcos_t*, portmod_dual_vcos_t, dual_vco, 1, 0); 2220 2221 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 2222 portmod_port_vcos_get, 2223 int, int, unit, 0, 0, 2224 int, int, port, 0, 0, 2225 portmod_vcos_speed_config_t*, portmod_vcos_speed_config_t, speed_config_list, 1, 0, 2226 int, int, size, 0, 0, 2227 portmod_dual_vcos_t*, portmod_dual_vcos_t, dual_vco, 1, 0); 2228 2229 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2230 portmod_port_mac_timestamp_enable_get, 2231 int, int, unit, 0, 0, 2232 int, int, port, 0, 0, 2233 int*, int, enable, 1, 0); 2234 2235 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2236 portmod_port_mac_timestamp_enable_set, 2237 int, int, unit, 0, 0, 2238 int, int, port, 0, 0, 2239 int, int, enable, 0, 0); 2240 2241 #ifdef CPRIMOD_SUPPORT 2242 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2243 portmod_cpri_port_rx_cw_sync_info_get, 2244 int, int, unit, 0, 0, 2245 int, int, port, 0, 0, 2246 uint32*, uint32, hyper_frame_num, 1, 0, 2247 uint32*, uint32, radio_frame_num, 1, 0); 2248 2249 #endif /* CPRIMOD_SUPPORT */ 2250 #ifdef CPRIMOD_SUPPORT 2251 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2252 portmod_cpri_port_rx_cw_l1_signal_info_get, 2253 int, int, unit, 0, 0, 2254 int, int, port, 0, 0, 2255 portmod_cpri_cw_l1_protocol_info_t*, portmod_cpri_cw_l1_protocol_info_t, l1_info, 1, 0); 2256 2257 #endif /* CPRIMOD_SUPPORT */ 2258 #ifdef CPRIMOD_SUPPORT 2259 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2260 portmod_cpri_port_rx_cw_l1_signal_signal_protection_get, 2261 int, int, unit, 0, 0, 2262 int, int, port, 0, 0, 2263 uint32, uint32, signal_map, 0, 0, 2264 uint32*, uint32, enable, 1, 0); 2265 2266 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2267 portmod_cpri_port_rx_cw_l1_signal_signal_protection_set, 2268 int, int, unit, 0, 0, 2269 int, int, port, 0, 0, 2270 uint32, uint32, signal_map, 0, 0, 2271 uint32, uint32, enable, 0, 0); 2272 2273 #endif /* CPRIMOD_SUPPORT */ 2274 #ifdef CPRIMOD_SUPPORT 2275 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2276 portmod_cpri_port_cw_slow_hdlc_config_get, 2277 int, int, unit, 0, 0, 2278 int, int, port, 0, 0, 2279 portmod_cpri_slow_hdlc_config_info_t*, portmod_cpri_slow_hdlc_config_info_t, config_info, 1, 0); 2280 2281 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2282 portmod_cpri_port_cw_slow_hdlc_config_set, 2283 int, int, unit, 0, 0, 2284 int, int, port, 0, 0, 2285 portmod_cpri_slow_hdlc_config_info_t*, portmod_cpri_slow_hdlc_config_info_t, config_info, 1, 0); 2286 2287 #endif /* CPRIMOD_SUPPORT */ 2288 #ifdef CPRIMOD_SUPPORT 2289 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2290 portmod_cpri_port_cw_fast_eth_config_get, 2291 int, int, unit, 0, 0, 2292 int, int, port, 0, 0, 2293 portmod_cpri_fast_eth_config_info_t*, portmod_cpri_fast_eth_config_info_t, config_info, 1, 0); 2294 2295 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2296 portmod_cpri_port_cw_fast_eth_config_set, 2297 int, int, unit, 0, 0, 2298 int, int, port, 0, 0, 2299 portmod_cpri_fast_eth_config_info_t*, portmod_cpri_fast_eth_config_info_t, config_info, 1, 0); 2300 2301 #endif /* CPRIMOD_SUPPORT */ 2302 #ifdef CPRIMOD_SUPPORT 2303 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2304 portmod_cpri_port_rx_vsd_config_get, 2305 int, int, unit, 0, 0, 2306 int, int, port, 0, 0, 2307 portmod_cpri_rx_vsd_config_info_t*, portmod_cpri_rx_vsd_config_info_t, config_info, 1, 0); 2308 2309 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2310 portmod_cpri_port_rx_vsd_config_set, 2311 int, int, unit, 0, 0, 2312 int, int, port, 0, 0, 2313 portmod_cpri_rx_vsd_config_info_t*, portmod_cpri_rx_vsd_config_info_t, config_info, 1, 0); 2314 2315 #endif /* CPRIMOD_SUPPORT */ 2316 #ifdef CPRIMOD_SUPPORT 2317 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2318 portmod_cpri_port_tx_vsd_config_get, 2319 int, int, unit, 0, 0, 2320 int, int, port, 0, 0, 2321 portmod_cpri_tx_vsd_config_info_t*, portmod_cpri_tx_vsd_config_info_t, config_info, 1, 0); 2322 2323 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2324 portmod_cpri_port_tx_vsd_config_set, 2325 int, int, unit, 0, 0, 2326 int, int, port, 0, 0, 2327 portmod_cpri_tx_vsd_config_info_t*, portmod_cpri_tx_vsd_config_info_t, config_info, 1, 0); 2328 2329 #endif /* CPRIMOD_SUPPORT */ 2330 #ifdef CPRIMOD_SUPPORT 2331 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2332 portmod_cpri_port_rx_vsd_flow_add, 2333 int, int, unit, 0, 0, 2334 int, int, port, 0, 0, 2335 uint32, uint32, group_id, 0, 0, 2336 portmod_cpri_rx_vsd_flow_info_t*, portmod_cpri_rx_vsd_flow_info_t, flow_info, 1, 0); 2337 2338 #endif /* CPRIMOD_SUPPORT */ 2339 #ifdef CPRIMOD_SUPPORT 2340 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2341 portmod_cpri_port_rx_vsd_flow_get, 2342 int, int, unit, 0, 0, 2343 int, int, port, 0, 0, 2344 uint32, uint32, group_id, 0, 0, 2345 portmod_cpri_rx_vsd_flow_info_t*, portmod_cpri_rx_vsd_flow_info_t, flow_info, 1, 0); 2346 2347 #endif /* CPRIMOD_SUPPORT */ 2348 #ifdef CPRIMOD_SUPPORT 2349 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2350 portmod_cpri_port_rx_vsd_flow_delete, 2351 int, int, unit, 0, 0, 2352 int, int, port, 0, 0, 2353 uint32, uint32, group_id, 0, 0); 2354 2355 #endif /* CPRIMOD_SUPPORT */ 2356 #ifdef CPRIMOD_SUPPORT 2357 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2358 portmod_cpri_port_tx_vsd_flow_add, 2359 int, int, unit, 0, 0, 2360 int, int, port, 0, 0, 2361 uint32, uint32, group_id, 0, 0, 2362 portmod_cpri_tx_vsd_flow_info_t*, portmod_cpri_tx_vsd_flow_info_t, flow_info, 1, 0); 2363 2364 #endif /* CPRIMOD_SUPPORT */ 2365 #ifdef CPRIMOD_SUPPORT 2366 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2367 portmod_cpri_port_tx_vsd_flow_delete, 2368 int, int, unit, 0, 0, 2369 int, int, port, 0, 0, 2370 uint32, uint32, group_id, 0, 0); 2371 2372 #endif /* CPRIMOD_SUPPORT */ 2373 #ifdef CPRIMOD_SUPPORT 2374 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2375 portmod_cpri_port_tx_vsd_flow_get, 2376 int, int, unit, 0, 0, 2377 int, int, port, 0, 0, 2378 uint32, uint32, group_id, 0, 0, 2379 portmod_cpri_tx_vsd_flow_info_t*, portmod_cpri_tx_vsd_flow_info_t, flow_info, 1, 0); 2380 2381 #endif /* CPRIMOD_SUPPORT */ 2382 #ifdef CPRIMOD_SUPPORT 2383 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2384 portmod_cpri_port_encap_queue_control_tag_to_flow_map_get, 2385 int, int, unit, 0, 0, 2386 int, int, port, 0, 0, 2387 uint32, uint32, tag_id, 0, 0, 2388 uint32*, uint32, flow_id, 1, 0); 2389 2390 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2391 portmod_cpri_port_encap_queue_control_tag_to_flow_map_set, 2392 int, int, unit, 0, 0, 2393 int, int, port, 0, 0, 2394 uint32, uint32, tag_id, 0, 0, 2395 uint32, uint32, flow_id, 0, 0); 2396 2397 #endif /* CPRIMOD_SUPPORT */ 2398 #ifdef CPRIMOD_SUPPORT 2399 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2400 portmod_cpri_port_rx_vsd_raw_config_get, 2401 int, int, unit, 0, 0, 2402 int, int, port, 0, 0, 2403 uint32, uint32, index, 0, 0, 2404 portmod_cpri_rx_vsd_raw_config_t*, portmod_cpri_rx_vsd_raw_config_t, config_info, 1, 0); 2405 2406 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2407 portmod_cpri_port_rx_vsd_raw_config_set, 2408 int, int, unit, 0, 0, 2409 int, int, port, 0, 0, 2410 uint32, uint32, index, 0, 0, 2411 portmod_cpri_rx_vsd_raw_config_t*, portmod_cpri_rx_vsd_raw_config_t, config_info, 1, 0); 2412 2413 #endif /* CPRIMOD_SUPPORT */ 2414 #ifdef CPRIMOD_SUPPORT 2415 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2416 portmod_cpri_port_tx_vsd_raw_config_get, 2417 int, int, unit, 0, 0, 2418 int, int, port, 0, 0, 2419 uint32, uint32, index, 0, 0, 2420 portmod_cpri_tx_vsd_raw_config_t*, portmod_cpri_tx_vsd_raw_config_t, config_info, 1, 0); 2421 2422 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2423 portmod_cpri_port_tx_vsd_raw_config_set, 2424 int, int, unit, 0, 0, 2425 int, int, port, 0, 0, 2426 uint32, uint32, index, 0, 0, 2427 portmod_cpri_tx_vsd_raw_config_t*, portmod_cpri_tx_vsd_raw_config_t, config_info, 1, 0); 2428 2429 #endif /* CPRIMOD_SUPPORT */ 2430 #ifdef CPRIMOD_SUPPORT 2431 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2432 portmod_cpri_port_tx_vsd_raw_filter_get, 2433 int, int, unit, 0, 0, 2434 int, int, port, 0, 0, 2435 uint32*, uint32, bfn0_value, 1, 0, 2436 uint32*, uint32, bfn0_mask, 1, 0, 2437 uint32*, uint32, bfn1_value, 1, 0, 2438 uint32*, uint32, bfn1_mask, 1, 0); 2439 2440 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2441 portmod_cpri_port_tx_vsd_raw_filter_set, 2442 int, int, unit, 0, 0, 2443 int, int, port, 0, 0, 2444 uint32, uint32, bfn0_value, 0, 0, 2445 uint32, uint32, bfn0_mask, 0, 0, 2446 uint32, uint32, bfn1_value, 0, 0, 2447 uint32, uint32, bfn1_mask, 0, 0); 2448 2449 #endif /* CPRIMOD_SUPPORT */ 2450 #ifdef CPRIMOD_SUPPORT 2451 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2452 portmod_cpri_port_rx_brcm_rsvd5_config_get, 2453 int, int, unit, 0, 0, 2454 int, int, port, 0, 0, 2455 portmod_cpri_rx_brcm_rsvd5_config_t*, portmod_cpri_rx_brcm_rsvd5_config_t, config_info, 1, 0); 2456 2457 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2458 portmod_cpri_port_rx_brcm_rsvd5_config_set, 2459 int, int, unit, 0, 0, 2460 int, int, port, 0, 0, 2461 portmod_cpri_rx_brcm_rsvd5_config_t*, portmod_cpri_rx_brcm_rsvd5_config_t, config_info, 1, 0); 2462 2463 #endif /* CPRIMOD_SUPPORT */ 2464 #ifdef CPRIMOD_SUPPORT 2465 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2466 portmod_cpri_port_tx_brcm_rsvd5_config_get, 2467 int, int, unit, 0, 0, 2468 int, int, port, 0, 0, 2469 portmod_cpri_tx_brcm_rsvd5_config_t*, portmod_cpri_tx_brcm_rsvd5_config_t, config_info, 1, 0); 2470 2471 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2472 portmod_cpri_port_tx_brcm_rsvd5_config_set, 2473 int, int, unit, 0, 0, 2474 int, int, port, 0, 0, 2475 portmod_cpri_tx_brcm_rsvd5_config_t*, portmod_cpri_tx_brcm_rsvd5_config_t, config_info, 1, 0); 2476 2477 #endif /* CPRIMOD_SUPPORT */ 2478 #ifdef CPRIMOD_SUPPORT 2479 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2480 portmod_cpri_port_rx_gcw_config_get, 2481 int, int, unit, 0, 0, 2482 int, int, port, 0, 0, 2483 uint32, uint32, index, 0, 0, 2484 portmod_cpri_rx_gcw_config_t*, portmod_cpri_rx_gcw_config_t, config_info, 1, 0); 2485 2486 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2487 portmod_cpri_port_rx_gcw_config_set, 2488 int, int, unit, 0, 0, 2489 int, int, port, 0, 0, 2490 uint32, uint32, index, 0, 0, 2491 portmod_cpri_rx_gcw_config_t*, portmod_cpri_rx_gcw_config_t, config_info, 1, 0); 2492 2493 #endif /* CPRIMOD_SUPPORT */ 2494 #ifdef CPRIMOD_SUPPORT 2495 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2496 portmod_cpri_port_tx_gcw_config_get, 2497 int, int, unit, 0, 0, 2498 int, int, port, 0, 0, 2499 uint32, uint32, index, 0, 0, 2500 portmod_cpri_tx_gcw_config_t*, portmod_cpri_tx_gcw_config_t, config_info, 1, 0); 2501 2502 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2503 portmod_cpri_port_tx_gcw_config_set, 2504 int, int, unit, 0, 0, 2505 int, int, port, 0, 0, 2506 uint32, uint32, index, 0, 0, 2507 portmod_cpri_tx_gcw_config_t*, portmod_cpri_tx_gcw_config_t, config_info, 1, 0); 2508 2509 #endif /* CPRIMOD_SUPPORT */ 2510 #ifdef CPRIMOD_SUPPORT 2511 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2512 portmod_cpri_port_tx_gcw_filter_get, 2513 int, int, unit, 0, 0, 2514 int, int, port, 0, 0, 2515 uint32*, uint32, bfn0_value, 1, 0, 2516 uint32*, uint32, bfn0_mask, 1, 0, 2517 uint32*, uint32, bfn1_value, 1, 0, 2518 uint32*, uint32, bfn1_mask, 1, 0); 2519 2520 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2521 portmod_cpri_port_tx_gcw_filter_set, 2522 int, int, unit, 0, 0, 2523 int, int, port, 0, 0, 2524 uint32, uint32, bfn0_value, 0, 0, 2525 uint32, uint32, bfn0_mask, 0, 0, 2526 uint32, uint32, bfn1_value, 0, 0, 2527 uint32, uint32, bfn1_mask, 0, 0); 2528 2529 #endif /* CPRIMOD_SUPPORT */ 2530 #ifdef CPRIMOD_SUPPORT 2531 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2532 portmod_cpri_port_tx_cw_sync_info_get, 2533 int, int, unit, 0, 0, 2534 int, int, port, 0, 0, 2535 uint32*, uint32, hyper_frame_num, 1, 0, 2536 uint32*, uint32, radio_frame_num, 1, 0); 2537 2538 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2539 portmod_cpri_port_tx_cw_sync_info_set, 2540 int, int, unit, 0, 0, 2541 int, int, port, 0, 0, 2542 uint32, uint32, hyper_frame_num, 0, 0, 2543 uint32, uint32, radio_frame_num, 0, 0); 2544 2545 #endif /* CPRIMOD_SUPPORT */ 2546 #ifdef CPRIMOD_SUPPORT 2547 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2548 portmod_cpri_port_tx_cw_l1_config_set, 2549 int, int, unit, 0, 0, 2550 int, int, port, 0, 0, 2551 portmod_cpri_cw_l1_config_info_t*, portmod_cpri_cw_l1_config_info_t, control_info, 1, 0); 2552 2553 #endif /* CPRIMOD_SUPPORT */ 2554 #ifdef CPRIMOD_SUPPORT 2555 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2556 portmod_rsvd4_rx_control_flow_add, 2557 int, int, unit, 0, 0, 2558 int, int, port, 0, 0, 2559 uint32, uint32, flow_id, 0, 0, 2560 portmod_control_flow_config_t*, portmod_control_flow_config_t, config, 1, 0); 2561 2562 #endif /* CPRIMOD_SUPPORT */ 2563 #ifdef CPRIMOD_SUPPORT 2564 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2565 portmod_rsvd4_rx_control_flow_delete, 2566 int, int, unit, 0, 0, 2567 int, int, port, 0, 0, 2568 uint32, uint32, flow_id, 0, 0, 2569 portmod_control_flow_config_t*, portmod_control_flow_config_t, config, 1, 0); 2570 2571 #endif /* CPRIMOD_SUPPORT */ 2572 #ifdef CPRIMOD_SUPPORT 2573 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2574 portmod_rsvd4_fast_eth_config_set, 2575 int, int, unit, 0, 0, 2576 int, int, port, 0, 0, 2577 portmod_cpri_fast_eth_config_t*, portmod_cpri_fast_eth_config_t, config_info, 1, 0); 2578 2579 #endif /* CPRIMOD_SUPPORT */ 2580 #ifdef CPRIMOD_SUPPORT 2581 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2582 portmod_rsvd4_rx_sync_profile_entry_get, 2583 int, int, unit, 0, 0, 2584 int, int, port, 0, 0, 2585 uint32, uint32, profile_id, 0, 0, 2586 portmod_sync_profile_entry_t*, portmod_sync_profile_entry_t, entry, 1, 0); 2587 2588 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2589 portmod_rsvd4_rx_sync_profile_entry_set, 2590 int, int, unit, 0, 0, 2591 int, int, port, 0, 0, 2592 uint32, uint32, profile_id, 0, 0, 2593 portmod_sync_profile_entry_t*, portmod_sync_profile_entry_t, entry, 1, 0); 2594 2595 #endif /* CPRIMOD_SUPPORT */ 2596 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2597 portmod_rx_tag_config_set, 2598 int, int, unit, 0, 0, 2599 int, int, port, 0, 0, 2600 uint32, uint32, default_tag, 0, 0, 2601 uint32, uint32, no_match_tag, 0, 0); 2602 2603 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2604 portmod_rx_tag_gen_entry_add, 2605 int, int, unit, 0, 0, 2606 int, int, port, 0, 0, 2607 portmod_tag_gen_entry_t*, portmod_tag_gen_entry_t, entry, 1, 0); 2608 2609 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2610 portmod_rx_tag_gen_entry_delete, 2611 int, int, unit, 0, 0, 2612 int, int, port, 0, 0, 2613 portmod_tag_gen_entry_t*, portmod_tag_gen_entry_t, entry, 1, 0); 2614 2615 #ifdef CPRIMOD_SUPPORT 2616 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2617 portmod_rsvd4_tx_control_flow_group_member_add, 2618 int, int, unit, 0, 0, 2619 int, int, port, 0, 0, 2620 uint32, uint32, group_id, 0, 0, 2621 uint32, uint32, priority, 0, 0, 2622 uint32, uint32, queue_num, 0, 0, 2623 portmod_control_msg_proc_type_t, portmod_control_msg_proc_type_t, proc_type, 0, 0); 2624 2625 #endif /* CPRIMOD_SUPPORT */ 2626 #ifdef CPRIMOD_SUPPORT 2627 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2628 portmod_rsvd4_tx_control_flow_group_member_delete, 2629 int, int, unit, 0, 0, 2630 int, int, port, 0, 0, 2631 uint32, uint32, group_id, 0, 0, 2632 uint32, uint32, priority, 0, 0); 2633 2634 #endif /* CPRIMOD_SUPPORT */ 2635 #ifdef CPRIMOD_SUPPORT 2636 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2637 portmod_rsvd4_tx_eth_message_config_set, 2638 int, int, unit, 0, 0, 2639 int, int, port, 0, 0, 2640 uint32, uint32, msg_node, 0, 0, 2641 uint32, uint32, msg_subnode, 0, 0, 2642 uint32, uint32, msg_type, 0, 0, 2643 uint32, uint32, msg_padding, 0, 0); 2644 2645 #endif /* CPRIMOD_SUPPORT */ 2646 #ifdef CPRIMOD_SUPPORT 2647 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2648 portmod_rsvd4_tx_single_raw_message_config_set, 2649 int, int, unit, 0, 0, 2650 int, int, port, 0, 0, 2651 uint32, uint32, msg_id, 0, 0, 2652 uint32, uint32, msg_type, 0, 0); 2653 2654 #endif /* CPRIMOD_SUPPORT */ 2655 #ifdef CPRIMOD_SUPPORT 2656 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2657 portmod_rsvd4_tx_control_flow_config_get, 2658 int, int, unit, 0, 0, 2659 int, int, port, 0, 0, 2660 uint32, uint32, flow_id, 0, 0, 2661 portmod_rsvd4_tx_config_info_t*, portmod_rsvd4_tx_config_info_t, config_info, 1, 0); 2662 2663 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2664 portmod_rsvd4_tx_control_flow_config_set, 2665 int, int, unit, 0, 0, 2666 int, int, port, 0, 0, 2667 uint32, uint32, flow_id, 0, 0, 2668 portmod_rsvd4_tx_config_info_t*, portmod_rsvd4_tx_config_info_t, config_info, 1, 0); 2669 2670 #endif /* CPRIMOD_SUPPORT */ 2671 #ifdef CPRIMOD_SUPPORT 2672 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2673 portmod_rsvd4_tx_control_flow_header_index_get, 2674 int, int, unit, 0, 0, 2675 int, int, port, 0, 0, 2676 uint32, uint32, roe_flow_id, 0, 0, 2677 uint32*, uint32, index, 1, 0); 2678 2679 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2680 portmod_rsvd4_tx_control_flow_header_index_set, 2681 int, int, unit, 0, 0, 2682 int, int, port, 0, 0, 2683 uint32, uint32, roe_flow_id, 0, 0, 2684 uint32, uint32, index, 0, 0); 2685 2686 #endif /* CPRIMOD_SUPPORT */ 2687 #ifdef CPRIMOD_SUPPORT 2688 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2689 portmod_rsvd4_tx_control_header_entry_get, 2690 int, int, unit, 0, 0, 2691 int, int, port, 0, 0, 2692 uint32, uint32, index, 0, 0, 2693 uint32*, uint32, header_node, 1, 0, 2694 uint32*, uint32, header_subnode, 1, 0, 2695 uint32*, uint32, payload_node, 1, 0); 2696 2697 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2698 portmod_rsvd4_tx_control_header_entry_set, 2699 int, int, unit, 0, 0, 2700 int, int, port, 0, 0, 2701 uint32, uint32, index, 0, 0, 2702 uint32, uint32, header_node, 0, 0, 2703 uint32, uint32, header_subnode, 0, 0, 2704 uint32, uint32, payload_node, 0, 0); 2705 2706 #endif /* CPRIMOD_SUPPORT */ 2707 #ifdef CPRIMOD_SUPPORT 2708 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2709 portmod_rsvd4_tx_single_tunnel_message_config_set, 2710 int, int, unit, 0, 0, 2711 int, int, port, 0, 0, 2712 portmod_cpri_crc_option_t, portmod_cpri_crc_option_t, crc_option, 0, 0); 2713 2714 #endif /* CPRIMOD_SUPPORT */ 2715 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2716 portmod_port_txpi_override_get, 2717 int, int, unit, 0, 0, 2718 int, int, port, 0, 0, 2719 portmod_txpi_override_t*, portmod_txpi_override_t, override, 1, 0); 2720 2721 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2722 portmod_port_txpi_override_set, 2723 int, int, unit, 0, 0, 2724 int, int, port, 0, 0, 2725 portmod_txpi_override_t*, portmod_txpi_override_t, override, 1, 0); 2726 2727 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2728 portmod_port_txpi_sdm_data_get, 2729 int, int, unit, 0, 0, 2730 int, int, port, 0, 0, 2731 int*, int, value, 1, 0); 2732 2733 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 2734 portmod_pm_speed_config_validate, 2735 int, int, unit, 0, 0, 2736 int, int, pm_id, 0, 0, 2737 portmod_pbmp_t*, portmod_pbmp_t, ports, 1, 0, 2738 int, int, flag, 0, 0, 2739 portmod_pm_vco_setting_t*, portmod_pm_vco_setting_t, vco_setting, 1, 0); 2740 2741 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2742 portmod_pm_vcos_get, 2743 int, int, unit, 0, 0, 2744 portmod_dispatch_type_t, portmod_dispatch_type_t, pm_type, 0, 0, 2745 uint32, uint32, flags, 0, 0, 2746 portmod_pm_vco_setting_t*, portmod_pm_vco_setting_t, vco_select, 1, 0); 2747 2748 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 2749 portmod_port_autoneg_ability_advert_get, 2750 int, int, unit, 0, 0, 2751 int, int, port, 0, 0, 2752 int, int, max_num_abilities, 0, 0, 2753 portmod_port_speed_ability_t*, portmod_port_speed_ability_t, abilities, 1, 0, 2754 int*, int, actual_num_abilities, 1, 0); 2755 2756 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2757 portmod_port_autoneg_ability_advert_set, 2758 int, int, unit, 0, 0, 2759 int, int, port, 0, 0, 2760 int, int, num_abilities, 0, 0, 2761 portmod_port_speed_ability_t*, portmod_port_speed_ability_t, abilities, 1, 0); 2762 2763 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 2764 portmod_port_autoneg_ability_remote_get, 2765 int, int, unit, 0, 0, 2766 int, int, port, 0, 0, 2767 int, int, max_num_abilities, 0, 0, 2768 portmod_port_speed_ability_t*, portmod_port_speed_ability_t, abilities, 1, 0, 2769 int*, int, actual_num_abilities, 1, 0); 2770 2771 #ifdef CPRIMOD_SUPPORT 2772 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2773 portmod_cpri_port_interrupt_callback_register, 2774 int, int, unit, 0, 0, 2775 portmod_cpri_port_intr_type_t, portmod_cpri_port_intr_type_t, cpri_intr_type, 0, 0, 2776 portmod_cpri_port_interrupt_callback_t, portmod_cpri_port_interrupt_callback_t, callback, 0, 0, 2777 void*, void, cb_data, 1, 0); 2778 2779 #endif /* CPRIMOD_SUPPORT */ 2780 #ifdef CPRIMOD_SUPPORT 2781 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2782 portmod_cpri_port_interrupt_callback_unregister, 2783 int, int, unit, 0, 0, 2784 portmod_cpri_port_intr_type_t, portmod_cpri_port_intr_type_t, cpri_intr_type, 0, 0, 2785 cprimod_cpri_port_interrupt_callback_t, cprimod_cpri_port_interrupt_callback_t, callback, 0, 0); 2786 2787 #endif /* CPRIMOD_SUPPORT */ 2788 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 2789 portmod_phy_pms_ids_get, 2790 int, int, unit, 0, 0, 2791 int, int, phy, 0, 0, 2792 int, int, max_pms, 0, 0, 2793 int*, int, nof_pms, 1, 0, 2794 portmod_dispatch_type_t*, portmod_dispatch_type_t, pms_types, 1, 0, 2795 int*, int, pms_ids, 1, 0); 2796 2797 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2798 portmod_port_pm_id_get, 2799 int, int, unit, 0, 0, 2800 int, int, port, 0, 0, 2801 int*, int, pm_id, 1, 0); 2802 2803 #ifdef CPRIMOD_SUPPORT 2804 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 2805 portmod_cpri_port_interrupt_enable_set, 2806 int, int, unit, 0, 0, 2807 int, int, port, 0, 0, 2808 portmod_cpri_port_intr_type_t, portmod_cpri_port_intr_type_t, cpri_intr_type, 0, 0, 2809 int, int, data, 0, 0, 2810 int, int, enable, 0, 0); 2811 2812 #endif /* CPRIMOD_SUPPORT */ 2813 #ifdef CPRIMOD_SUPPORT 2814 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 2815 portmod_cpri_port_interrupt_process, 2816 int, int, unit, 0, 0, 2817 int, int, port, 0, 0); 2818 2819 #endif /* CPRIMOD_SUPPORT */ 2820 #ifdef CPRIMOD_SUPPORT 2821 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2822 portmod_fast_clk_bit_time_period_get, 2823 int, int, unit, 0, 0, 2824 int, int, port, 0, 0, 2825 uint32*, uint32, bit_time_period, 1, 0); 2826 2827 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2828 portmod_fast_clk_bit_time_period_set, 2829 int, int, unit, 0, 0, 2830 int, int, port, 0, 0, 2831 uint32, uint32, bit_time_period, 0, 0); 2832 2833 #endif /* CPRIMOD_SUPPORT */ 2834 #ifdef CPRIMOD_SUPPORT 2835 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2836 portmod_1588_bit_time_period_get, 2837 int, int, unit, 0, 0, 2838 int, int, port, 0, 0, 2839 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2840 uint32*, uint32, bit_time_period, 1, 0); 2841 2842 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2843 portmod_1588_bit_time_period_set, 2844 int, int, unit, 0, 0, 2845 int, int, port, 0, 0, 2846 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2847 cprimod_port_speed_t, cprimod_port_speed_t, speed, 0, 0); 2848 2849 #endif /* CPRIMOD_SUPPORT */ 2850 #ifdef CPRIMOD_SUPPORT 2851 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2852 portmod_1588_timestamp_capture_config_get, 2853 int, int, unit, 0, 0, 2854 int, int, port, 0, 0, 2855 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2856 cprimod_1588_capture_config_t*, cprimod_1588_capture_config_t, config, 1, 0); 2857 2858 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2859 portmod_1588_timestamp_capture_config_set, 2860 int, int, unit, 0, 0, 2861 int, int, port, 0, 0, 2862 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2863 cprimod_1588_capture_config_t*, cprimod_1588_capture_config_t, config, 1, 0); 2864 2865 #endif /* CPRIMOD_SUPPORT */ 2866 #ifdef CPRIMOD_SUPPORT 2867 CINT_FWRAPPER_CREATE_RP7(int, int, 0, 0, 2868 portmod_1588_captured_timestamp_get, 2869 int, int, unit, 0, 0, 2870 int, int, port, 0, 0, 2871 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2872 portmod_1588_ts_type_t, portmod_1588_ts_type_t, ts_type, 0, 0, 2873 uint8, uint8, mx_cnt, 0, 0, 2874 uint8*, uint8, count, 1, 0, 2875 uint64*, uint64, captured_time, 1, 0); 2876 2877 #endif /* CPRIMOD_SUPPORT */ 2878 #ifdef CPRIMOD_SUPPORT 2879 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2880 portmod_1588_timestamp_adjust_get, 2881 int, int, unit, 0, 0, 2882 int, int, port, 0, 0, 2883 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2884 cprimod_1588_time_t*, cprimod_1588_time_t, adjust_time, 1, 0); 2885 2886 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2887 portmod_1588_timestamp_adjust_set, 2888 int, int, unit, 0, 0, 2889 int, int, port, 0, 0, 2890 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2891 cprimod_1588_time_t*, cprimod_1588_time_t, adjust_time, 1, 0); 2892 2893 #endif /* CPRIMOD_SUPPORT */ 2894 #ifdef CPRIMOD_SUPPORT 2895 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2896 portmod_1588_timestamp_fifo_config_get, 2897 int, int, unit, 0, 0, 2898 int, int, port, 0, 0, 2899 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2900 uint16*, uint16, modulo, 1, 0); 2901 2902 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2903 portmod_1588_timestamp_fifo_config_set, 2904 int, int, unit, 0, 0, 2905 int, int, port, 0, 0, 2906 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2907 uint16, uint16, modulo, 0, 0); 2908 2909 #endif /* CPRIMOD_SUPPORT */ 2910 #ifdef CPRIMOD_SUPPORT 2911 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2912 portmod_1588_timestamp_cmic_config_get, 2913 int, int, unit, 0, 0, 2914 int, int, port, 0, 0, 2915 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2916 uint16*, uint16, modulo, 1, 0); 2917 2918 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2919 portmod_1588_timestamp_cmic_config_set, 2920 int, int, unit, 0, 0, 2921 int, int, port, 0, 0, 2922 portmod_direction_t, portmod_direction_t, direction, 0, 0, 2923 uint16, uint16, modulo, 0, 0); 2924 2925 #endif /* CPRIMOD_SUPPORT */ 2926 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2927 portmod_port_tx_get, 2928 int, int, unit, 0, 0, 2929 int, int, port, 0, 0, 2930 phymod_tx_t*, phymod_tx_t, tx, 1, 0); 2931 2932 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2933 portmod_port_tx_set, 2934 int, int, unit, 0, 0, 2935 int, int, port, 0, 0, 2936 phymod_tx_t*, phymod_tx_t, tx, 1, 0); 2937 2938 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2939 portmod_port_synce_clk_ctrl_get, 2940 int, int, unit, 0, 0, 2941 int, int, port, 0, 0, 2942 portmod_port_synce_clk_ctrl_t*, portmod_port_synce_clk_ctrl_t, cfg, 1, 0); 2943 2944 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 2945 portmod_port_synce_clk_ctrl_set, 2946 int, int, unit, 0, 0, 2947 int, int, port, 0, 0, 2948 portmod_port_synce_clk_ctrl_t*, portmod_port_synce_clk_ctrl_t, cfg, 1, 0); 2949 2950 #ifdef CPRIMOD_SUPPORT 2951 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2952 portmod_cpri_port_rx_agnostic_config_get, 2953 int, int, unit, 0, 0, 2954 int, int, port, 0, 0, 2955 int*, int, enable, 1, 0, 2956 portmod_cpri_rx_agnostic_config_info_t*, portmod_cpri_rx_agnostic_config_info_t, config_info, 1, 0); 2957 2958 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2959 portmod_cpri_port_rx_agnostic_config_set, 2960 int, int, unit, 0, 0, 2961 int, int, port, 0, 0, 2962 int, int, enable, 0, 0, 2963 portmod_cpri_rx_agnostic_config_info_t*, portmod_cpri_rx_agnostic_config_info_t, config_info, 1, 0); 2964 2965 #endif /* CPRIMOD_SUPPORT */ 2966 #ifdef CPRIMOD_SUPPORT 2967 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2968 portmod_cpri_port_tx_agnostic_config_get, 2969 int, int, unit, 0, 0, 2970 int, int, port, 0, 0, 2971 int*, int, enable, 1, 0, 2972 portmod_cpri_tx_agnostic_config_info_t*, portmod_cpri_tx_agnostic_config_info_t, config_info, 1, 0); 2973 2974 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2975 portmod_cpri_port_tx_agnostic_config_set, 2976 int, int, unit, 0, 0, 2977 int, int, port, 0, 0, 2978 int, int, enable, 0, 0, 2979 portmod_cpri_tx_agnostic_config_info_t*, portmod_cpri_tx_agnostic_config_info_t, config_info, 1, 0); 2980 2981 #endif /* CPRIMOD_SUPPORT */ 2982 #ifdef CPRIMOD_SUPPORT 2983 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2984 portmod_cpri_port_encap_presentation_time_config_get, 2985 int, int, unit, 0, 0, 2986 int, int, port, 0, 0, 2987 portmod_presentation_time_attribute_t, portmod_presentation_time_attribute_t, attribute, 0, 0, 2988 portmod_presentation_time_t*, portmod_presentation_time_t, time, 1, 0); 2989 2990 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 2991 portmod_cpri_port_encap_presentation_time_config_set, 2992 int, int, unit, 0, 0, 2993 int, int, port, 0, 0, 2994 portmod_presentation_time_attribute_t, portmod_presentation_time_attribute_t, attribute, 0, 0, 2995 portmod_presentation_time_t*, portmod_presentation_time_t, time, 1, 0); 2996 2997 #endif /* CPRIMOD_SUPPORT */ 2998 #ifdef CPRIMOD_SUPPORT 2999 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3000 portmod_cpri_port_decap_presentation_time_config_get, 3001 int, int, unit, 0, 0, 3002 int, int, port, 0, 0, 3003 portmod_decap_presentation_time_config_t*, portmod_decap_presentation_time_config_t, config, 1, 0); 3004 3005 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3006 portmod_cpri_port_decap_presentation_time_config_set, 3007 int, int, unit, 0, 0, 3008 int, int, port, 0, 0, 3009 portmod_decap_presentation_time_config_t*, portmod_decap_presentation_time_config_t, config, 1, 0); 3010 3011 #endif /* CPRIMOD_SUPPORT */ 3012 #ifdef CPRIMOD_SUPPORT 3013 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 3014 portmod_cpri_port_compression_lookup_table_get, 3015 int, int, unit, 0, 0, 3016 int, int, port, 0, 0, 3017 int, int, max_depth, 0, 0, 3018 int*, int, table_depth, 1, 0, 3019 uint32*, uint32, table, 1, 0); 3020 3021 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3022 portmod_cpri_port_compression_lookup_table_set, 3023 int, int, unit, 0, 0, 3024 int, int, port, 0, 0, 3025 int, int, table_depth, 0, 0, 3026 uint32*, uint32, table, 1, 0); 3027 3028 #endif /* CPRIMOD_SUPPORT */ 3029 #ifdef CPRIMOD_SUPPORT 3030 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 3031 portmod_cpri_port_decompression_lookup_table_get, 3032 int, int, unit, 0, 0, 3033 int, int, port, 0, 0, 3034 int, int, max_depth, 0, 0, 3035 int*, int, table_depth, 1, 0, 3036 uint32*, uint32, table, 1, 0); 3037 3038 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3039 portmod_cpri_port_decompression_lookup_table_set, 3040 int, int, unit, 0, 0, 3041 int, int, port, 0, 0, 3042 int, int, table_depth, 0, 0, 3043 uint32*, uint32, table, 1, 0); 3044 3045 #endif /* CPRIMOD_SUPPORT */ 3046 #ifdef CPRIMOD_SUPPORT 3047 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 3048 portmod_cpri_port_decap_queue_flow_control_get, 3049 int, int, unit, 0, 0, 3050 int, int, port, 0, 0, 3051 uint32, uint32, queue_num, 0, 0, 3052 int*, int, enable, 1, 0, 3053 uint32_t*, uint32_t, xon_threshold, 1, 0, 3054 uint32_t*, uint32_t, xoff_threshold, 1, 0); 3055 3056 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 3057 portmod_cpri_port_decap_queue_flow_control_set, 3058 int, int, unit, 0, 0, 3059 int, int, port, 0, 0, 3060 uint32, uint32, queue_num, 0, 0, 3061 int, int, enable, 0, 0, 3062 uint32_t, uint32_t, xon_threshold, 0, 0, 3063 uint32_t, uint32_t, xoff_threshold, 0, 0); 3064 3065 #endif /* CPRIMOD_SUPPORT */ 3066 #ifdef CPRIMOD_SUPPORT 3067 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3068 portmod_cpri_port_fec_enable_get, 3069 int, int, unit, 0, 0, 3070 int, int, port, 0, 0, 3071 portmod_direction_t, portmod_direction_t, dir, 0, 0, 3072 int*, int, enable, 1, 0); 3073 3074 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3075 portmod_cpri_port_fec_enable_set, 3076 int, int, unit, 0, 0, 3077 int, int, port, 0, 0, 3078 portmod_direction_t, portmod_direction_t, dir, 0, 0, 3079 int, int, enable, 0, 0); 3080 3081 #endif /* CPRIMOD_SUPPORT */ 3082 #ifdef CPRIMOD_SUPPORT 3083 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3084 portmod_cpri_port_fec_timestamp_config_get, 3085 int, int, unit, 0, 0, 3086 int, int, port, 0, 0, 3087 portmod_direction_t, portmod_direction_t, dir, 0, 0, 3088 portmod_fec_timestamp_config_t*, portmod_fec_timestamp_config_t, config, 1, 0); 3089 3090 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3091 portmod_cpri_port_fec_timestamp_config_set, 3092 int, int, unit, 0, 0, 3093 int, int, port, 0, 0, 3094 portmod_direction_t, portmod_direction_t, dir, 0, 0, 3095 portmod_fec_timestamp_config_t*, portmod_fec_timestamp_config_t, config, 1, 0); 3096 3097 #endif /* CPRIMOD_SUPPORT */ 3098 #ifdef CPRIMOD_SUPPORT 3099 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3100 portmod_cpri_port_fec_aux_config_get, 3101 int, int, unit, 0, 0, 3102 int, int, port, 0, 0, 3103 portmod_fec_aux_config_para_t, portmod_fec_aux_config_para_t, parameter_id, 0, 0, 3104 uint32*, uint32, value, 1, 0); 3105 3106 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3107 portmod_cpri_port_fec_aux_config_set, 3108 int, int, unit, 0, 0, 3109 int, int, port, 0, 0, 3110 portmod_fec_aux_config_para_t, portmod_fec_aux_config_para_t, parameter_id, 0, 0, 3111 uint32, uint32, value, 0, 0); 3112 3113 #endif /* CPRIMOD_SUPPORT */ 3114 #ifdef CPRIMOD_SUPPORT 3115 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3116 portmod_cpri_port_ecc_interrupt_enable_set, 3117 int, int, unit, 0, 0, 3118 int, int, port, 0, 0, 3119 int, int, enable, 0, 0); 3120 3121 #endif /* CPRIMOD_SUPPORT */ 3122 #ifdef CPRIMOD_SUPPORT 3123 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3124 portmod_cpri_port_ecc_interrupt_status_get, 3125 int, int, unit, 0, 0, 3126 int, int, port, 0, 0, 3127 portmod_cpri_ecc_intr_info_t*, portmod_cpri_ecc_intr_info_t, ecc_err_info, 1, 0); 3128 3129 #endif /* CPRIMOD_SUPPORT */ 3130 #ifdef CPRIMOD_SUPPORT 3131 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 3132 portmod_cpri_init, 3133 int, int, unit, 0, 0, 3134 int, int, port, 0, 0); 3135 3136 #endif /* CPRIMOD_SUPPORT */ 3137 #ifdef CPRIMOD_SUPPORT 3138 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3139 portmod_cpri_port_rx_gcw_word_get, 3140 int, int, unit, 0, 0, 3141 int, int, port, 0, 0, 3142 int, int, group_index, 0, 0, 3143 uint16*, uint16, gcw_word, 1, 0); 3144 3145 #endif /* CPRIMOD_SUPPORT */ 3146 #ifdef CPRIMOD_SUPPORT 3147 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3148 portmod_cpri_port_tx_gcw_word_set, 3149 int, int, unit, 0, 0, 3150 int, int, port, 0, 0, 3151 int, int, group_index, 0, 0, 3152 uint16, uint16, gcw_word, 0, 0); 3153 3154 #endif /* CPRIMOD_SUPPORT */ 3155 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3156 portmod_pm_interrupt_process, 3157 int, int, unit, 0, 0, 3158 int, int, pm_id, 0, 0, 3159 portmod_ecc_intr_info_t*, portmod_ecc_intr_info_t, ecc_err_info, 1, 0); 3160 3161 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3162 portmod_port_rlm_config_set, 3163 int, int, unit, 0, 0, 3164 int, int, port, 0, 0, 3165 int, int, enable, 0, 0, 3166 portmod_port_rlm_config_t*, portmod_port_rlm_config_t, rlm_config, 1, 0); 3167 3168 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3169 portmod_port_rlm_config_get, 3170 int, int, unit, 0, 0, 3171 int, int, port, 0, 0, 3172 int*, int, enable, 1, 0, 3173 portmod_port_rlm_config_t*, portmod_port_rlm_config_t, rlm_status, 1, 0); 3174 3175 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3176 portmod_port_rlm_status_get, 3177 int, int, unit, 0, 0, 3178 int, int, port, 0, 0, 3179 portmod_port_rlm_status_t*, portmod_port_rlm_status_t, rlm_status, 1, 0); 3180 3181 #ifdef CPRIMOD_SUPPORT 3182 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3183 portmod_cpri_port_rx_tunnel_mode_config_get, 3184 int, int, unit, 0, 0, 3185 int, int, port, 0, 0, 3186 int*, int, enable, 1, 0, 3187 portmod_cpri_rx_tunnel_mode_config_t*, portmod_cpri_rx_tunnel_mode_config_t, config_info, 1, 0); 3188 3189 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3190 portmod_cpri_port_rx_tunnel_mode_config_set, 3191 int, int, unit, 0, 0, 3192 int, int, port, 0, 0, 3193 int, int, enable, 0, 0, 3194 portmod_cpri_rx_tunnel_mode_config_t*, portmod_cpri_rx_tunnel_mode_config_t, config_info, 1, 0); 3195 3196 #endif /* CPRIMOD_SUPPORT */ 3197 #ifdef CPRIMOD_SUPPORT 3198 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3199 portmod_cpri_port_tx_tunnel_mode_config_get, 3200 int, int, unit, 0, 0, 3201 int, int, port, 0, 0, 3202 int*, int, enable, 1, 0, 3203 portmod_cpri_tx_tunnel_mode_config_t*, portmod_cpri_tx_tunnel_mode_config_t, config_info, 1, 0); 3204 3205 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3206 portmod_cpri_port_tx_tunnel_mode_config_set, 3207 int, int, unit, 0, 0, 3208 int, int, port, 0, 0, 3209 int, int, enable, 0, 0, 3210 portmod_cpri_tx_tunnel_mode_config_t*, portmod_cpri_tx_tunnel_mode_config_t, config_info, 1, 0); 3211 3212 #endif /* CPRIMOD_SUPPORT */ 3213 #ifdef CPRIMOD_SUPPORT 3214 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3215 portmod_rsvd4_port_rx_agnostic_config_get, 3216 int, int, unit, 0, 0, 3217 int, int, port, 0, 0, 3218 int*, int, enable, 1, 0, 3219 portmod_rsvd4_rx_agnostic_config_t*, portmod_rsvd4_rx_agnostic_config_t, config_info, 1, 0); 3220 3221 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3222 portmod_rsvd4_port_rx_agnostic_config_set, 3223 int, int, unit, 0, 0, 3224 int, int, port, 0, 0, 3225 int, int, enable, 0, 0, 3226 portmod_rsvd4_rx_agnostic_config_t*, portmod_rsvd4_rx_agnostic_config_t, config_info, 1, 0); 3227 3228 #endif /* CPRIMOD_SUPPORT */ 3229 #ifdef CPRIMOD_SUPPORT 3230 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3231 portmod_rsvd4_port_tx_agnostic_config_get, 3232 int, int, unit, 0, 0, 3233 int, int, port, 0, 0, 3234 int*, int, enable, 1, 0, 3235 portmod_rsvd4_tx_agnostic_config_t*, portmod_rsvd4_tx_agnostic_config_t, config_info, 1, 0); 3236 3237 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 3238 portmod_rsvd4_port_tx_agnostic_config_set, 3239 int, int, unit, 0, 0, 3240 int, int, port, 0, 0, 3241 int, int, enable, 0, 0, 3242 portmod_rsvd4_tx_agnostic_config_t*, portmod_rsvd4_tx_agnostic_config_t, config_info, 1, 0); 3243 3244 #endif /* CPRIMOD_SUPPORT */ 3245 #ifdef CPRIMOD_SUPPORT 3246 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3247 portmod_cpri_port_frame_config_set, 3248 int, int, unit, 0, 0, 3249 int, int, port, 0, 0, 3250 portmod_cpri_port_frame_config_t*, portmod_cpri_port_frame_config_t, config, 1, 0); 3251 3252 #endif /* CPRIMOD_SUPPORT */ 3253 #ifdef CPRIMOD_SUPPORT 3254 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3255 portmod_cpri_port_compression_saturation_config_get, 3256 int, int, unit, 0, 0, 3257 int, int, port, 0, 0, 3258 uint32*, uint32, threshold_value, 1, 0); 3259 3260 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3261 portmod_cpri_port_compression_saturation_config_set, 3262 int, int, unit, 0, 0, 3263 int, int, port, 0, 0, 3264 uint32, uint32, threshold_value, 0, 0); 3265 3266 #endif /* CPRIMOD_SUPPORT */ 3267 #ifdef CPRIMOD_SUPPORT 3268 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3269 portmod_cpri_port_decompression_saturation_config_get, 3270 int, int, unit, 0, 0, 3271 int, int, port, 0, 0, 3272 uint32*, uint32, sat_value, 1, 0); 3273 3274 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 3275 portmod_cpri_port_decompression_saturation_config_set, 3276 int, int, unit, 0, 0, 3277 int, int, port, 0, 0, 3278 uint32, uint32, sat_value, 0, 0); 3279 3280 #endif /* CPRIMOD_SUPPORT */ 3281 3282 /* Functions and Macros mapping */ 3283 static cint_function_t __cint_functions[] = 3284 { 3285 CINT_FWRAPPER_ENTRY(portmod_port_speed_ability_local_get), 3286 CINT_FWRAPPER_ENTRY(portmod_create), 3287 CINT_FWRAPPER_ENTRY(portmod_destroy), 3288 CINT_FWRAPPER_ENTRY(portmod_port_macro_add), 3289 CINT_FWRAPPER_ENTRY(portmod_port_add), 3290 CINT_FWRAPPER_ENTRY(portmod_port_remove), 3291 CINT_FWRAPPER_ENTRY(portmod_port_first_phy_get), 3292 CINT_FWRAPPER_ENTRY(portmod_port_phys_get), 3293 CINT_FWRAPPER_ENTRY(portmod_port_is_valid), 3294 CINT_FWRAPPER_ENTRY(portmod_port_pm_type_get), 3295 CINT_FWRAPPER_ENTRY(portmod_port_enable_get), 3296 CINT_FWRAPPER_ENTRY(portmod_port_enable_set), 3297 CINT_FWRAPPER_ENTRY(portmod_port_cdr_lock_get), 3298 CINT_FWRAPPER_ENTRY(portmod_port_interface_config_get), 3299 CINT_FWRAPPER_ENTRY(portmod_port_interface_config_set), 3300 CINT_FWRAPPER_ENTRY(portmod_port_default_interface_get), 3301 CINT_FWRAPPER_ENTRY(portmod_port_interface_check), 3302 CINT_FWRAPPER_ENTRY(portmod_port_encoding_get), 3303 CINT_FWRAPPER_ENTRY(portmod_port_encoding_set), 3304 CINT_FWRAPPER_ENTRY(portmod_port_cl72_get), 3305 CINT_FWRAPPER_ENTRY(portmod_port_cl72_set), 3306 CINT_FWRAPPER_ENTRY(portmod_port_cl72_status_get), 3307 CINT_FWRAPPER_ENTRY(portmod_port_loopback_get), 3308 CINT_FWRAPPER_ENTRY(portmod_port_loopback_set), 3309 CINT_FWRAPPER_ENTRY(portmod_port_pass_through_get), 3310 CINT_FWRAPPER_ENTRY(portmod_port_pass_through_set), 3311 CINT_FWRAPPER_ENTRY(portmod_port_pass_through_calibrate), 3312 CINT_FWRAPPER_ENTRY(portmod_port_pass_through_fec_enable_get), 3313 CINT_FWRAPPER_ENTRY(portmod_port_pass_through_fec_enable_set), 3314 CINT_FWRAPPER_ENTRY(portmod_port_rx_mac_enable_get), 3315 CINT_FWRAPPER_ENTRY(portmod_port_rx_mac_enable_set), 3316 CINT_FWRAPPER_ENTRY(portmod_port_tx_mac_enable_get), 3317 CINT_FWRAPPER_ENTRY(portmod_port_tx_mac_enable_set), 3318 CINT_FWRAPPER_ENTRY(portmod_port_ability_local_get), 3319 CINT_FWRAPPER_ENTRY(portmod_port_autoneg_get), 3320 CINT_FWRAPPER_ENTRY(portmod_port_autoneg_set), 3321 CINT_FWRAPPER_ENTRY(portmod_port_autoneg_status_get), 3322 CINT_FWRAPPER_ENTRY(portmod_port_link_get), 3323 CINT_FWRAPPER_ENTRY(portmod_port_link_latch_down_get), 3324 CINT_FWRAPPER_ENTRY(portmod_port_phy_link_up_event), 3325 CINT_FWRAPPER_ENTRY(portmod_port_phy_link_down_event), 3326 CINT_FWRAPPER_ENTRY(portmod_port_prbs_config_get), 3327 CINT_FWRAPPER_ENTRY(portmod_port_prbs_config_set), 3328 CINT_FWRAPPER_ENTRY(portmod_port_prbs_enable_get), 3329 CINT_FWRAPPER_ENTRY(portmod_port_prbs_enable_set), 3330 CINT_FWRAPPER_ENTRY(portmod_port_prbs_status_get), 3331 CINT_FWRAPPER_ENTRY(portmod_port_nof_lanes_get), 3332 CINT_FWRAPPER_ENTRY(portmod_port_ilkn_nof_segments_get), 3333 CINT_FWRAPPER_ENTRY(portmod_port_ilkn_nof_segments_set), 3334 CINT_FWRAPPER_ENTRY(portmod_ilkn_retranstmit_config_get), 3335 CINT_FWRAPPER_ENTRY(portmod_ilkn_retranstmit_config_set), 3336 CINT_FWRAPPER_ENTRY(portmod_port_lanes_assign), 3337 CINT_FWRAPPER_ENTRY(portmod_port_lanes_retrieve), 3338 CINT_FWRAPPER_ENTRY(portmod_port_firmware_mode_get), 3339 CINT_FWRAPPER_ENTRY(portmod_port_firmware_mode_set), 3340 CINT_FWRAPPER_ENTRY(portmod_port_runt_threshold_get), 3341 CINT_FWRAPPER_ENTRY(portmod_port_runt_threshold_set), 3342 CINT_FWRAPPER_ENTRY(portmod_port_max_packet_size_get), 3343 CINT_FWRAPPER_ENTRY(portmod_port_max_packet_size_set), 3344 CINT_FWRAPPER_ENTRY(portmod_port_pad_size_get), 3345 CINT_FWRAPPER_ENTRY(portmod_port_pad_size_set), 3346 CINT_FWRAPPER_ENTRY(portmod_port_tx_mac_sa_get), 3347 CINT_FWRAPPER_ENTRY(portmod_port_tx_mac_sa_set), 3348 CINT_FWRAPPER_ENTRY(portmod_port_rx_mac_sa_get), 3349 CINT_FWRAPPER_ENTRY(portmod_port_rx_mac_sa_set), 3350 CINT_FWRAPPER_ENTRY(portmod_port_tx_average_ipg_get), 3351 CINT_FWRAPPER_ENTRY(portmod_port_tx_average_ipg_set), 3352 CINT_FWRAPPER_ENTRY(portmod_port_tx_preamble_length_get), 3353 CINT_FWRAPPER_ENTRY(portmod_port_tx_preamble_length_set), 3354 CINT_FWRAPPER_ENTRY(portmod_port_local_fault_control_get), 3355 CINT_FWRAPPER_ENTRY(portmod_port_local_fault_control_set), 3356 CINT_FWRAPPER_ENTRY(portmod_port_remote_fault_control_get), 3357 CINT_FWRAPPER_ENTRY(portmod_port_remote_fault_control_set), 3358 CINT_FWRAPPER_ENTRY(portmod_port_local_fault_status_get), 3359 CINT_FWRAPPER_ENTRY(portmod_port_remote_fault_status_get), 3360 CINT_FWRAPPER_ENTRY(portmod_port_local_fault_status_clear), 3361 CINT_FWRAPPER_ENTRY(portmod_port_remote_fault_status_clear), 3362 CINT_FWRAPPER_ENTRY(portmod_port_pause_control_get), 3363 CINT_FWRAPPER_ENTRY(portmod_port_pause_control_set), 3364 CINT_FWRAPPER_ENTRY(portmod_port_pfc_control_get), 3365 CINT_FWRAPPER_ENTRY(portmod_port_pfc_control_set), 3366 CINT_FWRAPPER_ENTRY(portmod_port_llfc_control_get), 3367 CINT_FWRAPPER_ENTRY(portmod_port_llfc_control_set), 3368 CINT_FWRAPPER_ENTRY(portmod_port_update), 3369 CINT_FWRAPPER_ENTRY(portmod_port_core_access_get), 3370 CINT_FWRAPPER_ENTRY(portmod_port_phy_lane_access_get), 3371 CINT_FWRAPPER_ENTRY(portmod_pm_phy_lane_access_get), 3372 CINT_FWRAPPER_ENTRY(portmod_pm_diag_info_get), 3373 CINT_FWRAPPER_ENTRY(portmod_port_diag_info_get), 3374 CINT_FWRAPPER_ENTRY(portmod_port_duplex_get), 3375 CINT_FWRAPPER_ENTRY(portmod_port_duplex_set), 3376 CINT_FWRAPPER_ENTRY(portmod_port_phy_reg_read), 3377 CINT_FWRAPPER_ENTRY(portmod_port_phy_reg_write), 3378 CINT_FWRAPPER_ENTRY(portmod_port_reset_get), 3379 CINT_FWRAPPER_ENTRY(portmod_port_reset_set), 3380 CINT_FWRAPPER_ENTRY(portmod_port_adv_remote_get), 3381 CINT_FWRAPPER_ENTRY(portmod_port_drv_name), 3382 CINT_FWRAPPER_ENTRY(portmod_port_drv_name_get), 3383 CINT_FWRAPPER_ENTRY(portmod_port_fec_enable_get), 3384 CINT_FWRAPPER_ENTRY(portmod_port_fec_enable_set), 3385 CINT_FWRAPPER_ENTRY(portmod_port_ability_advert_get), 3386 CINT_FWRAPPER_ENTRY(portmod_port_ability_advert_set), 3387 CINT_FWRAPPER_ENTRY(portmod_port_ability_remote_get), 3388 CINT_FWRAPPER_ENTRY(portmod_port_frame_spacing_stretch_get), 3389 CINT_FWRAPPER_ENTRY(portmod_port_frame_spacing_stretch_set), 3390 CINT_FWRAPPER_ENTRY(portmod_port_diag_fifo_status_get), 3391 CINT_FWRAPPER_ENTRY(portmod_port_rx_control_get), 3392 CINT_FWRAPPER_ENTRY(portmod_port_rx_control_set), 3393 CINT_FWRAPPER_ENTRY(portmod_port_pfc_config_get), 3394 CINT_FWRAPPER_ENTRY(portmod_port_pfc_config_set), 3395 CINT_FWRAPPER_ENTRY(portmod_port_eee_get), 3396 CINT_FWRAPPER_ENTRY(portmod_port_eee_set), 3397 CINT_FWRAPPER_ENTRY(portmod_port_eee_clock_get), 3398 CINT_FWRAPPER_ENTRY(portmod_port_eee_clock_set), 3399 CINT_FWRAPPER_ENTRY(portmod_port_vlan_tag_get), 3400 CINT_FWRAPPER_ENTRY(portmod_port_vlan_tag_set), 3401 CINT_FWRAPPER_ENTRY(portmod_port_to_phyaddr), 3402 CINT_FWRAPPER_ENTRY(portmod_port_to_phyaddr_int), 3403 CINT_FWRAPPER_ENTRY(portmod_port_modid_set), 3404 CINT_FWRAPPER_ENTRY(portmod_port_led_chain_config), 3405 CINT_FWRAPPER_ENTRY(portmod_port_clear_rx_lss_status_get), 3406 CINT_FWRAPPER_ENTRY(portmod_port_clear_rx_lss_status_set), 3407 CINT_FWRAPPER_ENTRY(portmod_xphy_lane_attach), 3408 CINT_FWRAPPER_ENTRY(portmod_xphy_lane_detach), 3409 CINT_FWRAPPER_ENTRY(portmod_xphy_add), 3410 CINT_FWRAPPER_ENTRY(portmod_xphy_delete), 3411 CINT_FWRAPPER_ENTRY(portmod_xphy_wb_db_restore), 3412 CINT_FWRAPPER_ENTRY(portmod_ext_phy_lane_attach), 3413 CINT_FWRAPPER_ENTRY(portmod_ext_phy_lane_detach), 3414 CINT_FWRAPPER_ENTRY(portmod_port_lag_failover_status_toggle), 3415 CINT_FWRAPPER_ENTRY(portmod_port_lag_failover_loopback_get), 3416 CINT_FWRAPPER_ENTRY(portmod_port_lag_failover_loopback_set), 3417 CINT_FWRAPPER_ENTRY(portmod_port_mode_get), 3418 CINT_FWRAPPER_ENTRY(portmod_port_mode_set), 3419 CINT_FWRAPPER_ENTRY(portmod_port_encap_get), 3420 CINT_FWRAPPER_ENTRY(portmod_port_encap_set), 3421 CINT_FWRAPPER_ENTRY(portmod_port_higig_mode_get), 3422 CINT_FWRAPPER_ENTRY(portmod_port_higig_mode_set), 3423 CINT_FWRAPPER_ENTRY(portmod_port_higig2_mode_get), 3424 CINT_FWRAPPER_ENTRY(portmod_port_higig2_mode_set), 3425 CINT_FWRAPPER_ENTRY(portmod_port_config_port_type_get), 3426 CINT_FWRAPPER_ENTRY(portmod_port_config_port_type_set), 3427 CINT_FWRAPPER_ENTRY(portmod_port_trunk_hwfailover_config_get), 3428 CINT_FWRAPPER_ENTRY(portmod_port_trunk_hwfailover_config_set), 3429 CINT_FWRAPPER_ENTRY(portmod_port_trunk_hwfailover_status_get), 3430 CINT_FWRAPPER_ENTRY(portmod_port_diag_ctrl), 3431 CINT_FWRAPPER_ENTRY(portmod_port_ref_clk_get), 3432 CINT_FWRAPPER_ENTRY(portmod_port_lag_failover_disable), 3433 CINT_FWRAPPER_ENTRY(portmod_port_lag_remove_failover_lpbk_get), 3434 CINT_FWRAPPER_ENTRY(portmod_port_lag_remove_failover_lpbk_set), 3435 CINT_FWRAPPER_ENTRY(portmod_port_cntmaxsize_get), 3436 CINT_FWRAPPER_ENTRY(portmod_port_cntmaxsize_set), 3437 CINT_FWRAPPER_ENTRY(portmod_port_multi_get), 3438 CINT_FWRAPPER_ENTRY(portmod_port_drain_cell_get), 3439 CINT_FWRAPPER_ENTRY(portmod_port_drain_cell_stop), 3440 CINT_FWRAPPER_ENTRY(portmod_port_drain_cell_start), 3441 CINT_FWRAPPER_ENTRY(portmod_port_drain_cells_rx_enable), 3442 CINT_FWRAPPER_ENTRY(portmod_port_egress_queue_drain_rx_en), 3443 CINT_FWRAPPER_ENTRY(portmod_port_mac_ctrl_set), 3444 CINT_FWRAPPER_ENTRY(portmod_port_txfifo_cell_cnt_get), 3445 CINT_FWRAPPER_ENTRY(portmod_port_egress_queue_drain_get), 3446 CINT_FWRAPPER_ENTRY(portmod_port_mac_reset_get), 3447 CINT_FWRAPPER_ENTRY(portmod_port_mac_reset_set), 3448 CINT_FWRAPPER_ENTRY(portmod_port_soft_reset_toggle), 3449 CINT_FWRAPPER_ENTRY(portmod_port_mac_reset_check), 3450 CINT_FWRAPPER_ENTRY(portmod_port_core_num_get), 3451 CINT_FWRAPPER_ENTRY(portmod_port_e2ecc_hdr_get), 3452 CINT_FWRAPPER_ENTRY(portmod_port_e2ecc_hdr_set), 3453 CINT_FWRAPPER_ENTRY(portmod_port_e2e_enable_get), 3454 CINT_FWRAPPER_ENTRY(portmod_port_e2e_enable_set), 3455 CINT_FWRAPPER_ENTRY(portmod_port_fallback_lane_get), 3456 CINT_FWRAPPER_ENTRY(portmod_port_speed_get), 3457 CINT_FWRAPPER_ENTRY(portmod_port_tsc_refclock_get), 3458 CINT_FWRAPPER_ENTRY(portmod_port_tsc_refclock_set), 3459 CINT_FWRAPPER_ENTRY(portmod_port_discard_set), 3460 CINT_FWRAPPER_ENTRY(portmod_port_soft_reset_set), 3461 CINT_FWRAPPER_ENTRY(portmod_port_tx_down), 3462 CINT_FWRAPPER_ENTRY(portmod_port_logical_lane_order_get), 3463 CINT_FWRAPPER_ENTRY(portmod_port_logical_lane_order_set), 3464 CINT_FWRAPPER_ENTRY(portmod_port_pgw_reconfig), 3465 CINT_FWRAPPER_ENTRY(portmod_port_notify), 3466 CINT_FWRAPPER_ENTRY(portmod_port_control_phy_timesync_get), 3467 CINT_FWRAPPER_ENTRY(portmod_port_control_phy_timesync_set), 3468 CINT_FWRAPPER_ENTRY(portmod_port_timesync_config_get), 3469 CINT_FWRAPPER_ENTRY(portmod_port_timesync_config_set), 3470 CINT_FWRAPPER_ENTRY(portmod_port_timesync_enable_get), 3471 CINT_FWRAPPER_ENTRY(portmod_port_timesync_enable_set), 3472 CINT_FWRAPPER_ENTRY(portmod_port_timesync_nco_addend_get), 3473 CINT_FWRAPPER_ENTRY(portmod_port_timesync_nco_addend_set), 3474 CINT_FWRAPPER_ENTRY(portmod_port_timesync_framesync_mode_get), 3475 CINT_FWRAPPER_ENTRY(portmod_port_timesync_framesync_mode_set), 3476 CINT_FWRAPPER_ENTRY(portmod_port_timesync_local_time_get), 3477 CINT_FWRAPPER_ENTRY(portmod_port_timesync_local_time_set), 3478 CINT_FWRAPPER_ENTRY(portmod_port_timesync_load_ctrl_get), 3479 CINT_FWRAPPER_ENTRY(portmod_port_timesync_load_ctrl_set), 3480 CINT_FWRAPPER_ENTRY(portmod_port_timesync_tx_timestamp_offset_get), 3481 CINT_FWRAPPER_ENTRY(portmod_port_timesync_tx_timestamp_offset_set), 3482 CINT_FWRAPPER_ENTRY(portmod_port_timesync_rx_timestamp_offset_get), 3483 CINT_FWRAPPER_ENTRY(portmod_port_timesync_rx_timestamp_offset_set), 3484 CINT_FWRAPPER_ENTRY(portmod_port_timestamp_adjust_get), 3485 CINT_FWRAPPER_ENTRY(portmod_port_timestamp_adjust_set), 3486 CINT_FWRAPPER_ENTRY(portmod_port_phy_intr_enable_get), 3487 CINT_FWRAPPER_ENTRY(portmod_port_phy_intr_enable_set), 3488 CINT_FWRAPPER_ENTRY(portmod_port_phy_intr_status_get), 3489 CINT_FWRAPPER_ENTRY(portmod_port_phy_intr_status_clear), 3490 CINT_FWRAPPER_ENTRY(portmod_port_phy_timesync_do_sync), 3491 CINT_FWRAPPER_ENTRY(portmod_port_timesync_capture_timestamp_get), 3492 CINT_FWRAPPER_ENTRY(portmod_port_timesync_heartbeat_timestamp_get), 3493 CINT_FWRAPPER_ENTRY(portmod_port_edc_config_get), 3494 CINT_FWRAPPER_ENTRY(portmod_port_edc_config_set), 3495 CINT_FWRAPPER_ENTRY(portmod_port_interrupt_enable_get), 3496 CINT_FWRAPPER_ENTRY(portmod_port_interrupt_enable_set), 3497 CINT_FWRAPPER_ENTRY(portmod_port_interrupt_get), 3498 CINT_FWRAPPER_ENTRY(portmod_port_interrupts_get), 3499 CINT_FWRAPPER_ENTRY(portmod_port_stats_read), 3500 CINT_FWRAPPER_ENTRY(portmod_port_stats_clear), 3501 CINT_FWRAPPER_ENTRY(portmod_port_check_legacy_phy), 3502 CINT_FWRAPPER_ENTRY(portmod_port_failover_mode_get), 3503 CINT_FWRAPPER_ENTRY(portmod_port_failover_mode_set), 3504 CINT_FWRAPPER_ENTRY(portmod_port_warmboot_db_restore), 3505 CINT_FWRAPPER_ENTRY(portmod_port_flow_control_set), 3506 CINT_FWRAPPER_ENTRY(portmod_port_update_dynamic_state), 3507 CINT_FWRAPPER_ENTRY(portmod_port_phy_op_mode_get), 3508 CINT_FWRAPPER_ENTRY(portmod_port_lane_map_get), 3509 CINT_FWRAPPER_ENTRY(portmod_port_lane_map_set), 3510 CINT_FWRAPPER_ENTRY(portmod_port_polarity_get), 3511 CINT_FWRAPPER_ENTRY(portmod_port_polarity_set), 3512 CINT_FWRAPPER_ENTRY(portmod_port_medium_config_get), 3513 CINT_FWRAPPER_ENTRY(portmod_port_medium_config_set), 3514 CINT_FWRAPPER_ENTRY(portmod_port_medium_get), 3515 CINT_FWRAPPER_ENTRY(portmod_pm_port_pll_div_get), 3516 CINT_FWRAPPER_ENTRY(portmod_port_master_get), 3517 CINT_FWRAPPER_ENTRY(portmod_port_master_set), 3518 CINT_FWRAPPER_ENTRY(portmod_preemption_control_get), 3519 CINT_FWRAPPER_ENTRY(portmod_preemption_control_set), 3520 CINT_FWRAPPER_ENTRY(portmod_preemption_tx_status_get), 3521 CINT_FWRAPPER_ENTRY(portmod_preemption_verify_status_get), 3522 CINT_FWRAPPER_ENTRY(portmod_preemption_force_rx_eop_mode_get), 3523 CINT_FWRAPPER_ENTRY(portmod_preemption_force_rx_eop_mode_set), 3524 CINT_FWRAPPER_ENTRY(portmod_preemption_rx_timeout_get), 3525 CINT_FWRAPPER_ENTRY(portmod_preemption_rx_timeout_set), 3526 CINT_FWRAPPER_ENTRY(portmod_port_timesync_tx_info_get), 3527 CINT_FWRAPPER_ENTRY(portmod_core_add), 3528 CINT_FWRAPPER_ENTRY(portmod_pm_serdes_core_init), 3529 CINT_FWRAPPER_ENTRY(portmod_pm_is_initialized), 3530 CINT_FWRAPPER_ENTRY(portmod_port_speed_config_validate), 3531 CINT_FWRAPPER_ENTRY(portmod_pm_enable), 3532 CINT_FWRAPPER_ENTRY(portmod_phy_pm_id_get), 3533 CINT_FWRAPPER_ENTRY(portmod_pm_logical_pbmp_get), 3534 CINT_FWRAPPER_ENTRY(portmod_pm_vco_reconfig), 3535 CINT_FWRAPPER_ENTRY(portmod_port_speed_config_get), 3536 CINT_FWRAPPER_ENTRY(portmod_port_speed_config_set), 3537 CINT_FWRAPPER_ENTRY(portmod_port_credits_enable_set), 3538 #ifdef CPRIMOD_SUPPORT 3539 CINT_FWRAPPER_ENTRY(portmod_cpri_port_stage_activate), 3540 #endif /* CPRIMOD_SUPPORT */ 3541 #ifdef CPRIMOD_SUPPORT 3542 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_tx_fsm_state_set), 3543 #endif /* CPRIMOD_SUPPORT */ 3544 #ifdef CPRIMOD_SUPPORT 3545 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_tx_override_set), 3546 #endif /* CPRIMOD_SUPPORT */ 3547 #ifdef CPRIMOD_SUPPORT 3548 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_rx_override_set), 3549 #endif /* CPRIMOD_SUPPORT */ 3550 #ifdef CPRIMOD_SUPPORT 3551 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_axc_frame_add), 3552 #endif /* CPRIMOD_SUPPORT */ 3553 #ifdef CPRIMOD_SUPPORT 3554 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_frame_optional_config_get), 3555 #endif /* CPRIMOD_SUPPORT */ 3556 #ifdef CPRIMOD_SUPPORT 3557 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_frame_optional_config_set), 3558 #endif /* CPRIMOD_SUPPORT */ 3559 #ifdef CPRIMOD_SUPPORT 3560 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_optional_config_get), 3561 #endif /* CPRIMOD_SUPPORT */ 3562 #ifdef CPRIMOD_SUPPORT 3563 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_optional_config_set), 3564 #endif /* CPRIMOD_SUPPORT */ 3565 #ifdef CPRIMOD_SUPPORT 3566 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_rx_frame_optional_config_get), 3567 #endif /* CPRIMOD_SUPPORT */ 3568 #ifdef CPRIMOD_SUPPORT 3569 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_rx_frame_optional_config_set), 3570 #endif /* CPRIMOD_SUPPORT */ 3571 #ifdef CPRIMOD_SUPPORT 3572 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_tx_frame_optional_config_get), 3573 #endif /* CPRIMOD_SUPPORT */ 3574 #ifdef CPRIMOD_SUPPORT 3575 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_tx_frame_optional_config_set), 3576 #endif /* CPRIMOD_SUPPORT */ 3577 #ifdef CPRIMOD_SUPPORT 3578 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_rx_speed_get), 3579 #endif /* CPRIMOD_SUPPORT */ 3580 #ifdef CPRIMOD_SUPPORT 3581 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_rx_speed_set), 3582 #endif /* CPRIMOD_SUPPORT */ 3583 #ifdef CPRIMOD_SUPPORT 3584 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_tx_speed_get), 3585 #endif /* CPRIMOD_SUPPORT */ 3586 #ifdef CPRIMOD_SUPPORT 3587 CINT_FWRAPPER_ENTRY(portmod_port_rsvd4_tx_speed_set), 3588 #endif /* CPRIMOD_SUPPORT */ 3589 #ifdef CPRIMOD_SUPPORT 3590 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_axc_frame_delete), 3591 #endif /* CPRIMOD_SUPPORT */ 3592 #ifdef CPRIMOD_SUPPORT 3593 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_axc_frame_get), 3594 #endif /* CPRIMOD_SUPPORT */ 3595 #ifdef CPRIMOD_SUPPORT 3596 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_rx_fsm_state_set), 3597 #endif /* CPRIMOD_SUPPORT */ 3598 #ifdef CPRIMOD_SUPPORT 3599 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_axc_frame_add), 3600 #endif /* CPRIMOD_SUPPORT */ 3601 #ifdef CPRIMOD_SUPPORT 3602 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_axc_frame_delete), 3603 #endif /* CPRIMOD_SUPPORT */ 3604 #ifdef CPRIMOD_SUPPORT 3605 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_axc_frame_get), 3606 #endif /* CPRIMOD_SUPPORT */ 3607 #ifdef CPRIMOD_SUPPORT 3608 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_get), 3609 #endif /* CPRIMOD_SUPPORT */ 3610 #ifdef CPRIMOD_SUPPORT 3611 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_set), 3612 #endif /* CPRIMOD_SUPPORT */ 3613 #ifdef CPRIMOD_SUPPORT 3614 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_roe_ordering_info_get), 3615 #endif /* CPRIMOD_SUPPORT */ 3616 #ifdef CPRIMOD_SUPPORT 3617 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_roe_ordering_info_set), 3618 #endif /* CPRIMOD_SUPPORT */ 3619 #ifdef CPRIMOD_SUPPORT 3620 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_roe_ordering_sequence_offset_get), 3621 #endif /* CPRIMOD_SUPPORT */ 3622 #ifdef CPRIMOD_SUPPORT 3623 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_roe_ordering_sequence_offset_set), 3624 #endif /* CPRIMOD_SUPPORT */ 3625 #ifdef CPRIMOD_SUPPORT 3626 CINT_FWRAPPER_ENTRY(portmod_cpri_port_roe_encap_macda_entry_get), 3627 #endif /* CPRIMOD_SUPPORT */ 3628 #ifdef CPRIMOD_SUPPORT 3629 CINT_FWRAPPER_ENTRY(portmod_cpri_port_roe_encap_macda_entry_set), 3630 #endif /* CPRIMOD_SUPPORT */ 3631 #ifdef CPRIMOD_SUPPORT 3632 CINT_FWRAPPER_ENTRY(portmod_cpri_port_roe_encap_macsa_entry_get), 3633 #endif /* CPRIMOD_SUPPORT */ 3634 #ifdef CPRIMOD_SUPPORT 3635 CINT_FWRAPPER_ENTRY(portmod_cpri_port_roe_encap_macsa_entry_set), 3636 #endif /* CPRIMOD_SUPPORT */ 3637 #ifdef CPRIMOD_SUPPORT 3638 CINT_FWRAPPER_ENTRY(portmod_cpri_port_roe_encap_vlan_entry_get), 3639 #endif /* CPRIMOD_SUPPORT */ 3640 #ifdef CPRIMOD_SUPPORT 3641 CINT_FWRAPPER_ENTRY(portmod_cpri_port_roe_encap_vlan_entry_set), 3642 #endif /* CPRIMOD_SUPPORT */ 3643 #ifdef CPRIMOD_SUPPORT 3644 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_ethertype_config_get), 3645 #endif /* CPRIMOD_SUPPORT */ 3646 #ifdef CPRIMOD_SUPPORT 3647 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_ethertype_config_set), 3648 #endif /* CPRIMOD_SUPPORT */ 3649 #ifdef CPRIMOD_SUPPORT 3650 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_ethertype_config_get), 3651 #endif /* CPRIMOD_SUPPORT */ 3652 #ifdef CPRIMOD_SUPPORT 3653 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_ethertype_config_set), 3654 #endif /* CPRIMOD_SUPPORT */ 3655 #ifdef CPRIMOD_SUPPORT 3656 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_flow_config_get), 3657 #endif /* CPRIMOD_SUPPORT */ 3658 #ifdef CPRIMOD_SUPPORT 3659 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_flow_config_set), 3660 #endif /* CPRIMOD_SUPPORT */ 3661 #ifdef CPRIMOD_SUPPORT 3662 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_queue_to_ordering_info_index_get), 3663 #endif /* CPRIMOD_SUPPORT */ 3664 #ifdef CPRIMOD_SUPPORT 3665 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_queue_to_ordering_info_index_set), 3666 #endif /* CPRIMOD_SUPPORT */ 3667 #ifdef CPRIMOD_SUPPORT 3668 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_flow_to_queue_mapping_get), 3669 #endif /* CPRIMOD_SUPPORT */ 3670 #ifdef CPRIMOD_SUPPORT 3671 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_flow_to_queue_mapping_set), 3672 #endif /* CPRIMOD_SUPPORT */ 3673 #ifdef CPRIMOD_SUPPORT 3674 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_roe_ordering_info_get), 3675 #endif /* CPRIMOD_SUPPORT */ 3676 #ifdef CPRIMOD_SUPPORT 3677 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_roe_ordering_info_set), 3678 #endif /* CPRIMOD_SUPPORT */ 3679 #ifdef CPRIMOD_SUPPORT 3680 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_roe_ordering_sequence_offset_get), 3681 #endif /* CPRIMOD_SUPPORT */ 3682 #ifdef CPRIMOD_SUPPORT 3683 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_roe_ordering_sequence_offset_set), 3684 #endif /* CPRIMOD_SUPPORT */ 3685 #ifdef CPRIMOD_SUPPORT 3686 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_tgen_config_get), 3687 #endif /* CPRIMOD_SUPPORT */ 3688 #ifdef CPRIMOD_SUPPORT 3689 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_tgen_config_set), 3690 #endif /* CPRIMOD_SUPPORT */ 3691 #ifdef CPRIMOD_SUPPORT 3692 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_tgen_enable), 3693 #endif /* CPRIMOD_SUPPORT */ 3694 #ifdef CPRIMOD_SUPPORT 3695 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_tgen_ts_offset_get), 3696 #endif /* CPRIMOD_SUPPORT */ 3697 #ifdef CPRIMOD_SUPPORT 3698 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_tgen_ts_offset_set), 3699 #endif /* CPRIMOD_SUPPORT */ 3700 #ifdef CPRIMOD_SUPPORT 3701 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_next_hfn_get), 3702 #endif /* CPRIMOD_SUPPORT */ 3703 #ifdef CPRIMOD_SUPPORT 3704 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_frame_next_bfn_get), 3705 #endif /* CPRIMOD_SUPPORT */ 3706 #ifdef CPRIMOD_SUPPORT 3707 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_rx_flow_add), 3708 #endif /* CPRIMOD_SUPPORT */ 3709 #ifdef CPRIMOD_SUPPORT 3710 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_rx_flow_delete), 3711 #endif /* CPRIMOD_SUPPORT */ 3712 #ifdef CPRIMOD_SUPPORT 3713 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_tx_flow_add), 3714 #endif /* CPRIMOD_SUPPORT */ 3715 #ifdef CPRIMOD_SUPPORT 3716 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_tx_flow_delete), 3717 #endif /* CPRIMOD_SUPPORT */ 3718 #ifdef CPRIMOD_SUPPORT 3719 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_dbm_entry_get), 3720 #endif /* CPRIMOD_SUPPORT */ 3721 #ifdef CPRIMOD_SUPPORT 3722 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_dbm_entry_set), 3723 #endif /* CPRIMOD_SUPPORT */ 3724 #ifdef CPRIMOD_SUPPORT 3725 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_secondary_dbm_entry_get), 3726 #endif /* CPRIMOD_SUPPORT */ 3727 #ifdef CPRIMOD_SUPPORT 3728 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_secondary_dbm_entry_set), 3729 #endif /* CPRIMOD_SUPPORT */ 3730 #ifdef CPRIMOD_SUPPORT 3731 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_modulo_rule_entry_get), 3732 #endif /* CPRIMOD_SUPPORT */ 3733 #ifdef CPRIMOD_SUPPORT 3734 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_modulo_rule_entry_set), 3735 #endif /* CPRIMOD_SUPPORT */ 3736 #ifdef CPRIMOD_SUPPORT 3737 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_dbm_position_entry_get), 3738 #endif /* CPRIMOD_SUPPORT */ 3739 #ifdef CPRIMOD_SUPPORT 3740 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_dbm_position_entry_set), 3741 #endif /* CPRIMOD_SUPPORT */ 3742 #ifdef CPRIMOD_SUPPORT 3743 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_rx_master_frame_sync_config_get), 3744 #endif /* CPRIMOD_SUPPORT */ 3745 #ifdef CPRIMOD_SUPPORT 3746 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rsvd4_rx_master_frame_sync_config_set), 3747 #endif /* CPRIMOD_SUPPORT */ 3748 CINT_FWRAPPER_ENTRY(portmod_pm_supported_vcos_get), 3749 CINT_FWRAPPER_ENTRY(portmod_port_vcos_get), 3750 CINT_FWRAPPER_ENTRY(portmod_port_mac_timestamp_enable_get), 3751 CINT_FWRAPPER_ENTRY(portmod_port_mac_timestamp_enable_set), 3752 #ifdef CPRIMOD_SUPPORT 3753 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_cw_sync_info_get), 3754 #endif /* CPRIMOD_SUPPORT */ 3755 #ifdef CPRIMOD_SUPPORT 3756 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_cw_l1_signal_info_get), 3757 #endif /* CPRIMOD_SUPPORT */ 3758 #ifdef CPRIMOD_SUPPORT 3759 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_cw_l1_signal_signal_protection_get), 3760 #endif /* CPRIMOD_SUPPORT */ 3761 #ifdef CPRIMOD_SUPPORT 3762 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_cw_l1_signal_signal_protection_set), 3763 #endif /* CPRIMOD_SUPPORT */ 3764 #ifdef CPRIMOD_SUPPORT 3765 CINT_FWRAPPER_ENTRY(portmod_cpri_port_cw_slow_hdlc_config_get), 3766 #endif /* CPRIMOD_SUPPORT */ 3767 #ifdef CPRIMOD_SUPPORT 3768 CINT_FWRAPPER_ENTRY(portmod_cpri_port_cw_slow_hdlc_config_set), 3769 #endif /* CPRIMOD_SUPPORT */ 3770 #ifdef CPRIMOD_SUPPORT 3771 CINT_FWRAPPER_ENTRY(portmod_cpri_port_cw_fast_eth_config_get), 3772 #endif /* CPRIMOD_SUPPORT */ 3773 #ifdef CPRIMOD_SUPPORT 3774 CINT_FWRAPPER_ENTRY(portmod_cpri_port_cw_fast_eth_config_set), 3775 #endif /* CPRIMOD_SUPPORT */ 3776 #ifdef CPRIMOD_SUPPORT 3777 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_vsd_config_get), 3778 #endif /* CPRIMOD_SUPPORT */ 3779 #ifdef CPRIMOD_SUPPORT 3780 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_vsd_config_set), 3781 #endif /* CPRIMOD_SUPPORT */ 3782 #ifdef CPRIMOD_SUPPORT 3783 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_config_get), 3784 #endif /* CPRIMOD_SUPPORT */ 3785 #ifdef CPRIMOD_SUPPORT 3786 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_config_set), 3787 #endif /* CPRIMOD_SUPPORT */ 3788 #ifdef CPRIMOD_SUPPORT 3789 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_vsd_flow_add), 3790 #endif /* CPRIMOD_SUPPORT */ 3791 #ifdef CPRIMOD_SUPPORT 3792 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_vsd_flow_get), 3793 #endif /* CPRIMOD_SUPPORT */ 3794 #ifdef CPRIMOD_SUPPORT 3795 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_vsd_flow_delete), 3796 #endif /* CPRIMOD_SUPPORT */ 3797 #ifdef CPRIMOD_SUPPORT 3798 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_flow_add), 3799 #endif /* CPRIMOD_SUPPORT */ 3800 #ifdef CPRIMOD_SUPPORT 3801 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_flow_delete), 3802 #endif /* CPRIMOD_SUPPORT */ 3803 #ifdef CPRIMOD_SUPPORT 3804 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_flow_get), 3805 #endif /* CPRIMOD_SUPPORT */ 3806 #ifdef CPRIMOD_SUPPORT 3807 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_queue_control_tag_to_flow_map_get), 3808 #endif /* CPRIMOD_SUPPORT */ 3809 #ifdef CPRIMOD_SUPPORT 3810 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_queue_control_tag_to_flow_map_set), 3811 #endif /* CPRIMOD_SUPPORT */ 3812 #ifdef CPRIMOD_SUPPORT 3813 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_vsd_raw_config_get), 3814 #endif /* CPRIMOD_SUPPORT */ 3815 #ifdef CPRIMOD_SUPPORT 3816 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_vsd_raw_config_set), 3817 #endif /* CPRIMOD_SUPPORT */ 3818 #ifdef CPRIMOD_SUPPORT 3819 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_raw_config_get), 3820 #endif /* CPRIMOD_SUPPORT */ 3821 #ifdef CPRIMOD_SUPPORT 3822 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_raw_config_set), 3823 #endif /* CPRIMOD_SUPPORT */ 3824 #ifdef CPRIMOD_SUPPORT 3825 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_raw_filter_get), 3826 #endif /* CPRIMOD_SUPPORT */ 3827 #ifdef CPRIMOD_SUPPORT 3828 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_vsd_raw_filter_set), 3829 #endif /* CPRIMOD_SUPPORT */ 3830 #ifdef CPRIMOD_SUPPORT 3831 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_brcm_rsvd5_config_get), 3832 #endif /* CPRIMOD_SUPPORT */ 3833 #ifdef CPRIMOD_SUPPORT 3834 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_brcm_rsvd5_config_set), 3835 #endif /* CPRIMOD_SUPPORT */ 3836 #ifdef CPRIMOD_SUPPORT 3837 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_brcm_rsvd5_config_get), 3838 #endif /* CPRIMOD_SUPPORT */ 3839 #ifdef CPRIMOD_SUPPORT 3840 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_brcm_rsvd5_config_set), 3841 #endif /* CPRIMOD_SUPPORT */ 3842 #ifdef CPRIMOD_SUPPORT 3843 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_gcw_config_get), 3844 #endif /* CPRIMOD_SUPPORT */ 3845 #ifdef CPRIMOD_SUPPORT 3846 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_gcw_config_set), 3847 #endif /* CPRIMOD_SUPPORT */ 3848 #ifdef CPRIMOD_SUPPORT 3849 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_gcw_config_get), 3850 #endif /* CPRIMOD_SUPPORT */ 3851 #ifdef CPRIMOD_SUPPORT 3852 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_gcw_config_set), 3853 #endif /* CPRIMOD_SUPPORT */ 3854 #ifdef CPRIMOD_SUPPORT 3855 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_gcw_filter_get), 3856 #endif /* CPRIMOD_SUPPORT */ 3857 #ifdef CPRIMOD_SUPPORT 3858 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_gcw_filter_set), 3859 #endif /* CPRIMOD_SUPPORT */ 3860 #ifdef CPRIMOD_SUPPORT 3861 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_cw_sync_info_get), 3862 #endif /* CPRIMOD_SUPPORT */ 3863 #ifdef CPRIMOD_SUPPORT 3864 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_cw_sync_info_set), 3865 #endif /* CPRIMOD_SUPPORT */ 3866 #ifdef CPRIMOD_SUPPORT 3867 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_cw_l1_config_set), 3868 #endif /* CPRIMOD_SUPPORT */ 3869 #ifdef CPRIMOD_SUPPORT 3870 CINT_FWRAPPER_ENTRY(portmod_rsvd4_rx_control_flow_add), 3871 #endif /* CPRIMOD_SUPPORT */ 3872 #ifdef CPRIMOD_SUPPORT 3873 CINT_FWRAPPER_ENTRY(portmod_rsvd4_rx_control_flow_delete), 3874 #endif /* CPRIMOD_SUPPORT */ 3875 #ifdef CPRIMOD_SUPPORT 3876 CINT_FWRAPPER_ENTRY(portmod_rsvd4_fast_eth_config_set), 3877 #endif /* CPRIMOD_SUPPORT */ 3878 #ifdef CPRIMOD_SUPPORT 3879 CINT_FWRAPPER_ENTRY(portmod_rsvd4_rx_sync_profile_entry_get), 3880 #endif /* CPRIMOD_SUPPORT */ 3881 #ifdef CPRIMOD_SUPPORT 3882 CINT_FWRAPPER_ENTRY(portmod_rsvd4_rx_sync_profile_entry_set), 3883 #endif /* CPRIMOD_SUPPORT */ 3884 CINT_FWRAPPER_ENTRY(portmod_rx_tag_config_set), 3885 CINT_FWRAPPER_ENTRY(portmod_rx_tag_gen_entry_add), 3886 CINT_FWRAPPER_ENTRY(portmod_rx_tag_gen_entry_delete), 3887 #ifdef CPRIMOD_SUPPORT 3888 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_flow_group_member_add), 3889 #endif /* CPRIMOD_SUPPORT */ 3890 #ifdef CPRIMOD_SUPPORT 3891 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_flow_group_member_delete), 3892 #endif /* CPRIMOD_SUPPORT */ 3893 #ifdef CPRIMOD_SUPPORT 3894 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_eth_message_config_set), 3895 #endif /* CPRIMOD_SUPPORT */ 3896 #ifdef CPRIMOD_SUPPORT 3897 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_single_raw_message_config_set), 3898 #endif /* CPRIMOD_SUPPORT */ 3899 #ifdef CPRIMOD_SUPPORT 3900 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_flow_config_get), 3901 #endif /* CPRIMOD_SUPPORT */ 3902 #ifdef CPRIMOD_SUPPORT 3903 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_flow_config_set), 3904 #endif /* CPRIMOD_SUPPORT */ 3905 #ifdef CPRIMOD_SUPPORT 3906 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_flow_header_index_get), 3907 #endif /* CPRIMOD_SUPPORT */ 3908 #ifdef CPRIMOD_SUPPORT 3909 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_flow_header_index_set), 3910 #endif /* CPRIMOD_SUPPORT */ 3911 #ifdef CPRIMOD_SUPPORT 3912 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_header_entry_get), 3913 #endif /* CPRIMOD_SUPPORT */ 3914 #ifdef CPRIMOD_SUPPORT 3915 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_control_header_entry_set), 3916 #endif /* CPRIMOD_SUPPORT */ 3917 #ifdef CPRIMOD_SUPPORT 3918 CINT_FWRAPPER_ENTRY(portmod_rsvd4_tx_single_tunnel_message_config_set), 3919 #endif /* CPRIMOD_SUPPORT */ 3920 CINT_FWRAPPER_ENTRY(portmod_port_txpi_override_get), 3921 CINT_FWRAPPER_ENTRY(portmod_port_txpi_override_set), 3922 CINT_FWRAPPER_ENTRY(portmod_port_txpi_sdm_data_get), 3923 CINT_FWRAPPER_ENTRY(portmod_pm_speed_config_validate), 3924 CINT_FWRAPPER_ENTRY(portmod_pm_vcos_get), 3925 CINT_FWRAPPER_ENTRY(portmod_port_autoneg_ability_advert_get), 3926 CINT_FWRAPPER_ENTRY(portmod_port_autoneg_ability_advert_set), 3927 CINT_FWRAPPER_ENTRY(portmod_port_autoneg_ability_remote_get), 3928 #ifdef CPRIMOD_SUPPORT 3929 CINT_FWRAPPER_ENTRY(portmod_cpri_port_interrupt_callback_register), 3930 #endif /* CPRIMOD_SUPPORT */ 3931 #ifdef CPRIMOD_SUPPORT 3932 CINT_FWRAPPER_ENTRY(portmod_cpri_port_interrupt_callback_unregister), 3933 #endif /* CPRIMOD_SUPPORT */ 3934 CINT_FWRAPPER_ENTRY(portmod_phy_pms_ids_get), 3935 CINT_FWRAPPER_ENTRY(portmod_port_pm_id_get), 3936 #ifdef CPRIMOD_SUPPORT 3937 CINT_FWRAPPER_ENTRY(portmod_cpri_port_interrupt_enable_set), 3938 #endif /* CPRIMOD_SUPPORT */ 3939 #ifdef CPRIMOD_SUPPORT 3940 CINT_FWRAPPER_ENTRY(portmod_cpri_port_interrupt_process), 3941 #endif /* CPRIMOD_SUPPORT */ 3942 #ifdef CPRIMOD_SUPPORT 3943 CINT_FWRAPPER_ENTRY(portmod_fast_clk_bit_time_period_get), 3944 #endif /* CPRIMOD_SUPPORT */ 3945 #ifdef CPRIMOD_SUPPORT 3946 CINT_FWRAPPER_ENTRY(portmod_fast_clk_bit_time_period_set), 3947 #endif /* CPRIMOD_SUPPORT */ 3948 #ifdef CPRIMOD_SUPPORT 3949 CINT_FWRAPPER_ENTRY(portmod_1588_bit_time_period_get), 3950 #endif /* CPRIMOD_SUPPORT */ 3951 #ifdef CPRIMOD_SUPPORT 3952 CINT_FWRAPPER_ENTRY(portmod_1588_bit_time_period_set), 3953 #endif /* CPRIMOD_SUPPORT */ 3954 #ifdef CPRIMOD_SUPPORT 3955 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_capture_config_get), 3956 #endif /* CPRIMOD_SUPPORT */ 3957 #ifdef CPRIMOD_SUPPORT 3958 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_capture_config_set), 3959 #endif /* CPRIMOD_SUPPORT */ 3960 #ifdef CPRIMOD_SUPPORT 3961 CINT_FWRAPPER_ENTRY(portmod_1588_captured_timestamp_get), 3962 #endif /* CPRIMOD_SUPPORT */ 3963 #ifdef CPRIMOD_SUPPORT 3964 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_adjust_get), 3965 #endif /* CPRIMOD_SUPPORT */ 3966 #ifdef CPRIMOD_SUPPORT 3967 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_adjust_set), 3968 #endif /* CPRIMOD_SUPPORT */ 3969 #ifdef CPRIMOD_SUPPORT 3970 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_fifo_config_get), 3971 #endif /* CPRIMOD_SUPPORT */ 3972 #ifdef CPRIMOD_SUPPORT 3973 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_fifo_config_set), 3974 #endif /* CPRIMOD_SUPPORT */ 3975 #ifdef CPRIMOD_SUPPORT 3976 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_cmic_config_get), 3977 #endif /* CPRIMOD_SUPPORT */ 3978 #ifdef CPRIMOD_SUPPORT 3979 CINT_FWRAPPER_ENTRY(portmod_1588_timestamp_cmic_config_set), 3980 #endif /* CPRIMOD_SUPPORT */ 3981 CINT_FWRAPPER_ENTRY(portmod_port_tx_get), 3982 CINT_FWRAPPER_ENTRY(portmod_port_tx_set), 3983 CINT_FWRAPPER_ENTRY(portmod_port_synce_clk_ctrl_get), 3984 CINT_FWRAPPER_ENTRY(portmod_port_synce_clk_ctrl_set), 3985 #ifdef CPRIMOD_SUPPORT 3986 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_agnostic_config_get), 3987 #endif /* CPRIMOD_SUPPORT */ 3988 #ifdef CPRIMOD_SUPPORT 3989 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_agnostic_config_set), 3990 #endif /* CPRIMOD_SUPPORT */ 3991 #ifdef CPRIMOD_SUPPORT 3992 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_agnostic_config_get), 3993 #endif /* CPRIMOD_SUPPORT */ 3994 #ifdef CPRIMOD_SUPPORT 3995 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_agnostic_config_set), 3996 #endif /* CPRIMOD_SUPPORT */ 3997 #ifdef CPRIMOD_SUPPORT 3998 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_presentation_time_config_get), 3999 #endif /* CPRIMOD_SUPPORT */ 4000 #ifdef CPRIMOD_SUPPORT 4001 CINT_FWRAPPER_ENTRY(portmod_cpri_port_encap_presentation_time_config_set), 4002 #endif /* CPRIMOD_SUPPORT */ 4003 #ifdef CPRIMOD_SUPPORT 4004 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_presentation_time_config_get), 4005 #endif /* CPRIMOD_SUPPORT */ 4006 #ifdef CPRIMOD_SUPPORT 4007 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_presentation_time_config_set), 4008 #endif /* CPRIMOD_SUPPORT */ 4009 #ifdef CPRIMOD_SUPPORT 4010 CINT_FWRAPPER_ENTRY(portmod_cpri_port_compression_lookup_table_get), 4011 #endif /* CPRIMOD_SUPPORT */ 4012 #ifdef CPRIMOD_SUPPORT 4013 CINT_FWRAPPER_ENTRY(portmod_cpri_port_compression_lookup_table_set), 4014 #endif /* CPRIMOD_SUPPORT */ 4015 #ifdef CPRIMOD_SUPPORT 4016 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decompression_lookup_table_get), 4017 #endif /* CPRIMOD_SUPPORT */ 4018 #ifdef CPRIMOD_SUPPORT 4019 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decompression_lookup_table_set), 4020 #endif /* CPRIMOD_SUPPORT */ 4021 #ifdef CPRIMOD_SUPPORT 4022 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_queue_flow_control_get), 4023 #endif /* CPRIMOD_SUPPORT */ 4024 #ifdef CPRIMOD_SUPPORT 4025 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decap_queue_flow_control_set), 4026 #endif /* CPRIMOD_SUPPORT */ 4027 #ifdef CPRIMOD_SUPPORT 4028 CINT_FWRAPPER_ENTRY(portmod_cpri_port_fec_enable_get), 4029 #endif /* CPRIMOD_SUPPORT */ 4030 #ifdef CPRIMOD_SUPPORT 4031 CINT_FWRAPPER_ENTRY(portmod_cpri_port_fec_enable_set), 4032 #endif /* CPRIMOD_SUPPORT */ 4033 #ifdef CPRIMOD_SUPPORT 4034 CINT_FWRAPPER_ENTRY(portmod_cpri_port_fec_timestamp_config_get), 4035 #endif /* CPRIMOD_SUPPORT */ 4036 #ifdef CPRIMOD_SUPPORT 4037 CINT_FWRAPPER_ENTRY(portmod_cpri_port_fec_timestamp_config_set), 4038 #endif /* CPRIMOD_SUPPORT */ 4039 #ifdef CPRIMOD_SUPPORT 4040 CINT_FWRAPPER_ENTRY(portmod_cpri_port_fec_aux_config_get), 4041 #endif /* CPRIMOD_SUPPORT */ 4042 #ifdef CPRIMOD_SUPPORT 4043 CINT_FWRAPPER_ENTRY(portmod_cpri_port_fec_aux_config_set), 4044 #endif /* CPRIMOD_SUPPORT */ 4045 #ifdef CPRIMOD_SUPPORT 4046 CINT_FWRAPPER_ENTRY(portmod_cpri_port_ecc_interrupt_enable_set), 4047 #endif /* CPRIMOD_SUPPORT */ 4048 #ifdef CPRIMOD_SUPPORT 4049 CINT_FWRAPPER_ENTRY(portmod_cpri_port_ecc_interrupt_status_get), 4050 #endif /* CPRIMOD_SUPPORT */ 4051 #ifdef CPRIMOD_SUPPORT 4052 CINT_FWRAPPER_ENTRY(portmod_cpri_init), 4053 #endif /* CPRIMOD_SUPPORT */ 4054 #ifdef CPRIMOD_SUPPORT 4055 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_gcw_word_get), 4056 #endif /* CPRIMOD_SUPPORT */ 4057 #ifdef CPRIMOD_SUPPORT 4058 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_gcw_word_set), 4059 #endif /* CPRIMOD_SUPPORT */ 4060 CINT_FWRAPPER_ENTRY(portmod_pm_interrupt_process), 4061 CINT_FWRAPPER_ENTRY(portmod_port_rlm_config_set), 4062 CINT_FWRAPPER_ENTRY(portmod_port_rlm_config_get), 4063 CINT_FWRAPPER_ENTRY(portmod_port_rlm_status_get), 4064 #ifdef CPRIMOD_SUPPORT 4065 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_tunnel_mode_config_get), 4066 #endif /* CPRIMOD_SUPPORT */ 4067 #ifdef CPRIMOD_SUPPORT 4068 CINT_FWRAPPER_ENTRY(portmod_cpri_port_rx_tunnel_mode_config_set), 4069 #endif /* CPRIMOD_SUPPORT */ 4070 #ifdef CPRIMOD_SUPPORT 4071 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_tunnel_mode_config_get), 4072 #endif /* CPRIMOD_SUPPORT */ 4073 #ifdef CPRIMOD_SUPPORT 4074 CINT_FWRAPPER_ENTRY(portmod_cpri_port_tx_tunnel_mode_config_set), 4075 #endif /* CPRIMOD_SUPPORT */ 4076 #ifdef CPRIMOD_SUPPORT 4077 CINT_FWRAPPER_ENTRY(portmod_rsvd4_port_rx_agnostic_config_get), 4078 #endif /* CPRIMOD_SUPPORT */ 4079 #ifdef CPRIMOD_SUPPORT 4080 CINT_FWRAPPER_ENTRY(portmod_rsvd4_port_rx_agnostic_config_set), 4081 #endif /* CPRIMOD_SUPPORT */ 4082 #ifdef CPRIMOD_SUPPORT 4083 CINT_FWRAPPER_ENTRY(portmod_rsvd4_port_tx_agnostic_config_get), 4084 #endif /* CPRIMOD_SUPPORT */ 4085 #ifdef CPRIMOD_SUPPORT 4086 CINT_FWRAPPER_ENTRY(portmod_rsvd4_port_tx_agnostic_config_set), 4087 #endif /* CPRIMOD_SUPPORT */ 4088 #ifdef CPRIMOD_SUPPORT 4089 CINT_FWRAPPER_ENTRY(portmod_cpri_port_frame_config_set), 4090 #endif /* CPRIMOD_SUPPORT */ 4091 #ifdef CPRIMOD_SUPPORT 4092 CINT_FWRAPPER_ENTRY(portmod_cpri_port_compression_saturation_config_get), 4093 #endif /* CPRIMOD_SUPPORT */ 4094 #ifdef CPRIMOD_SUPPORT 4095 CINT_FWRAPPER_ENTRY(portmod_cpri_port_compression_saturation_config_set), 4096 #endif /* CPRIMOD_SUPPORT */ 4097 #ifdef CPRIMOD_SUPPORT 4098 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decompression_saturation_config_get), 4099 #endif /* CPRIMOD_SUPPORT */ 4100 #ifdef CPRIMOD_SUPPORT 4101 CINT_FWRAPPER_ENTRY(portmod_cpri_port_decompression_saturation_config_set), 4102 #endif /* CPRIMOD_SUPPORT */ 4103 { NULL } 4104 }; 4105 4106 /* Functions pointers section */ 4107 static cint_function_pointer_t __cint_function_pointers[6]; 4108 4109 static int 4110 __cint_fpointer__portmod_ilkn_core_lane_map_callback_get_f(int unit, int port, int nof_lanes, int* rx_lane_map, int* tx_lane_map) 4111 { 4112 int returnval; 4113 4114 cint_interpreter_callback(__cint_function_pointers+0, 5, 1, &unit, &port, &nof_lanes, &rx_lane_map, &tx_lane_map, &returnval); 4115 return returnval; 4116 } 4117 4118 static int 4119 __cint_fpointer__portmod_ilkn_pm_lane_map_callback_get_f(int unit, int port, int nof_lanes, int first_phy, phymod_lane_map_t* lane_map) 4120 { 4121 int returnval; 4122 4123 cint_interpreter_callback(__cint_function_pointers+1, 5, 1, &unit, &port, &nof_lanes, &first_phy, &lane_map, &returnval); 4124 return returnval; 4125 } 4126 4127 static int 4128 __cint_fpointer__portmod_mac_soft_reset_f(int unit, int port, portmod_call_back_action_type_t action) 4129 { 4130 int returnval; 4131 4132 cint_interpreter_callback(__cint_function_pointers+2, 3, 1, &unit, &port, &action, &returnval); 4133 return returnval; 4134 } 4135 4136 static int 4137 __cint_fpointer__portmod_phy_external_reset_f(int unit, int port, uint32 in_reset) 4138 { 4139 int returnval; 4140 4141 cint_interpreter_callback(__cint_function_pointers+3, 3, 1, &unit, &port, &in_reset, &returnval); 4142 return returnval; 4143 } 4144 4145 static int 4146 __cint_fpointer__portmod_egress_buffer_reset_f(int unit, int port) 4147 { 4148 int returnval; 4149 4150 cint_interpreter_callback(__cint_function_pointers+4, 2, 1, &unit, &port, &returnval); 4151 return returnval; 4152 } 4153 4154 4155 static cint_parameter_desc_t __cint_parameters_portmod_ilkn_core_lane_map_callback_get_f[] = 4156 { 4157 {"int", "r", 0, 0}, 4158 {"int", "unit", 0, 0}, 4159 {"int", "port", 0, 0}, 4160 {"int", "nof_lanes", 0, 0}, 4161 {"int", "rx_lane_map", 1, 0}, 4162 {"int", "tx_lane_map", 1, 0}, 4163 { NULL } 4164 }; 4165 4166 static cint_parameter_desc_t __cint_parameters_portmod_ilkn_pm_lane_map_callback_get_f[] = 4167 { 4168 {"int", "r", 0, 0}, 4169 {"int", "unit", 0, 0}, 4170 {"int", "port", 0, 0}, 4171 {"int", "nof_lanes", 0, 0}, 4172 {"int", "first_phy", 0, 0}, 4173 {"phymod_lane_map_t", "lane_map", 1, 0}, 4174 { NULL } 4175 }; 4176 4177 static cint_parameter_desc_t __cint_parameters_portmod_mac_soft_reset_f[] = 4178 { 4179 {"int", "r", 0, 0}, 4180 {"int", "unit", 0, 0}, 4181 {"int", "port", 0, 0}, 4182 {"portmod_call_back_action_type_t", "action", 0, 0}, 4183 { NULL } 4184 }; 4185 4186 static cint_parameter_desc_t __cint_parameters_portmod_phy_external_reset_f[] = 4187 { 4188 {"int", "r", 0, 0}, 4189 {"int", "unit", 0, 0}, 4190 {"int", "port", 0, 0}, 4191 {"uint32", "in_reset", 0, 0}, 4192 { NULL } 4193 }; 4194 4195 static cint_parameter_desc_t __cint_parameters_portmod_egress_buffer_reset_f[] = 4196 { 4197 {"int", "r", 0, 0}, 4198 {"int", "unit", 0, 0}, 4199 {"int", "port", 0, 0}, 4200 { NULL } 4201 }; 4202 4203 4204 static cint_function_pointer_t __cint_function_pointers[] = 4205 { 4206 { 4207 "portmod_ilkn_core_lane_map_callback_get_f", 4208 (cint_fpointer_t) __cint_fpointer__portmod_ilkn_core_lane_map_callback_get_f, 4209 __cint_parameters_portmod_ilkn_core_lane_map_callback_get_f 4210 }, 4211 { 4212 "portmod_ilkn_pm_lane_map_callback_get_f", 4213 (cint_fpointer_t) __cint_fpointer__portmod_ilkn_pm_lane_map_callback_get_f, 4214 __cint_parameters_portmod_ilkn_pm_lane_map_callback_get_f 4215 }, 4216 { 4217 "portmod_mac_soft_reset_f", 4218 (cint_fpointer_t) __cint_fpointer__portmod_mac_soft_reset_f, 4219 __cint_parameters_portmod_mac_soft_reset_f 4220 }, 4221 { 4222 "portmod_phy_external_reset_f", 4223 (cint_fpointer_t) __cint_fpointer__portmod_phy_external_reset_f, 4224 __cint_parameters_portmod_phy_external_reset_f 4225 }, 4226 { 4227 "portmod_egress_buffer_reset_f", 4228 (cint_fpointer_t) __cint_fpointer__portmod_egress_buffer_reset_f, 4229 __cint_parameters_portmod_egress_buffer_reset_f 4230 }, 4231 { NULL } 4232 }; 4233 4234 /* Structs section */ 4235 static void* 4236 __cint_maddr__portmod_default_user_access_t(void* p, int mnum, cint_struct_type_t* parent) 4237 { 4238 void* rv; 4239 portmod_default_user_access_t* s = (portmod_default_user_access_t*) p; 4240 switch(mnum) 4241 { 4242 case 0: rv = &(s->unit);break; 4243 case 1: rv = &(s->blk_id);break; 4244 case 2: rv = &(s->mutex);break; 4245 case 3: rv = &(s->flags);break; 4246 default: rv = NULL; break; 4247 } 4248 return rv; 4249 } 4250 4251 static void* 4252 __cint_maddr__portmod_pm4x10q_user_data_t(void* p, int mnum, cint_struct_type_t* parent) 4253 { 4254 void* rv; 4255 portmod_pm4x10q_user_data_t* s = (portmod_pm4x10q_user_data_t*) p; 4256 switch(mnum) 4257 { 4258 case 0: rv = &(s->pm4x10_access);break; 4259 case 1: rv = &(s->qsgmiie_user_data);break; 4260 default: rv = NULL; break; 4261 } 4262 return rv; 4263 } 4264 4265 static void* 4266 __cint_maddr__portmod_fifo_status_t(void* p, int mnum, cint_struct_type_t* parent) 4267 { 4268 void* rv; 4269 portmod_fifo_status_t* s = (portmod_fifo_status_t*) p; 4270 switch(mnum) 4271 { 4272 case 0: rv = &(s->timestamps_in_fifo);break; 4273 case 1: rv = &(s->timestamps_in_fifo_hi);break; 4274 case 2: rv = &(s->sequence_id);break; 4275 case 3: rv = &(s->timestamp_sub_nanosec);break; 4276 default: rv = NULL; break; 4277 } 4278 return rv; 4279 } 4280 4281 static void* 4282 __cint_maddr__portmod_pfc_config_t(void* p, int mnum, cint_struct_type_t* parent) 4283 { 4284 void* rv; 4285 portmod_pfc_config_t* s = (portmod_pfc_config_t*) p; 4286 switch(mnum) 4287 { 4288 case 0: rv = &(s->type);break; 4289 case 1: rv = &(s->opcode);break; 4290 case 2: rv = &(s->classes);break; 4291 case 3: rv = &(s->da_oui);break; 4292 case 4: rv = &(s->da_nonoui);break; 4293 case 5: rv = &(s->rxpass);break; 4294 default: rv = NULL; break; 4295 } 4296 return rv; 4297 } 4298 4299 static void* 4300 __cint_maddr__portmod_eee_t(void* p, int mnum, cint_struct_type_t* parent) 4301 { 4302 void* rv; 4303 portmod_eee_t* s = (portmod_eee_t*) p; 4304 switch(mnum) 4305 { 4306 case 0: rv = &(s->enable);break; 4307 case 1: rv = &(s->tx_idle_time);break; 4308 case 2: rv = &(s->tx_wake_time);break; 4309 default: rv = NULL; break; 4310 } 4311 return rv; 4312 } 4313 4314 static void* 4315 __cint_maddr__portmod_eee_clock_t(void* p, int mnum, cint_struct_type_t* parent) 4316 { 4317 void* rv; 4318 portmod_eee_clock_t* s = (portmod_eee_clock_t*) p; 4319 switch(mnum) 4320 { 4321 case 0: rv = &(s->clock_gate);break; 4322 case 1: rv = &(s->clock_count);break; 4323 case 2: rv = &(s->timer_pulse);break; 4324 default: rv = NULL; break; 4325 } 4326 return rv; 4327 } 4328 4329 static void* 4330 __cint_maddr__portmod_vlan_tag_t(void* p, int mnum, cint_struct_type_t* parent) 4331 { 4332 void* rv; 4333 portmod_vlan_tag_t* s = (portmod_vlan_tag_t*) p; 4334 switch(mnum) 4335 { 4336 case 0: rv = &(s->inner_vlan_tag);break; 4337 case 1: rv = &(s->outer_vlan_tag);break; 4338 default: rv = NULL; break; 4339 } 4340 return rv; 4341 } 4342 4343 static void* 4344 __cint_maddr__portmod_rx_control_t(void* p, int mnum, cint_struct_type_t* parent) 4345 { 4346 void* rv; 4347 portmod_rx_control_t* s = (portmod_rx_control_t*) p; 4348 switch(mnum) 4349 { 4350 case 0: rv = &(s->flags);break; 4351 case 1: rv = &(s->pass_control_frames);break; 4352 case 2: rv = &(s->pass_pfc_frames);break; 4353 case 3: rv = &(s->pass_pause_frames);break; 4354 default: rv = NULL; break; 4355 } 4356 return rv; 4357 } 4358 4359 static void* 4360 __cint_maddr__portmod_multi_get_t(void* p, int mnum, cint_struct_type_t* parent) 4361 { 4362 void* rv; 4363 portmod_multi_get_t* s = (portmod_multi_get_t*) p; 4364 switch(mnum) 4365 { 4366 case 0: rv = &(s->flags);break; 4367 case 1: rv = &(s->dev_addr);break; 4368 case 2: rv = &(s->offset);break; 4369 case 3: rv = &(s->max_size);break; 4370 case 4: rv = &(s->data);break; 4371 case 5: rv = &(s->actual_size);break; 4372 default: rv = NULL; break; 4373 } 4374 return rv; 4375 } 4376 4377 static void* 4378 __cint_maddr__portmod_portphy_ability_t(void* p, int mnum, cint_struct_type_t* parent) 4379 { 4380 void* rv; 4381 portmod_portphy_ability_t* s = (portmod_portphy_ability_t*) p; 4382 switch(mnum) 4383 { 4384 case 0: rv = &(s->cur_mode);break; 4385 case 1: rv = &(s->speed_half_duplex);break; 4386 case 2: rv = &(s->speed_full_duplex);break; 4387 case 3: rv = &(s->pause);break; 4388 case 4: rv = &(s->interface);break; 4389 case 5: rv = &(s->medium);break; 4390 case 6: rv = &(s->loopback);break; 4391 case 7: rv = &(s->flags);break; 4392 case 8: rv = &(s->eee);break; 4393 case 9: rv = &(s->fcmap);break; 4394 case 10: rv = &(s->encap);break; 4395 default: rv = NULL; break; 4396 } 4397 return rv; 4398 } 4399 4400 static void* 4401 __cint_maddr__portmod_pdata_t(void* p, int mnum, cint_struct_type_t* parent) 4402 { 4403 void* rv; 4404 portmod_pdata_t* s = (portmod_pdata_t*) p; 4405 switch(mnum) 4406 { 4407 case 0: rv = &(s->data);break; 4408 case 1: rv = &(s->enable);break; 4409 case 2: rv = &(s->pif);break; 4410 case 3: rv = &(s->ability);break; 4411 default: rv = NULL; break; 4412 } 4413 return rv; 4414 } 4415 4416 static void* 4417 __cint_maddr__portmod_port_mode_info_t(void* p, int mnum, cint_struct_type_t* parent) 4418 { 4419 void* rv; 4420 portmod_port_mode_info_t* s = (portmod_port_mode_info_t*) p; 4421 switch(mnum) 4422 { 4423 case 0: rv = &(s->cur_mode);break; 4424 case 1: rv = &(s->lanes);break; 4425 case 2: rv = &(s->port_index);break; 4426 default: rv = NULL; break; 4427 } 4428 return rv; 4429 } 4430 4431 static void* 4432 __cint_maddr__portmod_port_diag_info_t(void* p, int mnum, cint_struct_type_t* parent) 4433 { 4434 void* rv; 4435 portmod_port_diag_info_t* s = (portmod_port_diag_info_t*) p; 4436 switch(mnum) 4437 { 4438 case 0: rv = &(s->original_port);break; 4439 case 1: rv = &(s->interface);break; 4440 case 2: rv = &(s->pm_id);break; 4441 case 3: rv = &(s->phys);break; 4442 case 4: rv = &(s->sub_phy);break; 4443 case 5: rv = &(s->medium);break; 4444 case 6: rv = &(s->core_mode);break; 4445 case 7: rv = &(s->polarity);break; 4446 case 8: rv = &(s->fec);break; 4447 default: rv = NULL; break; 4448 } 4449 return rv; 4450 } 4451 4452 static void* 4453 __cint_maddr__portmod_pm_core_info_t(void* p, int mnum, cint_struct_type_t* parent) 4454 { 4455 void* rv; 4456 portmod_pm_core_info_t* s = (portmod_pm_core_info_t*) p; 4457 switch(mnum) 4458 { 4459 case 0: rv = &(s->ref_clk);break; 4460 case 1: rv = &(s->lane_map);break; 4461 case 2: rv = &(s->nof_phys);break; 4462 default: rv = NULL; break; 4463 } 4464 return rv; 4465 } 4466 4467 static void* 4468 __cint_maddr__portmod_pm_diag_info_t(void* p, int mnum, cint_struct_type_t* parent) 4469 { 4470 void* rv; 4471 portmod_pm_diag_info_t* s = (portmod_pm_diag_info_t*) p; 4472 switch(mnum) 4473 { 4474 case 0: rv = &(s->type);break; 4475 case 1: rv = &(s->core_info);break; 4476 case 2: rv = &(s->phys);break; 4477 case 3: rv = &(s->ports);break; 4478 case 4: rv = &(s->serdes_id0);break; 4479 case 5: rv = &(s->phy_id0);break; 4480 case 6: rv = &(s->phy_id1);break; 4481 case 7: rv = &(s->name);break; 4482 default: rv = NULL; break; 4483 } 4484 return rv; 4485 } 4486 4487 static void* 4488 __cint_maddr__portmod_port_ts_adjust_t(void* p, int mnum, cint_struct_type_t* parent) 4489 { 4490 void* rv; 4491 portmod_port_ts_adjust_t* s = (portmod_port_ts_adjust_t*) p; 4492 switch(mnum) 4493 { 4494 case 0: rv = &(s->speed);break; 4495 case 1: rv = &(s->osts_adjust);break; 4496 case 2: rv = &(s->tsts_adjust);break; 4497 default: rv = NULL; break; 4498 } 4499 return rv; 4500 } 4501 4502 static void* 4503 __cint_maddr__portmod_port_init_config_t(void* p, int mnum, cint_struct_type_t* parent) 4504 { 4505 void* rv; 4506 portmod_port_init_config_t* s = (portmod_port_init_config_t*) p; 4507 switch(mnum) 4508 { 4509 case 0: rv = &(s->phy_reset_config);break; 4510 case 1: rv = &(s->pattern);break; 4511 case 2: rv = &(s->cx4_10g);break; 4512 case 3: rv = &(s->pdetect1000x);break; 4513 case 4: rv = &(s->an_mode);break; 4514 case 5: rv = &(s->an_master_lane);break; 4515 case 6: rv = &(s->an_cl72);break; 4516 case 7: rv = &(s->fs_cl72);break; 4517 case 8: rv = &(s->an_fec);break; 4518 case 9: rv = &(s->serdes_fec_enable);break; 4519 case 10: rv = &(s->sgmii_mstr);break; 4520 case 11: rv = &(s->serdes_driver_current);break; 4521 case 12: rv = &(s->serdes_1000x_at_6250_vco);break; 4522 case 13: rv = &(s->serdes_1000x_at_12500_vco);break; 4523 case 14: rv = &(s->serdes_1000x_at_25g_vco);break; 4524 case 15: rv = &(s->serdes_10g_at_25g_vco);break; 4525 case 16: rv = &(s->pll_divider_req);break; 4526 case 17: rv = &(s->rxaui_mode);break; 4527 case 18: rv = &(s->port_fallback_lane);break; 4528 case 19: rv = &(s->tx_params_user_flag);break; 4529 case 20: rv = &(s->tx_params);break; 4530 case 21: rv = &(s->an_cl37);break; 4531 case 22: rv = &(s->cl37_sgmii_war);break; 4532 case 23: rv = &(s->cl37_sgmii_cnt);break; 4533 case 24: rv = &(s->cl37_sgmii_RESTART_CNT);break; 4534 case 25: rv = &(s->an_cl73);break; 4535 case 26: rv = &(s->is_hg);break; 4536 case 27: rv = &(s->ext_phy_tx_params_user_flag);break; 4537 case 28: rv = &(s->ext_phy_tx_params);break; 4538 case 29: rv = &(s->polarity);break; 4539 case 30: rv = &(s->polarity_overwrite);break; 4540 case 31: rv = &(s->lane_map);break; 4541 case 32: rv = &(s->lane_map_overwrite);break; 4542 case 33: rv = &(s->fw_load_method);break; 4543 case 34: rv = &(s->fw_load_method_overwrite);break; 4544 case 35: rv = &(s->ref_clk);break; 4545 case 36: rv = &(s->ref_clk_overwrite);break; 4546 case 37: rv = &(s->port_mode_aux_info);break; 4547 case 38: rv = &(s->port_ts_adjust);break; 4548 case 39: rv = &(s->txpi_mode);break; 4549 case 40: rv = &(s->txpi_sdm_scheme);break; 4550 case 41: rv = &(s->roe_stuffing_bit);break; 4551 case 42: rv = &(s->roe_reserved_bit);break; 4552 case 43: rv = &(s->cpm_core_mode);break; 4553 case 44: rv = &(s->qtc_mode);break; 4554 case 45: rv = &(s->parity_enable);break; 4555 default: rv = NULL; break; 4556 } 4557 return rv; 4558 } 4559 4560 static void* 4561 __cint_maddr__portmod_port_interface_config_t(void* p, int mnum, cint_struct_type_t* parent) 4562 { 4563 void* rv; 4564 portmod_port_interface_config_t* s = (portmod_port_interface_config_t*) p; 4565 switch(mnum) 4566 { 4567 case 0: rv = &(s->interface);break; 4568 case 1: rv = &(s->line_interface);break; 4569 case 2: rv = &(s->serdes_interface);break; 4570 case 3: rv = &(s->interface_modes);break; 4571 case 4: rv = &(s->flags);break; 4572 case 5: rv = &(s->port_refclk_int);break; 4573 case 6: rv = &(s->port_num_lanes);break; 4574 case 7: rv = &(s->speed);break; 4575 case 8: rv = &(s->max_speed);break; 4576 case 9: rv = &(s->encap_mode);break; 4577 case 10: rv = &(s->pll_divider_req);break; 4578 case 11: rv = &(s->port_op_mode);break; 4579 case 12: rv = &(s->serdes_scrambler_seed);break; 4580 case 13: rv = &(s->serdes_scrambler_enable);break; 4581 default: rv = NULL; break; 4582 } 4583 return rv; 4584 } 4585 4586 static void* 4587 __cint_maddr__portmod_port_speed_ability_t(void* p, int mnum, cint_struct_type_t* parent) 4588 { 4589 void* rv; 4590 portmod_port_speed_ability_t* s = (portmod_port_speed_ability_t*) p; 4591 switch(mnum) 4592 { 4593 case 0: rv = &(s->speed);break; 4594 case 1: rv = &(s->num_lanes);break; 4595 case 2: rv = &(s->fec_type);break; 4596 case 3: rv = &(s->medium);break; 4597 case 4: rv = &(s->pause);break; 4598 case 5: rv = &(s->channel);break; 4599 case 6: rv = &(s->an_mode);break; 4600 default: rv = NULL; break; 4601 } 4602 return rv; 4603 } 4604 4605 static void* 4606 __cint_maddr__portmod_speed_config_t(void* p, int mnum, cint_struct_type_t* parent) 4607 { 4608 void* rv; 4609 portmod_speed_config_t* s = (portmod_speed_config_t*) p; 4610 switch(mnum) 4611 { 4612 case 0: rv = &(s->speed);break; 4613 case 1: rv = &(s->num_lane);break; 4614 case 2: rv = &(s->fec);break; 4615 case 3: rv = &(s->link_training);break; 4616 case 4: rv = &(s->lane_config);break; 4617 case 5: rv = &(s->flags);break; 4618 default: rv = NULL; break; 4619 } 4620 return rv; 4621 } 4622 4623 static void* 4624 __cint_maddr__portmod_pm_identifier_t(void* p, int mnum, cint_struct_type_t* parent) 4625 { 4626 void* rv; 4627 portmod_pm_identifier_t* s = (portmod_pm_identifier_t*) p; 4628 switch(mnum) 4629 { 4630 case 0: rv = &(s->type);break; 4631 case 1: rv = &(s->phy);break; 4632 default: rv = NULL; break; 4633 } 4634 return rv; 4635 } 4636 4637 static void* 4638 __cint_maddr__portmod_port_add_info_t(void* p, int mnum, cint_struct_type_t* parent) 4639 { 4640 void* rv; 4641 portmod_port_add_info_t* s = (portmod_port_add_info_t*) p; 4642 switch(mnum) 4643 { 4644 case 0: rv = &(s->interface_config);break; 4645 case 1: rv = &(s->init_config);break; 4646 case 2: rv = &(s->speed_config);break; 4647 case 3: rv = &(s->tvco);break; 4648 case 4: rv = &(s->ovco);break; 4649 case 5: rv = &(s->phys);break; 4650 case 6: rv = &(s->phy_ports);break; 4651 case 7: rv = &(s->sub_phy);break; 4652 case 8: rv = &(s->autoneg_en);break; 4653 case 9: rv = &(s->link_training_en);break; 4654 case 10: rv = &(s->flags);break; 4655 case 11: rv = &(s->is_fabric_o_nif);break; 4656 case 12: rv = &(s->ilkn_core_id);break; 4657 case 13: rv = &(s->ilkn_port_is_over_fabric);break; 4658 case 14: rv = &(s->ilkn_burst_max);break; 4659 case 15: rv = &(s->ilkn_burst_min);break; 4660 case 16: rv = &(s->ilkn_burst_short);break; 4661 case 17: rv = &(s->ilkn_nof_segments);break; 4662 case 18: rv = &(s->ilkn_metaframe_period);break; 4663 case 19: rv = &(s->rx_retransmit);break; 4664 case 20: rv = &(s->tx_retransmit);break; 4665 case 21: rv = &(s->phy_op_mode);break; 4666 case 22: rv = &(s->phy_op_datapath);break; 4667 case 23: rv = &(s->ilkn_inb_cal_len_rx);break; 4668 case 24: rv = &(s->ilkn_inb_cal_len_tx);break; 4669 case 25: rv = &(s->ilkn_oob_cal_len_rx);break; 4670 case 26: rv = &(s->ilkn_oob_cal_len_tx);break; 4671 case 27: rv = &(s->reserved_channel_rx);break; 4672 case 28: rv = &(s->reserved_channel_tx);break; 4673 case 29: rv = &(s->ilkn_lanes);break; 4674 case 30: rv = &(s->nof_aggregated_pms);break; 4675 case 31: rv = &(s->controlled_pms);break; 4676 default: rv = NULL; break; 4677 } 4678 return rv; 4679 } 4680 4681 static void* 4682 __cint_maddr__portmod_dnx_fabric_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4683 { 4684 void* rv; 4685 portmod_dnx_fabric_create_info_t* s = (portmod_dnx_fabric_create_info_t*) p; 4686 switch(mnum) 4687 { 4688 case 0: rv = &(s->ref_clk);break; 4689 case 1: rv = &(s->com_clk);break; 4690 case 2: rv = &(s->access);break; 4691 case 3: rv = &(s->lane_map);break; 4692 case 4: rv = &(s->fw_load_method);break; 4693 case 5: rv = &(s->external_fw_loader);break; 4694 case 6: rv = &(s->polarity);break; 4695 case 7: rv = &(s->fmac_schan_id);break; 4696 case 8: rv = &(s->fsrd_schan_id);break; 4697 case 9: rv = &(s->fsrd_internal_quad);break; 4698 case 10: rv = &(s->first_phy_offset);break; 4699 case 11: rv = &(s->core_index);break; 4700 case 12: rv = &(s->is_over_nif);break; 4701 case 13: rv = &(s->fabric_o_nif_pm);break; 4702 default: rv = NULL; break; 4703 } 4704 return rv; 4705 } 4706 4707 static void* 4708 __cint_maddr__portmod_pm8x50_fabric_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4709 { 4710 void* rv; 4711 portmod_pm8x50_fabric_create_info_t* s = (portmod_pm8x50_fabric_create_info_t*) p; 4712 switch(mnum) 4713 { 4714 case 0: rv = &(s->ref_clk);break; 4715 case 1: rv = &(s->access);break; 4716 case 2: rv = &(s->fw_load_method);break; 4717 case 3: rv = &(s->external_fw_loader);break; 4718 case 4: rv = &(s->polarity);break; 4719 case 5: rv = &(s->fmac_schan_id);break; 4720 case 6: rv = &(s->fsrd_schan_id);break; 4721 case 7: rv = &(s->first_phy_offset);break; 4722 case 8: rv = &(s->core_index);break; 4723 case 9: rv = &(s->force_single_pll);break; 4724 case 10: rv = &(s->bypass_lanes_bitmap);break; 4725 case 11: rv = &(s->is_rx_ctrl_bypass_supported);break; 4726 default: rv = NULL; break; 4727 } 4728 return rv; 4729 } 4730 4731 static void* 4732 __cint_maddr__portmod_pm4x25_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4733 { 4734 void* rv; 4735 portmod_pm4x25_create_info_t* s = (portmod_pm4x25_create_info_t*) p; 4736 switch(mnum) 4737 { 4738 case 0: rv = &(s->ref_clk);break; 4739 case 1: rv = &(s->access);break; 4740 case 2: rv = &(s->lane_map);break; 4741 case 3: rv = &(s->fw_load_method);break; 4742 case 4: rv = &(s->external_fw_loader);break; 4743 case 5: rv = &(s->polarity);break; 4744 case 6: rv = &(s->in_pm_12x10);break; 4745 case 7: rv = &(s->core_num);break; 4746 case 8: rv = &(s->core_num_int);break; 4747 case 9: rv = &(s->portmod_mac_soft_reset);break; 4748 case 10: rv = &(s->afe_pll);break; 4749 case 11: rv = &(s->rescal);break; 4750 case 12: rv = &(s->port_mode_aux_info);break; 4751 default: rv = NULL; break; 4752 } 4753 return rv; 4754 } 4755 4756 static void* 4757 __cint_maddr__portmod_pm4x10_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4758 { 4759 void* rv; 4760 portmod_pm4x10_create_info_t* s = (portmod_pm4x10_create_info_t*) p; 4761 switch(mnum) 4762 { 4763 case 0: rv = &(s->phy_ports);break; 4764 case 1: rv = &(s->ref_clk);break; 4765 case 2: rv = &(s->access);break; 4766 case 3: rv = &(s->lane_map);break; 4767 case 4: rv = &(s->fw_load_method);break; 4768 case 5: rv = &(s->external_fw_loader);break; 4769 case 6: rv = &(s->polarity);break; 4770 case 7: rv = &(s->in_pm_12x10);break; 4771 case 8: rv = &(s->portmod_phy_external_reset);break; 4772 case 9: rv = &(s->portmod_mac_soft_reset);break; 4773 case 10: rv = &(s->core_num);break; 4774 case 11: rv = &(s->core_num_int);break; 4775 case 12: rv = &(s->port_mode_aux_info);break; 4776 case 13: rv = &(s->rescal);break; 4777 case 14: rv = &(s->is_pm4x10q);break; 4778 default: rv = NULL; break; 4779 } 4780 return rv; 4781 } 4782 4783 static void* 4784 __cint_maddr__portmod_pm_qtc_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4785 { 4786 void* rv; 4787 portmod_pm_qtc_create_info_t* s = (portmod_pm_qtc_create_info_t*) p; 4788 switch(mnum) 4789 { 4790 case 0: rv = &(s->ref_clk);break; 4791 case 1: rv = &(s->access);break; 4792 case 2: rv = &(s->lane_map);break; 4793 case 3: rv = &(s->fw_load_method);break; 4794 case 4: rv = &(s->external_fw_loader);break; 4795 case 5: rv = &(s->polarity);break; 4796 case 6: rv = &(s->portmod_phy_external_reset);break; 4797 case 7: rv = &(s->portmod_mac_soft_reset);break; 4798 case 8: rv = &(s->core_num);break; 4799 case 9: rv = &(s->core_clock_khz);break; 4800 default: rv = NULL; break; 4801 } 4802 return rv; 4803 } 4804 4805 static void* 4806 __cint_maddr__portmod_pm_gphy_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4807 { 4808 void* rv; 4809 portmod_pm_gphy_create_info_t* s = (portmod_pm_gphy_create_info_t*) p; 4810 switch(mnum) 4811 { 4812 case 0: rv = &(s->ref_clk);break; 4813 case 1: rv = &(s->access);break; 4814 case 2: rv = &(s->lane_map);break; 4815 case 3: rv = &(s->fw_load_method);break; 4816 case 4: rv = &(s->external_fw_loader);break; 4817 case 5: rv = &(s->polarity);break; 4818 case 6: rv = &(s->portmod_phy_external_reset);break; 4819 case 7: rv = &(s->portmod_mac_soft_reset);break; 4820 case 8: rv = &(s->core_num);break; 4821 default: rv = NULL; break; 4822 } 4823 return rv; 4824 } 4825 4826 static void* 4827 __cint_maddr__portmod_pm12x10_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4828 { 4829 void* rv; 4830 portmod_pm12x10_create_info_t* s = (portmod_pm12x10_create_info_t*) p; 4831 switch(mnum) 4832 { 4833 case 0: rv = &(s->pm4x10_infos);break; 4834 case 1: rv = &(s->pm4x25_info);break; 4835 case 2: rv = &(s->flags);break; 4836 case 3: rv = &(s->blk_id);break; 4837 case 4: rv = &(s->refclk_source);break; 4838 default: rv = NULL; break; 4839 } 4840 return rv; 4841 } 4842 4843 static void* 4844 __cint_maddr__portmod_pm4x10q_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4845 { 4846 void* rv; 4847 portmod_pm4x10q_create_info_t* s = (portmod_pm4x10q_create_info_t*) p; 4848 switch(mnum) 4849 { 4850 case 0: rv = &(s->pm4x10_info);break; 4851 case 1: rv = &(s->blk_id);break; 4852 case 2: rv = &(s->qsgmii_user_acc);break; 4853 case 3: rv = &(s->core_clock_khz);break; 4854 default: rv = NULL; break; 4855 } 4856 return rv; 4857 } 4858 4859 static void* 4860 __cint_maddr__portmod_ilkn_os_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4861 { 4862 void* rv; 4863 portmod_ilkn_os_create_info_t* s = (portmod_ilkn_os_create_info_t*) p; 4864 switch(mnum) 4865 { 4866 case 0: rv = &(s->nof_aggregated_pms);break; 4867 case 1: rv = &(s->controlled_pms);break; 4868 case 2: rv = &(s->wm_high);break; 4869 case 3: rv = &(s->wm_low);break; 4870 case 4: rv = &(s->is_over_fabric);break; 4871 case 5: rv = &(s->core_clock_khz);break; 4872 case 6: rv = &(s->ilkn_core_lane_map_get);break; 4873 case 7: rv = &(s->ilkn_pm_lane_map_get);break; 4874 case 8: rv = &(s->ilkn_block_index);break; 4875 default: rv = NULL; break; 4876 } 4877 return rv; 4878 } 4879 4880 static void* 4881 __cint_maddr__portmod_pm4x2p5_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4882 { 4883 void* rv; 4884 portmod_pm4x2p5_create_info_t* s = (portmod_pm4x2p5_create_info_t*) p; 4885 switch(mnum) 4886 { 4887 case 0: rv = &(s->phy_ports);break; 4888 case 1: rv = &(s->ref_clk);break; 4889 case 2: rv = &(s->access);break; 4890 case 3: rv = &(s->lane_map);break; 4891 case 4: rv = &(s->fw_load_method);break; 4892 case 5: rv = &(s->external_fw_loader);break; 4893 case 6: rv = &(s->polarity);break; 4894 case 7: rv = &(s->portmod_phy_external_reset);break; 4895 case 8: rv = &(s->portmod_mac_soft_reset);break; 4896 default: rv = NULL; break; 4897 } 4898 return rv; 4899 } 4900 4901 static void* 4902 __cint_maddr__portmod_pm8x50_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4903 { 4904 void* rv; 4905 portmod_pm8x50_create_info_t* s = (portmod_pm8x50_create_info_t*) p; 4906 switch(mnum) 4907 { 4908 case 0: rv = &(s->phy_ports);break; 4909 case 1: rv = &(s->ref_clk);break; 4910 case 2: rv = &(s->tvco);break; 4911 case 3: rv = &(s->ovco);break; 4912 case 4: rv = &(s->access);break; 4913 case 5: rv = &(s->lane_map);break; 4914 case 6: rv = &(s->fw_load_method);break; 4915 case 7: rv = &(s->external_fw_loader);break; 4916 case 8: rv = &(s->polarity);break; 4917 case 9: rv = &(s->portmod_phy_external_reset);break; 4918 case 10: rv = &(s->portmod_mac_soft_reset);break; 4919 case 11: rv = &(s->core_num);break; 4920 case 12: rv = &(s->afe_pll);break; 4921 case 13: rv = &(s->rescal);break; 4922 case 14: rv = &(s->is_master_pm);break; 4923 case 15: rv = &(s->portmod_egress_buffer_reset);break; 4924 case 16: rv = &(s->allow_20p625g_tvco);break; 4925 default: rv = NULL; break; 4926 } 4927 return rv; 4928 } 4929 4930 static void* 4931 __cint_maddr__portmod_pm4x10_qtc_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4932 { 4933 void* rv; 4934 portmod_pm4x10_qtc_create_info_t* s = (portmod_pm4x10_qtc_create_info_t*) p; 4935 switch(mnum) 4936 { 4937 case 0: rv = &(s->pm4x10_info);break; 4938 case 1: rv = &(s->pm_qtc_info);break; 4939 default: rv = NULL; break; 4940 } 4941 return rv; 4942 } 4943 4944 static void* 4945 __cint_maddr__portmod_pm_specific_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 4946 { 4947 void* rv; 4948 portmod_pm_specific_create_info_t* s = (portmod_pm_specific_create_info_t*) p; 4949 switch(mnum) 4950 { 4951 case 0: rv = &(s->pm4x10);break; 4952 case 1: rv = &(s->pm4x10q);break; 4953 case 2: rv = &(s->pm_qtc);break; 4954 case 3: rv = &(s->pm_gphy);break; 4955 case 4: rv = &(s->pm4x25);break; 4956 case 5: rv = &(s->pm12x10);break; 4957 case 6: rv = &(s->os_ilkn);break; 4958 case 7: rv = &(s->dnx_fabric);break; 4959 case 8: rv = &(s->pm8x50_fabric);break; 4960 case 9: rv = &(s->pm4x2p5);break; 4961 case 10: rv = &(s->pm8x50);break; 4962 case 11: rv = &(s->pm4x10_qtc);break; 4963 default: rv = NULL; break; 4964 } 4965 return rv; 4966 } 4967 4968 static void* 4969 __cint_maddr__portmod_remote_fault_control_t(void* p, int mnum, cint_struct_type_t* parent) 4970 { 4971 void* rv; 4972 portmod_remote_fault_control_t* s = (portmod_remote_fault_control_t*) p; 4973 switch(mnum) 4974 { 4975 case 0: rv = &(s->enable);break; 4976 case 1: rv = &(s->drop_tx_on_fault);break; 4977 default: rv = NULL; break; 4978 } 4979 return rv; 4980 } 4981 4982 static void* 4983 __cint_maddr__portmod_local_fault_control_t(void* p, int mnum, cint_struct_type_t* parent) 4984 { 4985 void* rv; 4986 portmod_local_fault_control_t* s = (portmod_local_fault_control_t*) p; 4987 switch(mnum) 4988 { 4989 case 0: rv = &(s->enable);break; 4990 case 1: rv = &(s->drop_tx_on_fault);break; 4991 default: rv = NULL; break; 4992 } 4993 return rv; 4994 } 4995 4996 static void* 4997 __cint_maddr__portmod_llfc_control_t(void* p, int mnum, cint_struct_type_t* parent) 4998 { 4999 void* rv; 5000 portmod_llfc_control_t* s = (portmod_llfc_control_t*) p; 5001 switch(mnum) 5002 { 5003 case 0: rv = &(s->rx_enable);break; 5004 case 1: rv = &(s->tx_enable);break; 5005 case 2: rv = &(s->crc_ignore);break; 5006 case 3: rv = &(s->in_ipg_only);break; 5007 default: rv = NULL; break; 5008 } 5009 return rv; 5010 } 5011 5012 static void* 5013 __cint_maddr__portmod_pfc_control_t(void* p, int mnum, cint_struct_type_t* parent) 5014 { 5015 void* rv; 5016 portmod_pfc_control_t* s = (portmod_pfc_control_t*) p; 5017 switch(mnum) 5018 { 5019 case 0: rv = &(s->rx_enable);break; 5020 case 1: rv = &(s->tx_enable);break; 5021 case 2: rv = &(s->stats_en);break; 5022 case 3: rv = &(s->force_xon);break; 5023 case 4: rv = &(s->refresh_timer);break; 5024 case 5: rv = &(s->xoff_timer);break; 5025 default: rv = NULL; break; 5026 } 5027 return rv; 5028 } 5029 5030 static void* 5031 __cint_maddr__portmod_pause_control_t(void* p, int mnum, cint_struct_type_t* parent) 5032 { 5033 void* rv; 5034 portmod_pause_control_t* s = (portmod_pause_control_t*) p; 5035 switch(mnum) 5036 { 5037 case 0: rv = &(s->rx_enable);break; 5038 case 1: rv = &(s->tx_enable);break; 5039 case 2: rv = &(s->refresh_timer);break; 5040 case 3: rv = &(s->xoff_timer);break; 5041 default: rv = NULL; break; 5042 } 5043 return rv; 5044 } 5045 5046 static void* 5047 __cint_maddr__portmod_drain_cells_t(void* p, int mnum, cint_struct_type_t* parent) 5048 { 5049 void* rv; 5050 portmod_drain_cells_t* s = (portmod_drain_cells_t*) p; 5051 switch(mnum) 5052 { 5053 case 0: rv = &(s->rx_pfc_en);break; 5054 case 1: rv = &(s->llfc_en);break; 5055 case 2: rv = &(s->rx_pause);break; 5056 case 3: rv = &(s->tx_pause);break; 5057 default: rv = NULL; break; 5058 } 5059 return rv; 5060 } 5061 5062 static void* 5063 __cint_maddr__portmod_pm_create_info_t(void* p, int mnum, cint_struct_type_t* parent) 5064 { 5065 void* rv; 5066 portmod_pm_create_info_t* s = (portmod_pm_create_info_t*) p; 5067 switch(mnum) 5068 { 5069 case 0: rv = &(s->type);break; 5070 case 1: rv = &(s->phys);break; 5071 case 2: rv = &(s->pm_specific_info);break; 5072 default: rv = NULL; break; 5073 } 5074 return rv; 5075 } 5076 5077 static void* 5078 __cint_maddr__portmod_access_get_params_t(void* p, int mnum, cint_struct_type_t* parent) 5079 { 5080 void* rv; 5081 portmod_access_get_params_t* s = (portmod_access_get_params_t*) p; 5082 switch(mnum) 5083 { 5084 case 0: rv = &(s->phyn);break; 5085 case 1: rv = &(s->sys_side);break; 5086 case 2: rv = &(s->lane);break; 5087 case 3: rv = &(s->apply_lane_mask);break; 5088 default: rv = NULL; break; 5089 } 5090 return rv; 5091 } 5092 5093 static void* 5094 __cint_maddr__portmod_pm_instances_t(void* p, int mnum, cint_struct_type_t* parent) 5095 { 5096 void* rv; 5097 portmod_pm_instances_t* s = (portmod_pm_instances_t*) p; 5098 switch(mnum) 5099 { 5100 case 0: rv = &(s->type);break; 5101 case 1: rv = &(s->instances);break; 5102 default: rv = NULL; break; 5103 } 5104 return rv; 5105 } 5106 5107 static void* 5108 __cint_maddr__portmod_port_update_control_t(void* p, int mnum, cint_struct_type_t* parent) 5109 { 5110 void* rv; 5111 portmod_port_update_control_t* s = (portmod_port_update_control_t*) p; 5112 switch(mnum) 5113 { 5114 case 0: rv = &(s->link_status);break; 5115 case 1: rv = &(s->flags);break; 5116 default: rv = NULL; break; 5117 } 5118 return rv; 5119 } 5120 5121 static void* 5122 __cint_maddr__portmod_lane_connection_t(void* p, int mnum, cint_struct_type_t* parent) 5123 { 5124 void* rv; 5125 portmod_lane_connection_t* s = (portmod_lane_connection_t*) p; 5126 switch(mnum) 5127 { 5128 case 0: rv = &(s->core_index);break; 5129 case 1: rv = &(s->lane_index);break; 5130 default: rv = NULL; break; 5131 } 5132 return rv; 5133 } 5134 5135 static void* 5136 __cint_maddr__portmod_phy_core_info_t(void* p, int mnum, cint_struct_type_t* parent) 5137 { 5138 void* rv; 5139 portmod_phy_core_info_t* s = (portmod_phy_core_info_t*) p; 5140 switch(mnum) 5141 { 5142 case 0: rv = &(s->core_access);break; 5143 default: rv = NULL; break; 5144 } 5145 return rv; 5146 } 5147 5148 static void* 5149 __cint_maddr__portmod_xphy_lane_connection_t(void* p, int mnum, cint_struct_type_t* parent) 5150 { 5151 void* rv; 5152 portmod_xphy_lane_connection_t* s = (portmod_xphy_lane_connection_t*) p; 5153 switch(mnum) 5154 { 5155 case 0: rv = &(s->xphy_id);break; 5156 case 1: rv = &(s->ss_lane_mask);break; 5157 case 2: rv = &(s->ls_lane_mask);break; 5158 case 3: rv = &(s->rsvd1);break; 5159 case 4: rv = &(s->rsvd2);break; 5160 default: rv = NULL; break; 5161 } 5162 return rv; 5163 } 5164 5165 static void* 5166 __cint_maddr__portmod_port_higig_e2ecc_hdr_t(void* p, int mnum, cint_struct_type_t* parent) 5167 { 5168 void* rv; 5169 portmod_port_higig_e2ecc_hdr_t* s = (portmod_port_higig_e2ecc_hdr_t*) p; 5170 switch(mnum) 5171 { 5172 case 0: rv = &(s->words);break; 5173 default: rv = NULL; break; 5174 } 5175 return rv; 5176 } 5177 5178 static void* 5179 __cint_maddr__portmod_port_resources_t(void* p, int mnum, cint_struct_type_t* parent) 5180 { 5181 void* rv; 5182 portmod_port_resources_t* s = (portmod_port_resources_t*) p; 5183 switch(mnum) 5184 { 5185 case 0: rv = &(s->pm_type);break; 5186 case 1: rv = &(s->speed);break; 5187 case 2: rv = &(s->num_lane);break; 5188 case 3: rv = &(s->encap_mode);break; 5189 case 4: rv = &(s->flag);break; 5190 default: rv = NULL; break; 5191 } 5192 return rv; 5193 } 5194 5195 static void* 5196 __cint_maddr__portmod_link_recovery_t(void* p, int mnum, cint_struct_type_t* parent) 5197 { 5198 void* rv; 5199 portmod_link_recovery_t* s = (portmod_link_recovery_t*) p; 5200 switch(mnum) 5201 { 5202 case 0: rv = &(s->state);break; 5203 case 1: rv = &(s->enabled);break; 5204 case 2: rv = &(s->tick_cnt);break; 5205 default: rv = NULL; break; 5206 } 5207 return rv; 5208 } 5209 5210 static void* 5211 __cint_maddr__portmod_pmd_lane_config_t(void* p, int mnum, cint_struct_type_t* parent) 5212 { 5213 void* rv; 5214 portmod_pmd_lane_config_t* s = (portmod_pmd_lane_config_t*) p; 5215 switch(mnum) 5216 { 5217 case 0: rv = &(s->pmd_firmware_lane_config);break; 5218 case 1: rv = &(s->pam4_channel_loss);break; 5219 default: rv = NULL; break; 5220 } 5221 return rv; 5222 } 5223 5224 static void* 5225 __cint_maddr__portmod_sbus_bcast_config_t(void* p, int mnum, cint_struct_type_t* parent) 5226 { 5227 void* rv; 5228 portmod_sbus_bcast_config_t* s = (portmod_sbus_bcast_config_t*) p; 5229 switch(mnum) 5230 { 5231 case 0: rv = &(s->flag);break; 5232 case 1: rv = &(s->bcast_id);break; 5233 case 2: rv = &(s->chain_last);break; 5234 default: rv = NULL; break; 5235 } 5236 return rv; 5237 } 5238 5239 #ifdef CPRIMOD_SUPPORT 5240 static void* 5241 __cint_maddr__portmod_cpri_axc_frame_info_t(void* p, int mnum, cint_struct_type_t* parent) 5242 { 5243 void* rv; 5244 portmod_cpri_axc_frame_info_t* s = (portmod_cpri_axc_frame_info_t*) p; 5245 switch(mnum) 5246 { 5247 case 0: rv = &(s->start_bit);break; 5248 case 1: rv = &(s->num_bits);break; 5249 case 2: rv = &(s->container_info);break; 5250 case 3: rv = &(s->roe_payload_info);break; 5251 case 4: rv = &(s->encap_data_info);break; 5252 default: rv = NULL; break; 5253 } 5254 return rv; 5255 } 5256 5257 #endif /* CPRIMOD_SUPPORT */ 5258 #ifdef CPRIMOD_SUPPORT 5259 static void* 5260 __cint_maddr__portmod_tx_frame_tgen_config_t(void* p, int mnum, cint_struct_type_t* parent) 5261 { 5262 void* rv; 5263 portmod_tx_frame_tgen_config_t* s = (portmod_tx_frame_tgen_config_t*) p; 5264 switch(mnum) 5265 { 5266 case 0: rv = &(s->tx_tgen_hfn);break; 5267 case 1: rv = &(s->tx_tgen_bfn);break; 5268 case 2: rv = &(s->tx_gen_bfn_hfn_sel);break; 5269 case 3: rv = &(s->tx_tgen_ts_offset);break; 5270 default: rv = NULL; break; 5271 } 5272 return rv; 5273 } 5274 5275 #endif /* CPRIMOD_SUPPORT */ 5276 #ifdef CPRIMOD_SUPPORT 5277 static void* 5278 __cint_maddr__portmod_rsvd4_rx_flow_info_t(void* p, int mnum, cint_struct_type_t* parent) 5279 { 5280 void* rv; 5281 portmod_rsvd4_rx_flow_info_t* s = (portmod_rsvd4_rx_flow_info_t*) p; 5282 switch(mnum) 5283 { 5284 case 0: rv = &(s->axc_id);break; 5285 case 1: rv = &(s->mask);break; 5286 case 2: rv = &(s->match_data);break; 5287 case 3: rv = &(s->packet_size);break; 5288 case 4: rv = &(s->last_packet_size);break; 5289 case 5: rv = &(s->last_packet_num);break; 5290 case 6: rv = &(s->stuffing_cnt);break; 5291 case 7: rv = &(s->msg_ts_mode);break; 5292 case 8: rv = &(s->msg_ts_count);break; 5293 case 9: rv = &(s->frame_sync_mode);break; 5294 case 10: rv = &(s->master_frame_offset);break; 5295 case 11: rv = &(s->message_number_offset);break; 5296 case 12: rv = &(s->container_block_count);break; 5297 case 13: rv = &(s->queue_size);break; 5298 case 14: rv = &(s->priority);break; 5299 case 15: rv = &(s->pad_size);break; 5300 case 16: rv = &(s->extra_pad_size);break; 5301 case 17: rv = &(s->pad_enable);break; 5302 case 18: rv = &(s->control_location);break; 5303 case 19: rv = &(s->tsn_bitmap);break; 5304 default: rv = NULL; break; 5305 } 5306 return rv; 5307 } 5308 5309 #endif /* CPRIMOD_SUPPORT */ 5310 #ifdef CPRIMOD_SUPPORT 5311 static void* 5312 __cint_maddr__portmod_rsvd4_tx_flow_info_t(void* p, int mnum, cint_struct_type_t* parent) 5313 { 5314 void* rv; 5315 portmod_rsvd4_tx_flow_info_t* s = (portmod_rsvd4_tx_flow_info_t*) p; 5316 switch(mnum) 5317 { 5318 case 0: rv = &(s->axc_id);break; 5319 case 1: rv = &(s->packet_size);break; 5320 case 2: rv = &(s->last_packet_size);break; 5321 case 3: rv = &(s->last_packet_num);break; 5322 case 4: rv = &(s->stuffing_cnt);break; 5323 case 5: rv = &(s->msg_ts_mode);break; 5324 case 6: rv = &(s->msg_ts_count);break; 5325 case 7: rv = &(s->frame_sync_mode);break; 5326 case 8: rv = &(s->master_frame_offset);break; 5327 case 9: rv = &(s->message_number_offset);break; 5328 case 10: rv = &(s->container_block_count);break; 5329 case 11: rv = &(s->buffer_size);break; 5330 case 12: rv = &(s->cycle_size);break; 5331 case 13: rv = &(s->use_ts_dbm);break; 5332 case 14: rv = &(s->ts_dbm_profile_num);break; 5333 case 15: rv = &(s->num_active_slot);break; 5334 case 16: rv = &(s->msg_addr);break; 5335 case 17: rv = &(s->msg_type);break; 5336 case 18: rv = &(s->msg_ts_offset);break; 5337 case 19: rv = &(s->pad_size);break; 5338 case 20: rv = &(s->extra_pad_size);break; 5339 case 21: rv = &(s->pad_enable);break; 5340 case 22: rv = &(s->control_location);break; 5341 default: rv = NULL; break; 5342 } 5343 return rv; 5344 } 5345 5346 #endif /* CPRIMOD_SUPPORT */ 5347 static void* 5348 __cint_maddr__portmod_vcos_speed_config_t(void* p, int mnum, cint_struct_type_t* parent) 5349 { 5350 void* rv; 5351 portmod_vcos_speed_config_t* s = (portmod_vcos_speed_config_t*) p; 5352 switch(mnum) 5353 { 5354 case 0: rv = &(s->speed);break; 5355 case 1: rv = &(s->num_lanes);break; 5356 case 2: rv = &(s->ieee_mode);break; 5357 case 3: rv = &(s->higig_mode);break; 5358 case 4: rv = &(s->txpi_mode);break; 5359 case 5: rv = &(s->eth_of_mixed_mode);break; 5360 case 6: rv = &(s->port_type);break; 5361 default: rv = NULL; break; 5362 } 5363 return rv; 5364 } 5365 5366 static void* 5367 __cint_maddr__portmod_dual_vcos_t(void* p, int mnum, cint_struct_type_t* parent) 5368 { 5369 void* rv; 5370 portmod_dual_vcos_t* s = (portmod_dual_vcos_t*) p; 5371 switch(mnum) 5372 { 5373 case 0: rv = &(s->vco_0);break; 5374 case 1: rv = &(s->vco_1);break; 5375 default: rv = NULL; break; 5376 } 5377 return rv; 5378 } 5379 5380 #ifdef CPRIMOD_SUPPORT 5381 static void* 5382 __cint_maddr__portmod_cpri_slow_hdlc_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 5383 { 5384 void* rv; 5385 portmod_cpri_slow_hdlc_config_info_t* s = (portmod_cpri_slow_hdlc_config_info_t*) p; 5386 switch(mnum) 5387 { 5388 case 0: rv = &(s->tx_crc_mode);break; 5389 case 1: rv = &(s->tx_flag_size);break; 5390 case 2: rv = &(s->tx_filling_flag_pattern);break; 5391 case 3: rv = &(s->crc_init_val);break; 5392 case 4: rv = &(s->use_fe_mac);break; 5393 case 5: rv = &(s->crc_byte_swap);break; 5394 case 6: rv = &(s->no_fcs_err_check);break; 5395 case 7: rv = &(s->cw_sel);break; 5396 case 8: rv = &(s->cw_size);break; 5397 case 9: rv = &(s->fcs_size);break; 5398 case 10: rv = &(s->runt_frame_drop);break; 5399 case 11: rv = &(s->long_frame_drop);break; 5400 case 12: rv = &(s->min_frame_size);break; 5401 case 13: rv = &(s->max_frame_size);break; 5402 case 14: rv = &(s->queue_num);break; 5403 case 15: rv = &(s->priority);break; 5404 case 16: rv = &(s->queue_size);break; 5405 case 17: rv = &(s->cycle_size);break; 5406 case 18: rv = &(s->buffer_size);break; 5407 default: rv = NULL; break; 5408 } 5409 return rv; 5410 } 5411 5412 #endif /* CPRIMOD_SUPPORT */ 5413 #ifdef CPRIMOD_SUPPORT 5414 static void* 5415 __cint_maddr__portmod_cpri_fast_eth_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 5416 { 5417 void* rv; 5418 portmod_cpri_fast_eth_config_info_t* s = (portmod_cpri_fast_eth_config_info_t*) p; 5419 switch(mnum) 5420 { 5421 case 0: rv = &(s->tx_crc_mode);break; 5422 case 1: rv = &(s->schan_start);break; 5423 case 2: rv = &(s->schan_size);break; 5424 case 3: rv = &(s->cw_sel);break; 5425 case 4: rv = &(s->cw_size);break; 5426 case 5: rv = &(s->min_packet_size);break; 5427 case 6: rv = &(s->max_packet_size);break; 5428 case 7: rv = &(s->min_packet_drop);break; 5429 case 8: rv = &(s->max_packet_drop);break; 5430 case 9: rv = &(s->strip_crc);break; 5431 case 10: rv = &(s->min_ipg);break; 5432 case 11: rv = &(s->queue_num);break; 5433 case 12: rv = &(s->priority);break; 5434 case 13: rv = &(s->queue_size);break; 5435 case 14: rv = &(s->cycle_size);break; 5436 case 15: rv = &(s->buffer_size);break; 5437 case 16: rv = &(s->no_fcs_err_check);break; 5438 default: rv = NULL; break; 5439 } 5440 return rv; 5441 } 5442 5443 #endif /* CPRIMOD_SUPPORT */ 5444 #ifdef CPRIMOD_SUPPORT 5445 static void* 5446 __cint_maddr__portmod_cpri_rx_vsd_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 5447 { 5448 void* rv; 5449 portmod_cpri_rx_vsd_config_info_t* s = (portmod_cpri_rx_vsd_config_info_t*) p; 5450 switch(mnum) 5451 { 5452 case 0: rv = &(s->subchan_start);break; 5453 case 1: rv = &(s->subchan_size);break; 5454 case 2: rv = &(s->subchan_bytes);break; 5455 case 3: rv = &(s->subchan_steps);break; 5456 case 4: rv = &(s->flow_bytes);break; 5457 case 5: rv = &(s->queue_num);break; 5458 case 6: rv = &(s->rsvd_sector_mask);break; 5459 case 7: rv = &(s->priority);break; 5460 case 8: rv = &(s->queue_size);break; 5461 default: rv = NULL; break; 5462 } 5463 return rv; 5464 } 5465 5466 #endif /* CPRIMOD_SUPPORT */ 5467 #ifdef CPRIMOD_SUPPORT 5468 static void* 5469 __cint_maddr__portmod_cpri_tx_vsd_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 5470 { 5471 void* rv; 5472 portmod_cpri_tx_vsd_config_info_t* s = (portmod_cpri_tx_vsd_config_info_t*) p; 5473 switch(mnum) 5474 { 5475 case 0: rv = &(s->subchan_start);break; 5476 case 1: rv = &(s->subchan_size);break; 5477 case 2: rv = &(s->subchan_bytes);break; 5478 case 3: rv = &(s->subchan_steps);break; 5479 case 4: rv = &(s->flow_bytes);break; 5480 case 5: rv = &(s->queue_num);break; 5481 case 6: rv = &(s->rsvd_sector_mask);break; 5482 case 7: rv = &(s->buffer_size);break; 5483 case 8: rv = &(s->cycle_size);break; 5484 case 9: rv = &(s->byte_order_swap);break; 5485 default: rv = NULL; break; 5486 } 5487 return rv; 5488 } 5489 5490 #endif /* CPRIMOD_SUPPORT */ 5491 #ifdef CPRIMOD_SUPPORT 5492 static void* 5493 __cint_maddr__portmod_cpri_rx_vsd_raw_config_t(void* p, int mnum, cint_struct_type_t* parent) 5494 { 5495 void* rv; 5496 portmod_cpri_rx_vsd_raw_config_t* s = (portmod_cpri_rx_vsd_raw_config_t*) p; 5497 switch(mnum) 5498 { 5499 case 0: rv = &(s->schan_start);break; 5500 case 1: rv = &(s->schan_size);break; 5501 case 2: rv = &(s->cw_sel);break; 5502 case 3: rv = &(s->cw_size);break; 5503 case 4: rv = &(s->filter_mode);break; 5504 case 5: rv = &(s->hyper_frame_index);break; 5505 case 6: rv = &(s->hyper_frame_modulo);break; 5506 case 7: rv = &(s->match_offset);break; 5507 case 8: rv = &(s->match_value);break; 5508 case 9: rv = &(s->match_mask);break; 5509 case 10: rv = &(s->queue_num);break; 5510 case 11: rv = &(s->priority);break; 5511 case 12: rv = &(s->queue_size);break; 5512 default: rv = NULL; break; 5513 } 5514 return rv; 5515 } 5516 5517 #endif /* CPRIMOD_SUPPORT */ 5518 #ifdef CPRIMOD_SUPPORT 5519 static void* 5520 __cint_maddr__portmod_cpri_tx_vsd_raw_config_t(void* p, int mnum, cint_struct_type_t* parent) 5521 { 5522 void* rv; 5523 portmod_cpri_tx_vsd_raw_config_t* s = (portmod_cpri_tx_vsd_raw_config_t*) p; 5524 switch(mnum) 5525 { 5526 case 0: rv = &(s->schan_start);break; 5527 case 1: rv = &(s->schan_size);break; 5528 case 2: rv = &(s->cw_sel);break; 5529 case 3: rv = &(s->cw_size);break; 5530 case 4: rv = &(s->hyper_frame_index);break; 5531 case 5: rv = &(s->hyper_frame_modulo);break; 5532 case 6: rv = &(s->queue_num);break; 5533 case 7: rv = &(s->map_mode);break; 5534 case 8: rv = &(s->repeat_enable);break; 5535 case 9: rv = &(s->bfn0_filter_enable);break; 5536 case 10: rv = &(s->bfn1_filter_enable);break; 5537 case 11: rv = &(s->idle_value);break; 5538 case 12: rv = &(s->buffer_size);break; 5539 case 13: rv = &(s->cycle_size);break; 5540 default: rv = NULL; break; 5541 } 5542 return rv; 5543 } 5544 5545 #endif /* CPRIMOD_SUPPORT */ 5546 #ifdef CPRIMOD_SUPPORT 5547 static void* 5548 __cint_maddr__portmod_cpri_rx_brcm_rsvd5_config_t(void* p, int mnum, cint_struct_type_t* parent) 5549 { 5550 void* rv; 5551 portmod_cpri_rx_brcm_rsvd5_config_t* s = (portmod_cpri_rx_brcm_rsvd5_config_t*) p; 5552 switch(mnum) 5553 { 5554 case 0: rv = &(s->schan_start);break; 5555 case 1: rv = &(s->schan_size);break; 5556 case 2: rv = &(s->parity_disable);break; 5557 case 3: rv = &(s->queue_num);break; 5558 case 4: rv = &(s->priority);break; 5559 case 5: rv = &(s->queue_size);break; 5560 default: rv = NULL; break; 5561 } 5562 return rv; 5563 } 5564 5565 #endif /* CPRIMOD_SUPPORT */ 5566 #ifdef CPRIMOD_SUPPORT 5567 static void* 5568 __cint_maddr__portmod_cpri_tx_brcm_rsvd5_config_t(void* p, int mnum, cint_struct_type_t* parent) 5569 { 5570 void* rv; 5571 portmod_cpri_tx_brcm_rsvd5_config_t* s = (portmod_cpri_tx_brcm_rsvd5_config_t*) p; 5572 switch(mnum) 5573 { 5574 case 0: rv = &(s->schan_start);break; 5575 case 1: rv = &(s->schan_size);break; 5576 case 2: rv = &(s->crc_enable);break; 5577 case 3: rv = &(s->queue_num);break; 5578 case 4: rv = &(s->buffer_size);break; 5579 case 5: rv = &(s->cycle_size);break; 5580 default: rv = NULL; break; 5581 } 5582 return rv; 5583 } 5584 5585 #endif /* CPRIMOD_SUPPORT */ 5586 #ifdef CPRIMOD_SUPPORT 5587 static void* 5588 __cint_maddr__portmod_cpri_rx_gcw_config_t(void* p, int mnum, cint_struct_type_t* parent) 5589 { 5590 void* rv; 5591 portmod_cpri_rx_gcw_config_t* s = (portmod_cpri_rx_gcw_config_t*) p; 5592 switch(mnum) 5593 { 5594 case 0: rv = &(s->Ns);break; 5595 case 1: rv = &(s->Xs);break; 5596 case 2: rv = &(s->Y);break; 5597 case 3: rv = &(s->mask);break; 5598 case 4: rv = &(s->filter_mode);break; 5599 case 5: rv = &(s->hyper_frame_index);break; 5600 case 6: rv = &(s->hyper_frame_modulo);break; 5601 case 7: rv = &(s->match_mask);break; 5602 case 8: rv = &(s->match_value);break; 5603 default: rv = NULL; break; 5604 } 5605 return rv; 5606 } 5607 5608 #endif /* CPRIMOD_SUPPORT */ 5609 #ifdef CPRIMOD_SUPPORT 5610 static void* 5611 __cint_maddr__portmod_cpri_tx_gcw_config_t(void* p, int mnum, cint_struct_type_t* parent) 5612 { 5613 void* rv; 5614 portmod_cpri_tx_gcw_config_t* s = (portmod_cpri_tx_gcw_config_t*) p; 5615 switch(mnum) 5616 { 5617 case 0: rv = &(s->Ns);break; 5618 case 1: rv = &(s->Xs);break; 5619 case 2: rv = &(s->Y);break; 5620 case 3: rv = &(s->mask);break; 5621 case 4: rv = &(s->hyper_frame_index);break; 5622 case 5: rv = &(s->hyper_frame_modulo);break; 5623 case 6: rv = &(s->repeat_enable);break; 5624 case 7: rv = &(s->bfn0_filter_enable);break; 5625 case 8: rv = &(s->bfn1_filter_enable);break; 5626 default: rv = NULL; break; 5627 } 5628 return rv; 5629 } 5630 5631 #endif /* CPRIMOD_SUPPORT */ 5632 static void* 5633 __cint_maddr__portmod_control_flow_config_t(void* p, int mnum, cint_struct_type_t* parent) 5634 { 5635 void* rv; 5636 portmod_control_flow_config_t* s = (portmod_control_flow_config_t*) p; 5637 switch(mnum) 5638 { 5639 case 0: rv = &(s->match_mask);break; 5640 case 1: rv = &(s->match_data);break; 5641 case 2: rv = &(s->proc_type);break; 5642 case 3: rv = &(s->queue_num);break; 5643 case 4: rv = &(s->sync_profile);break; 5644 case 5: rv = &(s->sync_enable);break; 5645 case 6: rv = &(s->priority);break; 5646 case 7: rv = &(s->queue_size);break; 5647 default: rv = NULL; break; 5648 } 5649 return rv; 5650 } 5651 5652 static void* 5653 __cint_maddr__portmod_sync_profile_entry_t(void* p, int mnum, cint_struct_type_t* parent) 5654 { 5655 void* rv; 5656 portmod_sync_profile_entry_t* s = (portmod_sync_profile_entry_t*) p; 5657 switch(mnum) 5658 { 5659 case 0: rv = &(s->count_cycle);break; 5660 case 1: rv = &(s->message_offset);break; 5661 case 2: rv = &(s->master_frame_offset);break; 5662 default: rv = NULL; break; 5663 } 5664 return rv; 5665 } 5666 5667 #ifdef CPRIMOD_SUPPORT 5668 static void* 5669 __cint_maddr__portmod_rsvd4_tx_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 5670 { 5671 void* rv; 5672 portmod_rsvd4_tx_config_info_t* s = (portmod_rsvd4_tx_config_info_t*) p; 5673 switch(mnum) 5674 { 5675 case 0: rv = &(s->proc_type);break; 5676 case 1: rv = &(s->queue_num);break; 5677 case 2: rv = &(s->queue_size);break; 5678 case 3: rv = &(s->cycle_size);break; 5679 case 4: rv = &(s->crc_mode);break; 5680 default: rv = NULL; break; 5681 } 5682 return rv; 5683 } 5684 5685 #endif /* CPRIMOD_SUPPORT */ 5686 static void* 5687 __cint_maddr__portmod_txpi_override_t(void* p, int mnum, cint_struct_type_t* parent) 5688 { 5689 void* rv; 5690 portmod_txpi_override_t* s = (portmod_txpi_override_t*) p; 5691 switch(mnum) 5692 { 5693 case 0: rv = &(s->enable);break; 5694 case 1: rv = &(s->value);break; 5695 default: rv = NULL; break; 5696 } 5697 return rv; 5698 } 5699 5700 static void* 5701 __cint_maddr__portmod_pm8x50_capability_t(void* p, int mnum, cint_struct_type_t* parent) 5702 { 5703 void* rv; 5704 portmod_pm8x50_capability_t* s = (portmod_pm8x50_capability_t*) p; 5705 switch(mnum) 5706 { 5707 case 0: rv = &(s->num_lanes);break; 5708 case 1: rv = &(s->num_cores);break; 5709 case 2: rv = &(s->num_plls);break; 5710 case 3: rv = &(s->num_vcos);break; 5711 case 4: rv = &(s->vcos);break; 5712 default: rv = NULL; break; 5713 } 5714 return rv; 5715 } 5716 5717 static void* 5718 __cint_maddr__portmod_pm_specific_capability_t(void* p, int mnum, cint_struct_type_t* parent) 5719 { 5720 void* rv; 5721 portmod_pm_specific_capability_t* s = (portmod_pm_specific_capability_t*) p; 5722 switch(mnum) 5723 { 5724 case 0: rv = &(s->pm8x50_cap);break; 5725 default: rv = NULL; break; 5726 } 5727 return rv; 5728 } 5729 5730 static void* 5731 __cint_maddr__portmod_pm_capability_t(void* p, int mnum, cint_struct_type_t* parent) 5732 { 5733 void* rv; 5734 portmod_pm_capability_t* s = (portmod_pm_capability_t*) p; 5735 switch(mnum) 5736 { 5737 case 0: rv = &(s->type);break; 5738 case 1: rv = &(s->pm_capability);break; 5739 default: rv = NULL; break; 5740 } 5741 return rv; 5742 } 5743 5744 static void* 5745 __cint_maddr__portmod_pm_vco_setting_t(void* p, int mnum, cint_struct_type_t* parent) 5746 { 5747 void* rv; 5748 portmod_pm_vco_setting_t* s = (portmod_pm_vco_setting_t*) p; 5749 switch(mnum) 5750 { 5751 case 0: rv = &(s->num_speeds);break; 5752 case 1: rv = &(s->speed_config_list);break; 5753 case 2: rv = &(s->port_starting_lane_list);break; 5754 case 3: rv = &(s->speed_for_pcs_bypass_port);break; 5755 case 4: rv = &(s->tvco);break; 5756 case 5: rv = &(s->ovco);break; 5757 case 6: rv = &(s->is_tvco_new);break; 5758 case 7: rv = &(s->is_ovco_new);break; 5759 default: rv = NULL; break; 5760 } 5761 return rv; 5762 } 5763 5764 static void* 5765 __cint_maddr__portmod_cpri_port_intr_info_t(void* p, int mnum, cint_struct_type_t* parent) 5766 { 5767 void* rv; 5768 portmod_cpri_port_intr_info_t* s = (portmod_cpri_port_intr_info_t*) p; 5769 switch(mnum) 5770 { 5771 case 0: rv = &(s->cpri_intr_type);break; 5772 case 1: rv = &(s->axc_id);break; 5773 case 2: rv = &(s->queue_num);break; 5774 case 3: rv = &(s->data);break; 5775 case 4: rv = &(s->data64);break; 5776 default: rv = NULL; break; 5777 } 5778 return rv; 5779 } 5780 5781 static void* 5782 __cint_maddr__portmod_port_synce_clk_ctrl_t(void* p, int mnum, cint_struct_type_t* parent) 5783 { 5784 void* rv; 5785 portmod_port_synce_clk_ctrl_t* s = (portmod_port_synce_clk_ctrl_t*) p; 5786 switch(mnum) 5787 { 5788 case 0: rv = &(s->stg0_mode);break; 5789 case 1: rv = &(s->stg1_mode);break; 5790 case 2: rv = &(s->sdm_val);break; 5791 default: rv = NULL; break; 5792 } 5793 return rv; 5794 } 5795 5796 #ifdef CPRIMOD_SUPPORT 5797 static void* 5798 __cint_maddr__portmod_cpri_rx_agnostic_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 5799 { 5800 void* rv; 5801 portmod_cpri_rx_agnostic_config_info_t* s = (portmod_cpri_rx_agnostic_config_info_t*) p; 5802 switch(mnum) 5803 { 5804 case 0: rv = &(s->sync_mode);break; 5805 case 1: rv = &(s->basic_frame_offset);break; 5806 case 2: rv = &(s->hyper_frame_offset);break; 5807 case 3: rv = &(s->radio_frame_offset);break; 5808 case 4: rv = &(s->payload_multiple);break; 5809 case 5: rv = &(s->pres_mod_count);break; 5810 case 6: rv = &(s->ordering_info_option);break; 5811 default: rv = NULL; break; 5812 } 5813 return rv; 5814 } 5815 5816 #endif /* CPRIMOD_SUPPORT */ 5817 #ifdef CPRIMOD_SUPPORT 5818 static void* 5819 __cint_maddr__portmod_cpri_tx_agnostic_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 5820 { 5821 void* rv; 5822 portmod_cpri_tx_agnostic_config_info_t* s = (portmod_cpri_tx_agnostic_config_info_t*) p; 5823 switch(mnum) 5824 { 5825 case 0: rv = &(s->sync_mode);break; 5826 case 1: rv = &(s->basic_frame_offset);break; 5827 case 2: rv = &(s->hyper_frame_offset);break; 5828 case 3: rv = &(s->radio_frame_offset);break; 5829 case 4: rv = &(s->payload_multiple);break; 5830 case 5: rv = &(s->queue_mod_count);break; 5831 case 6: rv = &(s->pres_mod_count);break; 5832 case 7: rv = &(s->pres_mod_offset);break; 5833 case 8: rv = &(s->ordering_info_option);break; 5834 default: rv = NULL; break; 5835 } 5836 return rv; 5837 } 5838 5839 #endif /* CPRIMOD_SUPPORT */ 5840 #ifdef CPRIMOD_SUPPORT 5841 static void* 5842 __cint_maddr__portmod_fec_timestamp_config_t(void* p, int mnum, cint_struct_type_t* parent) 5843 { 5844 void* rv; 5845 portmod_fec_timestamp_config_t* s = (portmod_fec_timestamp_config_t*) p; 5846 switch(mnum) 5847 { 5848 case 0: rv = &(s->enable);break; 5849 case 1: rv = &(s->fec_fifo_ts_source_select);break; 5850 case 2: rv = &(s->fec_cmic_ts_source_select);break; 5851 case 3: rv = &(s->control_bit_offset_0);break; 5852 case 4: rv = &(s->control_bit_offset_1);break; 5853 case 5: rv = &(s->control_bit_offset_2);break; 5854 case 6: rv = &(s->control_bit_offset_3);break; 5855 default: rv = NULL; break; 5856 } 5857 return rv; 5858 } 5859 5860 #endif /* CPRIMOD_SUPPORT */ 5861 static void* 5862 __cint_maddr__portmod_ecc_intr_info_t(void* p, int mnum, cint_struct_type_t* parent) 5863 { 5864 void* rv; 5865 portmod_ecc_intr_info_t* s = (portmod_ecc_intr_info_t*) p; 5866 switch(mnum) 5867 { 5868 case 0: rv = &(s->port);break; 5869 case 1: rv = &(s->err_mem_info);break; 5870 case 2: rv = &(s->ecc_reg_info);break; 5871 case 3: rv = &(s->ecc_num_bits_err);break; 5872 case 4: rv = &(s->err_addr);break; 5873 case 5: rv = &(s->mem_str);break; 5874 default: rv = NULL; break; 5875 } 5876 return rv; 5877 } 5878 5879 static void* 5880 __cint_maddr__portmod_port_rlm_config_t(void* p, int mnum, cint_struct_type_t* parent) 5881 { 5882 void* rv; 5883 portmod_port_rlm_config_t* s = (portmod_port_rlm_config_t*) p; 5884 switch(mnum) 5885 { 5886 case 0: rv = &(s->is_initiator);break; 5887 case 1: rv = &(s->active_lane_bit_map);break; 5888 default: rv = NULL; break; 5889 } 5890 return rv; 5891 } 5892 5893 static void* 5894 __cint_maddr__portmod_port_rlm_status_t(void* p, int mnum, cint_struct_type_t* parent) 5895 { 5896 void* rv; 5897 portmod_port_rlm_status_t* s = (portmod_port_rlm_status_t*) p; 5898 switch(mnum) 5899 { 5900 case 0: rv = &(s->rlm_disabled);break; 5901 case 1: rv = &(s->rlm_busy);break; 5902 case 2: rv = &(s->rlm_done);break; 5903 case 3: rv = &(s->rlm_failed);break; 5904 case 4: rv = &(s->rlm_status_count);break; 5905 default: rv = NULL; break; 5906 } 5907 return rv; 5908 } 5909 5910 #ifdef CPRIMOD_SUPPORT 5911 static void* 5912 __cint_maddr__portmod_cpri_rx_tunnel_mode_config_t(void* p, int mnum, cint_struct_type_t* parent) 5913 { 5914 void* rv; 5915 portmod_cpri_rx_tunnel_mode_config_t* s = (portmod_cpri_rx_tunnel_mode_config_t*) p; 5916 switch(mnum) 5917 { 5918 case 0: rv = &(s->payload_size);break; 5919 case 1: rv = &(s->pres_mod_count);break; 5920 case 2: rv = &(s->ordering_info_option);break; 5921 default: rv = NULL; break; 5922 } 5923 return rv; 5924 } 5925 5926 #endif /* CPRIMOD_SUPPORT */ 5927 #ifdef CPRIMOD_SUPPORT 5928 static void* 5929 __cint_maddr__portmod_cpri_tx_tunnel_mode_config_t(void* p, int mnum, cint_struct_type_t* parent) 5930 { 5931 void* rv; 5932 portmod_cpri_tx_tunnel_mode_config_t* s = (portmod_cpri_tx_tunnel_mode_config_t*) p; 5933 switch(mnum) 5934 { 5935 case 0: rv = &(s->payload_size);break; 5936 case 1: rv = &(s->queue_mod_count);break; 5937 case 2: rv = &(s->pres_mod_count);break; 5938 case 3: rv = &(s->pres_mod_offset);break; 5939 case 4: rv = &(s->ordering_info_option);break; 5940 default: rv = NULL; break; 5941 } 5942 return rv; 5943 } 5944 5945 #endif /* CPRIMOD_SUPPORT */ 5946 #ifdef CPRIMOD_SUPPORT 5947 static void* 5948 __cint_maddr__portmod_rsvd4_rx_agnostic_config_t(void* p, int mnum, cint_struct_type_t* parent) 5949 { 5950 void* rv; 5951 portmod_rsvd4_rx_agnostic_config_t* s = (portmod_rsvd4_rx_agnostic_config_t*) p; 5952 switch(mnum) 5953 { 5954 case 0: rv = &(s->frame_sync_mode);break; 5955 case 1: rv = &(s->master_frame_offset);break; 5956 case 2: rv = &(s->message_group_number);break; 5957 case 3: rv = &(s->payload_multiple);break; 5958 case 4: rv = &(s->pres_mod_count);break; 5959 case 5: rv = &(s->ordering_info_option);break; 5960 default: rv = NULL; break; 5961 } 5962 return rv; 5963 } 5964 5965 #endif /* CPRIMOD_SUPPORT */ 5966 #ifdef CPRIMOD_SUPPORT 5967 static void* 5968 __cint_maddr__portmod_rsvd4_tx_agnostic_config_t(void* p, int mnum, cint_struct_type_t* parent) 5969 { 5970 void* rv; 5971 portmod_rsvd4_tx_agnostic_config_t* s = (portmod_rsvd4_tx_agnostic_config_t*) p; 5972 switch(mnum) 5973 { 5974 case 0: rv = &(s->frame_sync_mode);break; 5975 case 1: rv = &(s->master_frame_offset);break; 5976 case 2: rv = &(s->message_group_number);break; 5977 case 3: rv = &(s->payload_multiple);break; 5978 case 4: rv = &(s->queue_mod_count);break; 5979 case 5: rv = &(s->pres_mod_count);break; 5980 case 6: rv = &(s->pres_mod_offset);break; 5981 case 7: rv = &(s->ordering_info_option);break; 5982 default: rv = NULL; break; 5983 } 5984 return rv; 5985 } 5986 5987 #endif /* CPRIMOD_SUPPORT */ 5988 #ifdef CPRIMOD_SUPPORT 5989 static void* 5990 __cint_maddr__portmod_cpri_port_frame_config_t(void* p, int mnum, cint_struct_type_t* parent) 5991 { 5992 void* rv; 5993 portmod_cpri_port_frame_config_t* s = (portmod_cpri_port_frame_config_t*) p; 5994 switch(mnum) 5995 { 5996 case 0: rv = &(s->frame_type);break; 5997 case 1: rv = &(s->decap_primary_key);break; 5998 case 2: rv = &(s->decap_secondary_key);break; 5999 default: rv = NULL; break; 6000 } 6001 return rv; 6002 } 6003 6004 #endif /* CPRIMOD_SUPPORT */ 6005 6006 static cint_parameter_desc_t __cint_struct_members__portmod_default_user_access_t[] = 6007 { 6008 {"int", "unit", 0, 0}, 6009 {"int", "blk_id", 0, 0}, 6010 {"sal_mutex_t", "mutex", 0, 0}, 6011 {"uint32", "flags", 0, 0}, 6012 { NULL } 6013 }; 6014 6015 static cint_parameter_desc_t __cint_struct_members__portmod_pm4x10q_user_data_t[] = 6016 { 6017 {"phymod_access_t", "pm4x10_access", 0, 0}, 6018 {"portmod_default_user_access_t", "qsgmiie_user_data", 0, 0}, 6019 { NULL } 6020 }; 6021 6022 static cint_parameter_desc_t __cint_struct_members__portmod_fifo_status_t[] = 6023 { 6024 {"uint32", "timestamps_in_fifo", 0, 0}, 6025 {"uint32", "timestamps_in_fifo_hi", 0, 0}, 6026 {"uint32", "sequence_id", 0, 0}, 6027 {"uint32", "timestamp_sub_nanosec", 0, 0}, 6028 { NULL } 6029 }; 6030 6031 static cint_parameter_desc_t __cint_struct_members__portmod_pfc_config_t[] = 6032 { 6033 {"uint32", "type", 0, 0}, 6034 {"uint32", "opcode", 0, 0}, 6035 {"uint32", "classes", 0, 0}, 6036 {"uint32", "da_oui", 0, 0}, 6037 {"uint32", "da_nonoui", 0, 0}, 6038 {"uint32", "rxpass", 0, 0}, 6039 { NULL } 6040 }; 6041 6042 static cint_parameter_desc_t __cint_struct_members__portmod_eee_t[] = 6043 { 6044 {"uint32", "enable", 0, 0}, 6045 {"uint32", "tx_idle_time", 0, 0}, 6046 {"uint32", "tx_wake_time", 0, 0}, 6047 { NULL } 6048 }; 6049 6050 static cint_parameter_desc_t __cint_struct_members__portmod_eee_clock_t[] = 6051 { 6052 {"uint32", "clock_gate", 0, 0}, 6053 {"uint32", "clock_count", 0, 0}, 6054 {"uint32", "timer_pulse", 0, 0}, 6055 { NULL } 6056 }; 6057 6058 static cint_parameter_desc_t __cint_struct_members__portmod_vlan_tag_t[] = 6059 { 6060 {"int", "inner_vlan_tag", 0, 0}, 6061 {"int", "outer_vlan_tag", 0, 0}, 6062 { NULL } 6063 }; 6064 6065 static cint_parameter_desc_t __cint_struct_members__portmod_rx_control_t[] = 6066 { 6067 {"uint32", "flags", 0, 0}, 6068 {"uint32", "pass_control_frames", 0, 0}, 6069 {"uint32", "pass_pfc_frames", 0, 0}, 6070 {"uint32", "pass_pause_frames", 0, 0}, 6071 { NULL } 6072 }; 6073 6074 static cint_parameter_desc_t __cint_struct_members__portmod_multi_get_t[] = 6075 { 6076 {"uint32", "flags", 0, 0}, 6077 {"uint32", "dev_addr", 0, 0}, 6078 {"uint32", "offset", 0, 0}, 6079 {"uint32", "max_size", 0, 0}, 6080 {"unsigned char", "data", 1, 0}, 6081 {"uint32", "actual_size", 1, 0}, 6082 { NULL } 6083 }; 6084 6085 static cint_parameter_desc_t __cint_struct_members__portmod_portphy_ability_t[] = 6086 { 6087 {"portmod_port_mode_t", "cur_mode", 0, 0}, 6088 {"portmod_port_mode_t", "speed_half_duplex", 0, 0}, 6089 {"portmod_port_mode_t", "speed_full_duplex", 0, 0}, 6090 {"portmod_port_mode_t", "pause", 0, 0}, 6091 {"portmod_port_mode_t", "interface", 0, 0}, 6092 {"portmod_port_mode_t", "medium", 0, 0}, 6093 {"portmod_port_mode_t", "loopback", 0, 0}, 6094 {"portmod_port_mode_t", "flags", 0, 0}, 6095 {"portmod_port_mode_t", "eee", 0, 0}, 6096 {"portmod_port_mode_t", "fcmap", 0, 0}, 6097 {"portmod_pa_encap_t", "encap", 0, 0}, 6098 { NULL } 6099 }; 6100 6101 static cint_parameter_desc_t __cint_struct_members__portmod_pdata_t[] = 6102 { 6103 {"uint32_t", "data", 0, 0}, 6104 {"uint32_t", "enable", 0, 0}, 6105 {"portmod_port_if_t", "pif", 0, 0}, 6106 {"portmod_port_ability_t", "ability", 1, 0}, 6107 { NULL } 6108 }; 6109 6110 static cint_parameter_desc_t __cint_struct_members__portmod_port_mode_info_t[] = 6111 { 6112 {"portmod_core_port_mode_t", "cur_mode", 0, 0}, 6113 {"int", "lanes", 0, 0}, 6114 {"int", "port_index", 0, 0}, 6115 { NULL } 6116 }; 6117 6118 static cint_parameter_desc_t __cint_struct_members__portmod_port_diag_info_t[] = 6119 { 6120 {"int", "original_port", 0, 0}, 6121 {"soc_port_if_t", "interface", 0, 0}, 6122 {"int", "pm_id", 0, 0}, 6123 {"portmod_pbmp_t", "phys", 0, 0}, 6124 {"int", "sub_phy", 0, 0}, 6125 {"int", "medium", 0, 0}, 6126 {"portmod_port_mode_info_t", "core_mode", 0, 0}, 6127 {"phymod_polarity_t", "polarity", 0, 0}, 6128 {"portmod_fec_t", "fec", 0, 0}, 6129 { NULL } 6130 }; 6131 6132 static cint_parameter_desc_t __cint_struct_members__portmod_pm_core_info_t[] = 6133 { 6134 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6135 {"phymod_lane_map_t", "lane_map", 0, 0}, 6136 {"int", "nof_phys", 0, 0}, 6137 { NULL } 6138 }; 6139 6140 static cint_parameter_desc_t __cint_struct_members__portmod_pm_diag_info_t[] = 6141 { 6142 {"portmod_dispatch_type_t", "type", 0, 0}, 6143 {"portmod_pm_core_info_t", "core_info", 0, 0}, 6144 {"portmod_pbmp_t", "phys", 0, 0}, 6145 {"soc_pbmp_t", "ports", 0, 0}, 6146 {"uint16", "serdes_id0", 0, 0}, 6147 {"uint16", "phy_id0", 0, 0}, 6148 {"uint16", "phy_id1", 0, 0}, 6149 {"char", "name", 0, PORTMOD_TSCE_LANE_NAME_LEN}, 6150 { NULL } 6151 }; 6152 6153 static cint_parameter_desc_t __cint_struct_members__portmod_port_ts_adjust_t[] = 6154 { 6155 {"int", "speed", 0, 0}, 6156 {"uint32", "osts_adjust", 0, 0}, 6157 {"uint32", "tsts_adjust", 0, 0}, 6158 { NULL } 6159 }; 6160 6161 static cint_parameter_desc_t __cint_struct_members__portmod_port_init_config_t[] = 6162 { 6163 {"phymod_phy_reset_t", "phy_reset_config", 0, 0}, 6164 {"phymod_pattern_t", "pattern", 0, 0}, 6165 {"int", "cx4_10g", 0, 0}, 6166 {"int", "pdetect1000x", 0, 0}, 6167 {"phymod_an_mode_type_t", "an_mode", 0, 0}, 6168 {"int", "an_master_lane", 0, 0}, 6169 {"int", "an_cl72", 0, 0}, 6170 {"int", "fs_cl72", 0, 0}, 6171 {"int", "an_fec", 0, 0}, 6172 {"int", "serdes_fec_enable", 0, 0}, 6173 {"int", "sgmii_mstr", 0, 0}, 6174 {"int", "serdes_driver_current", 0, 0}, 6175 {"int", "serdes_1000x_at_6250_vco", 0, 0}, 6176 {"int", "serdes_1000x_at_12500_vco", 0, 0}, 6177 {"int", "serdes_1000x_at_25g_vco", 0, 0}, 6178 {"int", "serdes_10g_at_25g_vco", 0, 0}, 6179 {"int", "pll_divider_req", 0, 0}, 6180 {"int", "rxaui_mode", 0, 0}, 6181 {"int", "port_fallback_lane", 0, 0}, 6182 {"int", "tx_params_user_flag", 0, PHYMOD_MAX_LANES_PER_PORT}, 6183 {"phymod_tx_t", "tx_params", 0, PHYMOD_MAX_LANES_PER_PORT}, 6184 {"int", "an_cl37", 0, 0}, 6185 {"int", "cl37_sgmii_war", 0, 0}, 6186 {"int", "cl37_sgmii_cnt", 0, 0}, 6187 {"int", "cl37_sgmii_RESTART_CNT", 0, 0}, 6188 {"int", "an_cl73", 0, 0}, 6189 {"int", "is_hg", 0, 0}, 6190 {"int", "ext_phy_tx_params_user_flag", 0, PHYMOD_MAX_LANES_PER_PORT}, 6191 {"phymod_tx_t", "ext_phy_tx_params", 0, PHYMOD_MAX_LANES_PER_PORT}, 6192 {"phymod_polarity_t", "polarity", 0, PORTMOD_MAX_CORES_PER_PORT}, 6193 {"uint8", "polarity_overwrite", 0, 0}, 6194 {"phymod_lane_map_t", "lane_map", 0, PORTMOD_MAX_CORES_PER_PORT}, 6195 {"uint8", "lane_map_overwrite", 0, 0}, 6196 {"phymod_firmware_load_method_t", "fw_load_method", 0, PORTMOD_MAX_CORES_PER_PORT}, 6197 {"uint8", "fw_load_method_overwrite", 0, 0}, 6198 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6199 {"uint8", "ref_clk_overwrite", 0, 0}, 6200 {"portmod_port_mode_aux_info_t", "port_mode_aux_info", 0, 0}, 6201 {"portmod_port_ts_adjust_t", "port_ts_adjust", 0, PORTMOD_TS_ADJUST_NUM}, 6202 {"uint32", "txpi_mode", 0, 0}, 6203 {"uint32", "txpi_sdm_scheme", 0, 0}, 6204 {"int", "roe_stuffing_bit", 0, 0}, 6205 {"int", "roe_reserved_bit", 0, 0}, 6206 {"portmod_cpm_core_mode_t", "cpm_core_mode", 0, 0}, 6207 {"portmod_qtc_mode_t", "qtc_mode", 0, 0}, 6208 {"int", "parity_enable", 0, 0}, 6209 { NULL } 6210 }; 6211 6212 static cint_parameter_desc_t __cint_struct_members__portmod_port_interface_config_t[] = 6213 { 6214 {"soc_port_if_t", "interface", 0, 0}, 6215 {"soc_port_if_t", "line_interface", 0, 0}, 6216 {"soc_port_if_t", "serdes_interface", 0, 0}, 6217 {"uint32", "interface_modes", 0, 0}, 6218 {"uint32", "flags", 0, 0}, 6219 {"uint32", "port_refclk_int", 0, 0}, 6220 {"int", "port_num_lanes", 0, 0}, 6221 {"int", "speed", 0, 0}, 6222 {"int", "max_speed", 0, 0}, 6223 {"portmod_encap_t", "encap_mode", 0, 0}, 6224 {"int", "pll_divider_req", 0, 0}, 6225 {"int", "port_op_mode", 0, 0}, 6226 {"uint32", "serdes_scrambler_seed", 0, 0}, 6227 {"uint32", "serdes_scrambler_enable", 0, 0}, 6228 { NULL } 6229 }; 6230 6231 static cint_parameter_desc_t __cint_struct_members__portmod_port_speed_ability_t[] = 6232 { 6233 {"uint32", "speed", 0, 0}, 6234 {"uint32", "num_lanes", 0, 0}, 6235 {"portmod_fec_t", "fec_type", 0, 0}, 6236 {"portmod_port_medium_t", "medium", 0, 0}, 6237 {"portmod_port_phy_pause_t", "pause", 0, 0}, 6238 {"portmod_port_phy_channel_t", "channel", 0, 0}, 6239 {"portmod_port_phy_control_autoneg_mode_t", "an_mode", 0, 0}, 6240 { NULL } 6241 }; 6242 6243 static cint_parameter_desc_t __cint_struct_members__portmod_speed_config_t[] = 6244 { 6245 {"int", "speed", 0, 0}, 6246 {"int", "num_lane", 0, 0}, 6247 {"portmod_fec_t", "fec", 0, 0}, 6248 {"int", "link_training", 0, 0}, 6249 {"int", "lane_config", 0, 0}, 6250 {"uint32", "flags", 0, 0}, 6251 { NULL } 6252 }; 6253 6254 static cint_parameter_desc_t __cint_struct_members__portmod_pm_identifier_t[] = 6255 { 6256 {"portmod_dispatch_type_t", "type", 0, 0}, 6257 {"int", "phy", 0, 0}, 6258 { NULL } 6259 }; 6260 6261 static cint_parameter_desc_t __cint_struct_members__portmod_port_add_info_t[] = 6262 { 6263 {"portmod_port_interface_config_t", "interface_config", 0, 0}, 6264 {"portmod_port_init_config_t", "init_config", 0, 0}, 6265 {"portmod_speed_config_t", "speed_config", 0, 0}, 6266 {"portmod_vco_type_t", "tvco", 0, 0}, 6267 {"portmod_vco_type_t", "ovco", 0, 0}, 6268 {"portmod_pbmp_t", "phys", 0, 0}, 6269 {"portmod_pbmp_t", "phy_ports", 0, 0}, 6270 {"int", "sub_phy", 0, 0}, 6271 {"uint8", "autoneg_en", 0, 0}, 6272 {"uint8", "link_training_en", 0, 0}, 6273 {"uint32", "flags", 0, 0}, 6274 {"uint32", "is_fabric_o_nif", 0, 0}, 6275 {"uint32", "ilkn_core_id", 0, 0}, 6276 {"uint32", "ilkn_port_is_over_fabric", 0, 0}, 6277 {"int", "ilkn_burst_max", 0, 0}, 6278 {"int", "ilkn_burst_min", 0, 0}, 6279 {"int", "ilkn_burst_short", 0, 0}, 6280 {"int", "ilkn_nof_segments", 0, 0}, 6281 {"int", "ilkn_metaframe_period", 0, 0}, 6282 {"uint32", "rx_retransmit", 0, 0}, 6283 {"uint32", "tx_retransmit", 0, 0}, 6284 {"phymod_operation_mode_t", "phy_op_mode", 0, 0}, 6285 {"phymod_datapath_t", "phy_op_datapath", 0, 0}, 6286 {"int", "ilkn_inb_cal_len_rx", 0, 0}, 6287 {"int", "ilkn_inb_cal_len_tx", 0, 0}, 6288 {"int", "ilkn_oob_cal_len_rx", 0, 0}, 6289 {"int", "ilkn_oob_cal_len_tx", 0, 0}, 6290 {"uint32", "reserved_channel_rx", 0, 0}, 6291 {"uint32", "reserved_channel_tx", 0, 0}, 6292 {"portmod_pbmp_t", "ilkn_lanes", 0, 0}, 6293 {"int", "nof_aggregated_pms", 0, 0}, 6294 {"portmod_pm_identifier_t", "controlled_pms", 0, PORTMOD_MAX_ILKN_AGGREGATED_PMS}, 6295 { NULL } 6296 }; 6297 6298 static cint_parameter_desc_t __cint_struct_members__portmod_dnx_fabric_create_info_t[] = 6299 { 6300 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6301 {"phymod_ref_clk_t", "com_clk", 0, 0}, 6302 {"phymod_access_t", "access", 0, 0}, 6303 {"phymod_lane_map_t", "lane_map", 0, 0}, 6304 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6305 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6306 {"phymod_polarity_t", "polarity", 0, 0}, 6307 {"int", "fmac_schan_id", 0, 0}, 6308 {"int", "fsrd_schan_id", 0, 0}, 6309 {"int", "fsrd_internal_quad", 0, 0}, 6310 {"int", "first_phy_offset", 0, 0}, 6311 {"int", "core_index", 0, 0}, 6312 {"int", "is_over_nif", 0, 0}, 6313 {"portmod_pm_identifier_t", "fabric_o_nif_pm", 0, 0}, 6314 { NULL } 6315 }; 6316 6317 static cint_parameter_desc_t __cint_struct_members__portmod_pm8x50_fabric_create_info_t[] = 6318 { 6319 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6320 {"phymod_access_t", "access", 0, 0}, 6321 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6322 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6323 {"phymod_polarity_t", "polarity", 0, 0}, 6324 {"int", "fmac_schan_id", 0, PORTMOD_NOF_FMACS_PER_PM8X50_FABRIC}, 6325 {"int", "fsrd_schan_id", 0, 0}, 6326 {"int", "first_phy_offset", 0, 0}, 6327 {"int", "core_index", 0, 0}, 6328 {"uint32", "force_single_pll", 0, 0}, 6329 {"uint32", "bypass_lanes_bitmap", 0, PORTMOD_NOF_WORDS_PER_PM8X50_FABRIC_LANES_BITMAP}, 6330 {"int", "is_rx_ctrl_bypass_supported", 0, 0}, 6331 { NULL } 6332 }; 6333 6334 static cint_parameter_desc_t __cint_struct_members__portmod_pm4x25_create_info_t[] = 6335 { 6336 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6337 {"phymod_access_t", "access", 0, 0}, 6338 {"phymod_lane_map_t", "lane_map", 0, 0}, 6339 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6340 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6341 {"phymod_polarity_t", "polarity", 0, 0}, 6342 {"uint8", "in_pm_12x10", 0, 0}, 6343 {"int", "core_num", 0, 0}, 6344 {"int", "core_num_int", 0, 0}, 6345 {"portmod_mac_soft_reset_f", "portmod_mac_soft_reset", 0, 0}, 6346 {"phymod_afe_pll_t", "afe_pll", 0, 0}, 6347 {"int", "rescal", 0, 0}, 6348 {"portmod_port_mode_aux_info_t", "port_mode_aux_info", 0, 0}, 6349 { NULL } 6350 }; 6351 6352 static cint_parameter_desc_t __cint_struct_members__portmod_pm4x10_create_info_t[] = 6353 { 6354 {"portmod_pbmp_t", "phy_ports", 0, 0}, 6355 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6356 {"phymod_access_t", "access", 0, 0}, 6357 {"phymod_lane_map_t", "lane_map", 0, 0}, 6358 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6359 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6360 {"phymod_polarity_t", "polarity", 0, 0}, 6361 {"uint8", "in_pm_12x10", 0, 0}, 6362 {"portmod_phy_external_reset_f", "portmod_phy_external_reset", 0, 0}, 6363 {"portmod_mac_soft_reset_f", "portmod_mac_soft_reset", 0, 0}, 6364 {"int", "core_num", 0, 0}, 6365 {"int", "core_num_int", 0, 0}, 6366 {"portmod_port_mode_aux_info_t", "port_mode_aux_info", 0, 0}, 6367 {"int", "rescal", 0, 0}, 6368 {"int", "is_pm4x10q", 0, 0}, 6369 { NULL } 6370 }; 6371 6372 static cint_parameter_desc_t __cint_struct_members__portmod_pm_qtc_create_info_t[] = 6373 { 6374 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6375 {"phymod_access_t", "access", 0, 0}, 6376 {"phymod_lane_map_t", "lane_map", 0, 0}, 6377 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6378 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6379 {"phymod_polarity_t", "polarity", 0, 0}, 6380 {"portmod_phy_external_reset_f", "portmod_phy_external_reset", 0, 0}, 6381 {"portmod_mac_soft_reset_f", "portmod_mac_soft_reset", 0, 0}, 6382 {"int", "core_num", 0, 0}, 6383 {"uint32", "core_clock_khz", 0, 0}, 6384 { NULL } 6385 }; 6386 6387 static cint_parameter_desc_t __cint_struct_members__portmod_pm_gphy_create_info_t[] = 6388 { 6389 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6390 {"phymod_access_t", "access", 0, 0}, 6391 {"phymod_lane_map_t", "lane_map", 0, 0}, 6392 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6393 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6394 {"phymod_polarity_t", "polarity", 0, 0}, 6395 {"portmod_phy_external_reset_f", "portmod_phy_external_reset", 0, 0}, 6396 {"portmod_mac_soft_reset_f", "portmod_mac_soft_reset", 0, 0}, 6397 {"int", "core_num", 0, 0}, 6398 { NULL } 6399 }; 6400 6401 static cint_parameter_desc_t __cint_struct_members__portmod_pm12x10_create_info_t[] = 6402 { 6403 {"portmod_pm4x10_create_info_t", "pm4x10_infos", 0, 3}, 6404 {"portmod_pm4x25_create_info_t", "pm4x25_info", 0, 0}, 6405 {"uint32", "flags", 0, 0}, 6406 {"int", "blk_id", 0, 0}, 6407 {"int", "refclk_source", 0, 0}, 6408 { NULL } 6409 }; 6410 6411 static cint_parameter_desc_t __cint_struct_members__portmod_pm4x10q_create_info_t[] = 6412 { 6413 {"portmod_pm4x10_create_info_t", "pm4x10_info", 0, 0}, 6414 {"uint32", "blk_id", 0, 0}, 6415 {"void", "qsgmii_user_acc", 1, 0}, 6416 {"uint32", "core_clock_khz", 0, 0}, 6417 { NULL } 6418 }; 6419 6420 static cint_parameter_desc_t __cint_struct_members__portmod_ilkn_os_create_info_t[] = 6421 { 6422 {"int", "nof_aggregated_pms", 0, 0}, 6423 {"portmod_pm_identifier_t", "controlled_pms", 1, 0}, 6424 {"int", "wm_high", 0, PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM}, 6425 {"int", "wm_low", 0, PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM}, 6426 {"uint32", "is_over_fabric", 0, 0}, 6427 {"uint32", "core_clock_khz", 0, 0}, 6428 {"portmod_ilkn_core_lane_map_callback_get_f", "ilkn_core_lane_map_get", 0, 0}, 6429 {"portmod_ilkn_pm_lane_map_callback_get_f", "ilkn_pm_lane_map_get", 0, 0}, 6430 {"uint32", "ilkn_block_index", 0, 0}, 6431 { NULL } 6432 }; 6433 6434 static cint_parameter_desc_t __cint_struct_members__portmod_pm4x2p5_create_info_t[] = 6435 { 6436 {"soc_pbmp_t", "phy_ports", 0, 0}, 6437 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6438 {"phymod_access_t", "access", 0, 0}, 6439 {"phymod_lane_map_t", "lane_map", 0, 0}, 6440 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6441 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6442 {"phymod_polarity_t", "polarity", 0, 0}, 6443 {"portmod_phy_external_reset_f", "portmod_phy_external_reset", 0, 0}, 6444 {"portmod_mac_soft_reset_f", "portmod_mac_soft_reset", 0, 0}, 6445 { NULL } 6446 }; 6447 6448 static cint_parameter_desc_t __cint_struct_members__portmod_pm8x50_create_info_t[] = 6449 { 6450 {"soc_pbmp_t", "phy_ports", 0, 0}, 6451 {"phymod_ref_clk_t", "ref_clk", 0, 0}, 6452 {"portmod_vco_type_t", "tvco", 0, 0}, 6453 {"portmod_vco_type_t", "ovco", 0, 0}, 6454 {"phymod_phy_access_t", "access", 0, 0}, 6455 {"phymod_lane_map_t", "lane_map", 0, 0}, 6456 {"phymod_firmware_load_method_t", "fw_load_method", 0, 0}, 6457 {"phymod_firmware_loader_f", "external_fw_loader", 0, 0}, 6458 {"phymod_polarity_t", "polarity", 0, 0}, 6459 {"portmod_phy_external_reset_f", "portmod_phy_external_reset", 0, 0}, 6460 {"portmod_mac_soft_reset_f", "portmod_mac_soft_reset", 0, 0}, 6461 {"int", "core_num", 0, 0}, 6462 {"phymod_afe_pll_t", "afe_pll", 0, 0}, 6463 {"int", "rescal", 0, 0}, 6464 {"int", "is_master_pm", 0, 0}, 6465 {"portmod_egress_buffer_reset_f", "portmod_egress_buffer_reset", 0, 0}, 6466 {"int", "allow_20p625g_tvco", 0, 0}, 6467 { NULL } 6468 }; 6469 6470 static cint_parameter_desc_t __cint_struct_members__portmod_pm4x10_qtc_create_info_t[] = 6471 { 6472 {"portmod_pm4x10_create_info_t", "pm4x10_info", 0, 0}, 6473 {"portmod_pm_qtc_create_info_t", "pm_qtc_info", 0, 0}, 6474 { NULL } 6475 }; 6476 6477 static cint_parameter_desc_t __cint_struct_members__portmod_pm_specific_create_info_t[] = 6478 { 6479 {"portmod_pm4x10_create_info_t", "pm4x10", 0, 0}, 6480 {"portmod_pm4x10q_create_info_t", "pm4x10q", 0, 0}, 6481 {"portmod_pm_qtc_create_info_t", "pm_qtc", 0, 0}, 6482 {"portmod_pm_gphy_create_info_t", "pm_gphy", 0, 0}, 6483 {"portmod_pm4x25_create_info_t", "pm4x25", 0, 0}, 6484 {"portmod_pm12x10_create_info_t", "pm12x10", 0, 0}, 6485 {"portmod_ilkn_os_create_info_t", "os_ilkn", 0, 0}, 6486 {"portmod_dnx_fabric_create_info_t", "dnx_fabric", 0, 0}, 6487 {"portmod_pm8x50_fabric_create_info_t", "pm8x50_fabric", 0, 0}, 6488 {"portmod_pm4x2p5_create_info_t", "pm4x2p5", 0, 0}, 6489 {"portmod_pm8x50_create_info_t", "pm8x50", 0, 0}, 6490 {"portmod_pm4x10_qtc_create_info_t", "pm4x10_qtc", 0, 0}, 6491 { NULL } 6492 }; 6493 6494 static cint_parameter_desc_t __cint_struct_members__portmod_remote_fault_control_t[] = 6495 { 6496 {"uint8", "enable", 0, 0}, 6497 {"uint8", "drop_tx_on_fault", 0, 0}, 6498 { NULL } 6499 }; 6500 6501 static cint_parameter_desc_t __cint_struct_members__portmod_local_fault_control_t[] = 6502 { 6503 {"uint8", "enable", 0, 0}, 6504 {"uint8", "drop_tx_on_fault", 0, 0}, 6505 { NULL } 6506 }; 6507 6508 static cint_parameter_desc_t __cint_struct_members__portmod_llfc_control_t[] = 6509 { 6510 {"uint8", "rx_enable", 0, 0}, 6511 {"uint8", "tx_enable", 0, 0}, 6512 {"uint8", "crc_ignore", 0, 0}, 6513 {"uint8", "in_ipg_only", 0, 0}, 6514 { NULL } 6515 }; 6516 6517 static cint_parameter_desc_t __cint_struct_members__portmod_pfc_control_t[] = 6518 { 6519 {"uint8", "rx_enable", 0, 0}, 6520 {"uint8", "tx_enable", 0, 0}, 6521 {"uint8", "stats_en", 0, 0}, 6522 {"uint8", "force_xon", 0, 0}, 6523 {"int", "refresh_timer", 0, 0}, 6524 {"int", "xoff_timer", 0, 0}, 6525 { NULL } 6526 }; 6527 6528 static cint_parameter_desc_t __cint_struct_members__portmod_pause_control_t[] = 6529 { 6530 {"uint8", "rx_enable", 0, 0}, 6531 {"uint8", "tx_enable", 0, 0}, 6532 {"int", "refresh_timer", 0, 0}, 6533 {"int", "xoff_timer", 0, 0}, 6534 { NULL } 6535 }; 6536 6537 static cint_parameter_desc_t __cint_struct_members__portmod_drain_cells_t[] = 6538 { 6539 {"int", "rx_pfc_en", 0, 0}, 6540 {"int", "llfc_en", 0, 0}, 6541 {"int", "rx_pause", 0, 0}, 6542 {"int", "tx_pause", 0, 0}, 6543 { NULL } 6544 }; 6545 6546 static cint_parameter_desc_t __cint_struct_members__portmod_pm_create_info_t[] = 6547 { 6548 {"portmod_dispatch_type_t", "type", 0, 0}, 6549 {"portmod_pbmp_t", "phys", 0, 0}, 6550 {"portmod_pm_specific_create_info_t", "pm_specific_info", 0, 0}, 6551 { NULL } 6552 }; 6553 6554 static cint_parameter_desc_t __cint_struct_members__portmod_access_get_params_t[] = 6555 { 6556 {"int", "phyn", 0, 0}, 6557 {"int", "sys_side", 0, 0}, 6558 {"int", "lane", 0, 0}, 6559 {"int", "apply_lane_mask", 0, 0}, 6560 { NULL } 6561 }; 6562 6563 static cint_parameter_desc_t __cint_struct_members__portmod_pm_instances_t[] = 6564 { 6565 {"portmod_dispatch_type_t", "type", 0, 0}, 6566 {"int", "instances", 0, 0}, 6567 { NULL } 6568 }; 6569 6570 static cint_parameter_desc_t __cint_struct_members__portmod_port_update_control_t[] = 6571 { 6572 {"int", "link_status", 0, 0}, 6573 {"uint32", "flags", 0, 0}, 6574 { NULL } 6575 }; 6576 6577 static cint_parameter_desc_t __cint_struct_members__portmod_lane_connection_t[] = 6578 { 6579 {"int", "core_index", 0, 0}, 6580 {"int", "lane_index", 0, 0}, 6581 { NULL } 6582 }; 6583 6584 static cint_parameter_desc_t __cint_struct_members__portmod_phy_core_info_t[] = 6585 { 6586 {"phymod_core_access_t", "core_access", 0, 0}, 6587 { NULL } 6588 }; 6589 6590 static cint_parameter_desc_t __cint_struct_members__portmod_xphy_lane_connection_t[] = 6591 { 6592 {"uint32", "xphy_id", 0, 0}, 6593 {"int", "ss_lane_mask", 0, 0}, 6594 {"int", "ls_lane_mask", 0, 0}, 6595 {"int", "rsvd1", 0, 0}, 6596 {"int", "rsvd2", 0, 0}, 6597 { NULL } 6598 }; 6599 6600 static cint_parameter_desc_t __cint_struct_members__portmod_port_higig_e2ecc_hdr_t[] = 6601 { 6602 {"uint32", "words", 0, 8}, 6603 { NULL } 6604 }; 6605 6606 static cint_parameter_desc_t __cint_struct_members__portmod_port_resources_t[] = 6607 { 6608 {"portmod_dispatch_type_t", "pm_type", 0, 0}, 6609 {"int", "speed", 0, 0}, 6610 {"int", "num_lane", 0, 0}, 6611 {"portmod_encap_t", "encap_mode", 0, 0}, 6612 {"uint32_t", "flag", 0, 0}, 6613 { NULL } 6614 }; 6615 6616 static cint_parameter_desc_t __cint_struct_members__portmod_link_recovery_t[] = 6617 { 6618 {"uint32", "state", 0, 0}, 6619 {"uint32", "enabled", 0, 0}, 6620 {"uint32", "tick_cnt", 0, 0}, 6621 { NULL } 6622 }; 6623 6624 static cint_parameter_desc_t __cint_struct_members__portmod_pmd_lane_config_t[] = 6625 { 6626 {"phymod_firmware_lane_config_t", "pmd_firmware_lane_config", 0, 0}, 6627 {"uint32_t", "pam4_channel_loss", 0, 0}, 6628 { NULL } 6629 }; 6630 6631 static cint_parameter_desc_t __cint_struct_members__portmod_sbus_bcast_config_t[] = 6632 { 6633 {"int", "flag", 0, 0}, 6634 {"int", "bcast_id", 0, 0}, 6635 {"int", "chain_last", 0, 0}, 6636 { NULL } 6637 }; 6638 6639 #ifdef CPRIMOD_SUPPORT 6640 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_axc_frame_info_t[] = 6641 { 6642 {"uint32", "start_bit", 0, 0}, 6643 {"uint32", "num_bits", 0, 0}, 6644 {"cprimod_cpri_container_config_t", "container_info", 0, 0}, 6645 {"cprimod_payload_size_info_t", "roe_payload_info", 0, 0}, 6646 {"cprimod_encap_decap_data_config_t", "encap_data_info", 0, 0}, 6647 { NULL } 6648 }; 6649 6650 #endif /* CPRIMOD_SUPPORT */ 6651 #ifdef CPRIMOD_SUPPORT 6652 static cint_parameter_desc_t __cint_struct_members__portmod_tx_frame_tgen_config_t[] = 6653 { 6654 {"uint32", "tx_tgen_hfn", 0, 0}, 6655 {"uint32", "tx_tgen_bfn", 0, 0}, 6656 {"cprimod_tgen_counter_select_t", "tx_gen_bfn_hfn_sel", 0, 0}, 6657 {"uint64", "tx_tgen_ts_offset", 0, 0}, 6658 { NULL } 6659 }; 6660 6661 #endif /* CPRIMOD_SUPPORT */ 6662 #ifdef CPRIMOD_SUPPORT 6663 static cint_parameter_desc_t __cint_struct_members__portmod_rsvd4_rx_flow_info_t[] = 6664 { 6665 {"uint32", "axc_id", 0, 0}, 6666 {"uint32", "mask", 0, 0}, 6667 {"uint32", "match_data", 0, 0}, 6668 {"uint32", "packet_size", 0, 0}, 6669 {"uint32", "last_packet_size", 0, 0}, 6670 {"uint32", "last_packet_num", 0, 0}, 6671 {"uint32", "stuffing_cnt", 0, 0}, 6672 {"cprimod_rsvd4_msg_ts_mode_t", "msg_ts_mode", 0, 0}, 6673 {"uint32", "msg_ts_count", 0, 0}, 6674 {"cprimod_rsvd4_frame_sync_mode_t", "frame_sync_mode", 0, 0}, 6675 {"uint32", "master_frame_offset", 0, 0}, 6676 {"uint32", "message_number_offset", 0, 0}, 6677 {"uint32", "container_block_count", 0, 0}, 6678 {"uint32", "queue_size", 0, 0}, 6679 {"uint32", "priority", 0, 0}, 6680 {"uint32", "pad_size", 0, 0}, 6681 {"uint32", "extra_pad_size", 0, 0}, 6682 {"uint32", "pad_enable", 0, 0}, 6683 {"uint32", "control_location", 0, 0}, 6684 {"uint32", "tsn_bitmap", 0, 0}, 6685 { NULL } 6686 }; 6687 6688 #endif /* CPRIMOD_SUPPORT */ 6689 #ifdef CPRIMOD_SUPPORT 6690 static cint_parameter_desc_t __cint_struct_members__portmod_rsvd4_tx_flow_info_t[] = 6691 { 6692 {"uint32", "axc_id", 0, 0}, 6693 {"uint32", "packet_size", 0, 0}, 6694 {"uint32", "last_packet_size", 0, 0}, 6695 {"uint32", "last_packet_num", 0, 0}, 6696 {"uint32", "stuffing_cnt", 0, 0}, 6697 {"cprimod_rsvd4_msg_ts_mode_t", "msg_ts_mode", 0, 0}, 6698 {"uint32", "msg_ts_count", 0, 0}, 6699 {"cprimod_rsvd4_frame_sync_mode_t", "frame_sync_mode", 0, 0}, 6700 {"uint32", "master_frame_offset", 0, 0}, 6701 {"uint32", "message_number_offset", 0, 0}, 6702 {"uint32", "container_block_count", 0, 0}, 6703 {"uint32", "buffer_size", 0, 0}, 6704 {"uint32", "cycle_size", 0, 0}, 6705 {"uint32", "use_ts_dbm", 0, 0}, 6706 {"uint32", "ts_dbm_profile_num", 0, 0}, 6707 {"uint32", "num_active_slot", 0, 0}, 6708 {"uint32", "msg_addr", 0, 0}, 6709 {"uint32", "msg_type", 0, 0}, 6710 {"uint32", "msg_ts_offset", 0, 0}, 6711 {"uint32", "pad_size", 0, 0}, 6712 {"uint32", "extra_pad_size", 0, 0}, 6713 {"uint32", "pad_enable", 0, 0}, 6714 {"uint32", "control_location", 0, 0}, 6715 { NULL } 6716 }; 6717 6718 #endif /* CPRIMOD_SUPPORT */ 6719 static cint_parameter_desc_t __cint_struct_members__portmod_vcos_speed_config_t[] = 6720 { 6721 {"uint32", "speed", 0, 0}, 6722 {"uint8", "num_lanes", 0, 0}, 6723 {"uint8", "ieee_mode", 0, 0}, 6724 {"uint8", "higig_mode", 0, 0}, 6725 {"uint8", "txpi_mode", 0, 0}, 6726 {"uint8", "eth_of_mixed_mode", 0, 0}, 6727 {"portmod_core_port_enet_cpri_type_t", "port_type", 0, 0}, 6728 { NULL } 6729 }; 6730 6731 static cint_parameter_desc_t __cint_struct_members__portmod_dual_vcos_t[] = 6732 { 6733 {"uint32", "vco_0", 0, 0}, 6734 {"uint32", "vco_1", 0, 0}, 6735 { NULL } 6736 }; 6737 6738 #ifdef CPRIMOD_SUPPORT 6739 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_slow_hdlc_config_info_t[] = 6740 { 6741 {"portmod_cpri_crc_mode_t", "tx_crc_mode", 0, 0}, 6742 {"portmod_cpri_hdlc_num_flag_bytes_t", "tx_flag_size", 0, 0}, 6743 {"portmod_cpri_hdlc_filling_flag_pattern_t", "tx_filling_flag_pattern", 0, 0}, 6744 {"portmod_cpri_hdlc_crc_init_val_t", "crc_init_val", 0, 0}, 6745 {"int", "use_fe_mac", 0, 0}, 6746 {"int", "crc_byte_swap", 0, 0}, 6747 {"int", "no_fcs_err_check", 0, 0}, 6748 {"uint32", "cw_sel", 0, 0}, 6749 {"uint32", "cw_size", 0, 0}, 6750 {"portmod_cpri_hdlc_fcs_size_t", "fcs_size", 0, 0}, 6751 {"int", "runt_frame_drop", 0, 0}, 6752 {"int", "long_frame_drop", 0, 0}, 6753 {"uint32", "min_frame_size", 0, 0}, 6754 {"uint32", "max_frame_size", 0, 0}, 6755 {"uint32", "queue_num", 0, 0}, 6756 {"uint32", "priority", 0, 0}, 6757 {"uint32", "queue_size", 0, 0}, 6758 {"uint32", "cycle_size", 0, 0}, 6759 {"uint32", "buffer_size", 0, 0}, 6760 { NULL } 6761 }; 6762 6763 #endif /* CPRIMOD_SUPPORT */ 6764 #ifdef CPRIMOD_SUPPORT 6765 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_fast_eth_config_info_t[] = 6766 { 6767 {"portmod_cpri_crc_mode_t", "tx_crc_mode", 0, 0}, 6768 {"uint32", "schan_start", 0, 0}, 6769 {"uint32", "schan_size", 0, 0}, 6770 {"uint32", "cw_sel", 0, 0}, 6771 {"uint32", "cw_size", 0, 0}, 6772 {"uint32", "min_packet_size", 0, 0}, 6773 {"uint32", "max_packet_size", 0, 0}, 6774 {"int", "min_packet_drop", 0, 0}, 6775 {"int", "max_packet_drop", 0, 0}, 6776 {"int", "strip_crc", 0, 0}, 6777 {"uint32", "min_ipg", 0, 0}, 6778 {"uint32", "queue_num", 0, 0}, 6779 {"uint32", "priority", 0, 0}, 6780 {"uint32", "queue_size", 0, 0}, 6781 {"uint32", "cycle_size", 0, 0}, 6782 {"uint32", "buffer_size", 0, 0}, 6783 {"int", "no_fcs_err_check", 0, 0}, 6784 { NULL } 6785 }; 6786 6787 #endif /* CPRIMOD_SUPPORT */ 6788 #ifdef CPRIMOD_SUPPORT 6789 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_rx_vsd_config_info_t[] = 6790 { 6791 {"uint32", "subchan_start", 0, 0}, 6792 {"portmod_cpri_vsd_control_subchan_size_t", "subchan_size", 0, 0}, 6793 {"portmod_cpri_vsd_control_subchan_num_bytes_t", "subchan_bytes", 0, 0}, 6794 {"uint32", "subchan_steps", 0, 0}, 6795 {"portmod_cpri_vsd_control_flow_num_bytes_t", "flow_bytes", 0, 0}, 6796 {"uint32", "queue_num", 0, 0}, 6797 {"uint32", "rsvd_sector_mask", 0, 4}, 6798 {"uint32", "priority", 0, 0}, 6799 {"uint32", "queue_size", 0, 0}, 6800 { NULL } 6801 }; 6802 6803 #endif /* CPRIMOD_SUPPORT */ 6804 #ifdef CPRIMOD_SUPPORT 6805 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_tx_vsd_config_info_t[] = 6806 { 6807 {"uint32", "subchan_start", 0, 0}, 6808 {"portmod_cpri_vsd_control_subchan_size_t", "subchan_size", 0, 0}, 6809 {"portmod_cpri_vsd_control_subchan_num_bytes_t", "subchan_bytes", 0, 0}, 6810 {"uint32", "subchan_steps", 0, 0}, 6811 {"portmod_cpri_vsd_control_flow_num_bytes_t", "flow_bytes", 0, 0}, 6812 {"uint32", "queue_num", 0, 0}, 6813 {"uint32", "rsvd_sector_mask", 0, 4}, 6814 {"uint32", "buffer_size", 0, 0}, 6815 {"uint32", "cycle_size", 0, 0}, 6816 {"int", "byte_order_swap", 0, 0}, 6817 { NULL } 6818 }; 6819 6820 #endif /* CPRIMOD_SUPPORT */ 6821 #ifdef CPRIMOD_SUPPORT 6822 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_rx_vsd_raw_config_t[] = 6823 { 6824 {"uint32", "schan_start", 0, 0}, 6825 {"uint32", "schan_size", 0, 0}, 6826 {"uint32", "cw_sel", 0, 0}, 6827 {"uint32", "cw_size", 0, 0}, 6828 {"portmod_cpri_cw_filter_mode_t", "filter_mode", 0, 0}, 6829 {"uint32", "hyper_frame_index", 0, 0}, 6830 {"uint32", "hyper_frame_modulo", 0, 0}, 6831 {"uint32", "match_offset", 0, 0}, 6832 {"uint32", "match_value", 0, 0}, 6833 {"uint32", "match_mask", 0, 0}, 6834 {"uint32", "queue_num", 0, 0}, 6835 {"uint32", "priority", 0, 0}, 6836 {"uint32", "queue_size", 0, 0}, 6837 { NULL } 6838 }; 6839 6840 #endif /* CPRIMOD_SUPPORT */ 6841 #ifdef CPRIMOD_SUPPORT 6842 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_tx_vsd_raw_config_t[] = 6843 { 6844 {"uint32", "schan_start", 0, 0}, 6845 {"uint32", "schan_size", 0, 0}, 6846 {"uint32", "cw_sel", 0, 0}, 6847 {"uint32", "cw_size", 0, 0}, 6848 {"uint32", "hyper_frame_index", 0, 0}, 6849 {"uint32", "hyper_frame_modulo", 0, 0}, 6850 {"uint32", "queue_num", 0, 0}, 6851 {"portmod_cpri_vsd_raw_map_mode_t", "map_mode", 0, 0}, 6852 {"int", "repeat_enable", 0, 0}, 6853 {"int", "bfn0_filter_enable", 0, 0}, 6854 {"int", "bfn1_filter_enable", 0, 0}, 6855 {"uint32", "idle_value", 0, 0}, 6856 {"uint32", "buffer_size", 0, 0}, 6857 {"uint32", "cycle_size", 0, 0}, 6858 { NULL } 6859 }; 6860 6861 #endif /* CPRIMOD_SUPPORT */ 6862 #ifdef CPRIMOD_SUPPORT 6863 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_rx_brcm_rsvd5_config_t[] = 6864 { 6865 {"uint32", "schan_start", 0, 0}, 6866 {"uint32", "schan_size", 0, 0}, 6867 {"int", "parity_disable", 0, 0}, 6868 {"uint32", "queue_num", 0, 0}, 6869 {"uint32", "priority", 0, 0}, 6870 {"uint32", "queue_size", 0, 0}, 6871 { NULL } 6872 }; 6873 6874 #endif /* CPRIMOD_SUPPORT */ 6875 #ifdef CPRIMOD_SUPPORT 6876 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_tx_brcm_rsvd5_config_t[] = 6877 { 6878 {"uint32", "schan_start", 0, 0}, 6879 {"uint32", "schan_size", 0, 0}, 6880 {"int", "crc_enable", 0, 0}, 6881 {"uint32", "queue_num", 0, 0}, 6882 {"uint32", "buffer_size", 0, 0}, 6883 {"uint32", "cycle_size", 0, 0}, 6884 { NULL } 6885 }; 6886 6887 #endif /* CPRIMOD_SUPPORT */ 6888 #ifdef CPRIMOD_SUPPORT 6889 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_rx_gcw_config_t[] = 6890 { 6891 {"uint32", "Ns", 0, 0}, 6892 {"uint32", "Xs", 0, 0}, 6893 {"uint32", "Y", 0, 0}, 6894 {"portmod_cpri_gcw_mask_t", "mask", 0, 0}, 6895 {"portmod_cpri_cw_filter_mode_t", "filter_mode", 0, 0}, 6896 {"uint32", "hyper_frame_index", 0, 0}, 6897 {"uint32", "hyper_frame_modulo", 0, 0}, 6898 {"uint32", "match_mask", 0, 0}, 6899 {"uint32", "match_value", 0, 0}, 6900 { NULL } 6901 }; 6902 6903 #endif /* CPRIMOD_SUPPORT */ 6904 #ifdef CPRIMOD_SUPPORT 6905 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_tx_gcw_config_t[] = 6906 { 6907 {"uint32", "Ns", 0, 0}, 6908 {"uint32", "Xs", 0, 0}, 6909 {"uint32", "Y", 0, 0}, 6910 {"portmod_cpri_gcw_mask_t", "mask", 0, 0}, 6911 {"uint32", "hyper_frame_index", 0, 0}, 6912 {"uint32", "hyper_frame_modulo", 0, 0}, 6913 {"int", "repeat_enable", 0, 0}, 6914 {"int", "bfn0_filter_enable", 0, 0}, 6915 {"int", "bfn1_filter_enable", 0, 0}, 6916 { NULL } 6917 }; 6918 6919 #endif /* CPRIMOD_SUPPORT */ 6920 static cint_parameter_desc_t __cint_struct_members__portmod_control_flow_config_t[] = 6921 { 6922 {"uint32", "match_mask", 0, 0}, 6923 {"uint32", "match_data", 0, 0}, 6924 {"portmod_control_msg_proc_type_t", "proc_type", 0, 0}, 6925 {"uint32", "queue_num", 0, 0}, 6926 {"uint32", "sync_profile", 0, 0}, 6927 {"int", "sync_enable", 0, 0}, 6928 {"uint32", "priority", 0, 0}, 6929 {"uint32", "queue_size", 0, 0}, 6930 { NULL } 6931 }; 6932 6933 static cint_parameter_desc_t __cint_struct_members__portmod_sync_profile_entry_t[] = 6934 { 6935 {"portmod_sync_count_cycle_t", "count_cycle", 0, 0}, 6936 {"uint32", "message_offset", 0, 0}, 6937 {"uint32", "master_frame_offset", 0, 0}, 6938 { NULL } 6939 }; 6940 6941 #ifdef CPRIMOD_SUPPORT 6942 static cint_parameter_desc_t __cint_struct_members__portmod_rsvd4_tx_config_info_t[] = 6943 { 6944 {"portmod_control_msg_proc_type_t", "proc_type", 0, 0}, 6945 {"uint8", "queue_num", 0, 0}, 6946 {"uint32", "queue_size", 0, 0}, 6947 {"uint32", "cycle_size", 0, 0}, 6948 {"uint8", "crc_mode", 0, 0}, 6949 { NULL } 6950 }; 6951 6952 #endif /* CPRIMOD_SUPPORT */ 6953 static cint_parameter_desc_t __cint_struct_members__portmod_txpi_override_t[] = 6954 { 6955 {"uint32", "enable", 0, 0}, 6956 {"int", "value", 0, 0}, 6957 { NULL } 6958 }; 6959 6960 static cint_parameter_desc_t __cint_struct_members__portmod_pm8x50_capability_t[] = 6961 { 6962 {"uint8", "num_lanes", 0, 0}, 6963 {"uint8", "num_cores", 0, 0}, 6964 {"uint8", "num_plls", 0, 0}, 6965 {"uint8", "num_vcos", 0, 0}, 6966 {"uint8", "vcos", 0, PORTMOD_PM8x50_MAX_VCOS}, 6967 { NULL } 6968 }; 6969 6970 static cint_parameter_desc_t __cint_struct_members__portmod_pm_specific_capability_t[] = 6971 { 6972 {"portmod_pm8x50_capability_t", "pm8x50_cap", 0, 0}, 6973 { NULL } 6974 }; 6975 6976 static cint_parameter_desc_t __cint_struct_members__portmod_pm_capability_t[] = 6977 { 6978 {"portmod_dispatch_type_t", "type", 0, 0}, 6979 {"portmod_pm_specific_capability_t", "pm_capability", 0, 0}, 6980 { NULL } 6981 }; 6982 6983 static cint_parameter_desc_t __cint_struct_members__portmod_pm_vco_setting_t[] = 6984 { 6985 {"int", "num_speeds", 0, 0}, 6986 {"portmod_speed_config_t", "speed_config_list", 1, 0}, 6987 {"int", "port_starting_lane_list", 1, 0}, 6988 {"int", "speed_for_pcs_bypass_port", 1, 0}, 6989 {"portmod_vco_type_t", "tvco", 0, 0}, 6990 {"portmod_vco_type_t", "ovco", 0, 0}, 6991 {"int", "is_tvco_new", 0, 0}, 6992 {"int", "is_ovco_new", 0, 0}, 6993 { NULL } 6994 }; 6995 6996 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_port_intr_info_t[] = 6997 { 6998 {"portmod_cpri_port_intr_type_t", "cpri_intr_type", 0, 0}, 6999 {"int", "axc_id", 0, 0}, 7000 {"int", "queue_num", 0, 0}, 7001 {"int", "data", 0, 0}, 7002 {"uint64", "data64", 0, 0}, 7003 { NULL } 7004 }; 7005 7006 static cint_parameter_desc_t __cint_struct_members__portmod_port_synce_clk_ctrl_t[] = 7007 { 7008 {"int", "stg0_mode", 0, 0}, 7009 {"int", "stg1_mode", 0, 0}, 7010 {"uint32", "sdm_val", 0, 0}, 7011 { NULL } 7012 }; 7013 7014 #ifdef CPRIMOD_SUPPORT 7015 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_rx_agnostic_config_info_t[] = 7016 { 7017 {"portmod_cpri_frame_sync_mode_t", "sync_mode", 0, 0}, 7018 {"uint32", "basic_frame_offset", 0, 0}, 7019 {"uint32", "hyper_frame_offset", 0, 0}, 7020 {"uint32", "radio_frame_offset", 0, 0}, 7021 {"portmod_cpri_roe_payload_multiple_t", "payload_multiple", 0, 0}, 7022 {"uint32", "pres_mod_count", 0, 0}, 7023 {"portmod_cpri_roe_ordering_info_option_t", "ordering_info_option", 0, 0}, 7024 { NULL } 7025 }; 7026 7027 #endif /* CPRIMOD_SUPPORT */ 7028 #ifdef CPRIMOD_SUPPORT 7029 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_tx_agnostic_config_info_t[] = 7030 { 7031 {"portmod_cpri_frame_sync_mode_t", "sync_mode", 0, 0}, 7032 {"uint32", "basic_frame_offset", 0, 0}, 7033 {"uint32", "hyper_frame_offset", 0, 0}, 7034 {"uint32", "radio_frame_offset", 0, 0}, 7035 {"portmod_cpri_roe_payload_multiple_t", "payload_multiple", 0, 0}, 7036 {"uint32", "queue_mod_count", 0, 0}, 7037 {"uint32", "pres_mod_count", 0, 0}, 7038 {"uint32", "pres_mod_offset", 0, 0}, 7039 {"portmod_cpri_roe_ordering_info_option_t", "ordering_info_option", 0, 0}, 7040 { NULL } 7041 }; 7042 7043 #endif /* CPRIMOD_SUPPORT */ 7044 #ifdef CPRIMOD_SUPPORT 7045 static cint_parameter_desc_t __cint_struct_members__portmod_fec_timestamp_config_t[] = 7046 { 7047 {"int", "enable", 0, 0}, 7048 {"portmod_fec_ts_source_t", "fec_fifo_ts_source_select", 0, 0}, 7049 {"portmod_fec_ts_source_t", "fec_cmic_ts_source_select", 0, 0}, 7050 {"uint32", "control_bit_offset_0", 0, 0}, 7051 {"uint32", "control_bit_offset_1", 0, 0}, 7052 {"uint32", "control_bit_offset_2", 0, 0}, 7053 {"uint32", "control_bit_offset_3", 0, 0}, 7054 { NULL } 7055 }; 7056 7057 #endif /* CPRIMOD_SUPPORT */ 7058 static cint_parameter_desc_t __cint_struct_members__portmod_ecc_intr_info_t[] = 7059 { 7060 {"int", "port", 0, 0}, 7061 {"soc_mem_t", "err_mem_info", 0, 0}, 7062 {"soc_reg_t", "ecc_reg_info", 0, 0}, 7063 {"int", "ecc_num_bits_err", 0, 0}, 7064 {"uint32", "err_addr", 0, 0}, 7065 {"char", "mem_str", 1, 0}, 7066 { NULL } 7067 }; 7068 7069 static cint_parameter_desc_t __cint_struct_members__portmod_port_rlm_config_t[] = 7070 { 7071 {"int", "is_initiator", 0, 0}, 7072 {"uint32", "active_lane_bit_map", 0, 0}, 7073 { NULL } 7074 }; 7075 7076 static cint_parameter_desc_t __cint_struct_members__portmod_port_rlm_status_t[] = 7077 { 7078 {"int", "rlm_disabled", 0, 0}, 7079 {"int", "rlm_busy", 0, 0}, 7080 {"int", "rlm_done", 0, 0}, 7081 {"int", "rlm_failed", 0, 0}, 7082 {"int", "rlm_status_count", 0, 0}, 7083 { NULL } 7084 }; 7085 7086 #ifdef CPRIMOD_SUPPORT 7087 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_rx_tunnel_mode_config_t[] = 7088 { 7089 {"uint32", "payload_size", 0, 0}, 7090 {"uint32", "pres_mod_count", 0, 0}, 7091 {"portmod_cpri_roe_ordering_info_option_t", "ordering_info_option", 0, 0}, 7092 { NULL } 7093 }; 7094 7095 #endif /* CPRIMOD_SUPPORT */ 7096 #ifdef CPRIMOD_SUPPORT 7097 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_tx_tunnel_mode_config_t[] = 7098 { 7099 {"uint32", "payload_size", 0, 0}, 7100 {"uint32", "queue_mod_count", 0, 0}, 7101 {"uint32", "pres_mod_count", 0, 0}, 7102 {"uint32", "pres_mod_offset", 0, 0}, 7103 {"portmod_cpri_roe_ordering_info_option_t", "ordering_info_option", 0, 0}, 7104 { NULL } 7105 }; 7106 7107 #endif /* CPRIMOD_SUPPORT */ 7108 #ifdef CPRIMOD_SUPPORT 7109 static cint_parameter_desc_t __cint_struct_members__portmod_rsvd4_rx_agnostic_config_t[] = 7110 { 7111 {"cprimod_rsvd4_frame_sync_mode_t", "frame_sync_mode", 0, 0}, 7112 {"uint32", "master_frame_offset", 0, 0}, 7113 {"uint32", "message_group_number", 0, 0}, 7114 {"uint32", "payload_multiple", 0, 0}, 7115 {"uint32", "pres_mod_count", 0, 0}, 7116 {"portmod_cpri_roe_ordering_info_option_t", "ordering_info_option", 0, 0}, 7117 { NULL } 7118 }; 7119 7120 #endif /* CPRIMOD_SUPPORT */ 7121 #ifdef CPRIMOD_SUPPORT 7122 static cint_parameter_desc_t __cint_struct_members__portmod_rsvd4_tx_agnostic_config_t[] = 7123 { 7124 {"cprimod_rsvd4_frame_sync_mode_t", "frame_sync_mode", 0, 0}, 7125 {"uint32", "master_frame_offset", 0, 0}, 7126 {"uint32", "message_group_number", 0, 0}, 7127 {"uint32", "payload_multiple", 0, 0}, 7128 {"uint32", "queue_mod_count", 0, 0}, 7129 {"uint32", "pres_mod_count", 0, 0}, 7130 {"uint32", "pres_mod_offset", 0, 0}, 7131 {"portmod_cpri_roe_ordering_info_option_t", "ordering_info_option", 0, 0}, 7132 { NULL } 7133 }; 7134 7135 #endif /* CPRIMOD_SUPPORT */ 7136 #ifdef CPRIMOD_SUPPORT 7137 static cint_parameter_desc_t __cint_struct_members__portmod_cpri_port_frame_config_t[] = 7138 { 7139 {"portmod_cpri_roe_frame_format_t", "frame_type", 0, 0}, 7140 {"portmod_cpri_ecpri_header_field_t", "decap_primary_key", 0, 0}, 7141 {"portmod_cpri_ecpri_header_field_t", "decap_secondary_key", 0, 0}, 7142 { NULL } 7143 }; 7144 7145 #endif /* CPRIMOD_SUPPORT */ 7146 7147 static cint_struct_type_t __cint_structures[] = 7148 { 7149 { 7150 "portmod_default_user_access_t", 7151 sizeof(portmod_default_user_access_t), 7152 __cint_struct_members__portmod_default_user_access_t, 7153 __cint_maddr__portmod_default_user_access_t 7154 }, 7155 { 7156 "portmod_pm4x10q_user_data_t", 7157 sizeof(portmod_pm4x10q_user_data_t), 7158 __cint_struct_members__portmod_pm4x10q_user_data_t, 7159 __cint_maddr__portmod_pm4x10q_user_data_t 7160 }, 7161 { 7162 "portmod_fifo_status_t", 7163 sizeof(portmod_fifo_status_t), 7164 __cint_struct_members__portmod_fifo_status_t, 7165 __cint_maddr__portmod_fifo_status_t 7166 }, 7167 { 7168 "portmod_pfc_config_t", 7169 sizeof(portmod_pfc_config_t), 7170 __cint_struct_members__portmod_pfc_config_t, 7171 __cint_maddr__portmod_pfc_config_t 7172 }, 7173 { 7174 "portmod_eee_t", 7175 sizeof(portmod_eee_t), 7176 __cint_struct_members__portmod_eee_t, 7177 __cint_maddr__portmod_eee_t 7178 }, 7179 { 7180 "portmod_eee_clock_t", 7181 sizeof(portmod_eee_clock_t), 7182 __cint_struct_members__portmod_eee_clock_t, 7183 __cint_maddr__portmod_eee_clock_t 7184 }, 7185 { 7186 "portmod_vlan_tag_t", 7187 sizeof(portmod_vlan_tag_t), 7188 __cint_struct_members__portmod_vlan_tag_t, 7189 __cint_maddr__portmod_vlan_tag_t 7190 }, 7191 { 7192 "portmod_rx_control_t", 7193 sizeof(portmod_rx_control_t), 7194 __cint_struct_members__portmod_rx_control_t, 7195 __cint_maddr__portmod_rx_control_t 7196 }, 7197 { 7198 "portmod_multi_get_t", 7199 sizeof(portmod_multi_get_t), 7200 __cint_struct_members__portmod_multi_get_t, 7201 __cint_maddr__portmod_multi_get_t 7202 }, 7203 { 7204 "portmod_portphy_ability_t", 7205 sizeof(portmod_portphy_ability_t), 7206 __cint_struct_members__portmod_portphy_ability_t, 7207 __cint_maddr__portmod_portphy_ability_t 7208 }, 7209 { 7210 "portmod_pdata_t", 7211 sizeof(portmod_pdata_t), 7212 __cint_struct_members__portmod_pdata_t, 7213 __cint_maddr__portmod_pdata_t 7214 }, 7215 { 7216 "portmod_port_mode_info_t", 7217 sizeof(portmod_port_mode_info_t), 7218 __cint_struct_members__portmod_port_mode_info_t, 7219 __cint_maddr__portmod_port_mode_info_t 7220 }, 7221 { 7222 "portmod_port_diag_info_t", 7223 sizeof(portmod_port_diag_info_t), 7224 __cint_struct_members__portmod_port_diag_info_t, 7225 __cint_maddr__portmod_port_diag_info_t 7226 }, 7227 { 7228 "portmod_pm_core_info_t", 7229 sizeof(portmod_pm_core_info_t), 7230 __cint_struct_members__portmod_pm_core_info_t, 7231 __cint_maddr__portmod_pm_core_info_t 7232 }, 7233 { 7234 "portmod_pm_diag_info_t", 7235 sizeof(portmod_pm_diag_info_t), 7236 __cint_struct_members__portmod_pm_diag_info_t, 7237 __cint_maddr__portmod_pm_diag_info_t 7238 }, 7239 { 7240 "portmod_port_ts_adjust_t", 7241 sizeof(portmod_port_ts_adjust_t), 7242 __cint_struct_members__portmod_port_ts_adjust_t, 7243 __cint_maddr__portmod_port_ts_adjust_t 7244 }, 7245 { 7246 "portmod_port_init_config_t", 7247 sizeof(portmod_port_init_config_t), 7248 __cint_struct_members__portmod_port_init_config_t, 7249 __cint_maddr__portmod_port_init_config_t 7250 }, 7251 { 7252 "portmod_port_interface_config_t", 7253 sizeof(portmod_port_interface_config_t), 7254 __cint_struct_members__portmod_port_interface_config_t, 7255 __cint_maddr__portmod_port_interface_config_t 7256 }, 7257 { 7258 "portmod_port_speed_ability_t", 7259 sizeof(portmod_port_speed_ability_t), 7260 __cint_struct_members__portmod_port_speed_ability_t, 7261 __cint_maddr__portmod_port_speed_ability_t 7262 }, 7263 { 7264 "portmod_speed_config_t", 7265 sizeof(portmod_speed_config_t), 7266 __cint_struct_members__portmod_speed_config_t, 7267 __cint_maddr__portmod_speed_config_t 7268 }, 7269 { 7270 "portmod_pm_identifier_t", 7271 sizeof(portmod_pm_identifier_t), 7272 __cint_struct_members__portmod_pm_identifier_t, 7273 __cint_maddr__portmod_pm_identifier_t 7274 }, 7275 { 7276 "portmod_port_add_info_t", 7277 sizeof(portmod_port_add_info_t), 7278 __cint_struct_members__portmod_port_add_info_t, 7279 __cint_maddr__portmod_port_add_info_t 7280 }, 7281 { 7282 "portmod_dnx_fabric_create_info_t", 7283 sizeof(portmod_dnx_fabric_create_info_t), 7284 __cint_struct_members__portmod_dnx_fabric_create_info_t, 7285 __cint_maddr__portmod_dnx_fabric_create_info_t 7286 }, 7287 { 7288 "portmod_pm8x50_fabric_create_info_t", 7289 sizeof(portmod_pm8x50_fabric_create_info_t), 7290 __cint_struct_members__portmod_pm8x50_fabric_create_info_t, 7291 __cint_maddr__portmod_pm8x50_fabric_create_info_t 7292 }, 7293 { 7294 "portmod_pm4x25_create_info_t", 7295 sizeof(portmod_pm4x25_create_info_t), 7296 __cint_struct_members__portmod_pm4x25_create_info_t, 7297 __cint_maddr__portmod_pm4x25_create_info_t 7298 }, 7299 { 7300 "portmod_pm4x10_create_info_t", 7301 sizeof(portmod_pm4x10_create_info_t), 7302 __cint_struct_members__portmod_pm4x10_create_info_t, 7303 __cint_maddr__portmod_pm4x10_create_info_t 7304 }, 7305 { 7306 "portmod_pm_qtc_create_info_t", 7307 sizeof(portmod_pm_qtc_create_info_t), 7308 __cint_struct_members__portmod_pm_qtc_create_info_t, 7309 __cint_maddr__portmod_pm_qtc_create_info_t 7310 }, 7311 { 7312 "portmod_pm_gphy_create_info_t", 7313 sizeof(portmod_pm_gphy_create_info_t), 7314 __cint_struct_members__portmod_pm_gphy_create_info_t, 7315 __cint_maddr__portmod_pm_gphy_create_info_t 7316 }, 7317 { 7318 "portmod_pm12x10_create_info_t", 7319 sizeof(portmod_pm12x10_create_info_t), 7320 __cint_struct_members__portmod_pm12x10_create_info_t, 7321 __cint_maddr__portmod_pm12x10_create_info_t 7322 }, 7323 { 7324 "portmod_pm4x10q_create_info_t", 7325 sizeof(portmod_pm4x10q_create_info_t), 7326 __cint_struct_members__portmod_pm4x10q_create_info_t, 7327 __cint_maddr__portmod_pm4x10q_create_info_t 7328 }, 7329 { 7330 "portmod_ilkn_os_create_info_t", 7331 sizeof(portmod_ilkn_os_create_info_t), 7332 __cint_struct_members__portmod_ilkn_os_create_info_t, 7333 __cint_maddr__portmod_ilkn_os_create_info_t 7334 }, 7335 { 7336 "portmod_pm4x2p5_create_info_t", 7337 sizeof(portmod_pm4x2p5_create_info_t), 7338 __cint_struct_members__portmod_pm4x2p5_create_info_t, 7339 __cint_maddr__portmod_pm4x2p5_create_info_t 7340 }, 7341 { 7342 "portmod_pm8x50_create_info_t", 7343 sizeof(portmod_pm8x50_create_info_t), 7344 __cint_struct_members__portmod_pm8x50_create_info_t, 7345 __cint_maddr__portmod_pm8x50_create_info_t 7346 }, 7347 { 7348 "portmod_pm4x10_qtc_create_info_t", 7349 sizeof(portmod_pm4x10_qtc_create_info_t), 7350 __cint_struct_members__portmod_pm4x10_qtc_create_info_t, 7351 __cint_maddr__portmod_pm4x10_qtc_create_info_t 7352 }, 7353 { 7354 "portmod_pm_specific_create_info_t", 7355 sizeof(portmod_pm_specific_create_info_t), 7356 __cint_struct_members__portmod_pm_specific_create_info_t, 7357 __cint_maddr__portmod_pm_specific_create_info_t 7358 }, 7359 { 7360 "portmod_remote_fault_control_t", 7361 sizeof(portmod_remote_fault_control_t), 7362 __cint_struct_members__portmod_remote_fault_control_t, 7363 __cint_maddr__portmod_remote_fault_control_t 7364 }, 7365 { 7366 "portmod_local_fault_control_t", 7367 sizeof(portmod_local_fault_control_t), 7368 __cint_struct_members__portmod_local_fault_control_t, 7369 __cint_maddr__portmod_local_fault_control_t 7370 }, 7371 { 7372 "portmod_llfc_control_t", 7373 sizeof(portmod_llfc_control_t), 7374 __cint_struct_members__portmod_llfc_control_t, 7375 __cint_maddr__portmod_llfc_control_t 7376 }, 7377 { 7378 "portmod_pfc_control_t", 7379 sizeof(portmod_pfc_control_t), 7380 __cint_struct_members__portmod_pfc_control_t, 7381 __cint_maddr__portmod_pfc_control_t 7382 }, 7383 { 7384 "portmod_pause_control_t", 7385 sizeof(portmod_pause_control_t), 7386 __cint_struct_members__portmod_pause_control_t, 7387 __cint_maddr__portmod_pause_control_t 7388 }, 7389 { 7390 "portmod_drain_cells_t", 7391 sizeof(portmod_drain_cells_t), 7392 __cint_struct_members__portmod_drain_cells_t, 7393 __cint_maddr__portmod_drain_cells_t 7394 }, 7395 { 7396 "portmod_pm_create_info_t", 7397 sizeof(portmod_pm_create_info_t), 7398 __cint_struct_members__portmod_pm_create_info_t, 7399 __cint_maddr__portmod_pm_create_info_t 7400 }, 7401 { 7402 "portmod_access_get_params_t", 7403 sizeof(portmod_access_get_params_t), 7404 __cint_struct_members__portmod_access_get_params_t, 7405 __cint_maddr__portmod_access_get_params_t 7406 }, 7407 { 7408 "portmod_pm_instances_t", 7409 sizeof(portmod_pm_instances_t), 7410 __cint_struct_members__portmod_pm_instances_t, 7411 __cint_maddr__portmod_pm_instances_t 7412 }, 7413 { 7414 "portmod_port_update_control_t", 7415 sizeof(portmod_port_update_control_t), 7416 __cint_struct_members__portmod_port_update_control_t, 7417 __cint_maddr__portmod_port_update_control_t 7418 }, 7419 { 7420 "portmod_lane_connection_t", 7421 sizeof(portmod_lane_connection_t), 7422 __cint_struct_members__portmod_lane_connection_t, 7423 __cint_maddr__portmod_lane_connection_t 7424 }, 7425 { 7426 "portmod_phy_core_info_t", 7427 sizeof(portmod_phy_core_info_t), 7428 __cint_struct_members__portmod_phy_core_info_t, 7429 __cint_maddr__portmod_phy_core_info_t 7430 }, 7431 { 7432 "portmod_xphy_lane_connection_t", 7433 sizeof(portmod_xphy_lane_connection_t), 7434 __cint_struct_members__portmod_xphy_lane_connection_t, 7435 __cint_maddr__portmod_xphy_lane_connection_t 7436 }, 7437 { 7438 "portmod_port_higig_e2ecc_hdr_t", 7439 sizeof(portmod_port_higig_e2ecc_hdr_t), 7440 __cint_struct_members__portmod_port_higig_e2ecc_hdr_t, 7441 __cint_maddr__portmod_port_higig_e2ecc_hdr_t 7442 }, 7443 { 7444 "portmod_port_resources_t", 7445 sizeof(portmod_port_resources_t), 7446 __cint_struct_members__portmod_port_resources_t, 7447 __cint_maddr__portmod_port_resources_t 7448 }, 7449 { 7450 "portmod_link_recovery_t", 7451 sizeof(portmod_link_recovery_t), 7452 __cint_struct_members__portmod_link_recovery_t, 7453 __cint_maddr__portmod_link_recovery_t 7454 }, 7455 { 7456 "portmod_pmd_lane_config_t", 7457 sizeof(portmod_pmd_lane_config_t), 7458 __cint_struct_members__portmod_pmd_lane_config_t, 7459 __cint_maddr__portmod_pmd_lane_config_t 7460 }, 7461 { 7462 "portmod_sbus_bcast_config_t", 7463 sizeof(portmod_sbus_bcast_config_t), 7464 __cint_struct_members__portmod_sbus_bcast_config_t, 7465 __cint_maddr__portmod_sbus_bcast_config_t 7466 }, 7467 #ifdef CPRIMOD_SUPPORT 7468 { 7469 "portmod_cpri_axc_frame_info_t", 7470 sizeof(portmod_cpri_axc_frame_info_t), 7471 __cint_struct_members__portmod_cpri_axc_frame_info_t, 7472 __cint_maddr__portmod_cpri_axc_frame_info_t 7473 }, 7474 #endif /* CPRIMOD_SUPPORT */ 7475 #ifdef CPRIMOD_SUPPORT 7476 { 7477 "portmod_tx_frame_tgen_config_t", 7478 sizeof(portmod_tx_frame_tgen_config_t), 7479 __cint_struct_members__portmod_tx_frame_tgen_config_t, 7480 __cint_maddr__portmod_tx_frame_tgen_config_t 7481 }, 7482 #endif /* CPRIMOD_SUPPORT */ 7483 #ifdef CPRIMOD_SUPPORT 7484 { 7485 "portmod_rsvd4_rx_flow_info_t", 7486 sizeof(portmod_rsvd4_rx_flow_info_t), 7487 __cint_struct_members__portmod_rsvd4_rx_flow_info_t, 7488 __cint_maddr__portmod_rsvd4_rx_flow_info_t 7489 }, 7490 #endif /* CPRIMOD_SUPPORT */ 7491 #ifdef CPRIMOD_SUPPORT 7492 { 7493 "portmod_rsvd4_tx_flow_info_t", 7494 sizeof(portmod_rsvd4_tx_flow_info_t), 7495 __cint_struct_members__portmod_rsvd4_tx_flow_info_t, 7496 __cint_maddr__portmod_rsvd4_tx_flow_info_t 7497 }, 7498 #endif /* CPRIMOD_SUPPORT */ 7499 { 7500 "portmod_vcos_speed_config_t", 7501 sizeof(portmod_vcos_speed_config_t), 7502 __cint_struct_members__portmod_vcos_speed_config_t, 7503 __cint_maddr__portmod_vcos_speed_config_t 7504 }, 7505 { 7506 "portmod_dual_vcos_t", 7507 sizeof(portmod_dual_vcos_t), 7508 __cint_struct_members__portmod_dual_vcos_t, 7509 __cint_maddr__portmod_dual_vcos_t 7510 }, 7511 #ifdef CPRIMOD_SUPPORT 7512 { 7513 "portmod_cpri_slow_hdlc_config_info_t", 7514 sizeof(portmod_cpri_slow_hdlc_config_info_t), 7515 __cint_struct_members__portmod_cpri_slow_hdlc_config_info_t, 7516 __cint_maddr__portmod_cpri_slow_hdlc_config_info_t 7517 }, 7518 #endif /* CPRIMOD_SUPPORT */ 7519 #ifdef CPRIMOD_SUPPORT 7520 { 7521 "portmod_cpri_fast_eth_config_info_t", 7522 sizeof(portmod_cpri_fast_eth_config_info_t), 7523 __cint_struct_members__portmod_cpri_fast_eth_config_info_t, 7524 __cint_maddr__portmod_cpri_fast_eth_config_info_t 7525 }, 7526 #endif /* CPRIMOD_SUPPORT */ 7527 #ifdef CPRIMOD_SUPPORT 7528 { 7529 "portmod_cpri_rx_vsd_config_info_t", 7530 sizeof(portmod_cpri_rx_vsd_config_info_t), 7531 __cint_struct_members__portmod_cpri_rx_vsd_config_info_t, 7532 __cint_maddr__portmod_cpri_rx_vsd_config_info_t 7533 }, 7534 #endif /* CPRIMOD_SUPPORT */ 7535 #ifdef CPRIMOD_SUPPORT 7536 { 7537 "portmod_cpri_tx_vsd_config_info_t", 7538 sizeof(portmod_cpri_tx_vsd_config_info_t), 7539 __cint_struct_members__portmod_cpri_tx_vsd_config_info_t, 7540 __cint_maddr__portmod_cpri_tx_vsd_config_info_t 7541 }, 7542 #endif /* CPRIMOD_SUPPORT */ 7543 #ifdef CPRIMOD_SUPPORT 7544 { 7545 "portmod_cpri_rx_vsd_raw_config_t", 7546 sizeof(portmod_cpri_rx_vsd_raw_config_t), 7547 __cint_struct_members__portmod_cpri_rx_vsd_raw_config_t, 7548 __cint_maddr__portmod_cpri_rx_vsd_raw_config_t 7549 }, 7550 #endif /* CPRIMOD_SUPPORT */ 7551 #ifdef CPRIMOD_SUPPORT 7552 { 7553 "portmod_cpri_tx_vsd_raw_config_t", 7554 sizeof(portmod_cpri_tx_vsd_raw_config_t), 7555 __cint_struct_members__portmod_cpri_tx_vsd_raw_config_t, 7556 __cint_maddr__portmod_cpri_tx_vsd_raw_config_t 7557 }, 7558 #endif /* CPRIMOD_SUPPORT */ 7559 #ifdef CPRIMOD_SUPPORT 7560 { 7561 "portmod_cpri_rx_brcm_rsvd5_config_t", 7562 sizeof(portmod_cpri_rx_brcm_rsvd5_config_t), 7563 __cint_struct_members__portmod_cpri_rx_brcm_rsvd5_config_t, 7564 __cint_maddr__portmod_cpri_rx_brcm_rsvd5_config_t 7565 }, 7566 #endif /* CPRIMOD_SUPPORT */ 7567 #ifdef CPRIMOD_SUPPORT 7568 { 7569 "portmod_cpri_tx_brcm_rsvd5_config_t", 7570 sizeof(portmod_cpri_tx_brcm_rsvd5_config_t), 7571 __cint_struct_members__portmod_cpri_tx_brcm_rsvd5_config_t, 7572 __cint_maddr__portmod_cpri_tx_brcm_rsvd5_config_t 7573 }, 7574 #endif /* CPRIMOD_SUPPORT */ 7575 #ifdef CPRIMOD_SUPPORT 7576 { 7577 "portmod_cpri_rx_gcw_config_t", 7578 sizeof(portmod_cpri_rx_gcw_config_t), 7579 __cint_struct_members__portmod_cpri_rx_gcw_config_t, 7580 __cint_maddr__portmod_cpri_rx_gcw_config_t 7581 }, 7582 #endif /* CPRIMOD_SUPPORT */ 7583 #ifdef CPRIMOD_SUPPORT 7584 { 7585 "portmod_cpri_tx_gcw_config_t", 7586 sizeof(portmod_cpri_tx_gcw_config_t), 7587 __cint_struct_members__portmod_cpri_tx_gcw_config_t, 7588 __cint_maddr__portmod_cpri_tx_gcw_config_t 7589 }, 7590 #endif /* CPRIMOD_SUPPORT */ 7591 { 7592 "portmod_control_flow_config_t", 7593 sizeof(portmod_control_flow_config_t), 7594 __cint_struct_members__portmod_control_flow_config_t, 7595 __cint_maddr__portmod_control_flow_config_t 7596 }, 7597 { 7598 "portmod_sync_profile_entry_t", 7599 sizeof(portmod_sync_profile_entry_t), 7600 __cint_struct_members__portmod_sync_profile_entry_t, 7601 __cint_maddr__portmod_sync_profile_entry_t 7602 }, 7603 #ifdef CPRIMOD_SUPPORT 7604 { 7605 "portmod_rsvd4_tx_config_info_t", 7606 sizeof(portmod_rsvd4_tx_config_info_t), 7607 __cint_struct_members__portmod_rsvd4_tx_config_info_t, 7608 __cint_maddr__portmod_rsvd4_tx_config_info_t 7609 }, 7610 #endif /* CPRIMOD_SUPPORT */ 7611 { 7612 "portmod_txpi_override_t", 7613 sizeof(portmod_txpi_override_t), 7614 __cint_struct_members__portmod_txpi_override_t, 7615 __cint_maddr__portmod_txpi_override_t 7616 }, 7617 { 7618 "portmod_pm8x50_capability_t", 7619 sizeof(portmod_pm8x50_capability_t), 7620 __cint_struct_members__portmod_pm8x50_capability_t, 7621 __cint_maddr__portmod_pm8x50_capability_t 7622 }, 7623 { 7624 "portmod_pm_specific_capability_t", 7625 sizeof(portmod_pm_specific_capability_t), 7626 __cint_struct_members__portmod_pm_specific_capability_t, 7627 __cint_maddr__portmod_pm_specific_capability_t 7628 }, 7629 { 7630 "portmod_pm_capability_t", 7631 sizeof(portmod_pm_capability_t), 7632 __cint_struct_members__portmod_pm_capability_t, 7633 __cint_maddr__portmod_pm_capability_t 7634 }, 7635 { 7636 "portmod_pm_vco_setting_t", 7637 sizeof(portmod_pm_vco_setting_t), 7638 __cint_struct_members__portmod_pm_vco_setting_t, 7639 __cint_maddr__portmod_pm_vco_setting_t 7640 }, 7641 { 7642 "portmod_cpri_port_intr_info_t", 7643 sizeof(portmod_cpri_port_intr_info_t), 7644 __cint_struct_members__portmod_cpri_port_intr_info_t, 7645 __cint_maddr__portmod_cpri_port_intr_info_t 7646 }, 7647 { 7648 "portmod_port_synce_clk_ctrl_t", 7649 sizeof(portmod_port_synce_clk_ctrl_t), 7650 __cint_struct_members__portmod_port_synce_clk_ctrl_t, 7651 __cint_maddr__portmod_port_synce_clk_ctrl_t 7652 }, 7653 #ifdef CPRIMOD_SUPPORT 7654 { 7655 "portmod_cpri_rx_agnostic_config_info_t", 7656 sizeof(portmod_cpri_rx_agnostic_config_info_t), 7657 __cint_struct_members__portmod_cpri_rx_agnostic_config_info_t, 7658 __cint_maddr__portmod_cpri_rx_agnostic_config_info_t 7659 }, 7660 #endif /* CPRIMOD_SUPPORT */ 7661 #ifdef CPRIMOD_SUPPORT 7662 { 7663 "portmod_cpri_tx_agnostic_config_info_t", 7664 sizeof(portmod_cpri_tx_agnostic_config_info_t), 7665 __cint_struct_members__portmod_cpri_tx_agnostic_config_info_t, 7666 __cint_maddr__portmod_cpri_tx_agnostic_config_info_t 7667 }, 7668 #endif /* CPRIMOD_SUPPORT */ 7669 #ifdef CPRIMOD_SUPPORT 7670 { 7671 "portmod_fec_timestamp_config_t", 7672 sizeof(portmod_fec_timestamp_config_t), 7673 __cint_struct_members__portmod_fec_timestamp_config_t, 7674 __cint_maddr__portmod_fec_timestamp_config_t 7675 }, 7676 #endif /* CPRIMOD_SUPPORT */ 7677 { 7678 "portmod_ecc_intr_info_t", 7679 sizeof(portmod_ecc_intr_info_t), 7680 __cint_struct_members__portmod_ecc_intr_info_t, 7681 __cint_maddr__portmod_ecc_intr_info_t 7682 }, 7683 { 7684 "portmod_port_rlm_config_t", 7685 sizeof(portmod_port_rlm_config_t), 7686 __cint_struct_members__portmod_port_rlm_config_t, 7687 __cint_maddr__portmod_port_rlm_config_t 7688 }, 7689 { 7690 "portmod_port_rlm_status_t", 7691 sizeof(portmod_port_rlm_status_t), 7692 __cint_struct_members__portmod_port_rlm_status_t, 7693 __cint_maddr__portmod_port_rlm_status_t 7694 }, 7695 #ifdef CPRIMOD_SUPPORT 7696 { 7697 "portmod_cpri_rx_tunnel_mode_config_t", 7698 sizeof(portmod_cpri_rx_tunnel_mode_config_t), 7699 __cint_struct_members__portmod_cpri_rx_tunnel_mode_config_t, 7700 __cint_maddr__portmod_cpri_rx_tunnel_mode_config_t 7701 }, 7702 #endif /* CPRIMOD_SUPPORT */ 7703 #ifdef CPRIMOD_SUPPORT 7704 { 7705 "portmod_cpri_tx_tunnel_mode_config_t", 7706 sizeof(portmod_cpri_tx_tunnel_mode_config_t), 7707 __cint_struct_members__portmod_cpri_tx_tunnel_mode_config_t, 7708 __cint_maddr__portmod_cpri_tx_tunnel_mode_config_t 7709 }, 7710 #endif /* CPRIMOD_SUPPORT */ 7711 #ifdef CPRIMOD_SUPPORT 7712 { 7713 "portmod_rsvd4_rx_agnostic_config_t", 7714 sizeof(portmod_rsvd4_rx_agnostic_config_t), 7715 __cint_struct_members__portmod_rsvd4_rx_agnostic_config_t, 7716 __cint_maddr__portmod_rsvd4_rx_agnostic_config_t 7717 }, 7718 #endif /* CPRIMOD_SUPPORT */ 7719 #ifdef CPRIMOD_SUPPORT 7720 { 7721 "portmod_rsvd4_tx_agnostic_config_t", 7722 sizeof(portmod_rsvd4_tx_agnostic_config_t), 7723 __cint_struct_members__portmod_rsvd4_tx_agnostic_config_t, 7724 __cint_maddr__portmod_rsvd4_tx_agnostic_config_t 7725 }, 7726 #endif /* CPRIMOD_SUPPORT */ 7727 #ifdef CPRIMOD_SUPPORT 7728 { 7729 "portmod_cpri_port_frame_config_t", 7730 sizeof(portmod_cpri_port_frame_config_t), 7731 __cint_struct_members__portmod_cpri_port_frame_config_t, 7732 __cint_maddr__portmod_cpri_port_frame_config_t 7733 }, 7734 #endif /* CPRIMOD_SUPPORT */ 7735 { NULL } 7736 }; 7737 7738 7739 /* Enums section */ 7740 static cint_enum_map_t __cint_enum_map__portmod_dispatch_type_t[] = 7741 { 7742 #ifdef PORTMOD_PM4X25_SUPPORT 7743 { "portmodDispatchTypePm4x25", portmodDispatchTypePm4x25 }, 7744 #endif /*PORTMOD_PM4X25_SUPPORT */ 7745 #ifdef PORTMOD_PM4X10_SUPPORT 7746 { "portmodDispatchTypePm4x10", portmodDispatchTypePm4x10 }, 7747 #endif /*PORTMOD_PM4X10_SUPPORT */ 7748 #ifdef PORTMOD_PM4X10TD_SUPPORT 7749 { "portmodDispatchTypePm4x10td", portmodDispatchTypePm4x10td }, 7750 #endif /*PORTMOD_PM4X10TD_SUPPORT */ 7751 #ifdef PORTMOD_PM12X10_SUPPORT 7752 { "portmodDispatchTypePm12x10", portmodDispatchTypePm12x10 }, 7753 #endif /*PORTMOD_PM12X10_SUPPORT */ 7754 #ifdef PORTMOD_PM4x10Q_SUPPORT 7755 { "portmodDispatchTypePm4x10Q", portmodDispatchTypePm4x10Q }, 7756 #endif /*PORTMOD_PM4x10Q_SUPPORT */ 7757 #ifdef PORTMOD_PM_QTC_SUPPORT 7758 { "portmodDispatchTypePm_qtc", portmodDispatchTypePm_qtc }, 7759 #endif /*PORTMOD_PM_QTC_SUPPORT */ 7760 #ifdef PORTMOD_PM_OS_ILKN_SUPPORT 7761 { "portmodDispatchTypePmOsILKN", portmodDispatchTypePmOsILKN }, 7762 #endif /*PORTMOD_PM_OS_ILKN_SUPPORT */ 7763 #ifdef PORTMOD_PM_OS_ILKN_50G_SUPPORT 7764 { "portmodDispatchTypePmOsILKN_50G", portmodDispatchTypePmOsILKN_50G }, 7765 #endif /*PORTMOD_PM_OS_ILKN_50G_SUPPORT */ 7766 #ifdef PORTMOD_DNX_FABRIC_SUPPORT 7767 { "portmodDispatchTypeDnx_fabric", portmodDispatchTypeDnx_fabric }, 7768 #endif /*PORTMOD_DNX_FABRIC_SUPPORT */ 7769 #ifdef PORTMOD_DNX_FABRIC_O_NIF_SUPPORT 7770 { "portmodDispatchTypeDnx_fabric_o_nif", portmodDispatchTypeDnx_fabric_o_nif }, 7771 #endif /*PORTMOD_DNX_FABRIC_O_NIF_SUPPORT */ 7772 #ifdef PORTMOD_PM8X50_FABRIC_SUPPORT 7773 { "portmodDispatchTypePm8x50_fabric", portmodDispatchTypePm8x50_fabric }, 7774 #endif /*PORTMOD_PM8X50_FABRIC_SUPPORT */ 7775 #ifdef PORTMOD_PM4X25TD_SUPPORT 7776 { "portmodDispatchTypePm4x25td", portmodDispatchTypePm4x25td }, 7777 #endif /*PORTMOD_PM4X25TD_SUPPORT */ 7778 #ifdef PORTMOD_PM12X10_XGS_SUPPORT 7779 { "portmodDispatchTypePm12x10_xgs", portmodDispatchTypePm12x10_xgs }, 7780 #endif /*PORTMOD_PM12X10_XGS_SUPPORT */ 7781 #ifdef PORTMOD_PM4X2P5_SUPPORT 7782 { "portmodDispatchTypePm4x2p5", portmodDispatchTypePm4x2p5 }, 7783 #endif /*PORTMOD_PM4X2P5_SUPPORT */ 7784 #ifdef PORTMOD_CPM4X25_SUPPORT 7785 { "portmodDispatchTypeCpm4x25", portmodDispatchTypeCpm4x25 }, 7786 #endif /*PORTMOD_CPM4X25_SUPPORT */ 7787 #ifdef PORTMOD_PM8X50_SUPPORT 7788 { "portmodDispatchTypePm8x50", portmodDispatchTypePm8x50 }, 7789 #endif /*PORTMOD_PM8X50_SUPPORT */ 7790 #ifdef PORTMOD_PM4X10_QTC_SUPPORT 7791 { "portmodDispatchTypePm4x10_qtc", portmodDispatchTypePm4x10_qtc }, 7792 #endif /*PORTMOD_PM4X10_QTC_SUPPORT */ 7793 #ifdef PORTMOD_PMNULL_SUPPORT 7794 { "portmodDispatchTypePmNull", portmodDispatchTypePmNull }, 7795 #endif /*PORTMOD_PMNULL_SUPPORT */ 7796 { "portmodDispatchTypeCount", portmodDispatchTypeCount }, 7797 { NULL } 7798 }; 7799 7800 static cint_enum_map_t __cint_enum_map__portmod_loopback_mode_t[] = 7801 { 7802 { "portmodLoopbackMacOuter", portmodLoopbackMacOuter }, 7803 { "portmodLoopbackMacCore", portmodLoopbackMacCore }, 7804 { "portmodLoopbackMacPCS", portmodLoopbackMacPCS }, 7805 { "portmodLoopbackMacAsyncFifo", portmodLoopbackMacAsyncFifo }, 7806 { "portmodLoopbackPhyGloopPCS", portmodLoopbackPhyGloopPCS }, 7807 { "portmodLoopbackPhyGloopPMD", portmodLoopbackPhyGloopPMD }, 7808 { "portmodLoopbackPhyRloopPCS", portmodLoopbackPhyRloopPCS }, 7809 { "portmodLoopbackPhyRloopPMD", portmodLoopbackPhyRloopPMD }, 7810 { "portmodLoopbackMacRloop", portmodLoopbackMacRloop }, 7811 { "portmodLoopbackCount", portmodLoopbackCount }, 7812 { NULL } 7813 }; 7814 7815 static cint_enum_map_t __cint_enum_map__portmod_core_port_mode_t[] = 7816 { 7817 { "portmodPortModeQuad", portmodPortModeQuad }, 7818 { "portmodPortModeTri012", portmodPortModeTri012 }, 7819 { "portmodPortModeTri023", portmodPortModeTri023 }, 7820 { "portmodPortModeDual", portmodPortModeDual }, 7821 { "portmodPortModeSingle", portmodPortModeSingle }, 7822 { "portmodPortModeCount", portmodPortModeCount }, 7823 { NULL } 7824 }; 7825 7826 static cint_enum_map_t __cint_enum_map__portmod_port_mode_aux_info_t[] = 7827 { 7828 { "portmodModeInfoNone", portmodModeInfoNone }, 7829 { "portmodModeInfoThreePorts", portmodModeInfoThreePorts }, 7830 { "portmodModeInfoTwoDualModePorts", portmodModeInfoTwoDualModePorts }, 7831 { "portmodModeInfoCount", portmodModeInfoCount }, 7832 { NULL } 7833 }; 7834 7835 static cint_enum_map_t __cint_enum_map__portmod_prbs_mode_t[] = 7836 { 7837 { "portmodPrbsModePhy", portmodPrbsModePhy }, 7838 { "portmodPrbsModeMac", portmodPrbsModeMac }, 7839 { "portmodPrbsModeCount", portmodPrbsModeCount }, 7840 { NULL } 7841 }; 7842 7843 static cint_enum_map_t __cint_enum_map__portmod_ext_to_int_phy_ctrlcode_t[] = 7844 { 7845 { "portmodExtToInt_CtrlCode_Init", portmodExtToInt_CtrlCode_Init }, 7846 { "portmodExtToInt_CtrlCode_Reset", portmodExtToInt_CtrlCode_Reset }, 7847 { "portmodExtToInt_CtrlCode_Link", portmodExtToInt_CtrlCode_Link }, 7848 { "portmodExtToInt_CtrlCode_Enable", portmodExtToInt_CtrlCode_Enable }, 7849 { "portmodExtToInt_CtrlCode_Duplex", portmodExtToInt_CtrlCode_Duplex }, 7850 { "portmodExtToInt_CtrlCode_Speed", portmodExtToInt_CtrlCode_Speed }, 7851 { "portmodExtToInt_CtrlCode_Master", portmodExtToInt_CtrlCode_Master }, 7852 { "portmodExtToInt_CtrlCode_AN", portmodExtToInt_CtrlCode_AN }, 7853 { "portmodExtToInt_CtrlCode_AdvLocal", portmodExtToInt_CtrlCode_AdvLocal }, 7854 { "portmodExtToInt_CtrlCode_AdvRemote", portmodExtToInt_CtrlCode_AdvRemote }, 7855 { "portmodExtToInt_CtrlCode_LB", portmodExtToInt_CtrlCode_LB }, 7856 { "portmodExtToInt_CtrlCode_Interface", portmodExtToInt_CtrlCode_Interface }, 7857 { "portmodExtToInt_CtrlCode_Ability", portmodExtToInt_CtrlCode_Ability }, 7858 { "portmodExtToInt_CtrlCode_AbilityAdvert", portmodExtToInt_CtrlCode_AbilityAdvert }, 7859 { "portmodExtToInt_CtrlCode_AbilityRemote", portmodExtToInt_CtrlCode_AbilityRemote }, 7860 { "portmodExtToInt_CtrlCode_AbilityLocal", portmodExtToInt_CtrlCode_AbilityLocal }, 7861 { "portmodExtToInt_CtrlCode_LinkupEvt", portmodExtToInt_CtrlCode_LinkupEvt }, 7862 { "portmodExtToInt_CtrlCode_LinkdnEvt", portmodExtToInt_CtrlCode_LinkdnEvt }, 7863 { "portmodExtToInt_CtrlCode_MDIX", portmodExtToInt_CtrlCode_MDIX }, 7864 { "portmodExtToInt_CtrlCode_MDIXStatus", portmodExtToInt_CtrlCode_MDIXStatus }, 7865 { "portmodExtToInt_CtrlCode_MediumConfig", portmodExtToInt_CtrlCode_MediumConfig }, 7866 { "portmodExtToInt_CtrlCode_Medium", portmodExtToInt_CtrlCode_Medium }, 7867 { "portmodExtToInt_CtrlCode_CableDiag", portmodExtToInt_CtrlCode_CableDiag }, 7868 { "portmodExtToInt_CtrlCode_Control", portmodExtToInt_CtrlCode_Control }, 7869 { "portmodExtToInt_CtrlCode_Firmware", portmodExtToInt_CtrlCode_Firmware }, 7870 { "portmodExtToInt_CtrlCode_TimesyncConfig", portmodExtToInt_CtrlCode_TimesyncConfig }, 7871 { "portmodExtToInt_CtrlCode_TimesyncControl", portmodExtToInt_CtrlCode_TimesyncControl }, 7872 { "portmodExtToInt_CtrlCode_TimesyncEnhancedCapture", portmodExtToInt_CtrlCode_TimesyncEnhancedCapture }, 7873 { "portmodExtToInt_CtrlCode_DiagCtrl", portmodExtToInt_CtrlCode_DiagCtrl }, 7874 { "portmodExtToInt_CtrlCode_LaneControl", portmodExtToInt_CtrlCode_LaneControl }, 7875 { "portmodExtToInt_CtrlCode_OAMConfig", portmodExtToInt_CtrlCode_OAMConfig }, 7876 { "portmodExtToInt_CtrlCode_OAMControl", portmodExtToInt_CtrlCode_OAMControl }, 7877 { "portmodExtToInt_CtrlCode_Multi", portmodExtToInt_CtrlCode_Multi }, 7878 { "portmodExtToInt_CtrlCode_Probe", portmodExtToInt_CtrlCode_Probe }, 7879 { "portmodExtToInt_CtrlCode_PreconditionBeforeProbe", portmodExtToInt_CtrlCode_PreconditionBeforeProbe }, 7880 { "portmodExtToInt_CtrlCode_LinkfaultGet", portmodExtToInt_CtrlCode_LinkfaultGet }, 7881 { "portmodExtToInt_CtrlCode_SpeedLine", portmodExtToInt_CtrlCode_SpeedLine }, 7882 { "portmodExtToInt_CtrlCode_Count", portmodExtToInt_CtrlCode_Count }, 7883 { NULL } 7884 }; 7885 7886 static cint_enum_map_t __cint_enum_map__portmod_cpm_core_mode_t[] = 7887 { 7888 { "portmodCpmAllCpri", portmodCpmAllCpri }, 7889 { "portmodCpmAllIEEE", portmodCpmAllIEEE }, 7890 { "portmodCpmAllHIGIG", portmodCpmAllHIGIG }, 7891 { "portmodCpmMixEthCpri", portmodCpmMixEthCpri }, 7892 { "portmodCpmCount", portmodCpmCount }, 7893 { NULL } 7894 }; 7895 7896 static cint_enum_map_t __cint_enum_map__portmod_core_port_enet_cpri_type_t[] = 7897 { 7898 { "portmodCpmPrtEthMode", portmodCpmPrtEthMode }, 7899 { "portmodCpmPrtEthOfMixedMode", portmodCpmPrtEthOfMixedMode }, 7900 { "portmodCpmPrtCpriMode", portmodCpmPrtCpriMode }, 7901 { "portmodCpmPrtCpriOfMixedMode", portmodCpmPrtCpriOfMixedMode }, 7902 { "portmodCpmPrtRsvd4Mode", portmodCpmPrtRsvd4Mode }, 7903 { "portmodCpmPrtRsvd4OfMixedMode", portmodCpmPrtRsvd4OfMixedMode }, 7904 { "portmodCpmPrtCount", portmodCpmPrtCount }, 7905 { NULL } 7906 }; 7907 7908 static cint_enum_map_t __cint_enum_map__portmod_qtc_mode_t[] = 7909 { 7910 { "portmodQtcModeInvalid", portmodQtcModeInvalid }, 7911 { "portmodQtcModeEthernet", portmodQtcModeEthernet }, 7912 { "portmodQtcModeQsgmii", portmodQtcModeQsgmii }, 7913 { "portmodQtcModeUsxgmii", portmodQtcModeUsxgmii }, 7914 { "portmodQtcModeCount", portmodQtcModeCount }, 7915 { NULL } 7916 }; 7917 7918 static cint_enum_map_t __cint_enum_map__portmod_vco_type_t[] = 7919 { 7920 { "portmodVCOInvalid", portmodVCOInvalid }, 7921 { "portmodVCO20G", portmodVCO20G }, 7922 { "portmodVCO21G", portmodVCO21G }, 7923 { "portmodVCO25G", portmodVCO25G }, 7924 { "portmodVCO26G", portmodVCO26G }, 7925 { "portmodVCO27G", portmodVCO27G }, 7926 { "portmodVCO20P625G", portmodVCO20P625G }, 7927 { "portmodVCO20P937G", portmodVCO20P937G }, 7928 { "portmodVCO22P5G", portmodVCO22P5G }, 7929 { "portmodVCO23G", portmodVCO23G }, 7930 { "portmodVCO25P781G", portmodVCO25P781G }, 7931 { "portmodVCO26P562G", portmodVCO26P562G }, 7932 { "portmodVCO6P25G", portmodVCO6P25G }, 7933 { "portmodVCO6P5625G", portmodVCO6P5625G }, 7934 { "portmodVCO8P125G", portmodVCO8P125G }, 7935 { "portmodVCO9P735G", portmodVCO9P735G }, 7936 { "portmodVCO10G", portmodVCO10G }, 7937 { "portmodVCO10P3125G", portmodVCO10P3125G }, 7938 { "portmodVCO10P9375G", portmodVCO10P9375G }, 7939 { "portmodVCO12P5G", portmodVCO12P5G }, 7940 { "portmodVCO27P343G", portmodVCO27P343G }, 7941 { "portmodVCO28P125G", portmodVCO28P125G }, 7942 { "portmodVCOCount", portmodVCOCount }, 7943 { NULL } 7944 }; 7945 7946 static cint_enum_map_t __cint_enum_map__portmod_call_back_action_type_t[] = 7947 { 7948 { "portmodCallBackActionTypePre", portmodCallBackActionTypePre }, 7949 { "portmodCallBackActionTypeDuring", portmodCallBackActionTypeDuring }, 7950 { "portmodCallBackActionTypePost", portmodCallBackActionTypePost }, 7951 { "portmodCallBackActionTypeCount", portmodCallBackActionTypeCount }, 7952 { NULL } 7953 }; 7954 7955 static cint_enum_map_t __cint_enum_map__portmod_intr_type_t[] = 7956 { 7957 { "portmodIntrTypeMibTxMemErr", portmodIntrTypeMibTxMemErr }, 7958 { "portmodIntrTypeMibRxMemErr", portmodIntrTypeMibRxMemErr }, 7959 { "portmodIntrTypeMacTxCdcMemErr", portmodIntrTypeMacTxCdcMemErr }, 7960 { "portmodIntrTypeMacRxCdcMemErr", portmodIntrTypeMacRxCdcMemErr }, 7961 { "portmodIntrTypeMacRxTsCdcMemErr", portmodIntrTypeMacRxTsCdcMemErr }, 7962 { "portmodIntrTypeTscErr", portmodIntrTypeTscErr }, 7963 { "portmodIntrTypePmdErr", portmodIntrTypePmdErr }, 7964 { "portmodIntrTypeRxFcReqFull", portmodIntrTypeRxFcReqFull }, 7965 { "portmodIntrTypeCore0Intr", portmodIntrTypeCore0Intr }, 7966 { "portmodIntrTypeCore1Intr", portmodIntrTypeCore1Intr }, 7967 { "portmodIntrTypeCore2Intr", portmodIntrTypeCore2Intr }, 7968 { "portmodIntrTypeCore3Intr", portmodIntrTypeCore3Intr }, 7969 { "portmodIntrTypeTsc0Intr", portmodIntrTypeTsc0Intr }, 7970 { "portmodIntrTypeTsc1Intr", portmodIntrTypeTsc1Intr }, 7971 { "portmodIntrTypeTsc2Intr", portmodIntrTypeTsc2Intr }, 7972 { "portmodIntrTypeLinkdown", portmodIntrTypeLinkdown }, 7973 { "portmodIntrTypeMacErr", portmodIntrTypeMacErr }, 7974 { "portmodIntrTypeTxPktUnderflow", portmodIntrTypeTxPktUnderflow }, 7975 { "portmodIntrTypeTxPktOverflow", portmodIntrTypeTxPktOverflow }, 7976 { "portmodIntrTypeTxLlfcMsgOverflow", portmodIntrTypeTxLlfcMsgOverflow }, 7977 { "portmodIntrTypeTxTSFifoOverflow", portmodIntrTypeTxTSFifoOverflow }, 7978 { "portmodIntrTypeRxPktOverflow", portmodIntrTypeRxPktOverflow }, 7979 { "portmodIntrTypeRxMsgOverflow", portmodIntrTypeRxMsgOverflow }, 7980 { "portmodIntrTypeTxCdcSingleBitErr", portmodIntrTypeTxCdcSingleBitErr }, 7981 { "portmodIntrTypeTxCdcDoubleBitErr", portmodIntrTypeTxCdcDoubleBitErr }, 7982 { "portmodIntrTypeRxCdcSingleBitErr", portmodIntrTypeRxCdcSingleBitErr }, 7983 { "portmodIntrTypeRxCdcDoubleBitErr", portmodIntrTypeRxCdcDoubleBitErr }, 7984 { "portmodIntrTypeRxTsMemSingleBitErr", portmodIntrTypeRxTsMemSingleBitErr }, 7985 { "portmodIntrTypeRxTsMemDoubleBitErr", portmodIntrTypeRxTsMemDoubleBitErr }, 7986 { "portmodIntrTypeLocalFaultStatus", portmodIntrTypeLocalFaultStatus }, 7987 { "portmodIntrTypeRemoteFaultStatus", portmodIntrTypeRemoteFaultStatus }, 7988 { "portmodIntrTypeLinkInterruptionStatus", portmodIntrTypeLinkInterruptionStatus }, 7989 { "portmodIntrTypeTsEntryValid", portmodIntrTypeTsEntryValid }, 7990 { "portmodIntrTypeMibMemSingleBitErr", portmodIntrTypeMibMemSingleBitErr }, 7991 { "portmodIntrTypeMibMemDoubleBitErr", portmodIntrTypeMibMemDoubleBitErr }, 7992 { "portmodIntrTypeMibMemMultipleBitErr", portmodIntrTypeMibMemMultipleBitErr }, 7993 { "portmodIntrTypeTscCore0Err", portmodIntrTypeTscCore0Err }, 7994 { "portmodIntrTypeTscCore1Err", portmodIntrTypeTscCore1Err }, 7995 { "portmodIntrTypeFcReqFull", portmodIntrTypeFcReqFull }, 7996 { "portmodIntrTypeCount", portmodIntrTypeCount }, 7997 { NULL } 7998 }; 7999 8000 static cint_enum_map_t __cint_enum_map__portmod_stat_val_t[] = 8001 { 8002 { "portmodIfInOctets", portmodIfInOctets }, 8003 { "portmodIfInUcastPkts", portmodIfInUcastPkts }, 8004 { "portmodIfInNUcastPkts", portmodIfInNUcastPkts }, 8005 { "portmodIfInBroadcastPkts", portmodIfInBroadcastPkts }, 8006 { "portmodIfInMulticastPkts", portmodIfInMulticastPkts }, 8007 { "portmodIfInDiscards", portmodIfInDiscards }, 8008 { "portmodIfInErrors", portmodIfInErrors }, 8009 { "portmodIfOutOctets", portmodIfOutOctets }, 8010 { "portmodIfOutUcastPkts", portmodIfOutUcastPkts }, 8011 { "portmodIfOutNUcastPkts", portmodIfOutNUcastPkts }, 8012 { "portmodIfOutBroadcastPkts", portmodIfOutBroadcastPkts }, 8013 { "portmodIfOutMulticastPkts", portmodIfOutMulticastPkts }, 8014 { "portmodIfOutDiscards", portmodIfOutDiscards }, 8015 { "portmodIfOutErrors", portmodIfOutErrors }, 8016 { "portmodIpInReceives", portmodIpInReceives }, 8017 { "portmodIpInHdrErrors", portmodIpInHdrErrors }, 8018 { "portmodIpForwDatagrams", portmodIpForwDatagrams }, 8019 { "portmodIpInDiscards", portmodIpInDiscards }, 8020 { "portmodDot1dBasePortMtuExceededDiscards", portmodDot1dBasePortMtuExceededDiscards }, 8021 { "portmodDot1dTpPortInFrames", portmodDot1dTpPortInFrames }, 8022 { "portmodDot1dTpPortOutFrames", portmodDot1dTpPortOutFrames }, 8023 { "portmodDot1dPortInDiscards", portmodDot1dPortInDiscards }, 8024 { "portmodEtherStatsDropEvents", portmodEtherStatsDropEvents }, 8025 { "portmodEtherStatsOctets", portmodEtherStatsOctets }, 8026 { "portmodEtherStatsPkts", portmodEtherStatsPkts }, 8027 { "portmodEtherStatsBroadcastPkts", portmodEtherStatsBroadcastPkts }, 8028 { "portmodEtherStatsMulticastPkts", portmodEtherStatsMulticastPkts }, 8029 { "portmodEtherStatsCRCAlignErrors", portmodEtherStatsCRCAlignErrors }, 8030 { "portmodEtherStatsUndersizePkts", portmodEtherStatsUndersizePkts }, 8031 { "portmodEtherStatsOversizePkts", portmodEtherStatsOversizePkts }, 8032 { "portmodEtherRxOversizePkts", portmodEtherRxOversizePkts }, 8033 { "portmodEtherTxOversizePkts", portmodEtherTxOversizePkts }, 8034 { "portmodEtherStatsFragments", portmodEtherStatsFragments }, 8035 { "portmodEtherStatsJabbers", portmodEtherStatsJabbers }, 8036 { "portmodEtherStatsPkts64Octets", portmodEtherStatsPkts64Octets }, 8037 { "portmodEtherStatsPkts65to127Octets", portmodEtherStatsPkts65to127Octets }, 8038 { "portmodEtherStatsPkts128to255Octets", portmodEtherStatsPkts128to255Octets }, 8039 { "portmodEtherStatsPkts256to511Octets", portmodEtherStatsPkts256to511Octets }, 8040 { "portmodEtherStatsPkts512to1023Octets", portmodEtherStatsPkts512to1023Octets }, 8041 { "portmodEtherStatsPkts1024to1518Octets", portmodEtherStatsPkts1024to1518Octets }, 8042 { "portmodBcmEtherStatsPkts1519to1522Octets", portmodBcmEtherStatsPkts1519to1522Octets }, 8043 { "portmodBcmEtherStatsPkts1522to2047Octets", portmodBcmEtherStatsPkts1522to2047Octets }, 8044 { "portmodBcmEtherStatsPkts2048to4095Octets", portmodBcmEtherStatsPkts2048to4095Octets }, 8045 { "portmodBcmEtherStatsPkts4095to9216Octets", portmodBcmEtherStatsPkts4095to9216Octets }, 8046 { "portmodBcmEtherStatsPkts9217to16383Octets", portmodBcmEtherStatsPkts9217to16383Octets }, 8047 { "portmodBcmReceivedPkts64Octets", portmodBcmReceivedPkts64Octets }, 8048 { "portmodBcmReceivedPkts65to127Octets", portmodBcmReceivedPkts65to127Octets }, 8049 { "portmodBcmReceivedPkts128to255Octets", portmodBcmReceivedPkts128to255Octets }, 8050 { "portmodBcmReceivedPkts256to511Octets", portmodBcmReceivedPkts256to511Octets }, 8051 { "portmodBcmReceivedPkts512to1023Octets", portmodBcmReceivedPkts512to1023Octets }, 8052 { "portmodBcmReceivedPkts1024to1518Octets", portmodBcmReceivedPkts1024to1518Octets }, 8053 { "portmodBcmReceivedPkts1519to2047Octets", portmodBcmReceivedPkts1519to2047Octets }, 8054 { "portmodBcmReceivedPkts2048to4095Octets", portmodBcmReceivedPkts2048to4095Octets }, 8055 { "portmodBcmReceivedPkts4095to9216Octets", portmodBcmReceivedPkts4095to9216Octets }, 8056 { "portmodBcmReceivedPkts9217to16383Octets", portmodBcmReceivedPkts9217to16383Octets }, 8057 { "portmodBcmTransmittedPkts64Octets", portmodBcmTransmittedPkts64Octets }, 8058 { "portmodBcmTransmittedPkts65to127Octets", portmodBcmTransmittedPkts65to127Octets }, 8059 { "portmodBcmTransmittedPkts128to255Octets", portmodBcmTransmittedPkts128to255Octets }, 8060 { "portmodBcmTransmittedPkts256to511Octets", portmodBcmTransmittedPkts256to511Octets }, 8061 { "portmodBcmTransmittedPkts512to1023Octets", portmodBcmTransmittedPkts512to1023Octets }, 8062 { "portmodBcmTransmittedPkts1024to1518Octets", portmodBcmTransmittedPkts1024to1518Octets }, 8063 { "portmodBcmTransmittedPkts1519to2047Octets", portmodBcmTransmittedPkts1519to2047Octets }, 8064 { "portmodBcmTransmittedPkts2048to4095Octets", portmodBcmTransmittedPkts2048to4095Octets }, 8065 { "portmodBcmTransmittedPkts4095to9216Octets", portmodBcmTransmittedPkts4095to9216Octets }, 8066 { "portmodBcmTransmittedPkts9217to16383Octets", portmodBcmTransmittedPkts9217to16383Octets }, 8067 { "portmodEtherStatsTXNoErrors", portmodEtherStatsTXNoErrors }, 8068 { "portmodEtherStatsRXNoErrors", portmodEtherStatsRXNoErrors }, 8069 { "portmodDot3StatsFCSErrors", portmodDot3StatsFCSErrors }, 8070 { "portmodDot3StatsInternalMacTransmitErrors", portmodDot3StatsInternalMacTransmitErrors }, 8071 { "portmodDot3StatsFrameTooLongs", portmodDot3StatsFrameTooLongs }, 8072 { "portmodDot3StatsSymbolErrors", portmodDot3StatsSymbolErrors }, 8073 { "portmodDot3ControlInUnknownOpcodes", portmodDot3ControlInUnknownOpcodes }, 8074 { "portmodDot3InPauseFrames", portmodDot3InPauseFrames }, 8075 { "portmodDot3OutPauseFrames", portmodDot3OutPauseFrames }, 8076 { "portmodIfHCInOctets", portmodIfHCInOctets }, 8077 { "portmodIfHCInUcastPkts", portmodIfHCInUcastPkts }, 8078 { "portmodIfHCInMulticastPkts", portmodIfHCInMulticastPkts }, 8079 { "portmodIfHCInBroadcastPkts", portmodIfHCInBroadcastPkts }, 8080 { "portmodIfHCOutOctets", portmodIfHCOutOctets }, 8081 { "portmodIfHCOutUcastPkts", portmodIfHCOutUcastPkts }, 8082 { "portmodIfHCOutMulticastPkts", portmodIfHCOutMulticastPkts }, 8083 { "portmodIfHCOutBroadcastPckts", portmodIfHCOutBroadcastPckts }, 8084 { "portmodIpv6IfStatsInReceives", portmodIpv6IfStatsInReceives }, 8085 { "portmodIpv6IfStatsInHdrErrors", portmodIpv6IfStatsInHdrErrors }, 8086 { "portmodIpv6IfStatsInAddrErrors", portmodIpv6IfStatsInAddrErrors }, 8087 { "portmodIpv6IfStatsInDiscards", portmodIpv6IfStatsInDiscards }, 8088 { "portmodIpv6IfStatsOutForwDatagrams", portmodIpv6IfStatsOutForwDatagrams }, 8089 { "portmodIpv6IfStatsOutDiscards", portmodIpv6IfStatsOutDiscards }, 8090 { "portmodIpv6IfStatsInMcastPkts", portmodIpv6IfStatsInMcastPkts }, 8091 { "portmodIpv6IfStatsOutMcastPkts", portmodIpv6IfStatsOutMcastPkts }, 8092 { "portmodIeee8021PfcRequests", portmodIeee8021PfcRequests }, 8093 { "portmodIeee8021PfcIndications", portmodIeee8021PfcIndications }, 8094 { "portmodBcmIPMCBridgedPckts", portmodBcmIPMCBridgedPckts }, 8095 { "portmodBcmIPMCRoutedPckts", portmodBcmIPMCRoutedPckts }, 8096 { "portmodBcmIPMCInDroppedPckts", portmodBcmIPMCInDroppedPckts }, 8097 { "portmodBcmIPMCOutDroppedPckts", portmodBcmIPMCOutDroppedPckts }, 8098 { "portmodBcmRxVlanTagFrame", portmodBcmRxVlanTagFrame }, 8099 { "portmodBcmRxDoubleVlanTagFrame", portmodBcmRxDoubleVlanTagFrame }, 8100 { "portmodBcmTxVlanTagFrame", portmodBcmTxVlanTagFrame }, 8101 { "portmodBcmTxDoubleVlanTagFrame", portmodBcmTxDoubleVlanTagFrame }, 8102 { "portmodBcmRxPFCControlFrame", portmodBcmRxPFCControlFrame }, 8103 { "portmodBcmTxPFCControlFrame", portmodBcmTxPFCControlFrame }, 8104 { "portmodBcmRxPFCFramePriority0", portmodBcmRxPFCFramePriority0 }, 8105 { "portmodBcmRxPFCFramePriority1", portmodBcmRxPFCFramePriority1 }, 8106 { "portmodBcmRxPFCFramePriority2", portmodBcmRxPFCFramePriority2 }, 8107 { "portmodBcmRxPFCFramePriority3", portmodBcmRxPFCFramePriority3 }, 8108 { "portmodBcmRxPFCFramePriority4", portmodBcmRxPFCFramePriority4 }, 8109 { "portmodBcmRxPFCFramePriority5", portmodBcmRxPFCFramePriority5 }, 8110 { "portmodBcmRxPFCFramePriority6", portmodBcmRxPFCFramePriority6 }, 8111 { "portmodBcmRxPFCFramePriority7", portmodBcmRxPFCFramePriority7 }, 8112 { "portmodBcmTxPFCFramePriority0", portmodBcmTxPFCFramePriority0 }, 8113 { "portmodBcmTxPFCFramePriority1", portmodBcmTxPFCFramePriority1 }, 8114 { "portmodBcmTxPFCFramePriority2", portmodBcmTxPFCFramePriority2 }, 8115 { "portmodBcmTxPFCFramePriority3", portmodBcmTxPFCFramePriority3 }, 8116 { "portmodBcmTxPFCFramePriority4", portmodBcmTxPFCFramePriority4 }, 8117 { "portmodBcmTxPFCFramePriority5", portmodBcmTxPFCFramePriority5 }, 8118 { "portmodBcmTxPFCFramePriority6", portmodBcmTxPFCFramePriority6 }, 8119 { "portmodBcmTxPFCFramePriority7", portmodBcmTxPFCFramePriority7 }, 8120 { "portmodCount", portmodCount }, 8121 { NULL } 8122 }; 8123 8124 static cint_enum_map_t __cint_enum_map__portmod_preemption_control_t[] = 8125 { 8126 { "portmodPreemptionControlInvalid", portmodPreemptionControlInvalid }, 8127 { "portmodPreemptionControlPreemptionSupport", portmodPreemptionControlPreemptionSupport }, 8128 { "portmodPreemptionControlEnableTx", portmodPreemptionControlEnableTx }, 8129 { "portmodPreemptionControlVerifyEnable", portmodPreemptionControlVerifyEnable }, 8130 { "portmodPreemptionControlVerifyTime", portmodPreemptionControlVerifyTime }, 8131 { "portmodPreemptionControlVerifyAttempts", portmodPreemptionControlVerifyAttempts }, 8132 { "portmodPreemptionControlNonFinalFragSizeRx", portmodPreemptionControlNonFinalFragSizeRx }, 8133 { "portmodPreemptionControlFinalFragSizeRx", portmodPreemptionControlFinalFragSizeRx }, 8134 { "portmodPreemptionControlCount", portmodPreemptionControlCount }, 8135 { NULL } 8136 }; 8137 8138 static cint_enum_map_t __cint_enum_map__portmod_preemption_tx_status_t[] = 8139 { 8140 { "portmodPreemptionTxStatusInactive", portmodPreemptionTxStatusInactive }, 8141 { "portmodPreemptionTxStatusVerifying", portmodPreemptionTxStatusVerifying }, 8142 { "portmodPreemptionTxStatusActive", portmodPreemptionTxStatusActive }, 8143 { "portmodPreemptionTxStatusCount", portmodPreemptionTxStatusCount }, 8144 { NULL } 8145 }; 8146 8147 static cint_enum_map_t __cint_enum_map__portmod_preemption_verify_status_type_t[] = 8148 { 8149 { "portmodPreemptionVerifyStatus", portmodPreemptionVerifyStatus }, 8150 { "portmodPreemptionVerifyCountStatus", portmodPreemptionVerifyCountStatus }, 8151 { "portmodPreemptionVerifyCount", portmodPreemptionVerifyCount }, 8152 { NULL } 8153 }; 8154 8155 static cint_enum_map_t __cint_enum_map__portmod_preemption_verify_status_t[] = 8156 { 8157 { "portmodPreemptionVerifyStatusDisabled", portmodPreemptionVerifyStatusDisabled }, 8158 { "portmodPreemptionVerifyStatusInitial", portmodPreemptionVerifyStatusInitial }, 8159 { "portmodPreemptionVerifyStatusInProgress", portmodPreemptionVerifyStatusInProgress }, 8160 { "portmodPreemptionVerifyStatusSucceeded", portmodPreemptionVerifyStatusSucceeded }, 8161 { "portmodPreemptionVerifyStatusFailed", portmodPreemptionVerifyStatusFailed }, 8162 { "portmodPreemptionVerifyStatusCount", portmodPreemptionVerifyStatusCount }, 8163 { NULL } 8164 }; 8165 8166 static cint_enum_map_t __cint_enum_map__portmod_preemption_force_rx_eop_mode_t[] = 8167 { 8168 { "portmodPreemptionForceSwRxEop", portmodPreemptionForceSwRxEop }, 8169 { "portmodPreemptionForceAutoHwEop", portmodPreemptionForceAutoHwEop }, 8170 { "portmodPreemptionForceCount", portmodPreemptionForceCount }, 8171 { NULL } 8172 }; 8173 8174 #ifdef CPRIMOD_SUPPORT 8175 static cint_enum_map_t __cint_enum_map__portmod_cpri_stage_t[] = 8176 { 8177 { "portmodCpriStageRx", portmodCpriStageRx }, 8178 { "portmodCpriStageTx", portmodCpriStageTx }, 8179 { "portmodCpriStageCount", portmodCpriStageCount }, 8180 { NULL } 8181 }; 8182 8183 #endif /* CPRIMOD_SUPPORT */ 8184 8185 static cint_enum_type_t __cint_enums[] = 8186 { 8187 {"portmod_dispatch_type_t", __cint_enum_map__portmod_dispatch_type_t }, 8188 {"portmod_loopback_mode_t", __cint_enum_map__portmod_loopback_mode_t }, 8189 {"portmod_core_port_mode_t", __cint_enum_map__portmod_core_port_mode_t }, 8190 {"portmod_port_mode_aux_info_t", __cint_enum_map__portmod_port_mode_aux_info_t }, 8191 {"portmod_prbs_mode_t", __cint_enum_map__portmod_prbs_mode_t }, 8192 {"portmod_ext_to_int_phy_ctrlcode_t", __cint_enum_map__portmod_ext_to_int_phy_ctrlcode_t }, 8193 {"portmod_cpm_core_mode_t", __cint_enum_map__portmod_cpm_core_mode_t }, 8194 {"portmod_core_port_enet_cpri_type_t", __cint_enum_map__portmod_core_port_enet_cpri_type_t }, 8195 {"portmod_qtc_mode_t", __cint_enum_map__portmod_qtc_mode_t }, 8196 {"portmod_vco_type_t", __cint_enum_map__portmod_vco_type_t }, 8197 {"portmod_call_back_action_type_t", __cint_enum_map__portmod_call_back_action_type_t }, 8198 {"portmod_intr_type_t", __cint_enum_map__portmod_intr_type_t }, 8199 {"portmod_stat_val_t", __cint_enum_map__portmod_stat_val_t }, 8200 {"portmod_preemption_control_t", __cint_enum_map__portmod_preemption_control_t }, 8201 {"portmod_preemption_tx_status_t", __cint_enum_map__portmod_preemption_tx_status_t }, 8202 {"portmod_preemption_verify_status_type_t", __cint_enum_map__portmod_preemption_verify_status_type_t }, 8203 {"portmod_preemption_verify_status_t", __cint_enum_map__portmod_preemption_verify_status_t }, 8204 {"portmod_preemption_force_rx_eop_mode_t", __cint_enum_map__portmod_preemption_force_rx_eop_mode_t }, 8205 #ifdef CPRIMOD_SUPPORT 8206 {"portmod_cpri_stage_t", __cint_enum_map__portmod_cpri_stage_t }, 8207 #endif /* CPRIMOD_SUPPORT */ 8208 { NULL } 8209 }; 8210 8211 /* Defines section */ 8212 static cint_constants_t __cint_constants[] = 8213 { 8214 { "PORTMOD_USER_ACCESS_FW_LOAD_REVERSE", PORTMOD_USER_ACCESS_FW_LOAD_REVERSE }, 8215 { "PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO", PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO }, 8216 { "PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST", PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST }, 8217 { "PORTMOD_MAC_PASS_CONTROL_FRAME", PORTMOD_MAC_PASS_CONTROL_FRAME }, 8218 { "PORTMOD_MAC_PASS_PFC_FRAME", PORTMOD_MAC_PASS_PFC_FRAME }, 8219 { "PORTMOD_MAC_PASS_PAUSE_FRAME", PORTMOD_MAC_PASS_PAUSE_FRAME }, 8220 { "PORTMOD_NUM_PATTERN_DATA_INTS", PORTMOD_NUM_PATTERN_DATA_INTS }, 8221 { "PORTMOD_TSCE_LANE_NAME_LEN", PORTMOD_TSCE_LANE_NAME_LEN }, 8222 { "PORTMOD_PCS_8B9B_LFEC", PORTMOD_PCS_8B9B_LFEC }, 8223 { "PORTMOD_PCS_8B10B", PORTMOD_PCS_8B10B }, 8224 { "PORTMOD_PCS_64B66B_FEC", PORTMOD_PCS_64B66B_FEC }, 8225 { "PORTMOD_PCS_64B66B_BEC", PORTMOD_PCS_64B66B_BEC }, 8226 { "PORTMOD_PCS_64B66B", PORTMOD_PCS_64B66B }, 8227 { "PORTMOD_PCS_64B66B_RS_FEC", PORTMOD_PCS_64B66B_RS_FEC }, 8228 { "PORTMOD_PCS_64B66B_LOW_LATENCY_RS_FEC", PORTMOD_PCS_64B66B_LOW_LATENCY_RS_FEC }, 8229 { "PORTMOD_PCS_64B66B_15T_RS_FEC", PORTMOD_PCS_64B66B_15T_RS_FEC }, 8230 { "PORTMOD_PCS_64B66B_15T_LOW_LATENCY_RS_FEC", PORTMOD_PCS_64B66B_15T_LOW_LATENCY_RS_FEC }, 8231 { "PORTMOD_PCS_UNKNOWN", PORTMOD_PCS_UNKNOWN }, 8232 { "PORTMOD_CL37_DISABLE", PORTMOD_CL37_DISABLE }, 8233 { "PORTMOD_CL37_W_BAM", PORTMOD_CL37_W_BAM }, 8234 { "PORTMOD_CL37_WO_BAM", PORTMOD_CL37_WO_BAM }, 8235 { "PORTMOD_CL37_W_10G", PORTMOD_CL37_W_10G }, 8236 { "PORTMOD_CL37_HR2SPM", PORTMOD_CL37_HR2SPM }, 8237 { "PORTMOD_CL37_HR2SPM_W_10G", PORTMOD_CL37_HR2SPM_W_10G }, 8238 { "PORTMOD_CL37_W_BAM_HG", PORTMOD_CL37_W_BAM_HG }, 8239 { "PORTMOD_CL37_SGMII_COMBO", PORTMOD_CL37_SGMII_COMBO }, 8240 { "PORTMOD_CL73_DISABLE", PORTMOD_CL73_DISABLE }, 8241 { "PORTMOD_CL73_WO_BAM", PORTMOD_CL73_WO_BAM }, 8242 { "PORTMOD_CL73_W_BAM", PORTMOD_CL73_W_BAM }, 8243 { "PORTMOD_CL73_MSA", PORTMOD_CL73_MSA }, 8244 { "PORTMOD_MSA", PORTMOD_MSA }, 8245 { "PORTMOD_CL73_CL37", PORTMOD_CL73_CL37 }, 8246 { "PORTMOD_CL73_HG", PORTMOD_CL73_HG }, 8247 { "PORTMOD_CL73_HPAM", PORTMOD_CL73_HPAM }, 8248 { "PORTMOD_CL73_HPAM_VS_SW", PORTMOD_CL73_HPAM_VS_SW }, 8249 { "PORTMOD_PORT_ENABLE_MAC", PORTMOD_PORT_ENABLE_MAC }, 8250 { "PORTMOD_PORT_ENABLE_PHY", PORTMOD_PORT_ENABLE_PHY }, 8251 { "PORTMOD_PORT_ENABLE_TX", PORTMOD_PORT_ENABLE_TX }, 8252 { "PORTMOD_PORT_ENABLE_RX", PORTMOD_PORT_ENABLE_RX }, 8253 { "PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY", PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY }, 8254 { "PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG", PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG }, 8255 { "PORTMOD_USER_SET_TX_AMP_BY_CONFIG", PORTMOD_USER_SET_TX_AMP_BY_CONFIG }, 8256 { "PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API", PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API }, 8257 { "PORTMOD_USER_SET_TX_AMP_BY_API", PORTMOD_USER_SET_TX_AMP_BY_API }, 8258 { "PORTMOD_ENCODING_LOW_LATENCY_LLFC", PORTMOD_ENCODING_LOW_LATENCY_LLFC }, 8259 { "PORTMOD_ENCODING_FEC_ERROR_DETECT", PORTMOD_ENCODING_FEC_ERROR_DETECT }, 8260 { "PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC", PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC }, 8261 { "PORTMOD_ENCODING_LLFC_AFTER_FEC", PORTMOD_ENCODING_LLFC_AFTER_FEC }, 8262 { "PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS", PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS }, 8263 { "PORTMOD_MAX_CORES_PER_PORT", PORTMOD_MAX_CORES_PER_PORT }, 8264 { "PORTMOD_TS_ADJUST_NUM_OLD", PORTMOD_TS_ADJUST_NUM_OLD }, 8265 { "PORTMOD_TS_ADJUST_NUM", PORTMOD_TS_ADJUST_NUM }, 8266 { "PORTMOD_PORT_ADD_F_INIT_PASS1", PORTMOD_PORT_ADD_F_INIT_PASS1 }, 8267 { "PORTMOD_PORT_ADD_F_INIT_PASS2", PORTMOD_PORT_ADD_F_INIT_PASS2 }, 8268 { "PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY", PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY }, 8269 { "PORTMOD_PORT_ADD_F_RX_SRIP_CRC", PORTMOD_PORT_ADD_F_RX_SRIP_CRC }, 8270 { "PORTMOD_PORT_ADD_F_TX_APPEND_CRC", PORTMOD_PORT_ADD_F_TX_APPEND_CRC }, 8271 { "PORTMOD_PORT_ADD_F_TX_REPLACE_CRC", PORTMOD_PORT_ADD_F_TX_REPLACE_CRC }, 8272 { "PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC", PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC }, 8273 { "PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT", PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT }, 8274 { "PORTMOD_PORT_ADD_F_INIT_CORE_PROBE", PORTMOD_PORT_ADD_F_INIT_CORE_PROBE }, 8275 { "PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP", PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP }, 8276 { "PORTMOD_PORT_ADD_F_ELK", PORTMOD_PORT_ADD_F_ELK }, 8277 { "PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE", PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE }, 8278 { "PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP", PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP }, 8279 { "PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST", PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST }, 8280 { "PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT", PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT }, 8281 { "PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2", PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2 }, 8282 { "PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5", PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5 }, 8283 { "PORTMOD_PORT_ADD_F_PCS_BYPASSED", PORTMOD_PORT_ADD_F_PCS_BYPASSED }, 8284 { "PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK", PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK }, 8285 { "PORTMOD_CORE_INIT_FLAG_INITIALZIED", PORTMOD_CORE_INIT_FLAG_INITIALZIED }, 8286 { "PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED", PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED }, 8287 { "PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED", PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED }, 8288 { "PORTMOD_PORT_PHY_FEC_INVALID", PORTMOD_PORT_PHY_FEC_INVALID }, 8289 { "PORTMOD_PORT_PHY_FEC_NONE", PORTMOD_PORT_PHY_FEC_NONE }, 8290 { "PORTMOD_PORT_PHY_FEC_BASE_R", PORTMOD_PORT_PHY_FEC_BASE_R }, 8291 { "PORTMOD_PORT_PHY_FEC_RS_FEC", PORTMOD_PORT_PHY_FEC_RS_FEC }, 8292 { "PORTMOD_PORT_PHY_FEC_RS_544", PORTMOD_PORT_PHY_FEC_RS_544 }, 8293 { "PORTMOD_PORT_PHY_FEC_RS_272", PORTMOD_PORT_PHY_FEC_RS_272 }, 8294 { "PORTMOD_PORT_PHY_FEC_RS_206", PORTMOD_PORT_PHY_FEC_RS_206 }, 8295 { "PORTMOD_PORT_PHY_FEC_RS_108", PORTMOD_PORT_PHY_FEC_RS_108 }, 8296 { "PORTMOD_PORT_PHY_FEC_RS_545", PORTMOD_PORT_PHY_FEC_RS_545 }, 8297 { "PORTMOD_PORT_PHY_FEC_RS_304", PORTMOD_PORT_PHY_FEC_RS_304 }, 8298 { "PORTMOD_PORT_PHY_FEC_RS_544_2XN", PORTMOD_PORT_PHY_FEC_RS_544_2XN }, 8299 { "PORTMOD_PORT_PHY_FEC_RS_272_2XN", PORTMOD_PORT_PHY_FEC_RS_272_2XN }, 8300 { "PORTMOD_PORT_PHY_FEC_FEC_COUNT", PORTMOD_PORT_PHY_FEC_FEC_COUNT }, 8301 { "PORTMOD_PORT_PHY_MEDIUM_COPPER", PORTMOD_PORT_PHY_MEDIUM_COPPER }, 8302 { "PORTMOD_PORT_PHY_MEDIUM_BACKPLANE", PORTMOD_PORT_PHY_MEDIUM_BACKPLANE }, 8303 { "PORTMOD_PORT_PHY_MEDIUM_ALL", PORTMOD_PORT_PHY_MEDIUM_ALL }, 8304 { "PORTMOD_PORT_PHY_PAUSE_NONE", PORTMOD_PORT_PHY_PAUSE_NONE }, 8305 { "PORTMOD_PORT_PHY_PAUSE_TX", PORTMOD_PORT_PHY_PAUSE_TX }, 8306 { "PORTMOD_PORT_PHY_PAUSE_RX", PORTMOD_PORT_PHY_PAUSE_RX }, 8307 { "PORTMOD_PORT_PHY_PAUSE_SYMM", PORTMOD_PORT_PHY_PAUSE_SYMM }, 8308 { "PORTMOD_PORT_PHY_PAUSE_ALL", PORTMOD_PORT_PHY_PAUSE_ALL }, 8309 { "PORTMOD_PORT_PHY_CHANNEL_SHORT", PORTMOD_PORT_PHY_CHANNEL_SHORT }, 8310 { "PORTMOD_PORT_PHY_CHANNEL_LONG", PORTMOD_PORT_PHY_CHANNEL_LONG }, 8311 { "PORTMOD_PORT_PHY_CHANNEL_ALL", PORTMOD_PORT_PHY_CHANNEL_ALL }, 8312 { "PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73", PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73 }, 8313 { "PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM", PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM }, 8314 { "PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_MSA", PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_MSA }, 8315 { "PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_NONE", PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_NONE }, 8316 { "PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION", PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION }, 8317 { "PORTMOD_NOF_FMACS_PER_PM8X50_FABRIC", PORTMOD_NOF_FMACS_PER_PM8X50_FABRIC }, 8318 { "PORTMOD_NOF_WORDS_PER_PM8X50_FABRIC_LANES_BITMAP", PORTMOD_NOF_WORDS_PER_PM8X50_FABRIC_LANES_BITMAP }, 8319 { "PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE", PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE }, 8320 { "PORTMOD_PM12x10_F_USE_PM_TD", PORTMOD_PM12x10_F_USE_PM_TD }, 8321 { "PORTMOD_PM12x10_F_USE_PM_XGS", PORTMOD_PM12x10_F_USE_PM_XGS }, 8322 { "PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM", PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM }, 8323 { "PORTMOD_SIDE_SYSTEM", PORTMOD_SIDE_SYSTEM }, 8324 { "PORTMOD_SIDE_LINE", PORTMOD_SIDE_LINE }, 8325 { "PORTMOD_PHYN_LAST_ONE", PORTMOD_PHYN_LAST_ONE }, 8326 { "PORTMOD_ALL_LANES_ARE_ACTIVE", PORTMOD_ALL_LANES_ARE_ACTIVE }, 8327 { "PORTMOD_NO_LANE_IS_ACTIVE", PORTMOD_NO_LANE_IS_ACTIVE }, 8328 { "PORTMOD_CREATE_F_PM_NULL", PORTMOD_CREATE_F_PM_NULL }, 8329 { "PORTMOD_EEE_ENABLE_LPI_BYPASS", PORTMOD_EEE_ENABLE_LPI_BYPASS }, 8330 { "PORTMOD_PORT_LINK_LATCH_DOWN_F_CLEAR", PORTMOD_PORT_LINK_LATCH_DOWN_F_CLEAR }, 8331 { "PORTMOD_PORT_UPDATE_F_DISABLE_MAC", PORTMOD_PORT_UPDATE_F_DISABLE_MAC }, 8332 { "PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK", PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK }, 8333 { "PORTMOD_PRIMARY_PORT_INVALID", PORTMOD_PRIMARY_PORT_INVALID }, 8334 { "PORTMOD_PORT_OFFSET_INVALID", PORTMOD_PORT_OFFSET_INVALID }, 8335 { "PORTMOD_CORE_INDEX_INVALID", PORTMOD_CORE_INDEX_INVALID }, 8336 { "PORTMOD_LANE_INDEX_INVALID", PORTMOD_LANE_INDEX_INVALID }, 8337 { "PORTMOD_XPHY_ID_INVALID", PORTMOD_XPHY_ID_INVALID }, 8338 { "PORTMOD_MAX_NUM_XPHY_SUPPORTED", PORTMOD_MAX_NUM_XPHY_SUPPORTED }, 8339 { "PORTMOD_XPHY_EXISTING_IDX", PORTMOD_XPHY_EXISTING_IDX }, 8340 { "PORTMOD_PORT_REG_ACCESS_DEFAULT", PORTMOD_PORT_REG_ACCESS_DEFAULT }, 8341 { "PORTMOD_PORT_REG_ACCESS_DIRECT", PORTMOD_PORT_REG_ACCESS_DIRECT }, 8342 { "PORTMOD_PORT_PGW_CONFIGURE", PORTMOD_PORT_PGW_CONFIGURE }, 8343 { "PORTMOD_PORT_PGW_MAC_RESET", PORTMOD_PORT_PGW_MAC_RESET }, 8344 { "PORTMOD_PORT_PGW_POWER_SAVE", PORTMOD_PORT_PGW_POWER_SAVE }, 8345 { "PORTMOD_PORT_PGW_MAC_UNRESET", PORTMOD_PORT_PGW_MAC_UNRESET }, 8346 { "PORTMOD_INIT_F_EXTERNAL_MOST_ONLY", PORTMOD_INIT_F_EXTERNAL_MOST_ONLY }, 8347 { "PORTMOD_INIT_F_ALL_PHYS", PORTMOD_INIT_F_ALL_PHYS }, 8348 { "PORTMOD_INIT_F_INTERNAL_SERDES_ONLY", PORTMOD_INIT_F_INTERNAL_SERDES_ONLY }, 8349 { "PORTMOD_INIT_F_EXTERNAL_PHYS_ONLY", PORTMOD_INIT_F_EXTERNAL_PHYS_ONLY }, 8350 { "PORTMOD_INIT_F_TX_ONLY", PORTMOD_INIT_F_TX_ONLY }, 8351 { "PORTMOD_INIT_F_RX_ONLY", PORTMOD_INIT_F_RX_ONLY }, 8352 { "PORTMOD_LANE_MAP_MAC_ONLY", PORTMOD_LANE_MAP_MAC_ONLY }, 8353 { "PORTMOD_SERDES_1000X_AT_6250", PORTMOD_SERDES_1000X_AT_6250 }, 8354 { "PORTMOD_SERDES_1000X_AT_12500", PORTMOD_SERDES_1000X_AT_12500 }, 8355 { "PORTMOD_SERDES_1000X_AT_25G", PORTMOD_SERDES_1000X_AT_25G }, 8356 { "PORTMOD_SERDES_10G_AT_25G", PORTMOD_SERDES_10G_AT_25G }, 8357 { "PORTMOD_LINK_RECOVERY_STATE_LINK_GOOD", PORTMOD_LINK_RECOVERY_STATE_LINK_GOOD }, 8358 { "PORTMOD_LINK_RECOVERY_STATE_WAIT_FOR_LINK", PORTMOD_LINK_RECOVERY_STATE_WAIT_FOR_LINK }, 8359 { "PORTMOD_LINK_RECOVERY_STATE_RESET_RX", PORTMOD_LINK_RECOVERY_STATE_RESET_RX }, 8360 { "PORTMOD_LINK_RECOVERY_LINK_WAIT_CNT_LIMIT", PORTMOD_LINK_RECOVERY_LINK_WAIT_CNT_LIMIT }, 8361 { "PORTMOD_PM_SPEED_VALIDATE_F_PLL_SWITCH_DEFAULT", PORTMOD_PM_SPEED_VALIDATE_F_PLL_SWITCH_DEFAULT }, 8362 { "PORTMOD_PM_SPEED_VALIDATE_F_PLL_SWITCH_NOT_ALLOWED", PORTMOD_PM_SPEED_VALIDATE_F_PLL_SWITCH_NOT_ALLOWED }, 8363 { "PORTMOD_PM_SPEED_VALIDATE_F_ONE_PLL_SWITCH_ALLOWED", PORTMOD_PM_SPEED_VALIDATE_F_ONE_PLL_SWITCH_ALLOWED }, 8364 { "PORTMOD_PM_SPEED_VALIDATE_F_TWO_PLL_SWITCH_ALLOWED", PORTMOD_PM_SPEED_VALIDATE_F_TWO_PLL_SWITCH_ALLOWED }, 8365 #ifdef CPRIMOD_SUPPORT 8366 { "PORTMOD_CPRI_HDLC_FCS_SIZE_8_BITS", PORTMOD_CPRI_HDLC_FCS_SIZE_8_BITS }, 8367 { "PORTMOD_CPRI_HDLC_FCS_SIZE_16_BITS", PORTMOD_CPRI_HDLC_FCS_SIZE_16_BITS }, 8368 { "PORTMOD_CPRI_HDLC_FCS_SIZE_32_BITS", PORTMOD_CPRI_HDLC_FCS_SIZE_32_BITS }, 8369 #endif /* CPRIMOD_SUPPORT */ 8370 #ifdef CPRIMOD_SUPPORT 8371 { "PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E", PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E }, 8372 { "PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7F", PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7F }, 8373 { "PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_FF", PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_FF }, 8374 #endif /* CPRIMOD_SUPPORT */ 8375 #ifdef CPRIMOD_SUPPORT 8376 { "PORTMOD_HDLC_FLAG_SIZE_1_BYTE", PORTMOD_HDLC_FLAG_SIZE_1_BYTE }, 8377 { "PORTMOD_HDLC_FLAG_SIZE_2_BYTE", PORTMOD_HDLC_FLAG_SIZE_2_BYTE }, 8378 #endif /* CPRIMOD_SUPPORT */ 8379 #ifdef CPRIMOD_SUPPORT 8380 { "PORTMOD_CPRI_HDLC_CRC_MODE_APPEND", PORTMOD_CPRI_HDLC_CRC_MODE_APPEND }, 8381 { "PORTMOD_CPRI_HDLC_CRC_MODE_REPLACE", PORTMOD_CPRI_HDLC_CRC_MODE_REPLACE }, 8382 { "PORTMOD_CPRI_HDLC_CRC_MODE_NO_UPDATE", PORTMOD_CPRI_HDLC_CRC_MODE_NO_UPDATE }, 8383 #endif /* CPRIMOD_SUPPORT */ 8384 #ifdef CPRIMOD_SUPPORT 8385 { "PORTMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_0", PORTMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_0 }, 8386 { "PORTMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1", PORTMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1 }, 8387 #endif /* CPRIMOD_SUPPORT */ 8388 { "PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1", PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1 }, 8389 { "PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2", PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2 }, 8390 { "PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4", PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4 }, 8391 { "PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_2", PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_2 }, 8392 { "PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_4", PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_4 }, 8393 { "PORTMOD_CPRI_CONTROL_FLOW_NUM_BYTES_2", PORTMOD_CPRI_CONTROL_FLOW_NUM_BYTES_2 }, 8394 { "PORTMOD_CPRI_CONTROL_FLOW_NUM_BYTES_4", PORTMOD_CPRI_CONTROL_FLOW_NUM_BYTES_4 }, 8395 #ifdef CPRIMOD_SUPPORT 8396 { "PORTMOD_CPRI_CW_FILTER_DISABLE", PORTMOD_CPRI_CW_FILTER_DISABLE }, 8397 { "PORTMOD_CPRI_CW_FILTER_NON_ZERO", PORTMOD_CPRI_CW_FILTER_NON_ZERO }, 8398 { "PORTMOD_CPRI_CW_FILTER_PERIODIC", PORTMOD_CPRI_CW_FILTER_PERIODIC }, 8399 { "PORTMOD_CPRI_CW_FILTER_CHANGE", PORTMOD_CPRI_CW_FILTER_CHANGE }, 8400 { "PORTMOD_CPRI_CW_FILTER_PATTERN_MATCH", PORTMOD_CPRI_CW_FILTER_PATTERN_MATCH }, 8401 #endif /* CPRIMOD_SUPPORT */ 8402 #ifdef CPRIMOD_SUPPORT 8403 { "PORTMOD_CPRI_CW_MAP_MODE_PERIODIC", PORTMOD_CPRI_CW_MAP_MODE_PERIODIC }, 8404 { "PORTMOD_CPRI_CW_MAP_MODE_ROE_FRAME", PORTMOD_CPRI_CW_MAP_MODE_ROE_FRAME }, 8405 #endif /* CPRIMOD_SUPPORT */ 8406 #ifdef CPRIMOD_SUPPORT 8407 { "PORTMOD_CPRI_GCW_MASK_NONE", PORTMOD_CPRI_GCW_MASK_NONE }, 8408 { "PORTMOD_CPRI_GCW_MASK_LSB", PORTMOD_CPRI_GCW_MASK_LSB }, 8409 { "PORTMOD_CPRI_GCW_MASK_MSB", PORTMOD_CPRI_GCW_MASK_MSB }, 8410 { "PORTMOD_CPRI_GCW_MASK_BOTH", PORTMOD_CPRI_GCW_MASK_BOTH }, 8411 #endif /* CPRIMOD_SUPPORT */ 8412 { "PORTMOD_CONTROL_MSG_PROC_TYPE_FE", PORTMOD_CONTROL_MSG_PROC_TYPE_FE }, 8413 { "PORTMOD_CONTROL_MSG_PROC_TYPE_FCB", PORTMOD_CONTROL_MSG_PROC_TYPE_FCB }, 8414 { "PORTMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD", PORTMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD }, 8415 { "PORTMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE", PORTMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE }, 8416 { "PORTMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG", PORTMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG }, 8417 { "PORTMOD_SYNC_COUNT_CYCLE_EVERY_MF", PORTMOD_SYNC_COUNT_CYCLE_EVERY_MF }, 8418 { "PORTMOD_SYNC_COUNT_CYCLE_UP_TO_6MF", PORTMOD_SYNC_COUNT_CYCLE_UP_TO_6MF }, 8419 #ifdef CPRIMOD_SUPPORT 8420 { "PORTMOD_CPRI_CRC_USE_ROE", PORTMOD_CPRI_CRC_USE_ROE }, 8421 { "PORTMOD_CPRI_CRC_REGENERATE", PORTMOD_CPRI_CRC_REGENERATE }, 8422 #endif /* CPRIMOD_SUPPORT */ 8423 { "PORTMOD_PM8x50_MAX_VCOS", PORTMOD_PM8x50_MAX_VCOS }, 8424 { "PORTMOD_PM8x50_NUM_PLLS", PORTMOD_PM8x50_NUM_PLLS }, 8425 { "PORTMOD_PM8x50_NUM_CORES", PORTMOD_PM8x50_NUM_CORES }, 8426 { "PORTMOD_PM8x50_NUM_LANES", PORTMOD_PM8x50_NUM_LANES }, 8427 { "PORTMOD_PM8X50_REV0_16NM", PORTMOD_PM8X50_REV0_16NM }, 8428 { "PORTMOD_ALLOW_20P625G_TVCO", PORTMOD_ALLOW_20P625G_TVCO }, 8429 { "PORTMOD_DIR_TX", PORTMOD_DIR_TX }, 8430 { "PORTMOD_DIR_RX", PORTMOD_DIR_RX }, 8431 { "PORTMOD_1588_TS_TYPE_FIFO", PORTMOD_1588_TS_TYPE_FIFO }, 8432 { "PORTMOD_1588_TS_TYPE_CMIC", PORTMOD_1588_TS_TYPE_CMIC }, 8433 { "PORTMOD_1588_TS_TYPE_SW_CAP", PORTMOD_1588_TS_TYPE_SW_CAP }, 8434 { "PORTMOD_CPRI_FRAME_SYNC_MODE_HYPER", PORTMOD_CPRI_FRAME_SYNC_MODE_HYPER }, 8435 { "PORTMOD_CPRI_FRAME_SYNC_MODE_RADIO", PORTMOD_CPRI_FRAME_SYNC_MODE_RADIO }, 8436 { "PORTMOD_CPRI_FRAME_SYNC_MODE_BASIC", PORTMOD_CPRI_FRAME_SYNC_MODE_BASIC }, 8437 { "PORTMOD_CPRI_FRAME_SYNC_MODE_TUNNEL", PORTMOD_CPRI_FRAME_SYNC_MODE_TUNNEL }, 8438 { "PORTMOD_CPRI_PAYLOAD_MULTIPLE_1X", PORTMOD_CPRI_PAYLOAD_MULTIPLE_1X }, 8439 { "PORTMOD_CPRI_PAYLOAD_MULTIPLE_1P5X", PORTMOD_CPRI_PAYLOAD_MULTIPLE_1P5X }, 8440 { "PORTMOD_CPRI_PAYLOAD_MULTIPLE_2X", PORTMOD_CPRI_PAYLOAD_MULTIPLE_2X }, 8441 { "PORTMOD_CPRI_PAYLOAD_MULTIPLE_4X", PORTMOD_CPRI_PAYLOAD_MULTIPLE_4X }, 8442 { "PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM", PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM }, 8443 { "PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP", PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP }, 8444 { "PORTMOD_ENCAP_PRESENTATION_TIME_ADJUST", PORTMOD_ENCAP_PRESENTATION_TIME_ADJUST }, 8445 { "PORTMOD_ENCAP_PRESENTATION_APPRIOX_INC", PORTMOD_ENCAP_PRESENTATION_APPRIOX_INC }, 8446 { "PORTMOD_CPRI_FEC_TS_SOURCE_66B", PORTMOD_CPRI_FEC_TS_SOURCE_66B }, 8447 { "PORTMOD_CPRI_FEC_TS_SOURCE_257B", PORTMOD_CPRI_FEC_TS_SOURCE_257B }, 8448 { "PORTMOD_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX", PORTMOD_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX }, 8449 { "PORTMOD_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX", PORTMOD_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX }, 8450 { "PORTMOD_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE", PORTMOD_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE }, 8451 { "PORTMOD_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE", PORTMOD_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE }, 8452 { "PORTMOD_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCK_ENABLE", PORTMOD_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCK_ENABLE }, 8453 { "PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE", PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE }, 8454 { "PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TIMER_PERIOD", PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TIMER_PERIOD }, 8455 { "PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_COUNT_THRESHOLD", PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_COUNT_THRESHOLD }, 8456 { "PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_WINDOW", PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_WINDOW }, 8457 { "PORTMOD_CPRI_FEC_AUX_CONFIG_TICK_DENOMINATOR", PORTMOD_CPRI_FEC_AUX_CONFIG_TICK_DENOMINATOR }, 8458 { "PORTMOD_CPRI_FEC_AUX_CONFIG_TICK_NUMERATOR", PORTMOD_CPRI_FEC_AUX_CONFIG_TICK_NUMERATOR }, 8459 { "PORTMOD_CPRI_FEC_AUX_CONFIG_SOFT_RESET", PORTMOD_CPRI_FEC_AUX_CONFIG_SOFT_RESET }, 8460 #ifdef CPRIMOD_SUPPORT 8461 { "PORTMOD_PM_CPRI_ECC_ERR_NONE", PORTMOD_PM_CPRI_ECC_ERR_NONE }, 8462 { "PORTMOD_PM_CPRI_ECC_ERR_1_BIT", PORTMOD_PM_CPRI_ECC_ERR_1_BIT }, 8463 { "PORTMOD_PM_CPRI_ECC_ERR_2_BIT", PORTMOD_PM_CPRI_ECC_ERR_2_BIT }, 8464 { "PORTMOD_PM_CPRI_ECC_ERR_MULTI_BIT", PORTMOD_PM_CPRI_ECC_ERR_MULTI_BIT }, 8465 #endif /* CPRIMOD_SUPPORT */ 8466 { "PORTMOD_PM_ECC_NO_ERR", PORTMOD_PM_ECC_NO_ERR }, 8467 { "PORTMOD_PM_ECC_1B_ERR", PORTMOD_PM_ECC_1B_ERR }, 8468 { "PORTMOD_PM_ECC_2B_ERR", PORTMOD_PM_ECC_2B_ERR }, 8469 { "PORTMOD_PM_ECC_MULTIB_ERR", PORTMOD_PM_ECC_MULTIB_ERR }, 8470 #ifdef CPRIMOD_SUPPORT 8471 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_0", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_0 }, 8472 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1 }, 8473 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2 }, 8474 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3 }, 8475 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_4", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_4 }, 8476 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_5", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_5 }, 8477 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_6", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_6 }, 8478 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_7", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_7 }, 8479 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_8", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_8 }, 8480 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_9", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_9 }, 8481 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_10", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_10 }, 8482 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_11", PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_11 }, 8483 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0", PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0 }, 8484 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1", PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1 }, 8485 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0", PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0 }, 8486 { "PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1", PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1 }, 8487 #endif /* CPRIMOD_SUPPORT */ 8488 #ifdef CPRIMOD_SUPPORT 8489 { "PORTMOD_CPRI_ROE_FRAME_FORMAT_IEEE1914", PORTMOD_CPRI_ROE_FRAME_FORMAT_IEEE1914 }, 8490 { "PORTMOD_CPRI_ROE_FRAME_FORMAT_RSVD3", PORTMOD_CPRI_ROE_FRAME_FORMAT_RSVD3 }, 8491 { "PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8", PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8 }, 8492 { "PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12", PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12 }, 8493 #endif /* CPRIMOD_SUPPORT */ 8494 { NULL } 8495 }; 8496 8497 8498 /* Typedefs section */ 8499 static cint_parameter_desc_t __cint_typedefs[] = 8500 { 8501 {"_shr_port_pcs_t", "portmod_port_pcs_t" , 0 , 0}, 8502 {"_shr_port_phy_fec_t", "portmod_fec_t" , 0 , 0}, 8503 {"_shr_port_encap_t", "portmod_encap_t" , 0 , 0}, 8504 {"_shr_port_medium_t", "portmod_port_medium_t" , 0 , 0}, 8505 {"_shr_port_phy_pause_t", "portmod_port_phy_pause_t" , 0 , 0}, 8506 {"_shr_port_phy_channel_t", "portmod_port_phy_channel_t" , 0 , 0}, 8507 {"_shr_port_phy_control_autoneg_mode_t", "portmod_port_phy_control_autoneg_mode_t" , 0 , 0}, 8508 {"soc_port_phy_timesync_config_t", "portmod_phy_timesync_config_t" , 0 , 0}, 8509 {"_shr_port_control_phy_timesync_t", "portmod_port_control_phy_timesync_t" , 0 , 0}, 8510 {"phymod_timesync_framesync_t", "portmod_timesync_framesync_t" , 0 , 0}, 8511 {"phymod_edc_config_t", "portmod_edc_config_t" , 0 , 0}, 8512 #ifdef CPRIMOD_SUPPORT 8513 {"_shr_cpri_cw_l1_protocol_info_t", "portmod_cpri_cw_l1_protocol_info_t" , 0 , 0}, 8514 #endif /* CPRIMOD_SUPPORT */ 8515 #ifdef CPRIMOD_SUPPORT 8516 {"_shr_cpri_hdlc_fcs_size_t", "portmod_cpri_hdlc_fcs_size_t" , 0 , 0}, 8517 #endif /* CPRIMOD_SUPPORT */ 8518 #ifdef CPRIMOD_SUPPORT 8519 {"_shr_cpri_hdlc_filling_flag_pattern_t", "portmod_cpri_hdlc_filling_flag_pattern_t" , 0 , 0}, 8520 #endif /* CPRIMOD_SUPPORT */ 8521 #ifdef CPRIMOD_SUPPORT 8522 {"_shr_cpri_hdlc_flag_size_t", "portmod_cpri_hdlc_num_flag_bytes_t" , 0 , 0}, 8523 #endif /* CPRIMOD_SUPPORT */ 8524 #ifdef CPRIMOD_SUPPORT 8525 {"_shr_cpri_hdlc_crc_mode_t", "portmod_cpri_crc_mode_t" , 0 , 0}, 8526 #endif /* CPRIMOD_SUPPORT */ 8527 #ifdef CPRIMOD_SUPPORT 8528 {"_shr_cpri_hdlc_crc_init_val_t", "portmod_cpri_hdlc_crc_init_val_t" , 0 , 0}, 8529 #endif /* CPRIMOD_SUPPORT */ 8530 {"_shr_cpri_vsd_control_subchan_num_bytes_t", "portmod_cpri_vsd_control_subchan_num_bytes_t" , 0 , 0}, 8531 {"_shr_cpri_vsd_control_subchan_size_t", "portmod_cpri_vsd_control_subchan_size_t" , 0 , 0}, 8532 {"_shr_cpri_vsd_control_flow_num_bytes_t", "portmod_cpri_vsd_control_flow_num_bytes_t" , 0 , 0}, 8533 #ifdef CPRIMOD_SUPPORT 8534 {"_shr_cpri_rx_vsd_flow_info_t", "portmod_cpri_rx_vsd_flow_info_t" , 0 , 0}, 8535 #endif /* CPRIMOD_SUPPORT */ 8536 {"_shr_cpri_tx_vsd_flow_info_t", "portmod_cpri_tx_vsd_flow_info_t" , 0 , 0}, 8537 #ifdef CPRIMOD_SUPPORT 8538 {"_shr_cpri_cw_filter_mode_t", "portmod_cpri_cw_filter_mode_t" , 0 , 0}, 8539 #endif /* CPRIMOD_SUPPORT */ 8540 #ifdef CPRIMOD_SUPPORT 8541 {"_shr_vsd_raw_map_mode_t", "portmod_cpri_vsd_raw_map_mode_t" , 0 , 0}, 8542 #endif /* CPRIMOD_SUPPORT */ 8543 #ifdef CPRIMOD_SUPPORT 8544 {"_shr_cpri_gcw_mask_t", "portmod_cpri_gcw_mask_t" , 0 , 0}, 8545 #endif /* CPRIMOD_SUPPORT */ 8546 #ifdef CPRIMOD_SUPPORT 8547 {"_shr_cpri_cw_l1_config_info_t", "portmod_cpri_cw_l1_config_info_t" , 0 , 0}, 8548 #endif /* CPRIMOD_SUPPORT */ 8549 {"_shr_rsvd4_control_msg_proc_type_t", "portmod_control_msg_proc_type_t" , 0 , 0}, 8550 #ifdef CPRIMOD_SUPPORT 8551 {"_shr_cpri_fast_eth_config_t", "portmod_cpri_fast_eth_config_t" , 0 , 0}, 8552 #endif /* CPRIMOD_SUPPORT */ 8553 {"_shr_rsvd4_sync_count_cycle_t", "portmod_sync_count_cycle_t" , 0 , 0}, 8554 {"_shr_cpri_tag_gen_entry_t", "portmod_tag_gen_entry_t" , 0 , 0}, 8555 #ifdef CPRIMOD_SUPPORT 8556 {"_shr_rsvd4_crc_option_t", "portmod_cpri_crc_option_t" , 0 , 0}, 8557 #endif /* CPRIMOD_SUPPORT */ 8558 {"_shr_cpri_interrupt_type_t", "portmod_cpri_port_intr_type_t" , 0 , 0}, 8559 {"_shr_cpri_port_interrupt_callback_t", "portmod_cpri_port_interrupt_callback_t" , 0 , 0}, 8560 {"_shr_cpri_dir_t", "portmod_direction_t" , 0 , 0}, 8561 {"_shr_cpri_1588_ts_type_t", "portmod_1588_ts_type_t" , 0 , 0}, 8562 {"_shr_cpri_frame_sync_mode_t", "portmod_cpri_frame_sync_mode_t" , 0 , 0}, 8563 {"_shr_cpri_roe_payload_multiple_t", "portmod_cpri_roe_payload_multiple_t" , 0 , 0}, 8564 {"_shr_cpri_roe_ordering_info_option_t", "portmod_cpri_roe_ordering_info_option_t" , 0 , 0}, 8565 {"_shr_cpri_presentation_ts_attribute_t", "portmod_presentation_time_attribute_t" , 0 , 0}, 8566 {"_shr_cpri_presentation_time_t", "portmod_presentation_time_t" , 0 , 0}, 8567 {"_shr_cpri_decap_presentation_config_t", "portmod_decap_presentation_time_config_t" , 0 , 0}, 8568 {"_shr_cpri_fec_ts_source_t", "portmod_fec_ts_source_t" , 0 , 0}, 8569 {"_shr_cpri_fec_aux_config_t", "portmod_fec_aux_config_para_t" , 0 , 0}, 8570 #ifdef CPRIMOD_SUPPORT 8571 {"portmod_ecc_intr_info_t", "portmod_cpri_ecc_intr_info_t" , 0 , 0}, 8572 #endif /* CPRIMOD_SUPPORT */ 8573 {"_shr_cpri_ecpri_header_field_t", "portmod_cpri_ecpri_header_field_t" , 0 , 0}, 8574 {"_shr_cpri_roe_frame_format_t", "portmod_cpri_roe_frame_format_t" , 0 , 0}, 8575 { NULL } 8576 }; 8577 8578 8579 cint_data_t portmod_cint_data = 8580 { 8581 NULL, 8582 __cint_functions, 8583 __cint_structures, 8584 __cint_enums, 8585 __cint_typedefs, 8586 __cint_constants, 8587 __cint_function_pointers, 8588 }; 8589 8590 8591 #endif /* defined(PORTMOD_SUPPORT) */ 8592 8593 #endif /* defined(INCLUDE_LIB_CINT) */