phymod_cint_data.c (176126B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 * 9 * 10 * DO NOT EDIT THIS FILE! 11 */ 12 13 #if defined(INCLUDE_LIB_CINT) 14 15 #include <cint_config.h> 16 #include <cint_types.h> 17 #include <cint_porting.h> 18 19 #if defined(PHYMOD_SUPPORT) 20 21 #include <phymod/phymod_diagnostics.h> 22 #include <phymod/phymod.h> 23 24 /* Macros section */ 25 26 /* Functions section */ 27 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 28 phymod_core_probe, 29 phymod_access_t*, phymod_access_t, access, 1, 0, 30 phymod_dispatch_type_t*, phymod_dispatch_type_t, type, 1, 0, 31 int*, int, is_probed, 1, 0); 32 33 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 34 phymod_core_identify, 35 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 36 uint32_t, uint32_t, core_id, 0, 0, 37 uint32_t*, uint32_t, is_identified, 1, 0); 38 39 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 40 phymod_core_info_get, 41 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 42 phymod_core_info_t*, phymod_core_info_t, info, 1, 0); 43 44 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 45 phymod_core_lane_map_get, 46 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 47 phymod_lane_map_t*, phymod_lane_map_t, lane_map, 1, 0); 48 49 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 50 phymod_core_lane_map_set, 51 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 52 phymod_lane_map_t*, phymod_lane_map_t, lane_map, 1, 0); 53 54 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 55 phymod_core_reset_get, 56 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 57 phymod_reset_mode_t, phymod_reset_mode_t, reset_mode, 0, 0, 58 phymod_reset_direction_t*, phymod_reset_direction_t, direction, 1, 0); 59 60 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 61 phymod_core_reset_set, 62 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 63 phymod_reset_mode_t, phymod_reset_mode_t, reset_mode, 0, 0, 64 phymod_reset_direction_t, phymod_reset_direction_t, direction, 0, 0); 65 66 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 67 phymod_core_firmware_info_get, 68 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 69 phymod_core_firmware_info_t*, phymod_core_firmware_info_t, fw_info, 1, 0); 70 71 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 72 phymod_phy_firmware_core_config_get, 73 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 74 phymod_firmware_core_config_t*, phymod_firmware_core_config_t, fw_core_config, 1, 0); 75 76 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 77 phymod_phy_firmware_core_config_set, 78 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 79 phymod_firmware_core_config_t, phymod_firmware_core_config_t, fw_core_config, 0, 0); 80 81 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 82 phymod_phy_firmware_lane_config_get, 83 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 84 phymod_firmware_lane_config_t*, phymod_firmware_lane_config_t, fw_lane_config, 1, 0); 85 86 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 87 phymod_phy_firmware_lane_config_set, 88 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 89 phymod_firmware_lane_config_t, phymod_firmware_lane_config_t, fw_lane_config, 0, 0); 90 91 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 92 phymod_core_pll_sequencer_restart, 93 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 94 uint32_t, uint32_t, flags, 0, 0, 95 phymod_sequencer_operation_t, phymod_sequencer_operation_t, operation, 0, 0); 96 97 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 98 phymod_core_wait_event, 99 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 100 phymod_core_event_t, phymod_core_event_t, event, 0, 0, 101 uint32_t, uint32_t, timeout, 0, 0); 102 103 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 104 phymod_phy_rx_restart, 105 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0); 106 107 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 108 phymod_phy_polarity_get, 109 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 110 phymod_polarity_t*, phymod_polarity_t, polarity, 1, 0); 111 112 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 113 phymod_phy_polarity_set, 114 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 115 phymod_polarity_t*, phymod_polarity_t, polarity, 1, 0); 116 117 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 118 phymod_phy_tx_get, 119 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 120 phymod_tx_t*, phymod_tx_t, tx, 1, 0); 121 122 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 123 phymod_phy_tx_set, 124 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 125 phymod_tx_t*, phymod_tx_t, tx, 1, 0); 126 127 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 128 phymod_phy_training_tx_fir_post_set, 129 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 130 uint8_t, uint8_t, tx_post, 0, 0); 131 132 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 133 phymod_phy_media_type_tx_get, 134 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 135 phymod_media_typed_t, phymod_media_typed_t, media, 0, 0, 136 phymod_tx_t*, phymod_tx_t, tx, 1, 0); 137 138 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 139 phymod_phy_tx_override_get, 140 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 141 phymod_tx_override_t*, phymod_tx_override_t, tx_override, 1, 0); 142 143 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 144 phymod_phy_tx_override_set, 145 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 146 phymod_tx_override_t*, phymod_tx_override_t, tx_override, 1, 0); 147 148 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 149 phymod_phy_txpi_config_get, 150 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 151 phymod_txpi_config_t*, phymod_txpi_config_t, config, 1, 0); 152 153 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 154 phymod_phy_txpi_config_set, 155 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 156 phymod_txpi_config_t*, phymod_txpi_config_t, config, 1, 0); 157 158 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 159 phymod_phy_rx_get, 160 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 161 phymod_rx_t*, phymod_rx_t, rx, 1, 0); 162 163 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 164 phymod_phy_rx_set, 165 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 166 phymod_rx_t*, phymod_rx_t, rx, 1, 0); 167 168 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 169 phymod_phy_rx_adaptation_resume, 170 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0); 171 172 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 173 phymod_phy_reset_get, 174 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 175 phymod_phy_reset_t*, phymod_phy_reset_t, reset, 1, 0); 176 177 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 178 phymod_phy_reset_set, 179 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 180 phymod_phy_reset_t*, phymod_phy_reset_t, reset, 1, 0); 181 182 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 183 phymod_phy_power_get, 184 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 185 phymod_phy_power_t*, phymod_phy_power_t, power, 1, 0); 186 187 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 188 phymod_phy_power_set, 189 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 190 phymod_phy_power_t*, phymod_phy_power_t, power, 1, 0); 191 192 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 193 phymod_phy_hg2_codec_control_get, 194 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 195 phymod_phy_hg2_codec_t*, phymod_phy_hg2_codec_t, hg2_codec, 1, 0); 196 197 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 198 phymod_phy_hg2_codec_control_set, 199 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 200 phymod_phy_hg2_codec_t, phymod_phy_hg2_codec_t, hg2_codec, 0, 0); 201 202 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 203 phymod_phy_tx_lane_control_get, 204 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 205 phymod_phy_tx_lane_control_t*, phymod_phy_tx_lane_control_t, tx_control, 1, 0); 206 207 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 208 phymod_phy_tx_lane_control_set, 209 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 210 phymod_phy_tx_lane_control_t, phymod_phy_tx_lane_control_t, tx_control, 0, 0); 211 212 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 213 phymod_phy_rx_lane_control_get, 214 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 215 phymod_phy_rx_lane_control_t*, phymod_phy_rx_lane_control_t, rx_control, 1, 0); 216 217 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 218 phymod_phy_rx_lane_control_set, 219 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 220 phymod_phy_rx_lane_control_t, phymod_phy_rx_lane_control_t, rx_control, 0, 0); 221 222 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 223 phymod_phy_fec_enable_get, 224 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 225 uint32_t*, uint32_t, enable, 1, 0); 226 227 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 228 phymod_phy_fec_enable_set, 229 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 230 uint32_t, uint32_t, enable, 0, 0); 231 232 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 233 phymod_phy_fec_override_get, 234 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 235 uint32_t*, uint32_t, enable, 1, 0); 236 237 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 238 phymod_phy_fec_override_set, 239 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 240 uint32_t, uint32_t, enable, 0, 0); 241 242 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 243 phymod_phy_forced_speed_line_side_get, 244 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 245 uint32_t*, uint32_t, speed, 1, 0); 246 247 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 248 phymod_phy_forced_speed_line_side_set, 249 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 250 uint32_t, uint32_t, speed, 0, 0); 251 252 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 253 phymod_phy_autoneg_line_side_get, 254 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 255 uint32_t*, uint32_t, enable, 1, 0); 256 257 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 258 phymod_phy_autoneg_line_side_set, 259 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 260 uint32_t, uint32_t, enable, 0, 0); 261 262 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 263 phymod_phy_flow_control_mode_get, 264 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 265 uint32_t, uint32_t, ingress, 0, 0, 266 uint32_t*, uint32_t, mode, 1, 0); 267 268 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 269 phymod_phy_flow_control_mode_set, 270 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 271 uint32_t, uint32_t, mode, 0, 0, 272 uint32_t, uint32_t, ingress, 0, 0); 273 274 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 275 phymod_phy_psm_cos_bmp_get, 276 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 277 uint32_t*, uint32_t, cos_bmp, 1, 0); 278 279 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 280 phymod_phy_psm_cos_bmp_set, 281 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 282 uint32_t, uint32_t, cos_bmp, 0, 0); 283 284 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 285 phymod_phy_pfc_use_ip_cos_get, 286 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 287 uint32_t*, uint32_t, enable, 1, 0); 288 289 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 290 phymod_phy_pfc_use_ip_cos_set, 291 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 292 uint32_t, uint32_t, enable, 0, 0); 293 294 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 295 phymod_phy_autoneg_oui_get, 296 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 297 phymod_autoneg_oui_t*, phymod_autoneg_oui_t, an_oui, 1, 0); 298 299 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 300 phymod_phy_autoneg_oui_set, 301 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 302 phymod_autoneg_oui_t, phymod_autoneg_oui_t, an_oui, 0, 0); 303 304 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 305 phymod_phy_eee_get, 306 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 307 uint32_t*, uint32_t, enable, 1, 0); 308 309 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 310 phymod_phy_eee_set, 311 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 312 uint32_t, uint32_t, enable, 0, 0); 313 314 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 315 phymod_phy_interface_config_get, 316 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 317 uint32_t, uint32_t, flags, 0, 0, 318 phymod_ref_clk_t, phymod_ref_clk_t, ref_clock, 0, 0, 319 phymod_phy_inf_config_t*, phymod_phy_inf_config_t, config, 1, 0); 320 321 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 322 phymod_phy_interface_config_set, 323 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 324 uint32_t, uint32_t, flags, 0, 0, 325 phymod_phy_inf_config_t*, phymod_phy_inf_config_t, config, 1, 0); 326 327 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 328 phymod_phy_cl72_get, 329 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 330 uint32_t*, uint32_t, cl72_en, 1, 0); 331 332 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 333 phymod_phy_cl72_set, 334 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 335 uint32_t, uint32_t, cl72_en, 0, 0); 336 337 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 338 phymod_phy_cl72_status_get, 339 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 340 phymod_cl72_status_t*, phymod_cl72_status_t, status, 1, 0); 341 342 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 343 phymod_phy_autoneg_ability_get, 344 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 345 phymod_autoneg_ability_t*, phymod_autoneg_ability_t, an_ability_get_type, 1, 0); 346 347 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 348 phymod_phy_autoneg_ability_set, 349 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 350 phymod_autoneg_ability_t*, phymod_autoneg_ability_t, an_ability_set_type, 1, 0); 351 352 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 353 phymod_phy_autoneg_remote_ability_get, 354 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 355 phymod_autoneg_ability_t*, phymod_autoneg_ability_t, an_ability_get_type, 1, 0); 356 357 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 358 phymod_phy_autoneg_get, 359 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 360 phymod_autoneg_control_t*, phymod_autoneg_control_t, an, 1, 0, 361 uint32_t*, uint32_t, an_done, 1, 0); 362 363 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 364 phymod_phy_autoneg_set, 365 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 366 phymod_autoneg_control_t*, phymod_autoneg_control_t, an, 1, 0); 367 368 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 369 phymod_phy_autoneg_restart_set, 370 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 371 phymod_autoneg_control_t*, phymod_autoneg_control_t, an, 1, 0); 372 373 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 374 phymod_phy_autoneg_status_get, 375 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 376 phymod_autoneg_status_t*, phymod_autoneg_status_t, status, 1, 0); 377 378 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 379 phymod_core_init, 380 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 381 phymod_core_init_config_t*, phymod_core_init_config_t, init_config, 1, 0, 382 phymod_core_status_t*, phymod_core_status_t, core_status, 1, 0); 383 384 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 385 phymod_phy_pll_multiplier_get, 386 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 387 uint32_t*, uint32_t, core_vco_pll_multiplier, 1, 0); 388 389 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 390 phymod_phy_init, 391 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 392 phymod_phy_init_config_t*, phymod_phy_init_config_t, init_config, 1, 0); 393 394 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 395 phymod_phy_loopback_get, 396 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 397 phymod_loopback_mode_t, phymod_loopback_mode_t, loopback, 0, 0, 398 uint32_t*, uint32_t, enable, 1, 0); 399 400 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 401 phymod_phy_loopback_set, 402 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 403 phymod_loopback_mode_t, phymod_loopback_mode_t, loopback, 0, 0, 404 uint32_t, uint32_t, enable, 0, 0); 405 406 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 407 phymod_phy_rx_pmd_locked_get, 408 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 409 uint32_t*, uint32_t, rx_pmd_locked, 1, 0); 410 411 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 412 phymod_phy_rx_signal_detect_get, 413 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 414 uint32_t*, uint32_t, rx_signal_detect, 1, 0); 415 416 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 417 phymod_phy_link_status_get, 418 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 419 uint32_t*, uint32_t, link_status, 1, 0); 420 421 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 422 phymod_phy_status_dump, 423 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0); 424 425 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 426 phymod_phy_pcs_userspeed_get, 427 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 428 phymod_pcs_userspeed_config_t*, phymod_pcs_userspeed_config_t, config, 1, 0); 429 430 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 431 phymod_phy_pcs_userspeed_set, 432 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 433 phymod_pcs_userspeed_config_t*, phymod_pcs_userspeed_config_t, config, 1, 0); 434 435 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 436 phymod_phy_reg_read, 437 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 438 uint32_t, uint32_t, reg_addr, 0, 0, 439 uint32_t*, uint32_t, val, 1, 0); 440 441 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 442 phymod_phy_reg_write, 443 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 444 uint32_t, uint32_t, reg_addr, 0, 0, 445 uint32_t, uint32_t, val, 0, 0); 446 447 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 448 phymod_phy_private_read, 449 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 450 uint32_t, uint32_t, addr, 0, 0, 451 uint32_t*, uint32_t, val, 1, 0); 452 453 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 454 phymod_phy_private_write, 455 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 456 uint32_t, uint32_t, addr, 0, 0, 457 uint32_t, uint32_t, val, 0, 0); 458 459 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 460 phymod_phy_rev_id, 461 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 462 uint32_t*, uint32_t, rev_id, 1, 0); 463 464 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 465 phymod_phy_lane_cross_switch_map_get, 466 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 467 uint32_t*, uint32_t, tx_array, 1, 0); 468 469 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 470 phymod_phy_lane_cross_switch_map_set, 471 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 472 uint32_t*, uint32_t, tx_array, 1, 0); 473 474 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 475 phymod_phy_intr_enable_get, 476 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 477 uint32_t*, uint32_t, enable, 1, 0); 478 479 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 480 phymod_phy_intr_enable_set, 481 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 482 uint32_t, uint32_t, enable, 0, 0); 483 484 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 485 phymod_phy_intr_status_get, 486 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 487 uint32_t*, uint32_t, intr_status, 1, 0); 488 489 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 490 phymod_phy_intr_status_clear, 491 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 492 uint32_t, uint32_t, intr_clr, 0, 0); 493 494 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 495 phymod_phy_i2c_read, 496 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 497 uint32_t, uint32_t, flags, 0, 0, 498 uint32_t, uint32_t, addr, 0, 0, 499 uint32_t, uint32_t, offset, 0, 0, 500 uint32_t, uint32_t, size, 0, 0, 501 uint8_t*, uint8_t, data, 1, 0); 502 503 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 504 phymod_phy_i2c_write, 505 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 506 uint32_t, uint32_t, flags, 0, 0, 507 uint32_t, uint32_t, addr, 0, 0, 508 uint32_t, uint32_t, offset, 0, 0, 509 uint32_t, uint32_t, size, 0, 0, 510 uint8_t*, uint8_t, data, 1, 0); 511 512 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 513 phymod_phy_gpio_config_get, 514 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 515 int, int, pin_no, 0, 0, 516 phymod_gpio_mode_t*, phymod_gpio_mode_t, gpio_mode, 1, 0); 517 518 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 519 phymod_phy_gpio_config_set, 520 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 521 int, int, pin_no, 0, 0, 522 phymod_gpio_mode_t, phymod_gpio_mode_t, gpio_mode, 0, 0); 523 524 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 525 phymod_phy_gpio_pin_value_get, 526 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 527 int, int, pin_no, 0, 0, 528 int*, int, value, 1, 0); 529 530 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 531 phymod_phy_gpio_pin_value_set, 532 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 533 int, int, pin_no, 0, 0, 534 int, int, value, 0, 0); 535 536 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 537 phymod_osr_mode_to_actual_os, 538 phymod_osr_mode_t, phymod_osr_mode_t, osr_mode, 0, 0, 539 uint32_t*, uint32_t, os_int, 1, 0, 540 uint32_t*, uint32_t, os_remainder, 1, 0); 541 542 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 543 phymod_timesync_config_get, 544 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 545 phymod_timesync_config_t*, phymod_timesync_config_t, config, 1, 0); 546 547 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 548 phymod_timesync_config_set, 549 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 550 phymod_timesync_config_t*, phymod_timesync_config_t, config, 1, 0); 551 552 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 553 phymod_timesync_enable_get, 554 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 555 uint32_t, uint32_t, flags, 0, 0, 556 uint32_t*, uint32_t, enable, 1, 0); 557 558 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 559 phymod_timesync_enable_set, 560 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 561 uint32_t, uint32_t, flags, 0, 0, 562 uint32_t, uint32_t, enable, 0, 0); 563 564 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 565 phymod_timesync_nco_addend_get, 566 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 567 uint32_t*, uint32_t, freq_step, 1, 0); 568 569 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 570 phymod_timesync_nco_addend_set, 571 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 572 uint32_t, uint32_t, freq_step, 0, 0); 573 574 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 575 phymod_timesync_framesync_mode_get, 576 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 577 phymod_timesync_framesync_t*, phymod_timesync_framesync_t, framesync, 1, 0); 578 579 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 580 phymod_timesync_framesync_mode_set, 581 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 582 phymod_timesync_framesync_t*, phymod_timesync_framesync_t, framesync, 1, 0); 583 584 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 585 phymod_timesync_local_time_get, 586 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 587 uint64_t*, uint64_t, local_time, 1, 0); 588 589 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 590 phymod_timesync_local_time_set, 591 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 592 uint64_t, uint64_t, local_time, 0, 0); 593 594 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 595 phymod_timesync_load_ctrl_get, 596 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 597 uint32_t*, uint32_t, load_once, 1, 0, 598 uint32_t*, uint32_t, load_always, 1, 0); 599 600 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 601 phymod_timesync_load_ctrl_set, 602 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 603 uint32_t, uint32_t, load_once, 0, 0, 604 uint32_t, uint32_t, load_always, 0, 0); 605 606 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 607 phymod_timesync_tx_timestamp_offset_get, 608 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 609 uint32_t*, uint32_t, ts_offset, 1, 0); 610 611 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 612 phymod_timesync_tx_timestamp_offset_set, 613 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 614 uint32_t, uint32_t, ts_offset, 0, 0); 615 616 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 617 phymod_timesync_rx_timestamp_offset_get, 618 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 619 uint32_t*, uint32_t, ts_offset, 1, 0); 620 621 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 622 phymod_timesync_rx_timestamp_offset_set, 623 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 624 uint32_t, uint32_t, ts_offset, 0, 0); 625 626 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 627 phymod_timesync_capture_timestamp_get, 628 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 629 uint64_t*, uint64_t, cap_ts, 1, 0); 630 631 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 632 phymod_timesync_heartbeat_timestamp_get, 633 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 634 uint64_t*, uint64_t, hb_ts, 1, 0); 635 636 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 637 phymod_timesync_do_sync, 638 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0); 639 640 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 641 phymod_timesync_offset_set, 642 phymod_core_access_t*, phymod_core_access_t, core, 1, 0, 643 uint32_t, uint32_t, ts_offset, 0, 0); 644 645 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 646 phymod_timesync_adjust_set, 647 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 648 phymod_timesync_compensation_mode_t, phymod_timesync_compensation_mode_t, ts_am_norm_mode, 0, 0); 649 650 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 651 phymod_edc_config_get, 652 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 653 phymod_edc_config_t*, phymod_edc_config_t, edc_config, 1, 0); 654 655 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 656 phymod_edc_config_set, 657 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 658 phymod_edc_config_t*, phymod_edc_config_t, edc_config, 1, 0); 659 660 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 661 phymod_phy_core_mode_get, 662 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 663 phymod_core_mode_t*, phymod_core_mode_t, core_mode, 1, 0); 664 665 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 666 phymod_phy_core_mode_set, 667 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 668 phymod_core_mode_t, phymod_core_mode_t, core_mode, 0, 0); 669 670 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 671 phymod_failover_mode_get, 672 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 673 phymod_failover_mode_t*, phymod_failover_mode_t, failover_mode, 1, 0); 674 675 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 676 phymod_failover_mode_set, 677 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 678 phymod_failover_mode_t, phymod_failover_mode_t, failover_mode, 0, 0); 679 680 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 681 phymod_port_init, 682 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 683 phymod_port_config_t*, phymod_port_config_t, port_config, 1, 0); 684 685 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 686 phymod_phy_autoneg_try_enable, 687 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 688 phymod_an_try_enable_control_t*, phymod_an_try_enable_control_t, an, 1, 0, 689 phymod_phy_an_status_t*, phymod_phy_an_status_t, an_status, 1, 0); 690 691 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 692 phymod_debug_ether, 693 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0); 694 695 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 696 phymod_reset_interface, 697 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0); 698 699 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 700 phymod_phy_short_chn_mode_enable_get, 701 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 702 uint32_t*, uint32_t, enable, 1, 0, 703 uint32_t*, uint32_t, status, 1, 0); 704 705 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 706 phymod_phy_short_chn_mode_enable_set, 707 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 708 uint32_t, uint32_t, enable, 0, 0); 709 710 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 711 phymod_port_enable_get, 712 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 713 uint32_t*, uint32_t, enable, 1, 0); 714 715 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 716 phymod_port_enable_set, 717 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 718 uint32_t, uint32_t, enable, 0, 0); 719 720 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 721 phymod_phy_eye_margin_est_get, 722 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 723 phymod_eye_margin_mode_t, phymod_eye_margin_mode_t, eye_margin_mode, 0, 0, 724 uint32_t*, uint32_t, value, 1, 0); 725 726 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 727 phymod_phy_multi_get, 728 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 729 phymod_multi_data_t*, phymod_multi_data_t, multi_data, 1, 0); 730 731 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 732 phymod_phy_rescal_get, 733 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 734 uint32_t*, uint32_t, value, 1, 0); 735 736 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 737 phymod_phy_rescal_set, 738 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 739 uint32_t, uint32_t, enable, 0, 0, 740 uint32_t, uint32_t, value, 0, 0); 741 742 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 743 phymod_phy_sw_an_control_status_get, 744 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 745 phymod_sw_an_ctrl_status_t*, phymod_sw_an_ctrl_status_t, an_ctrl_status, 1, 0); 746 747 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 748 phymod_phy_sw_an_base_page_exchange_handler, 749 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 750 phymod_sw_an_ctxt_t*, phymod_sw_an_ctxt_t, an_ctxt, 1, 0); 751 752 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 753 phymod_phy_sw_an_lp_page_rdy_handler, 754 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 755 phymod_sw_an_ctxt_t*, phymod_sw_an_ctxt_t, an_ctxt, 1, 0); 756 757 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 758 phymod_phy_sw_an_advert_set, 759 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 760 phymod_autoneg_ability_t*, phymod_autoneg_ability_t, an_ability_set_type, 1, 0, 761 phymod_sw_an_ctxt_t*, phymod_sw_an_ctxt_t, an_ctxt, 1, 0); 762 763 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 764 phymod_phy_sw_autoneg_enable, 765 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 766 int, int, enable, 0, 0); 767 768 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 769 phymod_phy_speed_config_get, 770 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 771 phymod_phy_speed_config_t*, phymod_phy_speed_config_t, speed_config, 1, 0); 772 773 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 774 phymod_phy_speed_config_set, 775 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 776 phymod_phy_speed_config_t*, phymod_phy_speed_config_t, speed_config, 1, 0, 777 phymod_phy_pll_state_t*, phymod_phy_pll_state_t, old_pll_state, 1, 0, 778 phymod_phy_pll_state_t*, phymod_phy_pll_state_t, new_pll_state, 1, 0); 779 780 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 781 phymod_phy_op_mode_get, 782 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 783 phymod_operation_mode_t*, phymod_operation_mode_t, op_mode, 1, 0); 784 785 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 786 phymod_phy_tx_taps_default_get, 787 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 788 phymod_phy_signalling_method_t, phymod_phy_signalling_method_t, mode, 0, 0, 789 phymod_tx_t*, phymod_tx_t, tx, 1, 0); 790 791 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 792 phymod_phy_lane_config_default_get, 793 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 794 phymod_phy_signalling_method_t, phymod_phy_signalling_method_t, mode, 0, 0, 795 phymod_firmware_lane_config_t*, phymod_firmware_lane_config_t, lane_config, 1, 0); 796 797 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 798 phymod_phy_firmware_load_info_get, 799 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 800 phymod_firmware_load_info_t*, phymod_firmware_load_info_t, info, 1, 0); 801 802 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 803 phymod_phy_autoneg_advert_ability_get, 804 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 805 phymod_autoneg_advert_abilities_t*, phymod_autoneg_advert_abilities_t, an_advert_abilities, 1, 0); 806 807 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 808 phymod_phy_autoneg_advert_ability_set, 809 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 810 phymod_autoneg_advert_abilities_t*, phymod_autoneg_advert_abilities_t, an_advert_abilities, 1, 0, 811 phymod_phy_pll_state_t*, phymod_phy_pll_state_t, old_pll_adv_state, 1, 0, 812 phymod_phy_pll_state_t*, phymod_phy_pll_state_t, new_pll_adv_state, 1, 0); 813 814 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 815 phymod_phy_autoneg_remote_advert_ability_get, 816 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 817 phymod_autoneg_advert_abilities_t*, phymod_autoneg_advert_abilities_t, an_advert_abilities, 1, 0); 818 819 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 820 phymod_phy_bond_in_pwrdn_override, 821 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 822 uint32_t, uint32_t, enable, 0, 0); 823 824 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 825 phymod_phy_tx_pam4_precoder_enable_get, 826 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 827 int*, int, enable, 1, 0); 828 829 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 830 phymod_phy_tx_pam4_precoder_enable_set, 831 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 832 int, int, enable, 0, 0); 833 834 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 835 phymod_phy_tx_phase_lock_set, 836 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 837 uint8_t, uint8_t, enable, 0, 0); 838 839 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 840 phymod_phy_pll_reconfig, 841 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 842 uint8_t, uint8_t, pll_index, 0, 0, 843 uint32_t, uint32_t, pll_div, 0, 0); 844 845 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 846 phymod_phy_pll_pwrdn, 847 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 848 uint32_t, uint32_t, pll_index, 0, 0, 849 uint32_t, uint32_t, pwrdn, 0, 0); 850 851 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 852 phymod_phy_linkdown_transmit_get, 853 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 854 uint32_t*, uint32_t, enable, 1, 0); 855 856 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 857 phymod_phy_linkdown_transmit_set, 858 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 859 uint32_t, uint32_t, enable, 0, 0); 860 861 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 862 phymod_phy_synce_clk_ctrl_get, 863 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 864 phymod_synce_clk_ctrl_t*, phymod_synce_clk_ctrl_t, cfg, 1, 0); 865 866 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 867 phymod_phy_synce_clk_ctrl_set, 868 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 869 phymod_synce_clk_ctrl_t, phymod_synce_clk_ctrl_t, cfg, 0, 0); 870 871 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 872 phymod_phy_pcs_enable_set, 873 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 874 uint32_t, uint32_t, enable, 0, 0); 875 876 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 877 phymod_phy_rx_ppm_get, 878 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 879 int16_t*, int16_t, rx_ppm, 1, 0); 880 881 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 882 phymod_phy_channel_loss_hint_get, 883 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 884 uint32_t*, uint32_t, channel_loss, 1, 0); 885 886 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 887 phymod_phy_channel_loss_hint_set, 888 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 889 uint32_t, uint32_t, channel_loss, 0, 0); 890 891 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 892 phymod_intr_handler, 893 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 894 phymod_interrupt_type_t, phymod_interrupt_type_t, type, 0, 0, 895 uint32_t*, uint32_t, is_handled, 1, 0); 896 897 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 898 phymod_timesync_tx_info_get, 899 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 900 phymod_ts_fifo_status_t*, phymod_ts_fifo_status_t, ts_tx_info, 1, 0); 901 902 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 903 phymod_phy_master_get, 904 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 905 phymod_master_mode_t*, phymod_master_mode_t, master_mode, 1, 0); 906 907 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 908 phymod_phy_master_set, 909 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 910 phymod_master_mode_t, phymod_master_mode_t, master_mode, 0, 0); 911 912 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 913 phymod_phy_pcs_lane_swap_adjust, 914 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 915 uint32_t, uint32_t, active_lane_map, 0, 0, 916 uint32_t, uint32_t, original_tx_lane_map, 0, 0, 917 uint32_t, uint32_t, original_rx_lane_map, 0, 0); 918 919 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 920 phymod_phy_load_speed_id_entry, 921 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 922 uint32_t, uint32_t, speed, 0, 0, 923 uint32_t, uint32_t, num_lane, 0, 0, 924 phymod_fec_type_t, phymod_fec_type_t, fec_type, 0, 0); 925 926 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 927 phymod_phy_pmd_override_enable_set, 928 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 929 phymod_override_type_t, phymod_override_type_t, pmd_override_type, 0, 0, 930 uint32_t, uint32_t, override_enable, 0, 0, 931 uint32_t, uint32_t, override_val, 0, 0); 932 933 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 934 phymod_phy_duplex_get, 935 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 936 phymod_duplex_mode_t*, phymod_duplex_mode_t, duplex, 1, 0); 937 938 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 939 phymod_phy_duplex_set, 940 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 941 phymod_duplex_mode_t, phymod_duplex_mode_t, duplex, 0, 0); 942 943 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 944 phymod_phy_pmd_info_init, 945 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0); 946 947 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 948 phymod_phy_pll_powerdown_get, 949 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 950 uint32_t, uint32_t, pll_index, 0, 0, 951 uint32_t*, uint32_t, powerdown, 1, 0); 952 953 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 954 phymod_phy_pmd_info_size_get, 955 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 956 uint32_t*, uint32_t, size, 1, 0); 957 958 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 959 phymod_phy_fec_bypass_indication_get, 960 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 961 uint32_t*, uint32_t, enable, 1, 0); 962 963 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 964 phymod_phy_fec_bypass_indication_set, 965 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 966 uint32_t, uint32_t, enable, 0, 0); 967 968 969 /* Functions and Macros mapping */ 970 static cint_function_t __cint_functions[] = 971 { 972 CINT_FWRAPPER_ENTRY(phymod_core_probe), 973 CINT_FWRAPPER_ENTRY(phymod_core_identify), 974 CINT_FWRAPPER_ENTRY(phymod_core_info_get), 975 CINT_FWRAPPER_ENTRY(phymod_core_lane_map_get), 976 CINT_FWRAPPER_ENTRY(phymod_core_lane_map_set), 977 CINT_FWRAPPER_ENTRY(phymod_core_reset_get), 978 CINT_FWRAPPER_ENTRY(phymod_core_reset_set), 979 CINT_FWRAPPER_ENTRY(phymod_core_firmware_info_get), 980 CINT_FWRAPPER_ENTRY(phymod_phy_firmware_core_config_get), 981 CINT_FWRAPPER_ENTRY(phymod_phy_firmware_core_config_set), 982 CINT_FWRAPPER_ENTRY(phymod_phy_firmware_lane_config_get), 983 CINT_FWRAPPER_ENTRY(phymod_phy_firmware_lane_config_set), 984 CINT_FWRAPPER_ENTRY(phymod_core_pll_sequencer_restart), 985 CINT_FWRAPPER_ENTRY(phymod_core_wait_event), 986 CINT_FWRAPPER_ENTRY(phymod_phy_rx_restart), 987 CINT_FWRAPPER_ENTRY(phymod_phy_polarity_get), 988 CINT_FWRAPPER_ENTRY(phymod_phy_polarity_set), 989 CINT_FWRAPPER_ENTRY(phymod_phy_tx_get), 990 CINT_FWRAPPER_ENTRY(phymod_phy_tx_set), 991 CINT_FWRAPPER_ENTRY(phymod_phy_training_tx_fir_post_set), 992 CINT_FWRAPPER_ENTRY(phymod_phy_media_type_tx_get), 993 CINT_FWRAPPER_ENTRY(phymod_phy_tx_override_get), 994 CINT_FWRAPPER_ENTRY(phymod_phy_tx_override_set), 995 CINT_FWRAPPER_ENTRY(phymod_phy_txpi_config_get), 996 CINT_FWRAPPER_ENTRY(phymod_phy_txpi_config_set), 997 CINT_FWRAPPER_ENTRY(phymod_phy_rx_get), 998 CINT_FWRAPPER_ENTRY(phymod_phy_rx_set), 999 CINT_FWRAPPER_ENTRY(phymod_phy_rx_adaptation_resume), 1000 CINT_FWRAPPER_ENTRY(phymod_phy_reset_get), 1001 CINT_FWRAPPER_ENTRY(phymod_phy_reset_set), 1002 CINT_FWRAPPER_ENTRY(phymod_phy_power_get), 1003 CINT_FWRAPPER_ENTRY(phymod_phy_power_set), 1004 CINT_FWRAPPER_ENTRY(phymod_phy_hg2_codec_control_get), 1005 CINT_FWRAPPER_ENTRY(phymod_phy_hg2_codec_control_set), 1006 CINT_FWRAPPER_ENTRY(phymod_phy_tx_lane_control_get), 1007 CINT_FWRAPPER_ENTRY(phymod_phy_tx_lane_control_set), 1008 CINT_FWRAPPER_ENTRY(phymod_phy_rx_lane_control_get), 1009 CINT_FWRAPPER_ENTRY(phymod_phy_rx_lane_control_set), 1010 CINT_FWRAPPER_ENTRY(phymod_phy_fec_enable_get), 1011 CINT_FWRAPPER_ENTRY(phymod_phy_fec_enable_set), 1012 CINT_FWRAPPER_ENTRY(phymod_phy_fec_override_get), 1013 CINT_FWRAPPER_ENTRY(phymod_phy_fec_override_set), 1014 CINT_FWRAPPER_ENTRY(phymod_phy_forced_speed_line_side_get), 1015 CINT_FWRAPPER_ENTRY(phymod_phy_forced_speed_line_side_set), 1016 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_line_side_get), 1017 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_line_side_set), 1018 CINT_FWRAPPER_ENTRY(phymod_phy_flow_control_mode_get), 1019 CINT_FWRAPPER_ENTRY(phymod_phy_flow_control_mode_set), 1020 CINT_FWRAPPER_ENTRY(phymod_phy_psm_cos_bmp_get), 1021 CINT_FWRAPPER_ENTRY(phymod_phy_psm_cos_bmp_set), 1022 CINT_FWRAPPER_ENTRY(phymod_phy_pfc_use_ip_cos_get), 1023 CINT_FWRAPPER_ENTRY(phymod_phy_pfc_use_ip_cos_set), 1024 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_oui_get), 1025 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_oui_set), 1026 CINT_FWRAPPER_ENTRY(phymod_phy_eee_get), 1027 CINT_FWRAPPER_ENTRY(phymod_phy_eee_set), 1028 CINT_FWRAPPER_ENTRY(phymod_phy_interface_config_get), 1029 CINT_FWRAPPER_ENTRY(phymod_phy_interface_config_set), 1030 CINT_FWRAPPER_ENTRY(phymod_phy_cl72_get), 1031 CINT_FWRAPPER_ENTRY(phymod_phy_cl72_set), 1032 CINT_FWRAPPER_ENTRY(phymod_phy_cl72_status_get), 1033 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_ability_get), 1034 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_ability_set), 1035 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_remote_ability_get), 1036 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_get), 1037 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_set), 1038 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_restart_set), 1039 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_status_get), 1040 CINT_FWRAPPER_ENTRY(phymod_core_init), 1041 CINT_FWRAPPER_ENTRY(phymod_phy_pll_multiplier_get), 1042 CINT_FWRAPPER_ENTRY(phymod_phy_init), 1043 CINT_FWRAPPER_ENTRY(phymod_phy_loopback_get), 1044 CINT_FWRAPPER_ENTRY(phymod_phy_loopback_set), 1045 CINT_FWRAPPER_ENTRY(phymod_phy_rx_pmd_locked_get), 1046 CINT_FWRAPPER_ENTRY(phymod_phy_rx_signal_detect_get), 1047 CINT_FWRAPPER_ENTRY(phymod_phy_link_status_get), 1048 CINT_FWRAPPER_ENTRY(phymod_phy_status_dump), 1049 CINT_FWRAPPER_ENTRY(phymod_phy_pcs_userspeed_get), 1050 CINT_FWRAPPER_ENTRY(phymod_phy_pcs_userspeed_set), 1051 CINT_FWRAPPER_ENTRY(phymod_phy_reg_read), 1052 CINT_FWRAPPER_ENTRY(phymod_phy_reg_write), 1053 CINT_FWRAPPER_ENTRY(phymod_phy_private_read), 1054 CINT_FWRAPPER_ENTRY(phymod_phy_private_write), 1055 CINT_FWRAPPER_ENTRY(phymod_phy_rev_id), 1056 CINT_FWRAPPER_ENTRY(phymod_phy_lane_cross_switch_map_get), 1057 CINT_FWRAPPER_ENTRY(phymod_phy_lane_cross_switch_map_set), 1058 CINT_FWRAPPER_ENTRY(phymod_phy_intr_enable_get), 1059 CINT_FWRAPPER_ENTRY(phymod_phy_intr_enable_set), 1060 CINT_FWRAPPER_ENTRY(phymod_phy_intr_status_get), 1061 CINT_FWRAPPER_ENTRY(phymod_phy_intr_status_clear), 1062 CINT_FWRAPPER_ENTRY(phymod_phy_i2c_read), 1063 CINT_FWRAPPER_ENTRY(phymod_phy_i2c_write), 1064 CINT_FWRAPPER_ENTRY(phymod_phy_gpio_config_get), 1065 CINT_FWRAPPER_ENTRY(phymod_phy_gpio_config_set), 1066 CINT_FWRAPPER_ENTRY(phymod_phy_gpio_pin_value_get), 1067 CINT_FWRAPPER_ENTRY(phymod_phy_gpio_pin_value_set), 1068 CINT_FWRAPPER_ENTRY(phymod_osr_mode_to_actual_os), 1069 CINT_FWRAPPER_ENTRY(phymod_timesync_config_get), 1070 CINT_FWRAPPER_ENTRY(phymod_timesync_config_set), 1071 CINT_FWRAPPER_ENTRY(phymod_timesync_enable_get), 1072 CINT_FWRAPPER_ENTRY(phymod_timesync_enable_set), 1073 CINT_FWRAPPER_ENTRY(phymod_timesync_nco_addend_get), 1074 CINT_FWRAPPER_ENTRY(phymod_timesync_nco_addend_set), 1075 CINT_FWRAPPER_ENTRY(phymod_timesync_framesync_mode_get), 1076 CINT_FWRAPPER_ENTRY(phymod_timesync_framesync_mode_set), 1077 CINT_FWRAPPER_ENTRY(phymod_timesync_local_time_get), 1078 CINT_FWRAPPER_ENTRY(phymod_timesync_local_time_set), 1079 CINT_FWRAPPER_ENTRY(phymod_timesync_load_ctrl_get), 1080 CINT_FWRAPPER_ENTRY(phymod_timesync_load_ctrl_set), 1081 CINT_FWRAPPER_ENTRY(phymod_timesync_tx_timestamp_offset_get), 1082 CINT_FWRAPPER_ENTRY(phymod_timesync_tx_timestamp_offset_set), 1083 CINT_FWRAPPER_ENTRY(phymod_timesync_rx_timestamp_offset_get), 1084 CINT_FWRAPPER_ENTRY(phymod_timesync_rx_timestamp_offset_set), 1085 CINT_FWRAPPER_ENTRY(phymod_timesync_capture_timestamp_get), 1086 CINT_FWRAPPER_ENTRY(phymod_timesync_heartbeat_timestamp_get), 1087 CINT_FWRAPPER_ENTRY(phymod_timesync_do_sync), 1088 CINT_FWRAPPER_ENTRY(phymod_timesync_offset_set), 1089 CINT_FWRAPPER_ENTRY(phymod_timesync_adjust_set), 1090 CINT_FWRAPPER_ENTRY(phymod_edc_config_get), 1091 CINT_FWRAPPER_ENTRY(phymod_edc_config_set), 1092 CINT_FWRAPPER_ENTRY(phymod_phy_core_mode_get), 1093 CINT_FWRAPPER_ENTRY(phymod_phy_core_mode_set), 1094 CINT_FWRAPPER_ENTRY(phymod_failover_mode_get), 1095 CINT_FWRAPPER_ENTRY(phymod_failover_mode_set), 1096 CINT_FWRAPPER_ENTRY(phymod_port_init), 1097 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_try_enable), 1098 CINT_FWRAPPER_ENTRY(phymod_debug_ether), 1099 CINT_FWRAPPER_ENTRY(phymod_reset_interface), 1100 CINT_FWRAPPER_ENTRY(phymod_phy_short_chn_mode_enable_get), 1101 CINT_FWRAPPER_ENTRY(phymod_phy_short_chn_mode_enable_set), 1102 CINT_FWRAPPER_ENTRY(phymod_port_enable_get), 1103 CINT_FWRAPPER_ENTRY(phymod_port_enable_set), 1104 CINT_FWRAPPER_ENTRY(phymod_phy_eye_margin_est_get), 1105 CINT_FWRAPPER_ENTRY(phymod_phy_multi_get), 1106 CINT_FWRAPPER_ENTRY(phymod_phy_rescal_get), 1107 CINT_FWRAPPER_ENTRY(phymod_phy_rescal_set), 1108 CINT_FWRAPPER_ENTRY(phymod_phy_sw_an_control_status_get), 1109 CINT_FWRAPPER_ENTRY(phymod_phy_sw_an_base_page_exchange_handler), 1110 CINT_FWRAPPER_ENTRY(phymod_phy_sw_an_lp_page_rdy_handler), 1111 CINT_FWRAPPER_ENTRY(phymod_phy_sw_an_advert_set), 1112 CINT_FWRAPPER_ENTRY(phymod_phy_sw_autoneg_enable), 1113 CINT_FWRAPPER_ENTRY(phymod_phy_speed_config_get), 1114 CINT_FWRAPPER_ENTRY(phymod_phy_speed_config_set), 1115 CINT_FWRAPPER_ENTRY(phymod_phy_op_mode_get), 1116 CINT_FWRAPPER_ENTRY(phymod_phy_tx_taps_default_get), 1117 CINT_FWRAPPER_ENTRY(phymod_phy_lane_config_default_get), 1118 CINT_FWRAPPER_ENTRY(phymod_phy_firmware_load_info_get), 1119 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_advert_ability_get), 1120 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_advert_ability_set), 1121 CINT_FWRAPPER_ENTRY(phymod_phy_autoneg_remote_advert_ability_get), 1122 CINT_FWRAPPER_ENTRY(phymod_phy_bond_in_pwrdn_override), 1123 CINT_FWRAPPER_ENTRY(phymod_phy_tx_pam4_precoder_enable_get), 1124 CINT_FWRAPPER_ENTRY(phymod_phy_tx_pam4_precoder_enable_set), 1125 CINT_FWRAPPER_ENTRY(phymod_phy_tx_phase_lock_set), 1126 CINT_FWRAPPER_ENTRY(phymod_phy_pll_reconfig), 1127 CINT_FWRAPPER_ENTRY(phymod_phy_pll_pwrdn), 1128 CINT_FWRAPPER_ENTRY(phymod_phy_linkdown_transmit_get), 1129 CINT_FWRAPPER_ENTRY(phymod_phy_linkdown_transmit_set), 1130 CINT_FWRAPPER_ENTRY(phymod_phy_synce_clk_ctrl_get), 1131 CINT_FWRAPPER_ENTRY(phymod_phy_synce_clk_ctrl_set), 1132 CINT_FWRAPPER_ENTRY(phymod_phy_pcs_enable_set), 1133 CINT_FWRAPPER_ENTRY(phymod_phy_rx_ppm_get), 1134 CINT_FWRAPPER_ENTRY(phymod_phy_channel_loss_hint_get), 1135 CINT_FWRAPPER_ENTRY(phymod_phy_channel_loss_hint_set), 1136 CINT_FWRAPPER_ENTRY(phymod_intr_handler), 1137 CINT_FWRAPPER_ENTRY(phymod_timesync_tx_info_get), 1138 CINT_FWRAPPER_ENTRY(phymod_phy_master_get), 1139 CINT_FWRAPPER_ENTRY(phymod_phy_master_set), 1140 CINT_FWRAPPER_ENTRY(phymod_phy_pcs_lane_swap_adjust), 1141 CINT_FWRAPPER_ENTRY(phymod_phy_load_speed_id_entry), 1142 CINT_FWRAPPER_ENTRY(phymod_phy_pmd_override_enable_set), 1143 CINT_FWRAPPER_ENTRY(phymod_phy_duplex_get), 1144 CINT_FWRAPPER_ENTRY(phymod_phy_duplex_set), 1145 CINT_FWRAPPER_ENTRY(phymod_phy_pmd_info_init), 1146 CINT_FWRAPPER_ENTRY(phymod_phy_pll_powerdown_get), 1147 CINT_FWRAPPER_ENTRY(phymod_phy_pmd_info_size_get), 1148 CINT_FWRAPPER_ENTRY(phymod_phy_fec_bypass_indication_get), 1149 CINT_FWRAPPER_ENTRY(phymod_phy_fec_bypass_indication_set), 1150 { NULL } 1151 }; 1152 1153 /* Functions pointers section */ 1154 static cint_function_pointer_t __cint_function_pointers[10]; 1155 1156 static int 1157 __cint_fpointer__phymod_bus_read_f(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t* val) 1158 { 1159 int returnval; 1160 1161 cint_interpreter_callback(__cint_function_pointers+0, 4, 1, &user_acc, &core_addr, ®_addr, &val, &returnval); 1162 return returnval; 1163 } 1164 1165 static int 1166 __cint_fpointer__phymod_bus_write_f(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t val) 1167 { 1168 int returnval; 1169 1170 cint_interpreter_callback(__cint_function_pointers+1, 4, 1, &user_acc, &core_addr, ®_addr, &val, &returnval); 1171 return returnval; 1172 } 1173 1174 static int 1175 __cint_fpointer__phymod_mem_read_f(void* user_acc, phymod_mem_type_t mem_type, uint32_t mem_index, uint32_t* val) 1176 { 1177 int returnval; 1178 1179 cint_interpreter_callback(__cint_function_pointers+2, 4, 1, &user_acc, &mem_type, &mem_index, &val, &returnval); 1180 return returnval; 1181 } 1182 1183 static int 1184 __cint_fpointer__phymod_mem_write_f(void* user_acc, phymod_mem_type_t mem_type, uint32_t mem_index, const uint32_t* val) 1185 { 1186 int returnval; 1187 1188 cint_interpreter_callback(__cint_function_pointers+3, 4, 1, &user_acc, &mem_type, &mem_index, &val, &returnval); 1189 return returnval; 1190 } 1191 1192 static int 1193 __cint_fpointer__phymod_bus_write_disabled_f(void* user_acc, uint32_t* val) 1194 { 1195 int returnval; 1196 1197 cint_interpreter_callback(__cint_function_pointers+4, 2, 1, &user_acc, &val, &returnval); 1198 return returnval; 1199 } 1200 1201 static int 1202 __cint_fpointer__phymod_bus_mutex_take_f(void* user_acc) 1203 { 1204 int returnval; 1205 1206 cint_interpreter_callback(__cint_function_pointers+5, 1, 1, &user_acc, &returnval); 1207 return returnval; 1208 } 1209 1210 static int 1211 __cint_fpointer__phymod_bus_mutex_give_f(void* user_acc) 1212 { 1213 int returnval; 1214 1215 cint_interpreter_callback(__cint_function_pointers+6, 1, 1, &user_acc, &returnval); 1216 return returnval; 1217 } 1218 1219 static int 1220 __cint_fpointer__phymod_ext_acc_f(void* acc_data) 1221 { 1222 int returnval; 1223 1224 cint_interpreter_callback(__cint_function_pointers+7, 1, 1, &acc_data, &returnval); 1225 return returnval; 1226 } 1227 1228 static int 1229 __cint_fpointer__phymod_firmware_loader_f(const phymod_core_access_t* core, uint32_t length, const uint8_t* data) 1230 { 1231 int returnval; 1232 1233 cint_interpreter_callback(__cint_function_pointers+8, 3, 1, &core, &length, &data, &returnval); 1234 return returnval; 1235 } 1236 1237 1238 static cint_parameter_desc_t __cint_parameters_phymod_bus_read_f[] = 1239 { 1240 {"int", "r", 0, 0}, 1241 {"void", "user_acc", 1, 0}, 1242 {"uint32_t", "core_addr", 0, 0}, 1243 {"uint32_t", "reg_addr", 0, 0}, 1244 {"uint32_t", "val", 1, 0}, 1245 { NULL } 1246 }; 1247 1248 static cint_parameter_desc_t __cint_parameters_phymod_bus_write_f[] = 1249 { 1250 {"int", "r", 0, 0}, 1251 {"void", "user_acc", 1, 0}, 1252 {"uint32_t", "core_addr", 0, 0}, 1253 {"uint32_t", "reg_addr", 0, 0}, 1254 {"uint32_t", "val", 0, 0}, 1255 { NULL } 1256 }; 1257 1258 static cint_parameter_desc_t __cint_parameters_phymod_mem_read_f[] = 1259 { 1260 {"int", "r", 0, 0}, 1261 {"void", "user_acc", 1, 0}, 1262 {"phymod_mem_type_t", "mem_type", 0, 0}, 1263 {"uint32_t", "mem_index", 0, 0}, 1264 {"uint32_t", "val", 1, 0}, 1265 { NULL } 1266 }; 1267 1268 static cint_parameter_desc_t __cint_parameters_phymod_mem_write_f[] = 1269 { 1270 {"int", "r", 0, 0}, 1271 {"void", "user_acc", 1, 0}, 1272 {"phymod_mem_type_t", "mem_type", 0, 0}, 1273 {"uint32_t", "mem_index", 0, 0}, 1274 {"const uint32_t", "val", 1, 0}, 1275 { NULL } 1276 }; 1277 1278 static cint_parameter_desc_t __cint_parameters_phymod_bus_write_disabled_f[] = 1279 { 1280 {"int", "r", 0, 0}, 1281 {"void", "user_acc", 1, 0}, 1282 {"uint32_t", "val", 1, 0}, 1283 { NULL } 1284 }; 1285 1286 static cint_parameter_desc_t __cint_parameters_phymod_bus_mutex_take_f[] = 1287 { 1288 {"int", "r", 0, 0}, 1289 {"void", "user_acc", 1, 0}, 1290 { NULL } 1291 }; 1292 1293 static cint_parameter_desc_t __cint_parameters_phymod_bus_mutex_give_f[] = 1294 { 1295 {"int", "r", 0, 0}, 1296 {"void", "user_acc", 1, 0}, 1297 { NULL } 1298 }; 1299 1300 static cint_parameter_desc_t __cint_parameters_phymod_ext_acc_f[] = 1301 { 1302 {"int", "r", 0, 0}, 1303 {"void", "acc_data", 1, 0}, 1304 { NULL } 1305 }; 1306 1307 static cint_parameter_desc_t __cint_parameters_phymod_firmware_loader_f[] = 1308 { 1309 {"int", "r", 0, 0}, 1310 {"const phymod_core_access_t", "core", 1, 0}, 1311 {"uint32_t", "length", 0, 0}, 1312 {"const uint8_t", "data", 1, 0}, 1313 { NULL } 1314 }; 1315 1316 1317 static cint_function_pointer_t __cint_function_pointers[] = 1318 { 1319 { 1320 "phymod_bus_read_f", 1321 (cint_fpointer_t) __cint_fpointer__phymod_bus_read_f, 1322 __cint_parameters_phymod_bus_read_f 1323 }, 1324 { 1325 "phymod_bus_write_f", 1326 (cint_fpointer_t) __cint_fpointer__phymod_bus_write_f, 1327 __cint_parameters_phymod_bus_write_f 1328 }, 1329 { 1330 "phymod_mem_read_f", 1331 (cint_fpointer_t) __cint_fpointer__phymod_mem_read_f, 1332 __cint_parameters_phymod_mem_read_f 1333 }, 1334 { 1335 "phymod_mem_write_f", 1336 (cint_fpointer_t) __cint_fpointer__phymod_mem_write_f, 1337 __cint_parameters_phymod_mem_write_f 1338 }, 1339 { 1340 "phymod_bus_write_disabled_f", 1341 (cint_fpointer_t) __cint_fpointer__phymod_bus_write_disabled_f, 1342 __cint_parameters_phymod_bus_write_disabled_f 1343 }, 1344 { 1345 "phymod_bus_mutex_take_f", 1346 (cint_fpointer_t) __cint_fpointer__phymod_bus_mutex_take_f, 1347 __cint_parameters_phymod_bus_mutex_take_f 1348 }, 1349 { 1350 "phymod_bus_mutex_give_f", 1351 (cint_fpointer_t) __cint_fpointer__phymod_bus_mutex_give_f, 1352 __cint_parameters_phymod_bus_mutex_give_f 1353 }, 1354 { 1355 "phymod_ext_acc_f", 1356 (cint_fpointer_t) __cint_fpointer__phymod_ext_acc_f, 1357 __cint_parameters_phymod_ext_acc_f 1358 }, 1359 { 1360 "phymod_firmware_loader_f", 1361 (cint_fpointer_t) __cint_fpointer__phymod_firmware_loader_f, 1362 __cint_parameters_phymod_firmware_loader_f 1363 }, 1364 { NULL } 1365 }; 1366 1367 /* Structs section */ 1368 static void* 1369 __cint_maddr__phymod_bus_t(void* p, int mnum, cint_struct_type_t* parent) 1370 { 1371 void* rv; 1372 phymod_bus_t* s = (phymod_bus_t*) p; 1373 switch(mnum) 1374 { 1375 case 0: rv = &(s->bus_name);break; 1376 case 1: rv = &(s->read);break; 1377 case 2: rv = &(s->write);break; 1378 case 3: rv = &(s->is_write_disabled);break; 1379 case 4: rv = &(s->mutex_take);break; 1380 case 5: rv = &(s->mutex_give);break; 1381 case 6: rv = &(s->mem_read);break; 1382 case 7: rv = &(s->mem_write);break; 1383 case 8: rv = &(s->bus_capabilities);break; 1384 default: rv = NULL; break; 1385 } 1386 return rv; 1387 } 1388 1389 static void* 1390 __cint_maddr__phymod_access_t(void* p, int mnum, cint_struct_type_t* parent) 1391 { 1392 void* rv; 1393 phymod_access_t* s = (phymod_access_t*) p; 1394 switch(mnum) 1395 { 1396 case 0: rv = &(s->user_acc);break; 1397 case 1: rv = &(s->ext_acc);break; 1398 case 2: rv = &(s->bus);break; 1399 case 3: rv = &(s->flags);break; 1400 case 4: rv = &(s->lane_mask);break; 1401 case 5: rv = &(s->addr);break; 1402 case 6: rv = &(s->devad);break; 1403 case 7: rv = &(s->pll_idx);break; 1404 case 8: rv = &(s->tvco_pll_index);break; 1405 case 9: rv = &(s->pmd_info_ptr);break; 1406 default: rv = NULL; break; 1407 } 1408 return rv; 1409 } 1410 1411 static void* 1412 __cint_maddr__phymod_core_access_t(void* p, int mnum, cint_struct_type_t* parent) 1413 { 1414 void* rv; 1415 phymod_core_access_t* s = (phymod_core_access_t*) p; 1416 switch(mnum) 1417 { 1418 case 0: rv = &(s->port_loc);break; 1419 case 1: rv = &(s->device_op_mode);break; 1420 case 2: rv = &(s->access);break; 1421 case 3: rv = &(s->type);break; 1422 default: rv = NULL; break; 1423 } 1424 return rv; 1425 } 1426 1427 static void* 1428 __cint_maddr__phymod_phy_access_t(void* p, int mnum, cint_struct_type_t* parent) 1429 { 1430 void* rv; 1431 phymod_phy_access_t* s = (phymod_phy_access_t*) p; 1432 switch(mnum) 1433 { 1434 case 0: rv = &(s->port_loc);break; 1435 case 1: rv = &(s->device_op_mode);break; 1436 case 2: rv = &(s->access);break; 1437 case 3: rv = &(s->type);break; 1438 default: rv = NULL; break; 1439 } 1440 return rv; 1441 } 1442 1443 static void* 1444 __cint_maddr__phymod_port_config_t(void* p, int mnum, cint_struct_type_t* parent) 1445 { 1446 void* rv; 1447 phymod_port_config_t* s = (phymod_port_config_t*) p; 1448 switch(mnum) 1449 { 1450 case 0: rv = &(s->speed);break; 1451 case 1: rv = &(s->interface);break; 1452 case 2: rv = &(s->sys_lane_count);break; 1453 case 3: rv = &(s->ln_lane_count);break; 1454 case 4: rv = &(s->an_mode);break; 1455 case 5: rv = &(s->an_cl72);break; 1456 case 6: rv = &(s->fs_cl72);break; 1457 case 7: rv = &(s->fs_cl72_sys);break; 1458 case 8: rv = &(s->an_fec);break; 1459 case 9: rv = &(s->port_is_higig);break; 1460 case 10: rv = &(s->fiber_pref);break; 1461 case 11: rv = &(s->fiber_pref_sys);break; 1462 case 12: rv = &(s->port_mode);break; 1463 case 13: rv = &(s->is_bootmaster);break; 1464 case 14: rv = &(s->fs_fec);break; 1465 case 15: rv = &(s->fs_fec_sys);break; 1466 case 16: rv = &(s->is_flex);break; 1467 case 17: rv = &(s->quad_mode);break; 1468 default: rv = NULL; break; 1469 } 1470 return rv; 1471 } 1472 1473 static void* 1474 __cint_maddr__phymod_value_override_t(void* p, int mnum, cint_struct_type_t* parent) 1475 { 1476 void* rv; 1477 phymod_value_override_t* s = (phymod_value_override_t*) p; 1478 switch(mnum) 1479 { 1480 case 0: rv = &(s->enable);break; 1481 case 1: rv = &(s->value);break; 1482 default: rv = NULL; break; 1483 } 1484 return rv; 1485 } 1486 1487 static void* 1488 __cint_maddr__phymod_core_info_t(void* p, int mnum, cint_struct_type_t* parent) 1489 { 1490 void* rv; 1491 phymod_core_info_t* s = (phymod_core_info_t*) p; 1492 switch(mnum) 1493 { 1494 case 0: rv = &(s->core_version);break; 1495 case 1: rv = &(s->serdes_id);break; 1496 case 2: rv = &(s->phy_id0);break; 1497 case 3: rv = &(s->phy_id1);break; 1498 case 4: rv = &(s->name);break; 1499 default: rv = NULL; break; 1500 } 1501 return rv; 1502 } 1503 1504 static void* 1505 __cint_maddr__phymod_lane_map_t(void* p, int mnum, cint_struct_type_t* parent) 1506 { 1507 void* rv; 1508 phymod_lane_map_t* s = (phymod_lane_map_t*) p; 1509 switch(mnum) 1510 { 1511 case 0: rv = &(s->num_of_lanes);break; 1512 case 1: rv = &(s->lane_map_rx);break; 1513 case 2: rv = &(s->lane_map_tx);break; 1514 default: rv = NULL; break; 1515 } 1516 return rv; 1517 } 1518 1519 static void* 1520 __cint_maddr__phymod_core_firmware_info_t(void* p, int mnum, cint_struct_type_t* parent) 1521 { 1522 void* rv; 1523 phymod_core_firmware_info_t* s = (phymod_core_firmware_info_t*) p; 1524 switch(mnum) 1525 { 1526 case 0: rv = &(s->fw_version);break; 1527 case 1: rv = &(s->fw_crc);break; 1528 default: rv = NULL; break; 1529 } 1530 return rv; 1531 } 1532 1533 static void* 1534 __cint_maddr__phymod_firmware_core_config_t(void* p, int mnum, cint_struct_type_t* parent) 1535 { 1536 void* rv; 1537 phymod_firmware_core_config_t* s = (phymod_firmware_core_config_t*) p; 1538 switch(mnum) 1539 { 1540 case 0: rv = &(s->CoreConfigFromPCS);break; 1541 case 1: rv = &(s->VcoRate);break; 1542 case 2: rv = &(s->disable_write_pll_iqp);break; 1543 case 3: rv = &(s->osr_2p5_available);break; 1544 default: rv = NULL; break; 1545 } 1546 return rv; 1547 } 1548 1549 static void* 1550 __cint_maddr__phymod_firmware_lane_config_t(void* p, int mnum, cint_struct_type_t* parent) 1551 { 1552 void* rv; 1553 phymod_firmware_lane_config_t* s = (phymod_firmware_lane_config_t*) p; 1554 switch(mnum) 1555 { 1556 case 0: rv = &(s->LaneConfigFromPCS);break; 1557 case 1: rv = &(s->AnEnabled);break; 1558 case 2: rv = &(s->DfeOn);break; 1559 case 3: rv = &(s->ForceBrDfe);break; 1560 case 4: rv = &(s->LpDfeOn);break; 1561 case 5: rv = &(s->MediaType);break; 1562 case 6: rv = &(s->UnreliableLos);break; 1563 case 7: rv = &(s->ScramblingDisable);break; 1564 case 8: rv = &(s->Cl72AutoPolEn);break; 1565 case 9: rv = &(s->Cl72RestTO);break; 1566 case 10: rv = &(s->ForceExtenedReach);break; 1567 case 11: rv = &(s->ForceNormalReach);break; 1568 case 12: rv = &(s->LpPrecoderEnabled);break; 1569 case 13: rv = &(s->ForcePAM4Mode);break; 1570 case 14: rv = &(s->ForceNRZMode);break; 1571 default: rv = NULL; break; 1572 } 1573 return rv; 1574 } 1575 1576 static void* 1577 __cint_maddr__phymod_polarity_t(void* p, int mnum, cint_struct_type_t* parent) 1578 { 1579 void* rv; 1580 phymod_polarity_t* s = (phymod_polarity_t*) p; 1581 switch(mnum) 1582 { 1583 case 0: rv = &(s->rx_polarity);break; 1584 case 1: rv = &(s->tx_polarity);break; 1585 default: rv = NULL; break; 1586 } 1587 return rv; 1588 } 1589 1590 static void* 1591 __cint_maddr__phymod_tx_t(void* p, int mnum, cint_struct_type_t* parent) 1592 { 1593 void* rv; 1594 phymod_tx_t* s = (phymod_tx_t*) p; 1595 switch(mnum) 1596 { 1597 case 0: rv = &(s->pre);break; 1598 case 1: rv = &(s->main);break; 1599 case 2: rv = &(s->post);break; 1600 case 3: rv = &(s->post2);break; 1601 case 4: rv = &(s->post3);break; 1602 case 5: rv = &(s->amp);break; 1603 case 6: rv = &(s->drivermode);break; 1604 case 7: rv = &(s->pre2);break; 1605 case 8: rv = &(s->tap_mode);break; 1606 case 9: rv = &(s->rpara);break; 1607 case 10: rv = &(s->sig_method);break; 1608 default: rv = NULL; break; 1609 } 1610 return rv; 1611 } 1612 1613 static void* 1614 __cint_maddr__phymod_tx_override_t(void* p, int mnum, cint_struct_type_t* parent) 1615 { 1616 void* rv; 1617 phymod_tx_override_t* s = (phymod_tx_override_t*) p; 1618 switch(mnum) 1619 { 1620 case 0: rv = &(s->phase_interpolator);break; 1621 default: rv = NULL; break; 1622 } 1623 return rv; 1624 } 1625 1626 static void* 1627 __cint_maddr__phymod_txpi_config_t(void* p, int mnum, cint_struct_type_t* parent) 1628 { 1629 void* rv; 1630 phymod_txpi_config_t* s = (phymod_txpi_config_t*) p; 1631 switch(mnum) 1632 { 1633 case 0: rv = &(s->enable);break; 1634 case 1: rv = &(s->mode);break; 1635 default: rv = NULL; break; 1636 } 1637 return rv; 1638 } 1639 1640 static void* 1641 __cint_maddr__phymod_rx_t(void* p, int mnum, cint_struct_type_t* parent) 1642 { 1643 void* rv; 1644 phymod_rx_t* s = (phymod_rx_t*) p; 1645 switch(mnum) 1646 { 1647 case 0: rv = &(s->vga);break; 1648 case 1: rv = &(s->num_of_dfe_taps);break; 1649 case 2: rv = &(s->dfe);break; 1650 case 3: rv = &(s->peaking_filter);break; 1651 case 4: rv = &(s->low_freq_peaking_filter);break; 1652 case 5: rv = &(s->high_freq_peaking_filter);break; 1653 case 6: rv = &(s->rx_adaptation_on);break; 1654 default: rv = NULL; break; 1655 } 1656 return rv; 1657 } 1658 1659 static void* 1660 __cint_maddr__phymod_phy_reset_t(void* p, int mnum, cint_struct_type_t* parent) 1661 { 1662 void* rv; 1663 phymod_phy_reset_t* s = (phymod_phy_reset_t*) p; 1664 switch(mnum) 1665 { 1666 case 0: rv = &(s->rx);break; 1667 case 1: rv = &(s->tx);break; 1668 default: rv = NULL; break; 1669 } 1670 return rv; 1671 } 1672 1673 static void* 1674 __cint_maddr__phymod_phy_power_t(void* p, int mnum, cint_struct_type_t* parent) 1675 { 1676 void* rv; 1677 phymod_phy_power_t* s = (phymod_phy_power_t*) p; 1678 switch(mnum) 1679 { 1680 case 0: rv = &(s->rx);break; 1681 case 1: rv = &(s->tx);break; 1682 default: rv = NULL; break; 1683 } 1684 return rv; 1685 } 1686 1687 static void* 1688 __cint_maddr__phymod_autoneg_oui_t(void* p, int mnum, cint_struct_type_t* parent) 1689 { 1690 void* rv; 1691 phymod_autoneg_oui_t* s = (phymod_autoneg_oui_t*) p; 1692 switch(mnum) 1693 { 1694 case 0: rv = &(s->oui);break; 1695 case 1: rv = &(s->oui_override_bam73_adv);break; 1696 case 2: rv = &(s->oui_override_bam73_det);break; 1697 case 3: rv = &(s->oui_override_hpam_adv);break; 1698 case 4: rv = &(s->oui_override_hpam_det);break; 1699 case 5: rv = &(s->oui_override_bam37_adv);break; 1700 case 6: rv = &(s->oui_override_bam37_det);break; 1701 default: rv = NULL; break; 1702 } 1703 return rv; 1704 } 1705 1706 static void* 1707 __cint_maddr__phymod_phy_inf_config_t(void* p, int mnum, cint_struct_type_t* parent) 1708 { 1709 void* rv; 1710 phymod_phy_inf_config_t* s = (phymod_phy_inf_config_t*) p; 1711 switch(mnum) 1712 { 1713 case 0: rv = &(s->interface_type);break; 1714 case 1: rv = &(s->data_rate);break; 1715 case 2: rv = &(s->interface_modes);break; 1716 case 3: rv = &(s->ref_clock);break; 1717 case 4: rv = &(s->com_clock);break; 1718 case 5: rv = &(s->pll_divider_req);break; 1719 case 6: rv = &(s->device_aux_modes);break; 1720 case 7: rv = &(s->otn_type);break; 1721 default: rv = NULL; break; 1722 } 1723 return rv; 1724 } 1725 1726 static void* 1727 __cint_maddr__phymod_cl72_status_t(void* p, int mnum, cint_struct_type_t* parent) 1728 { 1729 void* rv; 1730 phymod_cl72_status_t* s = (phymod_cl72_status_t*) p; 1731 switch(mnum) 1732 { 1733 case 0: rv = &(s->enabled);break; 1734 case 1: rv = &(s->locked);break; 1735 default: rv = NULL; break; 1736 } 1737 return rv; 1738 } 1739 1740 static void* 1741 __cint_maddr__phymod_autoneg_ability_t(void* p, int mnum, cint_struct_type_t* parent) 1742 { 1743 void* rv; 1744 phymod_autoneg_ability_t* s = (phymod_autoneg_ability_t*) p; 1745 switch(mnum) 1746 { 1747 case 0: rv = &(s->an_cap);break; 1748 case 1: rv = &(s->cl73bam_cap);break; 1749 case 2: rv = &(s->cl37bam_cap);break; 1750 case 3: rv = &(s->an_fec);break; 1751 case 4: rv = &(s->an_cl72);break; 1752 case 5: rv = &(s->an_hg2);break; 1753 case 6: rv = &(s->capabilities);break; 1754 case 7: rv = &(s->sgmii_speed);break; 1755 case 8: rv = &(s->an_master_lane);break; 1756 default: rv = NULL; break; 1757 } 1758 return rv; 1759 } 1760 1761 static void* 1762 __cint_maddr__phymod_autoneg_control_t(void* p, int mnum, cint_struct_type_t* parent) 1763 { 1764 void* rv; 1765 phymod_autoneg_control_t* s = (phymod_autoneg_control_t*) p; 1766 switch(mnum) 1767 { 1768 case 0: rv = &(s->an_mode);break; 1769 case 1: rv = &(s->num_lane_adv);break; 1770 case 2: rv = &(s->flags);break; 1771 case 3: rv = &(s->enable);break; 1772 default: rv = NULL; break; 1773 } 1774 return rv; 1775 } 1776 1777 static void* 1778 __cint_maddr__phymod_autoneg_status_t(void* p, int mnum, cint_struct_type_t* parent) 1779 { 1780 void* rv; 1781 phymod_autoneg_status_t* s = (phymod_autoneg_status_t*) p; 1782 switch(mnum) 1783 { 1784 case 0: rv = &(s->enabled);break; 1785 case 1: rv = &(s->locked);break; 1786 case 2: rv = &(s->data_rate);break; 1787 case 3: rv = &(s->interface);break; 1788 case 4: rv = &(s->resolved_num_lane);break; 1789 case 5: rv = &(s->resolved_port_mode);break; 1790 default: rv = NULL; break; 1791 } 1792 return rv; 1793 } 1794 1795 static void* 1796 __cint_maddr__phymod_afe_pll_t(void* p, int mnum, cint_struct_type_t* parent) 1797 { 1798 void* rv; 1799 phymod_afe_pll_t* s = (phymod_afe_pll_t*) p; 1800 switch(mnum) 1801 { 1802 case 0: rv = &(s->afe_pll_change_default);break; 1803 case 1: rv = &(s->ams_pll_iqp);break; 1804 case 2: rv = &(s->ams_pll_en_hrz);break; 1805 default: rv = NULL; break; 1806 } 1807 return rv; 1808 } 1809 1810 static void* 1811 __cint_maddr__phymod_core_init_config_t(void* p, int mnum, cint_struct_type_t* parent) 1812 { 1813 void* rv; 1814 phymod_core_init_config_t* s = (phymod_core_init_config_t*) p; 1815 switch(mnum) 1816 { 1817 case 0: rv = &(s->lane_map);break; 1818 case 1: rv = &(s->polarity_map);break; 1819 case 2: rv = &(s->firmware_load_method);break; 1820 case 3: rv = &(s->firmware_loader);break; 1821 case 4: rv = &(s->firmware_core_config);break; 1822 case 5: rv = &(s->interface);break; 1823 case 6: rv = &(s->flags);break; 1824 case 7: rv = &(s->op_datapath);break; 1825 case 8: rv = &(s->rx_fifo_sync_offset);break; 1826 case 9: rv = &(s->tx_fifo_sync_offset);break; 1827 case 10: rv = &(s->tx_input_voltage);break; 1828 case 11: rv = &(s->afe_pll);break; 1829 case 12: rv = &(s->core_mode);break; 1830 case 13: rv = &(s->trcvr_host_managed);break; 1831 case 14: rv = &(s->pll0_div_init_value);break; 1832 case 15: rv = &(s->pll1_div_init_value);break; 1833 default: rv = NULL; break; 1834 } 1835 return rv; 1836 } 1837 1838 static void* 1839 __cint_maddr__phymod_core_status_t(void* p, int mnum, cint_struct_type_t* parent) 1840 { 1841 void* rv; 1842 phymod_core_status_t* s = (phymod_core_status_t*) p; 1843 switch(mnum) 1844 { 1845 case 0: rv = &(s->pmd_active);break; 1846 default: rv = NULL; break; 1847 } 1848 return rv; 1849 } 1850 1851 static void* 1852 __cint_maddr__phymod_rx_los_t(void* p, int mnum, cint_struct_type_t* parent) 1853 { 1854 void* rv; 1855 phymod_rx_los_t* s = (phymod_rx_los_t*) p; 1856 switch(mnum) 1857 { 1858 case 0: rv = &(s->rx_los_en);break; 1859 case 1: rv = &(s->rx_los_invert_en);break; 1860 default: rv = NULL; break; 1861 } 1862 return rv; 1863 } 1864 1865 static void* 1866 __cint_maddr__phymod_phy_init_config_t(void* p, int mnum, cint_struct_type_t* parent) 1867 { 1868 void* rv; 1869 phymod_phy_init_config_t* s = (phymod_phy_init_config_t*) p; 1870 switch(mnum) 1871 { 1872 case 0: rv = &(s->polarity);break; 1873 case 1: rv = &(s->tx_params_user_flag);break; 1874 case 2: rv = &(s->tx);break; 1875 case 3: rv = &(s->cl72_en);break; 1876 case 4: rv = &(s->an_en);break; 1877 case 5: rv = &(s->op_mode);break; 1878 case 6: rv = &(s->an_link_qualifier);break; 1879 case 7: rv = &(s->interface);break; 1880 case 8: rv = &(s->rx_los);break; 1881 case 9: rv = &(s->ext_phy_tx_params_user_flag);break; 1882 case 10: rv = &(s->ext_phy_tx);break; 1883 case 11: rv = &(s->rx_swing);break; 1884 case 12: rv = &(s->flags);break; 1885 default: rv = NULL; break; 1886 } 1887 return rv; 1888 } 1889 1890 static void* 1891 __cint_maddr__phymod_pcs_userspeed_config_t(void* p, int mnum, cint_struct_type_t* parent) 1892 { 1893 void* rv; 1894 phymod_pcs_userspeed_config_t* s = (phymod_pcs_userspeed_config_t*) p; 1895 switch(mnum) 1896 { 1897 case 0: rv = &(s->mode);break; 1898 case 1: rv = &(s->param);break; 1899 case 2: rv = &(s->value);break; 1900 case 3: rv = &(s->current_entry);break; 1901 default: rv = NULL; break; 1902 } 1903 return rv; 1904 } 1905 1906 static void* 1907 __cint_maddr__phymod_timesync_timer_adjust_t(void* p, int mnum, cint_struct_type_t* parent) 1908 { 1909 void* rv; 1910 phymod_timesync_timer_adjust_t* s = (phymod_timesync_timer_adjust_t*) p; 1911 switch(mnum) 1912 { 1913 case 0: rv = &(s->mode);break; 1914 case 1: rv = &(s->delta);break; 1915 default: rv = NULL; break; 1916 } 1917 return rv; 1918 } 1919 1920 static void* 1921 __cint_maddr__phymod_timesync_inband_ctrl_t(void* p, int mnum, cint_struct_type_t* parent) 1922 { 1923 void* rv; 1924 phymod_timesync_inband_ctrl_t* s = (phymod_timesync_inband_ctrl_t*) p; 1925 switch(mnum) 1926 { 1927 case 0: rv = &(s->flags);break; 1928 case 1: rv = &(s->resv0_id);break; 1929 case 2: rv = &(s->timer_mode);break; 1930 default: rv = NULL; break; 1931 } 1932 return rv; 1933 } 1934 1935 static void* 1936 __cint_maddr__phymod_timesync_framesync_t(void* p, int mnum, cint_struct_type_t* parent) 1937 { 1938 void* rv; 1939 phymod_timesync_framesync_t* s = (phymod_timesync_framesync_t*) p; 1940 switch(mnum) 1941 { 1942 case 0: rv = &(s->mode);break; 1943 case 1: rv = &(s->length_threshold);break; 1944 case 2: rv = &(s->event_offset);break; 1945 default: rv = NULL; break; 1946 } 1947 return rv; 1948 } 1949 1950 static void* 1951 __cint_maddr__phymod_timesync_syncout_t(void* p, int mnum, cint_struct_type_t* parent) 1952 { 1953 void* rv; 1954 phymod_timesync_syncout_t* s = (phymod_timesync_syncout_t*) p; 1955 switch(mnum) 1956 { 1957 case 0: rv = &(s->pulse_1_length);break; 1958 case 1: rv = &(s->pulse_2_length);break; 1959 case 2: rv = &(s->interval);break; 1960 case 3: rv = &(s->timestamp);break; 1961 default: rv = NULL; break; 1962 } 1963 return rv; 1964 } 1965 1966 static void* 1967 __cint_maddr__phymod_timesync_timespec_t(void* p, int mnum, cint_struct_type_t* parent) 1968 { 1969 void* rv; 1970 phymod_timesync_timespec_t* s = (phymod_timesync_timespec_t*) p; 1971 switch(mnum) 1972 { 1973 case 0: rv = &(s->isnegative);break; 1974 case 1: rv = &(s->seconds);break; 1975 case 2: rv = &(s->nanoseconds);break; 1976 default: rv = NULL; break; 1977 } 1978 return rv; 1979 } 1980 1981 static void* 1982 __cint_maddr__phymod_timesync_mpls_label_t(void* p, int mnum, cint_struct_type_t* parent) 1983 { 1984 void* rv; 1985 phymod_timesync_mpls_label_t* s = (phymod_timesync_mpls_label_t*) p; 1986 switch(mnum) 1987 { 1988 case 0: rv = &(s->value);break; 1989 case 1: rv = &(s->mask);break; 1990 case 2: rv = &(s->flags);break; 1991 default: rv = NULL; break; 1992 } 1993 return rv; 1994 } 1995 1996 static void* 1997 __cint_maddr__phymod_timesync_mpls_ctrl_t(void* p, int mnum, cint_struct_type_t* parent) 1998 { 1999 void* rv; 2000 phymod_timesync_mpls_ctrl_t* s = (phymod_timesync_mpls_ctrl_t*) p; 2001 switch(mnum) 2002 { 2003 case 0: rv = &(s->flags);break; 2004 case 1: rv = &(s->special_label);break; 2005 case 2: rv = &(s->labels);break; 2006 case 3: rv = &(s->size);break; 2007 default: rv = NULL; break; 2008 } 2009 return rv; 2010 } 2011 2012 static void* 2013 __cint_maddr__phymod_timesync_config_t(void* p, int mnum, cint_struct_type_t* parent) 2014 { 2015 void* rv; 2016 phymod_timesync_config_t* s = (phymod_timesync_config_t*) p; 2017 switch(mnum) 2018 { 2019 case 0: rv = &(s->capabilities);break; 2020 case 1: rv = &(s->flags);break; 2021 case 2: rv = &(s->itpid);break; 2022 case 3: rv = &(s->otpid);break; 2023 case 4: rv = &(s->otpid2);break; 2024 case 5: rv = &(s->timer_adjust);break; 2025 case 6: rv = &(s->inband_ctrl);break; 2026 case 7: rv = &(s->gmode);break; 2027 case 8: rv = &(s->syncout);break; 2028 case 9: rv = &(s->ts_divider);break; 2029 case 10: rv = &(s->original_timecode);break; 2030 case 11: rv = &(s->rx_link_delay);break; 2031 case 12: rv = &(s->tx_sync_mode);break; 2032 case 13: rv = &(s->tx_delay_req_mode);break; 2033 case 14: rv = &(s->tx_pdelay_req_mode);break; 2034 case 15: rv = &(s->tx_pdelay_resp_mode);break; 2035 case 16: rv = &(s->rx_sync_mode);break; 2036 case 17: rv = &(s->rx_delay_req_mode);break; 2037 case 18: rv = &(s->rx_pdelay_req_mode);break; 2038 case 19: rv = &(s->rx_pdelay_resp_mode);break; 2039 case 20: rv = &(s->mpls_ctrl);break; 2040 case 21: rv = &(s->sync_freq);break; 2041 case 22: rv = &(s->phy_1588_dpll_k1);break; 2042 case 23: rv = &(s->phy_1588_dpll_k2);break; 2043 case 24: rv = &(s->phy_1588_dpll_k3);break; 2044 case 25: rv = &(s->phy_1588_dpll_loop_filter);break; 2045 case 26: rv = &(s->phy_1588_dpll_ref_phase);break; 2046 case 27: rv = &(s->phy_1588_dpll_ref_phase_delta);break; 2047 default: rv = NULL; break; 2048 } 2049 return rv; 2050 } 2051 2052 static void* 2053 __cint_maddr__phymod_edc_config_t(void* p, int mnum, cint_struct_type_t* parent) 2054 { 2055 void* rv; 2056 phymod_edc_config_t* s = (phymod_edc_config_t*) p; 2057 switch(mnum) 2058 { 2059 case 0: rv = &(s->method);break; 2060 case 1: rv = &(s->mode_val);break; 2061 default: rv = NULL; break; 2062 } 2063 return rv; 2064 } 2065 2066 static void* 2067 __cint_maddr__phymod_an_try_enable_control_t(void* p, int mnum, cint_struct_type_t* parent) 2068 { 2069 void* rv; 2070 phymod_an_try_enable_control_t* s = (phymod_an_try_enable_control_t*) p; 2071 switch(mnum) 2072 { 2073 case 0: rv = &(s->an_mode);break; 2074 case 1: rv = &(s->num_lane_adv);break; 2075 case 2: rv = &(s->flags);break; 2076 case 3: rv = &(s->enable);break; 2077 case 4: rv = &(s->speed);break; 2078 default: rv = NULL; break; 2079 } 2080 return rv; 2081 } 2082 2083 static void* 2084 __cint_maddr__phymod_phy_an_status_t(void* p, int mnum, cint_struct_type_t* parent) 2085 { 2086 void* rv; 2087 phymod_phy_an_status_t* s = (phymod_phy_an_status_t*) p; 2088 switch(mnum) 2089 { 2090 case 0: rv = &(s->hcd_speed);break; 2091 case 1: rv = &(s->result);break; 2092 default: rv = NULL; break; 2093 } 2094 return rv; 2095 } 2096 2097 static void* 2098 __cint_maddr__phymod_multi_data_t(void* p, int mnum, cint_struct_type_t* parent) 2099 { 2100 void* rv; 2101 phymod_multi_data_t* s = (phymod_multi_data_t*) p; 2102 switch(mnum) 2103 { 2104 case 0: rv = &(s->flags);break; 2105 case 1: rv = &(s->dev_addr);break; 2106 case 2: rv = &(s->offset);break; 2107 case 3: rv = &(s->max_size);break; 2108 case 4: rv = &(s->data);break; 2109 case 5: rv = &(s->actual_size);break; 2110 default: rv = NULL; break; 2111 } 2112 return rv; 2113 } 2114 2115 static void* 2116 __cint_maddr__phymod_an_page_t(void* p, int mnum, cint_struct_type_t* parent) 2117 { 2118 void* rv; 2119 phymod_an_page_t* s = (phymod_an_page_t*) p; 2120 switch(mnum) 2121 { 2122 case 0: rv = &(s->page_0);break; 2123 case 1: rv = &(s->page_1);break; 2124 case 2: rv = &(s->page_2);break; 2125 default: rv = NULL; break; 2126 } 2127 return rv; 2128 } 2129 2130 static void* 2131 __cint_maddr__phymod_sw_an_ctrl_status_t(void* p, int mnum, cint_struct_type_t* parent) 2132 { 2133 void* rv; 2134 phymod_sw_an_ctrl_status_t* s = (phymod_sw_an_ctrl_status_t*) p; 2135 switch(mnum) 2136 { 2137 case 0: rv = &(s->seq_restart);break; 2138 case 1: rv = &(s->lp_page_rdy);break; 2139 case 2: rv = &(s->page_req);break; 2140 case 3: rv = &(s->an_completed);break; 2141 default: rv = NULL; break; 2142 } 2143 return rv; 2144 } 2145 2146 static void* 2147 __cint_maddr__phymod_an_pages_t(void* p, int mnum, cint_struct_type_t* parent) 2148 { 2149 void* rv; 2150 phymod_an_pages_t* s = (phymod_an_pages_t*) p; 2151 switch(mnum) 2152 { 2153 case 0: rv = &(s->base_page);break; 2154 case 1: rv = &(s->msg_page);break; 2155 case 2: rv = &(s->ufmt_page);break; 2156 case 3: rv = &(s->null_page);break; 2157 default: rv = NULL; break; 2158 } 2159 return rv; 2160 } 2161 2162 static void* 2163 __cint_maddr__phymod_sw_an_ctxt_t(void* p, int mnum, cint_struct_type_t* parent) 2164 { 2165 void* rv; 2166 phymod_sw_an_ctxt_t* s = (phymod_sw_an_ctxt_t*) p; 2167 switch(mnum) 2168 { 2169 case 0: rv = &(s->tx_pages);break; 2170 case 1: rv = &(s->rx_pages);break; 2171 case 2: rv = &(s->no_pages_to_be_txed);break; 2172 case 3: rv = &(s->tx_pages_cnt);break; 2173 case 4: rv = &(s->rx_pages_cnt);break; 2174 case 5: rv = &(s->an_mode);break; 2175 default: rv = NULL; break; 2176 } 2177 return rv; 2178 } 2179 2180 static void* 2181 __cint_maddr__phymod_phy_speed_config_t(void* p, int mnum, cint_struct_type_t* parent) 2182 { 2183 void* rv; 2184 phymod_phy_speed_config_t* s = (phymod_phy_speed_config_t*) p; 2185 switch(mnum) 2186 { 2187 case 0: rv = &(s->data_rate);break; 2188 case 1: rv = &(s->fec_type);break; 2189 case 2: rv = &(s->linkTraining);break; 2190 case 3: rv = &(s->flags);break; 2191 case 4: rv = &(s->PAM4_channel_loss);break; 2192 case 5: rv = &(s->pmd_lane_config);break; 2193 default: rv = NULL; break; 2194 } 2195 return rv; 2196 } 2197 2198 static void* 2199 __cint_maddr__phymod_phy_pll_state_t(void* p, int mnum, cint_struct_type_t* parent) 2200 { 2201 void* rv; 2202 phymod_phy_pll_state_t* s = (phymod_phy_pll_state_t*) p; 2203 switch(mnum) 2204 { 2205 case 0: rv = &(s->pll0_lanes_bitmap);break; 2206 case 1: rv = &(s->pll1_lanes_bitmap);break; 2207 default: rv = NULL; break; 2208 } 2209 return rv; 2210 } 2211 2212 static void* 2213 __cint_maddr__phymod_dual_plls_t(void* p, int mnum, cint_struct_type_t* parent) 2214 { 2215 void* rv; 2216 phymod_dual_plls_t* s = (phymod_dual_plls_t*) p; 2217 switch(mnum) 2218 { 2219 case 0: rv = &(s->pll0_div);break; 2220 case 1: rv = &(s->pll1_div);break; 2221 default: rv = NULL; break; 2222 } 2223 return rv; 2224 } 2225 2226 static void* 2227 __cint_maddr__phymod_firmware_load_info_t(void* p, int mnum, cint_struct_type_t* parent) 2228 { 2229 void* rv; 2230 phymod_firmware_load_info_t* s = (phymod_firmware_load_info_t*) p; 2231 switch(mnum) 2232 { 2233 case 0: rv = &(s->ucode_ptr);break; 2234 case 1: rv = &(s->ucode_len);break; 2235 default: rv = NULL; break; 2236 } 2237 return rv; 2238 } 2239 2240 static void* 2241 __cint_maddr__phymod_autoneg_advert_ability_t(void* p, int mnum, cint_struct_type_t* parent) 2242 { 2243 void* rv; 2244 phymod_autoneg_advert_ability_t* s = (phymod_autoneg_advert_ability_t*) p; 2245 switch(mnum) 2246 { 2247 case 0: rv = &(s->speed);break; 2248 case 1: rv = &(s->resolved_num_lanes);break; 2249 case 2: rv = &(s->fec);break; 2250 case 3: rv = &(s->pause);break; 2251 case 4: rv = &(s->medium);break; 2252 case 5: rv = &(s->channel);break; 2253 case 6: rv = &(s->an_mode);break; 2254 default: rv = NULL; break; 2255 } 2256 return rv; 2257 } 2258 2259 static void* 2260 __cint_maddr__phymod_autoneg_advert_abilities_t(void* p, int mnum, cint_struct_type_t* parent) 2261 { 2262 void* rv; 2263 phymod_autoneg_advert_abilities_t* s = (phymod_autoneg_advert_abilities_t*) p; 2264 switch(mnum) 2265 { 2266 case 0: rv = &(s->num_abilities);break; 2267 case 1: rv = &(s->autoneg_abilities);break; 2268 default: rv = NULL; break; 2269 } 2270 return rv; 2271 } 2272 2273 static void* 2274 __cint_maddr__phymod_synce_clk_ctrl_t(void* p, int mnum, cint_struct_type_t* parent) 2275 { 2276 void* rv; 2277 phymod_synce_clk_ctrl_t* s = (phymod_synce_clk_ctrl_t*) p; 2278 switch(mnum) 2279 { 2280 case 0: rv = &(s->stg0_mode);break; 2281 case 1: rv = &(s->stg1_mode);break; 2282 case 2: rv = &(s->sdm_val);break; 2283 default: rv = NULL; break; 2284 } 2285 return rv; 2286 } 2287 2288 static void* 2289 __cint_maddr__phymod_ts_fifo_status_t(void* p, int mnum, cint_struct_type_t* parent) 2290 { 2291 void* rv; 2292 phymod_ts_fifo_status_t* s = (phymod_ts_fifo_status_t*) p; 2293 switch(mnum) 2294 { 2295 case 0: rv = &(s->ts_in_fifo_lo);break; 2296 case 1: rv = &(s->ts_in_fifo_hi);break; 2297 case 2: rv = &(s->ts_seq_id);break; 2298 case 3: rv = &(s->ts_sub_nanosec);break; 2299 default: rv = NULL; break; 2300 } 2301 return rv; 2302 } 2303 2304 2305 static cint_parameter_desc_t __cint_struct_members__phymod_bus_t[] = 2306 { 2307 {"char", "bus_name", 1, 0}, 2308 {"phymod_bus_read_f", "read", 0, 0}, 2309 {"phymod_bus_write_f", "write", 0, 0}, 2310 {"phymod_bus_write_disabled_f", "is_write_disabled", 0, 0}, 2311 {"phymod_bus_mutex_take_f", "mutex_take", 0, 0}, 2312 {"phymod_bus_mutex_give_f", "mutex_give", 0, 0}, 2313 {"phymod_mem_read_f", "mem_read", 0, 0}, 2314 {"phymod_mem_write_f", "mem_write", 0, 0}, 2315 {"uint32_t", "bus_capabilities", 0, 0}, 2316 { NULL } 2317 }; 2318 2319 static cint_parameter_desc_t __cint_struct_members__phymod_access_t[] = 2320 { 2321 {"void", "user_acc", 1, 0}, 2322 {"phymod_ext_acc_f", "ext_acc", 0, 0}, 2323 {"phymod_bus_t", "bus", 1, 0}, 2324 {"uint32_t", "flags", 0, 0}, 2325 {"uint32_t", "lane_mask", 0, 0}, 2326 {"uint32_t", "addr", 0, 0}, 2327 {"uint32_t", "devad", 0, 0}, 2328 {"uint8_t", "pll_idx", 0, 0}, 2329 {"uint8_t", "tvco_pll_index", 0, 0}, 2330 {"void", "pmd_info_ptr", 1, 0}, 2331 { NULL } 2332 }; 2333 2334 static cint_parameter_desc_t __cint_struct_members__phymod_core_access_t[] = 2335 { 2336 {"phymod_port_loc_t", "port_loc", 0, 0}, 2337 {"uint32_t", "device_op_mode", 0, 0}, 2338 {"phymod_access_t", "access", 0, 0}, 2339 {"phymod_dispatch_type_t", "type", 0, 0}, 2340 { NULL } 2341 }; 2342 2343 static cint_parameter_desc_t __cint_struct_members__phymod_phy_access_t[] = 2344 { 2345 {"phymod_port_loc_t", "port_loc", 0, 0}, 2346 {"uint32_t", "device_op_mode", 0, 0}, 2347 {"phymod_access_t", "access", 0, 0}, 2348 {"phymod_dispatch_type_t", "type", 0, 0}, 2349 { NULL } 2350 }; 2351 2352 static cint_parameter_desc_t __cint_struct_members__phymod_port_config_t[] = 2353 { 2354 {"uint32_t", "speed", 0, 0}, 2355 {"uint8_t", "interface", 0, 0}, 2356 {"uint8_t", "sys_lane_count", 0, 0}, 2357 {"uint8_t", "ln_lane_count", 0, 0}, 2358 {"uint8_t", "an_mode", 0, 0}, 2359 {"uint8_t", "an_cl72", 0, 0}, 2360 {"uint8_t", "fs_cl72", 0, 0}, 2361 {"uint8_t", "fs_cl72_sys", 0, 0}, 2362 {"uint8_t", "an_fec", 0, 0}, 2363 {"uint8_t", "port_is_higig", 0, 0}, 2364 {"uint8_t", "fiber_pref", 0, 0}, 2365 {"uint8_t", "fiber_pref_sys", 0, 0}, 2366 {"uint8_t", "port_mode", 0, 0}, 2367 {"uint8_t", "is_bootmaster", 0, 0}, 2368 {"uint8_t", "fs_fec", 0, 0}, 2369 {"uint8_t", "fs_fec_sys", 0, 0}, 2370 {"uint8_t", "is_flex", 0, 0}, 2371 {"uint8_t", "quad_mode", 0, 0}, 2372 { NULL } 2373 }; 2374 2375 static cint_parameter_desc_t __cint_struct_members__phymod_value_override_t[] = 2376 { 2377 {"uint32_t", "enable", 0, 0}, 2378 {"int32_t", "value", 0, 0}, 2379 { NULL } 2380 }; 2381 2382 static cint_parameter_desc_t __cint_struct_members__phymod_core_info_t[] = 2383 { 2384 {"phymod_core_version_t", "core_version", 0, 0}, 2385 {"uint32_t", "serdes_id", 0, 0}, 2386 {"uint32_t", "phy_id0", 0, 0}, 2387 {"uint32_t", "phy_id1", 0, 0}, 2388 {"char", "name", 0, 30}, 2389 { NULL } 2390 }; 2391 2392 static cint_parameter_desc_t __cint_struct_members__phymod_lane_map_t[] = 2393 { 2394 {"uint32_t", "num_of_lanes", 0, 0}, 2395 {"uint32_t", "lane_map_rx", 0, PHYMOD_MAX_LANES_PER_CORE}, 2396 {"uint32_t", "lane_map_tx", 0, PHYMOD_MAX_LANES_PER_CORE}, 2397 { NULL } 2398 }; 2399 2400 static cint_parameter_desc_t __cint_struct_members__phymod_core_firmware_info_t[] = 2401 { 2402 {"uint32_t", "fw_version", 0, 0}, 2403 {"uint32_t", "fw_crc", 0, 0}, 2404 { NULL } 2405 }; 2406 2407 static cint_parameter_desc_t __cint_struct_members__phymod_firmware_core_config_t[] = 2408 { 2409 {"uint32_t", "CoreConfigFromPCS", 0, 0}, 2410 {"uint32_t", "VcoRate", 0, 0}, 2411 {"uint32_t", "disable_write_pll_iqp", 0, 0}, 2412 {"uint32_t", "osr_2p5_available", 0, 0}, 2413 { NULL } 2414 }; 2415 2416 static cint_parameter_desc_t __cint_struct_members__phymod_firmware_lane_config_t[] = 2417 { 2418 {"uint32_t", "LaneConfigFromPCS", 0, 0}, 2419 {"uint32_t", "AnEnabled", 0, 0}, 2420 {"uint32_t", "DfeOn", 0, 0}, 2421 {"uint32_t", "ForceBrDfe", 0, 0}, 2422 {"uint32_t", "LpDfeOn", 0, 0}, 2423 {"phymod_firmware_media_type_t", "MediaType", 0, 0}, 2424 {"uint32_t", "UnreliableLos", 0, 0}, 2425 {"uint32_t", "ScramblingDisable", 0, 0}, 2426 {"uint32_t", "Cl72AutoPolEn", 0, 0}, 2427 {"uint32_t", "Cl72RestTO", 0, 0}, 2428 {"uint32_t", "ForceExtenedReach", 0, 0}, 2429 {"uint32_t", "ForceNormalReach", 0, 0}, 2430 {"uint32_t", "LpPrecoderEnabled", 0, 0}, 2431 {"uint32_t", "ForcePAM4Mode", 0, 0}, 2432 {"uint32_t", "ForceNRZMode", 0, 0}, 2433 { NULL } 2434 }; 2435 2436 static cint_parameter_desc_t __cint_struct_members__phymod_polarity_t[] = 2437 { 2438 {"uint32_t", "rx_polarity", 0, 0}, 2439 {"uint32_t", "tx_polarity", 0, 0}, 2440 { NULL } 2441 }; 2442 2443 static cint_parameter_desc_t __cint_struct_members__phymod_tx_t[] = 2444 { 2445 {"int16_t", "pre", 0, 0}, 2446 {"int16_t", "main", 0, 0}, 2447 {"int16_t", "post", 0, 0}, 2448 {"int16_t", "post2", 0, 0}, 2449 {"int16_t", "post3", 0, 0}, 2450 {"int16_t", "amp", 0, 0}, 2451 {"int16_t", "drivermode", 0, 0}, 2452 {"int16_t", "pre2", 0, 0}, 2453 {"phymod_tx_tap_mode_t", "tap_mode", 0, 0}, 2454 {"int16_t", "rpara", 0, 0}, 2455 {"phymod_phy_signalling_method_t", "sig_method", 0, 0}, 2456 { NULL } 2457 }; 2458 2459 static cint_parameter_desc_t __cint_struct_members__phymod_tx_override_t[] = 2460 { 2461 {"phymod_value_override_t", "phase_interpolator", 0, 0}, 2462 { NULL } 2463 }; 2464 2465 static cint_parameter_desc_t __cint_struct_members__phymod_txpi_config_t[] = 2466 { 2467 {"uint32_t", "enable", 0, 0}, 2468 {"uint32_t", "mode", 0, 0}, 2469 { NULL } 2470 }; 2471 2472 static cint_parameter_desc_t __cint_struct_members__phymod_rx_t[] = 2473 { 2474 {"phymod_value_override_t", "vga", 0, 0}, 2475 {"uint32_t", "num_of_dfe_taps", 0, 0}, 2476 {"phymod_value_override_t", "dfe", 0, PHYMOD_NUM_DFE_TAPS}, 2477 {"phymod_value_override_t", "peaking_filter", 0, 0}, 2478 {"phymod_value_override_t", "low_freq_peaking_filter", 0, 0}, 2479 {"phymod_value_override_t", "high_freq_peaking_filter", 0, 0}, 2480 {"uint32_t", "rx_adaptation_on", 0, 0}, 2481 { NULL } 2482 }; 2483 2484 static cint_parameter_desc_t __cint_struct_members__phymod_phy_reset_t[] = 2485 { 2486 {"phymod_reset_direction_t", "rx", 0, 0}, 2487 {"phymod_reset_direction_t", "tx", 0, 0}, 2488 { NULL } 2489 }; 2490 2491 static cint_parameter_desc_t __cint_struct_members__phymod_phy_power_t[] = 2492 { 2493 {"phymod_power_t", "rx", 0, 0}, 2494 {"phymod_power_t", "tx", 0, 0}, 2495 { NULL } 2496 }; 2497 2498 static cint_parameter_desc_t __cint_struct_members__phymod_autoneg_oui_t[] = 2499 { 2500 {"uint32_t", "oui", 0, 0}, 2501 {"uint16_t", "oui_override_bam73_adv", 0, 0}, 2502 {"uint16_t", "oui_override_bam73_det", 0, 0}, 2503 {"uint16_t", "oui_override_hpam_adv", 0, 0}, 2504 {"uint16_t", "oui_override_hpam_det", 0, 0}, 2505 {"uint16_t", "oui_override_bam37_adv", 0, 0}, 2506 {"uint16_t", "oui_override_bam37_det", 0, 0}, 2507 { NULL } 2508 }; 2509 2510 static cint_parameter_desc_t __cint_struct_members__phymod_phy_inf_config_t[] = 2511 { 2512 {"phymod_interface_t", "interface_type", 0, 0}, 2513 {"uint32_t", "data_rate", 0, 0}, 2514 {"uint32_t", "interface_modes", 0, 0}, 2515 {"phymod_ref_clk_t", "ref_clock", 0, 0}, 2516 {"phymod_ref_clk_t", "com_clock", 0, 0}, 2517 {"uint16_t", "pll_divider_req", 0, 0}, 2518 {"void", "device_aux_modes", 1, 0}, 2519 {"phymod_otn_type_t", "otn_type", 0, 0}, 2520 { NULL } 2521 }; 2522 2523 static cint_parameter_desc_t __cint_struct_members__phymod_cl72_status_t[] = 2524 { 2525 {"uint32_t", "enabled", 0, 0}, 2526 {"uint32_t", "locked", 0, 0}, 2527 { NULL } 2528 }; 2529 2530 static cint_parameter_desc_t __cint_struct_members__phymod_autoneg_ability_t[] = 2531 { 2532 {"uint32_t", "an_cap", 0, 0}, 2533 {"uint32_t", "cl73bam_cap", 0, 0}, 2534 {"uint32_t", "cl37bam_cap", 0, 0}, 2535 {"uint32_t", "an_fec", 0, 0}, 2536 {"uint32_t", "an_cl72", 0, 0}, 2537 {"uint32_t", "an_hg2", 0, 0}, 2538 {"uint32_t", "capabilities", 0, 0}, 2539 {"phymod_cl37_sgmii_speed_t", "sgmii_speed", 0, 0}, 2540 {"uint32_t", "an_master_lane", 0, 0}, 2541 { NULL } 2542 }; 2543 2544 static cint_parameter_desc_t __cint_struct_members__phymod_autoneg_control_t[] = 2545 { 2546 {"phymod_an_mode_type_t", "an_mode", 0, 0}, 2547 {"uint32_t", "num_lane_adv", 0, 0}, 2548 {"uint32_t", "flags", 0, 0}, 2549 {"uint32_t", "enable", 0, 0}, 2550 { NULL } 2551 }; 2552 2553 static cint_parameter_desc_t __cint_struct_members__phymod_autoneg_status_t[] = 2554 { 2555 {"uint32_t", "enabled", 0, 0}, 2556 {"uint32_t", "locked", 0, 0}, 2557 {"uint32_t", "data_rate", 0, 0}, 2558 {"phymod_interface_t", "interface", 0, 0}, 2559 {"uint32_t", "resolved_num_lane", 0, 0}, 2560 {"uint32_t", "resolved_port_mode", 0, 0}, 2561 { NULL } 2562 }; 2563 2564 static cint_parameter_desc_t __cint_struct_members__phymod_afe_pll_t[] = 2565 { 2566 {"uint32_t", "afe_pll_change_default", 0, 0}, 2567 {"uint32_t", "ams_pll_iqp", 0, 0}, 2568 {"uint32_t", "ams_pll_en_hrz", 0, 0}, 2569 { NULL } 2570 }; 2571 2572 static cint_parameter_desc_t __cint_struct_members__phymod_core_init_config_t[] = 2573 { 2574 {"phymod_lane_map_t", "lane_map", 0, 0}, 2575 {"phymod_polarity_t", "polarity_map", 0, 0}, 2576 {"phymod_firmware_load_method_t", "firmware_load_method", 0, 0}, 2577 {"phymod_firmware_loader_f", "firmware_loader", 0, 0}, 2578 {"phymod_firmware_core_config_t", "firmware_core_config", 0, 0}, 2579 {"phymod_phy_inf_config_t", "interface", 0, 0}, 2580 {"uint32_t", "flags", 0, 0}, 2581 {"phymod_datapath_t", "op_datapath", 0, 0}, 2582 {"int", "rx_fifo_sync_offset", 0, 0}, 2583 {"int", "tx_fifo_sync_offset", 0, 0}, 2584 {"phymod_tx_input_voltage_t", "tx_input_voltage", 0, 0}, 2585 {"phymod_afe_pll_t", "afe_pll", 0, 0}, 2586 {"uint8_t", "core_mode", 0, 0}, 2587 {"uint8_t", "trcvr_host_managed", 0, 0}, 2588 {"uint32_t", "pll0_div_init_value", 0, 0}, 2589 {"uint32_t", "pll1_div_init_value", 0, 0}, 2590 { NULL } 2591 }; 2592 2593 static cint_parameter_desc_t __cint_struct_members__phymod_core_status_t[] = 2594 { 2595 {"uint32_t", "pmd_active", 0, 0}, 2596 { NULL } 2597 }; 2598 2599 static cint_parameter_desc_t __cint_struct_members__phymod_rx_los_t[] = 2600 { 2601 {"uint32_t", "rx_los_en", 0, 0}, 2602 {"uint32_t", "rx_los_invert_en", 0, 0}, 2603 { NULL } 2604 }; 2605 2606 static cint_parameter_desc_t __cint_struct_members__phymod_phy_init_config_t[] = 2607 { 2608 {"phymod_polarity_t", "polarity", 0, 0}, 2609 {"uint32_t", "tx_params_user_flag", 0, PHYMOD_MAX_LANES_PER_CORE}, 2610 {"phymod_tx_t", "tx", 0, PHYMOD_MAX_LANES_PER_CORE}, 2611 {"uint32_t", "cl72_en", 0, 0}, 2612 {"uint32_t", "an_en", 0, 0}, 2613 {"phymod_operation_mode_t", "op_mode", 0, 0}, 2614 {"phymod_autoneg_link_qualifier_t", "an_link_qualifier", 0, 0}, 2615 {"phymod_phy_inf_config_t", "interface", 0, 0}, 2616 {"phymod_rx_los_t", "rx_los", 0, 0}, 2617 {"uint32_t", "ext_phy_tx_params_user_flag", 0, PHYMOD_MAX_LANES_PER_CORE}, 2618 {"phymod_tx_t", "ext_phy_tx", 0, PHYMOD_MAX_LANES_PER_CORE}, 2619 {"uint32_t", "rx_swing", 0, 0}, 2620 {"uint32_t", "flags", 0, 0}, 2621 { NULL } 2622 }; 2623 2624 static cint_parameter_desc_t __cint_struct_members__phymod_pcs_userspeed_config_t[] = 2625 { 2626 {"phymod_pcs_userspeed_mode_t", "mode", 0, 0}, 2627 {"phymod_pcs_userspeed_param_t", "param", 0, 0}, 2628 {"uint32_t", "value", 0, 0}, 2629 {"uint16_t", "current_entry", 0, 0}, 2630 { NULL } 2631 }; 2632 2633 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_timer_adjust_t[] = 2634 { 2635 {"phymod_timesync_timer_mode_t", "mode", 0, 0}, 2636 {"int", "delta", 0, 0}, 2637 { NULL } 2638 }; 2639 2640 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_inband_ctrl_t[] = 2641 { 2642 {"uint32_t", "flags", 0, 0}, 2643 {"int", "resv0_id", 0, 0}, 2644 {"phymod_timesync_timer_mode_t", "timer_mode", 0, 0}, 2645 { NULL } 2646 }; 2647 2648 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_framesync_t[] = 2649 { 2650 {"phymod_timesync_framesync_mode_t", "mode", 0, 0}, 2651 {"uint32_t", "length_threshold", 0, 0}, 2652 {"uint32_t", "event_offset", 0, 0}, 2653 { NULL } 2654 }; 2655 2656 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_syncout_t[] = 2657 { 2658 {"uint16_t", "pulse_1_length", 0, 0}, 2659 {"uint16_t", "pulse_2_length", 0, 0}, 2660 {"uint32_t", "interval", 0, 0}, 2661 {"uint64_t", "timestamp", 0, 0}, 2662 { NULL } 2663 }; 2664 2665 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_timespec_t[] = 2666 { 2667 {"uint8_t", "isnegative", 0, 0}, 2668 {"uint64_t", "seconds", 0, 0}, 2669 {"uint32_t", "nanoseconds", 0, 0}, 2670 { NULL } 2671 }; 2672 2673 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_mpls_label_t[] = 2674 { 2675 {"uint32_t", "value", 0, 0}, 2676 {"uint32_t", "mask", 0, 0}, 2677 {"uint32_t", "flags", 0, 0}, 2678 { NULL } 2679 }; 2680 2681 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_mpls_ctrl_t[] = 2682 { 2683 {"uint32_t", "flags", 0, 0}, 2684 {"uint32_t", "special_label", 0, 0}, 2685 {"phymod_timesync_mpls_label_t", "labels", 0, 10}, 2686 {"int", "size", 0, 0}, 2687 { NULL } 2688 }; 2689 2690 static cint_parameter_desc_t __cint_struct_members__phymod_timesync_config_t[] = 2691 { 2692 {"uint32_t", "capabilities", 0, 0}, 2693 {"uint32_t", "flags", 0, 0}, 2694 {"uint16_t", "itpid", 0, 0}, 2695 {"uint16_t", "otpid", 0, 0}, 2696 {"uint16_t", "otpid2", 0, 0}, 2697 {"phymod_timesync_timer_adjust_t", "timer_adjust", 0, 0}, 2698 {"phymod_timesync_inband_ctrl_t", "inband_ctrl", 0, 0}, 2699 {"phymod_timesync_global_mode_t", "gmode", 0, 0}, 2700 {"phymod_timesync_syncout_t", "syncout", 0, 0}, 2701 {"uint16_t", "ts_divider", 0, 0}, 2702 {"phymod_timesync_timespec_t", "original_timecode", 0, 0}, 2703 {"uint32_t", "rx_link_delay", 0, 0}, 2704 {"phymod_timesync_event_msg_action_t", "tx_sync_mode", 0, 0}, 2705 {"phymod_timesync_event_msg_action_t", "tx_delay_req_mode", 0, 0}, 2706 {"phymod_timesync_event_msg_action_t", "tx_pdelay_req_mode", 0, 0}, 2707 {"phymod_timesync_event_msg_action_t", "tx_pdelay_resp_mode", 0, 0}, 2708 {"phymod_timesync_event_msg_action_t", "rx_sync_mode", 0, 0}, 2709 {"phymod_timesync_event_msg_action_t", "rx_delay_req_mode", 0, 0}, 2710 {"phymod_timesync_event_msg_action_t", "rx_pdelay_req_mode", 0, 0}, 2711 {"phymod_timesync_event_msg_action_t", "rx_pdelay_resp_mode", 0, 0}, 2712 {"phymod_timesync_mpls_ctrl_t", "mpls_ctrl", 0, 0}, 2713 {"uint32_t", "sync_freq", 0, 0}, 2714 {"uint16_t", "phy_1588_dpll_k1", 0, 0}, 2715 {"uint16_t", "phy_1588_dpll_k2", 0, 0}, 2716 {"uint16_t", "phy_1588_dpll_k3", 0, 0}, 2717 {"uint64_t", "phy_1588_dpll_loop_filter", 0, 0}, 2718 {"uint64_t", "phy_1588_dpll_ref_phase", 0, 0}, 2719 {"uint32_t", "phy_1588_dpll_ref_phase_delta", 0, 0}, 2720 { NULL } 2721 }; 2722 2723 static cint_parameter_desc_t __cint_struct_members__phymod_edc_config_t[] = 2724 { 2725 {"phymod_edc_config_method_t", "method", 0, 0}, 2726 {"uint32_t", "mode_val", 0, 0}, 2727 { NULL } 2728 }; 2729 2730 static cint_parameter_desc_t __cint_struct_members__phymod_an_try_enable_control_t[] = 2731 { 2732 {"phymod_an_mode_type_t", "an_mode", 0, 0}, 2733 {"uint32_t", "num_lane_adv", 0, 0}, 2734 {"uint32_t", "flags", 0, 0}, 2735 {"uint32_t", "enable", 0, 0}, 2736 {"uint32_t", "speed", 0, 0}, 2737 { NULL } 2738 }; 2739 2740 static cint_parameter_desc_t __cint_struct_members__phymod_phy_an_status_t[] = 2741 { 2742 {"uint32_t", "hcd_speed", 0, 0}, 2743 {"uint8_t", "result", 0, 0}, 2744 { NULL } 2745 }; 2746 2747 static cint_parameter_desc_t __cint_struct_members__phymod_multi_data_t[] = 2748 { 2749 {"uint32_t", "flags", 0, 0}, 2750 {"uint32_t", "dev_addr", 0, 0}, 2751 {"uint32_t", "offset", 0, 0}, 2752 {"uint32_t", "max_size", 0, 0}, 2753 {"unsigned char", "data", 1, 0}, 2754 {"uint32_t", "actual_size", 1, 0}, 2755 { NULL } 2756 }; 2757 2758 static cint_parameter_desc_t __cint_struct_members__phymod_an_page_t[] = 2759 { 2760 {"unsigned short", "page_0", 0, 0}, 2761 {"unsigned short", "page_1", 0, 0}, 2762 {"unsigned short", "page_2", 0, 0}, 2763 { NULL } 2764 }; 2765 2766 static cint_parameter_desc_t __cint_struct_members__phymod_sw_an_ctrl_status_t[] = 2767 { 2768 {"uint8_t", "seq_restart", 0, 0}, 2769 {"uint8_t", "lp_page_rdy", 0, 0}, 2770 {"uint8_t", "page_req", 0, 0}, 2771 {"uint8_t", "an_completed", 0, 0}, 2772 { NULL } 2773 }; 2774 2775 static cint_parameter_desc_t __cint_struct_members__phymod_an_pages_t[] = 2776 { 2777 {"phymod_an_page_t", "base_page", 0, 0}, 2778 {"phymod_an_page_t", "msg_page", 0, 0}, 2779 {"phymod_an_page_t", "ufmt_page", 0, 0}, 2780 {"phymod_an_page_t", "null_page", 0, 0}, 2781 { NULL } 2782 }; 2783 2784 static cint_parameter_desc_t __cint_struct_members__phymod_sw_an_ctxt_t[] = 2785 { 2786 {"phymod_an_pages_t", "tx_pages", 0, 0}, 2787 {"phymod_an_pages_t", "rx_pages", 0, 0}, 2788 {"uint32_t", "no_pages_to_be_txed", 0, 0}, 2789 {"uint32_t", "tx_pages_cnt", 0, 0}, 2790 {"uint32_t", "rx_pages_cnt", 0, 0}, 2791 {"phymod_an_mode_type_t", "an_mode", 0, 0}, 2792 { NULL } 2793 }; 2794 2795 static cint_parameter_desc_t __cint_struct_members__phymod_phy_speed_config_t[] = 2796 { 2797 {"uint32_t", "data_rate", 0, 0}, 2798 {"phymod_fec_type_t", "fec_type", 0, 0}, 2799 {"uint32_t", "linkTraining", 0, 0}, 2800 {"uint32_t", "flags", 0, 0}, 2801 {"uint32_t", "PAM4_channel_loss", 0, 0}, 2802 {"phymod_firmware_lane_config_t", "pmd_lane_config", 0, 0}, 2803 { NULL } 2804 }; 2805 2806 static cint_parameter_desc_t __cint_struct_members__phymod_phy_pll_state_t[] = 2807 { 2808 {"uint32_t", "pll0_lanes_bitmap", 0, 0}, 2809 {"uint32_t", "pll1_lanes_bitmap", 0, 0}, 2810 { NULL } 2811 }; 2812 2813 static cint_parameter_desc_t __cint_struct_members__phymod_dual_plls_t[] = 2814 { 2815 {"uint32_t", "pll0_div", 0, 0}, 2816 {"uint32_t", "pll1_div", 0, 0}, 2817 { NULL } 2818 }; 2819 2820 static cint_parameter_desc_t __cint_struct_members__phymod_firmware_load_info_t[] = 2821 { 2822 {"unsigned char", "ucode_ptr", 1, 0}, 2823 {"unsigned int", "ucode_len", 0, 0}, 2824 { NULL } 2825 }; 2826 2827 static cint_parameter_desc_t __cint_struct_members__phymod_autoneg_advert_ability_t[] = 2828 { 2829 {"uint32_t", "speed", 0, 0}, 2830 {"uint32_t", "resolved_num_lanes", 0, 0}, 2831 {"phymod_fec_type_t", "fec", 0, 0}, 2832 {"phymod_pause_type_t", "pause", 0, 0}, 2833 {"phymod_firmware_media_type_t", "medium", 0, 0}, 2834 {"uint32_t", "channel", 0, 0}, 2835 {"phymod_an_mode_type_t", "an_mode", 0, 0}, 2836 { NULL } 2837 }; 2838 2839 static cint_parameter_desc_t __cint_struct_members__phymod_autoneg_advert_abilities_t[] = 2840 { 2841 {"uint32_t", "num_abilities", 0, 0}, 2842 {"phymod_autoneg_advert_ability_t", "autoneg_abilities", 1, 0}, 2843 { NULL } 2844 }; 2845 2846 static cint_parameter_desc_t __cint_struct_members__phymod_synce_clk_ctrl_t[] = 2847 { 2848 {"int", "stg0_mode", 0, 0}, 2849 {"int", "stg1_mode", 0, 0}, 2850 {"uint32_t", "sdm_val", 0, 0}, 2851 { NULL } 2852 }; 2853 2854 static cint_parameter_desc_t __cint_struct_members__phymod_ts_fifo_status_t[] = 2855 { 2856 {"uint32_t", "ts_in_fifo_lo", 0, 0}, 2857 {"uint32_t", "ts_in_fifo_hi", 0, 0}, 2858 {"uint32_t", "ts_seq_id", 0, 0}, 2859 {"uint32_t", "ts_sub_nanosec", 0, 0}, 2860 { NULL } 2861 }; 2862 2863 2864 static cint_struct_type_t __cint_structures[] = 2865 { 2866 { 2867 "phymod_bus_t", 2868 sizeof(phymod_bus_t), 2869 __cint_struct_members__phymod_bus_t, 2870 __cint_maddr__phymod_bus_t 2871 }, 2872 { 2873 "phymod_access_t", 2874 sizeof(phymod_access_t), 2875 __cint_struct_members__phymod_access_t, 2876 __cint_maddr__phymod_access_t 2877 }, 2878 { 2879 "phymod_core_access_t", 2880 sizeof(phymod_core_access_t), 2881 __cint_struct_members__phymod_core_access_t, 2882 __cint_maddr__phymod_core_access_t 2883 }, 2884 { 2885 "phymod_phy_access_t", 2886 sizeof(phymod_phy_access_t), 2887 __cint_struct_members__phymod_phy_access_t, 2888 __cint_maddr__phymod_phy_access_t 2889 }, 2890 { 2891 "phymod_port_config_t", 2892 sizeof(phymod_port_config_t), 2893 __cint_struct_members__phymod_port_config_t, 2894 __cint_maddr__phymod_port_config_t 2895 }, 2896 { 2897 "phymod_value_override_t", 2898 sizeof(phymod_value_override_t), 2899 __cint_struct_members__phymod_value_override_t, 2900 __cint_maddr__phymod_value_override_t 2901 }, 2902 { 2903 "phymod_core_info_t", 2904 sizeof(phymod_core_info_t), 2905 __cint_struct_members__phymod_core_info_t, 2906 __cint_maddr__phymod_core_info_t 2907 }, 2908 { 2909 "phymod_lane_map_t", 2910 sizeof(phymod_lane_map_t), 2911 __cint_struct_members__phymod_lane_map_t, 2912 __cint_maddr__phymod_lane_map_t 2913 }, 2914 { 2915 "phymod_core_firmware_info_t", 2916 sizeof(phymod_core_firmware_info_t), 2917 __cint_struct_members__phymod_core_firmware_info_t, 2918 __cint_maddr__phymod_core_firmware_info_t 2919 }, 2920 { 2921 "phymod_firmware_core_config_t", 2922 sizeof(phymod_firmware_core_config_t), 2923 __cint_struct_members__phymod_firmware_core_config_t, 2924 __cint_maddr__phymod_firmware_core_config_t 2925 }, 2926 { 2927 "phymod_firmware_lane_config_t", 2928 sizeof(phymod_firmware_lane_config_t), 2929 __cint_struct_members__phymod_firmware_lane_config_t, 2930 __cint_maddr__phymod_firmware_lane_config_t 2931 }, 2932 { 2933 "phymod_polarity_t", 2934 sizeof(phymod_polarity_t), 2935 __cint_struct_members__phymod_polarity_t, 2936 __cint_maddr__phymod_polarity_t 2937 }, 2938 { 2939 "phymod_tx_t", 2940 sizeof(phymod_tx_t), 2941 __cint_struct_members__phymod_tx_t, 2942 __cint_maddr__phymod_tx_t 2943 }, 2944 { 2945 "phymod_tx_override_t", 2946 sizeof(phymod_tx_override_t), 2947 __cint_struct_members__phymod_tx_override_t, 2948 __cint_maddr__phymod_tx_override_t 2949 }, 2950 { 2951 "phymod_txpi_config_t", 2952 sizeof(phymod_txpi_config_t), 2953 __cint_struct_members__phymod_txpi_config_t, 2954 __cint_maddr__phymod_txpi_config_t 2955 }, 2956 { 2957 "phymod_rx_t", 2958 sizeof(phymod_rx_t), 2959 __cint_struct_members__phymod_rx_t, 2960 __cint_maddr__phymod_rx_t 2961 }, 2962 { 2963 "phymod_phy_reset_t", 2964 sizeof(phymod_phy_reset_t), 2965 __cint_struct_members__phymod_phy_reset_t, 2966 __cint_maddr__phymod_phy_reset_t 2967 }, 2968 { 2969 "phymod_phy_power_t", 2970 sizeof(phymod_phy_power_t), 2971 __cint_struct_members__phymod_phy_power_t, 2972 __cint_maddr__phymod_phy_power_t 2973 }, 2974 { 2975 "phymod_autoneg_oui_t", 2976 sizeof(phymod_autoneg_oui_t), 2977 __cint_struct_members__phymod_autoneg_oui_t, 2978 __cint_maddr__phymod_autoneg_oui_t 2979 }, 2980 { 2981 "phymod_phy_inf_config_t", 2982 sizeof(phymod_phy_inf_config_t), 2983 __cint_struct_members__phymod_phy_inf_config_t, 2984 __cint_maddr__phymod_phy_inf_config_t 2985 }, 2986 { 2987 "phymod_cl72_status_t", 2988 sizeof(phymod_cl72_status_t), 2989 __cint_struct_members__phymod_cl72_status_t, 2990 __cint_maddr__phymod_cl72_status_t 2991 }, 2992 { 2993 "phymod_autoneg_ability_t", 2994 sizeof(phymod_autoneg_ability_t), 2995 __cint_struct_members__phymod_autoneg_ability_t, 2996 __cint_maddr__phymod_autoneg_ability_t 2997 }, 2998 { 2999 "phymod_autoneg_control_t", 3000 sizeof(phymod_autoneg_control_t), 3001 __cint_struct_members__phymod_autoneg_control_t, 3002 __cint_maddr__phymod_autoneg_control_t 3003 }, 3004 { 3005 "phymod_autoneg_status_t", 3006 sizeof(phymod_autoneg_status_t), 3007 __cint_struct_members__phymod_autoneg_status_t, 3008 __cint_maddr__phymod_autoneg_status_t 3009 }, 3010 { 3011 "phymod_afe_pll_t", 3012 sizeof(phymod_afe_pll_t), 3013 __cint_struct_members__phymod_afe_pll_t, 3014 __cint_maddr__phymod_afe_pll_t 3015 }, 3016 { 3017 "phymod_core_init_config_t", 3018 sizeof(phymod_core_init_config_t), 3019 __cint_struct_members__phymod_core_init_config_t, 3020 __cint_maddr__phymod_core_init_config_t 3021 }, 3022 { 3023 "phymod_core_status_t", 3024 sizeof(phymod_core_status_t), 3025 __cint_struct_members__phymod_core_status_t, 3026 __cint_maddr__phymod_core_status_t 3027 }, 3028 { 3029 "phymod_rx_los_t", 3030 sizeof(phymod_rx_los_t), 3031 __cint_struct_members__phymod_rx_los_t, 3032 __cint_maddr__phymod_rx_los_t 3033 }, 3034 { 3035 "phymod_phy_init_config_t", 3036 sizeof(phymod_phy_init_config_t), 3037 __cint_struct_members__phymod_phy_init_config_t, 3038 __cint_maddr__phymod_phy_init_config_t 3039 }, 3040 { 3041 "phymod_pcs_userspeed_config_t", 3042 sizeof(phymod_pcs_userspeed_config_t), 3043 __cint_struct_members__phymod_pcs_userspeed_config_t, 3044 __cint_maddr__phymod_pcs_userspeed_config_t 3045 }, 3046 { 3047 "phymod_timesync_timer_adjust_t", 3048 sizeof(phymod_timesync_timer_adjust_t), 3049 __cint_struct_members__phymod_timesync_timer_adjust_t, 3050 __cint_maddr__phymod_timesync_timer_adjust_t 3051 }, 3052 { 3053 "phymod_timesync_inband_ctrl_t", 3054 sizeof(phymod_timesync_inband_ctrl_t), 3055 __cint_struct_members__phymod_timesync_inband_ctrl_t, 3056 __cint_maddr__phymod_timesync_inband_ctrl_t 3057 }, 3058 { 3059 "phymod_timesync_framesync_t", 3060 sizeof(phymod_timesync_framesync_t), 3061 __cint_struct_members__phymod_timesync_framesync_t, 3062 __cint_maddr__phymod_timesync_framesync_t 3063 }, 3064 { 3065 "phymod_timesync_syncout_t", 3066 sizeof(phymod_timesync_syncout_t), 3067 __cint_struct_members__phymod_timesync_syncout_t, 3068 __cint_maddr__phymod_timesync_syncout_t 3069 }, 3070 { 3071 "phymod_timesync_timespec_t", 3072 sizeof(phymod_timesync_timespec_t), 3073 __cint_struct_members__phymod_timesync_timespec_t, 3074 __cint_maddr__phymod_timesync_timespec_t 3075 }, 3076 { 3077 "phymod_timesync_mpls_label_t", 3078 sizeof(phymod_timesync_mpls_label_t), 3079 __cint_struct_members__phymod_timesync_mpls_label_t, 3080 __cint_maddr__phymod_timesync_mpls_label_t 3081 }, 3082 { 3083 "phymod_timesync_mpls_ctrl_t", 3084 sizeof(phymod_timesync_mpls_ctrl_t), 3085 __cint_struct_members__phymod_timesync_mpls_ctrl_t, 3086 __cint_maddr__phymod_timesync_mpls_ctrl_t 3087 }, 3088 { 3089 "phymod_timesync_config_t", 3090 sizeof(phymod_timesync_config_t), 3091 __cint_struct_members__phymod_timesync_config_t, 3092 __cint_maddr__phymod_timesync_config_t 3093 }, 3094 { 3095 "phymod_edc_config_t", 3096 sizeof(phymod_edc_config_t), 3097 __cint_struct_members__phymod_edc_config_t, 3098 __cint_maddr__phymod_edc_config_t 3099 }, 3100 { 3101 "phymod_an_try_enable_control_t", 3102 sizeof(phymod_an_try_enable_control_t), 3103 __cint_struct_members__phymod_an_try_enable_control_t, 3104 __cint_maddr__phymod_an_try_enable_control_t 3105 }, 3106 { 3107 "phymod_phy_an_status_t", 3108 sizeof(phymod_phy_an_status_t), 3109 __cint_struct_members__phymod_phy_an_status_t, 3110 __cint_maddr__phymod_phy_an_status_t 3111 }, 3112 { 3113 "phymod_multi_data_t", 3114 sizeof(phymod_multi_data_t), 3115 __cint_struct_members__phymod_multi_data_t, 3116 __cint_maddr__phymod_multi_data_t 3117 }, 3118 { 3119 "phymod_an_page_t", 3120 sizeof(phymod_an_page_t), 3121 __cint_struct_members__phymod_an_page_t, 3122 __cint_maddr__phymod_an_page_t 3123 }, 3124 { 3125 "phymod_sw_an_ctrl_status_t", 3126 sizeof(phymod_sw_an_ctrl_status_t), 3127 __cint_struct_members__phymod_sw_an_ctrl_status_t, 3128 __cint_maddr__phymod_sw_an_ctrl_status_t 3129 }, 3130 { 3131 "phymod_an_pages_t", 3132 sizeof(phymod_an_pages_t), 3133 __cint_struct_members__phymod_an_pages_t, 3134 __cint_maddr__phymod_an_pages_t 3135 }, 3136 { 3137 "phymod_sw_an_ctxt_t", 3138 sizeof(phymod_sw_an_ctxt_t), 3139 __cint_struct_members__phymod_sw_an_ctxt_t, 3140 __cint_maddr__phymod_sw_an_ctxt_t 3141 }, 3142 { 3143 "phymod_phy_speed_config_t", 3144 sizeof(phymod_phy_speed_config_t), 3145 __cint_struct_members__phymod_phy_speed_config_t, 3146 __cint_maddr__phymod_phy_speed_config_t 3147 }, 3148 { 3149 "phymod_phy_pll_state_t", 3150 sizeof(phymod_phy_pll_state_t), 3151 __cint_struct_members__phymod_phy_pll_state_t, 3152 __cint_maddr__phymod_phy_pll_state_t 3153 }, 3154 { 3155 "phymod_dual_plls_t", 3156 sizeof(phymod_dual_plls_t), 3157 __cint_struct_members__phymod_dual_plls_t, 3158 __cint_maddr__phymod_dual_plls_t 3159 }, 3160 { 3161 "phymod_firmware_load_info_t", 3162 sizeof(phymod_firmware_load_info_t), 3163 __cint_struct_members__phymod_firmware_load_info_t, 3164 __cint_maddr__phymod_firmware_load_info_t 3165 }, 3166 { 3167 "phymod_autoneg_advert_ability_t", 3168 sizeof(phymod_autoneg_advert_ability_t), 3169 __cint_struct_members__phymod_autoneg_advert_ability_t, 3170 __cint_maddr__phymod_autoneg_advert_ability_t 3171 }, 3172 { 3173 "phymod_autoneg_advert_abilities_t", 3174 sizeof(phymod_autoneg_advert_abilities_t), 3175 __cint_struct_members__phymod_autoneg_advert_abilities_t, 3176 __cint_maddr__phymod_autoneg_advert_abilities_t 3177 }, 3178 { 3179 "phymod_synce_clk_ctrl_t", 3180 sizeof(phymod_synce_clk_ctrl_t), 3181 __cint_struct_members__phymod_synce_clk_ctrl_t, 3182 __cint_maddr__phymod_synce_clk_ctrl_t 3183 }, 3184 { 3185 "phymod_ts_fifo_status_t", 3186 sizeof(phymod_ts_fifo_status_t), 3187 __cint_struct_members__phymod_ts_fifo_status_t, 3188 __cint_maddr__phymod_ts_fifo_status_t 3189 }, 3190 { NULL } 3191 }; 3192 3193 3194 /* Enums section */ 3195 static cint_enum_map_t __cint_enum_map__phymod_dispatch_type_t[] = 3196 { 3197 #ifdef PHYMOD_EAGLE_SUPPORT 3198 { "phymodDispatchTypeEagle", phymodDispatchTypeEagle }, 3199 #endif /*PHYMOD_EAGLE_SUPPORT */ 3200 #ifdef PHYMOD_FALCON_SUPPORT 3201 { "phymodDispatchTypeFalcon", phymodDispatchTypeFalcon }, 3202 #endif /*PHYMOD_FALCON_SUPPORT */ 3203 #ifdef PHYMOD_QSGMIIE_SUPPORT 3204 { "phymodDispatchTypeQsgmiie", phymodDispatchTypeQsgmiie }, 3205 #endif /*PHYMOD_QSGMIIE_SUPPORT */ 3206 #ifdef PHYMOD_TSCE_SUPPORT 3207 { "phymodDispatchTypeTsce", phymodDispatchTypeTsce }, 3208 #endif /*PHYMOD_TSCE_SUPPORT */ 3209 #ifdef PHYMOD_TSCF_SUPPORT 3210 { "phymodDispatchTypeTscf", phymodDispatchTypeTscf }, 3211 #endif /*PHYMOD_TSCF_SUPPORT */ 3212 #ifdef PHYMOD_PHY8806X_SUPPORT 3213 { "phymodDispatchTypePhy8806x", phymodDispatchTypePhy8806x }, 3214 #endif /*PHYMOD_PHY8806X_SUPPORT */ 3215 #ifdef PHYMOD_FURIA_SUPPORT 3216 { "phymodDispatchTypeFuria", phymodDispatchTypeFuria }, 3217 #endif /*PHYMOD_FURIA_SUPPORT */ 3218 #ifdef PHYMOD_VIPER_SUPPORT 3219 { "phymodDispatchTypeViper", phymodDispatchTypeViper }, 3220 #endif /*PHYMOD_VIPER_SUPPORT */ 3221 #ifdef PHYMOD_SESTO_SUPPORT 3222 { "phymodDispatchTypeSesto", phymodDispatchTypeSesto }, 3223 #endif /*PHYMOD_SESTO_SUPPORT */ 3224 #ifdef PHYMOD_QUADRA28_SUPPORT 3225 { "phymodDispatchTypeQuadra28", phymodDispatchTypeQuadra28 }, 3226 #endif /*PHYMOD_QUADRA28_SUPPORT */ 3227 #ifdef PHYMOD_QTCE_SUPPORT 3228 { "phymodDispatchTypeQtce", phymodDispatchTypeQtce }, 3229 #endif /*PHYMOD_QTCE_SUPPORT */ 3230 #ifdef PHYMOD_HURACAN_SUPPORT 3231 { "phymodDispatchTypeHuracan", phymodDispatchTypeHuracan }, 3232 #endif /*PHYMOD_HURACAN_SUPPORT */ 3233 #ifdef PHYMOD_MADURA_SUPPORT 3234 { "phymodDispatchTypeMadura", phymodDispatchTypeMadura }, 3235 #endif /*PHYMOD_MADURA_SUPPORT */ 3236 #ifdef PHYMOD_FURIA_SUPPORT 3237 { "phymodDispatchTypeFuria_82212", phymodDispatchTypeFuria_82212 }, 3238 #endif /*PHYMOD_FURIA_SUPPORT */ 3239 #ifdef PHYMOD_DINO_SUPPORT 3240 { "phymodDispatchTypeDino", phymodDispatchTypeDino }, 3241 #endif /*PHYMOD_DINO_SUPPORT */ 3242 #ifdef PHYMOD_TSCE_DPLL_SUPPORT 3243 { "phymodDispatchTypeTsce_dpll", phymodDispatchTypeTsce_dpll }, 3244 #endif /*PHYMOD_TSCE_DPLL_SUPPORT */ 3245 #ifdef PHYMOD_EAGLE_DPLL_SUPPORT 3246 { "phymodDispatchTypeEagle_dpll", phymodDispatchTypeEagle_dpll }, 3247 #endif /*PHYMOD_EAGLE_DPLL_SUPPORT */ 3248 #ifdef PHYMOD_TSCF16_SUPPORT 3249 { "phymodDispatchTypeTscf16", phymodDispatchTypeTscf16 }, 3250 #endif /*PHYMOD_TSCF16_SUPPORT */ 3251 #ifdef PHYMOD_FALCON16_SUPPORT 3252 { "phymodDispatchTypeFalcon16", phymodDispatchTypeFalcon16 }, 3253 #endif /*PHYMOD_FALCON16_SUPPORT */ 3254 #ifdef PHYMOD_MERLIN16_SUPPORT 3255 { "phymodDispatchTypeMerlin16", phymodDispatchTypeMerlin16 }, 3256 #endif /*PHYMOD_MERLIN16_SUPPORT */ 3257 #ifdef PHYMOD_TSCE16_SUPPORT 3258 { "phymodDispatchTypeTsce16", phymodDispatchTypeTsce16 }, 3259 #endif /*PHYMOD_TSCE16_SUPPORT */ 3260 #ifdef PHYMOD_TSCF_GEN3_SUPPORT 3261 { "phymodDispatchTypeTscf_gen3", phymodDispatchTypeTscf_gen3 }, 3262 #endif /*PHYMOD_TSCF_GEN3_SUPPORT */ 3263 #ifdef PHYMOD_FALCON_DPLL_SUPPORT 3264 { "phymodDispatchTypeFalcon_dpll", phymodDispatchTypeFalcon_dpll }, 3265 #endif /*PHYMOD_FALCON_DPLL_SUPPORT */ 3266 #ifdef PHYMOD_BLACKHAWK_SUPPORT 3267 { "phymodDispatchTypeBlackhawk", phymodDispatchTypeBlackhawk }, 3268 #endif /*PHYMOD_BLACKHAWK_SUPPORT */ 3269 #ifdef PHYMOD_TSCBH_SUPPORT 3270 { "phymodDispatchTypeTscbh", phymodDispatchTypeTscbh }, 3271 #endif /*PHYMOD_TSCBH_SUPPORT */ 3272 #ifdef PHYMOD_QTCE16_SUPPORT 3273 { "phymodDispatchTypeQtce16", phymodDispatchTypeQtce16 }, 3274 #endif /*PHYMOD_QTCE16_SUPPORT */ 3275 #ifdef PHYMOD_NULL_SUPPORT 3276 { "phymodDispatchTypeNull", phymodDispatchTypeNull }, 3277 #endif /*PHYMOD_NULL_SUPPORT */ 3278 { "phymodDispatchTypeInvalid", phymodDispatchTypeInvalid }, 3279 #ifdef PHYMOD_BLACKHAWK7_V1L8P2_SUPPORT 3280 { "phymodDispatchTypeBlackhawk7_v1l8p2", phymodDispatchTypeBlackhawk7_v1l8p2 }, 3281 #endif /*PHYMOD_BLACKHAWK7_V1L8P2_SUPPORT */ 3282 #ifdef PHYMOD_TSCBH_GEN2_SUPPORT 3283 { "phymodDispatchTypeTscbh_gen2", phymodDispatchTypeTscbh_gen2 }, 3284 #endif /*PHYMOD_TSCBH_GEN2_SUPPORT */ 3285 #ifdef PHYMOD_MERLIN7_SUPPORT 3286 { "phymodDispatchTypeMerlin7", phymodDispatchTypeMerlin7 }, 3287 #endif /*PHYMOD_MERLIN7_SUPPORT */ 3288 #ifdef PHYMOD_TSCE7_SUPPORT 3289 { "phymodDispatchTypeTsce7", phymodDispatchTypeTsce7 }, 3290 #endif /*PHYMOD_TSCE7_SUPPORT */ 3291 { "phymodDispatchTypeCount", phymodDispatchTypeCount }, 3292 { NULL } 3293 }; 3294 3295 static cint_enum_map_t __cint_enum_map__phymod_mem_type_t[] = 3296 { 3297 { "phymodMemSpeedIdTable", phymodMemSpeedIdTable }, 3298 { "phymodMemAMTable", phymodMemAMTable }, 3299 { "phymodMemUMTable", phymodMemUMTable }, 3300 { "phymodMemTxLkup1588Mpp0", phymodMemTxLkup1588Mpp0 }, 3301 { "phymodMemTxLkup1588Mpp1", phymodMemTxLkup1588Mpp1 }, 3302 { "phymodMemTxLkup1588400G", phymodMemTxLkup1588400G }, 3303 { "phymodMemRxLkup1588Mpp0", phymodMemRxLkup1588Mpp0 }, 3304 { "phymodMemRxLkup1588Mpp1", phymodMemRxLkup1588Mpp1 }, 3305 { "phymodMemRxLkup1588400G", phymodMemRxLkup1588400G }, 3306 { "phymodMemSpeedPriorityMapTable", phymodMemSpeedPriorityMapTable }, 3307 { "phymodMemCount", phymodMemCount }, 3308 { NULL } 3309 }; 3310 3311 static cint_enum_map_t __cint_enum_map__phymod_port_loc_t[] = 3312 { 3313 { "phymodPortLocDC", phymodPortLocDC }, 3314 { "phymodPortLocLine", phymodPortLocLine }, 3315 { "phymodPortLocSys", phymodPortLocSys }, 3316 { "phymodPortCount", phymodPortCount }, 3317 { NULL } 3318 }; 3319 3320 static cint_enum_map_t __cint_enum_map__phymod_core_version_t[] = 3321 { 3322 { "phymodCoreVersionFalconA0", phymodCoreVersionFalconA0 }, 3323 { "phymodCoreVersionEagleA0", phymodCoreVersionEagleA0 }, 3324 { "phymodCoreVersionQsgmiieA0", phymodCoreVersionQsgmiieA0 }, 3325 { "phymodCoreVersionTsce4A0", phymodCoreVersionTsce4A0 }, 3326 { "phymodCoreVersionTsce12A0", phymodCoreVersionTsce12A0 }, 3327 { "phymodCoreVersionTscfA0", phymodCoreVersionTscfA0 }, 3328 { "phymodCoreVersionTscfB0", phymodCoreVersionTscfB0 }, 3329 { "phymodCoreVersionPhy8806x", phymodCoreVersionPhy8806x }, 3330 { "phymodCoreVersionFuriaA2", phymodCoreVersionFuriaA2 }, 3331 { "phymodCoreVersionViperXA0", phymodCoreVersionViperXA0 }, 3332 { "phymodCoreVersionViperGA0", phymodCoreVersionViperGA0 }, 3333 { "phymodCoreVersionSestoA0", phymodCoreVersionSestoA0 }, 3334 { "phymodCoreVersionQuadra28", phymodCoreVersionQuadra28 }, 3335 { "phymodCoreVersionHuracan", phymodCoreVersionHuracan }, 3336 { "phymodCoreVersionMadura", phymodCoreVersionMadura }, 3337 { "phymodCoreVersionSestoB0", phymodCoreVersionSestoB0 }, 3338 { "phymodCoreVersionDino", phymodCoreVersionDino }, 3339 { "phymodCoreVersionTsceDpll", phymodCoreVersionTsceDpll }, 3340 { "phymodCoreVersionFalcon16", phymodCoreVersionFalcon16 }, 3341 { "phymodCoreVersionTscf16", phymodCoreVersionTscf16 }, 3342 { "phymodCoreVersionMerlin16", phymodCoreVersionMerlin16 }, 3343 { "phymodCoreVersionTscfB1", phymodCoreVersionTscfB1 }, 3344 { "phymodCoreVersionTsce16", phymodCoreVersionTsce16 }, 3345 { "phymodCoreVersionfalconDpll", phymodCoreVersionfalconDpll }, 3346 { "phymodCoreVersionTscfGen3", phymodCoreVersionTscfGen3 }, 3347 { "phymodCoreVersionBlackhawk16", phymodCoreVersionBlackhawk16 }, 3348 { "phymodCoreVersionTscbh16", phymodCoreVersionTscbh16 }, 3349 { "phymodCoreVersionQtceA0", phymodCoreVersionQtceA0 }, 3350 { "phymodCoreVersionQtce16", phymodCoreVersionQtce16 }, 3351 { "phymodCoreVersionBlackhawk7_v1l8p2", phymodCoreVersionBlackhawk7_v1l8p2 }, 3352 { "phymodCoreVersionTscbhGen2", phymodCoreVersionTscbhGen2 }, 3353 { "phymodCoreVersionMerlin7", phymodCoreVersionMerlin7 }, 3354 { "phymodCoreVersionTsce7", phymodCoreVersionTsce7 }, 3355 { "phymodCoreVersionCount", phymodCoreVersionCount }, 3356 { NULL } 3357 }; 3358 3359 static cint_enum_map_t __cint_enum_map__phymod_reset_mode_t[] = 3360 { 3361 { "phymodResetModeHard", phymodResetModeHard }, 3362 { "phymodResetModeSoft", phymodResetModeSoft }, 3363 { "phymodResetModeCount", phymodResetModeCount }, 3364 { NULL } 3365 }; 3366 3367 static cint_enum_map_t __cint_enum_map__phymod_reset_direction_t[] = 3368 { 3369 { "phymodResetDirectionIn", phymodResetDirectionIn }, 3370 { "phymodResetDirectionOut", phymodResetDirectionOut }, 3371 { "phymodResetDirectionInOut", phymodResetDirectionInOut }, 3372 { "phymodResetDirectionCount", phymodResetDirectionCount }, 3373 { NULL } 3374 }; 3375 3376 static cint_enum_map_t __cint_enum_map__phymod_firmware_media_type_t[] = 3377 { 3378 { "phymodFirmwareMediaTypePcbTraceBackPlane", phymodFirmwareMediaTypePcbTraceBackPlane }, 3379 { "phymodFirmwareMediaTypeCopperCable", phymodFirmwareMediaTypeCopperCable }, 3380 { "phymodFirmwareMediaTypeOptics", phymodFirmwareMediaTypeOptics }, 3381 { "phymodFirmwareMediaTypeCount", phymodFirmwareMediaTypeCount }, 3382 { NULL } 3383 }; 3384 3385 static cint_enum_map_t __cint_enum_map__phymod_sequencer_operation_t[] = 3386 { 3387 { "phymodSeqOpStop", phymodSeqOpStop }, 3388 { "phymodSeqOpStart", phymodSeqOpStart }, 3389 { "phymodSeqOpRestart", phymodSeqOpRestart }, 3390 { "phymodSeqOpCount", phymodSeqOpCount }, 3391 { NULL } 3392 }; 3393 3394 static cint_enum_map_t __cint_enum_map__phymod_core_event_t[] = 3395 { 3396 { "phymodCoreEventPllLock", phymodCoreEventPllLock }, 3397 { "phymodCoreEventCount", phymodCoreEventCount }, 3398 { NULL } 3399 }; 3400 3401 static cint_enum_map_t __cint_enum_map__phymod_drivermode_t[] = 3402 { 3403 { "phymodTxDriverModeDefault", phymodTxDriverModeDefault }, 3404 { "phymodTxDriverModeNotSupported", phymodTxDriverModeNotSupported }, 3405 { "phymodTxDriverModeHalfAmp", phymodTxDriverModeHalfAmp }, 3406 { "phymodTxDriverModeHalfAmpHiImped", phymodTxDriverModeHalfAmpHiImped }, 3407 { "phymodTxDriverModeCount", phymodTxDriverModeCount }, 3408 { NULL } 3409 }; 3410 3411 static cint_enum_map_t __cint_enum_map__phymod_tx_tap_mode_t[] = 3412 { 3413 { "phymodTxTapModeDefault", phymodTxTapModeDefault }, 3414 { "phymodTxTapMode6Tap", phymodTxTapMode6Tap }, 3415 { "phymodTxTapMode3Tap", phymodTxTapMode3Tap }, 3416 { "phymodTxTapModeCount", phymodTxTapModeCount }, 3417 { NULL } 3418 }; 3419 3420 static cint_enum_map_t __cint_enum_map__phymod_phy_signalling_method_t[] = 3421 { 3422 { "phymodSignallingMethodNRZ", phymodSignallingMethodNRZ }, 3423 { "phymodSignallingMethodPAM4", phymodSignallingMethodPAM4 }, 3424 { "phymodSignallingMethodCount", phymodSignallingMethodCount }, 3425 { NULL } 3426 }; 3427 3428 static cint_enum_map_t __cint_enum_map__phymod_media_typed_t[] = 3429 { 3430 { "phymodMediaTypeChipToChip", phymodMediaTypeChipToChip }, 3431 { "phymodMediaTypeShort", phymodMediaTypeShort }, 3432 { "phymodMediaTypeMid", phymodMediaTypeMid }, 3433 { "phymodMediaTypeLong", phymodMediaTypeLong }, 3434 { "phymodMediaTypeCount", phymodMediaTypeCount }, 3435 { NULL } 3436 }; 3437 3438 static cint_enum_map_t __cint_enum_map__phymod_power_t[] = 3439 { 3440 { "phymodPowerOff", phymodPowerOff }, 3441 { "phymodPowerOn", phymodPowerOn }, 3442 { "phymodPowerOffOn", phymodPowerOffOn }, 3443 { "phymodPowerNoChange", phymodPowerNoChange }, 3444 { "phymodPowerCount", phymodPowerCount }, 3445 { NULL } 3446 }; 3447 3448 static cint_enum_map_t __cint_enum_map__phymod_phy_hg2_codec_t[] = 3449 { 3450 { "phymodBcmHG2CodecOff", phymodBcmHG2CodecOff }, 3451 { "phymodBcmHG2CodecOnWith8ByteIPG", phymodBcmHG2CodecOnWith8ByteIPG }, 3452 { "phymodBcmHG2CodecOnWith9ByteIPG", phymodBcmHG2CodecOnWith9ByteIPG }, 3453 { "phymodBcmHG2CodecCount", phymodBcmHG2CodecCount }, 3454 { NULL } 3455 }; 3456 3457 static cint_enum_map_t __cint_enum_map__phymod_phy_tx_lane_control_t[] = 3458 { 3459 { "phymodTxTrafficDisable", phymodTxTrafficDisable }, 3460 { "phymodTxTrafficEnable", phymodTxTrafficEnable }, 3461 { "phymodTxReset", phymodTxReset }, 3462 { "phymodTxSquelchOn", phymodTxSquelchOn }, 3463 { "phymodTxSquelchOff", phymodTxSquelchOff }, 3464 { "phymodTxElectricalIdleEnable", phymodTxElectricalIdleEnable }, 3465 { "phymodTxElectricalIdleDisable", phymodTxElectricalIdleDisable }, 3466 { "phymodTxCount", phymodTxCount }, 3467 { NULL } 3468 }; 3469 3470 static cint_enum_map_t __cint_enum_map__phymod_phy_rx_lane_control_t[] = 3471 { 3472 { "phymodRxReset", phymodRxReset }, 3473 { "phymodRxSquelchOn", phymodRxSquelchOn }, 3474 { "phymodRxSquelchOff", phymodRxSquelchOff }, 3475 { "phymodRxDisable", phymodRxDisable }, 3476 { "phymodRxCount", phymodRxCount }, 3477 { NULL } 3478 }; 3479 3480 static cint_enum_map_t __cint_enum_map__phymod_interface_t[] = 3481 { 3482 { "phymodInterfaceBypass", phymodInterfaceBypass }, 3483 { "phymodInterfaceSR", phymodInterfaceSR }, 3484 { "phymodInterfaceSR4", phymodInterfaceSR4 }, 3485 { "phymodInterfaceKX", phymodInterfaceKX }, 3486 { "phymodInterfaceKX4", phymodInterfaceKX4 }, 3487 { "phymodInterfaceKR", phymodInterfaceKR }, 3488 { "phymodInterfaceKR2", phymodInterfaceKR2 }, 3489 { "phymodInterfaceKR4", phymodInterfaceKR4 }, 3490 { "phymodInterfaceCX", phymodInterfaceCX }, 3491 { "phymodInterfaceCX2", phymodInterfaceCX2 }, 3492 { "phymodInterfaceCX4", phymodInterfaceCX4 }, 3493 { "phymodInterfaceCR", phymodInterfaceCR }, 3494 { "phymodInterfaceCR2", phymodInterfaceCR2 }, 3495 { "phymodInterfaceCR4", phymodInterfaceCR4 }, 3496 { "phymodInterfaceCR10", phymodInterfaceCR10 }, 3497 { "phymodInterfaceXFI", phymodInterfaceXFI }, 3498 { "phymodInterfaceSFI", phymodInterfaceSFI }, 3499 { "phymodInterfaceSFPDAC", phymodInterfaceSFPDAC }, 3500 { "phymodInterfaceXGMII", phymodInterfaceXGMII }, 3501 { "phymodInterface1000X", phymodInterface1000X }, 3502 { "phymodInterfaceSGMII", phymodInterfaceSGMII }, 3503 { "phymodInterfaceXAUI", phymodInterfaceXAUI }, 3504 { "phymodInterfaceRXAUI", phymodInterfaceRXAUI }, 3505 { "phymodInterfaceX2", phymodInterfaceX2 }, 3506 { "phymodInterfaceXLAUI", phymodInterfaceXLAUI }, 3507 { "phymodInterfaceXLAUI2", phymodInterfaceXLAUI2 }, 3508 { "phymodInterfaceCAUI", phymodInterfaceCAUI }, 3509 { "phymodInterfaceQSGMII", phymodInterfaceQSGMII }, 3510 { "phymodInterfaceLR4", phymodInterfaceLR4 }, 3511 { "phymodInterfaceLR", phymodInterfaceLR }, 3512 { "phymodInterfaceLR2", phymodInterfaceLR2 }, 3513 { "phymodInterfaceER", phymodInterfaceER }, 3514 { "phymodInterfaceER2", phymodInterfaceER2 }, 3515 { "phymodInterfaceER4", phymodInterfaceER4 }, 3516 { "phymodInterfaceSR2", phymodInterfaceSR2 }, 3517 { "phymodInterfaceSR10", phymodInterfaceSR10 }, 3518 { "phymodInterfaceCAUI4", phymodInterfaceCAUI4 }, 3519 { "phymodInterfaceVSR", phymodInterfaceVSR }, 3520 { "phymodInterfaceLR10", phymodInterfaceLR10 }, 3521 { "phymodInterfaceKR10", phymodInterfaceKR10 }, 3522 { "phymodInterfaceCAUI4_C2C", phymodInterfaceCAUI4_C2C }, 3523 { "phymodInterfaceCAUI4_C2M", phymodInterfaceCAUI4_C2M }, 3524 { "phymodInterfaceZR", phymodInterfaceZR }, 3525 { "phymodInterfaceLRM", phymodInterfaceLRM }, 3526 { "phymodInterfaceXLPPI", phymodInterfaceXLPPI }, 3527 { "phymodInterfaceOTN", phymodInterfaceOTN }, 3528 { "phymodInterfaceCount", phymodInterfaceCount }, 3529 { NULL } 3530 }; 3531 3532 static cint_enum_map_t __cint_enum_map__phymod_ref_clk_t[] = 3533 { 3534 { "phymodRefClk156Mhz", phymodRefClk156Mhz }, 3535 { "phymodRefClk125Mhz", phymodRefClk125Mhz }, 3536 { "phymodRefClk106Mhz", phymodRefClk106Mhz }, 3537 { "phymodRefClk161Mhz", phymodRefClk161Mhz }, 3538 { "phymodRefClk174Mhz", phymodRefClk174Mhz }, 3539 { "phymodRefClk312Mhz", phymodRefClk312Mhz }, 3540 { "phymodRefClk322Mhz", phymodRefClk322Mhz }, 3541 { "phymodRefClk349Mhz", phymodRefClk349Mhz }, 3542 { "phymodRefClk644Mhz", phymodRefClk644Mhz }, 3543 { "phymodRefClk698Mhz", phymodRefClk698Mhz }, 3544 { "phymodRefClk155Mhz", phymodRefClk155Mhz }, 3545 { "phymodRefClk156P6Mhz", phymodRefClk156P6Mhz }, 3546 { "phymodRefClk157Mhz", phymodRefClk157Mhz }, 3547 { "phymodRefClk158Mhz", phymodRefClk158Mhz }, 3548 { "phymodRefClk159Mhz", phymodRefClk159Mhz }, 3549 { "phymodRefClk168Mhz", phymodRefClk168Mhz }, 3550 { "phymodRefClk172Mhz", phymodRefClk172Mhz }, 3551 { "phymodRefClk173Mhz", phymodRefClk173Mhz }, 3552 { "phymodRefClk169P409Mhz", phymodRefClk169P409Mhz }, 3553 { "phymodRefClk348P125Mhz", phymodRefClk348P125Mhz }, 3554 { "phymodRefClk162P948Mhz", phymodRefClk162P948Mhz }, 3555 { "phymodRefClk336P094Mhz", phymodRefClk336P094Mhz }, 3556 { "phymodRefClk168P12Mhz", phymodRefClk168P12Mhz }, 3557 { "phymodRefClk346P74Mhz", phymodRefClk346P74Mhz }, 3558 { "phymodRefClk167P41Mhz", phymodRefClk167P41Mhz }, 3559 { "phymodRefClk345P28Mhz", phymodRefClk345P28Mhz }, 3560 { "phymodRefClk162P26Mhz", phymodRefClk162P26Mhz }, 3561 { "phymodRefClk334P66Mhz", phymodRefClk334P66Mhz }, 3562 { "phymodRefClkCount", phymodRefClkCount }, 3563 { NULL } 3564 }; 3565 3566 static cint_enum_map_t __cint_enum_map__phymod_triple_core_t[] = 3567 { 3568 { "phymodTripleCore444", phymodTripleCore444 }, 3569 { "phymodTripleCore343", phymodTripleCore343 }, 3570 { "phymodTripleCore442", phymodTripleCore442 }, 3571 { "phymodTripleCore244", phymodTripleCore244 }, 3572 { "phymodTripleCoreCount", phymodTripleCoreCount }, 3573 { NULL } 3574 }; 3575 3576 static cint_enum_map_t __cint_enum_map__phymod_otn_type_t[] = 3577 { 3578 { "phymodOTNOTU1", phymodOTNOTU1 }, 3579 { "phymodOTNOTU1e", phymodOTNOTU1e }, 3580 { "phymodOTNOTU2", phymodOTNOTU2 }, 3581 { "phymodOTNOTU2e", phymodOTNOTU2e }, 3582 { "phymodOTNOTU2f", phymodOTNOTU2f }, 3583 { "phymodOTNOTU3", phymodOTNOTU3 }, 3584 { "phymodOTNOTU3e2", phymodOTNOTU3e2 }, 3585 { "phymodOTNOTU4", phymodOTNOTU4 }, 3586 { "phymodOTNOTU4p10", phymodOTNOTU4p10 }, 3587 { "phymodOTNCount", phymodOTNCount }, 3588 { NULL } 3589 }; 3590 3591 static cint_enum_map_t __cint_enum_map__phymod_an_mode_type_t[] = 3592 { 3593 { "phymod_AN_MODE_NONE", phymod_AN_MODE_NONE }, 3594 { "phymod_AN_MODE_CL73", phymod_AN_MODE_CL73 }, 3595 { "phymod_AN_MODE_CL37", phymod_AN_MODE_CL37 }, 3596 { "phymod_AN_MODE_CL73BAM", phymod_AN_MODE_CL73BAM }, 3597 { "phymod_AN_MODE_CL37BAM", phymod_AN_MODE_CL37BAM }, 3598 { "phymod_AN_MODE_HPAM", phymod_AN_MODE_HPAM }, 3599 { "phymod_AN_MODE_SGMII", phymod_AN_MODE_SGMII }, 3600 { "phymod_AN_MODE_CL37BAM_10P9375G_VCO", phymod_AN_MODE_CL37BAM_10P9375G_VCO }, 3601 { "phymod_AN_MODE_CL37_SGMII", phymod_AN_MODE_CL37_SGMII }, 3602 { "phymod_AN_MODE_CL73_MSA", phymod_AN_MODE_CL73_MSA }, 3603 { "phymod_AN_MODE_MSA", phymod_AN_MODE_MSA }, 3604 { "phymod_AN_MODE_Count", phymod_AN_MODE_Count }, 3605 { NULL } 3606 }; 3607 3608 static cint_enum_map_t __cint_enum_map__phymod_cl37_sgmii_speed_t[] = 3609 { 3610 { "phymod_CL37_SGMII_10M", phymod_CL37_SGMII_10M }, 3611 { "phymod_CL37_SGMII_100M", phymod_CL37_SGMII_100M }, 3612 { "phymod_CL37_SGMII_1000M", phymod_CL37_SGMII_1000M }, 3613 { "phymod_CL37_SGMII_2500M", phymod_CL37_SGMII_2500M }, 3614 { "phymod_CL37_SGMII_Count", phymod_CL37_SGMII_Count }, 3615 { NULL } 3616 }; 3617 3618 static cint_enum_map_t __cint_enum_map__phymod_firmware_load_force_t[] = 3619 { 3620 { "phymodFirmwareLoadSkip", phymodFirmwareLoadSkip }, 3621 { "phymodFirmwareLoadForce", phymodFirmwareLoadForce }, 3622 { "phymodFirmwareLoadAuto", phymodFirmwareLoadAuto }, 3623 { "phymodFirmwareLoadCount", phymodFirmwareLoadCount }, 3624 { NULL } 3625 }; 3626 3627 static cint_enum_map_t __cint_enum_map__phymod_firmware_load_method_t[] = 3628 { 3629 { "phymodFirmwareLoadMethodNone", phymodFirmwareLoadMethodNone }, 3630 { "phymodFirmwareLoadMethodInternal", phymodFirmwareLoadMethodInternal }, 3631 { "phymodFirmwareLoadMethodExternal", phymodFirmwareLoadMethodExternal }, 3632 { "phymodFirmwareLoadMethodProgEEPROM", phymodFirmwareLoadMethodProgEEPROM }, 3633 { "phymodFirmwareLoadMethodCount", phymodFirmwareLoadMethodCount }, 3634 { NULL } 3635 }; 3636 3637 static cint_enum_map_t __cint_enum_map__phymod_datapath_t[] = 3638 { 3639 { "phymodDatapathNormal", phymodDatapathNormal }, 3640 { "phymodDatapathUll", phymodDatapathUll }, 3641 { "phymodDatapathCount", phymodDatapathCount }, 3642 { NULL } 3643 }; 3644 3645 static cint_enum_map_t __cint_enum_map__phymod_tx_input_voltage_t[] = 3646 { 3647 { "phymodTxInputVoltageDefault", phymodTxInputVoltageDefault }, 3648 { "phymodTxInputVoltage1p00", phymodTxInputVoltage1p00 }, 3649 { "phymodTxInputVoltage1p25", phymodTxInputVoltage1p25 }, 3650 { "phymodTxInputVoltageCount", phymodTxInputVoltageCount }, 3651 { NULL } 3652 }; 3653 3654 static cint_enum_map_t __cint_enum_map__phymod_operation_mode_t[] = 3655 { 3656 { "phymodOperationModeRetimer", phymodOperationModeRetimer }, 3657 { "phymodOperationModeRepeater", phymodOperationModeRepeater }, 3658 { "phymodOperationModePassthru", phymodOperationModePassthru }, 3659 { "phymodOperationModeCount", phymodOperationModeCount }, 3660 { NULL } 3661 }; 3662 3663 static cint_enum_map_t __cint_enum_map__phymod_autoneg_link_qualifier_t[] = 3664 { 3665 { "phymodAutonegLinkQualifierRegisterWrite", phymodAutonegLinkQualifierRegisterWrite }, 3666 { "phymodAutonegLinkQualifierKRBlockLock", phymodAutonegLinkQualifierKRBlockLock }, 3667 { "phymodAutonegLinkQualifierKR4BlockLock", phymodAutonegLinkQualifierKR4BlockLock }, 3668 { "phymodAutonegLinkQualifierKR4PMDLock", phymodAutonegLinkQualifierKR4PMDLock }, 3669 { "phymodAutonegLinkQualifierExternalPCS", phymodAutonegLinkQualifierExternalPCS }, 3670 { "phymodAutonegLinkQualifierDefault", phymodAutonegLinkQualifierDefault }, 3671 { "phymodAutonegLinkQualifierCount", phymodAutonegLinkQualifierCount }, 3672 { NULL } 3673 }; 3674 3675 static cint_enum_map_t __cint_enum_map__phymod_loopback_mode_t[] = 3676 { 3677 { "phymodLoopbackGlobal", phymodLoopbackGlobal }, 3678 { "phymodLoopbackGlobalPMD", phymodLoopbackGlobalPMD }, 3679 { "phymodLoopbackGlobalPCS", phymodLoopbackGlobalPCS }, 3680 { "phymodLoopbackRemotePMD", phymodLoopbackRemotePMD }, 3681 { "phymodLoopbackRemotePCS", phymodLoopbackRemotePCS }, 3682 { "phymodLoopbackSysGlobal", phymodLoopbackSysGlobal }, 3683 { "phymodLoopbackSysGlobalPMD", phymodLoopbackSysGlobalPMD }, 3684 { "phymodLoopbackSysGlobalPCS", phymodLoopbackSysGlobalPCS }, 3685 { "phymodLoopbackSysRemotePMD", phymodLoopbackSysRemotePMD }, 3686 { "phymodLoopbackSysRemotePCS", phymodLoopbackSysRemotePCS }, 3687 { "phymodLoopbackCount", phymodLoopbackCount }, 3688 { NULL } 3689 }; 3690 3691 static cint_enum_map_t __cint_enum_map__phymod_pcs_userspeed_mode_t[] = 3692 { 3693 { "phymodPcsUserSpeedModeST", phymodPcsUserSpeedModeST }, 3694 { "phymodPcsUserSpeedModeHTO", phymodPcsUserSpeedModeHTO }, 3695 { "phymodPcsUserSpeedModeCount", phymodPcsUserSpeedModeCount }, 3696 { NULL } 3697 }; 3698 3699 static cint_enum_map_t __cint_enum_map__phymod_pcs_userspeed_param_t[] = 3700 { 3701 { "phymodPcsUserSpeedParamEntry", phymodPcsUserSpeedParamEntry }, 3702 { "phymodPcsUserSpeedParamHCD", phymodPcsUserSpeedParamHCD }, 3703 { "phymodPcsUserSpeedParamClear", phymodPcsUserSpeedParamClear }, 3704 { "phymodPcsUserSpeedParamPllDiv", phymodPcsUserSpeedParamPllDiv }, 3705 { "phymodPcsUserSpeedParamPmaOS", phymodPcsUserSpeedParamPmaOS }, 3706 { "phymodPcsUserSpeedParamScramble", phymodPcsUserSpeedParamScramble }, 3707 { "phymodPcsUserSpeedParamEncode", phymodPcsUserSpeedParamEncode }, 3708 { "phymodPcsUserSpeedParamCl48CheckEnd", phymodPcsUserSpeedParamCl48CheckEnd }, 3709 { "phymodPcsUserSpeedParamBlkSync", phymodPcsUserSpeedParamBlkSync }, 3710 { "phymodPcsUserSpeedParamReorder", phymodPcsUserSpeedParamReorder }, 3711 { "phymodPcsUserSpeedParamCl36Enable", phymodPcsUserSpeedParamCl36Enable }, 3712 { "phymodPcsUserSpeedParamDescr1", phymodPcsUserSpeedParamDescr1 }, 3713 { "phymodPcsUserSpeedParamDecode1", phymodPcsUserSpeedParamDecode1 }, 3714 { "phymodPcsUserSpeedParamDeskew", phymodPcsUserSpeedParamDeskew }, 3715 { "phymodPcsUserSpeedParamDescr2", phymodPcsUserSpeedParamDescr2 }, 3716 { "phymodPcsUserSpeedParamDescr2ByteDel", phymodPcsUserSpeedParamDescr2ByteDel }, 3717 { "phymodPcsUserSpeedParamBrcm64B66", phymodPcsUserSpeedParamBrcm64B66 }, 3718 { "phymodPcsUserSpeedParamSgmii", phymodPcsUserSpeedParamSgmii }, 3719 { "phymodPcsUserSpeedParamClkcnt0", phymodPcsUserSpeedParamClkcnt0 }, 3720 { "phymodPcsUserSpeedParamClkcnt1", phymodPcsUserSpeedParamClkcnt1 }, 3721 { "phymodPcsUserSpeedParamLpcnt0", phymodPcsUserSpeedParamLpcnt0 }, 3722 { "phymodPcsUserSpeedParamLpcnt1", phymodPcsUserSpeedParamLpcnt1 }, 3723 { "phymodPcsUserSpeedParamMacCGC", phymodPcsUserSpeedParamMacCGC }, 3724 { "phymodPcsUserSpeedParamRepcnt", phymodPcsUserSpeedParamRepcnt }, 3725 { "phymodPcsUserSpeedParamCrdtEn", phymodPcsUserSpeedParamCrdtEn }, 3726 { "phymodPcsUserSpeedParamPcsClkcnt", phymodPcsUserSpeedParamPcsClkcnt }, 3727 { "phymodPcsUserSpeedParamPcsCGC", phymodPcsUserSpeedParamPcsCGC }, 3728 { "phymodPcsUserSpeedParamCl72En", phymodPcsUserSpeedParamCl72En }, 3729 { "phymodPcsUserSpeedParamNumOfLanes", phymodPcsUserSpeedParamNumOfLanes }, 3730 { "phymodPcsUserSpeedParamCount", phymodPcsUserSpeedParamCount }, 3731 { NULL } 3732 }; 3733 3734 static cint_enum_map_t __cint_enum_map__phymod_gpio_mode_t[] = 3735 { 3736 { "phymodGpioModeDisabled", phymodGpioModeDisabled }, 3737 { "phymodGpioModeOutput", phymodGpioModeOutput }, 3738 { "phymodGpioModeInput", phymodGpioModeInput }, 3739 { "phymodGpioModeCount", phymodGpioModeCount }, 3740 { NULL } 3741 }; 3742 3743 static cint_enum_map_t __cint_enum_map__phymod_osr_mode_t[] = 3744 { 3745 { "phymodOversampleMode1", phymodOversampleMode1 }, 3746 { "phymodOversampleMode2", phymodOversampleMode2 }, 3747 { "phymodOversampleMode3", phymodOversampleMode3 }, 3748 { "phymodOversampleMode3P3", phymodOversampleMode3P3 }, 3749 { "phymodOversampleMode4", phymodOversampleMode4 }, 3750 { "phymodOversampleMode5", phymodOversampleMode5 }, 3751 { "phymodOversampleMode7P5", phymodOversampleMode7P5 }, 3752 { "phymodOversampleMode8", phymodOversampleMode8 }, 3753 { "phymodOversampleMode8P25", phymodOversampleMode8P25 }, 3754 { "phymodOversampleMode10", phymodOversampleMode10 }, 3755 { "phymodOversampleMode16P5", phymodOversampleMode16P5 }, 3756 { "phymodOversampleMode20P625", phymodOversampleMode20P625 }, 3757 { "phymodOversampleModeCount", phymodOversampleModeCount }, 3758 { NULL } 3759 }; 3760 3761 static cint_enum_map_t __cint_enum_map__phymod_timesync_timer_mode_t[] = 3762 { 3763 { "phymodTimesyncTimerModeNone", phymodTimesyncTimerModeNone }, 3764 { "phymodTimesyncTimerModeDefault", phymodTimesyncTimerModeDefault }, 3765 { "phymodTimesyncTimerMode32Bit", phymodTimesyncTimerMode32Bit }, 3766 { "phymodTimesyncTimerMode48Bit", phymodTimesyncTimerMode48Bit }, 3767 { "phymodTimesyncTimerMode64Bit", phymodTimesyncTimerMode64Bit }, 3768 { "phymodTimesyncTimerMode80Bit", phymodTimesyncTimerMode80Bit }, 3769 { "phymodTimesyncTimerModeCount", phymodTimesyncTimerModeCount }, 3770 { NULL } 3771 }; 3772 3773 static cint_enum_map_t __cint_enum_map__phymod_timesync_global_mode_t[] = 3774 { 3775 { "phymodTimesyncGLobalModeFree", phymodTimesyncGLobalModeFree }, 3776 { "phymodTimesyncGLobalModeSyncIn", phymodTimesyncGLobalModeSyncIn }, 3777 { "phymodTimesyncGLobalModeCpu", phymodTimesyncGLobalModeCpu }, 3778 { "phymodTimesyncGLobalModeCount", phymodTimesyncGLobalModeCount }, 3779 { NULL } 3780 }; 3781 3782 static cint_enum_map_t __cint_enum_map__phymod_timesync_framesync_mode_t[] = 3783 { 3784 { "phymodTimesyncFramsyncModeNone", phymodTimesyncFramsyncModeNone }, 3785 { "phymodTimesyncFramsyncModeSyncIn0", phymodTimesyncFramsyncModeSyncIn0 }, 3786 { "phymodTimesyncFramsyncModeSyncIn1", phymodTimesyncFramsyncModeSyncIn1 }, 3787 { "phymodTimesyncFramsyncModeSyncOut", phymodTimesyncFramsyncModeSyncOut }, 3788 { "phymodTimesyncFramsyncModeCpu", phymodTimesyncFramsyncModeCpu }, 3789 { "phymodTimesyncFramsyncModeCount", phymodTimesyncFramsyncModeCount }, 3790 { NULL } 3791 }; 3792 3793 static cint_enum_map_t __cint_enum_map__phymod_timesync_syncout_mode_t[] = 3794 { 3795 { "phymodTimesyncSyncoutModeDisable", phymodTimesyncSyncoutModeDisable }, 3796 { "phymodTimesyncSyncoutModeOneTime", phymodTimesyncSyncoutModeOneTime }, 3797 { "phymodTimesyncSyncoutModePulseTrain", phymodTimesyncSyncoutModePulseTrain }, 3798 { "phymodTimesyncSyncoutModePulseTrainWithSync", phymodTimesyncSyncoutModePulseTrainWithSync }, 3799 { "phymodTimesyncSyncoutModeCount", phymodTimesyncSyncoutModeCount }, 3800 { NULL } 3801 }; 3802 3803 static cint_enum_map_t __cint_enum_map__phymod_timesync_event_msg_action_t[] = 3804 { 3805 { "phymodTimesyncEventMsgActionNone", phymodTimesyncEventMsgActionNone }, 3806 { "phymodTimesyncEventMsgActionEgrModeUpdateCorrectionField", phymodTimesyncEventMsgActionEgrModeUpdateCorrectionField }, 3807 { "phymodTimesyncEventMsgActionEgrModeReplaceCorrectionFieldOrigin", phymodTimesyncEventMsgActionEgrModeReplaceCorrectionFieldOrigin }, 3808 { "phymodTimesyncEventMsgActionEgrModeCaptureTimestamp", phymodTimesyncEventMsgActionEgrModeCaptureTimestamp }, 3809 { "phymodTimesyncEventMsgActionIngModeUpdateCorrectionField", phymodTimesyncEventMsgActionIngModeUpdateCorrectionField }, 3810 { "phymodTimesyncEventMsgActionIngModeInsertTimestamp", phymodTimesyncEventMsgActionIngModeInsertTimestamp }, 3811 { "phymodTimesyncEventMsgActionIngModeInsertDelaytime", phymodTimesyncEventMsgActionIngModeInsertDelaytime }, 3812 { "phymodTimesyncEventMsgActionCount", phymodTimesyncEventMsgActionCount }, 3813 { NULL } 3814 }; 3815 3816 static cint_enum_map_t __cint_enum_map__phymod_timesync_compensation_mode_t[] = 3817 { 3818 { "phymodTimesyncCompensationModeNone", phymodTimesyncCompensationModeNone }, 3819 { "phymodTimesyncCompensationModeEarliestLane", phymodTimesyncCompensationModeEarliestLane }, 3820 { "phymodTimesyncCompensationModeLatestlane", phymodTimesyncCompensationModeLatestlane }, 3821 { "phymodTimesyncCompensationModeCount", phymodTimesyncCompensationModeCount }, 3822 { NULL } 3823 }; 3824 3825 static cint_enum_map_t __cint_enum_map__phymod_edc_config_method_t[] = 3826 { 3827 { "phymodEdcConfigMethodNone", phymodEdcConfigMethodNone }, 3828 { "phymodEdcConfigMethodHardware", phymodEdcConfigMethodHardware }, 3829 { "phymodEdcConfigMethodSoftware", phymodEdcConfigMethodSoftware }, 3830 { "phymodEdcConfigMethodCount", phymodEdcConfigMethodCount }, 3831 { NULL } 3832 }; 3833 3834 static cint_enum_map_t __cint_enum_map__phymod_core_mode_t[] = 3835 { 3836 { "phymodCoreModeDefault", phymodCoreModeDefault }, 3837 { "phymodCoreModeSingle", phymodCoreModeSingle }, 3838 { "phymodCoreModeDual", phymodCoreModeDual }, 3839 { "phymodCoreModeIndepLane", phymodCoreModeIndepLane }, 3840 { "phymodCoreModeSplit012", phymodCoreModeSplit012 }, 3841 { "phymodCoreModeSplit023", phymodCoreModeSplit023 }, 3842 { "phymodCoreModeTriple244", phymodCoreModeTriple244 }, 3843 { "phymodCoreModeTriple343", phymodCoreModeTriple343 }, 3844 { "phymodCoreModeTriple442", phymodCoreModeTriple442 }, 3845 { "phymodCoreModeCount", phymodCoreModeCount }, 3846 { NULL } 3847 }; 3848 3849 static cint_enum_map_t __cint_enum_map__phymod_failover_mode_t[] = 3850 { 3851 { "phymodFailovermodeNone", phymodFailovermodeNone }, 3852 { "phymodFailovermodeEnable", phymodFailovermodeEnable }, 3853 { "phymodFailovermodeCount", phymodFailovermodeCount }, 3854 { NULL } 3855 }; 3856 3857 static cint_enum_map_t __cint_enum_map__phymod_eye_margin_mode_t[] = 3858 { 3859 { "phymod_eye_marign_HZ_L", phymod_eye_marign_HZ_L }, 3860 { "phymod_eye_marign_HZ_R", phymod_eye_marign_HZ_R }, 3861 { "phymod_eye_marign_VT_U", phymod_eye_marign_VT_U }, 3862 { "phymod_eye_marign_VT_D", phymod_eye_marign_VT_D }, 3863 { "phymod_eye_marign_Count", phymod_eye_marign_Count }, 3864 { NULL } 3865 }; 3866 3867 static cint_enum_map_t __cint_enum_map__phymod_tsce_pll_multiplier_t[] = 3868 { 3869 { "phymod_TSCE_PLL_DIV46", phymod_TSCE_PLL_DIV46 }, 3870 { "phymod_TSCE_PLL_DIV72", phymod_TSCE_PLL_DIV72 }, 3871 { "phymod_TSCE_PLL_DIV40", phymod_TSCE_PLL_DIV40 }, 3872 { "phymod_TSCE_PLL_DIV42", phymod_TSCE_PLL_DIV42 }, 3873 { "phymod_TSCE_PLL_DIV48", phymod_TSCE_PLL_DIV48 }, 3874 { "phymod_TSCE_PLL_DIV50", phymod_TSCE_PLL_DIV50 }, 3875 { "phymod_TSCE_PLL_DIV52", phymod_TSCE_PLL_DIV52 }, 3876 { "phymod_TSCE_PLL_DIV54", phymod_TSCE_PLL_DIV54 }, 3877 { "phymod_TSCE_PLL_DIV60", phymod_TSCE_PLL_DIV60 }, 3878 { "phymod_TSCE_PLL_DIV64", phymod_TSCE_PLL_DIV64 }, 3879 { "phymod_TSCE_PLL_DIV66", phymod_TSCE_PLL_DIV66 }, 3880 { "phymod_TSCE_PLL_DIV68", phymod_TSCE_PLL_DIV68 }, 3881 { "phymod_TSCE_PLL_DIV70", phymod_TSCE_PLL_DIV70 }, 3882 { "phymod_TSCE_PLL_DIV80", phymod_TSCE_PLL_DIV80 }, 3883 { "phymod_TSCE_PLL_DIV92", phymod_TSCE_PLL_DIV92 }, 3884 { "phymod_TSCE_PLL_DIV100", phymod_TSCE_PLL_DIV100 }, 3885 { "phymod_TSCE_PLL_DIV82P5", phymod_TSCE_PLL_DIV82P5 }, 3886 { "phymod_TSCE_PLL_DIV87P5", phymod_TSCE_PLL_DIV87P5 }, 3887 { "phymod_TSCE_PLL_Count", phymod_TSCE_PLL_Count }, 3888 { NULL } 3889 }; 3890 3891 static cint_enum_map_t __cint_enum_map__phymod_tscf_pll_multiplier_t[] = 3892 { 3893 { "phymod_TSCF_PLL_DIV64", phymod_TSCF_PLL_DIV64 }, 3894 { "phymod_TSCF_PLL_DIV66", phymod_TSCF_PLL_DIV66 }, 3895 { "phymod_TSCF_PLL_DIV80", phymod_TSCF_PLL_DIV80 }, 3896 { "phymod_TSCF_PLL_DIV128", phymod_TSCF_PLL_DIV128 }, 3897 { "phymod_TSCF_PLL_DIV132", phymod_TSCF_PLL_DIV132 }, 3898 { "phymod_TSCF_PLL_DIV140", phymod_TSCF_PLL_DIV140 }, 3899 { "phymod_TSCF_PLL_DIV160", phymod_TSCF_PLL_DIV160 }, 3900 { "phymod_TSCF_PLL_DIV165", phymod_TSCF_PLL_DIV165 }, 3901 { "phymod_TSCF_PLL_DIV168", phymod_TSCF_PLL_DIV168 }, 3902 { "phymod_TSCF_PLL_DIV170", phymod_TSCF_PLL_DIV170 }, 3903 { "phymod_TSCF_PLL_DIV175", phymod_TSCF_PLL_DIV175 }, 3904 { "phymod_TSCF_PLL_DIV180", phymod_TSCF_PLL_DIV180 }, 3905 { "phymod_TSCF_PLL_DIV184", phymod_TSCF_PLL_DIV184 }, 3906 { "phymod_TSCF_PLL_DIV200", phymod_TSCF_PLL_DIV200 }, 3907 { "phymod_TSCF_PLL_DIV224", phymod_TSCF_PLL_DIV224 }, 3908 { "phymod_TSCF_PLL_DIV264", phymod_TSCF_PLL_DIV264 }, 3909 { "phymod_TSCF_PLL_DIV96", phymod_TSCF_PLL_DIV96 }, 3910 { "phymod_TSCF_PLL_DIV120", phymod_TSCF_PLL_DIV120 }, 3911 { "phymod_TSCF_PLL_DIV144", phymod_TSCF_PLL_DIV144 }, 3912 { "phymod_TSCF_PLL_DIV198", phymod_TSCF_PLL_DIV198 }, 3913 { "phymod_TSCF_PLL_Count", phymod_TSCF_PLL_Count }, 3914 { NULL } 3915 }; 3916 3917 static cint_enum_map_t __cint_enum_map__phymod_tscbh_pll_multiplier_t[] = 3918 { 3919 { "phymod_TSCBH_PLL_DIVNONE", phymod_TSCBH_PLL_DIVNONE }, 3920 { "phymod_TSCBH_PLL_DIV66", phymod_TSCBH_PLL_DIV66 }, 3921 { "phymod_TSCBH_PLL_DIV67", phymod_TSCBH_PLL_DIV67 }, 3922 { "phymod_TSCBH_PLL_DIV70", phymod_TSCBH_PLL_DIV70 }, 3923 { "phymod_TSCBH_PLL_DIV72", phymod_TSCBH_PLL_DIV72 }, 3924 { "phymod_TSCBH_PLL_DIV73P6", phymod_TSCBH_PLL_DIV73P6 }, 3925 { "phymod_TSCBH_PLL_DIV79P2", phymod_TSCBH_PLL_DIV79P2 }, 3926 { "phymod_TSCBH_PLL_DIV80", phymod_TSCBH_PLL_DIV80 }, 3927 { "phymod_TSCBH_PLL_DIV82P5", phymod_TSCBH_PLL_DIV82P5 }, 3928 { "phymod_TSCBH_PLL_DIV84", phymod_TSCBH_PLL_DIV84 }, 3929 { "phymod_TSCBH_PLL_DIV85", phymod_TSCBH_PLL_DIV85 }, 3930 { "phymod_TSCBH_PLL_DIV87P5", phymod_TSCBH_PLL_DIV87P5 }, 3931 { "phymod_TSCBH_PLL_DIV89P6", phymod_TSCBH_PLL_DIV89P6 }, 3932 { "phymod_TSCBH_PLL_DIV90", phymod_TSCBH_PLL_DIV90 }, 3933 { "phymod_TSCBH_PLL_DIV96", phymod_TSCBH_PLL_DIV96 }, 3934 { "phymod_TSCBH_PLL_DIV100", phymod_TSCBH_PLL_DIV100 }, 3935 { "phymod_TSCBH_PLL_DIV120", phymod_TSCBH_PLL_DIV120 }, 3936 { "phymod_TSCBH_PLL_DIV127P4", phymod_TSCBH_PLL_DIV127P4 }, 3937 { "phymod_TSCBH_PLL_DIV128", phymod_TSCBH_PLL_DIV128 }, 3938 { "phymod_TSCBH_PLL_DIV132", phymod_TSCBH_PLL_DIV132 }, 3939 { "phymod_TSCBH_PLL_DIV140", phymod_TSCBH_PLL_DIV140 }, 3940 { "phymod_TSCBH_PLL_DIV144", phymod_TSCBH_PLL_DIV144 }, 3941 { "phymod_TSCBH_PLL_DIV147P2", phymod_TSCBH_PLL_DIV147P2 }, 3942 { "phymod_TSCBH_PLL_DIV158P4", phymod_TSCBH_PLL_DIV158P4 }, 3943 { "phymod_TSCBH_PLL_DIV160", phymod_TSCBH_PLL_DIV160 }, 3944 { "phymod_TSCBH_PLL_DIV165", phymod_TSCBH_PLL_DIV165 }, 3945 { "phymod_TSCBH_PLL_DIV168", phymod_TSCBH_PLL_DIV168 }, 3946 { "phymod_TSCBH_PLL_DIV170", phymod_TSCBH_PLL_DIV170 }, 3947 { "phymod_TSCBH_PLL_DIV175", phymod_TSCBH_PLL_DIV175 }, 3948 { "phymod_TSCBH_PLL_DIV180", phymod_TSCBH_PLL_DIV180 }, 3949 { "phymod_TSCBH_PLL_DIV184", phymod_TSCBH_PLL_DIV184 }, 3950 { "phymod_TSCBH_PLL_DIV192", phymod_TSCBH_PLL_DIV192 }, 3951 { "phymod_TSCBH_PLL_DIV198", phymod_TSCBH_PLL_DIV198 }, 3952 { "phymod_TSCBH_PLL_DIV200", phymod_TSCBH_PLL_DIV200 }, 3953 { "phymod_TSCBH_PLL_DIV224", phymod_TSCBH_PLL_DIV224 }, 3954 { "phymod_TSCBH_PLL_DIV240", phymod_TSCBH_PLL_DIV240 }, 3955 { "phymod_TSCBH_PLL_DIV264", phymod_TSCBH_PLL_DIV264 }, 3956 { "phymod_TSCBH_PLL_DIV280", phymod_TSCBH_PLL_DIV280 }, 3957 { "phymod_TSCBH_PLL_Count", phymod_TSCBH_PLL_Count }, 3958 { NULL } 3959 }; 3960 3961 static cint_enum_map_t __cint_enum_map__phymod_fec_type_t[] = 3962 { 3963 { "phymod_fec_None", phymod_fec_None }, 3964 { "phymod_fec_CL74", phymod_fec_CL74 }, 3965 { "phymod_fec_CL91", phymod_fec_CL91 }, 3966 { "phymod_fec_RS544", phymod_fec_RS544 }, 3967 { "phymod_fec_RS272", phymod_fec_RS272 }, 3968 { "phymod_fec_RS544_2XN", phymod_fec_RS544_2XN }, 3969 { "phymod_fec_RS272_2XN", phymod_fec_RS272_2XN }, 3970 { "phymod_fec_Count", phymod_fec_Count }, 3971 { NULL } 3972 }; 3973 3974 static cint_enum_map_t __cint_enum_map__phymod_dfe_mode_t[] = 3975 { 3976 { "phymod_dfe_off", phymod_dfe_off }, 3977 { "phymod_dfe_on", phymod_dfe_on }, 3978 { "phymod_dfe_lp_on", phymod_dfe_lp_on }, 3979 { "phymod_dfe_Count", phymod_dfe_Count }, 3980 { NULL } 3981 }; 3982 3983 static cint_enum_map_t __cint_enum_map__phymod_pause_type_t[] = 3984 { 3985 { "phymod_pause_none", phymod_pause_none }, 3986 { "phymod_pause_symm", phymod_pause_symm }, 3987 { "phymod_pause_asym", phymod_pause_asym }, 3988 { "phymod_pause_asym_symm", phymod_pause_asym_symm }, 3989 { "phymod_pause_Count", phymod_pause_Count }, 3990 { NULL } 3991 }; 3992 3993 static cint_enum_map_t __cint_enum_map__phymod_channel_type_t[] = 3994 { 3995 { "phymod_channel_long", phymod_channel_long }, 3996 { "phymod_channel_short", phymod_channel_short }, 3997 { "phymod_channel_Count", phymod_channel_Count }, 3998 { NULL } 3999 }; 4000 4001 static cint_enum_map_t __cint_enum_map__phymod_interrupt_type_t[] = 4002 { 4003 { "phymodIntrNone", phymodIntrNone }, 4004 { "phymodIntrEccRx1588400g", phymodIntrEccRx1588400g }, 4005 { "phymodIntrEccRx1588Mpp1", phymodIntrEccRx1588Mpp1 }, 4006 { "phymodIntrEccRx1588Mpp0", phymodIntrEccRx1588Mpp0 }, 4007 { "phymodIntrEccTx1588400g", phymodIntrEccTx1588400g }, 4008 { "phymodIntrEccTx1588Mpp1", phymodIntrEccTx1588Mpp1 }, 4009 { "phymodIntrEccTx1588Mpp0", phymodIntrEccTx1588Mpp0 }, 4010 { "phymodIntrEccUMTable", phymodIntrEccUMTable }, 4011 { "phymodIntrEccAMTable", phymodIntrEccAMTable }, 4012 { "phymodIntrEccSpeedTable", phymodIntrEccSpeedTable }, 4013 { "phymodIntrEccDeskew", phymodIntrEccDeskew }, 4014 { "phymodIntrEccRsFECRs400gMpp1", phymodIntrEccRsFECRs400gMpp1 }, 4015 { "phymodIntrEccRsFECRs400gMpp0", phymodIntrEccRsFECRs400gMpp0 }, 4016 { "phymodIntrEccRsFECRbufMpp1", phymodIntrEccRsFECRbufMpp1 }, 4017 { "phymodIntrEccRsFECRbufMpp0", phymodIntrEccRsFECRbufMpp0 }, 4018 { "phymodIntrEccBaseRFEC", phymodIntrEccBaseRFEC }, 4019 { "phymodIntrCount", phymodIntrCount }, 4020 { NULL } 4021 }; 4022 4023 static cint_enum_map_t __cint_enum_map__phymod_master_mode_t[] = 4024 { 4025 { "phymodMSNone", phymodMSNone }, 4026 { "phymodMSSlave", phymodMSSlave }, 4027 { "phymodMSMaster", phymodMSMaster }, 4028 { "phymodMSAuto", phymodMSAuto }, 4029 { "phymodMSCount", phymodMSCount }, 4030 { NULL } 4031 }; 4032 4033 static cint_enum_map_t __cint_enum_map__phymod_override_type_t[] = 4034 { 4035 { "phymodPMDRxLock ", phymodPMDRxLock }, 4036 { "phymodPMDSignalDetect", phymodPMDSignalDetect }, 4037 { "phymodPMDRxClkValid", phymodPMDRxClkValid }, 4038 { "phymodPMDLaneMode", phymodPMDLaneMode }, 4039 { "phymodPMDOsrMode", phymodPMDOsrMode }, 4040 { "phymodPMDTxDisable", phymodPMDTxDisable }, 4041 { "phymodPMDLaneReset", phymodPMDLaneReset }, 4042 { "phymodPMDTxClkValid", phymodPMDTxClkValid }, 4043 { "phymodPMDCount", phymodPMDCount }, 4044 { NULL } 4045 }; 4046 4047 static cint_enum_map_t __cint_enum_map__phymod_duplex_mode_t[] = 4048 { 4049 { "phymodDuplexHalf", phymodDuplexHalf }, 4050 { "phymodDuplexFull", phymodDuplexFull }, 4051 { "phymodDuplexCount", phymodDuplexCount }, 4052 { NULL } 4053 }; 4054 4055 4056 static cint_enum_type_t __cint_enums[] = 4057 { 4058 {"phymod_dispatch_type_t", __cint_enum_map__phymod_dispatch_type_t }, 4059 {"phymod_mem_type_t", __cint_enum_map__phymod_mem_type_t }, 4060 {"phymod_port_loc_t", __cint_enum_map__phymod_port_loc_t }, 4061 {"phymod_core_version_t", __cint_enum_map__phymod_core_version_t }, 4062 {"phymod_reset_mode_t", __cint_enum_map__phymod_reset_mode_t }, 4063 {"phymod_reset_direction_t", __cint_enum_map__phymod_reset_direction_t }, 4064 {"phymod_firmware_media_type_t", __cint_enum_map__phymod_firmware_media_type_t }, 4065 {"phymod_sequencer_operation_t", __cint_enum_map__phymod_sequencer_operation_t }, 4066 {"phymod_core_event_t", __cint_enum_map__phymod_core_event_t }, 4067 {"phymod_drivermode_t", __cint_enum_map__phymod_drivermode_t }, 4068 {"phymod_tx_tap_mode_t", __cint_enum_map__phymod_tx_tap_mode_t }, 4069 {"phymod_phy_signalling_method_t", __cint_enum_map__phymod_phy_signalling_method_t }, 4070 {"phymod_media_typed_t", __cint_enum_map__phymod_media_typed_t }, 4071 {"phymod_power_t", __cint_enum_map__phymod_power_t }, 4072 {"phymod_phy_hg2_codec_t", __cint_enum_map__phymod_phy_hg2_codec_t }, 4073 {"phymod_phy_tx_lane_control_t", __cint_enum_map__phymod_phy_tx_lane_control_t }, 4074 {"phymod_phy_rx_lane_control_t", __cint_enum_map__phymod_phy_rx_lane_control_t }, 4075 {"phymod_interface_t", __cint_enum_map__phymod_interface_t }, 4076 {"phymod_ref_clk_t", __cint_enum_map__phymod_ref_clk_t }, 4077 {"phymod_triple_core_t", __cint_enum_map__phymod_triple_core_t }, 4078 {"phymod_otn_type_t", __cint_enum_map__phymod_otn_type_t }, 4079 {"phymod_an_mode_type_t", __cint_enum_map__phymod_an_mode_type_t }, 4080 {"phymod_cl37_sgmii_speed_t", __cint_enum_map__phymod_cl37_sgmii_speed_t }, 4081 {"phymod_firmware_load_force_t", __cint_enum_map__phymod_firmware_load_force_t }, 4082 {"phymod_firmware_load_method_t", __cint_enum_map__phymod_firmware_load_method_t }, 4083 {"phymod_datapath_t", __cint_enum_map__phymod_datapath_t }, 4084 {"phymod_tx_input_voltage_t", __cint_enum_map__phymod_tx_input_voltage_t }, 4085 {"phymod_operation_mode_t", __cint_enum_map__phymod_operation_mode_t }, 4086 {"phymod_autoneg_link_qualifier_t", __cint_enum_map__phymod_autoneg_link_qualifier_t }, 4087 {"phymod_loopback_mode_t", __cint_enum_map__phymod_loopback_mode_t }, 4088 {"phymod_pcs_userspeed_mode_t", __cint_enum_map__phymod_pcs_userspeed_mode_t }, 4089 {"phymod_pcs_userspeed_param_t", __cint_enum_map__phymod_pcs_userspeed_param_t }, 4090 {"phymod_gpio_mode_t", __cint_enum_map__phymod_gpio_mode_t }, 4091 {"phymod_osr_mode_t", __cint_enum_map__phymod_osr_mode_t }, 4092 {"phymod_timesync_timer_mode_t", __cint_enum_map__phymod_timesync_timer_mode_t }, 4093 {"phymod_timesync_global_mode_t", __cint_enum_map__phymod_timesync_global_mode_t }, 4094 {"phymod_timesync_framesync_mode_t", __cint_enum_map__phymod_timesync_framesync_mode_t }, 4095 {"phymod_timesync_syncout_mode_t", __cint_enum_map__phymod_timesync_syncout_mode_t }, 4096 {"phymod_timesync_event_msg_action_t", __cint_enum_map__phymod_timesync_event_msg_action_t }, 4097 {"phymod_timesync_compensation_mode_t", __cint_enum_map__phymod_timesync_compensation_mode_t }, 4098 {"phymod_edc_config_method_t", __cint_enum_map__phymod_edc_config_method_t }, 4099 {"phymod_core_mode_t", __cint_enum_map__phymod_core_mode_t }, 4100 {"phymod_failover_mode_t", __cint_enum_map__phymod_failover_mode_t }, 4101 {"phymod_eye_margin_mode_t", __cint_enum_map__phymod_eye_margin_mode_t }, 4102 {"phymod_tsce_pll_multiplier_t", __cint_enum_map__phymod_tsce_pll_multiplier_t }, 4103 {"phymod_tscf_pll_multiplier_t", __cint_enum_map__phymod_tscf_pll_multiplier_t }, 4104 {"phymod_tscbh_pll_multiplier_t", __cint_enum_map__phymod_tscbh_pll_multiplier_t }, 4105 {"phymod_fec_type_t", __cint_enum_map__phymod_fec_type_t }, 4106 {"phymod_dfe_mode_t", __cint_enum_map__phymod_dfe_mode_t }, 4107 {"phymod_pause_type_t", __cint_enum_map__phymod_pause_type_t }, 4108 {"phymod_channel_type_t", __cint_enum_map__phymod_channel_type_t }, 4109 {"phymod_interrupt_type_t", __cint_enum_map__phymod_interrupt_type_t }, 4110 {"phymod_master_mode_t", __cint_enum_map__phymod_master_mode_t }, 4111 {"phymod_override_type_t", __cint_enum_map__phymod_override_type_t }, 4112 {"phymod_duplex_mode_t", __cint_enum_map__phymod_duplex_mode_t }, 4113 { NULL } 4114 }; 4115 4116 /* Defines section */ 4117 static cint_constants_t __cint_constants[] = 4118 { 4119 { "PHYMOD_MAX_LANES_PER_CORE", PHYMOD_MAX_LANES_PER_CORE }, 4120 { "PHYMOD_MAX_LANES_PER_PORT", PHYMOD_MAX_LANES_PER_PORT }, 4121 { "PHYMOD_BUS_CAP_WR_MODIFY", PHYMOD_BUS_CAP_WR_MODIFY }, 4122 { "PHYMOD_BUS_CAP_LANE_CTRL", PHYMOD_BUS_CAP_LANE_CTRL }, 4123 { "PHYMOD_ACC_F_CLAUSE45", PHYMOD_ACC_F_CLAUSE45 }, 4124 { "PHYMOD_ACC_F_QMODE", PHYMOD_ACC_F_QMODE }, 4125 { "PHYMOD_ACC_F_PRECONDITION", PHYMOD_ACC_F_PRECONDITION }, 4126 { "PHYMOD_ACC_F_USXMODE", PHYMOD_ACC_F_USXMODE }, 4127 { "PHYMOD_ACC_F_PHYSIM", PHYMOD_ACC_F_PHYSIM }, 4128 { "PHYMOD_ACC_DEVAD_0_OVERRIDE_MASK", PHYMOD_ACC_DEVAD_0_OVERRIDE_MASK }, 4129 { "PHYMOD_ACC_DEVAD_FORCE_MASK", PHYMOD_ACC_DEVAD_FORCE_MASK }, 4130 { "PHYMOD_ACC_DEVAD_MASK", PHYMOD_ACC_DEVAD_MASK }, 4131 { "PHYMOD_DEVICE_OP_MODE_PCS_BYPASS", PHYMOD_DEVICE_OP_MODE_PCS_BYPASS }, 4132 { "PHYMOD_SEQ_F_WAIT_UNTIL_DONE", PHYMOD_SEQ_F_WAIT_UNTIL_DONE }, 4133 { "PHYMOD_TIMEOUT_DEFAULT", PHYMOD_TIMEOUT_DEFAULT }, 4134 { "PHYMOD_TX_DO_NOT_CHANGE_VAL", PHYMOD_TX_DO_NOT_CHANGE_VAL }, 4135 { "PHYMOD_TXPI_NORMAL_MODE", PHYMOD_TXPI_NORMAL_MODE }, 4136 { "PHYMOD_TXPI_EXT_PD_MODE", PHYMOD_TXPI_EXT_PD_MODE }, 4137 { "PHYMOD_NUM_DFE_TAPS", PHYMOD_NUM_DFE_TAPS }, 4138 { "PHYMOD_RX_ADAPTATION_ON", PHYMOD_RX_ADAPTATION_ON }, 4139 { "PHYMOD_FEC_CL91", PHYMOD_FEC_CL91 }, 4140 { "PHYMOD_FEC_CL108", PHYMOD_FEC_CL108 }, 4141 { "PHYMOD_LPI_BYPASS", PHYMOD_LPI_BYPASS }, 4142 { "PHYMOD_DEFAULT_RATE", PHYMOD_DEFAULT_RATE }, 4143 { "PHYMOD_INTF_MODES_HIGIG", PHYMOD_INTF_MODES_HIGIG }, 4144 { "PHYMOD_INTF_MODES_OS2", PHYMOD_INTF_MODES_OS2 }, 4145 { "PHYMOD_INTF_MODES_SCR", PHYMOD_INTF_MODES_SCR }, 4146 { "PHYMOD_INTF_MODES_HALF_DUPLEX", PHYMOD_INTF_MODES_HALF_DUPLEX }, 4147 { "PHYMOD_INTF_MODES_FIBER", PHYMOD_INTF_MODES_FIBER }, 4148 { "PHYMOD_INTF_MODES_TRIPLE_CORE", PHYMOD_INTF_MODES_TRIPLE_CORE }, 4149 { "PHYMOD_INTF_MODES_TC_343", PHYMOD_INTF_MODES_TC_343 }, 4150 { "PHYMOD_INTF_MODES_TC_442", PHYMOD_INTF_MODES_TC_442 }, 4151 { "PHYMOD_INTF_MODES_TC_244", PHYMOD_INTF_MODES_TC_244 }, 4152 { "PHYMOD_INTF_MODES_BACKPLANE", PHYMOD_INTF_MODES_BACKPLANE }, 4153 { "PHYMOD_INTF_MODES_COPPER", PHYMOD_INTF_MODES_COPPER }, 4154 { "PHYMOD_INTF_MODES_OTN", PHYMOD_INTF_MODES_OTN }, 4155 { "PHYMOD_INTF_MODES_SIMPLEX", PHYMOD_INTF_MODES_SIMPLEX }, 4156 { "PHYMOD_INTF_MODES_UNRELIABLE_LOS", PHYMOD_INTF_MODES_UNRELIABLE_LOS }, 4157 { "PHYMOD_INTF_F_DONT_TURN_OFF_PLL", PHYMOD_INTF_F_DONT_TURN_OFF_PLL }, 4158 { "PHYMOD_INTF_F_DONT_OVERIDE_FW_MODE", PHYMOD_INTF_F_DONT_OVERIDE_FW_MODE }, 4159 { "PHYMOD_INTF_F_DONT_OVERIDE_TX_PARAMS", PHYMOD_INTF_F_DONT_OVERIDE_TX_PARAMS }, 4160 { "PHYMOD_INTF_F_PLL_DIVIDER_OVERRIDE", PHYMOD_INTF_F_PLL_DIVIDER_OVERRIDE }, 4161 { "PHYMOD_INTF_F_PCS_TABLE_OVERRIDE", PHYMOD_INTF_F_PCS_TABLE_OVERRIDE }, 4162 { "PHYMOD_INTF_F_INTF_PARAM_SET_ONLY", PHYMOD_INTF_F_INTF_PARAM_SET_ONLY }, 4163 { "PHYMOD_INTF_F_SET_CORE_MAP_MODE", PHYMOD_INTF_F_SET_CORE_MAP_MODE }, 4164 { "PHYMOD_INTF_F_SET_SPD_TRIGGER", PHYMOD_INTF_F_SET_SPD_TRIGGER }, 4165 { "PHYMOD_INTF_F_SET_SPD_DISABLE", PHYMOD_INTF_F_SET_SPD_DISABLE }, 4166 { "PHYMOD_INTF_F_SET_SPD_NO_TRIGGER", PHYMOD_INTF_F_SET_SPD_NO_TRIGGER }, 4167 { "PHYMOD_INTF_F_CL72_REQUESTED_BY_CNFG", PHYMOD_INTF_F_CL72_REQUESTED_BY_CNFG }, 4168 { "PHYMOD_INTF_F_CL72_REQUESTED_BY_API", PHYMOD_INTF_F_CL72_REQUESTED_BY_API }, 4169 { "PHYMOD_INTF_F_UPDATE_SPEED_LINKUP", PHYMOD_INTF_F_UPDATE_SPEED_LINKUP }, 4170 { "PHYMOD_INTF_F_UPDATE_INTERNAL_SERDES_ONLY", PHYMOD_INTF_F_UPDATE_INTERNAL_SERDES_ONLY }, 4171 { "PHYMOD_INTF_F_CORE_MAP_MODE_FLIP", PHYMOD_INTF_F_CORE_MAP_MODE_FLIP }, 4172 { "PHYMOD_INTF_F_SPEED_CONFIG_CLEAR", PHYMOD_INTF_F_SPEED_CONFIG_CLEAR }, 4173 { "PHYMOD_INTF_F_SCRAMBLE_FORCED_ON", PHYMOD_INTF_F_SCRAMBLE_FORCED_ON }, 4174 { "PHYMOD_INTF_F_SCRAMBLE_FORCED_OFF", PHYMOD_INTF_F_SCRAMBLE_FORCED_OFF }, 4175 { "PHYMOD_INTF_F_SINGLE_PLL_ONLY", PHYMOD_INTF_F_SINGLE_PLL_ONLY }, 4176 { "PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE", PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE }, 4177 { "PHYMOD_INTF_CONFIG_PHY_PIN_COMPATIBILITY_ENABLE", PHYMOD_INTF_CONFIG_PHY_PIN_COMPATIBILITY_ENABLE }, 4178 { "PHYMOD_INTF_CONFIG_PORT_PHY_MODE_REVERSE", PHYMOD_INTF_CONFIG_PORT_PHY_MODE_REVERSE }, 4179 { "PHYMOD_INTF_CONFIG_PHY_PSC_REPEATER_MODE", PHYMOD_INTF_CONFIG_PHY_PSC_REPEATER_MODE }, 4180 { "PHYMOD_INTF_CONFIG_TX_FIR_DRIVERMODE_ENABLE", PHYMOD_INTF_CONFIG_TX_FIR_DRIVERMODE_ENABLE }, 4181 { "PHYMOD_AN_CAP_1G_KX", PHYMOD_AN_CAP_1G_KX }, 4182 { "PHYMOD_AN_CAP_10G_KX4", PHYMOD_AN_CAP_10G_KX4 }, 4183 { "PHYMOD_AN_CAP_10G_KR", PHYMOD_AN_CAP_10G_KR }, 4184 { "PHYMOD_AN_CAP_40G_KR4", PHYMOD_AN_CAP_40G_KR4 }, 4185 { "PHYMOD_AN_CAP_40G_CR4", PHYMOD_AN_CAP_40G_CR4 }, 4186 { "PHYMOD_AN_CAP_100G_CR10", PHYMOD_AN_CAP_100G_CR10 }, 4187 { "PHYMOD_AN_CAP_100G_CR4", PHYMOD_AN_CAP_100G_CR4 }, 4188 { "PHYMOD_AN_CAP_100G_KR4", PHYMOD_AN_CAP_100G_KR4 }, 4189 { "PHYMOD_AN_CAP_100G_KR10", PHYMOD_AN_CAP_100G_KR10 }, 4190 { "PHYMOD_AN_CAP_100M", PHYMOD_AN_CAP_100M }, 4191 { "PHYMOD_AN_CAP_25G_KR1", PHYMOD_AN_CAP_25G_KR1 }, 4192 { "PHYMOD_AN_CAP_25G_CR1", PHYMOD_AN_CAP_25G_CR1 }, 4193 { "PHYMOD_AN_CAP_25G_KRS1", PHYMOD_AN_CAP_25G_KRS1 }, 4194 { "PHYMOD_AN_CAP_25G_CRS1", PHYMOD_AN_CAP_25G_CRS1 }, 4195 { "PHYMOD_AN_CAP_2P5G_X", PHYMOD_AN_CAP_2P5G_X }, 4196 { "PHYMOD_AN_CAP_5G_KR1", PHYMOD_AN_CAP_5G_KR1 }, 4197 { "PHYMOD_BAM_CL73_CAP_20G_KR2", PHYMOD_BAM_CL73_CAP_20G_KR2 }, 4198 { "PHYMOD_BAM_CL73_CAP_20G_CR2", PHYMOD_BAM_CL73_CAP_20G_CR2 }, 4199 { "PHYMOD_BAM_CL73_CAP_40G_KR2", PHYMOD_BAM_CL73_CAP_40G_KR2 }, 4200 { "PHYMOD_BAM_CL73_CAP_40G_CR2", PHYMOD_BAM_CL73_CAP_40G_CR2 }, 4201 { "PHYMOD_BAM_CL73_CAP_50G_KR2", PHYMOD_BAM_CL73_CAP_50G_KR2 }, 4202 { "PHYMOD_BAM_CL73_CAP_50G_CR2", PHYMOD_BAM_CL73_CAP_50G_CR2 }, 4203 { "PHYMOD_BAM_CL73_CAP_50G_KR4", PHYMOD_BAM_CL73_CAP_50G_KR4 }, 4204 { "PHYMOD_BAM_CL73_CAP_50G_CR4", PHYMOD_BAM_CL73_CAP_50G_CR4 }, 4205 { "PHYMOD_BAM_CL73_CAP_20G_KR1", PHYMOD_BAM_CL73_CAP_20G_KR1 }, 4206 { "PHYMOD_BAM_CL73_CAP_20G_CR1", PHYMOD_BAM_CL73_CAP_20G_CR1 }, 4207 { "PHYMOD_BAM_CL73_CAP_25G_KR1", PHYMOD_BAM_CL73_CAP_25G_KR1 }, 4208 { "PHYMOD_BAM_CL73_CAP_25G_CR1", PHYMOD_BAM_CL73_CAP_25G_CR1 }, 4209 { "PHYMOD_BAM_CL37_CAP_2P5G", PHYMOD_BAM_CL37_CAP_2P5G }, 4210 { "PHYMOD_BAM_CL37_CAP_5G_X4", PHYMOD_BAM_CL37_CAP_5G_X4 }, 4211 { "PHYMOD_BAM_CL37_CAP_6G_X4", PHYMOD_BAM_CL37_CAP_6G_X4 }, 4212 { "PHYMOD_BAM_CL37_CAP_10G_HIGIG", PHYMOD_BAM_CL37_CAP_10G_HIGIG }, 4213 { "PHYMOD_BAM_CL37_CAP_10G_CX4", PHYMOD_BAM_CL37_CAP_10G_CX4 }, 4214 { "PHYMOD_BAM_CL37_CAP_12G_X4", PHYMOD_BAM_CL37_CAP_12G_X4 }, 4215 { "PHYMOD_BAM_CL37_CAP_12P5_X4", PHYMOD_BAM_CL37_CAP_12P5_X4 }, 4216 { "PHYMOD_BAM_CL37_CAP_13G_X4", PHYMOD_BAM_CL37_CAP_13G_X4 }, 4217 { "PHYMOD_BAM_CL37_CAP_15G_X4", PHYMOD_BAM_CL37_CAP_15G_X4 }, 4218 { "PHYMOD_BAM_CL37_CAP_16G_X4", PHYMOD_BAM_CL37_CAP_16G_X4 }, 4219 { "PHYMOD_BAM_CL37_CAP_20G_X4_CX4", PHYMOD_BAM_CL37_CAP_20G_X4_CX4 }, 4220 { "PHYMOD_BAM_CL37_CAP_20G_X4", PHYMOD_BAM_CL37_CAP_20G_X4 }, 4221 { "PHYMOD_BAM_CL37_CAP_21G_X4", PHYMOD_BAM_CL37_CAP_21G_X4 }, 4222 { "PHYMOD_BAM_CL37_CAP_25P455G", PHYMOD_BAM_CL37_CAP_25P455G }, 4223 { "PHYMOD_BAM_CL37_CAP_31P5G", PHYMOD_BAM_CL37_CAP_31P5G }, 4224 { "PHYMOD_BAM_CL37_CAP_32P7G", PHYMOD_BAM_CL37_CAP_32P7G }, 4225 { "PHYMOD_BAM_CL37_CAP_40G", PHYMOD_BAM_CL37_CAP_40G }, 4226 { "PHYMOD_BAM_CL37_CAP_10G_X2_CX4", PHYMOD_BAM_CL37_CAP_10G_X2_CX4 }, 4227 { "PHYMOD_BAM_CL37_CAP_10G_DXGXS", PHYMOD_BAM_CL37_CAP_10G_DXGXS }, 4228 { "PHYMOD_BAM_CL37_CAP_10P5G_DXGXS", PHYMOD_BAM_CL37_CAP_10P5G_DXGXS }, 4229 { "PHYMOD_BAM_CL37_CAP_12P7_DXGXS", PHYMOD_BAM_CL37_CAP_12P7_DXGXS }, 4230 { "PHYMOD_BAM_CL37_CAP_15P75G_R2", PHYMOD_BAM_CL37_CAP_15P75G_R2 }, 4231 { "PHYMOD_BAM_CL37_CAP_20G_X2_CX4", PHYMOD_BAM_CL37_CAP_20G_X2_CX4 }, 4232 { "PHYMOD_BAM_CL37_CAP_20G_X2", PHYMOD_BAM_CL37_CAP_20G_X2 }, 4233 { "PHYMOD_AN_FEC_OFF", PHYMOD_AN_FEC_OFF }, 4234 { "PHYMOD_AN_FEC_CL74", PHYMOD_AN_FEC_CL74 }, 4235 { "PHYMOD_AN_FEC_CL91", PHYMOD_AN_FEC_CL91 }, 4236 { "PHYMOD_AN_CAP_CL37", PHYMOD_AN_CAP_CL37 }, 4237 { "PHYMOD_AN_CAP_CL73", PHYMOD_AN_CAP_CL73 }, 4238 { "PHYMOD_AN_CAP_CL37BAM", PHYMOD_AN_CAP_CL37BAM }, 4239 { "PHYMOD_AN_CAP_CL73BAM", PHYMOD_AN_CAP_CL73BAM }, 4240 { "PHYMOD_AN_CAP_HPAM", PHYMOD_AN_CAP_HPAM }, 4241 { "PHYMOD_AN_CAP_SGMII", PHYMOD_AN_CAP_SGMII }, 4242 { "PHYMOD_AN_CAP_SYMM_PAUSE", PHYMOD_AN_CAP_SYMM_PAUSE }, 4243 { "PHYMOD_AN_CAP_ASYM_PAUSE", PHYMOD_AN_CAP_ASYM_PAUSE }, 4244 { "PHYMOD_AN_CAP_HALF_DUPLEX", PHYMOD_AN_CAP_HALF_DUPLEX }, 4245 { "PHYMOD_AN_F_ALLOW_PLL_CHANGE", PHYMOD_AN_F_ALLOW_PLL_CHANGE }, 4246 { "PHYMOD_AN_F_SET_PRIOR_ENABLE", PHYMOD_AN_F_SET_PRIOR_ENABLE }, 4247 { "PHYMOD_AN_F_ALLOW_CL72_CONFIG_CHANGE", PHYMOD_AN_F_ALLOW_CL72_CONFIG_CHANGE }, 4248 { "PHYMOD_AN_F_IGNORE_MEDIUM_CHECK", PHYMOD_AN_F_IGNORE_MEDIUM_CHECK }, 4249 { "PHYMOD_AN_F_SET_CL73_PDET_KX_ENABLE", PHYMOD_AN_F_SET_CL73_PDET_KX_ENABLE }, 4250 { "PHYMOD_AN_F_SET_CL73_PDET_KX4_ENABLE", PHYMOD_AN_F_SET_CL73_PDET_KX4_ENABLE }, 4251 { "PHYMOD_AN_F_SET_CL73_PDET_2P5G_KX_ENABLE", PHYMOD_AN_F_SET_CL73_PDET_2P5G_KX_ENABLE }, 4252 { "PHYMOD_AN_F_AUTO_MEDIUM_DETECT", PHYMOD_AN_F_AUTO_MEDIUM_DETECT }, 4253 { "PHYMOD_AN_F_FEC_RS272_CLR", PHYMOD_AN_F_FEC_RS272_CLR }, 4254 { "PHYMOD_AN_F_SGMII_MASTER_MODE", PHYMOD_AN_F_SGMII_MASTER_MODE }, 4255 { "PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD", PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD }, 4256 { "PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD", PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD }, 4257 { "PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY", PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY }, 4258 { "PHYMOD_CORE_INIT_F_EXECUTE_PASS1", PHYMOD_CORE_INIT_F_EXECUTE_PASS1 }, 4259 { "PHYMOD_CORE_INIT_F_EXECUTE_PASS2", PHYMOD_CORE_INIT_F_EXECUTE_PASS2 }, 4260 { "PHYMOD_CORE_INIT_F_BYPASS_CRC_CHECK", PHYMOD_CORE_INIT_F_BYPASS_CRC_CHECK }, 4261 { "PHYMOD_CORE_INIT_F_FW_FORCE_DOWNLOAD", PHYMOD_CORE_INIT_F_FW_FORCE_DOWNLOAD }, 4262 { "PHYMOD_CORE_INIT_F_EXECUTE_FW_LOAD", PHYMOD_CORE_INIT_F_EXECUTE_FW_LOAD }, 4263 { "PHYMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD", PHYMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD }, 4264 { "PHYMOD_CORE_INIT_F_FW_LOAD_END", PHYMOD_CORE_INIT_F_FW_LOAD_END }, 4265 { "PHYMOD_CORE_INIT_F_FW_AUTO_DOWNLOAD", PHYMOD_CORE_INIT_F_FW_AUTO_DOWNLOAD }, 4266 { "PHYMOD_CORE_INIT_F_SERDES_FW_BCAST", PHYMOD_CORE_INIT_F_SERDES_FW_BCAST }, 4267 { "PHYMOD_CORE_INIT_F_CLK4PCS_3BIT_40T", PHYMOD_CORE_INIT_F_CLK4PCS_3BIT_40T }, 4268 { "PHYMOD_CORE_INIT_F_DEFAULT_OSR2P5", PHYMOD_CORE_INIT_F_DEFAULT_OSR2P5 }, 4269 { "PHYMOD_PHY_INIT_F_ENABLE_PASS_THROUGH_CONFIGURATION", PHYMOD_PHY_INIT_F_ENABLE_PASS_THROUGH_CONFIGURATION }, 4270 { "PHYMOD_INTR_TIMESYNC_FRAMESYNC", PHYMOD_INTR_TIMESYNC_FRAMESYNC }, 4271 { "PHYMOD_INTR_TIMESYNC_TIMESTAMP", PHYMOD_INTR_TIMESYNC_TIMESTAMP }, 4272 { "PHYMOD_INTR_LINK_EVENT", PHYMOD_INTR_LINK_EVENT }, 4273 { "PHYMOD_INTR_AUTONEG_EVENT", PHYMOD_INTR_AUTONEG_EVENT }, 4274 { "PHYMOD_INTR_PLL_EVENT", PHYMOD_INTR_PLL_EVENT }, 4275 { "PHYMOD_INTR_UC_EVENT", PHYMOD_INTR_UC_EVENT }, 4276 { "PHYMOD_INTR_EMON_EVENT", PHYMOD_INTR_EMON_EVENT }, 4277 { "PHYMOD_INTR_AUX_EVENT", PHYMOD_INTR_AUX_EVENT }, 4278 { "PHYMOD_TS_CAP_MPLS", PHYMOD_TS_CAP_MPLS }, 4279 { "PHYMOD_TS_CAP_ENHANCED_TSFIFO", PHYMOD_TS_CAP_ENHANCED_TSFIFO }, 4280 { "PHYMOD_TS_CAP_INBAND_TS", PHYMOD_TS_CAP_INBAND_TS }, 4281 { "PHYMOD_TS_CAP_FOLLOW_UP_ASSIST", PHYMOD_TS_CAP_FOLLOW_UP_ASSIST }, 4282 { "PHYMOD_TS_CAP_DELAY_RESP_ASSIST", PHYMOD_TS_CAP_DELAY_RESP_ASSIST }, 4283 { "PHYMOD_TS_CAP_CAPTURE_TIMESTAMP_MSG", PHYMOD_TS_CAP_CAPTURE_TIMESTAMP_MSG }, 4284 { "PHYMOD_TS_F_CAPTURE_TS_ENABLE", PHYMOD_TS_F_CAPTURE_TS_ENABLE }, 4285 { "PHYMOD_TS_F_HEARTBEAT_TS_ENABLE", PHYMOD_TS_F_HEARTBEAT_TS_ENABLE }, 4286 { "PHYMOD_TS_F_RX_CRC_ENABLE", PHYMOD_TS_F_RX_CRC_ENABLE }, 4287 { "PHYMOD_TS_F_8021AS_ENABLE", PHYMOD_TS_F_8021AS_ENABLE }, 4288 { "PHYMOD_TS_F_L2_ENABLE", PHYMOD_TS_F_L2_ENABLE }, 4289 { "PHYMOD_TS_F_IP4_ENABLE", PHYMOD_TS_F_IP4_ENABLE }, 4290 { "PHYMOD_TS_F_IP6_ENABLE", PHYMOD_TS_F_IP6_ENABLE }, 4291 { "PHYMOD_TS_F_CLOCK_SRC_EXT", PHYMOD_TS_F_CLOCK_SRC_EXT }, 4292 { "PHYMOD_TS_F_CLOCK_SRC_EXT_MODE", PHYMOD_TS_F_CLOCK_SRC_EXT_MODE }, 4293 { "PHYMOD_TS_F_1588_ENCRYPTED_MODE", PHYMOD_TS_F_1588_ENCRYPTED_MODE }, 4294 { "PHYMOD_TS_F_FOLLOW_UP_ASSIST_ENABLE", PHYMOD_TS_F_FOLLOW_UP_ASSIST_ENABLE }, 4295 { "PHYMOD_TS_F_DELAY_RESP_ASSIST_ENABLE", PHYMOD_TS_F_DELAY_RESP_ASSIST_ENABLE }, 4296 { "PHYMOD_TS_F_64BIT_TIMESTAMP_ENABLE", PHYMOD_TS_F_64BIT_TIMESTAMP_ENABLE }, 4297 { "PHYMOD_TS_F_1588_OVER_HSR_ENABLE", PHYMOD_TS_F_1588_OVER_HSR_ENABLE }, 4298 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_SYNC", PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_SYNC }, 4299 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_DELAY_REQ", PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_DELAY_REQ }, 4300 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_PDELAY_REQ", PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_PDELAY_REQ }, 4301 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_PDELAY_RESP", PHYMOD_TS_F_CAPTURE_TIMESTAMP_TX_PDELAY_RESP }, 4302 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_SYNC", PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_SYNC }, 4303 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_DELAY_REQ", PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_DELAY_REQ }, 4304 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_PDELAY_REQ", PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_PDELAY_REQ }, 4305 { "PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_PDELAY_RESP", PHYMOD_TS_F_CAPTURE_TIMESTAMP_RX_PDELAY_RESP }, 4306 { "PHYMOD_TS_LDCTL_TN_LOAD", PHYMOD_TS_LDCTL_TN_LOAD }, 4307 { "PHYMOD_TS_LDCTL_TIMECODE_LOAD", PHYMOD_TS_LDCTL_TIMECODE_LOAD }, 4308 { "PHYMOD_TS_LDCTL_SYNCOUT_LOAD", PHYMOD_TS_LDCTL_SYNCOUT_LOAD }, 4309 { "PHYMOD_TS_LDCTL_NCO_DIVIDER_LOAD", PHYMOD_TS_LDCTL_NCO_DIVIDER_LOAD }, 4310 { "PHYMOD_TS_LDCTL_LOCAL_TIME_LOAD", PHYMOD_TS_LDCTL_LOCAL_TIME_LOAD }, 4311 { "PHYMOD_TS_LDCTL_NCO_ADDEND_LOAD", PHYMOD_TS_LDCTL_NCO_ADDEND_LOAD }, 4312 { "PHYMOD_TS_LDCTL_DPLL_LOOP_FILTER_LOAD", PHYMOD_TS_LDCTL_DPLL_LOOP_FILTER_LOAD }, 4313 { "PHYMOD_TS_LDCTL_DPLL_REF_PHASE_LOAD", PHYMOD_TS_LDCTL_DPLL_REF_PHASE_LOAD }, 4314 { "PHYMOD_TS_LDCTL_DPLL_REF_PHASE_DELTA_LOAD", PHYMOD_TS_LDCTL_DPLL_REF_PHASE_DELTA_LOAD }, 4315 { "PHYMOD_TS_LDCTL_DPLL_K3_LOAD", PHYMOD_TS_LDCTL_DPLL_K3_LOAD }, 4316 { "PHYMOD_TS_LDCTL_DPLL_K2_LOAD", PHYMOD_TS_LDCTL_DPLL_K2_LOAD }, 4317 { "PHYMOD_TS_LDCTL_DPLL_K1_LOAD", PHYMOD_TS_LDCTL_DPLL_K1_LOAD }, 4318 { "PHYMOD_TS_MPLS_LABEL_F_IN", PHYMOD_TS_MPLS_LABEL_F_IN }, 4319 { "PHYMOD_TS_MPLS_LABEL_F_OUT", PHYMOD_TS_MPLS_LABEL_F_OUT }, 4320 { "PHYMOD_TS_MPLS_F_ENABLE", PHYMOD_TS_MPLS_F_ENABLE }, 4321 { "PHYMOD_TS_MPLS_F_ENTROPY_ENABLE", PHYMOD_TS_MPLS_F_ENTROPY_ENABLE }, 4322 { "PHYMOD_TS_MPLS_F_SPECIAL_LABEL_ENABLE", PHYMOD_TS_MPLS_F_SPECIAL_LABEL_ENABLE }, 4323 { "PHYMOD_TS_MPLS_F_CONTROL_WORD_ENABLE", PHYMOD_TS_MPLS_F_CONTROL_WORD_ENABLE }, 4324 { "PHYMOD_TIMESYNC_ENABLE_F_CORE", PHYMOD_TIMESYNC_ENABLE_F_CORE }, 4325 { "PHYMOD_TIMESYNC_ENABLE_F_RX", PHYMOD_TIMESYNC_ENABLE_F_RX }, 4326 { "PHYMOD_TIMESYNC_ENABLE_F_ONE_STEP_PIPELINE", PHYMOD_TIMESYNC_ENABLE_F_ONE_STEP_PIPELINE }, 4327 { "PHYMOD_SPEED_CONFIG_ONLY_PLL0_IS_ACTIVE", PHYMOD_SPEED_CONFIG_ONLY_PLL0_IS_ACTIVE }, 4328 { "PHYMOD_SPEED_CONFIG_REF_CLK_IS_156P25MHZ", PHYMOD_SPEED_CONFIG_REF_CLK_IS_156P25MHZ }, 4329 { NULL } 4330 }; 4331 4332 4333 /* Typedefs section */ 4334 static cint_parameter_desc_t __cint_typedefs[] = 4335 { 4336 { NULL } 4337 }; 4338 4339 4340 cint_data_t phymod_cint_data = 4341 { 4342 NULL, 4343 __cint_functions, 4344 __cint_structures, 4345 __cint_enums, 4346 __cint_typedefs, 4347 __cint_constants, 4348 __cint_function_pointers, 4349 }; 4350 4351 4352 #endif /* defined(PHYMOD_SUPPORT) */ 4353 4354 #endif /* defined(INCLUDE_LIB_CINT) */