cprimod_cint_data.c (215482B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 * 9 * 10 * DO NOT EDIT THIS FILE! 11 */ 12 13 #if defined(INCLUDE_LIB_CINT) 14 15 #include <cint_config.h> 16 #include <cint_types.h> 17 #include <cint_porting.h> 18 19 #if defined(CPRIMOD_SUPPORT) 20 21 #include <soc/cprimod/cprimod.h> 22 23 /* Macros section */ 24 25 /* Functions section */ 26 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 27 cprimod_test_api_non_dispatch, 28 int, int, unit, 0, 0, 29 int, int, port, 0, 0, 30 int*, int, value, 1, 0); 31 32 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 33 cprimod_test_api_dispatch, 34 int, int, unit, 0, 0, 35 int, int, port, 0, 0, 36 int*, int, value, 1, 0); 37 38 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 39 cprimod_basic_frame_parser_active_table_get, 40 int, int, unit, 0, 0, 41 int, int, port, 0, 0, 42 cprimod_basic_frame_table_id_t*, cprimod_basic_frame_table_id_t, table, 1, 0); 43 44 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 45 cprimod_basic_frame_parser_active_table_set, 46 int, int, unit, 0, 0, 47 int, int, port, 0, 0, 48 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 49 int, int, sync_enable, 0, 0); 50 51 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 52 cprimod_basic_frame_parser_table_num_entries_get, 53 int, int, unit, 0, 0, 54 int, int, port, 0, 0, 55 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 56 uint32*, uint32, num_entries, 1, 0); 57 58 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 59 cprimod_basic_frame_parser_table_num_entries_set, 60 int, int, unit, 0, 0, 61 int, int, port, 0, 0, 62 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 63 uint32, uint32, num_entries, 0, 0); 64 65 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 66 cprimod_basic_frame_assembly_active_table_get, 67 int, int, unit, 0, 0, 68 int, int, port, 0, 0, 69 cprimod_basic_frame_table_id_t*, cprimod_basic_frame_table_id_t, table, 1, 0); 70 71 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 72 cprimod_basic_frame_assembly_active_table_set, 73 int, int, unit, 0, 0, 74 int, int, port, 0, 0, 75 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 76 int, int, sync_enable, 0, 0); 77 78 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 79 cprimod_basic_frame_assembly_table_num_entries_get, 80 int, int, unit, 0, 0, 81 int, int, port, 0, 0, 82 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 83 uint32*, uint32, num_entries, 1, 0); 84 85 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 86 cprimod_basic_frame_assembly_table_num_entries_set, 87 int, int, unit, 0, 0, 88 int, int, port, 0, 0, 89 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 90 uint32, uint32, num_entries, 0, 0); 91 92 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 93 cprimod_basic_frame_parser_switch_active_table, 94 int, int, unit, 0, 0, 95 int, int, port, 0, 0); 96 97 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 98 cprimod_basic_frame_assembly_switch_active_table, 99 int, int, unit, 0, 0, 100 int, int, port, 0, 0); 101 102 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 103 cprimod_rx_axc_basic_frame_add, 104 int, int, unit, 0, 0, 105 int, int, port, 0, 0, 106 uint32, uint32, axc_id, 0, 0, 107 uint32, uint32, start_bit, 0, 0, 108 uint32, uint32, num_bit, 0, 0); 109 110 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 111 cprimod_rx_axc_basic_frame_delete, 112 int, int, unit, 0, 0, 113 int, int, port, 0, 0, 114 uint32, uint32, axc_id, 0, 0); 115 116 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 117 cprimod_rx_axc_basic_frame_clear, 118 int, int, unit, 0, 0, 119 int, int, port, 0, 0); 120 121 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 122 cprimod_rx_axc_basic_frame_get, 123 int, int, unit, 0, 0, 124 int, int, port, 0, 0, 125 uint32, uint32, axc_id, 0, 0, 126 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 127 cprimod_basic_frame_usage_entry_t*, cprimod_basic_frame_usage_entry_t, usage_table, 1, 0, 128 int*, int, num_entries, 1, 0); 129 130 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 131 cprimod_tx_axc_basic_frame_add, 132 int, int, unit, 0, 0, 133 int, int, port, 0, 0, 134 uint32, uint32, axc_id, 0, 0, 135 uint32, uint32, start_bit, 0, 0, 136 uint32, uint32, num_bit, 0, 0); 137 138 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 139 cprimod_tx_axc_basic_frame_delete, 140 int, int, unit, 0, 0, 141 int, int, port, 0, 0, 142 uint32, uint32, axc_id, 0, 0); 143 144 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 145 cprimod_tx_axc_basic_frame_clear, 146 int, int, unit, 0, 0, 147 int, int, port, 0, 0); 148 149 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 150 cprimod_tx_axc_basic_frame_get, 151 int, int, unit, 0, 0, 152 int, int, port, 0, 0, 153 uint32, uint32, axc_id, 0, 0, 154 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, table, 0, 0, 155 cprimod_basic_frame_usage_entry_t*, cprimod_basic_frame_usage_entry_t, usage_table, 1, 0, 156 int*, int, num_entries, 1, 0); 157 158 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 159 cprimod_basic_frame_debug, 160 int, int, unit, 0, 0, 161 int, int, port, 0, 0, 162 uint32, uint32, axc_id, 0, 0, 163 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, rx_table, 0, 0, 164 cprimod_basic_frame_table_id_t, cprimod_basic_frame_table_id_t, tx_table, 0, 0, 165 uint32, uint32, flags, 0, 0); 166 167 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 168 cprimod_cpri_rx_axc_container_config_get, 169 int, int, unit, 0, 0, 170 int, int, port, 0, 0, 171 uint32, uint32, axc_id, 0, 0, 172 cprimod_cpri_container_config_t*, cprimod_cpri_container_config_t, config_info, 1, 0); 173 174 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 175 cprimod_cpri_rx_axc_container_config_set, 176 int, int, unit, 0, 0, 177 int, int, port, 0, 0, 178 uint32, uint32, axc_id, 0, 0, 179 cprimod_cpri_container_config_t*, cprimod_cpri_container_config_t, config_info, 1, 0); 180 181 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 182 cprimod_cpri_tx_axc_container_config_get, 183 int, int, unit, 0, 0, 184 int, int, port, 0, 0, 185 uint32, uint32, axc_id, 0, 0, 186 cprimod_cpri_container_config_t*, cprimod_cpri_container_config_t, config_info, 1, 0); 187 188 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 189 cprimod_cpri_tx_axc_container_config_set, 190 int, int, unit, 0, 0, 191 int, int, port, 0, 0, 192 uint32, uint32, axc_id, 0, 0, 193 cprimod_cpri_container_config_t*, cprimod_cpri_container_config_t, config_info, 1, 0); 194 195 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 196 cprimod_rsvd4_rx_axc_container_config_get, 197 int, int, unit, 0, 0, 198 int, int, port, 0, 0, 199 uint32, uint32, flow_id, 0, 0, 200 cprimod_rsvd4_container_config_t*, cprimod_rsvd4_container_config_t, config_info, 1, 0); 201 202 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 203 cprimod_rsvd4_rx_axc_container_config_set, 204 int, int, unit, 0, 0, 205 int, int, port, 0, 0, 206 uint32, uint32, flow_id, 0, 0, 207 cprimod_rsvd4_container_config_t*, cprimod_rsvd4_container_config_t, config_info, 1, 0); 208 209 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 210 cprimod_rsvd4_tx_axc_container_config_get, 211 int, int, unit, 0, 0, 212 int, int, port, 0, 0, 213 uint32, uint32, flow_id, 0, 0, 214 cprimod_rsvd4_container_config_t*, cprimod_rsvd4_container_config_t, config_info, 1, 0); 215 216 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 217 cprimod_rsvd4_tx_axc_container_config_set, 218 int, int, unit, 0, 0, 219 int, int, port, 0, 0, 220 uint32, uint32, flow_id, 0, 0, 221 cprimod_rsvd4_container_config_t*, cprimod_rsvd4_container_config_t, config_info, 1, 0); 222 223 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 224 cprimod_rx_roe_payload_size_get, 225 int, int, unit, 0, 0, 226 int, int, port, 0, 0, 227 uint32, uint32, axc_id, 0, 0, 228 cprimod_payload_size_info_t*, cprimod_payload_size_info_t, config_info, 1, 0); 229 230 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 231 cprimod_rx_roe_payload_size_set, 232 int, int, unit, 0, 0, 233 int, int, port, 0, 0, 234 uint32, uint32, axc_id, 0, 0, 235 cprimod_payload_size_info_t*, cprimod_payload_size_info_t, config_info, 1, 0); 236 237 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 238 cprimod_tx_roe_payload_size_get, 239 int, int, unit, 0, 0, 240 int, int, port, 0, 0, 241 uint32, uint32, axc_id, 0, 0, 242 cprimod_payload_size_info_t*, cprimod_payload_size_info_t, config_info, 1, 0); 243 244 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 245 cprimod_tx_roe_payload_size_set, 246 int, int, unit, 0, 0, 247 int, int, port, 0, 0, 248 uint32, uint32, axc_id, 0, 0, 249 cprimod_payload_size_info_t*, cprimod_payload_size_info_t, config_info, 1, 0); 250 251 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 252 cprimod_cpri_encap_data_config_get, 253 int, int, unit, 0, 0, 254 int, int, port, 0, 0, 255 uint32, uint32, queue_num, 0, 0, 256 cprimod_encap_decap_data_config_t*, cprimod_encap_decap_data_config_t, config_info, 1, 0); 257 258 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 259 cprimod_cpri_encap_data_config_set, 260 int, int, unit, 0, 0, 261 int, int, port, 0, 0, 262 uint32, uint32, queue_num, 0, 0, 263 cprimod_encap_decap_data_config_t*, cprimod_encap_decap_data_config_t, config_info, 1, 0); 264 265 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 266 cprimod_cpri_decap_data_config_get, 267 int, int, unit, 0, 0, 268 int, int, port, 0, 0, 269 uint32, uint32, queue_num, 0, 0, 270 cprimod_encap_decap_data_config_t*, cprimod_encap_decap_data_config_t, config_info, 1, 0); 271 272 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 273 cprimod_cpri_decap_data_config_set, 274 int, int, unit, 0, 0, 275 int, int, port, 0, 0, 276 uint32, uint32, queue_num, 0, 0, 277 cprimod_encap_decap_data_config_t*, cprimod_encap_decap_data_config_t, config_info, 1, 0); 278 279 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 280 cprimod_rsvd4_encap_data_config_get, 281 int, int, unit, 0, 0, 282 int, int, port, 0, 0, 283 uint32, uint32, queue_num, 0, 0, 284 cprimod_rsvd4_encap_data_config_t*, cprimod_rsvd4_encap_data_config_t, config_info, 1, 0); 285 286 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 287 cprimod_rsvd4_encap_data_config_set, 288 int, int, unit, 0, 0, 289 int, int, port, 0, 0, 290 uint32, uint32, queue_num, 0, 0, 291 cprimod_rsvd4_encap_data_config_t*, cprimod_rsvd4_encap_data_config_t, config_info, 1, 0); 292 293 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 294 cprimod_rsvd4_decap_data_config_get, 295 int, int, unit, 0, 0, 296 int, int, port, 0, 0, 297 uint32, uint32, queue_num, 0, 0, 298 cprimod_rsvd4_decap_data_config_t*, cprimod_rsvd4_decap_data_config_t, config_info, 1, 0); 299 300 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 301 cprimod_rsvd4_decap_data_config_set, 302 int, int, unit, 0, 0, 303 int, int, port, 0, 0, 304 uint32, uint32, queue_num, 0, 0, 305 cprimod_rsvd4_decap_data_config_t*, cprimod_rsvd4_decap_data_config_t, config_info, 1, 0); 306 307 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 308 cprimod_encap_header_config_get, 309 int, int, unit, 0, 0, 310 int, int, port, 0, 0, 311 uint32, uint32, queue_num, 0, 0, 312 cprimod_encap_header_config_t*, cprimod_encap_header_config_t, config_info, 1, 0); 313 314 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 315 cprimod_encap_header_config_set, 316 int, int, unit, 0, 0, 317 int, int, port, 0, 0, 318 uint32, uint32, queue_num, 0, 0, 319 cprimod_encap_header_config_t*, cprimod_encap_header_config_t, config_info, 1, 0); 320 321 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 322 cprimod_rx_rsvd4_gsm_tsn_bitmap_get, 323 int, int, unit, 0, 0, 324 int, int, port, 0, 0, 325 uint32, uint32, queue_num, 0, 0, 326 uint32*, uint32, tsn_bitmap, 1, 0); 327 328 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 329 cprimod_rx_rsvd4_gsm_tsn_bitmap_set, 330 int, int, unit, 0, 0, 331 int, int, port, 0, 0, 332 uint32, uint32, queue_num, 0, 0, 333 uint32, uint32, tsn_bitmap, 0, 0); 334 335 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 336 cprimod_encap_ordering_info_entry_get, 337 int, int, unit, 0, 0, 338 int, int, port, 0, 0, 339 uint32, uint32, index, 0, 0, 340 cprimod_encap_ordering_info_entry_t*, cprimod_encap_ordering_info_entry_t, user_entry, 1, 0); 341 342 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 343 cprimod_encap_ordering_info_entry_set, 344 int, int, unit, 0, 0, 345 int, int, port, 0, 0, 346 uint32, uint32, index, 0, 0, 347 cprimod_encap_ordering_info_entry_t*, cprimod_encap_ordering_info_entry_t, user_entry, 1, 0); 348 349 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 350 cprimod_decap_ordering_info_entry_get, 351 int, int, unit, 0, 0, 352 int, int, port, 0, 0, 353 uint32, uint32, index, 0, 0, 354 cprimod_decap_ordering_info_entry_t*, cprimod_decap_ordering_info_entry_t, user_entry, 1, 0); 355 356 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 357 cprimod_decap_ordering_info_entry_set, 358 int, int, unit, 0, 0, 359 int, int, port, 0, 0, 360 uint32, uint32, index, 0, 0, 361 cprimod_decap_ordering_info_entry_t*, cprimod_decap_ordering_info_entry_t, user_entry, 1, 0); 362 363 CINT_FWRAPPER_CREATE_RP7(int, int, 0, 0, 364 cprimod_encap_ordering_info_sequence_offset_get, 365 int, int, unit, 0, 0, 366 int, int, port, 0, 0, 367 uint32, uint32, queue, 0, 0, 368 uint32, uint32, control, 0, 0, 369 uint32, uint32, pcnt_size, 0, 0, 370 uint32, uint32, qcnt_size, 0, 0, 371 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, offset_entry, 1, 0); 372 373 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 374 cprimod_encap_ordering_info_sequence_offset_set, 375 int, int, unit, 0, 0, 376 int, int, port, 0, 0, 377 uint32, uint32, queue, 0, 0, 378 uint32, uint32, control, 0, 0, 379 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, offset_entry, 1, 0); 380 381 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 382 cprimod_decap_ordering_info_sequence_offset_get, 383 int, int, unit, 0, 0, 384 int, int, port, 0, 0, 385 uint32, uint32, queue, 0, 0, 386 uint32, uint32, pcnt_size, 0, 0, 387 uint32, uint32, qcnt_size, 0, 0, 388 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, offset_entry, 1, 0); 389 390 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 391 cprimod_decap_ordering_info_sequence_offset_set, 392 int, int, unit, 0, 0, 393 int, int, port, 0, 0, 394 uint32, uint32, queue, 0, 0, 395 cprimod_cpri_ordering_info_offset_t*, cprimod_cpri_ordering_info_offset_t, offset_entry, 1, 0); 396 397 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 398 cprimod_encap_mac_da_entry_get, 399 int, int, unit, 0, 0, 400 int, int, port, 0, 0, 401 uint32, uint32, index, 0, 0, 402 cprimod_mac_addr_t, cprimod_mac_addr_t, addr, 0, 0); 403 404 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 405 cprimod_encap_mac_da_entry_set, 406 int, int, unit, 0, 0, 407 int, int, port, 0, 0, 408 uint32, uint32, index, 0, 0, 409 cprimod_mac_addr_t, cprimod_mac_addr_t, addr, 0, 0); 410 411 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 412 cprimod_encap_mac_sa_entry_get, 413 int, int, unit, 0, 0, 414 int, int, port, 0, 0, 415 uint32, uint32, index, 0, 0, 416 cprimod_mac_addr_t, cprimod_mac_addr_t, addr, 0, 0); 417 418 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 419 cprimod_encap_mac_sa_entry_set, 420 int, int, unit, 0, 0, 421 int, int, port, 0, 0, 422 uint32, uint32, index, 0, 0, 423 cprimod_mac_addr_t, cprimod_mac_addr_t, addr, 0, 0); 424 425 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 426 cprimod_encap_vlan_id_entry_get, 427 int, int, unit, 0, 0, 428 int, int, port, 0, 0, 429 cprimod_vlan_table_id_t, cprimod_vlan_table_id_t, table_id, 0, 0, 430 uint32, uint32, index, 0, 0, 431 uint32*, uint32, vlan_id, 1, 0); 432 433 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 434 cprimod_encap_vlan_id_entry_set, 435 int, int, unit, 0, 0, 436 int, int, port, 0, 0, 437 cprimod_vlan_table_id_t, cprimod_vlan_table_id_t, table_id, 0, 0, 438 uint32, uint32, index, 0, 0, 439 uint32, uint32, vlan_id, 0, 0); 440 441 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 442 cprimod_decap_ethertype_config_get, 443 int, int, unit, 0, 0, 444 int, int, port, 0, 0, 445 cprimod_ethertype_t, cprimod_ethertype_t, type_id, 0, 0, 446 uint16*, uint16, ethertype, 1, 0); 447 448 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 449 cprimod_decap_ethertype_config_set, 450 int, int, unit, 0, 0, 451 int, int, port, 0, 0, 452 cprimod_ethertype_t, cprimod_ethertype_t, type_id, 0, 0, 453 uint16, uint16, ethertype, 0, 0); 454 455 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 456 cprimod_encap_ethertype_config_get, 457 int, int, unit, 0, 0, 458 int, int, port, 0, 0, 459 cprimod_ethertype_t, cprimod_ethertype_t, type_id, 0, 0, 460 uint16*, uint16, ethertype, 1, 0); 461 462 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 463 cprimod_encap_ethertype_config_set, 464 int, int, unit, 0, 0, 465 int, int, port, 0, 0, 466 cprimod_ethertype_t, cprimod_ethertype_t, type_id, 0, 0, 467 uint16, uint16, ethertype, 0, 0); 468 469 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 470 cprimod_encap_memory_clear, 471 int, int, unit, 0, 0, 472 int, int, port, 0, 0, 473 int, int, queue_num, 0, 0); 474 475 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 476 cprimod_cpri_rx_framer_state_clear, 477 int, int, unit, 0, 0, 478 int, int, port, 0, 0, 479 int, int, queue_num, 0, 0); 480 481 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 482 cprimod_decap_memory_clear, 483 int, int, unit, 0, 0, 484 int, int, port, 0, 0, 485 int, int, queue_num, 0, 0); 486 487 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 488 cprimod_cpri_tx_framer_state_clear, 489 int, int, unit, 0, 0, 490 int, int, port, 0, 0, 491 int, int, queue_num, 0, 0); 492 493 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 494 cprimod_decap_flow_classification_config_get, 495 int, int, unit, 0, 0, 496 int, int, port, 0, 0, 497 uint8, uint8, subtype, 0, 0, 498 uint32*, uint32, queue_num, 1, 0, 499 cprimod_cls_option_t*, cprimod_cls_option_t, cls_option, 1, 0, 500 cprimod_cls_flow_type_t*, cprimod_cls_flow_type_t, flow_type, 1, 0); 501 502 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 503 cprimod_decap_flow_classification_config_set, 504 int, int, unit, 0, 0, 505 int, int, port, 0, 0, 506 uint8, uint8, subtype, 0, 0, 507 uint32, uint32, queue_num, 0, 0, 508 cprimod_cls_option_t, cprimod_cls_option_t, cls_option, 0, 0, 509 cprimod_cls_flow_type_t, cprimod_cls_flow_type_t, flow_type, 0, 0); 510 511 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 512 cprimod_decap_flow_to_queue_mapping_get, 513 int, int, unit, 0, 0, 514 int, int, port, 0, 0, 515 uint32, uint32, flow_id, 0, 0, 516 uint32*, uint32, queue_num, 1, 0); 517 518 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 519 cprimod_decap_flow_to_queue_mapping_set, 520 int, int, unit, 0, 0, 521 int, int, port, 0, 0, 522 uint32, uint32, flow_id, 0, 0, 523 uint32, uint32, queue_num, 0, 0); 524 525 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 526 cprimod_decap_queue_to_ordering_info_index_mapping_get, 527 int, int, unit, 0, 0, 528 int, int, port, 0, 0, 529 uint32, uint32, queue_num, 0, 0, 530 uint32*, uint32, ordering_info_index, 1, 0); 531 532 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 533 cprimod_decap_queue_to_ordering_info_index_mapping_set, 534 int, int, unit, 0, 0, 535 int, int, port, 0, 0, 536 uint32, uint32, queue_num, 0, 0, 537 uint32, uint32, ordering_info_index, 0, 0); 538 539 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 540 cprimod_tx_framer_tgen_tick_get, 541 int, int, unit, 0, 0, 542 int, int, port, 0, 0, 543 uint32*, uint32, divider, 1, 0, 544 uint32*, uint32, basic_frame_tick, 1, 0, 545 uint32*, uint32, tick_bitmap, 1, 0, 546 uint32*, uint32, tick_bitmap_size, 1, 0); 547 548 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 549 cprimod_tx_framer_tgen_tick_set, 550 int, int, unit, 0, 0, 551 int, int, port, 0, 0, 552 uint32, uint32, divider, 0, 0, 553 uint32, uint32, basic_frame_tick, 0, 0, 554 uint32, uint32, tick_bitmap, 0, 0, 555 uint32, uint32, tick_bitmap_size, 0, 0); 556 557 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 558 cprimod_tx_framer_tgen_enable, 559 int, int, unit, 0, 0, 560 int, int, port, 0, 0, 561 uint8, uint8, enable, 0, 0); 562 563 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 564 cprimod_tx_framer_tgen_offset_get, 565 int, int, unit, 0, 0, 566 int, int, port, 0, 0, 567 uint64*, uint64, timestamp_offset, 1, 0); 568 569 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 570 cprimod_tx_framer_tgen_offset_set, 571 int, int, unit, 0, 0, 572 int, int, port, 0, 0, 573 uint64, uint64, timestamp_offset, 0, 0); 574 575 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 576 cprimod_tx_framer_tgen_next_bfn_config_get, 577 int, int, unit, 0, 0, 578 int, int, port, 0, 0, 579 uint32*, uint32, tgen_bfn, 1, 0); 580 581 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 582 cprimod_tx_framer_tgen_next_bfn_config_set, 583 int, int, unit, 0, 0, 584 int, int, port, 0, 0, 585 uint32, uint32, tgen_bfn, 0, 0); 586 587 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 588 cprimod_tx_framer_tgen_next_hfn_config_get, 589 int, int, unit, 0, 0, 590 int, int, port, 0, 0, 591 uint32*, uint32, tgen_hfn, 1, 0); 592 593 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 594 cprimod_tx_framer_tgen_next_hfn_config_set, 595 int, int, unit, 0, 0, 596 int, int, port, 0, 0, 597 uint32, uint32, tgen_hfn, 0, 0); 598 599 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 600 cprimod_tx_framer_next_bfn_get, 601 int, int, unit, 0, 0, 602 int, int, port, 0, 0, 603 uint32*, uint32, tgen_bfn, 1, 0); 604 605 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 606 cprimod_tx_framer_next_hfn_get, 607 int, int, unit, 0, 0, 608 int, int, port, 0, 0, 609 uint32*, uint32, tgen_hfn, 1, 0); 610 611 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 612 cprimod_tx_framer_tgen_select_counter_get, 613 int, int, unit, 0, 0, 614 int, int, port, 0, 0, 615 cprimod_tgen_counter_select_t*, cprimod_tgen_counter_select_t, tgen_counter_select, 1, 0); 616 617 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 618 cprimod_tx_framer_tgen_select_counter_set, 619 int, int, unit, 0, 0, 620 int, int, port, 0, 0, 621 cprimod_tgen_counter_select_t, cprimod_tgen_counter_select_t, tgen_counter_select, 0, 0); 622 623 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 624 cprimod_header_compare_entry_add, 625 int, int, unit, 0, 0, 626 int, int, port, 0, 0, 627 cprimod_header_compare_entry_t*, cprimod_header_compare_entry_t, compare_entry, 1, 0); 628 629 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 630 cprimod_header_compare_entry_delete, 631 int, int, unit, 0, 0, 632 int, int, port, 0, 0, 633 cprimod_header_compare_entry_t*, cprimod_header_compare_entry_t, compare_entry, 1, 0); 634 635 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 636 cprimod_header_compare_entry_for_flow_delete, 637 int, int, unit, 0, 0, 638 int, int, port, 0, 0, 639 uint8, uint8, flow_id, 0, 0, 640 cprimod_flow_type_t, cprimod_flow_type_t, flow_type, 0, 0); 641 642 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 643 cprimod_modulo_rule_entry_get, 644 int, int, unit, 0, 0, 645 int, int, port, 0, 0, 646 uint8, uint8, modulo_rule_num, 0, 0, 647 cprimod_transmission_rule_type_t, cprimod_transmission_rule_type_t, modulo_rule_type, 0, 0, 648 cprimod_modulo_rule_entry_t*, cprimod_modulo_rule_entry_t, modulo_rule, 1, 0); 649 650 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 651 cprimod_modulo_rule_entry_set, 652 int, int, unit, 0, 0, 653 int, int, port, 0, 0, 654 uint8, uint8, modulo_rule_num, 0, 0, 655 cprimod_transmission_rule_type_t, cprimod_transmission_rule_type_t, modulo_rule_type, 0, 0, 656 cprimod_modulo_rule_entry_t*, cprimod_modulo_rule_entry_t, modulo_rule, 1, 0); 657 658 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 659 cprimod_dual_bitmap_rule_entry_get, 660 int, int, unit, 0, 0, 661 int, int, port, 0, 0, 662 uint8, uint8, dbm_rule_num, 0, 0, 663 cprimod_dbm_rule_entry_t*, cprimod_dbm_rule_entry_t, dbm_rule, 1, 0); 664 665 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 666 cprimod_dual_bitmap_rule_entry_set, 667 int, int, unit, 0, 0, 668 int, int, port, 0, 0, 669 uint8, uint8, dbm_rule_num, 0, 0, 670 cprimod_dbm_rule_entry_t*, cprimod_dbm_rule_entry_t, dbm_rule, 1, 0); 671 672 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 673 cprimod_secondary_dual_bitmap_rule_entry_get, 674 int, int, unit, 0, 0, 675 int, int, port, 0, 0, 676 uint8, uint8, dbm_rule_num, 0, 0, 677 cprimod_secondary_dbm_rule_entry_t*, cprimod_secondary_dbm_rule_entry_t, dbm_rule, 1, 0); 678 679 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 680 cprimod_secondary_dual_bitmap_rule_entry_set, 681 int, int, unit, 0, 0, 682 int, int, port, 0, 0, 683 uint8, uint8, dbm_rule_num, 0, 0, 684 cprimod_secondary_dbm_rule_entry_t*, cprimod_secondary_dbm_rule_entry_t, dbm_rule, 1, 0); 685 686 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 687 cprimod_dbm_position_entry_get, 688 int, int, unit, 0, 0, 689 int, int, port, 0, 0, 690 uint8, uint8, index, 0, 0, 691 cprimod_dbm_pos_table_entry_t*, cprimod_dbm_pos_table_entry_t, pos_entry, 1, 0); 692 693 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 694 cprimod_dbm_position_entry_set, 695 int, int, unit, 0, 0, 696 int, int, port, 0, 0, 697 uint8, uint8, index, 0, 0, 698 cprimod_dbm_pos_table_entry_t*, cprimod_dbm_pos_table_entry_t, pos_entry, 1, 0); 699 700 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 701 cprimod_port_rx_interface_config_get, 702 int, int, unit, 0, 0, 703 int, int, port, 0, 0, 704 cprimod_port_interface_config_t*, cprimod_port_interface_config_t, config, 1, 0); 705 706 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 707 cprimod_port_rx_interface_config_set, 708 int, int, unit, 0, 0, 709 int, int, port, 0, 0, 710 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 711 cprimod_port_interface_config_t*, cprimod_port_interface_config_t, config, 1, 0); 712 713 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 714 cprimod_port_tx_interface_config_get, 715 int, int, unit, 0, 0, 716 int, int, port, 0, 0, 717 cprimod_port_interface_config_t*, cprimod_port_interface_config_t, config, 1, 0); 718 719 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 720 cprimod_port_tx_interface_config_set, 721 int, int, unit, 0, 0, 722 int, int, port, 0, 0, 723 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 724 cprimod_port_interface_config_t*, cprimod_port_interface_config_t, config, 1, 0); 725 726 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 727 cprimod_port_rsvd4_rx_config_get, 728 int, int, unit, 0, 0, 729 int, int, port, 0, 0, 730 cprimod_port_rsvd4_config_t*, cprimod_port_rsvd4_config_t, config, 1, 0); 731 732 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 733 cprimod_port_rsvd4_rx_config_set, 734 int, int, unit, 0, 0, 735 int, int, port, 0, 0, 736 cprimod_port_rsvd4_config_t*, cprimod_port_rsvd4_config_t, config, 1, 0); 737 738 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 739 cprimod_port_rsvd4_tx_config_get, 740 int, int, unit, 0, 0, 741 int, int, port, 0, 0, 742 cprimod_port_rsvd4_config_t*, cprimod_port_rsvd4_config_t, config, 1, 0); 743 744 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 745 cprimod_port_rsvd4_tx_config_set, 746 int, int, unit, 0, 0, 747 int, int, port, 0, 0, 748 cprimod_port_rsvd4_config_t*, cprimod_port_rsvd4_config_t, config, 1, 0); 749 750 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 751 cprimod_port_rx_frame_optional_config_get, 752 int, int, unit, 0, 0, 753 int, int, port, 0, 0, 754 cprimod_rx_config_field_t, cprimod_rx_config_field_t, field, 0, 0, 755 int*, int, value, 1, 0); 756 757 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 758 cprimod_port_rx_frame_optional_config_set, 759 int, int, unit, 0, 0, 760 int, int, port, 0, 0, 761 cprimod_rx_config_field_t, cprimod_rx_config_field_t, field, 0, 0, 762 int, int, value, 0, 0); 763 764 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 765 cprimod_port_tx_frame_optional_config_get, 766 int, int, unit, 0, 0, 767 int, int, port, 0, 0, 768 cprimod_tx_config_field_t, cprimod_tx_config_field_t, field, 0, 0, 769 uint32*, uint32, value, 1, 0); 770 771 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 772 cprimod_port_tx_frame_optional_config_set, 773 int, int, unit, 0, 0, 774 int, int, port, 0, 0, 775 cprimod_tx_config_field_t, cprimod_tx_config_field_t, field, 0, 0, 776 uint32, uint32, value, 0, 0); 777 778 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 779 cprimod_port_rsvd4_rx_frame_optional_config_get, 780 int, int, unit, 0, 0, 781 int, int, port, 0, 0, 782 cprimod_rsvd4_rx_config_field_t, cprimod_rsvd4_rx_config_field_t, field, 0, 0, 783 int*, int, value, 1, 0); 784 785 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 786 cprimod_port_rsvd4_rx_frame_optional_config_set, 787 int, int, unit, 0, 0, 788 int, int, port, 0, 0, 789 cprimod_rsvd4_rx_config_field_t, cprimod_rsvd4_rx_config_field_t, field, 0, 0, 790 int, int, value, 0, 0); 791 792 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 793 cprimod_port_rsvd4_rx_speed_get, 794 int, int, unit, 0, 0, 795 int, int, port, 0, 0, 796 cprimod_port_rsvd4_speed_mult_t*, cprimod_port_rsvd4_speed_mult_t, speed, 1, 0); 797 798 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 799 cprimod_port_rsvd4_rx_speed_set, 800 int, int, unit, 0, 0, 801 int, int, port, 0, 0, 802 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 803 cprimod_port_rsvd4_speed_mult_t, cprimod_port_rsvd4_speed_mult_t, speed, 0, 0); 804 805 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 806 cprimod_port_rsvd4_tx_speed_get, 807 int, int, unit, 0, 0, 808 int, int, port, 0, 0, 809 cprimod_port_rsvd4_speed_mult_t*, cprimod_port_rsvd4_speed_mult_t, speed, 1, 0); 810 811 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 812 cprimod_port_rsvd4_tx_speed_set, 813 int, int, unit, 0, 0, 814 int, int, port, 0, 0, 815 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 816 cprimod_port_rsvd4_speed_mult_t, cprimod_port_rsvd4_speed_mult_t, speed, 0, 0); 817 818 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 819 cprimod_port_rsvd4_rx_fsm_state_get, 820 int, int, unit, 0, 0, 821 int, int, port, 0, 0, 822 cprimod_rsvd4_rx_fsm_state_t*, cprimod_rsvd4_rx_fsm_state_t, state, 1, 0); 823 824 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 825 cprimod_port_rsvd4_rx_fsm_state_set, 826 int, int, unit, 0, 0, 827 int, int, port, 0, 0, 828 cprimod_rsvd4_rx_fsm_state_t, cprimod_rsvd4_rx_fsm_state_t, state, 0, 0); 829 830 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 831 cprimod_port_rsvd4_rx_overide_get, 832 int, int, unit, 0, 0, 833 int, int, port, 0, 0, 834 cprimod_rsvd4_rx_overide_t, cprimod_rsvd4_rx_overide_t, parameter, 0, 0, 835 int*, int, enable, 1, 0, 836 int*, int, value, 1, 0); 837 838 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 839 cprimod_port_rsvd4_rx_overide_set, 840 int, int, unit, 0, 0, 841 int, int, port, 0, 0, 842 cprimod_rsvd4_rx_overide_t, cprimod_rsvd4_rx_overide_t, parameter, 0, 0, 843 int, int, enable, 0, 0, 844 int, int, value, 0, 0); 845 846 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 847 cprimod_port_rsvd4_tx_frame_optional_config_get, 848 int, int, unit, 0, 0, 849 int, int, port, 0, 0, 850 cprimod_rsvd4_tx_config_field_t, cprimod_rsvd4_tx_config_field_t, field, 0, 0, 851 int*, int, value, 1, 0); 852 853 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 854 cprimod_port_rsvd4_tx_frame_optional_config_set, 855 int, int, unit, 0, 0, 856 int, int, port, 0, 0, 857 cprimod_rsvd4_tx_config_field_t, cprimod_rsvd4_tx_config_field_t, field, 0, 0, 858 int, int, value, 0, 0); 859 860 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 861 cprimod_port_rsvd4_tx_fsm_state_get, 862 int, int, unit, 0, 0, 863 int, int, port, 0, 0, 864 cprimod_rsvd4_tx_fsm_state_t*, cprimod_rsvd4_tx_fsm_state_t, state, 1, 0); 865 866 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 867 cprimod_port_rsvd4_tx_fsm_state_set, 868 int, int, unit, 0, 0, 869 int, int, port, 0, 0, 870 cprimod_rsvd4_tx_fsm_state_t, cprimod_rsvd4_tx_fsm_state_t, state, 0, 0); 871 872 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 873 cprimod_port_rsvd4_tx_overide_get, 874 int, int, unit, 0, 0, 875 int, int, port, 0, 0, 876 cprimod_rsvd4_tx_overide_t, cprimod_rsvd4_tx_overide_t, parameter, 0, 0, 877 int*, int, enable, 1, 0, 878 int*, int, value, 1, 0); 879 880 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 881 cprimod_port_rsvd4_tx_overide_set, 882 int, int, unit, 0, 0, 883 int, int, port, 0, 0, 884 cprimod_rsvd4_tx_overide_t, cprimod_rsvd4_tx_overide_t, parameter, 0, 0, 885 int, int, enable, 0, 0, 886 int, int, value, 0, 0); 887 888 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 889 cprimod_port_rx_pcs_status_get, 890 int, int, unit, 0, 0, 891 int, int, port, 0, 0, 892 cprimod_rx_pcs_status_t, cprimod_rx_pcs_status_t, status, 0, 0, 893 uint32*, uint32, value, 1, 0); 894 895 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 896 cprimod_core_init, 897 int, int, unit, 0, 0, 898 int, int, port, 0, 0, 899 phymod_core_access_t*, phymod_core_access_t, phy, 1, 0, 900 phymod_core_init_config_t*, phymod_core_init_config_t, init_config, 1, 0, 901 phymod_core_status_t*, phymod_core_status_t, core_status, 1, 0); 902 903 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 904 cprimod_port_init, 905 int, int, unit, 0, 0, 906 int, int, port, 0, 0, 907 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 908 cprimod_port_init_config_t*, cprimod_port_init_config_t, port_config, 1, 0); 909 910 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 911 cprimod_rsvd4_rx_master_frame_sync_config_get, 912 int, int, unit, 0, 0, 913 int, int, port, 0, 0, 914 uint32*, uint32, master_frame_number, 1, 0, 915 uint64*, uint64, master_frame_start_time, 1, 0); 916 917 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 918 cprimod_rsvd4_rx_master_frame_sync_config_set, 919 int, int, unit, 0, 0, 920 int, int, port, 0, 0, 921 uint32, uint32, master_frame_number, 0, 0, 922 uint64, uint64, master_frame_start_time, 0, 0); 923 924 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 925 cprimod_cpri_rx_control_word_sync_info_get, 926 int, int, unit, 0, 0, 927 int, int, port, 0, 0, 928 uint32*, uint32, hyper_frame_num, 1, 0, 929 uint32*, uint32, radio_frame_num, 1, 0); 930 931 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 932 cprimod_cpri_rx_control_word_l1_signal_info_get, 933 int, int, unit, 0, 0, 934 int, int, port, 0, 0, 935 cprimod_cpri_cw_l1_protocol_info_t*, cprimod_cpri_cw_l1_protocol_info_t, l1_info, 1, 0); 936 937 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 938 cprimod_cpri_rx_control_word_l1_signal_signal_protection_get, 939 int, int, unit, 0, 0, 940 int, int, port, 0, 0, 941 uint32, uint32, signal_map, 0, 0, 942 uint32*, uint32, enable, 1, 0); 943 944 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 945 cprimod_cpri_rx_control_word_l1_signal_signal_protection_set, 946 int, int, unit, 0, 0, 947 int, int, port, 0, 0, 948 uint32, uint32, signal_map, 0, 0, 949 uint32, uint32, enable, 0, 0); 950 951 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 952 cprimod_cpri_port_cw_slow_hdlc_config_get, 953 int, int, unit, 0, 0, 954 int, int, port, 0, 0, 955 cprimod_slow_hdlc_config_info_t*, cprimod_slow_hdlc_config_info_t, config_info, 1, 0); 956 957 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 958 cprimod_cpri_port_cw_slow_hdlc_config_set, 959 int, int, unit, 0, 0, 960 int, int, port, 0, 0, 961 cprimod_slow_hdlc_config_info_t*, cprimod_slow_hdlc_config_info_t, config_info, 1, 0); 962 963 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 964 cprimod_cpri_port_cw_fast_eth_config_get, 965 int, int, unit, 0, 0, 966 int, int, port, 0, 0, 967 cprimod_fast_eth_config_info_t*, cprimod_fast_eth_config_info_t, config_info, 1, 0); 968 969 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 970 cprimod_cpri_port_cw_fast_eth_config_set, 971 int, int, unit, 0, 0, 972 int, int, port, 0, 0, 973 cprimod_fast_eth_config_info_t*, cprimod_fast_eth_config_info_t, config_info, 1, 0); 974 975 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 976 cprimod_cpri_port_rx_vsd_cw_config_get, 977 int, int, unit, 0, 0, 978 int, int, port, 0, 0, 979 cprimod_cpri_rx_vsd_config_info_t*, cprimod_cpri_rx_vsd_config_info_t, config_info, 1, 0); 980 981 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 982 cprimod_cpri_port_rx_vsd_cw_config_set, 983 int, int, unit, 0, 0, 984 int, int, port, 0, 0, 985 cprimod_cpri_rx_vsd_config_info_t*, cprimod_cpri_rx_vsd_config_info_t, config_info, 1, 0); 986 987 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 988 cprimod_cpri_port_rx_vsd_ctrl_flow_add, 989 int, int, unit, 0, 0, 990 int, int, port, 0, 0, 991 uint32, uint32, group_id, 0, 0, 992 cprimod_cpri_rx_vsd_flow_info_t*, cprimod_cpri_rx_vsd_flow_info_t, config_info, 1, 0); 993 994 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 995 cprimod_cpri_port_rx_vsd_ctrl_flow_delete, 996 int, int, unit, 0, 0, 997 int, int, port, 0, 0, 998 uint32, uint32, group_id, 0, 0); 999 1000 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1001 cprimod_cpri_port_rx_vsd_ctrl_flow_get, 1002 int, int, unit, 0, 0, 1003 int, int, port, 0, 0, 1004 uint32, uint32, group_id, 0, 0, 1005 cprimod_cpri_rx_vsd_flow_info_t*, cprimod_cpri_rx_vsd_flow_info_t, config_info, 1, 0); 1006 1007 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1008 cprimod_encap_control_queue_tag_to_flow_id_map_get, 1009 int, int, unit, 0, 0, 1010 int, int, port, 0, 0, 1011 uint32, uint32, tag_id, 0, 0, 1012 uint32*, uint32, flow_id, 1, 0); 1013 1014 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1015 cprimod_encap_control_queue_tag_to_flow_id_map_set, 1016 int, int, unit, 0, 0, 1017 int, int, port, 0, 0, 1018 uint32, uint32, tag_id, 0, 0, 1019 uint32, uint32, flow_id, 0, 0); 1020 1021 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1022 cprimod_cpri_port_tx_vsd_cw_config_get, 1023 int, int, unit, 0, 0, 1024 int, int, port, 0, 0, 1025 cprimod_cpri_tx_vsd_config_info_t*, cprimod_cpri_tx_vsd_config_info_t, config_info, 1, 0); 1026 1027 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1028 cprimod_cpri_port_tx_vsd_cw_config_set, 1029 int, int, unit, 0, 0, 1030 int, int, port, 0, 0, 1031 cprimod_cpri_tx_vsd_config_info_t*, cprimod_cpri_tx_vsd_config_info_t, config_info, 1, 0); 1032 1033 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1034 cprimod_cpri_port_tx_vsd_ctrl_flow_add, 1035 int, int, unit, 0, 0, 1036 int, int, port, 0, 0, 1037 uint32, uint32, group_id, 0, 0, 1038 uint32*, uint32, group_list, 1, 0, 1039 cprimod_cpri_tx_vsd_flow_info_t*, cprimod_cpri_tx_vsd_flow_info_t, config_info, 1, 0); 1040 1041 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1042 cprimod_cpri_port_tx_vsd_ctrl_flow_delete, 1043 int, int, unit, 0, 0, 1044 int, int, port, 0, 0, 1045 uint32, uint32, group_id, 0, 0, 1046 uint32*, uint32, group_list, 1, 0); 1047 1048 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1049 cprimod_cpri_port_tx_vsd_ctrl_flow_get, 1050 int, int, unit, 0, 0, 1051 int, int, port, 0, 0, 1052 uint32, uint32, group_id, 0, 0, 1053 uint32*, uint32, group_list, 1, 0, 1054 cprimod_cpri_tx_vsd_flow_info_t*, cprimod_cpri_tx_vsd_flow_info_t, config_info, 1, 0); 1055 1056 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1057 cprimod_cpri_port_rx_vsd_raw_config_get, 1058 int, int, unit, 0, 0, 1059 int, int, port, 0, 0, 1060 uint32, uint32, index, 0, 0, 1061 cprimod_cpri_rx_vsd_raw_config_t*, cprimod_cpri_rx_vsd_raw_config_t, config_info, 1, 0); 1062 1063 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1064 cprimod_cpri_port_rx_vsd_raw_config_set, 1065 int, int, unit, 0, 0, 1066 int, int, port, 0, 0, 1067 uint32, uint32, index, 0, 0, 1068 cprimod_cpri_rx_vsd_raw_config_t*, cprimod_cpri_rx_vsd_raw_config_t, config_info, 1, 0); 1069 1070 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1071 cprimod_cpri_port_tx_vsd_raw_config_get, 1072 int, int, unit, 0, 0, 1073 int, int, port, 0, 0, 1074 uint32, uint32, index, 0, 0, 1075 cprimod_cpri_tx_vsd_raw_config_t*, cprimod_cpri_tx_vsd_raw_config_t, config_info, 1, 0); 1076 1077 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1078 cprimod_cpri_port_tx_vsd_raw_config_set, 1079 int, int, unit, 0, 0, 1080 int, int, port, 0, 0, 1081 uint32, uint32, index, 0, 0, 1082 cprimod_cpri_tx_vsd_raw_config_t*, cprimod_cpri_tx_vsd_raw_config_t, config_info, 1, 0); 1083 1084 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1085 cprimod_cpri_port_tx_vsd_raw_filter_get, 1086 int, int, unit, 0, 0, 1087 int, int, port, 0, 0, 1088 uint32*, uint32, bfn0_value, 1, 0, 1089 uint32*, uint32, bfn0_mask, 1, 0, 1090 uint32*, uint32, bfn1_value, 1, 0, 1091 uint32*, uint32, bfn1_mask, 1, 0); 1092 1093 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1094 cprimod_cpri_port_tx_vsd_raw_filter_set, 1095 int, int, unit, 0, 0, 1096 int, int, port, 0, 0, 1097 uint32, uint32, bfn0_value, 0, 0, 1098 uint32, uint32, bfn0_mask, 0, 0, 1099 uint32, uint32, bfn1_value, 0, 0, 1100 uint32, uint32, bfn1_mask, 0, 0); 1101 1102 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1103 cprimod_cpri_port_rx_brcm_rsvd5_control_config_get, 1104 int, int, unit, 0, 0, 1105 int, int, port, 0, 0, 1106 uint32*, uint32, schan_start, 1, 0, 1107 uint32*, uint32, schan_size, 1, 0, 1108 uint32*, uint32, queue_num, 1, 0, 1109 int*, int, parity_disable, 1, 0); 1110 1111 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1112 cprimod_cpri_port_rx_brcm_rsvd5_control_config_set, 1113 int, int, unit, 0, 0, 1114 int, int, port, 0, 0, 1115 uint32, uint32, schan_start, 0, 0, 1116 uint32, uint32, schan_size, 0, 0, 1117 uint32, uint32, queue_num, 0, 0, 1118 int, int, parity_disable, 0, 0); 1119 1120 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1121 cprimod_cpri_port_tx_brcm_rsvd5_control_config_get, 1122 int, int, unit, 0, 0, 1123 int, int, port, 0, 0, 1124 uint32*, uint32, schan_start, 1, 0, 1125 uint32*, uint32, schan_size, 1, 0, 1126 uint32*, uint32, queue_num, 1, 0, 1127 int*, int, crc_enable, 1, 0); 1128 1129 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1130 cprimod_cpri_port_tx_brcm_rsvd5_control_config_set, 1131 int, int, unit, 0, 0, 1132 int, int, port, 0, 0, 1133 uint32, uint32, schan_start, 0, 0, 1134 uint32, uint32, schan_size, 0, 0, 1135 uint32, uint32, queue_num, 0, 0, 1136 int, int, crc_enable, 0, 0); 1137 1138 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1139 cprimod_cpri_port_rx_gcw_config_get, 1140 int, int, unit, 0, 0, 1141 int, int, port, 0, 0, 1142 uint32, uint32, index, 0, 0, 1143 cprimod_cpri_rx_gcw_config_t*, cprimod_cpri_rx_gcw_config_t, config_info, 1, 0); 1144 1145 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1146 cprimod_cpri_port_rx_gcw_config_set, 1147 int, int, unit, 0, 0, 1148 int, int, port, 0, 0, 1149 uint32, uint32, index, 0, 0, 1150 cprimod_cpri_rx_gcw_config_t*, cprimod_cpri_rx_gcw_config_t, config_info, 1, 0); 1151 1152 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1153 cprimod_cpri_port_tx_gcw_config_get, 1154 int, int, unit, 0, 0, 1155 int, int, port, 0, 0, 1156 uint32, uint32, index, 0, 0, 1157 cprimod_cpri_tx_gcw_config_t*, cprimod_cpri_tx_gcw_config_t, config_info, 1, 0); 1158 1159 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1160 cprimod_cpri_port_tx_gcw_config_set, 1161 int, int, unit, 0, 0, 1162 int, int, port, 0, 0, 1163 uint32, uint32, index, 0, 0, 1164 cprimod_cpri_tx_gcw_config_t*, cprimod_cpri_tx_gcw_config_t, config_info, 1, 0); 1165 1166 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1167 cprimod_cpri_port_tx_gcw_filter_get, 1168 int, int, unit, 0, 0, 1169 int, int, port, 0, 0, 1170 uint32*, uint32, bfn0_value, 1, 0, 1171 uint32*, uint32, bfn0_mask, 1, 0, 1172 uint32*, uint32, bfn1_value, 1, 0, 1173 uint32*, uint32, bfn1_mask, 1, 0); 1174 1175 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1176 cprimod_cpri_port_tx_gcw_filter_set, 1177 int, int, unit, 0, 0, 1178 int, int, port, 0, 0, 1179 uint32, uint32, bfn0_value, 0, 0, 1180 uint32, uint32, bfn0_mask, 0, 0, 1181 uint32, uint32, bfn1_value, 0, 0, 1182 uint32, uint32, bfn1_mask, 0, 0); 1183 1184 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1185 cprimod_cpri_port_tx_control_word_set, 1186 int, int, unit, 0, 0, 1187 int, int, port, 0, 0, 1188 cprimod_cpri_cw_l1_config_info_t*, cprimod_cpri_cw_l1_config_info_t, control_info, 1, 0); 1189 1190 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1191 cprimod_rsvd4_rx_control_message_config_set, 1192 int, int, unit, 0, 0, 1193 int, int, port, 0, 0, 1194 uint32, uint32, queue_num, 0, 0, 1195 uint32, uint32, default_tag, 0, 0, 1196 uint32, uint32, no_match_tag, 0, 0); 1197 1198 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1199 cprimod_rsvd4_rx_control_flow_config_get, 1200 int, int, unit, 0, 0, 1201 int, int, port, 0, 0, 1202 uint32, uint32, flow_id, 0, 0, 1203 cprimod_control_flow_config_t*, cprimod_control_flow_config_t, config, 1, 0); 1204 1205 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1206 cprimod_rsvd4_rx_control_flow_config_set, 1207 int, int, unit, 0, 0, 1208 int, int, port, 0, 0, 1209 uint32, uint32, flow_id, 0, 0, 1210 cprimod_control_flow_config_t*, cprimod_control_flow_config_t, config, 1, 0); 1211 1212 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1213 cprimod_rsvd4_rx_sync_profile_entry_get, 1214 int, int, unit, 0, 0, 1215 int, int, port, 0, 0, 1216 uint32, uint32, profile_id, 0, 0, 1217 cprimod_sync_profile_entry_t*, cprimod_sync_profile_entry_t, entry, 1, 0); 1218 1219 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1220 cprimod_rsvd4_rx_sync_profile_entry_set, 1221 int, int, unit, 0, 0, 1222 int, int, port, 0, 0, 1223 uint32, uint32, profile_id, 0, 0, 1224 cprimod_sync_profile_entry_t*, cprimod_sync_profile_entry_t, entry, 1, 0); 1225 1226 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1227 cprimod_rx_tag_config_set, 1228 int, int, unit, 0, 0, 1229 int, int, port, 0, 0, 1230 uint32, uint32, default_tag, 0, 0, 1231 uint32, uint32, no_match_tag, 0, 0); 1232 1233 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1234 cprimod_rx_tag_gen_entry_add, 1235 int, int, unit, 0, 0, 1236 int, int, port, 0, 0, 1237 cprimod_tag_gen_entry_t*, cprimod_tag_gen_entry_t, entry, 1, 0); 1238 1239 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1240 cprimod_rx_tag_gen_entry_delete, 1241 int, int, unit, 0, 0, 1242 int, int, port, 0, 0, 1243 cprimod_tag_gen_entry_t*, cprimod_tag_gen_entry_t, entry, 1, 0); 1244 1245 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1246 cprimod_rx_control_flow_tag_option_set, 1247 int, int, unit, 0, 0, 1248 int, int, port, 0, 0, 1249 uint32, uint32, flow_id, 0, 0, 1250 cprimod_cpri_tag_option_t, cprimod_cpri_tag_option_t, tag_option, 0, 0); 1251 1252 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1253 cprimod_rsvd4_tx_control_flow_group_member_add, 1254 int, int, unit, 0, 0, 1255 int, int, port, 0, 0, 1256 uint32, uint32, group_id, 0, 0, 1257 uint32, uint32, priority, 0, 0, 1258 uint32, uint32, queue_num, 0, 0, 1259 cprimod_control_msg_proc_type_t, cprimod_control_msg_proc_type_t, proc_type, 0, 0); 1260 1261 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1262 cprimod_rsvd4_tx_control_flow_group_member_delete, 1263 int, int, unit, 0, 0, 1264 int, int, port, 0, 0, 1265 uint32, uint32, group_id, 0, 0, 1266 uint32, uint32, priority, 0, 0); 1267 1268 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1269 cprimod_rsvd4_tx_eth_message_config_set, 1270 int, int, unit, 0, 0, 1271 int, int, port, 0, 0, 1272 uint32, uint32, msg_node, 0, 0, 1273 uint32, uint32, msg_subnode, 0, 0, 1274 uint32, uint32, msg_type, 0, 0, 1275 uint32, uint32, msg_padding, 0, 0); 1276 1277 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1278 cprimod_rsvd4_tx_single_raw_message_config_set, 1279 int, int, unit, 0, 0, 1280 int, int, port, 0, 0, 1281 uint32, uint32, msg_id, 0, 0, 1282 uint32, uint32, msg_type, 0, 0); 1283 1284 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1285 cprimod_rsvd4_tx_single_tunnel_message_config_set, 1286 int, int, unit, 0, 0, 1287 int, int, port, 0, 0, 1288 cprimod_cpri_crc_option_t, cprimod_cpri_crc_option_t, crc_option, 0, 0); 1289 1290 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1291 cprimod_rsvd4_tx_control_flow_config_get, 1292 int, int, unit, 0, 0, 1293 int, int, port, 0, 0, 1294 uint32, uint32, flow_id, 0, 0, 1295 cprimod_rsvd4_tx_config_info_t*, cprimod_rsvd4_tx_config_info_t, config_info, 1, 0); 1296 1297 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1298 cprimod_rsvd4_tx_control_flow_config_set, 1299 int, int, unit, 0, 0, 1300 int, int, port, 0, 0, 1301 uint32, uint32, flow_id, 0, 0, 1302 cprimod_rsvd4_tx_config_info_t*, cprimod_rsvd4_tx_config_info_t, config_info, 1, 0); 1303 1304 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1305 cprimod_rsvd4_tx_control_flow_header_index_get, 1306 int, int, unit, 0, 0, 1307 int, int, port, 0, 0, 1308 uint32, uint32, roe_flow_id, 0, 0, 1309 uint32*, uint32, index, 1, 0); 1310 1311 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1312 cprimod_rsvd4_tx_control_flow_header_index_set, 1313 int, int, unit, 0, 0, 1314 int, int, port, 0, 0, 1315 uint32, uint32, roe_flow_id, 0, 0, 1316 uint32, uint32, index, 0, 0); 1317 1318 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1319 cprimod_rsvd4_tx_control_header_entry_get, 1320 int, int, unit, 0, 0, 1321 int, int, port, 0, 0, 1322 uint32, uint32, index, 0, 0, 1323 uint32*, uint32, header_node, 1, 0, 1324 uint32*, uint32, header_subnode, 1, 0, 1325 uint32*, uint32, payload_node, 1, 0); 1326 1327 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1328 cprimod_rsvd4_tx_control_header_entry_set, 1329 int, int, unit, 0, 0, 1330 int, int, port, 0, 0, 1331 uint32, uint32, index, 0, 0, 1332 uint32, uint32, header_node, 0, 0, 1333 uint32, uint32, header_subnode, 0, 0, 1334 uint32, uint32, payload_node, 0, 0); 1335 1336 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1337 cprimod_rsvd4_fast_eth_config_set, 1338 int, int, unit, 0, 0, 1339 int, int, port, 0, 0, 1340 cprimod_cpri_fast_eth_config_t*, cprimod_cpri_fast_eth_config_t, config_info, 1, 0); 1341 1342 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1343 cprimod_cpri_or_enet_port_get, 1344 int, int, unit, 0, 0, 1345 int, int, port, 0, 0, 1346 int*, int, val, 1, 0); 1347 1348 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1349 cprimod_cpri_or_enet_port_set, 1350 int, int, unit, 0, 0, 1351 int, int, port, 0, 0, 1352 int, int, val, 0, 0); 1353 1354 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1355 cprimod_cpri_port_rx_enable_get, 1356 int, int, unit, 0, 0, 1357 int, int, port, 0, 0, 1358 int*, int, val, 1, 0); 1359 1360 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1361 cprimod_cpri_port_rx_enable_set, 1362 int, int, unit, 0, 0, 1363 int, int, port, 0, 0, 1364 int, int, val, 0, 0); 1365 1366 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1367 cprimod_cpri_port_tx_enable_get, 1368 int, int, unit, 0, 0, 1369 int, int, port, 0, 0, 1370 int*, int, val, 1, 0); 1371 1372 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1373 cprimod_cpri_port_tx_enable_set, 1374 int, int, unit, 0, 0, 1375 int, int, port, 0, 0, 1376 int, int, val, 0, 0); 1377 1378 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1379 cprimod_cpri_port_interrupt_link_status_get, 1380 int, int, unit, 0, 0, 1381 int, int, port, 0, 0, 1382 int*, int, is_link_intr_status, 1, 0); 1383 1384 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1385 cprimod_cpri_port_interrupt_callback_register, 1386 int, int, unit, 0, 0, 1387 cprimod_cpri_port_intr_type_t, cprimod_cpri_port_intr_type_t, cpri_intr_type, 0, 0, 1388 cprimod_cpri_port_interrupt_callback_t, cprimod_cpri_port_interrupt_callback_t, callback, 0, 0, 1389 void*, void, cb_data, 1, 0); 1390 1391 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1392 cprimod_cpri_port_interrupt_callback_unregister, 1393 int, int, unit, 0, 0, 1394 cprimod_cpri_port_intr_type_t, cprimod_cpri_port_intr_type_t, cpri_intr_type, 0, 0, 1395 cprimod_cpri_port_interrupt_callback_t, cprimod_cpri_port_interrupt_callback_t, callback, 0, 0); 1396 1397 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1398 cprimod_cpri_port_interrupt_enable_set, 1399 int, int, unit, 0, 0, 1400 int, int, port, 0, 0, 1401 cprimod_cpri_port_intr_type_t, cprimod_cpri_port_intr_type_t, cpri_intr_type, 0, 0, 1402 int, int, data, 0, 0, 1403 int, int, enable, 0, 0); 1404 1405 CINT_FWRAPPER_CREATE_RP1(int, int, 0, 0, 1406 cprimod_cpri_cpm_interrupt_data_init, 1407 int, int, unit, 0, 0); 1408 1409 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1410 cprimod_cpri_port_interrupt_process, 1411 int, int, unit, 0, 0, 1412 int, int, port, 0, 0); 1413 1414 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1415 cprimod_fast_clk_bit_time_period_get, 1416 int, int, unit, 0, 0, 1417 int, int, port, 0, 0, 1418 uint32*, uint32, bit_time_period, 1, 0); 1419 1420 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1421 cprimod_fast_clk_bit_time_period_set, 1422 int, int, unit, 0, 0, 1423 int, int, port, 0, 0, 1424 uint32, uint32, bit_time_period, 0, 0); 1425 1426 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1427 cprimod_1588_bit_time_period_get, 1428 int, int, unit, 0, 0, 1429 int, int, port, 0, 0, 1430 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1431 uint32*, uint32, bit_time_period, 1, 0); 1432 1433 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1434 cprimod_1588_bit_time_period_set, 1435 int, int, unit, 0, 0, 1436 int, int, port, 0, 0, 1437 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1438 cprimod_port_speed_t, cprimod_port_speed_t, speed, 0, 0); 1439 1440 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1441 cprimod_1588_timestamp_capture_config_get, 1442 int, int, unit, 0, 0, 1443 int, int, port, 0, 0, 1444 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1445 cprimod_1588_capture_config_t*, cprimod_1588_capture_config_t, config, 1, 0); 1446 1447 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1448 cprimod_1588_timestamp_capture_config_set, 1449 int, int, unit, 0, 0, 1450 int, int, port, 0, 0, 1451 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1452 cprimod_1588_capture_config_t*, cprimod_1588_capture_config_t, config, 1, 0); 1453 1454 CINT_FWRAPPER_CREATE_RP7(int, int, 0, 0, 1455 cprimod_1588_captured_timestamp_get, 1456 int, int, unit, 0, 0, 1457 int, int, port, 0, 0, 1458 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1459 uint8, uint8, fifo0_sw1, 0, 0, 1460 uint8, uint8, mx_cnt, 0, 0, 1461 uint8*, uint8, count, 1, 0, 1462 uint64*, uint64, captured_time, 1, 0); 1463 1464 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1465 cprimod_1588_timestamp_adjust_get, 1466 int, int, unit, 0, 0, 1467 int, int, port, 0, 0, 1468 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1469 cprimod_1588_time_t*, cprimod_1588_time_t, adjust_time, 1, 0); 1470 1471 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1472 cprimod_1588_timestamp_adjust_set, 1473 int, int, unit, 0, 0, 1474 int, int, port, 0, 0, 1475 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1476 cprimod_1588_time_t*, cprimod_1588_time_t, adjust_time, 1, 0); 1477 1478 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1479 cprimod_1588_timestamp_fifo_config_get, 1480 int, int, unit, 0, 0, 1481 int, int, port, 0, 0, 1482 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1483 uint16*, uint16, modulo, 1, 0); 1484 1485 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1486 cprimod_1588_timestamp_fifo_config_set, 1487 int, int, unit, 0, 0, 1488 int, int, port, 0, 0, 1489 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1490 uint16, uint16, modulo, 0, 0); 1491 1492 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1493 cprimod_1588_timestamp_cmic_config_get, 1494 int, int, unit, 0, 0, 1495 int, int, port, 0, 0, 1496 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1497 uint16*, uint16, modulo, 1, 0); 1498 1499 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1500 cprimod_1588_timestamp_cmic_config_set, 1501 int, int, unit, 0, 0, 1502 int, int, port, 0, 0, 1503 cprimod_direction_t, cprimod_direction_t, direction, 0, 0, 1504 uint16, uint16, modulo, 0, 0); 1505 1506 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1507 cprimod_cpri_basic_frame_info_get, 1508 int, int, unit, 0, 0, 1509 int, int, port, 0, 0, 1510 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1511 uint32*, uint32, frame_len_in_bits, 1, 0, 1512 uint32*, uint32, control_word_len_in_bits, 1, 0); 1513 1514 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1515 cprimod_cpri_agnostic_mode_basic_frame_config_set, 1516 int, int, unit, 0, 0, 1517 int, int, port, 0, 0, 1518 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1519 int, int, enable, 0, 0); 1520 1521 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1522 cprimod_cpri_interface_bus_width_get, 1523 int, int, unit, 0, 0, 1524 int, int, port, 0, 0, 1525 int*, int, is_10bit_mode, 1, 0); 1526 1527 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1528 cprimod_cpri_tunnel_mode_basic_frame_config_set, 1529 int, int, unit, 0, 0, 1530 int, int, port, 0, 0, 1531 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1532 int, int, enable, 0, 0); 1533 1534 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1535 cprimod_rsvd4_agnostic_mode_basic_frame_config_set, 1536 int, int, unit, 0, 0, 1537 int, int, port, 0, 0, 1538 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1539 int, int, enable, 0, 0); 1540 1541 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1542 cprimod_encap_presentation_time_enable_get, 1543 int, int, unit, 0, 0, 1544 int, int, port, 0, 0, 1545 int*, int, enable, 1, 0); 1546 1547 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1548 cprimod_encap_presentation_time_enable_set, 1549 int, int, unit, 0, 0, 1550 int, int, port, 0, 0, 1551 int, int, enable, 0, 0); 1552 1553 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1554 cprimod_encap_presentation_time_config_get, 1555 int, int, unit, 0, 0, 1556 int, int, port, 0, 0, 1557 cprimod_encap_presentation_time_config_t*, cprimod_encap_presentation_time_config_t, config, 1, 0); 1558 1559 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1560 cprimod_encap_presentation_time_config_set, 1561 int, int, unit, 0, 0, 1562 int, int, port, 0, 0, 1563 cprimod_encap_presentation_time_config_t*, cprimod_encap_presentation_time_config_t, config, 1, 0); 1564 1565 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1566 cprimod_encap_presentation_time_adjust_get, 1567 int, int, unit, 0, 0, 1568 int, int, port, 0, 0, 1569 uint32*, uint32, time, 1, 0); 1570 1571 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1572 cprimod_encap_presentation_time_adjust_set, 1573 int, int, unit, 0, 0, 1574 int, int, port, 0, 0, 1575 uint32, uint32, time, 0, 0); 1576 1577 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1578 cprimod_encap_presentation_time_approximate_increment_get, 1579 int, int, unit, 0, 0, 1580 int, int, port, 0, 0, 1581 uint32*, uint32, time, 1, 0); 1582 1583 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1584 cprimod_encap_presentation_time_approximate_increment_set, 1585 int, int, unit, 0, 0, 1586 int, int, port, 0, 0, 1587 uint32, uint32, time, 0, 0); 1588 1589 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1590 cprimod_decap_agnostic_mode_enable_get, 1591 int, int, unit, 0, 0, 1592 int, int, port, 0, 0, 1593 int*, int, enable, 1, 0, 1594 cprimod_cpri_roe_ordering_info_option_t*, cprimod_cpri_roe_ordering_info_option_t, mode, 1, 0); 1595 1596 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1597 cprimod_decap_agnostic_mode_enable_set, 1598 int, int, unit, 0, 0, 1599 int, int, port, 0, 0, 1600 int, int, enable, 0, 0, 1601 cprimod_cpri_roe_ordering_info_option_t, cprimod_cpri_roe_ordering_info_option_t, mode, 0, 0); 1602 1603 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1604 cprimod_decap_agnostic_mode_config_get, 1605 int, int, unit, 0, 0, 1606 int, int, port, 0, 0, 1607 cprimod_decap_agnostic_mode_config_t*, cprimod_decap_agnostic_mode_config_t, config, 1, 0); 1608 1609 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1610 cprimod_decap_agnostic_mode_config_set, 1611 int, int, unit, 0, 0, 1612 int, int, port, 0, 0, 1613 cprimod_decap_agnostic_mode_config_t*, cprimod_decap_agnostic_mode_config_t, config, 1, 0); 1614 1615 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1616 cprimod_decap_presentation_time_config_get, 1617 int, int, unit, 0, 0, 1618 int, int, port, 0, 0, 1619 uint32*, uint32, mod_offset, 1, 0, 1620 uint32*, uint32, mod_count, 1, 0); 1621 1622 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1623 cprimod_decap_presentation_time_config_set, 1624 int, int, unit, 0, 0, 1625 int, int, port, 0, 0, 1626 uint32, uint32, mod_offset, 0, 0, 1627 uint32, uint32, mod_count, 0, 0); 1628 1629 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1630 cprimod_compression_lookup_table_get, 1631 int, int, unit, 0, 0, 1632 int, int, port, 0, 0, 1633 int, int, max_depth, 0, 0, 1634 int*, int, table_depth, 1, 0, 1635 uint32*, uint32, table, 1, 0); 1636 1637 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1638 cprimod_compression_lookup_table_set, 1639 int, int, unit, 0, 0, 1640 int, int, port, 0, 0, 1641 int, int, table_depth, 0, 0, 1642 uint32*, uint32, table, 1, 0); 1643 1644 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1645 cprimod_decompression_lookup_table_get, 1646 int, int, unit, 0, 0, 1647 int, int, port, 0, 0, 1648 int, int, max_depth, 0, 0, 1649 int*, int, table_depth, 1, 0, 1650 uint32*, uint32, table, 1, 0); 1651 1652 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1653 cprimod_decompression_lookup_table_set, 1654 int, int, unit, 0, 0, 1655 int, int, port, 0, 0, 1656 int, int, table_depth, 0, 0, 1657 uint32*, uint32, table, 1, 0); 1658 1659 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1660 cprimod_cpri_port_decap_queue_flow_control_get, 1661 int, int, unit, 0, 0, 1662 int, int, port, 0, 0, 1663 uint32, uint32, queue_num, 0, 0, 1664 int*, int, enable, 1, 0, 1665 uint32_t*, uint32_t, xon_threshold, 1, 0, 1666 uint32_t*, uint32_t, xoff_threshold, 1, 0); 1667 1668 CINT_FWRAPPER_CREATE_RP6(int, int, 0, 0, 1669 cprimod_cpri_port_decap_queue_flow_control_set, 1670 int, int, unit, 0, 0, 1671 int, int, port, 0, 0, 1672 uint32, uint32, queue_num, 0, 0, 1673 int, int, enable, 0, 0, 1674 uint32_t, uint32_t, xon_threshold, 0, 0, 1675 uint32_t, uint32_t, xoff_threshold, 0, 0); 1676 1677 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1678 cprimod_cpri_port_fec_enable_get, 1679 int, int, unit, 0, 0, 1680 int, int, port, 0, 0, 1681 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1682 int*, int, enable, 1, 0); 1683 1684 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1685 cprimod_cpri_port_fec_enable_set, 1686 int, int, unit, 0, 0, 1687 int, int, port, 0, 0, 1688 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1689 int, int, enable, 0, 0); 1690 1691 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1692 cprimod_cpri_port_fec_timestamp_config_get, 1693 int, int, unit, 0, 0, 1694 int, int, port, 0, 0, 1695 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1696 cprimod_fec_timestamp_config_t*, cprimod_fec_timestamp_config_t, config, 1, 0); 1697 1698 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1699 cprimod_cpri_port_fec_timestamp_config_set, 1700 int, int, unit, 0, 0, 1701 int, int, port, 0, 0, 1702 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1703 cprimod_fec_timestamp_config_t*, cprimod_fec_timestamp_config_t, config, 1, 0); 1704 1705 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1706 cprimod_cpri_port_fec_aux_config_get, 1707 int, int, unit, 0, 0, 1708 int, int, port, 0, 0, 1709 cprimod_fec_aux_config_para_t, cprimod_fec_aux_config_para_t, parameter_id, 0, 0, 1710 uint32*, uint32, value, 1, 0); 1711 1712 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1713 cprimod_cpri_port_fec_aux_config_set, 1714 int, int, unit, 0, 0, 1715 int, int, port, 0, 0, 1716 cprimod_fec_aux_config_para_t, cprimod_fec_aux_config_para_t, parameter_id, 0, 0, 1717 uint32, uint32, value, 0, 0); 1718 1719 #ifdef CPRIMOD_SUPPORT 1720 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1721 cprimod_cpri_port_ecc_interrupt_enable_set, 1722 int, int, unit, 0, 0, 1723 int, int, port, 0, 0, 1724 int, int, enable, 0, 0); 1725 1726 #endif /* CPRIMOD_SUPPORT */ 1727 #ifdef CPRIMOD_SUPPORT 1728 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1729 cprimod_cpri_port_ecc_interrupt_status_get, 1730 int, int, unit, 0, 0, 1731 int, int, port, 0, 0, 1732 cprimod_cpri_ecc_intr_info_t*, cprimod_cpri_ecc_intr_info_t, ecc_err_info, 1, 0); 1733 1734 #endif /* CPRIMOD_SUPPORT */ 1735 #ifdef CPRIMOD_SUPPORT_ECC_INJECT 1736 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1737 cprimod_cpri_port_ecc_interrupt_test, 1738 int, int, unit, 0, 0, 1739 int, int, port, 0, 0); 1740 1741 #endif /* CPRIMOD_SUPPORT_ECC_INJECT */ 1742 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1743 cprimod_cpri_pll_status_get, 1744 int, int, unit, 0, 0, 1745 int, int, port, 0, 0, 1746 phymod_phy_access_t*, phymod_phy_access_t, phy, 1, 0, 1747 int*, int, pll_sel, 1, 0, 1748 int*, int, pll_lock, 1, 0); 1749 1750 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1751 cprimod_cpri_port_reset_get, 1752 int, int, unit, 0, 0, 1753 int, int, port, 0, 0, 1754 int*, int, rst, 1, 0); 1755 1756 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1757 cprimod_cpri_port_reset_set, 1758 int, int, unit, 0, 0, 1759 int, int, port, 0, 0, 1760 int, int, rst, 0, 0); 1761 1762 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1763 cprimod_cpri_init, 1764 int, int, unit, 0, 0, 1765 int, int, port, 0, 0); 1766 1767 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1768 cprimod_cpri_port_rx_gcw_word_get, 1769 int, int, unit, 0, 0, 1770 int, int, port, 0, 0, 1771 int, int, group_index, 0, 0, 1772 uint16*, uint16, gcw_word, 1, 0); 1773 1774 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1775 cprimod_cpri_port_tx_gcw_word_set, 1776 int, int, unit, 0, 0, 1777 int, int, port, 0, 0, 1778 int, int, group_index, 0, 0, 1779 uint16, uint16, gcw_word, 0, 0); 1780 1781 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1782 cprimod_cpri_mac_drain_start, 1783 int, int, unit, 0, 0, 1784 int, int, port, 0, 0); 1785 1786 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1787 cprimod_cpri_mac_drain_stop, 1788 int, int, unit, 0, 0, 1789 int, int, port, 0, 0); 1790 1791 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1792 cprimod_cpri_mac_credit_reset_get, 1793 int, int, unit, 0, 0, 1794 int, int, port, 0, 0, 1795 int*, int, rst, 1, 0); 1796 1797 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1798 cprimod_cpri_mac_credit_reset_set, 1799 int, int, unit, 0, 0, 1800 int, int, port, 0, 0, 1801 int, int, rst, 0, 0); 1802 1803 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1804 cprimod_cpri_port_link_up_event, 1805 int, int, unit, 0, 0, 1806 int, int, port, 0, 0); 1807 1808 CINT_FWRAPPER_CREATE_RP2(int, int, 0, 0, 1809 cprimod_cpri_port_link_down_event, 1810 int, int, unit, 0, 0, 1811 int, int, port, 0, 0); 1812 1813 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1814 cprimod_cpri_port_rx_tunnel_mode_get, 1815 int, int, unit, 0, 0, 1816 int, int, port, 0, 0, 1817 int*, int, enable, 1, 0, 1818 uint32*, uint32, payload_size, 1, 0); 1819 1820 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1821 cprimod_cpri_port_rx_tunnel_mode_set, 1822 int, int, unit, 0, 0, 1823 int, int, port, 0, 0, 1824 int, int, enable, 0, 0, 1825 uint32, uint32, payload_size, 0, 0); 1826 1827 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1828 cprimod_cpri_port_tx_agnostic_mode_get, 1829 int, int, unit, 0, 0, 1830 int, int, port, 0, 0, 1831 int*, int, enable, 1, 0, 1832 cprimod_agnostic_mode_type_t*, cprimod_agnostic_mode_type_t, mode, 1, 0, 1833 uint32*, uint32, payload_size, 1, 0); 1834 1835 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1836 cprimod_cpri_port_tx_agnostic_mode_set, 1837 int, int, unit, 0, 0, 1838 int, int, port, 0, 0, 1839 int, int, enable, 0, 0, 1840 cprimod_agnostic_mode_type_t, cprimod_agnostic_mode_type_t, mode, 0, 0, 1841 uint32, uint32, payload_size, 0, 0); 1842 1843 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1844 cprimod_cpri_port_rx_agnostic_mode_get, 1845 int, int, unit, 0, 0, 1846 int, int, port, 0, 0, 1847 int*, int, enable, 1, 0, 1848 cprimod_agnostic_mode_type_t*, cprimod_agnostic_mode_type_t, mode, 1, 0); 1849 1850 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1851 cprimod_port_pmd_status_get, 1852 int, int, unit, 0, 0, 1853 int, int, port, 0, 0, 1854 cprimod_pmd_port_status_t, cprimod_pmd_port_status_t, status, 0, 0, 1855 uint32*, uint32, value, 1, 0); 1856 1857 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1858 cprimod_cpri_port_link_get, 1859 int, int, unit, 0, 0, 1860 int, int, port, 0, 0, 1861 int*, int, link, 1, 0); 1862 1863 #ifdef CPRIMOD_SUPPORT 1864 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1865 cprimod_cpri_encap_header_field_mapping_get, 1866 int, int, unit, 0, 0, 1867 int, int, port, 0, 0, 1868 cprimod_cpri_encap_header_field_mapping_t*, cprimod_cpri_encap_header_field_mapping_t, mapping, 1, 0); 1869 1870 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1871 cprimod_cpri_encap_header_field_mapping_set, 1872 int, int, unit, 0, 0, 1873 int, int, port, 0, 0, 1874 cprimod_cpri_encap_header_field_mapping_t*, cprimod_cpri_encap_header_field_mapping_t, mapping, 1, 0); 1875 1876 #endif /* CPRIMOD_SUPPORT */ 1877 #ifdef CPRIMOD_SUPPORT 1878 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1879 cprimod_cpri_decap_header_field_mapping_get, 1880 int, int, unit, 0, 0, 1881 int, int, port, 0, 0, 1882 cprimod_cpri_decap_header_field_mapping_t*, cprimod_cpri_decap_header_field_mapping_t, mapping, 1, 0); 1883 1884 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1885 cprimod_cpri_decap_header_field_mapping_set, 1886 int, int, unit, 0, 0, 1887 int, int, port, 0, 0, 1888 cprimod_cpri_decap_header_field_mapping_t*, cprimod_cpri_decap_header_field_mapping_t, mapping, 1, 0); 1889 1890 #endif /* CPRIMOD_SUPPORT */ 1891 #ifdef CPRIMOD_SUPPORT 1892 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1893 cprimod_cpri_header_field_adjustment_config_get, 1894 int, int, unit, 0, 0, 1895 int, int, port, 0, 0, 1896 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1897 int*, int, ext_hdr_enable, 1, 0, 1898 int*, int, len_field_adj, 1, 0); 1899 1900 CINT_FWRAPPER_CREATE_RP5(int, int, 0, 0, 1901 cprimod_cpri_header_field_adjustment_config_set, 1902 int, int, unit, 0, 0, 1903 int, int, port, 0, 0, 1904 cprimod_direction_t, cprimod_direction_t, dir, 0, 0, 1905 int, int, ext_hdr_enable, 0, 0, 1906 int, int, len_field_adj, 0, 0); 1907 1908 #endif /* CPRIMOD_SUPPORT */ 1909 #ifdef CPRIMOD_SUPPORT 1910 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1911 cprimod_cpri_decap_header_field_mask_get, 1912 int, int, unit, 0, 0, 1913 int, int, port, 0, 0, 1914 cprimod_cpri_roe_header_field_t, cprimod_cpri_roe_header_field_t, field_id, 0, 0, 1915 uint32*, uint32, mask, 1, 0); 1916 1917 CINT_FWRAPPER_CREATE_RP4(int, int, 0, 0, 1918 cprimod_cpri_decap_header_field_mask_set, 1919 int, int, unit, 0, 0, 1920 int, int, port, 0, 0, 1921 cprimod_cpri_roe_header_field_t, cprimod_cpri_roe_header_field_t, field_id, 0, 0, 1922 uint32, uint32, mask, 0, 0); 1923 1924 #endif /* CPRIMOD_SUPPORT */ 1925 #ifdef CPRIMOD_SUPPORT 1926 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1927 cprimod_cpri_port_compression_saturation_config_get, 1928 int, int, unit, 0, 0, 1929 int, int, port, 0, 0, 1930 uint32*, uint32, threshold_value, 1, 0); 1931 1932 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1933 cprimod_cpri_port_compression_saturation_config_set, 1934 int, int, unit, 0, 0, 1935 int, int, port, 0, 0, 1936 uint32, uint32, threshold_value, 0, 0); 1937 1938 #endif /* CPRIMOD_SUPPORT */ 1939 #ifdef CPRIMOD_SUPPORT 1940 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1941 cprimod_cpri_port_decompression_saturation_config_get, 1942 int, int, unit, 0, 0, 1943 int, int, port, 0, 0, 1944 uint32*, uint32, sat_value, 1, 0); 1945 1946 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1947 cprimod_cpri_port_decompression_saturation_config_set, 1948 int, int, unit, 0, 0, 1949 int, int, port, 0, 0, 1950 uint32, uint32, sat_value, 0, 0); 1951 1952 #endif /* CPRIMOD_SUPPORT */ 1953 #ifdef CPRIMOD_SUPPORT 1954 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1955 cprimod_rsvd4_tx_padding_size_get, 1956 int, int, unit, 0, 0, 1957 int, int, port, 0, 0, 1958 uint32*, uint32, padding_size, 1, 0); 1959 1960 CINT_FWRAPPER_CREATE_RP3(int, int, 0, 0, 1961 cprimod_rsvd4_tx_padding_size_set, 1962 int, int, unit, 0, 0, 1963 int, int, port, 0, 0, 1964 uint32, uint32, padding_size, 0, 0); 1965 1966 #endif /* CPRIMOD_SUPPORT */ 1967 1968 /* Functions and Macros mapping */ 1969 static cint_function_t __cint_functions[] = 1970 { 1971 CINT_FWRAPPER_ENTRY(cprimod_test_api_non_dispatch), 1972 CINT_FWRAPPER_ENTRY(cprimod_test_api_dispatch), 1973 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_parser_active_table_get), 1974 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_parser_active_table_set), 1975 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_parser_table_num_entries_get), 1976 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_parser_table_num_entries_set), 1977 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_assembly_active_table_get), 1978 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_assembly_active_table_set), 1979 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_assembly_table_num_entries_get), 1980 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_assembly_table_num_entries_set), 1981 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_parser_switch_active_table), 1982 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_assembly_switch_active_table), 1983 CINT_FWRAPPER_ENTRY(cprimod_rx_axc_basic_frame_add), 1984 CINT_FWRAPPER_ENTRY(cprimod_rx_axc_basic_frame_delete), 1985 CINT_FWRAPPER_ENTRY(cprimod_rx_axc_basic_frame_clear), 1986 CINT_FWRAPPER_ENTRY(cprimod_rx_axc_basic_frame_get), 1987 CINT_FWRAPPER_ENTRY(cprimod_tx_axc_basic_frame_add), 1988 CINT_FWRAPPER_ENTRY(cprimod_tx_axc_basic_frame_delete), 1989 CINT_FWRAPPER_ENTRY(cprimod_tx_axc_basic_frame_clear), 1990 CINT_FWRAPPER_ENTRY(cprimod_tx_axc_basic_frame_get), 1991 CINT_FWRAPPER_ENTRY(cprimod_basic_frame_debug), 1992 CINT_FWRAPPER_ENTRY(cprimod_cpri_rx_axc_container_config_get), 1993 CINT_FWRAPPER_ENTRY(cprimod_cpri_rx_axc_container_config_set), 1994 CINT_FWRAPPER_ENTRY(cprimod_cpri_tx_axc_container_config_get), 1995 CINT_FWRAPPER_ENTRY(cprimod_cpri_tx_axc_container_config_set), 1996 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_axc_container_config_get), 1997 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_axc_container_config_set), 1998 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_axc_container_config_get), 1999 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_axc_container_config_set), 2000 CINT_FWRAPPER_ENTRY(cprimod_rx_roe_payload_size_get), 2001 CINT_FWRAPPER_ENTRY(cprimod_rx_roe_payload_size_set), 2002 CINT_FWRAPPER_ENTRY(cprimod_tx_roe_payload_size_get), 2003 CINT_FWRAPPER_ENTRY(cprimod_tx_roe_payload_size_set), 2004 CINT_FWRAPPER_ENTRY(cprimod_cpri_encap_data_config_get), 2005 CINT_FWRAPPER_ENTRY(cprimod_cpri_encap_data_config_set), 2006 CINT_FWRAPPER_ENTRY(cprimod_cpri_decap_data_config_get), 2007 CINT_FWRAPPER_ENTRY(cprimod_cpri_decap_data_config_set), 2008 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_encap_data_config_get), 2009 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_encap_data_config_set), 2010 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_decap_data_config_get), 2011 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_decap_data_config_set), 2012 CINT_FWRAPPER_ENTRY(cprimod_encap_header_config_get), 2013 CINT_FWRAPPER_ENTRY(cprimod_encap_header_config_set), 2014 CINT_FWRAPPER_ENTRY(cprimod_rx_rsvd4_gsm_tsn_bitmap_get), 2015 CINT_FWRAPPER_ENTRY(cprimod_rx_rsvd4_gsm_tsn_bitmap_set), 2016 CINT_FWRAPPER_ENTRY(cprimod_encap_ordering_info_entry_get), 2017 CINT_FWRAPPER_ENTRY(cprimod_encap_ordering_info_entry_set), 2018 CINT_FWRAPPER_ENTRY(cprimod_decap_ordering_info_entry_get), 2019 CINT_FWRAPPER_ENTRY(cprimod_decap_ordering_info_entry_set), 2020 CINT_FWRAPPER_ENTRY(cprimod_encap_ordering_info_sequence_offset_get), 2021 CINT_FWRAPPER_ENTRY(cprimod_encap_ordering_info_sequence_offset_set), 2022 CINT_FWRAPPER_ENTRY(cprimod_decap_ordering_info_sequence_offset_get), 2023 CINT_FWRAPPER_ENTRY(cprimod_decap_ordering_info_sequence_offset_set), 2024 CINT_FWRAPPER_ENTRY(cprimod_encap_mac_da_entry_get), 2025 CINT_FWRAPPER_ENTRY(cprimod_encap_mac_da_entry_set), 2026 CINT_FWRAPPER_ENTRY(cprimod_encap_mac_sa_entry_get), 2027 CINT_FWRAPPER_ENTRY(cprimod_encap_mac_sa_entry_set), 2028 CINT_FWRAPPER_ENTRY(cprimod_encap_vlan_id_entry_get), 2029 CINT_FWRAPPER_ENTRY(cprimod_encap_vlan_id_entry_set), 2030 CINT_FWRAPPER_ENTRY(cprimod_decap_ethertype_config_get), 2031 CINT_FWRAPPER_ENTRY(cprimod_decap_ethertype_config_set), 2032 CINT_FWRAPPER_ENTRY(cprimod_encap_ethertype_config_get), 2033 CINT_FWRAPPER_ENTRY(cprimod_encap_ethertype_config_set), 2034 CINT_FWRAPPER_ENTRY(cprimod_encap_memory_clear), 2035 CINT_FWRAPPER_ENTRY(cprimod_cpri_rx_framer_state_clear), 2036 CINT_FWRAPPER_ENTRY(cprimod_decap_memory_clear), 2037 CINT_FWRAPPER_ENTRY(cprimod_cpri_tx_framer_state_clear), 2038 CINT_FWRAPPER_ENTRY(cprimod_decap_flow_classification_config_get), 2039 CINT_FWRAPPER_ENTRY(cprimod_decap_flow_classification_config_set), 2040 CINT_FWRAPPER_ENTRY(cprimod_decap_flow_to_queue_mapping_get), 2041 CINT_FWRAPPER_ENTRY(cprimod_decap_flow_to_queue_mapping_set), 2042 CINT_FWRAPPER_ENTRY(cprimod_decap_queue_to_ordering_info_index_mapping_get), 2043 CINT_FWRAPPER_ENTRY(cprimod_decap_queue_to_ordering_info_index_mapping_set), 2044 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_tick_get), 2045 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_tick_set), 2046 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_enable), 2047 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_offset_get), 2048 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_offset_set), 2049 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_next_bfn_config_get), 2050 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_next_bfn_config_set), 2051 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_next_hfn_config_get), 2052 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_next_hfn_config_set), 2053 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_next_bfn_get), 2054 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_next_hfn_get), 2055 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_select_counter_get), 2056 CINT_FWRAPPER_ENTRY(cprimod_tx_framer_tgen_select_counter_set), 2057 CINT_FWRAPPER_ENTRY(cprimod_header_compare_entry_add), 2058 CINT_FWRAPPER_ENTRY(cprimod_header_compare_entry_delete), 2059 CINT_FWRAPPER_ENTRY(cprimod_header_compare_entry_for_flow_delete), 2060 CINT_FWRAPPER_ENTRY(cprimod_modulo_rule_entry_get), 2061 CINT_FWRAPPER_ENTRY(cprimod_modulo_rule_entry_set), 2062 CINT_FWRAPPER_ENTRY(cprimod_dual_bitmap_rule_entry_get), 2063 CINT_FWRAPPER_ENTRY(cprimod_dual_bitmap_rule_entry_set), 2064 CINT_FWRAPPER_ENTRY(cprimod_secondary_dual_bitmap_rule_entry_get), 2065 CINT_FWRAPPER_ENTRY(cprimod_secondary_dual_bitmap_rule_entry_set), 2066 CINT_FWRAPPER_ENTRY(cprimod_dbm_position_entry_get), 2067 CINT_FWRAPPER_ENTRY(cprimod_dbm_position_entry_set), 2068 CINT_FWRAPPER_ENTRY(cprimod_port_rx_interface_config_get), 2069 CINT_FWRAPPER_ENTRY(cprimod_port_rx_interface_config_set), 2070 CINT_FWRAPPER_ENTRY(cprimod_port_tx_interface_config_get), 2071 CINT_FWRAPPER_ENTRY(cprimod_port_tx_interface_config_set), 2072 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_config_get), 2073 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_config_set), 2074 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_config_get), 2075 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_config_set), 2076 CINT_FWRAPPER_ENTRY(cprimod_port_rx_frame_optional_config_get), 2077 CINT_FWRAPPER_ENTRY(cprimod_port_rx_frame_optional_config_set), 2078 CINT_FWRAPPER_ENTRY(cprimod_port_tx_frame_optional_config_get), 2079 CINT_FWRAPPER_ENTRY(cprimod_port_tx_frame_optional_config_set), 2080 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_frame_optional_config_get), 2081 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_frame_optional_config_set), 2082 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_speed_get), 2083 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_speed_set), 2084 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_speed_get), 2085 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_speed_set), 2086 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_fsm_state_get), 2087 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_fsm_state_set), 2088 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_overide_get), 2089 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_rx_overide_set), 2090 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_frame_optional_config_get), 2091 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_frame_optional_config_set), 2092 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_fsm_state_get), 2093 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_fsm_state_set), 2094 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_overide_get), 2095 CINT_FWRAPPER_ENTRY(cprimod_port_rsvd4_tx_overide_set), 2096 CINT_FWRAPPER_ENTRY(cprimod_port_rx_pcs_status_get), 2097 CINT_FWRAPPER_ENTRY(cprimod_core_init), 2098 CINT_FWRAPPER_ENTRY(cprimod_port_init), 2099 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_master_frame_sync_config_get), 2100 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_master_frame_sync_config_set), 2101 CINT_FWRAPPER_ENTRY(cprimod_cpri_rx_control_word_sync_info_get), 2102 CINT_FWRAPPER_ENTRY(cprimod_cpri_rx_control_word_l1_signal_info_get), 2103 CINT_FWRAPPER_ENTRY(cprimod_cpri_rx_control_word_l1_signal_signal_protection_get), 2104 CINT_FWRAPPER_ENTRY(cprimod_cpri_rx_control_word_l1_signal_signal_protection_set), 2105 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_cw_slow_hdlc_config_get), 2106 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_cw_slow_hdlc_config_set), 2107 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_cw_fast_eth_config_get), 2108 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_cw_fast_eth_config_set), 2109 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_vsd_cw_config_get), 2110 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_vsd_cw_config_set), 2111 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_vsd_ctrl_flow_add), 2112 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_vsd_ctrl_flow_delete), 2113 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_vsd_ctrl_flow_get), 2114 CINT_FWRAPPER_ENTRY(cprimod_encap_control_queue_tag_to_flow_id_map_get), 2115 CINT_FWRAPPER_ENTRY(cprimod_encap_control_queue_tag_to_flow_id_map_set), 2116 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_cw_config_get), 2117 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_cw_config_set), 2118 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_ctrl_flow_add), 2119 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_ctrl_flow_delete), 2120 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_ctrl_flow_get), 2121 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_vsd_raw_config_get), 2122 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_vsd_raw_config_set), 2123 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_raw_config_get), 2124 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_raw_config_set), 2125 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_raw_filter_get), 2126 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_vsd_raw_filter_set), 2127 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_brcm_rsvd5_control_config_get), 2128 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_brcm_rsvd5_control_config_set), 2129 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_brcm_rsvd5_control_config_get), 2130 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_brcm_rsvd5_control_config_set), 2131 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_gcw_config_get), 2132 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_gcw_config_set), 2133 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_gcw_config_get), 2134 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_gcw_config_set), 2135 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_gcw_filter_get), 2136 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_gcw_filter_set), 2137 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_control_word_set), 2138 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_control_message_config_set), 2139 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_control_flow_config_get), 2140 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_control_flow_config_set), 2141 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_sync_profile_entry_get), 2142 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_rx_sync_profile_entry_set), 2143 CINT_FWRAPPER_ENTRY(cprimod_rx_tag_config_set), 2144 CINT_FWRAPPER_ENTRY(cprimod_rx_tag_gen_entry_add), 2145 CINT_FWRAPPER_ENTRY(cprimod_rx_tag_gen_entry_delete), 2146 CINT_FWRAPPER_ENTRY(cprimod_rx_control_flow_tag_option_set), 2147 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_flow_group_member_add), 2148 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_flow_group_member_delete), 2149 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_eth_message_config_set), 2150 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_single_raw_message_config_set), 2151 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_single_tunnel_message_config_set), 2152 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_flow_config_get), 2153 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_flow_config_set), 2154 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_flow_header_index_get), 2155 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_flow_header_index_set), 2156 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_header_entry_get), 2157 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_control_header_entry_set), 2158 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_fast_eth_config_set), 2159 CINT_FWRAPPER_ENTRY(cprimod_cpri_or_enet_port_get), 2160 CINT_FWRAPPER_ENTRY(cprimod_cpri_or_enet_port_set), 2161 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_enable_get), 2162 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_enable_set), 2163 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_enable_get), 2164 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_enable_set), 2165 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_interrupt_link_status_get), 2166 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_interrupt_callback_register), 2167 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_interrupt_callback_unregister), 2168 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_interrupt_enable_set), 2169 CINT_FWRAPPER_ENTRY(cprimod_cpri_cpm_interrupt_data_init), 2170 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_interrupt_process), 2171 CINT_FWRAPPER_ENTRY(cprimod_fast_clk_bit_time_period_get), 2172 CINT_FWRAPPER_ENTRY(cprimod_fast_clk_bit_time_period_set), 2173 CINT_FWRAPPER_ENTRY(cprimod_1588_bit_time_period_get), 2174 CINT_FWRAPPER_ENTRY(cprimod_1588_bit_time_period_set), 2175 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_capture_config_get), 2176 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_capture_config_set), 2177 CINT_FWRAPPER_ENTRY(cprimod_1588_captured_timestamp_get), 2178 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_adjust_get), 2179 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_adjust_set), 2180 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_fifo_config_get), 2181 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_fifo_config_set), 2182 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_cmic_config_get), 2183 CINT_FWRAPPER_ENTRY(cprimod_1588_timestamp_cmic_config_set), 2184 CINT_FWRAPPER_ENTRY(cprimod_cpri_basic_frame_info_get), 2185 CINT_FWRAPPER_ENTRY(cprimod_cpri_agnostic_mode_basic_frame_config_set), 2186 CINT_FWRAPPER_ENTRY(cprimod_cpri_interface_bus_width_get), 2187 CINT_FWRAPPER_ENTRY(cprimod_cpri_tunnel_mode_basic_frame_config_set), 2188 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_agnostic_mode_basic_frame_config_set), 2189 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_enable_get), 2190 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_enable_set), 2191 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_config_get), 2192 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_config_set), 2193 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_adjust_get), 2194 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_adjust_set), 2195 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_approximate_increment_get), 2196 CINT_FWRAPPER_ENTRY(cprimod_encap_presentation_time_approximate_increment_set), 2197 CINT_FWRAPPER_ENTRY(cprimod_decap_agnostic_mode_enable_get), 2198 CINT_FWRAPPER_ENTRY(cprimod_decap_agnostic_mode_enable_set), 2199 CINT_FWRAPPER_ENTRY(cprimod_decap_agnostic_mode_config_get), 2200 CINT_FWRAPPER_ENTRY(cprimod_decap_agnostic_mode_config_set), 2201 CINT_FWRAPPER_ENTRY(cprimod_decap_presentation_time_config_get), 2202 CINT_FWRAPPER_ENTRY(cprimod_decap_presentation_time_config_set), 2203 CINT_FWRAPPER_ENTRY(cprimod_compression_lookup_table_get), 2204 CINT_FWRAPPER_ENTRY(cprimod_compression_lookup_table_set), 2205 CINT_FWRAPPER_ENTRY(cprimod_decompression_lookup_table_get), 2206 CINT_FWRAPPER_ENTRY(cprimod_decompression_lookup_table_set), 2207 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_decap_queue_flow_control_get), 2208 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_decap_queue_flow_control_set), 2209 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_fec_enable_get), 2210 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_fec_enable_set), 2211 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_fec_timestamp_config_get), 2212 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_fec_timestamp_config_set), 2213 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_fec_aux_config_get), 2214 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_fec_aux_config_set), 2215 #ifdef CPRIMOD_SUPPORT 2216 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_ecc_interrupt_enable_set), 2217 #endif /* CPRIMOD_SUPPORT */ 2218 #ifdef CPRIMOD_SUPPORT 2219 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_ecc_interrupt_status_get), 2220 #endif /* CPRIMOD_SUPPORT */ 2221 #ifdef CPRIMOD_SUPPORT_ECC_INJECT 2222 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_ecc_interrupt_test), 2223 #endif /* CPRIMOD_SUPPORT_ECC_INJECT */ 2224 CINT_FWRAPPER_ENTRY(cprimod_cpri_pll_status_get), 2225 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_reset_get), 2226 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_reset_set), 2227 CINT_FWRAPPER_ENTRY(cprimod_cpri_init), 2228 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_gcw_word_get), 2229 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_gcw_word_set), 2230 CINT_FWRAPPER_ENTRY(cprimod_cpri_mac_drain_start), 2231 CINT_FWRAPPER_ENTRY(cprimod_cpri_mac_drain_stop), 2232 CINT_FWRAPPER_ENTRY(cprimod_cpri_mac_credit_reset_get), 2233 CINT_FWRAPPER_ENTRY(cprimod_cpri_mac_credit_reset_set), 2234 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_link_up_event), 2235 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_link_down_event), 2236 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_tunnel_mode_get), 2237 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_tunnel_mode_set), 2238 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_agnostic_mode_get), 2239 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_tx_agnostic_mode_set), 2240 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_rx_agnostic_mode_get), 2241 CINT_FWRAPPER_ENTRY(cprimod_port_pmd_status_get), 2242 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_link_get), 2243 #ifdef CPRIMOD_SUPPORT 2244 CINT_FWRAPPER_ENTRY(cprimod_cpri_encap_header_field_mapping_get), 2245 #endif /* CPRIMOD_SUPPORT */ 2246 #ifdef CPRIMOD_SUPPORT 2247 CINT_FWRAPPER_ENTRY(cprimod_cpri_encap_header_field_mapping_set), 2248 #endif /* CPRIMOD_SUPPORT */ 2249 #ifdef CPRIMOD_SUPPORT 2250 CINT_FWRAPPER_ENTRY(cprimod_cpri_decap_header_field_mapping_get), 2251 #endif /* CPRIMOD_SUPPORT */ 2252 #ifdef CPRIMOD_SUPPORT 2253 CINT_FWRAPPER_ENTRY(cprimod_cpri_decap_header_field_mapping_set), 2254 #endif /* CPRIMOD_SUPPORT */ 2255 #ifdef CPRIMOD_SUPPORT 2256 CINT_FWRAPPER_ENTRY(cprimod_cpri_header_field_adjustment_config_get), 2257 #endif /* CPRIMOD_SUPPORT */ 2258 #ifdef CPRIMOD_SUPPORT 2259 CINT_FWRAPPER_ENTRY(cprimod_cpri_header_field_adjustment_config_set), 2260 #endif /* CPRIMOD_SUPPORT */ 2261 #ifdef CPRIMOD_SUPPORT 2262 CINT_FWRAPPER_ENTRY(cprimod_cpri_decap_header_field_mask_get), 2263 #endif /* CPRIMOD_SUPPORT */ 2264 #ifdef CPRIMOD_SUPPORT 2265 CINT_FWRAPPER_ENTRY(cprimod_cpri_decap_header_field_mask_set), 2266 #endif /* CPRIMOD_SUPPORT */ 2267 #ifdef CPRIMOD_SUPPORT 2268 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_compression_saturation_config_get), 2269 #endif /* CPRIMOD_SUPPORT */ 2270 #ifdef CPRIMOD_SUPPORT 2271 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_compression_saturation_config_set), 2272 #endif /* CPRIMOD_SUPPORT */ 2273 #ifdef CPRIMOD_SUPPORT 2274 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_decompression_saturation_config_get), 2275 #endif /* CPRIMOD_SUPPORT */ 2276 #ifdef CPRIMOD_SUPPORT 2277 CINT_FWRAPPER_ENTRY(cprimod_cpri_port_decompression_saturation_config_set), 2278 #endif /* CPRIMOD_SUPPORT */ 2279 #ifdef CPRIMOD_SUPPORT 2280 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_padding_size_get), 2281 #endif /* CPRIMOD_SUPPORT */ 2282 #ifdef CPRIMOD_SUPPORT 2283 CINT_FWRAPPER_ENTRY(cprimod_rsvd4_tx_padding_size_set), 2284 #endif /* CPRIMOD_SUPPORT */ 2285 { NULL } 2286 }; 2287 2288 /* Functions pointers section */ 2289 static cint_function_pointer_t __cint_function_pointers[2]; 2290 2291 static int 2292 __cint_fpointer__cprimod_firmware_loader_f(const phymod_core_access_t* core, uint32_t length, const uint8_t* data) 2293 { 2294 int returnval; 2295 2296 cint_interpreter_callback(__cint_function_pointers+0, 3, 1, &core, &length, &data, &returnval); 2297 return returnval; 2298 } 2299 2300 2301 static cint_parameter_desc_t __cint_parameters_cprimod_firmware_loader_f[] = 2302 { 2303 {"int", "r", 0, 0}, 2304 {"const phymod_core_access_t", "core", 1, 0}, 2305 {"uint32_t", "length", 0, 0}, 2306 {"const uint8_t", "data", 1, 0}, 2307 { NULL } 2308 }; 2309 2310 2311 static cint_function_pointer_t __cint_function_pointers[] = 2312 { 2313 { 2314 "cprimod_firmware_loader_f", 2315 (cint_fpointer_t) __cint_fpointer__cprimod_firmware_loader_f, 2316 __cint_parameters_cprimod_firmware_loader_f 2317 }, 2318 { NULL } 2319 }; 2320 2321 /* Structs section */ 2322 static void* 2323 __cint_maddr__cprimod_basic_frame_usage_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2324 { 2325 void* rv; 2326 cprimod_basic_frame_usage_entry_t* s = (cprimod_basic_frame_usage_entry_t*) p; 2327 switch(mnum) 2328 { 2329 case 0: rv = &(s->axc_id);break; 2330 case 1: rv = &(s->start_bit);break; 2331 case 2: rv = &(s->num_bits);break; 2332 default: rv = NULL; break; 2333 } 2334 return rv; 2335 } 2336 2337 static void* 2338 __cint_maddr__cprimod_cpri_container_config_t(void* p, int mnum, cint_struct_type_t* parent) 2339 { 2340 void* rv; 2341 cprimod_cpri_container_config_t* s = (cprimod_cpri_container_config_t*) p; 2342 switch(mnum) 2343 { 2344 case 0: rv = &(s->map_method);break; 2345 case 1: rv = &(s->Naxc);break; 2346 case 2: rv = &(s->K);break; 2347 case 3: rv = &(s->Nst);break; 2348 case 4: rv = &(s->Na);break; 2349 case 5: rv = &(s->Nc);break; 2350 case 6: rv = &(s->Nv);break; 2351 case 7: rv = &(s->frame_sync_mode);break; 2352 case 8: rv = &(s->basic_frame_offset);break; 2353 case 9: rv = &(s->radio_frame_offset);break; 2354 case 10: rv = &(s->hyper_frame_offset);break; 2355 case 11: rv = &(s->cblk_cnt);break; 2356 default: rv = NULL; break; 2357 } 2358 return rv; 2359 } 2360 2361 static void* 2362 __cint_maddr__cprimod_rsvd4_container_config_t(void* p, int mnum, cint_struct_type_t* parent) 2363 { 2364 void* rv; 2365 cprimod_rsvd4_container_config_t* s = (cprimod_rsvd4_container_config_t*) p; 2366 switch(mnum) 2367 { 2368 case 0: rv = &(s->axc_id);break; 2369 case 1: rv = &(s->stuffing_cnt);break; 2370 case 2: rv = &(s->msg_ts_mode);break; 2371 case 3: rv = &(s->msg_ts_cnt);break; 2372 case 4: rv = &(s->frame_sync_mode);break; 2373 case 5: rv = &(s->master_frame_offset);break; 2374 case 6: rv = &(s->message_number_offset);break; 2375 case 7: rv = &(s->container_block_cnt);break; 2376 case 8: rv = &(s->use_ts_dbm);break; 2377 case 9: rv = &(s->ts_dbm_prof_num);break; 2378 case 10: rv = &(s->num_active_slots);break; 2379 case 11: rv = &(s->msg_addr);break; 2380 case 12: rv = &(s->msg_type);break; 2381 case 13: rv = &(s->msg_ts_offset);break; 2382 default: rv = NULL; break; 2383 } 2384 return rv; 2385 } 2386 2387 static void* 2388 __cint_maddr__cprimod_payload_size_info_t(void* p, int mnum, cint_struct_type_t* parent) 2389 { 2390 void* rv; 2391 cprimod_payload_size_info_t* s = (cprimod_payload_size_info_t*) p; 2392 switch(mnum) 2393 { 2394 case 0: rv = &(s->packet_size);break; 2395 case 1: rv = &(s->last_packet_num);break; 2396 case 2: rv = &(s->last_packet_size);break; 2397 default: rv = NULL; break; 2398 } 2399 return rv; 2400 } 2401 2402 static void* 2403 __cint_maddr__cprimod_encap_decap_data_config_t(void* p, int mnum, cint_struct_type_t* parent) 2404 { 2405 void* rv; 2406 cprimod_encap_decap_data_config_t* s = (cprimod_encap_decap_data_config_t*) p; 2407 switch(mnum) 2408 { 2409 case 0: rv = &(s->sample_size);break; 2410 case 1: rv = &(s->truncation_enable);break; 2411 case 2: rv = &(s->truncation_type);break; 2412 case 3: rv = &(s->compression_type);break; 2413 case 4: rv = &(s->mux_enable);break; 2414 case 5: rv = &(s->bit_reversal);break; 2415 case 6: rv = &(s->buffer_size);break; 2416 case 7: rv = &(s->priority);break; 2417 case 8: rv = &(s->cycle_size);break; 2418 case 9: rv = &(s->is_agnostic);break; 2419 default: rv = NULL; break; 2420 } 2421 return rv; 2422 } 2423 2424 static void* 2425 __cint_maddr__cprimod_rsvd4_encap_data_config_t(void* p, int mnum, cint_struct_type_t* parent) 2426 { 2427 void* rv; 2428 cprimod_rsvd4_encap_data_config_t* s = (cprimod_rsvd4_encap_data_config_t*) p; 2429 switch(mnum) 2430 { 2431 case 0: rv = &(s->buffer_size);break; 2432 case 1: rv = &(s->priority);break; 2433 case 2: rv = &(s->gsm_pad_size);break; 2434 case 3: rv = &(s->gsm_extra_pad_size);break; 2435 case 4: rv = &(s->gsm_pad_enable);break; 2436 case 5: rv = &(s->gsm_control_location);break; 2437 case 6: rv = &(s->bit_reversal);break; 2438 default: rv = NULL; break; 2439 } 2440 return rv; 2441 } 2442 2443 static void* 2444 __cint_maddr__cprimod_rsvd4_decap_data_config_t(void* p, int mnum, cint_struct_type_t* parent) 2445 { 2446 void* rv; 2447 cprimod_rsvd4_decap_data_config_t* s = (cprimod_rsvd4_decap_data_config_t*) p; 2448 switch(mnum) 2449 { 2450 case 0: rv = &(s->buffer_size);break; 2451 case 1: rv = &(s->cycle_size);break; 2452 case 2: rv = &(s->gsm_pad_size);break; 2453 case 3: rv = &(s->gsm_extra_pad_size);break; 2454 case 4: rv = &(s->gsm_pad_enable);break; 2455 case 5: rv = &(s->gsm_control_location);break; 2456 case 6: rv = &(s->bit_reversal);break; 2457 default: rv = NULL; break; 2458 } 2459 return rv; 2460 } 2461 2462 static void* 2463 __cint_maddr__cprimod_encap_header_config_t(void* p, int mnum, cint_struct_type_t* parent) 2464 { 2465 void* rv; 2466 cprimod_encap_header_config_t* s = (cprimod_encap_header_config_t*) p; 2467 switch(mnum) 2468 { 2469 case 0: rv = &(s->header_type);break; 2470 case 1: rv = &(s->flow_id);break; 2471 case 2: rv = &(s->roe_subtype);break; 2472 case 3: rv = &(s->ordering_info_index);break; 2473 case 4: rv = &(s->mac_da_index);break; 2474 case 5: rv = &(s->mac_sa_index);break; 2475 case 6: rv = &(s->vlan_type);break; 2476 case 7: rv = &(s->vlan_id_0_index);break; 2477 case 8: rv = &(s->vlan_id_1_index);break; 2478 case 9: rv = &(s->vlan_0_priority);break; 2479 case 10: rv = &(s->vlan_1_priority);break; 2480 case 11: rv = &(s->vlan_eth_type_index);break; 2481 case 12: rv = &(s->use_tagid_for_vlan);break; 2482 case 13: rv = &(s->use_tagid_for_flowid);break; 2483 case 14: rv = &(s->use_opcode);break; 2484 case 15: rv = &(s->roe_opcode);break; 2485 case 16: rv = &(s->version);break; 2486 case 17: rv = &(s->roe_frame_format);break; 2487 case 18: rv = &(s->ecpri_pc_id);break; 2488 case 19: rv = &(s->ecpri_msg_type);break; 2489 default: rv = NULL; break; 2490 } 2491 return rv; 2492 } 2493 2494 static void* 2495 __cint_maddr__cprimod_encap_ordering_info_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2496 { 2497 void* rv; 2498 cprimod_encap_ordering_info_entry_t* s = (cprimod_encap_ordering_info_entry_t*) p; 2499 switch(mnum) 2500 { 2501 case 0: rv = &(s->type);break; 2502 case 1: rv = &(s->pcnt_prop);break; 2503 case 2: rv = &(s->pcnt_size);break; 2504 case 3: rv = &(s->pcnt_increment);break; 2505 case 4: rv = &(s->pcnt_max);break; 2506 case 5: rv = &(s->qcnt_prop);break; 2507 case 6: rv = &(s->qcnt_size);break; 2508 case 7: rv = &(s->qcnt_increment);break; 2509 case 8: rv = &(s->qcnt_max);break; 2510 case 9: rv = &(s->seq_reserve_value);break; 2511 default: rv = NULL; break; 2512 } 2513 return rv; 2514 } 2515 2516 static void* 2517 __cint_maddr__cprimod_decap_ordering_info_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2518 { 2519 void* rv; 2520 cprimod_decap_ordering_info_entry_t* s = (cprimod_decap_ordering_info_entry_t*) p; 2521 switch(mnum) 2522 { 2523 case 0: rv = &(s->type);break; 2524 case 1: rv = &(s->pcnt_extended);break; 2525 case 2: rv = &(s->pcnt_pkt_count);break; 2526 case 3: rv = &(s->pcnt_size);break; 2527 case 4: rv = &(s->pcnt_increment);break; 2528 case 5: rv = &(s->pcnt_max);break; 2529 case 6: rv = &(s->pcnt_bias);break; 2530 case 7: rv = &(s->pcnt_increment_p2);break; 2531 case 8: rv = &(s->qcnt_size);break; 2532 case 9: rv = &(s->qcnt_increment);break; 2533 case 10: rv = &(s->qcnt_max);break; 2534 case 11: rv = &(s->qcnt_bias);break; 2535 case 12: rv = &(s->qcnt_increment_p2);break; 2536 case 13: rv = &(s->modulo_2);break; 2537 case 14: rv = &(s->gsm_tsn_bitmap);break; 2538 case 15: rv = &(s->seq_reserve_value);break; 2539 default: rv = NULL; break; 2540 } 2541 return rv; 2542 } 2543 2544 static void* 2545 __cint_maddr__cprimod_cpri_ordering_info_offset_t(void* p, int mnum, cint_struct_type_t* parent) 2546 { 2547 void* rv; 2548 cprimod_cpri_ordering_info_offset_t* s = (cprimod_cpri_ordering_info_offset_t*) p; 2549 switch(mnum) 2550 { 2551 case 0: rv = &(s->p_size);break; 2552 case 1: rv = &(s->p_offset);break; 2553 case 2: rv = &(s->q_size);break; 2554 case 3: rv = &(s->q_offset);break; 2555 default: rv = NULL; break; 2556 } 2557 return rv; 2558 } 2559 2560 static void* 2561 __cint_maddr__cprimod_header_compare_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2562 { 2563 void* rv; 2564 cprimod_header_compare_entry_t* s = (cprimod_header_compare_entry_t*) p; 2565 switch(mnum) 2566 { 2567 case 0: rv = &(s->valid);break; 2568 case 1: rv = &(s->match_data);break; 2569 case 2: rv = &(s->mask);break; 2570 case 3: rv = &(s->flow_id);break; 2571 case 4: rv = &(s->flow_type);break; 2572 default: rv = NULL; break; 2573 } 2574 return rv; 2575 } 2576 2577 static void* 2578 __cint_maddr__cprimod_modulo_rule_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2579 { 2580 void* rv; 2581 cprimod_modulo_rule_entry_t* s = (cprimod_modulo_rule_entry_t*) p; 2582 switch(mnum) 2583 { 2584 case 0: rv = &(s->active);break; 2585 case 1: rv = &(s->modulo_value);break; 2586 case 2: rv = &(s->modulo_index);break; 2587 case 3: rv = &(s->dbm_enable);break; 2588 case 4: rv = &(s->flow_dbm_id);break; 2589 case 5: rv = &(s->flow_type);break; 2590 default: rv = NULL; break; 2591 } 2592 return rv; 2593 } 2594 2595 static void* 2596 __cint_maddr__cprimod_dbm_rule_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2597 { 2598 void* rv; 2599 cprimod_dbm_rule_entry_t* s = (cprimod_dbm_rule_entry_t*) p; 2600 switch(mnum) 2601 { 2602 case 0: rv = &(s->bm1_mult);break; 2603 case 1: rv = &(s->bm1);break; 2604 case 2: rv = &(s->bm1_size);break; 2605 case 3: rv = &(s->bm2);break; 2606 case 4: rv = &(s->bm2_size);break; 2607 case 5: rv = &(s->num_slots);break; 2608 case 6: rv = &(s->pos_grp_index);break; 2609 case 7: rv = &(s->pos_grp_size);break; 2610 default: rv = NULL; break; 2611 } 2612 return rv; 2613 } 2614 2615 static void* 2616 __cint_maddr__cprimod_secondary_dbm_rule_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2617 { 2618 void* rv; 2619 cprimod_secondary_dbm_rule_entry_t* s = (cprimod_secondary_dbm_rule_entry_t*) p; 2620 switch(mnum) 2621 { 2622 case 0: rv = &(s->bm1_mult);break; 2623 case 1: rv = &(s->bm1);break; 2624 case 2: rv = &(s->bm1_size);break; 2625 case 3: rv = &(s->bm2);break; 2626 case 4: rv = &(s->bm2_size);break; 2627 case 5: rv = &(s->num_slots);break; 2628 default: rv = NULL; break; 2629 } 2630 return rv; 2631 } 2632 2633 static void* 2634 __cint_maddr__cprimod_dbm_pos_table_entry_t(void* p, int mnum, cint_struct_type_t* parent) 2635 { 2636 void* rv; 2637 cprimod_dbm_pos_table_entry_t* s = (cprimod_dbm_pos_table_entry_t*) p; 2638 switch(mnum) 2639 { 2640 case 0: rv = &(s->valid);break; 2641 case 1: rv = &(s->flow_id);break; 2642 case 2: rv = &(s->flow_type);break; 2643 case 3: rv = &(s->index);break; 2644 default: rv = NULL; break; 2645 } 2646 return rv; 2647 } 2648 2649 static void* 2650 __cint_maddr__cprimod_port_interface_config_t(void* p, int mnum, cint_struct_type_t* parent) 2651 { 2652 void* rv; 2653 cprimod_port_interface_config_t* s = (cprimod_port_interface_config_t*) p; 2654 switch(mnum) 2655 { 2656 case 0: rv = &(s->speed);break; 2657 case 1: rv = &(s->interface);break; 2658 default: rv = NULL; break; 2659 } 2660 return rv; 2661 } 2662 2663 static void* 2664 __cint_maddr__cprimod_port_rsvd4_config_t(void* p, int mnum, cint_struct_type_t* parent) 2665 { 2666 void* rv; 2667 cprimod_port_rsvd4_config_t* s = (cprimod_port_rsvd4_config_t*) p; 2668 switch(mnum) 2669 { 2670 case 0: rv = &(s->speed);break; 2671 case 1: rv = &(s->interface);break; 2672 default: rv = NULL; break; 2673 } 2674 return rv; 2675 } 2676 2677 static void* 2678 __cint_maddr__cprimod_polarity_t(void* p, int mnum, cint_struct_type_t* parent) 2679 { 2680 void* rv; 2681 cprimod_polarity_t* s = (cprimod_polarity_t*) p; 2682 switch(mnum) 2683 { 2684 case 0: rv = &(s->rx_polarity);break; 2685 case 1: rv = &(s->tx_polarity);break; 2686 default: rv = NULL; break; 2687 } 2688 return rv; 2689 } 2690 2691 static void* 2692 __cint_maddr__cprimod_lane_map_t(void* p, int mnum, cint_struct_type_t* parent) 2693 { 2694 void* rv; 2695 cprimod_lane_map_t* s = (cprimod_lane_map_t*) p; 2696 switch(mnum) 2697 { 2698 case 0: rv = &(s->num_of_lanes);break; 2699 case 1: rv = &(s->lane_map_rx);break; 2700 case 2: rv = &(s->lane_map_tx);break; 2701 default: rv = NULL; break; 2702 } 2703 return rv; 2704 } 2705 2706 static void* 2707 __cint_maddr__cprimod_firmware_core_config_t(void* p, int mnum, cint_struct_type_t* parent) 2708 { 2709 void* rv; 2710 cprimod_firmware_core_config_t* s = (cprimod_firmware_core_config_t*) p; 2711 switch(mnum) 2712 { 2713 case 0: rv = &(s->CoreConfigFromPCS);break; 2714 case 1: rv = &(s->VcoRate);break; 2715 case 2: rv = &(s->disable_write_pll_iqp);break; 2716 default: rv = NULL; break; 2717 } 2718 return rv; 2719 } 2720 2721 static void* 2722 __cint_maddr__cprimod_afe_pll_t(void* p, int mnum, cint_struct_type_t* parent) 2723 { 2724 void* rv; 2725 cprimod_afe_pll_t* s = (cprimod_afe_pll_t*) p; 2726 switch(mnum) 2727 { 2728 case 0: rv = &(s->afe_pll_change_default);break; 2729 case 1: rv = &(s->ams_pll_iqp);break; 2730 case 2: rv = &(s->ams_pll_en_hrz);break; 2731 default: rv = NULL; break; 2732 } 2733 return rv; 2734 } 2735 2736 static void* 2737 __cint_maddr__cprimod_pll_parm_t(void* p, int mnum, cint_struct_type_t* parent) 2738 { 2739 void* rv; 2740 cprimod_pll_parm_t* s = (cprimod_pll_parm_t*) p; 2741 switch(mnum) 2742 { 2743 case 0: rv = &(s->change_pll);break; 2744 case 1: rv = &(s->vcoRate);break; 2745 case 2: rv = &(s->div2);break; 2746 case 3: rv = &(s->div4);break; 2747 case 4: rv = &(s->afe_pll);break; 2748 default: rv = NULL; break; 2749 } 2750 return rv; 2751 } 2752 2753 static void* 2754 __cint_maddr__cprimod_core_init_config_t(void* p, int mnum, cint_struct_type_t* parent) 2755 { 2756 void* rv; 2757 cprimod_core_init_config_t* s = (cprimod_core_init_config_t*) p; 2758 switch(mnum) 2759 { 2760 case 0: rv = &(s->lane_map);break; 2761 case 1: rv = &(s->firmware_load_method);break; 2762 case 2: rv = &(s->firmware_loader);break; 2763 case 3: rv = &(s->firmware_core_config);break; 2764 case 4: rv = &(s->flags);break; 2765 case 5: rv = &(s->tx_input_voltage);break; 2766 case 6: rv = &(s->pll0);break; 2767 case 7: rv = &(s->pll1);break; 2768 case 8: rv = &(s->trcvr_host_managed);break; 2769 default: rv = NULL; break; 2770 } 2771 return rv; 2772 } 2773 2774 static void* 2775 __cint_maddr__cprimod_core_status_t(void* p, int mnum, cint_struct_type_t* parent) 2776 { 2777 void* rv; 2778 cprimod_core_status_t* s = (cprimod_core_status_t*) p; 2779 switch(mnum) 2780 { 2781 case 0: rv = &(s->pmd_active);break; 2782 default: rv = NULL; break; 2783 } 2784 return rv; 2785 } 2786 2787 static void* 2788 __cint_maddr__cprimod_port_init_config_t(void* p, int mnum, cint_struct_type_t* parent) 2789 { 2790 void* rv; 2791 cprimod_port_init_config_t* s = (cprimod_port_init_config_t*) p; 2792 switch(mnum) 2793 { 2794 case 0: rv = &(s->polarity_rx);break; 2795 case 1: rv = &(s->polarity_tx);break; 2796 case 2: rv = &(s->interface);break; 2797 case 3: rv = &(s->tx_cpri_speed);break; 2798 case 4: rv = &(s->rx_cpri_speed);break; 2799 case 5: rv = &(s->tx_rsvd4_speed);break; 2800 case 6: rv = &(s->rx_rsvd4_speed);break; 2801 case 7: rv = &(s->roe_stuffing_bit);break; 2802 case 8: rv = &(s->roe_reserved_bit);break; 2803 case 9: rv = &(s->serdes_scrambler_seed);break; 2804 case 10: rv = &(s->serdes_scrambler_enable);break; 2805 case 11: rv = &(s->mix_cpri_enet);break; 2806 case 12: rv = &(s->vco_for_lane);break; 2807 case 13: rv = &(s->pll_in_use);break; 2808 case 14: rv = &(s->tx_params);break; 2809 case 15: rv = &(s->tx_params_user_config);break; 2810 case 16: rv = &(s->parity_enable);break; 2811 default: rv = NULL; break; 2812 } 2813 return rv; 2814 } 2815 2816 static void* 2817 __cint_maddr__cprimod_slow_hdlc_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 2818 { 2819 void* rv; 2820 cprimod_slow_hdlc_config_info_t* s = (cprimod_slow_hdlc_config_info_t*) p; 2821 switch(mnum) 2822 { 2823 case 0: rv = &(s->tx_crc_mode);break; 2824 case 1: rv = &(s->tx_flag_size);break; 2825 case 2: rv = &(s->tx_filling_flag_pattern);break; 2826 case 3: rv = &(s->crc_init_val);break; 2827 case 4: rv = &(s->use_fe_mac);break; 2828 case 5: rv = &(s->crc_byte_swap);break; 2829 case 6: rv = &(s->no_fcs_err_check);break; 2830 case 7: rv = &(s->cw_sel);break; 2831 case 8: rv = &(s->cw_size);break; 2832 case 9: rv = &(s->fcs_size);break; 2833 case 10: rv = &(s->runt_frame_drop);break; 2834 case 11: rv = &(s->long_frame_drop);break; 2835 case 12: rv = &(s->min_frame_size);break; 2836 case 13: rv = &(s->max_frame_size);break; 2837 case 14: rv = &(s->queue_num);break; 2838 default: rv = NULL; break; 2839 } 2840 return rv; 2841 } 2842 2843 static void* 2844 __cint_maddr__cprimod_fast_eth_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 2845 { 2846 void* rv; 2847 cprimod_fast_eth_config_info_t* s = (cprimod_fast_eth_config_info_t*) p; 2848 switch(mnum) 2849 { 2850 case 0: rv = &(s->tx_crc_mode);break; 2851 case 1: rv = &(s->schan_start);break; 2852 case 2: rv = &(s->schan_size);break; 2853 case 3: rv = &(s->cw_sel);break; 2854 case 4: rv = &(s->cw_size);break; 2855 case 5: rv = &(s->min_packet_size);break; 2856 case 6: rv = &(s->max_packet_size);break; 2857 case 7: rv = &(s->min_packet_drop);break; 2858 case 8: rv = &(s->max_packet_drop);break; 2859 case 9: rv = &(s->strip_crc);break; 2860 case 10: rv = &(s->min_ipg);break; 2861 case 11: rv = &(s->queue_num);break; 2862 case 12: rv = &(s->no_fcs_err_check);break; 2863 default: rv = NULL; break; 2864 } 2865 return rv; 2866 } 2867 2868 static void* 2869 __cint_maddr__cprimod_cpri_rx_vsd_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 2870 { 2871 void* rv; 2872 cprimod_cpri_rx_vsd_config_info_t* s = (cprimod_cpri_rx_vsd_config_info_t*) p; 2873 switch(mnum) 2874 { 2875 case 0: rv = &(s->subchan_start);break; 2876 case 1: rv = &(s->subchan_size);break; 2877 case 2: rv = &(s->subchan_bytes);break; 2878 case 3: rv = &(s->subchan_steps);break; 2879 case 4: rv = &(s->flow_bytes);break; 2880 case 5: rv = &(s->queue_num);break; 2881 case 6: rv = &(s->rsvd_sector_mask);break; 2882 default: rv = NULL; break; 2883 } 2884 return rv; 2885 } 2886 2887 static void* 2888 __cint_maddr__cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t(void* p, int mnum, cint_struct_type_t* parent) 2889 { 2890 void* rv; 2891 cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t* s = (cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t*) p; 2892 switch(mnum) 2893 { 2894 case 0: rv = &(s->hyper_frame_number);break; 2895 case 1: rv = &(s->hyper_frame_modulo);break; 2896 case 2: rv = &(s->filter_zero_data);break; 2897 case 3: rv = &(s->section_num);break; 2898 case 4: rv = &(s->num_sector);break; 2899 case 5: rv = &(s->tag_id);break; 2900 default: rv = NULL; break; 2901 } 2902 return rv; 2903 } 2904 2905 static void* 2906 __cint_maddr__cprimod_cpri_tx_vsd_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 2907 { 2908 void* rv; 2909 cprimod_cpri_tx_vsd_config_info_t* s = (cprimod_cpri_tx_vsd_config_info_t*) p; 2910 switch(mnum) 2911 { 2912 case 0: rv = &(s->subchan_start);break; 2913 case 1: rv = &(s->subchan_size);break; 2914 case 2: rv = &(s->subchan_bytes);break; 2915 case 3: rv = &(s->subchan_steps);break; 2916 case 4: rv = &(s->flow_bytes);break; 2917 case 5: rv = &(s->queue_num);break; 2918 case 6: rv = &(s->rsvd_sector_mask);break; 2919 case 7: rv = &(s->byte_order_swap);break; 2920 default: rv = NULL; break; 2921 } 2922 return rv; 2923 } 2924 2925 static void* 2926 __cint_maddr__cprimod_cpri_tx_vsd_flow_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 2927 { 2928 void* rv; 2929 cprimod_cpri_tx_vsd_flow_config_info_t* s = (cprimod_cpri_tx_vsd_flow_config_info_t*) p; 2930 switch(mnum) 2931 { 2932 case 0: rv = &(s->hyper_frame_number);break; 2933 case 1: rv = &(s->hyper_frame_modulo);break; 2934 case 2: rv = &(s->repeat_mode);break; 2935 case 3: rv = &(s->section_num);break; 2936 case 4: rv = &(s->num_sector);break; 2937 default: rv = NULL; break; 2938 } 2939 return rv; 2940 } 2941 2942 static void* 2943 __cint_maddr__cprimod_cpri_rx_vsd_raw_config_t(void* p, int mnum, cint_struct_type_t* parent) 2944 { 2945 void* rv; 2946 cprimod_cpri_rx_vsd_raw_config_t* s = (cprimod_cpri_rx_vsd_raw_config_t*) p; 2947 switch(mnum) 2948 { 2949 case 0: rv = &(s->schan_start);break; 2950 case 1: rv = &(s->schan_size);break; 2951 case 2: rv = &(s->cw_sel);break; 2952 case 3: rv = &(s->cw_size);break; 2953 case 4: rv = &(s->filter_mode);break; 2954 case 5: rv = &(s->hyper_frame_index);break; 2955 case 6: rv = &(s->hyper_frame_modulo);break; 2956 case 7: rv = &(s->match_offset);break; 2957 case 8: rv = &(s->match_value);break; 2958 case 9: rv = &(s->match_mask);break; 2959 case 10: rv = &(s->queue_num);break; 2960 default: rv = NULL; break; 2961 } 2962 return rv; 2963 } 2964 2965 static void* 2966 __cint_maddr__cprimod_cpri_tx_vsd_raw_config_t(void* p, int mnum, cint_struct_type_t* parent) 2967 { 2968 void* rv; 2969 cprimod_cpri_tx_vsd_raw_config_t* s = (cprimod_cpri_tx_vsd_raw_config_t*) p; 2970 switch(mnum) 2971 { 2972 case 0: rv = &(s->schan_start);break; 2973 case 1: rv = &(s->schan_size);break; 2974 case 2: rv = &(s->cw_sel);break; 2975 case 3: rv = &(s->cw_size);break; 2976 case 4: rv = &(s->hyper_frame_index);break; 2977 case 5: rv = &(s->hyper_frame_modulo);break; 2978 case 6: rv = &(s->queue_num);break; 2979 case 7: rv = &(s->map_mode);break; 2980 case 8: rv = &(s->repeat_enable);break; 2981 case 9: rv = &(s->bfn0_filter_enable);break; 2982 case 10: rv = &(s->bfn1_filter_enable);break; 2983 case 11: rv = &(s->idle_value);break; 2984 default: rv = NULL; break; 2985 } 2986 return rv; 2987 } 2988 2989 static void* 2990 __cint_maddr__cprimod_cpri_rx_gcw_config_t(void* p, int mnum, cint_struct_type_t* parent) 2991 { 2992 void* rv; 2993 cprimod_cpri_rx_gcw_config_t* s = (cprimod_cpri_rx_gcw_config_t*) p; 2994 switch(mnum) 2995 { 2996 case 0: rv = &(s->Ns);break; 2997 case 1: rv = &(s->Xs);break; 2998 case 2: rv = &(s->Y);break; 2999 case 3: rv = &(s->mask);break; 3000 case 4: rv = &(s->filter_mode);break; 3001 case 5: rv = &(s->hyper_frame_index);break; 3002 case 6: rv = &(s->hyper_frame_modulo);break; 3003 case 7: rv = &(s->match_mask);break; 3004 case 8: rv = &(s->match_value);break; 3005 default: rv = NULL; break; 3006 } 3007 return rv; 3008 } 3009 3010 static void* 3011 __cint_maddr__cprimod_cpri_tx_gcw_config_t(void* p, int mnum, cint_struct_type_t* parent) 3012 { 3013 void* rv; 3014 cprimod_cpri_tx_gcw_config_t* s = (cprimod_cpri_tx_gcw_config_t*) p; 3015 switch(mnum) 3016 { 3017 case 0: rv = &(s->Ns);break; 3018 case 1: rv = &(s->Xs);break; 3019 case 2: rv = &(s->Y);break; 3020 case 3: rv = &(s->mask);break; 3021 case 4: rv = &(s->hyper_frame_index);break; 3022 case 5: rv = &(s->hyper_frame_modulo);break; 3023 case 6: rv = &(s->repeat_enable);break; 3024 case 7: rv = &(s->bfn0_filter_enable);break; 3025 case 8: rv = &(s->bfn1_filter_enable);break; 3026 default: rv = NULL; break; 3027 } 3028 return rv; 3029 } 3030 3031 static void* 3032 __cint_maddr__cprimod_cpri_tx_control_word_t(void* p, int mnum, cint_struct_type_t* parent) 3033 { 3034 void* rv; 3035 cprimod_cpri_tx_control_word_t* s = (cprimod_cpri_tx_control_word_t*) p; 3036 switch(mnum) 3037 { 3038 case 0: rv = &(s->enet_ptr);break; 3039 case 1: rv = &(s->l1_fun);break; 3040 case 2: rv = &(s->hdlc_rate);break; 3041 case 3: rv = &(s->protocol_ver);break; 3042 default: rv = NULL; break; 3043 } 3044 return rv; 3045 } 3046 3047 static void* 3048 __cint_maddr__cprimod_control_flow_config_t(void* p, int mnum, cint_struct_type_t* parent) 3049 { 3050 void* rv; 3051 cprimod_control_flow_config_t* s = (cprimod_control_flow_config_t*) p; 3052 switch(mnum) 3053 { 3054 case 0: rv = &(s->proc_type);break; 3055 case 1: rv = &(s->queue_num);break; 3056 case 2: rv = &(s->sync_profile);break; 3057 case 3: rv = &(s->sync_enable);break; 3058 default: rv = NULL; break; 3059 } 3060 return rv; 3061 } 3062 3063 static void* 3064 __cint_maddr__cprimod_sync_profile_entry_t(void* p, int mnum, cint_struct_type_t* parent) 3065 { 3066 void* rv; 3067 cprimod_sync_profile_entry_t* s = (cprimod_sync_profile_entry_t*) p; 3068 switch(mnum) 3069 { 3070 case 0: rv = &(s->count_cycle);break; 3071 case 1: rv = &(s->message_offset);break; 3072 case 2: rv = &(s->master_frame_offset);break; 3073 default: rv = NULL; break; 3074 } 3075 return rv; 3076 } 3077 3078 static void* 3079 __cint_maddr__cprimod_rsvd4_tx_config_info_t(void* p, int mnum, cint_struct_type_t* parent) 3080 { 3081 void* rv; 3082 cprimod_rsvd4_tx_config_info_t* s = (cprimod_rsvd4_tx_config_info_t*) p; 3083 switch(mnum) 3084 { 3085 case 0: rv = &(s->proc_type);break; 3086 case 1: rv = &(s->queue_num);break; 3087 case 2: rv = &(s->crc_mode);break; 3088 default: rv = NULL; break; 3089 } 3090 return rv; 3091 } 3092 3093 static void* 3094 __cint_maddr__cprimod_interrupt_callback_entry_t(void* p, int mnum, cint_struct_type_t* parent) 3095 { 3096 void* rv; 3097 cprimod_interrupt_callback_entry_t* s = (cprimod_interrupt_callback_entry_t*) p; 3098 switch(mnum) 3099 { 3100 case 0: rv = &(s->cb_func);break; 3101 case 1: rv = &(s->cb_data);break; 3102 default: rv = NULL; break; 3103 } 3104 return rv; 3105 } 3106 3107 static void* 3108 __cint_maddr__cprimod_1588_capture_config_t(void* p, int mnum, cint_struct_type_t* parent) 3109 { 3110 void* rv; 3111 cprimod_1588_capture_config_t* s = (cprimod_1588_capture_config_t*) p; 3112 switch(mnum) 3113 { 3114 case 0: rv = &(s->mode);break; 3115 case 1: rv = &(s->capture_bfn_num);break; 3116 case 2: rv = &(s->capture_hfn_num);break; 3117 default: rv = NULL; break; 3118 } 3119 return rv; 3120 } 3121 3122 static void* 3123 __cint_maddr__cprimod_1588_time_t(void* p, int mnum, cint_struct_type_t* parent) 3124 { 3125 void* rv; 3126 cprimod_1588_time_t* s = (cprimod_1588_time_t*) p; 3127 switch(mnum) 3128 { 3129 case 0: rv = &(s->nano_sec);break; 3130 case 1: rv = &(s->sub_nano_sec);break; 3131 case 2: rv = &(s->sign_bit);break; 3132 default: rv = NULL; break; 3133 } 3134 return rv; 3135 } 3136 3137 static void* 3138 __cint_maddr__cprimod_encap_presentation_time_config_t(void* p, int mnum, cint_struct_type_t* parent) 3139 { 3140 void* rv; 3141 cprimod_encap_presentation_time_config_t* s = (cprimod_encap_presentation_time_config_t*) p; 3142 switch(mnum) 3143 { 3144 case 0: rv = &(s->mod_count);break; 3145 case 1: rv = &(s->frame_sync_mode);break; 3146 case 2: rv = &(s->radio_frame_offset);break; 3147 case 3: rv = &(s->hyper_frame_offset);break; 3148 case 4: rv = &(s->approx_inc_disable);break; 3149 default: rv = NULL; break; 3150 } 3151 return rv; 3152 } 3153 3154 static void* 3155 __cint_maddr__cprimod_decap_agnostic_mode_config_t(void* p, int mnum, cint_struct_type_t* parent) 3156 { 3157 void* rv; 3158 cprimod_decap_agnostic_mode_config_t* s = (cprimod_decap_agnostic_mode_config_t*) p; 3159 switch(mnum) 3160 { 3161 case 0: rv = &(s->mod_count);break; 3162 case 1: rv = &(s->packet_size);break; 3163 case 2: rv = &(s->queue_num);break; 3164 default: rv = NULL; break; 3165 } 3166 return rv; 3167 } 3168 3169 static void* 3170 __cint_maddr__cprimod_fec_timestamp_config_t(void* p, int mnum, cint_struct_type_t* parent) 3171 { 3172 void* rv; 3173 cprimod_fec_timestamp_config_t* s = (cprimod_fec_timestamp_config_t*) p; 3174 switch(mnum) 3175 { 3176 case 0: rv = &(s->enable);break; 3177 case 1: rv = &(s->fec_fifo_ts_source_select);break; 3178 case 2: rv = &(s->fec_cmic_ts_source_select);break; 3179 case 3: rv = &(s->control_bit_offset_0);break; 3180 case 4: rv = &(s->control_bit_offset_1);break; 3181 case 5: rv = &(s->control_bit_offset_2);break; 3182 case 6: rv = &(s->control_bit_offset_3);break; 3183 default: rv = NULL; break; 3184 } 3185 return rv; 3186 } 3187 3188 #ifdef CPRIMOD_SUPPORT 3189 static void* 3190 __cint_maddr__cprimod_cpri_ecc_intr_info_t(void* p, int mnum, cint_struct_type_t* parent) 3191 { 3192 void* rv; 3193 cprimod_cpri_ecc_intr_info_t* s = (cprimod_cpri_ecc_intr_info_t*) p; 3194 switch(mnum) 3195 { 3196 case 0: rv = &(s->port);break; 3197 case 1: rv = &(s->err_mem_info);break; 3198 case 2: rv = &(s->ecc_reg_info);break; 3199 case 3: rv = &(s->ecc_num_bits_err);break; 3200 case 4: rv = &(s->err_addr);break; 3201 case 5: rv = &(s->mem_str);break; 3202 default: rv = NULL; break; 3203 } 3204 return rv; 3205 } 3206 3207 #endif /* CPRIMOD_SUPPORT */ 3208 #ifdef CPRIMOD_SUPPORT 3209 static void* 3210 __cint_maddr__cprimod_cpri_encap_header_field_mapping_t(void* p, int mnum, cint_struct_type_t* parent) 3211 { 3212 void* rv; 3213 cprimod_cpri_encap_header_field_mapping_t* s = (cprimod_cpri_encap_header_field_mapping_t*) p; 3214 switch(mnum) 3215 { 3216 case 0: rv = &(s->hdr_byte0_sel);break; 3217 case 1: rv = &(s->hdr_byte1_sel);break; 3218 case 2: rv = &(s->hdr_byte2_sel);break; 3219 case 3: rv = &(s->hdr_byte3_sel);break; 3220 case 4: rv = &(s->hdr_byte4_sel);break; 3221 case 5: rv = &(s->hdr_byte5_sel);break; 3222 case 6: rv = &(s->hdr_byte6_sel);break; 3223 case 7: rv = &(s->hdr_byte7_sel);break; 3224 case 8: rv = &(s->hdr_byte8_sel);break; 3225 case 9: rv = &(s->hdr_byte9_sel);break; 3226 case 10: rv = &(s->hdr_byte10_sel);break; 3227 case 11: rv = &(s->hdr_byte11_sel);break; 3228 default: rv = NULL; break; 3229 } 3230 return rv; 3231 } 3232 3233 #endif /* CPRIMOD_SUPPORT */ 3234 #ifdef CPRIMOD_SUPPORT 3235 static void* 3236 __cint_maddr__cprimod_cpri_decap_header_field_mapping_t(void* p, int mnum, cint_struct_type_t* parent) 3237 { 3238 void* rv; 3239 cprimod_cpri_decap_header_field_mapping_t* s = (cprimod_cpri_decap_header_field_mapping_t*) p; 3240 switch(mnum) 3241 { 3242 case 0: rv = &(s->subtype_sel);break; 3243 case 1: rv = &(s->flowid_sel);break; 3244 case 2: rv = &(s->length_15_8_sel);break; 3245 case 3: rv = &(s->length_7_0_sel);break; 3246 case 4: rv = &(s->orderinginfo_31_24_sel);break; 3247 case 5: rv = &(s->orderinginfo_23_16_sel);break; 3248 case 6: rv = &(s->orderinginfo_15_8_sel);break; 3249 case 7: rv = &(s->orderinginfo_7_0_sel);break; 3250 default: rv = NULL; break; 3251 } 3252 return rv; 3253 } 3254 3255 #endif /* CPRIMOD_SUPPORT */ 3256 3257 static cint_parameter_desc_t __cint_struct_members__cprimod_basic_frame_usage_entry_t[] = 3258 { 3259 {"uint32", "axc_id", 0, 0}, 3260 {"uint32", "start_bit", 0, 0}, 3261 {"uint32", "num_bits", 0, 0}, 3262 { NULL } 3263 }; 3264 3265 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_container_config_t[] = 3266 { 3267 {"cprimod_cpri_frame_map_method_t", "map_method", 0, 0}, 3268 {"uint32", "Naxc", 0, 0}, 3269 {"uint32", "K", 0, 0}, 3270 {"uint32", "Nst", 0, 0}, 3271 {"uint32", "Na", 0, 0}, 3272 {"uint32", "Nc", 0, 0}, 3273 {"uint32", "Nv", 0, 0}, 3274 {"cprimod_cpri_frame_sync_mode_t", "frame_sync_mode", 0, 0}, 3275 {"uint32", "basic_frame_offset", 0, 0}, 3276 {"uint32", "radio_frame_offset", 0, 0}, 3277 {"uint32", "hyper_frame_offset", 0, 0}, 3278 {"uint32", "cblk_cnt", 0, 0}, 3279 { NULL } 3280 }; 3281 3282 static cint_parameter_desc_t __cint_struct_members__cprimod_rsvd4_container_config_t[] = 3283 { 3284 {"uint32", "axc_id", 0, 0}, 3285 {"uint32", "stuffing_cnt", 0, 0}, 3286 {"cprimod_rsvd4_msg_ts_mode_t", "msg_ts_mode", 0, 0}, 3287 {"uint32", "msg_ts_cnt", 0, 0}, 3288 {"cprimod_rsvd4_frame_sync_mode_t", "frame_sync_mode", 0, 0}, 3289 {"uint32", "master_frame_offset", 0, 0}, 3290 {"uint32", "message_number_offset", 0, 0}, 3291 {"uint32", "container_block_cnt", 0, 0}, 3292 {"uint32", "use_ts_dbm", 0, 0}, 3293 {"uint32", "ts_dbm_prof_num", 0, 0}, 3294 {"uint32", "num_active_slots", 0, 0}, 3295 {"uint32", "msg_addr", 0, 0}, 3296 {"uint32", "msg_type", 0, 0}, 3297 {"uint32", "msg_ts_offset", 0, 0}, 3298 { NULL } 3299 }; 3300 3301 static cint_parameter_desc_t __cint_struct_members__cprimod_payload_size_info_t[] = 3302 { 3303 {"uint32", "packet_size", 0, 0}, 3304 {"uint32", "last_packet_num", 0, 0}, 3305 {"uint32", "last_packet_size", 0, 0}, 3306 { NULL } 3307 }; 3308 3309 static cint_parameter_desc_t __cint_struct_members__cprimod_encap_decap_data_config_t[] = 3310 { 3311 {"uint32", "sample_size", 0, 0}, 3312 {"uint32", "truncation_enable", 0, 0}, 3313 {"cprimod_truncation_type_t", "truncation_type", 0, 0}, 3314 {"cprimod_compression_type_t", "compression_type", 0, 0}, 3315 {"uint32", "mux_enable", 0, 0}, 3316 {"uint32", "bit_reversal", 0, 0}, 3317 {"uint32", "buffer_size", 0, 0}, 3318 {"uint32", "priority", 0, 0}, 3319 {"uint32", "cycle_size", 0, 0}, 3320 {"int", "is_agnostic", 0, 0}, 3321 { NULL } 3322 }; 3323 3324 static cint_parameter_desc_t __cint_struct_members__cprimod_rsvd4_encap_data_config_t[] = 3325 { 3326 {"uint32", "buffer_size", 0, 0}, 3327 {"uint32", "priority", 0, 0}, 3328 {"uint32", "gsm_pad_size", 0, 0}, 3329 {"uint32", "gsm_extra_pad_size", 0, 0}, 3330 {"uint32", "gsm_pad_enable", 0, 0}, 3331 {"uint32", "gsm_control_location", 0, 0}, 3332 {"uint32", "bit_reversal", 0, 0}, 3333 { NULL } 3334 }; 3335 3336 static cint_parameter_desc_t __cint_struct_members__cprimod_rsvd4_decap_data_config_t[] = 3337 { 3338 {"uint32", "buffer_size", 0, 0}, 3339 {"uint32", "cycle_size", 0, 0}, 3340 {"uint32", "gsm_pad_size", 0, 0}, 3341 {"uint32", "gsm_extra_pad_size", 0, 0}, 3342 {"uint32", "gsm_pad_enable", 0, 0}, 3343 {"uint32", "gsm_control_location", 0, 0}, 3344 {"uint32", "bit_reversal", 0, 0}, 3345 { NULL } 3346 }; 3347 3348 static cint_parameter_desc_t __cint_struct_members__cprimod_encap_header_config_t[] = 3349 { 3350 {"cprimod_hdr_encap_type_t", "header_type", 0, 0}, 3351 {"uint32", "flow_id", 0, 0}, 3352 {"uint32", "roe_subtype", 0, 0}, 3353 {"uint32", "ordering_info_index", 0, 0}, 3354 {"uint32", "mac_da_index", 0, 0}, 3355 {"uint32", "mac_sa_index", 0, 0}, 3356 {"cprimod_hdr_vlan_type_t", "vlan_type", 0, 0}, 3357 {"uint32", "vlan_id_0_index", 0, 0}, 3358 {"uint32", "vlan_id_1_index", 0, 0}, 3359 {"uint32", "vlan_0_priority", 0, 0}, 3360 {"uint32", "vlan_1_priority", 0, 0}, 3361 {"uint32", "vlan_eth_type_index", 0, 0}, 3362 {"uint32", "use_tagid_for_vlan", 0, 0}, 3363 {"uint32", "use_tagid_for_flowid", 0, 0}, 3364 {"uint32", "use_opcode", 0, 0}, 3365 {"uint32", "roe_opcode", 0, 0}, 3366 {"uint8", "version", 0, 0}, 3367 {"cprimod_cpri_roe_frame_format_t", "roe_frame_format", 0, 0}, 3368 {"uint32", "ecpri_pc_id", 0, 0}, 3369 {"uint32", "ecpri_msg_type", 0, 0}, 3370 { NULL } 3371 }; 3372 3373 static cint_parameter_desc_t __cint_struct_members__cprimod_encap_ordering_info_entry_t[] = 3374 { 3375 {"cprimod_ordering_info_type_t", "type", 0, 0}, 3376 {"cprimod_ordering_info_prop_t", "pcnt_prop", 0, 0}, 3377 {"uint32", "pcnt_size", 0, 0}, 3378 {"uint32", "pcnt_increment", 0, 0}, 3379 {"uint32", "pcnt_max", 0, 0}, 3380 {"cprimod_ordering_info_prop_t", "qcnt_prop", 0, 0}, 3381 {"uint32", "qcnt_size", 0, 0}, 3382 {"uint32", "qcnt_increment", 0, 0}, 3383 {"uint32", "qcnt_max", 0, 0}, 3384 {"uint32", "seq_reserve_value", 0, 0}, 3385 { NULL } 3386 }; 3387 3388 static cint_parameter_desc_t __cint_struct_members__cprimod_decap_ordering_info_entry_t[] = 3389 { 3390 {"cprimod_ordering_info_type_t", "type", 0, 0}, 3391 {"uint32", "pcnt_extended", 0, 0}, 3392 {"uint32", "pcnt_pkt_count", 0, 0}, 3393 {"uint32", "pcnt_size", 0, 0}, 3394 {"uint32", "pcnt_increment", 0, 0}, 3395 {"uint32", "pcnt_max", 0, 0}, 3396 {"uint32", "pcnt_bias", 0, 0}, 3397 {"uint32", "pcnt_increment_p2", 0, 0}, 3398 {"uint32", "qcnt_size", 0, 0}, 3399 {"uint32", "qcnt_increment", 0, 0}, 3400 {"uint32", "qcnt_max", 0, 0}, 3401 {"uint32", "qcnt_bias", 0, 0}, 3402 {"uint32", "qcnt_increment_p2", 0, 0}, 3403 {"uint32", "modulo_2", 0, 0}, 3404 {"uint32", "gsm_tsn_bitmap", 0, 0}, 3405 {"uint32", "seq_reserve_value", 0, 0}, 3406 { NULL } 3407 }; 3408 3409 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_ordering_info_offset_t[] = 3410 { 3411 {"uint32", "p_size", 0, 0}, 3412 {"uint32", "p_offset", 0, 0}, 3413 {"uint32", "q_size", 0, 0}, 3414 {"uint32", "q_offset", 0, 0}, 3415 { NULL } 3416 }; 3417 3418 static cint_parameter_desc_t __cint_struct_members__cprimod_header_compare_entry_t[] = 3419 { 3420 {"uint8", "valid", 0, 0}, 3421 {"uint32", "match_data", 0, 0}, 3422 {"uint32", "mask", 0, 0}, 3423 {"uint8", "flow_id", 0, 0}, 3424 {"cprimod_flow_type_t", "flow_type", 0, 0}, 3425 { NULL } 3426 }; 3427 3428 static cint_parameter_desc_t __cint_struct_members__cprimod_modulo_rule_entry_t[] = 3429 { 3430 {"uint8", "active", 0, 0}, 3431 {"cprimod_modulo_rule_mod_t", "modulo_value", 0, 0}, 3432 {"uint8", "modulo_index", 0, 0}, 3433 {"uint8", "dbm_enable", 0, 0}, 3434 {"uint8", "flow_dbm_id", 0, 0}, 3435 {"cprimod_flow_type_t", "flow_type", 0, 0}, 3436 { NULL } 3437 }; 3438 3439 static cint_parameter_desc_t __cint_struct_members__cprimod_dbm_rule_entry_t[] = 3440 { 3441 {"uint8", "bm1_mult", 0, 0}, 3442 {"uint32", "bm1", 0, 3}, 3443 {"uint8", "bm1_size", 0, 0}, 3444 {"uint32", "bm2", 0, 2}, 3445 {"uint8", "bm2_size", 0, 0}, 3446 {"uint8", "num_slots", 0, 0}, 3447 {"cprimod_dbm_rule_pos_index_t", "pos_grp_index", 0, 0}, 3448 {"cprimod_dbm_rule_pos_grp_size_t", "pos_grp_size", 0, 0}, 3449 { NULL } 3450 }; 3451 3452 static cint_parameter_desc_t __cint_struct_members__cprimod_secondary_dbm_rule_entry_t[] = 3453 { 3454 {"uint8", "bm1_mult", 0, 0}, 3455 {"uint8", "bm1", 0, 0}, 3456 {"uint8", "bm1_size", 0, 0}, 3457 {"uint8", "bm2", 0, 0}, 3458 {"uint8", "bm2_size", 0, 0}, 3459 {"uint8", "num_slots", 0, 0}, 3460 { NULL } 3461 }; 3462 3463 static cint_parameter_desc_t __cint_struct_members__cprimod_dbm_pos_table_entry_t[] = 3464 { 3465 {"uint8", "valid", 0, 0}, 3466 {"uint8", "flow_id", 0, 0}, 3467 {"cprimod_flow_type_t", "flow_type", 0, 0}, 3468 {"uint8", "index", 0, 0}, 3469 { NULL } 3470 }; 3471 3472 static cint_parameter_desc_t __cint_struct_members__cprimod_port_interface_config_t[] = 3473 { 3474 {"cprimod_port_speed_t", "speed", 0, 0}, 3475 {"cprimod_port_interface_type_t", "interface", 0, 0}, 3476 { NULL } 3477 }; 3478 3479 static cint_parameter_desc_t __cint_struct_members__cprimod_port_rsvd4_config_t[] = 3480 { 3481 {"cprimod_port_rsvd4_speed_mult_t", "speed", 0, 0}, 3482 {"cprimod_port_interface_type_t", "interface", 0, 0}, 3483 { NULL } 3484 }; 3485 3486 static cint_parameter_desc_t __cint_struct_members__cprimod_polarity_t[] = 3487 { 3488 {"uint32_t", "rx_polarity", 0, 0}, 3489 {"uint32_t", "tx_polarity", 0, 0}, 3490 { NULL } 3491 }; 3492 3493 static cint_parameter_desc_t __cint_struct_members__cprimod_lane_map_t[] = 3494 { 3495 {"uint32_t", "num_of_lanes", 0, 0}, 3496 {"uint32_t", "lane_map_rx", 0, CPRIMOD_MAX_LANES_PER_CORE}, 3497 {"uint32_t", "lane_map_tx", 0, CPRIMOD_MAX_LANES_PER_CORE}, 3498 { NULL } 3499 }; 3500 3501 static cint_parameter_desc_t __cint_struct_members__cprimod_firmware_core_config_t[] = 3502 { 3503 {"uint32_t", "CoreConfigFromPCS", 0, 0}, 3504 {"uint32_t", "VcoRate", 0, 0}, 3505 {"uint32_t", "disable_write_pll_iqp", 0, 0}, 3506 { NULL } 3507 }; 3508 3509 static cint_parameter_desc_t __cint_struct_members__cprimod_afe_pll_t[] = 3510 { 3511 {"uint32_t", "afe_pll_change_default", 0, 0}, 3512 {"uint32_t", "ams_pll_iqp", 0, 0}, 3513 {"uint32_t", "ams_pll_en_hrz", 0, 0}, 3514 { NULL } 3515 }; 3516 3517 static cint_parameter_desc_t __cint_struct_members__cprimod_pll_parm_t[] = 3518 { 3519 {"uint32_t", "change_pll", 0, 0}, 3520 {"uint32_t", "vcoRate", 0, 0}, 3521 {"int", "div2", 0, 0}, 3522 {"int", "div4", 0, 0}, 3523 {"cprimod_afe_pll_t", "afe_pll", 0, 0}, 3524 { NULL } 3525 }; 3526 3527 static cint_parameter_desc_t __cint_struct_members__cprimod_core_init_config_t[] = 3528 { 3529 {"cprimod_lane_map_t", "lane_map", 0, 0}, 3530 {"cprimod_firmware_load_method_t", "firmware_load_method", 0, 0}, 3531 {"cprimod_firmware_loader_f", "firmware_loader", 0, 0}, 3532 {"cprimod_firmware_core_config_t", "firmware_core_config", 0, 0}, 3533 {"uint32_t", "flags", 0, 0}, 3534 {"cprimod_tx_input_voltage_t", "tx_input_voltage", 0, 0}, 3535 {"cprimod_pll_parm_t", "pll0", 0, 0}, 3536 {"cprimod_pll_parm_t", "pll1", 0, 0}, 3537 {"uint8_t", "trcvr_host_managed", 0, 0}, 3538 { NULL } 3539 }; 3540 3541 static cint_parameter_desc_t __cint_struct_members__cprimod_core_status_t[] = 3542 { 3543 {"uint32_t", "pmd_active", 0, 0}, 3544 { NULL } 3545 }; 3546 3547 static cint_parameter_desc_t __cint_struct_members__cprimod_port_init_config_t[] = 3548 { 3549 {"int", "polarity_rx", 0, 0}, 3550 {"int", "polarity_tx", 0, 0}, 3551 {"cprimod_port_interface_type_t", "interface", 0, 0}, 3552 {"cprimod_port_speed_t", "tx_cpri_speed", 0, 0}, 3553 {"cprimod_port_speed_t", "rx_cpri_speed", 0, 0}, 3554 {"cprimod_port_rsvd4_speed_mult_t", "tx_rsvd4_speed", 0, 0}, 3555 {"cprimod_port_rsvd4_speed_mult_t", "rx_rsvd4_speed", 0, 0}, 3556 {"int", "roe_stuffing_bit", 0, 0}, 3557 {"int", "roe_reserved_bit", 0, 0}, 3558 {"uint32", "serdes_scrambler_seed", 0, 0}, 3559 {"uint32", "serdes_scrambler_enable", 0, 0}, 3560 {"int", "mix_cpri_enet", 0, 0}, 3561 {"int", "vco_for_lane", 0, 0}, 3562 {"cprimod_pll_num_in_use_t", "pll_in_use", 0, 0}, 3563 {"phymod_tx_t", "tx_params", 0, PHYMOD_MAX_LANES_PER_PORT}, 3564 {"int", "tx_params_user_config", 0, 0}, 3565 {"int", "parity_enable", 0, 0}, 3566 { NULL } 3567 }; 3568 3569 static cint_parameter_desc_t __cint_struct_members__cprimod_slow_hdlc_config_info_t[] = 3570 { 3571 {"cprimod_cpri_crc_mode_t", "tx_crc_mode", 0, 0}, 3572 {"cprimod_cpri_hdlc_num_flag_bytes_t", "tx_flag_size", 0, 0}, 3573 {"cprimod_cpri_hdlc_filling_flag_pattern_t", "tx_filling_flag_pattern", 0, 0}, 3574 {"cprimod_cpri_hdlc_crc_init_val_t", "crc_init_val", 0, 0}, 3575 {"int", "use_fe_mac", 0, 0}, 3576 {"int", "crc_byte_swap", 0, 0}, 3577 {"int", "no_fcs_err_check", 0, 0}, 3578 {"uint32", "cw_sel", 0, 0}, 3579 {"uint32", "cw_size", 0, 0}, 3580 {"cprimod_cpri_hdlc_fcs_size_t", "fcs_size", 0, 0}, 3581 {"int", "runt_frame_drop", 0, 0}, 3582 {"int", "long_frame_drop", 0, 0}, 3583 {"uint32", "min_frame_size", 0, 0}, 3584 {"uint32", "max_frame_size", 0, 0}, 3585 {"uint32", "queue_num", 0, 0}, 3586 { NULL } 3587 }; 3588 3589 static cint_parameter_desc_t __cint_struct_members__cprimod_fast_eth_config_info_t[] = 3590 { 3591 {"cprimod_cpri_crc_mode_t", "tx_crc_mode", 0, 0}, 3592 {"uint32", "schan_start", 0, 0}, 3593 {"uint32", "schan_size", 0, 0}, 3594 {"uint32", "cw_sel", 0, 0}, 3595 {"uint32", "cw_size", 0, 0}, 3596 {"uint32", "min_packet_size", 0, 0}, 3597 {"uint32", "max_packet_size", 0, 0}, 3598 {"int", "min_packet_drop", 0, 0}, 3599 {"int", "max_packet_drop", 0, 0}, 3600 {"int", "strip_crc", 0, 0}, 3601 {"uint32", "min_ipg", 0, 0}, 3602 {"uint32", "queue_num", 0, 0}, 3603 {"int", "no_fcs_err_check", 0, 0}, 3604 { NULL } 3605 }; 3606 3607 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_rx_vsd_config_info_t[] = 3608 { 3609 {"uint32", "subchan_start", 0, 0}, 3610 {"cprimod_cpri_vsd_control_subchan_size_t", "subchan_size", 0, 0}, 3611 {"cprimod_cpri_vsd_control_subchan_num_bytes_t", "subchan_bytes", 0, 0}, 3612 {"uint32", "subchan_steps", 0, 0}, 3613 {"cprimod_cpri_vsd_control_flow_num_bytes_t", "flow_bytes", 0, 0}, 3614 {"uint32", "queue_num", 0, 0}, 3615 {"uint32", "rsvd_sector_mask", 0, 4}, 3616 { NULL } 3617 }; 3618 3619 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t[] = 3620 { 3621 {"uint32", "hyper_frame_number", 0, 0}, 3622 {"uint32", "hyper_frame_modulo", 0, 0}, 3623 {"int", "filter_zero_data", 0, 0}, 3624 {"uint32", "section_num", 0, 4}, 3625 {"uint32", "num_sector", 0, 0}, 3626 {"uint32", "tag_id", 0, 0}, 3627 { NULL } 3628 }; 3629 3630 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_tx_vsd_config_info_t[] = 3631 { 3632 {"uint32", "subchan_start", 0, 0}, 3633 {"cprimod_cpri_vsd_control_subchan_size_t", "subchan_size", 0, 0}, 3634 {"cprimod_cpri_vsd_control_subchan_num_bytes_t", "subchan_bytes", 0, 0}, 3635 {"uint32", "subchan_steps", 0, 0}, 3636 {"cprimod_cpri_vsd_control_flow_num_bytes_t", "flow_bytes", 0, 0}, 3637 {"uint32", "queue_num", 0, 0}, 3638 {"uint32", "rsvd_sector_mask", 0, 4}, 3639 {"int", "byte_order_swap", 0, 0}, 3640 { NULL } 3641 }; 3642 3643 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_tx_vsd_flow_config_info_t[] = 3644 { 3645 {"uint32", "hyper_frame_number", 0, 0}, 3646 {"uint32", "hyper_frame_modulo", 0, 0}, 3647 {"int", "repeat_mode", 0, 0}, 3648 {"uint32", "section_num", 0, 4}, 3649 {"uint32", "num_sector", 0, 0}, 3650 { NULL } 3651 }; 3652 3653 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_rx_vsd_raw_config_t[] = 3654 { 3655 {"uint32", "schan_start", 0, 0}, 3656 {"uint32", "schan_size", 0, 0}, 3657 {"uint32", "cw_sel", 0, 0}, 3658 {"uint32", "cw_size", 0, 0}, 3659 {"cprimod_cpri_cw_filter_mode_t", "filter_mode", 0, 0}, 3660 {"uint32", "hyper_frame_index", 0, 0}, 3661 {"uint32", "hyper_frame_modulo", 0, 0}, 3662 {"uint32", "match_offset", 0, 0}, 3663 {"uint32", "match_value", 0, 0}, 3664 {"uint32", "match_mask", 0, 0}, 3665 {"uint32", "queue_num", 0, 0}, 3666 { NULL } 3667 }; 3668 3669 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_tx_vsd_raw_config_t[] = 3670 { 3671 {"uint32", "schan_start", 0, 0}, 3672 {"uint32", "schan_size", 0, 0}, 3673 {"uint32", "cw_sel", 0, 0}, 3674 {"uint32", "cw_size", 0, 0}, 3675 {"uint32", "hyper_frame_index", 0, 0}, 3676 {"uint32", "hyper_frame_modulo", 0, 0}, 3677 {"uint32", "queue_num", 0, 0}, 3678 {"cprimod_cpri_vsd_raw_map_mode_t", "map_mode", 0, 0}, 3679 {"int", "repeat_enable", 0, 0}, 3680 {"int", "bfn0_filter_enable", 0, 0}, 3681 {"int", "bfn1_filter_enable", 0, 0}, 3682 {"uint32", "idle_value", 0, 0}, 3683 { NULL } 3684 }; 3685 3686 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_rx_gcw_config_t[] = 3687 { 3688 {"uint32", "Ns", 0, 0}, 3689 {"uint32", "Xs", 0, 0}, 3690 {"uint32", "Y", 0, 0}, 3691 {"cprimod_cpri_gcw_mask_t", "mask", 0, 0}, 3692 {"cprimod_cpri_cw_filter_mode_t", "filter_mode", 0, 0}, 3693 {"uint32", "hyper_frame_index", 0, 0}, 3694 {"uint32", "hyper_frame_modulo", 0, 0}, 3695 {"uint32", "match_mask", 0, 0}, 3696 {"uint32", "match_value", 0, 0}, 3697 { NULL } 3698 }; 3699 3700 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_tx_gcw_config_t[] = 3701 { 3702 {"uint32", "Ns", 0, 0}, 3703 {"uint32", "Xs", 0, 0}, 3704 {"uint32", "Y", 0, 0}, 3705 {"cprimod_cpri_gcw_mask_t", "mask", 0, 0}, 3706 {"uint32", "hyper_frame_index", 0, 0}, 3707 {"uint32", "hyper_frame_modulo", 0, 0}, 3708 {"int", "repeat_enable", 0, 0}, 3709 {"int", "bfn0_filter_enable", 0, 0}, 3710 {"int", "bfn1_filter_enable", 0, 0}, 3711 { NULL } 3712 }; 3713 3714 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_tx_control_word_t[] = 3715 { 3716 {"uint32", "enet_ptr", 0, 0}, 3717 {"uint32", "l1_fun", 0, 0}, 3718 {"uint32", "hdlc_rate", 0, 0}, 3719 {"uint32", "protocol_ver", 0, 0}, 3720 { NULL } 3721 }; 3722 3723 static cint_parameter_desc_t __cint_struct_members__cprimod_control_flow_config_t[] = 3724 { 3725 {"cprimod_control_msg_proc_type_t", "proc_type", 0, 0}, 3726 {"uint32", "queue_num", 0, 0}, 3727 {"uint32", "sync_profile", 0, 0}, 3728 {"int", "sync_enable", 0, 0}, 3729 { NULL } 3730 }; 3731 3732 static cint_parameter_desc_t __cint_struct_members__cprimod_sync_profile_entry_t[] = 3733 { 3734 {"cprimod_sync_count_cycle_t", "count_cycle", 0, 0}, 3735 {"uint32", "message_offset", 0, 0}, 3736 {"uint32", "master_frame_offset", 0, 0}, 3737 { NULL } 3738 }; 3739 3740 static cint_parameter_desc_t __cint_struct_members__cprimod_rsvd4_tx_config_info_t[] = 3741 { 3742 {"cprimod_control_msg_proc_type_t", "proc_type", 0, 0}, 3743 {"uint8", "queue_num", 0, 0}, 3744 {"uint8", "crc_mode", 0, 0}, 3745 { NULL } 3746 }; 3747 3748 static cint_parameter_desc_t __cint_struct_members__cprimod_interrupt_callback_entry_t[] = 3749 { 3750 {"cprimod_cpri_port_interrupt_callback_t", "cb_func", 0, 0}, 3751 {"void", "cb_data", 1, 0}, 3752 { NULL } 3753 }; 3754 3755 static cint_parameter_desc_t __cint_struct_members__cprimod_1588_capture_config_t[] = 3756 { 3757 {"cprimod_1588_capture_mode_t", "mode", 0, 0}, 3758 {"uint16", "capture_bfn_num", 0, 0}, 3759 {"uint8", "capture_hfn_num", 0, 0}, 3760 { NULL } 3761 }; 3762 3763 static cint_parameter_desc_t __cint_struct_members__cprimod_1588_time_t[] = 3764 { 3765 {"uint64", "nano_sec", 0, 0}, 3766 {"uint8", "sub_nano_sec", 0, 0}, 3767 {"uint8", "sign_bit", 0, 0}, 3768 { NULL } 3769 }; 3770 3771 static cint_parameter_desc_t __cint_struct_members__cprimod_encap_presentation_time_config_t[] = 3772 { 3773 {"uint32", "mod_count", 0, 0}, 3774 {"cprimod_cpri_frame_sync_mode_t", "frame_sync_mode", 0, 0}, 3775 {"uint32", "radio_frame_offset", 0, 0}, 3776 {"uint32", "hyper_frame_offset", 0, 0}, 3777 {"int", "approx_inc_disable", 0, 0}, 3778 { NULL } 3779 }; 3780 3781 static cint_parameter_desc_t __cint_struct_members__cprimod_decap_agnostic_mode_config_t[] = 3782 { 3783 {"uint32", "mod_count", 0, 0}, 3784 {"uint32", "packet_size", 0, 0}, 3785 {"uint32", "queue_num", 0, 0}, 3786 { NULL } 3787 }; 3788 3789 static cint_parameter_desc_t __cint_struct_members__cprimod_fec_timestamp_config_t[] = 3790 { 3791 {"int", "enable", 0, 0}, 3792 {"cprimod_fec_ts_source_t", "fec_fifo_ts_source_select", 0, 0}, 3793 {"cprimod_fec_ts_source_t", "fec_cmic_ts_source_select", 0, 0}, 3794 {"uint32", "control_bit_offset_0", 0, 0}, 3795 {"uint32", "control_bit_offset_1", 0, 0}, 3796 {"uint32", "control_bit_offset_2", 0, 0}, 3797 {"uint32", "control_bit_offset_3", 0, 0}, 3798 { NULL } 3799 }; 3800 3801 #ifdef CPRIMOD_SUPPORT 3802 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_ecc_intr_info_t[] = 3803 { 3804 {"int", "port", 0, 0}, 3805 {"soc_mem_t", "err_mem_info", 0, 0}, 3806 {"soc_reg_t", "ecc_reg_info", 0, 0}, 3807 {"int", "ecc_num_bits_err", 0, 0}, 3808 {"uint32", "err_addr", 0, 0}, 3809 {"char", "mem_str", 1, 0}, 3810 { NULL } 3811 }; 3812 3813 #endif /* CPRIMOD_SUPPORT */ 3814 #ifdef CPRIMOD_SUPPORT 3815 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_encap_header_field_mapping_t[] = 3816 { 3817 {"cprimod_cpri_roe_header_field_t", "hdr_byte0_sel", 0, 0}, 3818 {"cprimod_cpri_roe_header_field_t", "hdr_byte1_sel", 0, 0}, 3819 {"cprimod_cpri_roe_header_field_t", "hdr_byte2_sel", 0, 0}, 3820 {"cprimod_cpri_roe_header_field_t", "hdr_byte3_sel", 0, 0}, 3821 {"cprimod_cpri_roe_header_field_t", "hdr_byte4_sel", 0, 0}, 3822 {"cprimod_cpri_roe_header_field_t", "hdr_byte5_sel", 0, 0}, 3823 {"cprimod_cpri_roe_header_field_t", "hdr_byte6_sel", 0, 0}, 3824 {"cprimod_cpri_roe_header_field_t", "hdr_byte7_sel", 0, 0}, 3825 {"cprimod_cpri_roe_header_field_t", "hdr_byte8_sel", 0, 0}, 3826 {"cprimod_cpri_roe_header_field_t", "hdr_byte9_sel", 0, 0}, 3827 {"cprimod_cpri_roe_header_field_t", "hdr_byte10_sel", 0, 0}, 3828 {"cprimod_cpri_roe_header_field_t", "hdr_byte11_sel", 0, 0}, 3829 { NULL } 3830 }; 3831 3832 #endif /* CPRIMOD_SUPPORT */ 3833 #ifdef CPRIMOD_SUPPORT 3834 static cint_parameter_desc_t __cint_struct_members__cprimod_cpri_decap_header_field_mapping_t[] = 3835 { 3836 {"cprimod_cpri_ecpri_header_field_t", "subtype_sel", 0, 0}, 3837 {"cprimod_cpri_ecpri_header_field_t", "flowid_sel", 0, 0}, 3838 {"cprimod_cpri_ecpri_header_field_t", "length_15_8_sel", 0, 0}, 3839 {"cprimod_cpri_ecpri_header_field_t", "length_7_0_sel", 0, 0}, 3840 {"cprimod_cpri_ecpri_header_field_t", "orderinginfo_31_24_sel", 0, 0}, 3841 {"cprimod_cpri_ecpri_header_field_t", "orderinginfo_23_16_sel", 0, 0}, 3842 {"cprimod_cpri_ecpri_header_field_t", "orderinginfo_15_8_sel", 0, 0}, 3843 {"cprimod_cpri_ecpri_header_field_t", "orderinginfo_7_0_sel", 0, 0}, 3844 { NULL } 3845 }; 3846 3847 #endif /* CPRIMOD_SUPPORT */ 3848 3849 static cint_struct_type_t __cint_structures[] = 3850 { 3851 { 3852 "cprimod_basic_frame_usage_entry_t", 3853 sizeof(cprimod_basic_frame_usage_entry_t), 3854 __cint_struct_members__cprimod_basic_frame_usage_entry_t, 3855 __cint_maddr__cprimod_basic_frame_usage_entry_t 3856 }, 3857 { 3858 "cprimod_cpri_container_config_t", 3859 sizeof(cprimod_cpri_container_config_t), 3860 __cint_struct_members__cprimod_cpri_container_config_t, 3861 __cint_maddr__cprimod_cpri_container_config_t 3862 }, 3863 { 3864 "cprimod_rsvd4_container_config_t", 3865 sizeof(cprimod_rsvd4_container_config_t), 3866 __cint_struct_members__cprimod_rsvd4_container_config_t, 3867 __cint_maddr__cprimod_rsvd4_container_config_t 3868 }, 3869 { 3870 "cprimod_payload_size_info_t", 3871 sizeof(cprimod_payload_size_info_t), 3872 __cint_struct_members__cprimod_payload_size_info_t, 3873 __cint_maddr__cprimod_payload_size_info_t 3874 }, 3875 { 3876 "cprimod_encap_decap_data_config_t", 3877 sizeof(cprimod_encap_decap_data_config_t), 3878 __cint_struct_members__cprimod_encap_decap_data_config_t, 3879 __cint_maddr__cprimod_encap_decap_data_config_t 3880 }, 3881 { 3882 "cprimod_rsvd4_encap_data_config_t", 3883 sizeof(cprimod_rsvd4_encap_data_config_t), 3884 __cint_struct_members__cprimod_rsvd4_encap_data_config_t, 3885 __cint_maddr__cprimod_rsvd4_encap_data_config_t 3886 }, 3887 { 3888 "cprimod_rsvd4_decap_data_config_t", 3889 sizeof(cprimod_rsvd4_decap_data_config_t), 3890 __cint_struct_members__cprimod_rsvd4_decap_data_config_t, 3891 __cint_maddr__cprimod_rsvd4_decap_data_config_t 3892 }, 3893 { 3894 "cprimod_encap_header_config_t", 3895 sizeof(cprimod_encap_header_config_t), 3896 __cint_struct_members__cprimod_encap_header_config_t, 3897 __cint_maddr__cprimod_encap_header_config_t 3898 }, 3899 { 3900 "cprimod_encap_ordering_info_entry_t", 3901 sizeof(cprimod_encap_ordering_info_entry_t), 3902 __cint_struct_members__cprimod_encap_ordering_info_entry_t, 3903 __cint_maddr__cprimod_encap_ordering_info_entry_t 3904 }, 3905 { 3906 "cprimod_decap_ordering_info_entry_t", 3907 sizeof(cprimod_decap_ordering_info_entry_t), 3908 __cint_struct_members__cprimod_decap_ordering_info_entry_t, 3909 __cint_maddr__cprimod_decap_ordering_info_entry_t 3910 }, 3911 { 3912 "cprimod_cpri_ordering_info_offset_t", 3913 sizeof(cprimod_cpri_ordering_info_offset_t), 3914 __cint_struct_members__cprimod_cpri_ordering_info_offset_t, 3915 __cint_maddr__cprimod_cpri_ordering_info_offset_t 3916 }, 3917 { 3918 "cprimod_header_compare_entry_t", 3919 sizeof(cprimod_header_compare_entry_t), 3920 __cint_struct_members__cprimod_header_compare_entry_t, 3921 __cint_maddr__cprimod_header_compare_entry_t 3922 }, 3923 { 3924 "cprimod_modulo_rule_entry_t", 3925 sizeof(cprimod_modulo_rule_entry_t), 3926 __cint_struct_members__cprimod_modulo_rule_entry_t, 3927 __cint_maddr__cprimod_modulo_rule_entry_t 3928 }, 3929 { 3930 "cprimod_dbm_rule_entry_t", 3931 sizeof(cprimod_dbm_rule_entry_t), 3932 __cint_struct_members__cprimod_dbm_rule_entry_t, 3933 __cint_maddr__cprimod_dbm_rule_entry_t 3934 }, 3935 { 3936 "cprimod_secondary_dbm_rule_entry_t", 3937 sizeof(cprimod_secondary_dbm_rule_entry_t), 3938 __cint_struct_members__cprimod_secondary_dbm_rule_entry_t, 3939 __cint_maddr__cprimod_secondary_dbm_rule_entry_t 3940 }, 3941 { 3942 "cprimod_dbm_pos_table_entry_t", 3943 sizeof(cprimod_dbm_pos_table_entry_t), 3944 __cint_struct_members__cprimod_dbm_pos_table_entry_t, 3945 __cint_maddr__cprimod_dbm_pos_table_entry_t 3946 }, 3947 { 3948 "cprimod_port_interface_config_t", 3949 sizeof(cprimod_port_interface_config_t), 3950 __cint_struct_members__cprimod_port_interface_config_t, 3951 __cint_maddr__cprimod_port_interface_config_t 3952 }, 3953 { 3954 "cprimod_port_rsvd4_config_t", 3955 sizeof(cprimod_port_rsvd4_config_t), 3956 __cint_struct_members__cprimod_port_rsvd4_config_t, 3957 __cint_maddr__cprimod_port_rsvd4_config_t 3958 }, 3959 { 3960 "cprimod_polarity_t", 3961 sizeof(cprimod_polarity_t), 3962 __cint_struct_members__cprimod_polarity_t, 3963 __cint_maddr__cprimod_polarity_t 3964 }, 3965 { 3966 "cprimod_lane_map_t", 3967 sizeof(cprimod_lane_map_t), 3968 __cint_struct_members__cprimod_lane_map_t, 3969 __cint_maddr__cprimod_lane_map_t 3970 }, 3971 { 3972 "cprimod_firmware_core_config_t", 3973 sizeof(cprimod_firmware_core_config_t), 3974 __cint_struct_members__cprimod_firmware_core_config_t, 3975 __cint_maddr__cprimod_firmware_core_config_t 3976 }, 3977 { 3978 "cprimod_afe_pll_t", 3979 sizeof(cprimod_afe_pll_t), 3980 __cint_struct_members__cprimod_afe_pll_t, 3981 __cint_maddr__cprimod_afe_pll_t 3982 }, 3983 { 3984 "cprimod_pll_parm_t", 3985 sizeof(cprimod_pll_parm_t), 3986 __cint_struct_members__cprimod_pll_parm_t, 3987 __cint_maddr__cprimod_pll_parm_t 3988 }, 3989 { 3990 "cprimod_core_init_config_t", 3991 sizeof(cprimod_core_init_config_t), 3992 __cint_struct_members__cprimod_core_init_config_t, 3993 __cint_maddr__cprimod_core_init_config_t 3994 }, 3995 { 3996 "cprimod_core_status_t", 3997 sizeof(cprimod_core_status_t), 3998 __cint_struct_members__cprimod_core_status_t, 3999 __cint_maddr__cprimod_core_status_t 4000 }, 4001 { 4002 "cprimod_port_init_config_t", 4003 sizeof(cprimod_port_init_config_t), 4004 __cint_struct_members__cprimod_port_init_config_t, 4005 __cint_maddr__cprimod_port_init_config_t 4006 }, 4007 { 4008 "cprimod_slow_hdlc_config_info_t", 4009 sizeof(cprimod_slow_hdlc_config_info_t), 4010 __cint_struct_members__cprimod_slow_hdlc_config_info_t, 4011 __cint_maddr__cprimod_slow_hdlc_config_info_t 4012 }, 4013 { 4014 "cprimod_fast_eth_config_info_t", 4015 sizeof(cprimod_fast_eth_config_info_t), 4016 __cint_struct_members__cprimod_fast_eth_config_info_t, 4017 __cint_maddr__cprimod_fast_eth_config_info_t 4018 }, 4019 { 4020 "cprimod_cpri_rx_vsd_config_info_t", 4021 sizeof(cprimod_cpri_rx_vsd_config_info_t), 4022 __cint_struct_members__cprimod_cpri_rx_vsd_config_info_t, 4023 __cint_maddr__cprimod_cpri_rx_vsd_config_info_t 4024 }, 4025 { 4026 "cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t", 4027 sizeof(cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t), 4028 __cint_struct_members__cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t, 4029 __cint_maddr__cprimod_cpri_rx_vsd_ctrl_flow_config_xxx_t 4030 }, 4031 { 4032 "cprimod_cpri_tx_vsd_config_info_t", 4033 sizeof(cprimod_cpri_tx_vsd_config_info_t), 4034 __cint_struct_members__cprimod_cpri_tx_vsd_config_info_t, 4035 __cint_maddr__cprimod_cpri_tx_vsd_config_info_t 4036 }, 4037 { 4038 "cprimod_cpri_tx_vsd_flow_config_info_t", 4039 sizeof(cprimod_cpri_tx_vsd_flow_config_info_t), 4040 __cint_struct_members__cprimod_cpri_tx_vsd_flow_config_info_t, 4041 __cint_maddr__cprimod_cpri_tx_vsd_flow_config_info_t 4042 }, 4043 { 4044 "cprimod_cpri_rx_vsd_raw_config_t", 4045 sizeof(cprimod_cpri_rx_vsd_raw_config_t), 4046 __cint_struct_members__cprimod_cpri_rx_vsd_raw_config_t, 4047 __cint_maddr__cprimod_cpri_rx_vsd_raw_config_t 4048 }, 4049 { 4050 "cprimod_cpri_tx_vsd_raw_config_t", 4051 sizeof(cprimod_cpri_tx_vsd_raw_config_t), 4052 __cint_struct_members__cprimod_cpri_tx_vsd_raw_config_t, 4053 __cint_maddr__cprimod_cpri_tx_vsd_raw_config_t 4054 }, 4055 { 4056 "cprimod_cpri_rx_gcw_config_t", 4057 sizeof(cprimod_cpri_rx_gcw_config_t), 4058 __cint_struct_members__cprimod_cpri_rx_gcw_config_t, 4059 __cint_maddr__cprimod_cpri_rx_gcw_config_t 4060 }, 4061 { 4062 "cprimod_cpri_tx_gcw_config_t", 4063 sizeof(cprimod_cpri_tx_gcw_config_t), 4064 __cint_struct_members__cprimod_cpri_tx_gcw_config_t, 4065 __cint_maddr__cprimod_cpri_tx_gcw_config_t 4066 }, 4067 { 4068 "cprimod_cpri_tx_control_word_t", 4069 sizeof(cprimod_cpri_tx_control_word_t), 4070 __cint_struct_members__cprimod_cpri_tx_control_word_t, 4071 __cint_maddr__cprimod_cpri_tx_control_word_t 4072 }, 4073 { 4074 "cprimod_control_flow_config_t", 4075 sizeof(cprimod_control_flow_config_t), 4076 __cint_struct_members__cprimod_control_flow_config_t, 4077 __cint_maddr__cprimod_control_flow_config_t 4078 }, 4079 { 4080 "cprimod_sync_profile_entry_t", 4081 sizeof(cprimod_sync_profile_entry_t), 4082 __cint_struct_members__cprimod_sync_profile_entry_t, 4083 __cint_maddr__cprimod_sync_profile_entry_t 4084 }, 4085 { 4086 "cprimod_rsvd4_tx_config_info_t", 4087 sizeof(cprimod_rsvd4_tx_config_info_t), 4088 __cint_struct_members__cprimod_rsvd4_tx_config_info_t, 4089 __cint_maddr__cprimod_rsvd4_tx_config_info_t 4090 }, 4091 { 4092 "cprimod_interrupt_callback_entry_t", 4093 sizeof(cprimod_interrupt_callback_entry_t), 4094 __cint_struct_members__cprimod_interrupt_callback_entry_t, 4095 __cint_maddr__cprimod_interrupt_callback_entry_t 4096 }, 4097 { 4098 "cprimod_1588_capture_config_t", 4099 sizeof(cprimod_1588_capture_config_t), 4100 __cint_struct_members__cprimod_1588_capture_config_t, 4101 __cint_maddr__cprimod_1588_capture_config_t 4102 }, 4103 { 4104 "cprimod_1588_time_t", 4105 sizeof(cprimod_1588_time_t), 4106 __cint_struct_members__cprimod_1588_time_t, 4107 __cint_maddr__cprimod_1588_time_t 4108 }, 4109 { 4110 "cprimod_encap_presentation_time_config_t", 4111 sizeof(cprimod_encap_presentation_time_config_t), 4112 __cint_struct_members__cprimod_encap_presentation_time_config_t, 4113 __cint_maddr__cprimod_encap_presentation_time_config_t 4114 }, 4115 { 4116 "cprimod_decap_agnostic_mode_config_t", 4117 sizeof(cprimod_decap_agnostic_mode_config_t), 4118 __cint_struct_members__cprimod_decap_agnostic_mode_config_t, 4119 __cint_maddr__cprimod_decap_agnostic_mode_config_t 4120 }, 4121 { 4122 "cprimod_fec_timestamp_config_t", 4123 sizeof(cprimod_fec_timestamp_config_t), 4124 __cint_struct_members__cprimod_fec_timestamp_config_t, 4125 __cint_maddr__cprimod_fec_timestamp_config_t 4126 }, 4127 #ifdef CPRIMOD_SUPPORT 4128 { 4129 "cprimod_cpri_ecc_intr_info_t", 4130 sizeof(cprimod_cpri_ecc_intr_info_t), 4131 __cint_struct_members__cprimod_cpri_ecc_intr_info_t, 4132 __cint_maddr__cprimod_cpri_ecc_intr_info_t 4133 }, 4134 #endif /* CPRIMOD_SUPPORT */ 4135 #ifdef CPRIMOD_SUPPORT 4136 { 4137 "cprimod_cpri_encap_header_field_mapping_t", 4138 sizeof(cprimod_cpri_encap_header_field_mapping_t), 4139 __cint_struct_members__cprimod_cpri_encap_header_field_mapping_t, 4140 __cint_maddr__cprimod_cpri_encap_header_field_mapping_t 4141 }, 4142 #endif /* CPRIMOD_SUPPORT */ 4143 #ifdef CPRIMOD_SUPPORT 4144 { 4145 "cprimod_cpri_decap_header_field_mapping_t", 4146 sizeof(cprimod_cpri_decap_header_field_mapping_t), 4147 __cint_struct_members__cprimod_cpri_decap_header_field_mapping_t, 4148 __cint_maddr__cprimod_cpri_decap_header_field_mapping_t 4149 }, 4150 #endif /* CPRIMOD_SUPPORT */ 4151 { NULL } 4152 }; 4153 4154 4155 /* Enums section */ 4156 static cint_enum_map_t __cint_enum_map__cprimod_dispatch_type_t[] = 4157 { 4158 #ifdef CPRIMOD_CPRI_FALCON_SUPPORT 4159 { "cprimodDispatchTypeCprif", cprimodDispatchTypeCprif }, 4160 #endif /*CPRIMOD_CPRI_FALCON_SUPPORT */ 4161 { "cprimodDispatchTypeCount", cprimodDispatchTypeCount }, 4162 { NULL } 4163 }; 4164 4165 static cint_enum_map_t __cint_enum_map__cprimod_basic_frame_table_id_t[] = 4166 { 4167 { "cprimod_basic_frame_table_0", cprimod_basic_frame_table_0 }, 4168 { "cprimod_basic_frame_table_1", cprimod_basic_frame_table_1 }, 4169 { "cprimod_basic_frame_table_Count", cprimod_basic_frame_table_Count }, 4170 { NULL } 4171 }; 4172 4173 static cint_enum_map_t __cint_enum_map__cprimod_cpri_frame_map_method_t[] = 4174 { 4175 { "cprimod_cpri_frame_map_method_1", cprimod_cpri_frame_map_method_1 }, 4176 { "cprimod_cpri_frame_map_method_2", cprimod_cpri_frame_map_method_2 }, 4177 { "cprimod_cpri_frame_map_method_3", cprimod_cpri_frame_map_method_3 }, 4178 { "cprimod_cpri_frame_map_method_Count", cprimod_cpri_frame_map_method_Count }, 4179 { NULL } 4180 }; 4181 4182 static cint_enum_map_t __cint_enum_map__cprimod_compression_type_t[] = 4183 { 4184 { "cprimod_compress", cprimod_compress }, 4185 { "cprimod_decompress", cprimod_decompress }, 4186 { "cprimod_no_compress", cprimod_no_compress }, 4187 { "cprimod_Count", cprimod_Count }, 4188 { NULL } 4189 }; 4190 4191 static cint_enum_map_t __cint_enum_map__cprimod_truncation_type_t[] = 4192 { 4193 { "cprimod_truncation_type_15_to_16", cprimod_truncation_type_15_to_16 }, 4194 { "cprimod_truncation_type_add_0", cprimod_truncation_type_add_0 }, 4195 { "cprimod_truncation_type_16_to_15", cprimod_truncation_type_16_to_15 }, 4196 { "cprimod_truncation_type_add_1", cprimod_truncation_type_add_1 }, 4197 { "cprimod_truncation_type_Count", cprimod_truncation_type_Count }, 4198 { NULL } 4199 }; 4200 4201 static cint_enum_map_t __cint_enum_map__cprimod_hdr_encap_type_t[] = 4202 { 4203 { "cprimod_hdr_encap_type_roe", cprimod_hdr_encap_type_roe }, 4204 { "cprimod_hdr_encap_type_encap_none", cprimod_hdr_encap_type_encap_none }, 4205 { "cprimod_hdr_encap_type_Count", cprimod_hdr_encap_type_Count }, 4206 { NULL } 4207 }; 4208 4209 static cint_enum_map_t __cint_enum_map__cprimod_hdr_vlan_type_t[] = 4210 { 4211 { "cprimodHdrVlanTypeUntagged", cprimodHdrVlanTypeUntagged }, 4212 { "cprimodHdrVlanTypeTaggedVlan0", cprimodHdrVlanTypeTaggedVlan0 }, 4213 { "cprimodHdrVlanTypeQinQ", cprimodHdrVlanTypeQinQ }, 4214 { "cprimodHdrVlanTypeTaggedVlan1", cprimodHdrVlanTypeTaggedVlan1 }, 4215 { "cprimodHdrVlanTypeCount", cprimodHdrVlanTypeCount }, 4216 { NULL } 4217 }; 4218 4219 static cint_enum_map_t __cint_enum_map__cprimod_ordering_info_type_t[] = 4220 { 4221 { "cprimod_ordering_info_type_roe_sequence", cprimod_ordering_info_type_roe_sequence }, 4222 { "cprimod_ordering_info_type_bfn_for_qcnt", cprimod_ordering_info_type_bfn_for_qcnt }, 4223 { "cprimod_ordering_info_type_use_pinfo", cprimod_ordering_info_type_use_pinfo }, 4224 { "cprimod_ordering_info_type_Count", cprimod_ordering_info_type_Count }, 4225 { NULL } 4226 }; 4227 4228 static cint_enum_map_t __cint_enum_map__cprimod_ordering_info_prop_t[] = 4229 { 4230 { "cprimod_ordering_info_prop_no_increment", cprimod_ordering_info_prop_no_increment }, 4231 { "cprimod_ordering_info_prop_increment_by_constant", cprimod_ordering_info_prop_increment_by_constant }, 4232 { "cprimod_ordering_info_prop_increment_by_payload", cprimod_ordering_info_prop_increment_by_payload }, 4233 { "cprimod_ordering_info_prop_Count", cprimod_ordering_info_prop_Count }, 4234 { NULL } 4235 }; 4236 4237 static cint_enum_map_t __cint_enum_map__cprimod_vlan_table_id_t[] = 4238 { 4239 { "cprimodVlanTable0", cprimodVlanTable0 }, 4240 { "cprimodVlanTable1", cprimodVlanTable1 }, 4241 { "cprimodVlanTableCount", cprimodVlanTableCount }, 4242 { NULL } 4243 }; 4244 4245 static cint_enum_map_t __cint_enum_map__cprimod_ethertype_t[] = 4246 { 4247 { "cprimodEthertypeRoe", cprimodEthertypeRoe }, 4248 { "cprimodEthertypeFast", cprimodEthertypeFast }, 4249 { "cprimodEthertypeVlan", cprimodEthertypeVlan }, 4250 { "cprimodEthertypeQinQ", cprimodEthertypeQinQ }, 4251 { "cprimodEthertypeRoe1", cprimodEthertypeRoe1 }, 4252 { "cprimodEthertypeCount", cprimodEthertypeCount }, 4253 { NULL } 4254 }; 4255 4256 static cint_enum_map_t __cint_enum_map__cprimod_cls_option_t[] = 4257 { 4258 { "cprimodClsOptionUseQueueNum", cprimodClsOptionUseQueueNum }, 4259 { "cprimodClsOptionUseFlowIdToQueue", cprimodClsOptionUseFlowIdToQueue }, 4260 { "cprimodClsOptionUseOpcodeToQueue", cprimodClsOptionUseOpcodeToQueue }, 4261 { "cprimodClsOptionCount", cprimodClsOptionCount }, 4262 { NULL } 4263 }; 4264 4265 static cint_enum_map_t __cint_enum_map__cprimod_cls_flow_type_t[] = 4266 { 4267 { "cprimodClsFlowTypeData", cprimodClsFlowTypeData }, 4268 { "cprimodClsFlowTypeDataWithExt", cprimodClsFlowTypeDataWithExt }, 4269 { "cprimodClsFlowTypeCtrlWithOpcode", cprimodClsFlowTypeCtrlWithOpcode }, 4270 { "cprimodClsFlowTypeCtrl", cprimodClsFlowTypeCtrl }, 4271 { "cprimodClsFlowTypeCount", cprimodClsFlowTypeCount }, 4272 { NULL } 4273 }; 4274 4275 static cint_enum_map_t __cint_enum_map__cprimod_tgen_counter_select_t[] = 4276 { 4277 { "cprimodTgenCounterSelectBfn", cprimodTgenCounterSelectBfn }, 4278 { "cprimodTgenCounterSelectHfn", cprimodTgenCounterSelectHfn }, 4279 { "cprimodTgenCounterSelectCount", cprimodTgenCounterSelectCount }, 4280 { NULL } 4281 }; 4282 4283 static cint_enum_map_t __cint_enum_map__cprimod_flow_type_t[] = 4284 { 4285 { "cprimodFlowTypeData", cprimodFlowTypeData }, 4286 { "cprimodFlowTypeCtrl", cprimodFlowTypeCtrl }, 4287 { "cprimodFlowTypeCount", cprimodFlowTypeCount }, 4288 { NULL } 4289 }; 4290 4291 static cint_enum_map_t __cint_enum_map__cprimod_transmission_rule_type_t[] = 4292 { 4293 { "cprimodTxRuleTypeData", cprimodTxRuleTypeData }, 4294 { "cprimodTxRuleTypeCtrl", cprimodTxRuleTypeCtrl }, 4295 { "cprimodTxRuleTypeCount", cprimodTxRuleTypeCount }, 4296 { NULL } 4297 }; 4298 4299 static cint_enum_map_t __cint_enum_map__cprimod_modulo_rule_mod_t[] = 4300 { 4301 { "cprimodModuloRuleMod1", cprimodModuloRuleMod1 }, 4302 { "cprimodModuloRuleMod2", cprimodModuloRuleMod2 }, 4303 { "cprimodModuloRuleMod4", cprimodModuloRuleMod4 }, 4304 { "cprimodModuloRuleMod8", cprimodModuloRuleMod8 }, 4305 { "cprimodModuloRuleMod16", cprimodModuloRuleMod16 }, 4306 { "cprimodModuloRuleMod32", cprimodModuloRuleMod32 }, 4307 { "cprimodModuloRuleMod64", cprimodModuloRuleMod64 }, 4308 { "cprimodModuloRuleModCount", cprimodModuloRuleModCount }, 4309 { NULL } 4310 }; 4311 4312 static cint_enum_map_t __cint_enum_map__cprimod_dbm_rule_pos_index_t[] = 4313 { 4314 { "cprimodDbmRulePosIndexStart0", cprimodDbmRulePosIndexStart0 }, 4315 { "cprimodDbmRulePosIndexStart10", cprimodDbmRulePosIndexStart10 }, 4316 { "cprimodDbmRulePosIndexStart20", cprimodDbmRulePosIndexStart20 }, 4317 { "cprimodDbmRulePosIndexStart30", cprimodDbmRulePosIndexStart30 }, 4318 { "cprimodDbmRulePosIndexStart40", cprimodDbmRulePosIndexStart40 }, 4319 { "cprimodDbmRulePosIndexStart50", cprimodDbmRulePosIndexStart50 }, 4320 { "cprimodDbmRulePosIndexStart60", cprimodDbmRulePosIndexStart60 }, 4321 { "cprimodDbmRulePosIndexStart70", cprimodDbmRulePosIndexStart70 }, 4322 { "cprimodDbmRulePosIndexCount", cprimodDbmRulePosIndexCount }, 4323 { NULL } 4324 }; 4325 4326 static cint_enum_map_t __cint_enum_map__cprimod_dbm_rule_pos_grp_size_t[] = 4327 { 4328 { "cprimodDbmRulePosGrpSize10", cprimodDbmRulePosGrpSize10 }, 4329 { "cprimodDbmRulePosGrpSize20", cprimodDbmRulePosGrpSize20 }, 4330 { "cprimodDbmRulePosGrpSize40", cprimodDbmRulePosGrpSize40 }, 4331 { "cprimodDbmRulePosGrpSize80", cprimodDbmRulePosGrpSize80 }, 4332 { "cprimodDbmRulePosGrpSizeCount", cprimodDbmRulePosGrpSizeCount }, 4333 { NULL } 4334 }; 4335 4336 static cint_enum_map_t __cint_enum_map__cprimod_cpri_pcs_mode_t[] = 4337 { 4338 { "cprimodCpriPcsMode8b10b", cprimodCpriPcsMode8b10b }, 4339 { "cprimodCpriPcsMode64b66b", cprimodCpriPcsMode64b66b }, 4340 { "cprimodCpriPcsModeCount", cprimodCpriPcsModeCount }, 4341 { NULL } 4342 }; 4343 4344 static cint_enum_map_t __cint_enum_map__cprimod_port_speed_t[] = 4345 { 4346 { "cprimodSpd614p4", cprimodSpd614p4 }, 4347 { "cprimodSpd1228p8", cprimodSpd1228p8 }, 4348 { "cprimodSpd2457p6", cprimodSpd2457p6 }, 4349 { "cprimodSpd3072p0", cprimodSpd3072p0 }, 4350 { "cprimodSpd4915p2", cprimodSpd4915p2 }, 4351 { "cprimodSpd6144p0", cprimodSpd6144p0 }, 4352 { "cprimodSpd8110p08", cprimodSpd8110p08 }, 4353 { "cprimodSpd9830p4", cprimodSpd9830p4 }, 4354 { "cprimodSpd10137p6", cprimodSpd10137p6 }, 4355 { "cprimodSpd12165p12", cprimodSpd12165p12 }, 4356 { "cprimodSpd24330p24", cprimodSpd24330p24 }, 4357 { "cprimodSpdCount", cprimodSpdCount }, 4358 { NULL } 4359 }; 4360 4361 static cint_enum_map_t __cint_enum_map__cprimod_supported_port_speed_t[] = 4362 { 4363 { "cprimodSupportedSpd1228p8", cprimodSupportedSpd1228p8 }, 4364 { "cprimodSupportedSpd2457p6", cprimodSupportedSpd2457p6 }, 4365 { "cprimodSupportedSpd3072p0", cprimodSupportedSpd3072p0 }, 4366 { "cprimodSupportedSpd4915p2", cprimodSupportedSpd4915p2 }, 4367 { "cprimodSupportedSpd6144p0", cprimodSupportedSpd6144p0 }, 4368 { "cprimodSupportedSpd9830p4", cprimodSupportedSpd9830p4 }, 4369 { "cprimodSupportedSpd10137p6", cprimodSupportedSpd10137p6 }, 4370 { "cprimodSupportedSpd12165p12", cprimodSupportedSpd12165p12 }, 4371 { "cprimodSupportedSpd24330p24", cprimodSupportedSpd24330p24 }, 4372 { "cprimodSupportedSpdCount", cprimodSupportedSpdCount }, 4373 { NULL } 4374 }; 4375 4376 static cint_enum_map_t __cint_enum_map__cprimod_pll_num_in_use_t[] = 4377 { 4378 { "cprimodInUseDefault", cprimodInUseDefault }, 4379 { "cprimodInUsePll0", cprimodInUsePll0 }, 4380 { "cprimodInUsePll1", cprimodInUsePll1 }, 4381 { "cprimodInUsePll0_1", cprimodInUsePll0_1 }, 4382 { "cprimodInUseCount", cprimodInUseCount }, 4383 { NULL } 4384 }; 4385 4386 static cint_enum_map_t __cint_enum_map__cprimod_port_interface_type_t[] = 4387 { 4388 { "cprimodCpri", cprimodCpri }, 4389 { "cprimodRsvd4", cprimodRsvd4 }, 4390 { "cprimodCount", cprimodCount }, 4391 { NULL } 4392 }; 4393 4394 static cint_enum_map_t __cint_enum_map__cprimod_port_rsvd4_speed_mult_t[] = 4395 { 4396 { "cprimodRsvd4SpdMult4X", cprimodRsvd4SpdMult4X }, 4397 { "cprimodRsvd4SpdMult8X", cprimodRsvd4SpdMult8X }, 4398 { "cprimodRsvd4SpdMultCount", cprimodRsvd4SpdMultCount }, 4399 { NULL } 4400 }; 4401 4402 static cint_enum_map_t __cint_enum_map__cprimod_rsvd4_rx_config_field_t[] = 4403 { 4404 { "cprimodRsvd4RxConfigDescrambleEnable", cprimodRsvd4RxConfigDescrambleEnable }, 4405 { "cprimodRsvd4RxConfigSyncThreshold", cprimodRsvd4RxConfigSyncThreshold }, 4406 { "cprimodRsvd4RxConfigUnsyncThreshold", cprimodRsvd4RxConfigUnsyncThreshold }, 4407 { "cprimodRsvd4RxConfigFrameSyncThreshold", cprimodRsvd4RxConfigFrameSyncThreshold }, 4408 { "cprimodRsvd4RxConfigFrameUnsyncThreshold", cprimodRsvd4RxConfigFrameUnsyncThreshold }, 4409 { "cprimodRsvd4RxConfigBlockSize", cprimodRsvd4RxConfigBlockSize }, 4410 { "cprimodRsvd4RxConfigFwdIdlesToFramer", cprimodRsvd4RxConfigFwdIdlesToFramer }, 4411 { "cprimodRsvd4RxConfigCount", cprimodRsvd4RxConfigCount }, 4412 { NULL } 4413 }; 4414 4415 static cint_enum_map_t __cint_enum_map__cprimod_rx_config_field_t[] = 4416 { 4417 { "cprimodRxConfig8b10bAllowSeedChange", cprimodRxConfig8b10bAllowSeedChange }, 4418 { "cprimodRxConfig8b10bDescrHw", cprimodRxConfig8b10bDescrHw }, 4419 { "cprimodRxConfig8b10bDescrEn", cprimodRxConfig8b10bDescrEn }, 4420 { "cprimodRxConfiglinkAcqSwMode", cprimodRxConfiglinkAcqSwMode }, 4421 { "cprimodRxConfig64b66bLosOption", cprimodRxConfig64b66bLosOption }, 4422 { "cprimodRxConfig8b10bForceCommaAlignEn", cprimodRxConfig8b10bForceCommaAlignEn }, 4423 { "cprimodRxConfig64b66bBerWindowLimit", cprimodRxConfig64b66bBerWindowLimit }, 4424 { "cprimodRxConfig64b66bBerLimit", cprimodRxConfig64b66bBerLimit }, 4425 { "cprimodRxConfigtestMode", cprimodRxConfigtestMode }, 4426 { "cprimodRxConfig64b66bInvalidShCnt", cprimodRxConfig64b66bInvalidShCnt }, 4427 { "cprimodRxConfig64b66bValidShCnt", cprimodRxConfig64b66bValidShCnt }, 4428 { "cprimodRxConfigCount", cprimodRxConfigCount }, 4429 { NULL } 4430 }; 4431 4432 static cint_enum_map_t __cint_enum_map__cprimod_rsvd4_rx_fsm_state_t[] = 4433 { 4434 { "cprimodRsvd4RxFsmStateUnsync", cprimodRsvd4RxFsmStateUnsync }, 4435 { "cprimodRsvd4RxFsmStateWaitForSeed", cprimodRsvd4RxFsmStateWaitForSeed }, 4436 { "cprimodRsvd4RxFsmStateWaitForAck", cprimodRsvd4RxFsmStateWaitForAck }, 4437 { "cprimodRsvd4RxFsmStateWaitForK28p7Idles", cprimodRsvd4RxFsmStateWaitForK28p7Idles }, 4438 { "cprimodRsvd4RxFsmStateWaitForFrameSync", cprimodRsvd4RxFsmStateWaitForFrameSync }, 4439 { "cprimodRsvd4RxFsmStateFrameSync", cprimodRsvd4RxFsmStateFrameSync }, 4440 { "cprimodRsvd4RxFsmStateCount", cprimodRsvd4RxFsmStateCount }, 4441 { NULL } 4442 }; 4443 4444 static cint_enum_map_t __cint_enum_map__cprimod_rsvd4_rx_overide_t[] = 4445 { 4446 { "cprimodRsvd4RxOverideFrameUnsyncTInvldMgRecvd", cprimodRsvd4RxOverideFrameUnsyncTInvldMgRecvd }, 4447 { "cprimodRsvd4RxOverideFrameSyncTVldMgRecvd", cprimodRsvd4RxOverideFrameSyncTVldMgRecvd }, 4448 { "cprimodRsvd4RxOverideKMgIdlesRecvd", cprimodRsvd4RxOverideKMgIdlesRecvd }, 4449 { "cprimodRsvd4RxOverideIdleReqRecvd", cprimodRsvd4RxOverideIdleReqRecvd }, 4450 { "cprimodRsvd4RxOverideIdleAckRecvd", cprimodRsvd4RxOverideIdleAckRecvd }, 4451 { "cprimodRsvd4RxOverideSeedCapAndVerifyDone", cprimodRsvd4RxOverideSeedCapAndVerifyDone }, 4452 { "cprimodRsvd4RxOverideCount", cprimodRsvd4RxOverideCount }, 4453 { NULL } 4454 }; 4455 4456 static cint_enum_map_t __cint_enum_map__cprimod_rsvd4_tx_config_field_t[] = 4457 { 4458 { "cprimodRsvd4TxConfigForceOffState", cprimodRsvd4TxConfigForceOffState }, 4459 { "cprimodRsvd4TxConfigAckT", cprimodRsvd4TxConfigAckT }, 4460 { "cprimodRsvd4TxConfigForceIdleAck", cprimodRsvd4TxConfigForceIdleAck }, 4461 { "cprimodRsvd4TxConfigLosEnable", cprimodRsvd4TxConfigLosEnable }, 4462 { "cprimodRsvd4TxConfigScrambleEnable", cprimodRsvd4TxConfigScrambleEnable }, 4463 { "cprimodRsvd4TxConfigScramblerSeed", cprimodRsvd4TxConfigScramblerSeed }, 4464 { "cprimodRsvd4TxConfigTransmitterEnable", cprimodRsvd4TxConfigTransmitterEnable }, 4465 { "cprimodRsvd4TxConfigCount", cprimodRsvd4TxConfigCount }, 4466 { NULL } 4467 }; 4468 4469 static cint_enum_map_t __cint_enum_map__cprimod_tx_config_field_t[] = 4470 { 4471 { "cprimodTxConfigagnosticMode", cprimodTxConfigagnosticMode }, 4472 { "cprimodTxConfigtxpmdDisableOverrideVal", cprimodTxConfigtxpmdDisableOverrideVal }, 4473 { "cprimodTxConfigtxpmdDisableOverrideEn", cprimodTxConfigtxpmdDisableOverrideEn }, 4474 { "cprimodTxConfigseed8B10B", cprimodTxConfigseed8B10B }, 4475 { "cprimodTxConfigscrambleBypass", cprimodTxConfigscrambleBypass }, 4476 { "cprimodTxConfigseed8b10b", cprimodTxConfigseed8b10b }, 4477 { "cprimodTxConfigcwaScrEn8b10b", cprimodTxConfigcwaScrEn8b10b }, 4478 { "cprimodTxConfigCount", cprimodTxConfigCount }, 4479 { NULL } 4480 }; 4481 4482 static cint_enum_map_t __cint_enum_map__cprimod_rsvd4_tx_fsm_state_t[] = 4483 { 4484 { "cprimodRsvd4TxFsmStateOff", cprimodRsvd4TxFsmStateOff }, 4485 { "cprimodRsvd4TxFsmStateIdle", cprimodRsvd4TxFsmStateIdle }, 4486 { "cprimodRsvd4TxFsmStateIdleReq", cprimodRsvd4TxFsmStateIdleReq }, 4487 { "cprimodRsvd4TxFsmStateIdleAck", cprimodRsvd4TxFsmStateIdleAck }, 4488 { "cprimodRsvd4TxFsmStateFrameTx", cprimodRsvd4TxFsmStateFrameTx }, 4489 { "cprimodRsvd4TxFsmStateCount", cprimodRsvd4TxFsmStateCount }, 4490 { NULL } 4491 }; 4492 4493 static cint_enum_map_t __cint_enum_map__cprimod_rsvd4_tx_overide_t[] = 4494 { 4495 { "cprimodRsvd4TxOverideStartTx", cprimodRsvd4TxOverideStartTx }, 4496 { "cprimodRsvd4TxOverideRxPcsAckCap", cprimodRsvd4TxOverideRxPcsAckCap }, 4497 { "cprimodRsvd4TxOverideRxPcsIdleReq", cprimodRsvd4TxOverideRxPcsIdleReq }, 4498 { "cprimodRsvd4TxOverideRxPcsScrLock", cprimodRsvd4TxOverideRxPcsScrLock }, 4499 { "cprimodRsvd4TxOverideLosStauts", cprimodRsvd4TxOverideLosStauts }, 4500 { "cprimodRsvd4TxOverideCount", cprimodRsvd4TxOverideCount }, 4501 { NULL } 4502 }; 4503 4504 static cint_enum_map_t __cint_enum_map__cprimod_rx_pcs_status_t[] = 4505 { 4506 { "cprimodRxPcsStatusLinkStatusLive", cprimodRxPcsStatusLinkStatusLive }, 4507 { "cprimodRxPcsStatusSeedLocked", cprimodRxPcsStatusSeedLocked }, 4508 { "cprimodRxPcsStatusSeedVector", cprimodRxPcsStatusSeedVector }, 4509 { "cprimodRxPcsStatusLosLive", cprimodRxPcsStatusLosLive }, 4510 { "cprimodRxPcsStatus64b66bHiBerLive", cprimodRxPcsStatus64b66bHiBerLive }, 4511 { "cprimodRxPcsStatus64b66bBlockLockLive", cprimodRxPcsStatus64b66bBlockLockLive }, 4512 { "cprimodRxPcsStatusCount", cprimodRxPcsStatusCount }, 4513 { NULL } 4514 }; 4515 4516 static cint_enum_map_t __cint_enum_map__cprimod_firmware_load_force_t[] = 4517 { 4518 { "cprimodFirmwareLoadSkip", cprimodFirmwareLoadSkip }, 4519 { "cprimodFirmwareLoadForce", cprimodFirmwareLoadForce }, 4520 { "cprimodFirmwareLoadAuto", cprimodFirmwareLoadAuto }, 4521 { "cprimodFirmwareLoadCount", cprimodFirmwareLoadCount }, 4522 { NULL } 4523 }; 4524 4525 static cint_enum_map_t __cint_enum_map__cprimod_firmware_load_method_t[] = 4526 { 4527 { "cprimodFirmwareLoadMethodNone", cprimodFirmwareLoadMethodNone }, 4528 { "cprimodFirmwareLoadMethodInternal", cprimodFirmwareLoadMethodInternal }, 4529 { "cprimodFirmwareLoadMethodExternal", cprimodFirmwareLoadMethodExternal }, 4530 { "cprimodFirmwareLoadMethodProgEEPROM", cprimodFirmwareLoadMethodProgEEPROM }, 4531 { "cprimodFirmwareLoadMethodCount", cprimodFirmwareLoadMethodCount }, 4532 { NULL } 4533 }; 4534 4535 static cint_enum_map_t __cint_enum_map__cprimod_tx_input_voltage_t[] = 4536 { 4537 { "cprimodTxInputVoltageDefault", cprimodTxInputVoltageDefault }, 4538 { "cprimodTxInputVoltage1p00", cprimodTxInputVoltage1p00 }, 4539 { "cprimodTxInputVoltage1p25", cprimodTxInputVoltage1p25 }, 4540 { "cprimodTxInputVoltageCount", cprimodTxInputVoltageCount }, 4541 { NULL } 4542 }; 4543 4544 static cint_enum_map_t __cint_enum_map__cprimod_hdlc_crc_byte_order_t[] = 4545 { 4546 { "cprimodHdlcCrcByteOrderNone", cprimodHdlcCrcByteOrderNone }, 4547 { "cprimodHdlcCrcByteOrderSwap", cprimodHdlcCrcByteOrderSwap }, 4548 { "cprimodHdlcCrcByteOrderCount", cprimodHdlcCrcByteOrderCount }, 4549 { NULL } 4550 }; 4551 4552 static cint_enum_map_t __cint_enum_map__cprimod_hdlc_fcs_err_check_t[] = 4553 { 4554 { "cprimodHdlcFcsErrCheck", cprimodHdlcFcsErrCheck }, 4555 { "cprimodHdlcFcsErrNoCheck", cprimodHdlcFcsErrNoCheck }, 4556 { "cprimodHdlcFcsErrCount", cprimodHdlcFcsErrCount }, 4557 { NULL } 4558 }; 4559 4560 static cint_enum_map_t __cint_enum_map__cprimod_cw_filter_mode_t[] = 4561 { 4562 { "cprimodCwFilterDisable", cprimodCwFilterDisable }, 4563 { "cprimodCwFilterNonZero", cprimodCwFilterNonZero }, 4564 { "cprimodCwFilterPeriodic", cprimodCwFilterPeriodic }, 4565 { "cprimodCwFilterChange", cprimodCwFilterChange }, 4566 { "cprimodCwFilterPatternMatch", cprimodCwFilterPatternMatch }, 4567 { "cprimodCwFilterCount", cprimodCwFilterCount }, 4568 { NULL } 4569 }; 4570 4571 static cint_enum_map_t __cint_enum_map__cprimod_vsd_raw_map_mode_t[] = 4572 { 4573 { "cprimodVsdRawMapModePeriodic", cprimodVsdRawMapModePeriodic }, 4574 { "cprimodVsdRawMapModeRoeFrame", cprimodVsdRawMapModeRoeFrame }, 4575 { "cprimodVsdRawMapModeCount", cprimodVsdRawMapModeCount }, 4576 { NULL } 4577 }; 4578 4579 static cint_enum_map_t __cint_enum_map__cprimod_gcw_mask_t[] = 4580 { 4581 { "cprimodGcwMaskNone", cprimodGcwMaskNone }, 4582 { "cprimodGcwMaskLSB", cprimodGcwMaskLSB }, 4583 { "cprimodGcwMaskMSB", cprimodGcwMaskMSB }, 4584 { "cprimodGcwMaskBOTH", cprimodGcwMaskBOTH }, 4585 { "cprimodGcwMaskCount", cprimodGcwMaskCount }, 4586 { NULL } 4587 }; 4588 4589 static cint_enum_map_t __cint_enum_map__cprimod_1588_capture_mode_t[] = 4590 { 4591 { "cprimod_1588_MATCH_BFN_AND_HFN", cprimod_1588_MATCH_BFN_AND_HFN }, 4592 { "cprimod_1588_MATCH_HFN_ONLY", cprimod_1588_MATCH_HFN_ONLY }, 4593 { "cprimod_1588_MATCH_Count", cprimod_1588_MATCH_Count }, 4594 { NULL } 4595 }; 4596 4597 static cint_enum_map_t __cint_enum_map__cprimod_agnostic_mode_type_t[] = 4598 { 4599 { "cprimod_agnostic_mode_cpri", cprimod_agnostic_mode_cpri }, 4600 { "cprimod_agnostic_mode_rsvd4", cprimod_agnostic_mode_rsvd4 }, 4601 { "cprimod_agnostic_mode_tunnel", cprimod_agnostic_mode_tunnel }, 4602 { "cprimod_agnostic_mode_Count", cprimod_agnostic_mode_Count }, 4603 { NULL } 4604 }; 4605 4606 static cint_enum_map_t __cint_enum_map__cprimod_pmd_port_status_t[] = 4607 { 4608 { "cprimodPmdPortStatusTxClockValid", cprimodPmdPortStatusTxClockValid }, 4609 { "cprimodPmdPortStatusRxClockValid", cprimodPmdPortStatusRxClockValid }, 4610 { "cprimodPmdPortStatusRxLock", cprimodPmdPortStatusRxLock }, 4611 { "cprimodPmdPortStatusEnergyDetected", cprimodPmdPortStatusEnergyDetected }, 4612 { "cprimodPmdPortStatusSignalDetected", cprimodPmdPortStatusSignalDetected }, 4613 { "cprimodPmdPortStatusCount", cprimodPmdPortStatusCount }, 4614 { NULL } 4615 }; 4616 4617 4618 static cint_enum_type_t __cint_enums[] = 4619 { 4620 {"cprimod_dispatch_type_t", __cint_enum_map__cprimod_dispatch_type_t }, 4621 {"cprimod_basic_frame_table_id_t", __cint_enum_map__cprimod_basic_frame_table_id_t }, 4622 {"cprimod_cpri_frame_map_method_t", __cint_enum_map__cprimod_cpri_frame_map_method_t }, 4623 {"cprimod_compression_type_t", __cint_enum_map__cprimod_compression_type_t }, 4624 {"cprimod_truncation_type_t", __cint_enum_map__cprimod_truncation_type_t }, 4625 {"cprimod_hdr_encap_type_t", __cint_enum_map__cprimod_hdr_encap_type_t }, 4626 {"cprimod_hdr_vlan_type_t", __cint_enum_map__cprimod_hdr_vlan_type_t }, 4627 {"cprimod_ordering_info_type_t", __cint_enum_map__cprimod_ordering_info_type_t }, 4628 {"cprimod_ordering_info_prop_t", __cint_enum_map__cprimod_ordering_info_prop_t }, 4629 {"cprimod_vlan_table_id_t", __cint_enum_map__cprimod_vlan_table_id_t }, 4630 {"cprimod_ethertype_t", __cint_enum_map__cprimod_ethertype_t }, 4631 {"cprimod_cls_option_t", __cint_enum_map__cprimod_cls_option_t }, 4632 {"cprimod_cls_flow_type_t", __cint_enum_map__cprimod_cls_flow_type_t }, 4633 {"cprimod_tgen_counter_select_t", __cint_enum_map__cprimod_tgen_counter_select_t }, 4634 {"cprimod_flow_type_t", __cint_enum_map__cprimod_flow_type_t }, 4635 {"cprimod_transmission_rule_type_t", __cint_enum_map__cprimod_transmission_rule_type_t }, 4636 {"cprimod_modulo_rule_mod_t", __cint_enum_map__cprimod_modulo_rule_mod_t }, 4637 {"cprimod_dbm_rule_pos_index_t", __cint_enum_map__cprimod_dbm_rule_pos_index_t }, 4638 {"cprimod_dbm_rule_pos_grp_size_t", __cint_enum_map__cprimod_dbm_rule_pos_grp_size_t }, 4639 {"cprimod_cpri_pcs_mode_t", __cint_enum_map__cprimod_cpri_pcs_mode_t }, 4640 {"cprimod_port_speed_t", __cint_enum_map__cprimod_port_speed_t }, 4641 {"cprimod_supported_port_speed_t", __cint_enum_map__cprimod_supported_port_speed_t }, 4642 {"cprimod_pll_num_in_use_t", __cint_enum_map__cprimod_pll_num_in_use_t }, 4643 {"cprimod_port_interface_type_t", __cint_enum_map__cprimod_port_interface_type_t }, 4644 {"cprimod_port_rsvd4_speed_mult_t", __cint_enum_map__cprimod_port_rsvd4_speed_mult_t }, 4645 {"cprimod_rsvd4_rx_config_field_t", __cint_enum_map__cprimod_rsvd4_rx_config_field_t }, 4646 {"cprimod_rx_config_field_t", __cint_enum_map__cprimod_rx_config_field_t }, 4647 {"cprimod_rsvd4_rx_fsm_state_t", __cint_enum_map__cprimod_rsvd4_rx_fsm_state_t }, 4648 {"cprimod_rsvd4_rx_overide_t", __cint_enum_map__cprimod_rsvd4_rx_overide_t }, 4649 {"cprimod_rsvd4_tx_config_field_t", __cint_enum_map__cprimod_rsvd4_tx_config_field_t }, 4650 {"cprimod_tx_config_field_t", __cint_enum_map__cprimod_tx_config_field_t }, 4651 {"cprimod_rsvd4_tx_fsm_state_t", __cint_enum_map__cprimod_rsvd4_tx_fsm_state_t }, 4652 {"cprimod_rsvd4_tx_overide_t", __cint_enum_map__cprimod_rsvd4_tx_overide_t }, 4653 {"cprimod_rx_pcs_status_t", __cint_enum_map__cprimod_rx_pcs_status_t }, 4654 {"cprimod_firmware_load_force_t", __cint_enum_map__cprimod_firmware_load_force_t }, 4655 {"cprimod_firmware_load_method_t", __cint_enum_map__cprimod_firmware_load_method_t }, 4656 {"cprimod_tx_input_voltage_t", __cint_enum_map__cprimod_tx_input_voltage_t }, 4657 {"cprimod_hdlc_crc_byte_order_t", __cint_enum_map__cprimod_hdlc_crc_byte_order_t }, 4658 {"cprimod_hdlc_fcs_err_check_t", __cint_enum_map__cprimod_hdlc_fcs_err_check_t }, 4659 {"cprimod_cw_filter_mode_t", __cint_enum_map__cprimod_cw_filter_mode_t }, 4660 {"cprimod_vsd_raw_map_mode_t", __cint_enum_map__cprimod_vsd_raw_map_mode_t }, 4661 {"cprimod_gcw_mask_t", __cint_enum_map__cprimod_gcw_mask_t }, 4662 {"cprimod_1588_capture_mode_t", __cint_enum_map__cprimod_1588_capture_mode_t }, 4663 {"cprimod_agnostic_mode_type_t", __cint_enum_map__cprimod_agnostic_mode_type_t }, 4664 {"cprimod_pmd_port_status_t", __cint_enum_map__cprimod_pmd_port_status_t }, 4665 { NULL } 4666 }; 4667 4668 /* Defines section */ 4669 static cint_constants_t __cint_constants[] = 4670 { 4671 { "CPRIMOD_MAX_LANES_PER_CORE", CPRIMOD_MAX_LANES_PER_CORE }, 4672 { "CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY", CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY }, 4673 { "CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY", CPRIMOD_BASIC_FRAME_MAX_BITS_PER_ENTRY }, 4674 { "CPRIMOD_AXC_ID_AGNOSTIC", CPRIMOD_AXC_ID_AGNOSTIC }, 4675 { "CPRIMOD_AXC_ID_CONTROL", CPRIMOD_AXC_ID_CONTROL }, 4676 { "CPRIMOD_AXC_ID_ALL", CPRIMOD_AXC_ID_ALL }, 4677 { "CPRIMOD_DEBUG_BASIC_FRAME_USAGE", CPRIMOD_DEBUG_BASIC_FRAME_USAGE }, 4678 { "CPRIMOD_DEBUG_BASIC_FRAME_RAW", CPRIMOD_DEBUG_BASIC_FRAME_RAW }, 4679 { "CPRIMOD_RSVD4_HEADER_SIZE", CPRIMOD_RSVD4_HEADER_SIZE }, 4680 { "CPRIMOD_RSVD4_PAYLOAD_SIZE", CPRIMOD_RSVD4_PAYLOAD_SIZE }, 4681 { "CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER", CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER }, 4682 { "CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO", CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO }, 4683 { "CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC", CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC }, 4684 { "CPRIMOD_CPRI_FRAME_SYNC_MODE_TUNNEL", CPRIMOD_CPRI_FRAME_SYNC_MODE_TUNNEL }, 4685 { "CPRIMOD_RSVD4_FRAME_SYNC_MODE_NO_SYNC", CPRIMOD_RSVD4_FRAME_SYNC_MODE_NO_SYNC }, 4686 { "CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_OFFSET", CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_OFFSET }, 4687 { "CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_AND_MASTER_OFFSET", CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_AND_MASTER_OFFSET }, 4688 { "CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_NO_SYNC", CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_NO_SYNC }, 4689 { "CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_OFFSET", CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_OFFSET }, 4690 { "CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_AND_MASTER_OFFSET", CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_AND_MASTER_OFFSET }, 4691 { "CPRIMOD_RSVD4_MSG_TS_MODE_WCDMA", CPRIMOD_RSVD4_MSG_TS_MODE_WCDMA }, 4692 { "CPRIMOD_RSVD4_MSG_TS_MODE_LTE", CPRIMOD_RSVD4_MSG_TS_MODE_LTE }, 4693 { "CPRIMOD_RSVD4_MSG_TS_MODE_GSM_DL", CPRIMOD_RSVD4_MSG_TS_MODE_GSM_DL }, 4694 { "CPRIMOD_RSVD4_MSG_TS_MODE_GSM_UL", CPRIMOD_RSVD4_MSG_TS_MODE_GSM_UL }, 4695 { "CPRIMOD_CPRI_ROE_FRAME_FORMAT_IEEE1914", CPRIMOD_CPRI_ROE_FRAME_FORMAT_IEEE1914 }, 4696 { "CPRIMOD_CPRI_ROE_FRAME_FORMAT_RSVD3", CPRIMOD_CPRI_ROE_FRAME_FORMAT_RSVD3 }, 4697 { "CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8", CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8 }, 4698 { "CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12", CPRIMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12 }, 4699 { "CPRIMOD_CORE_INIT_F_UNTIL_FW_LOAD", CPRIMOD_CORE_INIT_F_UNTIL_FW_LOAD }, 4700 { "CPRIMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD", CPRIMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD }, 4701 { "CPRIMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY", CPRIMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY }, 4702 { "CPRIMOD_CORE_INIT_F_EXECUTE_PASS1", CPRIMOD_CORE_INIT_F_EXECUTE_PASS1 }, 4703 { "CPRIMOD_CORE_INIT_F_EXECUTE_PASS2", CPRIMOD_CORE_INIT_F_EXECUTE_PASS2 }, 4704 { "CPRIMOD_CORE_INIT_F_BYPASS_CRC_CHECK", CPRIMOD_CORE_INIT_F_BYPASS_CRC_CHECK }, 4705 { "CPRIMOD_CORE_INIT_F_FW_FORCE_DOWNLOAD", CPRIMOD_CORE_INIT_F_FW_FORCE_DOWNLOAD }, 4706 { "CPRIMOD_CORE_INIT_F_EXECUTE_FW_LOAD", CPRIMOD_CORE_INIT_F_EXECUTE_FW_LOAD }, 4707 { "CPRIMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD", CPRIMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD }, 4708 { "CPRIMOD_CORE_INIT_F_FW_LOAD_END", CPRIMOD_CORE_INIT_F_FW_LOAD_END }, 4709 { "CPRIMOD_CORE_INIT_F_FW_AUTO_DOWNLOAD", CPRIMOD_CORE_INIT_F_FW_AUTO_DOWNLOAD }, 4710 { "CPRIMOD_L1_SIGNAL_LOF", CPRIMOD_L1_SIGNAL_LOF }, 4711 { "CPRIMOD_L1_SIGNAL_LOS", CPRIMOD_L1_SIGNAL_LOS }, 4712 { "CPRIMOD_L1_SIGNAL_SDI", CPRIMOD_L1_SIGNAL_SDI }, 4713 { "CPRIMOD_L1_SIGNAL_RAI", CPRIMOD_L1_SIGNAL_RAI }, 4714 { "CPRIMOD_L1_SIGNAL_RESET", CPRIMOD_L1_SIGNAL_RESET }, 4715 { "CPRIMOD_L1_SIGNAL_ETH_PTR", CPRIMOD_L1_SIGNAL_ETH_PTR }, 4716 { "CPRIMOD_L1_SIGNAL_HDLC_RATE", CPRIMOD_L1_SIGNAL_HDLC_RATE }, 4717 { "CPRIMOD_L1_SIGNAL_PROT_VER", CPRIMOD_L1_SIGNAL_PROT_VER }, 4718 { "CPRIMOD_CPRI_HDLC_FCS_SIZE_8_BITS", CPRIMOD_CPRI_HDLC_FCS_SIZE_8_BITS }, 4719 { "CPRIMOD_CPRI_HDLC_FCS_SIZE_16_BITS", CPRIMOD_CPRI_HDLC_FCS_SIZE_16_BITS }, 4720 { "CPRIMOD_CPRI_HDLC_FCS_SIZE_32_BITS", CPRIMOD_CPRI_HDLC_FCS_SIZE_32_BITS }, 4721 { "CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E", CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E }, 4722 { "CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7F", CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7F }, 4723 { "CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_FF", CPRIMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_FF }, 4724 { "CPRIMOD_HDLC_FLAG_SIZE_1_BYTE", CPRIMOD_HDLC_FLAG_SIZE_1_BYTE }, 4725 { "CPRIMOD_HDLC_FLAG_SIZE_2_BYTE", CPRIMOD_HDLC_FLAG_SIZE_2_BYTE }, 4726 { "CPRIMOD_CPRI_CRC_MODE_APPEND", CPRIMOD_CPRI_CRC_MODE_APPEND }, 4727 { "CPRIMOD_CPRI_CRC_MODE_REPLACE", CPRIMOD_CPRI_CRC_MODE_REPLACE }, 4728 { "CPRIMOD_CPRI_CRC_MODE_NO_UPDATE", CPRIMOD_CPRI_CRC_MODE_NO_UPDATE }, 4729 { "CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_0", CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_0 }, 4730 { "CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1", CPRIMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1 }, 4731 { "CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1", CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1 }, 4732 { "CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2", CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2 }, 4733 { "CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4", CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4 }, 4734 { "CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_2", CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_2 }, 4735 { "CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_4", CPRIMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_4 }, 4736 { "CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_2", CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_2 }, 4737 { "CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_4", CPRIMOD_CPRI_VSD_CONTROL_FLOW_NUM_BYTES_4 }, 4738 { "CPRIMOD_CPRI_CW_FILTER_DISABLE", CPRIMOD_CPRI_CW_FILTER_DISABLE }, 4739 { "CPRIMOD_CPRI_CW_FILTER_NON_ZERO", CPRIMOD_CPRI_CW_FILTER_NON_ZERO }, 4740 { "CPRIMOD_CPRI_CW_FILTER_PERIODIC", CPRIMOD_CPRI_CW_FILTER_PERIODIC }, 4741 { "CPRIMOD_CPRI_CW_FILTER_CHANGE", CPRIMOD_CPRI_CW_FILTER_CHANGE }, 4742 { "CPRIMOD_CPRI_CW_FILTER_PATTERN_MATCH", CPRIMOD_CPRI_CW_FILTER_PATTERN_MATCH }, 4743 { "CPRIMOD_CPRI_CW_MAP_MODE_PERIODIC", CPRIMOD_CPRI_CW_MAP_MODE_PERIODIC }, 4744 { "CPRIMOD_CPRI_CW_MAP_MODE_ROE_FRAME", CPRIMOD_CPRI_CW_MAP_MODE_ROE_FRAME }, 4745 { "CPRIMOD_CPRI_GCW_MASK_NONE", CPRIMOD_CPRI_GCW_MASK_NONE }, 4746 { "CPRIMOD_CPRI_GCW_MASK_LSB", CPRIMOD_CPRI_GCW_MASK_LSB }, 4747 { "CPRIMOD_CPRI_GCW_MASK_MSB", CPRIMOD_CPRI_GCW_MASK_MSB }, 4748 { "CPRIMOD_CPRI_GCW_MASK_BOTH", CPRIMOD_CPRI_GCW_MASK_BOTH }, 4749 { "CPRIMOD_CONTROL_MSG_PROC_TYPE_FE", CPRIMOD_CONTROL_MSG_PROC_TYPE_FE }, 4750 { "CPRIMOD_CONTROL_MSG_PROC_TYPE_FCB", CPRIMOD_CONTROL_MSG_PROC_TYPE_FCB }, 4751 { "CPRIMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD", CPRIMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD }, 4752 { "CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE", CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE }, 4753 { "CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG", CPRIMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG }, 4754 { "CPRIMOD_SYNC_COUNT_CYCLE_EVERY_MF", CPRIMOD_SYNC_COUNT_CYCLE_EVERY_MF }, 4755 { "CPRIMOD_SYNC_COUNT_CYCLE_UP_TO_6MF", CPRIMOD_SYNC_COUNT_CYCLE_UP_TO_6MF }, 4756 { "CPRIMOD_CPRI_TAG_DEFAULT", CPRIMOD_CPRI_TAG_DEFAULT }, 4757 { "CPRIMOD_CPRI_TAG_LOOKUP", CPRIMOD_CPRI_TAG_LOOKUP }, 4758 { "CPRIMOD_CPRI_CRC_USE_ROE", CPRIMOD_CPRI_CRC_USE_ROE }, 4759 { "CPRIMOD_CPRI_CRC_REGENERATE", CPRIMOD_CPRI_CRC_REGENERATE }, 4760 { "CPRIMOD_INTR_DATA_NUM_OF_DATA64", CPRIMOD_INTR_DATA_NUM_OF_DATA64 }, 4761 { "CPRIMOD_1588_TS_TYPE_FIFO", CPRIMOD_1588_TS_TYPE_FIFO }, 4762 { "CPRIMOD_1588_TS_TYPE_CMIC", CPRIMOD_1588_TS_TYPE_CMIC }, 4763 { "CPRIMOD_1588_TS_TYPE_SW_CAP", CPRIMOD_1588_TS_TYPE_SW_CAP }, 4764 { "CPRIMOD_DIR_TX", CPRIMOD_DIR_TX }, 4765 { "CPRIMOD_DIR_RX", CPRIMOD_DIR_RX }, 4766 { "CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1X", CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1X }, 4767 { "CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1P5X", CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1P5X }, 4768 { "CPRIMOD_CPRI_PAYLOAD_MULTIPLE_2X", CPRIMOD_CPRI_PAYLOAD_MULTIPLE_2X }, 4769 { "CPRIMOD_CPRI_PAYLOAD_MULTIPLE_4X", CPRIMOD_CPRI_PAYLOAD_MULTIPLE_4X }, 4770 { "CPRIMOD_CPRI_PAYLOAD_MULTIPLE_8X", CPRIMOD_CPRI_PAYLOAD_MULTIPLE_8X }, 4771 { "CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM", CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM }, 4772 { "CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP", CPRIMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP }, 4773 { "CPRIMOD_CPRI_FEC_TS_SOURCE_66B", CPRIMOD_CPRI_FEC_TS_SOURCE_66B }, 4774 { "CPRIMOD_CPRI_FEC_TS_SOURCE_257B", CPRIMOD_CPRI_FEC_TS_SOURCE_257B }, 4775 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX", CPRIMOD_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX }, 4776 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX", CPRIMOD_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX }, 4777 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE", CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE }, 4778 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE", CPRIMOD_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE }, 4779 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCK_ENABLE", CPRIMOD_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCK_ENABLE }, 4780 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE", CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE }, 4781 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TIMER_PERIOD", CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TIMER_PERIOD }, 4782 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_COUNT_THRESHOLD", CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_COUNT_THRESHOLD }, 4783 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_WINDOW", CPRIMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_WINDOW }, 4784 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_DENOMINATOR", CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_DENOMINATOR }, 4785 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_NUMERATOR", CPRIMOD_CPRI_FEC_AUX_CONFIG_TICK_NUMERATOR }, 4786 { "CPRIMOD_CPRI_FEC_AUX_CONFIG_SOFT_RESET", CPRIMOD_CPRI_FEC_AUX_CONFIG_SOFT_RESET }, 4787 #ifdef CPRIMOD_SUPPORT 4788 { "CPRIMOD_PM_ECC_ERR_NONE", CPRIMOD_PM_ECC_ERR_NONE }, 4789 { "CPRIMOD_PM_ECC_ERR_1_BIT", CPRIMOD_PM_ECC_ERR_1_BIT }, 4790 { "CPRIMOD_PM_ECC_ERR_2_BIT", CPRIMOD_PM_ECC_ERR_2_BIT }, 4791 { "CPRIMOD_PM_ECC_ERR_MULTI_BIT", CPRIMOD_PM_ECC_ERR_MULTI_BIT }, 4792 #endif /* CPRIMOD_SUPPORT */ 4793 #ifdef CPRIMOD_SUPPORT 4794 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE", CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE }, 4795 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID", CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID }, 4796 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8", CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8 }, 4797 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0", CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0 }, 4798 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24", CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24 }, 4799 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16", CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16 }, 4800 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8", CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8 }, 4801 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0", CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0 }, 4802 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_OPCODE", CPRIMOD_CPRI_ROE_HEADER_FIELD_OPCODE }, 4803 { "CPRIMOD_CPRI_ROE_HEADER_FIELD_UNMAPPED", CPRIMOD_CPRI_ROE_HEADER_FIELD_UNMAPPED }, 4804 #endif /* CPRIMOD_SUPPORT */ 4805 #ifdef CPRIMOD_SUPPORT 4806 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_0", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_0 }, 4807 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1 }, 4808 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2 }, 4809 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3 }, 4810 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_4", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_4 }, 4811 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_5", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_5 }, 4812 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_6", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_6 }, 4813 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_7", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_7 }, 4814 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_8", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_8 }, 4815 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_9", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_9 }, 4816 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_10", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_10 }, 4817 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_11", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_11 }, 4818 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0 }, 4819 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1 }, 4820 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0 }, 4821 { "CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1", CPRIMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1 }, 4822 #endif /* CPRIMOD_SUPPORT */ 4823 { NULL } 4824 }; 4825 4826 4827 /* Typedefs section */ 4828 static cint_parameter_desc_t __cint_typedefs[] = 4829 { 4830 {"_shr_cpri_frame_sync_mode_t", "cprimod_cpri_frame_sync_mode_t" , 0 , 0}, 4831 {"_shr_rsvd4_sync_mode_t", "cprimod_rsvd4_frame_sync_mode_t" , 0 , 0}, 4832 {"_shr_rsvd4_msg_ts_mode_t", "cprimod_rsvd4_msg_ts_mode_t" , 0 , 0}, 4833 {"_shr_cpri_roe_frame_format_t", "cprimod_cpri_roe_frame_format_t" , 0 , 0}, 4834 {"bcm_mac_t", "cprimod_mac_addr_t" , 0 , 0}, 4835 {"_shr_cpri_cw_l1_protocol_info_t", "cprimod_cpri_cw_l1_protocol_info_t" , 0 , 0}, 4836 {"_shr_cpri_hdlc_fcs_size_t", "cprimod_cpri_hdlc_fcs_size_t" , 0 , 0}, 4837 {"_shr_cpri_hdlc_filling_flag_pattern_t", "cprimod_cpri_hdlc_filling_flag_pattern_t" , 0 , 0}, 4838 {"_shr_cpri_hdlc_flag_size_t", "cprimod_cpri_hdlc_num_flag_bytes_t" , 0 , 0}, 4839 {"_shr_cpri_hdlc_crc_mode_t", "cprimod_cpri_crc_mode_t" , 0 , 0}, 4840 {"_shr_cpri_hdlc_crc_init_val_t", "cprimod_cpri_hdlc_crc_init_val_t" , 0 , 0}, 4841 {"_shr_cpri_vsd_control_subchan_num_bytes_t", "cprimod_cpri_vsd_control_subchan_num_bytes_t" , 0 , 0}, 4842 {"_shr_cpri_vsd_control_subchan_size_t", "cprimod_cpri_vsd_control_subchan_size_t" , 0 , 0}, 4843 {"_shr_cpri_vsd_control_flow_num_bytes_t", "cprimod_cpri_vsd_control_flow_num_bytes_t" , 0 , 0}, 4844 {"_shr_cpri_rx_vsd_flow_info_t", "cprimod_cpri_rx_vsd_flow_info_t" , 0 , 0}, 4845 {"_shr_cpri_tx_vsd_flow_info_t", "cprimod_cpri_tx_vsd_flow_info_t" , 0 , 0}, 4846 {"_shr_cpri_cw_filter_mode_t", "cprimod_cpri_cw_filter_mode_t" , 0 , 0}, 4847 {"_shr_vsd_raw_map_mode_t", "cprimod_cpri_vsd_raw_map_mode_t" , 0 , 0}, 4848 {"_shr_cpri_gcw_mask_t", "cprimod_cpri_gcw_mask_t" , 0 , 0}, 4849 {"_shr_cpri_cw_l1_config_info_t", "cprimod_cpri_cw_l1_config_info_t" , 0 , 0}, 4850 {"_shr_rsvd4_control_msg_proc_type_t", "cprimod_control_msg_proc_type_t" , 0 , 0}, 4851 {"_shr_rsvd4_sync_count_cycle_t", "cprimod_sync_count_cycle_t" , 0 , 0}, 4852 {"_shr_cpri_tag_gen_entry_t", "cprimod_tag_gen_entry_t" , 0 , 0}, 4853 {"_shr_cpri_tag_option_t", "cprimod_cpri_tag_option_t" , 0 , 0}, 4854 {"_shr_rsvd4_crc_option_t", "cprimod_cpri_crc_option_t" , 0 , 0}, 4855 {"_shr_cpri_fast_eth_config_t", "cprimod_cpri_fast_eth_config_t" , 0 , 0}, 4856 {"_shr_cpri_port_interrupt_callback_t", "cprimod_cpri_port_interrupt_callback_t" , 0 , 0}, 4857 {"_shr_cpri_interrupt_type_t", "cprimod_cpri_port_intr_type_t" , 0 , 0}, 4858 {"_shr_cpri_intr_info_t", "cprimod_cpri_intr_info_t" , 0 , 0}, 4859 {"_shr_cpri_1588_ts_type_t", "cprimod_1588_ts_type_t" , 0 , 0}, 4860 {"_shr_cpri_dir_t", "cprimod_direction_t" , 0 , 0}, 4861 {"_shr_cpri_roe_payload_multiple_t", "cprimod_cpri_roe_payload_multiple_t" , 0 , 0}, 4862 {"_shr_cpri_roe_ordering_info_option_t", "cprimod_cpri_roe_ordering_info_option_t" , 0 , 0}, 4863 {"_shr_cpri_fec_ts_source_t", "cprimod_fec_ts_source_t" , 0 , 0}, 4864 {"_shr_cpri_fec_aux_config_t", "cprimod_fec_aux_config_para_t" , 0 , 0}, 4865 {"_shr_cpri_roe_header_field_t", "cprimod_cpri_roe_header_field_t" , 0 , 0}, 4866 {"_shr_cpri_ecpri_header_field_t", "cprimod_cpri_ecpri_header_field_t" , 0 , 0}, 4867 { NULL } 4868 }; 4869 4870 4871 cint_data_t cprimod_cint_data = 4872 { 4873 NULL, 4874 __cint_functions, 4875 __cint_structures, 4876 __cint_enums, 4877 __cint_typedefs, 4878 __cint_constants, 4879 __cint_function_pointers, 4880 }; 4881 4882 4883 #endif /* defined(CPRIMOD_SUPPORT) */ 4884 4885 #endif /* defined(INCLUDE_LIB_CINT) */