openbcm

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wh2sanity.soc (64068B)

      1 # 
      2 # This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      3 # 
      4 # Copyright 2007-2019 Broadcom Inc. All rights reserved.
      5 
      6 # Wolfhound2 (BCM53540) Sanity
      7 #
      8 # Script to run all available tests as quickly as possible.
      9 # For testing basic sanity of new drivers, simulators, chips, etc.
     10 #
     11 
     12 echo "testsuite: started: sanity"
     13 rcload rc.soc
     14 counter off
     15 l2mode off
     16 
     17 # We need to print out port status since any cabling effects results.
     18 *:ps
     19 
     20 # Avoid link messages while testing
     21 linkscan off
     22 
     23 init
     24 init misc
     25 init mmu
     26 
     27 local done 'echo "   Done"'
     28 
     29 # Set run command script not to fail on errors reported by commands
     30 # this allows the script to continue if a test fails
     31 set rcerror=false
     32 
     33 # Set up test mode: don't stop on errors, show progress on each test
     34 tm -stoponerror +progress
     35 # Unselect all
     36 ts -*
     37 
     38 #Display some useful information
     39 date
     40 ver
     41 soc
     42 
     43 #Start Test
     44 if !$?ihost_mode \
     45     'echo "Running PCI Compliance ...";\
     46      tr 2;\
     47      $done;'
     48 
     49 #Start Test
     50 echo "Running PCI S-Channel Buf ..."
     51 tr 4
     52 $done
     53 
     54 echo "Running Register reset defaults ..."
     55 tr 1
     56 $done
     57 
     58 echo "Running Register read/write ..."
     59 tr 3 mask64
     60 $done
     61 
     62 init soc; init misc; init mmu;
     63 #Clean up after register read/write test.
     64 
     65 rcload rc.soc
     66 counter off
     67 l2mode off
     68 echo "Running CPU Benchmarks ..."
     69 tr 21
     70 $done
     71 
     72 set rct=false
     73 
     74 echo "Running Switching Memory Tests ..."
     75 
     76 #Need to init misc before testing for MMU_XQ0, 1 ~29
     77 init soc; init misc;
     78 
     79 echo " MMU_XQ0";
     80 tr 50 M=MMU_XQ0;
     81 tr 51 M=MMU_XQ0;
     82 tr 52 M=MMU_XQ0;
     83 tr 71 M=MMU_XQ0 TSE=F SLTH=T;
     84 tr 71 M=MMU_XQ0 TSE=T SLTH=T;
     85 tr 71 M=MMU_XQ0 TSE=T SLTH=F;
     86 echo " MMU_XQ10";
     87 tr 50 M=MMU_XQ10;
     88 tr 51 M=MMU_XQ10;
     89 tr 52 M=MMU_XQ10;
     90 tr 71 M=MMU_XQ10 TSE=F SLTH=T;
     91 tr 71 M=MMU_XQ10 TSE=T SLTH=T;
     92 tr 71 M=MMU_XQ10 TSE=T SLTH=F;
     93 echo " MMU_XQ11";
     94 tr 50 M=MMU_XQ11;
     95 tr 51 M=MMU_XQ11;
     96 tr 52 M=MMU_XQ11;
     97 tr 71 M=MMU_XQ11 TSE=F SLTH=T;
     98 tr 71 M=MMU_XQ11 TSE=T SLTH=T;
     99 tr 71 M=MMU_XQ11 TSE=T SLTH=F;
    100 echo " MMU_XQ12";
    101 tr 50 M=MMU_XQ12;
    102 tr 51 M=MMU_XQ12;
    103 tr 52 M=MMU_XQ12;
    104 tr 71 M=MMU_XQ12 TSE=F SLTH=T;
    105 tr 71 M=MMU_XQ12 TSE=T SLTH=T;
    106 tr 71 M=MMU_XQ12 TSE=T SLTH=F;
    107 echo " MMU_XQ13";
    108 tr 50 M=MMU_XQ13;
    109 tr 51 M=MMU_XQ13;
    110 tr 52 M=MMU_XQ13;
    111 tr 71 M=MMU_XQ13 TSE=F SLTH=T;
    112 tr 71 M=MMU_XQ13 TSE=T SLTH=T;
    113 tr 71 M=MMU_XQ13 TSE=T SLTH=F;
    114 echo " MMU_XQ14";
    115 tr 50 M=MMU_XQ14;
    116 tr 51 M=MMU_XQ14;
    117 tr 52 M=MMU_XQ14;
    118 tr 71 M=MMU_XQ14 TSE=F SLTH=T;
    119 tr 71 M=MMU_XQ14 TSE=T SLTH=T;
    120 tr 71 M=MMU_XQ14 TSE=T SLTH=F;
    121 echo " MMU_XQ15";
    122 tr 50 M=MMU_XQ15;
    123 tr 51 M=MMU_XQ15;
    124 tr 52 M=MMU_XQ15;
    125 tr 71 M=MMU_XQ15 TSE=F SLTH=T;
    126 tr 71 M=MMU_XQ15 TSE=T SLTH=T;
    127 tr 71 M=MMU_XQ15 TSE=T SLTH=F;
    128 echo " MMU_XQ16";
    129 tr 50 M=MMU_XQ16;
    130 tr 51 M=MMU_XQ16;
    131 tr 52 M=MMU_XQ16;
    132 tr 71 M=MMU_XQ16 TSE=F SLTH=T;
    133 tr 71 M=MMU_XQ16 TSE=T SLTH=T;
    134 tr 71 M=MMU_XQ16 TSE=T SLTH=F;
    135 echo " MMU_XQ17";
    136 tr 50 M=MMU_XQ17;
    137 tr 51 M=MMU_XQ17;
    138 tr 52 M=MMU_XQ17;
    139 tr 71 M=MMU_XQ17 TSE=F SLTH=T;
    140 tr 71 M=MMU_XQ17 TSE=T SLTH=T;
    141 tr 71 M=MMU_XQ17 TSE=T SLTH=F;
    142 echo " MMU_XQ18";
    143 tr 50 M=MMU_XQ18;
    144 tr 51 M=MMU_XQ18;
    145 tr 52 M=MMU_XQ18;
    146 tr 71 M=MMU_XQ18 TSE=F SLTH=T;
    147 tr 71 M=MMU_XQ18 TSE=T SLTH=T;
    148 tr 71 M=MMU_XQ18 TSE=T SLTH=F;
    149 echo " MMU_XQ19";
    150 tr 50 M=MMU_XQ19;
    151 tr 51 M=MMU_XQ19;
    152 tr 52 M=MMU_XQ19;
    153 tr 71 M=MMU_XQ19 TSE=F SLTH=T;
    154 tr 71 M=MMU_XQ19 TSE=T SLTH=T;
    155 tr 71 M=MMU_XQ19 TSE=T SLTH=F;
    156 echo " MMU_XQ2";
    157 tr 50 M=MMU_XQ2;
    158 tr 51 M=MMU_XQ2;
    159 tr 52 M=MMU_XQ2;
    160 tr 71 M=MMU_XQ2 TSE=F SLTH=T;
    161 tr 71 M=MMU_XQ2 TSE=T SLTH=T;
    162 tr 71 M=MMU_XQ2 TSE=T SLTH=F;
    163 echo " MMU_XQ20";
    164 tr 50 M=MMU_XQ20;
    165 tr 51 M=MMU_XQ20;
    166 tr 52 M=MMU_XQ20;
    167 tr 71 M=MMU_XQ20 TSE=F SLTH=T;
    168 tr 71 M=MMU_XQ20 TSE=T SLTH=T;
    169 tr 71 M=MMU_XQ20 TSE=T SLTH=F;
    170 echo " MMU_XQ21";
    171 tr 50 M=MMU_XQ21;
    172 tr 51 M=MMU_XQ21;
    173 tr 52 M=MMU_XQ21;
    174 tr 71 M=MMU_XQ21 TSE=F SLTH=T;
    175 tr 71 M=MMU_XQ21 TSE=T SLTH=T;
    176 tr 71 M=MMU_XQ21 TSE=T SLTH=F;
    177 echo " MMU_XQ22";
    178 tr 50 M=MMU_XQ22;
    179 tr 51 M=MMU_XQ22;
    180 tr 52 M=MMU_XQ22;
    181 tr 71 M=MMU_XQ22 TSE=F SLTH=T;
    182 tr 71 M=MMU_XQ22 TSE=T SLTH=T;
    183 tr 71 M=MMU_XQ22 TSE=T SLTH=F;
    184 echo " MMU_XQ23";
    185 tr 50 M=MMU_XQ23;
    186 tr 51 M=MMU_XQ23;
    187 tr 52 M=MMU_XQ23;
    188 tr 71 M=MMU_XQ23 TSE=F SLTH=T;
    189 tr 71 M=MMU_XQ23 TSE=T SLTH=T;
    190 tr 71 M=MMU_XQ23 TSE=T SLTH=F;
    191 echo " MMU_XQ24";
    192 tr 50 M=MMU_XQ24;
    193 tr 51 M=MMU_XQ24;
    194 tr 52 M=MMU_XQ24;
    195 tr 71 M=MMU_XQ24 TSE=F SLTH=T;
    196 tr 71 M=MMU_XQ24 TSE=T SLTH=T;
    197 tr 71 M=MMU_XQ24 TSE=T SLTH=F;
    198 echo " MMU_XQ25";
    199 tr 50 M=MMU_XQ25;
    200 tr 51 M=MMU_XQ25;
    201 tr 52 M=MMU_XQ25;
    202 tr 71 M=MMU_XQ25 TSE=F SLTH=T;
    203 tr 71 M=MMU_XQ25 TSE=T SLTH=T;
    204 tr 71 M=MMU_XQ25 TSE=T SLTH=F;
    205 echo " MMU_XQ26";
    206 tr 50 M=MMU_XQ26;
    207 tr 51 M=MMU_XQ26;
    208 tr 52 M=MMU_XQ26;
    209 tr 71 M=MMU_XQ26 TSE=F SLTH=T;
    210 tr 71 M=MMU_XQ26 TSE=T SLTH=T;
    211 tr 71 M=MMU_XQ26 TSE=T SLTH=F;
    212 echo " MMU_XQ27";
    213 tr 50 M=MMU_XQ27;
    214 tr 51 M=MMU_XQ27;
    215 tr 52 M=MMU_XQ27;
    216 tr 71 M=MMU_XQ27 TSE=F SLTH=T;
    217 tr 71 M=MMU_XQ27 TSE=T SLTH=T;
    218 tr 71 M=MMU_XQ27 TSE=T SLTH=F;
    219 echo " MMU_XQ28";
    220 tr 50 M=MMU_XQ28;
    221 tr 51 M=MMU_XQ28;
    222 tr 52 M=MMU_XQ28;
    223 tr 71 M=MMU_XQ28 TSE=F SLTH=T;
    224 tr 71 M=MMU_XQ28 TSE=T SLTH=T;
    225 tr 71 M=MMU_XQ28 TSE=T SLTH=F;
    226 echo " MMU_XQ29";
    227 tr 50 M=MMU_XQ29;
    228 tr 51 M=MMU_XQ29;
    229 tr 52 M=MMU_XQ29;
    230 tr 71 M=MMU_XQ29 TSE=F SLTH=T;
    231 tr 71 M=MMU_XQ29 TSE=T SLTH=T;
    232 tr 71 M=MMU_XQ29 TSE=T SLTH=F;
    233 echo " MMU_XQ3";
    234 tr 50 M=MMU_XQ3;
    235 tr 51 M=MMU_XQ3;
    236 tr 52 M=MMU_XQ3;
    237 tr 71 M=MMU_XQ3 TSE=F SLTH=T;
    238 tr 71 M=MMU_XQ3 TSE=T SLTH=T;
    239 tr 71 M=MMU_XQ3 TSE=T SLTH=F;
    240 echo " MMU_XQ4";
    241 tr 50 M=MMU_XQ4;
    242 tr 51 M=MMU_XQ4;
    243 tr 52 M=MMU_XQ4;
    244 tr 71 M=MMU_XQ4 TSE=F SLTH=T;
    245 tr 71 M=MMU_XQ4 TSE=T SLTH=T;
    246 tr 71 M=MMU_XQ4 TSE=T SLTH=F;
    247 echo " MMU_XQ5";
    248 tr 50 M=MMU_XQ5;
    249 tr 51 M=MMU_XQ5;
    250 tr 52 M=MMU_XQ5;
    251 tr 71 M=MMU_XQ5 TSE=F SLTH=T;
    252 tr 71 M=MMU_XQ5 TSE=T SLTH=T;
    253 tr 71 M=MMU_XQ5 TSE=T SLTH=F;
    254 echo " MMU_XQ6";
    255 tr 50 M=MMU_XQ6;
    256 tr 51 M=MMU_XQ6;
    257 tr 52 M=MMU_XQ6;
    258 tr 71 M=MMU_XQ6 TSE=F SLTH=T;
    259 tr 71 M=MMU_XQ6 TSE=T SLTH=T;
    260 tr 71 M=MMU_XQ6 TSE=T SLTH=F;
    261 echo " MMU_XQ7";
    262 tr 50 M=MMU_XQ7;
    263 tr 51 M=MMU_XQ7;
    264 tr 52 M=MMU_XQ7;
    265 tr 71 M=MMU_XQ7 TSE=F SLTH=T;
    266 tr 71 M=MMU_XQ7 TSE=T SLTH=T;
    267 tr 71 M=MMU_XQ7 TSE=T SLTH=F;
    268 echo " MMU_XQ8";
    269 tr 50 M=MMU_XQ8;
    270 tr 51 M=MMU_XQ8;
    271 tr 52 M=MMU_XQ8;
    272 tr 71 M=MMU_XQ8 TSE=F SLTH=T;
    273 tr 71 M=MMU_XQ8 TSE=T SLTH=T;
    274 tr 71 M=MMU_XQ8 TSE=T SLTH=F;
    275 echo " MMU_XQ9";
    276 tr 50 M=MMU_XQ9;
    277 tr 51 M=MMU_XQ9;
    278 tr 52 M=MMU_XQ9;
    279 tr 71 M=MMU_XQ9 TSE=F SLTH=T;
    280 tr 71 M=MMU_XQ9 TSE=T SLTH=T;
    281 tr 71 M=MMU_XQ9 TSE=T SLTH=F;
    282 
    283 init soc; init mmu;
    284 
    285 echo " ALTERNATE_EMIRROR_BITMAP";
    286 tr 50 M=ALTERNATE_EMIRROR_BITMAP;
    287 tr 51 M=ALTERNATE_EMIRROR_BITMAP;
    288 tr 52 M=ALTERNATE_EMIRROR_BITMAP;
    289 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=F SLTH=T;
    290 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=T SLTH=T;
    291 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=T SLTH=F;
    292 echo " CNG_MAP";
    293 tr 50 M=CNG_MAP;
    294 tr 51 M=CNG_MAP;
    295 tr 52 M=CNG_MAP;
    296 tr 71 M=CNG_MAP TSE=F SLTH=T;
    297 tr 71 M=CNG_MAP TSE=T SLTH=T;
    298 tr 71 M=CNG_MAP TSE=T SLTH=F;
    299 echo " CPU_COS_MAP";
    300 tr 50 M=CPU_COS_MAP;
    301 tr 51 M=CPU_COS_MAP;
    302 tr 52 M=CPU_COS_MAP;
    303 tr 71 M=CPU_COS_MAP TSE=F SLTH=T;
    304 tr 71 M=CPU_COS_MAP TSE=T SLTH=T;
    305 tr 71 M=CPU_COS_MAP TSE=T SLTH=F;
    306 echo " CPU_COS_MAP_DATA_ONLY";
    307 tr 50 M=CPU_COS_MAP_DATA_ONLY;
    308 tr 51 M=CPU_COS_MAP_DATA_ONLY;
    309 tr 52 M=CPU_COS_MAP_DATA_ONLY;
    310 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=F SLTH=T;
    311 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=T SLTH=T;
    312 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=T SLTH=F;
    313 echo " CPU_COS_MAP_ONLY";
    314 tr 50 M=CPU_COS_MAP_ONLY;
    315 tr 51 M=CPU_COS_MAP_ONLY;
    316 tr 52 M=CPU_COS_MAP_ONLY;
    317 tr 71 M=CPU_COS_MAP_ONLY TSE=F SLTH=T;
    318 tr 71 M=CPU_COS_MAP_ONLY TSE=T SLTH=T;
    319 tr 71 M=CPU_COS_MAP_ONLY TSE=T SLTH=F;
    320 echo " CPU_TS_MAP";
    321 tr 50 M=CPU_TS_MAP;
    322 tr 51 M=CPU_TS_MAP;
    323 tr 52 M=CPU_TS_MAP;
    324 tr 71 M=CPU_TS_MAP TSE=F SLTH=T;
    325 tr 71 M=CPU_TS_MAP TSE=T SLTH=T;
    326 tr 71 M=CPU_TS_MAP TSE=T SLTH=F;
    327 echo " CUSTOM_HEADER_MATCH";
    328 tr 50 M=CUSTOM_HEADER_MATCH;
    329 tr 51 M=CUSTOM_HEADER_MATCH;
    330 tr 52 M=CUSTOM_HEADER_MATCH;
    331 tr 71 M=CUSTOM_HEADER_MATCH TSE=F SLTH=T;
    332 tr 71 M=CUSTOM_HEADER_MATCH TSE=T SLTH=T;
    333 tr 71 M=CUSTOM_HEADER_MATCH TSE=T SLTH=F;
    334 echo " CUSTOM_HEADER_POLICY_TABLE";
    335 tr 50 M=CUSTOM_HEADER_POLICY_TABLE;
    336 tr 51 M=CUSTOM_HEADER_POLICY_TABLE;
    337 tr 52 M=CUSTOM_HEADER_POLICY_TABLE;
    338 tr 71 M=CUSTOM_HEADER_POLICY_TABLE TSE=F SLTH=T;
    339 tr 71 M=CUSTOM_HEADER_POLICY_TABLE TSE=T SLTH=T;
    340 tr 71 M=CUSTOM_HEADER_POLICY_TABLE TSE=T SLTH=F;
    341 echo " DSCP_TABLE";
    342 tr 50 M=DSCP_TABLE;
    343 tr 51 M=DSCP_TABLE;
    344 tr 52 M=DSCP_TABLE;
    345 tr 71 M=DSCP_TABLE TSE=F SLTH=T;
    346 tr 71 M=DSCP_TABLE TSE=T SLTH=T;
    347 tr 71 M=DSCP_TABLE TSE=T SLTH=F;
    348 echo " E2E_HOL_STATUS";
    349 tr 50 M=E2E_HOL_STATUS;
    350 tr 51 M=E2E_HOL_STATUS;
    351 tr 52 M=E2E_HOL_STATUS;
    352 tr 71 M=E2E_HOL_STATUS TSE=F SLTH=T;
    353 tr 71 M=E2E_HOL_STATUS TSE=T SLTH=T;
    354 tr 71 M=E2E_HOL_STATUS TSE=T SLTH=F;
    355 echo " FP_GLOBAL_MASK_TCAM";
    356 tr 50 M=FP_GLOBAL_MASK_TCAM;
    357 tr 51 M=FP_GLOBAL_MASK_TCAM;
    358 tr 52 M=FP_GLOBAL_MASK_TCAM;
    359 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=F SLTH=T;
    360 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=T;
    361 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=F;
    362 
    363 echo " FP_TCAM";
    364 tr 50 M=FP_TCAM;
    365 tr 51 M=FP_TCAM;
    366 tr 52 M=FP_TCAM;
    367 tr 71 M=FP_TCAM TSE=F SLTH=T;
    368 tr 71 M=FP_TCAM TSE=T SLTH=T;
    369 tr 71 M=FP_TCAM TSE=T SLTH=F;
    370 
    371 echo " EGR_1588_SA";
    372 tr 50 M=EGR_1588_SA;
    373 tr 51 M=EGR_1588_SA;
    374 tr 52 M=EGR_1588_SA;
    375 tr 71 M=EGR_1588_SA TSE=F SLTH=T;
    376 tr 71 M=EGR_1588_SA TSE=T SLTH=T;
    377 tr 71 M=EGR_1588_SA TSE=T SLTH=F;
    378 echo " EGR_DSCP_ECN_MAP";
    379 tr 50 M=EGR_DSCP_ECN_MAP;
    380 tr 51 M=EGR_DSCP_ECN_MAP;
    381 tr 52 M=EGR_DSCP_ECN_MAP;
    382 tr 71 M=EGR_DSCP_ECN_MAP TSE=F SLTH=T;
    383 tr 71 M=EGR_DSCP_ECN_MAP TSE=T SLTH=T;
    384 tr 71 M=EGR_DSCP_ECN_MAP TSE=T SLTH=F;
    385 echo " EGR_DSCP_TABLE";
    386 tr 50 M=EGR_DSCP_TABLE;
    387 tr 51 M=EGR_DSCP_TABLE;
    388 tr 52 M=EGR_DSCP_TABLE;
    389 tr 71 M=EGR_DSCP_TABLE TSE=F SLTH=T;
    390 tr 71 M=EGR_DSCP_TABLE TSE=T SLTH=T;
    391 tr 71 M=EGR_DSCP_TABLE TSE=T SLTH=F;
    392 echo " EGR_EDB_XMIT_CTRL";
    393 tr 50 M=EGR_EDB_XMIT_CTRL;
    394 tr 51 M=EGR_EDB_XMIT_CTRL;
    395 tr 52 M=EGR_EDB_XMIT_CTRL;
    396 tr 71 M=EGR_EDB_XMIT_CTRL TSE=F SLTH=T;
    397 tr 71 M=EGR_EDB_XMIT_CTRL TSE=T SLTH=T;
    398 tr 71 M=EGR_EDB_XMIT_CTRL TSE=T SLTH=F;
    399 echo " EGR_EM_MTP_INDEX";
    400 tr 50 M=EGR_EM_MTP_INDEX;
    401 tr 51 M=EGR_EM_MTP_INDEX;
    402 tr 52 M=EGR_EM_MTP_INDEX;
    403 tr 71 M=EGR_EM_MTP_INDEX TSE=F SLTH=T;
    404 tr 71 M=EGR_EM_MTP_INDEX TSE=T SLTH=T;
    405 tr 71 M=EGR_EM_MTP_INDEX TSE=T SLTH=F;
    406 echo " EGR_ENABLE";
    407 tr 50 M=EGR_ENABLE;
    408 tr 51 M=EGR_ENABLE;
    409 tr 52 M=EGR_ENABLE;
    410 tr 71 M=EGR_ENABLE TSE=F SLTH=T;
    411 tr 71 M=EGR_ENABLE TSE=T SLTH=T;
    412 tr 71 M=EGR_ENABLE TSE=T SLTH=F;
    413 echo " EGR_ETAG_PCP_MAPPING";
    414 tr 50 M=EGR_ETAG_PCP_MAPPING;
    415 tr 51 M=EGR_ETAG_PCP_MAPPING;
    416 tr 52 M=EGR_ETAG_PCP_MAPPING;
    417 tr 71 M=EGR_ETAG_PCP_MAPPING TSE=F SLTH=T;
    418 tr 71 M=EGR_ETAG_PCP_MAPPING TSE=T SLTH=T;
    419 tr 71 M=EGR_ETAG_PCP_MAPPING TSE=T SLTH=F;
    420 echo " EGR_GPP_ATTRIBUTES";
    421 tr 50 M=EGR_GPP_ATTRIBUTES;
    422 tr 51 M=EGR_GPP_ATTRIBUTES;
    423 tr 52 M=EGR_GPP_ATTRIBUTES;
    424 tr 71 M=EGR_GPP_ATTRIBUTES TSE=F SLTH=T;
    425 tr 71 M=EGR_GPP_ATTRIBUTES TSE=T SLTH=T;
    426 tr 71 M=EGR_GPP_ATTRIBUTES TSE=T SLTH=F;
    427 echo " EGR_GPP_ATTRIBUTES_MODBASE";
    428 tr 50 M=EGR_GPP_ATTRIBUTES_MODBASE;
    429 tr 51 M=EGR_GPP_ATTRIBUTES_MODBASE;
    430 tr 52 M=EGR_GPP_ATTRIBUTES_MODBASE;
    431 tr 71 M=EGR_GPP_ATTRIBUTES_MODBASE TSE=F SLTH=T;
    432 tr 71 M=EGR_GPP_ATTRIBUTES_MODBASE TSE=T SLTH=T;
    433 tr 71 M=EGR_GPP_ATTRIBUTES_MODBASE TSE=T SLTH=F;
    434 echo " EGR_HEADER_ENCAP_DATA";
    435 tr 50 M=EGR_HEADER_ENCAP_DATA;
    436 tr 51 M=EGR_HEADER_ENCAP_DATA;
    437 tr 52 M=EGR_HEADER_ENCAP_DATA;
    438 tr 71 M=EGR_HEADER_ENCAP_DATA TSE=F SLTH=T;
    439 tr 71 M=EGR_HEADER_ENCAP_DATA TSE=T SLTH=T;
    440 tr 71 M=EGR_HEADER_ENCAP_DATA TSE=T SLTH=F;
    441 echo " EGR_IM_MTP_INDEX";
    442 tr 50 M=EGR_IM_MTP_INDEX;
    443 tr 51 M=EGR_IM_MTP_INDEX;
    444 tr 52 M=EGR_IM_MTP_INDEX;
    445 tr 71 M=EGR_IM_MTP_INDEX TSE=F SLTH=T;
    446 tr 71 M=EGR_IM_MTP_INDEX TSE=T SLTH=T;
    447 tr 71 M=EGR_IM_MTP_INDEX TSE=T SLTH=F;
    448 echo " EGR_INT_CN_TO_IP_MAPPING";
    449 tr 50 M=EGR_INT_CN_TO_IP_MAPPING;
    450 tr 51 M=EGR_INT_CN_TO_IP_MAPPING;
    451 tr 52 M=EGR_INT_CN_TO_IP_MAPPING;
    452 tr 71 M=EGR_INT_CN_TO_IP_MAPPING TSE=F SLTH=T;
    453 tr 71 M=EGR_INT_CN_TO_IP_MAPPING TSE=T SLTH=T;
    454 tr 71 M=EGR_INT_CN_TO_IP_MAPPING TSE=T SLTH=F;
    455 echo " EGR_INT_CN_UPDATE";
    456 tr 50 M=EGR_INT_CN_UPDATE;
    457 tr 51 M=EGR_INT_CN_UPDATE;
    458 tr 52 M=EGR_INT_CN_UPDATE;
    459 tr 71 M=EGR_INT_CN_UPDATE TSE=F SLTH=T;
    460 tr 71 M=EGR_INT_CN_UPDATE TSE=T SLTH=T;
    461 tr 71 M=EGR_INT_CN_UPDATE TSE=T SLTH=F;
    462 echo " EGR_L3_INTF";
    463 tr 50 M=EGR_L3_INTF;
    464 tr 51 M=EGR_L3_INTF;
    465 tr 52 M=EGR_L3_INTF;
    466 tr 71 M=EGR_L3_INTF TSE=F SLTH=T;
    467 tr 71 M=EGR_L3_INTF TSE=T SLTH=T;
    468 tr 71 M=EGR_L3_INTF TSE=T SLTH=F;
    469 echo " EGR_L3_NEXT_HOP";
    470 tr 50 M=EGR_L3_NEXT_HOP;
    471 tr 51 M=EGR_L3_NEXT_HOP;
    472 tr 52 M=EGR_L3_NEXT_HOP;
    473 tr 71 M=EGR_L3_NEXT_HOP TSE=F SLTH=T;
    474 tr 71 M=EGR_L3_NEXT_HOP TSE=T SLTH=T;
    475 tr 71 M=EGR_L3_NEXT_HOP TSE=T SLTH=F;
    476 echo " EGR_MAC_DA_PROFILE";
    477 tr 50 M=EGR_MAC_DA_PROFILE;
    478 tr 51 M=EGR_MAC_DA_PROFILE;
    479 tr 52 M=EGR_MAC_DA_PROFILE;
    480 tr 71 M=EGR_MAC_DA_PROFILE TSE=F SLTH=T;
    481 tr 71 M=EGR_MAC_DA_PROFILE TSE=T SLTH=T;
    482 tr 71 M=EGR_MAC_DA_PROFILE TSE=T SLTH=F;
    483 echo " EGR_MASK";
    484 tr 50 M=EGR_MASK;
    485 tr 51 M=EGR_MASK;
    486 tr 52 M=EGR_MASK;
    487 tr 71 M=EGR_MASK TSE=F SLTH=T;
    488 tr 71 M=EGR_MASK TSE=T SLTH=T;
    489 tr 71 M=EGR_MASK TSE=T SLTH=F;
    490 echo " EGR_MASK_MODBASE";
    491 tr 50 M=EGR_MASK_MODBASE;
    492 tr 51 M=EGR_MASK_MODBASE;
    493 tr 52 M=EGR_MASK_MODBASE;
    494 tr 71 M=EGR_MASK_MODBASE TSE=F SLTH=T;
    495 tr 71 M=EGR_MASK_MODBASE TSE=T SLTH=T;
    496 tr 71 M=EGR_MASK_MODBASE TSE=T SLTH=F;
    497 #echo " EGR_MAX_USED_ENTRIES";
    498 #tr 50 M=EGR_MAX_USED_ENTRIES;
    499 #tr 51 M=EGR_MAX_USED_ENTRIES;
    500 #tr 52 M=EGR_MAX_USED_ENTRIES;
    501 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=F SLTH=T;
    502 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=T SLTH=T;
    503 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=T SLTH=F;
    504 echo " EGR_MIRROR_ENCAP_CONTROL";
    505 tr 50 M=EGR_MIRROR_ENCAP_CONTROL;
    506 tr 51 M=EGR_MIRROR_ENCAP_CONTROL;
    507 tr 52 M=EGR_MIRROR_ENCAP_CONTROL;
    508 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=F SLTH=T;
    509 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=T SLTH=T;
    510 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=T SLTH=F;
    511 echo " EGR_MIRROR_ENCAP_DATA_1";
    512 tr 50 M=EGR_MIRROR_ENCAP_DATA_1;
    513 tr 51 M=EGR_MIRROR_ENCAP_DATA_1;
    514 tr 52 M=EGR_MIRROR_ENCAP_DATA_1;
    515 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=F SLTH=T;
    516 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=T SLTH=T;
    517 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=T SLTH=F;
    518 echo " EGR_MIRROR_ENCAP_DATA_2";
    519 tr 50 M=EGR_MIRROR_ENCAP_DATA_2;
    520 tr 51 M=EGR_MIRROR_ENCAP_DATA_2;
    521 tr 52 M=EGR_MIRROR_ENCAP_DATA_2;
    522 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=F SLTH=T;
    523 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=T SLTH=T;
    524 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=T SLTH=F;
    525 #echo " EGR_MMU_REQUESTS";
    526 #tr 50 M=EGR_MMU_REQUESTS;
    527 #tr 51 M=EGR_MMU_REQUESTS;
    528 #tr 52 M=EGR_MMU_REQUESTS;
    529 #tr 71 M=EGR_MMU_REQUESTS TSE=F SLTH=T;
    530 #tr 71 M=EGR_MMU_REQUESTS TSE=T SLTH=T;
    531 #tr 71 M=EGR_MMU_REQUESTS TSE=T SLTH=F;
    532 echo " EGR_MOD_MAP_TABLE";
    533 tr 50 M=EGR_MOD_MAP_TABLE;
    534 tr 51 M=EGR_MOD_MAP_TABLE;
    535 tr 52 M=EGR_MOD_MAP_TABLE;
    536 tr 71 M=EGR_MOD_MAP_TABLE TSE=F SLTH=T;
    537 tr 71 M=EGR_MOD_MAP_TABLE TSE=T SLTH=T;
    538 tr 71 M=EGR_MOD_MAP_TABLE TSE=T SLTH=F;
    539 echo " EGR_MPLS_PRI_MAPPING";
    540 tr 50 M=EGR_MPLS_PRI_MAPPING;
    541 tr 51 M=EGR_MPLS_PRI_MAPPING;
    542 tr 52 M=EGR_MPLS_PRI_MAPPING;
    543 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=F SLTH=T;
    544 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=T SLTH=T;
    545 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=T SLTH=F;
    546 echo " EGR_OAM_MAC_ADDRESS";
    547 tr 50 M=EGR_OAM_MAC_ADDRESS;
    548 tr 51 M=EGR_OAM_MAC_ADDRESS;
    549 tr 52 M=EGR_OAM_MAC_ADDRESS;
    550 tr 71 M=EGR_OAM_MAC_ADDRESS TSE=F SLTH=T;
    551 tr 71 M=EGR_OAM_MAC_ADDRESS TSE=T SLTH=T;
    552 tr 71 M=EGR_OAM_MAC_ADDRESS TSE=T SLTH=F;
    553 echo " EGR_PERQ_XMT_COUNTERS";
    554 tr 50 M=EGR_PERQ_XMT_COUNTERS;
    555 tr 51 M=EGR_PERQ_XMT_COUNTERS;
    556 tr 52 M=EGR_PERQ_XMT_COUNTERS;
    557 tr 71 M=EGR_PERQ_XMT_COUNTERS TSE=F SLTH=T;
    558 tr 71 M=EGR_PERQ_XMT_COUNTERS TSE=T SLTH=T;
    559 tr 71 M=EGR_PERQ_XMT_COUNTERS TSE=T SLTH=F;
    560 echo " EGR_PER_Q_ECN_MARKED";
    561 tr 50 M=EGR_PER_Q_ECN_MARKED;
    562 tr 51 M=EGR_PER_Q_ECN_MARKED;
    563 tr 52 M=EGR_PER_Q_ECN_MARKED;
    564 tr 71 M=EGR_PER_Q_ECN_MARKED TSE=F SLTH=T;
    565 tr 71 M=EGR_PER_Q_ECN_MARKED TSE=T SLTH=T;
    566 tr 71 M=EGR_PER_Q_ECN_MARKED TSE=T SLTH=F;
    567 echo " EGR_PFC_CONTROL";
    568 tr 50 M=EGR_PFC_CONTROL;
    569 tr 51 M=EGR_PFC_CONTROL;
    570 tr 52 M=EGR_PFC_CONTROL;
    571 tr 71 M=EGR_PFC_CONTROL TSE=F SLTH=T;
    572 tr 71 M=EGR_PFC_CONTROL TSE=T SLTH=T;
    573 tr 71 M=EGR_PFC_CONTROL TSE=T SLTH=F;
    574 echo " EGR_PORT_CREDIT_RESET";
    575 tr 50 M=EGR_PORT_CREDIT_RESET;
    576 tr 51 M=EGR_PORT_CREDIT_RESET;
    577 tr 52 M=EGR_PORT_CREDIT_RESET;
    578 tr 71 M=EGR_PORT_CREDIT_RESET TSE=F SLTH=T;
    579 tr 71 M=EGR_PORT_CREDIT_RESET TSE=T SLTH=T;
    580 tr 71 M=EGR_PORT_CREDIT_RESET TSE=T SLTH=F;
    581 #echo " EGR_PORT_REQUESTS";
    582 #tr 50 M=EGR_PORT_REQUESTS;
    583 #tr 51 M=EGR_PORT_REQUESTS;
    584 #tr 52 M=EGR_PORT_REQUESTS;
    585 #tr 71 M=EGR_PORT_REQUESTS TSE=F SLTH=T;
    586 #tr 71 M=EGR_PORT_REQUESTS TSE=T SLTH=T;
    587 #tr 71 M=EGR_PORT_REQUESTS TSE=T SLTH=F;
    588 echo " EGR_PRI_CNG_MAP";
    589 tr 50 M=EGR_PRI_CNG_MAP;
    590 tr 51 M=EGR_PRI_CNG_MAP;
    591 tr 52 M=EGR_PRI_CNG_MAP;
    592 tr 71 M=EGR_PRI_CNG_MAP TSE=F SLTH=T;
    593 tr 71 M=EGR_PRI_CNG_MAP TSE=T SLTH=T;
    594 tr 71 M=EGR_PRI_CNG_MAP TSE=T SLTH=F;
    595 echo " EGR_VLAN";
    596 tr 50 M=EGR_VLAN;
    597 tr 51 M=EGR_VLAN;
    598 tr 52 M=EGR_VLAN;
    599 tr 71 M=EGR_VLAN TSE=F SLTH=T;
    600 tr 71 M=EGR_VLAN TSE=T SLTH=T;
    601 tr 71 M=EGR_VLAN TSE=T SLTH=F;
    602 echo " EGR_VLAN_COUNTER_PRI_COS_MAP";
    603 tr 50 M=EGR_VLAN_COUNTER_PRI_COS_MAP;
    604 tr 51 M=EGR_VLAN_COUNTER_PRI_COS_MAP;
    605 tr 52 M=EGR_VLAN_COUNTER_PRI_COS_MAP;
    606 tr 71 M=EGR_VLAN_COUNTER_PRI_COS_MAP TSE=F SLTH=T;
    607 tr 71 M=EGR_VLAN_COUNTER_PRI_COS_MAP TSE=T SLTH=T;
    608 tr 71 M=EGR_VLAN_COUNTER_PRI_COS_MAP TSE=T SLTH=F;
    609 echo " EGR_VLAN_COUNTER_TABLE";
    610 tr 50 M=EGR_VLAN_COUNTER_TABLE;
    611 tr 51 M=EGR_VLAN_COUNTER_TABLE;
    612 tr 52 M=EGR_VLAN_COUNTER_TABLE;
    613 tr 71 M=EGR_VLAN_COUNTER_TABLE TSE=F SLTH=T;
    614 tr 71 M=EGR_VLAN_COUNTER_TABLE TSE=T SLTH=T;
    615 tr 71 M=EGR_VLAN_COUNTER_TABLE TSE=T SLTH=F;
    616 echo " EGR_VLAN_STG";
    617 tr 50 M=EGR_VLAN_STG;
    618 tr 51 M=EGR_VLAN_STG;
    619 tr 52 M=EGR_VLAN_STG;
    620 tr 71 M=EGR_VLAN_STG TSE=F SLTH=T;
    621 tr 71 M=EGR_VLAN_STG TSE=T SLTH=T;
    622 tr 71 M=EGR_VLAN_STG TSE=T SLTH=F;
    623 echo " EGR_VLAN_TAG_ACTION_PROFILE";
    624 tr 50 M=EGR_VLAN_TAG_ACTION_PROFILE;
    625 tr 51 M=EGR_VLAN_TAG_ACTION_PROFILE;
    626 tr 52 M=EGR_VLAN_TAG_ACTION_PROFILE;
    627 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=F SLTH=T;
    628 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=T;
    629 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=F;
    630 echo " EGR_VLAN_XLATE";
    631 tr 50 M=EGR_VLAN_XLATE;
    632 tr 51 M=EGR_VLAN_XLATE;
    633 tr 52 M=EGR_VLAN_XLATE;
    634 tr 71 M=EGR_VLAN_XLATE TSE=F SLTH=T;
    635 tr 71 M=EGR_VLAN_XLATE TSE=T SLTH=T;
    636 tr 71 M=EGR_VLAN_XLATE TSE=T SLTH=F;
    637 echo " EM_MTP_INDEX";
    638 tr 50 M=EM_MTP_INDEX;
    639 tr 51 M=EM_MTP_INDEX;
    640 tr 52 M=EM_MTP_INDEX;
    641 tr 71 M=EM_MTP_INDEX TSE=F SLTH=T;
    642 tr 71 M=EM_MTP_INDEX TSE=T SLTH=T;
    643 tr 71 M=EM_MTP_INDEX TSE=T SLTH=F;
    644 echo " FP_COUNTER_TABLE";
    645 tr 50 M=FP_COUNTER_TABLE;
    646 tr 51 M=FP_COUNTER_TABLE;
    647 tr 52 M=FP_COUNTER_TABLE;
    648 tr 71 M=FP_COUNTER_TABLE TSE=F SLTH=T;
    649 tr 71 M=FP_COUNTER_TABLE TSE=T SLTH=T;
    650 tr 71 M=FP_COUNTER_TABLE TSE=T SLTH=F;
    651 echo " FP_METER_TABLE";
    652 tr 50 M=FP_METER_TABLE;
    653 tr 51 M=FP_METER_TABLE;
    654 tr 52 M=FP_METER_TABLE;
    655 tr 71 M=FP_METER_TABLE TSE=F SLTH=T;
    656 tr 71 M=FP_METER_TABLE TSE=T SLTH=T;
    657 tr 71 M=FP_METER_TABLE TSE=T SLTH=F;
    658 echo " FP_POLICY_TABLE";
    659 tr 50 M=FP_POLICY_TABLE;
    660 tr 51 M=FP_POLICY_TABLE;
    661 tr 52 M=FP_POLICY_TABLE;
    662 tr 71 M=FP_POLICY_TABLE TSE=F SLTH=T;
    663 tr 71 M=FP_POLICY_TABLE TSE=T SLTH=T;
    664 tr 71 M=FP_POLICY_TABLE TSE=T SLTH=F;
    665 echo " FP_PORT_FIELD_SEL";
    666 tr 50 M=FP_PORT_FIELD_SEL;
    667 tr 51 M=FP_PORT_FIELD_SEL;
    668 tr 52 M=FP_PORT_FIELD_SEL;
    669 tr 71 M=FP_PORT_FIELD_SEL TSE=F SLTH=T;
    670 tr 71 M=FP_PORT_FIELD_SEL TSE=T SLTH=T;
    671 tr 71 M=FP_PORT_FIELD_SEL TSE=T SLTH=F;
    672 echo " FP_PORT_METER_MAP";
    673 tr 50 M=FP_PORT_METER_MAP;
    674 tr 51 M=FP_PORT_METER_MAP;
    675 tr 52 M=FP_PORT_METER_MAP;
    676 tr 71 M=FP_PORT_METER_MAP TSE=F SLTH=T;
    677 tr 71 M=FP_PORT_METER_MAP TSE=T SLTH=T;
    678 tr 71 M=FP_PORT_METER_MAP TSE=T SLTH=F;
    679 echo " FP_RANGE_CHECK";
    680 tr 50 M=FP_RANGE_CHECK;
    681 tr 51 M=FP_RANGE_CHECK;
    682 tr 52 M=FP_RANGE_CHECK;
    683 tr 71 M=FP_RANGE_CHECK TSE=F SLTH=T;
    684 tr 71 M=FP_RANGE_CHECK TSE=T SLTH=T;
    685 tr 71 M=FP_RANGE_CHECK TSE=T SLTH=F;
    686 echo " FP_SLICE_KEY_CONTROL";
    687 tr 50 M=FP_SLICE_KEY_CONTROL;
    688 #tr 51 M=FP_SLICE_KEY_CONTROL;
    689 #tr 52 M=FP_SLICE_KEY_CONTROL;
    690 tr 71 M=FP_SLICE_KEY_CONTROL TSE=F SLTH=T;
    691 tr 71 M=FP_SLICE_KEY_CONTROL TSE=T SLTH=T;
    692 tr 71 M=FP_SLICE_KEY_CONTROL TSE=T SLTH=F;
    693 echo " FP_SLICE_MAP";
    694 tr 50 M=FP_SLICE_MAP;
    695 #tr 51 M=FP_SLICE_MAP;
    696 #tr 52 M=FP_SLICE_MAP;
    697 tr 71 M=FP_SLICE_MAP TSE=F SLTH=T;
    698 tr 71 M=FP_SLICE_MAP TSE=T SLTH=T;
    699 tr 71 M=FP_SLICE_MAP TSE=T SLTH=F;
    700 echo " FP_STORM_CONTROL_METERS";
    701 tr 50 M=FP_STORM_CONTROL_METERS;
    702 tr 51 M=FP_STORM_CONTROL_METERS;
    703 tr 52 M=FP_STORM_CONTROL_METERS;
    704 tr 71 M=FP_STORM_CONTROL_METERS TSE=F SLTH=T;
    705 tr 71 M=FP_STORM_CONTROL_METERS TSE=T SLTH=T;
    706 tr 71 M=FP_STORM_CONTROL_METERS TSE=T SLTH=F;
    707 echo " FP_UDF_OFFSET";
    708 tr 50 M=FP_UDF_OFFSET;
    709 tr 51 M=FP_UDF_OFFSET;
    710 tr 52 M=FP_UDF_OFFSET;
    711 tr 71 M=FP_UDF_OFFSET TSE=F SLTH=T;
    712 tr 71 M=FP_UDF_OFFSET TSE=T SLTH=T;
    713 tr 71 M=FP_UDF_OFFSET TSE=T SLTH=F;
    714 echo " HG_TRUNK_FAILOVER_SET";
    715 tr 50 M=HG_TRUNK_FAILOVER_SET;
    716 tr 51 M=HG_TRUNK_FAILOVER_SET;
    717 tr 52 M=HG_TRUNK_FAILOVER_SET;
    718 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=F SLTH=T;
    719 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=T SLTH=T;
    720 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=T SLTH=F;
    721 echo " IARB_TDM_TABLE";
    722 tr 50 M=IARB_TDM_TABLE;
    723 tr 51 M=IARB_TDM_TABLE;
    724 tr 52 M=IARB_TDM_TABLE;
    725 tr 71 M=IARB_TDM_TABLE TSE=F SLTH=T;
    726 tr 71 M=IARB_TDM_TABLE TSE=T SLTH=T;
    727 tr 71 M=IARB_TDM_TABLE TSE=T SLTH=F;
    728 #echo " IFP_PORT_FIELD_SEL";
    729 #HWALIAS to FP_PORT_FIELD_SEL -- NOTEST
    730 #tr 50 M=IFP_PORT_FIELD_SEL;
    731 #tr 51 M=IFP_PORT_FIELD_SEL;
    732 #tr 52 M=IFP_PORT_FIELD_SEL;
    733 #tr 71 M=IFP_PORT_FIELD_SEL TSE=F SLTH=T;
    734 #tr 71 M=IFP_PORT_FIELD_SEL TSE=T SLTH=T;
    735 #tr 71 M=IFP_PORT_FIELD_SEL TSE=T SLTH=F;
    736 echo " IFP_REDIRECTION_PROFILE";
    737 tr 50 M=IFP_REDIRECTION_PROFILE;
    738 tr 51 M=IFP_REDIRECTION_PROFILE;
    739 tr 52 M=IFP_REDIRECTION_PROFILE;
    740 tr 71 M=IFP_REDIRECTION_PROFILE TSE=F SLTH=T;
    741 tr 71 M=IFP_REDIRECTION_PROFILE TSE=T SLTH=T;
    742 tr 71 M=IFP_REDIRECTION_PROFILE TSE=T SLTH=F;
    743 echo " IM_MTP_INDEX";
    744 tr 50 M=IM_MTP_INDEX;
    745 tr 51 M=IM_MTP_INDEX;
    746 tr 52 M=IM_MTP_INDEX;
    747 tr 71 M=IM_MTP_INDEX TSE=F SLTH=T;
    748 tr 71 M=IM_MTP_INDEX TSE=T SLTH=T;
    749 tr 71 M=IM_MTP_INDEX TSE=T SLTH=F;
    750 echo " ING_1588_INGRESS_CTRL";
    751 tr 50 M=ING_1588_INGRESS_CTRL;
    752 tr 51 M=ING_1588_INGRESS_CTRL;
    753 tr 52 M=ING_1588_INGRESS_CTRL;
    754 tr 71 M=ING_1588_INGRESS_CTRL TSE=F SLTH=T;
    755 tr 71 M=ING_1588_INGRESS_CTRL TSE=T SLTH=T;
    756 tr 71 M=ING_1588_INGRESS_CTRL TSE=T SLTH=F;
    757 echo " ING_ETAG_PCP_MAPPING";
    758 tr 50 M=ING_ETAG_PCP_MAPPING;
    759 tr 51 M=ING_ETAG_PCP_MAPPING;
    760 tr 52 M=ING_ETAG_PCP_MAPPING;
    761 tr 71 M=ING_ETAG_PCP_MAPPING TSE=F SLTH=T;
    762 tr 71 M=ING_ETAG_PCP_MAPPING TSE=T SLTH=T;
    763 tr 71 M=ING_ETAG_PCP_MAPPING TSE=T SLTH=F;
    764 echo " ING_IPV6_MC_RESERVED_ADDRESS";
    765 tr 50 M=ING_IPV6_MC_RESERVED_ADDRESS;
    766 #tr 51 M=ING_IPV6_MC_RESERVED_ADDRESS;
    767 #tr 52 M=ING_IPV6_MC_RESERVED_ADDRESS;
    768 tr 71 M=ING_IPV6_MC_RESERVED_ADDRESS TSE=F SLTH=T;
    769 tr 71 M=ING_IPV6_MC_RESERVED_ADDRESS TSE=T SLTH=T;
    770 tr 71 M=ING_IPV6_MC_RESERVED_ADDRESS TSE=T SLTH=F;
    771 echo " ING_L3_NEXT_HOP";
    772 tr 50 M=ING_L3_NEXT_HOP;
    773 tr 51 M=ING_L3_NEXT_HOP;
    774 tr 52 M=ING_L3_NEXT_HOP;
    775 tr 71 M=ING_L3_NEXT_HOP TSE=F SLTH=T;
    776 tr 71 M=ING_L3_NEXT_HOP TSE=T SLTH=T;
    777 tr 71 M=ING_L3_NEXT_HOP TSE=T SLTH=F;
    778 echo " ING_MOD_MAP_TABLE";
    779 tr 50 M=ING_MOD_MAP_TABLE;
    780 tr 51 M=ING_MOD_MAP_TABLE;
    781 tr 52 M=ING_MOD_MAP_TABLE;
    782 tr 71 M=ING_MOD_MAP_TABLE TSE=F SLTH=T;
    783 tr 71 M=ING_MOD_MAP_TABLE TSE=T SLTH=T;
    784 tr 71 M=ING_MOD_MAP_TABLE TSE=T SLTH=F;
    785 echo " ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE";
    786 tr 50 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE;
    787 tr 51 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE;
    788 tr 52 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE;
    789 tr 71 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE TSE=F SLTH=T;
    790 tr 71 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE TSE=T SLTH=T;
    791 tr 71 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE TSE=T SLTH=F;
    792 echo " ING_PRI_CNG_MAP";
    793 tr 50 M=ING_PRI_CNG_MAP;
    794 tr 51 M=ING_PRI_CNG_MAP;
    795 tr 52 M=ING_PRI_CNG_MAP;
    796 tr 71 M=ING_PRI_CNG_MAP TSE=F SLTH=T;
    797 tr 71 M=ING_PRI_CNG_MAP TSE=T SLTH=T;
    798 tr 71 M=ING_PRI_CNG_MAP TSE=T SLTH=F;
    799 echo " ING_SERVICE_PRI_MAP";
    800 tr 50 M=ING_SERVICE_PRI_MAP;
    801 tr 51 M=ING_SERVICE_PRI_MAP;
    802 tr 52 M=ING_SERVICE_PRI_MAP;
    803 tr 71 M=ING_SERVICE_PRI_MAP TSE=F SLTH=T;
    804 tr 71 M=ING_SERVICE_PRI_MAP TSE=T SLTH=T;
    805 tr 71 M=ING_SERVICE_PRI_MAP TSE=T SLTH=F;
    806 echo " ING_VLAN_COUNTER_PRI_COS_MAP";
    807 tr 50 M=ING_VLAN_COUNTER_PRI_COS_MAP;
    808 tr 51 M=ING_VLAN_COUNTER_PRI_COS_MAP;
    809 tr 52 M=ING_VLAN_COUNTER_PRI_COS_MAP;
    810 tr 71 M=ING_VLAN_COUNTER_PRI_COS_MAP TSE=F SLTH=T;
    811 tr 71 M=ING_VLAN_COUNTER_PRI_COS_MAP TSE=T SLTH=T;
    812 tr 71 M=ING_VLAN_COUNTER_PRI_COS_MAP TSE=T SLTH=F;
    813 echo " ING_VLAN_COUNTER_TABLE";
    814 tr 50 M=ING_VLAN_COUNTER_TABLE;
    815 tr 51 M=ING_VLAN_COUNTER_TABLE;
    816 tr 52 M=ING_VLAN_COUNTER_TABLE;
    817 tr 71 M=ING_VLAN_COUNTER_TABLE TSE=F SLTH=T;
    818 tr 71 M=ING_VLAN_COUNTER_TABLE TSE=T SLTH=T;
    819 tr 71 M=ING_VLAN_COUNTER_TABLE TSE=T SLTH=F;
    820 echo " ING_VLAN_RANGE";
    821 tr 50 M=ING_VLAN_RANGE;
    822 tr 51 M=ING_VLAN_RANGE;
    823 tr 52 M=ING_VLAN_RANGE;
    824 tr 71 M=ING_VLAN_RANGE TSE=F SLTH=T;
    825 tr 71 M=ING_VLAN_RANGE TSE=T SLTH=T;
    826 tr 71 M=ING_VLAN_RANGE TSE=T SLTH=F;
    827 echo " ING_VLAN_TAG_ACTION_PROFILE";
    828 tr 50 M=ING_VLAN_TAG_ACTION_PROFILE;
    829 tr 51 M=ING_VLAN_TAG_ACTION_PROFILE;
    830 tr 52 M=ING_VLAN_TAG_ACTION_PROFILE;
    831 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=F SLTH=T;
    832 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=T;
    833 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=F;
    834 echo " INITIAL_ING_L3_NEXT_HOP";
    835 tr 50 M=INITIAL_ING_L3_NEXT_HOP;
    836 tr 51 M=INITIAL_ING_L3_NEXT_HOP;
    837 tr 52 M=INITIAL_ING_L3_NEXT_HOP;
    838 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=F SLTH=T;
    839 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=T SLTH=T;
    840 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=T SLTH=F;
    841 echo " INT_CN_TO_MMUIF_MAPPING";
    842 tr 50 M=INT_CN_TO_MMUIF_MAPPING;
    843 tr 51 M=INT_CN_TO_MMUIF_MAPPING;
    844 tr 52 M=INT_CN_TO_MMUIF_MAPPING;
    845 tr 71 M=INT_CN_TO_MMUIF_MAPPING TSE=F SLTH=T;
    846 tr 71 M=INT_CN_TO_MMUIF_MAPPING TSE=T SLTH=T;
    847 tr 71 M=INT_CN_TO_MMUIF_MAPPING TSE=T SLTH=F;
    848 echo " IPORT_TABLE";
    849 tr 50 M=IPORT_TABLE;
    850 tr 51 M=IPORT_TABLE;
    851 tr 52 M=IPORT_TABLE;
    852 tr 71 M=IPORT_TABLE TSE=F SLTH=T;
    853 tr 71 M=IPORT_TABLE TSE=T SLTH=T;
    854 tr 71 M=IPORT_TABLE TSE=T SLTH=F;
    855 echo " IPV4_IN_IPV6_PREFIX_MATCH_TABLE";
    856 tr 50 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE;
    857 tr 51 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE;
    858 tr 52 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE;
    859 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=F SLTH=T;
    860 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=T SLTH=T;
    861 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=T SLTH=F;
    862 echo " IPV6_PROXY_ENABLE_TABLE";
    863 tr 50 M=IPV6_PROXY_ENABLE_TABLE;
    864 tr 51 M=IPV6_PROXY_ENABLE_TABLE;
    865 tr 52 M=IPV6_PROXY_ENABLE_TABLE;
    866 tr 71 M=IPV6_PROXY_ENABLE_TABLE TSE=F SLTH=T;
    867 tr 71 M=IPV6_PROXY_ENABLE_TABLE TSE=T SLTH=T;
    868 tr 71 M=IPV6_PROXY_ENABLE_TABLE TSE=T SLTH=F;
    869 echo " IP_TO_INT_CN_MAPPING";
    870 tr 50 M=IP_TO_INT_CN_MAPPING;
    871 tr 51 M=IP_TO_INT_CN_MAPPING;
    872 tr 52 M=IP_TO_INT_CN_MAPPING;
    873 tr 71 M=IP_TO_INT_CN_MAPPING TSE=F SLTH=T;
    874 tr 71 M=IP_TO_INT_CN_MAPPING TSE=T SLTH=T;
    875 tr 71 M=IP_TO_INT_CN_MAPPING TSE=T SLTH=F;
    876 echo " L2MC";
    877 tr 50 M=L2MC;
    878 tr 51 M=L2MC;
    879 tr 52 M=L2MC;
    880 tr 71 M=L2MC TSE=F SLTH=T;
    881 tr 71 M=L2MC TSE=T SLTH=T;
    882 tr 71 M=L2MC TSE=T SLTH=F;
    883 echo " L2X";
    884 tr 50 M=L2X;
    885 tr 51 M=L2X;
    886 tr 52 M=L2X;
    887 tr 71 M=L2X TSE=F SLTH=T;
    888 tr 71 M=L2X TSE=T SLTH=T;
    889 tr 71 M=L2X TSE=T SLTH=F;
    890 echo " L2_ENTRY_ONLY";
    891 tr 50 M=L2_ENTRY_ONLY;
    892 tr 51 M=L2_ENTRY_ONLY;
    893 tr 52 M=L2_ENTRY_ONLY;
    894 tr 71 M=L2_ENTRY_ONLY TSE=F SLTH=T;
    895 tr 71 M=L2_ENTRY_ONLY TSE=T SLTH=T;
    896 tr 71 M=L2_ENTRY_ONLY TSE=T SLTH=F;
    897 echo " L2_ENTRY_OVERFLOW";
    898 tr 50 M=L2_ENTRY_OVERFLOW;
    899 tr 51 M=L2_ENTRY_OVERFLOW;
    900 tr 52 M=L2_ENTRY_OVERFLOW;
    901 tr 71 M=L2_ENTRY_OVERFLOW TSE=F SLTH=T;
    902 tr 71 M=L2_ENTRY_OVERFLOW TSE=T SLTH=T;
    903 tr 71 M=L2_ENTRY_OVERFLOW TSE=T SLTH=F;
    904 echo " L2_HITDA_ONLY";
    905 tr 50 M=L2_HITDA_ONLY;
    906 tr 51 M=L2_HITDA_ONLY;
    907 tr 52 M=L2_HITDA_ONLY;
    908 tr 71 M=L2_HITDA_ONLY TSE=F SLTH=T;
    909 tr 71 M=L2_HITDA_ONLY TSE=T SLTH=T;
    910 tr 71 M=L2_HITDA_ONLY TSE=T SLTH=F;
    911 echo " L2_HITSA_ONLY";
    912 tr 50 M=L2_HITSA_ONLY;
    913 tr 51 M=L2_HITSA_ONLY;
    914 tr 52 M=L2_HITSA_ONLY;
    915 tr 71 M=L2_HITSA_ONLY TSE=F SLTH=T;
    916 tr 71 M=L2_HITSA_ONLY TSE=T SLTH=T;
    917 tr 71 M=L2_HITSA_ONLY TSE=T SLTH=F;
    918 echo " L2_MOD_FIFO";
    919 tr 50 M=L2_MOD_FIFO;
    920 tr 51 M=L2_MOD_FIFO;
    921 tr 52 M=L2_MOD_FIFO;
    922 tr 71 M=L2_MOD_FIFO TSE=F SLTH=T;
    923 tr 71 M=L2_MOD_FIFO TSE=T SLTH=T;
    924 tr 71 M=L2_MOD_FIFO TSE=T SLTH=F;
    925 echo " L2_USER_ENTRY";
    926 tr 50 M=L2_USER_ENTRY;
    927 tr 51 M=L2_USER_ENTRY;
    928 tr 52 M=L2_USER_ENTRY;
    929 tr 71 M=L2_USER_ENTRY TSE=F SLTH=T;
    930 tr 71 M=L2_USER_ENTRY TSE=T SLTH=T;
    931 tr 71 M=L2_USER_ENTRY TSE=T SLTH=F;
    932 echo " L2_USER_ENTRY_DATA_ONLY";
    933 tr 50 M=L2_USER_ENTRY_DATA_ONLY;
    934 tr 51 M=L2_USER_ENTRY_DATA_ONLY;
    935 tr 52 M=L2_USER_ENTRY_DATA_ONLY;
    936 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=F SLTH=T;
    937 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=T SLTH=T;
    938 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=T SLTH=F;
    939 echo " L2_USER_ENTRY_ONLY";
    940 tr 50 M=L2_USER_ENTRY_ONLY;
    941 tr 51 M=L2_USER_ENTRY_ONLY;
    942 tr 52 M=L2_USER_ENTRY_ONLY;
    943 tr 71 M=L2_USER_ENTRY_ONLY TSE=F SLTH=T;
    944 tr 71 M=L2_USER_ENTRY_ONLY TSE=T SLTH=T;
    945 tr 71 M=L2_USER_ENTRY_ONLY TSE=T SLTH=F;
    946 echo " L3_DEFIP";
    947 tr 50 M=L3_DEFIP;
    948 tr 51 M=L3_DEFIP;
    949 tr 52 M=L3_DEFIP;
    950 tr 71 M=L3_DEFIP TSE=F SLTH=T;
    951 tr 71 M=L3_DEFIP TSE=T SLTH=T;
    952 tr 71 M=L3_DEFIP TSE=T SLTH=F;
    953 echo " L3_DEFIP_DATA_ONLY";
    954 tr 50 M=L3_DEFIP_DATA_ONLY;
    955 tr 51 M=L3_DEFIP_DATA_ONLY;
    956 tr 52 M=L3_DEFIP_DATA_ONLY;
    957 tr 71 M=L3_DEFIP_DATA_ONLY TSE=F SLTH=T;
    958 tr 71 M=L3_DEFIP_DATA_ONLY TSE=T SLTH=T;
    959 tr 71 M=L3_DEFIP_DATA_ONLY TSE=T SLTH=F;
    960 echo " L3_DEFIP_HIT_ONLY";
    961 tr 50 M=L3_DEFIP_HIT_ONLY;
    962 tr 51 M=L3_DEFIP_HIT_ONLY;
    963 tr 52 M=L3_DEFIP_HIT_ONLY;
    964 tr 71 M=L3_DEFIP_HIT_ONLY TSE=F SLTH=T;
    965 tr 71 M=L3_DEFIP_HIT_ONLY TSE=T SLTH=T;
    966 tr 71 M=L3_DEFIP_HIT_ONLY TSE=T SLTH=F;
    967 echo " L3_DEFIP_ONLY";
    968 tr 50 M=L3_DEFIP_ONLY;
    969 tr 51 M=L3_DEFIP_ONLY;
    970 tr 52 M=L3_DEFIP_ONLY;
    971 tr 71 M=L3_DEFIP_ONLY TSE=F SLTH=T;
    972 tr 71 M=L3_DEFIP_ONLY TSE=T SLTH=T;
    973 tr 71 M=L3_DEFIP_ONLY TSE=T SLTH=F;
    974 echo " L3_ENTRY_HIT_ONLY";
    975 tr 50 M=L3_ENTRY_HIT_ONLY;
    976 tr 51 M=L3_ENTRY_HIT_ONLY;
    977 tr 52 M=L3_ENTRY_HIT_ONLY;
    978 tr 71 M=L3_ENTRY_HIT_ONLY TSE=F SLTH=T;
    979 tr 71 M=L3_ENTRY_HIT_ONLY TSE=T SLTH=T;
    980 tr 71 M=L3_ENTRY_HIT_ONLY TSE=T SLTH=F;
    981 echo " L3_ENTRY_IPV4_MULTICAST";
    982 tr 50 M=L3_ENTRY_IPV4_MULTICAST;
    983 tr 51 M=L3_ENTRY_IPV4_MULTICAST;
    984 tr 52 M=L3_ENTRY_IPV4_MULTICAST;
    985 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=F SLTH=T;
    986 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=T SLTH=T;
    987 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=T SLTH=F;
    988 echo " L3_ENTRY_IPV4_UNICAST";
    989 tr 50 M=L3_ENTRY_IPV4_UNICAST;
    990 tr 51 M=L3_ENTRY_IPV4_UNICAST;
    991 tr 52 M=L3_ENTRY_IPV4_UNICAST;
    992 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=F SLTH=T;
    993 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=T SLTH=T;
    994 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=T SLTH=F;
    995 echo " L3_ENTRY_IPV6_MULTICAST";
    996 tr 50 M=L3_ENTRY_IPV6_MULTICAST;
    997 tr 51 M=L3_ENTRY_IPV6_MULTICAST;
    998 tr 52 M=L3_ENTRY_IPV6_MULTICAST;
    999 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=F SLTH=T;
   1000 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=T SLTH=T;
   1001 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=T SLTH=F;
   1002 echo " L3_ENTRY_IPV6_UNICAST";
   1003 tr 50 M=L3_ENTRY_IPV6_UNICAST;
   1004 tr 51 M=L3_ENTRY_IPV6_UNICAST;
   1005 tr 52 M=L3_ENTRY_IPV6_UNICAST;
   1006 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=F SLTH=T;
   1007 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=T SLTH=T;
   1008 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=T SLTH=F;
   1009 echo " L3_ENTRY_ONLY";
   1010 tr 50 M=L3_ENTRY_ONLY;
   1011 tr 51 M=L3_ENTRY_ONLY;
   1012 tr 52 M=L3_ENTRY_ONLY;
   1013 tr 71 M=L3_ENTRY_ONLY TSE=F SLTH=T;
   1014 tr 71 M=L3_ENTRY_ONLY TSE=T SLTH=T;
   1015 tr 71 M=L3_ENTRY_ONLY TSE=T SLTH=F;
   1016 echo " L3_ENTRY_VALID_ONLY";
   1017 tr 50 M=L3_ENTRY_VALID_ONLY;
   1018 tr 51 M=L3_ENTRY_VALID_ONLY;
   1019 tr 52 M=L3_ENTRY_VALID_ONLY;
   1020 tr 71 M=L3_ENTRY_VALID_ONLY TSE=F SLTH=T;
   1021 tr 71 M=L3_ENTRY_VALID_ONLY TSE=T SLTH=T;
   1022 tr 71 M=L3_ENTRY_VALID_ONLY TSE=T SLTH=F;
   1023 echo " L3_IPMC";
   1024 tr 50 M=L3_IPMC;
   1025 tr 51 M=L3_IPMC;
   1026 tr 52 M=L3_IPMC;
   1027 tr 71 M=L3_IPMC TSE=F SLTH=T;
   1028 tr 71 M=L3_IPMC TSE=T SLTH=T;
   1029 tr 71 M=L3_IPMC TSE=T SLTH=F;
   1030 echo " L3_MTU_VALUES";
   1031 tr 50 M=L3_MTU_VALUES;
   1032 tr 51 M=L3_MTU_VALUES;
   1033 tr 52 M=L3_MTU_VALUES;
   1034 tr 71 M=L3_MTU_VALUES TSE=F SLTH=T;
   1035 tr 71 M=L3_MTU_VALUES TSE=T SLTH=T;
   1036 tr 71 M=L3_MTU_VALUES TSE=T SLTH=F;
   1037 echo " L3_IIF";
   1038 tr 50 M=L3_IIF;
   1039 tr 51 M=L3_IIF;
   1040 tr 52 M=L3_IIF;
   1041 tr 71 M=L3_IIF TSE=F SLTH=T;
   1042 tr 71 M=L3_IIF TSE=T SLTH=T;
   1043 tr 71 M=L3_IIF TSE=T SLTH=F;
   1044 echo " LMEP";
   1045 tr 50 M=LMEP;
   1046 tr 51 M=LMEP;
   1047 tr 52 M=LMEP;
   1048 tr 71 M=LMEP TSE=F SLTH=T;
   1049 tr 71 M=LMEP TSE=T SLTH=T;
   1050 tr 71 M=LMEP TSE=T SLTH=F;
   1051 echo " LMEP_DA";
   1052 tr 50 M=LMEP_DA;
   1053 tr 51 M=LMEP_DA;
   1054 tr 52 M=LMEP_DA;
   1055 tr 71 M=LMEP_DA TSE=F SLTH=T;
   1056 tr 71 M=LMEP_DA TSE=T SLTH=T;
   1057 tr 71 M=LMEP_DA TSE=T SLTH=F;
   1058 echo " LPORT_TAB";
   1059 tr 50 M=LPORT_TAB;
   1060 tr 51 M=LPORT_TAB;
   1061 tr 52 M=LPORT_TAB;
   1062 tr 71 M=LPORT_TAB TSE=F SLTH=T;
   1063 tr 71 M=LPORT_TAB TSE=T SLTH=T;
   1064 tr 71 M=LPORT_TAB TSE=T SLTH=F;
   1065 echo " MAC_BLOCK";
   1066 tr 50 M=MAC_BLOCK;
   1067 tr 51 M=MAC_BLOCK;
   1068 tr 52 M=MAC_BLOCK;
   1069 tr 71 M=MAC_BLOCK TSE=F SLTH=T;
   1070 tr 71 M=MAC_BLOCK TSE=T SLTH=T;
   1071 tr 71 M=MAC_BLOCK TSE=T SLTH=F;
   1072 echo " MAID_REDUCTION";
   1073 tr 50 M=MAID_REDUCTION;
   1074 tr 51 M=MAID_REDUCTION;
   1075 tr 52 M=MAID_REDUCTION;
   1076 tr 71 M=MAID_REDUCTION TSE=F SLTH=T;
   1077 tr 71 M=MAID_REDUCTION TSE=T SLTH=T;
   1078 tr 71 M=MAID_REDUCTION TSE=T SLTH=F;
   1079 echo " MA_INDEX";
   1080 tr 50 M=MA_INDEX;
   1081 tr 51 M=MA_INDEX;
   1082 tr 52 M=MA_INDEX;
   1083 tr 71 M=MA_INDEX TSE=F SLTH=T;
   1084 tr 71 M=MA_INDEX TSE=T SLTH=T;
   1085 tr 71 M=MA_INDEX TSE=T SLTH=F;
   1086 echo " MA_STATE";
   1087 tr 50 M=MA_STATE;
   1088 tr 51 M=MA_STATE;
   1089 tr 52 M=MA_STATE;
   1090 tr 71 M=MA_STATE TSE=F SLTH=T;
   1091 tr 71 M=MA_STATE TSE=T SLTH=T;
   1092 tr 71 M=MA_STATE TSE=T SLTH=F;
   1093 echo " MMU_AGING_CTR";
   1094 tr 50 M=MMU_AGING_CTR;
   1095 tr 51 M=MMU_AGING_CTR;
   1096 tr 52 M=MMU_AGING_CTR;
   1097 tr 71 M=MMU_AGING_CTR TSE=F SLTH=T;
   1098 tr 71 M=MMU_AGING_CTR TSE=T SLTH=T;
   1099 tr 71 M=MMU_AGING_CTR TSE=T SLTH=F;
   1100 echo " MMU_AGING_EXP";
   1101 tr 50 M=MMU_AGING_EXP;
   1102 tr 51 M=MMU_AGING_EXP;
   1103 tr 52 M=MMU_AGING_EXP;
   1104 tr 71 M=MMU_AGING_EXP TSE=F SLTH=T;
   1105 tr 71 M=MMU_AGING_EXP TSE=T SLTH=T;
   1106 tr 71 M=MMU_AGING_EXP TSE=T SLTH=F;
   1107 echo " MMU_ARB_TDM_TABLE";
   1108 tr 50 M=MMU_ARB_TDM_TABLE;
   1109 tr 51 M=MMU_ARB_TDM_TABLE;
   1110 tr 52 M=MMU_ARB_TDM_TABLE;
   1111 tr 71 M=MMU_ARB_TDM_TABLE TSE=F SLTH=T;
   1112 tr 71 M=MMU_ARB_TDM_TABLE TSE=T SLTH=T;
   1113 tr 71 M=MMU_ARB_TDM_TABLE TSE=T SLTH=F;
   1114 echo " MMU_CBPCellHeader";
   1115 tr 50 M=MMU_CBPCellHeader;
   1116 tr 51 M=MMU_CBPCellHeader;
   1117 tr 52 M=MMU_CBPCellHeader;
   1118 tr 71 M=MMU_CBPCellHeader TSE=F SLTH=T;
   1119 tr 71 M=MMU_CBPCellHeader TSE=T SLTH=T;
   1120 tr 71 M=MMU_CBPCellHeader TSE=T SLTH=F;
   1121 echo " MMU_CBPData0";
   1122 tr 50 M=MMU_CBPData0;
   1123 tr 51 M=MMU_CBPData0;
   1124 tr 52 M=MMU_CBPData0;
   1125 tr 71 M=MMU_CBPData0 TSE=F SLTH=T;
   1126 tr 71 M=MMU_CBPData0 TSE=T SLTH=T;
   1127 tr 71 M=MMU_CBPData0 TSE=T SLTH=F;
   1128 echo " MMU_CBPData1";
   1129 tr 50 M=MMU_CBPData1;
   1130 tr 51 M=MMU_CBPData1;
   1131 tr 52 M=MMU_CBPData1;
   1132 tr 71 M=MMU_CBPData1 TSE=F SLTH=T;
   1133 tr 71 M=MMU_CBPData1 TSE=T SLTH=T;
   1134 tr 71 M=MMU_CBPData1 TSE=T SLTH=F;
   1135 echo " MMU_CBPData2";
   1136 tr 50 M=MMU_CBPData2;
   1137 tr 51 M=MMU_CBPData2;
   1138 tr 52 M=MMU_CBPData2;
   1139 tr 71 M=MMU_CBPData2 TSE=F SLTH=T;
   1140 tr 71 M=MMU_CBPData2 TSE=T SLTH=T;
   1141 tr 71 M=MMU_CBPData2 TSE=T SLTH=F;
   1142 echo " MMU_CBPData3";
   1143 tr 50 M=MMU_CBPData3;
   1144 tr 51 M=MMU_CBPData3;
   1145 tr 52 M=MMU_CBPData3;
   1146 tr 71 M=MMU_CBPData3 TSE=F SLTH=T;
   1147 tr 71 M=MMU_CBPData3 TSE=T SLTH=T;
   1148 tr 71 M=MMU_CBPData3 TSE=T SLTH=F;
   1149 echo " MMU_CBPData4";
   1150 tr 50 M=MMU_CBPData4;
   1151 tr 51 M=MMU_CBPData4;
   1152 tr 52 M=MMU_CBPData4;
   1153 tr 71 M=MMU_CBPData4 TSE=F SLTH=T;
   1154 tr 71 M=MMU_CBPData4 TSE=T SLTH=T;
   1155 tr 71 M=MMU_CBPData4 TSE=T SLTH=F;
   1156 echo " MMU_CBPData5";
   1157 tr 50 M=MMU_CBPData5;
   1158 tr 51 M=MMU_CBPData5;
   1159 tr 52 M=MMU_CBPData5;
   1160 tr 71 M=MMU_CBPData5 TSE=F SLTH=T;
   1161 tr 71 M=MMU_CBPData5 TSE=T SLTH=T;
   1162 tr 71 M=MMU_CBPData5 TSE=T SLTH=F;
   1163 echo " MMU_CBPData6";
   1164 tr 50 M=MMU_CBPData6;
   1165 tr 51 M=MMU_CBPData6;
   1166 tr 52 M=MMU_CBPData6;
   1167 tr 71 M=MMU_CBPData6 TSE=F SLTH=T;
   1168 tr 71 M=MMU_CBPData6 TSE=T SLTH=T;
   1169 tr 71 M=MMU_CBPData6 TSE=T SLTH=F;
   1170 echo " MMU_CBPData7";
   1171 tr 50 M=MMU_CBPData7;
   1172 tr 51 M=MMU_CBPData7;
   1173 tr 52 M=MMU_CBPData7;
   1174 tr 71 M=MMU_CBPData7 TSE=F SLTH=T;
   1175 tr 71 M=MMU_CBPData7 TSE=T SLTH=T;
   1176 tr 71 M=MMU_CBPData7 TSE=T SLTH=F;
   1177 echo " MMU_CBPPktHeader0";
   1178 tr 50 M=MMU_CBPPktHeader0;
   1179 tr 51 M=MMU_CBPPktHeader0;
   1180 tr 52 M=MMU_CBPPktHeader0;
   1181 tr 71 M=MMU_CBPPktHeader0 TSE=F SLTH=T;
   1182 tr 71 M=MMU_CBPPktHeader0 TSE=T SLTH=T;
   1183 tr 71 M=MMU_CBPPktHeader0 TSE=T SLTH=F;
   1184 echo " MMU_CBPPktHeader1";
   1185 tr 50 M=MMU_CBPPktHeader1;
   1186 tr 51 M=MMU_CBPPktHeader1;
   1187 tr 52 M=MMU_CBPPktHeader1;
   1188 tr 71 M=MMU_CBPPktHeader1 TSE=F SLTH=T;
   1189 tr 71 M=MMU_CBPPktHeader1 TSE=T SLTH=T;
   1190 tr 71 M=MMU_CBPPktHeader1 TSE=T SLTH=F;
   1191 echo " MMU_CBPPktHeader2";
   1192 tr 50 M=MMU_CBPPktHeader2;
   1193 tr 51 M=MMU_CBPPktHeader2;
   1194 tr 52 M=MMU_CBPPktHeader2;
   1195 tr 71 M=MMU_CBPPktHeader2 TSE=F SLTH=T;
   1196 tr 71 M=MMU_CBPPktHeader2 TSE=T SLTH=T;
   1197 tr 71 M=MMU_CBPPktHeader2 TSE=T SLTH=F;
   1198 echo " MMU_CBPPktHeader_EXT";
   1199 tr 50 M=MMU_CBPPktHeader_EXT;
   1200 tr 51 M=MMU_CBPPktHeader_EXT;
   1201 tr 52 M=MMU_CBPPktHeader_EXT;
   1202 tr 71 M=MMU_CBPPktHeader_EXT TSE=F SLTH=T;
   1203 tr 71 M=MMU_CBPPktHeader_EXT TSE=T SLTH=T;
   1204 tr 71 M=MMU_CBPPktHeader_EXT TSE=T SLTH=F;
   1205 echo " MMU_CCP";
   1206 tr 50 M=MMU_CCP;
   1207 tr 51 M=MMU_CCP;
   1208 tr 52 M=MMU_CCP;
   1209 tr 71 M=MMU_CCP TSE=F SLTH=T;
   1210 tr 71 M=MMU_CCP TSE=T SLTH=T;
   1211 tr 71 M=MMU_CCP TSE=T SLTH=F;
   1212 echo " MMU_CFAP";
   1213 tr 50 M=MMU_CFAP;
   1214 tr 51 M=MMU_CFAP;
   1215 tr 52 M=MMU_CFAP;
   1216 tr 71 M=MMU_CFAP TSE=F SLTH=T;
   1217 tr 71 M=MMU_CFAP TSE=T SLTH=T;
   1218 tr 71 M=MMU_CFAP TSE=T SLTH=F;
   1219 echo " MMU_IPMC_GROUP_TBL10";
   1220 tr 50 M=MMU_IPMC_GROUP_TBL10;
   1221 tr 51 M=MMU_IPMC_GROUP_TBL10;
   1222 tr 52 M=MMU_IPMC_GROUP_TBL10;
   1223 tr 71 M=MMU_IPMC_GROUP_TBL10 TSE=F SLTH=T;
   1224 tr 71 M=MMU_IPMC_GROUP_TBL10 TSE=T SLTH=T;
   1225 tr 71 M=MMU_IPMC_GROUP_TBL10 TSE=T SLTH=F;
   1226 echo " MMU_IPMC_GROUP_TBL11";
   1227 tr 50 M=MMU_IPMC_GROUP_TBL11;
   1228 tr 51 M=MMU_IPMC_GROUP_TBL11;
   1229 tr 52 M=MMU_IPMC_GROUP_TBL11;
   1230 tr 71 M=MMU_IPMC_GROUP_TBL11 TSE=F SLTH=T;
   1231 tr 71 M=MMU_IPMC_GROUP_TBL11 TSE=T SLTH=T;
   1232 tr 71 M=MMU_IPMC_GROUP_TBL11 TSE=T SLTH=F;
   1233 echo " MMU_IPMC_GROUP_TBL12";
   1234 tr 50 M=MMU_IPMC_GROUP_TBL12;
   1235 tr 51 M=MMU_IPMC_GROUP_TBL12;
   1236 tr 52 M=MMU_IPMC_GROUP_TBL12;
   1237 tr 71 M=MMU_IPMC_GROUP_TBL12 TSE=F SLTH=T;
   1238 tr 71 M=MMU_IPMC_GROUP_TBL12 TSE=T SLTH=T;
   1239 tr 71 M=MMU_IPMC_GROUP_TBL12 TSE=T SLTH=F;
   1240 echo " MMU_IPMC_GROUP_TBL13";
   1241 tr 50 M=MMU_IPMC_GROUP_TBL13;
   1242 tr 51 M=MMU_IPMC_GROUP_TBL13;
   1243 tr 52 M=MMU_IPMC_GROUP_TBL13;
   1244 tr 71 M=MMU_IPMC_GROUP_TBL13 TSE=F SLTH=T;
   1245 tr 71 M=MMU_IPMC_GROUP_TBL13 TSE=T SLTH=T;
   1246 tr 71 M=MMU_IPMC_GROUP_TBL13 TSE=T SLTH=F;
   1247 echo " MMU_IPMC_GROUP_TBL14";
   1248 tr 50 M=MMU_IPMC_GROUP_TBL14;
   1249 tr 51 M=MMU_IPMC_GROUP_TBL14;
   1250 tr 52 M=MMU_IPMC_GROUP_TBL14;
   1251 tr 71 M=MMU_IPMC_GROUP_TBL14 TSE=F SLTH=T;
   1252 tr 71 M=MMU_IPMC_GROUP_TBL14 TSE=T SLTH=T;
   1253 tr 71 M=MMU_IPMC_GROUP_TBL14 TSE=T SLTH=F;
   1254 echo " MMU_IPMC_GROUP_TBL15";
   1255 tr 50 M=MMU_IPMC_GROUP_TBL15;
   1256 tr 51 M=MMU_IPMC_GROUP_TBL15;
   1257 tr 52 M=MMU_IPMC_GROUP_TBL15;
   1258 tr 71 M=MMU_IPMC_GROUP_TBL15 TSE=F SLTH=T;
   1259 tr 71 M=MMU_IPMC_GROUP_TBL15 TSE=T SLTH=T;
   1260 tr 71 M=MMU_IPMC_GROUP_TBL15 TSE=T SLTH=F;
   1261 echo " MMU_IPMC_GROUP_TBL16";
   1262 tr 50 M=MMU_IPMC_GROUP_TBL16;
   1263 tr 51 M=MMU_IPMC_GROUP_TBL16;
   1264 tr 52 M=MMU_IPMC_GROUP_TBL16;
   1265 tr 71 M=MMU_IPMC_GROUP_TBL16 TSE=F SLTH=T;
   1266 tr 71 M=MMU_IPMC_GROUP_TBL16 TSE=T SLTH=T;
   1267 tr 71 M=MMU_IPMC_GROUP_TBL16 TSE=T SLTH=F;
   1268 echo " MMU_IPMC_GROUP_TBL17";
   1269 tr 50 M=MMU_IPMC_GROUP_TBL17;
   1270 tr 51 M=MMU_IPMC_GROUP_TBL17;
   1271 tr 52 M=MMU_IPMC_GROUP_TBL17;
   1272 tr 71 M=MMU_IPMC_GROUP_TBL17 TSE=F SLTH=T;
   1273 tr 71 M=MMU_IPMC_GROUP_TBL17 TSE=T SLTH=T;
   1274 tr 71 M=MMU_IPMC_GROUP_TBL17 TSE=T SLTH=F;
   1275 echo " MMU_IPMC_GROUP_TBL18";
   1276 tr 50 M=MMU_IPMC_GROUP_TBL18;
   1277 tr 51 M=MMU_IPMC_GROUP_TBL18;
   1278 tr 52 M=MMU_IPMC_GROUP_TBL18;
   1279 tr 71 M=MMU_IPMC_GROUP_TBL18 TSE=F SLTH=T;
   1280 tr 71 M=MMU_IPMC_GROUP_TBL18 TSE=T SLTH=T;
   1281 tr 71 M=MMU_IPMC_GROUP_TBL18 TSE=T SLTH=F;
   1282 echo " MMU_IPMC_GROUP_TBL19";
   1283 tr 50 M=MMU_IPMC_GROUP_TBL19;
   1284 tr 51 M=MMU_IPMC_GROUP_TBL19;
   1285 tr 52 M=MMU_IPMC_GROUP_TBL19;
   1286 tr 71 M=MMU_IPMC_GROUP_TBL19 TSE=F SLTH=T;
   1287 tr 71 M=MMU_IPMC_GROUP_TBL19 TSE=T SLTH=T;
   1288 tr 71 M=MMU_IPMC_GROUP_TBL19 TSE=T SLTH=F;
   1289 echo " MMU_IPMC_GROUP_TBL2";
   1290 tr 50 M=MMU_IPMC_GROUP_TBL2;
   1291 tr 51 M=MMU_IPMC_GROUP_TBL2;
   1292 tr 52 M=MMU_IPMC_GROUP_TBL2;
   1293 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=F SLTH=T;
   1294 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=T SLTH=T;
   1295 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=T SLTH=F;
   1296 echo " MMU_IPMC_GROUP_TBL20";
   1297 tr 50 M=MMU_IPMC_GROUP_TBL20;
   1298 tr 51 M=MMU_IPMC_GROUP_TBL20;
   1299 tr 52 M=MMU_IPMC_GROUP_TBL20;
   1300 tr 71 M=MMU_IPMC_GROUP_TBL20 TSE=F SLTH=T;
   1301 tr 71 M=MMU_IPMC_GROUP_TBL20 TSE=T SLTH=T;
   1302 tr 71 M=MMU_IPMC_GROUP_TBL20 TSE=T SLTH=F;
   1303 echo " MMU_IPMC_GROUP_TBL21";
   1304 tr 50 M=MMU_IPMC_GROUP_TBL21;
   1305 tr 51 M=MMU_IPMC_GROUP_TBL21;
   1306 tr 52 M=MMU_IPMC_GROUP_TBL21;
   1307 tr 71 M=MMU_IPMC_GROUP_TBL21 TSE=F SLTH=T;
   1308 tr 71 M=MMU_IPMC_GROUP_TBL21 TSE=T SLTH=T;
   1309 tr 71 M=MMU_IPMC_GROUP_TBL21 TSE=T SLTH=F;
   1310 echo " MMU_IPMC_GROUP_TBL22";
   1311 tr 50 M=MMU_IPMC_GROUP_TBL22;
   1312 tr 51 M=MMU_IPMC_GROUP_TBL22;
   1313 tr 52 M=MMU_IPMC_GROUP_TBL22;
   1314 tr 71 M=MMU_IPMC_GROUP_TBL22 TSE=F SLTH=T;
   1315 tr 71 M=MMU_IPMC_GROUP_TBL22 TSE=T SLTH=T;
   1316 tr 71 M=MMU_IPMC_GROUP_TBL22 TSE=T SLTH=F;
   1317 echo " MMU_IPMC_GROUP_TBL23";
   1318 tr 50 M=MMU_IPMC_GROUP_TBL23;
   1319 tr 51 M=MMU_IPMC_GROUP_TBL23;
   1320 tr 52 M=MMU_IPMC_GROUP_TBL23;
   1321 tr 71 M=MMU_IPMC_GROUP_TBL23 TSE=F SLTH=T;
   1322 tr 71 M=MMU_IPMC_GROUP_TBL23 TSE=T SLTH=T;
   1323 tr 71 M=MMU_IPMC_GROUP_TBL23 TSE=T SLTH=F;
   1324 echo " MMU_IPMC_GROUP_TBL24";
   1325 tr 50 M=MMU_IPMC_GROUP_TBL24;
   1326 tr 51 M=MMU_IPMC_GROUP_TBL24;
   1327 tr 52 M=MMU_IPMC_GROUP_TBL24;
   1328 tr 71 M=MMU_IPMC_GROUP_TBL24 TSE=F SLTH=T;
   1329 tr 71 M=MMU_IPMC_GROUP_TBL24 TSE=T SLTH=T;
   1330 tr 71 M=MMU_IPMC_GROUP_TBL24 TSE=T SLTH=F;
   1331 echo " MMU_IPMC_GROUP_TBL25";
   1332 tr 50 M=MMU_IPMC_GROUP_TBL25;
   1333 tr 51 M=MMU_IPMC_GROUP_TBL25;
   1334 tr 52 M=MMU_IPMC_GROUP_TBL25;
   1335 tr 71 M=MMU_IPMC_GROUP_TBL25 TSE=F SLTH=T;
   1336 tr 71 M=MMU_IPMC_GROUP_TBL25 TSE=T SLTH=T;
   1337 tr 71 M=MMU_IPMC_GROUP_TBL25 TSE=T SLTH=F;
   1338 echo " MMU_IPMC_GROUP_TBL26";
   1339 tr 50 M=MMU_IPMC_GROUP_TBL26;
   1340 tr 51 M=MMU_IPMC_GROUP_TBL26;
   1341 tr 52 M=MMU_IPMC_GROUP_TBL26;
   1342 tr 71 M=MMU_IPMC_GROUP_TBL26 TSE=F SLTH=T;
   1343 tr 71 M=MMU_IPMC_GROUP_TBL26 TSE=T SLTH=T;
   1344 tr 71 M=MMU_IPMC_GROUP_TBL26 TSE=T SLTH=F;
   1345 echo " MMU_IPMC_GROUP_TBL27";
   1346 tr 50 M=MMU_IPMC_GROUP_TBL27;
   1347 tr 51 M=MMU_IPMC_GROUP_TBL27;
   1348 tr 52 M=MMU_IPMC_GROUP_TBL27;
   1349 tr 71 M=MMU_IPMC_GROUP_TBL27 TSE=F SLTH=T;
   1350 tr 71 M=MMU_IPMC_GROUP_TBL27 TSE=T SLTH=T;
   1351 tr 71 M=MMU_IPMC_GROUP_TBL27 TSE=T SLTH=F;
   1352 echo " MMU_IPMC_GROUP_TBL28";
   1353 tr 50 M=MMU_IPMC_GROUP_TBL28;
   1354 tr 51 M=MMU_IPMC_GROUP_TBL28;
   1355 tr 52 M=MMU_IPMC_GROUP_TBL28;
   1356 tr 71 M=MMU_IPMC_GROUP_TBL28 TSE=F SLTH=T;
   1357 tr 71 M=MMU_IPMC_GROUP_TBL28 TSE=T SLTH=T;
   1358 tr 71 M=MMU_IPMC_GROUP_TBL28 TSE=T SLTH=F;
   1359 echo " MMU_IPMC_GROUP_TBL29";
   1360 tr 50 M=MMU_IPMC_GROUP_TBL29;
   1361 tr 51 M=MMU_IPMC_GROUP_TBL29;
   1362 tr 52 M=MMU_IPMC_GROUP_TBL29;
   1363 tr 71 M=MMU_IPMC_GROUP_TBL29 TSE=F SLTH=T;
   1364 tr 71 M=MMU_IPMC_GROUP_TBL29 TSE=T SLTH=T;
   1365 tr 71 M=MMU_IPMC_GROUP_TBL29 TSE=T SLTH=F;
   1366 echo " MMU_IPMC_GROUP_TBL3";
   1367 tr 50 M=MMU_IPMC_GROUP_TBL3;
   1368 tr 51 M=MMU_IPMC_GROUP_TBL3;
   1369 tr 52 M=MMU_IPMC_GROUP_TBL3;
   1370 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=F SLTH=T;
   1371 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=T SLTH=T;
   1372 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=T SLTH=F;
   1373 echo " MMU_IPMC_GROUP_TBL4";
   1374 tr 50 M=MMU_IPMC_GROUP_TBL4;
   1375 tr 51 M=MMU_IPMC_GROUP_TBL4;
   1376 tr 52 M=MMU_IPMC_GROUP_TBL4;
   1377 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=F SLTH=T;
   1378 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=T SLTH=T;
   1379 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=T SLTH=F;
   1380 echo " MMU_IPMC_GROUP_TBL5";
   1381 tr 50 M=MMU_IPMC_GROUP_TBL5;
   1382 tr 51 M=MMU_IPMC_GROUP_TBL5;
   1383 tr 52 M=MMU_IPMC_GROUP_TBL5;
   1384 tr 71 M=MMU_IPMC_GROUP_TBL5 TSE=F SLTH=T;
   1385 tr 71 M=MMU_IPMC_GROUP_TBL5 TSE=T SLTH=T;
   1386 tr 71 M=MMU_IPMC_GROUP_TBL5 TSE=T SLTH=F;
   1387 echo " MMU_IPMC_GROUP_TBL6";
   1388 tr 50 M=MMU_IPMC_GROUP_TBL6;
   1389 tr 51 M=MMU_IPMC_GROUP_TBL6;
   1390 tr 52 M=MMU_IPMC_GROUP_TBL6;
   1391 tr 71 M=MMU_IPMC_GROUP_TBL6 TSE=F SLTH=T;
   1392 tr 71 M=MMU_IPMC_GROUP_TBL6 TSE=T SLTH=T;
   1393 tr 71 M=MMU_IPMC_GROUP_TBL6 TSE=T SLTH=F;
   1394 echo " MMU_IPMC_GROUP_TBL7";
   1395 tr 50 M=MMU_IPMC_GROUP_TBL7;
   1396 tr 51 M=MMU_IPMC_GROUP_TBL7;
   1397 tr 52 M=MMU_IPMC_GROUP_TBL7;
   1398 tr 71 M=MMU_IPMC_GROUP_TBL7 TSE=F SLTH=T;
   1399 tr 71 M=MMU_IPMC_GROUP_TBL7 TSE=T SLTH=T;
   1400 tr 71 M=MMU_IPMC_GROUP_TBL7 TSE=T SLTH=F;
   1401 echo " MMU_IPMC_GROUP_TBL8";
   1402 tr 50 M=MMU_IPMC_GROUP_TBL8;
   1403 tr 51 M=MMU_IPMC_GROUP_TBL8;
   1404 tr 52 M=MMU_IPMC_GROUP_TBL8;
   1405 tr 71 M=MMU_IPMC_GROUP_TBL8 TSE=F SLTH=T;
   1406 tr 71 M=MMU_IPMC_GROUP_TBL8 TSE=T SLTH=T;
   1407 tr 71 M=MMU_IPMC_GROUP_TBL8 TSE=T SLTH=F;
   1408 echo " MMU_IPMC_GROUP_TBL9";
   1409 tr 50 M=MMU_IPMC_GROUP_TBL9;
   1410 tr 51 M=MMU_IPMC_GROUP_TBL9;
   1411 tr 52 M=MMU_IPMC_GROUP_TBL9;
   1412 tr 71 M=MMU_IPMC_GROUP_TBL9 TSE=F SLTH=T;
   1413 tr 71 M=MMU_IPMC_GROUP_TBL9 TSE=T SLTH=T;
   1414 tr 71 M=MMU_IPMC_GROUP_TBL9 TSE=T SLTH=F;
   1415 echo " MMU_IPMC_VLAN_TBL";
   1416 tr 50 M=MMU_IPMC_VLAN_TBL;
   1417 tr 51 M=MMU_IPMC_VLAN_TBL;
   1418 tr 52 M=MMU_IPMC_VLAN_TBL;
   1419 tr 71 M=MMU_IPMC_VLAN_TBL TSE=F SLTH=T;
   1420 tr 71 M=MMU_IPMC_VLAN_TBL TSE=T SLTH=T;
   1421 tr 71 M=MMU_IPMC_VLAN_TBL TSE=T SLTH=F;
   1422 echo " MODPORT_MAP";
   1423 tr 50 M=MODPORT_MAP;
   1424 tr 51 M=MODPORT_MAP;
   1425 tr 52 M=MODPORT_MAP;
   1426 tr 71 M=MODPORT_MAP TSE=F SLTH=T;
   1427 tr 71 M=MODPORT_MAP TSE=T SLTH=T;
   1428 tr 71 M=MODPORT_MAP TSE=T SLTH=F;
   1429 echo " MODPORT_MAP_EM";
   1430 tr 50 M=MODPORT_MAP_EM;
   1431 tr 51 M=MODPORT_MAP_EM;
   1432 tr 52 M=MODPORT_MAP_EM;
   1433 tr 71 M=MODPORT_MAP_EM TSE=F SLTH=T;
   1434 tr 71 M=MODPORT_MAP_EM TSE=T SLTH=T;
   1435 tr 71 M=MODPORT_MAP_EM TSE=T SLTH=F;
   1436 echo " MODPORT_MAP_IM";
   1437 tr 50 M=MODPORT_MAP_IM;
   1438 tr 51 M=MODPORT_MAP_IM;
   1439 tr 52 M=MODPORT_MAP_IM;
   1440 tr 71 M=MODPORT_MAP_IM TSE=F SLTH=T;
   1441 tr 71 M=MODPORT_MAP_IM TSE=T SLTH=T;
   1442 tr 71 M=MODPORT_MAP_IM TSE=T SLTH=F;
   1443 echo " MODPORT_MAP_SW";
   1444 tr 50 M=MODPORT_MAP_SW;
   1445 tr 51 M=MODPORT_MAP_SW;
   1446 tr 52 M=MODPORT_MAP_SW;
   1447 tr 71 M=MODPORT_MAP_SW TSE=F SLTH=T;
   1448 tr 71 M=MODPORT_MAP_SW TSE=T SLTH=T;
   1449 tr 71 M=MODPORT_MAP_SW TSE=T SLTH=F;
   1450 echo " NONUCAST_TRUNK_BLOCK_MASK";
   1451 tr 50 M=NONUCAST_TRUNK_BLOCK_MASK;
   1452 tr 51 M=NONUCAST_TRUNK_BLOCK_MASK;
   1453 tr 52 M=NONUCAST_TRUNK_BLOCK_MASK;
   1454 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=F SLTH=T;
   1455 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=T SLTH=T;
   1456 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=T SLTH=F;
   1457 echo " OAM_LM_COUNTERS";
   1458 tr 50 M=OAM_LM_COUNTERS;
   1459 tr 51 M=OAM_LM_COUNTERS;
   1460 tr 52 M=OAM_LM_COUNTERS;
   1461 tr 71 M=OAM_LM_COUNTERS TSE=F SLTH=T;
   1462 tr 71 M=OAM_LM_COUNTERS TSE=T SLTH=T;
   1463 tr 71 M=OAM_LM_COUNTERS TSE=T SLTH=F;
   1464 echo " OAM_OPCODE_CONTROL_PROFILE";
   1465 tr 50 M=OAM_OPCODE_CONTROL_PROFILE;
   1466 tr 51 M=OAM_OPCODE_CONTROL_PROFILE;
   1467 tr 52 M=OAM_OPCODE_CONTROL_PROFILE;
   1468 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=F SLTH=T;
   1469 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=T;
   1470 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=F;
   1471 echo " PAYLOAD_TOS_FN";
   1472 tr 50 M=PAYLOAD_TOS_FN;
   1473 tr 51 M=PAYLOAD_TOS_FN;
   1474 tr 52 M=PAYLOAD_TOS_FN;
   1475 tr 71 M=PAYLOAD_TOS_FN TSE=F SLTH=T;
   1476 tr 71 M=PAYLOAD_TOS_FN TSE=T SLTH=T;
   1477 tr 71 M=PAYLOAD_TOS_FN TSE=T SLTH=F;
   1478 echo " PORT_COS_MAP";
   1479 tr 50 M=PORT_COS_MAP;
   1480 tr 51 M=PORT_COS_MAP;
   1481 tr 52 M=PORT_COS_MAP;
   1482 tr 71 M=PORT_COS_MAP TSE=F SLTH=T;
   1483 tr 71 M=PORT_COS_MAP TSE=T SLTH=T;
   1484 tr 71 M=PORT_COS_MAP TSE=T SLTH=F;
   1485 echo " PORT_OR_TRUNK_MAC_COUNT";
   1486 tr 50 M=PORT_OR_TRUNK_MAC_COUNT;
   1487 tr 51 M=PORT_OR_TRUNK_MAC_COUNT;
   1488 tr 52 M=PORT_OR_TRUNK_MAC_COUNT;
   1489 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=F SLTH=T;
   1490 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=T SLTH=T;
   1491 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=T SLTH=F;
   1492 echo " PORT_OR_TRUNK_MAC_LIMIT";
   1493 tr 50 M=PORT_OR_TRUNK_MAC_LIMIT;
   1494 tr 51 M=PORT_OR_TRUNK_MAC_LIMIT;
   1495 tr 52 M=PORT_OR_TRUNK_MAC_LIMIT;
   1496 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=F SLTH=T;
   1497 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=T SLTH=T;
   1498 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=T SLTH=F;
   1499 echo " PORT_TAB";
   1500 tr 50 M=PORT_TAB;
   1501 tr 51 M=PORT_TAB;
   1502 tr 52 M=PORT_TAB;
   1503 tr 71 M=PORT_TAB TSE=F SLTH=T;
   1504 tr 71 M=PORT_TAB TSE=T SLTH=T;
   1505 tr 71 M=PORT_TAB TSE=T SLTH=F;
   1506 echo " RESPONSIVE_PROTOCOL_MATCH";
   1507 tr 50 M=RESPONSIVE_PROTOCOL_MATCH;
   1508 tr 51 M=RESPONSIVE_PROTOCOL_MATCH;
   1509 tr 52 M=RESPONSIVE_PROTOCOL_MATCH;
   1510 tr 71 M=RESPONSIVE_PROTOCOL_MATCH TSE=F SLTH=T;
   1511 tr 71 M=RESPONSIVE_PROTOCOL_MATCH TSE=T SLTH=T;
   1512 tr 71 M=RESPONSIVE_PROTOCOL_MATCH TSE=T SLTH=F;
   1513 echo " RMEP";
   1514 tr 50 M=RMEP;
   1515 tr 51 M=RMEP;
   1516 tr 52 M=RMEP;
   1517 tr 71 M=RMEP TSE=F SLTH=T;
   1518 tr 71 M=RMEP TSE=T SLTH=T;
   1519 tr 71 M=RMEP TSE=T SLTH=F;
   1520 echo " SER_MEMORY";
   1521 tr 50 M=SER_MEMORY;
   1522 tr 51 M=SER_MEMORY;
   1523 tr 52 M=SER_MEMORY;
   1524 tr 71 M=SER_MEMORY TSE=F SLTH=T;
   1525 tr 71 M=SER_MEMORY TSE=T SLTH=T;
   1526 tr 71 M=SER_MEMORY TSE=T SLTH=F;
   1527 echo " SER_RESULT_0";
   1528 tr 50 M=SER_RESULT_0;
   1529 #tr 51 M=SER_RESULT_0;
   1530 #tr 52 M=SER_RESULT_0;
   1531 tr 71 M=SER_RESULT_0 TSE=F SLTH=T;
   1532 tr 71 M=SER_RESULT_0 TSE=T SLTH=T;
   1533 tr 71 M=SER_RESULT_0 TSE=T SLTH=F;
   1534 echo " SER_RESULT_1";
   1535 tr 50 M=SER_RESULT_1;
   1536 #tr 51 M=SER_RESULT_1;
   1537 #tr 52 M=SER_RESULT_1;
   1538 tr 71 M=SER_RESULT_1 TSE=F SLTH=T;
   1539 tr 71 M=SER_RESULT_1 TSE=T SLTH=T;
   1540 tr 71 M=SER_RESULT_1 TSE=T SLTH=F;
   1541 echo " SER_RESULT_DATA_0";
   1542 tr 50 M=SER_RESULT_DATA_0;
   1543 #tr 51 M=SER_RESULT_DATA_0;
   1544 #tr 52 M=SER_RESULT_DATA_0;
   1545 tr 71 M=SER_RESULT_DATA_0 TSE=F SLTH=T;
   1546 tr 71 M=SER_RESULT_DATA_0 TSE=T SLTH=T;
   1547 tr 71 M=SER_RESULT_DATA_0 TSE=T SLTH=F;
   1548 echo " SER_RESULT_DATA_1";
   1549 tr 50 M=SER_RESULT_DATA_1;
   1550 #tr 51 M=SER_RESULT_DATA_1;
   1551 #tr 52 M=SER_RESULT_DATA_1;
   1552 tr 71 M=SER_RESULT_DATA_1 TSE=F SLTH=T;
   1553 tr 71 M=SER_RESULT_DATA_1 TSE=T SLTH=T;
   1554 tr 71 M=SER_RESULT_DATA_1 TSE=T SLTH=F;
   1555 echo " SER_RESULT_EXPECTED_0";
   1556 tr 50 M=SER_RESULT_EXPECTED_0;
   1557 #tr 51 M=SER_RESULT_EXPECTED_0;
   1558 #tr 52 M=SER_RESULT_EXPECTED_0;
   1559 tr 71 M=SER_RESULT_EXPECTED_0 TSE=F SLTH=T;
   1560 tr 71 M=SER_RESULT_EXPECTED_0 TSE=T SLTH=T;
   1561 tr 71 M=SER_RESULT_EXPECTED_0 TSE=T SLTH=F;
   1562 echo " SER_RESULT_EXPECTED_1";
   1563 tr 50 M=SER_RESULT_EXPECTED_1;
   1564 #tr 51 M=SER_RESULT_EXPECTED_1;
   1565 #tr 52 M=SER_RESULT_EXPECTED_1;
   1566 tr 71 M=SER_RESULT_EXPECTED_1 TSE=F SLTH=T;
   1567 tr 71 M=SER_RESULT_EXPECTED_1 TSE=T SLTH=T;
   1568 tr 71 M=SER_RESULT_EXPECTED_1 TSE=T SLTH=F;
   1569 echo " SOURCE_TRUNK_MAP_MODBASE";
   1570 tr 50 M=SOURCE_TRUNK_MAP_MODBASE;
   1571 tr 51 M=SOURCE_TRUNK_MAP_MODBASE;
   1572 tr 52 M=SOURCE_TRUNK_MAP_MODBASE;
   1573 tr 71 M=SOURCE_TRUNK_MAP_MODBASE TSE=F SLTH=T;
   1574 tr 71 M=SOURCE_TRUNK_MAP_MODBASE TSE=T SLTH=T;
   1575 tr 71 M=SOURCE_TRUNK_MAP_MODBASE TSE=T SLTH=F;
   1576 echo " SOURCE_TRUNK_MAP_TABLE";
   1577 tr 50 M=SOURCE_TRUNK_MAP_TABLE;
   1578 tr 51 M=SOURCE_TRUNK_MAP_TABLE;
   1579 tr 52 M=SOURCE_TRUNK_MAP_TABLE;
   1580 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=F SLTH=T;
   1581 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=T SLTH=T;
   1582 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=T SLTH=F;
   1583 echo " SRC_MODID_BLOCK";
   1584 tr 50 M=SRC_MODID_BLOCK;
   1585 tr 51 M=SRC_MODID_BLOCK;
   1586 tr 52 M=SRC_MODID_BLOCK;
   1587 tr 71 M=SRC_MODID_BLOCK TSE=F SLTH=T;
   1588 tr 71 M=SRC_MODID_BLOCK TSE=T SLTH=T;
   1589 tr 71 M=SRC_MODID_BLOCK TSE=T SLTH=F;
   1590 echo " STG_TAB";
   1591 tr 50 M=STG_TAB;
   1592 tr 51 M=STG_TAB;
   1593 tr 52 M=STG_TAB;
   1594 tr 71 M=STG_TAB TSE=F SLTH=T;
   1595 tr 71 M=STG_TAB TSE=T SLTH=T;
   1596 tr 71 M=STG_TAB TSE=T SLTH=F;
   1597 echo " SYSTEM_CONFIG_TABLE";
   1598 tr 50 M=SYSTEM_CONFIG_TABLE;
   1599 tr 51 M=SYSTEM_CONFIG_TABLE;
   1600 tr 52 M=SYSTEM_CONFIG_TABLE;
   1601 tr 71 M=SYSTEM_CONFIG_TABLE TSE=F SLTH=T;
   1602 tr 71 M=SYSTEM_CONFIG_TABLE TSE=T SLTH=T;
   1603 tr 71 M=SYSTEM_CONFIG_TABLE TSE=T SLTH=F;
   1604 echo " SYSTEM_CONFIG_TABLE_MODBASE";
   1605 tr 50 M=SYSTEM_CONFIG_TABLE_MODBASE;
   1606 tr 51 M=SYSTEM_CONFIG_TABLE_MODBASE;
   1607 tr 52 M=SYSTEM_CONFIG_TABLE_MODBASE;
   1608 tr 71 M=SYSTEM_CONFIG_TABLE_MODBASE TSE=F SLTH=T;
   1609 tr 71 M=SYSTEM_CONFIG_TABLE_MODBASE TSE=T SLTH=T;
   1610 tr 71 M=SYSTEM_CONFIG_TABLE_MODBASE TSE=T SLTH=F;
   1611 echo " TCP_FN";
   1612 tr 50 M=TCP_FN;
   1613 tr 51 M=TCP_FN;
   1614 tr 52 M=TCP_FN;
   1615 tr 71 M=TCP_FN TSE=F SLTH=T;
   1616 tr 71 M=TCP_FN TSE=T SLTH=T;
   1617 tr 71 M=TCP_FN TSE=T SLTH=F;
   1618 echo " TOS_FN";
   1619 tr 50 M=TOS_FN;
   1620 tr 51 M=TOS_FN;
   1621 tr 52 M=TOS_FN;
   1622 tr 71 M=TOS_FN TSE=F SLTH=T;
   1623 tr 71 M=TOS_FN TSE=T SLTH=T;
   1624 tr 71 M=TOS_FN TSE=T SLTH=F;
   1625 echo " TRUNK32_CONFIG_TABLE";
   1626 tr 50 M=TRUNK32_CONFIG_TABLE;
   1627 tr 51 M=TRUNK32_CONFIG_TABLE;
   1628 tr 52 M=TRUNK32_CONFIG_TABLE;
   1629 tr 71 M=TRUNK32_CONFIG_TABLE TSE=F SLTH=T;
   1630 tr 71 M=TRUNK32_CONFIG_TABLE TSE=T SLTH=T;
   1631 tr 71 M=TRUNK32_CONFIG_TABLE TSE=T SLTH=F;
   1632 echo " TRUNK32_PORT_TABLE";
   1633 tr 50 M=TRUNK32_PORT_TABLE;
   1634 tr 51 M=TRUNK32_PORT_TABLE;
   1635 tr 52 M=TRUNK32_PORT_TABLE;
   1636 tr 71 M=TRUNK32_PORT_TABLE TSE=F SLTH=T;
   1637 tr 71 M=TRUNK32_PORT_TABLE TSE=T SLTH=T;
   1638 tr 71 M=TRUNK32_PORT_TABLE TSE=T SLTH=F;
   1639 echo " TRUNK_BITMAP";
   1640 tr 50 M=TRUNK_BITMAP;
   1641 tr 51 M=TRUNK_BITMAP;
   1642 tr 52 M=TRUNK_BITMAP;
   1643 tr 71 M=TRUNK_BITMAP TSE=F SLTH=T;
   1644 tr 71 M=TRUNK_BITMAP TSE=T SLTH=T;
   1645 tr 71 M=TRUNK_BITMAP TSE=T SLTH=F;
   1646 echo " TRUNK_EGR_MASK";
   1647 tr 50 M=TRUNK_EGR_MASK;
   1648 tr 51 M=TRUNK_EGR_MASK;
   1649 tr 52 M=TRUNK_EGR_MASK;
   1650 tr 71 M=TRUNK_EGR_MASK TSE=F SLTH=T;
   1651 tr 71 M=TRUNK_EGR_MASK TSE=T SLTH=T;
   1652 tr 71 M=TRUNK_EGR_MASK TSE=T SLTH=F;
   1653 echo " TRUNK_GROUP";
   1654 tr 50 M=TRUNK_GROUP;
   1655 tr 51 M=TRUNK_GROUP;
   1656 tr 52 M=TRUNK_GROUP;
   1657 tr 71 M=TRUNK_GROUP TSE=F SLTH=T;
   1658 tr 71 M=TRUNK_GROUP TSE=T SLTH=T;
   1659 tr 71 M=TRUNK_GROUP TSE=T SLTH=F;
   1660 echo " TTL_FN";
   1661 tr 50 M=TTL_FN;
   1662 tr 51 M=TTL_FN;
   1663 tr 52 M=TTL_FN;
   1664 tr 71 M=TTL_FN TSE=F SLTH=T;
   1665 tr 71 M=TTL_FN TSE=T SLTH=T;
   1666 tr 71 M=TTL_FN TSE=T SLTH=F;
   1667 echo " VLAN_MAC";
   1668 tr 50 M=VLAN_MAC;
   1669 tr 51 M=VLAN_MAC;
   1670 tr 52 M=VLAN_MAC;
   1671 tr 71 M=VLAN_MAC TSE=F SLTH=T;
   1672 tr 71 M=VLAN_MAC TSE=T SLTH=T;
   1673 tr 71 M=VLAN_MAC TSE=T SLTH=F;
   1674 echo " VLAN_OR_VFI_MAC_COUNT";
   1675 tr 50 M=VLAN_OR_VFI_MAC_COUNT;
   1676 tr 51 M=VLAN_OR_VFI_MAC_COUNT;
   1677 tr 52 M=VLAN_OR_VFI_MAC_COUNT;
   1678 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=F SLTH=T;
   1679 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=T SLTH=T;
   1680 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=T SLTH=F;
   1681 echo " VLAN_OR_VFI_MAC_LIMIT";
   1682 tr 50 M=VLAN_OR_VFI_MAC_LIMIT;
   1683 tr 51 M=VLAN_OR_VFI_MAC_LIMIT;
   1684 tr 52 M=VLAN_OR_VFI_MAC_LIMIT;
   1685 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=F SLTH=T;
   1686 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=T SLTH=T;
   1687 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=T SLTH=F;
   1688 echo " VLAN_PROFILE_2";
   1689 tr 50 M=VLAN_PROFILE_2;
   1690 tr 51 M=VLAN_PROFILE_2;
   1691 tr 52 M=VLAN_PROFILE_2;
   1692 tr 71 M=VLAN_PROFILE_2 TSE=F SLTH=T;
   1693 tr 71 M=VLAN_PROFILE_2 TSE=T SLTH=T;
   1694 tr 71 M=VLAN_PROFILE_2 TSE=T SLTH=F;
   1695 echo " VLAN_PROFILE_TAB";
   1696 tr 50 M=VLAN_PROFILE_TAB;
   1697 tr 51 M=VLAN_PROFILE_TAB;
   1698 tr 52 M=VLAN_PROFILE_TAB;
   1699 tr 71 M=VLAN_PROFILE_TAB TSE=F SLTH=T;
   1700 tr 71 M=VLAN_PROFILE_TAB TSE=T SLTH=T;
   1701 tr 71 M=VLAN_PROFILE_TAB TSE=T SLTH=F;
   1702 echo " VLAN_PROTOCOL";
   1703 tr 50 M=VLAN_PROTOCOL;
   1704 tr 51 M=VLAN_PROTOCOL;
   1705 tr 52 M=VLAN_PROTOCOL;
   1706 tr 71 M=VLAN_PROTOCOL TSE=F SLTH=T;
   1707 tr 71 M=VLAN_PROTOCOL TSE=T SLTH=T;
   1708 tr 71 M=VLAN_PROTOCOL TSE=T SLTH=F;
   1709 echo " VLAN_PROTOCOL_DATA";
   1710 tr 50 M=VLAN_PROTOCOL_DATA;
   1711 tr 51 M=VLAN_PROTOCOL_DATA;
   1712 tr 52 M=VLAN_PROTOCOL_DATA;
   1713 tr 71 M=VLAN_PROTOCOL_DATA TSE=F SLTH=T;
   1714 tr 71 M=VLAN_PROTOCOL_DATA TSE=T SLTH=T;
   1715 tr 71 M=VLAN_PROTOCOL_DATA TSE=T SLTH=F;
   1716 echo " VLAN_SUBNET";
   1717 tr 50 M=VLAN_SUBNET;
   1718 tr 51 M=VLAN_SUBNET;
   1719 tr 52 M=VLAN_SUBNET;
   1720 tr 71 M=VLAN_SUBNET TSE=F SLTH=T;
   1721 tr 71 M=VLAN_SUBNET TSE=T SLTH=T;
   1722 tr 71 M=VLAN_SUBNET TSE=T SLTH=F;
   1723 echo " VLAN_SUBNET_DATA_ONLY";
   1724 tr 50 M=VLAN_SUBNET_DATA_ONLY;
   1725 tr 51 M=VLAN_SUBNET_DATA_ONLY;
   1726 tr 52 M=VLAN_SUBNET_DATA_ONLY;
   1727 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=F SLTH=T;
   1728 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=T SLTH=T;
   1729 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=T SLTH=F;
   1730 echo " VLAN_SUBNET_ONLY";
   1731 tr 50 M=VLAN_SUBNET_ONLY;
   1732 tr 51 M=VLAN_SUBNET_ONLY;
   1733 tr 52 M=VLAN_SUBNET_ONLY;
   1734 tr 71 M=VLAN_SUBNET_ONLY TSE=F SLTH=T;
   1735 tr 71 M=VLAN_SUBNET_ONLY TSE=T SLTH=T;
   1736 tr 71 M=VLAN_SUBNET_ONLY TSE=T SLTH=F;
   1737 echo " VLAN_TAB";
   1738 tr 50 M=VLAN_TAB;
   1739 tr 51 M=VLAN_TAB;
   1740 tr 52 M=VLAN_TAB;
   1741 tr 71 M=VLAN_TAB TSE=F SLTH=T;
   1742 tr 71 M=VLAN_TAB TSE=T SLTH=T;
   1743 tr 71 M=VLAN_TAB TSE=T SLTH=F;
   1744 echo " VLAN_XLATE";
   1745 tr 50 M=VLAN_XLATE;
   1746 tr 51 M=VLAN_XLATE;
   1747 tr 52 M=VLAN_XLATE;
   1748 tr 71 M=VLAN_XLATE TSE=F SLTH=T;
   1749 tr 71 M=VLAN_XLATE TSE=T SLTH=T;
   1750 tr 71 M=VLAN_XLATE TSE=T SLTH=F;
   1751 
   1752 
   1753 echo " PORT_MAC_BLOCK";
   1754 tr 50 M=PORT_MAC_BLOCK;
   1755 tr 51 M=PORT_MAC_BLOCK;
   1756 tr 52 M=PORT_MAC_BLOCK;
   1757 tr 71 M=PORT_MAC_BLOCK TSE=F SLTH=T;
   1758 tr 71 M=PORT_MAC_BLOCK TSE=T SLTH=T;
   1759 tr 71 M=PORT_MAC_BLOCK TSE=T SLTH=F;
   1760 echo " CBPCELLHEADER";
   1761 tr 50 M=CBPCELLHEADER;
   1762 tr 51 M=CBPCELLHEADER;
   1763 tr 52 M=CBPCELLHEADER;
   1764 tr 71 M=CBPCELLHEADER TSE=F SLTH=T;
   1765 tr 71 M=CBPCELLHEADER TSE=T SLTH=T;
   1766 tr 71 M=CBPCELLHEADER TSE=T SLTH=F;
   1767 echo " CBPDATA0";
   1768 tr 50 M=CBPDATA0;
   1769 tr 51 M=CBPDATA0;
   1770 tr 52 M=CBPDATA0;
   1771 tr 71 M=CBPDATA0 TSE=F SLTH=T;
   1772 tr 71 M=CBPDATA0 TSE=T SLTH=T;
   1773 tr 71 M=CBPDATA0 TSE=T SLTH=F;
   1774 echo " CBPDATA1";
   1775 tr 50 M=CBPDATA1;
   1776 tr 51 M=CBPDATA1;
   1777 tr 52 M=CBPDATA1;
   1778 tr 71 M=CBPDATA1 TSE=F SLTH=T;
   1779 tr 71 M=CBPDATA1 TSE=T SLTH=T;
   1780 tr 71 M=CBPDATA1 TSE=T SLTH=F;
   1781 echo " CBPDATA2";
   1782 tr 50 M=CBPDATA2;
   1783 tr 51 M=CBPDATA2;
   1784 tr 52 M=CBPDATA2;
   1785 tr 71 M=CBPDATA2 TSE=F SLTH=T;
   1786 tr 71 M=CBPDATA2 TSE=T SLTH=T;
   1787 tr 71 M=CBPDATA2 TSE=T SLTH=F;
   1788 echo " CBPDATA3";
   1789 tr 50 M=CBPDATA3;
   1790 tr 51 M=CBPDATA3;
   1791 tr 52 M=CBPDATA3;
   1792 tr 71 M=CBPDATA3 TSE=F SLTH=T;
   1793 tr 71 M=CBPDATA3 TSE=T SLTH=T;
   1794 tr 71 M=CBPDATA3 TSE=T SLTH=F;
   1795 echo " CBPDATA4";
   1796 tr 50 M=CBPDATA4;
   1797 tr 51 M=CBPDATA4;
   1798 tr 52 M=CBPDATA4;
   1799 tr 71 M=CBPDATA4 TSE=F SLTH=T;
   1800 tr 71 M=CBPDATA4 TSE=T SLTH=T;
   1801 tr 71 M=CBPDATA4 TSE=T SLTH=F;
   1802 echo " CBPDATA5";
   1803 tr 50 M=CBPDATA5;
   1804 tr 51 M=CBPDATA5;
   1805 tr 52 M=CBPDATA5;
   1806 tr 71 M=CBPDATA5 TSE=F SLTH=T;
   1807 tr 71 M=CBPDATA5 TSE=T SLTH=T;
   1808 tr 71 M=CBPDATA5 TSE=T SLTH=F;
   1809 echo " CBPDATA6";
   1810 tr 50 M=CBPDATA6;
   1811 tr 51 M=CBPDATA6;
   1812 tr 52 M=CBPDATA6;
   1813 tr 71 M=CBPDATA6 TSE=F SLTH=T;
   1814 tr 71 M=CBPDATA6 TSE=T SLTH=T;
   1815 tr 71 M=CBPDATA6 TSE=T SLTH=F;
   1816 echo " CBPDATA7";
   1817 tr 50 M=CBPDATA7;
   1818 tr 51 M=CBPDATA7;
   1819 tr 52 M=CBPDATA7;
   1820 tr 71 M=CBPDATA7 TSE=F SLTH=T;
   1821 tr 71 M=CBPDATA7 TSE=T SLTH=T;
   1822 tr 71 M=CBPDATA7 TSE=T SLTH=F;
   1823 echo " CBPPKTHEADER0";
   1824 tr 50 M=CBPPKTHEADER0;
   1825 tr 51 M=CBPPKTHEADER0;
   1826 tr 52 M=CBPPKTHEADER0;
   1827 tr 71 M=CBPPKTHEADER0 TSE=F SLTH=T;
   1828 tr 71 M=CBPPKTHEADER0 TSE=T SLTH=T;
   1829 tr 71 M=CBPPKTHEADER0 TSE=T SLTH=F;
   1830 echo " CBPPKTHEADER1";
   1831 tr 50 M=CBPPKTHEADER1;
   1832 tr 51 M=CBPPKTHEADER1;
   1833 tr 52 M=CBPPKTHEADER1;
   1834 tr 71 M=CBPPKTHEADER1 TSE=F SLTH=T;
   1835 tr 71 M=CBPPKTHEADER1 TSE=T SLTH=T;
   1836 tr 71 M=CBPPKTHEADER1 TSE=T SLTH=F;
   1837 echo " CBPPKTHEADER2";
   1838 tr 50 M=CBPPKTHEADER2;
   1839 tr 51 M=CBPPKTHEADER2;
   1840 tr 52 M=CBPPKTHEADER2;
   1841 tr 71 M=CBPPKTHEADER2 TSE=F SLTH=T;
   1842 tr 71 M=CBPPKTHEADER2 TSE=T SLTH=T;
   1843 tr 71 M=CBPPKTHEADER2 TSE=T SLTH=F;
   1844 echo " CBPPKTHEADER_EXT";
   1845 tr 50 M=CBPPKTHEADER_EXT;
   1846 tr 51 M=CBPPKTHEADER_EXT;
   1847 tr 52 M=CBPPKTHEADER_EXT;
   1848 tr 71 M=CBPPKTHEADER_EXT TSE=F SLTH=T;
   1849 tr 71 M=CBPPKTHEADER_EXT TSE=T SLTH=T;
   1850 tr 71 M=CBPPKTHEADER_EXT TSE=T SLTH=F;
   1851 echo " MMU_WRED_UC_QUEUE_CONFIG";
   1852 tr 50 M=MMU_WRED_UC_QUEUE_CONFIG;
   1853 tr 51 M=MMU_WRED_UC_QUEUE_CONFIG;
   1854 tr 52 M=MMU_WRED_UC_QUEUE_CONFIG;
   1855 tr 71 M=MMU_WRED_UC_QUEUE_CONFIG TSE=F SLTH=T;
   1856 tr 71 M=MMU_WRED_UC_QUEUE_CONFIG TSE=T SLTH=T;
   1857 tr 71 M=MMU_WRED_UC_QUEUE_CONFIG TSE=T SLTH=F;
   1858 echo " MMU_WRED_DROP_PROFILE_GREEN";
   1859 tr 50 M=MMU_WRED_DROP_PROFILE_GREEN;
   1860 tr 51 M=MMU_WRED_DROP_PROFILE_GREEN;
   1861 tr 52 M=MMU_WRED_DROP_PROFILE_GREEN;
   1862 tr 71 M=MMU_WRED_DROP_PROFILE_GREEN TSE=F SLTH=T;
   1863 tr 71 M=MMU_WRED_DROP_PROFILE_GREEN TSE=T SLTH=T;
   1864 tr 71 M=MMU_WRED_DROP_PROFILE_GREEN TSE=T SLTH=F;
   1865 echo " MMU_WRED_DROP_PROFILE_RED";
   1866 tr 50 M=MMU_WRED_DROP_PROFILE_RED;
   1867 tr 51 M=MMU_WRED_DROP_PROFILE_RED;
   1868 tr 52 M=MMU_WRED_DROP_PROFILE_RED;
   1869 tr 71 M=MMU_WRED_DROP_PROFILE_RED TSE=F SLTH=T;
   1870 tr 71 M=MMU_WRED_DROP_PROFILE_RED TSE=T SLTH=T;
   1871 tr 71 M=MMU_WRED_DROP_PROFILE_RED TSE=T SLTH=F;
   1872 echo " MMU_WRED_DROP_PROFILE_YELLOW";
   1873 tr 50 M=MMU_WRED_DROP_PROFILE_YELLOW;
   1874 tr 51 M=MMU_WRED_DROP_PROFILE_YELLOW;
   1875 tr 52 M=MMU_WRED_DROP_PROFILE_YELLOW;
   1876 tr 71 M=MMU_WRED_DROP_PROFILE_YELLOW TSE=F SLTH=T;
   1877 tr 71 M=MMU_WRED_DROP_PROFILE_YELLOW TSE=T SLTH=T;
   1878 tr 71 M=MMU_WRED_DROP_PROFILE_YELLOW TSE=T SLTH=F;
   1879 echo " MMU_WRED_MARK_PROFILE_GREEN";
   1880 tr 50 M=MMU_WRED_MARK_PROFILE_GREEN;
   1881 tr 51 M=MMU_WRED_MARK_PROFILE_GREEN;
   1882 tr 52 M=MMU_WRED_MARK_PROFILE_GREEN;
   1883 tr 71 M=MMU_WRED_MARK_PROFILE_GREEN TSE=F SLTH=T;
   1884 tr 71 M=MMU_WRED_MARK_PROFILE_GREEN TSE=T SLTH=T;
   1885 tr 71 M=MMU_WRED_MARK_PROFILE_GREEN TSE=T SLTH=F;
   1886 echo " MMU_WRED_MARK_PROFILE_RED";
   1887 tr 50 M=MMU_WRED_MARK_PROFILE_RED;
   1888 tr 51 M=MMU_WRED_MARK_PROFILE_RED;
   1889 tr 52 M=MMU_WRED_MARK_PROFILE_RED;
   1890 tr 71 M=MMU_WRED_MARK_PROFILE_RED TSE=F SLTH=T;
   1891 tr 71 M=MMU_WRED_MARK_PROFILE_RED TSE=T SLTH=T;
   1892 tr 71 M=MMU_WRED_MARK_PROFILE_RED TSE=T SLTH=F;
   1893 echo " MMU_WRED_MARK_PROFILE_YELLOW";
   1894 tr 50 M=MMU_WRED_MARK_PROFILE_YELLOW;
   1895 tr 51 M=MMU_WRED_MARK_PROFILE_YELLOW;
   1896 tr 52 M=MMU_WRED_MARK_PROFILE_YELLOW;
   1897 tr 71 M=MMU_WRED_MARK_PROFILE_YELLOW TSE=F SLTH=T;
   1898 tr 71 M=MMU_WRED_MARK_PROFILE_YELLOW TSE=T SLTH=T;
   1899 tr 71 M=MMU_WRED_MARK_PROFILE_YELLOW TSE=T SLTH=F;
   1900 
   1901 echo " SER_ACC_TYPE_MAP";
   1902 tr 50 M=SER_ACC_TYPE_MAP;
   1903 tr 51 M=SER_ACC_TYPE_MAP;
   1904 tr 52 M=SER_ACC_TYPE_MAP;
   1905 tr 71 M=SER_ACC_TYPE_MAP TSE=F SLTH=T;
   1906 tr 71 M=SER_ACC_TYPE_MAP TSE=T SLTH=T;
   1907 tr 71 M=SER_ACC_TYPE_MAP TSE=T SLTH=F;
   1908 
   1909 #The BUCKETf will be updated if MISCCONFIG.METERING_CLK_ENf=1
   1910 # The bit will be set after doing init misc
   1911 init soc; init mmu;
   1912 echo " MMU_MAX_BUCKET_EVEN";
   1913 tr 50 M=MMU_MAX_BUCKET_EVEN;
   1914 tr 51 M=MMU_MAX_BUCKET_EVEN;
   1915 tr 52 M=MMU_MAX_BUCKET_EVEN;
   1916 tr 71 M=MMU_MAX_BUCKET_EVEN TSE=F SLTH=T;
   1917 tr 71 M=MMU_MAX_BUCKET_EVEN TSE=T SLTH=T;
   1918 tr 71 M=MMU_MAX_BUCKET_EVEN TSE=T SLTH=F;
   1919 echo " MMU_MAX_BUCKET_ODD";
   1920 tr 50 M=MMU_MAX_BUCKET_ODD;
   1921 tr 51 M=MMU_MAX_BUCKET_ODD;
   1922 tr 52 M=MMU_MAX_BUCKET_ODD;
   1923 tr 71 M=MMU_MAX_BUCKET_ODD TSE=F SLTH=T;
   1924 tr 71 M=MMU_MAX_BUCKET_ODD TSE=T SLTH=T;
   1925 tr 71 M=MMU_MAX_BUCKET_ODD TSE=T SLTH=F;
   1926 echo " MMU_MIN_BUCKET_EVEN";
   1927 tr 50 M=MMU_MIN_BUCKET_EVEN;
   1928 tr 51 M=MMU_MIN_BUCKET_EVEN;
   1929 tr 52 M=MMU_MIN_BUCKET_EVEN;
   1930 tr 71 M=MMU_MIN_BUCKET_EVEN TSE=F SLTH=T;
   1931 tr 71 M=MMU_MIN_BUCKET_EVEN TSE=T SLTH=T;
   1932 tr 71 M=MMU_MIN_BUCKET_EVEN TSE=T SLTH=F;
   1933 tr 51 M=MMU_MIN_BUCKET_ODD;
   1934 echo " MMU_MIN_BUCKET_ODD";
   1935 tr 50 M=MMU_MIN_BUCKET_ODD;
   1936 tr 52 M=MMU_MIN_BUCKET_ODD;
   1937 tr 71 M=MMU_MIN_BUCKET_ODD TSE=F SLTH=T;
   1938 tr 71 M=MMU_MIN_BUCKET_ODD TSE=T SLTH=T;
   1939 tr 71 M=MMU_MIN_BUCKET_ODD TSE=T SLTH=F;
   1940 
   1941 #It doesn't support read. Write also require MMU_MIN_BUCKET_ODDother commends. 
   1942 #echo " XLPORT_WC_UCMEM_DATA";
   1943 #tr 50 M=XLPORT_WC_UCMEM_DATA;
   1944 #tr 51 M=XLPORT_WC_UCMEM_DATA;
   1945 #tr 52 M=XLPORT_WC_UCMEM_DATA;
   1946 #tr 71 M=XLPORT_WC_UCMEM_DATA TSE=F SLTH=T;
   1947 #tr 71 M=XLPORT_WC_UCMEM_DATA TSE=T SLTH=T;
   1948 #tr 71 M=XLPORT_WC_UCMEM_DATA TSE=T SLTH=F;
   1949 
   1950 #Need to disable WRED_REFRESH_ENf before testing
   1951 #echo " MMU_WRED_UC_QUEUE_AVG_QSIZE";
   1952 #tr 50 M=MMU_WRED_UC_QUEUE_AVG_QSIZE;
   1953 #tr 51 M=MMU_WRED_UC_QUEUE_AVG_QSIZE;
   1954 #tr 52 M=MMU_WRED_UC_QUEUE_AVG_QSIZE;
   1955 #tr 71 M=MMU_WRED_UC_QUEUE_AVG_QSIZE TSE=F SLTH=T;
   1956 #tr 71 M=MMU_WRED_UC_QUEUE_AVG_QSIZE TSE=T SLTH=T;
   1957 #tr 71 M=MMU_WRED_UC_QUEUE_AVG_QSIZE TSE=T SLTH=F;
   1958 #echo " MMU_WRED_MARK_THD";
   1959 #tr 50 M=MMU_WRED_MARK_THD;
   1960 #tr 51 M=MMU_WRED_MARK_THD;
   1961 #tr 52 M=MMU_WRED_MARK_THD;
   1962 #tr 71 M=MMU_WRED_MARK_THD TSE=F SLTH=T;
   1963 #tr 71 M=MMU_WRED_MARK_THD TSE=T SLTH=T;
   1964 #tr 71 M=MMU_WRED_MARK_THD TSE=T SLTH=F;
   1965 
   1966 # Re-initialize to clean up of various read/wrires to MMU memories
   1967 set rct=true
   1968 rcload rc.soc
   1969 counter off
   1970 l2mode off
   1971 linkscan off
   1972 
   1973 echo "Running counter width verification test ..."
   1974 tr 30
   1975 $done
   1976 
   1977 echo "Running counter read/write test ..."
   1978 tr 31
   1979 $done
   1980 
   1981 #L2/L3 hashing tests
   1982 echo "Running L2 insert/delete/lookup test ..."
   1983 tr 32
   1984 $done
   1985 
   1986 echo "Running L2 overflow insert test ..."
   1987 tr 33
   1988 $done
   1989 
   1990 echo "Running L2 hash test ..."
   1991 tr 34
   1992 $done
   1993 
   1994 echo "Running L2 delete by port test ..."
   1995 tr 35
   1996 $done
   1997 
   1998 echo "Running L2 delete by vlan test ..."
   1999 tr 36
   2000 $done
   2001 
   2002 echo "Running IPV4 overflow insert test ...";
   2003 tr 87 IPMCEnable=False;
   2004 tr 87 IPMCEnable=True;
   2005 echo "Running IPV4 hash test ...";
   2006 tr 88 IPMCEnable=False;
   2007 tr 88 IPMCEnable=True;
   2008 echo "Running IPV6 overflow insert test ...";
   2009 tr 85 IPMCEnable=False;
   2010 tr 85 IPMCEnable=True;
   2011 echo "Running IPV6 hash test ...";
   2012 tr 86 IPMCEnable=False;
   2013 tr 86 IPMCEnable=True;
   2014 
   2015 echo "Running VLAN translate overflow insert test ..."
   2016 tr 100
   2017 
   2018 echo "Running VLAN translate hash tests ..."
   2019 tr 101 hash=0
   2020 tr 101 hash=1
   2021 tr 101 hash=2
   2022 tr 101 hash=3
   2023 tr 101 hash=4
   2024 tr 101 hash=5
   2025 $done
   2026 
   2027 echo "Running Egress VLAN translate overflow insert test ..."
   2028 tr 102
   2029 $done
   2030 
   2031 echo "Running Egress VLAN translate hash tests ..."
   2032 tr 103 hash=0
   2033 tr 103 hash=1
   2034 tr 103 hash=2
   2035 tr 103 hash=3
   2036 tr 103 hash=4
   2037 tr 103 hash=5
   2038 $done
   2039 #no mpls in hurricane3
   2040 #echo "Running MPLS overflow insert test ..."
   2041 #tr 104
   2042 #$done
   2043 
   2044 #echo "Running MPLS hash tests ..."
   2045 #tr 105 hash=0
   2046 #tr 105 hash=1
   2047 #tr 105 hash=2
   2048 #tr 105 hash=3
   2049 #tr 105 hash=4
   2050 #tr 105 hash=5
   2051 #$done
   2052 
   2053 echo "Running Software Error Recovery ..."
   2054 tr 144 testType=spread
   2055 $done
   2056 
   2057 # Disable the link thread while testing the tr 60
   2058 # Reload rc will restart the link thread, so set rct=false before testing
   2059 set rct=false
   2060 rcload rc.soc
   2061 linkscan off
   2062 
   2063 echo "Running MDIO Linkscan test"
   2064 tr 60 readcount=10000
   2065 $done
   2066 # Re-initialize to set rct=true after tr 60 testing
   2067 set rct=true
   2068 
   2069 echo "Testing CPU DMA loopback ..."
   2070 tr 17 c=5
   2071 $done
   2072 
   2073 echo "Testing CPU DMA, Scatter/Gather Reload ..."
   2074 tr 22
   2075 $done
   2076 
   2077 echo "Testing CPU DMA, Scatter/Gather Simple ..."
   2078 tr 23
   2079 $done
   2080 
   2081 echo "Testing CPU DMA, Scatter/Gather Random ..."
   2082 tr 24
   2083 $done
   2084 
   2085 echo "Running BCM Packet Send Test..."
   2086 tr 40 pbm=ge
   2087 $done
   2088 
   2089 echo "Running BCM Packet Receive Test..."
   2090 tr 41
   2091 $done
   2092 
   2093 # WH2 support only cos=0 - cos=3
   2094 echo "Running MAC loopback V2 on all ports ..."
   2095 tr 48 coss=0 cose=3 smi=103 dmi=42 vlan=5 pi=0x11335577 sendm=single
   2096 $done
   2097 
   2098 echo "Running PHY loopback V2 on all ports ..."
   2099 tr 49 coss=0 cose=3 smi=52 dmi=83 vlan=23 pi=0x01204007
   2100 $done
   2101 
   2102 #Internal snake Loopback
   2103 echo "Running internal snake on all ports, MAC loopback ..."
   2104 tr 39 coss=0 cose=3 loopbackmode=mac snakepath=two PBM=e
   2105 $done
   2106 
   2107 echo "Running internal snake on all ports, PHY loopback ..."
   2108 tr 39 coss=0 cose=3 loopbackmode=phy snakepath=two PBM=e
   2109 $done
   2110 
   2111 echo "Running MAC loopback TR 18 on all ports ..."
   2112 tr 18 coss=0 cose=3 pbm=ge speed=10
   2113 tr 18 coss=0 cose=3 pbm=ge speed=100
   2114 tr 18 coss=0 cose=3 pbm=ge speed=1000
   2115 tr 18 coss=0 cose=3 pbm=ge speed=MAX
   2116 $done
   2117 
   2118 echo "Running PHY loopback TR 19 on all ports ..."
   2119 tr 19 coss=0 cose=3 pbm=ge speed=10
   2120 tr 19 coss=0 cose=3 pbm=ge speed=100
   2121 tr 19 coss=0 cose=3 pbm=ge speed=1000
   2122 tr 19 coss=0 cose=3 pbm=ge speed=MAX
   2123 $done
   2124 
   2125 #Traffic Test
   2126 echo "Running Traffic Test in MAC mode ..."
   2127 tr 72 RM=MAC PBM=ge
   2128 #tr 72 RM=MAC PBM=xe
   2129 $done
   2130 
   2131 echo "Running Traffic Test in PHY mode ..."
   2132 tr 72 RM=PHY PBM=ge
   2133 #tr 72 RM=PHY PBM=xe
   2134 $done
   2135 
   2136 #SNMP
   2137 echo "SNMP MIB Object Test"
   2138 tr 73
   2139 $done
   2140 
   2141 #Reload Test
   2142 echo "TX Reload Test"
   2143 tr 90 port=ge0
   2144 
   2145 echo "RX Reload Test"
   2146 tr 91 port=ge1 TxPktCount=10
   2147 
   2148 # Show status
   2149 date
   2150 tl
   2151 local returnCode $?
   2152 
   2153 echo Tests Complete.  Reinitializing ...
   2154 config refresh
   2155 rcload rc.soc
   2156 counter off
   2157 l2mode off
   2158 
   2159 # We want to show the return code from the tl command which
   2160 # lists the results. The automated test infrastructure keys off of this
   2161 # value
   2162 echo "testsuite: finished: sanity: $returnCode"