kt2sanity.soc (181752B)
1 # 2 # This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 # 4 # Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 6 # Katana2 (BCM56450) Sanity 7 # 8 # Script to run all available tests as quickly as possible. 9 # For testing basic sanity of new drivers, simulators, chips, etc. 10 # 11 local CIs ci0,ci2,ci4; 12 local DNs 0-5; 13 14 if $?BCM56450_A0 || $?BCM56450_B0 \ 15 'local LIKE_BCM56450 1' 16 17 if $?BCM56248_A0 || $?BCM56248_B0 \ 18 'local LIKE_BCM56248 1' 19 20 if $?BCM55455_A0 || $?BCM55455_B0 \ 21 'local LIKE_BCM55455 1' 22 23 if $?BCM56455_A0 || $?BCM56455_B0 \ 24 'local LIKE_BCM56455 1; \ 25 local CIs ci0,ci2;\ 26 local DNs 0-2;' 27 28 29 config clear 30 31 config add bcm5645x_config=2 32 config bcm5645x_config=2 33 34 config add auto_polarity_flip=1 35 config auto_polarity_flip=1 36 37 config add auto_portgroup=1 38 config auto_portgroup=1 39 40 config add parity_enable=0; 41 config parity_enable=0; 42 43 config 44 45 # PCI override is a temporary stuff 46 47 if $?BCM56455_A0 || $?BCM56455_B0 \ 48 'echo "KT1 Package"; \ 49 config clear; \ 50 config add bcm5645x_config=1; \ 51 config add pci_override_dev=0xb455; \ 52 config add parity_enable=0; \ 53 config; \ 54 $done;' 55 56 if $?BCM56248_A0 || $?BCM56248_B0 || $?BCM56456_A0 || $?BCM56456_B0 || $?BCM55455_A0 || $?BCM55455_B0\ 57 'local LIKE_BCM56456 1' 58 59 if $?run_full_sanity "echo Running FullSanity" else "echo Running ScreenSanity" 60 61 62 # This line is used for automated sanity regression - PLEASE DO NOT REMOVE 63 echo "testsuite: started: sanity" 64 65 rcload rc.soc 66 counter off 67 l2mode off 68 69 # We need to print out port status since any cabling effects results. 70 *:ps 71 72 # Avoid link messages while testing 73 linkscan off 74 75 init 76 init misc 77 init mmu 78 79 local done 'echo " Done"' 80 81 # Set run command script not to fail on errors reported by commands 82 # this allows the script to continue if a test fails 83 #set rcerror=false 84 85 # Set up test mode: don't stop on errors, show progress on each test 86 tm -stoponerror +progress 87 # Unselect all 88 ts -* 89 90 #Display some useful information 91 date 92 ver 93 soc 94 95 #Start Test 96 echo "Running PCI S-Channel Buf ..." 97 tr 4 98 $done 99 100 echo "Running Register reset defaults ..." 101 tr 1 102 $done 103 104 if !$?ihost_mode \ 105 'echo "Running PCI Compliance ..."; \ 106 tr 2; \ 107 $done;' 108 109 if !$?ihost_mode \ 110 'echo "Running Register read/write ..."; \ 111 tr 3; \ 112 echo "DONE ..."; \ 113 $done;' 114 115 init soc; init misc; init mmu; 116 #Clean up after register read/write test. 117 118 rcload rc.soc 119 counter off 120 l2mode off 121 echo "Running CPU Benchmarks ..." 122 tr 21 123 $done 124 linkscan off 125 126 init soc; init misc; init mmu; 127 kt2sanity_ecc_off.soc 128 #set rctest=false 129 130 echo "Running Switching Memory Tests ..." 131 132 echo " ALTERNATE_EMIRROR_BITMAP"; 133 tr 50 M=ALTERNATE_EMIRROR_BITMAP; 134 tr 51 M=ALTERNATE_EMIRROR_BITMAP; 135 tr 52 M=ALTERNATE_EMIRROR_BITMAP; 136 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=F SLTH=T; 137 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=T SLTH=T; 138 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=T SLTH=F; 139 echo " BCAST_BLOCK_MASK"; 140 tr 50 M=BCAST_BLOCK_MASK; 141 tr 51 M=BCAST_BLOCK_MASK; 142 tr 52 M=BCAST_BLOCK_MASK; 143 tr 71 M=BCAST_BLOCK_MASK TSE=F SLTH=T; 144 tr 71 M=BCAST_BLOCK_MASK TSE=T SLTH=T; 145 tr 71 M=BCAST_BLOCK_MASK TSE=T SLTH=F; 146 echo " COS_MAP_SEL"; 147 tr 50 M=COS_MAP_SEL; 148 tr 51 M=COS_MAP_SEL; 149 tr 52 M=COS_MAP_SEL; 150 tr 71 M=COS_MAP_SEL TSE=F SLTH=T; 151 tr 71 M=COS_MAP_SEL TSE=T SLTH=T; 152 tr 71 M=COS_MAP_SEL TSE=T SLTH=F; 153 echo " CPU_COS_MAP"; 154 tr 50 M=CPU_COS_MAP; 155 tr 51 M=CPU_COS_MAP; 156 tr 52 M=CPU_COS_MAP; 157 tr 71 M=CPU_COS_MAP TSE=F SLTH=T; 158 tr 71 M=CPU_COS_MAP TSE=T SLTH=T; 159 tr 71 M=CPU_COS_MAP TSE=T SLTH=F; 160 echo " CPU_COS_MAP_DATA_ONLY"; 161 tr 50 M=CPU_COS_MAP_DATA_ONLY; 162 tr 51 M=CPU_COS_MAP_DATA_ONLY; 163 tr 52 M=CPU_COS_MAP_DATA_ONLY; 164 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=F SLTH=T; 165 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=T SLTH=T; 166 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=T SLTH=F; 167 echo " CPU_COS_MAP_ONLY"; 168 tr 50 M=CPU_COS_MAP_ONLY; 169 tr 51 M=CPU_COS_MAP_ONLY; 170 tr 52 M=CPU_COS_MAP_ONLY; 171 tr 71 M=CPU_COS_MAP_ONLY TSE=F SLTH=T; 172 tr 71 M=CPU_COS_MAP_ONLY TSE=T SLTH=T; 173 tr 71 M=CPU_COS_MAP_ONLY TSE=T SLTH=F; 174 echo " CPU_PBM"; 175 tr 50 M=CPU_PBM; 176 #tr 51 M=CPU_PBM; 177 #tr 52 M=CPU_PBM; 178 tr 71 M=CPU_PBM TSE=F SLTH=T; 179 tr 71 M=CPU_PBM TSE=T SLTH=T; 180 tr 71 M=CPU_PBM TSE=T SLTH=F; 181 echo " CPU_PBM_2"; 182 tr 50 M=CPU_PBM_2; 183 #tr 51 M=CPU_PBM_2; 184 #tr 52 M=CPU_PBM_2; 185 tr 71 M=CPU_PBM_2 TSE=F SLTH=T; 186 tr 71 M=CPU_PBM_2 TSE=T SLTH=T; 187 tr 71 M=CPU_PBM_2 TSE=T SLTH=F; 188 echo " CPU_TS_MAP"; 189 tr 50 M=CPU_TS_MAP; 190 tr 51 M=CPU_TS_MAP; 191 tr 52 M=CPU_TS_MAP; 192 tr 71 M=CPU_TS_MAP TSE=F SLTH=T; 193 tr 71 M=CPU_TS_MAP TSE=T SLTH=T; 194 tr 71 M=CPU_TS_MAP TSE=T SLTH=F; 195 echo " CTR_DEQ_STATUS_MEM"; 196 tr 50 M=CTR_DEQ_STATUS_MEM; 197 tr 51 M=CTR_DEQ_STATUS_MEM; 198 tr 52 M=CTR_DEQ_STATUS_MEM; 199 tr 71 M=CTR_DEQ_STATUS_MEM TSE=F SLTH=T; 200 tr 71 M=CTR_DEQ_STATUS_MEM TSE=T SLTH=T; 201 tr 71 M=CTR_DEQ_STATUS_MEM TSE=T SLTH=F; 202 echo " CTR_FLEX_COUNT_0"; 203 tr 50 M=CTR_FLEX_COUNT_0; 204 tr 51 M=CTR_FLEX_COUNT_0; 205 tr 52 M=CTR_FLEX_COUNT_0; 206 tr 71 M=CTR_FLEX_COUNT_0 TSE=F SLTH=T; 207 tr 71 M=CTR_FLEX_COUNT_0 TSE=T SLTH=T; 208 tr 71 M=CTR_FLEX_COUNT_0 TSE=T SLTH=F; 209 echo " CTR_FLEX_COUNT_1"; 210 tr 50 M=CTR_FLEX_COUNT_1; 211 tr 51 M=CTR_FLEX_COUNT_1; 212 tr 52 M=CTR_FLEX_COUNT_1; 213 tr 71 M=CTR_FLEX_COUNT_1 TSE=F SLTH=T; 214 tr 71 M=CTR_FLEX_COUNT_1 TSE=T SLTH=T; 215 tr 71 M=CTR_FLEX_COUNT_1 TSE=T SLTH=F; 216 echo " CTR_FLEX_COUNT_10"; 217 tr 50 M=CTR_FLEX_COUNT_10; 218 tr 51 M=CTR_FLEX_COUNT_10; 219 tr 52 M=CTR_FLEX_COUNT_10; 220 tr 71 M=CTR_FLEX_COUNT_10 TSE=F SLTH=T; 221 tr 71 M=CTR_FLEX_COUNT_10 TSE=T SLTH=T; 222 tr 71 M=CTR_FLEX_COUNT_10 TSE=T SLTH=F; 223 echo " CTR_FLEX_COUNT_11"; 224 tr 50 M=CTR_FLEX_COUNT_11; 225 tr 51 M=CTR_FLEX_COUNT_11; 226 tr 52 M=CTR_FLEX_COUNT_11; 227 tr 71 M=CTR_FLEX_COUNT_11 TSE=F SLTH=T; 228 tr 71 M=CTR_FLEX_COUNT_11 TSE=T SLTH=T; 229 tr 71 M=CTR_FLEX_COUNT_11 TSE=T SLTH=F; 230 echo " CTR_FLEX_COUNT_2"; 231 tr 50 M=CTR_FLEX_COUNT_2; 232 tr 51 M=CTR_FLEX_COUNT_2; 233 tr 52 M=CTR_FLEX_COUNT_2; 234 tr 71 M=CTR_FLEX_COUNT_2 TSE=F SLTH=T; 235 tr 71 M=CTR_FLEX_COUNT_2 TSE=T SLTH=T; 236 tr 71 M=CTR_FLEX_COUNT_2 TSE=T SLTH=F; 237 echo " CTR_FLEX_COUNT_3"; 238 tr 50 M=CTR_FLEX_COUNT_3; 239 tr 51 M=CTR_FLEX_COUNT_3; 240 tr 52 M=CTR_FLEX_COUNT_3; 241 tr 71 M=CTR_FLEX_COUNT_3 TSE=F SLTH=T; 242 tr 71 M=CTR_FLEX_COUNT_3 TSE=T SLTH=T; 243 tr 71 M=CTR_FLEX_COUNT_3 TSE=T SLTH=F; 244 echo " CTR_FLEX_COUNT_4"; 245 tr 50 M=CTR_FLEX_COUNT_4; 246 tr 51 M=CTR_FLEX_COUNT_4; 247 tr 52 M=CTR_FLEX_COUNT_4; 248 tr 71 M=CTR_FLEX_COUNT_4 TSE=F SLTH=T; 249 tr 71 M=CTR_FLEX_COUNT_4 TSE=T SLTH=T; 250 tr 71 M=CTR_FLEX_COUNT_4 TSE=T SLTH=F; 251 echo " CTR_FLEX_COUNT_5"; 252 tr 50 M=CTR_FLEX_COUNT_5; 253 tr 51 M=CTR_FLEX_COUNT_5; 254 tr 52 M=CTR_FLEX_COUNT_5; 255 tr 71 M=CTR_FLEX_COUNT_5 TSE=F SLTH=T; 256 tr 71 M=CTR_FLEX_COUNT_5 TSE=T SLTH=T; 257 tr 71 M=CTR_FLEX_COUNT_5 TSE=T SLTH=F; 258 echo " CTR_FLEX_COUNT_6"; 259 tr 50 M=CTR_FLEX_COUNT_6; 260 tr 51 M=CTR_FLEX_COUNT_6; 261 tr 52 M=CTR_FLEX_COUNT_6; 262 tr 71 M=CTR_FLEX_COUNT_6 TSE=F SLTH=T; 263 tr 71 M=CTR_FLEX_COUNT_6 TSE=T SLTH=T; 264 tr 71 M=CTR_FLEX_COUNT_6 TSE=T SLTH=F; 265 echo " CTR_FLEX_COUNT_7"; 266 tr 50 M=CTR_FLEX_COUNT_7; 267 tr 51 M=CTR_FLEX_COUNT_7; 268 tr 52 M=CTR_FLEX_COUNT_7; 269 tr 71 M=CTR_FLEX_COUNT_7 TSE=F SLTH=T; 270 tr 71 M=CTR_FLEX_COUNT_7 TSE=T SLTH=T; 271 tr 71 M=CTR_FLEX_COUNT_7 TSE=T SLTH=F; 272 echo " CTR_FLEX_COUNT_8"; 273 tr 50 M=CTR_FLEX_COUNT_8; 274 tr 51 M=CTR_FLEX_COUNT_8; 275 tr 52 M=CTR_FLEX_COUNT_8; 276 tr 71 M=CTR_FLEX_COUNT_8 TSE=F SLTH=T; 277 tr 71 M=CTR_FLEX_COUNT_8 TSE=T SLTH=T; 278 tr 71 M=CTR_FLEX_COUNT_8 TSE=T SLTH=F; 279 echo " CTR_FLEX_COUNT_9"; 280 tr 50 M=CTR_FLEX_COUNT_9; 281 tr 51 M=CTR_FLEX_COUNT_9; 282 tr 52 M=CTR_FLEX_COUNT_9; 283 tr 71 M=CTR_FLEX_COUNT_9 TSE=F SLTH=T; 284 tr 71 M=CTR_FLEX_COUNT_9 TSE=T SLTH=T; 285 tr 71 M=CTR_FLEX_COUNT_9 TSE=T SLTH=F; 286 echo " DEVICE_STREAM_ID_TO_PP_PORT_MAP"; 287 tr 50 M=DEVICE_STREAM_ID_TO_PP_PORT_MAP; 288 tr 51 M=DEVICE_STREAM_ID_TO_PP_PORT_MAP; 289 tr 52 M=DEVICE_STREAM_ID_TO_PP_PORT_MAP; 290 tr 71 M=DEVICE_STREAM_ID_TO_PP_PORT_MAP TSE=F SLTH=T; 291 tr 71 M=DEVICE_STREAM_ID_TO_PP_PORT_MAP TSE=T SLTH=T; 292 tr 71 M=DEVICE_STREAM_ID_TO_PP_PORT_MAP TSE=T SLTH=F; 293 echo " DSCP_TABLE"; 294 tr 50 M=DSCP_TABLE; 295 tr 51 M=DSCP_TABLE; 296 tr 52 M=DSCP_TABLE; 297 tr 71 M=DSCP_TABLE TSE=F SLTH=T; 298 tr 71 M=DSCP_TABLE TSE=T SLTH=T; 299 tr 71 M=DSCP_TABLE TSE=T SLTH=F; 300 echo " E2E_HOL_STATUS"; 301 tr 50 M=E2E_HOL_STATUS; 302 tr 51 M=E2E_HOL_STATUS; 303 tr 52 M=E2E_HOL_STATUS; 304 tr 71 M=E2E_HOL_STATUS TSE=F SLTH=T; 305 tr 71 M=E2E_HOL_STATUS TSE=T SLTH=T; 306 tr 71 M=E2E_HOL_STATUS TSE=T SLTH=F; 307 echo " E2E_HOL_STATUS_1"; 308 tr 50 M=E2E_HOL_STATUS_1; 309 tr 51 M=E2E_HOL_STATUS_1; 310 tr 52 M=E2E_HOL_STATUS_1; 311 tr 71 M=E2E_HOL_STATUS_1 TSE=F SLTH=T; 312 tr 71 M=E2E_HOL_STATUS_1 TSE=T SLTH=T; 313 tr 71 M=E2E_HOL_STATUS_1 TSE=T SLTH=F; 314 echo " EFP_COUNTER_TABLE"; 315 tr 50 M=EFP_COUNTER_TABLE; 316 tr 51 M=EFP_COUNTER_TABLE; 317 tr 52 M=EFP_COUNTER_TABLE; 318 tr 71 M=EFP_COUNTER_TABLE TSE=F SLTH=T; 319 tr 71 M=EFP_COUNTER_TABLE TSE=T SLTH=T; 320 tr 71 M=EFP_COUNTER_TABLE TSE=T SLTH=F; 321 echo " EFP_METER_TABLE"; 322 tr 50 M=EFP_METER_TABLE; 323 tr 51 M=EFP_METER_TABLE; 324 tr 52 M=EFP_METER_TABLE; 325 tr 71 M=EFP_METER_TABLE TSE=F SLTH=T; 326 tr 71 M=EFP_METER_TABLE TSE=T SLTH=T; 327 tr 71 M=EFP_METER_TABLE TSE=T SLTH=F; 328 echo " EFP_POLICY_TABLE"; 329 tr 50 M=EFP_POLICY_TABLE; 330 tr 51 M=EFP_POLICY_TABLE; 331 tr 52 M=EFP_POLICY_TABLE; 332 tr 71 M=EFP_POLICY_TABLE TSE=F SLTH=T; 333 tr 71 M=EFP_POLICY_TABLE TSE=T SLTH=T; 334 tr 71 M=EFP_POLICY_TABLE TSE=T SLTH=F; 335 echo " EFP_TCAM"; 336 tr 50 M=EFP_TCAM; 337 tr 51 M=EFP_TCAM; 338 tr 52 M=EFP_TCAM; 339 tr 71 M=EFP_TCAM TSE=F SLTH=T; 340 tr 71 M=EFP_TCAM TSE=T SLTH=T; 341 tr 71 M=EFP_TCAM TSE=T SLTH=F; 342 echo " EGR_1588_SA"; 343 tr 50 M=EGR_1588_SA; 344 tr 51 M=EGR_1588_SA; 345 tr 52 M=EGR_1588_SA; 346 tr 71 M=EGR_1588_SA TSE=F SLTH=T; 347 tr 71 M=EGR_1588_SA TSE=T SLTH=T; 348 tr 71 M=EGR_1588_SA TSE=T SLTH=F; 349 echo " EGR_COS_MAP"; 350 tr 50 M=EGR_COS_MAP; 351 tr 51 M=EGR_COS_MAP; 352 tr 52 M=EGR_COS_MAP; 353 tr 71 M=EGR_COS_MAP TSE=F SLTH=T; 354 tr 71 M=EGR_COS_MAP TSE=T SLTH=T; 355 tr 71 M=EGR_COS_MAP TSE=T SLTH=F; 356 echo " EGR_CPU_COS_MAP"; 357 tr 50 M=EGR_CPU_COS_MAP; 358 tr 51 M=EGR_CPU_COS_MAP; 359 tr 52 M=EGR_CPU_COS_MAP; 360 tr 71 M=EGR_CPU_COS_MAP TSE=F SLTH=T; 361 tr 71 M=EGR_CPU_COS_MAP TSE=T SLTH=T; 362 tr 71 M=EGR_CPU_COS_MAP TSE=T SLTH=F; 363 echo " EGR_DSCP_ECN_MAP"; 364 tr 50 M=EGR_DSCP_ECN_MAP; 365 tr 51 M=EGR_DSCP_ECN_MAP; 366 tr 52 M=EGR_DSCP_ECN_MAP; 367 tr 71 M=EGR_DSCP_ECN_MAP TSE=F SLTH=T; 368 tr 71 M=EGR_DSCP_ECN_MAP TSE=T SLTH=T; 369 tr 71 M=EGR_DSCP_ECN_MAP TSE=T SLTH=F; 370 echo " EGR_DSCP_TABLE"; 371 tr 50 M=EGR_DSCP_TABLE; 372 tr 51 M=EGR_DSCP_TABLE; 373 tr 52 M=EGR_DSCP_TABLE; 374 tr 71 M=EGR_DSCP_TABLE TSE=F SLTH=T; 375 tr 71 M=EGR_DSCP_TABLE TSE=T SLTH=T; 376 tr 71 M=EGR_DSCP_TABLE TSE=T SLTH=F; 377 echo " EGR_DVP_ATTRIBUTE"; 378 tr 50 M=EGR_DVP_ATTRIBUTE; 379 tr 51 M=EGR_DVP_ATTRIBUTE; 380 tr 52 M=EGR_DVP_ATTRIBUTE; 381 tr 71 M=EGR_DVP_ATTRIBUTE TSE=F SLTH=T; 382 tr 71 M=EGR_DVP_ATTRIBUTE TSE=T SLTH=T; 383 tr 71 M=EGR_DVP_ATTRIBUTE TSE=T SLTH=F; 384 echo " EGR_EM_MTP_INDEX"; 385 tr 50 M=EGR_EM_MTP_INDEX; 386 tr 51 M=EGR_EM_MTP_INDEX; 387 tr 52 M=EGR_EM_MTP_INDEX; 388 tr 71 M=EGR_EM_MTP_INDEX TSE=F SLTH=T; 389 tr 71 M=EGR_EM_MTP_INDEX TSE=T SLTH=T; 390 tr 71 M=EGR_EM_MTP_INDEX TSE=T SLTH=F; 391 echo " EGR_ENABLE"; 392 tr 50 M=EGR_ENABLE; 393 tr 51 M=EGR_ENABLE; 394 tr 52 M=EGR_ENABLE; 395 tr 71 M=EGR_ENABLE TSE=F SLTH=T; 396 tr 71 M=EGR_ENABLE TSE=T SLTH=T; 397 tr 71 M=EGR_ENABLE TSE=T SLTH=F; 398 echo " EGR_EP_REDIRECT_EM_MTP_INDEX"; 399 tr 50 M=EGR_EP_REDIRECT_EM_MTP_INDEX; 400 tr 51 M=EGR_EP_REDIRECT_EM_MTP_INDEX; 401 tr 52 M=EGR_EP_REDIRECT_EM_MTP_INDEX; 402 tr 71 M=EGR_EP_REDIRECT_EM_MTP_INDEX TSE=F SLTH=T; 403 tr 71 M=EGR_EP_REDIRECT_EM_MTP_INDEX TSE=T SLTH=T; 404 tr 71 M=EGR_EP_REDIRECT_EM_MTP_INDEX TSE=T SLTH=F; 405 echo " EGR_FLEX_CTR_COUNTER_TABLE_0"; 406 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_0; 407 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_0; 408 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_0; 409 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_0 TSE=F SLTH=T; 410 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_0 TSE=T SLTH=T; 411 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_0 TSE=T SLTH=F; 412 echo " EGR_FLEX_CTR_COUNTER_TABLE_1"; 413 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_1; 414 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_1; 415 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_1; 416 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_1 TSE=F SLTH=T; 417 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_1 TSE=T SLTH=T; 418 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_1 TSE=T SLTH=F; 419 echo " EGR_FLEX_CTR_COUNTER_TABLE_2"; 420 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_2; 421 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_2; 422 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_2; 423 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_2 TSE=F SLTH=T; 424 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_2 TSE=T SLTH=T; 425 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_2 TSE=T SLTH=F; 426 echo " EGR_FLEX_CTR_COUNTER_TABLE_3"; 427 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_3; 428 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_3; 429 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_3; 430 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_3 TSE=F SLTH=T; 431 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_3 TSE=T SLTH=T; 432 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_3 TSE=T SLTH=F; 433 echo " EGR_FLEX_CTR_COUNTER_TABLE_4"; 434 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_4; 435 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_4; 436 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_4; 437 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_4 TSE=F SLTH=T; 438 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_4 TSE=T SLTH=T; 439 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_4 TSE=T SLTH=F; 440 echo " EGR_FLEX_CTR_COUNTER_TABLE_5"; 441 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_5; 442 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_5; 443 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_5; 444 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_5 TSE=F SLTH=T; 445 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_5 TSE=T SLTH=T; 446 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_5 TSE=T SLTH=F; 447 echo " EGR_FLEX_CTR_COUNTER_TABLE_6"; 448 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_6; 449 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_6; 450 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_6; 451 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_6 TSE=F SLTH=T; 452 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_6 TSE=T SLTH=T; 453 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_6 TSE=T SLTH=F; 454 echo " EGR_FLEX_CTR_COUNTER_TABLE_7"; 455 tr 50 M=EGR_FLEX_CTR_COUNTER_TABLE_7; 456 tr 51 M=EGR_FLEX_CTR_COUNTER_TABLE_7; 457 tr 52 M=EGR_FLEX_CTR_COUNTER_TABLE_7; 458 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_7 TSE=F SLTH=T; 459 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_7 TSE=T SLTH=T; 460 tr 71 M=EGR_FLEX_CTR_COUNTER_TABLE_7 TSE=T SLTH=F; 461 echo " EGR_FLEX_CTR_OFFSET_TABLE_0"; 462 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_0; 463 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_0; 464 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_0; 465 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_0 TSE=F SLTH=T; 466 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_0 TSE=T SLTH=T; 467 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_0 TSE=T SLTH=F; 468 echo " EGR_FLEX_CTR_OFFSET_TABLE_1"; 469 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_1; 470 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_1; 471 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_1; 472 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_1 TSE=F SLTH=T; 473 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_1 TSE=T SLTH=T; 474 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_1 TSE=T SLTH=F; 475 echo " EGR_FLEX_CTR_OFFSET_TABLE_2"; 476 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_2; 477 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_2; 478 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_2; 479 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_2 TSE=F SLTH=T; 480 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_2 TSE=T SLTH=T; 481 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_2 TSE=T SLTH=F; 482 echo " EGR_FLEX_CTR_OFFSET_TABLE_3"; 483 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_3; 484 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_3; 485 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_3; 486 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_3 TSE=F SLTH=T; 487 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_3 TSE=T SLTH=T; 488 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_3 TSE=T SLTH=F; 489 echo " EGR_FLEX_CTR_OFFSET_TABLE_4"; 490 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_4; 491 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_4; 492 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_4; 493 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_4 TSE=F SLTH=T; 494 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_4 TSE=T SLTH=T; 495 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_4 TSE=T SLTH=F; 496 echo " EGR_FLEX_CTR_OFFSET_TABLE_5"; 497 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_5; 498 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_5; 499 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_5; 500 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_5 TSE=F SLTH=T; 501 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_5 TSE=T SLTH=T; 502 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_5 TSE=T SLTH=F; 503 echo " EGR_FLEX_CTR_OFFSET_TABLE_6"; 504 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_6; 505 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_6; 506 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_6; 507 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_6 TSE=F SLTH=T; 508 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_6 TSE=T SLTH=T; 509 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_6 TSE=T SLTH=F; 510 echo " EGR_FLEX_CTR_OFFSET_TABLE_7"; 511 tr 50 M=EGR_FLEX_CTR_OFFSET_TABLE_7; 512 tr 51 M=EGR_FLEX_CTR_OFFSET_TABLE_7; 513 tr 52 M=EGR_FLEX_CTR_OFFSET_TABLE_7; 514 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_7 TSE=F SLTH=T; 515 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_7 TSE=T SLTH=T; 516 tr 71 M=EGR_FLEX_CTR_OFFSET_TABLE_7 TSE=T SLTH=F; 517 echo " EGR_FLEX_CTR_PKT_PRI_MAP"; 518 tr 50 M=EGR_FLEX_CTR_PKT_PRI_MAP; 519 tr 51 M=EGR_FLEX_CTR_PKT_PRI_MAP; 520 tr 52 M=EGR_FLEX_CTR_PKT_PRI_MAP; 521 tr 71 M=EGR_FLEX_CTR_PKT_PRI_MAP TSE=F SLTH=T; 522 tr 71 M=EGR_FLEX_CTR_PKT_PRI_MAP TSE=T SLTH=T; 523 tr 71 M=EGR_FLEX_CTR_PKT_PRI_MAP TSE=T SLTH=F; 524 echo " EGR_FLEX_CTR_PKT_RES_MAP"; 525 tr 50 M=EGR_FLEX_CTR_PKT_RES_MAP; 526 tr 51 M=EGR_FLEX_CTR_PKT_RES_MAP; 527 tr 52 M=EGR_FLEX_CTR_PKT_RES_MAP; 528 tr 71 M=EGR_FLEX_CTR_PKT_RES_MAP TSE=F SLTH=T; 529 tr 71 M=EGR_FLEX_CTR_PKT_RES_MAP TSE=T SLTH=T; 530 tr 71 M=EGR_FLEX_CTR_PKT_RES_MAP TSE=T SLTH=F; 531 echo " EGR_FLEX_CTR_PORT_MAP"; 532 tr 50 M=EGR_FLEX_CTR_PORT_MAP; 533 tr 51 M=EGR_FLEX_CTR_PORT_MAP; 534 tr 52 M=EGR_FLEX_CTR_PORT_MAP; 535 tr 71 M=EGR_FLEX_CTR_PORT_MAP TSE=F SLTH=T; 536 tr 71 M=EGR_FLEX_CTR_PORT_MAP TSE=T SLTH=T; 537 tr 71 M=EGR_FLEX_CTR_PORT_MAP TSE=T SLTH=F; 538 echo " EGR_FLEX_CTR_PRI_CNG_MAP"; 539 tr 50 M=EGR_FLEX_CTR_PRI_CNG_MAP; 540 tr 51 M=EGR_FLEX_CTR_PRI_CNG_MAP; 541 tr 52 M=EGR_FLEX_CTR_PRI_CNG_MAP; 542 tr 71 M=EGR_FLEX_CTR_PRI_CNG_MAP TSE=F SLTH=T; 543 tr 71 M=EGR_FLEX_CTR_PRI_CNG_MAP TSE=T SLTH=T; 544 tr 71 M=EGR_FLEX_CTR_PRI_CNG_MAP TSE=T SLTH=F; 545 echo " EGR_FLEX_CTR_TOS_MAP"; 546 tr 50 M=EGR_FLEX_CTR_TOS_MAP; 547 tr 51 M=EGR_FLEX_CTR_TOS_MAP; 548 tr 52 M=EGR_FLEX_CTR_TOS_MAP; 549 tr 71 M=EGR_FLEX_CTR_TOS_MAP TSE=F SLTH=T; 550 tr 71 M=EGR_FLEX_CTR_TOS_MAP TSE=T SLTH=T; 551 tr 71 M=EGR_FLEX_CTR_TOS_MAP TSE=T SLTH=F; 552 echo " EGR_FRAGMENT_ID_TABLE"; 553 tr 50 M=EGR_FRAGMENT_ID_TABLE; 554 tr 51 M=EGR_FRAGMENT_ID_TABLE; 555 tr 52 M=EGR_FRAGMENT_ID_TABLE; 556 tr 71 M=EGR_FRAGMENT_ID_TABLE TSE=F SLTH=T; 557 tr 71 M=EGR_FRAGMENT_ID_TABLE TSE=T SLTH=T; 558 tr 71 M=EGR_FRAGMENT_ID_TABLE TSE=T SLTH=F; 559 echo " EGR_GPP_ATTRIBUTES"; 560 tr 50 M=EGR_GPP_ATTRIBUTES; 561 tr 51 M=EGR_GPP_ATTRIBUTES; 562 tr 52 M=EGR_GPP_ATTRIBUTES; 563 tr 71 M=EGR_GPP_ATTRIBUTES TSE=F SLTH=T; 564 tr 71 M=EGR_GPP_ATTRIBUTES TSE=T SLTH=T; 565 tr 71 M=EGR_GPP_ATTRIBUTES TSE=T SLTH=F; 566 echo " EGR_GPP_ATTRIBUTES_MODBASE"; 567 tr 50 M=EGR_GPP_ATTRIBUTES_MODBASE; 568 tr 51 M=EGR_GPP_ATTRIBUTES_MODBASE; 569 tr 52 M=EGR_GPP_ATTRIBUTES_MODBASE; 570 tr 71 M=EGR_GPP_ATTRIBUTES_MODBASE TSE=F SLTH=T; 571 tr 71 M=EGR_GPP_ATTRIBUTES_MODBASE TSE=T SLTH=T; 572 tr 71 M=EGR_GPP_ATTRIBUTES_MODBASE TSE=T SLTH=F; 573 echo " EGR_IM_MTP_INDEX"; 574 tr 50 M=EGR_IM_MTP_INDEX; 575 tr 51 M=EGR_IM_MTP_INDEX; 576 tr 52 M=EGR_IM_MTP_INDEX; 577 tr 71 M=EGR_IM_MTP_INDEX TSE=F SLTH=T; 578 tr 71 M=EGR_IM_MTP_INDEX TSE=T SLTH=T; 579 tr 71 M=EGR_IM_MTP_INDEX TSE=T SLTH=F; 580 echo " EGR_IPMC"; 581 tr 50 M=EGR_IPMC; 582 tr 51 M=EGR_IPMC; 583 tr 52 M=EGR_IPMC; 584 tr 71 M=EGR_IPMC TSE=F SLTH=T; 585 tr 71 M=EGR_IPMC TSE=T SLTH=T; 586 tr 71 M=EGR_IPMC TSE=T SLTH=F; 587 echo " EGR_IP_TUNNEL"; 588 tr 50 M=EGR_IP_TUNNEL; 589 tr 51 M=EGR_IP_TUNNEL; 590 tr 52 M=EGR_IP_TUNNEL; 591 tr 71 M=EGR_IP_TUNNEL TSE=F SLTH=T; 592 tr 71 M=EGR_IP_TUNNEL TSE=T SLTH=T; 593 tr 71 M=EGR_IP_TUNNEL TSE=T SLTH=F; 594 echo " EGR_IP_TUNNEL_IPV6"; 595 tr 50 M=EGR_IP_TUNNEL_IPV6; 596 tr 51 M=EGR_IP_TUNNEL_IPV6; 597 tr 52 M=EGR_IP_TUNNEL_IPV6; 598 tr 71 M=EGR_IP_TUNNEL_IPV6 TSE=F SLTH=T; 599 tr 71 M=EGR_IP_TUNNEL_IPV6 TSE=T SLTH=T; 600 tr 71 M=EGR_IP_TUNNEL_IPV6 TSE=T SLTH=F; 601 echo " EGR_IP_TUNNEL_MPLS"; 602 tr 50 M=EGR_IP_TUNNEL_MPLS; 603 tr 51 M=EGR_IP_TUNNEL_MPLS; 604 tr 52 M=EGR_IP_TUNNEL_MPLS; 605 tr 71 M=EGR_IP_TUNNEL_MPLS TSE=F SLTH=T; 606 tr 71 M=EGR_IP_TUNNEL_MPLS TSE=T SLTH=T; 607 tr 71 M=EGR_IP_TUNNEL_MPLS TSE=T SLTH=F; 608 echo " EGR_L3_INTF"; 609 tr 50 M=EGR_L3_INTF; 610 tr 51 M=EGR_L3_INTF; 611 tr 52 M=EGR_L3_INTF; 612 tr 71 M=EGR_L3_INTF TSE=F SLTH=T; 613 tr 71 M=EGR_L3_INTF TSE=T SLTH=T; 614 tr 71 M=EGR_L3_INTF TSE=T SLTH=F; 615 echo " EGR_L3_NEXT_HOP"; 616 tr 50 M=EGR_L3_NEXT_HOP; 617 tr 51 M=EGR_L3_NEXT_HOP; 618 tr 52 M=EGR_L3_NEXT_HOP; 619 tr 71 M=EGR_L3_NEXT_HOP TSE=F SLTH=T; 620 tr 71 M=EGR_L3_NEXT_HOP TSE=T SLTH=T; 621 tr 71 M=EGR_L3_NEXT_HOP TSE=T SLTH=F; 622 echo " EGR_LM_COUNTER_CONTROL"; 623 tr 50 M=EGR_LM_COUNTER_CONTROL; 624 tr 51 M=EGR_LM_COUNTER_CONTROL; 625 tr 52 M=EGR_LM_COUNTER_CONTROL; 626 tr 71 M=EGR_LM_COUNTER_CONTROL TSE=F SLTH=T; 627 tr 71 M=EGR_LM_COUNTER_CONTROL TSE=T SLTH=T; 628 tr 71 M=EGR_LM_COUNTER_CONTROL TSE=T SLTH=F; 629 echo " EGR_MAC_DA_PROFILE"; 630 tr 50 M=EGR_MAC_DA_PROFILE; 631 tr 51 M=EGR_MAC_DA_PROFILE; 632 tr 52 M=EGR_MAC_DA_PROFILE; 633 tr 71 M=EGR_MAC_DA_PROFILE TSE=F SLTH=T; 634 tr 71 M=EGR_MAC_DA_PROFILE TSE=T SLTH=T; 635 tr 71 M=EGR_MAC_DA_PROFILE TSE=T SLTH=F; 636 echo " EGR_MAP_MH"; 637 tr 50 M=EGR_MAP_MH; 638 tr 51 M=EGR_MAP_MH; 639 tr 52 M=EGR_MAP_MH; 640 tr 71 M=EGR_MAP_MH TSE=F SLTH=T; 641 tr 71 M=EGR_MAP_MH TSE=T SLTH=T; 642 tr 71 M=EGR_MAP_MH TSE=T SLTH=F; 643 echo " EGR_MASK"; 644 tr 50 M=EGR_MASK; 645 tr 51 M=EGR_MASK; 646 tr 52 M=EGR_MASK; 647 tr 71 M=EGR_MASK TSE=F SLTH=T; 648 tr 71 M=EGR_MASK TSE=T SLTH=T; 649 tr 71 M=EGR_MASK TSE=T SLTH=F; 650 echo " EGR_MASK_MODBASE"; 651 tr 50 M=EGR_MASK_MODBASE; 652 tr 51 M=EGR_MASK_MODBASE; 653 tr 52 M=EGR_MASK_MODBASE; 654 tr 71 M=EGR_MASK_MODBASE TSE=F SLTH=T; 655 tr 71 M=EGR_MASK_MODBASE TSE=T SLTH=T; 656 tr 71 M=EGR_MASK_MODBASE TSE=T SLTH=F; 657 #echo " EGR_MAX_USED_ENTRIES"; 658 #tr 50 M=EGR_MAX_USED_ENTRIES; 659 #tr 51 M=EGR_MAX_USED_ENTRIES; 660 #tr 52 M=EGR_MAX_USED_ENTRIES; 661 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=F SLTH=T; 662 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=T SLTH=T; 663 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=T SLTH=F; 664 echo " EGR_MA_INDEX"; 665 tr 50 M=EGR_MA_INDEX; 666 tr 51 M=EGR_MA_INDEX; 667 tr 52 M=EGR_MA_INDEX; 668 tr 71 M=EGR_MA_INDEX TSE=F SLTH=T; 669 tr 71 M=EGR_MA_INDEX TSE=T SLTH=T; 670 tr 71 M=EGR_MA_INDEX TSE=T SLTH=F; 671 echo " EGR_MIRROR_ENCAP_CONTROL"; 672 tr 50 M=EGR_MIRROR_ENCAP_CONTROL; 673 tr 51 M=EGR_MIRROR_ENCAP_CONTROL; 674 tr 52 M=EGR_MIRROR_ENCAP_CONTROL; 675 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=F SLTH=T; 676 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=T SLTH=T; 677 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=T SLTH=F; 678 echo " EGR_MIRROR_ENCAP_DATA_1"; 679 tr 50 M=EGR_MIRROR_ENCAP_DATA_1; 680 tr 51 M=EGR_MIRROR_ENCAP_DATA_1; 681 tr 52 M=EGR_MIRROR_ENCAP_DATA_1; 682 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=F SLTH=T; 683 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=T SLTH=T; 684 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=T SLTH=F; 685 echo " EGR_MIRROR_ENCAP_DATA_2"; 686 tr 50 M=EGR_MIRROR_ENCAP_DATA_2; 687 tr 51 M=EGR_MIRROR_ENCAP_DATA_2; 688 tr 52 M=EGR_MIRROR_ENCAP_DATA_2; 689 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=F SLTH=T; 690 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=T SLTH=T; 691 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=T SLTH=F; 692 #echo " EGR_MMU_REQUESTS"; 693 #tr 50 M=EGR_MMU_REQUESTS; 694 #tr 51 M=EGR_MMU_REQUESTS; 695 #tr 52 M=EGR_MMU_REQUESTS; 696 #tr 71 M=EGR_MMU_REQUESTS TSE=F SLTH=T; 697 #tr 71 M=EGR_MMU_REQUESTS TSE=T SLTH=T; 698 #tr 71 M=EGR_MMU_REQUESTS TSE=T SLTH=F; 699 echo " EGR_MOD_MAP_TABLE"; 700 tr 50 M=EGR_MOD_MAP_TABLE; 701 tr 51 M=EGR_MOD_MAP_TABLE; 702 tr 52 M=EGR_MOD_MAP_TABLE; 703 tr 71 M=EGR_MOD_MAP_TABLE TSE=F SLTH=T; 704 tr 71 M=EGR_MOD_MAP_TABLE TSE=T SLTH=T; 705 tr 71 M=EGR_MOD_MAP_TABLE TSE=T SLTH=F; 706 echo " EGR_MPLS_EXP_MAPPING_1"; 707 tr 50 M=EGR_MPLS_EXP_MAPPING_1; 708 tr 51 M=EGR_MPLS_EXP_MAPPING_1; 709 tr 52 M=EGR_MPLS_EXP_MAPPING_1; 710 tr 71 M=EGR_MPLS_EXP_MAPPING_1 TSE=F SLTH=T; 711 tr 71 M=EGR_MPLS_EXP_MAPPING_1 TSE=T SLTH=T; 712 tr 71 M=EGR_MPLS_EXP_MAPPING_1 TSE=T SLTH=F; 713 echo " EGR_MPLS_EXP_MAPPING_2"; 714 tr 50 M=EGR_MPLS_EXP_MAPPING_2; 715 tr 51 M=EGR_MPLS_EXP_MAPPING_2; 716 tr 52 M=EGR_MPLS_EXP_MAPPING_2; 717 tr 71 M=EGR_MPLS_EXP_MAPPING_2 TSE=F SLTH=T; 718 tr 71 M=EGR_MPLS_EXP_MAPPING_2 TSE=T SLTH=T; 719 tr 71 M=EGR_MPLS_EXP_MAPPING_2 TSE=T SLTH=F; 720 echo " EGR_MPLS_EXP_PRI_MAPPING"; 721 tr 50 M=EGR_MPLS_EXP_PRI_MAPPING; 722 tr 51 M=EGR_MPLS_EXP_PRI_MAPPING; 723 tr 52 M=EGR_MPLS_EXP_PRI_MAPPING; 724 tr 71 M=EGR_MPLS_EXP_PRI_MAPPING TSE=F SLTH=T; 725 tr 71 M=EGR_MPLS_EXP_PRI_MAPPING TSE=T SLTH=T; 726 tr 71 M=EGR_MPLS_EXP_PRI_MAPPING TSE=T SLTH=F; 727 echo " EGR_MPLS_PRI_MAPPING"; 728 tr 50 M=EGR_MPLS_PRI_MAPPING; 729 tr 51 M=EGR_MPLS_PRI_MAPPING; 730 tr 52 M=EGR_MPLS_PRI_MAPPING; 731 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=F SLTH=T; 732 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=T SLTH=T; 733 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=T SLTH=F; 734 echo " EGR_MPLS_VC_AND_SWAP_LABEL_TABLE"; 735 tr 50 M=EGR_MPLS_VC_AND_SWAP_LABEL_TABLE; 736 tr 51 M=EGR_MPLS_VC_AND_SWAP_LABEL_TABLE; 737 tr 52 M=EGR_MPLS_VC_AND_SWAP_LABEL_TABLE; 738 tr 71 M=EGR_MPLS_VC_AND_SWAP_LABEL_TABLE TSE=F SLTH=T; 739 tr 71 M=EGR_MPLS_VC_AND_SWAP_LABEL_TABLE TSE=T SLTH=T; 740 tr 71 M=EGR_MPLS_VC_AND_SWAP_LABEL_TABLE TSE=T SLTH=F; 741 echo " EGR_MP_GROUP"; 742 tr 50 M=EGR_MP_GROUP; 743 tr 51 M=EGR_MP_GROUP; 744 tr 52 M=EGR_MP_GROUP; 745 tr 71 M=EGR_MP_GROUP TSE=F SLTH=T; 746 tr 71 M=EGR_MP_GROUP TSE=T SLTH=T; 747 tr 71 M=EGR_MP_GROUP TSE=T SLTH=F; 748 echo " EGR_NETWORK_PRUNE_CONTROL"; 749 tr 50 M=EGR_NETWORK_PRUNE_CONTROL; 750 tr 51 M=EGR_NETWORK_PRUNE_CONTROL; 751 tr 52 M=EGR_NETWORK_PRUNE_CONTROL; 752 tr 71 M=EGR_NETWORK_PRUNE_CONTROL TSE=F SLTH=T; 753 tr 71 M=EGR_NETWORK_PRUNE_CONTROL TSE=T SLTH=T; 754 tr 71 M=EGR_NETWORK_PRUNE_CONTROL TSE=T SLTH=F; 755 echo " EGR_OAM_DGLP_PROFILE"; 756 tr 50 M=EGR_OAM_DGLP_PROFILE; 757 tr 51 M=EGR_OAM_DGLP_PROFILE; 758 tr 52 M=EGR_OAM_DGLP_PROFILE; 759 tr 71 M=EGR_OAM_DGLP_PROFILE TSE=F SLTH=T; 760 tr 71 M=EGR_OAM_DGLP_PROFILE TSE=T SLTH=T; 761 tr 71 M=EGR_OAM_DGLP_PROFILE TSE=T SLTH=F; 762 echo " EGR_OAM_FLEXIBLE_DOMAIN_CONTROL"; 763 tr 50 M=EGR_OAM_FLEXIBLE_DOMAIN_CONTROL; 764 tr 51 M=EGR_OAM_FLEXIBLE_DOMAIN_CONTROL; 765 tr 52 M=EGR_OAM_FLEXIBLE_DOMAIN_CONTROL; 766 tr 71 M=EGR_OAM_FLEXIBLE_DOMAIN_CONTROL TSE=F SLTH=T; 767 tr 71 M=EGR_OAM_FLEXIBLE_DOMAIN_CONTROL TSE=T SLTH=T; 768 tr 71 M=EGR_OAM_FLEXIBLE_DOMAIN_CONTROL TSE=T SLTH=F; 769 echo " EGR_OAM_LM_COUNTERS_0"; 770 tr 50 M=EGR_OAM_LM_COUNTERS_0; 771 tr 51 M=EGR_OAM_LM_COUNTERS_0; 772 tr 52 M=EGR_OAM_LM_COUNTERS_0; 773 tr 71 M=EGR_OAM_LM_COUNTERS_0 TSE=F SLTH=T; 774 tr 71 M=EGR_OAM_LM_COUNTERS_0 TSE=T SLTH=T; 775 tr 71 M=EGR_OAM_LM_COUNTERS_0 TSE=T SLTH=F; 776 echo " EGR_OAM_LM_COUNTERS_1"; 777 tr 50 M=EGR_OAM_LM_COUNTERS_1; 778 tr 51 M=EGR_OAM_LM_COUNTERS_1; 779 tr 52 M=EGR_OAM_LM_COUNTERS_1; 780 tr 71 M=EGR_OAM_LM_COUNTERS_1 TSE=F SLTH=T; 781 tr 71 M=EGR_OAM_LM_COUNTERS_1 TSE=T SLTH=T; 782 tr 71 M=EGR_OAM_LM_COUNTERS_1 TSE=T SLTH=F; 783 echo " EGR_OAM_OPCODE_CONTROL_PROFILE"; 784 tr 50 M=EGR_OAM_OPCODE_CONTROL_PROFILE; 785 tr 51 M=EGR_OAM_OPCODE_CONTROL_PROFILE; 786 tr 52 M=EGR_OAM_OPCODE_CONTROL_PROFILE; 787 tr 71 M=EGR_OAM_OPCODE_CONTROL_PROFILE TSE=F SLTH=T; 788 tr 71 M=EGR_OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=T; 789 tr 71 M=EGR_OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=F; 790 echo " EGR_OAM_OPCODE_GROUP"; 791 tr 50 M=EGR_OAM_OPCODE_GROUP; 792 tr 51 M=EGR_OAM_OPCODE_GROUP; 793 tr 52 M=EGR_OAM_OPCODE_GROUP; 794 tr 71 M=EGR_OAM_OPCODE_GROUP TSE=F SLTH=T; 795 tr 71 M=EGR_OAM_OPCODE_GROUP TSE=T SLTH=T; 796 tr 71 M=EGR_OAM_OPCODE_GROUP TSE=T SLTH=F; 797 echo " EGR_OLP_CONFIG"; 798 tr 50 M=EGR_OLP_CONFIG; 799 #tr 51 M=EGR_OLP_CONFIG; 800 #tr 52 M=EGR_OLP_CONFIG; 801 tr 71 M=EGR_OLP_CONFIG TSE=F SLTH=T; 802 tr 71 M=EGR_OLP_CONFIG TSE=T SLTH=T; 803 tr 71 M=EGR_OLP_CONFIG TSE=T SLTH=F; 804 echo " EGR_OLP_DGPP_CONFIG"; 805 tr 50 M=EGR_OLP_DGPP_CONFIG; 806 tr 51 M=EGR_OLP_DGPP_CONFIG; 807 tr 52 M=EGR_OLP_DGPP_CONFIG; 808 tr 71 M=EGR_OLP_DGPP_CONFIG TSE=F SLTH=T; 809 tr 71 M=EGR_OLP_DGPP_CONFIG TSE=T SLTH=T; 810 tr 71 M=EGR_OLP_DGPP_CONFIG TSE=T SLTH=F; 811 echo " EGR_OLP_HEADER_TYPE_MAPPING"; 812 tr 50 M=EGR_OLP_HEADER_TYPE_MAPPING; 813 tr 51 M=EGR_OLP_HEADER_TYPE_MAPPING; 814 tr 52 M=EGR_OLP_HEADER_TYPE_MAPPING; 815 tr 71 M=EGR_OLP_HEADER_TYPE_MAPPING TSE=F SLTH=T; 816 tr 71 M=EGR_OLP_HEADER_TYPE_MAPPING TSE=T SLTH=T; 817 tr 71 M=EGR_OLP_HEADER_TYPE_MAPPING TSE=T SLTH=F; 818 #echo " EGR_PBE_DEBUG_0"; 819 #tr 50 M=EGR_PBE_DEBUG_0; 820 #tr 51 M=EGR_PBE_DEBUG_0; 821 #tr 52 M=EGR_PBE_DEBUG_0; 822 #tr 71 M=EGR_PBE_DEBUG_0 TSE=F SLTH=T; 823 #tr 71 M=EGR_PBE_DEBUG_0 TSE=T SLTH=T; 824 #tr 71 M=EGR_PBE_DEBUG_0 TSE=T SLTH=F; 825 #echo " EGR_PBE_DEBUG_1"; 826 #tr 50 M=EGR_PBE_DEBUG_1; 827 #tr 51 M=EGR_PBE_DEBUG_1; 828 #tr 52 M=EGR_PBE_DEBUG_1; 829 #tr 71 M=EGR_PBE_DEBUG_1 TSE=F SLTH=T; 830 #tr 71 M=EGR_PBE_DEBUG_1 TSE=T SLTH=T; 831 #tr 71 M=EGR_PBE_DEBUG_1 TSE=T SLTH=F; 832 echo " EGR_PCP_DE_MAPPING"; 833 tr 50 M=EGR_PCP_DE_MAPPING; 834 tr 51 M=EGR_PCP_DE_MAPPING; 835 tr 52 M=EGR_PCP_DE_MAPPING; 836 tr 71 M=EGR_PCP_DE_MAPPING TSE=F SLTH=T; 837 tr 71 M=EGR_PCP_DE_MAPPING TSE=T SLTH=T; 838 tr 71 M=EGR_PCP_DE_MAPPING TSE=T SLTH=F; 839 echo " EGR_PHYSICAL_PORT"; 840 tr 50 M=EGR_PHYSICAL_PORT; 841 tr 51 M=EGR_PHYSICAL_PORT; 842 tr 52 M=EGR_PHYSICAL_PORT; 843 tr 71 M=EGR_PHYSICAL_PORT TSE=F SLTH=T; 844 tr 71 M=EGR_PHYSICAL_PORT TSE=T SLTH=T; 845 tr 71 M=EGR_PHYSICAL_PORT TSE=T SLTH=F; 846 echo " EGR_PORT"; 847 tr 50 M=EGR_PORT; 848 tr 51 M=EGR_PORT; 849 tr 52 M=EGR_PORT; 850 tr 71 M=EGR_PORT TSE=F SLTH=T; 851 tr 71 M=EGR_PORT TSE=T SLTH=T; 852 tr 71 M=EGR_PORT TSE=T SLTH=F; 853 #echo " EGR_PORT_REQUESTS"; 854 #tr 50 M=EGR_PORT_REQUESTS; 855 #tr 51 M=EGR_PORT_REQUESTS; 856 #tr 52 M=EGR_PORT_REQUESTS; 857 #tr 71 M=EGR_PORT_REQUESTS TSE=F SLTH=T; 858 #tr 71 M=EGR_PORT_REQUESTS TSE=T SLTH=T; 859 #tr 71 M=EGR_PORT_REQUESTS TSE=T SLTH=F; 860 echo " EGR_PP_PORT_GPP_TRANSLATION_1"; 861 tr 50 M=EGR_PP_PORT_GPP_TRANSLATION_1; 862 #tr 51 M=EGR_PP_PORT_GPP_TRANSLATION_1; 863 #tr 52 M=EGR_PP_PORT_GPP_TRANSLATION_1; 864 tr 71 M=EGR_PP_PORT_GPP_TRANSLATION_1 TSE=F SLTH=T; 865 tr 71 M=EGR_PP_PORT_GPP_TRANSLATION_1 TSE=T SLTH=T; 866 tr 71 M=EGR_PP_PORT_GPP_TRANSLATION_1 TSE=T SLTH=F; 867 echo " EGR_PP_PORT_GPP_TRANSLATION_2"; 868 tr 50 M=EGR_PP_PORT_GPP_TRANSLATION_2; 869 #tr 51 M=EGR_PP_PORT_GPP_TRANSLATION_2; 870 #tr 52 M=EGR_PP_PORT_GPP_TRANSLATION_2; 871 tr 71 M=EGR_PP_PORT_GPP_TRANSLATION_2 TSE=F SLTH=T; 872 tr 71 M=EGR_PP_PORT_GPP_TRANSLATION_2 TSE=T SLTH=T; 873 tr 71 M=EGR_PP_PORT_GPP_TRANSLATION_2 TSE=T SLTH=F; 874 echo " EGR_PRI_CNG_MAP"; 875 tr 50 M=EGR_PRI_CNG_MAP; 876 tr 51 M=EGR_PRI_CNG_MAP; 877 tr 52 M=EGR_PRI_CNG_MAP; 878 tr 71 M=EGR_PRI_CNG_MAP TSE=F SLTH=T; 879 tr 71 M=EGR_PRI_CNG_MAP TSE=T SLTH=T; 880 tr 71 M=EGR_PRI_CNG_MAP TSE=T SLTH=F; 881 echo " EGR_PW_INIT_COUNTERS"; 882 tr 50 M=EGR_PW_INIT_COUNTERS; 883 tr 51 M=EGR_PW_INIT_COUNTERS; 884 tr 52 M=EGR_PW_INIT_COUNTERS; 885 tr 71 M=EGR_PW_INIT_COUNTERS TSE=F SLTH=T; 886 tr 71 M=EGR_PW_INIT_COUNTERS TSE=T SLTH=T; 887 tr 71 M=EGR_PW_INIT_COUNTERS TSE=T SLTH=F; 888 echo " EGR_QUEUE_TO_PP_PORT_MAP"; 889 tr 50 M=EGR_QUEUE_TO_PP_PORT_MAP; 890 tr 51 M=EGR_QUEUE_TO_PP_PORT_MAP; 891 tr 52 M=EGR_QUEUE_TO_PP_PORT_MAP; 892 tr 71 M=EGR_QUEUE_TO_PP_PORT_MAP TSE=F SLTH=T; 893 tr 71 M=EGR_QUEUE_TO_PP_PORT_MAP TSE=T SLTH=T; 894 tr 71 M=EGR_QUEUE_TO_PP_PORT_MAP TSE=T SLTH=F; 895 echo " EGR_SERVICE_PRI_MAP"; 896 tr 50 M=EGR_SERVICE_PRI_MAP; 897 tr 51 M=EGR_SERVICE_PRI_MAP; 898 tr 52 M=EGR_SERVICE_PRI_MAP; 899 tr 71 M=EGR_SERVICE_PRI_MAP TSE=F SLTH=T; 900 tr 71 M=EGR_SERVICE_PRI_MAP TSE=T SLTH=T; 901 tr 71 M=EGR_SERVICE_PRI_MAP TSE=T SLTH=F; 902 echo " EGR_SUBPORT_TAG_DOT1P_MAP"; 903 tr 50 M=EGR_SUBPORT_TAG_DOT1P_MAP; 904 tr 51 M=EGR_SUBPORT_TAG_DOT1P_MAP; 905 tr 52 M=EGR_SUBPORT_TAG_DOT1P_MAP; 906 tr 71 M=EGR_SUBPORT_TAG_DOT1P_MAP TSE=F SLTH=T; 907 tr 71 M=EGR_SUBPORT_TAG_DOT1P_MAP TSE=T SLTH=T; 908 tr 71 M=EGR_SUBPORT_TAG_DOT1P_MAP TSE=T SLTH=F; 909 echo " EGR_VFI"; 910 tr 50 M=EGR_VFI; 911 tr 51 M=EGR_VFI; 912 tr 52 M=EGR_VFI; 913 tr 71 M=EGR_VFI TSE=F SLTH=T; 914 tr 71 M=EGR_VFI TSE=T SLTH=T; 915 tr 71 M=EGR_VFI TSE=T SLTH=F; 916 echo " EGR_VLAN"; 917 tr 50 M=EGR_VLAN; 918 tr 51 M=EGR_VLAN; 919 tr 52 M=EGR_VLAN; 920 tr 71 M=EGR_VLAN TSE=F SLTH=T; 921 tr 71 M=EGR_VLAN TSE=T SLTH=T; 922 tr 71 M=EGR_VLAN TSE=T SLTH=F; 923 echo " EGR_VLAN_STG"; 924 tr 50 M=EGR_VLAN_STG; 925 tr 51 M=EGR_VLAN_STG; 926 tr 52 M=EGR_VLAN_STG; 927 tr 71 M=EGR_VLAN_STG TSE=F SLTH=T; 928 tr 71 M=EGR_VLAN_STG TSE=T SLTH=T; 929 tr 71 M=EGR_VLAN_STG TSE=T SLTH=F; 930 echo " EGR_VLAN_TAG_ACTION_PROFILE"; 931 tr 50 M=EGR_VLAN_TAG_ACTION_PROFILE; 932 tr 51 M=EGR_VLAN_TAG_ACTION_PROFILE; 933 tr 52 M=EGR_VLAN_TAG_ACTION_PROFILE; 934 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=F SLTH=T; 935 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=T; 936 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=F; 937 echo " EGR_VLAN_XLATE"; 938 tr 50 M=EGR_VLAN_XLATE; 939 tr 51 M=EGR_VLAN_XLATE; 940 tr 52 M=EGR_VLAN_XLATE; 941 tr 71 M=EGR_VLAN_XLATE TSE=F SLTH=T; 942 tr 71 M=EGR_VLAN_XLATE TSE=T SLTH=T; 943 tr 71 M=EGR_VLAN_XLATE TSE=T SLTH=F; 944 echo " EGR_VLAN_XLATE_OVERFLOW"; 945 tr 50 M=EGR_VLAN_XLATE_OVERFLOW; 946 tr 51 M=EGR_VLAN_XLATE_OVERFLOW; 947 tr 52 M=EGR_VLAN_XLATE_OVERFLOW; 948 tr 71 M=EGR_VLAN_XLATE_OVERFLOW TSE=F SLTH=T; 949 tr 71 M=EGR_VLAN_XLATE_OVERFLOW TSE=T SLTH=T; 950 tr 71 M=EGR_VLAN_XLATE_OVERFLOW TSE=T SLTH=F; 951 echo " EMIRROR_CONTROL"; 952 tr 50 M=EMIRROR_CONTROL; 953 tr 51 M=EMIRROR_CONTROL; 954 tr 52 M=EMIRROR_CONTROL; 955 tr 71 M=EMIRROR_CONTROL TSE=F SLTH=T; 956 tr 71 M=EMIRROR_CONTROL TSE=T SLTH=T; 957 tr 71 M=EMIRROR_CONTROL TSE=T SLTH=F; 958 echo " EMIRROR_CONTROL1"; 959 tr 50 M=EMIRROR_CONTROL1; 960 tr 51 M=EMIRROR_CONTROL1; 961 tr 52 M=EMIRROR_CONTROL1; 962 tr 71 M=EMIRROR_CONTROL1 TSE=F SLTH=T; 963 tr 71 M=EMIRROR_CONTROL1 TSE=T SLTH=T; 964 tr 71 M=EMIRROR_CONTROL1 TSE=T SLTH=F; 965 echo " EMIRROR_CONTROL2"; 966 tr 50 M=EMIRROR_CONTROL2; 967 tr 51 M=EMIRROR_CONTROL2; 968 tr 52 M=EMIRROR_CONTROL2; 969 tr 71 M=EMIRROR_CONTROL2 TSE=F SLTH=T; 970 tr 71 M=EMIRROR_CONTROL2 TSE=T SLTH=T; 971 tr 71 M=EMIRROR_CONTROL2 TSE=T SLTH=F; 972 echo " EMIRROR_CONTROL3"; 973 tr 50 M=EMIRROR_CONTROL3; 974 tr 51 M=EMIRROR_CONTROL3; 975 tr 52 M=EMIRROR_CONTROL3; 976 tr 71 M=EMIRROR_CONTROL3 TSE=F SLTH=T; 977 tr 71 M=EMIRROR_CONTROL3 TSE=T SLTH=T; 978 tr 71 M=EMIRROR_CONTROL3 TSE=T SLTH=F; 979 echo " EM_MTP_INDEX"; 980 tr 50 M=EM_MTP_INDEX; 981 tr 51 M=EM_MTP_INDEX; 982 tr 52 M=EM_MTP_INDEX; 983 tr 71 M=EM_MTP_INDEX TSE=F SLTH=T; 984 tr 71 M=EM_MTP_INDEX TSE=T SLTH=T; 985 tr 71 M=EM_MTP_INDEX TSE=T SLTH=F; 986 echo " EPC_LINK_BMAP"; 987 tr 50 M=EPC_LINK_BMAP; 988 #tr 51 M=EPC_LINK_BMAP; 989 #tr 52 M=EPC_LINK_BMAP; 990 tr 71 M=EPC_LINK_BMAP TSE=F SLTH=T; 991 tr 71 M=EPC_LINK_BMAP TSE=T SLTH=T; 992 tr 71 M=EPC_LINK_BMAP TSE=T SLTH=F; 993 echo " EP_REDIRECT_EM_MTP_INDEX"; 994 tr 50 M=EP_REDIRECT_EM_MTP_INDEX; 995 tr 51 M=EP_REDIRECT_EM_MTP_INDEX; 996 tr 52 M=EP_REDIRECT_EM_MTP_INDEX; 997 tr 71 M=EP_REDIRECT_EM_MTP_INDEX TSE=F SLTH=T; 998 tr 71 M=EP_REDIRECT_EM_MTP_INDEX TSE=T SLTH=T; 999 tr 71 M=EP_REDIRECT_EM_MTP_INDEX TSE=T SLTH=F; 1000 echo " FLOOD_LEARN_MATCH_VLANS_PORT_A"; 1001 tr 50 M=FLOOD_LEARN_MATCH_VLANS_PORT_A; 1002 tr 51 M=FLOOD_LEARN_MATCH_VLANS_PORT_A; 1003 tr 52 M=FLOOD_LEARN_MATCH_VLANS_PORT_A; 1004 tr 71 M=FLOOD_LEARN_MATCH_VLANS_PORT_A TSE=F SLTH=T; 1005 tr 71 M=FLOOD_LEARN_MATCH_VLANS_PORT_A TSE=T SLTH=T; 1006 tr 71 M=FLOOD_LEARN_MATCH_VLANS_PORT_A TSE=T SLTH=F; 1007 echo " FLOOD_LEARN_MATCH_VLANS_PORT_B"; 1008 tr 50 M=FLOOD_LEARN_MATCH_VLANS_PORT_B; 1009 tr 51 M=FLOOD_LEARN_MATCH_VLANS_PORT_B; 1010 tr 52 M=FLOOD_LEARN_MATCH_VLANS_PORT_B; 1011 tr 71 M=FLOOD_LEARN_MATCH_VLANS_PORT_B TSE=F SLTH=T; 1012 tr 71 M=FLOOD_LEARN_MATCH_VLANS_PORT_B TSE=T SLTH=T; 1013 tr 71 M=FLOOD_LEARN_MATCH_VLANS_PORT_B TSE=T SLTH=F; 1014 echo " FP_COUNTER_TABLE"; 1015 tr 50 M=FP_COUNTER_TABLE; 1016 tr 51 M=FP_COUNTER_TABLE; 1017 tr 52 M=FP_COUNTER_TABLE; 1018 tr 71 M=FP_COUNTER_TABLE TSE=F SLTH=T; 1019 tr 71 M=FP_COUNTER_TABLE TSE=T SLTH=T; 1020 tr 71 M=FP_COUNTER_TABLE TSE=T SLTH=F; 1021 echo " FP_FLEX_KEY_SELECTOR"; 1022 tr 50 M=FP_FLEX_KEY_SELECTOR; 1023 tr 51 M=FP_FLEX_KEY_SELECTOR; 1024 tr 52 M=FP_FLEX_KEY_SELECTOR; 1025 tr 71 M=FP_FLEX_KEY_SELECTOR TSE=F SLTH=T; 1026 tr 71 M=FP_FLEX_KEY_SELECTOR TSE=T SLTH=T; 1027 tr 71 M=FP_FLEX_KEY_SELECTOR TSE=T SLTH=F; 1028 echo " FP_GLOBAL_MASK_TCAM"; 1029 tr 50 M=FP_GLOBAL_MASK_TCAM; 1030 tr 51 M=FP_GLOBAL_MASK_TCAM; 1031 tr 52 M=FP_GLOBAL_MASK_TCAM; 1032 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=F SLTH=T; 1033 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=T; 1034 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=F; 1035 echo " FP_HG_CLASSID_SELECT"; 1036 tr 50 M=FP_HG_CLASSID_SELECT; 1037 tr 51 M=FP_HG_CLASSID_SELECT; 1038 tr 52 M=FP_HG_CLASSID_SELECT; 1039 tr 71 M=FP_HG_CLASSID_SELECT TSE=F SLTH=T; 1040 tr 71 M=FP_HG_CLASSID_SELECT TSE=T SLTH=T; 1041 tr 71 M=FP_HG_CLASSID_SELECT TSE=T SLTH=F; 1042 echo " FP_I2E_CLASSID_SELECT"; 1043 tr 50 M=FP_I2E_CLASSID_SELECT; 1044 tr 51 M=FP_I2E_CLASSID_SELECT; 1045 tr 52 M=FP_I2E_CLASSID_SELECT; 1046 tr 71 M=FP_I2E_CLASSID_SELECT TSE=F SLTH=T; 1047 tr 71 M=FP_I2E_CLASSID_SELECT TSE=T SLTH=T; 1048 tr 71 M=FP_I2E_CLASSID_SELECT TSE=T SLTH=F; 1049 echo " FP_METER_TABLE"; 1050 tr 50 M=FP_METER_TABLE; 1051 tr 51 M=FP_METER_TABLE; 1052 tr 52 M=FP_METER_TABLE; 1053 tr 71 M=FP_METER_TABLE TSE=F SLTH=T; 1054 tr 71 M=FP_METER_TABLE TSE=T SLTH=T; 1055 tr 71 M=FP_METER_TABLE TSE=T SLTH=F; 1056 echo " FP_POLICY_TABLE"; 1057 tr 50 M=FP_POLICY_TABLE; 1058 tr 51 M=FP_POLICY_TABLE; 1059 tr 52 M=FP_POLICY_TABLE; 1060 tr 71 M=FP_POLICY_TABLE TSE=F SLTH=T; 1061 tr 71 M=FP_POLICY_TABLE TSE=T SLTH=T; 1062 tr 71 M=FP_POLICY_TABLE TSE=T SLTH=F; 1063 echo " FP_PORT_FIELD_SEL"; 1064 tr 50 M=FP_PORT_FIELD_SEL; 1065 tr 51 M=FP_PORT_FIELD_SEL; 1066 tr 52 M=FP_PORT_FIELD_SEL; 1067 tr 71 M=FP_PORT_FIELD_SEL TSE=F SLTH=T; 1068 tr 71 M=FP_PORT_FIELD_SEL TSE=T SLTH=T; 1069 tr 71 M=FP_PORT_FIELD_SEL TSE=T SLTH=F; 1070 echo " FP_PORT_METER_MAP"; 1071 tr 50 M=FP_PORT_METER_MAP; 1072 tr 51 M=FP_PORT_METER_MAP; 1073 tr 52 M=FP_PORT_METER_MAP; 1074 tr 71 M=FP_PORT_METER_MAP TSE=F SLTH=T; 1075 tr 71 M=FP_PORT_METER_MAP TSE=T SLTH=T; 1076 tr 71 M=FP_PORT_METER_MAP TSE=T SLTH=F; 1077 echo " FP_RANGE_CHECK"; 1078 tr 50 M=FP_RANGE_CHECK; 1079 tr 51 M=FP_RANGE_CHECK; 1080 tr 52 M=FP_RANGE_CHECK; 1081 tr 71 M=FP_RANGE_CHECK TSE=F SLTH=T; 1082 tr 71 M=FP_RANGE_CHECK TSE=T SLTH=T; 1083 tr 71 M=FP_RANGE_CHECK TSE=T SLTH=F; 1084 echo " FP_SLICE_KEY_CONTROL"; 1085 tr 50 M=FP_SLICE_KEY_CONTROL; 1086 #tr 51 M=FP_SLICE_KEY_CONTROL; 1087 #tr 52 M=FP_SLICE_KEY_CONTROL; 1088 tr 71 M=FP_SLICE_KEY_CONTROL TSE=F SLTH=T; 1089 tr 71 M=FP_SLICE_KEY_CONTROL TSE=T SLTH=T; 1090 tr 71 M=FP_SLICE_KEY_CONTROL TSE=T SLTH=F; 1091 echo " FP_SLICE_MAP"; 1092 tr 50 M=FP_SLICE_MAP; 1093 #tr 51 M=FP_SLICE_MAP; 1094 #tr 52 M=FP_SLICE_MAP; 1095 tr 71 M=FP_SLICE_MAP TSE=F SLTH=T; 1096 tr 71 M=FP_SLICE_MAP TSE=T SLTH=T; 1097 tr 71 M=FP_SLICE_MAP TSE=T SLTH=F; 1098 echo " FP_STORM_CONTROL_METERS"; 1099 tr 50 M=FP_STORM_CONTROL_METERS; 1100 tr 51 M=FP_STORM_CONTROL_METERS; 1101 tr 52 M=FP_STORM_CONTROL_METERS; 1102 tr 71 M=FP_STORM_CONTROL_METERS TSE=F SLTH=T; 1103 tr 71 M=FP_STORM_CONTROL_METERS TSE=T SLTH=T; 1104 tr 71 M=FP_STORM_CONTROL_METERS TSE=T SLTH=F; 1105 echo " FP_TCAM"; 1106 tr 50 M=FP_TCAM; 1107 tr 51 M=FP_TCAM; 1108 tr 52 M=FP_TCAM; 1109 tr 71 M=FP_TCAM TSE=F SLTH=T; 1110 tr 71 M=FP_TCAM TSE=T SLTH=T; 1111 tr 71 M=FP_TCAM TSE=T SLTH=F; 1112 echo " FP_UDF_OFFSET"; 1113 tr 50 M=FP_UDF_OFFSET; 1114 tr 51 M=FP_UDF_OFFSET; 1115 tr 52 M=FP_UDF_OFFSET; 1116 tr 71 M=FP_UDF_OFFSET TSE=F SLTH=T; 1117 tr 71 M=FP_UDF_OFFSET TSE=T SLTH=T; 1118 tr 71 M=FP_UDF_OFFSET TSE=T SLTH=F; 1119 echo " FP_UDF_TCAM"; 1120 tr 50 M=FP_UDF_TCAM; 1121 tr 51 M=FP_UDF_TCAM; 1122 tr 52 M=FP_UDF_TCAM; 1123 tr 71 M=FP_UDF_TCAM TSE=F SLTH=T; 1124 tr 71 M=FP_UDF_TCAM TSE=T SLTH=T; 1125 tr 71 M=FP_UDF_TCAM TSE=T SLTH=F; 1126 echo " GTP_PORT_TABLE"; 1127 tr 50 M=GTP_PORT_TABLE; 1128 tr 51 M=GTP_PORT_TABLE; 1129 tr 52 M=GTP_PORT_TABLE; 1130 tr 71 M=GTP_PORT_TABLE TSE=F SLTH=T; 1131 tr 71 M=GTP_PORT_TABLE TSE=T SLTH=T; 1132 tr 71 M=GTP_PORT_TABLE TSE=T SLTH=F; 1133 echo " HG_TRUNK_BITMAP"; 1134 tr 50 M=HG_TRUNK_BITMAP; 1135 tr 51 M=HG_TRUNK_BITMAP; 1136 tr 52 M=HG_TRUNK_BITMAP; 1137 tr 71 M=HG_TRUNK_BITMAP TSE=F SLTH=T; 1138 tr 71 M=HG_TRUNK_BITMAP TSE=T SLTH=T; 1139 tr 71 M=HG_TRUNK_BITMAP TSE=T SLTH=F; 1140 echo " HG_TRUNK_FAILOVER_ENABLE"; 1141 tr 50 M=HG_TRUNK_FAILOVER_ENABLE; 1142 #tr 51 M=HG_TRUNK_FAILOVER_ENABLE; 1143 #tr 52 M=HG_TRUNK_FAILOVER_ENABLE; 1144 tr 71 M=HG_TRUNK_FAILOVER_ENABLE TSE=F SLTH=T; 1145 tr 71 M=HG_TRUNK_FAILOVER_ENABLE TSE=T SLTH=T; 1146 tr 71 M=HG_TRUNK_FAILOVER_ENABLE TSE=T SLTH=F; 1147 echo " HG_TRUNK_FAILOVER_SET"; 1148 tr 50 M=HG_TRUNK_FAILOVER_SET; 1149 tr 51 M=HG_TRUNK_FAILOVER_SET; 1150 tr 52 M=HG_TRUNK_FAILOVER_SET; 1151 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=F SLTH=T; 1152 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=T SLTH=T; 1153 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=T SLTH=F; 1154 echo " HG_TRUNK_GROUP"; 1155 tr 50 M=HG_TRUNK_GROUP; 1156 tr 51 M=HG_TRUNK_GROUP; 1157 tr 52 M=HG_TRUNK_GROUP; 1158 tr 71 M=HG_TRUNK_GROUP TSE=F SLTH=T; 1159 tr 71 M=HG_TRUNK_GROUP TSE=T SLTH=T; 1160 tr 71 M=HG_TRUNK_GROUP TSE=T SLTH=F; 1161 echo " HG_TRUNK_MEMBER"; 1162 tr 50 M=HG_TRUNK_MEMBER; 1163 tr 51 M=HG_TRUNK_MEMBER; 1164 tr 52 M=HG_TRUNK_MEMBER; 1165 tr 71 M=HG_TRUNK_MEMBER TSE=F SLTH=T; 1166 tr 71 M=HG_TRUNK_MEMBER TSE=T SLTH=T; 1167 tr 71 M=HG_TRUNK_MEMBER TSE=T SLTH=F; 1168 echo " HIGIG_TRUNK_CONTROL"; 1169 tr 50 M=HIGIG_TRUNK_CONTROL; 1170 #tr 51 M=HIGIG_TRUNK_CONTROL; 1171 #tr 52 M=HIGIG_TRUNK_CONTROL; 1172 tr 71 M=HIGIG_TRUNK_CONTROL TSE=F SLTH=T; 1173 tr 71 M=HIGIG_TRUNK_CONTROL TSE=T SLTH=T; 1174 tr 71 M=HIGIG_TRUNK_CONTROL TSE=T SLTH=F; 1175 echo " IARB_ING_PHYSICAL_PORT"; 1176 tr 50 M=IARB_ING_PHYSICAL_PORT; 1177 tr 51 M=IARB_ING_PHYSICAL_PORT; 1178 tr 52 M=IARB_ING_PHYSICAL_PORT; 1179 tr 71 M=IARB_ING_PHYSICAL_PORT TSE=F SLTH=T; 1180 tr 71 M=IARB_ING_PHYSICAL_PORT TSE=T SLTH=T; 1181 tr 71 M=IARB_ING_PHYSICAL_PORT TSE=T SLTH=F; 1182 echo " IARB_TDM_TABLE"; 1183 tr 50 M=IARB_TDM_TABLE; 1184 tr 51 M=IARB_TDM_TABLE; 1185 tr 52 M=IARB_TDM_TABLE; 1186 tr 71 M=IARB_TDM_TABLE TSE=F SLTH=T; 1187 tr 71 M=IARB_TDM_TABLE TSE=T SLTH=T; 1188 tr 71 M=IARB_TDM_TABLE TSE=T SLTH=F; 1189 echo " IARB_TDM_TABLE_1"; 1190 tr 50 M=IARB_TDM_TABLE_1; 1191 tr 51 M=IARB_TDM_TABLE_1; 1192 tr 52 M=IARB_TDM_TABLE_1; 1193 tr 71 M=IARB_TDM_TABLE_1 TSE=F SLTH=T; 1194 tr 71 M=IARB_TDM_TABLE_1 TSE=T SLTH=T; 1195 tr 71 M=IARB_TDM_TABLE_1 TSE=T SLTH=F; 1196 echo " ICONTROL_OPCODE_BITMAP"; 1197 tr 50 M=ICONTROL_OPCODE_BITMAP; 1198 tr 51 M=ICONTROL_OPCODE_BITMAP; 1199 tr 52 M=ICONTROL_OPCODE_BITMAP; 1200 tr 71 M=ICONTROL_OPCODE_BITMAP TSE=F SLTH=T; 1201 tr 71 M=ICONTROL_OPCODE_BITMAP TSE=T SLTH=T; 1202 tr 71 M=ICONTROL_OPCODE_BITMAP TSE=T SLTH=F; 1203 echo " IFP_COS_MAP"; 1204 tr 50 M=IFP_COS_MAP; 1205 tr 51 M=IFP_COS_MAP; 1206 tr 52 M=IFP_COS_MAP; 1207 tr 71 M=IFP_COS_MAP TSE=F SLTH=T; 1208 tr 71 M=IFP_COS_MAP TSE=T SLTH=T; 1209 tr 71 M=IFP_COS_MAP TSE=T SLTH=F; 1210 echo " IFP_REDIRECTION_PROFILE"; 1211 tr 50 M=IFP_REDIRECTION_PROFILE; 1212 tr 51 M=IFP_REDIRECTION_PROFILE; 1213 tr 52 M=IFP_REDIRECTION_PROFILE; 1214 tr 71 M=IFP_REDIRECTION_PROFILE TSE=F SLTH=T; 1215 tr 71 M=IFP_REDIRECTION_PROFILE TSE=T SLTH=T; 1216 tr 71 M=IFP_REDIRECTION_PROFILE TSE=T SLTH=F; 1217 echo " IMIRROR_BITMAP"; 1218 tr 50 M=IMIRROR_BITMAP; 1219 tr 51 M=IMIRROR_BITMAP; 1220 tr 52 M=IMIRROR_BITMAP; 1221 tr 71 M=IMIRROR_BITMAP TSE=F SLTH=T; 1222 tr 71 M=IMIRROR_BITMAP TSE=T SLTH=T; 1223 tr 71 M=IMIRROR_BITMAP TSE=T SLTH=F; 1224 echo " IM_MTP_INDEX"; 1225 tr 50 M=IM_MTP_INDEX; 1226 tr 51 M=IM_MTP_INDEX; 1227 tr 52 M=IM_MTP_INDEX; 1228 tr 71 M=IM_MTP_INDEX TSE=F SLTH=T; 1229 tr 71 M=IM_MTP_INDEX TSE=T SLTH=T; 1230 tr 71 M=IM_MTP_INDEX TSE=T SLTH=F; 1231 echo " INGRESS_OAM_OPCODE_GROUP"; 1232 tr 50 M=INGRESS_OAM_OPCODE_GROUP; 1233 tr 51 M=INGRESS_OAM_OPCODE_GROUP; 1234 tr 52 M=INGRESS_OAM_OPCODE_GROUP; 1235 tr 71 M=INGRESS_OAM_OPCODE_GROUP TSE=F SLTH=T; 1236 tr 71 M=INGRESS_OAM_OPCODE_GROUP TSE=T SLTH=T; 1237 tr 71 M=INGRESS_OAM_OPCODE_GROUP TSE=T SLTH=F; 1238 echo " ING_1588_TS_DISPOSITION_PROFILE_TABLE"; 1239 tr 50 M=ING_1588_TS_DISPOSITION_PROFILE_TABLE; 1240 tr 51 M=ING_1588_TS_DISPOSITION_PROFILE_TABLE; 1241 tr 52 M=ING_1588_TS_DISPOSITION_PROFILE_TABLE; 1242 tr 71 M=ING_1588_TS_DISPOSITION_PROFILE_TABLE TSE=F SLTH=T; 1243 tr 71 M=ING_1588_TS_DISPOSITION_PROFILE_TABLE TSE=T SLTH=T; 1244 tr 71 M=ING_1588_TS_DISPOSITION_PROFILE_TABLE TSE=T SLTH=F; 1245 echo " ING_DVP_TABLE"; 1246 tr 50 M=ING_DVP_TABLE; 1247 tr 51 M=ING_DVP_TABLE; 1248 tr 52 M=ING_DVP_TABLE; 1249 tr 71 M=ING_DVP_TABLE TSE=F SLTH=T; 1250 tr 71 M=ING_DVP_TABLE TSE=T SLTH=T; 1251 tr 71 M=ING_DVP_TABLE TSE=T SLTH=F; 1252 echo " ING_EGRMSKBMAP"; 1253 tr 50 M=ING_EGRMSKBMAP; 1254 tr 51 M=ING_EGRMSKBMAP; 1255 tr 52 M=ING_EGRMSKBMAP; 1256 tr 71 M=ING_EGRMSKBMAP TSE=F SLTH=T; 1257 tr 71 M=ING_EGRMSKBMAP TSE=T SLTH=T; 1258 tr 71 M=ING_EGRMSKBMAP TSE=T SLTH=F; 1259 echo " ING_EN_EFILTER_BITMAP"; 1260 tr 50 M=ING_EN_EFILTER_BITMAP; 1261 #tr 51 M=ING_EN_EFILTER_BITMAP; 1262 #tr 52 M=ING_EN_EFILTER_BITMAP; 1263 tr 71 M=ING_EN_EFILTER_BITMAP TSE=F SLTH=T; 1264 tr 71 M=ING_EN_EFILTER_BITMAP TSE=T SLTH=T; 1265 tr 71 M=ING_EN_EFILTER_BITMAP TSE=T SLTH=F; 1266 echo " ING_FLEX_CTR_COUNTER_TABLE_0"; 1267 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_0; 1268 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_0; 1269 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_0; 1270 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_0 TSE=F SLTH=T; 1271 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_0 TSE=T SLTH=T; 1272 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_0 TSE=T SLTH=F; 1273 echo " ING_FLEX_CTR_COUNTER_TABLE_1"; 1274 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_1; 1275 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_1; 1276 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_1; 1277 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_1 TSE=F SLTH=T; 1278 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_1 TSE=T SLTH=T; 1279 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_1 TSE=T SLTH=F; 1280 echo " ING_FLEX_CTR_COUNTER_TABLE_2"; 1281 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_2; 1282 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_2; 1283 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_2; 1284 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_2 TSE=F SLTH=T; 1285 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_2 TSE=T SLTH=T; 1286 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_2 TSE=T SLTH=F; 1287 echo " ING_FLEX_CTR_COUNTER_TABLE_3"; 1288 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_3; 1289 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_3; 1290 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_3; 1291 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_3 TSE=F SLTH=T; 1292 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_3 TSE=T SLTH=T; 1293 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_3 TSE=T SLTH=F; 1294 echo " ING_FLEX_CTR_COUNTER_TABLE_4"; 1295 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_4; 1296 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_4; 1297 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_4; 1298 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_4 TSE=F SLTH=T; 1299 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_4 TSE=T SLTH=T; 1300 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_4 TSE=T SLTH=F; 1301 echo " ING_FLEX_CTR_COUNTER_TABLE_5"; 1302 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_5; 1303 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_5; 1304 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_5; 1305 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_5 TSE=F SLTH=T; 1306 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_5 TSE=T SLTH=T; 1307 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_5 TSE=T SLTH=F; 1308 echo " ING_FLEX_CTR_COUNTER_TABLE_6"; 1309 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_6; 1310 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_6; 1311 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_6; 1312 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_6 TSE=F SLTH=T; 1313 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_6 TSE=T SLTH=T; 1314 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_6 TSE=T SLTH=F; 1315 echo " ING_FLEX_CTR_COUNTER_TABLE_7"; 1316 tr 50 M=ING_FLEX_CTR_COUNTER_TABLE_7; 1317 tr 51 M=ING_FLEX_CTR_COUNTER_TABLE_7; 1318 tr 52 M=ING_FLEX_CTR_COUNTER_TABLE_7; 1319 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_7 TSE=F SLTH=T; 1320 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_7 TSE=T SLTH=T; 1321 tr 71 M=ING_FLEX_CTR_COUNTER_TABLE_7 TSE=T SLTH=F; 1322 echo " ING_FLEX_CTR_OFFSET_TABLE_0"; 1323 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_0; 1324 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_0; 1325 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_0; 1326 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_0 TSE=F SLTH=T; 1327 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_0 TSE=T SLTH=T; 1328 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_0 TSE=T SLTH=F; 1329 echo " ING_FLEX_CTR_OFFSET_TABLE_1"; 1330 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_1; 1331 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_1; 1332 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_1; 1333 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_1 TSE=F SLTH=T; 1334 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_1 TSE=T SLTH=T; 1335 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_1 TSE=T SLTH=F; 1336 echo " ING_FLEX_CTR_OFFSET_TABLE_2"; 1337 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_2; 1338 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_2; 1339 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_2; 1340 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_2 TSE=F SLTH=T; 1341 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_2 TSE=T SLTH=T; 1342 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_2 TSE=T SLTH=F; 1343 echo " ING_FLEX_CTR_OFFSET_TABLE_3"; 1344 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_3; 1345 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_3; 1346 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_3; 1347 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_3 TSE=F SLTH=T; 1348 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_3 TSE=T SLTH=T; 1349 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_3 TSE=T SLTH=F; 1350 echo " ING_FLEX_CTR_OFFSET_TABLE_4"; 1351 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_4; 1352 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_4; 1353 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_4; 1354 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_4 TSE=F SLTH=T; 1355 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_4 TSE=T SLTH=T; 1356 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_4 TSE=T SLTH=F; 1357 echo " ING_FLEX_CTR_OFFSET_TABLE_5"; 1358 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_5; 1359 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_5; 1360 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_5; 1361 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_5 TSE=F SLTH=T; 1362 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_5 TSE=T SLTH=T; 1363 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_5 TSE=T SLTH=F; 1364 echo " ING_FLEX_CTR_OFFSET_TABLE_6"; 1365 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_6; 1366 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_6; 1367 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_6; 1368 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_6 TSE=F SLTH=T; 1369 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_6 TSE=T SLTH=T; 1370 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_6 TSE=T SLTH=F; 1371 echo " ING_FLEX_CTR_OFFSET_TABLE_7"; 1372 tr 50 M=ING_FLEX_CTR_OFFSET_TABLE_7; 1373 tr 51 M=ING_FLEX_CTR_OFFSET_TABLE_7; 1374 tr 52 M=ING_FLEX_CTR_OFFSET_TABLE_7; 1375 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_7 TSE=F SLTH=T; 1376 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_7 TSE=T SLTH=T; 1377 tr 71 M=ING_FLEX_CTR_OFFSET_TABLE_7 TSE=T SLTH=F; 1378 echo " ING_FLEX_CTR_PKT_PRI_MAP"; 1379 tr 50 M=ING_FLEX_CTR_PKT_PRI_MAP; 1380 tr 51 M=ING_FLEX_CTR_PKT_PRI_MAP; 1381 tr 52 M=ING_FLEX_CTR_PKT_PRI_MAP; 1382 tr 71 M=ING_FLEX_CTR_PKT_PRI_MAP TSE=F SLTH=T; 1383 tr 71 M=ING_FLEX_CTR_PKT_PRI_MAP TSE=T SLTH=T; 1384 tr 71 M=ING_FLEX_CTR_PKT_PRI_MAP TSE=T SLTH=F; 1385 echo " ING_FLEX_CTR_PKT_RES_MAP"; 1386 tr 50 M=ING_FLEX_CTR_PKT_RES_MAP; 1387 tr 51 M=ING_FLEX_CTR_PKT_RES_MAP; 1388 tr 52 M=ING_FLEX_CTR_PKT_RES_MAP; 1389 tr 71 M=ING_FLEX_CTR_PKT_RES_MAP TSE=F SLTH=T; 1390 tr 71 M=ING_FLEX_CTR_PKT_RES_MAP TSE=T SLTH=T; 1391 tr 71 M=ING_FLEX_CTR_PKT_RES_MAP TSE=T SLTH=F; 1392 echo " ING_FLEX_CTR_PORT_MAP"; 1393 tr 50 M=ING_FLEX_CTR_PORT_MAP; 1394 tr 51 M=ING_FLEX_CTR_PORT_MAP; 1395 tr 52 M=ING_FLEX_CTR_PORT_MAP; 1396 tr 71 M=ING_FLEX_CTR_PORT_MAP TSE=F SLTH=T; 1397 tr 71 M=ING_FLEX_CTR_PORT_MAP TSE=T SLTH=T; 1398 tr 71 M=ING_FLEX_CTR_PORT_MAP TSE=T SLTH=F; 1399 echo " ING_FLEX_CTR_PRI_CNG_MAP"; 1400 tr 50 M=ING_FLEX_CTR_PRI_CNG_MAP; 1401 tr 51 M=ING_FLEX_CTR_PRI_CNG_MAP; 1402 tr 52 M=ING_FLEX_CTR_PRI_CNG_MAP; 1403 tr 71 M=ING_FLEX_CTR_PRI_CNG_MAP TSE=F SLTH=T; 1404 tr 71 M=ING_FLEX_CTR_PRI_CNG_MAP TSE=T SLTH=T; 1405 tr 71 M=ING_FLEX_CTR_PRI_CNG_MAP TSE=T SLTH=F; 1406 echo " ING_FLEX_CTR_TOS_MAP"; 1407 tr 50 M=ING_FLEX_CTR_TOS_MAP; 1408 tr 51 M=ING_FLEX_CTR_TOS_MAP; 1409 tr 52 M=ING_FLEX_CTR_TOS_MAP; 1410 tr 71 M=ING_FLEX_CTR_TOS_MAP TSE=F SLTH=T; 1411 tr 71 M=ING_FLEX_CTR_TOS_MAP TSE=T SLTH=T; 1412 tr 71 M=ING_FLEX_CTR_TOS_MAP TSE=T SLTH=F; 1413 echo " ING_HIGIG_TRUNK_OVERRIDE_PROFILE"; 1414 tr 50 M=ING_HIGIG_TRUNK_OVERRIDE_PROFILE; 1415 tr 51 M=ING_HIGIG_TRUNK_OVERRIDE_PROFILE; 1416 tr 52 M=ING_HIGIG_TRUNK_OVERRIDE_PROFILE; 1417 tr 71 M=ING_HIGIG_TRUNK_OVERRIDE_PROFILE TSE=F SLTH=T; 1418 tr 71 M=ING_HIGIG_TRUNK_OVERRIDE_PROFILE TSE=T SLTH=T; 1419 tr 71 M=ING_HIGIG_TRUNK_OVERRIDE_PROFILE TSE=T SLTH=F; 1420 echo " ING_L3_NEXT_HOP"; 1421 tr 50 M=ING_L3_NEXT_HOP; 1422 tr 51 M=ING_L3_NEXT_HOP; 1423 tr 52 M=ING_L3_NEXT_HOP; 1424 tr 71 M=ING_L3_NEXT_HOP TSE=F SLTH=T; 1425 tr 71 M=ING_L3_NEXT_HOP TSE=T SLTH=T; 1426 tr 71 M=ING_L3_NEXT_HOP TSE=T SLTH=F; 1427 echo " ING_MOD_MAP_TABLE"; 1428 tr 50 M=ING_MOD_MAP_TABLE; 1429 tr 51 M=ING_MOD_MAP_TABLE; 1430 tr 52 M=ING_MOD_MAP_TABLE; 1431 tr 71 M=ING_MOD_MAP_TABLE TSE=F SLTH=T; 1432 tr 71 M=ING_MOD_MAP_TABLE TSE=T SLTH=T; 1433 tr 71 M=ING_MOD_MAP_TABLE TSE=T SLTH=F; 1434 echo " ING_MPLS_EXP_MAPPING"; 1435 tr 50 M=ING_MPLS_EXP_MAPPING; 1436 tr 51 M=ING_MPLS_EXP_MAPPING; 1437 tr 52 M=ING_MPLS_EXP_MAPPING; 1438 tr 71 M=ING_MPLS_EXP_MAPPING TSE=F SLTH=T; 1439 tr 71 M=ING_MPLS_EXP_MAPPING TSE=T SLTH=T; 1440 tr 71 M=ING_MPLS_EXP_MAPPING TSE=T SLTH=F; 1441 echo " ING_NETWORK_PRUNE_CONTROL"; 1442 tr 50 M=ING_NETWORK_PRUNE_CONTROL; 1443 tr 51 M=ING_NETWORK_PRUNE_CONTROL; 1444 tr 52 M=ING_NETWORK_PRUNE_CONTROL; 1445 tr 71 M=ING_NETWORK_PRUNE_CONTROL TSE=F SLTH=T; 1446 tr 71 M=ING_NETWORK_PRUNE_CONTROL TSE=T SLTH=T; 1447 tr 71 M=ING_NETWORK_PRUNE_CONTROL TSE=T SLTH=F; 1448 echo " ING_OAM_DGLP_PROFILE"; 1449 tr 50 M=ING_OAM_DGLP_PROFILE; 1450 tr 51 M=ING_OAM_DGLP_PROFILE; 1451 tr 52 M=ING_OAM_DGLP_PROFILE; 1452 tr 71 M=ING_OAM_DGLP_PROFILE TSE=F SLTH=T; 1453 tr 71 M=ING_OAM_DGLP_PROFILE TSE=T SLTH=T; 1454 tr 71 M=ING_OAM_DGLP_PROFILE TSE=T SLTH=F; 1455 echo " ING_OAM_FLEXIBLE_DOMAIN_CONTROL"; 1456 tr 50 M=ING_OAM_FLEXIBLE_DOMAIN_CONTROL; 1457 tr 51 M=ING_OAM_FLEXIBLE_DOMAIN_CONTROL; 1458 tr 52 M=ING_OAM_FLEXIBLE_DOMAIN_CONTROL; 1459 tr 71 M=ING_OAM_FLEXIBLE_DOMAIN_CONTROL TSE=F SLTH=T; 1460 tr 71 M=ING_OAM_FLEXIBLE_DOMAIN_CONTROL TSE=T SLTH=T; 1461 tr 71 M=ING_OAM_FLEXIBLE_DOMAIN_CONTROL TSE=T SLTH=F; 1462 #echo " ING_PBI_DEBUG_0_HI"; 1463 #tr 50 M=ING_PBI_DEBUG_0_HI; 1464 #tr 51 M=ING_PBI_DEBUG_0_HI; 1465 #tr 52 M=ING_PBI_DEBUG_0_HI; 1466 #tr 71 M=ING_PBI_DEBUG_0_HI TSE=F SLTH=T; 1467 #tr 71 M=ING_PBI_DEBUG_0_HI TSE=T SLTH=T; 1468 #tr 71 M=ING_PBI_DEBUG_0_HI TSE=T SLTH=F; 1469 #echo " ING_PBI_DEBUG_0_LO"; 1470 #tr 50 M=ING_PBI_DEBUG_0_LO; 1471 #tr 51 M=ING_PBI_DEBUG_0_LO; 1472 #tr 52 M=ING_PBI_DEBUG_0_LO; 1473 #tr 71 M=ING_PBI_DEBUG_0_LO TSE=F SLTH=T; 1474 #tr 71 M=ING_PBI_DEBUG_0_LO TSE=T SLTH=T; 1475 #tr 71 M=ING_PBI_DEBUG_0_LO TSE=T SLTH=F; 1476 #echo " ING_PBI_DEBUG_1"; 1477 #tr 50 M=ING_PBI_DEBUG_1; 1478 #tr 51 M=ING_PBI_DEBUG_1; 1479 #tr 52 M=ING_PBI_DEBUG_1; 1480 #tr 71 M=ING_PBI_DEBUG_1 TSE=F SLTH=T; 1481 #tr 71 M=ING_PBI_DEBUG_1 TSE=T SLTH=T; 1482 #tr 71 M=ING_PBI_DEBUG_1 TSE=T SLTH=F; 1483 echo " ING_PHYSICAL_PORT_TABLE"; 1484 tr 50 M=ING_PHYSICAL_PORT_TABLE; 1485 tr 51 M=ING_PHYSICAL_PORT_TABLE; 1486 tr 52 M=ING_PHYSICAL_PORT_TABLE; 1487 tr 71 M=ING_PHYSICAL_PORT_TABLE TSE=F SLTH=T; 1488 tr 71 M=ING_PHYSICAL_PORT_TABLE TSE=T SLTH=T; 1489 tr 71 M=ING_PHYSICAL_PORT_TABLE TSE=T SLTH=F; 1490 echo " ING_PRI_CNG_MAP"; 1491 tr 50 M=ING_PRI_CNG_MAP; 1492 tr 51 M=ING_PRI_CNG_MAP; 1493 tr 52 M=ING_PRI_CNG_MAP; 1494 tr 71 M=ING_PRI_CNG_MAP TSE=F SLTH=T; 1495 tr 71 M=ING_PRI_CNG_MAP TSE=T SLTH=T; 1496 tr 71 M=ING_PRI_CNG_MAP TSE=T SLTH=F; 1497 echo " ING_PW_TERM_SEQ_NUM"; 1498 tr 50 M=ING_PW_TERM_SEQ_NUM; 1499 tr 51 M=ING_PW_TERM_SEQ_NUM; 1500 tr 52 M=ING_PW_TERM_SEQ_NUM; 1501 tr 71 M=ING_PW_TERM_SEQ_NUM TSE=F SLTH=T; 1502 tr 71 M=ING_PW_TERM_SEQ_NUM TSE=T SLTH=T; 1503 tr 71 M=ING_PW_TERM_SEQ_NUM TSE=T SLTH=F; 1504 echo " ING_QUEUE_MAP"; 1505 tr 50 M=ING_QUEUE_MAP; 1506 tr 51 M=ING_QUEUE_MAP; 1507 tr 52 M=ING_QUEUE_MAP; 1508 tr 71 M=ING_QUEUE_MAP TSE=F SLTH=T; 1509 tr 71 M=ING_QUEUE_MAP TSE=T SLTH=T; 1510 tr 71 M=ING_QUEUE_MAP TSE=T SLTH=F; 1511 echo " ING_QUEUE_OFFSET_MAPPING_TABLE"; 1512 tr 50 M=ING_QUEUE_OFFSET_MAPPING_TABLE; 1513 tr 51 M=ING_QUEUE_OFFSET_MAPPING_TABLE; 1514 tr 52 M=ING_QUEUE_OFFSET_MAPPING_TABLE; 1515 tr 71 M=ING_QUEUE_OFFSET_MAPPING_TABLE TSE=F SLTH=T; 1516 tr 71 M=ING_QUEUE_OFFSET_MAPPING_TABLE TSE=T SLTH=T; 1517 tr 71 M=ING_QUEUE_OFFSET_MAPPING_TABLE TSE=T SLTH=F; 1518 echo " ING_SERVICE_PRI_MAP"; 1519 tr 50 M=ING_SERVICE_PRI_MAP; 1520 tr 51 M=ING_SERVICE_PRI_MAP; 1521 tr 52 M=ING_SERVICE_PRI_MAP; 1522 tr 71 M=ING_SERVICE_PRI_MAP TSE=F SLTH=T; 1523 tr 71 M=ING_SERVICE_PRI_MAP TSE=T SLTH=T; 1524 tr 71 M=ING_SERVICE_PRI_MAP TSE=T SLTH=F; 1525 echo " ING_SVM_PKT_PRI_MAP"; 1526 tr 50 M=ING_SVM_PKT_PRI_MAP; 1527 tr 51 M=ING_SVM_PKT_PRI_MAP; 1528 tr 52 M=ING_SVM_PKT_PRI_MAP; 1529 tr 71 M=ING_SVM_PKT_PRI_MAP TSE=F SLTH=T; 1530 tr 71 M=ING_SVM_PKT_PRI_MAP TSE=T SLTH=T; 1531 tr 71 M=ING_SVM_PKT_PRI_MAP TSE=T SLTH=F; 1532 echo " ING_SVM_PKT_RES_MAP"; 1533 tr 50 M=ING_SVM_PKT_RES_MAP; 1534 tr 51 M=ING_SVM_PKT_RES_MAP; 1535 tr 52 M=ING_SVM_PKT_RES_MAP; 1536 tr 71 M=ING_SVM_PKT_RES_MAP TSE=F SLTH=T; 1537 tr 71 M=ING_SVM_PKT_RES_MAP TSE=T SLTH=T; 1538 tr 71 M=ING_SVM_PKT_RES_MAP TSE=T SLTH=F; 1539 echo " ING_SVM_PORT_MAP"; 1540 tr 50 M=ING_SVM_PORT_MAP; 1541 tr 51 M=ING_SVM_PORT_MAP; 1542 tr 52 M=ING_SVM_PORT_MAP; 1543 tr 71 M=ING_SVM_PORT_MAP TSE=F SLTH=T; 1544 tr 71 M=ING_SVM_PORT_MAP TSE=T SLTH=T; 1545 tr 71 M=ING_SVM_PORT_MAP TSE=T SLTH=F; 1546 echo " ING_SVM_PRI_CNG_MAP"; 1547 tr 50 M=ING_SVM_PRI_CNG_MAP; 1548 tr 51 M=ING_SVM_PRI_CNG_MAP; 1549 tr 52 M=ING_SVM_PRI_CNG_MAP; 1550 tr 71 M=ING_SVM_PRI_CNG_MAP TSE=F SLTH=T; 1551 tr 71 M=ING_SVM_PRI_CNG_MAP TSE=T SLTH=T; 1552 tr 71 M=ING_SVM_PRI_CNG_MAP TSE=T SLTH=F; 1553 echo " ING_SVM_TOS_MAP"; 1554 tr 50 M=ING_SVM_TOS_MAP; 1555 tr 51 M=ING_SVM_TOS_MAP; 1556 tr 52 M=ING_SVM_TOS_MAP; 1557 tr 71 M=ING_SVM_TOS_MAP TSE=F SLTH=T; 1558 tr 71 M=ING_SVM_TOS_MAP TSE=T SLTH=T; 1559 tr 71 M=ING_SVM_TOS_MAP TSE=T SLTH=F; 1560 echo " ING_UNTAGGED_PHB"; 1561 tr 50 M=ING_UNTAGGED_PHB; 1562 tr 51 M=ING_UNTAGGED_PHB; 1563 tr 52 M=ING_UNTAGGED_PHB; 1564 tr 71 M=ING_UNTAGGED_PHB TSE=F SLTH=T; 1565 tr 71 M=ING_UNTAGGED_PHB TSE=T SLTH=T; 1566 tr 71 M=ING_UNTAGGED_PHB TSE=T SLTH=F; 1567 echo " ING_VLAN_RANGE"; 1568 tr 50 M=ING_VLAN_RANGE; 1569 tr 51 M=ING_VLAN_RANGE; 1570 tr 52 M=ING_VLAN_RANGE; 1571 tr 71 M=ING_VLAN_RANGE TSE=F SLTH=T; 1572 tr 71 M=ING_VLAN_RANGE TSE=T SLTH=T; 1573 tr 71 M=ING_VLAN_RANGE TSE=T SLTH=F; 1574 echo " ING_VLAN_TAG_ACTION_PROFILE"; 1575 tr 50 M=ING_VLAN_TAG_ACTION_PROFILE; 1576 tr 51 M=ING_VLAN_TAG_ACTION_PROFILE; 1577 tr 52 M=ING_VLAN_TAG_ACTION_PROFILE; 1578 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=F SLTH=T; 1579 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=T; 1580 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=F; 1581 echo " INITIAL_ING_L3_NEXT_HOP"; 1582 tr 50 M=INITIAL_ING_L3_NEXT_HOP; 1583 tr 51 M=INITIAL_ING_L3_NEXT_HOP; 1584 tr 52 M=INITIAL_ING_L3_NEXT_HOP; 1585 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=F SLTH=T; 1586 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=T SLTH=T; 1587 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=T SLTH=F; 1588 echo " INITIAL_L3_ECMP"; 1589 tr 50 M=INITIAL_L3_ECMP; 1590 tr 51 M=INITIAL_L3_ECMP; 1591 tr 52 M=INITIAL_L3_ECMP; 1592 tr 71 M=INITIAL_L3_ECMP TSE=F SLTH=T; 1593 tr 71 M=INITIAL_L3_ECMP TSE=T SLTH=T; 1594 tr 71 M=INITIAL_L3_ECMP TSE=T SLTH=F; 1595 echo " INITIAL_L3_ECMP_GROUP"; 1596 tr 50 M=INITIAL_L3_ECMP_GROUP; 1597 tr 51 M=INITIAL_L3_ECMP_GROUP; 1598 tr 52 M=INITIAL_L3_ECMP_GROUP; 1599 tr 71 M=INITIAL_L3_ECMP_GROUP TSE=F SLTH=T; 1600 tr 71 M=INITIAL_L3_ECMP_GROUP TSE=T SLTH=T; 1601 tr 71 M=INITIAL_L3_ECMP_GROUP TSE=T SLTH=F; 1602 echo " INITIAL_PROT_GROUP_TABLE"; 1603 tr 50 M=INITIAL_PROT_GROUP_TABLE; 1604 tr 51 M=INITIAL_PROT_GROUP_TABLE; 1605 tr 52 M=INITIAL_PROT_GROUP_TABLE; 1606 tr 71 M=INITIAL_PROT_GROUP_TABLE TSE=F SLTH=T; 1607 tr 71 M=INITIAL_PROT_GROUP_TABLE TSE=T SLTH=T; 1608 tr 71 M=INITIAL_PROT_GROUP_TABLE TSE=T SLTH=F; 1609 echo " INITIAL_PROT_NHI_TABLE"; 1610 tr 50 M=INITIAL_PROT_NHI_TABLE; 1611 tr 51 M=INITIAL_PROT_NHI_TABLE; 1612 tr 52 M=INITIAL_PROT_NHI_TABLE; 1613 tr 71 M=INITIAL_PROT_NHI_TABLE TSE=F SLTH=T; 1614 tr 71 M=INITIAL_PROT_NHI_TABLE TSE=T SLTH=T; 1615 tr 71 M=INITIAL_PROT_NHI_TABLE TSE=T SLTH=F; 1616 echo " INITIAL_PROT_NHI_TABLE_1"; 1617 tr 50 M=INITIAL_PROT_NHI_TABLE_1; 1618 tr 51 M=INITIAL_PROT_NHI_TABLE_1; 1619 tr 52 M=INITIAL_PROT_NHI_TABLE_1; 1620 tr 71 M=INITIAL_PROT_NHI_TABLE_1 TSE=F SLTH=T; 1621 tr 71 M=INITIAL_PROT_NHI_TABLE_1 TSE=T SLTH=T; 1622 tr 71 M=INITIAL_PROT_NHI_TABLE_1 TSE=T SLTH=F; 1623 echo " INITIAL_PROT_NHI_TABLE_1_DMA"; 1624 tr 50 M=INITIAL_PROT_NHI_TABLE_1_DMA; 1625 tr 51 M=INITIAL_PROT_NHI_TABLE_1_DMA; 1626 tr 52 M=INITIAL_PROT_NHI_TABLE_1_DMA; 1627 tr 71 M=INITIAL_PROT_NHI_TABLE_1_DMA TSE=F SLTH=T; 1628 tr 71 M=INITIAL_PROT_NHI_TABLE_1_DMA TSE=T SLTH=T; 1629 tr 71 M=INITIAL_PROT_NHI_TABLE_1_DMA TSE=T SLTH=F; 1630 echo " IPV4_IN_IPV6_PREFIX_MATCH_TABLE"; 1631 tr 50 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE; 1632 tr 51 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE; 1633 tr 52 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE; 1634 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=F SLTH=T; 1635 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=T SLTH=T; 1636 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=T SLTH=F; 1637 echo " KNOWN_MCAST_BLOCK_MASK"; 1638 tr 50 M=KNOWN_MCAST_BLOCK_MASK; 1639 tr 51 M=KNOWN_MCAST_BLOCK_MASK; 1640 tr 52 M=KNOWN_MCAST_BLOCK_MASK; 1641 tr 71 M=KNOWN_MCAST_BLOCK_MASK TSE=F SLTH=T; 1642 tr 71 M=KNOWN_MCAST_BLOCK_MASK TSE=T SLTH=T; 1643 tr 71 M=KNOWN_MCAST_BLOCK_MASK TSE=T SLTH=F; 1644 echo " L2MC"; 1645 tr 50 M=L2MC; 1646 tr 51 M=L2MC; 1647 tr 52 M=L2MC; 1648 tr 71 M=L2MC TSE=F SLTH=T; 1649 tr 71 M=L2MC TSE=T SLTH=T; 1650 tr 71 M=L2MC TSE=T SLTH=F; 1651 echo " L2X"; 1652 tr 50 M=L2X; 1653 tr 51 M=L2X; 1654 tr 52 M=L2X; 1655 tr 71 M=L2X TSE=F SLTH=T; 1656 tr 71 M=L2X TSE=T SLTH=T; 1657 tr 71 M=L2X TSE=T SLTH=F; 1658 echo " L2_BULK_MATCH_DATA"; 1659 tr 50 M=L2_BULK_MATCH_DATA; 1660 #tr 51 M=L2_BULK_MATCH_DATA; 1661 #tr 52 M=L2_BULK_MATCH_DATA; 1662 tr 71 M=L2_BULK_MATCH_DATA TSE=F SLTH=T; 1663 tr 71 M=L2_BULK_MATCH_DATA TSE=T SLTH=T; 1664 tr 71 M=L2_BULK_MATCH_DATA TSE=T SLTH=F; 1665 echo " L2_BULK_MATCH_MASK"; 1666 tr 50 M=L2_BULK_MATCH_MASK; 1667 #tr 51 M=L2_BULK_MATCH_MASK; 1668 #tr 52 M=L2_BULK_MATCH_MASK; 1669 tr 71 M=L2_BULK_MATCH_MASK TSE=F SLTH=T; 1670 tr 71 M=L2_BULK_MATCH_MASK TSE=T SLTH=T; 1671 tr 71 M=L2_BULK_MATCH_MASK TSE=T SLTH=F; 1672 echo " L2_BULK_MATCH_VLANS_PORT_A"; 1673 tr 50 M=L2_BULK_MATCH_VLANS_PORT_A; 1674 tr 51 M=L2_BULK_MATCH_VLANS_PORT_A; 1675 tr 52 M=L2_BULK_MATCH_VLANS_PORT_A; 1676 tr 71 M=L2_BULK_MATCH_VLANS_PORT_A TSE=F SLTH=T; 1677 tr 71 M=L2_BULK_MATCH_VLANS_PORT_A TSE=T SLTH=T; 1678 tr 71 M=L2_BULK_MATCH_VLANS_PORT_A TSE=T SLTH=F; 1679 echo " L2_BULK_MATCH_VLANS_PORT_B"; 1680 tr 50 M=L2_BULK_MATCH_VLANS_PORT_B; 1681 tr 51 M=L2_BULK_MATCH_VLANS_PORT_B; 1682 tr 52 M=L2_BULK_MATCH_VLANS_PORT_B; 1683 tr 71 M=L2_BULK_MATCH_VLANS_PORT_B TSE=F SLTH=T; 1684 tr 71 M=L2_BULK_MATCH_VLANS_PORT_B TSE=T SLTH=T; 1685 tr 71 M=L2_BULK_MATCH_VLANS_PORT_B TSE=T SLTH=F; 1686 echo " L2_BULK_REPLACE_DATA"; 1687 tr 50 M=L2_BULK_REPLACE_DATA; 1688 #tr 51 M=L2_BULK_REPLACE_DATA; 1689 #tr 52 M=L2_BULK_REPLACE_DATA; 1690 tr 71 M=L2_BULK_REPLACE_DATA TSE=F SLTH=T; 1691 tr 71 M=L2_BULK_REPLACE_DATA TSE=T SLTH=T; 1692 tr 71 M=L2_BULK_REPLACE_DATA TSE=T SLTH=F; 1693 echo " L2_BULK_REPLACE_MASK"; 1694 tr 50 M=L2_BULK_REPLACE_MASK; 1695 #tr 51 M=L2_BULK_REPLACE_MASK; 1696 #tr 52 M=L2_BULK_REPLACE_MASK; 1697 tr 71 M=L2_BULK_REPLACE_MASK TSE=F SLTH=T; 1698 tr 71 M=L2_BULK_REPLACE_MASK TSE=T SLTH=T; 1699 tr 71 M=L2_BULK_REPLACE_MASK TSE=T SLTH=F; 1700 echo " L2_ENTRY_ONLY"; 1701 tr 50 M=L2_ENTRY_ONLY; 1702 tr 51 M=L2_ENTRY_ONLY; 1703 tr 52 M=L2_ENTRY_ONLY; 1704 tr 71 M=L2_ENTRY_ONLY TSE=F SLTH=T; 1705 tr 71 M=L2_ENTRY_ONLY TSE=T SLTH=T; 1706 tr 71 M=L2_ENTRY_ONLY TSE=T SLTH=F; 1707 echo " L2_ENTRY_OVERFLOW"; 1708 tr 50 M=L2_ENTRY_OVERFLOW; 1709 #tr 51 M=L2_ENTRY_OVERFLOW; 1710 #tr 52 M=L2_ENTRY_OVERFLOW; 1711 tr 71 M=L2_ENTRY_OVERFLOW TSE=F SLTH=T; 1712 tr 71 M=L2_ENTRY_OVERFLOW TSE=T SLTH=T; 1713 tr 71 M=L2_ENTRY_OVERFLOW TSE=T SLTH=F; 1714 echo " L2_HITDA_ONLY"; 1715 tr 50 M=L2_HITDA_ONLY; 1716 tr 51 M=L2_HITDA_ONLY; 1717 tr 52 M=L2_HITDA_ONLY; 1718 tr 71 M=L2_HITDA_ONLY TSE=F SLTH=T; 1719 tr 71 M=L2_HITDA_ONLY TSE=T SLTH=T; 1720 tr 71 M=L2_HITDA_ONLY TSE=T SLTH=F; 1721 echo " L2_HITSA_ONLY"; 1722 tr 50 M=L2_HITSA_ONLY; 1723 tr 51 M=L2_HITSA_ONLY; 1724 tr 52 M=L2_HITSA_ONLY; 1725 tr 71 M=L2_HITSA_ONLY TSE=F SLTH=T; 1726 tr 71 M=L2_HITSA_ONLY TSE=T SLTH=T; 1727 tr 71 M=L2_HITSA_ONLY TSE=T SLTH=F; 1728 echo " L2_MOD_FIFO"; 1729 tr 50 M=L2_MOD_FIFO; 1730 tr 51 M=L2_MOD_FIFO; 1731 tr 52 M=L2_MOD_FIFO; 1732 tr 71 M=L2_MOD_FIFO TSE=F SLTH=T; 1733 tr 71 M=L2_MOD_FIFO TSE=T SLTH=T; 1734 tr 71 M=L2_MOD_FIFO TSE=T SLTH=F; 1735 echo " L2_USER_ENTRY"; 1736 tr 50 M=L2_USER_ENTRY; 1737 tr 51 M=L2_USER_ENTRY; 1738 tr 52 M=L2_USER_ENTRY; 1739 tr 71 M=L2_USER_ENTRY TSE=F SLTH=T; 1740 tr 71 M=L2_USER_ENTRY TSE=T SLTH=T; 1741 tr 71 M=L2_USER_ENTRY TSE=T SLTH=F; 1742 echo " L2_USER_ENTRY_DATA_ONLY"; 1743 tr 50 M=L2_USER_ENTRY_DATA_ONLY; 1744 tr 51 M=L2_USER_ENTRY_DATA_ONLY; 1745 tr 52 M=L2_USER_ENTRY_DATA_ONLY; 1746 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=F SLTH=T; 1747 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=T SLTH=T; 1748 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=T SLTH=F; 1749 echo " L2_USER_ENTRY_ONLY"; 1750 tr 50 M=L2_USER_ENTRY_ONLY; 1751 tr 51 M=L2_USER_ENTRY_ONLY; 1752 tr 52 M=L2_USER_ENTRY_ONLY; 1753 tr 71 M=L2_USER_ENTRY_ONLY TSE=F SLTH=T; 1754 tr 71 M=L2_USER_ENTRY_ONLY TSE=T SLTH=T; 1755 tr 71 M=L2_USER_ENTRY_ONLY TSE=T SLTH=F; 1756 if !$?LIKE_BCM55455 \ 1757 'echo " L3_DEFIP"; \ 1758 tr 50 M=L3_DEFIP; \ 1759 tr 51 M=L3_DEFIP; \ 1760 tr 52 M=L3_DEFIP; \ 1761 tr 71 M=L3_DEFIP TSE=F SLTH=T; \ 1762 tr 71 M=L3_DEFIP TSE=T SLTH=T; \ 1763 tr 71 M=L3_DEFIP TSE=T SLTH=F; \ 1764 echo " L3_DEFIP_DATA_ONLY"; \ 1765 tr 50 M=L3_DEFIP_DATA_ONLY; \ 1766 tr 51 M=L3_DEFIP_DATA_ONLY; \ 1767 tr 52 M=L3_DEFIP_DATA_ONLY; \ 1768 tr 71 M=L3_DEFIP_DATA_ONLY TSE=F SLTH=T; \ 1769 tr 71 M=L3_DEFIP_DATA_ONLY TSE=T SLTH=T; \ 1770 tr 71 M=L3_DEFIP_DATA_ONLY TSE=T SLTH=F; \ 1771 echo " L3_DEFIP_HIT_ONLY"; \ 1772 tr 50 M=L3_DEFIP_HIT_ONLY; \ 1773 tr 51 M=L3_DEFIP_HIT_ONLY; \ 1774 tr 52 M=L3_DEFIP_HIT_ONLY; \ 1775 tr 71 M=L3_DEFIP_HIT_ONLY TSE=F SLTH=T; \ 1776 tr 71 M=L3_DEFIP_HIT_ONLY TSE=T SLTH=T; \ 1777 tr 71 M=L3_DEFIP_HIT_ONLY TSE=T SLTH=F; \ 1778 echo " L3_DEFIP_ONLY"; \ 1779 tr 50 M=L3_DEFIP_ONLY; \ 1780 tr 51 M=L3_DEFIP_ONLY; \ 1781 tr 52 M=L3_DEFIP_ONLY; \ 1782 tr 71 M=L3_DEFIP_ONLY TSE=F SLTH=T; \ 1783 tr 71 M=L3_DEFIP_ONLY TSE=T SLTH=T; \ 1784 tr 71 M=L3_DEFIP_ONLY TSE=T SLTH=F; \ 1785 kt2sanity_ecc_off.soc \ 1786 echo " L3_DEFIP_PAIR_128"; \ 1787 tr 50 M=L3_DEFIP_PAIR_128; \ 1788 tr 51 M=L3_DEFIP_PAIR_128; \ 1789 tr 52 M=L3_DEFIP_PAIR_128; \ 1790 tr 71 M=L3_DEFIP_PAIR_128 TSE=F SLTH=T; \ 1791 tr 71 M=L3_DEFIP_PAIR_128 TSE=T SLTH=T; \ 1792 tr 71 M=L3_DEFIP_PAIR_128 TSE=T SLTH=F; \ 1793 echo " L3_DEFIP_PAIR_128_DATA_ONLY"; \ 1794 tr 50 M=L3_DEFIP_PAIR_128_DATA_ONLY; \ 1795 tr 51 M=L3_DEFIP_PAIR_128_DATA_ONLY; \ 1796 tr 52 M=L3_DEFIP_PAIR_128_DATA_ONLY; \ 1797 tr 71 M=L3_DEFIP_PAIR_128_DATA_ONLY TSE=F SLTH=T; \ 1798 tr 71 M=L3_DEFIP_PAIR_128_DATA_ONLY TSE=T SLTH=T; \ 1799 tr 71 M=L3_DEFIP_PAIR_128_DATA_ONLY TSE=T SLTH=F; \ 1800 echo " L3_DEFIP_PAIR_128_HIT_ONLY"; \ 1801 tr 50 M=L3_DEFIP_PAIR_128_HIT_ONLY; \ 1802 tr 51 M=L3_DEFIP_PAIR_128_HIT_ONLY; \ 1803 tr 52 M=L3_DEFIP_PAIR_128_HIT_ONLY; \ 1804 tr 71 M=L3_DEFIP_PAIR_128_HIT_ONLY TSE=F SLTH=T; \ 1805 tr 71 M=L3_DEFIP_PAIR_128_HIT_ONLY TSE=T SLTH=T; \ 1806 tr 71 M=L3_DEFIP_PAIR_128_HIT_ONLY TSE=T SLTH=F; \ 1807 echo " L3_DEFIP_PAIR_128_ONLY"; \ 1808 tr 50 M=L3_DEFIP_PAIR_128_ONLY; \ 1809 tr 51 M=L3_DEFIP_PAIR_128_ONLY; \ 1810 tr 52 M=L3_DEFIP_PAIR_128_ONLY; \ 1811 tr 71 M=L3_DEFIP_PAIR_128_ONLY TSE=F SLTH=T; \ 1812 tr 71 M=L3_DEFIP_PAIR_128_ONLY TSE=T SLTH=T; \ 1813 tr 71 M=L3_DEFIP_PAIR_128_ONLY TSE=T SLTH=F; \ 1814 $done;' 1815 echo " L3_ECMP"; 1816 tr 50 M=L3_ECMP; 1817 tr 51 M=L3_ECMP; 1818 tr 52 M=L3_ECMP; 1819 tr 71 M=L3_ECMP TSE=F SLTH=T; 1820 tr 71 M=L3_ECMP TSE=T SLTH=T; 1821 tr 71 M=L3_ECMP TSE=T SLTH=F; 1822 echo " L3_ECMP_COUNT"; 1823 tr 50 M=L3_ECMP_COUNT; 1824 tr 51 M=L3_ECMP_COUNT; 1825 tr 52 M=L3_ECMP_COUNT; 1826 tr 71 M=L3_ECMP_COUNT TSE=F SLTH=T; 1827 tr 71 M=L3_ECMP_COUNT TSE=T SLTH=T; 1828 tr 71 M=L3_ECMP_COUNT TSE=T SLTH=F; 1829 echo " L3_ENTRY_HIT_ONLY"; 1830 tr 50 M=L3_ENTRY_HIT_ONLY; 1831 tr 51 M=L3_ENTRY_HIT_ONLY; 1832 tr 52 M=L3_ENTRY_HIT_ONLY; 1833 tr 71 M=L3_ENTRY_HIT_ONLY TSE=F SLTH=T; 1834 tr 71 M=L3_ENTRY_HIT_ONLY TSE=T SLTH=T; 1835 tr 71 M=L3_ENTRY_HIT_ONLY TSE=T SLTH=F; 1836 echo " L3_ENTRY_IPV4_MULTICAST"; 1837 tr 50 M=L3_ENTRY_IPV4_MULTICAST; 1838 tr 51 M=L3_ENTRY_IPV4_MULTICAST; 1839 tr 52 M=L3_ENTRY_IPV4_MULTICAST; 1840 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=F SLTH=T; 1841 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=T SLTH=T; 1842 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=T SLTH=F; 1843 echo " L3_ENTRY_IPV4_UNICAST"; 1844 tr 50 M=L3_ENTRY_IPV4_UNICAST; 1845 tr 51 M=L3_ENTRY_IPV4_UNICAST; 1846 tr 52 M=L3_ENTRY_IPV4_UNICAST; 1847 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=F SLTH=T; 1848 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=T SLTH=T; 1849 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=T SLTH=F; 1850 echo " L3_ENTRY_IPV6_MULTICAST"; 1851 tr 50 M=L3_ENTRY_IPV6_MULTICAST; 1852 tr 51 M=L3_ENTRY_IPV6_MULTICAST; 1853 tr 52 M=L3_ENTRY_IPV6_MULTICAST; 1854 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=F SLTH=T; 1855 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=T SLTH=T; 1856 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=T SLTH=F; 1857 echo " L3_ENTRY_IPV6_UNICAST"; 1858 tr 50 M=L3_ENTRY_IPV6_UNICAST; 1859 tr 51 M=L3_ENTRY_IPV6_UNICAST; 1860 tr 52 M=L3_ENTRY_IPV6_UNICAST; 1861 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=F SLTH=T; 1862 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=T SLTH=T; 1863 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=T SLTH=F; 1864 echo " L3_ENTRY_ONLY"; 1865 tr 50 M=L3_ENTRY_ONLY; 1866 tr 51 M=L3_ENTRY_ONLY; 1867 tr 52 M=L3_ENTRY_ONLY; 1868 tr 71 M=L3_ENTRY_ONLY TSE=F SLTH=T; 1869 tr 71 M=L3_ENTRY_ONLY TSE=T SLTH=T; 1870 tr 71 M=L3_ENTRY_ONLY TSE=T SLTH=F; 1871 echo " L3_IIF"; 1872 tr 50 M=L3_IIF; 1873 tr 51 M=L3_IIF; 1874 tr 52 M=L3_IIF; 1875 tr 71 M=L3_IIF TSE=F SLTH=T; 1876 tr 71 M=L3_IIF TSE=T SLTH=T; 1877 tr 71 M=L3_IIF TSE=T SLTH=F; 1878 echo " L3_IPMC"; 1879 tr 50 M=L3_IPMC; 1880 tr 51 M=L3_IPMC; 1881 tr 52 M=L3_IPMC; 1882 tr 71 M=L3_IPMC TSE=F SLTH=T; 1883 tr 71 M=L3_IPMC TSE=T SLTH=T; 1884 tr 71 M=L3_IPMC TSE=T SLTH=F; 1885 echo " L3_IPMC_1"; 1886 tr 50 M=L3_IPMC_1; 1887 tr 51 M=L3_IPMC_1; 1888 tr 52 M=L3_IPMC_1; 1889 tr 71 M=L3_IPMC_1 TSE=F SLTH=T; 1890 tr 71 M=L3_IPMC_1 TSE=T SLTH=T; 1891 tr 71 M=L3_IPMC_1 TSE=T SLTH=F; 1892 echo " L3_IPMC_2"; 1893 tr 50 M=L3_IPMC_2; 1894 tr 51 M=L3_IPMC_2; 1895 tr 52 M=L3_IPMC_2; 1896 tr 71 M=L3_IPMC_2 TSE=F SLTH=T; 1897 tr 71 M=L3_IPMC_2 TSE=T SLTH=T; 1898 tr 71 M=L3_IPMC_2 TSE=T SLTH=F; 1899 echo " L3_IPMC_REMAP"; 1900 tr 50 M=L3_IPMC_REMAP; 1901 tr 51 M=L3_IPMC_REMAP; 1902 tr 52 M=L3_IPMC_REMAP; 1903 tr 71 M=L3_IPMC_REMAP TSE=F SLTH=T; 1904 tr 71 M=L3_IPMC_REMAP TSE=T SLTH=T; 1905 tr 71 M=L3_IPMC_REMAP TSE=T SLTH=F; 1906 echo " L3_MTU_VALUES"; 1907 tr 50 M=L3_MTU_VALUES; 1908 tr 51 M=L3_MTU_VALUES; 1909 tr 52 M=L3_MTU_VALUES; 1910 tr 71 M=L3_MTU_VALUES TSE=F SLTH=T; 1911 tr 71 M=L3_MTU_VALUES TSE=T SLTH=T; 1912 tr 71 M=L3_MTU_VALUES TSE=T SLTH=F; 1913 echo " L3_TUNNEL"; 1914 tr 50 M=L3_TUNNEL; 1915 tr 51 M=L3_TUNNEL; 1916 tr 52 M=L3_TUNNEL; 1917 tr 71 M=L3_TUNNEL TSE=F SLTH=T; 1918 tr 71 M=L3_TUNNEL TSE=T SLTH=T; 1919 tr 71 M=L3_TUNNEL TSE=T SLTH=F; 1920 echo " L3_TUNNEL_DATA_ONLY"; 1921 tr 50 M=L3_TUNNEL_DATA_ONLY; 1922 tr 51 M=L3_TUNNEL_DATA_ONLY; 1923 tr 52 M=L3_TUNNEL_DATA_ONLY; 1924 tr 71 M=L3_TUNNEL_DATA_ONLY TSE=F SLTH=T; 1925 tr 71 M=L3_TUNNEL_DATA_ONLY TSE=T SLTH=T; 1926 tr 71 M=L3_TUNNEL_DATA_ONLY TSE=T SLTH=F; 1927 echo " L3_TUNNEL_ONLY"; 1928 tr 50 M=L3_TUNNEL_ONLY; 1929 tr 51 M=L3_TUNNEL_ONLY; 1930 tr 52 M=L3_TUNNEL_ONLY; 1931 tr 71 M=L3_TUNNEL_ONLY TSE=F SLTH=T; 1932 tr 71 M=L3_TUNNEL_ONLY TSE=T SLTH=T; 1933 tr 71 M=L3_TUNNEL_ONLY TSE=T SLTH=F; 1934 #echo " LINK_STATUS"; 1935 #tr 50 M=LINK_STATUS; 1936 #tr 51 M=LINK_STATUS; 1937 #tr 52 M=LINK_STATUS; 1938 #tr 71 M=LINK_STATUS TSE=F SLTH=T; 1939 #tr 71 M=LINK_STATUS TSE=T SLTH=T; 1940 #tr 71 M=LINK_STATUS TSE=T SLTH=F; 1941 echo " LLS_L0_CHILD_STATE1"; 1942 tr 50 M=LLS_L0_CHILD_STATE1; 1943 tr 51 M=LLS_L0_CHILD_STATE1; 1944 tr 52 M=LLS_L0_CHILD_STATE1; 1945 tr 71 M=LLS_L0_CHILD_STATE1 TSE=F SLTH=T; 1946 tr 71 M=LLS_L0_CHILD_STATE1 TSE=T SLTH=T; 1947 tr 71 M=LLS_L0_CHILD_STATE1 TSE=T SLTH=F; 1948 echo " LLS_L0_CHILD_WEIGHT_CFG_CNT"; 1949 tr 50 M=LLS_L0_CHILD_WEIGHT_CFG_CNT; 1950 tr 51 M=LLS_L0_CHILD_WEIGHT_CFG_CNT; 1951 tr 52 M=LLS_L0_CHILD_WEIGHT_CFG_CNT; 1952 tr 71 M=LLS_L0_CHILD_WEIGHT_CFG_CNT TSE=F SLTH=T; 1953 tr 71 M=LLS_L0_CHILD_WEIGHT_CFG_CNT TSE=T SLTH=T; 1954 tr 71 M=LLS_L0_CHILD_WEIGHT_CFG_CNT TSE=T SLTH=F; 1955 echo " LLS_L0_CONFIG"; 1956 tr 50 M=LLS_L0_CONFIG; 1957 tr 51 M=LLS_L0_CONFIG; 1958 tr 52 M=LLS_L0_CONFIG; 1959 tr 71 M=LLS_L0_CONFIG TSE=F SLTH=T; 1960 tr 71 M=LLS_L0_CONFIG TSE=T SLTH=T; 1961 tr 71 M=LLS_L0_CONFIG TSE=T SLTH=F; 1962 echo " LLS_L0_EF_NEXT"; 1963 tr 50 M=LLS_L0_EF_NEXT; 1964 tr 51 M=LLS_L0_EF_NEXT; 1965 tr 52 M=LLS_L0_EF_NEXT; 1966 tr 71 M=LLS_L0_EF_NEXT TSE=F SLTH=T; 1967 tr 71 M=LLS_L0_EF_NEXT TSE=T SLTH=T; 1968 tr 71 M=LLS_L0_EF_NEXT TSE=T SLTH=F; 1969 echo " LLS_L0_ERROR"; 1970 tr 50 M=LLS_L0_ERROR; 1971 tr 51 M=LLS_L0_ERROR; 1972 tr 52 M=LLS_L0_ERROR; 1973 tr 71 M=LLS_L0_ERROR TSE=F SLTH=T; 1974 tr 71 M=LLS_L0_ERROR TSE=T SLTH=T; 1975 tr 71 M=LLS_L0_ERROR TSE=T SLTH=F; 1976 echo " LLS_L0_ERROR_MIN"; 1977 tr 50 M=LLS_L0_ERROR_MIN; 1978 tr 51 M=LLS_L0_ERROR_MIN; 1979 tr 52 M=LLS_L0_ERROR_MIN; 1980 tr 71 M=LLS_L0_ERROR_MIN TSE=F SLTH=T; 1981 tr 71 M=LLS_L0_ERROR_MIN TSE=T SLTH=T; 1982 tr 71 M=LLS_L0_ERROR_MIN TSE=T SLTH=F; 1983 echo " LLS_L0_HEADS_TAILS"; 1984 tr 50 M=LLS_L0_HEADS_TAILS; 1985 tr 51 M=LLS_L0_HEADS_TAILS; 1986 tr 52 M=LLS_L0_HEADS_TAILS; 1987 tr 71 M=LLS_L0_HEADS_TAILS TSE=F SLTH=T; 1988 tr 71 M=LLS_L0_HEADS_TAILS TSE=T SLTH=T; 1989 tr 71 M=LLS_L0_HEADS_TAILS TSE=T SLTH=F; 1990 #echo " LLS_L0_MIN_BUCKET_C"; 1991 #tr 50 M=LLS_L0_MIN_BUCKET_C; 1992 #tr 51 M=LLS_L0_MIN_BUCKET_C; 1993 #tr 52 M=LLS_L0_MIN_BUCKET_C; 1994 #tr 71 M=LLS_L0_MIN_BUCKET_C TSE=F SLTH=T; 1995 #tr 71 M=LLS_L0_MIN_BUCKET_C TSE=T SLTH=T; 1996 #tr 71 M=LLS_L0_MIN_BUCKET_C TSE=T SLTH=F; 1997 echo " LLS_L0_MIN_CONFIG_C"; 1998 tr 50 M=LLS_L0_MIN_CONFIG_C; 1999 tr 51 M=LLS_L0_MIN_CONFIG_C; 2000 tr 52 M=LLS_L0_MIN_CONFIG_C; 2001 tr 71 M=LLS_L0_MIN_CONFIG_C TSE=F SLTH=T; 2002 tr 71 M=LLS_L0_MIN_CONFIG_C TSE=T SLTH=T; 2003 tr 71 M=LLS_L0_MIN_CONFIG_C TSE=T SLTH=F; 2004 echo " LLS_L0_MIN_NEXT"; 2005 tr 50 M=LLS_L0_MIN_NEXT; 2006 tr 51 M=LLS_L0_MIN_NEXT; 2007 tr 52 M=LLS_L0_MIN_NEXT; 2008 tr 71 M=LLS_L0_MIN_NEXT TSE=F SLTH=T; 2009 tr 71 M=LLS_L0_MIN_NEXT TSE=T SLTH=T; 2010 tr 71 M=LLS_L0_MIN_NEXT TSE=T SLTH=F; 2011 echo " LLS_L0_PARENT"; 2012 tr 50 M=LLS_L0_PARENT; 2013 tr 51 M=LLS_L0_PARENT; 2014 tr 52 M=LLS_L0_PARENT; 2015 tr 71 M=LLS_L0_PARENT TSE=F SLTH=T; 2016 tr 71 M=LLS_L0_PARENT TSE=T SLTH=T; 2017 tr 71 M=LLS_L0_PARENT TSE=T SLTH=F; 2018 echo " LLS_L0_PARENT_STATE"; 2019 tr 50 M=LLS_L0_PARENT_STATE; 2020 tr 51 M=LLS_L0_PARENT_STATE; 2021 tr 52 M=LLS_L0_PARENT_STATE; 2022 tr 71 M=LLS_L0_PARENT_STATE TSE=F SLTH=T; 2023 tr 71 M=LLS_L0_PARENT_STATE TSE=T SLTH=T; 2024 tr 71 M=LLS_L0_PARENT_STATE TSE=T SLTH=F; 2025 #echo " LLS_L0_SHAPER_BUCKET_C"; 2026 #tr 50 M=LLS_L0_SHAPER_BUCKET_C; 2027 #tr 51 M=LLS_L0_SHAPER_BUCKET_C; 2028 #tr 52 M=LLS_L0_SHAPER_BUCKET_C; 2029 #tr 71 M=LLS_L0_SHAPER_BUCKET_C TSE=F SLTH=T; 2030 #tr 71 M=LLS_L0_SHAPER_BUCKET_C TSE=T SLTH=T; 2031 #tr 71 M=LLS_L0_SHAPER_BUCKET_C TSE=T SLTH=F; 2032 echo " LLS_L0_SHAPER_CONFIG_C"; 2033 tr 50 M=LLS_L0_SHAPER_CONFIG_C; 2034 tr 51 M=LLS_L0_SHAPER_CONFIG_C; 2035 tr 52 M=LLS_L0_SHAPER_CONFIG_C; 2036 tr 71 M=LLS_L0_SHAPER_CONFIG_C TSE=F SLTH=T; 2037 tr 71 M=LLS_L0_SHAPER_CONFIG_C TSE=T SLTH=T; 2038 tr 71 M=LLS_L0_SHAPER_CONFIG_C TSE=T SLTH=F; 2039 echo " LLS_L0_WERR_MAX_SC"; 2040 tr 50 M=LLS_L0_WERR_MAX_SC; 2041 tr 51 M=LLS_L0_WERR_MAX_SC; 2042 tr 52 M=LLS_L0_WERR_MAX_SC; 2043 tr 71 M=LLS_L0_WERR_MAX_SC TSE=F SLTH=T; 2044 tr 71 M=LLS_L0_WERR_MAX_SC TSE=T SLTH=T; 2045 tr 71 M=LLS_L0_WERR_MAX_SC TSE=T SLTH=F; 2046 echo " LLS_L0_WERR_NEXT"; 2047 tr 50 M=LLS_L0_WERR_NEXT; 2048 tr 51 M=LLS_L0_WERR_NEXT; 2049 tr 52 M=LLS_L0_WERR_NEXT; 2050 tr 71 M=LLS_L0_WERR_NEXT TSE=F SLTH=T; 2051 tr 71 M=LLS_L0_WERR_NEXT TSE=T SLTH=T; 2052 tr 71 M=LLS_L0_WERR_NEXT TSE=T SLTH=F; 2053 echo " LLS_L0_XOFF"; 2054 #tr 50 M=LLS_L0_XOFF; 2055 #tr 51 M=LLS_L0_XOFF; 2056 #tr 52 M=LLS_L0_XOFF; 2057 #tr 71 M=LLS_L0_XOFF TSE=F SLTH=T; 2058 #tr 71 M=LLS_L0_XOFF TSE=T SLTH=T; 2059 #tr 71 M=LLS_L0_XOFF TSE=T SLTH=F; 2060 echo " LLS_L1_CHILD_STATE1"; 2061 #tr 50 M=LLS_L1_CHILD_STATE1; 2062 #tr 51 M=LLS_L1_CHILD_STATE1; 2063 #tr 52 M=LLS_L1_CHILD_STATE1; 2064 #tr 71 M=LLS_L1_CHILD_STATE1 TSE=F SLTH=T; 2065 #tr 71 M=LLS_L1_CHILD_STATE1 TSE=T SLTH=T; 2066 #tr 71 M=LLS_L1_CHILD_STATE1 TSE=T SLTH=F; 2067 echo " LLS_L1_CHILD_WEIGHT_CFG_CNT"; 2068 tr 50 M=LLS_L1_CHILD_WEIGHT_CFG_CNT; 2069 tr 51 M=LLS_L1_CHILD_WEIGHT_CFG_CNT; 2070 tr 52 M=LLS_L1_CHILD_WEIGHT_CFG_CNT; 2071 tr 71 M=LLS_L1_CHILD_WEIGHT_CFG_CNT TSE=F SLTH=T; 2072 tr 71 M=LLS_L1_CHILD_WEIGHT_CFG_CNT TSE=T SLTH=T; 2073 tr 71 M=LLS_L1_CHILD_WEIGHT_CFG_CNT TSE=T SLTH=F; 2074 echo " LLS_L1_CONFIG"; 2075 tr 50 M=LLS_L1_CONFIG; 2076 tr 51 M=LLS_L1_CONFIG; 2077 tr 52 M=LLS_L1_CONFIG; 2078 tr 71 M=LLS_L1_CONFIG TSE=F SLTH=T; 2079 tr 71 M=LLS_L1_CONFIG TSE=T SLTH=T; 2080 tr 71 M=LLS_L1_CONFIG TSE=T SLTH=F; 2081 echo " LLS_L1_EF_NEXT"; 2082 tr 50 M=LLS_L1_EF_NEXT; 2083 tr 51 M=LLS_L1_EF_NEXT; 2084 tr 52 M=LLS_L1_EF_NEXT; 2085 tr 71 M=LLS_L1_EF_NEXT TSE=F SLTH=T; 2086 tr 71 M=LLS_L1_EF_NEXT TSE=T SLTH=T; 2087 tr 71 M=LLS_L1_EF_NEXT TSE=T SLTH=F; 2088 echo " LLS_L1_ERROR"; 2089 tr 50 M=LLS_L1_ERROR; 2090 tr 51 M=LLS_L1_ERROR; 2091 tr 52 M=LLS_L1_ERROR; 2092 tr 71 M=LLS_L1_ERROR TSE=F SLTH=T; 2093 tr 71 M=LLS_L1_ERROR TSE=T SLTH=T; 2094 tr 71 M=LLS_L1_ERROR TSE=T SLTH=F; 2095 echo " LLS_L1_ERROR_MIN"; 2096 tr 50 M=LLS_L1_ERROR_MIN; 2097 tr 51 M=LLS_L1_ERROR_MIN; 2098 tr 52 M=LLS_L1_ERROR_MIN; 2099 tr 71 M=LLS_L1_ERROR_MIN TSE=F SLTH=T; 2100 tr 71 M=LLS_L1_ERROR_MIN TSE=T SLTH=T; 2101 tr 71 M=LLS_L1_ERROR_MIN TSE=T SLTH=F; 2102 echo " LLS_L1_HEADS_TAILS"; 2103 tr 50 M=LLS_L1_HEADS_TAILS; 2104 tr 51 M=LLS_L1_HEADS_TAILS; 2105 tr 52 M=LLS_L1_HEADS_TAILS; 2106 tr 71 M=LLS_L1_HEADS_TAILS TSE=F SLTH=T; 2107 tr 71 M=LLS_L1_HEADS_TAILS TSE=T SLTH=T; 2108 tr 71 M=LLS_L1_HEADS_TAILS TSE=T SLTH=F; 2109 #echo " LLS_L1_MIN_BUCKET_C"; 2110 #tr 50 M=LLS_L1_MIN_BUCKET_C; 2111 #tr 51 M=LLS_L1_MIN_BUCKET_C; 2112 #tr 52 M=LLS_L1_MIN_BUCKET_C; 2113 #tr 71 M=LLS_L1_MIN_BUCKET_C TSE=F SLTH=T; 2114 #tr 71 M=LLS_L1_MIN_BUCKET_C TSE=T SLTH=T; 2115 #tr 71 M=LLS_L1_MIN_BUCKET_C TSE=T SLTH=F; 2116 echo " LLS_L1_MIN_CONFIG_C"; 2117 tr 50 M=LLS_L1_MIN_CONFIG_C; 2118 tr 51 M=LLS_L1_MIN_CONFIG_C; 2119 tr 52 M=LLS_L1_MIN_CONFIG_C; 2120 tr 71 M=LLS_L1_MIN_CONFIG_C TSE=F SLTH=T; 2121 tr 71 M=LLS_L1_MIN_CONFIG_C TSE=T SLTH=T; 2122 tr 71 M=LLS_L1_MIN_CONFIG_C TSE=T SLTH=F; 2123 echo " LLS_L1_MIN_NEXT"; 2124 tr 50 M=LLS_L1_MIN_NEXT; 2125 tr 51 M=LLS_L1_MIN_NEXT; 2126 tr 52 M=LLS_L1_MIN_NEXT; 2127 tr 71 M=LLS_L1_MIN_NEXT TSE=F SLTH=T; 2128 tr 71 M=LLS_L1_MIN_NEXT TSE=T SLTH=T; 2129 tr 71 M=LLS_L1_MIN_NEXT TSE=T SLTH=F; 2130 echo " LLS_L1_PARENT"; 2131 tr 50 M=LLS_L1_PARENT; 2132 tr 51 M=LLS_L1_PARENT; 2133 tr 52 M=LLS_L1_PARENT; 2134 tr 71 M=LLS_L1_PARENT TSE=F SLTH=T; 2135 tr 71 M=LLS_L1_PARENT TSE=T SLTH=T; 2136 tr 71 M=LLS_L1_PARENT TSE=T SLTH=F; 2137 echo " LLS_L1_PARENT_STATE"; 2138 tr 50 M=LLS_L1_PARENT_STATE; 2139 tr 51 M=LLS_L1_PARENT_STATE; 2140 tr 52 M=LLS_L1_PARENT_STATE; 2141 tr 71 M=LLS_L1_PARENT_STATE TSE=F SLTH=T; 2142 tr 71 M=LLS_L1_PARENT_STATE TSE=T SLTH=T; 2143 tr 71 M=LLS_L1_PARENT_STATE TSE=T SLTH=F; 2144 #echo " LLS_L1_SHAPER_BUCKET_C"; 2145 #tr 50 M=LLS_L1_SHAPER_BUCKET_C; 2146 #tr 51 M=LLS_L1_SHAPER_BUCKET_C; 2147 #tr 52 M=LLS_L1_SHAPER_BUCKET_C; 2148 #tr 71 M=LLS_L1_SHAPER_BUCKET_C TSE=F SLTH=T; 2149 #tr 71 M=LLS_L1_SHAPER_BUCKET_C TSE=T SLTH=T; 2150 #tr 71 M=LLS_L1_SHAPER_BUCKET_C TSE=T SLTH=F; 2151 echo " LLS_L1_SHAPER_CONFIG_C"; 2152 tr 50 M=LLS_L1_SHAPER_CONFIG_C; 2153 tr 51 M=LLS_L1_SHAPER_CONFIG_C; 2154 tr 52 M=LLS_L1_SHAPER_CONFIG_C; 2155 tr 71 M=LLS_L1_SHAPER_CONFIG_C TSE=F SLTH=T; 2156 tr 71 M=LLS_L1_SHAPER_CONFIG_C TSE=T SLTH=T; 2157 tr 71 M=LLS_L1_SHAPER_CONFIG_C TSE=T SLTH=F; 2158 echo " LLS_L1_WERR_MAX_SC"; 2159 tr 50 M=LLS_L1_WERR_MAX_SC; 2160 tr 51 M=LLS_L1_WERR_MAX_SC; 2161 tr 52 M=LLS_L1_WERR_MAX_SC; 2162 tr 71 M=LLS_L1_WERR_MAX_SC TSE=F SLTH=T; 2163 tr 71 M=LLS_L1_WERR_MAX_SC TSE=T SLTH=T; 2164 tr 71 M=LLS_L1_WERR_MAX_SC TSE=T SLTH=F; 2165 echo " LLS_L1_WERR_NEXT"; 2166 tr 50 M=LLS_L1_WERR_NEXT; 2167 tr 51 M=LLS_L1_WERR_NEXT; 2168 tr 52 M=LLS_L1_WERR_NEXT; 2169 tr 71 M=LLS_L1_WERR_NEXT TSE=F SLTH=T; 2170 tr 71 M=LLS_L1_WERR_NEXT TSE=T SLTH=T; 2171 tr 71 M=LLS_L1_WERR_NEXT TSE=T SLTH=F; 2172 echo " LLS_L1_XOFF"; 2173 #tr 50 M=LLS_L1_XOFF; 2174 #tr 51 M=LLS_L1_XOFF; 2175 #tr 52 M=LLS_L1_XOFF; 2176 #tr 71 M=LLS_L1_XOFF TSE=F SLTH=T; 2177 #tr 71 M=LLS_L1_XOFF TSE=T SLTH=T; 2178 #tr 71 M=LLS_L1_XOFF TSE=T SLTH=F; 2179 echo " LLS_L2_ACT_MIN"; 2180 tr 50 M=LLS_L2_ACT_MIN; 2181 tr 51 M=LLS_L2_ACT_MIN; 2182 tr 52 M=LLS_L2_ACT_MIN; 2183 tr 71 M=LLS_L2_ACT_MIN TSE=F SLTH=T; 2184 tr 71 M=LLS_L2_ACT_MIN TSE=T SLTH=T; 2185 tr 71 M=LLS_L2_ACT_MIN TSE=T SLTH=F; 2186 echo " LLS_L2_ACT_SHAPER"; 2187 tr 50 M=LLS_L2_ACT_SHAPER; 2188 tr 51 M=LLS_L2_ACT_SHAPER; 2189 tr 52 M=LLS_L2_ACT_SHAPER; 2190 tr 71 M=LLS_L2_ACT_SHAPER TSE=F SLTH=T; 2191 tr 71 M=LLS_L2_ACT_SHAPER TSE=T SLTH=T; 2192 tr 71 M=LLS_L2_ACT_SHAPER TSE=T SLTH=F; 2193 echo " LLS_L2_ACT_XON"; 2194 tr 50 M=LLS_L2_ACT_XON; 2195 tr 51 M=LLS_L2_ACT_XON; 2196 tr 52 M=LLS_L2_ACT_XON; 2197 tr 71 M=LLS_L2_ACT_XON TSE=F SLTH=T; 2198 tr 71 M=LLS_L2_ACT_XON TSE=T SLTH=T; 2199 tr 71 M=LLS_L2_ACT_XON TSE=T SLTH=F; 2200 echo " LLS_L2_CHILD_STATE1"; 2201 tr 50 M=LLS_L2_CHILD_STATE1; 2202 tr 51 M=LLS_L2_CHILD_STATE1; 2203 tr 52 M=LLS_L2_CHILD_STATE1; 2204 tr 71 M=LLS_L2_CHILD_STATE1 TSE=F SLTH=T; 2205 tr 71 M=LLS_L2_CHILD_STATE1 TSE=T SLTH=T; 2206 tr 71 M=LLS_L2_CHILD_STATE1 TSE=T SLTH=F; 2207 echo " LLS_L2_CHILD_WEIGHT_CFG_CNT"; 2208 tr 50 M=LLS_L2_CHILD_WEIGHT_CFG_CNT; 2209 tr 51 M=LLS_L2_CHILD_WEIGHT_CFG_CNT; 2210 tr 52 M=LLS_L2_CHILD_WEIGHT_CFG_CNT; 2211 tr 71 M=LLS_L2_CHILD_WEIGHT_CFG_CNT TSE=F SLTH=T; 2212 tr 71 M=LLS_L2_CHILD_WEIGHT_CFG_CNT TSE=T SLTH=T; 2213 tr 71 M=LLS_L2_CHILD_WEIGHT_CFG_CNT TSE=T SLTH=F; 2214 echo " LLS_L2_EMPTY_STATE"; 2215 tr 50 M=LLS_L2_EMPTY_STATE; 2216 tr 51 M=LLS_L2_EMPTY_STATE; 2217 tr 52 M=LLS_L2_EMPTY_STATE; 2218 tr 71 M=LLS_L2_EMPTY_STATE TSE=F SLTH=T; 2219 tr 71 M=LLS_L2_EMPTY_STATE TSE=T SLTH=T; 2220 tr 71 M=LLS_L2_EMPTY_STATE TSE=T SLTH=F; 2221 echo " LLS_L2_ERROR"; 2222 tr 50 M=LLS_L2_ERROR; 2223 tr 51 M=LLS_L2_ERROR; 2224 tr 52 M=LLS_L2_ERROR; 2225 tr 71 M=LLS_L2_ERROR TSE=F SLTH=T; 2226 tr 71 M=LLS_L2_ERROR TSE=T SLTH=T; 2227 tr 71 M=LLS_L2_ERROR TSE=T SLTH=F; 2228 echo " LLS_L2_ERROR_MIN"; 2229 tr 50 M=LLS_L2_ERROR_MIN; 2230 tr 51 M=LLS_L2_ERROR_MIN; 2231 tr 52 M=LLS_L2_ERROR_MIN; 2232 tr 71 M=LLS_L2_ERROR_MIN TSE=F SLTH=T; 2233 tr 71 M=LLS_L2_ERROR_MIN TSE=T SLTH=T; 2234 tr 71 M=LLS_L2_ERROR_MIN TSE=T SLTH=F; 2235 #echo " LLS_L2_MIN_BUCKET_LOWER_C"; 2236 #tr 50 M=LLS_L2_MIN_BUCKET_LOWER_C; 2237 #tr 51 M=LLS_L2_MIN_BUCKET_LOWER_C; 2238 #tr 52 M=LLS_L2_MIN_BUCKET_LOWER_C; 2239 #tr 71 M=LLS_L2_MIN_BUCKET_LOWER_C TSE=F SLTH=T; 2240 #tr 71 M=LLS_L2_MIN_BUCKET_LOWER_C TSE=T SLTH=T; 2241 #tr 71 M=LLS_L2_MIN_BUCKET_LOWER_C TSE=T SLTH=F; 2242 #echo " LLS_L2_MIN_BUCKET_UPPER_C"; 2243 #tr 50 M=LLS_L2_MIN_BUCKET_UPPER_C; 2244 #tr 51 M=LLS_L2_MIN_BUCKET_UPPER_C; 2245 #tr 52 M=LLS_L2_MIN_BUCKET_UPPER_C; 2246 #tr 71 M=LLS_L2_MIN_BUCKET_UPPER_C TSE=F SLTH=T; 2247 #tr 71 M=LLS_L2_MIN_BUCKET_UPPER_C TSE=T SLTH=T; 2248 #tr 71 M=LLS_L2_MIN_BUCKET_UPPER_C TSE=T SLTH=F; 2249 echo " LLS_L2_MIN_CONFIG_LOWER_C"; 2250 tr 50 M=LLS_L2_MIN_CONFIG_LOWER_C; 2251 tr 51 M=LLS_L2_MIN_CONFIG_LOWER_C; 2252 tr 52 M=LLS_L2_MIN_CONFIG_LOWER_C; 2253 tr 71 M=LLS_L2_MIN_CONFIG_LOWER_C TSE=F SLTH=T; 2254 tr 71 M=LLS_L2_MIN_CONFIG_LOWER_C TSE=T SLTH=T; 2255 tr 71 M=LLS_L2_MIN_CONFIG_LOWER_C TSE=T SLTH=F; 2256 echo " LLS_L2_MIN_CONFIG_UPPER_C"; 2257 tr 50 M=LLS_L2_MIN_CONFIG_UPPER_C; 2258 tr 51 M=LLS_L2_MIN_CONFIG_UPPER_C; 2259 tr 52 M=LLS_L2_MIN_CONFIG_UPPER_C; 2260 tr 71 M=LLS_L2_MIN_CONFIG_UPPER_C TSE=F SLTH=T; 2261 tr 71 M=LLS_L2_MIN_CONFIG_UPPER_C TSE=T SLTH=T; 2262 tr 71 M=LLS_L2_MIN_CONFIG_UPPER_C TSE=T SLTH=F; 2263 echo " LLS_L2_MIN_NEXT"; 2264 tr 50 M=LLS_L2_MIN_NEXT; 2265 tr 51 M=LLS_L2_MIN_NEXT; 2266 tr 52 M=LLS_L2_MIN_NEXT; 2267 tr 71 M=LLS_L2_MIN_NEXT TSE=F SLTH=T; 2268 tr 71 M=LLS_L2_MIN_NEXT TSE=T SLTH=T; 2269 tr 71 M=LLS_L2_MIN_NEXT TSE=T SLTH=F; 2270 echo " LLS_L2_PARENT"; 2271 tr 50 M=LLS_L2_PARENT; 2272 tr 51 M=LLS_L2_PARENT; 2273 tr 52 M=LLS_L2_PARENT; 2274 tr 71 M=LLS_L2_PARENT TSE=F SLTH=T; 2275 tr 71 M=LLS_L2_PARENT TSE=T SLTH=T; 2276 tr 71 M=LLS_L2_PARENT TSE=T SLTH=F; 2277 #echo " LLS_L2_SHAPER_BUCKET_LOWER"; 2278 #tr 50 M=LLS_L2_SHAPER_BUCKET_LOWER; 2279 #tr 51 M=LLS_L2_SHAPER_BUCKET_LOWER; 2280 #tr 52 M=LLS_L2_SHAPER_BUCKET_LOWER; 2281 #tr 71 M=LLS_L2_SHAPER_BUCKET_LOWER TSE=F SLTH=T; 2282 #tr 71 M=LLS_L2_SHAPER_BUCKET_LOWER TSE=T SLTH=T; 2283 #tr 71 M=LLS_L2_SHAPER_BUCKET_LOWER TSE=T SLTH=F; 2284 #echo " LLS_L2_SHAPER_BUCKET_UPPER"; 2285 #tr 50 M=LLS_L2_SHAPER_BUCKET_UPPER; 2286 #tr 51 M=LLS_L2_SHAPER_BUCKET_UPPER; 2287 #tr 52 M=LLS_L2_SHAPER_BUCKET_UPPER; 2288 #tr 71 M=LLS_L2_SHAPER_BUCKET_UPPER TSE=F SLTH=T; 2289 #tr 71 M=LLS_L2_SHAPER_BUCKET_UPPER TSE=T SLTH=T; 2290 #tr 71 M=LLS_L2_SHAPER_BUCKET_UPPER TSE=T SLTH=F; 2291 echo " LLS_L2_SHAPER_CONFIG_LOWER"; 2292 tr 50 M=LLS_L2_SHAPER_CONFIG_LOWER; 2293 tr 51 M=LLS_L2_SHAPER_CONFIG_LOWER; 2294 tr 52 M=LLS_L2_SHAPER_CONFIG_LOWER; 2295 tr 71 M=LLS_L2_SHAPER_CONFIG_LOWER TSE=F SLTH=T; 2296 tr 71 M=LLS_L2_SHAPER_CONFIG_LOWER TSE=T SLTH=T; 2297 tr 71 M=LLS_L2_SHAPER_CONFIG_LOWER TSE=T SLTH=F; 2298 echo " LLS_L2_SHAPER_CONFIG_UPPER"; 2299 tr 50 M=LLS_L2_SHAPER_CONFIG_UPPER; 2300 tr 51 M=LLS_L2_SHAPER_CONFIG_UPPER; 2301 tr 52 M=LLS_L2_SHAPER_CONFIG_UPPER; 2302 tr 71 M=LLS_L2_SHAPER_CONFIG_UPPER TSE=F SLTH=T; 2303 tr 71 M=LLS_L2_SHAPER_CONFIG_UPPER TSE=T SLTH=T; 2304 tr 71 M=LLS_L2_SHAPER_CONFIG_UPPER TSE=T SLTH=F; 2305 echo " LLS_L2_WERR_NEXT"; 2306 tr 50 M=LLS_L2_WERR_NEXT; 2307 tr 51 M=LLS_L2_WERR_NEXT; 2308 tr 52 M=LLS_L2_WERR_NEXT; 2309 tr 71 M=LLS_L2_WERR_NEXT TSE=F SLTH=T; 2310 tr 71 M=LLS_L2_WERR_NEXT TSE=T SLTH=T; 2311 tr 71 M=LLS_L2_WERR_NEXT TSE=T SLTH=F; 2312 #echo " LLS_L2_XOFF"; 2313 #tr 50 M=LLS_L2_XOFF; 2314 #tr 51 M=LLS_L2_XOFF; 2315 #tr 52 M=LLS_L2_XOFF; 2316 #tr 71 M=LLS_L2_XOFF TSE=F SLTH=T; 2317 #tr 71 M=LLS_L2_XOFF TSE=T SLTH=T; 2318 #tr 71 M=LLS_L2_XOFF TSE=T SLTH=F; 2319 echo " LLS_PORT_CONFIG"; 2320 tr 50 M=LLS_PORT_CONFIG; 2321 tr 51 M=LLS_PORT_CONFIG; 2322 tr 52 M=LLS_PORT_CONFIG; 2323 tr 71 M=LLS_PORT_CONFIG TSE=F SLTH=T; 2324 tr 71 M=LLS_PORT_CONFIG TSE=T SLTH=T; 2325 tr 71 M=LLS_PORT_CONFIG TSE=T SLTH=F; 2326 echo " LLS_PORT_ERROR"; 2327 tr 50 M=LLS_PORT_ERROR; 2328 tr 51 M=LLS_PORT_ERROR; 2329 tr 52 M=LLS_PORT_ERROR; 2330 tr 71 M=LLS_PORT_ERROR TSE=F SLTH=T; 2331 tr 71 M=LLS_PORT_ERROR TSE=T SLTH=T; 2332 tr 71 M=LLS_PORT_ERROR TSE=T SLTH=F; 2333 echo " LLS_PORT_HEADS"; 2334 tr 50 M=LLS_PORT_HEADS; 2335 tr 51 M=LLS_PORT_HEADS; 2336 tr 52 M=LLS_PORT_HEADS; 2337 tr 71 M=LLS_PORT_HEADS TSE=F SLTH=T; 2338 tr 71 M=LLS_PORT_HEADS TSE=T SLTH=T; 2339 tr 71 M=LLS_PORT_HEADS TSE=T SLTH=F; 2340 echo " LLS_PORT_PARENT_STATE"; 2341 tr 50 M=LLS_PORT_PARENT_STATE; 2342 tr 51 M=LLS_PORT_PARENT_STATE; 2343 tr 52 M=LLS_PORT_PARENT_STATE; 2344 tr 71 M=LLS_PORT_PARENT_STATE TSE=F SLTH=T; 2345 tr 71 M=LLS_PORT_PARENT_STATE TSE=T SLTH=T; 2346 tr 71 M=LLS_PORT_PARENT_STATE TSE=T SLTH=F; 2347 #echo " LLS_PORT_SHAPER_BUCKET_C"; 2348 #tr 50 M=LLS_PORT_SHAPER_BUCKET_C; 2349 #tr 51 M=LLS_PORT_SHAPER_BUCKET_C; 2350 #tr 52 M=LLS_PORT_SHAPER_BUCKET_C; 2351 #tr 71 M=LLS_PORT_SHAPER_BUCKET_C TSE=F SLTH=T; 2352 #tr 71 M=LLS_PORT_SHAPER_BUCKET_C TSE=T SLTH=T; 2353 #tr 71 M=LLS_PORT_SHAPER_BUCKET_C TSE=T SLTH=F; 2354 echo " LLS_PORT_SHAPER_CONFIG_C"; 2355 tr 50 M=LLS_PORT_SHAPER_CONFIG_C EccAsData=0; 2356 tr 51 M=LLS_PORT_SHAPER_CONFIG_C EccAsData=0; 2357 tr 52 M=LLS_PORT_SHAPER_CONFIG_C EccAsData=0; 2358 tr 71 M=LLS_PORT_SHAPER_CONFIG_C TSE=F SLTH=T EccAsData=0; 2359 tr 71 M=LLS_PORT_SHAPER_CONFIG_C TSE=T SLTH=T EccAsData=0; 2360 tr 71 M=LLS_PORT_SHAPER_CONFIG_C TSE=T SLTH=F EccAsData=0; 2361 echo " LLS_PORT_TAILS"; 2362 tr 50 M=LLS_PORT_TAILS; 2363 tr 51 M=LLS_PORT_TAILS; 2364 tr 52 M=LLS_PORT_TAILS; 2365 tr 71 M=LLS_PORT_TAILS TSE=F SLTH=T; 2366 tr 71 M=LLS_PORT_TAILS TSE=T SLTH=T; 2367 tr 71 M=LLS_PORT_TAILS TSE=T SLTH=F; 2368 echo " LLS_PORT_TDM"; 2369 tr 50 M=LLS_PORT_TDM EccAsData=0; 2370 tr 51 M=LLS_PORT_TDM EccAsData=0; 2371 tr 52 M=LLS_PORT_TDM EccAsData=0; 2372 tr 71 M=LLS_PORT_TDM TSE=F SLTH=T EccAsData=0; 2373 tr 71 M=LLS_PORT_TDM TSE=T SLTH=T EccAsData=0; 2374 tr 71 M=LLS_PORT_TDM TSE=T SLTH=F EccAsData=0; 2375 echo " LLS_PORT_WERR_MAX_SC"; 2376 tr 50 M=LLS_PORT_WERR_MAX_SC EccAsData=0; 2377 tr 51 M=LLS_PORT_WERR_MAX_SC EccAsData=0; 2378 tr 52 M=LLS_PORT_WERR_MAX_SC EccAsData=0; 2379 tr 71 M=LLS_PORT_WERR_MAX_SC TSE=F SLTH=T EccAsData=0; 2380 tr 71 M=LLS_PORT_WERR_MAX_SC TSE=T SLTH=T EccAsData=0; 2381 tr 71 M=LLS_PORT_WERR_MAX_SC TSE=T SLTH=F EccAsData=0; 2382 echo " LLS_PORT_XOFF"; 2383 tr 50 M=LLS_PORT_XOFF; 2384 #tr 51 M=LLS_PORT_XOFF; 2385 #tr 52 M=LLS_PORT_XOFF; 2386 tr 71 M=LLS_PORT_XOFF TSE=F SLTH=T; 2387 tr 71 M=LLS_PORT_XOFF TSE=T SLTH=T; 2388 tr 71 M=LLS_PORT_XOFF TSE=T SLTH=F; 2389 echo " LLS_S0_ERROR"; 2390 tr 50 M=LLS_S0_ERROR; 2391 tr 51 M=LLS_S0_ERROR; 2392 tr 52 M=LLS_S0_ERROR; 2393 tr 71 M=LLS_S0_ERROR TSE=F SLTH=T; 2394 tr 71 M=LLS_S0_ERROR TSE=T SLTH=T; 2395 tr 71 M=LLS_S0_ERROR TSE=T SLTH=F; 2396 #echo " LLS_S0_SHAPER_BUCKET_C"; 2397 #tr 50 M=LLS_S0_SHAPER_BUCKET_C; 2398 #tr 51 M=LLS_S0_SHAPER_BUCKET_C; 2399 #tr 52 M=LLS_S0_SHAPER_BUCKET_C; 2400 #tr 71 M=LLS_S0_SHAPER_BUCKET_C TSE=F SLTH=T; 2401 #tr 71 M=LLS_S0_SHAPER_BUCKET_C TSE=T SLTH=T; 2402 #tr 71 M=LLS_S0_SHAPER_BUCKET_C TSE=T SLTH=F; 2403 echo " LLS_S0_SHAPER_CONFIG_C"; 2404 tr 50 M=LLS_S0_SHAPER_CONFIG_C EccAsData=0; 2405 tr 51 M=LLS_S0_SHAPER_CONFIG_C EccAsData=0; 2406 tr 52 M=LLS_S0_SHAPER_CONFIG_C EccAsData=0; 2407 tr 71 M=LLS_S0_SHAPER_CONFIG_C TSE=F SLTH=T EccAsData=0; 2408 tr 71 M=LLS_S0_SHAPER_CONFIG_C TSE=T SLTH=T EccAsData=0; 2409 tr 71 M=LLS_S0_SHAPER_CONFIG_C TSE=T SLTH=F EccAsData=0; 2410 echo " LLS_S1_CONFIG"; 2411 tr 50 M=LLS_S1_CONFIG; 2412 tr 51 M=LLS_S1_CONFIG; 2413 tr 52 M=LLS_S1_CONFIG; 2414 tr 71 M=LLS_S1_CONFIG TSE=F SLTH=T; 2415 tr 71 M=LLS_S1_CONFIG TSE=T SLTH=T; 2416 tr 71 M=LLS_S1_CONFIG TSE=T SLTH=F; 2417 echo " LLS_S1_ERROR"; 2418 tr 50 M=LLS_S1_ERROR; 2419 tr 51 M=LLS_S1_ERROR; 2420 tr 52 M=LLS_S1_ERROR; 2421 tr 71 M=LLS_S1_ERROR TSE=F SLTH=T; 2422 tr 71 M=LLS_S1_ERROR TSE=T SLTH=T; 2423 tr 71 M=LLS_S1_ERROR TSE=T SLTH=F; 2424 echo " LLS_S1_HEADS"; 2425 tr 50 M=LLS_S1_HEADS; 2426 tr 51 M=LLS_S1_HEADS; 2427 tr 52 M=LLS_S1_HEADS; 2428 tr 71 M=LLS_S1_HEADS TSE=F SLTH=T; 2429 tr 71 M=LLS_S1_HEADS TSE=T SLTH=T; 2430 tr 71 M=LLS_S1_HEADS TSE=T SLTH=F; 2431 echo " LLS_S1_PARENT_STATE"; 2432 tr 50 M=LLS_S1_PARENT_STATE; 2433 tr 51 M=LLS_S1_PARENT_STATE; 2434 tr 52 M=LLS_S1_PARENT_STATE; 2435 tr 71 M=LLS_S1_PARENT_STATE TSE=F SLTH=T; 2436 tr 71 M=LLS_S1_PARENT_STATE TSE=T SLTH=T; 2437 tr 71 M=LLS_S1_PARENT_STATE TSE=T SLTH=F; 2438 #echo " LLS_S1_SHAPER_BUCKET_C"; 2439 #tr 50 M=LLS_S1_SHAPER_BUCKET_C; 2440 #tr 51 M=LLS_S1_SHAPER_BUCKET_C; 2441 #tr 52 M=LLS_S1_SHAPER_BUCKET_C; 2442 #tr 71 M=LLS_S1_SHAPER_BUCKET_C TSE=F SLTH=T; 2443 #tr 71 M=LLS_S1_SHAPER_BUCKET_C TSE=T SLTH=T; 2444 #tr 71 M=LLS_S1_SHAPER_BUCKET_C TSE=T SLTH=F; 2445 echo " LLS_S1_SHAPER_CONFIG_C"; 2446 tr 50 M=LLS_S1_SHAPER_CONFIG_C EccAsData=0; 2447 tr 51 M=LLS_S1_SHAPER_CONFIG_C EccAsData=0; 2448 tr 52 M=LLS_S1_SHAPER_CONFIG_C EccAsData=0; 2449 tr 71 M=LLS_S1_SHAPER_CONFIG_C TSE=F SLTH=T EccAsData=0; 2450 tr 71 M=LLS_S1_SHAPER_CONFIG_C TSE=T SLTH=T EccAsData=0; 2451 tr 71 M=LLS_S1_SHAPER_CONFIG_C TSE=T SLTH=F EccAsData=0; 2452 echo " LLS_S1_TAILS"; 2453 tr 50 M=LLS_S1_TAILS EccAsData=0; 2454 tr 51 M=LLS_S1_TAILS EccAsData=0; 2455 tr 52 M=LLS_S1_TAILS EccAsData=0; 2456 tr 71 M=LLS_S1_TAILS TSE=F SLTH=T EccAsData=0; 2457 tr 71 M=LLS_S1_TAILS TSE=T SLTH=T EccAsData=0; 2458 tr 71 M=LLS_S1_TAILS TSE=T SLTH=F EccAsData=0; 2459 echo " LMEP"; 2460 tr 50 M=LMEP; 2461 tr 51 M=LMEP; 2462 tr 52 M=LMEP; 2463 tr 71 M=LMEP TSE=F SLTH=T; 2464 tr 71 M=LMEP TSE=T SLTH=T; 2465 tr 71 M=LMEP TSE=T SLTH=F; 2466 echo " LMEP_1"; 2467 tr 50 M=LMEP_1; 2468 tr 51 M=LMEP_1; 2469 tr 52 M=LMEP_1; 2470 tr 71 M=LMEP_1 TSE=F SLTH=T; 2471 tr 71 M=LMEP_1 TSE=T SLTH=T; 2472 tr 71 M=LMEP_1 TSE=T SLTH=F; 2473 echo " LM_COUNTER_CONTROL"; 2474 tr 50 M=LM_COUNTER_CONTROL; 2475 tr 51 M=LM_COUNTER_CONTROL; 2476 tr 52 M=LM_COUNTER_CONTROL; 2477 tr 71 M=LM_COUNTER_CONTROL TSE=F SLTH=T; 2478 tr 71 M=LM_COUNTER_CONTROL TSE=T SLTH=T; 2479 tr 71 M=LM_COUNTER_CONTROL TSE=T SLTH=F; 2480 echo " LOCAL_SW_DISABLE_DEFAULT_PBM"; 2481 tr 50 M=LOCAL_SW_DISABLE_DEFAULT_PBM; 2482 tr 51 M=LOCAL_SW_DISABLE_DEFAULT_PBM; 2483 tr 52 M=LOCAL_SW_DISABLE_DEFAULT_PBM; 2484 tr 71 M=LOCAL_SW_DISABLE_DEFAULT_PBM TSE=F SLTH=T; 2485 tr 71 M=LOCAL_SW_DISABLE_DEFAULT_PBM TSE=T SLTH=T; 2486 tr 71 M=LOCAL_SW_DISABLE_DEFAULT_PBM TSE=T SLTH=F; 2487 echo " LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR"; 2488 tr 50 M=LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR; 2489 tr 51 M=LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR; 2490 tr 52 M=LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR; 2491 tr 71 M=LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR TSE=F SLTH=T; 2492 tr 71 M=LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR TSE=T SLTH=T; 2493 tr 71 M=LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR TSE=T SLTH=F; 2494 echo " LPORT_TAB"; 2495 tr 50 M=LPORT_TAB; 2496 tr 51 M=LPORT_TAB; 2497 tr 52 M=LPORT_TAB; 2498 tr 71 M=LPORT_TAB TSE=F SLTH=T; 2499 tr 71 M=LPORT_TAB TSE=T SLTH=T; 2500 tr 71 M=LPORT_TAB TSE=T SLTH=F; 2501 echo " MAC_BLOCK"; 2502 tr 50 M=MAC_BLOCK; 2503 tr 51 M=MAC_BLOCK; 2504 tr 52 M=MAC_BLOCK; 2505 tr 71 M=MAC_BLOCK TSE=F SLTH=T; 2506 tr 71 M=MAC_BLOCK TSE=T SLTH=T; 2507 tr 71 M=MAC_BLOCK TSE=T SLTH=F; 2508 echo " MAID_REDUCTION"; 2509 tr 50 M=MAID_REDUCTION; 2510 tr 51 M=MAID_REDUCTION; 2511 tr 52 M=MAID_REDUCTION; 2512 tr 71 M=MAID_REDUCTION TSE=F SLTH=T; 2513 tr 71 M=MAID_REDUCTION TSE=T SLTH=T; 2514 tr 71 M=MAID_REDUCTION TSE=T SLTH=F; 2515 echo " MA_INDEX"; 2516 tr 50 M=MA_INDEX; 2517 tr 51 M=MA_INDEX; 2518 tr 52 M=MA_INDEX; 2519 tr 71 M=MA_INDEX TSE=F SLTH=T; 2520 tr 71 M=MA_INDEX TSE=T SLTH=T; 2521 tr 71 M=MA_INDEX TSE=T SLTH=F; 2522 echo " MA_STATE"; 2523 tr 50 M=MA_STATE; 2524 tr 51 M=MA_STATE; 2525 tr 52 M=MA_STATE; 2526 tr 71 M=MA_STATE TSE=F SLTH=T; 2527 tr 71 M=MA_STATE TSE=T SLTH=T; 2528 tr 71 M=MA_STATE TSE=T SLTH=F; 2529 echo " MIRROR_CONTROL"; 2530 tr 50 M=MIRROR_CONTROL; 2531 tr 51 M=MIRROR_CONTROL; 2532 tr 52 M=MIRROR_CONTROL; 2533 tr 71 M=MIRROR_CONTROL TSE=F SLTH=T; 2534 tr 71 M=MIRROR_CONTROL TSE=T SLTH=T; 2535 tr 71 M=MIRROR_CONTROL TSE=T SLTH=F; 2536 #echo " MMU_ADM_QUEUE_DB"; 2537 #tr 50 M=MMU_ADM_QUEUE_DB; 2538 #tr 51 M=MMU_ADM_QUEUE_DB; 2539 #tr 52 M=MMU_ADM_QUEUE_DB; 2540 #tr 71 M=MMU_ADM_QUEUE_DB TSE=F SLTH=T; 2541 #tr 71 M=MMU_ADM_QUEUE_DB TSE=T SLTH=T; 2542 #tr 71 M=MMU_ADM_QUEUE_DB TSE=T SLTH=F; 2543 echo " MMU_ADM_SRC_CTXT_DB"; 2544 tr 50 M=MMU_ADM_SRC_CTXT_DB EccAsData=0; 2545 tr 51 M=MMU_ADM_SRC_CTXT_DB EccAsData=0; 2546 tr 52 M=MMU_ADM_SRC_CTXT_DB EccAsData=0; 2547 tr 71 M=MMU_ADM_SRC_CTXT_DB TSE=F SLTH=T EccAsData=0; 2548 tr 71 M=MMU_ADM_SRC_CTXT_DB TSE=T SLTH=T EccAsData=0; 2549 tr 71 M=MMU_ADM_SRC_CTXT_DB TSE=T SLTH=F EccAsData=0; 2550 if !$?LIKE_BCM56456 \ 2551 'echo " MMU_AGING_CTR_EXT"; \ 2552 tr 50 M=MMU_AGING_CTR_EXT; \ 2553 tr 51 M=MMU_AGING_CTR_EXT; \ 2554 tr 52 M=MMU_AGING_CTR_EXT; \ 2555 tr 71 M=MMU_AGING_CTR_EXT TSE=F SLTH=T; \ 2556 tr 71 M=MMU_AGING_CTR_EXT TSE=T SLTH=T; \ 2557 tr 71 M=MMU_AGING_CTR_EXT TSE=T SLTH=F; \ 2558 $done;' 2559 echo " MMU_AGING_CTR_INT"; 2560 tr 50 M=MMU_AGING_CTR_INT; 2561 tr 51 M=MMU_AGING_CTR_INT; 2562 tr 52 M=MMU_AGING_CTR_INT; 2563 tr 71 M=MMU_AGING_CTR_INT TSE=F SLTH=T; 2564 tr 71 M=MMU_AGING_CTR_INT TSE=T SLTH=T; 2565 tr 71 M=MMU_AGING_CTR_INT TSE=T SLTH=F; 2566 if !$?LIKE_BCM56456 \ 2567 'echo " MMU_AGING_EXP_EXT"; \ 2568 tr 50 M=MMU_AGING_EXP_EXT; \ 2569 tr 51 M=MMU_AGING_EXP_EXT; \ 2570 tr 52 M=MMU_AGING_EXP_EXT; \ 2571 tr 71 M=MMU_AGING_EXP_EXT TSE=F SLTH=T; \ 2572 tr 71 M=MMU_AGING_EXP_EXT TSE=T SLTH=T; \ 2573 tr 71 M=MMU_AGING_EXP_EXT TSE=T SLTH=F; \ 2574 $done;' 2575 echo " MMU_AGING_EXP_INT"; 2576 tr 50 M=MMU_AGING_EXP_INT; 2577 tr 51 M=MMU_AGING_EXP_INT; 2578 tr 52 M=MMU_AGING_EXP_INT; 2579 tr 71 M=MMU_AGING_EXP_INT TSE=F SLTH=T; 2580 tr 71 M=MMU_AGING_EXP_INT TSE=T SLTH=T; 2581 tr 71 M=MMU_AGING_EXP_INT TSE=T SLTH=F; 2582 echo " MMU_AGING_LMT_EXT"; 2583 tr 50 M=MMU_AGING_LMT_EXT; 2584 tr 51 M=MMU_AGING_LMT_EXT; 2585 tr 52 M=MMU_AGING_LMT_EXT; 2586 tr 71 M=MMU_AGING_LMT_EXT TSE=F SLTH=T; 2587 tr 71 M=MMU_AGING_LMT_EXT TSE=T SLTH=T; 2588 tr 71 M=MMU_AGING_LMT_EXT TSE=T SLTH=F; 2589 echo " MMU_AGING_LMT_INT"; 2590 tr 50 M=MMU_AGING_LMT_INT; 2591 tr 51 M=MMU_AGING_LMT_INT; 2592 tr 52 M=MMU_AGING_LMT_INT; 2593 tr 71 M=MMU_AGING_LMT_INT TSE=F SLTH=T; 2594 tr 71 M=MMU_AGING_LMT_INT TSE=T SLTH=T; 2595 tr 71 M=MMU_AGING_LMT_INT TSE=T SLTH=F; 2596 echo " MMU_CBPI_0"; 2597 tr 50 M=MMU_CBPI_0; 2598 tr 51 M=MMU_CBPI_0; 2599 tr 52 M=MMU_CBPI_0; 2600 tr 71 M=MMU_CBPI_0 TSE=F SLTH=T; 2601 tr 71 M=MMU_CBPI_0 TSE=T SLTH=T; 2602 tr 71 M=MMU_CBPI_0 TSE=T SLTH=F; 2603 echo " MMU_CBPI_1"; 2604 tr 50 M=MMU_CBPI_1; 2605 tr 51 M=MMU_CBPI_1; 2606 tr 52 M=MMU_CBPI_1; 2607 tr 71 M=MMU_CBPI_1 TSE=F SLTH=T; 2608 tr 71 M=MMU_CBPI_1 TSE=T SLTH=T; 2609 tr 71 M=MMU_CBPI_1 TSE=T SLTH=F; 2610 echo " MMU_CBPI_10"; 2611 tr 50 M=MMU_CBPI_10; 2612 tr 51 M=MMU_CBPI_10; 2613 tr 52 M=MMU_CBPI_10; 2614 tr 71 M=MMU_CBPI_10 TSE=F SLTH=T; 2615 tr 71 M=MMU_CBPI_10 TSE=T SLTH=T; 2616 tr 71 M=MMU_CBPI_10 TSE=T SLTH=F; 2617 echo " MMU_CBPI_11"; 2618 tr 50 M=MMU_CBPI_11; 2619 tr 51 M=MMU_CBPI_11; 2620 tr 52 M=MMU_CBPI_11; 2621 tr 71 M=MMU_CBPI_11 TSE=F SLTH=T; 2622 tr 71 M=MMU_CBPI_11 TSE=T SLTH=T; 2623 tr 71 M=MMU_CBPI_11 TSE=T SLTH=F; 2624 echo " MMU_CBPI_2"; 2625 tr 50 M=MMU_CBPI_2; 2626 tr 51 M=MMU_CBPI_2; 2627 tr 52 M=MMU_CBPI_2; 2628 tr 71 M=MMU_CBPI_2 TSE=F SLTH=T; 2629 tr 71 M=MMU_CBPI_2 TSE=T SLTH=T; 2630 tr 71 M=MMU_CBPI_2 TSE=T SLTH=F; 2631 echo " MMU_CBPI_3"; 2632 tr 50 M=MMU_CBPI_3; 2633 tr 51 M=MMU_CBPI_3; 2634 tr 52 M=MMU_CBPI_3; 2635 tr 71 M=MMU_CBPI_3 TSE=F SLTH=T; 2636 tr 71 M=MMU_CBPI_3 TSE=T SLTH=T; 2637 tr 71 M=MMU_CBPI_3 TSE=T SLTH=F; 2638 echo " MMU_CBPI_4"; 2639 tr 50 M=MMU_CBPI_4; 2640 tr 51 M=MMU_CBPI_4; 2641 tr 52 M=MMU_CBPI_4; 2642 tr 71 M=MMU_CBPI_4 TSE=F SLTH=T; 2643 tr 71 M=MMU_CBPI_4 TSE=T SLTH=T; 2644 tr 71 M=MMU_CBPI_4 TSE=T SLTH=F; 2645 echo " MMU_CBPI_5"; 2646 tr 50 M=MMU_CBPI_5; 2647 tr 51 M=MMU_CBPI_5; 2648 tr 52 M=MMU_CBPI_5; 2649 tr 71 M=MMU_CBPI_5 TSE=F SLTH=T; 2650 tr 71 M=MMU_CBPI_5 TSE=T SLTH=T; 2651 tr 71 M=MMU_CBPI_5 TSE=T SLTH=F; 2652 echo " MMU_CBPI_6"; 2653 tr 50 M=MMU_CBPI_6; 2654 tr 51 M=MMU_CBPI_6; 2655 tr 52 M=MMU_CBPI_6; 2656 tr 71 M=MMU_CBPI_6 TSE=F SLTH=T; 2657 tr 71 M=MMU_CBPI_6 TSE=T SLTH=T; 2658 tr 71 M=MMU_CBPI_6 TSE=T SLTH=F; 2659 echo " MMU_CBPI_7"; 2660 tr 50 M=MMU_CBPI_7; 2661 tr 51 M=MMU_CBPI_7; 2662 tr 52 M=MMU_CBPI_7; 2663 tr 71 M=MMU_CBPI_7 TSE=F SLTH=T; 2664 tr 71 M=MMU_CBPI_7 TSE=T SLTH=T; 2665 tr 71 M=MMU_CBPI_7 TSE=T SLTH=F; 2666 echo " MMU_CBPI_8"; 2667 tr 50 M=MMU_CBPI_8; 2668 tr 51 M=MMU_CBPI_8; 2669 tr 52 M=MMU_CBPI_8; 2670 tr 71 M=MMU_CBPI_8 TSE=F SLTH=T; 2671 tr 71 M=MMU_CBPI_8 TSE=T SLTH=T; 2672 tr 71 M=MMU_CBPI_8 TSE=T SLTH=F; 2673 echo " MMU_CBPI_9"; 2674 tr 50 M=MMU_CBPI_9; 2675 tr 51 M=MMU_CBPI_9; 2676 tr 52 M=MMU_CBPI_9; 2677 tr 71 M=MMU_CBPI_9 TSE=F SLTH=T; 2678 tr 71 M=MMU_CBPI_9 TSE=T SLTH=T; 2679 tr 71 M=MMU_CBPI_9 TSE=T SLTH=F; 2680 if !$?LIKE_BCM56456 \ 2681 'echo " MMU_CCPE_MEM"; \ 2682 tr 50 M=MMU_CCPE_MEM; \ 2683 tr 51 M=MMU_CCPE_MEM; \ 2684 tr 52 M=MMU_CCPE_MEM; \ 2685 tr 71 M=MMU_CCPE_MEM TSE=F SLTH=T; \ 2686 tr 71 M=MMU_CCPE_MEM TSE=T SLTH=T; \ 2687 tr 71 M=MMU_CCPE_MEM TSE=T SLTH=F; \ 2688 $done;' 2689 echo " MMU_CCPI_MEM"; 2690 tr 50 M=MMU_CCPI_MEM; 2691 tr 51 M=MMU_CCPI_MEM; 2692 tr 52 M=MMU_CCPI_MEM; 2693 tr 71 M=MMU_CCPI_MEM TSE=F SLTH=T; 2694 tr 71 M=MMU_CCPI_MEM TSE=T SLTH=T; 2695 tr 71 M=MMU_CCPI_MEM TSE=T SLTH=F; 2696 #echo " MMU_CELLLINKE"; 2697 #tr 50 M=MMU_CELLLINKE; 2698 #tr 51 M=MMU_CELLLINKE; 2699 #tr 52 M=MMU_CELLLINKE; 2700 #tr 71 M=MMU_CELLLINKE TSE=F SLTH=T; 2701 #tr 71 M=MMU_CELLLINKE TSE=T SLTH=T; 2702 #tr 71 M=MMU_CELLLINKE TSE=T SLTH=F; 2703 echo " MMU_CELLLINKI"; 2704 tr 50 M=MMU_CELLLINKI; 2705 tr 51 M=MMU_CELLLINKI; 2706 tr 52 M=MMU_CELLLINKI; 2707 tr 71 M=MMU_CELLLINKI TSE=F SLTH=T; 2708 tr 71 M=MMU_CELLLINKI TSE=T SLTH=T; 2709 tr 71 M=MMU_CELLLINKI TSE=T SLTH=F; 2710 echo " MMU_CFAPE_BITMAP"; 2711 tr 50 M=MMU_CFAPE_BITMAP; 2712 tr 51 M=MMU_CFAPE_BITMAP; 2713 tr 52 M=MMU_CFAPE_BITMAP; 2714 tr 71 M=MMU_CFAPE_BITMAP TSE=F SLTH=T; 2715 tr 71 M=MMU_CFAPE_BITMAP TSE=T SLTH=T; 2716 tr 71 M=MMU_CFAPE_BITMAP TSE=T SLTH=F; 2717 echo " MMU_CFAPE_STACK"; 2718 tr 50 M=MMU_CFAPE_STACK; 2719 tr 51 M=MMU_CFAPE_STACK; 2720 tr 52 M=MMU_CFAPE_STACK; 2721 tr 71 M=MMU_CFAPE_STACK TSE=F SLTH=T; 2722 tr 71 M=MMU_CFAPE_STACK TSE=T SLTH=T; 2723 tr 71 M=MMU_CFAPE_STACK TSE=T SLTH=F; 2724 echo " MMU_CFAPI_BITMAP"; 2725 tr 50 M=MMU_CFAPI_BITMAP; 2726 tr 51 M=MMU_CFAPI_BITMAP; 2727 tr 52 M=MMU_CFAPI_BITMAP; 2728 tr 71 M=MMU_CFAPI_BITMAP TSE=F SLTH=T; 2729 tr 71 M=MMU_CFAPI_BITMAP TSE=T SLTH=T; 2730 tr 71 M=MMU_CFAPI_BITMAP TSE=T SLTH=F; 2731 echo " MMU_CFAPI_STACK"; 2732 tr 50 M=MMU_CFAPI_STACK; 2733 tr 51 M=MMU_CFAPI_STACK; 2734 tr 52 M=MMU_CFAPI_STACK; 2735 tr 71 M=MMU_CFAPI_STACK TSE=F SLTH=T; 2736 tr 71 M=MMU_CFAPI_STACK TSE=T SLTH=T; 2737 tr 71 M=MMU_CFAPI_STACK TSE=T SLTH=F; 2738 echo " MMU_CHFC_SYSPORT_MAPPING"; 2739 tr 50 M=MMU_CHFC_SYSPORT_MAPPING; 2740 tr 51 M=MMU_CHFC_SYSPORT_MAPPING; 2741 tr 52 M=MMU_CHFC_SYSPORT_MAPPING; 2742 tr 71 M=MMU_CHFC_SYSPORT_MAPPING TSE=F SLTH=T; 2743 tr 71 M=MMU_CHFC_SYSPORT_MAPPING TSE=T SLTH=T; 2744 tr 71 M=MMU_CHFC_SYSPORT_MAPPING TSE=T SLTH=F; 2745 echo " MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM"; 2746 tr 50 M=MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM; 2747 tr 51 M=MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM; 2748 tr 52 M=MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM; 2749 tr 71 M=MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM TSE=F SLTH=T; 2750 tr 71 M=MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM TSE=T SLTH=T; 2751 tr 71 M=MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM TSE=T SLTH=F; 2752 #echo " MMU_ENQ_CBP_32B_WR_STORE_0"; 2753 #tr 50 M=MMU_ENQ_CBP_32B_WR_STORE_0; 2754 #tr 51 M=MMU_ENQ_CBP_32B_WR_STORE_0; 2755 #tr 52 M=MMU_ENQ_CBP_32B_WR_STORE_0; 2756 #tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_0 TSE=F SLTH=T; 2757 #tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_0 TSE=T SLTH=T; 2758 #tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_0 TSE=T SLTH=F; 2759 #echo " MMU_ENQ_CBP_32B_WR_STORE_1"; 2760 #tr 50 M=MMU_ENQ_CBP_32B_WR_STORE_1; 2761 #tr 51 M=MMU_ENQ_CBP_32B_WR_STORE_1; 2762 #tr 52 M=MMU_ENQ_CBP_32B_WR_STORE_1; 2763 #tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_1 TSE=F SLTH=T; 2764 #tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_1 TSE=T SLTH=T; 2765 #tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_1 TSE=T SLTH=F; 2766 echo " MMU_ENQ_CBP_32B_WR_STORE_2"; 2767 tr 50 M=MMU_ENQ_CBP_32B_WR_STORE_2; 2768 tr 51 M=MMU_ENQ_CBP_32B_WR_STORE_2; 2769 tr 52 M=MMU_ENQ_CBP_32B_WR_STORE_2; 2770 tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_2 TSE=F SLTH=T; 2771 tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_2 TSE=T SLTH=T; 2772 tr 71 M=MMU_ENQ_CBP_32B_WR_STORE_2 TSE=T SLTH=F; 2773 echo " MMU_ENQ_CFAPI_INTERNAL_RECYCLE"; 2774 tr 50 M=MMU_ENQ_CFAPI_INTERNAL_RECYCLE; 2775 tr 51 M=MMU_ENQ_CFAPI_INTERNAL_RECYCLE; 2776 tr 52 M=MMU_ENQ_CFAPI_INTERNAL_RECYCLE; 2777 tr 71 M=MMU_ENQ_CFAPI_INTERNAL_RECYCLE TSE=F SLTH=T; 2778 tr 71 M=MMU_ENQ_CFAPI_INTERNAL_RECYCLE TSE=T SLTH=T; 2779 tr 71 M=MMU_ENQ_CFAPI_INTERNAL_RECYCLE TSE=T SLTH=F; 2780 echo " MMU_ENQ_FAP_BITMAP"; 2781 tr 50 M=MMU_ENQ_FAP_BITMAP; 2782 tr 51 M=MMU_ENQ_FAP_BITMAP; 2783 tr 52 M=MMU_ENQ_FAP_BITMAP; 2784 tr 71 M=MMU_ENQ_FAP_BITMAP TSE=F SLTH=T; 2785 tr 71 M=MMU_ENQ_FAP_BITMAP TSE=T SLTH=T; 2786 tr 71 M=MMU_ENQ_FAP_BITMAP TSE=T SLTH=F; 2787 echo " MMU_ENQ_FAP_STACK"; 2788 tr 50 M=MMU_ENQ_FAP_STACK; 2789 tr 51 M=MMU_ENQ_FAP_STACK; 2790 tr 52 M=MMU_ENQ_FAP_STACK; 2791 tr 71 M=MMU_ENQ_FAP_STACK TSE=F SLTH=T; 2792 tr 71 M=MMU_ENQ_FAP_STACK TSE=T SLTH=T; 2793 tr 71 M=MMU_ENQ_FAP_STACK TSE=T SLTH=F; 2794 echo " MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL"; 2795 tr 50 M=MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL; 2796 tr 51 M=MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL; 2797 tr 52 M=MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL; 2798 tr 71 M=MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL TSE=F SLTH=T; 2799 tr 71 M=MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL TSE=T SLTH=T; 2800 tr 71 M=MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL TSE=T SLTH=F; 2801 #echo " MMU_ENQ_RQE_WR_COMPLETE_0"; 2802 #tr 50 M=MMU_ENQ_RQE_WR_COMPLETE_0; 2803 #tr 51 M=MMU_ENQ_RQE_WR_COMPLETE_0; 2804 #tr 52 M=MMU_ENQ_RQE_WR_COMPLETE_0; 2805 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_0 TSE=F SLTH=T; 2806 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_0 TSE=T SLTH=T; 2807 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_0 TSE=T SLTH=F; 2808 #echo " MMU_ENQ_RQE_WR_COMPLETE_1"; 2809 #tr 50 M=MMU_ENQ_RQE_WR_COMPLETE_1; 2810 #tr 51 M=MMU_ENQ_RQE_WR_COMPLETE_1; 2811 #tr 52 M=MMU_ENQ_RQE_WR_COMPLETE_1; 2812 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_1 TSE=F SLTH=T; 2813 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_1 TSE=T SLTH=T; 2814 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_1 TSE=T SLTH=F; 2815 #echo " MMU_ENQ_RQE_WR_COMPLETE_2"; 2816 #tr 50 M=MMU_ENQ_RQE_WR_COMPLETE_2; 2817 #tr 51 M=MMU_ENQ_RQE_WR_COMPLETE_2; 2818 #tr 52 M=MMU_ENQ_RQE_WR_COMPLETE_2; 2819 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_2 TSE=F SLTH=T; 2820 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_2 TSE=T SLTH=T; 2821 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_2 TSE=T SLTH=F; 2822 #echo " MMU_ENQ_RQE_WR_COMPLETE_3"; 2823 #tr 50 M=MMU_ENQ_RQE_WR_COMPLETE_3; 2824 #tr 51 M=MMU_ENQ_RQE_WR_COMPLETE_3; 2825 #tr 52 M=MMU_ENQ_RQE_WR_COMPLETE_3; 2826 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_3 TSE=F SLTH=T; 2827 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_3 TSE=T SLTH=T; 2828 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_3 TSE=T SLTH=F; 2829 #echo " MMU_ENQ_RQE_WR_COMPLETE_4"; 2830 #tr 50 M=MMU_ENQ_RQE_WR_COMPLETE_4; 2831 #tr 51 M=MMU_ENQ_RQE_WR_COMPLETE_4; 2832 #tr 52 M=MMU_ENQ_RQE_WR_COMPLETE_4; 2833 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_4 TSE=F SLTH=T; 2834 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_4 TSE=T SLTH=T; 2835 #tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_4 TSE=T SLTH=F; 2836 echo " MMU_ENQ_RQE_WR_COMPLETE_5"; 2837 tr 50 M=MMU_ENQ_RQE_WR_COMPLETE_5; 2838 tr 51 M=MMU_ENQ_RQE_WR_COMPLETE_5; 2839 tr 52 M=MMU_ENQ_RQE_WR_COMPLETE_5; 2840 tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_5 TSE=F SLTH=T; 2841 tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_5 TSE=T SLTH=T; 2842 tr 71 M=MMU_ENQ_RQE_WR_COMPLETE_5 TSE=T SLTH=F; 2843 #echo " MMU_ENQ_SRC_PORT_STATE_0"; 2844 #tr 50 M=MMU_ENQ_SRC_PORT_STATE_0; 2845 #tr 51 M=MMU_ENQ_SRC_PORT_STATE_0; 2846 #tr 52 M=MMU_ENQ_SRC_PORT_STATE_0; 2847 #tr 71 M=MMU_ENQ_SRC_PORT_STATE_0 TSE=F SLTH=T; 2848 #tr 71 M=MMU_ENQ_SRC_PORT_STATE_0 TSE=T SLTH=T; 2849 #tr 71 M=MMU_ENQ_SRC_PORT_STATE_0 TSE=T SLTH=F; 2850 #echo " MMU_ENQ_SRC_PORT_STATE_1"; 2851 #tr 50 M=MMU_ENQ_SRC_PORT_STATE_1; 2852 #tr 51 M=MMU_ENQ_SRC_PORT_STATE_1; 2853 #tr 52 M=MMU_ENQ_SRC_PORT_STATE_1; 2854 #tr 71 M=MMU_ENQ_SRC_PORT_STATE_1 TSE=F SLTH=T; 2855 #tr 71 M=MMU_ENQ_SRC_PORT_STATE_1 TSE=T SLTH=T; 2856 #tr 71 M=MMU_ENQ_SRC_PORT_STATE_1 TSE=T SLTH=F; 2857 echo " MMU_ENQ_SRC_PORT_STATE_2"; 2858 tr 50 M=MMU_ENQ_SRC_PORT_STATE_2; 2859 tr 51 M=MMU_ENQ_SRC_PORT_STATE_2; 2860 tr 52 M=MMU_ENQ_SRC_PORT_STATE_2; 2861 tr 71 M=MMU_ENQ_SRC_PORT_STATE_2 TSE=F SLTH=T; 2862 tr 71 M=MMU_ENQ_SRC_PORT_STATE_2 TSE=T SLTH=T; 2863 tr 71 M=MMU_ENQ_SRC_PORT_STATE_2 TSE=T SLTH=F; 2864 echo " MMU_ENQ_SRC_PPP_TO_S1_LOOKUP"; 2865 tr 50 M=MMU_ENQ_SRC_PPP_TO_S1_LOOKUP; 2866 tr 51 M=MMU_ENQ_SRC_PPP_TO_S1_LOOKUP; 2867 tr 52 M=MMU_ENQ_SRC_PPP_TO_S1_LOOKUP; 2868 tr 71 M=MMU_ENQ_SRC_PPP_TO_S1_LOOKUP TSE=F SLTH=T; 2869 tr 71 M=MMU_ENQ_SRC_PPP_TO_S1_LOOKUP TSE=T SLTH=T; 2870 tr 71 M=MMU_ENQ_SRC_PPP_TO_S1_LOOKUP TSE=T SLTH=F; 2871 echo " MMU_EXT_MC_GROUP_MAP"; 2872 tr 50 M=MMU_EXT_MC_GROUP_MAP; 2873 tr 51 M=MMU_EXT_MC_GROUP_MAP; 2874 tr 52 M=MMU_EXT_MC_GROUP_MAP; 2875 tr 71 M=MMU_EXT_MC_GROUP_MAP TSE=F SLTH=T; 2876 tr 71 M=MMU_EXT_MC_GROUP_MAP TSE=T SLTH=T; 2877 tr 71 M=MMU_EXT_MC_GROUP_MAP TSE=T SLTH=F; 2878 echo " MMU_EXT_MC_QUEUE_LIST0"; 2879 tr 50 M=MMU_EXT_MC_QUEUE_LIST0; 2880 tr 51 M=MMU_EXT_MC_QUEUE_LIST0; 2881 tr 52 M=MMU_EXT_MC_QUEUE_LIST0; 2882 tr 71 M=MMU_EXT_MC_QUEUE_LIST0 TSE=F SLTH=T; 2883 tr 71 M=MMU_EXT_MC_QUEUE_LIST0 TSE=T SLTH=T; 2884 tr 71 M=MMU_EXT_MC_QUEUE_LIST0 TSE=T SLTH=F; 2885 echo " MMU_EXT_MC_QUEUE_LIST1"; 2886 tr 50 M=MMU_EXT_MC_QUEUE_LIST1; 2887 tr 51 M=MMU_EXT_MC_QUEUE_LIST1; 2888 tr 52 M=MMU_EXT_MC_QUEUE_LIST1; 2889 tr 71 M=MMU_EXT_MC_QUEUE_LIST1 TSE=F SLTH=T; 2890 tr 71 M=MMU_EXT_MC_QUEUE_LIST1 TSE=T SLTH=T; 2891 tr 71 M=MMU_EXT_MC_QUEUE_LIST1 TSE=T SLTH=F; 2892 echo " MMU_EXT_MC_QUEUE_LIST4"; 2893 tr 50 M=MMU_EXT_MC_QUEUE_LIST4; 2894 tr 51 M=MMU_EXT_MC_QUEUE_LIST4; 2895 tr 52 M=MMU_EXT_MC_QUEUE_LIST4; 2896 tr 71 M=MMU_EXT_MC_QUEUE_LIST4 TSE=F SLTH=T; 2897 tr 71 M=MMU_EXT_MC_QUEUE_LIST4 TSE=T SLTH=T; 2898 tr 71 M=MMU_EXT_MC_QUEUE_LIST4 TSE=T SLTH=F; 2899 echo " MMU_INTFI_BASE_INDEX_TBL"; 2900 tr 50 M=MMU_INTFI_BASE_INDEX_TBL; 2901 tr 51 M=MMU_INTFI_BASE_INDEX_TBL; 2902 tr 52 M=MMU_INTFI_BASE_INDEX_TBL; 2903 tr 71 M=MMU_INTFI_BASE_INDEX_TBL TSE=F SLTH=T; 2904 tr 71 M=MMU_INTFI_BASE_INDEX_TBL TSE=T SLTH=T; 2905 tr 71 M=MMU_INTFI_BASE_INDEX_TBL TSE=T SLTH=F; 2906 #echo " MMU_INTFI_DEBUG_MEM"; 2907 #tr 50 M=MMU_INTFI_DEBUG_MEM; 2908 #tr 51 M=MMU_INTFI_DEBUG_MEM; 2909 #tr 52 M=MMU_INTFI_DEBUG_MEM; 2910 #tr 71 M=MMU_INTFI_DEBUG_MEM TSE=F SLTH=T; 2911 #tr 71 M=MMU_INTFI_DEBUG_MEM TSE=T SLTH=T; 2912 #tr 71 M=MMU_INTFI_DEBUG_MEM TSE=T SLTH=F; 2913 echo " MMU_INTFI_FC_MAP_TBL0"; 2914 tr 50 M=MMU_INTFI_FC_MAP_TBL0; 2915 tr 51 M=MMU_INTFI_FC_MAP_TBL0; 2916 tr 52 M=MMU_INTFI_FC_MAP_TBL0; 2917 tr 71 M=MMU_INTFI_FC_MAP_TBL0 TSE=F SLTH=T; 2918 tr 71 M=MMU_INTFI_FC_MAP_TBL0 TSE=T SLTH=T; 2919 tr 71 M=MMU_INTFI_FC_MAP_TBL0 TSE=T SLTH=F; 2920 echo " MMU_INTFI_FC_MAP_TBL1"; 2921 tr 50 M=MMU_INTFI_FC_MAP_TBL1; 2922 tr 51 M=MMU_INTFI_FC_MAP_TBL1; 2923 tr 52 M=MMU_INTFI_FC_MAP_TBL1; 2924 tr 71 M=MMU_INTFI_FC_MAP_TBL1 TSE=F SLTH=T; 2925 tr 71 M=MMU_INTFI_FC_MAP_TBL1 TSE=T SLTH=T; 2926 tr 71 M=MMU_INTFI_FC_MAP_TBL1 TSE=T SLTH=F; 2927 echo " MMU_INTFI_FC_MAP_TBL2"; 2928 tr 50 M=MMU_INTFI_FC_MAP_TBL2 EccAsData=0; 2929 tr 51 M=MMU_INTFI_FC_MAP_TBL2 EccAsData=0; 2930 tr 52 M=MMU_INTFI_FC_MAP_TBL2 EccAsData=0; 2931 tr 71 M=MMU_INTFI_FC_MAP_TBL2 TSE=F SLTH=T EccAsData=0; 2932 tr 71 M=MMU_INTFI_FC_MAP_TBL2 TSE=T SLTH=T EccAsData=0; 2933 tr 71 M=MMU_INTFI_FC_MAP_TBL2 TSE=T SLTH=F EccAsData=0; 2934 echo " MMU_INTFI_FC_ST_TBL0"; 2935 tr 50 M=MMU_INTFI_FC_ST_TBL0; 2936 tr 51 M=MMU_INTFI_FC_ST_TBL0; 2937 tr 52 M=MMU_INTFI_FC_ST_TBL0; 2938 tr 71 M=MMU_INTFI_FC_ST_TBL0 TSE=F SLTH=T; 2939 tr 71 M=MMU_INTFI_FC_ST_TBL0 TSE=T SLTH=T; 2940 tr 71 M=MMU_INTFI_FC_ST_TBL0 TSE=T SLTH=F; 2941 echo " MMU_INTFI_FC_ST_TBL1"; 2942 tr 50 M=MMU_INTFI_FC_ST_TBL1; 2943 tr 51 M=MMU_INTFI_FC_ST_TBL1; 2944 tr 52 M=MMU_INTFI_FC_ST_TBL1; 2945 tr 71 M=MMU_INTFI_FC_ST_TBL1 TSE=F SLTH=T; 2946 tr 71 M=MMU_INTFI_FC_ST_TBL1 TSE=T SLTH=T; 2947 tr 71 M=MMU_INTFI_FC_ST_TBL1 TSE=T SLTH=F; 2948 echo " MMU_INTFI_FC_ST_TBL2"; 2949 tr 50 M=MMU_INTFI_FC_ST_TBL2; 2950 tr 51 M=MMU_INTFI_FC_ST_TBL2; 2951 tr 52 M=MMU_INTFI_FC_ST_TBL2; 2952 tr 71 M=MMU_INTFI_FC_ST_TBL2 TSE=F SLTH=T; 2953 tr 71 M=MMU_INTFI_FC_ST_TBL2 TSE=T SLTH=T; 2954 tr 71 M=MMU_INTFI_FC_ST_TBL2 TSE=T SLTH=F; 2955 echo " MMU_INTFI_MERGE_ST_TBL"; 2956 tr 50 M=MMU_INTFI_MERGE_ST_TBL; 2957 tr 51 M=MMU_INTFI_MERGE_ST_TBL; 2958 tr 52 M=MMU_INTFI_MERGE_ST_TBL; 2959 tr 71 M=MMU_INTFI_MERGE_ST_TBL TSE=F SLTH=T; 2960 tr 71 M=MMU_INTFI_MERGE_ST_TBL TSE=T SLTH=T; 2961 tr 71 M=MMU_INTFI_MERGE_ST_TBL TSE=T SLTH=F; 2962 echo " MMU_INTFI_OFFSET_MAP_TBL"; 2963 tr 50 M=MMU_INTFI_OFFSET_MAP_TBL; 2964 tr 51 M=MMU_INTFI_OFFSET_MAP_TBL; 2965 tr 52 M=MMU_INTFI_OFFSET_MAP_TBL; 2966 tr 71 M=MMU_INTFI_OFFSET_MAP_TBL TSE=F SLTH=T; 2967 tr 71 M=MMU_INTFI_OFFSET_MAP_TBL TSE=T SLTH=T; 2968 tr 71 M=MMU_INTFI_OFFSET_MAP_TBL TSE=T SLTH=F; 2969 #echo " MMU_INTFI_PFC_ST_TBL"; 2970 #tr 50 M=MMU_INTFI_PFC_ST_TBL; 2971 #tr 51 M=MMU_INTFI_PFC_ST_TBL; 2972 #tr 52 M=MMU_INTFI_PFC_ST_TBL; 2973 #tr 71 M=MMU_INTFI_PFC_ST_TBL TSE=F SLTH=T; 2974 #tr 71 M=MMU_INTFI_PFC_ST_TBL TSE=T SLTH=T; 2975 #tr 71 M=MMU_INTFI_PFC_ST_TBL TSE=T SLTH=F; 2976 echo " MMU_INTFI_ST_TRANS_TBL"; 2977 tr 50 M=MMU_INTFI_ST_TRANS_TBL EccAsData=0; 2978 tr 51 M=MMU_INTFI_ST_TRANS_TBL EccAsData=0; 2979 tr 52 M=MMU_INTFI_ST_TRANS_TBL EccAsData=0; 2980 tr 71 M=MMU_INTFI_ST_TRANS_TBL TSE=F SLTH=T EccAsData=0; 2981 tr 71 M=MMU_INTFI_ST_TRANS_TBL TSE=T SLTH=T EccAsData=0; 2982 tr 71 M=MMU_INTFI_ST_TRANS_TBL TSE=T SLTH=F EccAsData=0; 2983 echo " MMU_INTFO_TC2PRI_MAPPING"; 2984 tr 50 M=MMU_INTFO_TC2PRI_MAPPING EccAsData=0; 2985 tr 51 M=MMU_INTFO_TC2PRI_MAPPING EccAsData=0; 2986 tr 52 M=MMU_INTFO_TC2PRI_MAPPING EccAsData=0; 2987 tr 71 M=MMU_INTFO_TC2PRI_MAPPING TSE=F SLTH=T EccAsData=0; 2988 tr 71 M=MMU_INTFO_TC2PRI_MAPPING TSE=T SLTH=T EccAsData=0; 2989 tr 71 M=MMU_INTFO_TC2PRI_MAPPING TSE=T SLTH=F EccAsData=0; 2990 echo " MMU_IPCTR_CTXT_COUNTER_0"; 2991 tr 50 M=MMU_IPCTR_CTXT_COUNTER_0 EccAsData=0; 2992 tr 51 M=MMU_IPCTR_CTXT_COUNTER_0 EccAsData=0; 2993 tr 52 M=MMU_IPCTR_CTXT_COUNTER_0 EccAsData=0; 2994 tr 71 M=MMU_IPCTR_CTXT_COUNTER_0 TSE=F SLTH=T EccAsData=0; 2995 tr 71 M=MMU_IPCTR_CTXT_COUNTER_0 TSE=T SLTH=T EccAsData=0; 2996 tr 71 M=MMU_IPCTR_CTXT_COUNTER_0 TSE=T SLTH=F EccAsData=0; 2997 echo " MMU_IPCTR_PG_COUNTER_0"; 2998 tr 50 M=MMU_IPCTR_PG_COUNTER_0 EccAsData=0; 2999 tr 51 M=MMU_IPCTR_PG_COUNTER_0 EccAsData=0; 3000 tr 52 M=MMU_IPCTR_PG_COUNTER_0 EccAsData=0; 3001 tr 71 M=MMU_IPCTR_PG_COUNTER_0 TSE=F SLTH=T EccAsData=0; 3002 tr 71 M=MMU_IPCTR_PG_COUNTER_0 TSE=T SLTH=T EccAsData=0; 3003 tr 71 M=MMU_IPCTR_PG_COUNTER_0 TSE=T SLTH=F EccAsData=0; 3004 echo " MMU_IPCTR_PG_COUNTER_1"; 3005 tr 50 M=MMU_IPCTR_PG_COUNTER_1 EccAsData=0; 3006 tr 51 M=MMU_IPCTR_PG_COUNTER_1 EccAsData=0; 3007 tr 52 M=MMU_IPCTR_PG_COUNTER_1 EccAsData=0; 3008 tr 71 M=MMU_IPCTR_PG_COUNTER_1 TSE=F SLTH=T EccAsData=0; 3009 tr 71 M=MMU_IPCTR_PG_COUNTER_1 TSE=T SLTH=T EccAsData=0; 3010 tr 71 M=MMU_IPCTR_PG_COUNTER_1 TSE=T SLTH=F EccAsData=0; 3011 echo " MMU_IPMC_GROUP_TBL0"; 3012 tr 50 M=MMU_IPMC_GROUP_TBL0; 3013 tr 51 M=MMU_IPMC_GROUP_TBL0; 3014 tr 52 M=MMU_IPMC_GROUP_TBL0; 3015 tr 71 M=MMU_IPMC_GROUP_TBL0 TSE=F SLTH=T; 3016 tr 71 M=MMU_IPMC_GROUP_TBL0 TSE=T SLTH=T; 3017 tr 71 M=MMU_IPMC_GROUP_TBL0 TSE=T SLTH=F; 3018 echo " MMU_IPMC_GROUP_TBL1"; 3019 tr 50 M=MMU_IPMC_GROUP_TBL1; 3020 tr 51 M=MMU_IPMC_GROUP_TBL1; 3021 tr 52 M=MMU_IPMC_GROUP_TBL1; 3022 tr 71 M=MMU_IPMC_GROUP_TBL1 TSE=F SLTH=T; 3023 tr 71 M=MMU_IPMC_GROUP_TBL1 TSE=T SLTH=T; 3024 tr 71 M=MMU_IPMC_GROUP_TBL1 TSE=T SLTH=F; 3025 echo " MMU_IPMC_GROUP_TBL2"; 3026 tr 50 M=MMU_IPMC_GROUP_TBL2; 3027 tr 51 M=MMU_IPMC_GROUP_TBL2; 3028 tr 52 M=MMU_IPMC_GROUP_TBL2; 3029 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=F SLTH=T; 3030 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=T SLTH=T; 3031 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=T SLTH=F; 3032 echo " MMU_IPMC_GROUP_TBL3"; 3033 tr 50 M=MMU_IPMC_GROUP_TBL3; 3034 tr 51 M=MMU_IPMC_GROUP_TBL3; 3035 tr 52 M=MMU_IPMC_GROUP_TBL3; 3036 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=F SLTH=T; 3037 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=T SLTH=T; 3038 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=T SLTH=F; 3039 echo " MMU_IPMC_GROUP_TBL4"; 3040 tr 50 M=MMU_IPMC_GROUP_TBL4; 3041 tr 51 M=MMU_IPMC_GROUP_TBL4; 3042 tr 52 M=MMU_IPMC_GROUP_TBL4; 3043 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=F SLTH=T; 3044 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=T SLTH=T; 3045 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=T SLTH=F; 3046 echo " MMU_ITE_PACKET_PTR_STORE"; 3047 tr 50 M=MMU_ITE_PACKET_PTR_STORE; 3048 tr 51 M=MMU_ITE_PACKET_PTR_STORE; 3049 tr 52 M=MMU_ITE_PACKET_PTR_STORE; 3050 tr 71 M=MMU_ITE_PACKET_PTR_STORE TSE=F SLTH=T; 3051 tr 71 M=MMU_ITE_PACKET_PTR_STORE TSE=T SLTH=T; 3052 tr 71 M=MMU_ITE_PACKET_PTR_STORE TSE=T SLTH=F; 3053 echo " MMU_ITE_QMGR_FLL"; 3054 tr 50 M=MMU_ITE_QMGR_FLL; 3055 tr 51 M=MMU_ITE_QMGR_FLL; 3056 tr 52 M=MMU_ITE_QMGR_FLL; 3057 tr 71 M=MMU_ITE_QMGR_FLL TSE=F SLTH=T; 3058 tr 71 M=MMU_ITE_QMGR_FLL TSE=T SLTH=T; 3059 tr 71 M=MMU_ITE_QMGR_FLL TSE=T SLTH=F; 3060 echo " MMU_ITE_QMGR_QLL"; 3061 tr 50 M=MMU_ITE_QMGR_QLL; 3062 tr 51 M=MMU_ITE_QMGR_QLL; 3063 tr 52 M=MMU_ITE_QMGR_QLL; 3064 tr 71 M=MMU_ITE_QMGR_QLL TSE=F SLTH=T; 3065 tr 71 M=MMU_ITE_QMGR_QLL TSE=T SLTH=T; 3066 tr 71 M=MMU_ITE_QMGR_QLL TSE=T SLTH=F; 3067 #echo " MMU_ITE_WORK_QUEUE_0"; 3068 #tr 50 M=MMU_ITE_WORK_QUEUE_0; 3069 #tr 51 M=MMU_ITE_WORK_QUEUE_0; 3070 #tr 52 M=MMU_ITE_WORK_QUEUE_0; 3071 #tr 71 M=MMU_ITE_WORK_QUEUE_0 TSE=F SLTH=T; 3072 #tr 71 M=MMU_ITE_WORK_QUEUE_0 TSE=T SLTH=T; 3073 #tr 71 M=MMU_ITE_WORK_QUEUE_0 TSE=T SLTH=F; 3074 #echo " MMU_ITE_WORK_QUEUE_1"; 3075 #tr 50 M=MMU_ITE_WORK_QUEUE_1; 3076 #tr 51 M=MMU_ITE_WORK_QUEUE_1; 3077 #tr 52 M=MMU_ITE_WORK_QUEUE_1; 3078 #tr 71 M=MMU_ITE_WORK_QUEUE_1 TSE=F SLTH=T; 3079 #tr 71 M=MMU_ITE_WORK_QUEUE_1 TSE=T SLTH=T; 3080 #tr 71 M=MMU_ITE_WORK_QUEUE_1 TSE=T SLTH=F; 3081 echo " MMU_ITE_WORK_QUEUE_2"; 3082 tr 50 M=MMU_ITE_WORK_QUEUE_2; 3083 tr 51 M=MMU_ITE_WORK_QUEUE_2; 3084 tr 52 M=MMU_ITE_WORK_QUEUE_2; 3085 tr 71 M=MMU_ITE_WORK_QUEUE_2 TSE=F SLTH=T; 3086 tr 71 M=MMU_ITE_WORK_QUEUE_2 TSE=T SLTH=T; 3087 tr 71 M=MMU_ITE_WORK_QUEUE_2 TSE=T SLTH=F; 3088 echo " MMU_QSTRUCT_QBLOCK_BM_0"; 3089 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_0; 3090 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_0; 3091 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_0; 3092 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_0 TSE=F SLTH=T; 3093 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_0 TSE=T SLTH=T; 3094 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_0 TSE=T SLTH=F; 3095 echo " MMU_QSTRUCT_QBLOCK_BM_1"; 3096 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_1; 3097 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_1; 3098 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_1; 3099 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_1 TSE=F SLTH=T; 3100 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_1 TSE=T SLTH=T; 3101 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_1 TSE=T SLTH=F; 3102 echo " MMU_QSTRUCT_QBLOCK_BM_2"; 3103 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_2; 3104 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_2; 3105 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_2; 3106 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_2 TSE=F SLTH=T; 3107 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_2 TSE=T SLTH=T; 3108 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_2 TSE=T SLTH=F; 3109 echo " MMU_QSTRUCT_QBLOCK_BM_3"; 3110 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_3; 3111 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_3; 3112 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_3; 3113 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_3 TSE=F SLTH=T; 3114 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_3 TSE=T SLTH=T; 3115 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_3 TSE=T SLTH=F; 3116 echo " MMU_QSTRUCT_QBLOCK_BM_FIFO_0"; 3117 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_0; 3118 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_0; 3119 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_0; 3120 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_0 TSE=F SLTH=T; 3121 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_0 TSE=T SLTH=T; 3122 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_0 TSE=T SLTH=F; 3123 echo " MMU_QSTRUCT_QBLOCK_BM_FIFO_1"; 3124 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_1; 3125 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_1; 3126 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_1; 3127 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_1 TSE=F SLTH=T; 3128 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_1 TSE=T SLTH=T; 3129 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_1 TSE=T SLTH=F; 3130 echo " MMU_QSTRUCT_QBLOCK_BM_FIFO_2"; 3131 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_2; 3132 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_2; 3133 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_2; 3134 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_2 TSE=F SLTH=T; 3135 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_2 TSE=T SLTH=T; 3136 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_2 TSE=T SLTH=F; 3137 echo " MMU_QSTRUCT_QBLOCK_BM_FIFO_3"; 3138 tr 50 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_3; 3139 tr 51 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_3; 3140 tr 52 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_3; 3141 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_3 TSE=F SLTH=T; 3142 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_3 TSE=T SLTH=T; 3143 tr 71 M=MMU_QSTRUCT_QBLOCK_BM_FIFO_3 TSE=T SLTH=F; 3144 echo " MMU_QSTRUCT_QBLOCK_NEXT_0"; 3145 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_0; 3146 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_0; 3147 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_0; 3148 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_0 TSE=F SLTH=T; 3149 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_0 TSE=T SLTH=T; 3150 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_0 TSE=T SLTH=F; 3151 echo " MMU_QSTRUCT_QBLOCK_NEXT_1"; 3152 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_1; 3153 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_1; 3154 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_1; 3155 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_1 TSE=F SLTH=T; 3156 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_1 TSE=T SLTH=T; 3157 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_1 TSE=T SLTH=F; 3158 echo " MMU_QSTRUCT_QBLOCK_NEXT_2"; 3159 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_2; 3160 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_2; 3161 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_2; 3162 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_2 TSE=F SLTH=T; 3163 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_2 TSE=T SLTH=T; 3164 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_2 TSE=T SLTH=F; 3165 echo " MMU_QSTRUCT_QBLOCK_NEXT_3"; 3166 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_3; 3167 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_3; 3168 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_3; 3169 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_3 TSE=F SLTH=T; 3170 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_3 TSE=T SLTH=T; 3171 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_3 TSE=T SLTH=F; 3172 echo " MMU_QSTRUCT_QBLOCK_NEXT_4"; 3173 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_4; 3174 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_4; 3175 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_4; 3176 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_4 TSE=F SLTH=T; 3177 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_4 TSE=T SLTH=T; 3178 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_4 TSE=T SLTH=F; 3179 echo " MMU_QSTRUCT_QBLOCK_NEXT_5"; 3180 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_5; 3181 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_5; 3182 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_5; 3183 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_5 TSE=F SLTH=T; 3184 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_5 TSE=T SLTH=T; 3185 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_5 TSE=T SLTH=F; 3186 echo " MMU_QSTRUCT_QBLOCK_NEXT_6"; 3187 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_6; 3188 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_6; 3189 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_6; 3190 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_6 TSE=F SLTH=T; 3191 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_6 TSE=T SLTH=T; 3192 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_6 TSE=T SLTH=F; 3193 echo " MMU_QSTRUCT_QBLOCK_NEXT_7"; 3194 tr 50 M=MMU_QSTRUCT_QBLOCK_NEXT_7; 3195 tr 51 M=MMU_QSTRUCT_QBLOCK_NEXT_7; 3196 tr 52 M=MMU_QSTRUCT_QBLOCK_NEXT_7; 3197 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_7 TSE=F SLTH=T; 3198 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_7 TSE=T SLTH=T; 3199 tr 71 M=MMU_QSTRUCT_QBLOCK_NEXT_7 TSE=T SLTH=F; 3200 if !$?LIKE_BCM56456 \ 3201 'echo " MMU_QSTRUCT_QENTRY_LOWER_0"; \ 3202 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_0; \ 3203 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_0; \ 3204 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_0; \ 3205 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_0 TSE=F SLTH=T; \ 3206 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_0 TSE=T SLTH=T; \ 3207 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_0 TSE=T SLTH=F; \ 3208 echo " MMU_QSTRUCT_QENTRY_LOWER_1"; \ 3209 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_1; \ 3210 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_1; \ 3211 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_1; \ 3212 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_1 TSE=F SLTH=T; \ 3213 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_1 TSE=T SLTH=T; \ 3214 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_1 TSE=T SLTH=F; \ 3215 echo " MMU_QSTRUCT_QENTRY_LOWER_2"; \ 3216 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_2; \ 3217 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_2; \ 3218 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_2; \ 3219 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_2 TSE=F SLTH=T; \ 3220 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_2 TSE=T SLTH=T; \ 3221 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_2 TSE=T SLTH=F; \ 3222 echo " MMU_QSTRUCT_QENTRY_LOWER_3"; \ 3223 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_3; \ 3224 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_3; \ 3225 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_3; \ 3226 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_3 TSE=F SLTH=T; \ 3227 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_3 TSE=T SLTH=T; \ 3228 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_3 TSE=T SLTH=F; \ 3229 echo " MMU_QSTRUCT_QENTRY_LOWER_4"; \ 3230 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_4; \ 3231 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_4; \ 3232 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_4; \ 3233 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_4 TSE=F SLTH=T; \ 3234 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_4 TSE=T SLTH=T; \ 3235 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_4 TSE=T SLTH=F; \ 3236 echo " MMU_QSTRUCT_QENTRY_LOWER_5"; \ 3237 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_5; \ 3238 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_5; \ 3239 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_5; \ 3240 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_5 TSE=F SLTH=T; \ 3241 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_5 TSE=T SLTH=T; \ 3242 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_5 TSE=T SLTH=F; \ 3243 echo " MMU_QSTRUCT_QENTRY_LOWER_6"; \ 3244 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_6; \ 3245 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_6; \ 3246 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_6; \ 3247 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_6 TSE=F SLTH=T; \ 3248 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_6 TSE=T SLTH=T; \ 3249 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_6 TSE=T SLTH=F; \ 3250 echo " MMU_QSTRUCT_QENTRY_LOWER_7"; \ 3251 tr 50 M=MMU_QSTRUCT_QENTRY_LOWER_7; \ 3252 tr 51 M=MMU_QSTRUCT_QENTRY_LOWER_7; \ 3253 tr 52 M=MMU_QSTRUCT_QENTRY_LOWER_7; \ 3254 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_7 TSE=F SLTH=T; \ 3255 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_7 TSE=T SLTH=T; \ 3256 tr 71 M=MMU_QSTRUCT_QENTRY_LOWER_7 TSE=T SLTH=F; \ 3257 $done;' 3258 echo " MMU_QSTRUCT_QENTRY_UPPER_0"; 3259 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_0; 3260 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_0; 3261 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_0; 3262 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_0 TSE=F SLTH=T; 3263 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_0 TSE=T SLTH=T; 3264 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_0 TSE=T SLTH=F; 3265 echo " MMU_QSTRUCT_QENTRY_UPPER_1"; 3266 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_1; 3267 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_1; 3268 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_1; 3269 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_1 TSE=F SLTH=T; 3270 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_1 TSE=T SLTH=T; 3271 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_1 TSE=T SLTH=F; 3272 echo " MMU_QSTRUCT_QENTRY_UPPER_2"; 3273 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_2; 3274 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_2; 3275 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_2; 3276 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_2 TSE=F SLTH=T; 3277 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_2 TSE=T SLTH=T; 3278 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_2 TSE=T SLTH=F; 3279 echo " MMU_QSTRUCT_QENTRY_UPPER_3"; 3280 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_3; 3281 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_3; 3282 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_3; 3283 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_3 TSE=F SLTH=T; 3284 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_3 TSE=T SLTH=T; 3285 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_3 TSE=T SLTH=F; 3286 echo " MMU_QSTRUCT_QENTRY_UPPER_4"; 3287 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_4; 3288 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_4; 3289 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_4; 3290 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_4 TSE=F SLTH=T; 3291 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_4 TSE=T SLTH=T; 3292 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_4 TSE=T SLTH=F; 3293 echo " MMU_QSTRUCT_QENTRY_UPPER_5"; 3294 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_5; 3295 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_5; 3296 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_5; 3297 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_5 TSE=F SLTH=T; 3298 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_5 TSE=T SLTH=T; 3299 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_5 TSE=T SLTH=F; 3300 echo " MMU_QSTRUCT_QENTRY_UPPER_6"; 3301 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_6; 3302 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_6; 3303 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_6; 3304 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_6 TSE=F SLTH=T; 3305 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_6 TSE=T SLTH=T; 3306 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_6 TSE=T SLTH=F; 3307 echo " MMU_QSTRUCT_QENTRY_UPPER_7"; 3308 tr 50 M=MMU_QSTRUCT_QENTRY_UPPER_7; 3309 tr 51 M=MMU_QSTRUCT_QENTRY_UPPER_7; 3310 tr 52 M=MMU_QSTRUCT_QENTRY_UPPER_7; 3311 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_7 TSE=F SLTH=T; 3312 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_7 TSE=T SLTH=T; 3313 tr 71 M=MMU_QSTRUCT_QENTRY_UPPER_7 TSE=T SLTH=F; 3314 echo " MMU_RDE_ADM_DPC_STORE_MEM"; 3315 tr 50 M=MMU_RDE_ADM_DPC_STORE_MEM EccAsData=0; 3316 tr 51 M=MMU_RDE_ADM_DPC_STORE_MEM EccAsData=0; 3317 tr 52 M=MMU_RDE_ADM_DPC_STORE_MEM EccAsData=0; 3318 tr 71 M=MMU_RDE_ADM_DPC_STORE_MEM TSE=F SLTH=T EccAsData=0; 3319 tr 71 M=MMU_RDE_ADM_DPC_STORE_MEM TSE=T SLTH=T EccAsData=0; 3320 tr 71 M=MMU_RDE_ADM_DPC_STORE_MEM TSE=T SLTH=F EccAsData=0; 3321 echo " MMU_RDE_ITE_REL_FIFO_MEM"; 3322 tr 50 M=MMU_RDE_ITE_REL_FIFO_MEM EccAsData=0; 3323 tr 51 M=MMU_RDE_ITE_REL_FIFO_MEM EccAsData=0; 3324 tr 52 M=MMU_RDE_ITE_REL_FIFO_MEM EccAsData=0; 3325 tr 71 M=MMU_RDE_ITE_REL_FIFO_MEM TSE=F SLTH=T EccAsData=0; 3326 tr 71 M=MMU_RDE_ITE_REL_FIFO_MEM TSE=T SLTH=T EccAsData=0; 3327 tr 71 M=MMU_RDE_ITE_REL_FIFO_MEM TSE=T SLTH=F EccAsData=0; 3328 echo " MMU_RDE_PQE_FIFO_MEM"; 3329 tr 50 M=MMU_RDE_PQE_FIFO_MEM EccAsData=0; 3330 tr 51 M=MMU_RDE_PQE_FIFO_MEM EccAsData=0; 3331 tr 52 M=MMU_RDE_PQE_FIFO_MEM EccAsData=0; 3332 tr 71 M=MMU_RDE_PQE_FIFO_MEM TSE=F SLTH=T EccAsData=0; 3333 tr 71 M=MMU_RDE_PQE_FIFO_MEM TSE=T SLTH=T EccAsData=0; 3334 tr 71 M=MMU_RDE_PQE_FIFO_MEM TSE=T SLTH=F EccAsData=0; 3335 echo " MMU_RDE_REAL_CELL_FIFO_MEM"; 3336 tr 50 M=MMU_RDE_REAL_CELL_FIFO_MEM EccAsData=0; 3337 tr 51 M=MMU_RDE_REAL_CELL_FIFO_MEM EccAsData=0; 3338 tr 52 M=MMU_RDE_REAL_CELL_FIFO_MEM EccAsData=0; 3339 tr 71 M=MMU_RDE_REAL_CELL_FIFO_MEM TSE=F SLTH=T EccAsData=0; 3340 tr 71 M=MMU_RDE_REAL_CELL_FIFO_MEM TSE=T SLTH=T EccAsData=0; 3341 tr 71 M=MMU_RDE_REAL_CELL_FIFO_MEM TSE=T SLTH=F EccAsData=0; 3342 echo " MMU_RDE_TXQ_FLL"; 3343 tr 50 M=MMU_RDE_TXQ_FLL EccAsData=0; 3344 tr 51 M=MMU_RDE_TXQ_FLL EccAsData=0; 3345 tr 52 M=MMU_RDE_TXQ_FLL EccAsData=0; 3346 tr 71 M=MMU_RDE_TXQ_FLL TSE=F SLTH=T EccAsData=0; 3347 tr 71 M=MMU_RDE_TXQ_FLL TSE=T SLTH=T EccAsData=0; 3348 tr 71 M=MMU_RDE_TXQ_FLL TSE=T SLTH=F EccAsData=0; 3349 echo " MMU_RDE_TXQ_QLL"; 3350 tr 50 M=MMU_RDE_TXQ_QLL EccAsData=0; 3351 tr 51 M=MMU_RDE_TXQ_QLL EccAsData=0; 3352 tr 52 M=MMU_RDE_TXQ_QLL EccAsData=0; 3353 tr 71 M=MMU_RDE_TXQ_QLL TSE=F SLTH=T EccAsData=0; 3354 tr 71 M=MMU_RDE_TXQ_QLL TSE=T SLTH=T EccAsData=0; 3355 tr 71 M=MMU_RDE_TXQ_QLL TSE=T SLTH=F EccAsData=0; 3356 echo " MMU_RDE_TXQ_STATE"; 3357 tr 50 M=MMU_RDE_TXQ_STATE EccAsData=0; 3358 tr 51 M=MMU_RDE_TXQ_STATE EccAsData=0; 3359 tr 52 M=MMU_RDE_TXQ_STATE EccAsData=0; 3360 tr 71 M=MMU_RDE_TXQ_STATE TSE=F SLTH=T EccAsData=0; 3361 tr 71 M=MMU_RDE_TXQ_STATE TSE=T SLTH=T EccAsData=0; 3362 tr 71 M=MMU_RDE_TXQ_STATE TSE=T SLTH=F EccAsData=0; 3363 echo " MMU_REPL_GRP_TBL0"; 3364 tr 50 M=MMU_REPL_GRP_TBL0; 3365 tr 51 M=MMU_REPL_GRP_TBL0; 3366 tr 52 M=MMU_REPL_GRP_TBL0; 3367 tr 71 M=MMU_REPL_GRP_TBL0 TSE=F SLTH=T; 3368 tr 71 M=MMU_REPL_GRP_TBL0 TSE=T SLTH=T; 3369 tr 71 M=MMU_REPL_GRP_TBL0 TSE=T SLTH=F; 3370 echo " MMU_REPL_GRP_TBL1"; 3371 tr 50 M=MMU_REPL_GRP_TBL1; 3372 tr 51 M=MMU_REPL_GRP_TBL1; 3373 tr 52 M=MMU_REPL_GRP_TBL1; 3374 tr 71 M=MMU_REPL_GRP_TBL1 TSE=F SLTH=T; 3375 tr 71 M=MMU_REPL_GRP_TBL1 TSE=T SLTH=T; 3376 tr 71 M=MMU_REPL_GRP_TBL1 TSE=T SLTH=F; 3377 echo " MMU_REPL_GRP_TBL2"; 3378 tr 50 M=MMU_REPL_GRP_TBL2; 3379 tr 51 M=MMU_REPL_GRP_TBL2; 3380 tr 52 M=MMU_REPL_GRP_TBL2; 3381 tr 71 M=MMU_REPL_GRP_TBL2 TSE=F SLTH=T; 3382 tr 71 M=MMU_REPL_GRP_TBL2 TSE=T SLTH=T; 3383 tr 71 M=MMU_REPL_GRP_TBL2 TSE=T SLTH=F; 3384 echo " MMU_REPL_HEAD_TBL"; 3385 tr 50 M=MMU_REPL_HEAD_TBL; 3386 tr 51 M=MMU_REPL_HEAD_TBL; 3387 tr 52 M=MMU_REPL_HEAD_TBL; 3388 tr 71 M=MMU_REPL_HEAD_TBL TSE=F SLTH=T; 3389 tr 71 M=MMU_REPL_HEAD_TBL TSE=T SLTH=T; 3390 tr 71 M=MMU_REPL_HEAD_TBL TSE=T SLTH=F; 3391 echo " MMU_REPL_LIST_TBL"; 3392 tr 50 M=MMU_REPL_LIST_TBL; 3393 tr 51 M=MMU_REPL_LIST_TBL; 3394 tr 52 M=MMU_REPL_LIST_TBL; 3395 tr 71 M=MMU_REPL_LIST_TBL TSE=F SLTH=T; 3396 tr 71 M=MMU_REPL_LIST_TBL TSE=T SLTH=T; 3397 tr 71 M=MMU_REPL_LIST_TBL TSE=T SLTH=F; 3398 echo " MMU_REPL_MAP_TBL"; 3399 tr 50 M=MMU_REPL_MAP_TBL; 3400 tr 51 M=MMU_REPL_MAP_TBL; 3401 tr 52 M=MMU_REPL_MAP_TBL; 3402 tr 71 M=MMU_REPL_MAP_TBL TSE=F SLTH=T; 3403 tr 71 M=MMU_REPL_MAP_TBL TSE=T SLTH=T; 3404 tr 71 M=MMU_REPL_MAP_TBL TSE=T SLTH=F; 3405 echo " MMU_REPL_STATE_TBL"; 3406 tr 50 M=MMU_REPL_STATE_TBL; 3407 tr 51 M=MMU_REPL_STATE_TBL; 3408 tr 52 M=MMU_REPL_STATE_TBL; 3409 tr 71 M=MMU_REPL_STATE_TBL TSE=F SLTH=T; 3410 tr 71 M=MMU_REPL_STATE_TBL TSE=T SLTH=T; 3411 tr 71 M=MMU_REPL_STATE_TBL TSE=T SLTH=F; 3412 echo " MMU_RPFAP_BITMAP"; 3413 tr 50 M=MMU_RPFAP_BITMAP EccAsData=0; 3414 tr 51 M=MMU_RPFAP_BITMAP EccAsData=0; 3415 tr 52 M=MMU_RPFAP_BITMAP EccAsData=0; 3416 tr 71 M=MMU_RPFAP_BITMAP TSE=F SLTH=T EccAsData=0; 3417 tr 71 M=MMU_RPFAP_BITMAP TSE=T SLTH=T EccAsData=0; 3418 tr 71 M=MMU_RPFAP_BITMAP TSE=T SLTH=F EccAsData=0; 3419 echo " MMU_RPFAP_STACK"; 3420 tr 50 M=MMU_RPFAP_STACK EccAsData=0; 3421 tr 51 M=MMU_RPFAP_STACK EccAsData=0; 3422 tr 52 M=MMU_RPFAP_STACK EccAsData=0; 3423 tr 71 M=MMU_RPFAP_STACK TSE=F SLTH=T EccAsData=0; 3424 tr 71 M=MMU_RPFAP_STACK TSE=T SLTH=T EccAsData=0; 3425 tr 71 M=MMU_RPFAP_STACK TSE=T SLTH=F EccAsData=0; 3426 echo " MMU_RQE_QMGR_FLL"; 3427 tr 50 M=MMU_RQE_QMGR_FLL; 3428 tr 51 M=MMU_RQE_QMGR_FLL; 3429 tr 52 M=MMU_RQE_QMGR_FLL; 3430 tr 71 M=MMU_RQE_QMGR_FLL TSE=F SLTH=T; 3431 tr 71 M=MMU_RQE_QMGR_FLL TSE=T SLTH=T; 3432 tr 71 M=MMU_RQE_QMGR_FLL TSE=T SLTH=F; 3433 echo " MMU_RQE_QMGR_QLL"; 3434 tr 50 M=MMU_RQE_QMGR_QLL; 3435 tr 51 M=MMU_RQE_QMGR_QLL; 3436 tr 52 M=MMU_RQE_QMGR_QLL; 3437 tr 71 M=MMU_RQE_QMGR_QLL TSE=F SLTH=T; 3438 tr 71 M=MMU_RQE_QMGR_QLL TSE=T SLTH=T; 3439 tr 71 M=MMU_RQE_QMGR_QLL TSE=T SLTH=F; 3440 echo " MMU_RQE_QUEUE_OP_NODE_MAP"; 3441 tr 50 M=MMU_RQE_QUEUE_OP_NODE_MAP; 3442 tr 51 M=MMU_RQE_QUEUE_OP_NODE_MAP; 3443 tr 52 M=MMU_RQE_QUEUE_OP_NODE_MAP; 3444 tr 71 M=MMU_RQE_QUEUE_OP_NODE_MAP TSE=F SLTH=T; 3445 tr 71 M=MMU_RQE_QUEUE_OP_NODE_MAP TSE=T SLTH=T; 3446 tr 71 M=MMU_RQE_QUEUE_OP_NODE_MAP TSE=T SLTH=F; 3447 echo " MMU_RQE_WORK_QUEUE"; 3448 tr 50 M=MMU_RQE_WORK_QUEUE; 3449 tr 51 M=MMU_RQE_WORK_QUEUE; 3450 tr 52 M=MMU_RQE_WORK_QUEUE; 3451 tr 71 M=MMU_RQE_WORK_QUEUE TSE=F SLTH=T; 3452 tr 71 M=MMU_RQE_WORK_QUEUE TSE=T SLTH=T; 3453 tr 71 M=MMU_RQE_WORK_QUEUE TSE=T SLTH=F; 3454 echo " MMU_THDO_CTRO_UC_DTYPE"; 3455 tr 50 M=MMU_THDO_CTRO_UC_DTYPE; 3456 tr 51 M=MMU_THDO_CTRO_UC_DTYPE; 3457 tr 52 M=MMU_THDO_CTRO_UC_DTYPE; 3458 tr 71 M=MMU_THDO_CTRO_UC_DTYPE TSE=F SLTH=T; 3459 tr 71 M=MMU_THDO_CTRO_UC_DTYPE TSE=T SLTH=T; 3460 tr 71 M=MMU_THDO_CTRO_UC_DTYPE TSE=T SLTH=F; 3461 echo " MMU_THDO_CTRO_UC_PKT_STORE"; 3462 tr 50 M=MMU_THDO_CTRO_UC_PKT_STORE; 3463 tr 51 M=MMU_THDO_CTRO_UC_PKT_STORE; 3464 tr 52 M=MMU_THDO_CTRO_UC_PKT_STORE; 3465 tr 71 M=MMU_THDO_CTRO_UC_PKT_STORE TSE=F SLTH=T; 3466 tr 71 M=MMU_THDO_CTRO_UC_PKT_STORE TSE=T SLTH=T; 3467 tr 71 M=MMU_THDO_CTRO_UC_PKT_STORE TSE=T SLTH=F; 3468 echo " MMU_THDO_OPNCONFIG_CELL"; 3469 tr 50 M=MMU_THDO_OPNCONFIG_CELL; 3470 tr 51 M=MMU_THDO_OPNCONFIG_CELL; 3471 tr 52 M=MMU_THDO_OPNCONFIG_CELL; 3472 tr 71 M=MMU_THDO_OPNCONFIG_CELL TSE=F SLTH=T; 3473 tr 71 M=MMU_THDO_OPNCONFIG_CELL TSE=T SLTH=T; 3474 tr 71 M=MMU_THDO_OPNCONFIG_CELL TSE=T SLTH=F; 3475 echo " MMU_THDO_OPNCONFIG_QENTRY"; 3476 tr 50 M=MMU_THDO_OPNCONFIG_QENTRY; 3477 tr 51 M=MMU_THDO_OPNCONFIG_QENTRY; 3478 tr 52 M=MMU_THDO_OPNCONFIG_QENTRY; 3479 tr 71 M=MMU_THDO_OPNCONFIG_QENTRY TSE=F SLTH=T; 3480 tr 71 M=MMU_THDO_OPNCONFIG_QENTRY TSE=T SLTH=T; 3481 tr 71 M=MMU_THDO_OPNCONFIG_QENTRY TSE=T SLTH=F; 3482 echo " MMU_THDO_OPNCOUNT_CELL"; 3483 tr 50 M=MMU_THDO_OPNCOUNT_CELL; 3484 tr 51 M=MMU_THDO_OPNCOUNT_CELL; 3485 tr 52 M=MMU_THDO_OPNCOUNT_CELL; 3486 tr 71 M=MMU_THDO_OPNCOUNT_CELL TSE=F SLTH=T; 3487 tr 71 M=MMU_THDO_OPNCOUNT_CELL TSE=T SLTH=T; 3488 tr 71 M=MMU_THDO_OPNCOUNT_CELL TSE=T SLTH=F; 3489 echo " MMU_THDO_OPNOFFSET_CELL"; 3490 tr 50 M=MMU_THDO_OPNOFFSET_CELL; 3491 tr 51 M=MMU_THDO_OPNOFFSET_CELL; 3492 tr 52 M=MMU_THDO_OPNOFFSET_CELL; 3493 tr 71 M=MMU_THDO_OPNOFFSET_CELL TSE=F SLTH=T; 3494 tr 71 M=MMU_THDO_OPNOFFSET_CELL TSE=T SLTH=T; 3495 tr 71 M=MMU_THDO_OPNOFFSET_CELL TSE=T SLTH=F; 3496 echo " MMU_THDO_OPNOFFSET_QENTRY"; 3497 tr 50 M=MMU_THDO_OPNOFFSET_QENTRY; 3498 tr 51 M=MMU_THDO_OPNOFFSET_QENTRY; 3499 tr 52 M=MMU_THDO_OPNOFFSET_QENTRY; 3500 tr 71 M=MMU_THDO_OPNOFFSET_QENTRY TSE=F SLTH=T; 3501 tr 71 M=MMU_THDO_OPNOFFSET_QENTRY TSE=T SLTH=T; 3502 tr 71 M=MMU_THDO_OPNOFFSET_QENTRY TSE=T SLTH=F; 3503 echo " MMU_THDO_OPNSTATUS_CELL"; 3504 tr 50 M=MMU_THDO_OPNSTATUS_CELL; 3505 tr 51 M=MMU_THDO_OPNSTATUS_CELL; 3506 tr 52 M=MMU_THDO_OPNSTATUS_CELL; 3507 tr 71 M=MMU_THDO_OPNSTATUS_CELL TSE=F SLTH=T; 3508 tr 71 M=MMU_THDO_OPNSTATUS_CELL TSE=T SLTH=T; 3509 tr 71 M=MMU_THDO_OPNSTATUS_CELL TSE=T SLTH=F; 3510 echo " MMU_THDO_OPNSTATUS_QENTRY"; 3511 tr 50 M=MMU_THDO_OPNSTATUS_QENTRY; 3512 tr 51 M=MMU_THDO_OPNSTATUS_QENTRY; 3513 tr 52 M=MMU_THDO_OPNSTATUS_QENTRY; 3514 tr 71 M=MMU_THDO_OPNSTATUS_QENTRY TSE=F SLTH=T; 3515 tr 71 M=MMU_THDO_OPNSTATUS_QENTRY TSE=T SLTH=T; 3516 tr 71 M=MMU_THDO_OPNSTATUS_QENTRY TSE=T SLTH=F; 3517 echo " MMU_THDO_QCONFIG_CELL"; 3518 tr 50 M=MMU_THDO_QCONFIG_CELL; 3519 tr 51 M=MMU_THDO_QCONFIG_CELL; 3520 tr 52 M=MMU_THDO_QCONFIG_CELL; 3521 tr 71 M=MMU_THDO_QCONFIG_CELL TSE=F SLTH=T; 3522 tr 71 M=MMU_THDO_QCONFIG_CELL TSE=T SLTH=T; 3523 tr 71 M=MMU_THDO_QCONFIG_CELL TSE=T SLTH=F; 3524 echo " MMU_THDO_QCONFIG_QENTRY"; 3525 tr 50 M=MMU_THDO_QCONFIG_QENTRY; 3526 tr 51 M=MMU_THDO_QCONFIG_QENTRY; 3527 tr 52 M=MMU_THDO_QCONFIG_QENTRY; 3528 tr 71 M=MMU_THDO_QCONFIG_QENTRY TSE=F SLTH=T; 3529 tr 71 M=MMU_THDO_QCONFIG_QENTRY TSE=T SLTH=T; 3530 tr 71 M=MMU_THDO_QCONFIG_QENTRY TSE=T SLTH=F; 3531 echo " MMU_THDO_QCOUNT_CELL_0"; 3532 tr 50 M=MMU_THDO_QCOUNT_CELL_0; 3533 tr 51 M=MMU_THDO_QCOUNT_CELL_0; 3534 tr 52 M=MMU_THDO_QCOUNT_CELL_0; 3535 tr 71 M=MMU_THDO_QCOUNT_CELL_0 TSE=F SLTH=T; 3536 tr 71 M=MMU_THDO_QCOUNT_CELL_0 TSE=T SLTH=T; 3537 tr 71 M=MMU_THDO_QCOUNT_CELL_0 TSE=T SLTH=F; 3538 echo " MMU_THDO_QOFFSET_CELL"; 3539 tr 50 M=MMU_THDO_QOFFSET_CELL; 3540 tr 51 M=MMU_THDO_QOFFSET_CELL; 3541 tr 52 M=MMU_THDO_QOFFSET_CELL; 3542 tr 71 M=MMU_THDO_QOFFSET_CELL TSE=F SLTH=T; 3543 tr 71 M=MMU_THDO_QOFFSET_CELL TSE=T SLTH=T; 3544 tr 71 M=MMU_THDO_QOFFSET_CELL TSE=T SLTH=F; 3545 echo " MMU_THDO_QOFFSET_QENTRY"; 3546 tr 50 M=MMU_THDO_QOFFSET_QENTRY; 3547 tr 51 M=MMU_THDO_QOFFSET_QENTRY; 3548 tr 52 M=MMU_THDO_QOFFSET_QENTRY; 3549 tr 71 M=MMU_THDO_QOFFSET_QENTRY TSE=F SLTH=T; 3550 tr 71 M=MMU_THDO_QOFFSET_QENTRY TSE=T SLTH=T; 3551 tr 71 M=MMU_THDO_QOFFSET_QENTRY TSE=T SLTH=F; 3552 echo " MMU_THDO_QRESET_VALUE_CELL_0"; 3553 tr 50 M=MMU_THDO_QRESET_VALUE_CELL_0; 3554 tr 51 M=MMU_THDO_QRESET_VALUE_CELL_0; 3555 tr 52 M=MMU_THDO_QRESET_VALUE_CELL_0; 3556 tr 71 M=MMU_THDO_QRESET_VALUE_CELL_0 TSE=F SLTH=T; 3557 tr 71 M=MMU_THDO_QRESET_VALUE_CELL_0 TSE=T SLTH=T; 3558 tr 71 M=MMU_THDO_QRESET_VALUE_CELL_0 TSE=T SLTH=F; 3559 echo " MMU_THDO_QRESET_VALUE_QENTRY_0"; 3560 tr 50 M=MMU_THDO_QRESET_VALUE_QENTRY_0; 3561 tr 51 M=MMU_THDO_QRESET_VALUE_QENTRY_0; 3562 tr 52 M=MMU_THDO_QRESET_VALUE_QENTRY_0; 3563 tr 71 M=MMU_THDO_QRESET_VALUE_QENTRY_0 TSE=F SLTH=T; 3564 tr 71 M=MMU_THDO_QRESET_VALUE_QENTRY_0 TSE=T SLTH=T; 3565 tr 71 M=MMU_THDO_QRESET_VALUE_QENTRY_0 TSE=T SLTH=F; 3566 echo " MMU_THDO_QSTATUS_CELL_0"; 3567 tr 50 M=MMU_THDO_QSTATUS_CELL_0; 3568 tr 51 M=MMU_THDO_QSTATUS_CELL_0; 3569 tr 52 M=MMU_THDO_QSTATUS_CELL_0; 3570 tr 71 M=MMU_THDO_QSTATUS_CELL_0 TSE=F SLTH=T; 3571 tr 71 M=MMU_THDO_QSTATUS_CELL_0 TSE=T SLTH=T; 3572 tr 71 M=MMU_THDO_QSTATUS_CELL_0 TSE=T SLTH=F; 3573 echo " MMU_THDO_QSTATUS_QENTRY_0"; 3574 tr 50 M=MMU_THDO_QSTATUS_QENTRY_0; 3575 tr 51 M=MMU_THDO_QSTATUS_QENTRY_0; 3576 tr 52 M=MMU_THDO_QSTATUS_QENTRY_0; 3577 tr 71 M=MMU_THDO_QSTATUS_QENTRY_0 TSE=F SLTH=T; 3578 tr 71 M=MMU_THDO_QSTATUS_QENTRY_0 TSE=T SLTH=T; 3579 tr 71 M=MMU_THDO_QSTATUS_QENTRY_0 TSE=T SLTH=F; 3580 echo " MMU_TOQ_EOPE_TBL"; 3581 tr 50 M=MMU_TOQ_EOPE_TBL; 3582 tr 51 M=MMU_TOQ_EOPE_TBL; 3583 tr 52 M=MMU_TOQ_EOPE_TBL; 3584 tr 71 M=MMU_TOQ_EOPE_TBL TSE=F SLTH=T; 3585 tr 71 M=MMU_TOQ_EOPE_TBL TSE=T SLTH=T; 3586 tr 71 M=MMU_TOQ_EOPE_TBL TSE=T SLTH=F; 3587 echo " MMU_TOQ_PORT_STATE_MEM"; 3588 tr 50 M=MMU_TOQ_PORT_STATE_MEM; 3589 tr 51 M=MMU_TOQ_PORT_STATE_MEM; 3590 tr 52 M=MMU_TOQ_PORT_STATE_MEM; 3591 tr 71 M=MMU_TOQ_PORT_STATE_MEM TSE=F SLTH=T; 3592 tr 71 M=MMU_TOQ_PORT_STATE_MEM TSE=T SLTH=T; 3593 tr 71 M=MMU_TOQ_PORT_STATE_MEM TSE=T SLTH=F; 3594 echo " MMU_TOQ_QPACK_MODE"; 3595 tr 50 M=MMU_TOQ_QPACK_MODE; 3596 tr 51 M=MMU_TOQ_QPACK_MODE; 3597 tr 52 M=MMU_TOQ_QPACK_MODE; 3598 tr 71 M=MMU_TOQ_QPACK_MODE TSE=F SLTH=T; 3599 tr 71 M=MMU_TOQ_QPACK_MODE TSE=T SLTH=T; 3600 tr 71 M=MMU_TOQ_QPACK_MODE TSE=T SLTH=F; 3601 echo " MMU_TOQ_STATE_MEM0"; 3602 tr 50 M=MMU_TOQ_STATE_MEM0; 3603 tr 51 M=MMU_TOQ_STATE_MEM0; 3604 tr 52 M=MMU_TOQ_STATE_MEM0; 3605 tr 71 M=MMU_TOQ_STATE_MEM0 TSE=F SLTH=T; 3606 tr 71 M=MMU_TOQ_STATE_MEM0 TSE=T SLTH=T; 3607 tr 71 M=MMU_TOQ_STATE_MEM0 TSE=T SLTH=F; 3608 echo " MMU_TOQ_STATE_MEM1"; 3609 tr 50 M=MMU_TOQ_STATE_MEM1; 3610 tr 51 M=MMU_TOQ_STATE_MEM1; 3611 tr 52 M=MMU_TOQ_STATE_MEM1; 3612 tr 71 M=MMU_TOQ_STATE_MEM1 TSE=F SLTH=T; 3613 tr 71 M=MMU_TOQ_STATE_MEM1 TSE=T SLTH=T; 3614 tr 71 M=MMU_TOQ_STATE_MEM1 TSE=T SLTH=F; 3615 echo " MMU_WRED_DROP_CURVE_PROFILE_0"; 3616 tr 50 M=MMU_WRED_DROP_CURVE_PROFILE_0; 3617 tr 51 M=MMU_WRED_DROP_CURVE_PROFILE_0; 3618 tr 52 M=MMU_WRED_DROP_CURVE_PROFILE_0; 3619 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_0 TSE=F SLTH=T; 3620 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_0 TSE=T SLTH=T; 3621 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_0 TSE=T SLTH=F; 3622 echo " MMU_WRED_DROP_CURVE_PROFILE_1"; 3623 tr 50 M=MMU_WRED_DROP_CURVE_PROFILE_1; 3624 tr 51 M=MMU_WRED_DROP_CURVE_PROFILE_1; 3625 tr 52 M=MMU_WRED_DROP_CURVE_PROFILE_1; 3626 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_1 TSE=F SLTH=T; 3627 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_1 TSE=T SLTH=T; 3628 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_1 TSE=T SLTH=F; 3629 echo " MMU_WRED_DROP_CURVE_PROFILE_2"; 3630 tr 50 M=MMU_WRED_DROP_CURVE_PROFILE_2; 3631 tr 51 M=MMU_WRED_DROP_CURVE_PROFILE_2; 3632 tr 52 M=MMU_WRED_DROP_CURVE_PROFILE_2; 3633 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_2 TSE=F SLTH=T; 3634 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_2 TSE=T SLTH=T; 3635 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_2 TSE=T SLTH=F; 3636 echo " MMU_WRED_DROP_CURVE_PROFILE_3"; 3637 tr 50 M=MMU_WRED_DROP_CURVE_PROFILE_3; 3638 tr 51 M=MMU_WRED_DROP_CURVE_PROFILE_3; 3639 tr 52 M=MMU_WRED_DROP_CURVE_PROFILE_3; 3640 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_3 TSE=F SLTH=T; 3641 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_3 TSE=T SLTH=T; 3642 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_3 TSE=T SLTH=F; 3643 echo " MMU_WRED_DROP_CURVE_PROFILE_4"; 3644 tr 50 M=MMU_WRED_DROP_CURVE_PROFILE_4; 3645 tr 51 M=MMU_WRED_DROP_CURVE_PROFILE_4; 3646 tr 52 M=MMU_WRED_DROP_CURVE_PROFILE_4; 3647 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_4 TSE=F SLTH=T; 3648 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_4 TSE=T SLTH=T; 3649 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_4 TSE=T SLTH=F; 3650 echo " MMU_WRED_DROP_CURVE_PROFILE_5"; 3651 tr 50 M=MMU_WRED_DROP_CURVE_PROFILE_5; 3652 tr 51 M=MMU_WRED_DROP_CURVE_PROFILE_5; 3653 tr 52 M=MMU_WRED_DROP_CURVE_PROFILE_5; 3654 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_5 TSE=F SLTH=T; 3655 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_5 TSE=T SLTH=T; 3656 tr 71 M=MMU_WRED_DROP_CURVE_PROFILE_5 TSE=T SLTH=F; 3657 echo " MMU_WRED_OPN_AVG_QSIZE_BUFFER"; 3658 tr 50 M=MMU_WRED_OPN_AVG_QSIZE_BUFFER; 3659 tr 51 M=MMU_WRED_OPN_AVG_QSIZE_BUFFER; 3660 tr 52 M=MMU_WRED_OPN_AVG_QSIZE_BUFFER; 3661 tr 71 M=MMU_WRED_OPN_AVG_QSIZE_BUFFER TSE=F SLTH=T; 3662 tr 71 M=MMU_WRED_OPN_AVG_QSIZE_BUFFER TSE=T SLTH=T; 3663 tr 71 M=MMU_WRED_OPN_AVG_QSIZE_BUFFER TSE=T SLTH=F; 3664 echo " MMU_WRED_OPN_AVG_QSIZE_QENTRY"; 3665 tr 50 M=MMU_WRED_OPN_AVG_QSIZE_QENTRY; 3666 tr 51 M=MMU_WRED_OPN_AVG_QSIZE_QENTRY; 3667 tr 52 M=MMU_WRED_OPN_AVG_QSIZE_QENTRY; 3668 tr 71 M=MMU_WRED_OPN_AVG_QSIZE_QENTRY TSE=F SLTH=T; 3669 tr 71 M=MMU_WRED_OPN_AVG_QSIZE_QENTRY TSE=T SLTH=T; 3670 tr 71 M=MMU_WRED_OPN_AVG_QSIZE_QENTRY TSE=T SLTH=F; 3671 echo " MMU_WRED_OPN_CONFIG_BUFFER"; 3672 tr 50 M=MMU_WRED_OPN_CONFIG_BUFFER; 3673 tr 51 M=MMU_WRED_OPN_CONFIG_BUFFER; 3674 tr 52 M=MMU_WRED_OPN_CONFIG_BUFFER; 3675 tr 71 M=MMU_WRED_OPN_CONFIG_BUFFER TSE=F SLTH=T; 3676 tr 71 M=MMU_WRED_OPN_CONFIG_BUFFER TSE=T SLTH=T; 3677 tr 71 M=MMU_WRED_OPN_CONFIG_BUFFER TSE=T SLTH=F; 3678 echo " MMU_WRED_OPN_CONFIG_QENTRY"; 3679 tr 50 M=MMU_WRED_OPN_CONFIG_QENTRY; 3680 tr 51 M=MMU_WRED_OPN_CONFIG_QENTRY; 3681 tr 52 M=MMU_WRED_OPN_CONFIG_QENTRY; 3682 tr 71 M=MMU_WRED_OPN_CONFIG_QENTRY TSE=F SLTH=T; 3683 tr 71 M=MMU_WRED_OPN_CONFIG_QENTRY TSE=T SLTH=T; 3684 tr 71 M=MMU_WRED_OPN_CONFIG_QENTRY TSE=T SLTH=F; 3685 echo " MMU_WRED_OPN_DROP_THD_DEQ"; 3686 tr 50 M=MMU_WRED_OPN_DROP_THD_DEQ; 3687 tr 51 M=MMU_WRED_OPN_DROP_THD_DEQ; 3688 tr 52 M=MMU_WRED_OPN_DROP_THD_DEQ; 3689 tr 71 M=MMU_WRED_OPN_DROP_THD_DEQ TSE=F SLTH=T; 3690 tr 71 M=MMU_WRED_OPN_DROP_THD_DEQ TSE=T SLTH=T; 3691 tr 71 M=MMU_WRED_OPN_DROP_THD_DEQ TSE=T SLTH=F; 3692 echo " MMU_WRED_OPN_DROP_THD_ENQ"; 3693 tr 50 M=MMU_WRED_OPN_DROP_THD_ENQ; 3694 tr 51 M=MMU_WRED_OPN_DROP_THD_ENQ; 3695 tr 52 M=MMU_WRED_OPN_DROP_THD_ENQ; 3696 tr 71 M=MMU_WRED_OPN_DROP_THD_ENQ TSE=F SLTH=T; 3697 tr 71 M=MMU_WRED_OPN_DROP_THD_ENQ TSE=T SLTH=T; 3698 tr 71 M=MMU_WRED_OPN_DROP_THD_ENQ TSE=T SLTH=F; 3699 echo " MMU_WRED_QUEUE_AVG_QSIZE_BUFFER"; 3700 tr 50 M=MMU_WRED_QUEUE_AVG_QSIZE_BUFFER; 3701 tr 51 M=MMU_WRED_QUEUE_AVG_QSIZE_BUFFER; 3702 tr 52 M=MMU_WRED_QUEUE_AVG_QSIZE_BUFFER; 3703 tr 71 M=MMU_WRED_QUEUE_AVG_QSIZE_BUFFER TSE=F SLTH=T; 3704 tr 71 M=MMU_WRED_QUEUE_AVG_QSIZE_BUFFER TSE=T SLTH=T; 3705 tr 71 M=MMU_WRED_QUEUE_AVG_QSIZE_BUFFER TSE=T SLTH=F; 3706 echo " MMU_WRED_QUEUE_AVG_QSIZE_QENTRY"; 3707 tr 50 M=MMU_WRED_QUEUE_AVG_QSIZE_QENTRY; 3708 tr 51 M=MMU_WRED_QUEUE_AVG_QSIZE_QENTRY; 3709 tr 52 M=MMU_WRED_QUEUE_AVG_QSIZE_QENTRY; 3710 tr 71 M=MMU_WRED_QUEUE_AVG_QSIZE_QENTRY TSE=F SLTH=T; 3711 tr 71 M=MMU_WRED_QUEUE_AVG_QSIZE_QENTRY TSE=T SLTH=T; 3712 tr 71 M=MMU_WRED_QUEUE_AVG_QSIZE_QENTRY TSE=T SLTH=F; 3713 echo " MMU_WRED_QUEUE_CONFIG_BUFFER"; 3714 tr 50 M=MMU_WRED_QUEUE_CONFIG_BUFFER; 3715 tr 51 M=MMU_WRED_QUEUE_CONFIG_BUFFER; 3716 tr 52 M=MMU_WRED_QUEUE_CONFIG_BUFFER; 3717 tr 71 M=MMU_WRED_QUEUE_CONFIG_BUFFER TSE=F SLTH=T; 3718 tr 71 M=MMU_WRED_QUEUE_CONFIG_BUFFER TSE=T SLTH=T; 3719 tr 71 M=MMU_WRED_QUEUE_CONFIG_BUFFER TSE=T SLTH=F; 3720 echo " MMU_WRED_QUEUE_CONFIG_QENTRY"; 3721 tr 50 M=MMU_WRED_QUEUE_CONFIG_QENTRY; 3722 tr 51 M=MMU_WRED_QUEUE_CONFIG_QENTRY; 3723 tr 52 M=MMU_WRED_QUEUE_CONFIG_QENTRY; 3724 tr 71 M=MMU_WRED_QUEUE_CONFIG_QENTRY TSE=F SLTH=T; 3725 tr 71 M=MMU_WRED_QUEUE_CONFIG_QENTRY TSE=T SLTH=T; 3726 tr 71 M=MMU_WRED_QUEUE_CONFIG_QENTRY TSE=T SLTH=F; 3727 echo " MMU_WRED_QUEUE_DROP_THD_DEQ"; 3728 tr 50 M=MMU_WRED_QUEUE_DROP_THD_DEQ; 3729 tr 51 M=MMU_WRED_QUEUE_DROP_THD_DEQ; 3730 tr 52 M=MMU_WRED_QUEUE_DROP_THD_DEQ; 3731 tr 71 M=MMU_WRED_QUEUE_DROP_THD_DEQ TSE=F SLTH=T; 3732 tr 71 M=MMU_WRED_QUEUE_DROP_THD_DEQ TSE=T SLTH=T; 3733 tr 71 M=MMU_WRED_QUEUE_DROP_THD_DEQ TSE=T SLTH=F; 3734 echo " MMU_WRED_QUEUE_DROP_THD_ENQ_0"; 3735 tr 50 M=MMU_WRED_QUEUE_DROP_THD_ENQ_0; 3736 tr 51 M=MMU_WRED_QUEUE_DROP_THD_ENQ_0; 3737 tr 52 M=MMU_WRED_QUEUE_DROP_THD_ENQ_0; 3738 tr 71 M=MMU_WRED_QUEUE_DROP_THD_ENQ_0 TSE=F SLTH=T; 3739 tr 71 M=MMU_WRED_QUEUE_DROP_THD_ENQ_0 TSE=T SLTH=T; 3740 tr 71 M=MMU_WRED_QUEUE_DROP_THD_ENQ_0 TSE=T SLTH=F; 3741 if !$?LIKE_BCM56456 \ 3742 'echo " MMU_WRED_QUEUE_DROP_THD_ENQ_1"; \ 3743 tr 50 M=MMU_WRED_QUEUE_DROP_THD_ENQ_1; \ 3744 tr 51 M=MMU_WRED_QUEUE_DROP_THD_ENQ_1; \ 3745 tr 52 M=MMU_WRED_QUEUE_DROP_THD_ENQ_1; \ 3746 tr 71 M=MMU_WRED_QUEUE_DROP_THD_ENQ_1 TSE=F SLTH=T; \ 3747 tr 71 M=MMU_WRED_QUEUE_DROP_THD_ENQ_1 TSE=T SLTH=T; \ 3748 tr 71 M=MMU_WRED_QUEUE_DROP_THD_ENQ_1 TSE=T SLTH=F; \ 3749 $done;' 3750 echo " MMU_WRED_QUEUE_OP_NODE_MAP"; 3751 tr 50 M=MMU_WRED_QUEUE_OP_NODE_MAP; 3752 tr 51 M=MMU_WRED_QUEUE_OP_NODE_MAP; 3753 tr 52 M=MMU_WRED_QUEUE_OP_NODE_MAP; 3754 tr 71 M=MMU_WRED_QUEUE_OP_NODE_MAP TSE=F SLTH=T; 3755 tr 71 M=MMU_WRED_QUEUE_OP_NODE_MAP TSE=T SLTH=T; 3756 tr 71 M=MMU_WRED_QUEUE_OP_NODE_MAP TSE=T SLTH=F; 3757 echo " MODPORT_MAP_M0"; 3758 tr 50 M=MODPORT_MAP_M0; 3759 tr 51 M=MODPORT_MAP_M0; 3760 tr 52 M=MODPORT_MAP_M0; 3761 tr 71 M=MODPORT_MAP_M0 TSE=F SLTH=T; 3762 tr 71 M=MODPORT_MAP_M0 TSE=T SLTH=T; 3763 tr 71 M=MODPORT_MAP_M0 TSE=T SLTH=F; 3764 echo " MODPORT_MAP_M1"; 3765 tr 50 M=MODPORT_MAP_M1; 3766 tr 51 M=MODPORT_MAP_M1; 3767 tr 52 M=MODPORT_MAP_M1; 3768 tr 71 M=MODPORT_MAP_M1 TSE=F SLTH=T; 3769 tr 71 M=MODPORT_MAP_M1 TSE=T SLTH=T; 3770 tr 71 M=MODPORT_MAP_M1 TSE=T SLTH=F; 3771 echo " MODPORT_MAP_M2"; 3772 tr 50 M=MODPORT_MAP_M2; 3773 tr 51 M=MODPORT_MAP_M2; 3774 tr 52 M=MODPORT_MAP_M2; 3775 tr 71 M=MODPORT_MAP_M2 TSE=F SLTH=T; 3776 tr 71 M=MODPORT_MAP_M2 TSE=T SLTH=T; 3777 tr 71 M=MODPORT_MAP_M2 TSE=T SLTH=F; 3778 echo " MODPORT_MAP_M3"; 3779 tr 50 M=MODPORT_MAP_M3; 3780 tr 51 M=MODPORT_MAP_M3; 3781 tr 52 M=MODPORT_MAP_M3; 3782 tr 71 M=MODPORT_MAP_M3 TSE=F SLTH=T; 3783 tr 71 M=MODPORT_MAP_M3 TSE=T SLTH=T; 3784 tr 71 M=MODPORT_MAP_M3 TSE=T SLTH=F; 3785 kt2sanity_ecc_off.soc 3786 echo " MODPORT_MAP_MIRROR"; 3787 tr 50 M=MODPORT_MAP_MIRROR; 3788 tr 51 M=MODPORT_MAP_MIRROR; 3789 tr 52 M=MODPORT_MAP_MIRROR; 3790 tr 71 M=MODPORT_MAP_MIRROR TSE=F SLTH=T; 3791 tr 71 M=MODPORT_MAP_MIRROR TSE=T SLTH=T; 3792 tr 71 M=MODPORT_MAP_MIRROR TSE=T SLTH=F; 3793 echo " MODPORT_MAP_SW"; 3794 tr 50 M=MODPORT_MAP_SW; 3795 tr 51 M=MODPORT_MAP_SW; 3796 tr 52 M=MODPORT_MAP_SW; 3797 tr 71 M=MODPORT_MAP_SW TSE=F SLTH=T; 3798 tr 71 M=MODPORT_MAP_SW TSE=T SLTH=T; 3799 tr 71 M=MODPORT_MAP_SW TSE=T SLTH=F; 3800 echo " MPLS_ENTRY"; 3801 tr 50 M=MPLS_ENTRY; 3802 tr 51 M=MPLS_ENTRY; 3803 tr 52 M=MPLS_ENTRY; 3804 tr 71 M=MPLS_ENTRY TSE=F SLTH=T; 3805 tr 71 M=MPLS_ENTRY TSE=T SLTH=T; 3806 tr 71 M=MPLS_ENTRY TSE=T SLTH=F; 3807 echo " MULTIPASS_LOOPBACK_BITMAP"; 3808 tr 50 M=MULTIPASS_LOOPBACK_BITMAP; 3809 #tr 51 M=MULTIPASS_LOOPBACK_BITMAP; 3810 #tr 52 M=MULTIPASS_LOOPBACK_BITMAP; 3811 tr 71 M=MULTIPASS_LOOPBACK_BITMAP TSE=F SLTH=T; 3812 tr 71 M=MULTIPASS_LOOPBACK_BITMAP TSE=T SLTH=T; 3813 tr 71 M=MULTIPASS_LOOPBACK_BITMAP TSE=T SLTH=F; 3814 echo " MY_STATION_TCAM"; 3815 tr 50 M=MY_STATION_TCAM; 3816 tr 51 M=MY_STATION_TCAM; 3817 tr 52 M=MY_STATION_TCAM; 3818 tr 71 M=MY_STATION_TCAM TSE=F SLTH=T; 3819 tr 71 M=MY_STATION_TCAM TSE=T SLTH=T; 3820 tr 71 M=MY_STATION_TCAM TSE=T SLTH=F; 3821 echo " MY_STATION_TCAM_DATA_ONLY"; 3822 tr 50 M=MY_STATION_TCAM_DATA_ONLY; 3823 tr 51 M=MY_STATION_TCAM_DATA_ONLY; 3824 tr 52 M=MY_STATION_TCAM_DATA_ONLY; 3825 tr 71 M=MY_STATION_TCAM_DATA_ONLY TSE=F SLTH=T; 3826 tr 71 M=MY_STATION_TCAM_DATA_ONLY TSE=T SLTH=T; 3827 tr 71 M=MY_STATION_TCAM_DATA_ONLY TSE=T SLTH=F; 3828 echo " MY_STATION_TCAM_ENTRY_ONLY"; 3829 tr 50 M=MY_STATION_TCAM_ENTRY_ONLY; 3830 tr 51 M=MY_STATION_TCAM_ENTRY_ONLY; 3831 tr 52 M=MY_STATION_TCAM_ENTRY_ONLY; 3832 tr 71 M=MY_STATION_TCAM_ENTRY_ONLY TSE=F SLTH=T; 3833 tr 71 M=MY_STATION_TCAM_ENTRY_ONLY TSE=T SLTH=T; 3834 tr 71 M=MY_STATION_TCAM_ENTRY_ONLY TSE=T SLTH=F; 3835 echo " NHI_GROUP_TC_PROFILE"; 3836 tr 50 M=NHI_GROUP_TC_PROFILE; 3837 tr 51 M=NHI_GROUP_TC_PROFILE; 3838 tr 52 M=NHI_GROUP_TC_PROFILE; 3839 tr 71 M=NHI_GROUP_TC_PROFILE TSE=F SLTH=T; 3840 tr 71 M=NHI_GROUP_TC_PROFILE TSE=T SLTH=T; 3841 tr 71 M=NHI_GROUP_TC_PROFILE TSE=T SLTH=F; 3842 echo " NONUCAST_TRUNK_BLOCK_MASK"; 3843 tr 50 M=NONUCAST_TRUNK_BLOCK_MASK; 3844 tr 51 M=NONUCAST_TRUNK_BLOCK_MASK; 3845 tr 52 M=NONUCAST_TRUNK_BLOCK_MASK; 3846 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=F SLTH=T; 3847 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=T SLTH=T; 3848 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=T SLTH=F; 3849 echo " OAM_LM_COUNTERS_0"; 3850 tr 50 M=OAM_LM_COUNTERS_0; 3851 tr 51 M=OAM_LM_COUNTERS_0; 3852 tr 52 M=OAM_LM_COUNTERS_0; 3853 tr 71 M=OAM_LM_COUNTERS_0 TSE=F SLTH=T; 3854 tr 71 M=OAM_LM_COUNTERS_0 TSE=T SLTH=T; 3855 tr 71 M=OAM_LM_COUNTERS_0 TSE=T SLTH=F; 3856 echo " OAM_LM_COUNTERS_1"; 3857 tr 50 M=OAM_LM_COUNTERS_1; 3858 tr 51 M=OAM_LM_COUNTERS_1; 3859 tr 52 M=OAM_LM_COUNTERS_1; 3860 tr 71 M=OAM_LM_COUNTERS_1 TSE=F SLTH=T; 3861 tr 71 M=OAM_LM_COUNTERS_1 TSE=T SLTH=T; 3862 tr 71 M=OAM_LM_COUNTERS_1 TSE=T SLTH=F; 3863 echo " OAM_OPCODE_CONTROL_PROFILE"; 3864 tr 50 M=OAM_OPCODE_CONTROL_PROFILE; 3865 tr 51 M=OAM_OPCODE_CONTROL_PROFILE; 3866 tr 52 M=OAM_OPCODE_CONTROL_PROFILE; 3867 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=F SLTH=T; 3868 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=T; 3869 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=F; 3870 echo " PHB2_COS_MAP"; 3871 tr 50 M=PHB2_COS_MAP; 3872 tr 51 M=PHB2_COS_MAP; 3873 tr 52 M=PHB2_COS_MAP; 3874 tr 71 M=PHB2_COS_MAP TSE=F SLTH=T; 3875 tr 71 M=PHB2_COS_MAP TSE=T SLTH=T; 3876 tr 71 M=PHB2_COS_MAP TSE=T SLTH=F; 3877 echo " PHYSICAL_PORT_BASE_QUEUE"; 3878 tr 50 M=PHYSICAL_PORT_BASE_QUEUE; 3879 tr 51 M=PHYSICAL_PORT_BASE_QUEUE; 3880 tr 52 M=PHYSICAL_PORT_BASE_QUEUE; 3881 tr 71 M=PHYSICAL_PORT_BASE_QUEUE TSE=F SLTH=T; 3882 tr 71 M=PHYSICAL_PORT_BASE_QUEUE TSE=T SLTH=T; 3883 tr 71 M=PHYSICAL_PORT_BASE_QUEUE TSE=T SLTH=F; 3884 echo " PORT_BRIDGE_BMAP"; 3885 tr 50 M=PORT_BRIDGE_BMAP; 3886 #tr 51 M=PORT_BRIDGE_BMAP; 3887 #tr 52 M=PORT_BRIDGE_BMAP; 3888 tr 71 M=PORT_BRIDGE_BMAP TSE=F SLTH=T; 3889 tr 71 M=PORT_BRIDGE_BMAP TSE=T SLTH=T; 3890 tr 71 M=PORT_BRIDGE_BMAP TSE=T SLTH=F; 3891 echo " PORT_BRIDGE_MIRROR_BMAP"; 3892 tr 50 M=PORT_BRIDGE_MIRROR_BMAP; 3893 #tr 51 M=PORT_BRIDGE_MIRROR_BMAP; 3894 #tr 52 M=PORT_BRIDGE_MIRROR_BMAP; 3895 tr 71 M=PORT_BRIDGE_MIRROR_BMAP TSE=F SLTH=T; 3896 tr 71 M=PORT_BRIDGE_MIRROR_BMAP TSE=T SLTH=T; 3897 tr 71 M=PORT_BRIDGE_MIRROR_BMAP TSE=T SLTH=F; 3898 echo " PORT_CBL_TABLE"; 3899 tr 50 M=PORT_CBL_TABLE; 3900 tr 51 M=PORT_CBL_TABLE; 3901 tr 52 M=PORT_CBL_TABLE; 3902 tr 71 M=PORT_CBL_TABLE TSE=F SLTH=T; 3903 tr 71 M=PORT_CBL_TABLE TSE=T SLTH=T; 3904 tr 71 M=PORT_CBL_TABLE TSE=T SLTH=F; 3905 echo " PORT_CBL_TABLE_MODBASE"; 3906 tr 50 M=PORT_CBL_TABLE_MODBASE; 3907 tr 51 M=PORT_CBL_TABLE_MODBASE; 3908 tr 52 M=PORT_CBL_TABLE_MODBASE; 3909 tr 71 M=PORT_CBL_TABLE_MODBASE TSE=F SLTH=T; 3910 tr 71 M=PORT_CBL_TABLE_MODBASE TSE=T SLTH=T; 3911 tr 71 M=PORT_CBL_TABLE_MODBASE TSE=T SLTH=F; 3912 echo " PORT_COS_MAP"; 3913 tr 50 M=PORT_COS_MAP; 3914 tr 51 M=PORT_COS_MAP; 3915 tr 52 M=PORT_COS_MAP; 3916 tr 71 M=PORT_COS_MAP TSE=F SLTH=T; 3917 tr 71 M=PORT_COS_MAP TSE=T SLTH=T; 3918 tr 71 M=PORT_COS_MAP TSE=T SLTH=F; 3919 echo " PORT_LAG_FAILOVER_SET"; 3920 tr 50 M=PORT_LAG_FAILOVER_SET; 3921 tr 51 M=PORT_LAG_FAILOVER_SET; 3922 tr 52 M=PORT_LAG_FAILOVER_SET; 3923 tr 71 M=PORT_LAG_FAILOVER_SET TSE=F SLTH=T; 3924 tr 71 M=PORT_LAG_FAILOVER_SET TSE=T SLTH=T; 3925 tr 71 M=PORT_LAG_FAILOVER_SET TSE=T SLTH=F; 3926 echo " PORT_OR_TRUNK_MAC_COUNT"; 3927 tr 50 M=PORT_OR_TRUNK_MAC_COUNT; 3928 tr 51 M=PORT_OR_TRUNK_MAC_COUNT; 3929 tr 52 M=PORT_OR_TRUNK_MAC_COUNT; 3930 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=F SLTH=T; 3931 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=T SLTH=T; 3932 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=T SLTH=F; 3933 echo " PORT_OR_TRUNK_MAC_LIMIT"; 3934 tr 50 M=PORT_OR_TRUNK_MAC_LIMIT; 3935 tr 51 M=PORT_OR_TRUNK_MAC_LIMIT; 3936 tr 52 M=PORT_OR_TRUNK_MAC_LIMIT; 3937 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=F SLTH=T; 3938 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=T SLTH=T; 3939 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=T SLTH=F; 3940 echo " PORT_TAB"; 3941 tr 50 M=PORT_TAB; 3942 tr 51 M=PORT_TAB; 3943 tr 52 M=PORT_TAB; 3944 tr 71 M=PORT_TAB TSE=F SLTH=T; 3945 tr 71 M=PORT_TAB TSE=T SLTH=T; 3946 tr 71 M=PORT_TAB TSE=T SLTH=F; 3947 echo " PP_PORT_GPP_TRANSLATION_1"; 3948 tr 50 M=PP_PORT_GPP_TRANSLATION_1; 3949 #tr 51 M=PP_PORT_GPP_TRANSLATION_1; 3950 #tr 52 M=PP_PORT_GPP_TRANSLATION_1; 3951 tr 71 M=PP_PORT_GPP_TRANSLATION_1 TSE=F SLTH=T; 3952 tr 71 M=PP_PORT_GPP_TRANSLATION_1 TSE=T SLTH=T; 3953 tr 71 M=PP_PORT_GPP_TRANSLATION_1 TSE=T SLTH=F; 3954 echo " PP_PORT_GPP_TRANSLATION_2"; 3955 tr 50 M=PP_PORT_GPP_TRANSLATION_2; 3956 #tr 51 M=PP_PORT_GPP_TRANSLATION_2; 3957 #tr 52 M=PP_PORT_GPP_TRANSLATION_2; 3958 tr 71 M=PP_PORT_GPP_TRANSLATION_2 TSE=F SLTH=T; 3959 tr 71 M=PP_PORT_GPP_TRANSLATION_2 TSE=T SLTH=T; 3960 tr 71 M=PP_PORT_GPP_TRANSLATION_2 TSE=T SLTH=F; 3961 echo " PP_PORT_GPP_TRANSLATION_3"; 3962 tr 50 M=PP_PORT_GPP_TRANSLATION_3; 3963 #tr 51 M=PP_PORT_GPP_TRANSLATION_3; 3964 #tr 52 M=PP_PORT_GPP_TRANSLATION_3; 3965 tr 71 M=PP_PORT_GPP_TRANSLATION_3 TSE=F SLTH=T; 3966 tr 71 M=PP_PORT_GPP_TRANSLATION_3 TSE=T SLTH=T; 3967 tr 71 M=PP_PORT_GPP_TRANSLATION_3 TSE=T SLTH=F; 3968 echo " PP_PORT_GPP_TRANSLATION_4"; 3969 tr 50 M=PP_PORT_GPP_TRANSLATION_4; 3970 #tr 51 M=PP_PORT_GPP_TRANSLATION_4; 3971 #tr 52 M=PP_PORT_GPP_TRANSLATION_4; 3972 tr 71 M=PP_PORT_GPP_TRANSLATION_4 TSE=F SLTH=T; 3973 tr 71 M=PP_PORT_GPP_TRANSLATION_4 TSE=T SLTH=T; 3974 tr 71 M=PP_PORT_GPP_TRANSLATION_4 TSE=T SLTH=F; 3975 echo " PP_PORT_TO_PHYSICAL_PORT_MAP"; 3976 tr 50 M=PP_PORT_TO_PHYSICAL_PORT_MAP; 3977 tr 51 M=PP_PORT_TO_PHYSICAL_PORT_MAP; 3978 tr 52 M=PP_PORT_TO_PHYSICAL_PORT_MAP; 3979 tr 71 M=PP_PORT_TO_PHYSICAL_PORT_MAP TSE=F SLTH=T; 3980 tr 71 M=PP_PORT_TO_PHYSICAL_PORT_MAP TSE=T SLTH=T; 3981 tr 71 M=PP_PORT_TO_PHYSICAL_PORT_MAP TSE=T SLTH=F; 3982 echo " PTP_LABEL_RANGE_PROFILE_TABLE"; 3983 tr 50 M=PTP_LABEL_RANGE_PROFILE_TABLE; 3984 tr 51 M=PTP_LABEL_RANGE_PROFILE_TABLE; 3985 tr 52 M=PTP_LABEL_RANGE_PROFILE_TABLE; 3986 tr 71 M=PTP_LABEL_RANGE_PROFILE_TABLE TSE=F SLTH=T; 3987 tr 71 M=PTP_LABEL_RANGE_PROFILE_TABLE TSE=T SLTH=T; 3988 tr 71 M=PTP_LABEL_RANGE_PROFILE_TABLE TSE=T SLTH=F; 3989 echo " RMEP"; 3990 tr 50 M=RMEP; 3991 tr 51 M=RMEP; 3992 tr 52 M=RMEP; 3993 tr 71 M=RMEP TSE=F SLTH=T; 3994 tr 71 M=RMEP TSE=T SLTH=T; 3995 tr 71 M=RMEP TSE=T SLTH=F; 3996 echo " RTAG7_FLOW_BASED_HASH"; 3997 tr 50 M=RTAG7_FLOW_BASED_HASH; 3998 tr 51 M=RTAG7_FLOW_BASED_HASH; 3999 tr 52 M=RTAG7_FLOW_BASED_HASH; 4000 tr 71 M=RTAG7_FLOW_BASED_HASH TSE=F SLTH=T; 4001 tr 71 M=RTAG7_FLOW_BASED_HASH TSE=T SLTH=T; 4002 tr 71 M=RTAG7_FLOW_BASED_HASH TSE=T SLTH=F; 4003 echo " RTAG7_PORT_BASED_HASH"; 4004 tr 50 M=RTAG7_PORT_BASED_HASH; 4005 tr 51 M=RTAG7_PORT_BASED_HASH; 4006 tr 52 M=RTAG7_PORT_BASED_HASH; 4007 tr 71 M=RTAG7_PORT_BASED_HASH TSE=F SLTH=T; 4008 tr 71 M=RTAG7_PORT_BASED_HASH TSE=T SLTH=T; 4009 tr 71 M=RTAG7_PORT_BASED_HASH TSE=T SLTH=F; 4010 #echo " RXLP_CHANNEL_CONTROL_BUFFER"; 4011 #tr 50 M=RXLP_CHANNEL_CONTROL_BUFFER; 4012 #tr 51 M=RXLP_CHANNEL_CONTROL_BUFFER; 4013 #tr 52 M=RXLP_CHANNEL_CONTROL_BUFFER; 4014 #tr 71 M=RXLP_CHANNEL_CONTROL_BUFFER TSE=F SLTH=T; 4015 #tr 71 M=RXLP_CHANNEL_CONTROL_BUFFER TSE=T SLTH=T; 4016 #tr 71 M=RXLP_CHANNEL_CONTROL_BUFFER TSE=T SLTH=F; 4017 echo " RXLP_DEBUG_COUNTER0"; 4018 tr 50 M=RXLP_DEBUG_COUNTER0; 4019 tr 51 M=RXLP_DEBUG_COUNTER0; 4020 tr 52 M=RXLP_DEBUG_COUNTER0; 4021 tr 71 M=RXLP_DEBUG_COUNTER0 TSE=F SLTH=T; 4022 tr 71 M=RXLP_DEBUG_COUNTER0 TSE=T SLTH=T; 4023 tr 71 M=RXLP_DEBUG_COUNTER0 TSE=T SLTH=F; 4024 echo " RXLP_DEBUG_COUNTER1"; 4025 tr 50 M=RXLP_DEBUG_COUNTER1; 4026 tr 51 M=RXLP_DEBUG_COUNTER1; 4027 tr 52 M=RXLP_DEBUG_COUNTER1; 4028 tr 71 M=RXLP_DEBUG_COUNTER1 TSE=F SLTH=T; 4029 tr 71 M=RXLP_DEBUG_COUNTER1 TSE=T SLTH=T; 4030 tr 71 M=RXLP_DEBUG_COUNTER1 TSE=T SLTH=F; 4031 echo " RXLP_DEBUG_COUNTER10"; 4032 tr 50 M=RXLP_DEBUG_COUNTER10; 4033 tr 51 M=RXLP_DEBUG_COUNTER10; 4034 tr 52 M=RXLP_DEBUG_COUNTER10; 4035 tr 71 M=RXLP_DEBUG_COUNTER10 TSE=F SLTH=T; 4036 tr 71 M=RXLP_DEBUG_COUNTER10 TSE=T SLTH=T; 4037 tr 71 M=RXLP_DEBUG_COUNTER10 TSE=T SLTH=F; 4038 echo " RXLP_DEBUG_COUNTER11"; 4039 tr 50 M=RXLP_DEBUG_COUNTER11; 4040 tr 51 M=RXLP_DEBUG_COUNTER11; 4041 tr 52 M=RXLP_DEBUG_COUNTER11; 4042 tr 71 M=RXLP_DEBUG_COUNTER11 TSE=F SLTH=T; 4043 tr 71 M=RXLP_DEBUG_COUNTER11 TSE=T SLTH=T; 4044 tr 71 M=RXLP_DEBUG_COUNTER11 TSE=T SLTH=F; 4045 echo " RXLP_DEBUG_COUNTER2"; 4046 tr 50 M=RXLP_DEBUG_COUNTER2; 4047 tr 51 M=RXLP_DEBUG_COUNTER2; 4048 tr 52 M=RXLP_DEBUG_COUNTER2; 4049 tr 71 M=RXLP_DEBUG_COUNTER2 TSE=F SLTH=T; 4050 tr 71 M=RXLP_DEBUG_COUNTER2 TSE=T SLTH=T; 4051 tr 71 M=RXLP_DEBUG_COUNTER2 TSE=T SLTH=F; 4052 echo " RXLP_DEBUG_COUNTER3"; 4053 tr 50 M=RXLP_DEBUG_COUNTER3; 4054 tr 51 M=RXLP_DEBUG_COUNTER3; 4055 tr 52 M=RXLP_DEBUG_COUNTER3; 4056 tr 71 M=RXLP_DEBUG_COUNTER3 TSE=F SLTH=T; 4057 tr 71 M=RXLP_DEBUG_COUNTER3 TSE=T SLTH=T; 4058 tr 71 M=RXLP_DEBUG_COUNTER3 TSE=T SLTH=F; 4059 echo " RXLP_DEBUG_COUNTER4"; 4060 tr 50 M=RXLP_DEBUG_COUNTER4; 4061 tr 51 M=RXLP_DEBUG_COUNTER4; 4062 tr 52 M=RXLP_DEBUG_COUNTER4; 4063 tr 71 M=RXLP_DEBUG_COUNTER4 TSE=F SLTH=T; 4064 tr 71 M=RXLP_DEBUG_COUNTER4 TSE=T SLTH=T; 4065 tr 71 M=RXLP_DEBUG_COUNTER4 TSE=T SLTH=F; 4066 echo " RXLP_DEBUG_COUNTER5"; 4067 tr 50 M=RXLP_DEBUG_COUNTER5; 4068 tr 51 M=RXLP_DEBUG_COUNTER5; 4069 tr 52 M=RXLP_DEBUG_COUNTER5; 4070 tr 71 M=RXLP_DEBUG_COUNTER5 TSE=F SLTH=T; 4071 tr 71 M=RXLP_DEBUG_COUNTER5 TSE=T SLTH=T; 4072 tr 71 M=RXLP_DEBUG_COUNTER5 TSE=T SLTH=F; 4073 echo " RXLP_DEBUG_COUNTER6"; 4074 tr 50 M=RXLP_DEBUG_COUNTER6; 4075 tr 51 M=RXLP_DEBUG_COUNTER6; 4076 tr 52 M=RXLP_DEBUG_COUNTER6; 4077 tr 71 M=RXLP_DEBUG_COUNTER6 TSE=F SLTH=T; 4078 tr 71 M=RXLP_DEBUG_COUNTER6 TSE=T SLTH=T; 4079 tr 71 M=RXLP_DEBUG_COUNTER6 TSE=T SLTH=F; 4080 echo " RXLP_DEBUG_COUNTER7"; 4081 tr 50 M=RXLP_DEBUG_COUNTER7; 4082 tr 51 M=RXLP_DEBUG_COUNTER7; 4083 tr 52 M=RXLP_DEBUG_COUNTER7; 4084 tr 71 M=RXLP_DEBUG_COUNTER7 TSE=F SLTH=T; 4085 tr 71 M=RXLP_DEBUG_COUNTER7 TSE=T SLTH=T; 4086 tr 71 M=RXLP_DEBUG_COUNTER7 TSE=T SLTH=F; 4087 echo " RXLP_DEBUG_COUNTER8"; 4088 tr 50 M=RXLP_DEBUG_COUNTER8; 4089 tr 51 M=RXLP_DEBUG_COUNTER8; 4090 tr 52 M=RXLP_DEBUG_COUNTER8; 4091 tr 71 M=RXLP_DEBUG_COUNTER8 TSE=F SLTH=T; 4092 tr 71 M=RXLP_DEBUG_COUNTER8 TSE=T SLTH=T; 4093 tr 71 M=RXLP_DEBUG_COUNTER8 TSE=T SLTH=F; 4094 echo " RXLP_DEBUG_COUNTER9"; 4095 tr 50 M=RXLP_DEBUG_COUNTER9; 4096 tr 51 M=RXLP_DEBUG_COUNTER9; 4097 tr 52 M=RXLP_DEBUG_COUNTER9; 4098 tr 71 M=RXLP_DEBUG_COUNTER9 TSE=F SLTH=T; 4099 tr 71 M=RXLP_DEBUG_COUNTER9 TSE=T SLTH=T; 4100 tr 71 M=RXLP_DEBUG_COUNTER9 TSE=T SLTH=F; 4101 echo " RXLP_DFC_MSG_BIT_REMAP_PORT_0"; 4102 tr 50 M=RXLP_DFC_MSG_BIT_REMAP_PORT_0; 4103 tr 51 M=RXLP_DFC_MSG_BIT_REMAP_PORT_0; 4104 tr 52 M=RXLP_DFC_MSG_BIT_REMAP_PORT_0; 4105 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_0 TSE=F SLTH=T; 4106 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_0 TSE=T SLTH=T; 4107 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_0 TSE=T SLTH=F; 4108 echo " RXLP_DFC_MSG_BIT_REMAP_PORT_1"; 4109 tr 50 M=RXLP_DFC_MSG_BIT_REMAP_PORT_1; 4110 tr 51 M=RXLP_DFC_MSG_BIT_REMAP_PORT_1; 4111 tr 52 M=RXLP_DFC_MSG_BIT_REMAP_PORT_1; 4112 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_1 TSE=F SLTH=T; 4113 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_1 TSE=T SLTH=T; 4114 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_1 TSE=T SLTH=F; 4115 echo " RXLP_DFC_MSG_BIT_REMAP_PORT_2"; 4116 tr 50 M=RXLP_DFC_MSG_BIT_REMAP_PORT_2; 4117 tr 51 M=RXLP_DFC_MSG_BIT_REMAP_PORT_2; 4118 tr 52 M=RXLP_DFC_MSG_BIT_REMAP_PORT_2; 4119 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_2 TSE=F SLTH=T; 4120 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_2 TSE=T SLTH=T; 4121 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_2 TSE=T SLTH=F; 4122 echo " RXLP_DFC_MSG_BIT_REMAP_PORT_3"; 4123 tr 50 M=RXLP_DFC_MSG_BIT_REMAP_PORT_3; 4124 tr 51 M=RXLP_DFC_MSG_BIT_REMAP_PORT_3; 4125 tr 52 M=RXLP_DFC_MSG_BIT_REMAP_PORT_3; 4126 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_3 TSE=F SLTH=T; 4127 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_3 TSE=T SLTH=T; 4128 tr 71 M=RXLP_DFC_MSG_BIT_REMAP_PORT_3 TSE=T SLTH=F; 4129 #echo " RXLP_ERROR_ACTION_MAP_DATA"; 4130 #tr 50 M=RXLP_ERROR_ACTION_MAP_DATA; 4131 #tr 51 M=RXLP_ERROR_ACTION_MAP_DATA; 4132 #tr 52 M=RXLP_ERROR_ACTION_MAP_DATA; 4133 #tr 71 M=RXLP_ERROR_ACTION_MAP_DATA TSE=F SLTH=T; 4134 #tr 71 M=RXLP_ERROR_ACTION_MAP_DATA TSE=T SLTH=T; 4135 #tr 71 M=RXLP_ERROR_ACTION_MAP_DATA TSE=T SLTH=F; 4136 #echo " RXLP_ERROR_ACTION_MAP_TCAM"; 4137 #tr 50 M=RXLP_ERROR_ACTION_MAP_TCAM; 4138 #tr 51 M=RXLP_ERROR_ACTION_MAP_TCAM; 4139 #tr 52 M=RXLP_ERROR_ACTION_MAP_TCAM; 4140 #tr 71 M=RXLP_ERROR_ACTION_MAP_TCAM TSE=F SLTH=T; 4141 #tr 71 M=RXLP_ERROR_ACTION_MAP_TCAM TSE=T SLTH=T; 4142 #tr 71 M=RXLP_ERROR_ACTION_MAP_TCAM TSE=T SLTH=F; 4143 echo " RXLP_INTERNAL_STREAM_MAP_PORT_0"; 4144 tr 50 M=RXLP_INTERNAL_STREAM_MAP_PORT_0; 4145 tr 51 M=RXLP_INTERNAL_STREAM_MAP_PORT_0; 4146 tr 52 M=RXLP_INTERNAL_STREAM_MAP_PORT_0; 4147 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_0 TSE=F SLTH=T; 4148 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_0 TSE=T SLTH=T; 4149 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_0 TSE=T SLTH=F; 4150 echo " RXLP_INTERNAL_STREAM_MAP_PORT_1"; 4151 tr 50 M=RXLP_INTERNAL_STREAM_MAP_PORT_1; 4152 tr 51 M=RXLP_INTERNAL_STREAM_MAP_PORT_1; 4153 tr 52 M=RXLP_INTERNAL_STREAM_MAP_PORT_1; 4154 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_1 TSE=F SLTH=T; 4155 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_1 TSE=T SLTH=T; 4156 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_1 TSE=T SLTH=F; 4157 echo " RXLP_INTERNAL_STREAM_MAP_PORT_2"; 4158 tr 50 M=RXLP_INTERNAL_STREAM_MAP_PORT_2; 4159 tr 51 M=RXLP_INTERNAL_STREAM_MAP_PORT_2; 4160 tr 52 M=RXLP_INTERNAL_STREAM_MAP_PORT_2; 4161 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_2 TSE=F SLTH=T; 4162 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_2 TSE=T SLTH=T; 4163 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_2 TSE=T SLTH=F; 4164 echo " RXLP_INTERNAL_STREAM_MAP_PORT_3"; 4165 tr 50 M=RXLP_INTERNAL_STREAM_MAP_PORT_3; 4166 tr 51 M=RXLP_INTERNAL_STREAM_MAP_PORT_3; 4167 tr 52 M=RXLP_INTERNAL_STREAM_MAP_PORT_3; 4168 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_3 TSE=F SLTH=T; 4169 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_3 TSE=T SLTH=T; 4170 tr 71 M=RXLP_INTERNAL_STREAM_MAP_PORT_3 TSE=T SLTH=F; 4171 #echo " RXLP_INTR_DATA_MEM"; 4172 #tr 50 M=RXLP_INTR_DATA_MEM; 4173 #tr 51 M=RXLP_INTR_DATA_MEM; 4174 #tr 52 M=RXLP_INTR_DATA_MEM; 4175 #tr 71 M=RXLP_INTR_DATA_MEM TSE=F SLTH=T; 4176 #tr 71 M=RXLP_INTR_DATA_MEM TSE=T SLTH=T; 4177 #tr 71 M=RXLP_INTR_DATA_MEM TSE=T SLTH=F; 4178 echo " RXLP_MAX_FRAME_SIZE"; 4179 tr 50 M=RXLP_MAX_FRAME_SIZE; 4180 tr 51 M=RXLP_MAX_FRAME_SIZE; 4181 tr 52 M=RXLP_MAX_FRAME_SIZE; 4182 tr 71 M=RXLP_MAX_FRAME_SIZE TSE=F SLTH=T; 4183 tr 71 M=RXLP_MAX_FRAME_SIZE TSE=T SLTH=T; 4184 tr 71 M=RXLP_MAX_FRAME_SIZE TSE=T SLTH=F; 4185 echo " RX_PROT_GROUP_TABLE"; 4186 tr 50 M=RX_PROT_GROUP_TABLE; 4187 tr 51 M=RX_PROT_GROUP_TABLE; 4188 tr 52 M=RX_PROT_GROUP_TABLE; 4189 tr 71 M=RX_PROT_GROUP_TABLE TSE=F SLTH=T; 4190 tr 71 M=RX_PROT_GROUP_TABLE TSE=T SLTH=T; 4191 tr 71 M=RX_PROT_GROUP_TABLE TSE=T SLTH=F; 4192 echo " RX_PROT_GROUP_TABLE_1"; 4193 tr 50 M=RX_PROT_GROUP_TABLE_1; 4194 tr 51 M=RX_PROT_GROUP_TABLE_1; 4195 tr 52 M=RX_PROT_GROUP_TABLE_1; 4196 tr 71 M=RX_PROT_GROUP_TABLE_1 TSE=F SLTH=T; 4197 tr 71 M=RX_PROT_GROUP_TABLE_1 TSE=T SLTH=T; 4198 tr 71 M=RX_PROT_GROUP_TABLE_1 TSE=T SLTH=F; 4199 echo " RX_PROT_GROUP_TABLE_1_DMA"; 4200 tr 50 M=RX_PROT_GROUP_TABLE_1_DMA; 4201 tr 51 M=RX_PROT_GROUP_TABLE_1_DMA; 4202 tr 52 M=RX_PROT_GROUP_TABLE_1_DMA; 4203 tr 71 M=RX_PROT_GROUP_TABLE_1_DMA TSE=F SLTH=T; 4204 tr 71 M=RX_PROT_GROUP_TABLE_1_DMA TSE=T SLTH=T; 4205 tr 71 M=RX_PROT_GROUP_TABLE_1_DMA TSE=T SLTH=F; 4206 echo " RX_PROT_GROUP_TABLE_DMA"; 4207 tr 50 M=RX_PROT_GROUP_TABLE_DMA; 4208 tr 51 M=RX_PROT_GROUP_TABLE_DMA; 4209 tr 52 M=RX_PROT_GROUP_TABLE_DMA; 4210 tr 71 M=RX_PROT_GROUP_TABLE_DMA TSE=F SLTH=T; 4211 tr 71 M=RX_PROT_GROUP_TABLE_DMA TSE=T SLTH=T; 4212 tr 71 M=RX_PROT_GROUP_TABLE_DMA TSE=T SLTH=F; 4213 echo " SERVICE_COS_MAP"; 4214 tr 50 M=SERVICE_COS_MAP; 4215 tr 51 M=SERVICE_COS_MAP; 4216 tr 52 M=SERVICE_COS_MAP; 4217 tr 71 M=SERVICE_COS_MAP TSE=F SLTH=T; 4218 tr 71 M=SERVICE_COS_MAP TSE=T SLTH=T; 4219 tr 71 M=SERVICE_COS_MAP TSE=T SLTH=F; 4220 echo " SER_MEMORY"; 4221 tr 50 M=SER_MEMORY; 4222 tr 51 M=SER_MEMORY; 4223 tr 52 M=SER_MEMORY; 4224 tr 71 M=SER_MEMORY TSE=F SLTH=T; 4225 tr 71 M=SER_MEMORY TSE=T SLTH=T; 4226 tr 71 M=SER_MEMORY TSE=T SLTH=F; 4227 echo " SER_RESULT_0"; 4228 tr 50 M=SER_RESULT_0; 4229 #tr 51 M=SER_RESULT_0; 4230 #tr 52 M=SER_RESULT_0; 4231 tr 71 M=SER_RESULT_0 TSE=F SLTH=T; 4232 tr 71 M=SER_RESULT_0 TSE=T SLTH=T; 4233 tr 71 M=SER_RESULT_0 TSE=T SLTH=F; 4234 echo " SER_RESULT_1"; 4235 tr 50 M=SER_RESULT_1; 4236 #tr 51 M=SER_RESULT_1; 4237 #tr 52 M=SER_RESULT_1; 4238 tr 71 M=SER_RESULT_1 TSE=F SLTH=T; 4239 tr 71 M=SER_RESULT_1 TSE=T SLTH=T; 4240 tr 71 M=SER_RESULT_1 TSE=T SLTH=F; 4241 echo " SER_RESULT_DATA_0"; 4242 tr 50 M=SER_RESULT_DATA_0; 4243 #tr 51 M=SER_RESULT_DATA_0; 4244 #tr 52 M=SER_RESULT_DATA_0; 4245 tr 71 M=SER_RESULT_DATA_0 TSE=F SLTH=T; 4246 tr 71 M=SER_RESULT_DATA_0 TSE=T SLTH=T; 4247 tr 71 M=SER_RESULT_DATA_0 TSE=T SLTH=F; 4248 echo " SER_RESULT_DATA_1"; 4249 tr 50 M=SER_RESULT_DATA_1; 4250 #tr 51 M=SER_RESULT_DATA_1; 4251 #tr 52 M=SER_RESULT_DATA_1; 4252 tr 71 M=SER_RESULT_DATA_1 TSE=F SLTH=T; 4253 tr 71 M=SER_RESULT_DATA_1 TSE=T SLTH=T; 4254 tr 71 M=SER_RESULT_DATA_1 TSE=T SLTH=F; 4255 echo " SER_RESULT_EXPECTED_0"; 4256 tr 50 M=SER_RESULT_EXPECTED_0; 4257 #tr 51 M=SER_RESULT_EXPECTED_0; 4258 #tr 52 M=SER_RESULT_EXPECTED_0; 4259 tr 71 M=SER_RESULT_EXPECTED_0 TSE=F SLTH=T; 4260 tr 71 M=SER_RESULT_EXPECTED_0 TSE=T SLTH=T; 4261 tr 71 M=SER_RESULT_EXPECTED_0 TSE=T SLTH=F; 4262 echo " SER_RESULT_EXPECTED_1"; 4263 tr 50 M=SER_RESULT_EXPECTED_1; 4264 #tr 51 M=SER_RESULT_EXPECTED_1; 4265 #tr 52 M=SER_RESULT_EXPECTED_1; 4266 tr 71 M=SER_RESULT_EXPECTED_1 TSE=F SLTH=T; 4267 tr 71 M=SER_RESULT_EXPECTED_1 TSE=T SLTH=T; 4268 tr 71 M=SER_RESULT_EXPECTED_1 TSE=T SLTH=F; 4269 echo " SOURCE_MOD_PROXY_TABLE"; 4270 tr 50 M=SOURCE_MOD_PROXY_TABLE; 4271 tr 51 M=SOURCE_MOD_PROXY_TABLE; 4272 tr 52 M=SOURCE_MOD_PROXY_TABLE; 4273 tr 71 M=SOURCE_MOD_PROXY_TABLE TSE=F SLTH=T; 4274 tr 71 M=SOURCE_MOD_PROXY_TABLE TSE=T SLTH=T; 4275 tr 71 M=SOURCE_MOD_PROXY_TABLE TSE=T SLTH=F; 4276 echo " SOURCE_TRUNK_MAP_MODBASE"; 4277 tr 50 M=SOURCE_TRUNK_MAP_MODBASE; 4278 tr 51 M=SOURCE_TRUNK_MAP_MODBASE; 4279 tr 52 M=SOURCE_TRUNK_MAP_MODBASE; 4280 tr 71 M=SOURCE_TRUNK_MAP_MODBASE TSE=F SLTH=T; 4281 tr 71 M=SOURCE_TRUNK_MAP_MODBASE TSE=T SLTH=T; 4282 tr 71 M=SOURCE_TRUNK_MAP_MODBASE TSE=T SLTH=F; 4283 echo " SOURCE_TRUNK_MAP_TABLE"; 4284 tr 50 M=SOURCE_TRUNK_MAP_TABLE; 4285 tr 51 M=SOURCE_TRUNK_MAP_TABLE; 4286 tr 52 M=SOURCE_TRUNK_MAP_TABLE; 4287 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=F SLTH=T; 4288 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=T SLTH=T; 4289 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=T SLTH=F; 4290 echo " SOURCE_VP"; 4291 tr 50 M=SOURCE_VP; 4292 tr 51 M=SOURCE_VP; 4293 tr 52 M=SOURCE_VP; 4294 tr 71 M=SOURCE_VP TSE=F SLTH=T; 4295 tr 71 M=SOURCE_VP TSE=T SLTH=T; 4296 tr 71 M=SOURCE_VP TSE=T SLTH=F; 4297 echo " SRC_MODID_EGRESS"; 4298 tr 50 M=SRC_MODID_EGRESS; 4299 tr 51 M=SRC_MODID_EGRESS; 4300 tr 52 M=SRC_MODID_EGRESS; 4301 tr 71 M=SRC_MODID_EGRESS TSE=F SLTH=T; 4302 tr 71 M=SRC_MODID_EGRESS TSE=T SLTH=T; 4303 tr 71 M=SRC_MODID_EGRESS TSE=T SLTH=F; 4304 echo " SRC_MODID_INGRESS_BLOCK"; 4305 tr 50 M=SRC_MODID_INGRESS_BLOCK; 4306 tr 51 M=SRC_MODID_INGRESS_BLOCK; 4307 tr 52 M=SRC_MODID_INGRESS_BLOCK; 4308 tr 71 M=SRC_MODID_INGRESS_BLOCK TSE=F SLTH=T; 4309 tr 71 M=SRC_MODID_INGRESS_BLOCK TSE=T SLTH=T; 4310 tr 71 M=SRC_MODID_INGRESS_BLOCK TSE=T SLTH=F; 4311 echo " STG_TAB"; 4312 tr 50 M=STG_TAB; 4313 tr 51 M=STG_TAB; 4314 tr 52 M=STG_TAB; 4315 tr 71 M=STG_TAB TSE=F SLTH=T; 4316 tr 71 M=STG_TAB TSE=T SLTH=T; 4317 tr 71 M=STG_TAB TSE=T SLTH=F; 4318 echo " SUBPORT_TAG_TO_PP_PORT_MAP"; 4319 tr 50 M=SUBPORT_TAG_TO_PP_PORT_MAP; 4320 tr 51 M=SUBPORT_TAG_TO_PP_PORT_MAP; 4321 tr 52 M=SUBPORT_TAG_TO_PP_PORT_MAP; 4322 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP TSE=F SLTH=T; 4323 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP TSE=T SLTH=T; 4324 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP TSE=T SLTH=F; 4325 echo " SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY"; 4326 tr 50 M=SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY; 4327 tr 51 M=SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY; 4328 tr 52 M=SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY; 4329 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY TSE=F SLTH=T; 4330 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY TSE=T SLTH=T; 4331 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY TSE=T SLTH=F; 4332 echo " SUBPORT_TAG_TO_PP_PORT_MAP_ONLY"; 4333 tr 50 M=SUBPORT_TAG_TO_PP_PORT_MAP_ONLY; 4334 tr 51 M=SUBPORT_TAG_TO_PP_PORT_MAP_ONLY; 4335 tr 52 M=SUBPORT_TAG_TO_PP_PORT_MAP_ONLY; 4336 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP_ONLY TSE=F SLTH=T; 4337 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP_ONLY TSE=T SLTH=T; 4338 tr 71 M=SUBPORT_TAG_TO_PP_PORT_MAP_ONLY TSE=T SLTH=F; 4339 echo " SVM_MACROFLOW_INDEX_TABLE"; 4340 tr 50 M=SVM_MACROFLOW_INDEX_TABLE; 4341 tr 51 M=SVM_MACROFLOW_INDEX_TABLE; 4342 tr 52 M=SVM_MACROFLOW_INDEX_TABLE; 4343 tr 71 M=SVM_MACROFLOW_INDEX_TABLE TSE=F SLTH=T; 4344 tr 71 M=SVM_MACROFLOW_INDEX_TABLE TSE=T SLTH=T; 4345 tr 71 M=SVM_MACROFLOW_INDEX_TABLE TSE=T SLTH=F; 4346 echo " SVM_METER_TABLE"; 4347 tr 50 M=SVM_METER_TABLE; 4348 tr 51 M=SVM_METER_TABLE; 4349 tr 52 M=SVM_METER_TABLE; 4350 tr 71 M=SVM_METER_TABLE TSE=F SLTH=T; 4351 tr 71 M=SVM_METER_TABLE TSE=T SLTH=T; 4352 tr 71 M=SVM_METER_TABLE TSE=T SLTH=F; 4353 echo " SVM_OFFSET_TABLE"; 4354 tr 50 M=SVM_OFFSET_TABLE; 4355 tr 51 M=SVM_OFFSET_TABLE; 4356 tr 52 M=SVM_OFFSET_TABLE; 4357 tr 71 M=SVM_OFFSET_TABLE TSE=F SLTH=T; 4358 tr 71 M=SVM_OFFSET_TABLE TSE=T SLTH=T; 4359 tr 71 M=SVM_OFFSET_TABLE TSE=T SLTH=F; 4360 echo " SVM_POLICY_TABLE"; 4361 tr 50 M=SVM_POLICY_TABLE; 4362 tr 51 M=SVM_POLICY_TABLE; 4363 tr 52 M=SVM_POLICY_TABLE; 4364 tr 71 M=SVM_POLICY_TABLE TSE=F SLTH=T; 4365 tr 71 M=SVM_POLICY_TABLE TSE=T SLTH=T; 4366 tr 71 M=SVM_POLICY_TABLE TSE=T SLTH=F; 4367 echo " SYSTEM_CONFIG_TABLE"; 4368 tr 50 M=SYSTEM_CONFIG_TABLE; 4369 tr 51 M=SYSTEM_CONFIG_TABLE; 4370 tr 52 M=SYSTEM_CONFIG_TABLE; 4371 tr 71 M=SYSTEM_CONFIG_TABLE TSE=F SLTH=T; 4372 tr 71 M=SYSTEM_CONFIG_TABLE TSE=T SLTH=T; 4373 tr 71 M=SYSTEM_CONFIG_TABLE TSE=T SLTH=F; 4374 echo " SYSTEM_CONFIG_TABLE_MODBASE"; 4375 tr 50 M=SYSTEM_CONFIG_TABLE_MODBASE; 4376 tr 51 M=SYSTEM_CONFIG_TABLE_MODBASE; 4377 tr 52 M=SYSTEM_CONFIG_TABLE_MODBASE; 4378 tr 71 M=SYSTEM_CONFIG_TABLE_MODBASE TSE=F SLTH=T; 4379 tr 71 M=SYSTEM_CONFIG_TABLE_MODBASE TSE=T SLTH=T; 4380 tr 71 M=SYSTEM_CONFIG_TABLE_MODBASE TSE=T SLTH=F; 4381 echo " TCP_FN"; 4382 tr 50 M=TCP_FN; 4383 tr 51 M=TCP_FN; 4384 tr 52 M=TCP_FN; 4385 tr 71 M=TCP_FN TSE=F SLTH=T; 4386 tr 71 M=TCP_FN TSE=T SLTH=T; 4387 tr 71 M=TCP_FN TSE=T SLTH=F; 4388 #echo " THDIEMA_THDI_PORT_PG_CNTRS"; 4389 #tr 50 M=THDIEMA_THDI_PORT_PG_CNTRS; 4390 #tr 51 M=THDIEMA_THDI_PORT_PG_CNTRS; 4391 #tr 52 M=THDIEMA_THDI_PORT_PG_CNTRS; 4392 #tr 71 M=THDIEMA_THDI_PORT_PG_CNTRS TSE=F SLTH=T; 4393 #tr 71 M=THDIEMA_THDI_PORT_PG_CNTRS TSE=T SLTH=T; 4394 #tr 71 M=THDIEMA_THDI_PORT_PG_CNTRS TSE=T SLTH=F; 4395 #echo " THDIEMA_THDI_PORT_PG_CONFIG"; 4396 #tr 50 M=THDIEMA_THDI_PORT_PG_CONFIG; 4397 #tr 51 M=THDIEMA_THDI_PORT_PG_CONFIG; 4398 #tr 52 M=THDIEMA_THDI_PORT_PG_CONFIG; 4399 #tr 71 M=THDIEMA_THDI_PORT_PG_CONFIG TSE=F SLTH=T; 4400 #tr 71 M=THDIEMA_THDI_PORT_PG_CONFIG TSE=T SLTH=T; 4401 #tr 71 M=THDIEMA_THDI_PORT_PG_CONFIG TSE=T SLTH=F; 4402 #echo " THDIEMA_THDI_PORT_SP_CNTRS"; 4403 #tr 50 M=THDIEMA_THDI_PORT_SP_CNTRS; 4404 #tr 51 M=THDIEMA_THDI_PORT_SP_CNTRS; 4405 #tr 52 M=THDIEMA_THDI_PORT_SP_CNTRS; 4406 #tr 71 M=THDIEMA_THDI_PORT_SP_CNTRS TSE=F SLTH=T; 4407 #tr 71 M=THDIEMA_THDI_PORT_SP_CNTRS TSE=T SLTH=T; 4408 #tr 71 M=THDIEMA_THDI_PORT_SP_CNTRS TSE=T SLTH=F; 4409 #echo " THDIEMA_THDI_PORT_SP_CONFIG"; 4410 #tr 50 M=THDIEMA_THDI_PORT_SP_CONFIG; 4411 #tr 51 M=THDIEMA_THDI_PORT_SP_CONFIG; 4412 #tr 52 M=THDIEMA_THDI_PORT_SP_CONFIG; 4413 #tr 71 M=THDIEMA_THDI_PORT_SP_CONFIG TSE=F SLTH=T; 4414 #tr 71 M=THDIEMA_THDI_PORT_SP_CONFIG TSE=T SLTH=T; 4415 #tr 71 M=THDIEMA_THDI_PORT_SP_CONFIG TSE=T SLTH=F; 4416 #echo " THDIEXT_THDI_PORT_PG_CNTRS"; 4417 #tr 50 M=THDIEXT_THDI_PORT_PG_CNTRS; 4418 #tr 51 M=THDIEXT_THDI_PORT_PG_CNTRS; 4419 #tr 52 M=THDIEXT_THDI_PORT_PG_CNTRS; 4420 #tr 71 M=THDIEXT_THDI_PORT_PG_CNTRS TSE=F SLTH=T; 4421 #tr 71 M=THDIEXT_THDI_PORT_PG_CNTRS TSE=T SLTH=T; 4422 #tr 71 M=THDIEXT_THDI_PORT_PG_CNTRS TSE=T SLTH=F; 4423 #echo " THDIEXT_THDI_PORT_PG_CONFIG"; 4424 #tr 50 M=THDIEXT_THDI_PORT_PG_CONFIG; 4425 #tr 51 M=THDIEXT_THDI_PORT_PG_CONFIG; 4426 #tr 52 M=THDIEXT_THDI_PORT_PG_CONFIG; 4427 #tr 71 M=THDIEXT_THDI_PORT_PG_CONFIG TSE=F SLTH=T; 4428 #tr 71 M=THDIEXT_THDI_PORT_PG_CONFIG TSE=T SLTH=T; 4429 #tr 71 M=THDIEXT_THDI_PORT_PG_CONFIG TSE=T SLTH=F; 4430 #echo " THDIEXT_THDI_PORT_SP_CNTRS"; 4431 #tr 50 M=THDIEXT_THDI_PORT_SP_CNTRS; 4432 #tr 51 M=THDIEXT_THDI_PORT_SP_CNTRS; 4433 #tr 52 M=THDIEXT_THDI_PORT_SP_CNTRS; 4434 #tr 71 M=THDIEXT_THDI_PORT_SP_CNTRS TSE=F SLTH=T; 4435 #tr 71 M=THDIEXT_THDI_PORT_SP_CNTRS TSE=T SLTH=T; 4436 #tr 71 M=THDIEXT_THDI_PORT_SP_CNTRS TSE=T SLTH=F; 4437 #echo " THDIEXT_THDI_PORT_SP_CONFIG"; 4438 #tr 50 M=THDIEXT_THDI_PORT_SP_CONFIG; 4439 #tr 51 M=THDIEXT_THDI_PORT_SP_CONFIG; 4440 #tr 52 M=THDIEXT_THDI_PORT_SP_CONFIG; 4441 #tr 71 M=THDIEXT_THDI_PORT_SP_CONFIG TSE=F SLTH=T; 4442 #tr 71 M=THDIEXT_THDI_PORT_SP_CONFIG TSE=T SLTH=T; 4443 #tr 71 M=THDIEXT_THDI_PORT_SP_CONFIG TSE=T SLTH=F; 4444 #echo " THDIQEN_THDI_PORT_PG_CNTRS"; 4445 #tr 50 M=THDIQEN_THDI_PORT_PG_CNTRS; 4446 #tr 51 M=THDIQEN_THDI_PORT_PG_CNTRS; 4447 #tr 52 M=THDIQEN_THDI_PORT_PG_CNTRS; 4448 #tr 71 M=THDIQEN_THDI_PORT_PG_CNTRS TSE=F SLTH=T; 4449 #tr 71 M=THDIQEN_THDI_PORT_PG_CNTRS TSE=T SLTH=T; 4450 #tr 71 M=THDIQEN_THDI_PORT_PG_CNTRS TSE=T SLTH=F; 4451 #echo " THDIQEN_THDI_PORT_PG_CONFIG"; 4452 #tr 50 M=THDIQEN_THDI_PORT_PG_CONFIG; 4453 #tr 51 M=THDIQEN_THDI_PORT_PG_CONFIG; 4454 #tr 52 M=THDIQEN_THDI_PORT_PG_CONFIG; 4455 #tr 71 M=THDIQEN_THDI_PORT_PG_CONFIG TSE=F SLTH=T; 4456 #tr 71 M=THDIQEN_THDI_PORT_PG_CONFIG TSE=T SLTH=T; 4457 #tr 71 M=THDIQEN_THDI_PORT_PG_CONFIG TSE=T SLTH=F; 4458 #echo " THDIQEN_THDI_PORT_SP_CNTRS"; 4459 #tr 50 M=THDIQEN_THDI_PORT_SP_CNTRS; 4460 #tr 51 M=THDIQEN_THDI_PORT_SP_CNTRS; 4461 #tr 52 M=THDIQEN_THDI_PORT_SP_CNTRS; 4462 #tr 71 M=THDIQEN_THDI_PORT_SP_CNTRS TSE=F SLTH=T; 4463 #tr 71 M=THDIQEN_THDI_PORT_SP_CNTRS TSE=T SLTH=T; 4464 #tr 71 M=THDIQEN_THDI_PORT_SP_CNTRS TSE=T SLTH=F; 4465 #echo " THDIQEN_THDI_PORT_SP_CONFIG"; 4466 #tr 50 M=THDIQEN_THDI_PORT_SP_CONFIG; 4467 #tr 51 M=THDIQEN_THDI_PORT_SP_CONFIG; 4468 #tr 52 M=THDIQEN_THDI_PORT_SP_CONFIG; 4469 #tr 71 M=THDIQEN_THDI_PORT_SP_CONFIG TSE=F SLTH=T; 4470 #tr 71 M=THDIQEN_THDI_PORT_SP_CONFIG TSE=T SLTH=T; 4471 #tr 71 M=THDIQEN_THDI_PORT_SP_CONFIG TSE=T SLTH=F; 4472 #echo " THDIRQE_THDI_PORT_PG_CNTRS"; 4473 #tr 50 M=THDIRQE_THDI_PORT_PG_CNTRS; 4474 #tr 51 M=THDIRQE_THDI_PORT_PG_CNTRS; 4475 #tr 52 M=THDIRQE_THDI_PORT_PG_CNTRS; 4476 #tr 71 M=THDIRQE_THDI_PORT_PG_CNTRS TSE=F SLTH=T; 4477 #tr 71 M=THDIRQE_THDI_PORT_PG_CNTRS TSE=T SLTH=T; 4478 #tr 71 M=THDIRQE_THDI_PORT_PG_CNTRS TSE=T SLTH=F; 4479 #echo " THDIRQE_THDI_PORT_PG_CONFIG"; 4480 #tr 50 M=THDIRQE_THDI_PORT_PG_CONFIG; 4481 #tr 51 M=THDIRQE_THDI_PORT_PG_CONFIG; 4482 #tr 52 M=THDIRQE_THDI_PORT_PG_CONFIG; 4483 #tr 71 M=THDIRQE_THDI_PORT_PG_CONFIG TSE=F SLTH=T; 4484 #tr 71 M=THDIRQE_THDI_PORT_PG_CONFIG TSE=T SLTH=T; 4485 #tr 71 M=THDIRQE_THDI_PORT_PG_CONFIG TSE=T SLTH=F; 4486 #echo " THDIRQE_THDI_PORT_SP_CNTRS"; 4487 #tr 50 M=THDIRQE_THDI_PORT_SP_CNTRS; 4488 #tr 51 M=THDIRQE_THDI_PORT_SP_CNTRS; 4489 #tr 52 M=THDIRQE_THDI_PORT_SP_CNTRS; 4490 #tr 71 M=THDIRQE_THDI_PORT_SP_CNTRS TSE=F SLTH=T; 4491 #tr 71 M=THDIRQE_THDI_PORT_SP_CNTRS TSE=T SLTH=T; 4492 #tr 71 M=THDIRQE_THDI_PORT_SP_CNTRS TSE=T SLTH=F; 4493 #echo " THDIRQE_THDI_PORT_SP_CONFIG"; 4494 #tr 50 M=THDIRQE_THDI_PORT_SP_CONFIG; 4495 #tr 51 M=THDIRQE_THDI_PORT_SP_CONFIG; 4496 #tr 52 M=THDIRQE_THDI_PORT_SP_CONFIG; 4497 #tr 71 M=THDIRQE_THDI_PORT_SP_CONFIG TSE=F SLTH=T; 4498 #tr 71 M=THDIRQE_THDI_PORT_SP_CONFIG TSE=T SLTH=T; 4499 #tr 71 M=THDIRQE_THDI_PORT_SP_CONFIG TSE=T SLTH=F; 4500 #echo " THDI_PORT_PG_CNTRS"; 4501 #tr 50 M=THDI_PORT_PG_CNTRS; 4502 #tr 51 M=THDI_PORT_PG_CNTRS; 4503 #tr 52 M=THDI_PORT_PG_CNTRS; 4504 #tr 71 M=THDI_PORT_PG_CNTRS TSE=F SLTH=T; 4505 #tr 71 M=THDI_PORT_PG_CNTRS TSE=T SLTH=T; 4506 #tr 71 M=THDI_PORT_PG_CNTRS TSE=T SLTH=F; 4507 #echo " THDI_PORT_PG_CONFIG"; 4508 #tr 50 M=THDI_PORT_PG_CONFIG; 4509 #tr 51 M=THDI_PORT_PG_CONFIG; 4510 #tr 52 M=THDI_PORT_PG_CONFIG; 4511 #tr 71 M=THDI_PORT_PG_CONFIG TSE=F SLTH=T; 4512 #tr 71 M=THDI_PORT_PG_CONFIG TSE=T SLTH=T; 4513 #tr 71 M=THDI_PORT_PG_CONFIG TSE=T SLTH=F; 4514 #echo " THDI_PORT_SP_CNTRS"; 4515 #tr 50 M=THDI_PORT_SP_CNTRS; 4516 #tr 51 M=THDI_PORT_SP_CNTRS; 4517 #tr 52 M=THDI_PORT_SP_CNTRS; 4518 #tr 71 M=THDI_PORT_SP_CNTRS TSE=F SLTH=T; 4519 #tr 71 M=THDI_PORT_SP_CNTRS TSE=T SLTH=T; 4520 #tr 71 M=THDI_PORT_SP_CNTRS TSE=T SLTH=F; 4521 #echo " THDI_PORT_SP_CONFIG"; 4522 #tr 50 M=THDI_PORT_SP_CONFIG; 4523 #tr 51 M=THDI_PORT_SP_CONFIG; 4524 #tr 52 M=THDI_PORT_SP_CONFIG; 4525 #tr 71 M=THDI_PORT_SP_CONFIG TSE=F SLTH=T; 4526 #tr 71 M=THDI_PORT_SP_CONFIG TSE=T SLTH=T; 4527 #tr 71 M=THDI_PORT_SP_CONFIG TSE=T SLTH=F; 4528 echo " THDO_OPNCOUNT_QENTRY"; 4529 tr 50 M=THDO_OPNCOUNT_QENTRY; 4530 tr 51 M=THDO_OPNCOUNT_QENTRY; 4531 tr 52 M=THDO_OPNCOUNT_QENTRY; 4532 tr 71 M=THDO_OPNCOUNT_QENTRY TSE=F SLTH=T; 4533 tr 71 M=THDO_OPNCOUNT_QENTRY TSE=T SLTH=T; 4534 tr 71 M=THDO_OPNCOUNT_QENTRY TSE=T SLTH=F; 4535 if !$?LIKE_BCM56456 \ 4536 'echo " THDO_QCOUNT_CELL_1"; \ 4537 tr 50 M=THDO_QCOUNT_CELL_1; \ 4538 tr 51 M=THDO_QCOUNT_CELL_1; \ 4539 tr 52 M=THDO_QCOUNT_CELL_1; \ 4540 tr 71 M=THDO_QCOUNT_CELL_1 TSE=F SLTH=T; \ 4541 tr 71 M=THDO_QCOUNT_CELL_1 TSE=T SLTH=T; \ 4542 tr 71 M=THDO_QCOUNT_CELL_1 TSE=T SLTH=F; \ 4543 $done;' 4544 echo " THDO_QCOUNT_QENTRY_0"; 4545 tr 50 M=THDO_QCOUNT_QENTRY_0; 4546 tr 51 M=THDO_QCOUNT_QENTRY_0; 4547 tr 52 M=THDO_QCOUNT_QENTRY_0; 4548 tr 71 M=THDO_QCOUNT_QENTRY_0 TSE=F SLTH=T; 4549 tr 71 M=THDO_QCOUNT_QENTRY_0 TSE=T SLTH=T; 4550 tr 71 M=THDO_QCOUNT_QENTRY_0 TSE=T SLTH=F; 4551 if !$?LIKE_BCM56456 \ 4552 'echo " THDO_QCOUNT_QENTRY_1"; \ 4553 tr 50 M=THDO_QCOUNT_QENTRY_1; \ 4554 tr 51 M=THDO_QCOUNT_QENTRY_1; \ 4555 tr 52 M=THDO_QCOUNT_QENTRY_1; \ 4556 tr 71 M=THDO_QCOUNT_QENTRY_1 TSE=F SLTH=T; \ 4557 tr 71 M=THDO_QCOUNT_QENTRY_1 TSE=T SLTH=T; \ 4558 tr 71 M=THDO_QCOUNT_QENTRY_1 TSE=T SLTH=F; \ 4559 echo " THDO_QRESET_VALUE_CELL_1"; \ 4560 tr 50 M=THDO_QRESET_VALUE_CELL_1; \ 4561 tr 51 M=THDO_QRESET_VALUE_CELL_1; \ 4562 tr 52 M=THDO_QRESET_VALUE_CELL_1; \ 4563 tr 71 M=THDO_QRESET_VALUE_CELL_1 TSE=F SLTH=T; \ 4564 tr 71 M=THDO_QRESET_VALUE_CELL_1 TSE=T SLTH=T; \ 4565 tr 71 M=THDO_QRESET_VALUE_CELL_1 TSE=T SLTH=F; \ 4566 echo " THDO_QRESET_VALUE_QENTRY_1"; \ 4567 tr 50 M=THDO_QRESET_VALUE_QENTRY_1; \ 4568 tr 51 M=THDO_QRESET_VALUE_QENTRY_1; \ 4569 tr 52 M=THDO_QRESET_VALUE_QENTRY_1; \ 4570 tr 71 M=THDO_QRESET_VALUE_QENTRY_1 TSE=F SLTH=T; \ 4571 tr 71 M=THDO_QRESET_VALUE_QENTRY_1 TSE=T SLTH=T; \ 4572 tr 71 M=THDO_QRESET_VALUE_QENTRY_1 TSE=T SLTH=F; \ 4573 echo " THDO_QSTATUS_CELL_1"; \ 4574 tr 50 M=THDO_QSTATUS_CELL_1; \ 4575 tr 51 M=THDO_QSTATUS_CELL_1; \ 4576 tr 52 M=THDO_QSTATUS_CELL_1; \ 4577 tr 71 M=THDO_QSTATUS_CELL_1 TSE=F SLTH=T; \ 4578 tr 71 M=THDO_QSTATUS_CELL_1 TSE=T SLTH=T; \ 4579 tr 71 M=THDO_QSTATUS_CELL_1 TSE=T SLTH=F; \ 4580 echo " THDO_QSTATUS_QENTRY_1"; \ 4581 tr 50 M=THDO_QSTATUS_QENTRY_1; \ 4582 tr 51 M=THDO_QSTATUS_QENTRY_1; \ 4583 tr 52 M=THDO_QSTATUS_QENTRY_1; \ 4584 tr 71 M=THDO_QSTATUS_QENTRY_1 TSE=F SLTH=T; \ 4585 tr 71 M=THDO_QSTATUS_QENTRY_1 TSE=T SLTH=T; \ 4586 tr 71 M=THDO_QSTATUS_QENTRY_1 TSE=T SLTH=F; \ 4587 done;' 4588 echo " TOS_FN"; 4589 tr 50 M=TOS_FN; 4590 tr 51 M=TOS_FN; 4591 tr 52 M=TOS_FN; 4592 tr 71 M=TOS_FN TSE=F SLTH=T; 4593 tr 71 M=TOS_FN TSE=T SLTH=T; 4594 tr 71 M=TOS_FN TSE=T SLTH=F; 4595 echo " TRUNK_BITMAP"; 4596 tr 50 M=TRUNK_BITMAP; 4597 tr 51 M=TRUNK_BITMAP; 4598 tr 52 M=TRUNK_BITMAP; 4599 tr 71 M=TRUNK_BITMAP TSE=F SLTH=T; 4600 tr 71 M=TRUNK_BITMAP TSE=T SLTH=T; 4601 tr 71 M=TRUNK_BITMAP TSE=T SLTH=F; 4602 echo " TRUNK_CBL_TABLE"; 4603 tr 50 M=TRUNK_CBL_TABLE; 4604 tr 51 M=TRUNK_CBL_TABLE; 4605 tr 52 M=TRUNK_CBL_TABLE; 4606 tr 71 M=TRUNK_CBL_TABLE TSE=F SLTH=T; 4607 tr 71 M=TRUNK_CBL_TABLE TSE=T SLTH=T; 4608 tr 71 M=TRUNK_CBL_TABLE TSE=T SLTH=F; 4609 echo " TRUNK_GROUP"; 4610 tr 50 M=TRUNK_GROUP; 4611 tr 51 M=TRUNK_GROUP; 4612 tr 52 M=TRUNK_GROUP; 4613 tr 71 M=TRUNK_GROUP TSE=F SLTH=T; 4614 tr 71 M=TRUNK_GROUP TSE=T SLTH=T; 4615 tr 71 M=TRUNK_GROUP TSE=T SLTH=F; 4616 echo " TRUNK_MEMBER"; 4617 tr 50 M=TRUNK_MEMBER; 4618 tr 51 M=TRUNK_MEMBER; 4619 tr 52 M=TRUNK_MEMBER; 4620 tr 71 M=TRUNK_MEMBER TSE=F SLTH=T; 4621 tr 71 M=TRUNK_MEMBER TSE=T SLTH=T; 4622 tr 71 M=TRUNK_MEMBER TSE=T SLTH=F; 4623 echo " TTL_FN"; 4624 tr 50 M=TTL_FN; 4625 tr 51 M=TTL_FN; 4626 tr 52 M=TTL_FN; 4627 tr 71 M=TTL_FN TSE=F SLTH=T; 4628 tr 71 M=TTL_FN TSE=T SLTH=T; 4629 tr 71 M=TTL_FN TSE=T SLTH=F; 4630 echo " TXLP_DEBUG_COUNTER0"; 4631 tr 50 M=TXLP_DEBUG_COUNTER0; 4632 tr 51 M=TXLP_DEBUG_COUNTER0; 4633 tr 52 M=TXLP_DEBUG_COUNTER0; 4634 tr 71 M=TXLP_DEBUG_COUNTER0 TSE=F SLTH=T; 4635 tr 71 M=TXLP_DEBUG_COUNTER0 TSE=T SLTH=T; 4636 tr 71 M=TXLP_DEBUG_COUNTER0 TSE=T SLTH=F; 4637 echo " TXLP_DEBUG_COUNTER1"; 4638 tr 50 M=TXLP_DEBUG_COUNTER1; 4639 tr 51 M=TXLP_DEBUG_COUNTER1; 4640 tr 52 M=TXLP_DEBUG_COUNTER1; 4641 tr 71 M=TXLP_DEBUG_COUNTER1 TSE=F SLTH=T; 4642 tr 71 M=TXLP_DEBUG_COUNTER1 TSE=T SLTH=T; 4643 tr 71 M=TXLP_DEBUG_COUNTER1 TSE=T SLTH=F; 4644 echo " TXLP_DEBUG_COUNTER10"; 4645 tr 50 M=TXLP_DEBUG_COUNTER10; 4646 tr 51 M=TXLP_DEBUG_COUNTER10; 4647 tr 52 M=TXLP_DEBUG_COUNTER10; 4648 tr 71 M=TXLP_DEBUG_COUNTER10 TSE=F SLTH=T; 4649 tr 71 M=TXLP_DEBUG_COUNTER10 TSE=T SLTH=T; 4650 tr 71 M=TXLP_DEBUG_COUNTER10 TSE=T SLTH=F; 4651 echo " TXLP_DEBUG_COUNTER11"; 4652 tr 50 M=TXLP_DEBUG_COUNTER11; 4653 tr 51 M=TXLP_DEBUG_COUNTER11; 4654 tr 52 M=TXLP_DEBUG_COUNTER11; 4655 tr 71 M=TXLP_DEBUG_COUNTER11 TSE=F SLTH=T; 4656 tr 71 M=TXLP_DEBUG_COUNTER11 TSE=T SLTH=T; 4657 tr 71 M=TXLP_DEBUG_COUNTER11 TSE=T SLTH=F; 4658 echo " TXLP_DEBUG_COUNTER2"; 4659 tr 50 M=TXLP_DEBUG_COUNTER2; 4660 tr 51 M=TXLP_DEBUG_COUNTER2; 4661 tr 52 M=TXLP_DEBUG_COUNTER2; 4662 tr 71 M=TXLP_DEBUG_COUNTER2 TSE=F SLTH=T; 4663 tr 71 M=TXLP_DEBUG_COUNTER2 TSE=T SLTH=T; 4664 tr 71 M=TXLP_DEBUG_COUNTER2 TSE=T SLTH=F; 4665 echo " TXLP_DEBUG_COUNTER3"; 4666 tr 50 M=TXLP_DEBUG_COUNTER3; 4667 tr 51 M=TXLP_DEBUG_COUNTER3; 4668 tr 52 M=TXLP_DEBUG_COUNTER3; 4669 tr 71 M=TXLP_DEBUG_COUNTER3 TSE=F SLTH=T; 4670 tr 71 M=TXLP_DEBUG_COUNTER3 TSE=T SLTH=T; 4671 tr 71 M=TXLP_DEBUG_COUNTER3 TSE=T SLTH=F; 4672 echo " TXLP_DEBUG_COUNTER4"; 4673 tr 50 M=TXLP_DEBUG_COUNTER4; 4674 tr 51 M=TXLP_DEBUG_COUNTER4; 4675 tr 52 M=TXLP_DEBUG_COUNTER4; 4676 tr 71 M=TXLP_DEBUG_COUNTER4 TSE=F SLTH=T; 4677 tr 71 M=TXLP_DEBUG_COUNTER4 TSE=T SLTH=T; 4678 tr 71 M=TXLP_DEBUG_COUNTER4 TSE=T SLTH=F; 4679 echo " TXLP_DEBUG_COUNTER5"; 4680 tr 50 M=TXLP_DEBUG_COUNTER5; 4681 tr 51 M=TXLP_DEBUG_COUNTER5; 4682 tr 52 M=TXLP_DEBUG_COUNTER5; 4683 tr 71 M=TXLP_DEBUG_COUNTER5 TSE=F SLTH=T; 4684 tr 71 M=TXLP_DEBUG_COUNTER5 TSE=T SLTH=T; 4685 tr 71 M=TXLP_DEBUG_COUNTER5 TSE=T SLTH=F; 4686 echo " TXLP_DEBUG_COUNTER6"; 4687 tr 50 M=TXLP_DEBUG_COUNTER6; 4688 tr 51 M=TXLP_DEBUG_COUNTER6; 4689 tr 52 M=TXLP_DEBUG_COUNTER6; 4690 tr 71 M=TXLP_DEBUG_COUNTER6 TSE=F SLTH=T; 4691 tr 71 M=TXLP_DEBUG_COUNTER6 TSE=T SLTH=T; 4692 tr 71 M=TXLP_DEBUG_COUNTER6 TSE=T SLTH=F; 4693 echo " TXLP_DEBUG_COUNTER7"; 4694 tr 50 M=TXLP_DEBUG_COUNTER7; 4695 tr 51 M=TXLP_DEBUG_COUNTER7; 4696 tr 52 M=TXLP_DEBUG_COUNTER7; 4697 tr 71 M=TXLP_DEBUG_COUNTER7 TSE=F SLTH=T; 4698 tr 71 M=TXLP_DEBUG_COUNTER7 TSE=T SLTH=T; 4699 tr 71 M=TXLP_DEBUG_COUNTER7 TSE=T SLTH=F; 4700 echo " TXLP_DEBUG_COUNTER8"; 4701 tr 50 M=TXLP_DEBUG_COUNTER8; 4702 tr 51 M=TXLP_DEBUG_COUNTER8; 4703 tr 52 M=TXLP_DEBUG_COUNTER8; 4704 tr 71 M=TXLP_DEBUG_COUNTER8 TSE=F SLTH=T; 4705 tr 71 M=TXLP_DEBUG_COUNTER8 TSE=T SLTH=T; 4706 tr 71 M=TXLP_DEBUG_COUNTER8 TSE=T SLTH=F; 4707 echo " TXLP_DEBUG_COUNTER9"; 4708 tr 50 M=TXLP_DEBUG_COUNTER9; 4709 tr 51 M=TXLP_DEBUG_COUNTER9; 4710 tr 52 M=TXLP_DEBUG_COUNTER9; 4711 tr 71 M=TXLP_DEBUG_COUNTER9 TSE=F SLTH=T; 4712 tr 71 M=TXLP_DEBUG_COUNTER9 TSE=T SLTH=T; 4713 tr 71 M=TXLP_DEBUG_COUNTER9 TSE=T SLTH=F; 4714 echo " TXLP_INT2EXT_STREAM_MAP_TABLE"; 4715 tr 50 M=TXLP_INT2EXT_STREAM_MAP_TABLE; 4716 tr 51 M=TXLP_INT2EXT_STREAM_MAP_TABLE; 4717 tr 52 M=TXLP_INT2EXT_STREAM_MAP_TABLE; 4718 tr 71 M=TXLP_INT2EXT_STREAM_MAP_TABLE TSE=F SLTH=T; 4719 tr 71 M=TXLP_INT2EXT_STREAM_MAP_TABLE TSE=T SLTH=T; 4720 tr 71 M=TXLP_INT2EXT_STREAM_MAP_TABLE TSE=T SLTH=F; 4721 echo " TXLP_PORT_ADDR_MAP_TABLE"; 4722 tr 50 M=TXLP_PORT_ADDR_MAP_TABLE; 4723 tr 51 M=TXLP_PORT_ADDR_MAP_TABLE; 4724 tr 52 M=TXLP_PORT_ADDR_MAP_TABLE; 4725 tr 71 M=TXLP_PORT_ADDR_MAP_TABLE TSE=F SLTH=T; 4726 tr 71 M=TXLP_PORT_ADDR_MAP_TABLE TSE=T SLTH=T; 4727 tr 71 M=TXLP_PORT_ADDR_MAP_TABLE TSE=T SLTH=F; 4728 #echo " TXLP_PORT_MMU_REQUESTS"; 4729 #tr 50 M=TXLP_PORT_MMU_REQUESTS; 4730 #tr 51 M=TXLP_PORT_MMU_REQUESTS; 4731 #tr 52 M=TXLP_PORT_MMU_REQUESTS; 4732 #tr 71 M=TXLP_PORT_MMU_REQUESTS TSE=F SLTH=T; 4733 #tr 71 M=TXLP_PORT_MMU_REQUESTS TSE=T SLTH=T; 4734 #tr 71 M=TXLP_PORT_MMU_REQUESTS TSE=T SLTH=F; 4735 #echo " TXLP_PORT_REQUESTS"; 4736 #tr 50 M=TXLP_PORT_REQUESTS; 4737 #tr 51 M=TXLP_PORT_REQUESTS; 4738 #tr 52 M=TXLP_PORT_REQUESTS; 4739 #tr 71 M=TXLP_PORT_REQUESTS TSE=F SLTH=T; 4740 #tr 71 M=TXLP_PORT_REQUESTS TSE=T SLTH=T; 4741 #tr 71 M=TXLP_PORT_REQUESTS TSE=T SLTH=F; 4742 echo " TXLP_PORT_STREAM_BITMAP_TABLE"; 4743 tr 50 M=TXLP_PORT_STREAM_BITMAP_TABLE; 4744 tr 51 M=TXLP_PORT_STREAM_BITMAP_TABLE; 4745 tr 52 M=TXLP_PORT_STREAM_BITMAP_TABLE; 4746 tr 71 M=TXLP_PORT_STREAM_BITMAP_TABLE TSE=F SLTH=T; 4747 tr 71 M=TXLP_PORT_STREAM_BITMAP_TABLE TSE=T SLTH=T; 4748 tr 71 M=TXLP_PORT_STREAM_BITMAP_TABLE TSE=T SLTH=F; 4749 #echo " TXLP_PORT_USED_ENTRIES"; 4750 #tr 50 M=TXLP_PORT_USED_ENTRIES; 4751 #tr 51 M=TXLP_PORT_USED_ENTRIES; 4752 #tr 52 M=TXLP_PORT_USED_ENTRIES; 4753 #tr 71 M=TXLP_PORT_USED_ENTRIES TSE=F SLTH=T; 4754 #tr 71 M=TXLP_PORT_USED_ENTRIES TSE=T SLTH=T; 4755 #tr 71 M=TXLP_PORT_USED_ENTRIES TSE=T SLTH=F; 4756 echo " TXLP_STREAM_ADDR_MAP_TABLE"; 4757 tr 50 M=TXLP_STREAM_ADDR_MAP_TABLE; 4758 tr 51 M=TXLP_STREAM_ADDR_MAP_TABLE; 4759 tr 52 M=TXLP_STREAM_ADDR_MAP_TABLE; 4760 tr 71 M=TXLP_STREAM_ADDR_MAP_TABLE TSE=F SLTH=T; 4761 tr 71 M=TXLP_STREAM_ADDR_MAP_TABLE TSE=T SLTH=T; 4762 tr 71 M=TXLP_STREAM_ADDR_MAP_TABLE TSE=T SLTH=F; 4763 #echo " TXLP_STREAM_MMU_REQUESTS"; 4764 #tr 50 M=TXLP_STREAM_MMU_REQUESTS; 4765 #tr 51 M=TXLP_STREAM_MMU_REQUESTS; 4766 #tr 52 M=TXLP_STREAM_MMU_REQUESTS; 4767 #tr 71 M=TXLP_STREAM_MMU_REQUESTS TSE=F SLTH=T; 4768 #tr 71 M=TXLP_STREAM_MMU_REQUESTS TSE=T SLTH=T; 4769 #tr 71 M=TXLP_STREAM_MMU_REQUESTS TSE=T SLTH=F; 4770 #echo " TXLP_STREAM_USED_ENTRIES"; 4771 #tr 50 M=TXLP_STREAM_USED_ENTRIES; 4772 #tr 51 M=TXLP_STREAM_USED_ENTRIES; 4773 #tr 52 M=TXLP_STREAM_USED_ENTRIES; 4774 #tr 71 M=TXLP_STREAM_USED_ENTRIES TSE=F SLTH=T; 4775 #tr 71 M=TXLP_STREAM_USED_ENTRIES TSE=T SLTH=T; 4776 #tr 71 M=TXLP_STREAM_USED_ENTRIES TSE=T SLTH=F; 4777 echo " UDF_CONDITIONAL_CHECK_TABLE_CAM"; 4778 tr 50 M=UDF_CONDITIONAL_CHECK_TABLE_CAM; 4779 tr 51 M=UDF_CONDITIONAL_CHECK_TABLE_CAM; 4780 tr 52 M=UDF_CONDITIONAL_CHECK_TABLE_CAM; 4781 tr 71 M=UDF_CONDITIONAL_CHECK_TABLE_CAM TSE=F SLTH=T; 4782 tr 71 M=UDF_CONDITIONAL_CHECK_TABLE_CAM TSE=T SLTH=T; 4783 tr 71 M=UDF_CONDITIONAL_CHECK_TABLE_CAM TSE=T SLTH=F; 4784 echo " UDF_CONDITIONAL_CHECK_TABLE_RAM"; 4785 tr 50 M=UDF_CONDITIONAL_CHECK_TABLE_RAM; 4786 tr 51 M=UDF_CONDITIONAL_CHECK_TABLE_RAM; 4787 tr 52 M=UDF_CONDITIONAL_CHECK_TABLE_RAM; 4788 tr 71 M=UDF_CONDITIONAL_CHECK_TABLE_RAM TSE=F SLTH=T; 4789 tr 71 M=UDF_CONDITIONAL_CHECK_TABLE_RAM TSE=T SLTH=T; 4790 tr 71 M=UDF_CONDITIONAL_CHECK_TABLE_RAM TSE=T SLTH=F; 4791 echo " UNKNOWN_HGI_BITMAP"; 4792 tr 50 M=UNKNOWN_HGI_BITMAP; 4793 tr 51 M=UNKNOWN_HGI_BITMAP; 4794 tr 52 M=UNKNOWN_HGI_BITMAP; 4795 tr 71 M=UNKNOWN_HGI_BITMAP TSE=F SLTH=T; 4796 tr 71 M=UNKNOWN_HGI_BITMAP TSE=T SLTH=T; 4797 tr 71 M=UNKNOWN_HGI_BITMAP TSE=T SLTH=F; 4798 echo " UNKNOWN_MCAST_BLOCK_MASK"; 4799 tr 50 M=UNKNOWN_MCAST_BLOCK_MASK; 4800 tr 51 M=UNKNOWN_MCAST_BLOCK_MASK; 4801 tr 52 M=UNKNOWN_MCAST_BLOCK_MASK; 4802 tr 71 M=UNKNOWN_MCAST_BLOCK_MASK TSE=F SLTH=T; 4803 tr 71 M=UNKNOWN_MCAST_BLOCK_MASK TSE=T SLTH=T; 4804 tr 71 M=UNKNOWN_MCAST_BLOCK_MASK TSE=T SLTH=F; 4805 echo " UNKNOWN_UCAST_BLOCK_MASK"; 4806 tr 50 M=UNKNOWN_UCAST_BLOCK_MASK; 4807 tr 51 M=UNKNOWN_UCAST_BLOCK_MASK; 4808 tr 52 M=UNKNOWN_UCAST_BLOCK_MASK; 4809 tr 71 M=UNKNOWN_UCAST_BLOCK_MASK TSE=F SLTH=T; 4810 tr 71 M=UNKNOWN_UCAST_BLOCK_MASK TSE=T SLTH=T; 4811 tr 71 M=UNKNOWN_UCAST_BLOCK_MASK TSE=T SLTH=F; 4812 echo " VFI"; 4813 tr 50 M=VFI; 4814 tr 51 M=VFI; 4815 tr 52 M=VFI; 4816 tr 71 M=VFI TSE=F SLTH=T; 4817 tr 71 M=VFI TSE=T SLTH=T; 4818 tr 71 M=VFI TSE=T SLTH=F; 4819 echo " VFI_1"; 4820 tr 50 M=VFI_1; 4821 tr 51 M=VFI_1; 4822 tr 52 M=VFI_1; 4823 tr 71 M=VFI_1 TSE=F SLTH=T; 4824 tr 71 M=VFI_1 TSE=T SLTH=T; 4825 tr 71 M=VFI_1 TSE=T SLTH=F; 4826 echo " VFP_HASH_FIELD_BMAP_TABLE_A"; 4827 tr 50 M=VFP_HASH_FIELD_BMAP_TABLE_A; 4828 tr 51 M=VFP_HASH_FIELD_BMAP_TABLE_A; 4829 tr 52 M=VFP_HASH_FIELD_BMAP_TABLE_A; 4830 tr 71 M=VFP_HASH_FIELD_BMAP_TABLE_A TSE=F SLTH=T; 4831 tr 71 M=VFP_HASH_FIELD_BMAP_TABLE_A TSE=T SLTH=T; 4832 tr 71 M=VFP_HASH_FIELD_BMAP_TABLE_A TSE=T SLTH=F; 4833 echo " VFP_HASH_FIELD_BMAP_TABLE_B"; 4834 tr 50 M=VFP_HASH_FIELD_BMAP_TABLE_B; 4835 tr 51 M=VFP_HASH_FIELD_BMAP_TABLE_B; 4836 tr 52 M=VFP_HASH_FIELD_BMAP_TABLE_B; 4837 tr 71 M=VFP_HASH_FIELD_BMAP_TABLE_B TSE=F SLTH=T; 4838 tr 71 M=VFP_HASH_FIELD_BMAP_TABLE_B TSE=T SLTH=T; 4839 tr 71 M=VFP_HASH_FIELD_BMAP_TABLE_B TSE=T SLTH=F; 4840 echo " VFP_POLICY_TABLE"; 4841 tr 50 M=VFP_POLICY_TABLE; 4842 tr 51 M=VFP_POLICY_TABLE; 4843 tr 52 M=VFP_POLICY_TABLE; 4844 tr 71 M=VFP_POLICY_TABLE TSE=F SLTH=T; 4845 tr 71 M=VFP_POLICY_TABLE TSE=T SLTH=T; 4846 tr 71 M=VFP_POLICY_TABLE TSE=T SLTH=F; 4847 echo " VFP_TCAM"; 4848 tr 50 M=VFP_TCAM; 4849 tr 51 M=VFP_TCAM; 4850 tr 52 M=VFP_TCAM; 4851 tr 71 M=VFP_TCAM TSE=F SLTH=T; 4852 tr 71 M=VFP_TCAM TSE=T SLTH=T; 4853 tr 71 M=VFP_TCAM TSE=T SLTH=F; 4854 echo " VLAN_MAC"; 4855 tr 50 M=VLAN_MAC; 4856 tr 51 M=VLAN_MAC; 4857 tr 52 M=VLAN_MAC; 4858 tr 71 M=VLAN_MAC TSE=F SLTH=T; 4859 tr 71 M=VLAN_MAC TSE=T SLTH=T; 4860 tr 71 M=VLAN_MAC TSE=T SLTH=F; 4861 echo " VLAN_MAC_OVERFLOW"; 4862 tr 50 M=VLAN_MAC_OVERFLOW; 4863 tr 51 M=VLAN_MAC_OVERFLOW; 4864 tr 52 M=VLAN_MAC_OVERFLOW; 4865 tr 71 M=VLAN_MAC_OVERFLOW TSE=F SLTH=T; 4866 tr 71 M=VLAN_MAC_OVERFLOW TSE=T SLTH=T; 4867 tr 71 M=VLAN_MAC_OVERFLOW TSE=T SLTH=F; 4868 echo " VLAN_MPLS"; 4869 tr 50 M=VLAN_MPLS; 4870 tr 51 M=VLAN_MPLS; 4871 tr 52 M=VLAN_MPLS; 4872 tr 71 M=VLAN_MPLS TSE=F SLTH=T; 4873 tr 71 M=VLAN_MPLS TSE=T SLTH=T; 4874 tr 71 M=VLAN_MPLS TSE=T SLTH=F; 4875 echo " VLAN_OR_VFI_MAC_COUNT"; 4876 tr 50 M=VLAN_OR_VFI_MAC_COUNT; 4877 tr 51 M=VLAN_OR_VFI_MAC_COUNT; 4878 tr 52 M=VLAN_OR_VFI_MAC_COUNT; 4879 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=F SLTH=T; 4880 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=T SLTH=T; 4881 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=T SLTH=F; 4882 echo " VLAN_OR_VFI_MAC_LIMIT"; 4883 tr 50 M=VLAN_OR_VFI_MAC_LIMIT; 4884 tr 51 M=VLAN_OR_VFI_MAC_LIMIT; 4885 tr 52 M=VLAN_OR_VFI_MAC_LIMIT; 4886 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=F SLTH=T; 4887 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=T SLTH=T; 4888 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=T SLTH=F; 4889 echo " VLAN_PROFILE_2"; 4890 tr 50 M=VLAN_PROFILE_2; 4891 tr 51 M=VLAN_PROFILE_2; 4892 tr 52 M=VLAN_PROFILE_2; 4893 tr 71 M=VLAN_PROFILE_2 TSE=F SLTH=T; 4894 tr 71 M=VLAN_PROFILE_2 TSE=T SLTH=T; 4895 tr 71 M=VLAN_PROFILE_2 TSE=T SLTH=F; 4896 echo " VLAN_PROFILE_TAB"; 4897 tr 50 M=VLAN_PROFILE_TAB; 4898 tr 51 M=VLAN_PROFILE_TAB; 4899 tr 52 M=VLAN_PROFILE_TAB; 4900 tr 71 M=VLAN_PROFILE_TAB TSE=F SLTH=T; 4901 tr 71 M=VLAN_PROFILE_TAB TSE=T SLTH=T; 4902 tr 71 M=VLAN_PROFILE_TAB TSE=T SLTH=F; 4903 echo " VLAN_PROTOCOL"; 4904 tr 50 M=VLAN_PROTOCOL; 4905 tr 51 M=VLAN_PROTOCOL; 4906 tr 52 M=VLAN_PROTOCOL; 4907 tr 71 M=VLAN_PROTOCOL TSE=F SLTH=T; 4908 tr 71 M=VLAN_PROTOCOL TSE=T SLTH=T; 4909 tr 71 M=VLAN_PROTOCOL TSE=T SLTH=F; 4910 echo " VLAN_PROTOCOL_DATA"; 4911 tr 50 M=VLAN_PROTOCOL_DATA; 4912 tr 51 M=VLAN_PROTOCOL_DATA; 4913 tr 52 M=VLAN_PROTOCOL_DATA; 4914 tr 71 M=VLAN_PROTOCOL_DATA TSE=F SLTH=T; 4915 tr 71 M=VLAN_PROTOCOL_DATA TSE=T SLTH=T; 4916 tr 71 M=VLAN_PROTOCOL_DATA TSE=T SLTH=F; 4917 echo " VLAN_SUBNET"; 4918 tr 50 M=VLAN_SUBNET; 4919 tr 51 M=VLAN_SUBNET; 4920 tr 52 M=VLAN_SUBNET; 4921 tr 71 M=VLAN_SUBNET TSE=F SLTH=T; 4922 tr 71 M=VLAN_SUBNET TSE=T SLTH=T; 4923 tr 71 M=VLAN_SUBNET TSE=T SLTH=F; 4924 echo " VLAN_SUBNET_DATA_ONLY"; 4925 tr 50 M=VLAN_SUBNET_DATA_ONLY; 4926 tr 51 M=VLAN_SUBNET_DATA_ONLY; 4927 tr 52 M=VLAN_SUBNET_DATA_ONLY; 4928 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=F SLTH=T; 4929 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=T SLTH=T; 4930 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=T SLTH=F; 4931 echo " VLAN_SUBNET_ONLY"; 4932 tr 50 M=VLAN_SUBNET_ONLY; 4933 tr 51 M=VLAN_SUBNET_ONLY; 4934 tr 52 M=VLAN_SUBNET_ONLY; 4935 tr 71 M=VLAN_SUBNET_ONLY TSE=F SLTH=T; 4936 tr 71 M=VLAN_SUBNET_ONLY TSE=T SLTH=T; 4937 tr 71 M=VLAN_SUBNET_ONLY TSE=T SLTH=F; 4938 echo " VLAN_TAB"; 4939 tr 50 M=VLAN_TAB; 4940 tr 51 M=VLAN_TAB; 4941 tr 52 M=VLAN_TAB; 4942 tr 71 M=VLAN_TAB TSE=F SLTH=T; 4943 tr 71 M=VLAN_TAB TSE=T SLTH=T; 4944 tr 71 M=VLAN_TAB TSE=T SLTH=F; 4945 echo " VLAN_XLATE"; 4946 tr 50 M=VLAN_XLATE; 4947 tr 51 M=VLAN_XLATE; 4948 tr 52 M=VLAN_XLATE; 4949 tr 71 M=VLAN_XLATE TSE=F SLTH=T; 4950 tr 71 M=VLAN_XLATE TSE=T SLTH=T; 4951 tr 71 M=VLAN_XLATE TSE=T SLTH=F; 4952 echo " VLAN_XLATE_OVERFLOW"; 4953 tr 50 M=VLAN_XLATE_OVERFLOW; 4954 tr 51 M=VLAN_XLATE_OVERFLOW; 4955 tr 52 M=VLAN_XLATE_OVERFLOW; 4956 tr 71 M=VLAN_XLATE_OVERFLOW TSE=F SLTH=T; 4957 tr 71 M=VLAN_XLATE_OVERFLOW TSE=T SLTH=T; 4958 tr 71 M=VLAN_XLATE_OVERFLOW TSE=T SLTH=F; 4959 echo " VRF"; 4960 tr 50 M=VRF; 4961 tr 51 M=VRF; 4962 tr 52 M=VRF; 4963 tr 71 M=VRF TSE=F SLTH=T; 4964 tr 71 M=VRF TSE=T SLTH=T; 4965 tr 71 M=VRF TSE=T SLTH=F; 4966 echo " XPORT_WC_UCMEM_DATA"; 4967 #tr 50 M=XPORT_WC_UCMEM_DATA; 4968 #tr 51 M=XPORT_WC_UCMEM_DATA; 4969 #tr 52 M=XPORT_WC_UCMEM_DATA; 4970 #tr 71 M=XPORT_WC_UCMEM_DATA TSE=F SLTH=T; 4971 #tr 71 M=XPORT_WC_UCMEM_DATA TSE=T SLTH=T; 4972 #tr 71 M=XPORT_WC_UCMEM_DATA TSE=T SLTH=F; 4973 4974 # Re-initialize to clean up of various read/wrires to MMU memories 4975 set rctest=true 4976 set rcload=true 4977 rcload rc.soc 4978 counter off 4979 l2mode off 4980 linkscan off 4981 4982 echo "Running counter width verification test ..." 4983 tr 30 4984 $done 4985 4986 echo "Running counter read/write test ..." 4987 tr 31 4988 $done 4989 4990 #L2/L3 hashing tests 4991 echo "Running L2 insert/delete/lookup test ..." 4992 tr 32 4993 $done 4994 4995 echo "Running L2 overflow insert test ..." 4996 tr 33 4997 $done 4998 4999 if !$?LIKE_BCM56248 \ 5000 'echo "Running L2 hash test ..."; \ 5001 tr 34; \ 5002 $done; \ 5003 echo "Running L2 delete by port test ..."; \ 5004 tr 35; \ 5005 $done; \ 5006 echo "Running L2 delete by vlan test ..."; \ 5007 tr 36; \ 5008 $done;' 5009 5010 if !$?LIKE_BCM55455 && $?run_full_sanity \ 5011 'echo "Running IPV4 overflow insert test ..."; \ 5012 tr 87 IPMCEnable=False; \ 5013 tr 87 IPMCEnable=True; \ 5014 $done; \ 5015 echo "Running IPV6 hash test ..."; \ 5016 tr 88 IPMCEnable=False; \ 5017 tr 88 IPMCEnable=True; \ 5018 $done; \ 5019 echo "Running IPV6 overflow insert test ..."; \ 5020 tr 85 IPMCEnable=False; \ 5021 tr 85 IPMCEnable=True; \ 5022 $done; \ 5023 echo "Running IPV6 hash test ..."; \ 5024 tr 86 IPMCEnable=False; \ 5025 tr 86 IPMCEnable=True; \ 5026 $done;' 5027 5028 echo "Running VLAN translate overflow insert test ..." 5029 tr 100; 5030 $done; 5031 5032 if $?run_full_sanity \ 5033 'echo "Running VLAN translate hash tests ..."; \ 5034 rc; \ 5035 tr 101 hash=0; \ 5036 tr 101 hash=1; \ 5037 tr 101 hash=2; \ 5038 tr 101 hash=3; \ 5039 tr 101 hash=4; \ 5040 tr 101 hash=5; \ 5041 $done;' 5042 5043 echo "Running Egress VLAN translate overflow insert test ..." 5044 tr 102; 5045 $done; 5046 5047 if $?run_full_sanity \ 5048 'echo "Running Egress VLAN translate hash tests ..."; \ 5049 rc; \ 5050 tr 103 hash=0; \ 5051 tr 103 hash=1; \ 5052 tr 103 hash=2; \ 5053 tr 103 hash=3; \ 5054 tr 103 hash=4; \ 5055 tr 103 hash=5; \ 5056 $done;' 5057 5058 if $?run_full_sanity \ 5059 'echo "Running MPLS overflow insert test ..."; \ 5060 tr 104; \ 5061 $done;' 5062 5063 if $?run_full_sanity \ 5064 'echo "Running MPLS hash tests ..."; \ 5065 tr 105 hash=0; \ 5066 tr 105 hash=1; \ 5067 tr 105 hash=2; \ 5068 tr 105 hash=3; \ 5069 tr 105 hash=4; \ 5070 tr 105 hash=5; \ 5071 $done;' 5072 5073 echo "Running MDIO Linkscan test" 5074 tr 60 readcount=10000 5075 $done 5076 5077 rc 5078 5079 if $?run_full_sanity \ 5080 'echo "Testing CPU DMA loopback ..."; \ 5081 tr 17 c=5; \ 5082 $done;' 5083 5084 if $?run_full_sanity \ 5085 'echo "Testing CPU DMA, Scatter/Gather Reload ..."; \ 5086 tr 22; \ 5087 $done;' 5088 5089 if $?run_full_sanity \ 5090 'echo "Testing CPU DMA, Scatter/Gather Simple ..."; \ 5091 tr 23; \ 5092 $done;' 5093 5094 if $?run_full_sanity \ 5095 'echo "Testing CPU DMA, Scatter/Gather Random ..."; \ 5096 tr 24; \ 5097 $done;' 5098 5099 #Internal snake Loopback 5100 if $?BCM56452_B0 || $?BCM56455_B0 || $?BCM56457_B0 \ 5101 'echo "Running internal snake on all ports, MAC loopback ..."; \ 5102 tr 39 loopbackmode=mac snakepath=two PBM=e; \ 5103 echo "Running internal snake on all ports, PHY loopback ..."; \ 5104 tr 39 loopbackmode=phy snakepath=two PBM=e; \ 5105 $done; ' \ 5106 else \ 5107 'echo "Running internal snake on all ports, MAC loopback ..."; \ 5108 tr 39 loopbackmode=mac snakepath=two PBM=xe; \ 5109 echo "Running internal snake on all ports, PHY loopback ..."; \ 5110 tr 39 loopbackmode=phy snakepath=two PBM=xe; \ 5111 $done;' 5112 5113 if $?run_full_sanity \ 5114 'echo "Running Mac loopback test case on ge port ..."; \ 5115 tr 18 pbm=xe speed=10G; \ 5116 $done;' 5117 5118 if $?run_full_sanity "local phy_mode none" else "local phy_mode ge" 5119 5120 5121 echo "Running PHY External loopback test case on ge port ..." 5122 if $?BCM56455_A0 || $?BCM56455_B0 \ 5123 'tr 19 pbm=ge epbm=none; \ 5124 $done; ' \ 5125 else \ 5126 'tr 19 pbm=ge epbm=$phy_mode; \ 5127 $done;' 5128 5129 if $?run_full_sanity \ 5130 'echo "Running MAC loopback V2 on all ports ..."; \ 5131 tr 48 pbm=e smi=103 dmi=42 vlan=5 pi=0x11335577 sendm=single; \ 5132 $done;' 5133 5134 if $?run_full_sanity \ 5135 'echo "Running PHY loopback V2 on all ports ..."; \ 5136 tr 49 pbm=e smi=52 dmi=83 vlan=23 pi=0x01204007; \ 5137 $done;' 5138 5139 #Traffic Test 5140 if $?run_full_sanity "local ext_phy_mode MAC" else "local ext_phy_mode external" 5141 5142 echo "Running Traffic Test in external mode on xe port..." 5143 if $?BCM56455_A0 || $?BCM56455_B0 \ 5144 'tr 72 RM=$ext_phy_mode PBM=hg; \ 5145 $done; ' \ 5146 else \ 5147 'tr 72 RM=$ext_phy_mode PBM=xe; \ 5148 $done; ' 5149 5150 #SNMP 5151 if $?run_full_sanity \ 5152 'echo "SNMP MIB Object Test"; \ 5153 tr 73; \ 5154 $done;' 5155 5156 #Reload Test 5157 #echo "TX Reload Test" 5158 #tr 90 5159 #$done 5160 5161 #echo "RX Reload Test" 5162 #tr 91 5163 #$done 5164 5165 echo "Running Software Error Recovery Test ..." 5166 config add parity_enable=1 5167 rc 5168 linkscan off 5169 tr 144; 5170 $done; 5171 config add parity_enable=0; 5172 config parity_enable=0; 5173 5174 if !$?LIKE_BCM56456 \ 5175 'echo "DDR memory Test"; \ 5176 config add pbmp_ext_mem=0x2222; \ 5177 rc; \ 5178 ddrphytune $CIs plot=false ct=1 pt=1; \ 5179 tr 140 dn=$DNs ww=255 rw=255 bna=1000000 ea=0xffffff pm=1; \ 5180 config delete pbmp_ext_mem; \ 5181 $done; ' 5182 5183 set rct=t; set rcl=t; 5184 # Show status 5185 date 5186 tl 5187 local returnCode $? 5188 5189 echo Tests Complete. Reinitializing ... 5190 config refresh 5191 rcload rc.soc 5192 counter off 5193 l2mode off 5194 5195 # We want to show the return code from the tl command which 5196 # lists the results. The automated test infrastructure keys off of this 5197 # value 5198 echo "testsuite: finished: sanity: $returnCode"