ghsanity.soc (64600B)
1 # 2 # This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 # 4 # Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 6 # Greyhound (BCM53400) Sanity 7 # 8 # Script to run all available tests as quickly as possible. 9 # For testing basic sanity of new drivers, simulators, chips, etc. 10 # 11 12 # Greyhound, 53369 13 if $?BCM53400_A0 || \ 14 $?BCM53401_A0 || $?BCM53402_A0 || $?BCM53403_A0 || $?BCM53404_A0 || \ 15 $?BCM53405_A0 || $?BCM53406_A0 || $?BCM53408_A0 || $?BCM53369_A0 || \ 16 $?BCM53411_A0 || $?BCM53412_A0 || $?BCM53413_A0 || $?BCM53414_A0 || \ 17 $?BCM53415_A0 || $?BCM53416_A0 || $?BCM53418_A0 \ 18 'local BCM534XX_A0 1' 19 20 # Ranger2 21 if $?BCM56060_A0 || $?BCM56062_A0 || $?BCM56063_A0 || $?BCM56064_A0 || \ 22 $?BCM56065_A0 || $?BCM56066_A0 \ 23 'local BCM5606X_A0 1' 24 25 # Elkhound 26 if $?BCM53454_A0 || $?BCM53455_A0 || $?BCM53456_A0 || $?BCM53457_A0 \ 27 'local BCM5345X_A0 1' 28 29 # Bloodhound, 53365 30 if $?BCM53422_A0 || $?BCM53424_A0 || $?BCM53426_A0 || $?BCM53365_A0 \ 31 'local BCM5342X_A0 1' 32 33 echo "testsuite: started: sanity" 34 rcload rc.soc 35 counter off 36 l2mode off 37 38 # We need to print out port status since any cabling effects results. 39 *:ps 40 41 # Avoid link messages while testing 42 linkscan off 43 44 init 45 init misc 46 init mmu 47 48 local done 'echo " Done"' 49 50 # Set run command script not to fail on errors reported by commands 51 # this allows the script to continue if a test fails 52 set rcerror=false 53 54 # Set up test mode: don't stop on errors, show progress on each test 55 tm -stoponerror +progress 56 # Unselect all 57 ts -* 58 59 #Display some useful information 60 date 61 ver 62 soc 63 64 #Start Test 65 if !$?ihost_mode \ 66 'echo "Running PCI Compliance ...";\ 67 tr 2;\ 68 $done;' 69 70 #Start Test 71 echo "Running PCI S-Channel Buf ..." 72 tr 4 73 $done 74 75 echo "Running Register reset defaults ..." 76 tr 1 77 $done 78 79 echo "Running Register read/write ..." 80 tr 3 mask64 81 $done 82 83 init soc; init misc; init mmu; 84 #Clean up after register read/write test. 85 86 rcload rc.soc 87 counter off 88 l2mode off 89 echo "Running CPU Benchmarks ..." 90 tr 21 91 $done 92 linkscan off 93 94 set rct=false 95 96 echo "Running Switching Memory Tests ..." 97 98 #Need to init misc before testing for MMU_XQ0, 1 ~29 99 init soc; init misc; 100 101 echo " MMU_XQ0"; 102 tr 50 M=MMU_XQ0; 103 tr 51 M=MMU_XQ0; 104 tr 52 M=MMU_XQ0; 105 tr 71 M=MMU_XQ0 TSE=F SLTH=T; 106 tr 71 M=MMU_XQ0 TSE=T SLTH=T; 107 tr 71 M=MMU_XQ0 TSE=T SLTH=F; 108 echo " MMU_XQ10"; 109 tr 50 M=MMU_XQ10; 110 tr 51 M=MMU_XQ10; 111 tr 52 M=MMU_XQ10; 112 tr 71 M=MMU_XQ10 TSE=F SLTH=T; 113 tr 71 M=MMU_XQ10 TSE=T SLTH=T; 114 tr 71 M=MMU_XQ10 TSE=T SLTH=F; 115 echo " MMU_XQ11"; 116 tr 50 M=MMU_XQ11; 117 tr 51 M=MMU_XQ11; 118 tr 52 M=MMU_XQ11; 119 tr 71 M=MMU_XQ11 TSE=F SLTH=T; 120 tr 71 M=MMU_XQ11 TSE=T SLTH=T; 121 tr 71 M=MMU_XQ11 TSE=T SLTH=F; 122 echo " MMU_XQ12"; 123 tr 50 M=MMU_XQ12; 124 tr 51 M=MMU_XQ12; 125 tr 52 M=MMU_XQ12; 126 tr 71 M=MMU_XQ12 TSE=F SLTH=T; 127 tr 71 M=MMU_XQ12 TSE=T SLTH=T; 128 tr 71 M=MMU_XQ12 TSE=T SLTH=F; 129 echo " MMU_XQ13"; 130 tr 50 M=MMU_XQ13; 131 tr 51 M=MMU_XQ13; 132 tr 52 M=MMU_XQ13; 133 tr 71 M=MMU_XQ13 TSE=F SLTH=T; 134 tr 71 M=MMU_XQ13 TSE=T SLTH=T; 135 tr 71 M=MMU_XQ13 TSE=T SLTH=F; 136 echo " MMU_XQ14"; 137 tr 50 M=MMU_XQ14; 138 tr 51 M=MMU_XQ14; 139 tr 52 M=MMU_XQ14; 140 tr 71 M=MMU_XQ14 TSE=F SLTH=T; 141 tr 71 M=MMU_XQ14 TSE=T SLTH=T; 142 tr 71 M=MMU_XQ14 TSE=T SLTH=F; 143 echo " MMU_XQ15"; 144 tr 50 M=MMU_XQ15; 145 tr 51 M=MMU_XQ15; 146 tr 52 M=MMU_XQ15; 147 tr 71 M=MMU_XQ15 TSE=F SLTH=T; 148 tr 71 M=MMU_XQ15 TSE=T SLTH=T; 149 tr 71 M=MMU_XQ15 TSE=T SLTH=F; 150 echo " MMU_XQ16"; 151 tr 50 M=MMU_XQ16; 152 tr 51 M=MMU_XQ16; 153 tr 52 M=MMU_XQ16; 154 tr 71 M=MMU_XQ16 TSE=F SLTH=T; 155 tr 71 M=MMU_XQ16 TSE=T SLTH=T; 156 tr 71 M=MMU_XQ16 TSE=T SLTH=F; 157 echo " MMU_XQ17"; 158 tr 50 M=MMU_XQ17; 159 tr 51 M=MMU_XQ17; 160 tr 52 M=MMU_XQ17; 161 tr 71 M=MMU_XQ17 TSE=F SLTH=T; 162 tr 71 M=MMU_XQ17 TSE=T SLTH=T; 163 tr 71 M=MMU_XQ17 TSE=T SLTH=F; 164 echo " MMU_XQ18"; 165 tr 50 M=MMU_XQ18; 166 tr 51 M=MMU_XQ18; 167 tr 52 M=MMU_XQ18; 168 tr 71 M=MMU_XQ18 TSE=F SLTH=T; 169 tr 71 M=MMU_XQ18 TSE=T SLTH=T; 170 tr 71 M=MMU_XQ18 TSE=T SLTH=F; 171 echo " MMU_XQ19"; 172 tr 50 M=MMU_XQ19; 173 tr 51 M=MMU_XQ19; 174 tr 52 M=MMU_XQ19; 175 tr 71 M=MMU_XQ19 TSE=F SLTH=T; 176 tr 71 M=MMU_XQ19 TSE=T SLTH=T; 177 tr 71 M=MMU_XQ19 TSE=T SLTH=F; 178 echo " MMU_XQ2"; 179 tr 50 M=MMU_XQ2; 180 tr 51 M=MMU_XQ2; 181 tr 52 M=MMU_XQ2; 182 tr 71 M=MMU_XQ2 TSE=F SLTH=T; 183 tr 71 M=MMU_XQ2 TSE=T SLTH=T; 184 tr 71 M=MMU_XQ2 TSE=T SLTH=F; 185 echo " MMU_XQ20"; 186 tr 50 M=MMU_XQ20; 187 tr 51 M=MMU_XQ20; 188 tr 52 M=MMU_XQ20; 189 tr 71 M=MMU_XQ20 TSE=F SLTH=T; 190 tr 71 M=MMU_XQ20 TSE=T SLTH=T; 191 tr 71 M=MMU_XQ20 TSE=T SLTH=F; 192 echo " MMU_XQ21"; 193 tr 50 M=MMU_XQ21; 194 tr 51 M=MMU_XQ21; 195 tr 52 M=MMU_XQ21; 196 tr 71 M=MMU_XQ21 TSE=F SLTH=T; 197 tr 71 M=MMU_XQ21 TSE=T SLTH=T; 198 tr 71 M=MMU_XQ21 TSE=T SLTH=F; 199 echo " MMU_XQ22"; 200 tr 50 M=MMU_XQ22; 201 tr 51 M=MMU_XQ22; 202 tr 52 M=MMU_XQ22; 203 tr 71 M=MMU_XQ22 TSE=F SLTH=T; 204 tr 71 M=MMU_XQ22 TSE=T SLTH=T; 205 tr 71 M=MMU_XQ22 TSE=T SLTH=F; 206 echo " MMU_XQ23"; 207 tr 50 M=MMU_XQ23; 208 tr 51 M=MMU_XQ23; 209 tr 52 M=MMU_XQ23; 210 tr 71 M=MMU_XQ23 TSE=F SLTH=T; 211 tr 71 M=MMU_XQ23 TSE=T SLTH=T; 212 tr 71 M=MMU_XQ23 TSE=T SLTH=F; 213 echo " MMU_XQ24"; 214 tr 50 M=MMU_XQ24; 215 tr 51 M=MMU_XQ24; 216 tr 52 M=MMU_XQ24; 217 tr 71 M=MMU_XQ24 TSE=F SLTH=T; 218 tr 71 M=MMU_XQ24 TSE=T SLTH=T; 219 tr 71 M=MMU_XQ24 TSE=T SLTH=F; 220 echo " MMU_XQ25"; 221 tr 50 M=MMU_XQ25; 222 tr 51 M=MMU_XQ25; 223 tr 52 M=MMU_XQ25; 224 tr 71 M=MMU_XQ25 TSE=F SLTH=T; 225 tr 71 M=MMU_XQ25 TSE=T SLTH=T; 226 tr 71 M=MMU_XQ25 TSE=T SLTH=F; 227 echo " MMU_XQ26"; 228 tr 50 M=MMU_XQ26; 229 tr 51 M=MMU_XQ26; 230 tr 52 M=MMU_XQ26; 231 tr 71 M=MMU_XQ26 TSE=F SLTH=T; 232 tr 71 M=MMU_XQ26 TSE=T SLTH=T; 233 tr 71 M=MMU_XQ26 TSE=T SLTH=F; 234 echo " MMU_XQ27"; 235 tr 50 M=MMU_XQ27; 236 tr 51 M=MMU_XQ27; 237 tr 52 M=MMU_XQ27; 238 tr 71 M=MMU_XQ27 TSE=F SLTH=T; 239 tr 71 M=MMU_XQ27 TSE=T SLTH=T; 240 tr 71 M=MMU_XQ27 TSE=T SLTH=F; 241 echo " MMU_XQ28"; 242 tr 50 M=MMU_XQ28; 243 tr 51 M=MMU_XQ28; 244 tr 52 M=MMU_XQ28; 245 tr 71 M=MMU_XQ28 TSE=F SLTH=T; 246 tr 71 M=MMU_XQ28 TSE=T SLTH=T; 247 tr 71 M=MMU_XQ28 TSE=T SLTH=F; 248 echo " MMU_XQ29"; 249 tr 50 M=MMU_XQ29; 250 tr 51 M=MMU_XQ29; 251 tr 52 M=MMU_XQ29; 252 tr 71 M=MMU_XQ29 TSE=F SLTH=T; 253 tr 71 M=MMU_XQ29 TSE=T SLTH=T; 254 tr 71 M=MMU_XQ29 TSE=T SLTH=F; 255 echo " MMU_XQ3"; 256 tr 50 M=MMU_XQ3; 257 tr 51 M=MMU_XQ3; 258 tr 52 M=MMU_XQ3; 259 tr 71 M=MMU_XQ3 TSE=F SLTH=T; 260 tr 71 M=MMU_XQ3 TSE=T SLTH=T; 261 tr 71 M=MMU_XQ3 TSE=T SLTH=F; 262 echo " MMU_XQ4"; 263 tr 50 M=MMU_XQ4; 264 tr 51 M=MMU_XQ4; 265 tr 52 M=MMU_XQ4; 266 tr 71 M=MMU_XQ4 TSE=F SLTH=T; 267 tr 71 M=MMU_XQ4 TSE=T SLTH=T; 268 tr 71 M=MMU_XQ4 TSE=T SLTH=F; 269 echo " MMU_XQ5"; 270 tr 50 M=MMU_XQ5; 271 tr 51 M=MMU_XQ5; 272 tr 52 M=MMU_XQ5; 273 tr 71 M=MMU_XQ5 TSE=F SLTH=T; 274 tr 71 M=MMU_XQ5 TSE=T SLTH=T; 275 tr 71 M=MMU_XQ5 TSE=T SLTH=F; 276 echo " MMU_XQ6"; 277 tr 50 M=MMU_XQ6; 278 tr 51 M=MMU_XQ6; 279 tr 52 M=MMU_XQ6; 280 tr 71 M=MMU_XQ6 TSE=F SLTH=T; 281 tr 71 M=MMU_XQ6 TSE=T SLTH=T; 282 tr 71 M=MMU_XQ6 TSE=T SLTH=F; 283 echo " MMU_XQ7"; 284 tr 50 M=MMU_XQ7; 285 tr 51 M=MMU_XQ7; 286 tr 52 M=MMU_XQ7; 287 tr 71 M=MMU_XQ7 TSE=F SLTH=T; 288 tr 71 M=MMU_XQ7 TSE=T SLTH=T; 289 tr 71 M=MMU_XQ7 TSE=T SLTH=F; 290 echo " MMU_XQ8"; 291 tr 50 M=MMU_XQ8; 292 tr 51 M=MMU_XQ8; 293 tr 52 M=MMU_XQ8; 294 tr 71 M=MMU_XQ8 TSE=F SLTH=T; 295 tr 71 M=MMU_XQ8 TSE=T SLTH=T; 296 tr 71 M=MMU_XQ8 TSE=T SLTH=F; 297 echo " MMU_XQ9"; 298 tr 50 M=MMU_XQ9; 299 tr 51 M=MMU_XQ9; 300 tr 52 M=MMU_XQ9; 301 tr 71 M=MMU_XQ9 TSE=F SLTH=T; 302 tr 71 M=MMU_XQ9 TSE=T SLTH=T; 303 tr 71 M=MMU_XQ9 TSE=T SLTH=F; 304 305 init soc; init mmu; 306 307 echo " ALTERNATE_EMIRROR_BITMAP"; 308 tr 50 M=ALTERNATE_EMIRROR_BITMAP; 309 tr 51 M=ALTERNATE_EMIRROR_BITMAP; 310 tr 52 M=ALTERNATE_EMIRROR_BITMAP; 311 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=F SLTH=T; 312 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=T SLTH=T; 313 tr 71 M=ALTERNATE_EMIRROR_BITMAP TSE=T SLTH=F; 314 echo " CPU_COS_MAP"; 315 tr 50 M=CPU_COS_MAP; 316 tr 51 M=CPU_COS_MAP; 317 tr 52 M=CPU_COS_MAP; 318 tr 71 M=CPU_COS_MAP TSE=F SLTH=T; 319 tr 71 M=CPU_COS_MAP TSE=T SLTH=T; 320 tr 71 M=CPU_COS_MAP TSE=T SLTH=F; 321 echo " CPU_COS_MAP_DATA_ONLY"; 322 tr 50 M=CPU_COS_MAP_DATA_ONLY; 323 tr 51 M=CPU_COS_MAP_DATA_ONLY; 324 tr 52 M=CPU_COS_MAP_DATA_ONLY; 325 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=F SLTH=T; 326 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=T SLTH=T; 327 tr 71 M=CPU_COS_MAP_DATA_ONLY TSE=T SLTH=F; 328 echo " CPU_COS_MAP_ONLY"; 329 tr 50 M=CPU_COS_MAP_ONLY; 330 tr 51 M=CPU_COS_MAP_ONLY; 331 tr 52 M=CPU_COS_MAP_ONLY; 332 tr 71 M=CPU_COS_MAP_ONLY TSE=F SLTH=T; 333 tr 71 M=CPU_COS_MAP_ONLY TSE=T SLTH=T; 334 tr 71 M=CPU_COS_MAP_ONLY TSE=T SLTH=F; 335 echo " CPU_TS_MAP"; 336 tr 50 M=CPU_TS_MAP; 337 tr 51 M=CPU_TS_MAP; 338 tr 52 M=CPU_TS_MAP; 339 tr 71 M=CPU_TS_MAP TSE=F SLTH=T; 340 tr 71 M=CPU_TS_MAP TSE=T SLTH=T; 341 tr 71 M=CPU_TS_MAP TSE=T SLTH=F; 342 echo " DSCP_TABLE"; 343 tr 50 M=DSCP_TABLE; 344 tr 51 M=DSCP_TABLE; 345 tr 52 M=DSCP_TABLE; 346 tr 71 M=DSCP_TABLE TSE=F SLTH=T; 347 tr 71 M=DSCP_TABLE TSE=T SLTH=T; 348 tr 71 M=DSCP_TABLE TSE=T SLTH=F; 349 if $?BCM5606X_A0 \ 350 'echo " EFP_COUNTER_TABLE"; \ 351 tr 50 M=EFP_COUNTER_TABLE; \ 352 tr 51 M=EFP_COUNTER_TABLE; \ 353 tr 52 M=EFP_COUNTER_TABLE; \ 354 tr 71 M=EFP_COUNTER_TABLE TSE=F SLTH=T; \ 355 tr 71 M=EFP_COUNTER_TABLE TSE=T SLTH=T; \ 356 tr 71 M=EFP_COUNTER_TABLE TSE=T SLTH=F; \ 357 echo " EFP_METER_TABLE"; \ 358 tr 50 M=EFP_METER_TABLE; \ 359 tr 51 M=EFP_METER_TABLE; \ 360 tr 52 M=EFP_METER_TABLE; \ 361 tr 71 M=EFP_METER_TABLE TSE=F SLTH=T; \ 362 tr 71 M=EFP_METER_TABLE TSE=T SLTH=T; \ 363 tr 71 M=EFP_METER_TABLE TSE=T SLTH=F; \ 364 echo " EFP_POLICY_TABLE"; \ 365 tr 50 M=EFP_POLICY_TABLE; \ 366 tr 51 M=EFP_POLICY_TABLE; \ 367 tr 52 M=EFP_POLICY_TABLE; \ 368 tr 71 M=EFP_POLICY_TABLE TSE=F SLTH=T; \ 369 tr 71 M=EFP_POLICY_TABLE TSE=T SLTH=T; \ 370 tr 71 M=EFP_POLICY_TABLE TSE=T SLTH=F; \ 371 echo " EFP_TCAM"; \ 372 tr 50 M=EFP_TCAM; \ 373 tr 51 M=EFP_TCAM; \ 374 tr 52 M=EFP_TCAM; \ 375 tr 71 M=EFP_TCAM TSE=F SLTH=T; \ 376 tr 71 M=EFP_TCAM TSE=T SLTH=T; \ 377 tr 71 M=EFP_TCAM TSE=T SLTH=F; \ 378 echo " VFP_POLICY_TABLE"; \ 379 tr 50 M=VFP_POLICY_TABLE; \ 380 tr 51 M=VFP_POLICY_TABLE; \ 381 tr 52 M=VFP_POLICY_TABLE; \ 382 tr 71 M=VFP_POLICY_TABLE TSE=F SLTH=T; \ 383 tr 71 M=VFP_POLICY_TABLE TSE=T SLTH=T; \ 384 tr 71 M=VFP_POLICY_TABLE TSE=T SLTH=F; \ 385 echo " VFP_TCAM"; \ 386 tr 50 M=VFP_TCAM; \ 387 tr 51 M=VFP_TCAM; \ 388 tr 52 M=VFP_TCAM; \ 389 tr 71 M=VFP_TCAM TSE=F SLTH=T; \ 390 tr 71 M=VFP_TCAM TSE=T SLTH=T; \ 391 tr 71 M=VFP_TCAM TSE=T SLTH=F; \ 392 echo " INITIAL_L3_ECMP"; \ 393 tr 50 M=INITIAL_L3_ECMP; \ 394 tr 51 M=INITIAL_L3_ECMP; \ 395 tr 52 M=INITIAL_L3_ECMP; \ 396 tr 71 M=INITIAL_L3_ECMP TSE=F SLTH=T; \ 397 tr 71 M=INITIAL_L3_ECMP TSE=T SLTH=T; \ 398 tr 71 M=INITIAL_L3_ECMP TSE=T SLTH=F; \ 399 echo " INITIAL_L3_ECMP_GROUP"; \ 400 tr 50 M=INITIAL_L3_ECMP_GROUP; \ 401 tr 51 M=INITIAL_L3_ECMP_GROUP; \ 402 tr 52 M=INITIAL_L3_ECMP_GROUP; \ 403 tr 71 M=INITIAL_L3_ECMP_GROUP TSE=F SLTH=T; \ 404 tr 71 M=INITIAL_L3_ECMP_GROUP TSE=T SLTH=T; \ 405 tr 71 M=INITIAL_L3_ECMP_GROUP TSE=T SLTH=F; \ 406 echo " L3_ECMP"; \ 407 tr 50 M=L3_ECMP; \ 408 tr 51 M=L3_ECMP; \ 409 tr 52 M=L3_ECMP; \ 410 tr 71 M=L3_ECMP TSE=F SLTH=T; \ 411 tr 71 M=L3_ECMP TSE=T SLTH=T; \ 412 tr 71 M=L3_ECMP TSE=T SLTH=F;' 413 echo " FP_GLOBAL_MASK_TCAM"; 414 tr 50 M=FP_GLOBAL_MASK_TCAM; 415 tr 51 M=FP_GLOBAL_MASK_TCAM; 416 tr 52 M=FP_GLOBAL_MASK_TCAM; 417 if $?BCM5606X_A0 \ 418 'tr 71 M=FP_GLOBAL_MASK_TCAM TSE=F SLTH=T; \ 419 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=T; \ 420 tr 71 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=F;' \ 421 else 422 for s=0,1920,128 \ 423 'echo " Start = $s Count = 64"; \ 424 tr 71 Start=$s Count=64 M=FP_GLOBAL_MASK_TCAM TSE=F SLTH=T; \ 425 tr 71 Start=$s Count=64 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=T; \ 426 tr 71 Start=$s Count=64 M=FP_GLOBAL_MASK_TCAM TSE=T SLTH=F;' 427 echo " FP_TCAM"; 428 tr 50 M=FP_TCAM; 429 tr 51 M=FP_TCAM; 430 tr 52 M=FP_TCAM; 431 if $?BCM5606X_A0 \ 432 'tr 71 M=FP_TCAM TSE=F SLTH=T; \ 433 tr 71 M=FP_TCAM TSE=T SLTH=T; \ 434 tr 71 M=FP_TCAM TSE=T SLTH=F;' \ 435 else 436 for s=0,1920,128 \ 437 'echo " Start = $s Count = 64"; \ 438 tr 71 Start=$s Count=64 M=FP_TCAM TSE=F SLTH=T; \ 439 tr 71 Start=$s Count=64 M=FP_TCAM TSE=T SLTH=T; \ 440 tr 71 Start=$s Count=64 M=FP_TCAM TSE=T SLTH=F;' 441 echo " EGR_1588_SA"; 442 tr 50 M=EGR_1588_SA; 443 tr 51 M=EGR_1588_SA; 444 tr 52 M=EGR_1588_SA; 445 tr 71 M=EGR_1588_SA TSE=F SLTH=T; 446 tr 71 M=EGR_1588_SA TSE=T SLTH=T; 447 tr 71 M=EGR_1588_SA TSE=T SLTH=F; 448 echo " EGR_DSCP_ECN_MAP"; 449 tr 50 M=EGR_DSCP_ECN_MAP; 450 tr 51 M=EGR_DSCP_ECN_MAP; 451 tr 52 M=EGR_DSCP_ECN_MAP; 452 tr 71 M=EGR_DSCP_ECN_MAP TSE=F SLTH=T; 453 tr 71 M=EGR_DSCP_ECN_MAP TSE=T SLTH=T; 454 tr 71 M=EGR_DSCP_ECN_MAP TSE=T SLTH=F; 455 echo " EGR_DSCP_TABLE"; 456 tr 50 M=EGR_DSCP_TABLE; 457 tr 51 M=EGR_DSCP_TABLE; 458 tr 52 M=EGR_DSCP_TABLE; 459 tr 71 M=EGR_DSCP_TABLE TSE=F SLTH=T; 460 tr 71 M=EGR_DSCP_TABLE TSE=T SLTH=T; 461 tr 71 M=EGR_DSCP_TABLE TSE=T SLTH=F; 462 echo " EGR_EDB_XMIT_CTRL"; 463 tr 50 M=EGR_EDB_XMIT_CTRL; 464 tr 51 M=EGR_EDB_XMIT_CTRL; 465 tr 52 M=EGR_EDB_XMIT_CTRL; 466 tr 71 M=EGR_EDB_XMIT_CTRL TSE=F SLTH=T; 467 tr 71 M=EGR_EDB_XMIT_CTRL TSE=T SLTH=T; 468 tr 71 M=EGR_EDB_XMIT_CTRL TSE=T SLTH=F; 469 echo " EGR_EM_MTP_INDEX"; 470 tr 50 M=EGR_EM_MTP_INDEX; 471 tr 51 M=EGR_EM_MTP_INDEX; 472 tr 52 M=EGR_EM_MTP_INDEX; 473 tr 71 M=EGR_EM_MTP_INDEX TSE=F SLTH=T; 474 tr 71 M=EGR_EM_MTP_INDEX TSE=T SLTH=T; 475 tr 71 M=EGR_EM_MTP_INDEX TSE=T SLTH=F; 476 echo " EGR_ENABLE"; 477 tr 50 M=EGR_ENABLE; 478 tr 51 M=EGR_ENABLE; 479 tr 52 M=EGR_ENABLE; 480 tr 71 M=EGR_ENABLE TSE=F SLTH=T; 481 tr 71 M=EGR_ENABLE TSE=T SLTH=T; 482 tr 71 M=EGR_ENABLE TSE=T SLTH=F; 483 echo " EGR_MIRROR_ENCAP_CONTROL"; 484 tr 50 M=EGR_MIRROR_ENCAP_CONTROL; 485 tr 51 M=EGR_MIRROR_ENCAP_CONTROL; 486 tr 52 M=EGR_MIRROR_ENCAP_CONTROL; 487 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=F SLTH=T; 488 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=T SLTH=T; 489 tr 71 M=EGR_MIRROR_ENCAP_CONTROL TSE=T SLTH=F; 490 echo " EGR_IM_MTP_INDEX"; 491 tr 50 M=EGR_IM_MTP_INDEX; 492 tr 51 M=EGR_IM_MTP_INDEX; 493 tr 52 M=EGR_IM_MTP_INDEX; 494 tr 71 M=EGR_IM_MTP_INDEX TSE=F SLTH=T; 495 tr 71 M=EGR_IM_MTP_INDEX TSE=T SLTH=T; 496 tr 71 M=EGR_IM_MTP_INDEX TSE=T SLTH=F; 497 if !$?BCM5342X_A0 \ 498 'echo " EGR_L3_INTF"; \ 499 tr 50 M=EGR_L3_INTF; \ 500 tr 51 M=EGR_L3_INTF; \ 501 tr 52 M=EGR_L3_INTF; \ 502 tr 71 M=EGR_L3_INTF TSE=F SLTH=T; \ 503 tr 71 M=EGR_L3_INTF TSE=T SLTH=T; \ 504 tr 71 M=EGR_L3_INTF TSE=T SLTH=F; \ 505 echo " EGR_L3_NEXT_HOP"; \ 506 tr 50 M=EGR_L3_NEXT_HOP; \ 507 tr 51 M=EGR_L3_NEXT_HOP; \ 508 tr 52 M=EGR_L3_NEXT_HOP; \ 509 tr 71 M=EGR_L3_NEXT_HOP TSE=F SLTH=T; \ 510 tr 71 M=EGR_L3_NEXT_HOP TSE=T SLTH=T; \ 511 tr 71 M=EGR_L3_NEXT_HOP TSE=T SLTH=F;' 512 echo " EGR_MASK"; 513 tr 50 M=EGR_MASK; 514 tr 51 M=EGR_MASK; 515 tr 52 M=EGR_MASK; 516 tr 71 M=EGR_MASK TSE=F SLTH=T; 517 tr 71 M=EGR_MASK TSE=T SLTH=T; 518 tr 71 M=EGR_MASK TSE=T SLTH=F; 519 #echo " EGR_MAX_USED_ENTRIES"; 520 #tr 50 M=EGR_MAX_USED_ENTRIES; 521 #tr 51 M=EGR_MAX_USED_ENTRIES; 522 #tr 52 M=EGR_MAX_USED_ENTRIES; 523 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=F SLTH=T; 524 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=T SLTH=T; 525 #tr 71 M=EGR_MAX_USED_ENTRIES TSE=T SLTH=F; 526 #echo " EGR_MMU_REQUESTS"; 527 #tr 50 M=EGR_MMU_REQUESTS; 528 #tr 51 M=EGR_MMU_REQUESTS; 529 #tr 52 M=EGR_MMU_REQUESTS; 530 #tr 71 M=EGR_MMU_REQUESTS TSE=F SLTH=T; 531 #tr 71 M=EGR_MMU_REQUESTS TSE=T SLTH=T; 532 #tr 71 M=EGR_MMU_REQUESTS TSE=T SLTH=F; 533 echo " EGR_MOD_MAP_TABLE"; 534 tr 50 M=EGR_MOD_MAP_TABLE; 535 tr 51 M=EGR_MOD_MAP_TABLE; 536 tr 52 M=EGR_MOD_MAP_TABLE; 537 tr 71 M=EGR_MOD_MAP_TABLE TSE=F SLTH=T; 538 tr 71 M=EGR_MOD_MAP_TABLE TSE=T SLTH=T; 539 tr 71 M=EGR_MOD_MAP_TABLE TSE=T SLTH=F; 540 echo " EGR_MPLS_PRI_MAPPING"; 541 tr 50 M=EGR_MPLS_PRI_MAPPING; 542 tr 51 M=EGR_MPLS_PRI_MAPPING; 543 tr 52 M=EGR_MPLS_PRI_MAPPING; 544 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=F SLTH=T; 545 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=T SLTH=T; 546 tr 71 M=EGR_MPLS_PRI_MAPPING TSE=T SLTH=F; 547 echo " EGR_OAM_MAC_ADDRESS"; 548 tr 50 M=EGR_OAM_MAC_ADDRESS; 549 tr 51 M=EGR_OAM_MAC_ADDRESS; 550 tr 52 M=EGR_OAM_MAC_ADDRESS; 551 tr 71 M=EGR_OAM_MAC_ADDRESS TSE=F SLTH=T; 552 tr 71 M=EGR_OAM_MAC_ADDRESS TSE=T SLTH=T; 553 tr 71 M=EGR_OAM_MAC_ADDRESS TSE=T SLTH=F; 554 echo " EGR_PERQ_XMT_COUNTERS"; 555 tr 50 M=EGR_PERQ_XMT_COUNTERS; 556 tr 51 M=EGR_PERQ_XMT_COUNTERS; 557 tr 52 M=EGR_PERQ_XMT_COUNTERS; 558 tr 71 M=EGR_PERQ_XMT_COUNTERS TSE=F SLTH=T; 559 tr 71 M=EGR_PERQ_XMT_COUNTERS TSE=T SLTH=T; 560 tr 71 M=EGR_PERQ_XMT_COUNTERS TSE=T SLTH=F; 561 echo " EGR_PORT_CREDIT_RESET"; 562 tr 50 M=EGR_PORT_CREDIT_RESET; 563 tr 51 M=EGR_PORT_CREDIT_RESET; 564 tr 52 M=EGR_PORT_CREDIT_RESET; 565 tr 71 M=EGR_PORT_CREDIT_RESET TSE=F SLTH=T; 566 tr 71 M=EGR_PORT_CREDIT_RESET TSE=T SLTH=T; 567 tr 71 M=EGR_PORT_CREDIT_RESET TSE=T SLTH=F; 568 #echo " EGR_PORT_REQUESTS"; 569 #tr 50 M=EGR_PORT_REQUESTS; 570 #tr 51 M=EGR_PORT_REQUESTS; 571 #tr 52 M=EGR_PORT_REQUESTS; 572 #tr 71 M=EGR_PORT_REQUESTS TSE=F SLTH=T; 573 #tr 71 M=EGR_PORT_REQUESTS TSE=T SLTH=T; 574 #tr 71 M=EGR_PORT_REQUESTS TSE=T SLTH=F; 575 echo " EGR_PRI_CNG_MAP"; 576 tr 50 M=EGR_PRI_CNG_MAP; 577 tr 51 M=EGR_PRI_CNG_MAP; 578 tr 52 M=EGR_PRI_CNG_MAP; 579 tr 71 M=EGR_PRI_CNG_MAP TSE=F SLTH=T; 580 tr 71 M=EGR_PRI_CNG_MAP TSE=T SLTH=T; 581 tr 71 M=EGR_PRI_CNG_MAP TSE=T SLTH=F; 582 echo " EGR_VLAN"; 583 tr 50 M=EGR_VLAN; 584 tr 51 M=EGR_VLAN; 585 tr 52 M=EGR_VLAN; 586 tr 71 M=EGR_VLAN TSE=F SLTH=T; 587 tr 71 M=EGR_VLAN TSE=T SLTH=T; 588 tr 71 M=EGR_VLAN TSE=T SLTH=F; 589 echo " EGR_VLAN_STG"; 590 tr 50 M=EGR_VLAN_STG; 591 tr 51 M=EGR_VLAN_STG; 592 tr 52 M=EGR_VLAN_STG; 593 tr 71 M=EGR_VLAN_STG TSE=F SLTH=T; 594 tr 71 M=EGR_VLAN_STG TSE=T SLTH=T; 595 tr 71 M=EGR_VLAN_STG TSE=T SLTH=F; 596 echo " EGR_VLAN_TAG_ACTION_PROFILE"; 597 tr 50 M=EGR_VLAN_TAG_ACTION_PROFILE; 598 tr 51 M=EGR_VLAN_TAG_ACTION_PROFILE; 599 tr 52 M=EGR_VLAN_TAG_ACTION_PROFILE; 600 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=F SLTH=T; 601 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=T; 602 tr 71 M=EGR_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=F; 603 echo " EGR_VLAN_XLATE"; 604 tr 50 M=EGR_VLAN_XLATE; 605 tr 51 M=EGR_VLAN_XLATE; 606 tr 52 M=EGR_VLAN_XLATE; 607 tr 71 M=EGR_VLAN_XLATE TSE=F SLTH=T; 608 tr 71 M=EGR_VLAN_XLATE TSE=T SLTH=T; 609 tr 71 M=EGR_VLAN_XLATE TSE=T SLTH=F; 610 echo " EM_MTP_INDEX"; 611 tr 50 M=EM_MTP_INDEX; 612 tr 51 M=EM_MTP_INDEX; 613 tr 52 M=EM_MTP_INDEX; 614 tr 71 M=EM_MTP_INDEX TSE=F SLTH=T; 615 tr 71 M=EM_MTP_INDEX TSE=T SLTH=T; 616 tr 71 M=EM_MTP_INDEX TSE=T SLTH=F; 617 echo " FP_COUNTER_TABLE"; 618 tr 50 M=FP_COUNTER_TABLE; 619 tr 51 M=FP_COUNTER_TABLE; 620 tr 52 M=FP_COUNTER_TABLE; 621 tr 71 M=FP_COUNTER_TABLE TSE=F SLTH=T; 622 tr 71 M=FP_COUNTER_TABLE TSE=T SLTH=T; 623 tr 71 M=FP_COUNTER_TABLE TSE=T SLTH=F; 624 echo " FP_METER_TABLE"; 625 tr 50 M=FP_METER_TABLE; 626 tr 51 M=FP_METER_TABLE; 627 tr 52 M=FP_METER_TABLE; 628 tr 71 M=FP_METER_TABLE TSE=F SLTH=T; 629 tr 71 M=FP_METER_TABLE TSE=T SLTH=T; 630 tr 71 M=FP_METER_TABLE TSE=T SLTH=F; 631 echo " FP_POLICY_TABLE"; 632 tr 50 M=FP_POLICY_TABLE; 633 tr 51 M=FP_POLICY_TABLE; 634 tr 52 M=FP_POLICY_TABLE; 635 tr 71 M=FP_POLICY_TABLE TSE=F SLTH=T; 636 tr 71 M=FP_POLICY_TABLE TSE=T SLTH=T; 637 tr 71 M=FP_POLICY_TABLE TSE=T SLTH=F; 638 echo " FP_PORT_FIELD_SEL"; 639 tr 50 M=FP_PORT_FIELD_SEL; 640 tr 51 M=FP_PORT_FIELD_SEL; 641 tr 52 M=FP_PORT_FIELD_SEL; 642 tr 71 M=FP_PORT_FIELD_SEL TSE=F SLTH=T; 643 tr 71 M=FP_PORT_FIELD_SEL TSE=T SLTH=T; 644 tr 71 M=FP_PORT_FIELD_SEL TSE=T SLTH=F; 645 echo " FP_PORT_METER_MAP"; 646 tr 50 M=FP_PORT_METER_MAP; 647 tr 51 M=FP_PORT_METER_MAP; 648 tr 52 M=FP_PORT_METER_MAP; 649 tr 71 M=FP_PORT_METER_MAP TSE=F SLTH=T; 650 tr 71 M=FP_PORT_METER_MAP TSE=T SLTH=T; 651 tr 71 M=FP_PORT_METER_MAP TSE=T SLTH=F; 652 echo " FP_RANGE_CHECK"; 653 tr 50 M=FP_RANGE_CHECK; 654 tr 51 M=FP_RANGE_CHECK; 655 tr 52 M=FP_RANGE_CHECK; 656 tr 71 M=FP_RANGE_CHECK TSE=F SLTH=T; 657 tr 71 M=FP_RANGE_CHECK TSE=T SLTH=T; 658 tr 71 M=FP_RANGE_CHECK TSE=T SLTH=F; 659 echo " FP_SLICE_KEY_CONTROL"; 660 tr 50 M=FP_SLICE_KEY_CONTROL; 661 #tr 51 M=FP_SLICE_KEY_CONTROL; 662 #tr 52 M=FP_SLICE_KEY_CONTROL; 663 tr 71 M=FP_SLICE_KEY_CONTROL TSE=F SLTH=T; 664 tr 71 M=FP_SLICE_KEY_CONTROL TSE=T SLTH=T; 665 tr 71 M=FP_SLICE_KEY_CONTROL TSE=T SLTH=F; 666 echo " FP_SLICE_MAP"; 667 tr 50 M=FP_SLICE_MAP; 668 #tr 51 M=FP_SLICE_MAP; 669 #tr 52 M=FP_SLICE_MAP; 670 tr 71 M=FP_SLICE_MAP TSE=F SLTH=T; 671 tr 71 M=FP_SLICE_MAP TSE=T SLTH=T; 672 tr 71 M=FP_SLICE_MAP TSE=T SLTH=F; 673 echo " FP_STORM_CONTROL_METERS"; 674 tr 50 M=FP_STORM_CONTROL_METERS; 675 tr 51 M=FP_STORM_CONTROL_METERS; 676 tr 52 M=FP_STORM_CONTROL_METERS; 677 tr 71 M=FP_STORM_CONTROL_METERS TSE=F SLTH=T; 678 tr 71 M=FP_STORM_CONTROL_METERS TSE=T SLTH=T; 679 tr 71 M=FP_STORM_CONTROL_METERS TSE=T SLTH=F; 680 echo " FP_UDF_OFFSET"; 681 tr 50 M=FP_UDF_OFFSET; 682 tr 51 M=FP_UDF_OFFSET; 683 tr 52 M=FP_UDF_OFFSET; 684 tr 71 M=FP_UDF_OFFSET TSE=F SLTH=T; 685 tr 71 M=FP_UDF_OFFSET TSE=T SLTH=T; 686 tr 71 M=FP_UDF_OFFSET TSE=T SLTH=F; 687 echo " HG_TRUNK_FAILOVER_SET"; 688 tr 50 M=HG_TRUNK_FAILOVER_SET; 689 tr 51 M=HG_TRUNK_FAILOVER_SET; 690 tr 52 M=HG_TRUNK_FAILOVER_SET; 691 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=F SLTH=T; 692 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=T SLTH=T; 693 tr 71 M=HG_TRUNK_FAILOVER_SET TSE=T SLTH=F; 694 echo " IARB_TDM_TABLE"; 695 tr 50 M=IARB_TDM_TABLE; 696 tr 51 M=IARB_TDM_TABLE; 697 tr 52 M=IARB_TDM_TABLE; 698 tr 71 M=IARB_TDM_TABLE TSE=F SLTH=T; 699 tr 71 M=IARB_TDM_TABLE TSE=T SLTH=T; 700 tr 71 M=IARB_TDM_TABLE TSE=T SLTH=F; 701 #echo " IFP_PORT_FIELD_SEL"; 702 #HWALIAS to FP_PORT_FIELD_SEL -- NOTEST 703 #tr 50 M=IFP_PORT_FIELD_SEL; 704 #tr 51 M=IFP_PORT_FIELD_SEL; 705 #tr 52 M=IFP_PORT_FIELD_SEL; 706 #tr 71 M=IFP_PORT_FIELD_SEL TSE=F SLTH=T; 707 #tr 71 M=IFP_PORT_FIELD_SEL TSE=T SLTH=T; 708 #tr 71 M=IFP_PORT_FIELD_SEL TSE=T SLTH=F; 709 echo " IFP_REDIRECTION_PROFILE"; 710 tr 50 M=IFP_REDIRECTION_PROFILE; 711 tr 51 M=IFP_REDIRECTION_PROFILE; 712 tr 52 M=IFP_REDIRECTION_PROFILE; 713 tr 71 M=IFP_REDIRECTION_PROFILE TSE=F SLTH=T; 714 tr 71 M=IFP_REDIRECTION_PROFILE TSE=T SLTH=T; 715 tr 71 M=IFP_REDIRECTION_PROFILE TSE=T SLTH=F; 716 echo " IM_MTP_INDEX"; 717 tr 50 M=IM_MTP_INDEX; 718 tr 51 M=IM_MTP_INDEX; 719 tr 52 M=IM_MTP_INDEX; 720 tr 71 M=IM_MTP_INDEX TSE=F SLTH=T; 721 tr 71 M=IM_MTP_INDEX TSE=T SLTH=T; 722 tr 71 M=IM_MTP_INDEX TSE=T SLTH=F; 723 echo " ING_1588_INGRESS_CTRL"; 724 tr 50 M=ING_1588_INGRESS_CTRL; 725 tr 51 M=ING_1588_INGRESS_CTRL; 726 tr 52 M=ING_1588_INGRESS_CTRL; 727 tr 71 M=ING_1588_INGRESS_CTRL TSE=F SLTH=T; 728 tr 71 M=ING_1588_INGRESS_CTRL TSE=T SLTH=T; 729 tr 71 M=ING_1588_INGRESS_CTRL TSE=T SLTH=F; 730 echo " ING_IPV6_MC_RESERVED_ADDRESS"; 731 tr 50 M=ING_IPV6_MC_RESERVED_ADDRESS; 732 #tr 51 M=ING_IPV6_MC_RESERVED_ADDRESS; 733 #tr 52 M=ING_IPV6_MC_RESERVED_ADDRESS; 734 tr 71 M=ING_IPV6_MC_RESERVED_ADDRESS TSE=F SLTH=T; 735 tr 71 M=ING_IPV6_MC_RESERVED_ADDRESS TSE=T SLTH=T; 736 tr 71 M=ING_IPV6_MC_RESERVED_ADDRESS TSE=T SLTH=F; 737 if !$?BCM5342X_A0 \ 738 'echo " ING_L3_NEXT_HOP"; \ 739 tr 50 M=ING_L3_NEXT_HOP; \ 740 tr 51 M=ING_L3_NEXT_HOP; \ 741 tr 52 M=ING_L3_NEXT_HOP; \ 742 tr 71 M=ING_L3_NEXT_HOP TSE=F SLTH=T; \ 743 tr 71 M=ING_L3_NEXT_HOP TSE=T SLTH=T; \ 744 tr 71 M=ING_L3_NEXT_HOP TSE=T SLTH=F;' 745 echo " ING_MOD_MAP_TABLE"; 746 tr 50 M=ING_MOD_MAP_TABLE; 747 tr 51 M=ING_MOD_MAP_TABLE; 748 tr 52 M=ING_MOD_MAP_TABLE; 749 tr 71 M=ING_MOD_MAP_TABLE TSE=F SLTH=T; 750 tr 71 M=ING_MOD_MAP_TABLE TSE=T SLTH=T; 751 tr 71 M=ING_MOD_MAP_TABLE TSE=T SLTH=F; 752 echo " ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE"; 753 tr 50 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE; 754 tr 51 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE; 755 tr 52 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE; 756 tr 71 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE TSE=F SLTH=T; 757 tr 71 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE TSE=T SLTH=T; 758 tr 71 M=ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE TSE=T SLTH=F; 759 echo " ING_PRI_CNG_MAP"; 760 tr 50 M=ING_PRI_CNG_MAP; 761 tr 51 M=ING_PRI_CNG_MAP; 762 tr 52 M=ING_PRI_CNG_MAP; 763 tr 71 M=ING_PRI_CNG_MAP TSE=F SLTH=T; 764 tr 71 M=ING_PRI_CNG_MAP TSE=T SLTH=T; 765 tr 71 M=ING_PRI_CNG_MAP TSE=T SLTH=F; 766 echo " ING_SERVICE_PRI_MAP"; 767 tr 50 M=ING_SERVICE_PRI_MAP; 768 tr 51 M=ING_SERVICE_PRI_MAP; 769 tr 52 M=ING_SERVICE_PRI_MAP; 770 tr 71 M=ING_SERVICE_PRI_MAP TSE=F SLTH=T; 771 tr 71 M=ING_SERVICE_PRI_MAP TSE=T SLTH=T; 772 tr 71 M=ING_SERVICE_PRI_MAP TSE=T SLTH=F; 773 echo " ING_VLAN_RANGE"; 774 tr 50 M=ING_VLAN_RANGE; 775 tr 51 M=ING_VLAN_RANGE; 776 tr 52 M=ING_VLAN_RANGE; 777 tr 71 M=ING_VLAN_RANGE TSE=F SLTH=T; 778 tr 71 M=ING_VLAN_RANGE TSE=T SLTH=T; 779 tr 71 M=ING_VLAN_RANGE TSE=T SLTH=F; 780 echo " ING_VLAN_TAG_ACTION_PROFILE"; 781 tr 50 M=ING_VLAN_TAG_ACTION_PROFILE; 782 tr 51 M=ING_VLAN_TAG_ACTION_PROFILE; 783 tr 52 M=ING_VLAN_TAG_ACTION_PROFILE; 784 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=F SLTH=T; 785 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=T; 786 tr 71 M=ING_VLAN_TAG_ACTION_PROFILE TSE=T SLTH=F; 787 if !$?BCM5342X_A0 \ 788 'echo " INITIAL_ING_L3_NEXT_HOP"; \ 789 tr 50 M=INITIAL_ING_L3_NEXT_HOP; \ 790 tr 51 M=INITIAL_ING_L3_NEXT_HOP; \ 791 tr 52 M=INITIAL_ING_L3_NEXT_HOP; \ 792 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=F SLTH=T; \ 793 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=T SLTH=T; \ 794 tr 71 M=INITIAL_ING_L3_NEXT_HOP TSE=T SLTH=F;' 795 echo " IPORT_TABLE"; 796 tr 50 M=IPORT_TABLE; 797 tr 51 M=IPORT_TABLE; 798 tr 52 M=IPORT_TABLE; 799 tr 71 M=IPORT_TABLE TSE=F SLTH=T; 800 tr 71 M=IPORT_TABLE TSE=T SLTH=T; 801 tr 71 M=IPORT_TABLE TSE=T SLTH=F; 802 echo " IPV4_IN_IPV6_PREFIX_MATCH_TABLE"; 803 tr 50 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE; 804 tr 51 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE; 805 tr 52 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE; 806 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=F SLTH=T; 807 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=T SLTH=T; 808 tr 71 M=IPV4_IN_IPV6_PREFIX_MATCH_TABLE TSE=T SLTH=F; 809 echo " IPV6_PROXY_ENABLE_TABLE"; 810 tr 50 M=IPV6_PROXY_ENABLE_TABLE; 811 tr 51 M=IPV6_PROXY_ENABLE_TABLE; 812 tr 52 M=IPV6_PROXY_ENABLE_TABLE; 813 tr 71 M=IPV6_PROXY_ENABLE_TABLE TSE=F SLTH=T; 814 tr 71 M=IPV6_PROXY_ENABLE_TABLE TSE=T SLTH=T; 815 tr 71 M=IPV6_PROXY_ENABLE_TABLE TSE=T SLTH=F; 816 echo " L2MC"; 817 tr 50 M=L2MC; 818 tr 51 M=L2MC; 819 tr 52 M=L2MC; 820 tr 71 M=L2MC TSE=F SLTH=T; 821 tr 71 M=L2MC TSE=T SLTH=T; 822 tr 71 M=L2MC TSE=T SLTH=F; 823 echo " L2X"; 824 tr 50 M=L2X; 825 tr 51 M=L2X; 826 tr 52 M=L2X; 827 tr 71 M=L2X TSE=F SLTH=T; 828 tr 71 M=L2X TSE=T SLTH=T; 829 tr 71 M=L2X TSE=T SLTH=F; 830 echo " L2_ENTRY_ONLY"; 831 tr 50 M=L2_ENTRY_ONLY; 832 tr 51 M=L2_ENTRY_ONLY; 833 tr 52 M=L2_ENTRY_ONLY; 834 tr 71 M=L2_ENTRY_ONLY TSE=F SLTH=T; 835 tr 71 M=L2_ENTRY_ONLY TSE=T SLTH=T; 836 tr 71 M=L2_ENTRY_ONLY TSE=T SLTH=F; 837 echo " L2_ENTRY_OVERFLOW"; 838 tr 50 M=L2_ENTRY_OVERFLOW; 839 #tr 51 M=L2_ENTRY_OVERFLOW; 840 #tr 52 M=L2_ENTRY_OVERFLOW; 841 tr 71 M=L2_ENTRY_OVERFLOW TSE=F SLTH=T; 842 tr 71 M=L2_ENTRY_OVERFLOW TSE=T SLTH=T; 843 tr 71 M=L2_ENTRY_OVERFLOW TSE=T SLTH=F; 844 echo " L2_HITDA_ONLY"; 845 tr 50 M=L2_HITDA_ONLY; 846 tr 51 M=L2_HITDA_ONLY; 847 tr 52 M=L2_HITDA_ONLY; 848 tr 71 M=L2_HITDA_ONLY TSE=F SLTH=T; 849 tr 71 M=L2_HITDA_ONLY TSE=T SLTH=T; 850 tr 71 M=L2_HITDA_ONLY TSE=T SLTH=F; 851 echo " L2_HITSA_ONLY"; 852 tr 50 M=L2_HITSA_ONLY; 853 tr 51 M=L2_HITSA_ONLY; 854 tr 52 M=L2_HITSA_ONLY; 855 tr 71 M=L2_HITSA_ONLY TSE=F SLTH=T; 856 tr 71 M=L2_HITSA_ONLY TSE=T SLTH=T; 857 tr 71 M=L2_HITSA_ONLY TSE=T SLTH=F; 858 echo " L2_MOD_FIFO"; 859 tr 50 M=L2_MOD_FIFO; 860 tr 51 M=L2_MOD_FIFO; 861 tr 52 M=L2_MOD_FIFO; 862 tr 71 M=L2_MOD_FIFO TSE=F SLTH=T; 863 tr 71 M=L2_MOD_FIFO TSE=T SLTH=T; 864 tr 71 M=L2_MOD_FIFO TSE=T SLTH=F; 865 echo " L2_USER_ENTRY"; 866 tr 50 M=L2_USER_ENTRY; 867 tr 51 M=L2_USER_ENTRY; 868 tr 52 M=L2_USER_ENTRY; 869 tr 71 M=L2_USER_ENTRY TSE=F SLTH=T; 870 tr 71 M=L2_USER_ENTRY TSE=T SLTH=T; 871 tr 71 M=L2_USER_ENTRY TSE=T SLTH=F; 872 echo " L2_USER_ENTRY_DATA_ONLY"; 873 tr 50 M=L2_USER_ENTRY_DATA_ONLY; 874 tr 51 M=L2_USER_ENTRY_DATA_ONLY; 875 tr 52 M=L2_USER_ENTRY_DATA_ONLY; 876 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=F SLTH=T; 877 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=T SLTH=T; 878 tr 71 M=L2_USER_ENTRY_DATA_ONLY TSE=T SLTH=F; 879 echo " L2_USER_ENTRY_ONLY"; 880 tr 50 M=L2_USER_ENTRY_ONLY; 881 tr 51 M=L2_USER_ENTRY_ONLY; 882 tr 52 M=L2_USER_ENTRY_ONLY; 883 tr 71 M=L2_USER_ENTRY_ONLY TSE=F SLTH=T; 884 tr 71 M=L2_USER_ENTRY_ONLY TSE=T SLTH=T; 885 tr 71 M=L2_USER_ENTRY_ONLY TSE=T SLTH=F; 886 if !$?BCM5342X_A0 \ 887 'echo " L3_DEFIP"; \ 888 tr 50 M=L3_DEFIP; \ 889 tr 51 M=L3_DEFIP; \ 890 tr 52 M=L3_DEFIP; \ 891 tr 71 M=L3_DEFIP TSE=F SLTH=T; \ 892 tr 71 M=L3_DEFIP TSE=T SLTH=T; \ 893 tr 71 M=L3_DEFIP TSE=T SLTH=F; \ 894 echo " L3_DEFIP_DATA_ONLY"; \ 895 tr 50 M=L3_DEFIP_DATA_ONLY; \ 896 tr 51 M=L3_DEFIP_DATA_ONLY; \ 897 tr 52 M=L3_DEFIP_DATA_ONLY; \ 898 tr 71 M=L3_DEFIP_DATA_ONLY TSE=F SLTH=T; \ 899 tr 71 M=L3_DEFIP_DATA_ONLY TSE=T SLTH=T; \ 900 tr 71 M=L3_DEFIP_DATA_ONLY TSE=T SLTH=F; \ 901 echo " L3_DEFIP_HIT_ONLY"; \ 902 tr 50 M=L3_DEFIP_HIT_ONLY; \ 903 tr 51 M=L3_DEFIP_HIT_ONLY; \ 904 tr 52 M=L3_DEFIP_HIT_ONLY; \ 905 tr 71 M=L3_DEFIP_HIT_ONLY TSE=F SLTH=T; \ 906 tr 71 M=L3_DEFIP_HIT_ONLY TSE=T SLTH=T; \ 907 tr 71 M=L3_DEFIP_HIT_ONLY TSE=T SLTH=F; \ 908 echo " L3_DEFIP_ONLY"; \ 909 tr 50 M=L3_DEFIP_ONLY; \ 910 tr 51 M=L3_DEFIP_ONLY; \ 911 tr 52 M=L3_DEFIP_ONLY; \ 912 tr 71 M=L3_DEFIP_ONLY TSE=F SLTH=T; \ 913 tr 71 M=L3_DEFIP_ONLY TSE=T SLTH=T; \ 914 tr 71 M=L3_DEFIP_ONLY TSE=T SLTH=F; \ 915 echo " L3_ENTRY_HIT_ONLY"; \ 916 tr 50 M=L3_ENTRY_HIT_ONLY; \ 917 tr 51 M=L3_ENTRY_HIT_ONLY; \ 918 tr 52 M=L3_ENTRY_HIT_ONLY; \ 919 tr 71 M=L3_ENTRY_HIT_ONLY TSE=F SLTH=T; \ 920 tr 71 M=L3_ENTRY_HIT_ONLY TSE=T SLTH=T; \ 921 tr 71 M=L3_ENTRY_HIT_ONLY TSE=T SLTH=F; \ 922 echo " L3_ENTRY_IPV4_MULTICAST"; \ 923 tr 50 M=L3_ENTRY_IPV4_MULTICAST; \ 924 tr 51 M=L3_ENTRY_IPV4_MULTICAST; \ 925 tr 52 M=L3_ENTRY_IPV4_MULTICAST; \ 926 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=F SLTH=T; \ 927 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=T SLTH=T; \ 928 tr 71 M=L3_ENTRY_IPV4_MULTICAST TSE=T SLTH=F; \ 929 echo " L3_ENTRY_IPV4_UNICAST"; \ 930 tr 50 M=L3_ENTRY_IPV4_UNICAST; \ 931 tr 51 M=L3_ENTRY_IPV4_UNICAST; \ 932 tr 52 M=L3_ENTRY_IPV4_UNICAST; \ 933 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=F SLTH=T; \ 934 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=T SLTH=T; \ 935 tr 71 M=L3_ENTRY_IPV4_UNICAST TSE=T SLTH=F; \ 936 echo " L3_ENTRY_IPV6_MULTICAST"; \ 937 tr 50 M=L3_ENTRY_IPV6_MULTICAST; \ 938 tr 51 M=L3_ENTRY_IPV6_MULTICAST; \ 939 tr 52 M=L3_ENTRY_IPV6_MULTICAST; \ 940 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=F SLTH=T; \ 941 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=T SLTH=T; \ 942 tr 71 M=L3_ENTRY_IPV6_MULTICAST TSE=T SLTH=F; \ 943 echo " L3_ENTRY_IPV6_UNICAST"; \ 944 tr 50 M=L3_ENTRY_IPV6_UNICAST; \ 945 tr 51 M=L3_ENTRY_IPV6_UNICAST; \ 946 tr 52 M=L3_ENTRY_IPV6_UNICAST; \ 947 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=F SLTH=T; \ 948 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=T SLTH=T; \ 949 tr 71 M=L3_ENTRY_IPV6_UNICAST TSE=T SLTH=F; \ 950 echo " L3_ENTRY_ONLY"; \ 951 tr 50 M=L3_ENTRY_ONLY; \ 952 tr 51 M=L3_ENTRY_ONLY; \ 953 tr 52 M=L3_ENTRY_ONLY; \ 954 tr 71 M=L3_ENTRY_ONLY TSE=F SLTH=T; \ 955 tr 71 M=L3_ENTRY_ONLY TSE=T SLTH=T; \ 956 tr 71 M=L3_ENTRY_ONLY TSE=T SLTH=F; \ 957 echo " L3_ENTRY_VALID_ONLY"; \ 958 tr 50 M=L3_ENTRY_VALID_ONLY; \ 959 tr 51 M=L3_ENTRY_VALID_ONLY; \ 960 tr 52 M=L3_ENTRY_VALID_ONLY; \ 961 tr 71 M=L3_ENTRY_VALID_ONLY TSE=F SLTH=T; \ 962 tr 71 M=L3_ENTRY_VALID_ONLY TSE=T SLTH=T; \ 963 tr 71 M=L3_ENTRY_VALID_ONLY TSE=T SLTH=F; \ 964 echo " L3_IPMC"; \ 965 tr 50 M=L3_IPMC; \ 966 tr 51 M=L3_IPMC; \ 967 tr 52 M=L3_IPMC; \ 968 tr 71 M=L3_IPMC TSE=F SLTH=T; \ 969 tr 71 M=L3_IPMC TSE=T SLTH=T; \ 970 tr 71 M=L3_IPMC TSE=T SLTH=F; \ 971 echo " L3_MTU_VALUES"; \ 972 tr 50 M=L3_MTU_VALUES; \ 973 tr 51 M=L3_MTU_VALUES; \ 974 tr 52 M=L3_MTU_VALUES; \ 975 tr 71 M=L3_MTU_VALUES TSE=F SLTH=T; \ 976 tr 71 M=L3_MTU_VALUES TSE=T SLTH=T; \ 977 tr 71 M=L3_MTU_VALUES TSE=T SLTH=F;' 978 echo " LMEP"; 979 tr 50 M=LMEP; 980 tr 51 M=LMEP; 981 tr 52 M=LMEP; 982 tr 71 M=LMEP TSE=F SLTH=T; 983 tr 71 M=LMEP TSE=T SLTH=T; 984 tr 71 M=LMEP TSE=T SLTH=F; 985 echo " LMEP_DA"; 986 tr 50 M=LMEP_DA; 987 tr 51 M=LMEP_DA; 988 tr 52 M=LMEP_DA; 989 tr 71 M=LMEP_DA TSE=F SLTH=T; 990 tr 71 M=LMEP_DA TSE=T SLTH=T; 991 tr 71 M=LMEP_DA TSE=T SLTH=F; 992 echo " LPORT_TAB"; 993 tr 50 M=LPORT_TAB; 994 tr 51 M=LPORT_TAB; 995 tr 52 M=LPORT_TAB; 996 tr 71 M=LPORT_TAB TSE=F SLTH=T; 997 tr 71 M=LPORT_TAB TSE=T SLTH=T; 998 tr 71 M=LPORT_TAB TSE=T SLTH=F; 999 echo " MAC_BLOCK"; 1000 tr 50 M=MAC_BLOCK; 1001 tr 51 M=MAC_BLOCK; 1002 tr 52 M=MAC_BLOCK; 1003 tr 71 M=MAC_BLOCK TSE=F SLTH=T; 1004 tr 71 M=MAC_BLOCK TSE=T SLTH=T; 1005 tr 71 M=MAC_BLOCK TSE=T SLTH=F; 1006 echo " MAID_REDUCTION"; 1007 tr 50 M=MAID_REDUCTION; 1008 tr 51 M=MAID_REDUCTION; 1009 tr 52 M=MAID_REDUCTION; 1010 tr 71 M=MAID_REDUCTION TSE=F SLTH=T; 1011 tr 71 M=MAID_REDUCTION TSE=T SLTH=T; 1012 tr 71 M=MAID_REDUCTION TSE=T SLTH=F; 1013 echo " MA_INDEX"; 1014 tr 50 M=MA_INDEX; 1015 tr 51 M=MA_INDEX; 1016 tr 52 M=MA_INDEX; 1017 tr 71 M=MA_INDEX TSE=F SLTH=T; 1018 tr 71 M=MA_INDEX TSE=T SLTH=T; 1019 tr 71 M=MA_INDEX TSE=T SLTH=F; 1020 echo " MA_STATE"; 1021 tr 50 M=MA_STATE; 1022 tr 51 M=MA_STATE; 1023 tr 52 M=MA_STATE; 1024 tr 71 M=MA_STATE TSE=F SLTH=T; 1025 tr 71 M=MA_STATE TSE=T SLTH=T; 1026 tr 71 M=MA_STATE TSE=T SLTH=F; 1027 echo " MMU_AGING_CTR"; 1028 tr 50 M=MMU_AGING_CTR; 1029 tr 51 M=MMU_AGING_CTR; 1030 tr 52 M=MMU_AGING_CTR; 1031 tr 71 M=MMU_AGING_CTR TSE=F SLTH=T; 1032 tr 71 M=MMU_AGING_CTR TSE=T SLTH=T; 1033 tr 71 M=MMU_AGING_CTR TSE=T SLTH=F; 1034 echo " MMU_AGING_EXP"; 1035 tr 50 M=MMU_AGING_EXP; 1036 tr 51 M=MMU_AGING_EXP; 1037 tr 52 M=MMU_AGING_EXP; 1038 tr 71 M=MMU_AGING_EXP TSE=F SLTH=T; 1039 tr 71 M=MMU_AGING_EXP TSE=T SLTH=T; 1040 tr 71 M=MMU_AGING_EXP TSE=T SLTH=F; 1041 echo " MMU_ARB_TDM_TABLE"; 1042 tr 50 M=MMU_ARB_TDM_TABLE; 1043 tr 51 M=MMU_ARB_TDM_TABLE; 1044 tr 52 M=MMU_ARB_TDM_TABLE; 1045 tr 71 M=MMU_ARB_TDM_TABLE TSE=F SLTH=T; 1046 tr 71 M=MMU_ARB_TDM_TABLE TSE=T SLTH=T; 1047 tr 71 M=MMU_ARB_TDM_TABLE TSE=T SLTH=F; 1048 echo " MMU_CBPCellHeader"; 1049 tr 50 M=MMU_CBPCellHeader; 1050 tr 51 M=MMU_CBPCellHeader; 1051 tr 52 M=MMU_CBPCellHeader; 1052 tr 71 M=MMU_CBPCellHeader TSE=F SLTH=T; 1053 tr 71 M=MMU_CBPCellHeader TSE=T SLTH=T; 1054 tr 71 M=MMU_CBPCellHeader TSE=T SLTH=F; 1055 echo " MMU_CBPData0"; 1056 tr 50 M=MMU_CBPData0; 1057 tr 51 M=MMU_CBPData0; 1058 tr 52 M=MMU_CBPData0; 1059 tr 71 M=MMU_CBPData0 TSE=F SLTH=T; 1060 tr 71 M=MMU_CBPData0 TSE=T SLTH=T; 1061 tr 71 M=MMU_CBPData0 TSE=T SLTH=F; 1062 echo " MMU_CBPData1"; 1063 tr 50 M=MMU_CBPData1; 1064 tr 51 M=MMU_CBPData1; 1065 tr 52 M=MMU_CBPData1; 1066 tr 71 M=MMU_CBPData1 TSE=F SLTH=T; 1067 tr 71 M=MMU_CBPData1 TSE=T SLTH=T; 1068 tr 71 M=MMU_CBPData1 TSE=T SLTH=F; 1069 echo " MMU_CBPData2"; 1070 tr 50 M=MMU_CBPData2; 1071 tr 51 M=MMU_CBPData2; 1072 tr 52 M=MMU_CBPData2; 1073 tr 71 M=MMU_CBPData2 TSE=F SLTH=T; 1074 tr 71 M=MMU_CBPData2 TSE=T SLTH=T; 1075 tr 71 M=MMU_CBPData2 TSE=T SLTH=F; 1076 echo " MMU_CBPData3"; 1077 tr 50 M=MMU_CBPData3; 1078 tr 51 M=MMU_CBPData3; 1079 tr 52 M=MMU_CBPData3; 1080 tr 71 M=MMU_CBPData3 TSE=F SLTH=T; 1081 tr 71 M=MMU_CBPData3 TSE=T SLTH=T; 1082 tr 71 M=MMU_CBPData3 TSE=T SLTH=F; 1083 echo " MMU_CBPData4"; 1084 tr 50 M=MMU_CBPData4; 1085 tr 51 M=MMU_CBPData4; 1086 tr 52 M=MMU_CBPData4; 1087 tr 71 M=MMU_CBPData4 TSE=F SLTH=T; 1088 tr 71 M=MMU_CBPData4 TSE=T SLTH=T; 1089 tr 71 M=MMU_CBPData4 TSE=T SLTH=F; 1090 echo " MMU_CBPData5"; 1091 tr 50 M=MMU_CBPData5; 1092 tr 51 M=MMU_CBPData5; 1093 tr 52 M=MMU_CBPData5; 1094 tr 71 M=MMU_CBPData5 TSE=F SLTH=T; 1095 tr 71 M=MMU_CBPData5 TSE=T SLTH=T; 1096 tr 71 M=MMU_CBPData5 TSE=T SLTH=F; 1097 echo " MMU_CBPData6"; 1098 tr 50 M=MMU_CBPData6; 1099 tr 51 M=MMU_CBPData6; 1100 tr 52 M=MMU_CBPData6; 1101 tr 71 M=MMU_CBPData6 TSE=F SLTH=T; 1102 tr 71 M=MMU_CBPData6 TSE=T SLTH=T; 1103 tr 71 M=MMU_CBPData6 TSE=T SLTH=F; 1104 echo " MMU_CBPData7"; 1105 tr 50 M=MMU_CBPData7; 1106 tr 51 M=MMU_CBPData7; 1107 tr 52 M=MMU_CBPData7; 1108 tr 71 M=MMU_CBPData7 TSE=F SLTH=T; 1109 tr 71 M=MMU_CBPData7 TSE=T SLTH=T; 1110 tr 71 M=MMU_CBPData7 TSE=T SLTH=F; 1111 echo " MMU_CBPPktHeader0"; 1112 tr 50 M=MMU_CBPPktHeader0; 1113 tr 51 M=MMU_CBPPktHeader0; 1114 tr 52 M=MMU_CBPPktHeader0; 1115 tr 71 M=MMU_CBPPktHeader0 TSE=F SLTH=T; 1116 tr 71 M=MMU_CBPPktHeader0 TSE=T SLTH=T; 1117 tr 71 M=MMU_CBPPktHeader0 TSE=T SLTH=F; 1118 echo " MMU_CBPPktHeader1"; 1119 tr 50 M=MMU_CBPPktHeader1; 1120 tr 51 M=MMU_CBPPktHeader1; 1121 tr 52 M=MMU_CBPPktHeader1; 1122 tr 71 M=MMU_CBPPktHeader1 TSE=F SLTH=T; 1123 tr 71 M=MMU_CBPPktHeader1 TSE=T SLTH=T; 1124 tr 71 M=MMU_CBPPktHeader1 TSE=T SLTH=F; 1125 echo " MMU_CBPPktHeader2"; 1126 tr 50 M=MMU_CBPPktHeader2; 1127 tr 51 M=MMU_CBPPktHeader2; 1128 tr 52 M=MMU_CBPPktHeader2; 1129 tr 71 M=MMU_CBPPktHeader2 TSE=F SLTH=T; 1130 tr 71 M=MMU_CBPPktHeader2 TSE=T SLTH=T; 1131 tr 71 M=MMU_CBPPktHeader2 TSE=T SLTH=F; 1132 echo " MMU_CBPPktHeader_EXT"; 1133 tr 50 M=MMU_CBPPktHeader_EXT; 1134 tr 51 M=MMU_CBPPktHeader_EXT; 1135 tr 52 M=MMU_CBPPktHeader_EXT; 1136 tr 71 M=MMU_CBPPktHeader_EXT TSE=F SLTH=T; 1137 tr 71 M=MMU_CBPPktHeader_EXT TSE=T SLTH=T; 1138 tr 71 M=MMU_CBPPktHeader_EXT TSE=T SLTH=F; 1139 echo " MMU_CCP"; 1140 tr 50 M=MMU_CCP; 1141 tr 51 M=MMU_CCP; 1142 tr 52 M=MMU_CCP; 1143 tr 71 M=MMU_CCP TSE=F SLTH=T; 1144 tr 71 M=MMU_CCP TSE=T SLTH=T; 1145 tr 71 M=MMU_CCP TSE=T SLTH=F; 1146 echo " MMU_CFAP"; 1147 tr 50 M=MMU_CFAP; 1148 tr 51 M=MMU_CFAP; 1149 tr 52 M=MMU_CFAP; 1150 tr 71 M=MMU_CFAP TSE=F SLTH=T; 1151 tr 71 M=MMU_CFAP TSE=T SLTH=T; 1152 tr 71 M=MMU_CFAP TSE=T SLTH=F; 1153 echo " MMU_IPMC_GROUP_TBL10"; 1154 tr 50 M=MMU_IPMC_GROUP_TBL10; 1155 tr 51 M=MMU_IPMC_GROUP_TBL10; 1156 tr 52 M=MMU_IPMC_GROUP_TBL10; 1157 tr 71 M=MMU_IPMC_GROUP_TBL10 TSE=F SLTH=T; 1158 tr 71 M=MMU_IPMC_GROUP_TBL10 TSE=T SLTH=T; 1159 tr 71 M=MMU_IPMC_GROUP_TBL10 TSE=T SLTH=F; 1160 echo " MMU_IPMC_GROUP_TBL11"; 1161 tr 50 M=MMU_IPMC_GROUP_TBL11; 1162 tr 51 M=MMU_IPMC_GROUP_TBL11; 1163 tr 52 M=MMU_IPMC_GROUP_TBL11; 1164 tr 71 M=MMU_IPMC_GROUP_TBL11 TSE=F SLTH=T; 1165 tr 71 M=MMU_IPMC_GROUP_TBL11 TSE=T SLTH=T; 1166 tr 71 M=MMU_IPMC_GROUP_TBL11 TSE=T SLTH=F; 1167 echo " MMU_IPMC_GROUP_TBL12"; 1168 tr 50 M=MMU_IPMC_GROUP_TBL12; 1169 tr 51 M=MMU_IPMC_GROUP_TBL12; 1170 tr 52 M=MMU_IPMC_GROUP_TBL12; 1171 tr 71 M=MMU_IPMC_GROUP_TBL12 TSE=F SLTH=T; 1172 tr 71 M=MMU_IPMC_GROUP_TBL12 TSE=T SLTH=T; 1173 tr 71 M=MMU_IPMC_GROUP_TBL12 TSE=T SLTH=F; 1174 echo " MMU_IPMC_GROUP_TBL13"; 1175 tr 50 M=MMU_IPMC_GROUP_TBL13; 1176 tr 51 M=MMU_IPMC_GROUP_TBL13; 1177 tr 52 M=MMU_IPMC_GROUP_TBL13; 1178 tr 71 M=MMU_IPMC_GROUP_TBL13 TSE=F SLTH=T; 1179 tr 71 M=MMU_IPMC_GROUP_TBL13 TSE=T SLTH=T; 1180 tr 71 M=MMU_IPMC_GROUP_TBL13 TSE=T SLTH=F; 1181 echo " MMU_IPMC_GROUP_TBL14"; 1182 tr 50 M=MMU_IPMC_GROUP_TBL14; 1183 tr 51 M=MMU_IPMC_GROUP_TBL14; 1184 tr 52 M=MMU_IPMC_GROUP_TBL14; 1185 tr 71 M=MMU_IPMC_GROUP_TBL14 TSE=F SLTH=T; 1186 tr 71 M=MMU_IPMC_GROUP_TBL14 TSE=T SLTH=T; 1187 tr 71 M=MMU_IPMC_GROUP_TBL14 TSE=T SLTH=F; 1188 echo " MMU_IPMC_GROUP_TBL15"; 1189 tr 50 M=MMU_IPMC_GROUP_TBL15; 1190 tr 51 M=MMU_IPMC_GROUP_TBL15; 1191 tr 52 M=MMU_IPMC_GROUP_TBL15; 1192 tr 71 M=MMU_IPMC_GROUP_TBL15 TSE=F SLTH=T; 1193 tr 71 M=MMU_IPMC_GROUP_TBL15 TSE=T SLTH=T; 1194 tr 71 M=MMU_IPMC_GROUP_TBL15 TSE=T SLTH=F; 1195 echo " MMU_IPMC_GROUP_TBL16"; 1196 tr 50 M=MMU_IPMC_GROUP_TBL16; 1197 tr 51 M=MMU_IPMC_GROUP_TBL16; 1198 tr 52 M=MMU_IPMC_GROUP_TBL16; 1199 tr 71 M=MMU_IPMC_GROUP_TBL16 TSE=F SLTH=T; 1200 tr 71 M=MMU_IPMC_GROUP_TBL16 TSE=T SLTH=T; 1201 tr 71 M=MMU_IPMC_GROUP_TBL16 TSE=T SLTH=F; 1202 echo " MMU_IPMC_GROUP_TBL17"; 1203 tr 50 M=MMU_IPMC_GROUP_TBL17; 1204 tr 51 M=MMU_IPMC_GROUP_TBL17; 1205 tr 52 M=MMU_IPMC_GROUP_TBL17; 1206 tr 71 M=MMU_IPMC_GROUP_TBL17 TSE=F SLTH=T; 1207 tr 71 M=MMU_IPMC_GROUP_TBL17 TSE=T SLTH=T; 1208 tr 71 M=MMU_IPMC_GROUP_TBL17 TSE=T SLTH=F; 1209 echo " MMU_IPMC_GROUP_TBL18"; 1210 tr 50 M=MMU_IPMC_GROUP_TBL18; 1211 tr 51 M=MMU_IPMC_GROUP_TBL18; 1212 tr 52 M=MMU_IPMC_GROUP_TBL18; 1213 tr 71 M=MMU_IPMC_GROUP_TBL18 TSE=F SLTH=T; 1214 tr 71 M=MMU_IPMC_GROUP_TBL18 TSE=T SLTH=T; 1215 tr 71 M=MMU_IPMC_GROUP_TBL18 TSE=T SLTH=F; 1216 echo " MMU_IPMC_GROUP_TBL19"; 1217 tr 50 M=MMU_IPMC_GROUP_TBL19; 1218 tr 51 M=MMU_IPMC_GROUP_TBL19; 1219 tr 52 M=MMU_IPMC_GROUP_TBL19; 1220 tr 71 M=MMU_IPMC_GROUP_TBL19 TSE=F SLTH=T; 1221 tr 71 M=MMU_IPMC_GROUP_TBL19 TSE=T SLTH=T; 1222 tr 71 M=MMU_IPMC_GROUP_TBL19 TSE=T SLTH=F; 1223 echo " MMU_IPMC_GROUP_TBL2"; 1224 tr 50 M=MMU_IPMC_GROUP_TBL2; 1225 tr 51 M=MMU_IPMC_GROUP_TBL2; 1226 tr 52 M=MMU_IPMC_GROUP_TBL2; 1227 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=F SLTH=T; 1228 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=T SLTH=T; 1229 tr 71 M=MMU_IPMC_GROUP_TBL2 TSE=T SLTH=F; 1230 echo " MMU_IPMC_GROUP_TBL20"; 1231 tr 50 M=MMU_IPMC_GROUP_TBL20; 1232 tr 51 M=MMU_IPMC_GROUP_TBL20; 1233 tr 52 M=MMU_IPMC_GROUP_TBL20; 1234 tr 71 M=MMU_IPMC_GROUP_TBL20 TSE=F SLTH=T; 1235 tr 71 M=MMU_IPMC_GROUP_TBL20 TSE=T SLTH=T; 1236 tr 71 M=MMU_IPMC_GROUP_TBL20 TSE=T SLTH=F; 1237 echo " MMU_IPMC_GROUP_TBL21"; 1238 tr 50 M=MMU_IPMC_GROUP_TBL21; 1239 tr 51 M=MMU_IPMC_GROUP_TBL21; 1240 tr 52 M=MMU_IPMC_GROUP_TBL21; 1241 tr 71 M=MMU_IPMC_GROUP_TBL21 TSE=F SLTH=T; 1242 tr 71 M=MMU_IPMC_GROUP_TBL21 TSE=T SLTH=T; 1243 tr 71 M=MMU_IPMC_GROUP_TBL21 TSE=T SLTH=F; 1244 echo " MMU_IPMC_GROUP_TBL22"; 1245 tr 50 M=MMU_IPMC_GROUP_TBL22; 1246 tr 51 M=MMU_IPMC_GROUP_TBL22; 1247 tr 52 M=MMU_IPMC_GROUP_TBL22; 1248 tr 71 M=MMU_IPMC_GROUP_TBL22 TSE=F SLTH=T; 1249 tr 71 M=MMU_IPMC_GROUP_TBL22 TSE=T SLTH=T; 1250 tr 71 M=MMU_IPMC_GROUP_TBL22 TSE=T SLTH=F; 1251 echo " MMU_IPMC_GROUP_TBL23"; 1252 tr 50 M=MMU_IPMC_GROUP_TBL23; 1253 tr 51 M=MMU_IPMC_GROUP_TBL23; 1254 tr 52 M=MMU_IPMC_GROUP_TBL23; 1255 tr 71 M=MMU_IPMC_GROUP_TBL23 TSE=F SLTH=T; 1256 tr 71 M=MMU_IPMC_GROUP_TBL23 TSE=T SLTH=T; 1257 tr 71 M=MMU_IPMC_GROUP_TBL23 TSE=T SLTH=F; 1258 echo " MMU_IPMC_GROUP_TBL24"; 1259 tr 50 M=MMU_IPMC_GROUP_TBL24; 1260 tr 51 M=MMU_IPMC_GROUP_TBL24; 1261 tr 52 M=MMU_IPMC_GROUP_TBL24; 1262 tr 71 M=MMU_IPMC_GROUP_TBL24 TSE=F SLTH=T; 1263 tr 71 M=MMU_IPMC_GROUP_TBL24 TSE=T SLTH=T; 1264 tr 71 M=MMU_IPMC_GROUP_TBL24 TSE=T SLTH=F; 1265 echo " MMU_IPMC_GROUP_TBL25"; 1266 tr 50 M=MMU_IPMC_GROUP_TBL25; 1267 tr 51 M=MMU_IPMC_GROUP_TBL25; 1268 tr 52 M=MMU_IPMC_GROUP_TBL25; 1269 tr 71 M=MMU_IPMC_GROUP_TBL25 TSE=F SLTH=T; 1270 tr 71 M=MMU_IPMC_GROUP_TBL25 TSE=T SLTH=T; 1271 tr 71 M=MMU_IPMC_GROUP_TBL25 TSE=T SLTH=F; 1272 echo " MMU_IPMC_GROUP_TBL26"; 1273 tr 50 M=MMU_IPMC_GROUP_TBL26; 1274 tr 51 M=MMU_IPMC_GROUP_TBL26; 1275 tr 52 M=MMU_IPMC_GROUP_TBL26; 1276 tr 71 M=MMU_IPMC_GROUP_TBL26 TSE=F SLTH=T; 1277 tr 71 M=MMU_IPMC_GROUP_TBL26 TSE=T SLTH=T; 1278 tr 71 M=MMU_IPMC_GROUP_TBL26 TSE=T SLTH=F; 1279 echo " MMU_IPMC_GROUP_TBL27"; 1280 tr 50 M=MMU_IPMC_GROUP_TBL27; 1281 tr 51 M=MMU_IPMC_GROUP_TBL27; 1282 tr 52 M=MMU_IPMC_GROUP_TBL27; 1283 tr 71 M=MMU_IPMC_GROUP_TBL27 TSE=F SLTH=T; 1284 tr 71 M=MMU_IPMC_GROUP_TBL27 TSE=T SLTH=T; 1285 tr 71 M=MMU_IPMC_GROUP_TBL27 TSE=T SLTH=F; 1286 echo " MMU_IPMC_GROUP_TBL28"; 1287 tr 50 M=MMU_IPMC_GROUP_TBL28; 1288 tr 51 M=MMU_IPMC_GROUP_TBL28; 1289 tr 52 M=MMU_IPMC_GROUP_TBL28; 1290 tr 71 M=MMU_IPMC_GROUP_TBL28 TSE=F SLTH=T; 1291 tr 71 M=MMU_IPMC_GROUP_TBL28 TSE=T SLTH=T; 1292 tr 71 M=MMU_IPMC_GROUP_TBL28 TSE=T SLTH=F; 1293 echo " MMU_IPMC_GROUP_TBL29"; 1294 tr 50 M=MMU_IPMC_GROUP_TBL29; 1295 tr 51 M=MMU_IPMC_GROUP_TBL29; 1296 tr 52 M=MMU_IPMC_GROUP_TBL29; 1297 tr 71 M=MMU_IPMC_GROUP_TBL29 TSE=F SLTH=T; 1298 tr 71 M=MMU_IPMC_GROUP_TBL29 TSE=T SLTH=T; 1299 tr 71 M=MMU_IPMC_GROUP_TBL29 TSE=T SLTH=F; 1300 echo " MMU_IPMC_GROUP_TBL3"; 1301 tr 50 M=MMU_IPMC_GROUP_TBL3; 1302 tr 51 M=MMU_IPMC_GROUP_TBL3; 1303 tr 52 M=MMU_IPMC_GROUP_TBL3; 1304 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=F SLTH=T; 1305 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=T SLTH=T; 1306 tr 71 M=MMU_IPMC_GROUP_TBL3 TSE=T SLTH=F; 1307 echo " MMU_IPMC_GROUP_TBL4"; 1308 tr 50 M=MMU_IPMC_GROUP_TBL4; 1309 tr 51 M=MMU_IPMC_GROUP_TBL4; 1310 tr 52 M=MMU_IPMC_GROUP_TBL4; 1311 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=F SLTH=T; 1312 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=T SLTH=T; 1313 tr 71 M=MMU_IPMC_GROUP_TBL4 TSE=T SLTH=F; 1314 echo " MMU_IPMC_GROUP_TBL5"; 1315 tr 50 M=MMU_IPMC_GROUP_TBL5; 1316 tr 51 M=MMU_IPMC_GROUP_TBL5; 1317 tr 52 M=MMU_IPMC_GROUP_TBL5; 1318 tr 71 M=MMU_IPMC_GROUP_TBL5 TSE=F SLTH=T; 1319 tr 71 M=MMU_IPMC_GROUP_TBL5 TSE=T SLTH=T; 1320 tr 71 M=MMU_IPMC_GROUP_TBL5 TSE=T SLTH=F; 1321 echo " MMU_IPMC_GROUP_TBL6"; 1322 tr 50 M=MMU_IPMC_GROUP_TBL6; 1323 tr 51 M=MMU_IPMC_GROUP_TBL6; 1324 tr 52 M=MMU_IPMC_GROUP_TBL6; 1325 tr 71 M=MMU_IPMC_GROUP_TBL6 TSE=F SLTH=T; 1326 tr 71 M=MMU_IPMC_GROUP_TBL6 TSE=T SLTH=T; 1327 tr 71 M=MMU_IPMC_GROUP_TBL6 TSE=T SLTH=F; 1328 echo " MMU_IPMC_GROUP_TBL7"; 1329 tr 50 M=MMU_IPMC_GROUP_TBL7; 1330 tr 51 M=MMU_IPMC_GROUP_TBL7; 1331 tr 52 M=MMU_IPMC_GROUP_TBL7; 1332 tr 71 M=MMU_IPMC_GROUP_TBL7 TSE=F SLTH=T; 1333 tr 71 M=MMU_IPMC_GROUP_TBL7 TSE=T SLTH=T; 1334 tr 71 M=MMU_IPMC_GROUP_TBL7 TSE=T SLTH=F; 1335 echo " MMU_IPMC_GROUP_TBL8"; 1336 tr 50 M=MMU_IPMC_GROUP_TBL8; 1337 tr 51 M=MMU_IPMC_GROUP_TBL8; 1338 tr 52 M=MMU_IPMC_GROUP_TBL8; 1339 tr 71 M=MMU_IPMC_GROUP_TBL8 TSE=F SLTH=T; 1340 tr 71 M=MMU_IPMC_GROUP_TBL8 TSE=T SLTH=T; 1341 tr 71 M=MMU_IPMC_GROUP_TBL8 TSE=T SLTH=F; 1342 echo " MMU_IPMC_GROUP_TBL9"; 1343 tr 50 M=MMU_IPMC_GROUP_TBL9; 1344 tr 51 M=MMU_IPMC_GROUP_TBL9; 1345 tr 52 M=MMU_IPMC_GROUP_TBL9; 1346 tr 71 M=MMU_IPMC_GROUP_TBL9 TSE=F SLTH=T; 1347 tr 71 M=MMU_IPMC_GROUP_TBL9 TSE=T SLTH=T; 1348 tr 71 M=MMU_IPMC_GROUP_TBL9 TSE=T SLTH=F; 1349 echo " MMU_IPMC_VLAN_TBL"; 1350 tr 50 M=MMU_IPMC_VLAN_TBL; 1351 tr 51 M=MMU_IPMC_VLAN_TBL; 1352 tr 52 M=MMU_IPMC_VLAN_TBL; 1353 tr 71 M=MMU_IPMC_VLAN_TBL TSE=F SLTH=T; 1354 tr 71 M=MMU_IPMC_VLAN_TBL TSE=T SLTH=T; 1355 tr 71 M=MMU_IPMC_VLAN_TBL TSE=T SLTH=F; 1356 echo " MODPORT_MAP"; 1357 tr 50 M=MODPORT_MAP; 1358 tr 51 M=MODPORT_MAP; 1359 tr 52 M=MODPORT_MAP; 1360 tr 71 M=MODPORT_MAP TSE=F SLTH=T; 1361 tr 71 M=MODPORT_MAP TSE=T SLTH=T; 1362 tr 71 M=MODPORT_MAP TSE=T SLTH=F; 1363 echo " MODPORT_MAP_EM"; 1364 tr 50 M=MODPORT_MAP_EM; 1365 tr 51 M=MODPORT_MAP_EM; 1366 tr 52 M=MODPORT_MAP_EM; 1367 tr 71 M=MODPORT_MAP_EM TSE=F SLTH=T; 1368 tr 71 M=MODPORT_MAP_EM TSE=T SLTH=T; 1369 tr 71 M=MODPORT_MAP_EM TSE=T SLTH=F; 1370 echo " MODPORT_MAP_IM"; 1371 tr 50 M=MODPORT_MAP_IM; 1372 tr 51 M=MODPORT_MAP_IM; 1373 tr 52 M=MODPORT_MAP_IM; 1374 tr 71 M=MODPORT_MAP_IM TSE=F SLTH=T; 1375 tr 71 M=MODPORT_MAP_IM TSE=T SLTH=T; 1376 tr 71 M=MODPORT_MAP_IM TSE=T SLTH=F; 1377 echo " MODPORT_MAP_SW"; 1378 tr 50 M=MODPORT_MAP_SW; 1379 tr 51 M=MODPORT_MAP_SW; 1380 tr 52 M=MODPORT_MAP_SW; 1381 tr 71 M=MODPORT_MAP_SW TSE=F SLTH=T; 1382 tr 71 M=MODPORT_MAP_SW TSE=T SLTH=T; 1383 tr 71 M=MODPORT_MAP_SW TSE=T SLTH=F; 1384 echo " NONUCAST_TRUNK_BLOCK_MASK"; 1385 tr 50 M=NONUCAST_TRUNK_BLOCK_MASK; 1386 tr 51 M=NONUCAST_TRUNK_BLOCK_MASK; 1387 tr 52 M=NONUCAST_TRUNK_BLOCK_MASK; 1388 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=F SLTH=T; 1389 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=T SLTH=T; 1390 tr 71 M=NONUCAST_TRUNK_BLOCK_MASK TSE=T SLTH=F; 1391 echo " OAM_LM_COUNTERS"; 1392 tr 50 M=OAM_LM_COUNTERS; 1393 tr 51 M=OAM_LM_COUNTERS; 1394 tr 52 M=OAM_LM_COUNTERS; 1395 tr 71 M=OAM_LM_COUNTERS TSE=F SLTH=T; 1396 tr 71 M=OAM_LM_COUNTERS TSE=T SLTH=T; 1397 tr 71 M=OAM_LM_COUNTERS TSE=T SLTH=F; 1398 echo " OAM_OPCODE_CONTROL_PROFILE"; 1399 tr 50 M=OAM_OPCODE_CONTROL_PROFILE; 1400 tr 51 M=OAM_OPCODE_CONTROL_PROFILE; 1401 tr 52 M=OAM_OPCODE_CONTROL_PROFILE; 1402 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=F SLTH=T; 1403 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=T; 1404 tr 71 M=OAM_OPCODE_CONTROL_PROFILE TSE=T SLTH=F; 1405 echo " PORT_COS_MAP"; 1406 tr 50 M=PORT_COS_MAP; 1407 tr 51 M=PORT_COS_MAP; 1408 tr 52 M=PORT_COS_MAP; 1409 tr 71 M=PORT_COS_MAP TSE=F SLTH=T; 1410 tr 71 M=PORT_COS_MAP TSE=T SLTH=T; 1411 tr 71 M=PORT_COS_MAP TSE=T SLTH=F; 1412 echo " PORT_OR_TRUNK_MAC_COUNT"; 1413 tr 50 M=PORT_OR_TRUNK_MAC_COUNT; 1414 tr 51 M=PORT_OR_TRUNK_MAC_COUNT; 1415 tr 52 M=PORT_OR_TRUNK_MAC_COUNT; 1416 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=F SLTH=T; 1417 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=T SLTH=T; 1418 tr 71 M=PORT_OR_TRUNK_MAC_COUNT TSE=T SLTH=F; 1419 echo " PORT_OR_TRUNK_MAC_LIMIT"; 1420 tr 50 M=PORT_OR_TRUNK_MAC_LIMIT; 1421 tr 51 M=PORT_OR_TRUNK_MAC_LIMIT; 1422 tr 52 M=PORT_OR_TRUNK_MAC_LIMIT; 1423 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=F SLTH=T; 1424 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=T SLTH=T; 1425 tr 71 M=PORT_OR_TRUNK_MAC_LIMIT TSE=T SLTH=F; 1426 echo " PORT_TAB"; 1427 tr 50 M=PORT_TAB; 1428 tr 51 M=PORT_TAB; 1429 tr 52 M=PORT_TAB; 1430 tr 71 M=PORT_TAB TSE=F SLTH=T; 1431 tr 71 M=PORT_TAB TSE=T SLTH=T; 1432 tr 71 M=PORT_TAB TSE=T SLTH=F; 1433 echo " RMEP"; 1434 tr 50 M=RMEP; 1435 tr 51 M=RMEP; 1436 tr 52 M=RMEP; 1437 tr 71 M=RMEP TSE=F SLTH=T; 1438 tr 71 M=RMEP TSE=T SLTH=T; 1439 tr 71 M=RMEP TSE=T SLTH=F; 1440 echo " SER_MEMORY"; 1441 tr 50 M=SER_MEMORY; 1442 tr 51 M=SER_MEMORY; 1443 tr 52 M=SER_MEMORY; 1444 tr 71 M=SER_MEMORY TSE=F SLTH=T; 1445 tr 71 M=SER_MEMORY TSE=T SLTH=T; 1446 tr 71 M=SER_MEMORY TSE=T SLTH=F; 1447 echo " SER_RESULT_0"; 1448 tr 50 M=SER_RESULT_0; 1449 #tr 51 M=SER_RESULT_0; 1450 #tr 52 M=SER_RESULT_0; 1451 tr 71 M=SER_RESULT_0 TSE=F SLTH=T; 1452 tr 71 M=SER_RESULT_0 TSE=T SLTH=T; 1453 tr 71 M=SER_RESULT_0 TSE=T SLTH=F; 1454 echo " SER_RESULT_1"; 1455 tr 50 M=SER_RESULT_1; 1456 #tr 51 M=SER_RESULT_1; 1457 #tr 52 M=SER_RESULT_1; 1458 tr 71 M=SER_RESULT_1 TSE=F SLTH=T; 1459 tr 71 M=SER_RESULT_1 TSE=T SLTH=T; 1460 tr 71 M=SER_RESULT_1 TSE=T SLTH=F; 1461 echo " SER_RESULT_DATA_0"; 1462 tr 50 M=SER_RESULT_DATA_0; 1463 #tr 51 M=SER_RESULT_DATA_0; 1464 #tr 52 M=SER_RESULT_DATA_0; 1465 tr 71 M=SER_RESULT_DATA_0 TSE=F SLTH=T; 1466 tr 71 M=SER_RESULT_DATA_0 TSE=T SLTH=T; 1467 tr 71 M=SER_RESULT_DATA_0 TSE=T SLTH=F; 1468 echo " SER_RESULT_DATA_1"; 1469 tr 50 M=SER_RESULT_DATA_1; 1470 #tr 51 M=SER_RESULT_DATA_1; 1471 #tr 52 M=SER_RESULT_DATA_1; 1472 tr 71 M=SER_RESULT_DATA_1 TSE=F SLTH=T; 1473 tr 71 M=SER_RESULT_DATA_1 TSE=T SLTH=T; 1474 tr 71 M=SER_RESULT_DATA_1 TSE=T SLTH=F; 1475 echo " SER_RESULT_EXPECTED_0"; 1476 tr 50 M=SER_RESULT_EXPECTED_0; 1477 #tr 51 M=SER_RESULT_EXPECTED_0; 1478 #tr 52 M=SER_RESULT_EXPECTED_0; 1479 tr 71 M=SER_RESULT_EXPECTED_0 TSE=F SLTH=T; 1480 tr 71 M=SER_RESULT_EXPECTED_0 TSE=T SLTH=T; 1481 tr 71 M=SER_RESULT_EXPECTED_0 TSE=T SLTH=F; 1482 echo " SER_RESULT_EXPECTED_1"; 1483 tr 50 M=SER_RESULT_EXPECTED_1; 1484 #tr 51 M=SER_RESULT_EXPECTED_1; 1485 #tr 52 M=SER_RESULT_EXPECTED_1; 1486 tr 71 M=SER_RESULT_EXPECTED_1 TSE=F SLTH=T; 1487 tr 71 M=SER_RESULT_EXPECTED_1 TSE=T SLTH=T; 1488 tr 71 M=SER_RESULT_EXPECTED_1 TSE=T SLTH=F; 1489 echo " SOURCE_TRUNK_MAP_TABLE"; 1490 tr 50 M=SOURCE_TRUNK_MAP_TABLE; 1491 tr 51 M=SOURCE_TRUNK_MAP_TABLE; 1492 tr 52 M=SOURCE_TRUNK_MAP_TABLE; 1493 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=F SLTH=T; 1494 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=T SLTH=T; 1495 tr 71 M=SOURCE_TRUNK_MAP_TABLE TSE=T SLTH=F; 1496 echo " SRC_MODID_BLOCK"; 1497 tr 50 M=SRC_MODID_BLOCK; 1498 tr 51 M=SRC_MODID_BLOCK; 1499 tr 52 M=SRC_MODID_BLOCK; 1500 tr 71 M=SRC_MODID_BLOCK TSE=F SLTH=T; 1501 tr 71 M=SRC_MODID_BLOCK TSE=T SLTH=T; 1502 tr 71 M=SRC_MODID_BLOCK TSE=T SLTH=F; 1503 echo " STG_TAB"; 1504 tr 50 M=STG_TAB; 1505 tr 51 M=STG_TAB; 1506 tr 52 M=STG_TAB; 1507 tr 71 M=STG_TAB TSE=F SLTH=T; 1508 tr 71 M=STG_TAB TSE=T SLTH=T; 1509 tr 71 M=STG_TAB TSE=T SLTH=F; 1510 echo " SYSTEM_CONFIG_TABLE"; 1511 tr 50 M=SYSTEM_CONFIG_TABLE; 1512 tr 51 M=SYSTEM_CONFIG_TABLE; 1513 tr 52 M=SYSTEM_CONFIG_TABLE; 1514 tr 71 M=SYSTEM_CONFIG_TABLE TSE=F SLTH=T; 1515 tr 71 M=SYSTEM_CONFIG_TABLE TSE=T SLTH=T; 1516 tr 71 M=SYSTEM_CONFIG_TABLE TSE=T SLTH=F; 1517 echo " TCP_FN"; 1518 tr 50 M=TCP_FN; 1519 tr 51 M=TCP_FN; 1520 tr 52 M=TCP_FN; 1521 tr 71 M=TCP_FN TSE=F SLTH=T; 1522 tr 71 M=TCP_FN TSE=T SLTH=T; 1523 tr 71 M=TCP_FN TSE=T SLTH=F; 1524 echo " TOS_FN"; 1525 tr 50 M=TOS_FN; 1526 tr 51 M=TOS_FN; 1527 tr 52 M=TOS_FN; 1528 tr 71 M=TOS_FN TSE=F SLTH=T; 1529 tr 71 M=TOS_FN TSE=T SLTH=T; 1530 tr 71 M=TOS_FN TSE=T SLTH=F; 1531 echo " TRUNK32_CONFIG_TABLE"; 1532 tr 50 M=TRUNK32_CONFIG_TABLE; 1533 tr 51 M=TRUNK32_CONFIG_TABLE; 1534 tr 52 M=TRUNK32_CONFIG_TABLE; 1535 tr 71 M=TRUNK32_CONFIG_TABLE TSE=F SLTH=T; 1536 tr 71 M=TRUNK32_CONFIG_TABLE TSE=T SLTH=T; 1537 tr 71 M=TRUNK32_CONFIG_TABLE TSE=T SLTH=F; 1538 echo " TRUNK32_PORT_TABLE"; 1539 tr 50 M=TRUNK32_PORT_TABLE; 1540 tr 51 M=TRUNK32_PORT_TABLE; 1541 tr 52 M=TRUNK32_PORT_TABLE; 1542 tr 71 M=TRUNK32_PORT_TABLE TSE=F SLTH=T; 1543 tr 71 M=TRUNK32_PORT_TABLE TSE=T SLTH=T; 1544 tr 71 M=TRUNK32_PORT_TABLE TSE=T SLTH=F; 1545 echo " TRUNK_BITMAP"; 1546 tr 50 M=TRUNK_BITMAP; 1547 tr 51 M=TRUNK_BITMAP; 1548 tr 52 M=TRUNK_BITMAP; 1549 tr 71 M=TRUNK_BITMAP TSE=F SLTH=T; 1550 tr 71 M=TRUNK_BITMAP TSE=T SLTH=T; 1551 tr 71 M=TRUNK_BITMAP TSE=T SLTH=F; 1552 echo " TRUNK_EGR_MASK"; 1553 tr 50 M=TRUNK_EGR_MASK; 1554 tr 51 M=TRUNK_EGR_MASK; 1555 tr 52 M=TRUNK_EGR_MASK; 1556 tr 71 M=TRUNK_EGR_MASK TSE=F SLTH=T; 1557 tr 71 M=TRUNK_EGR_MASK TSE=T SLTH=T; 1558 tr 71 M=TRUNK_EGR_MASK TSE=T SLTH=F; 1559 echo " TRUNK_GROUP"; 1560 tr 50 M=TRUNK_GROUP; 1561 tr 51 M=TRUNK_GROUP; 1562 tr 52 M=TRUNK_GROUP; 1563 tr 71 M=TRUNK_GROUP TSE=F SLTH=T; 1564 tr 71 M=TRUNK_GROUP TSE=T SLTH=T; 1565 tr 71 M=TRUNK_GROUP TSE=T SLTH=F; 1566 echo " TTL_FN"; 1567 tr 50 M=TTL_FN; 1568 tr 51 M=TTL_FN; 1569 tr 52 M=TTL_FN; 1570 tr 71 M=TTL_FN TSE=F SLTH=T; 1571 tr 71 M=TTL_FN TSE=T SLTH=T; 1572 tr 71 M=TTL_FN TSE=T SLTH=F; 1573 echo " VLAN_MAC"; 1574 tr 50 M=VLAN_MAC; 1575 tr 51 M=VLAN_MAC; 1576 tr 52 M=VLAN_MAC; 1577 tr 71 M=VLAN_MAC TSE=F SLTH=T; 1578 tr 71 M=VLAN_MAC TSE=T SLTH=T; 1579 tr 71 M=VLAN_MAC TSE=T SLTH=F; 1580 echo " VLAN_OR_VFI_MAC_COUNT"; 1581 tr 50 M=VLAN_OR_VFI_MAC_COUNT; 1582 tr 51 M=VLAN_OR_VFI_MAC_COUNT; 1583 tr 52 M=VLAN_OR_VFI_MAC_COUNT; 1584 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=F SLTH=T; 1585 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=T SLTH=T; 1586 tr 71 M=VLAN_OR_VFI_MAC_COUNT TSE=T SLTH=F; 1587 echo " VLAN_OR_VFI_MAC_LIMIT"; 1588 tr 50 M=VLAN_OR_VFI_MAC_LIMIT; 1589 tr 51 M=VLAN_OR_VFI_MAC_LIMIT; 1590 tr 52 M=VLAN_OR_VFI_MAC_LIMIT; 1591 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=F SLTH=T; 1592 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=T SLTH=T; 1593 tr 71 M=VLAN_OR_VFI_MAC_LIMIT TSE=T SLTH=F; 1594 echo " VLAN_PROFILE_2"; 1595 tr 50 M=VLAN_PROFILE_2; 1596 tr 51 M=VLAN_PROFILE_2; 1597 tr 52 M=VLAN_PROFILE_2; 1598 tr 71 M=VLAN_PROFILE_2 TSE=F SLTH=T; 1599 tr 71 M=VLAN_PROFILE_2 TSE=T SLTH=T; 1600 tr 71 M=VLAN_PROFILE_2 TSE=T SLTH=F; 1601 echo " VLAN_PROFILE_TAB"; 1602 tr 50 M=VLAN_PROFILE_TAB; 1603 tr 51 M=VLAN_PROFILE_TAB; 1604 tr 52 M=VLAN_PROFILE_TAB; 1605 tr 71 M=VLAN_PROFILE_TAB TSE=F SLTH=T; 1606 tr 71 M=VLAN_PROFILE_TAB TSE=T SLTH=T; 1607 tr 71 M=VLAN_PROFILE_TAB TSE=T SLTH=F; 1608 echo " VLAN_PROTOCOL"; 1609 tr 50 M=VLAN_PROTOCOL; 1610 tr 51 M=VLAN_PROTOCOL; 1611 tr 52 M=VLAN_PROTOCOL; 1612 tr 71 M=VLAN_PROTOCOL TSE=F SLTH=T; 1613 tr 71 M=VLAN_PROTOCOL TSE=T SLTH=T; 1614 tr 71 M=VLAN_PROTOCOL TSE=T SLTH=F; 1615 echo " VLAN_PROTOCOL_DATA"; 1616 tr 50 M=VLAN_PROTOCOL_DATA; 1617 tr 51 M=VLAN_PROTOCOL_DATA; 1618 tr 52 M=VLAN_PROTOCOL_DATA; 1619 tr 71 M=VLAN_PROTOCOL_DATA TSE=F SLTH=T; 1620 tr 71 M=VLAN_PROTOCOL_DATA TSE=T SLTH=T; 1621 tr 71 M=VLAN_PROTOCOL_DATA TSE=T SLTH=F; 1622 echo " VLAN_SUBNET"; 1623 tr 50 M=VLAN_SUBNET; 1624 tr 51 M=VLAN_SUBNET; 1625 tr 52 M=VLAN_SUBNET; 1626 tr 71 M=VLAN_SUBNET TSE=F SLTH=T; 1627 tr 71 M=VLAN_SUBNET TSE=T SLTH=T; 1628 tr 71 M=VLAN_SUBNET TSE=T SLTH=F; 1629 echo " VLAN_SUBNET_DATA_ONLY"; 1630 tr 50 M=VLAN_SUBNET_DATA_ONLY; 1631 tr 51 M=VLAN_SUBNET_DATA_ONLY; 1632 tr 52 M=VLAN_SUBNET_DATA_ONLY; 1633 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=F SLTH=T; 1634 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=T SLTH=T; 1635 tr 71 M=VLAN_SUBNET_DATA_ONLY TSE=T SLTH=F; 1636 echo " VLAN_SUBNET_ONLY"; 1637 tr 50 M=VLAN_SUBNET_ONLY; 1638 tr 51 M=VLAN_SUBNET_ONLY; 1639 tr 52 M=VLAN_SUBNET_ONLY; 1640 tr 71 M=VLAN_SUBNET_ONLY TSE=F SLTH=T; 1641 tr 71 M=VLAN_SUBNET_ONLY TSE=T SLTH=T; 1642 tr 71 M=VLAN_SUBNET_ONLY TSE=T SLTH=F; 1643 echo " VLAN_TAB"; 1644 tr 50 M=VLAN_TAB; 1645 tr 51 M=VLAN_TAB; 1646 tr 52 M=VLAN_TAB; 1647 tr 71 M=VLAN_TAB TSE=F SLTH=T; 1648 tr 71 M=VLAN_TAB TSE=T SLTH=T; 1649 tr 71 M=VLAN_TAB TSE=T SLTH=F; 1650 echo " VLAN_XLATE"; 1651 tr 50 M=VLAN_XLATE; 1652 tr 51 M=VLAN_XLATE; 1653 tr 52 M=VLAN_XLATE; 1654 tr 71 M=VLAN_XLATE TSE=F SLTH=T; 1655 tr 71 M=VLAN_XLATE TSE=T SLTH=T; 1656 tr 71 M=VLAN_XLATE TSE=T SLTH=F; 1657 1658 #New add memories test 1659 echo " EGR_ETAG_PCP_MAPPING"; 1660 tr 50 M=EGR_ETAG_PCP_MAPPING; 1661 tr 51 M=EGR_ETAG_PCP_MAPPING; 1662 tr 52 M=EGR_ETAG_PCP_MAPPING; 1663 tr 71 M=EGR_ETAG_PCP_MAPPING TSE=F SLTH=T; 1664 tr 71 M=EGR_ETAG_PCP_MAPPING TSE=T SLTH=T; 1665 tr 71 M=EGR_ETAG_PCP_MAPPING TSE=T SLTH=F; 1666 echo " EGR_GPP_ATTRIBUTES"; 1667 tr 50 M=EGR_GPP_ATTRIBUTES; 1668 tr 51 M=EGR_GPP_ATTRIBUTES; 1669 tr 52 M=EGR_GPP_ATTRIBUTES; 1670 tr 71 M=EGR_GPP_ATTRIBUTES TSE=F SLTH=T; 1671 tr 71 M=EGR_GPP_ATTRIBUTES TSE=T SLTH=T; 1672 tr 71 M=EGR_GPP_ATTRIBUTES TSE=T SLTH=F; 1673 echo " EGR_INT_CN_TO_IP_MAPPING"; 1674 tr 50 M=EGR_INT_CN_TO_IP_MAPPING; 1675 tr 51 M=EGR_INT_CN_TO_IP_MAPPING; 1676 tr 52 M=EGR_INT_CN_TO_IP_MAPPING; 1677 tr 71 M=EGR_INT_CN_TO_IP_MAPPING TSE=F SLTH=T; 1678 tr 71 M=EGR_INT_CN_TO_IP_MAPPING TSE=T SLTH=T; 1679 tr 71 M=EGR_INT_CN_TO_IP_MAPPING TSE=T SLTH=F; 1680 echo " EGR_INT_CN_UPDATE"; 1681 tr 50 M=EGR_INT_CN_UPDATE; 1682 tr 51 M=EGR_INT_CN_UPDATE; 1683 tr 52 M=EGR_INT_CN_UPDATE; 1684 tr 71 M=EGR_INT_CN_UPDATE TSE=F SLTH=T; 1685 tr 71 M=EGR_INT_CN_UPDATE TSE=T SLTH=T; 1686 tr 71 M=EGR_INT_CN_UPDATE TSE=T SLTH=F; 1687 echo " EGRESS_MASK"; 1688 tr 50 M=EGRESS_MASK; 1689 tr 51 M=EGRESS_MASK; 1690 tr 52 M=EGRESS_MASK; 1691 tr 71 M=EGRESS_MASK TSE=F SLTH=T; 1692 tr 71 M=EGRESS_MASK TSE=T SLTH=T; 1693 tr 71 M=EGRESS_MASK TSE=T SLTH=F; 1694 echo " EGR_MIRROR_ENCAP_DATA_1"; 1695 tr 50 M=EGR_MIRROR_ENCAP_DATA_1; 1696 tr 51 M=EGR_MIRROR_ENCAP_DATA_1; 1697 tr 52 M=EGR_MIRROR_ENCAP_DATA_1; 1698 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=F SLTH=T; 1699 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=T SLTH=T; 1700 tr 71 M=EGR_MIRROR_ENCAP_DATA_1 TSE=T SLTH=F; 1701 echo " EGR_MIRROR_ENCAP_DATA_2"; 1702 tr 50 M=EGR_MIRROR_ENCAP_DATA_2; 1703 tr 51 M=EGR_MIRROR_ENCAP_DATA_2; 1704 tr 52 M=EGR_MIRROR_ENCAP_DATA_2; 1705 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=F SLTH=T; 1706 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=T SLTH=T; 1707 tr 71 M=EGR_MIRROR_ENCAP_DATA_2 TSE=T SLTH=F; 1708 echo " EGR_PER_Q_ECN_MARKED"; 1709 tr 50 M=EGR_PER_Q_ECN_MARKED; 1710 tr 51 M=EGR_PER_Q_ECN_MARKED; 1711 tr 52 M=EGR_PER_Q_ECN_MARKED; 1712 tr 71 M=EGR_PER_Q_ECN_MARKED TSE=F SLTH=T; 1713 tr 71 M=EGR_PER_Q_ECN_MARKED TSE=T SLTH=T; 1714 tr 71 M=EGR_PER_Q_ECN_MARKED TSE=T SLTH=F; 1715 echo " EGR_PFC_CONTROL"; 1716 tr 50 M=EGR_PFC_CONTROL; 1717 tr 51 M=EGR_PFC_CONTROL; 1718 tr 52 M=EGR_PFC_CONTROL; 1719 tr 71 M=EGR_PFC_CONTROL TSE=F SLTH=T; 1720 tr 71 M=EGR_PFC_CONTROL TSE=T SLTH=T; 1721 tr 71 M=EGR_PFC_CONTROL TSE=T SLTH=F; 1722 echo " ING_ETAG_PCP_MAPPING"; 1723 tr 50 M=ING_ETAG_PCP_MAPPING; 1724 tr 51 M=ING_ETAG_PCP_MAPPING; 1725 tr 52 M=ING_ETAG_PCP_MAPPING; 1726 tr 71 M=ING_ETAG_PCP_MAPPING TSE=F SLTH=T; 1727 tr 71 M=ING_ETAG_PCP_MAPPING TSE=T SLTH=T; 1728 tr 71 M=ING_ETAG_PCP_MAPPING TSE=T SLTH=F; 1729 echo " INT_CN_TO_MMUIF_MAPPING"; 1730 tr 50 M=INT_CN_TO_MMUIF_MAPPING; 1731 tr 51 M=INT_CN_TO_MMUIF_MAPPING; 1732 tr 52 M=INT_CN_TO_MMUIF_MAPPING; 1733 tr 71 M=INT_CN_TO_MMUIF_MAPPING TSE=F SLTH=T; 1734 tr 71 M=INT_CN_TO_MMUIF_MAPPING TSE=T SLTH=T; 1735 tr 71 M=INT_CN_TO_MMUIF_MAPPING TSE=T SLTH=F; 1736 echo " IP_TO_INT_CN_MAPPING"; 1737 tr 50 M=IP_TO_INT_CN_MAPPING; 1738 tr 51 M=IP_TO_INT_CN_MAPPING; 1739 tr 52 M=IP_TO_INT_CN_MAPPING; 1740 tr 71 M=IP_TO_INT_CN_MAPPING TSE=F SLTH=T; 1741 tr 71 M=IP_TO_INT_CN_MAPPING TSE=T SLTH=T; 1742 tr 71 M=IP_TO_INT_CN_MAPPING TSE=T SLTH=F; 1743 echo " PORT_MAC_BLOCK"; 1744 tr 50 M=PORT_MAC_BLOCK; 1745 tr 51 M=PORT_MAC_BLOCK; 1746 tr 52 M=PORT_MAC_BLOCK; 1747 tr 71 M=PORT_MAC_BLOCK TSE=F SLTH=T; 1748 tr 71 M=PORT_MAC_BLOCK TSE=T SLTH=T; 1749 tr 71 M=PORT_MAC_BLOCK TSE=T SLTH=F; 1750 echo " CBPCELLHEADER"; 1751 tr 50 M=CBPCELLHEADER; 1752 tr 51 M=CBPCELLHEADER; 1753 tr 52 M=CBPCELLHEADER; 1754 tr 71 M=CBPCELLHEADER TSE=F SLTH=T; 1755 tr 71 M=CBPCELLHEADER TSE=T SLTH=T; 1756 tr 71 M=CBPCELLHEADER TSE=T SLTH=F; 1757 echo " CBPDATA0"; 1758 tr 50 M=CBPDATA0; 1759 tr 51 M=CBPDATA0; 1760 tr 52 M=CBPDATA0; 1761 tr 71 M=CBPDATA0 TSE=F SLTH=T; 1762 tr 71 M=CBPDATA0 TSE=T SLTH=T; 1763 tr 71 M=CBPDATA0 TSE=T SLTH=F; 1764 echo " CBPDATA1"; 1765 tr 50 M=CBPDATA1; 1766 tr 51 M=CBPDATA1; 1767 tr 52 M=CBPDATA1; 1768 tr 71 M=CBPDATA1 TSE=F SLTH=T; 1769 tr 71 M=CBPDATA1 TSE=T SLTH=T; 1770 tr 71 M=CBPDATA1 TSE=T SLTH=F; 1771 echo " CBPDATA2"; 1772 tr 50 M=CBPDATA2; 1773 tr 51 M=CBPDATA2; 1774 tr 52 M=CBPDATA2; 1775 tr 71 M=CBPDATA2 TSE=F SLTH=T; 1776 tr 71 M=CBPDATA2 TSE=T SLTH=T; 1777 tr 71 M=CBPDATA2 TSE=T SLTH=F; 1778 echo " CBPDATA3"; 1779 tr 50 M=CBPDATA3; 1780 tr 51 M=CBPDATA3; 1781 tr 52 M=CBPDATA3; 1782 tr 71 M=CBPDATA3 TSE=F SLTH=T; 1783 tr 71 M=CBPDATA3 TSE=T SLTH=T; 1784 tr 71 M=CBPDATA3 TSE=T SLTH=F; 1785 echo " CBPDATA4"; 1786 tr 50 M=CBPDATA4; 1787 tr 51 M=CBPDATA4; 1788 tr 52 M=CBPDATA4; 1789 tr 71 M=CBPDATA4 TSE=F SLTH=T; 1790 tr 71 M=CBPDATA4 TSE=T SLTH=T; 1791 tr 71 M=CBPDATA4 TSE=T SLTH=F; 1792 echo " CBPDATA5"; 1793 tr 50 M=CBPDATA5; 1794 tr 51 M=CBPDATA5; 1795 tr 52 M=CBPDATA5; 1796 tr 71 M=CBPDATA5 TSE=F SLTH=T; 1797 tr 71 M=CBPDATA5 TSE=T SLTH=T; 1798 tr 71 M=CBPDATA5 TSE=T SLTH=F; 1799 echo " CBPDATA6"; 1800 tr 50 M=CBPDATA6; 1801 tr 51 M=CBPDATA6; 1802 tr 52 M=CBPDATA6; 1803 tr 71 M=CBPDATA6 TSE=F SLTH=T; 1804 tr 71 M=CBPDATA6 TSE=T SLTH=T; 1805 tr 71 M=CBPDATA6 TSE=T SLTH=F; 1806 echo " CBPDATA7"; 1807 tr 50 M=CBPDATA7; 1808 tr 51 M=CBPDATA7; 1809 tr 52 M=CBPDATA7; 1810 tr 71 M=CBPDATA7 TSE=F SLTH=T; 1811 tr 71 M=CBPDATA7 TSE=T SLTH=T; 1812 tr 71 M=CBPDATA7 TSE=T SLTH=F; 1813 echo " CBPPKTHEADER0"; 1814 tr 50 M=CBPPKTHEADER0; 1815 tr 51 M=CBPPKTHEADER0; 1816 tr 52 M=CBPPKTHEADER0; 1817 tr 71 M=CBPPKTHEADER0 TSE=F SLTH=T; 1818 tr 71 M=CBPPKTHEADER0 TSE=T SLTH=T; 1819 tr 71 M=CBPPKTHEADER0 TSE=T SLTH=F; 1820 echo " CBPPKTHEADER1"; 1821 tr 50 M=CBPPKTHEADER1; 1822 tr 51 M=CBPPKTHEADER1; 1823 tr 52 M=CBPPKTHEADER1; 1824 tr 71 M=CBPPKTHEADER1 TSE=F SLTH=T; 1825 tr 71 M=CBPPKTHEADER1 TSE=T SLTH=T; 1826 tr 71 M=CBPPKTHEADER1 TSE=T SLTH=F; 1827 echo " CBPPKTHEADER2"; 1828 tr 50 M=CBPPKTHEADER2; 1829 tr 51 M=CBPPKTHEADER2; 1830 tr 52 M=CBPPKTHEADER2; 1831 tr 71 M=CBPPKTHEADER2 TSE=F SLTH=T; 1832 tr 71 M=CBPPKTHEADER2 TSE=T SLTH=T; 1833 tr 71 M=CBPPKTHEADER2 TSE=T SLTH=F; 1834 echo " CBPPKTHEADER_EXT"; 1835 tr 50 M=CBPPKTHEADER_EXT; 1836 tr 51 M=CBPPKTHEADER_EXT; 1837 tr 52 M=CBPPKTHEADER_EXT; 1838 tr 71 M=CBPPKTHEADER_EXT TSE=F SLTH=T; 1839 tr 71 M=CBPPKTHEADER_EXT TSE=T SLTH=T; 1840 tr 71 M=CBPPKTHEADER_EXT TSE=T SLTH=F; 1841 echo " MMU_WRED_UC_QUEUE_CONFIG"; 1842 tr 50 M=MMU_WRED_UC_QUEUE_CONFIG; 1843 tr 51 M=MMU_WRED_UC_QUEUE_CONFIG; 1844 tr 52 M=MMU_WRED_UC_QUEUE_CONFIG; 1845 tr 71 M=MMU_WRED_UC_QUEUE_CONFIG TSE=F SLTH=T; 1846 tr 71 M=MMU_WRED_UC_QUEUE_CONFIG TSE=T SLTH=T; 1847 tr 71 M=MMU_WRED_UC_QUEUE_CONFIG TSE=T SLTH=F; 1848 echo " MMU_WRED_DROP_PROFILE_GREEN"; 1849 tr 50 M=MMU_WRED_DROP_PROFILE_GREEN; 1850 tr 51 M=MMU_WRED_DROP_PROFILE_GREEN; 1851 tr 52 M=MMU_WRED_DROP_PROFILE_GREEN; 1852 tr 71 M=MMU_WRED_DROP_PROFILE_GREEN TSE=F SLTH=T; 1853 tr 71 M=MMU_WRED_DROP_PROFILE_GREEN TSE=T SLTH=T; 1854 tr 71 M=MMU_WRED_DROP_PROFILE_GREEN TSE=T SLTH=F; 1855 echo " MMU_WRED_DROP_PROFILE_RED"; 1856 tr 50 M=MMU_WRED_DROP_PROFILE_RED; 1857 tr 51 M=MMU_WRED_DROP_PROFILE_RED; 1858 tr 52 M=MMU_WRED_DROP_PROFILE_RED; 1859 tr 71 M=MMU_WRED_DROP_PROFILE_RED TSE=F SLTH=T; 1860 tr 71 M=MMU_WRED_DROP_PROFILE_RED TSE=T SLTH=T; 1861 tr 71 M=MMU_WRED_DROP_PROFILE_RED TSE=T SLTH=F; 1862 echo " MMU_WRED_DROP_PROFILE_YELLOW"; 1863 tr 50 M=MMU_WRED_DROP_PROFILE_YELLOW; 1864 tr 51 M=MMU_WRED_DROP_PROFILE_YELLOW; 1865 tr 52 M=MMU_WRED_DROP_PROFILE_YELLOW; 1866 tr 71 M=MMU_WRED_DROP_PROFILE_YELLOW TSE=F SLTH=T; 1867 tr 71 M=MMU_WRED_DROP_PROFILE_YELLOW TSE=T SLTH=T; 1868 tr 71 M=MMU_WRED_DROP_PROFILE_YELLOW TSE=T SLTH=F; 1869 echo " MMU_WRED_MARK_PROFILE_GREEN"; 1870 tr 50 M=MMU_WRED_MARK_PROFILE_GREEN; 1871 tr 51 M=MMU_WRED_MARK_PROFILE_GREEN; 1872 tr 52 M=MMU_WRED_MARK_PROFILE_GREEN; 1873 tr 71 M=MMU_WRED_MARK_PROFILE_GREEN TSE=F SLTH=T; 1874 tr 71 M=MMU_WRED_MARK_PROFILE_GREEN TSE=T SLTH=T; 1875 tr 71 M=MMU_WRED_MARK_PROFILE_GREEN TSE=T SLTH=F; 1876 echo " MMU_WRED_MARK_PROFILE_RED"; 1877 tr 50 M=MMU_WRED_MARK_PROFILE_RED; 1878 tr 51 M=MMU_WRED_MARK_PROFILE_RED; 1879 tr 52 M=MMU_WRED_MARK_PROFILE_RED; 1880 tr 71 M=MMU_WRED_MARK_PROFILE_RED TSE=F SLTH=T; 1881 tr 71 M=MMU_WRED_MARK_PROFILE_RED TSE=T SLTH=T; 1882 tr 71 M=MMU_WRED_MARK_PROFILE_RED TSE=T SLTH=F; 1883 echo " MMU_WRED_MARK_PROFILE_YELLOW"; 1884 tr 50 M=MMU_WRED_MARK_PROFILE_YELLOW; 1885 tr 51 M=MMU_WRED_MARK_PROFILE_YELLOW; 1886 tr 52 M=MMU_WRED_MARK_PROFILE_YELLOW; 1887 tr 71 M=MMU_WRED_MARK_PROFILE_YELLOW TSE=F SLTH=T; 1888 tr 71 M=MMU_WRED_MARK_PROFILE_YELLOW TSE=T SLTH=T; 1889 tr 71 M=MMU_WRED_MARK_PROFILE_YELLOW TSE=T SLTH=F; 1890 echo " RESPONSIVE_PROTOCOL_MATCH"; 1891 tr 50 M=RESPONSIVE_PROTOCOL_MATCH; 1892 tr 51 M=RESPONSIVE_PROTOCOL_MATCH; 1893 tr 52 M=RESPONSIVE_PROTOCOL_MATCH; 1894 tr 71 M=RESPONSIVE_PROTOCOL_MATCH TSE=F SLTH=T; 1895 tr 71 M=RESPONSIVE_PROTOCOL_MATCH TSE=T SLTH=T; 1896 tr 71 M=RESPONSIVE_PROTOCOL_MATCH TSE=T SLTH=F; 1897 echo " SER_ACC_TYPE_MAP"; 1898 tr 50 M=SER_ACC_TYPE_MAP; 1899 tr 51 M=SER_ACC_TYPE_MAP; 1900 tr 52 M=SER_ACC_TYPE_MAP; 1901 tr 71 M=SER_ACC_TYPE_MAP TSE=F SLTH=T; 1902 tr 71 M=SER_ACC_TYPE_MAP TSE=T SLTH=T; 1903 tr 71 M=SER_ACC_TYPE_MAP TSE=T SLTH=F; 1904 1905 #The BUCKETf will be updated if MISCCONFIG.METERING_CLK_ENf=1 1906 # The bit will be set after doing init misc 1907 echo " MMU_MAX_BUCKET_PGRP0"; 1908 tr 50 M=MMU_MAX_BUCKET_PGRP0; 1909 tr 51 M=MMU_MAX_BUCKET_PGRP0; 1910 tr 52 M=MMU_MAX_BUCKET_PGRP0; 1911 tr 71 M=MMU_MAX_BUCKET_PGRP0 TSE=F SLTH=T; 1912 tr 71 M=MMU_MAX_BUCKET_PGRP0 TSE=T SLTH=T; 1913 tr 71 M=MMU_MAX_BUCKET_PGRP0 TSE=T SLTH=F; 1914 echo " MMU_MAX_BUCKET_PGRP1"; 1915 tr 50 M=MMU_MAX_BUCKET_PGRP1; 1916 tr 51 M=MMU_MAX_BUCKET_PGRP1; 1917 tr 52 M=MMU_MAX_BUCKET_PGRP1; 1918 tr 71 M=MMU_MAX_BUCKET_PGRP1 TSE=F SLTH=T; 1919 tr 71 M=MMU_MAX_BUCKET_PGRP1 TSE=T SLTH=T; 1920 tr 71 M=MMU_MAX_BUCKET_PGRP1 TSE=T SLTH=F; 1921 echo " MMU_MIN_BUCKET_PGRP0"; 1922 tr 50 M=MMU_MIN_BUCKET_PGRP0; 1923 tr 51 M=MMU_MIN_BUCKET_PGRP0; 1924 tr 52 M=MMU_MIN_BUCKET_PGRP0; 1925 tr 71 M=MMU_MIN_BUCKET_PGRP0 TSE=F SLTH=T; 1926 tr 71 M=MMU_MIN_BUCKET_PGRP0 TSE=T SLTH=T; 1927 tr 71 M=MMU_MIN_BUCKET_PGRP0 TSE=T SLTH=F; 1928 echo " MMU_MIN_BUCKET_PGRP1"; 1929 tr 50 M=MMU_MIN_BUCKET_PGRP1; 1930 tr 51 M=MMU_MIN_BUCKET_PGRP1; 1931 tr 52 M=MMU_MIN_BUCKET_PGRP1; 1932 tr 71 M=MMU_MIN_BUCKET_PGRP1 TSE=F SLTH=T; 1933 tr 71 M=MMU_MIN_BUCKET_PGRP1 TSE=T SLTH=T; 1934 tr 71 M=MMU_MIN_BUCKET_PGRP1 TSE=T SLTH=F; 1935 1936 #It doesn't support read. Write also require other commends. 1937 #echo " XLPORT_WC_UCMEM_DATA"; 1938 #tr 50 M=XLPORT_WC_UCMEM_DATA; 1939 #tr 51 M=XLPORT_WC_UCMEM_DATA; 1940 #tr 52 M=XLPORT_WC_UCMEM_DATA; 1941 #tr 71 M=XLPORT_WC_UCMEM_DATA TSE=F SLTH=T; 1942 #tr 71 M=XLPORT_WC_UCMEM_DATA TSE=T SLTH=T; 1943 #tr 71 M=XLPORT_WC_UCMEM_DATA TSE=T SLTH=F; 1944 1945 #Need to disable WRED_REFRESH_ENf before testing 1946 #echo " MMU_WRED_UC_QUEUE_AVG_QSIZE"; 1947 #tr 50 M=MMU_WRED_UC_QUEUE_AVG_QSIZE; 1948 #tr 51 M=MMU_WRED_UC_QUEUE_AVG_QSIZE; 1949 #tr 52 M=MMU_WRED_UC_QUEUE_AVG_QSIZE; 1950 #tr 71 M=MMU_WRED_UC_QUEUE_AVG_QSIZE TSE=F SLTH=T; 1951 #tr 71 M=MMU_WRED_UC_QUEUE_AVG_QSIZE TSE=T SLTH=T; 1952 #tr 71 M=MMU_WRED_UC_QUEUE_AVG_QSIZE TSE=T SLTH=F; 1953 #echo " MMU_WRED_MARK_THD"; 1954 #tr 50 M=MMU_WRED_MARK_THD; 1955 #tr 51 M=MMU_WRED_MARK_THD; 1956 #tr 52 M=MMU_WRED_MARK_THD; 1957 #tr 71 M=MMU_WRED_MARK_THD TSE=F SLTH=T; 1958 #tr 71 M=MMU_WRED_MARK_THD TSE=T SLTH=T; 1959 #tr 71 M=MMU_WRED_MARK_THD TSE=T SLTH=F; 1960 1961 # Re-initialize to clean up of various read/wrires to MMU memories 1962 set rct=true 1963 rcload rc.soc 1964 counter off 1965 l2mode off 1966 linkscan off 1967 1968 echo "Running counter width verification test ..." 1969 tr 30 1970 $done 1971 1972 echo "Running counter read/write test ..." 1973 tr 31 1974 $done 1975 1976 #L2/L3 hashing tests 1977 echo "Running L2 insert/delete/lookup test ..." 1978 tr 32 1979 $done 1980 1981 echo "Running L2 overflow insert test ..." 1982 tr 33 1983 $done 1984 1985 echo "Running L2 hash test ..." 1986 tr 34 1987 $done 1988 1989 echo "Running L2 delete by port test ..." 1990 tr 35 1991 $done 1992 1993 echo "Running L2 delete by vlan test ..." 1994 tr 36 1995 $done 1996 1997 if !$?BCM5342X_A0 \ 1998 'echo "Running IPV4 overflow insert test ..."; \ 1999 tr 87 IPMCEnable=False; \ 2000 tr 87 IPMCEnable=True; \ 2001 echo "Running IPV4 hash test ..."; \ 2002 tr 88 IPMCEnable=False; \ 2003 tr 88 IPMCEnable=True; \ 2004 echo "Running IPV6 overflow insert test ..."; \ 2005 tr 85 IPMCEnable=False; \ 2006 tr 85 IPMCEnable=True; \ 2007 echo "Running IPV6 hash test ..."; \ 2008 tr 86 IPMCEnable=False; \ 2009 tr 86 IPMCEnable=True;' 2010 2011 echo "Running VLAN translate overflow insert test ..." 2012 tr 100 2013 2014 echo "Running VLAN translate hash tests ..." 2015 tr 101 hash=0 2016 tr 101 hash=1 2017 tr 101 hash=2 2018 tr 101 hash=3 2019 tr 101 hash=4 2020 tr 101 hash=5 2021 $done 2022 2023 echo "Running Egress VLAN translate overflow insert test ..." 2024 tr 102 2025 $done 2026 2027 echo "Running Egress VLAN translate hash tests ..." 2028 tr 103 hash=0 2029 tr 103 hash=1 2030 tr 103 hash=2 2031 tr 103 hash=3 2032 tr 103 hash=4 2033 tr 103 hash=5 2034 $done 2035 #no mpls in greyhound 2036 #echo "Running MPLS overflow insert test ..." 2037 #tr 104 2038 #$done 2039 2040 #echo "Running MPLS hash tests ..." 2041 #tr 105 hash=0 2042 #tr 105 hash=1 2043 #tr 105 hash=2 2044 #tr 105 hash=3 2045 #tr 105 hash=4 2046 #tr 105 hash=5 2047 #$done 2048 2049 echo "Running Software Error Recovery ..." 2050 tr 144 testType=spread 2051 $done 2052 2053 # Disable the link thread while testing the tr 60 2054 # Reload rc will restart the link thread, so set rct=false before testing 2055 set rct=false 2056 rcload rc.soc 2057 linkscan off 2058 2059 echo "Running MDIO Linkscan test" 2060 tr 60 readcount=10000 2061 $done 2062 # Re-initialize to set rct=true after tr 60 testing 2063 set rct=true 2064 2065 echo "Testing CPU DMA loopback ..." 2066 tr 17 c=5 2067 $done 2068 2069 echo "Testing CPU DMA, Scatter/Gather Reload ..." 2070 tr 22 2071 $done 2072 2073 echo "Testing CPU DMA, Scatter/Gather Simple ..." 2074 tr 23 2075 $done 2076 2077 echo "Testing CPU DMA, Scatter/Gather Random ..." 2078 tr 24 2079 $done 2080 2081 tr 48 smi=103 dmi=42 vlan=5 pi=0x11335577 sendm=single 2082 $done 2083 2084 echo "Running PHY loopback V2 on all ports ..." 2085 tr 49 smi=52 dmi=83 vlan=23 pi=0x01204007 2086 $done 2087 2088 #Internal snake Loopback 2089 echo "Running internal snake on all ports, MAC loopback ..." 2090 tr 39 loopbackmode=mac snakepath=two 2091 $done 2092 2093 echo "Running internal snake on all ports, PHY loopback ..." 2094 tr 39 loopbackmode=phy snakepath=two 2095 $done 2096 2097 echo "Running MAC loopback TR 18 on all ports ..." 2098 tr 18 pbm=ge speed=10 2099 tr 18 pbm=ge speed=100 2100 tr 18 pbm=ge speed=1000 2101 if !$?BCM56062_A0 \ 2102 'tr 18 pbm=xe speed=10G;' 2103 tr 18 pbm=xe speed=MAX 2104 if !$?BCM56062_A0 \ 2105 'tr 18 pbm=hg speed=10G;' 2106 tr 18 pbm=hg speed=MAX 2107 $done 2108 2109 echo "Running PHY loopback TR 19 on all ports ..." 2110 tr 19 pbm=ge speed=10 2111 tr 19 pbm=ge speed=100 2112 tr 19 pbm=ge speed=1000 2113 if !$?BCM56062_A0 \ 2114 'tr 19 pbm=xe speed=10G;' 2115 tr 19 pbm=xe speed=MAX 2116 if !$?BCM56062_A0 \ 2117 'tr 19 pbm=hg speed=10G;' 2118 tr 19 pbm=hg speed=MAX 2119 $done 2120 2121 #Traffic Test 2122 echo "Running Traffic Test in MAC mode ..." 2123 tr 72 RM=MAC PBM=ge 2124 tr 72 RM=MAC PBM=xe 2125 $done 2126 2127 echo "Running Traffic Test in PHY mode ..." 2128 tr 72 RM=PHY PBM=ge 2129 tr 72 RM=PHY PBM=xe 2130 $done 2131 2132 #SNMP 2133 echo "SNMP MIB Object Test" 2134 tr 73 2135 $done 2136 2137 #Reload Test 2138 echo "TX Reload Test" 2139 tr 90 2140 2141 echo "RX Reload Test" 2142 tr 91 TxPktCount=10 2143 2144 # Show status 2145 date 2146 tl 2147 local returnCode $? 2148 2149 echo Tests Complete. Reinitializing ... 2150 config refresh 2151 rcload rc.soc 2152 counter off 2153 l2mode off 2154 2155 # We want to show the return code from the tl command which 2156 # lists the results. The automated test infrastructure keys off of this 2157 # value 2158 echo "testsuite: finished: sanity: $returnCode"