BCM953025K.bcm (5209B)
1 # 2 # This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 # 4 # Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 6 # There are various configurationis can be selectived of this board 7 #################################################################################### 8 # case 1 : port 0~4 are connected with internal GPHYs, port 5 is connected with GMAC0 9 pbmp_valid.0=0x0000011f 10 # internal GPHY 11 phy_sys_interface_ge4.0=1 12 phy_port_primary_and_offset_ge0=0x0000 13 phy_port_primary_and_offset_ge1=0x0001 14 phy_port_primary_and_offset_ge2=0x0002 15 phy_port_primary_and_offset_ge3=0x0003 16 phy_port_primary_and_offset_ge4=0x0004 17 18 ## ==== MacSec Section ==== ## 19 macsec_enable = 1 20 #MACSEC device address. MACSEC devices address, used to adress MACSEC core. 21 #This is MDIO address that is being assigned to MACSEC core. The MDIO address 22 #gets programmed to MACSEC PHY during initialization if MACSEC is enabled. 23 macsec_dev_addr_ge4=0x21B 24 #A MACSEC phy could be an integrated PHYs with multiple ports. This property 25 #is needed to identify the index of each PHY port. 26 macsec_port_index_ge4=0 27 28 ######################################################################################## 29 # case 2 : port 0~3 are connected with inetrnal GPHYs, port 4~5 are connected in RGMII mode 30 pbmp_valid.0=0x0000013f 31 # RGMII mode 32 phy_sys_interface_ge4.0=7 33 phy_sys_interface_ge5.0=7 34 # external PHY address 35 port_phy_addr_ge4.0=0x101 36 port_phy_addr_ge5.0=0x110 37 phy_port_primary_and_offset_ge0=0x0000 38 phy_port_primary_and_offset_ge1=0x0001 39 phy_port_primary_and_offset_ge2=0x0002 40 phy_port_primary_and_offset_ge3=0x0003 41 42 ## ==== MacSec Section ==== ## 43 macsec_enable = 1 44 45 #MACSEC device address. MACSEC devices address, used to adress MACSEC core. 46 #This is MDIO address that is being assigned to MACSEC core. The MDIO address 47 #gets programmed to MACSEC PHY during initialization if MACSEC is enabled. 48 macsec_dev_addr_ge4=0x21B 49 macsec_dev_addr_ge5=0x21A 50 51 #A MACSEC phy could be an integrated PHYs with multiple ports. This property 52 #is needed to identify the index of each PHY port. 53 macsec_port_index_ge4=0 54 macsec_port_index_ge5=0 55 56 ###################################################################################### 57 # case 3 : port 0~3 are connect with inetrnal GPHYs, port 4~5 are connected in SGMII mode 58 pbmp_valid.0=0x0000013f 59 # SGMII mode 60 phy_sys_interface_ge4.0=4 61 phy_sys_interface_ge5.0=4 62 phy_fiber_pref=1 63 phy_port_primary_and_offset_ge0=0x0000 64 phy_port_primary_and_offset_ge1=0x0001 65 phy_port_primary_and_offset_ge2=0x0002 66 phy_port_primary_and_offset_ge3=0x0003 67 68 ## ==== MacSec Section ==== ## 69 macsec_enable = 1 70 71 #MACSEC device address. MACSEC devices address, used to adress MACSEC core. 72 #This is MDIO address that is being assigned to MACSEC core. The MDIO address 73 #gets programmed to MACSEC PHY during initialization if MACSEC is enabled. 74 macsec_dev_addr_ge4=0x21B 75 macsec_dev_addr_ge5=0x21A 76 77 #A MACSEC phy could be an integrated PHYs with multiple ports. This property 78 #is needed to identify the index of each PHY port. 79 macsec_port_index_ge4=0 80 macsec_port_index_ge5=0 81 82 ########################################################################################################## 83 # case 4 : port 0~2 are connect with internal GPHYs, port4 is connected with GPHY4 and port 5 is connected with GPHY3 84 pbmp_valid.0=0x00000137 85 # internal GPHY 86 phy_sys_interface_ge3.0=1 87 phy_sys_interface_ge4.0=1 88 phy_port_primary_and_offset_ge0=0x0000 89 phy_port_primary_and_offset_ge1=0x0001 90 phy_port_primary_and_offset_ge2=0x0002 91 phy_port_primary_and_offset_ge3=0x0004 92 phy_port_primary_and_offset_ge4=0x0003 93 94 ## ==== MacSec Section ==== ## 95 macsec_enable = 1 96 97 #MACSEC device address. MACSEC devices address, used to adress MACSEC core. 98 #This is MDIO address that is being assigned to MACSEC core. The MDIO address 99 #gets programmed to MACSEC PHY during initialization if MACSEC is enabled. 100 macsec_dev_addr_ge3=0x21B 101 macsec_dev_addr_ge4=0x21A 102 103 #A MACSEC phy could be an integrated PHYs with multiple ports. This property 104 #is needed to identify the index of each PHY port. 105 macsec_port_index_ge3=0 106 macsec_port_index_ge4=0 107 108 ######################################################################################################## 109 # case 5 : port 0~4 are connected with inetrnal GPHTs, port 5 is connected with external PHY via GMII interface 110 pbmp_valid.0=0x0000013f 111 # internal GPHY 112 phy_sys_interface_ge4.0=1 113 # GMII internal 114 phy_sys_interface_ge5.0=3 115 port_phy_addr_ge5.0=0x110 116 phy_port_primary_and_offset_ge0=0x0000 117 phy_port_primary_and_offset_ge1=0x0001 118 phy_port_primary_and_offset_ge2=0x0002 119 phy_port_primary_and_offset_ge3=0x0003 120 phy_port_primary_and_offset_ge4=0x0004 121 122 ## ==== MacSec Section ==== ## 123 macsec_enable = 1 124 125 #MACSEC device address. MACSEC devices address, used to adress MACSEC core. 126 #This is MDIO address that is being assigned to MACSEC core. The MDIO address 127 #gets programmed to MACSEC PHY during initialization if MACSEC is enabled. 128 macsec_dev_addr_ge4=0x21B 129 macsec_dev_addr_ge5=0x21A 130 131 #A MACSEC phy could be an integrated PHYs with multiple ports. This property 132 #is needed to identify the index of each PHY port. 133 macsec_port_index_ge4=0 134 macsec_port_index_ge5=0 135